coreboot-gerrit January 2016

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: ec/google/chromeec/acpi :Enable DPTF charger/TSR1/TSR2 participant
by Hannah Williams 28 Jan '16

28 Jan '16

Hannah Williams (hannah.williams(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12748 -gerrit commit fccdb2e7aa88e22049500b9da5515b18c255f61c Author: Freddy Paul <freddy.paul(a)intel.com> Date: Fri Oct 2 19:06:57 2015 -0700 ec/google/chromeec/acpi :Enable DPTF charger/TSR1/TSR2 participant . TEST=Plug/Unplug AC Adapter multiple times and make sure device is charging properly. Original-Reviewed-on: https://chromium-review.googlesource.com/303990 Original-Reviewed-by: Jenny Tc <jenny.tc(a)intel.com> Original-Reviewed-by: T.H. Lin <T.H_Lin(a)quantatw.com> Original-Tested-by: T.H. Lin <T.H_Lin(a)quantatw.com> Original-Tested-by: Jagadish Krishnamoorthy <jagadish.krishnamoorthy(a)intel.com> Original-Reviewed-by: Divya Jyothi <divya.jyothi(a)intel.com> Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Signed-off-by: Freddy Paul <freddy.paul(a)intel.com> Change-Id: I188e80e6688d0bac5bed6dd64cd2d0feefa30d3f Signed-off-by: Hannah Williams <hannah.williams(a)intel.com> Signed-off-by: Freddy Paul <freddy.paul(a)intel.com> Signed-off-by: Hannah Williams <hannah.williams(a)intel.com> --- src/ec/google/chromeec/acpi/ec.asl | 6 ++++++ src/mainboard/google/cyan/acpi/dptf.asl | 29 +++++++++++++++++++++-------- 2 files changed, 27 insertions(+), 8 deletions(-) diff --git a/src/ec/google/chromeec/acpi/ec.asl b/src/ec/google/chromeec/acpi/ec.asl index 68d5106..4eb4e17 100644 --- a/src/ec/google/chromeec/acpi/ec.asl +++ b/src/ec/google/chromeec/acpi/ec.asl @@ -22,7 +22,9 @@ // Mainboard specific throttle handler External (\_TZ.THRT, MethodObj) External (\_SB.DPTF.TEVT, MethodObj) +#ifdef DPTF_ENABLE_CHARGER External (\_SB.DPTF.TCHG, DeviceObj) +#endif Device (EC0) { @@ -170,10 +172,12 @@ Device (EC0) Store ("EC: AC CONNECTED", Debug) Store (ACEX, \PWRS) Notify (AC, 0x80) +#ifdef DPTF_ENABLE_CHARGER If (CondRefOf (\_SB.DPTF.TCHG)) { \_SB.DPTF.TCHG.SPPC (\_SB.DPTF.TCHG.PPPC ()) Notify (\_SB.DPTF.TCHG, 0x80) } +#endif \PNOT () } @@ -183,9 +187,11 @@ Device (EC0) Store ("EC: AC DISCONNECTED", Debug) Store (ACEX, \PWRS) Notify (AC, 0x80) +#ifdef DPTF_ENABLE_CHARGER If (CondRefOf (\_SB.DPTF.TCHG)) { Notify (\_SB.DPTF.TCHG, 0x80) } +#endif \PNOT () } diff --git a/src/mainboard/google/cyan/acpi/dptf.asl b/src/mainboard/google/cyan/acpi/dptf.asl index 95b6951..ffa8886 100755 --- a/src/mainboard/google/cyan/acpi/dptf.asl +++ b/src/mainboard/google/cyan/acpi/dptf.asl @@ -16,18 +16,20 @@ #define DPTF_TSR0_SENSOR_ID 0 #define DPTF_TSR0_SENSOR_NAME "TMP432_Internal" -#define DPTF_TSR0_PASSIVE 49 -#define DPTF_TSR0_CRITICAL 75 +#define DPTF_TSR0_PASSIVE 48 +#define DPTF_TSR0_CRITICAL 70 + #define DPTF_TSR1_SENSOR_ID 1 #define DPTF_TSR1_SENSOR_NAME "TMP432_Power_top" -#define DPTF_TSR1_PASSIVE 65 -#define DPTF_TSR1_CRITICAL 85 +#define DPTF_TSR1_PASSIVE 60 +#define DPTF_TSR1_CRITICAL 70 #define DPTF_TSR2_SENSOR_ID 2 #define DPTF_TSR2_SENSOR_NAME "TMP432_CPU_bottom" -#define DPTF_TSR2_PASSIVE 49 -#define DPTF_TSR2_CRITICAL 75 +#define DPTF_TSR2_PASSIVE 55 +#define DPTF_TSR2_CRITICAL 70 + #define DPTF_ENABLE_CHARGER @@ -48,7 +50,18 @@ Name (DTRT, Package () { Package () { \_SB.PCI0.B0DB, \_SB.PCI0.B0DB, 100, 50, 0, 0, 0, 0 }, /* CPU Effect on Temp Sensor 0 */ - Package () { \_SB.PCI0.B0DB, \_SB.DPTF.TSR0, 100, 100, 0, 0, 0, 0 }, + Package () { \_SB.PCI0.B0DB, \_SB.DPTF.TSR0, 100, 600, 0, 0, 0, 0 }, + +#ifdef DPTF_ENABLE_CHARGER + /* Charger Effect on Temp Sensor 1 */ + Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR1, 200, 600, 0, 0, 0, 0 }, +#endif + + /* CPU Effect on Temp Sensor 1 */ + Package () { \_SB.PCI0.B0DB, \_SB.DPTF.TSR1, 100, 600, 0, 0, 0, 0 }, + + /* CPU Effect on Temp Sensor 2 */ + Package () { \_SB.PCI0.B0DB, \_SB.DPTF.TSR2, 100, 600, 0, 0, 0, 0 }, }) Name (MPPC, Package () @@ -56,7 +69,7 @@ Name (MPPC, Package () 0x2, /* Revision */ Package () { /* Power Limit 1 */ 0, /* PowerLimitIndex, 0 for Power Limit 1 */ - 2000, /* PowerLimitMinimum */ + 1600, /* PowerLimitMinimum */ 6200, /* PowerLimitMaximum */ 1000, /* TimeWindowMinimum */ 1000, /* TimeWindowMaximum */

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New patch to review for coreboot: ec/google/chromeec/acpi: Set Charger current limit
by Hannah Williams 28 Jan '16

28 Jan '16

Hannah Williams (hannah.williams(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13494 -gerrit commit 5a445978dc0a501de9b362ba2c8b85dd19b1af8e Author: Hannah Williams <hannah.williams(a)intel.com> Date: Wed Jan 27 18:26:29 2016 -0800 ec/google/chromeec/acpi: Set Charger current limit Call the method that sets the charger current limit Change-Id: I9608404412aea6448bc2847ec3bf369fd8aedb2a Signed-off-by: Hannah Williams <hannah.williams(a)intel.com> --- src/ec/google/chromeec/acpi/ec.asl | 1 + 1 file changed, 1 insertion(+) diff --git a/src/ec/google/chromeec/acpi/ec.asl b/src/ec/google/chromeec/acpi/ec.asl index bcb26bf..68d5106 100644 --- a/src/ec/google/chromeec/acpi/ec.asl +++ b/src/ec/google/chromeec/acpi/ec.asl @@ -171,6 +171,7 @@ Device (EC0) Store (ACEX, \PWRS) Notify (AC, 0x80) If (CondRefOf (\_SB.DPTF.TCHG)) { + \_SB.DPTF.TCHG.SPPC (\_SB.DPTF.TCHG.PPPC ()) Notify (\_SB.DPTF.TCHG, 0x80) } \PNOT ()

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Patch set updated for coreboot: soc/braswell: Add interface to program USB2_COMPBG register
by Hannah Williams 28 Jan '16

28 Jan '16

Hannah Williams (hannah.williams(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12739 -gerrit commit d049442de52ba75e266788b2ffebfcb442dafec2 Author: shkim <sh_.kim(a)samsung.com> Date: Tue Sep 22 17:53:58 2015 +0900 soc/braswell: Add interface to program USB2_COMPBG register Add interface to program USB2_COMPBG register to set HS_DISC_BG and HS_SQ reference voltage for each project. TEST=Get build success and do EFT test Original-Reviewed-on: https://chromium-review.googlesource.com/300846 Original-Reviewed-by: Shawn N <shawnn(a)chromium.org> Original-Tested-by: shkim <sh_.kim(a)samsung.com> Change-Id: If2201829e1a16b4f9916547f08c24e9291358325 Signed-off-by: Kenji Chen <kenji.chen(a)intel.com> Signed-off-by: shkim <sh_.kim(a)samsung.com> Signed-off-by: Hannah Williams <hannah.williams(a)intel.com> --- src/soc/intel/braswell/chip.h | 20 ++++++++++ src/soc/intel/braswell/include/soc/iosf.h | 5 +++ src/soc/intel/braswell/iosf.c | 15 +++++++- src/soc/intel/braswell/xhci.c | 62 +++++++++++++++++++++++++++++++ 4 files changed, 101 insertions(+), 1 deletion(-) diff --git a/src/soc/intel/braswell/chip.h b/src/soc/intel/braswell/chip.h index 6eb1451..fbac84d 100644 --- a/src/soc/intel/braswell/chip.h +++ b/src/soc/intel/braswell/chip.h @@ -38,6 +38,18 @@ enum lpe_clk_src { LPE_CLK_SRC_PLL, }; +enum usb_comp_bg_value { + USB_COMP_BG_575_MV = 7, + USB_COMP_BG_650_MV = 6, + USB_COMP_BG_550_MV = 5, + USB_COMP_BG_537_MV = 4, + USB_COMP_BG_625_MV = 3, + USB_COMP_BG_700_MV = 2, + USB_COMP_BG_600_MV = 1, + USB_COMP_BG_675_MV = 0, +}; + + struct soc_intel_braswell_config { uint8_t enable_xdp_tap; uint8_t clkreq_enable; @@ -61,6 +73,14 @@ struct soc_intel_braswell_config { /* Allow PCIe devices to wake system from suspend. */ int pcie_wake_enable; + /* Program USB2_COMPBG register. + * [10:7] - select vref to AFE port + * x111 - 575mV, x110 - 650mV, x101 - 550mV, x100 - 537.5mV, + * x011 - 625mV, x010 - 700mV, x001 - 600mV, x000 - 675mV + */ + enum usb_comp_bg_value usb_comp_bg; + + /* * The following fields come from fsp_vpd.h .aka. VpdHeader.h. * These are configuration values that are passed to FSP during diff --git a/src/soc/intel/braswell/include/soc/iosf.h b/src/soc/intel/braswell/include/soc/iosf.h index add602f..e6758a6 100644 --- a/src/soc/intel/braswell/include/soc/iosf.h +++ b/src/soc/intel/braswell/include/soc/iosf.h @@ -69,6 +69,8 @@ uint32_t iosf_port58_read(int reg); void iosf_port58_write(int reg, uint32_t val); uint32_t iosf_scc_read(int reg); void iosf_scc_write(int reg, uint32_t val); +uint32_t iosf_usbphy_read(int reg); +void iosf_usbphy_write(int reg, uint32_t val); #if ENV_RAMSTAGE uint64_t reg_script_read_iosf(struct reg_script_context *ctx); @@ -91,6 +93,7 @@ void reg_script_write_iosf(struct reg_script_context *ctx); #define IOSF_PORT_0x5a 0x5a #define IOSF_PORT_USHPHY 0x61 /* USB XHCI PHY */ #define IOSF_PORT_SCC 0x63 /* Storage Control Cluster */ +#define IOSF_PORT_USBPHY 0x43 /* USB PHY */ #define IOSF_PORT_LPSS 0xa0 /* LPSS - Low Power Subsystem */ #define IOSF_PORT_0xa2 0xa2 #define IOSF_PORT_SSUS 0xa8 /* SUS */ @@ -109,6 +112,8 @@ void reg_script_write_iosf(struct reg_script_context *ctx); #define IOSF_OP_WRITE_0x58 (IOSF_OP_READ_0x58 | 1) #define IOSF_OP_READ_SCC 0x06 #define IOSF_OP_WRITE_SCC (IOSF_OP_READ_SCC | 1) +#define IOSF_OP_READ_USBPHY 0x06 +#define IOSF_OP_WRITE_USBPHY (IOSF_OP_READ_USBPHY | 1) /* * BUNIT Registers. diff --git a/src/soc/intel/braswell/iosf.c b/src/soc/intel/braswell/iosf.c index 1e7b924..98d1610 100644 --- a/src/soc/intel/braswell/iosf.c +++ b/src/soc/intel/braswell/iosf.c @@ -122,6 +122,15 @@ void iosf_scc_write(int reg, uint32_t val) return iosf_write_port(IOSF_WRITE(SCC), reg, val); } +uint32_t iosf_usbphy_read(int reg) +{ + return iosf_read_port(IOSF_READ(USBPHY), reg); +} + +void iosf_usbphy_write(int reg, uint32_t val) +{ + return iosf_write_port(IOSF_WRITE(USBPHY), reg, val); +} #if ENV_RAMSTAGE uint64_t reg_script_read_iosf(struct reg_script_context *ctx) @@ -140,6 +149,8 @@ uint64_t reg_script_read_iosf(struct reg_script_context *ctx) return iosf_port58_read(step->reg); case IOSF_PORT_SCC: return iosf_scc_read(step->reg); + case IOSF_PORT_USBPHY: + return iosf_usbphy_read(step->reg); default: printk(BIOS_DEBUG, "No read support for IOSF port 0x%x.\n", step->id); @@ -169,7 +180,9 @@ void reg_script_write_iosf(struct reg_script_context *ctx) case IOSF_PORT_SCC: iosf_scc_write(step->reg, step->value); break; - + case IOSF_PORT_USBPHY: + iosf_usbphy_write(step->reg, step->value); + break; default: printk(BIOS_DEBUG, "No write support for IOSF port 0x%x.\n", step->id); diff --git a/src/soc/intel/braswell/xhci.c b/src/soc/intel/braswell/xhci.c new file mode 100644 index 0000000..e3e3462 --- /dev/null +++ b/src/soc/intel/braswell/xhci.c @@ -0,0 +1,62 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2013 Google Inc. + * Copyright (C) 2015 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include <arch/acpi.h> +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <stdint.h> +#include <reg_script.h> + +#include <soc/iomap.h> +#include <soc/iosf.h> +#include <soc/pci_devs.h> +#include <soc/pm.h> +#include <soc/ramstage.h> +#include <soc/xhci.h> + +#include "chip.h" + +static void xhci_init(device_t dev) +{ + struct soc_intel_braswell_config *config = dev->chip_info; + + if (config && config->usb_comp_bg) { + struct reg_script ops[] = { + REG_IOSF_WRITE(IOSF_PORT_USBPHY, USBPHY_COMPBG, + config->usb_comp_bg), + REG_SCRIPT_END + }; + printk(BIOS_INFO, "Override USB2_COMPBG to: 0x%X\n", config->usb_comp_bg); + reg_script_run(ops); + } +} + +static struct device_operations xhci_device_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = xhci_init, + .ops_pci = &soc_pci_ops, +}; + +static const struct pci_driver soc_xhci __pci_driver = { + .ops = &xhci_device_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = XHCI_DEVID +};

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Patch set updated for coreboot: soc/braswell: Fix issues found during static code analysis
by Hannah Williams 28 Jan '16

28 Jan '16

Hannah Williams (hannah.williams(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12738 -gerrit commit 86881d04214c47c91437bed3f9e973395bd5f8fd Author: Ravi Sarawadi <ravishankar.sarawadi(a)intel.com> Date: Wed Sep 9 14:12:16 2015 -0700 soc/braswell: Fix issues found during static code analysis TEST=Build, boot to OS Original-Reviewed-on: https://chromium-review.googlesource.com/299483 Original-Reviewed-by: Aaron Durbin <adurbin(a)google.com> Change-Id: I738003b8dfff6a5255085d39e378e18d6ad36bcf Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi(a)intel.com> --- src/mainboard/google/cyan/spd/spd.c | 2 +- src/soc/intel/braswell/chip.c | 10 +++++++++- src/soc/intel/braswell/pmutil.c | 13 ++++--------- src/soc/intel/braswell/romstage/romstage.c | 7 +++++++ 4 files changed, 21 insertions(+), 11 deletions(-) diff --git a/src/mainboard/google/cyan/spd/spd.c b/src/mainboard/google/cyan/spd/spd.c index 31f6911..5890204 100644 --- a/src/mainboard/google/cyan/spd/spd.c +++ b/src/mainboard/google/cyan/spd/spd.c @@ -135,7 +135,7 @@ void mainboard_fill_spd_data(struct pei_data *ps) static void set_dimm_info(uint32_t chips, uint8_t *spd, struct dimm_info *dimm) { uint16_t clock_frequency; - uint32_t log2_chips; + uint32_t log2_chips = 0; /* Parse the SPD data to determine the DIMM information */ dimm->ddr_type = MEMORY_TYPE_DDR3; diff --git a/src/soc/intel/braswell/chip.c b/src/soc/intel/braswell/chip.c index 6cf3e8a..a0e6d21 100644 --- a/src/soc/intel/braswell/chip.c +++ b/src/soc/intel/braswell/chip.c @@ -84,7 +84,15 @@ static void enable_dev(device_t dev) void soc_silicon_init_params(SILICON_INIT_UPD *params) { device_t dev = dev_find_slot(0, PCI_DEVFN(LPC_DEV, LPC_FUNC)); - struct soc_intel_braswell_config *config = dev->chip_info; + struct soc_intel_braswell_config *config; + + if (!dev) { + printk(BIOS_ERR, + "Error! Device (%s) not found, soc_silicon_init_params!\n",dev_path(dev)); + return; + } + + config = dev->chip_info; /* Set the parameters for SiliconInit */ printk(BIOS_DEBUG, "Updating UPD values for SiliconInit\n"); diff --git a/src/soc/intel/braswell/pmutil.c b/src/soc/intel/braswell/pmutil.c index 4611510..018915c 100644 --- a/src/soc/intel/braswell/pmutil.c +++ b/src/soc/intel/braswell/pmutil.c @@ -68,11 +68,6 @@ static void print_num_status_bits(int num_bits, uint32_t status, } } -static void print_status_bits(uint32_t status, const char * const bit_names[]) -{ - print_num_status_bits(32, status, bit_names); -} - static uint32_t print_smi_status(uint32_t smi_sts) { static const char * const smi_sts_bits[] = { @@ -99,7 +94,7 @@ static uint32_t print_smi_status(uint32_t smi_sts) return 0; printk(BIOS_DEBUG, "SMI_STS: "); - print_status_bits(smi_sts, smi_sts_bits); + print_num_status_bits(30, smi_sts, smi_sts_bits); printk(BIOS_DEBUG, "\n"); return smi_sts; @@ -175,7 +170,7 @@ static uint16_t print_pm1_status(uint16_t pm1_sts) return 0; printk(BIOS_SPEW, "PM1_STS: "); - print_status_bits(pm1_sts, pm1_sts_bits); + print_num_status_bits(16, pm1_sts, pm1_sts_bits); printk(BIOS_SPEW, "\n"); return pm1_sts; @@ -202,7 +197,7 @@ static uint32_t print_tco_status(uint32_t tco_sts) return 0; printk(BIOS_DEBUG, "TCO_STS: "); - print_status_bits(tco_sts, tco_sts_bits); + print_num_status_bits(18, tco_sts, tco_sts_bits); printk(BIOS_DEBUG, "\n"); return tco_sts; @@ -289,7 +284,7 @@ static uint32_t print_gpe_sts(uint32_t gpe_sts) return gpe_sts; printk(BIOS_DEBUG, "GPE0a_STS: "); - print_status_bits(gpe_sts, gpe_sts_bits); + print_num_status_bits(32, gpe_sts, gpe_sts_bits); printk(BIOS_DEBUG, "\n"); return gpe_sts; diff --git a/src/soc/intel/braswell/romstage/romstage.c b/src/soc/intel/braswell/romstage/romstage.c index 2581583..71402ac 100644 --- a/src/soc/intel/braswell/romstage/romstage.c +++ b/src/soc/intel/braswell/romstage/romstage.c @@ -200,6 +200,13 @@ void soc_memory_init_params(struct romstage_params *params, /* Set the parameters for MemoryInit */ dev = dev_find_slot(0, PCI_DEVFN(LPC_DEV, LPC_FUNC)); + + if (!dev) { + printk(BIOS_ERR, + "Error! Device (PCI:0:%02x.%01x) not found, soc_memory_init_params!\n", LPC_DEV, LPC_FUNC); + return; + } + config = dev->chip_info; printk(BIOS_DEBUG, "Updating UPD values for MemoryInit\n"); upd->PcdMrcInitTsegSize = IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) ?

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Patch set updated for coreboot: intel/strago: Get Boot Flash Write Protect status
by Hannah Williams 28 Jan '16

28 Jan '16

Hannah Williams (hannah.williams(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13186 -gerrit commit 2013cdcf7c145c1c22a94b59efd0624a807ae59a Author: Hannah Williams <hannah.williams(a)intel.com> Date: Fri Jan 22 23:04:05 2016 -0800 intel/strago: Get Boot Flash Write Protect status Read GPIO to get the status Change-Id: Id2d56ce4b47c4cccba2de3f113afaee6c49885c9 Signed-off-by: Hannah Williams <hannah.williams(a)intel.com> --- src/mainboard/intel/strago/chromeos.c | 16 +++++++--------- 1 file changed, 7 insertions(+), 9 deletions(-) diff --git a/src/mainboard/intel/strago/chromeos.c b/src/mainboard/intel/strago/chromeos.c index 969021c..741933f 100755 --- a/src/mainboard/intel/strago/chromeos.c +++ b/src/mainboard/intel/strago/chromeos.c @@ -23,12 +23,11 @@ #include <ec/google/chromeec/ec.h> #endif #include <rules.h> -#include <soc/gpio.h> +#include <gpio.h> #include <string.h> #include <vendorcode/google/chromeos/chromeos.h> -/* The WP status pin lives on GPIO_SSUS_6 which is pad 36 in the SUS well. */ -#define WP_STATUS_PAD 36 +#define WP_GPIO GP_E_22 #if ENV_RAMSTAGE #include <boot/coreboot_tables.h> @@ -115,15 +114,14 @@ int get_write_protect_state(void) { /* * The vboot loader queries this function in romstage. The GPIOs have - * not been set up yet as that configuration is done in ramstage. The - * hardware defaults to an input but there is a 20K pulldown. Externally - * there is a 10K pullup. Disable the internal pull in romstage so that - * there isn't any ambiguity in the reading. + * not been set up yet as that configuration is done in ramstage. + * Configuring this GPIO as input so that there isn't any ambiguity + * in the reading. */ #if ENV_ROMSTAGE - ssus_disable_internal_pull(WP_STATUS_PAD); + gpio_input_pullup(WP_GPIO); #endif /* WP is enabled when the pin is reading high. */ - return ssus_get_gpio(WP_STATUS_PAD); + return !!gpio_get(WP_GPIO); }

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Patch set updated for coreboot: soc/braswell: Configure Boot Flash Write Protect status GPIO
by Hannah Williams 28 Jan '16

28 Jan '16

Hannah Williams (hannah.williams(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13185 -gerrit commit e0639bb8a76d2ef6aee41214e6bde8579799a3c4 Author: Hannah Williams <hannah.williams(a)intel.com> Date: Wed May 13 21:48:52 2015 -0700 soc/braswell: Configure Boot Flash Write Protect status GPIO Set up the GPIO(MF_ISH_GPIO_4) to read WP status. TEST=Use crossystem to read the WP status Signed-off-by: Hannah Williams <hannah.williams(a)intel.com> Change-Id: I17cbcba013e2a11c2527731df985aa1243065eff Original-Reviewed-on: https://chromium-review.googlesource.com/302424 Original-Tested-by: John Zhao <john.zhao(a)intel.com> Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Commit-Queue: Hannah Williams <hannah.williams(a)intel.com> Signed-off-by: Hannah Williams <hannah.williams(a)intel.com> --- src/mainboard/intel/strago/gpio.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/intel/strago/gpio.c b/src/mainboard/intel/strago/gpio.c index 47588fc..2157c8d 100755 --- a/src/mainboard/intel/strago/gpio.c +++ b/src/mainboard/intel/strago/gpio.c @@ -242,7 +242,7 @@ static const struct soc_gpio_map gpe_gpio_map[] = { GPIO_NC, /* 19 MF_GPIO_5 */ GPIO_NC, /* 20 MF_GPIO_9 */ GPIO_NC, /* 21 MF_GPIO_0 */ - GPIO_NC, /* 22 MF_GPIO_4 */ + GPIO_INPUT_PU_20K, /* 22 MF_GPIO_4 */ GPIO_NC, /* 23 MF_GPIO_8 */ GPIO_NC, /* 24 MF_GPIO_2 */ GPIO_NC, /* 25 MF_GPIO_6 */

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Patch set updated for coreboot: soc/braswell: Fix for auto wake from S5
by Hannah Williams 28 Jan '16

28 Jan '16

Hannah Williams (hannah.williams(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13425 -gerrit commit 6d5dc911a3a5750341122a2c452794d23a42f4de Author: Hannah Williams <hannah.williams(a)intel.com> Date: Mon Jul 27 19:46:34 2015 -0700 soc/braswell: Fix for auto wake from S5 Disabling S5 wake from touch panel and trackpad TEST=Build and boot the platform. TEST=Poweroff platform -> enter PG3 -> remove AC -> close Lid Plug AC in -> EC boots up and AP will shutdown the platform and open Lid -> platform boots to OS. Change-Id: I7b661a9f1327b97d904bac40e78612648f353e39 Signed-off-by: Hannah Williams <hannah.williams(a)intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/288970 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Commit-Queue: Divagar Mohandass <divagar.mohandass(a)intel.com> Original-Tested-by: Divagar Mohandass <divagar.mohandass(a)intel.com> --- src/mainboard/google/cyan/smihandler.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/src/mainboard/google/cyan/smihandler.c b/src/mainboard/google/cyan/smihandler.c index 04cc899..9b363ca 100644 --- a/src/mainboard/google/cyan/smihandler.c +++ b/src/mainboard/google/cyan/smihandler.c @@ -28,6 +28,8 @@ /* The wake gpio is SUS_GPIO[0]. */ #define WAKE_GPIO_EN SUS_GPIO_EN0 +#define GPIO_SUS7_WAKE_MASK (1 << 12) +#define GPIO_SUS1_WAKE_MASK (1 << 13) int mainboard_io_trap_handler(int smif) { @@ -96,6 +98,9 @@ void mainboard_smi_gpi(uint32_t alt_gpio_smi) void mainboard_smi_sleep(uint8_t slp_typ) { + void *addr; + uint32_t mask; + /* Disable USB charging if required */ switch (slp_typ) { case 3: @@ -125,6 +130,16 @@ void mainboard_smi_sleep(uint8_t slp_typ) /* Enable wake events */ google_chromeec_set_wake_mask(MAINBOARD_EC_S5_WAKE_EVENTS); #endif + + /* Disabling wake from SUS_GPIO1 (TOUCH INT) and + * SUS_GPIO7 (TRACKPAD INT) in North bank as they are not + * valid S5 wake sources + */ + addr = (void *)(IO_BASE_ADDRESS + COMMUNITY_OFFSET_GPNORTH + + GPIO_WAKE_MASK_REG0); + mask = ~(GPIO_SUS1_WAKE_MASK | GPIO_SUS7_WAKE_MASK); + write32(addr, read32(addr) & mask); + break; }

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Patch set updated for coreboot: soc/braswell: Set max frequency to be turbo frequency
by Hannah Williams 28 Jan '16

28 Jan '16

Hannah Williams (hannah.williams(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12736 -gerrit commit 01acb39c474511f5e53470de94c1cc2c59aeb8cb Author: Hannah Williams <hannah.williams(a)intel.com> Date: Sun Aug 23 17:24:43 2015 -0700 soc/braswell: Set max frequency to be turbo frequency In set_max_freq, instead of using ratio from IA_CORE_RATIOS, using ratio from MSR_IACORE_TURBO_RATIOS Also, punit_init needs to be called before enabling this frequency. Original-Reviewed-on: https://chromium-review.googlesource.com/295268 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Tested-by: Hannah Williams <hannah.williams(a)intel.com> Change-Id: Iabdab9ec45f8eef0a105a5a05dbcdb997b6764b0 Signed-off-by: Hannah Williams <hannah.williams(a)intel.com> --- src/soc/intel/braswell/ramstage.c | 1 + src/soc/intel/braswell/tsc_freq.c | 9 +++++++-- 2 files changed, 8 insertions(+), 2 deletions(-) diff --git a/src/soc/intel/braswell/ramstage.c b/src/soc/intel/braswell/ramstage.c index 1e085d7..155c8a2 100644 --- a/src/soc/intel/braswell/ramstage.c +++ b/src/soc/intel/braswell/ramstage.c @@ -196,6 +196,7 @@ void soc_init_pre_device(struct soc_intel_braswell_config *config) /* Perform silicon specific init. */ intel_silicon_init(); + set_max_freq(); set_board_id(); /* Get GPIO initial states from mainboard */ diff --git a/src/soc/intel/braswell/tsc_freq.c b/src/soc/intel/braswell/tsc_freq.c index fff882e..f4f1a8b 100644 --- a/src/soc/intel/braswell/tsc_freq.c +++ b/src/soc/intel/braswell/tsc_freq.c @@ -72,18 +72,23 @@ void set_max_freq(void) msr.lo |= (1 << 16); wrmsr(MSR_IA32_MISC_ENABLES, msr); + /* Enable Burst Mode */ + msr = rdmsr(MSR_IA32_MISC_ENABLES); + msr.hi = 0; + wrmsr(MSR_IA32_MISC_ENABLES, msr); + /* * Set guranteed ratio [21:16] from IACORE_RATIOS to bits [15:8] of * the PERF_CTL. */ - msr = rdmsr(MSR_IACORE_RATIOS); + msr = rdmsr(MSR_IACORE_TURBO_RATIOS); perf_ctl.lo = (msr.lo & 0x3f0000) >> 8; /* * Set guranteed vid [21:16] from IACORE_VIDS to bits [7:0] of * the PERF_CTL. */ - msr = rdmsr(MSR_IACORE_VIDS); + msr = rdmsr(MSR_IACORE_TURBO_VIDS); perf_ctl.lo |= (msr.lo & 0x7f0000) >> 16; perf_ctl.hi = 0;

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Patch set updated for coreboot: intel/strago: Fix for Crossystem "wpsw_cur" status
by Hannah Williams 28 Jan '16

28 Jan '16

Hannah Williams (hannah.williams(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13424 -gerrit commit 10ca634bd8e26ff86a91b9cff206e15c6c1d8716 Author: Kumar, Gomathi <gomathi.kumar(a)intel.com> Date: Fri Aug 7 16:39:48 2015 +0530 intel/strago: Fix for Crossystem "wpsw_cur" status The GPIO mapping was incorrect for wpsw_cur. The GPIOs for East community are in two ranges - 0: INT33FF:02 GPIOS [373 - 384] PINS [0 - 11] and 12: INT33FF:02 GPIOS [385 - 396] PINS [15 - 26] The discontinuity was not accounted for, hence the error.Original offset was 0x16 whereas it should be 0x13 TEST=Run crossystem and test wpsw_cur entry. If screw is present, it should be 1 and if not present, it should be 0 Change-Id: I29e19589b3a358a42818afbc6d017d6cbc6a9c4c Original-Signed-off-by: Kumar, Gomathi <gomathi.kumar(a)intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/291572 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Commit-Queue: Icarus W Sparry <icarus.w.sparry(a)intel.com> --- src/mainboard/intel/strago/acpi/chromeos.asl | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/mainboard/intel/strago/acpi/chromeos.asl b/src/mainboard/intel/strago/acpi/chromeos.asl index 84c1313..c470ca3 100644 --- a/src/mainboard/intel/strago/acpi/chromeos.asl +++ b/src/mainboard/intel/strago/acpi/chromeos.asl @@ -23,11 +23,11 @@ * * Note: We need to encode gpios within the 4 separate banks * with the MMIO offset of each banks space. e.g. MF_ISH_GPIO_4 would be encoded - * as 0x10016 where the SUS offset (COMMUNITY_OFFSET_GPEAST) is 0x10000. + * as 0x10013 where the SUS offset (COMMUNITY_OFFSET_GPEAST) is 0x10000. */ Name(OIPG, Package() { /* No physical recovery button */ Package () { 0x0001, 0, 0xFFFFFFFF, "Braswell" }, - Package () { 0x0003, 1, 0x10016, "Braswell" }, + Package () { 0x0003, 1, 0x10013, "Braswell" }, })

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Patch set updated for coreboot: soc/braswell: Disable SD card detect simulation in FSP
by Hannah Williams 28 Jan '16

28 Jan '16

Hannah Williams (hannah.williams(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12742 -gerrit commit cb7fe7abaa60e5f2b1e48ff9967ec885ae00ed18 Author: Divya Sasidharan <divya.s.sasidharan(a)intel.com> Date: Wed Oct 28 15:02:35 2015 -0700 soc/braswell: Disable SD card detect simulation in FSP CQ-DEPEND=CL:13038 Debounce for SD card detect takes a long time and thus affects boot time. Disabling SD card detect simulation in FSP through UPD Original-Reviewed-on: https://chromium-review.googlesource.com/311850 Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Tested-by: Hannah Williams <hannah.williams(a)intel.com> Change-Id: Iab0794ec058460df94f6bbed5c9b0911e57e3a71 Signed-off-by: Divya Sasidharan <divya.s.sasidharan(a)intel.com> --- src/soc/intel/braswell/chip.c | 3 +++ src/soc/intel/braswell/chip.h | 1 + 2 files changed, 4 insertions(+) diff --git a/src/soc/intel/braswell/chip.c b/src/soc/intel/braswell/chip.c index a0e6d21..a362664 100644 --- a/src/soc/intel/braswell/chip.c +++ b/src/soc/intel/braswell/chip.c @@ -160,6 +160,7 @@ void soc_silicon_init_params(SILICON_INIT_UPD *params) params->PMIC_I2CBus = config->PMIC_I2CBus; params->ISPEnable = config->ISPEnable; params->ISPPciDevConfig = config->ISPPciDevConfig; + params->PcdSdDetectChk = config->PcdSdDetectChk; } void soc_display_silicon_init_params(const SILICON_INIT_UPD *old, @@ -320,6 +321,8 @@ void soc_display_silicon_init_params(const SILICON_INIT_UPD *old, old->ISPEnable, new->ISPEnable); fsp_display_upd_value("ISPPciDevConfig", 1, old->ISPPciDevConfig, new->ISPPciDevConfig); + fsp_display_upd_value("PcdSdDetectChk", 1, + old->PcdSdDetectChk, new->PcdSdDetectChk); } /* Called at BS_DEV_INIT_CHIPS time -- very early. Just after BS_PRE_DEVICE. */ diff --git a/src/soc/intel/braswell/chip.h b/src/soc/intel/braswell/chip.h index fbac84d..341ab92 100644 --- a/src/soc/intel/braswell/chip.h +++ b/src/soc/intel/braswell/chip.h @@ -159,6 +159,7 @@ struct soc_intel_braswell_config { UINT8 PMIC_I2CBus; UINT8 ISPEnable; UINT8 ISPPciDevConfig; + UINT8 PcdSdDetectChk; /*Enable\Disable SD Card Detect Simulation*/ }; extern struct chip_operations soc_intel_braswell_ops;

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coreboot-gerrit January 2016