coreboot-gerrit January 2016

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: soc/braswell: Set max frequency to be turbo frequency
by Hannah Williams 28 Jan '16

28 Jan '16

Hannah Williams (hannah.williams(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12736 -gerrit commit daa014a848308348044ec8422f36cb89b9f21b6f Author: Hannah Williams <hannah.williams(a)intel.com> Date: Sun Aug 23 17:24:43 2015 -0700 soc/braswell: Set max frequency to be turbo frequency In set_max_freq, instead of using ratio from IA_CORE_RATIOS, using ratio from MSR_IACORE_TURBO_RATIOS Also, punit_init needs to be called before enabling this frequency. Original-Reviewed-on: https://chromium-review.googlesource.com/295268 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Tested-by: Hannah Williams <hannah.williams(a)intel.com> Change-Id: Iabdab9ec45f8eef0a105a5a05dbcdb997b6764b0 Signed-off-by: Hannah Williams <hannah.williams(a)intel.com> --- src/soc/intel/braswell/ramstage.c | 1 + src/soc/intel/braswell/tsc_freq.c | 9 +++++++-- 2 files changed, 8 insertions(+), 2 deletions(-) diff --git a/src/soc/intel/braswell/ramstage.c b/src/soc/intel/braswell/ramstage.c index 1e085d7..155c8a2 100644 --- a/src/soc/intel/braswell/ramstage.c +++ b/src/soc/intel/braswell/ramstage.c @@ -196,6 +196,7 @@ void soc_init_pre_device(struct soc_intel_braswell_config *config) /* Perform silicon specific init. */ intel_silicon_init(); + set_max_freq(); set_board_id(); /* Get GPIO initial states from mainboard */ diff --git a/src/soc/intel/braswell/tsc_freq.c b/src/soc/intel/braswell/tsc_freq.c index fff882e..f4f1a8b 100644 --- a/src/soc/intel/braswell/tsc_freq.c +++ b/src/soc/intel/braswell/tsc_freq.c @@ -72,18 +72,23 @@ void set_max_freq(void) msr.lo |= (1 << 16); wrmsr(MSR_IA32_MISC_ENABLES, msr); + /* Enable Burst Mode */ + msr = rdmsr(MSR_IA32_MISC_ENABLES); + msr.hi = 0; + wrmsr(MSR_IA32_MISC_ENABLES, msr); + /* * Set guranteed ratio [21:16] from IACORE_RATIOS to bits [15:8] of * the PERF_CTL. */ - msr = rdmsr(MSR_IACORE_RATIOS); + msr = rdmsr(MSR_IACORE_TURBO_RATIOS); perf_ctl.lo = (msr.lo & 0x3f0000) >> 8; /* * Set guranteed vid [21:16] from IACORE_VIDS to bits [7:0] of * the PERF_CTL. */ - msr = rdmsr(MSR_IACORE_VIDS); + msr = rdmsr(MSR_IACORE_TURBO_VIDS); perf_ctl.lo |= (msr.lo & 0x7f0000) >> 16; perf_ctl.hi = 0;

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Patch set updated for coreboot: soc/braswell: Fix DSP clock
by Hannah Williams 28 Jan '16

28 Jan '16

Hannah Williams (hannah.williams(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12732 -gerrit commit dc4b92086596227bd7e7768b2c6a5d36e27782fd Author: fdurairx <felixx.durairaj(a)intel.com> Date: Fri Aug 21 15:36:53 2015 -0700 soc/braswell: Fix DSP clock The codec clock frequency was incorrectly set to 25MHz. The only available frequency is 19.2MHz through external clock and PLL. Original-Reviewed-on: https://chromium-review.googlesource.com/295768 Original-Tested-by: Hannah Williams <hannah.williams(a)intel.com> Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Change-Id: I9bef334a5a3aaee28fcc4937180896ff49969bc5 Signed-off-by: Felix Durairaj <felixx.durairaj(a)intel.com> --- src/mainboard/google/cyan/devicetree.cb | 3 +-- src/mainboard/intel/strago/devicetree.cb | 3 +-- src/soc/intel/braswell/chip.h | 8 ++++++-- src/soc/intel/braswell/include/soc/pm.h | 4 ++-- src/soc/intel/braswell/lpe.c | 24 +++++++++++------------- 5 files changed, 21 insertions(+), 21 deletions(-) diff --git a/src/mainboard/google/cyan/devicetree.cb b/src/mainboard/google/cyan/devicetree.cb index c36ae3d..8932cf4 100755 --- a/src/mainboard/google/cyan/devicetree.cb +++ b/src/mainboard/google/cyan/devicetree.cb @@ -72,8 +72,7 @@ chip soc/intel/braswell register "ISPPciDevConfig" = "3" # LPE audio codec settings - register "lpe_codec_clk_freq" = "25" # 25MHz clock - register "lpe_codec_clk_num" = "0" # PMC_PLT_CLK[0] + register "lpe_codec_clk_src" = "LPE_CLK_SRC_XTAL" # 19.2MHz clock # Enable devices in ACPI mode register "lpss_acpi_mode" = "1" diff --git a/src/mainboard/intel/strago/devicetree.cb b/src/mainboard/intel/strago/devicetree.cb index c2aa47a..2bca939 100755 --- a/src/mainboard/intel/strago/devicetree.cb +++ b/src/mainboard/intel/strago/devicetree.cb @@ -72,8 +72,7 @@ chip soc/intel/braswell register "ISPPciDevConfig" = "3" # LPE audio codec settings - register "lpe_codec_clk_freq" = "25" # 25MHz clock - register "lpe_codec_clk_num" = "0" # PMC_PLT_CLK[0] + register "lpe_codec_clk_src" = "LPE_CLK_SRC_XTAL" # 19.2MHz clock # Enable devices in ACPI mode register "lpss_acpi_mode" = "1" diff --git a/src/soc/intel/braswell/chip.h b/src/soc/intel/braswell/chip.h index 0f3c1d0..6eb1451 100644 --- a/src/soc/intel/braswell/chip.h +++ b/src/soc/intel/braswell/chip.h @@ -33,6 +33,11 @@ #define MEM_DDR3 0 #define MEM_LPDDR3 1 +enum lpe_clk_src { + LPE_CLK_SRC_XTAL, + LPE_CLK_SRC_PLL, +}; + struct soc_intel_braswell_config { uint8_t enable_xdp_tap; uint8_t clkreq_enable; @@ -41,8 +46,7 @@ struct soc_intel_braswell_config { int disable_slp_x_stretch_sus_fail; /* LPE Audio Clock configuration. */ - int lpe_codec_clk_freq; /* 19 or 25 are valid. */ - int lpe_codec_clk_num; /* Platform clock pins. [0:5] are valid. */ + enum lpe_clk_src lpe_codec_clk_src; /* 0=xtal 1=PLL, Both are 19.2Mhz. */ /* Native SD Card controller - override controller capabilities. */ uint32_t sdcard_cap_low; diff --git a/src/soc/intel/braswell/include/soc/pm.h b/src/soc/intel/braswell/include/soc/pm.h index 9e527e1..ec10101 100644 --- a/src/soc/intel/braswell/include/soc/pm.h +++ b/src/soc/intel/braswell/include/soc/pm.h @@ -116,8 +116,8 @@ #define PLT_CLK_CTL_3 0x6c #define PLT_CLK_CTL_4 0x70 #define PLT_CLK_CTL_5 0x74 -# define CLK_FREQ_25MHZ (0x0 << 2) -# define CLK_FREQ_19P2MHZ (0x1 << 2) +# define CLK_SRC_XTAL (0x0 << 2) +# define CLK_SRC_PLL (0x1 << 2) # define CLK_CTL_D3_LPE (0x0 << 0) # define CLK_CTL_ON (0x1 << 0) # define CLK_CTL_OFF (0x2 << 0) diff --git a/src/soc/intel/braswell/lpe.c b/src/soc/intel/braswell/lpe.c index a1a7c64..4662b43 100644 --- a/src/soc/intel/braswell/lpe.c +++ b/src/soc/intel/braswell/lpe.c @@ -96,32 +96,30 @@ static void setup_codec_clock(device_t dev) const char *freq_str; config = dev->chip_info; - switch (config->lpe_codec_clk_freq) { - case 19: - freq_str = "19.2"; - reg = CLK_FREQ_19P2MHZ; + switch (config->lpe_codec_clk_src) { + case LPE_CLK_SRC_XTAL: + /* XTAL driven bit2=0 */ + freq_str = "19.2MHz External Crystal"; + reg = CLK_SRC_XTAL; break; - case 25: - freq_str = "25"; - reg = CLK_FREQ_25MHZ; + case LPE_CLK_SRC_PLL: + /* PLL driven bit2=1 */ + freq_str = "19.2MHz PLL"; + reg = CLK_SRC_PLL; break; default: - printk(BIOS_DEBUG, "LPE codec clock not required.\n"); + reg = CLK_SRC_XTAL; + printk(BIOS_DEBUG, "LPE codec clock default to using Crystal\n"); return; } /* Default to always running. */ reg |= CLK_CTL_ON; - if (config->lpe_codec_clk_num < 0 || config->lpe_codec_clk_num > 5) { - printk(BIOS_DEBUG, "Invalid LPE codec clock number.\n"); - return; - } printk(BIOS_DEBUG, "LPE Audio codec clock set to %sMHz.\n", freq_str); clk_reg = (u32 *) (PMC_BASE_ADDRESS + PLT_CLK_CTL_0); - clk_reg += config->lpe_codec_clk_num; write32(clk_reg, (read32(clk_reg) & ~0x7) | reg); }

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Patch set updated for coreboot: google/peppy/Kconfig: Move select MAINBOARD_DO_NATIVE_VGA_INIT
by Jean Lucas 28 Jan '16

28 Jan '16

Jean Lucas (jean(a)4ray.co) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13493 -gerrit commit 4c3bf273f608e7ed62c75e8fb5e7663e95ff5493 Author: Jean Lucas <jean(a)4ray.co> Date: Wed Jan 27 16:04:43 2016 -0500 google/peppy/Kconfig: Move select MAINBOARD_DO_NATIVE_VGA_INIT Move the default select of "Use native graphics initialization" for Peppy to the ChromeOS section as SeaBIOS (default payload) requires a vBIOS and takes twice as long to load with this option enabled. For the same reasons, this option shouldn't be enabled by default (def_bool y). Change-Id: I1f2163e0a1e4bf8e5041dad150bdf7de804fb4db Signed-off-by: Jean Lucas <jean(a)4ray.co> --- src/mainboard/google/peppy/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/google/peppy/Kconfig b/src/mainboard/google/peppy/Kconfig index 428d293..3e12a00 100644 --- a/src/mainboard/google/peppy/Kconfig +++ b/src/mainboard/google/peppy/Kconfig @@ -17,12 +17,12 @@ config BOARD_SPECIFIC_OPTIONS # dummy select MAINBOARD_HAS_CHROMEOS select MAINBOARD_HAS_LPC_TPM select MAINBOARD_HAS_NATIVE_VGA_INIT - select MAINBOARD_DO_NATIVE_VGA_INIT select INTEL_DP select INTEL_DDI select INTEL_INT15 config CHROMEOS + select MAINBOARD_DO_NATIVE_VGA_INIT select CHROMEOS_VBNV_CMOS select LID_SWITCH select EC_SOFTWARE_SYNC

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Patch set updated for coreboot: google/peppy/Kconfig: Move select MAINBOARD_DO_NATIVE_VGA_INIT
by Jean Lucas 28 Jan '16

28 Jan '16

Jean Lucas (jean(a)4ray.co) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13493 -gerrit commit 2fe84f08a549856612eb1b94b1be91ad1155d6cf Author: Jean Lucas <jean(a)4ray.co> Date: Wed Jan 27 16:04:43 2016 -0500 google/peppy/Kconfig: Move select MAINBOARD_DO_NATIVE_VGA_INIT Move the default select of "Use native graphics initialization" for Peppy to the ChromeOS section as SeaBIOS (default payload) requires a vBIOS and takes twice as long to load with this option enabled. For the same reasons, this option shouldn't be enabled by default (def_bool y). Change-Id: I1f2163e0a1e4bf8e5041dad150bdf7de804fb4db Signed-off-by: Jean Lucas <jean(a)4ray.co> --- src/mainboard/google/peppy/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/google/peppy/Kconfig b/src/mainboard/google/peppy/Kconfig index 428d293..3e12a00 100644 --- a/src/mainboard/google/peppy/Kconfig +++ b/src/mainboard/google/peppy/Kconfig @@ -17,12 +17,12 @@ config BOARD_SPECIFIC_OPTIONS # dummy select MAINBOARD_HAS_CHROMEOS select MAINBOARD_HAS_LPC_TPM select MAINBOARD_HAS_NATIVE_VGA_INIT - select MAINBOARD_DO_NATIVE_VGA_INIT select INTEL_DP select INTEL_DDI select INTEL_INT15 config CHROMEOS + select MAINBOARD_DO_NATIVE_VGA_INIT select CHROMEOS_VBNV_CMOS select LID_SWITCH select EC_SOFTWARE_SYNC

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Patch set updated for coreboot: intel/strago: Fix for Crossystem "wpsw_cur" status
by Hannah Williams 28 Jan '16

28 Jan '16

Hannah Williams (hannah.williams(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13424 -gerrit commit 9bfbf42a37ee3490548c543aa306e8fed795969f Author: Kumar, Gomathi <gomathi.kumar(a)intel.com> Date: Fri Aug 7 16:39:48 2015 +0530 intel/strago: Fix for Crossystem "wpsw_cur" status The GPIO mapping was incorrect for wpsw_cur. The GPIOs for East community are in two ranges - 0: INT33FF:02 GPIOS [373 - 384] PINS [0 - 11] and 12: INT33FF:02 GPIOS [385 - 396] PINS [15 - 26] The discontinuity was not accounted for, hence the error.Original offset was 0x16 whereas it should be 0x13 TEST=Run crossystem and test wpsw_cur entry. If screw is present, it should be 1 and if not present, it should be 0 Change-Id: I29e19589b3a358a42818afbc6d017d6cbc6a9c4c Original-Signed-off-by: Kumar, Gomathi <gomathi.kumar(a)intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/291572 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Commit-Queue: Icarus W Sparry <icarus.w.sparry(a)intel.com> --- src/mainboard/intel/strago/acpi/chromeos.asl | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/mainboard/intel/strago/acpi/chromeos.asl b/src/mainboard/intel/strago/acpi/chromeos.asl index 84c1313..c470ca3 100644 --- a/src/mainboard/intel/strago/acpi/chromeos.asl +++ b/src/mainboard/intel/strago/acpi/chromeos.asl @@ -23,11 +23,11 @@ * * Note: We need to encode gpios within the 4 separate banks * with the MMIO offset of each banks space. e.g. MF_ISH_GPIO_4 would be encoded - * as 0x10016 where the SUS offset (COMMUNITY_OFFSET_GPEAST) is 0x10000. + * as 0x10013 where the SUS offset (COMMUNITY_OFFSET_GPEAST) is 0x10000. */ Name(OIPG, Package() { /* No physical recovery button */ Package () { 0x0001, 0, 0xFFFFFFFF, "Braswell" }, - Package () { 0x0003, 1, 0x10016, "Braswell" }, + Package () { 0x0003, 1, 0x10013, "Braswell" }, })

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Patch set updated for coreboot: Remove the default select of "Use native graphics initialization" for Peppy as not all build targets require this option enabled.
by Jean Lucas 28 Jan '16

28 Jan '16

Jean Lucas (jean(a)4ray.co) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13493 -gerrit commit f528f879e0b9e5eecb9b42d7e4dbc6757a0ba6a9 Author: Jean Lucas <jean(a)4ray.co> Date: Wed Jan 27 16:04:43 2016 -0500 Remove the default select of "Use native graphics initialization" for Peppy as not all build targets require this option enabled. Change-Id: I1f2163e0a1e4bf8e5041dad150bdf7de804fb4db --- src/mainboard/google/peppy/Kconfig | 1 - 1 file changed, 1 deletion(-) diff --git a/src/mainboard/google/peppy/Kconfig b/src/mainboard/google/peppy/Kconfig index 428d293..9eb4910 100644 --- a/src/mainboard/google/peppy/Kconfig +++ b/src/mainboard/google/peppy/Kconfig @@ -17,7 +17,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select MAINBOARD_HAS_CHROMEOS select MAINBOARD_HAS_LPC_TPM select MAINBOARD_HAS_NATIVE_VGA_INIT - select MAINBOARD_DO_NATIVE_VGA_INIT select INTEL_DP select INTEL_DDI select INTEL_INT15

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Patch merged into coreboot/master: mb/intel/d510mo: Use SATA AHCI by default
by gerrit＠coreboot.org 28 Jan '16

28 Jan '16

the following patch was just integrated into master: commit 63eb9172758c7ed9f14713ab71a0281125ef8a28 Author: Damien Zammit <damien(a)zamaudio.com> Date: Tue Jan 26 14:03:37 2016 +1100 mb/intel/d510mo: Use SATA AHCI by default Change-Id: I6f9772c5bcf9a50dfbc3d1cfaeb79f4454d1fb27 Signed-off-by: Damien Zammit <damien(a)zamaudio.com> Reviewed-on: https://review.coreboot.org/13454 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Reviewed-by: Alexander Couzens <lynxis(a)fe80.eu> See https://review.coreboot.org/13454 for details. -gerrit

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Patch set updated for coreboot: mb/intel/d510mo: Use SATA AHCI by default
by Martin Roth 28 Jan '16

28 Jan '16

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13454 -gerrit commit 8368d0fefd1e5f83cf01d6a1b0b6004d86a3ebb7 Author: Damien Zammit <damien(a)zamaudio.com> Date: Tue Jan 26 14:03:37 2016 +1100 mb/intel/d510mo: Use SATA AHCI by default Change-Id: I6f9772c5bcf9a50dfbc3d1cfaeb79f4454d1fb27 Signed-off-by: Damien Zammit <damien(a)zamaudio.com> --- src/mainboard/intel/d510mo/devicetree.cb | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/src/mainboard/intel/d510mo/devicetree.cb b/src/mainboard/intel/d510mo/devicetree.cb index df5a0f9..c0f38de 100644 --- a/src/mainboard/intel/d510mo/devicetree.cb +++ b/src/mainboard/intel/d510mo/devicetree.cb @@ -38,10 +38,8 @@ chip northbridge/intel/pineview # Northbridge register "pirqf_routing" = "0x0b" register "pirqg_routing" = "0x0b" register "pirqh_routing" = "0x0b" - register "ide_legacy_combined" = "0x1" - register "ide_enable_primary" = "0x1" - register "ide_enable_secondary" = "0x0" - register "sata_ahci" = "0x0" + register "sata_ahci" = "0x1" + register "sata_ports_implemented" = "0x3" register "gpe0_en" = "0x20000040" device pci 1b.0 on end # Audio

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Patch merged into coreboot/master: mb/intel/d510mo: Use native gfx initialization
by gerrit＠coreboot.org 28 Jan '16

28 Jan '16

the following patch was just integrated into master: commit 761c2942ef1a26dde2b1c9a126c62f091daef789 Author: Damien Zammit <damien(a)zamaudio.com> Date: Tue Jan 26 13:55:43 2016 +1100 mb/intel/d510mo: Use native gfx initialization Change-Id: Ic4de7a762e90b379be3814afc61467e1cd099215 Signed-off-by: Damien Zammit <damien(a)zamaudio.com> Reviewed-on: https://review.coreboot.org/13034 Tested-by: build bot (Jenkins) Reviewed-by: Alexander Couzens <lynxis(a)fe80.eu> Reviewed-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> See https://review.coreboot.org/13034 for details. -gerrit

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Patch merged into coreboot/master: mb/intel/d510mo: Add CPU, SMI-trap and PIC to DSDT
by gerrit＠coreboot.org 28 Jan '16

28 Jan '16

the following patch was just integrated into master: commit 301999f4b86b2848d8027f889879db1c20cb270b Author: Damien Zammit <damien(a)zamaudio.com> Date: Tue Jan 26 13:57:17 2016 +1100 mb/intel/d510mo: Add CPU, SMI-trap and PIC to DSDT Change-Id: I80853cadb4762d9bb34926e31d65d248c5683417 Signed-off-by: Damien Zammit <damien(a)zamaudio.com> Reviewed-on: https://review.coreboot.org/13453 Tested-by: build bot (Jenkins) Reviewed-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> See https://review.coreboot.org/13453 for details. -gerrit

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coreboot-gerrit January 2016