coreboot-gerrit January 2016

coreboot-gerrit@coreboot.org

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Patch merged into coreboot/master: soc/braswell/acpi: Fix CID1 offset in comment
by gerrit＠coreboot.org 28 Jan '16

28 Jan '16

the following patch was just integrated into master: commit ba6dfe4cc57578cbce1e710c8477d6dda997541a Author: Hannah Williams <hannah.williams(a)intel.com> Date: Tue Jan 26 15:40:24 2016 -0800 soc/braswell/acpi: Fix CID1 offset in comment Signed-off-by: Hannah Williams <hannah.williams(a)intel.com> Change-Id: I9fd2ebba985362fe8068c10390bb014cf9015ac5 Reviewed-on: https://review.coreboot.org/13483 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/13483 for details. -gerrit

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Patch merged into coreboot/master: soc/braswell: Fix for auto wake from S5
by gerrit＠coreboot.org 28 Jan '16

28 Jan '16

the following patch was just integrated into master: commit 73600e31992bf115b47de37dcd597b8560b05751 Author: Hannah Williams <hannah.williams(a)intel.com> Date: Mon Jul 27 19:46:34 2015 -0700 soc/braswell: Fix for auto wake from S5 Disabling S5 wake from touch panel and trackpad TEST=Build and boot the platform. TEST=Poweroff platform -> enter PG3 -> remove AC -> close Lid Plug AC in -> EC boots up and AP will shutdown the platform and open Lid -> platform boots to OS. Change-Id: I7b661a9f1327b97d904bac40e78612648f353e39 Signed-off-by: Hannah Williams <hannah.williams(a)intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/288970 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Commit-Queue: Divagar Mohandass <divagar.mohandass(a)intel.com> Original-Tested-by: Divagar Mohandass <divagar.mohandass(a)intel.com> Reviewed-on: https://review.coreboot.org/13425 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/13425 for details. -gerrit

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Patch merged into coreboot/master: intel/strago: Fix for Crossystem "wpsw_cur" status
by gerrit＠coreboot.org 28 Jan '16

28 Jan '16

the following patch was just integrated into master: commit 2b9696239fb3ee6551ae51aa85080206cce9bfed Author: Kumar, Gomathi <gomathi.kumar(a)intel.com> Date: Fri Aug 7 16:39:48 2015 +0530 intel/strago: Fix for Crossystem "wpsw_cur" status The GPIO mapping was incorrect for wpsw_cur. The GPIOs for East community are in two ranges - 0: INT33FF:02 GPIOS [373 - 384] PINS [0 - 11] and 12: INT33FF:02 GPIOS [385 - 396] PINS [15 - 26] The discontinuity was not accounted for, hence the error.Original offset was 0x16 whereas it should be 0x13 TEST=Run crossystem and test wpsw_cur entry. If screw is present, it should be 1 and if not present, it should be 0 Change-Id: I29e19589b3a358a42818afbc6d017d6cbc6a9c4c Original-Signed-off-by: Kumar, Gomathi <gomathi.kumar(a)intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/291572 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Commit-Queue: Icarus W Sparry <icarus.w.sparry(a)intel.com> Reviewed-on: https://review.coreboot.org/13424 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/13424 for details. -gerrit

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Patch merged into coreboot/master: soc/braswell: Fix issues found during static code analysis
by gerrit＠coreboot.org 28 Jan '16

28 Jan '16

the following patch was just integrated into master: commit d077b58c61896c71218a90292bbcd5063c11698f Author: Ravi Sarawadi <ravishankar.sarawadi(a)intel.com> Date: Wed Sep 9 14:12:16 2015 -0700 soc/braswell: Fix issues found during static code analysis TEST=Build, boot to OS Original-Reviewed-on: https://chromium-review.googlesource.com/299483 Original-Reviewed-by: Aaron Durbin <adurbin(a)google.com> Change-Id: I738003b8dfff6a5255085d39e378e18d6ad36bcf Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi(a)intel.com> Reviewed-on: https://review.coreboot.org/12738 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/12738 for details. -gerrit

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Patch merged into coreboot/master: intel/strago: Get Boot Flash Write Protect status
by gerrit＠coreboot.org 28 Jan '16

28 Jan '16

the following patch was just integrated into master: commit 9657f3bb097ef5506d66a999118a4157ddadf7d5 Author: Hannah Williams <hannah.williams(a)intel.com> Date: Fri Jan 22 23:04:05 2016 -0800 intel/strago: Get Boot Flash Write Protect status Read GPIO to get the status Change-Id: Id2d56ce4b47c4cccba2de3f113afaee6c49885c9 Signed-off-by: Hannah Williams <hannah.williams(a)intel.com> Reviewed-on: https://review.coreboot.org/13186 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/13186 for details. -gerrit

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Patch merged into coreboot/master: Braswell: Separate L1 Sub State init procedure for boards.
by gerrit＠coreboot.org 28 Jan '16

28 Jan '16

the following patch was just integrated into master: commit b1e4bd0d28bb65474c0a954374124f21cac05972 Author: Kenji Chen <kenji.chen(a)intel.com> Date: Mon Nov 16 17:08:32 2015 +0800 Braswell: Separate L1 Sub State init procedure for boards. Original-Reviewed-on: https://chromium-review.googlesource.com/312743 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Signed-off-by: Kenji Chen <kenji.chen(a)intel.com> Change-Id: Ib0a891f229477cf359bff6cd02f305606468f07f Signed-off-by: Hannah Williams <hannah.williams(a)intel.com> Signed-off-by: Kenji Chen <kenji.chen(a)intel.com> Reviewed-on: https://review.coreboot.org/12750 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/12750 for details. -gerrit

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Patch merged into coreboot/master: Strago: Enable CA Mirror
by gerrit＠coreboot.org 28 Jan '16

28 Jan '16

the following patch was just integrated into master: commit c4153c1b15fa88796ce3bcccb49e3537c9e65ff3 Author: Shobhit Srivastava <shobhit.srivastava(a)intel.com> Date: Fri Oct 9 17:05:16 2015 +0530 Strago: Enable CA Mirror Configuring UPD PcdCaMirrorEn. This is a board specific parameter. CA mirror is the Command Address mirroring option that is enabled on this board CQ-DEPEND=CL:13038 Original-Reviewed-on: https://chromium-review.googlesource.com/309190 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Tested-by: Hannah Williams <hannah.williams(a)intel.com> Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Change-Id: I05174e18d650332d838e5036c713e91c4840ee75 Signed-off-by: Divya Sasidharan <divya.s.sasidharan(a)intel.com> Signed-off-by: Hannah Williams <hannah.williams(a)intel.com> Reviewed-on: https://review.coreboot.org/12749 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/12749 for details. -gerrit

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Patch merged into coreboot/master: intel/cyan: Disable SD Card Detect Simulation in FSP
by gerrit＠coreboot.org 28 Jan '16

28 Jan '16

the following patch was just integrated into master: commit 731e463495b0ebcf16515172b0bded02e318ce9d Author: Hannah Williams <hannah.williams(a)intel.com> Date: Sun Jan 17 23:22:12 2016 -0800 intel/cyan: Disable SD Card Detect Simulation in FSP CQ-DEPEND=CL:12742 Change-Id: Ifc95809e342d87f863dd60967f5b3a6ca5c0f7b3 Signed-off-by: Hannah Williams <hannah.williams(a)intel.com> Reviewed-on: https://review.coreboot.org/13036 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/13036 for details. -gerrit

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Patch merged into coreboot/master: Strago: Disable SD Card Detect Simulation in FSP
by gerrit＠coreboot.org 28 Jan '16

28 Jan '16

the following patch was just integrated into master: commit 79445c72b2a338581f72f1bbe0f5897b38855a5f Author: Hannah Williams <hannah.williams(a)intel.com> Date: Sun Jan 17 23:11:25 2016 -0800 Strago: Disable SD Card Detect Simulation in FSP CQ-DEPEND=CL:12742 Signed-off-by: Hannah Williams <hannah.williams(a)intel.com> Change-Id: I6c39ffebe407a4ef8555b2f050a96d33709dc624 Reviewed-on: https://review.coreboot.org/13035 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/13035 for details. -gerrit

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Patch merged into coreboot/master: soc/braswell: Disable SD card detect simulation in FSP
by gerrit＠coreboot.org 28 Jan '16

28 Jan '16

the following patch was just integrated into master: commit 89a6685edea6b583f4a9da5bd53f818428c1cadf Author: Divya Sasidharan <divya.s.sasidharan(a)intel.com> Date: Wed Oct 28 15:02:35 2015 -0700 soc/braswell: Disable SD card detect simulation in FSP CQ-DEPEND=CL:13038 Debounce for SD card detect takes a long time and thus affects boot time. Disabling SD card detect simulation in FSP through UPD Original-Reviewed-on: https://chromium-review.googlesource.com/311850 Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Tested-by: Hannah Williams <hannah.williams(a)intel.com> Change-Id: Iab0794ec058460df94f6bbed5c9b0911e57e3a71 Signed-off-by: Divya Sasidharan <divya.s.sasidharan(a)intel.com> Reviewed-on: https://review.coreboot.org/12742 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/12742 for details. -gerrit

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coreboot-gerrit January 2016