coreboot-gerrit January 2016

coreboot-gerrit@coreboot.org

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2471 discussions

Patch merged into coreboot/master: via/cx700: Use zeroptr over 0
by gerrit＠coreboot.org 28 Jan '16

28 Jan '16

the following patch was just integrated into master: commit 23cc9b09c7b5d1d18432b2553e177aa61697b490 Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Wed Jan 27 08:19:36 2016 +0100 via/cx700: Use zeroptr over 0 This eliminates all "ud2" instances from romstage disassembly. Change-Id: I3b0c8322a4ca4a851b0cce8f3941425d9cb30383 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Reviewed-on: https://review.coreboot.org/13488 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/13488 for details. -gerrit

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Patch merged into coreboot/master: Provide a gcc-safe zero pointer
by gerrit＠coreboot.org 28 Jan '16

28 Jan '16

the following patch was just integrated into master: commit ff8076d75ace8da247b927f7de37f3ed5081b55e Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Wed Jan 27 08:18:16 2016 +0100 Provide a gcc-safe zero pointer zeroptr is a linker object pointing at 0 that can be used to thwart GCC's (and other compilers') "dereferencing NULL is undefined" optimization strategy when it gets in the way. Change-Id: I6aa6f28283281ebae73d6349811e290bf1b99483 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Reviewed-on: https://review.coreboot.org/12294 Tested-by: Raptor Engineering Automated Test Stand <noreply(a)raptorengineeringinc.com> Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/12294 for details. -gerrit

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New patch to review for coreboot: soc/braswell: Fix Global NVS base address
by Hannah Williams 28 Jan '16

28 Jan '16

Hannah Williams (hannah.williams(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13506 -gerrit commit 6aa723a8450d10ccfe312cee76f9150b2ace5012 Author: Hannah Williams <hannah.williams(a)intel.com> Date: Thu Jan 28 14:25:32 2016 -0800 soc/braswell: Fix Global NVS base address TEST=Boot to OS Signed-off-by: Hannah Williams <hannah.williams(a)intel.com> Change-Id: I9b43eb4f6f7af62a8a0bbe7bfa08feee1eaca24e --- src/soc/intel/braswell/acpi/globalnvs.asl | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/soc/intel/braswell/acpi/globalnvs.asl b/src/soc/intel/braswell/acpi/globalnvs.asl index 5c8a75f..a53834a 100644 --- a/src/soc/intel/braswell/acpi/globalnvs.asl +++ b/src/soc/intel/braswell/acpi/globalnvs.asl @@ -25,8 +25,9 @@ Name(\PICM, 0) /* IOAPIC/8259 */ * we have to fix it up in coreboot's ACPI creation phase. */ +External (NVSA) -OperationRegion (GNVS, SystemMemory, 0xC0DEBABE, 0x2000) +OperationRegion (GNVS, SystemMemory, NVSA, 0x2000) Field (GNVS, ByteAcc, NoLock, Preserve) { /* Miscellaneous */

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Patch set updated for coreboot: nb/amd/mct_ddr3: Fix RDIMM training failure on Fam15h
by Timothy Pearson 28 Jan '16

28 Jan '16

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13148 -gerrit commit 270bb05f76efaec99cfadb96fd8345cb4941e47c Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Tue Nov 24 14:11:52 2015 -0600 nb/amd/mct_ddr3: Fix RDIMM training failure on Fam15h Certain registered DIMMs failed training due to an error likely introduced during historical rebase. Ensure that the SubMemclkRegDly bit is set according to BKDG recommendations on Family 15 processors. Change-Id: I24c95265dada9eabf4df280b6f2b4a1eb9cecaf1 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/northbridge/amd/amdmct/mct_ddr3/mctproc.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctproc.c b/src/northbridge/amd/amdmct/mct_ddr3/mctproc.c index cf13b40..fc62afb 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctproc.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctproc.c @@ -66,6 +66,9 @@ u32 mct_SetDramConfigMisc2(struct DCTStatStruc *pDCTstat, misc2 |= ((cs_mux_67 & 0x1) << 27); misc2 &= ~(0x1 << 26); /* CsMux45 = cs_mux_45 */ misc2 |= ((cs_mux_45 & 0x1) << 26); + + if (pDCTstat->Status & (1 << SB_Registered)) + misc2 |= 1 << SubMemclkRegDly; } else if (pDCTstat->LogicalCPUID & (AMD_DR_Dx | AMD_DR_Cx)) { if (pDCTstat->Status & (1 << SB_Registered)) { misc2 |= 1 << SubMemclkRegDly;

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Patch set updated for coreboot: mainboard/asus/kgpe-d16: Add CPB control CMOS option
by Timothy Pearson 28 Jan '16

28 Jan '16

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13173 -gerrit commit 86fc953a1fe0a975298c737304ed3ce164b3c4c0 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Tue Nov 24 14:12:07 2015 -0600 mainboard/asus/kgpe-d16: Add CPB control CMOS option Change-Id: I28ad2298ad4dfb428dcd41a4f00db88c5e817cd7 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/mainboard/asus/kgpe-d16/cmos.default | 1 + src/mainboard/asus/kgpe-d16/cmos.layout | 5 +++-- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/src/mainboard/asus/kgpe-d16/cmos.default b/src/mainboard/asus/kgpe-d16/cmos.default index a05b9c3..0e7afb3 100644 --- a/src/mainboard/asus/kgpe-d16/cmos.default +++ b/src/mainboard/asus/kgpe-d16/cmos.default @@ -17,6 +17,7 @@ interleave_nodes = Disable interleave_memory_channels = Enable cpu_c_states = Enable cpu_cc6_state = Enable +cpu_core_boost = Enable sata_ahci_mode = Enable sata_alpm = Disable maximum_p_state_limit = 0xf diff --git a/src/mainboard/asus/kgpe-d16/cmos.layout b/src/mainboard/asus/kgpe-d16/cmos.layout index d1c0702..075388e 100644 --- a/src/mainboard/asus/kgpe-d16/cmos.layout +++ b/src/mainboard/asus/kgpe-d16/cmos.layout @@ -48,8 +48,9 @@ entries 476 1 e 1 l3_cache_partitioning 477 1 e 1 ieee1394_controller 478 1 e 1 iommu -479 1 e 1 experimental_memory_speed_boost -480 1 r 0 allow_spd_nvram_cache_restore +479 1 e 1 cpu_core_boost +480 1 e 1 experimental_memory_speed_boost +481 1 r 0 allow_spd_nvram_cache_restore 728 256 h 0 user_data 984 16 h 0 check_sum # Reserve the extended AMD configuration registers

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Patch set updated for coreboot: cpu/amd/fam10h-fam15h: Add CMOS option to disable CPB (core boost)
by Timothy Pearson 28 Jan '16

28 Jan '16

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13172 -gerrit commit 7cda92e4f9ade99d9cbc46d62a453627ba2fceef Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Tue Nov 24 14:12:07 2015 -0600 cpu/amd/fam10h-fam15h: Add CMOS option to disable CPB (core boost) On certain systems and CPUs Core Performance Boost (CPB) may cause sporadic system lockups. This issue is also somewhat known on the various proprietary BIOSes, therefore it seems to be a hardware incompatibility when present. Allow the user to disable CBP if needed. Change-Id: Id6395d067d48963f6c084ad0bf79e23419af24d8 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/cpu/amd/family_10h-family_15h/init_cpus.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/src/cpu/amd/family_10h-family_15h/init_cpus.c b/src/cpu/amd/family_10h-family_15h/init_cpus.c index e2a1bf3..c1ff240 100644 --- a/src/cpu/amd/family_10h-family_15h/init_cpus.c +++ b/src/cpu/amd/family_10h-family_15h/init_cpus.c @@ -987,6 +987,7 @@ void cpuSetAMDMSR(uint8_t node_id) u32 platform; uint64_t revision; uint8_t enable_c_states; + uint8_t enable_cpb; printk(BIOS_DEBUG, "cpuSetAMDMSR "); @@ -1078,6 +1079,19 @@ void cpuSetAMDMSR(uint8_t node_id) enable_c_states = 0; #endif + if (revision & AMD_FAM15_ALL) { + enable_cpb = 1; + if (get_option(&nvram, "cpu_core_boost") == CB_SUCCESS) + enable_cpb = !!nvram; + + if (!enable_cpb) { + /* Disable Core Performance Boost */ + msr = rdmsr(0xc0010015); + msr.lo |= (0x1 << 25); /* CpbDis = 1 */ + wrmsr(0xc0010015, msr); + } + } + printk(BIOS_DEBUG, " done\n"); }

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Patch set updated for coreboot: cpu/amd/fam10h-15h: Set PowerStepUp/PowerStepDown on Fam15h
by Timothy Pearson 28 Jan '16

28 Jan '16

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13174 -gerrit commit 5c6629710aaba7016e16effa2c6b9b7da6533202 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Tue Nov 24 14:12:07 2015 -0600 cpu/amd/fam10h-15h: Set PowerStepUp/PowerStepDown on Fam15h Multilink Family 15h processors were being configured with an incorrect PowerStepUp/PowerStepDown value. Set the value according to the BKDG, and clean up the terrible formatting of the power_up_down() function that led to the incorrect values being overlooked until now. Change-Id: I16e1f5205d6b5f349a3e7167dea04c9eefda4684 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/cpu/amd/family_10h-family_15h/fidvid.c | 96 ++++++++++++++++-------------- 1 file changed, 50 insertions(+), 46 deletions(-) diff --git a/src/cpu/amd/family_10h-family_15h/fidvid.c b/src/cpu/amd/family_10h-family_15h/fidvid.c index 2edb75e..5bef7d3 100644 --- a/src/cpu/amd/family_10h-family_15h/fidvid.c +++ b/src/cpu/amd/family_10h-family_15h/fidvid.c @@ -390,56 +390,60 @@ static u32 nb_clk_did(uint8_t node, uint64_t cpuRev, uint8_t procPkg) { static u32 power_up_down(int node, u8 procPkg) { - u32 dword=0; - /* from CPU rev guide #41322 rev 3.74 June 2010 Table 26 */ - u8 singleLinkFlag = ((procPkg == AMD_PKGTYPE_AM3_2r2) - || (procPkg == AMD_PKGTYPE_S1gX) - || (procPkg == AMD_PKGTYPE_ASB2)); - - if (singleLinkFlag) { - /* - * PowerStepUp=01000b - 50nS - * PowerStepDown=01000b - 50ns - */ - dword |= PW_STP_UP50 | PW_STP_DN50; - } else { - u32 dispRefModeEn = (pci_read_config32(NODE_PCI(node,0),0x68) >> 24) & 1; - u32 isocEn = 0; - int j; - for(j=0 ; (j<4) && (!isocEn) ; j++ ) { - u8 offset; - if (AMD_CpuFindCapability(node, j, &offset)) { - isocEn = (pci_read_config32(NODE_PCI(node,0),offset+4) >>12) & 1; - } - } - - if (dispRefModeEn || isocEn) { - dword |= PW_STP_UP50 | PW_STP_DN50 ; - } else { - /* get number of cores for PowerStepUp & PowerStepDown in server - 1 core - 400nS - 0000b - 2 cores - 200nS - 0010b - 3 cores - 133nS -> 100nS - 0011b - 4 cores - 100nS - 0011b + uint32_t dword=0; + /* from CPU rev guide #41322 rev 3.74 June 2010 Table 26 */ + u8 singleLinkFlag = ((procPkg == AMD_PKGTYPE_AM3_2r2) + || (procPkg == AMD_PKGTYPE_S1gX) + || (procPkg == AMD_PKGTYPE_ASB2)); + + if (singleLinkFlag) { + /* + * PowerStepUp=01000b - 50nS + * PowerStepDown=01000b - 50ns */ - switch (get_core_num_in_bsp(node)) { - case 0: - dword |= PW_STP_UP400 | PW_STP_DN400; - break; - case 1: - case 2: - dword |= PW_STP_UP200 | PW_STP_DN200; - break; - case 3: - dword |= PW_STP_UP100 | PW_STP_DN100; - break; - default: + dword |= PW_STP_UP50 | PW_STP_DN50; + } else { + uint32_t dispRefModeEn = (pci_read_config32(NODE_PCI(node,0),0x68) >> 24) & 1; + uint32_t isocEn = 0; + int j; + for (j=0 ; (j<4) && (!isocEn) ; j++ ) { + u8 offset; + if (AMD_CpuFindCapability(node, j, &offset)) { + isocEn = (pci_read_config32(NODE_PCI(node,0),offset+4) >>12) & 1; + } + } + + if (is_fam15h()) { + /* Family 15h always uses 100ns for multilink processors */ dword |= PW_STP_UP100 | PW_STP_DN100; - break; + } else if (dispRefModeEn || isocEn) { + dword |= PW_STP_UP50 | PW_STP_DN50 ; + } else { + /* get number of cores for PowerStepUp & PowerStepDown in server + * 1 core - 400nS - 0000b + * 2 cores - 200nS - 0010b + * 3 cores - 133nS -> 100nS - 0011b + * 4 cores - 100nS - 0011b + */ + switch (get_core_num_in_bsp(node)) { + case 0: + dword |= PW_STP_UP400 | PW_STP_DN400; + break; + case 1: + case 2: + dword |= PW_STP_UP200 | PW_STP_DN200; + break; + case 3: + dword |= PW_STP_UP100 | PW_STP_DN100; + break; + default: + dword |= PW_STP_UP100 | PW_STP_DN100; + break; + } } - } } - return dword; + + return dword; } static void config_clk_power_ctrl_reg0(uint8_t node, uint64_t cpuRev, uint8_t procPkg) {

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New patch to review for coreboot: build system: allow modifying cbfstool options for files-in-regions
by Patrick Georgi 28 Jan '16

28 Jan '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13505 -gerrit commit 31ab1d95cea5b6eff91ee65feec50abdf457b1ae Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Thu Jan 28 22:34:50 2016 +0100 build system: allow modifying cbfstool options for files-in-regions By implementing a more complex options-for-region function, special needs for certain files in certain regions can be dealt with. Change-Id: I2e1e08d5357b717011c41675f76908bf2319f91d Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> --- Makefile.inc | 14 +++++++++++--- 1 file changed, 11 insertions(+), 3 deletions(-) diff --git a/Makefile.inc b/Makefile.inc index 8b69109..122b83a 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -645,6 +645,13 @@ extract_nth=$(subst *,$(spc),$(patsubst -%-,%,$(word $(1), $(subst |,- -,-$(2)-) # multiple CBFSes in fmap regions, override it. regions-for-file ?= COREBOOT +# options-for-region +# $(call options-for-region,$(filename),$(region),$(options)) +# +# Returns potentially modified options, depending on file and region. +# Default is to return it unmodified +options-for-region ?= $(3) + ifeq ($(CONFIG_CBFS_AUTOGEN_ATTRIBUTES),y) cbfs-autogen-attributes=-g endif @@ -660,9 +667,10 @@ define cbfs-add-cmd-for-region $(if $(call extract_nth,4,$(1)),-c $(call extract_nth,4,$(1))) \ $(cbfs-autogen-attributes) \ -r $(2) \ - $(if $(call extract_nth,6,$(1)),-a $(call extract_nth,6,$(file)), \ - $(if $(call extract_nth,5,$(file)),-b $(call extract_nth,5,$(file)))) \ - $(call extract_nth,7,$(1)) + $(call options-for-region,$(call extract_nth,2,$(1)),$(2), \ + $(if $(call extract_nth,6,$(1)),-a $(call extract_nth,6,$(file)), \ + $(if $(call extract_nth,5,$(file)),-b $(call extract_nth,5,$(file)))) \ + $(call extract_nth,7,$(1))) endef # Empty line before endef is necessary so cbfs-add-cmd-for-region ends in a

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New patch to review for coreboot: build system: Unwind multi-region cbfstool add commands
by Patrick Georgi 28 Jan '16

28 Jan '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13504 -gerrit commit 0d47172af0032ac6fcd305e8f738b2be211a5d58 Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Thu Jan 28 22:22:38 2016 +0100 build system: Unwind multi-region cbfstool add commands Add files to fmap regions one-by-one, so we can modify options per-file-per-region. Change-Id: Ic3ff5a4e563796c9fdd5705236aef37c883abf5e Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> --- Makefile.inc | 21 +++++++++++++++++---- 1 file changed, 17 insertions(+), 4 deletions(-) diff --git a/Makefile.inc b/Makefile.inc index 84d7a2d..8b69109 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -649,9 +649,9 @@ ifeq ($(CONFIG_CBFS_AUTOGEN_ATTRIBUTES),y) cbfs-autogen-attributes=-g endif -define cbfs-add-cmd - printf " CBFS $(call extract_nth,2,$(1))\n" - $(if $(2),-$(CBFSTOOL) $@.tmp remove -n $(call extract_nth,2,$(file)) 2>/dev/null) +# cbfs-add-cmd-for-region +# $(call cbfs-add-cmd-for-region,file in extract_nth format,region name) +define cbfs-add-cmd-for-region $(CBFSTOOL) $@.tmp \ add$(if $(filter stage,$(call extract_nth,3,$(1))),-stage)$(if $(filter payload,$(call extract_nth,3,$(1))),-payload) \ -f $(call extract_nth,1,$(1)) \ @@ -659,10 +659,23 @@ define cbfs-add-cmd $(if $(filter-out stage,$(call extract_nth,3,$(1))),-t $(call extract_nth,3,$(1))) \ $(if $(call extract_nth,4,$(1)),-c $(call extract_nth,4,$(1))) \ $(cbfs-autogen-attributes) \ - -r $(call regions-for-file,$(call extract_nth,2,$(1))) \ + -r $(2) \ $(if $(call extract_nth,6,$(1)),-a $(call extract_nth,6,$(file)), \ $(if $(call extract_nth,5,$(file)),-b $(call extract_nth,5,$(file)))) \ $(call extract_nth,7,$(1)) + +endef +# Empty line before endef is necessary so cbfs-add-cmd-for-region ends in a +# newline + +# cbfs-add-cmd +# $(call cbfs-add-cmd,file in extract_nth format,non-empty if file removal requested) +define cbfs-add-cmd + printf " CBFS $(call extract_nth,2,$(1))\n" + $(if $(2),-$(CBFSTOOL) $@.tmp remove -n $(call extract_nth,2,$(file)) 2>/dev/null) + $(eval _tmp-cbfs-add-cmd-regions=$(call regions-for-file,$(call extract_nth,2,$(1)))) \ + $(foreach region,$(subst $(comma),$(spc),$(_tmp-cbfs-add-cmd-regions)), \ + $(call cbfs-add-cmd-for-region,$(1),$(region))) endef cbfs-files=$(cbfs-files-fixed) $(cbfs-files-aligned) $(cbfs-files-regular)

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New patch to review for coreboot: build system: deduplicate users of cbfs-add-cmd
by Patrick Georgi 28 Jan '16

28 Jan '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13503 -gerrit commit 099d46e1271a9cb206f9c061b0399d1828f2b81a Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Thu Jan 28 21:57:29 2016 +0100 build system: deduplicate users of cbfs-add-cmd When adding the cbfstool remove requirement of the UPDATE_IMAGE path to cbfs-add-cmd, prebuil[dt]-files become identical in both cases. Change-Id: I80faaf1c83368b9dd00a9f247bf89e6d596be996 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> --- Makefile.inc | 12 +++--------- 1 file changed, 3 insertions(+), 9 deletions(-) diff --git a/Makefile.inc b/Makefile.inc index 3fcddbc..84d7a2d 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -651,6 +651,7 @@ endif define cbfs-add-cmd printf " CBFS $(call extract_nth,2,$(1))\n" + $(if $(2),-$(CBFSTOOL) $@.tmp remove -n $(call extract_nth,2,$(file)) 2>/dev/null) $(CBFSTOOL) $@.tmp \ add$(if $(filter stage,$(call extract_nth,3,$(1))),-stage)$(if $(filter payload,$(call extract_nth,3,$(1))),-payload) \ -f $(call extract_nth,1,$(1)) \ @@ -665,10 +666,10 @@ define cbfs-add-cmd endef cbfs-files=$(cbfs-files-fixed) $(cbfs-files-aligned) $(cbfs-files-regular) -ifneq ($(CONFIG_UPDATE_IMAGE),y) -prebuild-files = $(foreach file,$(cbfs-files), $(call cbfs-add-cmd,$(file))) prebuilt-files = $(foreach file,$(cbfs-files), $(call extract_nth,1,$(file))) +prebuild-files = $(foreach file,$(cbfs-files), $(call cbfs-add-cmd,$(file),$(CONFIG_UPDATE_IMAGE))) +ifneq ($(CONFIG_UPDATE_IMAGE),y) ifeq ($(CONFIG_FMDFILE),) # For a description of the flash layout described by these variables, check # the $(DEFAULT_FLASHMAP) .fmd files. @@ -760,13 +761,6 @@ endif # ifeq ($(CONFIG_ARCH_X86),y) $(prebuild-files) true mv $@.tmp $@ else # ifneq ($(CONFIG_UPDATE_IMAGE),y) -prebuilt-files = $(foreach file,$(cbfs-files), $(call extract_nth,1,$(file))) -# Add all cbfs files to image of the form: CONFIG_CBFS_PREFIX/<filename> -prebuild-files = \ - $(foreach file,$(cbfs-files), \ - $(CBFSTOOL) $@.tmp remove -n $(call extract_nth,2,$(file)) 2>/dev/null ; \ - $(call cbfs-add-cmd,$(file))) - .PHONY: $(obj)/coreboot.pre $(obj)/coreboot.pre: $$(prebuilt-files) $(CBFSTOOL) mv $(obj)/coreboot.rom $@.tmp || \

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coreboot-gerrit January 2016