coreboot-gerrit January 2016

coreboot-gerrit@coreboot.org

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Patch merged into coreboot/master: cpu/amd/fam10h-fam15h: Correctly create APIC ID on single node systems
by gerrit＠coreboot.org 29 Jan '16

29 Jan '16

the following patch was just integrated into master: commit 71f864191ff6f9c8afe9acf0706b6fe07c5cf68d Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Tue Nov 24 14:11:53 2015 -0600 cpu/amd/fam10h-fam15h: Correctly create APIC ID on single node systems The existing code generated an incorrect boot APIC ID from node and core number for single node packages, leading to a boot failure when the second node was installed. Properly generate the boot APIC ID from node and core number. Change-Id: I7a00e216a6841c527b0a016fa07befb42162414a Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/13149 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply(a)raptorengineeringinc.com> Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/13149 for details. -gerrit

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Patch merged into coreboot/master: mb/gigabyte/ga-g41m-es2l: Remove PMBASE settings and commented code.
by gerrit＠coreboot.org 29 Jan '16

29 Jan '16

the following patch was just integrated into master: commit 9253ce60c4bce74854938c22008829da48ae97a9 Author: Damien Zammit <damien(a)zamaudio.com> Date: Tue Jan 26 17:24:48 2016 +1100 mb/gigabyte/ga-g41m-es2l: Remove PMBASE settings and commented code. Fixed incorrect comment regarding port 80 LPC route. Change-Id: Ifbb73753d5a0737418b869085f2329a02504e5dc Signed-off-by: Damien Zammit <damien(a)zamaudio.com> Reviewed-on: https://review.coreboot.org/13466 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> Reviewed-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> See https://review.coreboot.org/13466 for details. -gerrit

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Patch merged into coreboot/master: mb/gigabyte/ga-g41m-es2l: Remove copy-pasted cstates
by gerrit＠coreboot.org 29 Jan '16

29 Jan '16

the following patch was just integrated into master: commit c70966cd267783e2819418e5d881a2098c476d80 Author: Damien Zammit <damien(a)zamaudio.com> Date: Tue Jan 26 17:17:27 2016 +1100 mb/gigabyte/ga-g41m-es2l: Remove copy-pasted cstates Change-Id: I5b6edbd97d4e6ed8b03f2f319a338022647e26ea Signed-off-by: Damien Zammit <damien(a)zamaudio.com> Reviewed-on: https://review.coreboot.org/13465 Tested-by: build bot (Jenkins) Reviewed-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> See https://review.coreboot.org/13465 for details. -gerrit

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Patch merged into coreboot/master: mb/gigabyte/ga-g41m-es2l: Move MMCONF base address to 0xe0000000
by gerrit＠coreboot.org 29 Jan '16

29 Jan '16

the following patch was just integrated into master: commit c4d317f10799fadcd6cf66558f363041106699ae Author: Damien Zammit <damien(a)zamaudio.com> Date: Tue Jan 26 17:15:55 2016 +1100 mb/gigabyte/ga-g41m-es2l: Move MMCONF base address to 0xe0000000 Change-Id: I3873d92069cc1d113a8092d609d1768ff45cbd45 Signed-off-by: Damien Zammit <damien(a)zamaudio.com> Reviewed-on: https://review.coreboot.org/13129 Reviewed-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Tested-by: build bot (Jenkins) See https://review.coreboot.org/13129 for details. -gerrit

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Patch merged into coreboot/master: nb/intel/x4x: Move to early cbmem
by gerrit＠coreboot.org 29 Jan '16

29 Jan '16

the following patch was just integrated into master: commit 5680fafb4d2cdc1d914226ff4d01b9b12ba75097 Author: Damien Zammit <damien(a)zamaudio.com> Date: Fri Jan 22 22:12:30 2016 +1100 nb/intel/x4x: Move to early cbmem Previously with errors in the ram init, early cbmem was disabled. Now that the ram is working correctly, set as early cbmem platform and update all (1) boards to use it. Tested on GA-G41M-ES2L Change-Id: I5925c28821537f0e326b4f5a2ac39778e4724a3c Signed-off-by: Damien Zammit <damien(a)zamaudio.com> Reviewed-on: https://review.coreboot.org/13131 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> See https://review.coreboot.org/13131 for details. -gerrit

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Patch merged into coreboot/master: nb/intel/x4x: Cleanup gma.c
by gerrit＠coreboot.org 29 Jan '16

29 Jan '16

the following patch was just integrated into master: commit 216fc50411a354917cee97b243cdb1dbf1e0a76d Author: Damien Zammit <damien(a)zamaudio.com> Date: Fri Jan 22 19:13:18 2016 +1100 nb/intel/x4x: Cleanup gma.c Tidy up the code and move vga_textmode_init() later Change-Id: I49967e7197416c955ae6c8775eac7d1a60c92d1c Signed-off-by: Damien Zammit <damien(a)zamaudio.com> Reviewed-on: https://review.coreboot.org/13128 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> See https://review.coreboot.org/13128 for details. -gerrit

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Patch merged into coreboot/master: nb/intel/x4x: Tidy up raminit and fix msbpos() function
by gerrit＠coreboot.org 29 Jan '16

29 Jan '16

the following patch was just integrated into master: commit d63115daa8830ee94b188bbed76eb460aa05eb8a Author: Damien Zammit <damien(a)zamaudio.com> Date: Fri Jan 22 19:11:44 2016 +1100 nb/intel/x4x: Tidy up raminit and fix msbpos() function - Fix bug with msbpos, it was not returning the correct result due to typo in logic, and unsigned value needed to be negative. - Add reclaim above 4GiB - Fix to ME related registers near the end of raminit Change-Id: I04acd0593a457437ee4a42e14b287b2b17a160af Signed-off-by: Damien Zammit <damien(a)zamaudio.com> Reviewed-on: https://review.coreboot.org/13127 Tested-by: build bot (Jenkins) Reviewed-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> See https://review.coreboot.org/13127 for details. -gerrit

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Patch merged into coreboot/master: nb/intel/x4x: Tidy up northbridge
by gerrit＠coreboot.org 29 Jan '16

29 Jan '16

the following patch was just integrated into master: commit fe9876a7631c7982fccf38692dbed955e229f47b Author: Damien Zammit <damien(a)zamaudio.com> Date: Fri Jan 22 19:11:05 2016 +1100 nb/intel/x4x: Tidy up northbridge - Add device enable macros - Set the PMBASE correctly through southbridge device Change-Id: I1b8cc3de96b1ecaf01e31bad8fba1fada8671c2d Signed-off-by: Damien Zammit <damien(a)zamaudio.com> Reviewed-on: https://review.coreboot.org/13126 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Reviewed-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> See https://review.coreboot.org/13126 for details. -gerrit

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Patch merged into coreboot/master: nb/intel/x4x: Fix memory hole with both channels populated
by gerrit＠coreboot.org 29 Jan '16

29 Jan '16

the following patch was just integrated into master: commit 9fb08f55a86467ba1a36d4f5e6196a77b534778d Author: Damien Zammit <damien(a)zamaudio.com> Date: Fri Jan 22 18:56:23 2016 +1100 nb/intel/x4x: Fix memory hole with both channels populated Previously, 0xa0000000 to 0xc0000000 needed to be reserved as a non-usable memory hole because it would hang on memory i/o. Memtest86+ now passes with no errors on both channels populated. Tested on GA-G41M-ES2L with 2x2GiB sticks of ram. Change-Id: Ib52a63a80f5f69c16841f10ddb896ab3c7d30462 Signed-off-by: Damien Zammit <damien(a)zamaudio.com> Reviewed-on: https://review.coreboot.org/13125 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Tested-by: build bot (Jenkins) See https://review.coreboot.org/13125 for details. -gerrit

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Patch set updated for coreboot: include/device: Move inline functions from pci_def.h to pci.h
by Alexandru Gagniuc 28 Jan '16

28 Jan '16

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13300 -gerrit commit 81f5e37473bde2d7ed27d3ede0abac412424d0d8 Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Tue Jan 5 17:00:27 2016 -0800 include/device: Move inline functions from pci_def.h to pci.h pci_def.h is supposed to only contain definitions, such that it may be included in assembly files. Declaration of functions in said file prevents that. Change-Id: I0f90a74291c8a2ef7a1e1027d2d2182f896050fb Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- src/include/device/pci.h | 7 +++++++ src/include/device/pci_def.h | 7 ------- 2 files changed, 7 insertions(+), 7 deletions(-) diff --git a/src/include/device/pci.h b/src/include/device/pci.h index fe31b54..9ef3614 100644 --- a/src/include/device/pci.h +++ b/src/include/device/pci.h @@ -119,6 +119,13 @@ unsigned pci_find_capability(device_t dev, unsigned cap); void pci_early_bridge_init(void); int pci_early_device_probe(u8 bus, u8 dev, u32 mmio_base); +#ifndef __ROMCC__ +static inline int pci_base_address_is_memory_space(unsigned int attr) +{ + return (attr & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_MEMORY; +} +#endif + #endif /* CONFIG_PCI */ #endif /* PCI_H */ diff --git a/src/include/device/pci_def.h b/src/include/device/pci_def.h index 04cf945..ef3427b 100644 --- a/src/include/device/pci_def.h +++ b/src/include/device/pci_def.h @@ -78,13 +78,6 @@ #define PCI_BASE_ADDRESS_IO_ATTR_MASK 0x03 /* bit 1 is reserved if address_space = 1 */ -#ifndef __ROMCC__ -static inline int pci_base_address_is_memory_space(unsigned int attr) -{ - return (attr & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_MEMORY; -} -#endif - /* Header type 0 (normal devices) */ #define PCI_CARDBUS_CIS 0x28 #define PCI_SUBSYSTEM_VENDOR_ID 0x2c

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coreboot-gerrit January 2016