Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/11784
-gerrit
commit 09a4a872d9a1e9ff68775a7aaace3af4f17466fd
Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com>
Date: Fri Oct 2 12:42:26 2015 -0700
arch/x86: Rename bootblock.S to bootblock_romcc.S
bootblock.S was used strictly for setting up the system so that the
assembly generated by ROMCC could be executed. Since the
infrastructure now exists to run a bootblock wihtout ROMCC, rename
this file accordingly. this is done to prevent any future confusion.
Change-Id: Icbf5804b66b9517f9ceb352bed86978dcf92228f
Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com>
---
src/arch/x86/Makefile.inc | 10 ++++----
src/arch/x86/bootblock.S | 40 -------------------------------
src/arch/x86/bootblock_romcc.S | 53 ++++++++++++++++++++++++++++++++++++++++++
3 files changed, 58 insertions(+), 45 deletions(-)
diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc
index bc4a7d4..bc64815 100644
--- a/src/arch/x86/Makefile.inc
+++ b/src/arch/x86/Makefile.inc
@@ -107,9 +107,6 @@ bootblock-y += memcpy.c
bootblock-y += memset.c
bootblock-y += mmap_boot.c
-# Add the assembly file that pulls in the rest of the dependencies in
-# the right order. Make sure the auto generated bootblock.inc is a proper
-# dependency. Make the same true for the linker sript.
bootblock-y += id.S
$(obj)/arch/x86/id.bootblock.o: $(obj)/build.h
@@ -132,9 +129,12 @@ else
LDFLAGS_bootblock += -m elf_x86_64 --oformat elf64-x86-64
endif
-bootblock-y += bootblock.S
+# Add the assembly file that pulls in the rest of the dependencies in
+# the right order. Make sure the auto generated bootblock.inc is a proper
+# dependency. Make the same true for the linker sript.
+bootblock-y += bootblock_romcc.S
bootblock-y += walkcbfs.S
-$(obj)/arch/x86/bootblock.bootblock.o: $(objgenerated)/bootblock.inc
+$(obj)/arch/x86/bootblock_romcc.bootblock.o: $(objgenerated)/bootblock.inc
bootblock-y += bootblock.ld
$(obj)/arch/x86/bootblock.bootblock.ld: $(objgenerated)/bootblock.ld
diff --git a/src/arch/x86/bootblock.S b/src/arch/x86/bootblock.S
deleted file mode 100644
index 27a23eb..0000000
--- a/src/arch/x86/bootblock.S
+++ /dev/null
@@ -1,40 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2015 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-/* This file assembles the bootblock program by the order of the includes. Thus,
- * it's extremely important that one pays very careful attention to the order
- * of the includes. */
-
-#include <arch/x86/prologue.inc>
-#include <cpu/x86/16bit/entry16.inc>
-#include <cpu/x86/16bit/reset16.inc>
-#include <cpu/x86/32bit/entry32.inc>
-
-#ifdef CONFIG_CHIPSET_BOOTBLOCK_INCLUDE
-#include CONFIG_CHIPSET_BOOTBLOCK_INCLUDE
-#endif
-
-#if IS_ENABLED(CONFIG_SSE)
-#include <cpu/x86/sse_enable.inc>
-#endif
-
-/*
- * This bootblock.inc file is generated by ROMCC. The above program flow
- * falls through to this point. ROMCC assumes the last function it parsed
- * is the main function and it places its instructions at the beginning of
- * the generated file. Moreover, any library/common code needed in bootblock
- * needs to come after bootblock.inc.
- */
-#include <generated/bootblock.inc>
diff --git a/src/arch/x86/bootblock_romcc.S b/src/arch/x86/bootblock_romcc.S
new file mode 100644
index 0000000..6c1723a
--- /dev/null
+++ b/src/arch/x86/bootblock_romcc.S
@@ -0,0 +1,53 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/*
+ * This is the original bootblock used by coreboot on x86 systems. It contains
+ * a monolithic code flow, assembled from the following stages:
+ * - reset16.inc: the reset vector
+ * - entry16.inc: protected mode setup
+ * - entry32.inc: segment descriptor setup
+ * - CONFIG_CHIPSET_BOOTBLOCK_INCLUDE: chipset-specific initialization
+ * - generated/bootblock.inc: ROMCC part of the bootblock
+ *
+ * This is used on platforms which do not select C_ENVIRONMENT_BOOTBLOCK, and it
+ * tries to do the absolute minimum before walking CBFS and jumping to romstage.
+ *
+ * This file assembles the bootblock program by the order of the includes. Thus,
+ * it's extremely important that one pays very careful attention to the order
+ * of the includes.
+ */
+
+#include <arch/x86/prologue.inc>
+#include <cpu/x86/16bit/entry16.inc>
+#include <cpu/x86/16bit/reset16.inc>
+#include <cpu/x86/32bit/entry32.inc>
+
+#ifdef CONFIG_CHIPSET_BOOTBLOCK_INCLUDE
+#include CONFIG_CHIPSET_BOOTBLOCK_INCLUDE
+#endif
+
+#if IS_ENABLED(CONFIG_SSE)
+#include <cpu/x86/sse_enable.inc>
+#endif
+
+/*
+ * This bootblock.inc file is generated by ROMCC. The above program flow
+ * falls through to this point. ROMCC assumes the last function it parsed
+ * is the main function and it places its instructions at the beginning of
+ * the generated file. Moreover, any library/common code needed in bootblock
+ * needs to come after bootblock.inc.
+ */
+#include <generated/bootblock.inc>
the following patch was just integrated into master:
commit cc728f02846a1752215503dc7897caf6fc5a1fc1
Author: shkim <sh_.kim(a)samsung.com>
Date: Tue Sep 22 17:53:58 2015 +0900
soc/braswell: Add interface to program USB2_COMPBG register
Add interface to program USB2_COMPBG register to set
HS_DISC_BG and HS_SQ reference voltage for each project.
TEST=Get build success and do EFT test
Original-Reviewed-on: https://chromium-review.googlesource.com/300846
Original-Reviewed-by: Shawn N <shawnn(a)chromium.org>
Original-Tested-by: shkim <sh_.kim(a)samsung.com>
Change-Id: If2201829e1a16b4f9916547f08c24e9291358325
Signed-off-by: Kenji Chen <kenji.chen(a)intel.com>
Signed-off-by: shkim <sh_.kim(a)samsung.com>
Signed-off-by: Hannah Williams <hannah.williams(a)intel.com>
Reviewed-on: https://review.coreboot.org/12739
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth(a)google.com>
See https://review.coreboot.org/12739 for details.
-gerrit
the following patch was just integrated into master:
commit e8cc52fab012798dd9f5ad12cd6a8d238ea360c7
Author: Freddy Paul <freddy.paul(a)intel.com>
Date: Fri Oct 2 19:06:57 2015 -0700
ec/google/chromeec/acpi :Enable DPTF charger/TSR1/TSR2 participant.
TEST=Plug/Unplug AC Adapter multiple times and make sure device is
charging properly.
Original-Reviewed-on: https://chromium-review.googlesource.com/303990
Original-Reviewed-by: Jenny Tc <jenny.tc(a)intel.com>
Original-Reviewed-by: T.H. Lin <T.H_Lin(a)quantatw.com>
Original-Tested-by: T.H. Lin <T.H_Lin(a)quantatw.com>
Original-Tested-by: Jagadish Krishnamoorthy <jagadish.krishnamoorthy(a)intel.com>
Original-Reviewed-by: Divya Jyothi <divya.jyothi(a)intel.com>
Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
Original-Signed-off-by: Freddy Paul <freddy.paul(a)intel.com>
Change-Id: I188e80e6688d0bac5bed6dd64cd2d0feefa30d3f
Signed-off-by: Hannah Williams <hannah.williams(a)intel.com>
Signed-off-by: Freddy Paul <freddy.paul(a)intel.com>
Signed-off-by: Hannah Williams <hannah.williams(a)intel.com>
Reviewed-on: https://review.coreboot.org/12748
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth(a)google.com>
See https://review.coreboot.org/12748 for details.
-gerrit
the following patch was just integrated into master:
commit 01be52eca9c1c207613c8d4070a1982ddac9af2f
Author: Jenny TC <jenny.tc(a)intel.com>
Date: Fri Jul 24 15:04:06 2015 +0530
soc/braswell/acpi/DPTF: Write TCHG state on AC connect.
DPTF should update the charger cooling device state during
boot time and every 3 seconds after boot. But 3 seconds polling
doesn't seems to be working with current version of DPTF.
This impacts charging since DPTF writes states 4 when charger
is not connected at boot time. On connecting the charger,
DPTF doesn't write 0 to enable charging. This issue is addressed
by calling the PPPC function to read cooling device state and passing
the value to SPPC to set cooling device state. This doesn't
compromise safety since DPTF can override this value
later based on the platform thermal condition. Also this provides
additional safety measure in the unlikely event that DPTF crashes
and is not re-spawned by OS. With this patch even after DPTF crashes,
if the power adapter is plugged it would still allow the system to
charge correctly.
Original-Reviewed-on: https://chromium-review.googlesource.com/288460
Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
Original-Tested-by: Jenny Tc <jenny.tc(a)intel.com>
Change-Id: I50c7666b86e45d5ab537a9d4149e6c71eba04e50
Signed-off-by: Hannah Williams <hannah.williams(a)intel.com>
Reviewed-on: https://review.coreboot.org/12729
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth(a)google.com>
See https://review.coreboot.org/12729 for details.
-gerrit
the following patch was just integrated into master:
commit 060bc7941f645c9bba27ec618591bc3f1ce89685
Author: Divagar Mohandass <divagar.mohandass(a)intel.com>
Date: Tue Sep 29 15:01:58 2015 +0530
intel/strago: Update DPTF parameters to higher temperature.
Fish bowl HTML5 graphics benchmark with 250 fish
is not reaching 60 FPS. This change will update
the DPTF parameters to accommodate this test.
TEST=Run fish bowl benchmark with 250 fish
and check for 60 FPS.
Change-Id: I6b6827199cb0f5ab44c354abc477ea73e4de9ec5
Original-Signed-off-by: Divagar Mohandass <divagar.mohandass(a)intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/302208
Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
Reviewed-on: https://review.coreboot.org/13484
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth(a)google.com>
See https://review.coreboot.org/13484 for details.
-gerrit