coreboot-gerrit January 2016

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Patch set updated for coreboot: soc/apollolake: Add initial cache-as-ram setup for bootblock
by Alexandru Gagniuc 28 Jan '16

28 Jan '16

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13301 -gerrit commit a4af8d0acf1ac4a58996f021e99223920d95a6d4 Author: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> Date: Tue Oct 6 17:16:41 2015 -0700 soc/apollolake: Add initial cache-as-ram setup for bootblock This is the minimum setup needed to both get cache-as-ram setup and a C environment working. On apollolake, we only get 32 KiB of data loaded into an SRAM that is readonly to the main CPU. Due to this restriction we have to set CAR and a C environment very early on. While we originally had the code written in ATT syntax, we decided to rewrite in intel syntax so we can better collaborate with other teams. The rewrite also helped us catch a few bugs. Change-Id: I65c51f972580609d2c1f03dfe2a86bc5d45d1e46 Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> --- src/soc/intel/apollolake/Kconfig | 27 ++++ src/soc/intel/apollolake/Makefile.inc | 6 + src/soc/intel/apollolake/bootblock/bootblock_car.c | 23 +++ src/soc/intel/apollolake/bootblock/cache_as_ram.S | 162 +++++++++++++++++++++ .../apollolake/bootblock/early_chipset_config.S | 94 ++++++++++++ src/soc/intel/apollolake/include/soc/bootblock.h | 18 +++ 6 files changed, 330 insertions(+) diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index ca38494..f7ae68e 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -18,6 +18,7 @@ config CPU_SPECIFIC_OPTIONS select SSE2 select SUPPORT_CPU_UCODE_IN_CBFS # Misc options + select C_ENVIRONMENT_BOOTBLOCK select COLLECT_TIMESTAMPS select HAVE_INTEL_FIRMWARE select MMCONF_SUPPORT @@ -32,6 +33,32 @@ config CPU_SPECIFIC_OPTIONS select SOC_INTEL_COMMON select UDELAY_TSC +config MMCONF_BASE_ADDRESS + hex "PCI MMIO Base Address" + default 0xe0000000 + +config IOSF_BASE_ADDRESS + hex "MMIO Base Address of sideband bus" + default 0xd0000000 + +config DCACHE_RAM_BASE + hex "Base address of cache-as-RAM" + default 0xfef00000 + +config DCACHE_RAM_SIZE + hex "Length in bytes of cache-as-RAM" + default 0x80000 + help + The size of the cache-as-ram region required during bootblock + and/or romstage. + +config DCACHE_RAM_BOOTBLOCK_STACK_SIZE + hex + default 0x800 + help + The amount of anticipated stack usage from the bootblock during + pre-romstage initialization. + config CPU_ADDR_BITS int default 36 diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc index b37cf8d..cc3e013 100644 --- a/src/soc/intel/apollolake/Makefile.inc +++ b/src/soc/intel/apollolake/Makefile.inc @@ -7,8 +7,14 @@ subdirs-y += ../../../cpu/x86/mtrr subdirs-y += ../../../cpu/x86/smm subdirs-y += ../../../cpu/x86/tsc +bootblock-y += bootblock/bootblock_car.c +bootblock-y += bootblock/cache_as_ram.S +bootblock-y += bootblock/early_chipset_config.S + romstage-y += placeholders.c smm-y += placeholders.c ramstage-y += placeholders.c +CPPFLAGS_common += -I$(src)/soc/intel/apollolake/include + endif diff --git a/src/soc/intel/apollolake/bootblock/bootblock_car.c b/src/soc/intel/apollolake/bootblock/bootblock_car.c new file mode 100644 index 0000000..4be0815 --- /dev/null +++ b/src/soc/intel/apollolake/bootblock/bootblock_car.c @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * (Written by Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include <arch/io.h> +#include <soc/bootblock.h> + +void bootblock_car_main(void) +{ + /* Quick post code to show we made it to C code */ + outb(0x30, 0x80); + /* Don't return, so we see the above post code */ + while (1) + ; +} diff --git a/src/soc/intel/apollolake/bootblock/cache_as_ram.S b/src/soc/intel/apollolake/bootblock/cache_as_ram.S new file mode 100644 index 0000000..944c73d --- /dev/null +++ b/src/soc/intel/apollolake/bootblock/cache_as_ram.S @@ -0,0 +1,162 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * (Written by Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include <device/pci_def.h> +#include <cpu/x86/mtrr.h> +#include <cpu/x86/cache.h> +#include <cpu/x86/cr.h> +#include <cpu/x86/post_code.h> + +#define EVICT_CTL_MSR 0x2e0 + +.intel_syntax noprefix + +#undef post_code +#define post_code(value) \ + mov al, value; \ + outb CONFIG_POST_IO_PORT, al + +.global cache_as_ram +cache_as_ram: + post_code(0x21) + + /* Clear/disable fixed MTRRs */ + mov ebx, offset fixed_mtrr_list_size + xor eax, eax + xor edx, edx +clear_fixed_mtrr: + add ebx, -2 + movzxw ecx, word ptr [fixed_mtrr_list + ebx] + wrmsr + jnz clear_fixed_mtrr + + post_code(0x22) + + /* Figure put how many MTRRs we have, and clear them out */ + mov ecx, MTRR_CAP_MSR + rdmsr + movzxb ebx, al /* Number of variable MTRRs */ + mov ecx, MTRR_PHYS_BASE(0) + xor eax, eax + xor edx, edx +clear_var_mtrr: + wrmsr + inc ecx + wrmsr + inc ecx + dec ebx + jnz clear_var_mtrr + + post_code(0x23) + + /* Disable MTTRs, configure default memory type to uncacheable (UC) */ + mov ecx, MTRR_DEF_TYPE_MSR + rdmsr + and eax, ~0xcff + wrmsr + + post_code(0x24) + + /* Configure CAR region as write-back (WB) */ + mov ecx, MTRR_PHYS_BASE(0) + mov eax, CONFIG_DCACHE_RAM_BASE /* base */ + or eax, MTRR_TYPE_WRBACK + xor edx, edx + wrmsr + + /* Configure the MTRR mask for the size region */ + mov ecx, MTRR_PHYS_MASK(0) + mov eax, ~(CONFIG_DCACHE_RAM_SIZE - 1) /* size mask */ + or eax, MTRR_PHYS_MASK_VALID + wrmsr + + post_code(0x25) + + /* Enable variable MTRRs */ + mov ecx, MTRR_DEF_TYPE_MSR + rdmsr + or eax, MTRR_DEF_TYPE_EN + wrmsr + + /* Enable caching */ + mov eax, cr0 + and eax, ~(CR0_CD | CR0_NW) + invd + mov cr0, eax + + /* Disable cache eviction (setup stage) */ + mov ecx, EVICT_CTL_MSR + rdmsr + or eax, 1 + wrmsr + + post_code(0x26) + + /* Write something to each cache line */ + mov eax, 0xcafebabe + mov edi, CONFIG_DCACHE_RAM_BASE + mov ecx, (CONFIG_DCACHE_RAM_SIZE >> 6) +cache_init_loop: + mov [edi], eax + sfence + add edi, 64 + loop cache_init_loop + + post_code(0x27) + + /* Disable cache eviction (run stage) */ + mov ecx, EVICT_CTL_MSR + rdmsr + or eax, 2 + wrmsr + + post_code(0x28) + +car_init_done: + + /* Setup bootblock stack */ + mov esp, CONFIG_DCACHE_RAM_BASE + add esp, CONFIG_DCACHE_RAM_BOOTBLOCK_STACK_SIZE + + /* Make sure CAR region is executable */ + mov ecx, 0x120 + rdmsr + or ah, 0x1 + wrmsr + +before_carstage: + post_code(0x2b) + + /* Call romstage.c main function. */ + push .halt_forever /* In case bootblock_car_main returns */ + jmp bootblock_car_main + + /* Never reached */ + +.halt_forever: + post_code(POST_DEAD_CODE) + hlt + jmp .halt_forever + +fixed_mtrr_list: + .word MTRR_FIX_64K_00000 + .word MTRR_FIX_16K_80000 + .word MTRR_FIX_16K_A0000 + .word MTRR_FIX_4K_C0000 + .word MTRR_FIX_4K_C8000 + .word MTRR_FIX_4K_D0000 + .word MTRR_FIX_4K_D8000 + .word MTRR_FIX_4K_E0000 + .word MTRR_FIX_4K_E8000 + .word MTRR_FIX_4K_F0000 + .word MTRR_FIX_4K_F8000 +fixed_mtrr_list_size = . - fixed_mtrr_list diff --git a/src/soc/intel/apollolake/bootblock/early_chipset_config.S b/src/soc/intel/apollolake/bootblock/early_chipset_config.S new file mode 100644 index 0000000..95081d3 --- /dev/null +++ b/src/soc/intel/apollolake/bootblock/early_chipset_config.S @@ -0,0 +1,94 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * (Written by Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +.intel_syntax noprefix +.extern cache_as_ram + +#define post_code(value) \ + mov al, value; \ + outb CONFIG_POST_IO_PORT, al + +.global bootblock_pre_c_entry +bootblock_pre_c_entry: + /* + * eax: BIST value + */ + movd mm2, eax + + post_code(0x20) + +enable_pciex_bar: + mov eax, 0x80000060 /* ROOT PCI device reg60 PCIEX_BAR_*/ + mov dx, 0xcf8 + out dx, eax + mov eax, (CONFIG_MMCONF_BASE_ADDRESS | 1) + mov dx, 0xcfc + out dx, eax + +enable_iosf_bar: + mov ebp, (CONFIG_MMCONF_BASE_ADDRESS | 0x68000) /* IOSF PCI dev */ + mov dword ptr [ebp + 0x10], CONFIG_IOSF_BASE_ADDRESS /* BAR 0 */ + mov word ptr [ebp + 0x04], 0x06 /* PCI command */ + + +/* We need LPC for port80, but it won't work if the pads are not configured */ +configure_lpc_pads: + mov ecx, offset num_lpc_pads /* Number of pads to configure */ + lea esi, lpc_pad_params +init_lpc_pad: + mov edi, [esi + 0x00] /* MMIO addr of pad config registers */ + mov eax, [esi + 0x04] /* Pad CONF0 value */ + mov edx, [esi + 0x08] /* Pad CONF1 value */ + mov [edi + 0x00], eax /* Write CONF0 to config register */ + mov [edi + 0x04], edx /* Write CONF1 to config register */ + add esi, 0x0c + loop init_lpc_pad + + jmp cache_as_ram + +/* FIXME: Find a better way to define these */ + +#define LPC_CLKOUT0 0x118 +#define LPC_CLKOUT1 0x120 +#define LPC_AD0 0x128 +#define LPC_AD1 0x130 +#define LPC_AD2 0x138 +#define LPC_AD3 0x140 +#define LPC_CLKRUN 0x148 +#define LPC_FRAME 0x150 + +#define XLATE_LPC(off) ((0xc0 << 16 ) | (0x500 + (off))) +#define PAD_MMIO_ADDR(poff) CONFIG_IOSF_BASE_ADDRESS + XLATE_LPC(poff) + +lpc_pad_params: + .long PAD_MMIO_ADDR(LPC_CLKOUT0) + .long 0x44000400 + .long 0x0003C000 + .long PAD_MMIO_ADDR(LPC_AD0) + .long 0x44000402 + .long 0x0003F000 + .long PAD_MMIO_ADDR(LPC_AD1) + .long 0x44000402 + .long 0x0003F000 + .long PAD_MMIO_ADDR(LPC_AD2) + .long 0x44000402 + .long 0x0003F000 + .long PAD_MMIO_ADDR(LPC_AD3) + .long 0x44000402 + .long 0x0003F000 + .long PAD_MMIO_ADDR(LPC_FRAME) + .long 0x44000400 + .long 0x0003F000 + .long PAD_MMIO_ADDR(LPC_CLKOUT1) + .long 0x44000400 + .long 0x0003C000 +num_lpc_pads = ( . - lpc_pad_params) / 0xc diff --git a/src/soc/intel/apollolake/include/soc/bootblock.h b/src/soc/intel/apollolake/include/soc/bootblock.h new file mode 100644 index 0000000..f5fab18 --- /dev/null +++ b/src/soc/intel/apollolake/include/soc/bootblock.h @@ -0,0 +1,18 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * (Written by Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef _APOLLOLAKE_BOOTBLOCK_H_ +#define _APOLLOLAKE_BOOTBLOCK_H_ + +void bootblock_car_main(void); + +#endif /* _APOLLOLAKE_BOOTBLOCK_H_ */

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Patch set updated for coreboot: arch/x86: Implement minimal bootblock for C_ENVIRONMENT_BOTOBLOCK
by Alexandru Gagniuc 28 Jan '16

28 Jan '16

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13485 -gerrit commit c21bd6a6dbc79d9c6983f494345259686a26941d Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Tue Jan 26 18:22:43 2016 -0800 arch/x86: Implement minimal bootblock for C_ENVIRONMENT_BOTOBLOCK Some newer x86 systems can boot from non-memory-mapped boot media (e.g. EMMC). The bootblock may be backed by small amounts of SRAM, or other memory, similar to how most ARM chipsets work. In such cases, we may not have enough code space for romstage very early on. This means that CAR setup and early boot media (e.g. SPI, EMMC) drivers need to be implemented within the limited amount memory of storage available. Since the reset vector has to be contained in this early code memory, the bootblock is the best place to implement loading of other stages. Implement a bootblock which does the minimal initialization, up to, and including switch to protected mode. This then transfers control to platform-specific code. No stack is needed, and control is transferred via a "jmp" such that no stack operations are involved. Change-Id: I009b42b9a707cf11a74493bd4d8c189dc09b8ace Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- src/arch/x86/Makefile.inc | 1 + src/arch/x86/bootblock_crt0.S | 55 +++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 56 insertions(+) diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index bc64815..821e7ee 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -112,6 +112,7 @@ $(obj)/arch/x86/id.bootblock.o: $(obj)/build.h ifeq ($(CONFIG_C_ENVIRONMENT_BOOTBLOCK),y) +bootblock-y += bootblock_crt0.S bootblock-y += memlayout.ld ifeq ($(CONFIG_ARCH_BOOTBLOCK_X86_32),y) diff --git a/src/arch/x86/bootblock_crt0.S b/src/arch/x86/bootblock_crt0.S new file mode 100644 index 0000000..926cda0 --- /dev/null +++ b/src/arch/x86/bootblock_crt0.S @@ -0,0 +1,55 @@ +/* + * This is the modern bootblock. It is used by platforms which select + * C_ENVIRONMENT_BOOTBLOCK, and it prepares the system for C environment runtime + * setup. The actual setup is done by hardware-specific code. + * + * It provides a bootflow similar to other architectures, and thus is considered + * to be the modern approach. + * + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#define CR0_MP (1 << 1) +#define CR0_EM (1 << 2) + +#define CR4_OSFXSR (1 << 9) +#define CR4_OSXMMEXCPT (1 << 10) + +/* + * Include the old code for reset vector and protected mode entry. That code has + * withstood the test of time. + */ +#include <arch/x86/prologue.inc> +#include <cpu/x86/16bit/entry16.inc> +#include <cpu/x86/16bit/reset16.inc> +#include <cpu/x86/32bit/entry32.inc> + + +bootblock_protected_mode_entry: + /* Save BIST result */ + movd %eax, %mm0 + /* Save an early timestamp */ + rdtsc + movd %eax, %mm1 + movd %edx, %mm2 + +#if !IS_ENABLED(CONFIG_SSE) +enable_sse: + mov %cr0, %eax + and $~CR0_EM, %ax /* Clear coprocessor emulation CR0.EM */ + or $CR0_MP, %ax /* Set coprocessor monitoring CR0.MP */ + mov %eax, %cr0 + mov %cr4, %eax + or $(CR4_OSFXSR | CR4_OSXMMEXCPT), %ax + mov %eax, %cr4 +#endif /* IS_ENABLED(CONFIG_SSE) */ + + /* We're done. Now it's up to platform-specific code */ + jmp bootblock_pre_c_entry

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Patch set updated for coreboot: cpu/x86/tsc: Compile delay_tsc.c for the bootblock as well
by Alexandru Gagniuc 28 Jan '16

28 Jan '16

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13302 -gerrit commit f0f02db99cef3cfd782125629a772e2ecd7586a7 Author: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> Date: Wed Oct 7 11:06:14 2015 -0700 cpu/x86/tsc: Compile delay_tsc.c for the bootblock as well This is needed in a follow-on patch to enable udelay() handling on apollolake, which is a dependency for the console code. Change-Id: I7da6a060a91b83f3b32c5c5d269c102ce7ae3b8a Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> --- src/cpu/x86/tsc/Makefile.inc | 1 + 1 file changed, 1 insertion(+) diff --git a/src/cpu/x86/tsc/Makefile.inc b/src/cpu/x86/tsc/Makefile.inc index bbebda9..7e2eab2 100644 --- a/src/cpu/x86/tsc/Makefile.inc +++ b/src/cpu/x86/tsc/Makefile.inc @@ -1,3 +1,4 @@ +bootblock-$(CONFIG_UDELAY_TSC) += delay_tsc.c ramstage-$(CONFIG_UDELAY_TSC) += delay_tsc.c romstage-$(CONFIG_TSC_CONSTANT_RATE) += delay_tsc.c verstage-$(CONFIG_TSC_CONSTANT_RATE) += delay_tsc.c

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Patch set updated for coreboot: soc/apollolake: Add tsc_freq_mhz() functionality for udelay()
by Alexandru Gagniuc 28 Jan '16

28 Jan '16

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13303 -gerrit commit 05d53f82521dff182d1e17270ab5a596bd6f3425 Author: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> Date: Tue Oct 6 16:31:34 2015 -0700 soc/apollolake: Add tsc_freq_mhz() functionality for udelay() Change-Id: I2f1147cefe2438992bff45fc0a1e91064217915d Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> --- src/soc/intel/apollolake/Kconfig | 1 + src/soc/intel/apollolake/Makefile.inc | 5 +++++ src/soc/intel/apollolake/include/soc/cpu.h | 20 ++++++++++++++++++++ src/soc/intel/apollolake/tsc_freq.c | 21 +++++++++++++++++++++ 4 files changed, 47 insertions(+) diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index f7ae68e..825a40f 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -32,6 +32,7 @@ config CPU_SPECIFIC_OPTIONS select RELOCATABLE_RAMSTAGE # Build fails if this is not selected select SOC_INTEL_COMMON select UDELAY_TSC + select TSC_CONSTANT_RATE config MMCONF_BASE_ADDRESS hex "PCI MMIO Base Address" diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc index cc3e013..d7d7ebc 100644 --- a/src/soc/intel/apollolake/Makefile.inc +++ b/src/soc/intel/apollolake/Makefile.inc @@ -8,9 +8,14 @@ subdirs-y += ../../../cpu/x86/smm subdirs-y += ../../../cpu/x86/tsc bootblock-y += bootblock/bootblock_car.c +bootblock-y += tsc_freq.c bootblock-y += bootblock/cache_as_ram.S bootblock-y += bootblock/early_chipset_config.S +romstage-y += tsc_freq.c + +ramstage-y += tsc_freq.c + romstage-y += placeholders.c smm-y += placeholders.c ramstage-y += placeholders.c diff --git a/src/soc/intel/apollolake/include/soc/cpu.h b/src/soc/intel/apollolake/include/soc/cpu.h new file mode 100644 index 0000000..d0d6afd --- /dev/null +++ b/src/soc/intel/apollolake/include/soc/cpu.h @@ -0,0 +1,20 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * (Written by Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef _SOC_APOLLOLAKE_CPU_H_ +#define _SOC_APOLLOLAKE_CPU_H_ + +#define MSR_PLATFORM_INFO 0xce + +#define BASE_CLOCK_MHZ 100 + +#endif /* _SOC_APOLLOLAKE_CPU_H_ */ diff --git a/src/soc/intel/apollolake/tsc_freq.c b/src/soc/intel/apollolake/tsc_freq.c new file mode 100644 index 0000000..2e90ef2 --- /dev/null +++ b/src/soc/intel/apollolake/tsc_freq.c @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * (Written by Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include <cpu/x86/msr.h> +#include <cpu/x86/tsc.h> +#include <soc/cpu.h> + +unsigned long tsc_freq_mhz(void) +{ + msr_t msr = rdmsr(MSR_PLATFORM_INFO); + return (BASE_CLOCK_MHZ * ((msr.lo >> 8) & 0xff)); +}

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Patch set updated for coreboot: soc/intel: Add skeleton infrastructure for Apollolake SOC
by Alexandru Gagniuc 28 Jan '16

28 Jan '16

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13297 -gerrit commit 3e6c52d17870f245024b9cba729421776e887d7d Author: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> Date: Tue Oct 6 10:33:49 2015 -0700 soc/intel: Add skeleton infrastructure for Apollolake SOC This is the very very minimum needed to compile the code. Change-Id: I7f9e5f564181071591a4640019f59f91a4c456c6 Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> --- src/soc/intel/apollolake/Kconfig | 39 +++++++++++++++++++++++++++++++++ src/soc/intel/apollolake/Makefile.inc | 14 ++++++++++++ src/soc/intel/apollolake/placeholders.c | 11 ++++++++++ 3 files changed, 64 insertions(+) diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig new file mode 100644 index 0000000..ca38494 --- /dev/null +++ b/src/soc/intel/apollolake/Kconfig @@ -0,0 +1,39 @@ +config SOC_INTEL_APOLLOLAKE + bool + help + Intel Apollolake support + +if SOC_INTEL_APOLLOLAKE + +config CPU_SPECIFIC_OPTIONS + def_bool y + select ARCH_BOOTBLOCK_X86_32 + select ARCH_RAMSTAGE_X86_32 + select ARCH_ROMSTAGE_X86_32 + select ARCH_VERSTAGE_X86_32 + # CPU specific options + select CPU_INTEL_FIRMWARE_INTERFACE_TABLE + select IOAPIC + select SMP + select SSE2 + select SUPPORT_CPU_UCODE_IN_CBFS + # Misc options + select COLLECT_TIMESTAMPS + select HAVE_INTEL_FIRMWARE + select MMCONF_SUPPORT + select MMCONF_SUPPORT_DEFAULT + select PARALLEL_MP + select PCIEXP_ASPM + select PCIEXP_COMMON_CLOCK + select PCIEXP_CLK_PM + select PCIEXP_L1_SUB_STATE + select REG_SCRIPT + select RELOCATABLE_RAMSTAGE # Build fails if this is not selected + select SOC_INTEL_COMMON + select UDELAY_TSC + +config CPU_ADDR_BITS + int + default 36 + +endif diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc new file mode 100644 index 0000000..b37cf8d --- /dev/null +++ b/src/soc/intel/apollolake/Makefile.inc @@ -0,0 +1,14 @@ +ifeq ($(CONFIG_SOC_INTEL_APOLLOLAKE),y) + +subdirs-y += ../../../cpu/intel/microcode +subdirs-y += ../../../cpu/intel/turbo +subdirs-y += ../../../cpu/x86/lapic +subdirs-y += ../../../cpu/x86/mtrr +subdirs-y += ../../../cpu/x86/smm +subdirs-y += ../../../cpu/x86/tsc + +romstage-y += placeholders.c +smm-y += placeholders.c +ramstage-y += placeholders.c + +endif diff --git a/src/soc/intel/apollolake/placeholders.c b/src/soc/intel/apollolake/placeholders.c new file mode 100644 index 0000000..cf0fe36 --- /dev/null +++ b/src/soc/intel/apollolake/placeholders.c @@ -0,0 +1,11 @@ +#include <cbmem.h> +#include <cpu/x86/smm.h> + +void *cbmem_top(void) +{ + return NULL; +} + +void southbridge_smi_set_eos(void) +{ +}

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Patch set updated for coreboot: mainboard/intel: Add skeleton for Apollolake RVP board
by Alexandru Gagniuc 28 Jan '16

28 Jan '16

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13298 -gerrit commit 7004f5b5891672cc1329cc09f1643687a0992e77 Author: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> Date: Tue Oct 6 10:36:20 2015 -0700 mainboard/intel: Add skeleton for Apollolake RVP board Change-Id: I3e47c157c49ad55ff1ba824672ac2630a64a6037 Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> --- src/mainboard/intel/apollolake_rvp/Kconfig | 20 ++++++++++++++++++++ src/mainboard/intel/apollolake_rvp/Kconfig.name | 2 ++ src/mainboard/intel/apollolake_rvp/Makefile.inc | 1 + src/mainboard/intel/apollolake_rvp/devicetree.cb | 8 ++++++++ src/mainboard/intel/apollolake_rvp/romstage.c | 1 + 5 files changed, 32 insertions(+) diff --git a/src/mainboard/intel/apollolake_rvp/Kconfig b/src/mainboard/intel/apollolake_rvp/Kconfig new file mode 100755 index 0000000..2c3e898 --- /dev/null +++ b/src/mainboard/intel/apollolake_rvp/Kconfig @@ -0,0 +1,20 @@ +if BOARD_INTEL_APOLLOLAKE_RVP2 + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select SOC_INTEL_APOLLOLAKE + select BOARD_ROMSIZE_KB_8192 + +config MAINBOARD_DIR + string + default intel/apollolake_rvp + +config MAINBOARD_PART_NUMBER + string + default "Apollolake RVP2" + +config MAINBOARD_VENDOR + string + default "Intel" + +endif # BOARD_INTEL_APOLLOLAKE_RVP2 diff --git a/src/mainboard/intel/apollolake_rvp/Kconfig.name b/src/mainboard/intel/apollolake_rvp/Kconfig.name new file mode 100644 index 0000000..56d5b4b --- /dev/null +++ b/src/mainboard/intel/apollolake_rvp/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_INTEL_APOLLOLAKE_RVP2 + bool "Apollolake LPDDR3 RVP2" diff --git a/src/mainboard/intel/apollolake_rvp/Makefile.inc b/src/mainboard/intel/apollolake_rvp/Makefile.inc new file mode 100755 index 0000000..a48936e --- /dev/null +++ b/src/mainboard/intel/apollolake_rvp/Makefile.inc @@ -0,0 +1 @@ +# Nothing yet here diff --git a/src/mainboard/intel/apollolake_rvp/devicetree.cb b/src/mainboard/intel/apollolake_rvp/devicetree.cb new file mode 100755 index 0000000..741d88e --- /dev/null +++ b/src/mainboard/intel/apollolake_rvp/devicetree.cb @@ -0,0 +1,8 @@ +chip soc/intel/apollolake + + device cpu_cluster 0 on + device lapic 0 on end + end + device domain 0 on + end +end diff --git a/src/mainboard/intel/apollolake_rvp/romstage.c b/src/mainboard/intel/apollolake_rvp/romstage.c new file mode 100644 index 0000000..c5d3ce1 --- /dev/null +++ b/src/mainboard/intel/apollolake_rvp/romstage.c @@ -0,0 +1 @@ +/* Nothing here yet, but this file is needed by the buildsystem */

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Patch set updated for coreboot: arch/x86/Makefile.inc: Re-enable -Wa, --divide assembler flag
by Alexandru Gagniuc 28 Jan '16

28 Jan '16

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13299 -gerrit commit f5123a94cef39b1c3e6fde387ab71e79eeaa7724 Author: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> Date: Tue Oct 6 14:41:20 2015 -0700 arch/x86/Makefile.inc: Re-enable -Wa,--divide assembler flag In the follow-on patches, we use constant division to calculate the number of elements in an assembly structure. Since the size of one element is not a power of two for all structures, we can't bit shift. This allows us to do the computation at assembly time rather than runtime. Change-Id: Ic5693f39dee8daf759bfc16c79ac3c7ddb4de465 Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> --- src/arch/x86/Makefile.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 821e7ee..616bc5c 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -84,7 +84,7 @@ define early_x86_stage $(1)-y += memlayout.ld # The '.' include path is needed for the generated assembly.inc file. -$(1)-S-ccopts += -I. +$(1)-S-ccopts += -I. -Wa,--divide $$(objcbfs)/$(1).debug: $$$$($(1)-libs) $$$$($(1)-objs) @printf " LINK $$(subst $$(obj)/,,$$(@))\n"

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Patch set updated for coreboot: soc/apollolake: Add minimal accessors for sideband bus (IOSF)
by Alexandru Gagniuc 28 Jan '16

28 Jan '16

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13304 -gerrit commit 9f507da022122dd2ee9597fcd8e46e4d74c898ec Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Mon Oct 5 13:45:22 2015 -0700 soc/apollolake: Add minimal accessors for sideband bus (IOSF) Some configuration registers for the UART are placed behind the sideband bus. Change-Id: I84a620dbd0cf4b8f3fec119836d1c8f75c7f200a Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> --- src/soc/intel/apollolake/include/soc/iosf.h | 30 +++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/src/soc/intel/apollolake/include/soc/iosf.h b/src/soc/intel/apollolake/include/soc/iosf.h new file mode 100644 index 0000000..c9f578c --- /dev/null +++ b/src/soc/intel/apollolake/include/soc/iosf.h @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * (Written by Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef _SOC_APOLLOLAKE_IOSF_H_ +#define _SOC_APOLLOLAKE_IOSF_H_ + +#include <arch/io.h> + +inline static void iosf_write(uint8_t port, uint16_t reg, uint32_t val) +{ + uintptr_t base = CONFIG_IOSF_BASE_ADDRESS | (port << 16) | (reg & ~3); + write32((void *)base, val); +} + +inline static uint32_t iosf_read(uint8_t port, uint16_t reg) +{ + uintptr_t base = CONFIG_IOSF_BASE_ADDRESS | (port << 16) | (reg & ~3); + return read32((void *)base); +} + +#endif /* _SOC_APOLLOLAKE_IOSF_H_ */

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Patch set updated for coreboot: mainboard/intel: Add dummy Apollolake RVP1 support
by Alexandru Gagniuc 28 Jan '16

28 Jan '16

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13305 -gerrit commit a3302da1d3a7815ea3dd986112ba8332015cbaf6 Author: Andrey Petrov <andrey.petrov(a)intel.com> Date: Thu Oct 8 12:32:50 2015 -0700 mainboard/intel: Add dummy Apollolake RVP1 support Change-Id: Ie1ab158da9a1d9ba892c9b7119e67e3138eeaf2f Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> --- src/mainboard/intel/apollolake_rvp/Kconfig | 6 +++--- src/mainboard/intel/apollolake_rvp/Kconfig.name | 3 +++ 2 files changed, 6 insertions(+), 3 deletions(-) diff --git a/src/mainboard/intel/apollolake_rvp/Kconfig b/src/mainboard/intel/apollolake_rvp/Kconfig index 2c3e898..152e092 100755 --- a/src/mainboard/intel/apollolake_rvp/Kconfig +++ b/src/mainboard/intel/apollolake_rvp/Kconfig @@ -1,4 +1,4 @@ -if BOARD_INTEL_APOLLOLAKE_RVP2 +if BOARD_INTEL_APOLLOLAKE_RVP1 || BOARD_INTEL_APOLLOLAKE_RVP2 config BOARD_SPECIFIC_OPTIONS def_bool y @@ -11,10 +11,10 @@ config MAINBOARD_DIR config MAINBOARD_PART_NUMBER string - default "Apollolake RVP2" + default "Apollolake RVP" config MAINBOARD_VENDOR string default "Intel" -endif # BOARD_INTEL_APOLLOLAKE_RVP2 +endif # BOARD_INTEL_APOLLOLAKE_RVP1 || BOARD_INTEL_APOLLOLAKE_RVP2 diff --git a/src/mainboard/intel/apollolake_rvp/Kconfig.name b/src/mainboard/intel/apollolake_rvp/Kconfig.name index 56d5b4b..c0cbd5e 100644 --- a/src/mainboard/intel/apollolake_rvp/Kconfig.name +++ b/src/mainboard/intel/apollolake_rvp/Kconfig.name @@ -1,2 +1,5 @@ +config BOARD_INTEL_APOLLOLAKE_RVP1 + bool "Apollolake DDR3 RVP1" + config BOARD_INTEL_APOLLOLAKE_RVP2 bool "Apollolake LPDDR3 RVP2"

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Patch merged into coreboot/master: src/: give scripts a .sh extension for easy identification
by gerrit＠coreboot.org 28 Jan '16

28 Jan '16

the following patch was just integrated into master: commit 43f16f8dd82e79d15a7bd067e45b0356cd5b3dd6 Author: Martin Roth <martinroth(a)google.com> Date: Mon Jan 25 15:02:32 2016 -0700 src/: give scripts a .sh extension for easy identification Just rename the two scripts that are in the src/ tree to give them a .sh extension. Since we generally expect files in the src directory to be source files, this allows to identify these as scripts easily. Change-Id: I0ab20a083880370164488d37a752ba2d5a192fdc Signed-off-by: Martin Roth <martinroth(a)google.com> Reviewed-on: https://review.coreboot.org/13432 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See https://review.coreboot.org/13432 for details. -gerrit

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