Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13439
-gerrit
commit ef34df750ffa1a21c787e430d6264b7393a0fe4e
Author: Lee Leahy <lpleahyjr(a)gmail.com>
Date: Fri Jan 1 18:08:48 2016 -0800
soc/intel/quark: Add minimal Quark SoC files
Add the files for minimal Quark SoC support including HTML
documentation:
* Declare pei_data structure
* Declare sleep states and chipset_power_state structure
* Specify top of memory
* Empty FspUpdVpd.h file
TEST=None
Change-Id: If741f84904394780e1f29bd6ddbd81514c3e21c9
Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com>
---
src/soc/intel/quark/Kconfig | 30 ++++
src/soc/intel/quark/Makefile.inc | 31 ++++
src/soc/intel/quark/include/soc/pei_wrapper.h | 60 ++++++++
src/soc/intel/quark/include/soc/pm.h | 33 +++++
src/soc/intel/quark/memmap.c | 22 +++
src/soc/intel/quark/quark.html | 98 +++++++++++++
src/vendorcode/intel/fsp/fsp1_1/quark/FspUpdVpd.h | 171 ++++++++++++++++++++++
7 files changed, 445 insertions(+)
diff --git a/src/soc/intel/quark/Kconfig b/src/soc/intel/quark/Kconfig
new file mode 100644
index 0000000..4bc3ebc
--- /dev/null
+++ b/src/soc/intel/quark/Kconfig
@@ -0,0 +1,30 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2015-2016 Intel Corp.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+
+config SOC_INTEL_QUARK
+ bool
+ help
+ Intel Quark support
+
+if SOC_INTEL_QUARK
+
+config CPU_SPECIFIC_OPTIONS
+ def_bool y
+ select ARCH_BOOTBLOCK_X86_32
+ select ARCH_RAMSTAGE_X86_32
+ select ARCH_ROMSTAGE_X86_32
+ select ARCH_VERSTAGE_X86_32
+
+endif # SOC_INTEL_QUARK
diff --git a/src/soc/intel/quark/Makefile.inc b/src/soc/intel/quark/Makefile.inc
new file mode 100644
index 0000000..39d45fa
--- /dev/null
+++ b/src/soc/intel/quark/Makefile.inc
@@ -0,0 +1,31 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2015-2016 Intel Corporation.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+
+ifeq ($(CONFIG_SOC_INTEL_QUARK),y)
+
+subdirs-y += ../../../cpu/x86/tsc
+
+romstage-y += memmap.c
+
+ramstage-y += memmap.c
+
+CPPFLAGS_common += -I$(src)/soc/intel/quark/include
+
+# Currently used for microcode path.
+CPPFLAGS_common += -I3rdparty/blobs/mainboard/$(CONFIG_MAINBOARD_DIR)
+
+ROMCCFLAGS := -mcpu=p4 -fno-simplify-phi -O2
+
+endif # CONFIG_SOC_INTEL_QUARK
diff --git a/src/soc/intel/quark/include/soc/pei_wrapper.h b/src/soc/intel/quark/include/soc/pei_wrapper.h
new file mode 100644
index 0000000..5328e76
--- /dev/null
+++ b/src/soc/intel/quark/include/soc/pei_wrapper.h
@@ -0,0 +1,60 @@
+/*
+ * UEFI PEI wrapper
+ *
+ * Copyright (C) 2014 Google Inc.
+ * Copyright (C) 2015-2016 Intel Corporation.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Google Inc. nor the
+ * names of its contributors may be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL GOOGLE INC BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _PEI_WRAPPER_H_
+#define _PEI_WRAPPER_H_
+
+#include <types.h>
+
+#define PEI_VERSION 22
+
+#define ABI_X86 __attribute__((regparm(0)))
+
+typedef void ABI_X86(*tx_byte_func)(unsigned char byte);
+
+struct pei_data {
+ uint32_t pei_version;
+
+ int boot_mode;
+
+ /* Data read from flash and passed into MRC */
+ const void *saved_data;
+ int saved_data_size;
+
+ /* Disable use of saved data (can be set by mainboard) */
+ int disable_saved_data;
+
+ /* Data from MRC that should be saved to flash */
+ void *data_to_save;
+ int data_to_save_size;
+} __attribute__((packed));
+
+typedef struct pei_data PEI_DATA;
+
+#endif /* _PEI_WRAPPER_H_ */
diff --git a/src/soc/intel/quark/include/soc/pm.h b/src/soc/intel/quark/include/soc/pm.h
new file mode 100644
index 0000000..f9ae027
--- /dev/null
+++ b/src/soc/intel/quark/include/soc/pm.h
@@ -0,0 +1,33 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ * Copyright (C) 2015-2016 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _SOC_PM_H_
+#define _SOC_PM_H_
+
+#include <stdint.h>
+
+/* Generic sleep state types */
+#define SLEEP_STATE_S0 0
+#define SLEEP_STATE_S3 3
+#define SLEEP_STATE_S5 5
+
+struct chipset_power_state {
+ uint32_t prev_sleep_state;
+} __attribute__ ((packed));
+
+struct chipset_power_state *fill_power_state(void);
+
+#endif
diff --git a/src/soc/intel/quark/memmap.c b/src/soc/intel/quark/memmap.c
new file mode 100644
index 0000000..975128c
--- /dev/null
+++ b/src/soc/intel/quark/memmap.c
@@ -0,0 +1,22 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ * Copyright (C) 2015-2016 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <cbmem.h>
+
+void *cbmem_top(void)
+{
+ return (void *)0x1c000000;
+}
diff --git a/src/soc/intel/quark/quark.html b/src/soc/intel/quark/quark.html
new file mode 100644
index 0000000..4b4cd0f
--- /dev/null
+++ b/src/soc/intel/quark/quark.html
@@ -0,0 +1,98 @@
+<!DOCTYPE html>
+<html>
+ <head>
+ <title>Quark™ SoC</title>
+ </head>
+ <body>
+
+<h1>Intel® Quark™ SoC</h1>
+<table>
+ <tr>
+ <td><a target="_blank" href="http://www.intel.com/content/dam/www/public/us/en/images/embedded/16x9/edc-…"><img alt="Quark Block Diagram" src="http://www.intel.com/content/dam/www/public/us/en/images/embedded/16x9/edc-…" width=500></a></td>
+ <td>
+<table>
+ <tr bgcolor="#ffc0c0">
+ <td>
+Warning: Use of the Intel® Quark™ SoC code requires modification of the util/xcompile/xcompile file to change the machine
+architecture from i686 to i586 because the Quark™ processor does not support the instructions
+introduced with the Pentium™ 6 architecture.
+<ol>
+ <li>Edit the file util/xcompile/xcompile</li>
+ <li>Search for
+<a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=util/xcompile/xco…">-march</a></li>
+ <li>Replace i686 with i586</li>
+ <li>Save the result</li>
+</ol>
+Without this change the Quark™ processor will halt when it executes one of the
+instructions introduced with the Pentium™ 6 architecture.
+ </td>
+ </tr>
+</table>
+<p>
+ The Quark™ SoC code was developed using the
+ <a target="_blank" href="../../../mainboard/intel/galileo/galileo.html">Galileo Gen 2</a>
+ board:
+</p>
+<ul>
+ <li><a target="_blank" href="../../../../Documentation/x86Development.html">Overall</a> development</li>
+ <li><a target="_blank" href="../soc/soc.html">SoC</a> support</li>
+ <li><a target="_blank" href="../../../drivers/intel/fsp1_1/fsp1_1.html">FSP 1.1</a> integration</li>
+ <li><a target="_blank" href="../../../mainboard/intel/board.html">Board</a> support</li>
+</ul>
+ </td>
+ </tr>
+</table>
+
+
+
+<hr>
+<h1>Quark™ Documentation</h1>
+<ul>
+ <li><a target="_blank" href="http://www.intel.com/content/dam/www/public/us/en/images/embedded/16x9/edc-…">Block Diagram</a></li>
+ <li>Intel® 64 and IA-32 Architectures <a target="_blank" href="http://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-3…">Software Developer Manual</a></li>
+ <li><a target="_blank" href="http://www.intel.com/content/www/us/en/embedded/products/quark/specificatio…">Specifications</a>:
+ <ul>
+ <li><a target="_blank" href="http://ark.intel.com/products/79084/Intel-Quark-SoC-X1000-16K-Cache-400-MHz">X1000</a>
+ - <a target="_blank" href="http://www.intel.com/content/www/us/en/search.html?keyword=X1000">Documentation</a>:
+ <ul>
+ <li><a target="_blank" href="http://www.intel.com/content/dam/www/public/us/en/documents/datasheets/quar…">Datasheet</a></li>
+ <li><a target="_blank" href="http://www.intel.com/content/dam/support/us/en/documents/processors/quark/s…">Developer's Manual</a></li>
+ <li><a target="_blank" href="http://www.intel.com/content/dam/www/public/us/en/documents/product-briefs/…">Product Brief</a></li>
+ </ul>
+ </li>
+ </ul>
+ </li>
+</ul>
+
+
+
+<hr>
+<h1>Quark™ FSP</h1>
+<ul>
+ <li>Intel® Firmware Support Package External Architecture Specification <a target="_blank" href="http://www.intel.com/content/dam/www/public/us/en/documents/technical-speci…">V1.1</a></li>
+ <li>Intel® Quark™ SoC X1000 <a target="_blank" href="http://www.intel.com/content/dam/www/public/us/en/documents/guides/quark-x1…">UEFI Firmware Writer's Guide</a></li>
+ <li>EDK2 Sources:
+ <ul>
+ <li>EDK2: git clone <a target="_blank" href="https://github.com/tianocore/edk2.git">https://github.com/tianocore/edk2.git</a></li>
+ <li>EDK2-FatPkg: git clone <a target="_blank" href="https://github.com/tianocore/edk2-FatPkg.git">https://github.com/tianocore/edk2-FatPkg.git</a> FatPkg</li>
+ <li>EDK2-non-osi: git clone <a target="_blank" href="https://github.com/tianocore/edk2-non-osi.git">https://github.com/tianocore/edk2-non-osi.git</a></li>
+ <li>Win32 BaseTools: git clone <a target="_blank" href="https://github.com/tianocore/edk2-BaseTools-win32.git">https://github.com/tianocore/edk2-BaseTools-win32.git</a></li>
+ </ul>
+ </li>
+ <li>Win32 Build Instructions:
+<pre><code>set WORKSPACE=%CD%
+set PACKAGES_PATH=%WORKSPACE%\edk2;%WORKSPACE%\FatPkg;%WORKSPACE%\edk2-non-osi
+set EDK_TOOLS_BIN=%WORKSPACE%\edk2-BaseTools-win32
+cd edk2
+edksetup.bat
+build -p QuarkPlatformPkg/Quark.dsc -a IA32 -t VS2012x86 -b DEBUG -DDEBUG_PROPERTY_MASK=0x27 -DDEBUG_PRINT_ERROR_LEVEL=0x80000042
+</code></pre>
+ </li>
+</ul>
+
+
+
+<hr>
+<p>Modified: 27 January 2016</p>
+ </body>
+</html>
\ No newline at end of file
diff --git a/src/vendorcode/intel/fsp/fsp1_1/quark/FspUpdVpd.h b/src/vendorcode/intel/fsp/fsp1_1/quark/FspUpdVpd.h
new file mode 100644
index 0000000..2a11b20
--- /dev/null
+++ b/src/vendorcode/intel/fsp/fsp1_1/quark/FspUpdVpd.h
@@ -0,0 +1,171 @@
+/** @file
+
+Copyright (c) 2015-2016, Intel Corporation. All rights reserved.<BR>
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+* Redistributions of source code must retain the above copyright notice, this
+ list of conditions and the following disclaimer.
+* Redistributions in binary form must reproduce the above copyright notice, this
+ list of conditions and the following disclaimer in the documentation and/or
+ other materials provided with the distribution.
+* Neither the name of Intel Corporation nor the names of its contributors may
+ be used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ THE POSSIBILITY OF SUCH DAMAGE.
+
+ This file is automatically generated. Please do NOT modify !!!
+
+**/
+
+#ifndef __FSPUPDVPD_H__
+#define __FSPUPDVPD_H__
+
+#pragma pack(push, 1)
+
+#define MAX_CHANNELS_NUM 2
+#define MAX_DIMMS_NUM 2
+
+typedef struct {
+ UINT8 DimmId;
+ UINT32 SizeInMb;
+ UINT16 MfgId;
+ UINT8 ModulePartNum[20];/* Module part number for DDR3 is 18 bytes however for DRR4 20 bytes as per JEDEC Spec, so reserving 20 bytes */
+} DIMM_INFO;
+
+typedef struct {
+ UINT8 ChannelId;
+ UINT8 DimmCount;
+ DIMM_INFO DimmInfo[MAX_DIMMS_NUM];
+} CHANNEL_INFO;
+
+typedef struct {
+ UINT8 Revision;
+ UINT16 DataWidth;
+ /** As defined in SMBIOS 3.0 spec
+ Section 7.18.2 and Table 75
+ **/
+ UINT8 MemoryType;
+ UINT16 MemoryFrequencyInMHz;
+ /** As defined in SMBIOS 3.0 spec
+ Section 7.17.3 and Table 72
+ **/
+ UINT8 ErrorCorrectionType;
+ UINT8 ChannelCount;
+ CHANNEL_INFO ChannelInfo[MAX_CHANNELS_NUM];
+} FSP_SMBIOS_MEMORY_INFO;
+
+/** UPD data structure for FspMemoryInitApi
+**/
+typedef struct {
+
+/** Offset 0x0020
+**/
+ UINT64 Signature;
+
+/** Offset 0x0028 - Revision
+ Revision version of the MemoryInitUpd Region
+**/
+ UINT8 Revision;
+} MEMORY_INIT_UPD;
+
+/** UPD data structure for FspSiliconInitApi
+**/
+typedef struct {
+
+/** Offset 0x0200
+**/
+ UINT64 Signature;
+
+/** Offset 0x0208 - Revision
+ Revision version of the SiliconInitUpd Region
+**/
+ UINT8 Revision;
+} SILICON_INIT_UPD;
+
+#define FSP_UPD_SIGNATURE 0x244450554B525124 /* '$QRKUPD$' */
+#define FSP_MEMORY_INIT_UPD_SIGNATURE 0x244450554D454D24 /* '$MEMUPD$' */
+#define FSP_SILICON_INIT_UPD_SIGNATURE 0x244450555F495324 /* '$SI_UPD$' */
+
+/** UPD data structure. The UPD_DATA_REGION may contain some reserved or unused fields in the data structure. These fields are required to use the default values provided in the FSP binary. Intel always recommends copying the whole UPD_DATA_REGION from the flash to a local structure in the stack before overriding any field.
+**/
+typedef struct {
+
+/** Offset 0x0000
+**/
+ UINT64 Signature;
+
+/** Offset 0x0008 - This field is not an option and is a Revision of the UPD_DATA_REGION. It can be used by the boot loader to validate the UPD region. If the value in this field is changed for an FSP release, the boot loader should not assume the same layout for the UPD_DATA_REGION data structure. Instead it should use the new FspUpdVpd.h from the FSP release package.
+ Size of SMRAM memory reserved. 0x400000 for Release build and 0x1000000 for Debug build
+**/
+ UINT8 Revision;
+
+/** Offset 0x0009
+**/
+ UINT8 ReservedUpd0[7];
+
+/** Offset 0x0010 - MemoryInitUpdOffset
+ This field contains the offset of the MemoryInitUpd structure relative to UPD_DATA_REGION
+**/
+ UINT32 MemoryInitUpdOffset;
+
+/** Offset 0x0014 - SiliconInitUpdOffset
+ This field contains the offset of the SiliconInitUpd structure relative to UPD_DATA_REGION
+**/
+ UINT32 SiliconInitUpdOffset;
+
+/** Offset 0x0018
+**/
+ UINT64 ReservedUpd1;
+
+/** Offset 0x0020
+**/
+ MEMORY_INIT_UPD MemoryInitUpd;
+
+/** Offset 0x0200
+**/
+ SILICON_INIT_UPD SiliconInitUpd;
+
+/** Offset 0x03FA - RegionTerminator
+ This field is not an option and is a termination field at the end of the data structure. This field is will have a value 0x55AA indicating the end of UPD data.The boot loader should never override this field.
+**/
+ UINT16 RegionTerminator;
+} UPD_DATA_REGION;
+
+#define FSP_IMAGE_ID 0x305053462D4B5551 /* 'QUK-FSP0' */
+#define FSP_IMAGE_REV 0x00000000 /* 0.0 */
+
+/** VPD data structure
+**/
+typedef struct {
+
+/** Offset 0x0000
+**/
+ UINT64 PcdVpdRegionSign;
+
+/** Offset 0x0008 - PcdImageRevision
+ This field is not an option and is a revision ID for the FSP release. It can be used by the boot loader to validate the VPD/UPD region. If the value in this field is changed for an FSP release, the boot loader should not assume the same layout for the UPD_DATA_REGION/VPD_DATA_REGION data structure. Instead it should use the new FspUpdVpd.h from the FSP release package. This should match the ImageRevision in FSP_INFO_HEADER.
+**/
+ UINT32 PcdImageRevision;
+
+/** Offset 0x000C - PcdUpdRegionOffset
+ This field is not an option and contains the offset of the UPD data region within the FSP release image. The boot loader can use it to find the location of UPD_DATA_REGION.
+**/
+ UINT32 PcdUpdRegionOffset;
+} VPD_DATA_REGION;
+
+#pragma pack(pop)
+
+#endif
Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13443
-gerrit
commit 5fb65cb8978496a3e598c403c67ac89dbfce7ca2
Author: Lee Leahy <leroy.p.leahy(a)intel.com>
Date: Tue Jan 26 15:53:35 2016 -0800
soc/intel/quark: Add TempRamInit support
Successfully invoke TempRamInit from the FSP binary:
* Don't relocate the FSP binary image
* Move the FSP binary into ESRAM
* Test by setting the following Kconfig values one at a time:
* CONFIG_ENABLE_DEBUG_LED_FINDFSP
* CONFIG_ENABLE_DEBUG_LED_TEMPRAMINIT
TEST=Build and run on Galileo Gen2
Change-Id: I1e2e413a8573f750c611b0f9df101b2c869a789e
Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com>
---
src/soc/intel/quark/Kconfig | 33 ++++++
src/soc/intel/quark/memmap.c | 7 ++
src/soc/intel/quark/romstage/Makefile.inc | 1 +
src/soc/intel/quark/romstage/cache_as_ram.inc | 165 ++++++++++++++++++++++++++
src/soc/intel/quark/romstage/esram_init.inc | 20 +++-
5 files changed, 224 insertions(+), 2 deletions(-)
diff --git a/src/soc/intel/quark/Kconfig b/src/soc/intel/quark/Kconfig
index 2509e06..fae29cc 100644
--- a/src/soc/intel/quark/Kconfig
+++ b/src/soc/intel/quark/Kconfig
@@ -38,6 +38,39 @@ config CBFS_SIZE
This option specifies the maximum size of the CBFS portion in the
firmware image.
+config ENABLE_DEBUG_LED
+ bool
+ default n
+ help
+ Enable the use of the SD LED for early debugging before serial output is
+ available. Setting this LED indicates that control has reached the desired
+ check point. The assembly code below may be inserted into cache_as_ram.inc:
+ movl $SD_HOST_CTRL, %ebx
+ movb 0(%ebx), %al
+ orb $1, %al
+ movb %al, 0(%ebx)
+
+config ENABLE_DEBUG_LED_ESRAM
+ bool "SD LED indicates ESRAM initialized"
+ default n
+ select ENABLE_DEBUG_LED
+ help
+ Indicate that ESRAM has been successfully initialized.
+
+config ENABLE_DEBUG_LED_FINDFSP
+ bool "SD LED indicates fsp.bin file was found"
+ default n
+ select ENABLE_DEBUG_LED
+ help
+ Indicate that fsp.bin was found.
+
+config ENABLE_DEBUG_LED_TEMPRAMINIT
+ bool "SD LED indicates TempRamInit was successful"
+ default n
+ select ENABLE_DEBUG_LED
+ help
+ Indicate that TempRamInit was successful.
+
config HAVE_RMU_FILE
bool
default n
diff --git a/src/soc/intel/quark/memmap.c b/src/soc/intel/quark/memmap.c
index 975128c..4f47afa 100644
--- a/src/soc/intel/quark/memmap.c
+++ b/src/soc/intel/quark/memmap.c
@@ -15,6 +15,13 @@
*/
#include <cbmem.h>
+#include <fsp/memmap.h>
+
+size_t mmap_region_granluarity(void)
+{
+ /* Align to 8 MiB by default */
+ return 8 << 20;
+}
void *cbmem_top(void)
{
diff --git a/src/soc/intel/quark/romstage/Makefile.inc b/src/soc/intel/quark/romstage/Makefile.inc
index a0be5d5..cb17d3d 100644
--- a/src/soc/intel/quark/romstage/Makefile.inc
+++ b/src/soc/intel/quark/romstage/Makefile.inc
@@ -14,3 +14,4 @@
#
cpu_incs-y += $(src)/soc/intel/quark/romstage/esram_init.inc
+cpu_incs-y += $(src)/soc/intel/quark/romstage/cache_as_ram.inc
diff --git a/src/soc/intel/quark/romstage/cache_as_ram.inc b/src/soc/intel/quark/romstage/cache_as_ram.inc
new file mode 100644
index 0000000..80ac64d
--- /dev/null
+++ b/src/soc/intel/quark/romstage/cache_as_ram.inc
@@ -0,0 +1,165 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2000,2007 Ronald G. Minnich <rminnich(a)gmail.com>
+ * Copyright (C) 2007-2008 coresystems GmbH
+ * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC.
+ * Copyright (C) 2015-2016 Intel Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/*
+ * Replacement for cache_as_ram.inc when using the FSP binary. This code
+ * locates the FSP binary, initializes the cache as RAM and performs the
+ * first stage of initialization. Next this code switches the stack from
+ * the cache to RAM and then disables the cache as RAM. Finally this code
+ * performs the final stage of initialization.
+ */
+
+#include <rules.h>
+
+ /*
+ * eax: BIST value
+ */
+
+ mov %eax, %edi
+
+cache_as_ram:
+ post_code(0x20)
+
+ /*
+ * edi: BIST value
+ */
+
+ /*
+ * Find the FSP binary in cbfs.
+ * Make a fake stack that has the return value back to this code.
+ */
+ lea fake_fsp_stack, %esp
+ jmp find_fsp
+
+find_fsp_ret:
+ /* Save the FSP location */
+ mov %eax, %ebp
+
+ /*
+ * Only when a valid FSP binary is found at CONFIG_FSP_LOC is
+ * the returned FSP_INFO_HEADER structure address above the base
+ * address of FSP binary specified by the CONFIG_FSP_LOC value.
+ * All of the error values are in the 0x8xxxxxxx range which are
+ * below the CONFIG_FSP_LOC value.
+ */
+ cmp $CONFIG_FSP_SRAM_LOC, %eax
+ jbe halt1
+
+ post_code(POST_FSP_TEMP_RAM_INIT)
+
+#if IS_ENABLED(CONFIG_ENABLE_DEBUG_LED_FINDFSP)
+ movl $SD_HOST_CTRL, %ebx
+ movb 0(%ebx), %al
+ orb $1, %al
+ movb %al, 0(%ebx)
+#endif /* CONFIG_ENABLE_DEBUG_LED_FINDFSP */
+
+ /* Calculate entry into FSP */
+ mov 0x30(%ebp), %eax /* Load TempRamInitEntry */
+ add 0x1c(%ebp), %eax /* add in the offset for FSP */
+
+ /*
+ * Pass early init variables on a fake stack (no memory yet)
+ * as well as the return location
+ */
+ lea CAR_init_stack, %esp
+
+ /*
+ * BIST value is zero
+ * eax: TempRamInitApi address
+ * ebp: FSP_INFO_HEADER address
+ * edi: BIST value
+ * esi: Not used
+ */
+
+ /* call FSP binary to setup temporary stack */
+ jmp *%eax
+
+CAR_init_done:
+ addl $4, %esp
+
+ /*
+ * ebp: FSP_INFO_HEADER address
+ * ecx: Temp RAM base
+ * edx: Temp RAM top
+ * edi: BIST value
+ */
+
+ cmp $0, %eax
+ jne halt2
+
+#if IS_ENABLED(CONFIG_ENABLE_DEBUG_LED_TEMPRAMINIT)
+ movl %edx, %esi
+ movl $SD_HOST_CTRL, %ebx
+ movb 0(%ebx), %al
+ orb $1, %al
+ movb %al, 0(%ebx)
+ movl %esi, %edx
+#endif /* CONFIG_ENABLE_DEBUG_LED_TEMPRAMINIT */
+
+ clrl %eax
+ jmp halt2
+
+halt1:
+ /*
+ * Failures for postcode 0xBA - failed in fsp_fih_early_find()
+ *
+ * Values are:
+ * 0x01 - FV signature, "_FVH" not present
+ * 0x02 - FFS GUID not present
+ * 0x03 - FSP INFO Header not found
+ * 0x04 - ImageBase does not equal CONFIG_FSP_LOC - Is the FSP rebased to
+ * a different location, or does it need to be?
+ * 0x05 - FSP INFO Header signature "FSPH" not found
+ * 0x06 - FSP Image ID is not the expected ID.
+ */
+ movb $0xBA, %ah
+ jmp .Lhlt
+
+halt2:
+ /*
+ * Failures for postcode 0xBB - failed in the FSP:
+ *
+ * 0x00 - FSP_SUCCESS: Temp RAM was initialized successfully.
+ * 0x02 - FSP_INVALID_PARAMETER: Input parameters are invalid.
+ * 0x03 - FSP_UNSUPPORTED: The FSP calling conditions were not met.
+ * 0x07 - FSP_DEVICE_ERROR: Temp RAM initialization failed
+ * 0x0E - FSP_NOT_FOUND: No valid microcode was found in the microcode region.
+ * 0x14 - FSP_ALREADY_STARTED: Temp RAM initialization has been invoked
+ */
+ movb $0xBB, %ah
+ jmp .Lhlt
+
+/*
+ * esp is set to this location so that the call into and return from the FSP
+ * in find_fsp will work.
+ */
+ .align 4
+fake_fsp_stack:
+ .long find_fsp_ret
+ .long CONFIG_FSP_SRAM_LOC /* FSP base address */
+
+CAR_init_params:
+ .long CONFIG_CPU_MICROCODE_CBFS_LOC /* Microcode Location */
+ .long CONFIG_CPU_MICROCODE_CBFS_LEN /* Microcode Length */
+ .long 0xFFFFFFFF - CONFIG_ROM_SIZE + 1 /* Firmware Location */
+ .long CONFIG_ROM_SIZE /* Total Firmware Length */
+
+CAR_init_stack:
+ .long CAR_init_done
+ .long CAR_init_params
diff --git a/src/soc/intel/quark/romstage/esram_init.inc b/src/soc/intel/quark/romstage/esram_init.inc
index 065dd2d..23c2ff1 100644
--- a/src/soc/intel/quark/romstage/esram_init.inc
+++ b/src/soc/intel/quark/romstage/esram_init.inc
@@ -514,6 +514,20 @@ stackless_PCIConfig_Read:
#----------------------------------------------------------------------------
esram_init_done:
+ #
+ # Copy FSP image to SRAM and call it.
+ #
+ #TODO - FSP location/size could be got in a routine.
+ cld
+ movl $(0x00040000), %ecx # 256K DWORDs = 64K
+ shrl $2, %ecx
+ movl $CONFIG_FSP_LOC, %esi # The source address.
+ movl $CONFIG_FSP_SRAM_LOC, %edi # The destination address in QUARK_ESRAM_MEM_BASE_ADDRESS.
+ rep movsl
+
+#if IS_ENABLED(CONFIG_ENABLE_DEBUG_LED)
+sd_led:
+ movl %eax, %ecx
.equ SD_PFA, (0x14 << 11) # B0:D20:F0 - SDIO controller
.equ SD_CFG_BASE, (PCI_CFG | SD_PFA) # SD controller base in PCI config space
@@ -555,10 +569,12 @@ L43:
jmp stackless_PCIConfig_Read
L44:
+#if IS_ENABLED(CONFIG_ENABLE_DEBUG_LED_ESRAM)
movl $SD_HOST_CTRL, %ebx
movb 0(%ebx), %al
orb $1, %al
movb %al, 0(%ebx)
+#endif /* CONFIG_ENABLE_DEBUG_LED_ESRAM */
- movl $0, %eax
- jmp .Lhlt
+ movl %ecx, %eax
+#endif /* CONFIG_ENABLE_DEBUG_LED */
Damien Zammit (damien(a)zamaudio.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13455
-gerrit
commit 0557cb057cf277b30284e32578d7b38af87337f4
Author: Damien Zammit <damien(a)zamaudio.com>
Date: Tue Jan 26 14:06:26 2016 +1100
mb/intel/d510mo: Explicitly select NIC on PCI in devicetree
While the board configuration still works without this,
It's nicer to have the device statically defined since
the NIC is hardwired to the board.
Change-Id: Ic6682865dd17672c3782bfba9511cd120d1657c1
Signed-off-by: Damien Zammit <damien(a)zamaudio.com>
---
src/mainboard/intel/d510mo/devicetree.cb | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/src/mainboard/intel/d510mo/devicetree.cb b/src/mainboard/intel/d510mo/devicetree.cb
index c0f38de..c5b885f 100644
--- a/src/mainboard/intel/d510mo/devicetree.cb
+++ b/src/mainboard/intel/d510mo/devicetree.cb
@@ -43,7 +43,9 @@ chip northbridge/intel/pineview # Northbridge
register "gpe0_en" = "0x20000040"
device pci 1b.0 on end # Audio
- device pci 1c.0 on end # PCIe 1
+ device pci 1c.0 on # PCIe 1
+ device pci 0.0 on end # NIC
+ end
device pci 1c.1 on end # PCIe 2
device pci 1c.2 on end # PCIe 3
device pci 1c.3 on end # PCIe 4
the following patch was just integrated into master:
commit 988ee17fd2486415e8be4ebf49f57b5a1b97e685
Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com>
Date: Tue Nov 24 14:11:57 2015 -0600
superio/winbond/w83667hg-a: Add support for W83667HG-A
The KGPE-D16 and KCMA-D8 use a Winbond W83667HG-A SuperIO. While
the Nuvoton NCT5572D is effectively the same core, and a close
enough match to get things working initially, the W83667HG-A
has a different LDN mapping and several extra features that
require a separate support driver.
Clone the Nuvoton NCT5572D and modify according to the W83667HG-A
datasheet, version 1.4.
Change-Id: I707ba2e40a22d41cd813003d84a82cb20304f55b
Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/13156
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply(a)raptorengineeringinc.com>
Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de>
See https://review.coreboot.org/13156 for details.
-gerrit
the following patch was just integrated into master:
commit 8274accde894af7fb2e44ee70662eb632beebaf9
Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com>
Date: Tue Nov 24 14:11:56 2015 -0600
southbridge/amd/sb700: Add missing DMA setup step from AMD RRG
Change-Id: I412a0e5f2e0686b10a295dd7c0e9b537dc1a0940
Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/13154
Tested-by: build bot (Jenkins)
Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de>
Tested-by: Raptor Engineering Automated Test Stand <noreply(a)raptorengineeringinc.com>
See https://review.coreboot.org/13154 for details.
-gerrit
the following patch was just integrated into master:
commit 2ba84cd7ded80f6f4a17085ee4dd6af274ad3dde
Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com>
Date: Tue Nov 24 14:11:55 2015 -0600
mainboard/asus/kgpe-d16: Use stock PS/2 ACPI ASL file
Change-Id: Iad724e9e1d3e64e2af3f74fed9dec30aa34e2af5
Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/13153
Tested-by: build bot (Jenkins)
Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de>
Tested-by: Raptor Engineering Automated Test Stand <noreply(a)raptorengineeringinc.com>
See https://review.coreboot.org/13153 for details.
-gerrit
the following patch was just integrated into master:
commit cfea0bb44eb0eba5ed96b726f8846306f5d62f4b
Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com>
Date: Tue Nov 24 14:11:55 2015 -0600
mainboard/asus/kgpe-d16: Enable ASUS MIO audio option
The KGPE-D16 supports an optional MIO audio card, which connects
to the on-board HDA interface of the SP5100.
Enable the HDA interface for use with the MIO card.
Change-Id: Idfe069f4bce7b94a7460bc7fcdd378eb57e51fda
Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/13152
Tested-by: build bot (Jenkins)
Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de>
Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net>
Tested-by: Raptor Engineering Automated Test Stand <noreply(a)raptorengineeringinc.com>
See https://review.coreboot.org/13152 for details.
-gerrit
the following patch was just integrated into master:
commit 4c9c2f0d0df4a1c30bf78f80e282e2f6a2459a2b
Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com>
Date: Tue Nov 24 14:11:54 2015 -0600
mainboard/asus/kgpe-d16: Move memory test before IMD setup
Change-Id: Ic6fbf6688e4c2adc85e4eb9fa17e79d29dda58c0
Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/13151
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply(a)raptorengineeringinc.com>
Reviewed-by: Martin Roth <martinroth(a)google.com>
See https://review.coreboot.org/13151 for details.
-gerrit
the following patch was just integrated into master:
commit 8e9106db2064b3ab96ea840b60ab14c8fb558449
Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com>
Date: Tue Nov 24 14:11:53 2015 -0600
nb/amdmct/mct_ddr3: Enable mainboard voltage set
The existing code used an incorrect macro name to check for mainboard
DRAM voltage set support, and as a result no voltages were actually
set. Furthermore, the existing code did not contain a centralized
voltage assumption for boards that did not have a DIMM voltage set
implementation.
Use the correct macro name to test for boards with voltage set
implementation, and provide a basic fallback to 1.5V operation
for boards without a voltage set implementation.
Change-Id: I638c65fe013a8e600694d8cbedf6a10b33b0ef95
Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/13150
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply(a)raptorengineeringinc.com>
Reviewed-by: Martin Roth <martinroth(a)google.com>
See https://review.coreboot.org/13150 for details.
-gerrit