coreboot-gerrit January 2016

coreboot-gerrit@coreboot.org

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New patch to review for coreboot: amd/agesa/family15tn: Add Richland CPU ID
by Patrick Georgi 29 Jan '16

29 Jan '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13510 -gerrit commit 62e8bbc225b1dc1b0b825619e3b856db291df321 Author: Loic <hackurx(a)opensec.fr> Date: Fri Jan 29 14:14:16 2016 +0100 amd/agesa/family15tn: Add Richland CPU ID Add the AMD A8-660K APU. Change-Id: I210a8ba962529c26a535965689672a46b09e325f Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> --- src/cpu/amd/agesa/family15tn/model_15_init.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/cpu/amd/agesa/family15tn/model_15_init.c b/src/cpu/amd/agesa/family15tn/model_15_init.c index eda05f6..77357e9 100644 --- a/src/cpu/amd/agesa/family15tn/model_15_init.c +++ b/src/cpu/amd/agesa/family15tn/model_15_init.c @@ -130,6 +130,7 @@ static struct device_operations cpu_dev_ops = { static struct cpu_device_id cpu_table[] = { { X86_VENDOR_AMD, 0x610f00 }, /* TN-A0 */ + { X86_VENDOR_AMD, 0x610f31 }, /* RL-A1 (Richland) */ { 0, 0 }, };

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Patch set updated for coreboot: intel/skylake: Implement native Cache-as-RAM (CAR)
by Patrick Georgi 29 Jan '16

29 Jan '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13138 -gerrit commit 60df61c98bc36ff38944fd34a01f3c8e52ace3ab Author: Subrata Banik <subrata.banik(a)intel.com> Date: Tue Jan 19 19:19:15 2016 +0530 intel/skylake: Implement native Cache-as-RAM (CAR) Now coreboot should do BIOS CAR setup along with NEM mode setup. This patch also provides a mechanism to use 16MB code caching benefit although LLC still limited to 1M/1.5M based on SOC LLC limit. Here with unlimited cache line gets replaced. Now we could use unlimited cache size along with well defined data size [pg: updated to current upstream #defines] BUG=chrome-os-partner:48412 BRANCH=glados TEST=Builds and Boots on FAB4 SKU2/3. Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> Signed-off-by: pchandri <preetham.chandrian(a)intel.com> Signed-off-by: Dhaval Sharma <dhaval.v.sharma(a)intel.com> Change-Id: I96a9cf3a6e41cae9619c683dca28ad31dcaa2536 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 2ec51f15c874ad2f1f4fad52fa8deced7b27a24b Original-Change-Id: Id62c15799d98bc27b5e558adfa7c7b3468aa153a Original-Reviewed-on: https://chromium-review.googlesource.com/320855 Original-Commit-Ready: Subrata Banik <subrata.banik(a)intel.com> Original-Tested-by: Subrata Banik <subrata.banik(a)intel.com> Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/drivers/intel/fsp1_1/Kconfig | 8 - src/drivers/intel/fsp1_1/after_raminit.S | 11 +- src/drivers/intel/fsp1_1/cache_as_ram.inc | 19 +- src/soc/intel/skylake/Kconfig | 10 + src/soc/intel/skylake/include/soc/car_setup.S | 334 +++++++++++++++++++++++ src/soc/intel/skylake/include/soc/car_teardown.S | 54 ++++ src/soc/intel/skylake/romstage/romstage.c | 8 + 7 files changed, 427 insertions(+), 17 deletions(-) diff --git a/src/drivers/intel/fsp1_1/Kconfig b/src/drivers/intel/fsp1_1/Kconfig index c959e57..9b2c463 100644 --- a/src/drivers/intel/fsp1_1/Kconfig +++ b/src/drivers/intel/fsp1_1/Kconfig @@ -23,14 +23,6 @@ if PLATFORM_USES_FSP1_1 comment "Intel FSP 1.1" -config DCACHE_RAM_BASE - hex - default 0xfef00000 - -config DCACHE_RAM_SIZE - hex - default 0x4000 - config HAVE_FSP_BIN bool "Should the Intel FSP binary be added to the flash image" help diff --git a/src/drivers/intel/fsp1_1/after_raminit.S b/src/drivers/intel/fsp1_1/after_raminit.S index 85a0a8c..eb99157 100644 --- a/src/drivers/intel/fsp1_1/after_raminit.S +++ b/src/drivers/intel/fsp1_1/after_raminit.S @@ -20,7 +20,6 @@ #include <cpu/x86/cache.h> #include <cpu/x86/post_code.h> -.extern fih_car /* * This is the common entry point after DRAM has been initialized. */ @@ -31,6 +30,14 @@ /* Switch to the stack in RAM */ movl %eax, %esp +#if IS_ENABLED(CONFIG_SKIP_FSP_CAR) + + /* SOC specific NEM */ + #include <soc/car_teardown.S> + +#else +.extern fih_car + post_code(POST_FSP_TEMP_RAM_EXIT) /* Calculate TempRamExit entry into FSP */ @@ -56,8 +63,8 @@ */ movb $0xBC, %ah jmp .Lhlt - 1: +#endif /* Display the MTRRs */ call soc_display_mtrrs diff --git a/src/drivers/intel/fsp1_1/cache_as_ram.inc b/src/drivers/intel/fsp1_1/cache_as_ram.inc index 35abdb4..6e7e50b 100644 --- a/src/drivers/intel/fsp1_1/cache_as_ram.inc +++ b/src/drivers/intel/fsp1_1/cache_as_ram.inc @@ -33,17 +33,22 @@ * mm0: low 32-bits of TSC value * mm1: high 32-bits of TSC value */ - - mov %eax, %edi - + movl %eax, %edi cache_as_ram: post_code(0x20) +#if IS_ENABLED(CONFIG_SKIP_FSP_CAR) + /* - * edi: BIST value - * mm0: low 32-bits of TSC value - * mm1: high 32-bits of TSC value + * SOC specific setup + * NOTE: This has to preserve the registers + * mm0, mm1 and edi. */ + #include <soc/car_setup.S> + + post_code(0x28) + +#endif /* * Find the FSP binary in cbfs. @@ -143,7 +148,7 @@ CAR_init_done: rep stosl before_romstage: - post_code(0x23) + post_code(0x2A) /* Call cache_as_ram_main(struct cache_as_ram_params *) */ call cache_as_ram_main diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index 58b828f..35b2a18 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -176,4 +176,14 @@ config NHLT_SSM4567 help Include DSP firmware settings for ssm4567 smart amplifier. +config DCACHE_RAM_SIZE_TOTAL + hex + default 0x40000 + +config SKIP_FSP_CAR + bool "Skip cache as RAM setup in FSP" + default y + help + Skip Cache as RAM setup in FSP. + endif diff --git a/src/soc/intel/skylake/include/soc/car_setup.S b/src/soc/intel/skylake/include/soc/car_setup.S new file mode 100644 index 0000000..4b881a1 --- /dev/null +++ b/src/soc/intel/skylake/include/soc/car_setup.S @@ -0,0 +1,334 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC. + * Copyright (C) 2016 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include <cpu/x86/mtrr.h> +#include <cpu/x86/cache.h> +#include <cpu/x86/post_code.h> + +/* + * MTRR definitions + */ +.equ IA32_MTRR_CAP, 0x00fe + +.equ NO_EVICT_MODE, 0x02e0 + +.equ IA32_PQR_ASSOC, 0x0c8f +.equ IA32_L3_MASK_1, 0x0c91 +.equ IA32_L3_MASK_2, 0x0c92 +.equ CACHE_INIT_VALUE, 0 + +/* + * See BWG - chapter "Determining Cacheable Code Region Base Addresses and Ranges". + * + */ + + movl %edi, %ebp /* Put BIST value in a safe place */ + /* + * Ensure that all variable-range MTRR valid flags are clear and + * IA32_MTRR_DEF_TYPE MSR E flag is clear. Note: This is the default state + * after hardware reset. + * + * Initialize all fixed-range and variable-range MTRR register fields to 0. + */ + mov $(MtrrByteCountFixed), %ebx /* EBX = size of Fixed MTRRs */ + + xorl %eax, %eax /* Clear the low dword to write */ + xorl %edx, %edx /* Clear the high dword to write */ + xorl %ecx, %ecx + /* Clearing Fixed Range MTRRs */ +clear_mtrr_fixed: + addl $(-2), %ebx /* need to check it */ + movw (MtrrInitTable)(%ebx), %cx /* cx <- address of mtrr to zero */ + wrmsr + jnz clear_mtrr_fixed /* loop through the whole table */ + + post_code(0x21) + + /* Clearing Variable Range MTRRs */ + movl $MTRR_CAP_MSR, %ecx + rdmsr + movzx %al, %ebx + clr %eax + clr %edx + movl $MTRR_PHYS_BASE(0), %ecx +clear_var_mtrr: + wrmsr + inc %ecx + wrmsr + inc %ecx + dec %ebx + jnz clear_var_mtrr + + post_code(0x22) + + /* + * Configure the default memory type to un-cacheable (UC) in the + * IA32_MTRR_DEF_TYPE MSR. + */ + + movl $MTRR_DEF_TYPE_MSR, %ecx /* Load the MTRR default type index */ + rdmsr + andl $0xFFFFF300, %eax /* Clear the enable bits and def type UC. */ + wrmsr + + /* Configure MTRR_PHYS_MASK_HIGH for proper addressing above 4GB + * based on the physical address size supported for this processor + * This is based on read from CPUID EAX = 080000008h, EAX bits [7:0] + * + * Examples: + * MTRR_PHYS_MASK_HIGH = 00000000Fh For 36 bit addressing + * MTRR_PHYS_MASK_HIGH = 0000000FFh For 40 bit addressing + */ + + movl $0x80000008, %eax /* Address sizes leaf */ + cpuid + sub $32, %al + movzx %al, %eax + xorl %esi, %esi + bts %eax, %esi + dec %esi /* esi <- MTRR_PHYS_MASK_HIGH */ + + /* + * Configure the DataStack region as write-back (WB) cacheable memory type + * using the variable range MTRRs. + * + * + * Set the base address of the DataStack cache range + */ + + movl $CONFIG_DCACHE_RAM_BASE, %eax + orl $MTRR_TYPE_WRBACK, %eax /* Load the write-back cache value */ + xorl %edx, %edx /* clear upper dword */ + movl $MTRR_PHYS_BASE(0), %ecx /* Load the MTRR index */ + wrmsr /* the value in MTRR_PHYS_BASE_0 */ + + /* + * Set the mask for the DataStack cache range + * Compute MTRR mask value: Mask = NOT (Size - 1) + */ + movl $CONFIG_DCACHE_RAM_SIZE_TOTAL, %eax + dec %eax + not %eax + orl $MTRR_PHYS_MASK_VALID, %eax /* turn on the Valid flag */ + movl %esi, %edx /* edx <- MTRR_PHYS_MASK_HIGH */ + inc %ecx + wrmsr /* the value in MTRR_PHYS_MASK_0 */ + + post_code(0x23) + + /* + * Enable the MTRRs by setting the IA32_MTRR_DEF_TYPE MSR E flag. + */ + movl $MTRR_DEF_TYPE_MSR, %ecx /* Load the MTRR default type index */ + rdmsr + orl $MTRR_DEF_TYPE_EN, %eax /* Enable variable range MTRRs */ + wrmsr + + post_code(0x24) + + /* + * Enable the logical processor's (BSP) cache: execute INVD and set + * CR0.CD = 0, CR0.NW = 0. + */ + movl %cr0, %eax + and $(~(CR0_CD + CR0_NW)), %eax + invd + movl %eax, %cr0 + + /* + * Enable No-Eviction Mode Setup State by setting + * NO_EVICT_MODE MSR 2E0h bit [0] = '1'. + */ + movl $NO_EVICT_MODE, %ecx + rdmsr + orl $0x01, %eax + wrmsr + + /* Create n-way set associativity of cache */ + xorl %edi, %edi +Find_LLC_subleaf: + movl %edi, %ecx + movl $0x04, %eax + cpuid + inc %edi + and $0xe0, %al /* EAX[7:5] = Cache Level */ + cmp $0x60, %al /* Check to see if it is LLC */ + jnz Find_LLC_subleaf + + /* + * Set MSR 0xC91 IA32_L3_MASK_! = 0xE/0xFE/0xFFE/0xFFFE + * for 4/8/16 way of LLC + */ + shr $22, %ebx + inc %ebx + /* Calculate n-way associativity of LLC */ + mov %bl, %cl + + /* + * Maximizing RO cacheability while locking in the CAR to a + * single way since that particular way won't be victim candidate + * for evictions. + * This has been done after programing LLC_WAY_MASK_1 MSR + * with desired LLC way as mentioned below. + * + * Hence create Code and Data Size as per request + * Code Size (RO) : Up to 16M + * Data Size (RW) : Up to 256K + */ + movl $0x01, %eax + /* + * LLC Ways -> LLC_WAY_MASK_1: + * 4: 0x000E + * 8: 0x00FE + * 12: 0x0FFE + * 16: 0xFFFE + * + * These MSRs contain one bit per each way of LLC + * - If this bit is '0' - the way is protected from eviction + * - If this bit is '1' - the way is not protected from eviction + */ + shl %cl, %eax + subl $0x02, %eax + movl $IA32_L3_MASK_1, %ecx + xorl %edx, %edx + wrmsr + /* + * Set MSR 0xC92 IA32_L3_MASK_2 = 0x1 + * + * For SKL SOC, data size remains 256K consistently. + * Hence, creating 1-way associative cache for Data + */ + mov $IA32_L3_MASK_2, %ecx + mov $0x01, %eax + xorl %edx, %edx + wrmsr + /* + * Set IA32_PQR_ASSOC = 0x02 + * + * Possible values: + * 0: Default value, no way mask should be applied + * 1: Apply way mask 1 to LLC + * 2: Apply way mask 2 to LLC + * 3: Shouldn't be use in NEM Mode + */ + movl $IA32_PQR_ASSOC, %ecx + movl $0x02, %eax + xorl %edx, %edx + wrmsr + + movl $CONFIG_DCACHE_RAM_BASE, %edi + movl $CONFIG_DCACHE_RAM_SIZE_TOTAL, %ecx + shr $0x02, %ecx + movl $CACHE_INIT_VALUE, %eax + cld + rep stosl + /* + * Set IA32_PQR_ASSOC = 0x01 + * At this stage we apply LLC_WAY_MASK_1 to the cache. + * i.e. way 0 is protected from eviction. + */ + movl $IA32_PQR_ASSOC, %ecx + movl $0x01, %eax + xorl %edx, %edx + wrmsr + + /* + * Enable No-Eviction Mode Run State by setting + * NO_EVICT_MODE MSR 2E0h bit [1] = '1'. + */ + + movl $NO_EVICT_MODE, %ecx + rdmsr + orl $0x02, %eax + wrmsr + + post_code(0x25) + /* + * Configure the BIOS code region as write-protected (WP) cacheable + * memory type using a single variable range MTRR. + * + * Ensure region to cache meets MTRR requirements for + * size and alignment. + */ + movl $(0xFFFFFFFF - CONFIG_ROM_SIZE + 1), %edi /* Code region base */ + movl $CONFIG_ROM_SIZE, %eax /* Code region size */ + cmpl $0, %edi + jz InvalidParameter + cmpl $0, %eax + jz InvalidParameter + jmp CheckPass + +InvalidParameter: + movl $0x80000002, %eax /* RETURN_INVALID_PARAMETER */ + jmp .Lhlt + +CheckPass: + + post_code(0x26) + + /* + * Program base register + */ + xorl %edx, %edx /* clear upper dword */ + movl $MTRR_PHYS_BASE(1), %ecx /* setup variable mtrr */ + movl %edi, %eax + orl $MTRR_TYPE_WRPROT, %eax /* set type to write protect */ + wrmsr + + movl $CONFIG_ROM_SIZE, %eax + + /* + * Compute MTRR mask value: Mask = NOT (Size - 1) + */ + dec %eax /* eax - size to cache less one byte */ + not %eax /* eax contains low 32 bits of mask */ + or $MTRR_PHYS_MASK_VALID, %eax + /* + * Program mask register + */ + movl $MTRR_PHYS_MASK(1) , %ecx /* setup variable mtrr */ + movl %esi, %edx /* edx <- MTRR_PHYS_MASK_HIGH */ + wrmsr + + post_code(0x27) + + /* + * edi: BIST value + * mm0: low 32-bits of TSC value + * mm1: high 32-bits of TSC value + */ + movl %ebp, %edi /* Restore BIST value */ + + .section .rodata + +MtrrInitTable: + .word MTRR_DEF_TYPE_MSR + .word MTRR_FIX_64K_00000 + .word MTRR_FIX_16K_80000 + .word MTRR_FIX_16K_A0000 + .word MTRR_FIX_4K_C0000 + .word MTRR_FIX_4K_C8000 + .word MTRR_FIX_4K_D0000 + .word MTRR_FIX_4K_D8000 + .word MTRR_FIX_4K_E0000 + .word MTRR_FIX_4K_E8000 + .word MTRR_FIX_4K_F0000 + .word MTRR_FIX_4K_F8000 + +.equ MtrrByteCountFixed, (.-MtrrInitTable) + + .previous diff --git a/src/soc/intel/skylake/include/soc/car_teardown.S b/src/soc/intel/skylake/include/soc/car_teardown.S new file mode 100644 index 0000000..315b3c1 --- /dev/null +++ b/src/soc/intel/skylake/include/soc/car_teardown.S @@ -0,0 +1,54 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC. + * Copyright (C) 2016 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +.equ IA32_PQR_ASSOC, 0x0c8f + + /* Disable MTRR by clearing the IA32_MTRR_DEF_TYPE MSR E flag. */ + movl $MTRR_DEF_TYPE_MSR, %ecx + rdmsr + andl $(~MTRR_DEF_TYPE_EN), %eax + wrmsr + + /* Invalidate Cache */ + invd + + /* + * Disable No-Eviction Mode Run State by clearing + * NO_EVICT_MODE MSR 2E0h bit [1] = 0 + */ + movl $0x000002E0, %ecx + rdmsr + andl $~(0x2), %eax + wrmsr + + /* + * Disable No-Eviction Mode Setup State by clearing + * NO_EVICT_MODE MSR 2E0h bit [0] = 0 + */ + rdmsr + andl $~(0x1), %eax + wrmsr + + /* + * Set IA32_PQR_ASSOC = 0x00 + * This step guarantees that no protected way remain in LLC cache, + * all the ways are open for the evictions. + */ + movl $IA32_PQR_ASSOC, %ecx + movl $0x00, %eax + xorl %edx, %edx + wrmsr diff --git a/src/soc/intel/skylake/romstage/romstage.c b/src/soc/intel/skylake/romstage/romstage.c index b872d39..9b95f72 100644 --- a/src/soc/intel/skylake/romstage/romstage.c +++ b/src/soc/intel/skylake/romstage/romstage.c @@ -96,6 +96,10 @@ void soc_memory_init_params(struct romstage_params *params, upd->SaGv = config->SaGv; upd->RMT = config->Rmt; upd->DdrFreqLimit = config->DdrFreqLimit; + if (IS_ENABLED(CONFIG_SKIP_FSP_CAR)) { + upd->FspCarBase = CONFIG_DCACHE_RAM_BASE; + upd->FspCarSize = CONFIG_DCACHE_RAM_SIZE_TOTAL; + } } void soc_display_memory_init_params(const MEMORY_INIT_UPD *old, @@ -232,6 +236,10 @@ void soc_display_memory_init_params(const MEMORY_INIT_UPD *old, new->ApertureSize); fsp_display_upd_value("SaGv", 1, old->SaGv, new->SaGv); fsp_display_upd_value("RMT", 1, old->RMT, new->RMT); + fsp_display_upd_value("FspCarBase", 1, old->FspCarBase, + new->FspCarBase); + fsp_display_upd_value("FspCarSize", 1, old->FspCarSize, + new->FspCarSize); } /* SOC initialization after RAM is enabled. */

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Patch set updated for coreboot: OBSOLETE: soc/apollolake/cache_as_ram: Fix initial stack pointer calculation
by Andrey Petrov 29 Jan '16

29 Jan '16

Andrey Petrov (andrey.petrov(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13314 -gerrit commit 866c2a1e5c893db30f4b12f7beb0a321ed905b44 Author: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> Date: Thu Oct 22 09:28:13 2015 -0700 OBSOLETE: soc/apollolake/cache_as_ram: Fix initial stack pointer calculation We want the initial stack pointer to point within the region allocated for stack, and not above it. This means we need to place it four bytes below the end address, so the first push does not write above the allocated stack region. Change-Id: I288b3c0f04b9e3be742012124ecac7825874cb7f Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> --- src/soc/intel/apollolake/bootblock/cache_as_ram.S | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/soc/intel/apollolake/bootblock/cache_as_ram.S b/src/soc/intel/apollolake/bootblock/cache_as_ram.S index 6ecfa86..e496087 100644 --- a/src/soc/intel/apollolake/bootblock/cache_as_ram.S +++ b/src/soc/intel/apollolake/bootblock/cache_as_ram.S @@ -124,7 +124,7 @@ car_init_done: /* Setup bootblock stack */ mov esp, CONFIG_DCACHE_RAM_BASE - add esp, CONFIG_DCACHE_RAM_BOOTBLOCK_STACK_SIZE + add esp, CONFIG_DCACHE_RAM_BOOTBLOCK_STACK_SIZE - 4 /* Make sure CAR region is executable */ mov ecx, 0x120

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Patch set updated for coreboot: OBSOLETE: soc/apollolake: Add uart_platform_refclk() for ramstage
by Andrey Petrov 29 Jan '16

29 Jan '16

Andrey Petrov (andrey.petrov(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13333 -gerrit commit 01432d8010d822a7a33c63c96852f7d210a15f67 Author: Andrey Petrov <andrey.petrov(a)intel.com> Date: Mon Nov 2 15:52:56 2015 -0800 OBSOLETE: soc/apollolake: Add uart_platform_refclk() for ramstage Add uart_platform_refclk() so that it can be used in ramstage Change-Id: I0ef9501f372f098601edd49658e875478d0f70e7 Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> --- src/soc/intel/apollolake/uart.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/src/soc/intel/apollolake/uart.c b/src/soc/intel/apollolake/uart.c index 9663130..00bc45f 100644 --- a/src/soc/intel/apollolake/uart.c +++ b/src/soc/intel/apollolake/uart.c @@ -20,3 +20,9 @@ uintptr_t uart_platform_base(int idx) { return (CONFIG_CONSOLE_UART_BASE_ADDRESS); } + +unsigned int uart_platform_refclk(void) +{ + /* That's within 0.5% of the actual value we've set earlier */ + return 115200 * 16; +}

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Patch set updated for coreboot: OBSOLETE: soc/apollolake: Rename cpu.c to tsc_freq.c, add copyright header
by Andrey Petrov 29 Jan '16

29 Jan '16

Andrey Petrov (andrey.petrov(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13343 -gerrit commit fc1f129367678a5f4314eed245c74ee87bbb8387 Author: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> Date: Thu Nov 5 11:14:51 2015 -0800 OBSOLETE: soc/apollolake: Rename cpu.c to tsc_freq.c, add copyright header To be consistent with other platforms, cpu.c should contain the ramstage CPU drivers. Since other Intel SOCs use tsc_freq.c for the same purpose we used cpu.c, rename it accordingly. Change-Id: I4ce6d9d9b37cc28d3cd74f7dd795718a07c6e8d4 Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> --- src/soc/intel/apollolake/Makefile.inc | 6 +++--- src/soc/intel/apollolake/cpu.c | 9 --------- src/soc/intel/apollolake/tsc_freq.c | 21 +++++++++++++++++++++ 3 files changed, 24 insertions(+), 12 deletions(-) diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc index 63c39b3..ca81304 100644 --- a/src/soc/intel/apollolake/Makefile.inc +++ b/src/soc/intel/apollolake/Makefile.inc @@ -8,26 +8,26 @@ subdirs-y += ../../../cpu/x86/smm subdirs-y += ../../../cpu/x86/tsc bootblock-y += bootblock/bootblock_car.c -bootblock-y += cpu.c bootblock-y += gpio.c bootblock-y += bootblock/cache_as_ram.S bootblock-y += bootblock/early_chipset_config.S bootblock-y += mmap_boot.c +bootblock-y += tsc_freq.c bootblock-y += uart_early.c cpu_incs-y += $(src)/soc/intel/apollolake/romstage/entry.inc -romstage-y += cpu.c romstage-y += gpio.c romstage-y += memmap.c romstage-y += mmap_boot.c romstage-y += romstage/romstage.c +romstage-y += tsc_freq.c romstage-y += uart_early.c ramstage-y += chip.c -ramstage-y += cpu.c ramstage-y += gpio.c ramstage-y += memmap.c ramstage-y += mmap_boot.c +ramstage-y += tsc_freq.c ramstage-y += uart.c romstage-y += placeholders.c diff --git a/src/soc/intel/apollolake/cpu.c b/src/soc/intel/apollolake/cpu.c deleted file mode 100644 index e804697..0000000 --- a/src/soc/intel/apollolake/cpu.c +++ /dev/null @@ -1,9 +0,0 @@ -#include <cpu/x86/msr.h> -#include <cpu/x86/tsc.h> -#include <soc/cpu.h> - -unsigned long tsc_freq_mhz(void) -{ - msr_t msr = rdmsr(MSR_PLATFORM_INFO); - return (BASE_CLOCK_MHZ * ((msr.lo >> 8) & 0xff)); -} diff --git a/src/soc/intel/apollolake/tsc_freq.c b/src/soc/intel/apollolake/tsc_freq.c new file mode 100644 index 0000000..2e90ef2 --- /dev/null +++ b/src/soc/intel/apollolake/tsc_freq.c @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * (Written by Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include <cpu/x86/msr.h> +#include <cpu/x86/tsc.h> +#include <soc/cpu.h> + +unsigned long tsc_freq_mhz(void) +{ + msr_t msr = rdmsr(MSR_PLATFORM_INFO); + return (BASE_CLOCK_MHZ * ((msr.lo >> 8) & 0xff)); +}

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New patch to review for coreboot: mainboard/intel/galileo: Enable Serial Output
by Leroy P Leahy 29 Jan '16

29 Jan '16

Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13509 -gerrit commit cdd8841dcb587440e6a37a570e298a4fe1f7f02d Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Tue Jan 26 15:20:45 2016 -0800 mainboard/intel/galileo: Enable Serial Output Add the code to enable debug serial output using HSUART1: * Enable the code using Kconfig value ENABLE_BUILTIN_HSUART1 * Specify the portion of ESRAM to be used by romstage * Initialize the debug serial port * Serial output indicates a successful test TEST=Build and run on Galileo CQ-DEPEND=CL:13445 Change-Id: I91bf5257bd841ce9aa486887b35218336462ebea Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- src/mainboard/intel/galileo/Kconfig | 9 +++++++++ src/mainboard/intel/galileo/Makefile.inc | 2 ++ src/mainboard/intel/galileo/com_init.c | 26 ++++++++++++++++++++++++++ 3 files changed, 37 insertions(+) diff --git a/src/mainboard/intel/galileo/Kconfig b/src/mainboard/intel/galileo/Kconfig index dd2d1bb..6fe9abc 100755 --- a/src/mainboard/intel/galileo/Kconfig +++ b/src/mainboard/intel/galileo/Kconfig @@ -18,9 +18,18 @@ if BOARD_INTEL_GALILEO config BOARD_SPECIFIC_OPTIONS def_bool y select BOARD_ROMSIZE_KB_8192 + select ENABLE_BUILTIN_HSUART1 select PLATFORM_USES_FSP1_1 select SOC_INTEL_QUARK +config DCACHE_RAM_BASE + hex + default 0x80070000 + +config DCACHE_RAM_SIZE + hex + default 0x00008000 + if PLATFORM_USES_FSP1_1 config FSP_IMAGE_ID_STRING diff --git a/src/mainboard/intel/galileo/Makefile.inc b/src/mainboard/intel/galileo/Makefile.inc index 2c4be88..11010eb 100755 --- a/src/mainboard/intel/galileo/Makefile.inc +++ b/src/mainboard/intel/galileo/Makefile.inc @@ -15,6 +15,8 @@ CPPFLAGS_common += -I$(src)/vendorcode/intel/fsp/fsp1_1/quark +romstage-$(CONFIG_ENABLE_BUILTIN_HSUART1) += com_init.c + # Add the FSP binary to the cbfs image ifeq ($(CONFIG_HAVE_FSP_RAW_BIN),y) cbfs-files-y += fsp.bin diff --git a/src/mainboard/intel/galileo/com_init.c b/src/mainboard/intel/galileo/com_init.c new file mode 100644 index 0000000..3cf4cd6 --- /dev/null +++ b/src/mainboard/intel/galileo/com_init.c @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015-2016 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <fsp/car.h> +#include <device/pci.h> +#include <soc/iomap.h> +#include <soc/pci_devs.h> +#include <soc/romstage.h> + +void car_mainboard_pre_console_init(void) +{ + set_base_address_and_enable_uart(0, HSUART1_DEV, HSUART1_FUNC, UART_BASE_ADDRESS); +}

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New patch to review for coreboot: mainboard/intel/galileo: Add FSP binary support
by Leroy P Leahy 29 Jan '16

29 Jan '16

Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13508 -gerrit commit 6e8dfb1e87fbb60e466305008ba37400611d6927 Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Tue Jan 26 15:10:53 2016 -0800 mainboard/intel/galileo: Add FSP binary support Add the FSP binary to the flash image: * Specify the FSP binary image ID * Specify the default FSP binary file location * Specify where in the flash image the FSP image must reside * Specify where in the ESRAM the FSP image must reside * Note that the FSP binary image does not get relocated! Testing requires selecting HAVE_FSP_RAW_BIN and an FSP.bin file in the location specified by CONFIG_FSP_FILE. TEST=Build and run on Galileo Change-Id: I4d28b8e55d775a0906b6f535a8b9673f1b56fa30 Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- src/mainboard/intel/galileo/Kconfig | 63 ++++++++++++++++++++++++++++++++ src/mainboard/intel/galileo/Makefile.inc | 15 ++++++++ 2 files changed, 78 insertions(+) diff --git a/src/mainboard/intel/galileo/Kconfig b/src/mainboard/intel/galileo/Kconfig index cae136f..dd2d1bb 100755 --- a/src/mainboard/intel/galileo/Kconfig +++ b/src/mainboard/intel/galileo/Kconfig @@ -21,6 +21,69 @@ config BOARD_SPECIFIC_OPTIONS select PLATFORM_USES_FSP1_1 select SOC_INTEL_QUARK +if PLATFORM_USES_FSP1_1 + +config FSP_IMAGE_ID_STRING + string "8 byte platform string identifying the FSP platform" + default "QUK-FSP0" + help + 8 ASCII character byte signature string that will help match the FSP + binary to a supported hardware configuration. + +config FSP_FILE + string + default "3rdparty/blobs/mainboard/$(MAINBOARDDIR)/fsp.bin" + help + The path and filename of the Intel FSP binary for this platform. + +config FSP_LOC + hex + default 0xfff80000 + help + The location in CBFS that the FSP is located. This must match the + value that is set in the FSP binary. If the FSP needs to be moved, + rebase the FSP with Intel's BCT (tool). + +config FSP_PDAT_FILE + string + default "3rdparty/blobs/mainboard/$(MAINBOARDDIR)/pdat.bin" + depends on PLATFORM_USES_FSP1_1 + help + The path and filename of the Intel Galileo PDAT binary. This binary + is dumpped from Galileo BIOS. + +config FSP_PDAT_LOC + hex + default 0xfff10000 + depends on PLATFORM_USES_FSP1_1 + help + The location in CBFS that the PDAT is located. It must match the + PCD PcdPlatformDataBaseAddress of Quark SoC FSP. + +config FSP_SRAM_LOC + hex + default 0x80000000 + help + The location in SRAM where a copy of the FSP binary is placed. + +config HAVE_FSP_PDAT_FILE + bool + default n + help + The PDAT file is required for the FSP 1.1 binary + +config HAVE_FSP_RAW_BIN + bool "Should the Intel FSP binary be added to the flash image" + default n + help + Select this option to add an Intel FSP binary to + the resulting coreboot image. + + Note: Without this binary, coreboot builds relying on the FSP + will not boot + +endif # PLATFORM_USES_FSP1_1 + config MAINBOARD_DIR string default intel/galileo diff --git a/src/mainboard/intel/galileo/Makefile.inc b/src/mainboard/intel/galileo/Makefile.inc index 3ffba1c..2c4be88 100755 --- a/src/mainboard/intel/galileo/Makefile.inc +++ b/src/mainboard/intel/galileo/Makefile.inc @@ -14,3 +14,18 @@ ## CPPFLAGS_common += -I$(src)/vendorcode/intel/fsp/fsp1_1/quark + +# Add the FSP binary to the cbfs image +ifeq ($(CONFIG_HAVE_FSP_RAW_BIN),y) +cbfs-files-y += fsp.bin +fsp.bin-file := $(call strip_quotes,$(CONFIG_FSP_FILE)) +fsp.bin-position := $(CONFIG_FSP_LOC) +fsp.bin-type := raw +endif # CONFIG_HAVE_FSP_RAW_BIN + +ifeq ($(CONFIG_HAVE_FSP_PDAT_FILE),y) +cbfs-files-y += pdat.bin +pdat.bin-file := $(call strip_quotes,$(CONFIG_FSP_PDAT_FILE)) +pdat.bin-position := $(CONFIG_FSP_PDAT_LOC) +pdat.bin-type := raw +endif # CONFIG_HAVE_FSP_PDAT_FILE

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New patch to review for coreboot: mainboard/intel/galileo: Add Intel Galileo Gen 2 Support
by Leroy P Leahy 29 Jan '16

29 Jan '16

Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13507 -gerrit commit b265ac7e40e5e3cec10599ae5a916f5cf3940781 Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Tue Jan 26 10:06:42 2016 -0800 mainboard/intel/galileo: Add Intel Galileo Gen 2 Support Add the files to build soc/intel/quark and mainboard/intel/galileo for a minimal coreboot image. Please note that this configuration does not run. Include HTML documentation for the Galileo Gen 2 board. TEST=Build for Galileo CQ-DEPEND=CL:13436 CL:13439 Change-Id: Idd3fda1b8ed9460fa8c92e6dcaa601c3c9f63a36 Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- src/mainboard/intel/galileo/Kconfig | 36 +++++++++++ src/mainboard/intel/galileo/Kconfig.name | 17 +++++ src/mainboard/intel/galileo/Makefile.inc | 16 +++++ src/mainboard/intel/galileo/devicetree.cb | 24 +++++++ src/mainboard/intel/galileo/galileo.html | 100 ++++++++++++++++++++++++++++++ src/mainboard/intel/galileo/romstage.c | 24 +++++++ 6 files changed, 217 insertions(+) diff --git a/src/mainboard/intel/galileo/Kconfig b/src/mainboard/intel/galileo/Kconfig new file mode 100755 index 0000000..cae136f --- /dev/null +++ b/src/mainboard/intel/galileo/Kconfig @@ -0,0 +1,36 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2015-2016 Intel Corp. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +if BOARD_INTEL_GALILEO + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_8192 + select PLATFORM_USES_FSP1_1 + select SOC_INTEL_QUARK + +config MAINBOARD_DIR + string + default intel/galileo + +config MAINBOARD_PART_NUMBER + string + default "Galileo" + +config MAINBOARD_VENDOR + string + default "Intel" + +endif # BOARD_INTEL_QUARK diff --git a/src/mainboard/intel/galileo/Kconfig.name b/src/mainboard/intel/galileo/Kconfig.name new file mode 100644 index 0000000..124aa7a --- /dev/null +++ b/src/mainboard/intel/galileo/Kconfig.name @@ -0,0 +1,17 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2016 Intel Corp. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +config BOARD_INTEL_GALILEO + bool "Galileo" diff --git a/src/mainboard/intel/galileo/Makefile.inc b/src/mainboard/intel/galileo/Makefile.inc new file mode 100755 index 0000000..3ffba1c --- /dev/null +++ b/src/mainboard/intel/galileo/Makefile.inc @@ -0,0 +1,16 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2015-2016 Intel Corp. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +CPPFLAGS_common += -I$(src)/vendorcode/intel/fsp/fsp1_1/quark diff --git a/src/mainboard/intel/galileo/devicetree.cb b/src/mainboard/intel/galileo/devicetree.cb new file mode 100755 index 0000000..ab4f246 --- /dev/null +++ b/src/mainboard/intel/galileo/devicetree.cb @@ -0,0 +1,24 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2013 Google Inc. +## Copyright (C) 2015-2016 Intel Corp. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +chip soc/intel/quark + + device domain 0 on + # EDS Table 3 + device pci 00.0 on end # 8086 0958 - Host Bridge + device pci 1f.0 on end # 8086 095e - Legacy Bridge + end +end diff --git a/src/mainboard/intel/galileo/galileo.html b/src/mainboard/intel/galileo/galileo.html new file mode 100644 index 0000000..6fb75c9 --- /dev/null +++ b/src/mainboard/intel/galileo/galileo.html @@ -0,0 +1,100 @@ +<!DOCTYPE html> +<html> + <head> + <title>Galileo Gen 2</title> + </head> + <body> + +<h1>Intel® Galileo Gen 2 Development Board</h1> +<table> + <tr> + <td><a target="_blank" href="http://www.mouser.com/images/microsites/Intel_Galileo2_lrg.jpg"><img alt="Galileo Gen 2" src="http://www.mouser.com/images/microsites/Intel_Galileo2_lrg.jpg" width=500></a></td> + <td> +<table> + <tr bgcolor="#ffc0c0"> + <td> +Warning: Use of the Intel® Galileo Gen 2 mainboard code requires modification of the +util/xcompile/xcompile file to change the machine architecture from i686 to i586 because +the Quark™ processor does not support the instructions introduced with the +Pentium™ 6 architecture. +<ol> + <li>Edit the file util/xcompile/xcompile</li> + <li>Search for +<a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=util/xcompile/xco…">-march</a></li> + <li>Replace i686 with i586</li> + <li>Save the result</li> +</ol> +Without this change the Quark™ processor will halt when it executes one of the +instructions introduced with the Pentium™ 6 architecture. + </td> + </tr> +</table> +<p> + The Intel® Galileo Gen 2 mainboard code was developed along with the Intel® + <a target="_blank" href="../../../soc/intel/quark/quark.html">Quark™</a> SoC: +</p> +<ul> + <li><a target="_blank" href="../../../../Documentation/x86Development.html">Overall</a> development</li> + <li><a target="_blank" href="../../../soc/intel/soc.html">SoC</a> support</li> + <li><a target="_blank" href="../../../drivers/intel/fsp1_1/1_1.html">FSP 1.1</a> integration</li> + <li><a target="_blank" href="../board.html">Board</a> support</li> +</ul> + </td> + </tr> +</table> + + + +<hr> +<h1>Galileo Gen 2 Board Documentation</h1> +<ul> + <li><a target="_blank" href="http://files.linuxgizmos.com/intel_galileo_gen2_blockdiagram.jpg">Block Diagram</a></li> + <li><a target="_blank" href="https://software.intel.com/en-us/iot/library/galileo-getting-started">Getting Started</a></li> + <li><a target="_blank" href="http://www.intel.com/content/www/us/en/embedded/products/galileo/galileo-ov…">Overview</a></li> + <li><a target="_blank" href="http://files.linuxgizmos.com/intel_galileo_gen2_ports.jpg">Port Diagram</a></li> + <li><a target="_blank" href="http://download.intel.com/support/galileo/sb/intelgalileogen2prodbrief_3307…">Product Brief</a></li> + <li><a target="_blank" href="http://www.intel.com/content/dam/www/public/us/en/documents/guides/galileo-…">Schematic</a></li> + <li><a target="_blank" href="http://download.intel.com/support/galileo/sb/galileo_boarduserguide_330237_…">User Guide</a></li> + <li>Components + <ul> + <li>A/D: Texas Instruments <a target="_blank" href="http://www.ti.com/lit/ds/symlink/adc108s102.pdf">ADC108S102</a></li> + <li>Analog Switch: Texas Instruments <a target="_blank" href="http://www.ti.com/lit/ds/symlink/ts5a23159.pdf">TS5A23159</a></li> + <li>Ethernet (10/100 MB/S): Texas Instruments <a target="_blank" href="http://www.ti.com/lit/ds/symlink/dp83848-ep.pdf">DP83848</a></li> + <li>Load Switch: Texas Instruments <a target="_blank" href="http://www.ti.com/lit/ds/symlink/tps22920.pdf">TPS22920x</a></li> + <li>Memory (256 MiB): Micron <a target="_blank" href="https://www.micron.com/~/media/Documents/Products/Data%20Sheet/DRAM/DDR3/1G…">MT41K128M8</a></li> + <li>SoC: Intel® Quark™ <a target="_blank" href="../../../soc/intel/quark/quark.html">X-1000</a></li> + <li>Serial EEPROM (1 KiB): ON Semiconductor® <a target="_blank" href="http://www.onsemi.com/pub_link/Collateral/CAT24C01-D.PDF">CAT24C08</a></li> + <li>SPI Flash (8 MiB): Winbond™ <a target="_blank" href="http://www.winbond-usa.com/resource-files/w25q64fv_revl1_100713.pdf">W25Q64FV</a></li> + <li>Step Down Converter: Texas Instruments <a target="_blank" href="http://www.ti.com/lit/ds/slvsag7c/slvsag7c.pdf">TPS62130</a></li> + <li>Step Down Converter: Texas Instruments <a target="_blank" href="http://www.ti.com/lit/ug/slvu570/slvu570.pdf">TPS652510</a></li> + <li>Termination Regulator: Texas Instruments <a target="_blank" href="http://www.ti.com/lit/ds/symlink/tps51200.pdf">TPS51200</a></li> + </ul> + </li> +</ul> + + + +<hr> +<h1>Debug Tools</h1> +<ul> + <li>Flash Programmer: + <ul> + <li>Dediprog <a target="_blank" href="http://www.dediprog.com/pd/spi-flash-solution/SF100">SF100</a> ISP IC Programmer</li> + </ul> + </li> + <li>JTAG Connector: <a target="_blank" href="https://www.google.com/webhp?sourceid=chrome-instant&ion=1&espv=2&ie=UTF-8#…">Olimex ARM-JTAG-20-10</a></li> + <li>JTAG Debugger: + <ul> + <li>Olimex LTD <a target="_blank" href="https://www.google.com/webhp?sourceid=chrome-instant&ion=1&espv=2&ie=UTF-8#…">ARM-USB-OCD-H</a></li> + <li>Tincan Tools <a target="_blank" href="https://www.tincantools.com/wiki/Flyswatter2">Flyswatter2</a></li> + </ul> + </li> + <li><a target="_blank" href="http://download.intel.com/support/processors/quark/sb/sourcedebugusingopeno…">Hardware Setup and Software Installation</a></li> + <li>USB Serial cable: FTDI <a target="_blank" href="https://www.google.com/webhp?sourceid=chrome-instant&ion=1&espv=2&ie=UTF-8#…">TTL-232R-3V3</a></li> +</ul> + + +<hr> +<p>Modified: 27 January 2016</p> + </body> +</html> diff --git a/src/mainboard/intel/galileo/romstage.c b/src/mainboard/intel/galileo/romstage.c new file mode 100755 index 0000000..dfae772 --- /dev/null +++ b/src/mainboard/intel/galileo/romstage.c @@ -0,0 +1,24 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015-2016 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <fsp/romstage.h> + +/* All FSP specific code goes in this block */ +void mainboard_romstage_entry(struct romstage_params *rp) +{ + /* Call back into chipset code with platform values updated. */ + romstage_common(rp); +}

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Patch set updated for coreboot: soc/intel/quark: Enable Serial Port
by Leroy P Leahy 29 Jan '16

29 Jan '16

Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13445 -gerrit commit 48fe9009568d487a5766090a881ed6df9a73b1af Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Tue Jan 26 15:54:52 2016 -0800 soc/intel/quark: Enable Serial Port Add the code to enable debug serial output using HSUART1: * Enable the code using Kconfig value ENABLE_BUILTIN_HSUART1 * Note that the BIST value is always zero as validated in esram_init.inc * The initial TSC value is currently not saved! TEST=None CQ-DEPEND=CL:13443 Change-Id: I7e6181e8b9bc901c3ab236f0b56534850bb6bfd0 Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- src/soc/intel/quark/Kconfig | 30 ++++++++++++++++++ src/soc/intel/quark/Makefile.inc | 4 +++ src/soc/intel/quark/include/soc/iomap.h | 27 ++++++++++++++++ src/soc/intel/quark/include/soc/pci_devs.h | 26 ++++++++++++++++ src/soc/intel/quark/include/soc/romstage.h | 29 +++++++++++++++++ src/soc/intel/quark/romstage/Makefile.inc | 2 ++ src/soc/intel/quark/romstage/cache_as_ram.inc | 45 +++++++++++++++++++++++++-- src/soc/intel/quark/romstage/uart.c | 42 +++++++++++++++++++++++++ src/soc/intel/quark/tsc_freq.c | 36 +++++++++++++++++++++ src/soc/intel/quark/uart.c | 44 ++++++++++++++++++++++++++ 10 files changed, 283 insertions(+), 2 deletions(-) diff --git a/src/soc/intel/quark/Kconfig b/src/soc/intel/quark/Kconfig index fae29cc..cf8de91 100644 --- a/src/soc/intel/quark/Kconfig +++ b/src/soc/intel/quark/Kconfig @@ -26,6 +26,9 @@ config CPU_SPECIFIC_OPTIONS select ARCH_RAMSTAGE_X86_32 select ARCH_ROMSTAGE_X86_32 select ARCH_VERSTAGE_X86_32 + select SOC_INTEL_COMMON + select TSC_CONSTANT_RATE + select UDELAY_TSC config CBFS_SIZE hex @@ -71,6 +74,14 @@ config ENABLE_DEBUG_LED_TEMPRAMINIT help Indicate that TempRamInit was successful. +config ENABLE_BUILTIN_HSUART1 + bool "Enable built-in HSUART1" + default n + help + The Quark SoC has two HSUART. Choose this option to + configure the pads and enable HSUART1, which can be used for + the debug console. + config HAVE_RMU_FILE bool default n @@ -92,4 +103,23 @@ config RMU_LOC The location in CBFS that the RMU is located. It must match the strap-determined base address. +if ENABLE_BUILTIN_HSUART1 +config INTEL_UART_SPECIFIC_OPTIONS + def_bool y + select NO_UART_ON_SUPERIO + select DRIVERS_UART_8250MEM_32 + +config TTYS0_BASE + hex "HSUART1 Base Address" + depends on ENABLE_BUILTIN_HSUART1 + default 0xA0019000 + help + Memory mapped MMIO of HSUART1. + +config TTYS0_LCS + int + depends on ENABLE_BUILTIN_HSUART1 + default 3 + +endif # ENABLE_BUILTIN_HSUART1 endif # SOC_INTEL_QUARK diff --git a/src/soc/intel/quark/Makefile.inc b/src/soc/intel/quark/Makefile.inc index 5c22d34..622b649 100644 --- a/src/soc/intel/quark/Makefile.inc +++ b/src/soc/intel/quark/Makefile.inc @@ -19,8 +19,12 @@ subdirs-y += romstage subdirs-y += ../../../cpu/x86/tsc romstage-y += memmap.c +romstage-y += tsc_freq.c +romstage-$(CONFIG_ENABLE_BUILTIN_HSUART1) += uart.c ramstage-y += memmap.c +ramstage-y += tsc_freq.c +ramstage-$(CONFIG_ENABLE_BUILTIN_HSUART1) += uart.c CPPFLAGS_common += -I$(src)/soc/intel/quark/include diff --git a/src/soc/intel/quark/include/soc/iomap.h b/src/soc/intel/quark/include/soc/iomap.h new file mode 100644 index 0000000..f033dcb --- /dev/null +++ b/src/soc/intel/quark/include/soc/iomap.h @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015-2016 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _QUARK_IOMAP_H_ +#define _QUARK_IOMAP_H_ + +/* + * Memory Mapped IO base addresses. + */ + +/* UART MMIO */ +#define UART_BASE_ADDRESS CONFIG_TTYS0_BASE + +#endif /* _QUARK_IOMAP_H_ */ diff --git a/src/soc/intel/quark/include/soc/pci_devs.h b/src/soc/intel/quark/include/soc/pci_devs.h new file mode 100644 index 0000000..0543a05 --- /dev/null +++ b/src/soc/intel/quark/include/soc/pci_devs.h @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2013 Sage Electronic Engineering, LLC. + * Copyright (C) 2015-2016 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _QUARK_PCI_DEVS_H_ +#define _QUARK_PCI_DEVS_H_ + +/* IO Fabric 1 */ +#define SIO1_DEV 0x14 +# define HSUART1_DEV SIO1_DEV +# define HSUART1_FUNC 5 + +#endif /* _QUARK_PCI_DEVS_H_ */ diff --git a/src/soc/intel/quark/include/soc/romstage.h b/src/soc/intel/quark/include/soc/romstage.h new file mode 100644 index 0000000..a35f4a6 --- /dev/null +++ b/src/soc/intel/quark/include/soc/romstage.h @@ -0,0 +1,29 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2014 Sage Electronic Engineering, LLC. + * Copyright (C) 2015-2016 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _QUARK_ROMSTAGE_H_ +#define _QUARK_ROMSTAGE_H_ + +#if !defined(__PRE_RAM__) +#error "Don't include romstage.h from a ramstage compilation unit!" +#endif + +#include <fsp/util.h> + +int set_base_address_and_enable_uart(u8 bus, u8 dev, u8 func, u32 mmio_base); + +#endif /* _QUARK_ROMSTAGE_H_ */ diff --git a/src/soc/intel/quark/romstage/Makefile.inc b/src/soc/intel/quark/romstage/Makefile.inc index cb17d3d..518c6a5 100644 --- a/src/soc/intel/quark/romstage/Makefile.inc +++ b/src/soc/intel/quark/romstage/Makefile.inc @@ -15,3 +15,5 @@ cpu_incs-y += $(src)/soc/intel/quark/romstage/esram_init.inc cpu_incs-y += $(src)/soc/intel/quark/romstage/cache_as_ram.inc + +romstage-$(CONFIG_ENABLE_BUILTIN_HSUART1) += uart.c diff --git a/src/soc/intel/quark/romstage/cache_as_ram.inc b/src/soc/intel/quark/romstage/cache_as_ram.inc index 80ac64d..e1dcb62 100644 --- a/src/soc/intel/quark/romstage/cache_as_ram.inc +++ b/src/soc/intel/quark/romstage/cache_as_ram.inc @@ -112,8 +112,49 @@ CAR_init_done: movl %esi, %edx #endif /* CONFIG_ENABLE_DEBUG_LED_TEMPRAMINIT */ - clrl %eax - jmp halt2 + /* Setup bootloader stack */ + movl %edx, %esp + + /* + * eax: 0 + * ebp: FSP_INFO_HEADER address + * ecx: Temp RAM base + * edx: Temp RAM top + * edi: BIST value + * esp: Top of stack in temp RAM + */ + + /* Create cache_as_ram_params on stack */ + pushl %edx /* bootloader CAR end */ + pushl %ecx /* bootloader CAR begin */ + pushl %ebp /* FSP_INFO_HEADER */ + pushl %edi /* bist */ +// movd %mm1, %eax + pushl %eax /* tsc[63:32] */ +// movd %mm0, %eax + pushl %eax /* tsc[31:0] */ + pushl %esp /* pointer to cache_as_ram_params */ + + /* Save FSP_INFO_HEADER location in ebx */ + mov %ebp, %ebx + + /* Coreboot assumes stack/heap region will be zero */ + cld + movl %ecx, %edi + neg %ecx + /* Only clear up to current stack value. */ + add %esp, %ecx + shrl $2, %ecx + xorl %eax, %eax + rep stosl + +before_romstage: + post_code(0x23) + + /* Call cache_as_ram_main(struct cache_as_ram_params *) */ + call cache_as_ram_main + movb $0xB8, %ah + jmp .Lhlt halt1: /* diff --git a/src/soc/intel/quark/romstage/uart.c b/src/soc/intel/quark/romstage/uart.c new file mode 100644 index 0000000..2d53a48 --- /dev/null +++ b/src/soc/intel/quark/romstage/uart.c @@ -0,0 +1,42 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2003 Eric Biederman + * Copyright (C) 2006-2010 coresystems GmbH + * Copyright (C) 2015-2016 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +// Use simple device model for this file even in ramstage +#define __SIMPLE_DEVICE__ + +#include <device/pci.h> +#include <device/pci_def.h> +#include <rules.h> +#include <soc/romstage.h> + +int set_base_address_and_enable_uart(u8 bus, u8 dev, u8 func, u32 mmio_base) +{ + uint16_t reg16; + + /* HSUART controller #1 (B0:D20:F5). */ + device_t uart_dev = PCI_DEV(bus, dev, func); + + /* Decode BAR0(offset 0x10). */ + pci_write_config32(uart_dev, PCI_BASE_ADDRESS_0, mmio_base); + + /* Enable MEMBASE at CMD(offset 0x04). */ + reg16 = pci_read_config16(uart_dev, PCI_COMMAND); + reg16 |= PCI_COMMAND_MEMORY; + pci_write_config16(uart_dev, PCI_COMMAND, reg16); + + return 0; +} diff --git a/src/soc/intel/quark/tsc_freq.c b/src/soc/intel/quark/tsc_freq.c new file mode 100644 index 0000000..a770c81 --- /dev/null +++ b/src/soc/intel/quark/tsc_freq.c @@ -0,0 +1,36 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015-2016 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdint.h> +#include <cpu/x86/msr.h> +#include <cpu/x86/tsc.h> + +static unsigned long bus_freq_khz(void) +{ + /* cpu freq = 400 MHz */ + return 400 * 1000; +} + +unsigned long tsc_freq_mhz(void) +{ + /* assume ratio=1 */ + unsigned bclk_khz = bus_freq_khz(); + + if (!bclk_khz) + return 0; + + return (bclk_khz * 1) / 1000; +} diff --git a/src/soc/intel/quark/uart.c b/src/soc/intel/quark/uart.c new file mode 100644 index 0000000..f0e6c12 --- /dev/null +++ b/src/soc/intel/quark/uart.c @@ -0,0 +1,44 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2003 Eric Biederman + * Copyright (C) 2006-2010 coresystems GmbH + * Copyright (C) 2015-2016 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +// Use simple device model for this file even in ramstage +#define __SIMPLE_DEVICE__ + +#include <console/uart.h> +#include <device/pci.h> +#include <device/pci_def.h> +#include <rules.h> +#include <soc/pci_devs.h> + +unsigned int uart_platform_refclk(void) +{ + return 44236800; +} + +uintptr_t uart_platform_base(int idx) +{ + if (idx < 6) { + /* HSUART controller #1 (B0:D20:F5). */ + device_t dev = PCI_DEV(0, HSUART1_DEV, HSUART1_FUNC); + + /* UART base address at BAR0(offset 0x10). */ + return (unsigned int) (pci_read_config32(dev, PCI_BASE_ADDRESS_0) & ~0xfff); + } + else { + return 0; + } +}

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Patch set updated for coreboot: soc/intel/quark: FSP MemoryInit Support
by Leroy P Leahy 29 Jan '16

29 Jan '16

Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13447 -gerrit commit 0eed1aef3aeb9fe53dc04694336a3606338f0bdf Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Thu Jan 28 15:51:32 2016 -0800 soc/intel/quark: FSP MemoryInit Support Add a dummy fill_power_state routine so that execution is able to reach FSP MemoryInit. TEST=Build and run on Galileo Change-Id: I2a116e1e769ac09915638aa9e5d7c58a4aac3cce Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- src/soc/intel/quark/romstage/Makefile.inc | 1 + src/soc/intel/quark/romstage/cache_as_ram.inc | 11 ++++++++-- src/soc/intel/quark/romstage/romstage.c | 30 +++++++++++++++++++++++++++ 3 files changed, 40 insertions(+), 2 deletions(-) diff --git a/src/soc/intel/quark/romstage/Makefile.inc b/src/soc/intel/quark/romstage/Makefile.inc index 518c6a5..6ade32d 100644 --- a/src/soc/intel/quark/romstage/Makefile.inc +++ b/src/soc/intel/quark/romstage/Makefile.inc @@ -16,4 +16,5 @@ cpu_incs-y += $(src)/soc/intel/quark/romstage/esram_init.inc cpu_incs-y += $(src)/soc/intel/quark/romstage/cache_as_ram.inc +romstage-y += romstage.c romstage-$(CONFIG_ENABLE_BUILTIN_HSUART1) += uart.c diff --git a/src/soc/intel/quark/romstage/cache_as_ram.inc b/src/soc/intel/quark/romstage/cache_as_ram.inc index e1dcb62..e7aab3f 100644 --- a/src/soc/intel/quark/romstage/cache_as_ram.inc +++ b/src/soc/intel/quark/romstage/cache_as_ram.inc @@ -153,8 +153,15 @@ before_romstage: /* Call cache_as_ram_main(struct cache_as_ram_params *) */ call cache_as_ram_main - movb $0xB8, %ah - jmp .Lhlt + +/* One will never return from cache_as_ram_main() in verstage so there's + * no such thing as after ram init. */ +#if !ENV_VERSTAGE +#include "src/drivers/intel/fsp1_1/after_raminit.S" +#endif + + movb $0x69, %ah + jmp .Lhlt halt1: /* diff --git a/src/soc/intel/quark/romstage/romstage.c b/src/soc/intel/quark/romstage/romstage.c new file mode 100644 index 0000000..c1bc17e --- /dev/null +++ b/src/soc/intel/quark/romstage/romstage.c @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015-2016 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/early_variables.h> +#include <console/console.h> +#include <soc/pm.h> + +static struct chipset_power_state power_state CAR_GLOBAL; + +struct chipset_power_state *fill_power_state(void) +{ + struct chipset_power_state *ps = car_get_var_ptr(&power_state); + + ps->prev_sleep_state = 0; + printk(BIOS_DEBUG, "prev_sleep_state %d\n", ps->prev_sleep_state); + return ps; +}

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