the following patch was just integrated into master:
commit f8e491339f685bc43a0b8812f9f00a2918ce7611
Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com>
Date: Fri Oct 2 12:42:26 2015 -0700
arch/x86: Rename bootblock.S to bootblock_romcc.S
bootblock.S was used strictly for setting up the system so that the
assembly generated by ROMCC could be executed. Since the
infrastructure now exists to run a bootblock wihtout ROMCC, rename
this file accordingly. this is done to prevent any future confusion.
Change-Id: Icbf5804b66b9517f9ceb352bed86978dcf92228f
Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com>
Reviewed-on: https://review.coreboot.org/11784
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
See https://review.coreboot.org/11784 for details.
-gerrit
Andrey Petrov (andrey.petrov(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13351
-gerrit
commit b28f0af713de40de825f278b53644348c7eca973
Author: Andrey Petrov <andrey.petrov(a)intel.com>
Date: Thu Nov 5 14:43:14 2015 -0800
soc/apollolake: Reserve FSP memory in CBMEM
FSP needs to reserve some space in DRAM (just under TSEG) which may not
be touched by coreboot. We initialize cbmem in such a way this memory is
added as first element.
Change-Id: I9a9b7c9e9132acd2f341d72f7e34e78299815acd
Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com>
---
src/soc/intel/apollolake/romstage/romstage.c | 15 ++++++++++++++-
1 file changed, 14 insertions(+), 1 deletion(-)
diff --git a/src/soc/intel/apollolake/romstage/romstage.c b/src/soc/intel/apollolake/romstage/romstage.c
index 88d872e..b7ffd3a 100644
--- a/src/soc/intel/apollolake/romstage/romstage.c
+++ b/src/soc/intel/apollolake/romstage/romstage.c
@@ -18,6 +18,8 @@
#include <cpu/x86/msr.h>
#include <device/pci_def.h>
#include <fsp/api.h>
+#include <fsp/util.h>
+#include <device/resource.h>
#include <soc/iomap.h>
#include <soc/romstage.h>
#include <soc/uart.h>
@@ -74,6 +76,8 @@ static void *alloc_stack_in_ram(void)
asmlinkage void* romstage_entry(void)
{
void *hob_list_ptr;
+ struct resource fsp_mem;
+
/* Be careful. Bootblock might already have initialized the console */
if (!IS_ENABLED(CONFIG_BOOTBLOCK_CONSOLE)) {
lpss_console_uart_init();
@@ -86,7 +90,16 @@ asmlinkage void* romstage_entry(void)
fsp_memory_init(&hob_list_ptr);
- cbmem_initialize_empty();
+ fsp_find_reserved_memory(&fsp_mem, hob_list_ptr);
+
+ /* initialize cbmem by adding FSP reserved memory first thing */
+ cbmem_initialize_empty_id_size(CBMEM_ID_FSP_RESERVED_MEMORY,
+ fsp_mem.size);
+
+ /* make sure FSP memory is reserved in cbmem */
+ if (fsp_mem.base != (uintptr_t)cbmem_find(CBMEM_ID_FSP_RESERVED_MEMORY))
+ die("Failed to accommodate FSP reserved memory request");
+
return alloc_stack_in_ram();
}
Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13514
-gerrit
commit c3da55ef8a6d3041eb6a91c8221419fbc5659bb4
Author: Patrick Georgi <pgeorgi(a)chromium.org>
Date: Fri Jan 29 23:02:56 2016 +0100
util/release: extend release script
Add the ability to release a given commit id, and normalize the tarballs
to use coreboot/1000 for owner and group, and the last commit date as
mtime for all files.
Change-Id: Ia349f429090fe9804f7f14c226812646e2f712be
Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org>
---
util/release/build-release | 11 ++++++++---
1 file changed, 8 insertions(+), 3 deletions(-)
diff --git a/util/release/build-release b/util/release/build-release
index ae00dbf..f09f5b2 100755
--- a/util/release/build-release
+++ b/util/release/build-release
@@ -1,16 +1,21 @@
#!/bin/bash
# $1: new version name
+# $2: commit id (if not master)
set -e
if [ -z "$1" ]; then
- echo "usage: $0 version"
+ echo "usage: $0 version [commit id]"
echo "tags a new coreboot version and creates a tar archive"
exit 1
fi
git clone --recurse-submodules http://review.coreboot.org/coreboot.git coreboot-$1
cd coreboot-$1
+if [ -n "$2" ]; then
+ git reset --hard $2
+fi
git submodule update --init --checkout
git tag -a --force $1 -m "coreboot version $1"
printf "$1-$(git log --pretty=%H|head -1)\n" > .coreboot-version
+tstamp=$(git log --pretty=format:%ci -1)
cd ..
-tar --exclude-vcs --exclude=coreboot-${1}/3rdparty/blobs -cvf - coreboot-${1} |xz -9 > coreboot-${1}.tar.xz
-tar --exclude-vcs -cvf - coreboot-${1}/3rdparty/blobs |xz -9 > coreboot-blobs-${1}.tar.xz
+tar --mtime="$tstamp" --owner=coreboot:1000 --group=coreboot:1000 --exclude-vcs --exclude=coreboot-${1}/3rdparty/blobs -cvf - coreboot-${1} |xz -9 > coreboot-${1}.tar.xz
+tar --mtime="$tstamp" --owner=coreboot:1000 --group=coreboot:1000 --exclude-vcs -cvf - coreboot-${1}/3rdparty/blobs |xz -9 > coreboot-blobs-${1}.tar.xz
Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/11784
-gerrit
commit 54a78912bf2da82817d3ea6230ba37eced19bd05
Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com>
Date: Fri Oct 2 12:42:26 2015 -0700
arch/x86: Rename bootblock.S to bootblock_romcc.S
bootblock.S was used strictly for setting up the system so that the
assembly generated by ROMCC could be executed. Since the
infrastructure now exists to run a bootblock wihtout ROMCC, rename
this file accordingly. this is done to prevent any future confusion.
Change-Id: Icbf5804b66b9517f9ceb352bed86978dcf92228f
Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com>
---
src/arch/x86/Makefile.inc | 10 ++++----
src/arch/x86/bootblock.S | 40 -------------------------------
src/arch/x86/bootblock_romcc.S | 53 ++++++++++++++++++++++++++++++++++++++++++
3 files changed, 58 insertions(+), 45 deletions(-)
diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc
index 82b8ae3..2942cae 100644
--- a/src/arch/x86/Makefile.inc
+++ b/src/arch/x86/Makefile.inc
@@ -107,9 +107,6 @@ bootblock-y += memcpy.c
bootblock-y += memset.c
bootblock-y += mmap_boot.c
-# Add the assembly file that pulls in the rest of the dependencies in
-# the right order. Make sure the auto generated bootblock.inc is a proper
-# dependency. Make the same true for the linker sript.
bootblock-y += id.S
$(call src-to-obj,bootblock,$(dir)/id.S): $(obj)/build.h
@@ -132,9 +129,12 @@ else
LDFLAGS_bootblock += -m elf_x86_64 --oformat elf64-x86-64
endif
-bootblock-y += bootblock.S
+# Add the assembly file that pulls in the rest of the dependencies in
+# the right order. Make sure the auto generated bootblock.inc is a proper
+# dependency. Make the same true for the linker sript.
+bootblock-y += bootblock_romcc.S
bootblock-y += walkcbfs.S
-$(call src-to-obj,bootblock,$(dir)/bootblock.S): $(objgenerated)/bootblock.inc
+$(call src-to-obj,bootblock,$(dir)/bootblock_romcc.S): $(objgenerated)/bootblock.inc
bootblock-y += bootblock.ld
$(call src-to-obj,bootblock,$(dir)/bootblock.ld): $(objgenerated)/bootblock.ld
diff --git a/src/arch/x86/bootblock.S b/src/arch/x86/bootblock.S
deleted file mode 100644
index 27a23eb..0000000
--- a/src/arch/x86/bootblock.S
+++ /dev/null
@@ -1,40 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2015 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-/* This file assembles the bootblock program by the order of the includes. Thus,
- * it's extremely important that one pays very careful attention to the order
- * of the includes. */
-
-#include <arch/x86/prologue.inc>
-#include <cpu/x86/16bit/entry16.inc>
-#include <cpu/x86/16bit/reset16.inc>
-#include <cpu/x86/32bit/entry32.inc>
-
-#ifdef CONFIG_CHIPSET_BOOTBLOCK_INCLUDE
-#include CONFIG_CHIPSET_BOOTBLOCK_INCLUDE
-#endif
-
-#if IS_ENABLED(CONFIG_SSE)
-#include <cpu/x86/sse_enable.inc>
-#endif
-
-/*
- * This bootblock.inc file is generated by ROMCC. The above program flow
- * falls through to this point. ROMCC assumes the last function it parsed
- * is the main function and it places its instructions at the beginning of
- * the generated file. Moreover, any library/common code needed in bootblock
- * needs to come after bootblock.inc.
- */
-#include <generated/bootblock.inc>
diff --git a/src/arch/x86/bootblock_romcc.S b/src/arch/x86/bootblock_romcc.S
new file mode 100644
index 0000000..6c1723a
--- /dev/null
+++ b/src/arch/x86/bootblock_romcc.S
@@ -0,0 +1,53 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2015 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/*
+ * This is the original bootblock used by coreboot on x86 systems. It contains
+ * a monolithic code flow, assembled from the following stages:
+ * - reset16.inc: the reset vector
+ * - entry16.inc: protected mode setup
+ * - entry32.inc: segment descriptor setup
+ * - CONFIG_CHIPSET_BOOTBLOCK_INCLUDE: chipset-specific initialization
+ * - generated/bootblock.inc: ROMCC part of the bootblock
+ *
+ * This is used on platforms which do not select C_ENVIRONMENT_BOOTBLOCK, and it
+ * tries to do the absolute minimum before walking CBFS and jumping to romstage.
+ *
+ * This file assembles the bootblock program by the order of the includes. Thus,
+ * it's extremely important that one pays very careful attention to the order
+ * of the includes.
+ */
+
+#include <arch/x86/prologue.inc>
+#include <cpu/x86/16bit/entry16.inc>
+#include <cpu/x86/16bit/reset16.inc>
+#include <cpu/x86/32bit/entry32.inc>
+
+#ifdef CONFIG_CHIPSET_BOOTBLOCK_INCLUDE
+#include CONFIG_CHIPSET_BOOTBLOCK_INCLUDE
+#endif
+
+#if IS_ENABLED(CONFIG_SSE)
+#include <cpu/x86/sse_enable.inc>
+#endif
+
+/*
+ * This bootblock.inc file is generated by ROMCC. The above program flow
+ * falls through to this point. ROMCC assumes the last function it parsed
+ * is the main function and it places its instructions at the beginning of
+ * the generated file. Moreover, any library/common code needed in bootblock
+ * needs to come after bootblock.inc.
+ */
+#include <generated/bootblock.inc>
the following patch was just integrated into master:
commit 3141eac9007634710d9e307170e821f805204683
Author: Vladimir Serbinenko <phcoder(a)gmail.com>
Date: Fri Jan 29 19:42:02 2016 +0100
Revert "northbridge/intel/sandybridge: Fix random raminit failures"
It break x230 access to channel 1.
This reverts commit 9f1fbb9a3002e8d74d53d7973bd1c7e3d4879238.
Change-Id: I8a3b13d17729f25cea3460ac2f87bca3c193d388
Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com>
Reviewed-on: https://review.coreboot.org/13512
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Rudolph <siro(a)das-labor.org>
See https://review.coreboot.org/13512 for details.
-gerrit