coreboot-gerrit January 2016

coreboot-gerrit@coreboot.org

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2471 discussions

Patch set updated for coreboot: cpu/amd/fam10h-15h: Add workaround for AMD Erratum 600
by Timothy Pearson 30 Jan '16

30 Jan '16

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13170 -gerrit commit b6cead1f02d335d11afcc1e385e31d8c161a68aa Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Tue Nov 24 14:12:04 2015 -0600 cpu/amd/fam10h-15h: Add workaround for AMD Erratum 600 Change-Id: Ie175b5b490f77cc380536ebd737da8618d4b448b Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/cpu/amd/family_10h-family_15h/defaults.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/cpu/amd/family_10h-family_15h/defaults.h b/src/cpu/amd/family_10h-family_15h/defaults.h index 3618cb8..88950a3 100644 --- a/src/cpu/amd/family_10h-family_15h/defaults.h +++ b/src/cpu/amd/family_10h-family_15h/defaults.h @@ -270,6 +270,10 @@ static const struct { ForceErrType = 0x0, MultRetryErr = 0x0 */ + /* Errata 600 */ + { 0, 0x150, AMD_OR_B2, AMD_PTYPE_ALL, + 0x00000000, 0x00000e00 }, /* HtRetryCrcDatIns = 0x0 */ + /* Errata 351 * System software should program the Link Extended Control Registers[LS2En] * (F0x[18C:170][8]) to 0b for all links. System software should also

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Patch set updated for coreboot: lib/gcov-glue.c: Remove trailing number from COVERAGE_MAGIC macro
by Jean Lucas 30 Jan '16

30 Jan '16

Jean Lucas (jean(a)4ray.co) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13520 -gerrit commit 57541f5cc6d0b36950f05b6cd6759a3c79e81ca6 Author: Jean Lucas <jean(a)4ray.co> Date: Sat Jan 30 01:20:54 2016 -0500 lib/gcov-glue.c: Remove trailing number from COVERAGE_MAGIC macro The COVERAGE_MAGIC macro has a trailing `4' on it, which makes it a 64-bit large integer, as opposed to a 32-bit unsigned integer, as originally designated in `util/cbmem/cbmem.c'. Remove this number so building with CODE_COVERAGE will succeed. Change-Id: Ib5d7f2704a4c092c3eca6f62e219edb30950d793 Signed-off-by: Jean Lucas <jean(a)4ray.co> --- src/lib/gcov-glue.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/lib/gcov-glue.c b/src/lib/gcov-glue.c index 4e5a9e1..0e45247 100644 --- a/src/lib/gcov-glue.c +++ b/src/lib/gcov-glue.c @@ -34,7 +34,7 @@ typedef struct file { #define COVERAGE_SIZE (32*1024) -#define COVERAGE_MAGIC 0x584d41534 +#define COVERAGE_MAGIC 0x584d4153 static FILE *current_file = NULL; static FILE *previous_file = NULL;

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Patch set updated for coreboot: lib/gcov-glue.c: Remove trailing number from COVERAGE_MAGIC macro
by Jean Lucas 30 Jan '16

30 Jan '16

Jean Lucas (jean(a)4ray.co) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13520 -gerrit commit 56314c1e71c0775eb6d89ccb57f856f06f182305 Author: Jean Lucas <jean(a)4ray.co> Date: Sat Jan 30 01:20:54 2016 -0500 lib/gcov-glue.c: Remove trailing number from COVERAGE_MAGIC macro The COVERAGE_MAGIC macro has a trailing `4' on it, which makes it a 64-bit large integer, as opposed to a 32-bit unsigned integer, a originally designated in `util/cbmem/cbmem.c'. Remove this number so building with CODE_COVERAGE will succeed. Change-Id: Ib5d7f2704a4c092c3eca6f62e219edb30950d793 Signed-off-by: Jean Lucas <jean(a)4ray.co> --- src/lib/gcov-glue.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/lib/gcov-glue.c b/src/lib/gcov-glue.c index 4e5a9e1..0e45247 100644 --- a/src/lib/gcov-glue.c +++ b/src/lib/gcov-glue.c @@ -34,7 +34,7 @@ typedef struct file { #define COVERAGE_SIZE (32*1024) -#define COVERAGE_MAGIC 0x584d41534 +#define COVERAGE_MAGIC 0x584d4153 static FILE *current_file = NULL; static FILE *previous_file = NULL;

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Patch set updated for coreboot: lib/gcov-glue.c: Remove trailing number from COVERAGE_MAGIC macro
by Jean Lucas 30 Jan '16

30 Jan '16

Jean Lucas (jean(a)4ray.co) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13520 -gerrit commit 5121d744b9880967ebbc8bb72751c026ac381699 Author: Jean Lucas <jean(a)4ray.co> Date: Sat Jan 30 01:20:54 2016 -0500 lib/gcov-glue.c: Remove trailing number from COVERAGE_MAGIC macro The COVERAGE_MAGIC macro has a trailing `4' on it, which makes it a 64-bit large integer, as opposed to a 32-bit unsigned integer, a originally designated in `util/cbmem/cbmem.c'. Remove this number so so building with CODE_COVERAGE will succeed. Change-Id: Ib5d7f2704a4c092c3eca6f62e219edb30950d793 Signed-off-by: Jean Lucas <jean(a)4ray.co> --- src/lib/gcov-glue.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/lib/gcov-glue.c b/src/lib/gcov-glue.c index 4e5a9e1..0e45247 100644 --- a/src/lib/gcov-glue.c +++ b/src/lib/gcov-glue.c @@ -34,7 +34,7 @@ typedef struct file { #define COVERAGE_SIZE (32*1024) -#define COVERAGE_MAGIC 0x584d41534 +#define COVERAGE_MAGIC 0x584d4153 static FILE *current_file = NULL; static FILE *previous_file = NULL;

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New patch to review for coreboot: lib/gcov-glue.c: Remove trailing number from COVERAGE_MAGIC macro
by Jean Lucas 30 Jan '16

30 Jan '16

Jean Lucas (jean(a)4ray.co) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13520 -gerrit commit 3854a9cd0d71b647e05700ce941f01f570edd2ed Author: Jean Lucas <jean(a)4ray.co> Date: Sat Jan 30 01:20:54 2016 -0500 lib/gcov-glue.c: Remove trailing number from COVERAGE_MAGIC macro The COVERAGE_MAGIC macro has a trailing `4' on it, which makes it a 64-bit large integer, as opposed to a 32-bit unsigned integer, as originally designated in `util/cbmem/cbmem.c'. Remove this number so building with CODE_COVERAGE will succeed. Change-Id: Ib5d7f2704a4c092c3eca6f62e219edb30950d793 Signed-off-by: Jean Lucas <jean(a)4ray.co> --- src/lib/gcov-glue.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/lib/gcov-glue.c b/src/lib/gcov-glue.c index 4e5a9e1..0e45247 100644 --- a/src/lib/gcov-glue.c +++ b/src/lib/gcov-glue.c @@ -34,7 +34,7 @@ typedef struct file { #define COVERAGE_SIZE (32*1024) -#define COVERAGE_MAGIC 0x584d41534 +#define COVERAGE_MAGIC 0x584d4153 static FILE *current_file = NULL; static FILE *previous_file = NULL;

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Patch set updated for coreboot: mainboard/intel: Add dummy Apollolake RVP1 support
by Alexandru Gagniuc 30 Jan '16

30 Jan '16

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13305 -gerrit commit 301a0145b0214eb086f9ced2fe6774a819d999d5 Author: Andrey Petrov <andrey.petrov(a)intel.com> Date: Thu Oct 8 12:32:50 2015 -0700 mainboard/intel: Add dummy Apollolake RVP1 support Change-Id: Ie1ab158da9a1d9ba892c9b7119e67e3138eeaf2f Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> --- src/mainboard/intel/apollolake_rvp/Kconfig | 6 +++--- src/mainboard/intel/apollolake_rvp/Kconfig.name | 7 +++++++ 2 files changed, 10 insertions(+), 3 deletions(-) diff --git a/src/mainboard/intel/apollolake_rvp/Kconfig b/src/mainboard/intel/apollolake_rvp/Kconfig index 2c3e898..152e092 100644 --- a/src/mainboard/intel/apollolake_rvp/Kconfig +++ b/src/mainboard/intel/apollolake_rvp/Kconfig @@ -1,4 +1,4 @@ -if BOARD_INTEL_APOLLOLAKE_RVP2 +if BOARD_INTEL_APOLLOLAKE_RVP1 || BOARD_INTEL_APOLLOLAKE_RVP2 config BOARD_SPECIFIC_OPTIONS def_bool y @@ -11,10 +11,10 @@ config MAINBOARD_DIR config MAINBOARD_PART_NUMBER string - default "Apollolake RVP2" + default "Apollolake RVP" config MAINBOARD_VENDOR string default "Intel" -endif # BOARD_INTEL_APOLLOLAKE_RVP2 +endif # BOARD_INTEL_APOLLOLAKE_RVP1 || BOARD_INTEL_APOLLOLAKE_RVP2 diff --git a/src/mainboard/intel/apollolake_rvp/Kconfig.name b/src/mainboard/intel/apollolake_rvp/Kconfig.name index 56d5b4b..2443997 100644 --- a/src/mainboard/intel/apollolake_rvp/Kconfig.name +++ b/src/mainboard/intel/apollolake_rvp/Kconfig.name @@ -1,2 +1,9 @@ +# Two DDR3 SODIMM slots +# Discrete voltage regulators (VR) +config BOARD_INTEL_APOLLOLAKE_RVP1 + bool "Apollolake DDR3 RVP1" + +# Four LPDDR3 footprints (chip can be soldered or fixated with BGA sockets) +# PMIC instead of discrete VRs config BOARD_INTEL_APOLLOLAKE_RVP2 bool "Apollolake LPDDR3 RVP2"

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Patch set updated for coreboot: include/device: Move inline functions from pci_def.h to pci.h
by Alexandru Gagniuc 30 Jan '16

30 Jan '16

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13300 -gerrit commit 48e9779c56299385773c3f7fd21b58d725881f12 Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Tue Jan 5 17:00:27 2016 -0800 include/device: Move inline functions from pci_def.h to pci.h pci_def.h is supposed to only contain definitions, such that it may be included in assembly files. Declaration of functions in said file prevents that. Change-Id: I0f90a74291c8a2ef7a1e1027d2d2182f896050fb Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- src/include/device/pci.h | 7 +++++++ src/include/device/pci_def.h | 7 ------- 2 files changed, 7 insertions(+), 7 deletions(-) diff --git a/src/include/device/pci.h b/src/include/device/pci.h index fe31b54..9ef3614 100644 --- a/src/include/device/pci.h +++ b/src/include/device/pci.h @@ -119,6 +119,13 @@ unsigned pci_find_capability(device_t dev, unsigned cap); void pci_early_bridge_init(void); int pci_early_device_probe(u8 bus, u8 dev, u32 mmio_base); +#ifndef __ROMCC__ +static inline int pci_base_address_is_memory_space(unsigned int attr) +{ + return (attr & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_MEMORY; +} +#endif + #endif /* CONFIG_PCI */ #endif /* PCI_H */ diff --git a/src/include/device/pci_def.h b/src/include/device/pci_def.h index 04cf945..ef3427b 100644 --- a/src/include/device/pci_def.h +++ b/src/include/device/pci_def.h @@ -78,13 +78,6 @@ #define PCI_BASE_ADDRESS_IO_ATTR_MASK 0x03 /* bit 1 is reserved if address_space = 1 */ -#ifndef __ROMCC__ -static inline int pci_base_address_is_memory_space(unsigned int attr) -{ - return (attr & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_MEMORY; -} -#endif - /* Header type 0 (normal devices) */ #define PCI_CARDBUS_CIS 0x28 #define PCI_SUBSYSTEM_VENDOR_ID 0x2c

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Patch set updated for coreboot: soc/apollolake: Add initial cache-as-ram setup for bootblock
by Alexandru Gagniuc 30 Jan '16

30 Jan '16

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13301 -gerrit commit 00528235ffdf79f87ffaf216e749f2f5da7d6a64 Author: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> Date: Tue Oct 6 17:16:41 2015 -0700 soc/apollolake: Add initial cache-as-ram setup for bootblock This is the minimum setup needed to both get cache-as-ram setup and a C environment working. On apollolake, we only get 32 KiB of data loaded into an SRAM that is readonly to the main CPU. Due to this restriction we have to set CAR and a C environment very early on. While we originally had the code written in ATT syntax, we decided to rewrite in intel syntax so we can better collaborate with other teams. The rewrite also helped us catch a few bugs. Change-Id: I65c51f972580609d2c1f03dfe2a86bc5d45d1e46 Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> --- src/soc/intel/apollolake/Kconfig | 27 ++++ src/soc/intel/apollolake/Makefile.inc | 6 + src/soc/intel/apollolake/bootblock/bootblock_car.c | 23 +++ src/soc/intel/apollolake/bootblock/cache_as_ram.S | 162 +++++++++++++++++++++ .../apollolake/bootblock/early_chipset_config.S | 94 ++++++++++++ src/soc/intel/apollolake/include/soc/bootblock.h | 18 +++ 6 files changed, 330 insertions(+) diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index ca38494..f7ae68e 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -18,6 +18,7 @@ config CPU_SPECIFIC_OPTIONS select SSE2 select SUPPORT_CPU_UCODE_IN_CBFS # Misc options + select C_ENVIRONMENT_BOOTBLOCK select COLLECT_TIMESTAMPS select HAVE_INTEL_FIRMWARE select MMCONF_SUPPORT @@ -32,6 +33,32 @@ config CPU_SPECIFIC_OPTIONS select SOC_INTEL_COMMON select UDELAY_TSC +config MMCONF_BASE_ADDRESS + hex "PCI MMIO Base Address" + default 0xe0000000 + +config IOSF_BASE_ADDRESS + hex "MMIO Base Address of sideband bus" + default 0xd0000000 + +config DCACHE_RAM_BASE + hex "Base address of cache-as-RAM" + default 0xfef00000 + +config DCACHE_RAM_SIZE + hex "Length in bytes of cache-as-RAM" + default 0x80000 + help + The size of the cache-as-ram region required during bootblock + and/or romstage. + +config DCACHE_RAM_BOOTBLOCK_STACK_SIZE + hex + default 0x800 + help + The amount of anticipated stack usage from the bootblock during + pre-romstage initialization. + config CPU_ADDR_BITS int default 36 diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc index b37cf8d..cc3e013 100644 --- a/src/soc/intel/apollolake/Makefile.inc +++ b/src/soc/intel/apollolake/Makefile.inc @@ -7,8 +7,14 @@ subdirs-y += ../../../cpu/x86/mtrr subdirs-y += ../../../cpu/x86/smm subdirs-y += ../../../cpu/x86/tsc +bootblock-y += bootblock/bootblock_car.c +bootblock-y += bootblock/cache_as_ram.S +bootblock-y += bootblock/early_chipset_config.S + romstage-y += placeholders.c smm-y += placeholders.c ramstage-y += placeholders.c +CPPFLAGS_common += -I$(src)/soc/intel/apollolake/include + endif diff --git a/src/soc/intel/apollolake/bootblock/bootblock_car.c b/src/soc/intel/apollolake/bootblock/bootblock_car.c new file mode 100644 index 0000000..4be0815 --- /dev/null +++ b/src/soc/intel/apollolake/bootblock/bootblock_car.c @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * (Written by Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include <arch/io.h> +#include <soc/bootblock.h> + +void bootblock_car_main(void) +{ + /* Quick post code to show we made it to C code */ + outb(0x30, 0x80); + /* Don't return, so we see the above post code */ + while (1) + ; +} diff --git a/src/soc/intel/apollolake/bootblock/cache_as_ram.S b/src/soc/intel/apollolake/bootblock/cache_as_ram.S new file mode 100644 index 0000000..944c73d --- /dev/null +++ b/src/soc/intel/apollolake/bootblock/cache_as_ram.S @@ -0,0 +1,162 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * (Written by Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include <device/pci_def.h> +#include <cpu/x86/mtrr.h> +#include <cpu/x86/cache.h> +#include <cpu/x86/cr.h> +#include <cpu/x86/post_code.h> + +#define EVICT_CTL_MSR 0x2e0 + +.intel_syntax noprefix + +#undef post_code +#define post_code(value) \ + mov al, value; \ + outb CONFIG_POST_IO_PORT, al + +.global cache_as_ram +cache_as_ram: + post_code(0x21) + + /* Clear/disable fixed MTRRs */ + mov ebx, offset fixed_mtrr_list_size + xor eax, eax + xor edx, edx +clear_fixed_mtrr: + add ebx, -2 + movzxw ecx, word ptr [fixed_mtrr_list + ebx] + wrmsr + jnz clear_fixed_mtrr + + post_code(0x22) + + /* Figure put how many MTRRs we have, and clear them out */ + mov ecx, MTRR_CAP_MSR + rdmsr + movzxb ebx, al /* Number of variable MTRRs */ + mov ecx, MTRR_PHYS_BASE(0) + xor eax, eax + xor edx, edx +clear_var_mtrr: + wrmsr + inc ecx + wrmsr + inc ecx + dec ebx + jnz clear_var_mtrr + + post_code(0x23) + + /* Disable MTTRs, configure default memory type to uncacheable (UC) */ + mov ecx, MTRR_DEF_TYPE_MSR + rdmsr + and eax, ~0xcff + wrmsr + + post_code(0x24) + + /* Configure CAR region as write-back (WB) */ + mov ecx, MTRR_PHYS_BASE(0) + mov eax, CONFIG_DCACHE_RAM_BASE /* base */ + or eax, MTRR_TYPE_WRBACK + xor edx, edx + wrmsr + + /* Configure the MTRR mask for the size region */ + mov ecx, MTRR_PHYS_MASK(0) + mov eax, ~(CONFIG_DCACHE_RAM_SIZE - 1) /* size mask */ + or eax, MTRR_PHYS_MASK_VALID + wrmsr + + post_code(0x25) + + /* Enable variable MTRRs */ + mov ecx, MTRR_DEF_TYPE_MSR + rdmsr + or eax, MTRR_DEF_TYPE_EN + wrmsr + + /* Enable caching */ + mov eax, cr0 + and eax, ~(CR0_CD | CR0_NW) + invd + mov cr0, eax + + /* Disable cache eviction (setup stage) */ + mov ecx, EVICT_CTL_MSR + rdmsr + or eax, 1 + wrmsr + + post_code(0x26) + + /* Write something to each cache line */ + mov eax, 0xcafebabe + mov edi, CONFIG_DCACHE_RAM_BASE + mov ecx, (CONFIG_DCACHE_RAM_SIZE >> 6) +cache_init_loop: + mov [edi], eax + sfence + add edi, 64 + loop cache_init_loop + + post_code(0x27) + + /* Disable cache eviction (run stage) */ + mov ecx, EVICT_CTL_MSR + rdmsr + or eax, 2 + wrmsr + + post_code(0x28) + +car_init_done: + + /* Setup bootblock stack */ + mov esp, CONFIG_DCACHE_RAM_BASE + add esp, CONFIG_DCACHE_RAM_BOOTBLOCK_STACK_SIZE + + /* Make sure CAR region is executable */ + mov ecx, 0x120 + rdmsr + or ah, 0x1 + wrmsr + +before_carstage: + post_code(0x2b) + + /* Call romstage.c main function. */ + push .halt_forever /* In case bootblock_car_main returns */ + jmp bootblock_car_main + + /* Never reached */ + +.halt_forever: + post_code(POST_DEAD_CODE) + hlt + jmp .halt_forever + +fixed_mtrr_list: + .word MTRR_FIX_64K_00000 + .word MTRR_FIX_16K_80000 + .word MTRR_FIX_16K_A0000 + .word MTRR_FIX_4K_C0000 + .word MTRR_FIX_4K_C8000 + .word MTRR_FIX_4K_D0000 + .word MTRR_FIX_4K_D8000 + .word MTRR_FIX_4K_E0000 + .word MTRR_FIX_4K_E8000 + .word MTRR_FIX_4K_F0000 + .word MTRR_FIX_4K_F8000 +fixed_mtrr_list_size = . - fixed_mtrr_list diff --git a/src/soc/intel/apollolake/bootblock/early_chipset_config.S b/src/soc/intel/apollolake/bootblock/early_chipset_config.S new file mode 100644 index 0000000..95081d3 --- /dev/null +++ b/src/soc/intel/apollolake/bootblock/early_chipset_config.S @@ -0,0 +1,94 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * (Written by Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +.intel_syntax noprefix +.extern cache_as_ram + +#define post_code(value) \ + mov al, value; \ + outb CONFIG_POST_IO_PORT, al + +.global bootblock_pre_c_entry +bootblock_pre_c_entry: + /* + * eax: BIST value + */ + movd mm2, eax + + post_code(0x20) + +enable_pciex_bar: + mov eax, 0x80000060 /* ROOT PCI device reg60 PCIEX_BAR_*/ + mov dx, 0xcf8 + out dx, eax + mov eax, (CONFIG_MMCONF_BASE_ADDRESS | 1) + mov dx, 0xcfc + out dx, eax + +enable_iosf_bar: + mov ebp, (CONFIG_MMCONF_BASE_ADDRESS | 0x68000) /* IOSF PCI dev */ + mov dword ptr [ebp + 0x10], CONFIG_IOSF_BASE_ADDRESS /* BAR 0 */ + mov word ptr [ebp + 0x04], 0x06 /* PCI command */ + + +/* We need LPC for port80, but it won't work if the pads are not configured */ +configure_lpc_pads: + mov ecx, offset num_lpc_pads /* Number of pads to configure */ + lea esi, lpc_pad_params +init_lpc_pad: + mov edi, [esi + 0x00] /* MMIO addr of pad config registers */ + mov eax, [esi + 0x04] /* Pad CONF0 value */ + mov edx, [esi + 0x08] /* Pad CONF1 value */ + mov [edi + 0x00], eax /* Write CONF0 to config register */ + mov [edi + 0x04], edx /* Write CONF1 to config register */ + add esi, 0x0c + loop init_lpc_pad + + jmp cache_as_ram + +/* FIXME: Find a better way to define these */ + +#define LPC_CLKOUT0 0x118 +#define LPC_CLKOUT1 0x120 +#define LPC_AD0 0x128 +#define LPC_AD1 0x130 +#define LPC_AD2 0x138 +#define LPC_AD3 0x140 +#define LPC_CLKRUN 0x148 +#define LPC_FRAME 0x150 + +#define XLATE_LPC(off) ((0xc0 << 16 ) | (0x500 + (off))) +#define PAD_MMIO_ADDR(poff) CONFIG_IOSF_BASE_ADDRESS + XLATE_LPC(poff) + +lpc_pad_params: + .long PAD_MMIO_ADDR(LPC_CLKOUT0) + .long 0x44000400 + .long 0x0003C000 + .long PAD_MMIO_ADDR(LPC_AD0) + .long 0x44000402 + .long 0x0003F000 + .long PAD_MMIO_ADDR(LPC_AD1) + .long 0x44000402 + .long 0x0003F000 + .long PAD_MMIO_ADDR(LPC_AD2) + .long 0x44000402 + .long 0x0003F000 + .long PAD_MMIO_ADDR(LPC_AD3) + .long 0x44000402 + .long 0x0003F000 + .long PAD_MMIO_ADDR(LPC_FRAME) + .long 0x44000400 + .long 0x0003F000 + .long PAD_MMIO_ADDR(LPC_CLKOUT1) + .long 0x44000400 + .long 0x0003C000 +num_lpc_pads = ( . - lpc_pad_params) / 0xc diff --git a/src/soc/intel/apollolake/include/soc/bootblock.h b/src/soc/intel/apollolake/include/soc/bootblock.h new file mode 100644 index 0000000..f5fab18 --- /dev/null +++ b/src/soc/intel/apollolake/include/soc/bootblock.h @@ -0,0 +1,18 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * (Written by Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef _APOLLOLAKE_BOOTBLOCK_H_ +#define _APOLLOLAKE_BOOTBLOCK_H_ + +void bootblock_car_main(void); + +#endif /* _APOLLOLAKE_BOOTBLOCK_H_ */

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Patch set updated for coreboot: cpu/x86/tsc: Compile delay_tsc.c for the bootblock as well
by Alexandru Gagniuc 30 Jan '16

30 Jan '16

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13302 -gerrit commit 50d70eca7fa7ebb5862cf0635c159b2a963db171 Author: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> Date: Wed Oct 7 11:06:14 2015 -0700 cpu/x86/tsc: Compile delay_tsc.c for the bootblock as well This is needed in a follow-on patch to enable udelay() handling on apollolake, which is a dependency for the console code. Change-Id: I7da6a060a91b83f3b32c5c5d269c102ce7ae3b8a Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> --- src/cpu/x86/tsc/Makefile.inc | 1 + 1 file changed, 1 insertion(+) diff --git a/src/cpu/x86/tsc/Makefile.inc b/src/cpu/x86/tsc/Makefile.inc index bbebda9..7e2eab2 100644 --- a/src/cpu/x86/tsc/Makefile.inc +++ b/src/cpu/x86/tsc/Makefile.inc @@ -1,3 +1,4 @@ +bootblock-$(CONFIG_UDELAY_TSC) += delay_tsc.c ramstage-$(CONFIG_UDELAY_TSC) += delay_tsc.c romstage-$(CONFIG_TSC_CONSTANT_RATE) += delay_tsc.c verstage-$(CONFIG_TSC_CONSTANT_RATE) += delay_tsc.c

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Patch set updated for coreboot: soc/apollolake: Add tsc_freq_mhz() functionality for udelay()
by Alexandru Gagniuc 30 Jan '16

30 Jan '16

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13303 -gerrit commit 1c13fbf97ee429bb19cc70b728b455bfdeedc8c4 Author: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> Date: Tue Oct 6 16:31:34 2015 -0700 soc/apollolake: Add tsc_freq_mhz() functionality for udelay() Change-Id: I2f1147cefe2438992bff45fc0a1e91064217915d Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> --- src/soc/intel/apollolake/Kconfig | 1 + src/soc/intel/apollolake/Makefile.inc | 5 +++++ src/soc/intel/apollolake/include/soc/cpu.h | 20 ++++++++++++++++++++ src/soc/intel/apollolake/tsc_freq.c | 21 +++++++++++++++++++++ 4 files changed, 47 insertions(+) diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index f7ae68e..825a40f 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -32,6 +32,7 @@ config CPU_SPECIFIC_OPTIONS select RELOCATABLE_RAMSTAGE # Build fails if this is not selected select SOC_INTEL_COMMON select UDELAY_TSC + select TSC_CONSTANT_RATE config MMCONF_BASE_ADDRESS hex "PCI MMIO Base Address" diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc index cc3e013..17b4ae4 100644 --- a/src/soc/intel/apollolake/Makefile.inc +++ b/src/soc/intel/apollolake/Makefile.inc @@ -10,6 +10,11 @@ subdirs-y += ../../../cpu/x86/tsc bootblock-y += bootblock/bootblock_car.c bootblock-y += bootblock/cache_as_ram.S bootblock-y += bootblock/early_chipset_config.S +bootblock-y += tsc_freq.c + +romstage-y += tsc_freq.c + +ramstage-y += tsc_freq.c romstage-y += placeholders.c smm-y += placeholders.c diff --git a/src/soc/intel/apollolake/include/soc/cpu.h b/src/soc/intel/apollolake/include/soc/cpu.h new file mode 100644 index 0000000..d0d6afd --- /dev/null +++ b/src/soc/intel/apollolake/include/soc/cpu.h @@ -0,0 +1,20 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * (Written by Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef _SOC_APOLLOLAKE_CPU_H_ +#define _SOC_APOLLOLAKE_CPU_H_ + +#define MSR_PLATFORM_INFO 0xce + +#define BASE_CLOCK_MHZ 100 + +#endif /* _SOC_APOLLOLAKE_CPU_H_ */ diff --git a/src/soc/intel/apollolake/tsc_freq.c b/src/soc/intel/apollolake/tsc_freq.c new file mode 100644 index 0000000..2e90ef2 --- /dev/null +++ b/src/soc/intel/apollolake/tsc_freq.c @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * (Written by Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include <cpu/x86/msr.h> +#include <cpu/x86/tsc.h> +#include <soc/cpu.h> + +unsigned long tsc_freq_mhz(void) +{ + msr_t msr = rdmsr(MSR_PLATFORM_INFO); + return (BASE_CLOCK_MHZ * ((msr.lo >> 8) & 0xff)); +}

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coreboot-gerrit January 2016