coreboot-gerrit January 2016

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Patch set updated for coreboot: mainboard/intel: Add skeleton for Apollolake RVP board
by Alexandru Gagniuc 30 Jan '16

30 Jan '16

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13298 -gerrit commit 47e2045594cdf5584a895d3e79b02f0fbaabad8b Author: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> Date: Tue Oct 6 10:36:20 2015 -0700 mainboard/intel: Add skeleton for Apollolake RVP board Change-Id: I3e47c157c49ad55ff1ba824672ac2630a64a6037 Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> --- src/mainboard/intel/apollolake_rvp/Kconfig | 20 ++++++++++++++++++++ src/mainboard/intel/apollolake_rvp/Kconfig.name | 2 ++ src/mainboard/intel/apollolake_rvp/Makefile.inc | 1 + src/mainboard/intel/apollolake_rvp/devicetree.cb | 8 ++++++++ src/mainboard/intel/apollolake_rvp/romstage.c | 1 + 5 files changed, 32 insertions(+) diff --git a/src/mainboard/intel/apollolake_rvp/Kconfig b/src/mainboard/intel/apollolake_rvp/Kconfig new file mode 100644 index 0000000..2c3e898 --- /dev/null +++ b/src/mainboard/intel/apollolake_rvp/Kconfig @@ -0,0 +1,20 @@ +if BOARD_INTEL_APOLLOLAKE_RVP2 + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select SOC_INTEL_APOLLOLAKE + select BOARD_ROMSIZE_KB_8192 + +config MAINBOARD_DIR + string + default intel/apollolake_rvp + +config MAINBOARD_PART_NUMBER + string + default "Apollolake RVP2" + +config MAINBOARD_VENDOR + string + default "Intel" + +endif # BOARD_INTEL_APOLLOLAKE_RVP2 diff --git a/src/mainboard/intel/apollolake_rvp/Kconfig.name b/src/mainboard/intel/apollolake_rvp/Kconfig.name new file mode 100644 index 0000000..56d5b4b --- /dev/null +++ b/src/mainboard/intel/apollolake_rvp/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_INTEL_APOLLOLAKE_RVP2 + bool "Apollolake LPDDR3 RVP2" diff --git a/src/mainboard/intel/apollolake_rvp/Makefile.inc b/src/mainboard/intel/apollolake_rvp/Makefile.inc new file mode 100644 index 0000000..a48936e --- /dev/null +++ b/src/mainboard/intel/apollolake_rvp/Makefile.inc @@ -0,0 +1 @@ +# Nothing yet here diff --git a/src/mainboard/intel/apollolake_rvp/devicetree.cb b/src/mainboard/intel/apollolake_rvp/devicetree.cb new file mode 100644 index 0000000..741d88e --- /dev/null +++ b/src/mainboard/intel/apollolake_rvp/devicetree.cb @@ -0,0 +1,8 @@ +chip soc/intel/apollolake + + device cpu_cluster 0 on + device lapic 0 on end + end + device domain 0 on + end +end diff --git a/src/mainboard/intel/apollolake_rvp/romstage.c b/src/mainboard/intel/apollolake_rvp/romstage.c new file mode 100644 index 0000000..c5d3ce1 --- /dev/null +++ b/src/mainboard/intel/apollolake_rvp/romstage.c @@ -0,0 +1 @@ +/* Nothing here yet, but this file is needed by the buildsystem */

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Patch set updated for coreboot: arch/x86/Makefile.inc: Re-enable -Wa, --divide assembler flag
by Alexandru Gagniuc 30 Jan '16

30 Jan '16

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13299 -gerrit commit c1c4a60489df9780a376b25b66e40075afa4f281 Author: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> Date: Tue Oct 6 14:41:20 2015 -0700 arch/x86/Makefile.inc: Re-enable -Wa,--divide assembler flag In the follow-on patches, we use constant division to calculate the number of elements in an assembly structure. Since the size of one element is not a power of two for all structures, we can't bit shift. This allows us to do the computation at assembly time rather than runtime. Change-Id: Ic5693f39dee8daf759bfc16c79ac3c7ddb4de465 Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> --- src/arch/x86/Makefile.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 21084d3..d96f6e7 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -84,7 +84,7 @@ define early_x86_stage $(1)-y += memlayout.ld # The '.' include path is needed for the generated assembly.inc file. -$(1)-S-ccopts += -I. +$(1)-S-ccopts += -I. -Wa,--divide $$(objcbfs)/$(1).debug: $$$$($(1)-libs) $$$$($(1)-objs) @printf " LINK $$(subst $$(obj)/,,$$(@))\n"

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Patch set updated for coreboot: soc/apollolake: Add minimal accessors for sideband bus (IOSF)
by Alexandru Gagniuc 30 Jan '16

30 Jan '16

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13304 -gerrit commit d4a9a4a556762a6bc94a2c8686628f7e881ce2e4 Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Mon Oct 5 13:45:22 2015 -0700 soc/apollolake: Add minimal accessors for sideband bus (IOSF) Some configuration registers for the UART are placed behind the sideband bus. Change-Id: I84a620dbd0cf4b8f3fec119836d1c8f75c7f200a Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> --- src/soc/intel/apollolake/include/soc/iosf.h | 30 +++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/src/soc/intel/apollolake/include/soc/iosf.h b/src/soc/intel/apollolake/include/soc/iosf.h new file mode 100644 index 0000000..c9f578c --- /dev/null +++ b/src/soc/intel/apollolake/include/soc/iosf.h @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * (Written by Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef _SOC_APOLLOLAKE_IOSF_H_ +#define _SOC_APOLLOLAKE_IOSF_H_ + +#include <arch/io.h> + +inline static void iosf_write(uint8_t port, uint16_t reg, uint32_t val) +{ + uintptr_t base = CONFIG_IOSF_BASE_ADDRESS | (port << 16) | (reg & ~3); + write32((void *)base, val); +} + +inline static uint32_t iosf_read(uint8_t port, uint16_t reg) +{ + uintptr_t base = CONFIG_IOSF_BASE_ADDRESS | (port << 16) | (reg & ~3); + return read32((void *)base); +} + +#endif /* _SOC_APOLLOLAKE_IOSF_H_ */

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Patch set updated for coreboot: mainboard/intel: Add dummy Apollolake RVP1 support
by Alexandru Gagniuc 30 Jan '16

30 Jan '16

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13305 -gerrit commit 68e5fc2a6a975f9ab498e8af42708e17858a427b Author: Andrey Petrov <andrey.petrov(a)intel.com> Date: Thu Oct 8 12:32:50 2015 -0700 mainboard/intel: Add dummy Apollolake RVP1 support Change-Id: Ie1ab158da9a1d9ba892c9b7119e67e3138eeaf2f Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> --- src/mainboard/intel/apollolake_rvp/Kconfig | 6 +++--- src/mainboard/intel/apollolake_rvp/Kconfig.name | 3 +++ 2 files changed, 6 insertions(+), 3 deletions(-) diff --git a/src/mainboard/intel/apollolake_rvp/Kconfig b/src/mainboard/intel/apollolake_rvp/Kconfig index 2c3e898..152e092 100644 --- a/src/mainboard/intel/apollolake_rvp/Kconfig +++ b/src/mainboard/intel/apollolake_rvp/Kconfig @@ -1,4 +1,4 @@ -if BOARD_INTEL_APOLLOLAKE_RVP2 +if BOARD_INTEL_APOLLOLAKE_RVP1 || BOARD_INTEL_APOLLOLAKE_RVP2 config BOARD_SPECIFIC_OPTIONS def_bool y @@ -11,10 +11,10 @@ config MAINBOARD_DIR config MAINBOARD_PART_NUMBER string - default "Apollolake RVP2" + default "Apollolake RVP" config MAINBOARD_VENDOR string default "Intel" -endif # BOARD_INTEL_APOLLOLAKE_RVP2 +endif # BOARD_INTEL_APOLLOLAKE_RVP1 || BOARD_INTEL_APOLLOLAKE_RVP2 diff --git a/src/mainboard/intel/apollolake_rvp/Kconfig.name b/src/mainboard/intel/apollolake_rvp/Kconfig.name index 56d5b4b..c0cbd5e 100644 --- a/src/mainboard/intel/apollolake_rvp/Kconfig.name +++ b/src/mainboard/intel/apollolake_rvp/Kconfig.name @@ -1,2 +1,5 @@ +config BOARD_INTEL_APOLLOLAKE_RVP1 + bool "Apollolake DDR3 RVP1" + config BOARD_INTEL_APOLLOLAKE_RVP2 bool "Apollolake LPDDR3 RVP2"

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Patch set updated for coreboot: buildgcc: Update coreboot's IASL version to 20151218
by Stefan Reinauer 30 Jan '16

30 Jan '16

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12817 -gerrit commit 1fdf04ede3d26407b9500b1bc48dd546b86a79fb Author: Martin Roth <gaumless(a)gmail.com> Date: Wed Dec 30 15:10:13 2015 -0700 buildgcc: Update coreboot's IASL version to 20151218 Update IASL from 20150619 to 20151218 See release notes at acpica.org Change-Id: Ic7e7b3956378ad611069e984d5a59c78e4cb08b1 Signed-off-by: Martin Roth <gaumless(a)gmail.com> --- util/crossgcc/buildgcc | 2 +- .../patches/acpica-unix-20150619_iasl.patch | 12 ---------- .../patches/acpica-unix-20151218_iasl.patch | 27 ++++++++++++++++++++++ .../crossgcc/sum/acpica-unix-20150619.tar.gz.cksum | 1 - .../crossgcc/sum/acpica-unix-20151218.tar.gz.cksum | 1 + 5 files changed, 29 insertions(+), 14 deletions(-) diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index 66fa127..4540659 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -39,7 +39,7 @@ GCC_VERSION=5.2.0 GCC_AUTOCONF_VERSION=2.69 BINUTILS_VERSION=2.25 GDB_VERSION=7.9.1 -IASL_VERSION=20150619 +IASL_VERSION=20151218 PYTHON_VERSION=3.4.3 EXPAT_VERSION=2.1.0 # CLANG version number diff --git a/util/crossgcc/patches/acpica-unix-20150619_iasl.patch b/util/crossgcc/patches/acpica-unix-20150619_iasl.patch deleted file mode 100644 index 6cb087c..0000000 --- a/util/crossgcc/patches/acpica-unix-20150619_iasl.patch +++ /dev/null @@ -1,12 +0,0 @@ -diff -urN acpica-unix-20150619/source/compiler/asloptions.c acpica-unix-20150619/source/compiler/asloptions.c ---- acpica-unix-20150619/source/compiler/asloptions.c 2015-06-19 08:56:19.000000000 -0600 -+++ acpica-unix-20150619/source/compiler/asloptions.c 2015-12-08 10:44:58.816669240 -0700 -@@ -717,6 +717,7 @@ - case '^': - - printf (ACPI_COMMON_SIGNON (ASL_COMPILER_NAME)); -+ printf ("%s\n", COREBOOT_TOOLCHAIN_VERSION); - exit (0); - - case 'a': - diff --git a/util/crossgcc/patches/acpica-unix-20151218_iasl.patch b/util/crossgcc/patches/acpica-unix-20151218_iasl.patch new file mode 100644 index 0000000..e35a360 --- /dev/null +++ b/util/crossgcc/patches/acpica-unix-20151218_iasl.patch @@ -0,0 +1,27 @@ +Add coreboot toolchain version string +--- acpica-unix-20151218/source/compiler/asloptions.c ++++ acpica-unix-20151218/source/compiler/asloptions.c +@@ -169,6 +169,7 @@ + if (argc < 2) + { + printf (ACPI_COMMON_SIGNON (ASL_COMPILER_NAME)); ++ printf ("%s\n", COREBOOT_TOOLCHAIN_VERSION); + Usage (); + exit (1); + } +@@ -199,6 +200,7 @@ + if (Gbl_DoSignon) + { + printf (ACPI_COMMON_SIGNON (ASL_COMPILER_NAME)); ++ printf ("%s\n", COREBOOT_TOOLCHAIN_VERSION); + if (Gbl_IgnoreErrors) + { + printf ("Ignoring all errors, forcing AML file generation\n\n"); +@@ -743,6 +745,7 @@ + case '^': + + printf (ACPI_COMMON_SIGNON (ASL_COMPILER_NAME)); ++ printf ("%s\n", COREBOOT_TOOLCHAIN_VERSION); + exit (0); + + case 'a': diff --git a/util/crossgcc/sum/acpica-unix-20150619.tar.gz.cksum b/util/crossgcc/sum/acpica-unix-20150619.tar.gz.cksum deleted file mode 100644 index 4047300..0000000 --- a/util/crossgcc/sum/acpica-unix-20150619.tar.gz.cksum +++ /dev/null @@ -1 +0,0 @@ -ccc86513f10c47762bf46bf4d348c8cbda4336f5 tarballs/acpica-unix-20150619.tar.gz diff --git a/util/crossgcc/sum/acpica-unix-20151218.tar.gz.cksum b/util/crossgcc/sum/acpica-unix-20151218.tar.gz.cksum new file mode 100644 index 0000000..fb9876b --- /dev/null +++ b/util/crossgcc/sum/acpica-unix-20151218.tar.gz.cksum @@ -0,0 +1 @@ +97e430aa6e936e77abeba936345588fff003e280 tarballs/acpica-unix-20151218.tar.gz

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Patch set updated for coreboot: kconfig_lint: Add warning if tristate type is used in coreboot
by Martin Roth 30 Jan '16

30 Jan '16

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13460 -gerrit commit 34d91f63a91235356d3d12ed3d0a6d6fe18edfff Author: Martin Roth <martinroth(a)google.com> Date: Mon Jan 25 16:39:32 2016 -0700 kconfig_lint: Add warning if tristate type is used in coreboot Although there's no reason we COULDN'T use tristate types, we haven't up to this point. If there's a good reason to use them in the future, this check can be removed. Change-Id: I5f1903341f522bc957e394bc0fd288ba1adab431 Signed-off-by: Martin Roth <martinroth(a)google.com> --- util/lint/kconfig_lint | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/util/lint/kconfig_lint b/util/lint/kconfig_lint index 9384336..8bdca8d 100755 --- a/util/lint/kconfig_lint +++ b/util/lint/kconfig_lint @@ -949,6 +949,10 @@ sub handle_type { my $expression; ( $type, $expression ) = handle_if_line( $type, $inside_config, $filename, $line_no ); + if ( $type =~ /tristate/ ) { + show_warning("$filename:$line_no - tristate types are not used."); + } + if ($inside_config) { if ( exists( $symbols{$inside_config}{type} ) ) { if ( $symbols{$inside_config}{type} !~ /$type/ ) {

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Patch merged into coreboot/master: lint: Add a check for the executable bit being set on source code
by gerrit＠coreboot.org 30 Jan '16

30 Jan '16

the following patch was just integrated into master: commit 721ee01bb0668d2ea207048a11c339313ed248f5 Author: Martin Roth <martinroth(a)google.com> Date: Mon Jan 25 15:12:21 2016 -0700 lint: Add a check for the executable bit being set on source code Change-Id: Ia51bd0fa742b2cb17f638c15d669ad1a7f65fefd Signed-off-by: Martin Roth <martinroth(a)google.com> Reviewed-on: https://review.coreboot.org/13433 Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> Tested-by: build bot (Jenkins) See https://review.coreboot.org/13433 for details. -gerrit

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Patch set updated for coreboot: xcompile: Tell gcc that we need to access NULL pointers occassionally
by Patrick Georgi 30 Jan '16

30 Jan '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12298 -gerrit commit bd1edbcc7cf3e3e075ecdb6f34e6b47cfe40d174 Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Tue Nov 3 15:30:02 2015 +0100 xcompile: Tell gcc that we need to access NULL pointers occassionally gcc developers consider NULL pointers to be so bad that they add a trap instruction (ud2 on x86, something similar on ARM) when gcc encounters one. We need them every now and then (eg. via/cx700 raminit), so tell the compiler not to treat us like a userspace program. Change-Id: I1a062bfa55548ed0c2d11196633c6f63e83b807c Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> --- util/xcompile/xcompile | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/util/xcompile/xcompile b/util/xcompile/xcompile index 76c3698..8718c67 100755 --- a/util/xcompile/xcompile +++ b/util/xcompile/xcompile @@ -161,6 +161,11 @@ detect_special_flags() { testcc "$GCC" "$CFLAGS_GCC -Wl,--build-id=none" && CFLAGS_GCC="$CFLAGS_GCC -Wl,--build-id=none" + # Without this flag, gcc's __builtin_trap() traps accesses to NULL + # that may well be intended in RAM init code. + testcc "$GCC" "$CFLAGS_GCC -fno-delete-null-pointer-checks"&& + CFLAGS_GCC="$CFLAGS_GCC -fno-delete-null-pointer-checks" + case "$architecture" in x86) # Always build for i686 -- no sse/mmx instructions since SMM

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Patch merged into coreboot/master: soc/intel: Add skeleton infrastructure for Apollolake SOC
by gerrit＠coreboot.org 30 Jan '16

30 Jan '16

the following patch was just integrated into master: commit 7e86cd4bb2fd403951b068b0c70fb4f77ef6d072 Author: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> Date: Tue Oct 6 10:33:49 2015 -0700 soc/intel: Add skeleton infrastructure for Apollolake SOC This is the very very minimum needed to compile the code. Change-Id: I7f9e5f564181071591a4640019f59f91a4c456c6 Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> Reviewed-on: https://review.coreboot.org/13297 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See https://review.coreboot.org/13297 for details. -gerrit

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Patch merged into coreboot/master: arch/x86: Implement minimal bootblock for C_ENVIRONMENT_BOTOBLOCK
by gerrit＠coreboot.org 30 Jan '16

30 Jan '16

the following patch was just integrated into master: commit 6be6c8f2820db761c09ee4bd2cb4e3fd76285207 Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Tue Jan 26 18:22:43 2016 -0800 arch/x86: Implement minimal bootblock for C_ENVIRONMENT_BOTOBLOCK Some newer x86 systems can boot from non-memory-mapped boot media (e.g. EMMC). The bootblock may be backed by small amounts of SRAM, or other memory, similar to how most ARM chipsets work. In such cases, we may not have enough code space for romstage very early on. This means that CAR setup and early boot media (e.g. SPI, EMMC) drivers need to be implemented within the limited amount memory of storage available. Since the reset vector has to be contained in this early code memory, the bootblock is the best place to implement loading of other stages. Implement a bootblock which does the minimal initialization, up to, and including switch to protected mode. This then transfers control to platform-specific code. No stack is needed, and control is transferred via a "jmp" such that no stack operations are involved. Change-Id: I009b42b9a707cf11a74493bd4d8c189dc09b8ace Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Reviewed-on: https://review.coreboot.org/13485 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See https://review.coreboot.org/13485 for details. -gerrit

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coreboot-gerrit January 2016