coreboot-gerrit January 2016

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: mainboard/asus/kgpe-d16: Use W83667HG-A SuperIO instead of NCT5572D
by Timothy Pearson 30 Jan '16

30 Jan '16

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13157 -gerrit commit 667b0e3fafc6b21905363290af8ea3fda7d573ea Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Tue Nov 24 14:11:57 2015 -0600 mainboard/asus/kgpe-d16: Use W83667HG-A SuperIO instead of NCT5572D Change-Id: If67999098fbe2831eeb30cb8b362c558db5d2688 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/mainboard/asus/kgpe-d16/Kconfig | 2 +- src/mainboard/asus/kgpe-d16/devicetree.cb | 16 +++++++++------- src/mainboard/asus/kgpe-d16/romstage.c | 8 ++++---- 3 files changed, 14 insertions(+), 12 deletions(-) diff --git a/src/mainboard/asus/kgpe-d16/Kconfig b/src/mainboard/asus/kgpe-d16/Kconfig index f394ca9..23c91f0 100644 --- a/src/mainboard/asus/kgpe-d16/Kconfig +++ b/src/mainboard/asus/kgpe-d16/Kconfig @@ -12,7 +12,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SOUTHBRIDGE_AMD_SB700 select SOUTHBRIDGE_AMD_SB700_DISABLE_ISA_DMA select SOUTHBRIDGE_AMD_SUBTYPE_SP5100 - select SUPERIO_NUVOTON_NCT5572D + select SUPERIO_WINBOND_W83667HG_A select PARALLEL_CPU_INIT select HAVE_ROMSTAGE_CONSOLE_SPINLOCK select HAVE_ROMSTAGE_NVRAM_CBFS_SPINLOCK diff --git a/src/mainboard/asus/kgpe-d16/devicetree.cb b/src/mainboard/asus/kgpe-d16/devicetree.cb index 96372f9..8d64ac7 100644 --- a/src/mainboard/asus/kgpe-d16/devicetree.cb +++ b/src/mainboard/asus/kgpe-d16/devicetree.cb @@ -177,24 +177,27 @@ chip northbridge/amd/amdfam10/root_complex # Root complex device pci 14.1 on end # IDE 0x439c device pci 14.2 on end # HDA 0x4383 (ASUS MIO add-on card) device pci 14.3 on # LPC 0x439d (SMBUS primary controller) - chip superio/nuvoton/nct5572d # Super I/O + chip superio/winbond/w83667hg-a # Super I/O device pnp 2e.0 off end # FDC; Not available on the KGPE-D16 device pnp 2e.1 off end # LPT1; Not available on the KGPE-D16 device pnp 2e.2 on # Com1 io 0x60 = 0x3f8 irq 0x70 = 4 end - device pnp 2e.3 off end # IR: Not available on the KGPE-D16 + device pnp 2e.3 on # Com2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end device pnp 2e.5 on # PS/2 keyboard & mouse io 0x60 = 0x60 io 0x62 = 0x64 irq 0x70 = 1 irq 0x72 = 12 end - device pnp 2e.6 off end # CIR: Not available on the KGPE-D16 - device pnp 2e.7 off end # GIPO689 + device pnp 2e.6 off end # SPI: Not available on the KGPE-D16 + device pnp 2e.7 off end # GIPO6789 device pnp 2e.8 off end # WDT - device pnp 2e.9 off end # GPIO235 + device pnp 2e.9 off end # GPIO2345 device pnp 2e.a on end # ACPI device pnp 2e.b on # HW Monitor io 0x60 = 0x290 @@ -202,8 +205,7 @@ chip northbridge/amd/amdfam10/root_complex # Root complex irq 0x70 = 5 end device pnp 2e.c off end # PECI - device pnp 2e.d off end # SUSLED - device pnp 2e.e off end # CIRWKUP + device pnp 2e.d off end # VID_BUSSEL device pnp 2e.f off end # GPIO_PP_OD end end diff --git a/src/mainboard/asus/kgpe-d16/romstage.c b/src/mainboard/asus/kgpe-d16/romstage.c index 13af96f..89183cc 100644 --- a/src/mainboard/asus/kgpe-d16/romstage.c +++ b/src/mainboard/asus/kgpe-d16/romstage.c @@ -35,8 +35,8 @@ #include <delay.h> #include <cpu/x86/lapic.h> #include "northbridge/amd/amdfam10/reset_test.c" -#include <superio/nuvoton/common/nuvoton.h> -#include <superio/nuvoton/nct5572d/nct5572d.h> +#include <superio/winbond/common/winbond.h> +#include <superio/winbond/w83667hg-a/w83667hg-a.h> #include <cpu/x86/bist.h> #include <smp/spinlock.h> // #include "northbridge/amd/amdk8/incoherent_ht.c" @@ -46,7 +46,7 @@ #include "northbridge/amd/amdfam10/debug.c" #include "northbridge/amd/amdfam10/setup_resource_map.c" -#define SERIAL_DEV PNP_DEV(0x2e, NCT5572D_SP1) +#define SERIAL_DEV PNP_DEV(0x2e, W83667HG_A_SP1) static void activate_spd_rom(const struct mem_controller *ctrl); @@ -393,7 +393,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) sb7xx_51xx_pci_port80(); /* Initialize early serial */ - nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); /* Disable LPC legacy DMA support to prevent lockup */

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Patch set updated for coreboot: cpu/amd/fam10h-15h: Fix Family 15h boot hang when BSP lift enabled
by Timothy Pearson 30 Jan '16

30 Jan '16

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13158 -gerrit commit 9387e097b76f347e0515ac30d2735de377cd7b4f Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Tue Nov 24 14:11:58 2015 -0600 cpu/amd/fam10h-15h: Fix Family 15h boot hang when BSP lift enabled The existing code did not allow for the second core of the BSP to reside on an APIC ID other than 1, leading to a boot hang on Family 15h processors when APIC_ID_OFFSET was set to anything other than 0. Furthermore, insufficient AP stack space was allocated for AP start. Change-Id: I4ded3cfb3736149e2265848014352d7622d5042a Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/cpu/amd/family_10h-family_15h/Kconfig | 2 +- src/cpu/amd/family_10h-family_15h/init_cpus.c | 8 +++++++- 2 files changed, 8 insertions(+), 2 deletions(-) diff --git a/src/cpu/amd/family_10h-family_15h/Kconfig b/src/cpu/amd/family_10h-family_15h/Kconfig index bfb6751..2f3dfc0 100644 --- a/src/cpu/amd/family_10h-family_15h/Kconfig +++ b/src/cpu/amd/family_10h-family_15h/Kconfig @@ -48,7 +48,7 @@ config DCACHE_BSP_STACK_SLUSH config DCACHE_AP_STACK_SIZE hex - default 0x400 + default 0x500 config UDELAY_IO bool diff --git a/src/cpu/amd/family_10h-family_15h/init_cpus.c b/src/cpu/amd/family_10h-family_15h/init_cpus.c index 5a67601..e8e81d2 100644 --- a/src/cpu/amd/family_10h-family_15h/init_cpus.c +++ b/src/cpu/amd/family_10h-family_15h/init_cpus.c @@ -356,6 +356,7 @@ static u32 init_cpus(u32 cpu_init_detectedx, struct sys_info *sysinfo) uint32_t dword; uint8_t set_mtrrs; uint8_t node_count; + uint8_t fam15_bsp_core1_apicid; struct node_core_id id; /* Please refer to the calculations and explaination in cache_as_ram.inc before modifying these values */ @@ -483,7 +484,12 @@ static u32 init_cpus(u32 cpu_init_detectedx, struct sys_info *sysinfo) if (is_fam15h()) { /* core 1 on node 0 is special; to avoid corrupting the * BSP do not alter MTRRs on that core */ - if (apicid == 1) + if (IS_ENABLED(CONFIG_ENABLE_APIC_EXT_ID) && (CONFIG_APIC_ID_OFFSET > 0)) + fam15_bsp_core1_apicid = CONFIG_APIC_ID_OFFSET + 1; + else + fam15_bsp_core1_apicid = 1; + + if (apicid == fam15_bsp_core1_apicid) set_mtrrs = 0; else set_mtrrs = !!(apicid & 0x1);

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Patch set updated for coreboot: southbridge/amd/sb700: Set HPET min tick value to RPR recommendation
by Timothy Pearson 30 Jan '16

30 Jan '16

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13159 -gerrit commit cd195f0d03ac7a580ec7efd2f8309314ec7e493f Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Tue Nov 24 14:11:58 2015 -0600 southbridge/amd/sb700: Set HPET min tick value to RPR recommendation Change-Id: I766eca6369b60a79a6823bc744934e3f1fbc17b2 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/southbridge/amd/sb700/Kconfig | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/southbridge/amd/sb700/Kconfig b/src/southbridge/amd/sb700/Kconfig index 9a0ddb2..9a988a9 100644 --- a/src/southbridge/amd/sb700/Kconfig +++ b/src/southbridge/amd/sb700/Kconfig @@ -50,4 +50,8 @@ config EHCI_BAR hex default 0xfef00000 +config HPET_MIN_TICKS + hex + default 0x14 + endif # SOUTHBRIDGE_AMD_SB700

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Patch set updated for coreboot: nb/amd/mct_ddr3: Fix RDIMM training failure on Fam15h
by Timothy Pearson 30 Jan '16

30 Jan '16

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13148 -gerrit commit a35f8ec33b5b94312fcf8caf772994eb457846bb Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Tue Nov 24 14:11:52 2015 -0600 nb/amd/mct_ddr3: Fix RDIMM training failure on Fam15h Certain registered DIMMs failed training due to an error likely introduced during historical rebase. Ensure that the SubMemclkRegDly bit is set according to BKDG recommendations on Family 15 processors. Change-Id: I24c95265dada9eabf4df280b6f2b4a1eb9cecaf1 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/northbridge/amd/amdmct/mct_ddr3/mctproc.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctproc.c b/src/northbridge/amd/amdmct/mct_ddr3/mctproc.c index cf13b40..fc62afb 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctproc.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctproc.c @@ -66,6 +66,9 @@ u32 mct_SetDramConfigMisc2(struct DCTStatStruc *pDCTstat, misc2 |= ((cs_mux_67 & 0x1) << 27); misc2 &= ~(0x1 << 26); /* CsMux45 = cs_mux_45 */ misc2 |= ((cs_mux_45 & 0x1) << 26); + + if (pDCTstat->Status & (1 << SB_Registered)) + misc2 |= 1 << SubMemclkRegDly; } else if (pDCTstat->LogicalCPUID & (AMD_DR_Dx | AMD_DR_Cx)) { if (pDCTstat->Status & (1 << SB_Registered)) { misc2 |= 1 << SubMemclkRegDly;

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Patch set updated for coreboot: mainboard/asus/kgpe-d16: Add CPB control CMOS option
by Timothy Pearson 30 Jan '16

30 Jan '16

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13173 -gerrit commit ffc6cd57ce0046c6bcdda34a9a214979b4a070ac Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Tue Nov 24 14:12:07 2015 -0600 mainboard/asus/kgpe-d16: Add CPB control CMOS option Change-Id: I28ad2298ad4dfb428dcd41a4f00db88c5e817cd7 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/mainboard/asus/kgpe-d16/cmos.default | 1 + src/mainboard/asus/kgpe-d16/cmos.layout | 5 +++-- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/src/mainboard/asus/kgpe-d16/cmos.default b/src/mainboard/asus/kgpe-d16/cmos.default index a05b9c3..0e7afb3 100644 --- a/src/mainboard/asus/kgpe-d16/cmos.default +++ b/src/mainboard/asus/kgpe-d16/cmos.default @@ -17,6 +17,7 @@ interleave_nodes = Disable interleave_memory_channels = Enable cpu_c_states = Enable cpu_cc6_state = Enable +cpu_core_boost = Enable sata_ahci_mode = Enable sata_alpm = Disable maximum_p_state_limit = 0xf diff --git a/src/mainboard/asus/kgpe-d16/cmos.layout b/src/mainboard/asus/kgpe-d16/cmos.layout index d1c0702..075388e 100644 --- a/src/mainboard/asus/kgpe-d16/cmos.layout +++ b/src/mainboard/asus/kgpe-d16/cmos.layout @@ -48,8 +48,9 @@ entries 476 1 e 1 l3_cache_partitioning 477 1 e 1 ieee1394_controller 478 1 e 1 iommu -479 1 e 1 experimental_memory_speed_boost -480 1 r 0 allow_spd_nvram_cache_restore +479 1 e 1 cpu_core_boost +480 1 e 1 experimental_memory_speed_boost +481 1 r 0 allow_spd_nvram_cache_restore 728 256 h 0 user_data 984 16 h 0 check_sum # Reserve the extended AMD configuration registers

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Patch set updated for coreboot: cpu/amd/fam10h-fam15h: Add CMOS option to disable CPB (core boost)
by Timothy Pearson 30 Jan '16

30 Jan '16

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13172 -gerrit commit 4f1e1e64ac9685093bdea76f1ab67d4f10a5120d Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Tue Nov 24 14:12:07 2015 -0600 cpu/amd/fam10h-fam15h: Add CMOS option to disable CPB (core boost) On certain systems and CPUs Core Performance Boost (CPB) may cause sporadic system lockups. This issue is also somewhat known on the various proprietary BIOSes, therefore it seems to be a hardware incompatibility when present. Allow the user to disable CBP if needed. Change-Id: Id6395d067d48963f6c084ad0bf79e23419af24d8 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/cpu/amd/family_10h-family_15h/init_cpus.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/src/cpu/amd/family_10h-family_15h/init_cpus.c b/src/cpu/amd/family_10h-family_15h/init_cpus.c index e2a1bf3..c1ff240 100644 --- a/src/cpu/amd/family_10h-family_15h/init_cpus.c +++ b/src/cpu/amd/family_10h-family_15h/init_cpus.c @@ -987,6 +987,7 @@ void cpuSetAMDMSR(uint8_t node_id) u32 platform; uint64_t revision; uint8_t enable_c_states; + uint8_t enable_cpb; printk(BIOS_DEBUG, "cpuSetAMDMSR "); @@ -1078,6 +1079,19 @@ void cpuSetAMDMSR(uint8_t node_id) enable_c_states = 0; #endif + if (revision & AMD_FAM15_ALL) { + enable_cpb = 1; + if (get_option(&nvram, "cpu_core_boost") == CB_SUCCESS) + enable_cpb = !!nvram; + + if (!enable_cpb) { + /* Disable Core Performance Boost */ + msr = rdmsr(0xc0010015); + msr.lo |= (0x1 << 25); /* CpbDis = 1 */ + wrmsr(0xc0010015, msr); + } + } + printk(BIOS_DEBUG, " done\n"); }

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Patch set updated for coreboot: cpu/amd/fam10h-15h: Set PowerStepUp/PowerStepDown on Fam15h
by Timothy Pearson 30 Jan '16

30 Jan '16

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13174 -gerrit commit c59ee9ec5cabae504faa864cd60dc67c75626425 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Tue Nov 24 14:12:07 2015 -0600 cpu/amd/fam10h-15h: Set PowerStepUp/PowerStepDown on Fam15h Multilink Family 15h processors were being configured with an incorrect PowerStepUp/PowerStepDown value. Set the value according to the BKDG, and clean up the terrible formatting of the power_up_down() function that led to the incorrect values being overlooked until now. Change-Id: I16e1f5205d6b5f349a3e7167dea04c9eefda4684 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/cpu/amd/family_10h-family_15h/fidvid.c | 96 ++++++++++++++++-------------- 1 file changed, 50 insertions(+), 46 deletions(-) diff --git a/src/cpu/amd/family_10h-family_15h/fidvid.c b/src/cpu/amd/family_10h-family_15h/fidvid.c index 2edb75e..5bef7d3 100644 --- a/src/cpu/amd/family_10h-family_15h/fidvid.c +++ b/src/cpu/amd/family_10h-family_15h/fidvid.c @@ -390,56 +390,60 @@ static u32 nb_clk_did(uint8_t node, uint64_t cpuRev, uint8_t procPkg) { static u32 power_up_down(int node, u8 procPkg) { - u32 dword=0; - /* from CPU rev guide #41322 rev 3.74 June 2010 Table 26 */ - u8 singleLinkFlag = ((procPkg == AMD_PKGTYPE_AM3_2r2) - || (procPkg == AMD_PKGTYPE_S1gX) - || (procPkg == AMD_PKGTYPE_ASB2)); - - if (singleLinkFlag) { - /* - * PowerStepUp=01000b - 50nS - * PowerStepDown=01000b - 50ns - */ - dword |= PW_STP_UP50 | PW_STP_DN50; - } else { - u32 dispRefModeEn = (pci_read_config32(NODE_PCI(node,0),0x68) >> 24) & 1; - u32 isocEn = 0; - int j; - for(j=0 ; (j<4) && (!isocEn) ; j++ ) { - u8 offset; - if (AMD_CpuFindCapability(node, j, &offset)) { - isocEn = (pci_read_config32(NODE_PCI(node,0),offset+4) >>12) & 1; - } - } - - if (dispRefModeEn || isocEn) { - dword |= PW_STP_UP50 | PW_STP_DN50 ; - } else { - /* get number of cores for PowerStepUp & PowerStepDown in server - 1 core - 400nS - 0000b - 2 cores - 200nS - 0010b - 3 cores - 133nS -> 100nS - 0011b - 4 cores - 100nS - 0011b + uint32_t dword=0; + /* from CPU rev guide #41322 rev 3.74 June 2010 Table 26 */ + u8 singleLinkFlag = ((procPkg == AMD_PKGTYPE_AM3_2r2) + || (procPkg == AMD_PKGTYPE_S1gX) + || (procPkg == AMD_PKGTYPE_ASB2)); + + if (singleLinkFlag) { + /* + * PowerStepUp=01000b - 50nS + * PowerStepDown=01000b - 50ns */ - switch (get_core_num_in_bsp(node)) { - case 0: - dword |= PW_STP_UP400 | PW_STP_DN400; - break; - case 1: - case 2: - dword |= PW_STP_UP200 | PW_STP_DN200; - break; - case 3: - dword |= PW_STP_UP100 | PW_STP_DN100; - break; - default: + dword |= PW_STP_UP50 | PW_STP_DN50; + } else { + uint32_t dispRefModeEn = (pci_read_config32(NODE_PCI(node,0),0x68) >> 24) & 1; + uint32_t isocEn = 0; + int j; + for (j=0 ; (j<4) && (!isocEn) ; j++ ) { + u8 offset; + if (AMD_CpuFindCapability(node, j, &offset)) { + isocEn = (pci_read_config32(NODE_PCI(node,0),offset+4) >>12) & 1; + } + } + + if (is_fam15h()) { + /* Family 15h always uses 100ns for multilink processors */ dword |= PW_STP_UP100 | PW_STP_DN100; - break; + } else if (dispRefModeEn || isocEn) { + dword |= PW_STP_UP50 | PW_STP_DN50 ; + } else { + /* get number of cores for PowerStepUp & PowerStepDown in server + * 1 core - 400nS - 0000b + * 2 cores - 200nS - 0010b + * 3 cores - 133nS -> 100nS - 0011b + * 4 cores - 100nS - 0011b + */ + switch (get_core_num_in_bsp(node)) { + case 0: + dword |= PW_STP_UP400 | PW_STP_DN400; + break; + case 1: + case 2: + dword |= PW_STP_UP200 | PW_STP_DN200; + break; + case 3: + dword |= PW_STP_UP100 | PW_STP_DN100; + break; + default: + dword |= PW_STP_UP100 | PW_STP_DN100; + break; + } } - } } - return dword; + + return dword; } static void config_clk_power_ctrl_reg0(uint8_t node, uint64_t cpuRev, uint8_t procPkg) {

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Patch set updated for coreboot: mainboard/asus/kgpe-d16: Wait for all APs to stop before MCT setup
by Timothy Pearson 30 Jan '16

30 Jan '16

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13169 -gerrit commit fa9f44375d5a382d6e355c74da366762e1c92a4b Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Tue Nov 24 14:12:03 2015 -0600 mainboard/asus/kgpe-d16: Wait for all APs to stop before MCT setup Under certain conditions when the APs are still executing during MCT setup the system can hang. This was the root cause of most of the S3 resume failures on this platform; waiting for AP stop before MCT setup allows for reliable S3 resume. Change-Id: I329eea9a8912d7b57efe6aae327d24fd6c3fd782 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/mainboard/asus/kgpe-d16/romstage.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/mainboard/asus/kgpe-d16/romstage.c b/src/mainboard/asus/kgpe-d16/romstage.c index 89183cc..1904bc2 100644 --- a/src/mainboard/asus/kgpe-d16/romstage.c +++ b/src/mainboard/asus/kgpe-d16/romstage.c @@ -515,6 +515,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x3B); + /* Wait for all APs to be stopped, otherwise ram initialization may hang */ + if (IS_ENABLED(CONFIG_LOGICAL_CPUS)) + wait_all_other_cores_stopped(bsp_apicid); + /* It's the time to set ctrl in sysinfo now; */ printk(BIOS_DEBUG, "fill_mem_ctrl() detected %d nodes\n", sysinfo->nodes); if (is_fam15h())

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Patch set updated for coreboot: cpu/amd/fam10h-fam15h: Add new wait_ap_stopped function
by Timothy Pearson 30 Jan '16

30 Jan '16

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13168 -gerrit commit 77b07718bb39fc9df65f9be446e220ad088e5789 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Tue Nov 24 14:12:02 2015 -0600 cpu/amd/fam10h-fam15h: Add new wait_ap_stopped function Under certain conditions, such as when microcode updates are being performed, it is important to make sure all APs have finished updates and are halted before continuing with the boot process. Add a new wait_ap_stopped() function to allow for this functionality to be added to the appropriate mainboard romstage source files. Change-Id: Ib455c937888a58b283bd3f8fda1b486eea41b0a7 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/cpu/amd/family_10h-family_15h/init_cpus.c | 20 ++++++++++++++++++++ src/include/cpu/amd/multicore.h | 1 + 2 files changed, 21 insertions(+) diff --git a/src/cpu/amd/family_10h-family_15h/init_cpus.c b/src/cpu/amd/family_10h-family_15h/init_cpus.c index e8e81d2..e2a1bf3 100644 --- a/src/cpu/amd/family_10h-family_15h/init_cpus.c +++ b/src/cpu/amd/family_10h-family_15h/init_cpus.c @@ -299,6 +299,26 @@ void allow_all_aps_stop(u32 bsp_apicid) lapic_write(LAPIC_MSG_REG, (bsp_apicid << 24) | F10_APSTATE_STOPPED); } +static void wait_ap_stopped(u32 ap_apicid, void *gp) +{ + u32 timeout; + timeout = wait_cpu_state(ap_apicid, F10_APSTATE_ASLEEP, F10_APSTATE_ASLEEP); + printk(BIOS_DEBUG, "* AP %02x", ap_apicid); + if (timeout) { + printk(BIOS_DEBUG, " timed out:%08x\n", timeout); + } else { + printk(BIOS_DEBUG, "stopped\n"); + } +} + +void wait_all_other_cores_stopped(u32 bsp_apicid) +{ + // all aps other than core0 + printk(BIOS_DEBUG, "stopped ap apicid: "); + for_each_ap(bsp_apicid, 2, -1, wait_ap_stopped, (void *)0); + printk(BIOS_DEBUG, "\n"); +} + static void enable_apic_ext_id(u32 node) { u32 val; diff --git a/src/include/cpu/amd/multicore.h b/src/include/cpu/amd/multicore.h index b3a8237..0ddf866 100644 --- a/src/include/cpu/amd/multicore.h +++ b/src/include/cpu/amd/multicore.h @@ -35,6 +35,7 @@ void amd_sibling_init(struct device *cpu); void wait_all_core0_started(void); void wait_all_other_cores_started(u32 bsp_apicid); void wait_all_aps_started(u32 bsp_apicid); +void wait_all_other_cores_stopped(uint32_t bsp_apicid); void allow_all_aps_stop(u32 bsp_apicid); #endif u32 get_initial_apicid(void);

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Patch set updated for coreboot: mainboard/asus/kgpe-d16: Reenable power LED after S3 resume
by Timothy Pearson 30 Jan '16

30 Jan '16

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13171 -gerrit commit 53e451ba4a1a3ca9c408243e12c969b6296b783a Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Tue Nov 24 14:12:06 2015 -0600 mainboard/asus/kgpe-d16: Reenable power LED after S3 resume Change-Id: I958990f3203d3cbe7ae64833800d631c1034327f Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/mainboard/asus/kgpe-d16/acpi/pm_ctrl.asl | 7 +------ 1 file changed, 1 insertion(+), 6 deletions(-) diff --git a/src/mainboard/asus/kgpe-d16/acpi/pm_ctrl.asl b/src/mainboard/asus/kgpe-d16/acpi/pm_ctrl.asl index b5a7ed9..658d877 100644 --- a/src/mainboard/asus/kgpe-d16/acpi/pm_ctrl.asl +++ b/src/mainboard/asus/kgpe-d16/acpi/pm_ctrl.asl @@ -218,7 +218,7 @@ Method(\_WAK, 1) { /* Set up LEDs */ /* Set power LED to steady on */ - Store(0x3, BLNK) + Store(0x0, BLNK) /* Configure SuperIO for wake */ /* Access SuperIO ACPI device */ @@ -291,11 +291,6 @@ Method(\_PTS, 1) { /* Set suspend LED to 0.25Hz toggle pulse with 50% duty cycle */ Store(0x2, BLNK) } - if (LEqual(Arg0, 0x3)) /* Power state S3 requested */ - { - /* Set suspend LED to 0.25Hz toggle pulse with 25% duty cycle */ - Store(0x1, BLNK) - } /* Configure SuperIO for sleep */ /* Access SuperIO ACPI device */

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coreboot-gerrit January 2016