coreboot-gerrit January 2016

coreboot-gerrit@coreboot.org

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Patch merged into coreboot/master: kconfig_lint: merge 'git grep' and 'grep' exclude dir and files
by gerrit＠coreboot.org 30 Jan '16

30 Jan '16

the following patch was just integrated into master: commit 63ea4930e4ea127a317268de58371848944880a2 Author: Martin Roth <martinroth(a)google.com> Date: Mon Jan 25 16:08:27 2016 -0700 kconfig_lint: merge 'git grep' and 'grep' exclude dir and files The code had originally been using standard grep to look through the coreboot tree for Kconfig symbols. When this was switched to git grep, the --exclude-dir options didn't work, and nothing was added to exclude the directories that shouldn't be searched for symbols. This resulted in invalid warnings as it searched directories that had Kconfig symbols for other projects. This merges the exclusion list for both the regular and git versions of grep for consistent behavior. Change-Id: I69a1e0b30fecca152e02a511c82248b6091b3d8b Signed-off-by: Martin Roth <martinroth(a)google.com> Reviewed-on: https://review.coreboot.org/13456 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See https://review.coreboot.org/13456 for details. -gerrit

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Patch set updated for coreboot: buildgcc: Add GNU make to reference toolchain
by Stefan Reinauer 30 Jan '16

30 Jan '16

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13519 -gerrit commit 6d471ec67ec35f7023d0082c40659b22a3d8ea62 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Fri Jan 29 18:03:26 2016 -0800 buildgcc: Add GNU make to reference toolchain Change-Id: I8a41065880c3fd1f95ee8877031bf1738aaae859 Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- util/crossgcc/buildgcc | 19 ++++++++++++++++++- 1 file changed, 18 insertions(+), 1 deletion(-) diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index 590c15a..8f67949 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -44,6 +44,7 @@ PYTHON_VERSION=3.4.3 EXPAT_VERSION=2.1.0 # CLANG version number CLANG_VERSION=3.7.1 +MAKE_VERSION=4.1 # GCC toolchain archive locations GMP_ARCHIVE="http://ftpmirror.gnu.org/gmp/gmp-${GMP_VERSION}.tar.bz2" @@ -61,6 +62,7 @@ LLVM_ARCHIVE="http://llvm.org/releases/${CLANG_VERSION}/llvm-${CLANG_VERSION}.sr CFE_ARCHIVE="http://llvm.org/releases/${CLANG_VERSION}/cfe-${CLANG_VERSION}.src.tar.xz" CRT_ARCHIVE="http://llvm.org/releases/${CLANG_VERSION}/compiler-rt-${CLANG_VERSION}.src.…" CTE_ARCHIVE="http://llvm.org/releases/${CLANG_VERSION}/clang-tools-extra-${CLANG_VERSION…" +MAKE_ARCHIVE="http://ftpmirror.gnu.org/make/make-${MAKE_VERSION}.tar.bz2" # GCC toolchain directories GMP_DIR="gmp-${GMP_VERSION}" @@ -78,6 +80,7 @@ LLVM_DIR="llvm-${CLANG_VERSION}.src" CFE_DIR="cfe-${CLANG_VERSION}.src" CRT_DIR="compiler-rt-${CLANG_VERSION}.src" CTE_DIR="clang-tools-extra-${CLANG_VERSION}.src" +MAKE_DIR="make-${MAKE_VERSION}" unset MAKELEVEL MAKEFLAGS @@ -520,6 +523,15 @@ build_LLVM() { done } +build_MAKE() { + CC="$CC" CFLAGS="$HOSTCFLAGS" ../${MAKE_DIR}/configure --prefix=$TARGETDIR \ + --disable-nls || touch .failed + $MAKE $JOBS || touch .failed + $MAKE install DESTDIR=$DESTDIR || touch .failed + + normalize_dirs +} + print_stable() { case "$PRINTSTABLE" in AUTOCONF|autoconf) printf "%s\n" "$GCC_AUTOCONF_VERSION";; @@ -534,6 +546,7 @@ print_stable() { MPC|mpc) printf "%s\n" "$MPC_VERSION";; MPFR|mpfr) printf "%s\n" "$MPFR_VERSION";; PYTHON|python) printf "%s\n" "$PYTHON_VERSION";; + MAKE|make) printf "%s\n" "$MAKE_VERSION";; *) printf "Unknown tool %s\n" "$PRINTSTABLE";; esac } @@ -626,8 +639,12 @@ case "$PACKAGE" in NAME="IASL ACPI compiler" PACKAGES=IASL ;; + MAKE|make) + NAME="GNU Make" + PACKAGES=MAKE + ;; *) - printf "${red}ERROR: Unsupported package $PACKAGE. (Supported packages are GCC, GDB, CLANG, IASL)${NC}\n\n"; + printf "${red}ERROR: Unsupported package $PACKAGE. (Supported packages are GCC, GDB, CLANG, IASL, MAKE)${NC}\n\n"; exit 1 ;; esac

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Patch set updated for coreboot: buildgcc: Move all toolchain build targets to util/crossgcc
by Stefan Reinauer 30 Jan '16

30 Jan '16

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13518 -gerrit commit 2b86456c7972fe67c3c182567d8f7063d24a4333 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Fri Jan 29 17:48:47 2016 -0800 buildgcc: Move all toolchain build targets to util/crossgcc There is a lot of potential to completely get rid of Makefile and keep everything in Makefile.inc, but for now this declutters the main Makefile.inc Change-Id: I653313c74207f955514c036c81efcbfd988827c9 Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- Makefile.inc | 88 +-------------------------------------- util/crossgcc/Makefile.inc | 101 +++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 103 insertions(+), 86 deletions(-) diff --git a/Makefile.inc b/Makefile.inc index fba271d..52a63c0 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -471,95 +471,11 @@ gitconfig: git config remote.origin.push HEAD:refs/for/master (git config --global user.name >/dev/null && git config --global user.email >/dev/null) || (printf 'Please configure your name and email in git:\n\n git config --global user.name "Your Name Comes Here"\n git config --global user.email your.email(a)example.com\n'; exit 1) -help_toolchain help:: - @echo '*** Toolchain targets ***' - @echo ' crossgcc - Build coreboot cross-compilers for all platforms' - @echo ' crosstools - Build coreboot cross-compiler and GDB for all platforms' - @echo ' crossgcc-clean - Remove all built coreboot cross-compilers' - @echo ' iasl - Build coreboot IASL compiler (built by all cross targets)' - @echo ' clang - Build coreboot clang compiler' - @echo ' test-toolchain - Reports if toolchain components are out of date' - @echo ' crossgcc-ARCH - Build cross-compiler for specific architecture' - @echo ' crosstools-ARCH - Build cross-compiler with GDB for specific architecture' - @echo ' ARCH can be "i386", "x64", "arm", "aarch64", "mips", "riscv", or "power8"' - @echo ' Use "make [target] CPUS=#" to build toolchain using multiple cores' - @echo - -# For the toolchain builds, use CPUS=x to use multiple processors to build -# use BUILDGCC_OPTIONS= to set any crossgcc command line options -# Example: BUILDGCC_OPTIONS='-t' will keep temporary files after build -crossgcc: clean-for-update - $(MAKE) -C util/crossgcc all_without_gdb SKIP_CLANG=1 - -.PHONY: crossgcc crossgcc-i386 crossgcc-x64 crossgcc-arm crossgcc-aarch64 \ - crossgcc-mips crossgcc-riscv crossgcc-power8 crossgcc-clean iasl \ - clang tools crosstools-i386 crosstools-x64 crosstools-arm \ - crosstools-aarch64 crosstools-mips crosstools-riscv crosstools-power8 - -crossgcc-i386: clean-for-update - $(MAKE) -C util/crossgcc build-i386 SKIP_GDB=1 - -crossgcc-x64: clean-for-update - $(MAKE) -C util/crossgcc build-x64 SKIP_GDB=1 - -crossgcc-arm: clean-for-update - $(MAKE) -C util/crossgcc build-arm SKIP_GDB=1 - -crossgcc-aarch64: clean-for-update - $(MAKE) -C util/crossgcc build-aarch64 SKIP_GDB=1 - -crossgcc-mips: clean-for-update - $(MAKE) -C util/crossgcc build-mips SKIP_GDB=1 - -crossgcc-riscv: clean-for-update - $(MAKE) -C util/crossgcc build-riscv SKIP_GDB=1 - -crossgcc-power8: clean-for-update - $(MAKE) -C util/crossgcc build-power8 SKIP_GDB=1 - -crosstools: clean-for-update - $(MAKE) -C util/crossgcc all_with_gdb SKIP_CLANG=1 - -iasl: clean-for-update - $(MAKE) -C util/crossgcc build_iasl - -clang: clean-for-update - $(MAKE) -C util/crossgcc build_clang - -crosstools-i386: clean-for-update - $(MAKE) -C util/crossgcc build-i386 - -crosstools-x64: clean-for-update - $(MAKE) -C util/crossgcc build-x64 - -crosstools-arm: clean-for-update - $(MAKE) -C util/crossgcc build-arm - -crosstools-aarch64: clean-for-update - $(MAKE) -C util/crossgcc build-aarch64 - -crosstools-mips: clean-for-update - $(MAKE) -C util/crossgcc build-mips - -crosstools-riscv: clean-for-update - $(MAKE) -C util/crossgcc build-riscv - -crosstools-power8: clean-for-update - $(MAKE) -C util/crossgcc build-power8 - -crossgcc-clean: clean-for-update - $(MAKE) -C util/crossgcc clean +include util/crossgcc/Makefile.inc +.PHONY: tools tools: $(objutil)/kconfig/conf $(CBFSTOOL) $(FMAPTOOL) $(RMODTOOL) $(objutil)/nvramtool/nvramtool $(ROMCC_BIN) $(objutil)/sconfig/sconfig $(IFDTOOL) $(IFDFAKE) $(CBOOTIMAGE) $(AMDFWTOOL) -test-toolchain: -ifeq ($(COMPILER_OUT_OF_DATE),1) - echo "The coreboot toolchain is not the current version." - $(error ) -else - echo "The coreboot toolchain is the current version." -endif # ifeq ($(COMPILER_OUT_OF_DATE),1) - ########################################################################### # Common recipes for all stages ########################################################################### diff --git a/util/crossgcc/Makefile.inc b/util/crossgcc/Makefile.inc new file mode 100644 index 0000000..04eb70b --- /dev/null +++ b/util/crossgcc/Makefile.inc @@ -0,0 +1,101 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2016 Google Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +help_toolchain help:: + @echo '*** Toolchain targets ***' + @echo ' crossgcc - Build coreboot cross-compilers for all platforms' + @echo ' crosstools - Build coreboot cross-compiler and GDB for all platforms' + @echo ' crossgcc-clean - Remove all built coreboot cross-compilers' + @echo ' iasl - Build coreboot IASL compiler (built by all cross targets)' + @echo ' clang - Build coreboot clang compiler' + @echo ' test-toolchain - Reports if toolchain components are out of date' + @echo ' crossgcc-ARCH - Build cross-compiler for specific architecture' + @echo ' crosstools-ARCH - Build cross-compiler with GDB for specific architecture' + @echo ' ARCH can be "i386", "x64", "arm", "aarch64", "mips", "riscv", or "power8"' + @echo ' Use "make [target] CPUS=#" to build toolchain using multiple cores' + @echo + +# For the toolchain builds, use CPUS=x to use multiple processors to build +# use BUILDGCC_OPTIONS= to set any crossgcc command line options +# Example: BUILDGCC_OPTIONS='-t' will keep temporary files after build +crossgcc: clean-for-update + $(MAKE) -C util/crossgcc all_without_gdb SKIP_CLANG=1 + +.PHONY: crossgcc crossgcc-i386 crossgcc-x64 crossgcc-arm crossgcc-aarch64 \ + crossgcc-mips crossgcc-riscv crossgcc-power8 crossgcc-clean iasl \ + clang crosstools-i386 crosstools-x64 crosstools-arm \ + crosstools-aarch64 crosstools-mips crosstools-riscv crosstools-power8 + +crossgcc-i386: clean-for-update + $(MAKE) -C util/crossgcc build-i386 SKIP_GDB=1 + +crossgcc-x64: clean-for-update + $(MAKE) -C util/crossgcc build-x64 SKIP_GDB=1 + +crossgcc-arm: clean-for-update + $(MAKE) -C util/crossgcc build-arm SKIP_GDB=1 + +crossgcc-aarch64: clean-for-update + $(MAKE) -C util/crossgcc build-aarch64 SKIP_GDB=1 + +crossgcc-mips: clean-for-update + $(MAKE) -C util/crossgcc build-mips SKIP_GDB=1 + +crossgcc-riscv: clean-for-update + $(MAKE) -C util/crossgcc build-riscv SKIP_GDB=1 + +crossgcc-power8: clean-for-update + $(MAKE) -C util/crossgcc build-power8 SKIP_GDB=1 + +crosstools: clean-for-update + $(MAKE) -C util/crossgcc all_with_gdb SKIP_CLANG=1 + +iasl: clean-for-update + $(MAKE) -C util/crossgcc build_iasl + +clang: clean-for-update + $(MAKE) -C util/crossgcc build_clang + +crosstools-i386: clean-for-update + $(MAKE) -C util/crossgcc build-i386 + +crosstools-x64: clean-for-update + $(MAKE) -C util/crossgcc build-x64 + +crosstools-arm: clean-for-update + $(MAKE) -C util/crossgcc build-arm + +crosstools-aarch64: clean-for-update + $(MAKE) -C util/crossgcc build-aarch64 + +crosstools-mips: clean-for-update + $(MAKE) -C util/crossgcc build-mips + +crosstools-riscv: clean-for-update + $(MAKE) -C util/crossgcc build-riscv + +crosstools-power8: clean-for-update + $(MAKE) -C util/crossgcc build-power8 + +crossgcc-clean: clean-for-update + $(MAKE) -C util/crossgcc clean + +test-toolchain: +ifeq ($(COMPILER_OUT_OF_DATE),1) + echo "The coreboot toolchain is not the current version." + $(error ) +else + echo "The coreboot toolchain is the current version." +endif # ifeq ($(COMPILER_OUT_OF_DATE),1)

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Patch set updated for coreboot: buildgcc: clean up Makefile
by Stefan Reinauer 30 Jan '16

30 Jan '16

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13517 -gerrit commit 85ac69d09aa06a0187df6d3acea891bdd2ce4402 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Fri Jan 29 17:39:07 2016 -0800 buildgcc: clean up Makefile * Drop SKIP_IASL variable which is a leftover from when IASL was built automatically * Rename ARM target armv7a -> arm * all builds a nds32le compiler needed for some EC work Change-Id: Ia4f67abcffdfe9c56c5d1848c75dfea83755e755 Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- Makefile.inc | 4 ++-- util/crossgcc/Makefile | 31 +++++++++++++++---------------- 2 files changed, 17 insertions(+), 18 deletions(-) diff --git a/Makefile.inc b/Makefile.inc index 583e59a..fba271d 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -503,7 +503,7 @@ crossgcc-x64: clean-for-update $(MAKE) -C util/crossgcc build-x64 SKIP_GDB=1 crossgcc-arm: clean-for-update - $(MAKE) -C util/crossgcc build-armv7a SKIP_GDB=1 + $(MAKE) -C util/crossgcc build-arm SKIP_GDB=1 crossgcc-aarch64: clean-for-update $(MAKE) -C util/crossgcc build-aarch64 SKIP_GDB=1 @@ -533,7 +533,7 @@ crosstools-x64: clean-for-update $(MAKE) -C util/crossgcc build-x64 crosstools-arm: clean-for-update - $(MAKE) -C util/crossgcc build-armv7a + $(MAKE) -C util/crossgcc build-arm crosstools-aarch64: clean-for-update $(MAKE) -C util/crossgcc build-aarch64 diff --git a/util/crossgcc/Makefile b/util/crossgcc/Makefile index 79e0c3c..11cc5fc 100644 --- a/util/crossgcc/Makefile +++ b/util/crossgcc/Makefile @@ -7,18 +7,16 @@ BUILD_PLATFORM ?= i386-elf # Example: BUILDGCC_OPTIONS=-c to remove temporary files before build all all_with_gdb: - $(MAKE) build-i386 - $(MAKE) SKIP_IASL=1 \ - build-x64 build-armv7a build-mips build-riscv build-aarch64 \ - build_clang + $(MAKE) build-i386 build-x64 build-arm build-mips \ + build-riscv build-aarch64 build-power8 build-nds32le \ + build_clang build_iasl all_without_gdb: - $(MAKE) SKIP_GDB=1 build-i386 - $(MAKE) SKIP_IASL=1 SKIP_GDB=1 \ - build-x64 build-armv7a build-mips build-riscv build-aarch64 \ - build_clang + $(MAKE) SKIP_GDB=1 build-i386 build-x64 build-arm build-mips \ + build-riscv build-aarch64 build-power8 build-nds32le \ + build_clang build_iasl -build_tools: build_gcc build_iasl build_gdb +build_tools: build_gcc build_gdb ########################################################### ### targets to do buildgcc builds @@ -33,9 +31,7 @@ ifeq ($(SKIP_GDB),) endif build_iasl: -ifeq ($(SKIP_IASL),) bash ./buildgcc -P iasl $(if $(CPUS),-j $(CPUS)) $(if $(KEEP_SOURCES),-t) $(BUILDGCC_OPTIONS) -endif build_clang: ifeq ($(SKIP_CLANG),) @@ -49,8 +45,8 @@ build-i386: build-x64: @$(MAKE) build_tools BUILD_PLATFORM=x86_64-elf -build-armv7a: - @$(MAKE) build_tools BUILD_PLATFORM=armv7a-eabi +build-arm: + @$(MAKE) build_tools BUILD_PLATFORM=arm-eabi build-aarch64: @$(MAKE) build_tools BUILD_PLATFORM=aarch64-elf @@ -64,6 +60,9 @@ build-riscv: build-power8: @$(MAKE) build_tools BUILD_PLATFORM=powerpc64le-linux-gnu +build-nds32le: + @$(MAKE) build_tools BUILD_PLATFORM=nds32le-elf + clean_tempfiles: rm -rf build-* rm -rf binutils-* gcc-* gmp-* libelf-* mpc-* mpfr-* @@ -78,7 +77,7 @@ clean: clean_tempfiles distclean: clean rm -rf tarballs -.PHONY: build_gcc build_iasl build_gdb build_clang \ - all all_with_gdb all_without_gdb build_tools \ - build-i386 build-x64 build-armv7a build-aarch64 build-mips build-riscv build-power8 \ +.PHONY: build_gcc build_iasl build_gdb build_clang all all_with_gdb \ + all_without_gdb build_tools build-i386 build-x64 build-arm \ + build-aarch64 build-mips build-riscv build-power8 build-nds32le \ clean distclean clean_tempfiles

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Patch set updated for coreboot: buildgcc: clean up Makefile
by Stefan Reinauer 30 Jan '16

30 Jan '16

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13517 -gerrit commit ffebc77c9b3b1955066168b7929ec1056395ef0b Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Fri Jan 29 17:39:07 2016 -0800 buildgcc: clean up Makefile * Drop SKIP_IASL variable which is a leftover from when IASL was built automatically * Rename ARM target armv7a -> arm * all builds a nds32le compiler needed for some EC work Change-Id: Ia4f67abcffdfe9c56c5d1848c75dfea83755e755 Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- Makefile.inc | 4 ++-- util/crossgcc/Makefile | 31 +++++++++++++++---------------- 2 files changed, 17 insertions(+), 18 deletions(-) diff --git a/Makefile.inc b/Makefile.inc index 583e59a..fba271d 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -503,7 +503,7 @@ crossgcc-x64: clean-for-update $(MAKE) -C util/crossgcc build-x64 SKIP_GDB=1 crossgcc-arm: clean-for-update - $(MAKE) -C util/crossgcc build-armv7a SKIP_GDB=1 + $(MAKE) -C util/crossgcc build-arm SKIP_GDB=1 crossgcc-aarch64: clean-for-update $(MAKE) -C util/crossgcc build-aarch64 SKIP_GDB=1 @@ -533,7 +533,7 @@ crosstools-x64: clean-for-update $(MAKE) -C util/crossgcc build-x64 crosstools-arm: clean-for-update - $(MAKE) -C util/crossgcc build-armv7a + $(MAKE) -C util/crossgcc build-arm crosstools-aarch64: clean-for-update $(MAKE) -C util/crossgcc build-aarch64 diff --git a/util/crossgcc/Makefile b/util/crossgcc/Makefile index 79e0c3c..11cc5fc 100644 --- a/util/crossgcc/Makefile +++ b/util/crossgcc/Makefile @@ -7,18 +7,16 @@ BUILD_PLATFORM ?= i386-elf # Example: BUILDGCC_OPTIONS=-c to remove temporary files before build all all_with_gdb: - $(MAKE) build-i386 - $(MAKE) SKIP_IASL=1 \ - build-x64 build-armv7a build-mips build-riscv build-aarch64 \ - build_clang + $(MAKE) build-i386 build-x64 build-arm build-mips \ + build-riscv build-aarch64 build-power8 build-nds32le \ + build_clang build_iasl all_without_gdb: - $(MAKE) SKIP_GDB=1 build-i386 - $(MAKE) SKIP_IASL=1 SKIP_GDB=1 \ - build-x64 build-armv7a build-mips build-riscv build-aarch64 \ - build_clang + $(MAKE) SKIP_GDB=1 build-i386 build-x64 build-arm build-mips \ + build-riscv build-aarch64 build-power8 build-nds32le \ + build_clang build_iasl -build_tools: build_gcc build_iasl build_gdb +build_tools: build_gcc build_gdb ########################################################### ### targets to do buildgcc builds @@ -33,9 +31,7 @@ ifeq ($(SKIP_GDB),) endif build_iasl: -ifeq ($(SKIP_IASL),) bash ./buildgcc -P iasl $(if $(CPUS),-j $(CPUS)) $(if $(KEEP_SOURCES),-t) $(BUILDGCC_OPTIONS) -endif build_clang: ifeq ($(SKIP_CLANG),) @@ -49,8 +45,8 @@ build-i386: build-x64: @$(MAKE) build_tools BUILD_PLATFORM=x86_64-elf -build-armv7a: - @$(MAKE) build_tools BUILD_PLATFORM=armv7a-eabi +build-arm: + @$(MAKE) build_tools BUILD_PLATFORM=arm-eabi build-aarch64: @$(MAKE) build_tools BUILD_PLATFORM=aarch64-elf @@ -64,6 +60,9 @@ build-riscv: build-power8: @$(MAKE) build_tools BUILD_PLATFORM=powerpc64le-linux-gnu +build-nds32le: + @$(MAKE) build_tools BUILD_PLATFORM=nds32le-elf + clean_tempfiles: rm -rf build-* rm -rf binutils-* gcc-* gmp-* libelf-* mpc-* mpfr-* @@ -78,7 +77,7 @@ clean: clean_tempfiles distclean: clean rm -rf tarballs -.PHONY: build_gcc build_iasl build_gdb build_clang \ - all all_with_gdb all_without_gdb build_tools \ - build-i386 build-x64 build-armv7a build-aarch64 build-mips build-riscv build-power8 \ +.PHONY: build_gcc build_iasl build_gdb build_clang all all_with_gdb \ + all_without_gdb build_tools build-i386 build-x64 build-arm \ + build-aarch64 build-mips build-riscv build-power8 build-nds32le \ clean distclean clean_tempfiles

1 0

Patch set updated for coreboot: buildgcc: Update LLVM to 3.7.1
by Stefan Reinauer 30 Jan '16

30 Jan '16

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13516 -gerrit commit 57422d152e540124dcff35098ceec961e482bb20 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Fri Jan 29 17:33:56 2016 -0800 buildgcc: Update LLVM to 3.7.1 Not much testing, update mostly so we can test with the latest scan-build. Change-Id: I50d28b7e0dfd31f9ae565c8515d5ab1760ca4c62 Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- util/crossgcc/buildgcc | 6 +- util/crossgcc/patches/cfe-3.6.1.src_frontend.patch | 79 ---------------------- util/crossgcc/patches/cfe-3.7.1.src_frontend.patch | 79 ++++++++++++++++++++++ util/crossgcc/sum/cfe-3.6.1.src.tar.xz.cksum | 1 - util/crossgcc/sum/cfe-3.7.1.src.tar.xz.cksum | 1 + .../sum/clang-tools-extra-3.6.1.src.tar.xz.cksum | 1 - .../sum/clang-tools-extra-3.7.1.src.tar.xz.cksum | 1 + .../sum/compiler-rt-3.6.1.src.tar.xz.cksum | 1 - .../sum/compiler-rt-3.7.1.src.tar.xz.cksum | 1 + util/crossgcc/sum/llvm-3.6.1.src.tar.xz.cksum | 1 - util/crossgcc/sum/llvm-3.7.1.src.tar.xz.cksum | 1 + 11 files changed, 86 insertions(+), 86 deletions(-) diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index 3c6a606..590c15a 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -18,8 +18,8 @@ cd $(dirname $0) -CROSSGCC_DATE="November 25th, 2015" -CROSSGCC_VERSION="1.33" +CROSSGCC_DATE="January 29th, 2016" +CROSSGCC_VERSION="1.35" # default settings PACKAGE=GCC @@ -43,7 +43,7 @@ IASL_VERSION=20150619 PYTHON_VERSION=3.4.3 EXPAT_VERSION=2.1.0 # CLANG version number -CLANG_VERSION=3.6.1 +CLANG_VERSION=3.7.1 # GCC toolchain archive locations GMP_ARCHIVE="http://ftpmirror.gnu.org/gmp/gmp-${GMP_VERSION}.tar.bz2" diff --git a/util/crossgcc/patches/cfe-3.6.1.src_frontend.patch b/util/crossgcc/patches/cfe-3.6.1.src_frontend.patch deleted file mode 100644 index d69cb44..0000000 --- a/util/crossgcc/patches/cfe-3.6.1.src_frontend.patch +++ /dev/null @@ -1,79 +0,0 @@ -Frontend driver patch from Edward O'Callaghan - -https://llvm.org/bugs/show_bug.cgi?id=21538 - -Index: include/clang/Driver/Driver.h -=================================================================== ---- cfe-3.6.1.src/include/clang/Driver/Driver.h (revision 211898) -+++ cfe-3.6.1.src/include/clang/Driver/Driver.h (working copy) -@@ -325,6 +325,14 @@ - // FIXME: This should be in CompilationInfo. - std::string GetFilePath(const char *Name, const ToolChain &TC) const; - -+ /// GetCompilerRTPath - Find Compiler-RT library path -+ /// -+ /// \param TC - The provided tool chain for additional information on -+ /// directories to search. -+ // -+ // FIXME: This should be in CompilationInfo. -+ std::string GetCompilerRTPath(const ToolChain &TC) const; -+ - /// GetProgramPath - Lookup \p Name in the list of program search paths. - /// - /// \param TC - The provided tool chain for additional information on -Index: include/clang/Driver/Options.td -=================================================================== ---- cfe-3.6.1.src/include/clang/Driver/Options.td (revision 211898) -+++ cfe-3.6.1.src/include/clang/Driver/Options.td (working copy) -@@ -1269,6 +1269,8 @@ - HelpText<"Enable Objective-C Ivar layout bitmap print trace">; - def print_libgcc_file_name : Flag<["-", "--"], "print-libgcc-file-name">, - HelpText<"Print the library path for \"libgcc.a\"">; -+def print_librt_file_name : Flag<["-", "--"], "print-librt-file-name">, -+ HelpText<"Print the library path for \"libclang_rt.builtins-ARCH.a\"">; - def print_multi_directory : Flag<["-", "--"], "print-multi-directory">; - def print_multi_lib : Flag<["-", "--"], "print-multi-lib">; - def print_multi_os_directory : Flag<["-", "--"], "print-multi-os-directory">; -Index: lib/Driver/Driver.cpp -=================================================================== ---- cfe-3.6.1.src/lib/Driver/Driver.cpp (revision 211898) -+++ cfe-3.6.1.src/lib/Driver/Driver.cpp (working copy) -@@ -756,6 +756,11 @@ - return false; - } - -+ if (C.getArgs().hasArg(options::OPT_print_librt_file_name)) { -+ llvm::outs() << GetCompilerRTPath(TC) << "\n"; -+ return false; -+ } -+ - if (C.getArgs().hasArg(options::OPT_print_multi_lib)) { - const MultilibSet &Multilibs = TC.getMultilibs(); - -@@ -1820,6 +1825,26 @@ - return Name; - } - -+std::string Driver::GetCompilerRTPath(const ToolChain &TC) const { -+ // The runtimes are located in the OS-specific resource directory. -+ SmallString<128> Res(TC.getDriver().ResourceDir); -+ const llvm::Triple &Triple = TC.getTriple(); -+ -+ // TC.getOS() yield "freebsd10.0" whereas "freebsd" is expected. -+ StringRef OSLibName = (Triple.getOS() == llvm::Triple::FreeBSD) ? -+ "freebsd" : TC.getOS(); -+ llvm::sys::path::append(Res, "lib", OSLibName); -+ -+ StringRef archName = TC.getArchName(); -+ // Until ARM libraries are build separately, we have them all in one library -+ if (TC.getArch() == llvm::Triple::arm || -+ TC.getArch() == llvm::Triple::armeb) -+ archName = "arm"; -+ -+ llvm::sys::path::append(Res, Twine("libclang_rt.builtins-") + archName + ".a"); -+ return Res.str(); -+} -+ - std::string Driver::GetProgramPath(const char *Name, - const ToolChain &TC) const { - // FIXME: Needs a better variable than DefaultTargetTriple diff --git a/util/crossgcc/patches/cfe-3.7.1.src_frontend.patch b/util/crossgcc/patches/cfe-3.7.1.src_frontend.patch new file mode 100644 index 0000000..781878d --- /dev/null +++ b/util/crossgcc/patches/cfe-3.7.1.src_frontend.patch @@ -0,0 +1,79 @@ +Frontend driver patch from Edward O'Callaghan + +https://llvm.org/bugs/show_bug.cgi?id=21538 + +Index: include/clang/Driver/Driver.h +=================================================================== +--- cfe-3.7.1.src/include/clang/Driver/Driver.h (revision 211898) ++++ cfe-3.7.1.src/include/clang/Driver/Driver.h (working copy) +@@ -325,6 +325,14 @@ + // FIXME: This should be in CompilationInfo. + std::string GetFilePath(const char *Name, const ToolChain &TC) const; + ++ /// GetCompilerRTPath - Find Compiler-RT library path ++ /// ++ /// \param TC - The provided tool chain for additional information on ++ /// directories to search. ++ // ++ // FIXME: This should be in CompilationInfo. ++ std::string GetCompilerRTPath(const ToolChain &TC) const; ++ + /// GetProgramPath - Lookup \p Name in the list of program search paths. + /// + /// \param TC - The provided tool chain for additional information on +Index: include/clang/Driver/Options.td +=================================================================== +--- cfe-3.7.1.src/include/clang/Driver/Options.td (revision 211898) ++++ cfe-3.7.1.src/include/clang/Driver/Options.td (working copy) +@@ -1269,6 +1269,8 @@ + HelpText<"Enable Objective-C Ivar layout bitmap print trace">; + def print_libgcc_file_name : Flag<["-", "--"], "print-libgcc-file-name">, + HelpText<"Print the library path for \"libgcc.a\"">; ++def print_librt_file_name : Flag<["-", "--"], "print-librt-file-name">, ++ HelpText<"Print the library path for \"libclang_rt.builtins-ARCH.a\"">; + def print_multi_directory : Flag<["-", "--"], "print-multi-directory">; + def print_multi_lib : Flag<["-", "--"], "print-multi-lib">; + def print_multi_os_directory : Flag<["-", "--"], "print-multi-os-directory">; +Index: lib/Driver/Driver.cpp +=================================================================== +--- cfe-3.7.1.src/lib/Driver/Driver.cpp (revision 211898) ++++ cfe-3.7.1.src/lib/Driver/Driver.cpp (working copy) +@@ -756,6 +756,11 @@ + return false; + } + ++ if (C.getArgs().hasArg(options::OPT_print_librt_file_name)) { ++ llvm::outs() << GetCompilerRTPath(TC) << "\n"; ++ return false; ++ } ++ + if (C.getArgs().hasArg(options::OPT_print_multi_lib)) { + const MultilibSet &Multilibs = TC.getMultilibs(); + +@@ -1820,6 +1825,26 @@ + return Name; + } + ++std::string Driver::GetCompilerRTPath(const ToolChain &TC) const { ++ // The runtimes are located in the OS-specific resource directory. ++ SmallString<128> Res(TC.getDriver().ResourceDir); ++ const llvm::Triple &Triple = TC.getTriple(); ++ ++ // TC.getOS() yield "freebsd10.0" whereas "freebsd" is expected. ++ StringRef OSLibName = (Triple.getOS() == llvm::Triple::FreeBSD) ? ++ "freebsd" : TC.getOS(); ++ llvm::sys::path::append(Res, "lib", OSLibName); ++ ++ StringRef archName = TC.getArchName(); ++ // Until ARM libraries are build separately, we have them all in one library ++ if (TC.getArch() == llvm::Triple::arm || ++ TC.getArch() == llvm::Triple::armeb) ++ archName = "arm"; ++ ++ llvm::sys::path::append(Res, Twine("libclang_rt.builtins-") + archName + ".a"); ++ return Res.str(); ++} ++ + std::string Driver::GetProgramPath(const char *Name, + const ToolChain &TC) const { + // FIXME: Needs a better variable than DefaultTargetTriple diff --git a/util/crossgcc/sum/cfe-3.6.1.src.tar.xz.cksum b/util/crossgcc/sum/cfe-3.6.1.src.tar.xz.cksum deleted file mode 100644 index 661bf9c..0000000 --- a/util/crossgcc/sum/cfe-3.6.1.src.tar.xz.cksum +++ /dev/null @@ -1 +0,0 @@ -b7221d8fdd27e3ed519d0281646e82e17b51122c tarballs/cfe-3.6.1.src.tar.xz diff --git a/util/crossgcc/sum/cfe-3.7.1.src.tar.xz.cksum b/util/crossgcc/sum/cfe-3.7.1.src.tar.xz.cksum new file mode 100644 index 0000000..57b4bf5 --- /dev/null +++ b/util/crossgcc/sum/cfe-3.7.1.src.tar.xz.cksum @@ -0,0 +1 @@ +15475a2c1e750a13755812785a4796cf4d9fa4c2 tarballs/cfe-3.7.1.src.tar.xz diff --git a/util/crossgcc/sum/clang-tools-extra-3.6.1.src.tar.xz.cksum b/util/crossgcc/sum/clang-tools-extra-3.6.1.src.tar.xz.cksum deleted file mode 100644 index 17d55cb..0000000 --- a/util/crossgcc/sum/clang-tools-extra-3.6.1.src.tar.xz.cksum +++ /dev/null @@ -1 +0,0 @@ -d93136f56999d8ae1ffebb9cd0cd7f3c27ba77c4 tarballs/clang-tools-extra-3.6.1.src.tar.xz diff --git a/util/crossgcc/sum/clang-tools-extra-3.7.1.src.tar.xz.cksum b/util/crossgcc/sum/clang-tools-extra-3.7.1.src.tar.xz.cksum new file mode 100644 index 0000000..49eea30 --- /dev/null +++ b/util/crossgcc/sum/clang-tools-extra-3.7.1.src.tar.xz.cksum @@ -0,0 +1 @@ +af7b0208d00be365849a923b16b8e6d0fca2a2fc tarballs/clang-tools-extra-3.7.1.src.tar.xz diff --git a/util/crossgcc/sum/compiler-rt-3.6.1.src.tar.xz.cksum b/util/crossgcc/sum/compiler-rt-3.6.1.src.tar.xz.cksum deleted file mode 100644 index 51e426b..0000000 --- a/util/crossgcc/sum/compiler-rt-3.6.1.src.tar.xz.cksum +++ /dev/null @@ -1 +0,0 @@ -85dccdc6ccd9675e871dfd2786b45fbf53518485 tarballs/compiler-rt-3.6.1.src.tar.xz diff --git a/util/crossgcc/sum/compiler-rt-3.7.1.src.tar.xz.cksum b/util/crossgcc/sum/compiler-rt-3.7.1.src.tar.xz.cksum new file mode 100644 index 0000000..fd007e9 --- /dev/null +++ b/util/crossgcc/sum/compiler-rt-3.7.1.src.tar.xz.cksum @@ -0,0 +1 @@ +8ad98fcc0bc801ba448c9bc43942fd3f545a6923 tarballs/compiler-rt-3.7.1.src.tar.xz diff --git a/util/crossgcc/sum/llvm-3.6.1.src.tar.xz.cksum b/util/crossgcc/sum/llvm-3.6.1.src.tar.xz.cksum deleted file mode 100644 index 5ca7065..0000000 --- a/util/crossgcc/sum/llvm-3.6.1.src.tar.xz.cksum +++ /dev/null @@ -1 +0,0 @@ -01ecab99adc9030ee34e9a2e19e65dfe64e1affe tarballs/llvm-3.6.1.src.tar.xz diff --git a/util/crossgcc/sum/llvm-3.7.1.src.tar.xz.cksum b/util/crossgcc/sum/llvm-3.7.1.src.tar.xz.cksum new file mode 100644 index 0000000..b63e707 --- /dev/null +++ b/util/crossgcc/sum/llvm-3.7.1.src.tar.xz.cksum @@ -0,0 +1 @@ +5dbdcafac105273dcbff94c68837a66c6dd78cef tarballs/llvm-3.7.1.src.tar.xz

1 0

New patch to review for coreboot: commonlib: move uefi includes out of commonlib includes
by Stefan Reinauer 30 Jan '16

30 Jan '16

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13526 -gerrit commit 47c579373b82174a14d279d6ed2cd7b4c35251d1 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Sat Jan 30 02:05:56 2016 -0800 commonlib: move uefi includes out of commonlib includes ... and move them into the code using them, instead. Change-Id: I2391234797ad00da8038dda198eadf0b0fcaedb2 Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- src/commonlib/fsp1_1_relocate.c | 14 ++++++++++++++ src/commonlib/include/commonlib/fsp1_1.h | 16 ---------------- 2 files changed, 14 insertions(+), 16 deletions(-) diff --git a/src/commonlib/fsp1_1_relocate.c b/src/commonlib/fsp1_1_relocate.c index 7165d86..501c08d 100644 --- a/src/commonlib/fsp1_1_relocate.c +++ b/src/commonlib/fsp1_1_relocate.c @@ -16,6 +16,20 @@ #include <console/console.h> #include <commonlib/endian.h> #include <commonlib/fsp1_1.h> +/* + * Intel's code does not have a handle on changing global packing state. + * Therefore, one needs to protect against packing policies that are set + * globally for a compliation unit just by including a header file. + */ +#pragma pack(push) + +/* Default bind FSP 1.1 API to edk2 UEFI 2.4 types. */ +#include <vendorcode/intel/edk2/uefi_2.4/uefi_types.h> +#include <vendorcode/intel/fsp/fsp1_1/IntelFspPkg/Include/FspInfoHeader.h> + +/* Restore original packing policy. */ +#pragma pack(pop) + #include <commonlib/helpers.h> #include <stdlib.h> #include <stdint.h> diff --git a/src/commonlib/include/commonlib/fsp1_1.h b/src/commonlib/include/commonlib/fsp1_1.h index 3e4fd3e..a5bc193 100644 --- a/src/commonlib/include/commonlib/fsp1_1.h +++ b/src/commonlib/include/commonlib/fsp1_1.h @@ -20,22 +20,6 @@ #include <stdint.h> /* - * Intel's code does not have a handle on changing global packing state. - * Therefore, one needs to protect against packing policies that are set - * globally for a compliation unit just by including a header file. - */ -#pragma pack(push) - -/* Default bind FSP 1.1 API to edk2 UEFI 2.4 types. */ -#include <vendorcode/intel/edk2/uefi_2.4/uefi_types.h> - -#include <vendorcode/intel/fsp/fsp1_1/IntelFspPkg/Include/FspApi.h> -#include <vendorcode/intel/fsp/fsp1_1/IntelFspPkg/Include/FspInfoHeader.h> - -/* Restore original packing policy. */ -#pragma pack(pop) - -/* * Relocate FSP held within buffer defined by size to new_addr. Returns < 0 * on error, offset to FSP_INFO_HEADER on success. */

1 0

New patch to review for coreboot: vendorcode/intel: remove unused apple specific assembler macros
by Stefan Reinauer 30 Jan '16

30 Jan '16

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13525 -gerrit commit df53a07478f286973c588accdd5d247c65067031 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Sat Jan 30 02:02:21 2016 -0800 vendorcode/intel: remove unused apple specific assembler macros Since this code is pulled in through commonlib, it will break compilation of cbfstool on OSX. Change-Id: I342bfa7e755aa540c4563bb5cd8cccacee39d188 Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- src/vendorcode/intel/edk2/uefi_2.4/MdePkg/Include/Base.h | 10 ---------- src/vendorcode/intel/edk2/uefi_2.4/uefi_types.h | 1 - 2 files changed, 11 deletions(-) diff --git a/src/vendorcode/intel/edk2/uefi_2.4/MdePkg/Include/Base.h b/src/vendorcode/intel/edk2/uefi_2.4/MdePkg/Include/Base.h index e403ebd..b7dc94d 100644 --- a/src/vendorcode/intel/edk2/uefi_2.4/MdePkg/Include/Base.h +++ b/src/vendorcode/intel/edk2/uefi_2.4/MdePkg/Include/Base.h @@ -94,16 +94,6 @@ VERIFY_SIZE_OF (CHAR16, 2); /// #define ASM_PFX(name) _CONCATENATE (__USER_LABEL_PREFIX__, name) -#if __APPLE__ - // - // Apple extension that is used by the linker to optimize code size - // with assembly functions. Put at the end of your .S files - // - #define ASM_FUNCTION_REMOVE_IF_UNREFERENCED .subsections_via_symbols -#else - #define ASM_FUNCTION_REMOVE_IF_UNREFERENCED -#endif - #ifdef __CC_ARM // // Older RVCT ARM compilers don't fully support #pragma pack and require __packed diff --git a/src/vendorcode/intel/edk2/uefi_2.4/uefi_types.h b/src/vendorcode/intel/edk2/uefi_2.4/uefi_types.h index e68f8c9..910730b 100644 --- a/src/vendorcode/intel/edk2/uefi_2.4/uefi_types.h +++ b/src/vendorcode/intel/edk2/uefi_2.4/uefi_types.h @@ -34,7 +34,6 @@ are permitted provided that the following conditions are met: // // Set the UEFI types and attributes // -#define __APPLE__ 0 #include <stdlib.h> #include <Uefi/UefiBaseType.h> #include <Pi/PiBootMode.h>

1 0

New patch to review for coreboot: crossgcc/Makefile.inc: deduplicate cross*-$arch rules
by Patrick Georgi 30 Jan '16

30 Jan '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13524 -gerrit commit 022020e42865e231fe10028964f73c400180c7d3 Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Sat Jan 30 09:14:45 2016 +0100 crossgcc/Makefile.inc: deduplicate cross*-$arch rules Change-Id: Idee4eb5d112e3f6bffced0681e9112101bed6763 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> --- util/crossgcc/Makefile.inc | 48 +++++++--------------------------------------- 1 file changed, 7 insertions(+), 41 deletions(-) diff --git a/util/crossgcc/Makefile.inc b/util/crossgcc/Makefile.inc index 04eb70b..bd1b0cd 100644 --- a/util/crossgcc/Makefile.inc +++ b/util/crossgcc/Makefile.inc @@ -13,6 +13,8 @@ ## GNU General Public License for more details. ## +TOOLCHAIN_ARCHES := i386 x86 arm aarch64 mips riscv power8 + help_toolchain help:: @echo '*** Toolchain targets ***' @echo ' crossgcc - Build coreboot cross-compilers for all platforms' @@ -23,7 +25,7 @@ help_toolchain help:: @echo ' test-toolchain - Reports if toolchain components are out of date' @echo ' crossgcc-ARCH - Build cross-compiler for specific architecture' @echo ' crosstools-ARCH - Build cross-compiler with GDB for specific architecture' - @echo ' ARCH can be "i386", "x64", "arm", "aarch64", "mips", "riscv", or "power8"' + @echo ' ARCH can be "$(subst $(spc),"$(comma) ",$(TOOLCHAIN_ARCHES))"' @echo ' Use "make [target] CPUS=#" to build toolchain using multiple cores' @echo @@ -38,26 +40,8 @@ crossgcc: clean-for-update clang crosstools-i386 crosstools-x64 crosstools-arm \ crosstools-aarch64 crosstools-mips crosstools-riscv crosstools-power8 -crossgcc-i386: clean-for-update - $(MAKE) -C util/crossgcc build-i386 SKIP_GDB=1 - -crossgcc-x64: clean-for-update - $(MAKE) -C util/crossgcc build-x64 SKIP_GDB=1 - -crossgcc-arm: clean-for-update - $(MAKE) -C util/crossgcc build-arm SKIP_GDB=1 - -crossgcc-aarch64: clean-for-update - $(MAKE) -C util/crossgcc build-aarch64 SKIP_GDB=1 - -crossgcc-mips: clean-for-update - $(MAKE) -C util/crossgcc build-mips SKIP_GDB=1 - -crossgcc-riscv: clean-for-update - $(MAKE) -C util/crossgcc build-riscv SKIP_GDB=1 - -crossgcc-power8: clean-for-update - $(MAKE) -C util/crossgcc build-power8 SKIP_GDB=1 +$(foreach arch,$(TOOLCHAIN_ARCHES),crossgcc-$(arch)): clean-for-update + $(MAKE) -C util/crossgcc $(patsubst crossgcc-%,build-%,$@) SKIP_GDB=1 crosstools: clean-for-update $(MAKE) -C util/crossgcc all_with_gdb SKIP_CLANG=1 @@ -68,26 +52,8 @@ iasl: clean-for-update clang: clean-for-update $(MAKE) -C util/crossgcc build_clang -crosstools-i386: clean-for-update - $(MAKE) -C util/crossgcc build-i386 - -crosstools-x64: clean-for-update - $(MAKE) -C util/crossgcc build-x64 - -crosstools-arm: clean-for-update - $(MAKE) -C util/crossgcc build-arm - -crosstools-aarch64: clean-for-update - $(MAKE) -C util/crossgcc build-aarch64 - -crosstools-mips: clean-for-update - $(MAKE) -C util/crossgcc build-mips - -crosstools-riscv: clean-for-update - $(MAKE) -C util/crossgcc build-riscv - -crosstools-power8: clean-for-update - $(MAKE) -C util/crossgcc build-power8 +$(foreach arch,$(TOOLCHAIN_ARCHES),crosstools-$(arch)): clean-for-update + $(MAKE) -C util/crossgcc $(patsubst crosstools-%,build-%,$@) crossgcc-clean: clean-for-update $(MAKE) -C util/crossgcc clean

1 0

New patch to review for coreboot: mainboard/asus/kcma-d8: Add initial ASUS KCMA-D8 support
by Timothy Pearson 30 Jan '16

30 Jan '16

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13523 -gerrit commit 5a7f7c9e8fabac777ccb66719e01cf993dfef173 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Tue Nov 24 14:17:49 2015 -0600 mainboard/asus/kcma-d8: Add initial ASUS KCMA-D8 support Change-Id: Idefa304a27823c741fab72ff5c2f20fed1aa5a39 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/mainboard/asus/kcma-d8/cmos.default | 1 - src/mainboard/asus/kcma-d8/cmos.layout | 1 - src/mainboard/asus/kcma-d8/devicetree.cb | 46 ++++++---------- src/mainboard/asus/kcma-d8/dsdt.asl | 92 +++++++++----------------------- src/mainboard/asus/kcma-d8/mptable.c | 34 ++++++------ src/mainboard/asus/kcma-d8/resourcemap.c | 8 +-- src/mainboard/asus/kcma-d8/romstage.c | 62 ++++++--------------- 7 files changed, 80 insertions(+), 164 deletions(-) diff --git a/src/mainboard/asus/kcma-d8/cmos.default b/src/mainboard/asus/kcma-d8/cmos.default index 0e7afb3..c8edd97 100644 --- a/src/mainboard/asus/kcma-d8/cmos.default +++ b/src/mainboard/asus/kcma-d8/cmos.default @@ -23,7 +23,6 @@ sata_alpm = Disable maximum_p_state_limit = 0xf probe_filter = Auto l3_cache_partitioning = Disable -ieee1394_controller = Enable gart = Enable experimental_memory_speed_boost = Disable power_on_after_fail = On diff --git a/src/mainboard/asus/kcma-d8/cmos.layout b/src/mainboard/asus/kcma-d8/cmos.layout index 075388e..9bda1f6 100644 --- a/src/mainboard/asus/kcma-d8/cmos.layout +++ b/src/mainboard/asus/kcma-d8/cmos.layout @@ -46,7 +46,6 @@ entries 473 2 e 13 dimm_spd_checksum 475 1 e 14 probe_filter 476 1 e 1 l3_cache_partitioning -477 1 e 1 ieee1394_controller 478 1 e 1 iommu 479 1 e 1 cpu_core_boost 480 1 e 1 experimental_memory_speed_boost diff --git a/src/mainboard/asus/kcma-d8/devicetree.cb b/src/mainboard/asus/kcma-d8/devicetree.cb index 8d64ac7..1830f89 100644 --- a/src/mainboard/asus/kcma-d8/devicetree.cb +++ b/src/mainboard/asus/kcma-d8/devicetree.cb @@ -7,11 +7,10 @@ chip northbridge/amd/amdfam10/root_complex # Root complex device domain 0 on # PCI domain subsystemid 0x1043 0x8163 inherit chip northbridge/amd/amdfam10 # Northbridge / RAM controller - register "maximum_memory_capacity" = "0x4000000000" # 256GB + register "maximum_memory_capacity" = "0x2000000000" # 128GB device pci 18.0 on end # Link 0 == LDT 0 device pci 18.0 on end # Link 1 == LDT 1 - device pci 18.0 on end # Link 2 == LDT 2 - device pci 18.0 on # Link 3 == LDT 3 [SB on link 3] + device pci 18.0 on # Link 2 == LDT 2 [SB on link 2] chip southbridge/amd/sr5650 # Primary southbridge device pci 0.0 on end # HT Root Complex 0x9600 device pci 0.1 on end # CLKCONFIG @@ -36,16 +35,10 @@ chip northbridge/amd/amdfam10/root_complex # Root complex device pci b.0 on # Bridge (GPP2 Port0) # Slot # PCI E 4 end - device pci c.0 on # Bridge (GPP2 Port1) - # Slot # PCI E 5 - end - device pci d.0 on # Bridge (GPP3b Port0) - # Slot # PCI E 3 - end register "gpp1_configuration" = "0" # Configuration 16:0 default register "gpp2_configuration" = "1" # Configuration 8:8 register "gpp3a_configuration" = "2" # Configuration 4:1:1:0:0:0 - register "port_enable" = "0x3f1c" # Enable all ports except 0, 1, 5, 6, and 7 + register "port_enable" = "0x0f1c" # Enable all ports except 0, 1, 5, 6, and 7 register "pcie_settling_time" = "1000000" # Allow PIKE to be detected / configured end chip southbridge/amd/sb700 # Secondary southbridge @@ -150,7 +143,7 @@ chip northbridge/amd/amdfam10/root_complex # Root complex register "vsen5_low_limit_mv" = "1150" # VSEN5 (Node 0 HT link voltage) low limit to 1.15V register "vsen6_high_limit_mv" = "1250" # VSEN6 (Node 1 HT link voltage) high limit to 1.25V register "vsen6_low_limit_mv" = "1150" # VSEN6 (Node 1 HT link voltage) low limit to 1.15V - register "vsen7_high_limit_mv" = "1250" # VSEN7 (Northbridge core voltage) high limit to 1.25V + register "vsen7_high_limit_mv" = "1150" # VSEN7 (Northbridge core voltage) high limit to 1.15V register "vsen7_low_limit_mv" = "1050" # VSEN7 (Northbridge core voltage) low limit to 1.05V register "vsen8_high_limit_mv" = "1900" # VSEN8 (+1.8V) high limit to 1.9V register "vsen8_low_limit_mv" = "1700" # VSEN8 (+1.8V) low limit to 1.7V @@ -178,8 +171,8 @@ chip northbridge/amd/amdfam10/root_complex # Root complex device pci 14.2 on end # HDA 0x4383 (ASUS MIO add-on card) device pci 14.3 on # LPC 0x439d (SMBUS primary controller) chip superio/winbond/w83667hg-a # Super I/O - device pnp 2e.0 off end # FDC; Not available on the KGPE-D16 - device pnp 2e.1 off end # LPT1; Not available on the KGPE-D16 + device pnp 2e.0 off end # FDC; Not available on the KCMA-D8 + device pnp 2e.1 off end # LPT1; Not available on the KCMA-D8 device pnp 2e.2 on # Com1 io 0x60 = 0x3f8 irq 0x70 = 4 @@ -194,7 +187,7 @@ chip northbridge/amd/amdfam10/root_complex # Root complex irq 0x70 = 1 irq 0x72 = 12 end - device pnp 2e.6 off end # SPI: Not available on the KGPE-D16 + device pnp 2e.6 off end # SPI: Not available on the KCMA-D8 device pnp 2e.7 off end # GIPO6789 device pnp 2e.8 off end # WDT device pnp 2e.9 off end # GPIO2345 @@ -210,11 +203,16 @@ chip northbridge/amd/amdfam10/root_complex # Root complex end end device pci 14.4 on # Bridge - device pci 1.0 on end # VGA - device pci 2.0 on end # FireWire - device pci 3.0 on # Slot + device pci 1.0 on # Slot # Slot # PCI 0 end + device pci 2.0 on # Slot + # Slot # PCI 1 + end + device pci 3.0 on # Slot + # Slot # PCI 2 + end + device pci 5.0 on end # VGA end device pci 14.5 on end # USB OHCI2 0x4399 end @@ -224,24 +222,12 @@ chip northbridge/amd/amdfam10/root_complex # Root complex device pci 18.3 on end device pci 18.4 on end device pci 18.5 on end - device pci 19.0 on end # Socket 0 node 1 + device pci 19.0 on end # Socket 1 node 0 device pci 19.1 on end device pci 19.2 on end device pci 19.3 on end device pci 19.4 on end device pci 19.5 on end - device pci 1a.0 on end # Socket 1 node 0 - device pci 1a.1 on end - device pci 1a.2 on end - device pci 1a.3 on end - device pci 1a.4 on end - device pci 1a.5 on end - device pci 1b.0 on end # Socket 1 node 1 - device pci 1b.1 on end - device pci 1b.2 on end - device pci 1b.3 on end - device pci 1b.4 on end - device pci 1b.5 on end end end end diff --git a/src/mainboard/asus/kcma-d8/dsdt.asl b/src/mainboard/asus/kcma-d8/dsdt.asl index 5f9195a..ef87d31 100644 --- a/src/mainboard/asus/kcma-d8/dsdt.asl +++ b/src/mainboard/asus/kcma-d8/dsdt.asl @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, Raptor Engineering + * Copyright (C) 2015 Raptor Engineering * Copyright (C) 2005 - 2012 Advanced Micro Devices, Inc. * Copyright (C) 2007-2009 coresystems GmbH * Copyright (C) 2004 Nick Barker <Nick.Barker9(a)btinternet.com> @@ -116,8 +116,6 @@ DefinitionBlock ( Notify (\_SB.PCI0.NICA, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify (\_SB.PCI0.NICB, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify (\_SB.PCI0.PCE4, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify (\_SB.PCI0.PCE5, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify (\_SB.PCI0.PCE3, 0x02) /* NOTIFY_DEVICE_WAKE */ } } /* End Scope GPE */ @@ -125,13 +123,13 @@ DefinitionBlock ( /* Root of the bus hierarchy */ Scope (\_SB) { - /* Top southbridge PCI device (SR5690 + SP5100) */ + /* Top southbridge PCI device (SR5670 + SP5100) */ Device (PCI0) { /* BUS0 root bus */ - Name (_HID, EisaId ("PNP0A08")) /* PCI-e root bus (SR5690) */ - Name (_CID, EisaId ("PNP0A03")) /* PCI root bus (SP5100) */ + Name (_HID, EisaId ("PNP0A08")) /* PCI-e root bus (SR5670) */ + Name (_CID, EisaId ("PNP0A03")) /* PCI root bus (SP5100) */ Name (_ADR, 0x00180001) Name (_UID, 0x00) @@ -162,7 +160,7 @@ DefinitionBlock ( /* PCI Routing Tables */ Name (PR00, Package () { /* PIC */ - /* Top southbridge device (SR5690) */ + /* Top southbridge device (SR5670) */ /* HT Link */ Package (0x04) { 0x0000FFFF, 0x00, LNKA, 0x00 }, @@ -178,12 +176,6 @@ DefinitionBlock ( /* PCI-E Slot 4 (Bridge) */ Package (0x04) { 0x000BFFFF, 0x00, LNKG, 0x00 }, - /* PCI-E Slot 5 (Bridge) */ - Package (0x04) { 0x000CFFFF, 0x00, LNKG, 0x00 }, - - /* PCI-E Slot 3 (Bridge) */ - Package (0x04) { 0x000DFFFF, 0x00, LNKG, 0x00 }, - /* Bottom southbridge device (SP5100) */ /* SATA 0 */ Package (0x04) { 0x0011FFFF, 0x00, LNKG, 0x00 }, @@ -200,7 +192,7 @@ DefinitionBlock ( Package (0x04) { 0x0013FFFF, 0x02, LNKA, 0x00 }, Package (0x04) { 0x0013FFFF, 0x03, LNKB, 0x00 }, - /* SMBUS / IDE / LPC / VGA / FireWire / PCI Slot 0 */ + /* SMBUS / IDE / LPC / VGA / PCI Slots 0 - 2 */ Package (0x04) { 0x0014FFFF, 0x00, LNKA, 0x00 }, Package (0x04) { 0x0014FFFF, 0x01, LNKB, 0x00 }, Package (0x04) { 0x0014FFFF, 0x02, LNKC, 0x00 }, @@ -209,7 +201,7 @@ DefinitionBlock ( Name (AR00, Package () { /* APIC */ - /* Top southbridge device (SR5690) */ + /* Top southbridge device (SR5670) */ /* HT Link */ Package (0x04) { 0x0000FFFF, 0x00, 0x00, 55 }, @@ -225,12 +217,6 @@ DefinitionBlock ( /* PCI-E Slot 4 (Bridge) */ Package (0x04) { 0x000BFFFF, 0x00, 0x00, 54 }, - /* PCI-E Slot 5 (Bridge) */ - Package (0x04) { 0x000CFFFF, 0x00, 0x00, 54 }, - - /* PCI-E Slot 3 (Bridge) */ - Package (0x04) { 0x000DFFFF, 0x00, 0x00, 54 }, - /* Bottom southbridge device (SP5100) */ /* SATA 0 */ Package (0x04) { 0x0011FFFF, 0x00, 0x00, 22 }, @@ -247,7 +233,7 @@ DefinitionBlock ( Package (0x04) { 0x0013FFFF, 0x02, 0x00, 16 }, Package (0x04) { 0x0013FFFF, 0x03, 0x00, 17 }, - /* SMBUS / IDE / LPC / VGA / FireWire / PCI Slot 0 */ + /* SMBUS / IDE / LPC / VGA / PCI Slots 0 - 2 */ Package (0x04) { 0x0014FFFF, 0x00, 0x00, 16 }, Package (0x04) { 0x0014FFFF, 0x01, 0x00, 17 }, Package (0x04) { 0x0014FFFF, 0x02, 0x00, 18 }, @@ -256,22 +242,36 @@ DefinitionBlock ( Name (PR01, Package () { /* PIC */ - Package (0x04) { 0x1FFFF, 0x00, LNKF, 0x00 }, - Package (0x04) { 0x2FFFF, 0x00, LNKE, 0x00 }, + Package (0x04) { 0x1FFFF, 0x00, LNKE, 0x00 }, + Package (0x04) { 0x1FFFF, 0x01, LNKF, 0x00 }, + Package (0x04) { 0x1FFFF, 0x02, LNKG, 0x00 }, + Package (0x04) { 0x1FFFF, 0x03, LNKH, 0x00 }, + Package (0x04) { 0x2FFFF, 0x00, LNKF, 0x00 }, + Package (0x04) { 0x2FFFF, 0x01, LNKG, 0x00 }, + Package (0x04) { 0x2FFFF, 0x02, LNKH, 0x00 }, + Package (0x04) { 0x2FFFF, 0x03, LNKE, 0x00 }, Package (0x04) { 0x3FFFF, 0x00, LNKG, 0x00 }, Package (0x04) { 0x3FFFF, 0x01, LNKH, 0x00 }, Package (0x04) { 0x3FFFF, 0x02, LNKE, 0x00 }, Package (0x04) { 0x3FFFF, 0x03, LNKF, 0x00 }, + Package (0x04) { 0x5FFFF, 0x00, LNKH, 0x00 }, }) Name (AR01, Package () { /* APIC */ - Package (0x04) { 0x1FFFF, 0x00, 0x00, 21 }, - Package (0x04) { 0x2FFFF, 0x00, 0x00, 20 }, + Package (0x04) { 0x1FFFF, 0x00, 0x00, 20 }, + Package (0x04) { 0x1FFFF, 0x01, 0x00, 21 }, + Package (0x04) { 0x1FFFF, 0x02, 0x00, 22 }, + Package (0x04) { 0x1FFFF, 0x03, 0x00, 23 }, + Package (0x04) { 0x2FFFF, 0x00, 0x00, 21 }, + Package (0x04) { 0x2FFFF, 0x01, 0x00, 22 }, + Package (0x04) { 0x2FFFF, 0x02, 0x00, 23 }, + Package (0x04) { 0x2FFFF, 0x03, 0x00, 20 }, Package (0x04) { 0x3FFFF, 0x00, 0x00, 22 }, Package (0x04) { 0x3FFFF, 0x01, 0x00, 23 }, Package (0x04) { 0x3FFFF, 0x02, 0x00, 20 }, Package (0x04) { 0x3FFFF, 0x03, 0x00, 21 }, + Package (0x04) { 0x5FFFF, 0x00, 0x00, 23 }, }) Name (PR02, Package () { @@ -734,46 +734,6 @@ DefinitionBlock ( Name(_PRW, Package () {0x0B, 0x04}) // Wake from S1-S4 } } - - /* 6:00.0 PCIe x16 */ - Device (PCE5) - { - Name (_ADR, 0x000C0000) // _ADR: Address - Name(_PRW, Package () {0x11, 0x04}) // Wake from S1-S4 - Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table - { - If (PICM) { - Return (AR07) - } Else { - Return (PR07) - } - } - Device (SLT1) - { - Name (_ADR, 0xFFFF) // _ADR: Address - Name(_PRW, Package () {0x0B, 0x04}) // Wake from S1-S4 - } - } - - /* 7:00.0 PCIe x16 */ - Device (PCE3) - { - Name (_ADR, 0x000D0000) // _ADR: Address - Name(_PRW, Package () {0x11, 0x04}) // Wake from S1-S4 - Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table - { - If (PICM) { - Return (AR08) - } Else { - Return (PR08) - } - } - Device (SLT1) - { - Name (_ADR, 0xFFFF) // _ADR: Address - Name(_PRW, Package () {0x0B, 0x04}) // Wake from S1-S4 - } - } } Device (PWRB) { /* Start Power button device */ diff --git a/src/mainboard/asus/kcma-d8/mptable.c b/src/mainboard/asus/kcma-d8/mptable.c index c869d31..8967560 100644 --- a/src/mainboard/asus/kcma-d8/mptable.c +++ b/src/mainboard/asus/kcma-d8/mptable.c @@ -132,7 +132,6 @@ static void *smp_write_config_table(void *v) smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0, (((10)<<2)|(0)), apicid_sr5650, 30); /* Device 10 (LNKG, APIC pin 30) */ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0, (((11)<<2)|(0)), apicid_sr5650, 30); /* Device 11 (LNKG, APIC pin 30) */ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0, (((12)<<2)|(0)), apicid_sr5650, 30); /* Device 12 (LNKG, APIC pin 30) */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0, (((13)<<2)|(0)), apicid_sr5650, 30); /* Device 13 (LNKG, APIC pin 30)) */ dev = dev_find_slot(0, PCI_DEVFN(0x2, 0)); if (dev && dev->enabled) { @@ -164,11 +163,6 @@ static void *smp_write_config_table(void *v) uint8_t bus_pci = dev->link_list->secondary; smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pci, (((0)<<0xc)|(0)), apicid_sr5650, 0); /* card behind dev12 */ } - dev = dev_find_slot(0, PCI_DEVFN(0xd, 0)); - if (dev && dev->enabled) { - uint8_t bus_pci = dev->link_list->secondary; - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pci, (((0)<<0xd)|(0)), apicid_sr5650, 0); /* card behind dev13 */ - } /* PCI interrupts are level triggered, and are * associated with a specific bus/device/function tuple. @@ -195,23 +189,29 @@ static void *smp_write_config_table(void *v) if (dev && dev->enabled) { u8 bus_pci = dev->link_list->secondary; - /* PCI_SLOT 0. */ - PCI_INT(bus_pci, 0x1, 0x0, 0x15); - PCI_INT(bus_pci, 0x1, 0x1, 0x16); - PCI_INT(bus_pci, 0x1, 0x2, 0x17); - PCI_INT(bus_pci, 0x1, 0x3, 0x14); + /* PCI_SLOT 0 */ + PCI_INT(bus_pci, 0x1, 0x0, 0x14); + PCI_INT(bus_pci, 0x1, 0x1, 0x15); + PCI_INT(bus_pci, 0x1, 0x2, 0x16); + PCI_INT(bus_pci, 0x1, 0x3, 0x17); - /* PCI_SLOT 1. */ - PCI_INT(bus_pci, 0x2, 0x0, 0x14); - PCI_INT(bus_pci, 0x2, 0x1, 0x15); - PCI_INT(bus_pci, 0x2, 0x2, 0x16); - PCI_INT(bus_pci, 0x2, 0x3, 0x17); + /* PCI_SLOT 1 */ + PCI_INT(bus_pci, 0x2, 0x0, 0x15); + PCI_INT(bus_pci, 0x2, 0x1, 0x16); + PCI_INT(bus_pci, 0x2, 0x2, 0x17); + PCI_INT(bus_pci, 0x2, 0x3, 0x14); - /* PCI_SLOT 2. */ + /* PCI_SLOT 2 */ PCI_INT(bus_pci, 0x3, 0x0, 0x16); PCI_INT(bus_pci, 0x3, 0x1, 0x17); PCI_INT(bus_pci, 0x3, 0x2, 0x14); PCI_INT(bus_pci, 0x3, 0x3, 0x15); + + /* VGA */ + PCI_INT(bus_pci, 0x5, 0x0, 0x17); + PCI_INT(bus_pci, 0x5, 0x1, 0x14); + PCI_INT(bus_pci, 0x5, 0x2, 0x15); + PCI_INT(bus_pci, 0x5, 0x3, 0x16); } /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ diff --git a/src/mainboard/asus/kcma-d8/resourcemap.c b/src/mainboard/asus/kcma-d8/resourcemap.c index 8bcb28b..f7a2133 100644 --- a/src/mainboard/asus/kcma-d8/resourcemap.c +++ b/src/mainboard/asus/kcma-d8/resourcemap.c @@ -196,7 +196,7 @@ static void setup_mb_resource_map(void) * This field defines the end of PCI I/O region n * [31:25] Reserved */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC4), 0xFE000FC8, 0x00fff010, /* link 1 of cpu 0 --> AMD SR5690 */ + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC4), 0xFE000FC8, 0x00fff020, /* link 2 of cpu 0 --> AMD SR5690 */ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xCC), 0xFE000FC8, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD4), 0xFE000FC8, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xDC), 0xFE000FC8, 0x00000000, @@ -267,7 +267,7 @@ static void setup_mb_resource_map(void) * [31:24] Bus Number Limit i * This field defines the highest bus number in configuration region i */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0x05000103, /* link 1 of cpu 0 --> AMD SR5690 */ + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0x05000203, /* link 2 of cpu 0 --> AMD SR5690 */ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000FC88, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE8), 0x0000FC88, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xEC), 0x0000FC88, 0x00000000, @@ -451,7 +451,7 @@ static void setup_mb_resource_map(void) * This field defines the end of PCI I/O region n * [31:25] Reserved */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC4), 0xFE000FC8, 0x00fff110, /* link 3 of cpu 0 --> AMD SR5690 */ + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC4), 0xFE000FC8, 0x00fff020, /* link 2 of cpu 0 --> AMD SR5690 */ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xCC), 0xFE000FC8, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD4), 0xFE000FC8, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xDC), 0xFE000FC8, 0x00000000, @@ -522,7 +522,7 @@ static void setup_mb_resource_map(void) * [31:24] Bus Number Limit i * This field defines the highest bus number in configuration region i */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0x05000303, /* link 3 of cpu 0 --> AMD SR5690 */ + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0x05000203, /* link 2 of cpu 0 --> AMD SR5690 */ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000FC88, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE8), 0x0000FC88, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xEC), 0x0000FC88, 0x00000000, diff --git a/src/mainboard/asus/kcma-d8/romstage.c b/src/mainboard/asus/kcma-d8/romstage.c index 0b9a2ef..c9e0af5 100644 --- a/src/mainboard/asus/kcma-d8/romstage.c +++ b/src/mainboard/asus/kcma-d8/romstage.c @@ -96,28 +96,26 @@ static void switch_spd_mux(uint8_t channel) static const uint8_t spd_addr_fam15[] = { // Socket 0 Node 0 ("Node 0") RC00, DIMM0, DIMM1, 0, 0, DIMM2, DIMM3, 0, 0, - // Socket 0 Node 1 ("Node 1") - RC00, DIMM4, DIMM5, 0, 0, DIMM6, DIMM7, 0, 0, - // Socket 1 Node 0 ("Node 2") + // Socket 1 Node 0 ("Node 1") RC01, DIMM0, DIMM1, 0, 0, DIMM2, DIMM3, 0, 0, - // Socket 1 Node 1 ("Node 3") - RC01, DIMM4, DIMM5, 0, 0, DIMM6, DIMM7, 0, 0, }; static const uint8_t spd_addr_fam10[] = { // Socket 0 Node 0 ("Node 0") RC00, DIMM0, DIMM1, 0, 0, DIMM2, DIMM3, 0, 0, - // Socket 0 Node 1 ("Node 1") - RC00, DIMM4, DIMM5, 0, 0, DIMM6, DIMM7, 0, 0, - // Socket 1 Node 1 ("Node 2") - RC01, DIMM4, DIMM5, 0, 0, DIMM6, DIMM7, 0, 0, - // Socket 1 Node 0 ("Node 3") + // Socket 1 Node 0 ("Node 1") RC01, DIMM0, DIMM1, 0, 0, DIMM2, DIMM3, 0, 0, }; static void activate_spd_rom(const struct mem_controller *ctrl) { - /* Nothing needs to be done as there is no SPD mux on this board */ printk(BIOS_DEBUG, "activate_spd_rom() for node %02x\n", ctrl->node_id); + if (ctrl->node_id == 0) { + printk(BIOS_DEBUG, "enable_spd_node0()\n"); + switch_spd_mux(0x2); + } else if (ctrl->node_id == 1) { + printk(BIOS_DEBUG, "enable_spd_node1()\n"); + switch_spd_mux(0x3); + } } /* Voltages are specified by index @@ -189,13 +187,12 @@ void DIMMSetVoltages(struct MCTStatStruc *pMCTstat, } for (node = 0; node < MAX_NODES_SUPPORTED; node++) { - socket = node / 2; + socket = node; struct DCTStatStruc *pDCTstat; pDCTstat = pDCTstatA + node; /* reset socket_allowed_voltages before processing each socket */ - if (!(node % 2)) - socket_allowed_voltages = allowed_voltages; + socket_allowed_voltages = allowed_voltages; if (pDCTstat->NodePresent) { for (dimm = 0; dimm < MAX_DIMMS_SUPPORTED; dimm++) { @@ -203,10 +200,7 @@ void DIMMSetVoltages(struct MCTStatStruc *pMCTstat, socket_allowed_voltages &= pDCTstat->DimmSupportedVoltages[dimm]; } } - } - /* set voltage per socket after processing last contained node */ - if (pDCTstat->NodePresent && (node % 2)) { /* Set voltages */ if (socket_allowed_voltages & 0x8) { set_voltage = 0x8; @@ -223,16 +217,8 @@ void DIMMSetVoltages(struct MCTStatStruc *pMCTstat, } /* Save final DIMM voltages for MCT and SMBIOS use */ - if (pDCTstat->NodePresent) { - for (dimm = 0; dimm < MAX_DIMMS_SUPPORTED; dimm++) { - pDCTstat->DimmConfiguredVoltage[dimm] = set_voltage; - } - } - pDCTstat = pDCTstatA + (node - 1); - if (pDCTstat->NodePresent) { - for (dimm = 0; dimm < MAX_DIMMS_SUPPORTED; dimm++) { - pDCTstat->DimmConfiguredVoltage[dimm] = set_voltage; - } + for (dimm = 0; dimm < MAX_DIMMS_SUPPORTED; dimm++) { + pDCTstat->DimmConfiguredVoltage[dimm] = set_voltage; } } } @@ -243,23 +229,10 @@ void DIMMSetVoltages(struct MCTStatStruc *pMCTstat, static void set_peripheral_control_lines(void) { uint8_t byte; - uint8_t nvram; - uint8_t enable_ieee1394; - - enable_ieee1394 = 1; - - if (get_option(&nvram, "ieee1394_controller") == CB_SUCCESS) - enable_ieee1394 = nvram & 0x1; - if (enable_ieee1394) { - /* Enable PCICLK5 (onboard FireWire device) */ - outb(0x41, 0xcd6); - outb(0x02, 0xcd7); - } else { - /* Disable PCICLK5 (onboard FireWire device) */ - outb(0x41, 0xcd6); - outb(0x00, 0xcd7); - } + /* Enable PCICLK5 */ + outb(0x41, 0xcd6); + outb(0x02, 0xcd7); /* Enable the RTC AltCentury register */ outb(0x41, 0xcd6); @@ -584,8 +557,7 @@ BOOL AMD_CB_ManualBUIDSwapList (u8 node, u8 link, const u8 **List) { /* Force BUID to 0 */ static const u8 swaplist[] = {0, 0, 0xFF, 0, 0xFF}; - if ((is_fam15h() && (node == 0) && (link == 1)) /* Family 15h BSP SB link */ - || (!is_fam15h() && (node == 0) && (link == 3))) { /* Family 10h BSP SB link */ + if ((node == 0) && (link == 2)) { /* BSP SB link */ *List = swaplist; return 1; }

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coreboot-gerrit January 2016