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Patch set updated for coreboot: mainboard/asus/kcma-d8: Initial modification for KCMA-D8 name strings
by Timothy Pearson 31 Jan '16

31 Jan '16

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13522 -gerrit commit 4c5dae8b079842a3775aca67e266a82f7d816d43 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Tue Nov 24 14:12:08 2015 -0600 mainboard/asus/kcma-d8: Initial modification for KCMA-D8 name strings Change-Id: I841965279fae202894c31663b41610c5f069e125 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/mainboard/asus/kcma-d8/Kconfig | 18 +++++++++--------- src/mainboard/asus/kcma-d8/Kconfig.name | 4 ++-- src/mainboard/asus/kcma-d8/mainboard.c | 2 +- src/mainboard/asus/kcma-d8/romstage.c | 24 +++++------------------- 4 files changed, 17 insertions(+), 31 deletions(-) diff --git a/src/mainboard/asus/kcma-d8/Kconfig b/src/mainboard/asus/kcma-d8/Kconfig index 23c91f0..3c8cdcd 100644 --- a/src/mainboard/asus/kcma-d8/Kconfig +++ b/src/mainboard/asus/kcma-d8/Kconfig @@ -1,8 +1,8 @@ -if BOARD_ASUS_KGPE_D16 +if BOARD_ASUS_KCMA_D8 config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select CPU_AMD_SOCKET_G34_NON_AGESA + select CPU_AMD_SOCKET_C32_NON_AGESA select DIMM_DDR3 select DIMM_REGISTERED # select QRANK_DIMM_SUPPORT @@ -37,11 +37,11 @@ config BOARD_SPECIFIC_OPTIONS # dummy config MAINBOARD_DIR string - default "asus/kgpe-d16" + default "asus/kcma-d8" config BOOTBLOCK_MAINBOARD_INIT string - default "mainboard/asus/kgpe-d16/bootblock.c" + default "mainboard/asus/kcma-d8/bootblock.c" config DCACHE_RAM_BASE hex @@ -57,7 +57,7 @@ config APIC_ID_OFFSET config MAINBOARD_PART_NUMBER string - default "KGPE-D16" + default "KCMA-D8" config HW_MEM_HOLE_SIZEK hex @@ -65,12 +65,12 @@ config HW_MEM_HOLE_SIZEK config MAX_CPUS int - default 32 + default 16 -# 2 (internal) processors per G34 socket +# 1 (internal) processor per C32 socket config MAX_PHYSICAL_CPUS int - default 4 + default 2 config HT_CHAIN_UNITID_BASE hex @@ -100,4 +100,4 @@ config MAX_REBOOT_CNT int default 10 -endif # BOARD_ASUS_KGPE_D16 +endif # BOARD_ASUS_KCMA_D8 diff --git a/src/mainboard/asus/kcma-d8/Kconfig.name b/src/mainboard/asus/kcma-d8/Kconfig.name index bdfa31a..69b63ea 100644 --- a/src/mainboard/asus/kcma-d8/Kconfig.name +++ b/src/mainboard/asus/kcma-d8/Kconfig.name @@ -1,2 +1,2 @@ -config BOARD_ASUS_KGPE_D16 - bool "KGPE-D16" +config BOARD_ASUS_KCMA_D8 + bool "KCMA-D8" diff --git a/src/mainboard/asus/kcma-d8/mainboard.c b/src/mainboard/asus/kcma-d8/mainboard.c index 65029d4..0219ee6 100644 --- a/src/mainboard/asus/kcma-d8/mainboard.c +++ b/src/mainboard/asus/kcma-d8/mainboard.c @@ -52,7 +52,7 @@ void set_pcie_dereset(void) *************************************************/ static void mainboard_enable(device_t dev) { - printk(BIOS_INFO, "Mainboard KGPE-D16 Enable. dev=0x%p\n", dev); + printk(BIOS_INFO, "Mainboard KCMA-D8 initializing, dev=0x%p\n", dev); msr_t msr, msr2; diff --git a/src/mainboard/asus/kcma-d8/romstage.c b/src/mainboard/asus/kcma-d8/romstage.c index 1904bc2..4210a92 100644 --- a/src/mainboard/asus/kcma-d8/romstage.c +++ b/src/mainboard/asus/kcma-d8/romstage.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, Raptor Engineering + * Copyright (C) 2015 Raptor Engineering * * Copyright (C) 2007 AMD * Written by Yinghai Lu <yinghailu(a)amd.com> for AMD. @@ -67,7 +67,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "northbridge/amd/amdfam10/early_ht.c" /* - * ASUS KGPE-D16 specific SPD enable/disable magic. + * ASUS KCMA-D8 specific SPD enable/disable magic. * * Setting SP5100 GPIOs 59 and 60 controls an SPI mux with four settings: * 0: Disabled @@ -116,22 +116,8 @@ static const uint8_t spd_addr_fam10[] = { }; static void activate_spd_rom(const struct mem_controller *ctrl) { - struct sys_info *sysinfo = &sysinfo_car; - + /* Nothing needs to be done as there is no SPD mux on this board */ printk(BIOS_DEBUG, "activate_spd_rom() for node %02x\n", ctrl->node_id); - if (ctrl->node_id == 0) { - printk(BIOS_DEBUG, "enable_spd_node0()\n"); - switch_spd_mux(0x2); - } else if (ctrl->node_id == 1) { - printk(BIOS_DEBUG, "enable_spd_node1()\n"); - switch_spd_mux((is_fam15h() || (sysinfo->nodes <= 2))?0x2:0x3); - } else if (ctrl->node_id == 2) { - printk(BIOS_DEBUG, "enable_spd_node2()\n"); - switch_spd_mux((is_fam15h() || (sysinfo->nodes <= 2))?0x3:0x2); - } else if (ctrl->node_id == 3) { - printk(BIOS_DEBUG, "enable_spd_node3()\n"); - switch_spd_mux(0x3); - } } /* Voltages are specified by index @@ -414,8 +400,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) enable_sr5650_dev8(); sb7xx_51xx_lpc_init(); - if (CONFIG_MAX_PHYSICAL_CPUS != 4) - printk(BIOS_WARNING, "CONFIG_MAX_PHYSICAL_CPUS is %d, but this is a dual socket AMD G34 board!\n", CONFIG_MAX_PHYSICAL_CPUS); + if (CONFIG_MAX_PHYSICAL_CPUS != 2) + printk(BIOS_WARNING, "CONFIG_MAX_PHYSICAL_CPUS is %d, but this is a dual socket AMD C32 board!\n", CONFIG_MAX_PHYSICAL_CPUS); /* Halt if there was a built in self test failure */ report_bist_failure(bist);

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Patch set updated for coreboot: mainboard/asus/kcma-d8: Add initial ASUS KCMA-D8 support
by Timothy Pearson 31 Jan '16

31 Jan '16

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13523 -gerrit commit 52423f5f1494f4f3607b957cf86f69c6165074e0 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Tue Nov 24 14:17:49 2015 -0600 mainboard/asus/kcma-d8: Add initial ASUS KCMA-D8 support Change-Id: Idefa304a27823c741fab72ff5c2f20fed1aa5a39 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/mainboard/asus/kcma-d8/cmos.default | 1 - src/mainboard/asus/kcma-d8/cmos.layout | 1 - src/mainboard/asus/kcma-d8/devicetree.cb | 46 ++++++---------- src/mainboard/asus/kcma-d8/dsdt.asl | 92 +++++++++----------------------- src/mainboard/asus/kcma-d8/mptable.c | 34 ++++++------ src/mainboard/asus/kcma-d8/resourcemap.c | 8 +-- src/mainboard/asus/kcma-d8/romstage.c | 62 ++++++--------------- 7 files changed, 80 insertions(+), 164 deletions(-) diff --git a/src/mainboard/asus/kcma-d8/cmos.default b/src/mainboard/asus/kcma-d8/cmos.default index 0e7afb3..c8edd97 100644 --- a/src/mainboard/asus/kcma-d8/cmos.default +++ b/src/mainboard/asus/kcma-d8/cmos.default @@ -23,7 +23,6 @@ sata_alpm = Disable maximum_p_state_limit = 0xf probe_filter = Auto l3_cache_partitioning = Disable -ieee1394_controller = Enable gart = Enable experimental_memory_speed_boost = Disable power_on_after_fail = On diff --git a/src/mainboard/asus/kcma-d8/cmos.layout b/src/mainboard/asus/kcma-d8/cmos.layout index 075388e..9bda1f6 100644 --- a/src/mainboard/asus/kcma-d8/cmos.layout +++ b/src/mainboard/asus/kcma-d8/cmos.layout @@ -46,7 +46,6 @@ entries 473 2 e 13 dimm_spd_checksum 475 1 e 14 probe_filter 476 1 e 1 l3_cache_partitioning -477 1 e 1 ieee1394_controller 478 1 e 1 iommu 479 1 e 1 cpu_core_boost 480 1 e 1 experimental_memory_speed_boost diff --git a/src/mainboard/asus/kcma-d8/devicetree.cb b/src/mainboard/asus/kcma-d8/devicetree.cb index 8d64ac7..1830f89 100644 --- a/src/mainboard/asus/kcma-d8/devicetree.cb +++ b/src/mainboard/asus/kcma-d8/devicetree.cb @@ -7,11 +7,10 @@ chip northbridge/amd/amdfam10/root_complex # Root complex device domain 0 on # PCI domain subsystemid 0x1043 0x8163 inherit chip northbridge/amd/amdfam10 # Northbridge / RAM controller - register "maximum_memory_capacity" = "0x4000000000" # 256GB + register "maximum_memory_capacity" = "0x2000000000" # 128GB device pci 18.0 on end # Link 0 == LDT 0 device pci 18.0 on end # Link 1 == LDT 1 - device pci 18.0 on end # Link 2 == LDT 2 - device pci 18.0 on # Link 3 == LDT 3 [SB on link 3] + device pci 18.0 on # Link 2 == LDT 2 [SB on link 2] chip southbridge/amd/sr5650 # Primary southbridge device pci 0.0 on end # HT Root Complex 0x9600 device pci 0.1 on end # CLKCONFIG @@ -36,16 +35,10 @@ chip northbridge/amd/amdfam10/root_complex # Root complex device pci b.0 on # Bridge (GPP2 Port0) # Slot # PCI E 4 end - device pci c.0 on # Bridge (GPP2 Port1) - # Slot # PCI E 5 - end - device pci d.0 on # Bridge (GPP3b Port0) - # Slot # PCI E 3 - end register "gpp1_configuration" = "0" # Configuration 16:0 default register "gpp2_configuration" = "1" # Configuration 8:8 register "gpp3a_configuration" = "2" # Configuration 4:1:1:0:0:0 - register "port_enable" = "0x3f1c" # Enable all ports except 0, 1, 5, 6, and 7 + register "port_enable" = "0x0f1c" # Enable all ports except 0, 1, 5, 6, and 7 register "pcie_settling_time" = "1000000" # Allow PIKE to be detected / configured end chip southbridge/amd/sb700 # Secondary southbridge @@ -150,7 +143,7 @@ chip northbridge/amd/amdfam10/root_complex # Root complex register "vsen5_low_limit_mv" = "1150" # VSEN5 (Node 0 HT link voltage) low limit to 1.15V register "vsen6_high_limit_mv" = "1250" # VSEN6 (Node 1 HT link voltage) high limit to 1.25V register "vsen6_low_limit_mv" = "1150" # VSEN6 (Node 1 HT link voltage) low limit to 1.15V - register "vsen7_high_limit_mv" = "1250" # VSEN7 (Northbridge core voltage) high limit to 1.25V + register "vsen7_high_limit_mv" = "1150" # VSEN7 (Northbridge core voltage) high limit to 1.15V register "vsen7_low_limit_mv" = "1050" # VSEN7 (Northbridge core voltage) low limit to 1.05V register "vsen8_high_limit_mv" = "1900" # VSEN8 (+1.8V) high limit to 1.9V register "vsen8_low_limit_mv" = "1700" # VSEN8 (+1.8V) low limit to 1.7V @@ -178,8 +171,8 @@ chip northbridge/amd/amdfam10/root_complex # Root complex device pci 14.2 on end # HDA 0x4383 (ASUS MIO add-on card) device pci 14.3 on # LPC 0x439d (SMBUS primary controller) chip superio/winbond/w83667hg-a # Super I/O - device pnp 2e.0 off end # FDC; Not available on the KGPE-D16 - device pnp 2e.1 off end # LPT1; Not available on the KGPE-D16 + device pnp 2e.0 off end # FDC; Not available on the KCMA-D8 + device pnp 2e.1 off end # LPT1; Not available on the KCMA-D8 device pnp 2e.2 on # Com1 io 0x60 = 0x3f8 irq 0x70 = 4 @@ -194,7 +187,7 @@ chip northbridge/amd/amdfam10/root_complex # Root complex irq 0x70 = 1 irq 0x72 = 12 end - device pnp 2e.6 off end # SPI: Not available on the KGPE-D16 + device pnp 2e.6 off end # SPI: Not available on the KCMA-D8 device pnp 2e.7 off end # GIPO6789 device pnp 2e.8 off end # WDT device pnp 2e.9 off end # GPIO2345 @@ -210,11 +203,16 @@ chip northbridge/amd/amdfam10/root_complex # Root complex end end device pci 14.4 on # Bridge - device pci 1.0 on end # VGA - device pci 2.0 on end # FireWire - device pci 3.0 on # Slot + device pci 1.0 on # Slot # Slot # PCI 0 end + device pci 2.0 on # Slot + # Slot # PCI 1 + end + device pci 3.0 on # Slot + # Slot # PCI 2 + end + device pci 5.0 on end # VGA end device pci 14.5 on end # USB OHCI2 0x4399 end @@ -224,24 +222,12 @@ chip northbridge/amd/amdfam10/root_complex # Root complex device pci 18.3 on end device pci 18.4 on end device pci 18.5 on end - device pci 19.0 on end # Socket 0 node 1 + device pci 19.0 on end # Socket 1 node 0 device pci 19.1 on end device pci 19.2 on end device pci 19.3 on end device pci 19.4 on end device pci 19.5 on end - device pci 1a.0 on end # Socket 1 node 0 - device pci 1a.1 on end - device pci 1a.2 on end - device pci 1a.3 on end - device pci 1a.4 on end - device pci 1a.5 on end - device pci 1b.0 on end # Socket 1 node 1 - device pci 1b.1 on end - device pci 1b.2 on end - device pci 1b.3 on end - device pci 1b.4 on end - device pci 1b.5 on end end end end diff --git a/src/mainboard/asus/kcma-d8/dsdt.asl b/src/mainboard/asus/kcma-d8/dsdt.asl index 5f9195a..ef87d31 100644 --- a/src/mainboard/asus/kcma-d8/dsdt.asl +++ b/src/mainboard/asus/kcma-d8/dsdt.asl @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, Raptor Engineering + * Copyright (C) 2015 Raptor Engineering * Copyright (C) 2005 - 2012 Advanced Micro Devices, Inc. * Copyright (C) 2007-2009 coresystems GmbH * Copyright (C) 2004 Nick Barker <Nick.Barker9(a)btinternet.com> @@ -116,8 +116,6 @@ DefinitionBlock ( Notify (\_SB.PCI0.NICA, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify (\_SB.PCI0.NICB, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify (\_SB.PCI0.PCE4, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify (\_SB.PCI0.PCE5, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify (\_SB.PCI0.PCE3, 0x02) /* NOTIFY_DEVICE_WAKE */ } } /* End Scope GPE */ @@ -125,13 +123,13 @@ DefinitionBlock ( /* Root of the bus hierarchy */ Scope (\_SB) { - /* Top southbridge PCI device (SR5690 + SP5100) */ + /* Top southbridge PCI device (SR5670 + SP5100) */ Device (PCI0) { /* BUS0 root bus */ - Name (_HID, EisaId ("PNP0A08")) /* PCI-e root bus (SR5690) */ - Name (_CID, EisaId ("PNP0A03")) /* PCI root bus (SP5100) */ + Name (_HID, EisaId ("PNP0A08")) /* PCI-e root bus (SR5670) */ + Name (_CID, EisaId ("PNP0A03")) /* PCI root bus (SP5100) */ Name (_ADR, 0x00180001) Name (_UID, 0x00) @@ -162,7 +160,7 @@ DefinitionBlock ( /* PCI Routing Tables */ Name (PR00, Package () { /* PIC */ - /* Top southbridge device (SR5690) */ + /* Top southbridge device (SR5670) */ /* HT Link */ Package (0x04) { 0x0000FFFF, 0x00, LNKA, 0x00 }, @@ -178,12 +176,6 @@ DefinitionBlock ( /* PCI-E Slot 4 (Bridge) */ Package (0x04) { 0x000BFFFF, 0x00, LNKG, 0x00 }, - /* PCI-E Slot 5 (Bridge) */ - Package (0x04) { 0x000CFFFF, 0x00, LNKG, 0x00 }, - - /* PCI-E Slot 3 (Bridge) */ - Package (0x04) { 0x000DFFFF, 0x00, LNKG, 0x00 }, - /* Bottom southbridge device (SP5100) */ /* SATA 0 */ Package (0x04) { 0x0011FFFF, 0x00, LNKG, 0x00 }, @@ -200,7 +192,7 @@ DefinitionBlock ( Package (0x04) { 0x0013FFFF, 0x02, LNKA, 0x00 }, Package (0x04) { 0x0013FFFF, 0x03, LNKB, 0x00 }, - /* SMBUS / IDE / LPC / VGA / FireWire / PCI Slot 0 */ + /* SMBUS / IDE / LPC / VGA / PCI Slots 0 - 2 */ Package (0x04) { 0x0014FFFF, 0x00, LNKA, 0x00 }, Package (0x04) { 0x0014FFFF, 0x01, LNKB, 0x00 }, Package (0x04) { 0x0014FFFF, 0x02, LNKC, 0x00 }, @@ -209,7 +201,7 @@ DefinitionBlock ( Name (AR00, Package () { /* APIC */ - /* Top southbridge device (SR5690) */ + /* Top southbridge device (SR5670) */ /* HT Link */ Package (0x04) { 0x0000FFFF, 0x00, 0x00, 55 }, @@ -225,12 +217,6 @@ DefinitionBlock ( /* PCI-E Slot 4 (Bridge) */ Package (0x04) { 0x000BFFFF, 0x00, 0x00, 54 }, - /* PCI-E Slot 5 (Bridge) */ - Package (0x04) { 0x000CFFFF, 0x00, 0x00, 54 }, - - /* PCI-E Slot 3 (Bridge) */ - Package (0x04) { 0x000DFFFF, 0x00, 0x00, 54 }, - /* Bottom southbridge device (SP5100) */ /* SATA 0 */ Package (0x04) { 0x0011FFFF, 0x00, 0x00, 22 }, @@ -247,7 +233,7 @@ DefinitionBlock ( Package (0x04) { 0x0013FFFF, 0x02, 0x00, 16 }, Package (0x04) { 0x0013FFFF, 0x03, 0x00, 17 }, - /* SMBUS / IDE / LPC / VGA / FireWire / PCI Slot 0 */ + /* SMBUS / IDE / LPC / VGA / PCI Slots 0 - 2 */ Package (0x04) { 0x0014FFFF, 0x00, 0x00, 16 }, Package (0x04) { 0x0014FFFF, 0x01, 0x00, 17 }, Package (0x04) { 0x0014FFFF, 0x02, 0x00, 18 }, @@ -256,22 +242,36 @@ DefinitionBlock ( Name (PR01, Package () { /* PIC */ - Package (0x04) { 0x1FFFF, 0x00, LNKF, 0x00 }, - Package (0x04) { 0x2FFFF, 0x00, LNKE, 0x00 }, + Package (0x04) { 0x1FFFF, 0x00, LNKE, 0x00 }, + Package (0x04) { 0x1FFFF, 0x01, LNKF, 0x00 }, + Package (0x04) { 0x1FFFF, 0x02, LNKG, 0x00 }, + Package (0x04) { 0x1FFFF, 0x03, LNKH, 0x00 }, + Package (0x04) { 0x2FFFF, 0x00, LNKF, 0x00 }, + Package (0x04) { 0x2FFFF, 0x01, LNKG, 0x00 }, + Package (0x04) { 0x2FFFF, 0x02, LNKH, 0x00 }, + Package (0x04) { 0x2FFFF, 0x03, LNKE, 0x00 }, Package (0x04) { 0x3FFFF, 0x00, LNKG, 0x00 }, Package (0x04) { 0x3FFFF, 0x01, LNKH, 0x00 }, Package (0x04) { 0x3FFFF, 0x02, LNKE, 0x00 }, Package (0x04) { 0x3FFFF, 0x03, LNKF, 0x00 }, + Package (0x04) { 0x5FFFF, 0x00, LNKH, 0x00 }, }) Name (AR01, Package () { /* APIC */ - Package (0x04) { 0x1FFFF, 0x00, 0x00, 21 }, - Package (0x04) { 0x2FFFF, 0x00, 0x00, 20 }, + Package (0x04) { 0x1FFFF, 0x00, 0x00, 20 }, + Package (0x04) { 0x1FFFF, 0x01, 0x00, 21 }, + Package (0x04) { 0x1FFFF, 0x02, 0x00, 22 }, + Package (0x04) { 0x1FFFF, 0x03, 0x00, 23 }, + Package (0x04) { 0x2FFFF, 0x00, 0x00, 21 }, + Package (0x04) { 0x2FFFF, 0x01, 0x00, 22 }, + Package (0x04) { 0x2FFFF, 0x02, 0x00, 23 }, + Package (0x04) { 0x2FFFF, 0x03, 0x00, 20 }, Package (0x04) { 0x3FFFF, 0x00, 0x00, 22 }, Package (0x04) { 0x3FFFF, 0x01, 0x00, 23 }, Package (0x04) { 0x3FFFF, 0x02, 0x00, 20 }, Package (0x04) { 0x3FFFF, 0x03, 0x00, 21 }, + Package (0x04) { 0x5FFFF, 0x00, 0x00, 23 }, }) Name (PR02, Package () { @@ -734,46 +734,6 @@ DefinitionBlock ( Name(_PRW, Package () {0x0B, 0x04}) // Wake from S1-S4 } } - - /* 6:00.0 PCIe x16 */ - Device (PCE5) - { - Name (_ADR, 0x000C0000) // _ADR: Address - Name(_PRW, Package () {0x11, 0x04}) // Wake from S1-S4 - Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table - { - If (PICM) { - Return (AR07) - } Else { - Return (PR07) - } - } - Device (SLT1) - { - Name (_ADR, 0xFFFF) // _ADR: Address - Name(_PRW, Package () {0x0B, 0x04}) // Wake from S1-S4 - } - } - - /* 7:00.0 PCIe x16 */ - Device (PCE3) - { - Name (_ADR, 0x000D0000) // _ADR: Address - Name(_PRW, Package () {0x11, 0x04}) // Wake from S1-S4 - Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table - { - If (PICM) { - Return (AR08) - } Else { - Return (PR08) - } - } - Device (SLT1) - { - Name (_ADR, 0xFFFF) // _ADR: Address - Name(_PRW, Package () {0x0B, 0x04}) // Wake from S1-S4 - } - } } Device (PWRB) { /* Start Power button device */ diff --git a/src/mainboard/asus/kcma-d8/mptable.c b/src/mainboard/asus/kcma-d8/mptable.c index c869d31..8967560 100644 --- a/src/mainboard/asus/kcma-d8/mptable.c +++ b/src/mainboard/asus/kcma-d8/mptable.c @@ -132,7 +132,6 @@ static void *smp_write_config_table(void *v) smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0, (((10)<<2)|(0)), apicid_sr5650, 30); /* Device 10 (LNKG, APIC pin 30) */ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0, (((11)<<2)|(0)), apicid_sr5650, 30); /* Device 11 (LNKG, APIC pin 30) */ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0, (((12)<<2)|(0)), apicid_sr5650, 30); /* Device 12 (LNKG, APIC pin 30) */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0, (((13)<<2)|(0)), apicid_sr5650, 30); /* Device 13 (LNKG, APIC pin 30)) */ dev = dev_find_slot(0, PCI_DEVFN(0x2, 0)); if (dev && dev->enabled) { @@ -164,11 +163,6 @@ static void *smp_write_config_table(void *v) uint8_t bus_pci = dev->link_list->secondary; smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pci, (((0)<<0xc)|(0)), apicid_sr5650, 0); /* card behind dev12 */ } - dev = dev_find_slot(0, PCI_DEVFN(0xd, 0)); - if (dev && dev->enabled) { - uint8_t bus_pci = dev->link_list->secondary; - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pci, (((0)<<0xd)|(0)), apicid_sr5650, 0); /* card behind dev13 */ - } /* PCI interrupts are level triggered, and are * associated with a specific bus/device/function tuple. @@ -195,23 +189,29 @@ static void *smp_write_config_table(void *v) if (dev && dev->enabled) { u8 bus_pci = dev->link_list->secondary; - /* PCI_SLOT 0. */ - PCI_INT(bus_pci, 0x1, 0x0, 0x15); - PCI_INT(bus_pci, 0x1, 0x1, 0x16); - PCI_INT(bus_pci, 0x1, 0x2, 0x17); - PCI_INT(bus_pci, 0x1, 0x3, 0x14); + /* PCI_SLOT 0 */ + PCI_INT(bus_pci, 0x1, 0x0, 0x14); + PCI_INT(bus_pci, 0x1, 0x1, 0x15); + PCI_INT(bus_pci, 0x1, 0x2, 0x16); + PCI_INT(bus_pci, 0x1, 0x3, 0x17); - /* PCI_SLOT 1. */ - PCI_INT(bus_pci, 0x2, 0x0, 0x14); - PCI_INT(bus_pci, 0x2, 0x1, 0x15); - PCI_INT(bus_pci, 0x2, 0x2, 0x16); - PCI_INT(bus_pci, 0x2, 0x3, 0x17); + /* PCI_SLOT 1 */ + PCI_INT(bus_pci, 0x2, 0x0, 0x15); + PCI_INT(bus_pci, 0x2, 0x1, 0x16); + PCI_INT(bus_pci, 0x2, 0x2, 0x17); + PCI_INT(bus_pci, 0x2, 0x3, 0x14); - /* PCI_SLOT 2. */ + /* PCI_SLOT 2 */ PCI_INT(bus_pci, 0x3, 0x0, 0x16); PCI_INT(bus_pci, 0x3, 0x1, 0x17); PCI_INT(bus_pci, 0x3, 0x2, 0x14); PCI_INT(bus_pci, 0x3, 0x3, 0x15); + + /* VGA */ + PCI_INT(bus_pci, 0x5, 0x0, 0x17); + PCI_INT(bus_pci, 0x5, 0x1, 0x14); + PCI_INT(bus_pci, 0x5, 0x2, 0x15); + PCI_INT(bus_pci, 0x5, 0x3, 0x16); } /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ diff --git a/src/mainboard/asus/kcma-d8/resourcemap.c b/src/mainboard/asus/kcma-d8/resourcemap.c index 8bcb28b..f7a2133 100644 --- a/src/mainboard/asus/kcma-d8/resourcemap.c +++ b/src/mainboard/asus/kcma-d8/resourcemap.c @@ -196,7 +196,7 @@ static void setup_mb_resource_map(void) * This field defines the end of PCI I/O region n * [31:25] Reserved */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC4), 0xFE000FC8, 0x00fff010, /* link 1 of cpu 0 --> AMD SR5690 */ + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC4), 0xFE000FC8, 0x00fff020, /* link 2 of cpu 0 --> AMD SR5690 */ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xCC), 0xFE000FC8, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD4), 0xFE000FC8, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xDC), 0xFE000FC8, 0x00000000, @@ -267,7 +267,7 @@ static void setup_mb_resource_map(void) * [31:24] Bus Number Limit i * This field defines the highest bus number in configuration region i */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0x05000103, /* link 1 of cpu 0 --> AMD SR5690 */ + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0x05000203, /* link 2 of cpu 0 --> AMD SR5690 */ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000FC88, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE8), 0x0000FC88, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xEC), 0x0000FC88, 0x00000000, @@ -451,7 +451,7 @@ static void setup_mb_resource_map(void) * This field defines the end of PCI I/O region n * [31:25] Reserved */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC4), 0xFE000FC8, 0x00fff110, /* link 3 of cpu 0 --> AMD SR5690 */ + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xC4), 0xFE000FC8, 0x00fff020, /* link 2 of cpu 0 --> AMD SR5690 */ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xCC), 0xFE000FC8, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xD4), 0xFE000FC8, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xDC), 0xFE000FC8, 0x00000000, @@ -522,7 +522,7 @@ static void setup_mb_resource_map(void) * [31:24] Bus Number Limit i * This field defines the highest bus number in configuration region i */ - PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0x05000303, /* link 3 of cpu 0 --> AMD SR5690 */ + PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE0), 0x0000FC88, 0x05000203, /* link 2 of cpu 0 --> AMD SR5690 */ PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE4), 0x0000FC88, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xE8), 0x0000FC88, 0x00000000, PCI_ADDR(CONFIG_CBB, CONFIG_CDB, 1, 0xEC), 0x0000FC88, 0x00000000, diff --git a/src/mainboard/asus/kcma-d8/romstage.c b/src/mainboard/asus/kcma-d8/romstage.c index 4210a92..4552b1c 100644 --- a/src/mainboard/asus/kcma-d8/romstage.c +++ b/src/mainboard/asus/kcma-d8/romstage.c @@ -96,28 +96,26 @@ static void switch_spd_mux(uint8_t channel) static const uint8_t spd_addr_fam15[] = { // Socket 0 Node 0 ("Node 0") RC00, DIMM0, DIMM1, 0, 0, DIMM2, DIMM3, 0, 0, - // Socket 0 Node 1 ("Node 1") - RC00, DIMM4, DIMM5, 0, 0, DIMM6, DIMM7, 0, 0, - // Socket 1 Node 0 ("Node 2") + // Socket 1 Node 0 ("Node 1") RC01, DIMM0, DIMM1, 0, 0, DIMM2, DIMM3, 0, 0, - // Socket 1 Node 1 ("Node 3") - RC01, DIMM4, DIMM5, 0, 0, DIMM6, DIMM7, 0, 0, }; static const uint8_t spd_addr_fam10[] = { // Socket 0 Node 0 ("Node 0") RC00, DIMM0, DIMM1, 0, 0, DIMM2, DIMM3, 0, 0, - // Socket 0 Node 1 ("Node 1") - RC00, DIMM4, DIMM5, 0, 0, DIMM6, DIMM7, 0, 0, - // Socket 1 Node 1 ("Node 2") - RC01, DIMM4, DIMM5, 0, 0, DIMM6, DIMM7, 0, 0, - // Socket 1 Node 0 ("Node 3") + // Socket 1 Node 0 ("Node 1") RC01, DIMM0, DIMM1, 0, 0, DIMM2, DIMM3, 0, 0, }; static void activate_spd_rom(const struct mem_controller *ctrl) { - /* Nothing needs to be done as there is no SPD mux on this board */ printk(BIOS_DEBUG, "activate_spd_rom() for node %02x\n", ctrl->node_id); + if (ctrl->node_id == 0) { + printk(BIOS_DEBUG, "enable_spd_node0()\n"); + switch_spd_mux(0x2); + } else if (ctrl->node_id == 1) { + printk(BIOS_DEBUG, "enable_spd_node1()\n"); + switch_spd_mux(0x3); + } } /* Voltages are specified by index @@ -189,13 +187,12 @@ void DIMMSetVoltages(struct MCTStatStruc *pMCTstat, } for (node = 0; node < MAX_NODES_SUPPORTED; node++) { - socket = node / 2; + socket = node; struct DCTStatStruc *pDCTstat; pDCTstat = pDCTstatA + node; /* reset socket_allowed_voltages before processing each socket */ - if (!(node % 2)) - socket_allowed_voltages = allowed_voltages; + socket_allowed_voltages = allowed_voltages; if (pDCTstat->NodePresent) { for (dimm = 0; dimm < MAX_DIMMS_SUPPORTED; dimm++) { @@ -203,10 +200,7 @@ void DIMMSetVoltages(struct MCTStatStruc *pMCTstat, socket_allowed_voltages &= pDCTstat->DimmSupportedVoltages[dimm]; } } - } - /* set voltage per socket after processing last contained node */ - if (pDCTstat->NodePresent && (node % 2)) { /* Set voltages */ if (socket_allowed_voltages & 0x8) { set_voltage = 0x8; @@ -223,16 +217,8 @@ void DIMMSetVoltages(struct MCTStatStruc *pMCTstat, } /* Save final DIMM voltages for MCT and SMBIOS use */ - if (pDCTstat->NodePresent) { - for (dimm = 0; dimm < MAX_DIMMS_SUPPORTED; dimm++) { - pDCTstat->DimmConfiguredVoltage[dimm] = set_voltage; - } - } - pDCTstat = pDCTstatA + (node - 1); - if (pDCTstat->NodePresent) { - for (dimm = 0; dimm < MAX_DIMMS_SUPPORTED; dimm++) { - pDCTstat->DimmConfiguredVoltage[dimm] = set_voltage; - } + for (dimm = 0; dimm < MAX_DIMMS_SUPPORTED; dimm++) { + pDCTstat->DimmConfiguredVoltage[dimm] = set_voltage; } } } @@ -243,23 +229,10 @@ void DIMMSetVoltages(struct MCTStatStruc *pMCTstat, static void set_peripheral_control_lines(void) { uint8_t byte; - uint8_t nvram; - uint8_t enable_ieee1394; - - enable_ieee1394 = 1; - - if (get_option(&nvram, "ieee1394_controller") == CB_SUCCESS) - enable_ieee1394 = nvram & 0x1; - if (enable_ieee1394) { - /* Enable PCICLK5 (onboard FireWire device) */ - outb(0x41, 0xcd6); - outb(0x02, 0xcd7); - } else { - /* Disable PCICLK5 (onboard FireWire device) */ - outb(0x41, 0xcd6); - outb(0x00, 0xcd7); - } + /* Enable PCICLK5 */ + outb(0x41, 0xcd6); + outb(0x02, 0xcd7); /* Enable the RTC AltCentury register */ outb(0x41, 0xcd6); @@ -584,8 +557,7 @@ BOOL AMD_CB_ManualBUIDSwapList (u8 node, u8 link, const u8 **List) { /* Force BUID to 0 */ static const u8 swaplist[] = {0, 0, 0xFF, 0, 0xFF}; - if ((is_fam15h() && (node == 0) && (link == 1)) /* Family 15h BSP SB link */ - || (!is_fam15h() && (node == 0) && (link == 3))) { /* Family 10h BSP SB link */ + if ((node == 0) && (link == 2)) { /* BSP SB link */ *List = swaplist; return 1; }

1 0

Patch set updated for coreboot: mb/intel/d510mo: Explicitly select NIC on PCI in devicetree
by Damien Zammit 31 Jan '16

31 Jan '16

Damien Zammit (damien(a)zamaudio.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13455 -gerrit commit 8f70ac6e1243a5c588e6c7ac634f712c89f372fd Author: Damien Zammit <damien(a)zamaudio.com> Date: Tue Jan 26 14:06:26 2016 +1100 mb/intel/d510mo: Explicitly select NIC on PCI in devicetree While the board configuration still works without this, It's nicer to have the device statically defined since the NIC is hardwired to the board. Change-Id: Ic6682865dd17672c3782bfba9511cd120d1657c1 Signed-off-by: Damien Zammit <damien(a)zamaudio.com> --- src/mainboard/intel/d510mo/devicetree.cb | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/src/mainboard/intel/d510mo/devicetree.cb b/src/mainboard/intel/d510mo/devicetree.cb index c0f38de..c5b885f 100644 --- a/src/mainboard/intel/d510mo/devicetree.cb +++ b/src/mainboard/intel/d510mo/devicetree.cb @@ -43,7 +43,9 @@ chip northbridge/intel/pineview # Northbridge register "gpe0_en" = "0x20000040" device pci 1b.0 on end # Audio - device pci 1c.0 on end # PCIe 1 + device pci 1c.0 on # PCIe 1 + device pci 0.0 on end # NIC + end device pci 1c.1 on end # PCIe 2 device pci 1c.2 on end # PCIe 3 device pci 1c.3 on end # PCIe 4

1 0

Patch set updated for coreboot: Documentation: x86 Enable Serial Output
by Leroy P Leahy 31 Jan '16

31 Jan '16

Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13444 -gerrit commit 581a88dfeac3d556336b1e2fb404eaead414f4ab Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Sat Jan 30 17:40:40 2016 -0800 Documentation: x86 Enable Serial Output Document the steps necessary to enable serial output TEST=None Change-Id: Ifc0e700d7ef54fb1e28ca9bca34b94cccd3633ac Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- Documentation/Intel/Board/board.html | 25 +++++++++++++++++++ Documentation/Intel/SoC/soc.html | 47 +++++++++++++++++++++++++++++++++--- Documentation/Intel/development.html | 11 +++++++++ Documentation/Intel/fsp1_1.html | 14 +++++++++++ 4 files changed, 94 insertions(+), 3 deletions(-) diff --git a/Documentation/Intel/Board/board.html b/Documentation/Intel/Board/board.html index 71acfff..59aed39 100644 --- a/Documentation/Intel/Board/board.html +++ b/Documentation/Intel/Board/board.html @@ -14,6 +14,7 @@ </p> <ol> <li><a href="#RequiredFiles">Required Files</a></li> + <li>Enable <a href="#SerialOutput">Serial Output</a></li> </ol> @@ -78,6 +79,30 @@ <hr> +<h1><a name="SerialOutput">Enable Serial Output</a></h1> +<p> + Use the following steps to enable serial output: +</p> +<ol> + <li>Implement the car_mainboard_pre_console_init routine in the com_init.c + file: + <ol type="A"> + <li>Power on and enable the UART controller</li> + <li>Connect the UART receive and transmit data lines to the + appropriate SoC pins + </li> + </ol> + </li> + <li>Add Makefile.inc + <ol type="A"> + <li>Add com_init.c to romstage</li> + </ol> + </li> +</ol> + + + +<hr> <p>Modified: 30 January 2016</p> </body> </html> \ No newline at end of file diff --git a/Documentation/Intel/SoC/soc.html b/Documentation/Intel/SoC/soc.html index 7a74554..700a4a3 100644 --- a/Documentation/Intel/SoC/soc.html +++ b/Documentation/Intel/SoC/soc.html @@ -19,6 +19,11 @@ <li><a href="#EarlyDebug">Early Debug</a></li> <li><a href="#Bootblock">Bootblock</a></li> <li><a href="#TempRamInit">TempRamInit</a></li> + <li><a href="#Romstage">Romstage</a> + <ol type="A"> + <li>Enable <a href="#SerialOutput">Serial Output"</a></li> + </ol> + </li> </ol> @@ -197,9 +202,6 @@ mv build/coreboot.rom.new build/coreboot.rom <hr> -<<<<<<< HEAD:Documentation/Intel/SoC/soc.html -<p>Modified: 30 January 2016</p> -======= <h1><a name="TempRamInit">TempRamInit</a></h1> <p> Enable the call to TempRamInit using the following steps: @@ -270,6 +272,45 @@ mv build/coreboot.rom.new build/coreboot.rom <hr> +<h1><a name="Romstage">Romstage</a></h1> + +<h2><a name="SerialOutput">Serial Output</a></h2> +<p> + The following steps add the serial output support for romstage: +</p> +<ol> + <li>Create the romstage subdirectory</li> + <li>Add romstage/romstage.c + <ol type="A"> + <li>Program the necessary base addresses</li> + <li>Disable the TCO</li> + </ol> + </li> + <li>Add romstage/Makefile.inc + <ol type="A"> + <li>Add romstage.c to romstage</li> + </ol> + </li> + <li>Add gpio configuration support if necessary</li> + <li>Add the necessary .h files to support the build</li> + <li>Update Makefile.inc + <ol type="A"> + <li>Add the romstage subdirectory</li> + <li>Add the gpio configuration support file to romstage</li> + </ol> + </li> + <li>Set the necessary Kconfig values to enable serial output: + <ul> + <li>CONFIG_DRIVERS_UART_<driver>=y</li> + <li>CONFIG_CONSOLE_SERIAL=y</li> + <li>CONFIG_UART_FOR_CONSOLE=<port></li> + <li>CONFIG_CONSOLE_SERIAL_115200=y</li> + </ul> + </li> +</ol> + + +<hr> <p>Modified: 30 January 2016</p> </body> </html> \ No newline at end of file diff --git a/Documentation/Intel/development.html b/Documentation/Intel/development.html index d07bfb6..d1dd3a2 100644 --- a/Documentation/Intel/development.html +++ b/Documentation/Intel/development.html @@ -62,6 +62,17 @@ <li><a target="_blank" href="SoC/soc.html#EarlyDebug">Early Debug</a></li> <li>Implement and debug the <a target="_blank" href="SoC/soc.html#Bootblock">bootblock</a> code</li> <li>Implement and debug the call to <a target="_blank" href="SoC/soc.html#TempRamInit">TempRamInit</a></li> + <li>Enable the serial port + <ol type="A"> + <li>Power on, enable and configure GPIOs for the + <a target="_blank" href="Board/board.html#SerialOutput">debug serial UART</a> + </li> + <li>Add the <a target="_blank" href="SoC/soc.html#SerialOutput">serial outupt</a> + support to romstage + </li> + </ol> + </li> + <li>Enable <a target="_blank" href="fsp1_1.html#CorebootFspDebugging">coreboot/FSP</a> debugging</li> </ol> diff --git a/Documentation/Intel/fsp1_1.html b/Documentation/Intel/fsp1_1.html index 33385ac..53fc8e0 100644 --- a/Documentation/Intel/fsp1_1.html +++ b/Documentation/Intel/fsp1_1.html @@ -15,6 +15,7 @@ <ol> <li><a href="#RequiredFiles">Required Files</a></li> <li>Add the <a href="#FspBinary">FSP Binary File</a> to the Coreboot File System</li> + <li>Enable <a href="#CorebootFspDebugging">coreboot/FSP Debugging</a></li> </ol> <p> @@ -58,6 +59,19 @@ <hr> +<h1><a name="CorebootFspDebugging">Enable coreboot/FSP Debugging</a></h1> +<p> + Set the following Kconfig values: +</p> +<ul> + <li>CONFIG_DISPLAY_FSP_ENTRY_POINTS - Display the FSP entry points in romstage</li> + <li>CONFIG_DISPLAY_HOBS - Display and verify the hand-off-blocks (HOBs) returned by MemoryInit</li> + <li>CONFIG_DISPLAY_VBT - Display Video BIOS Table (VBT) used for GOP</li> + <li>CONFIG_DISPLAY_UPD_DATA - Display the user specified product data passed to MemoryInit and SiliconInit</li> +</ul> + + +<hr> <p>Modified: 30 January 2016</p> </body> </html> \ No newline at end of file

1 0

Patch set updated for coreboot: Documentation: x86 add sleep state and minimal memory setup
by Leroy P Leahy 31 Jan '16

31 Jan '16

Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13446 -gerrit commit 401ef6c01f40f51072161e39bac3420c6d2ea9b3 Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Sat Jan 30 17:42:28 2016 -0800 Documentation: x86 add sleep state and minimal memory setup Document how to add the sleep state and minimal memory setup. TEST=None Change-Id: Ibebeef34269dbf2366f1bea6d734f6bade4e4028 Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- Documentation/Intel/Board/board.html | 79 ++++++++++++++++++++++++++++++++++++ Documentation/Intel/SoC/soc.html | 53 ++++++++++++++++++++++++ Documentation/Intel/development.html | 14 +++++++ 3 files changed, 146 insertions(+) diff --git a/Documentation/Intel/Board/board.html b/Documentation/Intel/Board/board.html index 59aed39..3d93835 100644 --- a/Documentation/Intel/Board/board.html +++ b/Documentation/Intel/Board/board.html @@ -15,6 +15,7 @@ <ol> <li><a href="#RequiredFiles">Required Files</a></li> <li>Enable <a href="#SerialOutput">Serial Output</a></li> + <li>Load the <a href="#SpdData">Memory Timing Data</a></li> </ol> @@ -101,6 +102,84 @@ </ol> +<hr> +<h1><a name="SpdData">Memory Timing Data</a></h1> +<p> + Memory timing data is located in the flash. This data is in the format of + <a target="_blank" href="https://en.wikipedia.org/wiki/Serial_presence_detect">serial presence detect</a> + (SPD) data. + Use the following steps to load the SPD data: +</p> +<ol> + <li>Edit Kconfig to add the DISPLAY_SPD_DATA" value which enables the + display of the SPD data being passed to MemoryInit + </li> + <li>Create an "spd" subdirectory</li> + <li>Create an spd/spd.c file for the SPD implementation + <ol type="A"> + <li>Implement the mainboard_fill_spd_data routine + <ol type="i"> + <li>Read the SPD data either from the spd.bin file or using I2C or SMBUS</li> + <li>Fill in the pei_data structure with SPD data for each of the DIMMs</li> + <li>Set the DIMM channel configuration</li> + </ol> + </li> + </ol> + </li> + <li>Add an .spd.hex file containing the memory timing data to the spd subdirectory</li> + <li>Create spd/Makefile.inc + <ol type="A"> + <li>Add spd.c to romstage</li> + <li>Add the .spd.hex file to SPD_SOURCES</li> + </ol> + </li> + <li>Edit Makefile.inc to add the spd subdirectory</li> + <li>Edit romstage.c + <ol type="A"> + <li>Call mainboard_fill_spd_data</li> + <li>Add mainboard_memory_init_params to copy the SPD and DRAM + configuration data from the pei_data structure into the UPDs + for MemoryInit + </li> + </ol> + </li> + <li>Edit devicetree.cb + <ol type="A"> + <li>Include the UPD parameters for MemoryInit except for: + <ul> + <li>Address of SPD data</li> + <li>DRAM configuration set above</li> + </ul> + </li> + </ol> + </li> + <li>A working FSP + <a target="_blank" href="../fsp1_1.html#MemoryInit">MemoryInit</a> + routine is required to complete debugging</li> + <li>Debug the result until port 0x80 outputs + <ol type="A"> + <li>0x34: + - Just after entering + <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel…">raminit</a> + </li> + <li>0x36: + - Just before displaying the + <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel…">UPD parameters</a> + for FSP MemoryInit + </li> + <li>0x92: <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/include/conso…">POST_FSP_MEMORY_INIT</a> + - Just before calling FSP + <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel…">MemoryInit</a> + </li> + <li>0x37: + - Just after returning from FSP + <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel…">MemoryInit</a> + </li> + </ol> + </li> + <li>Continue debugging with CONFIG_DISPLAY_HOBS enabled until TempRamExit is called</li> +</ol> + <hr> <p>Modified: 30 January 2016</p> diff --git a/Documentation/Intel/SoC/soc.html b/Documentation/Intel/SoC/soc.html index 700a4a3..8672cca 100644 --- a/Documentation/Intel/SoC/soc.html +++ b/Documentation/Intel/SoC/soc.html @@ -22,6 +22,8 @@ <li><a href="#Romstage">Romstage</a> <ol type="A"> <li>Enable <a href="#SerialOutput">Serial Output"</a></li> + <li>Get the <a href="#PreviousSleepState">Previous Sleep State</a></li> + <li>Add the <a href="#MemoryInit">MemoryInit</a> Support</li> </ol> </li> </ol> @@ -310,6 +312,57 @@ mv build/coreboot.rom.new build/coreboot.rom </ol> +<h2><a name="PreviousSleepState">Determine Previous Sleep State</a></h2> +<p> + The following steps implement the code to get the previous sleep state: +</p> +<ol> + <li>Implement the fill_power_state routine which determines the previous sleep state</li> + <li>Debug the result until port 0x80 outputs + <ol type="A"> + <li>0x32: + - Just after entering + <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel…">romstage_common</a> + </li> + <li>0x33 - Just after calling + <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel…">soc_pre_ram_init</a> + </li> + <li>0x34: + - Just after entering + <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel…">raminit</a> + </li> + </ol> +</ol> + + +<h2><a name="MemoryInit">MemoryInit Support</a></h2> +<p> + The following steps implement the code to support the FSP MemoryInit call: +</p> +<ol> + <li>Add the chip.h header file to define the UPD values which get passed + to MemoryInit. Skip the values containing SPD addresses and DRAM + configuration data which is determined by the board. + <p> + <b>Build Note</b>: The src/mainboard/<Vendor>/<Board>/devicetree.cb + file specifies the default values for these parameters. The build + process creates the static.c module which contains the config data + structure containing these values. + </p> + </li> + <li>Edit romstage/romstage.c + <ol type="A"> + <li>Implement the romstage/romstage.c/soc_memory_init_params routine to + copy the values from the config structure into the UPD structure + </li> + <li>Implement the soc_display_memory_init_params routine to display + the updated UPD parameters by calling fsp_display_upd_value + </li> + </ol> + </li> +</ol> + + <hr> <p>Modified: 30 January 2016</p> </body> diff --git a/Documentation/Intel/development.html b/Documentation/Intel/development.html index d1dd3a2..cec17ec 100644 --- a/Documentation/Intel/development.html +++ b/Documentation/Intel/development.html @@ -73,6 +73,20 @@ </ol> </li> <li>Enable <a target="_blank" href="fsp1_1.html#CorebootFspDebugging">coreboot/FSP</a> debugging</li> + <li>Determine the <a target="_blank" href="SoC/soc.html#PreviousSleepState">Previous Sleep State</a></li> + <li>Enable DRAM: + <ol type="A"> + <li>Implement the SoC + <a target="_blank" href="SoC/soc.html#MemoryInit">MemoryInit</a> + Support + </li> + <li>Implement the board support to read the + <a target="_blank" href="Board/board.html#SpdData">Memory Timing Data</a> + </li> + </ol> + </li> + <li>Enable CONFIG_DISPLAY_MTRRS to verify the MTRR configuration</li> + <li>Coreboot should now attempt to load the payload</li> </ol>

1 0

Patch set updated for coreboot: Documentation: Add x86 bootblock support
by Leroy P Leahy 31 Jan '16

31 Jan '16

Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13441 -gerrit commit c4d39336c4cae9e1266deb5c9bc13505cfdd0ba1 Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Sat Jan 30 17:32:00 2016 -0800 Documentation: Add x86 bootblock support Document what is involved with adding the bootblock support. TEST=None Change-Id: I6c8cc38e1b9346b4962588b33ca5e4ab8eac24c3 Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- Documentation/Intel/SoC/soc.html | 96 ++++++++++++++++++++++++++++++++++++ Documentation/Intel/development.html | 1 + 2 files changed, 97 insertions(+) diff --git a/Documentation/Intel/SoC/soc.html b/Documentation/Intel/SoC/soc.html index ffa4a04..3fb61f6 100644 --- a/Documentation/Intel/SoC/soc.html +++ b/Documentation/Intel/SoC/soc.html @@ -17,6 +17,7 @@ <li>SoC <a href="#RequiredFiles">Required Files</a></li> <li><a href="#Descriptor">Start Booting</a></li> <li><a href="#EarlyDebug">Early Debug</a></li> + <li><a href="#Bootblock">Bootblock</a></li> </ol> @@ -100,6 +101,101 @@ mv build/coreboot.rom.new build/coreboot.rom <hr> +<h1><a name="Bootblock">Bootblock</a></h1> +<p> + Implement the bootblock using the following steps: +</p> +<ol> + <li>Create the directory as src/soc/<Vendor>/<Chip Family>/bootblock</li> + <li>Add the timestamp.inc file which initializes the floating point registers and saves + the initial timestamp. + </li> + <li>Add the bootblock.c file which: + <ol type="A"> + <li>Enables memory-mapped PCI config access</li> + <li>Updates the microcode by calling intel_update_microcode_from_cbfs</li> + <li>Enable ROM caching</li> + </ol> + </li> + <li>Edit the src/soc/<Vendor>/<Chip Family>/Kconfig file + <ol type="A"> + <li>Add the BOOTBLOCK_CPU_INIT value to point to the bootblock.c file</li> + <li>Add the CHIPSET_BOOTBLOCK_INCLUDE value to point to the timestamp.inc file</li> + </ol> + </li> + <li>Edit the src/soc/<Vendor>/<Chip Family>/Makefile.inc file + <ol type="A"> + <li>Add the bootblock subdirectory</li> + </ol> + </li> + <li>Edit the src/soc/<Vendor>/<Chip Family>/memmap.c file + <ol type="A"> + <li>Add the fsp/memmap.h include file</li> + <li>Add the mmap_region_granularity routine</li> + </ol> + </li> + <li>Add the necessary .h files to define the necessary values and structures</li> + <li>When successful port 0x80 will output the following values: + <ol type="A"> + <li>0x01: <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/include/conso…">POST_RESET_VECTOR_CORRECT</a> + - Bootblock successfully executed the + <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/cpu/x86/16bit…">reset vector</a> + and entered the 16-bit code at + <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/cpu/x86/16bit…">_start</a> + </li> + <li>0x10: <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/include/conso…">POST_ENTER_PROTECTED_MODE</a> + - Bootblock executing in + <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/cpu/x86/32bit…">32-bit mode</a> + </li> + <li>0x10 - Verstage/romstage reached 32-bit mode</li> + </ol> + </li> +</ol> + +<p> + <b>Build Note:</b> The following files are included into the default bootblock image: +</p> +<ul> + <li><a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/arch/x86/boot…">src/arch/x86/bootblock_romcc.S</a> + added by <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/arch/x86/Make…">src/arch/x86/Makefile.inc</a> + and includes the following files: + <ul> + <li><a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/arch/x86/prol…">src/arch/x86/prologue.inc</a></li> + <li><a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/cpu/x86/16bit…">src/cpu/x86/16bit/reset16.inc</a></li> + <li><a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/cpu/x86/16bit…">src/cpu/x86/16bit/entry16.inc</a></li> + <li><a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/cpu/x86/32bit…">src/cpu/x86/32bit/entry32.inc</a></li> + <li>The code in + <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/arch/x86/boot…">src/arch/x86/bootblock_romcc.S</a> + includes src/soc/<Vendor>/<Chip Family>/bootblock/timestamp.inc using the + CONFIG_CHIPSET_BOOTBLOCK_INCLUDE value set above + </li> + <li><a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/cpu/x86/sse_e…">src/cpu/x86/sse_enable.inc</a></li> + <li>The code in + <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/arch/x86/Make…">src/arch/x86/Makefile.inc</a> + invokes the ROMCC tool to convert the following "C" code into assembler as bootblock.inc: + <ul> + <li><a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/arch/x86/incl…">src/arch/x86/include/arch/bootblock_romcc.h</a></li> + <li><a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/cpu/x86/lapic…">src/cpu/x86/lapic/boot_cpu.c</a></li> + <li>The CONFIG_BOOTBLOCK_CPU_INIT value set above typically points to the code in + src/soc/<Vendor>/<Chip Family>/bootblock/bootblock.c + </li> + </ul> + </li> + </ul> + </li> + <li><a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/arch/x86/id.S">src/arch/x86/id.S</a> + added by <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/arch/x86/Make…">src/arch/x86/Makefile.inc</a> + </li> + <li><a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/cpu/intel/fit…">src/cpu/intel/fit/fit.S</a> + added by <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/cpu/intel/fit…">src/cpu/intel/fit/Makefile.inc</a> + </li> + <li><a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/arch/x86/walk…">src/arch/x86/walkcbfs.S</a> + added by <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/arch/x86/Make…">src/arch/x86/Makefile.inc</a> + </li> +</ul> + + +<hr> <p>Modified: 30 January 2016</p> </body> </html> \ No newline at end of file diff --git a/Documentation/Intel/development.html b/Documentation/Intel/development.html index 45477e0..7cb9b07 100644 --- a/Documentation/Intel/development.html +++ b/Documentation/Intel/development.html @@ -60,6 +60,7 @@ </li> <li>Get result to start <a target="_blank" href="SoC/soc.html#Descriptor">booting</a></li> <li><a target="_blank" href="SoC/soc.html#EarlyDebug">Early Debug</a></li> + <li>Implement and debug the <a target="_blank" href="SoC/soc.html#Bootblock">bootblock</a> code</li> </ol>

1 0

Patch set updated for coreboot: Documentation: Add x86 documentation for required files
by Leroy P Leahy 31 Jan '16

31 Jan '16

Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13438 -gerrit commit 541e3e2313bb67595c42fa72117d1ea9cc67e5ef Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Thu Jan 7 11:24:24 2016 -0800 Documentation: Add x86 documentation for required files Document the required files to perform a minimal coreboot/FSP build for x86. TEST=None Change-Id: I65b2947114634fce982ce82fb7c577fd5f47ed10 Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- Documentation/Intel/Board/board.html | 83 ++++++++++++++++++++++++++ Documentation/Intel/Board/galileo.html | 100 +++++++++++++++++++++++++++++++ Documentation/Intel/SoC/quark.html | 98 ++++++++++++++++++++++++++++++ Documentation/Intel/SoC/soc.html | 105 +++++++++++++++++++++++++++++++++ Documentation/Intel/development.html | 69 ++++++++++++++++++++++ Documentation/Intel/fsp1_1.html | 50 ++++++++++++++++ Documentation/Intel/index.html | 39 ++++++++++++ 7 files changed, 544 insertions(+) diff --git a/Documentation/Intel/Board/board.html b/Documentation/Intel/Board/board.html new file mode 100644 index 0000000..71acfff --- /dev/null +++ b/Documentation/Intel/Board/board.html @@ -0,0 +1,83 @@ +<!DOCTYPE html> +<html> + <head> + <title>Board</title> + </head> + <body> + +<h1>x86 Board Development</h1> +<p> + Board development requires System-on-a-Chip (SoC) support. + The combined steps are listed + <a target="_blank" href="../x86Development.html">here</a>. + The development steps for the board are listed below: +</p> +<ol> + <li><a href="#RequiredFiles">Required Files</a></li> +</ol> + + +<hr> +<h1><a name="RequiredFiles">Required Files</a></h1> +<p> + Create the board directory as src/mainboard/<Vendor>/<Board>. +</p> + +<p> + The following files are required to build a new board: +</p> +<ol> + <li>Kconfig.name - Defines the Kconfig value for the board</li> + <li>Kconfig + <ol type="A"> + <li>Selects the SoC for the board and specifies the SPI flash size + <ol type="I"> + <li>BOARD_ROMSIZE_KB_<Size></li> + <li>SOC_<Vendor>_<Chip Family></li> + </ol> + </li> + <li>Declare the Kconfig values for: + <ol type="I"> + <li>MAINBOARD_DIR</li> + <li>MAINBOARD_PART_NUMBER</li> + <li>MAINBOARD_VENDOR</li> + </ol> + </li> + </ol> + </li> + <li>devicetree.cb - Enable root bridge and serial port + <ol type="A"> + <li>The first line must be "chip soc/Intel/<soc family>"; + this path is used by the generated static.c to include the chip.h + header file + </li> + </ol> + </li> + <li>romstage.c + <ol type="A"> + <li>Add routine mainboard_romstage_entry which calls romstage_common</li> + </ol> + </li> + <li>Configure coreboot build: + <ol type="A"> + <li>Set LOCALVERSION</li> + <li>FLASHMAP_OFFSET = 0x00700000</li> + <li>Select vendor for the board</li> + <li>Select the board</li> + <LI>CBFS_SIZE = 0x00100000</li> + <li>Set the CPU_MICROCODE_CBFS_LEN</li> + <li>Set the CPU_MICROCODE_CBFS_LOC</li> + <li>Set the FSP_IMAGE_ID_STRING</li> + <li>Set the FSP_LOC</li> + <li>Disable GOP_SUPPORT</li> + <li>No payload</li> + <li>Choose the default value for all other options</li> + </ol> + </li> +</ol> + + +<hr> +<p>Modified: 30 January 2016</p> + </body> +</html> \ No newline at end of file diff --git a/Documentation/Intel/Board/galileo.html b/Documentation/Intel/Board/galileo.html new file mode 100644 index 0000000..210a821 --- /dev/null +++ b/Documentation/Intel/Board/galileo.html @@ -0,0 +1,100 @@ +<!DOCTYPE html> +<html> + <head> + <title>Galileo Gen 2</title> + </head> + <body> + +<h1>Intel® Galileo Gen 2 Development Board</h1> +<table> + <tr> + <td><a target="_blank" href="http://www.mouser.com/images/microsites/Intel_Galileo2_lrg.jpg"><img alt="Galileo Gen 2" src="http://www.mouser.com/images/microsites/Intel_Galileo2_lrg.jpg" width=500></a></td> + <td> +<table> + <tr bgcolor="#ffc0c0"> + <td> +Warning: Use of the Intel® Galileo Gen 2 mainboard code requires modification of the +util/xcompile/xcompile file to change the machine architecture from i686 to i586 because +the Quark™ processor does not support the instructions introduced with the +Pentium™ 6 architecture. +<ol> + <li>Edit the file util/xcompile/xcompile</li> + <li>Search for +<a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=util/xcompile/xco…">-march</a></li> + <li>Replace i686 with i586</li> + <li>Save the result</li> +</ol> +Without this change the Quark™ processor will halt when it executes one of the +instructions introduced with the Pentium™ 6 architecture. + </td> + </tr> +</table> +<p> + The Intel® Galileo Gen 2 mainboard code was developed along with the Intel® + <a target="_blank" href="../SoC/quark.html">Quark™</a> SoC: +</p> +<ul> + <li><a target="_blank" href="../x86Development.html">Overall</a> development</li> + <li><a target="_blank" href="../SoC/soc.html">SoC</a> support</li> + <li><a target="_blank" href="../fsp1_1.html">FSP 1.1</a> integration</li> + <li><a target="_blank" href="board.html">Board</a> support</li> +</ul> + </td> + </tr> +</table> + + + +<hr> +<h1>Galileo Gen 2 Board Documentation</h1> +<ul> + <li><a target="_blank" href="http://files.linuxgizmos.com/intel_galileo_gen2_blockdiagram.jpg">Block Diagram</a></li> + <li><a target="_blank" href="https://software.intel.com/en-us/iot/library/galileo-getting-started">Getting Started</a></li> + <li><a target="_blank" href="http://www.intel.com/content/www/us/en/embedded/products/galileo/galileo-ov…">Overview</a></li> + <li><a target="_blank" href="http://files.linuxgizmos.com/intel_galileo_gen2_ports.jpg">Port Diagram</a></li> + <li><a target="_blank" href="http://download.intel.com/support/galileo/sb/intelgalileogen2prodbrief_3307…">Product Brief</a></li> + <li><a target="_blank" href="http://www.intel.com/content/dam/www/public/us/en/documents/guides/galileo-…">Schematic</a></li> + <li><a target="_blank" href="http://download.intel.com/support/galileo/sb/galileo_boarduserguide_330237_…">User Guide</a></li> + <li>Components + <ul> + <li>A/D: Texas Instruments <a target="_blank" href="http://www.ti.com/lit/ds/symlink/adc108s102.pdf">ADC108S102</a></li> + <li>Analog Switch: Texas Instruments <a target="_blank" href="http://www.ti.com/lit/ds/symlink/ts5a23159.pdf">TS5A23159</a></li> + <li>Ethernet (10/100 MB/S): Texas Instruments <a target="_blank" href="http://www.ti.com/lit/ds/symlink/dp83848-ep.pdf">DP83848</a></li> + <li>Load Switch: Texas Instruments <a target="_blank" href="http://www.ti.com/lit/ds/symlink/tps22920.pdf">TPS22920x</a></li> + <li>Memory (256 MiB): Micron <a target="_blank" href="https://www.micron.com/~/media/Documents/Products/Data%20Sheet/DRAM/DDR3/1G…">MT41K128M8</a></li> + <li>SoC: Intel® Quark™ <a target="_blank" href="../SoC/quark.html">X-1000</a></li> + <li>Serial EEPROM (1 KiB): ON Semiconductor® <a target="_blank" href="http://www.onsemi.com/pub_link/Collateral/CAT24C01-D.PDF">CAT24C08</a></li> + <li>SPI Flash (8 MiB): Winbond™ <a target="_blank" href="http://www.winbond-usa.com/resource-files/w25q64fv_revl1_100713.pdf">W25Q64FV</a></li> + <li>Step Down Converter: Texas Instruments <a target="_blank" href="http://www.ti.com/lit/ds/slvsag7c/slvsag7c.pdf">TPS62130</a></li> + <li>Step Down Converter: Texas Instruments <a target="_blank" href="http://www.ti.com/lit/ug/slvu570/slvu570.pdf">TPS652510</a></li> + <li>Termination Regulator: Texas Instruments <a target="_blank" href="http://www.ti.com/lit/ds/symlink/tps51200.pdf">TPS51200</a></li> + </ul> + </li> +</ul> + + + +<hr> +<h1>Debug Tools</h1> +<ul> + <li>Flash Programmer: + <ul> + <li>Dediprog <a target="_blank" href="http://www.dediprog.com/pd/spi-flash-solution/SF100">SF100</a> ISP IC Programmer</li> + </ul> + </li> + <li>JTAG Connector: <a target="_blank" href="https://www.google.com/webhp?sourceid=chrome-instant&ion=1&espv=2&ie=UTF-8#…">Olimex ARM-JTAG-20-10</a></li> + <li>JTAG Debugger: + <ul> + <li>Olimex LTD <a target="_blank" href="https://www.google.com/webhp?sourceid=chrome-instant&ion=1&espv=2&ie=UTF-8#…">ARM-USB-OCD-H</a></li> + <li>Tincan Tools <a target="_blank" href="https://www.tincantools.com/wiki/Flyswatter2">Flyswatter2</a></li> + </ul> + </li> + <li><a target="_blank" href="http://download.intel.com/support/processors/quark/sb/sourcedebugusingopeno…">Hardware Setup and Software Installation</a></li> + <li>USB Serial cable: FTDI <a target="_blank" href="https://www.google.com/webhp?sourceid=chrome-instant&ion=1&espv=2&ie=UTF-8#…">TTL-232R-3V3</a></li> +</ul> + + +<hr> +<p>Modified: 30 January 2016</p> + </body> +</html> diff --git a/Documentation/Intel/SoC/quark.html b/Documentation/Intel/SoC/quark.html new file mode 100644 index 0000000..14dd507 --- /dev/null +++ b/Documentation/Intel/SoC/quark.html @@ -0,0 +1,98 @@ +<!DOCTYPE html> +<html> + <head> + <title>Quark™ SoC</title> + </head> + <body> + +<h1>Intel® Quark™ SoC</h1> +<table> + <tr> + <td><a target="_blank" href="http://www.intel.com/content/dam/www/public/us/en/images/embedded/16x9/edc-…"><img alt="Quark Block Diagram" src="http://www.intel.com/content/dam/www/public/us/en/images/embedded/16x9/edc-…" width=500></a></td> + <td> +<table> + <tr bgcolor="#ffc0c0"> + <td> +Warning: Use of the Intel® Quark™ SoC code requires modification of the util/xcompile/xcompile file to change the machine +architecture from i686 to i586 because the Quark™ processor does not support the instructions +introduced with the Pentium™ 6 architecture. +<ol> + <li>Edit the file util/xcompile/xcompile</li> + <li>Search for +<a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=util/xcompile/xco…">-march</a></li> + <li>Replace i686 with i586</li> + <li>Save the result</li> +</ol> +Without this change the Quark™ processor will halt when it executes one of the +instructions introduced with the Pentium™ 6 architecture. + </td> + </tr> +</table> +<p> + The Quark™ SoC code was developed using the + <a target="_blank" href="../Board/galileo.html">Galileo Gen 2</a> + board: +</p> +<ul> + <li><a target="_blank" href="../x86Development.html">Overall</a> development</li> + <li><a target="_blank" href="soc.html">SoC</a> support</li> + <li><a target="_blank" href="../fsp1_1.html">FSP 1.1</a> integration</li> + <li><a target="_blank" href="../Board/board.html">Board</a> support</li> +</ul> + </td> + </tr> +</table> + + + +<hr> +<h1>Quark™ Documentation</h1> +<ul> + <li><a target="_blank" href="http://www.intel.com/content/dam/www/public/us/en/images/embedded/16x9/edc-…">Block Diagram</a></li> + <li>Intel® 64 and IA-32 Architectures <a target="_blank" href="http://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-3…">Software Developer Manual</a></li> + <li><a target="_blank" href="http://www.intel.com/content/www/us/en/embedded/products/quark/specificatio…">Specifications</a>: + <ul> + <li><a target="_blank" href="http://ark.intel.com/products/79084/Intel-Quark-SoC-X1000-16K-Cache-400-MHz">X1000</a> + - <a target="_blank" href="http://www.intel.com/content/www/us/en/search.html?keyword=X1000">Documentation</a>: + <ul> + <li><a target="_blank" href="http://www.intel.com/content/dam/www/public/us/en/documents/datasheets/quar…">Datasheet</a></li> + <li><a target="_blank" href="http://www.intel.com/content/dam/support/us/en/documents/processors/quark/s…">Developer's Manual</a></li> + <li><a target="_blank" href="http://www.intel.com/content/dam/www/public/us/en/documents/product-briefs/…">Product Brief</a></li> + </ul> + </li> + </ul> + </li> +</ul> + + + +<hr> +<h1>Quark™ FSP</h1> +<ul> + <li>Intel® Firmware Support Package External Architecture Specification <a target="_blank" href="http://www.intel.com/content/dam/www/public/us/en/documents/technical-speci…">V1.1</a></li> + <li>Intel® Quark™ SoC X1000 <a target="_blank" href="http://www.intel.com/content/dam/www/public/us/en/documents/guides/quark-x1…">UEFI Firmware Writer's Guide</a></li> + <li>EDK2 Sources: + <ul> + <li>EDK2: git clone <a target="_blank" href="https://github.com/tianocore/edk2.git">https://github.com/tianocore/edk2.git</a></li> + <li>EDK2-FatPkg: git clone <a target="_blank" href="https://github.com/tianocore/edk2-FatPkg.git">https://github.com/tianocore/edk2-FatPkg.git</a> FatPkg</li> + <li>EDK2-non-osi: git clone <a target="_blank" href="https://github.com/tianocore/edk2-non-osi.git">https://github.com/tianocore/edk2-non-osi.git</a></li> + <li>Win32 BaseTools: git clone <a target="_blank" href="https://github.com/tianocore/edk2-BaseTools-win32.git">https://github.com/tianocore/edk2-BaseTools-win32.git</a></li> + </ul> + </li> + <li>Win32 Build Instructions: +<pre><code>set WORKSPACE=%CD% +set PACKAGES_PATH=%WORKSPACE%\edk2;%WORKSPACE%\FatPkg;%WORKSPACE%\edk2-non-osi +set EDK_TOOLS_BIN=%WORKSPACE%\edk2-BaseTools-win32 +cd edk2 +edksetup.bat +build -p QuarkPlatformPkg/Quark.dsc -a IA32 -t VS2012x86 -b DEBUG -DDEBUG_PROPERTY_MASK=0x27 -DDEBUG_PRINT_ERROR_LEVEL=0x80000042 +</code></pre> + </li> +</ul> + + + +<hr> +<p>Modified: 30 January 2016</p> + </body> +</html> \ No newline at end of file diff --git a/Documentation/Intel/SoC/soc.html b/Documentation/Intel/SoC/soc.html new file mode 100644 index 0000000..ffa4a04 --- /dev/null +++ b/Documentation/Intel/SoC/soc.html @@ -0,0 +1,105 @@ +<!DOCTYPE html> +<html> + <head> + <title>SoC</title> + </head> + <body> + +<h1>x86 System on a Chip (SoC) Development</h1> +<p> + SoC development is best done in parallel with development for a specific + board. The combined steps are listed + <a target="_blank" href="../x86Development.html">here</a>. + The development steps for the SoC are listed below: +</p> +<ol> + <li><a target="_blank" href="../fsp1_1.html#RequiredFiles">FSP 1.1</a> required files</li> + <li>SoC <a href="#RequiredFiles">Required Files</a></li> + <li><a href="#Descriptor">Start Booting</a></li> + <li><a href="#EarlyDebug">Early Debug</a></li> +</ol> + + +<hr> +<h1><a name="RequiredFiles">Required Files</a></h1> +<p> + Create the directory as src/soc/<Vendor>/<Chip Family>. +</p> + +<p> + The following files are required to build a new SoC: +</p> +<ul> + <li>Include files + <ul> + <li>include/soc/pei_data.h</li> + <li>include/soc/pm.h</li> + </ul> + </li> + <li>Kconfig - Defines the Kconfig value for the SoC and selects the tool + chains for the various stages: + <ul> + <li>select ARCH_BOOTBLOCK_<Tool Chain></li> + <li>select ARCH_RAMSTAGE_<Tool Chain></li> + <li>select ARCH_ROMSTAGE_<Tool Chain></li> + <li>select ARCH_VERSTAGE_<Tool Chain></li> + </ul> + </li> + <li>Makefile.inc - Specify the include paths</li> + <li>memmap.c - Top of usable RAM</li> +</ul> + + +<hr> +<h1><a name="Descriptor">Start Booting</a></h1> +<p> + Some SoC parts require additional firmware components in the flash. + This section describes how to add those pieces. +</p> + +<h2>Intel Firmware Descriptor</h2> +<p> + The Intel Firmware Descriptor (IFD) is located at the base of the flash part. + The following command overwrites the base of the flash image with the Intel + Firmware Descriptor: +</p> +<pre><code>dd if=descriptor.bin of=build/coreboot.rom conv=notrunc >/dev/null 2>&1</code></pre> + + +<h2><a name="MEB">Management Engine Binary</a></h2> +<p> + Some SoC parts contain and require that the Management Engine (ME) be running + before it is possible to bring the x86 processor out of reset. A binary file + containing the management engine code must be added to the firmware using the + ifdtool. The following commands add this binary blob: +</p> +<pre><code>util/ifdtool/ifdtool -i ME:me.bin build/coreboot.rom +mv build/coreboot.rom.new build/coreboot.rom +</code></pre> + + +<h2><a name="EarlyDebug">Early Debug</a></h2> +<p> + Early debugging between the reset vector and the time the serial port is enabled + is most easily done by writing values to port 0x80. +</p> + + +<h2>Success</h2> +<p> + When the reset vector is successfully invoked, port 0x80 will output the following value: +</p> +<ul> + <li>0x01: <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/include/conso…">POST_RESET_VECTOR_CORRECT</a> + - Bootblock successfully executed the + <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/cpu/x86/16bit…">reset vector</a> + and entered the 16-bit code at + <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/cpu/x86/16bit…">_start</a> + </li> +</ul> + + +<hr> +<p>Modified: 30 January 2016</p> + </body> +</html> \ No newline at end of file diff --git a/Documentation/Intel/development.html b/Documentation/Intel/development.html new file mode 100644 index 0000000..45477e0 --- /dev/null +++ b/Documentation/Intel/development.html @@ -0,0 +1,69 @@ +<!DOCTYPE html> +<html> + <head> + <title>Development</title> + </head> + <body> + +<h1>Coreboot/FSP Development Process for Intel® x86</h1> +<p> + The x86 development process for coreboot is broken into the following components: +</p> +<ul> + <li>Coreboot <a target="_blank" href="SoC/soc.html">SoC</a> development</li> + <li>Coreboot <a target="_blank" href="Board/board.html">mainboard</a> development</li> + <li><a target="_blank" href="fsp1_1.html">FSP 1.1</a> integration</li> +</ul> +<p> + The combined steps below describe how to bring up coreboot for a + system-on-a-chip (SoC) and a development board: +</p> +<table> + <tr bgcolor="#ffffc0"> + <td>The initial coreboot steps are single threaded! + The initial minimal FSP development is also single threaded. + Progress can speed up by adding more developers after the minimal coreboot/FSP + implementation reaches the payload. + </td> + </tr> +</table> +<ol> + <li>Get the necessary tools: + <ul> + <li>Linux: Use your package manager to install m4 bison flex and the libcurses development + package. + <ul> + <li>Ubuntu or other Linux distribution that use apt, run: +<pre><code>sudo apt-get install m4 bison flex ncurses-dev +</code></pre> + </li> + </ul> + </li> + </ul> + </li> + <li>Build the cross tools for i386: + <ul> + <li>Linux: +<pre><code>make crossgcc-i386</code></pre> + To use multiple processors for the toolchain build (which takes a long time), use: +<pre><code>make crossgcc-i386 CPUS=N</code></pre> + where N is the number of cores to use for the build. + </li> + </ul> + </li> + <li>Get something to build: + <ol type="A"> + <li><a target="_blank" href="fsp1_1.html#RequiredFiles">FSP 1.1</a> required files</li> + <li><a target="_blank" href="SoC/soc.html#RequiredFiles">SoC</a> required files</li> + <li><a target="_blank" href="Board/board.html#RequiredFiles">Board</a> required files</li> + </ol> + </li> + <li>Get result to start <a target="_blank" href="SoC/soc.html#Descriptor">booting</a></li> + <li><a target="_blank" href="SoC/soc.html#EarlyDebug">Early Debug</a></li> +</ol> + + +<hr> +<p>Modified: 30 January 2016</p> + </body> +</html> \ No newline at end of file diff --git a/Documentation/Intel/fsp1_1.html b/Documentation/Intel/fsp1_1.html new file mode 100644 index 0000000..949109f --- /dev/null +++ b/Documentation/Intel/fsp1_1.html @@ -0,0 +1,50 @@ +<!DOCTYPE html> +<html> + <head> + <title>FSP 1.1</title> + </head> + <body> + +<h1>x86 FSP 1.1 Development</h1> +<p> + Firmware Support Package (FSP) development requires System-on-a-Chip (SoC) + and board support. The combined steps are listed + <a target="_blank" href="x86Development.html">here</a>. + The development steps for FSP are listed below: +</p> +<ol> + <li><a href="#RequiredFiles">Required Files</a></li> +</ol> + +<p> + FSP Documentation: +</p> +<ul> + <li>Intel® Firmware Support Package External Architecture Specification <a target="_blank" href="http://www.intel.com/content/dam/www/public/us/en/documents/technical-speci…">V1.1</a></li> +</ul> + +<hr> +<h1><a name="RequiredFiles">Required Files</a></h1> +<h2><a name="CorebootRequiredFiles">Coreboot Required Files</a></h2> +<ol> + <li>Create the following directories if they do not already exist: + <ul> + <li>src/vendorcode/intel/fsp/fsp1_1/<Chip Family></li> + <li>3rdparty/blobs/mainboard/<Board Vendor>/<Board Name></li> + </ul> + </li> + <li> + The following files may need to be copied from the FSP build or release into the + directories above if they are not present or are out of date: + <ul> + <li>FspUpdVpd.h: src/vendorcode/intel/fsp/fsp1_1/<Chip Family>/FspUpdVpd.h</li> + <li>FSP.bin: 3rdparty/blobs/mainboard/<Board Vendor>/<Board Name>/fsp.bin</li> + </ul> + </li> +</ol> + + +<hr> +<p>Modified: 30 January 2016</p> + </body> +</html> \ No newline at end of file diff --git a/Documentation/Intel/index.html b/Documentation/Intel/index.html new file mode 100644 index 0000000..53b93e0 --- /dev/null +++ b/Documentation/Intel/index.html @@ -0,0 +1,39 @@ +<!DOCTYPE html> +<html> + <head> + <title>Intel® x86</title> + </head> + <body> + +<h1>Intel® x86 Boards</h1> +<ul> + <li><a target="_blank" href="Board/galileo.html">Galileo</a></li> +</ul> + + + +<h1>Intel® x86 SoCs</h1> +<ul> + <li><a target="_blank" href="SoC/quark.html">Quark™</a></li> +</ul> + + + +<h1>x86 Coreboot Development</h1> +<ul> + <li><a target="_blank" href="development.html">Overall</a></li> + <li><a target="_blank" href="fsp1_1.html">FSP 1.1</a> integration + <ul> + <li>Intel® Firmware Support Package External Architecture Specification <a target="_blank" href="http://www.intel.com/content/dam/www/public/us/en/documents/technical-speci…">V1.1</a></li> + </ul> + </li> + <li><a target="_blank" href="SoC/soc.html">SoC</a> support</li> + <li><a target="_blank" href="Board/board.html">Board</a> support</li> +</ul> + + + +<hr> +<p>Modified: 30 January 2016</p> + </body> +</html> \ No newline at end of file

1 0

Patch set updated for coreboot: Documentation: Add the x86 FSP Binary
by Leroy P Leahy 31 Jan '16

31 Jan '16

Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13442 -gerrit commit 60dd78e3114d5923e5803293c80cc23b9d31e352 Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Sat Jan 30 17:19:21 2016 -0800 Documentation: Add the x86 FSP Binary Document how to add the FSP binary to the SPI flash image. TEST=None Change-Id: I51b16600ea69853240282ac2eb0d84935b8e2a71 Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- Documentation/Intel/SoC/soc.html | 74 ++++++++++++++++++++++++++++++++++++ Documentation/Intel/development.html | 1 + Documentation/Intel/fsp1_1.html | 13 +++++++ 3 files changed, 88 insertions(+) diff --git a/Documentation/Intel/SoC/soc.html b/Documentation/Intel/SoC/soc.html index 3fb61f6..7a74554 100644 --- a/Documentation/Intel/SoC/soc.html +++ b/Documentation/Intel/SoC/soc.html @@ -18,6 +18,7 @@ <li><a href="#Descriptor">Start Booting</a></li> <li><a href="#EarlyDebug">Early Debug</a></li> <li><a href="#Bootblock">Bootblock</a></li> + <li><a href="#TempRamInit">TempRamInit</a></li> </ol> @@ -196,6 +197,79 @@ mv build/coreboot.rom.new build/coreboot.rom <hr> +<<<<<<< HEAD:Documentation/Intel/SoC/soc.html +<p>Modified: 30 January 2016</p> +======= +<h1><a name="TempRamInit">TempRamInit</a></h1> +<p> + Enable the call to TempRamInit using the following steps: +</p> +<ol> + <li>Edit the src/soc/<Vendor>/<Chip Family>/Kconfig file + <ol type="A"> + <li>Add "select USE_GENERIC_FSP_CAR_INC" to enable the use of + <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel…">src/drivers/intel/fsp1_1/cache_as_ram.inc</a> + </li> + <li>Add "select SOC_INTEL_COMMON" to enable the use of the files from src/soc/intel/common + specifically building + <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/soc/intel/com…">util.c</a> + </li> + </ol> + </li> + <li>Debug the result until port 0x80 outputs + <ol type="A"> + <li>0x90: <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/include/conso…">POST_FSP_TEMP_RAM_INIT</a> + - Just before calling + <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel…">TempRamInit</a> + </li> + <li>Alternating 0xba and 0x01 - The FSP image was not found</li> + </ol> + </li> + <li>Add the <a target="_blank" href="../fsp1_1.html#FspBinary">FSP binary file</a> to the flash image</li> + <li>Set the following Kconfig values: + <ul> + <li>CONFIG_FSP_LOC to the FSP base address specified in the previous step</li> + <li>CONFIG_FSP_IMAGE_ID_STRING</li> + </ul> + </li> + <li>Debug the result until port 0x80 outputs + <ol type="A"> + <li>0x90: <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/include/conso…">POST_FSP_TEMP_RAM_INIT</a> + - Just before calling + <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel…">TempRamInit</a> + </li> + <li>Alternating 0xbb and 0x02 - TempRamInit executed, no CPU microcode update found</li> + </ol> + </li> + <li>Add the CPU microcode update file + <ol type="A"> + <li>Add the microcode file with the following command +<pre><code>util/cbfstool/cbfstool build/coreboot.rom add -t microcode -n cpu_microcode_blob.bin -b <base address> -f cpu_microcode_blob.bin</code></pre> + </li> + <li>Set the Kconfig values + <ul> + <li>CONFIG_CPU_MICROCODE_CBFS_LOC set to the value from the previous step</li> + <li>CONFIG_CPU_MICROCODE_CBFS_LEN</li> + </ul> + </li> + </ol> + </li> + <li>Debug the result until port 0x80 outputs + <ol type="A"> + <li>0x90: <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/include/conso…">POST_FSP_TEMP_RAM_INIT</a> + - Just before calling + <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel…">TempRamInit</a> + </li> + <li>0x2A - Just before calling + <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel…">cache_as_ram_main</a> + which is the start of the verstage code which may be part of romstage + </li> + </ol> + </li> +</ol> + + +<hr> <p>Modified: 30 January 2016</p> </body> </html> \ No newline at end of file diff --git a/Documentation/Intel/development.html b/Documentation/Intel/development.html index 7cb9b07..d07bfb6 100644 --- a/Documentation/Intel/development.html +++ b/Documentation/Intel/development.html @@ -61,6 +61,7 @@ <li>Get result to start <a target="_blank" href="SoC/soc.html#Descriptor">booting</a></li> <li><a target="_blank" href="SoC/soc.html#EarlyDebug">Early Debug</a></li> <li>Implement and debug the <a target="_blank" href="SoC/soc.html#Bootblock">bootblock</a> code</li> + <li>Implement and debug the call to <a target="_blank" href="SoC/soc.html#TempRamInit">TempRamInit</a></li> </ol> diff --git a/Documentation/Intel/fsp1_1.html b/Documentation/Intel/fsp1_1.html index 949109f..33385ac 100644 --- a/Documentation/Intel/fsp1_1.html +++ b/Documentation/Intel/fsp1_1.html @@ -14,6 +14,7 @@ </p> <ol> <li><a href="#RequiredFiles">Required Files</a></li> + <li>Add the <a href="#FspBinary">FSP Binary File</a> to the Coreboot File System</li> </ol> <p> @@ -45,6 +46,18 @@ <hr> +<h1><a name="FspBinary">Add the FSP Binary File to Coreboot File System</a></h1> +<p> + Add the FSP binary to the coreboot flash image using the following command: +</p> +<pre><code>util/cbfstool/cbfstool build/coreboot.rom add -t fsp -n fsp.bin -b <base address> -f fsp.bin</code></pre> +<p> + This command relocates the FSP binary to the 4K byte aligned location in CBFS so that the + FSP code for TempRamInit may be executed in place. +</p> + + +<hr> <p>Modified: 30 January 2016</p> </body> </html> \ No newline at end of file

1 0

New patch to review for coreboot: soc/intel/quark: MTRR support
by Leroy P Leahy 31 Jan '16

31 Jan '16

Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13530 -gerrit commit c7eca87d2f2c22dddd1f7a17e1ed740b950b531c Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Sat Jan 30 10:07:05 2016 -0800 soc/intel/quark: MTRR support Add the SoC specific routines to access the MTRR registers. These registers exist in the host bridge and are not accessible via the rdmsr/wrmsr instructions. Directly use the QuarkSocPkg/QuarkNorthCluster/Include/QuarkNcSocId.h file from the EDK2 tree (https://github.com/tianocore/edk2.git) to enable easy differences and correct issues in coreboot that were found in EDK2. Testing: * Edit the src/mainboard/intel/galileo/Makefile.inc file * Add "select DISPLAY_MTRRS" * Add "select HAVE_FSP_PDAT_FILE" * Add "select HAVE_FSP_RAW_BIN" * Add "select HAVE_RMU_FILE" * Place the FSP.bin file in the location specified by CONFIG_FSP_FILE * Place the pdat.bin files in the location specified by CONFIG_FSP_PDAT_FILE * Place the rmu.bin file in the location specified by CONFIG_RMU_FILE * Testing is successful if: * The message "FSP TempRamInit successful" is displayed TEST=Build and run on Galileo Change-Id: I7c124145429ae1d1365a6222a68853edbef4ff69 Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- src/soc/intel/quark/Kconfig | 1 + src/soc/intel/quark/include/soc/QuarkNcSocId.h | 760 +++++++++++++++++++++++++ src/soc/intel/quark/include/soc/romstage.h | 2 + src/soc/intel/quark/romstage/romstage.c | 204 +++++++ 4 files changed, 967 insertions(+) diff --git a/src/soc/intel/quark/Kconfig b/src/soc/intel/quark/Kconfig index cf8de91..9c343f2 100644 --- a/src/soc/intel/quark/Kconfig +++ b/src/soc/intel/quark/Kconfig @@ -27,6 +27,7 @@ config CPU_SPECIFIC_OPTIONS select ARCH_ROMSTAGE_X86_32 select ARCH_VERSTAGE_X86_32 select SOC_INTEL_COMMON + select SOC_SETS_MTRRS select TSC_CONSTANT_RATE select UDELAY_TSC diff --git a/src/soc/intel/quark/include/soc/QuarkNcSocId.h b/src/soc/intel/quark/include/soc/QuarkNcSocId.h new file mode 100644 index 0000000..210bf55 --- /dev/null +++ b/src/soc/intel/quark/include/soc/QuarkNcSocId.h @@ -0,0 +1,760 @@ +/** @file +QuarkNcSocId Register Definitions + +Copyright (c) 2013-2015 Intel Corporation. + +This program and the accompanying materials +are licensed and made available under the terms and conditions of the BSD License +which accompanies this distribution. The full text of the license may be found at +http://opensource.org/licenses/bsd-license.php + +THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +Definitions beginning with "R_" are registers +Definitions beginning with "B_" are bits within registers +Definitions beginning with "V_" are meaningful values of bits within the registers +Definitions beginning with "S_" are register sizes +Definitions beginning with "N_" are the bit position + +**/ + +#ifndef _QUARK_NC_SOC_ID_H_ +#define _QUARK_NC_SOC_ID_H_ + +// +// QNC GMCH Equates +// + +// +// DEVICE 0 (Memroy Controller Hub) +// +#define MC_BUS PCI_BUS_NUMBER_QNC +#define MC_DEV 0x00 +#define MC_FUN 0x00 + +#define QUARK_MC_VENDOR_ID V_INTEL_VENDOR_ID +#define QUARK_MC_DEVICE_ID 0x0958 +#define QUARK2_MC_DEVICE_ID 0x12C0 +#define QNC_MC_REV_ID_A0 0x00 + + +// +// MCR - B0:D0:F0:RD0h (WO)- Message control register (Datasheet 12.5) +// [31:24] Message opcode - D0 read; E0 write; +// [23:16] Message port +// [15:8 ] Message target register address +// [ 7:4 ] Message write byte enable : F is enable +// [ 3:0 ] Reserved +// +#define QNC_ACCESS_PORT_MCR 0xD0 // Message Control Register +// Always Set to 0xF0 +#define QNC_MCR_MASK 0x000000ff +#define QNC_MCR_BYTE_ENABLES 0x000000f0 + +// +//MDR - B0:D0:F0:RD4h (RW)- Message data register +// +#define QNC_ACCESS_PORT_MDR 0xD4 // Message Data Register + +// +//MEA - B0:D0:F0:RD8h (RW)- Message extended address register +// +#define QNC_ACCESS_PORT_MEA 0xD8 // Message Extended Address Register +#define QNC_MEA_MASK 0xffffff00 + +#define QNC_MCR_OP_OFFSET 24 // Offset of the opcode field in MCR +#define QNC_MCR_PORT_OFFSET 16 // Offset of the port field in MCR +#define QNC_MCR_REG_OFFSET 8 // Offset of the register field in MCR + +// +// Misc Useful Macros +// + +#define LShift16(value) (value << 16) + +// +// QNC Message OpCodes and Attributes +// +#define QUARK_OPCODE_READ 0x10 // Quark message bus "read" opcode +#define QUARK_OPCODE_WRITE 0x11 // Quark message bus "write" opcode + +// +// Alternative opcodes for the SCSS block +// +#define QUARK_ALT_OPCODE_READ 0x06 // Quark message bus "read" opcode +#define QUARK_ALT_OPCODE_WRITE 0x07 // Quark message bus "write" opcode + +// +// QNC Message OpCodes and Attributes for IO +// +#define QUARK_OPCODE_IO_READ 0x02 // Quark message bus "IO read" opcode +#define QUARK_OPCODE_IO_WRITE 0x03 // Quark message bus "IO write" opcode + + +#define QUARK_DRAM_BASE_ADDR_READY 0x78 // Quark message bus "RMU Main binary shadow" opcode + +#define QUARK_ECC_SCRUB_RESUME 0xC2 // Quark Remote Management Unit "scrub resume" opcode +#define QUARK_ECC_SCRUB_PAUSE 0xC3 // Quark Remote Management Unit "scrub pause" opcode + +// +// QNC Message Ports and Registers +// +// Start of SB Port IDs +#define QUARK_NC_MEMORY_ARBITER_SB_PORT_ID 0x00 +#define QUARK_NC_MEMORY_CONTROLLER_SB_PORT_ID 0x01 +#define QUARK_NC_HOST_BRIDGE_SB_PORT_ID 0x03 +#define QUARK_NC_RMU_SB_PORT_ID 0x04 +#define QUARK_NC_MEMORY_MANAGER_SB_PORT_ID 0x05 +#define QUARK_SC_USB_AFE_SB_PORT_ID 0x14 +#define QUARK_SC_PCIE_AFE_SB_PORT_ID 0x16 +#define QUARK_SCSS_SOC_UNIT_SB_PORT_ID 0x31 +#define QUARK_SCSS_FUSE_SB_PORT_ID 0x33 +#define QUARK_ICLK_SB_PORT_ID 0x32 +#define QUARK_SCSS_CRU_SB_PORT_ID 0x34 + +// +// Quark Memory Arbiter Registers. +// +#define QUARK_NC_MEMORY_ARBITER_REG_ASTATUS 0x21 // Memory Arbiter PRI Status encodings register. +#define ASTATUS_PRI_CASUAL 0x0 // Serviced only if convenient +#define ASTATUS_PRI_IMPENDING 0x1 // Serviced if the DRAM is in Self-Refresh. +#define ASTATUS_PRI_NORMAL 0x2 // Normal request servicing. +#define ASTATUS_PRI_URGENT 0x3 // Urgent request servicing. +#define ASTATUS1_RASISED_BP (10) +#define ASTATUS1_RASISED_BP_MASK (0x03 << ASTATUS1_RASISED_BP) +#define ASTATUS0_RASISED_BP (8) +#define ASTATUS0_RASISED_BP_MASK (0x03 << ASTATUS1_RASISED_BP) +#define ASTATUS1_DEFAULT_BP (2) +#define ASTATUS1_DEFAULT_BP_MASK (0x03 << ASTATUS1_RASISED_BP) +#define ASTATUS0_DEFAULT_BP (0) +#define ASTATUS0_DEFAULT_BP_MASK (0x03 << ASTATUS1_RASISED_BP) + +// +// Quark Memory Controller Registers. +// +#define QUARK_NC_MEMORY_CONTROLLER_REG_DFUSESTAT 0x70 // Fuse status register. +#define B_DFUSESTAT_ECC_DIS (BIT0) // Disable ECC. + +// +// Quark Remote Management Unit Registers. +// +#define QNC_MSG_TMPM_REG_PMBA 0x70 // Power Management I/O Base Address + +#define QUARK_NC_RMU_REG_CONFIG 0x71 // Remote Management Unit configuration register. +#define TS_LOCK_AUX_TRIP_PT_REGS_ENABLE (BIT6) +#define TS_LOCK_THRM_CTRL_REGS_ENABLE (BIT5) + +#define QUARK_NC_RMU_REG_OPTIONS_1 0x72 // Remote Management Unit Options register 1. +#define OPTIONS_1_DMA_DISABLE (BIT0) + +#define QUARK_NC_RMU_REG_WDT_CONTROL 0x74 // Remote Management Unit Watchdog control register. +#define B_WDT_CONTROL_DBL_ECC_BIT_ERR_MASK (BIT19 | BIT18) +#define B_WDT_CONTROL_DBL_ECC_BIT_ERR_BP 18 +#define V_WDT_CONTROL_DBL_ECC_BIT_ERR_NONE (0x0 << B_WDT_CONTROL_DBL_ECC_BIT_ERR_BP) +#define V_WDT_CONTROL_DBL_ECC_BIT_ERR_CAT (0x1 << B_WDT_CONTROL_DBL_ECC_BIT_ERR_BP) +#define V_WDT_CONTROL_DBL_ECC_BIT_ERR_WARM (0x2 << B_WDT_CONTROL_DBL_ECC_BIT_ERR_BP) +#define V_WDT_CONTROL_DBL_ECC_BIT_ERR_SERR (0x3 << B_WDT_CONTROL_DBL_ECC_BIT_ERR_BP) + +#define QUARK_NC_RMU_REG_TS_MODE 0xB0 // Remote Management Unit Thermal sensor mode register. +#define TS_ENABLE (BIT15) +#define QUARK_NC_RMU_REG_TS_TRIP 0xB2 // Remote Management Unit Thermal sensor programmable trip point register. +#define TS_HOT_TRIP_CLEAR_THOLD_BP 24 +#define TS_HOT_TRIP_CLEAR_THOLD_MASK (0xFF << TS_HOT_TRIP_CLEAR_THOLD_BP) +#define TS_CAT_TRIP_CLEAR_THOLD_BP 16 +#define TS_CAT_TRIP_CLEAR_THOLD_MASK (0xFF << TS_CAT_TRIP_CLEAR_THOLD_BP) +#define TS_HOT_TRIP_SET_THOLD_BP 8 +#define TS_HOT_TRIP_SET_THOLD_MASK (0xFF << TS_HOT_TRIP_SET_THOLD_BP) +#define TS_CAT_TRIP_SET_THOLD_BP 0 +#define TS_CAT_TRIP_SET_THOLD_MASK (0xFF << TS_CAT_TRIP_SET_THOLD_BP) + +#define QUARK_NC_ECC_SCRUB_CONFIG_REG 0x50 +#define SCRUB_CFG_INTERVAL_SHIFT 0x00 +#define SCRUB_CFG_INTERVAL_MASK 0xFF +#define SCRUB_CFG_BLOCKSIZE_SHIFT 0x08 +#define SCRUB_CFG_BLOCKSIZE_MASK 0x1F +#define SCRUB_CFG_ACTIVE (BIT13) +#define SCRUB_CFG_INVALID 0x00000FFF + +#define QUARK_NC_ECC_SCRUB_START_MEM_REG 0x76 +#define QUARK_NC_ECC_SCRUB_END_MEM_REG 0x77 +#define QUARK_NC_ECC_SCRUB_NEXT_READ_REG 0x7C + +#define SCRUB_RESUME_MSG() ((UINT32)( \ + (QUARK_ECC_SCRUB_RESUME << QNC_MCR_OP_OFFSET) | \ + (QUARK_NC_RMU_SB_PORT_ID << QNC_MCR_PORT_OFFSET) | \ + 0xF0)) + +#define SCRUB_PAUSE_MSG() ((UINT32)( \ + (QUARK_ECC_SCRUB_PAUSE << QNC_MCR_OP_OFFSET) | \ + (QUARK_NC_RMU_SB_PORT_ID << QNC_MCR_PORT_OFFSET) | \ + 0xF0)) + +// +// Quark Memory Manager Registers +// +#define QUARK_NC_MEMORY_MANAGER_ESRAMPGCTRL_BLOCK 0x82 +#define BLOCK_ENABLE_PG (1 << 28) +#define BLOCK_DISABLE_PG (1 << 29) +#define QUARK_NC_MEMORY_MANAGER_BIMRVCTL 0x19 +#define EnableIMRInt BIT31 +#define QUARK_NC_MEMORY_MANAGER_BSMMVCTL 0x1C +#define EnableSMMInt BIT31 +#define QUARK_NC_MEMORY_MANAGER_BTHCTRL 0x20 +#define DRAM_NON_HOST_RQ_LIMIT_BP 0 +#define DRAM_NON_HOST_RQ_LIMIT_MASK (0x3f << DRAM_NON_HOST_RQ_LIMIT_BP) + +#define QUARK_NC_TOTAL_IMR_SET 0x8 +#define QUARK_NC_MEMORY_MANAGER_IMR0 0x40 +#define QUARK_NC_MEMORY_MANAGER_IMR1 0x44 +#define QUARK_NC_MEMORY_MANAGER_IMR2 0x48 +#define QUARK_NC_MEMORY_MANAGER_IMR3 0x4C +#define QUARK_NC_MEMORY_MANAGER_IMR4 0x50 +#define QUARK_NC_MEMORY_MANAGER_IMR5 0x54 +#define QUARK_NC_MEMORY_MANAGER_IMR6 0x58 +#define QUARK_NC_MEMORY_MANAGER_IMR7 0x5C + #define QUARK_NC_MEMORY_MANAGER_IMRXL 0x00 + #define IMR_LOCK BIT31 + #define IMR_EN BIT30 + #define IMRL_MASK 0x00FFFFFC + #define IMRL_RESET 0x00000000 + #define QUARK_NC_MEMORY_MANAGER_IMRXH 0x01 + #define IMRH_MASK 0x00FFFFFC + #define IMRH_RESET 0x00000000 + #define QUARK_NC_MEMORY_MANAGER_IMRXRM 0x02 + #define QUARK_NC_MEMORY_MANAGER_IMRXWM 0x03 + #define IMRX_ALL_ACCESS 0xFFFFFFFF + #define CPU_SNOOP BIT30 + #define RMU BIT29 + #define CPU0_NON_SMM BIT0 + +// +// Quark Host Bridge Registers (Datasheet 12.7.2) +// +#define QNC_MSG_FSBIC_REG_HMISC 0x03 // Host Misellaneous Controls +#define SMI_EN (BIT19) // SMI Global Enable (from Legacy Bridge) +#define QNC_MSG_FSBIC_REG_HSMMC 0x04 // Host SMM Control +#define NON_HOST_SMM_WR_OPEN (BIT18) // SMM Writes OPEN +#define NON_HOST_SMM_RD_OPEN (BIT17) // SMM Writes OPEN +#define SMM_CODE_RD_OPEN (BIT16) // SMM Code read OPEN +#define SMM_CTL_EN (BIT3) // SMM enable +#define SMM_WRITE_OPEN (BIT2) // SMM Writes OPEN +#define SMM_READ_OPEN (BIT1) // SMM Reads OPEN +#define SMM_LOCKED (BIT0) // SMM Locked +#define SMM_START_MASK 0x0000FFF0 +#define SMM_END_MASK 0xFFF00000 +#define QUARK_NC_HOST_BRIDGE_HMBOUND_REG 0x08 +#define HMBOUND_MASK 0x0FFFFF000 +#define HMBOUND_LOCK BIT0 +#define QUARK_NC_HOST_BRIDGE_HLEGACY_REG 0x0A +#define HLEGACY_SMI_PIN_VALUE BIT12 +#define QUARK_NC_HOST_BRIDGE_IA32_MTRR_CAP 0x40 +#define QUARK_NC_HOST_BRIDGE_IA32_MTRR_DEF_TYPE 0x41 +#define QUARK_NC_HOST_BRIDGE_MTRR_FIX64K_00000 0x42 +#define QUARK_NC_HOST_BRIDGE_MTRR_FIX16K_80000 0x44 +#define QUARK_NC_HOST_BRIDGE_MTRR_FIX16K_A0000 0x46 +#define QUARK_NC_HOST_BRIDGE_MTRR_FIX4K_C0000 0x48 +#define QUARK_NC_HOST_BRIDGE_MTRR_FIX4K_C8000 0x4A +#define QUARK_NC_HOST_BRIDGE_MTRR_FIX4K_D0000 0x4C +#define QUARK_NC_HOST_BRIDGE_MTRR_FIX4K_D8000 0x4E +#define QUARK_NC_HOST_BRIDGE_MTRR_FIX4K_E0000 0x50 +#define QUARK_NC_HOST_BRIDGE_MTRR_FIX4K_E8000 0x52 +#define QUARK_NC_HOST_BRIDGE_MTRR_FIX4K_F0000 0x54 +#define QUARK_NC_HOST_BRIDGE_MTRR_FIX4K_F8000 0x56 +#define QUARK_NC_HOST_BRIDGE_IA32_MTRR_SMRR_PHYSBASE 0x58 +#define QUARK_NC_HOST_BRIDGE_IA32_MTRR_SMRR_PHYSMASK 0x59 +#define QUARK_NC_HOST_BRIDGE_IA32_MTRR_PHYSBASE0 0x5A +#define QUARK_NC_HOST_BRIDGE_IA32_MTRR_PHYSMASK0 0x5B +#define QUARK_NC_HOST_BRIDGE_IA32_MTRR_PHYSBASE1 0x5C +#define QUARK_NC_HOST_BRIDGE_IA32_MTRR_PHYSMASK1 0x5D +#define QUARK_NC_HOST_BRIDGE_IA32_MTRR_PHYSBASE2 0x5E +#define QUARK_NC_HOST_BRIDGE_IA32_MTRR_PHYSMASK2 0x5F +#define QUARK_NC_HOST_BRIDGE_IA32_MTRR_PHYSBASE3 0x60 +#define QUARK_NC_HOST_BRIDGE_IA32_MTRR_PHYSMASK3 0x61 +#define QUARK_NC_HOST_BRIDGE_IA32_MTRR_PHYSBASE4 0x62 +#define QUARK_NC_HOST_BRIDGE_IA32_MTRR_PHYSMASK4 0x63 +#define QUARK_NC_HOST_BRIDGE_IA32_MTRR_PHYSBASE5 0x64 +#define QUARK_NC_HOST_BRIDGE_IA32_MTRR_PHYSMASK5 0x65 +#define QUARK_NC_HOST_BRIDGE_IA32_MTRR_PHYSBASE6 0x66 +#define QUARK_NC_HOST_BRIDGE_IA32_MTRR_PHYSMASK6 0x67 +#define QUARK_NC_HOST_BRIDGE_IA32_MTRR_PHYSBASE7 0x68 +#define QUARK_NC_HOST_BRIDGE_IA32_MTRR_PHYSMASK7 0x69 + +// +// System On Chip Unit (SOCUnit) Registers. +// +#define QUARK_SCSS_SOC_UNIT_STPDDRCFG 0x00 +#define B_STPDDRCFG_FORCE_RECOVERY BIT0 +#define QUARK_SCSS_SOC_UNIT_SPI_ROM_FUSE 0x25 +#define B_ROM_FUSE_IN_SECURE_SKU BIT6 + +#define QUARK_SCSS_SOC_UNIT_TSCGF1_CONFIG 0x31 +#define B_TSCGF1_CONFIG_ISNSCURRENTSEL_MASK (BIT5 | BIT4 | BIT3) +#define B_TSCGF1_CONFIG_ISNSCURRENTSEL_BP 3 +#define B_TSCGF1_CONFIG_ISNSCHOPSEL_MASK (BIT12 | BIT11 | BIT10 | BIT9 | BIT8) +#define B_TSCGF1_CONFIG_ISNSCHOPSEL_BP 8 +#define B_TSCGF1_CONFIG_IBGEN BIT17 +#define B_TSCGF1_CONFIG_IBGEN_BP 17 +#define B_TSCGF1_CONFIG_IBGCHOPEN BIT18 +#define B_TSCGF1_CONFIG_IBGCHOPEN_BP 18 +#define B_TSCGF1_CONFIG_ISNSINTERNALVREFEN BIT14 +#define B_TSCGF1_CONFIG_ISNSINTERNALVREFEN_BP 14 + +#define QUARK_SCSS_SOC_UNIT_TSCGF2_CONFIG 0x32 +#define B_TSCGF2_CONFIG_IDSCONTROL_MASK 0x0000FFFF +#define B_TSCGF2_CONFIG_IDSCONTROL_BP 0 +#define B_TSCGF2_CONFIG_IDSTIMING_MASK 0xFFFF0000 +#define B_TSCGF2_CONFIG_IDSTIMING_BP 16 + +#define QUARK_SCSS_SOC_UNIT_TSCGF2_CONFIG2 0x33 +#define B_TSCGF2_CONFIG2_ISPARECTRL_MASK 0xFF000000 +#define B_TSCGF2_CONFIG2_ISPARECTRL_BP 24 +#define B_TSCGF2_CONFIG2_ICALCONFIGSEL_MASK (BIT9 | BIT8) +#define B_TSCGF2_CONFIG2_ICALCONFIGSEL_BP 8 +#define B_TSCGF2_CONFIG2_ICALCOARSETUNE_MASK 0x000000FF +#define B_TSCGF2_CONFIG2_ICALCOARSETUNE_BP 0 + +#define QUARK_SCSS_SOC_UNIT_TSCGF3_CONFIG 0x34 +#define B_TSCGF3_CONFIG_ITSRST BIT0 +#define B_TSCGF3_CONFIG_ITSGAMMACOEFF_BP 11 +#define B_TSCGF3_CONFIG_ITSGAMMACOEFF_MASK (0xFFF << B_TSCGF3_CONFIG_ITSGAMMACOEFF_BP) + +#define QUARK_SCSS_SOC_UNIT_SOCCLKEN_CONFIG 0x36 +#define SOCCLKEN_CONFIG_PHY_I_SIDE_RST_L BIT20 +#define SOCCLKEN_CONFIG_PHY_I_CMNRESET_L BIT19 +#define SOCCLKEN_CONFIG_SBI_BB_RST_B BIT18 +#define SOCCLKEN_CONFIG_SBI_RST_100_CORE_B BIT17 +#define SOCCLKEN_CONFIG_BB_RST_B BIT16 + +#define QUARK_SCSS_SOC_UNIT_SOCCLKEN_CONFIG 0x36 + +#define QUARK_SCSS_SOC_UNIT_CFG_STICKY_RW 0x51 +#define B_CFG_STICKY_RW_SMM_VIOLATION BIT0 +#define B_CFG_STICKY_RW_HMB_VIOLATION BIT1 +#define B_CFG_STICKY_RW_IMR_VIOLATION BIT2 +#define B_CFG_STICKY_RW_DECC_VIOLATION BIT3 +#define B_CFG_STICKY_RW_WARM_RST BIT4 +#define B_CFG_STICKY_RW_FORCE_RECOVERY BIT9 +#define B_CFG_STICKY_RW_VIOLATION (B_CFG_STICKY_RW_SMM_VIOLATION | B_CFG_STICKY_RW_HMB_VIOLATION | B_CFG_STICKY_RW_IMR_VIOLATION | B_CFG_STICKY_RW_DECC_VIOLATION) +#define B_CFG_STICKY_RW_ALL (B_CFG_STICKY_RW_VIOLATION | B_CFG_STICKY_RW_WARM_RST) + +// +// iCLK Registers. +// +#define QUARK_ICLK_MUXTOP 0x0140 +#define B_MUXTOP_FLEX2_MASK (BIT25 | BIT24 | BIT23) +#define B_MUXTOP_FLEX2_BP 23 +#define B_MUXTOP_FLEX1_MASK (BIT22 | BIT21 | BIT20) +#define B_MUXTOP_FLEX1_BP 20 + +#define QUARK_ICLK_SSC1 0x0314 +#define QUARK_ICLK_SSC2 0x0414 +#define QUARK_ICLK_SSC3 0x0514 +#define QUARK_ICLK_REF2_DBUFF0 0x2000 + +// +// PCIe AFE Unit Registers (QUARK_SC_PCIE_AFE_SB_PORT_ID). +// +#define QUARK_PCIE_AFE_PCIE_RXPICTRL0_L0 0x2080 +#define QUARK_PCIE_AFE_PCIE_RXPICTRL0_L1 0x2180 +#define OCFGPIMIXLOAD_1_0 BIT6 +#define OCFGPIMIXLOAD_1_0_MASK 0xFFFFFF3F + +// +// QNC ICH Equates +// +#define V_INTEL_VENDOR_ID 0x8086 + +#define PCI_BUS_NUMBER_QNC 0x00 + +// +// PCI to LPC Bridge Registers (D31:F0) +// +#define PCI_DEVICE_NUMBER_QNC_LPC 31 +#define PCI_FUNCTION_NUMBER_QNC_LPC 0 + +#define R_QNC_LPC_VENDOR_ID 0x00 +#define V_LPC_VENDOR_ID V_INTEL_VENDOR_ID +#define R_QNC_LPC_DEVICE_ID 0x02 +#define QUARK_V_LPC_DEVICE_ID_0 0x095E +#define R_QNC_LPC_REV_ID 0x08 + +#define R_QNC_LPC_SMBUS_BASE 0x40 //~0x43 +#define B_QNC_LPC_SMBUS_BASE_EN (BIT31) +#define B_QNC_LPC_SMBUS_BASE_MASK 0x0000FFC0 //[15:6] +// +// SMBus register offsets from SMBA - "SMBA" (D31:F0:R40h) +// Suggested Value for SMBA = 0x1040 +// +#define R_QNC_SMBUS_HCTL 0x00 // Host Control Register R/W +#define B_QNC_SMBUS_START (BIT4) // Start/Stop +#define V_QNC_SMBUS_HCTL_CMD_QUICK 0 +#define V_QNC_SMBUS_HCTL_CMD_BYTE 1 +#define V_QNC_SMBUS_HCTL_CMD_BYTE_DATA 2 +#define V_QNC_SMBUS_HCTL_CMD_WORD_DATA 3 +#define V_QNC_SMBUS_HCTL_CMD_PROCESS_CALL 4 +#define V_QNC_SMBUS_HCTL_CMD_BLOCK 5 + +#define R_QNC_SMBUS_HSTS 0x01 // Host Status Register R/W +#define B_QNC_SMBUS_BERR (BIT2) // BUS Error +#define B_QNC_SMBUS_DERR (BIT1) // Device Error +#define B_QNC_SMBUS_BYTE_DONE_STS (BIT0) // Completion Status +#define B_QNC_SMBUS_HSTS_ALL 0x07 + +#define R_QNC_SMBUS_HCLK 0x02 // Host Clock Divider Register R/W +#define V_QNC_SMBUS_HCLK_100KHZ 0x0054 + +#define R_QNC_SMBUS_TSA 0x04 // Transmit Slave Address Register R/W +#define V_QNC_SMBUS_RW_SEL_READ 1 +#define V_QNC_SMBUS_RW_SEL_WRITE 0 + +#define R_QNC_SMBUS_HCMD 0x05 // Host Command Register R/W +#define R_QNC_SMBUS_HD0 0x06 // Data 0 Register R/W +#define R_QNC_SMBUS_HD1 0x07 // Data 1 Register R/W +#define R_QNC_SMBUS_HBD 0x20 // Host Block Data Register R/W [255:0] ~ 3Fh + +#define R_QNC_LPC_GBA_BASE 0x44 +#define B_QNC_LPC_GPA_BASE_MASK 0x0000FFC0 +// +// GPIO register offsets from GBA - "GPIO" (D31:F0:R44h) +// Suggested Value for GBA = 0x1080 +// +#define R_QNC_GPIO_CGEN_CORE_WELL 0x00 +#define R_QNC_GPIO_CGIO_CORE_WELL 0x04 +#define R_QNC_GPIO_CGLVL_CORE_WELL 0x08 +#define R_QNC_GPIO_CGTPE_CORE_WELL 0x0C // Core well GPIO Trigger Positive Edge Enable +#define R_QNC_GPIO_CGTNE_CORE_WELL 0x10 // Core well GPIO Trigger Negative Edge Enable +#define R_QNC_GPIO_CGGPE_CORE_WELL 0x14 // Core well GPIO GPE Enable +#define R_QNC_GPIO_CGSMI_CORE_WELL 0x18 // Core well GPIO SMI Enable +#define R_QNC_GPIO_CGTS_CORE_WELL 0x1C // Core well GPIO Trigger Status +#define R_QNC_GPIO_RGEN_RESUME_WELL 0x20 +#define R_QNC_GPIO_RGIO_RESUME_WELL 0x24 +#define R_QNC_GPIO_RGLVL_RESUME_WELL 0x28 +#define R_QNC_GPIO_RGTPE_RESUME_WELL 0x2C // Resume well GPIO Trigger Positive Edge Enable +#define R_QNC_GPIO_RGTNE_RESUME_WELL 0x30 // Resume well GPIO Trigger Negative Edge Enable +#define R_QNC_GPIO_RGGPE_RESUME_WELL 0x34 // Resume well GPIO GPE Enable +#define R_QNC_GPIO_RGSMI_RESUME_WELL 0x38 // Resume well GPIO SMI Enable +#define R_QNC_GPIO_RGTS_RESUME_WELL 0x3C // Resume well GPIO Trigger Status +#define R_QNC_GPIO_CNMIEN_CORE_WELL 0x40 // Core well GPIO NMI Enable +#define R_QNC_GPIO_RNMIEN_RESUME_WELL 0x44 // Resume well GPIO NMI Enable + +#define R_QNC_LPC_PM1BLK 0x48 +#define B_QNC_LPC_PM1BLK_MASK 0x0000FFF0 +// +// ACPI register offsets from PM1BLK - "ACPI PM1 Block" (D31:F0:R48h) +// Suggested Value for PM1BLK = 0x1000 +// +#define R_QNC_PM1BLK_PM1S 0x00 +#define S_QNC_PM1BLK_PM1S 2 +#define B_QNC_PM1BLK_PM1S_ALL (BIT15+BIT14+BIT10+BIT5+BIT0) +#define B_QNC_PM1BLK_PM1S_WAKE (BIT15) +#define B_QNC_PM1BLK_PM1S_PCIEWSTS (BIT14) +#define B_QNC_PM1BLK_PM1S_RTC (BIT10) +#define B_QNC_PM1BLK_PM1S_GLOB (BIT5) +#define B_QNC_PM1BLK_PM1S_TO (BIT0) +#define N_QNC_PM1BLK_PM1S_RTC 10 + + +#define R_QNC_PM1BLK_PM1E 0x02 +#define S_QNC_PM1BLK_PM1E 2 +#define B_QNC_PM1BLK_PM1E_PWAKED (BIT14) +#define B_QNC_PM1BLK_PM1E_RTC (BIT10) +#define B_QNC_PM1BLK_PM1E_GLOB (BIT5) +#define N_QNC_PM1BLK_PM1E_RTC 10 + +#define R_QNC_PM1BLK_PM1C 0x04 +#define B_QNC_PM1BLK_PM1C_SLPEN (BIT13) +#define B_QNC_PM1BLK_PM1C_SLPTP (BIT12+BIT11+BIT10) +#define V_S0 0x00000000 +#define V_S3 0x00001400 +#define V_S4 0x00001800 +#define V_S5 0x00001C00 +#define B_QNC_PM1BLK_PM1C_SCIEN (BIT0) + +#define R_QNC_PM1BLK_PM1T 0x08 + +#define R_QNC_LPC_GPE0BLK 0x4C +#define B_QNC_LPC_GPE0BLK_MASK 0x0000FFC0 +// Suggested Value for GPE0BLK = 0x10C0 +// +#define R_QNC_GPE0BLK_GPE0S 0x00 // General Purpose Event 0 Status +#define S_QNC_GPE0BLK_GPE0S 4 +#define B_QNC_GPE0BLK_GPE0S_ALL 0x00003F800 // used to clear the status reg +#define B_QNC_GPE0BLK_GPE0S_PCIE (BIT17) // PCIE +#define B_QNC_GPE0BLK_GPE0S_GPIO (BIT14) // GPIO +#define B_QNC_GPE0BLK_GPE0S_EGPE (BIT13) // External GPE +#define N_QNC_GPE0BLK_GPE0S_THRM 12 + +#define R_QNC_GPE0BLK_GPE0E 0x04 // General Purpose Event 0 Enable +#define S_QNC_GPE0BLK_GPE0E 4 +#define B_QNC_GPE0BLK_GPE0E_PCIE (BIT17) // PCIE +#define B_QNC_GPE0BLK_GPE0E_GPIO (BIT14) // GPIO +#define B_QNC_GPE0BLK_GPE0E_EGPE (BIT13) // External GPE +#define N_QNC_GPE0BLK_GPE0E_THRM 12 + +#define R_QNC_GPE0BLK_SMIE 0x10 // SMI_B Enable +#define S_QNC_GPE0BLK_SMIE 4 +#define B_QNC_GPE0BLK_SMIE_ALL 0x0003871F +#define B_QNC_GPE0BLK_SMIE_APM (BIT4) // APM +#define B_QNC_GPE0BLK_SMIE_SLP (BIT2) // Sleep +#define B_QNC_GPE0BLK_SMIE_SWT (BIT1) // Software Timer +#define N_QNC_GPE0BLK_SMIE_GPIO 9 +#define N_QNC_GPE0BLK_SMIE_ESMI 8 +#define N_QNC_GPE0BLK_SMIE_APM 4 +#define N_QNC_GPE0BLK_SMIE_SPI 3 +#define N_QNC_GPE0BLK_SMIE_SLP 2 +#define N_QNC_GPE0BLK_SMIE_SWT 1 + +#define R_QNC_GPE0BLK_SMIS 0x14 // SMI Status Register. +#define S_QNC_GPE0BLK_SMIS 4 +#define B_QNC_GPE0BLK_SMIS_ALL 0x0003871F +#define B_QNC_GPE0BLK_SMIS_EOS (BIT31) // End of SMI +#define B_QNC_GPE0BLK_SMIS_APM (BIT4) // APM +#define B_QNC_GPE0BLK_SMIS_SPI (BIT3) // SPI +#define B_QNC_GPE0BLK_SMIS_SLP (BIT2) // Sleep +#define B_QNC_GPE0BLK_SMIS_SWT (BIT1) // Software Timer +#define B_QNC_GPE0BLK_SMIS_BIOS (BIT0) // BIOS +#define N_QNC_GPE0BLK_SMIS_GPIO 9 +#define N_QNC_GPE0BLK_SMIS_APM 4 +#define N_QNC_GPE0BLK_SMIS_SPI 3 +#define N_QNC_GPE0BLK_SMIS_SLP 2 +#define N_QNC_GPE0BLK_SMIS_SWT 1 + +#define R_QNC_GPE0BLK_PMCW 0x28 // Power Management Configuration Core Well +#define B_QNC_GPE0BLK_PMCW_PSE (BIT31) // Periodic SMI Enable + +#define R_QNC_GPE0BLK_PMSW 0x2C // Power Management Configuration Suspend/Resume Well +#define B_QNC_GPE0BLK_PMSW_DRAM_INIT (BIT0) // Dram Initialization Sctrachpad + +#define R_QNC_LPC_ACTL 0x58 +#define V_QNC_LPC_ACTL_SCIS_IRQ9 0x00 + +// +// Number of PIRQs supported. PIRQA~PIRQH +// +#define QNC_NUMBER_PIRQS 8 +#define R_QNC_LPC_PIRQA_ROUT 0x60 +#define R_QNC_LPC_PIRQB_ROUT 0x61 +#define R_QNC_LPC_PIRQC_ROUT 0x62 +#define R_QNC_LPC_PIRQD_ROUT 0x63 +#define R_QNC_LPC_PIRQE_ROUT 0x64 +#define R_QNC_LPC_PIRQF_ROUT 0x65 +#define R_QNC_LPC_PIRQG_ROUT 0x66 +#define R_QNC_LPC_PIRQH_ROUT 0x67 + +// +// Bit values are the same for R_TNC_LPC_PIRQA_ROUT to +// R_TNC_LPC_PIRQH_ROUT +#define B_QNC_LPC_PIRQX_ROUT (BIT3+BIT2+BIT1+BIT0) + +#define R_QNC_LPC_WDTBA 0x84 +// Watchdog Timer register offsets from WDTBASE (in R_QNC_LPC_WDTBA)------------BEGIN +#define R_QNC_LPC_WDT_WDTCR 0x10 +#define R_QNC_LPC_WDT_WDTLR 0x18 +// Watchdog Timer register offsets from WDTBASE (in R_QNC_LPC_WDTBA)--------------END + +#define R_QNC_LPC_FWH_BIOS_DEC 0xD4 +#define B_QNC_LPC_FWH_BIOS_DEC_F8 (BIT31) +#define B_QNC_LPC_FWH_BIOS_DEC_F0 (BIT30) +#define B_QNC_LPC_FWH_BIOS_DEC_E8 (BIT29) +#define B_QNC_LPC_FWH_BIOS_DEC_E0 (BIT28) +#define B_QNC_LPC_FWH_BIOS_DEC_D8 (BIT27) +#define B_QNC_LPC_FWH_BIOS_DEC_D0 (BIT26) +#define B_QNC_LPC_FWH_BIOS_DEC_C8 (BIT25) +#define B_QNC_LPC_FWH_BIOS_DEC_C0 (BIT24) + +#define R_QNC_LPC_BIOS_CNTL 0xD8 +#define S_QNC_LPC_BIOS_CNTL 4 +#define B_QNC_LPC_BIOS_CNTL_PFE (BIT8) +#define B_QNC_LPC_BIOS_CNTL_SMM_BWP (BIT5) +#define B_QNC_LPC_BIOS_CNTL_BCD (BIT2) +#define B_QNC_LPC_BIOS_CNTL_BLE (BIT1) +#define B_QNC_LPC_BIOS_CNTL_BIOSWE (BIT0) +#define N_QNC_LPC_BIOS_CNTL_BLE 1 +#define N_QNC_LPC_BIOS_CNTL_BIOSWE 0 + +#define R_QNC_LPC_RCBA 0xF0 +#define B_QNC_LPC_RCBA_MASK 0xFFFFC000 +#define B_QNC_LPC_RCBA_EN (BIT0) + +//--------------------------------------------------------------------------- +// Fixed IO Decode on QuarkNcSocId +// +// 20h(2B) 24h(2B) 28h(2B) 2Ch(2B) 30h(2B) 34h(2B) 38h(2B) 3Ch(2B) : R/W 8259 master +// 40h(3B): R/W 8254 +// 43h(1B): W 8254 +// 50h(3B): R/W 8254 +// 53h(1B): W 8254 +// 61h(1B): R/W NMI Controller +// 63h(1B): R/W NMI Controller - can be disabled +// 65h(1B): R/W NMI Controller - can be disabled +// 67h(1B): R/W NMI Controller - can be disabled +// 70h(1B): W NMI & RTC +// 71h(1B): R/W RTC +// 72h(1B): R RTC; W NMI&RTC +// 73h(1B): R/W RTC +// 74h(1B): R RTC; W NMI&RTC +// 75h(1B): R/W RTC +// 76h(1B): R RTC; W NMI&RTC +// 77h(1B): R/W RTC +// 84h(3B): R/W Internal/LPC +// 88h(1B): R/W Internal/LPC +// 8Ch(3B): R/W Internal/LPC +// A0h(2B) A4h(2B) A8h(2B) ACh(2B) B0h(2B) B4h(2B) B8h(2B) BCh(2B): R/W 8259 slave +// B2h(1B) B3h(1B): R/W Power management +// 3B0h-3BBh: R/W VGA +// 3C0h-3DFh: R/W VGA +// CF8h(4B): R/W Internal +// CF9h(1B): R/W LPC +// CFCh(4B): R/W Internal +//--------------------------------------------------------------------------- + +#define R_APM_CNT 0xB2 + +// +// Reset Generator I/O Port +// +#define RST_CNT 0xCF9 +#define B_RST_CNT_COLD_RST (BIT3) // Cold reset +#define B_RST_CNT_WARM_RST (BIT1) // Warm reset + +// +// Processor interface registers (NMI) +// + +#define PCI_DEVICE_NUMBER_QNC_IOSF2AHB_0 20 +#define PCI_DEVICE_NUMBER_QNC_IOSF2AHB_1 21 +#define PCI_FUNCTION_NUMBER_QNC_IOSF2AHB 0 + +// +// Pci Express Root Ports (D23:F0/F1) +// +#define PCI_DEVICE_NUMBER_PCIE_ROOTPORT 23 +#define PCI_FUNCTION_NUMBER_PCIE_ROOTPORT_0 0 +#define PCI_FUNCTION_NUMBER_PCIE_ROOTPORT_1 1 + +#define MAX_PCI_EXPRESS_ROOT_PORTS 2 + +#define R_QNC_PCIE_BNUM 0x18 +#define R_QNC_PCIE_CAP_PTR 0x34 + +#define PCIE_CAPID 0x10 //PCIE Capability ID +#define PCIE_CAP_EXT_HEARDER_OFFSET 0x100 //PCIE Capability ID +#define PCIE_DEV_CAP_OFFSET 0x04 //PCIE Device Capability reg offset +#define PCIE_LINK_CAP_OFFSET 0x0C //PCIE Link Capability reg offset +#define PCIE_LINK_CNT_OFFSET 0x10 //PCIE Link control reg offset +#define PCIE_LINK_STS_OFFSET 0x12 //PCIE Link status reg offset +#define PCIE_SLOT_CAP_OFFSET 0x14 //PCIE Link Capability reg offset + +#define R_QNC_PCIE_XCAP 0x42 //~ 43h +#define B_QNC_PCIE_XCAP_SI (BIT8) //slot implemented +#define R_QNC_PCIE_DCAP 0x44 //~ 47h +#define B_QNC_PCIE_DCAP_E1AL (BIT11 | BIT10 | BIT9) // L1 Acceptable exit latency +#define B_QNC_PCIE_DCAP_E0AL (BIT8 | BIT7 | BIT6) // L0 Acceptable exit latency +#define R_QNC_PCIE_DCTL 0x48 //~ 49h +#define B_QNC_PCIE_DCTL_URE (BIT3) //Unsupported Request Reporting Enable +#define B_QNC_PCIE_DCTL_FEE (BIT2) //Fatal error Reporting Enable +#define B_QNC_PCIE_DCTL_NFE (BIT1) //Non Fatal error Reporting Enable +#define B_QNC_PCIE_DCTL_CEE (BIT0) //Correctable error Reporting Enable +#define R_QNC_PCIE_LCAP 0x4C //~ 4Fh +#define B_QNC_PCIE_LCAP_CPM (BIT18) //clock power management supported +#define B_QNC_PCIE_LCAP_EL1_MASK (BIT17 | BIT16 | BIT15) //L1 Exit latency mask +#define B_QNC_PCIE_LCAP_EL0_MASK (BIT14 | BIT13 | BIT12) //L0 Exit latency mask +#define B_QNC_PCIE_LCAP_APMS_MASK (BIT11 | BIT10) //Active state link PM support mask +#define V_QNC_PCIE_LCAP_APMS_OFFSET 10 //Active state link PM support mask +#define R_QNC_PCIE_LCTL 0x50 //~ 51h +#define B_QNC_PCIE_LCTL_CCC (BIT6) // Clock clock configuration +#define B_QNC_PCIE_LCTL_RL (BIT5) // Retrain link +#define R_QNC_PCIE_LSTS 0x52 //~ 53h +#define B_QNC_PCIE_LSTS_SCC (BIT12) //Slot clock configuration +#define B_QNC_PCIE_LSTS_LT (BIT11) //Link training +#define R_QNC_PCIE_SLCAP 0x54 //~ 57h +#define B_QNC_PCIE_SLCAP_MASK_RSV_VALUE 0x0006007F +#define V_QNC_PCIE_SLCAP_SLV 0x0A //Slot power limit value [14:7] +#define V_QNC_PCIE_SLCAP_SLV_OFFSET 7 //Slot power limit value offset is 7 [14:7] +#define V_QNC_PCIE_SLCAP_PSN_OFFSET 19 //Slot number offset is 19 [31:19] +#define R_QNC_PCIE_SLCTL 0x58 //~ 59h +#define B_QNC_PCIE_SLCTL_HPE (BIT5) // Hot plug interrupt enable +#define B_QNC_PCIE_SLCTL_PDE (BIT3) // Presense detect change enable +#define B_QNC_PCIE_SLCTL_ABE (BIT0) // Attention Button Pressed Enable +#define R_QNC_PCIE_SLSTS 0x5A //~ 5Bh +#define B_QNC_PCIE_SLSTS_PDS (BIT6) // Present Detect State = 1b : has device connected +#define B_QNC_PCIE_SLSTS_PDC (BIT3) // Present Detect changed = 1b : PDS state has changed +#define B_QNC_PCIE_SLSTS_ABP (BIT0) // Attention Button Pressed +#define R_QNC_PCIE_RCTL 0x5C //~ 5Dh +#define B_QNC_PCIE_RCTL_PIE (BIT3) //Root PCI-E PME Interrupt Enable +#define B_QNC_PCIE_RCTL_SFE (BIT2) //Root PCI-E System Error on Fatal Error Enable +#define B_QNC_PCIE_RCTL_SNE (BIT1) //Root PCI-E System Error on Non-Fatal Error Enable +#define B_QNC_PCIE_RCTL_SCE (BIT0) //Root PCI-E System Error on Correctable Error Enable +#define R_QNC_PCIE_SVID 0x94 //~ 97h +#define R_QNC_PCIE_CCFG 0xD0 //~ D3h +#define B_QNC_PCIE_CCFG_UPSD (BIT24) // Upstream Posted Split Disable +#define B_QNC_PCIE_CCFG_UNRS (BIT15) // Upstream Non-Posted Request Size +#define B_QNC_PCIE_CCFG_UPRS (BIT14) // Upstream Posted Request Size +#define R_QNC_PCIE_MPC2 0xD4 //~ D7h +#define B_QNC_PCIE_MPC2_IPF (BIT11) // ISOF Packet Fast Transmit Mode +#define R_QNC_PCIE_MPC 0xD8 //~ DBh +#define B_QNC_PCIE_MPC_PMCE (BIT31) // PM SCI Enable +#define B_QNC_PCIE_MPC_HPCE (BIT30) // Hot plug SCI enable + +#define B_QNC_PCIE_MPC_HPME (BIT1) // Hot plug SMI enable +#define B_QNC_PCIE_MPC_PMME (BIT0) // PM SMI Enable +#define R_QNC_PCIE_IOSFSBCTL 0xF6 +#define B_QNC_PCIE_IOSFSBCTL_SBIC_MASK (BIT1 | BIT0) // IOSF Sideband ISM Idle Counter. +#define B_QNC_PCIE_IOSFSBCTL_SBIC_IDLE_NEVER (BIT1 | BIT0) // Never transition to IDLE. + +#define V_PCIE_MAX_TRY_TIMES 200 + +// +// Misc PCI register offsets and sizes +// +#define R_EFI_PCI_SVID 0x2C + +// +// IO_APIC +// +#define IOAPIC_BASE 0xFEC00000 +#define IOAPIC_SIZE 0x1000 + +// +// Chipset configuration registers RCBA - "Root Complex Base Address" (D31:F0:RF0h) +// Suggested Value for RCBA = 0xFED1C000 +// + +#define R_QNC_RCRB_SPIBASE 0x3020 // SPI (Serial Peripheral Interface) in RCRB +#define R_QNC_RCRB_SPIS (R_QNC_RCRB_SPIBASE + 0x00) // SPI Status +#define B_QNC_RCRB_SPIS_SCL (BIT15) // SPI Configuration Lockdown +#define B_QNC_RCRB_SPIS_BAS (BIT3) // Blocked Access Status +#define B_QNC_RCRB_SPIS_CDS (BIT2) // Cycle Done Status +#define B_QNC_RCRB_SPIS_SCIP (BIT0) // SPI Cycle in Progress + +#define R_QNC_RCRB_SPIC (R_QNC_RCRB_SPIBASE + 0x02) // SPI Control +#define B_QNC_RCRB_SPIC_DC (BIT14) // SPI Data Cycle Enable +#define B_QNC_RCRB_SPIC_DBC 0x3F00 // SPI Data Byte Count (1..8,16,24,32,40,48,56,64) +#define B_QNC_RCRB_SPIC_COP (BIT6+BIT5+BIT4) // SPI Cycle Opcode Pointer +#define B_QNC_RCRB_SPIC_SPOP (BIT3) // Sequence Prefix Opcode Pointer +#define B_QNC_RCRB_SPIC_ACS (BIT2) // SPI Atomic Cycle Sequence +#define B_QNC_RCRB_SPIC_SCGO (BIT1) // SPI Cycle Go + +#define R_QNC_RCRB_SPIA (R_QNC_RCRB_SPIBASE + 0x04) // SPI Address +#define B_QNC_RCRB_SPIA_MASK 0x00FFFFFF // SPI Address mask +#define R_QNC_RCRB_SPID0 (R_QNC_RCRB_SPIBASE + 0x08) // SPI Data 0 +#define R_QNC_RCRB_SPIPREOP (R_QNC_RCRB_SPIBASE + 0x54) // Prefix Opcode Configuration +#define R_QNC_RCRB_SPIOPTYPE (R_QNC_RCRB_SPIBASE + 0x56) // Opcode Type Configuration +#define B_QNC_RCRB_SPIOPTYPE_NOADD_READ 0 +#define B_QNC_RCRB_SPIOPTYPE_NOADD_WRITE (BIT0) +#define B_QNC_RCRB_SPIOPTYPE_ADD_READ (BIT1) +#define B_QNC_RCRB_SPIOPTYPE_ADD_WRITE (BIT0 + BIT1) +#define R_QNC_RCRB_SPIOPMENU (R_QNC_RCRB_SPIBASE + 0x58) // Opcode Menu Configuration //R_OPMENU + +#define R_QNC_RCRB_SPIPBR0 (R_QNC_RCRB_SPIBASE + 0x60) // Protected BIOS Range 0. +#define R_QNC_RCRB_SPIPBR1 (R_QNC_RCRB_SPIBASE + 0x64) // Protected BIOS Range 1. +#define R_QNC_RCRB_SPIPBR2 (R_QNC_RCRB_SPIBASE + 0x68) // Protected BIOS Range 2. +#define B_QNC_RCRB_SPIPBRn_WPE (BIT31) // Write Protection Enable for above 3 registers. + +#define R_QNC_RCRB_AGENT0IR 0x3140 // AGENT0 interrupt route +#define R_QNC_RCRB_AGENT1IR 0x3142 // AGENT1 interrupt route +#define R_QNC_RCRB_AGENT2IR 0x3144 // AGENT2 interrupt route +#define R_QNC_RCRB_AGENT3IR 0x3146 // AGENT3 interrupt route + +#endif diff --git a/src/soc/intel/quark/include/soc/romstage.h b/src/soc/intel/quark/include/soc/romstage.h index a35f4a6..6b63ed0 100644 --- a/src/soc/intel/quark/include/soc/romstage.h +++ b/src/soc/intel/quark/include/soc/romstage.h @@ -22,7 +22,9 @@ #error "Don't include romstage.h from a ramstage compilation unit!" #endif +#include <fsp/romstage.h> #include <fsp/util.h> +#include <soc/QuarkNcSocId.h> int set_base_address_and_enable_uart(u8 bus, u8 dev, u8 func, u32 mmio_base); diff --git a/src/soc/intel/quark/romstage/romstage.c b/src/soc/intel/quark/romstage/romstage.c index c1bc17e..7434823 100644 --- a/src/soc/intel/quark/romstage/romstage.c +++ b/src/soc/intel/quark/romstage/romstage.c @@ -16,7 +16,14 @@ #include <arch/early_variables.h> #include <console/console.h> +#include <cpu/x86/msr.h> +#include <cpu/x86/mtrr.h> +#include <device/pci.h> +#include <device/pci_def.h> +#include <fsp/util.h> +#include <soc/intel/common/util.h> #include <soc/pm.h> +#include <soc/romstage.h> static struct chipset_power_state power_state CAR_GLOBAL; @@ -28,3 +35,200 @@ struct chipset_power_state *fill_power_state(void) printk(BIOS_DEBUG, "prev_sleep_state %d\n", ps->prev_sleep_state); return ps; } + +static void mea_write(uint32_t reg_address) +{ + device_t host_bridge_dev = PCI_DEV(0, 0, 0); + + pci_write_config32(host_bridge_dev, QNC_ACCESS_PORT_MEA, reg_address + & QNC_MEA_MASK); +} + +static void mcr_write(uint8_t opcode, uint8_t port, uint32_t reg_address) +{ + device_t host_bridge_dev = PCI_DEV(0, 0, 0); + + pci_write_config32(host_bridge_dev, QNC_ACCESS_PORT_MCR, + (opcode << QNC_MCR_OP_OFFSET) + | ((uint32_t)port << QNC_MCR_PORT_OFFSET) + | ((reg_address & QNC_MCR_MASK) << QNC_MCR_REG_OFFSET) + | QNC_MCR_BYTE_ENABLES); +} + +static uint32_t mdr_read(void) +{ + device_t host_bridge_dev = PCI_DEV(0, 0, 0); + + return pci_read_config32(host_bridge_dev, QNC_ACCESS_PORT_MDR); +} + +static void mdr_write(uint32_t value) +{ + device_t host_bridge_dev = PCI_DEV(0, 0, 0); + + pci_write_config32(host_bridge_dev, QNC_ACCESS_PORT_MDR, value); +} + +msr_t soc_mtrr_read(unsigned long index) +{ + uint32_t offset; + union { + uint64_t u64; + msr_t msr; + } value; + + /* Convert from MTTR index to host brigde offset (Datasheet 12.7.2) */ + if (index == MTRR_CAP_MSR) + offset = QUARK_NC_HOST_BRIDGE_IA32_MTRR_CAP; + else if (index == MTRR_DEF_TYPE_MSR) + offset = QUARK_NC_HOST_BRIDGE_IA32_MTRR_DEF_TYPE; + else if (index == MTRR_FIX_64K_00000) + offset = QUARK_NC_HOST_BRIDGE_MTRR_FIX64K_00000; + else if ((index >= MTRR_FIX_16K_80000) && (index <= MTRR_FIX_16K_A0000)) + offset = ((index - MTRR_FIX_16K_80000) << 1) + + QUARK_NC_HOST_BRIDGE_MTRR_FIX16K_80000; + else if ((index >= MTRR_FIX_4K_C0000) && (index <= MTRR_FIX_4K_F8000)) + offset = ((index - MTRR_FIX_4K_C0000) << 1) + + QUARK_NC_HOST_BRIDGE_IA32_MTRR_PHYSBASE0; + else if ((index >= MTRR_PHYS_BASE(0)) && (index <= MTRR_PHYS_MASK(7))) + offset = (index - MTRR_PHYS_BASE(0)) + + QUARK_NC_HOST_BRIDGE_IA32_MTRR_PHYSBASE0; + else { + printk(BIOS_DEBUG, "index: 0x%08lx\n", index); + die("Invalid MTTR index specified!\n"); + } + + /* Read the low 32-bits of the register */ + mea_write(offset); + mcr_write(QUARK_OPCODE_READ, QUARK_NC_HOST_BRIDGE_SB_PORT_ID, offset); + value.u64 = mdr_read(); + + /* For 64-bit registers, read the upper 32-bits */ + if ((offset >= QUARK_NC_HOST_BRIDGE_MTRR_FIX64K_00000) + && (offset <= QUARK_NC_HOST_BRIDGE_MTRR_FIX4K_F8000)) { + offset += 1; + mea_write(offset); + mcr_write(QUARK_OPCODE_READ, QUARK_NC_HOST_BRIDGE_SB_PORT_ID, + offset); + value.u64 |= mdr_read(); + } + return value.msr; +} + +void soc_mtrr_write(unsigned long index, msr_t msr) +{ + uint32_t offset; + union { + uint32_t u32[2]; + msr_t msr; + } value; + + /* Convert from MTTR index to host brigde offset (Datasheet 12.7.2) */ + if (index == MTRR_CAP_MSR) + offset = QUARK_NC_HOST_BRIDGE_IA32_MTRR_CAP; + else if (index == MTRR_DEF_TYPE_MSR) + offset = QUARK_NC_HOST_BRIDGE_IA32_MTRR_DEF_TYPE; + else if (index == MTRR_FIX_64K_00000) + offset = QUARK_NC_HOST_BRIDGE_MTRR_FIX64K_00000; + else if ((index >= MTRR_FIX_16K_80000) && (index <= MTRR_FIX_16K_A0000)) + offset = ((index - MTRR_FIX_16K_80000) << 1) + + QUARK_NC_HOST_BRIDGE_MTRR_FIX16K_80000; + else if ((index >= MTRR_FIX_4K_C0000) && (index <= MTRR_FIX_4K_F8000)) + offset = ((index - MTRR_FIX_4K_C0000) << 1) + + QUARK_NC_HOST_BRIDGE_IA32_MTRR_PHYSBASE0; + else if ((index >= MTRR_PHYS_BASE(0)) && (index <= MTRR_PHYS_MASK(7))) + offset = (index - MTRR_PHYS_BASE(0)) + + QUARK_NC_HOST_BRIDGE_IA32_MTRR_PHYSBASE0; + else { + printk(BIOS_DEBUG, "index: 0x%08lx\n", index); + die("Invalid MTTR index specified!\n"); + } + + /* Write the low 32-bits of the register */ + value.msr = msr; + mea_write(offset); + mdr_write(value.u32[0]); + mcr_write(QUARK_OPCODE_WRITE, QUARK_NC_HOST_BRIDGE_SB_PORT_ID, offset); + + /* For 64-bit registers, write the upper 32-bits */ + if ((offset >= QUARK_NC_HOST_BRIDGE_MTRR_FIX64K_00000) + && (offset <= QUARK_NC_HOST_BRIDGE_MTRR_FIX4K_F8000)) { + offset += 1; + mea_write(offset); + mdr_write(value.u32[1]); + mcr_write(QUARK_OPCODE_WRITE, QUARK_NC_HOST_BRIDGE_SB_PORT_ID, + offset); + } +} + +asmlinkage void *soc_set_mtrrs(uint32_t *top_of_stack) +{ + union { + uint32_t u32[2]; + uint64_t u64; + msr_t msr; + } data; + uint32_t mtrr_count; + uint32_t mtrr_reg; + + /* + * The stack contents are initialized in src/soc/intel/common/stack.c + * to be the following: + * + * * + * * + * * + * +36: MTRR mask 1 63:32 + * +32: MTRR mask 1 31:0 + * +28: MTRR base 1 63:32 + * +24: MTRR base 1 31:0 + * +20: MTRR mask 0 63:32 + * +16: MTRR mask 0 31:0 + * +12: MTRR base 0 63:32 + * +8: MTRR base 0 31:0 + * +4: Number of MTRRs to setup (described above) + * top_of_stack --> +0: Number of variable MTRRs to clear + * + * This routine: + * * Clears all of the variable MTRRs + * * Initializes the variable MTRRs with the data passed in + * * Returns the new top of stack after removing all of the + * data passed in. + */ + + /* Clear all of the variable MTRRs (base and mask). */ + mtrr_reg = MTRR_PHYS_BASE(0); + mtrr_count = (*top_of_stack++) << 1; + data.u64 = 0; + while (mtrr_count-- > 0) + soc_mtrr_write(mtrr_reg, data.msr); + + /* Setup the specified variable MTRRs (only lower 32-bits valid) */ + mtrr_reg = MTRR_PHYS_BASE(0); + mtrr_count = *top_of_stack++; + while (mtrr_count-- > 0) { + data.u32[0] = *top_of_stack; + top_of_stack += 2; + soc_mtrr_write(mtrr_reg++, data.msr); /* Base */ + data.u32[0] = *top_of_stack; + top_of_stack += 2; + soc_mtrr_write(mtrr_reg++, data.msr); /* Mask */ + } + + /* Return the top of stack */ + return top_of_stack; +} + +asmlinkage void soc_enable_mtrrs(void) +{ + union { + uint32_t u32[2]; + uint64_t u64; + msr_t msr; + } data; + + /* Enable MTRR. */ + data.msr = soc_mtrr_read(MTRR_DEF_TYPE_MSR); + data.u32[0] |= MTRR_DEF_TYPE_EN; + soc_mtrr_write(MTRR_DEF_TYPE_MSR, data.msr); +}

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New patch to review for coreboot: soc/intel/common: Use SoC specific routine to read/write MTRRs
by Leroy P Leahy 31 Jan '16

31 Jan '16

Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13529 -gerrit commit 1e09578e8c0b7a656517e771e4f91b6913c18529 Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Fri Jan 29 14:35:13 2016 -0800 soc/intel/common: Use SoC specific routine to read/write MTRRs The registers associated with the MTRRs for Quark are referenced through a port on the host bridge. Support the standard configurations by providing a weak routines which just do a rdmsr/wrmsr. Testing: * Edit the src/mainboard/intel/galileo/Makefile.inc file * Add "select DISPLAY_MTRRS" * Add "select HAVE_FSP_PDAT_FILE" * Add "select HAVE_FSP_RAW_BIN" * Add "select HAVE_RMU_FILE" * Place the FSP.bin file in the location specified by CONFIG_FSP_FILE * Place the pdat.bin files in the location specified by CONFIG_FSP_PDAT_FILE * Place the rmu.bin file in the location specified by CONFIG_RMU_FILE * Testing is successful if: * The MTRRs are displayed and * The message "FspTempRamExit returned successfully" is displayed TEST=Build and run on Galileo Change-Id: If2fea66d4b054be4555f5f172ea5945620648325 Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- src/drivers/intel/fsp1_1/Kconfig | 7 +++++ src/drivers/intel/fsp1_1/after_raminit.S | 13 +++++++++ src/drivers/intel/fsp1_1/include/fsp/romstage.h | 2 ++ src/soc/intel/common/util.c | 37 ++++++++++++++++--------- src/soc/intel/common/util.h | 3 ++ 5 files changed, 49 insertions(+), 13 deletions(-) diff --git a/src/drivers/intel/fsp1_1/Kconfig b/src/drivers/intel/fsp1_1/Kconfig index 9b2c463..39c2f6b 100644 --- a/src/drivers/intel/fsp1_1/Kconfig +++ b/src/drivers/intel/fsp1_1/Kconfig @@ -103,6 +103,13 @@ config ROMSTAGE_RAM_STACK_SIZE hex "Size of the romstage RAM stack in bytes" default 0x5000 +config SOC_SETS_MTRRS + bool + default n + help + The SoC needs uses different access methods for reading and writing + the MTRRs. Use SoC specific routines to handle the MTRR access. + config USE_GENERIC_FSP_CAR_INC bool default n diff --git a/src/drivers/intel/fsp1_1/after_raminit.S b/src/drivers/intel/fsp1_1/after_raminit.S index eb99157..7486e33 100644 --- a/src/drivers/intel/fsp1_1/after_raminit.S +++ b/src/drivers/intel/fsp1_1/after_raminit.S @@ -87,6 +87,13 @@ * +0: Number of variable MTRRs to clear */ +#if IS_ENABLED(CONFIG_SOC_SETS_MTRRS) + push %esp + call soc_set_mtrrs + + /* Remove the parameters from the stack */ + movl %eax, %esp +#else /* Clear all of the variable MTRRs. */ popl %ebx movl $MTRR_PHYS_BASE(0), %ecx @@ -129,6 +136,8 @@ dec %ebx jmp 2b 2: +#endif /* CONFIG_SOC_SETS_MTRRS */ + post_code(0x39) /* And enable cache again after setting MTRRs. */ @@ -138,11 +147,15 @@ post_code(0x3a) +#if IS_ENABLED(CONFIG_SOC_SETS_MTRRS) + call soc_enable_mtrrs +#else /* Enable MTRR. */ movl $MTRR_DEF_TYPE_MSR, %ecx rdmsr orl $MTRR_DEF_TYPE_EN, %eax wrmsr +#endif /* CONFIG_SOC_SETS_MTRRS */ post_code(0x3b) diff --git a/src/drivers/intel/fsp1_1/include/fsp/romstage.h b/src/drivers/intel/fsp1_1/include/fsp/romstage.h index 4683f5e..b861eeb 100644 --- a/src/drivers/intel/fsp1_1/include/fsp/romstage.h +++ b/src/drivers/intel/fsp1_1/include/fsp/romstage.h @@ -87,5 +87,7 @@ void soc_display_memory_init_params(const MEMORY_INIT_UPD *old, void soc_memory_init_params(struct romstage_params *params, MEMORY_INIT_UPD *upd); void soc_pre_ram_init(struct romstage_params *params); +asmlinkage void *soc_set_mtrrs(uint32_t *top_of_stack); +asmlinkage void soc_enable_mtrrs(void); #endif /* _COMMON_ROMSTAGE_H_ */ diff --git a/src/soc/intel/common/util.c b/src/soc/intel/common/util.c index dc3f139..64bf61f 100644 --- a/src/soc/intel/common/util.c +++ b/src/soc/intel/common/util.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Intel Corporation. + * Copyright (C) 2015-2016 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -15,22 +15,32 @@ #include <arch/cpu.h> #include <console/console.h> -#include <cpu/x86/msr.h> #include <cpu/x86/mtrr.h> #include <soc/intel/common/util.h> #include <stddef.h> +__attribute__((weak)) msr_t soc_mtrr_read(unsigned long index) +{ + return rdmsr(index); +} + +__attribute__((weak)) void soc_mtrr_write(unsigned long index, msr_t msr) +{ + return wrmsr(index, msr); +} + + uint32_t soc_get_variable_mtrr_count(uint64_t *msr) { union { uint64_t u64; msr_t s; - } mttrcap; + } mtrrcap; - mttrcap.s = rdmsr(MTRR_CAP_MSR); + mtrrcap.s = soc_mtrr_read(MTRR_CAP_MSR); if (msr != NULL) - *msr = mttrcap.u64; - return mttrcap.u64 & MTRR_CAP_VCNT; + *msr = mtrrcap.u64; + return mtrrcap.u64 & MTRR_CAP_VCNT; } static const char *soc_display_mtrr_type(uint32_t type) @@ -84,7 +94,7 @@ static void soc_display_4k_mtrr(uint32_t msr_reg, uint32_t starting_address, msr_t s; } msr; - msr.s = rdmsr(msr_reg); + msr.s = soc_mtrr_read(msr_reg); printk(BIOS_DEBUG, "0x%016llx: %s\n", msr.u64, name); soc_display_mtrr_fixed_types(msr.u64, starting_address, 0x1000); } @@ -97,7 +107,7 @@ static void soc_display_16k_mtrr(uint32_t msr_reg, uint32_t starting_address, msr_t s; } msr; - msr.s = rdmsr(msr_reg); + msr.s = soc_mtrr_read(msr_reg); printk(BIOS_DEBUG, "0x%016llx: %s\n", msr.u64, name); soc_display_mtrr_fixed_types(msr.u64, starting_address, 0x4000); } @@ -109,7 +119,7 @@ static void soc_display_64k_mtrr(void) msr_t s; } msr; - msr.s = rdmsr(MTRR_FIX_64K_00000); + msr.s = soc_mtrr_read(MTRR_FIX_64K_00000); printk(BIOS_DEBUG, "0x%016llx: IA32_MTRR_FIX64K_00000\n", msr.u64); soc_display_mtrr_fixed_types(msr.u64, 0, 0x10000); } @@ -137,12 +147,13 @@ static void soc_display_mtrr_def_type(void) msr_t s; } msr; - msr.s = rdmsr(MTRR_DEF_TYPE_MSR); + msr.s = soc_mtrr_read(MTRR_DEF_TYPE_MSR); printk(BIOS_DEBUG, "0x%016llx: IA32_MTRR_DEF_TYPE:%s%s %s\n", msr.u64, (msr.u64 & MTRR_DEF_TYPE_EN) ? " E," : "", (msr.u64 & MTRR_DEF_TYPE_FIX_EN) ? " FE," : "", - soc_display_mtrr_type((uint32_t)(msr.u64 & MTRR_DEF_TYPE_MASK))); + soc_display_mtrr_type((uint32_t)(msr.u64 & + MTRR_DEF_TYPE_MASK))); } static void soc_display_variable_mtrr(uint32_t msr_reg, int index, @@ -160,8 +171,8 @@ static void soc_display_variable_mtrr(uint32_t msr_reg, int index, msr_t s; } msr_m; - msr_a.s = rdmsr(msr_reg); - msr_m.s = rdmsr(msr_reg + 1); + msr_a.s = soc_mtrr_read(msr_reg); + msr_m.s = soc_mtrr_read(msr_reg + 1); if (msr_m.u64 & MTRR_PHYS_MASK_VALID) { base_address = (msr_a.u64 & 0xfffffffffffff000ULL) & address_mask; diff --git a/src/soc/intel/common/util.h b/src/soc/intel/common/util.h index 8c41151..1579e00 100644 --- a/src/soc/intel/common/util.h +++ b/src/soc/intel/common/util.h @@ -17,9 +17,12 @@ #define _INTEL_COMMON_UTIL_H_ #include <arch/cpu.h> +#include <cpu/x86/msr.h> #include <stdint.h> asmlinkage void soc_display_mtrrs(void); uint32_t soc_get_variable_mtrr_count(uint64_t *msr); +msr_t soc_mtrr_read(unsigned long index); +void soc_mtrr_write(unsigned long index, msr_t msr); #endif /* _INTEL_COMMON_UTIL_H_ */

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coreboot-gerrit January 2016