coreboot-gerrit January 2016

coreboot-gerrit@coreboot.org

1 participants
2471 discussions

Patch set updated for coreboot: mb/intel/d510mo: Use native gfx initialization
by Damien Zammit 28 Jan '16

28 Jan '16

Damien Zammit (damien(a)zamaudio.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13034 -gerrit commit 505f13a3d684a19539164b3609b4b3abb4374f82 Author: Damien Zammit <damien(a)zamaudio.com> Date: Tue Jan 26 13:55:43 2016 +1100 mb/intel/d510mo: Use native gfx initialization Change-Id: Ic4de7a762e90b379be3814afc61467e1cd099215 Signed-off-by: Damien Zammit <damien(a)zamaudio.com> --- src/mainboard/intel/d510mo/Kconfig | 2 ++ src/mainboard/intel/d510mo/devicetree.cb | 10 ++++++++-- src/mainboard/intel/d510mo/mainboard.c | 4 +++- 3 files changed, 13 insertions(+), 3 deletions(-) diff --git a/src/mainboard/intel/d510mo/Kconfig b/src/mainboard/intel/d510mo/Kconfig index 7981f92..7184665 100644 --- a/src/mainboard/intel/d510mo/Kconfig +++ b/src/mainboard/intel/d510mo/Kconfig @@ -23,6 +23,8 @@ config BOARD_SPECIFIC_OPTIONS select SUPERIO_WINBOND_W83627THG select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_1024 + select MAINBOARD_HAS_NATIVE_VGA_INIT + select INTEL_INT15 config MAX_CPUS int diff --git a/src/mainboard/intel/d510mo/devicetree.cb b/src/mainboard/intel/d510mo/devicetree.cb index c6f39a0..df5a0f9 100644 --- a/src/mainboard/intel/d510mo/devicetree.cb +++ b/src/mainboard/intel/d510mo/devicetree.cb @@ -15,14 +15,20 @@ # chip northbridge/intel/pineview # Northbridge + register "gfx.use_spread_spectrum_clock" = "0" + register "use_crt" = "1" + register "use_lvds" = "0" + device cpu_cluster 0 on # APIC cluster chip cpu/intel/socket_FCBGA559 # CPU device lapic 0 on end # APIC end end - device domain 0 on # PCI domain + device domain 0 on # PCI domain device pci 0.0 on end # Host Bridge - device pci 2.0 off end # Integrated graphics controller + device pci 1.0 off end # PEG + device pci 2.0 on end # Integrated graphics controller + device pci 2.1 on end # Integrated graphics controller 2 chip southbridge/intel/i82801gx # Southbridge register "pirqa_routing" = "0x0b" register "pirqb_routing" = "0x0b" diff --git a/src/mainboard/intel/d510mo/mainboard.c b/src/mainboard/intel/d510mo/mainboard.c index 94bee7e..4f0f32b 100644 --- a/src/mainboard/intel/d510mo/mainboard.c +++ b/src/mainboard/intel/d510mo/mainboard.c @@ -18,10 +18,12 @@ #include <device/pci_ops.h> #include <pc80/mc146818rtc.h> #include <device/pci.h> +#include <drivers/intel/gma/int15.h> static void mainboard_enable(device_t dev) { - dev->ops->init = NULL; + install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_NONE, + GMA_INT15_PANEL_FIT_DEFAULT, GMA_INT15_BOOT_DISPLAY_CRT, 0); } struct chip_operations mainboard_ops = {

1 0

Patch set updated for coreboot: nb/intel/x4x: Move to early cbmem
by Damien Zammit 28 Jan '16

28 Jan '16

Damien Zammit (damien(a)zamaudio.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13131 -gerrit commit ad098ad84165586c53858c8ebbdbc54f8eef3a7b Author: Damien Zammit <damien(a)zamaudio.com> Date: Fri Jan 22 22:12:30 2016 +1100 nb/intel/x4x: Move to early cbmem Previously with errors in the ram init, early cbmem was disabled. Now that the ram is working correctly, set as early cbmem platform and update all (1) boards to use it. Tested on GA-G41M-ES2L Change-Id: I5925c28821537f0e326b4f5a2ac39778e4724a3c Signed-off-by: Damien Zammit <damien(a)zamaudio.com> --- src/mainboard/gigabyte/ga-g41m-es2l/romstage.c | 1 + src/northbridge/intel/x4x/Kconfig | 2 +- src/northbridge/intel/x4x/northbridge.c | 3 --- src/northbridge/intel/x4x/ram_calc.c | 7 +++++++ 4 files changed, 9 insertions(+), 4 deletions(-) diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c b/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c index 6bae128..ca8ca5c 100644 --- a/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c +++ b/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c @@ -159,5 +159,6 @@ void main(unsigned long bist) printk(BIOS_DEBUG, "Initializing memory\n"); sdram_initialize(0, spd_addrmap); quick_ram_check(); + cbmem_initialize_empty(); printk(BIOS_DEBUG, "Memory initialized\n"); } diff --git a/src/northbridge/intel/x4x/Kconfig b/src/northbridge/intel/x4x/Kconfig index c330fd5..f643bb2 100644 --- a/src/northbridge/intel/x4x/Kconfig +++ b/src/northbridge/intel/x4x/Kconfig @@ -26,7 +26,7 @@ config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy select MMCONF_SUPPORT_DEFAULT select VGA select INTEL_GMA_ACPI - select LATE_CBMEM_INIT + select EARLY_CBMEM_INIT config BOOTBLOCK_NORTHBRIDGE_INIT string diff --git a/src/northbridge/intel/x4x/northbridge.c b/src/northbridge/intel/x4x/northbridge.c index 0fe8901..2d6c39f 100644 --- a/src/northbridge/intel/x4x/northbridge.c +++ b/src/northbridge/intel/x4x/northbridge.c @@ -29,7 +29,6 @@ #include <northbridge/intel/x4x/iomap.h> #include <northbridge/intel/x4x/chip.h> #include <northbridge/intel/x4x/x4x.h> -#include <cbmem.h> static void mch_domain_read_resources(device_t dev) { @@ -112,8 +111,6 @@ static void mch_domain_read_resources(device_t dev) fixed_mem_resource(dev, index++, pcie_config_base >> 10, pcie_config_size >> 10, IORESOURCE_RESERVE); } - - set_top_of_ram(usable_tomk * 1024); } static void mch_domain_set_resources(device_t dev) diff --git a/src/northbridge/intel/x4x/ram_calc.c b/src/northbridge/intel/x4x/ram_calc.c index f11b19a..27562ea 100644 --- a/src/northbridge/intel/x4x/ram_calc.c +++ b/src/northbridge/intel/x4x/ram_calc.c @@ -17,6 +17,7 @@ #define __SIMPLE_DEVICE__ +#include <cbmem.h> #include <commonlib/helpers.h> #include <stdint.h> #include <arch/io.h> @@ -86,3 +87,9 @@ u8 decode_pciebar(u32 *const base, u32 *const len) *len = max_buses << 20; return 1; } + +void *cbmem_top(void) +{ + u32 ramtop = pci_read_config32(PCI_DEV(0,0,0), D0F0_TSEG); + return (void*)(ramtop); +}

1 0

Patch set updated for coreboot: mb/gigabyte/ga-g41m-es2l: Remove copy-pasted cstates
by Damien Zammit 28 Jan '16

28 Jan '16

Damien Zammit (damien(a)zamaudio.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13465 -gerrit commit ed1665bdeb2e41b331d089bebad115aedc0c8405 Author: Damien Zammit <damien(a)zamaudio.com> Date: Tue Jan 26 17:17:27 2016 +1100 mb/gigabyte/ga-g41m-es2l: Remove copy-pasted cstates Change-Id: I5b6edbd97d4e6ed8b03f2f319a338022647e26ea Signed-off-by: Damien Zammit <damien(a)zamaudio.com> --- src/mainboard/gigabyte/ga-g41m-es2l/cstates.c | 13 +------------ src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb | 3 --- 2 files changed, 1 insertion(+), 15 deletions(-) diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/cstates.c b/src/mainboard/gigabyte/ga-g41m-es2l/cstates.c index dbac2ed..4d9f4ab 100644 --- a/src/mainboard/gigabyte/ga-g41m-es2l/cstates.c +++ b/src/mainboard/gigabyte/ga-g41m-es2l/cstates.c @@ -17,18 +17,7 @@ #include <device/device.h> #include <southbridge/intel/i82801gx/i82801gx.h> -static acpi_cstate_t cst_entries[] = { - { - /* acpi C1 / cpu C1 */ - 1, 0x01, 1000, - { ACPI_ADDRESS_SPACE_FIXED, 1, 2, { 1 }, 0, 0 } - }, - { - /* acpi C2 / cpu C2 */ - 2, 0x01, 500, - { ACPI_ADDRESS_SPACE_FIXED, 1, 2, { 1 }, 0x10, 0 } - }, -}; +static acpi_cstate_t cst_entries[] = {}; int get_cst_entries(acpi_cstate_t **entries) { diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb b/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb index e6b691c..3965538 100644 --- a/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb +++ b/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb @@ -21,9 +21,6 @@ chip northbridge/intel/x4x # Northbridge end chip cpu/intel/model_1067x # CPU device lapic 0xACAC off end - register "slfm" = "1" - register "c5" = "1" - register "c6" = "1" end end device domain 0 on # PCI domain

1 0

Patch set updated for coreboot: nb/intel/x4x: Cleanup gma.c
by Damien Zammit 28 Jan '16

28 Jan '16

Damien Zammit (damien(a)zamaudio.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13128 -gerrit commit 76785226569db05b9a6f7ad53de4202db6bc4283 Author: Damien Zammit <damien(a)zamaudio.com> Date: Fri Jan 22 19:13:18 2016 +1100 nb/intel/x4x: Cleanup gma.c Tidy up the code and move vga_textmode_init() later Change-Id: I49967e7197416c955ae6c8775eac7d1a60c92d1c Signed-off-by: Damien Zammit <damien(a)zamaudio.com> --- src/northbridge/intel/x4x/gma.c | 81 ++++++++++++----------------------------- 1 file changed, 24 insertions(+), 57 deletions(-) diff --git a/src/northbridge/intel/x4x/gma.c b/src/northbridge/intel/x4x/gma.c index 7891229..2679026 100644 --- a/src/northbridge/intel/x4x/gma.c +++ b/src/northbridge/intel/x4x/gma.c @@ -35,27 +35,14 @@ #include <pc80/vga.h> #include <pc80/vga_io.h> -static struct resource *gtt_res = NULL; - -void gtt_write(u32 reg, u32 data) -{ - write32(res2mmio(gtt_res, reg, 0), data); -} - static void intel_gma_init(const struct northbridge_intel_x4x_config *info, - u8 *mmio, u32 physbase, u16 piobase, u32 lfb) + u8 *mmio) { int i; u32 hactive, vactive; - vga_gr_write(0x18, 0); - /* Setup GTT. */ - for (i = 0; i < 0x2000; i++) - { - outl((i << 2) | 1, piobase); - outl(physbase + (i << 12) + 1, piobase + 4); - } + vga_gr_write(0x18, 0); write32(mmio + VGA0, 0x31108); write32(mmio + VGA1, 0x31406); @@ -92,8 +79,6 @@ static void intel_gma_init(const struct northbridge_intel_x4x_config *info, hactive = 640; vactive = 400; - vga_textmode_init(); - mdelay(1); write32(mmio + FP0(0), 0x31108); write32(mmio + DPLL(0), @@ -152,7 +137,8 @@ static void intel_gma_init(const struct northbridge_intel_x4x_config *info, write32(mmio + 0x000f000c, 0x00002050); write32(mmio + 0x00060100, 0x00044000); mdelay(1); - write32(mmio + PIPECONF(0), PIPECONF_ENABLE | PIPECONF_BPP_6 | PIPECONF_DITHER_EN); + write32(mmio + PIPECONF(0), PIPECONF_ENABLE + | PIPECONF_BPP_6 | PIPECONF_DITHER_EN); write32(mmio + VGACNTRL, 0x0); write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE | DISPPLANE_BGRX888); @@ -168,7 +154,7 @@ static void intel_gma_init(const struct northbridge_intel_x4x_config *info, | ADPA_DPMS_ON ); - write32(mmio + PP_CONTROL, PANEL_POWER_ON); + vga_textmode_init(); /* Enable screen memory. */ vga_sr_write(1, vga_sr_read(1) & ~0x20); @@ -178,6 +164,22 @@ static void intel_gma_init(const struct northbridge_intel_x4x_config *info, write32(mmio + SDEIIR, 0xffffffff); } +static void native_init(struct device *dev) +{ + struct resource *gtt_res = find_resource(dev, PCI_BASE_ADDRESS_0); + struct northbridge_intel_x4x_config *conf = dev->chip_info; + + if (gtt_res && gtt_res->base) { + printk(BIOS_SPEW, + "Initializing VGA without OPROM. MMIO 0x%llx\n", + gtt_res->base); + intel_gma_init(conf, res2mmio(gtt_res, 0, 0)); + } + + /* Linux relies on VBT for panel info. */ + generate_fake_intel_oprom(&conf->gfx, dev, "$VBT EAGLELAKE "); +} + static void gma_func0_init(struct device *dev) { u32 reg32; @@ -187,43 +189,10 @@ static void gma_func0_init(struct device *dev) reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO; pci_write_config32(dev, PCI_COMMAND, reg32); - /* Init graphics power management */ - gtt_res = find_resource(dev, PCI_BASE_ADDRESS_0); - - struct northbridge_intel_x4x_config *conf = dev->chip_info; - - if (!IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT)) { - /* PCI Init, will run VBIOS */ - pci_dev_init(dev); - } else { - u32 physbase; - struct resource *lfb_res; - struct resource *pio_res; - - lfb_res = find_resource(dev, PCI_BASE_ADDRESS_2); - pio_res = find_resource(dev, PCI_BASE_ADDRESS_4); - - physbase = pci_read_config32(dev, 0x5c) & ~0xf; - - if (gtt_res && gtt_res->base && physbase && pio_res && pio_res->base - && lfb_res && lfb_res->base) { - printk(BIOS_SPEW, "Initializing VGA without OPROM. MMIO 0x%llx\n", - gtt_res->base); - intel_gma_init(conf, res2mmio(gtt_res, 0, 0), physbase, - pio_res->base, lfb_res->base); - } - - /* Linux relies on VBT for panel info. */ - generate_fake_intel_oprom(&conf->gfx, dev, "$VBT EAGLELAKE "); - } - - /* Post VBIOS init */ - /* Enable Backlight */ - gtt_write(BLC_PWM_CTL2, (1 << 31)); - if (conf->gfx.backlight == 0) - gtt_write(BLC_PWM_CTL, 0x06100610); + if (IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT)) + native_init(dev); else - gtt_write(BLC_PWM_CTL, conf->gfx.backlight); + pci_dev_init(dev); } static void gma_set_subsystem(device_t dev, unsigned vendor, unsigned device) @@ -269,8 +238,6 @@ static struct device_operations gma_func0_ops = { .enable_resources = pci_dev_enable_resources, .acpi_fill_ssdt_generator = gma_ssdt, .init = gma_func0_init, - .scan_bus = 0, - .enable = 0, .ops_pci = &gma_pci_ops, };

1 0

Patch set updated for coreboot: mb/gigabyte/ga-g41m-es2l: Remove PMBASE settings and commented code.
by Damien Zammit 28 Jan '16

28 Jan '16

Damien Zammit (damien(a)zamaudio.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13466 -gerrit commit f53ffade4f9d14f7a041ee63191017f1041d96fc Author: Damien Zammit <damien(a)zamaudio.com> Date: Tue Jan 26 17:24:48 2016 +1100 mb/gigabyte/ga-g41m-es2l: Remove PMBASE settings and commented code. Fixed incorrect comment regarding port 80 LPC route. Change-Id: Ifbb73753d5a0737418b869085f2329a02504e5dc Signed-off-by: Damien Zammit <damien(a)zamaudio.com> --- src/mainboard/gigabyte/ga-g41m-es2l/romstage.c | 19 ++----------------- 1 file changed, 2 insertions(+), 17 deletions(-) diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c b/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c index ca8ca5c..bff481f 100644 --- a/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c +++ b/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c @@ -58,21 +58,6 @@ static void mb_gpio_init(void) outl(0x000000f0, DEFAULT_GPIOBASE + 0x34); outl(0x00000083, DEFAULT_GPIOBASE + 0x38); - /* Set default power management registers */ - pci_write_config32(dev, PMBASE, DEFAULT_PMBASE | 1); - outw(0x0011, DEFAULT_PMBASE + 0x00); - outw(0x0120, DEFAULT_PMBASE + 0x02); - outl(0x00001c01, DEFAULT_PMBASE + 0x04); - outl(0x00bb29d2, DEFAULT_PMBASE + 0x08); - outl(0x000000a0, DEFAULT_PMBASE + 0x10); - outl(0xc5000000, DEFAULT_PMBASE + 0x28); - outl(0x00000040, DEFAULT_PMBASE + 0x2c); - outw(0x13e0, DEFAULT_PMBASE + 0x44); - outw(0x003f, DEFAULT_PMBASE + 0x60); - outw(0x0800, DEFAULT_PMBASE + 0x68); - outw(0x0008, DEFAULT_PMBASE + 0x6a); - outw(0x003f, DEFAULT_PMBASE + 0x72); - /* Set default GPIOs on superio */ ite_reg_write(GPIO_DEV, 0x25, 0x00); ite_reg_write(GPIO_DEV, 0x26, 0xc7); @@ -137,8 +122,8 @@ void main(unsigned long bist) // ch0 ch1 const u8 spd_addrmap[4] = { 0x50, 0, 0x52, 0 }; - /* Disable watchdog timer and route port 80 to LPC */ - RCBA32(0x3410) = (RCBA32(0x3410) | 0x20);// & ~0x4; + /* Disable watchdog timer */ + RCBA32(0x3410) = RCBA32(0x3410) | 0x20; /* Set southbridge and Super I/O GPIOs. */ mb_gpio_init();

1 0

Patch set updated for coreboot: mb/gigabyte/ga-g41m-es2l: Move MMCONF base address to 0xe0000000
by Damien Zammit 28 Jan '16

28 Jan '16

Damien Zammit (damien(a)zamaudio.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13129 -gerrit commit 77c903ce50c7c538f971e9f168b11c6944b5de44 Author: Damien Zammit <damien(a)zamaudio.com> Date: Tue Jan 26 17:15:55 2016 +1100 mb/gigabyte/ga-g41m-es2l: Move MMCONF base address to 0xe0000000 Change-Id: I3873d92069cc1d113a8092d609d1768ff45cbd45 Signed-off-by: Damien Zammit <damien(a)zamaudio.com> --- src/mainboard/gigabyte/ga-g41m-es2l/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/Kconfig b/src/mainboard/gigabyte/ga-g41m-es2l/Kconfig index cf1077b..0a26f83 100644 --- a/src/mainboard/gigabyte/ga-g41m-es2l/Kconfig +++ b/src/mainboard/gigabyte/ga-g41m-es2l/Kconfig @@ -29,7 +29,7 @@ config BOARD_SPECIFIC_OPTIONS config MMCONF_BASE_ADDRESS hex - default 0xc0000000 + default 0xe0000000 config MAINBOARD_DIR string

1 0

Patch set updated for coreboot: nb/intel/x4x: Tidy up northbridge
by Damien Zammit 28 Jan '16

28 Jan '16

Damien Zammit (damien(a)zamaudio.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13126 -gerrit commit eebc79a9ecd9efa6d69746483be9dbce346d0e56 Author: Damien Zammit <damien(a)zamaudio.com> Date: Fri Jan 22 19:11:05 2016 +1100 nb/intel/x4x: Tidy up northbridge - Add device enable macros - Set the PMBASE correctly through southbridge device Change-Id: I1b8cc3de96b1ecaf01e31bad8fba1fada8671c2d Signed-off-by: Damien Zammit <damien(a)zamaudio.com> --- src/northbridge/intel/x4x/early_init.c | 11 +++-------- src/northbridge/intel/x4x/x4x.h | 11 ++++++++++- 2 files changed, 13 insertions(+), 9 deletions(-) diff --git a/src/northbridge/intel/x4x/early_init.c b/src/northbridge/intel/x4x/early_init.c index b98c42e..b522293 100644 --- a/src/northbridge/intel/x4x/early_init.c +++ b/src/northbridge/intel/x4x/early_init.c @@ -22,8 +22,6 @@ void x4x_early_init(void) { - u16 reg16; - const device_t d0f0 = PCI_DEV(0, 0, 0); /* Setup MCHBAR. */ @@ -36,12 +34,11 @@ void x4x_early_init(void) pci_write_config32(d0f0, D0F0_EPBAR_LO, DEFAULT_EPBAR | 1); /* Setup PMBASE */ - pci_write_config32(d0f0, D0F0_PMBASE, DEFAULT_PMBASE | 1); + pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE, DEFAULT_PMBASE | 1); + pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x44 /* ACPI_CNTL */ , 0x80); /* Setup HECIBAR */ pci_write_config32(PCI_DEV(0,3,0), 0x10, DEFAULT_HECIBAR); - reg16 = pci_read_config16(PCI_DEV(0,3,0), 0x4); - pci_write_config16(PCI_DEV(0,3,0), 0x4, reg16 | 0x6); /* Set C0000-FFFFF to access RAM on both reads and writes */ pci_write_config8(d0f0, D0F0_PAM(0), 0x30); @@ -53,8 +50,6 @@ void x4x_early_init(void) pci_write_config8(d0f0, D0F0_PAM(6), 0x33); /* Enable internal GFX */ + pci_write_config32(d0f0, D0F0_DEVEN, BOARD_DEVEN); pci_write_config16(d0f0, D0F0_GGC, 0x0170); - - reg16 = pci_read_config16(d0f0, D0F0_DEVEN); - pci_write_config16(d0f0, D0F0_DEVEN, reg16 | 0x8); } diff --git a/src/northbridge/intel/x4x/x4x.h b/src/northbridge/intel/x4x/x4x.h index c226950..e1ef745 100644 --- a/src/northbridge/intel/x4x/x4x.h +++ b/src/northbridge/intel/x4x/x4x.h @@ -27,11 +27,20 @@ #define D0F0_MCHBAR_HI 0x4c #define D0F0_GGC 0x52 #define D0F0_DEVEN 0x54 +#define D0EN (1 << 0) +#define D1EN (1 << 1) +#define IGD0EN (1 << 3) +#define IGD1EN (1 << 4) +#define D3F0EN (1 << 6) +#define D3F1EN (1 << 7) +#define D3F2EN (1 << 8) +#define D3F3EN (1 << 9) +#define PEG1EN (1 << 13) +#define BOARD_DEVEN (D0EN | D1EN | IGD0EN | IGD1EN) #define D0F0_PCIEXBAR_LO 0x60 #define D0F0_PCIEXBAR_HI 0x64 #define D0F0_DMIBAR_LO 0x68 #define D0F0_DMIBAR_HI 0x6c -#define D0F0_PMBASE 0x78 #define D0F0_PAM(x) (0x90+(x)) /* 0-6*/ #define D0F0_REMAPBASE 0x98 #define D0F0_REMAPLIMIT 0x9a

1 0

Patch set updated for coreboot: nb/intel/x4x: Tidy up raminit and fix msbpos() function
by Damien Zammit 28 Jan '16

28 Jan '16

Damien Zammit (damien(a)zamaudio.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13127 -gerrit commit e0f830f5efed9b122ef6eb549cf48fdc6db0e6b9 Author: Damien Zammit <damien(a)zamaudio.com> Date: Fri Jan 22 19:11:44 2016 +1100 nb/intel/x4x: Tidy up raminit and fix msbpos() function - Fix bug with msbpos, it was not returning the correct result due to typo in logic, and unsigned value needed to be negative. - Add reclaim above 4GiB - Fix to ME related registers near the end of raminit Change-Id: I04acd0593a457437ee4a42e14b287b2b17a160af Signed-off-by: Damien Zammit <damien(a)zamaudio.com> --- src/northbridge/intel/x4x/raminit_ddr2.c | 55 +++++++++++++++++++++++++++----- 1 file changed, 47 insertions(+), 8 deletions(-) diff --git a/src/northbridge/intel/x4x/raminit_ddr2.c b/src/northbridge/intel/x4x/raminit_ddr2.c index d21924b..3dd00fb 100644 --- a/src/northbridge/intel/x4x/raminit_ddr2.c +++ b/src/northbridge/intel/x4x/raminit_ddr2.c @@ -45,14 +45,22 @@ static u32 ddr2mhz(u32 speed) return mhz[speed]; } -static u8 msbpos(u8 val) //Reverse +/* Find MSB bitfield location using bit scan reverse instruction */ +static u8 msbpos(u32 val) { - u8 i; - for (i = 7; i >= 0; i--) { - if ((val & (1 << i)) == 0) - break; + u32 pos; + + if (val == 0) { + printk(BIOS_WARNING, "WARNING: Input to BSR is zero\n"); + return 0; } - return i; + + asm ("bsrl %1, %0" + :"=r"(pos) + :"r"(val) + ); + + return (u8)(pos & 0xff); } static void sdram_detect_smallest_params2(struct sysinfo *s) @@ -1614,7 +1622,9 @@ static void dradrb_ddr2(struct sysinfo *s) static void mmap_ddr2(struct sysinfo *s) { - u32 gfxsize, gttsize, tsegsize, mmiosize, tom, tolud, touud, gfxbase, gttbase, tsegbase; + bool reclaim; + u32 gfxsize, gttsize, tsegsize, mmiosize, tom, tolud, touud; + u32 gfxbase, gttbase, tsegbase, reclaimbase, reclaimlimit; u16 ggc; u16 ggc2uma[] = { 0, 0, 0, 0, 0, 32, 48, 64, 128, 256, 96, 160, 224, 352 }; u8 ggc2gtt[] = { 0, 1, 0, 2, 0, 0, 0, 0, 0, 2, 3, 4}; @@ -1626,13 +1636,34 @@ static void mmap_ddr2(struct sysinfo *s) mmiosize = 0x400; // 1GB MMIO tom = s->channel_capacity[0] + s->channel_capacity[1] - ME_UMA_SIZEMB; tolud = MIN(0x1000 - mmiosize, tom); + + reclaim = false; + if ((tom - tolud) > 0x40) + reclaim = true; + + if (reclaim) { + tolud = tolud & ~0x3f; + tom = tom & ~0x3f; + reclaimbase = MAX(0x1000, tom); + reclaimlimit = reclaimbase + (MIN(0x1000, tom) - tolud) - 0x40; + } + touud = tom; + if (reclaim) + touud = reclaimlimit + 0x40; + gfxbase = tolud - gfxsize; gttbase = gfxbase - gttsize; tsegbase = gttbase - tsegsize; pci_write_config16(PCI_DEV(0,0,0), 0xb0, tolud << 4); pci_write_config16(PCI_DEV(0,0,0), 0xa0, tom >> 6); + if (reclaim) { + pci_write_config16(PCI_DEV(0,0,0), 0x98, + (u16)(reclaimbase >> 6)); + pci_write_config16(PCI_DEV(0,0,0), 0x9a, + (u16)(reclaimlimit >> 6)); + } pci_write_config16(PCI_DEV(0,0,0), 0xa2, touud); pci_write_config32(PCI_DEV(0,0,0), 0xa4, gfxbase << 20); pci_write_config32(PCI_DEV(0,0,0), 0xa8, gttbase << 20); @@ -1993,7 +2024,15 @@ void raminit_ddr2(struct sysinfo *s) printk(BIOS_DEBUG, "Done power settings\n"); // ME related - //MCHBAR32(0xa30) = MCHBAR32(0xa30) | (1 << 26); + if (RANK_IS_POPULATED(s->dimms, 0, 0) + || RANK_IS_POPULATED(s->dimms, 1, 0)) { + MCHBAR8(0xa2f) = MCHBAR8(0xa2f) | (1 << 0); + } + if (RANK_IS_POPULATED(s->dimms, 0, 1) + || RANK_IS_POPULATED(s->dimms, 1, 1)) { + MCHBAR8(0xa2f) = MCHBAR8(0xa2f) | (1 << 1); + } + MCHBAR32(0xa30) = MCHBAR32(0xa30) | (1 << 26); printk(BIOS_DEBUG, "Done ddr2\n"); }

1 0

Patch set updated for coreboot: nb/intel/x4x: Fix memory hole with both channels populated
by Damien Zammit 28 Jan '16

28 Jan '16

Damien Zammit (damien(a)zamaudio.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13125 -gerrit commit 0aad2efd834214a036412607f48169c1a529867a Author: Damien Zammit <damien(a)zamaudio.com> Date: Fri Jan 22 18:56:23 2016 +1100 nb/intel/x4x: Fix memory hole with both channels populated Previously, 0xa0000000 to 0xc0000000 needed to be reserved as a non-usable memory hole because it would hang on memory i/o. Memtest86+ now passes with no errors on both channels populated. Tested on GA-G41M-ES2L with 2x2GiB sticks of ram. Change-Id: Ib52a63a80f5f69c16841f10ddb896ab3c7d30462 Signed-off-by: Damien Zammit <damien(a)zamaudio.com> --- src/northbridge/intel/x4x/northbridge.c | 62 +++++++++++++++----------------- src/northbridge/intel/x4x/raminit_ddr2.c | 53 ++++++++++++++++++--------- 2 files changed, 65 insertions(+), 50 deletions(-) diff --git a/src/northbridge/intel/x4x/northbridge.c b/src/northbridge/intel/x4x/northbridge.c index c5a8968..0fe8901 100644 --- a/src/northbridge/intel/x4x/northbridge.c +++ b/src/northbridge/intel/x4x/northbridge.c @@ -26,25 +26,24 @@ #include <cpu/cpu.h> #include <boot/tables.h> #include <arch/acpi.h> +#include <northbridge/intel/x4x/iomap.h> #include <northbridge/intel/x4x/chip.h> #include <northbridge/intel/x4x/x4x.h> - -/* Reserve segments A and B: - * - * 0xa0000 - 0xbffff: legacy VGA - */ -static const int legacy_hole_base_k = 0xa0000 / 1024; -static const int legacy_hole_size_k = 128; +#include <cbmem.h> static void mch_domain_read_resources(device_t dev) { + u8 index; u64 tom, touud; - u32 tomk, tsegk, tolud, usable_tomk; + u32 tomk, tseg_sizek, tolud, usable_tomk; u32 pcie_config_base, pcie_config_size; u32 uma_sizek = 0; + const u32 top32memk = 4 * (GiB / KiB); + index = 3; + /* 1024KiB TSEG */ - tsegk = 1 << 10; + tseg_sizek = 1024; pci_domain_read_resources(dev); @@ -77,53 +76,52 @@ static void mch_domain_read_resources(device_t dev) const u32 gsm_sizek = decode_igd_gtt_size((ggc >> 8) & 0xf); printk(BIOS_DEBUG, " and %uM GTT\n", gsm_sizek >> 10); - uma_sizek = gms_sizek + gsm_sizek + tsegk; + uma_sizek = gms_sizek + gsm_sizek + tseg_sizek; usable_tomk = tomk - uma_sizek; printk(BIOS_INFO, "Available memory below 4GB: %uM\n", usable_tomk >> 10); /* Report the memory regions */ - ram_resource(dev, 3, 0, legacy_hole_base_k); - ram_resource(dev, 4, legacy_hole_base_k + legacy_hole_size_k, - (usable_tomk - (legacy_hole_base_k + legacy_hole_size_k))); + ram_resource(dev, index++, 0, 0xa0000 >> 10); + ram_resource(dev, index++, 1*MiB >> 10, (usable_tomk - (1*MiB >> 10))); /* * If >= 4GB installed then memory from TOLUD to 4GB * is remapped above TOM, TOUUD will account for both */ touud >>= 10; /* Convert to KB */ - if (touud > 4096 * 1024) { - ram_resource(dev, 5, 4096 * 1024, touud - (4096 * 1024)); + if (touud > top32memk) { + ram_resource(dev, index++, top32memk, touud - top32memk); printk(BIOS_INFO, "Available memory above 4GB: %lluM\n", - (touud >> 10) - 4096); + (touud - top32memk) >> 10); } printk(BIOS_DEBUG, "Adding UMA memory area base=0x%08x " - "size=0x%08x\n", usable_tomk << 10, uma_sizek << 10); - fixed_mem_resource(dev, 6, usable_tomk, uma_sizek, IORESOURCE_RESERVE); + "size=0x%08x\n", usable_tomk << 10, uma_sizek << 10); + fixed_mem_resource(dev, index++, usable_tomk, uma_sizek, + IORESOURCE_RESERVE); - /* Some strange hole, reserve it */ - //fixed_mem_resource(dev, 7, usable_tomk - (0x02000000 >> 10), 0x02000000 >> 10, IORESOURCE_RESERVE); + /* Reserve high memory where the NB BARs are up to 4GiB */ + fixed_mem_resource(dev, index++, DEFAULT_HECIBAR >> 10, + top32memk - (DEFAULT_HECIBAR >> 10), + IORESOURCE_RESERVE); if (decode_pciebar(&pcie_config_base, &pcie_config_size)) { printk(BIOS_DEBUG, "Adding PCIe config bar base=0x%08x " "size=0x%x\n", pcie_config_base, pcie_config_size); - fixed_mem_resource(dev, 7, pcie_config_base >> 10, + fixed_mem_resource(dev, index++, pcie_config_base >> 10, pcie_config_size >> 10, IORESOURCE_RESERVE); } + + set_top_of_ram(usable_tomk * 1024); } static void mch_domain_set_resources(device_t dev) { - struct resource *resource; - int i; - - for (i = 3; i < 8; ++i) { - /* Report read resources. */ - resource = probe_resource(dev, i); - if (resource) - report_resource_stored(dev, resource, ""); - } + struct resource *res; + + for (res = dev->resource_list; res; res = res->next) + report_resource_stored(dev, res, ""); assign_resources(dev->link_list); } @@ -141,10 +139,9 @@ static void mch_domain_init(device_t dev) static struct device_operations pci_domain_ops = { .read_resources = mch_domain_read_resources, .set_resources = mch_domain_set_resources, - .enable_resources = NULL, .init = mch_domain_init, .scan_bus = pci_domain_scan_bus, - .ops_pci_bus = pci_bus_default_ops, + .ops_pci_bus = pci_bus_default_ops, .write_acpi_tables = northbridge_write_acpi_tables, .acpi_fill_ssdt_generator = generate_cpu_entries, }; @@ -160,7 +157,6 @@ static struct device_operations cpu_bus_ops = { .set_resources = DEVICE_NOOP, .enable_resources = DEVICE_NOOP, .init = cpu_bus_init, - .scan_bus = 0, }; diff --git a/src/northbridge/intel/x4x/raminit_ddr2.c b/src/northbridge/intel/x4x/raminit_ddr2.c index d77c2c4..d21924b 100644 --- a/src/northbridge/intel/x4x/raminit_ddr2.c +++ b/src/northbridge/intel/x4x/raminit_ddr2.c @@ -23,6 +23,8 @@ #include "iomap.h" #include "x4x.h" +#define ME_UMA_SIZEMB 0 + static inline void barrier(void) { asm volatile("mfence":::); @@ -1465,7 +1467,8 @@ static void dradrb_ddr2(struct sysinfo *s) u32 dra0; u32 dra1; u16 totalmemorymb; - u16 size, offset; + u32 size, offset; + u32 size0, size1; u8 dratab[2][2][2][4] = { { { @@ -1562,35 +1565,51 @@ static void dradrb_ddr2(struct sysinfo *s) MCHBAR16(0x606 + 2*msbpos(rankpop1)) = c0drb + c1drb; } - MCHBAR8(0x111) = MCHBAR8(0x111) | 0x2; - MCHBAR16(0x104) = 0; - size = s->channel_capacity[0] + s->channel_capacity[1]; - MCHBAR16(0x102) = size; + /* Populated channel sizes in MiB */ + size0 = s->channel_capacity[0]; + size1 = s->channel_capacity[1]; + + MCHBAR8(0x111) = MCHBAR8(0x111) & ~0x2; + MCHBAR8(0x111) = MCHBAR8(0x111) | (1 << 4); + + /* Set ME UMA size in MiB */ + MCHBAR16(0x100) = ME_UMA_SIZEMB; + + /* Set ME UMA Present bit */ + MCHBAR32(0x111) = MCHBAR32(0x111) | 1; + + size = MIN(size0 - ME_UMA_SIZEMB, size1) * 2; + + MCHBAR16(0x104) = size; + MCHBAR16(0x102) = size0 + size1 - size; + map = 0; - if (s->channel_capacity[0] == 0) { + if (size0 == 0) { map = 0; - } else if (s->channel_capacity[1] == 0) { + } else if (size1 == 0) { map |= 0x20; } else { map |= 0x40; } - map |= 0x18; - if (s->channel_capacity[0] <= s->channel_capacity[1]) { - map |= 0x5; - } else if (s->channel_capacity[0] > s->channel_capacity[1]) { + if (size == 0) { + map |= 0x18; + } + + if (size0 - ME_UMA_SIZEMB >= size1) { map |= 0x4; } MCHBAR8(0x110) = map; MCHBAR16(0x10e) = 0; - if (s->channel_capacity[1] != 0) { + + if (size1 != 0) { offset = 0; - } else if (s->channel_capacity[0] > s->channel_capacity[1]) { - offset = size; + } else if ((size0 > size1) && ((map & 0x7) == 0x4)) { + offset = size/2 + (size0 + size1 - size); } else { - offset = 0; + offset = size/2 + ME_UMA_SIZEMB; } MCHBAR16(0x108) = offset; - MCHBAR16(0x10a) = 0; + MCHBAR16(0x10a) = size/2; } static void mmap_ddr2(struct sysinfo *s) @@ -1605,7 +1624,7 @@ static void mmap_ddr2(struct sysinfo *s) gttsize = ggc2gtt[(ggc & 0xf00) >> 8]; tsegsize = 1; // 1MB TSEG mmiosize = 0x400; // 1GB MMIO - tom = s->channel_capacity[0] + s->channel_capacity[1]; + tom = s->channel_capacity[0] + s->channel_capacity[1] - ME_UMA_SIZEMB; tolud = MIN(0x1000 - mmiosize, tom); touud = tom; gfxbase = tolud - gfxsize;

1 0

Patch set updated for coreboot: ec/google/chromeec/acpi :Enable DPTF charger/TSR1/TSR2 participant.
by Hannah Williams 28 Jan '16

28 Jan '16

Hannah Williams (hannah.williams(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12748 -gerrit commit 9c7f4680fd4cad36a10e272c50d00b1cc45c066d Author: Freddy Paul <freddy.paul(a)intel.com> Date: Fri Oct 2 19:06:57 2015 -0700 ec/google/chromeec/acpi :Enable DPTF charger/TSR1/TSR2 participant. TEST=Plug/Unplug AC Adapter multiple times and make sure device is charging properly. Original-Reviewed-on: https://chromium-review.googlesource.com/303990 Original-Reviewed-by: Jenny Tc <jenny.tc(a)intel.com> Original-Reviewed-by: T.H. Lin <T.H_Lin(a)quantatw.com> Original-Tested-by: T.H. Lin <T.H_Lin(a)quantatw.com> Original-Tested-by: Jagadish Krishnamoorthy <jagadish.krishnamoorthy(a)intel.com> Original-Reviewed-by: Divya Jyothi <divya.jyothi(a)intel.com> Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Signed-off-by: Freddy Paul <freddy.paul(a)intel.com> Change-Id: I188e80e6688d0bac5bed6dd64cd2d0feefa30d3f Signed-off-by: Hannah Williams <hannah.williams(a)intel.com> Signed-off-by: Freddy Paul <freddy.paul(a)intel.com> Signed-off-by: Hannah Williams <hannah.williams(a)intel.com> --- src/ec/google/chromeec/acpi/ec.asl | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/src/ec/google/chromeec/acpi/ec.asl b/src/ec/google/chromeec/acpi/ec.asl index 68d5106..4eb4e17 100644 --- a/src/ec/google/chromeec/acpi/ec.asl +++ b/src/ec/google/chromeec/acpi/ec.asl @@ -22,7 +22,9 @@ // Mainboard specific throttle handler External (\_TZ.THRT, MethodObj) External (\_SB.DPTF.TEVT, MethodObj) +#ifdef DPTF_ENABLE_CHARGER External (\_SB.DPTF.TCHG, DeviceObj) +#endif Device (EC0) { @@ -170,10 +172,12 @@ Device (EC0) Store ("EC: AC CONNECTED", Debug) Store (ACEX, \PWRS) Notify (AC, 0x80) +#ifdef DPTF_ENABLE_CHARGER If (CondRefOf (\_SB.DPTF.TCHG)) { \_SB.DPTF.TCHG.SPPC (\_SB.DPTF.TCHG.PPPC ()) Notify (\_SB.DPTF.TCHG, 0x80) } +#endif \PNOT () } @@ -183,9 +187,11 @@ Device (EC0) Store ("EC: AC DISCONNECTED", Debug) Store (ACEX, \PWRS) Notify (AC, 0x80) +#ifdef DPTF_ENABLE_CHARGER If (CondRefOf (\_SB.DPTF.TCHG)) { Notify (\_SB.DPTF.TCHG, 0x80) } +#endif \PNOT () }

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit January 2016