coreboot-gerrit January 2016

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Patch set updated for coreboot: intel/strago: Disable unused lines on Gpio North Bank
by Hannah Williams 28 Jan '16

28 Jan '16

Hannah Williams (hannah.williams(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13176 -gerrit commit dec04b23ce588917b1d0e4601a3fe321c38ddfe8 Author: Jagadish Krishnamoorthy <jagadish.krishnamoorthy(a)intel.com> Date: Thu Nov 19 11:10:34 2015 -0800 intel/strago: Disable unused lines on Gpio North Bank The unused lines leads to spurious interrupts on few of the systems. TEST=run suspend_stress test and make sure that kbd is working. Change-Id: Ie539e1debc15dd1fd8707f8866c65714fc43e44b Signed-off-by: Jagadish Krishnamoorthy <jagadish.krishnamoorthy(a)intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/313417 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Signed-off-by: Hannah Williams <hannah.williams(a)intel.com> --- src/mainboard/intel/strago/gpio.c | 23 ++++++++++------------- 1 file changed, 10 insertions(+), 13 deletions(-) diff --git a/src/mainboard/intel/strago/gpio.c b/src/mainboard/intel/strago/gpio.c index 4b58eac..b18ad97 100755 --- a/src/mainboard/intel/strago/gpio.c +++ b/src/mainboard/intel/strago/gpio.c @@ -154,16 +154,15 @@ static const struct soc_gpio_map gpsw_gpio_map[] = { /* North Community */ static const struct soc_gpio_map gpn_gpio_map[] = { - Native_M5, /* 00 GPIO_DFX0 */ - Native_M5, /* 01 GPIO_DFX3 */ - Native_M1, /* 02 GPIO_DFX7 */ - Native_M5, /* 03 GPIO_DFX1 */ - Native_M1, /* 04 GPIO_DFX5 */ - Native_M1, /* 05 GPIO_DFX4 */ - GPI(trig_edge_low, L5, NA, non_maskable, en_rx_data, NA, NA), - /* 06 GPIO_DFX8 */ - Native_M5, /* 07 GPIO_DFX2 */ - Native_M8, /* 08 GPIO_DFX6 */ + GPIO_NC, /* 00 GPIO_DFX0 */ + GPIO_NC, /* 01 GPIO_DFX3 */ + GPIO_NC, /* 02 GPIO_DFX7 */ + GPIO_NC, /* 03 GPIO_DFX1 */ + GPIO_NC, /* 04 GPIO_DFX5 */ + GPIO_NC, /* 05 GPIO_DFX4 */ + GPIO_NC, /* 06 GPIO_DFX8 */ + GPIO_NC, /* 07 GPIO_DFX2 */ + GPIO_NC, /* 08 GPIO_DFX6 */ GPI(trig_edge_low, L8, NA, non_maskable, en_edge_rx_data , UNMASK_WAKE, SCI), /* 15 GPIO_SUS0 */ GPO_FUNC(NA, NA), /* 16 SEC_GPIO_SUS10 */ @@ -174,9 +173,7 @@ static const struct soc_gpio_map gpn_gpio_map[] = { GPI(trig_edge_low, L3, P_1K_H, non_maskable, NA, UNMASK_WAKE, NA), /* 19 GPIO_SUS1 */ GPIO_NC, /* 20 GPIO_SUS5 */ - GPI(trig_edge_high, L2, P_20K_H, non_maskable, - en_edge_rx_data, NA , NA), - /* 21 SEC_GPIO_SUS11 */ + GPIO_NC, /* 21 SEC_GPIO_SUS11 */ GPIO_NC, /* 22 GPIO_SUS4 */ GPIO_NC, /* 23 SEC_GPIO_SUS8 */

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Patch set updated for coreboot: google/peppy/Kconfig: Move select MAINBOARD_DO_NATIVE_VGA_INIT
by Jean Lucas 28 Jan '16

28 Jan '16

Jean Lucas (jean(a)4ray.co) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13493 -gerrit commit c440ce590d5264ed52fce2d45995ac1b3281b846 Author: Jean Lucas <jean(a)4ray.co> Date: Wed Jan 27 16:04:43 2016 -0500 google/peppy/Kconfig: Move select MAINBOARD_DO_NATIVE_VGA_INIT Move the default select of "Use native graphics initialization" for Peppy to the ChromeOS section as SeaBIOS (default payload) requires a vBIOS and takes twice as long to load with this option enabled. For the same reasons, this option shouldn't be enabled by default (def_bool y). Change-Id: I1f2163e0a1e4bf8e5041dad150bdf7de804fb4db --- src/mainboard/google/peppy/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/google/peppy/Kconfig b/src/mainboard/google/peppy/Kconfig index 428d293..3e12a00 100644 --- a/src/mainboard/google/peppy/Kconfig +++ b/src/mainboard/google/peppy/Kconfig @@ -17,12 +17,12 @@ config BOARD_SPECIFIC_OPTIONS # dummy select MAINBOARD_HAS_CHROMEOS select MAINBOARD_HAS_LPC_TPM select MAINBOARD_HAS_NATIVE_VGA_INIT - select MAINBOARD_DO_NATIVE_VGA_INIT select INTEL_DP select INTEL_DDI select INTEL_INT15 config CHROMEOS + select MAINBOARD_DO_NATIVE_VGA_INIT select CHROMEOS_VBNV_CMOS select LID_SWITCH select EC_SOFTWARE_SYNC

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Patch merged into coreboot/master: Move object files to $(obj)/<class>/
by gerrit＠coreboot.org 28 Jan '16

28 Jan '16

the following patch was just integrated into master: commit 98fc426a98db7e4dd5fea334edec720721d2a89c Author: Nico Huber <nico.h(a)gmx.de> Date: Sat Jan 23 01:24:33 2016 +0100 Move object files to $(obj)/<class>/ Instead of tagging object files with .<class>, move them to a <class> directory below $(obj)/. This way we can keep a 1:1 mapping between source- and object-file names. The 1:1 mapping is a prerequisite for Ada, where the compiler refuses any other object-file name. Tested by verifying that the resulting coreboot.rom files didn't change for all of Jenkins' abuild configurations. Change-Id: Idb7a8abec4ea0a37021d9fc24cc8583c4d3bf67c Signed-off-by: Nico Huber <nico.h(a)gmx.de> Reviewed-on: https://review.coreboot.org/13181 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Tested-by: build bot (Jenkins) See https://review.coreboot.org/13181 for details. -gerrit

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Patch merged into coreboot/master: Makefile: Make full use of src-to-obj macro
by gerrit＠coreboot.org 28 Jan '16

28 Jan '16

the following patch was just integrated into master: commit 81b09f40087d1a00afe30e379d2e8460203b1c5c Author: Nico Huber <nico.h(a)gmx.de> Date: Sat Jan 23 00:50:00 2016 +0100 Makefile: Make full use of src-to-obj macro There were several spots in the tree where the path to a per class object file was hardcoded. To make use of the src-to-obj macro for this, it had to be moved before the inclusion of subdirs. Which is fine, as it doesn't have dependencies beside $(obj). Tested by verifying that the resulting coreboot.rom files didn't change for all of Jenkins' abuild configurations. Change-Id: I2eb1beeb8ae55872edfd95f750d7d5a1cee474c4 Signed-off-by: Nico Huber <nico.h(a)gmx.de> Reviewed-on: https://review.coreboot.org/13180 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See https://review.coreboot.org/13180 for details. -gerrit

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Patch merged into coreboot/master: intel/strago: Set LPC_CLKRUNB to PU_20K to solve leakage issue.
by gerrit＠coreboot.org 28 Jan '16

28 Jan '16

the following patch was just integrated into master: commit 116d67323b78cad4b0ddd354fc154c4e4ac60225 Author: Kane Chen <kane.chen(a)intel.com> Date: Wed Dec 9 10:06:14 2015 +0800 intel/strago: Set LPC_CLKRUNB to PU_20K to solve leakage issue. LPC_CLKRUNB pin needs to be set to PU_20K to prevent leakage TEST=Test on Strago and make sure the leakage is gone Signed-off-by: Kane Chen <kane.chen(a)intel.com> Change-Id: Id2bf7511806cdc52b505bb469238a9465b356352 Original-Reviewed-on: https://chromium-review.googlesource.com/317020 Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Tested-by: Kane Chen <kane.chen(a)intel.com> Original-Commit-Queue: Kane Chen <kane.chen(a)intel.com> Signed-off-by: Hannah Williams <hannah.williams(a)intel.com> Reviewed-on: https://review.coreboot.org/13175 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/13175 for details. -gerrit

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Patch merged into coreboot/master: intel/strago: EC_IN_RW gpio input configuration.
by gerrit＠coreboot.org 28 Jan '16

28 Jan '16

the following patch was just integrated into master: commit 2abcffcc4014a3a5344d01d76c50d707eae62d17 Author: Divagar Mohandass <divagar.mohandass(a)intel.com> Date: Mon Oct 5 16:21:14 2015 +0530 intel/strago: EC_IN_RW gpio input configuration. Configure EC_IN_RW signal as gpio input. TEST=Boot to Chrome OS in normal mode and enter recovery mode use ctrl-d to switch to Dev mode. Change-Id: I835a1c70d89ef2ab75c35233f889124b60bb64a3 Signed-off-by: Hannah Williams <hannah.williams(a)intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/304040 Original-Tested-by: Divagar Mohandass <divagar.mohandass(a)intel.com> Original-Reviewed-by: Gomathi Kumar <gomathi.kumar(a)intel.com> Original-Reviewed-by: Shobhit Srivastava <shobhit.srivastava(a)intel.com> Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Commit-Queue: Shobhit Srivastava <shobhit.srivastava(a)intel.com> Reviewed-on: https://review.coreboot.org/13124 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/13124 for details. -gerrit

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Patch merged into coreboot/master: intel/strago: Clean up DDR configuration.
by gerrit＠coreboot.org 28 Jan '16

28 Jan '16

the following patch was just integrated into master: commit 39f84fa6623f8981816682138d02acf3c31f3672 Author: Divagar Mohandass <divagar.mohandass(a)intel.com> Date: Tue Sep 8 15:03:45 2015 +0530 intel/strago: Clean up DDR configuration. This change includes following changes: - Clean up the DDR configuration and flow. - Removing support for non LPDDR3 boards. - Supporting only LPDDR3 and PMIC config. TEST=Build/flash CB and boot the platform to OS. Change-Id: I8369443da728a4c07e0c1a82040d94034c3542da Signed-off-by: Divagar Mohandass <divagar.mohandass(a)intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/297941 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-by: Jenny Tc <jenny.tc(a)intel.com> Signed-off-by: Hannah Williams <hannah.williams(a)intel.com> Reviewed-on: https://review.coreboot.org/13122 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/13122 for details. -gerrit

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Patch merged into coreboot/master: intel/strago: Disable unused devices.
by gerrit＠coreboot.org 28 Jan '16

28 Jan '16

the following patch was just integrated into master: commit 4f4c6e88be48d62c41c88bc5b36828c967e0d6e4 Author: Divagar Mohandass <divagar.mohandass(a)intel.com> Date: Mon Sep 21 11:51:07 2015 +0530 intel/strago: Disable unused devices. This change will disable unused devices in device tree to improve boot performance. TEST=Build/Flash CB and boot to OS. verify Touch screen, Audio, WIFI and Track pad functionality. Change-Id: Ib5ae31c96d75f9a5b0f8d8b72d058e18fe7d7e67 Signed-off-by: Divagar Mohandass <divagar.mohandass(a)intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/300943 Original-Reviewed-by: Hannah Williams <hannah.williams(a)intel.com> Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Tested-by: Gomathi Kumar <gomathi.kumar(a)intel.com> Reviewed-on: https://review.coreboot.org/13423 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/13423 for details. -gerrit

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Patch merged into coreboot/master: soc/braswell: Fix leakage on V1P8S rail
by gerrit＠coreboot.org 27 Jan '16

27 Jan '16

the following patch was just integrated into master: commit 97f09c3f191f3dad474d5c1fd56682001095703e Author: Shobhit Srivastava <shobhit.srivastava(a)intel.com> Date: Mon Aug 10 11:48:23 2015 +0530 soc/braswell: Fix leakage on V1P8S rail Tristate MMC1_RCLK pin to fix leakage on V1P8S rail. Original-Reviewed-on: https://chromium-review.googlesource.com/292043 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Tested-by: Divagar Mohandass <divagar.mohandass(a)intel.com> Change-Id: I76cc9211ba93b2596d3c0d772d99f8934656e01c Signed-off-by: Shobhit Srivastava <shobhit.srivastava(a)intel.com> Reviewed-on: https://review.coreboot.org/12730 Reviewed-by: Martin Roth <martinroth(a)google.com> Tested-by: build bot (Jenkins) See https://review.coreboot.org/12730 for details. -gerrit

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Patch merged into coreboot/master: soc/braswell: Add macro NATIVE_INT_PU20K
by gerrit＠coreboot.org 27 Jan '16

27 Jan '16

the following patch was just integrated into master: commit fc5489fc5e620adf3ec9f3d692444aa4c2b3801e Author: Hannah Williams <hannah.williams(a)intel.com> Date: Tue Jan 19 11:58:58 2016 -0800 soc/braswell: Add macro NATIVE_INT_PU20K Change-Id: I04db02d37a76f0643a73ae4d67b839e5cd61f7e3 Signed-off-by: Hannah Williams <hannah.williams(a)intel.com> Reviewed-on: https://review.coreboot.org/13054 Reviewed-by: Martin Roth <martinroth(a)google.com> Tested-by: build bot (Jenkins) See https://review.coreboot.org/13054 for details. -gerrit

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coreboot-gerrit January 2016