coreboot-gerrit January 2016

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Patch set updated for coreboot: arch/x86: Implement minimal bootblock for C_ENVIRONMENT_BOTOBLOCK
by Alexandru Gagniuc 27 Jan '16

27 Jan '16

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13485 -gerrit commit 0e46df1cbfd247d47f8a2a5d6824276bd28bd4a0 Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Tue Jan 26 18:22:43 2016 -0800 arch/x86: Implement minimal bootblock for C_ENVIRONMENT_BOTOBLOCK Some newer x86 systems can boot from non-memory-mapped boot media (e.g. EMMC). The bootblock may be backed by small amounts of SRAM, or other memory, similar to how most ARM chipsets work. In such cases, we may not have enough code space for romstage very early on. This means that CAR setup and early boot media (e.g. SPI, EMMC) drivers need to be implemented within the limited amount memory of storage available. Since the reset vector has to be contained in this early code memory, the bootblock is the best place to implement loading of other stages. Implement a bootblock which does the minimal initialization, up to, and including switch to protected mode. This then transfers control to platform-specific code. No stack is needed, and control is transferred via a "jmp" such that no stack operations are involved. Change-Id: I009b42b9a707cf11a74493bd4d8c189dc09b8ace Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- src/arch/x86/Makefile.inc | 1 + src/arch/x86/bootblock_crt0.S | 55 +++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 56 insertions(+) diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 6667731..9084b11 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -112,6 +112,7 @@ $(obj)/arch/x86/id.bootblock.o: $(obj)/build.h ifeq ($(CONFIG_C_ENVIRONMENT_BOOTBLOCK),y) +bootblock-y += bootblock_crt0.S bootblock-y += memlayout.ld ifeq ($(CONFIG_ARCH_BOOTBLOCK_X86_32),y) diff --git a/src/arch/x86/bootblock_crt0.S b/src/arch/x86/bootblock_crt0.S new file mode 100644 index 0000000..926cda0 --- /dev/null +++ b/src/arch/x86/bootblock_crt0.S @@ -0,0 +1,55 @@ +/* + * This is the modern bootblock. It is used by platforms which select + * C_ENVIRONMENT_BOOTBLOCK, and it prepares the system for C environment runtime + * setup. The actual setup is done by hardware-specific code. + * + * It provides a bootflow similar to other architectures, and thus is considered + * to be the modern approach. + * + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#define CR0_MP (1 << 1) +#define CR0_EM (1 << 2) + +#define CR4_OSFXSR (1 << 9) +#define CR4_OSXMMEXCPT (1 << 10) + +/* + * Include the old code for reset vector and protected mode entry. That code has + * withstood the test of time. + */ +#include <arch/x86/prologue.inc> +#include <cpu/x86/16bit/entry16.inc> +#include <cpu/x86/16bit/reset16.inc> +#include <cpu/x86/32bit/entry32.inc> + + +bootblock_protected_mode_entry: + /* Save BIST result */ + movd %eax, %mm0 + /* Save an early timestamp */ + rdtsc + movd %eax, %mm1 + movd %edx, %mm2 + +#if !IS_ENABLED(CONFIG_SSE) +enable_sse: + mov %cr0, %eax + and $~CR0_EM, %ax /* Clear coprocessor emulation CR0.EM */ + or $CR0_MP, %ax /* Set coprocessor monitoring CR0.MP */ + mov %eax, %cr0 + mov %cr4, %eax + or $(CR4_OSFXSR | CR4_OSXMMEXCPT), %ax + mov %eax, %cr4 +#endif /* IS_ENABLED(CONFIG_SSE) */ + + /* We're done. Now it's up to platform-specific code */ + jmp bootblock_pre_c_entry

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Patch set updated for coreboot: drivers/intel/fsp1_1: Remove extra include references
by Leroy P Leahy 27 Jan '16

27 Jan '16

Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13436 -gerrit commit ba68cbb2ebaba50ed4ab881febc1f1775b9f7557 Author: Lee Leahy <lpleahyjr(a)gmail.com> Date: Fri Jan 1 18:09:50 2016 -0800 drivers/intel/fsp1_1: Remove extra include references Remove include references to the soc include directory which are not required to build the FSP driver. Remove "duplicate" include file definitions from file that include fsp/romstage.h. Move the definition of fill_power_state into soc/pm.h to ensure it is still available. TEST=Build and run on Galileo Change-Id: Ie519b3a8da8c36b47da512d3811796eab62ce208 Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- src/drivers/intel/fsp1_1/include/fsp/romstage.h | 4 ++-- src/drivers/intel/fsp1_1/raminit.c | 5 ++--- src/drivers/intel/fsp1_1/romstage.c | 12 ++---------- src/drivers/intel/fsp1_1/stack.c | 3 +-- src/soc/intel/braswell/include/soc/pm.h | 4 +++- src/soc/intel/braswell/include/soc/romstage.h | 3 +-- src/soc/intel/skylake/include/soc/pm.h | 4 +++- src/soc/intel/skylake/include/soc/romstage.h | 4 +--- 8 files changed, 15 insertions(+), 24 deletions(-) diff --git a/src/drivers/intel/fsp1_1/include/fsp/romstage.h b/src/drivers/intel/fsp1_1/include/fsp/romstage.h index eddf346..4683f5e 100644 --- a/src/drivers/intel/fsp1_1/include/fsp/romstage.h +++ b/src/drivers/intel/fsp1_1/include/fsp/romstage.h @@ -2,7 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015 Intel Corporation. + * Copyright (C) 2015-2016 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -23,7 +23,7 @@ #include <fsp/car.h> #include <fsp/util.h> #include <soc/intel/common/util.h> -#include <soc/pei_data.h> +#include <soc/pei_wrapper.h> #include <soc/pm.h> /* chip_power_state */ struct romstage_params { diff --git a/src/drivers/intel/fsp1_1/raminit.c b/src/drivers/intel/fsp1_1/raminit.c index 2ba77e3..e505b93 100644 --- a/src/drivers/intel/fsp1_1/raminit.c +++ b/src/drivers/intel/fsp1_1/raminit.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014-2015 Intel Corporation + * Copyright (C) 2014-2016 Intel Corporation * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -16,12 +16,11 @@ #include <cbmem.h> #include <console/console.h> #include <fsp/memmap.h> +#include <fsp/romstage.h> #include <fsp/util.h> #include <lib.h> /* hexdump */ #include <reset.h> #include <soc/intel/common/mma.h> -#include <soc/pei_data.h> -#include <soc/romstage.h> #include <string.h> #include <timestamp.h> #include <bootmode.h> diff --git a/src/drivers/intel/fsp1_1/romstage.c b/src/drivers/intel/fsp1_1/romstage.c index 16db4df..4402f9d 100644 --- a/src/drivers/intel/fsp1_1/romstage.c +++ b/src/drivers/intel/fsp1_1/romstage.c @@ -2,7 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015 Intel Corporation. + * Copyright (C) 2015-2016 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -15,8 +15,6 @@ */ #include <stddef.h> -#include <stdint.h> -#include <arch/cpu.h> #include <arch/io.h> #include <arch/cbfs.h> #include <arch/stages.h> @@ -28,17 +26,11 @@ #include <ec/google/chromeec/ec.h> #include <ec/google/chromeec/ec_commands.h> #include <elog.h> -#include <fsp/util.h> -#include <memory_info.h> +#include <fsp/romstage.h> #include <reset.h> #include <romstage_handoff.h> #include <smbios.h> #include <soc/intel/common/mrc_cache.h> -#include <soc/intel/common/util.h> -#include <soc/pei_wrapper.h> -#include <soc/pm.h> -#include <soc/romstage.h> -#include <soc/spi.h> #include <stage_cache.h> #include <timestamp.h> #include <tpm.h> diff --git a/src/drivers/intel/fsp1_1/stack.c b/src/drivers/intel/fsp1_1/stack.c index e5fd9a9..18a2454 100644 --- a/src/drivers/intel/fsp1_1/stack.c +++ b/src/drivers/intel/fsp1_1/stack.c @@ -2,7 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2013 Google Inc. - * Copyright (C) 2015 Intel Corp. + * Copyright (C) 2015-2016 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -20,7 +20,6 @@ #include <fsp/memmap.h> #include <fsp/romstage.h> #include <fsp/stack.h> -#include <soc/intel/common/util.h> #include <stdlib.h> const unsigned long romstage_ram_stack_size = CONFIG_ROMSTAGE_RAM_STACK_SIZE; diff --git a/src/soc/intel/braswell/include/soc/pm.h b/src/soc/intel/braswell/include/soc/pm.h index 9708b39..9e527e1 100644 --- a/src/soc/intel/braswell/include/soc/pm.h +++ b/src/soc/intel/braswell/include/soc/pm.h @@ -2,7 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2013 Google Inc. - * Copyright (C) 2015 Intel Corp. + * Copyright (C) 2015-2016 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -235,6 +235,8 @@ struct chipset_power_state { int prev_sleep_state; } __attribute__((packed)); +struct chipset_power_state *fill_power_state(void); + /* Power Management Utility Functions. */ uint16_t get_pmbase(void); uint32_t clear_smi_status(void); diff --git a/src/soc/intel/braswell/include/soc/romstage.h b/src/soc/intel/braswell/include/soc/romstage.h index e70510b..fc4f864 100644 --- a/src/soc/intel/braswell/include/soc/romstage.h +++ b/src/soc/intel/braswell/include/soc/romstage.h @@ -2,7 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2013 Google Inc. - * Copyright (C) 2015 Intel Corp. + * Copyright (C) 2015-2016 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -33,7 +33,6 @@ void set_max_freq(void); /* romstage_common.c functions */ void program_base_addresses(void); -struct chipset_power_state *fill_power_state(void); int chipset_prev_sleep_state(struct chipset_power_state *ps); #endif /* _SOC_ROMSTAGE_H_ */ diff --git a/src/soc/intel/skylake/include/soc/pm.h b/src/soc/intel/skylake/include/soc/pm.h index 79861e9..a89b764 100644 --- a/src/soc/intel/skylake/include/soc/pm.h +++ b/src/soc/intel/skylake/include/soc/pm.h @@ -2,7 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015 Intel Corporation. + * Copyright (C) 2015-2016 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -159,6 +159,8 @@ struct chipset_power_state { uint32_t prev_sleep_state; } __attribute__ ((packed)); +struct chipset_power_state *fill_power_state(void); + /* PM1_CNT */ void enable_pm1_control(uint32_t mask); void disable_pm1_control(uint32_t mask); diff --git a/src/soc/intel/skylake/include/soc/romstage.h b/src/soc/intel/skylake/include/soc/romstage.h index 5e73e1c..7fab8ce 100644 --- a/src/soc/intel/skylake/include/soc/romstage.h +++ b/src/soc/intel/skylake/include/soc/romstage.h @@ -2,7 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015 Intel Corporation. + * Copyright (C) 2015-2016 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -19,8 +19,6 @@ #include <fsp/romstage.h> -struct chipset_power_state; -struct chipset_power_state *fill_power_state(void); void systemagent_early_init(void); void pch_early_init(void); void pch_uart_init(void);

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Patch set updated for coreboot: soc/apollolake: Rewrite assembly in ATT, per Google's demand
by Alexandru Gagniuc 27 Jan '16

27 Jan '16

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13492 -gerrit commit 049b2357ed3fa4805d3c7e010a0b6df704c9cbc7 Author: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> Date: Wed Jan 27 10:06:18 2016 -0800 soc/apollolake: Rewrite assembly in ATT, per Google's demand Change-Id: Ief78cba4a771fc6549ee204f5df81bc93245a4a1 Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> --- src/soc/intel/apollolake/bootblock/cache_as_ram.S | 85 ++++++++++------------ .../apollolake/bootblock/early_chipset_config.S | 44 +++++------ src/soc/intel/apollolake/romstage/entry.inc | 5 +- 3 files changed, 61 insertions(+), 73 deletions(-) diff --git a/src/soc/intel/apollolake/bootblock/cache_as_ram.S b/src/soc/intel/apollolake/bootblock/cache_as_ram.S index 6ecfa86..1713877 100644 --- a/src/soc/intel/apollolake/bootblock/cache_as_ram.S +++ b/src/soc/intel/apollolake/bootblock/cache_as_ram.S @@ -21,101 +21,96 @@ #define EVICT_CTL_MSR 0x2e0 -.intel_syntax noprefix - -#undef post_code -#define post_code(value) \ - mov al, value; \ - outb CONFIG_POST_IO_PORT, al .global cache_as_ram cache_as_ram: post_code(0x21) /* Clear/disable fixed MTRRs */ - mov ebx, offset fixed_mtrr_list_size - xor eax, eax - xor edx, edx + mov $fixed_mtrr_list_size, %ebx + xor %eax, %eax + xor %edx, %edx clear_fixed_mtrr: - add ebx, -2 - movzxw ecx, word ptr [fixed_mtrr_list + ebx] + add $-2, %ebx + movzwl fixed_mtrr_list(%ebx), %ecx wrmsr jnz clear_fixed_mtrr post_code(0x22) /* Figure put how many MTRRs we have, and clear them out */ - mov ecx, MTRR_CAP_MSR + mov $MTRR_CAP_MSR, %ecx rdmsr - movzxb ebx, al /* Number of variable MTRRs */ - mov ecx, MTRR_PHYS_BASE(0) - xor eax, eax - xor edx, edx + movzb %al, %ebx /* Number of variable MTRRs */ + mov $MTRR_PHYS_BASE(0), %ecx + xor %eax, %eax + xor %edx, %edx + clear_var_mtrr: wrmsr - inc ecx + inc %ecx wrmsr - inc ecx - dec ebx + inc %ecx + dec %ebx jnz clear_var_mtrr post_code(0x23) /* Configure default memory type to uncacheable (UC) */ - mov ecx, MTRR_DEF_TYPE_MSR + mov $MTRR_DEF_TYPE_MSR, %ecx rdmsr - and eax, ~0xcff + and $~0xcff, %eax wrmsr post_code(0x24) /* Configure CAR region as write-back (WB) */ - mov ecx, MTRR_PHYS_BASE(0) - mov eax, CONFIG_DCACHE_RAM_BASE /* base */ - or eax, MTRR_TYPE_WRBACK - xor edx, edx + mov $MTRR_PHYS_BASE(0), %ecx + mov $CONFIG_DCACHE_RAM_BASE, %eax + or $MTRR_TYPE_WRBACK, %eax + xor %edx,%edx wrmsr /* Configure the MTRR mask for the size region */ - mov ecx, MTRR_PHYS_MASK(0) - mov eax, ~(CONFIG_DCACHE_RAM_SIZE - 1) /* size mask */ - or eax, MTRR_PHYS_MASK_VALID + mov $MTRR_PHYS_MASK(0), %ecx + mov $~(CONFIG_DCACHE_RAM_SIZE - 1), %eax /* size mask */ + or $0x800, %eax wrmsr post_code(0x25) /* Enable variable MTRRs */ - mov ecx, MTRR_DEF_TYPE_MSR + mov $MTRR_DEF_TYPE_MSR, %ecx rdmsr - or eax, MTRR_DEF_TYPE_EN + or $MTRR_DEF_TYPE_EN, %eax wrmsr /* Cache tricks */ - mov eax, cr0 - and eax, ~(CR0_CACHE_DISABLE | CR0_NO_WRITE) + mov %cr0, %eax + and $~(CR0_CACHE_DISABLE | CR0_NO_WRITE), %eax invd - mov cr0, eax + mov %eax, %cr0 /* Disable cache eviction (setup stage) */ - mov ecx, EVICT_CTL_MSR + mov $EVICT_CTL_MSR, %ecx rdmsr - or eax, 1 + or $0x1, %eax wrmsr post_code(0x26) /* Clear the cache memory region. This will also fill up the cache */ - mov edi, CONFIG_DCACHE_RAM_BASE - mov ecx, CONFIG_DCACHE_RAM_SIZE >> 2 - xor eax, eax - rep stos dword ptr es:[edi], eax + mov $CONFIG_DCACHE_RAM_BASE, %edi + mov $(CONFIG_DCACHE_RAM_SIZE >> 2), %ecx + xor %eax, %eax + rep stos %eax, %es:(%edi) post_code(0x27) /* Disable cache eviction (run stage) */ - mov ecx, EVICT_CTL_MSR + mov $EVICT_CTL_MSR, %ecx rdmsr - or eax, 2 + or $0x2, %eax wrmsr post_code(0x28) @@ -123,13 +118,13 @@ clear_var_mtrr: car_init_done: /* Setup bootblock stack */ - mov esp, CONFIG_DCACHE_RAM_BASE - add esp, CONFIG_DCACHE_RAM_BOOTBLOCK_STACK_SIZE + mov $CONFIG_DCACHE_RAM_BASE, %esp + add $CONFIG_DCACHE_RAM_BOOTBLOCK_STACK_SIZE, %esp /* Make sure CAR region is executable */ - mov ecx, 0x120 + mov $0x120, %ecx rdmsr - or ah, 0x1 + or $0x1, %ah wrmsr before_carstage: diff --git a/src/soc/intel/apollolake/bootblock/early_chipset_config.S b/src/soc/intel/apollolake/bootblock/early_chipset_config.S index a673a28..4f35211 100644 --- a/src/soc/intel/apollolake/bootblock/early_chipset_config.S +++ b/src/soc/intel/apollolake/bootblock/early_chipset_config.S @@ -10,6 +10,7 @@ * (at your option) any later version. */ +#include <cpu/x86/post_code.h> #include <soc/gpio_defs.h> /* Definitions used only here, for getting the MMIO base of LPC pad registers */ @@ -17,47 +18,40 @@ #define PAD_MMIO_ADDR(pad) (CONFIG_IOSF_BASE_ADDRESS + XLATE_LPC(pad)) -.intel_syntax noprefix -.extern cache_as_ram - -#define post_code(value) \ - mov al, value; \ - outb CONFIG_POST_IO_PORT, al - .global bootblock_pre_c_entry bootblock_pre_c_entry: /* * eax: BIST value */ - movd mm2, eax + movd %eax, %mm2 post_code(0x20) enable_pciex_bar: - mov eax, 0x80000060 /* ROOT PCI device reg60 PCIEX_BAR_*/ - mov dx, 0xcf8 - out dx, eax - mov eax, (CONFIG_MMCONF_BASE_ADDRESS | 1) - mov dx, 0xcfc - out dx, eax + mov $0x80000060, %eax /* ROOT PCI device reg60 PCIEX_BAR_*/ + mov $0xcf8, %dx + out %eax, %dx + mov $(CONFIG_MMCONF_BASE_ADDRESS | 1), %eax + mov $0xcfc, %dx + out %eax, %dx enable_iosf_bar: - mov ebp, 0xe0068000 /* IOSF PCI device */ - mov dword ptr [ebp + 0x10], CONFIG_IOSF_BASE_ADDRESS /* BAR 0 */ - mov word ptr [ebp + 0x04], 0x06 /* PCI command */ + mov $0xe0068000, %ebp /* IOSF PCI device */ + movl $CONFIG_IOSF_BASE_ADDRESS, 0x10(%ebp) /* BAR 0 */ + movl $0x06, 0x04(%ebp) /* PCI command */ /* We need LPC for port80, but it won't work if the pads are not configured */ configure_lpc_pads: - mov ecx, offset num_lpc_pads /* Number of pads to configure */ - lea esi, lpc_pad_params + mov $num_lpc_pads, %ecx /* Number of pads to configure */ + lea lpc_pad_params, %esi init_lpc_pad: - mov edi, [esi + 0x00] /* MMIO addr of pad config registers */ - mov eax, [esi + 0x04] /* Pad CONF0 value */ - mov edx, [esi + 0x08] /* Pad CONF1 value */ - mov [edi + 0x00], eax /* Write CONF0 to config register */ - mov [edi + 0x04], edx /* Write CONF1 to config register */ - add esi, 0x0c + mov 0x00(%esi), %edi /* MMIO addr of pad config registers */ + mov 0x04(%esi), %eax /* Pad CONF0 value */ + mov 0x08(%esi), %edx /* Pad CONF1 value */ + mov %eax, 0x00(%edi) /* Write CONF0 to config register */ + mov %edx, 0x04(%edi) /* Write CONF1 to config register */ + add $0x0c, %esi loop init_lpc_pad jmp cache_as_ram diff --git a/src/soc/intel/apollolake/romstage/entry.inc b/src/soc/intel/apollolake/romstage/entry.inc index 2c6dfd6..2e018ae 100644 --- a/src/soc/intel/apollolake/romstage/entry.inc +++ b/src/soc/intel/apollolake/romstage/entry.inc @@ -10,13 +10,12 @@ * (at your option) any later version. */ -.intel_syntax noprefix apollolake_entry: /* * TODO: Make sure the stack does not clash with .car.data. */ - mov esp, (CONFIG_DCACHE_RAM_BASE + 0x4000) + mov $(CONFIG_DCACHE_RAM_BASE + 0x4000), %esp call romstage_entry @@ -25,7 +24,7 @@ apollolake_entry: * to use as stack. The old stack is empty at this point, so we don't * have to relocate anything. */ - mov esp, eax + mov %eax, %esp /* * TODO: set up temporary cache for RAM

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New patch to review for coreboot: soc/apollolake: Rewrite assembly in ATT, per Google's feedback
by Alexandru Gagniuc 27 Jan '16

27 Jan '16

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13492 -gerrit commit 4b7f2a81fea7a0328e5cb825c791a8cb6972c4e9 Author: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> Date: Wed Jan 27 10:06:18 2016 -0800 soc/apollolake: Rewrite assembly in ATT, per Google's feedback Change-Id: Ief78cba4a771fc6549ee204f5df81bc93245a4a1 Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> --- src/soc/intel/apollolake/bootblock/cache_as_ram.S | 85 ++++++++++------------ .../apollolake/bootblock/early_chipset_config.S | 44 +++++------ src/soc/intel/apollolake/romstage/entry.inc | 5 +- 3 files changed, 61 insertions(+), 73 deletions(-) diff --git a/src/soc/intel/apollolake/bootblock/cache_as_ram.S b/src/soc/intel/apollolake/bootblock/cache_as_ram.S index 6ecfa86..1713877 100644 --- a/src/soc/intel/apollolake/bootblock/cache_as_ram.S +++ b/src/soc/intel/apollolake/bootblock/cache_as_ram.S @@ -21,101 +21,96 @@ #define EVICT_CTL_MSR 0x2e0 -.intel_syntax noprefix - -#undef post_code -#define post_code(value) \ - mov al, value; \ - outb CONFIG_POST_IO_PORT, al .global cache_as_ram cache_as_ram: post_code(0x21) /* Clear/disable fixed MTRRs */ - mov ebx, offset fixed_mtrr_list_size - xor eax, eax - xor edx, edx + mov $fixed_mtrr_list_size, %ebx + xor %eax, %eax + xor %edx, %edx clear_fixed_mtrr: - add ebx, -2 - movzxw ecx, word ptr [fixed_mtrr_list + ebx] + add $-2, %ebx + movzwl fixed_mtrr_list(%ebx), %ecx wrmsr jnz clear_fixed_mtrr post_code(0x22) /* Figure put how many MTRRs we have, and clear them out */ - mov ecx, MTRR_CAP_MSR + mov $MTRR_CAP_MSR, %ecx rdmsr - movzxb ebx, al /* Number of variable MTRRs */ - mov ecx, MTRR_PHYS_BASE(0) - xor eax, eax - xor edx, edx + movzb %al, %ebx /* Number of variable MTRRs */ + mov $MTRR_PHYS_BASE(0), %ecx + xor %eax, %eax + xor %edx, %edx + clear_var_mtrr: wrmsr - inc ecx + inc %ecx wrmsr - inc ecx - dec ebx + inc %ecx + dec %ebx jnz clear_var_mtrr post_code(0x23) /* Configure default memory type to uncacheable (UC) */ - mov ecx, MTRR_DEF_TYPE_MSR + mov $MTRR_DEF_TYPE_MSR, %ecx rdmsr - and eax, ~0xcff + and $~0xcff, %eax wrmsr post_code(0x24) /* Configure CAR region as write-back (WB) */ - mov ecx, MTRR_PHYS_BASE(0) - mov eax, CONFIG_DCACHE_RAM_BASE /* base */ - or eax, MTRR_TYPE_WRBACK - xor edx, edx + mov $MTRR_PHYS_BASE(0), %ecx + mov $CONFIG_DCACHE_RAM_BASE, %eax + or $MTRR_TYPE_WRBACK, %eax + xor %edx,%edx wrmsr /* Configure the MTRR mask for the size region */ - mov ecx, MTRR_PHYS_MASK(0) - mov eax, ~(CONFIG_DCACHE_RAM_SIZE - 1) /* size mask */ - or eax, MTRR_PHYS_MASK_VALID + mov $MTRR_PHYS_MASK(0), %ecx + mov $~(CONFIG_DCACHE_RAM_SIZE - 1), %eax /* size mask */ + or $0x800, %eax wrmsr post_code(0x25) /* Enable variable MTRRs */ - mov ecx, MTRR_DEF_TYPE_MSR + mov $MTRR_DEF_TYPE_MSR, %ecx rdmsr - or eax, MTRR_DEF_TYPE_EN + or $MTRR_DEF_TYPE_EN, %eax wrmsr /* Cache tricks */ - mov eax, cr0 - and eax, ~(CR0_CACHE_DISABLE | CR0_NO_WRITE) + mov %cr0, %eax + and $~(CR0_CACHE_DISABLE | CR0_NO_WRITE), %eax invd - mov cr0, eax + mov %eax, %cr0 /* Disable cache eviction (setup stage) */ - mov ecx, EVICT_CTL_MSR + mov $EVICT_CTL_MSR, %ecx rdmsr - or eax, 1 + or $0x1, %eax wrmsr post_code(0x26) /* Clear the cache memory region. This will also fill up the cache */ - mov edi, CONFIG_DCACHE_RAM_BASE - mov ecx, CONFIG_DCACHE_RAM_SIZE >> 2 - xor eax, eax - rep stos dword ptr es:[edi], eax + mov $CONFIG_DCACHE_RAM_BASE, %edi + mov $(CONFIG_DCACHE_RAM_SIZE >> 2), %ecx + xor %eax, %eax + rep stos %eax, %es:(%edi) post_code(0x27) /* Disable cache eviction (run stage) */ - mov ecx, EVICT_CTL_MSR + mov $EVICT_CTL_MSR, %ecx rdmsr - or eax, 2 + or $0x2, %eax wrmsr post_code(0x28) @@ -123,13 +118,13 @@ clear_var_mtrr: car_init_done: /* Setup bootblock stack */ - mov esp, CONFIG_DCACHE_RAM_BASE - add esp, CONFIG_DCACHE_RAM_BOOTBLOCK_STACK_SIZE + mov $CONFIG_DCACHE_RAM_BASE, %esp + add $CONFIG_DCACHE_RAM_BOOTBLOCK_STACK_SIZE, %esp /* Make sure CAR region is executable */ - mov ecx, 0x120 + mov $0x120, %ecx rdmsr - or ah, 0x1 + or $0x1, %ah wrmsr before_carstage: diff --git a/src/soc/intel/apollolake/bootblock/early_chipset_config.S b/src/soc/intel/apollolake/bootblock/early_chipset_config.S index a673a28..4f35211 100644 --- a/src/soc/intel/apollolake/bootblock/early_chipset_config.S +++ b/src/soc/intel/apollolake/bootblock/early_chipset_config.S @@ -10,6 +10,7 @@ * (at your option) any later version. */ +#include <cpu/x86/post_code.h> #include <soc/gpio_defs.h> /* Definitions used only here, for getting the MMIO base of LPC pad registers */ @@ -17,47 +18,40 @@ #define PAD_MMIO_ADDR(pad) (CONFIG_IOSF_BASE_ADDRESS + XLATE_LPC(pad)) -.intel_syntax noprefix -.extern cache_as_ram - -#define post_code(value) \ - mov al, value; \ - outb CONFIG_POST_IO_PORT, al - .global bootblock_pre_c_entry bootblock_pre_c_entry: /* * eax: BIST value */ - movd mm2, eax + movd %eax, %mm2 post_code(0x20) enable_pciex_bar: - mov eax, 0x80000060 /* ROOT PCI device reg60 PCIEX_BAR_*/ - mov dx, 0xcf8 - out dx, eax - mov eax, (CONFIG_MMCONF_BASE_ADDRESS | 1) - mov dx, 0xcfc - out dx, eax + mov $0x80000060, %eax /* ROOT PCI device reg60 PCIEX_BAR_*/ + mov $0xcf8, %dx + out %eax, %dx + mov $(CONFIG_MMCONF_BASE_ADDRESS | 1), %eax + mov $0xcfc, %dx + out %eax, %dx enable_iosf_bar: - mov ebp, 0xe0068000 /* IOSF PCI device */ - mov dword ptr [ebp + 0x10], CONFIG_IOSF_BASE_ADDRESS /* BAR 0 */ - mov word ptr [ebp + 0x04], 0x06 /* PCI command */ + mov $0xe0068000, %ebp /* IOSF PCI device */ + movl $CONFIG_IOSF_BASE_ADDRESS, 0x10(%ebp) /* BAR 0 */ + movl $0x06, 0x04(%ebp) /* PCI command */ /* We need LPC for port80, but it won't work if the pads are not configured */ configure_lpc_pads: - mov ecx, offset num_lpc_pads /* Number of pads to configure */ - lea esi, lpc_pad_params + mov $num_lpc_pads, %ecx /* Number of pads to configure */ + lea lpc_pad_params, %esi init_lpc_pad: - mov edi, [esi + 0x00] /* MMIO addr of pad config registers */ - mov eax, [esi + 0x04] /* Pad CONF0 value */ - mov edx, [esi + 0x08] /* Pad CONF1 value */ - mov [edi + 0x00], eax /* Write CONF0 to config register */ - mov [edi + 0x04], edx /* Write CONF1 to config register */ - add esi, 0x0c + mov 0x00(%esi), %edi /* MMIO addr of pad config registers */ + mov 0x04(%esi), %eax /* Pad CONF0 value */ + mov 0x08(%esi), %edx /* Pad CONF1 value */ + mov %eax, 0x00(%edi) /* Write CONF0 to config register */ + mov %edx, 0x04(%edi) /* Write CONF1 to config register */ + add $0x0c, %esi loop init_lpc_pad jmp cache_as_ram diff --git a/src/soc/intel/apollolake/romstage/entry.inc b/src/soc/intel/apollolake/romstage/entry.inc index 2c6dfd6..2e018ae 100644 --- a/src/soc/intel/apollolake/romstage/entry.inc +++ b/src/soc/intel/apollolake/romstage/entry.inc @@ -10,13 +10,12 @@ * (at your option) any later version. */ -.intel_syntax noprefix apollolake_entry: /* * TODO: Make sure the stack does not clash with .car.data. */ - mov esp, (CONFIG_DCACHE_RAM_BASE + 0x4000) + mov $(CONFIG_DCACHE_RAM_BASE + 0x4000), %esp call romstage_entry @@ -25,7 +24,7 @@ apollolake_entry: * to use as stack. The old stack is empty at this point, so we don't * have to relocate anything. */ - mov esp, eax + mov %eax, %esp /* * TODO: set up temporary cache for RAM

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New patch to review for coreboot: gigabyte/ga-g41m-es2l: default MAINBOARD_DO_NATIVE_VGA_INIT to y
by Martin Roth 27 Jan '16

27 Jan '16

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13491 -gerrit commit 43751e98e4a61159f614ce1038a74fb936501ca8 Author: Martin Roth <martinroth(a)google.com> Date: Wed Jan 27 10:31:32 2016 -0700 gigabyte/ga-g41m-es2l: default MAINBOARD_DO_NATIVE_VGA_INIT to y The select of MAINBOARD_DO_NATIVE_VGA_INIT was removed in commit 345f2b7d (ga-g41m-es2l: Instead of forcing native VGA, make it selectable). We still want it to be enabled by default, we just want to allow the user to turn it off if they choose. Change-Id: Ia72189c21b9c412b093c36100bd324518849ccdb Signed-off-by: Martin Roth <martinroth(a)google.com> --- src/mainboard/gigabyte/ga-g41m-es2l/Kconfig | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/Kconfig b/src/mainboard/gigabyte/ga-g41m-es2l/Kconfig index cf1077b..c812ede 100644 --- a/src/mainboard/gigabyte/ga-g41m-es2l/Kconfig +++ b/src/mainboard/gigabyte/ga-g41m-es2l/Kconfig @@ -27,6 +27,9 @@ config BOARD_SPECIFIC_OPTIONS select INTEL_EDID select MAINBOARD_HAS_NATIVE_VGA_INIT +config MAINBOARD_DO_NATIVE_VGA_INIT + def_bool y + config MMCONF_BASE_ADDRESS hex default 0xc0000000

1 0

Patch set updated for coreboot: drivers/intel/fsp1_1: Remove extra include references
by Leroy P Leahy 27 Jan '16

27 Jan '16

Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13436 -gerrit commit a572a34408d92bd0f96f3d494ee6ebf28796117e Author: Lee Leahy <lpleahyjr(a)gmail.com> Date: Fri Jan 1 18:09:50 2016 -0800 drivers/intel/fsp1_1: Remove extra include references Remove include references to the soc include directory which are not required to build the FSP driver. Remove "duplicate" include file definitions from file that include fsp/romstage.h. Move the definition of fill_power_state into soc/pm.h to ensure it is still available. TEST=Build and run on Galileo Change-Id: Ie519b3a8da8c36b47da512d3811796eab62ce208 Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- src/drivers/intel/fsp1_1/include/fsp/romstage.h | 2 +- src/drivers/intel/fsp1_1/raminit.c | 5 ++--- src/drivers/intel/fsp1_1/romstage.c | 12 ++---------- src/drivers/intel/fsp1_1/stack.c | 1 - src/soc/intel/braswell/include/soc/pm.h | 2 ++ src/soc/intel/braswell/include/soc/romstage.h | 1 - src/soc/intel/skylake/include/soc/pm.h | 2 ++ src/soc/intel/skylake/include/soc/romstage.h | 2 -- 8 files changed, 9 insertions(+), 18 deletions(-) diff --git a/src/drivers/intel/fsp1_1/include/fsp/romstage.h b/src/drivers/intel/fsp1_1/include/fsp/romstage.h index eddf346..61f4f14 100644 --- a/src/drivers/intel/fsp1_1/include/fsp/romstage.h +++ b/src/drivers/intel/fsp1_1/include/fsp/romstage.h @@ -23,7 +23,7 @@ #include <fsp/car.h> #include <fsp/util.h> #include <soc/intel/common/util.h> -#include <soc/pei_data.h> +#include <soc/pei_wrapper.h> #include <soc/pm.h> /* chip_power_state */ struct romstage_params { diff --git a/src/drivers/intel/fsp1_1/raminit.c b/src/drivers/intel/fsp1_1/raminit.c index 2ba77e3..e505b93 100644 --- a/src/drivers/intel/fsp1_1/raminit.c +++ b/src/drivers/intel/fsp1_1/raminit.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014-2015 Intel Corporation + * Copyright (C) 2014-2016 Intel Corporation * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -16,12 +16,11 @@ #include <cbmem.h> #include <console/console.h> #include <fsp/memmap.h> +#include <fsp/romstage.h> #include <fsp/util.h> #include <lib.h> /* hexdump */ #include <reset.h> #include <soc/intel/common/mma.h> -#include <soc/pei_data.h> -#include <soc/romstage.h> #include <string.h> #include <timestamp.h> #include <bootmode.h> diff --git a/src/drivers/intel/fsp1_1/romstage.c b/src/drivers/intel/fsp1_1/romstage.c index 16db4df..4402f9d 100644 --- a/src/drivers/intel/fsp1_1/romstage.c +++ b/src/drivers/intel/fsp1_1/romstage.c @@ -2,7 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015 Intel Corporation. + * Copyright (C) 2015-2016 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -15,8 +15,6 @@ */ #include <stddef.h> -#include <stdint.h> -#include <arch/cpu.h> #include <arch/io.h> #include <arch/cbfs.h> #include <arch/stages.h> @@ -28,17 +26,11 @@ #include <ec/google/chromeec/ec.h> #include <ec/google/chromeec/ec_commands.h> #include <elog.h> -#include <fsp/util.h> -#include <memory_info.h> +#include <fsp/romstage.h> #include <reset.h> #include <romstage_handoff.h> #include <smbios.h> #include <soc/intel/common/mrc_cache.h> -#include <soc/intel/common/util.h> -#include <soc/pei_wrapper.h> -#include <soc/pm.h> -#include <soc/romstage.h> -#include <soc/spi.h> #include <stage_cache.h> #include <timestamp.h> #include <tpm.h> diff --git a/src/drivers/intel/fsp1_1/stack.c b/src/drivers/intel/fsp1_1/stack.c index e5fd9a9..6444ab8 100644 --- a/src/drivers/intel/fsp1_1/stack.c +++ b/src/drivers/intel/fsp1_1/stack.c @@ -20,7 +20,6 @@ #include <fsp/memmap.h> #include <fsp/romstage.h> #include <fsp/stack.h> -#include <soc/intel/common/util.h> #include <stdlib.h> const unsigned long romstage_ram_stack_size = CONFIG_ROMSTAGE_RAM_STACK_SIZE; diff --git a/src/soc/intel/braswell/include/soc/pm.h b/src/soc/intel/braswell/include/soc/pm.h index 9708b39..79a6592 100644 --- a/src/soc/intel/braswell/include/soc/pm.h +++ b/src/soc/intel/braswell/include/soc/pm.h @@ -235,6 +235,8 @@ struct chipset_power_state { int prev_sleep_state; } __attribute__((packed)); +struct chipset_power_state *fill_power_state(void); + /* Power Management Utility Functions. */ uint16_t get_pmbase(void); uint32_t clear_smi_status(void); diff --git a/src/soc/intel/braswell/include/soc/romstage.h b/src/soc/intel/braswell/include/soc/romstage.h index e70510b..262797d 100644 --- a/src/soc/intel/braswell/include/soc/romstage.h +++ b/src/soc/intel/braswell/include/soc/romstage.h @@ -33,7 +33,6 @@ void set_max_freq(void); /* romstage_common.c functions */ void program_base_addresses(void); -struct chipset_power_state *fill_power_state(void); int chipset_prev_sleep_state(struct chipset_power_state *ps); #endif /* _SOC_ROMSTAGE_H_ */ diff --git a/src/soc/intel/skylake/include/soc/pm.h b/src/soc/intel/skylake/include/soc/pm.h index 79861e9..31cf7b4 100644 --- a/src/soc/intel/skylake/include/soc/pm.h +++ b/src/soc/intel/skylake/include/soc/pm.h @@ -159,6 +159,8 @@ struct chipset_power_state { uint32_t prev_sleep_state; } __attribute__ ((packed)); +struct chipset_power_state *fill_power_state(void); + /* PM1_CNT */ void enable_pm1_control(uint32_t mask); void disable_pm1_control(uint32_t mask); diff --git a/src/soc/intel/skylake/include/soc/romstage.h b/src/soc/intel/skylake/include/soc/romstage.h index 5e73e1c..e65bce2 100644 --- a/src/soc/intel/skylake/include/soc/romstage.h +++ b/src/soc/intel/skylake/include/soc/romstage.h @@ -19,8 +19,6 @@ #include <fsp/romstage.h> -struct chipset_power_state; -struct chipset_power_state *fill_power_state(void); void systemagent_early_init(void); void pch_early_init(void); void pch_uart_init(void);

1 0

Patch set updated for coreboot: util/crossgcc: Add option to bootstrap a host gcc
by Nico Huber 27 Jan '16

27 Jan '16

Nico Huber (nico.h(a)gmx.de) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13473 -gerrit commit 180a84ddef993218b0cac11a97d4de6445490f64 Author: Nico Huber <nico.huber(a)secunet.com> Date: Tue Jan 26 16:10:17 2016 +0100 util/crossgcc: Add option to bootstrap a host gcc Bootstrapping gcc is the recommended way if your host gcc's version doesn't match the gcc version you're going to build. While a build with an outdated host gcc usually succeeds, an outdated gnat seems to be a bigger issue. Change-Id: Icb47d3e9dbafc55737fbc3ce62a084fb9d5f359a Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- util/crossgcc/Makefile | 3 ++- util/crossgcc/buildgcc | 38 +++++++++++++++++++++++++++++++++++--- 2 files changed, 37 insertions(+), 4 deletions(-) diff --git a/util/crossgcc/Makefile b/util/crossgcc/Makefile index 79e0c3c..4f5d919 100644 --- a/util/crossgcc/Makefile +++ b/util/crossgcc/Makefile @@ -25,7 +25,8 @@ build_tools: build_gcc build_iasl build_gdb build_gcc: bash ./buildgcc -p $(BUILD_PLATFORM) $(if $(CPUS),-j $(CPUS)) $(if $(KEEP_SOURCES),-t) $(BUILDGCC_OPTIONS) \ - $(if $(BUILD_LANGUAGES),-l $(BUILD_LANGUAGES)) + $(if $(BUILD_LANGUAGES),-l $(BUILD_LANGUAGES)) \ + $(if $(BUILD_BOOTSTRAP),-b) \ build_gdb: ifeq ($(SKIP_GDB),) diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index 61c26d9..1150bdc 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -19,7 +19,7 @@ cd $(dirname $0) CROSSGCC_DATE="January 26th, 2016" -CROSSGCC_VERSION="1.35" +CROSSGCC_VERSION="1.36" # default settings PACKAGE=GCC @@ -31,6 +31,7 @@ DESTDIR= CLEANHOST=0 SAVETEMPS=0 SKIPPYTHON=1 +BOOTSTRAP=0 # GCC toolchain version numbers GMP_VERSION=6.1.0 @@ -367,6 +368,8 @@ myhelp() printf " [-P|--package <package>] Build a specific package: GCC, CLANG, IASL, GDB\n" printf " (defaults to $PACKAGE)\n" printf "GCC specific options:\n" + printf " [-b|--bootstrap] bootstrap the host compiler before building\n" + printf " the cross compiler\n" printf " [-p|--platform <platform>] target platform to build cross compiler for\n" printf " (defaults to $TARGETARCH)\n" printf " [-l|--languages <languages>] comma separated list of target languages\n" @@ -467,8 +470,24 @@ build_BINUTILS() { $MAKE install DESTDIR=$DESTDIR || touch .failed } +build_host_GCC() { + CC="$CC" CFLAGS_FOR_TARGET="-O2" BOOT_CFLAGS="-O2" \ + ../gcc-${GCC_VERSION}/configure \ + --prefix=$HOSTDIR --libexecdir=$HOSTDIR/lib \ + --enable-bootstrap \ + --disable-werror --disable-nls --disable-multilib \ + --disable-libssp --disable-libquadmath \ + ${GCC_OPTIONS} --enable-languages="${LANGUAGES}" \ + --with-gmp=$DESTDIR$HOSTDIR --with-mpfr=$DESTDIR$HOSTDIR \ + --with-mpc=$DESTDIR$HOSTDIR --with-libelf=$DESTDIR$HOSTDIR \ + --with-pkgversion="coreboot toolchain host bootstrap v$CROSSGCC_VERSION $CROSSGCC_DATE" \ + && \ + $MAKE $JOBS CFLAGS_FOR_BUILD="-O2" BOOT_CFLAGS="-O2" bootstrap && \ + $MAKE install DESTDIR=$DESTDIR && \ + ln -s gcc $DESTDIR$HOSTDIR/bin/cc || touch .failed +} -build_GCC() { +build_target_GCC() { # GCC does not honor HOSTCFLAGS at all. CFLAGS are used for # both target and host object files. # There's a work-around called CFLAGS_FOR_BUILD and CFLAGS_FOR_TARGET @@ -495,6 +514,14 @@ build_GCC() { fi } +build_GCC() { + if is_host_package $1; then + build_host_GCC $@ + else + build_target_GCC $@ + fi +} + build_EXPAT() { CC="$CC" CFLAGS="$HOSTCFLAGS" ../${EXPAT_DIR}/configure --disable-shared \ --prefix=$HOSTDIR --target=${TARGETARCH} || touch .failed @@ -614,6 +641,7 @@ while true ; do TARGETDIR="$(echo $1 | sed -e 's,/*$,,')" HOSTDIR="$TARGETDIR-host" shift;; + -b|--bootstrap) shift; BOOTSTRAP=1;; -p|--platform) shift; TARGETARCH="$1"; shift;; -l|--languages) shift; LANGUAGES="$1"; shift;; -D|--destdir) shift; DESTDIR="$1"; shift;; @@ -656,7 +684,11 @@ case "$PACKAGE" in GCC|gcc) echo "Target architecture is now $TARGETARCH" NAME="${TARGETARCH} cross GCC" - PACKAGES="host-GMP host-MPFR host-MPC host-LIBELF BINUTILS GCC" + if [ $BOOTSTRAP -eq 1 ]; then + PACKAGES="host-GMP host-MPFR host-MPC host-LIBELF host-GCC BINUTILS GCC" + else + PACKAGES="host-GMP host-MPFR host-MPC host-LIBELF BINUTILS GCC" + fi ;; GDB|gdb) NAME="${TARGETARCH} cross GDB"

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Patch set updated for coreboot: util/crossgcc: Build gmp, mpfr, mpc, libelf, expat, python and iasl for the host
by Nico Huber 27 Jan '16

27 Jan '16

Nico Huber (nico.h(a)gmx.de) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13472 -gerrit commit 25bf785188d95c82fe8cc9ba379c9a5fa561becb Author: Nico Huber <nico.huber(a)secunet.com> Date: Tue Jan 26 16:14:06 2016 +0100 util/crossgcc: Build gmp, mpfr, mpc, libelf, expat, python and iasl for the host Change-Id: I731cfe230304ccafad3e1f0527592c6a382e2cb1 Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- util/crossgcc/buildgcc | 54 +++++++++++++++++++++++++------------------------- 1 file changed, 27 insertions(+), 27 deletions(-) diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index d3a3cec..61c26d9 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -18,8 +18,8 @@ cd $(dirname $0) -CROSSGCC_DATE="November 25th, 2015" -CROSSGCC_VERSION="1.33" +CROSSGCC_DATE="January 26th, 2016" +CROSSGCC_VERSION="1.35" # default settings PACKAGE=GCC @@ -404,7 +404,7 @@ EOF } build_GMP() { - CC="$CC" CFLAGS="-Os" ../${GMP_DIR}/configure --disable-shared --enable-fat --prefix=$TARGETDIR $OPTIONS \ + CC="$CC" CFLAGS="-Os" ../${GMP_DIR}/configure --disable-shared --enable-fat --prefix=$HOSTDIR $OPTIONS \ || touch .failed $MAKE $JOBS || touch .failed $MAKE install DESTDIR=$DESTDIR || touch .failed @@ -413,15 +413,15 @@ build_GMP() { # Now set CFLAGS to match GMP CFLAGS but strip out -pedantic # as GCC 4.6.x fails if it's there. - export HOSTCFLAGS=$(grep __GMP_CFLAGS $DESTDIR$TARGETDIR/include/gmp.h |cut -d\" -f2 |\ + export HOSTCFLAGS=$(grep __GMP_CFLAGS $DESTDIR$HOSTDIR/include/gmp.h |cut -d\" -f2 |\ sed s,-pedantic,,) } build_MPFR() { test $UNAME = "Darwin" && CFLAGS="$CFLAGS -force_cpusubtype_ALL" - CC="$CC" ../${MPFR_DIR}/configure --disable-shared --prefix=$TARGETDIR \ - --infodir=$TARGETDIR/info \ - --with-gmp=$DESTDIR$TARGETDIR CFLAGS="$HOSTCFLAGS" || \ + CC="$CC" ../${MPFR_DIR}/configure --disable-shared --prefix=$HOSTDIR \ + --infodir=$HOSTDIR/info \ + --with-gmp=$DESTDIR$HOSTDIR CFLAGS="$HOSTCFLAGS" || \ touch .failed $MAKE $JOBS || touch .failed $MAKE install DESTDIR=$DESTDIR || touch .failed @@ -430,14 +430,14 @@ build_MPFR() { # work around build problem of libgmp.la if [ "$DESTDIR" != "" ]; then - perl -pi -e "s,$DESTDIR,," $DESTDIR$TARGETDIR/libgmp.la + perl -pi -e "s,$DESTDIR,," $DESTDIR$HOSTDIR/libgmp.la fi } build_MPC() { - CC="$CC" ../${MPC_DIR}/configure --disable-shared --prefix=$TARGETDIR \ - --infodir=$TARGETDIR/info --with-mpfr=$DESTDIR$TARGETDIR \ - --with-gmp=$DESTDIR$TARGETDIR CFLAGS="$HOSTCFLAGS" || \ + CC="$CC" ../${MPC_DIR}/configure --disable-shared --prefix=$HOSTDIR \ + --infodir=$HOSTDIR/info --with-mpfr=$DESTDIR$HOSTDIR \ + --with-gmp=$DESTDIR$HOSTDIR CFLAGS="$HOSTCFLAGS" || \ touch .failed $MAKE $JOBS || touch .failed $MAKE install DESTDIR=$DESTDIR || touch .failed @@ -447,10 +447,10 @@ build_MPC() { build_LIBELF() { CC="$CC" CFLAGS="$HOSTCFLAGS" libelf_cv_elf_h_works=no \ - ../${LIBELF_DIR}/configure --disable-shared --prefix=$TARGETDIR \ - --infodir=$TARGETDIR/info CFLAGS="$HOSTCFLAGS" || touch .failed + ../${LIBELF_DIR}/configure --disable-shared --prefix=$HOSTDIR \ + --infodir=$HOSTDIR/info CFLAGS="$HOSTCFLAGS" || touch .failed $MAKE $JOBS || touch .failed - $MAKE install prefix=$DESTDIR$TARGETDIR || touch .failed + $MAKE install prefix=$DESTDIR$HOSTDIR || touch .failed normalize_dirs } @@ -482,8 +482,8 @@ build_GCC() { --disable-libssp --disable-bootstrap --disable-nls \ --disable-libquadmath --without-headers \ ${GCC_OPTIONS} --enable-languages="${LANGUAGES}" \ - --with-gmp=$DESTDIR$TARGETDIR --with-mpfr=$DESTDIR$TARGETDIR \ - --with-mpc=$DESTDIR$TARGETDIR --with-libelf=$DESTDIR$TARGETDIR \ + --with-gmp=$DESTDIR$HOSTDIR --with-mpfr=$DESTDIR$HOSTDIR \ + --with-mpc=$DESTDIR$HOSTDIR --with-libelf=$DESTDIR$HOSTDIR \ --with-pkgversion="coreboot toolchain v$CROSSGCC_VERSION $CROSSGCC_DATE" \ || touch .failed $MAKE $JOBS CFLAGS_FOR_BUILD="$HOSTCFLAGS" all-gcc || touch .failed @@ -497,7 +497,7 @@ build_GCC() { build_EXPAT() { CC="$CC" CFLAGS="$HOSTCFLAGS" ../${EXPAT_DIR}/configure --disable-shared \ - --prefix=$TARGETDIR --target=${TARGETARCH} || touch .failed + --prefix=$HOSTDIR --target=${TARGETARCH} || touch .failed $MAKE || touch .failed $MAKE install DESTDIR=$DESTDIR || touch .failed @@ -505,7 +505,7 @@ build_EXPAT() { } build_PYTHON() { - CC="$CC" CFLAGS="$HOSTCFLAGS" ../${PYTHON_DIR}/configure --prefix=$TARGETDIR \ + CC="$CC" CFLAGS="$HOSTCFLAGS" ../${PYTHON_DIR}/configure --prefix=$HOSTDIR \ --target=${TARGETARCH} || touch .failed $MAKE $JOBS || touch .failed $MAKE install DESTDIR=$DESTDIR || touch .failed @@ -514,14 +514,14 @@ build_PYTHON() { } build_GDB() { - export PYTHONHOME=$DESTDIR$TARGETDIR + export PYTHONHOME=$DESTDIR$HOSTDIR if [ $(uname) != "FreeBSD" -a $(uname) != "NetBSD" ]; then LIBDL="-ldl" fi - LDFLAGS="-Wl,-rpath,\$\$ORIGIN/../lib/ -L$DESTDIR$TARGETDIR/lib \ + LDFLAGS="-Wl,-rpath,\$\$ORIGIN/../lib/ -L$DESTDIR$HOSTDIR/lib \ -lpthread $LIBDL -lutil" \ - CC="$CC" CFLAGS="$HOSTCFLAGS -I$DESTDIR$TARGETDIR/include" \ - ../${GDB_DIR}/configure --prefix=$TARGETDIR \ + CC="$CC" CFLAGS="$HOSTCFLAGS -I$DESTDIR$HOSTDIR/include" \ + ../${GDB_DIR}/configure --prefix=$HOSTDIR \ --target=${TARGETARCH} --disable-werror --disable-nls $MAKE $JOBS || touch .failed $MAKE install DESTDIR=$DESTDIR || touch .failed @@ -536,8 +536,8 @@ build_IASL() { test $UNAME = "FreeBSD" && HOST="_FreeBSD" test $UNAME = "Cygwin" && HOST="_CYGWIN" HOST="$HOST" OPT_CFLAGS="-O -D_FORTIFY_SOURCE=2 -D COREBOOT_TOOLCHAIN_VERSION='\"coreboot toolchain v$CROSSGCC_VERSION $CROSSGCC_DATE\"' " CFLAGS="$CFLAGS" $MAKE CC="$CC" iasl || touch $RDIR/.failed - rm -f $DESTDIR$TARGETDIR/bin/iasl || touch $RDIR/.failed - cp bin/iasl $DESTDIR$TARGETDIR/bin || touch $RDIR/.failed + rm -f $DESTDIR$HOSTDIR/bin/iasl || touch $RDIR/.failed + cp bin/iasl $DESTDIR$HOSTDIR/bin || touch $RDIR/.failed } build_LLVM() { @@ -656,13 +656,13 @@ case "$PACKAGE" in GCC|gcc) echo "Target architecture is now $TARGETARCH" NAME="${TARGETARCH} cross GCC" - PACKAGES="GMP MPFR MPC LIBELF BINUTILS GCC" + PACKAGES="host-GMP host-MPFR host-MPC host-LIBELF BINUTILS GCC" ;; GDB|gdb) NAME="${TARGETARCH} cross GDB" PACKAGES="GDB" if [ $SKIPPYTHON -eq 0 ]; then - PACKAGES="EXPAT PYTHON $PACKAGES" + PACKAGES="host-EXPAT host-PYTHON $PACKAGES" fi ;; CLANG|clang) @@ -672,7 +672,7 @@ case "$PACKAGE" in ;; IASL|iasl) NAME="IASL ACPI compiler" - PACKAGES=IASL + PACKAGES="host-IASL" ;; *) printf "${red}ERROR: Unsupported package $PACKAGE. (Supported packages are GCC, GDB, CLANG, IASL)${NC}\n\n";

1 0

New patch to review for coreboot: board_status/getrevision.sh: get rid of colons in dir names
by Martin Roth 27 Jan '16

27 Jan '16

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13490 -gerrit commit 3c6a1b6194f1af397363d2ab871b4b5c7b449aae Author: Martin Roth <martinroth(a)google.com> Date: Wed Jan 27 09:53:45 2016 -0700 board_status/getrevision.sh: get rid of colons in dir names Gnu make won't build in directories that have a colon in their name. As far as I can tell without extensive debug, this has to do with make's variable expansion. When we try to expand the directory name of a file in the tree, the colon turns the directory into a target. I've started including scripts into the board-status directories to do the build of the rom that was tested, and this is preventing them from working without renaming the directory before doing the build. Change-Id: I9dd8e4027be21363015cd8df9918610e206afce2 Signed-off-by: Martin Roth <martinroth(a)google.com> --- util/board_status/getrevision.sh | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/util/board_status/getrevision.sh b/util/board_status/getrevision.sh index 6559df3..168c972 100755 --- a/util/board_status/getrevision.sh +++ b/util/board_status/getrevision.sh @@ -96,7 +96,10 @@ timestamp() { if [ -z "$t" ]; then echo "Warning: Could not determine timestamp." 2>/dev/null fi - echo "${t}" + + # output the time, changing colons to underscores. + # gnu make doesn't work in directories with colons + echo "${t}" | tr ':' '_' } # Retrieve local SCM revision info. This is useful if we're working in a different SCM than upstream and/or

1 0

Patch set updated for coreboot: src: Fix various spelling and whitespace issues.
by Martin Roth 27 Jan '16

27 Jan '16

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13016 -gerrit commit 9cc8d5848ae8a56b03fbf7f64d8a96f352864d8c Author: Martin Roth <martinroth(a)google.com> Date: Fri Jan 15 10:20:11 2016 -0700 src: Fix various spelling and whitespace issues. This fixes some spelling and whitespace issues that I came across while working on various things in the tree. There are no functional changes. Change-Id: I33bc77282f2f94a1fc5f1bc713e44f72db20c1ab Signed-off-by: Martin Roth <martinroth(a)google.com> --- src/cpu/x86/mtrr/mtrr.c | 4 +-- src/mainboard/amd/dinar/gpio.c | 2 +- src/mainboard/amd/torpedo/gpio.c | 2 +- src/northbridge/amd/amdk8/raminit_f.c | 54 ++++++++++++++-------------- src/northbridge/amd/amdk8/raminit_f_dqs.c | 14 ++++---- src/northbridge/amd/amdmct/mct_ddr3/mwlc_d.h | 16 ++++----- 6 files changed, 46 insertions(+), 46 deletions(-) diff --git a/src/cpu/x86/mtrr/mtrr.c b/src/cpu/x86/mtrr/mtrr.c index ed5613c..efd0b68 100644 --- a/src/cpu/x86/mtrr/mtrr.c +++ b/src/cpu/x86/mtrr/mtrr.c @@ -92,7 +92,7 @@ static void enable_var_mtrr(unsigned char deftype) wrmsr(MTRR_DEF_TYPE_MSR, msr); } -/* fms: find most sigificant bit set, stolen from Linux Kernel Source. */ +/* fms: find most significant bit set, stolen from Linux Kernel Source. */ static inline unsigned int fms(unsigned int x) { int r; @@ -209,7 +209,7 @@ static struct memranges *get_physical_address_space(void) filter_vga_wrcomb); /* The address space below 4GiB is special. It needs to be - * covered entirly by range entries so that MTRR calculations + * covered entirely by range entries so that MTRR calculations * can be properly done for the full 32-bit address space. * Therefore, ensure holes are filled up to 4GiB as * uncacheable */ diff --git a/src/mainboard/amd/dinar/gpio.c b/src/mainboard/amd/dinar/gpio.c index 6cd85e3..17097b3 100644 --- a/src/mainboard/amd/dinar/gpio.c +++ b/src/mainboard/amd/dinar/gpio.c @@ -90,7 +90,7 @@ gpioEarlyInit( for (Index = 0; Index < MAX_GPIO_NO; Index++) { if (!(((Index >= GPIO_RSVD_ZONE0_S) && (Index <= GPIO_RSVD_ZONE0_E)) || ((Index >= GPIO_RSVD_ZONE1_S) && (Index <= GPIO_RSVD_ZONE1_E)))) { if ((StripInfo >= boardRevC) || ((Index != GPIO_111) && (Index != GPIO_113))) { - // Configure multi-funtion + // Configure multi-function Mmio8_And_Or (IoMuxMmioAddr, Index, 0x00, (gpio_table[Index].select & ~NonGpio)); } // Configure GPIO diff --git a/src/mainboard/amd/torpedo/gpio.c b/src/mainboard/amd/torpedo/gpio.c index 0078769..b9fe745 100644 --- a/src/mainboard/amd/torpedo/gpio.c +++ b/src/mainboard/amd/torpedo/gpio.c @@ -88,7 +88,7 @@ gpioEarlyInit( for (Index = 0; Index < MAX_GPIO_NO; Index++) { if (!(((Index >= GPIO_RSVD_ZONE0_S) && (Index <= GPIO_RSVD_ZONE0_E)) || ((Index >= GPIO_RSVD_ZONE1_S) && (Index <= GPIO_RSVD_ZONE1_E)))) { if ((StripInfo >= boardRevC) || ((Index != GPIO_111) && (Index != GPIO_113))) { - // Configure multi-funtion + // Configure multi-function Mmio8_And_Or (IoMuxMmioAddr, Index, 0x00, (gpio_table[Index].select & ~NonGpio)); } // Configure GPIO diff --git a/src/northbridge/amd/amdk8/raminit_f.c b/src/northbridge/amd/amdk8/raminit_f.c index f258cca..cd4b9fb 100644 --- a/src/northbridge/amd/amdk8/raminit_f.c +++ b/src/northbridge/amd/amdk8/raminit_f.c @@ -64,7 +64,7 @@ index: Write: - Write the data to DctOffsetData - Write register num to DctOffset with DctAccessWrite = 1 - - poll the DctAccessDone untio it = 1 + - poll the DctAccessDone until it = 1 */ @@ -153,7 +153,7 @@ static void sdram_set_registers(const struct mem_controller *ctrl, struct sys_in * 100 = reserved * 101 = reserved * 110 = reserved - * 111 = Interleve on A[12] and A[13] and A[14] (8 nodes) + * 111 = Interleave on A[12] and A[13] and A[14] (8 nodes) * [15:11] Reserved * [13:16] DRAM Base Address i Bits 39-24 * This field defines the upper address bits of a 40-bit address @@ -232,7 +232,7 @@ static void sdram_set_registers(const struct mem_controller *ctrl, struct sys_in * 100 = 2.5 Memory Clocks * 101 = 3 Memory Clocks * 110 = 3.5 Memory Clocks - * 111 = Reseved + * 111 = Reserved * [15: 7] Reserved * [16:16] AltVidC3MemClkTriEn (AltVID Memory Clock Tristate Enable) * Enables the DDR memory clocks to be tristated when alternate VID @@ -244,19 +244,19 @@ static void sdram_set_registers(const struct mem_controller *ctrl, struct sys_in * [18:18] DqsRcvEnTrain (DQS Receiver Enable Training Mode) * 0 = Normal DQS Receiver enable operation * 1 = DQS receiver enable training mode - * [31:19] reverved + * [31:19] reserved */ PCI_ADDR(0, 0x18, 2, 0x78), 0xfff80000, (6<<4)|(6<<0), /* DRAM Initialization Register * F2:0x7C * [15: 0] MrsAddress (Address for MRS/EMRS Commands) - * this field specifies the dsata driven on the DRAM address pins + * this field specifies the data driven on the DRAM address pins * 15-0 for MRS and EMRS commands * [18:16] MrsBank (Bank Address for MRS/EMRS Commands) * this files specifies the data driven on the DRAM bank pins for * the MRS and EMRS commands - * [23:19] reverved + * [23:19] reserved * [24:24] SendPchgAll (Send Precharge All Command) * Setting this bit causes the DRAM controller to send a precharge * all command. This bit is cleared by the hardware after the @@ -268,7 +268,7 @@ static void sdram_set_registers(const struct mem_controller *ctrl, struct sys_in * [26:26] SendMrsCmd (Send MRS/EMRS Command) * Setting this bit causes the DRAM controller to send the MRS or * EMRS command defined by the MrsAddress and MrsBank fields. This - * bit is cleared by the hardware adter the commmand completes + * bit is cleared by the hardware after the command completes * [27:27] DeassertMemRstX (De-assert Memory Reset) * Setting this bit causes the DRAM controller to de-assert the * memory reset pin. This bit cannot be used to assert the memory @@ -276,7 +276,7 @@ static void sdram_set_registers(const struct mem_controller *ctrl, struct sys_in * [28:28] AssertCke (Assert CKE) * setting this bit causes the DRAM controller to assert the CKE * pins. This bit cannot be used to de-assert the CKE pins - * [30:29] reverved + * [30:29] reserved * [31:31] EnDramInit (Enable DRAM Initialization) * Setting this bit puts the DRAM controller in a BIOS controlled * DRAM initialization mode. BIOS must clear this bit aster DRAM @@ -388,7 +388,7 @@ static void sdram_set_registers(const struct mem_controller *ctrl, struct sys_in * 111 = 9 bus clocks * [ 7: 7] Reserved * [ 9: 8] Twtr (Internal DRAM Write-to-Read Command Delay, - * minium write-to-read delay when both access the same chip select) + * Minimum write-to-read delay when both access the same chip select) * 00 = Reserved * 01 = 1 bus clocks * 10 = 2 bus clocks @@ -408,7 +408,7 @@ static void sdram_set_registers(const struct mem_controller *ctrl, struct sys_in * 00 = 2 bus clocks ( 1 idle cycle on the bus) * 01 = 3 bus clocks ( 2 idle cycles on the bus) * 10 = 4 bus clocks ( 3 idle cycles on the bus) - * 11 = 5 bus clocks ( 4 idel cycles on the bus) + * 11 = 5 bus clocks ( 4 idle cycles on the bus) * [17:16] Tref (Refresh Rate) * 00 = Undefined behavior * 01 = Reserved @@ -487,7 +487,7 @@ static void sdram_set_registers(const struct mem_controller *ctrl, struct sys_in * 010 = 333MHz * 011 = reserved * 1xx = reserved - * [ 3: 3] MemClkFreqVal (Memory Clock Freqency Valid) + * [ 3: 3] MemClkFreqVal (Memory Clock Frequency Valid) * 1 = BIOS need to set the bit when setting up MemClkFreq to * the proper value * [ 7: 4] MaxAsyncLat ( Maximum Asynchronous Latency) @@ -523,7 +523,7 @@ static void sdram_set_registers(const struct mem_controller *ctrl, struct sys_in * MEMCLK cycle * 1 = One additional MEMCLK of setup time is provided on all * DRAM address and control signals except CS, CKE, and ODT; - * i.e., these signals are drivern for two MEMCLK cycles + * i.e., these signals are driven for two MEMCLK cycles * rather than one * [21:21] Reserved * [22:22] BankSwizzleMode ( Bank Swizzle Mode), @@ -565,7 +565,7 @@ static void sdram_set_registers(const struct mem_controller *ctrl, struct sys_in * 1 When bit enables support for mismatched DIMMs when using * 128-bit DRAM interface, the Width128 no effect, only for * AM2 and s1g1 - * [ 5: 5] DCC_EN ( Dynamica Idle Cycle Counter Enable) + * [ 5: 5] DCC_EN ( Dynamic Idle Cycle Counter Enable) * When set to 1, indicates that each entry in the page tables * dynamically adjusts the idle cycle limit based on page * Conflict/Page Miss (PC/PM) traffic @@ -581,7 +581,7 @@ static void sdram_set_registers(const struct mem_controller *ctrl, struct sys_in * [ 9: 9] DramEnabled ( DRAM Enabled) * When Set, this bit indicates that the DRAM is enabled, this * bit is set by hardware after DRAM initialization or on an exit - * from self refresh. The DRAM controller is intialized after the + * from self refresh. The DRAM controller is initialized after the * hardware-controlled initialization process ( initiated by the * F2 0x90[DramInit]) completes or when the BIOS-controlled * initialization process completes (F2 0x7c(EnDramInit] is @@ -603,7 +603,7 @@ static void sdram_set_registers(const struct mem_controller *ctrl, struct sys_in /* DRAM Scrub Control Register * F3:0x58 - * [ 4: 0] DRAM Scrube Rate + * [ 4: 0] DRAM Scrub Rate * [ 7: 5] reserved * [12: 8] L2 Scrub Rate * [15:13] reserved @@ -646,7 +646,7 @@ static void sdram_set_registers(const struct mem_controller *ctrl, struct sys_in PCI_ADDR(0, 0x18, 3, 0x5C), 0x0000003e, 0x00000000, /* DRAM Scrub Address High Register * F3:0x60 - * [ 7: 0] DRAM Scrubb Address 39-32 + * [ 7: 0] DRAM Scrub Address 39-32 * [31: 8] Reserved */ PCI_ADDR(0, 0x18, 3, 0x60), 0xffffff00, 0x00000000, @@ -673,7 +673,7 @@ index: Write: - Write the data to DctOffsetData - Write register num to DctOffset with DctAccessWrite = 1 - - poll the DctAccessDone untio it = 1 + - poll the DctAccessDone until it = 1 */ int i; @@ -1161,7 +1161,7 @@ static unsigned long interleave_chip_selects(const struct mem_controller *ctrl, csbase_inc <<=1; } - /* Compute the initial values for csbase and csbask. + /* Compute the initial values for csbase and csmask. * In csbase just set the enable bit and the base to zero. * In csmask set the mask bits for the size and page level interleave. */ @@ -1196,7 +1196,7 @@ static unsigned long order_chip_selects(const struct mem_controller *ctrl) /* Remember which registers we have used in the high 8 bits of tom */ tom = 0; for (;;) { - /* Find the largest remaining canidate */ + /* Find the largest remaining candidate */ unsigned index, canidate; uint32_t csbase, csmask; unsigned size; @@ -1220,12 +1220,12 @@ static unsigned long order_chip_selects(const struct mem_controller *ctrl) if (tom & (1 << (index + 24))) { continue; } - /* I have a new canidate */ + /* I have a new candidate */ csbase = value; canidate = index; } - /* See if I have found a new canidate */ + /* See if I have found a new candidate */ if (csbase == 0) { break; } @@ -1352,7 +1352,7 @@ static long spd_handle_unbuffered_dimms(const struct mem_controller *ctrl, if (is_opteron(ctrl)) { #if 0 if ( registered != (meminfo->dimm_mask & ((1<<DIMM_SOCKETS)-1)) ) { - meminfo->dimm_mask &= (registered | (registered << DIMM_SOCKETS) ); //disable unbuffed dimm + meminfo->dimm_mask &= (registered | (registered << DIMM_SOCKETS) ); //disable unbuffered dimm // die("Mixed buffered and registered dimms not supported"); } //By yhlu for debug M2, s1g1 can do dual channel, but it use unbuffer DIMM @@ -1503,7 +1503,7 @@ static long spd_enable_2channels(const struct mem_controller *ctrl, struct mem_i printk(BIOS_SPEW, "Enabling dual channel memory\n"); dcl = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW); dcl &= ~DCL_BurstLength32; /* 32byte mode may be preferred in platforms that include graphics controllers that generate a lot of 32-bytes system memory accesses - 32byte mode is not supported when the DRAM interface is 128 bits wides, even 32byte mode is set, system still use 64 byte mode */ + 32byte mode is not supported when the DRAM interface is 128 bits wide, even 32byte mode is set, system still use 64 byte mode */ dcl |= DCL_Width128; pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW, dcl); meminfo->is_Width128 = 1; @@ -1720,8 +1720,8 @@ static int find_optimum_spd_latency(u32 spd_device, unsigned *min_latency, unsig /* Compute the lowest cas latency which can be expressed in this * particular SPD EEPROM. You can store at most settings for 3 * contiguous CAS latencies, so by taking the highest CAS - * latency maked as supported in the SPD and subtracting 2 you - * get the lowest expressable CAS latency. That latency is not + * latency marked as supported in the SPD and subtracting 2 you + * get the lowest expressible CAS latency. That latency is not * necessarily supported, but a (maybe invalid) entry exists * for it. */ @@ -2495,7 +2495,7 @@ static void set_max_async_latency(const struct mem_controller *ctrl, const struc dch = pci_read_config32(ctrl->f2, DRAM_CONFIG_HIGH); dch &= ~(DCH_MaxAsyncLat_MASK << DCH_MaxAsyncLat_SHIFT); - //FIXME: We need to use Max of DqsRcvEnDelay + 6ns here: After trainning and get that from index reg 0x10, 0x13, 0x16, 0x19, 0x30, 0x33, 0x36, 0x39 + //FIXME: We need to use Max of DqsRcvEnDelay + 6ns here: After training and get that from index reg 0x10, 0x13, 0x16, 0x19, 0x30, 0x33, 0x36, 0x39 async_lat = 6 + 6; @@ -2873,7 +2873,7 @@ static void sdram_set_spd_registers(const struct mem_controller *ctrl, if (meminfo->dimm_mask == -1) goto hw_spd_err; - //store memclk set to sysinfo, incase we need rebuilt param again + //store memclk set to sysinfo, in case we need rebuilt param again meminfo->memclk_set = param->dch_memclk; memcpy(&paramx, param, sizeof(paramx)); diff --git a/src/northbridge/amd/amdk8/raminit_f_dqs.c b/src/northbridge/amd/amdk8/raminit_f_dqs.c index 23ec60d..0b777d1 100644 --- a/src/northbridge/amd/amdk8/raminit_f_dqs.c +++ b/src/northbridge/amd/amdk8/raminit_f_dqs.c @@ -585,7 +585,7 @@ static unsigned TrainRcvrEn(const struct mem_controller *ctrl, unsigned Pass, st print_debug_dqs("\tTrainRcvEn51: channel ",channel, 1); /* for each rank */ - /* there are four recriver pairs, loosely associated with CS */ + /* there are four receiver pairs, loosely associated with CS */ for( receiver = 0; (receiver < 8) && (!Errors); receiver+=2) { @@ -664,14 +664,14 @@ static unsigned TrainRcvrEn(const struct mem_controller *ctrl, unsigned Pass, st /* FIXME: 64bit MUX */ if(is_Width128) { - /* Program current Receiver enable delay chaannel b */ + /* Program current Receiver enable delay channel b */ pci_write_config32_index_wait(ctrl->f2, 0x98, index+ 0x20, RcvrEnDly); } /* Program the MaxAsyncLat filed with the current DQS receiver enable setting plus 6ns */ - /*Porgram MaxAsyncLat to correspond with current delay */ + /* Program MaxAsyncLat to correspond with current delay */ SetMaxAL_RcvrDly(ctrl, RcvrEnDly); CurrTest = DQS_FAIL; @@ -688,7 +688,7 @@ static unsigned TrainRcvrEn(const struct mem_controller *ctrl, unsigned Pass, st if(Test0 == DQS_PASS) { Read1LTestPattern(TestAddr0B); - Test1 = CompareTestPatternQW0(channel, TestAddr0B, PatternB, TestPattern0, TestPattern1, TestPattern2, Pass, is_Width128); + Test1 = CompareTestPatternQW0(channel, TestAddr0B, PatternB, TestPattern0, TestPattern1, TestPattern2, Pass, is_Width128); proc_IOCLFLUSH(TestAddr0B); ResetDCTWrPtr(ctrl); @@ -755,7 +755,7 @@ static unsigned TrainRcvrEn(const struct mem_controller *ctrl, unsigned Pass, st } if(Pass == DQS_FIRST_PASS) { - // We need a better value for DQSPos trainning + // We need a better value for DQSPos training RcvrEnDly = RcvrEnDlyRmin /* + RCVREN_MARGIN * T1000/64/50 */; } else { RcvrEnDly = RcvrEnDlyRmin; @@ -1641,7 +1641,7 @@ static void set_var_mtrr_dqs( } -/* fms: find most sigificant bit set, stolen from Linux Kernel Source. */ +/* fms: find most significant bit set, stolen from Linux Kernel Source. */ static inline unsigned int fms(unsigned int x) { int r; @@ -1653,7 +1653,7 @@ static inline unsigned int fms(unsigned int x) return r; } -/* fls: find least sigificant bit set */ +/* fls: find least significant bit set */ static inline unsigned int fls(unsigned int x) { int r; diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mwlc_d.h b/src/northbridge/amd/amdmct/mct_ddr3/mwlc_d.h index 4de7af0..2bd39f9 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mwlc_d.h +++ b/src/northbridge/amd/amdmct/mct_ddr3/mwlc_d.h @@ -34,12 +34,12 @@ #define DCT_STATUS_LOAD_REDUCED 4 /* Load-Reduced DIMMs support */ #define DCT_STATUS_OnDimmMirror 24 /* OnDimmMirror support */ -/* PCI Defintions */ -#define FUN_HT 0 /* Funtion 0 Access */ -#define FUN_MAP 1 /* Funtion 1 Access */ -#define FUN_DCT 2 /* Funtion 2 Access */ -#define FUN_MISC 3 /* Funtion 3 Access */ -#define FUN_ADD_DCT 0xF /* Funtion 2 Additional Register Access */ +/* PCI Definitions */ +#define FUN_HT 0 /* Function 0 Access */ +#define FUN_MAP 1 /* Function 1 Access */ +#define FUN_DCT 2 /* Function 2 Access */ +#define FUN_MISC 3 /* Function 3 Access */ +#define FUN_ADD_DCT 0xF /* Function 2 Additional Register Access */ #define BOTH_DCTS 2 /* The access is independent of DCTs */ #define PCI_MIN_LOW 0 /* Lowest possible PCI register location */ #define PCI_MAX_HIGH 31 /* Highest possible PCI register location */ @@ -60,7 +60,7 @@ #define DRAM_CONT_ADD_ECC_PHASE_REC_CTRL 0x52 #define DRAM_CONT_ADD_WRITE_LEV_ERROR_REG 0x53 -/* CPU Register defintions */ +/* CPU Register definitions */ /* Register Bit Location */ #define DctAccessDone 31 @@ -155,7 +155,7 @@ typedef struct _sDCTStruct u8 ErrStatus[MAX_ERRORS]; /* Minor Error codes for DCT0 and 1 */ u8 DimmValid[MAX_TOTAL_DIMMS]; /* Indicates which DIMMs are valid for */ /* Total Number of DIMMs(per Node) */ - u8 WLTotalDelay[MAX_BYTE_LANES];/* Write Levelization Toral Delay */ + u8 WLTotalDelay[MAX_BYTE_LANES];/* Write Levelization Total Delay */ /* per byte lane */ u8 MaxDimmsInstalled; /* Max Dimms Installed for current DCT */ u8 DimmRanks[MAX_TOTAL_DIMMS]; /* Total Number of Ranks(per Dimm) */

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coreboot-gerrit January 2016