coreboot-gerrit January 2016

coreboot-gerrit@coreboot.org

1 participants
2471 discussions

Patch set updated for coreboot: util/cbfstool: add 'compact' command
by Aaron Durbin 27 Jan '16

27 Jan '16

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13479 -gerrit commit 4117a87c5787ff4586a4d65e5276f287afb45589 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue Jan 26 17:08:56 2016 -0600 util/cbfstool: add 'compact' command While assembling CBFS images within the RW slots on Chrome OS machines the current approach is to 'cbfstool copy' from the RO CBFS to each RW CBFS. Additional fixups are required such as removing unneeded files from the RW CBFS (e.g. verstage) as well as removing and adding back files with the proper arguments (FSP relocation as well as romstage XIP relocation). This ends up leaving holes in the RW CBFS. To speed up RW CBFS slot hashing it's beneficial to pack all non-empty files together at the beginning of the CBFS. Therefore, provide the 'compact' command which bubbles all the empty entries to the end of the CBFS. Change-Id: I8311172d71a2ccfccab384f8286cf9f21a17dec9 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- util/cbfstool/cbfs_image.c | 121 +++++++++++++++++++++++++++++++++++++++++++++ util/cbfstool/cbfs_image.h | 4 ++ util/cbfstool/cbfstool.c | 13 +++++ 3 files changed, 138 insertions(+) diff --git a/util/cbfstool/cbfs_image.c b/util/cbfstool/cbfs_image.c index b98df8a..0e0eabe 100644 --- a/util/cbfstool/cbfs_image.c +++ b/util/cbfstool/cbfs_image.c @@ -440,6 +440,127 @@ int cbfs_copy_instance(struct cbfs_image *image, struct buffer *dst) return 0; } +static size_t cbfs_file_entry_metadata_size(const struct cbfs_file *f) +{ + return ntohl(f->offset); +} + +static size_t cbfs_file_entry_data_size(const struct cbfs_file *f) +{ + return ntohl(f->len); +} + +static size_t cbfs_file_entry_size(const struct cbfs_file *f) +{ + return cbfs_file_entry_metadata_size(f) + cbfs_file_entry_data_size(f); +} + +int cbfs_compact_instance(struct cbfs_image *image) +{ + assert(image); + + struct cbfs_file *prev; + struct cbfs_file *cur; + + /* The prev entry will always be an empty entry. */ + prev = NULL; + + /* + * Note: this function does not honor alignment or fixed location files. + * It's behavior is akin to cbfs_copy_instance() in that it expects + * the caller to understand the ramifications of compacting a + * fragmented CBFS image. + */ + + for (cur = cbfs_find_first_entry(image); + cur && cbfs_is_valid_entry(image, cur); + cur = cbfs_find_next_entry(image, cur)) { + size_t prev_size; + size_t cur_size; + size_t empty_metadata_size; + size_t spill_size; + uint32_t type = htonl(cur->type); + + /* Current entry is empty. Kepp track of it. */ + if ((type == htonl(CBFS_COMPONENT_NULL)) || + (type == htonl(CBFS_COMPONENT_DELETED))) { + prev = cur; + continue; + } + + /* Need to ensure the previous entry is an empty one. */ + if (prev == NULL) + continue; + + /* At this point prev is an empty entry. Put the non-empty + * file in prev's location. Then add a new emptry entry. This + * essentialy bubbles empty entries towards the end. */ + + prev_size = cbfs_file_entry_size(prev); + cur_size = cbfs_file_entry_size(cur); + + /* + * Adjust the empty file size by the actual space occupied + * bewtween the beginning of the empty file and the non-empty + * file. + */ + prev_size += (cbfs_get_entry_addr(image, cur) - + cbfs_get_entry_addr(image, prev)) - prev_size; + + /* Move the non-empty file over the empty file. */ + memmove(prev, cur, cur_size); + + /* + * Get location of the empty file. Note that since prev was + * overwritten with the non-empty file the previously moved + * file needs to be used to calculate the empty file's location. + */ + cur = cbfs_find_next_entry(image, prev); + + /* + * The total space to work with for swapping the 2 entries + * consists of the 2 files' sizes combined. However, the + * cbfs_file entries start on CBFS_ALIGNMENT boundaries. + * Because of this the empty file size may end up smaller + * because of the non-empty file's metadata and data length. + * + * Calculate the spill size which is the amount of data lost + * due to the alignment constraints after moving the non-empty + * file. + */ + spill_size = (cbfs_get_entry_addr(image, cur) - + cbfs_get_entry_addr(image, prev)) - cur_size; + + empty_metadata_size = cbfs_calculate_file_header_size(""); + + /* Check if new empty size can contain the metadata. */ + if (empty_metadata_size + spill_size > prev_size) { + ERROR("Unable to swap '%s' with prev empty entry.\n", + prev->filename); + return 1; + } + + /* Update the empty file's size. */ + prev_size -= spill_size + empty_metadata_size; + + /* Create new empty file. */ + cbfs_create_empty_entry(cur, CBFS_COMPONENT_NULL, + prev_size, ""); + + /* Merge any potential empty entries together. */ + cbfs_walk(image, cbfs_merge_empty_entry, NULL); + + /* + * Since current switched to an empty file keep track of it. + * Even if any empty files were merged the empty entry still + * starts at previously calculated location. + */ + prev = cur; + } + + return 0; +} + int cbfs_image_delete(struct cbfs_image *image) { if (image == NULL) diff --git a/util/cbfstool/cbfs_image.h b/util/cbfstool/cbfs_image.h index 38510d2..0d7877a 100644 --- a/util/cbfstool/cbfs_image.h +++ b/util/cbfstool/cbfs_image.h @@ -76,6 +76,10 @@ int cbfs_image_from_buffer(struct cbfs_image *out, struct buffer *in, * Will not succeed on new-style images without a master header. */ int cbfs_copy_instance(struct cbfs_image *image, struct buffer *dst); +/* Compact a fragmented CBFS image by placing all the non-empty files at the + * beginning of the image. Returns 0 on success, otherwise non-zero. */ +int cbfs_compact_instance(struct cbfs_image *image); + /* Releases the CBFS image. Returns 0 on success, otherwise non-zero. */ int cbfs_image_delete(struct cbfs_image *image); diff --git a/util/cbfstool/cbfstool.c b/util/cbfstool/cbfstool.c index 13a9956..5be2d65 100644 --- a/util/cbfstool/cbfstool.c +++ b/util/cbfstool/cbfstool.c @@ -1054,6 +1054,16 @@ static int cbfs_copy(void) return cbfs_copy_instance(&src_image, param.image_region); } +static int cbfs_compact(void) +{ + struct cbfs_image image; + if (cbfs_image_from_buffer(&image, param.image_region, + param.headeroffset)) + return 1; + WARN("Compacting a CBFS doesn't honor alignment or fixed addresses!\n"); + return cbfs_compact_instance(&image); +} + static const struct command commands[] = { {"add", "H:r:f:n:t:c:b:a:vA:gh?", cbfs_add, true, true}, {"add-flat-binary", "H:r:f:n:l:e:c:b:vA:gh?", cbfs_add_flat_binary, @@ -1064,6 +1074,7 @@ static const struct command commands[] = { true, true}, {"add-int", "H:r:i:n:b:vgh?", cbfs_add_integer, true, true}, {"add-master-header", "H:r:vh?", cbfs_add_master_header, true, true}, + {"compact", "r:h?", cbfs_compact, true, true}, {"copy", "r:R:h?", cbfs_copy, true, true}, {"create", "M:r:s:B:b:H:o:m:vh?", cbfs_create, true, true}, {"hashcbfs", "r:R:A:vh?", cbfs_hash, true, true}, @@ -1198,6 +1209,8 @@ static void usage(char *name) "Add a legacy CBFS master header\n" " remove [-r image,regions] -n NAME " "Remove a component\n" + " compact -r image,regions " + "Defragment CBFS image.\n" " copy -r image,regions -R source-region " "Create a copy (duplicate) cbfs instance in fmap\n" " create -m ARCH -s size [-b bootblock offset] \\\n"

1 0

Patch set updated for coreboot: util/cbfstool: add machine parseable print
by Aaron Durbin 27 Jan '16

27 Jan '16

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13475 -gerrit commit 3d9c30f5662bcaa65b8e20ae22046a069940637a Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue Jan 26 15:35:34 2016 -0600 util/cbfstool: add machine parseable print In order to more easily process the output of 'cbfstool print' with other tools provide a -k option which spits out the tab-separated header and fields: Name Offset Type Metadata Size Data Size Total Size ALIGN_UP(Offset + Total Size, 64) would be the start of the next entry. Also, one can analzye the overhead and offsets of each file more easily. Example output (note: tabs aren't in here): $ ./coreboot-builds/sharedutils/cbfstool/cbfstool test.serial.bin print -r FW_MAIN_A -k Performing operation on 'FW_MAIN_A' region... Name Offset Type Metadata Size Data Size Total Size cmos_layout.bin 0x0 cmos_layout 0x38 0x48c 0x4c4 dmic-2ch-48khz-16b.bin 0x500 raw 0x48 0xb68 0xbb0 dmic-2ch-48khz-32b.bin 0x10c0 raw 0x48 0xb68 0xbb0 nau88l25-2ch-48khz-24b.bin 0x1c80 raw 0x48 0x54 0x9c ssm4567-render-2ch-48khz-24b.bin 0x1d40 raw 0x58 0x54 0xac ssm4567-capture-4ch-48khz-32b.bin 0x1e00 raw 0x58 0x54 0xac vbt.bin 0x1ec0 optionrom 0x38 0x1000 0x1038 spd.bin 0x2f00 spd 0x38 0x600 0x638 config 0x3540 raw 0x38 0x1ab7 0x1aef revision 0x5040 raw 0x38 0x25e 0x296 font.bin 0x5300 raw 0x38 0x77f 0x7b7 vbgfx.bin 0x5ac0 raw 0x38 0x32f8 0x3330 locales 0x8e00 raw 0x28 0x2 0x2a locale_en.bin 0x8e40 raw 0x38 0x29f6 0x2a2e u-boot.dtb 0xb880 mrc_cache 0x38 0xff1 0x1029 (empty) 0xc8c0 null 0x64 0xadf4 0xae58 fallback/ramstage 0x17740 stage 0x38 0x15238 0x15270 (empty) 0x2c9c0 null 0x64 0xd2c4 0xd328 fallback/payload 0x39d00 payload 0x38 0x12245 0x1227d cpu_microcode_blob.bin 0x4bf80 microcode 0x60 0x17000 0x17060 (empty) 0x63000 null 0x28 0x37cf98 0x37cfc0 Change-Id: I1c5f8c1b5f2f980033d6c954c9840299c6268431 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- util/cbfstool/cbfs_image.c | 55 ++++++++++++++++++++++++++++++++++++++++++++++ util/cbfstool/cbfs_image.h | 1 + util/cbfstool/cbfstool.c | 13 ++++++++--- 3 files changed, 66 insertions(+), 3 deletions(-) diff --git a/util/cbfstool/cbfs_image.c b/util/cbfstool/cbfs_image.c index 2d7a6f0..b98df8a 100644 --- a/util/cbfstool/cbfs_image.c +++ b/util/cbfstool/cbfs_image.c @@ -1075,6 +1075,41 @@ int cbfs_print_entry_info(struct cbfs_image *image, struct cbfs_file *entry, return 0; } +static int cbfs_print_parseable_entry_info(struct cbfs_image *image, + struct cbfs_file *entry, void *arg) +{ + FILE *fp = (FILE *)arg; + const char *name; + const char *type; + size_t offset; + size_t metadata_size; + size_t data_size; + const char *sep = "\t"; + + if (!cbfs_is_valid_entry(image, entry)) { + ERROR("cbfs_print_entry_info: Invalid entry at 0x%x\n", + cbfs_get_entry_addr(image, entry)); + return -1; + } + + name = entry->filename; + if (*name == '\0') + name = "(empty)"; + type = get_cbfs_entry_type_name(ntohl(entry->type)), + metadata_size = ntohl(entry->offset); + data_size = ntohl(entry->len); + offset = cbfs_get_entry_addr(image, entry); + + fprintf(fp, "%s%s", name, sep); + fprintf(fp, "0x%zx%s", offset, sep); + fprintf(fp, "%s%s", type, sep); + fprintf(fp, "0x%zx%s", metadata_size, sep); + fprintf(fp, "0x%zx%s", data_size, sep); + fprintf(fp, "0x%zx\n", metadata_size + data_size); + + return 0; +} + int cbfs_print_directory(struct cbfs_image *image) { if (cbfs_is_legacy_cbfs(image)) @@ -1084,6 +1119,26 @@ int cbfs_print_directory(struct cbfs_image *image) return 0; } +int cbfs_print_parseable_directory(struct cbfs_image *image) +{ + int i; + const char *header[] = { + "Name", + "Offset", + "Type", + "Metadata Size", + "Data Size", + "Total Size", + }; + const char *sep = "\t"; + + for (i = 0; i < ARRAY_SIZE(header) - 1; i++) + fprintf(stdout, "%s%s", header[i], sep); + fprintf(stdout, "%s\n", header[i]); + cbfs_walk(image, cbfs_print_parseable_entry_info, stdout); + return 0; +} + int cbfs_merge_empty_entry(struct cbfs_image *image, struct cbfs_file *entry, unused void *arg) { diff --git a/util/cbfstool/cbfs_image.h b/util/cbfstool/cbfs_image.h index 00adcc8..38510d2 100644 --- a/util/cbfstool/cbfs_image.h +++ b/util/cbfstool/cbfs_image.h @@ -158,6 +158,7 @@ int cbfs_is_valid_entry(struct cbfs_image *image, struct cbfs_file *entry); /* Print CBFS component information. */ int cbfs_print_directory(struct cbfs_image *image); +int cbfs_print_parseable_directory(struct cbfs_image *image); int cbfs_print_header_info(struct cbfs_image *image); int cbfs_print_entry_info(struct cbfs_image *image, struct cbfs_file *entry, void *arg); diff --git a/util/cbfstool/cbfstool.c b/util/cbfstool/cbfstool.c index 23787d8..13a9956 100644 --- a/util/cbfstool/cbfstool.c +++ b/util/cbfstool/cbfstool.c @@ -75,6 +75,7 @@ static struct param { bool show_immutable; bool stage_xip; bool autogen_attr; + bool machine_parseable; int fit_empty_entries; enum comp_algo compression; enum vb2_hash_algorithm hash; @@ -838,8 +839,10 @@ static int cbfs_print(void) if (cbfs_image_from_buffer(&image, param.image_region, param.headeroffset)) return 1; - cbfs_print_directory(&image); - return 0; + if (param.machine_parseable) + return cbfs_print_parseable_directory(&image); + else + return cbfs_print_directory(&image); } /* Forward declared so there aren't type collisions with cbfstool proper @@ -1066,7 +1069,7 @@ static const struct command commands[] = { {"hashcbfs", "r:R:A:vh?", cbfs_hash, true, true}, {"extract", "H:r:m:n:f:vh?", cbfs_extract, true, false}, {"layout", "wvh?", cbfs_layout, false, false}, - {"print", "H:r:vh?", cbfs_print, true, false}, + {"print", "H:r:vkh?", cbfs_print, true, false}, {"read", "r:f:vh?", cbfs_read, true, false}, {"remove", "H:r:n:vh?", cbfs_remove, true, true}, {"update-fit", "H:r:n:x:vh?", cbfs_update_fit, true, true}, @@ -1105,6 +1108,7 @@ static struct option long_options[] = { {"with-readonly", no_argument, 0, 'w' }, {"xip", no_argument, 0, 'y' }, {"gen-attribute", no_argument, 0, 'g' }, + {"mach-parseable",no_argument, 0, 'k' }, {NULL, 0, 0, 0 } }; @@ -1407,6 +1411,9 @@ int main(int argc, char **argv) case 'g': param.autogen_attr = true; break; + case 'k': + param.machine_parseable = true; + break; case 'h': case '?': usage(argv[0]);

1 0

Patch set updated for coreboot: northbridge/intel/peg: Disable unused ports
by Patrick Rudolph 27 Jan '16

27 Jan '16

Patrick Rudolph (siro(a)das-labor.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12894 -gerrit commit 603affcc37cf88bedf842d89a5ad5ce3a7c40f4b Author: Patrick Rudolph <siro(a)das-labor.org> Date: Mon Dec 28 12:59:47 2015 +0100 northbridge/intel/peg: Disable unused ports Walk the bus and try to find enabled devices. Disable the PEG port if no devices are attached. Change-Id: I67fcc831fd78ecc6dba83f4e0662ec7549cc2591 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- src/northbridge/intel/gm45/northbridge.c | 14 ++++++++++++- src/northbridge/intel/sandybridge/northbridge.c | 26 ++++++++++++++++++++----- 2 files changed, 34 insertions(+), 6 deletions(-) diff --git a/src/northbridge/intel/gm45/northbridge.c b/src/northbridge/intel/gm45/northbridge.c index ce75aea..84df62d 100644 --- a/src/northbridge/intel/gm45/northbridge.c +++ b/src/northbridge/intel/gm45/northbridge.c @@ -243,6 +243,17 @@ static void enable_dev(device_t dev) } } +static u8 scan_bus_unused(struct bus *link) +{ + struct device *dev; + + for (dev = link->children; dev; dev = dev->sibling) { + if (dev->enabled) + return 0; + } + return 1; +} + static void gm45_init(void *const chip_info) { int dev, fn, bit_base; @@ -268,7 +279,8 @@ static void gm45_init(void *const chip_info) for (; fn >= 0; --fn) { const struct device *const d = dev_find_slot(0, PCI_DEVFN(dev, fn)); - if (!d || d->enabled) continue; + if (d && d->enabled && d->link_list && !scan_bus_unused(d->link_list)) + continue; const u32 deven = pci_read_config32(d0f0, D0F0_DEVEN); pci_write_config32(d0f0, D0F0_DEVEN, deven & ~(1 << (bit_base + fn))); diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c index 53d93a2..3974fe8 100644 --- a/src/northbridge/intel/sandybridge/northbridge.c +++ b/src/northbridge/intel/sandybridge/northbridge.c @@ -368,6 +368,17 @@ static void northbridge_dmi_init(struct device *dev) DMIBAR32(0x88) = reg32; } +static u8 scan_bus_unused(struct bus *link) +{ + struct device *dev; + + for (dev = link->children; dev; dev = dev->sibling) { + if (dev->enabled) + return 0; + } + return 1; +} + /* Disable unused PEG devices based on devicetree */ static void disable_peg(void) { @@ -378,27 +389,32 @@ static void disable_peg(void) reg = pci_read_config32(dev, DEVEN); dev = dev_find_slot(0, PCI_DEVFN(1, 2)); - if (!dev || !dev->enabled) { + if (!dev || !dev->enabled || + (dev->link_list && scan_bus_unused(dev->link_list))) { printk(BIOS_DEBUG, "Disabling PEG12.\n"); reg &= ~DEVEN_PEG12; } dev = dev_find_slot(0, PCI_DEVFN(1, 1)); - if (!dev || !dev->enabled) { + if (!dev || !dev->enabled || + (dev->link_list && scan_bus_unused(dev->link_list))) { printk(BIOS_DEBUG, "Disabling PEG11.\n"); reg &= ~DEVEN_PEG11; } dev = dev_find_slot(0, PCI_DEVFN(1, 0)); - if (!dev || !dev->enabled) { + if (!dev || !dev->enabled || + (dev->link_list && scan_bus_unused(dev->link_list))) { printk(BIOS_DEBUG, "Disabling PEG10.\n"); reg &= ~DEVEN_PEG10; } dev = dev_find_slot(0, PCI_DEVFN(2, 0)); - if (!dev || !dev->enabled) { + if (!dev || !dev->enabled || + (dev->link_list && scan_bus_unused(dev->link_list))) { printk(BIOS_DEBUG, "Disabling IGD.\n"); reg &= ~DEVEN_IGD; } dev = dev_find_slot(0, PCI_DEVFN(6, 0)); - if (!dev || !dev->enabled) { + if (!dev || !dev->enabled || + (dev->link_list && scan_bus_unused(dev->link_list))) { printk(BIOS_DEBUG, "Disabling PEG60.\n"); reg &= ~DEVEN_PEG60; }

1 0

New patch to review for coreboot: nb/intel/sandybridge/romstage: Read fuse bits for max MEM Clk
by Patrick Rudolph 27 Jan '16

27 Jan '16

Patrick Rudolph (siro(a)das-labor.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13487 -gerrit commit 65bedcf9b5efb47548bdf8c8c373fa207cfdd4e2 Author: Patrick Rudolph <siro(a)das-labor.org> Date: Tue Jan 26 20:02:14 2016 +0100 nb/intel/sandybridge/romstage: Read fuse bits for max MEM Clk Instead of hardcoding the maximum supported DDR frequency to 800Mhz (DDR3-1600), read the fuse bits that encode this information. Test system: * Intel IvyBridge * Gigabyte GA-B75M-D3H Change-Id: I515a2695a490f16aeb946bfaf3a1e860c607cba9 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- src/include/device/dram/ddr3.h | 4 ++- src/northbridge/intel/sandybridge/romstage.c | 46 +++++++++++++++++++--------- 2 files changed, 35 insertions(+), 15 deletions(-) diff --git a/src/include/device/dram/ddr3.h b/src/include/device/dram/ddr3.h index de75aee..525f497 100644 --- a/src/include/device/dram/ddr3.h +++ b/src/include/device/dram/ddr3.h @@ -33,8 +33,10 @@ * These values are in 1/256 ns units. * @{ */ +#define TCK_1333MHZ 192 +#define TCK_1200MHZ 212 #define TCK_1066MHZ 240 -#define TCK_933MHZ 275 +#define TCK_933MHZ 275 #define TCK_800MHZ 320 #define TCK_666MHZ 384 #define TCK_533MHZ 480 diff --git a/src/northbridge/intel/sandybridge/romstage.c b/src/northbridge/intel/sandybridge/romstage.c index 34d759f..d1fedc7 100644 --- a/src/northbridge/intel/sandybridge/romstage.c +++ b/src/northbridge/intel/sandybridge/romstage.c @@ -36,30 +36,48 @@ #define HOST_BRIDGE PCI_DEVFN(0, 0) #define DEFAULT_TCK TCK_800MHZ +#define CAPID0_B 0xe8 static unsigned int get_mem_min_tck(void) { + u32 reg32; const struct device *dev; const struct northbridge_intel_sandybridge_config *cfg; dev = dev_find_slot(0, HOST_BRIDGE); - if (!(dev && dev->chip_info)) - return DEFAULT_TCK; - - cfg = dev->chip_info; + cfg = NULL; + if (dev) + cfg = dev->chip_info; /* If this is zero, it just means devicetree.cb didn't set it */ - if (cfg->max_mem_clock_mhz == 0) + if (!cfg || cfg->max_mem_clock_mhz == 0) { + /* read Capabilities B Register DMFC bits */ + reg32 = pci_read_config32(PCI_DEV(0, 0, 0), CAPID0_B); + reg32 = (reg32 >> 4) & 0x7; + + switch (reg32) { + case 7: return TCK_533MHZ; + case 6: return TCK_666MHZ; + case 5: return TCK_800MHZ; + case 4: return TCK_933MHZ; + case 3: return TCK_1066MHZ; + case 2: return TCK_1200MHZ; + case 1: return TCK_1333MHZ; + /* reserved: */ + default: + break; + } return DEFAULT_TCK; - - if (cfg->max_mem_clock_mhz >= 800) - return TCK_800MHZ; - else if (cfg->max_mem_clock_mhz >= 666) - return TCK_666MHZ; - else if (cfg->max_mem_clock_mhz >= 533) - return TCK_533MHZ; - else - return TCK_400MHZ; + } else { + if (cfg->max_mem_clock_mhz >= 800) + return TCK_800MHZ; + else if (cfg->max_mem_clock_mhz >= 666) + return TCK_666MHZ; + else if (cfg->max_mem_clock_mhz >= 533) + return TCK_533MHZ; + else + return TCK_400MHZ; + } } void main(unsigned long bist)

1 0

New patch to review for coreboot: nb/intel/sandybridge/raminit: Add XMP support
by Patrick Rudolph 27 Jan '16

27 Jan '16

Patrick Rudolph (siro(a)das-labor.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13486 -gerrit commit ac1a0bfa7700241385de98b1a82a8d07af1f5c32 Author: Patrick Rudolph <siro(a)das-labor.org> Date: Tue Jan 26 08:45:21 2016 +0100 nb/intel/sandybridge/raminit: Add XMP support Some vendors store lower frequency pofiles in the regular SPD, if the SPD contains a XMP profile. To make use of the board's and DIMM's maximum supported DRAM frequency, try to parse the XMP profile and use it instead. It's implemented as fallback allowing non XMP SPDs to work as usual. To reduce complexity only XMP Profile 1 is read. Allows my DRAM to run at 800Mhz instead of 666Mhz as encoded in the default SPD. Test system: * Gigabyte GA-B75M-D3H * Intel Pentium CPU G2130 Change-Id: Ib4dd68debfdcfdce138e813ad5b0e8e2ce3a40b2 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- src/device/dram/ddr3.c | 114 ++++++++++++++++++++++++++++ src/include/device/dram/ddr3.h | 10 +++ src/northbridge/intel/sandybridge/raminit.c | 17 ++++- 3 files changed, 140 insertions(+), 1 deletion(-) diff --git a/src/device/dram/ddr3.c b/src/device/dram/ddr3.c index fe9de2d..23e0d1e 100644 --- a/src/device/dram/ddr3.c +++ b/src/device/dram/ddr3.c @@ -116,6 +116,8 @@ int spd_decode_ddr3(dimm_attr * dimm, spd_raw_data spd) /* Don't assume we memset 0 dimm struct. Clear all our flags */ dimm->flags.raw = 0; + dimm->dimms_per_channel = 3; + /* Make sure that the SPD dump is indeed from a DDR3 module */ if (spd[2] != SPD_MEMORY_TYPE_SDRAM_DDR3) { printram("Not a DDR3 SPD!\n"); @@ -180,14 +182,17 @@ int spd_decode_ddr3(dimm_attr * dimm, spd_raw_data spd) printram(" Supported voltages:"); if (reg8 & (1 << 2)) { dimm->flags.operable_1_25V = 1; + dimm->voltage = 1250; printram(" 1.25V"); } if (reg8 & (1 << 1)) { dimm->flags.operable_1_35V = 1; + dimm->voltage = dimm->voltage < 1350 ? dimm->voltage : 1350; printram(" 1.35V"); } if (!(reg8 & (1 << 0))) { dimm->flags.operable_1_50V = 1; + dimm->voltage = dimm->voltage < 1500 ? dimm->voltage : 1500; printram(" 1.5V"); } printram("\n"); @@ -338,6 +343,115 @@ int spd_decode_ddr3(dimm_attr * dimm, spd_raw_data spd) return ret; } +/** + * \brief Decode the raw SPD XMP data + * + * Decodes a raw SPD XMP data from a DDR3 DIMM, and organizes it into a + * @ref dimm_attr structure. The SPD data must first be read in a contiguous + * array, and passed to this function. + * + * @param dimm pointer to @ref dimm_attr structure where the decoded data is to + * be stored + * @param spd array of raw data previously read from the SPD. + * + * @param profile select one of the profiles to load + * + * @return @ref spd_status enumerator + * SPD_STATUS_OK -- decoding was successful + * SPD_STATUS_INVALID -- invalid SPD or not a DDR3 SPD + * SPD_STATUS_CRC_ERROR -- CRC did not verify + * SPD_STATUS_INVALID_FIELD -- A field with an invalid value was + * detected. + */ +int spd_xmp_decode_ddr3(dimm_attr *dimm, spd_raw_data spd, enum ddr3_xmp_profile profile) +{ + int ret; + u32 mtb; /* medium time base */ + u8 *xmp; /* pointer to XMP profile data */ + + /* need a valid SPD */ + ret = spd_decode_ddr3(dimm, spd); + if (ret != SPD_STATUS_OK) + return ret; + + /* search for magic header */ + if (spd[176] != 0x0C || spd[177] != 0x4A) { + printram("Not a DDR3 XMP profile!\n"); + dimm->dram_type = SPD_MEMORY_TYPE_UNDEFINED; + return SPD_STATUS_INVALID; + } + + if (profile == DDR3_XMP_PROFILE_1) { + if (!(spd[178] & 1)) { + printram("Selected XMP profile disabled!\n"); + dimm->dram_type = SPD_MEMORY_TYPE_UNDEFINED; + return SPD_STATUS_INVALID; + } + printram(" XMP Profile 1\n"); + xmp = &spd[185]; + + /* Medium Timebase = + * Medium Timebase (MTB) Dividend / + * Medium Timebase (MTB) Divisor */ + mtb = (((u32) spd[180]) << 8) / spd[181]; + + dimm->dimms_per_channel = (spd[178] >> 2) & 0x3; + } else { + if (!(spd[178] & 2)) { + printram("Selected XMP profile disabled!\n"); + dimm->dram_type = SPD_MEMORY_TYPE_UNDEFINED; + return SPD_STATUS_INVALID; + } + printram(" XMP Profile 2\n"); + xmp = &spd[220]; + + /* Medium Timebase = + * Medium Timebase (MTB) Dividend / + * Medium Timebase (MTB) Divisor */ + mtb = (((u32) spd[182]) << 8) / spd[183]; + + dimm->dimms_per_channel = (spd[178] >> 4) & 0x3; + } + printram(" Max DIMMs per channel: %u\n", + dimm->dimms_per_channel + 1); + printram(" XMP Revision: %u.%u\n", spd[179] >> 4, spd[179] & 0xf); + + /* calculate voltage in mV */ + dimm->voltage = (xmp[0] & 1) * 50; + dimm->voltage += ((xmp[0] >> 1) & 0xf) * 100; + dimm->voltage += ((xmp[0] >> 5) & 0x3) * 1000; + printram(" Requested voltage: %u mV\n", dimm->voltage); + + /* SDRAM Minimum Cycle Time (tCKmin) */ + dimm->tCK = xmp[1] * mtb; + /* CAS Latencies Supported */ + dimm->cas_supported = (xmp[9] << 8) + xmp[8]; + /* Minimum CAS Latency Time (tAAmin) */ + dimm->tAA = xmp[2] * mtb; + /* Minimum Write Recovery Time (tWRmin) */ + dimm->tWR = xmp[8] * mtb; + /* Minimum RAS# to CAS# Delay Time (tRCDmin) */ + dimm->tRCD = xmp[7] * mtb; + /* Minimum Row Active to Row Active Delay Time (tRRDmin) */ + dimm->tRRD = xmp[17] * mtb; + /* Minimum Row Precharge Delay Time (tRPmin) */ + dimm->tRP = xmp[6] * mtb; + /* Minimum Active to Precharge Delay Time (tRASmin) */ + dimm->tRAS = (((xmp[9] & 0x0f) << 8) + xmp[10]) * mtb; + /* Minimum Active to Active/Refresh Delay Time (tRCmin) */ + dimm->tRC = (((xmp[9] & 0xf0) << 4) + xmp[11]) * mtb; + /* Minimum Refresh Recovery Delay Time (tRFCmin) */ + dimm->tRFC = ((xmp[15] << 8) + xmp[14]) * mtb; + /* Minimum Internal Write to Read Command Delay Time (tWTRmin) */ + dimm->tWTR = xmp[20] * mtb; + /* Minimum Internal Read to Precharge Command Delay Time (tRTPmin) */ + dimm->tRTP = xmp[16] * mtb; + /* Minimum Four Activate Window Delay Time (tFAWmin) */ + dimm->tFAW = (((xmp[18] & 0x0f) << 8) + xmp[19]) * mtb; + + return ret; +} + /* * The information printed below has a more informational character, and is not * necessarily tied in to RAM init debugging. Hence, we stop using printram(), diff --git a/src/include/device/dram/ddr3.h b/src/include/device/dram/ddr3.h index de75aee..cc47efb 100644 --- a/src/include/device/dram/ddr3.h +++ b/src/include/device/dram/ddr3.h @@ -161,6 +161,10 @@ typedef struct dimm_attr_st { u32 tFAW; u8 reference_card; + /* XMP: Module voltage in mV */ + u16 voltage; + /* XMP: max DIMMs per channel supported (1-4) */ + u8 dimms_per_channel; } dimm_attr; /** Result of the SPD decoding process */ @@ -171,12 +175,18 @@ enum spd_status { SPD_STATUS_INVALID_FIELD, }; +enum ddr3_xmp_profile { + DDR3_XMP_PROFILE_1 = 0, + DDR3_XMP_PROFILE_2 = 1, +}; + typedef u8 spd_raw_data[256]; u16 spd_ddr3_calc_crc(u8 *spd, int len); int spd_decode_ddr3(dimm_attr * dimm, spd_raw_data spd_data); int dimm_is_registered(enum spd_dimm_type type); void dram_print_spd_ddr3(const dimm_attr * dimm); +int spd_xmp_decode_ddr3(dimm_attr * dimm, spd_raw_data spd, enum ddr3_xmp_profile profile); /** * \brief Read double word from specified address diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c index 151a7ec..7bbe66a 100644 --- a/src/northbridge/intel/sandybridge/raminit.c +++ b/src/northbridge/intel/sandybridge/raminit.c @@ -281,7 +281,7 @@ void read_spd(spd_raw_data * spd, u8 addr) static void dram_find_spds_ddr3(spd_raw_data * spd, dimm_info * dimm, ramctr_timing * ctrl) { - int dimms = 0; + int dimms = 0, dimms_on_channel; int channel, slot, spd_slot; memset (ctrl->rankmap, 0, sizeof (ctrl->rankmap)); @@ -292,9 +292,24 @@ static void dram_find_spds_ddr3(spd_raw_data * spd, dimm_info * dimm, FOR_ALL_CHANNELS { ctrl->channel_size_mb[channel] = 0; + dimms_on_channel = 0; + /* count dimms on channel */ for (slot = 0; slot < NUM_SLOTS; slot++) { spd_slot = 2 * channel + slot; spd_decode_ddr3(&dimm->dimm[channel][slot], spd[spd_slot]); + if (dimm->dimm[channel][slot].dram_type == SPD_MEMORY_TYPE_SDRAM_DDR3) + dimms_on_channel++; + } + + for (slot = 0; slot < NUM_SLOTS; slot++) { + spd_slot = 2 * channel + slot; + /* search for XMP profile */ + spd_xmp_decode_ddr3(&dimm->dimm[channel][slot], spd[spd_slot], DDR3_XMP_PROFILE_1); + /* XMP limits the maximum number of DIMMs per channel */ + if ((dimm->dimm[channel][slot].dram_type != SPD_MEMORY_TYPE_SDRAM_DDR3) || + ((dimms_on_channel - 1) > dimm->dimm[channel][slot].dimms_per_channel)) { + spd_decode_ddr3(&dimm->dimm[channel][slot], spd[spd_slot]); + } if (dimm->dimm[channel][slot].dram_type != SPD_MEMORY_TYPE_SDRAM_DDR3) { // set dimm invalid dimm->dimm[channel][slot].ranks = 0;

1 0

Patch set updated for coreboot: drivers/lenovo: Add hybrid graphics driver
by Patrick Rudolph 27 Jan '16

27 Jan '16

Patrick Rudolph (siro(a)das-labor.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12896 -gerrit commit f7e3b8e8cc2661b17dda9f6404fe4f9472150213 Author: Patrick Rudolph <siro(a)das-labor.org> Date: Sat Dec 26 08:35:08 2015 +0100 drivers/lenovo: Add hybrid graphics driver Add a universal hybrid graphics driver compatible with all supported lenovo devices. Hybrid graphics allows to connect the display panel to either of one GPUs. As there are only two GPUs one GPIO needs to be toggled. In case the discrete GPU is activated the panel is routed to it. On deactivation the panel is routed to the integrated GPU and the discrete HDMI audio device is disabled too. The northbridge code won't disable the PEG port if the HDMI audio device is still visible. Tested on Lenovo T530 using Nvidia NVS 5400m. Depends on commit: "southbridge/intel: move gpio.c" Change-Id: I9b80b31a7749bdf893ed3b772a6505c9f29a56d1 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- src/drivers/lenovo/Kconfig | 12 +++ src/drivers/lenovo/Makefile.inc | 1 + src/drivers/lenovo/hybrid_graphics.c | 140 +++++++++++++++++++++++++++++++++++ src/mainboard/lenovo/t400/Kconfig | 1 + src/mainboard/lenovo/t420s/Kconfig | 1 + src/mainboard/lenovo/t430s/Kconfig | 1 + src/mainboard/lenovo/t520/Kconfig | 1 + src/mainboard/lenovo/t530/Kconfig | 1 + 8 files changed, 158 insertions(+) diff --git a/src/drivers/lenovo/Kconfig b/src/drivers/lenovo/Kconfig index f20f3b2..651ec80 100644 --- a/src/drivers/lenovo/Kconfig +++ b/src/drivers/lenovo/Kconfig @@ -27,3 +27,15 @@ config DIGITIZER_ABSENT endchoice endif + +config DRIVERS_LENOVO_HYBRID_GRAPHICS + bool + default n + +if DRIVERS_LENOVO_HYBRID_GRAPHICS + +config HYBRID_GRAPHICS_GPIO_NUM + int + default 52 + +endif diff --git a/src/drivers/lenovo/Makefile.inc b/src/drivers/lenovo/Makefile.inc index c50db5b..66f8594 100644 --- a/src/drivers/lenovo/Makefile.inc +++ b/src/drivers/lenovo/Makefile.inc @@ -1 +1,2 @@ ramstage-$(CONFIG_DRIVERS_LENOVO_WACOM) += wacom.c +ramstage-$(CONFIG_DRIVERS_LENOVO_HYBRID_GRAPHICS) += hybrid_graphics.c diff --git a/src/drivers/lenovo/hybrid_graphics.c b/src/drivers/lenovo/hybrid_graphics.c new file mode 100644 index 0000000..ada09df --- /dev/null +++ b/src/drivers/lenovo/hybrid_graphics.c @@ -0,0 +1,140 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Patrick Rudolph + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <types.h> +#include <string.h> +#include <device/device.h> +#include <device/pci_def.h> +#include <device/pci_ops.h> +#include <device/pci.h> +#include <console/console.h> +#include <southbridge/intel/common/gpio.h> + +#define VENDOR_ID_NVIDIA 0x10de +#define VENDOR_ID_AMD 0x1002 + +/* Hybrid graphics allows to connect LVDS interface to either iGPU + * or dGPU depending on GPIO level. + * On systems without dGPU this code is either not linked in or is never called + * and has no effect. + * + * Note: Once native gfx init is done for AMD or Nvida graphic + * cards merge this code. + */ + +static struct device *get_audio_dev(struct device *dev) +{ + /* returns the GPU HDMI audio device */ + if (dev->vendor == VENDOR_ID_NVIDIA) { + switch (dev->device) { + case 0x0def: + return dev_find_device(dev->vendor, 0x0bea, dev->bus->dev); + case 0x0dfc: + return dev_find_device(dev->vendor, 0x0bea, dev->bus->dev); + case 0x1056: + return dev_find_device(dev->vendor, 0x0e08, dev->bus->dev); + case 0x1057: + return dev_find_device(dev->vendor, 0x0bea, dev->bus->dev); + case 0x0a6c: + return dev_find_device(dev->vendor, 0x0be3, dev->bus->dev); + default: + break; + } + } else { + switch (dev->device) { + case 0x9591: + return dev_find_device(dev->vendor, 0xaa20, dev->bus->dev); + case 0x95c4: + return dev_find_device(dev->vendor, 0xaa28, dev->bus->dev); + default: + break; + } + } + return NULL; +} + +static void hybrid_graphics_enable_peg(struct device *dev) +{ + struct device *audio_dev; + + /* connect LVDS interface to dGPU */ + set_gpio(CONFIG_HYBRID_GRAPHICS_GPIO_NUM, GPIO_LEVEL_LOW); + printk(BIOS_DEBUG, "Switching panel to discrete GPU\n"); + dev->enabled = 1; + + audio_dev = get_audio_dev(dev); + if (audio_dev) + audio_dev->enabled = 1; +} + +static void hybrid_graphics_disable_peg(struct device *dev) +{ + struct device *audio_dev; + + /* connect LVDS interface to iGPU */ + set_gpio(CONFIG_HYBRID_GRAPHICS_GPIO_NUM, GPIO_LEVEL_HIGH); + printk(BIOS_DEBUG, "Switching panel to integrated GPU\n"); + printk(BIOS_DEBUG, "Disabling device 0x%04x:0x%04x on bus %s\n", + dev->vendor, dev->device, bus_path(dev->bus)); + dev->enabled = 0; + + audio_dev = get_audio_dev(dev); + if (audio_dev) { + printk(BIOS_DEBUG, "Disabling device 0x%04x:0x%04x on bus %s\n", + audio_dev->vendor, audio_dev->device, bus_path(audio_dev->bus)); + audio_dev->enabled = 0; + } +} + +static struct pci_operations pci_dev_ops_pci = { + .set_subsystem = pci_dev_set_subsystem, +}; + +struct device_operations hybrid_graphics_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = pci_dev_init, + .scan_bus = 0, + .enable = hybrid_graphics_enable_peg, + .disable = hybrid_graphics_disable_peg, + .ops_pci = &pci_dev_ops_pci, +}; + +static const unsigned short pci_device_ids_nvidia[] = { + 0x0def, /* NVidia NVS 5400m Lenovo T430/T530 */ + 0x0dfc, /* NVidia NVS 5200m Lenovo T430s */ + 0x1056, /* NVidia NVS 4200m Lenovo T420/T520 */ + 0x1057, /* NVidia NVS 4200m Lenovo T420/T520 */ + 0x0a6c, /* NVidia NVS 3100m Lenovo T410/T510 */ + 0 }; + +static const struct pci_driver hybrid_peg_nvidia __pci_driver = { + .ops = &hybrid_graphics_ops, + .vendor = VENDOR_ID_NVIDIA, + .devices = pci_device_ids_nvidia, +}; + +static const unsigned short pci_device_ids_amd[] = { + 0x9591, /* ATI Mobility Radeon HD 3650 Lenovo T500/W500 */ + 0x95c4, /* ATI Mobility Radeon HD 3470 Lenovo T400/R400 */ + 0 }; + +static const struct pci_driver hybrid_peg_amd __pci_driver = { + .ops = &hybrid_graphics_ops, + .vendor = VENDOR_ID_AMD, + .devices = pci_device_ids_amd, +}; + diff --git a/src/mainboard/lenovo/t400/Kconfig b/src/mainboard/lenovo/t400/Kconfig index 0eac311..59938bd 100644 --- a/src/mainboard/lenovo/t400/Kconfig +++ b/src/mainboard/lenovo/t400/Kconfig @@ -22,6 +22,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG select INTEL_INT15 select SUPERIO_NSC_PC87382 + select DRIVERS_LENOVO_HYBRID_GRAPHICS config MAINBOARD_DIR string diff --git a/src/mainboard/lenovo/t420s/Kconfig b/src/mainboard/lenovo/t420s/Kconfig index 65d37a7..d511a2b 100644 --- a/src/mainboard/lenovo/t420s/Kconfig +++ b/src/mainboard/lenovo/t420s/Kconfig @@ -21,6 +21,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG select SANDYBRIDGE_LVDS select MAINBOARD_HAS_LPC_TPM + select DRIVERS_LENOVO_HYBRID_GRAPHICS # Workaround for EC/KBC IRQ1. select SERIRQ_CONTINUOUS_MODE diff --git a/src/mainboard/lenovo/t430s/Kconfig b/src/mainboard/lenovo/t430s/Kconfig index 6e257dd..2ca71a4 100644 --- a/src/mainboard/lenovo/t430s/Kconfig +++ b/src/mainboard/lenovo/t430s/Kconfig @@ -22,6 +22,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select IVYBRIDGE_LVDS select ENABLE_VMX select MAINBOARD_HAS_LPC_TPM + select DRIVERS_LENOVO_HYBRID_GRAPHICS # Workaround for EC/KBC IRQ1. select SERIRQ_CONTINUOUS_MODE diff --git a/src/mainboard/lenovo/t520/Kconfig b/src/mainboard/lenovo/t520/Kconfig index df7c2db..4a7a6c2 100644 --- a/src/mainboard/lenovo/t520/Kconfig +++ b/src/mainboard/lenovo/t520/Kconfig @@ -21,6 +21,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG select SANDYBRIDGE_LVDS select MAINBOARD_HAS_LPC_TPM + select DRIVERS_LENOVO_HYBRID_GRAPHICS # Workaround for EC/KBC IRQ1. select SERIRQ_CONTINUOUS_MODE diff --git a/src/mainboard/lenovo/t530/Kconfig b/src/mainboard/lenovo/t530/Kconfig index 7b4ca7a..d947466 100644 --- a/src/mainboard/lenovo/t530/Kconfig +++ b/src/mainboard/lenovo/t530/Kconfig @@ -23,6 +23,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select MAINBOARD_DO_NATIVE_VGA_INIT # default to native vga init select ENABLE_VMX select MAINBOARD_HAS_LPC_TPM + select DRIVERS_LENOVO_HYBRID_GRAPHICS # Workaround for EC/KBC IRQ1. select SERIRQ_CONTINUOUS_MODE

1 0

Patch set updated for coreboot: nb/intel/sandybridge: Start PEG link training
by Patrick Rudolph 27 Jan '16

27 Jan '16

Patrick Rudolph (siro(a)das-labor.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/11917 -gerrit commit 235a55c2bcc38df41478a76d283352c86f15d9da Author: Patrick Rudolph <siro(a)das-labor.org> Date: Thu Oct 15 11:09:15 2015 +0200 nb/intel/sandybridge: Start PEG link training Issue observed: The PCIe Root port shows up in GNU/Linux but no PCIe device is being detected. Test system: * Gigabyte GA-B75M-D3H (Intel Pentium CPU G2130) * Lenovo T530 (Intel Core i5-3320M CPU) Problem description: The PEG Root port link training on Ivy Bridge needs to be manually started. Problem solution: The bits are set in early_init to meet PCIe reset timeout of 100msec. The bits should be set in PCI device enable function, but this causes the PCI enumeration to not detect the card, as it's still booting. Adding a fixed delay of 100msec resolves this problem, but this would increase boot time. Don't run the code on MRC path as it has its own PEG initilization code. Tested with: * Nvidia NVS 5400M (PCIe2) * ATI Radeon HD4780 (PCIe2) * Nvidia GeForce 8600 GT (PCIe1) Untested: * PCIe3 devices Final test results: The PEG device shows up under GNU/Linux and can be used without issues. Change-Id: Id8cfc43e5c4630b0ac217d98bb857c3308e6015b Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- src/northbridge/intel/sandybridge/early_init.c | 42 ++++++++++++++++++++++++++ 1 file changed, 42 insertions(+) diff --git a/src/northbridge/intel/sandybridge/early_init.c b/src/northbridge/intel/sandybridge/early_init.c index 81bf9d5..97a2cef 100644 --- a/src/northbridge/intel/sandybridge/early_init.c +++ b/src/northbridge/intel/sandybridge/early_init.c @@ -148,6 +148,39 @@ static void sandybridge_setup_graphics(void) MCHBAR32(0x5418) = reg32; } +/* PEG on IvyBridge+ needs a special startup sequence. + * As the MRC has its own initialization code skip it. + */ +static void start_peg_link_training(void) +{ +#ifdef CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE + u32 tmp; + u32 deven; + + deven = pci_read_config32(PCI_DEV(0, 0, 0), DEVEN); + + if (deven & DEVEN_PEG10) { + tmp = pci_read_config32(PCI_DEV(0, 1, 0), 0xC24) & ~(1 << 16); + pci_write_config32(PCI_DEV(0, 1, 0), 0xC24, tmp | (1 << 5)); + } + + if (deven & DEVEN_PEG11) { + tmp = pci_read_config32(PCI_DEV(0, 1, 1), 0xC24) & ~(1 << 16); + pci_write_config32(PCI_DEV(0, 1, 1), 0xC24, tmp | (1 << 5)); + } + + if (deven & DEVEN_PEG12) { + tmp = pci_read_config32(PCI_DEV(0, 1, 2), 0xC24) & ~(1 << 16); + pci_write_config32(PCI_DEV(0, 1, 2), 0xC24, tmp | (1 << 5)); + } + + if (deven & DEVEN_PEG60) { + tmp = pci_read_config32(PCI_DEV(0, 6, 0), 0xC24) & ~(1 << 16); + pci_write_config32(PCI_DEV(0, 6, 0), 0xC24, tmp | (1 << 5)); + } +#endif +} + void sandybridge_early_initialization(int chipset_type) { u32 capid0_a; @@ -177,6 +210,15 @@ void sandybridge_early_initialization(int chipset_type) pci_write_config32(PCI_DEV(0, 0, 0), DEVEN, deven); sandybridge_setup_graphics(); + + /* Write magic value to start PEG link training. + * This should be done in PCI device enumeration, but + * the PCIe specification requires to wait at least 100msec + * after reset for devices to come up. + * As we don't want to increase boot time, enable it early and + * assume the PEG is up as soon as PCI enumeration starts. + * TODO: use time stamps to ensure the timings are met */ + start_peg_link_training(); } void northbridge_romstage_finalize(int s3resume)

1 0

Patch set updated for coreboot: nb/intel/sandybridge/raminit: Fix two dimms per channel
by Patrick Rudolph 27 Jan '16

27 Jan '16

Patrick Rudolph (siro(a)das-labor.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13415 -gerrit commit 7b358d3cbaccc28150ae38cdf784f327f55e5612 Author: Patrick Rudolph <siro(a)das-labor.org> Date: Sun Jan 24 14:07:15 2016 +0100 nb/intel/sandybridge/raminit: Fix two dimms per channel Issue observed: The system boots with 4G in channel 0 and 4G in channel 1. The system doesn't boot with any combination of 4G + 1G in channel 0 and 4G in channel 1. In both cases DIMM1 failed, while DIMM0 showed no issues. Problem description: The CLK to CMD/CTL was off by a half clock cycle. The find the issue I X-Y plotted timC vs timB for every lane on the failing rank. You can see an offset by 32 units for timB, that is not present on other ranks. It turns out that the XOVER CMD/XOVER CTL enable bit for DIMM1 was missing in program_timings(), which caused the clock offset. Problem solution: Add two functions to calculate XOVER CMD and XOVER CTL and use both to set XOVER in program_timings() and dram_xover(). Final testing result: The system boots with 4G + 1G in channel 0 and 4G in channel 1. Test system: * Intel IvyBridge * Gigabyte GA-B75M-D3H Change-Id: I88694c86054ade77e9d8bb2f1fdaf7bc559c1218 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- src/northbridge/intel/sandybridge/raminit.c | 46 ++++++++++++++++++++--------- 1 file changed, 32 insertions(+), 14 deletions(-) diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c index 151a7ec..deb86ed 100644 --- a/src/northbridge/intel/sandybridge/raminit.c +++ b/src/northbridge/intel/sandybridge/raminit.c @@ -498,6 +498,28 @@ static u32 get_COMP2(u32 tCK) return frq_comp2_map[get_FRQ(tCK) - 3]; } +static u32 get_XOVER_CLK(u8 rankmap) +{ + return rankmap << 24; +} + +static u32 get_XOVER_CMD(u8 rankmap) +{ + u32 reg; + + // enable xover cmd + reg = 0x4000; + + // enable xover ctl + if (rankmap & 0x3) + reg |= 0x20000; + + if (rankmap & 0xc) + reg |= 0x4000000; + + return reg; +} + static void dram_timing(ramctr_timing * ctrl) { u8 val; @@ -699,20 +721,13 @@ static void dram_xover(ramctr_timing * ctrl) FOR_ALL_CHANNELS { // enable xover clk + reg = get_XOVER_CLK(ctrl->rankmap[channel]); printk(BIOS_DEBUG, "[%x] = %x\n", channel * 0x100 + 0xc14, - (ctrl->rankmap[channel] << 24)); - MCHBAR32(channel * 0x100 + 0xc14) = (ctrl->rankmap[channel] << 24); + reg); + MCHBAR32(channel * 0x100 + 0xc14) = reg; - // enable xover ctl - reg = 0; - if (ctrl->rankmap[channel] & 0x5) { - reg |= 0x20000; - } - if (ctrl->rankmap[channel] & 0xa) { - reg |= 0x4000000; - } - // enable xover cmd - reg |= 0x4000; + // enable xover ctl & xover cmd + reg = get_XOVER_CMD(ctrl->rankmap[channel]); printk(BIOS_DEBUG, "[%x] = %x\n", 0x100 * channel + 0x320c, reg); MCHBAR32(0x100 * channel + 0x320c) = reg; @@ -1493,14 +1508,16 @@ static void program_timings(ramctr_timing * ctrl, int channel) break; } - reg32 = (1 << 17) | (1 << 14); + /* enable CMD XOVER */ + reg32 = get_XOVER_CMD(ctrl->rankmap[channel]); reg32 |= ((slot320c[0] & 0x3f) << 6) | ((slot320c[0] & 0x40) << 9); reg32 |= (slot320c[1] & 0x7f) << 18; reg32 |= (full_shift & 0x3f) | ((full_shift & 0x40) << 6); MCHBAR32(0x320c + 0x100 * channel) = reg32; - reg_c14 = ctrl->rankmap[channel] << 24; + /* enable CLK XOVER */ + reg_c14 = get_XOVER_CLK(ctrl->rankmap[channel]); reg_c18 = 0; FOR_ALL_POPULATED_RANKS { @@ -1510,6 +1527,7 @@ static void program_timings(ramctr_timing * ctrl, int channel) if (shift < 0) shift = 0; offset_val_c14 = ctrl->reg_c14_offset + shift; + /* set CLK phase shift */ reg_c14 |= (offset_val_c14 & 0x3f) << (6 * slotrank); reg_c18 |= ((offset_val_c14 >> 6) & 1) << slotrank; }

1 0

Patch set updated for coreboot: nb/intel/sandybridge/raminit: Improve logging
by Patrick Rudolph 27 Jan '16

27 Jan '16

Patrick Rudolph (siro(a)das-labor.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13414 -gerrit commit 3cb3a5b51d91808001cb5982033a9784b43e4f66 Author: Patrick Rudolph <siro(a)das-labor.org> Date: Sun Jan 17 18:32:06 2016 +0100 nb/intel/sandybridge/raminit: Improve logging Use printram() in more places and use printk() only where it makes sense. Remove spamming "MRd: %x <= %x\n". Use common syntax for timing output. Change-Id: I38965967a029994112d7ab63afd4d9968a7728c5 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- src/northbridge/intel/sandybridge/raminit.c | 125 ++++++++++++++-------------- 1 file changed, 63 insertions(+), 62 deletions(-) diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c index 151a7ec..d3dfc23 100644 --- a/src/northbridge/intel/sandybridge/raminit.c +++ b/src/northbridge/intel/sandybridge/raminit.c @@ -312,7 +312,8 @@ static void dram_find_spds_ddr3(spd_raw_data * spd, dimm_info * dimm, ctrl->extended_temperature_range &= dimm->dimm[channel][slot].flags.ext_temp_refresh; ctrl->rankmap[channel] |= ((1 << dimm->dimm[channel][slot].ranks) - 1) << (2 * slot); - printk(BIOS_DEBUG, "rankmap[%d] = 0x%x\n", channel, ctrl->rankmap[channel]); + printk(BIOS_DEBUG, "channel[%d] rankmap = 0x%x\n", + channel, ctrl->rankmap[channel]); } if ((ctrl->rankmap[channel] & 3) && (ctrl->rankmap[channel] & 0xc) && dimm->dimm[channel][0].reference_card <= 5 && dimm->dimm[channel][1].reference_card <= 5) { @@ -699,7 +700,7 @@ static void dram_xover(ramctr_timing * ctrl) FOR_ALL_CHANNELS { // enable xover clk - printk(BIOS_DEBUG, "[%x] = %x\n", channel * 0x100 + 0xc14, + printram("XOVER CLK [%x] = %x\n", channel * 0x100 + 0xc14, (ctrl->rankmap[channel] << 24)); MCHBAR32(channel * 0x100 + 0xc14) = (ctrl->rankmap[channel] << 24); @@ -713,7 +714,7 @@ static void dram_xover(ramctr_timing * ctrl) } // enable xover cmd reg |= 0x4000; - printk(BIOS_DEBUG, "[%x] = %x\n", 0x100 * channel + 0x320c, + printram("XOVER CMD [%x] = %x\n", 0x100 * channel + 0x320c, reg); MCHBAR32(0x100 * channel + 0x320c) = reg; } @@ -733,8 +734,7 @@ static void dram_timing_regs(ramctr_timing * ctrl) reg |= (ctrl->CAS << 8); reg |= (ctrl->CWL << 12); reg |= (ctrl->tRAS << 16); - printk(BIOS_DEBUG, "[%x] = %x\n", 0x400 * channel + 0x4000, - reg); + printram("DBP [%x] = %x\n", 0x400 * channel + 0x4000, reg); MCHBAR32(0x400 * channel + 0x4000) = reg; // RAP @@ -746,8 +746,7 @@ static void dram_timing_regs(ramctr_timing * ctrl) reg |= (ctrl->tFAW << 16); reg |= (ctrl->tWR << 24); reg |= (3 << 30); - printk(BIOS_DEBUG, "[%x] = %x\n", 0x400 * channel + 0x4004, - reg); + printram("RAP [%x] = %x\n", 0x400 * channel + 0x4004, reg); MCHBAR32(0x400 * channel + 0x4004) = reg; // OTHP @@ -757,7 +756,7 @@ static void dram_timing_regs(ramctr_timing * ctrl) reg |= (ctrl->tXP << 5); reg |= (ctrl->tAONPD << 8); reg |= 0xa0000; - printk(BIOS_DEBUG, "[%x] = %x\n", addr, reg); + printram("OTHP [%x] = %x\n", addr, reg); MCHBAR32(addr) = reg; MCHBAR32(0x400 * channel + 0x4014) = 0; @@ -773,7 +772,7 @@ static void dram_timing_regs(ramctr_timing * ctrl) || (IS_SANDY_CPU(cpu) && IS_SANDY_CPU_D2(cpu))) { stretch = 2; addr = 0x400 * channel + 0x400c; - printk(BIOS_DEBUG, "[%x] = %x\n", + printram("ODT stretch [%x] = %x\n", 0x400 * channel + 0x400c, reg); reg = MCHBAR32(addr); @@ -786,7 +785,7 @@ static void dram_timing_regs(ramctr_timing * ctrl) // Rank 2 - operate on rank 0 reg = (reg & ~0x30000) | (stretch << 16); - printk(BIOS_DEBUG, "[%x] = %x\n", addr, reg); + printram("ODT stretch [%x] = %x\n", addr, reg); MCHBAR32(addr) = reg; } @@ -804,7 +803,7 @@ static void dram_timing_regs(ramctr_timing * ctrl) // Rank 2 - operate on rank 0 reg = (reg & ~0xc00) | (stretch << 10); - printk(BIOS_DEBUG, "[%x] = %x\n", addr, reg); + printram("ODT stretch [%x] = %x\n", addr, reg); MCHBAR32(addr) = reg; } } else { @@ -819,7 +818,7 @@ static void dram_timing_regs(ramctr_timing * ctrl) reg = (reg & ~0x1ff0000) | (val32 << 16); val32 = (u32) (ctrl->tREFI * 9) / 1024; reg = (reg & ~0xfe000000) | (val32 << 25); - printk(BIOS_DEBUG, "[%x] = %x\n", 0x400 * channel + 0x4298, + printram("REFI [%x] = %x\n", 0x400 * channel + 0x4298, reg); MCHBAR32(0x400 * channel + 0x4298) = reg; @@ -835,7 +834,7 @@ static void dram_timing_regs(ramctr_timing * ctrl) reg = (reg & ~0x3ff0000) | (val32 << 16); val32 = ctrl->tMOD - 8; reg = (reg & ~0xf0000000) | (val32 << 28); - printk(BIOS_DEBUG, "[%x] = %x\n", 0x400 * channel + 0x42a4, + printram("SRFTP [%x] = %x\n", 0x400 * channel + 0x42a4, reg); MCHBAR32(0x400 * channel + 0x42a4) = reg; } @@ -989,39 +988,40 @@ static void dram_memorymap(ramctr_timing * ctrl, int me_uma_size) } // Update memory map in pci-e configuration space + printk(BIOS_DEBUG, "Update PCI-E configuration space:\n"); // TOM (top of memory) reg = pcie_read_config32(PCI_DEV(0, 0, 0), 0xa0); val = tom & 0xfff; reg = (reg & ~0xfff00000) | (val << 20); - printk(BIOS_DEBUG, "PCI:[%x] = %x\n", 0xa0, reg); + printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", 0xa0, reg); pcie_write_config32(PCI_DEV(0, 0, 0), 0xa0, reg); reg = pcie_read_config32(PCI_DEV(0, 0, 0), 0xa4); val = tom & 0xfffff000; reg = (reg & ~0x000fffff) | (val >> 12); - printk(BIOS_DEBUG, "PCI:[%x] = %x\n", 0xa4, reg); + printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", 0xa4, reg); pcie_write_config32(PCI_DEV(0, 0, 0), 0xa4, reg); // TOLUD (top of low used dram) reg = pcie_read_config32(PCI_DEV(0, 0, 0), 0xbc); val = toludbase & 0xfff; reg = (reg & ~0xfff00000) | (val << 20); - printk(BIOS_DEBUG, "PCI:[%x] = %x\n", 0xbc, reg); + printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", 0xbc, reg); pcie_write_config32(PCI_DEV(0, 0, 0), 0xbc, reg); // TOUUD LSB (top of upper usable dram) reg = pcie_read_config32(PCI_DEV(0, 0, 0), 0xa8); val = touudbase & 0xfff; reg = (reg & ~0xfff00000) | (val << 20); - printk(BIOS_DEBUG, "PCI:[%x] = %x\n", 0xa8, reg); + printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", 0xa8, reg); pcie_write_config32(PCI_DEV(0, 0, 0), 0xa8, reg); // TOUUD MSB reg = pcie_read_config32(PCI_DEV(0, 0, 0), 0xac); val = touudbase & 0xfffff000; reg = (reg & ~0x000fffff) | (val >> 12); - printk(BIOS_DEBUG, "PCI:[%x] = %x\n", 0xac, reg); + printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", 0xac, reg); pcie_write_config32(PCI_DEV(0, 0, 0), 0xac, reg); if (reclaim) { @@ -1037,41 +1037,41 @@ static void dram_memorymap(ramctr_timing * ctrl, int me_uma_size) reg = pcie_read_config32(PCI_DEV(0, 0, 0), 0xb8); val = tsegbase & 0xfff; reg = (reg & ~0xfff00000) | (val << 20); - printk(BIOS_DEBUG, "PCI:[%x] = %x\n", 0xb8, reg); + printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", 0xb8, reg); pcie_write_config32(PCI_DEV(0, 0, 0), 0xb8, reg); // GFX stolen memory reg = pcie_read_config32(PCI_DEV(0, 0, 0), 0xb0); val = gfxstolenbase & 0xfff; reg = (reg & ~0xfff00000) | (val << 20); - printk(BIOS_DEBUG, "PCI:[%x] = %x\n", 0xb0, reg); + printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", 0xb0, reg); pcie_write_config32(PCI_DEV(0, 0, 0), 0xb0, reg); // GTT stolen memory reg = pcie_read_config32(PCI_DEV(0, 0, 0), 0xb4); val = gttbase & 0xfff; reg = (reg & ~0xfff00000) | (val << 20); - printk(BIOS_DEBUG, "PCI:[%x] = %x\n", 0xb4, reg); + printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", 0xb4, reg); pcie_write_config32(PCI_DEV(0, 0, 0), 0xb4, reg); if (me_uma_size) { reg = pcie_read_config32(PCI_DEV(0, 0, 0), 0x7c); val = (0x80000 - me_uma_size) & 0xfffff000; reg = (reg & ~0x000fffff) | (val >> 12); - printk(BIOS_DEBUG, "PCI:[%x] = %x\n", 0x7c, reg); + printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", 0x7c, reg); pcie_write_config32(PCI_DEV(0, 0, 0), 0x7c, reg); // ME base reg = pcie_read_config32(PCI_DEV(0, 0, 0), 0x70); val = mestolenbase & 0xfff; reg = (reg & ~0xfff00000) | (val << 20); - printk(BIOS_DEBUG, "PCI:[%x] = %x\n", 0x70, reg); + printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", 0x70, reg); pcie_write_config32(PCI_DEV(0, 0, 0), 0x70, reg); reg = pcie_read_config32(PCI_DEV(0, 0, 0), 0x74); val = mestolenbase & 0xfffff000; reg = (reg & ~0x000fffff) | (val >> 12); - printk(BIOS_DEBUG, "PCI:[%x] = %x\n", 0x74, reg); + printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", 0x74, reg); pcie_write_config32(PCI_DEV(0, 0, 0), 0x74, reg); // ME mask @@ -1081,7 +1081,7 @@ static void dram_memorymap(ramctr_timing * ctrl, int me_uma_size) reg = (reg & ~0x400) | (1 << 10); // set lockbit on ME mem reg = (reg & ~0x800) | (1 << 11); // set ME memory enable - printk(BIOS_DEBUG, "PCI:[%x] = %x\n", 0x78, reg); + printk(BIOS_DEBUG, "PCI(0, 0, 0)[%x] = %x\n", 0x78, reg); pcie_write_config32(PCI_DEV(0, 0, 0), 0x78, reg); } } @@ -1108,17 +1108,17 @@ static void dram_ioregs(ramctr_timing * ctrl) } // Rcomp - printk(BIOS_DEBUG, "RCOMP..."); + printram("RCOMP..."); reg = 0; while (reg == 0) { reg = MCHBAR32(0x5084) & 0x10000; } - printk(BIOS_DEBUG, "done\n"); + printram("done\n"); // Set comp2 comp2 = get_COMP2(ctrl->tCK); MCHBAR32(0x3714) = comp2; - printk(BIOS_DEBUG, "COMP2 done\n"); + printram("COMP2 done\n"); // Set comp1 FOR_ALL_POPULATED_CHANNELS { @@ -1128,12 +1128,12 @@ static void dram_ioregs(ramctr_timing * ctrl) reg = (reg & ~0x38000000) | (1 << 27); //ctl drive up MCHBAR32(0x1810 + channel * 0x100) = reg; } - printk(BIOS_DEBUG, "COMP1 done\n"); + printram("COMP1 done\n"); - printk(BIOS_DEBUG, "FORCE RCOMP and wait 20us..."); + printram("FORCE RCOMP and wait 20us..."); MCHBAR32(0x5f08) |= 0x100; udelay(20); - printk(BIOS_DEBUG, "done\n"); + printram("done\n"); } static void wait_428c(int channel) @@ -1242,8 +1242,6 @@ static void write_mrreg(ramctr_timing *ctrl, int channel, int slotrank, { wait_428c(channel); - printram("MRd: %x <= %x\n", reg, val); - if (ctrl->rank_mirror[channel][slotrank]) { /* DDR3 Rank1 Address mirror * swap the following pins: @@ -1253,8 +1251,6 @@ static void write_mrreg(ramctr_timing *ctrl, int channel, int slotrank, | ((val & 0xa8) << 1); } - printram("MRd: %x <= %x\n", reg, val); - /* DRAM command MRS */ write32(DEFAULT_MCHBAR + 0x4220 + 0x400 * channel, 0x0f000); write32(DEFAULT_MCHBAR + 0x4230 + 0x400 * channel, 0x41001); @@ -1720,7 +1716,7 @@ static void discover_timA_coarse(ramctr_timing * ctrl, int channel, FOR_ALL_LANES { statistics[lane][timA] = !does_lane_work(ctrl, channel, slotrank, lane); - printram("Astat: %d, %d, %d, %x, %x\n", + printram("Astat: %d, %d, %d: %x, %x\n", channel, slotrank, lane, timA, statistics[lane][timA]); } @@ -1731,9 +1727,9 @@ static void discover_timA_coarse(ramctr_timing * ctrl, int channel, upperA[lane] = rn.end; if (upperA[lane] < rn.middle) upperA[lane] += 128; - printram("Aval: %d, %d, %d, %x\n", channel, slotrank, + printram("Aval: %d, %d, %d: %x\n", channel, slotrank, lane, ctrl->timings[channel][slotrank].lanes[lane].timA); - printram("Aend: %d, %d, %d, %x\n", channel, slotrank, + printram("Aend: %d, %d, %d: %x\n", channel, slotrank, lane, upperA[lane]); } } @@ -1777,7 +1773,7 @@ static void discover_timA_fine(ramctr_timing * ctrl, int channel, int slotrank, ctrl->timings[channel][slotrank].lanes[lane].timA = (last_zero + first_all) / 2 + upperA[lane]; - printram("Aval: %d, %d, %d, %x\n", channel, slotrank, + printram("Aval: %d, %d, %d: %x\n", channel, slotrank, lane, ctrl->timings[channel][slotrank].lanes[lane].timA); } } @@ -1968,8 +1964,9 @@ static void read_training(ramctr_timing * ctrl) ctrl->timings[channel][slotrank].val_4024, ctrl->timings[channel][slotrank].val_4028); + printram("final results:\n"); FOR_ALL_LANES - printram("%d, %d, %d, %x\n", channel, slotrank, + printram("Aval: %d, %d, %d: %x\n", channel, slotrank, lane, ctrl->timings[channel][slotrank].lanes[lane].timA); @@ -2109,8 +2106,8 @@ static void discover_timC(ramctr_timing * ctrl, int channel, int slotrank) get_longest_zero_run(statistics[lane], MAX_TIMC + 1); ctrl->timings[channel][slotrank].lanes[lane].timC = rn.middle; if (rn.all) - printk(BIOS_CRIT, "timC discovery failed"); - printram("Cval: %d, %d, %d, %x\n", channel, slotrank, + die("timC discovery failed"); + printram("Cval: %d, %d, %d: %x\n", channel, slotrank, lane, ctrl->timings[channel][slotrank].lanes[lane].timC); } } @@ -2128,7 +2125,6 @@ static void fill_pattern0(ramctr_timing * ctrl, int channel, u32 a, u32 b) unsigned j; unsigned channel_offset = get_precedening_channels(ctrl, channel) * 0x40; - printram("channel_offset=%x\n", channel_offset); for (j = 0; j < 16; j++) write32((void *)(0x04000000 + channel_offset + 4 * j), j & 2 ? b : a); sfence(); @@ -2165,7 +2161,9 @@ static void precharge(ramctr_timing * ctrl) 16; ctrl->timings[channel][slotrank].lanes[lane].rising = 16; - } program_timings(ctrl, channel); + } + + program_timings(ctrl, channel); FOR_ALL_POPULATED_RANKS { wait_428c(channel); @@ -2327,7 +2325,7 @@ static void discover_timB(ramctr_timing * ctrl, int channel, int slotrank) (DEFAULT_MCHBAR + lane_registers[lane] + channel * 0x100 + 4 + ((timB / 32) & 1) * 4) >> (timB % 32)) & 1); - printram("Bstat: %d, %d, %d, %x, %x\n", + printram("Bstat: %d, %d, %d: %x, %x\n", channel, slotrank, lane, timB, statistics[lane][timB]); } @@ -2347,7 +2345,7 @@ static void discover_timB(ramctr_timing * ctrl, int channel, int slotrank) if (rn.all) die("timB discovery failed"); - printram("Bval: %d, %d, %d, %x\n", channel, slotrank, + printram("Bval: %d, %d, %d: %x\n", channel, slotrank, lane, ctrl->timings[channel][slotrank].lanes[lane].timB); } } @@ -2462,7 +2460,7 @@ static void adjust_high_timB(ramctr_timing * ctrl) ctrl->timings[channel][slotrank].lanes[lane].timB += get_timB_high_adjust(res) * 64; - printk(BIOS_DEBUG, "High adjust %d:%016llx\n", lane, res); + printram("High adjust %d:%016llx\n", lane, res); printram("Bval+: %d, %d, %d, %x -> %x\n", channel, slotrank, lane, old, ctrl->timings[channel][slotrank].lanes[lane]. @@ -2824,7 +2822,7 @@ static int try_cmd_stretch(ramctr_timing * ctrl, int cmd_stretch) FOR_ALL_POPULATED_RANKS { stat[slotrank][c320c + 127] = test_320c(ctrl, channel, slotrank); - printram("3stat: %d, %d, %d: %d\n", + printram("3stat: %d, %d, %d: %x\n", channel, slotrank, c320c, stat[slotrank][c320c + 127]); } @@ -2834,7 +2832,7 @@ static int try_cmd_stretch(ramctr_timing * ctrl, int cmd_stretch) get_longest_zero_run(stat[slotrank], 255); ctrl->timings[channel][slotrank].val_320c = rn.middle - 127; - printram("3val: %d, %d: %d\n", channel, + printram("3val: %d, %d: %x\n", channel, slotrank, ctrl->timings[channel][slotrank].val_320c); if (rn.all || rn.length < MIN_C320C_LEN) { @@ -2885,7 +2883,6 @@ static void discover_edges_real(ramctr_timing * ctrl, int channel, int slotrank, ctrl->timings[channel][slotrank].lanes[lane].falling = edge; } - printram("edge %02x\n", edge); program_timings(ctrl, channel); FOR_ALL_LANES { @@ -2947,7 +2944,7 @@ static void discover_edges_real(ramctr_timing * ctrl, int channel, int slotrank, edges[lane] = rn.middle; if (rn.all) die("edge discovery failed"); - printram("eval %d, %d, %d, %02x\n", channel, slotrank, + printram("eval %d, %d, %d: %02x\n", channel, slotrank, lane, edges[lane]); } } @@ -3108,6 +3105,7 @@ static void discover_edges(ramctr_timing * ctrl) /* FIXME: under some conditions (older chipsets?) vendor BIOS sets both edges to the same value. */ write32(DEFAULT_MCHBAR + 0x4eb0, 0x300); + printram("discover falling edges:\n[%x] = %x\n", 0x4eb0, 0x300); FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS { discover_edges_real(ctrl, channel, slotrank, @@ -3115,6 +3113,7 @@ static void discover_edges(ramctr_timing * ctrl) } write32(DEFAULT_MCHBAR + 0x4eb0, 0x200); + printram("discover rising edges:\n[%x] = %x\n", 0x4eb0, 0x200); FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS { discover_edges_real(ctrl, channel, slotrank, @@ -3160,13 +3159,12 @@ static void discover_edges_write_real(ramctr_timing * ctrl, int channel, for (i = 0; i < 3; i++) { write32(DEFAULT_MCHBAR + 0x3000 + 0x100 * channel, reg3000b24[i] << 24); + printram("[%x] = 0x%08x\n", + 0x3000 + 0x100 * channel, reg3000b24[i] << 24); for (pat = 0; pat < NUM_PATTERNS; pat++) { fill_pattern5(ctrl, channel, pat); write32(DEFAULT_MCHBAR + 0x4288 + 0x400 * channel, 0x1f); - printram("patterned\n"); - printram("[%x] = 0x%08x\n(%d, %d)\n", - 0x3000 + 0x100 * channel, reg3000b24[i] << 24, channel, - slotrank); + printram("using pattern %d\n", pat); for (edge = 0; edge <= MAX_EDGE_TIMING; edge++) { FOR_ALL_LANES { ctrl->timings[channel][slotrank].lanes[lane]. @@ -3244,7 +3242,7 @@ static void discover_edges_write_real(ramctr_timing * ctrl, int channel, ! !(raw_statistics[edge] & (1 << lane)); rn = get_longest_zero_run(statistics, MAX_EDGE_TIMING + 1); - printram("edges: %d, %d, %d: 0x%x-0x%x-0x%x, 0x%x-0x%x\n", + printram("edges: %d, %d, %d: 0x%02x-0x%02x-0x%02x, 0x%02x-0x%02x\n", channel, slotrank, i, rn.start, rn.middle, rn.end, rn.start + ctrl->edge_offset[i], rn.end - ctrl->edge_offset[i]); @@ -3272,6 +3270,7 @@ static void discover_edges_write(ramctr_timing * ctrl) /* FIXME: under some conditions (older chipsets?) vendor BIOS sets both edges to the same value. */ write32(DEFAULT_MCHBAR + 0x4eb0, 0x300); + printram("discover falling edges write:\n[%x] = %x\n", 0x4eb0, 0x300); FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS { discover_edges_write_real(ctrl, channel, slotrank, @@ -3279,6 +3278,7 @@ static void discover_edges_write(ramctr_timing * ctrl) } write32(DEFAULT_MCHBAR + 0x4eb0, 0x200); + printram("discover rising edges write:\n[%x] = %x\n", 0x4eb0, 0x200); FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS { discover_edges_write_real(ctrl, channel, slotrank, @@ -3368,6 +3368,7 @@ static void discover_timC_write(ramctr_timing * ctrl) } write32(DEFAULT_MCHBAR + 0x4ea8, 1); + printram("discover timC write:\n"); for (i = 0; i < 3; i++) FOR_ALL_POPULATED_CHANNELS { @@ -3404,7 +3405,7 @@ static void discover_timC_write(ramctr_timing * ctrl) MAX_TIMC + 1); if (rn.all) die("timC write discovery failed"); - printram("timC: %d, %d, %d: 0x%x-0x%x-0x%x, 0x%x-0x%x\n", + printram("timC: %d, %d, %d: 0x%02x-0x%02x-0x%02x, 0x%02x-0x%02x\n", channel, slotrank, i, rn.start, rn.middle, rn.end, rn.start + ctrl->timC_offset[i], @@ -3433,7 +3434,7 @@ static void discover_timC_write(ramctr_timing * ctrl) printram("CPB\n"); FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS FOR_ALL_LANES { - printram("timC [%d, %d, %d] = 0x%x\n", channel, + printram("timC %d, %d, %d: %x\n", channel, slotrank, lane, (lower[channel][slotrank][lane] + upper[channel][slotrank][lane]) / 2); @@ -3483,8 +3484,8 @@ static void channel_test(ramctr_timing * ctrl) int channel, slotrank, lane; FOR_ALL_POPULATED_CHANNELS - if (read32(DEFAULT_MCHBAR + 0x42a0 + (channel << 10)) & 0xa000) - die("Mini channel test failed (1)\n"); + if (read32(DEFAULT_MCHBAR + 0x42a0 + (channel << 10)) & 0xa000) + die("Mini channel test failed (1)\n"); FOR_ALL_POPULATED_CHANNELS { fill_pattern0(ctrl, channel, 0x12345678, 0x98765432); @@ -3526,8 +3527,8 @@ static void channel_test(ramctr_timing * ctrl) write32(DEFAULT_MCHBAR + 0x4284 + (channel << 10), 0x000c0001); wait_428c(channel); FOR_ALL_LANES - if (read32(DEFAULT_MCHBAR + 0x4340 + (channel << 10) + 4 * lane)) - die("Mini channel test failed (2)\n"); + if (read32(DEFAULT_MCHBAR + 0x4340 + (channel << 10) + 4 * lane)) + die("Mini channel test failed (2)\n"); } }

1 0

Patch merged into coreboot/master: cbfstool: Fix broken alignment because of flashmap
by gerrit＠coreboot.org 27 Jan '16

27 Jan '16

the following patch was just integrated into master: commit 95bfcaecf9c054bd116b7f36339f8de595026f28 Author: Werner Zeh <werner.zeh(a)siemens.com> Date: Mon Jan 25 12:47:20 2016 +0100 cbfstool: Fix broken alignment because of flashmap With the introduction of flashmap cbfs alignment of files gets broken because flashmap is located at the beginning of the flash and cbfstool didn't take care about that offset. This commit fixes the alignment in cbfs. Change-Id: Idebb86d4c691b49a351a402ef79c62d31622c773 Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> Reviewed-on: https://review.coreboot.org/13417 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See https://review.coreboot.org/13417 for details. -gerrit

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit January 2016