coreboot-gerrit January 2016

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Patch set updated for coreboot: drivers/intel/fsp2_0: Remove unused prototype in hand_off_block.c
by Alexandru Gagniuc 26 Jan '16

26 Jan '16

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13396 -gerrit commit f26df2090229c2016792f81e1169fbf870f5c7c4 Author: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> Date: Mon Dec 14 13:52:09 2015 -0800 drivers/intel/fsp2_0: Remove unused prototype in hand_off_block.c This was probably a test function that was removed, but the prototype was forgotten. Change-Id: Ied0d242fa317714d73399b480c663ac1ba996b89 Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> --- src/drivers/intel/fsp2_0/hand_off_block.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/src/drivers/intel/fsp2_0/hand_off_block.c b/src/drivers/intel/fsp2_0/hand_off_block.c index 4d061b5..df68e61 100644 --- a/src/drivers/intel/fsp2_0/hand_off_block.c +++ b/src/drivers/intel/fsp2_0/hand_off_block.c @@ -19,8 +19,6 @@ #include <lib.h> #include <string.h> -void hoboparse (const void *hob); - #define HOB_HEADER_LEN 8 struct hob_header {

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Patch set updated for coreboot: drivers/intel/fsp2_0: Update FspVpdUpd.h header
by Alexandru Gagniuc 26 Jan '16

26 Jan '16

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13399 -gerrit commit 23a8c4f6277434792c5959600daf617f30c4a443 Author: Zhao, Lijian <lijian.zhao(a)intel.com> Date: Wed Dec 16 14:46:42 2015 -0800 drivers/intel/fsp2_0: Update FspVpdUpd.h header FSP ABI is still changing (not finalized). We expect the ABI to be updated several times in the future before a "stable" release. Change-Id: I9e000cddfac5485f77a1d6af405728f17198a6e8 Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> --- src/drivers/intel/fsp2_0/include/fsp/FspUpdVpd.h | 379 +++++++++++++++++------ 1 file changed, 292 insertions(+), 87 deletions(-) diff --git a/src/drivers/intel/fsp2_0/include/fsp/FspUpdVpd.h b/src/drivers/intel/fsp2_0/include/fsp/FspUpdVpd.h index 23ae434..4b49f61 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/FspUpdVpd.h +++ b/src/drivers/intel/fsp2_0/include/fsp/FspUpdVpd.h @@ -1,6 +1,6 @@ /** @file -Copyright (c) 2015, Intel Corporation. All rights reserved.<BR> +Copyright (c) 2016, Intel Corporation. All rights reserved.<BR> Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -79,217 +79,229 @@ struct BL_GPIO_PAD_INIT { wchar_t *PadName; } __attribute__((packed)); +struct BL_HDA_VERB_TABLE_HEADER { + uint32_t VendorDeviceId; ///< Codec Vendor/Device ID + uint8_t RevisionId; ///< Revision ID of the codec. 0xFF matches any revision. + uint8_t SdiNo; ///< SDI number, 0xFF matches any SDI. + uint16_t DataDwords; ///< Number of data DWORDs following the header. + uint8_t FrontPanelSupport; + uint8_t Padding[3]; +} __attribute__((packed)); + +struct BL_HDAUDIO_VERB_TABLE { + struct BL_HDA_VERB_TABLE_HEADER VerbTableHeader; + uint32_t VerbTableData[]; +} __attribute__((packed)); + #define FSP_TEMP_RAM_INIT_UPD_SIGNATURE 0x4450555F54505346 /* 'FSPT_UPD' */ #define FSP_MEMORY_INIT_UPD_SIGNATURE 0x4450555F4D505346 /* 'FSPM_UPD' */ #define FSP_SILICON_INIT_UPD_SIGNATURE 0x4450555F53505346 /* 'FSPS_UPD' */ +#define FSP_IMAGE_ID 0x245053464C504124 /* '$APLFSP$' */ +#define FSP_IMAGE_REV 0x00060000 struct DRAM_CONFIG { -/** Offset 0x0000 +/** Offset 0x00A0 Package NOTE: First option is CoPOP if LPDDR3/LPDDR4 is being used. It is SODIMM if DDR3L is being used. **/ uint8_t Package; -/** Offset 0x0001 +/** Offset 0x00A1 Profile Profile list **/ uint8_t Profile; -/** Offset 0x0002 +/** Offset 0x00A2 MemoryDown Memory Down. **/ uint8_t MemoryDown; -/** Offset 0x0003 +/** Offset 0x00A3 DDR3LPageSize NOTE: Only for memory down or downgrade DDR3L frequency. **/ uint8_t DDR3LPageSize; -/** Offset 0x0004 +/** Offset 0x00A4 DDR3LASR NOTE: Only for memory down. **/ uint8_t DDR3LASR; -/** Offset 0x0005 +/** Offset 0x00A5 ScramblerSupport Scrambler Support. **/ uint8_t ScramblerSupport; -/** Offset 0x0006 +/** Offset 0x00A6 ChannelHashMask Channel Hash Mask. **/ uint16_t ChannelHashMask; -/** Offset 0x0008 +/** Offset 0x00A8 SliceHashMask Slice Hash Mask. **/ uint16_t SliceHashMask; -/** Offset 0x000A +/** Offset 0x00AA InterleavedMode Interleaved Mode. **/ uint8_t InterleavedMode; -/** Offset 0x000B +/** Offset 0x00AB ChannelsSlicesEnable Channels Slices Enable. **/ uint8_t ChannelsSlicesEnable; -/** Offset 0x000C +/** Offset 0x00AC MinRefRate2xEnable Provided as a means to defend against Row-Hammer attacks. **/ uint8_t MinRefRate2xEnable; -/** Offset 0x000D +/** Offset 0x00AD DualRankSupportEnable Dual Rank Support Enable. **/ uint8_t DualRankSupportEnable; -/** Offset 0x000E +/** Offset 0x00AE DisableFastBoot 00: Disabled; Used saved training data (if valid)\n01: Enabled; Full re-train of memory. **/ uint8_t DisableFastBoot; -/** Offset 0x000F +/** Offset 0x00AF RmtMode Rank Margin Tool Mode. **/ uint8_t RmtMode; -/** Offset 0x0010 +/** Offset 0x00B0 MemorySizeLimit Memory Size Limit: This value is used to restrict the total amount of memory and the calculations based on it. Value is in MB\nExample encodings are: 0x400 = 1GB, 0x800 = 2GB, 0x1000 = 4GB, 0x2000 8GB. **/ uint16_t MemorySizeLimit; -/** Offset 0x0012 +/** Offset 0x00B2 LowMemoryMaxValue Low Memory Max Value: This value is used to restrict the amount of memory below 4GB and the calculations based on it. Value is in MB\nExample encodings are: 0x400 = 1GB, 0x800 = 2GB, 0x1000 = 4GB, 0x2000 8GB. **/ uint16_t LowMemoryMaxValue; -/** Offset 0x0014 +/** Offset 0x00B4 HighMemoryMaxValue High Memory Max Value: This value is used to restrict the amount of memory above 4GB and the calculations based on it. Value is in MB\nExample encodings are: 0x400 = 1GB, 0x800 = 2GB, 0x1000 = 4GB, 0x2000 8GB. **/ uint16_t HighMemoryMaxValue; -/** Offset 0x0016 +/** Offset 0x00B6 DIMM0SPDAddress DIMM0 SPD Address (NOTE: Only for DDR3L only. Please put 0 for MemoryDown. **/ uint8_t DIMM0SPDAddress; -/** Offset 0x0017 +/** Offset 0x00B7 DIMM1SPDAddress DIMM1 SPD Address (NOTE: Only for DDR3L only. Please put 0 for MemoryDown. **/ uint8_t DIMM1SPDAddress; -/** Offset 0x0018 +/** Offset 0x00B8 Ch0_RankEnable NOTE: Only for memory down\n[0] Enable Rank 0: Must be set to 1 to enable use of this rank.\n[1] Enable Rank 1: Must be set to 1 to enable use of this rank. **/ uint8_t Ch0_RankEnable; -/** Offset 0x0019 +/** Offset 0x00B9 Ch0_DeviceWidth NOTE: Only for memory down\nDRAM Device Data Width populated on Ranks 0 and 1. **/ uint8_t Ch0_DeviceWidth; -/** Offset 0x001A +/** Offset 0x00BA Ch0_DramDensity NOTE: Only for memory down\nDRAM Device Density populated on Ranks 0 and 1. **/ uint8_t Ch0_DramDensity; -/** Offset 0x001B +/** Offset 0x00BB Ch0_Option [0] Rank Select Interleaving Enable. See Address Mapping section for full description.\n0 - Rank Select Interleaving disabled\n1 - Rank Select Interleaving enabled\n[1] Bank Address Hashing Enable. See Address Mapping section for full description.\n0 - Bank Address Hashing disabled\n1 - Bank Address Hashing enabled\n[3:2] Reserved\n[5:4] This register specifies the address mapping to be used:\n00 - 1KB (A)\n01 - 2KB (B). **/ uint8_t Ch0_Option; -/** Offset 0x001C +/** Offset 0x00BC Ch1_RankEnable NOTE: Only for memory down\n[0] Enable Rank 0: Must be set to 1 to enable use of this rank.\n[1] Enable Rank 1: Must be set to 1 to enable use of this rank. **/ uint8_t Ch1_RankEnable; -/** Offset 0x001D +/** Offset 0x00BD Ch1_DeviceWidth NOTE: Only for memory down\nDRAM Device Data Width populated on Ranks 0 and 1. **/ uint8_t Ch1_DeviceWidth; -/** Offset 0x001E +/** Offset 0x00BE Ch1_DramDensity NOTE: Only for memory down\nDRAM Device Density populated on Ranks 0 and 1. **/ uint8_t Ch1_DramDensity; -/** Offset 0x001F +/** Offset 0x00BF Ch1_Option [0] Rank Select Interleaving Enable. See Address Mapping section for full description.\n0 - Rank Select Interleaving disabled\n1 - Rank Select Interleaving enabled\n[1] Bank Address Hashing Enable. See Address Mapping section for full description.\n0 - Bank Address Hashing disabled\n1 - Bank Address Hashing enabled\n[3:2] Reserved\n[5:4] This register specifies the address mapping to be used:\n00 - 1KB (A)\n01 - 2KB (B). **/ uint8_t Ch1_Option; -/** Offset 0x0020 +/** Offset 0x00C0 Ch2_RankEnable NOTE: Only for memory down\n[0] Enable Rank 0: Must be set to 1 to enable use of this rank.\n[1] Enable Rank 1: Must be set to 1 to enable use of this rank. **/ uint8_t Ch2_RankEnable; -/** Offset 0x0021 +/** Offset 0x00C1 Ch2_DeviceWidth NOTE: Only for memory down\nDRAM Device Data Width populated on Ranks 0 and 1. **/ uint8_t Ch2_DeviceWidth; -/** Offset 0x0022 +/** Offset 0x00C2 Ch2_DramDensity NOTE: Only for memory down\nDRAM Device Density populated on Ranks 0 and 1. **/ uint8_t Ch2_DramDensity; -/** Offset 0x0023 +/** Offset 0x00C3 Ch2_Option [0] Rank Select Interleaving Enable. See Address Mapping section for full description.\n0 - Rank Select Interleaving disabled\n1 - Rank Select Interleaving enabled\n[1] Bank Address Hashing Enable. See Address Mapping section for full description.\n0 - Bank Address Hashing disabled\n1 - Bank Address Hashing enabled\n[3:2] Reserved\n[5:4] This register specifies the address mapping to be used:\n00 - 1KB (A)\n01 - 2KB (B). **/ uint8_t Ch2_Option; -/** Offset 0x0024 +/** Offset 0x00C4 Ch3_RankEnable NOTE: Only for memory down\n[0] Enable Rank 0: Must be set to 1 to enable use of this rank.\n[1] Enable Rank 1: Must be set to 1 to enable use of this rank. **/ uint8_t Ch3_RankEnable; -/** Offset 0x0025 +/** Offset 0x00C5 Ch3_DeviceWidth NOTE: Only for memory down\nDRAM Device Data Width populated on Ranks 0 and 1. **/ uint8_t Ch3_DeviceWidth; -/** Offset 0x0026 +/** Offset 0x00C6 Ch3_DramDensity NOTE: Only for memory down\nDRAM Device Density populated on Ranks 0 and 1. **/ uint8_t Ch3_DramDensity; -/** Offset 0x0027 +/** Offset 0x00C7 Ch3_Option [0] Rank Select Interleaving Enable. See Address Mapping section for full description.\n0 - Rank Select Interleaving disabled\n1 - Rank Select Interleaving enabled\n[1] Bank Address Hashing Enable. See Address Mapping section for full description.\n0 - Bank Address Hashing disabled\n1 - Bank Address Hashing enabled\n[3:2] Reserved\n[5:4] This register specifies the address mapping to be used:\n00 - 1KB (A)\n01 - 2KB (B). **/ uint8_t Ch3_Option; -/** Offset 0x0028 +/** Offset 0x00C8 Ch0_Bit_swizzling Channel 0 PHY to DUnit DQ mapping (only used if not 1-1 mapping)Range: 0-32. **/ uint8_t Ch0_Bit_swizzling[32]; -/** Offset 0x0048 +/** Offset 0x00E8 Ch1_Bit_swizzling Channel 1 PHY to DUnit DQ mapping (only used if not 1-1 mapping)Range: 0-32. **/ uint8_t Ch1_Bit_swizzling[32]; -/** Offset 0x0068 +/** Offset 0x0108 Ch2_Bit_swizzling Channel 2 PHY to DUnit DQ mapping (only used if not 1-1 mapping)Range: 0-32. **/ uint8_t Ch2_Bit_swizzling[32]; -/** Offset 0x0088 +/** Offset 0x0128 Ch3_Bit_swizzling Channel 3 PHY to DUnit DQ mapping (only used if not 1-1 mapping)Range: 0-32. **/ uint8_t Ch3_Bit_swizzling[32]; -/** Offset 0x00A8 +/** Offset 0x0148 **/ uint8_t DramReserved; } __attribute__((packed)); -#define FSP_IMAGE_ID 0x245053464C504124 /* '$APLFSP$' */ -#define FSP_IMAGE_REV 0x00060000 - - struct TEMP_RAM_INIT_UPD { /** Offset 0x0000 @@ -306,6 +318,7 @@ struct TEMP_RAM_INIT_UPD { uint32_t ReservedTempRamInitUpd; } __attribute__((packed)); + struct MEMORY_INIT_UPD { /** Offset 0x0000 **/ @@ -373,49 +386,40 @@ struct MEMORY_INIT_UPD { **/ uint8_t PrimaryVideoAdaptor; /** Offset 0x0095 - GT PM Support - Enable/Disable GT power management support. -**/ - uint8_t PmSupport; -/** Offset 0x0096 - RC6(Render Standby) - Enable/Disable render standby support. **/ - uint8_t EnableRenderStandby; -/** Offset 0x0097 - PAVP Enable - Enable/Disable Protected Audio Visual Path (PAVP). -**/ - uint8_t PavpEnable; -/** Offset 0x0098 -**/ - uint64_t UnusedUpdSpace3; -/** Offset 0x0000 + uint8_t UnusedUpdSpace3[11]; +/** Offset 0x00A0 **/ struct DRAM_CONFIG DramConfig; -/** Offset 0x01B9 +/** Offset 0x0149 +**/ + uint8_t UnusedUpdSpace4[31]; +/** Offset 0x0168 + FIT Table Pointer + FIT table pointer. **/ - uint8_t UnusedUpdSpace6[35]; -/** Offset 0x01DC + uint32_t FitTablePtr; +/** Offset 0x016C OEM File Loading Address Determine the memory base address to load a specified file from CSE file system after memory is available. **/ uint32_t OemLoadingBase; -/** Offset 0x01E0 +/** Offset 0x0170 OEM File Name to Load Specify a file name to load from CSE file system after memory is available. Empty indicates no file needs to be loaded. **/ uint8_t OemFileName[16]; -/** Offset 0x01F0 +/** Offset 0x0180 GPIO Table Pointer GPIO table pointer to a BL_GPIO_PAD_INIT structure. **/ struct BL_GPIO_PAD_INIT* GpioPadInitTablePtr; -/** Offset 0x01F4 +/** Offset 0x0184 **/ uint32_t ReservedMemoryInitUpd; } __attribute__((packed)); + struct SILICON_INIT_UPD { /** Offset 0x0000 **/ @@ -427,23 +431,129 @@ struct SILICON_INIT_UPD { **/ uint8_t UnusedUpdSpace0[23]; /** Offset 0x0020 + ActiveProcessorCores + Number of active cores. +**/ + uint8_t ActiveProcessorCores; +/** Offset 0x0021 + Disable Core1 + Disable/Enable Core1. +**/ + uint8_t DisableCore1; +/** Offset 0x0022 + Disable Core2 + Disable/Enable Core2. +**/ + uint8_t DisableCore2; +/** Offset 0x0023 + Disable Core3 + Disable/Enable Core3. +**/ + uint8_t DisableCore3; +/** Offset 0x0024 + VMX Enable + Enable or Disable VMX. +**/ + uint8_t VmxEnable; +/** Offset 0x0025 + Memory region allocation for Processor Trace + Memory region allocation for Processor Trace, allowed range is from 4K (0x0) to 128MB (0xF); <b>0xFF: Disable. +**/ + uint8_t ProcTraceMemSize; +/** Offset 0x0026 + Enable Processor Trace + Enable or Disable Processor Trace feature. +**/ + uint8_t ProcTraceEnable; +/** Offset 0x0027 + Eist + Enable or Disable Intel SpeedStep Technology. +**/ + uint8_t Eist; +/** Offset 0x0028 + Boot PState + Boot PState with HFM or LFM. 0: HFM; 1: LFM. +**/ + uint8_t BootPState; +/** Offset 0x0029 + CPU power states (C-states) + Enable or Disable CPU power states (C-states). 0: Disable; 1: Enable. +**/ + uint8_t EnableCx; +/** Offset 0x002A + Enhanced C-states + Enable or Disable Enhanced C-states. 0: Disable; 1: Enable. +**/ + uint8_t C1e; +/** Offset 0x002B + Bi-Directional PROCHOT# + Enable or Disable Bi-Directional PROCHOT#; 0: Disable; 1: Enable. +**/ + uint8_t BiProcHot; +/** Offset 0x002C + Max Pkg Cstate + Max Pkg Cstate. 0:PkgC0C1; 1:PkgC2; 2:PkgC3; 3:PkgC6; 4:PkgC7; 5:PkgC7s; 6:PkgC8; 7:PkgC9; 8:PkgC10; 9:PkgCMax; 254:PkgCpuDefault; 255:PkgAuto. +**/ + uint8_t PkgCStateLimit; +/** Offset 0x002D +**/ + uint8_t UnusedUpdSpace1; +/** Offset 0x002E + C-State auto-demotion + C-State Auto Demotion. 0:Disable C1 and C3 Auto-demotion; 1:Enable C3/C6/C7 Auto-demotion to C1; 2:Enable C6/C7 Auto-demotion to C3; 3:Enable C6/C7 Auto-demotion to C1 and C3. +**/ + uint8_t CStateAutoDemotion; +/** Offset 0x002F + C-State un-demotion + C-State un-demotion. 0:Disable C1 and C3 Un-demotion; 1:Enable C1 Un-demotion; 2:Enable C3 Un-demotion; 3:Enable C1 and C3 Un-demotion. +**/ + uint8_t CStateUnDemotion; +/** Offset 0x0030 + Max Core C-State + Max Core C-State. 0:Unlimited;1:C1;2:C3;3:C6;4:C7;5:C8;6:C9;7:C10;8:CCx. +**/ + uint8_t MaxCoreCState; +/** Offset 0x0031 + Package C-State Demotion + Enable or Disable Package Cstate Demotion. 0:Disable; 1: Enable. +**/ + uint8_t PkgCStateDemotion; +/** Offset 0x0032 + Package C-State Un-demotion + Enable or Disable Package Cstate UnDemotion. 0:Disable; 1: Enable. +**/ + uint8_t PkgCStateUnDemotion; +/** Offset 0x0033 + Turbo Mode + Enable or Disable long duration Turbo Mode. 0:Disable; 1: Enable. +**/ + uint8_t TurboMode; +/** Offset 0x0034 +**/ + uint8_t UnusedUpdSpace2[12]; +/** Offset 0x0040 + HD-Audio I/O Buffer Ownership + Set HD-Audio I/O Buffer Ownership. +**/ + uint8_t HdAudioIoBufferOwnership; +/** Offset 0x0041 +**/ + uint8_t UnusedUpdSpace3[60]; +/** Offset 0x007D Enable SD controller Enable/disable SD Card controller. **/ uint8_t SdcardEnabled; -/** Offset 0x0021 +/** Offset 0x007E Enable SDIO controller Enable/disable SDIO controller. **/ uint8_t SdioEnabled; -/** Offset 0x0022 +/** Offset 0x007F Enable eMMC controller Enable/disable eMMC controller. **/ uint8_t eMMCEnabled; -/** Offset 0x0023 -**/ - uint8_t UnusedUpdSpace1[93]; /** Offset 0x0080 Enable SATA Enable/disable SATA controller. @@ -473,7 +583,7 @@ struct SILICON_INIT_UPD { Enable PCIE RP Enable/disable PCIE Root Ports. 0: disable, 1: enable. One byte for each port, byte0 for port1, byte1 for port2, and so on. **/ - uint8_t PcieRpEnable[6]; + uint8_t PcieRootPortEn[6]; /** Offset 0x008D Configure CLKREQ Number Configure Root Port CLKREQ Number if CLKREQ is supported. Each value in array can be between 0-6. One byte for each port, byte0 for port1, byte1 for port2, and so on. @@ -490,26 +600,91 @@ struct SILICON_INIT_UPD { **/ uint8_t PortUsb30Enable[6]; /** Offset 0x00A1 - Enable XHCI SSIC Eanble - Enable/disable XHCI SSIC port. + Enable XHCI SSIC ports + Enable/disable XHCI SSIC ports. One byte for each port, byte0 for port0, byte1 for port1. **/ - uint8_t SsicPortEnable; -/** Offset 0x00A2 + uint8_t SsicPortEnable[2]; +/** Offset 0x00A3 Enable SMBus Enable/disable SMBus controller. **/ uint8_t SmbusEnable; -/** Offset 0x00A3 +/** Offset 0x00A4 + High Definition Audio Verb Table Pointer + High Definition Audio Verb Table structure for initialization. **/ - uint8_t UnusedUpdSpace2[13]; -/** Offset 0x00B0 + struct BL_HDAUDIO_VERB_TABLE* HdaVerbTablePtr; +/** Offset 0x00A8 + Enable/Disable P2SB device hidden. + Enable/Disable P2SB device hidden. +**/ + uint8_t HideP2sb; +/** Offset 0x00A9 +**/ + uint8_t UnusedUpdSpace4[52]; +/** Offset 0x00DD + Ufs Enable/Disable + Enable/Disable Ufs. +**/ + uint8_t UfsEnabled; +/** Offset 0x00DE IPU Enable/Disable Enable/Disable IPU Device. **/ uint8_t IpuEn; -/** Offset 0x00B1 -**/ - uint8_t UnusedUpdSpace3[303]; +/** Offset 0x00DF + IMGU ACPI mode selection + 0=Auto, 1(Default)=IGFX Child device, 2=ACPI device +**/ + uint8_t IpuAcpiMode; +/** Offset 0x00E0 + ResetSelect + ResetSelect. 0x6:warm reset; 0xE:cold reset +**/ + uint8_t ResetSelect; +/** Offset 0x00E1 + CRIDSettings + PMC CRID setting. 0:Disable;1:CRID_1;2:CRID_2;3:CRID_3 +**/ + uint8_t CRIDSettings; +/** Offset 0x00E2 + Enable HPET + Enable/disable HPET. +**/ + uint8_t Hpet; +/** Offset 0x00E3 + Enable PCIE Clock Gating + Enable/disable PCIE Clock Gating.0:Enable;1:Disable +**/ + uint8_t PcieClockGatingDisabled; +/** Offset 0x00E4 + Enable PCIE Root Port 8xh Decode + Enable/disable PCIE Root Port 8xh Decode.0:Disable;1:Enable +**/ + uint8_t PcieRootPort8xhDecode; +/** Offset 0x00E5 + PCIE 8xh Decode Port Index + PCIE 8xh Decode Port Index. +**/ + uint8_t Pcie8xhDecodePortIndex; +/** Offset 0x00E6 + Enable PCIE Root Port Peer Memory Write + Enable/disable PCIE root port peer memory write.0:Disable;1:Enable +**/ + uint8_t PcieRootPortPeerMemoryWriteEnable; +/** Offset 0x00E7 + Enable SC Gaussian Mixture Models + Enable/disable SC Gaussian Mixture Models.0:Disable;1:Enable +**/ + uint8_t Gmm; +/** Offset 0x00E8 + Enable S0ix + Enable/disable S0ix.0:Disable;1:Enable +**/ + uint8_t S0ix; +/** Offset 0x00E9 +**/ + uint8_t UnusedUpdSpace5[247]; /** Offset 0x01E0 BMP Logo Data Size BMP logo data buffer size. @@ -526,11 +701,41 @@ struct SILICON_INIT_UPD { **/ uint32_t GraphicsConfigPtr; /** Offset 0x01EC + GT PM Support + Enable/Disable GT power management support. +**/ + uint8_t PmSupport; +/** Offset 0x01ED + RC6(Render Standby) + Enable/Disable render standby support. +**/ + uint8_t EnableRenderStandby; +/** Offset 0x01EE + PAVP Enable + Enable/Disable Protected Audio Visual Path (PAVP). +**/ + uint8_t PavpEnable; +/** Offset 0x01EF + PAVP PR3 + Enable/Disable PAVP PR3 +**/ + uint8_t PavpPr3; +/** Offset 0x01F0 + CdClock Frequency selection + 0: 144 Mhz, 1: 288 Mhz, 2: 384 Mhz, 3: 576 Mhz, 4(Default): 624 Mhz +**/ + uint8_t CdClock; +/** Offset 0x01F1 + Enable/Disable PeiGraphicsPeimInit + Enable(Default): Enable PeiGraphicsPeimInit, Disable: Disable PeiGraphicsPeimInit +**/ + uint8_t PeiGraphicsPeimInit; +/** Offset 0x01F2 **/ - uint8_t UnusedUpdSpace4[12]; -/** Offset 0x01F8 + uint8_t UnusedUpdSpace6[11]; +/** Offset 0x01FD **/ - uint32_t ReservedSiliconInitUpd; + uint8_t ReservedSiliconInitUpd; } __attribute__((packed)); #endif

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Patch set updated for coreboot: soc/apollolake: Adjust CAR addresses for new FSP memory layout
by Alexandru Gagniuc 26 Jan '16

26 Jan '16

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13398 -gerrit commit d65768ae7597cb7c54905430e22a5fca48b59793 Author: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> Date: Wed Jan 13 14:11:11 2016 -0800 soc/apollolake: Adjust CAR addresses for new FSP memory layout The FSP memory layout changed, and things need to be shuffled around a bit, as well as doubling the size of the CAR region. Change-Id: I14cbcf5141eea9a7a69c8c1628aac701223c04e8 Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> --- src/soc/intel/apollolake/Kconfig | 18 +++++------------- 1 file changed, 5 insertions(+), 13 deletions(-) diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index 1b60bcf..179eaad 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -59,7 +59,7 @@ config DCACHE_RAM_BASE config DCACHE_RAM_SIZE hex "Length in bytes of cache-as-RAM" - default 0x80000 + default 0x100000 help The size of the cache-as-ram region required during bootblock and/or romstage. @@ -69,21 +69,13 @@ config DCACHE_RAM_BOOTBLOCK_STACK_SIZE default 0x800 help The amount of anticipated stack usage from the bootblock during - pre-romstage initialization.. + pre-romstage initialization. -config IFD_BIOS_START +config ROMSTAGE_CAR_ADDR hex - default 0x1000 + default 0xfef2e000 help - The starting address of flash region 1 (BIOS), as declared in the - firmware descriptor. This can be obtained via 'ifdtool -d'. - -config IFD_BIOS_END - hex - default ROM_SIZE - help - The ending address of flash region 1 (BIOS), as declared in the - firmware descriptor. This can be obtained via 'ifdtool -d'. + The base address (in CAR) where romstage should be linked config CPU_ADDR_BITS int

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Patch set updated for coreboot: drivers/intel/fsp2_0: Do not relocate FIT data to FSP stack
by Alexandru Gagniuc 26 Jan '16

26 Jan '16

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13400 -gerrit commit 87c53f6edb5191b94b415f34c1b845be7dec5654 Author: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> Date: Wed Dec 16 14:47:17 2015 -0800 drivers/intel/fsp2_0: Do not relocate FIT data to FSP stack With the newer FSP versions, we can simply pass in a pointer to the FIT data, instead of needing to copy it to FSP's stack. Change-Id: I695759bd775e4cf7a206c56d1ffc4619bae5c724 Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> --- src/drivers/intel/fsp2_0/Kconfig | 7 +------ src/drivers/intel/fsp2_0/memory_init.c | 14 ++------------ 2 files changed, 3 insertions(+), 18 deletions(-) diff --git a/src/drivers/intel/fsp2_0/Kconfig b/src/drivers/intel/fsp2_0/Kconfig index bfba51a..683c7df 100644 --- a/src/drivers/intel/fsp2_0/Kconfig +++ b/src/drivers/intel/fsp2_0/Kconfig @@ -39,10 +39,6 @@ config VBT_FILE help The path and filename of the VBT binary for this platform. -config FIT_CAR_ADDR - hex - default 0xfef2dc00 - # Cache As RAM region layout: # # +-------------+ DCACHE_RAM_BASE + DCACHE_RAM_SIZE [0xff000000] @@ -56,8 +52,7 @@ config FIT_CAR_ADDR # | romstage | # | code | # +-------------+ ROMSTAGE_CAR_ADDR [0xfef2e000] -# | FIT TABLE | -# +-------------+ FIT_CAR_ADDR [0xfef2dc00] +# | | # | FSP-M | # | stack/data | # +-------------+ DCACHE_RAM_BASE + 0x4000 [0xfef04000] diff --git a/src/drivers/intel/fsp2_0/memory_init.c b/src/drivers/intel/fsp2_0/memory_init.c index 84f6fe1..c9acb94c 100644 --- a/src/drivers/intel/fsp2_0/memory_init.c +++ b/src/drivers/intel/fsp2_0/memory_init.c @@ -83,6 +83,7 @@ static enum fsp_status do_fsp_memory_init(void **hob_list_ptr, /* Update the UPD data */ raminit_upd.GpioPadInitTablePtr = NULL; + raminit_upd.FitTablePtr = read32((void *)FIT_POINTER); fill_console_params(&raminit_upd); platform_fsp_memory_init_params_cb(&raminit_upd); @@ -103,23 +104,12 @@ static enum fsp_status do_fsp_memory_init(void **hob_list_ptr, return status; } -/* - * Relocate FIT table to FSP-M's stack/data space - * - * FSP-M expects to find FIT entries at some address hardcoded in FSP. - */ -static void relocate_fit(void) -{ - uint32_t fit_loc = read32((void *)FIT_POINTER); - memcpy((void*)CONFIG_FIT_CAR_ADDR, (void*)fit_loc, FIT_SIZE); -} - enum fsp_status fsp_memory_init(void **hob_list, size_t tolum_size) { struct fsp_header hdr; if (fsp_load_binary(&hdr, "blobs/fsp-m.bin") != CB_SUCCESS) return FSP_NOT_FOUND; - relocate_fit(); + return do_fsp_memory_init(hob_list, &hdr, tolum_size); }

1 0

Patch set updated for coreboot: soc/intel/apollolake: Do not setup ACPI SMI_CMD
by Alexandru Gagniuc 26 Jan '16

26 Jan '16

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13389 -gerrit commit 46b66c0625961d950b8db9bda88d467fa47ff4cb Author: Zhao, Lijian <lijian.zhao(a)intel.com> Date: Mon Jan 4 16:34:07 2016 -0800 soc/intel/apollolake: Do not setup ACPI SMI_CMD Current coreboot do not have the smm setup, also no smi handler yet.So we should not report the SMI CMD port to ACPI FADT table, also the ACPI enable and ACPI disable command should be zero as well. Change-Id: I1d03082359191eee7e13bfea5a98c65e0722dfb2 Signed-off-by: Zhao, Lijian <lijian.zhao(a)intel.com> --- src/soc/intel/apollolake/acpi.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/src/soc/intel/apollolake/acpi.c b/src/soc/intel/apollolake/acpi.c index 9939408..3b622b8 100644 --- a/src/soc/intel/apollolake/acpi.c +++ b/src/soc/intel/apollolake/acpi.c @@ -63,9 +63,7 @@ void soc_fill_common_fadt(acpi_fadt_t * fadt) const uint16_t pmbase = ACPI_PMIO_BASE; fadt->sci_int = acpi_sci_irq(); - fadt->smi_cmd = APM_CNT; - fadt->acpi_enable = APM_CNT_ACPI_ENABLE; - fadt->acpi_disable = APM_CNT_ACPI_DISABLE; + fadt->smi_cmd = 0; /* No Smi Handler as SMI_CMD is 0*/ fadt->pm1a_evt_blk = pmbase + PM1_STS; fadt->pm1a_cnt_blk = pmbase + PM1_CNT;

1 0

Patch set updated for coreboot: Move object files to $(obj)/<class>/
by Nico Huber 26 Jan '16

26 Jan '16

Nico Huber (nico.h(a)gmx.de) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13181 -gerrit commit 9d46bc2407bcc4895a5bbb838715a824d909a684 Author: Nico Huber <nico.h(a)gmx.de> Date: Sat Jan 23 01:24:33 2016 +0100 Move object files to $(obj)/<class>/ Instead of tagging object files with .<class>, move them to a <class> directory below $(obj)/. This way we can keep a 1:1 mapping between source- and object-file names. The 1:1 mapping is a prerequisite for Ada, where the compiler refuses any other object-file name. Tested by verifying that the resulting coreboot.rom files didn't change for all of Jenkins' abuild configurations. Change-Id: Idb7a8abec4ea0a37021d9fc24cc8583c4d3bf67c Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- Makefile | 8 +++++++- Makefile.inc | 16 ++-------------- src/arch/x86/car.ld | 4 ++-- src/cpu/x86/Makefile.inc | 4 +++- src/cpu/x86/smm/Makefile.inc | 32 ++++++++++++++++---------------- src/include/memlayout.h | 8 ++++---- 6 files changed, 34 insertions(+), 38 deletions(-) diff --git a/Makefile b/Makefile index 3652559..a464345 100644 --- a/Makefile +++ b/Makefile @@ -184,7 +184,13 @@ add-special-class= \ # Only .c and .S get converted to .o, other files (like .ld) keep their name. # $1 stage name # $2 file path (list) -src-to-obj=$(foreach file,$(2),$(subst .$(1),,$(basename $(patsubst src/%,$(obj)/%,$(file)))).$(1)$(patsubst %.c,%.o,$(patsubst %.S,%.o,$(suffix $(file))))) +src-to-obj=\ + $(patsubst $(obj)/%,$(obj)/$(1)/%,\ + $(patsubst $(obj)/$(1)/%,$(obj)/%,\ + $(patsubst src/%,$(obj)/%,\ + $(patsubst %.c,%.o,\ + $(patsubst %.S,%.o,\ + $(subst .$(1),,$(2))))))) # Clean -y variables, include Makefile.inc # Add paths to files in X-y to X-srcs diff --git a/Makefile.inc b/Makefile.inc index 8bf0ca5..078d43a 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -415,18 +415,6 @@ ramstage-y+=$(obj)/mainboard/$(MAINBOARDDIR)/static.c romstage-y+=$(obj)/mainboard/$(MAINBOARDDIR)/static.c verstage-y+=$(obj)/mainboard/$(MAINBOARDDIR)/static.c -$(obj)/%.ramstage.o $(abspath $(obj))/%.ramstage.o: $(obj)/%.c $(obj)/config.h $(OPTION_TABLE_H) - @printf " CC $(subst $(obj)/,,$(@))\n" - $(CC_ramstage) -MMD $(CFLAGS_ramstage) $(CPPFLAGS_ramstage) $(ramstage-c-ccopts) -c -o $@ $< - -$(obj)/%.romstage.o $(abspath $(obj))/%.romstage.o: $(obj)/%.c $(obj)/config.h $(OPTION_TABLE_H) - @printf " CC $(subst $(obj)/,,$(@))\n" - $(CC_romstage) -MMD $(CFLAGS_romstage) $(CPPFLAGS_romstage) $(romstage-c-ccopts) -c -o $@ $< - -$(obj)/%.bootblock.o $(abspath $(obj))/%.bootblock.o: $(obj)/%.c $(obj)/config.h $(OPTION_TABLE_H) - @printf " CC $(subst $(obj)/,,$(@))\n" - $(CC_bootblock) -MMD $(CFLAGS_bootblock) $(CPPFLAGS_bootblock) $(bootblock-c-ccopts) -c -o $@ $< - $(objgenerated)/libverstage.a: $$(libverstage-objs) rm -f $@ $(AR_libverstage) rcsT $@ $^ @@ -437,8 +425,8 @@ clean-abuild: rm -rf coreboot-builds clean-for-update-target: - rm -f $(obj)/ramstage* $(obj)/coreboot.romstage $(obj)/coreboot.pre* $(obj)/coreboot.bootblock $(obj)/coreboot.a - rm -rf $(obj)/bootblock* $(obj)/romstage* $(obj)/location.* + rm -f $(obj)/ramstage?* $(obj)/coreboot.romstage $(obj)/coreboot.pre* $(obj)/coreboot.bootblock $(obj)/coreboot.a + rm -rf $(obj)/bootblock?* $(obj)/romstage?* $(obj)/location.* rm -f $(obj)/option_table.* $(obj)/crt0.S $(obj)/ldscript rm -f $(obj)/mainboard/$(MAINBOARDDIR)/static.c $(obj)/mainboard/$(MAINBOARDDIR)/config.py $(obj)/mainboard/$(MAINBOARDDIR)/static.dot rm -f $(obj)/mainboard/$(MAINBOARDDIR)/crt0.s $(obj)/mainboard/$(MAINBOARDDIR)/crt0.disasm diff --git a/src/arch/x86/car.ld b/src/arch/x86/car.ld index e5669dc..191dcaf 100644 --- a/src/arch/x86/car.ld +++ b/src/arch/x86/car.ld @@ -55,8 +55,8 @@ . = 0xffffff00; .illegal_globals . : { - *(EXCLUDE_FILE ("*/libagesa.*.a:" "*/buildOpts.romstage.o" "*/agesawrapper.romstage.o" "*/vendorcode/amd/agesa/*" "*/vendorcode/amd/cimx/*") .data) - *(EXCLUDE_FILE ("*/libagesa.*.a:" "*/buildOpts.romstage.o" "*/agesawrapper.romstage.o" "*/vendorcode/amd/agesa/*" "*/vendorcode/amd/cimx/*") .data.*) + *(EXCLUDE_FILE ("*/libagesa.*.a:" "*/romstage*/buildOpts.o" "*/romstage*/agesawrapper.o" "*/vendorcode/amd/agesa/*" "*/vendorcode/amd/cimx/*") .data) + *(EXCLUDE_FILE ("*/libagesa.*.a:" "*/romstage*/buildOpts.o" "*/romstage*/agesawrapper.o" "*/vendorcode/amd/agesa/*" "*/vendorcode/amd/cimx/*") .data.*) *(.bss) *(.bss.*) *(.sbss) diff --git a/src/cpu/x86/Makefile.inc b/src/cpu/x86/Makefile.inc index ae81ab4..0efbdd7 100644 --- a/src/cpu/x86/Makefile.inc +++ b/src/cpu/x86/Makefile.inc @@ -6,6 +6,8 @@ subdirs-$(CONFIG_PARALLEL_MP) += name ramstage-$(CONFIG_PARALLEL_MP) += mp_init.c ramstage-$(CONFIG_MIRROR_PAYLOAD_TO_RAM_BEFORE_LOADING) += mirror_payload.c +additional-dirs += $(obj)/cpu/x86 + SIPI_ELF=$(obj)/cpu/x86/sipi_vector.elf SIPI_RMOD=$(SIPI_ELF).rmod SIPI_BIN=$(SIPI_ELF:.elf=) @@ -30,4 +32,4 @@ $(SIPI_BIN): $(SIPI_RMOD) $(call src-to-obj,ramstage,$(SIPI_BIN).manual): $(SIPI_BIN) @printf " OBJCOPY $(subst $(obj)/,,$(@))\n" - cd $(dir $@); $(OBJCOPY_rmodules_$(ARCH-ramstage-y)) -I binary $(notdir $<) $(target-objcopy) $(notdir $@) + cd $(dir $<); $(OBJCOPY_rmodules_$(ARCH-ramstage-y)) -I binary $(notdir $<) $(target-objcopy) $(abspath $@) diff --git a/src/cpu/x86/smm/Makefile.inc b/src/cpu/x86/smm/Makefile.inc index 46abd05..c912a8f 100644 --- a/src/cpu/x86/smm/Makefile.inc +++ b/src/cpu/x86/smm/Makefile.inc @@ -27,14 +27,14 @@ smmstub-generic-ccopts += -D__SMM__ smm-generic-ccopts += -D__SMM__ smm-c-deps:=$$(OPTION_TABLE_H) -$(obj)/cpu/x86/smm/smm.o: $$(smm-objs) $(COMPILER_RT_smm) +$(obj)/smm/smm.o: $$(smm-objs) $(COMPILER_RT_smm) $(LD_smm) -nostdlib -r -o $@ $(COMPILER_RT_FLAGS_smm) --whole-archive --start-group $(smm-objs) --no-whole-archive $(COMPILER_RT_smm) --end-group # change to the target path because objcopy will use the path name in its # ELF symbol names. -$(call src-to-obj,ramstage,$(obj)/cpu/x86/smm/smm.manual): $(obj)/cpu/x86/smm/smm +$(call src-to-obj,ramstage,$(obj)/cpu/x86/smm/smm.manual): $(obj)/smm/smm @printf " OBJCOPY $(subst $(obj)/,,$(@))\n" - cd $(dir $@); $(OBJCOPY_smm) -I binary $(notdir $<) $(target-objcopy) $(notdir $@) + cd $(dir $<); $(OBJCOPY_smm) -I binary $(notdir $<) $(target-objcopy) $(abspath $@) ifeq ($(CONFIG_SMM_TSEG),y) @@ -49,40 +49,40 @@ ramstage-srcs += $(obj)/cpu/x86/smm/smmstub.manual # SMM Stub Module. The stub is used as a trampoline for relocation and normal # SMM handling. -$(obj)/cpu/x86/smm/smmstub.o: $$(smmstub-objs) +$(obj)/smmstub/smmstub.o: $$(smmstub-objs) $(CC_smmstub) $(CFLAGS_smmstub) -nostdlib -r -o $@ $^ # Link the SMM stub module with a 0-byte heap. ifeq ($(CONFIG_ARCH_RAMSTAGE_X86_32),y) -$(eval $(call rmodule_link,$(obj)/cpu/x86/smm/smmstub.elf, $(obj)/cpu/x86/smm/smmstub.o, 0,x86_32)) +$(eval $(call rmodule_link,$(obj)/smmstub/smmstub.elf, $(obj)/smmstub/smmstub.o, 0,x86_32)) else -$(eval $(call rmodule_link,$(obj)/cpu/x86/smm/smmstub.elf, $(obj)/cpu/x86/smm/smmstub.o, 0,x86_64)) +$(eval $(call rmodule_link,$(obj)/smmstub/smmstub.elf, $(obj)/smmstub/smmstub.o, 0,x86_64)) endif -$(obj)/cpu/x86/smm/smmstub: $(obj)/cpu/x86/smm/smmstub.elf.rmod +$(obj)/smmstub/smmstub: $(obj)/smmstub/smmstub.elf.rmod $(OBJCOPY_smmstub) -O binary $< $@ -$(call src-to-obj,ramstage,$(obj)/cpu/x86/smm/smmstub.manual): $(obj)/cpu/x86/smm/smmstub +$(call src-to-obj,ramstage,$(obj)/cpu/x86/smm/smmstub.manual): $(obj)/smmstub/smmstub @printf " OBJCOPY $(subst $(obj)/,,$(@))\n" - cd $(dir $@); $(OBJCOPY_smmstub) -I binary $(notdir $<) $(target-objcopy) $(notdir $@) + cd $(dir $<); $(OBJCOPY_smmstub) -I binary $(notdir $<) $(target-objcopy) $(abspath $@) # C-based SMM handler. ifeq ($(CONFIG_ARCH_RAMSTAGE_X86_32),y) -$(eval $(call rmodule_link,$(obj)/cpu/x86/smm/smm.elf, $(obj)/cpu/x86/smm/smm.o, $(CONFIG_SMM_MODULE_HEAP_SIZE),x86_32)) +$(eval $(call rmodule_link,$(obj)/smm/smm.elf, $(obj)/smm/smm.o, $(CONFIG_SMM_MODULE_HEAP_SIZE),x86_32)) else -$(eval $(call rmodule_link,$(obj)/cpu/x86/smm/smm.elf, $(obj)/cpu/x86/smm/smm.o, $(CONFIG_SMM_MODULE_HEAP_SIZE),x86_64)) +$(eval $(call rmodule_link,$(obj)/smm/smm.elf, $(obj)/smm/smm.o, $(CONFIG_SMM_MODULE_HEAP_SIZE),x86_64)) endif -$(obj)/cpu/x86/smm/smm: $(obj)/cpu/x86/smm/smm.elf.rmod +$(obj)/smm/smm: $(obj)/smm/smm.elf.rmod $(OBJCOPY_smm) -O binary $< $@ else # CONFIG_SMM_TSEG -$(obj)/cpu/x86/smm/smm: $(obj)/cpu/x86/smm/smm.o $(src)/cpu/x86/smm/smm.ld - $(LD_smm) $(LDFLAGS_smm) -o $(obj)/cpu/x86/smm/smm.elf -T $(src)/cpu/x86/smm/smm.ld $(obj)/cpu/x86/smm/smm.o - $(NM_smm) -n $(obj)/cpu/x86/smm/smm.elf | sort > $(obj)/cpu/x86/smm/smm.map - $(OBJCOPY_smm) -O binary $(obj)/cpu/x86/smm/smm.elf $@ +$(obj)/smm/smm: $(obj)/smm/smm.o $(src)/cpu/x86/smm/smm.ld + $(LD_smm) $(LDFLAGS_smm) -o $(obj)/smm/smm.elf -T $(src)/cpu/x86/smm/smm.ld $(obj)/smm/smm.o + $(NM_smm) -n $(obj)/smm/smm.elf | sort > $(obj)/smm/smm.map + $(OBJCOPY_smm) -O binary $(obj)/smm/smm.elf $@ ifeq ($(CONFIG_HAVE_SMI_HANDLER),y) ramstage-srcs += $(obj)/cpu/x86/smm/smm.manual diff --git a/src/include/memlayout.h b/src/include/memlayout.h index 42d5608..e62782a 100644 --- a/src/include/memlayout.h +++ b/src/include/memlayout.h @@ -106,7 +106,7 @@ SET_COUNTER(bootblock, addr) \ _ = ASSERT(_eprogram - _program <= sz, \ STR(Bootblock exceeded its allotted size! (sz))); \ - INCLUDE "lib/program.bootblock.ld" + INCLUDE "bootblock/lib/program.ld" #else #define BOOTBLOCK(addr, sz) \ SET_COUNTER(bootblock, addr) \ @@ -118,7 +118,7 @@ SET_COUNTER(romstage, addr) \ _ = ASSERT(_eprogram - _program <= sz, \ STR(Romstage exceeded its allotted size! (sz))); \ - INCLUDE "lib/program.romstage.ld" + INCLUDE "romstage/lib/program.ld" #else #define ROMSTAGE(addr, sz) \ SET_COUNTER(romstage, addr) \ @@ -130,7 +130,7 @@ SET_COUNTER(ramstage, addr) \ _ = ASSERT(_eprogram - _program <= sz, \ STR(Ramstage exceeded its allotted size! (sz))); \ - INCLUDE "lib/program.ramstage.ld" + INCLUDE "ramstage/lib/program.ld" #else #define RAMSTAGE(addr, sz) \ SET_COUNTER(ramstage, addr) \ @@ -149,7 +149,7 @@ SET_COUNTER(verstage, addr) \ _ = ASSERT(_eprogram - _program <= sz, \ STR(Verstage exceeded its allotted size! (sz))); \ - INCLUDE "lib/program.verstage.ld" + INCLUDE "verstage/lib/program.ld" #define OVERLAP_VERSTAGE_ROMSTAGE(addr, size) VERSTAGE(addr, size) #else

1 0

Patch set updated for coreboot: libpayload: x86/arch: Implement basic CPUID functionality
by Alexandru Gagniuc 26 Jan '16

26 Jan '16

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13390 -gerrit commit da966d4d7dcce4a18ecc7bcddc4642f3f06a3ddf Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Tue Nov 24 16:23:28 2015 -0800 libpayload: x86/arch: Implement basic CPUID functionality This patch implements minimal cpuid functionality. The API and structure of the functions is kept consistent with coreboot's implementation. Change-Id: I6fbfbc3d1d040c02d4784afe6dc4397cff9fca64 Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> --- payloads/libpayload/include/x86/arch/cpuid.h | 121 +++++++++++++++++++++++++++ 1 file changed, 121 insertions(+) diff --git a/payloads/libpayload/include/x86/arch/cpuid.h b/payloads/libpayload/include/x86/arch/cpuid.h new file mode 100644 index 0000000..f3ee293 --- /dev/null +++ b/payloads/libpayload/include/x86/arch/cpuid.h @@ -0,0 +1,121 @@ +/* + * This file is part of the libpayload project. + * + * Copyright (C) 2015 Intel Corp. + * (Written by Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> for Intel Corp.) + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#ifndef _ARCH_X86_CPUID_H +#define _ARCH_X86_CPUID_H + +struct cpuid_result { + uint32_t eax; + uint32_t ebx; + uint32_t ecx; + uint32_t edx; +}; + +struct cpuid_fms { + uint16_t family; + uint8_t model; + uint8_t stepping; +}; + +static inline struct cpuid_result cpuid(uint32_t op_eax) +{ + struct cpuid_result res; + + __asm__ volatile( + "cpuid" + : "=a" (res.eax), "=b" (res.ebx), "=c" (res.ecx), "=d" (res.edx) + : "a" (op_eax) + ); + + return res; +} + +static inline uint32_t cpuid_eax(uint32_t op_eax) +{ + struct cpuid_result res = cpuid(op_eax); + + return res.eax; +} + +static inline uint32_t cpuid_ebx(uint32_t op_eax) +{ + struct cpuid_result res = cpuid(op_eax); + + return res.ebx; +} + +static inline uint32_t cpuid_ecx(uint32_t op_eax) +{ + struct cpuid_result res = cpuid(op_eax); + + return res.ecx; +} + +static inline uint32_t cpuid_edx(uint32_t op_eax) +{ + struct cpuid_result res = cpuid(op_eax); + + return res.edx; +} + +/** + * Extract the CPU family, model and stepping + * + * For details, see: + * Intel 64 and IA-32 Architectures Software Developer’s Manual + * Combined Volumes: 1, 2A, 2B, 2C, 3A, 3B, 3C and 3D + * Order Number: 325462-056US + * - Figure 3-6. Version Information Returned by CPUID in EAX + * pg. 3-190 Vol. 2A + * + * and + * + * AMD CPUID Specification + * Publication # 25481 Revision: 2.34 + * - CPUID Fn0000_0001_EAX Family, Model, Stepping Identifiers + * pg. 10 + */ +static inline struct cpuid_fms cpuid_get_fms(void) +{ + struct cpuid_fms fms; + const uint32_t eax = cpuid_eax(1); + + fms.family = (eax >> 8) & 0xf; + if (fms.family == 0xf) + fms.family += (eax >> 20) & 0xff; + + fms.model = ((eax >> 4) & 0xf); + if ((fms.family == 0xf) | (fms.family == 6)) + fms.model |= ((eax >> 16) & 0xf) << 4; + + fms.stepping = eax & 0xf; + + return fms; +} + +#endif /* _ARCH_X86_CPUID_H */

1 0

Patch set updated for coreboot: libpayload: x86/timer: Implement constant TSC based calibration
by Alexandru Gagniuc 26 Jan '16

26 Jan '16

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13391 -gerrit commit 8cd1ab462022e286e79b28473533befab35a32a9 Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Tue Nov 24 16:40:10 2015 -0800 libpayload: x86/timer: Implement constant TSC based calibration On certain SOCs, such as Apollolake, the 8254 timer is not present or not operational. On such systems, attempting to calibrate the TSC against the 8254 will hang the payload. The next best approach is to identify processors with a constant TSC rate, and determine the actual speed by reading model-specific registers. With this patch, filo can now succesfully load the filo shell on Appololalke RVP2 board. Change-Id: I863acbc015cf072fa007584ab1d4f4531f0a6d4f Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> --- payloads/libpayload/arch/x86/timer.c | 99 ++++++++++++++++++++++++++++++++++-- 1 file changed, 95 insertions(+), 4 deletions(-) diff --git a/payloads/libpayload/arch/x86/timer.c b/payloads/libpayload/arch/x86/timer.c index bf0c30a..d015dcc 100644 --- a/payloads/libpayload/arch/x86/timer.c +++ b/payloads/libpayload/arch/x86/timer.c @@ -33,20 +33,93 @@ */ #include <libpayload.h> +#include <arch/cpuid.h> #include <arch/rdtsc.h> +#include <arch/msr.h> +#define MSR_PLATFORM_INFO 0xce /** * @ingroup arch * Global variable containing the speed of the processor in KHz. */ uint32_t cpu_khz; -/** - * Calculate the speed of the processor for use in delays. +const char intel_cpuid_mfg_string[] = "GenuineIntel"; + +/* + * Certain Atom SOCs don't either don't have an 8254 timer (PIT), or coreboot + * disables the PIT. In these cases TSC calibration by PIT will hang. * - * @return The CPU speed in kHz. + * NOTE: This table and its associated helper functions can be extended to + * support a larger range of CPUs and access methods. This only includes tested + * CPUs. */ -unsigned int get_cpu_speed(void) +static const struct fsb_freq_descriptor { + uint8_t cpu_family; + uint8_t cpu_model; + unsigned int base_clock_khz; +} intel_freq_table[] = { + { 6, 0x5c, 100000 }, +}; + +static const struct fsb_freq_descriptor *get_cpu_freq_info(void) +{ + size_t i; + struct cpuid_fms fms = cpuid_get_fms(); + + for (i = 0; i < ARRAY_SIZE(intel_freq_table); i++) { + if ((intel_freq_table[i].cpu_family == fms.family) && + (intel_freq_table[i].cpu_model == fms.model)) { + return &intel_freq_table[i]; + } + } + + return NULL; +} + +static int is_intel_cpu(void) +{ + char id_string[12]; + struct cpuid_result res; + + /* Get manufacturer's ID string */ + res = cpuid(0); + memcpy(id_string + 0, &res.ebx, 4); + memcpy(id_string + 4, &res.edx, 4); + memcpy(id_string + 8, &res.ecx, 4); + + return !memcmp(intel_cpuid_mfg_string, id_string, 12); +} + +/* + * Get the speed of the processor's timestamp counter on supported CPUs + */ +static unsigned int get_cpu_speed_by_const_tsc(void) +{ + uint64_t msr; + uint32_t tsc_multiplier; + const struct fsb_freq_descriptor *freq_info; + + if (!is_intel_cpu()) + return 0; + + freq_info = get_cpu_freq_info(); + if (!freq_info) + return 0; + + msr = _rdmsr(MSR_PLATFORM_INFO); + tsc_multiplier = (msr >> 8) & 0xff; + + cpu_khz = (freq_info->base_clock_khz * tsc_multiplier); + return cpu_khz; +} + +/* + * Get the speed of the processor's timestamp counter by calibrating it + * against the 8254 programmable interval timer. + * This function waits 2 ms to get an accurate calibration. + */ +static unsigned int get_cpu_speed_by_8254_timer(void) { unsigned long long start, end; const uint32_t clock_rate = 1193182; // 1.193182 MHz @@ -76,3 +149,21 @@ unsigned int get_cpu_speed(void) return cpu_khz; } + +/** + * Calculate the speed of the processor for use in delays. + * + * @return The CPU speed in kHz. + */ +unsigned int get_cpu_speed(void) +{ + uint32_t tsc_rate_khz; + + tsc_rate_khz = get_cpu_speed_by_const_tsc(); + if (tsc_rate_khz) + return tsc_rate_khz; + + tsc_rate_khz = get_cpu_speed_by_8254_timer(); + + return tsc_rate_khz; +}

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Patch set updated for coreboot: drivers/intel/fsp2_0: Take cbmem overhead size as a parameter
by Alexandru Gagniuc 26 Jan '16

26 Jan '16

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13377 -gerrit commit bb2981d00f1477225b38f3cc926a40a355b87910 Author: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> Date: Mon Dec 7 15:42:54 2015 -0800 drivers/intel/fsp2_0: Take cbmem overhead size as a parameter FSP will reserve an area of memory at the top of usable RAM below 4GiB if asked. Rather than selecting the region's size in fsp_memory_init(), pass it as a parameter. This allows the caller to handle all the cbmem related logic, and removes the cbmem dependency from the FSP wrapper. Change-Id: I581b224ee83202732ae83a0f363f0bb717aae669 Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> --- src/drivers/intel/fsp2_0/include/fsp/api.h | 2 +- src/drivers/intel/fsp2_0/memory_init.c | 10 +++++----- src/soc/intel/apollolake/romstage/romstage.c | 2 +- 3 files changed, 7 insertions(+), 7 deletions(-) diff --git a/src/drivers/intel/fsp2_0/include/fsp/api.h b/src/drivers/intel/fsp2_0/include/fsp/api.h index 6d2efd8..08f5b57 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/api.h +++ b/src/drivers/intel/fsp2_0/include/fsp/api.h @@ -39,7 +39,7 @@ enum fsp_notify_phase { /* Main FSP stages */ -enum fsp_status fsp_memory_init(void **hob_list); +enum fsp_status fsp_memory_init(void **hob_list, size_t tolum_size); enum fsp_status fsp_silicon_init(void); enum fsp_status fsp_notify(enum fsp_notify_phase phase); diff --git a/src/drivers/intel/fsp2_0/memory_init.c b/src/drivers/intel/fsp2_0/memory_init.c index e9d6e42..84f6fe1 100644 --- a/src/drivers/intel/fsp2_0/memory_init.c +++ b/src/drivers/intel/fsp2_0/memory_init.c @@ -14,7 +14,6 @@ #include <arch/io.h> #include <arch/cpu.h> #include <console/console.h> -#include <cbmem.h> #include <fsp/api.h> #include <fsp/util.h> #include <string.h> @@ -58,7 +57,8 @@ void platform_fsp_memory_init_params_cb(struct MEMORY_INIT_UPD *memupd) } static enum fsp_status do_fsp_memory_init(void **hob_list_ptr, - struct fsp_header *hdr) + struct fsp_header *hdr, + size_t tolum_size) { enum fsp_status status; fsp_memory_init_fn fsp_raminit; @@ -74,7 +74,7 @@ static enum fsp_status do_fsp_memory_init(void **hob_list_ptr, memset(&rt_buffer, 0, sizeof(rt_buffer)); rt_buffer.upd_data_rgn = &raminit_upd; - rt_buffer.bootloader_tolum_size = cbmem_overhead_size(); + rt_buffer.bootloader_tolum_size = tolum_size; /* Get any board specific changes */ raminit_params.nvs_buffer = NULL; @@ -114,12 +114,12 @@ static void relocate_fit(void) memcpy((void*)CONFIG_FIT_CAR_ADDR, (void*)fit_loc, FIT_SIZE); } -enum fsp_status fsp_memory_init(void **hob_list) +enum fsp_status fsp_memory_init(void **hob_list, size_t tolum_size) { struct fsp_header hdr; if (fsp_load_binary(&hdr, "blobs/fsp-m.bin") != CB_SUCCESS) return FSP_NOT_FOUND; relocate_fit(); - return do_fsp_memory_init(hob_list, &hdr); + return do_fsp_memory_init(hob_list, &hdr, tolum_size); } diff --git a/src/soc/intel/apollolake/romstage/romstage.c b/src/soc/intel/apollolake/romstage/romstage.c index b1595e8..2a4b2ff 100644 --- a/src/soc/intel/apollolake/romstage/romstage.c +++ b/src/soc/intel/apollolake/romstage/romstage.c @@ -83,7 +83,7 @@ asmlinkage void* romstage_entry(void) soc_early_romstage_init(); - fsp_memory_init(&hob_list_ptr); + fsp_memory_init(&hob_list_ptr, cbmem_overhead_size()); fsp_find_reserved_memory(&fsp_mem, hob_list_ptr);

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Patch set updated for coreboot: drivers/intel/fsp2_0: Document the wrapper API
by Alexandru Gagniuc 26 Jan '16

26 Jan '16

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13378 -gerrit commit e3eceedbe3a781bb658d20696ddc990a5056330a Author: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> Date: Mon Dec 7 16:30:41 2015 -0800 drivers/intel/fsp2_0: Document the wrapper API The FSP 2.0 wrapper makes several assumptions about memory use and call order. Those have escaped undocumented... until now. Change-Id: I8ab0ced746ef884d9a686c5beb79252c0fa408e2 Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> --- src/drivers/intel/fsp2_0/include/fsp/api.h | 52 ++++++++++++++++++++++++++++++ 1 file changed, 52 insertions(+) diff --git a/src/drivers/intel/fsp2_0/include/fsp/api.h b/src/drivers/intel/fsp2_0/include/fsp/api.h index 08f5b57..11e29a0 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/api.h +++ b/src/drivers/intel/fsp2_0/include/fsp/api.h @@ -47,4 +47,56 @@ enum fsp_status fsp_notify(enum fsp_notify_phase phase); void platform_fsp_memory_init_params_cb(struct MEMORY_INIT_UPD *memupd); void platform_fsp_silicon_init_params_cb(struct SILICON_INIT_UPD *silupd); +/* + * # DOCUMENTATION: + * + * This file defines the interface between coreboot and the FSP 2.0 wrapper + * fsp_memory_init(), fsp_silicon_init(), and fsp_notify() are the main entry + * points and map 1:1 to the FSP entry points of the same name. + * + * ### fsp_memory_init(): + * - hob_list: retuns a pointer to the HOB storage area created by FSP + * - tolum_size: The size of the memory area below TSEG to reserve for + * use by coreboot + * + * This function is responsible for loading and executing the memory + * initialization code from the FSP-M binary. It expects this binary to reside + * in cbfs as "blobs/fsp-m.bin". + * + * The function takes two parameters, which are described below, but does not + * take in memory parameters as an argument. The memory parameters can be filled + * in with platform_fsp_memory_init_params_cb(). This is a weak callback symbol + * that fsp_memory_init() will call. + * + * FSP MemoryInit will "reserve" a memory area below TSEG for use by later FSP + * stages, and it expects that this memory area not be written. It can, however, + * leave an area of memory between TSEG and the fsp reserved region available + * for use by coreboot. The size of this area is specified by the "tolum_size" + * parameter. + * + * FSP returns information about the memory layout in a series of structures + * called hand-off-blocks (HOB). The "hob_list" output parameter will point to + * the start of the HOB list. The fsp reserved region will also be described by + * one of the HOBs. For more information on parsing these structures, see + * fsp/util.h + * + * + * ### fsp_silicon_init(): + * + * This function is responsible for loading and executing the silicon + * initialization code from the FSP-S binary. It expects this binary to reside + * in cbfs as "blobs/fsp-s.bin". + * + * Like fsp_memory_init(), it provides a callback to fill in FSP-specific + * parameters, via platform_fsp_silicon_init_params_cb(). + * + * + * ### fsp_notify(): + * - phase: Which FSP notification phase + * + * This function is responsible for loading and executing the notify code from + * the FSP-S binary. It expects that fsp_silicon_init() has already been called + * succesfully, and that the FSP-S binary is still loaded into memory. + */ + #endif /* _FSP2_0_API_H_ */

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coreboot-gerrit January 2016