coreboot-gerrit January 2016

coreboot-gerrit@coreboot.org

1 participants
2471 discussions

Patch set updated for coreboot: drivers/intel/fsp2_0: Update FspUpdVpd header and adjust wrapper code
by Alexandru Gagniuc 26 Jan '16

26 Jan '16

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13354 -gerrit commit dd0b067c961bd3c50ef98a9a87c1954b8267efaf Author: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> Date: Wed Nov 11 13:02:18 2015 -0800 drivers/intel/fsp2_0: Update FspUpdVpd header and adjust wrapper code As of this writing, the FSP2.0 ABI is not fully defined, and this is why wrapper code needs to be adjusted with this header update. Change-Id: I47a1e36a4a0481162976800950bc856094f25711 Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> --- src/drivers/intel/fsp2_0/include/fsp/FspUpdVpd.h | 361 +++++++++-------------- src/drivers/intel/fsp2_0/memory_init.c | 6 +- src/drivers/intel/fsp2_0/silicon_init.c | 5 +- 3 files changed, 142 insertions(+), 230 deletions(-) diff --git a/src/drivers/intel/fsp2_0/include/fsp/FspUpdVpd.h b/src/drivers/intel/fsp2_0/include/fsp/FspUpdVpd.h index bdd5999..b3e2b6b 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/FspUpdVpd.h +++ b/src/drivers/intel/fsp2_0/include/fsp/FspUpdVpd.h @@ -110,338 +110,253 @@ struct BL_GPIO_PAD_INIT { +#define FSP_TEMP_RAM_INIT_UPD_SIGNATURE 0x4450555F54505346 /* 'FSPT_UPD' */ +#define FSP_MEMORY_INIT_UPD_SIGNATURE 0x4450555F4D505346 /* 'FSPM_UPD' */ +#define FSP_SILICON_INIT_UPD_SIGNATURE 0x4450555F53505346 /* 'FSPS_UPD' */ + struct TEMP_RAM_INIT_UPD { -/** Offset 0x0020 +/** Offset 0x0000 **/ uint64_t Signature; -/** Offset 0x0028 +/** Offset 0x0008 **/ uint8_t Revision; -/** Offset 0x0029 +/** Offset 0x0009 **/ - uint8_t UnusedUpdSpace0[83]; -/** Offset 0x007C + uint8_t UnusedUpdSpace0[67]; +/** Offset 0x004C **/ uint32_t ReservedTempRamInitUpd; } __attribute__((packed)); struct MEMORY_INIT_UPD { -/** Offset 0x0080 +/** Offset 0x0000 **/ uint64_t Signature; -/** Offset 0x0088 +/** Offset 0x0008 **/ uint8_t Revision; -/** Offset 0x0089 +/** Offset 0x0009 **/ - uint8_t UnusedUpdSpace1[7]; -/** Offset 0x0090 + uint8_t UnusedUpdSpace0[23]; +/** Offset 0x0020 Debug Serial Port Base - Debug serial port resource base address, either I/O or MMIO base. + Debug serial port base address. This option will be used only when the 'Serial Port Debug Device' option is set to 'External Device'. **/ uint32_t SerialDebugPortAddress; -/** Offset 0x0094 +/** Offset 0x0024 Debug Serial Port Type - Debug serial port resource type. NONE means no serial port support. + 16550 compatible debug serial port resource type. NONE means no serial port support. **/ uint8_t SerialDebugPortType; -/** Offset 0x0095 +/** Offset 0x0025 Serial Port Debug Device - Select active serial port device. For SOC UART devices,'Debug Serial Port Base' options will be ignored. + Select active serial port device for debug. For SOC UART devices,'Debug Serial Port Base' options will be ignored. **/ uint8_t SerialDebugPortDevice; -/** Offset 0x0096 +/** Offset 0x0026 Debug Serial Port Stride Size - Debug serial port register map stride size. + Debug serial port register map stride size in bytes. **/ uint8_t SerialDebugPortStrideSize; -/** Offset 0x0097 +/** Offset 0x0027 **/ - uint8_t ReservedUpd1; -/** Offset 0x0098 - Memory FastBootSupport - MRC Fast Boot Support + uint8_t UnusedUpdSpace1; +/** Offset 0x0028 + Memory Fast Boot + Enable/Disable MRC fast boot support. **/ uint8_t MrcFastBoot; -/** Offset 0x0099 -**/ - uint8_t UnusedUpdSpace2[7]; -/** Offset 0x00A0 - Memory EccSupport - ECC Support -**/ - uint8_t EccSupport; -/** Offset 0x00A1 - Memory DdrFreqLimit - DDR Freq Limit -**/ - uint8_t DdrFreqLimit; -/** Offset 0x00A2 - Memory MaxTolud - MaxTolud -**/ - uint32_t MaxTolud; -/** Offset 0x00A6 - MrcDebugMsgLevel - Set MRC DebugMsg Level +/** Offset 0x0029 **/ - uint8_t MrcDebugMsgLevel; -/** Offset 0x00A7 + uint8_t UnusedUpdSpace2[103]; +/** Offset 0x0090 Integrated Graphics Device - Enable : Enable Integrated Graphics Device (IGD) when selected as the Primary Video Adaptor. Disable: Alwarys disable IGD + Enable : Enable Integrated Graphics Device (IGD) when selected as the Primary Video Adaptor. Disable: Always disable IGD. **/ uint8_t Igd; -/** Offset 0x00A8 +/** Offset 0x0091 DVMT Pre-Allocated - Select DVMT 5.0 Pre-Allocated (Fixed) Graphics Memory size used by the Internal Graphics Device + Select DVMT 5.0 Pre-Allocated (Fixed) Graphics Memory size used by the Internal Graphics Device. **/ uint8_t IgdDvmt50PreAlloc; -/** Offset 0x00A9 +/** Offset 0x0092 Aperture Size - Select the Aperture Size. + Select the Aperture Size used by the Internal Graphics Device. **/ uint8_t IgdApertureSize; -/** Offset 0x00AA +/** Offset 0x0093 GTT Size - Select the GTT Size. + Select the GTT Size used by the Internal Graphics Device. **/ uint8_t GTTSize; -/** Offset 0x00AB +/** Offset 0x0094 Primary Display Select which of IGD/PCI Graphics device should be Primary Display. **/ uint8_t PrimaryVideoAdaptor; -/** Offset 0x00AC +/** Offset 0x0095 + GT PM Support + Enable/Disable GT power management support. **/ uint8_t PmSupport; -/** Offset 0x00AD +/** Offset 0x0096 + RC6(Render Standby) + Enable/Disable render standby support. **/ uint8_t EnableRenderStandby; -/** Offset 0x00AE +/** Offset 0x0097 + PAVP Enable + Enable/Disable Protected Audio Visual Path (PAVP). **/ uint8_t PavpEnable; -/** Offset 0x00AF +/** Offset 0x0098 **/ - uint8_t SataEnable; -/** Offset 0x00B0 + uint8_t UnusedUpdSpace3[116]; +/** Offset 0x010C + OEM File Loading Address + Determine the memory base address to load a specified file from CSE file system after memory is available. +**/ + uint32_t ObbLoadingBase; +/** Offset 0x0110 + OEM file name to load + Specify a file name to load from CSE file system after memory is available. Empty indicates no file needs to be loaded. +**/ + uint8_t ObbFileName[16]; +/** Offset 0x0120 +**/ + uint8_t UnusedUpdSpace4[48]; +/** Offset 0x0150 + GPIO Table Pointer + GPIO table pointer to a BL_GPIO_PAD_INIT structure. +**/ + struct BL_GPIO_PAD_INIT* GpioPadInitTablePtr; +/** Offset 0x0154 +**/ + uint8_t UnusedUpdSpace5[56]; +/** Offset 0x018C +**/ + uint32_t ReservedMemoryInitUpd; +} __attribute__((packed)); + +struct SILICON_INIT_UPD { +/** Offset 0x0000 +**/ + uint64_t Signature; +/** Offset 0x0008 +**/ + uint8_t Revision; +/** Offset 0x0009 +**/ + uint8_t UnusedUpdSpace0[23]; +/** Offset 0x0020 + Enable SD controller + Enable/disable SD Card controller. +**/ + uint8_t SdcardEnabled; +/** Offset 0x0021 + Enable SDIO controller + Enable/disable SDIO controller. +**/ + uint8_t SdioEnabled; +/** Offset 0x0022 + Enable eMMC controller + Enable/disable eMMC controller. +**/ + uint8_t eMMCEnabled; +/** Offset 0x0023 +**/ + uint8_t UnusedUpdSpace1[93]; +/** Offset 0x0080 Enable SATA Enable/disable SATA controller. **/ uint8_t EnableSata; -/** Offset 0x00B1 +/** Offset 0x0081 SATA Mode Select SATA controller working mode. **/ uint8_t SataMode; -/** Offset 0x00B2 - Enable SATA - Enable/disable SATA controller. +/** Offset 0x0082 + Aggressive SATA LPM Support + Enable SOC to aggressively enter link power state for SATA. **/ uint8_t SataSalpSupport; -/** Offset 0x00B3 +/** Offset 0x0083 Enable SATA ports Enable/disable SATA ports. One byte for each port, byte0 for port0, byte1 for port1, and so on. **/ uint8_t SataPortsEnable[2]; -/** Offset 0x00B5 +/** Offset 0x0085 Enable SATA DEVSLP Feature Enable/disable SATA DEVSLP per port. 0 is disable, 1 is enable. One byte for each port, byte0 for port0, byte1 for port1, and so on. **/ uint8_t SataPortsDevSlp[2]; -/** Offset 0x00B7 +/** Offset 0x0087 Enable PCIE RP Enable/disable PCIE Root Ports. 0: disable, 1: enable. One byte for each port, byte0 for port1, byte1 for port2, and so on. **/ uint8_t PcieRpEnable[6]; -/** Offset 0x00BD +/** Offset 0x008D Configure CLKREQ Number - Configure Root Port CLKREQ Number if CLKREQ is supported. Each value in arrary can be between 0-6. One byte for each port, byte0 for port1, byte1 for port2, and so on. + Configure Root Port CLKREQ Number if CLKREQ is supported. Each value in array can be between 0-6. One byte for each port, byte0 for port1, byte1 for port2, and so on. **/ uint8_t PcieRpClkReqNumber[6]; -/** Offset 0x00C3 +/** Offset 0x0093 Enable USB2 ports Enable/disable per USB2 ports. One byte for each port, byte0 for port0, byte1 for port1, and so on. **/ uint8_t PortUsb20Enable[8]; -/** Offset 0x00CB +/** Offset 0x009B Enable USB3 ports Enable/disable per USB3 ports. One byte for each port, byte0 for port0, byte1 for port1, and so on. **/ uint8_t PortUsb30Enable[6]; -/** Offset 0x00D1 +/** Offset 0x00A1 Enable XHCI SSIC Eanble Enable/disable XHCI SSIC port. **/ uint8_t SsicPortEnable; -/** Offset 0x00D2 +/** Offset 0x00A2 Enable SMBus Enable/disable SMBus controller. **/ uint8_t SmbusEnable; -/** Offset 0x00D3 +/** Offset 0x00A3 **/ - uint8_t UnusedUpdSpace3[13]; -/** Offset 0x00E0 + uint8_t UnusedUpdSpace2[13]; +/** Offset 0x00B0 + ISP Enable/Disable + Enable/Disable ISP Device. **/ uint8_t IspEn; -/** Offset 0x00E1 -**/ - uint8_t IspAcpiMode; -/** Offset 0x00E2 -**/ - uint32_t AdditionalFvBase; -/** Offset 0x00E6 -**/ - uint8_t UnusedUpdSpace4[122]; -/** Offset 0x0160 -**/ - uint32_t ObbLoadingBase; -/** Offset 0x0164 -**/ - uint32_t ObbFlashBase; -/** Offset 0x0168 -**/ - uint32_t ObbFlashSize; -/** Offset 0x016C -**/ - uint8_t UnusedUpdSpace5[20]; -/** Offset 0x0180 -**/ - uint8_t ObbFileName[16]; -/** Offset 0x0190 -**/ - uint8_t UnusedUpdSpace6[48]; -/** Offset 0x01C0 -**/ - struct BL_GPIO_PAD_INIT* GpioPadInitTablePtr; -/** Offset 0x01C4 -**/ - uint8_t UnusedUpdSpace7[56]; -/** Offset 0x01FC -**/ - uint32_t ReservedMemoryInitUpd; -} __attribute__((packed)); - -struct SILICON_INIT_UPD { -/** Offset 0x0200 -**/ - uint64_t Signature; -/** Offset 0x0208 +/** Offset 0x00B1 **/ - uint8_t Revision; -/** Offset 0x0209 + uint8_t UnusedUpdSpace3[303]; +/** Offset 0x01E0 + BMP Logo Data Size + BMP logo data buffer size. **/ - uint8_t UnusedUpdSpace8[7]; -/** Offset 0x0210 - Logo Pointer - Points to PEI Display Logo Image + uint32_t LogoSize; +/** Offset 0x01E4 + BMP Logo Data Pointer + BMP logo data pointer to a BMP format buffer. **/ uint32_t LogoPtr; -/** Offset 0x0214 - Logo Size - Size of PEI Display Logo Image -**/ - uint32_t LogoSize; -/** Offset 0x0218 - Graphics Configuration Ptr - Points to VBT +/** Offset 0x01E8 + Graphics Configuration Data Pointer + Graphics configuration data used for initialization. **/ uint32_t GraphicsConfigPtr; -/** Offset 0x021C - Enable HD Audio DSP - Enable/disable HD Audio DSP feature. -**/ - uint8_t DspEnable; -/** Offset 0x021D - Select HDAudio IoBuffer Ownership - Select HDAudio IoBuffer Ownership. -**/ - uint8_t IoBufferOwnership; -/** Offset 0x021E - BXT PlatformType - BXT PlatformType. -**/ - uint8_t PlatformType; -/** Offset 0x021F - DynSR - Enable/disable DynSR feature. -**/ - uint8_t DynSR; -/** Offset 0x0220 +/** Offset 0x01EC **/ - uint8_t UnusedUpdSpace9[20]; -/** Offset 0x0234 + uint8_t UnusedUpdSpace4[12]; +/** Offset 0x01F8 **/ - uint8_t ReservedSiliconInitUpd[292]; -} __attribute__((packed)); - -#define FSP_UPD_SIGNATURE 0x2444505554584224 /* '$BXTUPD$' */ -#define FSP_TEMP_RAM_INIT_UPD_SIGNATURE 0x24445055504D5424 /* '$TMPUPD$' */ -#define FSP_MEMORY_INIT_UPD_SIGNATURE 0x244450554D454D24 /* '$MEMUPD$' */ -#define FSP_SILICON_INIT_UPD_SIGNATURE 0x244450555F495324 /* '$SI_UPD$' */ - -struct UPD_DATA_REGION { -/** Offset 0x0000 -**/ - uint64_t Signature; -/** Offset 0x0008 -**/ - uint8_t Revision; -/** Offset 0x0009 -**/ - uint8_t ReservedUpd0[7]; -/** Offset 0x0010 -**/ - uint32_t TempRamInitUpdOffset; -/** Offset 0x0014 -**/ - uint32_t MemoryInitUpdOffset; -/** Offset 0x0018 -**/ - uint32_t SiliconInitUpdOffset; -/** Offset 0x001C -**/ - uint32_t ReservedUpd1; -/** Offset 0x0020 -**/ - struct TEMP_RAM_INIT_UPD TempRamInitUpd; -/** Offset 0x0080 -**/ - struct MEMORY_INIT_UPD MemoryInitUpd; -/** Offset 0x0200 -**/ - struct SILICON_INIT_UPD SiliconInitUpd; -/** Offset 0x0358 -**/ - uint8_t UnusedUpdSpace10[166]; -/** Offset 0x03FE -**/ - uint16_t RegionTerminator; + uint32_t ReservedSiliconInitUpd; } __attribute__((packed)); #define FSP_IMAGE_ID 0x2450534654584224 /* '$BXTFSP$' */ -#define FSP_IMAGE_REV 0x01010000 - -struct VPD_DATA_REGION { -/** Offset 0x0000 -**/ - uint64_t PcdVpdRegionSign; -/** Offset 0x0008 - PcdImageRevision -**/ - uint32_t PcdImageRevision; -/** Offset 0x000C -**/ - uint32_t PcdUpdRegionOffset; -/** Offset 0x0010 -**/ - uint32_t PcdUpdRegionSize; -/** Offset 0x0014 -**/ - uint64_t UnusedVpdSpace0; -/** Offset 0x001C -**/ - uint32_t PcdVpdReserved; -} __attribute__((packed)); +#define FSP_IMAGE_REV 0x00060000 #endif diff --git a/src/drivers/intel/fsp2_0/memory_init.c b/src/drivers/intel/fsp2_0/memory_init.c index 92c30b4..4ac720d 100644 --- a/src/drivers/intel/fsp2_0/memory_init.c +++ b/src/drivers/intel/fsp2_0/memory_init.c @@ -41,7 +41,6 @@ typedef asmlinkage enum fsp_status (*fsp_memory_init_fn) static void fill_console_params(struct MEMORY_INIT_UPD *memupd) { - /* TODO: Check that FSP actually respects these flags */ if (IS_ENABLED(CONFIG_CONSOLE_SERIAL)) { memupd->SerialDebugPortDevice = CONFIG_UART_FOR_CONSOLE; memupd->SerialDebugPortType = 2; @@ -65,12 +64,11 @@ static enum fsp_status do_fsp_memory_init(void **hob_list_ptr, fsp_memory_init_fn fsp_raminit; struct fsp_memory_init_params raminit_params; struct fsp_init_rt_common_buffer rt_buffer; - struct MEMORY_INIT_UPD raminit_upd; - struct UPD_DATA_REGION *upd_region; + struct MEMORY_INIT_UPD raminit_upd, *upd_region; post_code(0x34); upd_region = (void*)(hdr->cfg_region_offset + hdr->image_base); - memcpy(&raminit_upd, upd_region, sizeof(raminit_upd)); + raminit_upd = *upd_region; /* Zero fill RT Buffer data and start populating fields. */ memset(&rt_buffer, 0, sizeof(rt_buffer)); diff --git a/src/drivers/intel/fsp2_0/silicon_init.c b/src/drivers/intel/fsp2_0/silicon_init.c index a6011c9..d600635 100644 --- a/src/drivers/intel/fsp2_0/silicon_init.c +++ b/src/drivers/intel/fsp2_0/silicon_init.c @@ -22,15 +22,14 @@ typedef asmlinkage enum fsp_status (*fsp_silicon_init_fn) static enum fsp_status do_silicon_init(struct fsp_header *hdr) { - struct SILICON_INIT_UPD silicon_upd; + struct SILICON_INIT_UPD silicon_upd, *upd_region; fsp_silicon_init_fn silicon_init; - void *upd_region; enum fsp_status status; upd_region = (void*)(hdr->cfg_region_offset + hdr->image_base); /* populate upd with defaults */ - memcpy(&silicon_upd, upd_region, sizeof(silicon_upd)); + silicon_upd = *upd_region; silicon_init = (void *)(hdr->image_base + hdr->silicon_init_entry_offset);

1 0

Patch set updated for coreboot: soc/intel/apollolake: Fill ACPI FADT table
by Alexandru Gagniuc 26 Jan '16

26 Jan '16

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13352 -gerrit commit 48c2bdb6b9e4b2728c547fbe8db8fa404585851b Author: Lance Zhao <lijian.zhao(a)intel.com> Date: Tue Nov 10 19:00:18 2015 -0800 soc/intel/apollolake: Fill ACPI FADT table Fill the ACPI FADT table base on apollolake SOC definition. Change-Id: Ib7226a3b130f14810dc2af5ca484cef58f477063 Signed-off-by: Lance Zhao <lijian.zhao(a)intel.com> --- src/soc/intel/apollolake/acpi.c | 73 ++++++++++++++++++++++++++++- src/soc/intel/apollolake/include/soc/acpi.h | 21 +++++++++ src/soc/intel/apollolake/include/soc/pm.h | 32 +++++++++++++ 3 files changed, 124 insertions(+), 2 deletions(-) diff --git a/src/soc/intel/apollolake/acpi.c b/src/soc/intel/apollolake/acpi.c index 4246f40..9be1705 100644 --- a/src/soc/intel/apollolake/acpi.c +++ b/src/soc/intel/apollolake/acpi.c @@ -11,12 +11,81 @@ */ #include <arch/acpi.h> +#include <cpu/x86/smm.h> +#include <soc/acpi.h> +#include <soc/iomap.h> +#include <soc/pm.h> + unsigned long acpi_fill_mcfg(unsigned long current) { - return 0; + return current; } + unsigned long acpi_fill_madt(unsigned long current) { - return 0; + return current; +} + +static int acpi_sci_irq(void) +{ + int sci_irq = 9; + return sci_irq; } +void soc_fill_common_fadt(acpi_fadt_t * fadt) +{ + const uint16_t pmbase = ACPI_PMIO_BASE; + + fadt->sci_int = acpi_sci_irq(); + fadt->smi_cmd = APM_CNT; + fadt->acpi_enable = APM_CNT_ACPI_ENABLE; + fadt->acpi_disable = APM_CNT_ACPI_DISABLE; + + fadt->pm1a_evt_blk = pmbase + PM1_STS; + fadt->pm1a_cnt_blk = pmbase + PM1_CNT; + fadt->pm_tmr_blk = pmbase + PM1_TMR; + fadt->gpe0_blk = pmbase + GPE0_STS(0); + + fadt->pm1_evt_len = 4; + fadt->pm1_cnt_len = 2; + fadt->pm_tmr_len = 4; + /* There are 4 GPE0 STS/EN pairs each 32 bits wide. */ + fadt->gpe0_blk_len = 2 * GPE0_REG_MAX * sizeof(uint32_t); + fadt->p_lvl2_lat = 0x65; + fadt->p_lvl3_lat = 0x3E9; + fadt->flush_size = 0x400; + fadt->flush_stride = 0x10; + fadt->duty_offset = 1; + fadt->duty_width = 3; + fadt->day_alrm = 0xd; + fadt->century = 0x32; + fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042; + + fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED | + ACPI_FADT_C2_MP_SUPPORTED | ACPI_FADT_SLEEP_BUTTON | + ACPI_FADT_RESET_REGISTER | ACPI_FADT_SEALED_CASE | + ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_PLATFORM_CLOCK; + + fadt->reset_reg.space_id = 1; + fadt->reset_reg.bit_width = 8; + fadt->reset_reg.addrl = 0xcf9; + fadt->reset_value = 6; + + fadt->x_pm1a_evt_blk.space_id = 1; + fadt->x_pm1a_evt_blk.bit_width = fadt->pm1_evt_len * 8; + fadt->x_pm1a_evt_blk.addrl = pmbase + PM1_STS; + + fadt->x_pm1b_evt_blk.space_id = 1; + + fadt->x_pm1a_cnt_blk.space_id = 1; + fadt->x_pm1a_cnt_blk.bit_width = fadt->pm1_cnt_len * 8; + fadt->x_pm1a_cnt_blk.addrl = pmbase + PM1_CNT; + + fadt->x_pm1b_cnt_blk.space_id = 1; + + fadt->x_pm_tmr_blk.space_id = 1; + fadt->x_pm_tmr_blk.bit_width = fadt->pm_tmr_len * 8; + fadt->x_pm_tmr_blk.addrl = pmbase + PM1_TMR; + + fadt->x_gpe1_blk.space_id = 1; +} diff --git a/src/soc/intel/apollolake/include/soc/acpi.h b/src/soc/intel/apollolake/include/soc/acpi.h new file mode 100644 index 0000000..7e112d7 --- /dev/null +++ b/src/soc/intel/apollolake/include/soc/acpi.h @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * (Written by Lance Zhao <lijian.zhao(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef _SOC_APOLLOLAKE_ACPI_H_ +#define _SOC_APOLLOLAKE_ACPI_H_ + +#include <arch/acpi.h> + +/* Zero value won't be programmed again in FADT table. */ +void soc_fill_common_fadt(acpi_fadt_t * fadt); + +#endif /* _SOC_APOLLOLAKE_ACPI_H_ */ diff --git a/src/soc/intel/apollolake/include/soc/pm.h b/src/soc/intel/apollolake/include/soc/pm.h new file mode 100644 index 0000000..5a3ac96 --- /dev/null +++ b/src/soc/intel/apollolake/include/soc/pm.h @@ -0,0 +1,32 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * (Written by Lance Zhao <lijian.zhao(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef _SOC_APOLLOLAKE_PM_H_ +#define _SOC_APOLLOLAKE_PM_H_ + +/* ACPI_BASE_ADDRESS / PMBASE */ + +#define PM1_STS 0x00 +#define PM1_EN 0x02 +#define PM1_CNT 0x04 +#define PM1_TMR 0x08 +#define SMI_EN 0x40 +#define SMI_STS 0x44 +#define GPE_CNTL 0x50 +#define DEVACT_STS 0x4c + +#define GPE0_REG_MAX 4 +#define GPE0_REG_SIZE 32 +#define GPE0_STS(x) (0x20 + (x * 4)) +#define GPE0_EN(x) (0x30 + (x * 4)) + +#endif

1 0

Patch set updated for coreboot: src/mainboard/intel/apollolake_rvp: Include FADT tables
by Alexandru Gagniuc 26 Jan '16

26 Jan '16

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13353 -gerrit commit 734f5c8458e7d5494cec37d3a30424f0d534ac5b Author: Lance Zhao <lijian.zhao(a)intel.com> Date: Wed Nov 11 15:14:29 2015 -0800 src/mainboard/intel/apollolake_rvp: Include FADT tables Include SOC specific FADT tables to current mainboard. Change-Id: Id4099528657304e9f7675c839e7666c58f189004 Signed-off-by: Lance Zhao <lijian.zhao(a)intel.com> --- src/mainboard/intel/apollolake_rvp/acpi_tables.c | 28 ++++++++++++++++++++++-- 1 file changed, 26 insertions(+), 2 deletions(-) diff --git a/src/mainboard/intel/apollolake_rvp/acpi_tables.c b/src/mainboard/intel/apollolake_rvp/acpi_tables.c index d21b743..c4910ea 100644 --- a/src/mainboard/intel/apollolake_rvp/acpi_tables.c +++ b/src/mainboard/intel/apollolake_rvp/acpi_tables.c @@ -10,9 +10,33 @@ * (at your option) any later version. */ -#include <arch/acpi.h> +#include <string.h> +#include <soc/acpi.h> void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt) { -} + acpi_header_t *header = &(fadt->header); + + memset(fadt, 0, sizeof(acpi_fadt_t)); + memcpy(header->signature, "FACP", 4); + header->length = sizeof(acpi_fadt_t); + header->revision = 5; + memcpy(header->oem_id, OEM_ID, 6); + memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); + memcpy(header->asl_compiler_id, ASLC, 4); + header->asl_compiler_revision = 1; + + fadt->firmware_ctrl = (uintptr_t)facs; + fadt->dsdt = (uintptr_t)dsdt; + fadt->model = 1; + fadt->preferred_pm_profile = PM_MOBILE; + fadt->x_firmware_ctl_l = (uintptr_t)facs; + fadt->x_firmware_ctl_h = 0; + fadt->x_dsdt_l = (uintptr_t)dsdt; + fadt->x_dsdt_h = 0; + + soc_fill_common_fadt(fadt); + + header->checksum = acpi_checksum((void *)fadt, header->length); +}

1 0

Patch set updated for coreboot: drivers/intel/fsp2_0: Define tentative coreboot <-> FSP 2.0 API
by Alexandru Gagniuc 26 Jan '16

26 Jan '16

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13335 -gerrit commit d2533c99e44a8ae10127847b531421876bd68a99 Author: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> Date: Thu Oct 29 17:48:14 2015 -0700 drivers/intel/fsp2_0: Define tentative coreboot <-> FSP 2.0 API This defines the initial API between coreboot and FSP 2.0. The design attempts to abstract from the common code as much of the FSP details as possible. Change-Id: I57f629eecb259cbe10c489d5dae56afe260b5197 Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> --- src/drivers/intel/fsp2_0/include/fsp/api.h | 43 ++++++++++++++++++++++++++++++ 1 file changed, 43 insertions(+) diff --git a/src/drivers/intel/fsp2_0/include/fsp/api.h b/src/drivers/intel/fsp2_0/include/fsp/api.h new file mode 100644 index 0000000..75dcffe --- /dev/null +++ b/src/drivers/intel/fsp2_0/include/fsp/api.h @@ -0,0 +1,43 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * (Written by Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef _FSP2_0_API_H_ +#define _FSP2_0_API_H_ + +#include "FspUpdVpd.h" + +enum fsp_status { + FSP_SUCCESS = 0x00000000, + FSP_INVALID_PARAMETER = 0x80000002, + FSP_UNSUPPORTED = 0x80000003, + FSP_NOT_READY = 0x80000006, + FSP_DEVICE_ERROR = 0x80000007, + FSP_OUT_OF_RESOURCES = 0x80000009, + FSP_VOLUME_CORRUPTED = 0x8000000a, + FSP_NOT_FOUND = 0x8000000a, + FSP_TIMEOUT = 0x80000012, + FSP_ABORTED = 0x80000015, + FSP_INCOMPATIBLE_VERSION = 0x80000010, + FSP_SECURITY_VIOLATION = 0x8000001a, + FSP_CRC_ERROR = 0x8000001b, +}; + +/* Main FSP stages */ +enum fsp_status fsp_memory_init(void); +enum fsp_status fsp_silicon_init(void); +enum fsp_status fsp_notify(void); + +/* Callbacks for updating stage-specific parameters */ +void platform_fsp_memory_init_params_cb(struct MEMORY_INIT_UPD *memupd); +void platform_fsp_silicon_init_params_cb(struct SILICON_INIT_UPD *silupd); + +#endif /* _FSP2_0_API_H_ */

1 0

Patch set updated for coreboot: drivers/intel/fsp2_0: Fix build warning for FSP header printing
by Alexandru Gagniuc 26 Jan '16

26 Jan '16

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13334 -gerrit commit c224b8482f2542c7014df356ae758ba7b929241b Author: Lance Zhao <lijian.zhao(a)intel.com> Date: Wed Nov 4 11:37:40 2015 -0800 drivers/intel/fsp2_0: Fix build warning for FSP header printing Debug print change the print type of image_base from size_t to uintptr_t Change-Id: I911ea9f37c7c6f8e7ecd79bef9ebf68a8960788f Signed-off-by: Lance Zhao <lijian.zhao(a)intel.com> --- src/drivers/intel/fsp2_0/util.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/drivers/intel/fsp2_0/util.c b/src/drivers/intel/fsp2_0/util.c index 4e1dbf3..e1b77a8 100644 --- a/src/drivers/intel/fsp2_0/util.c +++ b/src/drivers/intel/fsp2_0/util.c @@ -56,7 +56,7 @@ enum cb_err fsp_identify(struct fsp_header *hdr, const void *fsp_blob) void fsp_print_header_info(const struct fsp_header *hdr) { - printk(BIOS_DEBUG, "Revision %u, image ID: %s, base 0x%zx + 0x%zx\n", + printk(BIOS_DEBUG, "Revision %u, image ID: %s, base 0x%lx + 0x%zx\n", hdr->revision ,hdr->image_id, hdr->image_base, hdr->image_size); printk(BIOS_DEBUG, "\tConfig region 0x%zx + 0x%zx\n",

1 0

Patch set updated for coreboot: soc/apollolake: Add CPU driver skeleton
by Alexandru Gagniuc 26 Jan '16

26 Jan '16

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13344 -gerrit commit 57cab225d43774fa56b88b51e0229521fd58c672 Author: Andrey Petrov <andrey.petrov(a)intel.com> Date: Wed Nov 4 18:06:04 2015 -0800 soc/apollolake: Add CPU driver skeleton Change-Id: Ib0a4503f9b9d1ba3a4138e4cbd91e80a4de1e607 Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> --- src/soc/intel/apollolake/Makefile.inc | 1 + src/soc/intel/apollolake/cpu.c | 34 ++++++++++++++++++++++++++++++ src/soc/intel/apollolake/include/soc/cpu.h | 2 ++ 3 files changed, 37 insertions(+) diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc index ca81304..59d13e3 100644 --- a/src/soc/intel/apollolake/Makefile.inc +++ b/src/soc/intel/apollolake/Makefile.inc @@ -24,6 +24,7 @@ romstage-y += tsc_freq.c romstage-y += uart_early.c ramstage-y += chip.c +ramstage-y += cpu.c ramstage-y += gpio.c ramstage-y += memmap.c ramstage-y += mmap_boot.c diff --git a/src/soc/intel/apollolake/cpu.c b/src/soc/intel/apollolake/cpu.c new file mode 100644 index 0000000..8f3ccb3 --- /dev/null +++ b/src/soc/intel/apollolake/cpu.c @@ -0,0 +1,34 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * (Written by Andrey Petrov <andrey.petrov(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include <cpu/cpu.h> +#include <device/device.h> +#include <device/pci.h> +#include <soc/cpu.h> + +static void cpu_core_init(device_t cpu) +{ +} + +static struct device_operations cpu_dev_ops = { + .init = cpu_core_init, +}; + +static struct cpu_device_id cpu_table[] = { + { X86_VENDOR_INTEL, CPUID_APOLLOLAKE_A0 }, + { 0, 0 }, +}; + +static const struct cpu_driver driver __cpu_driver = { + .ops = &cpu_dev_ops, + .id_table = cpu_table, +}; diff --git a/src/soc/intel/apollolake/include/soc/cpu.h b/src/soc/intel/apollolake/include/soc/cpu.h index 9c32e8e..1e827b7 100644 --- a/src/soc/intel/apollolake/include/soc/cpu.h +++ b/src/soc/intel/apollolake/include/soc/cpu.h @@ -15,6 +15,8 @@ #include <cpu/x86/msr.h> +#define CPUID_APOLLOLAKE_A0 0x506c8 + #define MSR_PLATFORM_INFO 0xce #define BASE_CLOCK_MHZ 100

1 0

Patch set updated for coreboot: soc/apollolake: Implement post-raminit romstage and ramstage entry
by Alexandru Gagniuc 26 Jan '16

26 Jan '16

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13341 -gerrit commit af790f746fc5ebb6d24e956404698dbf935f0c74 Author: Andrey Petrov <andrey.petrov(a)intel.com> Date: Mon Nov 2 15:18:34 2015 -0800 soc/apollolake: Implement post-raminit romstage and ramstage entry In order to decompress ramstage, romstage needs significantly larger stack than originally set up. To do this, we switch the stack to memory right after raminit is done. The new stack is allocated in a fashion similar to other soc platforms, by reserving it in CBMEM. Change-Id: I068c283a90f318ce9ee2ad370c3fc2ccb1f8a746 Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> --- src/soc/intel/apollolake/Kconfig | 10 ++++++++ src/soc/intel/apollolake/include/soc/romstage.h | 3 ++- src/soc/intel/apollolake/romstage/entry.inc | 13 ++++++++++ src/soc/intel/apollolake/romstage/romstage.c | 33 ++++++++++++++++++++++--- 4 files changed, 54 insertions(+), 5 deletions(-) diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index 8bc7ad4..eb9bd79 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -72,6 +72,16 @@ config DCACHE_RAM_BOOTBLOCK_STACK_SIZE The amount of anticipated stack usage from the bootblock during pre-romstage initialization. +config ROMSTAGE_RAM_STACK_SIZE + hex + default 0x5000 + help + The size of the romstage stack after memory is available. Because CAR + space is very crowded, only a very limited part of CAR is available + for stack. More than that is needed to decompress ramstage. This + variable indicates how much RAM to reserve for the stack after + raminit. The stack is automatically switched after romstage_main(). + config IFD_BIOS_START hex default 0x1000 diff --git a/src/soc/intel/apollolake/include/soc/romstage.h b/src/soc/intel/apollolake/include/soc/romstage.h index f57f26d..eb69558 100644 --- a/src/soc/intel/apollolake/include/soc/romstage.h +++ b/src/soc/intel/apollolake/include/soc/romstage.h @@ -15,6 +15,7 @@ #include <arch/cpu.h> -asmlinkage void romstage_entry(void); +asmlinkage void *romstage_entry(void); +asmlinkage void romstage_after_raminit(void); #endif /* _SOC_APOLLOLAKE_ROMSTAGE_H_ */ diff --git a/src/soc/intel/apollolake/romstage/entry.inc b/src/soc/intel/apollolake/romstage/entry.inc index b04e17e..8c0670c 100644 --- a/src/soc/intel/apollolake/romstage/entry.inc +++ b/src/soc/intel/apollolake/romstage/entry.inc @@ -19,3 +19,16 @@ apollolake_entry: mov esp, (CONFIG_DCACHE_RAM_BASE + 0x4000) call romstage_entry + + /* + * eax contains pointer to a region in RAM that we've been given the go + * ahead to use as stack. The old stack is empty at this point, so we + * don't have to relocate anything. + */ + mov esp, eax + + /* + * TODO: set up temporary cache for RAM + * We can't tear down CAR yet because romstage resides in CAR. + */ + call romstage_after_raminit diff --git a/src/soc/intel/apollolake/romstage/romstage.c b/src/soc/intel/apollolake/romstage/romstage.c index 99953fd..6efbdd5 100644 --- a/src/soc/intel/apollolake/romstage/romstage.c +++ b/src/soc/intel/apollolake/romstage/romstage.c @@ -12,6 +12,8 @@ */ #include <arch/io.h> +#include <cbfs.h> +#include <cbmem.h> #include <console/console.h> #include <cpu/x86/msr.h> #include <device/pci_def.h> @@ -50,7 +52,26 @@ static void soc_early_romstage_init(void) pci_write_config32(PCI_DEV(0, 13, 0), 0x60, 1<<7); } -asmlinkage void romstage_entry(void) +static void *alloc_stack_in_ram(void) +{ + uint8_t *ram_stack = cbmem_add(CBMEM_ID_ROMSTAGE_RAM_STACK, + CONFIG_ROMSTAGE_RAM_STACK_SIZE); + + /* + * If cbmem fails to give us a memory window, try to get a stack at + * 2 MiB, and hope we can go forward. The 2 MiB address is arbitrary. + */ + if (ram_stack == NULL) { + printk(BIOS_ALERT, "Could not find place for stack\n"); + return (void *)(2 * MiB); + } + + /* The initial stack pointer should point at the top of the region */ + ram_stack += CONFIG_ROMSTAGE_RAM_STACK_SIZE - sizeof(size_t); + return ram_stack; +} + +asmlinkage void* romstage_entry(void) { /* Be careful. Bootblock might already have initialized the console */ if (!IS_ENABLED(CONFIG_BOOTBLOCK_CONSOLE)) { @@ -64,7 +85,11 @@ asmlinkage void romstage_entry(void) fsp_memory_init(); - /* This function must not return */ - while(1) - ; + cbmem_initialize_empty(); + return alloc_stack_in_ram(); +} + +asmlinkage void romstage_after_raminit(void) +{ + run_ramstage(); }

1 0

Patch set updated for coreboot: soc/apollolake: Call into FSP memory init
by Alexandru Gagniuc 26 Jan '16

26 Jan '16

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13340 -gerrit commit ec7d5f0b23a4be285e5743f88c2cadaa625d02ff Author: Andrey Petrov <andrey.petrov(a)intel.com> Date: Wed Oct 28 13:02:59 2015 -0700 soc/apollolake: Call into FSP memory init This is suficient to initialize memory as long as the UPD in the FSP binary matched the platform. A mechanism to provide platform-specific UPD data is not implemented in this patch. Change-Id: Ib500095ed5b73174f74e72a372529b095c4f8411 Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> --- src/soc/intel/apollolake/romstage/romstage.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/soc/intel/apollolake/romstage/romstage.c b/src/soc/intel/apollolake/romstage/romstage.c index 2cbf4a9..99953fd 100644 --- a/src/soc/intel/apollolake/romstage/romstage.c +++ b/src/soc/intel/apollolake/romstage/romstage.c @@ -15,6 +15,7 @@ #include <console/console.h> #include <cpu/x86/msr.h> #include <device/pci_def.h> +#include <fsp/api.h> #include <soc/iomap.h> #include <soc/romstage.h> #include <soc/uart.h> @@ -61,6 +62,8 @@ asmlinkage void romstage_entry(void) soc_early_romstage_init(); + fsp_memory_init(); + /* This function must not return */ while(1) ;

1 0

Patch set updated for coreboot: soc/apollolake: Rename cpu.c to tsc_freq.c, add copyright header
by Alexandru Gagniuc 26 Jan '16

26 Jan '16

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13343 -gerrit commit 7bf063658166e8ff274ea1b7e6861b010be3b329 Author: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> Date: Thu Nov 5 11:14:51 2015 -0800 soc/apollolake: Rename cpu.c to tsc_freq.c, add copyright header To be consistent with other platforms, cpu.c should contain the ramstage CPU drivers. Since other Intel SOCs use tsc_freq.c for the same purpose we used cpu.c, rename it accordingly. Change-Id: I4ce6d9d9b37cc28d3cd74f7dd795718a07c6e8d4 Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> --- src/soc/intel/apollolake/Makefile.inc | 6 +++--- src/soc/intel/apollolake/cpu.c | 9 --------- src/soc/intel/apollolake/tsc_freq.c | 21 +++++++++++++++++++++ 3 files changed, 24 insertions(+), 12 deletions(-) diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc index 63c39b3..ca81304 100644 --- a/src/soc/intel/apollolake/Makefile.inc +++ b/src/soc/intel/apollolake/Makefile.inc @@ -8,26 +8,26 @@ subdirs-y += ../../../cpu/x86/smm subdirs-y += ../../../cpu/x86/tsc bootblock-y += bootblock/bootblock_car.c -bootblock-y += cpu.c bootblock-y += gpio.c bootblock-y += bootblock/cache_as_ram.S bootblock-y += bootblock/early_chipset_config.S bootblock-y += mmap_boot.c +bootblock-y += tsc_freq.c bootblock-y += uart_early.c cpu_incs-y += $(src)/soc/intel/apollolake/romstage/entry.inc -romstage-y += cpu.c romstage-y += gpio.c romstage-y += memmap.c romstage-y += mmap_boot.c romstage-y += romstage/romstage.c +romstage-y += tsc_freq.c romstage-y += uart_early.c ramstage-y += chip.c -ramstage-y += cpu.c ramstage-y += gpio.c ramstage-y += memmap.c ramstage-y += mmap_boot.c +ramstage-y += tsc_freq.c ramstage-y += uart.c romstage-y += placeholders.c diff --git a/src/soc/intel/apollolake/cpu.c b/src/soc/intel/apollolake/cpu.c deleted file mode 100644 index e804697..0000000 --- a/src/soc/intel/apollolake/cpu.c +++ /dev/null @@ -1,9 +0,0 @@ -#include <cpu/x86/msr.h> -#include <cpu/x86/tsc.h> -#include <soc/cpu.h> - -unsigned long tsc_freq_mhz(void) -{ - msr_t msr = rdmsr(MSR_PLATFORM_INFO); - return (BASE_CLOCK_MHZ * ((msr.lo >> 8) & 0xff)); -} diff --git a/src/soc/intel/apollolake/tsc_freq.c b/src/soc/intel/apollolake/tsc_freq.c new file mode 100644 index 0000000..2e90ef2 --- /dev/null +++ b/src/soc/intel/apollolake/tsc_freq.c @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * (Written by Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include <cpu/x86/msr.h> +#include <cpu/x86/tsc.h> +#include <soc/cpu.h> + +unsigned long tsc_freq_mhz(void) +{ + msr_t msr = rdmsr(MSR_PLATFORM_INFO); + return (BASE_CLOCK_MHZ * ((msr.lo >> 8) & 0xff)); +}

1 0

Patch set updated for coreboot: soc/apollolake: Add chip_operations structure to enable bus scans
by Alexandru Gagniuc 26 Jan '16

26 Jan '16

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13342 -gerrit commit 23a9dc12ab34bcf2f0af952bc18fed618a89c8bb Author: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> Date: Wed Nov 4 16:25:47 2015 -0800 soc/apollolake: Add chip_operations structure to enable bus scans With the chip_operations structure in place, PCI enumeration now works in ramstage. Change-Id: I9a39f4d6d7233a9cc696c71e96e0c17d4db3c925 Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> --- src/soc/intel/apollolake/Makefile.inc | 1 + src/soc/intel/apollolake/chip.c | 52 +++++++++++++++++++++++++++++++++++ 2 files changed, 53 insertions(+) diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc index 7cddf5a..63c39b3 100644 --- a/src/soc/intel/apollolake/Makefile.inc +++ b/src/soc/intel/apollolake/Makefile.inc @@ -23,6 +23,7 @@ romstage-y += mmap_boot.c romstage-y += romstage/romstage.c romstage-y += uart_early.c +ramstage-y += chip.c ramstage-y += cpu.c ramstage-y += gpio.c ramstage-y += memmap.c diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c new file mode 100644 index 0000000..2b6384a --- /dev/null +++ b/src/soc/intel/apollolake/chip.c @@ -0,0 +1,52 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * (Written by Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include <cpu/cpu.h> +#include <device/device.h> +#include <device/pci.h> + +static struct device_operations pci_domain_ops = { + .read_resources = pci_domain_read_resources, + .set_resources = DEVICE_NOOP, + .enable_resources = NULL, + .init = NULL, + .scan_bus = pci_domain_scan_bus, + .ops_pci_bus = pci_bus_default_ops, +}; + +static void cpu_bus_init(device_t dev) +{ + initialize_cpus(dev->link_list); +} + +static struct device_operations cpu_bus_ops = { + .read_resources = DEVICE_NOOP, + .set_resources = DEVICE_NOOP, + .enable_resources = DEVICE_NOOP, + .init = cpu_bus_init, + .scan_bus = 0, +}; + +static void enable_dev(device_t dev) +{ + /* Set the operations if it is a special bus type */ + if (dev->path.type == DEVICE_PATH_DOMAIN) { + dev->ops = &pci_domain_ops; + } else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) { + dev->ops = &cpu_bus_ops; + } +} + +struct chip_operations soc_intel_apollolake_ops = { + CHIP_NAME("Intel Apollolake SOC") + .enable_dev = &enable_dev, +};

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit January 2016