coreboot-gerrit January 2016

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Patch set updated for coreboot: drivers/intel: Add FSP 2.0 skeleton infrastructure
by Alexandru Gagniuc 26 Jan '16

26 Jan '16

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13328 -gerrit commit 4972bb9b578d518bd39438865963e9d27a0d51f7 Author: Andrey Petrov <andrey.petrov(a)intel.com> Date: Tue Oct 27 16:27:26 2015 -0700 drivers/intel: Add FSP 2.0 skeleton infrastructure Change-Id: If5bea40112ef40eb54aa37e2880fe70075f9e02b Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> --- src/drivers/intel/Kconfig | 1 + src/drivers/intel/Makefile.inc | 1 + src/drivers/intel/fsp2_0/Kconfig | 56 +++++++++++++++++++++++++++++++++++ src/drivers/intel/fsp2_0/Makefile.inc | 10 +++++++ 4 files changed, 68 insertions(+) diff --git a/src/drivers/intel/Kconfig b/src/drivers/intel/Kconfig index 19986f4..e5525d8 100644 --- a/src/drivers/intel/Kconfig +++ b/src/drivers/intel/Kconfig @@ -14,5 +14,6 @@ ## source src/drivers/intel/fsp1_1/Kconfig +source src/drivers/intel/fsp2_0/Kconfig source src/drivers/intel/gma/Kconfig source src/drivers/intel/i210/Kconfig diff --git a/src/drivers/intel/Makefile.inc b/src/drivers/intel/Makefile.inc index e54f07b..67c1163 100644 --- a/src/drivers/intel/Makefile.inc +++ b/src/drivers/intel/Makefile.inc @@ -2,4 +2,5 @@ subdirs-y += gma subdirs-$(CONFIG_GENERATE_SMBIOS_TABLES) += wifi subdirs-$(CONFIG_PLATFORM_USES_FSP1_0) += fsp1_0 subdirs-$(CONFIG_PLATFORM_USES_FSP1_1) += fsp1_1 +subdirs-$(CONFIG_PLATFORM_USES_FSP2_0) += fsp2_0 subdirs-$(CONFIG_DRIVER_INTEL_I210) += i210 diff --git a/src/drivers/intel/fsp2_0/Kconfig b/src/drivers/intel/fsp2_0/Kconfig new file mode 100644 index 0000000..a029965 --- /dev/null +++ b/src/drivers/intel/fsp2_0/Kconfig @@ -0,0 +1,56 @@ +config PLATFORM_USES_FSP2_0 + bool + help + Include FSP 2.0 wrappers and functionality + +if PLATFORM_USES_FSP2_0 + +comment "Intel FSP 2.0" + +config ADD_FSP_BINARIES + bool "Add Intel FSP 2.0 binaries to CBFS" + help + Add the FSP-M and FSP-S binaries to CBFS. Note that coreboot does not + use the FSP-T binary, so that will not be included. + +if ADD_FSP_BINARIES + +config FSP_M_FILE + string "Intel FSP-M (memory init) binary path and filename" + help + The path and filename of the Intel FSP-M binary for this platform. + +config FSP_S_FILE + string "Intel FSP-S (silicon init) binary path and filename" + help + The path and filename of the Intel FSP-S binary for this platform. + +endif # ADD_FSP_BINARIES + +# Cache As RAM region layout: +# +# +-------------+ DCACHE_RAM_BASE + DCACHE_RAM_SIZE [0xfef80000] +# | | +# | FSP-M | +# | code | +# | | +# +-------------+ FSP-M [0xfef30000] +# | romstage | +# | code | +# +-------------+ ROMSTAGE_CAR_ADDR [0xfef28000] +# | FIT TABLE | +# +-------------+ FIT_CAR_ADDR [0xfef27c00] +# | FSP-M | +# | stack/data | +# +-------------+ DCACHE_RAM_BASE + 0x4000 [0xfef04000] +# | Stack | +# | | | +# | v | +# +-------------+ +# | ^ | +# | | | +# | CAR Globals | +# +-------------+ DCACHE_RAM_BASE [0xfef00000] + + +endif # PLATFORM_USES_FSP2_0 diff --git a/src/drivers/intel/fsp2_0/Makefile.inc b/src/drivers/intel/fsp2_0/Makefile.inc new file mode 100644 index 0000000..c85b4bc --- /dev/null +++ b/src/drivers/intel/fsp2_0/Makefile.inc @@ -0,0 +1,10 @@ + +CPPFLAGS_common += -I$(src)/drivers/intel/fsp2_0/include + +cbfs-files-$(CONFIG_ADD_FSP_BINARIES) += blobs/fsp-m.bin +blobs/fsp-m.bin-file := $(call strip_quotes,$(CONFIG_FSP_M_FILE)) +blobs/fsp-m.bin-type := raw + +cbfs-files-$(CONFIG_ADD_FSP_BINARIES) += blobs/fsp-s.bin +blobs/fsp-s.bin-file := $(call strip_quotes,$(CONFIG_FSP_S_FILE)) +blobs/fsp-s.bin-type := raw

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Patch set updated for coreboot: drivers/intel/fsp2.0: Add semantic patch for FspUpdVpd.h header
by Alexandru Gagniuc 26 Jan '16

26 Jan '16

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13331 -gerrit commit 59b37d9eee73e3c1c22afa869b358c34040f9eef Author: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> Date: Fri Oct 30 18:05:57 2015 -0700 drivers/intel/fsp2.0: Add semantic patch for FspUpdVpd.h header Previous FSP implementations in coreboot have included FspUpdVpd.h directly, along with with efi headers. Instead of taking that approach in FSP 2.0, we provide a semantic patch that, with minimal modifications, makes FspUpdVpd.h easier to include in coreboot, and eliminates reliance on external headers and definitions. Change-Id: I0c2a6f7baf6fb50ae22b64e08e653cfe1aefdaf9 Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> --- .../intel/fsp2_0/header_util/fspupdvpd.spatch | 147 +++++++++++++++++++++ .../intel/fsp2_0/header_util/fspupdvpd_sanitize.sh | 22 +++ 2 files changed, 169 insertions(+) diff --git a/src/drivers/intel/fsp2_0/header_util/fspupdvpd.spatch b/src/drivers/intel/fsp2_0/header_util/fspupdvpd.spatch new file mode 100644 index 0000000..8f41836 --- /dev/null +++ b/src/drivers/intel/fsp2_0/header_util/fspupdvpd.spatch @@ -0,0 +1,147 @@ +/* + * Semantic patch for fspupdvpd_sanitize.sh. Please call the script directly. + * + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * (Written by Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +@ kill_pragma_pack @ +@@ +- #pragma pack(...) + +/* + * Convert named typedef'd structs + */ +@ named_struct @ +identifier i; +type t; +@@ +typedef struct i { ... } t; + +/* Make typename usable as identifier */ +@ script:python named_struct_type @ +t << named_struct.t; +i; +@@ +coccinelle.i = t.rstrip('_t') + + +@ convert_named_struct_decls @ +type named_struct.t; +identifier named_struct_type.i; +identifier g; +@@ +- typedef struct g { ++ struct i { +... +} +- t +; + +/* Replace type with struct */ +@ named_typedef_to_struct @ +type named_struct.t; +identifier named_struct_type.i; +@@ +- t ++ struct i + + +/* + * Convert unnamed typedef'd structs + */ +@ unnamed_struct @ +type t; +@@ +typedef struct { ... } t; + +/* Make typename usable as identifier */ +@ script:python unnamed_struct_type @ +t << unnamed_struct.t; +i; +@@ +coccinelle.i = t.rstrip('_t') + +@ convert_unnamed_struct_decls @ +type unnamed_struct.t; +identifier unnamed_struct_type.i; +@@ +-typedef struct { ++struct i { + ... +} +- t +; + +/* Replace type with struct */ +@ unnamed_typedef_to_struct @ +type unnamed_struct.t; +identifier unnamed_struct_type.i; +@@ +-t ++struct i + +/* + * Pack _ALL_ structs + */ +@ pack_structs @ +identifier s; +@@ + +struct s { +... +} ++ __attribute__((packed)) +; + +/* + * BIGINT to stdint + */ +@ uint8_t @ +typedef UINT8; +typedef uint8_t; +@@ +- UINT8 ++ uint8_t + +@ uint16_t @ +typedef UINT16; +typedef uint16_t; +@@ +- UINT16 ++ uint16_t + +@ uint32_t @ +typedef UINT32; +typedef uint32_t; +@@ +- UINT32 ++ uint32_t + +@ uint64_t @ +typedef UINT64; +typedef uint64_t; +@@ +- UINT64 ++ uint64_t + +@ bool @ +typedef BOOLEAN; +typedef bool; +@@ +- BOOLEAN ++ bool + +@ wchar_t @ +typedef CHAR16; +typedef wchar_t; +@@ +- CHAR16 ++ wchar_t diff --git a/src/drivers/intel/fsp2_0/header_util/fspupdvpd_sanitize.sh b/src/drivers/intel/fsp2_0/header_util/fspupdvpd_sanitize.sh new file mode 100644 index 0000000..7c3195e --- /dev/null +++ b/src/drivers/intel/fsp2_0/header_util/fspupdvpd_sanitize.sh @@ -0,0 +1,22 @@ +# +# Convert the FspUpdVpd.h header file into a format usable by coreboot +# Usage: +# fspupdvpd_sanitize.sh <path/to/FspUpdVpd.h> +# +# This file is part of the coreboot project. +# +# Copyright (C) 2015 Intel Corp. +# (Written by Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> for Intel Corp.) +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. + +HOME=$(dirname "${BASH_SOURCE[0]}") +DEST=$HOME + +SPATCH=spatch + +$SPATCH -sp_file $HOME/fspupdvpd.spatch \ + -in_place $1

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Patch set updated for coreboot: drivers/intel/fsp2_0: Add functionality to decode FSP 2.0 headers
by Alexandru Gagniuc 26 Jan '16

26 Jan '16

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13330 -gerrit commit 54c89cf0fd4a5b6492680c0358ffd768d18ef073 Author: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> Date: Thu Oct 29 16:48:54 2015 -0700 drivers/intel/fsp2_0: Add functionality to decode FSP 2.0 headers This adds the minimum code needed to interpret the information in FSP headers. Only the fields that are useful are being decoded. Change-Id: Iffbeed2db1b267fe08f7935b797d94469f65b48b Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> --- src/drivers/intel/fsp2_0/Makefile.inc | 2 + src/drivers/intel/fsp2_0/include/fsp/info_header.h | 40 +++++++++++++ src/drivers/intel/fsp2_0/util.c | 70 ++++++++++++++++++++++ 3 files changed, 112 insertions(+) diff --git a/src/drivers/intel/fsp2_0/Makefile.inc b/src/drivers/intel/fsp2_0/Makefile.inc index c85b4bc..b6cb7cd 100644 --- a/src/drivers/intel/fsp2_0/Makefile.inc +++ b/src/drivers/intel/fsp2_0/Makefile.inc @@ -1,4 +1,6 @@ +romstage-y += util.c + CPPFLAGS_common += -I$(src)/drivers/intel/fsp2_0/include cbfs-files-$(CONFIG_ADD_FSP_BINARIES) += blobs/fsp-m.bin diff --git a/src/drivers/intel/fsp2_0/include/fsp/info_header.h b/src/drivers/intel/fsp2_0/include/fsp/info_header.h new file mode 100644 index 0000000..1e88410 --- /dev/null +++ b/src/drivers/intel/fsp2_0/include/fsp/info_header.h @@ -0,0 +1,40 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * (Written by Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef _FSP2_0_INFO_HEADER_H_ +#define _FSP2_0_INFO_HEADER_H_ + +#include <stdint.h> +#include <stdlib.h> +#include <types.h> + +#define FSP_HDR_OFFSET 0x94 +#define FSP_HDR_LEN 0x48 +#define FSP_HDR_SIGNATURE "FSPH" + +struct fsp_header { + uint32_t fsp_revision; + size_t image_size; + uintptr_t image_base; + size_t cfg_region_offset; + size_t cfg_region_size; + size_t notify_phase_entry_offset; + size_t memory_init_entry_offset; + size_t silicon_init_entry_offset; + char image_id[9]; + uint8_t revision; +}; + +enum cb_err fsp_identify(struct fsp_header *hdr, const void *fsp_blob); +void fsp_print_header_info(const struct fsp_header *hdr); + +#endif /* _FSP2_0_INFO_HEADER_H_ */ diff --git a/src/drivers/intel/fsp2_0/util.c b/src/drivers/intel/fsp2_0/util.c new file mode 100644 index 0000000..4e1dbf3 --- /dev/null +++ b/src/drivers/intel/fsp2_0/util.c @@ -0,0 +1,70 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * (Written by Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include <arch/io.h> +#include <console/console.h> +#include <fsp/info_header.h> +#include <lib.h> +#include <string.h> + +static bool looks_like_fsp_header(const uint8_t *raw_hdr) +{ + if (memcmp(raw_hdr, FSP_HDR_SIGNATURE, 4)) { + printk(BIOS_ALERT, "Did not find a valid FSP signature\n"); + return false; + } + + if (read32(raw_hdr + 4) != FSP_HDR_LEN) { + printk(BIOS_ALERT, "FSP header has invalid length\n"); + return false; + } + + return true; +} + +enum cb_err fsp_identify(struct fsp_header *hdr, const void *fsp_blob) +{ + const uint8_t *raw_hdr = fsp_blob; + raw_hdr += FSP_HDR_OFFSET; + + if (!looks_like_fsp_header(raw_hdr)) + return CB_ERR; + + hdr->revision = read8(raw_hdr + 0x0b); + hdr->fsp_revision = read32(raw_hdr + 0x0c); + memcpy(hdr->image_id, raw_hdr + 0x10, 8); + hdr->image_id[8] = '\0'; + hdr->image_size = read32(raw_hdr + 0x18); + hdr->image_base = read32(raw_hdr + 0x1c); + hdr->cfg_region_offset = read32(raw_hdr + 0x24); + hdr->cfg_region_size = read32(raw_hdr + 0x28); + hdr->notify_phase_entry_offset = read32(raw_hdr + 0x38); + hdr->memory_init_entry_offset = read32(raw_hdr + 0x3c); + hdr->silicon_init_entry_offset = read32(raw_hdr + 0x44); + + return CB_SUCCESS; +} + +void fsp_print_header_info(const struct fsp_header *hdr) +{ + printk(BIOS_DEBUG, "Revision %u, image ID: %s, base 0x%zx + 0x%zx\n", + hdr->revision ,hdr->image_id, hdr->image_base, hdr->image_size); + + printk(BIOS_DEBUG, "\tConfig region 0x%zx + 0x%zx\n", + hdr->cfg_region_offset, hdr->cfg_region_size); + printk(BIOS_DEBUG, "\tMemory init offset 0x%zx\n" + "\tSilicon init offset 0x%zx\n" + "\tNotify phase offset 0x%zx\n", + hdr->memory_init_entry_offset, + hdr->silicon_init_entry_offset, + hdr->notify_phase_entry_offset); +}

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Patch set updated for coreboot: soc/apollolake: Add BAR setup and enables essential for raminit
by Alexandru Gagniuc 26 Jan '16

26 Jan '16

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13324 -gerrit commit 96f419253ecd9c6cda8b63b5b9c0f6e466558a98 Author: Andrey Petrov <andrey.petrov(a)intel.com> Date: Mon Oct 26 18:10:04 2015 -0700 soc/apollolake: Add BAR setup and enables essential for raminit Change-Id: I884e677e607a14e9e88877a8e94e8518d473cf83 Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> --- src/soc/intel/apollolake/bootblock/bootblock_car.c | 7 ++-- src/soc/intel/apollolake/include/soc/iomap.h | 26 +++++++++++++++ src/soc/intel/apollolake/romstage/romstage.c | 38 ++++++++++++++++++++++ 3 files changed, 68 insertions(+), 3 deletions(-) diff --git a/src/soc/intel/apollolake/bootblock/bootblock_car.c b/src/soc/intel/apollolake/bootblock/bootblock_car.c index 7dd359b..8d317a1 100644 --- a/src/soc/intel/apollolake/bootblock/bootblock_car.c +++ b/src/soc/intel/apollolake/bootblock/bootblock_car.c @@ -16,6 +16,7 @@ #include <device/pci.h> #include <soc/bootblock.h> #include <soc/cpu.h> +#include <soc/iomap.h> #include <soc/uart.h> static void disable_watchdog(void) @@ -24,14 +25,14 @@ static void disable_watchdog(void) device_t dev = PCI_DEV(0, 0xd, 1); /* Open up an IO window */ - pci_write_config16(dev, PCI_BASE_ADDRESS_4, 0x400); + pci_write_config16(dev, PCI_BASE_ADDRESS_4, ACPI_PMIO_BASE); pci_write_config32(dev, PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_IO); /* We don't have documentation for this bit, but it prevents reboots */ - reg = inl(0x400 + 0x68); + reg = inl(ACPI_PMIO_BASE + 0x68); reg |= 1 << 11; - outl(reg, 0x400 + 0x68); + outl(reg, ACPI_PMIO_BASE + 0x68); } static void call_romstage(void *entry) diff --git a/src/soc/intel/apollolake/include/soc/iomap.h b/src/soc/intel/apollolake/include/soc/iomap.h new file mode 100644 index 0000000..09ae67d --- /dev/null +++ b/src/soc/intel/apollolake/include/soc/iomap.h @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * (Written by Andrey Petrov <andrey.petrov(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef _SOC_APOLLOLAKE_IOMAP_H_ +#define _SOC_APOLLOLAKE_IOMAP_H_ + +#define P2SB_BAR 0xd0000000 +#define MCH_BASE_ADDR 0xfed10000 + +#define ACPI_PMIO_BASE 0x400 +#define R_ACPI_PM1_TMR 0x8 + +/* Accesses to these BARs are hardcoded in FSP */ +#define PMC_BAR0 0xfe042000 +#define PMC_BAR1 0xfe044000 + +#endif /* _SOC_APOLLOLAKE_IOMAP_H_ */ diff --git a/src/soc/intel/apollolake/romstage/romstage.c b/src/soc/intel/apollolake/romstage/romstage.c index f76476b..38f4e85 100644 --- a/src/soc/intel/apollolake/romstage/romstage.c +++ b/src/soc/intel/apollolake/romstage/romstage.c @@ -3,6 +3,7 @@ * * Copyright (C) 2015 Intel Corp. * (Written by Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> for Intel Corp.) + * (Written by Andrey Petrov <andrey.petrov(a)intel.com> for Intel Corp.) * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -10,10 +11,45 @@ * (at your option) any later version. */ +#include <arch/io.h> #include <console/console.h> +#include <cpu/x86/msr.h> +#include <device/pci_def.h> +#include <soc/iomap.h> #include <soc/romstage.h> #include <soc/uart.h> +/* + * Enables several BARs and devices which are needed for memory init + * - MCH_BASE_ADDR is needed in order to talk to the memory controller + * - PMC_BAR0 and PMC_BAR1 are used by FSP (with the base address hardcoded) + * Once raminit is done, we can safely let the allocator re-assign them + * - HPET is enabled because FSP wants to store a pointer to global data in the + * HPET comparator register + */ +static void soc_early_romstage_init(void) +{ + msr_t msr; + device_t pmc = PCI_DEV(0, 13, 1); + + /* Set MCH base address */ + pci_write_config32(PCI_DEV(0, 0, 0), 0x48, MCH_BASE_ADDR); + + /* Set PMC base address */ + pci_write_config32(pmc, PCI_BASE_ADDRESS_0, PMC_BAR0); + pci_write_config32(pmc, PCI_BASE_ADDRESS_1, 0); /* 64-bit BAR */ + pci_write_config32(pmc, PCI_BASE_ADDRESS_2, PMC_BAR1); + pci_write_config32(pmc, PCI_BASE_ADDRESS_3, 0); /* 64-bit BAR */ + + /* PMIO BAR4 was already set in bootblock, hence the COMMAND_IO below */ + pci_write_config32(pmc, PCI_COMMAND, + PCI_COMMAND_IO | PCI_COMMAND_MEMORY | + PCI_COMMAND_MASTER); + + /* Enable decoding for HPET */ + pci_write_config32(PCI_DEV(0, 13, 0), 0x60, 1<<7); +} + asmlinkage void romstage_entry(void) { /* Be careful. Bootblock might already have initialized the console */ @@ -24,6 +60,8 @@ asmlinkage void romstage_entry(void) printk(BIOS_DEBUG, "Starting romstage...\n"); + soc_early_romstage_init(); + /* This function must not return */ while(1) ;

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Patch set updated for coreboot: soc/apollolake: Add enable bit for MCH BAR
by Alexandru Gagniuc 26 Jan '16

26 Jan '16

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13325 -gerrit commit bc805efa1b4890356135b0ec611d7365b7bf4226 Author: Andrey Petrov <andrey.petrov(a)intel.com> Date: Wed Oct 28 17:29:42 2015 -0700 soc/apollolake: Add enable bit for MCH BAR Change-Id: Iac8f2f819126401f470caa688600824ccc2edad9 Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> --- src/soc/intel/apollolake/romstage/romstage.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/soc/intel/apollolake/romstage/romstage.c b/src/soc/intel/apollolake/romstage/romstage.c index 38f4e85..a0d582d 100644 --- a/src/soc/intel/apollolake/romstage/romstage.c +++ b/src/soc/intel/apollolake/romstage/romstage.c @@ -32,8 +32,8 @@ static void soc_early_romstage_init(void) msr_t msr; device_t pmc = PCI_DEV(0, 13, 1); - /* Set MCH base address */ - pci_write_config32(PCI_DEV(0, 0, 0), 0x48, MCH_BASE_ADDR); + /* Set MCH base address and enable bit */ + pci_write_config32(PCI_DEV(0, 0, 0), 0x48, MCH_BASE_ADDR | 1); /* Set PMC base address */ pci_write_config32(pmc, PCI_BASE_ADDRESS_0, PMC_BAR0);

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Patch set updated for coreboot: soc/apollolake: Only allow mmaped accesses to IFD BIOS region
by Alexandru Gagniuc 26 Jan '16

26 Jan '16

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13326 -gerrit commit 07dad4366c0ea998b9e56d70eb3a645c1a00aca7 Author: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> Date: Wed Oct 28 12:28:41 2015 -0700 soc/apollolake: Only allow mmaped accesses to IFD BIOS region Only the BIOS region is memory-mapped by the hardware. Anything below that is invisible via MMIO. Also, the 256 KiB right below 4G are being decoded by readonly SRAM. Fail accesses to those regions, rather than returning false data. Change-Id: I34779109ffce50a1c5a4842d7bf75870b8b4dff8 Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> --- src/soc/intel/apollolake/Kconfig | 2 +- src/soc/intel/apollolake/mmap_boot.c | 32 ++++++++++++++++++++------------ 2 files changed, 21 insertions(+), 13 deletions(-) diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index 4a4efa4..317a439 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -78,7 +78,7 @@ config IFD_BIOS_START The starting address of flash region 1 (BIOS), as declared in the firmware descriptor. This can be obtained via 'ifdtool -d'. -config IFD_BIOS_SIZE +config IFD_BIOS_END hex default ROM_SIZE help diff --git a/src/soc/intel/apollolake/mmap_boot.c b/src/soc/intel/apollolake/mmap_boot.c index 7e9080b..60f7c1a 100644 --- a/src/soc/intel/apollolake/mmap_boot.c +++ b/src/soc/intel/apollolake/mmap_boot.c @@ -3,6 +3,7 @@ * * Copyright (C) 2015 Intel Corp. * (Written by Andrey Petrov <andrey.petrov(a)intel.com> for Intel Corp.) + * (Written by Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> for Intel Corp.) * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -11,31 +12,38 @@ */ #include <boot_device.h> -#include <console/console.h> #include <cbfs.h> -#include <endian.h> -#include <stdlib.h> #include <commonlib/region.h> +#include <console/console.h> #include <fmap.h> +#include <stdlib.h> +#include <string.h> + +/* The 256 KiB right below 4G are decoded by readonly SRAM, not boot media */ +#define IFD_BIOS_MAX_MAPPED (CONFIG_IFD_BIOS_END - 256 * KiB) +#define IFD_MAPPED_SIZE (IFD_BIOS_MAX_MAPPED - CONFIG_IFD_BIOS_START) +#define IFD_BIOS_SIZE (CONFIG_IFD_BIOS_END - CONFIG_IFD_BIOS_START) /* * If Apollo Lake is configured to boot from SPI flash "BIOS" region * (as defined in descriptor) is mapped below 4GiB. Form a pointer for * the base. */ -#define ROM_BASE ((void *)(uintptr_t)(0x100000000ULL - CONFIG_IFD_BIOS_SIZE)) +#define VIRTUAL_ROM_BASE ((uintptr_t)(0x100000000ULL - IFD_BIOS_SIZE)) -static const struct mem_region_device boot_dev = { - .base = (void *) ROM_BASE, - /* typically not whole flash is memory mapped */ - .rdev = REGION_DEV_INIT(&mem_rdev_ops, CONFIG_IFD_BIOS_START, - CONFIG_IFD_BIOS_SIZE) -}; +static const struct mem_region_device shadow_dev = MEM_REGION_DEV_INIT( + VIRTUAL_ROM_BASE, IFD_BIOS_MAX_MAPPED +); + +static const struct xlate_region_device real_dev = XLATE_REGION_INIT( + &shadow_dev.rdev, CONFIG_IFD_BIOS_START, + IFD_MAPPED_SIZE, CONFIG_ROM_SIZE +); const struct region_device *boot_device_ro(void) { - return &boot_dev.rdev; -} + return &real_dev.rdev; +}; static int iafw_boot_region_properties(struct cbfs_props *props) {

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Patch set updated for coreboot: intel/apollolake_rvp: Update name of IFD_BIOS_START variable
by Alexandru Gagniuc 26 Jan '16

26 Jan '16

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13327 -gerrit commit 341824a61770e45a7cc3b6cde5f6e6bfacbf4f99 Author: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> Date: Wed Oct 28 12:38:48 2015 -0700 intel/apollolake_rvp: Update name of IFD_BIOS_START variable It was recently changed in soc/intel/apollolake. Change-Id: I5cd41154bf85700752977e37cc1824ec2651e5bb Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> --- src/mainboard/intel/apollolake_rvp/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/intel/apollolake_rvp/Kconfig b/src/mainboard/intel/apollolake_rvp/Kconfig index 492ccdc..5e6c4f0 100755 --- a/src/mainboard/intel/apollolake_rvp/Kconfig +++ b/src/mainboard/intel/apollolake_rvp/Kconfig @@ -17,7 +17,7 @@ config MAINBOARD_VENDOR string default "Intel" -config IFD_BIOS_SIZE +config IFD_BIOS_END hex default 0x700000

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Patch set updated for coreboot: soc/apollolake: Handle romstage entry and call into C code
by Alexandru Gagniuc 26 Jan '16

26 Jan '16

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13323 -gerrit commit f51acb7963de86b1abcc1be92d0849511d3edb84 Author: Andrey Petrov <andrey.petrov(a)intel.com> Date: Tue Oct 27 22:08:03 2015 -0700 soc/apollolake: Handle romstage entry and call into C code Parameter passing between bootblock and romstage is not implemented at this point. This patch only resets the stack pointer on romstage entry before calling into C code. Change-Id: I7effcf3dcd78191a70c4d9caab56bee3d0a6d3ae Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> --- src/soc/intel/apollolake/Makefile.inc | 2 ++ src/soc/intel/apollolake/include/soc/romstage.h | 20 +++++++++++++++++ src/soc/intel/apollolake/romstage/entry.inc | 21 +++++++++++++++++ src/soc/intel/apollolake/romstage/romstage.c | 30 +++++++++++++++++++++++++ 4 files changed, 73 insertions(+) diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc index 4b0b31d..e57342a 100644 --- a/src/soc/intel/apollolake/Makefile.inc +++ b/src/soc/intel/apollolake/Makefile.inc @@ -15,9 +15,11 @@ bootblock-y += bootblock/early_chipset_config.S bootblock-y += mmap_boot.c bootblock-y += uart_early.c +cpu_incs-y += $(src)/soc/intel/apollolake/romstage/entry.inc romstage-y += cpu.c romstage-y += gpio.c romstage-y += mmap_boot.c +romstage-y += romstage/romstage.c romstage-y += uart_early.c ramstage-y += cpu.c diff --git a/src/soc/intel/apollolake/include/soc/romstage.h b/src/soc/intel/apollolake/include/soc/romstage.h new file mode 100644 index 0000000..f57f26d --- /dev/null +++ b/src/soc/intel/apollolake/include/soc/romstage.h @@ -0,0 +1,20 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * (Written by Andrey Petrov <andrey.petrov(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef _SOC_APOLLOLAKE_ROMSTAGE_H_ +#define _SOC_APOLLOLAKE_ROMSTAGE_H_ + +#include <arch/cpu.h> + +asmlinkage void romstage_entry(void); + +#endif /* _SOC_APOLLOLAKE_ROMSTAGE_H_ */ diff --git a/src/soc/intel/apollolake/romstage/entry.inc b/src/soc/intel/apollolake/romstage/entry.inc new file mode 100644 index 0000000..b04e17e --- /dev/null +++ b/src/soc/intel/apollolake/romstage/entry.inc @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * (Written by Andrey Petrov <andrey.petrov(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +.intel_syntax noprefix +apollolake_entry: + + /* + * TODO: Make sure the stack does not clash with .car.data. + */ + mov esp, (CONFIG_DCACHE_RAM_BASE + 0x4000) + + call romstage_entry diff --git a/src/soc/intel/apollolake/romstage/romstage.c b/src/soc/intel/apollolake/romstage/romstage.c new file mode 100644 index 0000000..f76476b --- /dev/null +++ b/src/soc/intel/apollolake/romstage/romstage.c @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * (Written by Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include <console/console.h> +#include <soc/romstage.h> +#include <soc/uart.h> + +asmlinkage void romstage_entry(void) +{ + /* Be careful. Bootblock might already have initialized the console */ + if (!IS_ENABLED(CONFIG_BOOTBLOCK_CONSOLE)) { + lpss_console_uart_init(); + console_init(); + } + + printk(BIOS_DEBUG, "Starting romstage...\n"); + + /* This function must not return */ + while(1) + ; +}

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Patch set updated for coreboot: cbfstool: Fix broken alignment because of flashmap
by Werner Zeh 26 Jan '16

26 Jan '16

Werner Zeh (werner.zeh(a)siemens.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13417 -gerrit commit 51a6c33d3153dec7ed8489dd236a5170cb5dbfd7 Author: Werner Zeh <werner.zeh(a)siemens.com> Date: Mon Jan 25 12:47:20 2016 +0100 cbfstool: Fix broken alignment because of flashmap With the introduction of flashmap cbfs alignment of files gets broken because flashmap is located at the beginning of the flash and cbfstool didn't take care about that offset. This commit fixes the alignment in cbfs. Change-Id: Idebb86d4c691b49a351a402ef79c62d31622c773 Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> --- util/cbfstool/cbfs_image.c | 19 +++++++++++++++---- util/cbfstool/cbfs_image.h | 1 + util/cbfstool/cbfstool.c | 2 ++ 3 files changed, 18 insertions(+), 4 deletions(-) diff --git a/util/cbfstool/cbfs_image.c b/util/cbfstool/cbfs_image.c index 2d7a6f0..2a26f85 100644 --- a/util/cbfstool/cbfs_image.c +++ b/util/cbfstool/cbfs_image.c @@ -2,6 +2,7 @@ * CBFS Image Manipulation * * Copyright (C) 2013 The Chromium OS Authors. All rights reserved. + * Copyright (C) 2016 Siemens AG. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -1410,6 +1411,16 @@ static int is_in_range(size_t start, size_t end, size_t metadata_size, return (offset >= start + metadata_size && offset + size <= end); } +static size_t absolute_align(const struct cbfs_image *image, size_t val, + size_t align) +{ + const size_t region_offset = buffer_offset(&image->buffer); + /* To perform alignment on absolute address, take the region offset */ + /* of the image into account. */ + return align_up(val + region_offset, align) - region_offset; + +} + int32_t cbfs_locate_entry(struct cbfs_image *image, size_t size, size_t page_size, size_t align, size_t metadata_size) { @@ -1474,15 +1485,15 @@ int32_t cbfs_locate_entry(struct cbfs_image *image, size_t size, if (addr_next - addr < need_len) continue; - offset = align_up(addr + metadata_size, align); + offset = absolute_align(image, addr + metadata_size, align); if (is_in_same_page(offset, size, page_size) && is_in_range(addr, addr_next, metadata_size, offset, size)) { DEBUG("cbfs_locate_entry: FIT (PAGE1)."); return offset; } - addr2 = align_up(addr, page_size); - offset = align_up(addr2, align); + addr2 = absolute_align(image, addr, page_size); + offset = absolute_align(image, addr2, align); if (is_in_range(addr, addr_next, metadata_size, offset, size)) { DEBUG("cbfs_locate_entry: OVERLAP (PAGE2)."); return offset; @@ -1492,7 +1503,7 @@ int32_t cbfs_locate_entry(struct cbfs_image *image, size_t size, * definitely provide the space for header. */ assert(page_size >= metadata_size); addr3 = addr2 + page_size; - offset = align_up(addr3, align); + offset = absolute_align(image, addr3, align); if (is_in_range(addr, addr_next, metadata_size, offset, size)) { DEBUG("cbfs_locate_entry: OVERLAP+ (PAGE3)."); return offset; diff --git a/util/cbfstool/cbfs_image.h b/util/cbfstool/cbfs_image.h index 00adcc8..19c0b69 100644 --- a/util/cbfstool/cbfs_image.h +++ b/util/cbfstool/cbfs_image.h @@ -2,6 +2,7 @@ * CBFS Image Manipulation * * Copyright (C) 2013 The Chromium OS Authors. All rights reserved. + * Copyright (C) 2016 Siemens AG. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/util/cbfstool/cbfstool.c b/util/cbfstool/cbfstool.c index 23787d8..5b3d58a 100644 --- a/util/cbfstool/cbfstool.c +++ b/util/cbfstool/cbfstool.c @@ -166,6 +166,8 @@ static int do_cbfs_locate(int32_t *cbfs_addr, size_t metadata_size) if (param.hash != VB2_HASH_INVALID) metadata_size += sizeof(struct cbfs_file_attr_hash); + /* image.buffer.offset is passed so alignment is calculated relative */ + /* to flash address, not the start of CBFS. */ int32_t address = cbfs_locate_entry(&image, buffer.size, param.pagesize, param.alignment, metadata_size); buffer_delete(&buffer);

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Patch merged into coreboot/master: cbfstool: provide buffer_offset()
by gerrit＠coreboot.org 26 Jan '16

26 Jan '16

the following patch was just integrated into master: commit 2dd5f4cce61f95468cd84d7272b8c455d0b6408b Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue Jan 26 09:01:14 2016 -0600 cbfstool: provide buffer_offset() Instead of people open coding the offset field access within a struct buffer provide buffer_offset() so that the implementation can change if needed without high touch in the code base. Change-Id: I751c7145687a8529ab549d87e412b7f2d1fb90ed Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://review.coreboot.org/13468 Tested-by: build bot (Jenkins) Reviewed-by: Werner Zeh <werner.zeh(a)siemens.com> See https://review.coreboot.org/13468 for details. -gerrit

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