coreboot-gerrit January 2016

coreboot-gerrit@coreboot.org

1 participants
2471 discussions

Patch merged into coreboot/master: cbfstool: Fix compile issue for older gcc versions
by gerrit＠coreboot.org 25 Jan '16

25 Jan '16

the following patch was just integrated into master: commit 998671c125fac6fdf894f5e8b4c02ade02417799 Author: Werner Zeh <werner.zeh(a)siemens.com> Date: Mon Jan 25 14:15:43 2016 +0100 cbfstool: Fix compile issue for older gcc versions gcc 4.4.7 fails to compile due to the missing initializers for all struct members. Add initializers for all fields. Change-Id: If1ad4fff0f965ccd7e821820c0703853c1e5c590 Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> Reviewed-on: https://review.coreboot.org/13418 Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/13418 for details. -gerrit

1 0

Patch set updated for coreboot: Strago: Disable SD Card Detect Simulation in FSP
by Hannah Williams 25 Jan '16

25 Jan '16

Hannah Williams (hannah.williams(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13035 -gerrit commit 87b1617cea1eafe6c0ac90dde6ec4cb00bb41105 Author: Hannah Williams <hannah.williams(a)intel.com> Date: Sun Jan 17 23:11:25 2016 -0800 Strago: Disable SD Card Detect Simulation in FSP CQ-DEPEND=CL:12742 Signed-off-by: Hannah Williams <hannah.williams(a)intel.com> Change-Id: I6c39ffebe407a4ef8555b2f050a96d33709dc624 --- src/mainboard/intel/strago/devicetree.cb | 1 + 1 file changed, 1 insertion(+) diff --git a/src/mainboard/intel/strago/devicetree.cb b/src/mainboard/intel/strago/devicetree.cb index 788153a..920c526 100755 --- a/src/mainboard/intel/strago/devicetree.cb +++ b/src/mainboard/intel/strago/devicetree.cb @@ -70,6 +70,7 @@ chip soc/intel/braswell register "PMIC_I2CBus" = "0" register "ISPEnable" = "0" # Disable IUNIT register "ISPPciDevConfig" = "3" + register "PcdSdDetectChk" = "0" # Disable SD card detect # LPE audio codec settings register "lpe_codec_clk_freq" = "25" # 25MHz clock

1 0

Patch set updated for coreboot: Strago: Disable SD Card Detect Simulation in FSP
by Hannah Williams 25 Jan '16

25 Jan '16

Hannah Williams (hannah.williams(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13035 -gerrit commit 8d1e7740dcc1e83c903dba8b371854d73bc08e03 Author: Hannah Williams <hannah.williams(a)intel.com> Date: Sun Jan 17 23:11:25 2016 -0800 Strago: Disable SD Card Detect Simulation in FSP CQ-DEPEND=CL:12742 Signed-off-by: Hannah Williams <hannah.williams(a)intel.com> Change-Id: I6c39ffebe407a4ef8555b2f050a96d33709dc624 --- src/mainboard/intel/strago/devicetree.cb | 1 + 1 file changed, 1 insertion(+) diff --git a/src/mainboard/intel/strago/devicetree.cb b/src/mainboard/intel/strago/devicetree.cb index 788153a..920c526 100755 --- a/src/mainboard/intel/strago/devicetree.cb +++ b/src/mainboard/intel/strago/devicetree.cb @@ -70,6 +70,7 @@ chip soc/intel/braswell register "PMIC_I2CBus" = "0" register "ISPEnable" = "0" # Disable IUNIT register "ISPPciDevConfig" = "3" + register "PcdSdDetectChk" = "0" # Disable SD card detect # LPE audio codec settings register "lpe_codec_clk_freq" = "25" # 25MHz clock

1 0

Patch set updated for coreboot: intel/strago: Cleanup GPIO config
by Hannah Williams 25 Jan '16

25 Jan '16

Hannah Williams (hannah.williams(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13431 -gerrit commit 4f73731db1690ea0e5344ee0a60c4dbd8934d592 Author: Hannah Williams <hannah.williams(a)intel.com> Date: Mon Jan 25 14:25:23 2016 -0800 intel/strago: Cleanup GPIO config Fix GPIO config for this board Change-Id: Iecb23df465a540a71f7268c5aac48617dc74ebf2 Signed-off-by: Hannah Williams <hannah.williams(a)intel.com> --- src/mainboard/intel/strago/gpio.c | 16 ++++++++++------ 1 file changed, 10 insertions(+), 6 deletions(-) diff --git a/src/mainboard/intel/strago/gpio.c b/src/mainboard/intel/strago/gpio.c index 8b6a0e7..c57a573 100755 --- a/src/mainboard/intel/strago/gpio.c +++ b/src/mainboard/intel/strago/gpio.c @@ -74,7 +74,9 @@ static const struct soc_gpio_map gpse_gpio_map[] = { Native_M1, /* 78 SDMMC3_PWR_EN_B */ GPIO_NC, /* 79 GPI ILB_SERIRQ */ Native_M1, /* 80 USB_OC0_B */ - NATIVE_INT(1, L1), /* 81 SDMMC3_CD_B */ + GPI(trig_edge_both, L1, P_20K_H, non_maskable, + en_edge_detect, NA , NA), + /* 81 SDMMC3_CD_B */ GPIO_NC, /* 82 spkr asummed gpio number */ Native_M1, /* 83 SUSPWRDNACK */ SPARE_PIN,/* 84 spare pin */ @@ -112,11 +114,11 @@ static const struct soc_gpio_map gpsw_gpio_map[] = { GPI(trig_edge_both, L2, P_1K_H, non_maskable, en_edge_detect, NA, NA), /* 37 MF_HDA_DOCKENB */ NATIVE_PU1K_CSEN_INVTX(1), /* 45 I2C5_SDA */ - GPIO_NC, /* 46 I2C4_SDA */ + NATIVE_PU1K_CSEN_INVTX(1), /* 46 I2C4_SDA */ NATIVE_PU1K_CSEN_INVTX(1), /* 47 I2C6_SDA */ NATIVE_PU1K_CSEN_INVTX(1), /* 48 I2C5_SCL */ GPIO_NC, /* 49 I2C_NFC_SDA */ - GPIO_NC, /* 50 I2C4_SCL */ + NATIVE_PU1K_CSEN_INVTX(1), /* 50 I2C4_SCL */ NATIVE_PU1K_CSEN_INVTX(1), /* 51 I2C6_SCL */ GPIO_NC, /* 52 I2C_NFC_SCL */ NATIVE_PU1K_CSEN_INVTX(1), /* 60 I2C1_SDA */ @@ -128,7 +130,7 @@ static const struct soc_gpio_map gpsw_gpio_map[] = { NATIVE_PU1K_CSEN_INVTX(1), /* 66 I2C2_SCL */ GPIO_INPUT_NO_PULL,/* 67 I2C3_SCL,RAMID1 */ GPIO_OUT_HIGH, /* 75 SATA_GP0 */ - GPI(trig_edge_low, L0, P_1K_H, non_maskable, NA, NA, NA), + GPIO_NC, /* 76 GPI SATA_GP1 */ Native_M1, /* 77 SATA_LEDN */ GPIO_NC, /* 80 SATA_GP3 */ @@ -169,9 +171,11 @@ static const struct soc_gpio_map gpn_gpio_map[] = { /* 17 GPIO_SUS3 */ GPI(trig_edge_low, L1, P_1K_H, non_maskable, NA, UNMASK_WAKE, NA), /* 18 GPIO_SUS7 */ - GPO_FUNC(0, 0), /* 19 GPIO_SUS1 */ + GPI(trig_edge_low, L3, P_1K_H, non_maskable, NA, UNMASK_WAKE, NA), + /* 19 GPIO_SUS1 */ GPIO_NC, /* 20 GPIO_SUS5 */ - GPI(trig_edge_high, L2, NA, non_maskable, en_edge_rx_data, NA , NA), + GPI(trig_edge_high, L2, P_20K_H, non_maskable, + en_edge_rx_data, NA , NA), /* 21 SEC_GPIO_SUS11 */ GPIO_NC, /* 22 GPIO_SUS4 */ GPIO_NC,

1 0

Patch set updated for coreboot: soc/braswell: Add macro NATIVE_INT_PU20K
by Hannah Williams 25 Jan '16

25 Jan '16

Hannah Williams (hannah.williams(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13054 -gerrit commit 3106c3caf04319f8f41088781e213f86c46e156f Author: Hannah Williams <hannah.williams(a)intel.com> Date: Tue Jan 19 11:58:58 2016 -0800 soc/braswell: Add macro NATIVE_INT_PU20K Change-Id: I04db02d37a76f0643a73ae4d67b839e5cd61f7e3 Signed-off-by: Hannah Williams <hannah.williams(a)intel.com> --- src/soc/intel/braswell/include/soc/gpio.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/src/soc/intel/braswell/include/soc/gpio.h b/src/soc/intel/braswell/include/soc/gpio.h index 11110c9..4ab6592 100644 --- a/src/soc/intel/braswell/include/soc/gpio.h +++ b/src/soc/intel/braswell/include/soc/gpio.h @@ -285,6 +285,11 @@ | PAD_GPIOFG_HI_Z | PAD_MODE_SELECTION(mode),\ .pad_conf1 = PAD_CONFIG1_DEFAULT0 } +#define NATIVE_INT_PU20K(mode, int_sel) {\ + .pad_conf0 = PAD_PULL_UP_20K | PAD_INT_SEL(int_sel) | PAD_GPIO_DISABLE \ + | PAD_GPIOFG_HI_Z | PAD_MODE_SELECTION(mode),\ + .pad_conf1 = PAD_CONFIG1_DEFAULT0 } + #define SPEAKER \ { .pad_conf0 = PAD_CONFIG0_DEFAULT0, \ .pad_conf1 = PAD_CONFIG1_DEFAULT0 }

1 0

Patch set updated for coreboot: soc/braswell: Update FspUpdVpd.h for PcdSdDetectChk and PcdCaMirrorEn
by Hannah Williams 25 Jan '16

25 Jan '16

Hannah Williams (hannah.williams(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13038 -gerrit commit c4db2b0055729bf4428319e131f792345f814943 Author: Hannah Williams <hannah.williams(a)intel.com> Date: Mon Jan 18 00:22:52 2016 -0800 soc/braswell: Update FspUpdVpd.h for PcdSdDetectChk and PcdCaMirrorEn Change-Id: I42200feafed613136f23e37d4ab4c90931698821 Signed-off-by: Hannah Williams <hannah.williams(a)intel.com> --- .../intel/fsp/fsp1_1/braswell/FspUpdVpd.h | 31 ++++++++++++---------- 1 file changed, 17 insertions(+), 14 deletions(-) diff --git a/src/vendorcode/intel/fsp/fsp1_1/braswell/FspUpdVpd.h b/src/vendorcode/intel/fsp/fsp1_1/braswell/FspUpdVpd.h index 9b9df0e..61673c6 100644 --- a/src/vendorcode/intel/fsp/fsp1_1/braswell/FspUpdVpd.h +++ b/src/vendorcode/intel/fsp/fsp1_1/braswell/FspUpdVpd.h @@ -188,8 +188,13 @@ typedef struct { **/ UINT8 PcdMemoryTypeEnable; /** Offset 0x0042 + CaMirrorEn + To Enable/Disable CaMirrorEn **/ - UINT8 ReservedMemoryInitUpd[190]; + UINT8 PcdCaMirrorEn; +/** Offset 0x0043 +**/ + UINT8 ReservedMemoryInitUpd[189]; } MEMORY_INIT_UPD; typedef struct { @@ -436,8 +441,18 @@ typedef struct { **/ UINT8 PcdTurboMode; /** Offset 0x0161 + Pnp-Power & Performance + select Pnp type +**/ + UINT8 PcdPnpSettings; +/** Offset 0x0162 + SdDetectChk + Check for Sd card detect **/ - UINT8 ReservedSiliconInitUpd[413]; + UINT8 PcdSdDetectChk; +/** Offset 0x0163 +**/ + UINT8 ReservedSiliconInitUpd[411]; } SILICON_INIT_UPD; #define FSP_UPD_SIGNATURE 0x2444505557534224 /* '$BSWUPD$' */ @@ -472,12 +487,6 @@ typedef struct _UPD_DATA_REGION { /** Offset 0x02FE **/ UINT16 PcdRegionTerminator; -/** Offset 0x0300 -**/ - UINT8 UnusedUpdSpace4[2123]; -/** Offset 0x0B4B -**/ - UINT8 PcdPaddingSpace; } UPD_DATA_REGION; #define FSP_IMAGE_ID 0x2450534657534224 /* '$BSWFSP$' */ @@ -494,12 +503,6 @@ typedef struct _VPD_DATA_REGION { /** Offset 0x000C **/ UINT32 PcdUpdRegionOffset; -/** Offset 0x0010 -**/ - UINT8 UnusedVpdSpace0[20]; -/** Offset 0x0024 -**/ - UINT8 PcdEnableSecureBoot; } VPD_DATA_REGION; #pragma pack(pop)

1 0

Patch set updated for coreboot: intel/strago: EC_IN_RW gpio input configuration.
by Hannah Williams 25 Jan '16

25 Jan '16

Hannah Williams (hannah.williams(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13124 -gerrit commit 4067a6fb2f37bbba32ff96862c3070ba52a9babb Author: Divagar Mohandass <divagar.mohandass(a)intel.com> Date: Mon Oct 5 16:21:14 2015 +0530 intel/strago: EC_IN_RW gpio input configuration. Configure EC_IN_RW signal as gpio input. TEST=Boot to Chrome OS in normal mode and enter recovery mode use ctrl-d to switch to Dev mode. Change-Id: I835a1c70d89ef2ab75c35233f889124b60bb64a3 Signed-off-by: Hannah Williams <hannah.williams(a)intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/304040 Original-Tested-by: Divagar Mohandass <divagar.mohandass(a)intel.com> Original-Reviewed-by: Gomathi Kumar <gomathi.kumar(a)intel.com> Original-Reviewed-by: Shobhit Srivastava <shobhit.srivastava(a)intel.com> Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Commit-Queue: Shobhit Srivastava <shobhit.srivastava(a)intel.com> --- src/mainboard/intel/strago/gpio.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/intel/strago/gpio.c b/src/mainboard/intel/strago/gpio.c index c57a573..14c5ab0 100755 --- a/src/mainboard/intel/strago/gpio.c +++ b/src/mainboard/intel/strago/gpio.c @@ -132,7 +132,7 @@ static const struct soc_gpio_map gpsw_gpio_map[] = { GPIO_OUT_HIGH, /* 75 SATA_GP0 */ GPIO_NC, /* 76 GPI SATA_GP1 */ - Native_M1, /* 77 SATA_LEDN */ + GPIO_INPUT_PU_20K, /* 77 SATA_LEDN , EC_IN_RW */ GPIO_NC, /* 80 SATA_GP3 */ Native_M1, /* 81 NFC_DEV_WAKE , MF_SMB_CLK */ GPIO_INPUT_NO_PULL, /* 80 SATA_GP3,RAMID0 */

1 0

Patch set updated for coreboot: intel/strago: Clean up DDR configuration.
by Hannah Williams 25 Jan '16

25 Jan '16

Hannah Williams (hannah.williams(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13122 -gerrit commit 5ba291c0dd6531b78fd044d60fece94e91e3b494 Author: Divagar Mohandass <divagar.mohandass(a)intel.com> Date: Tue Sep 8 15:03:45 2015 +0530 intel/strago: Clean up DDR configuration. This change includes following changes: - Clean up the DDR configuration and flow. - Removing support for non LPDDR3 boards. - Supporting only LPDDR3 and PMIC config. TEST=Build/flash CB and boot the platform to OS. Change-Id: I8369443da728a4c07e0c1a82040d94034c3542da Signed-off-by: Divagar Mohandass <divagar.mohandass(a)intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/297941 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-by: Jenny Tc <jenny.tc(a)intel.com> Signed-off-by: Hannah Williams <hannah.williams(a)intel.com> --- src/mainboard/intel/strago/Kconfig | 6 -- src/mainboard/intel/strago/Makefile.inc | 2 - src/mainboard/intel/strago/romstage.c | 26 +---- src/mainboard/intel/strago/spd/Makefile.inc | 38 ------- .../spd/hynix_2GiB_dimm_H5TC4G63AFR-PBA.spd.hex | 32 ------ ...nix_2GiB_dimm_HMT425S6CFR6A_H5TC4G63CFR.spd.hex | 32 ------ .../spd/samsung_2GiB_dimm_K4B4G1646Q-HYK0.spd.hex | 32 ------ src/mainboard/intel/strago/spd/spd.c | 116 --------------------- 8 files changed, 1 insertion(+), 283 deletions(-) diff --git a/src/mainboard/intel/strago/Kconfig b/src/mainboard/intel/strago/Kconfig index 204534a..f23a86c 100755 --- a/src/mainboard/intel/strago/Kconfig +++ b/src/mainboard/intel/strago/Kconfig @@ -21,12 +21,6 @@ config CHROMEOS select VBOOT_DYNAMIC_WORK_BUFFER select VIRTUAL_DEV_SWITCH -config DISPLAY_SPD_DATA - bool "Display Memory Serial Presence Detect Data" - default n - help - When enabled displays the memory configuration data. - config DYNAMIC_VNN_SUPPORT bool "Enables support for Dynamic VNN" default n diff --git a/src/mainboard/intel/strago/Makefile.inc b/src/mainboard/intel/strago/Makefile.inc index d53cd84..9c21bed 100755 --- a/src/mainboard/intel/strago/Makefile.inc +++ b/src/mainboard/intel/strago/Makefile.inc @@ -14,8 +14,6 @@ ## GNU General Public License for more details. ## -subdirs-y += spd - romstage-y += boardid.c romstage-$(CONFIG_MAINBOARD_HAS_CHROMEOS) += chromeos.c romstage-$(CONFIG_ENABLE_BUILTIN_COM1) += com_init.c diff --git a/src/mainboard/intel/strago/romstage.c b/src/mainboard/intel/strago/romstage.c index e582b56..56ab9a7 100755 --- a/src/mainboard/intel/strago/romstage.c +++ b/src/mainboard/intel/strago/romstage.c @@ -25,32 +25,8 @@ #include "onboard.h" #include <boardid.h> -/* All FSP specific code goes in this block */ -void mainboard_romstage_entry(struct romstage_params *rp) -{ - struct pei_data *ps = rp->pei_data; - - mainboard_fill_spd_data(ps); - - /* Call back into chipset code with platform values updated. */ - romstage_common(rp); -} - void mainboard_memory_init_params(struct romstage_params *params, MEMORY_INIT_UPD *memory_params) { - int id; - id = board_id(); - if (id == BOARD_BCRD2) { - memory_params->PcdMemoryTypeEnable = MEM_LPDDR3; - memory_params->PcdDvfsEnable = 0; - } else { - memory_params->PcdMemoryTypeEnable = MEM_DDR3; - memory_params->PcdMemorySpdPtr = - (u32)params->pei_data->spd_data_ch0; - memory_params->PcdMemChannel0Config = - params->pei_data->spd_ch0_config; - memory_params->PcdMemChannel1Config = - params->pei_data->spd_ch1_config; - } + memory_params->PcdMemoryTypeEnable = MEM_LPDDR3; } diff --git a/src/mainboard/intel/strago/spd/Makefile.inc b/src/mainboard/intel/strago/spd/Makefile.inc deleted file mode 100755 index 440735c..0000000 --- a/src/mainboard/intel/strago/spd/Makefile.inc +++ /dev/null @@ -1,38 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2013 Google Inc. -## Copyright (C) 2015 Intel Corp. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -romstage-y += spd.c - -SPD_BIN = $(obj)/spd.bin - -SPD_SOURCES = samsung_2GiB_dimm_K4B4G1646Q-HYK0 -SPD_SOURCES += hynix_2GiB_dimm_HMT425S6CFR6A_H5TC4G63CFR -SPD_SOURCES += samsung_2GiB_dimm_K4B4G1646Q-HYK0 -SPD_SOURCES += hynix_2GiB_dimm_HMT425S6CFR6A_H5TC4G63CFR - -SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex) - -# Include spd rom data -$(SPD_BIN): $(SPD_DEPS) - for f in $+; \ - do for c in $$(cat $$f | grep -v ^#); \ - do printf $$(printf '\%o' 0x$$c); \ - done; \ - done > $@ - -cbfs-files-y += spd.bin -spd.bin-file := $(SPD_BIN) -spd.bin-type := spd diff --git a/src/mainboard/intel/strago/spd/hynix_2GiB_dimm_H5TC4G63AFR-PBA.spd.hex b/src/mainboard/intel/strago/spd/hynix_2GiB_dimm_H5TC4G63AFR-PBA.spd.hex deleted file mode 100755 index ff4fd29..0000000 --- a/src/mainboard/intel/strago/spd/hynix_2GiB_dimm_H5TC4G63AFR-PBA.spd.hex +++ /dev/null @@ -1,32 +0,0 @@ -92 12 0b 03 04 19 02 02 -03 52 01 08 0a 00 fe 00 -69 78 69 3c 69 11 18 81 -20 08 3c 3c 01 40 83 01 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 0f 11 62 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 80 ad 01 -00 00 00 00 00 00 ff ab -48 4d 54 34 32 35 53 36 -41 46 52 36 41 2d 50 42 -20 20 4e 30 80 ad 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -ff ff ff ff ff ff ff ff -ff ff ff ff ff ff ff ff -ff ff ff ff ff ff ff ff -ff ff ff ff ff ff ff ff -ff ff ff ff ff ff ff ff -ff ff ff ff ff ff ff ff -ff ff ff ff ff ff ff ff -ff ff ff ff ff ff ff ff -ff ff ff ff ff ff ff ff -ff ff ff ff ff ff ff ff diff --git a/src/mainboard/intel/strago/spd/hynix_2GiB_dimm_HMT425S6CFR6A_H5TC4G63CFR.spd.hex b/src/mainboard/intel/strago/spd/hynix_2GiB_dimm_HMT425S6CFR6A_H5TC4G63CFR.spd.hex deleted file mode 100755 index fdd1a43..0000000 --- a/src/mainboard/intel/strago/spd/hynix_2GiB_dimm_HMT425S6CFR6A_H5TC4G63CFR.spd.hex +++ /dev/null @@ -1,32 +0,0 @@ -92 13 0B 03 04 19 02 02 -03 52 01 08 0A 00 FE 00 -69 78 69 3C 69 11 18 81 -20 08 3C 3C 01 40 83 01 -00 00 00 00 00 00 00 00 -00 88 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 0F 11 62 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 80 AD 01 -00 00 00 00 00 00 C9 C0 -48 4D 54 34 32 35 53 36 -43 46 52 36 41 2D 50 42 -20 20 4E 30 80 AD 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -FF FF FF FF FF FF FF FF -FF FF FF FF FF FF FF FF -FF FF FF FF FF FF FF FF -FF FF FF FF FF FF FF FF -FF FF FF FF FF FF FF FF -FF FF FF FF FF FF FF FF -FF FF FF FF FF FF FF FF -FF FF FF FF FF FF FF FF -FF FF FF FF FF FF FF FF -FF FF FF FF FF FF FF FF diff --git a/src/mainboard/intel/strago/spd/samsung_2GiB_dimm_K4B4G1646Q-HYK0.spd.hex b/src/mainboard/intel/strago/spd/samsung_2GiB_dimm_K4B4G1646Q-HYK0.spd.hex deleted file mode 100755 index e0b0ac5..0000000 --- a/src/mainboard/intel/strago/spd/samsung_2GiB_dimm_K4B4G1646Q-HYK0.spd.hex +++ /dev/null @@ -1,32 +0,0 @@ -92 12 0B 03 04 19 02 02 -03 11 01 08 0A 00 FE 00 -69 78 69 3C 69 11 18 81 -20 08 3C 3C 01 40 83 05 -00 00 00 00 00 00 00 00 -88 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 0F 01 02 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 80 CE 01 -00 00 00 00 00 00 6C F9 -4D 34 37 31 42 35 36 37 -34 51 48 30 2D 59 4B 30 -20 20 00 00 80 CE 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 diff --git a/src/mainboard/intel/strago/spd/spd.c b/src/mainboard/intel/strago/spd/spd.c deleted file mode 100755 index a711049..0000000 --- a/src/mainboard/intel/strago/spd/spd.c +++ /dev/null @@ -1,116 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2015 Intel Corp. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <cbfs.h> -#include <console/console.h> -#include <lib.h> -#include <soc/gpio.h> -#include <soc/romstage.h> -#include <string.h> - -#define SPD_SIZE 256 -#define SATA_GP3_PAD_CFG0 0x5828 -#define I2C3_SCL_PAD_CFG0 0x5438 -#define MF_PLT_CLK1_PAD_CFG0 0x4410 -#define I2C3_SDA_PAD_CFG0 0x5420 - -/* - * 0b0000 - 4GiB total - 2 x 2GiB Samsung K4B4G1646Q-HYK0 1600MHz - * 0b0001 - 4GiB total - 2 x 2GiB Hynix H5TC4G63CFR-PBA 1600MHz - * 0b0010- 2GiB total - 1 x 2GiB Samsung K4B4G1646Q-HYK0 1600MHz - * 0b0011 - 2GiB total - 1 x 2GiB Hynix H5TC4G63CFR-PBA 1600MHz - */ -static const uint32_t dual_channel_config = (1 << 0); - -static void *get_spd_pointer(char *spd_file_content, int total_spds, int *dual) -{ - int ram_id = 0; - ram_id |= get_gpio(COMMUNITY_GPSOUTHWEST_BASE, SATA_GP3_PAD_CFG0) << 0; - ram_id |= get_gpio(COMMUNITY_GPSOUTHWEST_BASE, I2C3_SCL_PAD_CFG0) << 1; - ram_id |= get_gpio(COMMUNITY_GPSOUTHEAST_BASE, MF_PLT_CLK1_PAD_CFG0) - << 2; - ram_id |= get_gpio(COMMUNITY_GPSOUTHWEST_BASE, I2C3_SDA_PAD_CFG0) << 3; - - /* - * There are only 2 SPDs supported on Cyan Board: - * Samsung 4G:0000 & Hynix 2G:0011 - */ - - /* - * RAMID0 on the first boot does not read the correct value,so checking - * bit 1 is enough as WA - */ - if (ram_id > 0) - ram_id = 3; - printk(BIOS_DEBUG, "ram_id=%d, total_spds: %d\n", ram_id, total_spds); - - if (ram_id >= total_spds) - return NULL; - - /* Single channel configs */ - if (dual_channel_config & (1 << ram_id)) - *dual = 1; - - return &spd_file_content[SPD_SIZE * ram_id]; -} - -/* Copy SPD data for on-board memory */ -void mainboard_fill_spd_data(struct pei_data *ps) -{ - char *spd_file; - size_t spd_file_len; - void *spd_content; - int dual_channel = 0; - - /* Find the SPD data in CBFS. */ - spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD, - &spd_file_len); - if (!spd_file) - die("SPD data not found."); - - if (spd_file_len < SPD_SIZE) - die("Missing SPD data."); - - /* - * Both channels are always present in SPD data. Always use matched - * DIMMs so use the same SPD data for each DIMM. - */ - spd_content = get_spd_pointer(spd_file, - spd_file_len / SPD_SIZE, - &dual_channel); - if (IS_ENABLED(CONFIG_DISPLAY_SPD_DATA) && spd_content != NULL) { - printk(BIOS_DEBUG, "SPD Data:\n"); - hexdump(spd_content, SPD_SIZE); - printk(BIOS_DEBUG, "\n"); - } - - /* - * Set SPD and memory configuration: - * Memory type: 0=DimmInstalled, - * 1=SolderDownMemory, - * 2=DimmDisabled - */ - if (spd_content != NULL) { - ps->spd_data_ch0 = spd_content; - ps->spd_ch0_config = 1; - if (dual_channel) { - ps->spd_data_ch1 = spd_content; - ps->spd_ch1_config = 1; - } else { - ps->spd_ch1_config = 2; - } - } -}

1 0

Patch set updated for coreboot: soc/braswell: Fix leakage on V1P8S rail
by Hannah Williams 25 Jan '16

25 Jan '16

Hannah Williams (hannah.williams(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12730 -gerrit commit 2f3f4250f6466dad2b7fb42769717824bb5c787e Author: Shobhit Srivastava <shobhit.srivastava(a)intel.com> Date: Mon Aug 10 11:48:23 2015 +0530 soc/braswell: Fix leakage on V1P8S rail Tristate MMC1_RCLK pin to fix leakage on V1P8S rail. Original-Reviewed-on: https://chromium-review.googlesource.com/292043 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Tested-by: Divagar Mohandass <divagar.mohandass(a)intel.com> Change-Id: I76cc9211ba93b2596d3c0d772d99f8934656e01c Signed-off-by: Shobhit Srivastava <shobhit.srivastava(a)intel.com> --- src/soc/intel/braswell/include/soc/gpio.h | 1 + src/soc/intel/braswell/smihandler.c | 2 ++ 2 files changed, 3 insertions(+) diff --git a/src/soc/intel/braswell/include/soc/gpio.h b/src/soc/intel/braswell/include/soc/gpio.h index 4ab6592..c7bfb65 100644 --- a/src/soc/intel/braswell/include/soc/gpio.h +++ b/src/soc/intel/braswell/include/soc/gpio.h @@ -105,6 +105,7 @@ #define MMC1_D5_MMIO_OFFSET GPIO_OFFSET(65) #define MMC1_D6_MMIO_OFFSET GPIO_OFFSET(63) #define MMC1_D7_MMIO_OFFSET GPIO_OFFSET(68) +#define MMC1_RCLK_OFFSET GPIO_OFFSET(69) #define HV_DDI2_DDC_SDA_MMIO_OFFSET GPIO_OFFSET(62) #define HV_DDI2_DDC_SCL_MMIO_OFFSET GPIO_OFFSET(67) #define CFIO_139_MMIO_OFFSET GPIO_OFFSET(64) diff --git a/src/soc/intel/braswell/smihandler.c b/src/soc/intel/braswell/smihandler.c index dabc0d2..760fba3 100644 --- a/src/soc/intel/braswell/smihandler.c +++ b/src/soc/intel/braswell/smihandler.c @@ -117,6 +117,8 @@ static void tristate_gpios(uint32_t val) MMC1_D6_MMIO_OFFSET, val); write32((void *)COMMUNITY_GPSOUTHEAST_BASE + MMC1_D7_MMIO_OFFSET, val); + write32((void *)COMMUNITY_GPSOUTHEAST_BASE + + MMC1_RCLK_OFFSET, val); /* Tri-state HDMI */ write32((void *)COMMUNITY_GPNORTH_BASE +

1 0

Patch merged into coreboot/master: Braswell: Implement Gpio library functions to read RAMID
by gerrit＠coreboot.org 25 Jan '16

25 Jan '16

the following patch was just integrated into master: commit ed7275f2c34e17585c59ecbcabaa813afc20aac0 Author: Subrata Banik <subrata.banik(a)intel.com> Date: Sat Aug 22 10:36:41 2015 +0530 Braswell: Implement Gpio library functions to read RAMID Added GPIO library code to allow all BSW board specific code to use memory configuration GPIOs in GPIO Input mode and read them to determine which memory type is on the board. Also added other GPIO related APIs to support GPIO access in BSW. Original-Reviewed-on: https://chromium-review.googlesource.com/294893 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Change-Id: Idd65136c0449f0cdebfae12a510985e29889fa2b Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> Signed-off-by: Hannah Williams <hannah.williams(a)intel.com> Reviewed-on: https://review.coreboot.org/12735 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/12735 for details. -gerrit

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit January 2016