coreboot-gerrit January 2016

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Patch set updated for coreboot: intel/strago: Cleanup GPIO config
by Hannah Williams 25 Jan '16

25 Jan '16

Hannah Williams (hannah.williams(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13431 -gerrit commit 592435b4fdb49c59db94372838c97da32055dd30 Author: Hannah Williams <hannah.williams(a)intel.com> Date: Mon Jan 25 14:25:23 2016 -0800 intel/strago: Cleanup GPIO config Fix GPIO config for this board Change-Id: Iecb23df465a540a71f7268c5aac48617dc74ebf2 Signed-off-by: Hannah Williams <hannah.williams(a)intel.com> --- src/mainboard/intel/strago/gpio.c | 16 ++++++++++------ 1 file changed, 10 insertions(+), 6 deletions(-) diff --git a/src/mainboard/intel/strago/gpio.c b/src/mainboard/intel/strago/gpio.c index 8b6a0e7..c57a573 100755 --- a/src/mainboard/intel/strago/gpio.c +++ b/src/mainboard/intel/strago/gpio.c @@ -74,7 +74,9 @@ static const struct soc_gpio_map gpse_gpio_map[] = { Native_M1, /* 78 SDMMC3_PWR_EN_B */ GPIO_NC, /* 79 GPI ILB_SERIRQ */ Native_M1, /* 80 USB_OC0_B */ - NATIVE_INT(1, L1), /* 81 SDMMC3_CD_B */ + GPI(trig_edge_both, L1, P_20K_H, non_maskable, + en_edge_detect, NA , NA), + /* 81 SDMMC3_CD_B */ GPIO_NC, /* 82 spkr asummed gpio number */ Native_M1, /* 83 SUSPWRDNACK */ SPARE_PIN,/* 84 spare pin */ @@ -112,11 +114,11 @@ static const struct soc_gpio_map gpsw_gpio_map[] = { GPI(trig_edge_both, L2, P_1K_H, non_maskable, en_edge_detect, NA, NA), /* 37 MF_HDA_DOCKENB */ NATIVE_PU1K_CSEN_INVTX(1), /* 45 I2C5_SDA */ - GPIO_NC, /* 46 I2C4_SDA */ + NATIVE_PU1K_CSEN_INVTX(1), /* 46 I2C4_SDA */ NATIVE_PU1K_CSEN_INVTX(1), /* 47 I2C6_SDA */ NATIVE_PU1K_CSEN_INVTX(1), /* 48 I2C5_SCL */ GPIO_NC, /* 49 I2C_NFC_SDA */ - GPIO_NC, /* 50 I2C4_SCL */ + NATIVE_PU1K_CSEN_INVTX(1), /* 50 I2C4_SCL */ NATIVE_PU1K_CSEN_INVTX(1), /* 51 I2C6_SCL */ GPIO_NC, /* 52 I2C_NFC_SCL */ NATIVE_PU1K_CSEN_INVTX(1), /* 60 I2C1_SDA */ @@ -128,7 +130,7 @@ static const struct soc_gpio_map gpsw_gpio_map[] = { NATIVE_PU1K_CSEN_INVTX(1), /* 66 I2C2_SCL */ GPIO_INPUT_NO_PULL,/* 67 I2C3_SCL,RAMID1 */ GPIO_OUT_HIGH, /* 75 SATA_GP0 */ - GPI(trig_edge_low, L0, P_1K_H, non_maskable, NA, NA, NA), + GPIO_NC, /* 76 GPI SATA_GP1 */ Native_M1, /* 77 SATA_LEDN */ GPIO_NC, /* 80 SATA_GP3 */ @@ -169,9 +171,11 @@ static const struct soc_gpio_map gpn_gpio_map[] = { /* 17 GPIO_SUS3 */ GPI(trig_edge_low, L1, P_1K_H, non_maskable, NA, UNMASK_WAKE, NA), /* 18 GPIO_SUS7 */ - GPO_FUNC(0, 0), /* 19 GPIO_SUS1 */ + GPI(trig_edge_low, L3, P_1K_H, non_maskable, NA, UNMASK_WAKE, NA), + /* 19 GPIO_SUS1 */ GPIO_NC, /* 20 GPIO_SUS5 */ - GPI(trig_edge_high, L2, NA, non_maskable, en_edge_rx_data, NA , NA), + GPI(trig_edge_high, L2, P_20K_H, non_maskable, + en_edge_rx_data, NA , NA), /* 21 SEC_GPIO_SUS11 */ GPIO_NC, /* 22 GPIO_SUS4 */ GPIO_NC,

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Patch set updated for coreboot: intel/strago: Cleanup GPIO config
by Hannah Williams 25 Jan '16

25 Jan '16

Hannah Williams (hannah.williams(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13431 -gerrit commit eb563bf217ceac932f8da284e1c04bd6c34a3eab Author: Hannah Williams <hannah.williams(a)intel.com> Date: Mon Jan 25 14:25:23 2016 -0800 intel/strago: Cleanup GPIO config Fix GPIO config for this board Change-Id: Iecb23df465a540a71f7268c5aac48617dc74ebf2 Signed-off-by: Hannah Williams <hannah.williams(a)intel.com> --- src/mainboard/intel/strago/gpio.c | 18 ++++++++++-------- 1 file changed, 10 insertions(+), 8 deletions(-) diff --git a/src/mainboard/intel/strago/gpio.c b/src/mainboard/intel/strago/gpio.c index 8b6a0e7..ad038a3 100755 --- a/src/mainboard/intel/strago/gpio.c +++ b/src/mainboard/intel/strago/gpio.c @@ -17,8 +17,6 @@ #include "irqroute.h" #include <soc/gpio.h> #include <stdlib.h> -#include <boardid.h> -#include "onboard.h" #include "gpio.h" /* South East Community */ @@ -74,7 +72,9 @@ static const struct soc_gpio_map gpse_gpio_map[] = { Native_M1, /* 78 SDMMC3_PWR_EN_B */ GPIO_NC, /* 79 GPI ILB_SERIRQ */ Native_M1, /* 80 USB_OC0_B */ - NATIVE_INT(1, L1), /* 81 SDMMC3_CD_B */ + GPI(trig_edge_both, L1, P_20K_H, non_maskable, + en_edge_detect, NA , NA), + /* 81 SDMMC3_CD_B */ GPIO_NC, /* 82 spkr asummed gpio number */ Native_M1, /* 83 SUSPWRDNACK */ SPARE_PIN,/* 84 spare pin */ @@ -112,11 +112,11 @@ static const struct soc_gpio_map gpsw_gpio_map[] = { GPI(trig_edge_both, L2, P_1K_H, non_maskable, en_edge_detect, NA, NA), /* 37 MF_HDA_DOCKENB */ NATIVE_PU1K_CSEN_INVTX(1), /* 45 I2C5_SDA */ - GPIO_NC, /* 46 I2C4_SDA */ + NATIVE_PU1K_CSEN_INVTX(1), /* 46 I2C4_SDA */ NATIVE_PU1K_CSEN_INVTX(1), /* 47 I2C6_SDA */ NATIVE_PU1K_CSEN_INVTX(1), /* 48 I2C5_SCL */ GPIO_NC, /* 49 I2C_NFC_SDA */ - GPIO_NC, /* 50 I2C4_SCL */ + NATIVE_PU1K_CSEN_INVTX(1), /* 50 I2C4_SCL */ NATIVE_PU1K_CSEN_INVTX(1), /* 51 I2C6_SCL */ GPIO_NC, /* 52 I2C_NFC_SCL */ NATIVE_PU1K_CSEN_INVTX(1), /* 60 I2C1_SDA */ @@ -128,7 +128,7 @@ static const struct soc_gpio_map gpsw_gpio_map[] = { NATIVE_PU1K_CSEN_INVTX(1), /* 66 I2C2_SCL */ GPIO_INPUT_NO_PULL,/* 67 I2C3_SCL,RAMID1 */ GPIO_OUT_HIGH, /* 75 SATA_GP0 */ - GPI(trig_edge_low, L0, P_1K_H, non_maskable, NA, NA, NA), + GPIO_NC, /* 76 GPI SATA_GP1 */ Native_M1, /* 77 SATA_LEDN */ GPIO_NC, /* 80 SATA_GP3 */ @@ -169,9 +169,11 @@ static const struct soc_gpio_map gpn_gpio_map[] = { /* 17 GPIO_SUS3 */ GPI(trig_edge_low, L1, P_1K_H, non_maskable, NA, UNMASK_WAKE, NA), /* 18 GPIO_SUS7 */ - GPO_FUNC(0, 0), /* 19 GPIO_SUS1 */ + GPI(trig_edge_low, L3, P_1K_H, non_maskable, NA, UNMASK_WAKE, NA), + /* 19 GPIO_SUS1 */ GPIO_NC, /* 20 GPIO_SUS5 */ - GPI(trig_edge_high, L2, NA, non_maskable, en_edge_rx_data, NA , NA), + GPI(trig_edge_high, L2, P_20K_H, non_maskable, + en_edge_rx_data, NA , NA), /* 21 SEC_GPIO_SUS11 */ GPIO_NC, /* 22 GPIO_SUS4 */ GPIO_NC,

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Patch merged into coreboot/master: nb/intel/pineview: Increase MMCONF decoding to 256 busses
by gerrit＠coreboot.org 25 Jan '16

25 Jan '16

the following patch was just integrated into master: commit 2cfab90baa2eca04f6a522b65ce23650e5af56ff Author: Damien Zammit <damien(a)zamaudio.com> Date: Mon Jan 18 16:39:51 2016 +1100 nb/intel/pineview: Increase MMCONF decoding to 256 busses Linux kernel detects 256 busses but previously only 64 were allocated. Removes warning in OS. Change-Id: Id83c85e60025a04acbe6a53dfea6878222d8791f Signed-off-by: Damien Zammit <damien(a)zamaudio.com> Reviewed-on: https://review.coreboot.org/13033 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> See https://review.coreboot.org/13033 for details. -gerrit

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Patch merged into coreboot/master: Makefile.inc: error if UPDATE_IMAGE is enabled with no coreboot.rom
by gerrit＠coreboot.org 25 Jan '16

25 Jan '16

the following patch was just integrated into master: commit b8f8cdbd9ea5a3fd5f73e40c63edc8f33f2b53f3 Author: Martin Roth <martinroth(a)google.com> Date: Wed Jan 20 14:54:27 2016 -0700 Makefile.inc: error if UPDATE_IMAGE is enabled with no coreboot.rom Instead of just failing with the statement: 'mv: cannot stat ‘coreboot.rom’: No such file or directory', fail with an error that helps the user understand the issue. Change-Id: Ie693d45710f599991514e0803a7c444636e473c9 Signed-off-by: Martin Roth <martinroth(a)google.com> Reviewed-on: https://review.coreboot.org/13065 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h(a)gmx.de> See https://review.coreboot.org/13065 for details. -gerrit

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Patch merged into coreboot/master: superiotool: fix out-of-box NetBSD Makefile support
by gerrit＠coreboot.org 25 Jan '16

25 Jan '16

the following patch was just integrated into master: commit decefea2729cb691d06f4c68c0c0d60c039d389f Author: Andrey Korolyov <andrey(a)xdel.ru> Date: Mon Jan 4 02:20:04 2016 +0300 superiotool: fix out-of-box NetBSD Makefile support Add NetBSD-specific locations under pkg/ and missing linker flag for libpciutils. Change-Id: I812817a374aaba561b28d8a22f20d238c9dca32b Signed-off-by: Andrey Korolyov <andrey(a)xdel.ru> Reviewed-on: https://review.coreboot.org/12830 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See https://review.coreboot.org/12830 for details. -gerrit

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Patch merged into coreboot/master: buildgcc: Help GMP build with 32-bit NetBSD
by gerrit＠coreboot.org 25 Jan '16

25 Jan '16

the following patch was just integrated into master: commit de45c590808184be24b5f9d271b93740da7c0976 Author: Nico Huber <nico.h(a)gmx.de> Date: Wed Jan 20 23:22:33 2016 +0100 buildgcc: Help GMP build with 32-bit NetBSD GMP's configure tries to build for 64-bit with a 32-bit userspace on NetBSD too. Help it by forcing ABI=32. Change-Id: I290ea0ef1626fdd88dc3ff74fadb9578ef6a1c9c Signed-off-by: Nico Huber <nico.h(a)gmx.de> Reviewed-on: https://review.coreboot.org/13067 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/13067 for details. -gerrit

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Patch merged into coreboot/master: src/arch: Update license headers missing paragraph 2
by gerrit＠coreboot.org 25 Jan '16

25 Jan '16

the following patch was just integrated into master: commit 4af5886ab12e852f4a28aaeaeb2c19873193c601 Author: Martin Roth <martinroth(a)google.com> Date: Thu Jan 21 13:15:16 2016 -0700 src/arch: Update license headers missing paragraph 2 For the coreboot license header, we want to use two paragraphs. See the section 'Common License Header' in the coreboot wiki for more details. Change-Id: I4a43f3573364a17b5d7f63b1f83b8ae424981b18 Signed-off-by: Martin Roth <martinroth(a)google.com> Reviewed-on: https://review.coreboot.org/13118 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See https://review.coreboot.org/13118 for details. -gerrit

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Patch merged into coreboot/master: ga-g41m-es2l: Instead of forcing native VGA, make it selectable
by gerrit＠coreboot.org 25 Jan '16

25 Jan '16

the following patch was just integrated into master: commit 345f2b7d6bb0d67d9836a687041d9dbf4af755a3 Author: Martin Roth <martinroth(a)google.com> Date: Tue Jan 5 19:30:37 2016 -0700 ga-g41m-es2l: Instead of forcing native VGA, make it selectable This allows the native VGA to be disabled for debug, or if someone wants to use the vbios. Change-Id: I59a94fa0d02bfe254c8a598e15d3d9d73ecfe650 Signed-off-by: Martin Roth <martinroth(a)google.com> Reviewed-on: https://review.coreboot.org/12848 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Reviewed-by: Damien Zammit <damien(a)zamaudio.com> See https://review.coreboot.org/12848 for details. -gerrit

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Patch merged into coreboot/master: mainboard/intel/d510mo: Licence fixes and azalia verb table
by gerrit＠coreboot.org 25 Jan '16

25 Jan '16

the following patch was just integrated into master: commit 2950cd2de173f8a4f0ffac32823b23774dac4db5 Author: Damien Zammit <damien(a)zamaudio.com> Date: Wed Dec 2 14:03:02 2015 +1100 mainboard/intel/d510mo: Licence fixes and azalia verb table Azalia verb table replicated from vendor bios. Licence headers added where appropriate. Change-Id: I29e4fe433dee6c5f30fe36055fc9a8bf2062fef5 Signed-off-by: Damien Zammit <damien(a)zamaudio.com> Reviewed-on: https://review.coreboot.org/12621 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> See https://review.coreboot.org/12621 for details. -gerrit

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Patch set updated for coreboot: intel/strago: Cleanup GPIO config
by Hannah Williams 25 Jan '16

25 Jan '16

Hannah Williams (hannah.williams(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13431 -gerrit commit dd0bc627806c447141157e670b7754318fa8f19e Author: Hannah Williams <hannah.williams(a)intel.com> Date: Mon Jan 25 14:25:23 2016 -0800 intel/strago: Cleanup GPIO config Fix GPIO config for this board Change-Id: Iecb23df465a540a71f7268c5aac48617dc74ebf2 Signed-off-by: Hannah Williams <hannah.williams(a)intel.com> --- src/mainboard/intel/strago/gpio.c | 18 ++++++++++-------- 1 file changed, 10 insertions(+), 8 deletions(-) diff --git a/src/mainboard/intel/strago/gpio.c b/src/mainboard/intel/strago/gpio.c index 8b6a0e7..ad038a3 100755 --- a/src/mainboard/intel/strago/gpio.c +++ b/src/mainboard/intel/strago/gpio.c @@ -17,8 +17,6 @@ #include "irqroute.h" #include <soc/gpio.h> #include <stdlib.h> -#include <boardid.h> -#include "onboard.h" #include "gpio.h" /* South East Community */ @@ -74,7 +72,9 @@ static const struct soc_gpio_map gpse_gpio_map[] = { Native_M1, /* 78 SDMMC3_PWR_EN_B */ GPIO_NC, /* 79 GPI ILB_SERIRQ */ Native_M1, /* 80 USB_OC0_B */ - NATIVE_INT(1, L1), /* 81 SDMMC3_CD_B */ + GPI(trig_edge_both, L1, P_20K_H, non_maskable, + en_edge_detect, NA , NA), + /* 81 SDMMC3_CD_B */ GPIO_NC, /* 82 spkr asummed gpio number */ Native_M1, /* 83 SUSPWRDNACK */ SPARE_PIN,/* 84 spare pin */ @@ -112,11 +112,11 @@ static const struct soc_gpio_map gpsw_gpio_map[] = { GPI(trig_edge_both, L2, P_1K_H, non_maskable, en_edge_detect, NA, NA), /* 37 MF_HDA_DOCKENB */ NATIVE_PU1K_CSEN_INVTX(1), /* 45 I2C5_SDA */ - GPIO_NC, /* 46 I2C4_SDA */ + NATIVE_PU1K_CSEN_INVTX(1), /* 46 I2C4_SDA */ NATIVE_PU1K_CSEN_INVTX(1), /* 47 I2C6_SDA */ NATIVE_PU1K_CSEN_INVTX(1), /* 48 I2C5_SCL */ GPIO_NC, /* 49 I2C_NFC_SDA */ - GPIO_NC, /* 50 I2C4_SCL */ + NATIVE_PU1K_CSEN_INVTX(1), /* 50 I2C4_SCL */ NATIVE_PU1K_CSEN_INVTX(1), /* 51 I2C6_SCL */ GPIO_NC, /* 52 I2C_NFC_SCL */ NATIVE_PU1K_CSEN_INVTX(1), /* 60 I2C1_SDA */ @@ -128,7 +128,7 @@ static const struct soc_gpio_map gpsw_gpio_map[] = { NATIVE_PU1K_CSEN_INVTX(1), /* 66 I2C2_SCL */ GPIO_INPUT_NO_PULL,/* 67 I2C3_SCL,RAMID1 */ GPIO_OUT_HIGH, /* 75 SATA_GP0 */ - GPI(trig_edge_low, L0, P_1K_H, non_maskable, NA, NA, NA), + GPIO_NC, /* 76 GPI SATA_GP1 */ Native_M1, /* 77 SATA_LEDN */ GPIO_NC, /* 80 SATA_GP3 */ @@ -169,9 +169,11 @@ static const struct soc_gpio_map gpn_gpio_map[] = { /* 17 GPIO_SUS3 */ GPI(trig_edge_low, L1, P_1K_H, non_maskable, NA, UNMASK_WAKE, NA), /* 18 GPIO_SUS7 */ - GPO_FUNC(0, 0), /* 19 GPIO_SUS1 */ + GPI(trig_edge_low, L3, P_1K_H, non_maskable, NA, UNMASK_WAKE, NA), + /* 19 GPIO_SUS1 */ GPIO_NC, /* 20 GPIO_SUS5 */ - GPI(trig_edge_high, L2, NA, non_maskable, en_edge_rx_data, NA , NA), + GPI(trig_edge_high, L2, P_20K_H, non_maskable, + en_edge_rx_data, NA , NA), /* 21 SEC_GPIO_SUS11 */ GPIO_NC, /* 22 GPIO_SUS4 */ GPIO_NC,

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coreboot-gerrit January 2016