coreboot-gerrit January 2016

coreboot-gerrit@coreboot.org

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2471 discussions

New patch to review for coreboot: kconfig_lint: merge 'git grep' and 'grep' exclude dir and files
by Martin Roth 25 Jan '16

25 Jan '16

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13456 -gerrit commit ad04facf1bb3212c495bcf65f4f38907c2492e50 Author: Martin Roth <martinroth(a)google.com> Date: Mon Jan 25 16:08:27 2016 -0700 kconfig_lint: merge 'git grep' and 'grep' exclude dir and files The code had originally been using standard grep to look through the coreboot tree for Kconfig symbols. When this was switched to git grep, the --exclude-dir options didn't work, and nothing was added to exclude the directories that shouldn't be searched for symbols. This resulted in invalid warnings as it searched directories that had Kconfig symbols for other projects. This merges the exclusion list for both the regular and git versions of grep for consistent behavior. Change-Id: I69a1e0b30fecca152e02a511c82248b6091b3d8b Signed-off-by: Martin Roth <martinroth(a)google.com> --- util/lint/kconfig_lint | 22 +++++++--------------- 1 file changed, 7 insertions(+), 15 deletions(-) diff --git a/util/lint/kconfig_lint b/util/lint/kconfig_lint index 7fa0d88..4315768 100755 --- a/util/lint/kconfig_lint +++ b/util/lint/kconfig_lint @@ -4,7 +4,7 @@ # This file is part of the coreboot project. # # Copyright (C) 2015 Martin L Roth <gaumless(a)gmail.com> -# Copyright (C) 2015 Google, Inc. +# Copyright (C) 2015-2016 Google, Inc. # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by @@ -38,11 +38,10 @@ my $top_dir = "."; # Directory where Kconfig is run my $root_dir = "src"; # Directory of the top level Kconfig file my $errors_found = 0; # count of errors my $warnings_found = 0; -my $exclude_dirs = - '--exclude-dir="build" --exclude-dir="coreboot-builds" ' - . '--exclude-dir="payloads" --exclude-dir="configs" ' - . '--exclude-dir="util"'; # directories to exclude when searching for used symbols - NOT USED FOR GIT GREP (TODO) -my @exclude_files = ( '\.txt$', '\.tex$', 'config', '\.tags' ); #files to exclude when looking for symbols +my $exclude_dirs_and_files = + '^build/\|^coreboot-builds/\|^payloads/libpayload\|^payloads/coreinfo\|^configs/\|^util/\|^\.git/' + . '\|' . # directories to exclude when searching for used symbols + '\.txt$\|\.tex$\|\.tags'; #files to exclude when looking for symbols my $config_file = ""; # name of config file to load symbol values from. my @wholeconfig; # document the entire kconfig structure my %loaded_files; # list of each Kconfig file loaded @@ -345,10 +344,10 @@ sub collect_used_symbols { # find all references to CONFIG_ statements in the tree if ($dont_use_git_grep) { - @collected_symbols = `grep -Irn $exclude_dirs -- "CONFIG_"`; + @collected_symbols = `grep -Irn -- "CONFIG_" | grep -v '$exclude_dirs_and_files'`; } else { - @collected_symbols = `git grep -In -- "CONFIG_"`; + @collected_symbols = `git grep -In -- "CONFIG_" | grep -v '$exclude_dirs_and_files'`; } my @used_symbols = @collected_symbols; @@ -362,13 +361,6 @@ sub collect_used_symbols { $filename = $1; } - my $skip = 0; - foreach my $exfile (@exclude_files) { - $skip = ( $filename =~ /$exfile/ ); - last if $skip; - } - last if $skip; - if ( exists $used_symbols{$symbol}{count} ) { $used_symbols{$symbol}{count}++; }

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New patch to review for coreboot: mb/intel/d510mo: Explicitly select NIC on PCI in devicetree
by Damien Zammit 25 Jan '16

25 Jan '16

Damien Zammit (damien(a)zamaudio.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13455 -gerrit commit f9716d67ba64673d1c5a806942c513945fc114e3 Author: Damien Zammit <damien(a)zamaudio.com> Date: Tue Jan 26 14:06:26 2016 +1100 mb/intel/d510mo: Explicitly select NIC on PCI in devicetree Change-Id: Ic6682865dd17672c3782bfba9511cd120d1657c1 Signed-off-by: Damien Zammit <damien(a)zamaudio.com> --- src/mainboard/intel/d510mo/devicetree.cb | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/src/mainboard/intel/d510mo/devicetree.cb b/src/mainboard/intel/d510mo/devicetree.cb index c0f38de..3cfcf5f 100644 --- a/src/mainboard/intel/d510mo/devicetree.cb +++ b/src/mainboard/intel/d510mo/devicetree.cb @@ -43,7 +43,10 @@ chip northbridge/intel/pineview # Northbridge register "gpe0_en" = "0x20000040" device pci 1b.0 on end # Audio - device pci 1c.0 on end # PCIe 1 + device pci 1c.0 on # PCIe 1 + device pci 0.0 on # NIC + end + end device pci 1c.1 on end # PCIe 2 device pci 1c.2 on end # PCIe 3 device pci 1c.3 on end # PCIe 4

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New patch to review for coreboot: mb/intel/d510mo: Use SATA AHCI by default
by Damien Zammit 25 Jan '16

25 Jan '16

Damien Zammit (damien(a)zamaudio.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13454 -gerrit commit 39cc91d5dbf47ac28cc730a2f3a7e65d2cefe866 Author: Damien Zammit <damien(a)zamaudio.com> Date: Tue Jan 26 14:03:37 2016 +1100 mb/intel/d510mo: Use SATA AHCI by default Change-Id: I6f9772c5bcf9a50dfbc3d1cfaeb79f4454d1fb27 Signed-off-by: Damien Zammit <damien(a)zamaudio.com> --- src/mainboard/intel/d510mo/devicetree.cb | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/src/mainboard/intel/d510mo/devicetree.cb b/src/mainboard/intel/d510mo/devicetree.cb index df5a0f9..c0f38de 100644 --- a/src/mainboard/intel/d510mo/devicetree.cb +++ b/src/mainboard/intel/d510mo/devicetree.cb @@ -38,10 +38,8 @@ chip northbridge/intel/pineview # Northbridge register "pirqf_routing" = "0x0b" register "pirqg_routing" = "0x0b" register "pirqh_routing" = "0x0b" - register "ide_legacy_combined" = "0x1" - register "ide_enable_primary" = "0x1" - register "ide_enable_secondary" = "0x0" - register "sata_ahci" = "0x0" + register "sata_ahci" = "0x1" + register "sata_ports_implemented" = "0x3" register "gpe0_en" = "0x20000040" device pci 1b.0 on end # Audio

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New patch to review for coreboot: mb/intel/d510mo: DSDT fix
by Damien Zammit 25 Jan '16

25 Jan '16

Damien Zammit (damien(a)zamaudio.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13453 -gerrit commit e798f4eaeecf87ea14d76b6729c76937ff7af110 Author: Damien Zammit <damien(a)zamaudio.com> Date: Tue Jan 26 13:57:17 2016 +1100 mb/intel/d510mo: DSDT fix Change-Id: I80853cadb4762d9bb34926e31d65d248c5683417 Signed-off-by: Damien Zammit <damien(a)zamaudio.com> --- src/mainboard/intel/d510mo/acpi/platform.asl | 28 ++++++++++++++++++++++++++++ src/mainboard/intel/d510mo/dsdt.asl | 5 ++++- 2 files changed, 32 insertions(+), 1 deletion(-) diff --git a/src/mainboard/intel/d510mo/acpi/platform.asl b/src/mainboard/intel/d510mo/acpi/platform.asl new file mode 100644 index 0000000..6c92a4e --- /dev/null +++ b/src/mainboard/intel/d510mo/acpi/platform.asl @@ -0,0 +1,28 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Damien Zammit <damien(a)zamaudio.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Method(_PIC, 1) +{ + /* Remember the OS' IRQ routing choice. */ + Store(Arg0, PICM) +} + +/* SMI I/O Trap */ +Method(TRAP, 1, Serialized) +{ + Store (Arg0, SMIF) /* SMI Function */ + Store (0, TRP0) /* Generate trap */ + Return (SMIF) /* Return value of SMI handler */ +} diff --git a/src/mainboard/intel/d510mo/dsdt.asl b/src/mainboard/intel/d510mo/dsdt.asl index c1f72f9..a7788bd 100644 --- a/src/mainboard/intel/d510mo/dsdt.asl +++ b/src/mainboard/intel/d510mo/dsdt.asl @@ -2,7 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2015 Damien Zammit <damien(a)zamaudio.com> + * Copyright (C) 2015 Damien Zammit <damien(a)zamaudio.com> * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -23,8 +23,11 @@ DefinitionBlock( 0x20090419 // OEM revision ) { + #include "acpi/platform.asl" #include <southbridge/intel/i82801gx/acpi/globalnvs.asl> + #include <cpu/intel/common/acpi/cpu.asl> + Scope (\_SB) { Device (PCI0) {

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New patch to review for coreboot: mb/intel/d510mo: GPIO and GPEN fix
by Damien Zammit 25 Jan '16

25 Jan '16

Damien Zammit (damien(a)zamaudio.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13452 -gerrit commit 1216827b4d9ca8fc32b401edf1adc0a2010e71dd Author: Damien Zammit <damien(a)zamaudio.com> Date: Tue Jan 26 13:52:33 2016 +1100 mb/intel/d510mo: GPIO and GPEN fix Change-Id: I56c0a55d57d8beabcb33cf1984b037556a71a8b9 Signed-off-by: Damien Zammit <damien(a)zamaudio.com> --- src/mainboard/intel/d510mo/devicetree.cb | 1 + src/mainboard/intel/d510mo/romstage.c | 1 + 2 files changed, 2 insertions(+) diff --git a/src/mainboard/intel/d510mo/devicetree.cb b/src/mainboard/intel/d510mo/devicetree.cb index 221cc54..c6f39a0 100644 --- a/src/mainboard/intel/d510mo/devicetree.cb +++ b/src/mainboard/intel/d510mo/devicetree.cb @@ -36,6 +36,7 @@ chip northbridge/intel/pineview # Northbridge register "ide_enable_primary" = "0x1" register "ide_enable_secondary" = "0x0" register "sata_ahci" = "0x0" + register "gpe0_en" = "0x20000040" device pci 1b.0 on end # Audio device pci 1c.0 on end # PCIe 1 diff --git a/src/mainboard/intel/d510mo/romstage.c b/src/mainboard/intel/d510mo/romstage.c index b0bd0c0..6b4f0f6 100644 --- a/src/mainboard/intel/d510mo/romstage.c +++ b/src/mainboard/intel/d510mo/romstage.c @@ -50,6 +50,7 @@ static void mb_gpio_init(void) outl(0x1ff9f7c1, DEFAULT_GPIOBASE + 0x00); /* GPIO_USE_SEL */ outl(0xe0e9e803, DEFAULT_GPIOBASE + 0x04); /* GP_IO_SEL */ outl(0xece9e842, DEFAULT_GPIOBASE + 0x0c); /* GP_LVL */ + outl(0x00000000, DEFAULT_GPIOBASE + 0x18); /* GPO_BLINK */ outl(0x00002000, DEFAULT_GPIOBASE + 0x2c); /* GPI_INV */ outl(0x000000fe, DEFAULT_GPIOBASE + 0x30); outl(0x0000007e, DEFAULT_GPIOBASE + 0x34);

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Patch set updated for coreboot: mb/intel/d510mo: Use native gfx initialization
by Damien Zammit 25 Jan '16

25 Jan '16

Damien Zammit (damien(a)zamaudio.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13034 -gerrit commit 600c790b9c1faeb8b275e69c0707b7a5fdeee254 Author: Damien Zammit <damien(a)zamaudio.com> Date: Tue Jan 26 13:55:43 2016 +1100 mb/intel/d510mo: Use native gfx initialization Change-Id: Ic4de7a762e90b379be3814afc61467e1cd099215 Signed-off-by: Damien Zammit <damien(a)zamaudio.com> --- src/mainboard/intel/d510mo/Kconfig | 2 ++ src/mainboard/intel/d510mo/devicetree.cb | 10 ++++++++-- src/mainboard/intel/d510mo/mainboard.c | 4 +++- 3 files changed, 13 insertions(+), 3 deletions(-) diff --git a/src/mainboard/intel/d510mo/Kconfig b/src/mainboard/intel/d510mo/Kconfig index 7981f92..7184665 100644 --- a/src/mainboard/intel/d510mo/Kconfig +++ b/src/mainboard/intel/d510mo/Kconfig @@ -23,6 +23,8 @@ config BOARD_SPECIFIC_OPTIONS select SUPERIO_WINBOND_W83627THG select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_1024 + select MAINBOARD_HAS_NATIVE_VGA_INIT + select INTEL_INT15 config MAX_CPUS int diff --git a/src/mainboard/intel/d510mo/devicetree.cb b/src/mainboard/intel/d510mo/devicetree.cb index c6f39a0..df5a0f9 100644 --- a/src/mainboard/intel/d510mo/devicetree.cb +++ b/src/mainboard/intel/d510mo/devicetree.cb @@ -15,14 +15,20 @@ # chip northbridge/intel/pineview # Northbridge + register "gfx.use_spread_spectrum_clock" = "0" + register "use_crt" = "1" + register "use_lvds" = "0" + device cpu_cluster 0 on # APIC cluster chip cpu/intel/socket_FCBGA559 # CPU device lapic 0 on end # APIC end end - device domain 0 on # PCI domain + device domain 0 on # PCI domain device pci 0.0 on end # Host Bridge - device pci 2.0 off end # Integrated graphics controller + device pci 1.0 off end # PEG + device pci 2.0 on end # Integrated graphics controller + device pci 2.1 on end # Integrated graphics controller 2 chip southbridge/intel/i82801gx # Southbridge register "pirqa_routing" = "0x0b" register "pirqb_routing" = "0x0b" diff --git a/src/mainboard/intel/d510mo/mainboard.c b/src/mainboard/intel/d510mo/mainboard.c index 94bee7e..4f0f32b 100644 --- a/src/mainboard/intel/d510mo/mainboard.c +++ b/src/mainboard/intel/d510mo/mainboard.c @@ -18,10 +18,12 @@ #include <device/pci_ops.h> #include <pc80/mc146818rtc.h> #include <device/pci.h> +#include <drivers/intel/gma/int15.h> static void mainboard_enable(device_t dev) { - dev->ops->init = NULL; + install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_NONE, + GMA_INT15_PANEL_FIT_DEFAULT, GMA_INT15_BOOT_DISPLAY_CRT, 0); } struct chip_operations mainboard_ops = {

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New patch to review for coreboot: mainboard/cubieboard: use bootblock_mainboard_early_init
by Iru Cai 25 Jan '16

25 Jan '16

Iru Cai (mytbk920423(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13448 -gerrit commit 854194639175ba885afe5d98dbbcb8e60df9dad2 Author: Iru Cai <mytbk920423(a)gmail.com> Date: Tue Jan 26 10:25:51 2016 +0800 mainboard/cubieboard: use bootblock_mainboard_early_init since commit f1e321001d5954096f06f9a43138219a9a46536e, the UART init should be in bootblock_mainboard_early_init() which runs before console init. (see src/lib/bootblock.c) Change-Id: Ib00afdd6e81e7689fbd743c8a5f547d424896d71 --- src/mainboard/cubietech/cubieboard/bootblock.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/cubietech/cubieboard/bootblock.c b/src/mainboard/cubietech/cubieboard/bootblock.c index e4a0313..738637e 100644 --- a/src/mainboard/cubietech/cubieboard/bootblock.c +++ b/src/mainboard/cubietech/cubieboard/bootblock.c @@ -127,7 +127,7 @@ static void cubieboard_raminit(void) ////ram_check((u32)test_base, (u32)test_base + 0x1000); } -void bootblock_mainboard_init(void) +void bootblock_mainboard_early_init(void) { /* A10 Timer init uses the 24MHz clock, not PLLs, so we can init it very * early on to get udelay, which is used almost everywhere else.

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Patch set updated for coreboot: Quark/Galileo: Enable Serial Port
by Leroy P Leahy 25 Jan '16

25 Jan '16

Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13445 -gerrit commit ebf0013da44e770b4b155c289f5c27f484f4f618 Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Sun Jan 24 18:51:58 2016 -0800 Quark/Galileo: Enable Serial Port Add the code to enable debug serial output using HSUART1: * Enable the code using Kconfig value ENABLE_BUILTIN_HSUART1 * Specify the portion of ESRAM to be used by romstage * Initialize the debug serial port * Note that the BIST value is always zero as validated in esram_init.inc * The initial TSC value is currently not saved! * Serial output indicates a successful test BRANCH=none BUG=None TEST=None Change-Id: I7e6181e8b9bc901c3ab236f0b56534850bb6bfd0 Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- src/mainboard/intel/galileo/Kconfig | 9 ++++ src/mainboard/intel/galileo/Makefile.inc | 4 ++ src/mainboard/intel/galileo/com_init.c | 32 +++++++++++++ src/soc/intel/quark/Kconfig | 30 ++++++++++++ src/soc/intel/quark/Makefile.inc | 4 ++ src/soc/intel/quark/include/soc/iomap.h | 31 +++++++++++++ src/soc/intel/quark/include/soc/pci_devs.h | 30 ++++++++++++ src/soc/intel/quark/include/soc/romstage.h | 33 +++++++++++++ src/soc/intel/quark/romstage/cache_as_ram.inc | 54 ++++++++++++++++++++- src/soc/intel/quark/tsc_freq.c | 40 ++++++++++++++++ src/soc/intel/quark/uart.c | 67 +++++++++++++++++++++++++++ 11 files changed, 332 insertions(+), 2 deletions(-) diff --git a/src/mainboard/intel/galileo/Kconfig b/src/mainboard/intel/galileo/Kconfig index eeb7ab4..b21df00 100755 --- a/src/mainboard/intel/galileo/Kconfig +++ b/src/mainboard/intel/galileo/Kconfig @@ -3,10 +3,19 @@ if BOARD_INTEL_GALILEO config BOARD_SPECIFIC_OPTIONS def_bool y select BOARD_ROMSIZE_KB_8192 + select ENABLE_BUILTIN_HSUART1 select HAVE_FSP_RAW_BIN select PLATFORM_USES_FSP1_1 select SOC_INTEL_QUARK +config DCACHE_RAM_BASE + hex + default 0x80070000 + +config DCACHE_RAM_SIZE + hex + default 0x00008000 + config HAVE_FSP_RAW_BIN bool "Should the Intel FSP binary be added to the flash image" help diff --git a/src/mainboard/intel/galileo/Makefile.inc b/src/mainboard/intel/galileo/Makefile.inc index 7a1603e..d6c5e52 100755 --- a/src/mainboard/intel/galileo/Makefile.inc +++ b/src/mainboard/intel/galileo/Makefile.inc @@ -18,6 +18,10 @@ ## Foundation, Inc. ## +romstage-$(CONFIG_ENABLE_BUILTIN_HSUART1) += com_init.c + +ramstage-$(CONFIG_ENABLE_BUILTIN_HSUART1) += com_init.c + # Add the FSP binary to the cbfs image ifeq ($(CONFIG_HAVE_FSP_RAW_BIN),y) cbfs-files-y += fsp.bin diff --git a/src/mainboard/intel/galileo/com_init.c b/src/mainboard/intel/galileo/com_init.c new file mode 100644 index 0000000..da50cfd --- /dev/null +++ b/src/mainboard/intel/galileo/com_init.c @@ -0,0 +1,32 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015-2016 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#include <fsp/car.h> +#include <device/pci.h> +#include <soc/iomap.h> +#include <soc/pci_devs.h> + +#if ENV_ROMSTAGE + +void car_mainboard_pre_console_init(void) +{ + pci_early_device_probe(0, HSUART1_DEV, UART_BASE_ADDRESS); +} +#endif /* ENV_ROMSTAGE */ diff --git a/src/soc/intel/quark/Kconfig b/src/soc/intel/quark/Kconfig index 197eb59..7b0cde1 100644 --- a/src/soc/intel/quark/Kconfig +++ b/src/soc/intel/quark/Kconfig @@ -11,6 +11,9 @@ config CPU_SPECIFIC_OPTIONS select ARCH_RAMSTAGE_X86_32 select ARCH_ROMSTAGE_X86_32 select ARCH_VERSTAGE_X86_32 + select SOC_INTEL_COMMON + select TSC_CONSTANT_RATE + select UDELAY_TSC config CBFS_SIZE hex @@ -56,6 +59,14 @@ config ENABLE_DEBUG_LED_TEMPRAMINIT help Indicate that TempRamInit was successful. +config ENABLE_BUILTIN_HSUART1 + bool "Enable built-in HSUART1" + default n + help + The Quark SoC has two HSUART. Choose this option to + configure the pads and enable HSUART1, which can be used for + the debug console. + config RMU_FILE string default "3rdparty/blobs/mainboard/$(MAINBOARDDIR)/rmu.bin" @@ -69,4 +80,23 @@ config RMU_LOC The location in CBFS that the RMU is located. It must match the strap-determined base address. +if ENABLE_BUILTIN_HSUART1 +config INTEL_UART_SPECIFIC_OPTIONS + def_bool y + select NO_UART_ON_SUPERIO + select DRIVERS_UART_8250MEM_32 + +config TTYS0_BASE + hex "HSUART1 Base Address" + depends on ENABLE_BUILTIN_HSUART1 + default 0xA0019000 + help + Memory mapped MMIO of HSUART1. + +config TTYS0_LCS + int + depends on ENABLE_BUILTIN_HSUART1 + default 3 + +endif # ENABLE_BUILTIN_HSUART1 endif # SOC_INTEL_QUARK diff --git a/src/soc/intel/quark/Makefile.inc b/src/soc/intel/quark/Makefile.inc index 39ad8af..bec1595 100644 --- a/src/soc/intel/quark/Makefile.inc +++ b/src/soc/intel/quark/Makefile.inc @@ -21,8 +21,12 @@ subdirs-y += romstage subdirs-y += ../../../cpu/x86/tsc romstage-y += memmap.c +romstage-y += tsc_freq.c +romstage-y += uart.c ramstage-y += memmap.c +ramstage-y += tsc_freq.c +ramstage-y += uart.c CPPFLAGS_common += -I$(src)/soc/intel/quark/include CPPFLAGS_common += -I$(src)/vendorcode/intel/fsp/fsp1_1/quark diff --git a/src/soc/intel/quark/include/soc/iomap.h b/src/soc/intel/quark/include/soc/iomap.h new file mode 100644 index 0000000..b6a7392 --- /dev/null +++ b/src/soc/intel/quark/include/soc/iomap.h @@ -0,0 +1,31 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015-2016 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _QUARK_IOMAP_H_ +#define _QUARK_IOMAP_H_ + +/* + * Memory Mapped IO base addresses. + */ + +/* UART MMIO */ +#define UART_BASE_ADDRESS CONFIG_TTYS0_BASE + +#endif /* _QUARK_IOMAP_H_ */ diff --git a/src/soc/intel/quark/include/soc/pci_devs.h b/src/soc/intel/quark/include/soc/pci_devs.h new file mode 100644 index 0000000..d022c66 --- /dev/null +++ b/src/soc/intel/quark/include/soc/pci_devs.h @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2013 Sage Electronic Engineering, LLC. + * Copyright (C) 2015-2016 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _QUARK_PCI_DEVS_H_ +#define _QUARK_PCI_DEVS_H_ + +/* IO Fabric 1 */ +#define SIO1_DEV 0x14 +# define HSUART1_DEV SIO1_DEV +# define HSUART1_FUNC 5 + +#endif /* _QUARK_PCI_DEVS_H_ */ diff --git a/src/soc/intel/quark/include/soc/romstage.h b/src/soc/intel/quark/include/soc/romstage.h new file mode 100644 index 0000000..8a80cd9 --- /dev/null +++ b/src/soc/intel/quark/include/soc/romstage.h @@ -0,0 +1,33 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2014 Sage Electronic Engineering, LLC. + * Copyright (C) 2015-2016 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _QUARK_ROMSTAGE_H_ +#define _QUARK_ROMSTAGE_H_ + +#if !defined(__PRE_RAM__) +#error "Don't include romstage.h from a ramstage compilation unit!" +#endif + +#include <fsp/util.h> + +int pci_early_device_func_probe(u8 bus, u8 dev, u8 func, u32 mmio_base); + +#endif /* _QUARK_ROMSTAGE_H_ */ diff --git a/src/soc/intel/quark/romstage/cache_as_ram.inc b/src/soc/intel/quark/romstage/cache_as_ram.inc index 80ac64d..89e6f88 100644 --- a/src/soc/intel/quark/romstage/cache_as_ram.inc +++ b/src/soc/intel/quark/romstage/cache_as_ram.inc @@ -112,8 +112,58 @@ CAR_init_done: movl %esi, %edx #endif /* CONFIG_ENABLE_DEBUG_LED_TEMPRAMINIT */ - clrl %eax - jmp halt2 + /* Setup bootloader stack */ + movl %edx, %esp + + /* + * eax: 0 + * ebp: FSP_INFO_HEADER address + * ecx: Temp RAM base + * edx: Temp RAM top + * edi: BIST value + * esp: Top of stack in temp RAM + */ + + /* Create cache_as_ram_params on stack */ + pushl %edx /* bootloader CAR end */ + pushl %ecx /* bootloader CAR begin */ + pushl %ebp /* FSP_INFO_HEADER */ + pushl %edi /* bist */ +// movd %mm1, %eax + pushl %eax /* tsc[63:32] */ +// movd %mm0, %eax + pushl %eax /* tsc[31:0] */ + pushl %esp /* pointer to cache_as_ram_params */ + + /* Save FSP_INFO_HEADER location in ebx */ + mov %ebp, %ebx + + /* Coreboot assumes stack/heap region will be zero */ + cld + movl %ecx, %edi + neg %ecx + /* Only clear up to current stack value. */ + add %esp, %ecx + shrl $2, %ecx + xorl %eax, %eax + rep stosl + +before_romstage: + post_code(0x23) + + /* Call cache_as_ram_main(struct cache_as_ram_params *) */ + call cache_as_ram_main + movb $0xB8, %ah + jmp .Lhlt + +/* One will never return from cache_as_ram_main() in verstage so there's + * no such thing as after ram init. */ +#if !ENV_VERSTAGE +#include "src/drivers/intel/fsp1_1/after_raminit.S" +#endif + + movb $0x69, %ah + jmp .Lhlt halt1: /* diff --git a/src/soc/intel/quark/tsc_freq.c b/src/soc/intel/quark/tsc_freq.c new file mode 100644 index 0000000..eef682a --- /dev/null +++ b/src/soc/intel/quark/tsc_freq.c @@ -0,0 +1,40 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stdint.h> +#include <cpu/x86/msr.h> +#include <cpu/x86/tsc.h> + +static unsigned long bus_freq_khz(void) +{ + /* cpu freq = 400 MHz */ + return 400 * 1000; +} + +unsigned long tsc_freq_mhz(void) +{ + /* assume ratio=1 */ + unsigned bclk_khz = bus_freq_khz(); + + if (!bclk_khz) + return 0; + + return (bclk_khz * 1) / 1000; +} diff --git a/src/soc/intel/quark/uart.c b/src/soc/intel/quark/uart.c new file mode 100644 index 0000000..2d39d1b --- /dev/null +++ b/src/soc/intel/quark/uart.c @@ -0,0 +1,67 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2003 Eric Biederman + * Copyright (C) 2006-2010 coresystems GmbH + * Copyright (C) 2015-2016 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +// Use simple device model for this file even in ramstage +#define __SIMPLE_DEVICE__ + +#include <console/uart.h> +#include <device/pci.h> +#include <device/pci_def.h> +#include <soc/pci_devs.h> + +#ifdef __PRE_RAM__ +int pci_early_device_probe(u8 bus, u8 dev, u32 mmio_base) +{ + uint16_t reg16; + + /* HSUART controller #1 (B0:D20:F5). */ + device_t uart_dev = PCI_DEV(bus, dev, HSUART1_FUNC); + + /* Decode BAR0(offset 0x10). */ + pci_write_config32(uart_dev, PCI_BASE_ADDRESS_0, mmio_base); + + /* Enable MEMBASE at CMD(offset 0x04). */ + reg16 = pci_read_config16(uart_dev, PCI_COMMAND); + reg16 |= PCI_COMMAND_MEMORY; + pci_write_config16(uart_dev, PCI_COMMAND, reg16); + + return 0; +} +#endif + +unsigned int uart_platform_refclk(void) +{ + return 44236800; +} + +uintptr_t uart_platform_base(int idx) +{ + if (idx < 6) { + /* HSUART controller #1 (B0:D20:F5). */ + device_t dev = PCI_DEV(0, HSUART1_DEV, HSUART1_FUNC); + + /* UART base address at BAR0(offset 0x10). */ + return (unsigned int) (pci_read_config32(dev, PCI_BASE_ADDRESS_0) & ~0xfff); + } + else { + return 0; + } +}

1 0

Patch set updated for coreboot: Quark: FSP MemoryInit Support
by Leroy P Leahy 25 Jan '16

25 Jan '16

Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13447 -gerrit commit 4b99b2216c61276b492b847dab819338686b3988 Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Mon Jan 25 14:32:25 2016 -0800 Quark: FSP MemoryInit Support Add a dummy fill_power_state routine so that execution is able to reach FSP MemoryInit. BRANCH=none BUG=None TEST=Build and run on Galileo Change-Id: I2a116e1e769ac09915638aa9e5d7c58a4aac3cce Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- src/soc/intel/quark/romstage/Makefile.inc | 2 ++ src/soc/intel/quark/romstage/romstage.c | 34 +++++++++++++++++++++++++++++++ 2 files changed, 36 insertions(+) diff --git a/src/soc/intel/quark/romstage/Makefile.inc b/src/soc/intel/quark/romstage/Makefile.inc index f664b38..85ebb75 100644 --- a/src/soc/intel/quark/romstage/Makefile.inc +++ b/src/soc/intel/quark/romstage/Makefile.inc @@ -16,3 +16,5 @@ # cpu_incs-y += $(src)/soc/intel/quark/romstage/esram_init.inc cpu_incs-y += $(src)/soc/intel/quark/romstage/cache_as_ram.inc + +romstage-y += romstage.c diff --git a/src/soc/intel/quark/romstage/romstage.c b/src/soc/intel/quark/romstage/romstage.c new file mode 100644 index 0000000..dc7b980 --- /dev/null +++ b/src/soc/intel/quark/romstage/romstage.c @@ -0,0 +1,34 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015-2016 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#include <arch/early_variables.h> +#include <console/console.h> +#include <soc/pm.h> + +static struct chipset_power_state power_state CAR_GLOBAL; + +struct chipset_power_state *fill_power_state(void) +{ + struct chipset_power_state *ps = car_get_var_ptr(&power_state); + + ps->prev_sleep_state = 0; + printk(BIOS_DEBUG, "prev_sleep_state %d\n", ps->prev_sleep_state); + return ps; +}

1 0

Patch set updated for coreboot: Intel Quark SoC and Galileo Gen 2 support
by Leroy P Leahy 25 Jan '16

25 Jan '16

Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13439 -gerrit commit b0b28022f834f5584d3f48a1a6be12af256ae461 Author: Lee Leahy <lpleahyjr(a)gmail.com> Date: Fri Jan 1 18:08:48 2016 -0800 Intel Quark SoC and Galileo Gen 2 support Add the files to build soc/intel/quark and mainboard/intel/galileo for a minimal coreboot image. Please note that this configuration does not run. Include HTML documentation for the Quark SoC and Galileo Gen 2 board. BRANCH=none BUG=None TEST=Build for Galileo Change-Id: If741f84904394780e1f29bd6ddbd81514c3e21c9 Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- src/mainboard/intel/galileo/Kconfig | 21 +++ src/mainboard/intel/galileo/Kconfig.name | 2 + src/mainboard/intel/galileo/devicetree.cb | 8 + src/mainboard/intel/galileo/galileo.html | 100 +++++++++++++ src/mainboard/intel/galileo/romstage.c | 24 +++ src/soc/intel/quark/Kconfig | 15 ++ src/soc/intel/quark/Makefile.inc | 34 +++++ src/soc/intel/quark/include/soc/pei_data.h | 60 ++++++++ src/soc/intel/quark/include/soc/pm.h | 33 +++++ src/soc/intel/quark/memmap.c | 22 +++ src/soc/intel/quark/quark.html | 98 +++++++++++++ src/vendorcode/intel/fsp/fsp1_1/quark/FspUpdVpd.h | 171 ++++++++++++++++++++++ 12 files changed, 588 insertions(+) diff --git a/src/mainboard/intel/galileo/Kconfig b/src/mainboard/intel/galileo/Kconfig new file mode 100755 index 0000000..8cf0cf7 --- /dev/null +++ b/src/mainboard/intel/galileo/Kconfig @@ -0,0 +1,21 @@ +if BOARD_INTEL_GALILEO + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_8192 + select PLATFORM_USES_FSP1_1 + select SOC_INTEL_QUARK + +config MAINBOARD_DIR + string + default intel/galileo + +config MAINBOARD_PART_NUMBER + string + default "Galileo" + +config MAINBOARD_VENDOR + string + default "Intel" + +endif # BOARD_INTEL_QUARK diff --git a/src/mainboard/intel/galileo/Kconfig.name b/src/mainboard/intel/galileo/Kconfig.name new file mode 100644 index 0000000..fc18e35 --- /dev/null +++ b/src/mainboard/intel/galileo/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_INTEL_GALILEO + bool "Galileo" diff --git a/src/mainboard/intel/galileo/devicetree.cb b/src/mainboard/intel/galileo/devicetree.cb new file mode 100755 index 0000000..6ada7e7 --- /dev/null +++ b/src/mainboard/intel/galileo/devicetree.cb @@ -0,0 +1,8 @@ +chip soc/intel/quark + + device domain 0 on + # EDS Table 3 + device pci 00.0 on end # 8086 0958 - Host Bridge + device pci 1f.0 on end # 8086 095e - Legacy Bridge + end +end diff --git a/src/mainboard/intel/galileo/galileo.html b/src/mainboard/intel/galileo/galileo.html new file mode 100644 index 0000000..8a2a99b --- /dev/null +++ b/src/mainboard/intel/galileo/galileo.html @@ -0,0 +1,100 @@ +<!DOCTYPE html> +<html> + <head> + <title>Galileo Gen 2</title> + </head> + <body> + +<h1>Intel® Galileo Gen 2 Development Board</h1> +<table> + <tr> + <td><a target="_blank" href="http://www.mouser.com/images/microsites/Intel_Galileo2_lrg.jpg"><img alt="Galileo Gen 2" src="http://www.mouser.com/images/microsites/Intel_Galileo2_lrg.jpg" width=500></a></td> + <td> +<table> + <tr bgcolor="#ffc0c0"> + <td> +Warning: Use of the Intel® Galileo Gen 2 mainboard code requires modification of the +util/xcompile/xcompile file to change the machine architecture from i686 to i586 because +the Quark™ processor does not support the instructions introduced with the +Pentium™ 6 architecture. +<ol> + <li>Edit the file util/xcompile/xcompile</li> + <li>Search for +<a target="_blank" href="https://chromium.googlesource.com/chromiumos/third_party/coreboot/+/chromeo…">-march</a></li> + <li>Replace i686 with i586</li> + <li>Save the result</li> +</ol> +Without this change the Quark™ processor will halt when it executes one of the +instructions introduced with the Pentium™ 6 architecture. + </td> + </tr> +</table> +<p> + The Intel® Galileo Gen 2 mainboard code was developed along with the Intel® + <a target="_blank" href="../../../soc/intel/quark/quark.html">Quark™</a> SoC: +</p> +<ul> + <li><a target="_blank" href="../../../../Documentation/x86Development.html">Overall</a> development</li> + <li><a target="_blank" href="../../../../Documentation/x86SoC.html">SoC</a> support</li> + <li><a target="_blank" href="../../../../Documentation/x86FSP1_1.html">FSP 1.1</a> integration</li> + <li><a target="_blank" href="../../../../Documentation/x86Board.html">Board</a> support</li> +</ul> + </td> + </tr> +</table> + + + +<hr> +<h1>Galileo Gen 2 Board Documentation</h1> +<ul> + <li><a target="_blank" href="http://files.linuxgizmos.com/intel_galileo_gen2_blockdiagram.jpg">Block Diagram</a></li> + <li><a target="_blank" href="https://software.intel.com/en-us/iot/library/galileo-getting-started">Getting Started</a></li> + <li><a target="_blank" href="http://www.intel.com/content/www/us/en/embedded/products/galileo/galileo-ov…">Overview</a></li> + <li><a target="_blank" href="http://files.linuxgizmos.com/intel_galileo_gen2_ports.jpg">Port Diagram</a></li> + <li><a target="_blank" href="http://download.intel.com/support/galileo/sb/intelgalileogen2prodbrief_3307…">Product Brief</a></li> + <li><a target="_blank" href="http://www.intel.com/content/dam/www/public/us/en/documents/guides/galileo-…">Schematic</a></li> + <li><a target="_blank" href="http://download.intel.com/support/galileo/sb/galileo_boarduserguide_330237_…">User Guide</a></li> + <li>Components + <ul> + <li>A/D: Texas Instruments <a target="_blank" href="http://www.ti.com/lit/ds/symlink/adc108s102.pdf">ADC108S102</a></li> + <li>Analog Switch: Texas Instruments <a target="_blank" href="http://www.ti.com/lit/ds/symlink/ts5a23159.pdf">TS5A23159</a></li> + <li>Ethernet (10/100 MB/S): Texas Instruments <a target="_blank" href="http://www.ti.com/lit/ds/symlink/dp83848-ep.pdf">DP83848</a></li> + <li>Load Switch: Texas Instruments <a target="_blank" href="http://www.ti.com/lit/ds/symlink/tps22920.pdf">TPS22920x</a></li> + <li>Memory (256 MiB): Micron <a target="_blank" href="https://www.micron.com/~/media/Documents/Products/Data%20Sheet/DRAM/DDR3/1G…">MT41K128M8</a></li> + <li>SoC: Intel® Quark™ <a target="_blank" href="../../../soc/intel/quark/quark.html">X-1000</a></li> + <li>Serial EEPROM (1 KiB): ON Semiconductor® <a target="_blank" href="http://www.onsemi.com/pub_link/Collateral/CAT24C01-D.PDF">CAT24C08</a></li> + <li>SPI Flash (8 MiB): Winbond™ <a target="_blank" href="http://www.winbond-usa.com/resource-files/w25q64fv_revl1_100713.pdf">W25Q64FV</a></li> + <li>Step Down Converter: Texas Instruments <a target="_blank" href="http://www.ti.com/lit/ds/slvsag7c/slvsag7c.pdf">TPS62130</a></li> + <li>Step Down Converter: Texas Instruments <a target="_blank" href="http://www.ti.com/lit/ug/slvu570/slvu570.pdf">TPS652510</a></li> + <li>Termination Regulator: Texas Instruments <a target="_blank" href="http://www.ti.com/lit/ds/symlink/tps51200.pdf">TPS51200</a></li> + </ul> + </li> +</ul> + + + +<hr> +<h1>Debug Tools</h1> +<ul> + <li>Flash Programmer: + <ul> + <li>Dediprog <a target="_blank" href="http://www.dediprog.com/pd/spi-flash-solution/SF100">SF100</a> ISP IC Programmer</li> + </ul> + </li> + <li>JTAG Connector: <a target="_blank" href="https://www.google.com/webhp?sourceid=chrome-instant&ion=1&espv=2&ie=UTF-8#…">Olimex ARM-JTAG-20-10</a></li> + <li>JTAG Debugger: + <ul> + <li>Olimex LTD <a target="_blank" href="https://www.google.com/webhp?sourceid=chrome-instant&ion=1&espv=2&ie=UTF-8#…">ARM-USB-OCD-H</a></li> + <li>Tincan Tools <a target="_blank" href="https://www.tincantools.com/wiki/Flyswatter2">Flyswatter2</a></li> + </ul> + </li> + <li><a target="_blank" href="http://download.intel.com/support/processors/quark/sb/sourcedebugusingopeno…">Hardware Setup and Software Installation</a></li> + <li>USB Serial cable: FTDI <a target="_blank" href="https://www.google.com/webhp?sourceid=chrome-instant&ion=1&espv=2&ie=UTF-8#…">TTL-232R-3V3</a></li> +</ul> + + +<hr> +<p>Modified: 25 January 2016</p> + </body> +</html> diff --git a/src/mainboard/intel/galileo/romstage.c b/src/mainboard/intel/galileo/romstage.c new file mode 100755 index 0000000..dfae772 --- /dev/null +++ b/src/mainboard/intel/galileo/romstage.c @@ -0,0 +1,24 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015-2016 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <fsp/romstage.h> + +/* All FSP specific code goes in this block */ +void mainboard_romstage_entry(struct romstage_params *rp) +{ + /* Call back into chipset code with platform values updated. */ + romstage_common(rp); +} diff --git a/src/soc/intel/quark/Kconfig b/src/soc/intel/quark/Kconfig new file mode 100644 index 0000000..8bb1e88 --- /dev/null +++ b/src/soc/intel/quark/Kconfig @@ -0,0 +1,15 @@ +config SOC_INTEL_QUARK + bool + help + Intel Quark support + +if SOC_INTEL_QUARK + +config CPU_SPECIFIC_OPTIONS + def_bool y + select ARCH_BOOTBLOCK_X86_32 + select ARCH_RAMSTAGE_X86_32 + select ARCH_ROMSTAGE_X86_32 + select ARCH_VERSTAGE_X86_32 + +endif # SOC_INTEL_QUARK diff --git a/src/soc/intel/quark/Makefile.inc b/src/soc/intel/quark/Makefile.inc new file mode 100644 index 0000000..d464735 --- /dev/null +++ b/src/soc/intel/quark/Makefile.inc @@ -0,0 +1,34 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2010 Google Inc. +# Copyright (C) 2013-2014 Sage Electronic Engineering, LLC. +# Copyright (C) 2015-2016 Intel Corporation. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# + +ifeq ($(CONFIG_SOC_INTEL_QUARK),y) + +subdirs-y += ../../../cpu/x86/tsc + +romstage-y += memmap.c + +ramstage-y += memmap.c + +CPPFLAGS_common += -I$(src)/soc/intel/quark/include +CPPFLAGS_common += -I$(src)/vendorcode/intel/fsp/fsp1_1/quark + +# Currently used for microcode path. +CPPFLAGS_common += -I3rdparty/blobs/mainboard/$(CONFIG_MAINBOARD_DIR) + +ROMCCFLAGS := -mcpu=p4 -fno-simplify-phi -O2 + +endif diff --git a/src/soc/intel/quark/include/soc/pei_data.h b/src/soc/intel/quark/include/soc/pei_data.h new file mode 100644 index 0000000..e3ec161 --- /dev/null +++ b/src/soc/intel/quark/include/soc/pei_data.h @@ -0,0 +1,60 @@ +/* + * UEFI PEI wrapper + * + * Copyright (C) 2014 Google Inc. + * Copyright (C) 2015-2016 Intel Corporation. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Google Inc. nor the + * names of its contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL GOOGLE INC BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef _PEI_DATA_H_ +#define _PEI_DATA_H_ + +#include <types.h> + +#define PEI_VERSION 22 + +#define ABI_X86 __attribute__((regparm(0))) + +typedef void ABI_X86(*tx_byte_func)(unsigned char byte); + +struct pei_data { + uint32_t pei_version; + + int boot_mode; + + /* Data read from flash and passed into MRC */ + const void *saved_data; + int saved_data_size; + + /* Disable use of saved data (can be set by mainboard) */ + int disable_saved_data; + + /* Data from MRC that should be saved to flash */ + void *data_to_save; + int data_to_save_size; +} __attribute__((packed)); + +typedef struct pei_data PEI_DATA; + +#endif /* _PEI_DATA_H_ */ diff --git a/src/soc/intel/quark/include/soc/pm.h b/src/soc/intel/quark/include/soc/pm.h new file mode 100644 index 0000000..f9ae027 --- /dev/null +++ b/src/soc/intel/quark/include/soc/pm.h @@ -0,0 +1,33 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * Copyright (C) 2015-2016 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_PM_H_ +#define _SOC_PM_H_ + +#include <stdint.h> + +/* Generic sleep state types */ +#define SLEEP_STATE_S0 0 +#define SLEEP_STATE_S3 3 +#define SLEEP_STATE_S5 5 + +struct chipset_power_state { + uint32_t prev_sleep_state; +} __attribute__ ((packed)); + +struct chipset_power_state *fill_power_state(void); + +#endif diff --git a/src/soc/intel/quark/memmap.c b/src/soc/intel/quark/memmap.c new file mode 100644 index 0000000..975128c --- /dev/null +++ b/src/soc/intel/quark/memmap.c @@ -0,0 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * Copyright (C) 2015-2016 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <cbmem.h> + +void *cbmem_top(void) +{ + return (void *)0x1c000000; +} diff --git a/src/soc/intel/quark/quark.html b/src/soc/intel/quark/quark.html new file mode 100644 index 0000000..40e091b --- /dev/null +++ b/src/soc/intel/quark/quark.html @@ -0,0 +1,98 @@ +<!DOCTYPE html> +<html> + <head> + <title>Quark™ SoC</title> + </head> + <body> + +<h1>Intel® Quark™ SoC</h1> +<table> + <tr> + <td><a target="_blank" href="http://www.intel.com/content/dam/www/public/us/en/images/embedded/16x9/edc-…"><img alt="Quark Block Diagram" src="http://www.intel.com/content/dam/www/public/us/en/images/embedded/16x9/edc-…" width=500></a></td> + <td> +<table> + <tr bgcolor="#ffc0c0"> + <td> +Warning: Use of the Intel® Quark™ SoC code requires modification of the util/xcompile/xcompile file to change the machine +architecture from i686 to i586 because the Quark™ processor does not support the instructions +introduced with the Pentium™ 6 architecture. +<ol> + <li>Edit the file util/xcompile/xcompile</li> + <li>Search for +<a target="_blank" href="https://chromium.googlesource.com/chromiumos/third_party/coreboot/+/chromeo…">-march</a></li> + <li>Replace i686 with i586</li> + <li>Save the result</li> +</ol> +Without this change the Quark™ processor will halt when it executes one of the +instructions introduced with the Pentium™ 6 architecture. + </td> + </tr> +</table> +<p> + The Quark™ SoC code was developed using the + <a target="_blank" href="../../../mainboard/intel/galileo/galileo.html">Galileo Gen 2</a> + board: +</p> +<ul> + <li><a target="_blank" href="../../../../Documentation/x86Development.html">Overall</a> development</li> + <li><a target="_blank" href="../../../../Documentation/x86SoC.html">SoC</a> support</li> + <li><a target="_blank" href="../../../../Documentation/x86FSP1_1.html">FSP 1.1</a> integration</li> + <li><a target="_blank" href="../../../../Documentation/x86Board.html">Board</a> support</li> +</ul> + </td> + </tr> +</table> + + + +<hr> +<h1>Quark™ Documentation</h1> +<ul> + <li><a target="_blank" href="http://www.intel.com/content/dam/www/public/us/en/images/embedded/16x9/edc-…">Block Diagram</a></li> + <li>Intel® 64 and IA-32 Architectures <a target="_blank" href="http://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-3…">Software Developer Manual</a></li> + <li><a target="_blank" href="http://www.intel.com/content/www/us/en/embedded/products/quark/specificatio…">Specifications</a>: + <ul> + <li><a target="_blank" href="http://ark.intel.com/products/79084/Intel-Quark-SoC-X1000-16K-Cache-400-MHz">X1000</a> + - <a target="_blank" href="http://www.intel.com/content/www/us/en/search.html?keyword=X1000">Documentation</a>: + <ul> + <li><a target="_blank" href="http://www.intel.com/content/dam/www/public/us/en/documents/datasheets/quar…">Datasheet</a></li> + <li><a target="_blank" href="http://www.intel.com/content/dam/support/us/en/documents/processors/quark/s…">Developer's Manual</a></li> + <li><a target="_blank" href="http://www.intel.com/content/dam/www/public/us/en/documents/product-briefs/…">Product Brief</a></li> + </ul> + </li> + </ul> + </li> +</ul> + + + +<hr> +<h1>Quark™ FSP</h1> +<ul> + <li>Intel® Firmware Support Package External Architecture Specification <a target="_blank" href="http://www.intel.com/content/dam/www/public/us/en/documents/technical-speci…">V1.1</a></li> + <li>Intel® Quark™ SoC X1000 <a target="_blank" href="http://www.intel.com/content/dam/www/public/us/en/documents/guides/quark-x1…">UEFI Firmware Writer's Guide</a></li> + <li>EDK2 Sources: + <ul> + <li>EDK2: git clone <a target="_blank" href="https://github.com/tianocore/edk2.git">https://github.com/tianocore/edk2.git</a></li> + <li>EDK2-FatPkg: git clone <a target="_blank" href="https://github.com/tianocore/edk2-FatPkg.git">https://github.com/tianocore/edk2-FatPkg.git</a> FatPkg</li> + <li>EDK2-non-osi: git clone <a target="_blank" href="https://github.com/tianocore/edk2-non-osi.git">https://github.com/tianocore/edk2-non-osi.git</a></li> + <li>Win32 BaseTools: git clone <a target="_blank" href="https://github.com/tianocore/edk2-BaseTools-win32.git">https://github.com/tianocore/edk2-BaseTools-win32.git</a></li> + </ul> + </li> + <li>Win32 Build Instructions: +<pre><code>set WORKSPACE=%CD% +set PACKAGES_PATH=%WORKSPACE%\edk2;%WORKSPACE%\FatPkg;%WORKSPACE%\edk2-non-osi +set EDK_TOOLS_BIN=%WORKSPACE%\edk2-BaseTools-win32 +cd edk2 +edksetup.bat +build -p QuarkPlatformPkg/Quark.dsc -a IA32 -t VS2012x86 -b DEBUG -DDEBUG_PROPERTY_MASK=0x27 -DDEBUG_PRINT_ERROR_LEVEL=0x80000042 +</code></pre> + </li> +</ul> + + + +<hr> +<p>Modified: 25 January 2016</p> + </body> +</html> \ No newline at end of file diff --git a/src/vendorcode/intel/fsp/fsp1_1/quark/FspUpdVpd.h b/src/vendorcode/intel/fsp/fsp1_1/quark/FspUpdVpd.h new file mode 100644 index 0000000..2a11b20 --- /dev/null +++ b/src/vendorcode/intel/fsp/fsp1_1/quark/FspUpdVpd.h @@ -0,0 +1,171 @@ +/** @file + +Copyright (c) 2015-2016, Intel Corporation. All rights reserved.<BR> + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +* Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. +* Redistributions in binary form must reproduce the above copyright notice, this + list of conditions and the following disclaimer in the documentation and/or + other materials provided with the distribution. +* Neither the name of Intel Corporation nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + THE POSSIBILITY OF SUCH DAMAGE. + + This file is automatically generated. Please do NOT modify !!! + +**/ + +#ifndef __FSPUPDVPD_H__ +#define __FSPUPDVPD_H__ + +#pragma pack(push, 1) + +#define MAX_CHANNELS_NUM 2 +#define MAX_DIMMS_NUM 2 + +typedef struct { + UINT8 DimmId; + UINT32 SizeInMb; + UINT16 MfgId; + UINT8 ModulePartNum[20];/* Module part number for DDR3 is 18 bytes however for DRR4 20 bytes as per JEDEC Spec, so reserving 20 bytes */ +} DIMM_INFO; + +typedef struct { + UINT8 ChannelId; + UINT8 DimmCount; + DIMM_INFO DimmInfo[MAX_DIMMS_NUM]; +} CHANNEL_INFO; + +typedef struct { + UINT8 Revision; + UINT16 DataWidth; + /** As defined in SMBIOS 3.0 spec + Section 7.18.2 and Table 75 + **/ + UINT8 MemoryType; + UINT16 MemoryFrequencyInMHz; + /** As defined in SMBIOS 3.0 spec + Section 7.17.3 and Table 72 + **/ + UINT8 ErrorCorrectionType; + UINT8 ChannelCount; + CHANNEL_INFO ChannelInfo[MAX_CHANNELS_NUM]; +} FSP_SMBIOS_MEMORY_INFO; + +/** UPD data structure for FspMemoryInitApi +**/ +typedef struct { + +/** Offset 0x0020 +**/ + UINT64 Signature; + +/** Offset 0x0028 - Revision + Revision version of the MemoryInitUpd Region +**/ + UINT8 Revision; +} MEMORY_INIT_UPD; + +/** UPD data structure for FspSiliconInitApi +**/ +typedef struct { + +/** Offset 0x0200 +**/ + UINT64 Signature; + +/** Offset 0x0208 - Revision + Revision version of the SiliconInitUpd Region +**/ + UINT8 Revision; +} SILICON_INIT_UPD; + +#define FSP_UPD_SIGNATURE 0x244450554B525124 /* '$QRKUPD$' */ +#define FSP_MEMORY_INIT_UPD_SIGNATURE 0x244450554D454D24 /* '$MEMUPD$' */ +#define FSP_SILICON_INIT_UPD_SIGNATURE 0x244450555F495324 /* '$SI_UPD$' */ + +/** UPD data structure. The UPD_DATA_REGION may contain some reserved or unused fields in the data structure. These fields are required to use the default values provided in the FSP binary. Intel always recommends copying the whole UPD_DATA_REGION from the flash to a local structure in the stack before overriding any field. +**/ +typedef struct { + +/** Offset 0x0000 +**/ + UINT64 Signature; + +/** Offset 0x0008 - This field is not an option and is a Revision of the UPD_DATA_REGION. It can be used by the boot loader to validate the UPD region. If the value in this field is changed for an FSP release, the boot loader should not assume the same layout for the UPD_DATA_REGION data structure. Instead it should use the new FspUpdVpd.h from the FSP release package. + Size of SMRAM memory reserved. 0x400000 for Release build and 0x1000000 for Debug build +**/ + UINT8 Revision; + +/** Offset 0x0009 +**/ + UINT8 ReservedUpd0[7]; + +/** Offset 0x0010 - MemoryInitUpdOffset + This field contains the offset of the MemoryInitUpd structure relative to UPD_DATA_REGION +**/ + UINT32 MemoryInitUpdOffset; + +/** Offset 0x0014 - SiliconInitUpdOffset + This field contains the offset of the SiliconInitUpd structure relative to UPD_DATA_REGION +**/ + UINT32 SiliconInitUpdOffset; + +/** Offset 0x0018 +**/ + UINT64 ReservedUpd1; + +/** Offset 0x0020 +**/ + MEMORY_INIT_UPD MemoryInitUpd; + +/** Offset 0x0200 +**/ + SILICON_INIT_UPD SiliconInitUpd; + +/** Offset 0x03FA - RegionTerminator + This field is not an option and is a termination field at the end of the data structure. This field is will have a value 0x55AA indicating the end of UPD data.The boot loader should never override this field. +**/ + UINT16 RegionTerminator; +} UPD_DATA_REGION; + +#define FSP_IMAGE_ID 0x305053462D4B5551 /* 'QUK-FSP0' */ +#define FSP_IMAGE_REV 0x00000000 /* 0.0 */ + +/** VPD data structure +**/ +typedef struct { + +/** Offset 0x0000 +**/ + UINT64 PcdVpdRegionSign; + +/** Offset 0x0008 - PcdImageRevision + This field is not an option and is a revision ID for the FSP release. It can be used by the boot loader to validate the VPD/UPD region. If the value in this field is changed for an FSP release, the boot loader should not assume the same layout for the UPD_DATA_REGION/VPD_DATA_REGION data structure. Instead it should use the new FspUpdVpd.h from the FSP release package. This should match the ImageRevision in FSP_INFO_HEADER. +**/ + UINT32 PcdImageRevision; + +/** Offset 0x000C - PcdUpdRegionOffset + This field is not an option and contains the offset of the UPD data region within the FSP release image. The boot loader can use it to find the location of UPD_DATA_REGION. +**/ + UINT32 PcdUpdRegionOffset; +} VPD_DATA_REGION; + +#pragma pack(pop) + +#endif

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coreboot-gerrit January 2016