coreboot-gerrit January 2016

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: intel/strago: Disable unused lines on Gpio North Bank
by Hannah Williams 25 Jan '16

25 Jan '16

Hannah Williams (hannah.williams(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13176 -gerrit commit ac0c5616e3192e307675744dcafcfc5ed3dcd477 Author: Jagadish Krishnamoorthy <jagadish.krishnamoorthy(a)intel.com> Date: Thu Nov 19 11:10:34 2015 -0800 intel/strago: Disable unused lines on Gpio North Bank The unused lines leads to spurious interrupts on few of the systems. TEST=run suspend_stress test and make sure that kbd is working. Change-Id: Ie539e1debc15dd1fd8707f8866c65714fc43e44b Signed-off-by: Jagadish Krishnamoorthy <jagadish.krishnamoorthy(a)intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/313417 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/mainboard/intel/strago/gpio.c | 23 ++++++++++------------- 1 file changed, 10 insertions(+), 13 deletions(-) diff --git a/src/mainboard/intel/strago/gpio.c b/src/mainboard/intel/strago/gpio.c index 3c8c8f5..fc8cab3 100644 --- a/src/mainboard/intel/strago/gpio.c +++ b/src/mainboard/intel/strago/gpio.c @@ -152,16 +152,15 @@ static const struct soc_gpio_map gpsw_gpio_map[] = { /* North Community */ static const struct soc_gpio_map gpn_gpio_map[] = { - Native_M5, /* 00 GPIO_DFX0 */ - Native_M5, /* 01 GPIO_DFX3 */ - Native_M1, /* 02 GPIO_DFX7 */ - Native_M5, /* 03 GPIO_DFX1 */ - Native_M1, /* 04 GPIO_DFX5 */ - Native_M1, /* 05 GPIO_DFX4 */ - GPI(trig_edge_low, L5, NA, non_maskable, en_rx_data, NA, NA), - /* 06 GPIO_DFX8 */ - Native_M5, /* 07 GPIO_DFX2 */ - Native_M8, /* 08 GPIO_DFX6 */ + GPIO_NC, /* 00 GPIO_DFX0 */ + GPIO_NC, /* 01 GPIO_DFX3 */ + GPIO_NC, /* 02 GPIO_DFX7 */ + GPIO_NC, /* 03 GPIO_DFX1 */ + GPIO_NC, /* 04 GPIO_DFX5 */ + GPIO_NC, /* 05 GPIO_DFX4 */ + GPIO_NC, /* 06 GPIO_DFX8 */ + GPIO_NC, /* 07 GPIO_DFX2 */ + GPIO_NC, /* 08 GPIO_DFX6 */ GPI(trig_edge_low, L8, NA, non_maskable, en_edge_rx_data , UNMASK_WAKE, SCI), /* 15 GPIO_SUS0 */ GPO_FUNC(NA, NA), /* 16 SEC_GPIO_SUS10 */ @@ -172,9 +171,7 @@ static const struct soc_gpio_map gpn_gpio_map[] = { GPI(trig_edge_low, L3, P_1K_H, non_maskable, NA, UNMASK_WAKE, NA), /* 19 GPIO_SUS1 */ GPIO_NC, /* 20 GPIO_SUS5 */ - GPI(trig_edge_high, L2, P_20K_H, non_maskable, - en_edge_rx_data, NA , NA), - /* 21 SEC_GPIO_SUS11 */ + GPIO_NC, /* 21 SEC_GPIO_SUS11 */ GPIO_NC, /* 22 GPIO_SUS4 */ GPIO_NC, /* 23 SEC_GPIO_SUS8 */

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Patch set updated for coreboot: soc/braswell: Fix DSP clock
by Hannah Williams 25 Jan '16

25 Jan '16

Hannah Williams (hannah.williams(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12732 -gerrit commit 31efaac50ab79c87eaee5d2e37ab90dc65f31765 Author: fdurairx <felixx.durairaj(a)intel.com> Date: Fri Aug 21 15:36:53 2015 -0700 soc/braswell: Fix DSP clock The codec clock frequency was incorrectly set to 25MHz. The only available frequency is 19.2MHz through external clock and PLL. Original-Reviewed-on: https://chromium-review.googlesource.com/295768 Original-Tested-by: Hannah Williams <hannah.williams(a)intel.com> Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Change-Id: I9bef334a5a3aaee28fcc4937180896ff49969bc5 Signed-off-by: Felix Durairaj <felixx.durairaj(a)intel.com> --- src/mainboard/google/cyan/devicetree.cb | 3 +-- src/mainboard/intel/strago/devicetree.cb | 3 +-- src/soc/intel/braswell/chip.h | 8 ++++++-- src/soc/intel/braswell/include/soc/pm.h | 4 ++-- src/soc/intel/braswell/lpe.c | 24 +++++++++++------------- 5 files changed, 21 insertions(+), 21 deletions(-) diff --git a/src/mainboard/google/cyan/devicetree.cb b/src/mainboard/google/cyan/devicetree.cb index c36ae3d..8932cf4 100755 --- a/src/mainboard/google/cyan/devicetree.cb +++ b/src/mainboard/google/cyan/devicetree.cb @@ -72,8 +72,7 @@ chip soc/intel/braswell register "ISPPciDevConfig" = "3" # LPE audio codec settings - register "lpe_codec_clk_freq" = "25" # 25MHz clock - register "lpe_codec_clk_num" = "0" # PMC_PLT_CLK[0] + register "lpe_codec_clk_src" = "LPE_CLK_SRC_XTAL" # 19.2MHz clock # Enable devices in ACPI mode register "lpss_acpi_mode" = "1" diff --git a/src/mainboard/intel/strago/devicetree.cb b/src/mainboard/intel/strago/devicetree.cb index 788153a..3b93f44 100755 --- a/src/mainboard/intel/strago/devicetree.cb +++ b/src/mainboard/intel/strago/devicetree.cb @@ -72,8 +72,7 @@ chip soc/intel/braswell register "ISPPciDevConfig" = "3" # LPE audio codec settings - register "lpe_codec_clk_freq" = "25" # 25MHz clock - register "lpe_codec_clk_num" = "0" # PMC_PLT_CLK[0] + register "lpe_codec_clk_src" = "LPE_CLK_SRC_XTAL" # 19.2MHz clock # Enable devices in ACPI mode register "lpss_acpi_mode" = "1" diff --git a/src/soc/intel/braswell/chip.h b/src/soc/intel/braswell/chip.h index 0f3c1d0..6eb1451 100644 --- a/src/soc/intel/braswell/chip.h +++ b/src/soc/intel/braswell/chip.h @@ -33,6 +33,11 @@ #define MEM_DDR3 0 #define MEM_LPDDR3 1 +enum lpe_clk_src { + LPE_CLK_SRC_XTAL, + LPE_CLK_SRC_PLL, +}; + struct soc_intel_braswell_config { uint8_t enable_xdp_tap; uint8_t clkreq_enable; @@ -41,8 +46,7 @@ struct soc_intel_braswell_config { int disable_slp_x_stretch_sus_fail; /* LPE Audio Clock configuration. */ - int lpe_codec_clk_freq; /* 19 or 25 are valid. */ - int lpe_codec_clk_num; /* Platform clock pins. [0:5] are valid. */ + enum lpe_clk_src lpe_codec_clk_src; /* 0=xtal 1=PLL, Both are 19.2Mhz. */ /* Native SD Card controller - override controller capabilities. */ uint32_t sdcard_cap_low; diff --git a/src/soc/intel/braswell/include/soc/pm.h b/src/soc/intel/braswell/include/soc/pm.h index 9708b39..a4b2e2d 100644 --- a/src/soc/intel/braswell/include/soc/pm.h +++ b/src/soc/intel/braswell/include/soc/pm.h @@ -116,8 +116,8 @@ #define PLT_CLK_CTL_3 0x6c #define PLT_CLK_CTL_4 0x70 #define PLT_CLK_CTL_5 0x74 -# define CLK_FREQ_25MHZ (0x0 << 2) -# define CLK_FREQ_19P2MHZ (0x1 << 2) +# define CLK_SRC_XTAL (0x0 << 2) +# define CLK_SRC_PLL (0x1 << 2) # define CLK_CTL_D3_LPE (0x0 << 0) # define CLK_CTL_ON (0x1 << 0) # define CLK_CTL_OFF (0x2 << 0) diff --git a/src/soc/intel/braswell/lpe.c b/src/soc/intel/braswell/lpe.c index a1a7c64..4662b43 100644 --- a/src/soc/intel/braswell/lpe.c +++ b/src/soc/intel/braswell/lpe.c @@ -96,32 +96,30 @@ static void setup_codec_clock(device_t dev) const char *freq_str; config = dev->chip_info; - switch (config->lpe_codec_clk_freq) { - case 19: - freq_str = "19.2"; - reg = CLK_FREQ_19P2MHZ; + switch (config->lpe_codec_clk_src) { + case LPE_CLK_SRC_XTAL: + /* XTAL driven bit2=0 */ + freq_str = "19.2MHz External Crystal"; + reg = CLK_SRC_XTAL; break; - case 25: - freq_str = "25"; - reg = CLK_FREQ_25MHZ; + case LPE_CLK_SRC_PLL: + /* PLL driven bit2=1 */ + freq_str = "19.2MHz PLL"; + reg = CLK_SRC_PLL; break; default: - printk(BIOS_DEBUG, "LPE codec clock not required.\n"); + reg = CLK_SRC_XTAL; + printk(BIOS_DEBUG, "LPE codec clock default to using Crystal\n"); return; } /* Default to always running. */ reg |= CLK_CTL_ON; - if (config->lpe_codec_clk_num < 0 || config->lpe_codec_clk_num > 5) { - printk(BIOS_DEBUG, "Invalid LPE codec clock number.\n"); - return; - } printk(BIOS_DEBUG, "LPE Audio codec clock set to %sMHz.\n", freq_str); clk_reg = (u32 *) (PMC_BASE_ADDRESS + PLT_CLK_CTL_0); - clk_reg += config->lpe_codec_clk_num; write32(clk_reg, (read32(clk_reg) & ~0x7) | reg); }

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Patch set updated for coreboot: soc/braswell: Update FspUpdVpd.h for PcdSdDetectChk and PcdCaMirrorEn
by Hannah Williams 25 Jan '16

25 Jan '16

Hannah Williams (hannah.williams(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13038 -gerrit commit b793048f349c0389ae4a846ace0c2322aeb55859 Author: Hannah Williams <hannah.williams(a)intel.com> Date: Mon Jan 18 00:22:52 2016 -0800 soc/braswell: Update FspUpdVpd.h for PcdSdDetectChk and PcdCaMirrorEn Change-Id: I42200feafed613136f23e37d4ab4c90931698821 Signed-off-by: Hannah Williams <hannah.williams(a)intel.com> --- .../intel/fsp/fsp1_1/braswell/FspUpdVpd.h | 31 ++++++++++++---------- 1 file changed, 17 insertions(+), 14 deletions(-) diff --git a/src/vendorcode/intel/fsp/fsp1_1/braswell/FspUpdVpd.h b/src/vendorcode/intel/fsp/fsp1_1/braswell/FspUpdVpd.h index 9b9df0e..61673c6 100644 --- a/src/vendorcode/intel/fsp/fsp1_1/braswell/FspUpdVpd.h +++ b/src/vendorcode/intel/fsp/fsp1_1/braswell/FspUpdVpd.h @@ -188,8 +188,13 @@ typedef struct { **/ UINT8 PcdMemoryTypeEnable; /** Offset 0x0042 + CaMirrorEn + To Enable/Disable CaMirrorEn **/ - UINT8 ReservedMemoryInitUpd[190]; + UINT8 PcdCaMirrorEn; +/** Offset 0x0043 +**/ + UINT8 ReservedMemoryInitUpd[189]; } MEMORY_INIT_UPD; typedef struct { @@ -436,8 +441,18 @@ typedef struct { **/ UINT8 PcdTurboMode; /** Offset 0x0161 + Pnp-Power & Performance + select Pnp type +**/ + UINT8 PcdPnpSettings; +/** Offset 0x0162 + SdDetectChk + Check for Sd card detect **/ - UINT8 ReservedSiliconInitUpd[413]; + UINT8 PcdSdDetectChk; +/** Offset 0x0163 +**/ + UINT8 ReservedSiliconInitUpd[411]; } SILICON_INIT_UPD; #define FSP_UPD_SIGNATURE 0x2444505557534224 /* '$BSWUPD$' */ @@ -472,12 +487,6 @@ typedef struct _UPD_DATA_REGION { /** Offset 0x02FE **/ UINT16 PcdRegionTerminator; -/** Offset 0x0300 -**/ - UINT8 UnusedUpdSpace4[2123]; -/** Offset 0x0B4B -**/ - UINT8 PcdPaddingSpace; } UPD_DATA_REGION; #define FSP_IMAGE_ID 0x2450534657534224 /* '$BSWFSP$' */ @@ -494,12 +503,6 @@ typedef struct _VPD_DATA_REGION { /** Offset 0x000C **/ UINT32 PcdUpdRegionOffset; -/** Offset 0x0010 -**/ - UINT8 UnusedVpdSpace0[20]; -/** Offset 0x0024 -**/ - UINT8 PcdEnableSecureBoot; } VPD_DATA_REGION; #pragma pack(pop)

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Patch set updated for coreboot: intel/strago: Set LPC_CLKRUNB to PU_20K to solve leakage issue.
by Hannah Williams 25 Jan '16

25 Jan '16

Hannah Williams (hannah.williams(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13175 -gerrit commit 56270d2829708050be4952793492c81d7c09b834 Author: Kane Chen <kane.chen(a)intel.com> Date: Wed Dec 9 10:06:14 2015 +0800 intel/strago: Set LPC_CLKRUNB to PU_20K to solve leakage issue. LPC_CLKRUNB pin needs to be set to PU_20K to prevent leakage TEST=Test on Strago and make sure the leakage is gone Signed-off-by: Kane Chen <kane.chen(a)intel.com> Change-Id: Id2bf7511806cdc52b505bb469238a9465b356352 Original-Reviewed-on: https://chromium-review.googlesource.com/317020 Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Tested-by: Kane Chen <kane.chen(a)intel.com> Original-Commit-Queue: Kane Chen <kane.chen(a)intel.com> Signed-off-by: Hannah Williams <hannah.williams(a)intel.com> --- src/mainboard/intel/strago/gpio.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/intel/strago/gpio.c b/src/mainboard/intel/strago/gpio.c index b64d867..3c8c8f5 100644 --- a/src/mainboard/intel/strago/gpio.c +++ b/src/mainboard/intel/strago/gpio.c @@ -48,7 +48,7 @@ static const struct soc_gpio_map gpse_gpio_map[] = { NATIVE_PU20K(1), /* 34 SDMMC3_CMD */ NATIVE_PU20K(1), /* 35 SDMMC3_D0 */ NATIVE_PU20K(1), /* 45 MF_LPC_AD2 */ - Native_M1, /* 46 LPC_CLKRUNB */ + NATIVE_PU20K(1), /* 46 LPC_CLKRUNB */ NATIVE_PU20K(1), /* 47 MF_LPC_AD0 */ Native_M1, /* 48 LPC_FRAMEB */ Native_M1, /* 49 MF_LPC_CLKOUT1 */

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Patch set updated for coreboot: Braswell: Implement Gpio library functions to read RAMID
by Hannah Williams 25 Jan '16

25 Jan '16

Hannah Williams (hannah.williams(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12735 -gerrit commit 6519de1d9b1070203675b934ea5d34f669763e8b Author: Subrata Banik <subrata.banik(a)intel.com> Date: Sat Aug 22 10:36:41 2015 +0530 Braswell: Implement Gpio library functions to read RAMID Added GPIO library code to allow all BSW board specific code to use memory configuration GPIOs in GPIO Input mode and read them to determine which memory type is on the board. Also added other GPIO related APIs to support GPIO access in BSW. Original-Reviewed-on: https://chromium-review.googlesource.com/294893 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Change-Id: Idd65136c0449f0cdebfae12a510985e29889fa2b Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> Signed-off-by: Hannah Williams <hannah.williams(a)intel.com> --- src/soc/intel/braswell/Makefile.inc | 1 + src/soc/intel/braswell/gpio_support.c | 91 +++++++++- src/soc/intel/braswell/include/soc/gpio.h | 13 ++ src/soc/intel/braswell/include/soc/gpio_defs.h | 219 +++++++++++++++++++++++++ 4 files changed, 321 insertions(+), 3 deletions(-) diff --git a/src/soc/intel/braswell/Makefile.inc b/src/soc/intel/braswell/Makefile.inc index b61323d..4a107ec 100644 --- a/src/soc/intel/braswell/Makefile.inc +++ b/src/soc/intel/braswell/Makefile.inc @@ -23,6 +23,7 @@ ramstage-y += gpio.c ifeq ($(CONFIG_GOP_SUPPORT),n) ramstage-y += gfx.c endif +ramstage-y += gpio_support.c ramstage-y += hda.c ramstage-y += iosf.c ramstage-y += lpe.c diff --git a/src/soc/intel/braswell/gpio_support.c b/src/soc/intel/braswell/gpio_support.c index 34e0196..14c4663 100644 --- a/src/soc/intel/braswell/gpio_support.c +++ b/src/soc/intel/braswell/gpio_support.c @@ -12,7 +12,7 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ - +#include <gpio.h> #include <console/console.h> #include <soc/gpio.h> @@ -71,12 +71,97 @@ uint32_t *gpio_pad_config_reg(uint8_t community, uint8_t pad) * Refer to BSW BIOS Writers Guide, Table "Per Pad Memory Space * Registers Addresses" for the Pad configuration register calculation. */ - pad_config_reg = (uint32_t *)(COMMUNITY_BASE(community) + 0x4400 + - (0x400 * (fpad >> 8)) + (8 * (fpad & 0xff))); + pad_config_reg = (uint32_t *)(COMMUNITY_BASE(community) + + FAMILY_PAD_REGS_OFF + (FAMILY_PAD_REGS_SIZE * (fpad >> 8)) + + (GPIO_REGS_SIZE * (fpad & 0xff))); return pad_config_reg; } +static int gpio_get_community_num(gpio_t gpio_num, int *pad) +{ + int comm = 0; + + if (gpio_num >= GP_SW_00 && gpio_num <= GP_SW_97) { + comm = GP_SOUTHWEST; + *pad = gpio_num % GP_SOUTHWEST_COUNT; + } else if (gpio_num >= GP_NC_00 && gpio_num <= GP_NC_72) { + comm = GP_NORTH; + *pad = gpio_num % GP_SOUTHWEST_COUNT; + } else if (gpio_num >= GP_E_00 && gpio_num <= GP_E_26) { + comm = GP_EAST; + *pad = gpio_num % + (GP_SOUTHWEST_COUNT + GP_NORTH_COUNT); + } else { + comm = GP_SOUTHEAST; + *pad = gpio_num % (GP_SOUTHWEST_COUNT + + GP_NORTH_COUNT + GP_EAST_COUNT); + } + return comm; +} + +static void gpio_config_pad(gpio_t gpio_num, const struct soc_gpio_map *cfg) +{ + int comm = 0; + int pad_num =0; + uint32_t *pad_config0_reg; + uint32_t *pad_config1_reg; + int max_gpio_cnt = GP_SOUTHWEST_COUNT + GP_NORTH_COUNT + GP_EAST_COUNT + + GP_SOUTHEAST_COUNT; + + if(gpio_num > max_gpio_cnt) + return; + /* Get GPIO Community based on GPIO_NUMBER */ + comm = gpio_get_community_num(gpio_num, &pad_num); + /* CONF0 */ + pad_config0_reg = gpio_pad_config_reg(comm, pad_num); + /* CONF1 */ + pad_config1_reg = pad_config0_reg + 1; + + write32(pad_config0_reg, cfg->pad_conf0); + write32(pad_config1_reg, cfg->pad_conf1); +} + +void gpio_input_pullup(gpio_t gpio_num) +{ + struct soc_gpio_map cfg = GPIO_INPUT_PU_20K; + gpio_config_pad(gpio_num, &cfg); +} + +void gpio_input_pulldown(gpio_t gpio_num) +{ + struct soc_gpio_map cfg = GPIO_INPUT_PD_20K; + gpio_config_pad(gpio_num, &cfg); +} + +void gpio_input(gpio_t gpio_num) +{ + struct soc_gpio_map cfg = GPIO_INPUT_NO_PULL; + gpio_config_pad(gpio_num, &cfg); +} + +int gpio_get(gpio_t gpio_num) +{ + int comm = 0; + int pad_num =0; + uint32_t *pad_config0_reg; + u32 pad_value; + int max_gpio_cnt = GP_SOUTHWEST_COUNT + GP_NORTH_COUNT + GP_EAST_COUNT + + GP_SOUTHEAST_COUNT; + + if(gpio_num > max_gpio_cnt) + return -1; + + /* Get GPIO Community based on GPIO_NUMBER */ + comm = gpio_get_community_num(gpio_num, &pad_num); + /* CONF0 */ + pad_config0_reg = gpio_pad_config_reg(comm, pad_num); + + pad_value = read32(pad_config0_reg); + + return pad_value & PAD_RX_BIT; +} + int get_gpio(int community_base, int pad0_offset) { return (read32((void *)(community_base + pad0_offset))) & PAD_RX_BIT; diff --git a/src/soc/intel/braswell/include/soc/gpio.h b/src/soc/intel/braswell/include/soc/gpio.h index 08cfd0c..11110c9 100644 --- a/src/soc/intel/braswell/include/soc/gpio.h +++ b/src/soc/intel/braswell/include/soc/gpio.h @@ -19,6 +19,7 @@ #include <stdint.h> #include <arch/io.h> +#include <soc/gpio_defs.h> #include <soc/iomap.h> #define COMMUNITY_SIZE 0x20000 @@ -235,6 +236,16 @@ | PAD_CONFIG0_GPI_DEFAULT, \ .pad_conf1 = PAD_CONFIG1_DEFAULT0 } +#define GPIO_INPUT_PD_5K \ + { .pad_conf0 = PAD_PULL_DOWN_5K | PAD_GPIO_ENABLE \ + | PAD_CONFIG0_GPI_DEFAULT, \ + .pad_conf1 = PAD_CONFIG1_DEFAULT0 } + +#define GPIO_INPUT_PD_20K \ + { .pad_conf0 = PAD_PULL_DOWN_20K | PAD_GPIO_ENABLE \ + | PAD_CONFIG0_GPI_DEFAULT, \ + .pad_conf1 = PAD_CONFIG1_DEFAULT0 } + #define GPIO_INPUT_PU_5K \ { .pad_conf0 = PAD_PULL_UP_5K | PAD_GPIO_ENABLE \ | PAD_CONFIG0_GPI_DEFAULT, \ @@ -567,6 +578,8 @@ static inline void ssus_disable_internal_pull(int pad) { } +typedef int gpio_t; + int get_gpio(int community_base, int pad0_offset); uint16_t gpio_family_number(uint8_t community, uint8_t pad); uint32_t *gpio_pad_config_reg(uint8_t community, uint8_t pad); diff --git a/src/soc/intel/braswell/include/soc/gpio_defs.h b/src/soc/intel/braswell/include/soc/gpio_defs.h new file mode 100644 index 0000000..c6a3c3b --- /dev/null +++ b/src/soc/intel/braswell/include/soc/gpio_defs.h @@ -0,0 +1,219 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2016 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_GPIO_DEFS_H_ +#define _SOC_GPIO_DEFS_H_ + +/* GPSOUTHWEST */ +#define GP_SW_00 0 +#define GP_SW_01 1 +#define GP_SW_02 2 +#define GP_SW_03 3 +#define GP_SW_04 4 +#define GP_SW_05 5 +#define GP_SW_06 6 +#define GP_SW_07 7 +#define GP_SW_15 8 +#define GP_SW_16 9 +#define GP_SW_17 10 +#define GP_SW_18 11 +#define GP_SW_19 12 +#define GP_SW_20 13 +#define GP_SW_21 14 +#define GP_SW_22 15 +#define GP_SW_30 16 +#define GP_SW_31 17 +#define GP_SW_32 18 +#define GP_SW_33 19 +#define GP_SW_34 20 +#define GP_SW_35 21 +#define GP_SW_36 22 +#define GP_SW_37 23 +#define GP_SW_45 24 +#define GP_SW_46 25 +#define GP_SW_47 26 +#define GP_SW_48 27 +#define GP_SW_49 28 +#define GP_SW_50 29 +#define GP_SW_51 30 +#define GP_SW_52 31 +#define GP_SW_60 32 +#define GP_SW_61 33 +#define GP_SW_62 34 +#define GP_SW_63 35 +#define GP_SW_64 36 +#define GP_SW_65 37 +#define GP_SW_66 38 +#define GP_SW_67 39 +#define GP_SW_75 40 +#define GP_SW_76 41 +#define GP_SW_77 42 +#define GP_SW_78 43 +#define GP_SW_79 44 +#define GP_SW_80 45 +#define GP_SW_81 46 +#define GP_SW_82 47 +#define GP_SW_90 48 +#define GP_SW_91 49 +#define GP_SW_92 50 +#define GP_SW_93 51 +#define GP_SW_94 52 +#define GP_SW_95 53 +#define GP_SW_96 54 +#define GP_SW_97 55 +/* GPNORTH */ +#define GP_NC_00 56 +#define GP_NC_01 57 +#define GP_NC_02 58 +#define GP_NC_03 59 +#define GP_NC_04 60 +#define GP_NC_05 61 +#define GP_NC_06 62 +#define GP_NC_07 63 +#define GP_NC_08 64 +#define GP_NC_15 65 +#define GP_NC_16 66 +#define GP_NC_17 67 +#define GP_NC_18 68 +#define GP_NC_19 69 +#define GP_NC_20 70 +#define GP_NC_21 71 +#define GP_NC_22 72 +#define GP_NC_23 73 +#define GP_NC_24 74 +#define GP_NC_25 75 +#define GP_NC_26 76 +#define GP_NC_27 77 +#define GP_NC_30 78 +#define GP_NC_31 79 +#define GP_NC_32 80 +#define GP_NC_33 81 +#define GP_NC_34 82 +#define GP_NC_35 83 +#define GP_NC_36 84 +#define GP_NC_37 85 +#define GP_NC_38 86 +#define GP_NC_39 87 +#define GP_NC_40 88 +#define GP_NC_41 89 +#define GP_NC_45 90 +#define GP_NC_46 91 +#define GP_NC_47 92 +#define GP_NC_48 93 +#define GP_NC_49 94 +#define GP_NC_50 95 +#define GP_NC_51 96 +#define GP_NC_52 97 +#define GP_NC_53 98 +#define GP_NC_54 99 +#define GP_NC_55 100 +#define GP_NC_56 101 +#define GP_NC_60 102 +#define GP_NC_61 103 +#define GP_NC_62 104 +#define GP_NC_63 105 +#define GP_NC_64 106 +#define GP_NC_65 107 +#define GP_NC_66 108 +#define GP_NC_67 119 +#define GP_NC_68 110 +#define GP_NC_69 111 +#define GP_NC_70 112 +#define GP_NC_71 113 +#define GP_NC_72 114 +/* GPEAST */ +#define GP_E_00 115 +#define GP_E_01 116 +#define GP_E_02 117 +#define GP_E_03 118 +#define GP_E_04 119 +#define GP_E_05 120 +#define GP_E_06 121 +#define GP_E_07 122 +#define GP_E_08 123 +#define GP_E_09 124 +#define GP_E_10 125 +#define GP_E_11 126 +#define GP_E_15 127 +#define GP_E_16 128 +#define GP_E_17 129 +#define GP_E_18 130 +#define GP_E_19 131 +#define GP_E_20 132 +#define GP_E_21 133 +#define GP_E_22 134 +#define GP_E_23 135 +#define GP_E_24 136 +#define GP_E_25 137 +#define GP_E_26 138 +/* GPSOUTHEAST */ +#define GP_SE_00 139 +#define GP_SE_01 140 +#define GP_SE_02 141 +#define GP_SE_03 142 +#define GP_SE_04 143 +#define GP_SE_05 144 +#define GP_SE_06 145 +#define GP_SE_07 146 +#define GP_SE_15 147 +#define GP_SE_16 148 +#define GP_SE_17 149 +#define GP_SE_18 150 +#define GP_SE_19 151 +#define GP_SE_20 152 +#define GP_SE_21 153 +#define GP_SE_22 154 +#define GP_SE_23 155 +#define GP_SE_24 156 +#define GP_SE_25 157 +#define GP_SE_26 158 +#define GP_SE_30 159 +#define GP_SE_31 160 +#define GP_SE_32 161 +#define GP_SE_33 162 +#define GP_SE_34 163 +#define GP_SE_35 164 +#define GP_SE_45 165 +#define GP_SE_46 166 +#define GP_SE_47 167 +#define GP_SE_48 168 +#define GP_SE_49 169 +#define GP_SE_50 170 +#define GP_SE_51 171 +#define GP_SE_52 172 +#define GP_SE_60 173 +#define GP_SE_61 174 +#define GP_SE_62 175 +#define GP_SE_63 176 +#define GP_SE_64 177 +#define GP_SE_65 178 +#define GP_SE_66 179 +#define GP_SE_67 180 +#define GP_SE_68 181 +#define GP_SE_69 182 +#define GP_SE_75 183 +#define GP_SE_76 184 +#define GP_SE_77 185 +#define GP_SE_78 186 +#define GP_SE_79 187 +#define GP_SE_80 188 +#define GP_SE_81 189 +#define GP_SE_82 190 +#define GP_SE_83 191 +#define GP_SE_84 192 +#define GP_SE_85 193 + +#endif /* _SOC_GPIO_DEFS_H_ */

1 0

Patch set updated for coreboot: Strago: Disable SD Card Detect Simulation in FSP
by Hannah Williams 25 Jan '16

25 Jan '16

Hannah Williams (hannah.williams(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13035 -gerrit commit 0765c2389a649b880ec662ef311a3e6b4ab94111 Author: Hannah Williams <hannah.williams(a)intel.com> Date: Sun Jan 17 23:11:25 2016 -0800 Strago: Disable SD Card Detect Simulation in FSP CQ-DEPEND=CL:12742 Signed-off-by: Hannah Williams <hannah.williams(a)intel.com> Change-Id: I6c39ffebe407a4ef8555b2f050a96d33709dc624 --- src/mainboard/intel/strago/devicetree.cb | 1 + 1 file changed, 1 insertion(+) diff --git a/src/mainboard/intel/strago/devicetree.cb b/src/mainboard/intel/strago/devicetree.cb index ae8c11e..b2d5115 100755 --- a/src/mainboard/intel/strago/devicetree.cb +++ b/src/mainboard/intel/strago/devicetree.cb @@ -71,6 +71,7 @@ chip soc/intel/braswell register "PMIC_I2CBus" = "0" register "ISPEnable" = "0" # Disable IUNIT register "ISPPciDevConfig" = "3" + register "PcdSdDetectChk" = "0" # Disable SD card detect # LPE audio codec settings register "lpe_codec_clk_src" = "LPE_CLK_SRC_XTAL" # 19.2MHz clock

1 0

Patch set updated for coreboot: soc/braswell: Fix leakage on V1P8S rail
by Hannah Williams 25 Jan '16

25 Jan '16

Hannah Williams (hannah.williams(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12730 -gerrit commit e1d6e61bccf1b636971c950ab24c08043f829dca Author: Shobhit Srivastava <shobhit.srivastava(a)intel.com> Date: Mon Aug 10 11:48:23 2015 +0530 soc/braswell: Fix leakage on V1P8S rail Tristate MMC1_RCLK pin to fix leakage on V1P8S rail. Original-Reviewed-on: https://chromium-review.googlesource.com/292043 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Tested-by: Divagar Mohandass <divagar.mohandass(a)intel.com> Change-Id: I76cc9211ba93b2596d3c0d772d99f8934656e01c Signed-off-by: Shobhit Srivastava <shobhit.srivastava(a)intel.com> --- src/soc/intel/braswell/include/soc/gpio.h | 1 + src/soc/intel/braswell/smihandler.c | 2 ++ 2 files changed, 3 insertions(+) diff --git a/src/soc/intel/braswell/include/soc/gpio.h b/src/soc/intel/braswell/include/soc/gpio.h index 4ab6592..c7bfb65 100644 --- a/src/soc/intel/braswell/include/soc/gpio.h +++ b/src/soc/intel/braswell/include/soc/gpio.h @@ -105,6 +105,7 @@ #define MMC1_D5_MMIO_OFFSET GPIO_OFFSET(65) #define MMC1_D6_MMIO_OFFSET GPIO_OFFSET(63) #define MMC1_D7_MMIO_OFFSET GPIO_OFFSET(68) +#define MMC1_RCLK_OFFSET GPIO_OFFSET(69) #define HV_DDI2_DDC_SDA_MMIO_OFFSET GPIO_OFFSET(62) #define HV_DDI2_DDC_SCL_MMIO_OFFSET GPIO_OFFSET(67) #define CFIO_139_MMIO_OFFSET GPIO_OFFSET(64) diff --git a/src/soc/intel/braswell/smihandler.c b/src/soc/intel/braswell/smihandler.c index dabc0d2..760fba3 100644 --- a/src/soc/intel/braswell/smihandler.c +++ b/src/soc/intel/braswell/smihandler.c @@ -117,6 +117,8 @@ static void tristate_gpios(uint32_t val) MMC1_D6_MMIO_OFFSET, val); write32((void *)COMMUNITY_GPSOUTHEAST_BASE + MMC1_D7_MMIO_OFFSET, val); + write32((void *)COMMUNITY_GPSOUTHEAST_BASE + + MMC1_RCLK_OFFSET, val); /* Tri-state HDMI */ write32((void *)COMMUNITY_GPNORTH_BASE +

1 0

New patch to review for coreboot: Quark: FSP MemoryInit Support
by Leroy P Leahy 25 Jan '16

25 Jan '16

Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13447 -gerrit commit e227c1e1227a2f5d4e5cb3138440d901a22d2282 Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Mon Jan 25 14:32:25 2016 -0800 Quark: FSP MemoryInit Support Add a dummy fill_power_state routine so that execution is able to reach FSP MemoryInit. BRANCH=none BUG=None TEST=Build and run on Galileo Change-Id: I2a116e1e769ac09915638aa9e5d7c58a4aac3cce Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- src/soc/intel/quark/romstage/Makefile.inc | 2 ++ src/soc/intel/quark/romstage/romstage.c | 34 +++++++++++++++++++++++++++++++ 2 files changed, 36 insertions(+) diff --git a/src/soc/intel/quark/romstage/Makefile.inc b/src/soc/intel/quark/romstage/Makefile.inc index f664b38..85ebb75 100644 --- a/src/soc/intel/quark/romstage/Makefile.inc +++ b/src/soc/intel/quark/romstage/Makefile.inc @@ -16,3 +16,5 @@ # cpu_incs-y += $(src)/soc/intel/quark/romstage/esram_init.inc cpu_incs-y += $(src)/soc/intel/quark/romstage/cache_as_ram.inc + +romstage-y += romstage.c diff --git a/src/soc/intel/quark/romstage/romstage.c b/src/soc/intel/quark/romstage/romstage.c new file mode 100644 index 0000000..dc7b980 --- /dev/null +++ b/src/soc/intel/quark/romstage/romstage.c @@ -0,0 +1,34 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015-2016 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#include <arch/early_variables.h> +#include <console/console.h> +#include <soc/pm.h> + +static struct chipset_power_state power_state CAR_GLOBAL; + +struct chipset_power_state *fill_power_state(void) +{ + struct chipset_power_state *ps = car_get_var_ptr(&power_state); + + ps->prev_sleep_state = 0; + printk(BIOS_DEBUG, "prev_sleep_state %d\n", ps->prev_sleep_state); + return ps; +}

1 0

New patch to review for coreboot: x86 Docs: Add sleep state and minimal memory setup
by Leroy P Leahy 25 Jan '16

25 Jan '16

Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13446 -gerrit commit be04317a94fa548a33d353ab9b7ffdf16fc9a446 Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Mon Jan 11 14:03:24 2016 -0800 x86 Docs: Add sleep state and minimal memory setup Document how to add the sleep state and minimal memory setup. BRANCH=none BUG=None TEST=None Change-Id: Ibebeef34269dbf2366f1bea6d734f6bade4e4028 Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- Documentation/x86Board.html | 79 +++++++++++++++++++++++++++++++++++++++ Documentation/x86Development.html | 14 +++++++ Documentation/x86SoC.html | 53 ++++++++++++++++++++++++++ 3 files changed, 146 insertions(+) diff --git a/Documentation/x86Board.html b/Documentation/x86Board.html index 76282a6..acf2bc6 100644 --- a/Documentation/x86Board.html +++ b/Documentation/x86Board.html @@ -15,6 +15,7 @@ <ol> <li><a href="#RequiredFiles">Required Files</a></li> <li>Enable <a href="#SerialOutput">Serial Output</a></li> + <li>Load the <a href="#SpdData">Memory Timing Data</a></li> </ol> @@ -101,6 +102,84 @@ </ol> +<hr> +<h1><a name="SpdData">Memory Timing Data</a></h1> +<p> + Memory timing data is located in the flash. This data is in the format of + <a target="_blank" href="https://en.wikipedia.org/wiki/Serial_presence_detect">serial presence detect</a> + (SPD) data. + Use the following steps to load the SPD data: +</p> +<ol> + <li>Edit Kconfig to add the DISPLAY_SPD_DATA" value which enables the + display of the SPD data being passed to MemoryInit + </li> + <li>Create an "spd" subdirectory</li> + <li>Create an spd/spd.c file for the SPD implementation + <ol type="A"> + <li>Implement the mainboard_fill_spd_data routine + <ol type="i"> + <li>Read the SPD data either from the spd.bin file or using I2C or SMBUS</li> + <li>Fill in the pei_data structure with SPD data for each of the DIMMs</li> + <li>Set the DIMM channel configuration</li> + </ol> + </li> + </ol> + </li> + <li>Add an .spd.hex file containing the memory timing data to the spd subdirectory</li> + <li>Create spd/Makefile.inc + <ol type="A"> + <li>Add spd.c to romstage</li> + <li>Add the .spd.hex file to SPD_SOURCES</li> + </ol> + </li> + <li>Edit Makefile.inc to add the spd subdirectory</li> + <li>Edit romstage.c + <ol type="A"> + <li>Call mainboard_fill_spd_data</li> + <li>Add mainboard_memory_init_params to copy the SPD and DRAM + configuration data from the pei_data structure into the UPDs + for MemoryInit + </li> + </ol> + </li> + <li>Edit devicetree.cb + <ol type="A"> + <li>Include the UPD parameters for MemoryInit except for: + <ul> + <li>Address of SPD data</li> + <li>DRAM configuration set above</li> + </ul> + </li> + </ol> + </li> + <li>A working FSP + <a target="_blank" href="x86FSP1_1.html#MemoryInit">MemoryInit</a> + routine is required to complete debugging</li> + <li>Debug the result until port 0x80 outputs + <ol type="A"> + <li>0x34: + - Just after entering + <a target="_blank" href="https://chromium.googlesource.com/chromiumos/third_party/coreboot/+/chromeo…">raminit</a> + </li> + <li>0x36: + - Just before displaying the + <a target="_blank" href="https://chromium.googlesource.com/chromiumos/third_party/coreboot/+/chromeo…">UPD parameters</a> + for FSP MemoryInit + </li> + <li>0x92: <a target="_blank" href="https://chromium.googlesource.com/chromiumos/third_party/coreboot/+/chromeo…">POST_FSP_MEMORY_INIT</a> + - Just before calling FSP + <a target="_blank" href="https://chromium.googlesource.com/chromiumos/third_party/coreboot/+/chromeo…">MemoryInit</a> + </li> + <li>0x37: + - Just after returning from FSP + <a target="_blank" href="https://chromium.googlesource.com/chromiumos/third_party/coreboot/+/chromeo…">MemoryInit</a> + </li> + </ol> + </li> + <li>Continue debugging with CONFIG_DISPLAY_HOBS enabled until TempRamExit is called</li> +</ol> + <hr> <p>Modified: 24 January 2016</p> diff --git a/Documentation/x86Development.html b/Documentation/x86Development.html index ab797cb..818da30 100644 --- a/Documentation/x86Development.html +++ b/Documentation/x86Development.html @@ -56,6 +56,20 @@ </ol> </li> <li>Enable <a target="_blank" href="x86FSP1_1.html#CorebootFspDebugging">coreboot/FSP</a> debugging</li> + <li>Determine the <a target="_blank" href="x86SoC.html#PreviousSleepState">Previous Sleep State</a></li> + <li>Enable DRAM: + <ol type="A"> + <li>Implement the SoC + <a target="_blank" href="x86SoC.html#MemoryInit">MemoryInit</a> + Support + </li> + <li>Implement the board support to read the + <a target="_blank" href="x86Board.html#SpdData">Memory Timing Data</a> + </li> + </ol> + </li> + <li>Enable CONFIG_DISPLAY_MTRRS to verify the MTRR configuration</li> + <li>Coreboot should now attempt to load the payload</li> </ol> diff --git a/Documentation/x86SoC.html b/Documentation/x86SoC.html index 00b78b1..23f7f64 100644 --- a/Documentation/x86SoC.html +++ b/Documentation/x86SoC.html @@ -22,6 +22,8 @@ <li><a href="#Romstage">Romstage</a> <ol type="A"> <li>Enable <a href="#SerialOutput">Serial Output"</a></li> + <li>Get the <a href="#PreviousSleepState">Previous Sleep State</a></li> + <li>Add the <a href="#MemoryInit">MemoryInit</a> Support</li> </ol> </li> </ol> @@ -295,6 +297,57 @@ mv build/coreboot.rom.new build/coreboot.rom </ol> +<h2><a name="PreviousSleepState">Determine Previous Sleep State</a></h2> +<p> + The following steps implement the code to get the previous sleep state: +</p> +<ol> + <li>Implement the fill_power_state routine which determines the previous sleep state</li> + <li>Debug the result until port 0x80 outputs + <ol type="A"> + <li>0x32: + - Just after entering + <a target="_blank" href="https://chromium.googlesource.com/chromiumos/third_party/coreboot/+/chromeo…">romstage_common</a> + </li> + <li>0x33 - Just after calling + <a target="_blank" href="https://chromium.googlesource.com/chromiumos/third_party/coreboot/+/chromeo…">soc_pre_ram_init</a> + </li> + <li>0x34: + - Just after entering + <a target="_blank" href="https://chromium.googlesource.com/chromiumos/third_party/coreboot/+/chromeo…">raminit</a> + </li> + </ol> +</ol> + + +<h2><a name="MemoryInit">MemoryInit Support</a></h2> +<p> + The following steps implement the code to support the FSP MemoryInit call: +</p> +<ol> + <li>Add the chip.h header file to define the UPD values which get passed + to MemoryInit. Skip the values containing SPD addresses and DRAM + configuration data which is determined by the board. + <p> + <b>Build Note</b>: The src/mainboard/<Vendor>/<Board>/devicetree.cb + file specifies the default values for these parameters. The build + process creates the static.c module which contains the config data + structure containing these values. + </p> + </li> + <li>Edit romstage/romstage.c + <ol type="A"> + <li>Implement the romstage/romstage.c/soc_memory_init_params routine to + copy the values from the config structure into the UPD structure + </li> + <li>Implement the soc_display_memory_init_params routine to display + the updated UPD parameters by calling fsp_display_upd_value + </li> + </ol> + </li> +</ol> + + <hr> <p>Modified: 24 January 2016</p> </body>

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New patch to review for coreboot: Quark/Galileo: Enable Serial Port
by Leroy P Leahy 25 Jan '16

25 Jan '16

Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13445 -gerrit commit f9f90d3527d12f8af59f994ab2f63581a0c3a049 Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Sun Jan 24 18:51:58 2016 -0800 Quark/Galileo: Enable Serial Port Add the code to enable debug serial output using HSUART1: * Enable the code using Kconfig value ENABLE_BUILTIN_HSUART1 * Specify the portion of ESRAM to be used by romstage * Initialize the debug serial port * Note that the BIST value is always zero as validated in esram_init.inc * The initial TSC value is currently not saved! * Serial output indicates a successful test BRANCH=none BUG=None TEST=None Change-Id: I7e6181e8b9bc901c3ab236f0b56534850bb6bfd0 Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- src/mainboard/intel/galileo/Kconfig | 9 ++++ src/mainboard/intel/galileo/Makefile.inc | 4 ++ src/mainboard/intel/galileo/com_init.c | 32 +++++++++++++ src/soc/intel/quark/Kconfig | 30 ++++++++++++ src/soc/intel/quark/Makefile.inc | 4 ++ src/soc/intel/quark/include/soc/iomap.h | 31 +++++++++++++ src/soc/intel/quark/include/soc/pci_devs.h | 30 ++++++++++++ src/soc/intel/quark/include/soc/romstage.h | 33 +++++++++++++ src/soc/intel/quark/romstage/cache_as_ram.inc | 54 ++++++++++++++++++++- src/soc/intel/quark/tsc_freq.c | 40 ++++++++++++++++ src/soc/intel/quark/uart.c | 67 +++++++++++++++++++++++++++ 11 files changed, 332 insertions(+), 2 deletions(-) diff --git a/src/mainboard/intel/galileo/Kconfig b/src/mainboard/intel/galileo/Kconfig index eeb7ab4..b21df00 100755 --- a/src/mainboard/intel/galileo/Kconfig +++ b/src/mainboard/intel/galileo/Kconfig @@ -3,10 +3,19 @@ if BOARD_INTEL_GALILEO config BOARD_SPECIFIC_OPTIONS def_bool y select BOARD_ROMSIZE_KB_8192 + select ENABLE_BUILTIN_HSUART1 select HAVE_FSP_RAW_BIN select PLATFORM_USES_FSP1_1 select SOC_INTEL_QUARK +config DCACHE_RAM_BASE + hex + default 0x80070000 + +config DCACHE_RAM_SIZE + hex + default 0x00008000 + config HAVE_FSP_RAW_BIN bool "Should the Intel FSP binary be added to the flash image" help diff --git a/src/mainboard/intel/galileo/Makefile.inc b/src/mainboard/intel/galileo/Makefile.inc index 7a1603e..d6c5e52 100755 --- a/src/mainboard/intel/galileo/Makefile.inc +++ b/src/mainboard/intel/galileo/Makefile.inc @@ -18,6 +18,10 @@ ## Foundation, Inc. ## +romstage-$(CONFIG_ENABLE_BUILTIN_HSUART1) += com_init.c + +ramstage-$(CONFIG_ENABLE_BUILTIN_HSUART1) += com_init.c + # Add the FSP binary to the cbfs image ifeq ($(CONFIG_HAVE_FSP_RAW_BIN),y) cbfs-files-y += fsp.bin diff --git a/src/mainboard/intel/galileo/com_init.c b/src/mainboard/intel/galileo/com_init.c new file mode 100644 index 0000000..da50cfd --- /dev/null +++ b/src/mainboard/intel/galileo/com_init.c @@ -0,0 +1,32 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015-2016 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#include <fsp/car.h> +#include <device/pci.h> +#include <soc/iomap.h> +#include <soc/pci_devs.h> + +#if ENV_ROMSTAGE + +void car_mainboard_pre_console_init(void) +{ + pci_early_device_probe(0, HSUART1_DEV, UART_BASE_ADDRESS); +} +#endif /* ENV_ROMSTAGE */ diff --git a/src/soc/intel/quark/Kconfig b/src/soc/intel/quark/Kconfig index 197eb59..7b0cde1 100644 --- a/src/soc/intel/quark/Kconfig +++ b/src/soc/intel/quark/Kconfig @@ -11,6 +11,9 @@ config CPU_SPECIFIC_OPTIONS select ARCH_RAMSTAGE_X86_32 select ARCH_ROMSTAGE_X86_32 select ARCH_VERSTAGE_X86_32 + select SOC_INTEL_COMMON + select TSC_CONSTANT_RATE + select UDELAY_TSC config CBFS_SIZE hex @@ -56,6 +59,14 @@ config ENABLE_DEBUG_LED_TEMPRAMINIT help Indicate that TempRamInit was successful. +config ENABLE_BUILTIN_HSUART1 + bool "Enable built-in HSUART1" + default n + help + The Quark SoC has two HSUART. Choose this option to + configure the pads and enable HSUART1, which can be used for + the debug console. + config RMU_FILE string default "3rdparty/blobs/mainboard/$(MAINBOARDDIR)/rmu.bin" @@ -69,4 +80,23 @@ config RMU_LOC The location in CBFS that the RMU is located. It must match the strap-determined base address. +if ENABLE_BUILTIN_HSUART1 +config INTEL_UART_SPECIFIC_OPTIONS + def_bool y + select NO_UART_ON_SUPERIO + select DRIVERS_UART_8250MEM_32 + +config TTYS0_BASE + hex "HSUART1 Base Address" + depends on ENABLE_BUILTIN_HSUART1 + default 0xA0019000 + help + Memory mapped MMIO of HSUART1. + +config TTYS0_LCS + int + depends on ENABLE_BUILTIN_HSUART1 + default 3 + +endif # ENABLE_BUILTIN_HSUART1 endif # SOC_INTEL_QUARK diff --git a/src/soc/intel/quark/Makefile.inc b/src/soc/intel/quark/Makefile.inc index 39ad8af..bec1595 100644 --- a/src/soc/intel/quark/Makefile.inc +++ b/src/soc/intel/quark/Makefile.inc @@ -21,8 +21,12 @@ subdirs-y += romstage subdirs-y += ../../../cpu/x86/tsc romstage-y += memmap.c +romstage-y += tsc_freq.c +romstage-y += uart.c ramstage-y += memmap.c +ramstage-y += tsc_freq.c +ramstage-y += uart.c CPPFLAGS_common += -I$(src)/soc/intel/quark/include CPPFLAGS_common += -I$(src)/vendorcode/intel/fsp/fsp1_1/quark diff --git a/src/soc/intel/quark/include/soc/iomap.h b/src/soc/intel/quark/include/soc/iomap.h new file mode 100644 index 0000000..b6a7392 --- /dev/null +++ b/src/soc/intel/quark/include/soc/iomap.h @@ -0,0 +1,31 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015-2016 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _QUARK_IOMAP_H_ +#define _QUARK_IOMAP_H_ + +/* + * Memory Mapped IO base addresses. + */ + +/* UART MMIO */ +#define UART_BASE_ADDRESS CONFIG_TTYS0_BASE + +#endif /* _QUARK_IOMAP_H_ */ diff --git a/src/soc/intel/quark/include/soc/pci_devs.h b/src/soc/intel/quark/include/soc/pci_devs.h new file mode 100644 index 0000000..d022c66 --- /dev/null +++ b/src/soc/intel/quark/include/soc/pci_devs.h @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2013 Sage Electronic Engineering, LLC. + * Copyright (C) 2015-2016 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _QUARK_PCI_DEVS_H_ +#define _QUARK_PCI_DEVS_H_ + +/* IO Fabric 1 */ +#define SIO1_DEV 0x14 +# define HSUART1_DEV SIO1_DEV +# define HSUART1_FUNC 5 + +#endif /* _QUARK_PCI_DEVS_H_ */ diff --git a/src/soc/intel/quark/include/soc/romstage.h b/src/soc/intel/quark/include/soc/romstage.h new file mode 100644 index 0000000..8a80cd9 --- /dev/null +++ b/src/soc/intel/quark/include/soc/romstage.h @@ -0,0 +1,33 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2014 Sage Electronic Engineering, LLC. + * Copyright (C) 2015-2016 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _QUARK_ROMSTAGE_H_ +#define _QUARK_ROMSTAGE_H_ + +#if !defined(__PRE_RAM__) +#error "Don't include romstage.h from a ramstage compilation unit!" +#endif + +#include <fsp/util.h> + +int pci_early_device_func_probe(u8 bus, u8 dev, u8 func, u32 mmio_base); + +#endif /* _QUARK_ROMSTAGE_H_ */ diff --git a/src/soc/intel/quark/romstage/cache_as_ram.inc b/src/soc/intel/quark/romstage/cache_as_ram.inc index 80ac64d..89e6f88 100644 --- a/src/soc/intel/quark/romstage/cache_as_ram.inc +++ b/src/soc/intel/quark/romstage/cache_as_ram.inc @@ -112,8 +112,58 @@ CAR_init_done: movl %esi, %edx #endif /* CONFIG_ENABLE_DEBUG_LED_TEMPRAMINIT */ - clrl %eax - jmp halt2 + /* Setup bootloader stack */ + movl %edx, %esp + + /* + * eax: 0 + * ebp: FSP_INFO_HEADER address + * ecx: Temp RAM base + * edx: Temp RAM top + * edi: BIST value + * esp: Top of stack in temp RAM + */ + + /* Create cache_as_ram_params on stack */ + pushl %edx /* bootloader CAR end */ + pushl %ecx /* bootloader CAR begin */ + pushl %ebp /* FSP_INFO_HEADER */ + pushl %edi /* bist */ +// movd %mm1, %eax + pushl %eax /* tsc[63:32] */ +// movd %mm0, %eax + pushl %eax /* tsc[31:0] */ + pushl %esp /* pointer to cache_as_ram_params */ + + /* Save FSP_INFO_HEADER location in ebx */ + mov %ebp, %ebx + + /* Coreboot assumes stack/heap region will be zero */ + cld + movl %ecx, %edi + neg %ecx + /* Only clear up to current stack value. */ + add %esp, %ecx + shrl $2, %ecx + xorl %eax, %eax + rep stosl + +before_romstage: + post_code(0x23) + + /* Call cache_as_ram_main(struct cache_as_ram_params *) */ + call cache_as_ram_main + movb $0xB8, %ah + jmp .Lhlt + +/* One will never return from cache_as_ram_main() in verstage so there's + * no such thing as after ram init. */ +#if !ENV_VERSTAGE +#include "src/drivers/intel/fsp1_1/after_raminit.S" +#endif + + movb $0x69, %ah + jmp .Lhlt halt1: /* diff --git a/src/soc/intel/quark/tsc_freq.c b/src/soc/intel/quark/tsc_freq.c new file mode 100644 index 0000000..eef682a --- /dev/null +++ b/src/soc/intel/quark/tsc_freq.c @@ -0,0 +1,40 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stdint.h> +#include <cpu/x86/msr.h> +#include <cpu/x86/tsc.h> + +static unsigned long bus_freq_khz(void) +{ + /* cpu freq = 400 MHz */ + return 400 * 1000; +} + +unsigned long tsc_freq_mhz(void) +{ + /* assume ratio=1 */ + unsigned bclk_khz = bus_freq_khz(); + + if (!bclk_khz) + return 0; + + return (bclk_khz * 1) / 1000; +} diff --git a/src/soc/intel/quark/uart.c b/src/soc/intel/quark/uart.c new file mode 100644 index 0000000..2d39d1b --- /dev/null +++ b/src/soc/intel/quark/uart.c @@ -0,0 +1,67 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2003 Eric Biederman + * Copyright (C) 2006-2010 coresystems GmbH + * Copyright (C) 2015-2016 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +// Use simple device model for this file even in ramstage +#define __SIMPLE_DEVICE__ + +#include <console/uart.h> +#include <device/pci.h> +#include <device/pci_def.h> +#include <soc/pci_devs.h> + +#ifdef __PRE_RAM__ +int pci_early_device_probe(u8 bus, u8 dev, u32 mmio_base) +{ + uint16_t reg16; + + /* HSUART controller #1 (B0:D20:F5). */ + device_t uart_dev = PCI_DEV(bus, dev, HSUART1_FUNC); + + /* Decode BAR0(offset 0x10). */ + pci_write_config32(uart_dev, PCI_BASE_ADDRESS_0, mmio_base); + + /* Enable MEMBASE at CMD(offset 0x04). */ + reg16 = pci_read_config16(uart_dev, PCI_COMMAND); + reg16 |= PCI_COMMAND_MEMORY; + pci_write_config16(uart_dev, PCI_COMMAND, reg16); + + return 0; +} +#endif + +unsigned int uart_platform_refclk(void) +{ + return 44236800; +} + +uintptr_t uart_platform_base(int idx) +{ + if (idx < 6) { + /* HSUART controller #1 (B0:D20:F5). */ + device_t dev = PCI_DEV(0, HSUART1_DEV, HSUART1_FUNC); + + /* UART base address at BAR0(offset 0x10). */ + return (unsigned int) (pci_read_config32(dev, PCI_BASE_ADDRESS_0) & ~0xfff); + } + else { + return 0; + } +}

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coreboot-gerrit January 2016