coreboot-gerrit January 2016

coreboot-gerrit@coreboot.org

1 participants
2471 discussions

Patch set updated for coreboot: mb/intel/d510mo: Use native gfx initialization
by Damien Zammit 25 Jan '16

25 Jan '16

Damien Zammit (damien(a)zamaudio.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13034 -gerrit commit 8485ef57bae58f6abbca80c9c680f38e94c74524 Author: Damien Zammit <damien(a)zamaudio.com> Date: Tue Jan 26 13:55:43 2016 +1100 mb/intel/d510mo: Use native gfx initialization Change-Id: Ic4de7a762e90b379be3814afc61467e1cd099215 Signed-off-by: Damien Zammit <damien(a)zamaudio.com> --- src/mainboard/intel/d510mo/Kconfig | 2 ++ src/mainboard/intel/d510mo/devicetree.cb | 10 ++++++++-- src/mainboard/intel/d510mo/mainboard.c | 4 +++- 3 files changed, 13 insertions(+), 3 deletions(-) diff --git a/src/mainboard/intel/d510mo/Kconfig b/src/mainboard/intel/d510mo/Kconfig index 7981f92..7184665 100644 --- a/src/mainboard/intel/d510mo/Kconfig +++ b/src/mainboard/intel/d510mo/Kconfig @@ -23,6 +23,8 @@ config BOARD_SPECIFIC_OPTIONS select SUPERIO_WINBOND_W83627THG select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_1024 + select MAINBOARD_HAS_NATIVE_VGA_INIT + select INTEL_INT15 config MAX_CPUS int diff --git a/src/mainboard/intel/d510mo/devicetree.cb b/src/mainboard/intel/d510mo/devicetree.cb index c6f39a0..df5a0f9 100644 --- a/src/mainboard/intel/d510mo/devicetree.cb +++ b/src/mainboard/intel/d510mo/devicetree.cb @@ -15,14 +15,20 @@ # chip northbridge/intel/pineview # Northbridge + register "gfx.use_spread_spectrum_clock" = "0" + register "use_crt" = "1" + register "use_lvds" = "0" + device cpu_cluster 0 on # APIC cluster chip cpu/intel/socket_FCBGA559 # CPU device lapic 0 on end # APIC end end - device domain 0 on # PCI domain + device domain 0 on # PCI domain device pci 0.0 on end # Host Bridge - device pci 2.0 off end # Integrated graphics controller + device pci 1.0 off end # PEG + device pci 2.0 on end # Integrated graphics controller + device pci 2.1 on end # Integrated graphics controller 2 chip southbridge/intel/i82801gx # Southbridge register "pirqa_routing" = "0x0b" register "pirqb_routing" = "0x0b" diff --git a/src/mainboard/intel/d510mo/mainboard.c b/src/mainboard/intel/d510mo/mainboard.c index 94bee7e..4f0f32b 100644 --- a/src/mainboard/intel/d510mo/mainboard.c +++ b/src/mainboard/intel/d510mo/mainboard.c @@ -18,10 +18,12 @@ #include <device/pci_ops.h> #include <pc80/mc146818rtc.h> #include <device/pci.h> +#include <drivers/intel/gma/int15.h> static void mainboard_enable(device_t dev) { - dev->ops->init = NULL; + install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_NONE, + GMA_INT15_PANEL_FIT_DEFAULT, GMA_INT15_BOOT_DISPLAY_CRT, 0); } struct chip_operations mainboard_ops = {

1 0

Patch set updated for coreboot: intel/strago: Remove support for older rev boards
by Hannah Williams 25 Jan '16

25 Jan '16

Hannah Williams (hannah.williams(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13434 -gerrit commit 18a6a70cb1abd3339c1b7ef7ab6ea009d4b44d6a Author: Hannah Williams <hannah.williams(a)intel.com> Date: Mon Jan 25 14:36:56 2016 -0800 intel/strago: Remove support for older rev boards Cleaning up code to remove support for early revs of Strago board Change-Id: Ic0647a17d78164fd7dfadc731c9395a8ba08c235 Signed-off-by: Hannah Williams <hannah.williams(a)intel.com> --- src/mainboard/intel/strago/Makefile.inc | 2 - src/mainboard/intel/strago/acpi/mainboard.asl | 49 +---- src/mainboard/intel/strago/acpi_tables.c | 5 +- src/mainboard/intel/strago/gpio.c | 9 +- src/mainboard/intel/strago/gpio.h | 21 -- src/mainboard/intel/strago/gpio_bcrd2.c | 268 -------------------------- src/mainboard/intel/strago/gpio_dvt.c | 265 ------------------------- src/mainboard/intel/strago/onboard.h | 7 +- src/mainboard/intel/strago/ramstage.c | 6 +- src/mainboard/intel/strago/smihandler.c | 8 +- 10 files changed, 13 insertions(+), 627 deletions(-) diff --git a/src/mainboard/intel/strago/Makefile.inc b/src/mainboard/intel/strago/Makefile.inc index 9c21bed..5ba7bcc 100755 --- a/src/mainboard/intel/strago/Makefile.inc +++ b/src/mainboard/intel/strago/Makefile.inc @@ -22,8 +22,6 @@ ramstage-y += boardid.c ramstage-$(CONFIG_MAINBOARD_HAS_CHROMEOS) += chromeos.c ramstage-$(CONFIG_MAINBOARD_HAS_CHROMEOS) += ec.c ramstage-$(CONFIG_MAINBOARD_HAS_CHROMEOS) += gpio.c -ramstage-$(CONFIG_MAINBOARD_HAS_CHROMEOS) += gpio_dvt.c -ramstage-$(CONFIG_MAINBOARD_HAS_CHROMEOS) += gpio_bcrd2.c ramstage-y += irqroute.c ramstage-y += ramstage.c ramstage-y += w25q64.c diff --git a/src/mainboard/intel/strago/acpi/mainboard.asl b/src/mainboard/intel/strago/acpi/mainboard.asl index 48cabff..0353eed 100755 --- a/src/mainboard/intel/strago/acpi/mainboard.asl +++ b/src/mainboard/intel/strago/acpi/mainboard.asl @@ -68,25 +68,7 @@ Scope (\_SB.I2C1) BOARD_TOUCH_IRQ } }) - Name (BUF1, ResourceTemplate () - { - I2cSerialBus( - 0x26, /* SlaveAddress */ - ControllerInitiated, /* SlaveMode */ - 400000, /* ConnectionSpeed */ - AddressingMode7Bit, /* AddressingMode */ - "\\_SB.I2C1", /* ResourceSource */ - ) - Interrupt (ResourceConsumer, Edge, ActiveLow) - { - BOARD_DVT_TOUCH_IRQ - } - }) - If (LEqual (\BDID, BOARD_EVT)) { - Return (BUF0) - } Else { - Return (BUF1) - } + Return (BUF0) } Method (_STA) @@ -125,25 +107,7 @@ Scope (\_SB.I2C1) BOARD_TOUCH_IRQ } }) - Name (BUF1, ResourceTemplate () - { - I2cSerialBus( - 0x4b, /* SlaveAddress */ - ControllerInitiated, /* SlaveMode */ - 400000, /* ConnectionSpeed */ - AddressingMode7Bit, /* AddressingMode */ - "\\_SB.I2C1", /* ResourceSource */ - ) - Interrupt (ResourceConsumer, Edge, ActiveLow) - { - BOARD_DVT_TOUCH_IRQ - } - }) - If (LEqual (\BDID, BOARD_EVT)) { - Return (BUF0) - } Else { - Return (BUF1) - } + Return (BUF0) } Method (_STA) @@ -164,7 +128,6 @@ Scope (\_SB.I2C1) Scope (\_SB.I2C5) { - /* Realtek Audio Codec */ Device (RTEK) /* Audio Codec driver I2C */ { @@ -186,7 +149,6 @@ Scope (\_SB.I2C5) "\\_SB.I2C5", /* ResourceSource: I2C bus controller name */ ) - /* Jack Detect (index 0) */ GpioInt (Edge, ActiveLow, ExclusiveAndWake, PullNone,, "\\_SB.GPSW") { JACK_DETECT_GPIO_INDEX } @@ -196,12 +158,7 @@ Scope (\_SB.I2C5) Method (_STA) { - If (LEqual (\S5EN, 1)) { - If (LEqual (\BDID, BOARD_BCRD2)) { - Return (0xF) - } - } - Return (0x0) + Return (0xF) } } } diff --git a/src/mainboard/intel/strago/acpi_tables.c b/src/mainboard/intel/strago/acpi_tables.c index 72538b7..591d934 100755 --- a/src/mainboard/intel/strago/acpi_tables.c +++ b/src/mainboard/intel/strago/acpi_tables.c @@ -47,8 +47,9 @@ void acpi_create_gnvs(global_nvs_t *gnvs) /* Enable DPTF */ gnvs->dpte = 1; - if (board_id() == BOARD_BCRD2) - gnvs->dev.lpss_en[LPSS_NVS_I2C2] = 0; + + /* PMIC is configured in I2C1, hidden it from OS */ + gnvs->dev.lpss_en[LPSS_NVS_I2C2] = 0; } unsigned long acpi_fill_madt(unsigned long current) diff --git a/src/mainboard/intel/strago/gpio.c b/src/mainboard/intel/strago/gpio.c index c57a573..0d126e4 100755 --- a/src/mainboard/intel/strago/gpio.c +++ b/src/mainboard/intel/strago/gpio.c @@ -266,12 +266,5 @@ static struct soc_gpio_config gpio_config = { struct soc_gpio_config *mainboard_get_gpios(void) { - switch (board_id()) { - case BOARD_DVT: - return get_override_gpios_dvt(); - case BOARD_BCRD2: - return get_override_gpios_bcrd2(); - default: - return &gpio_config; - } + return &gpio_config; } diff --git a/src/mainboard/intel/strago/gpio.h b/src/mainboard/intel/strago/gpio.h deleted file mode 100644 index c775995..0000000 --- a/src/mainboard/intel/strago/gpio.h +++ /dev/null @@ -1,21 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2015 Intel Corp. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ -#ifndef _BOARD_GPIO_H_ -#define _BOARD_GPIO_H_ - -struct soc_gpio_config *get_override_gpios_dvt(void); -struct soc_gpio_config *get_override_gpios_bcrd2(void); -#endif diff --git a/src/mainboard/intel/strago/gpio_bcrd2.c b/src/mainboard/intel/strago/gpio_bcrd2.c deleted file mode 100644 index 4cd622b..0000000 --- a/src/mainboard/intel/strago/gpio_bcrd2.c +++ /dev/null @@ -1,268 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright(C) 2013 Google Inc. - * Copyright (C) 2015 Intel Corp. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include "irqroute.h" -#include <soc/gpio.h> -#include <stdlib.h> -#include "gpio.h" - -/* South East Community */ -static const struct soc_gpio_map gpse_gpio_map[] = { - Native_M1,/* MF_PLT_CLK0 */ - GPIO_NC, /* 01 PWM1 */ - GPIO_INPUT_NO_PULL, /* 02 MF_PLT_CLK1, RAMID2 */ - GPIO_NC, /* 03 MF_PLT_CLK4 */ - GPIO_NC, /* 04 MF_PLT_CLK3 */ - GPIO_NC, /* PWM0 05 */ - GPIO_NC, /* 06 MF_PLT_CLK5 */ - GPIO_NC, /* 07 MF_PLT_CLK2 */ - GPIO_NC, /* 15 SDMMC2_D3_CD_B */ - Native_M1, /* 16 SDMMC1_CLK */ - NATIVE_PU20K(1), /* 17 SDMMC1_D0 */ - GPIO_NC, /* 18 SDMMC2_D1 */ - GPIO_NC, /* 19 SDMMC2_CLK */ - NATIVE_PU20K(1),/* 20 SDMMC1_D2 */ - GPIO_NC, /* 21 SDMMC2_D2 */ - GPIO_NC, /* 22 SDMMC2_CMD */ - NATIVE_PU20K(1), /* 23 SDMMC1_CMD */ - NATIVE_PU20K(1), /* 24 SDMMC1_D1 */ - GPIO_NC, /* 25 SDMMC2_D0 */ - NATIVE_PU20K(1), /* 26 SDMMC1_D3_CD_B */ - NATIVE_PU20K(1), /* 30 SDMMC3_D1 */ - Native_M1, /* 31 SDMMC3_CLK */ - NATIVE_PU20K(1), /* 32 SDMMC3_D3 */ - NATIVE_PU20K(1), /* 33 SDMMC3_D2 */ - NATIVE_PU20K(1), /* 34 SDMMC3_CMD */ - NATIVE_PU20K(1), /* 35 SDMMC3_D0 */ - NATIVE_PU20K(1), /* 45 MF_LPC_AD2 */ - Native_M1, /* 46 LPC_CLKRUNB */ - NATIVE_PU20K(1), /* 47 MF_LPC_AD0 */ - Native_M1, /* 48 LPC_FRAMEB */ - Native_M1, /* 49 MF_LPC_CLKOUT1 */ - NATIVE_PU20K(1), /* 50 MF_LPC_AD3 */ - Native_M1, /* 51 MF_LPC_CLKOUT0 */ - NATIVE_PU20K(1), /* 52 MF_LPC_AD1 */ - Native_M1,/* SPI1_MISO */ - Native_M1, /* 61 SPI1_CS0_B */ - Native_M1, /* SPI1_CLK */ - NATIVE_PU20K(1), /* 63 MMC1_D6 */ - Native_M1, /* 62 SPI1_MOSI */ - NATIVE_PU20K(1), /* 65 MMC1_D5 */ - GPIO_NC, /* SPI1_CS1_B 66 */ - NATIVE_PU20K(1), /* 67 MMC1_D4_SD_WE */ - NATIVE_PU20K(1), /* 68 MMC1_D7 */ - GPIO_NC, /* 69 MMC1_RCLK */ - Native_M1, /* 75 GPO USB_OC1_B */ - Native_M1, /* 76 PMU_RESETBUTTON_B */ - GPI(trig_edge_both, L0, NA, non_maskable, en_edge_detect, NA , NA), - /* GPIO_ALERT 77 */ - Native_M1, /* 78 SDMMC3_PWR_EN_B */ - GPIO_NC, /* 79 GPI ILB_SERIRQ */ - Native_M1, /* 80 USB_OC0_B */ - GPI(trig_edge_both, L1, P_20K_H, non_maskable, - en_edge_detect, NA , NA), - /* 81 SDMMC3_CD_B */ - GPIO_NC, /* 82 spkr asummed gpio number */ - Native_M1, /* 83 SUSPWRDNACK */ - SPARE_PIN,/* 84 spare pin */ - Native_M1, /* 85 SDMMC3_1P8_EN */ - GPIO_END -}; - - -/* South West Community */ -static const struct soc_gpio_map gpsw_gpio_map[] = { - GPIO_NC, /* 00 FST_SPI_D2 */ - Native_M1, /* 01 FST_SPI_D0 */ - Native_M1, /* 02 FST_SPI_CLK */ - GPIO_NC, /* 03 FST_SPI_D3 */ - GPIO_NC, /* GPO FST_SPI_CS1_B */ - Native_M1, /* 05 FST_SPI_D1 */ - Native_M1, /* 06 FST_SPI_CS0_B */ - GPIO_NC, /* 07 FST_SPI_CS2_B */ - GPIO_NC, /* 15 UART1_RTS_B */ - Native_M2, /* 16 UART1_RXD */ - GPIO_NC, /* 17 UART2_RXD */ - GPIO_NC, /* 18 UART1_CTS_B */ - GPIO_NC, /* 19 UART2_RTS_B */ - Native_M2, /* 20 UART1_TXD */ - GPIO_NC, /* 21 UART2_TXD */ - GPIO_NC, /* 22 UART2_CTS_B */ - GPIO_NC, /* 30 MF_HDA_CLK */ - GPIO_NC, /* 31 GPIO_SW31/MF_HDA_RSTB */ - GPIO_NC, /* 32 GPIO_SW32 /MF_HDA_SDI0 */ - GPIO_NC, /* 33 MF_HDA_SDO */ - GPI(trig_edge_both, L3, P_1K_H, non_maskable, en_edge_detect, NA, NA), - /* 34 MF_HDA_DOCKRSTB */ - GPIO_NC, /* 35 MF_HDA_SYNC */ - GPIO_NC, /* 36 GPIO_SW36 MF_HDA_SDI1 */ - GPI(trig_edge_both, L2, P_1K_H, non_maskable, en_edge_detect, NA, NA), - /* 37 MF_HDA_DOCKENB */ - NATIVE_PU1K_CSEN_INVTX(1), /* 45 I2C5_SDA */ - NATIVE_PU1K_CSEN_INVTX(1), /* 46 I2C4_SDA */ - NATIVE_PU1K_CSEN_INVTX(1), /* 47 I2C6_SDA */ - NATIVE_PU1K_CSEN_INVTX(1), /* 48 I2C5_SCL */ - GPIO_NC, /* 49 I2C_NFC_SDA */ - NATIVE_PU1K_CSEN_INVTX(1), /* 50 I2C4_SCL */ - NATIVE_PU1K_CSEN_INVTX(1), /* 51 I2C6_SCL */ - GPIO_NC, /* 52 I2C_NFC_SCL */ - NATIVE_PU1K_CSEN_INVTX(1), /* 60 I2C1_SDA */ - NATIVE_PU1K_CSEN_INVTX(1), /* 61 I2C0_SDA */ - NATIVE_PU1K_CSEN_INVTX(1), /* 62 I2C2_SDA */ - NATIVE_PU1K_CSEN_INVTX(1), /* 63 I2C1_SCL */ - GPIO_INPUT_NO_PULL, /* 64 I2C3_SDA RAMID3*/ - NATIVE_PU1K_CSEN_INVTX(1), /* 65 I2C0_SCL */ - NATIVE_PU1K_CSEN_INVTX(1), /* 66 I2C2_SCL */ - GPIO_INPUT_NO_PULL,/* 67 I2C3_SCL,RAMID1 */ - GPIO_OUT_HIGH, /* 75 SATA_GP0 */ - GPIO_NC, - /* 76 GPI SATA_GP1 */ - Native_M1, /* 77 SATA_LEDN */ - GPIO_NC, /* 80 SATA_GP3 */ - Native_M1, /* 81 NFC_DEV_WAKE , MF_SMB_CLK */ - GPIO_INPUT_NO_PULL, /* 80 SATA_GP3,RAMID0 */ - Native_M1, /* 81 NFC_DEV_WAKE , MF_SMB_CLK */ - Native_M1, /* 82 NFC_FW_DOWNLOAD, MF_SMB_DATA */ - /* Per DE request, change PCIE_CLKREQ0123B to GPIO_INPUT */ - Native_M1, /* 90 PCIE_CLKREQ0B */ - GPIO_INPUT_PU_20K, /* 91 GPI PCIE_CLKREQ1B/LTE_WAKE# */ - Native_M1, /* 92 GP_SSP_2_CLK */ - NATIVE_PU20K(1), /* 93 PCIE_CLKREQ2B/PCIE_CLKREQ_WLAN# */ - Native_M1, /* 94 GP_SSP_2_RXD */ - GPI(trig_edge_both, L1, P_5K_H, non_maskable, en_edge_detect, NA, NA), - /* 95 PCIE_CLKREQ3B/AUDIO_CODEC_IRQ */ - Native_M1, /* 96 GP_SSP_2_FS */ - NATIVE_FUNC(1, 0, inv_tx_enable), /* 97 GP_SSP_2f_TXD */ - GPIO_END -}; - - -/* North Community */ -static const struct soc_gpio_map gpn_gpio_map[] = { - Native_M5, /* 00 GPIO_DFX0 */ - Native_M5, /* 01 GPIO_DFX3 */ - Native_M1, /* 02 GPIO_DFX7 */ - Native_M5, /* 03 GPIO_DFX1 */ - Native_M1, /* 04 GPIO_DFX5 */ - Native_M1, /* 05 GPIO_DFX4 */ - GPI(trig_edge_low, L5, NA, non_maskable, en_rx_data, NA, NA), - /* 06 GPIO_DFX8 */ - Native_M5, /* 07 GPIO_DFX2 */ - Native_M8, /* 08 GPIO_DFX6 */ - GPI(trig_edge_low, L8, NA, non_maskable, en_edge_rx_data , - UNMASK_WAKE, SCI), /* 15 GPIO_SUS0 */ - GPO_FUNC(NA, NA), /* 16 SEC_GPIO_SUS10 */ - GPI(trig_edge_low, L0, P_1K_H, non_maskable, NA, NA, NA), - /* 17 GPIO_SUS3 */ - GPI(trig_edge_low, L1, P_1K_H, non_maskable, NA, UNMASK_WAKE, NA), - /* 18 GPIO_SUS7 */ - GPI(trig_edge_low, L3, P_1K_H, non_maskable, NA, UNMASK_WAKE, NA), - /* 19 GPIO_SUS1 */ - GPIO_NC, /* 20 GPIO_SUS5 */ - GPI(trig_edge_high, L2, P_20K_H, non_maskable, - en_edge_rx_data, NA , NA), - /* 21 SEC_GPIO_SUS11 */ - GPIO_NC, /* 22 GPIO_SUS4 */ - GPIO_NC, - /* 23 SEC_GPIO_SUS8 */ - Native_M6, /* 24 GPIO_SUS2 */ - GPIO_INPUT_PU_5K,/* 25 GPIO_SUS6 */ - Native_M1, /* 26 CX_PREQ_B */ - GPIO_NC, /* 27 SEC_GPIO_SUS9 */ - Native_M1, /* 30 TRST_B */ - Native_M1, /* 31 TCK */ - GPIO_SKIP, /* 32 PROCHOT_B */ - GPIO_SKIP, /* 33 SVID0_DATA */ - Native_M1, /* 34 TMS */ - GPIO_NC, /* 35 CX_PRDY_B_2 */ - GPIO_NC, /* 36 TDO_2 */ - Native_M1, /* 37 CX_PRDY_B */ - GPIO_SKIP, /* 38 SVID0_ALERT_B */ - Native_M1, /* 39 TDO */ - GPIO_SKIP, /* 40 SVID0_CLK */ - Native_M1, /* 41 TDI */ - Native_M2, /* 45 GP_CAMERASB05 */ - Native_M2, /* 46 GP_CAMERASB02 */ - Native_M2, /* 47 GP_CAMERASB08 */ - Native_M2, /* 48 GP_CAMERASB00 */ - Native_M2, /* 49 GP_CAMERASBO6 */ - GPIO_NC, /* 50 GP_CAMERASB10 */ - Native_M2, /* 51 GP_CAMERASB03 */ - GPIO_NC, /* 52 GP_CAMERASB09 */ - Native_M2, /* 53 GP_CAMERASB01 */ - Native_M2, /* 54 GP_CAMERASB07 */ - GPIO_NC, /* 55 GP_CAMERASB11 */ - Native_M2, /* 56 GP_CAMERASB04 */ - GPIO_NC, /* 60 PANEL0_BKLTEN */ - Native_M1, /* 61 HV_DDI0_HPD */ - NATIVE_PU1K_M1, /* 62 HV_DDI2_DDC_SDA */ - Native_M1, /* 63 PANEL1_BKLTCTL */ - NATIVE_TX_RX_EN, /* 64 HV_DDI1_HPD */ - GPIO_NC, /* 65 PANEL0_BKLTCTL */ - GPIO_NC, /* 66 HV_DDI0_DDC_SDA */ - NATIVE_PU1K_M1, /* 67 HV_DDI2_DDC_SCL */ - NATIVE_TX_RX_EN, /* 68 HV_DDI2_HPD */ - Native_M1, /* 69 PANEL1_VDDEN */ - Native_M1, /* 70 PANEL1_BKLTEN */ - GPIO_NC, /* 71 HV_DDI0_DDC_SCL */ - GPIO_NC, /* 72 PANEL0_VDDEN */ - GPIO_END -}; - - -/* East Community */ -static const struct soc_gpio_map gpe_gpio_map[] = { - Native_M1, /* 00 PMU_SLP_S3_B */ - GPIO_NC, /* 01 PMU_BATLOW_B */ - Native_M1, /* 02 SUS_STAT_B */ - Native_M1, /* 03 PMU_SLP_S0IX_B */ - Native_M1, /* 04 PMU_AC_PRESENT */ - Native_M1, /* 05 PMU_PLTRST_B */ - Native_M1, /* 06 PMU_SUSCLK */ - GPIO_NC, /* 07 PMU_SLP_LAN_B */ - Native_M1, /* 08 PMU_PWRBTN_B */ - Native_M1, /* 09 PMU_SLP_S4_B */ - NATIVE_FUNC(M1, P_1K_H, NA), /* 10 PMU_WAKE_B */ - GPIO_NC, /* 11 PMU_WAKE_LAN_B */ - GPIO_NC, /* 15 MF_GPIO_3 */ - GPIO_NC, /* 16 MF_GPIO_7 */ - GPIO_NC, /* 17 MF_I2C1_SCL */ - GPIO_NC, /* 18 MF_GPIO_1 */ - GPIO_NC, /* 19 MF_GPIO_5 */ - GPIO_NC, /* 20 MF_GPIO_9 */ - GPIO_NC, /* 21 MF_GPIO_0 */ - GPIO_NC, /* 22 MF_GPIO_4 */ - GPIO_NC, /* 23 MF_GPIO_8 */ - GPIO_NC, /* 24 MF_GPIO_2 */ - GPIO_NC, /* 25 MF_GPIO_6 */ - GPIO_NC, /* 26 MF_I2C1_SDA */ - GPIO_END -}; - - -static struct soc_gpio_config gpio_config = { - /* BSW */ - .north = gpn_gpio_map, - .southeast = gpse_gpio_map, - .southwest = gpsw_gpio_map, - .east = gpe_gpio_map -}; - -struct soc_gpio_config *get_override_gpios_bcrd2(void) -{ - return &gpio_config; - -} diff --git a/src/mainboard/intel/strago/gpio_dvt.c b/src/mainboard/intel/strago/gpio_dvt.c deleted file mode 100755 index 24c6b3d..0000000 --- a/src/mainboard/intel/strago/gpio_dvt.c +++ /dev/null @@ -1,265 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright(C) 2013 Google Inc. - * Copyright (C) 2015 Intel Corp. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include "irqroute.h" -#include <soc/gpio.h> -#include <stdlib.h> -#include "gpio.h" - -/* South East Community */ -static const struct soc_gpio_map gpse_gpio_map[] = { - Native_M1,/* MF_PLT_CLK0 */ - GPIO_NC, /* 01 PWM1 */ - GPIO_INPUT_NO_PULL, /* 02 MF_PLT_CLK1, RAMID2 */ - GPIO_NC, /* 03 MF_PLT_CLK4 */ - GPIO_NC, /* 04 MF_PLT_CLK3 */ - GPIO_NC, /* PWM0 05 */ - GPIO_NC, /* 06 MF_PLT_CLK5 */ - GPIO_NC, /* 07 MF_PLT_CLK2 */ - GPIO_NC, /* 15 SDMMC2_D3_CD_B */ - Native_M1, /* 16 SDMMC1_CLK */ - NATIVE_PU20K(1), /* 17 SDMMC1_D0 */ - GPIO_NC, /* 18 SDMMC2_D1 */ - GPIO_NC, /* 19 SDMMC2_CLK */ - NATIVE_PU20K(1),/* 20 SDMMC1_D2 */ - GPIO_NC, /* 21 SDMMC2_D2 */ - GPIO_NC, /* 22 SDMMC2_CMD */ - NATIVE_PU20K(1), /* 23 SDMMC1_CMD */ - NATIVE_PU20K(1), /* 24 SDMMC1_D1 */ - GPIO_NC, /* 25 SDMMC2_D0 */ - NATIVE_PU20K(1), /* 26 SDMMC1_D3_CD_B */ - NATIVE_PU20K(1), /* 30 SDMMC3_D1 */ - Native_M1, /* 31 SDMMC3_CLK */ - NATIVE_PU20K(1), /* 32 SDMMC3_D3 */ - NATIVE_PU20K(1), /* 33 SDMMC3_D2 */ - NATIVE_PU20K(1), /* 34 SDMMC3_CMD */ - NATIVE_PU20K(1), /* 35 SDMMC3_D0 */ - NATIVE_PU20K(1), /* 45 MF_LPC_AD2 */ - Native_M1, /* 46 LPC_CLKRUNB */ - NATIVE_PU20K(1), /* 47 MF_LPC_AD0 */ - Native_M1, /* 48 LPC_FRAMEB */ - Native_M1, /* 49 MF_LPC_CLKOUT1 */ - NATIVE_PU20K(1), /* 50 MF_LPC_AD3 */ - Native_M1, /* 51 MF_LPC_CLKOUT0 */ - NATIVE_PU20K(1), /* 52 MF_LPC_AD1 */ - Native_M1,/* SPI1_MISO */ - Native_M1, /* 61 SPI1_CS0_B */ - Native_M1, /* SPI1_CLK */ - NATIVE_PU20K(1), /* 63 MMC1_D6 */ - Native_M1, /* 62 SPI1_MOSI */ - NATIVE_PU20K(1), /* 65 MMC1_D5 */ - GPIO_NC, /* SPI1_CS1_B 66 */ - NATIVE_PU20K(1), /* 67 MMC1_D4_SD_WE */ - NATIVE_PU20K(1), /* 68 MMC1_D7 */ - GPIO_NC, /* 69 MMC1_RCLK */ - Native_M1, /* 75 GPO USB_OC1_B */ - Native_M1, /* 76 PMU_RESETBUTTON_B */ - GPI(trig_edge_both, L0, NA, non_maskable, en_edge_detect, NA , NA), - /* GPIO_ALERT 77 */ - Native_M1, /* 78 SDMMC3_PWR_EN_B */ - GPIO_NC, /* 79 GPI ILB_SERIRQ */ - Native_M1, /* 80 USB_OC0_B */ - NATIVE_INT(1, L1), /* 81 SDMMC3_CD_B */ - GPIO_NC, /* 82 spkr asummed gpio number */ - Native_M1, /* 83 SUSPWRDNACK */ - SPARE_PIN,/* 84 spare pin */ - Native_M1, /* 85 SDMMC3_1P8_EN */ - GPIO_END -}; - - -/* South West Community */ -static const struct soc_gpio_map gpsw_gpio_map[] = { - GPIO_NC, /* 00 FST_SPI_D2 */ - Native_M1, /* 01 FST_SPI_D0 */ - Native_M1, /* 02 FST_SPI_CLK */ - GPIO_NC, /* 03 FST_SPI_D3 */ - GPIO_NC, /* GPO FST_SPI_CS1_B */ - Native_M1, /* 05 FST_SPI_D1 */ - Native_M1, /* 06 FST_SPI_CS0_B */ - GPIO_NC, /* 07 FST_SPI_CS2_B */ - GPIO_NC, /* 15 UART1_RTS_B */ - Native_M2, /* 16 UART1_RXD */ - GPIO_NC, /* 17 UART2_RXD */ - GPIO_NC, /* 18 UART1_CTS_B */ - GPIO_NC, /* 19 UART2_RTS_B */ - Native_M2, /* 20 UART1_TXD */ - GPIO_NC, /* 21 UART2_TXD */ - GPIO_NC, /* 22 UART2_CTS_B */ - GPIO_NC, /* 30 MF_HDA_CLK */ - GPIO_NC, /* 31 GPIO_SW31/MF_HDA_RSTB */ - GPIO_NC, /* 32 GPIO_SW32 /MF_HDA_SDI0 */ - GPIO_NC, /* 33 MF_HDA_SDO */ - GPI(trig_edge_both, L3, P_1K_H, non_maskable, en_edge_detect, NA, NA), - /* 34 MF_HDA_DOCKRSTB */ - GPIO_NC, /* 35 MF_HDA_SYNC */ - GPIO_NC, /* 36 GPIO_SW36 MF_HDA_SDI1 */ - GPI(trig_edge_both, L2, P_1K_H, non_maskable, en_edge_detect, NA, NA), - /* 37 MF_HDA_DOCKENB */ - NATIVE_PU1K_CSEN_INVTX(1), /* 45 I2C5_SDA */ - GPIO_NC, /* 46 I2C4_SDA */ - NATIVE_PU1K_CSEN_INVTX(1), /* 47 I2C6_SDA */ - NATIVE_PU1K_CSEN_INVTX(1), /* 48 I2C5_SCL */ - GPIO_NC, /* 49 I2C_NFC_SDA */ - GPIO_NC, /* 50 I2C4_SCL */ - NATIVE_PU1K_CSEN_INVTX(1), /* 51 I2C6_SCL */ - GPIO_NC, /* 52 I2C_NFC_SCL */ - NATIVE_PU1K_CSEN_INVTX(1), /* 60 I2C1_SDA */ - NATIVE_PU1K_CSEN_INVTX(1), /* 61 I2C0_SDA */ - NATIVE_PU1K_CSEN_INVTX(1), /* 62 I2C2_SDA */ - NATIVE_PU1K_CSEN_INVTX(1), /* 63 I2C1_SCL */ - GPIO_INPUT_NO_PULL, /* 64 I2C3_SDA RAMID3*/ - NATIVE_PU1K_CSEN_INVTX(1), /* 65 I2C0_SCL */ - NATIVE_PU1K_CSEN_INVTX(1), /* 66 I2C2_SCL */ - GPIO_INPUT_NO_PULL,/* 67 I2C3_SCL,RAMID1 */ - GPIO_OUT_HIGH, /* 75 SATA_GP0 */ - GPIO_NC, - /* 76 GPI SATA_GP1 */ - Native_M1, /* 77 SATA_LEDN */ - GPIO_NC, /* 80 SATA_GP3 */ - Native_M1, /* 81 NFC_DEV_WAKE , MF_SMB_CLK */ - GPIO_INPUT_NO_PULL, /* 80 SATA_GP3,RAMID0 */ - Native_M1, /* 81 NFC_DEV_WAKE , MF_SMB_CLK */ - Native_M1, /* 82 NFC_FW_DOWNLOAD, MF_SMB_DATA */ - /* Per DE request, change PCIE_CLKREQ0123B to GPIO_INPUT */ - Native_M1, /* 90 PCIE_CLKREQ0B */ - GPIO_INPUT_PU_20K, /* 91 GPI PCIE_CLKREQ1B/LTE_WAKE# */ - Native_M1, /* 92 GP_SSP_2_CLK */ - NATIVE_PU20K(1), /* 93 PCIE_CLKREQ2B/PCIE_CLKREQ_WLAN# */ - Native_M1, /* 94 GP_SSP_2_RXD */ - GPI(trig_edge_both, L1, P_5K_H, non_maskable, en_edge_detect, NA, NA), - /* 95 PCIE_CLKREQ3B/AUDIO_CODEC_IRQ */ - Native_M1, /* 96 GP_SSP_2_FS */ - NATIVE_FUNC(1, 0, inv_tx_enable), /* 97 GP_SSP_2f_TXD */ - GPIO_END -}; - - -/* North Community */ -static const struct soc_gpio_map gpn_gpio_map[] = { - Native_M5, /* 00 GPIO_DFX0 */ - Native_M5, /* 01 GPIO_DFX3 */ - Native_M1, /* 02 GPIO_DFX7 */ - Native_M5, /* 03 GPIO_DFX1 */ - Native_M1, /* 04 GPIO_DFX5 */ - Native_M1, /* 05 GPIO_DFX4 */ - GPI(trig_edge_low, L5, NA, non_maskable, en_rx_data, NA, NA), - /* 06 GPIO_DFX8 */ - Native_M5, /* 07 GPIO_DFX2 */ - Native_M8, /* 08 GPIO_DFX6 */ - GPI(trig_edge_low, L8, NA, non_maskable, en_edge_rx_data , - UNMASK_WAKE, SCI), /* 15 GPIO_SUS0 */ - GPO_FUNC(NA, NA), /* 16 SEC_GPIO_SUS10 */ - GPI(trig_edge_low, L0, P_1K_H, non_maskable, NA, NA, NA), - /* 17 GPIO_SUS3 */ - GPI(trig_edge_low, L1, P_1K_H, non_maskable, NA, UNMASK_WAKE, NA), - /* 18 GPIO_SUS7 */ - GPI(trig_edge_low, L3, P_1K_H, non_maskable, NA, UNMASK_WAKE, NA), - /* 19 GPIO_SUS1 */ - GPIO_NC, /* 20 GPIO_SUS5 */ - GPI(trig_edge_high, L2, P_20K_H, non_maskable, en_edge_rx_data, NA , NA), - /* 21 SEC_GPIO_SUS11 */ - GPIO_NC, /* 22 GPIO_SUS4 */ - GPIO_NC, - /* 23 SEC_GPIO_SUS8 */ - Native_M6, /* 24 GPIO_SUS2 */ - GPIO_INPUT_PU_5K,/* 25 GPIO_SUS6 */ - Native_M1, /* 26 CX_PREQ_B */ - GPIO_NC, /* 27 SEC_GPIO_SUS9 */ - Native_M1, /* 30 TRST_B */ - Native_M1, /* 31 TCK */ - GPIO_SKIP, /* 32 PROCHOT_B */ - GPIO_SKIP, /* 33 SVID0_DATA */ - Native_M1, /* 34 TMS */ - GPIO_NC, /* 35 CX_PRDY_B_2 */ - GPIO_NC, /* 36 TDO_2 */ - Native_M1, /* 37 CX_PRDY_B */ - GPIO_SKIP, /* 38 SVID0_ALERT_B */ - Native_M1, /* 39 TDO */ - GPIO_SKIP, /* 40 SVID0_CLK */ - Native_M1, /* 41 TDI */ - Native_M2, /* 45 GP_CAMERASB05 */ - Native_M2, /* 46 GP_CAMERASB02 */ - Native_M2, /* 47 GP_CAMERASB08 */ - Native_M2, /* 48 GP_CAMERASB00 */ - Native_M2, /* 49 GP_CAMERASBO6 */ - GPIO_NC, /* 50 GP_CAMERASB10 */ - Native_M2, /* 51 GP_CAMERASB03 */ - GPIO_NC, /* 52 GP_CAMERASB09 */ - Native_M2, /* 53 GP_CAMERASB01 */ - Native_M2, /* 54 GP_CAMERASB07 */ - GPIO_NC, /* 55 GP_CAMERASB11 */ - Native_M2, /* 56 GP_CAMERASB04 */ - GPIO_NC, /* 60 PANEL0_BKLTEN */ - Native_M1, /* 61 HV_DDI0_HPD */ - NATIVE_PU1K_M1, /* 62 HV_DDI2_DDC_SDA */ - Native_M1, /* 63 PANEL1_BKLTCTL */ - NATIVE_TX_RX_EN, /* 64 HV_DDI1_HPD */ - GPIO_NC, /* 65 PANEL0_BKLTCTL */ - GPIO_NC, /* 66 HV_DDI0_DDC_SDA */ - NATIVE_PU1K_M1, /* 67 HV_DDI2_DDC_SCL */ - NATIVE_TX_RX_EN, /* 68 HV_DDI2_HPD */ - Native_M1, /* 69 PANEL1_VDDEN */ - Native_M1, /* 70 PANEL1_BKLTEN */ - GPIO_NC, /* 71 HV_DDI0_DDC_SCL */ - GPIO_NC, /* 72 PANEL0_VDDEN */ - GPIO_END -}; - - -/* East Community */ -static const struct soc_gpio_map gpe_gpio_map[] = { - Native_M1, /* 00 PMU_SLP_S3_B */ - GPIO_NC, /* 01 PMU_BATLOW_B */ - Native_M1, /* 02 SUS_STAT_B */ - Native_M1, /* 03 PMU_SLP_S0IX_B */ - Native_M1, /* 04 PMU_AC_PRESENT */ - Native_M1, /* 05 PMU_PLTRST_B */ - Native_M1, /* 06 PMU_SUSCLK */ - GPIO_NC, /* 07 PMU_SLP_LAN_B */ - Native_M1, /* 08 PMU_PWRBTN_B */ - Native_M1, /* 09 PMU_SLP_S4_B */ - NATIVE_FUNC(M1, P_1K_H, NA), /* 10 PMU_WAKE_B */ - GPIO_NC, /* 11 PMU_WAKE_LAN_B */ - GPIO_NC, /* 15 MF_GPIO_3 */ - GPIO_NC, /* 16 MF_GPIO_7 */ - GPIO_NC, /* 17 MF_I2C1_SCL */ - GPIO_NC, /* 18 MF_GPIO_1 */ - GPIO_NC, /* 19 MF_GPIO_5 */ - GPIO_NC, /* 20 MF_GPIO_9 */ - GPIO_NC, /* 21 MF_GPIO_0 */ - GPIO_NC, /* 22 MF_GPIO_4 */ - GPIO_NC, /* 23 MF_GPIO_8 */ - GPIO_NC, /* 24 MF_GPIO_2 */ - GPIO_NC, /* 25 MF_GPIO_6 */ - GPIO_NC, /* 26 MF_I2C1_SDA */ - GPIO_END -}; - - -static struct soc_gpio_config gpio_config = { - /* BSW */ - .north = gpn_gpio_map, - .southeast = gpse_gpio_map, - .southwest = gpsw_gpio_map, - .east = gpe_gpio_map -}; - -struct soc_gpio_config *get_override_gpios_dvt(void) -{ - return &gpio_config; - -} diff --git a/src/mainboard/intel/strago/onboard.h b/src/mainboard/intel/strago/onboard.h index 89c9b69..4527365 100755 --- a/src/mainboard/intel/strago/onboard.h +++ b/src/mainboard/intel/strago/onboard.h @@ -37,8 +37,7 @@ /* ToDo: change kbd irq to gpio bank index */ #define BOARD_I8042_IRQ 182 -#define BOARD_TOUCH_IRQ 156 -#define BOARD_DVT_TOUCH_IRQ 184 +#define BOARD_TOUCH_IRQ 184 /* Audio: Gpio index in SW bank */ @@ -68,10 +67,6 @@ #define AUDIO_CODEC_DDN "RTEK Codec Controller " #define AUDIO_CODEC_I2C_ADDR 0x1A -#define BOARD_EVT 0x02 -#define BOARD_DVT 0x03 -#define BOARD_BCRD2 0x04 - #define BCRD2_PMIC_I2C_BUS 0x01 #endif diff --git a/src/mainboard/intel/strago/ramstage.c b/src/mainboard/intel/strago/ramstage.c index c5cff68..a05cd90 100644 --- a/src/mainboard/intel/strago/ramstage.c +++ b/src/mainboard/intel/strago/ramstage.c @@ -19,8 +19,6 @@ void mainboard_silicon_init_params(SILICON_INIT_UPD *params) { - if (board_id() == BOARD_BCRD2) { - params->ChvSvidConfig = SVID_PMIC_CONFIG; - params->PMIC_I2CBus = BCRD2_PMIC_I2C_BUS; - } + params->ChvSvidConfig = SVID_PMIC_CONFIG; + params->PMIC_I2CBus = BCRD2_PMIC_I2C_BUS; } diff --git a/src/mainboard/intel/strago/smihandler.c b/src/mainboard/intel/strago/smihandler.c index b465e3a..0f77bf3 100755 --- a/src/mainboard/intel/strago/smihandler.c +++ b/src/mainboard/intel/strago/smihandler.c @@ -139,11 +139,9 @@ void mainboard_smi_sleep(uint8_t slp_typ) while (google_chromeec_get_event() != 0) ; - if (smm_get_gnvs()->bdid == BOARD_DVT) { - /* Set LPC lines to low power in S3/S5. */ - if ((slp_typ == SLEEP_STATE_S3) || (slp_typ == SLEEP_STATE_S5)) - lpc_set_low_power(); - } + /* Set LPC lines to low power in S3/S5. */ + if ((slp_typ == SLEEP_STATE_S3) || (slp_typ == SLEEP_STATE_S5)) + lpc_set_low_power(); #endif }

1 0

New patch to review for coreboot: mb/gigabyte/ga-g41m-es2l: Remove PMBASE settings and commented code.
by Damien Zammit 25 Jan '16

25 Jan '16

Damien Zammit (damien(a)zamaudio.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13466 -gerrit commit d4322abf236d1e955e969f1e3d2cf8ac8c95ca25 Author: Damien Zammit <damien(a)zamaudio.com> Date: Tue Jan 26 17:24:48 2016 +1100 mb/gigabyte/ga-g41m-es2l: Remove PMBASE settings and commented code. Change-Id: Ifbb73753d5a0737418b869085f2329a02504e5dc Signed-off-by: Damien Zammit <damien(a)zamaudio.com> --- src/mainboard/gigabyte/ga-g41m-es2l/romstage.c | 19 ++----------------- 1 file changed, 2 insertions(+), 17 deletions(-) diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c b/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c index ca8ca5c..bff481f 100644 --- a/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c +++ b/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c @@ -58,21 +58,6 @@ static void mb_gpio_init(void) outl(0x000000f0, DEFAULT_GPIOBASE + 0x34); outl(0x00000083, DEFAULT_GPIOBASE + 0x38); - /* Set default power management registers */ - pci_write_config32(dev, PMBASE, DEFAULT_PMBASE | 1); - outw(0x0011, DEFAULT_PMBASE + 0x00); - outw(0x0120, DEFAULT_PMBASE + 0x02); - outl(0x00001c01, DEFAULT_PMBASE + 0x04); - outl(0x00bb29d2, DEFAULT_PMBASE + 0x08); - outl(0x000000a0, DEFAULT_PMBASE + 0x10); - outl(0xc5000000, DEFAULT_PMBASE + 0x28); - outl(0x00000040, DEFAULT_PMBASE + 0x2c); - outw(0x13e0, DEFAULT_PMBASE + 0x44); - outw(0x003f, DEFAULT_PMBASE + 0x60); - outw(0x0800, DEFAULT_PMBASE + 0x68); - outw(0x0008, DEFAULT_PMBASE + 0x6a); - outw(0x003f, DEFAULT_PMBASE + 0x72); - /* Set default GPIOs on superio */ ite_reg_write(GPIO_DEV, 0x25, 0x00); ite_reg_write(GPIO_DEV, 0x26, 0xc7); @@ -137,8 +122,8 @@ void main(unsigned long bist) // ch0 ch1 const u8 spd_addrmap[4] = { 0x50, 0, 0x52, 0 }; - /* Disable watchdog timer and route port 80 to LPC */ - RCBA32(0x3410) = (RCBA32(0x3410) | 0x20);// & ~0x4; + /* Disable watchdog timer */ + RCBA32(0x3410) = RCBA32(0x3410) | 0x20; /* Set southbridge and Super I/O GPIOs. */ mb_gpio_init();

1 0

New patch to review for coreboot: mb/gigabyte/ga-g41m-es2l: Remove copy-pasted cstates
by Damien Zammit 25 Jan '16

25 Jan '16

Damien Zammit (damien(a)zamaudio.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13465 -gerrit commit bfd6f2e7820f7ca09f4771e1b49130eb4beb976c Author: Damien Zammit <damien(a)zamaudio.com> Date: Tue Jan 26 17:17:27 2016 +1100 mb/gigabyte/ga-g41m-es2l: Remove copy-pasted cstates Change-Id: I5b6edbd97d4e6ed8b03f2f319a338022647e26ea Signed-off-by: Damien Zammit <damien(a)zamaudio.com> --- src/mainboard/gigabyte/ga-g41m-es2l/cstates.c | 13 +------------ src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb | 3 --- 2 files changed, 1 insertion(+), 15 deletions(-) diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/cstates.c b/src/mainboard/gigabyte/ga-g41m-es2l/cstates.c index dbac2ed..4d9f4ab 100644 --- a/src/mainboard/gigabyte/ga-g41m-es2l/cstates.c +++ b/src/mainboard/gigabyte/ga-g41m-es2l/cstates.c @@ -17,18 +17,7 @@ #include <device/device.h> #include <southbridge/intel/i82801gx/i82801gx.h> -static acpi_cstate_t cst_entries[] = { - { - /* acpi C1 / cpu C1 */ - 1, 0x01, 1000, - { ACPI_ADDRESS_SPACE_FIXED, 1, 2, { 1 }, 0, 0 } - }, - { - /* acpi C2 / cpu C2 */ - 2, 0x01, 500, - { ACPI_ADDRESS_SPACE_FIXED, 1, 2, { 1 }, 0x10, 0 } - }, -}; +static acpi_cstate_t cst_entries[] = {}; int get_cst_entries(acpi_cstate_t **entries) { diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb b/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb index e6b691c..3965538 100644 --- a/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb +++ b/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb @@ -21,9 +21,6 @@ chip northbridge/intel/x4x # Northbridge end chip cpu/intel/model_1067x # CPU device lapic 0xACAC off end - register "slfm" = "1" - register "c5" = "1" - register "c6" = "1" end end device domain 0 on # PCI domain

1 0

Patch set updated for coreboot: nb/intel/x4x: Move to early cbmem
by Damien Zammit 25 Jan '16

25 Jan '16

Damien Zammit (damien(a)zamaudio.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13131 -gerrit commit bc44036d137e000b2214b7a3f81e5b522036ec79 Author: Damien Zammit <damien(a)zamaudio.com> Date: Fri Jan 22 22:12:30 2016 +1100 nb/intel/x4x: Move to early cbmem Previously with errors in the ram init, early cbmem was disabled. Now that the ram is working correctly, set as early cbmem platform and update all (1) boards to use it. Tested on GA-G41M-ES2L Change-Id: I5925c28821537f0e326b4f5a2ac39778e4724a3c Signed-off-by: Damien Zammit <damien(a)zamaudio.com> --- src/mainboard/gigabyte/ga-g41m-es2l/romstage.c | 1 + src/northbridge/intel/x4x/Kconfig | 2 +- src/northbridge/intel/x4x/northbridge.c | 3 --- src/northbridge/intel/x4x/ram_calc.c | 7 +++++++ 4 files changed, 9 insertions(+), 4 deletions(-) diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c b/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c index 6bae128..ca8ca5c 100644 --- a/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c +++ b/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c @@ -159,5 +159,6 @@ void main(unsigned long bist) printk(BIOS_DEBUG, "Initializing memory\n"); sdram_initialize(0, spd_addrmap); quick_ram_check(); + cbmem_initialize_empty(); printk(BIOS_DEBUG, "Memory initialized\n"); } diff --git a/src/northbridge/intel/x4x/Kconfig b/src/northbridge/intel/x4x/Kconfig index c330fd5..f643bb2 100644 --- a/src/northbridge/intel/x4x/Kconfig +++ b/src/northbridge/intel/x4x/Kconfig @@ -26,7 +26,7 @@ config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy select MMCONF_SUPPORT_DEFAULT select VGA select INTEL_GMA_ACPI - select LATE_CBMEM_INIT + select EARLY_CBMEM_INIT config BOOTBLOCK_NORTHBRIDGE_INIT string diff --git a/src/northbridge/intel/x4x/northbridge.c b/src/northbridge/intel/x4x/northbridge.c index 3befc8c..19c12f5 100644 --- a/src/northbridge/intel/x4x/northbridge.c +++ b/src/northbridge/intel/x4x/northbridge.c @@ -28,7 +28,6 @@ #include <arch/acpi.h> #include <northbridge/intel/x4x/chip.h> #include <northbridge/intel/x4x/x4x.h> -#include <cbmem.h> static void mch_domain_read_resources(device_t dev) { @@ -109,8 +108,6 @@ static void mch_domain_read_resources(device_t dev) fixed_mem_resource(dev, index++, pcie_config_base >> 10, pcie_config_size >> 10, IORESOURCE_RESERVE); } - - set_top_of_ram(usable_tomk * 1024); } static void mch_domain_set_resources(device_t dev) diff --git a/src/northbridge/intel/x4x/ram_calc.c b/src/northbridge/intel/x4x/ram_calc.c index f11b19a..27562ea 100644 --- a/src/northbridge/intel/x4x/ram_calc.c +++ b/src/northbridge/intel/x4x/ram_calc.c @@ -17,6 +17,7 @@ #define __SIMPLE_DEVICE__ +#include <cbmem.h> #include <commonlib/helpers.h> #include <stdint.h> #include <arch/io.h> @@ -86,3 +87,9 @@ u8 decode_pciebar(u32 *const base, u32 *const len) *len = max_buses << 20; return 1; } + +void *cbmem_top(void) +{ + u32 ramtop = pci_read_config32(PCI_DEV(0,0,0), D0F0_TSEG); + return (void*)(ramtop); +}

1 0

Patch set updated for coreboot: nb/intel/x4x: Cleanup gma.c
by Damien Zammit 25 Jan '16

25 Jan '16

Damien Zammit (damien(a)zamaudio.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13128 -gerrit commit ef705efdb4a1b75452e67b7a0385219a8141e9bf Author: Damien Zammit <damien(a)zamaudio.com> Date: Fri Jan 22 19:13:18 2016 +1100 nb/intel/x4x: Cleanup gma.c Tidy up the code and move vga_textmode_init() later Change-Id: I49967e7197416c955ae6c8775eac7d1a60c92d1c Signed-off-by: Damien Zammit <damien(a)zamaudio.com> --- src/northbridge/intel/x4x/gma.c | 81 ++++++++++++----------------------------- 1 file changed, 24 insertions(+), 57 deletions(-) diff --git a/src/northbridge/intel/x4x/gma.c b/src/northbridge/intel/x4x/gma.c index 7891229..2679026 100644 --- a/src/northbridge/intel/x4x/gma.c +++ b/src/northbridge/intel/x4x/gma.c @@ -35,27 +35,14 @@ #include <pc80/vga.h> #include <pc80/vga_io.h> -static struct resource *gtt_res = NULL; - -void gtt_write(u32 reg, u32 data) -{ - write32(res2mmio(gtt_res, reg, 0), data); -} - static void intel_gma_init(const struct northbridge_intel_x4x_config *info, - u8 *mmio, u32 physbase, u16 piobase, u32 lfb) + u8 *mmio) { int i; u32 hactive, vactive; - vga_gr_write(0x18, 0); - /* Setup GTT. */ - for (i = 0; i < 0x2000; i++) - { - outl((i << 2) | 1, piobase); - outl(physbase + (i << 12) + 1, piobase + 4); - } + vga_gr_write(0x18, 0); write32(mmio + VGA0, 0x31108); write32(mmio + VGA1, 0x31406); @@ -92,8 +79,6 @@ static void intel_gma_init(const struct northbridge_intel_x4x_config *info, hactive = 640; vactive = 400; - vga_textmode_init(); - mdelay(1); write32(mmio + FP0(0), 0x31108); write32(mmio + DPLL(0), @@ -152,7 +137,8 @@ static void intel_gma_init(const struct northbridge_intel_x4x_config *info, write32(mmio + 0x000f000c, 0x00002050); write32(mmio + 0x00060100, 0x00044000); mdelay(1); - write32(mmio + PIPECONF(0), PIPECONF_ENABLE | PIPECONF_BPP_6 | PIPECONF_DITHER_EN); + write32(mmio + PIPECONF(0), PIPECONF_ENABLE + | PIPECONF_BPP_6 | PIPECONF_DITHER_EN); write32(mmio + VGACNTRL, 0x0); write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE | DISPPLANE_BGRX888); @@ -168,7 +154,7 @@ static void intel_gma_init(const struct northbridge_intel_x4x_config *info, | ADPA_DPMS_ON ); - write32(mmio + PP_CONTROL, PANEL_POWER_ON); + vga_textmode_init(); /* Enable screen memory. */ vga_sr_write(1, vga_sr_read(1) & ~0x20); @@ -178,6 +164,22 @@ static void intel_gma_init(const struct northbridge_intel_x4x_config *info, write32(mmio + SDEIIR, 0xffffffff); } +static void native_init(struct device *dev) +{ + struct resource *gtt_res = find_resource(dev, PCI_BASE_ADDRESS_0); + struct northbridge_intel_x4x_config *conf = dev->chip_info; + + if (gtt_res && gtt_res->base) { + printk(BIOS_SPEW, + "Initializing VGA without OPROM. MMIO 0x%llx\n", + gtt_res->base); + intel_gma_init(conf, res2mmio(gtt_res, 0, 0)); + } + + /* Linux relies on VBT for panel info. */ + generate_fake_intel_oprom(&conf->gfx, dev, "$VBT EAGLELAKE "); +} + static void gma_func0_init(struct device *dev) { u32 reg32; @@ -187,43 +189,10 @@ static void gma_func0_init(struct device *dev) reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO; pci_write_config32(dev, PCI_COMMAND, reg32); - /* Init graphics power management */ - gtt_res = find_resource(dev, PCI_BASE_ADDRESS_0); - - struct northbridge_intel_x4x_config *conf = dev->chip_info; - - if (!IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT)) { - /* PCI Init, will run VBIOS */ - pci_dev_init(dev); - } else { - u32 physbase; - struct resource *lfb_res; - struct resource *pio_res; - - lfb_res = find_resource(dev, PCI_BASE_ADDRESS_2); - pio_res = find_resource(dev, PCI_BASE_ADDRESS_4); - - physbase = pci_read_config32(dev, 0x5c) & ~0xf; - - if (gtt_res && gtt_res->base && physbase && pio_res && pio_res->base - && lfb_res && lfb_res->base) { - printk(BIOS_SPEW, "Initializing VGA without OPROM. MMIO 0x%llx\n", - gtt_res->base); - intel_gma_init(conf, res2mmio(gtt_res, 0, 0), physbase, - pio_res->base, lfb_res->base); - } - - /* Linux relies on VBT for panel info. */ - generate_fake_intel_oprom(&conf->gfx, dev, "$VBT EAGLELAKE "); - } - - /* Post VBIOS init */ - /* Enable Backlight */ - gtt_write(BLC_PWM_CTL2, (1 << 31)); - if (conf->gfx.backlight == 0) - gtt_write(BLC_PWM_CTL, 0x06100610); + if (IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT)) + native_init(dev); else - gtt_write(BLC_PWM_CTL, conf->gfx.backlight); + pci_dev_init(dev); } static void gma_set_subsystem(device_t dev, unsigned vendor, unsigned device) @@ -269,8 +238,6 @@ static struct device_operations gma_func0_ops = { .enable_resources = pci_dev_enable_resources, .acpi_fill_ssdt_generator = gma_ssdt, .init = gma_func0_init, - .scan_bus = 0, - .enable = 0, .ops_pci = &gma_pci_ops, };

1 0

Patch set updated for coreboot: mb/gigabyte/ga-g41m-es2l: Move MMCONF base address to 0xe0000000
by Damien Zammit 25 Jan '16

25 Jan '16

Damien Zammit (damien(a)zamaudio.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13129 -gerrit commit 6951e41ba9aff6f9cfe223105df749d0ef9c1d7c Author: Damien Zammit <damien(a)zamaudio.com> Date: Tue Jan 26 17:15:55 2016 +1100 mb/gigabyte/ga-g41m-es2l: Move MMCONF base address to 0xe0000000 Change-Id: I3873d92069cc1d113a8092d609d1768ff45cbd45 Signed-off-by: Damien Zammit <damien(a)zamaudio.com> --- src/mainboard/gigabyte/ga-g41m-es2l/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/Kconfig b/src/mainboard/gigabyte/ga-g41m-es2l/Kconfig index 1892b37..1234569 100644 --- a/src/mainboard/gigabyte/ga-g41m-es2l/Kconfig +++ b/src/mainboard/gigabyte/ga-g41m-es2l/Kconfig @@ -30,7 +30,7 @@ config BOARD_SPECIFIC_OPTIONS config MMCONF_BASE_ADDRESS hex - default 0xc0000000 + default 0xe0000000 config MAINBOARD_DIR string

1 0

Patch set updated for coreboot: nb/intel/x4x: Tidy up raminit and fix msbpos() function
by Damien Zammit 25 Jan '16

25 Jan '16

Damien Zammit (damien(a)zamaudio.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13127 -gerrit commit c97ce316dc9f3b0b4728cc7d59af781aeff723dd Author: Damien Zammit <damien(a)zamaudio.com> Date: Fri Jan 22 19:11:44 2016 +1100 nb/intel/x4x: Tidy up raminit and fix msbpos() function - Fix bug with msbpos, it was not returning the correct result due to typo in logic, and unsigned value needed to be negative. - Add reclaim above 4GiB - Fix to ME related registers near the end of raminit Change-Id: I04acd0593a457437ee4a42e14b287b2b17a160af Signed-off-by: Damien Zammit <damien(a)zamaudio.com> --- src/northbridge/intel/x4x/raminit_ddr2.c | 49 ++++++++++++++++++++++++++------ 1 file changed, 41 insertions(+), 8 deletions(-) diff --git a/src/northbridge/intel/x4x/raminit_ddr2.c b/src/northbridge/intel/x4x/raminit_ddr2.c index 02606c6..5dd5170 100644 --- a/src/northbridge/intel/x4x/raminit_ddr2.c +++ b/src/northbridge/intel/x4x/raminit_ddr2.c @@ -47,12 +47,14 @@ static u32 ddr2mhz(u32 speed) static u8 msbpos(u8 val) //Reverse { - u8 i; - for (i = 7; i >= 0; i--) { - if ((val & (1 << i)) == 0) - break; - } - return i; + u8 pos; + + asm ("bsrl %1, %0" + :"=r"(pos) + :"r"(val) + ); + + return pos; } static void sdram_detect_smallest_params2(struct sysinfo *s) @@ -1613,7 +1615,9 @@ static void dradrb_ddr2(struct sysinfo *s) static void mmap_ddr2(struct sysinfo *s) { - u32 gfxsize, gttsize, tsegsize, mmiosize, tom, tolud, touud, gfxbase, gttbase, tsegbase; + bool reclaim; + u32 gfxsize, gttsize, tsegsize, mmiosize, tom, tolud, touud; + u32 gfxbase, gttbase, tsegbase, reclaimbase, reclaimlimit; u16 ggc; u16 mesize; u16 ggc2uma[] = { 0, 0, 0, 0, 0, 32, 48, 64, 128, 256, 96, 160, 224, 352 }; @@ -1627,13 +1631,34 @@ static void mmap_ddr2(struct sysinfo *s) mesize = ME_UMA_SIZE; tom = s->channel_capacity[0] + s->channel_capacity[1] - mesize; tolud = MIN(0x1000 - mmiosize, tom); + + reclaim = false; + if ((tom - tolud) > 0x40) + reclaim = true; + + if (reclaim) { + tolud = tolud & ~0x3f; + tom = tom & ~0x3f; + reclaimbase = MAX(0x1000, tom); + reclaimlimit = reclaimbase + (MIN(0x1000, tom) - tolud) - 0x40; + } + touud = tom; + if (reclaim) + touud = reclaimlimit + 0x40; + gfxbase = tolud - gfxsize; gttbase = gfxbase - gttsize; tsegbase = gttbase - tsegsize; pci_write_config16(PCI_DEV(0,0,0), 0xb0, tolud << 4); pci_write_config16(PCI_DEV(0,0,0), 0xa0, tom >> 6); + if (reclaim) { + pci_write_config16(PCI_DEV(0,0,0), 0x98, + (u16)(reclaimbase >> 6)); + pci_write_config16(PCI_DEV(0,0,0), 0x9a, + (u16)(reclaimlimit >> 6)); + } pci_write_config16(PCI_DEV(0,0,0), 0xa2, touud); pci_write_config32(PCI_DEV(0,0,0), 0xa4, gfxbase << 20); pci_write_config32(PCI_DEV(0,0,0), 0xa8, gttbase << 20); @@ -1994,7 +2019,15 @@ void raminit_ddr2(struct sysinfo *s) printk(BIOS_DEBUG, "Done power settings\n"); // ME related - //MCHBAR32(0xa30) = MCHBAR32(0xa30) | (1 << 26); + if (RANK_IS_POPULATED(s->dimms, 0, 0) + || RANK_IS_POPULATED(s->dimms, 1, 0)) { + MCHBAR8(0xa2f) = MCHBAR8(0xa2f) | (1 << 0); + } + if (RANK_IS_POPULATED(s->dimms, 0, 1) + || RANK_IS_POPULATED(s->dimms, 1, 1)) { + MCHBAR8(0xa2f) = MCHBAR8(0xa2f) | (1 << 1); + } + MCHBAR32(0xa30) = MCHBAR32(0xa30) | (1 << 26); printk(BIOS_DEBUG, "Done ddr2\n"); }

1 0

Patch set updated for coreboot: Strago: Enable CA Mirror
by Hannah Williams 25 Jan '16

25 Jan '16

Hannah Williams (hannah.williams(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12749 -gerrit commit 778df3585555a3ac0534730ab757ade33f759506 Author: Shobhit Srivastava <shobhit.srivastava(a)intel.com> Date: Fri Oct 9 17:05:16 2015 +0530 Strago: Enable CA Mirror Configuring UPD PcdCaMirrorEn. This is a board specific parameter. CA mirror is the Command Address mirroring option that is enabled on this board CQ-DEPEND=CL:13038 Original-Reviewed-on: https://chromium-review.googlesource.com/309190 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Tested-by: Hannah Williams <hannah.williams(a)intel.com> Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Change-Id: I05174e18d650332d838e5036c713e91c4840ee75 Signed-off-by: Divya Sasidharan <divya.s.sasidharan(a)intel.com> Signed-off-by: Hannah Williams <hannah.williams(a)intel.com> --- src/mainboard/intel/strago/devicetree.cb | 1 + src/soc/intel/braswell/chip.h | 1 + src/soc/intel/braswell/romstage/romstage.c | 1 + 3 files changed, 3 insertions(+) diff --git a/src/mainboard/intel/strago/devicetree.cb b/src/mainboard/intel/strago/devicetree.cb index 788153a..1183579 100755 --- a/src/mainboard/intel/strago/devicetree.cb +++ b/src/mainboard/intel/strago/devicetree.cb @@ -13,6 +13,7 @@ chip soc/intel/braswell register "PcdApertureSize" = "2" register "PcdGttSize" = "1" register "PcdDvfsEnable" = "0" + register "PcdCaMirrorEn" = "1" ############################################################ # Set the parameters for SiliconInit diff --git a/src/soc/intel/braswell/chip.h b/src/soc/intel/braswell/chip.h index 0f3c1d0..11c14b1 100644 --- a/src/soc/intel/braswell/chip.h +++ b/src/soc/intel/braswell/chip.h @@ -71,6 +71,7 @@ struct soc_intel_braswell_config { UINT8 PcdGttSize; UINT8 PcdLegacySegDecode; UINT8 PcdDvfsEnable; + UINT8 PcdCaMirrorEn; /* Command Address Mirroring Enabled */ /* * The following fields come from fsp_vpd.h .aka. VpdHeader.h. diff --git a/src/soc/intel/braswell/romstage/romstage.c b/src/soc/intel/braswell/romstage/romstage.c index 2581583..028469a 100644 --- a/src/soc/intel/braswell/romstage/romstage.c +++ b/src/soc/intel/braswell/romstage/romstage.c @@ -212,6 +212,7 @@ void soc_memory_init_params(struct romstage_params *params, upd->PcdGttSize = config->PcdGttSize; upd->PcdLegacySegDecode = config->PcdLegacySegDecode; upd->PcdDvfsEnable = config->PcdDvfsEnable; + upd->PcdCaMirrorEn = config->PcdCaMirrorEn; } void soc_display_memory_init_params(const MEMORY_INIT_UPD *old,

1 0

Patch set updated for coreboot: Strago: Disable SD Card Detect Simulation in FSP
by Hannah Williams 25 Jan '16

25 Jan '16

Hannah Williams (hannah.williams(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13035 -gerrit commit fd5f8c9bebdeaa0cb906f1fbe70351c4f9120026 Author: Hannah Williams <hannah.williams(a)intel.com> Date: Sun Jan 17 23:11:25 2016 -0800 Strago: Disable SD Card Detect Simulation in FSP CQ-DEPEND=CL:12742 Signed-off-by: Hannah Williams <hannah.williams(a)intel.com> Change-Id: I6c39ffebe407a4ef8555b2f050a96d33709dc624 --- src/mainboard/intel/strago/devicetree.cb | 1 + 1 file changed, 1 insertion(+) diff --git a/src/mainboard/intel/strago/devicetree.cb b/src/mainboard/intel/strago/devicetree.cb index 3b93f44..3ac70f0 100755 --- a/src/mainboard/intel/strago/devicetree.cb +++ b/src/mainboard/intel/strago/devicetree.cb @@ -70,6 +70,7 @@ chip soc/intel/braswell register "PMIC_I2CBus" = "0" register "ISPEnable" = "0" # Disable IUNIT register "ISPPciDevConfig" = "3" + register "PcdSdDetectChk" = "0" # Disable SD card detect # LPE audio codec settings register "lpe_codec_clk_src" = "LPE_CLK_SRC_XTAL" # 19.2MHz clock

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit January 2016