coreboot-gerrit January 2016

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Patch set updated for coreboot: drivers/intel: Add FSP 2.0 skeleton infrastructure
by Alexandru Gagniuc 26 Jan '16

26 Jan '16

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13328 -gerrit commit 06e0d8d99379cccfaed5567d69e5518689fcd90b Author: Andrey Petrov <andrey.petrov(a)intel.com> Date: Tue Oct 27 16:27:26 2015 -0700 drivers/intel: Add FSP 2.0 skeleton infrastructure Change-Id: If5bea40112ef40eb54aa37e2880fe70075f9e02b Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> --- src/drivers/intel/Kconfig | 1 + src/drivers/intel/Makefile.inc | 1 + src/drivers/intel/fsp2_0/Kconfig | 56 +++++++++++++++++++++++++++++++++++ src/drivers/intel/fsp2_0/Makefile.inc | 10 +++++++ 4 files changed, 68 insertions(+) diff --git a/src/drivers/intel/Kconfig b/src/drivers/intel/Kconfig index 19986f4..e5525d8 100644 --- a/src/drivers/intel/Kconfig +++ b/src/drivers/intel/Kconfig @@ -14,5 +14,6 @@ ## source src/drivers/intel/fsp1_1/Kconfig +source src/drivers/intel/fsp2_0/Kconfig source src/drivers/intel/gma/Kconfig source src/drivers/intel/i210/Kconfig diff --git a/src/drivers/intel/Makefile.inc b/src/drivers/intel/Makefile.inc index e54f07b..67c1163 100644 --- a/src/drivers/intel/Makefile.inc +++ b/src/drivers/intel/Makefile.inc @@ -2,4 +2,5 @@ subdirs-y += gma subdirs-$(CONFIG_GENERATE_SMBIOS_TABLES) += wifi subdirs-$(CONFIG_PLATFORM_USES_FSP1_0) += fsp1_0 subdirs-$(CONFIG_PLATFORM_USES_FSP1_1) += fsp1_1 +subdirs-$(CONFIG_PLATFORM_USES_FSP2_0) += fsp2_0 subdirs-$(CONFIG_DRIVER_INTEL_I210) += i210 diff --git a/src/drivers/intel/fsp2_0/Kconfig b/src/drivers/intel/fsp2_0/Kconfig new file mode 100644 index 0000000..a029965 --- /dev/null +++ b/src/drivers/intel/fsp2_0/Kconfig @@ -0,0 +1,56 @@ +config PLATFORM_USES_FSP2_0 + bool + help + Include FSP 2.0 wrappers and functionality + +if PLATFORM_USES_FSP2_0 + +comment "Intel FSP 2.0" + +config ADD_FSP_BINARIES + bool "Add Intel FSP 2.0 binaries to CBFS" + help + Add the FSP-M and FSP-S binaries to CBFS. Note that coreboot does not + use the FSP-T binary, so that will not be included. + +if ADD_FSP_BINARIES + +config FSP_M_FILE + string "Intel FSP-M (memory init) binary path and filename" + help + The path and filename of the Intel FSP-M binary for this platform. + +config FSP_S_FILE + string "Intel FSP-S (silicon init) binary path and filename" + help + The path and filename of the Intel FSP-S binary for this platform. + +endif # ADD_FSP_BINARIES + +# Cache As RAM region layout: +# +# +-------------+ DCACHE_RAM_BASE + DCACHE_RAM_SIZE [0xfef80000] +# | | +# | FSP-M | +# | code | +# | | +# +-------------+ FSP-M [0xfef30000] +# | romstage | +# | code | +# +-------------+ ROMSTAGE_CAR_ADDR [0xfef28000] +# | FIT TABLE | +# +-------------+ FIT_CAR_ADDR [0xfef27c00] +# | FSP-M | +# | stack/data | +# +-------------+ DCACHE_RAM_BASE + 0x4000 [0xfef04000] +# | Stack | +# | | | +# | v | +# +-------------+ +# | ^ | +# | | | +# | CAR Globals | +# +-------------+ DCACHE_RAM_BASE [0xfef00000] + + +endif # PLATFORM_USES_FSP2_0 diff --git a/src/drivers/intel/fsp2_0/Makefile.inc b/src/drivers/intel/fsp2_0/Makefile.inc new file mode 100644 index 0000000..c85b4bc --- /dev/null +++ b/src/drivers/intel/fsp2_0/Makefile.inc @@ -0,0 +1,10 @@ + +CPPFLAGS_common += -I$(src)/drivers/intel/fsp2_0/include + +cbfs-files-$(CONFIG_ADD_FSP_BINARIES) += blobs/fsp-m.bin +blobs/fsp-m.bin-file := $(call strip_quotes,$(CONFIG_FSP_M_FILE)) +blobs/fsp-m.bin-type := raw + +cbfs-files-$(CONFIG_ADD_FSP_BINARIES) += blobs/fsp-s.bin +blobs/fsp-s.bin-file := $(call strip_quotes,$(CONFIG_FSP_S_FILE)) +blobs/fsp-s.bin-type := raw

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Patch set updated for coreboot: drivers/intel/fsp2.0: Add semantic patch for FspUpdVpd.h header
by Alexandru Gagniuc 26 Jan '16

26 Jan '16

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13331 -gerrit commit 46deaabbcf03756783f8b444e67792172b9e7e1a Author: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> Date: Fri Oct 30 18:05:57 2015 -0700 drivers/intel/fsp2.0: Add semantic patch for FspUpdVpd.h header Previous FSP implementations in coreboot have included FspUpdVpd.h directly, along with with efi headers. Instead of taking that approach in FSP 2.0, we provide a semantic patch that, with minimal modifications, makes FspUpdVpd.h easier to include in coreboot, and eliminates reliance on external headers and definitions. Change-Id: I0c2a6f7baf6fb50ae22b64e08e653cfe1aefdaf9 Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> --- .../intel/fsp2_0/header_util/fspupdvpd.spatch | 147 +++++++++++++++++++++ .../intel/fsp2_0/header_util/fspupdvpd_sanitize.sh | 22 +++ 2 files changed, 169 insertions(+) diff --git a/src/drivers/intel/fsp2_0/header_util/fspupdvpd.spatch b/src/drivers/intel/fsp2_0/header_util/fspupdvpd.spatch new file mode 100644 index 0000000..8f41836 --- /dev/null +++ b/src/drivers/intel/fsp2_0/header_util/fspupdvpd.spatch @@ -0,0 +1,147 @@ +/* + * Semantic patch for fspupdvpd_sanitize.sh. Please call the script directly. + * + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * (Written by Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +@ kill_pragma_pack @ +@@ +- #pragma pack(...) + +/* + * Convert named typedef'd structs + */ +@ named_struct @ +identifier i; +type t; +@@ +typedef struct i { ... } t; + +/* Make typename usable as identifier */ +@ script:python named_struct_type @ +t << named_struct.t; +i; +@@ +coccinelle.i = t.rstrip('_t') + + +@ convert_named_struct_decls @ +type named_struct.t; +identifier named_struct_type.i; +identifier g; +@@ +- typedef struct g { ++ struct i { +... +} +- t +; + +/* Replace type with struct */ +@ named_typedef_to_struct @ +type named_struct.t; +identifier named_struct_type.i; +@@ +- t ++ struct i + + +/* + * Convert unnamed typedef'd structs + */ +@ unnamed_struct @ +type t; +@@ +typedef struct { ... } t; + +/* Make typename usable as identifier */ +@ script:python unnamed_struct_type @ +t << unnamed_struct.t; +i; +@@ +coccinelle.i = t.rstrip('_t') + +@ convert_unnamed_struct_decls @ +type unnamed_struct.t; +identifier unnamed_struct_type.i; +@@ +-typedef struct { ++struct i { + ... +} +- t +; + +/* Replace type with struct */ +@ unnamed_typedef_to_struct @ +type unnamed_struct.t; +identifier unnamed_struct_type.i; +@@ +-t ++struct i + +/* + * Pack _ALL_ structs + */ +@ pack_structs @ +identifier s; +@@ + +struct s { +... +} ++ __attribute__((packed)) +; + +/* + * BIGINT to stdint + */ +@ uint8_t @ +typedef UINT8; +typedef uint8_t; +@@ +- UINT8 ++ uint8_t + +@ uint16_t @ +typedef UINT16; +typedef uint16_t; +@@ +- UINT16 ++ uint16_t + +@ uint32_t @ +typedef UINT32; +typedef uint32_t; +@@ +- UINT32 ++ uint32_t + +@ uint64_t @ +typedef UINT64; +typedef uint64_t; +@@ +- UINT64 ++ uint64_t + +@ bool @ +typedef BOOLEAN; +typedef bool; +@@ +- BOOLEAN ++ bool + +@ wchar_t @ +typedef CHAR16; +typedef wchar_t; +@@ +- CHAR16 ++ wchar_t diff --git a/src/drivers/intel/fsp2_0/header_util/fspupdvpd_sanitize.sh b/src/drivers/intel/fsp2_0/header_util/fspupdvpd_sanitize.sh new file mode 100644 index 0000000..7c3195e --- /dev/null +++ b/src/drivers/intel/fsp2_0/header_util/fspupdvpd_sanitize.sh @@ -0,0 +1,22 @@ +# +# Convert the FspUpdVpd.h header file into a format usable by coreboot +# Usage: +# fspupdvpd_sanitize.sh <path/to/FspUpdVpd.h> +# +# This file is part of the coreboot project. +# +# Copyright (C) 2015 Intel Corp. +# (Written by Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> for Intel Corp.) +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. + +HOME=$(dirname "${BASH_SOURCE[0]}") +DEST=$HOME + +SPATCH=spatch + +$SPATCH -sp_file $HOME/fspupdvpd.spatch \ + -in_place $1

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Patch set updated for coreboot: drivers/intel/fsp2_0: Add functionality to decode FSP 2.0 headers
by Alexandru Gagniuc 26 Jan '16

26 Jan '16

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13330 -gerrit commit d3e6d3ff63ae1e9e62c6c19fe7b749745e9076e4 Author: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> Date: Thu Oct 29 16:48:54 2015 -0700 drivers/intel/fsp2_0: Add functionality to decode FSP 2.0 headers This adds the minimum code needed to interpret the information in FSP headers. Only the fields that are useful are being decoded. Change-Id: Iffbeed2db1b267fe08f7935b797d94469f65b48b Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> --- src/drivers/intel/fsp2_0/Makefile.inc | 2 + src/drivers/intel/fsp2_0/include/fsp/info_header.h | 40 +++++++++++++ src/drivers/intel/fsp2_0/util.c | 70 ++++++++++++++++++++++ 3 files changed, 112 insertions(+) diff --git a/src/drivers/intel/fsp2_0/Makefile.inc b/src/drivers/intel/fsp2_0/Makefile.inc index c85b4bc..b6cb7cd 100644 --- a/src/drivers/intel/fsp2_0/Makefile.inc +++ b/src/drivers/intel/fsp2_0/Makefile.inc @@ -1,4 +1,6 @@ +romstage-y += util.c + CPPFLAGS_common += -I$(src)/drivers/intel/fsp2_0/include cbfs-files-$(CONFIG_ADD_FSP_BINARIES) += blobs/fsp-m.bin diff --git a/src/drivers/intel/fsp2_0/include/fsp/info_header.h b/src/drivers/intel/fsp2_0/include/fsp/info_header.h new file mode 100644 index 0000000..1e88410 --- /dev/null +++ b/src/drivers/intel/fsp2_0/include/fsp/info_header.h @@ -0,0 +1,40 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * (Written by Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef _FSP2_0_INFO_HEADER_H_ +#define _FSP2_0_INFO_HEADER_H_ + +#include <stdint.h> +#include <stdlib.h> +#include <types.h> + +#define FSP_HDR_OFFSET 0x94 +#define FSP_HDR_LEN 0x48 +#define FSP_HDR_SIGNATURE "FSPH" + +struct fsp_header { + uint32_t fsp_revision; + size_t image_size; + uintptr_t image_base; + size_t cfg_region_offset; + size_t cfg_region_size; + size_t notify_phase_entry_offset; + size_t memory_init_entry_offset; + size_t silicon_init_entry_offset; + char image_id[9]; + uint8_t revision; +}; + +enum cb_err fsp_identify(struct fsp_header *hdr, const void *fsp_blob); +void fsp_print_header_info(const struct fsp_header *hdr); + +#endif /* _FSP2_0_INFO_HEADER_H_ */ diff --git a/src/drivers/intel/fsp2_0/util.c b/src/drivers/intel/fsp2_0/util.c new file mode 100644 index 0000000..4e1dbf3 --- /dev/null +++ b/src/drivers/intel/fsp2_0/util.c @@ -0,0 +1,70 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * (Written by Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include <arch/io.h> +#include <console/console.h> +#include <fsp/info_header.h> +#include <lib.h> +#include <string.h> + +static bool looks_like_fsp_header(const uint8_t *raw_hdr) +{ + if (memcmp(raw_hdr, FSP_HDR_SIGNATURE, 4)) { + printk(BIOS_ALERT, "Did not find a valid FSP signature\n"); + return false; + } + + if (read32(raw_hdr + 4) != FSP_HDR_LEN) { + printk(BIOS_ALERT, "FSP header has invalid length\n"); + return false; + } + + return true; +} + +enum cb_err fsp_identify(struct fsp_header *hdr, const void *fsp_blob) +{ + const uint8_t *raw_hdr = fsp_blob; + raw_hdr += FSP_HDR_OFFSET; + + if (!looks_like_fsp_header(raw_hdr)) + return CB_ERR; + + hdr->revision = read8(raw_hdr + 0x0b); + hdr->fsp_revision = read32(raw_hdr + 0x0c); + memcpy(hdr->image_id, raw_hdr + 0x10, 8); + hdr->image_id[8] = '\0'; + hdr->image_size = read32(raw_hdr + 0x18); + hdr->image_base = read32(raw_hdr + 0x1c); + hdr->cfg_region_offset = read32(raw_hdr + 0x24); + hdr->cfg_region_size = read32(raw_hdr + 0x28); + hdr->notify_phase_entry_offset = read32(raw_hdr + 0x38); + hdr->memory_init_entry_offset = read32(raw_hdr + 0x3c); + hdr->silicon_init_entry_offset = read32(raw_hdr + 0x44); + + return CB_SUCCESS; +} + +void fsp_print_header_info(const struct fsp_header *hdr) +{ + printk(BIOS_DEBUG, "Revision %u, image ID: %s, base 0x%zx + 0x%zx\n", + hdr->revision ,hdr->image_id, hdr->image_base, hdr->image_size); + + printk(BIOS_DEBUG, "\tConfig region 0x%zx + 0x%zx\n", + hdr->cfg_region_offset, hdr->cfg_region_size); + printk(BIOS_DEBUG, "\tMemory init offset 0x%zx\n" + "\tSilicon init offset 0x%zx\n" + "\tNotify phase offset 0x%zx\n", + hdr->memory_init_entry_offset, + hdr->silicon_init_entry_offset, + hdr->notify_phase_entry_offset); +}

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Patch set updated for coreboot: soc/apollolake: Add enable bit for MCH BAR
by Alexandru Gagniuc 26 Jan '16

26 Jan '16

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13325 -gerrit commit a7982c87f7e124d3f4eb7f44228370557fc80fdb Author: Andrey Petrov <andrey.petrov(a)intel.com> Date: Wed Oct 28 17:29:42 2015 -0700 soc/apollolake: Add enable bit for MCH BAR Change-Id: Iac8f2f819126401f470caa688600824ccc2edad9 Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> --- src/soc/intel/apollolake/romstage/romstage.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/soc/intel/apollolake/romstage/romstage.c b/src/soc/intel/apollolake/romstage/romstage.c index 1bf94f4..2cbf4a9 100644 --- a/src/soc/intel/apollolake/romstage/romstage.c +++ b/src/soc/intel/apollolake/romstage/romstage.c @@ -31,8 +31,8 @@ static void soc_early_romstage_init(void) { device_t pmc = PCI_DEV(0, 13, 1); - /* Set MCH base address */ - pci_write_config32(PCI_DEV(0, 0, 0), 0x48, MCH_BASE_ADDR); + /* Set MCH base address and enable bit */ + pci_write_config32(PCI_DEV(0, 0, 0), 0x48, MCH_BASE_ADDR | 1); /* Set PMC base address */ pci_write_config32(pmc, PCI_BASE_ADDRESS_0, PMC_BAR0);

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Patch set updated for coreboot: soc/apollolake: Only allow mmaped accesses to IFD BIOS region
by Alexandru Gagniuc 26 Jan '16

26 Jan '16

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13326 -gerrit commit 042c0da31046ca3acc287567d53b382e125b9952 Author: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> Date: Wed Oct 28 12:28:41 2015 -0700 soc/apollolake: Only allow mmaped accesses to IFD BIOS region Only the BIOS region is memory-mapped by the hardware. Anything below that is invisible via MMIO. Also, the 256 KiB right below 4G are being decoded by readonly SRAM. Fail accesses to those regions, rather than returning false data. Change-Id: I34779109ffce50a1c5a4842d7bf75870b8b4dff8 Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> --- src/soc/intel/apollolake/Kconfig | 2 +- src/soc/intel/apollolake/mmap_boot.c | 32 ++++++++++++++++++++------------ 2 files changed, 21 insertions(+), 13 deletions(-) diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index 4a4efa4..317a439 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -78,7 +78,7 @@ config IFD_BIOS_START The starting address of flash region 1 (BIOS), as declared in the firmware descriptor. This can be obtained via 'ifdtool -d'. -config IFD_BIOS_SIZE +config IFD_BIOS_END hex default ROM_SIZE help diff --git a/src/soc/intel/apollolake/mmap_boot.c b/src/soc/intel/apollolake/mmap_boot.c index 7e9080b..60f7c1a 100644 --- a/src/soc/intel/apollolake/mmap_boot.c +++ b/src/soc/intel/apollolake/mmap_boot.c @@ -3,6 +3,7 @@ * * Copyright (C) 2015 Intel Corp. * (Written by Andrey Petrov <andrey.petrov(a)intel.com> for Intel Corp.) + * (Written by Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> for Intel Corp.) * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -11,31 +12,38 @@ */ #include <boot_device.h> -#include <console/console.h> #include <cbfs.h> -#include <endian.h> -#include <stdlib.h> #include <commonlib/region.h> +#include <console/console.h> #include <fmap.h> +#include <stdlib.h> +#include <string.h> + +/* The 256 KiB right below 4G are decoded by readonly SRAM, not boot media */ +#define IFD_BIOS_MAX_MAPPED (CONFIG_IFD_BIOS_END - 256 * KiB) +#define IFD_MAPPED_SIZE (IFD_BIOS_MAX_MAPPED - CONFIG_IFD_BIOS_START) +#define IFD_BIOS_SIZE (CONFIG_IFD_BIOS_END - CONFIG_IFD_BIOS_START) /* * If Apollo Lake is configured to boot from SPI flash "BIOS" region * (as defined in descriptor) is mapped below 4GiB. Form a pointer for * the base. */ -#define ROM_BASE ((void *)(uintptr_t)(0x100000000ULL - CONFIG_IFD_BIOS_SIZE)) +#define VIRTUAL_ROM_BASE ((uintptr_t)(0x100000000ULL - IFD_BIOS_SIZE)) -static const struct mem_region_device boot_dev = { - .base = (void *) ROM_BASE, - /* typically not whole flash is memory mapped */ - .rdev = REGION_DEV_INIT(&mem_rdev_ops, CONFIG_IFD_BIOS_START, - CONFIG_IFD_BIOS_SIZE) -}; +static const struct mem_region_device shadow_dev = MEM_REGION_DEV_INIT( + VIRTUAL_ROM_BASE, IFD_BIOS_MAX_MAPPED +); + +static const struct xlate_region_device real_dev = XLATE_REGION_INIT( + &shadow_dev.rdev, CONFIG_IFD_BIOS_START, + IFD_MAPPED_SIZE, CONFIG_ROM_SIZE +); const struct region_device *boot_device_ro(void) { - return &boot_dev.rdev; -} + return &real_dev.rdev; +}; static int iafw_boot_region_properties(struct cbfs_props *props) {

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Patch set updated for coreboot: intel/apollolake_rvp: Update name of IFD_BIOS_START variable
by Alexandru Gagniuc 26 Jan '16

26 Jan '16

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13327 -gerrit commit 966ab9dac9ec343086963d215d7716140bd1e0c4 Author: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> Date: Wed Oct 28 12:38:48 2015 -0700 intel/apollolake_rvp: Update name of IFD_BIOS_START variable It was recently changed in soc/intel/apollolake. Change-Id: I5cd41154bf85700752977e37cc1824ec2651e5bb Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> --- src/mainboard/intel/apollolake_rvp/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/intel/apollolake_rvp/Kconfig b/src/mainboard/intel/apollolake_rvp/Kconfig index 492ccdc..5e6c4f0 100755 --- a/src/mainboard/intel/apollolake_rvp/Kconfig +++ b/src/mainboard/intel/apollolake_rvp/Kconfig @@ -17,7 +17,7 @@ config MAINBOARD_VENDOR string default "Intel" -config IFD_BIOS_SIZE +config IFD_BIOS_END hex default 0x700000

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Patch set updated for coreboot: soc/apollolake: Add BAR setup and enables essential for raminit
by Alexandru Gagniuc 26 Jan '16

26 Jan '16

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13324 -gerrit commit 479226c17026fb79893da9fc42040152e6dfc883 Author: Andrey Petrov <andrey.petrov(a)intel.com> Date: Mon Oct 26 18:10:04 2015 -0700 soc/apollolake: Add BAR setup and enables essential for raminit Change-Id: I884e677e607a14e9e88877a8e94e8518d473cf83 Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> --- src/soc/intel/apollolake/bootblock/bootblock_car.c | 7 ++-- src/soc/intel/apollolake/include/soc/iomap.h | 26 +++++++++++++++ src/soc/intel/apollolake/romstage/romstage.c | 37 ++++++++++++++++++++++ 3 files changed, 67 insertions(+), 3 deletions(-) diff --git a/src/soc/intel/apollolake/bootblock/bootblock_car.c b/src/soc/intel/apollolake/bootblock/bootblock_car.c index 7dd359b..8d317a1 100644 --- a/src/soc/intel/apollolake/bootblock/bootblock_car.c +++ b/src/soc/intel/apollolake/bootblock/bootblock_car.c @@ -16,6 +16,7 @@ #include <device/pci.h> #include <soc/bootblock.h> #include <soc/cpu.h> +#include <soc/iomap.h> #include <soc/uart.h> static void disable_watchdog(void) @@ -24,14 +25,14 @@ static void disable_watchdog(void) device_t dev = PCI_DEV(0, 0xd, 1); /* Open up an IO window */ - pci_write_config16(dev, PCI_BASE_ADDRESS_4, 0x400); + pci_write_config16(dev, PCI_BASE_ADDRESS_4, ACPI_PMIO_BASE); pci_write_config32(dev, PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_IO); /* We don't have documentation for this bit, but it prevents reboots */ - reg = inl(0x400 + 0x68); + reg = inl(ACPI_PMIO_BASE + 0x68); reg |= 1 << 11; - outl(reg, 0x400 + 0x68); + outl(reg, ACPI_PMIO_BASE + 0x68); } static void call_romstage(void *entry) diff --git a/src/soc/intel/apollolake/include/soc/iomap.h b/src/soc/intel/apollolake/include/soc/iomap.h new file mode 100644 index 0000000..09ae67d --- /dev/null +++ b/src/soc/intel/apollolake/include/soc/iomap.h @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * (Written by Andrey Petrov <andrey.petrov(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef _SOC_APOLLOLAKE_IOMAP_H_ +#define _SOC_APOLLOLAKE_IOMAP_H_ + +#define P2SB_BAR 0xd0000000 +#define MCH_BASE_ADDR 0xfed10000 + +#define ACPI_PMIO_BASE 0x400 +#define R_ACPI_PM1_TMR 0x8 + +/* Accesses to these BARs are hardcoded in FSP */ +#define PMC_BAR0 0xfe042000 +#define PMC_BAR1 0xfe044000 + +#endif /* _SOC_APOLLOLAKE_IOMAP_H_ */ diff --git a/src/soc/intel/apollolake/romstage/romstage.c b/src/soc/intel/apollolake/romstage/romstage.c index f76476b..1bf94f4 100644 --- a/src/soc/intel/apollolake/romstage/romstage.c +++ b/src/soc/intel/apollolake/romstage/romstage.c @@ -3,6 +3,7 @@ * * Copyright (C) 2015 Intel Corp. * (Written by Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> for Intel Corp.) + * (Written by Andrey Petrov <andrey.petrov(a)intel.com> for Intel Corp.) * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -10,10 +11,44 @@ * (at your option) any later version. */ +#include <arch/io.h> #include <console/console.h> +#include <cpu/x86/msr.h> +#include <device/pci_def.h> +#include <soc/iomap.h> #include <soc/romstage.h> #include <soc/uart.h> +/* + * Enables several BARs and devices which are needed for memory init + * - MCH_BASE_ADDR is needed in order to talk to the memory controller + * - PMC_BAR0 and PMC_BAR1 are used by FSP (with the base address hardcoded) + * Once raminit is done, we can safely let the allocator re-assign them + * - HPET is enabled because FSP wants to store a pointer to global data in the + * HPET comparator register + */ +static void soc_early_romstage_init(void) +{ + device_t pmc = PCI_DEV(0, 13, 1); + + /* Set MCH base address */ + pci_write_config32(PCI_DEV(0, 0, 0), 0x48, MCH_BASE_ADDR); + + /* Set PMC base address */ + pci_write_config32(pmc, PCI_BASE_ADDRESS_0, PMC_BAR0); + pci_write_config32(pmc, PCI_BASE_ADDRESS_1, 0); /* 64-bit BAR */ + pci_write_config32(pmc, PCI_BASE_ADDRESS_2, PMC_BAR1); + pci_write_config32(pmc, PCI_BASE_ADDRESS_3, 0); /* 64-bit BAR */ + + /* PMIO BAR4 was already set in bootblock, hence the COMMAND_IO below */ + pci_write_config32(pmc, PCI_COMMAND, + PCI_COMMAND_IO | PCI_COMMAND_MEMORY | + PCI_COMMAND_MASTER); + + /* Enable decoding for HPET */ + pci_write_config32(PCI_DEV(0, 13, 0), 0x60, 1<<7); +} + asmlinkage void romstage_entry(void) { /* Be careful. Bootblock might already have initialized the console */ @@ -24,6 +59,8 @@ asmlinkage void romstage_entry(void) printk(BIOS_DEBUG, "Starting romstage...\n"); + soc_early_romstage_init(); + /* This function must not return */ while(1) ;

1 0

Patch set updated for coreboot: cbfstool: Fix broken alignment because of flashmap
by Werner Zeh 26 Jan '16

26 Jan '16

Werner Zeh (werner.zeh(a)siemens.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13417 -gerrit commit 7468d7586efccfa8327f6dcae99a753d5c2071c2 Author: Werner Zeh <werner.zeh(a)siemens.com> Date: Mon Jan 25 12:47:20 2016 +0100 cbfstool: Fix broken alignment because of flashmap With the introduction of flashmap cbfs alignment of files gets broken because flashmap is located at the beginning of the flash and cbfstool didn't take care about that offset. This commit fixes the alignment in cbfs. Change-Id: Idebb86d4c691b49a351a402ef79c62d31622c773 Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> --- util/cbfstool/cbfs_image.c | 17 ++++++++++++++--- 1 file changed, 14 insertions(+), 3 deletions(-) diff --git a/util/cbfstool/cbfs_image.c b/util/cbfstool/cbfs_image.c index 2d7a6f0..95b2db7 100644 --- a/util/cbfstool/cbfs_image.c +++ b/util/cbfstool/cbfs_image.c @@ -2,6 +2,7 @@ * CBFS Image Manipulation * * Copyright (C) 2013 The Chromium OS Authors. All rights reserved. + * Copyright (C) 2016 Siemens AG. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -1410,6 +1411,16 @@ static int is_in_range(size_t start, size_t end, size_t metadata_size, return (offset >= start + metadata_size && offset + size <= end); } +static size_t absolute_align(const struct cbfs_image *image, size_t val, + size_t align) +{ + const size_t region_offset = buffer_offset(&image->buffer); + /* To perform alignment on absolute address, take the region offset */ + /* of the image into account. */ + return align_up(val + region_offset, align) - region_offset; + +} + int32_t cbfs_locate_entry(struct cbfs_image *image, size_t size, size_t page_size, size_t align, size_t metadata_size) { @@ -1474,7 +1485,7 @@ int32_t cbfs_locate_entry(struct cbfs_image *image, size_t size, if (addr_next - addr < need_len) continue; - offset = align_up(addr + metadata_size, align); + offset = absolute_align(image, addr + metadata_size, align); if (is_in_same_page(offset, size, page_size) && is_in_range(addr, addr_next, metadata_size, offset, size)) { DEBUG("cbfs_locate_entry: FIT (PAGE1)."); @@ -1482,7 +1493,7 @@ int32_t cbfs_locate_entry(struct cbfs_image *image, size_t size, } addr2 = align_up(addr, page_size); - offset = align_up(addr2, align); + offset = absolute_align(image, addr2, align); if (is_in_range(addr, addr_next, metadata_size, offset, size)) { DEBUG("cbfs_locate_entry: OVERLAP (PAGE2)."); return offset; @@ -1492,7 +1503,7 @@ int32_t cbfs_locate_entry(struct cbfs_image *image, size_t size, * definitely provide the space for header. */ assert(page_size >= metadata_size); addr3 = addr2 + page_size; - offset = align_up(addr3, align); + offset = absolute_align(image, addr3, align); if (is_in_range(addr, addr_next, metadata_size, offset, size)) { DEBUG("cbfs_locate_entry: OVERLAP+ (PAGE3)."); return offset;

1 0

Patch set updated for coreboot: drivers/intel/fsp2_0: Add initial FspUpdVpd.h header
by Alexandru Gagniuc 26 Jan '16

26 Jan '16

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13332 -gerrit commit 63dc0f404de6511abe352b0f7b5bd01d9b527471 Author: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> Date: Mon Nov 2 13:40:06 2015 -0800 drivers/intel/fsp2_0: Add initial FspUpdVpd.h header This is the header which defines the parameter interfaceof the FSP blob. Since thi is specific to the FSP blob, and is subject to change, it is added in a separate commit. Change-Id: I7b7bb77817ec0e757a569f90d0248d50df5e34c8 Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> --- src/drivers/intel/fsp2_0/include/fsp/FspUpdVpd.h | 447 +++++++++++++++++++++++ 1 file changed, 447 insertions(+) diff --git a/src/drivers/intel/fsp2_0/include/fsp/FspUpdVpd.h b/src/drivers/intel/fsp2_0/include/fsp/FspUpdVpd.h new file mode 100644 index 0000000..441e43a --- /dev/null +++ b/src/drivers/intel/fsp2_0/include/fsp/FspUpdVpd.h @@ -0,0 +1,447 @@ +/** @file + +Copyright (c) 2015, Intel Corporation. All rights reserved.<BR> + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +* Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. +* Redistributions in binary form must reproduce the above copyright notice, this + list of conditions and the following disclaimer in the documentation and/or + other materials provided with the distribution. +* Neither the name of Intel Corporation nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + THE POSSIBILITY OF SUCH DAMAGE. + + This file is automatically generated. Please do NOT modify !!! + +**/ + +#ifndef __FSPUPDVPD_H__ +#define __FSPUPDVPD_H__ + +#define MAX_CHANNELS_NUM 2 +#define MAX_DIMMS_NUM 2 + +struct DIMM_INFO { + uint8_t DimmId; + uint32_t SizeInMb; +} __attribute__((packed)); + +struct CHANNEL_INFO { + uint8_t ChannelId; + uint8_t DimmCount; + struct DIMM_INFO DimmInfo[MAX_DIMMS_NUM]; +} __attribute__((packed)); + +struct FSP_SMBIOS_MEMORY_INFO { + uint8_t Revision; + uint16_t DataWidth; + /** As defined in SMBIOS 3.0 spec + Section 7.18.2 and Table 75 + **/ + uint8_t MemoryType; + uint16_t MemoryFrequencyInMHz; + /** As defined in SMBIOS 3.0 spec + Section 7.17.3 and Table 72 + **/ + uint8_t ErrorCorrectionType; + uint8_t ChannelCount; + struct CHANNEL_INFO ChannelInfo[MAX_CHANNELS_NUM]; +} __attribute__((packed)); + +typedef union{ + uint32_t padCnf0; + struct { + uint32_t GPIOTxState:1; ///< 0 GPIO TX State + uint32_t GPIORxState:1; ///< 1 GPIO RX State, RO + uint32_t Reserved1:6; ///< 2-7 Reserved, RO + uint32_t GPIORxTxDis:2; ///< 8-9 GPIO RX Disable[9], GPIO TX Disable[8] + uint32_t PMode:3; ///< 10-12 Pad Mode, 0h = GPIO Controller controls the Pad; 1h = Native Function 1, if applicable, controls the pad; 2h = Native Function 2, if applicable, controls the pad, etc. + uint32_t Reserved2:4; ///< 13-16 Reserved, RO + uint32_t GPIRout:4; ///< 17-20 Route to IOxAPIC[20], SCI[19], SMI[18], NMI[17] + uint32_t RXTXEnCfg:2; ///< 21-22 RX/TX Enable Config (RXTXEnCfg) RO + uint32_t RXINV:1; ///< 23 RX Invert, 0 = No inversion; 1 = Inversion + uint32_t PreGfRXSel:1; ///< 24 Pre Glitch Filter Stage RX Pad State Select, RO, not support in BXT + uint32_t RxEvCfg:2; ///< 25-26 0h = Level 1h = Edge (RxInv=0 for rising edge; 1 for falling edge), 2h = Disabled ,3h = Either rising edge or falling edge + uint32_t Reserved3:1; ///< 27 RO + uint32_t RXRAW1:1; ///< 28 Override the RX to 1 + uint32_t RXPadStSel:1; ///< 29 RX Pad State Select + uint32_t PadRstCfg:2; ///< 30-31 Pad Reset Config + } r; +} BL_CONF_PAD0; + +typedef union{ + uint32_t padCnf1; + struct { + uint32_t IntSel:7; ///< 0-6 Interrupt Select. RO + uint32_t Reserved:1; ///< 7 Reserved. + uint32_t IOSTerm:2; ///< 8-9 I/O Standby Termination (IOSTerm) RW + uint32_t Term:4; ///< 10-13 Termination, + ///< 0 000: none;0 010: 5k wpd;0 100: 20k wpd;1 000: none;1 001: 1k wpu;1 011: 2k wpu;1 010: 5k wpu; + ///< 1 100: 20k wpu;1 101: 1k & 2k wpu;1 111: (optional) Native controller selected by Pad Mode controls the Termination + uint32_t IOSState:4; ///< 14-17 I/O Standby State, I/O Standby is not implemented in BXT, RW + uint32_t CFIOPadCfg:14; ///< 18-31 For BXT, this is done thru Family Register if necessary. RO + } r; +} BL_CONF_PAD1; + +struct BL_GPIO_PAD_INIT { + BL_CONF_PAD0 padConfg0; + BL_CONF_PAD1 padConfg1; + uint8_t Community; + uint16_t MMIO_ADDRESS; + bool HostSw; + bool WakeEnabled; ///< Wake enable for direct IRQ pin + wchar_t *pad_name; ///< GPIO Pin Name for debug purpose +} __attribute__((packed)); + + + +struct TEMP_RAM_INIT_UPD { +/** Offset 0x0020 +**/ + uint64_t Signature; +/** Offset 0x0028 +**/ + uint8_t Revision; +/** Offset 0x0029 +**/ + uint8_t UnusedUpdSpace0[83]; +/** Offset 0x007C +**/ + uint32_t ReservedTempRamInitUpd; +} __attribute__((packed)); + +struct MEMORY_INIT_UPD { +/** Offset 0x0080 +**/ + uint64_t Signature; +/** Offset 0x0088 +**/ + uint8_t Revision; +/** Offset 0x0089 +**/ + uint8_t UnusedUpdSpace1[7]; +/** Offset 0x0090 + Debug Serial Port Base + Debug serial port resource base address, either I/O or MMIO base. +**/ + uint32_t SerialDebugPortAddress; +/** Offset 0x0094 + Debug Serial Port Type + Debug serial port resource type. NONE means no serial port support. +**/ + uint8_t SerialDebugPortType; +/** Offset 0x0095 + Serial Port Debug Device + Select active serial port device. For SOC UART devices,'Debug Serial Port Base' options will be ignored. +**/ + uint8_t SerialDebugPortDevice; +/** Offset 0x0096 + Debug Serial Port Stride Size + Debug serial port register map stride size. +**/ + uint8_t SerialDebugPortStrideSize; +/** Offset 0x0097 +**/ + uint8_t ReservedUpd1; +/** Offset 0x0098 + Memory FastBootSupport + MRC Fast Boot Support +**/ + uint8_t MrcFastBoot; +/** Offset 0x0099 +**/ + uint8_t UnusedUpdSpace2[7]; +/** Offset 0x00A0 + Memory EccSupport + ECC Support +**/ + uint8_t EccSupport; +/** Offset 0x00A1 + Memory DdrFreqLimit + DDR Freq Limit +**/ + uint8_t DdrFreqLimit; +/** Offset 0x00A2 + Memory MaxTolud + MaxTolud +**/ + uint32_t MaxTolud; +/** Offset 0x00A6 + MrcDebugMsgLevel + Set MRC DebugMsg Level +**/ + uint8_t MrcDebugMsgLevel; +/** Offset 0x00A7 + Integrated Graphics Device + Enable : Enable Integrated Graphics Device (IGD) when selected as the Primary Video Adaptor. Disable: Alwarys disable IGD +**/ + uint8_t Igd; +/** Offset 0x00A8 + DVMT Pre-Allocated + Select DVMT 5.0 Pre-Allocated (Fixed) Graphics Memory size used by the Internal Graphics Device +**/ + uint8_t IgdDvmt50PreAlloc; +/** Offset 0x00A9 + Aperture Size + Select the Aperture Size. +**/ + uint8_t IgdApertureSize; +/** Offset 0x00AA + GTT Size + Select the GTT Size. +**/ + uint8_t GTTSize; +/** Offset 0x00AB + Primary Display + Select which of IGD/PCI Graphics device should be Primary Display. +**/ + uint8_t PrimaryVideoAdaptor; +/** Offset 0x00AC +**/ + uint8_t PmSupport; +/** Offset 0x00AD +**/ + uint8_t EnableRenderStandby; +/** Offset 0x00AE +**/ + uint8_t PavpEnable; +/** Offset 0x00AF +**/ + uint8_t SataEnable; +/** Offset 0x00B0 + Enable SATA + Enable/disable SATA controller. +**/ + uint8_t EnableSata; +/** Offset 0x00B1 + SATA Mode + Select SATA controller working mode. +**/ + uint8_t SataMode; +/** Offset 0x00B2 + Enable SATA + Enable/disable SATA controller. +**/ + uint8_t SataSalpSupport; +/** Offset 0x00B3 + Enable SATA ports + Enable/disable SATA ports. One byte for each port, byte0 for port0, byte1 for port1, and so on. +**/ + uint8_t SataPortsEnable[2]; +/** Offset 0x00B5 + Enable SATA DEVSLP Feature + Enable/disable SATA DEVSLP per port. 0 is disable, 1 is enable. One byte for each port, byte0 for port0, byte1 for port1, and so on. +**/ + uint8_t SataPortsDevSlp[2]; +/** Offset 0x00B7 + Enable PCIE RP + Enable/disable PCIE Root Ports. 0: disable, 1: enable. One byte for each port, byte0 for port1, byte1 for port2, and so on. +**/ + uint8_t PcieRpEnable[6]; +/** Offset 0x00BD + Configure CLKREQ Number + Configure Root Port CLKREQ Number if CLKREQ is supported. Each value in arrary can be between 0-6. One byte for each port, byte0 for port1, byte1 for port2, and so on. +**/ + uint8_t PcieRpClkReqNumber[6]; +/** Offset 0x00C3 + Enable USB2 ports + Enable/disable per USB2 ports. One byte for each port, byte0 for port0, byte1 for port1, and so on. +**/ + uint8_t PortUsb20Enable[8]; +/** Offset 0x00CB + Enable USB3 ports + Enable/disable per USB3 ports. One byte for each port, byte0 for port0, byte1 for port1, and so on. +**/ + uint8_t PortUsb30Enable[6]; +/** Offset 0x00D1 + Enable XHCI SSIC Eanble + Enable/disable XHCI SSIC port. +**/ + uint8_t SsicPortEnable; +/** Offset 0x00D2 + Enable SMBus + Enable/disable SMBus controller. +**/ + uint8_t SmbusEnable; +/** Offset 0x00D3 +**/ + uint8_t UnusedUpdSpace3[13]; +/** Offset 0x00E0 +**/ + uint8_t IspEn; +/** Offset 0x00E1 +**/ + uint8_t IspAcpiMode; +/** Offset 0x00E2 +**/ + uint32_t AdditionalFvBase; +/** Offset 0x00E6 +**/ + uint8_t UnusedUpdSpace4[122]; +/** Offset 0x0160 +**/ + uint32_t ObbLoadingBase; +/** Offset 0x0164 +**/ + uint32_t ObbFlashBase; +/** Offset 0x0168 +**/ + uint32_t ObbFlashSize; +/** Offset 0x016C +**/ + uint8_t UnusedUpdSpace5[20]; +/** Offset 0x0180 +**/ + uint8_t ObbFileName[16]; +/** Offset 0x0190 +**/ + uint8_t UnusedUpdSpace6[48]; +/** Offset 0x01C0 +**/ + struct BL_GPIO_PAD_INIT* GpioPadInitTablePtr; +/** Offset 0x01C4 +**/ + uint8_t UnusedUpdSpace7[56]; +/** Offset 0x01FC +**/ + uint32_t ReservedMemoryInitUpd; +} __attribute__((packed)); + +struct SILICON_INIT_UPD { +/** Offset 0x0200 +**/ + uint64_t Signature; +/** Offset 0x0208 +**/ + uint8_t Revision; +/** Offset 0x0209 +**/ + uint8_t UnusedUpdSpace8[7]; +/** Offset 0x0210 + Logo Pointer + Points to PEI Display Logo Image +**/ + uint32_t LogoPtr; +/** Offset 0x0214 + Logo Size + Size of PEI Display Logo Image +**/ + uint32_t LogoSize; +/** Offset 0x0218 + Graphics Configuration Ptr + Points to VBT +**/ + uint32_t GraphicsConfigPtr; +/** Offset 0x021C + Enable HD Audio DSP + Enable/disable HD Audio DSP feature. +**/ + uint8_t DspEnable; +/** Offset 0x021D + Select HDAudio IoBuffer Ownership + Select HDAudio IoBuffer Ownership. +**/ + uint8_t IoBufferOwnership; +/** Offset 0x021E + BXT PlatformType + BXT PlatformType. +**/ + uint8_t PlatformType; +/** Offset 0x021F + DynSR + Enable/disable DynSR feature. +**/ + uint8_t DynSR; +/** Offset 0x0220 +**/ + uint8_t UnusedUpdSpace9[20]; +/** Offset 0x0234 +**/ + uint8_t ReservedSiliconInitUpd[292]; +} __attribute__((packed)); + +#define FSP_UPD_SIGNATURE 0x2444505554584224 /* '$BXTUPD$' */ +#define FSP_TEMP_RAM_INIT_UPD_SIGNATURE 0x24445055504D5424 /* '$TMPUPD$' */ +#define FSP_MEMORY_INIT_UPD_SIGNATURE 0x244450554D454D24 /* '$MEMUPD$' */ +#define FSP_SILICON_INIT_UPD_SIGNATURE 0x244450555F495324 /* '$SI_UPD$' */ + +struct UPD_DATA_REGION { +/** Offset 0x0000 +**/ + uint64_t Signature; +/** Offset 0x0008 +**/ + uint8_t Revision; +/** Offset 0x0009 +**/ + uint8_t ReservedUpd0[7]; +/** Offset 0x0010 +**/ + uint32_t TempRamInitUpdOffset; +/** Offset 0x0014 +**/ + uint32_t MemoryInitUpdOffset; +/** Offset 0x0018 +**/ + uint32_t SiliconInitUpdOffset; +/** Offset 0x001C +**/ + uint32_t ReservedUpd1; +/** Offset 0x0020 +**/ + struct TEMP_RAM_INIT_UPD TempRamInitUpd; +/** Offset 0x0080 +**/ + struct MEMORY_INIT_UPD MemoryInitUpd; +/** Offset 0x0200 +**/ + struct SILICON_INIT_UPD SiliconInitUpd; +/** Offset 0x0358 +**/ + uint8_t UnusedUpdSpace10[166]; +/** Offset 0x03FE +**/ + uint16_t RegionTerminator; +} __attribute__((packed)); + +#define FSP_IMAGE_ID 0x2450534654584224 /* '$BXTFSP$' */ +#define FSP_IMAGE_REV 0x01010000 + +struct VPD_DATA_REGION { +/** Offset 0x0000 +**/ + uint64_t PcdVpdRegionSign; +/** Offset 0x0008 + PcdImageRevision +**/ + uint32_t PcdImageRevision; +/** Offset 0x000C +**/ + uint32_t PcdUpdRegionOffset; +/** Offset 0x0010 +**/ + uint32_t PcdUpdRegionSize; +/** Offset 0x0014 +**/ + uint64_t UnusedVpdSpace0; +/** Offset 0x001C +**/ + uint32_t PcdVpdReserved; +} __attribute__((packed)); + +#endif

1 0

Patch set updated for coreboot: soc/apollolake: Add cbmem_top() implementation
by Alexandru Gagniuc 26 Jan '16

26 Jan '16

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13329 -gerrit commit 8d7e5650356822f9fc80ec4814ad6123a4430189 Author: Andrey Petrov <andrey.petrov(a)intel.com> Date: Mon Nov 2 13:47:43 2015 -0800 soc/apollolake: Add cbmem_top() implementation Change-Id: Ibae9f43192f0e498e91ff8a51bd7d1e9a5b31350 Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> --- src/soc/intel/apollolake/Makefile.inc | 2 ++ src/soc/intel/apollolake/memmap.c | 27 +++++++++++++++++++++++++++ src/soc/intel/apollolake/placeholders.c | 5 ----- 3 files changed, 29 insertions(+), 5 deletions(-) diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc index e57342a..7cddf5a 100644 --- a/src/soc/intel/apollolake/Makefile.inc +++ b/src/soc/intel/apollolake/Makefile.inc @@ -18,12 +18,14 @@ bootblock-y += uart_early.c cpu_incs-y += $(src)/soc/intel/apollolake/romstage/entry.inc romstage-y += cpu.c romstage-y += gpio.c +romstage-y += memmap.c romstage-y += mmap_boot.c romstage-y += romstage/romstage.c romstage-y += uart_early.c ramstage-y += cpu.c ramstage-y += gpio.c +ramstage-y += memmap.c ramstage-y += mmap_boot.c ramstage-y += uart.c diff --git a/src/soc/intel/apollolake/memmap.c b/src/soc/intel/apollolake/memmap.c new file mode 100644 index 0000000..7de6217 --- /dev/null +++ b/src/soc/intel/apollolake/memmap.c @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * (Written by Andrey Petrov <andrey.petrov(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#define TSEG 0xb8 + +#define __SIMPLE_DEVICE__ +#include <arch/io.h> +#include <cbmem.h> + +static uintptr_t smm_region_start(void) +{ + return pci_read_config32(PCI_DEV(0, 0, 0), TSEG) & (~1); +} + +void *cbmem_top(void) +{ + return (void *)smm_region_start(); +} diff --git a/src/soc/intel/apollolake/placeholders.c b/src/soc/intel/apollolake/placeholders.c index cf0fe36..fc62d80 100644 --- a/src/soc/intel/apollolake/placeholders.c +++ b/src/soc/intel/apollolake/placeholders.c @@ -1,11 +1,6 @@ #include <cbmem.h> #include <cpu/x86/smm.h> -void *cbmem_top(void) -{ - return NULL; -} - void southbridge_smi_set_eos(void) { }

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coreboot-gerrit January 2016