coreboot-gerrit August 2015

coreboot-gerrit@coreboot.org

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814 discussions

Patch set updated for coreboot: intel/kunimitsu: fix kepler probing
by Patrick Georgi 29 Aug '15

29 Aug '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11431 -gerrit commit 740cb5246d772e3236c61b1bc06c9287e0e1961b Author: Wenkai Du <wenkai.du(a)intel.com> Date: Fri Aug 21 13:11:00 2015 -0700 intel/kunimitsu: fix kepler probing The patch was ported from commit: glados: fix kepler probing BUG=chrome-os-partner:44326 BRANCH=None TEST=Built and booted kunimitsu. lscpi shows the device on bus 2. Change-Id: I423e5d8414cb9864f6ff2f2ce7cd925baeb242eb Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Original-Commit-Id: 37bf5b7594a6784b3acb65410c670300e582e7aa Original-Original-change-Id: I7fe4a707f9321b7bdec4b4be729c5d0dcce65f6e Original-Originally-signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Original-Originally-reviewed-on: https://chromium-review.googlesource.com/294810 Original-Change-Id: I2fb620ebff5b477a1a457a354c65229ad1092cae Original-Signed-off-by: Wenkai Du <wenkai.du(a)intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/295164 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/mainboard/intel/kunimitsu/gpio.h | 8 ++++++++ src/mainboard/intel/kunimitsu/romstage.c | 11 +++++++++++ 2 files changed, 19 insertions(+) diff --git a/src/mainboard/intel/kunimitsu/gpio.h b/src/mainboard/intel/kunimitsu/gpio.h index 0dbf782..f1166c8 100644 --- a/src/mainboard/intel/kunimitsu/gpio.h +++ b/src/mainboard/intel/kunimitsu/gpio.h @@ -23,6 +23,7 @@ #include <soc/gpio.h> +/* Pad configuration in ramstage. */ static const struct pad_config gpio_table[] = { /* EC_PCH_RCIN */ PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), /* LPC_LAD_0 */ PAD_CFG_NF(GPP_A1, NONE, DEEP, NF1), @@ -189,4 +190,11 @@ static const struct pad_config gpio_table[] = { /* PM_SLP_S5# */ PAD_CFG_NF(GPD10, NONE, DEEP, NF1), /* LANPHYC */ /* GPD11 */ }; + +/* Early pad configuration in romstage. */ +static const struct pad_config early_gpio_table[] = { +/* SRCCLKREQ2# */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), /* KEPLER */ +/* UART0_CTS# */ PAD_CFG_GPO(GPP_C11, 1, DEEP), /* EN_PP3300_KEPLER */ +}; + #endif diff --git a/src/mainboard/intel/kunimitsu/romstage.c b/src/mainboard/intel/kunimitsu/romstage.c index c0d7aec..1491794 100644 --- a/src/mainboard/intel/kunimitsu/romstage.c +++ b/src/mainboard/intel/kunimitsu/romstage.c @@ -29,11 +29,22 @@ #include <soc/pei_wrapper.h> #include <soc/pm.h> #include <soc/romstage.h> +#include "gpio.h" #include "spd/spd.h" +static void early_config_gpio(void) +{ + /* This is a hack for FSP because it does things in MemoryInit() + * which it shouldn't be. We have to prepare certain gpios here + * because of the brokenness in FSP. */ + gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table)); +} + void mainboard_romstage_entry(struct romstage_params *params) { post_code(0x31); + early_config_gpio(); + /* Fill out PEI DATA */ mainboard_fill_pei_data(params->pei_data); mainboard_fill_spd_data(params->pei_data);

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Patch set updated for coreboot: intel/skylake: Add support for DPTF
by Patrick Georgi 29 Aug '15

29 Aug '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11430 -gerrit commit 51824c8151c0e8e157f3fef248d007850907f5fe Author: Shilpa Sreeramalu <shilpa.sreeramalu(a)intel.com> Date: Mon Jun 22 21:48:39 2015 +0530 intel/skylake: Add support for DPTF This patch adds the ASL files with the DPTF related settings and the thermal devices enabled in the SOC. It also enables the DPTF setting at the global NVS level. BRANCH=None BUG=chrome-os-partner:40855 TEST=Built for kunimitsu board. Tested to see that the thermal devices and the participants are enumerated and can be seen in the /sys/bus/platform/devices. Also checked the temperature readings of the cooling devices and the thermal zones enumerated in the /sys/class/thermal. Change-Id: I8ad044eaf1ad488fb1682097da83b40d2bede414 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Original-Commit-Id: 7624eeca19b4f286b30c3d4ac5b44c5e9619c2c7 Original-Change-Id: I0d92ef42cff5567ea6fc566730588802d8549ce0 Original-Signed-off-by: Shilpa Sreeramalu <shilpa.sreeramalu(a)intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/293391 Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Commit-Queue: Naveenkrishna Ch <naveenkrishna.ch(a)intel.com> --- src/soc/intel/skylake/acpi/dptf/charger.asl | 79 ++++++++++ src/soc/intel/skylake/acpi/dptf/cpu.asl | 226 ++++++++++++++++++++++++++++ src/soc/intel/skylake/acpi/dptf/dptf.asl | 102 +++++++++++++ src/soc/intel/skylake/acpi/dptf/thermal.asl | 223 +++++++++++++++++++++++++++ src/soc/intel/skylake/acpi/globalnvs.asl | 1 + src/soc/intel/skylake/include/soc/nvs.h | 3 +- 6 files changed, 633 insertions(+), 1 deletion(-) diff --git a/src/soc/intel/skylake/acpi/dptf/charger.asl b/src/soc/intel/skylake/acpi/dptf/charger.asl new file mode 100644 index 0000000..bcf5963 --- /dev/null +++ b/src/soc/intel/skylake/acpi/dptf/charger.asl @@ -0,0 +1,79 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * Copyright (C) 2015 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +Device (TCHG) +{ + Name (_HID, "INT3403") + Name (_UID, 0) + Name (PTYP, 0x0B) + Name (_STR, Unicode("Battery Charger")) + + Method (_STA) + { + If (LEqual (\DPTE, One)) { + Return (0xF) + } Else { + Return (0x0) + } + } + + /* Return charger performance states defined by mainboard */ + Method (PPSS) + { + Return (\_SB.CHPS) + } + + /* Return maximum charger current limit */ + Method (PPPC) + { + /* Convert size of PPSS table to index */ + Store (SizeOf (\_SB.CHPS), Local0) + Decrement (Local0) + + /* Check if charging is disabled (AC removed) */ + If (LEqual (\_SB.PCI0.LPCB.EC0.ACEX, Zero)) { + /* Return last power state */ + Return (Local0) + } Else { + /* Return highest power state */ + Return (0) + } + + Return (0) + } + + /* Set charger current limit */ + Method (SPPC, 1) + { + /* Retrieve Control (index 4) for specified PPSS level */ + Store (DeRefOf (Index (DeRefOf (Index + (\_SB.CHPS, ToInteger (Arg0))), 4)), Local0) + + /* Pass Control value to EC to limit charging */ + \_SB.PCI0.LPCB.EC0.CHGS (Local0) + } + + /* Initialize charger participant */ + Method (INIT) + { + /* Disable charge limit */ + \_SB.PCI0.LPCB.EC0.CHGD () + } +} diff --git a/src/soc/intel/skylake/acpi/dptf/cpu.asl b/src/soc/intel/skylake/acpi/dptf/cpu.asl new file mode 100644 index 0000000..56a0d07 --- /dev/null +++ b/src/soc/intel/skylake/acpi/dptf/cpu.asl @@ -0,0 +1,226 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * Copyright (C) 2015 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#ifndef DPTF_CPU_PASSIVE +#define DPTF_CPU_PASSIVE 80 +#endif + +#ifndef DPTF_CPU_CRITICAL +#define DPTF_CPU_CRITICAL 90 +#endif + +#ifndef DPTF_CPU_ACTIVE_AC0 +#define DPTF_CPU_ACTIVE_AC0 90 +#endif + +#ifndef DPTF_CPU_ACTIVE_AC1 +#define DPTF_CPU_ACTIVE_AC1 80 +#endif + +#ifndef DPTF_CPU_ACTIVE_AC2 +#define DPTF_CPU_ACTIVE_AC2 70 +#endif + +#ifndef DPTF_CPU_ACTIVE_AC3 +#define DPTF_CPU_ACTIVE_AC3 60 +#endif + +#ifndef DPTF_CPU_ACTIVE_AC4 +#define DPTF_CPU_ACTIVE_AC4 50 +#endif + +External (\_PR.CPU0._TSS, MethodObj) +External (\_PR.CPU0._TPC, MethodObj) +External (\_PR.CPU0._PTC, PkgObj) +External (\_PR.CPU0._TSD, PkgObj) + +Device (B0D4) +{ + Name(_ADR, 0x00040000) /* Bus 0, Device 4, Function 0 */ + + Method (_STA) + { + If (LEqual (\DPTE, One)) { + Return (0xF) + } Else { + Return (0x0) + } + } + + /* + * Processor Throttling Controls + */ + + Method (_TSS) + { + If (CondRefOf (\_PR.CPU0._TSS)) { + Return (\_PR.CPU0._TSS) + } Else { + Return (Package () + { + Package () { 0, 0, 0, 0, 0 } + }) + } + } + + Method (_TPC) + { + If (CondRefOf (\_PR.CPU0._TPC)) { + Return (\_PR.CPU0._TPC) + } Else { + Return (0) + } + } + + Method (_PTC) + { + If (CondRefOf (\_PR.CPU0._PTC)) { + Return (\_PR.CPU0._PTC) + } Else { + Return (Package () + { + Buffer () { 0 }, + Buffer () { 0 } + }) + } + } + + Method (_TSD) + { + If (CondRefOf (\_PR.CPU0._TSD)) { + Return (\_PR.CPU0._TSD) + } Else { + Return (Package () + { + Package () { 5, 0, 0, 0, 0 } + }) + } + } + + Method (_TDL) + { + If (CondRefOf (\_PR.CPU0._TSS)) { + Store (SizeOf (\_PR.CPU0._TSS ()), Local0) + Decrement (Local0) + Return (Local0) + } Else { + Return (0) + } + } + + /* + * Processor Performance Control + */ + + Method (_PPC) + { + Return (0) + } + + Method (SPPC, 1) + { + Store (Arg0, \PPCM) + + /* Notify OS to re-read _PPC limit on each CPU */ + \PPCN () + } + + Method (_PSS) + { + If (CondRefOf (\_PR.CP00._PSS)) { + Return (\_PR.CP00._PSS) + } Else { + Return (Package () + { + Package () { 0, 0, 0, 0, 0, 0 } + }) + } + } + + + Method (_PDL) + { + /* Check for mainboard specific _PDL override */ + If (CondRefOf (\_SB.MPDL)) { + Return (\_SB.MPDL) + } ElseIf (CondRefOf (\_PR.CP00._PSS)) { + Store (SizeOf (\_PR.CP00._PSS), Local0) + Decrement (Local0) + Return (Local0) + } Else { + Return (0) + } + } + + /* Return PPCC table defined by mainboard */ + Method (PPCC) + { + Return (\_SB.MPPC) + } + +#ifdef DPTF_CPU_CRITICAL + Method (_CRT) + { + Return (\_SB.DPTF.CTOK (DPTF_CPU_CRITICAL)) + } +#endif + +#ifdef DPTF_CPU_PASSIVE + Method (_PSV) + { + Return (\_SB.DPTF.CTOK (DPTF_CPU_PASSIVE)) + } +#endif + +#ifdef DPTF_CPU_ACTIVE_AC0 + Method (_AC0) + { + Return (\_SB.DPTF.CTOK (DPTF_CPU_ACTIVE_AC0)) + } +#endif + +#ifdef DPTF_CPU_ACTIVE_AC1 + Method (_AC1) + { + Return (\_SB.DPTF.CTOK (DPTF_CPU_ACTIVE_AC1)) + } +#endif + +#ifdef DPTF_CPU_ACTIVE_AC2 + Method (_AC2) + { + Return (\_SB.DPTF.CTOK (DPTF_CPU_ACTIVE_AC2)) + } +#endif + +#ifdef DPTF_CPU_ACTIVE_AC3 + Method (_AC3) + { + Return (\_SB.DPTF.CTOK (DPTF_CPU_ACTIVE_AC3)) + } +#endif + +#ifdef DPTF_CPU_ACTIVE_AC4 + Method (_AC4) + { + Return (\_SB.DPTF.CTOK (DPTF_CPU_ACTIVE_AC4)) + } +#endif +} diff --git a/src/soc/intel/skylake/acpi/dptf/dptf.asl b/src/soc/intel/skylake/acpi/dptf/dptf.asl new file mode 100644 index 0000000..7a8a8c7 --- /dev/null +++ b/src/soc/intel/skylake/acpi/dptf/dptf.asl @@ -0,0 +1,102 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * Copyright (C) 2015 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +Device (DPTF) +{ + Name (_HID, EISAID ("INT3400")) + Name (_UID, 0) + + Name (IDSP, Package() + { + /* DPPM Passive Policy 1.0 */ + ToUUID ("42A441D6-AE6A-462B-A84B-4A8CE79027D3"), + + /* DPPM Critical Policy */ + ToUUID ("97C68AE7-15FA-499c-B8C9-5DA81D606E0A"), + + /* DPPM Cooling Policy */ + ToUUID ("16CAF1B7-DD38-40ED-B1C1-1B8A1913D531"), + }) + + Method (_STA) + { + If (LEqual (\DPTE, One)) { + Return (0xF) + } Else { + Return (0x0) + } + } + + /* + * Arg0: Buffer containing UUID + * Arg1: Integer containing Revision ID of buffer format + * Arg2: Integer containing count of entries in Arg3 + * Arg3: Buffer containing list of DWORD capabilities + * Return: Buffer containing list of DWORD capabilities + */ + Method (_OSC, 4, Serialized) + { + /* Check for Passive Policy UUID */ + If (LEqual (DeRefOf (Index (IDSP, 0)), Arg0)) { + /* Initialize Thermal Devices */ + ^TINI () + +#ifdef DPTF_ENABLE_CHARGER + /* Initialize Charger Device */ + ^TCHG.INIT () +#endif + } + + Return (Arg3) + } + + /* Priority based _TRT */ + Name (TRTR, 1) + + Method (_TRT) + { + Return (\_SB.DTRT) + } + + /* Convert from Degrees C to 1/10 Kelvin for ACPI */ + Method (CTOK, 1) { + /* 10th of Degrees C */ + Multiply (Arg0, 10, Local0) + + /* Convert to Kelvin */ + Add (Local0, 2732, Local0) + + Return (Local0) + } + + /* Include Thermal Participants */ + #include "thermal.asl" + +#ifdef DPTF_ENABLE_CHARGER + /* Include Charger Participant */ + #include "charger.asl" +#endif + +} + +Scope (\_SB.PCI0) +{ + #include "cpu.asl" +} diff --git a/src/soc/intel/skylake/acpi/dptf/thermal.asl b/src/soc/intel/skylake/acpi/dptf/thermal.asl new file mode 100644 index 0000000..a6ab847 --- /dev/null +++ b/src/soc/intel/skylake/acpi/dptf/thermal.asl @@ -0,0 +1,223 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * Copyright (C) 2015 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +/* Thermal Threshold Event Handler */ +Method (TEVT, 1, NotSerialized) +{ + Store (ToInteger (Arg0), Local0) + +#ifdef DPTF_TSR0_SENSOR_ID + If (LEqual (Local0, DPTF_TSR0_SENSOR_ID)) { + Notify (^TSR0, 0x90) + } +#endif +#ifdef DPTF_TSR1_SENSOR_ID + If (LEqual (Local0, DPTF_TSR1_SENSOR_ID)) { + Notify (^TSR1, 0x90) + } +#endif +#ifdef DPTF_TSR2_SENSOR_ID + If (LEqual (Local0, DPTF_TSR2_SENSOR_ID)) { + Notify (^TSR2, 0x90) + } +#endif +} + +/* Thermal device initialization - Disable Aux Trip Points */ +Method (TINI) +{ +#ifdef DPTF_TSR0_SENSOR_ID + ^TSR0.PATD () +#endif +#ifdef DPTF_TSR1_SENSOR_ID + ^TSR1.PATD () +#endif +#ifdef DPTF_TSR2_SENSOR_ID + ^TSR2.PATD () +#endif +} + +#ifdef DPTF_TSR0_SENSOR_ID +Device (TSR0) +{ + Name (_HID, EISAID ("INT3403")) + Name (_UID, 1) + Name (PTYP, 0x03) + Name (TMPI, DPTF_TSR0_SENSOR_ID) + Name (_STR, Unicode (DPTF_TSR0_SENSOR_NAME)) + Name (GTSH, 20) /* 2 degree hysteresis */ + + Method (_STA) + { + If (LEqual (\DPTE, One)) { + Return (0xF) + } Else { + Return (0x0) + } + } + + Method (_TMP, 0, Serialized) + { + Return (\_SB.PCI0.LPCB.EC0.TSRD (TMPI)) + } + + Method (_PSV) + { + Return (CTOK (DPTF_TSR0_PASSIVE)) + } + + Method (_CRT) + { + Return (CTOK (DPTF_TSR0_CRITICAL)) + } + + Name (PATC, 2) + + /* Set Aux Trip Point */ + Method (PAT0, 1, Serialized) + { + \_SB.PCI0.LPCB.EC0.PAT0 (TMPI, Arg0) + } + + /* Set Aux Trip Point */ + Method (PAT1, 1, Serialized) + { + \_SB.PCI0.LPCB.EC0.PAT1 (TMPI, Arg0) + } + + /* Disable Aux Trip Point */ + Method (PATD, 0, Serialized) + { + \_SB.PCI0.LPCB.EC0.PATD (TMPI) + } +} +#endif + +#ifdef DPTF_TSR1_SENSOR_ID +Device (TSR1) +{ + Name (_HID, EISAID ("INT3403")) + Name (_UID, 2) + Name (PTYP, 0x03) + Name (TMPI, DPTF_TSR1_SENSOR_ID) + Name (_STR, Unicode (DPTF_TSR1_SENSOR_NAME)) + Name (GTSH, 20) /* 2 degree hysteresis */ + + Method (_STA) + { + If (LEqual (\DPTE, One)) { + Return (0xF) + } Else { + Return (0x0) + } + } + + Method (_TMP, 0, Serialized) + { + Return (\_SB.PCI0.LPCB.EC0.TSRD (TMPI)) + } + + Method (_PSV) + { + Return (CTOK (DPTF_TSR1_PASSIVE)) + } + + Method (_CRT) + { + Return (CTOK (DPTF_TSR1_CRITICAL)) + } + + Name (PATC, 2) + + /* Set Aux Trip Point */ + Method (PAT0, 1, Serialized) + { + \_SB.PCI0.LPCB.EC0.PAT0 (TMPI, Arg0) + } + + /* Set Aux Trip Point */ + Method (PAT1, 1, Serialized) + { + \_SB.PCI0.LPCB.EC0.PAT1 (TMPI, Arg0) + } + + /* Disable Aux Trip Point */ + Method (PATD, 0, Serialized) + { + \_SB.PCI0.LPCB.EC0.PATD (TMPI) + } +} +#endif + +#ifdef DPTF_TSR2_SENSOR_ID +Device (TSR2) +{ + Name (_HID, EISAID ("INT3403")) + Name (_UID, 3) + Name (PTYP, 0x03) + Name (TMPI, DPTF_TSR2_SENSOR_ID) + Name (_STR, Unicode (DPTF_TSR2_SENSOR_NAME)) + Name (GTSH, 20) /* 2 degree hysteresis */ + + Method (_STA) + { + If (LEqual (\DPTE, One)) { + Return (0xF) + } Else { + Return (0x0) + } + } + + Method (_TMP, 0, Serialized) + { + Return (\_SB.PCI0.LPCB.EC0.TSRD (TMPI)) + } + + Method (_PSV) + { + Return (CTOK (DPTF_TSR2_PASSIVE)) + } + + Method (_CRT) + { + Return (CTOK (DPTF_TSR2_CRITICAL)) + } + + Name (PATC, 2) + + /* Set Aux Trip Point */ + Method (PAT0, 1, Serialized) + { + \_SB.PCI0.LPCB.EC0.PAT0 (TMPI, Arg0) + } + + /* Set Aux Trip Point */ + Method (PAT1, 1, Serialized) + { + \_SB.PCI0.LPCB.EC0.PAT1 (TMPI, Arg0) + } + + /* Disable Aux Trip Point */ + Method (PATD, 0, Serialized) + { + \_SB.PCI0.LPCB.EC0.PATD (TMPI) + } +} +#endif diff --git a/src/soc/intel/skylake/acpi/globalnvs.asl b/src/soc/intel/skylake/acpi/globalnvs.asl index 5d07be7..b3d1bd2 100644 --- a/src/soc/intel/skylake/acpi/globalnvs.asl +++ b/src/soc/intel/skylake/acpi/globalnvs.asl @@ -75,6 +75,7 @@ Field (GNVS, ByteAcc, NoLock, Preserve) RPAA, 32, // 0x54 - 0x57 - Root port address 10 RPAB, 32, // 0x58 - 0x5b - Root port address 11 RPAC, 32, // 0x5c - 0x5f - Root port address 12 + DPTE, 8, // 0x60 - Enable DPTF /* ChromeOS specific */ Offset (0x100), diff --git a/src/soc/intel/skylake/include/soc/nvs.h b/src/soc/intel/skylake/include/soc/nvs.h index 2c83c5f..7fef190 100644 --- a/src/soc/intel/skylake/include/soc/nvs.h +++ b/src/soc/intel/skylake/include/soc/nvs.h @@ -56,8 +56,9 @@ typedef struct { u64 pm1i; /* 0x20 - 0x27 - PM1 wake status bit */ u64 gpei; /* 0x28 - 0x2f - GPE wake status bit */ u32 rpa[12]; /* 0x30 - 0x5f - Root Port Address */ + u8 dpte; /* 0x60 - Enable DPTF */ - u8 unused[160]; + u8 unused[159]; /* ChromeOS specific (0x100 - 0xfff) */ chromeos_acpi_t chromeos;

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Patch set updated for coreboot: intel/kunimitsu: Enable and support for DPTF
by Patrick Georgi 29 Aug '15

29 Aug '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11429 -gerrit commit 1982c6aee401d2bcf5d653a5c7516e333b7cad3e Author: Shilpa Sreeramalu <shilpa.sreeramalu(a)intel.com> Date: Mon Jun 22 21:54:51 2015 +0530 intel/kunimitsu: Enable and support for DPTF This patch includes the DPTF specific ASL files in the main DSDT definition and enables the CPU thermal participant device in the device tree. It also enables the DPTF flag in the global NVS table.It also adds the ASL settings specfic to the mainboard. BRANCH=None BUG=chrome-os-partner:40855 TEST=Built for kunimitsu board. Tested to see that the thermal devices and the participants are enumerated and can be seen in the /sys/bus/platform/devices. Also checked the temperature readings of the cooling devices and the thermal zones enumerated in the /sys/class/thermal. Change-Id: I5fb28e4480648eab39cc9b13ed55eae1d3db4d42 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Original-Commit-Id: 54f7f33a12eb5744d6108e362fa1d078fe838b3c Original-Change-Id: I82527989919bd4f3c49fb58dfc9463f1c1bd3353 Original-Signed-off-by: Shilpa Sreeramalu <shilpa.sreeramalu(a)intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/284821 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/294650 Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Commit-Queue: Naveenkrishna Ch <naveenkrishna.ch(a)intel.com> --- src/mainboard/intel/kunimitsu/acpi/dptf.asl | 100 ++++++++++++++++++++++++++++ src/mainboard/intel/kunimitsu/acpi_tables.c | 1 + src/mainboard/intel/kunimitsu/dsdt.asl | 2 + 3 files changed, 103 insertions(+) diff --git a/src/mainboard/intel/kunimitsu/acpi/dptf.asl b/src/mainboard/intel/kunimitsu/acpi/dptf.asl new file mode 100644 index 0000000..a056bf5 --- /dev/null +++ b/src/mainboard/intel/kunimitsu/acpi/dptf.asl @@ -0,0 +1,100 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * Copyright (C) 2015 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +/* CPU */ +#define DPTF_CPU_PASSIVE 80 +#define DPTF_CPU_CRITICAL 90 +#define DPTF_CPU_ACTIVE_AC0 90 +#define DPTF_CPU_ACTIVE_AC1 80 +#define DPTF_CPU_ACTIVE_AC2 70 +#define DPTF_CPU_ACTIVE_AC3 60 +#define DPTF_CPU_ACTIVE_AC4 50 + +#define DPTF_TSR0_SENSOR_ID 0 +#define DPTF_TSR0_SENSOR_NAME "TMP432_Internal" +#define DPTF_TSR0_PASSIVE 48 +#define DPTF_TSR0_CRITICAL 70 + +#define DPTF_TSR1_SENSOR_ID 1 +#define DPTF_TSR1_SENSOR_NAME "TMP432_Power_top" +#define DPTF_TSR1_PASSIVE 60 +#define DPTF_TSR1_CRITICAL 70 + +#define DPTF_TSR2_SENSOR_ID 2 +#define DPTF_TSR2_SENSOR_NAME "TMP432_CPU_bottom" +#define DPTF_TSR2_PASSIVE 55 +#define DPTF_TSR2_CRITICAL 70 + +#define DPTF_ENABLE_CHARGER + +/* Charger performance states, board-specific values from charger and EC */ +Name (CHPS, Package () { + Package () { 0, 0, 0, 0, 255, 0x6a4, "mA", 0 }, /* 1.7A (MAX) */ + Package () { 0, 0, 0, 0, 24, 0x600, "mA", 0 }, /* 1.5A */ + Package () { 0, 0, 0, 0, 16, 0x400, "mA", 0 }, /* 1.0A */ + Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 }, /* 0.5A */ + Package () { 0, 0, 0, 0, 0, 0x000, "mA", 0 }, /* 0.0A */ +}) + +/* Mainboard specific _PDL is 1GHz */ +Name (MPDL, 8) + +Name (DTRT, Package () { + /* CPU Throttle Effect on CPU */ + Package () { \_SB.PCI0.B0D4, \_SB.PCI0.B0D4, 100, 50, 0, 0, 0, 0 }, + + /* CPU Effect on Temp Sensor 0 */ + Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR0, 100, 600, 0, 0, 0, 0 }, + +#ifdef DPTF_ENABLE_CHARGER + /* Charger Effect on Temp Sensor 1 */ + Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR1, 200, 600, 0, 0, 0, 0 }, +#endif + + /* CPU Effect on Temp Sensor 1 */ + Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR1, 100, 600, 0, 0, 0, 0 }, + + /* CPU Effect on Temp Sensor 2 */ + Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR2, 100, 600, 0, 0, 0, 0 }, +}) + +Name (MPPC, Package () +{ + 0x2, /* Revision */ + Package () { /* Power Limit 1 */ + 0, /* PowerLimitIndex, 0 for Power Limit 1 */ + 1600, /* PowerLimitMinimum */ + 6000, /* PowerLimitMaximum */ + 1000, /* TimeWindowMinimum */ + 1000, /* TimeWindowMaximum */ + 200 /* StepSize */ + }, + Package () { /* Power Limit 2 */ + 1, /* PowerLimitIndex, 1 for Power Limit 2 */ + 8000, /* PowerLimitMinimum */ + 8000, /* PowerLimitMaximum */ + 1000, /* TimeWindowMinimum */ + 1000, /* TimeWindowMaximum */ + 1000 /* StepSize */ + } +}) + +/* Include DPTF */ +#include <soc/intel/skylake/acpi/dptf/dptf.asl> diff --git a/src/mainboard/intel/kunimitsu/acpi_tables.c b/src/mainboard/intel/kunimitsu/acpi_tables.c index f9eb7b0..640cd05 100644 --- a/src/mainboard/intel/kunimitsu/acpi_tables.c +++ b/src/mainboard/intel/kunimitsu/acpi_tables.c @@ -47,6 +47,7 @@ void acpi_create_gnvs(global_nvs_t *gnvs) gnvs->tcrt = CRITICAL_TEMPERATURE; gnvs->tpsv = PASSIVE_TEMPERATURE; gnvs->tmax = MAX_TEMPERATURE; + gnvs->dpte = 1; } unsigned long acpi_fill_madt(unsigned long current) diff --git a/src/mainboard/intel/kunimitsu/dsdt.asl b/src/mainboard/intel/kunimitsu/dsdt.asl index 6ac0be4..f9d67af 100644 --- a/src/mainboard/intel/kunimitsu/dsdt.asl +++ b/src/mainboard/intel/kunimitsu/dsdt.asl @@ -43,6 +43,8 @@ DefinitionBlock( #include <soc/intel/skylake/acpi/systemagent.asl> #include <soc/intel/skylake/acpi/pch.asl> } + // Thermal handler + #include "acpi/dptf.asl" } // Chrome OS specific

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Patch merged into coreboot/master: intel/sklrvp: Switch to using GPIO IRQ defines
by gerrit＠coreboot.org 29 Aug '15

29 Aug '15

the following patch was just integrated into master: commit bcd99301b8e2e312cb6a6a4d3adf749167fb84f9 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Fri Aug 21 11:36:23 2015 -0700 intel/sklrvp: Switch to using GPIO IRQ defines Use the macro for GPP_E22_IRQ instead of the ACPI code so it can be removed. BUG=chrome-os-partner:40635 BRANCH=none TEST=emerge-sklrvp coreboot Change-Id: I09bea748fea34072d4f8ad7470d37e423b7f63de Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Original-Commit-Id: 89069f5f318329182390cad679511547b7d2a6d5 Original-Change-Id: Iad181b4ce1c557ce8d17645431d8ba6f558bb837 Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/295171 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/11427 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See http://review.coreboot.org/11427 for details. -gerrit

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Patch set updated for coreboot: intel/sklrvp: Switch to using GPIO IRQ defines
by Patrick Georgi 29 Aug '15

29 Aug '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11427 -gerrit commit c71c01de65def81a24cb7f9b4344d0f3678360b3 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Fri Aug 21 11:36:23 2015 -0700 intel/sklrvp: Switch to using GPIO IRQ defines Use the macro for GPP_E22_IRQ instead of the ACPI code so it can be removed. BUG=chrome-os-partner:40635 BRANCH=none TEST=emerge-sklrvp coreboot Change-Id: I09bea748fea34072d4f8ad7470d37e423b7f63de Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Original-Commit-Id: 89069f5f318329182390cad679511547b7d2a6d5 Original-Change-Id: Iad181b4ce1c557ce8d17645431d8ba6f558bb837 Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/295171 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/mainboard/intel/sklrvp/acpi/mainboard.asl | 15 +++------------ 1 file changed, 3 insertions(+), 12 deletions(-) diff --git a/src/mainboard/intel/sklrvp/acpi/mainboard.asl b/src/mainboard/intel/sklrvp/acpi/mainboard.asl index d771f62..c80a03d 100644 --- a/src/mainboard/intel/sklrvp/acpi/mainboard.asl +++ b/src/mainboard/intel/sklrvp/acpi/mainboard.asl @@ -18,9 +18,7 @@ * Foundation, Inc. */ -/* REAKTEK Audio Jack Interrupt */ -#define GPIO_SKL_LP_GPP_E22 0x02040016 - +#include <soc/gpio.h> #include <mainboard/intel/sklrvp/onboard.h> /* @@ -138,18 +136,11 @@ Scope (\_SB.PCI0.I2C0) Name (SBFI, ResourceTemplate () { Interrupt (ResourceConsumer, Level, ActiveLow, - ExclusiveAndWake, ,, _Y22) + ExclusiveAndWake) { - 0x00000000, + GPP_E22_IRQ } }) - - /* _INT: Interrupts */ - CreateDWordField (SBFI, _Y22._INT, INT2) - - Store (INUM (GPIO_SKL_LP_GPP_E22), INT2) - - Return (ConcatenateResTemplate (RBUF, SBFI)) } Method (_STA, 0, NotSerialized)

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Patch merged into coreboot/master: intel/skylake: remove the gpio_fsp.h usage as skylake boards move gpio config to coreboot completely
by gerrit＠coreboot.org 29 Aug '15

29 Aug '15

the following patch was just integrated into master: commit ad3127f3445f2f8507d16cada09e2ece9703c049 Author: robbie zhang <robbie.zhang(a)intel.com> Date: Fri Aug 21 11:12:58 2015 -0700 intel/skylake: remove the gpio_fsp.h usage as skylake boards move gpio config to coreboot completely BUG=None BRANCH=None TEST=Built and booted kunimitsu. CQ-DEPEND=CL:295012 Change-Id: I78e16e8079c4ee0c4fa70cb7a74ba039ee89398f Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Original-Commit-Id: 6f1db1a2ffdbeb7dd21b4894f74d3feb44d69c49 Original-Change-Id: I8aafb0ef7d1b77cb8d386f4e73dc46ea3d8ee3a4 Original-Signed-off-by: robbie zhang <robbie.zhang(a)intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/294758 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Tested-by: Wenkai Du <wenkai.du(a)intel.com> Reviewed-on: http://review.coreboot.org/11426 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> See http://review.coreboot.org/11426 for details. -gerrit

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Patch set updated for coreboot: intel/skylake: remove the gpio_fsp.h usage as skylake boards move gpio config to coreboot completely
by Patrick Georgi 29 Aug '15

29 Aug '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11426 -gerrit commit f400989891f85ee13d78e9d0f4a137fa169bad83 Author: robbie zhang <robbie.zhang(a)intel.com> Date: Fri Aug 21 11:12:58 2015 -0700 intel/skylake: remove the gpio_fsp.h usage as skylake boards move gpio config to coreboot completely BUG=None BRANCH=None TEST=Built and booted kunimitsu. CQ-DEPEND=CL:295012 Change-Id: I78e16e8079c4ee0c4fa70cb7a74ba039ee89398f Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Original-Commit-Id: 6f1db1a2ffdbeb7dd21b4894f74d3feb44d69c49 Original-Change-Id: I8aafb0ef7d1b77cb8d386f4e73dc46ea3d8ee3a4 Original-Signed-off-by: robbie zhang <robbie.zhang(a)intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/294758 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Tested-by: Wenkai Du <wenkai.du(a)intel.com> --- src/soc/intel/skylake/include/soc/gpio.h | 1 - src/soc/intel/skylake/include/soc/gpio_fsp.h | 512 --------------------------- 2 files changed, 513 deletions(-) diff --git a/src/soc/intel/skylake/include/soc/gpio.h b/src/soc/intel/skylake/include/soc/gpio.h index 56fd52e..84d2a70 100644 --- a/src/soc/intel/skylake/include/soc/gpio.h +++ b/src/soc/intel/skylake/include/soc/gpio.h @@ -26,7 +26,6 @@ #ifndef __ACPI__ #include <stdint.h> #include <stddef.h> -#include <soc/gpio_fsp.h> typedef uint32_t gpio_t; diff --git a/src/soc/intel/skylake/include/soc/gpio_fsp.h b/src/soc/intel/skylake/include/soc/gpio_fsp.h deleted file mode 100644 index cedbf82..0000000 --- a/src/soc/intel/skylake/include/soc/gpio_fsp.h +++ /dev/null @@ -1,512 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015 Intel Corporation. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc. - */ - -#ifndef _SOC_GPIO_FSP_H_ -#define _SOC_GPIO_FSP_H_ - -#include <stdint.h> - -/* - * GPP_Ax to GPP_Gx; - * where x=24 [between GPIO Community A to F] - * = 7 [only for GPIO Community G] - */ -#define MAX_GPIO_NUMBER 151 /* zero based */ -#define GPIO_LIST_END 0xffffffff - -/* - * Skylake LP GPIO PIN to Pad Mapping - */ -#define GPIO_LP_GROUP_A 0x0 -#define GPIO_LP_GROUP_B 0x1 -#define GPIO_LP_GROUP_C 0x2 -#define GPIO_LP_GROUP_D 0x3 -#define GPIO_LP_GROUP_E 0x4 -#define GPIO_LP_GROUP_F 0x5 -#define GPIO_LP_GROUP_G 0x6 - -#define GPIO_LP_GROUP_GPP_A 0x0200 -#define GPIO_LP_GROUP_GPP_B 0x0201 -#define GPIO_LP_GROUP_GPP_C 0x0202 -#define GPIO_LP_GROUP_GPP_D 0x0203 -#define GPIO_LP_GROUP_GPP_E 0x0204 -#define GPIO_LP_GROUP_GPP_F 0x0205 -#define GPIO_LP_GROUP_GPP_G 0x0206 - -#define GPIO_GROUP_SHIFT 16 -#define MAX_GPIO_PIN_PER_GROUP 24 - -/* GPIO TX STATE */ -#define B_PCH_GPIO_TX_STATE 0x0001 -#define N_PCH_GPIO_TX_STATE 0 - -/* Interrupt number */ -#define B_PCH_GPIO_INTSEL 0x7F -#define N_PCH_GPIO_INTSEL 0 - -/* Structure for storing information about registers offset, community, - * maximal pad number, smi status and smi enable for available groups - */ -typedef struct { - u32 community; - u32 padcfgoffset; - u32 padpergroup; - u32 smistsoffset; - u32 smienoffset; -} GPIO_GROUP_INFO; - -/* - * GPIO Community 0 Registers are for GPP_A and GPP_B groups - */ -#define R_PCH_PCR_GPIO_GPP_A_PADCFG_OFFSET 0x400 -#define R_PCH_PCR_GPIO_GPP_B_PADCFG_OFFSET 0x4C0 -#define R_PCH_PCR_GPIO_GPP_A_SMI_STS 0x0180 -#define R_PCH_PCR_GPIO_GPP_B_SMI_STS 0x0184 -#define R_PCH_PCR_GPIO_GPP_A_SMI_EN 0x01A0 -#define R_PCH_PCR_GPIO_GPP_B_SMI_EN 0x01A4 - -/* - * GPIO Community 1 Registers are for GPP_C, GPP_D, GPP_E groups - */ -#define R_PCH_PCR_GPIO_GPP_C_PADCFG_OFFSET 0x400 -#define R_PCH_PCR_GPIO_GPP_D_PADCFG_OFFSET 0x4C0 -#define R_PCH_PCR_GPIO_GPP_E_PADCFG_OFFSET 0x580 -#define R_PCH_PCR_GPIO_GPP_C_SMI_STS 0x0180 -#define R_PCH_PCR_GPIO_GPP_D_SMI_STS 0x0184 -#define R_PCH_PCR_GPIO_GPP_E_SMI_STS 0x0188 -#define R_PCH_PCR_GPIO_GPP_C_SMI_EN 0x01A0 -#define R_PCH_PCR_GPIO_GPP_D_SMI_EN 0x01A4 -#define R_PCH_PCR_GPIO_GPP_E_SMI_EN 0x01A8 - -/* - * GPIO Community 3 Registers are for GPP_F and GPP_G groups - */ -#define R_PCH_PCR_GPIO_GPP_F_PADCFG_OFFSET 0x400 -#define R_PCH_PCR_GPIO_GPP_G_PADCFG_OFFSET 0x4C0 - -/* - * GPIO Community 2 Registers are for GPP_DSW - */ -#define R_PCH_PCR_GPIO_GPD_PADCFG_OFFSET 0x400 - -#define READ 0 -#define WRITE 1 - -/* If in GPIO_GROUP_INFO structure certain register doesn't exist - * it will have value equal to NO_REGISTER_PROPERTY - */ -#define NO_REGISTER_PROPERTY (~0u) - -#define V_PCH_GPIO_GPP_A_PAD_MAX 24 -#define V_PCH_GPIO_GPP_B_PAD_MAX 24 -#define V_PCH_GPIO_GPP_C_PAD_MAX 24 -#define V_PCH_GPIO_GPP_D_PAD_MAX 24 -#define V_PCH_GPIO_GPP_E_PAD_MAX 24 -#define V_PCH_GPIO_GPP_F_PAD_MAX 24 -#define V_PCH_GPIO_GPP_G_PAD_MAX 8 -#define V_PCH_GPIO_GPD_PAD_MAX 12 - -#define GPIO_GET_GROUP_INDEX(group) (group & 0xFF) -#define GPIO_GET_GROUP_INDEX_FROM_PAD(pad) (\ - GPIO_GET_GROUP_INDEX((pad >> 16))) -#define GPIO_GET_PAD_NUMBER(pad) (pad & 0xFFFF) - -/* Number of pins used by SerialIo controllers */ -#define PCH_SERIAL_IO_PINS_PER_UART_CONTROLLER 4 -#define PCH_SERIAL_IO_PINS_PER_UART_CONTROLLER_NO_FLOW_CTRL 2 - -/* Below defines are based on GPIO_CONFIG structure fields */ -#define GPIO_CONF_PAD_MODE_MASK 0xF -#define GPIO_CONF_PAD_MODE_BIT_POS 0 - -/* GPIO Pad Mode */ -#define B_PCH_GPIO_PAD_MODE (0x1000 | 0x800 | 0x400) -#define N_PCH_GPIO_PAD_MODE 10 - -/* For any GpioPad usage in code use GPIO_PAD type*/ -typedef u32 GPIO_PAD; - -/* For any GpioGroup usage in code use GPIO_GROUP type */ -typedef u32 GPIO_GROUP; - -/* - * GPIO configuration structure used for pin programming. - * Structure contains fields that can be used to configure pad. - */ -typedef struct { - /* - Pad Mode - Pad can be set as GPIO or one of its native functions. - When in native mode setting Direction, OutputState, Interrupt is unnecessary. - Refer to definition of GPIO_PAD_MODE. - Refer to EDS for each native mode according to the pad. - */ - u32 PadMode : 4; - /* - Host Software Pad Ownership - Set pad to ACPI mode or GPIO Driver Mode. - Refer to definition of GPIO_HOSTSW_OWN. - */ - u32 HostSoftPadOwn : 2; - /* - GPIO Direction - Can choose between In, In with inversion Out, both In and Out, both In with inversion and out or d - isabling both. - Refer to definition of GPIO_DIRECTION for supported settings. - */ - u32 Direction : 5; - /* - Output State - Set Pad output value. - Refer to definition of GPIO_OUTPUT_STATE for supported settings. - This setting takes place when output is enabled. - */ - u32 OutputState : 2; - /* - GPIO Interrupt Configuration - Set Pad to cause one of interrupts (IOxAPIC/SCI/SMI/NMI). This setting is applicable only if GPIO - A is in input mode. - If GPIO is set to cause an SCI then also Gpe is enabled for this pad. - Refer to definition of GPIO_INT_CONFIG for supported settings. - */ - u32 InterruptConfig : 8; - /* - GPIO Power Configuration. - This setting controls Pad Reset Configuration and Power Rail Type. - Refer to definition of GPIO_RESET_CONFIG for supported settings. - */ - u32 PowerConfig : 4; - /* - GPIO Electrical Configuration - This setting controls pads termination and voltage tolerance. - Refer to definition of GPIO_ELECTRICAL_CONFIG for supported settings. - */ - u32 ElectricalConfig : 7; - /* - GPIO Lock Configuration - This setting controls pads lock. - Refer to definition of GPIO_LOCK_CONFIG for supported settings. - */ - u32 LockConfig : 3; - /* - Additional GPIO configuration - Refer to definition of GPIO_OTHER_CONFIG for supported settings. - */ - u32 OtherSettings : 2; - u32 RsvdBits : 27; -} GPIO_CONFIG; - -typedef struct { - GPIO_PAD GpioPad; - GPIO_CONFIG GpioConfig; -} GPIO_INIT_CONFIG; - -typedef enum { - GpioHardwareDefault = 0x0 -} GPIO_HARDWARE_DEFAULT; - -/* GPIO Pad Mode */ -typedef enum { - GpioPadModeGpio = 0x1, - GpioPadModeNative1 = 0x3, - GpioPadModeNative2 = 0x5, - GpioPadModeNative3 = 0x7, - GpioPadModeNative4 = 0x9, -} GPIO_PAD_MODE; - -/* Host Software Pad Ownership modes */ -typedef enum { - GpioHostOwnDefault = 0x0, /* Leave ownership value unmodified */ - GpioHostOwnAcpi = 0x1, /* Set HOST ownership to ACPI */ - GpioHostOwnGpio = 0x3 /* Set HOST ownership to GPIO */ -} GPIO_HOSTSW_OWN; - -/* GPIO Direction */ -typedef enum { - GpioDirDefault = 0x0, /* Leave pad direction setting unmodified */ - GpioDirInOut = (0x1 | (0x1 << 3)), /* Set pad for both output and input */ - GpioDirInInvOut = (0x1 | (0x3 << 3)), /* Set pad for both output and input with inversion */ - GpioDirIn = (0x3 | (0x1 << 3)), /* Set pad for input only */ - GpioDirInInv = (0x3 | (0x3 << 3)), /* Set pad for input with inversion */ - GpioDirOut = 0x5, /* Set pad for output only */ - GpioDirNone = 0x7 /* Disable both output and input */ -} GPIO_DIRECTION; - -/* GPIO Output State */ -typedef enum { - GpioOutDefault = 0x0, - GpioOutLow = 0x1, - GpioOutHigh = 0x3 -} GPIO_OUTPUT_STATE; - -/* - * GPIO interrupt configuration - * This setting is applicable only if GPIO is in input mode. - * GPIO_INT_CONFIG allows to choose which interrupt is generted - * (IOxAPIC/SCI/SMI/NMI) and how it is triggered (edge or level). - * Field from GpioIntNmi to GpioIntApic can be OR'ed with GpioIntLevel to - * GpioIntBothEdgecan to describe an interrupt e.g. GpioIntApic | GpioIntLevel - * If GPIO is set to cause an SCI then also Gpe is enabled for this pad. - * Not all GPIO are capable of generating an SMI or NMI interrupt - */ -typedef enum { - GpioIntDefault = 0x0, /* Leave value of interrupt routing unmodified */ - GpioIntDis = 0x1, /* Disable IOxAPIC/SCI/SMI/NMI interrupt generation */ - GpioIntNmi = 0x3, /* Enable NMI interrupt only */ - GpioIntSmi = 0x5, /* Enable SMI interrupt only */ - GpioIntSci = 0x9, /* Enable SCI interrupt only */ - GpioIntApic = 0x11, /* Enable IOxAPIC interrupt only */ - GpioIntLevel = (0x1 << 5), /* Set interrupt as level triggered */ - GpioIntEdge = (0x3 << 5), /* Set interrupt as edge triggered */ - GpioIntLvlEdgDis = (0x5 << 5), /* Disable interrupt trigger */ - GpioIntBothEdge = (0x7 << 5) /* Set interrupt as both edge triggered */ -} GPIO_INT_CONFIG; - -/* - * GPIO Power Configuration - * GPIO_RESET_CONFIG allows to set GPIO Reset (used to reset the specified - * Pad Register fields). - */ -typedef enum { - GpioResetDefault = 0x0, /* Leave value of pad reset unmodified */ - GpioResetPwrGood = 0x1, /* Powergood reset */ - GpioResetDeep = 0x3, /* Deep GPIO Reset */ - GpioResetNormal = 0x5, /* GPIO Reset */ - GpioResetResume = 0x7 /* Resume Reset */ -} GPIO_RESET_CONFIG; - -/* - * GPIO Electrical Configuration - * Set GPIO termination and Pad Tolerance (applicable only for some pads) - * Field from GpioTermDefault to GpioTermNative can be OR'ed with - * GpioTolerance1v8. - */ -typedef enum { - GpioTermDefault = 0x0, /* Leave termination setting unmodified */ - GpioTermNone = 0x1, /* none */ - GpioTermWpd5K = 0x5, /* 5kOhm weak pull-down */ - GpioTermWpd20K = 0x9, /* 20kOhm weak pull-down */ - GpioTermWpu1K = 0x13, /* 1kOhm weak pull-up */ - GpioTermWpu2K = 0x17, /* 2kOhm weak pull-up */ - GpioTermWpu5K = 0x15, /* 5kOhm weak pull-up */ - GpioTermWpu20K = 0x19, /* 20kOhm weak pull-up */ - GpioTermWpu1K2K = 0x1B, /* 1kOhm & 2kOhm weak pull-up */ - GpioTermNative = 0x1F, /* Native function for pads termination */ - GpioNoTolerance1v8 = (0x1 << 5), /* Disable 1.8V pad tolerance */ - GpioTolerance1v8 = (0x3 << 5) /* Enable 1.8V pad tolerance */ -} GPIO_ELECTRICAL_CONFIG; - -/* - * GPIO LockConfiguration - * Set GPIO configuration lock and output state lock - * GpioLockPadConfig and GpioLockOutputState can be OR'ed - */ -typedef enum { - GpioLockDefault = 0x0, /* Leave lock setting unmodified */ - GpioPadConfigLock = 0x3, /* Lock Pad Configuration */ - GpioOutputStateLock = 0x5 /* Lock GPIO pad output value */ -} GPIO_LOCK_CONFIG; - -/* - * Other GPIO Configuration GPIO_OTHER_CONFIG is used for less often - * settings and for future extensions Supported settings: - * - RX raw override to '1' - allows to override input value to '1' - * This is applicable only if in input mode (both in GPIO and native usage) - * The override takes place at the internal pad state directly from buffer - * and before the RXINV. - */ -typedef enum { - GpioRxRaw1Default = 0x0, /* Use default input override value */ - GpioRxRaw1Dis = 0x1, /* Don't override input */ - GpioRxRaw1En = 0x3 /* Override input to '1' */ -} GPIO_OTHER_CONFIG; - -/* - * LP GPIO pins: Use below for functions from PCH GPIO Lib which - * require GpioPad as argument. Encoding used here - * has all information required by library functions - */ -#define GPIO_LP_GPP_A0 0x02000000 -#define GPIO_LP_GPP_A1 0x02000001 -#define GPIO_LP_GPP_A2 0x02000002 -#define GPIO_LP_GPP_A3 0x02000003 -#define GPIO_LP_GPP_A4 0x02000004 -#define GPIO_LP_GPP_A5 0x02000005 -#define GPIO_LP_GPP_A6 0x02000006 -#define GPIO_LP_GPP_A7 0x02000007 -#define GPIO_LP_GPP_A8 0x02000008 -#define GPIO_LP_GPP_A9 0x02000009 -#define GPIO_LP_GPP_A10 0x0200000A -#define GPIO_LP_GPP_A11 0x0200000B -#define GPIO_LP_GPP_A12 0x0200000C -#define GPIO_LP_GPP_A13 0x0200000D -#define GPIO_LP_GPP_A14 0x0200000E -#define GPIO_LP_GPP_A15 0x0200000F -#define GPIO_LP_GPP_A16 0x02000010 -#define GPIO_LP_GPP_A17 0x02000011 -#define GPIO_LP_GPP_A18 0x02000012 -#define GPIO_LP_GPP_A19 0x02000013 -#define GPIO_LP_GPP_A20 0x02000014 -#define GPIO_LP_GPP_A21 0x02000015 -#define GPIO_LP_GPP_A22 0x02000016 -#define GPIO_LP_GPP_A23 0x02000017 -#define GPIO_LP_GPP_B0 0x02010000 -#define GPIO_LP_GPP_B1 0x02010001 -#define GPIO_LP_GPP_B2 0x02010002 -#define GPIO_LP_GPP_B3 0x02010003 -#define GPIO_LP_GPP_B4 0x02010004 -#define GPIO_LP_GPP_B5 0x02010005 -#define GPIO_LP_GPP_B6 0x02010006 -#define GPIO_LP_GPP_B7 0x02010007 -#define GPIO_LP_GPP_B8 0x02010008 -#define GPIO_LP_GPP_B9 0x02010009 -#define GPIO_LP_GPP_B10 0x0201000A -#define GPIO_LP_GPP_B11 0x0201000B -#define GPIO_LP_GPP_B12 0x0201000C -#define GPIO_LP_GPP_B13 0x0201000D -#define GPIO_LP_GPP_B14 0x0201000E -#define GPIO_LP_GPP_B15 0x0201000F -#define GPIO_LP_GPP_B16 0x02010010 -#define GPIO_LP_GPP_B17 0x02010011 -#define GPIO_LP_GPP_B18 0x02010012 -#define GPIO_LP_GPP_B19 0x02010013 -#define GPIO_LP_GPP_B20 0x02010014 -#define GPIO_LP_GPP_B21 0x02010015 -#define GPIO_LP_GPP_B22 0x02010016 -#define GPIO_LP_GPP_B23 0x02010017 -#define GPIO_LP_GPP_C0 0x02020000 -#define GPIO_LP_GPP_C1 0x02020001 -#define GPIO_LP_GPP_C2 0x02020002 -#define GPIO_LP_GPP_C3 0x02020003 -#define GPIO_LP_GPP_C4 0x02020004 -#define GPIO_LP_GPP_C5 0x02020005 -#define GPIO_LP_GPP_C6 0x02020006 -#define GPIO_LP_GPP_C7 0x02020007 -#define GPIO_LP_GPP_C8 0x02020008 -#define GPIO_LP_GPP_C9 0x02020009 -#define GPIO_LP_GPP_C10 0x0202000A -#define GPIO_LP_GPP_C11 0x0202000B -#define GPIO_LP_GPP_C12 0x0202000C -#define GPIO_LP_GPP_C13 0x0202000D -#define GPIO_LP_GPP_C14 0x0202000E -#define GPIO_LP_GPP_C15 0x0202000F -#define GPIO_LP_GPP_C16 0x02020010 -#define GPIO_LP_GPP_C17 0x02020011 -#define GPIO_LP_GPP_C18 0x02020012 -#define GPIO_LP_GPP_C19 0x02020013 -#define GPIO_LP_GPP_C20 0x02020014 -#define GPIO_LP_GPP_C21 0x02020015 -#define GPIO_LP_GPP_C22 0x02020016 -#define GPIO_LP_GPP_C23 0x02020017 -#define GPIO_LP_GPP_D0 0x02030000 -#define GPIO_LP_GPP_D1 0x02030001 -#define GPIO_LP_GPP_D2 0x02030002 -#define GPIO_LP_GPP_D3 0x02030003 -#define GPIO_LP_GPP_D4 0x02030004 -#define GPIO_LP_GPP_D5 0x02030005 -#define GPIO_LP_GPP_D6 0x02030006 -#define GPIO_LP_GPP_D7 0x02030007 -#define GPIO_LP_GPP_D8 0x02030008 -#define GPIO_LP_GPP_D9 0x02030009 -#define GPIO_LP_GPP_D10 0x0203000A -#define GPIO_LP_GPP_D11 0x0203000B -#define GPIO_LP_GPP_D12 0x0203000C -#define GPIO_LP_GPP_D13 0x0203000D -#define GPIO_LP_GPP_D14 0x0203000E -#define GPIO_LP_GPP_D15 0x0203000F -#define GPIO_LP_GPP_D16 0x02030010 -#define GPIO_LP_GPP_D17 0x02030011 -#define GPIO_LP_GPP_D18 0x02030012 -#define GPIO_LP_GPP_D19 0x02030013 -#define GPIO_LP_GPP_D20 0x02030014 -#define GPIO_LP_GPP_D21 0x02030015 -#define GPIO_LP_GPP_D22 0x02030016 -#define GPIO_LP_GPP_D23 0x02030017 -#define GPIO_LP_GPP_E0 0x02040000 -#define GPIO_LP_GPP_E1 0x02040001 -#define GPIO_LP_GPP_E2 0x02040002 -#define GPIO_LP_GPP_E3 0x02040003 -#define GPIO_LP_GPP_E4 0x02040004 -#define GPIO_LP_GPP_E5 0x02040005 -#define GPIO_LP_GPP_E6 0x02040006 -#define GPIO_LP_GPP_E7 0x02040007 -#define GPIO_LP_GPP_E8 0x02040008 -#define GPIO_LP_GPP_E9 0x02040009 -#define GPIO_LP_GPP_E10 0x0204000A -#define GPIO_LP_GPP_E11 0x0204000B -#define GPIO_LP_GPP_E12 0x0204000C -#define GPIO_LP_GPP_E13 0x0204000D -#define GPIO_LP_GPP_E14 0x0204000E -#define GPIO_LP_GPP_E15 0x0204000F -#define GPIO_LP_GPP_E16 0x02040010 -#define GPIO_LP_GPP_E17 0x02040011 -#define GPIO_LP_GPP_E18 0x02040012 -#define GPIO_LP_GPP_E19 0x02040013 -#define GPIO_LP_GPP_E20 0x02040014 -#define GPIO_LP_GPP_E21 0x02040015 -#define GPIO_LP_GPP_E22 0x02040016 -#define GPIO_LP_GPP_E23 0x02040017 -#define GPIO_LP_GPP_F0 0x02050000 -#define GPIO_LP_GPP_F1 0x02050001 -#define GPIO_LP_GPP_F2 0x02050002 -#define GPIO_LP_GPP_F3 0x02050003 -#define GPIO_LP_GPP_F4 0x02050004 -#define GPIO_LP_GPP_F5 0x02050005 -#define GPIO_LP_GPP_F6 0x02050006 -#define GPIO_LP_GPP_F7 0x02050007 -#define GPIO_LP_GPP_F8 0x02050008 -#define GPIO_LP_GPP_F9 0x02050009 -#define GPIO_LP_GPP_F10 0x0205000A -#define GPIO_LP_GPP_F11 0x0205000B -#define GPIO_LP_GPP_F12 0x0205000C -#define GPIO_LP_GPP_F13 0x0205000D -#define GPIO_LP_GPP_F14 0x0205000E -#define GPIO_LP_GPP_F15 0x0205000F -#define GPIO_LP_GPP_F16 0x02050010 -#define GPIO_LP_GPP_F17 0x02050011 -#define GPIO_LP_GPP_F18 0x02050012 -#define GPIO_LP_GPP_F19 0x02050013 -#define GPIO_LP_GPP_F20 0x02050014 -#define GPIO_LP_GPP_F21 0x02050015 -#define GPIO_LP_GPP_F22 0x02050016 -#define GPIO_LP_GPP_F23 0x02050017 -#define GPIO_LP_GPP_G0 0x02060000 -#define GPIO_LP_GPP_G1 0x02060001 -#define GPIO_LP_GPP_G2 0x02060002 -#define GPIO_LP_GPP_G3 0x02060003 -#define GPIO_LP_GPP_G4 0x02060004 -#define GPIO_LP_GPP_G5 0x02060005 -#define GPIO_LP_GPP_G6 0x02060006 -#define GPIO_LP_GPP_G7 0x02060007 -#define GPIO_LP_GPD0 0x02070000 -#define GPIO_LP_GPD1 0x02070001 -#define GPIO_LP_GPD2 0x02070002 -#define GPIO_LP_GPD3 0x02070003 -#define GPIO_LP_GPD4 0x02070004 -#define GPIO_LP_GPD5 0x02070005 -#define GPIO_LP_GPD6 0x02070006 -#define GPIO_LP_GPD7 0x02070007 -#define GPIO_LP_GPD8 0x02070008 -#define GPIO_LP_GPD9 0x02070009 -#define GPIO_LP_GPD10 0x0207000A -#define GPIO_LP_GPD11 0x0207000B - -#define END_OF_GPIO_TABLE 0xFFFFFFFF -#endif

1 0

Patch merged into coreboot/master: intel/kunimitsu: do gpio configuration in coreboot instead of fsp
by gerrit＠coreboot.org 29 Aug '15

29 Aug '15

the following patch was just integrated into master: commit c9d9729f5cd80b29427e94b7ab91faaaa54d17db Author: robbie zhang <robbie.zhang(a)intel.com> Date: Fri Aug 21 09:47:34 2015 -0700 intel/kunimitsu: do gpio configuration in coreboot instead of fsp BUG=chrome-os-partner:44336 BRANCH=None TEST=Built and booted kunimitsu. Validation shows no regressions. CQ-DEPEND=CL:294757 Change-Id: If4207e87cf22982162a8d5d47fa9e0509a2b2ab1 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Original-Commit-Id: 2f43fd6b7afc426d041a242a7e03dbf5800e1eee Original-Change-Id: Id8ce1bd2f28d32898e99008e2a602d99a5c1098c Original-Signed-off-by: Robbie Zhang <robbie.zhang(a)intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/295012 Original-Reviewed-by: Wenkai Du <wenkai.du(a)intel.com> Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Tested-by: Wenkai Du <wenkai.du(a)intel.com> Reviewed-on: http://review.coreboot.org/11425 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> See http://review.coreboot.org/11425 for details. -gerrit

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Patch set updated for coreboot: intel/kunimitsu: do gpio configuration in coreboot instead of fsp
by Patrick Georgi 29 Aug '15

29 Aug '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11425 -gerrit commit 8dfb51b65e067bb719bdbdf410d0b0efe4fd39d1 Author: robbie zhang <robbie.zhang(a)intel.com> Date: Fri Aug 21 09:47:34 2015 -0700 intel/kunimitsu: do gpio configuration in coreboot instead of fsp BUG=chrome-os-partner:44336 BRANCH=None TEST=Built and booted kunimitsu. Validation shows no regressions. CQ-DEPEND=CL:294757 Change-Id: If4207e87cf22982162a8d5d47fa9e0509a2b2ab1 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Original-Commit-Id: 2f43fd6b7afc426d041a242a7e03dbf5800e1eee Original-Change-Id: Id8ce1bd2f28d32898e99008e2a602d99a5c1098c Original-Signed-off-by: Robbie Zhang <robbie.zhang(a)intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/295012 Original-Reviewed-by: Wenkai Du <wenkai.du(a)intel.com> Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Tested-by: Wenkai Du <wenkai.du(a)intel.com> --- src/mainboard/intel/kunimitsu/gpio.h | 642 ++++++++----------------------- src/mainboard/intel/kunimitsu/ramstage.c | 7 +- 2 files changed, 171 insertions(+), 478 deletions(-) diff --git a/src/mainboard/intel/kunimitsu/gpio.h b/src/mainboard/intel/kunimitsu/gpio.h index 6a9cec1..0dbf782 100644 --- a/src/mainboard/intel/kunimitsu/gpio.h +++ b/src/mainboard/intel/kunimitsu/gpio.h @@ -18,483 +18,175 @@ * Foundation, Inc. */ -#ifndef _MAINBOARD_GPIO_H_ -#define _MAINBOARD_GPIO_H_ +#ifndef MAINBOARD_GPIO_H +#define MAINBOARD_GPIO_H #include <soc/gpio.h> -const GPIO_INIT_CONFIG mainboard_gpio_table[] = { -//Primary Well Group A -/* EC_PCH_RCIN */ -{ GPIO_LP_GPP_A0, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, -/* LPC_LAD_0 */ -{ GPIO_LP_GPP_A1, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, -/* LPC_LAD_1 */ -{ GPIO_LP_GPP_A2, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, - GpioOutDefault, GpioIntDis, GpioTermNone} }, -/* LPC_LAD_2 */ -{ GPIO_LP_GPP_A3, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, -/* LPC_LAD_3 */ -{ GPIO_LP_GPP_A4, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, -/* LPC_FRAME */ -{ GPIO_LP_GPP_A5, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, -/* LPC_SERIRQ */ -{ GPIO_LP_GPP_A6, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, -/* XDP_PREQ */ -{ GPIO_LP_GPP_A7, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, -/* LPC_CLKRUN */ -{ GPIO_LP_GPP_A8, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, -/* EC_LPC_CLK */ -{ GPIO_LP_GPP_A9, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, -/* PCH_LPC_CLK */ -{ GPIO_LP_GPP_A10, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, -/* EC_HID_INT */ -{ GPIO_LP_GPP_A11, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, -/* ISH_KB_PROX_INT */ -{ GPIO_LP_GPP_A12, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, -/* PCH_SUSPWRACB */ -{ GPIO_LP_GPP_A13, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, -/* PM_SUS_STAT */ -{ GPIO_LP_GPP_A14, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, -/* PCH_SUSACK */ -{ GPIO_LP_GPP_A15, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, -/* SD_1P8_SEL */ -{ GPIO_LP_GPP_A16, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, -/* SD_PWR_EN */ -{ GPIO_LP_GPP_A17, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, -/* GYRO INTERRUPT */ -{ GPIO_LP_GPP_A18, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, -/* ALS INTERRUPT / SNSR_HUB_INT */ -{ GPIO_LP_GPP_A19, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, -/* ISH_GYRO_DRDY/ACCEL INTERRUPT */ -{ GPIO_LP_GPP_A20, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, -/* SNSR_HUB_STANDBY_WAKE */ -{ GPIO_LP_GPP_A21, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, -{ GPIO_LP_GPP_A22, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, -{ GPIO_LP_GPP_A23, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, -//Primary Well Group B - -{ GPIO_LP_GPP_B0, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, -{ GPIO_LP_GPP_B1, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, -/* HSJ_MIC_DET */ -{ GPIO_LP_GPP_B2, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, - GpioOutDefault, GpioIntEdge, GpioResetDeep, GpioTermNone} }, -/* TRACKPAD_INT */ -{ GPIO_LP_GPP_B3, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, - GpioOutDefault, (GpioIntApic | GpioIntLevel), GpioResetDeep, - GpioTermNone} }, -/* BT_RF_KILL */ -{ GPIO_LP_GPP_B4, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, - GpioOutHigh, GpioIntDis, GpioResetDeep, GpioTermNone} }, -{ GPIO_LP_GPP_B5, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, -/* WIFI_CLK_REQ */ -{ GPIO_LP_GPP_B6, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, - GpioOutDefault, GpioIntLevel, GpioResetDeep, GpioTermNone} }, -/* KEPLR_CLK_REQ/VIDEO_CLK_REQ */ -{ GPIO_LP_GPP_B7, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, - GpioOutDefault, GpioIntLevel, GpioResetDeep, GpioTermNone} }, -{ GPIO_LP_GPP_B8, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, - GpioOutDefault, GpioIntLevel, GpioResetDeep, GpioTermNone} }, -/* SSD_CLK_REQ/CLK_REQ_SSD */ -{ GPIO_LP_GPP_B9, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, - GpioOutDefault, GpioIntLevel, GpioResetDeep, GpioTermNone} }, -{ GPIO_LP_GPP_B10, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, - GpioOutDefault, GpioIntLevel, GpioResetDeep, GpioTermNone} }, -/* MPHY_EXT_PWR_GATE */ -{ GPIO_LP_GPP_B11, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, - GpioOutDefault, GpioIntLevel, GpioResetDeep, GpioTermNone} }, -/* PM_SLP_S0 */ -{ GPIO_LP_GPP_B12, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, - GpioOutHigh, GpioIntDis, GpioResetDeep, GpioTermNone} }, -/* PCH_PLT_RST */ -{ GPIO_LP_GPP_B13, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, - GpioOutHigh, GpioIntDis, GpioResetDeep, GpioTermNone} }, -{ GPIO_LP_GPP_B14, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, - GpioOutDefault, GpioIntLevel, GpioResetDeep, GpioTermNone} }, -/* WWAN_DISABLE */ -{ GPIO_LP_GPP_B15, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, - GpioOutLow, GpioIntDis, GpioResetDeep, GpioTermNone} }, -/* WLAN_PCIE_WAKE */ -{ GPIO_LP_GPP_B16, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, - GpioOutDefault, GpioIntEdge, GpioResetDeep, GpioTermNone} }, -/* SSD_PCIE_WAKE */ -{ GPIO_LP_GPP_B17, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, -{ GPIO_LP_GPP_B18, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, - GpioOutDefault, GpioIntLevel, GpioResetDeep, GpioTermNone} }, -/* CCODEC_SPI_CS */ -{ GPIO_LP_GPP_B19, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, -/* CODEC_SPI_CLK */ -{ GPIO_LP_GPP_B20, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, -/* CODEC_SPI_MISO */ -{ GPIO_LP_GPP_B21, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, -/* CODEC_SPI_MOSI */ -{ GPIO_LP_GPP_B22, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, -{ GPIO_LP_GPP_B23, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, - GpioOutDefault, GpioIntLevel, GpioResetDeep, GpioTermNone} }, -//Primary Well Group C -/* SMB_CLK */ -{ GPIO_LP_GPP_C0, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, -/* SMB_DATA */ -{ GPIO_LP_GPP_C1, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, -{ GPIO_LP_GPP_C2, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, -/* M2_WWAN_PWREN */ -{ GPIO_LP_GPP_C3, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, - GpioOutLow, GpioIntDis, GpioResetDeep, GpioTermNone} }, -{ GPIO_LP_GPP_C4, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, -{ GPIO_LP_GPP_C5, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, - GpioOutLow, GpioIntDis, GpioResetDeep, GpioTermNone} }, -/* EC_IN_RW */ -{ GPIO_LP_GPP_C6, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, - GpioOutDefault, GpioIntLevel, GpioResetDeep, GpioTermNone} }, -/* USB_CTL */ -{ GPIO_LP_GPP_C7, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, - GpioOutHigh, GpioIntDis, GpioResetDeep, GpioTermNone} }, -{ GPIO_LP_GPP_C8, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, -{ GPIO_LP_GPP_C9, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, -/* NFC_RST* */ -{ GPIO_LP_GPP_C10, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, -/* EN_PP3300_KEPLER */ -{ GPIO_LP_GPP_C11, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, - GpioOutHigh, GpioIntDis, GpioResetDeep, GpioTermWpd20K} }, -/* PCH_MEM_CFG0 */ -{ GPIO_LP_GPP_C12, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, -/* PCH_MEM_CFG1 */ -{ GPIO_LP_GPP_C13, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, -/* PCH_MEM_CFG2 */ -{ GPIO_LP_GPP_C14, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, -/* PCH_MEM_CFG3 */ -{ GPIO_LP_GPP_C15, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, -/* I2C0_SDA */ -{ GPIO_LP_GPP_C16, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermWpu5K} }, -/* I2C0_SCL */ -{ GPIO_LP_GPP_C17, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermWpu5K} }, -/* I2C1_SDA */ -{ GPIO_LP_GPP_C18, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, -/* I2C1_SCL */ -{ GPIO_LP_GPP_C19, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, -/* GD_UART2_RXD */ -{ GPIO_LP_GPP_C20, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, -/* GD_UART2_TXD */ -{ GPIO_LP_GPP_C21, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, -/* TCH_PNL_PWREN */ -{ GPIO_LP_GPP_C22, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, - GpioOutHigh, GpioIntDis, GpioResetDeep, GpioTermNone} }, -/* SCREW_SPI_WP_STATUS */ -{ GPIO_LP_GPP_C23, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, - GpioOutDefault, GpioIntLevel, GpioResetDeep, GpioTermWpu20K} }, - -// Primary Well Group D -/* ITCH_SPI_CS */ -{ GPIO_LP_GPP_D0, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, -/* ITCH_SPI_CLK */ -{ GPIO_LP_GPP_D1, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, -/* ITCH_SPI_MISO */ -{ GPIO_LP_GPP_D2, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, -/* CAM_FLASH_STROBE */ -{ GPIO_LP_GPP_D4, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, -/* EN_PP3300_DX_EMMC */ -{ GPIO_LP_GPP_D5, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, -/* EN_PP1800_DX_EMMC */ -{ GPIO_LP_GPP_D6, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, -/* SH_I2C1_SDA */ -{ GPIO_LP_GPP_D7, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, -/* SH_I2C1_SCL */ -{ GPIO_LP_GPP_D8, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, -{ GPIO_LP_GPP_D9, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, -/* USB_A0_ILIM_SEL */ -{ GPIO_LP_GPP_D10, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, - GpioOutLow, GpioIntDis, GpioResetDeep, GpioTermNone} }, -/* USB_A1_ILIM_SEL */ -{ GPIO_LP_GPP_D11, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, - GpioOutLow, GpioIntDis, GpioResetDeep, GpioTermNone} }, -/* EN_PP3300_DX_CAM */ -{ GPIO_LP_GPP_D12, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, -/* EN_PP1800_DX_AUDIO */ -{ GPIO_LP_GPP_D13, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, -/* WWAN_WAKE* */ -{ GPIO_LP_GPP_D14, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, - GpioOutDefault, GpioIntEdge, GpioResetDeep, GpioTermNone} }, -{ GPIO_LP_GPP_D15, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, -{ GPIO_LP_GPP_D16, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, -/* DMIC_CLK_1 */ -{ GPIO_LP_GPP_D17, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, -/* DMIC_DATA_1 */ -{ GPIO_LP_GPP_D18, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, -/* DMIC_CLK_0 */ -{ GPIO_LP_GPP_D19, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, -/* DMIC_DATA_0 */ -{ GPIO_LP_GPP_D20, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, -/* ITCH_SPI_D2 */ -{ GPIO_LP_GPP_D21, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, -/* ITCH_SPI_D3 */ -{ GPIO_LP_GPP_D22, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, -/* I2S_MCLK */ -{ GPIO_LP_GPP_D23, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, -//Primary Well Group E -/* SPI_TPM_IRQ */ -{ GPIO_LP_GPP_E0, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, - GpioOutDefault, GpioIntEdge, GpioResetDeep, GpioTermNone} }, -{ GPIO_LP_GPP_E1, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, -/* SSD_PEDET */ -{ GPIO_LP_GPP_E2, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, -{ GPIO_LP_GPP_E3, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirInOut, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, -{ GPIO_LP_GPP_E4, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, -{ GPIO_LP_GPP_E5, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, -/* SSD_SATA_DEVSLP */ -{ GPIO_LP_GPP_E6, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, - GpioOutHigh, GpioIntDis, GpioResetDeep, GpioTermNone} }, -/* TCH_PNL_INTR* */ -{ GPIO_LP_GPP_E7, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, - GpioOutDefault, (GpioIntApic | GpioIntLevel), - GpioResetDeep, GpioTermNone} }, -{ GPIO_LP_GPP_E8, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, -/* USB2_OC_0 */ -{ GPIO_LP_GPP_E9, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, - GpioOutDefault, GpioIntLevel, GpioResetDeep, GpioTermNone} }, -/* USB2_OC_1 */ -{ GPIO_LP_GPP_E10, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, - GpioOutDefault, GpioIntLevel, GpioResetDeep, GpioTermNone} }, -/* USB2_OC_2 */ -{ GPIO_LP_GPP_E11, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, - GpioOutDefault, GpioIntLevel, GpioResetDeep, GpioTermNone} }, -/* USB2_OC_3 */ -{ GPIO_LP_GPP_E12, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, - GpioOutDefault, GpioIntLevel, GpioResetDeep, GpioTermNone} }, -/* DDI1_HPD */ -{ GPIO_LP_GPP_E13, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, - GpioOutDefault, GpioIntLevel, GpioResetDeep, GpioTermNone} }, -/* DDI2_HPD */ -{ GPIO_LP_GPP_E14, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, - GpioOutDefault, GpioIntLevel, GpioResetDeep, GpioTermNone} }, -/* EC_SMI */ -{ GPIO_LP_GPP_E15, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, - GpioOutDefault, GpioIntEdge, GpioResetDeep, GpioTermNone} }, -/* EC_SCI */ -{ GPIO_LP_GPP_E16, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, - GpioOutDefault, GpioIntEdge, GpioResetDeep, GpioTermNone} }, -/* EDP_HPD */ -{ GPIO_LP_GPP_E17, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, - GpioOutDefault, GpioIntLevel, GpioResetDeep, GpioTermNone} }, -{ GPIO_LP_GPP_E18, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, -{ GPIO_LP_GPP_E19, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, -{ GPIO_LP_GPP_E20, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, -{ GPIO_LP_GPP_E21, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, -{ GPIO_LP_GPP_E22, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, -/* TCH_PNL_RST */ -{ GPIO_LP_GPP_E23, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, - GpioIntDis, GpioResetDeep, GpioTermNone} }, -//Primary Well Group F -/* I2S2_SCLK */ -{ GPIO_LP_GPP_F0, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirInOut, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, -/* I2S2_SFRM */ -{ GPIO_LP_GPP_F1, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirInOut, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, -/* I2S2_TXD */ -{ GPIO_LP_GPP_F2, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, -/* I2S2_RXD */ -{ GPIO_LP_GPP_F3, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, -{ GPIO_LP_GPP_F4, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, -{ GPIO_LP_GPP_F5, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, -{ GPIO_LP_GPP_F6, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, -{ GPIO_LP_GPP_F7, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, -/* I2C4_SDA */ -{ GPIO_LP_GPP_F8, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, -/* I2C4_SDA */ -{ GPIO_LP_GPP_F9, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, -/* AUDIO_IRQ */ -{ GPIO_LP_GPP_F10, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, - GpioOutDefault, GpioIntApic | GpioIntEdge, GpioResetDeep, GpioTermNone} }, -/* AUDIO_SW_INT* */ -{ GPIO_LP_GPP_F11, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirInInv, - GpioOutDefault, GpioIntApic | GpioIntEdge, GpioResetDeep, GpioTermNone} }, -/* EMMC_CMD */ -{ GPIO_LP_GPP_F12, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, -/* EMMC_D_0 */ -{ GPIO_LP_GPP_F13, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, -/* EMMC_D_1 */ -{ GPIO_LP_GPP_F14, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, -/* EMMC_D_2 */ -{ GPIO_LP_GPP_F15, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, -/* EMMC_D_3 */ -{ GPIO_LP_GPP_F16, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, -/* EMMC_D_4 */ -{ GPIO_LP_GPP_F17, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, -/* EMMC_D_5 */ -{ GPIO_LP_GPP_F18, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, -/* EMMC_D_6 */ -{ GPIO_LP_GPP_F19, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, -/* EMMC_D_7 */ -{ GPIO_LP_GPP_F20, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, -/* EMMC_RCLK */ -{ GPIO_LP_GPP_F21, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, -/* EMMC_CLK */ -{ GPIO_LP_GPP_F22, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, -/* USIM_DET */ -{ GPIO_LP_GPP_F23, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, -//Primary Well Group G -/* SD_CMD */ -{ GPIO_LP_GPP_G0, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, -/* SD_D_0 */ -{ GPIO_LP_GPP_G1, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, -/* SD_D_1 */ -{ GPIO_LP_GPP_G2, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, -/* SD_D_2 */ -{ GPIO_LP_GPP_G3, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, -/* SD_D_3 */ -{ GPIO_LP_GPP_G4, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, -/* SD_CD */ -{ GPIO_LP_GPP_G5, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, -/* SD_CLK */ -{ GPIO_LP_GPP_G6, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, - GpioOutDefault, GpioIntEdge, GpioResetDeep, GpioTermNone} }, -/* SD_WP */ -{ GPIO_LP_GPP_G7, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, - -//Deep Sleep Well Group -/* PCH_BATLOW */ -{ GPIO_LP_GPD0, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, -/* EC_PCH_ACPRESENT */ -{ GPIO_LP_GPD1, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, - GpioOutDefault, GpioIntLevel, GpioResetDeep, GpioTermNone} }, -/* EC_PCH_WAKE */ -{ GPIO_LP_GPD2, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, - GpioOutDefault, GpioIntEdge, GpioResetDeep, GpioTermNone} }, -/* EC_PCH_PWRBTN */ -{ GPIO_LP_GPD3, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, - GpioOutDefault, GpioIntLevel, GpioResetDeep, GpioTermNone} }, -/* PM_SLP_S3 */ -{ GPIO_LP_GPD4, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, - GpioOutHigh, GpioIntDis, GpioResetDeep, GpioTermNone} }, -/* PM_SLP_S4 */ -{ GPIO_LP_GPD5, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, - GpioOutHigh, GpioIntDis, GpioResetDeep, GpioTermNone} }, -/* PCH_SLP_SA */ -{ GPIO_LP_GPD6, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, -/* USB_WAKEOUT_INTRUDET */ -{ GPIO_LP_GPD7, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, -/* PM_SUSCLK */ -{ GPIO_LP_GPD8, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, GpioOutLow, - GpioIntDis, GpioResetDeep, GpioTermNone} }, -/* PCH_SLP_WLAN */ -{ GPIO_LP_GPD9, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, -/* PCH_SLP_S5 */ -{ GPIO_LP_GPD10, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, -/* PM_LANPHY_ENABLE */ -{ GPIO_LP_GPD11, { GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone} }, -{ END_OF_GPIO_TABLE, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirNone, - GpioOutDefault, GpioIntDis, GpioResetPwrGood, GpioTermNone} }, +static const struct pad_config gpio_table[] = { +/* EC_PCH_RCIN */ PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), +/* LPC_LAD_0 */ PAD_CFG_NF(GPP_A1, NONE, DEEP, NF1), +/* LPC_LAD_1 */ PAD_CFG_NF(GPP_A2, NONE, DEEP, NF1), +/* LPC_LAD_2 */ PAD_CFG_NF(GPP_A3, NONE, DEEP, NF1), +/* LPC_LAD_3 */ PAD_CFG_NF(GPP_A4, NONE, DEEP, NF1), +/* LPC_FRAME */ PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), +/* LPC_SERIRQ */ PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), +/* PIRQA# */ /* GPP_A7 */ +/* LPC_CLKRUN */ PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), +/* EC_LPC_CLK */ PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1), +/* PCH_LPC_CLK */ /* GPP_A10 */ +/* EC_HID_INT */ /* GPP_A11 */ +/* ISH_KB_PROX_INT */ PAD_CFG_GPO(GPP_A12, 0, DEEP), +/* PCH_SUSPWRACB */ PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), +/* PM_SUS_STAT */ PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), +/* PCH_SUSACK */ PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1), +/* SD_1P8_SEL */ PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), +/* SD_PWR_EN */ PAD_CFG_NF(GPP_A17, NONE, DEEP, NF1), +/* ACCEL INTERRUPT */ PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), +/* ISH_GP1 */ /* GPP_A19 */ +/* GYRO_DRDY */ PAD_CFG_NF(GPP_A20, NONE, DEEP, NF1), +/* FLIP_ACCEL_INT */ PAD_CFG_NF(GPP_A21, NONE, DEEP, NF1), +/* GYRO_INT */ PAD_CFG_NF(GPP_A22, NONE, DEEP, NF1), +/* ISH_GP5 */ /* GPP_A23 */ +/* CORE_VID0 */ /* GPP_B0 */ +/* CORE_VID1 */ /* GPP_B1 */ +/* HSJ_MIC_DET */ PAD_CFG_GPI(GPP_B2, NONE, DEEP), +/* TRACKPAD_INT */ PAD_CFG_GPI_APIC(GPP_B3, NONE, DEEP), +/* BT_RF_KILL */ PAD_CFG_GPO(GPP_B4, 0, DEEP), +/* SRCCLKREQ0# */ /* GPP_B5 */ +/* WIFI_CLK_REQ */ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), +/* KEPLR_CLK_REQ */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), +/* SRCCLKREQ3# */ /* GPP_B8 */ +/* SSD_CLK_REQ */ PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), +/* SRCCLKREQ5# */ /* GPP_B10 */ +/* MPHY_EXT_PWR_GATE */ PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1), +/* PM_SLP_S0 */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), +/* PCH_PLT_RST */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), +/* GPP_B_14_SPKR */ PAD_CFG_GPI(GPP_B14, NONE, DEEP), +/* GSPI0_CS# */ /* GPP_B15 */ +/* WLAN_PCIE_WAKE */ PAD_CFG_GPI(GPP_B16, NONE, DEEP), +/* SSD_PCIE_WAKE */ PAD_CFG_GPI(GPP_B17, NONE, DEEP), +/* GSPI0_MOSI */ /* GPP_B18 */ +/* CCODEC_SPI_CS */ PAD_CFG_NF(GPP_B19, NONE, DEEP, NF1), +/* CODEC_SPI_CLK */ PAD_CFG_NF(GPP_B20, NONE, DEEP, NF1), +/* CODEC_SPI_MISO */ PAD_CFG_NF(GPP_B21, NONE, DEEP, NF1), +/* CODEC_SPI_MOSI */ PAD_CFG_NF(GPP_B22, NONE, DEEP, NF1), +/* SM1ALERT# */ /* GPP_B23 */ +/* SMB_CLK */ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), +/* SMB_DATA */ PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), +/* SMBALERT# */ PAD_CFG_GPO(GPP_C2, 0, DEEP), +/* M2_WWAN_PWREN */ PAD_CFG_GPO(GPP_C3, 0, DEEP), +/* SML0DATA */ /* GPP_C4 */ +/* SML0ALERT# */ /* GPP_C5 */ +/* EC_IN_RW */ PAD_CFG_GPI(GPP_C6, NONE, DEEP), +/* USB_CTL */ PAD_CFG_GPO(GPP_C7, 1, DEEP), +/* UART0_RXD */ /* GPP_C8 */ +/* UART0_TXD */ /* GPP_C9 */ +/* NFC_RST* */ PAD_CFG_GPO(GPP_C10, 0, DEEP), +/* EN_PP3300_KEPLER */ PAD_CFG_TERM_GPO(GPP_C11, 1, 20K_PD, DEEP), +/* PCH_MEM_CFG0 */ PAD_CFG_GPI(GPP_C12, NONE, DEEP), +/* PCH_MEM_CFG1 */ PAD_CFG_GPI(GPP_C13, NONE, DEEP), +/* PCH_MEM_CFG2 */ PAD_CFG_GPI(GPP_C14, NONE, DEEP), +/* PCH_MEM_CFG3 */ PAD_CFG_GPI(GPP_C15, NONE, DEEP), +/* I2C0_SDA */ PAD_CFG_NF(GPP_C16, 5K_PU, DEEP, NF1), +/* I2C0_SCL */ PAD_CFG_NF(GPP_C17, 5K_PU, DEEP, NF1), +/* I2C1_SDA */ PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), +/* I2C1_SCL */ PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), +/* GD_UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), +/* GD_UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), +/* TCH_PNL_PWREN */ PAD_CFG_GPO(GPP_C22, 1, DEEP), +/* SPI_WP_STATUS */ PAD_CFG_GPI(GPP_C23, 20K_PU, DEEP), +/* ITCH_SPI_CS */ /* GPP_D0 */ +/* ITCH_SPI_CLK */ /* GPP_D1 */ +/* ITCH_SPI_MISO_1 */ /* GPP_D2 */ +/* ITCH_SPI_MISO_0 */ /* GPP_D3 */ +/* CAM_FLASH_STROBE */ PAD_CFG_NF(GPP_D4, NONE, DEEP, NF1), +/* EN_PP3300_DX_EMMC */ PAD_CFG_GPO(GPP_D5, 1, DEEP), +/* EN_PP1800_DX_EMMC */ PAD_CFG_GPO(GPP_D6, 1, DEEP), +/* SH_I2C1_SDA */ PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1), +/* SH_I2C1_SCL */ PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1), + PAD_CFG_GPO(GPP_D9, 0, DEEP), +/* USB_A0_ILIM_SEL */ PAD_CFG_GPO(GPP_D10, 1, DEEP), +/* USB_A1_ILIM_SEL */ PAD_CFG_GPO(GPP_D11, 1, DEEP), +/* EN_PP3300_DX_CAM */ PAD_CFG_GPO(GPP_D12, 1, DEEP), +/* EN_PP1800_DX_AUDIO */PAD_CFG_GPO(GPP_D13, 1, DEEP), +/* ISH_UART0_TXD */ /* GPP_D14 */ +/* ISH_UART0_RTS */ /* GPP_D15 */ +/* ISH_UART0_CTS */ /* GPP_D16 */ +/* DMIC_CLK_1 */ PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1), +/* DMIC_DATA_1 */ PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1), +/* DMIC_CLK_0 */ PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), +/* DMIC_DATA_0 */ PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1), +/* ITCH_SPI_D2 */ /* GPP_D21 */ +/* ITCH_SPI_D3 */ /* GPP_D22 */ +/* I2S_MCLK */ PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1), +/* SPI_TPM_IRQ */ PAD_CFG_GPI_APIC(GPP_E0, NONE, DEEP), +/* SATAXPCIE1 */ /* GPP_E1 */ +/* SSD_PEDET */ PAD_CFG_GPI(GPP_E2, NONE, DEEP), +/* CPU_GP0 */ /* GPP_E3 */ +/* SSD_SATA_DEVSLP */ PAD_CFG_GPO(GPP_E4, 0, DEEP), +/* SATA_DEVSLP1 */ /* GPP_E5 */ +/* SATA_DEVSLP2 */ /* GPP_E6 */ +/* TCH_PNL_INTR* */ PAD_CFG_GPI_APIC(GPP_E7, NONE, DEEP), +/* SATALED# */ /* GPP_E8 */ +/* USB2_OC_0 */ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), +/* USB2_OC_1 */ PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), +/* USB2_OC_2 */ PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1), +/* USB2_OC_3 */ PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1), +/* DDI1_HPD */ PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), +/* DDI2_HPD */ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), +/* EC_SMI */ PAD_CFG_GPI_ACPI_SMI(GPP_E15, NONE, DEEP, YES), +/* EC_SCI */ PAD_CFG_GPI_ACPI_SCI(GPP_E16, NONE, DEEP, YES), +/* EDP_HPD */ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), +/* DDPB_CTRLCLK */ PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1), +/* DDPB_CTRLDATA */ PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1), +/* DDPC_CTRLCLK */ PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1), +/* DDPC_CTRLDATA */ PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1), +/* DDPD_CTRLCLK */ PAD_CFG_GPI(GPP_E22, NONE, DEEP), +/* TCH_PNL_RST */ PAD_CFG_GPO(GPP_E23, 1, DEEP), +/* I2S2_SCLK */ PAD_CFG_GPI(GPP_F0, NONE, DEEP), +/* I2S2_SFRM */ PAD_CFG_GPI(GPP_F1, NONE, DEEP), +/* I2S2_TXD */ PAD_CFG_GPI(GPP_F2, NONE, DEEP), +/* I2S2_RXD */ PAD_CFG_GPI(GPP_F3, NONE, DEEP), +/* I2C2_SDA */ /* GPP_F4 */ +/* I2C2_SCL */ /* GPP_F5 */ +/* I2C3_SDA */ /* GPP_F6 */ +/* I2C3_SCL */ /* GPP_F7 */ +/* I2C4_SDA */ PAD_CFG_NF(GPP_F8, NONE, DEEP, NF1), +/* I2C4_SDA */ PAD_CFG_NF(GPP_F9, NONE, DEEP, NF1), +/* AUDIO_IRQ */ PAD_CFG_GPI_APIC(GPP_F10, NONE, DEEP), +/* I2C5_SCL */ /* GPP_F11 */ +/* EMMC_CMD */ PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1), +/* EMMC_DATA0 */ PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1), +/* EMMC_DATA1 */ PAD_CFG_NF(GPP_F14, NONE, DEEP, NF1), +/* EMMC_DATA2 */ PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1), +/* EMMC_DATA3 */ PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1), +/* EMMC_DATA4 */ PAD_CFG_NF(GPP_F17, NONE, DEEP, NF1), +/* EMMC_DATA5 */ PAD_CFG_NF(GPP_F18, NONE, DEEP, NF1), +/* EMMC_DATA6 */ PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), +/* EMMC_DATA7 */ PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), +/* EMMC_RCLK */ PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), +/* EMMC_CLK */ PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1), + /* GPP_F23 */ +/* SD_CMD */ PAD_CFG_NF(GPP_G0, NONE, DEEP, NF1), +/* SD_DATA0 */ PAD_CFG_NF(GPP_G1, NONE, DEEP, NF1), +/* SD_DATA1 */ PAD_CFG_NF(GPP_G2, NONE, DEEP, NF1), +/* SD_DATA2 */ PAD_CFG_NF(GPP_G3, NONE, DEEP, NF1), +/* SD_DATA3 */ PAD_CFG_NF(GPP_G4, NONE, DEEP, NF1), +/* SD_CD# */ PAD_CFG_NF(GPP_G5, NONE, DEEP, NF1), +/* SD_CLK */ PAD_CFG_NF(GPP_G6, NONE, DEEP, NF1), +/* SD_WP */ PAD_CFG_NF(GPP_G7, NONE, DEEP, NF1), +/* PCH_BATLOW */ PAD_CFG_NF(GPD0, NONE, DEEP, NF1), +/* EC_PCH_ACPRESENT */ PAD_CFG_NF(GPD1, NONE, DEEP, NF1), +/* EC_PCH_WAKE */ PAD_CFG_NF(GPD2, NONE, DEEP, NF1), +/* EC_PCH_PWRBTN */ PAD_CFG_NF(GPD3, NONE, DEEP, NF1), +/* PM_SLP_S3# */ PAD_CFG_NF(GPD4, NONE, DEEP, NF1), +/* PM_SLP_S4# */ PAD_CFG_NF(GPD5, NONE, DEEP, NF1), +/* PM_SLP_SA# */ PAD_CFG_NF(GPD6, NONE, DEEP, NF1), + /* GPD7 */ +/* PM_SUSCLK */ PAD_CFG_NF(GPD8, NONE, DEEP, NF1), +/* PCH_SLP_WLAN# */ /* GPD9 */ +/* PM_SLP_S5# */ PAD_CFG_NF(GPD10, NONE, DEEP, NF1), +/* LANPHYC */ /* GPD11 */ }; #endif diff --git a/src/mainboard/intel/kunimitsu/ramstage.c b/src/mainboard/intel/kunimitsu/ramstage.c index 34fac28..563c715 100644 --- a/src/mainboard/intel/kunimitsu/ramstage.c +++ b/src/mainboard/intel/kunimitsu/ramstage.c @@ -13,11 +13,12 @@ * GNU General Public License for more details. */ -#include "gpio.h" #include <soc/ramstage.h> +#include "gpio.h" void mainboard_silicon_init_params(SILICON_INIT_UPD *params) { - /*update gpio table*/ - params->GpioTablePtr = (UINT32 *)mainboard_gpio_table; + /* Configure pads prior to SiliconInit() in case there's any + * dependencies during hardware initialization. */ + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); }

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Patch merged into coreboot/master: intel/skylake: gpio macro adding - gpio output with term and 20k pd
by gerrit＠coreboot.org 29 Aug '15

29 Aug '15

the following patch was just integrated into master: commit 1f79be1f52bafde0caf87127dd2ab648aa07b7cd Author: robbie zhang <robbie.zhang(a)intel.com> Date: Fri Aug 21 09:39:55 2015 -0700 intel/skylake: gpio macro adding - gpio output with term and 20k pd This is also required for kunimitsu fab3 gpio settings. BUG=None BRANCH=None TEST=Built and booted kunimitsu. Change-Id: I61d71fe4576cd57d17f21aecb188cd5b7fdecca0 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Original-Commit-Id: f65c2618a47c71aad277fb2a11b17ade0a97e5f8 Original-Change-Id: Iebf272b5cc3e67ec35259f5b3e9041ab4cdaa207 Original-Signed-off-by: Robbie Zhang <robbie.zhang(a)intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/294757 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/11424 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See http://review.coreboot.org/11424 for details. -gerrit

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coreboot-gerrit August 2015