coreboot-gerrit August 2015

coreboot-gerrit@coreboot.org

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814 discussions

Patch set updated for coreboot: google/glados: Remove unnecessary check for mainboard_ec_init()
by Patrick Georgi 29 Aug '15

29 Aug '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11435 -gerrit commit 42483871ac3a6d59c5766cac24d43036fc0b83d1 Author: Martin Roth <martinroth(a)chromium.org> Date: Tue Aug 25 11:26:33 2015 -0600 google/glados: Remove unnecessary check for mainboard_ec_init() mainboard_ec_init() wasn't getting run due to an invalid Kconfig symbol. This check isn't required as the Kconfig option for the EC is forced to be enabled, and the function should always be run. BRANCH=none BUG=none TEST=Rebuilt glados mainboard. Change-Id: I2c4a33d80533a19b02b83b3aaa6a3386e927f1c7 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Original-Commit-Id: edd8c7a0666208b35ee81f57ec2626390958dfb7 Original-Change-Id: I2a92fd28347455c09ecf2119788ca9b6a97a11de Original-Signed-off-by: Martin Roth <martinroth(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/295143 Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/mainboard/google/glados/mainboard.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/src/mainboard/google/glados/mainboard.c b/src/mainboard/google/glados/mainboard.c index 5e48f17..ac4a2ad 100644 --- a/src/mainboard/google/glados/mainboard.c +++ b/src/mainboard/google/glados/mainboard.c @@ -25,8 +25,7 @@ static void mainboard_init(device_t dev) { - if (IS_ENABLED(CONFIG_GOOGLE_CHROME_EC)) - mainboard_ec_init(); + mainboard_ec_init(); } /*

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Patch set updated for coreboot: intel/kunimitsu: port the change from glados for enabling reading recovery mode.
by Patrick Georgi 29 Aug '15

29 Aug '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11434 -gerrit commit c19e727b3dc6f783f1d104f18283170677670365 Author: robbie zhang <robbie.zhang(a)intel.com> Date: Mon Aug 24 16:41:09 2015 -0700 intel/kunimitsu: port the change from glados for enabling reading recovery mode. BUG=chrome-os-partner:43683 BRANCH=none TEST=build and boot on kunimits and successfully enter recovery mode by pressing “Esc + refresh + Power” keys. Change-Id: Id25b9f2195f1caaa8b46967b4b5d4abdab48d6cc Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Original-Commit-Id: 96b1c295448b412a5662afc729fdd37294d3cb61 Original-Change-Id: I9f650b28b0a86b631ffdfe6de5d58d18e48a0a22 Original-Signed-off-by: robbie zhang <robbie.zhang(a)intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/295138 Original-Tested-by: Wenkai Du <wenkai.du(a)intel.com> Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/mainboard/intel/kunimitsu/chromeos.c | 17 +++++++++++++++-- 1 file changed, 15 insertions(+), 2 deletions(-) diff --git a/src/mainboard/intel/kunimitsu/chromeos.c b/src/mainboard/intel/kunimitsu/chromeos.c index 66d1a42..66be521 100644 --- a/src/mainboard/intel/kunimitsu/chromeos.c +++ b/src/mainboard/intel/kunimitsu/chromeos.c @@ -22,10 +22,10 @@ #include <console/console.h> #include <device/device.h> #include <device/pci.h> +#include <ec/google/chromeec/ec.h> #include <soc/gpio.h> #include <string.h> #include <vendorcode/google/chromeos/chromeos.h> - #include "gpio.h" #include "ec.h" @@ -69,7 +69,20 @@ int get_developer_mode_switch(void) int get_recovery_mode_switch(void) { - return 0; + /* Check for dedicated recovery switch first. */ + if (google_chromeec_get_switches() & EC_SWITCH_DEDICATED_RECOVERY) + return 1; + + /* Otherwise check if the EC has posted the keyboard recovery event. */ + return !!(google_chromeec_get_events_b() & + EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY)); +} + +int clear_recovery_mode_switch(void) +{ + /* Clear keyboard recovery event. */ + return google_chromeec_clear_events_b( + EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY)); } int get_write_protect_state(void)

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Patch set updated for coreboot: intel/kunimitsu: Adding mainboard init to enable SCI event
by Patrick Georgi 29 Aug '15

29 Aug '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11433 -gerrit commit 229409d5dd3e9f02662f7e2b740d8390d59e57f3 Author: pchandri <preetham.chandrian(a)intel.com> Date: Mon Aug 24 13:44:19 2015 -0700 intel/kunimitsu: Adding mainboard init to enable SCI event BUG=chrome-os-partner:44470 BRANCH=None TEST=Builds and Boots on FAB3 (Kunimitsu) Change-Id: I479fe60dcbdd51f4fa5bca857b4a166f958a54d5 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Original-Commit-Id: e88efdd8766e2846a650eb75709b29035c406bf8 Original-Change-Id: I9fe5697d31e188fca48b14fb76e71631f2974c2d Original-Signed-off-by: pchandri <preetham.chandrian(a)intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/295218 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/mainboard/intel/kunimitsu/mainboard.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/src/mainboard/intel/kunimitsu/mainboard.c b/src/mainboard/intel/kunimitsu/mainboard.c index 5c5bd69..40becdc 100644 --- a/src/mainboard/intel/kunimitsu/mainboard.c +++ b/src/mainboard/intel/kunimitsu/mainboard.c @@ -20,6 +20,23 @@ */ #include <device/device.h> +#include <stdlib.h> +#include "ec.h" + +static void mainboard_init(device_t dev) +{ + mainboard_ec_init(); +} + +/* + * mainboard_enable is executed as first thing after + * enumerate_buses(). + */ +static void mainboard_enable(device_t dev) +{ + dev->ops->init = mainboard_init; +} struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, };

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Patch merged into coreboot/master: intel/kunimitsu: fix SCI handling
by gerrit＠coreboot.org 29 Aug '15

29 Aug '15

the following patch was just integrated into master: commit 3b169252ea7c8f16a955890964b30eae19547dd6 Author: Wenkai Du <wenkai.du(a)intel.com> Date: Mon Aug 24 10:31:30 2015 -0700 intel/kunimitsu: fix SCI handling Ported below patch from glados to kunimitsu: glados: Abstract board GPIO configuration in gpio.h Original-change-Id: I3f1754012158dd5c7d5bbd6e07e40850f21af56d Originally-signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Originally-reviewed-on: https://chromium-review.googlesource.com/293942 BUG=chrome-os-partner:40828 BRANCH=none TEST=Verify that acpi interrupts are incrementing on kunimitsu. Change-Id: Ifeddb34289b6e62c936cf6c542906d6e7ef96ddd Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Original-Commit-Id: 8ff0dd2dcdf6485f0171fb967f7de3015cf4e4ad Original-Change-Id: I1f270a03a241d2285639f79854d04059d2c2c99f Original-Signed-off-by: Wenkai Du <wenkai.du(a)intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/295048 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-by: Robbie Zhang <robbie.zhang(a)intel.com> Original-Tested-by: Robbie Zhang <robbie.zhang(a)intel.com> Reviewed-on: http://review.coreboot.org/11432 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See http://review.coreboot.org/11432 for details. -gerrit

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Patch merged into coreboot/master: intel/kunimitsu: fix kepler probing
by gerrit＠coreboot.org 29 Aug '15

29 Aug '15

the following patch was just integrated into master: commit 1105fad6eaae6e4cfb599cffeaca576084719ce8 Author: Wenkai Du <wenkai.du(a)intel.com> Date: Fri Aug 21 13:11:00 2015 -0700 intel/kunimitsu: fix kepler probing The patch was ported from commit: glados: fix kepler probing BUG=chrome-os-partner:44326 BRANCH=None TEST=Built and booted kunimitsu. lscpi shows the device on bus 2. Change-Id: I423e5d8414cb9864f6ff2f2ce7cd925baeb242eb Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Original-Commit-Id: 37bf5b7594a6784b3acb65410c670300e582e7aa Original-Original-change-Id: I7fe4a707f9321b7bdec4b4be729c5d0dcce65f6e Original-Originally-signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Original-Originally-reviewed-on: https://chromium-review.googlesource.com/294810 Original-Change-Id: I2fb620ebff5b477a1a457a354c65229ad1092cae Original-Signed-off-by: Wenkai Du <wenkai.du(a)intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/295164 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/11431 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See http://review.coreboot.org/11431 for details. -gerrit

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Patch merged into coreboot/master: intel/skylake: Add support for DPTF
by gerrit＠coreboot.org 29 Aug '15

29 Aug '15

the following patch was just integrated into master: commit a0f515354be6b852eea9e4dfcb99198523e52579 Author: Shilpa Sreeramalu <shilpa.sreeramalu(a)intel.com> Date: Mon Jun 22 21:48:39 2015 +0530 intel/skylake: Add support for DPTF This patch adds the ASL files with the DPTF related settings and the thermal devices enabled in the SOC. It also enables the DPTF setting at the global NVS level. BRANCH=None BUG=chrome-os-partner:40855 TEST=Built for kunimitsu board. Tested to see that the thermal devices and the participants are enumerated and can be seen in the /sys/bus/platform/devices. Also checked the temperature readings of the cooling devices and the thermal zones enumerated in the /sys/class/thermal. Change-Id: I8ad044eaf1ad488fb1682097da83b40d2bede414 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Original-Commit-Id: 7624eeca19b4f286b30c3d4ac5b44c5e9619c2c7 Original-Change-Id: I0d92ef42cff5567ea6fc566730588802d8549ce0 Original-Signed-off-by: Shilpa Sreeramalu <shilpa.sreeramalu(a)intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/293391 Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Commit-Queue: Naveenkrishna Ch <naveenkrishna.ch(a)intel.com> Reviewed-on: http://review.coreboot.org/11430 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See http://review.coreboot.org/11430 for details. -gerrit

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Patch merged into coreboot/master: intel/kunimitsu: Enable and support for DPTF
by gerrit＠coreboot.org 29 Aug '15

29 Aug '15

the following patch was just integrated into master: commit 91a192f6d0e5706595e7b2bf4501aec2c8a674f0 Author: Shilpa Sreeramalu <shilpa.sreeramalu(a)intel.com> Date: Mon Jun 22 21:54:51 2015 +0530 intel/kunimitsu: Enable and support for DPTF This patch includes the DPTF specific ASL files in the main DSDT definition and enables the CPU thermal participant device in the device tree. It also enables the DPTF flag in the global NVS table.It also adds the ASL settings specfic to the mainboard. BRANCH=None BUG=chrome-os-partner:40855 TEST=Built for kunimitsu board. Tested to see that the thermal devices and the participants are enumerated and can be seen in the /sys/bus/platform/devices. Also checked the temperature readings of the cooling devices and the thermal zones enumerated in the /sys/class/thermal. Change-Id: I5fb28e4480648eab39cc9b13ed55eae1d3db4d42 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Original-Commit-Id: 54f7f33a12eb5744d6108e362fa1d078fe838b3c Original-Change-Id: I82527989919bd4f3c49fb58dfc9463f1c1bd3353 Original-Signed-off-by: Shilpa Sreeramalu <shilpa.sreeramalu(a)intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/284821 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/294650 Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Commit-Queue: Naveenkrishna Ch <naveenkrishna.ch(a)intel.com> Reviewed-on: http://review.coreboot.org/11429 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See http://review.coreboot.org/11429 for details. -gerrit

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Patch merged into coreboot/master: intel/kunimitsu: clean up ec smi and make EC_SMI_L functional
by gerrit＠coreboot.org 29 Aug '15

29 Aug '15

the following patch was just integrated into master: commit 17d2fb8dc191933d7c1edceeee145ed000df11a5 Author: robbie zhang <robbie.zhang(a)intel.com> Date: Fri Aug 21 12:56:04 2015 -0700 intel/kunimitsu: clean up ec smi and make EC_SMI_L functional forward port of "glados: make EC_SMI_L functional", commit 50ed38feba58f BUG=None BRANCH=None TEST=Built and booted kunimitsu. CQ-DEPEND=CL:295012 Change-Id: I41daeb8b729f2de117b5d57c460925437460e50a Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Original-Commit-Id: d9308c0b8eb05c756d88dc0c3d761c9e76d07e08 Original-Change-Id: Ia90c70d21af75d0f0da2af2b4437ccf26659a157 Original-Signed-off-by: robbie zhang <robbie.zhang(a)intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/295045 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Tested-by: Wenkai Du <wenkai.du(a)intel.com> Reviewed-on: http://review.coreboot.org/11428 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See http://review.coreboot.org/11428 for details. -gerrit

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Patch set updated for coreboot: intel/kunimitsu: clean up ec smi and make EC_SMI_L functional
by Patrick Georgi 29 Aug '15

29 Aug '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11428 -gerrit commit a0d0ada1f3f2ab35d043b28103e37c4c1a48b37b Author: robbie zhang <robbie.zhang(a)intel.com> Date: Fri Aug 21 12:56:04 2015 -0700 intel/kunimitsu: clean up ec smi and make EC_SMI_L functional forward port of "glados: make EC_SMI_L functional", commit 50ed38feba58f BUG=None BRANCH=None TEST=Built and booted kunimitsu. CQ-DEPEND=CL:295012 Change-Id: I41daeb8b729f2de117b5d57c460925437460e50a Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Original-Commit-Id: d9308c0b8eb05c756d88dc0c3d761c9e76d07e08 Original-Change-Id: Ia90c70d21af75d0f0da2af2b4437ccf26659a157 Original-Signed-off-by: robbie zhang <robbie.zhang(a)intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/295045 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Tested-by: Wenkai Du <wenkai.du(a)intel.com> --- src/mainboard/intel/kunimitsu/ec.h | 4 ++-- src/mainboard/intel/kunimitsu/smihandler.c | 5 ++--- 2 files changed, 4 insertions(+), 5 deletions(-) diff --git a/src/mainboard/intel/kunimitsu/ec.h b/src/mainboard/intel/kunimitsu/ec.h index 9da9d9f..9c8a9d1 100644 --- a/src/mainboard/intel/kunimitsu/ec.h +++ b/src/mainboard/intel/kunimitsu/ec.h @@ -22,11 +22,11 @@ #define MAINBOARD_EC_H #include <ec/google/chromeec/ec_commands.h> +#include <soc/gpio.h> /* GPP_E16 is EC_SCI_L */ #define EC_SCI_GPI 16 /* TODO: Update this */ -/* GPP_E15 is EC_SMI_L */ -#define EC_SMI_GPI 15 /* TODO: Update this */ +#define EC_SMI_GPI GPP_E15 #define MAINBOARD_EC_SCI_EVENTS \ (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED) |\ diff --git a/src/mainboard/intel/kunimitsu/smihandler.c b/src/mainboard/intel/kunimitsu/smihandler.c index 0529ba1..fe8e70c 100644 --- a/src/mainboard/intel/kunimitsu/smihandler.c +++ b/src/mainboard/intel/kunimitsu/smihandler.c @@ -74,10 +74,9 @@ static u8 mainboard_smi_ec(void) return cmd; } -/* gpi_sts is GPIO 47:32 */ -void mainboard_smi_gpi(u32 gpi_sts) +void mainboard_smi_gpi_handler(const struct gpi_status *sts) { - if (gpi_sts & (1 << EC_SMI_GPI)) { + if (gpi_status_get(sts, EC_SMI_GPI)) { /* Process all pending events */ while (mainboard_smi_ec() != 0) ;

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Patch set updated for coreboot: intel/kunimitsu: fix SCI handling
by Patrick Georgi 29 Aug '15

29 Aug '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11432 -gerrit commit e8c43021551387782c1830f933c1d491723eed81 Author: Wenkai Du <wenkai.du(a)intel.com> Date: Mon Aug 24 10:31:30 2015 -0700 intel/kunimitsu: fix SCI handling Ported below patch from glados to kunimitsu: glados: Abstract board GPIO configuration in gpio.h Original-change-Id: I3f1754012158dd5c7d5bbd6e07e40850f21af56d Originally-signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Originally-reviewed-on: https://chromium-review.googlesource.com/293942 BUG=chrome-os-partner:40828 BRANCH=none TEST=Verify that acpi interrupts are incrementing on kunimitsu. Change-Id: Ifeddb34289b6e62c936cf6c542906d6e7ef96ddd Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Original-Commit-Id: 8ff0dd2dcdf6485f0171fb967f7de3015cf4e4ad Original-Change-Id: I1f270a03a241d2285639f79854d04059d2c2c99f Original-Signed-off-by: Wenkai Du <wenkai.du(a)intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/295048 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-by: Robbie Zhang <robbie.zhang(a)intel.com> Original-Tested-by: Robbie Zhang <robbie.zhang(a)intel.com> --- src/mainboard/intel/kunimitsu/acpi/chromeos.asl | 10 +++++++--- src/mainboard/intel/kunimitsu/acpi/ec.asl | 3 ++- src/mainboard/intel/kunimitsu/acpi/mainboard.asl | 6 +++++- src/mainboard/intel/kunimitsu/chromeos.c | 3 +++ src/mainboard/intel/kunimitsu/ec.h | 5 ----- src/mainboard/intel/kunimitsu/gpio.h | 15 +++++++++++++++ src/mainboard/intel/kunimitsu/smihandler.c | 1 + 7 files changed, 33 insertions(+), 10 deletions(-) diff --git a/src/mainboard/intel/kunimitsu/acpi/chromeos.asl b/src/mainboard/intel/kunimitsu/acpi/chromeos.asl index c6665f9..d3ab569 100644 --- a/src/mainboard/intel/kunimitsu/acpi/chromeos.asl +++ b/src/mainboard/intel/kunimitsu/acpi/chromeos.asl @@ -18,7 +18,11 @@ * Foundation, Inc. */ -Name (OIPG, Package() { - Package () { 0x0001, 0, 0xFFFFFFFF, "INT3437:00" }, // no recovery button - Package () { 0x0003, 1, 16, "INT3437:00" }, // firmware write protect +#include "../gpio.h" + +Name (OIPG, Package () { + /* No physical recovery GPIO. */ + Package () { 0x0001, 0, 0xFFFFFFFF, "INT344B:00" }, + /* Firmware write protect GPIO. */ + Package () { 0x0003, 1, GPIO_PCH_WP, "INT344B:00" }, }) diff --git a/src/mainboard/intel/kunimitsu/acpi/ec.asl b/src/mainboard/intel/kunimitsu/acpi/ec.asl index 9ef2553..63c45de 100644 --- a/src/mainboard/intel/kunimitsu/acpi/ec.asl +++ b/src/mainboard/intel/kunimitsu/acpi/ec.asl @@ -18,7 +18,8 @@ */ /* mainboard configuration */ -#include <mainboard/intel/kunimitsu/ec.h> +#include "../ec.h" +#include "../gpio.h" /* Enable EC backed PD MCU device in ACPI */ #define EC_ENABLE_PD_MCU_DEVICE diff --git a/src/mainboard/intel/kunimitsu/acpi/mainboard.asl b/src/mainboard/intel/kunimitsu/acpi/mainboard.asl index aa752f9..4492a19 100644 --- a/src/mainboard/intel/kunimitsu/acpi/mainboard.asl +++ b/src/mainboard/intel/kunimitsu/acpi/mainboard.asl @@ -18,6 +18,8 @@ * Foundation, Inc. */ +#include "../gpio.h" + #define BOARD_TRACKPAD_IRQ 0x33 #define BOARD_TOUCHSCREEN_IRQ 0x1f @@ -36,11 +38,13 @@ Scope (\_SB) { Return (\_SB.PCI0.LPCB.EC0.LIDS) } + + Name (_PRW, Package () { GPE_EC_WAKE, 5 }) } Device (PWRB) { - Name(_HID, EisaId("PNP0C0C")) + Name (_HID, EisaId("PNP0C0C")) } } /* diff --git a/src/mainboard/intel/kunimitsu/chromeos.c b/src/mainboard/intel/kunimitsu/chromeos.c index 6767705..66d1a42 100644 --- a/src/mainboard/intel/kunimitsu/chromeos.c +++ b/src/mainboard/intel/kunimitsu/chromeos.c @@ -26,6 +26,9 @@ #include <string.h> #include <vendorcode/google/chromeos/chromeos.h> +#include "gpio.h" +#include "ec.h" + #if ENV_RAMSTAGE #include <boot/coreboot_tables.h> diff --git a/src/mainboard/intel/kunimitsu/ec.h b/src/mainboard/intel/kunimitsu/ec.h index 9c8a9d1..6408815 100644 --- a/src/mainboard/intel/kunimitsu/ec.h +++ b/src/mainboard/intel/kunimitsu/ec.h @@ -22,11 +22,6 @@ #define MAINBOARD_EC_H #include <ec/google/chromeec/ec_commands.h> -#include <soc/gpio.h> - -/* GPP_E16 is EC_SCI_L */ -#define EC_SCI_GPI 16 /* TODO: Update this */ -#define EC_SMI_GPI GPP_E15 #define MAINBOARD_EC_SCI_EVENTS \ (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED) |\ diff --git a/src/mainboard/intel/kunimitsu/gpio.h b/src/mainboard/intel/kunimitsu/gpio.h old mode 100644 new mode 100755 index f1166c8..0ab36f1 --- a/src/mainboard/intel/kunimitsu/gpio.h +++ b/src/mainboard/intel/kunimitsu/gpio.h @@ -21,8 +21,21 @@ #ifndef MAINBOARD_GPIO_H #define MAINBOARD_GPIO_H +#include <soc/gpe.h> #include <soc/gpio.h> +/* EC in RW */ +#define GPIO_EC_IN_RW GPP_C6 + +/* BIOS Flash Write Protect */ +#define GPIO_PCH_WP GPP_C23 +/* EC wake is LAN_WAKE# which is a special DeepSX wake pin */ +#define GPE_EC_WAKE GPE0_LAN_WAK +/* GPP_E16 is EC_SCI_L. GPP_E group is routed to dword 2 in the GPE0 block. */ +#define EC_SCI_GPI GPE0_DW2_16 +#define EC_SMI_GPI GPP_E15 + +#ifndef __ACPI__ /* Pad configuration in ramstage. */ static const struct pad_config gpio_table[] = { /* EC_PCH_RCIN */ PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), @@ -198,3 +211,5 @@ static const struct pad_config early_gpio_table[] = { }; #endif + +#endif diff --git a/src/mainboard/intel/kunimitsu/smihandler.c b/src/mainboard/intel/kunimitsu/smihandler.c index fe8e70c..1662144 100644 --- a/src/mainboard/intel/kunimitsu/smihandler.c +++ b/src/mainboard/intel/kunimitsu/smihandler.c @@ -28,6 +28,7 @@ #include <soc/pm.h> #include <soc/smm.h> #include "ec.h" +#include "gpio.h" int mainboard_io_trap_handler(int smif) {

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coreboot-gerrit August 2015