coreboot-gerrit August 2015

coreboot-gerrit@coreboot.org

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814 discussions

New patch to review for coreboot: drivers/intel/fsp_1_1: Remove useless #ifndef/#error pairs
by Alexandru Gagniuc 30 Aug '15

30 Aug '15

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11461 -gerrit commit 788ea1e17b3c1980fd2d3339f7d0a2e3229072b8 Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Sat Aug 29 17:48:01 2015 -0700 drivers/intel/fsp_1_1: Remove useless #ifndef/#error pairs The #error messages only say that "CONFIG_* must be defined", which conveys no more information that the compiler or assembler failing when it encounters an undefined CONFIG_* symbol. Change-Id: I6058474d4cd454cfc20290650425d379f388abd9 Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- src/drivers/intel/fsp1_1/cache_as_ram.inc | 18 ------------------ src/drivers/intel/fsp1_1/fsp_util.c | 4 ---- 2 files changed, 22 deletions(-) diff --git a/src/drivers/intel/fsp1_1/cache_as_ram.inc b/src/drivers/intel/fsp1_1/cache_as_ram.inc index f56d841..6af30ce 100644 --- a/src/drivers/intel/fsp1_1/cache_as_ram.inc +++ b/src/drivers/intel/fsp1_1/cache_as_ram.inc @@ -33,24 +33,6 @@ #include <cpu/x86/post_code.h> #include <cbmem.h> -#ifndef CONFIG_FSP_LOC -# error "CONFIG_FSP_LOC must be set." -#endif - -#ifndef CONFIG_POST_IO -# error "CONFIG_POST_IO must be set." -#endif - -#if IS_ENABLED(CONFIG_POST_IO) -# ifndef CONFIG_POST_IO_PORT -# error "CONFIG_POST_IO_PORT must be set." -# endif -#endif - -#ifndef CONFIG_CPU_MICROCODE_CBFS_LOC -# error "CONFIG_CPU_MICROCODE_CBFS_LOC must be set." -#endif - #define LHLT_DELAY 0x50000 /* I/O delay between post codes on failure */ /* diff --git a/src/drivers/intel/fsp1_1/fsp_util.c b/src/drivers/intel/fsp1_1/fsp_util.c index 51ddc67..e5624b3 100644 --- a/src/drivers/intel/fsp1_1/fsp_util.c +++ b/src/drivers/intel/fsp1_1/fsp_util.c @@ -38,10 +38,6 @@ FSP_INFO_HEADER *find_fsp(void) } fsp_ptr; u32 *image_id; -#ifndef CONFIG_FSP_LOC -#error "CONFIG_FSP_LOC must be set." -#endif - for (;;) { /* Get the FSP binary base address in CBFS */ fsp_ptr.u8 = (u8 *)CONFIG_FSP_LOC;

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Patch set updated for coreboot: Kconfig: Remove EXPERT mode
by Alexandru Gagniuc 29 Aug '15

29 Aug '15

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11365 -gerrit commit f98cc525e51a50c5741a552c1e8506b096795344 Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Wed Aug 26 10:11:02 2015 -0400 Kconfig: Remove EXPERT mode After much consideration, and many years of an EXPERT mode sitting almost completely unused, we've seen that it doesn't work for us. There is no standard on what constitutes EXPERT, and most of coreboot's options Kconfig are expert-level. We even joked that not selecting "EXPERT" should prevent coreboot from compiling: @echo $(shell whoami) is not permitted to compile coreboot Change-Id: Ic22dd54a48190b81d711625efb6b9f3078f41778 Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- payloads/external/SeaBIOS/Kconfig | 1 - src/Kconfig | 11 ----------- src/device/Kconfig | 11 +++-------- src/northbridge/amd/amdfam10/Kconfig | 2 +- src/northbridge/amd/amdht/h3finit.c | 4 ++-- 5 files changed, 6 insertions(+), 23 deletions(-) diff --git a/payloads/external/SeaBIOS/Kconfig b/payloads/external/SeaBIOS/Kconfig index b2ff21e..699b986 100644 --- a/payloads/external/SeaBIOS/Kconfig +++ b/payloads/external/SeaBIOS/Kconfig @@ -18,7 +18,6 @@ endchoice config SEABIOS_PS2_TIMEOUT prompt "PS/2 keyboard controller initialization timeout (milliseconds)" default 0 - depends on EXPERT int help Some PS/2 keyboard controllers don't respond to commands immediately diff --git a/src/Kconfig b/src/Kconfig index 9c01687..2c75750 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -22,14 +22,6 @@ mainmenu "coreboot configuration" menu "General setup" -config EXPERT - bool "Expert mode" - help - This allows you to select certain advanced configuration options. - - Warning: Only enable this option if you really know what you are - doing! You have been warned! - config LOCALVERSION string "Local version string" help @@ -111,7 +103,6 @@ config CCACHE config FMD_GENPARSER bool "Generate flashmap descriptor parser using flex and bison" default n - depends on EXPERT help Enable this option if you are working on the flashmap descriptor parser and made changes to fmd_scanner.l or fmd_parser.y. @@ -121,7 +112,6 @@ config FMD_GENPARSER config SCONFIG_GENPARSER bool "Generate SCONFIG parser using flex and bison" default n - depends on EXPERT help Enable this option if you are working on the sconfig device tree parser and made changes to sconfig.l or sconfig.y. @@ -283,7 +273,6 @@ config BOOTBLOCK_SOURCE config SKIP_MAX_REBOOT_CNT_CLEAR bool "Do not clear reboot count after successful boot" default n - depends on EXPERT help Do not clear the reboot count immediately after successful boot. Set to allow the payload to control normal/fallback image recovery. diff --git a/src/device/Kconfig b/src/device/Kconfig index 39e612d..613461b 100644 --- a/src/device/Kconfig +++ b/src/device/Kconfig @@ -51,7 +51,7 @@ config VGA_ROM_RUN bool "Run VGA Option ROMs" default n if PAYLOAD_SEABIOS default y if !PAYLOAD_SEABIOS - depends on PCI && !MAINBOARD_DO_NATIVE_VGA_INIT && EXPERT + depends on PCI && !MAINBOARD_DO_NATIVE_VGA_INIT help Execute VGA Option ROMs in coreboot if found. This is required to enable PCI/AGP/PCI-E video cards when not using a SeaBIOS @@ -92,7 +92,7 @@ config ON_DEVICE_ROM_RUN bool "Run Option ROMs on PCI devices" default n if PAYLOAD_SEABIOS default y if !PAYLOAD_SEABIOS - depends on PCI && EXPERT + depends on PCI help Execute Option ROMs stored on PCI/PCIe/AGP devices in coreboot. @@ -165,17 +165,12 @@ config YABEL_PCI_FAKE_WRITING_OTHER_DEVICES_CONFIG config YABEL_VIRTMEM_LOCATION prompt "Location of YABEL's virtual memory" hex - depends on PCI_OPTION_ROM_RUN_YABEL && EXPERT + depends on PCI_OPTION_ROM_RUN_YABEL default 0x1000000 help YABEL requires 1MB memory for its CPU emulation. This memory is normally located at 16MB. -config YABEL_VIRTMEM_LOCATION - hex - depends on PCI_OPTION_ROM_RUN_YABEL && !EXPERT - default 0x1000000 - config YABEL_DIRECTHW prompt "Direct hardware access" bool diff --git a/src/northbridge/amd/amdfam10/Kconfig b/src/northbridge/amd/amdfam10/Kconfig index 13954d4..4d7147d 100644 --- a/src/northbridge/amd/amdfam10/Kconfig +++ b/src/northbridge/amd/amdfam10/Kconfig @@ -120,7 +120,7 @@ config SVI_HIGH_FREQ menu "HyperTransport setup" #could be implemented for K8 (NORTHBRIDGE_AMD_AMDK8) - depends on (NORTHBRIDGE_AMD_AMDFAM10) && EXPERT + depends on (NORTHBRIDGE_AMD_AMDFAM10) choice prompt "HyperTransport downlink width" diff --git a/src/northbridge/amd/amdht/h3finit.c b/src/northbridge/amd/amdht/h3finit.c index 0138cd9..849f4a8 100644 --- a/src/northbridge/amd/amdht/h3finit.c +++ b/src/northbridge/amd/amdht/h3finit.c @@ -1399,13 +1399,13 @@ static void selectOptimalWidthAndFrequency(sMainData *pDat) cbPCBFreqLimit = ht_speed_mhz_to_hw(pDat->HtBlock->ht_link_configuration->ht_speed_limit); cbPCBFreqLimit = min(cbPCBFreqLimit, cbPCBFreqLimit_NVRAM); -#if CONFIG_EXPERT && CONFIG_LIMIT_HT_DOWN_WIDTH_8 +#if CONFIG_LIMIT_HT_DOWN_WIDTH_8 cbPCBABDownstreamWidth = 8; #else cbPCBABDownstreamWidth = 16; #endif -#if CONFIG_EXPERT && CONFIG_LIMIT_HT_UP_WIDTH_8 +#if CONFIG_LIMIT_HT_UP_WIDTH_8 cbPCBBAUpstreamWidth = 8; #else cbPCBBAUpstreamWidth = 16;

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Patch set updated for coreboot: Kconfig: Don't 'select' options based on PAYLOAD_SEABIOS
by Alexandru Gagniuc 29 Aug '15

29 Aug '15

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11293 -gerrit commit 9e62b43062ebc31c53bab2e912a652a781904f2c Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Thu Aug 20 16:25:02 2015 -0400 Kconfig: Don't 'select' options based on PAYLOAD_SEABIOS This is just wrong. PAYLOAD_SEABIOS tells us nothing about whether or not the payload will actually be SeaBIOS: 1. PAYLOAD_SEABIOS, but payload changed with cbfstool 2. !PAYLOAD_SEABIOS, but an elf payload was added which is SeaBIOS et. cetera. Change-Id: I4c17e8dde20bf21537f542fda2dad7d3a1894862 Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- src/device/Kconfig | 4 ++-- src/mainboard/google/cyan/Kconfig | 2 -- src/mainboard/google/rambi/Kconfig | 2 -- src/mainboard/intel/strago/Kconfig | 2 -- src/soc/intel/broadwell/Kconfig | 2 -- src/soc/intel/skylake/Kconfig | 2 -- 6 files changed, 2 insertions(+), 12 deletions(-) diff --git a/src/device/Kconfig b/src/device/Kconfig index d780d13..39e612d 100644 --- a/src/device/Kconfig +++ b/src/device/Kconfig @@ -51,7 +51,7 @@ config VGA_ROM_RUN bool "Run VGA Option ROMs" default n if PAYLOAD_SEABIOS default y if !PAYLOAD_SEABIOS - depends on PCI && !PAYLOAD_SEABIOS && !MAINBOARD_DO_NATIVE_VGA_INIT || EXPERT + depends on PCI && !MAINBOARD_DO_NATIVE_VGA_INIT && EXPERT help Execute VGA Option ROMs in coreboot if found. This is required to enable PCI/AGP/PCI-E video cards when not using a SeaBIOS @@ -92,7 +92,7 @@ config ON_DEVICE_ROM_RUN bool "Run Option ROMs on PCI devices" default n if PAYLOAD_SEABIOS default y if !PAYLOAD_SEABIOS - depends on PCI && !PAYLOAD_SEABIOS || EXPERT + depends on PCI && EXPERT help Execute Option ROMs stored on PCI/PCIe/AGP devices in coreboot. diff --git a/src/mainboard/google/cyan/Kconfig b/src/mainboard/google/cyan/Kconfig index f3bb851..e4dc322 100644 --- a/src/mainboard/google/cyan/Kconfig +++ b/src/mainboard/google/cyan/Kconfig @@ -2,8 +2,6 @@ if BOARD_GOOGLE_CYAN config BOARD_SPECIFIC_OPTIONS def_bool y - select VGA_ROM_RUN if !PAYLOAD_SEABIOS - select ALWAYS_LOAD_OPROM if !PAYLOAD_SEABIOS select BOARD_ROMSIZE_KB_8192 select EC_GOOGLE_CHROMEEC select EC_GOOGLE_CHROMEEC_MEC diff --git a/src/mainboard/google/rambi/Kconfig b/src/mainboard/google/rambi/Kconfig index 1ad2d6d..825df9a 100644 --- a/src/mainboard/google/rambi/Kconfig +++ b/src/mainboard/google/rambi/Kconfig @@ -11,8 +11,6 @@ config BOARD_SPECIFIC_OPTIONS select HAVE_ACPI_RESUME select MAINBOARD_HAS_CHROMEOS select MAINBOARD_HAS_LPC_TPM - select VGA_ROM_RUN if !PAYLOAD_SEABIOS - select ALWAYS_LOAD_OPROM if !PAYLOAD_SEABIOS config CHROMEOS select CHROMEOS_VBNV_CMOS diff --git a/src/mainboard/intel/strago/Kconfig b/src/mainboard/intel/strago/Kconfig index 1d4d4d8..1512a46 100755 --- a/src/mainboard/intel/strago/Kconfig +++ b/src/mainboard/intel/strago/Kconfig @@ -2,8 +2,6 @@ if BOARD_INTEL_STRAGO config BOARD_SPECIFIC_OPTIONS def_bool y - select VGA_ROM_RUN if !PAYLOAD_SEABIOS - select ALWAYS_LOAD_OPROM if !PAYLOAD_SEABIOS select BOARD_ROMSIZE_KB_8192 select EC_GOOGLE_CHROMEEC select EC_GOOGLE_CHROMEEC_MEC diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig index 524366c..0106255 100644 --- a/src/soc/intel/broadwell/Kconfig +++ b/src/soc/intel/broadwell/Kconfig @@ -11,8 +11,6 @@ config CPU_SPECIFIC_OPTIONS select ARCH_VERSTAGE_X86_32 select ARCH_ROMSTAGE_X86_32 select ARCH_RAMSTAGE_X86_32 - select VGA_ROM_RUN if !PAYLOAD_SEABIOS - select ALWAYS_LOAD_OPROM if !PAYLOAD_SEABIOS select BACKUP_DEFAULT_SMM_REGION select CACHE_MRC_SETTINGS select MRC_SETTINGS_PROTECT diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index f42d3ab..9805b6d 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -11,8 +11,6 @@ config CPU_SPECIFIC_OPTIONS select ARCH_RAMSTAGE_X86_32 select ARCH_ROMSTAGE_X86_32 select ARCH_VERSTAGE_X86_32 - select VGA_ROM_RUN if !PAYLOAD_SEABIOS - select ALWAYS_LOAD_OPROM if !PAYLOAD_SEABIOS select BACKUP_DEFAULT_SMM_REGION select CACHE_MRC_SETTINGS select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM

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Patch merged into coreboot/master: intel/kunimitsu: Export EC_IN_RW for depthcharge/vboot
by gerrit＠coreboot.org 29 Aug '15

29 Aug '15

the following patch was just integrated into master: commit cf1c94d1bf033396afb8605d79996a03d918a9d0 Author: zhuo-hao <zhuo-hao.lee(a)intel.com> Date: Wed Aug 26 12:31:30 2015 +0800 intel/kunimitsu: Export EC_IN_RW for depthcharge/vboot Reference CL:294712 BUG=chrome-os-partner:43072,chrome-os-partner:43707 BRANCH=none TEST=build coreboot and boot on Kunimitsu Fab3.1 Change-Id: Ic89f3bcad1f4b4b1dfe39025a51bfcb97ad87158 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Original-Commit-Id: 1c73c1a345bb3ac397f2da2d14b25d688cc00a92 Original-Change-Id: If38fb37c092cbf4aaa339da6a777f2ba80e8cd2a Original-Signed-off-by: Zhuo-hao Lee <zhuo-hao.lee(a)intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/295514 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/11437 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See http://review.coreboot.org/11437 for details. -gerrit

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Patch merged into coreboot/master: intel/kunimitsu: port the change from glados for correctly reading lid switch and SPI write protect for fill_lb_gpios() to coreboot table.
by gerrit＠coreboot.org 29 Aug '15

29 Aug '15

the following patch was just integrated into master: commit fada85e655879efc3774fc602987b078bc20fb41 Author: robbie zhang <robbie.zhang(a)intel.com> Date: Tue Aug 25 16:13:53 2015 -0700 intel/kunimitsu: port the change from glados for correctly reading lid switch and SPI write protect for fill_lb_gpios() to coreboot table. BUG=chrome-os-partner:43707 BRANCH=none TEST=build and boot on kunimits Signed-off-by: robbie zhang <robbie.zhang(a)intel.com> Change-Id: I82cd3f74d0ac26e369ee4274b2c65f4f93c1fd3b Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Original-Commit-Id: 804a8a60951321e1b5b1d7ddacb97ddbe0cd7680 Original-Change-Id: I31ed6c0e48089b84ef9d52753484253a091d5aa5 Original-Reviewed-on: https://chromium-review.googlesource.com/295580 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Commit-Queue: Wenkai Du <wenkai.du(a)intel.com> Original-Tested-by: Wenkai Du <wenkai.du(a)intel.com> Reviewed-on: http://review.coreboot.org/11436 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See http://review.coreboot.org/11436 for details. -gerrit

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Patch merged into coreboot/master: google/glados: Remove unnecessary check for mainboard_ec_init()
by gerrit＠coreboot.org 29 Aug '15

29 Aug '15

the following patch was just integrated into master: commit 302aeb7a4ee10897d42298726b85e2d0bb26e788 Author: Martin Roth <martinroth(a)chromium.org> Date: Tue Aug 25 11:26:33 2015 -0600 google/glados: Remove unnecessary check for mainboard_ec_init() mainboard_ec_init() wasn't getting run due to an invalid Kconfig symbol. This check isn't required as the Kconfig option for the EC is forced to be enabled, and the function should always be run. BRANCH=none BUG=none TEST=Rebuilt glados mainboard. Change-Id: I2c4a33d80533a19b02b83b3aaa6a3386e927f1c7 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Original-Commit-Id: edd8c7a0666208b35ee81f57ec2626390958dfb7 Original-Change-Id: I2a92fd28347455c09ecf2119788ca9b6a97a11de Original-Signed-off-by: Martin Roth <martinroth(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/295143 Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/11435 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See http://review.coreboot.org/11435 for details. -gerrit

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Patch set updated for coreboot: intel/kunimitsu: Export EC_IN_RW for depthcharge/vboot
by Patrick Georgi 29 Aug '15

29 Aug '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11437 -gerrit commit 1a1b7057d77003ea4feba70b319cd89c1e9c999e Author: zhuo-hao <zhuo-hao.lee(a)intel.com> Date: Wed Aug 26 12:31:30 2015 +0800 intel/kunimitsu: Export EC_IN_RW for depthcharge/vboot Reference CL:294712 BUG=chrome-os-partner:43072,chrome-os-partner:43707 BRANCH=none TEST=build coreboot and boot on Kunimitsu Fab3.1 Change-Id: Ic89f3bcad1f4b4b1dfe39025a51bfcb97ad87158 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Original-Commit-Id: 1c73c1a345bb3ac397f2da2d14b25d688cc00a92 Original-Change-Id: If38fb37c092cbf4aaa339da6a777f2ba80e8cd2a Original-Signed-off-by: Zhuo-hao Lee <zhuo-hao.lee(a)intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/295514 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/mainboard/intel/kunimitsu/chromeos.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/src/mainboard/intel/kunimitsu/chromeos.c b/src/mainboard/intel/kunimitsu/chromeos.c index d2cfeb7..441a5c8 100644 --- a/src/mainboard/intel/kunimitsu/chromeos.c +++ b/src/mainboard/intel/kunimitsu/chromeos.c @@ -33,16 +33,11 @@ #if ENV_RAMSTAGE #include <boot/coreboot_tables.h> -#define GPIO_COUNT 6 - void fill_lb_gpios(struct lb_gpios *gpios) { - struct lb_gpio *gpio; - - gpios->size = sizeof(*gpios) + (GPIO_COUNT * sizeof(struct lb_gpio)); - gpios->count = GPIO_COUNT; + struct lb_gpio *start_gpio = gpios->gpios; + struct lb_gpio *gpio = start_gpio; - gpio = gpios->gpios; fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "write protect", get_write_protect_state()); fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "recovery", @@ -53,6 +48,11 @@ void fill_lb_gpios(struct lb_gpios *gpios) get_lid_switch()); fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "power", 0); fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "oprom", gfx_get_init_done()); + fill_lb_gpio(gpio++, GPIO_EC_IN_RW, ACTIVE_HIGH, "EC in RW", + gpio_get(GPIO_EC_IN_RW)); + + gpios->count = gpio - start_gpio; + gpios->size = sizeof(*gpios) + (gpios->count * sizeof(*gpio)); } #endif /* ENV_RAMSTAGE */

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Patch set updated for coreboot: intel/kunimitsu: port the change from glados for correctly reading lid switch and SPI write protect for fill_lb_gpios() to coreboot table.
by Patrick Georgi 29 Aug '15

29 Aug '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11436 -gerrit commit 871576e927e2fa5b60bc0208ba74a5c0ae5da813 Author: robbie zhang <robbie.zhang(a)intel.com> Date: Tue Aug 25 16:13:53 2015 -0700 intel/kunimitsu: port the change from glados for correctly reading lid switch and SPI write protect for fill_lb_gpios() to coreboot table. BUG=chrome-os-partner:43707 BRANCH=none TEST=build and boot on kunimits Signed-off-by: robbie zhang <robbie.zhang(a)intel.com> Change-Id: I82cd3f74d0ac26e369ee4274b2c65f4f93c1fd3b Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Original-Commit-Id: 804a8a60951321e1b5b1d7ddacb97ddbe0cd7680 Original-Change-Id: I31ed6c0e48089b84ef9d52753484253a091d5aa5 Original-Reviewed-on: https://chromium-review.googlesource.com/295580 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Commit-Queue: Wenkai Du <wenkai.du(a)intel.com> Original-Tested-by: Wenkai Du <wenkai.du(a)intel.com> --- src/mainboard/intel/kunimitsu/chromeos.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/src/mainboard/intel/kunimitsu/chromeos.c b/src/mainboard/intel/kunimitsu/chromeos.c index 66be521..d2cfeb7 100644 --- a/src/mainboard/intel/kunimitsu/chromeos.c +++ b/src/mainboard/intel/kunimitsu/chromeos.c @@ -23,6 +23,7 @@ #include <device/device.h> #include <device/pci.h> #include <ec/google/chromeec/ec.h> +#include <gpio.h> #include <soc/gpio.h> #include <string.h> #include <vendorcode/google/chromeos/chromeos.h> @@ -57,13 +58,13 @@ void fill_lb_gpios(struct lb_gpios *gpios) int get_lid_switch(void) { - /* Default to force open */ - return 1; + /* Read lid switch state from the EC. */ + return !!(google_chromeec_get_switches() & EC_SWITCH_LID_OPEN); } -/* The dev-switch is virtual */ int get_developer_mode_switch(void) { + /* No physical developer mode switch. */ return 0; } @@ -87,5 +88,6 @@ int clear_recovery_mode_switch(void) int get_write_protect_state(void) { - return 0; + /* Read PCH_WP GPIO. */ + return gpio_get(GPIO_PCH_WP); }

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Patch merged into coreboot/master: intel/kunimitsu: port the change from glados for enabling reading recovery mode.
by gerrit＠coreboot.org 29 Aug '15

29 Aug '15

the following patch was just integrated into master: commit c8dd59df9138dc2b4770865c76025bbdf76304ad Author: robbie zhang <robbie.zhang(a)intel.com> Date: Mon Aug 24 16:41:09 2015 -0700 intel/kunimitsu: port the change from glados for enabling reading recovery mode. BUG=chrome-os-partner:43683 BRANCH=none TEST=build and boot on kunimits and successfully enter recovery mode by pressing “Esc + refresh + Power” keys. Change-Id: Id25b9f2195f1caaa8b46967b4b5d4abdab48d6cc Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Original-Commit-Id: 96b1c295448b412a5662afc729fdd37294d3cb61 Original-Change-Id: I9f650b28b0a86b631ffdfe6de5d58d18e48a0a22 Original-Signed-off-by: robbie zhang <robbie.zhang(a)intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/295138 Original-Tested-by: Wenkai Du <wenkai.du(a)intel.com> Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/11434 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See http://review.coreboot.org/11434 for details. -gerrit

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Patch merged into coreboot/master: intel/kunimitsu: Adding mainboard init to enable SCI event
by gerrit＠coreboot.org 29 Aug '15

29 Aug '15

the following patch was just integrated into master: commit dfdd33eb53fd5abf90c8bbd2c66c2a187bd6a426 Author: pchandri <preetham.chandrian(a)intel.com> Date: Mon Aug 24 13:44:19 2015 -0700 intel/kunimitsu: Adding mainboard init to enable SCI event BUG=chrome-os-partner:44470 BRANCH=None TEST=Builds and Boots on FAB3 (Kunimitsu) Change-Id: I479fe60dcbdd51f4fa5bca857b4a166f958a54d5 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Original-Commit-Id: e88efdd8766e2846a650eb75709b29035c406bf8 Original-Change-Id: I9fe5697d31e188fca48b14fb76e71631f2974c2d Original-Signed-off-by: pchandri <preetham.chandrian(a)intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/295218 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/11433 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See http://review.coreboot.org/11433 for details. -gerrit

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coreboot-gerrit August 2015