coreboot-gerrit August 2015

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Patch set updated for coreboot: intel/skylake: gpio macro adding - gpio output with term and 20k pd
by Patrick Georgi 29 Aug '15

29 Aug '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11424 -gerrit commit 99082456d73e4cced92f1d712d4b233b5fc9644c Author: robbie zhang <robbie.zhang(a)intel.com> Date: Fri Aug 21 09:39:55 2015 -0700 intel/skylake: gpio macro adding - gpio output with term and 20k pd This is also required for kunimitsu fab3 gpio settings. BUG=None BRANCH=None TEST=Built and booted kunimitsu. Change-Id: I61d71fe4576cd57d17f21aecb188cd5b7fdecca0 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Original-Commit-Id: f65c2618a47c71aad277fb2a11b17ade0a97e5f8 Original-Change-Id: Iebf272b5cc3e67ec35259f5b3e9041ab4cdaa207 Original-Signed-off-by: Robbie Zhang <robbie.zhang(a)intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/294757 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/soc/intel/skylake/include/soc/gpio.h | 10 +++++++--- src/soc/intel/skylake/include/soc/gpio_defs.h | 1 + 2 files changed, 8 insertions(+), 3 deletions(-) diff --git a/src/soc/intel/skylake/include/soc/gpio.h b/src/soc/intel/skylake/include/soc/gpio.h index 4871c8c..56fd52e 100644 --- a/src/soc/intel/skylake/include/soc/gpio.h +++ b/src/soc/intel/skylake/include/soc/gpio.h @@ -113,12 +113,16 @@ void gpio_configure_pads(const struct pad_config *cfgs, size_t num); _PAD_CFG(pad_, term_, \ _DW0_VALS(rst_, RAW, NO, LEVEL, NO, NO, NO, NO, NO, NO, func_, NO, NO)) -/* General purpose output. By default no termination. */ -#define PAD_CFG_GPO(pad_, val_, rst_) \ - _PAD_CFG(pad_, NONE, \ +/* General purpose output with termination. */ +#define PAD_CFG_TERM_GPO(pad_, val_, term_, rst_) \ + _PAD_CFG(pad_, term_, \ _DW0_VALS(rst_, RAW, NO, LEVEL, NO, NO, NO, NO, NO, NO, GPIO, YES, NO) \ | PAD_FIELD_VAL(GPIOTXSTATE, val_)) +/* General purpose output. By default no termination. */ +#define PAD_CFG_GPO(pad_, val_, rst_) \ + PAD_CFG_TERM_GPO(pad_, val_, NONE, rst_) + /* General purpose input with no special IRQ routing. */ #define PAD_CFG_GPI(pad_, term_, rst_) \ _PAD_CFG_ATTRS(pad_, term_, \ diff --git a/src/soc/intel/skylake/include/soc/gpio_defs.h b/src/soc/intel/skylake/include/soc/gpio_defs.h index 09f5019..8b8a1c0 100644 --- a/src/soc/intel/skylake/include/soc/gpio_defs.h +++ b/src/soc/intel/skylake/include/soc/gpio_defs.h @@ -492,6 +492,7 @@ #define PAD_TERM_MASK 0xf #define PAD_TERM_NONE 0 #define PAD_TERM_5K_PD 2 +#define PAD_TERM_20K_PD 4 #define PAD_TERM_1K_PU 9 #define PAD_TERM_2K_PU 11 #define PAD_TERM_5K_PU 10

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Patch merged into coreboot/master: intel/skylake: Implement HW Sequence based WP status read functionality
by gerrit＠coreboot.org 29 Aug '15

29 Aug '15

the following patch was just integrated into master: commit 7a2defb2ddc0e2872f00bfcdc7c383ed89a55097 Author: Barnali Sarkar <barnali.sarkar(a)intel.com> Date: Wed Aug 19 14:15:32 2015 +0530 intel/skylake: Implement HW Sequence based WP status read functionality Early(romstage) SPI write protected status read(wpsr) functionality was broken causing 2 sec timeout issue.Implementing HW Seq based rd status operation in romstage. BRANCH=NONE BUG=chrome-os-partner:42115 TEST=Built for sklrvp and kunimitsu and tested using below command flashrom -p host --wp-enable [this should enable WP on flash chip] Read using romstage SPI.c. WPSR=0x80 (CB is reading Bit 7 as locked) flashrom -p host --wp-disable [this should disable WP on flash chip] Read using romstage SPI.c. WPSR=0x00 (CB is reading Bit 7 as unlocked) Change-Id: I79f6767d88f766be1b47adaf7c6e2fa368750d5a Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Original-Commit-Id: 4b798c44634581ebf7cdeea76c486e95e1f0a488 Original-Change-Id: I7e9b02e313b84765ddfef06724e9921550c4e677 Original-Signed-off-by: Subrata <subrata.banik(a)intel.com> Original-Signed-off-by: Barnali Sarkar <barnali.sarkar(a)intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/294445 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/11423 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See http://review.coreboot.org/11423 for details. -gerrit

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Patch set updated for coreboot: intel/skylake: Implement HW Sequence based WP status read functionality
by Patrick Georgi 29 Aug '15

29 Aug '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11423 -gerrit commit 427c9e46b89527260954b1d78b95b1a8d00816fa Author: Barnali Sarkar <barnali.sarkar(a)intel.com> Date: Wed Aug 19 14:15:32 2015 +0530 intel/skylake: Implement HW Sequence based WP status read functionality Early(romstage) SPI write protected status read(wpsr) functionality was broken causing 2 sec timeout issue.Implementing HW Seq based rd status operation in romstage. BRANCH=NONE BUG=chrome-os-partner:42115 TEST=Built for sklrvp and kunimitsu and tested using below command flashrom -p host --wp-enable [this should enable WP on flash chip] Read using romstage SPI.c. WPSR=0x80 (CB is reading Bit 7 as locked) flashrom -p host --wp-disable [this should disable WP on flash chip] Read using romstage SPI.c. WPSR=0x00 (CB is reading Bit 7 as unlocked) Change-Id: I79f6767d88f766be1b47adaf7c6e2fa368750d5a Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Original-Commit-Id: 4b798c44634581ebf7cdeea76c486e95e1f0a488 Original-Change-Id: I7e9b02e313b84765ddfef06724e9921550c4e677 Original-Signed-off-by: Subrata <subrata.banik(a)intel.com> Original-Signed-off-by: Barnali Sarkar <barnali.sarkar(a)intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/294445 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/soc/intel/skylake/romstage/spi.c | 130 +++++------------------------------ 1 file changed, 19 insertions(+), 111 deletions(-) diff --git a/src/soc/intel/skylake/romstage/spi.c b/src/soc/intel/skylake/romstage/spi.c index 206350b..be6db41 100644 --- a/src/soc/intel/skylake/romstage/spi.c +++ b/src/soc/intel/skylake/romstage/spi.c @@ -18,100 +18,21 @@ * Foundation, Inc. */ -#include <arch/io.h> -#include <console/console.h> -#include <delay.h> -#include <soc/spi.h> +#include <flash_controller.h> #include <soc/romstage.h> -#define SPI_DELAY 10 /* 10us */ -#define SPI_RETRY 200000 /* 2s */ - -static int early_spi_read_block(u32 offset, u8 size, u8 *buffer) -{ - u32 *ptr32 = (u32 *)buffer; - u32 i; - u16 hsfs, hsfc; - void *spibar = get_spi_bar(); - - /* Clear status bits */ - hsfs = read16(spibar + SPIBAR_HSFS); - write16(spibar + SPIBAR_HSFS, hsfs | SPIBAR_HSFS_AEL | - SPIBAR_HSFS_FCERR | SPIBAR_HSFS_FDONE); - - if (read16(spibar + SPIBAR_HSFS) & SPIBAR_HSFS_SCIP) { - printk(BIOS_ERR, "SPI ERROR: transaction in progress\n"); - return -1; - } - - /* Set flash address */ - write32(spibar + SPIBAR_FADDR, offset); - - /* Setup read transaction */ - write16(spibar + SPIBAR_HSFC, SPIBAR_HSFC_BYTE_COUNT(size) | - SPIBAR_HSFC_CYCLE_READ); - - /* Start transactinon */ - hsfc = read16(spibar + SPIBAR_HSFC); - write16(spibar + SPIBAR_HSFC, hsfc | SPIBAR_HSFC_GO); - - /* Wait for completion */ - for (i = 0; i < SPI_RETRY; i++) { - if (read16(spibar + SPIBAR_HSFS) & SPIBAR_HSFS_SCIP) { - /* Cycle in progress, wait 1ms */ - udelay(SPI_DELAY); - continue; - } - - if (read16(spibar + SPIBAR_HSFS) & SPIBAR_HSFS_AEL) { - printk(BIOS_ERR, "SPI ERROR: Access Error\n"); - return -1; - - } - - if (read16(spibar + SPIBAR_HSFS) & SPIBAR_HSFS_FCERR) { - printk(BIOS_ERR, "SPI ERROR: Flash Cycle Error\n"); - return -1; - } - break; - } - - if (i >= SPI_RETRY) { - printk(BIOS_ERR, "SPI ERROR: Timeout\n"); - return -1; - } - - /* Read the data */ - for (i = 0; i < size; i += sizeof(u32)) { - if (size-i >= 4) { - /* reading >= dword */ - *ptr32++ = read32(spibar + - SPIBAR_FDATA(i/sizeof(u32))); - } else { - /* reading < dword */ - u8 j, *ptr8 = (u8 *)ptr32; - u32 temp; - - temp = read32(spibar + - SPIBAR_FDATA(i/sizeof(u32))); - for (j = 0; j < (size-i); j++) { - *ptr8++ = temp & 0xff; - temp >>= 8; - } - } - } - - return size; -} - int early_spi_read(u32 offset, u32 size, u8 *buffer) { u32 current = 0; + spi_init(); while (size > 0) { u8 count = (size < 64) ? size : 64; - if (early_spi_read_block(offset + current, count, - buffer + current) < 0) + /* sending NULL for spiflash struct parameter since we are not + * calling HWSEQ read() call via Probe. + */ + if (pch_hwseq_read(NULL, offset + current, count, + buffer + current) != 0) return -1; size -= count; current += count; @@ -122,37 +43,24 @@ int early_spi_read(u32 offset, u32 size, u8 *buffer) /* * Minimal set of commands to read WPSR from SPI. - * Don't use this code outside romstage -- it trashes the opmenu table. * Returns 0 on success, < 0 on failure. */ int early_spi_read_wpsr(u8 *sr) { - int retry; - void *spibar = get_spi_bar(); - - /* No address associated with rdsr */ - write8(spibar + SPIBAR_OPTYPE, 0x0); - /* Setup opcode[0] = read wpsr */ - write8(spibar + SPIBAR_OPMENU_LOWER, 0x5); + uint8_t rdsr; + int ret = 0; - /* Start transaction */ - write16(spibar + SPIBAR_SSFC, SPIBAR_SSFC_DATA | SPIBAR_SSFC_GO); - - /* Wait for error / complete status */ - for (retry = SPI_RETRY; retry; retry--) { - u16 status = read16(spibar + SPIBAR_SSFS); - if (status & SPIBAR_SSFS_ERROR) { - printk(BIOS_ERR, "SPI rdsr failed\n"); - return -1; - } else if (status & SPIBAR_SSFS_DONE) { - break; - } + spi_init(); - udelay(SPI_DELAY); - } - /* Flash protected range 0 register bit 31 indicates WP - * Bit 31[WPE] 1= WP Enable 0= WP Disable + /* sending NULL for spiflash struct parameter since we are not + * calling HWSEQ read_status() call via Probe. */ - *sr = (read32(spibar + SPIBAR_FPR(0)) & SPIBAR_FPR_WPE) >> 24; + ret = pch_hwseq_read_status(NULL, &rdsr); + if (ret) { + printk(BIOS_ERR, "SPI rdsr failed\n"); + return ret; + } + *sr = rdsr & WPSR_MASK_SRP0_BIT; + return 0; }

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Patch merged into coreboot/master: intel/skylake: Implemented generic SPI driver for ROM/RAMSTAGE access.
by gerrit＠coreboot.org 29 Aug '15

29 Aug '15

the following patch was just integrated into master: commit d92f6127e109e5bb595b6726a9f7adb61eac2d9d Author: Subrata <subrata.banik(a)intel.com> Date: Tue Jul 14 16:46:40 2015 +0530 intel/skylake: Implemented generic SPI driver for ROM/RAMSTAGE access. Created generic library to implement SPI read, write, erase and read status functionality for both ROMSTAGE and RAMSTAGE access. BRANCH=NONE BUG=chrome-os-partner:42115 TEST=Built for sklrvp and kunimitsu and verify SPI read, write, erase success from ELOG. Change-Id: Idf4ffdb550e2a3b87059554e8825a1182b448a8a Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Original-Commit-Id: 74907352931db78802298fe7280a39913a37f0c2 Original-Change-Id: Ib08da1b8825e2e88641acbac3863b926ec48afd9 Original-Signed-off-by: Barnali Sarkar <barnali.sarkar(a)intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/294444 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Tested-by: Subrata Banik <subrata.banik(a)intel.com> Original-Commit-Queue: Subrata Banik <subrata.banik(a)intel.com> Reviewed-on: http://review.coreboot.org/11422 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See http://review.coreboot.org/11422 for details. -gerrit

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Patch set updated for coreboot: intel/skylake: Implemented generic SPI driver for ROM/RAMSTAGE access.
by Patrick Georgi 29 Aug '15

29 Aug '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11422 -gerrit commit ac0f03e5b5790f2428bd381e9657da3067db4d24 Author: Subrata <subrata.banik(a)intel.com> Date: Tue Jul 14 16:46:40 2015 +0530 intel/skylake: Implemented generic SPI driver for ROM/RAMSTAGE access. Created generic library to implement SPI read, write, erase and read status functionality for both ROMSTAGE and RAMSTAGE access. BRANCH=NONE BUG=chrome-os-partner:42115 TEST=Built for sklrvp and kunimitsu and verify SPI read, write, erase success from ELOG. Change-Id: Idf4ffdb550e2a3b87059554e8825a1182b448a8a Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Original-Commit-Id: 74907352931db78802298fe7280a39913a37f0c2 Original-Change-Id: Ib08da1b8825e2e88641acbac3863b926ec48afd9 Original-Signed-off-by: Barnali Sarkar <barnali.sarkar(a)intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/294444 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Tested-by: Subrata Banik <subrata.banik(a)intel.com> Original-Commit-Queue: Subrata Banik <subrata.banik(a)intel.com> --- src/soc/intel/skylake/Makefile.inc | 1 + src/soc/intel/skylake/flash_controller.c | 382 +++++++---------------- src/soc/intel/skylake/include/flash_controller.h | 176 +++++++++++ 3 files changed, 290 insertions(+), 269 deletions(-) diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc index 9fa9503..7df7b2b 100644 --- a/src/soc/intel/skylake/Makefile.inc +++ b/src/soc/intel/skylake/Makefile.inc @@ -11,6 +11,7 @@ subdirs-y += ../../../cpu/x86/mtrr subdirs-y += ../../../cpu/x86/smm subdirs-y += ../../../cpu/x86/tsc +romstage-y += flash_controller.c romstage-y += gpio.c romstage-y += memmap.c romstage-y += pch.c diff --git a/src/soc/intel/skylake/flash_controller.c b/src/soc/intel/skylake/flash_controller.c index d8528b1..549e883 100644 --- a/src/soc/intel/skylake/flash_controller.c +++ b/src/soc/intel/skylake/flash_controller.c @@ -25,210 +25,33 @@ #include <string.h> #include <bootstate.h> #include <delay.h> -#include <arch/io.h> -#include <console/console.h> #include <device/pci_ids.h> +#include <flash_controller.h> #include <spi_flash.h> #include <spi-generic.h> #include <soc/pci_devs.h> #include <soc/spi.h> -#define HSFC_FCYCLE_OFF 1 /* 1-2: FLASH Cycle */ -#define HSFC_FCYCLE (0x3 << HSFC_FCYCLE_OFF) -#define HSFC_FCYCLE_WR (0x2 << HSFC_FCYCLE_OFF) -#define HSFC_FDBC_OFF 8 /* 8-13: Flash Data Byte Count */ -#define HSFC_FDBC (0x3f << HSFC_FDBC_OFF) - -#if ENV_SMM -#define pci_read_config_byte(dev, reg, targ)\ - (*(targ) = pci_read_config8(dev, reg)) -#define pci_read_config_word(dev, reg, targ)\ - (*(targ) = pci_read_config16(dev, reg)) -#define pci_read_config_dword(dev, reg, targ)\ - (*(targ) = pci_read_config32(dev, reg)) -#define pci_write_config_byte(dev, reg, val)\ - pci_write_config8(dev, reg, val) -#define pci_write_config_word(dev, reg, val)\ - pci_write_config16(dev, reg, val) -#define pci_write_config_dword(dev, reg, val)\ - pci_write_config32(dev, reg, val) -#else /* !ENV_SMM */ -#include <device/device.h> -#include <device/pci.h> -#define pci_read_config_byte(dev, reg, targ)\ - (*(targ) = pci_read_config8(dev, reg)) -#define pci_read_config_word(dev, reg, targ)\ - (*(targ) = pci_read_config16(dev, reg)) -#define pci_read_config_dword(dev, reg, targ)\ - (*(targ) = pci_read_config32(dev, reg)) -#define pci_write_config_byte(dev, reg, val)\ - pci_write_config8(dev, reg, val) -#define pci_write_config_word(dev, reg, val)\ - pci_write_config16(dev, reg, val) -#define pci_write_config_dword(dev, reg, val)\ - pci_write_config32(dev, reg, val) -#endif /* ENV_SMM */ - -#define B_PCH_SPI_BAR0_MASK 0x0FFF - +#if !(ENV_ROMSTAGE) typedef struct spi_slave pch_spi_slave; static struct spi_flash *spi_flash_hwseq_probe(struct spi_slave *spi); -static int pch_hwseq_write(struct spi_flash *flash, - u32 addr, size_t len, const void *buf); -static int pch_hwseq_read(struct spi_flash *flash, - u32 addr, size_t len, void *buf); - -typedef struct pch_spi_regs { - uint32_t bfpr; - uint16_t hsfs; - uint16_t hsfc; - uint32_t faddr; - uint32_t _reserved0; - uint32_t fdata[16]; - uint32_t frap; - uint32_t freg[6]; - uint32_t _reserved1[6]; - uint32_t pr[5]; - uint32_t _reserved2[2]; - uint8_t ssfs; - uint8_t ssfc[3]; - uint16_t preop; - uint16_t optype; - uint8_t opmenu[8]; - uint32_t bbar; - uint32_t fdoc; - uint32_t fdod; - uint8_t _reserved4[8]; - uint32_t afc; - uint32_t lvscc; - uint32_t uvscc; - uint8_t _reserved5[4]; - uint32_t fpb; - uint8_t _reserved6[28]; - uint32_t srdl; - uint32_t srdc; - uint32_t srd; -} __attribute__((packed)) pch_spi_regs; - -typedef struct pch_spi_controller { - int locked; - uint32_t flmap0; - uint32_t hsfs; - pch_spi_regs *pch_spi; - uint8_t *opmenu; - int menubytes; - uint16_t *preop; - uint16_t *optype; - uint32_t *addr; - uint8_t *data; - unsigned databytes; - uint8_t *status; - uint16_t *control; - uint32_t *bbar; -} pch_spi_controller; - -static pch_spi_controller cntlr; - -enum { - HSFS_FDONE = 0x0001, - HSFS_FCERR = 0x0002, - HSFS_AEL = 0x0004, - HSFS_BERASE_MASK = 0x0018, - HSFS_BERASE_SHIFT = 3, - HSFS_SCIP = 0x0020, - HSFS_FDOPSS = 0x2000, - HSFS_FDV = 0x4000, - HSFS_FLOCKDN = 0x8000 -}; - -enum { - HSFC_FGO = 0x0001, - HSFC_FCYCLE_MASK = 0x0006, - HSFC_FCYCLE_SHIFT = 1, - HSFC_FDBC_MASK = 0x3f00, - HSFC_FDBC_SHIFT = 8, - HSFC_FSMIE = 0x8000 -}; - -#if IS_ENABLED(CONFIG_DEBUG_SPI_FLASH) - -static u8 readb_(const void *addr) -{ - u8 v = read8(addr); - printk(BIOS_DEBUG, "read %2.2x from %4.4x\n", - v, ((unsigned) addr & 0xffff) - 0xf020); - return v; -} - -static u16 readw_(const void *addr) -{ - u16 v = read16(addr); - printk(BIOS_DEBUG, "read %4.4x from %4.4x\n", - v, ((unsigned) addr & 0xffff) - 0xf020); - return v; -} - -static u32 readl_(const void *addr) -{ - u32 v = read32(addr); - printk(BIOS_DEBUG, "read %8.8x from %4.4x\n", - v, ((unsigned) addr & 0xffff) - 0xf020); - return v; -} - -static void writeb_(u8 b, void *addr) -{ - write8(addr, b); - printk(BIOS_DEBUG, "wrote %2.2x to %4.4x\n", - b, ((unsigned) addr & 0xffff) - 0xf020); -} - -static void writew_(u16 b, void *addr) -{ - write16(addr, b); - printk(BIOS_DEBUG, "wrote %4.4x to %4.4x\n", - b, ((unsigned) addr & 0xffff) - 0xf020); -} - -static void writel_(u32 b, void *addr) -{ - write32(addr, b); - printk(BIOS_DEBUG, "wrote %8.8x to %4.4x\n", - b, ((unsigned) addr & 0xffff) - 0xf020); -} - -#else /* CONFIG_DEBUG_SPI_FLASH ^^^ enabled vvv NOT enabled */ - -#define readb_(a) read8(a) -#define readw_(a) read16(a) -#define readl_(a) read32(a) -#define writeb_(val, addr) write8(addr, val) -#define writew_(val, addr) write16(addr, val) -#define writel_(val, addr) write32(addr, val) - -#endif /* CONFIG_DEBUG_SPI_FLASH ^^^ NOT enabled */ - -static void pch_set_bbar(uint32_t minaddr) -{ - uint32_t pchspi_bbar; - - minaddr &= SPIBAR_MEMBAR_MASK; - pchspi_bbar = readl_(cntlr.bbar) & ~SPIBAR_MEMBAR_MASK; - pchspi_bbar |= minaddr; - writel_(pchspi_bbar, cntlr.bbar); -} +#endif unsigned int spi_crop_chunk(unsigned int cmd_len, unsigned int buf_len) { - return min(cntlr.databytes, buf_len); + pch_spi_regs *spi_bar; + + spi_bar = get_spi_bar(); + return min(sizeof(spi_bar->fdata), buf_len); } +#if !(ENV_ROMSTAGE) struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs) { pch_spi_slave *slave = malloc(sizeof(*slave)); if (!slave) { - printk(BIOS_DEBUG, "ICH SPI: Bad allocation\n"); + printk(BIOS_DEBUG, "PCH SPI: Bad allocation\n"); return NULL; } @@ -241,14 +64,15 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs) return slave; } +#endif -static u32 spi_get_flash_size(void) +static u32 spi_get_flash_size(pch_spi_regs *spi_bar) { uint32_t flcomp; u32 size; - writel_(SPIBAR_FDOC_COMPONENT, &cntlr.pch_spi->fdoc); - flcomp = readl_(&cntlr.pch_spi->fdod); + writel_(SPIBAR_FDOC_COMPONENT, &spi_bar->fdoc); + flcomp = readl_(&spi_bar->fdod); printk(BIOS_DEBUG, "flcomp = %x\n", flcomp); switch (flcomp & FLCOMP_C0DEN_MASK) { @@ -281,33 +105,17 @@ void spi_init(void) { uint8_t bios_cntl; device_t dev = PCH_DEV_SPI; - pch_spi_regs *pch_spi; + pch_spi_regs *spi_bar; uint16_t hsfs; /* Root Complex Register Block */ - pch_spi = (pch_spi_regs *)(get_spi_bar()); - cntlr.pch_spi = pch_spi; - hsfs = readw_(&pch_spi->hsfs); - cntlr.hsfs = hsfs; - cntlr.opmenu = pch_spi->opmenu; - cntlr.menubytes = sizeof(pch_spi->opmenu); - cntlr.optype = &pch_spi->optype; - cntlr.addr = &pch_spi->faddr; - cntlr.data = (uint8_t *)pch_spi->fdata; - cntlr.databytes = sizeof(pch_spi->fdata); - cntlr.status = &pch_spi->ssfs; - cntlr.control = (uint16_t *)pch_spi->ssfc; - cntlr.bbar = &pch_spi->bbar; - cntlr.preop = &pch_spi->preop; - - if (cntlr.hsfs & HSFS_FDV) { + spi_bar = get_spi_bar(); + hsfs = readw_(&spi_bar->hsfs); + if (hsfs & HSFS_FDV) { /* Select Flash Descriptor Section Index to 1 */ - writel_(SPIBAR_FDOC_FDSI_1, &pch_spi->fdoc); - cntlr.flmap0 = readl_(&pch_spi->fdod); + writel_(SPIBAR_FDOC_FDSI_1, &spi_bar->fdoc); } - pch_set_bbar(0); - /* Disable the BIOS write protect so write commands are allowed. */ pci_read_config_byte(dev, SPIBAR_BIOS_CNTL, &bios_cntl); bios_cntl &= ~SPIBAR_BC_EISS; @@ -315,17 +123,6 @@ void spi_init(void) pci_write_config_byte(dev, SPIBAR_BIOS_CNTL, bios_cntl); } -#if ENV_RAMSTAGE - -static void spi_init_cb(void *unused) -{ - spi_init(); -} - -BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_ENTRY, spi_init_cb, NULL); - -#endif /* ENV_RAMSTAGE */ - int spi_claim_bus(struct spi_slave *slave) { /* Handled by PCH automatically. */ @@ -337,10 +134,10 @@ void spi_release_bus(struct spi_slave *slave) /* Handled by PCH automatically. */ } -static void pch_hwseq_set_addr(uint32_t addr) +static void pch_hwseq_set_addr(uint32_t addr, pch_spi_regs *spi_bar) { - uint32_t addr_old = readl_(&cntlr.pch_spi->faddr) & ~SPIBAR_FADDR_MASK; - writel_((addr & SPIBAR_FADDR_MASK) | addr_old, &cntlr.pch_spi->faddr); + uint32_t addr_old = readl_(&spi_bar->faddr) & ~SPIBAR_FADDR_MASK; + writel_((addr & SPIBAR_FADDR_MASK) | addr_old, &spi_bar->faddr); } /* @@ -350,22 +147,22 @@ static void pch_hwseq_set_addr(uint32_t addr) * timeout us, 1 on errors. */ static int pch_hwseq_wait_for_cycle_complete(unsigned int timeout, - unsigned int len) + unsigned int len, pch_spi_regs *spi_bar) { uint16_t hsfs; uint32_t addr; timeout /= 8; /* scale timeout duration to counter */ - while ((((hsfs = readw_(&cntlr.pch_spi->hsfs)) & + while ((((hsfs = readw_(&spi_bar->hsfs)) & (HSFS_FDONE | HSFS_FCERR)) == 0) && --timeout) { udelay(8); } - writew_(readw_(&cntlr.pch_spi->hsfs), &cntlr.pch_spi->hsfs); + writew_(readw_(&spi_bar->hsfs), &spi_bar->hsfs); if (!timeout) { uint16_t hsfc; - addr = readl_(&cntlr.pch_spi->faddr) & SPIBAR_FADDR_MASK; - hsfc = readw_(&cntlr.pch_spi->hsfc); + addr = readl_(&spi_bar->faddr) & SPIBAR_FADDR_MASK; + hsfc = readw_(&spi_bar->hsfc); printk(BIOS_ERR, "Transaction timeout between offset 0x%08x \ and 0x%08x (= 0x%08x + %d) HSFC=%x HSFS=%x!\n", addr, addr + len - 1, addr, len - 1, @@ -375,8 +172,8 @@ static int pch_hwseq_wait_for_cycle_complete(unsigned int timeout, if (hsfs & HSFS_FCERR) { uint16_t hsfc; - addr = readl_(&cntlr.pch_spi->faddr) & SPIBAR_FADDR_MASK; - hsfc = readw_(&cntlr.pch_spi->hsfc); + addr = readl_(&spi_bar->faddr) & SPIBAR_FADDR_MASK; + hsfc = readw_(&spi_bar->hsfc); printk(BIOS_ERR, "Transaction error between offset 0x%08x and \ 0x%08x (= 0x%08x + %d) HSFC=%x HSFS=%x!\n", addr, addr + len - 1, addr, len - 1, @@ -386,14 +183,15 @@ static int pch_hwseq_wait_for_cycle_complete(unsigned int timeout, return 0; } - -static int pch_hwseq_erase(struct spi_flash *flash, u32 offset, size_t len) +int pch_hwseq_erase(struct spi_flash *flash, u32 offset, size_t len) { u32 start, end, erase_size; int ret; uint16_t hsfc; - uint16_t timeout = 1000 * 60; + uint32_t timeout = 5000 * 1000; /* 5 s for max 64 kB */ + pch_spi_regs *spi_bar; + spi_bar = get_spi_bar(); erase_size = flash->sector_size; if (offset % erase_size || len % erase_size) { printk(BIOS_ERR, "SF: Erase offset/length not multiple of erase size\n"); @@ -415,18 +213,18 @@ static int pch_hwseq_erase(struct spi_flash *flash, u32 offset, size_t len) * Make sure FDONE, FCERR, AEL are * cleared by writing 1 to them. */ - writew_(readw_(&cntlr.pch_spi->hsfs), &cntlr.pch_spi->hsfs); + writew_(readw_(&spi_bar->hsfs), &spi_bar->hsfs); - pch_hwseq_set_addr(offset); + pch_hwseq_set_addr(offset, spi_bar); offset += erase_size; - hsfc = readw_(&cntlr.pch_spi->hsfc); + hsfc = readw_(&spi_bar->hsfc); hsfc &= ~HSFC_FCYCLE; /* clear operation */ hsfc |= HSFC_FCYCLE; /* set erase operation */ hsfc |= HSFC_FGO; /* start */ - writew_(hsfc, &cntlr.pch_spi->hsfc); - if (pch_hwseq_wait_for_cycle_complete(timeout, len)) { + writew_(hsfc, &spi_bar->hsfc); + if (pch_hwseq_wait_for_cycle_complete(timeout, len, spi_bar)) { printk(BIOS_ERR, "SF: Erase failed at %x\n", offset - erase_size); ret = -1; @@ -442,27 +240,28 @@ out: return ret; } -static void pch_read_data(uint8_t *data, int len) +static void pch_read_data(uint8_t *data, int len, pch_spi_regs *spi_bar) { int i; uint32_t temp32 = 0; for (i = 0; i < len; i++) { if ((i % 4) == 0) - temp32 = readl_(cntlr.data + i); + temp32 = readl_((uint8_t *)spi_bar->fdata + i); data[i] = (temp32 >> ((i % 4) * 8)) & 0xff; } } - -static int pch_hwseq_read(struct spi_flash *flash, +int pch_hwseq_read(struct spi_flash *flash, u32 addr, size_t len, void *buf) { uint16_t hsfc; - uint16_t timeout = 100 * 60; + uint16_t timeout = 100 * 60; /* 6 mili secs timeout */ uint8_t block_len; + pch_spi_regs *spi_bar; - if (addr + len > spi_get_flash_size()) { + spi_bar = get_spi_bar(); + if (addr + len > spi_get_flash_size(spi_bar)) { printk(BIOS_ERR, "Attempt to read %x-%x which is out of chip\n", (unsigned) addr, @@ -471,24 +270,25 @@ static int pch_hwseq_read(struct spi_flash *flash, } /* clear FDONE, FCERR, AEL by writing 1 to them (if they are set) */ - writew_(readw_(&cntlr.pch_spi->hsfs), &cntlr.pch_spi->hsfs); + writew_(readw_(&spi_bar->hsfs), &spi_bar->hsfs); while (len > 0) { - block_len = min(len, cntlr.databytes); + block_len = min(len, sizeof(spi_bar->fdata)); if (block_len > (~addr & 0xff)) block_len = (~addr & 0xff) + 1; - pch_hwseq_set_addr(addr); - hsfc = readw_(&cntlr.pch_spi->hsfc); + pch_hwseq_set_addr(addr, spi_bar); + hsfc = readw_(&spi_bar->hsfc); hsfc &= ~HSFC_FCYCLE; /* set read operation */ hsfc &= ~HSFC_FDBC; /* clear byte count */ /* set byte count */ - hsfc |= (((block_len - 1) << HSFC_FDBC_OFF) & HSFC_FDBC); + hsfc |= (((block_len - 1) << HSFC_FDBC_SHIFT) & HSFC_FDBC); hsfc |= HSFC_FGO; /* start */ - writew_(hsfc, &cntlr.pch_spi->hsfc); + writew_(hsfc, &spi_bar->hsfc); - if (pch_hwseq_wait_for_cycle_complete(timeout, block_len)) - return 1; - pch_read_data(buf, block_len); + if (pch_hwseq_wait_for_cycle_complete + (timeout, block_len, spi_bar)) + return -1; + pch_read_data(buf, block_len, spi_bar); addr += block_len; buf += block_len; len -= block_len; @@ -505,7 +305,9 @@ static void pch_fill_data(const uint8_t *data, int len) { uint32_t temp32 = 0; int i; + pch_spi_regs *spi_bar; + spi_bar = get_spi_bar(); if (len <= 0) return; @@ -516,22 +318,26 @@ static void pch_fill_data(const uint8_t *data, int len) temp32 |= ((uint32_t) data[i]) << ((i % 4) * 8); if ((i % 4) == 3) /* 32 bits are full, write them to regs. */ - writel_(temp32, cntlr.data + (i - (i % 4))); + writel_(temp32, + (uint8_t *)spi_bar->fdata + (i - (i % 4))); } i--; if ((i % 4) != 3) /* Write remaining data to regs. */ - writel_(temp32, cntlr.data + (i - (i % 4))); + writel_(temp32, (uint8_t *)spi_bar->fdata + (i - (i % 4))); } -static int pch_hwseq_write(struct spi_flash *flash, +int pch_hwseq_write(struct spi_flash *flash, u32 addr, size_t len, const void *buf) { uint16_t hsfc; - uint16_t timeout = 100 * 60; + uint16_t timeout = 100 * 60; /* 6 mili secs timeout */ uint8_t block_len; uint32_t start = addr; + pch_spi_regs *spi_bar; + + spi_bar = get_spi_bar(); - if (addr + len > spi_get_flash_size()) { + if (addr + len > spi_get_flash_size(spi_bar)) { printk(BIOS_ERR, "Attempt to write 0x%x-0x%x which is out of chip\n", (unsigned)addr, (unsigned) (addr+len)); @@ -539,26 +345,27 @@ static int pch_hwseq_write(struct spi_flash *flash, } /* clear FDONE, FCERR, AEL by writing 1 to them (if they are set) */ - writew_(readw_(&cntlr.pch_spi->hsfs), &cntlr.pch_spi->hsfs); + writew_(readw_(&spi_bar->hsfs), &spi_bar->hsfs); while (len > 0) { - block_len = min(len, cntlr.databytes); + block_len = min(len, sizeof(spi_bar->fdata)); if (block_len > (~addr & 0xff)) block_len = (~addr & 0xff) + 1; - pch_hwseq_set_addr(addr); + pch_hwseq_set_addr(addr, spi_bar); pch_fill_data(buf, block_len); - hsfc = readw_(&cntlr.pch_spi->hsfc); + hsfc = readw_(&spi_bar->hsfc); hsfc &= ~HSFC_FCYCLE; /* clear operation */ hsfc |= HSFC_FCYCLE_WR; /* set write operation */ hsfc &= ~HSFC_FDBC; /* clear byte count */ /* set byte count */ - hsfc |= (((block_len - 1) << HSFC_FDBC_OFF) & HSFC_FDBC); + hsfc |= (((block_len - 1) << HSFC_FDBC_SHIFT) & HSFC_FDBC); hsfc |= HSFC_FGO; /* start */ - writew_(hsfc, &cntlr.pch_spi->hsfc); + writew_(hsfc, &spi_bar->hsfc); - if (pch_hwseq_wait_for_cycle_complete(timeout, block_len)) { + if (pch_hwseq_wait_for_cycle_complete + (timeout, block_len, spi_bar)) { printk(BIOS_ERR, "SF: write failure at %x\n", addr); return -1; } @@ -571,12 +378,46 @@ static int pch_hwseq_write(struct spi_flash *flash, return 0; } +int pch_hwseq_read_status(struct spi_flash *flash, u8 *reg) +{ + uint16_t hsfc; + uint16_t timeout = 100 * 60; /* 6 mili secs timeout */ + uint8_t block_len = SPI_READ_STATUS_LENGTH; + pch_spi_regs *spi_bar; + + spi_bar = get_spi_bar(); + /* clear FDONE, FCERR, AEL by writing 1 to them (if they are set) */ + writew_(readw_(&spi_bar->hsfs), &spi_bar->hsfs); + + hsfc = readw_(&spi_bar->hsfc); + hsfc &= ~HSFC_FCYCLE; /* set read operation */ + /* read status register */ + hsfc |= HSFC_FCYCLE_RS; + hsfc &= ~HSFC_FDBC; /* clear byte count */ + /* set byte count */ + hsfc |= (((block_len - 1) << HSFC_FDBC_SHIFT) & HSFC_FDBC); + hsfc |= HSFC_FGO; /* start */ + writew_(hsfc, &spi_bar->hsfc); + + if (pch_hwseq_wait_for_cycle_complete(timeout, + block_len, spi_bar)) + return -1; + pch_read_data(reg, block_len, spi_bar); + /* clear read status register */ + writew_(readw_(&spi_bar->hsfc) & + ~HSFC_FCYCLE_RS, &spi_bar->hsfc); + + return 0; +} +#if !(ENV_ROMSTAGE) static struct spi_flash *spi_flash_hwseq_probe(struct spi_slave *spi) { struct spi_flash *flash = NULL; u32 berase; + pch_spi_regs *spi_bar; + spi_bar = get_spi_bar(); flash = malloc(sizeof(*flash)); if (!flash) { printk(BIOS_WARNING, "SF: Failed to allocate memory\n"); @@ -589,9 +430,10 @@ static struct spi_flash *spi_flash_hwseq_probe(struct spi_slave *spi) flash->write = pch_hwseq_write; flash->erase = pch_hwseq_erase; flash->read = pch_hwseq_read; - pch_hwseq_set_addr(0); + flash->status = pch_hwseq_read_status; + pch_hwseq_set_addr(0, spi_bar); - berase = (cntlr.hsfs >> SPIBAR_HSFS_BERASE_OFFSET) & + berase = ((readw_(&spi_bar->hsfs)) >> SPIBAR_HSFS_BERASE_OFFSET) & SPIBAR_HSFS_BERASE_MASK; switch (berase) { @@ -609,7 +451,9 @@ static struct spi_flash *spi_flash_hwseq_probe(struct spi_slave *spi) break; } - flash->size = spi_get_flash_size(); + flash->size = spi_get_flash_size(spi_bar); return flash; } +#endif + diff --git a/src/soc/intel/skylake/include/flash_controller.h b/src/soc/intel/skylake/include/flash_controller.h new file mode 100644 index 0000000..c79d265 --- /dev/null +++ b/src/soc/intel/skylake/include/flash_controller.h @@ -0,0 +1,176 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., + */ + +#ifndef _FLASH_CONTROLLER__H_ +#define _FLASH_CONTROLLER__H_ + +#include <rules.h> +#include <arch/io.h> +#include <console/console.h> +#include <spi_flash.h> + +int pch_hwseq_erase(struct spi_flash *flash, u32 offset, size_t len); +int pch_hwseq_write(struct spi_flash *flash, + u32 addr, size_t len, const void *buf); + +int pch_hwseq_read(struct spi_flash *flash, + u32 addr, size_t len, void *buf); +int pch_hwseq_read_status(struct spi_flash *flash, u8 *reg); + + +#if IS_ENABLED(CONFIG_DEBUG_SPI_FLASH) +static u8 readb_(const void *addr) +{ + u8 v = read8(addr); + printk(BIOS_DEBUG, "read %2.2x from %4.4x\n", + v, ((unsigned) addr & 0xffff) - 0xf020); + return v; +} + +static u16 readw_(const void *addr) +{ + u16 v = read16(addr); + printk(BIOS_DEBUG, "read %4.4x from %4.4x\n", + v, ((unsigned) addr & 0xffff) - 0xf020); + return v; +} + +static u32 readl_(const void *addr) +{ + u32 v = read32(addr); + printk(BIOS_DEBUG, "read %8.8x from %4.4x\n", + v, ((unsigned) addr & 0xffff) - 0xf020); + return v; +} + +static void writeb_(u8 b, void *addr) +{ + write8(addr, b); + printk(BIOS_DEBUG, "wrote %2.2x to %4.4x\n", + b, ((unsigned) addr & 0xffff) - 0xf020); +} + +static void writew_(u16 b, void *addr) +{ + write16(addr, b); + printk(BIOS_DEBUG, "wrote %4.4x to %4.4x\n", + b, ((unsigned) addr & 0xffff) - 0xf020); +} + +static void writel_(u32 b, void *addr) +{ + write32(addr, b); + printk(BIOS_DEBUG, "wrote %8.8x to %4.4x\n", + b, ((unsigned) addr & 0xffff) - 0xf020); +} + +#else /* CONFIG_DEBUG_SPI_FLASH ^^^ enabled vvv NOT enabled */ + +#define readb_(a) read8(a) +#define readw_(a) read16(a) +#define readl_(a) read32(a) +#define writeb_(val, addr) write8(addr, val) +#define writew_(val, addr) write16(addr, val) +#define writel_(val, addr) write32(addr, val) + +#endif /* CONFIG_DEBUG_SPI_FLASH ^^^ NOT enabled */ + +#if ENV_SMM +#define pci_read_config_byte(dev, reg, targ)\ + (*(targ) = pci_read_config8(dev, reg)) +#define pci_read_config_word(dev, reg, targ)\ + (*(targ) = pci_read_config16(dev, reg)) +#define pci_read_config_dword(dev, reg, targ)\ + (*(targ) = pci_read_config32(dev, reg)) +#define pci_write_config_byte(dev, reg, val)\ + pci_write_config8(dev, reg, val) +#define pci_write_config_word(dev, reg, val)\ + pci_write_config16(dev, reg, val) +#define pci_write_config_dword(dev, reg, val)\ + pci_write_config32(dev, reg, val) +#else /* !ENV_SMM */ +#include <device/device.h> +#include <device/pci.h> +#define pci_read_config_byte(dev, reg, targ)\ + (*(targ) = pci_read_config8(dev, reg)) +#define pci_read_config_word(dev, reg, targ)\ + (*(targ) = pci_read_config16(dev, reg)) +#define pci_read_config_dword(dev, reg, targ)\ + (*(targ) = pci_read_config32(dev, reg)) +#define pci_write_config_byte(dev, reg, val)\ + pci_write_config8(dev, reg, val) +#define pci_write_config_word(dev, reg, val)\ + pci_write_config16(dev, reg, val) +#define pci_write_config_dword(dev, reg, val)\ + pci_write_config32(dev, reg, val) +#endif /* ENV_SMM */ + +#define HSFC_FCYCLE (0x3 << HSFC_FCYCLE_SHIFT) +#define HSFC_FCYCLE_WR (0x2 << HSFC_FCYCLE_SHIFT) +#define HSFC_FCYCLE_RS (0x8 << HSFC_FCYCLE_SHIFT) +#define HSFC_FDBC (0x3f << HSFC_FDBC_SHIFT) + +#define SPI_READ_STATUS_LENGTH 1 /* Read Status Register 1 */ + +#define WPSR_MASK_SRP0_BIT 0x80 + +typedef struct pch_spi_regs { + uint32_t bfpr; + uint16_t hsfs; + uint16_t hsfc; + uint32_t faddr; + uint32_t _reserved0; + uint32_t fdata[16]; + uint32_t frap; + uint32_t freg[6]; + uint32_t _reserved1[6]; + uint32_t pr[5]; + uint32_t gpr0; + uint32_t _reserved2; + uint32_t _reserved3; + uint16_t preop; + uint16_t optype; + uint8_t opmenu[8]; + uint32_t bbar; + uint32_t fdoc; + uint32_t fdod; + uint8_t _reserved4[8]; + uint32_t afc; + uint32_t lvscc; + uint32_t uvscc; + uint8_t _reserved5[4]; + uint32_t fpb; + uint8_t _reserved6[28]; + uint32_t srdl; + uint32_t srdc; + uint32_t srd; +} __attribute__((packed)) pch_spi_regs; + +enum { + HSFS_FDONE = 0x0001, + HSFS_FCERR = 0x0002, + HSFS_FDV = 0x4000, +}; + +enum { + HSFC_FGO = 0x0001, + HSFC_FCYCLE_SHIFT = 1, + HSFC_FDBC_SHIFT = 8, +}; +#endif /* _FLASH_CONTROLLER__H_ */

1 0

Patch merged into coreboot/master: intel/kunimitsu: add WP to gpio table
by gerrit＠coreboot.org 29 Aug '15

29 Aug '15

the following patch was just integrated into master: commit 6cba16f6ef7b2a33634d6a6b5c5bf79db956edc7 Author: Wenkai Du <wenkai.du(a)intel.com> Date: Thu Aug 20 15:17:13 2015 -0700 intel/kunimitsu: add WP to gpio table This is needed to fix error in depthcharge: src/vboot/util/flag.c:38 flag_fetch(): Don't have a gpio set up for flag 3. BUG=chrome-os-partner:44214 TEST=Verify depthcharge prints EC ID on boot up BRANCH=None Change-Id: Ia2d88b8427e54e2dc9e6c9abecc95fd7656abb66 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Original-Commit-Id: 142b156c72ceedfbd4bf3f54c0cb1128c0fad5a3 Original-Change-Id: I7e7a7d1b92bc1ee2c5ebac8de6946550ddd68a68 Original-Signed-off-by: Wenkai Du <wenkai.du(a)intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/294715 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/11421 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See http://review.coreboot.org/11421 for details. -gerrit

1 0

Patch set updated for coreboot: intel/kunimitsu: add WP to gpio table
by Patrick Georgi 29 Aug '15

29 Aug '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11421 -gerrit commit ea7a327070937c1b0afc15fb97bc874e2ac684a8 Author: Wenkai Du <wenkai.du(a)intel.com> Date: Thu Aug 20 15:17:13 2015 -0700 intel/kunimitsu: add WP to gpio table This is needed to fix error in depthcharge: src/vboot/util/flag.c:38 flag_fetch(): Don't have a gpio set up for flag 3. BUG=chrome-os-partner:44214 TEST=Verify depthcharge prints EC ID on boot up BRANCH=None Change-Id: Ia2d88b8427e54e2dc9e6c9abecc95fd7656abb66 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Original-Commit-Id: 142b156c72ceedfbd4bf3f54c0cb1128c0fad5a3 Original-Change-Id: I7e7a7d1b92bc1ee2c5ebac8de6946550ddd68a68 Original-Signed-off-by: Wenkai Du <wenkai.du(a)intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/294715 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/mainboard/intel/kunimitsu/chromeos.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/mainboard/intel/kunimitsu/chromeos.c b/src/mainboard/intel/kunimitsu/chromeos.c index 4447a6c..6767705 100644 --- a/src/mainboard/intel/kunimitsu/chromeos.c +++ b/src/mainboard/intel/kunimitsu/chromeos.c @@ -39,6 +39,8 @@ void fill_lb_gpios(struct lb_gpios *gpios) gpios->count = GPIO_COUNT; gpio = gpios->gpios; + fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "write protect", + get_write_protect_state()); fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "recovery", get_recovery_mode_switch()); fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "developer",

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Patch merged into coreboot/master: google/glados: configure gpio pads prior to SiliconInit()
by gerrit＠coreboot.org 29 Aug '15

29 Aug '15

the following patch was just integrated into master: commit a3fa98a5d75d1dcde97090aaa2e5a617c72b4559 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Aug 20 13:06:56 2015 -0500 google/glados: configure gpio pads prior to SiliconInit() Move the gpio pad configuration prior to SiliconInit() in case there are dependencies of the pads being configured in prior to SiliconInit(). BUG=chrome-os-partner:43522 BUG=chrome-os-partner:43492 BRANCH=None TEST=Built and booted glados. Change-Id: I84f8e965bf205a4945b14a63fa8074953750f785 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Original-Commit-Id: 5cce5347449f69ac6cf7030ea3b91d3f8b4cc7f9 Original-Change-Id: I18cd33a455d5635a866abb76142cab516b04f446 Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/294642 Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: http://review.coreboot.org/11420 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See http://review.coreboot.org/11420 for details. -gerrit

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Patch set updated for coreboot: google/glados: configure gpio pads prior to SiliconInit()
by Patrick Georgi 29 Aug '15

29 Aug '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11420 -gerrit commit 1c9897f4f7fb31f22479f739da4201ac523cc943 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Aug 20 13:06:56 2015 -0500 google/glados: configure gpio pads prior to SiliconInit() Move the gpio pad configuration prior to SiliconInit() in case there are dependencies of the pads being configured in prior to SiliconInit(). BUG=chrome-os-partner:43522 BUG=chrome-os-partner:43492 BRANCH=None TEST=Built and booted glados. Change-Id: I84f8e965bf205a4945b14a63fa8074953750f785 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Original-Commit-Id: 5cce5347449f69ac6cf7030ea3b91d3f8b4cc7f9 Original-Change-Id: I18cd33a455d5635a866abb76142cab516b04f446 Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/294642 Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/mainboard/google/glados/mainboard.c | 3 --- src/mainboard/google/glados/ramstage.c | 4 ++++ 2 files changed, 4 insertions(+), 3 deletions(-) diff --git a/src/mainboard/google/glados/mainboard.c b/src/mainboard/google/glados/mainboard.c index 61a5485..5e48f17 100644 --- a/src/mainboard/google/glados/mainboard.c +++ b/src/mainboard/google/glados/mainboard.c @@ -22,12 +22,9 @@ #include <device/device.h> #include <stdlib.h> #include "ec.h" -#include "gpio.h" static void mainboard_init(device_t dev) { - gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); - if (IS_ENABLED(CONFIG_GOOGLE_CHROME_EC)) mainboard_ec_init(); } diff --git a/src/mainboard/google/glados/ramstage.c b/src/mainboard/google/glados/ramstage.c index 8801380..4816fec 100644 --- a/src/mainboard/google/glados/ramstage.c +++ b/src/mainboard/google/glados/ramstage.c @@ -19,7 +19,11 @@ */ #include <soc/ramstage.h> +#include "gpio.h" void mainboard_silicon_init_params(SILICON_INIT_UPD *params) { + /* Configure pads prior to SiliconInit() in case there's any + * dependencies during hardware initialization. */ + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); }

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Patch merged into coreboot/master: google/glados: fix kepler probing
by gerrit＠coreboot.org 29 Aug '15

29 Aug '15

the following patch was just integrated into master: commit 31718c039f70c2903623e679bcb56a88bf5937ed Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Aug 20 12:18:08 2015 -0500 google/glados: fix kepler probing On proto2 boards the kepler device has its reset line pulled up to one of its IO rails with a zener in between. This results in the device not being visible at MemoryInit() time because for some reason FSP is doing PCIE configuration/probing in that path. Hack around the broken FSP logic by configuring the pads for kepler's power and clkreq. BUG=chrome-os-partner:44326 BRANCH=None TEST=Built and booted glados. lscpi shows the device on bus 2. Change-Id: I543eb3ccd3ab5ffacd6efc959e6e2f7a88de78b3 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Original-Commit-Id: 67f6b57487e8724b469f74870e0083d4e1dac4d2 Original-Change-Id: I7fe4a707f9321b7bdec4b4be729c5d0dcce65f6e Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/294810 Original-Reviewed-by: Robbie Zhang <robbie.zhang(a)intel.com> Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: http://review.coreboot.org/11419 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See http://review.coreboot.org/11419 for details. -gerrit

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coreboot-gerrit August 2015