coreboot-gerrit August 2015

coreboot-gerrit@coreboot.org

1 participants
814 discussions

Patch set updated for coreboot: google/glados: fix kepler probing
by Patrick Georgi 29 Aug '15

29 Aug '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11419 -gerrit commit 51b3870d0eaf10ed4952b816b890e1332f5bf910 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Aug 20 12:18:08 2015 -0500 google/glados: fix kepler probing On proto2 boards the kepler device has its reset line pulled up to one of its IO rails with a zener in between. This results in the device not being visible at MemoryInit() time because for some reason FSP is doing PCIE configuration/probing in that path. Hack around the broken FSP logic by configuring the pads for kepler's power and clkreq. BUG=chrome-os-partner:44326 BRANCH=None TEST=Built and booted glados. lscpi shows the device on bus 2. Change-Id: I543eb3ccd3ab5ffacd6efc959e6e2f7a88de78b3 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Original-Commit-Id: 67f6b57487e8724b469f74870e0083d4e1dac4d2 Original-Change-Id: I7fe4a707f9321b7bdec4b4be729c5d0dcce65f6e Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/294810 Original-Reviewed-by: Robbie Zhang <robbie.zhang(a)intel.com> Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/mainboard/google/glados/gpio.h | 8 ++++++++ src/mainboard/google/glados/romstage.c | 11 +++++++++++ 2 files changed, 19 insertions(+) diff --git a/src/mainboard/google/glados/gpio.h b/src/mainboard/google/glados/gpio.h index c4d3d92..fb37b3b 100644 --- a/src/mainboard/google/glados/gpio.h +++ b/src/mainboard/google/glados/gpio.h @@ -48,6 +48,7 @@ #define EC_SMI_GPI GPP_E15 #ifndef __ACPI__ +/* Pad configuration in ramstage. */ static const struct pad_config gpio_table[] = { /* RCIN# */ PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), /* LAD0 */ PAD_CFG_NF(GPP_A1, NONE, DEEP, NF1), @@ -219,6 +220,13 @@ static const struct pad_config gpio_table[] = { /* SLP_S5# */ PAD_CFG_NF(GPD10, NONE, DEEP, NF1), /* LANPHYC */ /* GPD11 */ }; + +/* Early pad configuration in romstage. */ +static const struct pad_config early_gpio_table[] = { +/* SRCCLKREQ2# */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), /* KEPLER */ +/* UART0_CTS# */ PAD_CFG_GPO(GPP_C11, 1, DEEP), /* EN_PP3300_KEPLER */ +}; + #endif #endif diff --git a/src/mainboard/google/glados/romstage.c b/src/mainboard/google/glados/romstage.c index 4d9aaf4..36a8453 100644 --- a/src/mainboard/google/glados/romstage.c +++ b/src/mainboard/google/glados/romstage.c @@ -27,10 +27,21 @@ #include <soc/pei_data.h> #include <soc/pei_wrapper.h> #include <soc/romstage.h> +#include "gpio.h" #include "spd/spd.h" +static void early_config_gpio(void) +{ + /* This is a hack for FSP because it does things in MemoryInit() + * which it shouldn't be. We have to prepare certain gpios here + * because of the brokenness in FSP. */ + gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table)); +} + void mainboard_romstage_entry(struct romstage_params *params) { + early_config_gpio(); + /* Fill out PEI DATA */ mainboard_fill_pei_data(params->pei_data); mainboard_fill_spd_data(params->pei_data);

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Patch merged into coreboot/master: google/glados: Export GPIO for EC_IN_RW
by gerrit＠coreboot.org 29 Aug '15

29 Aug '15

the following patch was just integrated into master: commit a58cf01a1fd545c01b036f9abaf354440822f043 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Thu Aug 20 09:54:18 2015 -0700 google/glados: Export GPIO for EC_IN_RW Export the proper GPIO for EC_IN_RW so it can be picked up and used by depthcharge/vboot. BUG=chrome-os-partner:43072 BRANCH=none TEST=build and boot on glados P2 Change-Id: I32d338ef424086ec9701900e976bd0dffe4637a0 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Original-Commit-Id: dd983c84de0c3b896b20d38438a3285cfcaf7e56 Original-Change-Id: I77f7d3a0c0d733302b81273d96026d39b001ed19 Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/294712 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/11418 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See http://review.coreboot.org/11418 for details. -gerrit

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Patch set updated for coreboot: google/glados: Export GPIO for EC_IN_RW
by Patrick Georgi 29 Aug '15

29 Aug '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11418 -gerrit commit 3182417934c0daeae4fc980deaf38ccff2fed069 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Thu Aug 20 09:54:18 2015 -0700 google/glados: Export GPIO for EC_IN_RW Export the proper GPIO for EC_IN_RW so it can be picked up and used by depthcharge/vboot. BUG=chrome-os-partner:43072 BRANCH=none TEST=build and boot on glados P2 Change-Id: I32d338ef424086ec9701900e976bd0dffe4637a0 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Original-Commit-Id: dd983c84de0c3b896b20d38438a3285cfcaf7e56 Original-Change-Id: I77f7d3a0c0d733302b81273d96026d39b001ed19 Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/294712 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/mainboard/google/glados/chromeos.c | 14 +++++++------- src/mainboard/google/glados/gpio.h | 3 +++ 2 files changed, 10 insertions(+), 7 deletions(-) diff --git a/src/mainboard/google/glados/chromeos.c b/src/mainboard/google/glados/chromeos.c index 13d0fce..dba1cbb 100644 --- a/src/mainboard/google/glados/chromeos.c +++ b/src/mainboard/google/glados/chromeos.c @@ -35,16 +35,11 @@ #if ENV_RAMSTAGE #include <boot/coreboot_tables.h> -#define GPIO_COUNT 6 - void fill_lb_gpios(struct lb_gpios *gpios) { - struct lb_gpio *gpio; - - gpios->size = sizeof(*gpios) + (GPIO_COUNT * sizeof(struct lb_gpio)); - gpios->count = GPIO_COUNT; + struct lb_gpio *start_gpio = gpios->gpios; + struct lb_gpio *gpio = start_gpio; - gpio = gpios->gpios; fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "write protect", get_write_protect_state()); fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "recovery", @@ -55,6 +50,11 @@ void fill_lb_gpios(struct lb_gpios *gpios) get_lid_switch()); fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "power", 0); fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "oprom", gfx_get_init_done()); + fill_lb_gpio(gpio++, GPIO_EC_IN_RW, ACTIVE_HIGH, "EC in RW", + gpio_get(GPIO_EC_IN_RW)); + + gpios->count = gpio - start_gpio; + gpios->size = sizeof(*gpios) + (gpios->count * sizeof(*gpio)); } #endif /* ENV_RAMSTAGE */ diff --git a/src/mainboard/google/glados/gpio.h b/src/mainboard/google/glados/gpio.h index fc5ffff..c4d3d92 100644 --- a/src/mainboard/google/glados/gpio.h +++ b/src/mainboard/google/glados/gpio.h @@ -23,6 +23,9 @@ #include <soc/gpe.h> #include <soc/gpio.h> +/* EC in RW */ +#define GPIO_EC_IN_RW GPP_C6 + /* BIOS Flash Write Protect */ #define GPIO_PCH_WP GPP_C23

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Patch merged into coreboot/master: intel/skylake: Fix RMT disable of saved training data
by gerrit＠coreboot.org 29 Aug '15

29 Aug '15

the following patch was just integrated into master: commit 08a6fd309f9396fc7bdcbdc9608661da3a8c94a7 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Wed Aug 19 11:03:59 2015 -0700 intel/skylake: Fix RMT disable of saved training data The RMT flag that was attempting to disable saved training to force a full memory train was happening too late. In testing I was actually hitting a case where FSP was training every time but it was not because it was properly being told to. This moves the check of the RMT flag from devicetree to happen ealier, before it is actually consumed by romstage_common(). BUG=chrome-os-partner:40635 BRANCH=none TEST=do both power off+on and warm resets to ensure that FSP is doing a full memory train every time with RMT enabled. Change-Id: Icf36e7b1ae20e08f6bc24bf832498d69b37dee92 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Original-Commit-Id: f3fa3846d51dec65f22f018acc8fb8c4d18688a7 Original-Change-Id: I2128b4a24bb8b2c8ddcb792c09b6fb0284d1fda4 Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/294177 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/11417 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See http://review.coreboot.org/11417 for details. -gerrit

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Patch set updated for coreboot: intel/skylake: Fix RMT disable of saved training data
by Patrick Georgi 29 Aug '15

29 Aug '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11417 -gerrit commit df29dc965cbd4ea663402160fad1895f99316f8d Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Wed Aug 19 11:03:59 2015 -0700 intel/skylake: Fix RMT disable of saved training data The RMT flag that was attempting to disable saved training to force a full memory train was happening too late. In testing I was actually hitting a case where FSP was training every time but it was not because it was properly being told to. This moves the check of the RMT flag from devicetree to happen ealier, before it is actually consumed by romstage_common(). BUG=chrome-os-partner:40635 BRANCH=none TEST=do both power off+on and warm resets to ensure that FSP is doing a full memory train every time with RMT enabled. Change-Id: Icf36e7b1ae20e08f6bc24bf832498d69b37dee92 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Original-Commit-Id: f3fa3846d51dec65f22f018acc8fb8c4d18688a7 Original-Change-Id: I2128b4a24bb8b2c8ddcb792c09b6fb0284d1fda4 Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/294177 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/soc/intel/skylake/pei_data.c | 14 ++++++++++++++ src/soc/intel/skylake/romstage/romstage.c | 7 +------ 2 files changed, 15 insertions(+), 6 deletions(-) diff --git a/src/soc/intel/skylake/pei_data.c b/src/soc/intel/skylake/pei_data.c index 47198a7..caee078 100644 --- a/src/soc/intel/skylake/pei_data.c +++ b/src/soc/intel/skylake/pei_data.c @@ -18,11 +18,15 @@ * Foundation, Inc. */ +#include <chip.h> #include <console/console.h> #include <console/streams.h> +#include <device/device.h> +#include <device/pci_def.h> #include <stdlib.h> #include <stdint.h> #include <soc/iomap.h> +#include <soc/pci_devs.h> #include <soc/pei_data.h> #include <soc/pei_wrapper.h> #include <soc/smm.h> @@ -34,6 +38,16 @@ static void ABI_X86 send_to_console(unsigned char b) void soc_fill_pei_data(struct pei_data *pei_data) { + const struct device *dev; + const struct soc_intel_skylake_config *config; + + /* Set the parameters for MemoryInit */ + dev = dev_find_slot(0, PCH_DEVFN_LPC); + config = dev->chip_info; + pei_data->pei_version = PEI_VERSION; pei_data->tx_byte = &send_to_console; + + /* Force a full memory train if RMT is enabled */ + pei_data->disable_saved_data = config->Rmt; } diff --git a/src/soc/intel/skylake/romstage/romstage.c b/src/soc/intel/skylake/romstage/romstage.c index e9f0d42..91a496e 100644 --- a/src/soc/intel/skylake/romstage/romstage.c +++ b/src/soc/intel/skylake/romstage/romstage.c @@ -103,12 +103,7 @@ void soc_memory_init_params(struct romstage_params *params, upd->SataMode = config->SataMode; upd->EnableTraceHub = config->EnableTraceHub; upd->SaGv = config->SaGv; - - if (config->Rmt) { - upd->RMT = 1; - /* Force a full memory train if RMT is enabled */ - params->pei_data->disable_saved_data = 1; - } + upd->RMT = config->Rmt; } void soc_display_memory_init_params(const MEMORY_INIT_UPD *old,

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Patch merged into coreboot/master: intel/skylake: mask off txstate before setting new gpio value
by gerrit＠coreboot.org 29 Aug '15

29 Aug '15

the following patch was just integrated into master: commit 162aee9a5dd5c03c519b3a3542ba2eca0ee43c92 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Aug 19 21:07:14 2015 -0500 intel/skylake: mask off txstate before setting new gpio value The previously driven TX state of the buffer was not being cleared before or'ing in the new value. Fix this oversight. BUG=chrome-os-partner:43522 BRANCH=None TEST=Built and booted glados. Also dumped assembly and saw the masking happen. Change-Id: I74ea469564d37d6b29e9481b0ea704f04f54ac30 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Original-Commit-Id: d399e8b32b30b8b2275bb6ff8dd24f7d5cfeadda Original-Change-Id: I341b396af5de20ffeeb2e42066b224dd54251793 Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/294541 Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: http://review.coreboot.org/11416 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> See http://review.coreboot.org/11416 for details. -gerrit

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Patch set updated for coreboot: intel/skylake: mask off txstate before setting new gpio value
by Patrick Georgi 29 Aug '15

29 Aug '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11416 -gerrit commit 00ff7a06819224ac5014ed1e063dad03b80d552d Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Aug 19 21:07:14 2015 -0500 intel/skylake: mask off txstate before setting new gpio value The previously driven TX state of the buffer was not being cleared before or'ing in the new value. Fix this oversight. BUG=chrome-os-partner:43522 BRANCH=None TEST=Built and booted glados. Also dumped assembly and saw the masking happen. Change-Id: I74ea469564d37d6b29e9481b0ea704f04f54ac30 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Original-Commit-Id: d399e8b32b30b8b2275bb6ff8dd24f7d5cfeadda Original-Change-Id: I341b396af5de20ffeeb2e42066b224dd54251793 Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/294541 Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/soc/intel/skylake/gpio.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/soc/intel/skylake/gpio.c b/src/soc/intel/skylake/gpio.c index 5493cbd..3610a6c 100644 --- a/src/soc/intel/skylake/gpio.c +++ b/src/soc/intel/skylake/gpio.c @@ -383,6 +383,7 @@ void gpio_set(gpio_t gpio_num, int value) return; reg = read32(&dw_regs[0]); + reg &= ~PAD_FIELD(GPIOTXSTATE, MASK); reg |= PAD_FIELD_VAL(GPIOTXSTATE, value); write32(&dw_regs[0], reg); /* GPIO port ids support posted write semantics. */

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Patch merged into coreboot/master: intel/skylake: Clean up Serial IO DMA channels
by gerrit＠coreboot.org 29 Aug '15

29 Aug '15

the following patch was just integrated into master: commit d2d4b5a4abf5e69db3dfa84cf38d16e1f0af4747 Author: Archana Patni <archana.patni(a)intel.com> Date: Tue Jul 28 18:43:13 2015 +0530 intel/skylake: Clean up Serial IO DMA channels This patch removes FixedDMA channels carryover code from BDW as in SKL Integrated DMA is present for each serial io controller. BRANCH=None BUG=BUG=chrome-os-partner:40383 TEST=Build and Boot kunimitsu. Tested IDMA on UART. Change-Id: I66c869d310febcda430809d194b53a903a21fd99 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Original-Commit-Id: 833a1980329fb03cf487482e9276c076ede0a0fa Original-Change-Id: If6ce19cd8d60c727c8f2ffcd9bb232521df63f08 Original-Signed-off-by: Archana Patni <archana.patni(a)intel.com> Original-Signed-off-by: Subramony Sesha <subramony.sesha(a)intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/293060 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/11415 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See http://review.coreboot.org/11415 for details. -gerrit

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Patch set updated for coreboot: intel/skylake: Clean up Serial IO DMA channels
by Patrick Georgi 29 Aug '15

29 Aug '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11415 -gerrit commit 138f493ef461059e85981968296d7b631ce141ed Author: Archana Patni <archana.patni(a)intel.com> Date: Tue Jul 28 18:43:13 2015 +0530 intel/skylake: Clean up Serial IO DMA channels This patch removes FixedDMA channels carryover code from BDW as in SKL Integrated DMA is present for each serial io controller. BRANCH=None BUG=BUG=chrome-os-partner:40383 TEST=Build and Boot kunimitsu. Tested IDMA on UART. Change-Id: I66c869d310febcda430809d194b53a903a21fd99 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Original-Commit-Id: 833a1980329fb03cf487482e9276c076ede0a0fa Original-Change-Id: If6ce19cd8d60c727c8f2ffcd9bb232521df63f08 Original-Signed-off-by: Archana Patni <archana.patni(a)intel.com> Original-Signed-off-by: Subramony Sesha <subramony.sesha(a)intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/293060 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/soc/intel/skylake/acpi/serialio.asl | 64 ++------------------------------- 1 file changed, 3 insertions(+), 61 deletions(-) diff --git a/src/soc/intel/skylake/acpi/serialio.asl b/src/soc/intel/skylake/acpi/serialio.asl index 62b83e0..c6f5446 100644 --- a/src/soc/intel/skylake/acpi/serialio.asl +++ b/src/soc/intel/skylake/acpi/serialio.asl @@ -99,12 +99,6 @@ Device (I2C0) { LPSS_I2C0_IRQ } }) - /* DMA channels are only used if Serial IO DMA controller is enabled */ - Name (DBUF, ResourceTemplate () - { - FixedDMA (0x18, 4, Width32Bit, DMA1) // Tx - FixedDMA (0x19, 5, Width32Bit, DMA2) // Rx - }) Method (_CRS, 0, NotSerialized) { /* Update BAR0 address and length if set in NVS */ @@ -116,6 +110,7 @@ Device (I2C0) } Return (RBUF) } + Method (_STA, 0, NotSerialized) { If (LEqual (\S0EN, 0)) { @@ -155,14 +150,6 @@ Device (I2C1) { LPSS_I2C1_IRQ } }) - /* DMA channels are only used if - * Serial IO DMA controller is enabled - */ - Name (DBUF, ResourceTemplate () - { - FixedDMA (0x1A, 6, Width32Bit, DMA1) // Tx - FixedDMA (0x1B, 7, Width32Bit, DMA2) // Rx - }) Method (_CRS, 0, NotSerialized) { /* Update BAR0 address and length if set in NVS */ @@ -174,6 +161,7 @@ Device (I2C1) } Return (RBUF) } + Method (_STA, 0, NotSerialized) { If (LEqual (\S1EN, 0)) { @@ -212,15 +200,6 @@ Device (I2C2) { LPSS_I2C2_IRQ } }) - /* DMA channels are only used if - * Serial IO DMA controller is enabled - */ - Name (DBUF, ResourceTemplate () - { - FixedDMA (0x1A, 6, Width32Bit, DMA1) - FixedDMA (0x1B, 7, Width32Bit, DMA2) - }) - Method (_CRS, 0, NotSerialized) { /* Update BAR0 address and length if set in NVS */ @@ -231,7 +210,6 @@ Device (I2C2) Store (SIO_BAR_LEN, B0LN) } - /* Check if Serial IO DMA Controller is enabled */ Return (RBUF) } @@ -272,15 +250,6 @@ Device (I2C3) { LPSS_I2C3_IRQ } }) - /* DMA channels are only used if - * Serial IO DMA controller is enabled - */ - Name (DBUF, ResourceTemplate () - { - FixedDMA (0x1A, 6, Width32Bit, DMA1) - FixedDMA (0x1B, 7, Width32Bit, DMA2) - }) - Method (_CRS, 0, NotSerialized) { /* Update BAR0 address and length if set in NVS */ @@ -291,7 +260,6 @@ Device (I2C3) Store (SIO_BAR_LEN, B0LN) } - /* Check if Serial IO DMA Controller is enabled */ Return (RBUF) } @@ -333,15 +301,6 @@ Device (I2C4) { LPSS_I2C4_IRQ } }) - /* DMA channels are only used if - * Serial IO DMA controller is enabled - */ - Name (DBUF, ResourceTemplate () - { - FixedDMA (0x1A, 6, Width32Bit, DMA1) - FixedDMA (0x1B, 7, Width32Bit, DMA2) - }) - Method (_CRS, 0, NotSerialized) { /* Update BAR0 address and length if set in NVS*/ @@ -352,9 +311,9 @@ Device (I2C4) Store (SIO_BAR_LEN, B0LN) } - /* Check if Serial IO DMA Controller is enabled */ Return (RBUF) } + Method (_STA, 0, NotSerialized) { If (LEqual (\S4EN, 0)) { @@ -392,15 +351,6 @@ Device (I2C5) { LPSS_I2C5_IRQ } }) - /* DMA channels are only used if - * Serial IO DMA controller is enabled - */ - Name (DBUF, ResourceTemplate () - { - FixedDMA (0x1A, 6, Width32Bit, DMA1) - FixedDMA (0x1B, 7, Width32Bit, DMA2) - }) - Method (_CRS, 0, NotSerialized) { /* Update BAR0 address and length if set in NVS */ @@ -409,8 +359,6 @@ Device (I2C5) Store (0xFE02A000, B0AD) Store (SIO_BAR_LEN, B0LN) - - /* Check if Serial IO DMA Controller is enabled */ Return (RBUF) } @@ -496,12 +444,6 @@ Device (SPI1) { LPSS_SPI1_IRQ } }) - /* DMA channels are only used if Serial IO DMA controller is enabled */ - Name (DBUF, ResourceTemplate () - { - FixedDMA (0x10, 0, Width32Bit, DMA1) /* Tx */ - FixedDMA (0x11, 1, Width32Bit, DMA2) /* Rx */ - }) Method (_CRS, 0, NotSerialized) { /* Update BAR0 address and length if set in NVS */

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Patch merged into coreboot/master: intel/skylake: Force full memory train if RMT is enabled
by gerrit＠coreboot.org 29 Aug '15

29 Aug '15

the following patch was just integrated into master: commit c07cdfee080240abd80deb36e2666f0f1afe5dfa Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Mon Aug 17 18:10:54 2015 -0700 intel/skylake: Force full memory train if RMT is enabled RMT is useless if the memory does not do a full training pass, and since FSP does not seem to handle that case itself have coreboot not pass in a valid set of saved training data so FSP will do a full memory train. BUG=chrome-os-partner:40635 BRANCH=none TEST=build and boot twice on glados with p2 and RMT enabled and see it do a full memory train on each boot. Change-Id: Ia4f29a937e726a5a676f056ce8970086988da5b6 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Original-Commit-Id: f01e99204409899d4adbaebbe221b0348975cfa6 Original-Change-Id: I0bb193c5f3c9206a67315906745aad96a95b3f74 Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/294067 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/11414 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See http://review.coreboot.org/11414 for details. -gerrit

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coreboot-gerrit August 2015