Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11414
-gerrit
commit 29a879fd428a5584db5745d4e415add7a40b91eb
Author: Duncan Laurie <dlaurie(a)chromium.org>
Date: Mon Aug 17 18:10:54 2015 -0700
intel/skylake: Force full memory train if RMT is enabled
RMT is useless if the memory does not do a full training pass,
and since FSP does not seem to handle that case itself have
coreboot not pass in a valid set of saved training data so FSP
will do a full memory train.
BUG=chrome-os-partner:40635
BRANCH=none
TEST=build and boot twice on glados with p2 and RMT enabled
and see it do a full memory train on each boot.
Change-Id: Ia4f29a937e726a5a676f056ce8970086988da5b6
Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de>
Original-Commit-Id: f01e99204409899d4adbaebbe221b0348975cfa6
Original-Change-Id: I0bb193c5f3c9206a67315906745aad96a95b3f74
Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/294067
Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
---
src/soc/intel/skylake/romstage/romstage.c | 7 ++++++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/src/soc/intel/skylake/romstage/romstage.c b/src/soc/intel/skylake/romstage/romstage.c
index 91a496e..e9f0d42 100644
--- a/src/soc/intel/skylake/romstage/romstage.c
+++ b/src/soc/intel/skylake/romstage/romstage.c
@@ -103,7 +103,12 @@ void soc_memory_init_params(struct romstage_params *params,
upd->SataMode = config->SataMode;
upd->EnableTraceHub = config->EnableTraceHub;
upd->SaGv = config->SaGv;
- upd->RMT = config->Rmt;
+
+ if (config->Rmt) {
+ upd->RMT = 1;
+ /* Force a full memory train if RMT is enabled */
+ params->pei_data->disable_saved_data = 1;
+ }
}
void soc_display_memory_init_params(const MEMORY_INIT_UPD *old,
the following patch was just integrated into master:
commit 9dcd4f059b5ba5229c90385e3d384ec04cc734f5
Author: Duncan Laurie <dlaurie(a)chromium.org>
Date: Mon Aug 17 18:09:14 2015 -0700
fsp raminit: Add romstage_params to soc_memory_init_params
The SOC handler for memory init params is only taking UPD
as an input which does not allow it to use romstage_params.
In addition the UPD input is called params which is confusing
so rename it to upd so romstage_params can be passed properly.
BUG=chrome-os-partner:40635
BRANCH=none
TEST=build and boot on glados p2
Change-Id: I414610fee2b5d03a8e2cebfa548ea8bf49932a48
Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de>
Original-Commit-Id: db94d6f3e6cad721de2188a136df10ccf66aff6a
Original-Change-Id: I7ec15edd4a16df121c5967aadd8b2651267ec773
Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/294066
Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
Reviewed-on: http://review.coreboot.org/11413
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
See http://review.coreboot.org/11413 for details.
-gerrit
the following patch was just integrated into master:
commit fd016a44bb5221c0b47dc9e1b922a5290c16526c
Author: Chiranjeevi Rapolu <chiranjeevi.rapolu(a)intel.com>
Date: Tue Aug 11 14:09:46 2015 -0700
intel/braswell: allow dirty cache line evictions for SMRAM to stick
The BUNIT controls the policy for read/write access to physical
memory. For the SMRAM range the policy was not allowing dirty
evictions to the SMRAM when the core causing the eviction was not
in SMM mode. This could happen when the SMM handler dirtied a line
and then RSM'd back into non-SMM mode. The cache line was dirtied
while in SMM mode, but when that particular cache line was evicted
it would be silently dropped. Fix this by allowing the BUNIT to honor
writes to the SMRAM range while the evicting core is not in SMM mode.
The core SMRR msr provides the mechanism for disallowing general access
to the SMRAM region while it is not in SMM mode.
BUG=chrome-os-partner:43091
BRANCH=None
TEST=Run suspend_stress_test and ensure there is no hang SMI handler
on suspend-path.
Signed-off-by: Chiranjeevi Rapolu <chiranjeevi.rapolu(a)intel.com>
Change-Id: Ie794aa3afd54b5e21d0d59a2a7388d507f233537
Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de>
Original-Commit-Id: 9c481ab339b4e5ab063e2c32b1f0a48b521142b2
Original-Change-Id: I3e7d41c794c6168eb2ad4eb047675bdb1728f72f
Original-Reviewed-on: https://chromium-review.googlesource.com/292890
Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
Original-Commit-Queue: Hannah Williams <hannah.williams(a)intel.com>
Original-Tested-by: Hannah Williams <hannah.williams(a)intel.com>
Reviewed-on: http://review.coreboot.org/11412
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
See http://review.coreboot.org/11412 for details.
-gerrit
Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11412
-gerrit
commit dda53386ab99ed4687f07d6b96f89494e55681c2
Author: Chiranjeevi Rapolu <chiranjeevi.rapolu(a)intel.com>
Date: Tue Aug 11 14:09:46 2015 -0700
intel/braswell: allow dirty cache line evictions for SMRAM to stick
The BUNIT controls the policy for read/write access to physical
memory. For the SMRAM range the policy was not allowing dirty
evictions to the SMRAM when the core causing the eviction was not
in SMM mode. This could happen when the SMM handler dirtied a line
and then RSM'd back into non-SMM mode. The cache line was dirtied
while in SMM mode, but when that particular cache line was evicted
it would be silently dropped. Fix this by allowing the BUNIT to honor
writes to the SMRAM range while the evicting core is not in SMM mode.
The core SMRR msr provides the mechanism for disallowing general access
to the SMRAM region while it is not in SMM mode.
BUG=chrome-os-partner:43091
BRANCH=None
TEST=Run suspend_stress_test and ensure there is no hang SMI handler
on suspend-path.
Signed-off-by: Chiranjeevi Rapolu <chiranjeevi.rapolu(a)intel.com>
Change-Id: Ie794aa3afd54b5e21d0d59a2a7388d507f233537
Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de>
Original-Commit-Id: 9c481ab339b4e5ab063e2c32b1f0a48b521142b2
Original-Change-Id: I3e7d41c794c6168eb2ad4eb047675bdb1728f72f
Original-Reviewed-on: https://chromium-review.googlesource.com/292890
Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
Original-Commit-Queue: Hannah Williams <hannah.williams(a)intel.com>
Original-Tested-by: Hannah Williams <hannah.williams(a)intel.com>
---
src/soc/intel/braswell/cpu.c | 10 ++++++++++
src/soc/intel/braswell/include/soc/iosf.h | 6 ++++++
2 files changed, 16 insertions(+)
diff --git a/src/soc/intel/braswell/cpu.c b/src/soc/intel/braswell/cpu.c
index e648ce0..2ab8725 100644
--- a/src/soc/intel/braswell/cpu.c
+++ b/src/soc/intel/braswell/cpu.c
@@ -30,6 +30,7 @@
#include <cpu/x86/smm.h>
#include <soc/intel/common/memmap.h>
#include <reg_script.h>
+#include <soc/iosf.h>
#include <soc/msr.h>
#include <soc/pattrs.h>
#include <soc/ramstage.h>
@@ -86,6 +87,7 @@ void soc_init_cpus(device_t dev)
const struct pattrs *pattrs = pattrs_get();
struct mp_params mp_params;
void *default_smm_area;
+ uint32_t bsmrwac;
printk(BIOS_SPEW, "%s/%s ( %s )\n",
__FILE__, __func__, dev_name(dev));
@@ -104,6 +106,14 @@ void soc_init_cpus(device_t dev)
default_smm_area = backup_default_smm_area();
+ /*
+ * Configure the BUNIT to allow dirty cache line evictions in non-SMM
+ * mode for the lines that were dirtied while in SMM mode. Otherwise
+ * the writes would be silently dropped.
+ */
+ bsmrwac = iosf_bunit_read(BUNIT_SMRWAC) | SAI_IA_UNTRUSTED;
+ iosf_bunit_write(BUNIT_SMRWAC, bsmrwac);
+
/* Set package MSRs */
reg_script_run(package_msr_script);
diff --git a/src/soc/intel/braswell/include/soc/iosf.h b/src/soc/intel/braswell/include/soc/iosf.h
index 1cdfb8f..cf56a05 100644
--- a/src/soc/intel/braswell/include/soc/iosf.h
+++ b/src/soc/intel/braswell/include/soc/iosf.h
@@ -131,9 +131,15 @@ void reg_script_write_iosf(struct reg_script_context *ctx);
#define BUNIT_MMCONF_REG 0x27
#define BUNIT_BMISC 0x28
/* The SMMRR registers define the SMM region in MiB granularity. */
+#define BUNIT_SMRWAC 0x2d
#define BUNIT_SMRRL 0x2e
#define BUNIT_SMRRH 0x2f
+/* SA ID bits. */
+#define SAI_IA_UNTRUSTED (1 << 0)
+#define SAI_IA_SMM (1 << 2)
+#define SAI_IA_BOOT (1 << 4)
+
/*
* LPSS Registers
*/
the following patch was just integrated into master:
commit 4aab85be3f1475926cabd93c75b002cc73e9ba64
Author: Prince Agyeman <prince.agyeman(a)intel.com>
Date: Wed Aug 5 20:17:38 2015 -0700
intel/braswell: Adding conditional statements to turn on/off DPTF WIFI and WWAN
TEST=Builds and boot on Cyan verified by DPTF team
BUG=None
BRANCH=None
Change-Id: I38ddf4a104eb3183d424b5df6b5eab9d406327ef
Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de>
Original-Commit-Id: 47cbf3893f7d5f1dfad73f57a71ade9382b0a06a
Original-Change-Id: Ide4b3987bfa5e7ec60ee4f47d0663bb71f8330b9
Original-Signed-off-by: Prince Agyeman <prince.agyeman(a)intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/291063
Original-Commit-Queue: Prince Agyeman <popagy(a)gmail.com>
Original-Tested-by: Prince Agyeman <popagy(a)gmail.com>
Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
Reviewed-on: http://review.coreboot.org/11411
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
See http://review.coreboot.org/11411 for details.
-gerrit
the following patch was just integrated into master:
commit 1244c2c961de413a8c73914f9801dcec7e31b09d
Author: Aaron Durbin <adurbin(a)chromium.org>
Date: Thu Jul 30 13:30:03 2015 -0500
intel/braswell: remove CBFS_SIZE option in SoC directory
CBFS_SIZE is living as a mainboard attribute. Because
of the Kconfig include ordering the SoC *cannot* set
the default.
BUG=chrome-os-partner:43419
BRANCH=None
TEST=None
Change-Id: If34e8fd965573fdc7f57b63201dbcb5256e132d6
Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de>
Original-Commit-Id: a820b11a0aa3b820c79b1f76b15370d969153175
Original-Change-Id: I7ba637e66878f5ae9caedb63fdd37ed7e375224e
Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/289832
Original-Reviewed-by: Martin Roth <martinroth(a)google.com>
Original-Reviewed-by: Patrick Georgi <pgeorgi(a)chromium.org>
Reviewed-on: http://review.coreboot.org/11410
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
See http://review.coreboot.org/11410 for details.
-gerrit
Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11410
-gerrit
commit 641d190baa417dafc1439031cfe3ad9639827d5d
Author: Aaron Durbin <adurbin(a)chromium.org>
Date: Thu Jul 30 13:30:03 2015 -0500
intel/braswell: remove CBFS_SIZE option in SoC directory
CBFS_SIZE is living as a mainboard attribute. Because
of the Kconfig include ordering the SoC *cannot* set
the default.
BUG=chrome-os-partner:43419
BRANCH=None
TEST=None
Change-Id: If34e8fd965573fdc7f57b63201dbcb5256e132d6
Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de>
Original-Commit-Id: a820b11a0aa3b820c79b1f76b15370d969153175
Original-Change-Id: I7ba637e66878f5ae9caedb63fdd37ed7e375224e
Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/289832
Original-Reviewed-by: Martin Roth <martinroth(a)google.com>
Original-Reviewed-by: Patrick Georgi <pgeorgi(a)chromium.org>
---
src/soc/intel/braswell/Kconfig | 12 ------------
1 file changed, 12 deletions(-)
diff --git a/src/soc/intel/braswell/Kconfig b/src/soc/intel/braswell/Kconfig
index 4f7ed6a..a3f6025 100644
--- a/src/soc/intel/braswell/Kconfig
+++ b/src/soc/intel/braswell/Kconfig
@@ -117,18 +117,6 @@ config RESET_ON_INVALID_RAMSTAGE_CACHE
the system will reset otherwise the ramstage will be reloaded from
cbfs.
-config CBFS_SIZE
- hex "Size of CBFS filesystem in ROM"
- default 0x100000
- help
- The firmware image has to store a lot more than just coreboot,
- including:
- - a firmware descriptor
- - Intel Management Engine firmware
- - MRC cache information
- This option allows to limit the size of the CBFS portion in the
- firmware image.
-
config LOCK_MANAGEMENT_ENGINE
bool "Lock Management Engine section"
default n
the following patch was just integrated into master:
commit 5c9a71e9d5215593a75de907ce085651f1198d97
Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com>
Date: Fri Aug 28 18:49:40 2015 -0400
intel/fsp1_1/hob.c: Refactor file to match coreboot coding style
Avoid ASSERT() when a better solution exists, avoid UPPERCASE types
when C99 types exist, and use stdlib functions where possible.
Change-Id: Ia40ec8ff34ec82994b687d517dc4b145fb58716c
Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com>
Reviewed-on: http://review.coreboot.org/11455
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
See http://review.coreboot.org/11455 for details.
-gerrit