coreboot-gerrit August 2015

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Patch set updated for coreboot: f14: Increase AP stack to 8k on 64bit
by Stefan Reinauer 01 Aug '15

01 Aug '15

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11025 -gerrit commit 49431ca446d918a1abf765059259e053ad2ea064 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Tue Jul 21 14:37:13 2015 -0700 f14: Increase AP stack to 8k on 64bit This has been broken out from http://review.coreboot.org/#/c/10581/ Change-Id: Ia6153115ff75e21657fa8c244c9eb993d0d63772 Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- src/vendorcode/amd/agesa/f14/gcccar.inc | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/vendorcode/amd/agesa/f14/gcccar.inc b/src/vendorcode/amd/agesa/f14/gcccar.inc index 2104c27..8f395ce 100644 --- a/src/vendorcode/amd/agesa/f14/gcccar.inc +++ b/src/vendorcode/amd/agesa/f14/gcccar.inc @@ -42,7 +42,11 @@ BSP_STACK_SIZE = 0x10000 /* 64KB for BSP core CORE0_STACK_BASE_ADDR = 0x80000 /* Base address for primary cores stack */ CORE0_STACK_SIZE = 0x4000 /* 16KB for primary cores */ CORE1_STACK_BASE_ADDR = 0x40000 /* Base address for AP cores */ +#ifdef __x86_64__ +CORE1_STACK_SIZE = 0x2000 /* 8KB for each AP cores */ +#else CORE1_STACK_SIZE = 0x1000 /* 4KB for each AP cores */ +#endif APIC_BASE_ADDRESS = 0x0000001B APIC_BSC = 8 /* Boot Strap Core */

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Patch set updated for coreboot: DO NOT COMMIT: Enable 64bit compilation for all AGESA boards
by Stefan Reinauer 01 Aug '15

01 Aug '15

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10594 -gerrit commit df8ba50221012069a54cadba9468b96eb0cef079 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Thu Jun 18 22:05:13 2015 -0700 DO NOT COMMIT: Enable 64bit compilation for all AGESA boards This used to break lots of boards, it's basically untested. Change-Id: I8d3908557904f6dd27154e2a4b842c94974df81a Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- src/cpu/amd/agesa/Kconfig | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/src/cpu/amd/agesa/Kconfig b/src/cpu/amd/agesa/Kconfig index 282e1ed..45e1d63 100644 --- a/src/cpu/amd/agesa/Kconfig +++ b/src/cpu/amd/agesa/Kconfig @@ -27,10 +27,10 @@ config CPU_AMD_AGESA default y if CPU_AMD_AGESA_FAMILY15_RL default y if CPU_AMD_AGESA_FAMILY16_KB default n - select ARCH_BOOTBLOCK_X86_32 - select ARCH_VERSTAGE_X86_32 - select ARCH_ROMSTAGE_X86_32 - select ARCH_RAMSTAGE_X86_32 + select ARCH_BOOTBLOCK_X86_64 + select ARCH_VERSTAGE_X86_64 + select ARCH_ROMSTAGE_X86_64 + select ARCH_RAMSTAGE_X86_64 select TSC_SYNC_LFENCE select UDELAY_LAPIC select LAPIC_MONOTONIC_TIMER

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Patch set updated for coreboot: Unify OBJCOPY arguments throughout various x86 stages
by Stefan Reinauer 01 Aug '15

01 Aug '15

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11090 -gerrit commit 5273f557a6f8d9353fd72270835356eb111eaf0d Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Thu Jul 30 18:03:18 2015 -0700 Unify OBJCOPY arguments throughout various x86 stages Instead of having to have an ifeq() all across the code base, use $(target-objcopy). And correct target-objcopy to a value that objcopy actually understands. Change-Id: Id5dea6420bee02a044dc488b5086d109e806d605 Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- src/arch/x86/Makefile.inc | 8 ++++---- src/cpu/x86/Makefile.inc | 6 +----- src/cpu/x86/smm/Makefile.inc | 12 ++---------- 3 files changed, 7 insertions(+), 19 deletions(-) diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index d5b320f..c333d9a 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -252,16 +252,16 @@ endif # CONFIG_ARCH_ROMSTAGE_X86_32 / CONFIG_ARCH_ROMSTAGE_X86_64 ifeq ($(CONFIG_ARCH_RAMSTAGE_X86_32)$(CONFIG_ARCH_RAMSTAGE_X86_64),y) -ifeq ($(CONFIG_COMPILE_IN_DSDT),y) -ramstage-srcs += $(obj)/dsdt.aml - ifeq ($(CONFIG_ARCH_RAMSTAGE_X86_32),y) target-objcopy=-O elf32-i386 -B i386 endif ifeq ($(CONFIG_ARCH_RAMSTAGE_X86_64),y) -target-objcopy=-O elf64-x86_64 -B x86_64 +target-objcopy=-O elf64-x86-64 -B i386:x86-64 endif +ifeq ($(CONFIG_COMPILE_IN_DSDT),y) +ramstage-srcs += $(obj)/dsdt.aml + define ramstage-objs_aml_template $(call src-to-obj,ramstage,$(1).aml): $(1).aml @printf " OBJCOPY $$(subst $$(obj)/,,$$(@))\n" diff --git a/src/cpu/x86/Makefile.inc b/src/cpu/x86/Makefile.inc index 9ec0768..fb9ea2d 100644 --- a/src/cpu/x86/Makefile.inc +++ b/src/cpu/x86/Makefile.inc @@ -30,8 +30,4 @@ $(SIPI_BIN): $(SIPI_RMOD) $(SIPI_BIN).ramstage.manual: $(SIPI_BIN) @printf " OBJCOPY $(subst $(obj)/,,$(@))\n" -ifeq ($(CONFIG_ARCH_RAMSTAGE_X86_32),y) - cd $(dir $@); $(OBJCOPY_rmodules_$(ARCH-ramstage-y)) -I binary $(notdir $<) -O elf32-i386 -B i386 $(notdir $@) -else - cd $(dir $@); $(OBJCOPY_rmodules_$(ARCH-ramstage-y)) -I binary $(notdir $<) -O elf64-x86_64 -B x86_64 $(notdir $@) -endif + cd $(dir $@); $(OBJCOPY_rmodules_$(ARCH-ramstage-y)) -I binary $(notdir $<) $(target-objcopy) $(notdir $@) diff --git a/src/cpu/x86/smm/Makefile.inc b/src/cpu/x86/smm/Makefile.inc index 2e61018..adf9b38 100644 --- a/src/cpu/x86/smm/Makefile.inc +++ b/src/cpu/x86/smm/Makefile.inc @@ -38,11 +38,7 @@ $(obj)/cpu/x86/smm/smm.o: $$(smm-objs) $(COMPILER_RT_smm) # ELF symbol names. $(obj)/cpu/x86/smm/smm.ramstage.manual: $(obj)/cpu/x86/smm/smm @printf " OBJCOPY $(subst $(obj)/,,$(@))\n" -ifeq ($(CONFIG_ARCH_RAMSTAGE_X86_32),y) - cd $(dir $@); $(OBJCOPY_smm) -I binary $(notdir $<) -O elf32-i386 -B i386 $(notdir $@) -else - cd $(dir $@); $(OBJCOPY_smm) -I binary $(notdir $<) -O elf64-x86_64 -B x86_64 $(notdir $@) -endif + cd $(dir $@); $(OBJCOPY_smm) -I binary $(notdir $<) $(target-objcopy) $(notdir $@) ifeq ($(CONFIG_SMM_TSEG),y) @@ -72,11 +68,7 @@ $(obj)/cpu/x86/smm/smmstub: $(obj)/cpu/x86/smm/smmstub.elf.rmod $(obj)/cpu/x86/smm/smmstub.ramstage.manual: $(obj)/cpu/x86/smm/smmstub @printf " OBJCOPY $(subst $(obj)/,,$(@))\n" -ifeq ($(CONFIG_ARCH_RAMSTAGE_X86_32),y) - cd $(dir $@); $(OBJCOPY_smmstub) -I binary $(notdir $<) -O elf32-i386 -B i386 $(notdir $@) -else - cd $(dir $@); $(OBJCOPY_smmstub) -I binary $(notdir $<) -O elf64-x86_64 -B x86_64 $(notdir $@) -endif + cd $(dir $@); $(OBJCOPY_smmstub) -I binary $(notdir $<) $(target-objcopy) $(notdir $@) # C-based SMM handler.

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Patch set updated for coreboot: Random x86_64 fixes from Scott
by Stefan Reinauer 01 Aug '15

01 Aug '15

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11107 -gerrit commit 0eff030a97dd8f520709a4412400c01fceff8352 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Fri Jul 31 16:44:03 2015 -0700 Random x86_64 fixes from Scott Need to figure out what to do with these Change-Id: I6ed295131347796b27e660ccf3fca0de22801069 Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Signed-off-by: Scott Duplichan <scott(a)notabs.org> --- src/lib/ramstage.ld | 3 ++- src/southbridge/amd/cimx/sb800/smbus_spd.c | 2 +- src/vendorcode/amd/agesa/f14/Proc/CPU/cahaltasm.S | 5 +++++ src/vendorcode/amd/agesa/f14/Proc/CPU/cpuApicUtilities.c | 8 ++++++++ 4 files changed, 16 insertions(+), 2 deletions(-) diff --git a/src/lib/ramstage.ld b/src/lib/ramstage.ld index 432df40..c5719d6 100644 --- a/src/lib/ramstage.ld +++ b/src/lib/ramstage.ld @@ -59,6 +59,7 @@ cpu_drivers = . ; KEEP(*(.rodata.cpu_driver)); ecpu_drivers = . ; + . = ALIGN(16); _bs_init_begin = .; KEEP(*(.bs_init)); LONG(0); @@ -100,7 +101,7 @@ _heap = .; /* Reserve CONFIG_HEAP_SIZE bytes for the heap */ . += CONFIG_HEAP_SIZE ; - . = ALIGN(4); + . = ALIGN(8); _eheap = .; _eramstage = .; _eprogram = .; diff --git a/src/southbridge/amd/cimx/sb800/smbus_spd.c b/src/southbridge/amd/cimx/sb800/smbus_spd.c index 1e458bd..052ee31 100644 --- a/src/southbridge/amd/cimx/sb800/smbus_spd.c +++ b/src/southbridge/amd/cimx/sb800/smbus_spd.c @@ -100,7 +100,7 @@ static UINT8 readspd(UINT16 iobase, UINT8 SmbusSlaveAddress, char *buffer, UINT16 count) { UINT16 index; - UINT8 status; + UINT8 status = 0; UINT8 initial_offset = 0; setupFch(iobase); diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/cahaltasm.S b/src/vendorcode/amd/agesa/f14/Proc/CPU/cahaltasm.S index 48ee5d0..9701087 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/CPU/cahaltasm.S +++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/cahaltasm.S @@ -75,6 +75,11 @@ ExecuteFinalHltInstruction: bt $0, %esi /* .if (esi & 1h) */ jz 2f +#ifdef __x86_64__ + /* hack to protect cache as ram page tables until copied to memory */ + jmp 7f +#endif + /* This core is a primary core and needs to do all the MTRRs, including shared MTRRs. */ movl %edi, %esi /* Get ApMtrrSettingList */ diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/cpuApicUtilities.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/cpuApicUtilities.c index ebcb58e..807a518 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/CPU/cpuApicUtilities.c +++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/cpuApicUtilities.c @@ -852,6 +852,10 @@ ApUtilSetupIdtForHlt ( UINT64 HandlerOffset; UINT64 EferRegister; IDT_BASE_LIMIT IdtInfo; +#ifdef __x86_64__ + // old way doesn't work with the -Og build + static const UINT8 iretOpcode [] = {/*0xEB, 0xFE,*/ 0x48, 0xCF}; // iretq +#endif LibAmdMsrRead (MSR_EXTENDED_FEATURE_EN, &EferRegister, StdHeader); if ((EferRegister & 0x100) != 0) { @@ -860,7 +864,11 @@ ApUtilSetupIdtForHlt ( DescSize = 8; } +#ifdef __x86_64__ + HandlerOffset = (UINT64) (intptr_t) &iretOpcode; +#else HandlerOffset = (UINT64) (intptr_t) &NmiHandler; +#endif NmiIdtDescPtr->OffsetLo = (UINT16) (HandlerOffset & 0xFFFF); NmiIdtDescPtr->OffsetHi = (UINT16) ((HandlerOffset >> 16) & 0xFFFF); GetCsSelector (&NmiIdtDescPtr->Selector, StdHeader);

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coreboot-gerrit August 2015