Patch merged into coreboot/master: buildgcc: Get the clean and correct uname on Cygwin
by gerrit＠coreboot.org 06 Aug '15
by gerrit＠coreboot.org 06 Aug '15
06 Aug '15
the following patch was just integrated into master:
commit e05c1eac44443f566af3909831328806bb8cd49a
Author: zbao <fishbaozi(a)gmail.com>
Date: Wed Aug 5 23:10:05 2015 -0400
buildgcc: Get the clean and correct uname on Cygwin
Running `uname` on Cygwin gets "CYGWIN_NT-6.1-WOW" instead of "Cygwin".
We need to fix the $UNAME on Cygwin.
Change-Id: I540bfc52089951006fd0e20bb9893a3d891df9e1
Signed-off-by: Zheng Bao <zheng.bao(a)amd.com>
Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com>
Reviewed-on: http://review.coreboot.org/11124
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org>
See http://review.coreboot.org/11124 for details.
-gerrit
1
0
New patch to review for coreboot: buildgcc: Get the clean and correct uname on Cygwin
by Zheng Bao 06 Aug '15
by Zheng Bao 06 Aug '15
06 Aug '15
Zheng Bao (zheng.bao(a)amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11124
-gerrit
commit 0ae65aac63cb2dd4e44bfa927e5982e13a3d91aa
Author: zbao <fishbaozi(a)gmail.com>
Date: Wed Aug 5 23:10:05 2015 -0400
buildgcc: Get the clean and correct uname on Cygwin
Running `uname` on Cygwin gets "CYGWIN_NT-6.1-WOW" instead of "Cygwin".
We need to fix the $UNAME on Cygwin.
Change-Id: I540bfc52089951006fd0e20bb9893a3d891df9e1
Signed-off-by: Zheng Bao <zheng.bao(a)amd.com>
Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com>
---
util/crossgcc/buildgcc | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc
index 590e1f8..cfe881b 100755
--- a/util/crossgcc/buildgcc
+++ b/util/crossgcc/buildgcc
@@ -94,7 +94,7 @@ cyan='\033[0;36m'
CYAN='\033[1;36m'
NC='\033[0m' # No Color
-UNAME=$(uname)
+UNAME=$(uname | grep -iq cygwin && echo Cygwin || uname)
normalize_dirs()
{
1
0
Patch set updated for coreboot: buildgcc: Deal with gmp on 32bit Cygwin on 64bit host
by Zheng Bao 06 Aug '15
by Zheng Bao 06 Aug '15
06 Aug '15
Zheng Bao (zheng.bao(a)amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11123
-gerrit
commit 13b766691091cc73636de4a1f30f2f3b8162bdd7
Author: zbao <fishbaozi(a)gmail.com>
Date: Wed Aug 5 23:15:54 2015 -0400
buildgcc: Deal with gmp on 32bit Cygwin on 64bit host
Similar to what the below change says,
(
http://review.coreboot.org/10792
commit ddb8f808940899240411282d0feb1e2f65ef43a9
Author: Patrick Georgi <patrick(a)georgi-clan.de>
Date: Sat Jul 4 17:45:54 2015 +0200
buildgcc: Deal with gmp on 32bit Linux on 64bit CPUs
GMP is overeager to detect 64bit ABIs even if the entire running codebase is
32bit (but on a 64bit CPU). Enforce a 32bit build in that situation.
)
building GMP can not detect Cygwin is 32bit either if the
host which Cygwin is running is 64bit. We set ABI=32
in that case.
Change-Id: Ic53d75defebbe902325eb07f3d8631b2a53245ef
Signed-off-by: Zheng Bao <zheng.bao(a)amd.com>
Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com>
---
util/crossgcc/buildgcc | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc
index cfe881b..eaeafcf 100755
--- a/util/crossgcc/buildgcc
+++ b/util/crossgcc/buildgcc
@@ -622,7 +622,7 @@ if [ $UNAME = "Darwin" ]; then
if $CC -v 2>&1 | grep -q LLVM; then
CC=llvm-gcc
fi
-elif [ $UNAME = "Linux" ]; then
+elif [ $UNAME = "Linux" -o $UNAME = "Cygwin" ]; then
# gmp is overeager with detecting 64bit CPUs even if they run
# a 32bit kernel and userland.
if [ "$(uname -m 2>/dev/null)" = "i686" ]; then
1
0
Patch set updated for coreboot: documentation: Add documentation for timestamp library
by Marc Jones 05 Aug '15
by Marc Jones 05 Aug '15
05 Aug '15
Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10741
-gerrit
commit 9ba9df22bd3105f3a3532b608d4c556c9a9bb210
Author: Furquan Shaikh <furquan(a)google.com>
Date: Fri Nov 14 11:57:00 2014 -0800
documentation: Add documentation for timestamp library
[pg: removed discussion of timestamp internals that isn't current anymore in
favor of some notes for users: when to run which function, what _not_ to do.
Also moved to markdown-ish layout. Will do further style cleanups later.]
BUG=chrome-os-partner:32973
BRANCH=None
TEST=None
Change-Id: I6ea7237f2fa749ce3a493f378f9937e642f3b678
Signed-off-by: Marc Jones <marc.jones(a)se-eng.com>
Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org>
Original-Commit-Id: 97e2a3ebd9552c2a91d9ea62be515059428631cb
Original-Change-Id: I4b184ffad6fcd93d63343a9bca34ad013e9d4263
Original-Signed-off-by: Furquan Shaikh <furquan(a)google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/229861
Original-Tested-by: Furquan Shaikh <furquan(a)chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan(a)chromium.org>
---
Documentation/timestamp.md | 200 +++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 200 insertions(+)
diff --git a/Documentation/timestamp.md b/Documentation/timestamp.md
new file mode 100644
index 0000000..3a4c73b
--- /dev/null
+++ b/Documentation/timestamp.md
@@ -0,0 +1,200 @@
+Table of Contents
+=================
+Introduction
+ Transition from cache to cbmem
+
+Data structures used
+ cache_state
+ table
+ entries
+
+Function APIs
+ timestamp_init
+ timestamp_add
+ timestamp_add_now
+ timestamp_sync
+
+Use / Test Cases
+ Case 1: Timestamp Region Exists
+ Case 2: No timestamp region, fresh boot, cbmem_initialize called after
+ timestamp_init
+ Case 3: No timestamp region, fresh boot, cbmem_initialize called before
+ timestamp_init
+ Case 4: No timestamp region, resume, cbmem_initialize called after
+ timestamp_init
+ Case 5: No timestamp region, resume, cbmem_initialize called before
+ timestamp_init
+
+
+Introduction
+============
+The aim of the timestamp library is to make it easier for different boards
+to save timestamps in cbmem / stash (until cbmem is brought up) by
+providing a simple API to initialize, add and sync timestamps. In order
+to make the timestamps persistent and accessible from the kernel, we
+need to ensure that all the saved timestamps end up in cbmem under
+the CBMEM_ID_TIMESTAMP tag. However, until the cbmem area is available,
+the timestamps can be saved to a SoC-defined \_timestamp region or in a
+local stage-specific stash. The work of identifying the right location for
+storing timestamps is done by the library and is not exposed to the user.
+
+Working of timestamp library from a user perspective can be outlined in
+the following steps:
+1. Initialize the base time and reset cbmem timestamp area
+2. Start adding timestamps
+
+Behind the scenes, the timestamp library takes care of:
+1. Identifying the correct location for storing timestamps (cbmem or timestamp
+ region or local stash).
+2. Once cbmem is up, ensure that all timestamps are synced from timestamp
+ region or local stash into the cbmem area.
+3. Add a new cbmem timestamp area based on whether a reset of the cbmem
+ timestamp region is required or not.
+
+Transition from cache to cbmem
+------------------------------
+To move timestamps from the cache to cbmem (and initialize the cbmem area in
+the first place), we use the CBMEM_INIT_HOOK infrastructure of coreboot.
+
+When cbmem is initialized, the hook is called, which creates the area,
+copies all timestamps to cbmem and disables the cache.
+
+After such a transition, timestamp_init() must not be run again.
+
+
+Data structures used
+====================
+The main structure that maintains information about the timestamp cache is:
+struct __attribute__((__packed__)) timestamp_cache {
+ uint16_t cache_state;
+ struct timestamp_table table;
+ struct timestamp_entry entries[MAX_TIMESTAMP_CACHE];
+};
+
+cache_state
+-----------
+The state of the cache is maintained by cache_state attribute which can
+be any one of the following:
+
+enum {
+ TIMESTAMP_CACHE_UNINITIALIZED = 0,
+ TIMESTAMP_CACHE_INITIALIZED,
+ TIMESTAMP_CACHE_NOT_NEEDED,
+};
+
+By default, if the cache is stored in local stash (bss area), then
+it will be reset to uninitialized state. However, if the cache is
+stored in timestamp region, then it might have garbage in any of the
+attributes. Thus, if the timestamp region is being used by any board, it is
+initialized to default values by the library.
+
+Once the cache is initialized, its state is set to
+CACHE_INITIALIZED. Henceforth, the calls to cache i.e. timestamp_add
+know that the state reflected is valid and timestamps can be directly
+saved in the cache.
+
+Once the cbmem area is up (i.e. call to timestamp_sync_cache_to_cbmem),
+we do not need to store the timestamps in local stash / timestamp area
+anymore. Thus, the cache state is set to CACHE_NOT_NEEDED, which allows
+timestamp_add to store all timestamps directly into the cbmem area.
+
+
+table
+-----
+This field is represented by a structure which provides overall
+information about the entries in the timestamp area:
+
+struct timestamp_table {
+ uint64_t base_time;
+ uint32_t max_entries;
+ uint32_t num_entries;
+ struct timestamp_entry entries[0]; /* Variable number of entries */
+} __attribute__((packed));
+
+It indicates the base time for all timestamp entries, maximum number
+of entries that can be stored, total number of entries that currently
+exist and an entry structure to hold variable number of entries.
+
+
+entries
+-------
+This field holds the details of each timestamp entry, upto a maximum
+of MAX_TIMESTAMP_CACHE which is defined as 16 entries. Each entry is
+defined by:
+
+struct timestamp_entry {
+ uint32_t entry_id;
+ uint64_t entry_stamp;
+} __attribute__((packed));
+
+entry_id holds the timestamp id corresponding to this entry and
+entry_stamp holds the actual timestamp.
+
+
+For timestamps stored in the cbmem area, a timestamp_table is allocated
+with space for MAX_TIMESTAMPS equal to 30. Thus, the cbmem area holds
+base_time, max_entries (which is 30), current number of entries and the
+actual entries represented by timestamp_entry.
+
+
+Function APIs
+=============
+
+timestamp_init
+--------------
+This function initializes the timestamp cache and should be run as early
+as possible. On platforms with SRAM, this might mean in bootblock, on
+x86 with its CAR backed memory in romstage, this means romstage before
+memory init.
+
+timestamp_add
+-------------
+This function accepts from user a timestamp id and time to record in the
+timestamp table. It stores the entry in the appropriate table in cbmem
+or _timestamp region or local stash.
+
+
+timestamp_add_now
+-----------------
+This function calls timestamp_add with user-provided id and current time.
+
+
+Use / Test Cases
+================
+
+The following cases have been considered while designing the timestamp
+library. It is important to ensure that any changes made to this library satisfy
+each of the following use cases:
+
+Case 1: Timestamp Region Exists (Fresh Boot / Resume)
+-----------------------------------------------------
+
+In this case, the library needs to call timestamp_init as early as possible to
+enable the timestamp cache. Once cbmem is available, the values will be
+transferred automatically.
+
+All regions are automatically reset on initialization.
+
+Case 2: No timestamp region, fresh boot, cbmem_initialize called after timestamp_init
+-------------------------------------------------------------------------------------
+
+timestamp_init will set up a local cache. cbmem must be initialized before that
+cache vanishes - as happens when jumping to the next stage.
+
+Case 3: No timestamp region, fresh boot, cbmem_initialize called before timestamp_init
+--------------------------------------------------------------------------------------
+
+This case is not supported right now, just don't call timestamp_init after
+cbmem_initialize. (Patches to make this more robust are welcome.)
+
+Case 4: No timestamp region, resume, cbmem_initialize called after timestamp_init
+---------------------------------------------------------------------------------
+
+We always reset the cbmem region before using it, so pre-suspend timestamps
+will be gone.
+
+Case 5: No timestamp region, resume, cbmem_initialize called before timestamp_init
+----------------------------------------------------------------------------------
+
+We always reset the cbmem region before using it, so pre-suspend timestamps
+will be gone.
1
0
Patch set updated for coreboot: vendorcode: Move AMD sources from blobs to vendorcode
by Marc Jones 05 Aug '15
by Marc Jones 05 Aug '15
05 Aug '15
Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10982
-gerrit
commit 3e03ef4da715dd25d7c02149a3b78cde6a096db8
Author: Marc Jones <marc.jones(a)se-eng.com>
Date: Sun Jul 19 15:20:17 2015 -0600
vendorcode: Move AMD sources from blobs to vendorcode
The AMD AGESA binaryPI sources were incorrectly committed to
3rdparty/blobs. Move them from blobs to vendorcode and fix
Kconfig and Makefile.inc to match.
Change-Id: I55a777553c1203464d7f7f4293b361fedcfa3283
Signed-off-by: Marc Jones <marc.jones(a)se-eng.com>
---
src/vendorcode/amd/pi/00630F01/AGESA.h | 3641 ++++++++++++++++++
src/vendorcode/amd/pi/00630F01/AMD.h | 475 +++
src/vendorcode/amd/pi/00630F01/Dispatcher.h | 51 +
src/vendorcode/amd/pi/00630F01/Include/Filecode.h | 781 ++++
src/vendorcode/amd/pi/00630F01/Include/Ids.h | 1428 +++++++
src/vendorcode/amd/pi/00630F01/Include/IdsPerf.h | 138 +
src/vendorcode/amd/pi/00630F01/Include/Options.h | 68 +
.../00630F01/Include/PlatformMemoryConfiguration.h | 515 +++
src/vendorcode/amd/pi/00630F01/Include/Topology.h | 86 +
src/vendorcode/amd/pi/00630F01/Porting.h | 299 ++
.../pi/00630F01/Proc/CPU/Family/cpuFamRegisters.h | 110 +
.../pi/00630F01/Proc/CPU/Feature/cpuCacheInit.h | 138 +
.../amd/pi/00630F01/Proc/CPU/cpuApicUtilities.h | 303 ++
.../amd/pi/00630F01/Proc/CPU/cpuEarlyInit.h | 290 ++
.../amd/pi/00630F01/Proc/CPU/cpuLateInit.h | 1141 ++++++
.../amd/pi/00630F01/Proc/CPU/cpuRegisters.h | 479 +++
.../amd/pi/00630F01/Proc/CPU/heapManager.h | 258 ++
.../amd/pi/00630F01/Proc/Common/AmdFch.h | 65 +
.../amd/pi/00630F01/Proc/Fch/Common/AcpiLib.h | 91 +
.../pi/00630F01/Proc/Fch/Common/FchBiosRamUsage.h | 67 +
.../amd/pi/00630F01/Proc/Fch/Common/FchCommonCfg.h | 1282 +++++++
.../amd/pi/00630F01/Proc/Fch/Common/FchDef.h | 477 +++
src/vendorcode/amd/pi/00630F01/Proc/Fch/Fch.h | 2285 ++++++++++++
.../amd/pi/00630F01/Proc/Fch/FchPlatform.h | 118 +
.../amd/pi/00630F01/Proc/IDS/Debug/IdsDebugPrint.h | 80 +
.../amd/pi/00630F01/Proc/IDS/Debug/IdsDpHdtout.h | 119 +
.../amd/pi/00630F01/Proc/IDS/Debug/IdsDpRam.h | 73 +
.../Proc/IDS/Family/0x15/IdsF15AllService.h | 49 +
.../Proc/IDS/Family/0x15/KV/IdsF15KvAllService.h | 49 +
.../Proc/IDS/Family/0x15/KV/IdsF15KvNvDef.h | 287 ++
.../Proc/IDS/Family/0x15/TN/IdsF15TnAllService.h | 49 +
.../Proc/IDS/Family/0x15/TN/IdsF15TnNvDef.h | 287 ++
src/vendorcode/amd/pi/00630F01/Proc/IDS/IdsLib.h | 381 ++
.../amd/pi/00630F01/Proc/IDS/OptionsIds.h | 92 +
src/vendorcode/amd/pi/00630F01/binaryPI/AGESA.c | 696 ++++
.../amd/pi/00630F01/binaryPI/FieldAccessors.h | 111 +
.../amd/pi/00630F01/binaryPI/gcc-intrin.h | 833 +++++
src/vendorcode/amd/pi/00630F01/binaryPI/gcccar.inc | 1596 ++++++++
src/vendorcode/amd/pi/00660F01/AGESA.h | 3889 ++++++++++++++++++++
src/vendorcode/amd/pi/00660F01/AMD.h | 476 +++
src/vendorcode/amd/pi/00660F01/Dispatcher.h | 51 +
src/vendorcode/amd/pi/00660F01/Include/Filecode.h | 648 ++++
.../amd/pi/00660F01/Include/GeneralServices.h | 222 ++
src/vendorcode/amd/pi/00660F01/Include/Ids.h | 1484 ++++++++
src/vendorcode/amd/pi/00660F01/Include/IdsPerf.h | 145 +
src/vendorcode/amd/pi/00660F01/Include/Options.h | 68 +
.../00660F01/Include/PlatformMemoryConfiguration.h | 530 +++
src/vendorcode/amd/pi/00660F01/Include/Topology.h | 86 +
src/vendorcode/amd/pi/00660F01/Porting.h | 286 ++
.../pi/00660F01/Proc/CPU/Family/cpuFamRegisters.h | 92 +
.../pi/00660F01/Proc/CPU/Feature/cpuCacheInit.h | 137 +
.../amd/pi/00660F01/Proc/CPU/cpuEarlyInit.h | 213 ++
.../amd/pi/00660F01/Proc/CPU/cpuLateInit.h | 1045 ++++++
.../amd/pi/00660F01/Proc/CPU/cpuRegisters.h | 502 +++
.../amd/pi/00660F01/Proc/CPU/heapManager.h | 241 ++
.../amd/pi/00660F01/Proc/Common/AmdFch.h | 63 +
.../amd/pi/00660F01/Proc/Fch/Common/AcpiLib.h | 90 +
.../pi/00660F01/Proc/Fch/Common/FchBiosRamUsage.h | 66 +
.../amd/pi/00660F01/Proc/Fch/Common/FchCommonCfg.h | 1359 +++++++
.../amd/pi/00660F01/Proc/Fch/Common/FchDef.h | 421 +++
.../amd/pi/00660F01/Proc/Fch/Common/FchLib.c | 672 ++++
.../amd/pi/00660F01/Proc/Fch/Common/FchPeLib.c | 310 ++
.../amd/pi/00660F01/Proc/Fch/Common/MemLib.c | 144 +
.../amd/pi/00660F01/Proc/Fch/Common/PciLib.c | 93 +
src/vendorcode/amd/pi/00660F01/Proc/Fch/Fch.h | 2603 +++++++++++++
.../amd/pi/00660F01/Proc/Fch/FchPlatform.h | 117 +
.../amd/pi/00660F01/Proc/Fch/Kern/KernFch.h | 200 +
.../pi/00660F01/Proc/Psp/PspBaseLib/PspBaseLib.c | 464 +++
.../pi/00660F01/Proc/Psp/PspBaseLib/PspBaseLib.h | 187 +
.../pi/00660F01/Proc/Psp/PspBaseLib/PspDirectory.h | 94 +
src/vendorcode/amd/pi/00660F01/binaryPI/AGESA.c | 543 +++
.../amd/pi/00660F01/binaryPI/FieldAccessors.h | 118 +
.../amd/pi/00660F01/binaryPI/OptionsIds.h | 124 +
.../amd/pi/00660F01/binaryPI/gcc-intrin.h | 744 ++++
src/vendorcode/amd/pi/00660F01/binaryPI/gcccar.inc | 1335 +++++++
src/vendorcode/amd/pi/00730F01/AGESA.h | 3657 ++++++++++++++++++
src/vendorcode/amd/pi/00730F01/AMD.h | 474 +++
src/vendorcode/amd/pi/00730F01/Dispatcher.h | 51 +
src/vendorcode/amd/pi/00730F01/Include/Filecode.h | 823 +++++
src/vendorcode/amd/pi/00730F01/Include/Ids.h | 1433 ++++++++
src/vendorcode/amd/pi/00730F01/Include/IdsPerf.h | 141 +
src/vendorcode/amd/pi/00730F01/Include/Options.h | 67 +
.../00730F01/Include/PlatformMemoryConfiguration.h | 516 +++
src/vendorcode/amd/pi/00730F01/Include/Topology.h | 86 +
src/vendorcode/amd/pi/00730F01/Porting.h | 307 ++
.../pi/00730F01/Proc/CPU/Family/cpuFamRegisters.h | 144 +
.../pi/00730F01/Proc/CPU/Feature/cpuCacheInit.h | 137 +
.../amd/pi/00730F01/Proc/CPU/cpuApicUtilities.h | 302 ++
.../amd/pi/00730F01/Proc/CPU/cpuEarlyInit.h | 289 ++
.../amd/pi/00730F01/Proc/CPU/cpuLateInit.h | 1140 ++++++
.../amd/pi/00730F01/Proc/CPU/cpuRegisters.h | 467 +++
.../amd/pi/00730F01/Proc/CPU/heapManager.h | 258 ++
.../amd/pi/00730F01/Proc/Common/AmdFch.h | 63 +
.../amd/pi/00730F01/Proc/Fch/Common/AcpiLib.h | 91 +
.../pi/00730F01/Proc/Fch/Common/FchBiosRamUsage.h | 67 +
.../amd/pi/00730F01/Proc/Fch/Common/FchCommonCfg.h | 1296 +++++++
.../amd/pi/00730F01/Proc/Fch/Common/FchDef.h | 400 ++
src/vendorcode/amd/pi/00730F01/Proc/Fch/Fch.h | 2318 ++++++++++++
.../amd/pi/00730F01/Proc/Fch/FchPlatform.h | 118 +
src/vendorcode/amd/pi/00730F01/binaryPI/AGESA.c | 691 ++++
.../amd/pi/00730F01/binaryPI/FieldAccessors.h | 111 +
.../amd/pi/00730F01/binaryPI/OptionsIds.h | 44 +
.../amd/pi/00730F01/binaryPI/gcc-intrin.h | 833 +++++
src/vendorcode/amd/pi/00730F01/binaryPI/gcccar.inc | 1311 +++++++
src/vendorcode/amd/pi/Kconfig | 16 +-
src/vendorcode/amd/pi/Makefile.inc | 4 +-
106 files changed, 56795 insertions(+), 10 deletions(-)
diff --git a/src/vendorcode/amd/pi/00630F01/AGESA.h b/src/vendorcode/amd/pi/00630F01/AGESA.h
new file mode 100644
index 0000000..1ef9e97
--- /dev/null
+++ b/src/vendorcode/amd/pi/00630F01/AGESA.h
@@ -0,0 +1,3641 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Agesa structures and definitions
+ *
+ * Contains AMD AGESA core interface
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: Include
+ * @e \$Revision: 296129 $ @e \$Date: 2014-06-23 09:45:14 -0500 (Mon, 23 Jun 2014) $
+ */
+/*****************************************************************************
+ *
+ * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ***************************************************************************/
+
+
+#ifndef _AGESA_H_
+#define _AGESA_H_
+
+#include "Porting.h"
+#include "AMD.h"
+
+//
+//
+// AGESA Types and Definitions
+//
+//
+
+// AGESA BASIC CALLOUTS
+#define AGESA_MEM_RELEASE 0x00028000ul
+
+// AGESA ADVANCED CALLOUTS, Processor
+#define AGESA_CHECK_UMA 0x00028100ul
+#define AGESA_DO_RESET 0x00028101ul
+#define AGESA_ALLOCATE_BUFFER 0x00028102ul
+#define AGESA_DEALLOCATE_BUFFER 0x00028103ul
+#define AGESA_LOCATE_BUFFER 0x00028104ul
+#define AGESA_RUNFUNC_ONAP 0x00028105ul
+
+// AGESA ADVANCED CALLOUTS, Memory
+#define AGESA_READ_SPD 0x00028140ul
+#define AGESA_HOOKBEFORE_DRAM_INIT 0x00028141ul
+#define AGESA_HOOKBEFORE_DQS_TRAINING 0x00028142ul
+#define AGESA_READ_SPD_RECOVERY 0x00028143ul
+#define AGESA_HOOKBEFORE_EXIT_SELF_REF 0x00028144ul
+#define AGESA_HOOKBEFORE_DRAM_INIT_RECOVERY 0x00028145ul
+#define AGESA_EXTERNAL_2D_TRAIN_VREF_CHANGE 0x00028146ul
+#define AGESA_EXTERNAL_VOLTAGE_ADJUST 0x00028147ul
+
+// AGESA IDS CALLOUTS
+#define AGESA_GET_IDS_INIT_DATA 0x00028200ul
+
+// AGESA GNB CALLOUTS
+#define AGESA_GNB_PCIE_SLOT_RESET 0x00028301ul
+#define AGESA_GNB_GFX_GET_VBIOS_IMAGE 0x00028302ul
+#define AGESA_GNB_PCIE_CLK_REQ 0x00028303ul
+
+// AGESA FCH CALLOUTS
+#define AGESA_FCH_OEM_CALLOUT 0x00028401ul
+
+//-----------------------------------------------------------------------------
+// FCH DEFINITIONS AND MACROS
+//
+//-----------------------------------------------------------------------------
+
+/// Configuration values for SdConfig
+typedef enum {
+ SdDisable = 0, ///< Disabled
+ SdAmda, ///< AMDA, set 24,18,16, default
+ SdDma, ///< DMA clear 24, 16, set 18
+ SdPio, ///< PIO clear 24,18,16
+ SdDump ///< SD DUMP, don't touch SD
+} SD_MODE;
+
+/// Configuration values for SdClockControl
+typedef enum {
+ Sd50MhzTraceCableLengthWithinSixInches = 4, ///< 50Mhz, default
+ Sd40MhzTraceCableLengthSix2ElevenInches = 6, ///< 40Mhz
+ Sd25MhzTraceCableLengthEleven2TwentyfourInches = 7, ///< 25Mhz
+} SD_CLOCK_CONTROL;
+
+/// Configuration values for AzaliaController
+typedef enum {
+ AzAuto = 0, ///< Auto - Detect Azalia controller automatically
+ AzDisable, ///< Diable - Disable Azalia controller
+ AzEnable ///< Enable - Enable Azalia controller
+} HDA_CONFIG;
+
+/// Configuration values for IrConfig
+typedef enum {
+ IrDisable = 0, ///< Disable
+ IrRxTx0 = 1, ///< Rx and Tx0
+ IrRxTx1 = 2, ///< Rx and Tx1
+ IrRxTx0Tx1 = 3 ///< Rx and both Tx0,Tx1
+} IR_CONFIG;
+
+/// Configuration values for SataClass
+typedef enum {
+ SataNativeIde = 0, ///< Native IDE mode
+ SataRaid, ///< RAID mode
+ SataAhci, ///< AHCI mode
+ SataLegacyIde, ///< Legacy IDE mode
+ SataIde2Ahci, ///< IDE->AHCI mode
+ SataAhci7804, ///< AHCI mode as 7804 ID (AMD driver)
+ SataIde2Ahci7804 ///< IDE->AHCI mode as 7804 ID (AMD driver)
+} SATA_CLASS;
+
+/// Configuration values for BLDCFG_FCH_GPP_LINK_CONFIG
+typedef enum {
+ PortA4 = 0, ///< 4:0:0:0
+ PortA2B2 = 2, ///< 2:2:0:0
+ PortA2B1C1 = 3, ///< 2:1:1:0
+ PortA1B1C1D1 = 4 ///< 1:1:1:1
+} GPP_LINKMODE;
+
+/// Configuration values for FchPowerFail
+typedef enum {
+ AlwaysOff = 0, ///< Always power off after power resumes
+ AlwaysOn = 1, ///< Always power on after power resumes
+ UsePrevious = 3, ///< Resume to same setting when power fails
+} POWER_FAIL;
+
+
+/// Configuration values for SATA Link Speed
+typedef enum {
+ Gen1 = 1, ///< SATA port GEN1 speed
+ Gen2 = 2, ///< SATA port GEN2 speed
+ Gen3 = 3, ///< SATA port GEN3 speed
+} SATA_SPEED;
+
+
+/// Configuration values for GPIO function
+typedef enum {
+ Function0 = 0, ///< GPIO Function 1
+ Function1 = 1, ///< GPIO Function 1
+ Function2 = 2, ///< GPIO Function 2
+ Function3 = 3, ///< GPIO Function 3
+} GPIO_FUN;
+
+/// Configuration values for memory phy voltage (VDDR)
+typedef enum {
+ VOLT0_95, ///< VDDR 0.95V
+ VOLT1_05, ///< VDDR 1.05V
+ MAX_VDDR ///< Maxmum value for this enum definition
+} MEMORY_PHY_VOLTAGE;
+
+/// Configuration values for GPIO_CFG
+typedef enum {
+ OwnedByEc = 1 << 0, ///< This bit can only be written by EC
+ OwnedByHost = 1 << 1, ///< This bit can only be written by host (BIOS)
+ Sticky = 1 << 2, ///< If set, [6:3] are sticky
+ PullUpB = 1 << 3, ///< 0: Pullup enable; 1: Pullup disabled
+ PullDown = 1 << 4, ///< 0: Pulldown disabled; 1: Pulldown enable
+ GpioOutEnB = 1 << 5, ///< 0: Output enable; 1: Output disable
+ GpioOut = 1 << 6, ///< Output state when GpioOutEnB is 0
+ GpioIn = 1 << 7, ///< This bit is read only - current pin state
+} CFG_BYTE;
+
+/// FCH GPIO CONTROL
+typedef struct {
+ IN UINT8 GpioPin; ///< Gpio Pin, valid range: 0-67, 128-150, 160-228
+ IN GPIO_FUN PinFunction; ///< Multi-function selection
+ IN CFG_BYTE CfgByte; ///< GPIO Register value
+} GPIO_CONTROL;
+
+///
+/// FCH SCI MAP CONTROL
+///
+typedef struct {
+ IN UINT8 InputPin; ///< Input Pin, valid range 0-63
+ IN UINT8 GpeMap; ///< Gpe Map, valid range 0-31
+} SCI_MAP_CONTROL;
+
+///
+/// FCH SATA PHY CONTROL
+///
+typedef struct {
+ IN BOOLEAN CommonPhy; ///< Common PHY or not
+ ///< @li <b>FALSE</b> - Only applied to specified port
+ ///< @li <b>TRUE</b> - Apply to all SATA ports
+ IN SATA_SPEED Gen; ///< SATA speed
+ IN UINT8 Port; ///< Port number, valid range: 0-7
+ IN UINT32 PhyData; ///< SATA PHY data, valid range: 0-0xFFFFFFFF
+} SATA_PHY_CONTROL;
+
+///
+/// FCH Component Data Structure in InitReset stage
+///
+typedef struct {
+ IN BOOLEAN UmiGen2; ///< Enable Gen2 data rate of UMI
+ ///< @li <b>FALSE</b> - Disable Gen2
+ ///< @li <b>TRUE</b> - Enable Gen2
+
+ IN BOOLEAN SataEnable; ///< SATA controller function
+ ///< @li <b>FALSE</b> - SATA controller is disabled
+ ///< @li <b>TRUE</b> - SATA controller is enabled
+
+ IN BOOLEAN IdeEnable; ///< SATA IDE controller mode enabled/disabled
+ ///< @li <b>FALSE</b> - IDE controller is disabled
+ ///< @li <b>TRUE</b> - IDE controller is enabled
+
+ IN BOOLEAN GppEnable; ///< Master switch of GPP function
+ ///< @li <b>FALSE</b> - GPP disabled
+ ///< @li <b>TRUE</b> - GPP enabled
+
+ IN BOOLEAN Xhci0Enable; ///< XHCI0 controller function
+ ///< @li <b>FALSE</b> - XHCI0 controller disabled
+ ///< @li <b>TRUE</b> - XHCI0 controller enabled
+
+ IN BOOLEAN Xhci1Enable; ///< XHCI1 controller function
+ ///< @li <b>FALSE</b> - XHCI1 controller disabled
+ ///< @li <b>TRUE</b> - XHCI1 controller enabled
+} FCH_RESET_INTERFACE;
+
+
+///
+/// FCH Component Data Structure from InitEnv stage
+///
+typedef struct {
+ IN SD_MODE SdConfig; ///< Secure Digital (SD) controller mode
+ IN HDA_CONFIG AzaliaController; ///< Azalia HD Audio Controller
+
+ IN IR_CONFIG IrConfig; ///< Infrared (IR) Configuration
+ IN BOOLEAN UmiGen2; ///< Enable Gen2 data rate of UMI
+ ///< @li <b>FALSE</b> - Disable Gen2
+ ///< @li <b>TRUE</b> - Enable Gen2
+
+ IN SATA_CLASS SataClass; ///< SATA controller mode
+ IN BOOLEAN SataEnable; ///< SATA controller function
+ ///< @li <b>FALSE</b> - SATA controller is disabled
+ ///< @li <b>TRUE</b> - SATA controller is enabled
+
+ IN BOOLEAN IdeEnable; ///< SATA IDE controller mode enabled/disabled
+ ///< @li <b>FALSE</b> - IDE controller is disabled
+ ///< @li <b>TRUE</b> - IDE controller is enabled
+
+ IN BOOLEAN SataIdeMode; ///< Native mode of SATA IDE controller
+ ///< @li <b>FALSE</b> - Legacy IDE mode
+ ///< @li <b>TRUE</b> - Native IDE mode
+
+ IN BOOLEAN Ohci1Enable; ///< OHCI controller #1 Function
+ ///< @li <b>FALSE</b> - OHCI1 is disabled
+ ///< @li <b>TRUE</b> - OHCI1 is enabled
+
+ IN BOOLEAN Ohci2Enable; ///< OHCI controller #2 Function
+ ///< @li <b>FALSE</b> - OHCI2 is disabled
+ ///< @li <b>TRUE</b> - OHCI2 is enabled
+
+ IN BOOLEAN Ohci3Enable; ///< OHCI controller #3 Function
+ ///< @li <b>FALSE</b> - OHCI3 is disabled
+ ///< @li <b>TRUE</b> - OHCI3 is enabled
+
+ IN BOOLEAN Ohci4Enable; ///< OHCI controller #4 Function
+ ///< @li <b>FALSE</b> - OHCI4 is disabled
+ ///< @li <b>TRUE</b> - OHCI4 is enabled
+
+ IN BOOLEAN GppEnable; ///< Master switch of GPP function
+ ///< @li <b>FALSE</b> - GPP disabled
+ ///< @li <b>TRUE</b> - GPP enabled
+
+ IN POWER_FAIL FchPowerFail; ///< FCH power failure option
+} FCH_INTERFACE;
+
+
+/*----------------------------------------------------------------------------
+ * CPU Feature related info
+ *----------------------------------------------------------------------------
+ */
+/// Build Configuration values for BLDCFG_PLATFORM_CONNECTED_STANDBY_MODE
+typedef enum {
+ ConnectedStandbyAuto = 0, ///< Auto
+ ConnectedStandbyDisabled = 1, ///< Disabled
+ MaxConnectedStandbyMode = 2 ///< Not a valid value, used for verifying input
+} PLATFORM_CONNECTED_STANDBY_MODES;
+
+/// Build Configuration values for BLDCFG_PLATFORM_CSTATE_MODE
+typedef enum {
+ CStateModeDisabled = 0, ///< Disabled
+ CStateModeC6 = 1, ///< C6 State
+ MaxCStateMode = 2 ///< Not a valid value, used for verifying input
+} PLATFORM_CSTATE_MODES;
+
+/// Build Configuration values for BLDCFG_PLATFORM_CPB_MODE
+typedef enum {
+ CpbModeAuto = 0, ///< Auto
+ CpbModeDisabled = 1, ///< Disabled
+ MaxCpbMode = 2 ///< Not a valid value, used for verifying input
+} PLATFORM_CPB_MODES;
+
+/// Build Configuration values for BLDCFG_LOW_POWER_PSTATE_FOR_PROCHOT_MODE
+typedef enum {
+ LOW_POWER_PSTATE_FOR_PROCHOT_AUTO = 0, ///< Auto
+ LOW_POWER_PSTATE_FOR_PROCHOT_DISABLE = 1, ///< Disabled
+ MAX_LOW_POWER_PSTATE_FOR_PROCHOT_MODE = 2 ///< Not a valid value, used for verifying input
+} PLATFORM_LOW_POWER_PSTATE_MODES;
+
+/// Build Configuration values for BLDCFG_ACPI_PSTATES_PSD_POLICY
+#define PsdPolicyProcessorDefault 0 ///< PSD is dependent or independent per processor default
+#define PsdPolicyDependent 1 ///< PSD is forced dependent
+#define PsdPolicyIndependent 2 ///< PSD is forced independent
+#define PsdPolicyMax 3 ///< Not a valid value, used for verifying input
+
+/*----------------------------------------------------------------------------
+ * GNB PCIe configuration info
+ *----------------------------------------------------------------------------
+ */
+
+// Event definitions
+
+#define GNB_EVENT_INVALID_CONFIGURATION 0x20010000ul // User configuration invalid
+#define GNB_EVENT_INVALID_PCIE_TOPOLOGY_CONFIGURATION 0x20010001ul // Requested lane allocation for PCIe port can not be supported
+#define GNB_EVENT_INVALID_PCIE_PORT_CONFIGURATION 0x20010002ul // Requested incorrect PCIe port device address
+#define GNB_EVENT_INVALID_DDI_LINK_CONFIGURATION 0x20010003ul // Incorrect parameter in DDI link configuration
+#define GNB_EVENT_INVALID_LINK_WIDTH_CONFIGURATION 0x20010004ul // Invalid with for PCIe port or DDI link
+#define GNB_EVENT_INVALID_LANES_CONFIGURATION 0x20010005ul // Lane double subscribe lanes
+#define GNB_EVENT_INVALID_DDI_TOPOLOGY_CONFIGURATION 0x20010006ul // Requested lane allocation for DDI link(s) can not be supported
+#define GNB_EVENT_LINK_TRAINING_FAIL 0x20020000ul // PCIe Link training fail
+#define GNB_EVENT_BROKEN_LANE_RECOVERY 0x20030000ul // Broken lane workaround applied to recover link training
+#define GNB_EVENT_GEN2_SUPPORT_RECOVERY 0x20040000ul // Scale back to GEN1 to recover link training
+
+
+#define DESCRIPTOR_TERMINATE_LIST 0x80000000ull
+#define DESCRIPTOR_IGNORE 0x40000000ull
+
+/// PCIe link initialization
+typedef enum {
+ EndpointDetect = 0, ///< Detect endpoint presence
+ EndpointNotPresent ///< Endpoint not present (or connected). Used in case there is alternative way to determine
+ ///< if device present on board or in slot. For example GPIO can be used to determine device presence.
+} PCIE_ENDPOINT_STATUS;
+
+
+/// PCIe port misc extended controls
+typedef struct {
+ IN UINT8 LinkComplianceMode :1; ///< Force port into compliance mode (device will not be trained, port output compliance pattern)
+ IN UINT8 LinkSafeMode :2; /**< Safe mode PCIe capability. (Parameter may limit PCIe speed requested through PCIe_PORT_DATA::LinkSpeedCapability)
+ * @li @b 0 - port can advertize muximum supported capability
+ * @li @b 1 - port limit advertized capability and speed to PCIe Gen1
+ */
+ IN UINT8 SbLink :1; /**< PCIe link type
+ * @li @b 0 - General purpose port
+ * @li @b 1 - Port connected to SB
+ */
+ IN UINT8 ClkPmSupport :1; /**< Clock Power Management Support
+ * @li @b 0 - Clock Power Management not configured
+ * @li @b 1 - Clock Power Management configured according to PCIe device capability
+ */
+} PCIe_PORT_MISC_CONTROL;
+
+/// The IO APIC Interrupt Mapping Info
+typedef struct {
+ IN UINT8 GroupMap; /**< Group mapping for slot or endpoint device (connected to PCIE port) interrupts .
+ * @li <b>0</b> - IGNORE THIS STRUCTURE AND USE RECOMMENDED SETTINGS
+ * @li <b>1</b> - mapped to Grp 0 (Interrupts 0..3 of IO APIC redirection table)
+ * @li <b>2</b> - mapped to Grp 1 (Interrupts 4..7 of IO APIC redirection table)
+ * @li ...
+ * @li <b>8</b> - mapped to Grp 7 (Interrupts 28..31 of IO APIC redirection table)
+ */
+ IN UINT8 Swizzle; /**< Swizzle interrupt in the Group.
+ * @li <b>0</b> - ABCD
+ * @li <b>1</b> - BCDA
+ * @li <b>2</b> - CDAB
+ * @li <b>3</b> - DABC
+ */
+ IN UINT8 BridgeInt; /**< IOAPIC redirection table entry for PCIE bridge interrupt
+ * @li <b>0</b> - Entry 0 of IO APIC redirection table
+ * @li <b>1</b> - Entry 1 of IO APIC redirection table
+ * @li ...
+ * @li <b>31</b> - Entry 31 of IO APIC redirection table
+ */
+} APIC_DEVICE_INFO;
+
+/// Initial Offset Calibration Control
+typedef enum {
+ ADAPT_IOC_DISABLED = 0, ///< Initial Offset Calibration Disabled
+ ADAPT_IOC_ENABLED ///< Initial Offset Calibration Enabled
+} ADAPT_IOC_CONTROL;
+
+/// DFE Control values
+typedef enum {
+ ADAPT_DFE_CONTROL_DISABLED = 0, ///< DFE Disabled
+ ADAPD_DFE_CONTROL_1TAP_DFE = 4, ///< 1-tap DFE
+ ADAPD_DFE_CONTROL_1TAP_DFE_FBF, ///< 1-tap DFE with Future Bit Filtering
+ ADAPD_DFE_CONTROL_2TAP_DFE, ///< 2-tap DFE
+ ADAPD_DFE_CONTROL_2TAP_DFE_FBF ///< 2-tap DFE with Future Bit Filtering
+} ADAPT_DFE_CONTROL;
+
+/// LEQ Control values
+typedef enum {
+ ADAPT_LEQ_CONTROL_DISABLED = 0, ///< LEQ Disabled
+ ADAPT_LEQ_CONTROL_DC_GAIN = 2, ///< DC Gain Adaptation
+ ADAPT_LEQ_CONTROL_DC_GAIN_POLE ///< DC Gain and Pole Adaptation
+} ADAPT_LEQ_CONTROL;
+
+/// Dynamic Offset Calibration Control
+typedef enum {
+ ADAPT_DOC_DISABLED = 0, ///< Dynamic Offset Calibration Disabled
+ ADAPT_DOC_ENABLED ///< Dynamic Offset Calibration Enabled
+} ADAPT_DOC_CONTROL;
+
+/// FOM Calculation Control
+typedef enum {
+ ADAPT_FOMC_DISABLED = 0, ///< FOM Calculation Disabled
+ ADAPT_FOMC_ENABLED ///< FOM Calculation Enabled
+} ADAPT_FOMC_CONTROL;
+
+/// PI Offset Calibration Control
+typedef enum {
+ ADAPT_PIOC_DISABLED = 0, ///< PI Offset Calibration Disabled
+ ADAPT_PIOC_ENABLED ///< PI Offset Calibration Enabled
+} ADAPT_PIOC_CONTROL;
+
+/// GEN3 RxAdaptMode Configuration Structure
+typedef struct {
+ IN BOOLEAN InitOffsetCancellation; ///< Initial Offset Cancellation Enable
+ IN UINT8 DFEControl; ///< DFE Control
+ IN UINT8 LEQControl; ///< LEQ Control
+ IN BOOLEAN DynamicOffsetCalibration; ///< Dynamic Offset Calibration Enable
+ IN BOOLEAN FOMCalculation; ///< FOM Calculation Enable
+ IN BOOLEAN PIOffsetCalibration; ///< PI Offset Calibratino Enable
+} RX_ADAPT_MODE;
+
+/// PCIe port configuration data
+typedef struct {
+ IN UINT8 PortPresent; ///< Enable PCIe port for initialization.
+ IN UINT8 ChannelType; /**< Channel type.
+ * @li @b 0 - "lowLoss",
+ * @li @b 1 - "highLoss",
+ * @li @b 2 - "mob0db",
+ * @li @b 3 - "mob3db",
+ * @li @b 4 - "extnd6db"
+ * @li @b 5 - "extnd8db"
+ */
+ IN UINT8 DeviceNumber; /**< PCI Device number for port.
+ * @li @b 0 - Native port device number
+ * @li @b N - Port device number (See available configurations in BKDG
+ */
+ IN UINT8 FunctionNumber; ///< Reserved for future use
+ IN UINT8 LinkSpeedCapability; /**< PCIe link speed/
+ * @li @b 0 - Maximum supported by silicon
+ * @li @b 1 - Gen1
+ * @li @b 2 - Gen2
+ * @li @b 3 - Gen3
+ */
+ IN UINT8 LinkAspm; /**< ASPM control. (see AgesaPcieLinkAspm for additional option to control ASPM)
+ * @li @b 0 - Disabled
+ * @li @b 1 - L0s only
+ * @li @b 2 - L1 only
+ * @li @b 3 - L0s and L1
+ */
+ IN UINT8 LinkHotplug; /**< Hotplug control.
+ * @li @b 0 - Disabled
+ * @li @b 1 - Basic
+ * @li @b 2 - Server
+ * @li @b 3 - Enhanced
+ */
+ IN UINT8 ResetId; /**< Arbitrary number greater than 0 assigned by platform firmware for GPIO
+ * identification which control reset for given port.
+ * Each port with unique GPIO should have unique ResetId assigned.
+ * All ports use same GPIO to control reset should have same ResetId assigned.
+ * see AgesaPcieSlotResetContol.
+ */
+ IN PCIe_PORT_MISC_CONTROL MiscControls; ///< Misc extended controls
+ IN APIC_DEVICE_INFO ApicDeviceInfo; ///< IOAPIC device programming info
+ IN PCIE_ENDPOINT_STATUS EndpointStatus; ///< PCIe endpoint (device connected to PCIe port) status
+ IN RX_ADAPT_MODE RxAdaptMode; ///< Gen3 RxAdaptMode configuration
+} PCIe_PORT_DATA;
+
+/// DDI channel lane mapping
+typedef struct { ///< Structure that discribe lane mapping
+ IN UINT8 Lane0 :2; /**< Lane 0 mapping
+ * @li @b 0 - Map to lane 0
+ * @li @b 1 - Map to lane 1
+ * @li @b 2 - Map to lane 2
+ * @li @b 3 - Map to lane 3
+ */
+ IN UINT8 Lane1 :2; ///< Lane 1 mapping (see "Lane 0 mapping")
+ IN UINT8 Lane2 :2; ///< Lane 2 mapping (see "Lane 0 mapping")
+ IN UINT8 Lane3 :2; ///< Lane 3 mapping (see "Lane 0 mapping")
+} CHANNEL_MAPPING; ///< Lane mapping
+
+/// Common Channel Mapping
+typedef union {
+ IN UINT8 ChannelMappingValue; ///< Raw lane mapping
+ IN CHANNEL_MAPPING ChannelMapping; ///< Channel mapping
+} CONN_CHANNEL_MAPPING;
+
+/// DDI Configuration data
+typedef struct {
+ IN UINT8 ConnectorType; /**< Display Connector Type
+ * @li @b 0 - DP
+ * @li @b 1 - eDP
+ * @li @b 2 - Single Link DVI-D
+ * @li @b 3 - Dual Link DVI-D (see @ref DualLinkDviDescription "Example Dual Link DVI connector description")
+ * @li @b 4 - HDMI
+ * @li @b 5 - DP-to-VGA
+ * @li @b 6 - DP-to-LVDS
+ * @li @b 7 - Hudson-2 NutMeg DP-to-VGA
+ * @li @b 8 - Single Link DVI-I
+ * @li @b 9 - Native CRT (Family 0x14)
+ * @li @b 10 - Native LVDS (Family 0x14)
+ * @li @b 11 - Auto detect LCD panel connector type. VBIOS is able to auto detect the LVDS connector type: native LVDS, eDP or DP-to-LVDS
+ * The auto detection method only support panel with EDID.
+ */
+ IN UINT8 AuxIndex; /**< Indicates which AUX or DDC Line is used
+ * @li @b 0 - AUX1
+ * @li @b 1 - AUX2
+ * @li @b 2 - AUX3
+ * @li @b 3 - AUX4
+ * @li @b 4 - AUX5
+ * @li @b 5 - AUX6
+ */
+ IN UINT8 HdpIndex; /**< Indicates which HDP pin is used
+ * @li @b 0 - HDP1
+ * @li @b 1 - HDP2
+ * @li @b 2 - HDP3
+ * @li @b 3 - HDP4
+ * @li @b 4 - HDP5
+ * @li @b 5 - HDP6
+ */
+ IN CONN_CHANNEL_MAPPING Mapping[2]; /**< Set specific mapping of lanes to connector pins
+ * @li Mapping[0] define mapping for group of 4 lanes starting at PCIe_ENGINE_DATA.StartLane
+ * @li Mapping[1] define mapping for group of 4 lanes ending at PCIe_ENGINE_DATA.EndLane (only applicable for Dual DDI link)
+ * if Mapping[x] set to 0 than default mapping assumed
+ */
+ IN UINT8 LanePnInversionMask; /**< Specifies whether to invert the state of P and N for each lane. Each bit represents a PCIe lane on the DDI port.
+ * @li 0 - Do not invert (default)
+ * @li 1 - Invert P and N on this lane
+ */
+ IN UINT8 Flags; /**< Capabilities flags
+ * @li Flags bit[0] DDI_DATA_FLAGS_DP1_1_ONLY Selects downgrade PHY link to DP1.1
+ * @li Flags bit[7:1] Reserved
+ */
+} PCIe_DDI_DATA;
+
+/// Engine Configuration
+typedef struct {
+ IN UINT8 EngineType; /**< Engine type
+ * @li @b 0 - Ignore engine configuration
+ * @li @b 1 - PCIe port
+ * @li @b 2 - DDI
+ */
+ IN UINT16 StartLane; /**< Start Lane ID (in reversed configuration StartLane > EndLane)
+ * Refer to lane descriptions and supported configurations in BKDG
+ */
+ IN UINT16 EndLane; /**< End lane ID (in reversed configuration StartLane > EndLane)
+ * Refer to lane descriptions and supported configurations in BKDG
+ */
+
+} PCIe_ENGINE_DATA;
+
+/// PCIe port descriptor
+typedef struct {
+ IN UINT32 Flags; /**< Descriptor flags
+ * @li @b Bit31 - last descriptor in complex
+ */
+ IN PCIe_ENGINE_DATA EngineData; ///< Engine data
+ IN PCIe_PORT_DATA Port; ///< PCIe port specific configuration info
+} PCIe_PORT_DESCRIPTOR;
+
+/// DDI descriptor
+typedef struct {
+ IN UINT32 Flags; /**< Descriptor flags
+ * @li @b Bit31 - last descriptor in complex
+ */
+ IN PCIe_ENGINE_DATA EngineData; ///< Engine data
+ IN PCIe_DDI_DATA Ddi; ///< DDI port specific configuration info
+} PCIe_DDI_DESCRIPTOR;
+
+/// PCIe Complex descriptor
+typedef struct {
+ IN UINT32 Flags; /**< Descriptor flags
+ * @li @b Bit31 - last descriptor in topology
+ */
+ IN UINT32 SocketId; ///< Socket Id
+ IN CONST PCIe_PORT_DESCRIPTOR *PciePortList; ///< Pointer to array of PCIe port descriptors or NULL (Last element of array must be terminated with DESCRIPTOR_TERMINATE_LIST).
+ IN CONST PCIe_DDI_DESCRIPTOR *DdiLinkList; ///< Pointer to array DDI link descriptors (Last element of array must be terminated with DESCRIPTOR_TERMINATE_LIST).
+ IN VOID *Reserved; ///< Reserved for future use
+} PCIe_COMPLEX_DESCRIPTOR;
+
+/// Action to control PCIe slot reset
+typedef enum {
+ AssertSlotReset, ///< Assert slot reset
+ DeassertSlotReset ///< Deassert slot reset
+} PCIE_RESET_CONTROL;
+
+///Slot Reset Info
+typedef struct {
+ IN AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header
+ IN UINT8 ResetId; ///< Slot reset ID as specified in PCIe_PORT_DESCRIPTOR
+ IN UINT8 ResetControl; ///< Reset control as in PCIE_RESET_CONTROL
+} PCIe_SLOT_RESET_INFO;
+
+#define GFX_VBIOS_IMAGE_FLAG_SPECIAL_POST 0x1
+
+///VBIOS image info
+typedef struct {
+ IN AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header
+ OUT VOID *ImagePtr; ///< Pointer to VBIOS image
+ IN PCI_ADDR GfxPciAddress; ///< PCI address of integrated graphics controller
+ IN UINT32 Flags; ///< BIT[0] - special repost requred
+} GFX_VBIOS_IMAGE_INFO;
+
+/// Engine descriptor type
+typedef enum {
+ PcieUnusedEngine = 0, ///< Unused descriptor
+ PciePortEngine = 1, ///< PCIe port
+ PcieDdiEngine = 2, ///< DDI
+ MaxPcieEngine ///< Max engine type for boundary check.
+} PCIE_ENGINE_TYPE;
+
+/// PCIe link capability/speed
+typedef enum {
+ PcieGenMaxSupported, ///< Maximum supported
+ PcieGen1 = 1, ///< Gen1
+ PcieGen2, ///< Gen2
+ PcieGen3, ///< Gen3
+ MaxPcieGen ///< Max Gen for boundary check
+} PCIE_LINK_SPEED_CAP;
+
+/// PCIe PSPP Power policy
+typedef enum {
+ PsppDisabled, ///< PSPP disabled
+ PsppPerformance = 1, ///< Performance
+ PsppBalanceHigh, ///< Balance-High
+ PsppBalanceLow, ///< Balance-Low
+ PsppPowerSaving, ///< Power Saving
+ MaxPspp ///< Max Pspp for boundary check
+} PCIE_PSPP_POLICY;
+
+/// DDI display connector type
+typedef enum {
+ ConnectorTypeDP, ///< DP
+ ConnectorTypeEDP, ///< eDP
+ ConnectorTypeSingleLinkDVI, ///< Single Link DVI-D
+ ConnectorTypeDualLinkDVI, ///< Dual Link DVI-D
+ ConnectorTypeHDMI, ///< HDMI
+ ConnectorTypeDpToVga, ///< DP-to-VGA
+ ConnectorTypeDpToLvds, ///< DP-to-LVDS
+ ConnectorTypeNutmegDpToVga, ///< Hudson-2 NutMeg DP-to-VGA
+ ConnectorTypeSingleLinkDviI, ///< Single Link DVI-I
+ ConnectorTypeCrt, ///< CRT (VGA)
+ ConnectorTypeLvds, ///< LVDS
+ ConnectorTypeEDPToLvds, ///< 3rd party common eDP-to-LVDS translator chip without AMD SW init
+ ConnectorTypeEDPToLvdsSwInit, ///< 3rd party eDP-to-LVDS translator which requires AMD SW init
+ ConnectorTypeAutoDetect, ///< VBIOS auto detect connector type (native LVDS, eDP or DP-to-LVDS)
+ MaxConnectorType ///< Not valid value, used to verify input
+} PCIE_CONNECTOR_TYPE;
+
+/// PCIe link channel type
+typedef enum {
+ ChannelTypeLowLoss, ///< Low Loss
+ ChannelTypeHighLoss, ///< High Loss
+ ChannelTypeMob0db, ///< Mobile 0dB
+ ChannelTypeMob3db, ///< Mobile 3dB
+ ChannelTypeExt6db, ///< Extended 6dB
+ ChannelTypeExt8db, ///< Extended 8dB
+ MaxChannelType ///< Not valid value, used to verify input
+} PCIE_CHANNEL_TYPE;
+
+/// PCIe link ASPM
+typedef enum {
+ AspmDisabled, ///< Disabled
+ AspmL0s, ///< PCIe L0s link state
+ AspmL1, ///< PCIe L1 link state
+ AspmL0sL1, ///< PCIe L0s & L1 link state
+ MaxAspm ///< Not valid value, used to verify input
+} PCIE_ASPM_TYPE;
+
+/// PCIe link hotplug support
+typedef enum {
+ HotplugDisabled, ///< Hotplug disable
+ HotplugBasic, ///< Basic Hotplug
+ HotplugServer, ///< Server Hotplug
+ HotplugEnhanced, ///< Enhanced
+ HotplugInboard, ///< Inboard
+ MaxHotplug ///< Not valid value, used to verify input
+} PCIE_HOTPLUG_TYPE;
+
+/// PCIe link initialization
+typedef enum {
+ PortDisabled, ///< Disable
+ PortEnabled ///< Enable
+} PCIE_PORT_ENABLE;
+
+/// PCIe ACS capability - Access Control Services
+typedef enum {
+ PcieAcsDisabled, ///< Disabled
+ PcieAcsEnabled, ///< Enabled
+} PCIE_ACS_CAP;
+
+/// PCIe ClkPmSupport initialization
+typedef enum {
+ ClkPmSupportDisabled, ///< Disable
+ ClkPmSupportEnabled ///< Enable
+} CLKPM_SUPPORT_ENABLE;
+
+/// DDI Aux channel
+typedef enum {
+ Aux1, ///< Aux1
+ Aux2, ///< Aux2
+ Aux3, ///< Aux3
+ Aux4, ///< Aux4
+ Aux5, ///< Aux5
+ Aux6, ///< Aux6
+ MaxAux ///< Not valid value, used to verify input
+} PCIE_AUX_TYPE;
+
+/// DDI Hdp Index
+typedef enum {
+ Hdp1, ///< Hdp1
+ Hdp2, ///< Hdp2
+ Hdp3, ///< Hdp3
+ Hdp4, ///< Hdp4
+ Hdp5, ///< Hdp5
+ Hdp6, ///< Hdp6
+ MaxHdp ///< Not valid value, used to verify input
+} PCIE_HDP_TYPE;
+
+/// PCIe_DDI_DATA.Flags definitions
+#define DDI_DATA_FLAGS_DP1_1_ONLY 0x01 ///< BIT[0] Selects downgrade PHY link to DP1.1
+#define EXT_DISPLAY_PATH_CAPS_DP_FIXED_VS_EN 0x02 ///< BIT[1] VBIOS will always output fixed voltage swing during DP link training
+/// DP receiver definitions with fixed voltage swing
+typedef enum {
+ DP_VS_0_4V_0DB, ///< 0x00
+ DP_VS_0_6V_0DB, ///< 0x01
+ DP_VS_0_8V_0DB, ///< 0x02
+ DP_VS_1_2V_0DB, ///< 0x03
+ DP_VS_0_4V_3_5DB = 0x8, ///< 0x08
+ DP_VS_0_6V_3_5DB, ///< 0x09
+ DP_VS_0_8V_3_5DB, ///< 0x0a
+ DP_VS_0_4V_6DB = 0x10, ///< 0x10
+ DP_VS_0_6V_6DB, ///< 0x11
+ DP_VS_0_4V_9_5DB = 0x18 ///< 0x18
+} DP_FIXED_VOLT_SWING_TYPE;
+
+// Macro for statically initializing various structures
+#define PCIE_ENGINE_DATA_INITIALIZER(mType, mStartLane, mEndLane) {mType, mStartLane, mEndLane}
+#define PCIE_PORT_DATA_INITIALIZER(mPortPresent, mChannelType, mDevAddress, mHotplug, mMaxLinkSpeed, mMaxLinkCap, mAspm, mResetId) \
+{mPortPresent, mChannelType, mDevAddress, 0, mMaxLinkSpeed, mAspm, mHotplug, mResetId, {0, mMaxLinkCap, 0, 0}, {0, 0, 0}, EndpointDetect, \
+{ADAPT_IOC_ENABLED, ADAPT_DFE_CONTROL_DISABLED, ADAPT_LEQ_CONTROL_DC_GAIN_POLE, ADAPT_DOC_DISABLED, ADAPT_FOMC_ENABLED, ADAPT_PIOC_DISABLED}}
+#define PCIE_PORT_DATA_INITIALIZER_V2(mPortPresent, mChannelType, mDevAddress, mDevFunction, mHotplug, mMaxLinkSpeed, mMaxLinkCap, mAspm, mResetId, mClkPmSupport) \
+{mPortPresent, mChannelType, mDevAddress, mDevFunction, mMaxLinkSpeed, mAspm, mHotplug, mResetId, {0, mMaxLinkCap, 0, mClkPmSupport}, {0, 0, 0}, EndpointDetect, \
+{ADAPT_IOC_ENABLED, ADAPT_DFE_CONTROL_DISABLED, ADAPT_LEQ_CONTROL_DC_GAIN_POLE, ADAPT_DOC_DISABLED, ADAPT_FOMC_ENABLED, ADAPT_PIOC_DISABLED}}
+#define PCIE_PORT_DATA_INITIALIZER_GEN3(mPortPresent, mChannelType, mDevAddress, mDevFunction, mHotplug, mMaxLinkSpeed, mMaxLinkCap, mAspm, mResetId, mClkPmSupport, \
+mInitOffsetCancellation, mDFEControl, mLEQControl, mDynamicOffsetCalibration, mFOMCalculation, mPIOffsetCalibration) \
+{mPortPresent, mChannelType, mDevAddress, mDevFunction, mMaxLinkSpeed, mAspm, mHotplug, mResetId, {0, mMaxLinkCap, 0, mClkPmSupport}, {0, 0, 0}, EndpointDetect, \
+{mInitOffsetCancellation, mDFEControl, mLEQControl, mDynamicOffsetCalibration, mFOMCalculation, mPIOffsetCalibration}}
+#define PCIE_DDI_DATA_INITIALIZER(mConnectorType, mAuxIndex, mHpdIndex ) \
+{mConnectorType, mAuxIndex, mHpdIndex, {{0},{0}}, 0, 0}
+#define PCIE_DDI_DATA_INITIALIZER_V1(mConnectorType, mAuxIndex, mHpdIndex, mMapping0, mMapping1, mPNInversion) \
+{mConnectorType, mAuxIndex, mHpdIndex, {mMapping0, mMapping1}, mPNInversion, 0}
+#define PCIE_DDI_DATA_INITIALIZER_V2(mConnectorType, mAuxIndex, mHpdIndex, mMapping0, mMapping1, mPNInversion, mFlags) \
+{mConnectorType, mAuxIndex, mHpdIndex, {mMapping0, mMapping1}, mPNInversion, mFlags}
+
+///IOMMU requestor ID
+typedef struct {
+ IN UINT16 Bus :8; ///< Bus
+ IN UINT16 Device :5; ///< Device
+ IN UINT16 Function :3; ///< Function
+} IOMMU_REQUESTOR_ID;
+
+/// IVMD exclusion range descriptor
+typedef struct {
+ IN UINT32 Flags; /**< Descriptor flags
+ * @li @b Flags[31] - Terminate descriptor array.
+ * @li @b Flags[30] - Ignore descriptor.
+ */
+ IN IOMMU_REQUESTOR_ID RequestorIdStart; ///< Requestor ID start
+ IN IOMMU_REQUESTOR_ID RequestorIdEnd; ///< Requestor ID end (use same as start for single ID)
+ IN UINT64 RangeBaseAddress; ///< Phisical base address of exclusion range
+ IN UINT64 RangeLength; ///< Length of exclusion range in bytes
+} IOMMU_EXCLUSION_RANGE_DESCRIPTOR;
+
+/*----------------------------------------------------------------------------
+ * GNB configuration info
+ *----------------------------------------------------------------------------
+ */
+
+/// LVDS Misc Control Field
+typedef struct {
+ IN UINT8 FpdiMode:1; ///< This item configures LVDS 888bit panel mode
+ ///< @li FALSE = LVDS 888 panel in LDI mode
+ ///< @li TRUE = LVDS 888 panel in FPDI mode
+ ///< @BldCfgItem{BLDCFG_LVDS_MISC_888_FPDI_MODE}
+ IN UINT8 DlChSwap:1; ///< This item configures LVDS panel lower and upper link mapping
+ ///< @li FALSE = Lower link and upper link not swap
+ ///< @li TRUE = Lower link and upper link are swapped
+ ///< @BldCfgItem{BLDCFG_LVDS_MISC_DL_CH_SWAP}
+ IN UINT8 VsyncActiveLow:1; ///< This item configures polarity of frame pulse encoded in lvds data stream
+ ///< @li FALSE = Active high Frame Pulse/Vsync
+ ///< @li TRUE = Active low Frame Pulse/Vsync
+ ///< @BldCfgItem{BLDCFG_LVDS_MISC_VSYNC_ACTIVE_LOW}
+ IN UINT8 HsyncActiveLow:1; ///< This item configures polarity of line pulse encoded in lvds data
+ ///< @li FALSE = Active high Line Pulse
+ ///< @li TRUE = Active low Line Pulse / Hsync
+ ///< @BldCfgItem{BLDCFG_LVDS_MISC_HSYNC_ACTIVE_LOW}
+ IN UINT8 BLONActiveLow:1; ///< This item configures polarity of signal sent to digital BLON output pin
+ ///< @li FALSE = Not inverted(active high)
+ ///< @li TRUE = Inverted (active low)
+ ///< @BldCfgItem{BLDCFG_LVDS_MISC_BLON_ACTIVE_LOW}
+ IN UINT8 LvdsVoltOverwriteEn:1; ///< This item configures polarity of DP-to-LVDS output voltage overwrite
+ ///< @li FALSE = DP-to-LVDS output voltage overwrite disable, use VBIOS default setting.
+ ///< @li TRUE = Use ucLVDSVolAdjust value to program register LVDS_CTRL_4
+ ///< @BldCfgItem{BLDCFG_LVDS_MISC_VOLT_OVERWRITE_ENABLE}
+ IN UINT8 Reserved:2; ///< Reserved
+} LVDS_MISC_CONTROL_FIELD;
+
+/// LVDS Misc Control
+typedef union _LVDS_MISC_CONTROL {
+ IN LVDS_MISC_CONTROL_FIELD Field; ///< LVDS_MISC_CONTROL_FIELD
+ IN UINT8 Value; ///< LVDS Misc Control Value
+} LVDS_MISC_CONTROL;
+
+/// Display Misc Control Field
+typedef struct {
+ IN UINT8 Reserved1:3; ///< Reserved
+ IN UINT8 VbiosFastBootEn:1; ///< This item configures VBIOS skip display device detection in every set mode if LCD panel is connect and LID is open.
+ ///< @li FALSE = VBIOS fast boot is disable.
+ ///< @li TRUE = VBIOS fast boot is enable.
+ ///< @BldCfgItem{BLDCFG_DISPLAY_MISC_VBIOS_FAST_BOOT_ENABLE}
+ IN UINT8 Reserved2:4; ///< Reserved
+} DISPLAY_MISC_CONTROL_FIELD;
+
+/// LVDS Misc Control
+typedef union _DISPLAY_MISC_CONTROL {
+ IN DISPLAY_MISC_CONTROL_FIELD Field; ///< DISPLAY_MISC_CONTROL_FIELD
+ IN UINT8 Value; ///< Display Misc Control Value
+} DISPLAY_MISC_CONTROL;
+
+/// POST Configuration settings for GNB.
+typedef struct {
+ IN UINT8 IgpuEnableDisablePolicy; ///< This item defines the iGPU Enable/Disable policy
+ ///< @li 0 = Auto - use existing default -
+ ///< @li 1 = Disable iGPU if any PCIe/PCI graphics card present
+ ///< @BldCfgItem{BLDCFG_IGPU_ENABLE_DISABLE_POLICY}
+} GNB_POST_CONFIGURATION;
+
+/// iGPU Enable/Disable Policy values
+#define IGPU_DISABLE_AUTO 0 ///< Auto setting - disable iGPU if ANY PCI graphics or non-AMD PCIe graphics
+#define IGPU_DISABLE_ANY_PCIE 1 ///< Disable iGPU if any PCI or PCIE graphics card is present
+
+/// ENV Configuration settings for GNB.
+typedef struct {
+ IN UINT8 Gnb3dStereoPinIndex; ///< 3D Stereo Pin ID.
+ ///< @li 0 = Stereo 3D is disabled (default).
+ ///< @li 1 = Use processor pin HPD1.
+ ///< @li 2 = Use processor pin HPD2
+ ///< @li 3 = Use processor pin HPD3
+ ///< @li 4 = Use processor pin HPD4
+ ///< @li 5 = Use processor pin HPD5
+ ///< @li 6 = Use processor pin HPD6
+ ///< @BldCfgItem{BLDCFG_STEREO_3D_PINOUT}
+ IN BOOLEAN IommuSupport; ///< IOMMU support.
+ ///< @li FALSE = Disabled. Disable and hide IOMMU device.
+ ///< @li TRUE = Initialize IOMMU subsystem. Generate ACPI IVRS table.
+ ///< BldCfgItem{BLDCFG_IOMMU_SUPPORT}
+ IN UINT16 LvdsSpreadSpectrum; ///< Spread spectrum value in 0.01 %
+ ///< BldCfgItem{BLDCFG_GFX_LVDS_SPREAD_SPECTRUM}
+ IN UINT16 LvdsSpreadSpectrumRate; ///< Spread spectrum frequency used by SS hardware logic in unit of 10Hz, 0 - default frequency 40kHz
+ ///< BldCfgItem{BLDCFG_GFX_LVDS_SPREAD_SPECTRUM_RATE}
+ IN UINT8 LvdsPowerOnSeqDigonToDe; ///< This item configures panel initialization timing.
+ ///< @BldCfgItem{BLDCFG_LVDS_POWER_ON_SEQ_DIGON_TO_DE}
+ IN UINT8 LvdsPowerOnSeqDeToVaryBl; ///< This item configures panel initialization timing.
+ ///< @BldCfgItem{BLDCFG_LVDS_POWER_ON_SEQ_DE_TO_VARY_BL}
+ IN UINT8 LvdsPowerOnSeqDeToDigon; ///< This item configures panel initialization timing.
+ ///< @BldCfgItem{BLDCFG_LVDS_POWER_ON_SEQ_DE_TO_DIGON}
+ IN UINT8 LvdsPowerOnSeqVaryBlToDe; ///< This item configures panel initialization timing.
+ ///< @BldCfgItem{BLDCFG_LVDS_POWERS_ON_SEQ_VARY_BL_TO_DE}
+ IN UINT8 LvdsPowerOnSeqOnToOffDelay; ///< This item configures panel initialization timing.
+ ///< @BldCfgItem{BLDCFG_LVDS_POWER_ON_SEQ_ON_TO_OFF_DELAY}
+ IN UINT8 LvdsPowerOnSeqVaryBlToBlon; ///< This item configures panel initialization timing.
+ ///< @BldCfgItem{BLDCFG_LVDS_POWER_ON_SEQ_VARY_BL_TO_BLON}
+ IN UINT8 LvdsPowerOnSeqBlonToVaryBl; ///< This item configures panel initialization timing.
+ ///< @BldCfgItem{BLDCFG_LVDS_POWER_ON_SEQ_BLON_TO_VARY_BL}
+ IN UINT16 LvdsMaxPixelClockFreq; ///< This item configures the maximum pixel clock frequency supported.
+ ///< @BldCfgItem{BLDCFG_LVDS_MAX_PIXEL_CLOCK_FREQ}
+ IN UINT32 LcdBitDepthControlValue; ///< This item configures the LCD bit depth control settings.
+ ///< @BldCfgItem{BLDCFG_LCD_BIT_DEPTH_CONTROL_VALUE}
+ IN UINT8 Lvds24bbpPanelMode; ///< This item configures the LVDS 24 BBP mode.
+ ///< @BldCfgItem{BLDCFG_LVDS_24BBP_PANEL_MODE}
+ IN LVDS_MISC_CONTROL LvdsMiscControl;///< This item configures LVDS swap/Hsync/Vsync/BLON
+ IN UINT16 PcieRefClkSpreadSpectrum; ///< Spread spectrum value in 0.01 %
+ ///< @BldCfgItem{BLDCFG_PCIE_REFCLK_SPREAD_SPECTRUM}
+ IN BOOLEAN GnbRemoteDisplaySupport; ///< This item enables Wireless Display Support
+ ///< @li TRUE = Enable Wireless Display Support
+ ///< @li FALSE = Disable Wireless Display Support
+ ///< @BldCfgItem{BLDCFG_REMOTE_DISPLAY_SUPPORT}
+ IN UINT8 LvdsMiscVoltAdjustment; ///< Register LVDS_CTRL_4 to adjust LVDS output voltage
+ ///< @BldCfgItem{BLDCFG_LVDS_MISC_VOL_ADJUSTMENT}
+ IN DISPLAY_MISC_CONTROL DisplayMiscControl;///< This item configures display misc control
+ IN DP_FIXED_VOLT_SWING_TYPE DpFixedVoltSwingType;///< To indicate fixed voltage swing value
+ ///< @BldCfgItem{BLDCFG_DP_FIXED_VOLT_SWING}
+ IN UINT32 GpuFrequencyLimit; ///< GNB GPU Max Frequency(NULL if platform configured)
+ ///< @BldCfgItem{BLDCFG_GPU_FREQUENCY_LIMIT}
+} GNB_ENV_CONFIGURATION;
+
+/// Configuration settings for GNB.
+typedef struct {
+ IN UINT8 iGpuVgaMode; ///< VGA resources decoding configuration for iGPU
+ ///< @li 0 = iGPU decode all VGA resources (must be primary VGA adapter)
+ ///< @li 1 = iGPU will not decode any VGA resources (must be secondary graphics adapter)
+ IN UINT8 PcieAcsCapability; ///< Pcie ACS Capability support
+ ///< @li 0 = Disabled
+ ///< @li 1 = Enabled
+ IN UINT64 GnbIoapicAddress; ///< GNB IOAPIC Base Address(NULL if platform configured)
+ ///< @BldCfgItem{BLDCFG_GNB_IOAPIC_ADDRESS}
+} GNB_MID_CONFIGURATION;
+
+/// GNB configuration info
+typedef struct {
+ IN const PCIe_COMPLEX_DESCRIPTOR *PcieComplexList; /**< Pointer to array of structures describe PCIe topology on each processor package or NULL.
+ * Last element of array must be terminated with DESCRIPTOR_TERMINATE_LIST
+ * Example of topology definition for single socket system:
+ * @code
+ * PCIe_PORT_DESCRIPTOR PortList [] = {
+ * // Initialize Port descriptor (PCIe port, Lanes 8:15, PCI Device Number 2, ...)
+ * {
+ * 0, //Descriptor flags
+ * PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 8, 15),
+ * PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 2, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0)
+ * },
+ * // Initialize Port descriptor (PCIe port, Lanes 16:19, PCI Device Number 3, ...)
+ * {
+ * 0, //Descriptor flags
+ * PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 16, 19),
+ * PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 3, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0)
+ * },
+ * // Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...)
+ * {
+ * DESCRIPTOR_TERMINATE_LIST, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array
+ * PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 4),
+ * PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 4, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0)
+ * }
+ * };
+ * PCIe_PORT_DESCRIPTOR DdiList [] = {
+ * // Initialize Ddi descriptor (DDI interface Lanes 24:27, Display Port Connector, ...)
+ * {
+ * 0, //Descriptor flags
+ * PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 24, 27),
+ * PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux1, Hdp1, 0)
+ * },
+ * // Initialize Ddi descriptor (DDI interface Lanes 28:31, HDMI, ...)
+ * {
+ * DESCRIPTOR_TERMINATE_LIST, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array
+ * PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 28, 31),
+ * PCIE_DDI_DATA_INITIALIZER (ConnectorTypeHDMI, Aux2, Hdp2, 0)
+ * }
+ * };
+ * PCIe_COMPLEX_DESCRIPTOR PlatformTopology = {
+ * DESCRIPTOR_TERMINATE_LIST, //Descriptor flags !!!IMPORTANT!!! Terminate complexes list
+ * 0, //Socket ID
+ * &PortList[0],
+ * &DdiList[0],
+ * }
+ * @endcode
+ */
+ IN UINT8 PsppPolicy; /**< PSPP (PCIe Speed Power Policy)
+ * @li @b 0 - Disabled
+ * @li @b 1 - Performance
+ * @li @b 2 - Balance-High
+ * @li @b 3 - Balance-Low
+ * @li @b 4 - Power Saving
+ */
+
+} GNB_CONFIGURATION;
+
+/// Late Configuration settings for GNB.
+typedef struct {
+ IN BOOLEAN DockedTdpHeadroom; ///< Docked TDP headroom
+ ///< @li TRUE = Enable docked TDP headroom
+ ///< @li FALSE = Disable docked TDP headroom
+ ///< @BldCfgItem{BLDCFG_DOCKED_TDP_HEADROOM}
+ IN UINT8 GnbIoapicId; ///< GNB IOAPIC ID, platform BIOS needs to pass correct id number, default is 0xFF.
+ ///< If BLDCFG_GNB_IOAPIC_ADDRESS == NULL or BLDCFG_IOMMU_SUPPORT == NULL or GnbIoapicId == default(0xFF), AGESA will skip it anyway.
+ ///< @li 0~n = IOAPIC ID number for IVRS which should be matched with MADT
+ IN UINT8 FchIoapicId; ///< Fch IOAPIC ID, platform BIOS needs to pass correct id number, default is 0xFF.
+ ///< If BLDCFG_IOMMU_SUPPORT == NULL or or FchIoapicId == default(0xFF), AGESA will skip it anyway.
+ ///< @li 0~n = IOAPIC ID number for IVRS which should be matched with MADT
+
+} GNB_LATE_CONFIGURATION;
+
+//
+// MEMORY-SPECIFIC DATA STRUCTURES
+//
+//
+//
+//
+// AGESA MAXIMIUM VALUES
+//
+// These Max values are used to define array sizes and associated loop
+// counts in the code. They reflect the maximum values that AGESA
+// currently supports and does not necessarily reflect the hardware
+// capabilities of configuration.
+//
+
+#define MAX_SOCKETS_SUPPORTED 1 ///< Max number of sockets in system
+#define MAX_CHANNELS_PER_SOCKET 4 ///< Max Channels per sockets
+#define MAX_DIMMS_PER_CHANNEL 4 ///< Max DIMMs on a memory channel (independent of platform)
+#define NUMBER_OF_DELAY_TABLES 9 ///< Number of tables defined in CH_DEF_STRUCT.
+ ///< Eg: UINT16 *RcvEnDlys;
+ ///< UINT8 *WrDqsDlys;
+ ///< UINT8 *RdDqsDlys;
+ ///< UINT8 *WrDatDlys;
+ ///< UINT8 *RdDqsMinDlys;
+ ///< UINT8 *RdDqsMaxDlys;
+ ///< UINT8 *WrDatMinDlys;
+ ///< UINT8 *WrDatMaxDlys;
+#define NUMBER_OF_FAILURE_MASK_TABLES 1 ///< Number of failure mask tables
+
+#define MAX_PLATFORM_TYPES 16 ///< Platform types per system
+
+#define MCT_TRNG_KEEPOUT_START 0x00004000ul ///< base [39:8]
+#define MCT_TRNG_KEEPOUT_END 0x00007FFFul ///< base [39:8]
+#define DATAEYE_VREF_RANGE 31 ///< Number of VREF steps in Data Eye Bitmap
+
+#define UMA_ATTRIBUTE_INTERLEAVE 0x80000000ul ///< Uma Region is interleaved
+#define UMA_ATTRIBUTE_ON_DCT0 0x40000000ul ///< UMA resides on memory that belongs to DCT0
+#define UMA_ATTRIBUTE_ON_DCT1 0x20000000ul ///< UMA resides on memory that belongs to DCT1
+#define UMA_ATTRIBUTE_ON_DCT2 0x10000000ul ///< UMA resides on memory that belongs to DCT2
+#define UMA_ATTRIBUTE_ON_DCT3 0x08000000ul ///< UMA resides on memory that belongs to DCT3
+
+typedef UINT8 PSO_TABLE; ///< Platform Configuration Table
+
+// AGESA DEFINITIONS
+//
+// Many of these are derived from the platform and hardware specific definitions
+
+/// EccSymbolSize override value
+#define ECCSYMBOLSIZE_USE_BKDG 0 ///< Use BKDG Recommended Value
+#define ECCSYMBOLSIZE_FORCE_X4 4 ///< Force to x4
+#define ECCSYMBOLSIZE_FORCE_X8 8 ///< Force to x8
+/// CPU Package Type
+#define PT_L1 0 ///< L1 Package type
+#define PT_M2 1 ///< AM Package type
+#define PT_S1 2 ///< S1 Package type
+
+/// Build Configuration values for BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT & BLDCFG_MEMORY_CLOCK_SELECT
+#define DDR400_FREQUENCY 200 ///< DDR 400
+#define DDR533_FREQUENCY 266 ///< DDR 533
+#define DDR667_FREQUENCY 333 ///< DDR 667
+#define DDR800_FREQUENCY 400 ///< DDR 800
+#define DDR1066_FREQUENCY 533 ///< DDR 1066
+#define DDR1333_FREQUENCY 667 ///< DDR 1333
+#define DDR1600_FREQUENCY 800 ///< DDR 1600
+#define DDR1866_FREQUENCY 933 ///< DDR 1866
+#define DDR2100_FREQUENCY 1050 ///< DDR 2100
+#define DDR2133_FREQUENCY 1066 ///< DDR 2133
+#define DDR2400_FREQUENCY 1200 ///< DDR 2400
+#define UNSUPPORTED_DDR_FREQUENCY 1201 ///< Highest limit of DDR frequency
+
+/// Build Configuration values for BLDCFG_TIMING_MODE_SELECT
+#define TIMING_MODE_AUTO 0 ///< Use best rate possible
+#define TIMING_MODE_LIMITED 1 ///< Set user top limit
+#define TIMING_MODE_SPECIFIC 2 ///< Set user specified speed
+
+/// Build Configuration values for BLDCFG_MEMORY_QUADRANK_TYPE
+#define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM
+#define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM
+
+/// Build Configuration values for BLDCFG_POWER_DOWN_MODE
+#define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode
+#define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode
+#define POWER_DOWN_MODE_AUTO 2 ///< AGESA to select power down mode
+
+/// Build Configuration limit for BLDCFG_GNB_GPU_MAX_FREQUENCY
+#define UNSUPPORTED_GPU_FREQUENCY 901 ///< Highest limit of GPU frequency
+
+/// Structures use to pass system Logical CPU-ID
+typedef struct {
+ IN OUT UINT64 Family; ///< Indicates logical ID Family
+ IN OUT UINT64 Revision; ///< Indicates logical ID Family
+} CPU_LOGICAL_ID;
+
+/// Structures use to report AMP status
+typedef struct {
+ OUT BOOLEAN AmpVoltageValid; ///< Indicates if Amp voltage is valid
+ OUT BOOLEAN AmpSupportDetectedButNotEnabled; ///< Indicates if Amp support is detected but not enabled
+ OUT BOOLEAN AmpSelectedButNotEnabled; ///< Indicates if Amp is selected but not enabled
+} AMP_STATUS;
+
+/// Normalized Critical Composite Data Eye
+/// Bit 15 represents trained eye Center
+/// Bit 0 represents eye center -15 delay steps
+/// Bit 31 represents eye center +16 delay steps
+/// Offset 0 represents +15 Vref Steps
+/// Offset 31 represents -15 Vref Steps
+typedef UINT32 COMPOSITE_DATAEYE[DATAEYE_VREF_RANGE];
+
+/// Build Configuration values for BLDCFG_AMD_PLATFORM_TYPE
+typedef enum {
+ AMD_PLATFORM_SERVER = 0x8000, ///< Server
+ AMD_PLATFORM_DESKTOP = 0x10000, ///< Desktop
+ AMD_PLATFORM_MOBILE = 0x20000, ///< Mobile
+} AMD_PLATFORM_TYPE;
+
+/// Dram technology type
+typedef enum {
+ DDR2_TECHNOLOGY, ///< DDR2 technology
+ DDR3_TECHNOLOGY, ///< DDR3 technology
+ GDDR5_TECHNOLOGY, ///< GDDR5 technology
+ UNSUPPORTED_TECHNOLOGY, ///< Unsupported technology
+} TECHNOLOGY_TYPE;
+
+/// Low voltage support
+typedef enum {
+ VOLT_INITIAL, ///< Initial value for VDDIO
+ VOLT1_5, ///< 1.5 Volt
+ VOLT1_35, ///< 1.35 Volt
+ VOLT1_25, ///< 1.25 Volt
+ VOLT_UNSUPPORTED = 0xFF ///< No common voltage found
+} DIMM_VOLTAGE;
+
+/// AMP voltage support
+typedef enum {
+ AMP_VOLT_RSVD, ///< Reserved
+ AMP_VOLT1_5, ///< 1.5 Volt
+ AMP_VOLT1_55, ///< 1.55 Volt
+ AMP_VOLT1_6, ///< 1.6 Volt
+ AMP_VOLT1_65, ///< 1.65 Volt
+ AMP_VOLT1_7, ///< 1.7 Volt
+ AMP_VOLT1_75, ///< 1.75 Volt
+ AMP_VOLT1_8, ///< 1.8 Volt
+ AMP_VOLT1_85, ///< 1.85 Volt
+ AMP_VOLT1_9, ///< 1.9 Volt
+ AMP_VOLT1_45 = 0x10, ///< 1.45 Volt
+ AMP_VOLT1_4 = 0x20, ///< 1.4 Volt
+ AMP_VOLT1_35 = 0x30, ///< 1.35 Volt
+ AMP_VOLT1_3 = 0x40, ///< 1.3 Volt
+ AMP_VOLT1_25 = 0x50, ///< 1.25 Volt
+ AMP_VOLT1_2 = 0x60 ///< 1.2 Volt
+} AMP_DIMM_VOLTAGE;
+
+/// Build Configuration values for BLDCFG_ACP_SIZE
+typedef enum {
+ NO_ACP_SIZE = 0x00, ///< NO ACP
+ ACP_SIZE_2MB = 0x20, ///< UMA 4MB aligned
+ ACP_SIZE_4MB = 0x40, ///< UMA 128MB aligned
+} ACP_SIZE;
+
+/// UMA Mode
+typedef enum {
+ UMA_NONE = 0, ///< UMA None
+ UMA_SPECIFIED = 1, ///< UMA Specified
+ UMA_AUTO = 2 ///< UMA Auto
+} UMA_MODE;
+
+/// Force Training Mode
+typedef enum {
+ FORCE_TRAIN_1D = 0, ///< 1D Training only
+ FORCE_TRAIN_2D = 1, ///< 2D Training only
+ FORCE_TRAIN_AUTO = 2 ///< Auto - 1D or 2D depending on configuration
+} FORCE_TRAIN_MODE;
+
+/// PMU Training Mode
+typedef enum {
+ PMU_TRAIN_1D = 0, ///< PMU 1D Training only
+ PMU_TRAIN_1D_2D_READ = 1, ///< PMU 1D and 2D Training read only
+ PMU_TRAIN_1D_2D = 2, ///< PMU 1D and 2D Training
+ PMU_TRAIN_AUTO = 3 ///< Auto - PMU Training depend on configuration
+} PMU_TRAIN_MODE;
+
+/// The possible DRAM prefetch mode settings.
+typedef enum {
+ DRAM_PREFETCHER_AUTO, ///< Use the recommended setting for the processor. In most cases, the recommended setting is enabled.
+ DISABLE_DRAM_PREFETCH_FOR_IO, ///< Disable DRAM prefetching for I/O requests only.
+ DISABLE_DRAM_PREFETCH_FOR_CPU, ///< Disable DRAM prefetching for requests from processor cores only.
+ DISABLE_DRAM_PREFETCHER, ///< Disable DRAM prefetching.
+ MAX_DRAM_FREFETCH_MODE ///< Not a DRAM prefetch mode, use for limit checking.
+} DRAM_PREFETCH_MODE;
+
+/// Build Configuration values for BLDCFG_UMA_ALIGNMENT
+typedef enum {
+ NO_UMA_ALIGNED = 0x00FFFFFF, ///< NO UMA aligned
+ UMA_4MB_ALIGNED = 0x00FFFFC0, ///< UMA 4MB aligned
+ UMA_128MB_ALIGNED = 0x00FFF800, ///< UMA 128MB aligned
+ UMA_256MB_ALIGNED = 0x00FFF000, ///< UMA 256MB aligned
+ UMA_512MB_ALIGNED = 0x00FFE000, ///< UMA 512MB aligned
+} UMA_ALIGNMENT;
+
+///
+/// Global MCT Configuration Status Word (GStatus)
+///
+typedef enum {
+ GsbMTRRshort, ///< Ran out of MTRRs while mapping memory
+ GsbAllECCDimms, ///< All banks of all Nodes are ECC capable
+ GsbDramECCDis, ///< Dram ECC requested but not enabled.
+ GsbSoftHole, ///< A Node Base gap was created
+ GsbHWHole, ///< A HW dram remap was created
+ GsbNodeIntlv, ///< Node Memory interleaving was enabled
+ GsbSpIntRemapHole, ///< Special condition for Node Interleave and HW remapping
+ GsbEnDIMMSpareNW, ///< Indicates that DIMM Spare can be used without a warm reset
+
+ GsbEOL ///< End of list
+} GLOBAL_STATUS_FIELD;
+
+///
+/// Local Error Status (DIE_STRUCT.ErrStatus[31:0])
+///
+typedef enum {
+ EsbNoDimms, ///< No DIMMs
+ EsbSpdChkSum, ///< SPD Checksum fail
+ EsbDimmMismatchM, ///< dimm module type(buffer) mismatch
+ EsbDimmMismatchT, ///< dimm CL/T mismatch
+ EsbDimmMismatchO, ///< dimm organization mismatch (128-bit)
+ EsbNoTrcTrfc, ///< SPD missing Trc or Trfc info
+ EsbNoCycTime, ///< SPD missing byte 23 or 25
+ EsbBkIntDis, ///< Bank interleave requested but not enabled
+ EsbDramECCDis, ///< Dram ECC requested but not enabled
+ EsbSpareDis, ///< Online spare requested but not enabled
+ EsbMinimumMode, ///< Running in Minimum Mode
+ EsbNoRcvrEn, ///< No DQS Receiver Enable pass window found
+ EsbSmallRcvr, ///< DQS Rcvr En pass window too small (far right of dynamic range)
+ EsbNoDqsPos, ///< No DQS-DQ passing positions
+ EsbSmallDqs, ///< DQS-DQ passing window too small
+ EsbDCBKScrubDis, ///< DCache scrub requested but not enabled
+
+ EsbEMPNotSupported, ///< Processor is not capable for EMP.
+ EsbEMPConflict, ///< EMP requested but cannot be enabled since
+ ///< channel interleaving, bank interleaving, or bank swizzle is enabled.
+ EsbEMPDis, ///< EMP requested but cannot be enabled since
+ ///< memory size of each DCT is not a power of two.
+
+ EsbEOL ///< End of list
+} ERROR_STATUS_FIELD;
+
+///
+/// Local Configuration Status (DIE_STRUCT.Status[31:0])
+///
+typedef enum {
+ SbRegistered, ///< All DIMMs are Registered
+ SbEccDimms, ///< All banks ECC capable
+ SbParDimms, ///< All banks Addr/CMD Parity capable
+ SbDiagClks, ///< Jedec ALL slots clock enable diag mode
+ Sb128bitmode, ///< DCT in 128-bit mode operation
+ Sb64MuxedMode, ///< DCT in 64-bit mux'ed mode.
+ Sb2TMode, ///< 2T CMD timing mode is enabled.
+ SbSWNodeHole, ///< Remapping of Node Base on this Node to create a gap.
+ SbHWHole, ///< Memory Hole created on this Node using HW remapping.
+ SbOver400Mhz, ///< DCT freq greater than or equal to 400MHz flag
+ SbDQSPosPass2, ///< Used for TrainDQSPos DIMM0/1, when freq greater than or equal to 400MHz
+ SbDQSRcvLimit, ///< Used for DQSRcvEnTrain to know we have reached the upper bound.
+ SbExtConfig, ///< Indicate the default setting for extended PCI configuration support
+ SbLrdimms, ///< All DIMMs are LRDIMMs
+
+ SbEOL ///< End of list
+} LOCAL_STATUS_FIELD;
+
+
+///< CPU MSR Register definitions ------------------------------------------
+#define SYS_CFG 0xC0010010ul
+#define TOP_MEM 0xC001001Aul
+#define TOP_MEM2 0xC001001Dul
+#define HWCR 0xC0010015ul
+#define NB_CFG 0xC001001Ful
+
+#define FS_BASE 0xC0000100ul
+#define IORR0_BASE 0xC0010016ul
+#define IORR0_MASK 0xC0010017ul
+#define BU_CFG 0xC0011023ul
+#define BU_CFG2 0xC001102Aul
+#define COFVID_STAT 0xC0010071ul
+#define TSC 0x10
+
+//-----------------------------------------------------------------------------
+///
+/// SPD Data for each DIMM.
+///
+typedef struct _SPD_DEF_STRUCT {
+ IN BOOLEAN DimmPresent; ///< Indicates that the DIMM is present and Data is valid
+ IN UINT8 Data[256]; ///< Buffer for 256 Bytes of SPD data from DIMM
+} SPD_DEF_STRUCT;
+
+
+//-----------------------------------------------------------------------------
+///
+/// VDDP_VDDR Voltage Info for Low Power DIMM
+///
+typedef struct _VDDP_VDDR_VOLTAGE {
+ IN BOOLEAN IsValid; ///< Indicates if daata is valid
+ IN MEMORY_PHY_VOLTAGE Voltage; ///< VDDP VDDR Voltage Value
+} VDDP_VDDR_VOLTAGE;
+
+///
+/// Channel Definition Structure.
+/// This data structure defines entries that are specific to the channel initialization
+///
+typedef struct _CH_DEF_STRUCT {
+ OUT UINT8 ChannelID; ///< Physical channel ID of a socket(0 = CH A, 1 = CH B, 2 = CH C, 3 = CH D)
+ OUT TECHNOLOGY_TYPE TechType; ///< Technology type of this channel
+ OUT UINT8 ChDimmPresent; ///< For each bit n 0..7, 1 = DIMM n is present.
+ ///< DIMM# Select Signal
+ ///< 0 MA0_CS_L[0, 1]
+ ///< 1 MB0_CS_L[0, 1]
+ ///< 2 MA1_CS_L[0, 1]
+ ///< 3 MB1_CS_L[0, 1]
+ ///< 4 MA2_CS_L[0, 1]
+ ///< 5 MB2_CS_L[0, 1]
+ ///< 6 MA3_CS_L[0, 1]
+ ///< 7 MB3_CS_L[0, 1]
+
+ OUT struct _DCT_STRUCT *DCTPtr; ///< Pointer to the DCT data of this channel.
+ OUT struct _DIE_STRUCT *MCTPtr; ///< Pointer to the node data of this channel.
+ OUT SPD_DEF_STRUCT *SpdPtr; ///< Pointer to the SPD data for this channel. (Setup by NB Constructor)
+ OUT SPD_DEF_STRUCT *DimmSpdPtr[MAX_DIMMS_PER_CHANNEL]; ///< Array of pointers to
+ ///< SPD Data for each Dimm. (Setup by Tech Block Constructor)
+ OUT UINT8 ChDimmValid; ///< For each bit n 0..3, 1 = DIMM n is valid and is/will be configured where 4..7 are reserved.
+ ///<
+ OUT UINT8 RegDimmPresent; ///< For each bit n 0..3, 1 = DIMM n is a registered DIMM where 4..7 are reserved.
+ OUT UINT8 LrDimmPresent; ///< For each bit n 0..3, 1 = DIMM n is Load Reduced DIMM where 4..7 are reserved.
+ OUT UINT8 SODimmPresent; ///< For each bit n 0..3, 1 = DIMM n is a SO-DIMM, where 4..7 are reserved.
+ OUT UINT8 Loads; ///< Number of devices loading bus
+ OUT UINT8 Dimms; ///< Number of DIMMs loading Channel
+ OUT UINT8 Ranks; ///< Number of ranks loading Channel DATA
+ OUT BOOLEAN SlowMode; ///< 1T or 2T CMD mode (slow access mode)
+ OUT BOOLEAN SlowModePs1; ///< 1T or 2T CMD mode (slow access mode) for Mem Pstate 1
+ ///< FALSE = 1T
+ ///< TRUE = 2T
+ ///< The following pointers will be pointed to dynamically allocated buffers.
+ ///< Each buffer is two dimensional (RowCount x ColumnCount) and is lay-outed as in below.
+ ///< Example: If DIMM and Byte based training, then
+ ///< XX is a value in Hex
+ ///< BYTE 0, BYTE 1, BYTE 2, BYTE 3, BYTE 4, BYTE 5, BYTE 6, BYTE 7, ECC BYTE
+ ///< Row1 - Logical DIMM0 XX XX XX XX XX XX XX XX XX
+ ///< Row2 - Logical DIMM1 XX XX XX XX XX XX XX XX XX
+ OUT UINT16 *RcvEnDlys; ///< DQS Receiver Enable Delays
+ OUT UINT8 *WrDqsDlys; ///< Write DQS delays (only valid for DDR3)
+ OUT UINT8 *RdDqsDlys; ///< Read Dqs delays
+ OUT UINT8 *WrDatDlys; ///< Write Data delays
+ OUT UINT8 *RdDqs2dDlys; ///< 2d Read DQS data
+ OUT UINT8 *RdDqsMinDlys; ///< Minimum Window for Read DQS
+ OUT UINT8 *RdDqsMaxDlys; ///< Maximum Window for Read DQS
+ OUT UINT8 *WrDatMinDlys; ///< Minimum Window for Write data
+ OUT UINT8 *WrDatMaxDlys; ///< Maximum Window for Write data
+ OUT UINT16 *RcvEnDlysMemPs1; ///< DQS Receiver Enable Delays for Mem Pstate 1
+ OUT UINT8 *WrDqsDlysMemPs1; ///< Write DQS delays (only valid for DDR3) for Mem Pstate 1
+ OUT UINT8 *RdDqsDlysMemPs1; ///< Read Dqs delays for Memory Pstate 1
+ OUT UINT8 *WrDatDlysMemPs1; ///< Write Data delays for Memory Pstate 1
+ OUT UINT8 *RdDqs2dDlysMemPs1; ///< 2d Read DQS data for Memory Pstate 1
+ OUT UINT8 *RdDqsMinDlysMemPs1; ///< Minimum Window for Read DQS for Memory Pstate 1
+ OUT UINT8 *RdDqsMaxDlysMemPs1; ///< Maximum Window for Read DQS for Memory Pstate 1
+ OUT UINT8 *WrDatMinDlysMemPs1; ///< Minimum Window for Write data for Memory Pstate 1
+ OUT UINT8 *WrDatMaxDlysMemPs1; ///< Maximum Window for Write data for Memory Pstate 1
+ OUT UINT8 RowCount; ///< Number of rows of the allocated buffer.
+ OUT UINT8 ColumnCount; ///< Number of columns of the allocated buffer.
+ OUT UINT8 *FailingBitMask; ///< Table of masks to Track Failing bits
+ OUT UINT8 *FailingBitMaskMemPs1; ///< Table of masks to Track Failing bits for Memory Pstate 1
+ OUT VOID *RdDataEyes; ///< Pointer to Read Data Eye Bitmaps
+ OUT VOID *WrDataEyes; ///< Pointer to Write Data Eye Bitmaps
+ OUT UINT32 DctOdcCtl; ///< Output Driver Strength (see BKDG FN2:Offset 9Ch, index 00h)
+ OUT UINT32 DctAddrTmg; ///< Address Bus Timing (see BKDG FN2:Offset 9Ch, index 04h)
+ OUT UINT32 DctAddrTmgPs1; ///< Address Bus Timing (see BKDG FN2:Offset 9Ch, index 04h) for Mem Pstate 1
+ OUT UINT32 PhyRODTCSLow; ///< Phy Read ODT Pattern Chip Select low (see BKDG FN2:Offset 9Ch, index 180h)
+ OUT UINT32 PhyRODTCSHigh; ///< Phy Read ODT Pattern Chip Select high (see BKDG FN2:Offset 9Ch, index 181h)
+ OUT UINT32 PhyWODTCSLow; ///< Phy Write ODT Pattern Chip Select low (see BKDG FN2:Offset 9Ch, index 182h)
+ OUT UINT32 PhyWODTCSHigh; ///< Phy Write ODT Pattern Chip Select high (see BKDG FN2:Offset 9Ch, index 183)
+ OUT UINT8 PhyWLODT[4]; ///< Write Levelization ODT Pattern for Dimm 0-3 or CS 0-7(see BKDG FN2:Offset 9Ch, index 0x8[11:8])
+ OUT UINT16 DctEccDqsLike; ///< DCT DQS ECC UINT8 like...
+ OUT UINT8 DctEccDqsScale; ///< DCT DQS ECC UINT8 scale
+ OUT UINT16 PtrPatternBufA; ///< Ptr on stack to aligned DQS testing pattern
+ OUT UINT16 PtrPatternBufB; ///< Ptr on stack to aligned DQS testing pattern
+ OUT UINT8 ByteLane; ///< Current UINT8 Lane (0..7)
+ OUT UINT8 Direction; ///< Current DQS-DQ training write direction (0=read, 1=write)
+ OUT UINT8 Pattern; ///< Current pattern
+ OUT UINT8 DqsDelay; ///< Current DQS delay value
+ OUT UINT16 HostBiosSrvc1; ///< UINT16 sized general purpose field for use by host BIOS. Scratch space.
+ OUT UINT32 HostBiosSrvc2; ///< UINT32 sized general purpose field for use by host BIOS. Scratch space.
+ OUT UINT16 DctMaxRdLat[4]; ///< Max Read Latency (ns) for the DCT
+ ///< DctMaxRdLat [i] is for NBPstate i
+ OUT UINT8 DIMMValidCh; ///< DIMM# in CH
+ OUT UINT8 MaxCh; ///< Max number of CH in system
+ OUT UINT8 Dct; ///< Dct pointer
+ OUT UINT8 WrDatGrossH; ///< Write Data Gross delay high value
+ OUT UINT8 DqsRcvEnGrossL; ///< DQS Receive Enable Gross Delay low
+
+ OUT UINT8 TrwtWB; ///< Non-SPD timing value for TrwtWB
+ OUT UINT8 CurrRcvrDctADelay; ///< for keep current RcvrEnDly
+ OUT UINT16 T1000; ///< get the T1000 figure (cycle time (ns) * 1K)
+ OUT UINT8 DqsRcvEnPass; ///< for TrainRcvrEn UINT8 lane pass flag
+ OUT UINT8 DqsRcvEnSaved; ///< for TrainRcvrEn UINT8 lane saved flag
+ OUT UINT8 SeedPass1Remainder; ///< for Phy assisted DQS receiver enable training
+
+ OUT UINT8 ClToNbFlag; ///< is used to restore ClLinesToNbDis bit after memory
+ OUT UINT32 NodeSysBase; ///< for channel interleave usage
+ OUT UINT8 RefRawCard[MAX_DIMMS_PER_CHANNEL]; ///< Array of rawcards detected
+ OUT UINT8 CtrlWrd02[MAX_DIMMS_PER_CHANNEL]; ///< Control Word 2 values per DIMM
+ OUT UINT8 CtrlWrd03[MAX_DIMMS_PER_CHANNEL]; ///< Control Word 3 values per DIMM
+ OUT UINT8 CtrlWrd04[MAX_DIMMS_PER_CHANNEL]; ///< Control Word 4 values per DIMM
+ OUT UINT8 CtrlWrd05[MAX_DIMMS_PER_CHANNEL]; ///< Control Word 5 values per DIMM
+ OUT UINT8 CtrlWrd08[MAX_DIMMS_PER_CHANNEL]; ///< Control Word 8 values per DIMM
+
+ OUT UINT16 CsPresentDCT; ///< For each bit n 0..7, 1 = Chip-select n is present
+ OUT UINT8 DimmMirrorPresent; ///< For each bit n 0..3, 1 = DIMM n is OnDimmMirror capable where 4..7 are reserved.
+ OUT UINT8 DimmSpdCse; ///< For each bit n 0..3, 1 = DIMM n SPD checksum error where 4..7 are reserved.
+ OUT UINT8 DimmExclude; ///< For each bit n 0..3, 1 = DIMM n gets excluded where 4..7 are reserved.
+ OUT UINT8 DimmYr06; ///< Bitmap indicating which Dimms have a manufacturer's year code <= 2006
+ OUT UINT8 DimmWk2406; ///< Bitmap indicating which Dimms have a manufacturer's week code <= 24 of 2006 (June)
+ OUT UINT8 DimmPlPresent; ///< Bitmap indicating that Planar (1) or Stacked (0) Dimms are present.
+ OUT UINT8 DimmQrPresent; ///< QuadRank DIMM present?
+ OUT UINT8 DimmDrPresent; ///< Bitmap indicating that Dual Rank Dimms are present
+ OUT UINT8 DimmSRPresent; ///< Bitmap indicating that Single Rank Dimms are present
+ OUT UINT8 Dimmx4Present; ///< For each bit n 0..3, 1 = DIMM n contains x4 data devices. where 4..7 are reserved.
+ OUT UINT8 Dimmx8Present; ///< For each bit n 0..3, 1 = DIMM n contains x8 data devices. where 4..7 are reserved.
+ OUT UINT8 Dimmx16Present; ///< For each bit n 0..3, 1 = DIMM n contains x16 data devices. where 4..7 are reserved.
+ OUT UINT8 LrdimmPhysicalRanks[MAX_DIMMS_PER_CHANNEL];///< Number of Physical Ranks for LRDIMMs
+ OUT UINT8 LrDimmLogicalRanks[MAX_DIMMS_PER_CHANNEL];///< Number of LRDIMM Logical ranks in this configuration
+ OUT UINT8 LrDimmRankMult[MAX_DIMMS_PER_CHANNEL];///< Rank Multipication factor per dimm.
+ OUT UINT8 DimmNibbleAccess; ///< For each bit n 0..3, 1 = DIMM n will use nibble signaling. Where 4..7 are reserved.
+ OUT UINT8 *MemClkDisMap; ///< This pointer will be set to point to an array that describes
+ ///< the routing of M[B,A]_CLK pins to the DIMMs' ranks. AGESA will
+ ///< base on this array to disable unused MemClk to save power.
+ ///<
+ ///< The array must have 8 entries. Each entry, which associates with
+ ///< one MemClkDis bit, is a bitmap of 8 CS that that MemClk is routed to.
+ ///< Example:
+ ///< BKDG definition of Fn2x88[MemClkDis] bitmap for AM3 package
+ ///< is like below:
+ ///< Bit AM3/S1g3 pin name
+ ///< 0 M[B,A]_CLK_H/L[0]
+ ///< 1 M[B,A]_CLK_H/L[1]
+ ///< 2 M[B,A]_CLK_H/L[2]
+ ///< 3 M[B,A]_CLK_H/L[3]
+ ///< 4 M[B,A]_CLK_H/L[4]
+ ///< 5 M[B,A]_CLK_H/L[5]
+ ///< 6 M[B,A]_CLK_H/L[6]
+ ///< 7 M[B,A]_CLK_H/L[7]
+ ///< And platform has the following routing:
+ ///< CS0 M[B,A]_CLK_H/L[4]
+ ///< CS1 M[B,A]_CLK_H/L[2]
+ ///< CS2 M[B,A]_CLK_H/L[3]
+ ///< CS3 M[B,A]_CLK_H/L[5]
+ ///< Then MemClkDisMap should be pointed to the following array:
+ ///< CLK_2 CLK_3 CLK_4 CLK_5
+ ///< 0x00, 0x00, 0x02, 0x04, 0x01, 0x08, 0x00, 0x00
+ ///< Each entry of the array is the bitmask of 8 chip selects.
+
+ OUT UINT8 *CKETriMap; ///< This pointer will be set to point to an array that describes
+ ///< the routing of CKE pins to the DIMMs' ranks.
+ ///< The array must have 2 entries. Each entry, which associates with
+ ///< one CKE pin, is a bitmap of 8 CS that that CKE is routed to.
+ ///< AGESA will base on this array to disable unused CKE pins to save power.
+
+ OUT UINT8 *ODTTriMap; ///< This pointer will be set to point to an array that describes
+ ///< the routing of ODT pins to the DIMMs' ranks.
+ ///< The array must have 4 entries. Each entry, which associates with
+ ///< one ODT pin, is a bitmap of 8 CS that that ODT is routed to.
+ ///< AGESA will base on this array to disable unused ODT pins to save power.
+
+ OUT UINT8 *ChipSelTriMap; ///< This pointer will be set to point to an array that describes
+ ///< the routing of chip select pins to the DIMMs' ranks.
+ ///< The array must have 8 entries. Each entry is a bitmap of 8 CS.
+ ///< AGESA will base on this array to disable unused Chip select pins to save power.
+
+ OUT BOOLEAN ExtendTmp; ///< If extended temperature is supported on all dimms on a channel.
+
+ OUT UINT8 MaxVref; ///< Maximum Vref Value for channel
+
+ OUT UINT8 Reserved[100]; ///< Reserved
+} CH_DEF_STRUCT;
+
+///
+/// DCT Channel Timing Parameters.
+/// This data structure sets timings that are specific to the channel.
+///
+typedef struct _CH_TIMING_STRUCT {
+ OUT UINT16 DctDimmValid; ///< For each bit n 0..3, 1=DIMM n is valid and is/will be configured where 4..7 are reserved.
+ OUT UINT16 DimmMirrorPresent; ///< For each bit n 0..3, 1=DIMM n is OnDimmMirror capable where 4..7 are reserved.
+ OUT UINT16 DimmSpdCse; ///< For each bit n 0..3, 1=DIMM n SPD checksum error where 4..7 are reserved.
+ OUT UINT16 DimmExclude; ///< For each bit n 0..3, 1 = DIMM n gets excluded where 4..7 are reserved.
+ OUT UINT16 CsPresent; ///< For each bit n 0..7, 1=Chip-select n is present
+ OUT UINT16 CsEnabled; ///< For each bit n 0..7, 1=Chip-select n is enabled
+ OUT UINT16 CsTestFail; ///< For each bit n 0..7, 1=Chip-select n is present but disabled
+ OUT UINT16 CsTrainFail; ///< Bitmap showing which chipselects failed training
+ OUT UINT16 DIMM1KPage; ///< For each bit n 0..3, 1=DIMM n contains 1K page devices. where 4..7 are reserved
+ OUT UINT16 DimmQrPresent; ///< QuadRank DIMM present?
+ OUT UINT16 DimmDrPresent; ///< Bitmap indicating that Dual Rank Dimms are present , where 4..7 are reserved
+ OUT UINT8 DimmSRPresent; ///< Bitmap indicating that Single Rank Dimms are present, where 4..7 are reserved
+ OUT UINT16 Dimmx4Present; ///< For each bit n 0..3, 1=DIMM n contains x4 data devices. where 4..7 are reserved
+ OUT UINT16 Dimmx8Present; ///< For each bit n 0..3, 1=DIMM n contains x8 data devices. where 4..7 are reserved
+ OUT UINT16 Dimmx16Present; ///< For each bit n 0..3, 1=DIMM n contains x16 data devices. where 4..7 are reserved
+
+ OUT UINT16 DIMMTrcd; ///< Minimax Trcd*40 (ns) of DIMMs
+ OUT UINT16 DIMMTrp; ///< Minimax Trp*40 (ns) of DIMMs
+ OUT UINT16 DIMMTrtp; ///< Minimax Trtp*40 (ns) of DIMMs
+ OUT UINT16 DIMMTras; ///< Minimax Tras*40 (ns) of DIMMs
+ OUT UINT16 DIMMTrc; ///< Minimax Trc*40 (ns) of DIMMs
+ OUT UINT16 DIMMTwr; ///< Minimax Twr*40 (ns) of DIMMs
+ OUT UINT16 DIMMTrrd; ///< Minimax Trrd*40 (ns) of DIMMs
+ OUT UINT16 DIMMTwtr; ///< Minimax Twtr*40 (ns) of DIMMs
+ OUT UINT16 DIMMTfaw; ///< Minimax Tfaw*40 (ns) of DIMMs
+ OUT UINT16 TargetSpeed; ///< Target DRAM bus speed in MHz
+ OUT UINT16 Speed; ///< DRAM bus speed in MHz
+ ///< 400 (MHz)
+ ///< 533 (MHz)
+ ///< 667 (MHz)
+ ///< 800 (MHz)
+ ///< and so on...
+ OUT UINT8 CasL; ///< CAS latency DCT setting (busclocks)
+ OUT UINT8 Trcd; ///< DCT Trcd (busclocks)
+ OUT UINT8 Trp; ///< DCT Trp (busclocks)
+ OUT UINT8 Trtp; ///< DCT Trtp (busclocks)
+ OUT UINT8 Tras; ///< DCT Tras (busclocks)
+ OUT UINT8 Trc; ///< DCT Trc (busclocks)
+ OUT UINT8 Twr; ///< DCT Twr (busclocks)
+ OUT UINT8 Trrd; ///< DCT Trrd (busclocks)
+ OUT UINT8 Twtr; ///< DCT Twtr (busclocks)
+ OUT UINT8 Tfaw; ///< DCT Tfaw (busclocks)
+ OUT UINT8 Trfc0; ///< DCT Logical DIMM0 Trfc
+ ///< 0 = 75ns (for 256Mb devs)
+ ///< 1 = 105ns (for 512Mb devs)
+ ///< 2 = 127.5ns (for 1Gb devs)
+ ///< 3 = 195ns (for 2Gb devs)
+ ///< 4 = 327.5ns (for 4Gb devs)
+ OUT UINT8 Trfc1; ///< DCT Logical DIMM1 Trfc (see Trfc0 for format)
+ OUT UINT8 Trfc2; ///< DCT Logical DIMM2 Trfc (see Trfc0 for format)
+ OUT UINT8 Trfc3; ///< DCT Logical DIMM3 Trfc (see Trfc0 for format)
+ OUT UINT32 DctMemSize; ///< Base[47:16], total DRAM size controlled by this DCT.
+ ///<
+ OUT BOOLEAN SlowMode; ///< 1T or 2T CMD mode (slow access mode)
+ ///< FALSE = 1T
+ ///< TRUE = 2T
+ OUT UINT8 TrwtTO; ///< DCT TrwtTO (busclocks)
+ OUT UINT8 Twrrd; ///< DCT Twrrd (busclocks)
+ OUT UINT8 Twrwr; ///< DCT Twrwr (busclocks)
+ OUT UINT8 Trdrd; ///< DCT Trdrd (busclocks)
+ OUT UINT8 TrwtWB; ///< DCT TrwtWB (busclocks)
+ OUT UINT8 TrdrdSD; ///< DCT TrdrdSD (busclocks)
+ OUT UINT8 TwrwrSD; ///< DCT TwrwrSD (busclocks)
+ OUT UINT8 TwrrdSD; ///< DCT TwrrdSD (busclocks)
+ OUT UINT16 MaxRdLat; ///< Max Read Latency
+ OUT UINT8 WrDatGrossH; ///< Temporary variables must be removed
+ OUT UINT8 DqsRcvEnGrossL; ///< Temporary variables must be removed
+} CH_TIMING_STRUCT;
+
+///
+/// Data for each DCT.
+/// This data structure defines data used to configure each DRAM controller.
+///
+typedef struct _DCT_STRUCT {
+ OUT UINT8 Dct; ///< Current Dct
+ OUT CH_TIMING_STRUCT Timings; ///< Channel Timing structure
+ OUT CH_TIMING_STRUCT *TimingsMemPs1; ///< Pointed to channel timing structure for memory Pstate 1
+ OUT CH_DEF_STRUCT *ChData; ///< Pointed to a dynamically allocated array of Channel structures
+ OUT UINT8 ChannelCount; ///< Number of channel per this DCT
+ OUT BOOLEAN BkIntDis; ///< Bank interleave requested but not enabled on current DCT
+ OUT UINT8 BankAddrMap; ///< Bank Address Mapping
+ OUT UINT8 EnabledChipSels; ///< Number of enabled chip selects on current DCT
+} DCT_STRUCT;
+
+
+///
+/// Data Structure defining each Die.
+/// This data structure contains information that is used to configure each Die.
+///
+typedef struct _DIE_STRUCT {
+
+ /// Advanced:
+
+ OUT UINT8 NodeId; ///< Node ID of current controller
+ OUT UINT8 SocketId; ///< Socket ID of this Die
+ OUT UINT8 DieId; ///< ID of this die relative to the socket
+ OUT PCI_ADDR PciAddr; ///< Pci bus and device number of this controller.
+ OUT AGESA_STATUS ErrCode; ///< Current error condition of Node
+ ///< 0x0 = AGESA_SUCCESS
+ ///< 0x1 = AGESA_UNSUPPORTED
+ ///< 0x2 = AGESA_BOUNDS_CHK
+ ///< 0x3 = AGESA_ALERT
+ ///< 0x4 = AGESA_WARNING
+ ///< 0x5 = AGESA_ERROR
+ ///< 0x6 = AGESA_CRITICAL
+ ///< 0x7 = AGESA_FATAL
+ ///<
+ OUT BOOLEAN ErrStatus[EsbEOL]; ///< Error Status bit Field
+ ///<
+ OUT BOOLEAN Status[SbEOL]; ///< Status bit Field
+ ///<
+ OUT UINT32 NodeMemSize; ///< Base[47:16], total DRAM size controlled by both DCT0 and DCT1 of this Node.
+ ///<
+ OUT UINT32 NodeSysBase; ///< Base[47:16] (system address) DRAM base address of this Node.
+ ///<
+ OUT UINT32 NodeHoleBase; ///< If not zero, Base[47:16] (system address) of dram hole for HW remapping. Dram hole exists on this Node
+ ///<
+ OUT UINT32 NodeSysLimit; ///< Base[47:16] (system address) DRAM limit address of this Node.
+ ///<
+ OUT UINT32 DimmPresent; ///< For each bit n 0..7, 1 = DIMM n is present.
+ ///< DIMM# Select Signal
+ ///< 0 MA0_CS_L[0, 1]
+ ///< 1 MB0_CS_L[0, 1]
+ ///< 2 MA1_CS_L[0, 1]
+ ///< 3 MB1_CS_L[0, 1]
+ ///< 4 MA2_CS_L[0, 1]
+ ///< 5 MB2_CS_L[0, 1]
+ ///< 6 MA3_CS_L[0, 1]
+ ///< 7 MB3_CS_L[0, 1]
+ ///<
+ OUT UINT32 DimmValid; ///< For each bit n 0..7, 1 = DIMM n is valid and is / will be configured
+ OUT UINT32 RegDimmPresent; ///< For each bit n 0..7, 1 = DIMM n is registered DIMM
+ OUT UINT32 LrDimmPresent; ///< For each bit n 0..7, 1 = DIMM n is Load Reduced DIMM
+ OUT UINT32 DimmEccPresent; ///< For each bit n 0..7, 1 = DIMM n is ECC capable.
+ OUT UINT32 DimmParPresent; ///< For each bit n 0..7, 1 = DIMM n is ADR/CMD Parity capable.
+ ///<
+ OUT UINT16 DimmTrainFail; ///< Bitmap showing which dimms failed training
+ OUT UINT16 ChannelTrainFail; ///< Bitmap showing the channel information about failed Chip Selects
+ ///< 0 in any bit field indicates Channel 0
+ ///< 1 in any bit field indicates Channel 1
+ OUT UINT8 Dct; ///< Need to be removed
+ ///< DCT pointer
+ OUT BOOLEAN GangedMode; ///< Ganged mode
+ ///< 0 = disabled
+ ///< 1 = enabled
+ OUT CPU_LOGICAL_ID LogicalCpuid; ///< The logical CPUID of the node
+ ///<
+ OUT UINT16 HostBiosSrvc1; ///< UINT16 sized general purpose field for use by host BIOS. Scratch space.
+ ///<
+ OUT UINT32 HostBiosSrvc2; ///< UINT32 sized general purpose field for use by host BIOS. Scratch space.
+ ///<
+ OUT UINT8 MLoad; ///< Need to be removed
+ ///< Number of devices loading MAA bus
+ ///<
+ OUT UINT8 MaxAsyncLat; ///< Legacy wrapper
+ ///<
+ OUT UINT8 ChbD3Rcvrdly; ///< Legacy wrapper
+ ///<
+ OUT UINT16 ChaMaxRdLat; ///< Max Read Latency (ns) for DCT 0
+ ///<
+ OUT UINT8 ChbD3BcRcvrdly; ///< CHB DIMM 3 Check UINT8 Receiver Enable Delay
+
+ OUT DCT_STRUCT *DctData; ///< Pointed to a dynamically allocated array of DCT_STRUCTs
+ OUT UINT8 DctCount; ///< Number of DCTs per this Die
+ OUT UINT8 Reserved[16]; ///< Reserved
+} DIE_STRUCT;
+
+/**********************************************************************
+ * S3 Support structure
+ **********************************************************************/
+/// AmdInitResume, AmdS3LateRestore, and AmdS3Save param structure
+typedef struct {
+ OUT UINT32 Signature; ///< "ASTR" for AMD Suspend-To-RAM
+ OUT UINT16 Version; ///< S3 Params version number
+ IN OUT UINT32 Flags; ///< Indicates operation
+ IN OUT VOID *NvStorage; ///< Pointer to memory critical save state data
+ IN OUT UINT32 NvStorageSize; ///< Size in bytes of the NvStorage region
+ IN OUT VOID *VolatileStorage; ///< Pointer to remaining AMD save state data
+ IN OUT UINT32 VolatileStorageSize; ///< Size in bytes of the VolatileStorage region
+} AMD_S3_PARAMS;
+
+///===============================================================================
+/// MEM_PARAMETER_STRUCT
+/// This data structure is used to pass wrapper parameters to the memory configuration code
+///
+typedef struct _MEM_PARAMETER_STRUCT {
+
+ // Basic (Return parameters)
+ // (This section contains the outbound parameters from the memory init code)
+
+ OUT BOOLEAN GStatus[GsbEOL]; ///< Global Status bitfield.
+ ///<
+ OUT UINT32 HoleBase; ///< If not zero Base[47:16] (system address) of sub 4GB dram hole for HW remapping.
+ ///<
+ OUT UINT32 Sub4GCacheTop; ///< If not zero, the 32-bit top of cacheable memory.
+ ///<
+ OUT UINT32 Sub1THoleBase; ///< If not zero Base[47:16] (system address) of sub 1TB dram hole.
+ ///<
+ OUT UINT32 SysLimit; ///< Limit[47:16] (system address).
+ ///<
+ OUT DIMM_VOLTAGE DDR3Voltage; ///< Find support voltage and send back to platform BIOS.
+ ///<
+ OUT VDDP_VDDR_VOLTAGE VddpVddrVoltage; ///< For a given configuration, request is made to change the VDDP/VDDR
+ ///< voltage in platform BIOS via AgesaHookBeforeDramInit callout and
+ ///< MEM_PARAMETER_STRUCT.VddpVddrVoltage.Voltage parameter if
+ ///< MEM_PARAMETER_STRUCT.VddpVddrVoltage.IsValid is TRUE. The
+ ///< MEM_PARAMETER_STRUCT.VddpVddrVoltage.Voltage is defined in
+ ///< MEMORY_PHY_VOLTAGE
+ OUT UINT8 ExternalVrefValue; ///< Target reference voltage for external Vref for 2D training
+ ///<
+ OUT struct _MEM_DATA_STRUCT *MemData; ///< Access to global memory init data.
+
+ // Advanced (Optional parameters)
+ // Optional (all defaults values will be initialized by the
+ // 'AmdMemInitDataStructDef' based on AMD defaults. It is up
+ // to the IBV/OEM to change the defaults after initialization
+ // but prior to the main entry to the memory code):
+
+ // Memory Map/Mgt.
+
+ IN UINT16 BottomIo; ///< Bottom of 32-bit IO space (8-bits).
+ ///< NV_BOTTOM_IO[7:0]=Addr[31:24]
+ ///<
+ IN BOOLEAN MemHoleRemapping; ///< Memory Hole Remapping (1-bit).
+ ///< FALSE = disable
+ ///< TRUE = enable
+ ///<
+ IN BOOLEAN LimitMemoryToBelow1Tb;///< Limit memory address space to below 1 TB
+ ///< FALSE = disable
+ ///< TRUE = enable
+ ///<
+ ///< @BldCfgItem{BLDCFG_LIMIT_MEMORY_TO_BELOW_1TB}
+
+
+ // Dram Timing
+
+ IN UINT32 UserTimingMode; ///< User Memclock Mode.
+ ///< @BldCfgItem{BLDCFG_TIMING_MODE_SELECT}
+
+ IN UINT32 MemClockValue; ///< Memory Clock Value.
+ ///< @BldCfgItem{BLDCFG_MEMORY_CLOCK_SELECT}
+
+
+ // Dram Configuration
+
+ IN BOOLEAN EnableBankIntlv; ///< Dram Bank (chip-select) Interleaving (1-bit).
+ ///< - FALSE =disable (default)
+ ///< - TRUE = enable
+ ///<
+ ///< @BldCfgItem{BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING}
+
+ IN BOOLEAN EnableNodeIntlv; ///< Node Memory Interleaving (1-bit).
+ ///< - FALSE = disable (default)
+ ///< - TRUE = enable
+ ///<
+ ///< @BldCfgItem{BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING}
+
+ IN BOOLEAN EnableChannelIntlv; ///< Channel Interleaving (1-bit).
+ ///< - FALSE = disable (default)
+ ///< - TRUE = enable
+ ///<
+ ///< @BldCfgItem{BLDCFG_MEMORY_CHANNEL_INTERLEAVING}
+ // DllPDBypassMode
+
+ IN BOOLEAN EnableDllPDBypassMode;///< Enable low-power DDR phy operation. This feature is used for low-power
+ ///< solder-down DRAM motherboard designs with route matched CK/DQS/DQ signals.
+ ///< It limits maximim achieveable DDR rates on the platform and should not be
+ ///< enabled for systems requiring high DDR rate operation and/or DIMM-based systems.
+ ///< - FALSE = disable
+ ///< - TRUE = enable (default)
+ ///<
+ ///< @BldCfgItem{BLDCFG_DDR_PHY_DLL_BYPASS_MODE}
+ // ECC
+
+ IN BOOLEAN EnableEccFeature; ///< enable ECC error to go into MCE.
+ ///< - FALSE = disable (default)
+ ///< - TRUE = enable
+ ///<
+ ///< @BldCfgItem{BLDCFG_ENABLE_ECC_FEATURE}
+ // Dram Power
+
+ IN BOOLEAN EnablePowerDown; ///< CKE based power down mode (1-bit).
+ ///< - FALSE =disable (default)
+ ///< - TRUE =enable
+ ///<
+ ///< @BldCfgItem{BLDCFG_MEMORY_POWER_DOWN}
+
+ // Online Spare
+
+ IN BOOLEAN EnableOnLineSpareCtl; ///< Chip Select Spare Control bit 0.
+ ///< - FALSE = disable Spare (default)
+ ///< - TRUE = enable Spare
+ ///<
+ ///< @BldCfgItem{BLDCFG_ONLINE_SPARE}
+
+ IN UINT8 *TableBasedAlterations; ///< Desired modifications to register settings.
+
+ IN PSO_TABLE *PlatformMemoryConfiguration;
+ ///< A table that contains platform specific settings.
+ ///< For example, MemClk routing, the number of DIMM slots per channel, ....
+ ///< AGESA initializes this pointer with DefaultPlatformMemoryConfiguration that
+ ///< contains default conservative settings. Platform BIOS can either tweak
+ ///< DefaultPlatformMemoryConfiguration or reassign this pointer to its own table.
+ ///<
+ IN BOOLEAN EnableParity; ///< Parity control.
+ ///< - TRUE = enable
+ ///< - FALSE = disable (default)
+ ///<
+ ///< @BldCfgItem{BLDCFG_MEMORY_PARITY_ENABLE}
+
+ IN BOOLEAN EnableBankSwizzle; ///< BankSwizzle control.
+ ///< - FALSE = disable
+ ///< - TRUE = enable (default)
+ ///<
+ ///< @BldCfgItem{BLDCFG_BANK_SWIZZLE}
+
+ ///<
+
+ IN BOOLEAN EnableMemClr; ///< Memory Clear functionality control.
+ ///< - FALSE = disable
+ ///< - TRUE = enable (default)
+ ///<
+
+ // Uma Configuration
+
+ IN UMA_MODE UmaMode; ///< Uma Mode
+ ///< 0 = None
+ ///< 1 = Specified
+ ///< 2 = Auto
+ IN OUT UINT32 UmaSize; ///< The size of shared graphics dram (16-bits)
+ ///< NV_UMA_Size[31:0]=Addr[47:16]
+ ///<
+ OUT UINT32 UmaBase; ///< The allocated Uma base address (32-bits)
+ ///< NV_UMA_Base[31:0]=Addr[47:16]
+ ///<
+
+ /// Memory Restore Feature
+
+ IN BOOLEAN MemRestoreCtl; ///< Memory context restore control
+ ///< FALSE = perform memory init as normal (AMD default)
+ ///< TRUE = restore memory context and skip training. This requires
+ ///< MemContext is valid before AmdInitPost
+ ///<
+ IN BOOLEAN SaveMemContextCtl; ///< Control switch to save memory context at the end of MemAuto
+ ///< TRUE = AGESA will setup MemContext block before exit AmdInitPost
+ ///< FALSE = AGESA will not setup MemContext block. Platform is
+ ///< expected to call S3Save later in POST if it wants to
+ ///< use memory context restore feature.
+ ///<
+ IN OUT AMD_S3_PARAMS MemContext; ///< Memory context block describes the data that platform needs to
+ ///< save and restore for memory context restore feature to work.
+ ///< It uses the subset of S3Save block to save/restore. Hence platform
+ ///< may save only S3 block and uses it for both S3 resume and
+ ///< memory context restore.
+ ///< - If MemRestoreCtl is TRUE, platform needs to pass in MemContext
+ ///< before AmdInitPost.
+ ///< - If SaveMemContextCtl is TRUE, platform needs to save MemContext
+ ///< right after AmdInitPost.
+ ///<
+ IN BOOLEAN IsCapsuleMode; ///< Capsule reboot control
+ ///< FALSE = This is not a capsule reboot.
+ ///< TRUE = This is a capsule reboot.
+ ///<
+ IN BOOLEAN ExternalVrefCtl; ///< Control the use of external Vref
+ ///< TRUE = AGESA will use the function defined in "AGESA_EXTERNAL_VREF_CHANGE" in function list
+ ///< to change the vref
+ ///< FALSE = AGESA will will use the internal vref control.
+ ///< @BldCfgItem{BLDCFG_ENABLE_EXTERNAL_VREF_FEATURE}
+ ///<
+ IN FORCE_TRAIN_MODE ForceTrainMode; ///< Training Mode
+ ///< 0 = Force 1D Training for all configurations
+ ///< 1 = Force 2D Training for all configurations
+ ///< 2 = Auto - AGESA will control 1D or 2D
+ IN TECHNOLOGY_TYPE DimmTypeUsedInMixedConfig; ///< Select the preferred technology type that AGESA will enable
+ ///< when it is mixed with other technology types.
+ ///< DDR3_TECHNOLOGY = Use DDR3 DIMMs
+ ///< GDDR5_TECHNOLOGY = Use GDDR5 DIMMs
+ ///< UNSUPPORTED_TECHNOLOGY = Exit with fatal error when DDR3 and GDDR5 DIMMs
+ ///< are installed on the same system
+ ///< @BldCfgItem{BLDCFG_DIMM_TYPE_USED_IN_MIXED_CONFIG}
+ IN BOOLEAN AmpEnable; ///< AMP functionality control
+ ///< TRUE = Enable, platform BIOS requests to enable memory overclocking function, and AGESA
+ ///< detects if memory is capable of it
+ ///< FALSE = Disable, there is no request to enable memory overclocking function
+ ///<
+ IN BOOLEAN AmpWarningMsgEnable; ///< AMP warning messages control
+ ///< TRUE = Enable to log the warning messages of AMP
+ ///< FALSE = Disable
+ ///<
+ OUT AMP_STATUS AmpStatus; ///< AMP status allows platform BIOS to check which voltage or warning message it should
+ ///< use/apply.
+ ///<
+ ///< AmpVoltageValid :
+ ///< TRUE - AGESA does enable AMP function, so use AmpVoltage for voltage adjustment
+ ///< FALSE - AGESA does not enable AMP function, so use DDR3Voltage for voltage adjustment
+ ///<
+ ///< AmpSupportDetectedButNotEnabled :
+ ///< TRUE - Display warning message of "AMP support detected but not enabled"
+ ///< FALSE - No corresponding message should be displayed
+ ///<
+ ///< AmpSelectedButNotEnabled :
+ ///< TRUE - Display warning message of "AMP selected but not enabled"
+ ///< FALSE - No corresponding message should be displayed
+ ///<
+ ///< Note that both of warning message status reports are controlled by AmpWarningMsgEnable
+ ///<
+ OUT AMP_DIMM_VOLTAGE AmpVoltage; ///< AMP voltage which will be sent back to platform BIOS, and
+ ///< the value in AmpVoltage is valid only if AmpStatus is TRUE returned
+ IN BOOLEAN DataEyeEn; ///< Get 2D training data eye
+ ///< TRUE = Enable to get the 2D data eye
+ ///< FALSE = The 2D data eye is not enabled
+ ///< @BldCfgItem{BLDCFG_ENABLE_DATA_EYE}
+ IN BOOLEAN DramDoubleRefreshRate;///< Specify the average time between refresh requests to all DRAM devices.
+ ///< TRUE = 2x refresh rate.
+ ///< FALSE = 1x refresh rate.
+ ///< @BldCfgItem{BLDCFG_DRAM_DOUBLE_REFRESH_RATE}
+ IN PMU_TRAIN_MODE PmuTrainMode; ///< PMU Training Mode
+ ///< @BldCfgItem{BLDCFG_PMU_TRAINING_MODE}
+ ///< 0 = PMU 1D Training only for all configurations
+ ///< 1 = PMU 1D and 2D Training read only for all configurations
+ ///< 2 = PMU 1D and 2D Training for all configurations
+ ///< 3 = AGESA control type of training depend on configurations
+} MEM_PARAMETER_STRUCT;
+
+
+///
+/// Function definition.
+/// This data structure passes function pointers to the memory configuration code.
+/// The wrapper can use this structure with customized versions.
+///
+typedef struct _MEM_FUNCTION_STRUCT {
+
+ // PUBLIC required Internal functions
+
+ IN OUT BOOLEAN (*amdMemGetPsCfgU) ( VOID *pMemData); ///< Proc for Unbuffered DIMMs, platform specific
+ IN OUT BOOLEAN (*amdMemGetPsCfgR) (VOID *pMemData); ///< Proc for Registered DIMMs, platform specific
+
+ // PUBLIC optional functions
+
+ IN OUT VOID (*amdMemEccInit) (VOID *pMemData); ///< NB proc for ECC feature
+ IN OUT VOID (*amdMemChipSelectInterleaveInit) (VOID *pMemData); ///< NB proc for CS interleave feature
+ IN OUT VOID (*amdMemDctInterleavingInit) (VOID *pMemData); ///< NB proc for Channel interleave feature
+ IN OUT VOID (*amdMemMctInterleavingInit) (VOID *pMemData); ///< NB proc for Node interleave feature
+ IN OUT VOID (*amdMemParallelTraining) (VOID *pMemData); ///< NB proc for parallel training feature
+ IN OUT VOID (*amdMemEarlySampleSupport) (VOID *pMemData); ///< NB code for early sample support feature
+ IN OUT VOID (*amdMemMultiPartInitSupport) (VOID *pMemData); ///< NB code for 'multi-part'
+ IN OUT VOID (*amdMemOnlineSpareSupport) (VOID *pMemData); ///< NB code for On-Line Spare feature
+ IN OUT VOID (*amdMemUDimmInit) (VOID *pMemData); ///< NB code for UDIMMs
+ IN OUT VOID (*amdMemRDimmInit) (VOID *pMemData); ///< NB code for RDIMMs
+ IN OUT VOID (*amdMemLrDimmInit) (VOID *pMemData); ///< NB code for LRDIMMs
+ IN OUT UINT32 Reserved[100]; ///< Reserved for later function definition
+} MEM_FUNCTION_STRUCT;
+
+///
+/// Socket Structure
+///
+///
+typedef struct _MEM_SOCKET_STRUCT {
+ OUT VOID *ChannelPtr[MAX_CHANNELS_PER_SOCKET]; ///< Pointers to each channels training data
+
+ OUT VOID *TimingsPtr[MAX_CHANNELS_PER_SOCKET]; ///< Pointers to each channels timing data
+} MEM_SOCKET_STRUCT;
+
+///
+/// Contains all data relevant to Memory Initialization.
+///
+typedef struct _MEM_DATA_STRUCT {
+ IN AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header
+
+ IN MEM_PARAMETER_STRUCT *ParameterListPtr; ///< List of input Parameters
+
+ OUT MEM_FUNCTION_STRUCT FunctionList; ///< List of function Pointers
+
+ IN OUT AGESA_STATUS (*GetPlatformCfg[MAX_PLATFORM_TYPES]) (struct _MEM_DATA_STRUCT *MemData, UINT8 SocketID, CH_DEF_STRUCT *CurrentChannel); ///< look-up platform info
+
+ IN OUT BOOLEAN (*ErrorHandling)(struct _DIE_STRUCT *MCTPtr, UINT8 DCT, UINT16 ChipSelMask, AMD_CONFIG_PARAMS *StdHeader); ///< Error Handling
+
+
+ OUT MEM_SOCKET_STRUCT SocketList[MAX_SOCKETS_SUPPORTED]; ///< Socket list for memory code.
+ ///< SocketList is a shortcut for IBVs to retrieve training
+ ///< and timing data for each channel indexed by socket/channel,
+ ///< eliminating their need to parse die/dct/channel etc.
+ ///< It contains pointers to the populated data structures for
+ ///< each channel and skips the channel structures that are
+ ///< unpopulated. In the case of channels sharing the same DCT,
+ ///< the pTimings pointers will point to the same DCT Timing data.
+
+ OUT DIE_STRUCT *DiesPerSystem; ///< Pointed to an array of DIE_STRUCTs
+ OUT UINT8 DieCount; ///< Number of MCTs in the system.
+
+ IN SPD_DEF_STRUCT *SpdDataStructure; ///< Pointer to SPD Data structure
+
+ IN OUT struct _PLATFORM_CONFIGURATION *PlatFormConfig; ///< Platform profile/build option config structure
+
+ IN OUT BOOLEAN IsFlowControlSupported; ///< Indicates if flow control is supported
+
+ OUT UINT32 TscRate; ///< The rate at which the TSC increments in megahertz.
+ IN BOOLEAN PhyReceiverLowPower; ///< Force PHY receiver in low power.
+ ///< TRUE = PHY receiver low power
+ ///< FALSE = PHY receiver high power
+} MEM_DATA_STRUCT;
+
+///
+/// Uma Structure
+///
+///
+typedef struct _UMA_INFO {
+ OUT UINT64 UmaBase; ///< UmaBase[63:0] = Addr[63:0]
+ OUT UINT32 UmaSize; ///< UmaSize[31:0] = Addr[31:0]
+ OUT UINT32 UmaAttributes; ///< Indicate the attribute of Uma
+ OUT UINT8 UmaMode; ///< Indicate the mode of Uma
+ OUT UINT16 MemClock; ///< Indicate memory running speed in MHz
+ OUT UINT8 MemType; ///< Indicate the DRAM technology type that is being used
+ OUT UINT8 Reserved[2]; ///< Reserved for future usage
+} UMA_INFO;
+
+
+/// Bitfield for ID
+typedef struct {
+ OUT UINT16 SocketId:8; ///< Socket ID
+ OUT UINT16 ModuleId:8; ///< Module ID
+} ID_FIELD;
+///
+/// Union for ID of socket and module that will be passed out in call out
+///
+typedef union {
+ OUT ID_FIELD IdField; ///< Bitfield for ID
+ OUT UINT16 IdInformation; ///< ID information for call out
+} ID_INFO;
+
+// AGESA MEMORY ERRORS
+
+// AGESA_SUCCESS memory events
+#define MEM_EVENT_CAPSULE_IN_EFFECT 0x04013600ul ///< Capsule is in effect
+#define MEM_EVENT_CONTEXT_RESTORE_IN_EFFECT 0x04023600ul ///< Context restore is in effect
+
+// AGESA_ALERT Memory Errors
+#define MEM_ALERT_USER_TMG_MODE_OVERRULED 0x04010000ul ///< TIMING_MODE_SPECIFIC is requested but
+ ///< cannot be applied to current configurations.
+#define MEM_ALERT_ORG_MISMATCH_DIMM 0x04010100ul ///< DIMM organization miss-match
+#define MEM_ALERT_BK_INT_DIS 0x04010200ul ///< Bank interleaving disable for internal issue
+
+// AGESA_ERROR Memory Errors
+#define MEM_ERROR_NO_DQS_POS_RD_WINDOW 0x04010300ul ///< No DQS Position window for RD DQS
+#define MEM_ERROR_SMALL_DQS_POS_RD_WINDOW 0x04020300ul ///< Small DQS Position window for RD DQS
+#define MEM_ERROR_NO_DQS_POS_WR_WINDOW 0x04030300ul ///< No DQS Position window for WR DQS
+#define MEM_ERROR_SMALL_DQS_POS_WR_WINDOW 0x04040300ul ///< Small DQS Position window for WR DQS
+#define MEM_ERROR_DIMM_SPARING_NOT_ENABLED 0x04010500ul ///< DIMM sparing has not been enabled for an internal issues
+#define MEM_ERROR_RCVR_EN_VALUE_TOO_LARGE 0x04050300ul ///< Receive Enable value is too large
+#define MEM_ERROR_RCVR_EN_NO_PASSING_WINDOW 0x04060300ul ///< There is no DQS receiver enable window
+#define MEM_ERROR_DRAM_ENABLED_TIME_OUT 0x04010600ul ///< Time out when polling DramEnabled bit
+#define MEM_ERROR_DCT_ACCESS_DONE_TIME_OUT 0x04010700ul ///< Time out when polling DctAccessDone bit
+#define MEM_ERROR_SEND_CTRL_WORD_TIME_OUT 0x04010800ul ///< Time out when polling SendCtrlWord bit
+#define MEM_ERROR_PREF_DRAM_TRAIN_MODE_TIME_OUT 0x04010900ul ///< Time out when polling PrefDramTrainMode bit
+#define MEM_ERROR_ENTER_SELF_REF_TIME_OUT 0x04010A00ul ///< Time out when polling EnterSelfRef bit
+#define MEM_ERROR_FREQ_CHG_IN_PROG_TIME_OUT 0x04010B00ul ///< Time out when polling FreqChgInProg bit
+#define MEM_ERROR_EXIT_SELF_REF_TIME_OUT 0x04020A00ul ///< Time out when polling ExitSelfRef bit
+#define MEM_ERROR_SEND_MRS_CMD_TIME_OUT 0x04010C00ul ///< Time out when polling SendMrsCmd bit
+#define MEM_ERROR_SEND_ZQ_CMD_TIME_OUT 0x04010D00ul ///< Time out when polling SendZQCmd bit
+#define MEM_ERROR_DCT_EXTRA_ACCESS_DONE_TIME_OUT 0x04010E00ul ///< Time out when polling DctExtraAccessDone bit
+#define MEM_ERROR_MEM_CLR_BUSY_TIME_OUT 0x04010F00ul ///< Time out when polling MemClrBusy bit
+#define MEM_ERROR_MEM_CLEARED_TIME_OUT 0x04020F00ul ///< Time out when polling MemCleared bit
+#define MEM_ERROR_FLUSH_WR_TIME_OUT 0x04011000ul ///< Time out when polling FlushWr bit
+#define MEM_ERROR_NBPSTATE_TRANSITION_TIME_OUT 0x04012600ul ///< Time out when polling CurNBPstate bit
+#define MEM_ERROR_MAX_LAT_NO_WINDOW 0x04070300ul ///< Fail to find pass during Max Rd Latency training
+#define MEM_ERROR_PARALLEL_TRAINING_LAUNCH_FAIL 0x04080300ul ///< Fail to launch training code on an AP
+#define MEM_ERROR_PARALLEL_TRAINING_TIME_OUT 0x04090300ul ///< Fail to finish parallel training
+#define MEM_ERROR_NO_ADDRESS_MAPPING 0x04011100ul ///< No address mapping found for a dimm
+#define MEM_ERROR_RCVR_EN_NO_PASSING_WINDOW_EQUAL_LIMIT 0x040A0300ul ///< There is no DQS receiver enable window and the value is equal to the largest value
+#define MEM_ERROR_RCVR_EN_VALUE_TOO_LARGE_LIMIT_LESS_ONE 0x040B0300ul ///< Receive Enable value is too large and is 1 less than limit
+#define MEM_ERROR_CHECKSUM_NV_SPDCHK_RESTRT_ERROR 0x04011200ul ///< SPD Checksum error for NV_SPDCHK_RESTRT
+#define MEM_ERROR_NO_CHIPSELECT 0x04011300ul ///< No chipselects found
+#define MEM_ERROR_UNSUPPORTED_333MHZ_UDIMM 0x04011500ul ///< Unbuffered dimm is not supported at 333MHz
+#define MEM_ERROR_WL_PRE_OUT_OF_RANGE 0x040C0300ul ///< Returned PRE value during write levelizzation was out of range
+#define MEM_ERROR_NO_2D_RDDQS_WINDOW 0x040D0300ul ///< No 2D RdDqs Window
+#define MEM_ERROR_NO_2D_RDDQS_HEIGHT 0x040E0300ul ///< No 2D RdDqs Height
+#define MEM_ERROR_2D_DQS_ERROR 0x040F0300ul ///< 2d RdDqs Error
+#define MEM_ERROR_INVALID_2D_RDDQS_VALUE 0x04022400ul ///< 2d RdDqs invalid value found
+#define MEM_ERROR_2D_DQS_VREF_MARGIN_ERROR 0x04023400ul ///< 2d RdDqs Vef Margin error found
+#define MEM_ERROR_LR_IBT_NOT_FOUND 0x04013500ul ///< No LR dimm IBT value is found
+#define MEM_ERROR_MR0_NOT_FOUND 0x04023500ul ///< No MR0 value is found
+#define MEM_ERROR_ODT_PATTERN_NOT_FOUND 0x04033500ul ///< No odt pattern value is found
+#define MEM_ERROR_RC2_IBT_NOT_FOUND 0x04043500ul ///< No RC2 IBT value is found
+#define MEM_ERROR_RC10_OP_SPEED_NOT_FOUND 0x04053500ul ///< No RC10 op speed is found
+#define MEM_ERROR_RTT_NOT_FOUND 0x04063500ul ///< No RTT value is found
+#define MEM_ERROR_P2D_NOT_FOUND 0x04073500ul ///< No 2D training config value is found
+#define MEM_ERROR_SAO_NOT_FOUND 0x04083500ul ///< No slow access mode, Address timing and Output driver compensation value is found
+#define MEM_ERROR_CLK_DIS_MAP_NOT_FOUND 0x04093500ul ///< No CLK disable map is found
+#define MEM_ERROR_CKE_TRI_MAP_NOT_FOUND 0x040A3500ul ///< No CKE tristate map is found
+#define MEM_ERROR_ODT_TRI_MAP_NOT_FOUND 0x040B3500ul ///< No ODT tristate map is found
+#define MEM_ERROR_CS_TRI_MAP_NOT_FOUND 0x040C3500ul ///< No CS tristate map is found
+#define MEM_ERROR_TRAINING_SEED_NOT_FOUND 0x040D3500ul ///< No training seed is found
+#define MEM_ERROR_NO_2D_WRDAT_WINDOW 0x040D0400ul ///< No 2D WrDat Window
+#define MEM_ERROR_NO_2D_WRDAT_HEIGHT 0x040E0400ul ///< No 2D WrDat Height
+#define MEM_ERROR_2D_WRDAT_ERROR 0x040F0400ul ///< 2d WrDat Error
+#define MEM_ERROR_INVALID_2D_WRDAT_VALUE 0x04100400ul ///< 2d WrDat invalid value found
+#define MEM_ERROR_2D_WRDAT_VREF_MARGIN_ERROR 0x04110400ul ///< 2d WrDat Vef Margin error found
+#define MEM_ERROR_PMU_TRAINING 0x04120400ul ///< Fail PMU training.
+
+// AGESA_WARNING Memory Errors
+#define MEM_WARNING_UNSUPPORTED_QRDIMM 0x04011600ul ///< QR DIMMs detected but not supported
+#define MEM_WARNING_UNSUPPORTED_UDIMM 0x04021600ul ///< U DIMMs detected but not supported
+#define MEM_WARNING_UNSUPPORTED_SODIMM 0x04031600ul ///< SO-DIMMs detected but not supported
+#define MEM_WARNING_UNSUPPORTED_X4DIMM 0x04041600ul ///< x4 DIMMs detected but not supported
+#define MEM_WARNING_UNSUPPORTED_RDIMM 0x04051600ul ///< R DIMMs detected but not supported
+#define MEM_WARNING_UNSUPPORTED_LRDIMM 0x04061600ul ///< LR DIMMs detected but not supported
+#define MEM_WARNING_EMP_NOT_SUPPORTED 0x04011700ul ///< Processor is not capable for EMP
+#define MEM_WARNING_EMP_CONFLICT 0x04021700ul ///< EMP cannot be enabled if channel interleaving,
+#define MEM_WARNING_EMP_NOT_ENABLED 0x04031700ul ///< Memory size is not power of two.
+#define MEM_WARNING_ECC_DIS 0x04041700ul ///< ECC has been disabled as a result of an internal issue
+#define MEM_WARNING_PERFORMANCE_ENABLED_BATTERY_LIFE_PREFERRED 0x04011800ul ///< Performance has been enabled, but battery life is preferred.
+ ///< bank interleaving, or bank swizzle is enabled.
+#define MEM_WARNING_NO_SPDTRC_FOUND 0x04011900ul ///< No Trc timing value found in SPD of a dimm.
+#define MEM_WARNING_NODE_INTERLEAVING_NOT_ENABLED 0x04012000ul ///< Node Interleaveing Requested, but could not be enabled
+#define MEM_WARNING_CHANNEL_INTERLEAVING_NOT_ENABLED 0x04012100ul ///< Channel Interleaveing Requested, but could not be enabled
+#define MEM_WARNING_BANK_INTERLEAVING_NOT_ENABLED 0x04012200ul ///< Bank Interleaveing Requested, but could not be enabled
+#define MEM_WARNING_VOLTAGE_1_35_NOT_SUPPORTED 0x04012300ul ///< Voltage 1.35 determined, but could not be supported
+#define MEM_WARNING_INITIAL_DDR3VOLT_NONZERO 0x04012400ul ///< DDR3 voltage initial value is not 0
+#define MEM_WARNING_NO_COMMONLY_SUPPORTED_VDDIO 0x04012500ul ///< Cannot find a commonly supported VDDIO
+#define MEM_WARNING_AMP_SUPPORT_DETECTED_BUT_NOT_ENABLED 0x04012900ul ///< AMP support detected but not enabled
+#define MEM_WARNING_AMP_SELECTED_BUT_NOT_ENABLED 0x04022900ul ///< AMP selected but not enabled
+
+// AGESA_FATAL Memory Errors
+#define MEM_ERROR_MINIMUM_MODE 0x04011A00ul ///< Running in minimum mode
+#define MEM_ERROR_MODULE_TYPE_MISMATCH_DIMM 0x04011B00ul ///< DIMM modules are miss-matched
+#define MEM_ERROR_NO_DIMM_FOUND_ON_SYSTEM 0x04011C00ul ///< No DIMMs have been found
+#define MEM_ERROR_MISMATCH_DIMM_CLOCKS 0x04011D00ul ///< DIMM clocks miss-matched
+#define MEM_ERROR_NO_CYC_TIME 0x04011E00ul ///< No cycle time found
+#define MEM_ERROR_HEAP_ALLOCATE_DYN_STORING_OF_TRAINED_TIMINGS 0x04011F00ul ///< Heap allocation error with dynamic storing of trained timings
+#define MEM_ERROR_HEAP_ALLOCATE_FOR_DCT_STRUCT_AND_CH_DEF_STRUCTs 0x04021F00ul ///< Heap allocation error for DCT_STRUCT and CH_DEF_STRUCT
+#define MEM_ERROR_HEAP_ALLOCATE_FOR_REMOTE_TRAINING_ENV 0x04031F00ul ///< Heap allocation error with REMOTE_TRAINING_ENV
+#define MEM_ERROR_HEAP_ALLOCATE_FOR_SPD 0x04041F00ul ///< Heap allocation error for SPD data
+#define MEM_ERROR_HEAP_ALLOCATE_FOR_RECEIVED_DATA 0x04051F00ul ///< Heap allocation error for RECEIVED_DATA during parallel training
+#define MEM_ERROR_HEAP_ALLOCATE_FOR_S3_SPECIAL_CASE_REGISTERS 0x04061F00ul ///< Heap allocation error for S3 "SPECIAL_CASE_REGISTER"
+#define MEM_ERROR_HEAP_ALLOCATE_FOR_TRAINING_DATA 0x04071F00ul ///< Heap allocation error for Training Data
+#define MEM_ERROR_HEAP_ALLOCATE_FOR_IDENTIFY_DIMM_MEM_NB_BLOCK 0x04081F00ul ///< Heap allocation error for DIMM Identify "MEM_NB_BLOCK
+#define MEM_ERROR_NO_CONSTRUCTOR_FOR_IDENTIFY_DIMM 0x04022300ul ///< No Constructor for DIMM Identify
+#define MEM_ERROR_VDDIO_UNSUPPORTED 0x04022500ul ///< VDDIO of the dimms on the board is not supported
+#define MEM_ERROR_HEAP_ALLOCATE_FOR_2D 0x040B1F00ul ///< Heap allocation error for 2D training data
+#define MEM_ERROR_HEAP_DEALLOCATE_FOR_2D 0x040C1F00ul ///< Heap de-allocation error for 2D training data
+#define MEM_ERROR_HEAP_ALLOCATE_FOR_DATAEYE 0x040F1F00ul ///< Heap allocation error for DATAEYE Storage
+#define MEM_ERROR_HEAP_DEALLOCATE_FOR_DATAEYE 0x040E1F00ul ///< Heap de-allocation error for DATAEYE Storage
+#define MEM_ERROR_HEAP_ALLOCATE_FOR_PMU_SRAM_MSG_BLOCK 0x04101F00ul ///< Heap allocation error for PMU SRAM Message Block Storage
+#define MEM_ERROR_HEAP_DEALLOCATE_FOR_PMU_SRAM_MSG_BLOCK 0x04111F00ul ///< Heap de-allocation error for PMU SRAM Message Block Storage
+#define MEM_ERROR_HEAP_LOCATE_FOR_PMU_SRAM_MSG_BLOCK 0x04121F00ul ///< Heap location error for PMU SRAM Message Block Storage
+
+// AGESA_CRITICAL Memory Errors
+#define MEM_ERROR_HEAP_ALLOCATE_FOR_DMI_TABLE_DDR3 0x04091F00ul ///< Heap allocation error for DMI table for DDR3
+#define MEM_ERROR_HEAP_ALLOCATE_FOR_DMI_TABLE_DDR2 0x040A1F00ul ///< Heap allocation error for DMI table for DDR2
+#define MEM_ERROR_UNSUPPORTED_DIMM_CONFIG 0x04011400ul ///< Dimm population is not supported
+#define MEM_ERROR_HEAP_ALLOCATE_FOR_CRAT_MEM_AFFINITY 0x040D1F00ul ///< Heap allocation error for CRAT memory affinity info
+
+
+
+/*----------------------------------------------------------------------------
+ *
+ * END OF MEMORY-SPECIFIC DATA STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+
+/*----------------------------------------------------------------------------
+ *
+ * CPU RELATED DEFINITIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+// CPU Event definitions.
+
+// Defines used to filter CPU events based on functional blocks
+#define CPU_EVENT_PM_EVENT_MASK 0xFF00FF00ul
+#define CPU_EVENT_PM_EVENT_CLASS 0x08000400ul
+
+//================================================================
+// CPU General events
+// Heap allocation (AppFunction = 01h)
+#define CPU_ERROR_HEAP_BUFFER_IS_NOT_PRESENT 0x08000100ul
+#define CPU_ERROR_HEAP_IS_ALREADY_INITIALIZED 0x08010100ul
+#define CPU_ERROR_HEAP_IS_FULL 0x08020100ul
+#define CPU_ERROR_HEAP_BUFFER_HANDLE_IS_ALREADY_USED 0x08030100ul
+#define CPU_ERROR_HEAP_BUFFER_HANDLE_IS_NOT_PRESENT 0x08040100ul
+// BrandId (AppFunction = 02h)
+#define CPU_ERROR_BRANDID_HEAP_NOT_AVAILABLE 0x08000200ul
+// Micro code patch (AppFunction = 03h)
+#define CPU_ERROR_MICRO_CODE_PATCH_IS_NOT_LOADED 0x08000300ul
+// Power management (AppFunction = 04h)
+#define CPU_EVENT_PM_PSTATE_OVERCURRENT 0x08000400ul
+#define CPU_EVENT_PM_ALL_PSTATE_OVERCURRENT 0x08010400ul
+#define CPU_ERROR_PSTATE_HEAP_NOT_AVAILABLE 0x08020400ul
+#define CPU_ERROR_PM_NB_PSTATE_MISMATCH 0x08030400ul
+#define CPU_ERROR_PM_ALL_PSTATE_OVER_FREQUENCY_LIMIT 0x08040400ul
+#define CPU_EVENT_PM_PSTATE_FREQUENCY_LIMIT 0x08050400ul
+// Other CPU events (AppFunction = 05h)
+#define CPU_EVENT_BIST_ERROR 0x08000500ul
+#define CPU_EVENT_UNKNOWN_PROCESSOR_FAMILY 0x08010500ul
+#define CPU_EVENT_STACK_REENTRY 0x08020500ul
+#define CPU_EVENT_CORE_NOT_IDENTIFIED 0x08030500ul
+
+//=================================================================
+// CPU Feature events
+// Execution cache (AppFunction = 21h)
+// AGESA_CACHE_SIZE_REDUCED 2101
+// AGESA_CACHE_REGIONS_ACROSS_1MB 2102
+// AGESA_CACHE_REGIONS_ACROSS_4GB 2103
+// AGESA_REGION_NOT_ALIGNED_ON_BOUNDARY 2104
+// AGESA_CACHE_START_ADDRESS_LESS_D0000 2105
+// AGESA_THREE_CACHE_REGIONS_ABOVE_1MB 2106
+// AGESA_DEALLOCATE_CACHE_REGIONS 2107
+#define CPU_EVENT_EXECUTION_CACHE_ALLOCATION_ERROR 0x08002100ul
+// Core Leveling (AppFunction = 22h)
+#define CPU_WARNING_ADJUSTED_LEVELING_MODE 0x08002200ul
+// SCS initialization (AppFunction = 24h)
+// AGESA_SCS_HEAP_ENTRY_MISSING 2401
+// AGESA_SCS_BUFFER_EMPTY 2402
+// AGESA_SCS_WEIGHTS_MISMATCH 2403
+#define CPU_EVENT_SCS_INITIALIZATION_ERROR 0x08002400ul
+
+// CPU Build Configuration structures and definitions
+
+/// Build Configuration structure for BLDCFG_AP_MTRR_SETTINGS
+typedef struct {
+ IN UINT32 MsrAddr; ///< Fixed-Sized MTRR address
+ IN UINT64 MsrData; ///< MTRR Settings
+} AP_MTRR_SETTINGS;
+
+#define AMD_AP_MTRR_FIX64k_00000 0x00000250ul
+#define AMD_AP_MTRR_FIX16k_80000 0x00000258ul
+#define AMD_AP_MTRR_FIX16k_A0000 0x00000259ul
+#define AMD_AP_MTRR_FIX4k_C0000 0x00000268ul
+#define AMD_AP_MTRR_FIX4k_C8000 0x00000269ul
+#define AMD_AP_MTRR_FIX4k_D0000 0x0000026Aul
+#define AMD_AP_MTRR_FIX4k_D8000 0x0000026Bul
+#define AMD_AP_MTRR_FIX4k_E0000 0x0000026Cul
+#define AMD_AP_MTRR_FIX4k_E8000 0x0000026Dul
+#define AMD_AP_MTRR_FIX4k_F0000 0x0000026Eul
+#define AMD_AP_MTRR_FIX4k_F8000 0x0000026Ful
+#define CPU_LIST_TERMINAL 0xFFFFFFFFul
+
+/// Data structure for the Mapping Item between Unified ID for IDS Setup Option
+/// and the option value.
+///
+typedef struct {
+ IN UINT16 IdsNvId; ///< Unified ID for IDS Setup Option.
+ OUT UINT16 IdsNvValue; ///< The value of IDS Setup Option.
+} IDS_NV_ITEM;
+
+/// Data Structure for IDS CallOut Function
+typedef struct {
+ IN AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header
+ IN IDS_NV_ITEM *IdsNvPtr; ///< Memory Pointer of IDS NV Table
+ IN OUT UINTN Reserved; ///< reserved
+} IDS_CALLOUT_STRUCT;
+
+/************************************************************************
+ *
+ * AGESA interface Call-Out function parameter structures
+ *
+ ***********************************************************************/
+
+/// Parameters structure for interface call-out AgesaAllocateBuffer
+typedef struct {
+ IN OUT AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header
+ IN OUT UINT32 BufferLength; ///< Size of buffer to allocate
+ IN UINT32 BufferHandle; ///< Identifier or name for the buffer
+ OUT VOID *BufferPointer; ///< location of the created buffer
+} AGESA_BUFFER_PARAMS;
+
+/// Parameters structure for interface call-out AgesaHeapRebase
+typedef struct {
+ IN OUT AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header
+ OUT UINTN HeapAddress; ///< The address which heap content will be temporarily stored in
+} AGESA_REBASE_PARAMS;
+
+/// Parameters structure for interface call-out AgesaRunCodeOnAp
+typedef struct {
+ IN OUT AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header
+ IN UINT32 FunctionNumber; ///< Index of the procedure to execute
+ IN VOID *RelatedDataBlock; ///< Location of data structure the procedure will use
+ IN UINT32 RelatedBlockLength; ///< Size of the related data block
+} AP_EXE_PARAMS;
+
+/// Parameters structure for the interface call-out AgesaReadSpd & AgesaReadSpdRecovery
+typedef struct {
+ IN OUT AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header
+ IN UINT8 SocketId; ///< Address of SPD - socket ID
+ IN UINT8 MemChannelId; ///< Address of SPD - memory channel ID
+ IN UINT8 DimmId; ///< Address of SPD - DIMM ID
+ IN OUT UINT8 *Buffer; ///< Location where to place the SPD content
+ IN OUT MEM_DATA_STRUCT *MemData; ///< Location of the MemData structure, for reference
+} AGESA_READ_SPD_PARAMS;
+
+/// VoltageType values
+typedef enum {
+ VTYPE_CPU_VREF, ///< Cpu side Vref
+ VTYPE_DIMM_VREF, ///< Dimm Side Vref
+ VTYPE_VDDIO ///< Vddio
+} VTYPE;
+
+/// Parameters structure for the interface call-out AgesaExternalVoltageAdjust
+typedef struct _VOLTAGE_ADJUST {
+ IN OUT AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header
+ IN OUT MEM_DATA_STRUCT *MemData; ///< Location of the MemData structure, for reference
+ IN VTYPE VoltageType; ///< Which Voltage Type to adjust
+ IN INT8 AdjustValue; ///< Positive/Negative Adjust Value
+} VOLTAGE_ADJUST;
+
+/// Buffer Handles
+typedef enum {
+ AMD_DMI_INFO_BUFFER_HANDLE = 0x000D000, ///< Assign 0x000D000 buffer handle to DMI function
+ AMD_PSTATE_DATA_BUFFER_HANDLE, ///< Assign 0x000D001 buffer handle to Pstate data
+ AMD_PSTATE_ACPI_BUFFER_HANDLE, ///< Assign 0x000D002 buffer handle to Pstate table
+ AMD_BRAND_ID_BUFFER_HANDLE, ///< Assign 0x000D003 buffer handle to Brand ID
+ AMD_ACPI_SLIT_BUFFER_HANDLE, ///< Assign 0x000D004 buffer handle to SLIT function
+ AMD_SRAT_INFO_BUFFER_HANDLE, ///< Assign 0x000D005 buffer handle to SRAT function
+ AMD_WHEA_BUFFER_HANDLE, ///< Assign 0x000D006 buffer handle to WHEA function
+ AMD_S3_INFO_BUFFER_HANDLE, ///< Assign 0x000D007 buffer handle to S3 function
+ AMD_S3_NB_INFO_BUFFER_HANDLE, ///< Assign 0x000D008 buffer handle to S3 NB device info
+ AMD_ACPI_ALIB_BUFFER_HANDLE, ///< Assign 0x000D009 buffer handle to ALIB SSDT table
+ AMD_ACPI_IVRS_BUFFER_HANDLE, ///< Assign 0x000D00A buffer handle to IOMMU IVRS table
+ AMD_CRAT_INFO_BUFFER_HANDLE, ///< Assign 0x000D00B buffer handle to CRAT function
+ AMD_ACPI_CDIT_BUFFER_HANDLE ///< Assign 0x000D00C buffer handle to CDIT function
+} AMD_BUFFER_HANDLE;
+
+
+/************************************************************************
+ *
+ * AGESA interface Call-Out function prototypes
+ *
+ ***********************************************************************/
+
+VOID
+AgesaDoReset (
+ IN UINTN ResetType,
+ IN OUT AMD_CONFIG_PARAMS *StdHeader
+ );
+
+AGESA_STATUS
+AgesaAllocateBuffer (
+ IN UINTN FcnData,
+ IN OUT AGESA_BUFFER_PARAMS *AllocParams
+ );
+
+AGESA_STATUS
+AgesaDeallocateBuffer (
+ IN UINTN FcnData,
+ IN OUT AGESA_BUFFER_PARAMS *DeallocParams
+ );
+
+AGESA_STATUS
+AgesaLocateBuffer (
+ IN UINTN FcnData,
+ IN OUT AGESA_BUFFER_PARAMS *LocateParams
+ );
+
+AGESA_STATUS
+AgesaHeapRebase (
+ IN UINTN FcnData,
+ IN OUT AGESA_REBASE_PARAMS *RebaseParams
+ );
+
+AGESA_STATUS
+AgesaReadSpd (
+ IN UINTN FcnData,
+ IN OUT AGESA_READ_SPD_PARAMS *ReadSpd
+ );
+
+AGESA_STATUS
+AgesaReadSpdRecovery (
+ IN UINTN FcnData,
+ IN OUT AGESA_READ_SPD_PARAMS *ReadSpd
+ );
+
+AGESA_STATUS
+AgesaHookBeforeDramInitRecovery (
+ IN UINTN FcnData,
+ IN OUT MEM_DATA_STRUCT *MemData
+ );
+
+AGESA_STATUS
+AgesaRunFcnOnAp (
+ IN UINTN ApicIdOfCore,
+ IN AP_EXE_PARAMS *LaunchApParams
+ );
+
+AGESA_STATUS
+AgesaHookBeforeDramInit (
+ IN UINTN SocketIdModuleId,
+ IN OUT MEM_DATA_STRUCT *MemData
+ );
+
+AGESA_STATUS
+AgesaHookBeforeDQSTraining (
+ IN UINTN SocketIdModuleId,
+ IN OUT MEM_DATA_STRUCT *MemData
+ );
+
+AGESA_STATUS
+AgesaHookBeforeExitSelfRefresh (
+ IN UINTN FcnData,
+ IN OUT MEM_DATA_STRUCT *MemData
+ );
+
+AGESA_STATUS
+AgesaPcieSlotResetControl (
+ IN UINTN FcnData,
+ IN PCIe_SLOT_RESET_INFO *ResetInfo
+ );
+
+AGESA_STATUS
+AgesaGetVbiosImage (
+ IN UINTN FcnData,
+ IN OUT GFX_VBIOS_IMAGE_INFO *VbiosImageInfo
+ );
+
+AGESA_STATUS
+AgesaFchOemCallout (
+ IN VOID *FchData
+ );
+
+AGESA_STATUS
+AgesaExternal2dTrainVrefChange (
+ IN UINTN SocketIdModuleId,
+ IN OUT MEM_DATA_STRUCT *MemData
+ );
+
+AGESA_STATUS
+AgesaGetIdsData (
+ IN UINTN Data,
+ IN OUT IDS_CALLOUT_STRUCT *IdsCalloutData
+ );
+
+AGESA_STATUS
+AgesaExternalVoltageAdjust (
+ IN UINTN SocketIdModuleId,
+ IN OUT VOLTAGE_ADJUST *AdjustValue
+ );
+
+AGESA_STATUS
+AgesaGnbOemCallout (
+ IN AMD_CONFIG_PARAMS *StdHeader,
+ IN UINTN FcnData,
+ IN OUT VOID *GnbCalloutData
+ );
+
+/************************************************************************
+ *
+ * AGESA interface structure definition and function prototypes
+ *
+ ***********************************************************************/
+
+/**********************************************************************
+ * Platform Configuration: The parameters in boot branch function
+ **********************************************************************/
+
+/// The possible platform control flow settings.
+typedef enum {
+ Nfcm, ///< Normal Flow Control Mode.
+ UmaDr, ///< UMA using Display Refresh flow control.
+ UmaIfcm, ///< UMA using Isochronous Flow Control.
+ Ifcm, ///< Isochronous Flow Control Mode (other than for UMA).
+ Iommu, ///< An IOMMU is in use in the system.
+ MaxControlFlow ///< Not a control flow mode, use for limit checking.
+} PLATFORM_CONTROL_FLOW;
+
+/// The possible hardware prefetch mode settings.
+typedef enum {
+ HARDWARE_PREFETCHER_AUTO, ///< Use the recommended setting for the processor. In most cases, the recommended setting is enabled.
+ DISABLE_HW_PREFETCHER_TRAINING_ON_SOFTWARE_PREFETCHES, ///< Use the recommended setting for the hardware prefetcher, but disable training on software prefetches.
+ DISABLE_L1_PREFETCHER, ///< Use the recommended settings for the hardware prefetcher, but disable L1 prefetching and above.
+ DISABLE_L1_PREFETCHER_AND_HW_PREFETCHER_TRAINING_ON_SOFTWARE_PREFETCHES, ///< (deprecated) - This setting is deprecated; it has the same effect as DISABLE_L1_PREFETCHER
+ DISABLE_L2_STRIDE_PREFETCHER, ///< Use the recommended settings for the hardware prefetcher, but disable the L2 stride prefetcher and above
+ DISABLE_HARDWARE_PREFETCH, ///< Disable hardware prefetching.
+ MAX_HARDWARE_PREFETCH_MODE ///< Not a hardware prefetch mode, use for limit checking.
+} HARDWARE_PREFETCH_MODE;
+
+/// The possible software prefetch mode settings.
+typedef enum {
+ SOFTWARE_PREFETCHES_AUTO, ///< Use the recommended setting for the processor. In most cases, the recommended setting is enabled.
+ DISABLE_SOFTWARE_PREFETCHES, ///< Disable software prefetches (convert software prefetch instructions to NOP).
+ MAX_SOFTWARE_PREFETCH_MODE ///< Not a software prefetch mode, use for limit checking.
+} SOFTWARE_PREFETCH_MODE;
+
+/// Advanced performance tunings, prefetchers.
+/// These settings provide for performance tuning to optimize for specific workloads.
+typedef struct {
+ IN HARDWARE_PREFETCH_MODE HardwarePrefetchMode; ///< This value provides for advanced performance tuning by controlling the hardware prefetcher setting.
+ IN SOFTWARE_PREFETCH_MODE SoftwarePrefetchMode; ///< This value provides for advanced performance tuning by controlling the software prefetch instructions.
+ IN DRAM_PREFETCH_MODE DramPrefetchMode; ///< This value provides for advanced performance tuning by controlling the DRAM prefetcher setting.
+} ADVANCED_PERFORMANCE_PROFILE;
+
+/// The possible platform power policy settings.
+typedef enum {
+ Performance, ///< Optimize for performance.
+ BatteryLife, ///< Optimize for battery life.
+ Auto, ///< Auto
+ MaxPowerPolicy ///< Not a power policy mode, use for limit checking.
+} PLATFORM_POWER_POLICY;
+
+/// Platform performance settings for optimized settings.
+/// Several configuration settings for the processor depend upon other parts and
+/// general designer choices for the system. The determination of these data points
+/// is not standard for all platforms, so the host environment needs to provide these
+/// to specify how the system is to be configured.
+typedef struct {
+ IN PLATFORM_CONTROL_FLOW PlatformControlFlowMode; ///< The platform's control flow mode for optimum platform performance.
+ ///< @BldCfgItem{BLDCFG_PLATFORM_CONTROL_FLOW_MODE}
+ IN BOOLEAN Use32ByteRefresh; ///< Display Refresh traffic generates 32 byte requests.
+ ///< @BldCfgItem{BLDCFG_USE_32_BYTE_REFRESH}
+ IN BOOLEAN UseVariableMctIsocPriority; ///< The Memory controller will be set to Variable Isoc Priority.
+ ///< @BldCfgItem{BLDCFG_USE_VARIABLE_MCT_ISOC_PRIORITY}
+ IN ADVANCED_PERFORMANCE_PROFILE AdvancedPerformanceProfile; ///< The advanced platform performance settings.
+ IN PLATFORM_POWER_POLICY PlatformPowerPolicy; ///< The platform's desired power policy
+ ///< @BldCfgItem{BLDCFG_PLATFORM_POWER_POLICY_MODE}
+ IN BOOLEAN NbPstatesSupported; ///< The Nb-Pstates is supported or not
+ ///< @BldCfgItem{BLDCFG_NB_PSTATES_SUPPORTED}
+} PERFORMANCE_PROFILE;
+
+/// Platform settings that describe the voltage regulator modules of the system.
+/// Many power management settings are dependent upon the characteristics of the
+/// on-board voltage regulator module (VRM). The host environment needs to provide
+/// these to specify how the system is to be configured.
+typedef struct {
+ IN UINT32 CurrentLimit; ///< Vrm Current Limit.
+ ///< @BldCfgItem{BLDCFG_VRM_CURRENT_LIMIT}
+ ///< @BldCfgItem{BLDCFG_VRM_NB_CURRENT_LIMIT}
+ IN UINT32 LowPowerThreshold; ///< Vrm Low Power Threshold.
+ ///< @BldCfgItem{BLDCFG_VRM_LOW_POWER_THRESHOLD}
+ ///< @BldCfgItem{BLDCFG_VRM_NB_LOW_POWER_THRESHOLD}
+ IN UINT32 SlewRate; ///< Vrm Slew Rate.
+ ///< @BldCfgItem{BLDCFG_VRM_SLEW_RATE}
+ ///< @BldCfgItem{BLDCFG_VRM_NB_SLEW_RATE}
+ IN BOOLEAN HiSpeedEnable; ///< Select high speed VRM.
+ ///< @BldCfgItem{BLDCFG_VRM_HIGH_SPEED_ENABLE}
+ ///< @BldCfgItem{BLDCFG_VRM_NB_HIGH_SPEED_ENABLE}
+ IN UINT32 MaximumCurrentLimit; ///< Vrm Maximum Current Limit.
+ ///< @BldCfgItem{BLDCFG_VRM_MAXIMUM_CURRENT_LIMIT}
+ ///< @BldCfgItem{BLDCFG_VRM_NB_MAXIMUM_CURRENT_LIMIT}
+ IN UINT32 SviOcpLevel; ///< SVI OCP Level.
+ ///< @BldCfgItem{BLDCFG_VRM_SVI_OCP_LEVEL}
+ ///< @BldCfgItem{BLDCFG_VRM_NB_SVI_OCP_LEVEL}
+} PLATFORM_VRM_CONFIGURATION;
+
+/// The VRM types to characterize.
+typedef enum {
+ CoreVrm, ///< VDD plane.
+ NbVrm, ///< VDDNB plane.
+ MaxVrmType ///< Not a valid VRM type, use for limit checking.
+} PLATFORM_VRM_TYPE;
+
+
+/// FCH Platform Configuration Policy
+typedef struct {
+ IN UINT16 CfgSmbus0BaseAddress; ///< SMBUS0 Controller Base Address
+ IN UINT16 CfgSmbus1BaseAddress; ///< SMBUS1 Controller Base Address
+ IN UINT16 CfgSioPmeBaseAddress; ///< I/O base address for LPC I/O target range
+ IN UINT16 CfgAcpiPm1EvtBlkAddr; ///< I/O base address of ACPI power management Event Block
+ IN UINT16 CfgAcpiPm1CntBlkAddr; ///< I/O base address of ACPI power management Control Block
+ IN UINT16 CfgAcpiPmTmrBlkAddr; ///< I/O base address of ACPI power management Timer Block
+ IN UINT16 CfgCpuControlBlkAddr; ///< I/O base address of ACPI power management CPU Control Block
+ IN UINT16 CfgAcpiGpe0BlkAddr; ///< I/O base address of ACPI power management General Purpose Event Block
+ IN UINT16 CfgSmiCmdPortAddr; ///< I/O base address of ACPI SMI Command Block
+ IN UINT16 CfgAcpiPmaCntBlkAddr; ///< I/O base address of ACPI power management additional control block
+ IN UINT32 CfgGecShadowRomBase; ///< 32-bit base address to the GEC shadow ROM
+ IN UINT32 CfgWatchDogTimerBase; ///< Watchdog Timer base address
+ IN UINT32 CfgSpiRomBaseAddress; ///< Base address for the SPI ROM controller
+ IN UINT32 CfgHpetBaseAddress; ///< HPET MMIO base address
+ IN UINT32 CfgAzaliaSsid; ///< Subsystem ID of HD Audio controller
+ IN UINT32 CfgSmbusSsid; ///< Subsystem ID of SMBUS controller
+ IN UINT32 CfgIdeSsid; ///< Subsystem ID of IDE controller
+ IN UINT32 CfgSataAhciSsid; ///< Subsystem ID of SATA controller in AHCI mode
+ IN UINT32 CfgSataIdeSsid; ///< Subsystem ID of SATA controller in IDE mode
+ IN UINT32 CfgSataRaid5Ssid; ///< Subsystem ID of SATA controller in RAID5 mode
+ IN UINT32 CfgSataRaidSsid; ///< Subsystem ID of SATA controller in RAID mode
+ IN UINT32 CfgEhciSsid; ///< Subsystem ID of EHCI
+ IN UINT32 CfgOhciSsid; ///< Subsystem ID of OHCI
+ IN UINT32 CfgLpcSsid; ///< Subsystem ID of LPC ISA Bridge
+ IN UINT32 CfgSdSsid; ///< Subsystem ID of SecureDigital controller
+ IN UINT32 CfgXhciSsid; ///< Subsystem ID of XHCI
+ IN BOOLEAN CfgFchPort80BehindPcib; ///< Is port80 cycle going to the PCI bridge
+ IN BOOLEAN CfgFchEnableAcpiSleepTrap; ///< ACPI sleep SMI enable/disable
+ IN GPP_LINKMODE CfgFchGppLinkConfig; ///< GPP link configuration
+ IN BOOLEAN CfgFchGppPort0Present; ///< Is FCH GPP port 0 present
+ IN BOOLEAN CfgFchGppPort1Present; ///< Is FCH GPP port 1 present
+ IN BOOLEAN CfgFchGppPort2Present; ///< Is FCH GPP port 2 present
+ IN BOOLEAN CfgFchGppPort3Present; ///< Is FCH GPP port 3 present
+ IN BOOLEAN CfgFchGppPort0HotPlug; ///< Is FCH GPP port 0 hotplug capable
+ IN BOOLEAN CfgFchGppPort1HotPlug; ///< Is FCH GPP port 1 hotplug capable
+ IN BOOLEAN CfgFchGppPort2HotPlug; ///< Is FCH GPP port 2 hotplug capable
+ IN BOOLEAN CfgFchGppPort3HotPlug; ///< Is FCH GPP port 3 hotplug capable
+
+ IN UINT8 CfgFchEsataPortBitMap; ///< ESATA Port definition, eg: [0]=1, means port 0 is ESATA capable
+ IN UINT8 CfgFchIrPinControl; ///< Register bitfield describing Infrared Pin Control:
+ ///< [0] - IR Enable 0
+ ///< [1] - IR Enable 1
+ ///< [2] - IR Tx0
+ ///< [3] - IR Tx1
+ ///< [4] - IR Open Drain
+ ///< [5] - IR Enable LED
+ IN SD_CLOCK_CONTROL CfgFchSdClockControl; ///< FCH SD Clock Control
+ IN SCI_MAP_CONTROL *CfgFchSciMapControl; ///< FCH SCI Mapping Control
+ IN SATA_PHY_CONTROL *CfgFchSataPhyControl; ///< FCH SATA PHY Control
+ IN GPIO_CONTROL *CfgFchGpioControl; ///< FCH GPIO Control
+ IN BOOLEAN CfgFchRtcWorkAround; ///< FCH RTC Workaround
+ IN BOOLEAN CfgFchUsbPortDisWorkAround; ///< FCH USB Workaround
+} FCH_PLATFORM_POLICY;
+
+
+/// Build Option/Configuration Boolean Structure.
+typedef struct {
+ IN AMD_CODE_HEADER VersionString; ///< AMD embedded code version string
+
+ //Build Option Area
+ IN BOOLEAN OptionUDimms; ///< @ref BLDOPT_REMOVE_UDIMMS_SUPPORT "BLDOPT_REMOVE_UDIMMS_SUPPORT"
+ IN BOOLEAN OptionRDimms; ///< @ref BLDOPT_REMOVE_RDIMMS_SUPPORT "BLDOPT_REMOVE_RDIMMS_SUPPORT"
+ IN BOOLEAN OptionLrDimms; ///< @ref BLDOPT_REMOVE_LRDIMMS_SUPPORT "BLDOPT_REMOVE_LRDIMMS_SUPPORT"
+ IN BOOLEAN OptionEcc; ///< @ref BLDOPT_REMOVE_ECC_SUPPORT "BLDOPT_REMOVE_ECC_SUPPORT"
+ IN BOOLEAN OptionBankInterleave; ///< @ref BLDOPT_REMOVE_BANK_INTERLEAVE "BLDOPT_REMOVE_BANK_INTERLEAVE"
+ IN BOOLEAN OptionDctInterleave; ///< @ref BLDOPT_REMOVE_DCT_INTERLEAVE "BLDOPT_REMOVE_DCT_INTERLEAVE"
+ IN BOOLEAN OptionNodeInterleave; ///< @ref BLDOPT_REMOVE_NODE_INTERLEAVE "BLDOPT_REMOVE_NODE_INTERLEAVE"
+ IN BOOLEAN OptionParallelTraining; ///< @ref BLDOPT_REMOVE_PARALLEL_TRAINING "BLDOPT_REMOVE_PARALLEL_TRAINING"
+ IN BOOLEAN OptionOnlineSpare; ///< @ref BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT "BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT"
+ IN BOOLEAN OptionMemRestore; ///< @ref BLDOPT_REMOVE_MEM_RESTORE_SUPPORT "BLDOPT_REMOVE_MEM_RESTORE_SUPPORT"
+ IN BOOLEAN OptionMultisocket; ///< @ref BLDOPT_REMOVE_MULTISOCKET_SUPPORT "BLDOPT_REMOVE_MULTISOCKET_SUPPORT"
+ IN BOOLEAN OptionAcpiPstates; ///< @ref BLDOPT_REMOVE_ACPI_PSTATES "BLDOPT_REMOVE_ACPI_PSTATES"
+ IN BOOLEAN OptionCrat; ///< @ref BLDOPT_REMOVE_CRAT "BLDOPT_REMOVE_CRAT"
+ IN BOOLEAN OptionCdit; ///< @ref BLDOPT_REMOVE_CDIT "BLDOPT_REMOVE_CDIT"
+ IN BOOLEAN OptionSrat; ///< @ref BLDOPT_REMOVE_SRAT "BLDOPT_REMOVE_SRAT"
+ IN BOOLEAN OptionSlit; ///< @ref BLDOPT_REMOVE_SLIT "BLDOPT_REMOVE_SLIT"
+ IN BOOLEAN OptionWhea; ///< @ref BLDOPT_REMOVE_WHEA "BLDOPT_REMOVE_WHEA"
+ IN BOOLEAN OptionDmi; ///< @ref BLDOPT_REMOVE_DMI "BLDOPT_REMOVE_DMI"
+ IN BOOLEAN OptionEarlySamples; ///< @ref BLDOPT_REMOVE_EARLY_SAMPLES "BLDOPT_REMOVE_EARLY_SAMPLES"
+ IN BOOLEAN OptionAddrToCsTranslator; ///< ADDR_TO_CS_TRANSLATOR
+
+ //Build Configuration Area
+ IN UINT64 CfgPciMmioAddress; ///< Pci Mmio Base Address to use for PCI Config accesses.
+ ///< Build-time customizable only - @BldCfgItem{BLDCFG_PCI_MMIO_BASE}
+ IN UINT32 CfgPciMmioSize; ///< Pci Mmio region Size.
+ ///< Build-time customizable only - @BldCfgItem{BLDCFG_PCI_MMIO_SIZE}
+ IN PLATFORM_VRM_CONFIGURATION CfgPlatVrmCfg[MaxVrmType]; ///< Several configuration settings for the voltage regulator modules.
+ IN UINT32 CfgCpuFrequencyLimit; ///< CPU frequency limit
+ IN PLATFORM_CONNECTED_STANDBY_MODES CfgPlatformConnectedStandbyMode; ///< Enable or disable connected standby
+ IN UINT32 CfgPlatNumIoApics; ///< The number of IO APICS for the platform.
+ IN UINT32 CfgMemInitPstate; ///< Memory Init Pstate.
+ IN PLATFORM_CSTATE_MODES CfgPlatformCStateMode; ///< Select the C-State Mode that will used.
+ IN UINT32 CfgPlatformCStateOpData; ///< An IO port or additional C-State setup data, depends on C-State mode.
+ IN UINT16 CfgPlatformCStateIoBaseAddress; ///< Specifies I/O ports that can be used to allow CPU to enter CStates
+ IN PLATFORM_CPB_MODES CfgPlatformCpbMode; ///< Enable or disable core performance boost
+ IN PLATFORM_LOW_POWER_PSTATE_MODES CfgLowPowerPstateForProcHot; ///< Low power Pstate for PROCHOT mode
+ IN UINT32 CfgCoreLevelingMode; ///< Apply any downcoring or core count leveling as specified.
+ IN PERFORMANCE_PROFILE CfgPerformanceProfile; ///< The platform's control flow mode and platform performance settings.
+
+ IN UINT32 CfgAmdPlatformType; ///< Designate the platform as a Server, Desktop, or Mobile.
+ IN UINT32 CfgAmdPowerCeiling; ///< PowerCeiling, specifies a maximum power usage limit for the platform
+ IN UINT16 CfgHtcTemperatureLimit; ///< Hardware Thermal Control temperature limit in tenths of degrees Celsius.
+ IN UINT16 CfgLhtcTemperatureLimit; ///< Local Hardware Thermal Control temperature limit in tenths of degrees Celsius.
+
+ IN UINT32 CfgMemoryBusFrequencyLimit; ///< Memory Bus Frequency Limit.
+ ///< Build-time customizable only - @BldCfgItem{BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT}
+ IN BOOLEAN CfgMemoryModeUnganged; ///< Memory Mode Unganged.
+ ///< Build-time customizable only - @BldCfgItem{BLDCFG_MEMORY_MODE_UNGANGED}
+ IN BOOLEAN CfgMemoryQuadRankCapable; ///< Memory Quad Rank Capable.
+ ///< Build-time customizable only - @BldCfgItem{BLDCFG_MEMORY_QUAD_RANK_CAPABLE}
+ IN UINT32 CfgMemoryQuadrankType; ///< Memory Quadrank Type.
+ ///< Build-time customizable only - @BldCfgItem{BLDCFG_MEMORY_QUADRANK_TYPE}
+ IN BOOLEAN CfgMemoryRDimmCapable; ///< Memory RDIMM Capable.
+ IN BOOLEAN CfgMemoryLRDimmCapable; ///< Memory LRDIMM Capable.
+ IN BOOLEAN CfgMemoryUDimmCapable; ///< Memory UDIMM Capable.
+ IN BOOLEAN CfgMemorySODimmCapable; ///< Memory SODimm Capable.
+ ///< Build-time customizable only - @BldCfgItem{BLDCFG_MEMORY_SODIMM_CAPABLE}
+ IN BOOLEAN CfgLimitMemoryToBelow1Tb; ///< Limit memory address space to below 1TB
+ IN BOOLEAN CfgMemoryEnableBankInterleaving; ///< Memory Enable Bank Interleaving.
+ IN BOOLEAN CfgMemoryEnableNodeInterleaving; ///< Memory Enable Node Interleaving.
+ IN BOOLEAN CfgMemoryChannelInterleaving; ///< Memory Channel Interleaving.
+ IN BOOLEAN CfgMemoryPowerDown; ///< Memory Power Down.
+ IN UINT32 CfgPowerDownMode; ///< Power Down Mode.
+ IN BOOLEAN CfgOnlineSpare; ///< Online Spare.
+ IN BOOLEAN CfgMemoryParityEnable; ///< Memory Parity Enable.
+ IN BOOLEAN CfgBankSwizzle; ///< Bank Swizzle.
+ IN UINT32 CfgTimingModeSelect; ///< Timing Mode Select.
+ IN UINT32 CfgMemoryClockSelect; ///< Memory Clock Select.
+ IN BOOLEAN CfgDqsTrainingControl; ///< Dqs Training Control.
+ ///< Build-time customizable only - @BldCfgItem{BLDCFG_DQS_TRAINING_CONTROL}
+ IN BOOLEAN CfgIgnoreSpdChecksum; ///< Ignore Spd Checksum.
+ ///< Build-time customizable only - @BldCfgItem{BLDCFG_IGNORE_SPD_CHECKSUM}
+ IN BOOLEAN CfgUseBurstMode; ///< Use Burst Mode.
+ ///< Build-time customizable only - @BldCfgItem{BLDCFG_USE_BURST_MODE}
+ IN BOOLEAN CfgMemoryAllClocksOn; ///< Memory All Clocks On.
+ ///< Build-time customizable only - @BldCfgItem{BLDCFG_MEMORY_ALL_CLOCKS_ON}
+ IN BOOLEAN CfgDdrPhyDllBypassMode; ///< Enable DllPDBypassMode
+ IN BOOLEAN CfgEnableEccFeature; ///< Enable ECC Feature.
+ IN BOOLEAN CfgEccRedirection; ///< ECC Redirection.
+ ///< Build-time customizable only - @BldCfgItem{BLDCFG_ECC_REDIRECTION}
+ IN UINT16 CfgScrubDramRate; ///< Scrub Dram Rate.
+ ///< Build-time customizable only - @BldCfgItem{BLDCFG_SCRUB_DRAM_RATE}
+ IN UINT16 CfgScrubL2Rate; ///< Scrub L2Rate.
+ ///< Build-time customizable only - @BldCfgItem{BLDCFG_SCRUB_L2_RATE}
+ IN UINT16 CfgScrubL3Rate; ///< Scrub L3Rate.
+ ///< Build-time customizable only - @BldCfgItem{BLDCFG_SCRUB_L3_RATE}
+ IN UINT16 CfgScrubIcRate; ///< Scrub Ic Rate.
+ ///< Build-time customizable only - @BldCfgItem{BLDCFG_SCRUB_IC_RATE}
+ IN UINT16 CfgScrubDcRate; ///< Scrub Dc Rate.
+ ///< Build-time customizable only - @BldCfgItem{BLDCFG_SCRUB_DC_RATE}
+ IN BOOLEAN CfgEccSyncFlood; ///< ECC Sync Flood.
+ ///< Build-time customizable only - @BldCfgItem{BLDCFG_ECC_SYNC_FLOOD}
+ IN UINT16 CfgEccSymbolSize; ///< ECC Symbol Size.
+ ///< Build-time customizable only - @BldCfgItem{BLDCFG_ECC_SYMBOL_SIZE}
+ IN UINT64 CfgHeapDramAddress; ///< Heap contents will be temporarily stored in this address during the transition.
+ ///< Build-time customizable only - @BldCfgItem{BLDCFG_HEAP_DRAM_ADDRESS}
+ IN BOOLEAN CfgNodeMem1GBAlign; ///< Node Mem 1GB boundary Alignment
+ IN BOOLEAN CfgS3LateRestore; ///< S3 Late Restore
+ IN BOOLEAN CfgAcpiPstateIndependent; ///< PSD method dependent/Independent
+ IN UINT32 CfgAcpiPstatesPsdPolicy; ///< PSD policy
+ IN AP_MTRR_SETTINGS *CfgApMtrrSettingsList; ///< The AP's MTRR settings before final halt
+ ///< Build-time customizable only - @BldCfgItem{BLDCFG_AP_MTRR_SETTINGS_LIST}
+ IN UMA_MODE CfgUmaMode; ///< Uma Mode
+ IN UINT32 CfgUmaSize; ///< Uma Size [31:0]=Addr[47:16]
+ IN BOOLEAN CfgUmaAbove4G; ///< Uma Above 4G Support
+ IN UMA_ALIGNMENT CfgUmaAlignment; ///< Uma alignment
+ IN BOOLEAN CfgProcessorScopeInSb; ///< ACPI Processor Object in \\_SB scope
+ IN CHAR8 CfgProcessorScopeName0; ///< OEM specific 1st character of processor scope name.
+ IN CHAR8 CfgProcessorScopeName1; ///< OEM specific 2nd character of processor scope name.
+ IN UINT8 CfgGnbHdAudio; ///< GNB HD Audio
+ IN UINT8 CfgAbmSupport; ///< Abm Support
+ IN UINT8 CfgDynamicRefreshRate; ///< DRR Dynamic Refresh Rate
+ IN UINT16 CfgLcdBackLightControl; ///< LCD Backlight Control
+ IN UINT8 CfgGnb3dStereoPinIndex; ///< 3D Stereo Pin ID.
+ IN UINT32 CfgTempPcieMmioBaseAddress; ///< Temp pcie MMIO base Address
+ ///< Build-time customizable only - @BldCfgItem{BLDCFG_TEMP_PCIE_MMIO_BASE_ADDRESS}
+ IN UINT32 CfgGnbIGPUSSID; ///< Gnb internal GPU SSID
+ ///< Build-time customizable only - @BldCfgItem{BLDCFG_IGPU_SUBSYSTEM_ID}
+ IN UINT32 CfgGnbHDAudioSSID; ///< Gnb HD Audio SSID
+ ///< Build-time customizable only - @BldCfgItem{BLDCFG_IGPU_HD_AUDIO_SUBSYSTEM_ID}
+ IN UINT32 CfgGnbPcieSSID; ///< Gnb PCIe SSID
+ ///< Build-time customizable only - @BldCfgItem{BLDCFG_APU_PCIE_PORTS_SUBSYSTEM_ID}
+ IN UINT16 CfgLvdsSpreadSpectrum; ///< Lvds Spread Spectrum
+ ///< Build-time customizable only - @BldCfgItem{BLDCFG_GFX_LVDS_SPREAD_SPECTRUM}
+ IN UINT16 CfgLvdsSpreadSpectrumRate; ///< Lvds Spread Spectrum Rate
+ ///< Build-time customizable only - @BldCfgItem{BLDCFG_GFX_LVDS_SPREAD_SPECTRUM_RATE}
+ IN FCH_PLATFORM_POLICY *FchBldCfg; ///< FCH platform build configuration policy
+
+ IN BOOLEAN CfgIommuSupport; ///< IOMMU support
+ IN UINT8 CfgLvdsPowerOnSeqDigonToDe; ///< Panel initialization timing
+ IN UINT8 CfgLvdsPowerOnSeqDeToVaryBl; ///< Panel initialization timing
+ IN UINT8 CfgLvdsPowerOnSeqDeToDigon; ///< Panel initialization timing
+ IN UINT8 CfgLvdsPowerOnSeqVaryBlToDe; ///< Panel initialization timing
+ IN UINT8 CfgLvdsPowerOnSeqOnToOffDelay; ///< Panel initialization timing
+ IN UINT8 CfgLvdsPowerOnSeqVaryBlToBlon; ///< Panel initialization timing
+ IN UINT8 CfgLvdsPowerOnSeqBlonToVaryBl; ///< Panel initialization timing
+ IN UINT16 CfgLvdsMaxPixelClockFreq; ///< The maximum pixel clock frequency supported
+ IN UINT32 CfgLcdBitDepthControlValue; ///< The LCD bit depth control settings
+ IN UINT8 CfgLvds24bbpPanelMode; ///< The LVDS 24 BBP mode
+ IN LVDS_MISC_CONTROL CfgLvdsMiscControl; ///< THe LVDS Misc control
+ IN UINT16 CfgPcieRefClkSpreadSpectrum; ///< PCIe Reference Clock Spread Spectrum
+ ///< Build-time customizable only - @BldCfgItem{BLDCFG_PCIE_REFCLK_SPREAD_SPECTRUM}
+ IN BOOLEAN CfgExternalVrefCtlFeature; ///< External Vref control
+ IN FORCE_TRAIN_MODE CfgForceTrainMode; ///< Force Train Mode
+ IN BOOLEAN CfgGnbRemoteDisplaySupport; ///< Wireless Display Support
+ IN IOMMU_EXCLUSION_RANGE_DESCRIPTOR *CfgIvrsExclusionRangeList;
+ IN BOOLEAN CfgGnbSyncFloodPinAsNmi; ///< @ref BLDCFG_USE_SYNCFLOOD_AS_NMI "BLDCFG_USE_SYNCFLOOD_AS_NMI"
+ IN UINT8 CfgIgpuEnableDisablePolicy; ///< This item defines the iGPU Enable/Disable policy
+ ///< @li 0 = Auto - use current default
+ ///< @li 2 = Disable iGPU if ANY PCI or PCIe Graphics card is present
+ ///< @BldCfgItem{BLDCFG_IGPU_ENABLE_DISABLE_POLICY}
+ IN UINT8 CfgGnbSwTjOffset; ///< Software-writeable TjOffset to account for changes in junction temperature
+ ///< Build-time customizable only - @BldCfgItem{BLDCFG_GNB_THERMAL_SENSOR_CORRECTION}
+ IN UINT8 CfgLvdsMiscVoltAdjustment; ///< Register LVDS_CTRL_4 to adjust LVDS output voltage
+ ///< Build-time customizable only - @BldCfgItem{BLDCFG_LVDS_MISC_VOL_ADJUSTMENT}
+ IN DISPLAY_MISC_CONTROL CfgDisplayMiscControl; ///< The Display Misc control
+ IN DP_FIXED_VOLT_SWING_TYPE CfgDpFixedVoltSwingType;///< To indicate fixed voltage swing value
+ ///< @BldCfgItem{BLDCFG_DP_FIXED_VOLT_SWING}
+ IN TECHNOLOGY_TYPE CfgDimmTypeUsedInMixedConfig; ///< Select the preferred technology type that AGESA will enable
+ ///< when it is mixed with other technology types.
+ IN BOOLEAN CfgHybridBoostEnable; ///< HyBrid Boost support
+ ///< @BldCfgItem{BLDCFG_HYBRID_BOOST_ENABLE}
+ IN UINT64 CfgGnbIoapicAddress; ///< GNB IOAPIC Base Address(NULL if platform configured)
+ ///< @BldCfgItem{BLDCFG_GNB_IOAPIC_ADDRESS}
+ IN BOOLEAN CfgDataEyeEn; ///< Enable get 2D Data Eye
+ IN BOOLEAN CfgDockedTdpHeadroom; ///< @BldCfgItem{BLDCFG_DOCKED_TDP_HEADROOM}
+ IN BOOLEAN CfgBatteryBoostEn; ///< @BldCfgItem{BLDCFG_BATTERY_BOOST_EN}
+ IN UINT32 CfgTdpAcDocked; ///< @BldCfgItem{BLDCFG_TDP_AC_DOCKED}
+ IN UINT32 CfgTdpDcDocked; ///< @BldCfgItem{BLDCFG_TDP_DC_DOCKED}
+ IN UINT32 CfgTdpAcUnDocked; ///< @BldCfgItem{BLDCFG_TDP_AC_UNDOCKED}
+ IN UINT32 CfgTdpDcUnDocked; ///< @BldCfgItem{BLDCFG_TDP_DC_UNDOCKED}
+ IN BOOLEAN CfgStapmEnAcDocked; ///< @BldCfgItem{BLDCFG_STAPM_EN_AC_DOCKED}
+ IN BOOLEAN CfgStapmEnDcDocked; ///< @BldCfgItem{BLDCFG_STAPM_EN_DC_DOCKED}
+ IN BOOLEAN CfgStapmEnAcUnDocked; ///< @BldCfgItem{BLDCFG_STAPM_EN_AC_UNDOCKED}
+ IN BOOLEAN CfgStapmEnDcUnDocked; ///< @BldCfgItem{BLDCFG_STAPM_EN_DC_UNDOCKED}
+ IN UINT32 CfgStapmPowerAcDocked; ///< @BldCfgItem{BLDCFG_STAPM_POWER_AC_DOCKED}
+ IN UINT32 CfgStapmPowerDcDocked; ///< @BldCfgItem{BLDCFG_STAPM_POWER_DC_DOCKED}
+ IN UINT32 CfgStapmPowerAcUnDocked; ///< @BldCfgItem{BLDCFG_STAPM_POWER_AC_UNDOCKED}
+ IN UINT32 CfgStapmPowerDcUnDocked; ///< @BldCfgItem{BLDCFG_STAPM_POWER_DC_UNDOCKED}
+ IN BOOLEAN CfgDramDoubleRefreshRateEn; ///< Double DRAM refresh rate
+ IN ACP_SIZE CfgGnbAcpSize; ///< ACP size [31:0]=Addr[47:16]
+ ///< @BldCfgItem{BLDCFG_ACP_SIZE}
+ IN PMU_TRAIN_MODE CfgPmuTrainMode; ///< Force Train Mode
+ ///< @BldCfgItem{BLDCFG_PMU_TRAINING_MODE}
+ IN MEMORY_PHY_VOLTAGE CfgMemoryPhyVoltage; ///< Memory Phy voltage (VDDR)
+ ///< @BldCfgItem{BLDCFG_MEMORY_PHY_VOLTAGE}
+ IN UINT32 CfgGpuFrequencyLimit; ///< @BldCfgItem{BLDCFG_GPU_FREQUENCY_LIMIT}
+ IN BOOLEAN CfgBapmEnable; ///< @BldCfgItem{BLDCFG_BAPM_ENABLE}
+ IN BOOLEAN Reserved; ///< reserved...
+} BUILD_OPT_CFG;
+
+/// A structure containing platform specific operational characteristics. This
+/// structure is initially populated by the initializer with a copy of the same
+/// structure that was created at build time using the build configuration controls.
+typedef struct _PLATFORM_CONFIGURATION {
+ IN PERFORMANCE_PROFILE PlatformProfile; ///< Several configuration settings for the processor.
+ IN UINT8 CoreLevelingMode; ///< Indicates how to balance the number of cores per processor.
+ ///< @BldCfgItem{BLDCFG_CORE_LEVELING_MODE}
+ IN PLATFORM_CSTATE_MODES CStateMode; ///< Specifies the method of C-State enablement - Disabled, or C6.
+ ///< @BldCfgItem{BLDCFG_PLATFORM_CSTATE_MODE}
+ IN UINT32 CStatePlatformData; ///< This element specifies some pertinent data needed for the operation of the Cstate feature
+ ///< If CStateMode is CStateModeC6, this item is reserved
+ ///< @BldCfgItem{BLDCFG_PLATFORM_CSTATE_OPDATA}
+ IN UINT16 CStateIoBaseAddress; ///< This item specifies a free block of 8 consecutive bytes of I/O ports that
+ ///< can be used to allow the CPU to enter Cstates.
+ ///< @BldCfgItem{BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS}
+ IN PLATFORM_CPB_MODES CpbMode; ///< Specifies the method of core performance boost enablement - Disabled, or Auto.
+ ///< @BldCfgItem{BLDCFG_PLATFORM_CPB_MODE}
+ IN BOOLEAN UserOptionDmi; ///< When set to TRUE, the DMI data table is generated.
+ IN BOOLEAN UserOptionPState; ///< When set to TRUE, the PState data tables are generated.
+ IN BOOLEAN UserOptionCrat; ///< When set to TRUE, the CRAT data table is generated.
+ IN BOOLEAN UserOptionCdit; ///< When set to TRUE, the CDIT data table is generated.
+ IN BOOLEAN UserOptionSrat; ///< When set to TRUE, the SRAT data table is generated.
+ IN BOOLEAN UserOptionSlit; ///< When set to TRUE, the SLIT data table is generated.
+ IN BOOLEAN UserOptionWhea; ///< When set to TRUE, the WHEA data table is generated.
+ IN PLATFORM_LOW_POWER_PSTATE_MODES LowPowerPstateForProcHot; ///< Specifies the method of low power Pstate for PROCHOT enablement - Disabled, or Auto.
+ IN UINT32 PowerCeiling; ///< P-State Ceiling Enabling Deck - Max power milli-watts.
+ IN BOOLEAN ForcePstateIndependent; ///< Deprecated in favor of PstatesPsdPolicy.
+ ///< P-State _PSD is forced independent.
+ ///< @BldCfgItem{BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT}
+ IN UINT32 PstatesPsdPolicy; ///< PSD policy
+ ///< @BldCfgItem{BLDCFG_ACPI_PSTATES_PSD_POLICY}
+ IN UINT32 CpuFrequencyLimit; ///< @BldCfgItem{BLDCFG_CPU_FREQUENCY_LIMIT}
+ IN PLATFORM_CONNECTED_STANDBY_MODES CfgPlatformConnectedStandbyMode; ///< @BldCfgItem{BLDCFG_CPU_CONNECTED_STANDBY_MODE}
+ IN UINT32 NumberOfIoApics; ///< Number of I/O APICs in the system
+ ///< @BldCfgItem{BLDCFG_PLATFORM_NUM_IO_APICS}
+ IN PLATFORM_VRM_CONFIGURATION VrmProperties[MaxVrmType]; ///< Several configuration settings for the voltage regulator modules.
+ IN BOOLEAN ProcessorScopeInSb; ///< ACPI Processor Object in \\_SB scope
+ ///< @BldCfgItem{BLDCFG_PROCESSOR_SCOPE_IN_SB}
+ IN CHAR8 ProcessorScopeName0; ///< OEM specific 1st character of processor scope name.
+ ///< @BldCfgItem{BLDCFG_PROCESSOR_SCOPE_NAME0}
+ IN CHAR8 ProcessorScopeName1; ///< OEM specific 2nd character of processor scope name.
+ ///< @BldCfgItem{BLDCFG_PROCESSOR_SCOPE_NAME1}
+ IN UINT8 GnbHdAudio; ///< Control GFX HD Audio controller(Used for HDMI and DP display output),
+ ///< essentially it enables function 1 of graphics device.
+ ///< @li 0 = HD Audio disable
+ ///< @li 1 = HD Audio enable
+ ///< @BldCfgItem{BLDCFG_CFG_GNB_HD_AUDIO}
+ IN UINT8 AbmSupport; ///< Automatic adjust LVDS/eDP Back light level support.It is
+ ///< characteristic specific to display panel which used by platform design.
+ ///< @li 0 = ABM support disabled
+ ///< @li 1 = ABM support enabled
+ ///< @BldCfgItem{BLDCFG_CFG_ABM_SUPPORT}
+ IN UINT8 DynamicRefreshRate; ///< Adjust refresh rate on LVDS/eDP.
+ ///< @BldCfgItem{BLDCFG_CFG_DYNAMIC_REFRESH_RATE}
+ IN UINT16 LcdBackLightControl; ///< The PWM frequency to LCD backlight control.
+ ///< If equal to 0 backlight not controlled by iGPU
+ ///< @BldCfgItem{BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL}
+ IN UINT16 HtcTemperatureLimit; ///< The Hardware Thermal Control temperature limit in tenths of degrees Celsius.
+ ///< If equal to 0, use hardware defaults.
+ ///< @BldCfgItem{BLDCFG_HTC_TEMPERATURE_LIMIT}
+ IN UINT16 LhtcTemperatureLimit; ///< The Local Hardware Thermal Control temperature limit in tenths of degrees Celsius.
+ ///< If equal to 0, use hardware defaults.
+ ///< @BldCfgItem{BLDCFG_LHTC_TEMPERATURE_LIMIT}
+ IN ACP_SIZE AcpSize; ///< The size of ACP dram
+ ///< ACP_Size[31:0]=Addr[47:16]
+ ///< @BldCfgItem{BLDCFG_ACP_SIZE}
+} PLATFORM_CONFIGURATION;
+
+
+/**********************************************************************
+ * Structures for: AmdInitLate
+ **********************************************************************/
+#define PROC_VERSION_LENGTH 48
+#define MAX_DIMMS_PER_SOCKET 16
+#define PROC_MANU_LENGTH 29
+
+/* Interface Parameter Structures */
+/// DMI Type4 - Processor ID
+typedef struct {
+ OUT UINT32 ProcIdLsd; ///< Lower half of 64b ID
+ OUT UINT32 ProcIdMsd; ///< Upper half of 64b ID
+} TYPE4_PROC_ID;
+
+/// DMI Type 4 - Processor information
+typedef struct {
+ OUT UINT8 T4ProcType; ///< CPU Type
+ OUT UINT8 T4ProcFamily; ///< Family 1
+ OUT TYPE4_PROC_ID T4ProcId; ///< Id
+ OUT UINT8 T4Voltage; ///< Voltage
+ OUT UINT16 T4ExternalClock; ///< External clock
+ OUT UINT16 T4MaxSpeed; ///< Max speed
+ OUT UINT16 T4CurrentSpeed; ///< Current speed
+ OUT UINT8 T4Status; ///< Status
+ OUT UINT8 T4ProcUpgrade; ///< Up grade
+ OUT UINT8 T4CoreCount; ///< Core count
+ OUT UINT8 T4CoreEnabled; ///< Core Enable
+ OUT UINT8 T4ThreadCount; ///< Thread count
+ OUT UINT16 T4ProcCharacteristics; ///< Characteristics
+ OUT UINT16 T4ProcFamily2; ///< Family 2
+ OUT CHAR8 T4ProcVersion[PROC_VERSION_LENGTH]; ///< Cpu version
+ OUT CHAR8 T4ProcManufacturer[PROC_MANU_LENGTH]; ///< Manufacturer
+} TYPE4_DMI_INFO;
+
+/// DMI Type 7 - Cache information
+typedef struct _TYPE7_DMI_INFO {
+ OUT UINT16 T7CacheCfg; ///< Cache cfg
+ OUT UINT16 T7MaxCacheSize; ///< Max size
+ OUT UINT16 T7InstallSize; ///< Install size
+ OUT UINT16 T7SupportedSramType; ///< Supported Sram Type
+ OUT UINT16 T7CurrentSramType; ///< Current type
+ OUT UINT8 T7CacheSpeed; ///< Speed
+ OUT UINT8 T7ErrorCorrectionType; ///< ECC type
+ OUT UINT8 T7SystemCacheType; ///< Cache type
+ OUT UINT8 T7Associativity; ///< Associativity
+} TYPE7_DMI_INFO;
+
+/// DMI Type 16 offset 04h - Location
+typedef enum {
+ OtherLocation = 0x01, ///< Assign 01 to Other
+ UnknownLocation, ///< Assign 02 to Unknown
+ SystemboardOrMotherboard, ///< Assign 03 to systemboard or motherboard
+ IsaAddonCard, ///< Assign 04 to ISA add-on card
+ EisaAddonCard, ///< Assign 05 to EISA add-on card
+ PciAddonCard, ///< Assign 06 to PCI add-on card
+ McaAddonCard, ///< Assign 07 to MCA add-on card
+ PcmciaAddonCard, ///< Assign 08 to PCMCIA add-on card
+ ProprietaryAddonCard, ///< Assign 09 to proprietary add-on card
+ NuBus, ///< Assign 0A to NuBus
+ Pc98C20AddonCard, ///< Assign 0A0 to PC-98/C20 add-on card
+ Pc98C24AddonCard, ///< Assign 0A1 to PC-98/C24 add-on card
+ Pc98EAddoncard, ///< Assign 0A2 to PC-98/E add-on card
+ Pc98LocalBusAddonCard ///< Assign 0A3 to PC-98/Local bus add-on card
+} DMI_T16_LOCATION;
+
+/// DMI Type 16 offset 05h - Memory Error Correction
+typedef enum {
+ OtherUse = 0x01, ///< Assign 01 to Other
+ UnknownUse, ///< Assign 02 to Unknown
+ SystemMemory, ///< Assign 03 to system memory
+ VideoMemory, ///< Assign 04 to video memory
+ FlashMemory, ///< Assign 05 to flash memory
+ NonvolatileRam, ///< Assign 06 to non-volatile RAM
+ CacheMemory ///< Assign 07 to cache memory
+} DMI_T16_USE;
+
+/// DMI Type 16 offset 07h - Maximum Capacity
+typedef enum {
+ Dmi16OtherErrCorrection = 0x01, ///< Assign 01 to Other
+ Dmi16UnknownErrCorrection, ///< Assign 02 to Unknown
+ Dmi16NoneErrCorrection, ///< Assign 03 to None
+ Dmi16Parity, ///< Assign 04 to parity
+ Dmi16SingleBitEcc, ///< Assign 05 to Single-bit ECC
+ Dmi16MultiBitEcc, ///< Assign 06 to Multi-bit ECC
+ Dmi16Crc ///< Assign 07 to CRC
+} DMI_T16_ERROR_CORRECTION;
+
+/// DMI Type 16 - Physical Memory Array
+typedef struct {
+ OUT DMI_T16_LOCATION Location; ///< The physical location of the Memory Array,
+ ///< whether on the system board or an add-in board.
+ OUT DMI_T16_USE Use; ///< Identifies the function for which the array
+ ///< is used.
+ OUT DMI_T16_ERROR_CORRECTION MemoryErrorCorrection; ///< The primary hardware error correction or
+ ///< detection method supported by this memory array.
+ OUT UINT16 NumberOfMemoryDevices; ///< The number of slots or sockets available
+ ///< for memory devices in this array.
+} TYPE16_DMI_INFO;
+
+/// DMI Type 17 offset 0Eh - Form Factor
+typedef enum {
+ OtherFormFactor = 0x01, ///< Assign 01 to Other
+ UnknowFormFactor, ///< Assign 02 to Unknown
+ SimmFormFactor, ///< Assign 03 to SIMM
+ SipFormFactor, ///< Assign 04 to SIP
+ ChipFormFactor, ///< Assign 05 to Chip
+ DipFormFactor, ///< Assign 06 to DIP
+ ZipFormFactor, ///< Assign 07 to ZIP
+ ProprietaryCardFormFactor, ///< Assign 08 to Proprietary Card
+ DimmFormFactorFormFactor, ///< Assign 09 to DIMM
+ TsopFormFactor, ///< Assign 10 to TSOP
+ RowOfChipsFormFactor, ///< Assign 11 to Row of chips
+ RimmFormFactor, ///< Assign 12 to RIMM
+ SodimmFormFactor, ///< Assign 13 to SODIMM
+ SrimmFormFactor, ///< Assign 14 to SRIMM
+ FbDimmFormFactor ///< Assign 15 to FB-DIMM
+} DMI_T17_FORM_FACTOR;
+
+/// DMI Type 17 offset 12h - Memory Type
+typedef enum {
+ OtherMemType = 0x01, ///< Assign 01 to Other
+ UnknownMemType, ///< Assign 02 to Unknown
+ DramMemType, ///< Assign 03 to DRAM
+ EdramMemType, ///< Assign 04 to EDRAM
+ VramMemType, ///< Assign 05 to VRAM
+ SramMemType, ///< Assign 06 to SRAM
+ RamMemType, ///< Assign 07 to RAM
+ RomMemType, ///< Assign 08 to ROM
+ FlashMemType, ///< Assign 09 to Flash
+ EepromMemType, ///< Assign 10 to EEPROM
+ FepromMemType, ///< Assign 11 to FEPROM
+ EpromMemType, ///< Assign 12 to EPROM
+ CdramMemType, ///< Assign 13 to CDRAM
+ ThreeDramMemType, ///< Assign 14 to 3DRAM
+ SdramMemType, ///< Assign 15 to SDRAM
+ SgramMemType, ///< Assign 16 to SGRAM
+ RdramMemType, ///< Assign 17 to RDRAM
+ DdrMemType, ///< Assign 18 to DDR
+ Ddr2MemType, ///< Assign 19 to DDR2
+ Ddr2FbdimmMemType, ///< Assign 20 to DDR2 FB-DIMM
+ Ddr3MemType = 0x18, ///< Assign 24 to DDR3
+ Fbd2MemType ///< Assign 25 to FBD2
+} DMI_T17_MEMORY_TYPE;
+
+/// DMI Type 17 offset 13h - Type Detail
+typedef struct {
+ OUT UINT16 Reserved1:1; ///< Reserved
+ OUT UINT16 Other:1; ///< Other
+ OUT UINT16 Unknown:1; ///< Unknown
+ OUT UINT16 FastPaged:1; ///< Fast-Paged
+ OUT UINT16 StaticColumn:1; ///< Static column
+ OUT UINT16 PseudoStatic:1; ///< Pseudo-static
+ OUT UINT16 Rambus:1; ///< RAMBUS
+ OUT UINT16 Synchronous:1; ///< Synchronous
+ OUT UINT16 Cmos:1; ///< CMOS
+ OUT UINT16 Edo:1; ///< EDO
+ OUT UINT16 WindowDram:1; ///< Window DRAM
+ OUT UINT16 CacheDram:1; ///< Cache Dram
+ OUT UINT16 NonVolatile:1; ///< Non-volatile
+ OUT UINT16 Registered:1; ///< Registered (Buffered)
+ OUT UINT16 Unbuffered:1; ///< Unbuffered (Unregistered)
+ OUT UINT16 Reserved2:1; ///< Reserved
+} DMI_T17_TYPE_DETAIL;
+
+/// DMI Type 17 - Memory Device
+typedef struct {
+ OUT UINT16 Handle; ///< The temporary handle, or instance number, associated with the structure
+ OUT UINT16 TotalWidth; ///< Total Width, in bits, of this memory device, including any check or error-correction bits.
+ OUT UINT16 DataWidth; ///< Data Width, in bits, of this memory device.
+ OUT UINT16 MemorySize; ///< The size of the memory device.
+ OUT DMI_T17_FORM_FACTOR FormFactor; ///< The implementation form factor for this memory device.
+ OUT UINT8 DeviceSet; ///< Identifies when the Memory Device is one of a set of
+ ///< Memory Devices that must be populated with all devices of
+ ///< the same type and size, and the set to which this device belongs.
+ OUT CHAR8 DeviceLocator[8]; ///< The string number of the string that identifies the physically labeled socket or board position where the memory device is located.
+ OUT CHAR8 BankLocator[10]; ///< The string number of the string that identifies the physically labeled bank where the memory device is located.
+ OUT DMI_T17_MEMORY_TYPE MemoryType; ///< The type of memory used in this device.
+ OUT DMI_T17_TYPE_DETAIL TypeDetail; ///< Additional detail on the memory device type
+ OUT UINT16 Speed; ///< Identifies the speed of the device, in megahertz (MHz).
+ OUT UINT64 ManufacturerIdCode; ///< Manufacturer ID code.
+ OUT CHAR8 SerialNumber[9]; ///< Serial Number.
+ OUT CHAR8 PartNumber[19]; ///< Part Number.
+ OUT UINT8 Attributes; ///< Bits 7-4: Reserved, Bits 3-0: rank.
+ OUT UINT32 ExtSize; ///< Extended Size.
+ OUT UINT16 ConfigSpeed; ///< Configured memory clock speed
+} TYPE17_DMI_INFO;
+
+/// Memory DMI Type 17 - for memory use
+typedef struct {
+ OUT UINT8 Socket:3; ///< Socket ID
+ OUT UINT8 Channel:2; ///< Channel ID
+ OUT UINT8 Dimm:2; ///< DIMM ID
+ OUT UINT8 DimmPresent:1; ///< Dimm Present
+ OUT UINT16 Handle; ///< The temporary handle, or instance number, associated with the structure
+ OUT UINT16 TotalWidth; ///< Total Width, in bits, of this memory device, including any check or error-correction bits.
+ OUT UINT16 DataWidth; ///< Data Width, in bits, of this memory device.
+ OUT UINT16 MemorySize; ///< The size of the memory device.
+ OUT DMI_T17_FORM_FACTOR FormFactor; ///< The implementation form factor for this memory device.
+ OUT UINT8 DeviceLocator; ///< The string number of the string that identifies the physically labeled socket or board position where the memory device is located.
+ OUT UINT8 BankLocator; ///< The string number of the string that identifies the physically labeled bank where the memory device is located.
+ OUT UINT16 Speed; ///< Identifies the speed of the device, in megahertz (MHz).
+ OUT UINT64 ManufacturerIdCode; ///< Manufacturer ID code.
+ OUT UINT8 SerialNumber[4]; ///< Serial Number.
+ OUT UINT8 PartNumber[18]; ///< Part Number.
+ OUT UINT8 Attributes; ///< Bits 7-4: Reserved, Bits 3-0: rank.
+ OUT UINT32 ExtSize; ///< Extended Size.
+ OUT UINT16 ConfigSpeed; ///< Configured memory clock speed
+} MEM_DMI_PHYSICAL_DIMM_INFO;
+
+/// Memory DMI Type 20 - for memory use
+typedef struct {
+ OUT UINT8 Socket:3; ///< Socket ID
+ OUT UINT8 Channel:2; ///< Channel ID
+ OUT UINT8 Dimm:2; ///< DIMM ID
+ OUT UINT8 DimmPresent:1; ///< Dimm Present
+ OUT UINT32 StartingAddr; ///< The physical address, in kilobytes, of a range
+ ///< of memory mapped to the referenced Memory Device.
+ OUT UINT32 EndingAddr; ///< The handle, or instance number, associated with
+ ///< the Memory Device structure to which this address
+ ///< range is mapped.
+ OUT UINT16 MemoryDeviceHandle; ///< The handle, or instance number, associated with
+ ///< the Memory Device structure to which this address
+ ///< range is mapped.
+ OUT UINT64 ExtStartingAddr; ///< The physical address, in bytes, of a range of
+ ///< memory mapped to the referenced Memory Device.
+ OUT UINT64 ExtEndingAddr; ///< The physical ending address, in bytes, of the last of
+ ///< a range of addresses mapped to the referenced Memory Device.
+} MEM_DMI_LOGICAL_DIMM_INFO;
+
+/// DMI Type 19 - Memory Array Mapped Address
+typedef struct {
+ OUT UINT32 StartingAddr; ///< The physical address, in kilobytes,
+ ///< of a range of memory mapped to the
+ ///< specified physical memory array.
+ OUT UINT32 EndingAddr; ///< The physical ending address of the
+ ///< last kilobyte of a range of addresses
+ ///< mapped to the specified physical memory array.
+ OUT UINT16 MemoryArrayHandle; ///< The handle, or instance number, associated
+ ///< with the physical memory array to which this
+ ///< address range is mapped.
+ OUT UINT8 PartitionWidth; ///< Identifies the number of memory devices that
+ ///< form a single row of memory for the address
+ ///< partition defined by this structure.
+ OUT UINT64 ExtStartingAddr; ///< The physical address, in bytes, of a range of
+ ///< memory mapped to the specified Physical Memory Array.
+ OUT UINT64 ExtEndingAddr; ///< The physical address, in bytes, of a range of
+ ///< memory mapped to the specified Physical Memory Array.
+} TYPE19_DMI_INFO;
+
+///DMI Type 20 - Memory Device Mapped Address
+typedef struct {
+ OUT UINT32 StartingAddr; ///< The physical address, in kilobytes, of a range
+ ///< of memory mapped to the referenced Memory Device.
+ OUT UINT32 EndingAddr; ///< The handle, or instance number, associated with
+ ///< the Memory Device structure to which this address
+ ///< range is mapped.
+ OUT UINT16 MemoryDeviceHandle; ///< The handle, or instance number, associated with
+ ///< the Memory Device structure to which this address
+ ///< range is mapped.
+ OUT UINT16 MemoryArrayMappedAddressHandle; ///< The handle, or instance number, associated
+ ///< with the Memory Array Mapped Address structure to
+ ///< which this device address range is mapped.
+ OUT UINT8 PartitionRowPosition; ///< Identifies the position of the referenced Memory
+ ///< Device in a row of the address partition.
+ OUT UINT8 InterleavePosition; ///< The position of the referenced Memory Device in
+ ///< an interleave.
+ OUT UINT8 InterleavedDataDepth; ///< The maximum number of consecutive rows from the
+ ///< referenced Memory Device that are accessed in a
+ ///< single interleaved transfer.
+ OUT UINT64 ExtStartingAddr; ///< The physical address, in bytes, of a range of
+ ///< memory mapped to the referenced Memory Device.
+ OUT UINT64 ExtEndingAddr; ///< The physical ending address, in bytes, of the last of
+ ///< a range of addresses mapped to the referenced Memory Device.
+} TYPE20_DMI_INFO;
+
+/// Collection of pointers to the DMI records
+typedef struct {
+ OUT TYPE4_DMI_INFO T4[MAX_SOCKETS_SUPPORTED]; ///< Type 4 struc
+ OUT TYPE7_DMI_INFO T7L1[MAX_SOCKETS_SUPPORTED]; ///< Type 7 struc 1
+ OUT TYPE7_DMI_INFO T7L2[MAX_SOCKETS_SUPPORTED]; ///< Type 7 struc 2
+ OUT TYPE7_DMI_INFO T7L3[MAX_SOCKETS_SUPPORTED]; ///< Type 7 struc 3
+ OUT TYPE16_DMI_INFO T16; ///< Type 16 struc
+ OUT TYPE17_DMI_INFO T17[MAX_SOCKETS_SUPPORTED][MAX_CHANNELS_PER_SOCKET][MAX_DIMMS_PER_CHANNEL]; ///< Type 17 struc
+ OUT TYPE19_DMI_INFO T19; ///< Type 19 struc
+ OUT TYPE20_DMI_INFO T20[MAX_SOCKETS_SUPPORTED][MAX_CHANNELS_PER_SOCKET][MAX_DIMMS_PER_CHANNEL]; ///< Type 20 struc
+} DMI_INFO;
+
+/**********************************************************************
+ * Interface call: AllocateExecutionCache
+ **********************************************************************/
+#define MAX_CACHE_REGIONS 3
+
+/// AllocateExecutionCache sub param structure for cached memory region
+typedef struct {
+ IN OUT UINT32 ExeCacheStartAddr; ///< Start address
+ IN OUT UINT32 ExeCacheSize; ///< Size
+} EXECUTION_CACHE_REGION;
+
+/**********************************************************************
+ * Interface call: AmdGetAvailableExeCacheSize
+ **********************************************************************/
+/// Get available Cache remain
+typedef struct {
+ IN OUT AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header
+ OUT UINT32 AvailableExeCacheSize; ///< Remain size
+} AMD_GET_EXE_SIZE_PARAMS;
+
+AGESA_STATUS
+AmdGetAvailableExeCacheSize (
+ IN OUT AMD_GET_EXE_SIZE_PARAMS *AmdGetExeSizeParams
+ );
+
+/// Selection type for core leveling
+typedef enum {
+ CORE_LEVEL_LOWEST, ///< Level to lowest common denominator
+ CORE_LEVEL_TWO, ///< Level to 2 cores
+ CORE_LEVEL_POWER_OF_TWO, ///< Level to 1,2,4 or 8
+ CORE_LEVEL_NONE, ///< Do no leveling
+ CORE_LEVEL_COMPUTE_UNIT, ///< Level cores to one core per compute unit
+ CORE_LEVEL_COMPUTE_UNIT_TWO, ///< Level cores to two cores per compute unit
+ CORE_LEVEL_COMPUTE_UNIT_THREE, ///< Level cores to three cores per compute unit
+ CORE_LEVEL_ONE, ///< Level to 1 core
+ CORE_LEVEL_THREE, ///< Level to 3 cores
+ CORE_LEVEL_FOUR, ///< Level to 4 cores
+ CORE_LEVEL_FIVE, ///< Level to 5 cores
+ CORE_LEVEL_SIX, ///< Level to 6 cores
+ CORE_LEVEL_SEVEN, ///< Level to 7 cores
+ CORE_LEVEL_EIGHT, ///< Level to 8 cores
+ CORE_LEVEL_NINE, ///< Level to 9 cores
+ CORE_LEVEL_TEN, ///< Level to 10 cores
+ CORE_LEVEL_ELEVEN, ///< Level to 11 cores
+ CORE_LEVEL_TWELVE, ///< Level to 12 cores
+ CORE_LEVEL_THIRTEEN, ///< Level to 13 cores
+ CORE_LEVEL_FOURTEEN, ///< Level to 14 cores
+ CORE_LEVEL_FIFTEEN, ///< Level to 15 cores
+ CoreLevelModeMax ///< Used for bounds checking
+} CORE_LEVELING_TYPE;
+
+
+
+
+
+/************************************************************************
+ *
+ * AGESA Basic Level interface structure definition and function prototypes
+ *
+ ***********************************************************************/
+
+/**********************************************************************
+ * Interface call: AmdCreateStruct
+ **********************************************************************/
+AGESA_STATUS
+AmdCreateStruct (
+ IN OUT AMD_INTERFACE_PARAMS *InterfaceParams
+ );
+
+/**********************************************************************
+ * Interface call: AmdReleaseStruct
+ **********************************************************************/
+AGESA_STATUS
+AmdReleaseStruct (
+ IN OUT AMD_INTERFACE_PARAMS *InterfaceParams
+ );
+
+/**********************************************************************
+ * Interface call: AmdInitReset
+ **********************************************************************/
+/// AmdInitReset param structure
+typedef struct {
+ IN AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header
+ IN EXECUTION_CACHE_REGION CacheRegion[3]; ///< The cached memory region
+ IN FCH_RESET_INTERFACE FchInterface; ///< Interface for FCH configuration
+} AMD_RESET_PARAMS;
+
+AGESA_STATUS
+AmdInitReset (
+ IN OUT AMD_RESET_PARAMS *ResetParams
+ );
+
+
+/**********************************************************************
+ * Interface call: AmdInitEarly
+ **********************************************************************/
+/// InitEarly param structure
+///
+/// Provide defaults or customizations to each service performed in AmdInitEarly.
+///
+typedef struct {
+ IN OUT AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header
+ IN EXECUTION_CACHE_REGION CacheRegion[3]; ///< Execution Map Interface
+ IN PLATFORM_CONFIGURATION PlatformConfig; ///< platform operational characteristics.
+ IN GNB_CONFIGURATION GnbConfig; ///< GNB configuration
+} AMD_EARLY_PARAMS;
+
+AGESA_STATUS
+AmdInitEarly (
+ IN OUT AMD_EARLY_PARAMS *EarlyParams
+ );
+
+
+/**********************************************************************
+ * Interface call: AmdInitPost
+ **********************************************************************/
+/// AmdInitPost param structure
+typedef struct {
+ IN OUT AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header
+ IN PLATFORM_CONFIGURATION PlatformConfig; ///< platform operational characteristics.
+ IN MEM_PARAMETER_STRUCT MemConfig; ///< Memory post param
+ IN GNB_POST_CONFIGURATION GnbPostConfig; ///< GNB post param
+} AMD_POST_PARAMS;
+
+AGESA_STATUS
+AmdInitPost (
+ IN OUT AMD_POST_PARAMS *PostParams ///< Amd Cpu init param
+ );
+
+
+/**********************************************************************
+ * Interface call: AmdInitEnv
+ **********************************************************************/
+/// AmdInitEnv param structure
+typedef struct {
+ IN OUT AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header
+ IN PLATFORM_CONFIGURATION PlatformConfig; ///< platform operational characteristics.
+ IN GNB_ENV_CONFIGURATION GnbEnvConfiguration; ///< GNB configuration
+ IN FCH_INTERFACE FchInterface; ///< FCH configuration
+} AMD_ENV_PARAMS;
+
+AGESA_STATUS
+AmdInitEnv (
+ IN OUT AMD_ENV_PARAMS *EnvParams
+ );
+
+
+/**********************************************************************
+ * Interface call: AmdInitMid
+ **********************************************************************/
+/// AmdInitMid param structure
+typedef struct {
+ IN OUT AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header
+ IN PLATFORM_CONFIGURATION PlatformConfig; ///< platform operational characteristics.
+ IN GNB_MID_CONFIGURATION GnbMidConfiguration; ///< GNB configuration
+ IN FCH_INTERFACE FchInterface; ///< FCH configuration
+} AMD_MID_PARAMS;
+
+AGESA_STATUS
+AmdInitMid (
+ IN OUT AMD_MID_PARAMS *MidParams
+ );
+
+
+/**********************************************************************
+ * Interface call: AmdInitLate
+ **********************************************************************/
+/// AmdInitLate param structure
+typedef struct {
+ IN OUT AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header
+ IN PLATFORM_CONFIGURATION PlatformConfig; ///< platform operational characteristics.
+ IN IOMMU_EXCLUSION_RANGE_DESCRIPTOR *IvrsExclusionRangeList; ///< Pointer to array of exclusion ranges
+ OUT DMI_INFO *DmiTable; ///< DMI Interface
+ OUT VOID *AcpiPState; ///< Acpi Pstate SSDT Table
+ OUT VOID *AcpiSrat; ///< SRAT Table
+ OUT VOID *AcpiSlit; ///< SLIT Table
+ OUT VOID *AcpiWheaMce; ///< WHEA MCE Table
+ OUT VOID *AcpiWheaCmc; ///< WHEA CMC Table
+ OUT VOID *AcpiAlib; ///< ACPI SSDT table with ALIB implementation
+ OUT VOID *AcpiIvrs; ///< IOMMU ACPI IVRS(I/O Virtualization Reporting Structure) table
+ OUT VOID *AcpiCrat; ///< Component Resource Affinity Table table
+ OUT VOID *AcpiCdit; ///< Component Locality Distance Information table
+ IN GNB_LATE_CONFIGURATION GnbLateConfiguration; ///< GNB configuration
+} AMD_LATE_PARAMS;
+
+AGESA_STATUS
+AmdInitLate (
+ IN OUT AMD_LATE_PARAMS *LateParams
+ );
+
+/**********************************************************************
+ * Interface call: AmdInitRecovery
+ **********************************************************************/
+/// CPU Recovery Parameters
+typedef struct {
+ IN OUT AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header
+ IN PLATFORM_CONFIGURATION PlatformConfig; ///< platform operational characteristics.
+} AMD_CPU_RECOVERY_PARAMS;
+
+/// AmdInitRecovery param structure
+typedef struct {
+ IN OUT AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header
+ IN MEM_PARAMETER_STRUCT MemConfig; ///< Memory post param
+ IN EXECUTION_CACHE_REGION CacheRegion[3]; ///< The cached memory region. And the max cache region is 3
+ IN AMD_CPU_RECOVERY_PARAMS CpuRecoveryParams; ///< Params for CPU related recovery init.
+} AMD_RECOVERY_PARAMS;
+
+AGESA_STATUS
+AmdInitRecovery (
+ IN OUT AMD_RECOVERY_PARAMS *RecoveryParams
+ );
+
+/**********************************************************************
+ * Interface call: AmdInitResume
+ **********************************************************************/
+/// AmdInitResume param structure
+typedef struct {
+ IN OUT AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header
+ IN PLATFORM_CONFIGURATION PlatformConfig; ///< Platform operational characteristics
+ IN AMD_S3_PARAMS S3DataBlock; ///< Save state data
+} AMD_RESUME_PARAMS;
+
+AGESA_STATUS
+AmdInitResume (
+ IN AMD_RESUME_PARAMS *ResumeParams
+ );
+
+
+/**********************************************************************
+ * Interface call: AmdS3LateRestore
+ **********************************************************************/
+/// AmdS3LateRestore param structure
+typedef struct {
+ IN OUT AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header
+ IN PLATFORM_CONFIGURATION PlatformConfig; ///< platform operational characteristics.
+ IN AMD_S3_PARAMS S3DataBlock; ///< Save state data
+} AMD_S3LATE_PARAMS;
+
+AGESA_STATUS
+AmdS3LateRestore (
+ IN OUT AMD_S3LATE_PARAMS *S3LateParams
+ );
+
+
+/**********************************************************************
+ * Interface call: AmdS3FinalRestore
+ **********************************************************************/
+/// AmdS3FinalRestore param structure
+typedef struct {
+ IN OUT AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header
+ IN PLATFORM_CONFIGURATION PlatformConfig; ///< platform operational characteristics.
+ IN AMD_S3_PARAMS S3DataBlock; ///< Save state data
+} AMD_S3FINAL_PARAMS;
+
+AGESA_STATUS
+AmdS3FinalRestore (
+ IN OUT AMD_S3FINAL_PARAMS *S3FinalParams
+ );
+
+
+/**********************************************************************
+ * Interface call: AmdS3Save
+ **********************************************************************/
+/// AmdS3Save param structure
+typedef struct {
+ IN OUT AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header
+ IN PLATFORM_CONFIGURATION PlatformConfig; ///< platform operational characteristics.
+ OUT AMD_S3_PARAMS S3DataBlock; ///< Standard header
+ IN FCH_INTERFACE FchInterface; ///< FCH configuration
+} AMD_S3SAVE_PARAMS;
+
+AGESA_STATUS
+AmdS3Save (
+ IN OUT AMD_S3SAVE_PARAMS *AmdS3SaveParams
+ );
+
+
+/**********************************************************************
+ * Interface call: AmdLateRunApTask
+ **********************************************************************/
+/**
+ * Entry point for AP tasking.
+ */
+AGESA_STATUS
+AmdLateRunApTask (
+ IN AP_EXE_PARAMS *AmdApExeParams
+);
+
+//
+// General Services API
+//
+
+/**********************************************************************
+ * Interface service call: AmdGetApicId
+ **********************************************************************/
+/// Request the APIC ID of a particular core.
+
+typedef struct {
+ IN AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header
+ IN UINT8 Socket; ///< The Core's Socket.
+ IN UINT8 Core; ///< The Core id.
+ OUT BOOLEAN IsPresent; ///< The Core is present, and ApicAddress is valid.
+ OUT UINT8 ApicAddress; ///< The Core's APIC ID.
+} AMD_APIC_PARAMS;
+
+/**
+ * Get a specified Core's APIC ID.
+ */
+AGESA_STATUS
+AmdGetApicId (
+ IN OUT AMD_APIC_PARAMS *AmdParamApic
+);
+
+/**********************************************************************
+ * Interface service call: AmdGetPciAddress
+ **********************************************************************/
+/// Request the PCI Address of a Processor Module (that is, its Northbridge)
+
+typedef struct {
+ IN AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header
+ IN UINT8 Socket; ///< The Processor's socket
+ IN UINT8 Module; ///< The Module in that Processor
+ OUT BOOLEAN IsPresent; ///< The Core is present, and PciAddress is valid.
+ OUT PCI_ADDR PciAddress; ///< The Processor's PCI Config Space address (Function 0, Register 0)
+} AMD_GET_PCI_PARAMS;
+
+/**
+ * Get Processor Module's PCI Config Space address.
+ */
+AGESA_STATUS
+AmdGetPciAddress (
+ IN OUT AMD_GET_PCI_PARAMS *AmdParamGetPci
+);
+
+/**********************************************************************
+ * Interface service call: AmdIdentifyCore
+ **********************************************************************/
+/// Request the identity (Socket, Module, Core) of the current Processor Core
+
+typedef struct {
+ IN AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header
+ OUT UINT8 Socket; ///< The current Core's Socket
+ OUT UINT8 Module; ///< The current Core's Processor Module
+ OUT UINT8 Core; ///< The current Core's core id.
+} AMD_IDENTIFY_PARAMS;
+
+/**
+ * "Who am I" for the current running core.
+ */
+AGESA_STATUS
+AmdIdentifyCore (
+ IN OUT AMD_IDENTIFY_PARAMS *AmdParamIdentify
+);
+
+/**********************************************************************
+ * Interface service call: AmdReadEventLog
+ **********************************************************************/
+/// An Event Log Entry.
+typedef struct {
+ IN AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header
+ OUT UINT32 EventClass; ///< The severity of this event, matches AGESA_STATUS.
+ OUT UINT32 EventInfo; ///< The unique event identifier, zero means "no event".
+ OUT UINT32 DataParam1; ///< Data specific to the Event.
+ OUT UINT32 DataParam2; ///< Data specific to the Event.
+ OUT UINT32 DataParam3; ///< Data specific to the Event.
+ OUT UINT32 DataParam4; ///< Data specific to the Event.
+} EVENT_PARAMS;
+
+/**
+ * Read an Event from the Event Log.
+ */
+AGESA_STATUS
+AmdReadEventLog (
+ IN EVENT_PARAMS *Event
+);
+
+/**********************************************************************
+ * Interface service call: AmdIdentifyDimm
+ **********************************************************************/
+/// Request the identity of dimm from system address
+
+typedef struct {
+ IN OUT AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header
+ IN UINT64 MemoryAddress; ///< System Address that needs to be translated to dimm identification.
+ OUT UINT8 SocketId; ///< The socket on which the targeted address locates.
+ OUT UINT8 MemChannelId; ///< The channel on which the targeted address locates.
+ OUT UINT8 DimmId; ///< The dimm on which the targeted address locates.
+ OUT UINT8 ChipSelect; ///< The chip select on which the targeted address locates.
+ OUT UINT8 Bank; ///< The Bank for which the error address resides
+ OUT UINT32 Row; ///< The Row for which the error address resides
+ OUT UINT16 Column; ///< The Column for which the error address resides
+} AMD_IDENTIFY_DIMM;
+
+/**
+ * Get the dimm identification for the address.
+ */
+AGESA_STATUS
+AmdIdentifyDimm (
+ IN OUT AMD_IDENTIFY_DIMM *AmdDimmIdentify
+);
+
+AGESA_STATUS
+AmdIdsRunApTaskLate (
+ IN AP_EXE_PARAMS *AmdApExeParams
+ );
+
+/// Request the 2D Data Eye Training Data
+#define RD_DATAEYE 0
+#define WR_DATAEYE 1
+
+/**********************************************************************
+ * Interface service call: AmdGet2DDataEye
+ **********************************************************************/
+/// Request the training data eye on Socket, Channel, Dimm.
+
+typedef struct _AMD_GET_DATAEYE {
+ IN OUT AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header
+ IN OUT AMD_POST_PARAMS *PostParamsPtr; ///< Pointer to AMD_POST_PARAMS
+ IN UINT8 SocketId; ///< The socket number to get the 2D data eye
+ IN UINT8 MemChannelId; ///< The channel number to get the 2D data eye
+ IN UINT8 DimmId; ///< The dimm number to get the 2D data eye
+ IN UINT8 DataEyeType; ///< Get the 2D data eye on read or write training
+ OUT UINT8* DataEyeBuffer; ///< The buffer to stores the 2D data eye
+} AMD_GET_DATAEYE;
+
+AGESA_STATUS
+AmdGet2DDataEye (
+ IN OUT AMD_GET_DATAEYE *AmdGetDataEye
+ );
+
+#define AGESA_IDS_DFT_VAL 0xFFFF ///< Default value of every uninitlized NV item, the action for it will be ignored
+#define AGESA_IDS_NV_END 0xFFFF ///< Flag specify end of option structure
+/// WARNING: Don't change the comment below, it used as signature for script
+/// AGESA IDS NV ID Definitions
+typedef enum {
+ AGESA_IDS_EXT_ID_START = 0x0000,///< 0x0000 specify the start of external NV id
+
+ AGESA_IDS_NV_UCODE, ///< 0x0001 Enable or disable microcode patching
+
+ AGESA_IDS_NV_TARGET_PSTATE, ///< 0x0002 Set the P-state required to be activated
+ AGESA_IDS_NV_POSTPSTATE, ///< 0x0003 Set the P-state required to be activated through POST
+
+ AGESA_IDS_NV_BANK_INTERLEAVE, ///< 0x0004 Enable or disable Bank Interleave
+ AGESA_IDS_NV_CHANNEL_INTERLEAVE, ///< 0x0005 Enable or disable Channel Interleave
+ AGESA_IDS_NV_NODE_INTERLEAVE, ///< 0x0006 Enable or disable Node Interleave
+ AGESA_IDS_NV_MEMHOLE, ///< 0x0007 Enables or disable memory hole
+
+ AGESA_IDS_NV_SCRUB_REDIRECTION, ///< 0x0008 Enable or disable a write to dram with corrected data
+ AGESA_IDS_NV_DRAM_SCRUB, ///< 0x0009 Set the rate of background scrubbing for DRAM
+ AGESA_IDS_NV_DCACHE_SCRUB, ///< 0x000A Set the rate of background scrubbing for the DCache.
+ AGESA_IDS_NV_L2_SCRUB, ///< 0x000B Set the rate of background scrubbing for the L2 cache
+ AGESA_IDS_NV_L3_SCRUB, ///< 0x000C Set the rate of background scrubbing for the L3 cache
+ AGESA_IDS_NV_ICACHE_SCRUB, ///< 0x000D Set the rate of background scrubbing for the Icache
+ AGESA_IDS_NV_SYNC_ON_ECC_ERROR, ///< 0x000E Enable or disable the sync flood on un-correctable ECC error
+ AGESA_IDS_NV_ECC_SYMBOL_SIZE, ///< 0x000F Set ECC symbol size
+
+ AGESA_IDS_NV_ALL_MEMCLKS, ///< 0x0010 Enable or disable all memory clocks enable
+ AGESA_IDS_NV_DCT_GANGING_MODE, ///< 0x0011 Set the Ganged mode
+ AGESA_IDS_NV_DRAM_BURST_LENGTH32, ///< 0x0012 Set the DRAM Burst Length 32
+ AGESA_IDS_NV_MEMORY_POWER_DOWN, ///< 0x0013 Enable or disable Memory power down mode
+ AGESA_IDS_NV_MEMORY_POWER_DOWN_MODE, ///< 0x0014 Set the Memory power down mode
+ AGESA_IDS_NV_DLL_SHUT_DOWN, ///< 0x0015 Enable or disable DLLShutdown
+ AGESA_IDS_NV_ONLINE_SPARE, ///< 0x0016 Enable or disable the Dram controller to designate a DIMM bank as a spare for logical swap
+
+ AGESA_IDS_NV_HDTOUT, ///< 0x0017 Enable or disable HDTOUT feature
+
+ AGESA_IDS_NV_GNBHDAUDIOEN, ///< 0x0018 Enable or disable GNB HD Audio
+
+ AGESA_IDS_NV_CPB_EN, ///< 0x0019 Core Performance Boost
+
+ AGESA_IDS_NV_HTC_EN, ///< 0x001A HTC Enable
+ AGESA_IDS_NV_HTC_OVERRIDE, ///< 0x001B HTC Override
+ AGESA_IDS_NV_HTC_PSTATE_LIMIT, ///< 0x001C HTC P-state limit select
+ AGESA_IDS_NV_HTC_TEMP_HYS, ///< 0x001D HTC Temperature Hysteresis
+ AGESA_IDS_NV_HTC_ACT_TEMP, ///< 0x001E HTC Activation Temp
+
+ AGESA_IDS_NV_POWER_POLICY, ///< 0x001F Select Platform Power Policy
+ AGESA_IDS_NV_DRAMCON, ///< 0x0020 Specify the mode for controller initialization
+ AGESA_IDS_EXT_ID_END, ///< 0x0021 specify the end of external NV ID
+} IDS_EX_NV_ID;
+
+
+#define IDS_NUM_EXT_NV_ITEM (AGESA_IDS_EXT_ID_END - AGESA_IDS_EXT_ID_START + 1)
+
+
+#endif // _AGESA_H_
diff --git a/src/vendorcode/amd/pi/00630F01/AMD.h b/src/vendorcode/amd/pi/00630F01/AMD.h
new file mode 100644
index 0000000..68f7c32
--- /dev/null
+++ b/src/vendorcode/amd/pi/00630F01/AMD.h
@@ -0,0 +1,475 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Agesa structures and definitions
+ *
+ * Contains AMD AGESA core interface
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: Include
+ * @e \$Revision: 281181 $ @e \$Date: 2013-12-18 02:18:55 -0600 (Wed, 18 Dec 2013) $
+ */
+/*****************************************************************************
+ *
+ * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ***************************************************************************/
+
+
+#ifndef _AMD_H_
+#define _AMD_H_
+
+#define Int16FromChar(a,b) (UINT16)((a) << 0 | (b) << 8)
+#define Int32FromChar(a,b,c,d) (UINT32)((a) << 0 | (b) << 8 | (c) << 16 | (d) << 24)
+#define Int64FromChar(a,b,c,d,e,f,g,h) ((UINT64)(Int32FromChar(a,b,c,d)<<32) | (UINT64)Int32FromChar(e,f,g,h))
+
+#define AGESA_REVISION "Arch2008"
+#define AGESA_ID {'A', 'G', 'E', 'S', 'A', 0x00, 0x00, 0x00}
+
+//
+//
+// AGESA Types and Definitions
+//
+//
+#define LAST_ENTRY 0xFFFFFFFFul
+#define IMAGE_SIGNATURE Int32FromChar ('$', 'A', 'M', 'D')
+#define MODULE_SIGNATURE Int32FromChar ('$', 'M', 'O', 'D')
+#define IOCF8 0xCF8
+#define IOCFC 0xCFC
+
+/// The return status for all AGESA public services.
+///
+/// Services return the most severe status of any logged event. Status other than SUCCESS, UNSUPPORTED, and BOUNDS_CHK
+/// will have log entries with more detail.
+///
+typedef enum {
+ AGESA_SUCCESS = 0, ///< The service completed normally. Info may be logged.
+ AGESA_UNSUPPORTED, ///< The dispatcher or create struct had an unimplemented function requested.
+ ///< Not logged.
+ AGESA_BOUNDS_CHK, ///< A dynamic parameter was out of range and the service was not provided.
+ ///< Example, memory address not installed, heap buffer handle not found.
+ ///< Not Logged.
+ // AGESA_STATUS of greater severity (the ones below this line), always have a log entry available.
+ AGESA_ALERT, ///< An observed condition, but no loss of function. See Log.
+ AGESA_WARNING, ///< Possible or minor loss of function. See Log.
+ AGESA_ERROR, ///< Significant loss of function, boot may be possible. See Log.
+ AGESA_CRITICAL, ///< Continue boot only to notify user. See Log.
+ AGESA_FATAL, ///< Halt booting. See Log, however Fatal errors pertaining to heap problems
+ ///< may not be able to reliably produce log events.
+ AgesaStatusMax ///< Not a status, for limit checking.
+} AGESA_STATUS;
+
+/// For checking whether a status is at or above the mandatory log level.
+#define AGESA_STATUS_LOG_LEVEL AGESA_ALERT
+
+/**
+ * Callout method to the host environment.
+ *
+ * Callout using a dispatch with appropriate thunk layer, which is determined by the host environment.
+ *
+ * @param[in] Function The specific callout function being invoked.
+ * @param[in] FcnData Function specific data item.
+ * @param[in,out] ConfigPtr Reference to Callout params.
+ */
+typedef AGESA_STATUS (*CALLOUT_ENTRY) (
+ IN UINT32 Function,
+ IN UINTN FcnData,
+ IN OUT VOID *ConfigPtr
+ );
+
+typedef AGESA_STATUS (*IMAGE_ENTRY) (VOID *ConfigPtr);
+typedef AGESA_STATUS (*MODULE_ENTRY) (VOID *ConfigPtr);
+
+///This allocation type is used by the AmdCreateStruct entry point
+typedef enum {
+ PreMemHeap = 0, ///< Create heap in cache.
+ PostMemDram, ///< Create heap in memory.
+ ByHost ///< Create heap by Host.
+} ALLOCATION_METHOD;
+
+/// These width descriptors are used by the library function, and others, to specify the data size
+typedef enum ACCESS_WIDTH {
+ AccessWidth8 = 1, ///< Access width is 8 bits.
+ AccessWidth16, ///< Access width is 16 bits.
+ AccessWidth32, ///< Access width is 32 bits.
+ AccessWidth64, ///< Access width is 64 bits.
+
+ AccessS3SaveWidth8 = 0x81, ///< Save 8 bits data.
+ AccessS3SaveWidth16, ///< Save 16 bits data.
+ AccessS3SaveWidth32, ///< Save 32 bits data.
+ AccessS3SaveWidth64, ///< Save 64 bits data.
+} ACCESS_WIDTH;
+
+/// AGESA struct name
+typedef enum {
+ // AGESA BASIC FUNCTIONS
+ AMD_INIT_RECOVERY = 0x00021000, ///< AmdInitRecovery entry point handle
+ AMD_CREATE_STRUCT = 0x00022000, ///< AmdCreateStruct handle
+ AMD_INIT_EARLY = 0x00023000, ///< AmdInitEarly entry point handle
+ AMD_INIT_ENV = 0x00024000, ///< AmdInitEnv entry point handle
+ AMD_INIT_LATE = 0x00025000, ///< AmdInitLate entry point handle
+ AMD_INIT_MID = 0x00026000, ///< AmdInitMid entry point handle
+ AMD_INIT_POST = 0x00027000, ///< AmdInitPost entry point handle
+ AMD_INIT_RESET = 0x00028000, ///< AmdInitReset entry point handle
+ AMD_INIT_RESUME = 0x00029000, ///< AmdInitResume entry point handle
+ AMD_RELEASE_STRUCT = 0x0002A000, ///< AmdReleaseStruct handle
+ AMD_S3LATE_RESTORE = 0x0002B000, ///< AmdS3LateRestore entry point handle
+ AMD_S3_SAVE = 0x0002C000, ///< AmdS3Save entry point handle
+ AMD_GET_APIC_ID = 0x0002D000, ///< AmdGetApicId entry point handle
+ AMD_GET_PCI_ADDRESS = 0x0002E000, ///< AmdGetPciAddress entry point handle
+ AMD_IDENTIFY_CORE = 0x0002F000, ///< AmdIdentifyCore general service handle
+ AMD_READ_EVENT_LOG = 0x00030000, ///< AmdReadEventLog general service handle
+ AMD_GET_EXECACHE_SIZE = 0x00031000, ///< AmdGetAvailableExeCacheSize general service handle
+ AMD_LATE_RUN_AP_TASK = 0x00032000, ///< AmdLateRunApTask entry point handle
+ AMD_IDENTIFY_DIMMS = 0x00033000, ///< AmdIdentifyDimm general service handle
+ AMD_GET_2D_DATA_EYE = 0x00034000, ///< AmdGet2DDataEye general service handle
+ AMD_S3FINAL_RESTORE = 0x00035000, ///< AmdS3FinalRestore entry point handle
+ AMD_HEAP_ALLOCATE_BUFFER = 0x00038000,
+ AMD_HEAP_DEALLOCATE_BUFFER = 0x00039000,
+ FCH_INIT_RESET = 0x00040000,
+ FCH_INIT_ENV = 0x00041000,
+ FCH_INIT_MID = 0x00042000,
+ FCH_INIT_LATE = 0x00043000,
+ FCH_INIT_S3_EARLY_RESTORE = 0x00044000,
+ FCH_INIT_S3_LATE_RESTORE = 0x00045000,
+ AMD_SET_VALUE = 0x00081000,
+ AMD_GET_VALUE = 0x00082000,
+} AGESA_STRUCT_NAME;
+
+ /* ResetType constant values */
+#define WARM_RESET_WHENEVER 1
+#define COLD_RESET_WHENEVER 2
+#define WARM_RESET_IMMEDIATELY 3
+#define COLD_RESET_IMMEDIATELY 4
+
+
+// AGESA Structures
+
+/// The standard header for all AGESA services.
+/// For internal AGESA naming conventions, see @ref amdconfigparamname .
+typedef struct {
+ IN VOID * ImageBasePtr; ///< The AGESA Image base address.
+ IN UINT32 Func; ///< The service desired
+ IN VOID * AltImageBasePtr; ///< Alternate Image location
+ IN CALLOUT_ENTRY CalloutPtr; ///< For Callout from AGESA
+ IN UINT8 HeapStatus; ///< For heap status from boot time slide.
+ IN UINT64 HeapBasePtr; ///< Location of the heap
+ IN OUT UINT8 Reserved[7]; ///< This space is reserved for future use.
+} AMD_CONFIG_PARAMS;
+
+
+/// Create Struct Interface.
+typedef struct {
+ IN AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header
+ IN AGESA_STRUCT_NAME AgesaFunctionName; ///< The service to init
+ IN ALLOCATION_METHOD AllocationMethod; ///< How to handle buffer allocation
+ IN OUT UINT32 NewStructSize; ///< The size of the allocated data, in for ByHost, else out only.
+ IN OUT VOID *NewStructPtr; ///< The struct for the service.
+ ///< The struct to init for ByHost allocation,
+ ///< the initialized struct on return.
+} AMD_INTERFACE_PARAMS;
+
+#define FUNC_0 0 // bit-placed for PCI address creation
+#define FUNC_1 1
+#define FUNC_2 2
+#define FUNC_3 3
+#define FUNC_4 4
+#define FUNC_5 5
+#define FUNC_6 6
+#define FUNC_7 7
+
+/// AGESA Binary module header structure
+typedef struct {
+ IN UINT32 Signature; ///< Binary Signature
+ IN CHAR8 CreatorID[8]; ///< 8 characters ID
+ IN CHAR8 Version[12]; ///< 12 characters version
+ IN UINT32 ModuleInfoOffset; ///< Offset of module
+ IN UINT32 EntryPointAddress; ///< Entry address
+ IN UINT32 ImageBase; ///< Image base
+ IN UINT32 RelocTableOffset; ///< Relocate Table offset
+ IN UINT32 ImageSize; ///< Size
+ IN UINT16 Checksum; ///< Checksum
+ IN UINT8 ImageType; ///< Type
+ IN UINT8 V_Reserved; ///< Reserved
+} AMD_IMAGE_HEADER;
+
+/// AGESA Binary module header structure
+typedef struct _AMD_MODULE_HEADER {
+ IN UINT32 ModuleHeaderSignature; ///< Module signature
+ IN CHAR8 ModuleIdentifier[8]; ///< 8 characters ID
+ IN CHAR8 ModuleVersion[12]; ///< 12 characters version
+ IN VOID *ModuleDispatcher; ///< A pointer point to dispatcher
+ IN struct _AMD_MODULE_HEADER *NextBlock; ///< Next module header link
+} AMD_MODULE_HEADER;
+
+// AMD_CODE_HEADER Signatures.
+#define AGESA_CODE_SIGNATURE {'!', '!', '!', 'A', 'G', 'E', 'S', 'A'}
+#define CIMXNB_CODE_SIGNATURE {'!', '!', 'C', 'I', 'M', 'X', 'N', 'B'}
+#define CIMXSB_CODE_SIGNATURE {'!', '!', 'C', 'I', 'M', 'X', 'S', 'B'}
+
+/// AGESA_CODE_SIGNATURE
+typedef struct {
+ IN CHAR8 Signature[8]; ///< code header Signature
+ IN CHAR8 ComponentName[16]; ///< 16 character name of the code module
+ IN CHAR8 Version[12]; ///< 12 character version string
+ IN CHAR8 TerminatorNull; ///< null terminated string
+ IN CHAR8 VerReserved[7]; ///< reserved space
+} AMD_CODE_HEADER;
+
+/// Extended PCI address format
+typedef struct {
+ IN OUT UINT32 Register:12; ///< Register offset
+ IN OUT UINT32 Function:3; ///< Function number
+ IN OUT UINT32 Device:5; ///< Device number
+ IN OUT UINT32 Bus:8; ///< Bus number
+ IN OUT UINT32 Segment:4; ///< Segment
+} EXT_PCI_ADDR;
+
+/// Union type for PCI address
+typedef union _PCI_ADDR {
+ IN UINT32 AddressValue; ///< Formal address
+ IN EXT_PCI_ADDR Address; ///< Extended address
+} PCI_ADDR;
+
+// SBDFO - Segment Bus Device Function Offset
+// 31:28 Segment (4-bits)
+// 27:20 Bus (8-bits)
+// 19:15 Device (5-bits)
+// 14:12 Function(3-bits)
+// 11:00 Offset (12-bits)
+
+#define MAKE_SBDFO(Seg, Bus, Dev, Fun, Off) ((((UINT32) (Seg)) << 28) | (((UINT32) (Bus)) << 20) | \
+ (((UINT32)(Dev)) << 15) | (((UINT32)(Fun)) << 12) | ((UINT32)(Off)))
+#define ILLEGAL_SBDFO 0xFFFFFFFFul
+
+/// CPUID data received registers format
+typedef struct {
+ OUT UINT32 EAX_Reg; ///< CPUID instruction result in EAX
+ OUT UINT32 EBX_Reg; ///< CPUID instruction result in EBX
+ OUT UINT32 ECX_Reg; ///< CPUID instruction result in ECX
+ OUT UINT32 EDX_Reg; ///< CPUID instruction result in EDX
+} CPUID_DATA;
+
+// Topology Services definitions and macros
+#define TOPOLOGY_LIST_TERMINAL 0xFF ///< End of list.
+
+
+#ifndef BIT0
+ #define BIT0 0x0000000000000001ull
+#endif
+#ifndef BIT1
+ #define BIT1 0x0000000000000002ull
+#endif
+#ifndef BIT2
+ #define BIT2 0x0000000000000004ull
+#endif
+#ifndef BIT3
+ #define BIT3 0x0000000000000008ull
+#endif
+#ifndef BIT4
+ #define BIT4 0x0000000000000010ull
+#endif
+#ifndef BIT5
+ #define BIT5 0x0000000000000020ull
+#endif
+#ifndef BIT6
+ #define BIT6 0x0000000000000040ull
+#endif
+#ifndef BIT7
+ #define BIT7 0x0000000000000080ull
+#endif
+#ifndef BIT8
+ #define BIT8 0x0000000000000100ull
+#endif
+#ifndef BIT9
+ #define BIT9 0x0000000000000200ull
+#endif
+#ifndef BIT10
+ #define BIT10 0x0000000000000400ull
+#endif
+#ifndef BIT11
+ #define BIT11 0x0000000000000800ull
+#endif
+#ifndef BIT12
+ #define BIT12 0x0000000000001000ull
+#endif
+#ifndef BIT13
+ #define BIT13 0x0000000000002000ull
+#endif
+#ifndef BIT14
+ #define BIT14 0x0000000000004000ull
+#endif
+#ifndef BIT15
+ #define BIT15 0x0000000000008000ull
+#endif
+#ifndef BIT16
+ #define BIT16 0x0000000000010000ull
+#endif
+#ifndef BIT17
+ #define BIT17 0x0000000000020000ull
+#endif
+#ifndef BIT18
+ #define BIT18 0x0000000000040000ull
+#endif
+#ifndef BIT19
+ #define BIT19 0x0000000000080000ull
+#endif
+#ifndef BIT20
+ #define BIT20 0x0000000000100000ull
+#endif
+#ifndef BIT21
+ #define BIT21 0x0000000000200000ull
+#endif
+#ifndef BIT22
+ #define BIT22 0x0000000000400000ull
+#endif
+#ifndef BIT23
+ #define BIT23 0x0000000000800000ull
+#endif
+#ifndef BIT24
+ #define BIT24 0x0000000001000000ull
+#endif
+#ifndef BIT25
+ #define BIT25 0x0000000002000000ull
+#endif
+#ifndef BIT26
+ #define BIT26 0x0000000004000000ull
+#endif
+#ifndef BIT27
+ #define BIT27 0x0000000008000000ull
+#endif
+#ifndef BIT28
+ #define BIT28 0x0000000010000000ull
+#endif
+#ifndef BIT29
+ #define BIT29 0x0000000020000000ull
+#endif
+#ifndef BIT30
+ #define BIT30 0x0000000040000000ull
+#endif
+#ifndef BIT31
+ #define BIT31 0x0000000080000000ull
+#endif
+#ifndef BIT32
+ #define BIT32 0x0000000100000000ull
+#endif
+#ifndef BIT33
+ #define BIT33 0x0000000200000000ull
+#endif
+#ifndef BIT34
+ #define BIT34 0x0000000400000000ull
+#endif
+#ifndef BIT35
+ #define BIT35 0x0000000800000000ull
+#endif
+#ifndef BIT36
+ #define BIT36 0x0000001000000000ull
+#endif
+#ifndef BIT37
+ #define BIT37 0x0000002000000000ull
+#endif
+#ifndef BIT38
+ #define BIT38 0x0000004000000000ull
+#endif
+#ifndef BIT39
+ #define BIT39 0x0000008000000000ull
+#endif
+#ifndef BIT40
+ #define BIT40 0x0000010000000000ull
+#endif
+#ifndef BIT41
+ #define BIT41 0x0000020000000000ull
+#endif
+#ifndef BIT42
+ #define BIT42 0x0000040000000000ull
+#endif
+#ifndef BIT43
+ #define BIT43 0x0000080000000000ull
+#endif
+#ifndef BIT44
+ #define BIT44 0x0000100000000000ull
+#endif
+#ifndef BIT45
+ #define BIT45 0x0000200000000000ull
+#endif
+#ifndef BIT46
+ #define BIT46 0x0000400000000000ull
+#endif
+#ifndef BIT47
+ #define BIT47 0x0000800000000000ull
+#endif
+#ifndef BIT48
+ #define BIT48 0x0001000000000000ull
+#endif
+#ifndef BIT49
+ #define BIT49 0x0002000000000000ull
+#endif
+#ifndef BIT50
+ #define BIT50 0x0004000000000000ull
+#endif
+#ifndef BIT51
+ #define BIT51 0x0008000000000000ull
+#endif
+#ifndef BIT52
+ #define BIT52 0x0010000000000000ull
+#endif
+#ifndef BIT53
+ #define BIT53 0x0020000000000000ull
+#endif
+#ifndef BIT54
+ #define BIT54 0x0040000000000000ull
+#endif
+#ifndef BIT55
+ #define BIT55 0x0080000000000000ull
+#endif
+#ifndef BIT56
+ #define BIT56 0x0100000000000000ull
+#endif
+#ifndef BIT57
+ #define BIT57 0x0200000000000000ull
+#endif
+#ifndef BIT58
+ #define BIT58 0x0400000000000000ull
+#endif
+#ifndef BIT59
+ #define BIT59 0x0800000000000000ull
+#endif
+#ifndef BIT60
+ #define BIT60 0x1000000000000000ull
+#endif
+#ifndef BIT61
+ #define BIT61 0x2000000000000000ull
+#endif
+#ifndef BIT62
+ #define BIT62 0x4000000000000000ull
+#endif
+#ifndef BIT63
+ #define BIT63 0x8000000000000000ull
+#endif
+
+#endif // _AMD_H_
diff --git a/src/vendorcode/amd/pi/00630F01/Dispatcher.h b/src/vendorcode/amd/pi/00630F01/Dispatcher.h
new file mode 100644
index 0000000..d14b419
--- /dev/null
+++ b/src/vendorcode/amd/pi/00630F01/Dispatcher.h
@@ -0,0 +1,51 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD Pushhigh Interface
+ *
+ * Contains interface to Pushhigh entry
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: Legacy
+ * @e \$Revision: 281181 $ @e \$Date: 2013-12-18 02:18:55 -0600 (Wed, 18 Dec 2013) $
+ *
+ */
+/*****************************************************************************
+ *
+ * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ***************************************************************************
+ */
+
+#ifndef _DISPATCHER_H_
+#define _DISPATCHER_H_
+
+// AGESA function prototypes
+AGESA_STATUS CALLCONV AmdAgesaDispatcher ( IN OUT VOID *ConfigPtr );
+AGESA_STATUS CALLCONV AmdAgesaCallout ( IN UINT32 Func, IN UINT32 Data, IN OUT VOID *ConfigPtr );
+
+#endif // _DISPATCHER_H_
diff --git a/src/vendorcode/amd/pi/00630F01/Include/Filecode.h b/src/vendorcode/amd/pi/00630F01/Include/Filecode.h
new file mode 100644
index 0000000..af31c46
--- /dev/null
+++ b/src/vendorcode/amd/pi/00630F01/Include/Filecode.h
@@ -0,0 +1,781 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Collectively assign unique filecodes for assert and debug to each source file.
+ *
+ * Publish values for decorated filenames, which can be used for
+ * ASSERT and debug support using a preprocessor define like:
+ * @n <tt> \#define FILECODE MY_C_FILENAME_FILECODE </tt> @n
+ * This file serves as a reference for debugging to associate the code and filename.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: Include
+ * @e \$Revision: 284995 $ @e \$Date: 2014-02-17 11:17:41 -0600 (Mon, 17 Feb 2014) $
+ */
+/*****************************************************************************
+ *
+ * Copyright (c) 2008 - 2014, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ***************************************************************************/
+
+#ifndef _FILECODE_H_
+#define _FILECODE_H_
+
+#define UNASSIGNED_FILE_FILECODE (0xFFFF)
+
+/// For debug use in any Platform's options C file.
+/// Can be reused for platforms and image builds, since only one options file can be built.
+#define PLATFORM_SPECIFIC_OPTIONS_FILECODE (0xBBBB)
+
+
+#define PROC_GNB_COMMON_GNBLIBFEATURES_FILECODE (0xA001)
+#define PROC_GNB_GNBINITATEARLY_FILECODE (0xA017)
+#define PROC_GNB_GNBINITATENV_FILECODE (0xA020)
+#define PROC_GNB_GNBINITATLATE_FILECODE (0xA021)
+#define PROC_GNB_GNBINITATMID_FILECODE (0xA022)
+#define PROC_GNB_GNBINITATPOST_FILECODE (0xA023)
+#define PROC_GNB_GNBINITATRESET_FILECODE (0xA024)
+#define PROC_GNB_MODULES_GNBCOMMONLIB_GNBLIB_FILECODE (0xA025)
+#define PROC_GNB_MODULES_GNBCOMMONLIB_GNBLIBCPUACC_FILECODE (0xA026)
+#define PROC_GNB_MODULES_GNBCOMMONLIB_GNBLIBHEAP_FILECODE (0xA027)
+#define PROC_GNB_MODULES_GNBCOMMONLIB_GNBLIBIOACC_FILECODE (0xA028)
+#define PROC_GNB_MODULES_GNBCOMMONLIB_GNBLIBMEMACC_FILECODE (0xA029)
+#define PROC_GNB_MODULES_GNBCOMMONLIB_GNBLIBPCI_FILECODE (0xA02A)
+#define PROC_GNB_MODULES_GNBCOMMONLIB_GNBLIBPCIACC_FILECODE (0xA030)
+#define PROC_GNB_MODULES_GNBGFXINITLIBV1_GFXCARDINFO_FILECODE (0xA031)
+#define PROC_GNB_MODULES_GNBGFXINITLIBV1_GFXENUMCONNECTORS_FILECODE (0xA032)
+#define PROC_GNB_MODULES_GNBGFXINITLIBV1_GFXPOWERPLAYTABLE_FILECODE (0xA033)
+#define PROC_GNB_MODULES_GNBNBINITLIBV1_GNBNBINITLIBV1_FILECODE (0xA034)
+#define PROC_GNB_MODULES_GNBPCIEALIBV1_PCIEALIB_FILECODE (0xA035)
+#define PROC_GNB_MODULES_GNBPCIECONFIG_PCIECONFIGDATA_FILECODE (0xA036)
+#define PROC_GNB_MODULES_GNBPCIECONFIG_PCIECONFIGLIB_FILECODE (0xA037)
+#define PROC_GNB_MODULES_GNBPCIECONFIG_PCIEINPUTPARSER_FILECODE (0xA038)
+#define PROC_GNB_MODULES_GNBPCIECONFIG_PCIEMAPTOPOLOGY_FILECODE (0xA039)
+#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEASPMBLACKLIST_FILECODE (0xA03B)
+#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEASPMEXITLATENCY_FILECODE (0xA03C)
+#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEPHYSERVICES_FILECODE (0xA03D)
+#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEPIFSERVICES_FILECODE (0xA03E)
+#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEPORTREGACC_FILECODE (0xA03F)
+#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEPORTSERVICES_FILECODE (0xA041)
+#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEPOWERMGMT_FILECODE (0xA043)
+#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIESILICONSERVICES_FILECODE (0xA045)
+#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIETIMER_FILECODE (0xA046)
+#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIETOPOLOGYSERVICES_FILECODE (0xA047)
+#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEUTILITYLIB_FILECODE (0xA048)
+#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEWRAPPERREGACC_FILECODE (0xA049)
+#define PROC_GNB_MODULES_GNBPCIETRAININGV1_PCIETRAINING_FILECODE (0xA04A)
+#define PROC_GNB_MODULES_GNBPCIETRAININGV1_PCIEWORKAROUNDS_FILECODE (0xA04B)
+#define PROC_GNB_MODULES_GNBPCIECOMMCLKCFG_PCIECOMMCLKCFG_FILECODE (0xA04C)
+
+#define PROC_GNB_MODULES_GNBGFXCONFIG_GFXCONFIGENV_FILECODE (0xA08E)
+#define PROC_GNB_MODULES_GNBGFXCONFIG_GFXCONFIGPOST_FILECODE (0xA08F)
+#define PROC_GNB_MODULES_GNBTABLE_GNBTABLE_FILECODE (0xA090)
+#define PROC_GNB_MODULES_GNBGFXINITLIBV1_GNBGFXINITLIBV1_FILECODE (0xA091)
+#define PROC_GNB_MODULES_GNBINITTN_GFXENVINITTN_FILECODE (0xA092)
+#define PROC_GNB_MODULES_GNBGFXCONFIG_GFXCONFIGLIB_FILECODE (0xA093)
+#define PROC_GNB_MODULES_GNBINITTN_GFXGMCINITTN_FILECODE (0xA094)
+#define PROC_GNB_MODULES_GNBINITTN_GFXINTEGRATEDINFOTABLETN_FILECODE (0xA095)
+#define PROC_GNB_MODULES_GNBINITTN_GFXLIBTN_FILECODE (0xA096)
+#define PROC_GNB_MODULES_GNBINITTN_GFXMIDINITTN_FILECODE (0xA097)
+#define PROC_GNB_MODULES_GNBINITTN_GNBPOSTINITTN_FILECODE (0xA098)
+#define PROC_GNB_MODULES_GNBINITTN_GNBEARLYINITTN_FILECODE (0xA09A)
+#define PROC_GNB_MODULES_GNBINITTN_GNBENVINITTN_FILECODE (0xA09B)
+#define PROC_GNB_MODULES_GNBINITTN_GNBFUSETABLETN_FILECODE (0xA09C)
+#define PROC_GNB_MODULES_GNBINITTN_GNBMIDINITTN_FILECODE (0xA09D)
+#define PROC_GNB_MODULES_GNBINITTN_GFXPOSTINITTN_FILECODE (0xA09E)
+#define PROC_GNB_MODULES_GNBINITTN_GNBREGISTERACCTN_FILECODE (0xA09F)
+#define PROC_GNB_MODULES_GNBINITTN_PCIECONFIGTN_FILECODE (0xA0A0)
+#define PROC_GNB_MODULES_GNBINITTN_PCIEEARLYINITTN_FILECODE (0xA0A1)
+#define PROC_GNB_MODULES_GNBINITTN_PCIEENVINITTN_FILECODE (0xA0A2)
+#define PROC_GNB_MODULES_GNBINITTN_PCIELIBTN_FILECODE (0xA0A3)
+#define PROC_GNB_MODULES_GNBINITTN_PCIEMIDINITTN_FILECODE (0xA0A4)
+#define PROC_GNB_MODULES_GNBINITTN_PCIEPOSTINITTN_FILECODE (0xA0A5)
+#define PROC_GNB_MODULES_GNBPCIEINITLIBV4_PCIEWRAPPERSERVICESV4_FILECODE (0xA0A6)
+#define PROC_GNB_MODULES_GNBIOMMUIVRS_GNBIOMMUIVRS_FILECODE (0xA0A7)
+#define PROC_GNB_MODULES_GNBIVRSLIB_GNBIVRSLIB_FILECODE (0xA0A8)
+#define PROC_GNB_MODULES_GNBNBINITLIBV4_GNBNBINITLIBV4_FILECODE (0xA0A9)
+#define PROC_GNB_MODULES_GNBFAMTRANSLATION_GNBPCIETRANSLATION_FILECODE (0xA0AA)
+#define PROC_GNB_MODULES_GNBINITTN_GNBIOMMUIVRSTN_FILECODE (0xA0AB)
+
+#define PROC_GNB_MODULES_GNBINITTN_PCIEPOWERGATETN_FILECODE (0xA0B8)
+#define PROC_GNB_MODULES_GNBINITTN_PCIEALIBTNFS1_FILECODE (0xA0B9)
+#define PROC_GNB_MODULES_GNBSBLIB_GNBSBPCIE_FILECODE (0xA0BA)
+#define PROC_GNB_MODULES_GNBSBLIB_GNBSBLIB_FILECODE (0xA0BB)
+#define PROC_GNB_MODULES_GNBSBIOMMULIB_GNBSBIOMMULIB_FILECODE (0xA0BC)
+#define PROC_GNB_MODULES_GNBCOMMONLIB_GNBTIMERLIB_FILECODE (0xA0BD)
+#define PROC_GNB_MODULES_GNBSSOCKETLIB_GNBSSOCKETLIB_FILECODE (0xA0BF)
+#define PROC_GNB_MODULES_GNBPCIECONFIG_GNBHANDLELIB_FILECODE (0xA0C0)
+#define PROC_GNB_MODULES_GNBINITTN_GNBBAPMCOEFFCALCTN_FILECODE (0xA0C1)
+#define PROC_GNB_MODULES_GNBPCIEASPM_PCIEASPM_FILECODE (0xA0C2)
+
+#define PROC_GNB_MODULES_GNBPCIEINITLIBV5_PCIEASPMEXITLATENCYV5_FILECODE (0xA0C5)
+#define PROC_GNB_MODULES_GNBPCIEINITLIBV5_PCIEPIFSERVICESV5_FILECODE (0xA0C6)
+#define PROC_GNB_MODULES_GNBPCIEINITLIBV5_PCIEPORTSERVICESV5_FILECODE (0xA0C7)
+#define PROC_GNB_MODULES_GNBPCIEINITLIBV5_PCIEPOWERMGMTV5_FILECODE (0xA0C8)
+#define PROC_GNB_MODULES_GNBPCIEINITLIBV5_PCIESILICONSERVICESV5_FILECODE (0xA0C9)
+#define PROC_GNB_MODULES_GNBPCIEINITLIBV5_PCIEWRAPPERSERVICESV5_FILECODE (0xA0CA)
+#define PROC_GNB_MODULES_GNBNBINITLIBV5_GNBNBINITLIBV5_FILECODE (0xA0CB)
+
+#define PROC_GNB_MODULES_GNBFAMTRANSLATION_GNBTRANSLATION_FILECODE (0xA0DB)
+#define PROC_GNB_MODULES_GNBPCIEINITLIBV4_PCIEPOWERMGMTV4_FILECODE (0xA0DC)
+#define PROC_GNB_MODULES_GNBPCIEINITLIBV4_PCIEPORTSERVICESV4_FILECODE (0xA0DD)
+
+#define PROC_GNB_MODULES_GNBINITTN_PCIEALIBTNFM2_FILECODE (0xA0DF)
+#define PROC_GNB_MODULES_GNBGFXCONFIG_GFXCONFIGMID_FILECODE (0xA0E0)
+
+#define PROC_GNB_MODULES_GNBIOAPIC_GNBIOAPIC_FILECODE (0xA0EE)
+
+#define PROC_GNB_MODULES_GNBPCIEMAXPAYLOAD_PCIEMAXPAYLOAD_FILECODE (0xA0F4)
+#define PROC_GNB_MODULES_GNBPCIECLKPM_PCIECLKPM_FILECODE (0xA0F5)
+
+#define PROC_GNB_MODULES_GNBPCIEINITLIBV5_PCIETOPOLOGYSERVICESV5_FILECODE (0xA100)
+#define PROC_GNB_MODULES_GNBPCIETRAININGV2_PCIETRAININGV2_FILECODE (0xA101)
+#define PROC_GNB_MODULES_GNBPCIETRAININGV2_PCIEWORKAROUNDSV2_FILECODE (0xA102)
+
+#define PROC_RECOVERY_GNB_GNBRECOVERY_FILECODE (0xAE01)
+#define PROC_RECOVERY_GNB_NBINITRECOVERY_FILECODE (0xAE02)
+#define PROC_GNB_GNBINITATS3SAVE_FILECODE (0xAE03)
+#define PROC_GNB_MODULES_GNBSVIEW_GNBSVIEW_FILECODE (0xAE04)
+
+#define PROC_GNB_MODULES_GNBINITKV_GFXENVINITKV_FILECODE (0xAE05)
+#define PROC_GNB_MODULES_GNBINITKV_GFXINTEGRATEDINFOTABLEKV_FILECODE (0xAE06)
+#define PROC_GNB_MODULES_GNBINITKV_GFXMIDINITKV_FILECODE (0xAE07)
+#define PROC_GNB_MODULES_GNBINITKV_GFXPOSTINITKV_FILECODE (0xAE08)
+#define PROC_GNB_MODULES_GNBINITKV_GNBEARLYINITKV_FILECODE (0xAE09)
+#define PROC_GNB_MODULES_GNBINITKV_GNBENVINITKV_FILECODE (0xAE0A)
+#define PROC_GNB_MODULES_GNBINITKV_GNBIOMMUIVRSKV_FILECODE (0xAE0B)
+#define PROC_GNB_MODULES_GNBINITKV_GNBMIDINITKV_FILECODE (0xAE0C)
+#define PROC_GNB_MODULES_GNBINITKV_GNBPOSTINITKV_FILECODE (0xAE0D)
+#define PROC_GNB_MODULES_GNBINITKV_GNBREGISTERACCKV_FILECODE (0xAE0E)
+#define PROC_GNB_MODULES_GNBINITKV_PCIECOMPLEXDATAKV_FILECODE (0xAE0F)
+#define PROC_GNB_MODULES_GNBINITKV_PCIECONFIGKV_FILECODE (0xAE10)
+#define PROC_GNB_MODULES_GNBINITKV_PCIEEARLYINITKV_FILECODE (0xAE11)
+#define PROC_GNB_MODULES_GNBINITKV_PCIEENVINITKV_FILECODE (0xAE12)
+#define PROC_GNB_MODULES_GNBINITKV_PCIELIBKV_FILECODE (0xAE13)
+#define PROC_GNB_MODULES_GNBINITKV_PCIEMIDINITKV_FILECODE (0xAE14)
+#define PROC_GNB_MODULES_GNBINITKV_PCIEPOSTINITKV_FILECODE (0xAE15)
+#define PROC_GNB_MODULES_GNBINITKV_GFXLIBKV_FILECODE (0xAE16)
+#define PROC_GNB_MODULES_GNBIOMMUSCRATCH_GNBIOMMUSCRATCH_FILECODE (0xAE18)
+#define PROC_GNB_MODULES_GNBINITKV_GFXGMCINITKV_FILECODE (0xAE19)
+#define PROC_GNB_MODULES_GNBSMULIBV7_GNBSMUINITLIBV7_FILECODE (0xAE1A)
+#define PROC_GNB_MODULES_GNBINITKV_GNBSMUBIOSTABLEKV_FILECODE (0xAE1B)
+#define PROC_GNB_MODULES_GNBINITKV_PCIEPOWERGATEKV_FILECODE (0xAE1C)
+
+#define PROC_GNB_MODULES_GNBPCIEALIBV2_PCIEALIBV2_FILECODE (0xAE33)
+#define PROC_GNB_MODULES_GNBINITKV_ALIBKVD_FILECODE (0xAE34)
+#define PROC_GNB_MODULES_GNBINITKV_ALIBKVM_FILECODE (0xAE35)
+#define PROC_GNB_MODULES_GNBINITKV_GNBFUSETABLEKV_FILECODE (0xAE39)
+#define PROC_GNB_MODULES_GNBURALIBV1_GNBURALIBV1_FILECODE (0xAE3A)
+#define PROC_GNB_MODULES_GNBINITKV_GNBURAKV_FILECODE (0xAE3B)
+#define PROC_GNB_MODULES_GNBINITKV_GNBURATOKENMAPKV_FILECODE (0xAE3C)
+#define PROC_GNB_MODULES_GNBGFXINTTABLEV3_GFXLIBV3_FILECODE (0xAE41)
+#define PROC_GNB_MODULES_GNBGFXINTTABLEV3_GFXINTEGRATEDINFOTABLE_FILECODE (0xAE42)
+#define PROC_GNB_MODULES_GNBGFXINTTABLEV3_GFXPWRPLAYTABLE_FILECODE (0xAE43)
+#define PROC_GNB_MODULES_GNBSCSLIBV1_GNBSCSLIBV1_FILECODE (0xAE44)
+
+// FCH
+#define PROC_FCH_AZALIA_AZALIARESET_FILECODE (0xB001)
+#define PROC_FCH_AZALIA_AZALIAENV_FILECODE (0xB002)
+#define PROC_FCH_AZALIA_AZALIAMID_FILECODE (0xB003)
+#define PROC_FCH_AZALIA_AZALIALATE_FILECODE (0xB004)
+#define PROC_FCH_COMMON_ACPILIB_FILECODE (0xB010)
+#define PROC_FCH_COMMON_FCHLIB_FILECODE (0xB011)
+#define PROC_FCH_COMMON_FCHCOMMON_FILECODE (0xB012)
+#define PROC_FCH_COMMON_FCHCOMMONSMM_FILECODE (0xB013)
+#define PROC_FCH_COMMON_MEMLIB_FILECODE (0xB014)
+#define PROC_FCH_COMMON_PCILIB_FILECODE (0xB015)
+#define PROC_FCH_COMMON_FCHPELIB_FILECODE (0xB016)
+#define PROC_FCH_GEC_GECRESET_FILECODE (0xB020)
+#define PROC_FCH_GEC_GECENV_FILECODE (0xB021)
+#define PROC_FCH_GEC_GECMID_FILECODE (0xB022)
+#define PROC_FCH_GEC_GECLATE_FILECODE (0xB023)
+#define PROC_FCH_GEC_FAMILY_HUDSON2_HUDSON2GECSERVICE_FILECODE (0xB024)
+#define PROC_FCH_GEC_FAMILY_HUDSON2_HUDSON2GECENVSERVICE_FILECODE (0xB025)
+#define PROC_FCH_HWACPI_HWACPIRESET_FILECODE (0xB030)
+#define PROC_FCH_HWACPI_HWACPIENV_FILECODE (0xB031)
+#define PROC_FCH_HWACPI_HWACPIMID_FILECODE (0xB032)
+#define PROC_FCH_HWACPI_HWACPILATE_FILECODE (0xB033)
+#define PROC_FCH_HWACPI_FAMILY_HUDSON2_HUDSON2HWACPIENVSERVICE_FILECODE (0xB034)
+#define PROC_FCH_HWACPI_FAMILY_HUDSON2_HUDSON2HWACPIMIDSERVICE_FILECODE (0xB035)
+#define PROC_FCH_HWACPI_FAMILY_HUDSON2_HUDSON2HWACPILATESERVICE_FILECODE (0xB036)
+#define PROC_FCH_HWACPI_FAMILY_HUDSON2_HUDSON2SSSERVICE_FILECODE (0xB037)
+#define PROC_FCH_HWM_HWMRESET_FILECODE (0xB050)
+#define PROC_FCH_HWM_HWMENV_FILECODE (0xB051)
+#define PROC_FCH_HWM_HWMMID_FILECODE (0xB052)
+#define PROC_FCH_HWM_HWMLATE_FILECODE (0xB053)
+#define PROC_FCH_HWM_FAMILY_HUDSON2_HUDSON2HWMENVSERVICE_FILECODE (0xB054)
+#define PROC_FCH_HWM_FAMILY_HUDSON2_HUDSON2HWMMIDSERVICE_FILECODE (0xB055)
+#define PROC_FCH_HWM_FAMILY_HUDSON2_HUDSON2HWMLATESERVICE_FILECODE (0xB056)
+#define PROC_FCH_IMC_IMCENV_FILECODE (0xB060)
+#define PROC_FCH_IMC_IMCMID_FILECODE (0xB061)
+#define PROC_FCH_IMC_IMCLATE_FILECODE (0xB062)
+#define PROC_FCH_IMC_IMCLIB_FILECODE (0xB063)
+#define PROC_FCH_IMC_IMCRESET_FILECODE (0xB064)
+#define PROC_FCH_IMC_FCHECENV_FILECODE (0xB065)
+#define PROC_FCH_IMC_FCHECMID_FILECODE (0xB066)
+#define PROC_FCH_IMC_FCHECLATE_FILECODE (0xB067)
+#define PROC_FCH_IMC_FCHECRESET_FILECODE (0xB068)
+#define PROC_FCH_IMC_FAMILY_HUDSON2_HUDSON2IMCSERVICE_FILECODE (0xB069)
+#define PROC_FCH_IDE_IDEENV_FILECODE (0xB06D)
+#define PROC_FCH_IDE_IDEMID_FILECODE (0xB06E)
+#define PROC_FCH_IDE_IDELATE_FILECODE (0xB06F)
+#define PROC_FCH_INTERFACE_INITRESETDEF_FILECODE (0xB070)
+#define PROC_FCH_INTERFACE_INITENVDEF_FILECODE (0xB071)
+#define PROC_FCH_INTERFACE_FCHINITRESET_FILECODE (0xB072)
+#define PROC_FCH_INTERFACE_FCHINITENV_FILECODE (0xB073)
+#define PROC_FCH_INTERFACE_FCHINITLATE_FILECODE (0xB074)
+#define PROC_FCH_INTERFACE_FCHINITMID_FILECODE (0xB075)
+#define PROC_FCH_INTERFACE_FCHINITS3_FILECODE (0xB076)
+#define PROC_FCH_INTERFACE_FCHTASKLAUNCHER_FILECODE (0xB077)
+#define PROC_FCH_IR_IRENV_FILECODE (0xB080)
+#define PROC_FCH_IR_IRMID_FILECODE (0xB081)
+#define PROC_FCH_IR_IRLATE_FILECODE (0xB082)
+#define PROC_FCH_PCIB_PCIBRESET_FILECODE (0xB090)
+#define PROC_FCH_PCIB_PCIBENV_FILECODE (0xB091)
+#define PROC_FCH_PCIB_PCIBMID_FILECODE (0xB092)
+#define PROC_FCH_PCIB_PCIBLATE_FILECODE (0xB093)
+#define PROC_FCH_PCIE_ABRESET_FILECODE (0xB0A0)
+#define PROC_FCH_PCIE_ABENV_FILECODE (0xB0A1)
+#define PROC_FCH_PCIE_ABMID_FILECODE (0xB0A2)
+#define PROC_FCH_PCIE_ABLATE_FILECODE (0xB0A3)
+#define PROC_FCH_PCIE_GPPHP_FILECODE (0xB0A4)
+#define PROC_FCH_PCIE_GPPLIB_FILECODE (0xB0A5)
+#define PROC_FCH_PCIE_GPPRESET_FILECODE (0xB0A6)
+#define PROC_FCH_PCIE_GPPENV_FILECODE (0xB0A7)
+#define PROC_FCH_PCIE_GPPMID_FILECODE (0xB0A8)
+#define PROC_FCH_PCIE_GPPLATE_FILECODE (0xB0A9)
+#define PROC_FCH_PCIE_PCIERESET_FILECODE (0xB0AA)
+#define PROC_FCH_PCIE_PCIEENV_FILECODE (0xB0AB)
+#define PROC_FCH_PCIE_PCIEMID_FILECODE (0xB0AC)
+#define PROC_FCH_PCIE_PCIELATE_FILECODE (0xB0AD)
+#define PROC_FCH_PCIE_FAMILY_HUDSON2_HUDSON2ABRESETSERVICE_FILECODE (0xB0AE)
+#define PROC_FCH_PCIE_FAMILY_HUDSON2_HUDSON2ABENVSERVICE_FILECODE (0xB0AF)
+#define PROC_FCH_PCIE_FAMILY_HUDSON2_HUDSON2ABSERVICE_FILECODE (0xB0B0)
+#define PROC_FCH_PCIE_FAMILY_HUDSON2_HUDSON2GPPRESETSERVICE_FILECODE (0xB0B1)
+#define PROC_FCH_PCIE_FAMILY_HUDSON2_HUDSON2GPPSERVICE_FILECODE (0xB0B2)
+#define PROC_FCH_PCIE_FAMILY_HUDSON2_HUDSON2PCIEENVSERVICE_FILECODE (0xB0B3)
+#define PROC_FCH_PCIE_FAMILY_HUDSON2_HUDSON2PCIESERVICE_FILECODE (0xB0B4)
+#define PROC_FCH_SATA_AHCIENV_FILECODE (0xB0C0)
+#define PROC_FCH_SATA_AHCIMID_FILECODE (0xB0C1)
+#define PROC_FCH_SATA_AHCILATE_FILECODE (0xB0C2)
+#define PROC_FCH_SATA_AHCILIB_FILECODE (0xB0C3)
+#define PROC_FCH_SATA_IDE2AHCIENV_FILECODE (0xB0C4)
+#define PROC_FCH_SATA_IDE2AHCIMID_FILECODE (0xB0C5)
+#define PROC_FCH_SATA_IDE2AHCILATE_FILECODE (0xB0C6)
+#define PROC_FCH_SATA_IDE2AHCILIB_FILECODE (0xB0C7)
+#define PROC_FCH_SATA_RAIDENV_FILECODE (0xB0C8)
+#define PROC_FCH_SATA_RAIDMID_FILECODE (0xB0C9)
+#define PROC_FCH_SATA_RAIDLATE_FILECODE (0xB0CA)
+#define PROC_FCH_SATA_RAIDLIB_FILECODE (0xB0CB)
+#define PROC_FCH_SATA_SATAENV_FILECODE (0xB0CC)
+#define PROC_FCH_SATA_SATAENVLIB_FILECODE (0xB0CD)
+#define PROC_FCH_SATA_SATAIDEENV_FILECODE (0xB0CE)
+#define PROC_FCH_SATA_SATAIDEMID_FILECODE (0xB0CF)
+#define PROC_FCH_SATA_SATAIDELATE_FILECODE (0xB0D0)
+#define PROC_FCH_SATA_SATAIDELIB_FILECODE (0xB0D1)
+#define PROC_FCH_SATA_SATAMID_FILECODE (0xB0D2)
+#define PROC_FCH_SATA_SATALATE_FILECODE (0xB0D3)
+#define PROC_FCH_SATA_SATALIB_FILECODE (0xB0D4)
+#define PROC_FCH_SATA_SATARESET_FILECODE (0xB0D5)
+#define PROC_FCH_SATA_FAMILY_HUDSON2_HUDSON2SATARESETSERVICE_FILECODE (0xB0D6)
+#define PROC_FCH_SATA_FAMILY_HUDSON2_HUDSON2SATAENVSERVICE_FILECODE (0xB0D7)
+#define PROC_FCH_SATA_FAMILY_HUDSON2_HUDSON2SATASERVICE_FILECODE (0xB0D8)
+#define PROC_FCH_SD_SDENV_FILECODE (0xB0E0)
+#define PROC_FCH_SD_SDMID_FILECODE (0xB0E1)
+#define PROC_FCH_SD_SDLATE_FILECODE (0xB0E2)
+#define PROC_FCH_SD_FAMILY_HUDSON2_HUDSON2SDSERVICE_FILECODE (0xB0E3)
+#define PROC_FCH_SD_FAMILY_HUDSON2_HUDSON2SDRESETSERVICE_FILECODE (0xB0E4)
+#define PROC_FCH_SD_FAMILY_HUDSON2_HUDSON2SDENVSERVICE_FILECODE (0xB0E5)
+#define PROC_FCH_SPI_LPCRESET_FILECODE (0xB0F0)
+#define PROC_FCH_SPI_LPCENV_FILECODE (0xB0F1)
+#define PROC_FCH_SPI_LPCMID_FILECODE (0xB0F2)
+#define PROC_FCH_SPI_LPCLATE_FILECODE (0xB0F3)
+#define PROC_FCH_SPI_SPIRESET_FILECODE (0xB0F4)
+#define PROC_FCH_SPI_SPIENV_FILECODE (0xB0F5)
+#define PROC_FCH_SPI_SPIMID_FILECODE (0xB0F6)
+#define PROC_FCH_SPI_SPILATE_FILECODE (0xB0F7)
+#define PROC_FCH_SPI_FAMILY_HUDSON2_HUDSON2LPCENVSERVICE_FILECODE (0xB0F8)
+#define PROC_FCH_SPI_FAMILY_HUDSON2_HUDSON2LPCRESETSERVICE_FILECODE (0xB0F9)
+#define PROC_FCH_USB_EHCIRESET_FILECODE (0xB100)
+#define PROC_FCH_USB_EHCIENV_FILECODE (0xB101)
+#define PROC_FCH_USB_EHCIMID_FILECODE (0xB102)
+#define PROC_FCH_USB_EHCILATE_FILECODE (0xB103)
+#define PROC_FCH_USB_OHCIRESET_FILECODE (0xB104)
+#define PROC_FCH_USB_OHCIENV_FILECODE (0xB105)
+#define PROC_FCH_USB_OHCIMID_FILECODE (0xB106)
+#define PROC_FCH_USB_OHCILATE_FILECODE (0xB107)
+#define PROC_FCH_USB_USBRESET_FILECODE (0xB108)
+#define PROC_FCH_USB_USBENV_FILECODE (0xB109)
+#define PROC_FCH_USB_USBMID_FILECODE (0xB10A)
+#define PROC_FCH_USB_USBLATE_FILECODE (0xB10B)
+#define PROC_FCH_USB_XHCIRESET_FILECODE (0xB10C)
+#define PROC_FCH_USB_XHCIENV_FILECODE (0xB10D)
+#define PROC_FCH_USB_XHCIMID_FILECODE (0xB10E)
+#define PROC_FCH_USB_XHCILATE_FILECODE (0xB10F)
+#define PROC_FCH_USB_FAMILY_HUDSON2_HUDSON2EHCIENVSERVICE_FILECODE (0xB110)
+#define PROC_FCH_USB_FAMILY_HUDSON2_HUDSON2EHCIMIDSERVICE_FILECODE (0xB111)
+#define PROC_FCH_USB_FAMILY_HUDSON2_HUDSON2EHCILATESERVICE_FILECODE (0xB112)
+#define PROC_FCH_USB_FAMILY_HUDSON2_HUDSON2OHCIENVSERVICE_FILECODE (0xB113)
+#define PROC_FCH_USB_FAMILY_HUDSON2_HUDSON2OHCIMIDSERVICE_FILECODE (0xB114)
+#define PROC_FCH_USB_FAMILY_HUDSON2_HUDSON2OHCILATESERVICE_FILECODE (0xB115)
+#define PROC_FCH_USB_FAMILY_HUDSON2_HUDSON2XHCIRESETSERVICE_FILECODE (0xB116)
+#define PROC_FCH_USB_FAMILY_HUDSON2_HUDSON2XHCIENVSERVICE_FILECODE (0xB117)
+#define PROC_FCH_USB_FAMILY_HUDSON2_HUDSON2XHCIMIDSERVICE_FILECODE (0xB118)
+#define PROC_FCH_USB_FAMILY_HUDSON2_HUDSON2XHCILATESERVICE_FILECODE (0xB119)
+#define PROC_FCH_USB_XHCIRECOVERY_FILECODE (0xB12E)
+#define PROC_FCH_PCIE_GPPPORTINIT_FILECODE (0xB12F)
+#define PROC_FCH_SPI_FAMILY_YUBA_YUBALPCRESETSERVICE_FILECODE (0xB160)
+#define UEFI_DXE_FCHDXE_FCHDXE_FILECODE (0xB200)
+#define UEFI_DXE_FCHDXE_USBOC_FILECODE (0xB201)
+#define UEFI_DXE_FCHDXEAUX_DXEGPIO_FILECODE (0xB202)
+#define UEFI_DXE_FCHDXEAUX_DXEGPIOREAD_FILECODE (0xB203)
+#define UEFI_DXE_FCHDXELPCCLKRUN_FCHDXELPCCLKRUN_FILECODE (0xB204)
+#define UEFI_DXE_AMDFCHWHEA_AMDFCHWHEA_FILECODE (0xB210)
+#define UEFI_DXE_AMDFCHWHEA_AMDFCHWHEAEINJ_FILECODE (0xB211)
+#define UEFI_DXE_AMDFCHWHEA_AMDFCHWHEAHEST_FILECODE (0xB212)
+#define UEFI_DXE_FCHDXEAUX_DXEDISUSBPORT_FILECODE (0xB213)
+#define UEFI_DXE_FCHDXEAUX_DXEBOOTTIMER_FILECODE (0xB214)
+#define UEFI_DXE_FCHDXEAUX_DXEESATAPORT_FILECODE (0xB215)
+#define UEFI_DXE_AMDFCHHWM_AMDFCHHWM_FILECODE (0xB216)
+#define UEFI_DXE_AMDIGPUVGACONTROLDXE_AMDIGPUVGACONTROLDXE_FILECODE (0xB218)
+#define UEFI_DXE_CF9RESET_CF9RESET_FILECODE (0xB220)
+#define UEFI_DXE_CF9RESET_IA32_IA32CF9RESET_FILECODE (0xB221)
+#define UEFI_DXE_CF9RESET_X64_X64CF9RESET_FILECODE (0xB222)
+#define UEFI_DXE_FCHDXEMMIO_FCHDXEMMIO_FILECODE (0xB223)
+#define UEFI_DXE_LEGACYINTERRUPT_LEGACYINTERRUPT_FILECODE (0xB230)
+#define UEFI_DXE_FCHACPICS_FCHACPICS_FILECODE (0xB231)
+#define UEFI_DXE_FCHACPICS_FCHACPICSAML_FILECODE (0xB232)
+#define UEFI_DXE_FCHACPICS_FCHACPICSCONTROL_FILECODE (0xB233)
+#define UEFI_DXE_FCHACPICS_FUNCTIONS_POWERBUTTON_POWERBUTTON_FILECODE (0xB234)
+#define UEFI_DXE_FCHACPICS_FUNCTIONS_SMBUSNFC_SMBUSNFC_FILECODE (0xB235)
+#define UEFI_DXE_SMMCONTROL_SMMCONTROL_FILECODE (0xB240)
+#define UEFI_SMM_FCHSMMLIB_FCHDXECOMMON_FILECODE (0xB250)
+#define UEFI_SMM_FCHSMMLIB_FCHSMMLIB_FILECODE (0xB251)
+#define UEFI_DXE_FCHDXELIB_FCHDXELIB_FILECODE (0xB252)
+#define UEFI_PEI_FCHPEI_FCHPEI_FILECODE (0xB260)
+#define UEFI_PEI_FCHPEI_FCHRESET_FILECODE (0xB261)
+#define UEFI_PEI_FCHPEI_FCHSTALL_FILECODE (0xB262)
+#define UEFI_DXE_FCHDXEAUX_FCHDXEAUX_FILECODE (0xB263)
+#define UEFI_PEI_FCHPEIAUX_FCHPEIAUX_FILECODE (0xB264)
+#define UEFI_PEI_FCHPEILIB_FCHPEILIB_FILECODE (0xB265)
+#define UEFI_PEI_FCHPEILIB_LIBAMDPEI_FILECODE (0xB266)
+#define UEFI_PEI_FCHPEIAUX_PEIGPIO_FILECODE (0xB267)
+#define UEFI_PEI_FCHPEIAUX_PEIGPIOREAD_FILECODE (0xB268)
+#define UEFI_PEI_FCHPEIAUX_PEIDISUSBPORT_FILECODE (0xB269)
+#define UEFI_PEI_FCHPEIAUX_PEIBOOTTIMER_FILECODE (0xB26A)
+#define UEFI_PEI_FCHPEIAUX_PEIOSCOUTCLOCK_FILECODE (0xB26B)
+#define UEFI_PEI_FCHPEI_FCHEHCIRECOVERY_FILECODE (0xB280)
+#define UEFI_PEI_FCHPEI_FCHSATARECOVERY_FILECODE (0xB281)
+#define UEFI_PEI_FCHPEI_FCHXHCIRECOVERY_FILECODE (0xB282)
+#define UEFI_PEI_FCHPEI_FCHGPPRECOVERY_FILECODE (0xB283)
+#define UEFI_PEI_SMBUS_SMBUS_FILECODE (0xB28A)
+#define UEFI_SMM_FCHSMM_FCHSMM_FILECODE (0xB290)
+#define UEFI_SMM_FCHSMMCOMPLEMENT_SDIOPOWER_SDIOPOWER_FILECODE (0xB291)
+#define UEFI_SMM_FCHSMMCOMPLEMENT_USB3PORTPROTECTWA_USB3PORTPROTECTWA_FILECODE (0xB292)
+#define UEFI_SMM_FCHSMM_GPESMI_FILECODE (0xB293)
+#define UEFI_SMM_FCHSMM_IOTRAPSMI_FILECODE (0xB294)
+#define UEFI_SMM_FCHSMM_MISCSMI_FILECODE (0xB295)
+#define UEFI_SMM_FCHSMM_PERIODICTIMERSMI_FILECODE (0xB296)
+#define UEFI_SMM_FCHSMM_POWERBUTTONSMI_FILECODE (0xB297)
+#define UEFI_SMM_FCHSMM_SWSMI_FILECODE (0xB298)
+#define UEFI_SMM_FCHSMM_SXSMI_FILECODE (0xB299)
+#define UEFI_SMM_FCHSMMCOMPLEMENT_IMCCONTROL_IMCCONTROL_FILECODE (0xB29A)
+#define UEFI_SMM_FCHSMMCOMPLEMENT_IMCCONTROL_IMCCONTROLLIB_FILECODE (0xB29B)
+#define UEFI_SMM_FCHSMMCOMPLEMENT_USB3PORTPROTECTWA_LIBAMDSMMLIB_FILECODE (0xB29C)
+#define UEFI_SMM_FCHSMMCOMPLEMENT_FCHPCIEWAKEWA_FCHPCIEWAKEWA_FILECODE (0xB29D)
+#define UEFI_SMM_FCHSMMCOMPLEMENT_SDCLKDRIVINGLOWWA_SDCLKDRIVINGLOWWA_FILECODE (0xB29E)
+#define UEFI_SMM_FCHSMMCOMPLEMENT_FCHSDVOLTAGESWITCH_FCHSDVOLTAGESWITCH_FILECODE (0xB29F)
+#define UEFI_DXE_SMBUS_SMBUSLIGHT_FILECODE (0xB2A0)
+#define UEFI_SMM_FCHSMMCOMPLEMENT_FCHIMCSPIWA_FCHIMCSPIWA_FILECODE (0xB2A1)
+#define UEFI_SMM_FCHSMMCOMPLEMENT_FCHXHCD3WA_FCHXHCD3WA_FILECODE (0xB2A2)
+#define UEFI_SMM_FCHSMMDISPATCHER_FCHSMMDISPATCHER_FILECODE (0xB2B0)
+#define UEFI_SMM_FCHSMMDISPATCHER_FCHSMMGPEDISPATCHER_FCHSMMGPEDISPATCHER_FILECODE (0xB2B1)
+#define UEFI_SMM_FCHSMMDISPATCHER_FCHSMMIOTRAPDISPATCHER_FCHSMMIOTRAPDISPATCHER_FILECODE (0xB2B2)
+#define UEFI_SMM_FCHSMMDISPATCHER_FCHSMMMISCDISPATCHER_FCHSMMMISCDISPATCHER_FILECODE (0xB2B3)
+#define UEFI_SMM_FCHSMMDISPATCHER_FCHSMMPERIODICALDISPATCHER_FCHSMMPERIODICALDISPATCHER_FILECODE (0xB2B4)
+#define UEFI_SMM_FCHSMMDISPATCHER_FCHSMMPWRBTNDISPATCHER_FCHSMMPWRBTNDISPATCHER_FILECODE (0xB2B5)
+#define UEFI_SMM_FCHSMMDISPATCHER_FCHSMMSWDISPATCHER_FCHSMMSWDISPATCHER_FILECODE (0xB2B6)
+#define UEFI_SMM_FCHSMMDISPATCHER_FCHSMMSXDISPATCHER_FCHSMMSXDISPATCHER_FILECODE (0xB2B7)
+#define UEFI_SMM_FCHSMMDISPATCHER_FCHSMMUSBDISPATCHER_FCHSMMUSBDISPATCHER_FILECODE (0xB2B8)
+#define PROC_FCH_PCIE_GPPALLINONE_FILECODE (0xB2C0)
+#define UEFI_SMM_MEMSMMLIB_MEMSMMLIB_FILECODE (0xB2C1)
+#define UEFI_SMM_MEMSMMLIB_KV_DRAMMAPKV_FILECODE (0xB2C3)
+
+#define LIB_AMDLIB_FILECODE (0xC001)
+
+#define LEGACY_PROC_AGESACALLOUTS_FILECODE (0xC010)
+#define LEGACY_PROC_HOBTRANSFER_FILECODE (0xC011)
+#define LEGACY_PROC_DISPATCHER_FILECODE (0xC012)
+
+#define UEFI_DXE_AMDAGESADXEDRIVER_AMDAGESADXEDRIVER_FILECODE (0xC120)
+
+#define UEFI_PEI_AMDINITPOSTPEIM_AMDINITPOSTPEIM_FILECODE (0xC140)
+#define UEFI_PEI_AMDPROCESSORINITPEIM_AMDPROCESSORINITPEIM_FILECODE (0xC141)
+#define UEFI_PEI_AMDRESETMANAGER_AMDRESETMANAGER_FILECODE (0xC142)
+#define UEFI_PROC_COMMON_HOBTRANSFERUEFI_FILECODE (0xC160)
+#define UEFI_PROC_DXE_HOBTRANSFERUEFIDXE_FILECODE (0xC161)
+#define UEFI_PROC_PEI_HOBTRANSFERUEFIPEI_FILECODE (0xC162)
+
+#define PROC_COMMON_AMDINITEARLY_FILECODE (0xC020)
+#define PROC_COMMON_AMDINITENV_FILECODE (0xC021)
+#define PROC_COMMON_AMDINITLATE_FILECODE (0xC022)
+#define PROC_COMMON_AMDINITMID_FILECODE (0xC023)
+#define PROC_COMMON_AMDINITPOST_FILECODE (0xC024)
+#define PROC_COMMON_AMDINITRECOVERY_FILECODE (0xC025)
+#define PROC_COMMON_AMDINITRESET_FILECODE (0xC026)
+#define PROC_COMMON_AMDINITRESUME_FILECODE (0xC027)
+#define PROC_COMMON_AMDS3LATERESTORE_FILECODE (0xC028)
+#define PROC_COMMON_AMDS3SAVE_FILECODE (0xC029)
+#define PROC_COMMON_AMDLATERUNAPTASK_FILECODE (0xC02A)
+#define PROC_COMMON_AMDS3FINALRESTORE_FILECODE (0xC02B)
+
+#define PROC_COMMON_COMMONRETURNS_FILECODE (0xC0C0)
+#define PROC_COMMON_CREATESTRUCT_FILECODE (0xC0D0)
+#define PROC_COMMON_COMMONINITS_FILECODE (0xC0F0)
+#define PROC_COMMON_S3RESTORESTATE_FILECODE (0xC0F8)
+#define PROC_COMMON_S3SAVESTATE_FILECODE (0xC0F9)
+
+#define PROC_CPU_CPUAPICUTILITIES_FILECODE (0xC401)
+#define PROC_CPU_TABLE_FILECODE (0xC403)
+#define PROC_CPU_CPUEARLYINIT_FILECODE (0xC405)
+#define PROC_CPU_CPUEVENTLOG_FILECODE (0xC406)
+#define PROC_CPU_CPUFAMILYTRANSLATION_FILECODE (0xC407)
+#define PROC_CPU_CPUGENERALSERVICES_FILECODE (0xC408)
+#define PROC_CPU_CPULATEINIT_FILECODE (0xC40A)
+#define PROC_CPU_CPUMICROCODEPATCH_FILECODE (0xC40B)
+#define PROC_CPU_CPUWARMRESET_FILECODE (0xC40C)
+#define PROC_CPU_HEAPMANAGER_FILECODE (0xC40D)
+#define PROC_CPU_CPUBIST_FILECODE (0xC40E)
+#define PROC_CPU_MMIOMAPMANAGER_FILECODE (0xC40F)
+
+#define PROC_CPU_CPUPOSTINIT_FILECODE (0xC420)
+#define PROC_CPU_CPUPOWERMGMT_FILECODE (0xC430)
+#define PROC_CPU_CPUPOWERMGMTMULTISOCKET_FILECODE (0xC431)
+#define PROC_CPU_CPUPOWERMGMTSINGLESOCKET_FILECODE (0xC432)
+#define PROC_CPU_S3_FILECODE (0xC460)
+
+// Family 15h
+#define PROC_CPU_FAMILY_0X15_CPUCOMMONF15UTILITIES_FILECODE (0xCB01)
+#define PROC_CPU_FAMILY_0X15_CPUF15BRANDID_FILECODE (0xCB02)
+#define PROC_CPU_FAMILY_0X15_CPUF15CACHEDEFAULTS_FILECODE (0xCB03)
+#define PROC_CPU_FAMILY_0X15_CPUF15DMI_FILECODE (0xCB04)
+#define PROC_CPU_FAMILY_0X15_CPUF15MSRTABLES_FILECODE (0xCB05)
+#define PROC_CPU_FAMILY_0X15_CPUF15PCITABLES_FILECODE (0xCB06)
+#define PROC_CPU_FAMILY_0X15_CPUF15POWERCHECK_FILECODE (0xCB07)
+#define PROC_CPU_FAMILY_0X15_CPUF15UTILITIES_FILECODE (0xCB08)
+#define PROC_CPU_FAMILY_0X15_CPUF15WHEAINITDATATABLES_FILECODE (0xCB09)
+#define PROC_CPU_FAMILY_0X15_CPUF15APM_FILECODE (0xCB0A)
+#define PROC_CPU_FAMILY_0X15_CPUF15CRAT_FILECODE (0xCB0B)
+#define PROC_CPU_FAMILY_0X15_CPUF15MMIOMAP_FILECODE (0xCB0C)
+#define PROC_CPU_FAMILY_0X15_CPUF15PREFETCHMODE_FILECODE (0xCB0D)
+
+#define PROC_CPU_FAMILY_0X15_TN_CPUF15TNCOREAFTERRESET_FILECODE (0xCB50)
+#define PROC_CPU_FAMILY_0X15_TN_CPUF15TNDMI_FILECODE (0xCB51)
+#define PROC_CPU_FAMILY_0X15_TN_CPUF15TNNBAFTERRESET_FILECODE (0xCB52)
+#define PROC_CPU_FAMILY_0X15_TN_CPUF15TNPSTATE_FILECODE (0xCB53)
+#define PROC_CPU_FAMILY_0X15_TN_F15TNLOGICALIDTABLES_FILECODE (0xCB54)
+#define PROC_CPU_FAMILY_0X15_TN_F15TNMICROCODEPATCHTABLES_FILECODE (0xCB55)
+#define PROC_CPU_FAMILY_0X15_TN_F15TNMSRTABLES_FILECODE (0xCB56)
+#define PROC_CPU_FAMILY_0X15_TN_F15TNSHAREDMSRTABLE_FILECODE (0xCB57)
+#define PROC_CPU_FAMILY_0X15_TN_F15TNEQUIVALENCETABLE_FILECODE (0xCB58)
+#define PROC_CPU_FAMILY_0X15_TN_F15TNPCITABLES_FILECODE (0xCB59)
+#define PROC_CPU_FAMILY_0X15_TN_F15TNPOWERMGMTSYSTEMTABLES_FILECODE (0xCB5A)
+#define PROC_CPU_FAMILY_0X15_TN_F15TNPOWERPLANE_FILECODE (0xCB5B)
+#define PROC_CPU_FAMILY_0X15_TN_F15TNUTILITIES_FILECODE (0xCB5C)
+#define PROC_CPU_FAMILY_0X15_TN_F15TNC6STATE_FILECODE (0xCB5D)
+#define PROC_CPU_FAMILY_0X15_TN_F15TNCPB_FILECODE (0xCB5E)
+#define PROC_CPU_FAMILY_0X15_TN_F15TNIOCSTATE_FILECODE (0xCB5F)
+#define PROC_CPU_FAMILY_0X15_TN_CPUF15TNCACHEFLUSHONHALT_FILECODE (0xCB60)
+#define PROC_CPU_FAMILY_0X15_TN_F15TNINITEARLYTABLE_FILECODE (0xCB62)
+#define PROC_CPU_FAMILY_0X15_TN_F15TNEARLYSAMPLES_FILECODE (0xCB63)
+#define PROC_CPU_FAMILY_0X15_TN_CPUF15TNPOWERCHECK_FILECODE (0xCB64)
+#define PROC_CPU_FAMILY_0X15_TN_CPUF15TNPSI_FILECODE (0xCB65)
+#define PROC_CPU_FAMILY_0X15_TN_CPUF15TNHTC_FILECODE (0xCB66)
+
+#define PROC_CPU_FAMILY_0X15_KV_CPUF15KVCOREAFTERRESET_FILECODE (0xCBE0)
+#define PROC_CPU_FAMILY_0X15_KV_CPUF15KVDMI_FILECODE (0xCBE1)
+#define PROC_CPU_FAMILY_0X15_KV_CPUF15KVNBAFTERRESET_FILECODE (0xCBE2)
+#define PROC_CPU_FAMILY_0X15_KV_CPUF15KVPSTATE_FILECODE (0xCBE3)
+#define PROC_CPU_FAMILY_0X15_KV_CPUF15KVLOGICALIDTABLES_FILECODE (0xCBE4)
+#define PROC_CPU_FAMILY_0X15_KV_CPUF15KVMICROCODEPATCHTABLES_FILECODE (0xCBE5)
+#define PROC_CPU_FAMILY_0X15_KV_CPUF15KVMSRTABLES_FILECODE (0xCBE6)
+#define PROC_CPU_FAMILY_0X15_KV_CPUF15KVSHAREDMSRTABLE_FILECODE (0xCBE7)
+#define PROC_CPU_FAMILY_0X15_KV_CPUF15KVEQUIVALENCETABLE_FILECODE (0xCBE8)
+#define PROC_CPU_FAMILY_0X15_KV_CPUF15KVPCITABLES_FILECODE (0xCBE9)
+#define PROC_CPU_FAMILY_0X15_KV_CPUF15KVPOWERMGMTSYSTEMTABLES_FILECODE (0xCBEA)
+#define PROC_CPU_FAMILY_0X15_KV_CPUF15KVBRANDID_FILECODE (0xCBEB)
+#define PROC_CPU_FAMILY_0X15_KV_CPUF15KVUTILITIES_FILECODE (0xCBEC)
+#define PROC_CPU_FAMILY_0X15_KV_CPUF15KVC6STATE_FILECODE (0xCBED)
+#define PROC_CPU_FAMILY_0X15_KV_CPUF15KVCPB_FILECODE (0xCBEE)
+#define PROC_CPU_FAMILY_0X15_KV_CPUF15KVIOCSTATE_FILECODE (0xCBEF)
+#define PROC_CPU_FAMILY_0X15_KV_CPUF15KVCACHEFLUSHONHALT_FILECODE (0xCBF0)
+#define PROC_CPU_FAMILY_0X15_KV_CPUF15KVHTC_FILECODE (0xCBF1)
+#define PROC_CPU_FAMILY_0X15_KV_CPUF15KVINITEARLYTABLE_FILECODE (0xCBF2)
+#define PROC_CPU_FAMILY_0X15_KV_CPUF15KVEARLYSAMPLES_FILECODE (0xCBF3)
+#define PROC_CPU_FAMILY_0X15_KV_CPUF15KVPOWERCHECK_FILECODE (0xCBF4)
+#define PROC_CPU_FAMILY_0X15_KV_CPUF15KVPSI_FILECODE (0xCBF5)
+#define PROC_CPU_FAMILY_0X15_KV_CPUF15KVSCS_FILECODE (0xCBF6)
+#define PROC_CPU_FAMILY_0X15_KV_CPUF15KVCC6EXITCONTROL_FILECODE (0xCBF7)
+
+#define PROC_CPU_FEATURE_CPUCACHEFLUSHONHALT_FILECODE (0xDC01)
+#define PROC_CPU_FEATURE_CPUCACHEINIT_FILECODE (0xDC02)
+#define PROC_CPU_FEATURE_CPUDMI_FILECODE (0xDC10)
+#define PROC_CPU_FEATURE_CPUPSTATEGATHER_FILECODE (0xDC41)
+#define PROC_CPU_FEATURE_CPUPSTATELEVELING_FILECODE (0xDC42)
+#define PROC_CPU_FEATURE_CPUPSTATETABLES_FILECODE (0xDC43)
+#define PROC_CPU_FEATURE_CPUSLIT_FILECODE (0xDC50)
+#define PROC_CPU_FEATURE_CPUSRAT_FILECODE (0xDC60)
+#define PROC_CPU_FEATURE_CPUWHEA_FILECODE (0xDC70)
+#define PROC_CPU_FEATURE_CPUC6STATE_FILECODE (0xDC82)
+#define PROC_CPU_FEATURE_CPUCPB_FILECODE (0xDC83)
+#define PROC_CPU_FEATURE_CPULOWPWRPSTATE_FILECODE (0xDC84)
+#define PROC_CPU_FEATURE_CPUIOCSTATE_FILECODE (0xDC85)
+#define PROC_CPU_FEATURE_CPUAPM_FILECODE (0xDC86)
+#define PROC_CPU_FEATURE_CPUFEATURES_FILECODE (0xDC90)
+#define PROC_CPU_FEATURE_CPUCORELEVELING_FILECODE (0xDCB0)
+#define PROC_CPU_FEATURE_CPUPSI_FILECODE (0xDCC0)
+#define PROC_CPU_FEATURE_CPUHTC_FILECODE (0xDCC1)
+#define PROC_CPU_FEATURE_CPUCRAT_FILECODE (0xDCD0)
+#define PROC_CPU_FEATURE_CPUCDIT_FILECODE (0xDCD1)
+#define PROC_CPU_FEATURE_CPUPREFETCHMODE_FILECODE (0xDCD3)
+#define PROC_CPU_FEATURE_CPUSCS_FILECODE (0xDCD4)
+#define PROC_CPU_FEATURE_CPUCC6EXITCONTROL_FILECODE (0xDCD5)
+
+#define PROC_RECOVERY_CPU_CPURECOVERY_FILECODE (0xDE01)
+
+#define PROC_TOPOLOGY_TOPOMAIN_FILECODE (0xE001)
+#define PROC_TOPOLOGY_TOPONB_FILECODE (0xE002)
+#define PROC_TOPOLOGY_FAM15_TOPONBFAM15_FILECODE (0xE087)
+#define PROC_TOPOLOGY_FAM15_TOPONBUTILITIESFAM15_FILECODE (0xE088)
+#define PROC_TOPOLOGY_FAM16_TOPONBFAM16_FILECODE (0xE097)
+#define PROC_TOPOLOGY_FAM16_TOPONBUTILITIESFAM16_FILECODE (0xE098)
+
+#define PROC_RECOVERY_TOPOLOGY_TOPOINITRECOVERY_FILECODE (0xE0FF)
+
+#define PROC_IDS_CONTROL_IDSCTRL_FILECODE (0xE801)
+#define PROC_IDS_LIBRARY_IDSLIB_FILECODE (0xE802)
+#define PROC_IDS_DEBUG_IDSDEBUG_FILECODE (0xE803)
+#define PROC_IDS_PERF_IDSPERF_FILECODE (0xE804)
+#define PROC_IDS_FAMILY_0X15_IDSF15ALLSERVICE_FILECODE (0xE80C)
+#define PROC_IDS_FAMILY_0X15_TN_IDSF15TNALLSERVICE_FILECODE (0xE80F)
+#define PROC_IDS_LIBRARY_IDSREGACC_FILECODE (0xE810)
+#define PROC_IDS_DEBUG_IDSDPHDTOUT_FILECODE (0xE811)
+#define PROC_IDS_DEBUG_IDSDEBUGPRINT_FILECODE (0xE812)
+#define PROC_IDS_DEBUG_IDSDPSERIAL_FILECODE (0xE813)
+#define PROC_IDS_DEBUG_IDSDPREDIRECTIO_FILECODE (0xE814)
+#define PROC_IDS_DEBUG_IDSDPRAM_FILECODE (0xE815)
+
+#define PROC_IDS_DEBUG_IDSIDTTABLE_FILECODE (0xE81E)
+#define PROC_IDS_CONTROL_IDSNVTOCMOS_FILECODE (0xE81F)
+#define PROC_IDS_FAMILY_0X15_KV_IDSF15KVALLSERVICE_FILECODE (0xE820)
+
+///0xE820 ~ 0xE840 is reserved for ids extend module
+
+#define PROC_MEM_ARDK_MA_FILECODE (0xF001)
+
+#define PROC_MEM_FEAT_CHINTLV_MFCHI_FILECODE (0xF081)
+#define PROC_MEM_FEAT_CSINTLV_MFCSI_FILECODE (0xF082)
+#define PROC_MEM_FEAT_ECC_MFECC_FILECODE (0xF083)
+#define PROC_MEM_FEAT_ECC_MFEMP_FILECODE (0xF085)
+#define PROC_MEM_FEAT_EXCLUDIMM_MFDIMMEXCLUD_FILECODE (0xF086)
+#define PROC_MEM_FEAT_IDENDIMM_MFIDENDIMM_FILECODE (0xF088)
+#define PROC_MEM_FEAT_INTLVRN_MFINTLVRN_FILECODE (0xF089)
+#define PROC_MEM_FEAT_LVDDR3_MFLVDDR3_FILECODE (0xF08A)
+#define PROC_MEM_FEAT_MEMCLR_MFMEMCLR_FILECODE (0xF08B)
+#define PROC_MEM_FEAT_NDINTLV_MFNDI_FILECODE (0xF08C)
+#define PROC_MEM_FEAT_ODTHERMAL_MFODTHERMAL_FILECODE (0xF08D)
+#define PROC_MEM_FEAT_OLSPARE_MFSPR_FILECODE (0xF08E)
+#define PROC_MEM_FEAT_PARTRN_MFPARALLELTRAINING_FILECODE (0xF08F)
+#define PROC_MEM_FEAT_PARTRN_MFSTANDARDTRAINING_FILECODE (0xF091)
+#define PROC_MEM_FEAT_S3_MFS3_FILECODE (0xF092)
+#define PROC_MEM_FEAT_TABLE_MFTDS_FILECODE (0xF093)
+#define PROC_MEM_FEAT_CHINTLV_MFMCHI_FILECODE (0xF094)
+#define PROC_MEM_FEAT_CRAT_MFCRAT_FILECODE (0xF095)
+#define PROC_MEM_FEAT_AMP_MFAMP_FILECODE (0xF096)
+#define PROC_MEM_FEAT_DATAEYE_MF2DDATAEYE_FILECODE (0xF097)
+#define PROC_MEM_FEAT_RDWR2DTRAINING_MFWRDAT2DTRAINING_FILECODE (0xF098)
+#define PROC_MEM_FEAT_RDWR2DTRAINING_MFRDWR2DEYERIMSEARCH_FILECODE (0xF099)
+#define PROC_MEM_FEAT_RDWR2DTRAINING_MFRDDQS2DTRAINING_FILECODE (0xF09A)
+#define PROC_MEM_FEAT_RDWR2DTRAINING_MFRDWR2DTRAINING_FILECODE (0xF09B)
+#define PROC_MEM_FEAT_RDWR2DTRAINING_MFRDWR2DPATTERNGENERATION_FILECODE (0xF09C)
+#define PROC_MEM_FEAT_AGGRESSOR_MFAGGRESSOR_FILECODE (0xF09F)
+#define PROC_MEM_FEAT_DLLPDBYPASS_MFDLLPDBYPASS_FILECODE (0xF0A0)
+
+#define PROC_MEM_MAIN_MDEF_FILECODE (0xF101)
+#define PROC_MEM_MAIN_MINIT_FILECODE (0xF102)
+#define PROC_MEM_MAIN_MM_FILECODE (0xF103)
+#define PROC_MEM_FEAT_DMI_MFDMI_FILECODE (0xF104)
+#define PROC_MEM_MAIN_MMECC_FILECODE (0xF105)
+#define PROC_MEM_MAIN_MMEXCLUDEDIMM_FILECODE (0xF106)
+#define PROC_MEM_MAIN_MMNODEINTERLEAVE_FILECODE (0xF10B)
+#define PROC_MEM_MAIN_MMONLINESPARE_FILECODE (0xF10C)
+#define PROC_MEM_MAIN_MMPARALLELTRAINING_FILECODE (0xF10D)
+#define PROC_MEM_MAIN_MMSTANDARDTRAINING_FILECODE (0xF10E)
+#define PROC_MEM_MAIN_MUC_FILECODE (0xF10F)
+#define PROC_MEM_MAIN_MMMEMCLR_FILECODE (0xF110)
+#define PROC_MEM_MAIN_MMFLOW_FILECODE (0xF112)
+#define PROC_MEM_MAIN_MERRHDL_FILECODE (0xF113)
+#define PROC_MEM_MAIN_MMLVDDR3_FILECODE (0xF115)
+#define PROC_MEM_MAIN_MMUMAALLOC_FILECODE (0xF116)
+#define PROC_MEM_MAIN_MMMEMRESTORE_FILECODE (0xF117)
+#define PROC_MEM_MAIN_MMCONDITIONALPSO_FILECODE (0xF118)
+#define PROC_MEM_MAIN_MMAGGRESSOR_FILECODE (0xF119)
+#define PROC_MEM_MAIN_TN_MMFLOWTN_FILECODE (0xF11C)
+#define PROC_MEM_MAIN_KV_MMFLOWD3KV_FILECODE (0xF122)
+
+#define PROC_MEM_NB_MN_FILECODE (0XF27C)
+#define PROC_MEM_NB_MNDCT_FILECODE (0XF27D)
+#define PROC_MEM_NB_MNPHY_FILECODE (0XF27E)
+#define PROC_MEM_NB_MNMCT_FILECODE (0XF27F)
+#define PROC_MEM_NB_MNS3_FILECODE (0XF280)
+#define PROC_MEM_NB_MNFLOW_FILECODE (0XF281)
+#define PROC_MEM_NB_MNFEAT_FILECODE (0XF282)
+#define PROC_MEM_NB_MNTRAIN3_FILECODE (0XF284)
+#define PROC_MEM_NB_MNREG_FILECODE (0XF285)
+#define PROC_MEM_NB_TN_MNREGTN_FILECODE (0XF29B)
+#define PROC_MEM_NB_TN_MNTN_FILECODE (0XF29C)
+#define PROC_MEM_NB_TN_MNMCTTN_FILECODE (0XF29D)
+#define PROC_MEM_NB_TN_MNOTTN_FILECODE (0XF29E)
+#define PROC_MEM_NB_TN_MNDCTTN_FILECODE (0XF29F)
+#define PROC_MEM_NB_TN_MNPHYTN_FILECODE (0XF2A0)
+#define PROC_MEM_NB_TN_MNS3TN_FILECODE (0XF2A1)
+#define PROC_MEM_NB_TN_MNIDENDIMMTN_FILECODE (0XF2A2)
+#define PROC_MEM_NB_TN_MNFLOWTN_FILECODE (0XF2A3)
+#define PROC_MEM_NB_TN_MNPROTOTN_FILECODE (0XF2A4)
+#define PROC_MEM_NB_KV_MNKV_FILECODE (0xF2AF)
+#define PROC_MEM_NB_KV_MNMCTKV_FILECODE (0xF2B0)
+#define PROC_MEM_NB_KV_MNDCTKV_FILECODE (0xF2B1)
+#define PROC_MEM_NB_KV_MNPHYKV_FILECODE (0xF2B2)
+#define PROC_MEM_NB_KV_MNS3KV_FILECODE (0xF2B3)
+#define PROC_MEM_NB_KV_MNIDENDIMMKV_FILECODE (0xF2B4)
+#define PROC_MEM_NB_KV_MNPROTOKV_FILECODE (0xF2B5)
+#define PROC_MEM_NB_KV_MNREGKV_FILECODE (0xF2B6)
+#define PROC_MEM_NB_MNPMU_FILECODE (0xF2B7)
+#define PROC_MEM_NB_KV_MNPMUKV_FILECODE (0XF2C2)
+#define PROC_MEM_NB_KV_MNPMUSRAMMSGBLOCKKV_FILECODE (0XF2D7)
+
+#define PROC_MEM_PS_MP_FILECODE (0XF401)
+#define PROC_MEM_PS_MPRTT_FILECODE (0XF422)
+#define PROC_MEM_PS_MPMAXFREQ_FILECODE (0XF423)
+#define PROC_MEM_PS_MPODTPAT_FILECODE (0XF424)
+#define PROC_MEM_PS_MPSAO_FILECODE (0XF425)
+#define PROC_MEM_PS_MPMR0_FILECODE (0XF426)
+#define PROC_MEM_PS_MPRC2IBT_FILECODE (0XF427)
+#define PROC_MEM_PS_MPRC10OPSPD_FILECODE (0XF428)
+#define PROC_MEM_PS_MPLRIBT_FILECODE (0XF429)
+#define PROC_MEM_PS_MPLRNPR_FILECODE (0XF42A)
+#define PROC_MEM_PS_MPLRNLR_FILECODE (0XF42B)
+#define PROC_MEM_PS_TN_MPSTN3_FILECODE (0XF42D)
+#define PROC_MEM_PS_TN_MPTN3_FILECODE (0XF42E)
+#define PROC_MEM_PS_TN_MPUTN3_FILECODE (0XF42F)
+#define PROC_MEM_PS_TN_FM2_MPUTNFM2_FILECODE (0XF430)
+#define PROC_MEM_PS_TN_FP2_MPSTNFP2_FILECODE (0XF431)
+#define PROC_MEM_PS_TN_FS1_MPSTNFS1_FILECODE (0XF432)
+#define PROC_MEM_PS_MPS2D_FILECODE (0XF436)
+#define PROC_MEM_PS_MPSEEDS_FILECODE (0XF437)
+#define PROC_MEM_PS_MPCADCFG_FILECODE (0XF43C)
+#define PROC_MEM_PS_MPDATACFG_FILECODE (0XF43D)
+#define PROC_MEM_PS_KV_MPKV3_FILECODE (0XF43E)
+#define PROC_MEM_PS_KV_MPSKV3_FILECODE (0XF43F)
+#define PROC_MEM_PS_KV_MPUKV3_FILECODE (0XF440)
+
+#define PROC_MEM_TECH_MT_FILECODE (0XF501)
+#define PROC_MEM_TECH_MTHDI_FILECODE (0XF502)
+#define PROC_MEM_TECH_MTTDIMBT_FILECODE (0XF504)
+#define PROC_MEM_TECH_MTTECC_FILECODE (0XF505)
+#define PROC_MEM_TECH_MTTHRC_FILECODE (0XF506)
+#define PROC_MEM_TECH_MTTML_FILECODE (0XF507)
+#define PROC_MEM_TECH_MTTOPTSRC_FILECODE (0XF509)
+#define PROC_MEM_TECH_MTTSRC_FILECODE (0XF50B)
+#define PROC_MEM_TECH_MTTEDGEDETECT_FILECODE (0XF50C)
+#define PROC_MEM_TECH_DDR3_MT3_FILECODE (0XF581)
+#define PROC_MEM_TECH_DDR3_MTOT3_FILECODE (0XF583)
+#define PROC_MEM_TECH_DDR3_MTRCI3_FILECODE (0XF584)
+#define PROC_MEM_TECH_DDR3_MTSDI3_FILECODE (0XF585)
+#define PROC_MEM_TECH_DDR3_MTSPD3_FILECODE (0XF586)
+#define PROC_MEM_TECH_DDR3_MTTWL3_FILECODE (0XF587)
+#define PROC_MEM_TECH_DDR3_MTTECC3_FILECODE (0XF588)
+#define PROC_MEM_TECH_DDR3_MTLRDIMM3_FILECODE (0XF589)
+#define PROC_MEM_TECH_MTTHRCSEEDTRAIN_FILECODE (0XF58A)
+#define PROC_MEM_TECH_MTTRDDQS2DTRAINING_FILECODE (0XF58B)
+#define PROC_MEM_TECH_MTTRDDQS2DEYERIMSEARCH_FILECODE (0XF58C)
+#define PROC_MEM_TECH_GDDR5_MNSPDG5_FILECODE (0XF58E)
+#define PROC_MEM_TECH_GDDR5_MNDCTG5_FILECODE (0xF58F)
+
+#define PROC_RECOVERY_MEM_MRDEF_FILECODE (0XF801)
+#define PROC_RECOVERY_MEM_MRINIT_FILECODE (0XF802)
+#define PROC_RECOVERY_MEM_MRM_FILECODE (0XF803)
+#define PROC_RECOVERY_MEM_MRUC_FILECODE (0XF804)
+#define PROC_RECOVERY_MEM_TECH_MRTTPOS_FILECODE (0XF8C1)
+#define PROC_RECOVERY_MEM_TECH_MRTTSRC_FILECODE (0XF8C2)
+#define PROC_RECOVERY_MEM_TECH_DDR3_MRT3_FILECODE (0XF8C3)
+#define PROC_RECOVERY_MEM_TECH_DDR3_MRTRCI3_FILECODE (0XF8C4)
+#define PROC_RECOVERY_MEM_TECH_DDR3_MRTSDI3_FILECODE (0XF8C5)
+#define PROC_RECOVERY_MEM_TECH_DDR3_MRTSPD3_FILECODE (0XF8C6)
+#define PROC_RECOVERY_MEM_TECH_DDR3_MRTTWL3_FILECODE (0XF8C7)
+#define PROC_RECOVERY_MEM_NB_MRN_FILECODE (0XF8C8)
+#define PROC_RECOVERY_MEM_NB_MRNDCT_FILECODE (0XF8C9)
+#define PROC_RECOVERY_MEM_NB_MRNMCT_FILECODE (0XF8CA)
+#define PROC_RECOVERY_MEM_NB_MRNTRAIN3_FILECODE (0XF8CB)
+#define PROC_RECOVERY_MEM_TECH_MRTTHRC_FILECODE (0XF8CC)
+#define PROC_RECOVERY_MEM_PS_MRP_FILECODE (0XF8E0)
+#define PROC_RECOVERY_MEM_PS_MRPRTT_FILECODE (0XF8E1)
+#define PROC_RECOVERY_MEM_PS_MRPODTPAT_FILECODE (0XF8E2)
+#define PROC_RECOVERY_MEM_PS_MRPSAO_FILECODE (0XF8E3)
+#define PROC_RECOVERY_MEM_PS_MRPMR0_FILECODE (0XF8E4)
+#define PROC_RECOVERY_MEM_PS_MRPRC2IBT_FILECODE (0XF8E5)
+#define PROC_RECOVERY_MEM_PS_MRPRC10OPSPD_FILECODE (0XF8E6)
+#define PROC_RECOVERY_MEM_PS_MRPLRIBT_FILECODE (0XF8E7)
+#define PROC_RECOVERY_MEM_PS_MRPLRNPR_FILECODE (0XF8E8)
+#define PROC_RECOVERY_MEM_PS_MRPLRNLR_FILECODE (0XF8E9)
+#define PROC_RECOVERY_MEM_NB_TN_MRNDCTTN_FILECODE (0XF8F3)
+#define PROC_RECOVERY_MEM_NB_TN_MRNTN_FILECODE (0XF8F4)
+#define PROC_RECOVERY_MEM_NB_TN_MRNMCTTN_FILECODE (0XF8F5)
+#define PROC_RECOVERY_MEM_NB_TN_MRNPROTOTN_FILECODE (0XF8F6)
+#define PROC_RECOVERY_MEM_PS_TN_MRPSTN3_FILECODE (0XF8F7)
+#define PROC_RECOVERY_MEM_PS_TN_MRPTN3_FILECODE (0XF8F8)
+#define PROC_RECOVERY_MEM_PS_TN_MRPUTN3_FILECODE (0XF8F9)
+#define PROC_RECOVERY_MEM_TECH_MRTTHRCSEEDTRAIN_FILECODE (0XF8FA)
+
+//Psp
+#define UEFI_PSP_DRIVERS_ITPMDXE_ITPMDXE_FILECODE (0xFA00)
+#define UEFI_PSP_DRIVERS_ITPMPEI_ITPMPEI_FILECODE (0xFA01)
+#define UEFI_PSP_DRIVERS_ITPMSMM_ITPMPSPCOMMAND_FILECODE (0xFA02)
+#define UEFI_PSP_DRIVERS_ITPMSMM_ITPMSMM_FILECODE (0xFA03)
+#define UEFI_PSP_DRIVERS_PSPPEI_PSPPEI_FILECODE (0xFA04)
+#define UEFI_PSP_DRIVERS_PSPSMM_PSPRESUMEHANDLING_FILECODE (0xFA05)
+#define UEFI_PSP_DRIVERS_PSPSMM_PSPRESUMESERVICES_FILECODE (0xFA06)
+#define UEFI_PSP_DRIVERS_PSPSMM_PSPSMM_FILECODE (0xFA07)
+#define UEFI_PSP_LIBRARY_PSPBASELIB_PSPBASELIB_FILECODE (0xFA08)
+#define UEFI_PSP_LIBRARY_PSPMBOX_PSPMBOX_FILECODE (0xFA09)
+#define UEFI_PSP_LIBRARY_SMMLOAD_SMMLOAD_FILECODE (0xFA0A)
+#define UEFI_PSP_DRIVERS_PSPDXE_PSPDXE_FILECODE (0xFA0B)
+#define UEFI_PSP_LIBRARY_PSPFTPMLIB_PSPFTPMLIB_FILECODE (0xFA0C)
+#define UEFI_PSP_LIBRARY_CCPSHALIB_CCPSHALIB_FILECODE (0xFA0D)
+
+#endif // _FILECODE_H_
diff --git a/src/vendorcode/amd/pi/00630F01/Include/Ids.h b/src/vendorcode/amd/pi/00630F01/Include/Ids.h
new file mode 100644
index 0000000..a0bc8ed
--- /dev/null
+++ b/src/vendorcode/amd/pi/00630F01/Include/Ids.h
@@ -0,0 +1,1428 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD IDS Routines
+ *
+ * Contains AMD AGESA Integrated Debug Macros
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: IDS
+ * @e \$Revision: 281181 $ @e \$Date: 2013-12-18 02:18:55 -0600 (Wed, 18 Dec 2013) $
+ */
+/*****************************************************************************
+ *
+ * Copyright 2008 - 2014 ADVANCED MICRO DEVICES, INC. All Rights Reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ***************************************************************************/
+
+ /* Macros to aid debugging */
+ /* These definitions expand to zero (0) bytes of code when disabled */
+
+#ifndef _IDS_H_
+#define _IDS_H_
+
+#undef FALSE
+#undef TRUE
+#define FALSE 0
+#define TRUE 1
+// Proto type for optionsids.h
+typedef UINT32 IDS_STATUS; ///< Status of IDS function.
+#define IDS_SUCCESS ((IDS_STATUS) 0x00000000ul) ///< IDS Function is Successful.
+#define IDS_UNSUPPORTED ((IDS_STATUS) 0xFFFFFFFFul) ///< IDS Function is not existed.
+
+#define IDS_STRINGIZE(a) #a ///< for define stringize macro
+#ifndef IDS_DEADLOOP
+ #define IDS_DEADLOOP() { volatile UINTN __i; __i = 1; while (__i); }
+#endif
+/**
+ * IDS Option Hook Points
+ *
+ * These are the values to indicate hook point in AGESA for IDS Options.
+ *
+ */
+typedef enum { //vv- for debug reference only
+ IDS_INIT_EARLY_BEFORE, ///< 00 Option Hook Point before AGESA function AMD_INIT_EARLY.
+ ///< IDS Object is initialized.
+ ///< Override CPU Core Leveling Mode.
+ ///< Set P-State in Post
+ IDS_INIT_EARLY_AFTER, ///< 01 Option Hook Point after AGESA function AMD_INIT_EARLY.
+ IDS_INIT_LATE_BEFORE, ///< 02 Option Hook Point before AGESA function AMD_INIT_LATE.
+ ///< It will be used to control the following tables.
+ ///< ACPI P-State Table (_PSS, XPSS, _PCT, _PSD, _PPC)
+ ///< ACPI SRAT Table
+ ///< ACPI SLIT Table
+ ///< ACPI WHEA Table
+ ///< DMI Table
+ IDS_INIT_LATE_AFTER, ///< 03 Option Hook Point after AGESA function AMD_INIT_LATE.
+ IDS_INIT_MID_BEFORE, ///< 04 Option Hook Point before AGESA function AMD_INIT_MID.
+ IDS_INIT_MID_AFTER, ///< 05 Option Hook Point after AGESA function AMD_INIT_MID.
+ IDS_INIT_POST_BEFORE, ///< 06 Option Hook Point before AGESA function AMD_INIT_POST.
+ ///< Control Interleaving and DRAM memory hole
+ ///< Override the setting of ECC Control
+ ///< Override the setting of Online Spare Rank
+ IDS_INIT_POST_AFTER, ///< 07 Option Hook Point after AGESA function AMD_INIT_POST.
+ IDS_INIT_RESET_BEFORE, ///< 08 Option Hook Point before AGESA function AMD_INIT_RESET.
+ IDS_INIT_RESET_AFTER, ///< 09 Option Hook Point after AGESA function AMD_INIT_RESET.
+ IDS_INIT_POST_MID, ///< 0a Option Hook Point after AGESA function AMD_INIT_POST.
+ IDS_BEFORE_S3_SAVE, ///< 0b override any settings before S3 save.
+ IDS_BEFORE_S3_RESTORE, ///< 0c override any settings before S3 restore
+ IDS_AFTER_S3_SAVE, ///< 0d Override any settings after S3 save
+ IDS_AFTER_S3_RESTORE, ///< 0e Override any settings after S3 restore
+ IDS_BEFORE_DQS_TRAINING, ///< 0f override any settings before DQS training
+ IDS_BEFORE_DRAM_INIT, ///< 10 override any settings before Dram initialization
+ IDS_BEFORE_MEM_FREQ_CHG, ///< 11 override settings before MemClk frequency change
+ IDS_BEFORE_WARM_RESET , ///< 12 Override PCI or MSR Registers Before Warm Reset
+ IDS_BEFORE_PCI_INIT, ///< 13 Override PCI or MSR Registers Before PCI Init
+ IDS_BEFORE_AP_EARLY_HALT, ///< 14 Option Hook Point before AP early halt
+ IDS_BEFORE_S3_RESUME, ///< 15 Option Hook Point before s3 resume
+ IDS_AFTER_S3_RESUME, ///< 16 Option Hook Point after s3 resume
+ IDS_BEFORE_PM_INIT, ///< 17 Option Hook Point Before Pm Init
+
+ IDS_MT_BASE = 0x20, ///< 0x20 ~ 0x38 24 time points reserved for MTTime
+
+ IDS_PLATFORM_RSVD1 = 0x38, ///< from 0x38 to 0x3f will reserved for platform used
+ IDS_PLATFORM_RSVD2 = 0x39, ///< from 0x38 to 0x3f will reserved for platform used
+ IDS_PLATFORM_RSVD3 = 0x3a, ///< from 0x38 to 0x3f will reserved for platform used
+ IDS_PLATFORM_RSVD4 = 0x3b, ///< from 0x38 to 0x3f will reserved for platform used
+ IDS_PLATFORM_RSVD5 = 0x3c, ///< from 0x38 to 0x3f will reserved for platform used
+ IDS_PLATFORM_RSVD6 = 0x3d, ///< from 0x38 to 0x3f will reserved for platform used
+ IDS_PLATFORM_RSVD7 = 0x3e, ///< from 0x38 to 0x3f will reserved for platform used
+ IDS_PLATFORM_RSVD8 = 0x3f, ///< from 0x38 to 0x3f will reserved for platform used
+
+ // All the above timing point is used by BVM, their value should never be changed
+ IDS_INIT_DRAM_TABLE, ///< 40 Generate override table for Dram Timing
+ ///< Dram Controller, Drive Strength and DQS Timing
+ IDS_GET_DRAM_TABLE, ///< 41 Generate override table for Dram Timing
+ IDS_GANGING_MODE, ///< 42 override Memory Mode Unganged
+ IDS_POWERDOWN_MODE, ///< 43 override Power Down Mode
+ IDS_BURST_LENGTH32, ///< 44 override Burst Length32
+ IDS_ALL_MEMORY_CLOCK, ///< 45 override All Memory Clks Enable
+ IDS_ECC, ///< 46 override ECC parameter
+ IDS_ECCSYMBOLSIZE, ///< 47 override ECC symbol size
+ IDS_CPU_Early_Override, ///< 48 override CPU early parameter
+ IDS_CACHE_FLUSH_HLT, ///< 49 override Cache Flush Hlt
+ IDS_CHANNEL_INTERLEAVE, ///< 4a override Channel Interleave
+ IDS_MEM_ERROR_RECOVERY, ///< 4b override memory error recovery
+ IDS_MEM_RETRAIN_TIMES, ///< 4c override memory retrain times
+ IDS_MEM_SIZE_OVERLAY, ///< 4d Override the syslimit
+ IDS_CHECK_NEGATIVE_WL, ///< 4e Check for negative write leveling result
+ IDS_DLL_SHUT_DOWN, ///< 4f Check for Dll Shut Down
+ IDS_POR_MEM_FREQ, ///< 50 Entry to enable/disable MemClk frequency enforcement
+ IDS_PHY_DLL_STANDBY_CTRL, ///< 51 Enable/Disable Phy DLL standby feature
+ IDS_PLATFORMCFG_OVERRIDE, ///< 52 Hook for Override PlatformConfig structure
+ IDS_LOADCARD_ERROR_RECOVERY, ///< 53 Special error handling for load card support
+ IDS_MEM_IGNORE_ERROR, ///< 54 Ignore error and do not do fatal exit in memory
+ IDS_GNB_SMU_SERVICE_CONFIG, ///< 55 Config GNB SMU service
+ IDS_GNB_ORBDYNAMIC_WAKE, ///< 56 config GNB dynamic wake
+ IDS_GNB_PLATFORMCFG_OVERRIDE, ///< 57 override ids gnb platform config
+ IDS_GNB_LCLK_DPM_EN, ///< 58 override GNB LCLK DPM configuration
+ IDS_GNB_LCLK_DEEP_SLEEP, ///< 59 override GNB LCLK DPM deep sleep
+ IDS_GNB_CLOCK_GATING, ///< 5a Override GNB Clock gating config
+ IDS_NB_PSTATE_DIDVID, ///< 5b Override NB P-state settings
+ IDS_CPB_CTRL, ///< 5c Config the Core peformance boost feature
+ IDS_HTC_CTRL, ///< 5d Hook for Hardware Thermal Control
+ IDS_CC6_WORKAROUND, ///< 5e Hook for skip CC6 work around
+ IDS_MEM_MR0, ///< 5f Hook for override Memory Mr0 register
+ IDS_TRAP_TABLE, ///< 60 Hook for add IDS register table to the loop
+ IDS_NBBUFFERALLOCATIONATEARLY, ///< 61 Hook for override North bridge bufer allocation
+ IDS_BEFORE_S3_SPECIAL, ///< 62 Hook to bypass S3 special functions
+ IDS_SET_PCI_REGISTER_ENTRY, ///< 63 Hook to SetRegisterForPciEntry
+ IDS_ERRATUM463_WORKAROUND, ///< 64 Hook to Erratum 463 workaround
+ IDS_BEFORE_MEMCLR, ///< 65 Hook before set Memclr bit
+ IDS_OVERRIDE_IO_CSTATE, ///< 66 Hook for override io C-state setting
+ IDS_NBPSDIS_OVERRIDE, ///< 67 Hook for override NB pstate disable setting
+ IDS_NBPS_REG_OVERRIDE, ///< 68 Hook for override Memory NBps reg
+ IDS_LOW_POWER_PSTATE, ///< 69 Hook for disable Low power_Pstates feature
+ IDS_CST_CREATE, ///< 6a Hook for create _CST
+ IDS_CST_SIZE, ///< 6b Hook for get _CST size
+ IDS_ENFORCE_VDDIO, ///< 6c Hook to override VDDIO
+ IDS_STRETCH_FREQUENCY_LIMIT, ///< 6d Hook for enforcing memory stretch frequency limit
+ IDS_INIT_MEM_REG_TABLE, ///< 6e Hook for init memory register table
+ IDS_SKIP_FUSED_MAX_RATE, ///< 6f Hook to skip fused max rate cap
+ IDS_FCH_INIT_AT_RESET, ///< 70 Hook for FCH reset parameter
+ IDS_FCH_INIT_AT_ENV, ///< 71 Hook for FCH ENV parameter
+ IDS_ENFORCE_PLAT_TABLES, ///< 72 Hook to enforce platform specific tables
+ IDS_NBPS_MIN_FREQ, ///< 73 Hook for override MIN nb ps freq
+ IDS_GNB_FORCE_CABLESAFE, ///< 74 Hook for override Force Cable Safe
+ IDS_SKIP_PM_TRANSITION_STEP, ///< 75 Hook for provide IDS ability to skip this PM step
+ IDS_GNB_PROPERTY, ///< 76 Hook for GNB Property
+ IDS_GNB_PCIE_POWER_GATING, ///< 77 Hook for GNB PCIe Power Gating
+ IDS_MEM_DYN_DRAM_TERM, ///< 78 Hook for Override Dynamic Dram Term
+ IDS_MEM_DRAM_TERM, ///< 79 Hook for Override Dram Term
+ IDS_GNB_ALTVDDNB, ///< 7a Hook for Override AltVddNB
+ IDS_UCODE, ///< 7b Enable or Disable microcode patching
+ IDS_FAM_REG_GMMX, ///< 7c GMMX register access
+ IDS_MEMORY_POWER_POLICY, ///< 7d Memory power policy
+ IDS_GET_STRETCH_FREQUENCY_LIMIT, ///< 7e Hook for enforcing memory stretch frequency limit
+ IDS_CPU_FEAT, ///< 7f Hook for runtime force cpu feature disable
+ IDS_AFTER_DCT_PHY_ACCESS, ///< 80 Hook for DctAccessDone check
+ IDS_FORCE_PHY_TO_M0, ///< 81 Hook to bypass M0 enforcement
+ IDS_GNB_PMM_SWTJOFFSET, ///< 82 Hook to GNBSWTJOFFSET
+ IDS_LOCK_DRAM_CFG, ///< 83 Hook to BFLockDramCfg
+ IDS_BEFORE_GEN2_INIT, ///< 84 Hook to Before Gen2 Init
+ IDS_BEFORE_GPP_TRAINING, ///< 85 Hook to Before Gpp training
+ IDS_BEFORE_RECONFIGURATION, ///< 86 Hook to Before Reconfiguration
+ IDS_BEFORE_GEN3_INIT, ///< 87 Hook to Before Gen3 Init
+ IDS_BEFORE_POWER_GATING, ///< 88 Hook to Before Power Gating
+ IDS_AFTER_EARLY_INIT_ONCORE, ///< 89 Hook to after EarlyInit On Core
+ IDS_GNB_PCIE_PORT_REMAP, ///< 8a Hook to change mapping of PCIe devices
+ IDS_ECC_CONTROL, ///< 8b Enable/Disable ECC feature
+ IDS_GNB_PCIE_PHY_ISOLATION, ///< 8c Enable/Disable PCIE PHY ISOLATION
+ IDS_AFTER_RESTORING_PCI_REG, ///< 8d Hook after restoring PCI register during S3 resume
+ IDS_MSR_ACCESS_OVERRIDE, ///< 8e Hook to disable MSR access
+ IDS_REPORT_SMU_FW_VERSION, ///< 8f Hook to report SMU firmware version
+ IDS_GNB_LOAD_SAMU_PATCH, ///< 90 Hook to Load SAMU patch
+ IDS_DLLSTAGGERDLY_OVERRIDE, ///< 91 Hook to skip Dll Stagger Delay
+ IDS_CSAMPLE_TIMER, ///< 92 Hook to override CSampleTimer
+ IDS_PIPE_THROTTLE, ///< 93 Hook to override PipeThrottle
+ IDS_GNB_PMM_NATIVEGEN1PLL, ///< 94 Enable/Disable Native Gen1 PLL
+ IDS_BEFORE_PLAT_TABLES, ///< 95 Hook before processing platform specific tables
+ IDS_GNB_PCIE_MASTERPLL_SELECTION, ///< 96 Hook to override PCIe Master PLL selection
+ IDS_GNB_PCIE_PHYLANE_CONFIG, ///< 97 Hook to override PCIe PhyLane configuration
+ IDS_DSM_LP_SELECTION, ///< 98 Set Dsm low power mode
+ IDS_GNB_EQUAL_PRESET, ///< 99 Set equalization preset
+ IDS_GNB_GEN1_LOOPBACK, ///< 9a Override Gen 1 loopback mode
+ IDS_GNB_SMU_SERVICE_MASK, ///< 9b Override SMU service enablement mask
+ IDS_BEFORE_HT_MEM_MAP, ///< 9c Hook before mapping memory address space among DCTs
+ IDS_GNB_GEN3_SETTINGS_OVERRIDE, ///< 9d Hook to override Gen3 Adapt PI Offset Bypass Enable
+ IDS_GNB_TARGET_TDP, ///< 9e Hook to override Target TDP
+ IDS_GNB_LOAD_BUILD_OPTIONS, ///< 9f Hook to override gnb build options
+ IDS_GNB_SMU_BIOS_TABLE, ///< A0 Hook to override gnb smu bios table
+ IDS_OPTION_END ///< A1 End of IDS option
+} AGESA_IDS_OPTION;
+
+#include "OptionsIds.h"
+#include "Filecode.h"
+#include "IdsPerf.h"
+
+/* Initialize IDS controls */
+#ifndef IDSOPT_IDS_ENABLED
+ #define IDSOPT_IDS_ENABLED FALSE
+#endif
+
+#ifndef IDSOPT_CONTROL_ENABLED
+ #define IDSOPT_CONTROL_ENABLED FALSE
+#endif
+
+#ifndef IDSOPT_CONTROL_NV_TO_CMOS
+ #define IDSOPT_CONTROL_NV_TO_CMOS FALSE
+#endif
+
+#ifndef IDSOPT_TRACING_ENABLED
+ #define IDSOPT_TRACING_ENABLED FALSE
+#endif
+
+#ifndef IDSOPT_TRACE_USER_OPTIONS
+ #define IDSOPT_TRACE_USER_OPTIONS TRUE
+#endif
+
+#ifndef IDSOPT_PERF_ANALYSIS
+ #define IDSOPT_PERF_ANALYSIS FALSE
+#endif
+
+#ifndef IDSOPT_HEAP_CHECKING
+ #define IDSOPT_HEAP_CHECKING FALSE
+#endif
+
+#ifndef IDSOPT_ASSERT_ENABLED
+ #define IDSOPT_ASSERT_ENABLED FALSE
+#endif
+
+#ifndef IDSOPT_ERROR_TRAP_ENABLED
+ #define IDSOPT_ERROR_TRAP_ENABLED FALSE
+#endif
+
+#ifndef IDSOPT_CAR_CORRUPTION_CHECK_ENABLED
+ #define IDSOPT_CAR_CORRUPTION_CHECK_ENABLED FALSE
+#endif
+
+#ifndef IDSOPT_DEBUG_CODE_ENABLED
+ #define IDSOPT_DEBUG_CODE_ENABLED FALSE
+#endif
+
+#ifndef IDSOPT_IDT_EXCEPTION_TRAP
+ #define IDSOPT_IDT_EXCEPTION_TRAP FALSE
+#endif
+
+#ifndef IDSOPT_C_OPTIMIZATION_DISABLED
+ #define IDSOPT_C_OPTIMIZATION_DISABLED FALSE
+#endif
+
+#ifndef IDSOPT_TRACING_CONSOLE_HDTOUT
+ #define IDSOPT_TRACING_CONSOLE_HDTOUT TRUE
+#endif
+
+#ifndef IDSOPT_TRACING_CONSOLE_SERIALPORT
+ #define IDSOPT_TRACING_CONSOLE_SERIALPORT FALSE
+#endif
+
+#ifndef IDSOPT_TRACING_CONSOLE_REDIRECT_IO
+ #define IDSOPT_TRACING_CONSOLE_REDIRECT_IO FALSE
+#endif
+
+#ifndef IDSOPT_TRACING_CONSOLE_RAM
+ #define IDSOPT_TRACING_CONSOLE_RAM FALSE
+#endif
+
+#if IDSOPT_IDS_ENABLED == FALSE
+ #undef IDSOPT_CONTROL_ENABLED
+ #undef IDSOPT_TRACING_ENABLED
+ #undef IDSOPT_PERF_ANALYSIS
+ #undef IDSOPT_HEAP_CHECKING
+ #undef IDSOPT_ASSERT_ENABLED
+ #undef IDSOPT_ERROR_TRAP_ENABLED
+ #undef IDSOPT_CAR_CORRUPTION_CHECK_ENABLED
+ #undef IDSOPT_DEBUG_CODE_ENABLED
+ #undef IDSOPT_TRACE_USER_OPTIONS
+ #undef IDSOPT_TRACING_CONSOLE_HDTOUT
+ #undef IDSOPT_TRACING_CONSOLE_SERIALPORT
+ #undef IDSOPT_TRACING_CONSOLE_REDIRECT_IO
+ #undef IDSOPT_TRACING_CONSOLE_RAM
+
+ #define IDSOPT_CONTROL_ENABLED FALSE
+ #define IDSOPT_TRACING_ENABLED FALSE
+ #define IDSOPT_PERF_ANALYSIS FALSE
+ #define IDSOPT_HEAP_CHECKING FALSE
+ #define IDSOPT_ASSERT_ENABLED FALSE
+ #define IDSOPT_ERROR_TRAP_ENABLED FALSE
+ #define IDSOPT_CAR_CORRUPTION_CHECK_ENABLED FALSE
+ #define IDSOPT_DEBUG_CODE_ENABLED FALSE
+ #define IDSOPT_TRACE_USER_OPTIONS FALSE
+ #define IDSOPT_TRACING_CONSOLE_HDTOUT FALSE
+ #define IDSOPT_TRACING_CONSOLE_SERIALPORT FALSE
+ #define IDSOPT_TRACING_CONSOLE_REDIRECT_IO FALSE
+ #define IDSOPT_TRACING_CONSOLE_RAM FALSE
+#endif
+
+//Disable when master token Tracing is set to FALSE
+#if (IDSOPT_TRACING_ENABLED == FALSE) || (defined (IDSOPT_CUSTOMIZE_TRACING_SERVICE))
+ #undef IDSOPT_TRACING_CONSOLE_HDTOUT
+ #define IDSOPT_TRACING_CONSOLE_HDTOUT FALSE
+
+ #undef IDSOPT_TRACING_CONSOLE_SERIALPORT
+ #define IDSOPT_TRACING_CONSOLE_SERIALPORT FALSE
+
+ #undef IDSOPT_TRACING_CONSOLE_REDIRECT_IO
+ #define IDSOPT_TRACING_CONSOLE_REDIRECT_IO FALSE
+
+ #undef IDSOPT_TRACING_CONSOLE_RAM
+ #define IDSOPT_TRACING_CONSOLE_RAM FALSE
+#endif
+
+//Disable Tracing if all support HW layer set to FALSE
+#if ((IDSOPT_TRACING_CONSOLE_HDTOUT == FALSE) && (IDSOPT_TRACING_CONSOLE_SERIALPORT == FALSE) && (IDSOPT_TRACING_CONSOLE_REDIRECT_IO == FALSE) && (IDSOPT_TRACING_CONSOLE_RAM == FALSE))
+ #ifndef IDSOPT_CUSTOMIZE_TRACING_SERVICE
+ #undef IDSOPT_TRACING_ENABLED
+ #define IDSOPT_TRACING_ENABLED FALSE
+ #endif
+#endif
+/**
+ * Make a Progress Report to the User.
+ *
+ * This Macro is always enabled. The default action is to write the TestPoint value
+ * to an I/O port. The I/O port is 8 bits in size and the default address is 0x80.
+ * IBVs can change AGESA's default port by defining IDS_DEBUG_PORT to desired port
+ * in OptionsIds.h in their build tip.
+ *
+ * @param[in] TestPoint The value for display indicating progress
+ * @param[in,out] StdHeader Pointer of AMD_CONFIG_PARAMS
+ *
+ **/
+
+#define AGESA_TESTPOINT(TestPoint, StdHeader) IdsAgesaTestPoint ((TestPoint), (StdHeader))
+
+#ifndef IDS_DEBUG_PORT
+ #define IDS_DEBUG_PORT 0x80
+#endif
+
+/**
+ * @def STOP_HERE
+ * (macro) - Causes program to halt. This is @b only for use during active debugging .
+ *
+ * Causes the program to halt and display the file number of the source of the
+ * halt (displayed in decimal).
+ *
+ **/
+#if IDSOPT_IDS_ENABLED == TRUE
+ #ifdef STOP_CODE
+ #undef STOP_CODE
+ #endif
+ #define STOP_CODE (((UINT32)FILECODE)*0x10000ul + \
+ ((__LINE__) % 10) + (((__LINE__ / 10) % 10)*0x10) + \
+ (((__LINE__ / 100) % 10)*0x100) + (((__LINE__ / 1000) % 10)*0x1000))
+ #define STOP_HERE IdsErrorStop (STOP_CODE);
+#else
+ #define STOP_HERE STOP_HERE_Needs_To_Be_Removed //"WARNING: Debug code needs to be removed for production builds."
+#endif
+
+/**
+ * @def ASSERT
+ * Test an assertion that the given statement is True.
+ *
+ * The statement is evaluated to a boolean value. If the statement is True,
+ * then no action is taken (no error). If the statement is False, a error stop
+ * is generated to halt the program. Used for testing for fatal errors that
+ * must be resolved before production. This is used to do parameter checks,
+ * bounds checking, range checks and 'sanity' checks.
+ *
+ * @param[in] conditional Assert that evaluating this conditional results in TRUE.
+ *
+ **/
+#ifndef ASSERT
+ #if IDSOPT_ASSERT_ENABLED == TRUE
+ #ifdef STOP_CODE
+ #undef STOP_CODE
+ #endif
+ #define STOP_CODE (((UINT32)FILECODE)*0x10000ul + \
+ ((__LINE__) % 10) + (((__LINE__ / 10) % 10)*0x10) + \
+ (((__LINE__ / 100) % 10)*0x100) + (((__LINE__ / 1000) % 10)*0x1000))
+
+ #define ASSERT(conditional) ((conditional) ? 0 : IdsAssert (STOP_CODE));
+ #else
+ #define ASSERT(conditional)
+ #endif
+#endif
+
+#if IDSOPT_CAR_CORRUPTION_CHECK_ENABLED == TRUE
+ #undef IDSOPT_ERROR_TRAP_ENABLED
+ #define IDSOPT_ERROR_TRAP_ENABLED TRUE
+ #define IDS_CAR_CORRUPTION_CHECK(StdHeader) IdsCarCorruptionCheck(StdHeader)
+#else
+ #define IDS_CAR_CORRUPTION_CHECK(StdHeader)
+#endif
+/**
+ * @def DEBUG_CODE
+ * Make the code active when IDSOPT_DEBUG_CODE_ENABLED enable
+ *
+ */
+#ifndef DEBUG_CODE
+ #if IDSOPT_DEBUG_CODE_ENABLED == TRUE
+ #define DEBUG_CODE(Code) Code
+ #else
+ #define DEBUG_CODE(Code)
+ #endif
+#endif
+
+/**
+ * @def IDS_ERROR_TRAP
+ * Trap AGESA Error events with stop code display.
+ *
+ * Works similarly to use of "ASSERT (FALSE);"
+ *
+ */
+#if IDSOPT_ERROR_TRAP_ENABLED == TRUE
+ #ifdef STOP_CODE
+ #undef STOP_CODE
+ #endif
+ #define STOP_CODE (((UINT32)FILECODE)*0x10000ul + \
+ ((__LINE__) % 10) + (((__LINE__ / 10) % 10)*0x10) + \
+ (((__LINE__ / 100) % 10)*0x100) + (((__LINE__ / 1000) % 10)*0x1000))
+
+ #define IDS_ERROR_TRAP IdsErrorStop (STOP_CODE)
+#else
+ #define IDS_ERROR_TRAP
+#endif
+
+///give the extended Macro default value
+#ifndef __IDS_EXTENDED__
+ #define IDS_EXTENDED_HOOK(idsoption, dataptr, idsnvptr, stdheader) IDS_SUCCESS
+ #define IDS_TRACE_DEFAULT (0)
+ #define IDS_INITIAL_F15_TN_PM_STEP
+ #define IDS_INITIAL_F15_KV_PM_STEP
+ #define IDS_F15_TN_PM_CUSTOM_STEP
+ #define IDS_F15_KV_PM_CUSTOM_STEP
+ #define IDS_EXTENDED_GET_DATA_EARLY(data, StdHeader)
+ #define IDS_EXTENDED_GET_DATA_LATE(data, StdHeader)
+ #define IDS_EXTENDED_HEAP_SIZE 0
+ #define IDS_EXT_INCLUDE_F15(file)
+ #define IDS_EXT_INCLUDE(file)
+ #define IDS_PAD_4K
+ #define IDS_EXTENDED_CODE(code)
+ #define SMU_FIRMWARE_PADS_1K
+#endif
+
+#ifndef IDS_NUM_NV_ITEM
+ #define IDS_NUM_NV_ITEM (IDS_NUM_EXT_NV_ITEM)
+#endif
+
+#define IDS_CMOS_INDEX_PORT 0x70
+#define IDS_CMOS_DATA_PORT 0x71
+#define IDS_CMOS_REGION_START 0x20
+#define IDS_CMOS_REGION_END 0x7F
+#define IDS_AP_GET_NV_FROM_CMOS(x) FALSE
+
+#if IDSOPT_CONTROL_ENABLED == TRUE
+ #define IDS_OPTION_HOOK(IdsOption, DataPtr, StdHeader) \
+ AmdIdsCtrlDispatcher ((IdsOption), (DataPtr), (StdHeader))
+
+ #define IDS_OPTION_CALLOUT(CallOutId, DataPtr, StdHeader) \
+ IdsOptionCallout ((CallOutId), (DataPtr), (StdHeader))
+ #if IDSOPT_CONTROL_NV_TO_CMOS == TRUE
+ #undef IDS_AP_GET_NV_FROM_CMOS
+ #define IDS_AP_GET_NV_FROM_CMOS(x) AmdIdsApGetNvFromCmos(x)
+ #ifdef IDS_OPT_CMOS_INDEX_PORT
+ #undef IDS_CMOS_INDEX_PORT
+ #define IDS_CMOS_INDEX_PORT IDS_OPT_CMOS_INDEX_PORT
+ #endif
+
+ #ifdef IDS_OPT_CMOS_DATA_PORT
+ #undef IDS_CMOS_DATA_PORT
+ #define IDS_CMOS_DATA_PORT IDS_OPT_CMOS_DATA_PORT
+ #endif
+
+ #ifdef IDS_OPT_CMOS_REGION_START
+ #undef IDS_CMOS_REGION_START
+ #define IDS_CMOS_REGION_START IDS_OPT_CMOS_REGION_START
+ #endif
+
+ #ifdef IDS_OPT_CMOS_REGION_END
+ #undef IDS_CMOS_REGION_END
+ #define IDS_CMOS_REGION_END IDS_OPT_CMOS_REGION_END
+ #endif
+ #endif
+#else
+ #define IDS_OPTION_HOOK(IdsOption, DataPtr, StdHeader)
+
+ #define IDS_OPTION_CALLOUT(CallOutId, DataPtr, StdHeader) AGESA_SUCCESS
+#endif
+
+/**
+ * Macro to add a *skip* hook for IDS options
+ *
+ * The default minimal action is to do nothing and there is no any code to increase.
+ * For debug environments, IDS dispatcher function will be called to perform
+ * the detailed action and to skip AGESA code if necessary.
+ *
+ * @param[in] IdsOption IDS Option ID for this hook point
+ * @param[in, out] DataPtr Data Pointer to override
+ * @param[in, out] StdHeader Pointer of AMD_CONFIG_PARAMS
+ *
+ *
+ **/
+
+#if IDSOPT_CONTROL_ENABLED == TRUE
+ #define IDS_SKIP_HOOK(IdsOption, DataPtr, StdHeader) \
+ if (AmdIdsCtrlDispatcher (IdsOption, DataPtr, StdHeader) == IDS_SUCCESS)
+#else
+ #define IDS_SKIP_HOOK(IdsOption, DataPtr, StdHeader)
+#endif
+
+/**
+ * Macro to add a heap manager routine
+ *
+ * when memory is allocated the heap manager actually allocates two extra dwords of data,
+ * one dword buffer before the actual memory, and one dword afterwards.
+ * a complete heap walk and check to be performed at any time.
+ * it would ASSERT if the heap is corrupt
+ *
+ * @param[in] StdHeader Pointer of AMD_CONFIG_PARAMS
+ *
+ *
+ **/
+
+// Heap debug feature
+#define SENTINEL_BEFORE_VALUE 0x64616548ul // "Head"
+#define SENTINEL_AFTER_VALUE 0x6C696154ul // "Tail"
+#if IDSOPT_IDS_ENABLED == TRUE
+ #if IDSOPT_HEAP_CHECKING == TRUE
+ #define SIZE_OF_SENTINEL 4
+ #define NUM_OF_SENTINEL 2 // Before ("Head") and After ("Tail")
+ #define SET_SENTINEL_BEFORE(NodePtr, AlignTo16Byte) (*(UINT32 *) ((UINT8 *) NodePtr + sizeof (BUFFER_NODE) + AlignTo16Byte) = SENTINEL_BEFORE_VALUE);
+ #define SET_SENTINEL_AFTER(NodePtr) (*(UINT32 *) ((UINT8 *) NodePtr + sizeof (BUFFER_NODE) + NodePtr->BufferSize - SIZE_OF_SENTINEL) = SENTINEL_AFTER_VALUE);
+ #define Heap_Check(stdheader) AmdHeapIntactCheck(stdheader)
+ #else
+ #define SIZE_OF_SENTINEL 0
+ #define NUM_OF_SENTINEL 0
+ #define SET_SENTINEL_BEFORE(NodePtr, AlignTo16Byte)
+ #define SET_SENTINEL_AFTER(NodePtr)
+ #define Heap_Check(stdheader)
+ #endif
+#else
+ #define SIZE_OF_SENTINEL 0
+ #define NUM_OF_SENTINEL 0
+ #define SET_SENTINEL_BEFORE(NodePtr, AlignTo16Byte)
+ #define SET_SENTINEL_AFTER(NodePtr)
+ #define Heap_Check(stdheader)
+#endif
+
+/**
+ * Macro to add IDT for debugging exception.
+ *
+ * A debug feature. Adding a 'jmp $' into every exception handler.
+ * So debugger could use HDT to skip 'jmp $' and execute the iret,
+ * then they could find which instruction cause the exception.
+ *
+ * @param[in] FunctionId IDS Function ID for this hook point
+ * @param[in, out] DataPtr Data Pointer to override
+ * @param[in, out] StdHeader Pointer of AMD_CONFIG_PARAMS
+ *
+ *
+ **/
+#if IDSOPT_IDS_ENABLED == TRUE
+ #if IDSOPT_IDT_EXCEPTION_TRAP == TRUE
+ #define IDS_EXCEPTION_TRAP(FunctionId, DataPtr, StdHeader) IdsExceptionTrap (FunctionId, DataPtr, StdHeader)
+ #else
+ #define IDS_EXCEPTION_TRAP(FunctionId, DataPtr, StdHeader)
+ #endif
+#else
+ #define IDS_EXCEPTION_TRAP(FunctionId, DataPtr, StdHeader)
+#endif
+
+
+ //Note a is from 0 to 63
+#define DEBUG_PRINT_SHIFT(a) ((UINT64)1 << a)
+//If you change the Bitmap definition below, please change the Hash in ParseFilter of hdtout2008.pl accordingly
+//Memory Masks
+#define MEM_SETREG DEBUG_PRINT_SHIFT (0)
+#define MEM_GETREG DEBUG_PRINT_SHIFT (1)
+#define MEM_FLOW DEBUG_PRINT_SHIFT (2)
+#define MEM_STATUS DEBUG_PRINT_SHIFT (3)
+#define MEM_UNDEF_BF DEBUG_PRINT_SHIFT (4)
+#define MEMORY_TRACE_RSV2 DEBUG_PRINT_SHIFT (5)
+#define MEMORY_TRACE_RSV3 DEBUG_PRINT_SHIFT (6)
+#define MEMORY_TRACE_RSV4 DEBUG_PRINT_SHIFT (7)
+#define MEMORY_TRACE_RSV5 DEBUG_PRINT_SHIFT (8)
+#define MEMORY_TRACE_RSV6 DEBUG_PRINT_SHIFT (9)
+
+//CPU Masks
+#define CPU_TRACE DEBUG_PRINT_SHIFT (10)
+#define CPU_TRACE_RSV1 DEBUG_PRINT_SHIFT (11)
+#define CPU_TRACE_RSV2 DEBUG_PRINT_SHIFT (12)
+#define CPU_TRACE_RSV3 DEBUG_PRINT_SHIFT (13)
+#define CPU_TRACE_RSV4 DEBUG_PRINT_SHIFT (14)
+#define CPU_TRACE_RSV5 DEBUG_PRINT_SHIFT (15)
+#define CPU_TRACE_RSV6 DEBUG_PRINT_SHIFT (16)
+#define CPU_TRACE_RSV7 DEBUG_PRINT_SHIFT (17)
+#define CPU_TRACE_RSV8 DEBUG_PRINT_SHIFT (18)
+#define CPU_TRACE_RSV9 DEBUG_PRINT_SHIFT (19)
+
+//GNB Masks
+#define GNB_TRACE DEBUG_PRINT_SHIFT (20)
+#define PCIE_MISC DEBUG_PRINT_SHIFT (21)
+#define PCIE_PORTREG_TRACE DEBUG_PRINT_SHIFT (22)
+#define PCIE_HOSTREG_TRACE DEBUG_PRINT_SHIFT (23)
+#define GNB_TRACE_RSV2 DEBUG_PRINT_SHIFT (24)
+#define NB_MISC DEBUG_PRINT_SHIFT (25)
+#define GNB_TRACE_RSV3 DEBUG_PRINT_SHIFT (26)
+#define GFX_MISC DEBUG_PRINT_SHIFT (27)
+#define NB_SMUREG_TRACE DEBUG_PRINT_SHIFT (28)
+#define GNB_TRACE_RSV1 DEBUG_PRINT_SHIFT (29)
+
+//Topology Masks
+#define TOPO_TRACE DEBUG_PRINT_SHIFT (30)
+#define TOPO_TRACE_RSV1 DEBUG_PRINT_SHIFT (31)
+#define TOPO_TRACE_RSV2 DEBUG_PRINT_SHIFT (32)
+#define TOPO_TRACE_RSV3 DEBUG_PRINT_SHIFT (33)
+#define TOPO_TRACE_RSV4 DEBUG_PRINT_SHIFT (34)
+#define TOPO_TRACE_RSV5 DEBUG_PRINT_SHIFT (35)
+#define TOPO_TRACE_RSV6 DEBUG_PRINT_SHIFT (36)
+#define TOPO_TRACE_RSV7 DEBUG_PRINT_SHIFT (37)
+#define TOPO_TRACE_RSV8 DEBUG_PRINT_SHIFT (38)
+#define TOPO_TRACE_RSV9 DEBUG_PRINT_SHIFT (39)
+
+//FCH Masks
+#define FCH_TRACE DEBUG_PRINT_SHIFT (40)
+#define FCH_TRACE_RSV1 DEBUG_PRINT_SHIFT (41)
+#define FCH_TRACE_RSV2 DEBUG_PRINT_SHIFT (42)
+#define FCH_TRACE_RSV3 DEBUG_PRINT_SHIFT (43)
+#define FCH_TRACE_RSV4 DEBUG_PRINT_SHIFT (44)
+#define FCH_TRACE_RSV5 DEBUG_PRINT_SHIFT (45)
+#define FCH_TRACE_RSV6 DEBUG_PRINT_SHIFT (46)
+#define FCH_TRACE_RSV7 DEBUG_PRINT_SHIFT (47)
+#define FCH_TRACE_RSV8 DEBUG_PRINT_SHIFT (48)
+#define FCH_TRACE_RSV9 DEBUG_PRINT_SHIFT (49)
+
+//Other Masks
+#define MAIN_FLOW DEBUG_PRINT_SHIFT (50)
+#define EVENT_LOG DEBUG_PRINT_SHIFT (51)
+#define PERFORMANCE_ANALYSE DEBUG_PRINT_SHIFT (52)
+
+//Ids Masks
+#define IDS_TRACE DEBUG_PRINT_SHIFT (53)
+#define BVM_TRACE DEBUG_PRINT_SHIFT (54)
+#define IDS_TRACE_RSV2 DEBUG_PRINT_SHIFT (55)
+#define IDS_TRACE_RSV3 DEBUG_PRINT_SHIFT (56)
+
+//S3
+#define S3_TRACE DEBUG_PRINT_SHIFT (57)
+
+//Library function to read/write PCI/MSR registers
+#define LIB_PCI_RD DEBUG_PRINT_SHIFT (58)
+#define LIB_PCI_WR DEBUG_PRINT_SHIFT (59)
+
+//AGESA test points
+#define TEST_POINT DEBUG_PRINT_SHIFT (60)
+
+//Reserved for platform log
+#define PLAT_RSV1 DEBUG_PRINT_SHIFT (61)
+#define PLAT_RSV2 DEBUG_PRINT_SHIFT (62)
+#define PLAT_RSV3 DEBUG_PRINT_SHIFT (63)
+
+#define GNB_TRACE_DEFAULT\
+ (\
+ GNB_TRACE | PCIE_MISC | NB_MISC | GFX_MISC \
+ )
+
+#define GNB_TRACE_REG\
+ (\
+ PCIE_PORTREG_TRACE | PCIE_HOSTREG_TRACE | \
+ NB_SMUREG_TRACE | GNB_TRACE_RSV1 \
+ )
+
+#define GNB_TRACE_ALL\
+ (\
+ GNB_TRACE_DEFAULT | GNB_TRACE_REG \
+ )
+
+#define CPU_TRACE_ALL\
+ (\
+ CPU_TRACE | CPU_TRACE_RSV1 | CPU_TRACE_RSV2 | CPU_TRACE_RSV3 | \
+ CPU_TRACE_RSV4 | CPU_TRACE_RSV5 | CPU_TRACE_RSV6 | CPU_TRACE_RSV7 | \
+ CPU_TRACE_RSV8 | CPU_TRACE_RSV9\
+ )
+
+#define MEMORY_TRACE_ALL\
+ (\
+ MEM_FLOW | MEM_GETREG | MEM_SETREG | MEM_STATUS | \
+ MEMORY_TRACE_RSV1 | MEMORY_TRACE_RSV2 | MEMORY_TRACE_RSV3 | MEMORY_TRACE_RSV4 | \
+ MEMORY_TRACE_RSV5 | MEMORY_TRACE_RSV6\
+ )
+
+#define TOPO_TRACE_ALL\
+ (\
+ TOPO_TRACE | TOPO_TRACE_RSV1 | TOPO_TRACE_RSV2 | TOPO_TRACE_RSV3 | \
+ TOPO_TRACE_RSV4 | TOPO_TRACE_RSV5 | TOPO_TRACE_RSV6 | TOPO_TRACE_RSV7 | \
+ TOPO_TRACE_RSV8 | TOPO_TRACE_RSV9\
+ )
+
+#define FCH_TRACE_ALL\
+ (\
+ FCH_TRACE | FCH_TRACE_RSV1 | FCH_TRACE_RSV2 | FCH_TRACE_RSV3 | \
+ FCH_TRACE_RSV4 | FCH_TRACE_RSV5 | FCH_TRACE_RSV6 | FCH_TRACE_RSV7 | \
+ FCH_TRACE_RSV8 | FCH_TRACE_RSV9\
+ )
+
+#define IDS_TRACE_ALL\
+ (\
+ IDS_TRACE | BVM_TRACE | IDS_TRACE_RSV2 | IDS_TRACE_RSV3\
+ )
+
+#define OTHER_TRACE_ALL\
+ (\
+ MAIN_FLOW | EVENT_LOG | PERFORMANCE_ANALYSE\
+ )
+
+
+#define TRACE_MASK_ALL (0xFFFFFFFFFFFFFFFFull)
+#ifndef IDS_DEBUG_PRINT_MASK
+ #define IDS_DEBUG_PRINT_MASK (GNB_TRACE_DEFAULT | CPU_TRACE_ALL | MEM_FLOW | MEM_STATUS | TOPO_TRACE_ALL | FCH_TRACE_ALL | MAIN_FLOW | IDS_TRACE_DEFAULT | TEST_POINT)
+#endif
+
+/// if no specific define INIT & EXIT will be NULL
+#define IDS_HDT_CONSOLE_INIT(x)
+#define IDS_HDT_CONSOLE_EXIT(x)
+
+/// AGESA tracing service
+#if IDSOPT_TRACING_ENABLED == TRUE
+ #ifdef VA_ARGS_SUPPORTED
+ #if IDSOPT_C_OPTIMIZATION_DISABLED == TRUE
+ #define IDS_HDT_CONSOLE(f, s, ...) AmdIdsDebugPrint (f, s, __VA_ARGS__)
+ #else
+ #pragma warning(disable: 4127)
+ #define IDS_HDT_CONSOLE(f, s, ...) if (f == MEM_FLOW) AmdIdsDebugPrintMem (s, __VA_ARGS__); \
+ else if (f == CPU_TRACE) AmdIdsDebugPrintCpu (s, __VA_ARGS__); \
+ else if (f == TOPO_TRACE) AmdIdsDebugPrintTopology (s, __VA_ARGS__); \
+ else if (f == GNB_TRACE) AmdIdsDebugPrintGnb (s, __VA_ARGS__); \
+ else AmdIdsDebugPrint (f, s, __VA_ARGS__)
+ #endif
+ #else
+ #define IDS_HDT_CONSOLE AmdIdsDebugPrint
+ #endif
+ #define CONSOLE AmdIdsDebugPrintAll
+ #define IDS_HDT_CONSOLE_DEBUG_CODE(Code) Code
+ #define IDS_TIMEOUT_CTL(t) IdsMemTimeOut (t)
+#else
+ #define IDS_HDT_CONSOLE 1 ? (VOID) 0 : AmdIdsDebugPrint
+ #define IDS_HDT_CONSOLE_DEBUG_CODE(Code)
+ #define CONSOLE CONSOLE_Needs_To_Be_Removed_For_Production_Build //"WARNING: CONSOLE needs to be removed for production builds."
+ #define IDS_TIMEOUT_CTL(t)
+#endif
+
+/// Macros for serial port tracing
+#ifdef IDSOPT_SERIAL_PORT
+ #define IDS_SERIAL_PORT IDSOPT_SERIAL_PORT
+#endif
+
+#ifndef IDS_SERIAL_PORT
+ #define IDS_SERIAL_PORT 0x3F8
+#endif
+
+// Macros for redirect IO tracing
+#ifdef IDSOPT_DEBUG_PRINT_IO_PORT
+ #define IDS_DEBUG_PRINT_IO_PORT IDSOPT_DEBUG_PRINT_IO_PORT
+#endif
+
+#ifndef IDS_DEBUG_PRINT_IO_PORT
+ #define IDS_DEBUG_PRINT_IO_PORT 0x80
+#endif
+
+#define IDS_DPRAM_BASE 0
+#define IDS_DPRAM_SIZE 0
+///Default policy, shift the old data when buffer full
+#define IDS_DPRAM_STOP_LOGGING_WHEN_BUFFER_FULL FALSE
+#if IDSOPT_TRACING_CONSOLE_RAM == TRUE
+ #ifdef IDSOPT_DPRAM_BASE
+ #undef IDS_DPRAM_BASE
+ #define IDS_DPRAM_BASE IDSOPT_DPRAM_BASE
+ #else
+ #error "Debug Print Ram Base not specified, please define IDSOPT_DPRAM_BASE in optionsids.h"
+ #endif
+
+ #ifdef IDSOPT_DPRAM_SIZE
+ #undef IDS_DPRAM_SIZE
+ #define IDS_DPRAM_SIZE IDSOPT_DPRAM_SIZE
+ #else
+ #error "Debug Print Ram size not specified, please define IDSOPT_DPRAM_SIZE in optionsids.h"
+ #endif
+
+ #ifdef IDSOPT_DPRAM_STOP_LOGGING_WHEN_BUFFER_FULL
+ #define IDS_DPRAM_STOP_LOGGING_WHEN_BUFFER_FULL IDSOPT_DPRAM_STOP_LOGGING_WHEN_BUFFER_FULL
+ #endif
+#endif
+/**
+ * Macros to add HDT OUT
+ *
+ * The default minimal action is to do nothing and there is no any code to increase.
+ * For debug environments, the debug information can be displayed in HDT or other
+ * devices.
+ *
+ **/
+#if IDSOPT_TRACING_CONSOLE_HDTOUT == TRUE
+ #undef IDS_HDT_CONSOLE_INIT
+ #undef IDS_HDT_CONSOLE_EXIT
+ #define IDS_HDT_CONSOLE_INIT(x) AmdIdsHdtOutInit (x)
+ #define IDS_HDT_CONSOLE_EXIT(x) AmdIdsHdtOutExit (x)
+ #define IDS_HDT_CONSOLE_S3_EXIT(x) AmdIdsHdtOutS3Exit (x)
+ #define IDS_HDT_CONSOLE_S3_AP_EXIT(x) AmdIdsHdtOutS3ApExit (x)
+
+ #define IDS_HDT_CONSOLE_FLUSH_BUFFER(x) AmdIdsHdtOutBufferFlush (x)
+ #define IDS_HDT_CONSOLE_ASSERT(x) AmdIdsDebugPrintAssert (x)
+ #define IDS_FUNCLIST_ADDR ScriptFuncList
+ #define IDS_FUNCLIST_EXTERN() extern SCRIPT_FUNCTION ScriptFuncList[]
+#else
+ #define IDS_HDT_CONSOLE_S3_EXIT(x)
+ #define IDS_HDT_CONSOLE_S3_AP_EXIT(x)
+ #define IDS_HDT_CONSOLE_FLUSH_BUFFER(x)
+ #define IDS_HDT_CONSOLE_ASSERT(x)
+ #define IDS_FUNCLIST_ADDR NULL
+ #define IDS_FUNCLIST_EXTERN()
+#endif
+
+#if IDSOPT_TRACING_ENABLED == TRUE
+ #ifdef IDSOPT_CUSTOMIZE_TRACING_SERVICE
+ #undef IDS_HDT_CONSOLE
+ #define IDS_HDT_CONSOLE IDSOPT_CUSTOMIZE_TRACING_SERVICE
+ #endif
+ #ifdef IDSOPT_CUSTOMIZE_TRACING_SERVICE_INIT
+ #undef IDS_HDT_CONSOLE_INIT
+ #define IDS_HDT_CONSOLE_INIT(x) IDSOPT_CUSTOMIZE_TRACING_SERVICE_INIT (x)
+ #endif
+ #ifdef IDSOPT_CUSTOMIZE_TRACING_SERVICE_EXIT
+ #undef IDS_HDT_CONSOLE_EXIT
+ #define IDS_HDT_CONSOLE_EXIT(x) IDSOPT_CUSTOMIZE_TRACING_SERVICE_EXIT (x)
+ #endif
+#endif
+
+#define IDS_TRACE_SHOW_BLD_OPT_CFG IDSOPT_TRACE_USER_OPTIONS
+
+#if IDSOPT_PERF_ANALYSIS == TRUE
+ #include "IdsPerf.h"
+ #ifdef STOP_CODE
+ #undef STOP_CODE
+ #endif
+ #define STOP_CODE (((UINT32)FILECODE)*0x10000ul + \
+ ((__LINE__) % 10) + (((__LINE__ / 10) % 10)*0x10) + \
+ (((__LINE__ / 100) % 10)*0x100) + (((__LINE__ / 1000) % 10)*0x1000))
+
+ #define IDS_PERF_TIMESTAMP(ID, StdHeader) IdsPerfTimestamp (STOP_CODE, ID, (StdHeader))
+ #define IDS_PERF_ANALYSE(StdHeader) IdsPerfAnalyseTimestamp (StdHeader)
+#else
+ #define IDS_PERF_TIMESTAMP(ID, StdHeader)
+ #define IDS_PERF_ANALYSE(StdHeader)
+#endif
+
+///For IDS feat use
+#define IDS_FAMILY_ALL 0xFFFFFFFFFFFFFFFFull
+#define IDS_BSP_ONLY TRUE
+#define IDS_ALL_CORES FALSE
+
+#define IDS_LATE_RUN_AP_TASK_ID PROC_IDS_LIBRARY_IDSLIB_FILECODE
+
+#define IDS_CALLOUT_INIT 0x01 ///< The function data of IDS callout function of initialization.
+
+#define IDS_CALLOUT_GNB_PPFUSE_OVERRIDE 0x83 ///< The function data of IDS callout function of GNB pp fuse table.
+#define IDS_CALLOUT_GNB_INTEGRATED_TABLE_CONFIG 0x84 ///< The function data of IDS callout function of GNB integrated table.
+#define IDS_CALLOUT_GNB_NB_POWERGATE_CONFIG 0x85 ///< The function data of IDS callout function of GNB NB power gate config.
+#define IDS_CALLOUT_GNB_PCIE_POWERGATE_CONFIG 0x86 ///< The function data of IDS callout function of GNB PCIE power gateconfig.
+#define IDS_CALLOUT_GNB_PCIE_PLATFORM_CONFIG 0x87 ///< The function data of IDS callout function of GNB pcie platform config.
+#define IDS_CALLOUT_GNB_PCIE_PHY_CONFIG 0x88 ///< The function data of IDS callout function of GNB pcie PHY config.
+#define IDS_CALLOUT_GNB_GMM_REGISTER_OVERRIDE 0x89 ///< The function data of IDS callout function of GNB GMM register override
+#define IDS_CALLOUT_FCH_INIT_RESET 0x8A ///< The function data of IDS callout function of FchInitReset
+#define IDS_CALLOUT_FCH_INIT_ENV 0x8B ///< The function data of IDS callout function of FchInitEnv.
+#define IDS_CALLOUT_POWER_PLAN_INIT 0x8C ///< The function data of IDS callout function of Override Power Plan Init
+#define IDS_CALLOUT_GET_PERF_BUFFER 0x8D ///< The function data of IDS callout function of get platform performance buffer.
+#define IDS_CALLOUT_GNB_PACKAGE_POWER_CONFIG 0x8E ///< The function data of IDS callout function of Bapm Package Power.
+#define IDS_CALLOUT_SMU_PORT80_LOGGING_BUFFER 0x8F ///< The function data of IDS callout function of SMU port80 logging buffer.
+#define IDS_CALLOUT_GNB_BEFORE_EARLY_INIT 0x90 ///< The function data of IDS callout function of GNB before early init.
+#define IDS_CALLOUT_GNB_SMUBIOSTABLE_OVERRIDE 0x91 ///< The function data of IDS callout function of GNB smu bios table.
+#define IDS_CALLOUT_GNB_PCIE_EARLY_PORT_CONFIG 0x92 ///< The function data of IDS callout function of GNB pcie early port config.
+
+/// Function entry for HDT script to call
+typedef struct _SCRIPT_FUNCTION {
+ UINT32 FuncAddr; ///< Function address in ROM
+ CHAR8 FuncName[40]; ///< Function name
+} SCRIPT_FUNCTION;
+
+/// Data Structure for Mem ECC parameter override
+typedef struct {
+ IN BOOLEAN CfgEccRedirection; ///< ECC Redirection
+ IN UINT16 CfgScrubDramRate; ///< Scrub Dram Rate
+ IN UINT16 CfgScrubL2Rate; ///< Scrub L2Rate
+ IN UINT16 CfgScrubL3Rate; ///< Scrub L3Rate
+ IN UINT16 CfgScrubIcRate; ///< Scrub Ic Rate
+ IN UINT16 CfgScrubDcRate; ///< Scrub Dc Rate
+ IN BOOLEAN CfgEccSyncFlood; ///< ECC Sync Flood
+} ECC_OVERRIDE_STRUCT;
+
+
+
+
+/**
+ * AGESA Test Points
+ *
+ * These are the values displayed to the user to indicate progress through boot.
+ * These can be used in a debug environment to stop the debugger at a specific
+ * test point:
+ * For SimNow!, this command
+ * bi 81 w vb 49
+ * will stop the debugger on one of the TracePoints (49 is the TP value in this example).
+ *
+ */
+typedef enum {
+ StartProcessorTestPoints, ///< 00 Entry used for range testing for @b Processor related TPs
+
+ // Memory test points
+ TpProcMemBeforeMemDataInit, ///< 01 .. Memory structure initialization (Public interface)
+ TpProcMemBeforeSpdProcessing, ///< 02 .. SPD Data processing (Public interface)
+ TpProcMemAmdMemAuto, ///< 03 .. Memory configuration (Public interface)
+ TpProcMemDramInit, ///< 04 .. DRAM initialization
+ TpProcMemSPDChecking, ///< 05 ..
+ TpProcMemModeChecking, ///< 06 ..
+ TpProcMemSpeedTclConfig, ///< 07 .. Speed and TCL configuration
+ TpProcMemSpdTiming, ///< 08 ..
+ TpProcMemDramMapping, ///< 09 ..
+ TpProcMemPlatformSpecificConfig, ///< 0A ..
+ TPProcMemPhyCompensation, ///< 0B ..
+ TpProcMemStartDcts, ///< 0C ..
+ TpProcMemBeforeDramInit, ///< 0D .. (Public interface)
+ TpProcMemPhyFenceTraining, ///< 0E ..
+ TpProcMemSynchronizeDcts, ///< 0F ..
+ TpProcMemSystemMemoryMapping, ///< 10 ..
+ TpProcMemMtrrConfiguration, ///< 11 ..
+ TpProcMemDramTraining, ///< 12 ..
+ TpProcMemBeforeAnyTraining, ///< 13 .. (Public interface)
+ TpProcMemWriteLevelizationTraining, ///< 14 ..
+ TpProcMemWlFirstPass, ///< 15 .. Below 800Mhz first pass start
+ TpProcMemWlSecondPass, ///< 16 .. Above 800Mhz second pass start
+ TpProcMemWlTrainTargetDimm, ///< 17 .. Target DIMM configured
+ TpProcMemWlPrepDimms, ///< 18 .. Prepare DIMMS for WL
+ TpProcMemWlConfigDimms, ///< 19 .. Configure DIMMS for WL
+ TpProcMemReceiverEnableTraining, ///< 1A ..
+ TpProcMemRcvrStartSweep, ///< 1B .. Start sweep loop
+ TpProcMemRcvrSetDelay, ///< 1C .. Set receiver Delay
+ TpProcMemRcvrWritePattern, ///< 1D .. Write test pattern
+ TpProcMemRcvrReadPattern, ///< 1E .. Read test pattern
+ TpProcMemRcvrTestPattern, ///< 1F .. Compare test pattern
+ TpProcMemRcvrCalcLatency, ///< 20 .. Calculate MaxRdLatency per channel
+ TpProcMemReceiveDqsTraining, ///< 21 ..
+ TpProcMemRcvDqsSetDelay, ///< 22 .. Set Write Data delay
+ TpProcMemRcvDqsWritePattern, ///< 23 .. Write test pattern
+ TpProcMemRcvDqsStartSweep, ///< 24 .. Start read sweep
+ TpProcMemRcvDqsSetRcvDelay, ///< 25 .. Set Receive DQS delay
+ TpProcMemRcvDqsReadPattern, ///< 26 .. Read Test pattern
+ TpProcMemRcvDqsTstPattern, ///< 27 .. Compare Test pattern
+ TpProcMemRcvDqsResults, ///< 28 .. Update results
+ TpProcMemRcvDqsFindWindow, ///< 29 .. Start Find passing window
+ TpProcMemTransmitDqsTraining, ///< 2A ..
+ TpProcMemTxDqStartSweep, ///< 2B .. Start write sweep
+ TpProcMemTxDqSetDelay, ///< 2C .. Set Transmit DQ delay
+ TpProcMemTxDqWritePattern, ///< 2D .. Write test pattern
+ TpProcMemTxDqReadPattern, ///< 2E .. Read Test pattern
+ TpProcMemTxDqTestPattern, ///< 2F .. Compare Test pattern
+ TpProcMemTxDqResults, ///< 30 .. Update results
+ TpProcMemTxDqFindWindow, ///< 31 .. Start Find passing window
+ TpProcMemMaxRdLatencyTraining, ///< 32 ..
+ TpProcMemMaxRdLatStartSweep, ///< 33 .. Start sweep
+ TpProcMemMaxRdLatSetDelay, ///< 34 .. Set delay
+ TpProcMemMaxRdLatWritePattern, ///< 35 .. Write test pattern
+ TpProcMemMaxRdLatReadPattern, ///< 36 .. Read Test pattern
+ TpProcMemMaxRdLatTestPattern, ///< 37 .. Compare Test pattern
+ TpProcMemOnlineSpareInit, ///< 38 .. Online Spare init
+ TpProcMemBankInterleaveInit, ///< 39 .. Bank Interleave Init
+ TpProcMemNodeInterleaveInit, ///< 3A .. Node Interleave Init
+ TpProcMemChannelInterleaveInit, ///< 3B .. Channel Interleave Init
+ TpProcMemEccInitialization, ///< 3C .. ECC initialization
+ TpProcMemPlatformSpecificInit, ///< 3D .. Platform Specific Init
+ TpProcMemBeforeAgesaReadSpd, ///< 3E .. Before callout for "AgesaReadSpd"
+ TpProcMemAfterAgesaReadSpd, ///< 3F .. After callout for "AgesaReadSpd"
+ TpProcMemBeforeAgesaHookBeforeDramInit, ///< 40 .. Before optional callout "AgesaHookBeforeDramInit"
+ TpProcMemAfterAgesaHookBeforeDramInit, ///< 41 .. After optional callout "AgesaHookBeforeDramInit"
+ TpProcMemBeforeAgesaHookBeforeDQSTraining, ///< 42 .. Before optional callout "AgesaHookBeforeDQSTraining"
+ TpProcMemAfterAgesaHookBeforeDQSTraining, ///< 43 .. After optional callout "AgesaHookBeforeDQSTraining"
+ TpProcMemBeforeAgesaHookBeforeExitSelfRef, ///< 44 .. Before optional callout "AgesaHookBeforeDramInit"
+ TpProcMemAfterAgesaHookBeforeExitSelfRef, ///< 45 .. After optional callout "AgesaHookBeforeDramInit"
+ TpProcMemAfterMemDataInit, ///< 46 .. After MemDataInit
+ TpProcMemInitializeMCT, ///< 47 .. Before InitializeMCT
+ TpProcMemLvDdr3, ///< 48 .. Before LV DDR3
+ TpProcMemInitMCT, ///< 49 .. Before InitMCT
+ TpProcMemOtherTiming, ///< 4A.. Before OtherTiming
+ TpProcMemUMAMemTyping, ///< 4B .. Before UMAMemTyping
+ TpProcMemSetDqsEccTmgs, ///< 4C .. Before SetDqsEccTmgs
+ TpProcMemMemClr, ///< 4D .. Before MemClr
+ TpProcMemOnDimmThermal, ///< 4E .. Before On DIMM Thermal
+ TpProcMemDmi, ///< 4F .. Before DMI
+ TpProcMemEnd, ///< 50 .. End of memory code
+
+ // CPU test points
+ TpProcCpuEntryDmi, ///< 51 .. Entry point CreateDmiRecords
+ TpProcCpuEntryPstate, ///< 52 .. Entry point GenerateSsdt
+ TpProcCpuEntryPstateLeveling, ///< 53 .. Entry point PStateLeveling
+ TpProcCpuEntryPstateGather, ///< 54 .. Entry point PStateGatherData
+ TpProcCpuEntryWhea, ///< 55 .. Entry point CreateAcpiWhea
+ TpProcCpuEntrySrat, ///< 56 .. Entry point CreateAcpiSrat
+ TpProcCpuEntrySlit, ///< 57 .. Entry point CreateAcpiSlit
+ TpProcCpuProcessRegisterTables, ///< 58 .. Register table processing
+ TpProcCpuSetBrandID, ///< 59 .. Set brand ID
+ TpProcCpuLocalApicInit, ///< 5A .. Initialize local APIC
+ TpProcCpuLoadUcode, ///< 5B .. Load microcode patch
+ TpProcCpuBeforePMFeatureInit, ///< 5C .. BeforePM feature dispatch point
+ TpProcCpuPowerMgmtInit, ///< 5D .. Power Management table processing
+ TpProcCpuEarlyFeatureInit, ///< 5E .. Early feature dispatch point
+ TpProcCpuCoreLeveling, ///< 5F .. Core Leveling
+ TpProcCpuApMtrrSync, ///< 60 .. AP MTRR sync up
+ TpProcCpuPostFeatureInit, ///< 61 .. POST feature dispatch point
+ TpProcCpuBeforeRelinquishAPsFeatureInit = 0x63, ///< 63 .. Before Relinquishing control of APs feature dispatch point
+ TpProcCpuBeforeAllocateWheaBuffer, ///< 64 .. Before the WHEA init code calls out to allocate a buffer
+ TpProcCpuAfterAllocateWheaBuffer, ///< 65 .. After the WHEA init code calls out to allocate a buffer
+ TpProcCpuBeforeAllocateSratBuffer, ///< 66 .. Before the SRAT init code calls out to allocate a buffer
+ TpProcCpuAfterAllocateSratBuffer, ///< 67 .. After the SRAT init code calls out to allocate a buffer
+ TpProcCpuBeforeLocateSsdtBuffer, ///< 68 .. Before the P-state init code calls out to locate a buffer
+ TpProcCpuAfterLocateSsdtBuffer, ///< 69 .. After the P-state init code calls out to locate a buffer
+ TpProcCpuBeforeAllocateSsdtBuffer, ///< 6A .. Before the P-state init code calls out to allocate a buffer
+ TpProcCpuAfterAllocateSsdtBuffer, ///< 6B .. After the P-state init code calls out to allocate a buffer
+ TpProcCpuEntryCrat, ///< 6C .. Entry point CreateAcpiCrat
+ TpProcCpuEntryCdit, ///< 6D .. Entry point CreateAcpiCdit
+ TpProcCpuEntryScs, ///< 6E .. Entry point InitializeScsFeature
+
+ // Topology test points
+ TpProcTopologyEntry = 0x71, ///< 71 .. Topology Init begin
+ TpProcTopologyDone = 0x7C, ///< 7C .. Topology Init complete
+
+ // Extended memory test point
+ TpProcMemSendMRS2 = 0x80, ///< 80 .. Sending MRS2
+ TpProcMemSendMRS3, ///< 81 .. Sedding MRS3
+ TpProcMemSendMRS1, ///< 82 .. Sending MRS1
+ TpProcMemSendMRS0, ///< 83 .. Sending MRS0
+ TpProcMemContinPatternGenRead, ///< 84 .. Continuous Pattern Read
+ TpProcMemContinPatternGenWrite, ///< 85 .. Continuous Pattern Write
+ TpProcMem2dRdDqsTraining, ///< 86 .. Mem: 2d RdDqs Training begin
+ TpProcMemBefore2dTrainExtVrefChange,///< 87 .. Mem: Before optional callout to platform BIOS to change External Vref during 2d Training
+ TpProcMemAfter2dTrainExtVrefChange, ///< 88 .. Mem: After optional callout to platform BIOS to change External Vref during 2d Training
+ TpProcMemConfigureDCTForGeneral, ///< 89 .. Configure DCT For General use begin
+ TpProcMemProcConfigureDCTForTraining, ///< 8A .. Configure DCT For training begin
+ TpProcMemConfigureDCTNonExplicitSeq,///< 8B .. Configure DCT For Non-Explicit
+ TpProcMemSynchronizeChannels, ///< 8C .. Configure to Sync channels
+ TpProcMemC6StorageAllocation, ///< 8D .. Allocate C6 Storage
+
+ // Gnb Earlier init
+ TpGnbEarlierPcieConfigurationInit = 0x90, ///< 90 .. GNB earlier PCIE configuration init
+ TpGnbEarlierInterface = 0x91, ///< 91 .. GNB earlier interface
+ // Gnb Early init
+ TpGnbEarlyInterface = 0x92, ///< 92 .. GNB early interface
+ TpGnbPcieConfigurationMap, ///< 93 .. GNB early PCIE configuration map
+ TpGnbPcieEarlyInterface, ///< 94 .. GNB early PCIE interface
+ //Gnb post init
+ TpGnbPciePostEarlyInterface = 0x95, ///< 95 .. GNB post early interface
+ TpGnbGfxConfigPostInterface, ///< 96 .. GNB post GFX config interface
+ TpGnbGfxPostInterface, ///< 97 .. GNB post GFX interface
+ // Gnb post after DRAM init
+ TpGnbPostInterface = 0x98, ///< 98 .. GNB post after DRAM interface
+ TpGnbPciePostInterface, ///< 99 .. GNB post after DRAM PCIE interface
+ // Gnb Env init
+ TpGnbEnvInterface, ///< 9A .. GNB Env Nb interface
+ TpGnbPcieEnvInterface, ///< 9B .. GNB Env PCIE interface
+ TpGnbGfxConfigEnvInterface, ///< 9C .. GNB Env GFX Config interface
+ TpGnbGfxEnvInterface, ///< 9D .. GNB Env GFX interface
+ // Gnb Mid init
+ TpGnbGfxConfigMidInterface = 0xA1, ///< A1 .. GNB Mid GFX config interface
+ TpGnbGfxMidInterface, ///< A2 .. GNB Mid GFX interface
+ TpPcieMidInterface, ///< A3 .. GNB Mid PCIE interface
+ TpGnbMidInterface, ///< A4 .. GNB Mid interface
+ TpNbLclkFeature, ///< A5 .. GNB Mid Nclk feature
+ TpPciePowerGateFeature, ///< A6 .. GNB Mid pcie power gate feature
+ TpGnbPcieMaxPayloadInterface, ///< A7 .. GNB Mid pcie max payload interface
+ TpGnbPcieClkPmInterface, ///< A8 .. GNB Mid pcie clk pm port interface
+ TpGnbPcieAspmInterface, ///< A9 .. GNB Mid pcie ASPM interface
+ TpGnbNbIoapicInterface, ///< AA .. GNB Mid IOAPIC interface
+ // Gnb Late init
+ TpGnbPcieAlibFeature = 0xAB, ///< AB .. GNB Late pcie ALIB feature
+ TpGnbIommuIvrsTable, ///< AC .. GNB Late pcie IOMMU
+ // Gnb S3 Save
+ TpGnbGfxInitSview = 0xAD, ///< AD .. GNB S3SAVE GFX sview init
+ TpGnbAlibDispatchFeature = 0xAE, ///< AE .. GNB ALIB dispatch feature
+ EndGnbTestPoints = 0xAF, ///< AF End of TP range for GNB
+
+ StartFchTestPoints = 0xB0, ///< B0 Entry used for range testing for @b FCH related TPs
+ TpFchInitResetDispatching, ///< B1 .. FCH InitReset dispatch point
+ TpFchGppBeforePortTraining, ///< B2 .. Before FCH GPP port training
+ TpFchGppGen1PortPolling, ///< B3 .. FCH GPP port polling with GEN1 speed
+ TpFchGppGen2PortPolling, ///< B4 .. FCH GPP port polling with GEN2 speed
+ TpFchGppAfterPortTraining, ///< B5 .. After FCH GPP port training
+ TpFchInitEnvDispatching, ///< B6 .. FCH InitEnv dispatch point
+ TpFchInitMidDispatching, ///< B7 .. FCH InitMid dispatch point
+ TpFchInitLateDispatching, ///< B8 .. FCH InitLate dispatch point
+ TpFchGppHotPlugging, ///< B9 .. FCH GPP hot plug event
+ TpFchGppHotUnplugging, ///< BA .. AFCH GPP hot unplug event
+ TpFchInitS3EarlyDispatching, ///< BB .. FCH InitS3Early dispatch point
+ TpFchInitS3LateDispatching, ///< BC .. FCH InitS3Late dispatch point
+ EndFchTestPoints, ///< BF End of TP range for FCH
+
+ // Interface test points
+ TpIfAmdInitResetEntry = 0xC0, ///< C0 .. Entry to AmdInitReset
+ TpIfAmdInitResetExit, ///< C1 .. Exiting from AmdInitReset
+ TpIfAmdInitRecoveryEntry, ///< C2 .. Entry to AmdInitRecovery
+ TpIfAmdInitRecoveryExit, ///< C3 .. Exiting from AmdInitRecovery
+ TpIfAmdInitEarlyEntry, ///< C4 .. Entry to AmdInitEarly
+ TpIfAmdInitEarlyExit, ///< C5 .. Exiting from AmdInitEarly
+ TpIfAmdInitPostEntry, ///< C6 .. Entry to AmdInitPost
+ TpIfAmdInitPostExit, ///< C7 .. Exiting from AmdInitPost
+ TpIfAmdInitEnvEntry, ///< C8 .. Entry to AmdInitEnv
+ TpIfAmdInitEnvExit, ///< C9 .. Exiting from AmdInitEnv
+ TpIfAmdInitMidEntry, ///< CA .. Entry to AmdInitMid
+ TpIfAmdInitMidExit, ///< CB .. Exiting from AmdInitMid
+ TpIfAmdInitLateEntry, ///< CC .. Entry to AmdInitLate
+ TpIfAmdInitLateExit, ///< CD .. Exiting from AmdInitLate
+ TpIfAmdS3SaveEntry, ///< CE .. Entry to AmdS3Save
+ TpIfAmdS3SaveExit, ///< CF .. Exiting from AmdS3Save
+ TpIfAmdInitResumeEntry, ///< D0 .. Entry to AmdInitResume
+ TpIfAmdInitResumeExit, ///< D1 .. Exiting from AmdInitResume
+ TpIfAmdS3LateRestoreEntry, ///< D2 .. Entry to AmdS3LateRestore
+ TpIfAmdS3LateRestoreExit, ///< D3 .. Exiting from AmdS3LateRestore
+ TpIfAmdLateRunApTaskEntry, ///< D4 .. Entry to AmdS3LateRestore
+ TpIfAmdLateRunApTaskExit, ///< D5 .. Exiting from AmdS3LateRestore
+ TpIfAmdReadEventLogEntry, ///< D6 .. Entry to AmdReadEventLog
+ TpIfAmdReadEventLogExit, ///< D7 .. Exiting from AmdReadEventLog
+ TpIfAmdGetApicIdEntry, ///< D8 .. Entry to AmdGetApicId
+ TpIfAmdGetApicIdExit, ///< D9 .. Exiting from AmdGetApicId
+ TpIfAmdGetPciAddressEntry, ///< DA .. Entry to AmdGetPciAddress
+ TpIfAmdGetPciAddressExit, ///< DB .. Exiting from AmdGetPciAddress
+ TpIfAmdIdentifyCoreEntry, ///< DC .. Entry to AmdIdentifyCore
+ TpIfAmdIdentifyCoreExit, ///< DD .. Exiting from AmdIdentifyCore
+ TpIfBeforeRunApFromIds, ///< DE .. After IDS calls out to run code on an AP
+ TpIfAfterRunApFromIds, ///< DF .. After IDS calls out to run code on an AP
+ TpIfBeforeGetIdsData, ///< E0 .. Before IDS calls out to get IDS data
+ TpIfAfterGetIdsData, ///< E1 .. After IDS calls out to get IDS data
+ TpIfBeforeAllocateHeapBuffer, ///< E2 .. Before the heap manager calls out to allocate a buffer
+ TpIfAfterAllocateHeapBuffer, ///< E3 .. After the heap manager calls out to allocate a buffer
+ TpIfBeforeDeallocateHeapBuffer, ///< E4 .. Before the heap manager calls out to deallocate a buffer
+ TpIfAfterDeallocateHeapBuffer, ///< E5 .. After the heap manager calls out to deallocate a buffer
+ TpIfBeforeLocateHeapBuffer, ///< E6 .. Before the heap manager calls out to locate a buffer
+ TpIfAfterLocateHeapBuffer, ///< E7 .. After the heap manager calls out to locate a buffer
+ TpIfBeforeRunApFromAllAps, ///< E8 .. Before the BSP calls out to run code on an AP
+ TpIfAfterRunApFromAllAps, ///< E9 .. After the BSP calls out to run code on an AP
+ TpIfBeforeRunApFromAllCore0s, ///< EA .. Before the BSP calls out to run code on an AP
+ TpIfAfterRunApFromAllCore0s, ///< EB .. After the BSP calls out to run code on an AP
+ TpIfBeforeAllocateS3SaveBuffer, ///< EC .. Before the S3 save code calls out to allocate a buffer
+ TpIfAfterAllocateS3SaveBuffer, ///< ED .. After the S3 save code calls out to allocate a buffer
+ TpIfBeforeAllocateMemoryS3SaveBuffer, ///< EE .. Before the memory S3 save code calls out to allocate a buffer
+ TpIfAfterAllocateMemoryS3SaveBuffer, ///< EF .. After the memory S3 save code calls out to allocate a buffer
+ TpIfBeforeLocateS3PciBuffer, ///< F0 .. Before the memory code calls out to locate a buffer
+ TpIfAfterLocateS3PciBuffer, ///< F1 .. After the memory code calls out to locate a buffer
+ TpIfBeforeLocateS3CPciBuffer, ///< F2 .. Before the memory code calls out to locate a buffer
+ TpIfAfterLocateS3CPciBuffer, ///< F3 .. After the memory code calls out to locate a buffer
+ TpIfBeforeLocateS3MsrBuffer, ///< F4 .. Before the memory code calls out to locate a buffer
+ TpIfAfterLocateS3MsrBuffer, ///< F5 .. After the memory code calls out to locate a buffer
+ TpIfBeforeLocateS3CMsrBuffer, ///< F6 .. Before the memory code calls out to locate a buffer
+ TpIfAfterLocateS3CMsrBuffer, ///< F7 .. After the memory code calls out to locate a buffer
+ TpReadyToBoot, ///< F8 .. Ready to boot event
+ // PMU test points
+ TpProcMemPmuFailed, ///< F9 .. Failed PMU training.
+ TpIfAmdS3FinalRestoreEntry, ///< FA .. Entry to AmdS3FinalRestore
+ TpIfAmdS3FinalRestoreExit, ///< FB .. Exiting from AmdS3FinalRestore
+
+ EndAgesaTps = 0xFF, ///< Last defined AGESA TP
+} AGESA_TP;
+
+///Ids Feat description
+typedef enum {
+ IDS_FEAT_UCODE_UPDATE = 0x0000, ///< Feat for Ucode Update
+ IDS_FEAT_TARGET_PSTATE, ///< Feat for Target Pstate
+ IDS_FEAT_POSTPSTATE, ///< Feat for Post Pstate
+ IDS_FEAT_ECC_CTRL, ///< Feat for Ecc Control
+ IDS_FEAT_ECC_SYMBOL_SIZE, ///< Feat for Ecc symbol size
+ IDS_FEAT_DCT_ALLMEMCLK, ///< Feat for all memory clock
+ IDS_FEAT_DCT_GANGMODE, ///< Feat for Dct gang mode
+ IDS_FEAT_DCT_BURSTLENGTH, ///< Feat for dct burst length
+ IDS_FEAT_DCT_POWERDOWN, ///< Feat for dct power down
+ IDS_FEAT_DCT_DLLSHUTDOWN, ///< Feat for dct dll shut down
+ IDS_FEAT_HDTOUT, ///< Feat for hdt out
+ IDS_FEAT_GNB_PLATFORMCFG, ///< Feat for override GNB platform config
+ IDS_FEAT_CPB_CTRL, ///< Feat for Config the Core peformance boost feature
+ IDS_FEAT_HTC_CTRL, ///< Feat for Hardware Thermal Control
+ IDS_FEAT_MEMORY_MAPPING, ///< Feat for Memory Mapping
+ IDS_FEAT_POWER_POLICY, ///< Feat for Power Policy
+ IDS_FEAT_NV_TO_CMOS, ///< Feat for Save BSP Nv to CMOS
+ IDS_FEAT_COMMON, ///< Common Feat
+ IDS_FEAT_END = 0xFF ///< End of Common feat
+} IDS_FEAT;
+
+///Ids IDT table function ID
+typedef enum {
+ IDS_IDT_REPLACE_IDTR_FOR_BSC = 0x0000, ///< Function ID for saving IDTR for BSC
+ IDS_IDT_RESTORE_IDTR_FOR_BSC, ///< Function ID for restoring IDTR for BSC
+ IDS_IDT_UPDATE_EXCEPTION_VECTOR_FOR_AP, ///< Function ID for updating exception vector
+} IDS_IDT_FUNC_ID;
+
+typedef IDS_STATUS IDS_COMMON_FUNC (
+ IN OUT VOID *DataPtr,
+ IN OUT AMD_CONFIG_PARAMS *StdHeader,
+ IN IDS_NV_ITEM *IdsNvPtr
+ );
+
+typedef IDS_COMMON_FUNC *PIDS_COMMON_FUNC;
+
+/// Data Structure of IDS Feature block
+typedef struct _IDS_FAMILY_FEAT_STRUCT {
+ IDS_FEAT IdsFeat; ///< Ids Feat ID
+ BOOLEAN IsBsp; ///< swith for Bsp check
+ AGESA_IDS_OPTION IdsOption; ///< IDS option
+ UINT64 CpuFamily; ///<
+ PIDS_COMMON_FUNC pf_idsoption; ///<pointer to function
+} IDS_FAMILY_FEAT_STRUCT;
+
+
+/// Data Structure of IDS option
+typedef struct _IDS_OPTION_STRUCT {
+ AGESA_IDS_OPTION idsoption; ///< IDS option
+ PIDS_COMMON_FUNC pf_idsoption; ///<pointer to function
+} IDS_OPTION_STRUCT;
+
+/// Data Structure of IDS option table
+typedef struct _IDS_OPTION_STRUCT_TBL {
+ UINT8 version; ///<Version of IDS option table
+ UINT16 size; ///<Size of IDS option table
+ CONST IDS_OPTION_STRUCT *pIdsOptionStruct; ///<pointer to array of structure
+} IDS_OPTION_STRUCT_TBL;
+
+#define IDS_NV_TO_CMOS_LEN_BYTE 1
+#define IDS_NV_TO_CMOS_LEN_WORD 2
+#define IDS_NV_TO_CMOS_LEN_END 0xFF
+#define IDS_NV_TO_CMOS_ID_END 0xFFFF
+
+/// Data struct of set/get NV to/from CMOS
+typedef struct _IDS_NV_TO_CMOS {
+ UINT8 Length; ///< Length of NV
+ UINT16 IDS_NV_ID; ///< IDS id
+} IDS_NV_TO_CMOS;
+
+IDS_STATUS
+AmdIdsCtrlDispatcher (
+ IN AGESA_IDS_OPTION IdsOption,
+ IN OUT VOID *DataPtr,
+ IN OUT AMD_CONFIG_PARAMS *StdHeader
+ );
+
+AGESA_STATUS
+IdsOptionCallout (
+ IN UINTN CallOutId,
+ IN OUT VOID *DataPtr,
+ IN OUT AMD_CONFIG_PARAMS *StdHeader
+ );
+
+VOID
+AmdIdsHdtOutInit (
+ IN OUT AMD_CONFIG_PARAMS *StdHeader
+ );
+
+VOID
+AmdIdsHdtOutExit (
+ IN OUT AMD_CONFIG_PARAMS *StdHeader
+ );
+
+VOID
+AmdIdsHdtOutS3Exit (
+ IN OUT AMD_CONFIG_PARAMS *StdHeader
+ );
+
+VOID
+AmdIdsHdtOutS3ApExit (
+ IN OUT AMD_CONFIG_PARAMS *StdHeader
+ );
+
+VOID
+AmdIdsDebugPrint (
+ IN UINT64 Flag,
+ IN CHAR8 *Format,
+ IN ...
+ );
+
+VOID
+AmdIdsDebugPrintTopology (
+ IN CHAR8 *Format,
+ IN ...
+ );
+
+VOID
+AmdIdsDebugPrintCpu (
+ IN CHAR8 *Format,
+ IN ...
+ );
+
+VOID
+AmdIdsDebugPrintMem (
+ IN CHAR8 *Format,
+ IN ...
+ );
+
+VOID
+AmdIdsDebugPrintGnb (
+ IN CHAR8 *Format,
+ IN ...
+ );
+
+VOID
+AmdIdsDebugPrintAll (
+ IN CHAR8 *Format,
+ IN ...
+ );
+
+VOID
+AmdIdsHdtOutBufferFlush (
+ IN OUT AMD_CONFIG_PARAMS *StdHeader
+ );
+
+VOID
+IdsMemTimeOut (
+ IN OUT VOID *DataPtr
+ );
+
+VOID
+IdsAgesaTestPoint (
+ IN AGESA_TP TestPoint,
+ IN OUT AMD_CONFIG_PARAMS *StdHeader
+ );
+
+/**
+ * IDS Backend Function for ASSERT
+ *
+ * Halt execution with stop code display. Stop Code is displayed on port 80, with rotation so that
+ * it is visible on 8, 16, or 32 bit display. The stop code is alternated with 0xDEAD on the display,
+ * to help distinguish the stop code from a post code loop.
+ * Additional features may be available if using simulation.
+ *
+ * @param[in] FileCode File code(define in FILECODE.h) mix with assert Line num.
+ *
+ * @retval TRUE No error
+**/
+BOOLEAN
+IdsAssert (
+ IN UINT32 FileCode
+ );
+
+/**
+ * The engine code for ASSERT MACRO
+ *
+ * Halt execution with stop code display. Stop Code is displayed on port 80, with rotation so that
+ * it is visible on 8, 16, or 32 bit display. The stop code is alternated with 0xDEAD on the display,
+ * to help distinguish the stop code from a post code loop.
+ * Additional features may be available if using simulation.
+ *
+ * @param[in] FileCode File code(define in FILECODE.h) mix with assert Line num.
+ *
+ */
+BOOLEAN
+IdsErrorStop (
+ IN UINT32 FileCode
+ );
+
+VOID
+IdsDelay (
+ IN VOID
+ );
+
+BOOLEAN
+AmdHeapIntactCheck (
+ IN AMD_CONFIG_PARAMS *StdHeader
+ );
+
+VOID
+IdsCarCorruptionCheck (
+ IN OUT AMD_CONFIG_PARAMS *StdHeader
+ );
+
+IDS_STATUS
+IdsExceptionTrap (
+ IN IDS_IDT_FUNC_ID IdsIdtFuncId,
+ IN VOID *DataPtr,
+ IN OUT AMD_CONFIG_PARAMS *StdHeader
+ );
+
+AGESA_STATUS
+IdsPerfTimestamp (
+ IN UINT32 LineInFile,
+ IN UINT32 Description,
+ IN OUT AMD_CONFIG_PARAMS *StdHeader
+ );
+
+AGESA_STATUS
+IdsPerfAnalyseTimestamp (
+ IN OUT AMD_CONFIG_PARAMS *StdHeader
+ );
+
+
+#if IDSOPT_IDS_ENABLED == FALSE
+ #undef IEM_SKIP_CODE
+ #undef IEM_INSERT_CODE
+#endif
+#ifndef IEM_SKIP_CODE
+ #define IEM_SKIP_CODE(L)
+#endif
+#ifndef IEM_INSERT_CODE
+ #define IEM_INSERT_CODE(L, Fn, Parm)
+#endif
+
+#endif // _IDS_H_
diff --git a/src/vendorcode/amd/pi/00630F01/Include/IdsPerf.h b/src/vendorcode/amd/pi/00630F01/Include/IdsPerf.h
new file mode 100644
index 0000000..c11db8b
--- /dev/null
+++ b/src/vendorcode/amd/pi/00630F01/Include/IdsPerf.h
@@ -0,0 +1,138 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD Integrated Debug Routines for performance analysis
+ *
+ * Contains AMD AGESA debug macros and functions for performance analysis
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: IDS
+ * @e \$Revision: 281181 $ @e \$Date: 2013-12-18 02:18:55 -0600 (Wed, 18 Dec 2013) $
+ */
+/*****************************************************************************
+ *
+ * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ***************************************************************************/
+#ifndef _IDS_PERFORMANCE_DATA_POINT
+
+ #define _IDS_PERFORMANCE_DATA_POINT
+ #define IDS_PERF_VERSION 0x00010000ul //version number 0.1.0.0
+/// Time points performance function used
+ typedef enum {
+ TP_BEGINPROCAMDINITEARLY = 0x100, ///< BeginProcAmdInitEarly
+ TP_ENDPROCAMDINITEARLY = 0x101, ///< EndProcAmdInitEarly
+ TP_BEGINAMDTOPOINITIALIZE = 0x102, ///< BeginAmdTopoInitialize
+ TP_ENDAMDTOPOINITIALIZE = 0x103, ///< EndAmdTopoInitialize
+ TP_BEGINGNBINITATEARLIER = 0x104, ///< BeginGnbInitAtEarlier
+ TP_ENDGNBINITATEARLIER = 0x105, ///< EndGnbInitAtEarlier
+ TP_BEGINAMDCPUEARLY = 0x106, ///< BeginAmdCpuEarly
+ TP_ENDAMDCPUEARLY = 0x107, ///< EndAmdCpuEarly
+ TP_BEGINGNBINITATEARLY = 0x108, ///< BeginGnbInitAtEarly
+ TP_ENDGNBINITATEARLY = 0x109, ///< EndGnbInitAtEarly
+ TP_BEGINPROCAMDINITENV = 0x10A, ///< BeginProcAmdInitEnv
+ TP_ENDPROCAMDINITENV = 0x10B, ///< EndProcAmdInitEnv
+ TP_BEGININITENV = 0x10C, ///< BeginInitEnv
+ TP_ENDINITENV = 0x10D, ///< EndInitEnv
+ TP_BEGINGNBINITATENV = 0x10E, ///< BeginGnbInitAtEnv
+ TP_ENDGNBINITATENV = 0x10F, ///< EndGnbInitAtEnv
+ TP_BEGINPROCAMDINITLATE = 0x110, ///< BeginProcAmdInitLate
+ TP_ENDPROCAMDINITLATE = 0x111, ///< EndProcAmdInitLate
+ TP_BEGINCREATSYSTEMTABLE = 0x112, ///< BeginCreatSystemTable
+ TP_ENDCREATSYSTEMTABLE = 0x113, ///< EndCreatSystemTable
+ TP_BEGINDISPATCHCPUFEATURESLATE = 0x114, ///< BeginDispatchCpuFeaturesLate
+ TP_ENDDISPATCHCPUFEATURESLATE = 0x115, ///< EndDispatchCpuFeaturesLate
+ TP_BEGINAMDCPULATE = 0x116, ///< BeginAmdCpuLate
+ TP_ENDAMDCPULATE = 0x117, ///< EndAmdCpuLate
+ TP_BEGINGNBINITATLATE = 0x118, ///< BeginGnbInitAtLate
+ TP_ENDGNBINITATLATE = 0x119, ///< EndGnbInitAtLate
+ TP_BEGINPROCAMDINITMID = 0x11A, ///< BeginProcAmdInitMid
+ TP_ENDPROCAMDINITMID = 0x11B, ///< EndProcAmdInitMid
+ TP_BEGININITMID = 0x11E, ///< BeginInitMid
+ TP_ENDINITMID = 0x11F, ///< EndInitMid
+ TP_BEGINGNBINITATMID = 0x120, ///< BeginGnbInitAtMid
+ TP_ENDGNBINITATMID = 0x121, ///< EndGnbInitAtMid
+ TP_BEGINPROCAMDINITPOST = 0x122, ///< BeginProcAmdInitPost
+ TP_ENDPROCAMDINITPOST = 0x123, ///< EndProcAmdInitPost
+ TP_BEGINGNBINITATPOST = 0x124, ///< BeginGnbInitAtPost
+ TP_ENDGNBINITATPOST = 0x125, ///< EndGnbInitAtPost
+ TP_BEGINAMDMEMAUTO = 0x126, ///< BeginAmdMemAuto
+ TP_ENDAMDMEMAUTO = 0x127, ///< EndAmdMemAuto
+ TP_BEGINAMDCPUPOST = 0x128, ///< BeginAmdCpuPost
+ TP_ENDAMDCPUPOST = 0x129, ///< EndAmdCpuPost
+ TP_BEGINGNBINITATPOSTAFTERDRAM = 0x12A, ///< BeginGnbInitAtPostAfterDram
+ TP_ENDGNBINITATPOSTAFTERDRAM = 0x12B, ///< EndGnbInitAtPostAfterDram
+ TP_BEGINPROCAMDINITRESET = 0x12C, ///< BeginProcAmdInitReset
+ TP_ENDPROCAMDINITRESET = 0x12D, ///< EndProcAmdInitReset
+ TP_BEGININITRESET = 0x12E, ///< BeginInitReset
+ TP_ENDINITRESET = 0x12F, ///< EndInitReset
+ TP_BEGINHTINITRESET = 0x130, ///< BeginHtInitReset
+ TP_ENDHTINITRESET = 0x131, ///< EndHtInitReset
+ TP_BEGINPROCAMDINITRESUME = 0x132, ///< BeginProcAmdInitResume
+ TP_ENDPROCAMDINITRESUME = 0x133, ///< EndProcAmdInitResume
+ TP_BEGINAMDMEMS3RESUME = 0x134, ///< BeginAmdMemS3Resume
+ TP_ENDAMDMEMS3RESUME = 0x135, ///< EndAmdMemS3Resume
+ TP_BEGINDISPATCHCPUFEATURESS3RESUME = 0x136, ///< BeginDispatchCpuFeaturesS3Resume
+ TP_ENDDISPATCHCPUFEATURESS3RESUME = 0x137, ///< EndDispatchCpuFeaturesS3Resume
+ TP_BEGINSETCORESTSCFREQSEL = 0x138, ///< BeginSetCoresTscFreqSel
+ TP_ENDSETCORESTSCFREQSEL = 0x139, ///< EndSetCoresTscFreqSel
+ TP_BEGINMEMFMCTMEMCLR_INIT = 0x13A, ///< BeginMemFMctMemClr_Init
+ TP_ENDNMEMFMCTMEMCLR_INIT = 0x13B, ///< EndnMemFMctMemClr_Init
+ TP_BEGINMEMBEFOREMEMDATAINIT = 0x13C, ///< BeginMemBeforeMemDataInit
+ TP_ENDMEMBEFOREMEMDATAINIT = 0x13D, ///< EndMemBeforeMemDataInit
+ TP_BEGINPROCAMDMEMAUTO = 0x13E, ///< BeginProcAmdMemAuto
+ TP_ENDPROCAMDMEMAUTO = 0x13F, ///< EndProcAmdMemAuto
+ TP_BEGINMEMMFLOWC32 = 0x140, ///< BeginMemMFlowC32
+ TP_ENDMEMMFLOWC32 = 0x141, ///< EndMemMFlowC32
+ TP_BEGINMEMINITIALIZEMCT = 0x142, ///< BeginMemInitializeMCT
+ TP_ENDMEMINITIALIZEMCT = 0x143, ///< EndMemInitializeMCT
+ TP_BEGINMEMSYSTEMMEMORYMAPPING = 0x144, ///< BeginMemSystemMemoryMapping
+ TP_ENDMEMSYSTEMMEMORYMAPPING = 0x145, ///< EndMemSystemMemoryMapping
+ TP_BEGINMEMDRAMTRAINING = 0x146, ///< BeginMemDramTraining
+ TP_ENDMEMDRAMTRAINING = 0x147, ///< EndMemDramTraining
+ TP_BEGINMEMOTHERTIMING = 0x148, ///< BeginMemOtherTiming
+ TP_ENDMEMOTHERTIMING = 0x149, ///< EndMemOtherTiming
+ TP_BEGINMEMUMAMEMTYPING = 0x14A, ///< BeginMemUMAMemTyping
+ TP_ENDMEMUMAMEMTYPING = 0x14B, ///< EndMemUMAMemTyping
+ TP_BEGINMEMMEMCLR = 0x14C, ///< BeginMemMemClr
+ TP_ENDMEMMEMCLR = 0x14D, ///< EndMemMemClr
+ TP_BEGINMEMMFLOWTN = 0x14E, ///< BeginMemMFlowTN
+ TP_ENDMEMMFLOWTN = 0x14F, ///< EndMemMFlowTN
+ TP_BEGINAGESAHOOKBEFOREDRAMINIT = 0x150, ///< BeginAgesaHookBeforeDramInit
+ TP_ENDAGESAHOOKBEFOREDRAMINIT = 0x151, ///< EndAgesaHookBeforeDramInit
+ TP_BEGINPROCMEMDRAMTRAINING = 0x152, ///< BeginProcMemDramTraining
+ TP_ENDPROCMEMDRAMTRAINING = 0x153, ///< EndProcMemDramTraining
+ TP_BEGINGNBINITATS3SAVE = 0x154, ///< BeginGnbInitAtS3Save
+ TP_ENDGNBINITATS3SAVE = 0x155, ///< EndGnbInitAtS3Save
+ TP_BEGINGNBLOADSCSDATA = 0x156, ///< BeginGnbLoadScsData
+ TP_ENDGNBLOADSCSDATA = 0x157, ///< EndGnbLoadScsData
+ TP_BEGINGNBPCIETRAINING = 0x158, ///< BeginGnbPcieTraining
+ TP_ENDGNBPCIETRAINING = 0x159, ///< EndGnbPcieTraining
+ IDS_TP_END ///< End of IDS TP list
+ } IDS_PERF_DATA;
+#endif
diff --git a/src/vendorcode/amd/pi/00630F01/Include/Options.h b/src/vendorcode/amd/pi/00630F01/Include/Options.h
new file mode 100644
index 0000000..737dfb7
--- /dev/null
+++ b/src/vendorcode/amd/pi/00630F01/Include/Options.h
@@ -0,0 +1,68 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AGESA options structures
+ *
+ * Contains options control structures for the AGESA build options
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: Core
+ * @e \$Revision: 281181 $ @e \$Date: 2013-12-18 02:18:55 -0600 (Wed, 18 Dec 2013) $
+ */
+/*****************************************************************************
+ *
+ * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ***************************************************************************/
+
+
+#ifndef _OPTIONS_H_
+#define _OPTIONS_H_
+
+/**
+ * Provide topology limits for loops and runtime, based on supported families.
+ */
+typedef struct {
+ UINT32 PlatformNumberOfSockets; ///< The limit to the number of processors based on
+ ///< supported families and other build options.
+ UINT32 PlatformNumberOfModules; ///< The limit to the number of modules in a processor, based
+ ///< on supported families.
+} OPTIONS_CONFIG_TOPOLOGY;
+
+/**
+ * Dispatch Table.
+ *
+ * The push high dispatcher uses this table to find what entries are currently in the build image.
+ */
+typedef struct {
+ UINT32 FunctionId; ///< The function id specified.
+ IMAGE_ENTRY EntryPoint; ///< The corresponding entry point to call.
+} DISPATCH_TABLE;
+
+
+#endif // _OPTIONS_H_
diff --git a/src/vendorcode/amd/pi/00630F01/Include/PlatformMemoryConfiguration.h b/src/vendorcode/amd/pi/00630F01/Include/PlatformMemoryConfiguration.h
new file mode 100644
index 0000000..943bdf7
--- /dev/null
+++ b/src/vendorcode/amd/pi/00630F01/Include/PlatformMemoryConfiguration.h
@@ -0,0 +1,515 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD Platform Specific Memory Configuration
+ *
+ * Contains Definitions and Macros for control of AGESA Memory code on a per platform basis
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: OPTION
+ * @e \$Revision: 281181 $ @e \$Date: 2013-12-18 02:18:55 -0600 (Wed, 18 Dec 2013) $
+ *
+ */
+/*****************************************************************************
+ *
+ * Copyright 2008 - 2014 ADVANCED MICRO DEVICES, INC. All Rights Reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ***************************************************************************/
+
+#ifndef _PLATFORM_MEMORY_CONFIGURATION_H_
+#define _PLATFORM_MEMORY_CONFIGURATION_H_
+
+/*----------------------------------------------------------------------------------------
+ * M I X E D (Definitions And Macros / Typedefs, Structures, Enums)
+ *----------------------------------------------------------------------------------------
+ */
+#ifndef PSO_ENTRY
+ #define PSO_ENTRY UINT8
+#endif
+
+/*----------------------------------------------------------------------------------------
+ * D E F I N I T I O N S A N D M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+/*----------------------------------------------------------------------------------------
+ * T Y P E D E F S, S T R U C T U R E S, E N U M S
+ *----------------------------------------------------------------------------------------
+ */
+/*----------------------------------------------------------------------------------------
+ * PLATFORM SPECIFIC MEMORY DEFINITIONS
+ *----------------------------------------------------------------------------------------
+ */
+///
+/// Memory Speed and DIMM Population Masks
+///
+///< DDR Speed Masks
+///< Specifies the DDR Speed on a memory channel
+///
+#define ANY_SPEED 0xFFFFFFFFul
+#define DDR400 ((UINT32) 1 << (DDR400_FREQUENCY / 66))
+#define DDR533 ((UINT32) 1 << (DDR533_FREQUENCY / 66))
+#define DDR667 ((UINT32) 1 << (DDR667_FREQUENCY / 66))
+#define DDR800 ((UINT32) 1 << (DDR800_FREQUENCY / 66))
+#define DDR1066 ((UINT32) 1 << (DDR1066_FREQUENCY / 66))
+#define DDR1333 ((UINT32) 1 << (DDR1333_FREQUENCY / 66))
+#define DDR1600 ((UINT32) 1 << (DDR1600_FREQUENCY / 66))
+#define DDR1866 ((UINT32) 1 << (DDR1866_FREQUENCY / 66))
+#define DDR2133 ((UINT32) 1 << (DDR2133_FREQUENCY / 66))
+#define DDR2400 ((UINT32) 1 << (DDR2400_FREQUENCY / 66))
+///
+///< DIMM POPULATION MASKS
+///< Specifies the DIMM Population on a channel (can be added together to specify configuration).
+///< ex. SR_DIMM0 + SR_DIMM1 : Single Rank Dimm in slot 0 AND Slot 1
+///< SR_DIMM0 + DR_DIMM0 + SR_DIMM1 +DR_DIMM1 : Single OR Dual rank in Slot 0 AND Single OR Dual rank in Slot 1
+///
+#define ANY_ 0xFF ///< Any dimm configuration the current channel
+#define SR_DIMM0 0x0001 ///< Single rank dimm in slot 0 on the current channel
+#define SR_DIMM1 0x0010 ///< Single rank dimm in slot 1 on the current channel
+#define SR_DIMM2 0x0100 ///< Single rank dimm in slot 2 on the current channel
+#define SR_DIMM3 0x1000 ///< Single rank dimm in slot 3 on the current channel
+#define DR_DIMM0 0x0002 ///< Dual rank dimm in slot 0 on the current channel
+#define DR_DIMM1 0x0020 ///< Dual rank dimm in slot 1 on the current channel
+#define DR_DIMM2 0x0200 ///< Dual rank dimm in slot 2 on the current channel
+#define DR_DIMM3 0x2000 ///< Dual rank dimm in slot 3 on the current channel
+#define QR_DIMM0 0x0004 ///< Quad rank dimm in slot 0 on the current channel
+#define QR_DIMM1 0x0040 ///< Quad rank dimm in slot 1 on the current channel
+#define QR_DIMM2 0x0400 ///< Quad rank dimm in slot 2 on the current channel
+#define QR_DIMM3 0x4000 ///< Quad rank dimm in slot 3 on the current channel
+#define LR_DIMM0 0x0001 ///< Lrdimm in slot 0 on the current channel
+#define LR_DIMM1 0x0010 ///< Lrdimm in slot 1 on the current channel
+#define LR_DIMM2 0x0100 ///< Lrdimm in slot 2 on the current channel
+#define LR_DIMM3 0x1000 ///< Lrdimm in slot 3 on the current channel
+#define ANY_DIMM0 0x000F ///< Any Dimm combination in slot 0 on the current channel
+#define ANY_DIMM1 0x00F0 ///< Any Dimm combination in slot 1 on the current channel
+#define ANY_DIMM2 0x0F00 ///< Any Dimm combination in slot 2 on the current channel
+#define ANY_DIMM3 0xF000 ///< Any Dimm combination in slot 3 on the current channel
+///
+///< CS POPULATION MASKS
+///< Specifies the CS Population on a channel (can be added together to specify configuration).
+///< ex. CS0 + CS1 : CS0 and CS1 apply to the setting
+///
+#define CS_ANY_ 0xFF ///< Any CS configuration
+#define CS0_ 0x01 ///< CS0 bit map mask
+#define CS1_ 0x02 ///< CS1 bit map mask
+#define CS2_ 0x04 ///< CS2 bit map mask
+#define CS3_ 0x08 ///< CS3 bit map mask
+#define CS4_ 0x10 ///< CS4 bit map mask
+#define CS5_ 0x20 ///< CS5 bit map mask
+#define CS6_ 0x40 ///< CS6 bit map mask
+#define CS7_ 0x80 ///< CS7 bit map mask
+///
+///< Number of Dimms on the current channel
+///< This is a mask used to indicate the number of dimms in a channel
+///< They can be added to indicate multiple conditions (i.e 1 OR 2 Dimms)
+///
+#define ANY_NUM 0xFF ///< Any number of Dimms
+#define NO_DIMM 0x00 ///< No Dimms present
+#define ONE_DIMM 0x01 ///< One dimm Poulated on the current channel
+#define TWO_DIMM 0x02 ///< Two dimms Poulated on the current channel
+#define THREE_DIMM 0x04 ///< Three dimms Poulated on the current channel
+#define FOUR_DIMM 0x08 ///< Four dimms Poulated on the current channel
+
+///
+///< DIMM VOLTAGE MASKS
+///
+#define VOLT_ANY_ 0xFF ///< Any voltage configuration
+#define VOLT1_5_ 0x01 ///< Voltage 1.5V bit map mask
+#define VOLT1_35_ 0x02 ///< Voltage 1.35V bit map mask
+#define VOLT1_25_ 0x04 ///< Voltage 1.25V bit map mask
+
+//
+// < Not applicable
+//
+#define NA_ 0 ///< Not applicable
+
+/*----------------------------------------------------------------------------------------
+ *
+ * Platform Specific Override Definitions for Socket, Channel and Dimm
+ * This indicates where a platform override will be applied.
+ *
+ *----------------------------------------------------------------------------------------
+ */
+///
+///< SOCKET MASKS
+///< Indicates associated processor sockets to apply override settings
+///
+#define ANY_SOCKET 0xFF ///< Apply to all sockets
+#define SOCKET0 0x01 ///< Apply to socket 0
+#define SOCKET1 0x02 ///< Apply to socket 1
+#define SOCKET2 0x04 ///< Apply to socket 2
+#define SOCKET3 0x08 ///< Apply to socket 3
+#define SOCKET4 0x10 ///< Apply to socket 4
+#define SOCKET5 0x20 ///< Apply to socket 5
+#define SOCKET6 0x40 ///< Apply to socket 6
+#define SOCKET7 0x80 ///< Apply to socket 7
+///
+///< CHANNEL MASKS
+///< Indicates Memory channels where override should be applied
+///
+#define ANY_CHANNEL 0xFF ///< Apply to all Memory channels
+#define CHANNEL_A 0x01 ///< Apply to Channel A
+#define CHANNEL_B 0x02 ///< Apply to Channel B
+#define CHANNEL_C 0x04 ///< Apply to Channel C
+#define CHANNEL_D 0x08 ///< Apply to Channel D
+///
+/// DIMM MASKS
+/// Indicates Dimm Slots where override should be applied
+///
+#define ALL_DIMMS 0xFF ///< Apply to all dimm slots
+#define DIMM0 0x01 ///< Apply to Dimm Slot 0
+#define DIMM1 0x02 ///< Apply to Dimm Slot 1
+#define DIMM2 0x04 ///< Apply to Dimm Slot 2
+#define DIMM3 0x08 ///< Apply to Dimm Slot 3
+///
+/// REGISTER ACCESS MASKS
+/// Not supported as an at this time
+///
+#define ACCESS_NB0 0x0
+#define ACCESS_NB1 0x1
+#define ACCESS_NB2 0x2
+#define ACCESS_NB3 0x3
+#define ACCESS_NB4 0x4
+#define ACCESS_PHY 0x5
+#define ACCESS_DCT_XT 0x6
+///
+/// MOTHER BOARD DESIGN LAYERS MASKS
+/// Indicates the layer design of mother board
+///
+#define LAYERS_4 0x0
+#define LAYERS_6 0x1
+/*----------------------------------------------------------------------------------------
+ *
+ * Platform Specific Overriding Table Definitions
+ *
+ *----------------------------------------------------------------------------------------
+ */
+
+#define PSO_END 0 ///< Table End
+#define PSO_CKE_TRI 1 ///< CKE Tristate Map
+#define PSO_ODT_TRI 2 ///< ODT Tristate Map
+#define PSO_CS_TRI 3 ///< CS Tristate Map
+#define PSO_MAX_DIMMS 4 ///< Max Dimms per channel
+#define PSO_CLK_SPEED 5 ///< Clock Speed
+#define PSO_DIMM_TYPE 6 ///< Dimm Type
+#define PSO_MEMCLK_DIS 7 ///< MEMCLK Disable Map
+#define PSO_MAX_CHNLS 8 ///< Max Channels per Socket
+#define PSO_BUS_SPEED 9 ///< Max Memory Bus Speed
+#define PSO_MAX_CHIPSELS 10 ///< Max Chipsel per Channel
+#define PSO_MEM_TECH 11 ///< Channel Memory Type
+#define PSO_WL_SEED 12 ///< DDR3 Write Levelization Seed delay
+#define PSO_RXEN_SEED 13 ///< Hardwared based RxEn seed
+#define PSO_NO_LRDIMM_CS67_ROUTING 14 ///< CS6 and CS7 are not Routed to all Memoy slots on a channel for LRDIMMs
+#define PSO_SOLDERED_DOWN_SODIMM_TYPE 15 ///< Soldered down SODIMM type
+#define PSO_LVDIMM_VOLT1_5_SUPPORT 16 ///< Force LvDimm voltage to 1.5V
+#define PSO_MIN_RD_WR_DATAEYE_WIDTH 17 ///< Min RD/WR dataeye width
+#define PSO_CPU_FAMILY_TO_OVERRIDE 18 ///< CPU family signature to tell following PSO macros are CPU family dependent
+#define PSO_MAX_SOLDERED_DOWN_DIMMS 19 ///< Max Soldered-down Dimms per channel
+#define PSO_MEMORY_POWER_POLICY 20 ///< Memory power policy override
+#define PSO_MOTHER_BOARD_LAYERS 21 ///< Mother board layer design
+
+/*----------------------------------
+ * CONDITIONAL PSO SPECIFIC ENTRIES
+ *---------------------------------*/
+// Condition Types
+#define CONDITIONAL_PSO_MIN 100 ///< Start of Conditional Entry Types
+#define PSO_CONDITION_AND 100 ///< And Block - Start of Conditional block
+#define PSO_CONDITION_LOC 101 ///< Location - Specify Socket, Channel, Dimms to be affected
+#define PSO_CONDITION_SPD 102 ///< SPD - Specify a specific SPD value on a Dimm on the channel
+#define PSO_CONDITION_REG 103 // Reserved
+#define PSO_CONDITION_MAX 103 ///< End Of Condition Entry Types
+// Action Types
+#define PSO_ACTION_MIN 120 ///< Start of Action Entry Types
+#define PSO_ACTION_ODT 120 ///< ODT values to override
+#define PSO_ACTION_ADDRTMG 121 ///< Address/Timing values to override
+#define PSO_ACTION_ODCCONTROL 122 ///< ODC Control values to override
+#define PSO_ACTION_SLEWRATE 123 ///< Slew Rate value to override
+#define PSO_ACTION_REG 124 // Reserved
+#define PSO_ACTION_SPEEDLIMIT 125 ///< Memory Bus speed Limit based on configuration
+#define PSO_ACTION_MAX 125 ///< End of Action Entry Types
+#define CONDITIONAL_PSO_MAX 139 ///< End of Conditional Entry Types
+
+/*----------------------------------
+ * TABLE DRIVEN PSO SPECIFIC ENTRIES
+ *---------------------------------*/
+// Condition descriptor
+#define PSO_TBLDRV_CONFIG 200 ///< Configuration Descriptor
+
+// Overriding entry types
+#define PSO_TBLDRV_START 210 ///< Start of Table Driven Overriding Entry Types
+#define PSO_TBLDRV_SPEEDLIMIT 210 ///< Speed Limit
+#define PSO_TBLDRV_ODT_RTTNOM 211 ///< RttNom
+#define PSO_TBLDRV_ODT_RTTWR 212 ///< RttWr
+#define PSO_TBLDRV_ODTPATTERN 213 ///< Odt Patterns
+#define PSO_TBLDRV_ADDRTMG 214 ///< Address/Timing values
+#define PSO_TBLDRV_ODCCTRL 215 ///< ODC Control values
+#define PSO_TBLDRV_SLOWACCMODE 216 ///< Slow Access Mode
+#define PSO_TBLDRV_MR0_CL 217 ///< MR0[CL]
+#define PSO_TBLDRV_MR0_WR 218 ///< MR0[WR]
+#define PSO_TBLDRV_RC2_IBT 219 ///< RC2[IBT]
+#define PSO_TBLDRV_RC10_OPSPEED 220 ///< RC10[Opearting Speed]
+#define PSO_TBLDRV_LRDIMM_IBT 221 ///< LrDIMM IBT
+#define PSO_TBLDRV_2D_TRAINING 222 ///< 2D training
+#define PSO_TBLDRV_INVALID_TYPE 223 ///< Invalid Type
+#define PSO_TBLDRV_END 223 ///< End of Table Driven Overriding Entry Types
+
+/*----------------------------------------------------------------------------------------
+ * CONDITIONAL OVERRIDE TABLE MACROS
+ *----------------------------------------------------------------------------------------
+ */
+#define CPU_FAMILY_TO_OVERRIDE(CpuFamilyRevision) \
+ PSO_CPU_FAMILY_TO_OVERRIDE, 4, \
+ ((CpuFamilyRevision) & 0x0FF), (((CpuFamilyRevision) >> 8)& 0x0FF), (((CpuFamilyRevision) >> 16)& 0x0FF), (((CpuFamilyRevision) >> 24)& 0x0FF)
+
+#define MEMCLK_DIS_MAP(SocketID, ChannelID, Bit0Map, Bit1Map, Bit2Map, Bit3Map, Bit4Map, Bit5Map, Bit6Map, Bit7Map) \
+ PSO_MEMCLK_DIS, 11, SocketID, ChannelID, ALL_DIMMS, Bit0Map, Bit1Map, Bit2Map, Bit3Map, Bit4Map, Bit5Map, Bit6Map \
+ , Bit7Map
+
+#define CKE_TRI_MAP(SocketID, ChannelID, Bit0Map, Bit1Map, Bit2Map, Bit3Map) \
+ PSO_CKE_TRI, 7, SocketID, ChannelID, ALL_DIMMS, Bit0Map, Bit1Map, Bit2Map, Bit3Map
+
+#define ODT_TRI_MAP(SocketID, ChannelID, Bit0Map, Bit1Map, Bit2Map, Bit3Map) \
+ PSO_ODT_TRI, 7, SocketID, ChannelID, ALL_DIMMS, Bit0Map, Bit1Map, Bit2Map, Bit3Map
+
+#define CS_TRI_MAP(SocketID, ChannelID, Bit0Map, Bit1Map, Bit2Map, Bit3Map, Bit4Map, Bit5Map, Bit6Map, Bit7Map) \
+ PSO_CS_TRI, 11, SocketID, ChannelID, ALL_DIMMS, Bit0Map, Bit1Map, Bit2Map, Bit3Map, Bit4Map, Bit5Map, Bit6Map, Bit7Map
+
+#define NUMBER_OF_DIMMS_SUPPORTED(SocketID, ChannelID, NumberOfDimmSlotsPerChannel) \
+ PSO_MAX_DIMMS, 4, SocketID, ChannelID, ALL_DIMMS, NumberOfDimmSlotsPerChannel
+
+#define NUMBER_OF_SOLDERED_DOWN_DIMMS_SUPPORTED(SocketID, ChannelID, NumberOfSolderedDownDimmsPerChannel) \
+ PSO_MAX_SOLDERED_DOWN_DIMMS, 4, SocketID, ChannelID, ALL_DIMMS, NumberOfSolderedDownDimmsPerChannel
+
+#define NUMBER_OF_CHIP_SELECTS_SUPPORTED(SocketID, ChannelID, NumberOfChipSelectsPerChannel) \
+ PSO_MAX_CHIPSELS, 4, SocketID, ChannelID, ALL_DIMMS, NumberOfChipSelectsPerChannel
+
+#define NUMBER_OF_CHANNELS_SUPPORTED(SocketID, NumberOfChannelsPerSocket) \
+ PSO_MAX_CHNLS, 4, SocketID, ANY_CHANNEL, ALL_DIMMS, NumberOfChannelsPerSocket
+
+#define OVERRIDE_DDR_BUS_SPEED(SocketID, ChannelID, TimingMode, BusSpeed) \
+ PSO_BUS_SPEED, 11, SocketID, ChannelID, ALL_DIMMS, TimingMode, (TimingMode >> 8), (TimingMode >> 16), (TimingMode >> 24), \
+ BusSpeed, (BusSpeed >> 8), (BusSpeed >> 16), (BusSpeed >> 24)
+
+#define DRAM_TECHNOLOGY(SocketID, MemTechType) \
+ PSO_MEM_TECH, 7, SocketID, ANY_CHANNEL, ALL_DIMMS, MemTechType, (MemTechType >> 8), (MemTechType >> 16), (MemTechType >> 24)
+
+#define WRITE_LEVELING_SEED(SocketID, ChannelID, DimmID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed, \
+ Byte6Seed, Byte7Seed, ByteEccSeed) \
+ PSO_WL_SEED, 12, SocketID, ChannelID, DimmID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed, \
+ Byte6Seed, Byte7Seed, ByteEccSeed
+
+#define HW_RXEN_SEED(SocketID, ChannelID, DimmID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed, \
+ Byte6Seed, Byte7Seed, ByteEccSeed) \
+ PSO_RXEN_SEED, 21, SocketID, ChannelID, DimmID, Byte0Seed, (Byte0Seed >> 8), Byte1Seed, (Byte1Seed >> 8), Byte2Seed, (Byte2Seed >> 8), \
+ Byte3Seed, (Byte3Seed >> 8), Byte4Seed, (Byte4Seed >> 8), Byte5Seed, (Byte5Seed >> 8), Byte6Seed, (Byte6Seed >> 8), \
+ Byte7Seed, (Byte7Seed >> 8), ByteEccSeed, (ByteEccSeed >> 8)
+
+#define NO_LRDIMM_CS67_ROUTING(SocketID, ChannelID) \
+ PSO_NO_LRDIMM_CS67_ROUTING, 4, SocketID, ChannelID, ALL_DIMMS, TRUE
+
+#define SOLDERED_DOWN_SODIMM_TYPE(SocketID, ChannelID) \
+ PSO_SOLDERED_DOWN_SODIMM_TYPE, 4, SocketID, ChannelID, ALL_DIMMS, TRUE
+
+#define LVDIMM_FORCE_VOLT1_5_FOR_D0 \
+ PSO_LVDIMM_VOLT1_5_SUPPORT, 4, ANY_SOCKET, ANY_CHANNEL, ALL_DIMMS, TRUE
+
+#define MIN_RD_WR_DATAEYE_WIDTH(SocketID, ChannelID, MinRdDataeyeWidth, MinWrDataeyeWidth) \
+ PSO_MIN_RD_WR_DATAEYE_WIDTH, 5, SocketID, ChannelID, ALL_DIMMS, MinRdDataeyeWidth, MinWrDataeyeWidth
+
+#define MEMORY_POWER_POLICY_OVERRIDE(PowerPolicy) \
+ PSO_MEMORY_POWER_POLICY, 4, ANY_SOCKET, ANY_CHANNEL, ALL_DIMMS, PowerPolicy
+
+#define MOTHER_BOARD_LAYERS(Layers) \
+ PSO_MOTHER_BOARD_LAYERS, 4, ANY_SOCKET, ANY_CHANNEL, ALL_DIMMS, Layers
+
+/*----------------------------------------------------------------------------------------
+ * CONDITIONAL OVERRIDE TABLE MACROS
+ *----------------------------------------------------------------------------------------
+ */
+#define CONDITION_AND \
+ PSO_CONDITION_AND, 0
+
+#define COND_LOC(SocketMsk, ChannelMsk, DimmMsk) \
+ PSO_CONDITION_LOC, 3, SocketMsk, ChannelMsk, DimmMsk
+
+#define COND_SPD(Byte, Mask, Value) \
+ PSO_CONDITION_SPD, 3, Byte, Mask, Value
+
+#define COND_REG(Access, Offset, Mask, Value) \
+ PSO_CONDITION_REG, 11, Access, (Offset & 0x0FF), (Offset >> 8), \
+ ((Mask) & 0x0FF), (((Mask) >> 8) & 0x0FF), (((Mask) >> 16) & 0x0FF), (((Mask) >> 24) & 0x0FF), \
+ ((Value) & 0x0FF), (((Value) >> 8) & 0x0FF), (((Value) >> 16) & 0x0FF), (((Value) >> 24) & 0x0FF)
+
+#define ACTION_ODT(Frequency, Dimms, QrDimms, DramOdt, QrDramOdt, DramDynOdt) \
+ PSO_ACTION_ODT, 9, \
+ ((Frequency) & 0x0FF), (((Frequency) >> 8)& 0x0FF), (((Frequency) >> 16)& 0x0FF), ((Frequency >> 24)& 0x0FF), \
+ Dimms, QrDimms, DramOdt, QrDramOdt, DramDynOdt
+
+#define ACTION_ADDRTMG(Frequency, DimmConfig, AddrTmg) \
+ PSO_ACTION_ADDRTMG, 10, \
+ ((Frequency) & 0x0FF), (((Frequency) >> 8)& 0x0FF), (((Frequency) >> 16)& 0x0FF), (((Frequency) >> 24)& 0x0FF), \
+ ((DimmConfig) & 0x0FF), (((DimmConfig) >> 8) & 0x0FF), \
+ (AddrTmg & 0x0FF), ((AddrTmg >> 8)& 0x0FF), ((AddrTmg >> 16)& 0x0FF), ((AddrTmg >> 24)& 0x0FF)
+
+#define ACTION_ODCCTRL(Frequency, DimmConfig, OdcCtrl) \
+ PSO_ACTION_ODCCONTROL, 10, \
+ ((Frequency) & 0x0FF), (((Frequency) >> 8)& 0x0FF), (((Frequency) >> 16)& 0x0FF), (((Frequency) >> 24)& 0x0FF), \
+ ((DimmConfig) & 0x0FF), (((DimmConfig) >> 8) & 0x0FF), \
+ (OdcCtrl & 0x0FF), ((OdcCtrl >> 8)& 0x0FF), ((OdcCtrl >> 16)& 0x0FF), ((OdcCtrl >> 24)& 0x0FF)
+
+#define ACTION_SLEWRATE(Frequency, DimmConfig, SlewRate) \
+ PSO_ACTION_SLEWRATE, 10, \
+ ((Frequency) & 0x0FF), (((Frequency) >> 8)& 0x0FF), (((Frequency) >> 16)& 0x0FF), (((Frequency) >> 24)& 0x0FF), \
+ ((DimmConfig) & 0x0FF), (((DimmConfig) >> 8) & 0x0FF), \
+ (SlewRate & 0x0FF), ((SlewRate >> 8)& 0x0FF), ((SlewRate >> 16)& 0x0FF), ((SlewRate >> 24)& 0x0FF)
+
+#define ACTION_SPEEDLIMIT(DimmConfig, Dimms, SpeedLimit15, SpeedLimit135, SpeedLimit125) \
+ PSO_ACTION_SPEEDLIMIT, 9, \
+ ((DimmConfig) & 0x0FF), (((DimmConfig) >> 8) & 0x0FF), Dimms, \
+ (SpeedLimit15 & 0x0FF), ((SpeedLimit15 >> 8)& 0x0FF), \
+ (SpeedLimit135 & 0x0FF), ((SpeedLimit135 >> 8)& 0x0FF), \
+ (SpeedLimit125 & 0x0FF), ((SpeedLimit125 >> 8)& 0x0FF)
+
+/*----------------------------------------------------------------------------------------
+ * END OF CONDITIONAL OVERRIDE TABLE MACROS
+ *----------------------------------------------------------------------------------------
+ */
+/*----------------------------------------------------------------------------------------
+ * TABLE DRIVEN OVERRIDE MACROS
+ *----------------------------------------------------------------------------------------
+ */
+/// Configuration sub-descriptors
+typedef enum {
+ CONFIG_GENERAL, ///< CONFIG_GENERAL
+ CONFIG_SPEEDLIMIT, ///< CONFIG_SPEEDLIMIT
+ CONFIG_RC2IBT, ///< CONFIG_RC2IBT
+ CONFIG_DONT_CARE, ///< CONFIG_DONT_CARE
+} Config_Type;
+
+// ====================
+// Configuration Macros
+// ====================
+#define TBLDRV_CONFIG_TO_OVERRIDE(DimmPerCH, Frequency, DimmVolt, DimmConfig) \
+ PSO_TBLDRV_CONFIG, 9, \
+ CONFIG_GENERAL, \
+ DimmPerCH, DimmVolt, \
+ ((Frequency) & 0x0FF), (((Frequency) >> 8)& 0x0FF), (((Frequency) >> 16)& 0x0FF), (((Frequency) >> 24)& 0x0FF), \
+ ((DimmConfig) & 0x0FF), (((DimmConfig) >> 8) & 0x0FF)
+
+#define TBLDRV_SPEEDLIMIT_CONFIG_TO_OVERRIDE(DimmPerCH, Dimms, NumOfSR, NumOfDR, NumOfQR, NumOfLRDimm) \
+ PSO_TBLDRV_CONFIG, 7, \
+ CONFIG_SPEEDLIMIT, \
+ DimmPerCH, Dimms, NumOfSR, NumOfDR, NumOfQR, NumOfLRDimm
+
+#define TBLDRV_RC2IBT_CONFIG_TO_OVERRIDE(DimmPerCH, Frequency, DimmVolt, DimmConfig, NumOfReg) \
+ PSO_TBLDRV_CONFIG, 10, \
+ CONFIG_RC2IBT, \
+ DimmPerCH, DimmVolt, \
+ ((Frequency) & 0x0FF), (((Frequency) >> 8)& 0x0FF), (((Frequency) >> 16)& 0x0FF), (((Frequency) >> 24)& 0x0FF), \
+ ((DimmConfig) & 0x0FF), (((DimmConfig) >> 8) & 0x0FF), \
+ NumOfReg
+
+//==================
+// Overriding Macros
+//==================
+#define TBLDRV_CONFIG_ENTRY_SPEEDLIMIT(SpeedLimit1_5, SpeedLimit1_35, SpeedLimit1_25) \
+ PSO_TBLDRV_SPEEDLIMIT, 6, \
+ (SpeedLimit1_5 & 0x0FF), ((SpeedLimit1_5 >> 8)& 0x0FF), \
+ (SpeedLimit1_35 & 0x0FF), ((SpeedLimit1_35 >> 8)& 0x0FF), \
+ (SpeedLimit1_25 & 0x0FF), ((SpeedLimit1_25 >> 8)& 0x0FF)
+
+#define TBLDRV_CONFIG_ENTRY_ODT_RTTNOM(TgtCS, RttNom) \
+ PSO_TBLDRV_ODT_RTTNOM, 2, \
+ TgtCS, RttNom
+
+#define TBLDRV_CONFIG_ENTRY_ODT_RTTWR(TgtCS, RttWr) \
+ PSO_TBLDRV_ODT_RTTWR, 2, \
+ TgtCS, RttWr
+
+#define TBLDRV_CONFIG_ENTRY_ODTPATTERN(RdODTCSHigh, RdODTCSLow, WrODTCSHigh, WrODTCSLow) \
+ PSO_TBLDRV_ODTPATTERN, 16, \
+ ((RdODTCSHigh) & 0x0FF), (((RdODTCSHigh) >> 8)& 0x0FF), (((RdODTCSHigh) >> 16)& 0x0FF), (((RdODTCSHigh) >> 24)& 0x0FF), \
+ ((RdODTCSLow) & 0x0FF), (((RdODTCSLow) >> 8)& 0x0FF), (((RdODTCSLow) >> 16)& 0x0FF), (((RdODTCSLow) >> 24)& 0x0FF), \
+ ((WrODTCSHigh) & 0x0FF), (((WrODTCSHigh) >> 8)& 0x0FF), (((WrODTCSHigh) >> 16)& 0x0FF), (((WrODTCSHigh) >> 24)& 0x0FF), \
+ ((WrODTCSLow) & 0x0FF), (((WrODTCSLow) >> 8)& 0x0FF), (((WrODTCSLow) >> 16)& 0x0FF), (((WrODTCSLow) >> 24)& 0x0FF)
+
+#define TBLDRV_CONFIG_ENTRY_ADDRTMG(AddrTmg) \
+ PSO_TBLDRV_ADDRTMG, 4, \
+ ((AddrTmg) & 0x0FF), (((AddrTmg) >> 8)& 0x0FF), (((AddrTmg) >> 16)& 0x0FF), (((AddrTmg) >> 24)& 0x0FF)
+
+#define TBLDRV_CONFIG_ENTRY_ODCCTRL(OdcCtrl) \
+ PSO_TBLDRV_ODCCTRL, 4, \
+ ((OdcCtrl) & 0x0FF), (((OdcCtrl) >> 8)& 0x0FF), (((OdcCtrl) >> 16)& 0x0FF), (((OdcCtrl) >> 24)& 0x0FF)
+
+#define TBLDRV_CONFIG_ENTRY_SLOWACCMODE(SlowAccMode) \
+ PSO_TBLDRV_SLOWACCMODE, 1, \
+ SlowAccMode
+
+#define TBLDRV_CONFIG_ENTRY_RC2_IBT(TgtDimm, IBT) \
+ PSO_TBLDRV_RC2_IBT, 2, \
+ TgtDimm, IBT
+
+#define TBLDRV_OVERRIDE_MR0_CL(RegValOfTcl, MR0CL13, MR0CL0) \
+ PSO_TBLDRV_CONFIG, 1, \
+ CONFIG_DONT_CARE, \
+ PSO_TBLDRV_MR0_CL, 3, \
+ RegValOfTcl, MR0CL13, MR0CL0
+
+#define TBLDRV_OVERRIDE_MR0_WR(RegValOfTwr, MR0WR) \
+ PSO_TBLDRV_CONFIG, 1, \
+ CONFIG_DONT_CARE, \
+ PSO_TBLDRV_MR0_WR, 2, \
+ RegValOfTwr, MR0WR
+
+#define TBLDRV_OVERRIDE_RC10_OPSPEED(Frequency, MR10OPSPEED) \
+ PSO_TBLDRV_CONFIG, 1, \
+ CONFIG_DONT_CARE, \
+ PSO_TBLDRV_RC10_OPSPEED, 5, \
+ ((Frequency) & 0x0FF), (((Frequency) >> 8)& 0x0FF), (((Frequency) >> 16)& 0x0FF), (((Frequency) >> 24)& 0x0FF), \
+ MR10OPSPEED
+
+#define TBLDRV_CONFIG_ENTRY_LRDMM_IBT(F0RC8, F1RC0, F1RC1, F1RC2) \
+ PSO_TBLDRV_LRDIMM_IBT, 4, \
+ F0RC8, F1RC0, F1RC1, F1RC2
+
+#define TBLDRV_CONFIG_ENTRY_2D_TRAINING(Training2dMode) \
+ PSO_TBLDRV_2D_TRAINING, 1, \
+ Training2dMode
+
+//============================
+// Macros for removing entries
+//============================
+#define INVALID_CONFIG_FLAG 0x8000
+
+#define TBLDRV_INVALID_CONFIG \
+ PSO_TBLDRV_INVALID_TYPE, 0
+
+/*----------------------------------------------------------------------------------------
+ * END OF TABLE DRIVEN OVERRIDE MACROS
+ *----------------------------------------------------------------------------------------
+ */
+
+#endif // _PLATFORM_MEMORY_CONFIGURATION_H_
diff --git a/src/vendorcode/amd/pi/00630F01/Include/Topology.h b/src/vendorcode/amd/pi/00630F01/Include/Topology.h
new file mode 100644
index 0000000..489248b
--- /dev/null
+++ b/src/vendorcode/amd/pi/00630F01/Include/Topology.h
@@ -0,0 +1,86 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Topology interface definitions.
+ *
+ * Contains AMD AGESA internal interface for topology related data which
+ * is consumed by code other than Topology Services init.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: Core
+ * @e \$Revision: 281181 $ @e \$Date: 2013-12-18 02:18:55 -0600 (Wed, 18 Dec 2013) $
+ */
+/*****************************************************************************
+ *
+ * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ***************************************************************************/
+
+#ifndef _TOPOLOGY_H_
+#define _TOPOLOGY_H_
+
+// Defines for limiting data structure maximum allocation and limit checking.
+#define MAX_NODES 1
+#define MAX_SOCKETS MAX_NODES
+#define MAX_DIES 1
+
+/**
+ * Socket and Module to Node Map Item.
+ * Provide the Node Id and core id range for each module in each processor.
+ */
+typedef struct {
+ UINT8 Node; ///< The module's Node id.
+ UINT8 LowCore; ///< The lowest processor core id for this module.
+ UINT8 HighCore; ///< The highest processor core id for this module.
+ UINT8 EnabledComputeUnits; ///< The value of Enabled for this processor module.
+ UINT8 DualCoreComputeUnits; ///< The value of DualCore for this processor module.
+ UINT8 TripleCoreComputeUnits;///< The value of TripleCore for this processor module.
+ UINT8 QuadCoreComputeUnits; ///< The value of QuadCore for this processor module.
+} SOCKET_DIE_TO_NODE_ITEM;
+
+/**
+ * Socket and Module to Node Map.
+ * This type is a pointer to the actual map, it can be used for a struct item or
+ * for typecasting a heap buffer pointer.
+ */
+typedef SOCKET_DIE_TO_NODE_ITEM (*SOCKET_DIE_TO_NODE_MAP)[MAX_SOCKETS][MAX_DIES];
+
+/**
+ * Node id to Socket Die Map Item.
+ */
+typedef struct {
+ UINT8 Socket; ///< socket of the processor containing the Node.
+ UINT8 Die; ///< the module in the processor which is Node.
+} NODE_TO_SOCKET_DIE_ITEM;
+
+/**
+ * Node id to Socket Die Map.
+ */
+typedef NODE_TO_SOCKET_DIE_ITEM (*NODE_TO_SOCKET_DIE_MAP)[MAX_NODES];
+
+#endif // _TOPOLOGY_H_
diff --git a/src/vendorcode/amd/pi/00630F01/Porting.h b/src/vendorcode/amd/pi/00630F01/Porting.h
new file mode 100644
index 0000000..9bafee1
--- /dev/null
+++ b/src/vendorcode/amd/pi/00630F01/Porting.h
@@ -0,0 +1,299 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Describes compiler dependencies - to support several compile time environments
+ *
+ * Contains compiler environment porting descriptions
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: Includes
+ * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 03:16:51 -0600 (Wed, 22 Dec 2010) $
+ */
+/*****************************************************************************
+ *
+ * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
+ * 2013 - 2014, Sage Electronic Engineering, LLC
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ***************************************************************************/
+
+#ifndef _PORTING_H_
+#define _PORTING_H_
+
+#if defined (_MSC_VER)
+ #pragma warning(push)
+ #pragma warning(disable: 4103 4001 4733)
+ // -----------------------------------------------------------------------
+ // Define a code_seg MACRO
+ //
+ #define MAKE_AS_A_STRING(arg) #arg
+
+ #define CODE_GROUP(arg) __pragma (code_seg (MAKE_AS_A_STRING (.t##arg)))
+
+ #define RDATA_GROUP(arg) __pragma (const_seg (MAKE_AS_A_STRING (.d##arg)))
+ #define FUNC_ATTRIBUTE(arg) __declspec(arg)
+ //#include <intrin.h> // MS has built-in functions
+
+ #if _MSC_VER < 900
+ // -----------------------------------------------------------------------
+ // Assume MSVC 1.52C (16-bit)
+ //
+ // NOTE: When using MSVC 1.52C use the following command line:
+ //
+ // CL.EXE /G3 /AL /O1i /Fa <FILENAME.C>
+ //
+ // This will produce 32-bit code in USE16 segment that is optimized for code
+ // size.
+ typedef void VOID;
+
+ // Create the universal 32, 16, and 8-bit data types
+ typedef unsigned long UINTN;
+ typedef long INT32;
+ typedef unsigned long UINT32;
+ typedef int INT16;
+ typedef unsigned int UINT16;
+ typedef char INT8;
+ typedef unsigned char UINT8;
+ typedef char CHAR8;
+ typedef unsigned short CHAR16;
+
+ /// struct for 16-bit environment handling of 64-bit value
+ typedef struct _UINT64 {
+ IN OUT UINT32 lo; ///< lower 32-bits of 64-bit value
+ IN OUT UINT32 hi; ///< highest 32-bits of 64-bit value
+ } UINT64;
+
+ // Create the Boolean type
+ #define TRUE 1
+ #define FALSE 0
+ typedef unsigned char BOOLEAN;
+
+ #define CONST const
+ #define STATIC static
+ #define VOLATILE volatile
+ #define CALLCONV __pascal
+ #define ROMDATA __based( __segname( "_CODE" ) )
+ #define _16BYTE_ALIGN __declspec(align(16))
+ #define _8BYTE_ALIGN
+ #define _4BYTE_ALIGN
+ #define _2BYTE_ALIGN
+ #define _1BYTE_ALIGN
+
+ // Force tight packing of structures
+ // Note: Entire AGESA (Project / Solution) will be using pragma pack 1
+ #pragma warning( disable : 4103 ) // Disable '#pragma pack' in .h warning
+ #pragma pack(1)
+
+ // Disable WORD->BYTE automatic conversion warnings. Example:
+ // BYTE LocalByte;
+ // void MyFunc(BYTE val);
+ //
+ // MyFunc(LocalByte*2+1); // Warning, automatic conversion
+ //
+ // The problem is any time math is performed on a BYTE, it is converted to a
+ // WORD by MSVC 1.52c, and then when it is converted back to a BYTE, a warning
+ // is generated. Disable warning C4761
+ #pragma warning( disable : 4761 )
+
+ #else
+ // -----------------------------------------------------------------------
+ // Assume a 32-bit MSVC++
+ //
+ // Disable the following warnings:
+ // 4100 - 'identifier' : unreferenced formal parameter
+ // 4276 - 'function' : no prototype provided; assumed no parameters
+ // 4214 - non standard extension used : bit field types other than int
+ // 4001 - nonstandard extension 'single line comment' was used
+ // 4142 - benign redefinition of type for following declaration
+ // - typedef char INT8
+ #if defined (_M_IX86)
+ #pragma warning (disable: 4100 4276 4214 4001 4142 4305 4306)
+
+ #ifndef VOID
+ typedef void VOID;
+ #endif
+ // Create the universal 32, 16, and 8-bit data types
+ #ifndef UINTN
+ typedef unsigned __w64 UINTN;
+ #endif
+ typedef __int64 INT64;
+ typedef unsigned __int64 UINT64;
+ typedef int INT32;
+ typedef unsigned int UINT32;
+ typedef short INT16;
+ typedef unsigned short UINT16;
+ typedef char INT8;
+ typedef unsigned char UINT8;
+ typedef char CHAR8;
+ typedef unsigned short CHAR16;
+
+ // Create the Boolean type
+ #ifndef TRUE
+ #define TRUE 1
+ #endif
+ #ifndef FALSE
+ #define FALSE 0
+ #endif
+ typedef unsigned char BOOLEAN;
+
+ // Force tight packing of structures
+ // Note: Entire AGESA (Project / Solution) will be using pragma pack 1
+ #pragma pack(1)
+
+ #define CONST const
+ #define STATIC static
+ #define VOLATILE volatile
+ #define CALLCONV
+ #define ROMDATA
+ #define _16BYTE_ALIGN __declspec(align(64))
+ #define _8BYTE_ALIGN
+ #define _4BYTE_ALIGN
+ #define _2BYTE_ALIGN
+ #define _1BYTE_ALIGN
+ #if _MSC_VER >= 1400
+ #define VA_ARGS_SUPPORTED
+ #endif
+ // 64 bit of compiler
+ #else
+ #pragma warning (disable: 4100 4276 4214 4001 4142 4305 4306 4366)
+
+ #ifndef VOID
+ typedef void VOID;
+ #endif
+ // Create the universal 32, 16, and 8-bit data types
+ #ifndef UINTN
+ typedef unsigned __int64 UINTN;
+ #endif
+ typedef __int64 INT64;
+ typedef unsigned __int64 UINT64;
+ typedef int INT32;
+ typedef unsigned int UINT32;
+ typedef short INT16;
+ typedef unsigned short UINT16;
+ typedef char INT8;
+ typedef unsigned char UINT8;
+ typedef char CHAR8;
+ typedef unsigned short CHAR16;
+
+ // Create the Boolean type
+ #ifndef TRUE
+ #define TRUE 1
+ #endif
+ #ifndef FALSE
+ #define FALSE 0
+ #endif
+ typedef unsigned char BOOLEAN;
+ #define _8BYTE_ALIGN
+ #define _4BYTE_ALIGN
+ #define _2BYTE_ALIGN
+ #define _1BYTE_ALIGN
+ // Force tight packing of structures
+ // Note: Entire AGESA (Project / Solution) will be using pragma pack 1
+ #pragma pack(1)
+
+ #define CONST const
+ #define STATIC static
+ #define VOLATILE volatile
+ #define CALLCONV
+ #define ROMDATA
+ #endif
+ #endif
+ // -----------------------------------------------------------------------
+ // End of MS compiler versions
+
+#elif defined __GNUC__
+
+ #define IN
+ #define OUT
+ #define STATIC static
+ #define VOLATILE volatile
+ #define TRUE 1
+ #define FALSE 0
+// #undef CONST
+ #define CONST const
+ #define ROMDATA
+ #define CALLCONV
+ #define _16BYTE_ALIGN __attribute__ ((aligned (16)))
+ #define _8BYTE_ALIGN __attribute__ ((aligned (8)))
+ #define _4BYTE_ALIGN __attribute__ ((aligned (4)))
+ #define _2BYTE_ALIGN __attribute__ ((aligned (2)))
+ #define _1BYTE_ALIGN __attribute__ ((aligned (1)))
+
+ typedef unsigned char BOOLEAN;
+ typedef signed char INT8;
+ typedef signed short INT16;
+ typedef signed long INT32;
+ typedef signed long long INT64;
+ typedef char CHAR8;
+ typedef unsigned char UINT8;
+ typedef unsigned short UINT16;
+ typedef unsigned long UINT32;
+ typedef unsigned long UINTN;
+ typedef unsigned long long UINT64;
+ typedef void VOID;
+ //typedef unsigned long size_t;
+ //typedef unsigned int uintptr_t;
+ #define CODE_GROUP(arg)
+ #define RDATA_GROUP(arg)
+
+ //#include <intrin.h> // MingW-w64 library header
+ //#include <MyIntrinsics.h> // AGESA temp file for GCC until support is added to MinGW
+
+#pragma pack(1)
+
+#define FUNC_ATTRIBUTE(arg) __attribute__((arg))
+#define MAKE_AS_A_STRING(arg) #arg
+#include <stddef.h>
+#include <gcc-intrin.h>
+
+#include <assert.h>
+#include <console/console.h>
+#include <console/loglevel.h>
+
+#ifndef NULL
+ #define NULL ((void *)0)
+#endif
+
+#else
+ // -----------------------------------------------------------------------
+ // Unknown or unsupported compiler
+ //
+ #error "Unknown compiler in use"
+#endif
+
+// -----------------------------------------------------------------------
+// Common definitions for all compilers
+//
+
+//Support forward reference construct
+#define AGESA_FORWARD_DECLARATION(x) typedef struct _##x x
+
+// The following are use in conformance to the UEFI style guide
+#define IN
+#define OUT
+
+#endif // _PORTING_H_
diff --git a/src/vendorcode/amd/pi/00630F01/Proc/CPU/Family/cpuFamRegisters.h b/src/vendorcode/amd/pi/00630F01/Proc/CPU/Family/cpuFamRegisters.h
new file mode 100644
index 0000000..b93d396
--- /dev/null
+++ b/src/vendorcode/amd/pi/00630F01/Proc/CPU/Family/cpuFamRegisters.h
@@ -0,0 +1,110 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD CPU Register Table Related Functions
+ *
+ * Contains the definition of the CPU CPUID MSRs and PCI registers with BKDG recommended values
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: CPU
+ * @e \$Revision: 281181 $ @e \$Date: 2013-12-18 02:18:55 -0600 (Wed, 18 Dec 2013) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ ******************************************************************************
+ */
+
+#ifndef _CPU_FAM_REGISTERS_H_
+#define _CPU_FAM_REGISTERS_H_
+
+/*
+ *--------------------------------------------------------------
+ *
+ * M O D U L E S U S E D
+ *
+ *---------------------------------------------------------------
+ */
+
+/*
+ *--------------------------------------------------------------
+ *
+ * D E F I N I T I O N S / M A C R O S
+ *
+ *---------------------------------------------------------------
+ */
+
+// This define should be equal to the total number of families
+// in the cpuFamily enum.
+#define MAX_CPU_FAMILIES 64
+#define MAX_CPU_REVISIONS 63 // Max Cpu Revisions Per Family
+
+// CPU_LOGICAL_ID.Family equates
+// Family 15h equates
+#define AMD_FAMILY_15_TN 0x0000000000000200ull
+#define AMD_FAMILY_TN (AMD_FAMILY_15_TN)
+#define AMD_FAMILY_15_RL (AMD_FAMILY_15_TN)
+#define AMD_FAMILY_RL (AMD_FAMILY_15_TN)
+#define AMD_FAMILY_15_KV 0x0000000000000400ull
+#define AMD_FAMILY_KV (AMD_FAMILY_15_KV)
+#define AMD_FAMILY_15 (AMD_FAMILY_15_TN | AMD_FAMILY_15_KV)
+
+// Family Unknown
+#define AMD_FAMILY_UNKNOWN 0x8000000000000000ull
+
+
+// Family 15h CPU_LOGICAL_ID.Revision equates
+// -------------------------------------
+
+ // Family 15h TN steppings
+#define AMD_F15_TN_A0 0x0000000000000100ull
+#define AMD_F15_TN_A1 0x0000000000000200ull
+#define AMD_F15_RL_A1 0x0000000000000400ull
+ // Family 15h KV steppings
+#define AMD_F15_KV_A0 0x0000000000100000ull
+#define AMD_F15_KV_A1 0x0000000000200000ull
+ // Family 15h Unknown stepping
+#define AMD_F15_UNKNOWN 0x8000000000000000ull
+
+#define AMD_F15_RL_Ax (AMD_F15_RL_A1)
+#define AMD_F15_RL_ALL (AMD_F15_RL_Ax)
+
+#define AMD_F15_TN_Ax (AMD_F15_TN_A0 | AMD_F15_TN_A1)
+#define AMD_F15_TN_GT_A0 (AMD_F15_TN_ALL & ~AMD_F15_TN_A0)
+#define AMD_F15_TN_ONLY (AMD_F15_TN_Ax)
+#define AMD_F15_TN_ALL (AMD_F15_TN_Ax | AMD_F15_RL_ALL)
+
+#define AMD_F15_KV_Ax (AMD_F15_KV_A0 | AMD_F15_KV_A1)
+#define AMD_F15_KV_ALL (AMD_F15_KV_Ax)
+
+#define AMD_F15_ALL (AMD_F15_TN_ALL | AMD_F15_KV_ALL)
+
+#endif // _CPU_FAM_REGISTERS_H_
+
diff --git a/src/vendorcode/amd/pi/00630F01/Proc/CPU/Feature/cpuCacheInit.h b/src/vendorcode/amd/pi/00630F01/Proc/CPU/Feature/cpuCacheInit.h
new file mode 100644
index 0000000..f353157
--- /dev/null
+++ b/src/vendorcode/amd/pi/00630F01/Proc/CPU/Feature/cpuCacheInit.h
@@ -0,0 +1,138 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD CPU Execution Cache Allocation functions.
+ *
+ * Contains code for doing Execution Cache Allocation for ROM space
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: CPU
+ * @e \$Revision: 192403 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ ******************************************************************************
+ */
+
+#ifndef _CPU_CACHE_INIT_H_
+#define _CPU_CACHE_INIT_H_
+
+/*----------------------------------------------------------------------------
+ * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*-----------------------------------------------------------------------------
+ * DEFINITIONS AND MACROS
+ *
+ *-----------------------------------------------------------------------------
+ */
+#define BSP_STACK_SIZE_64K 65536
+#define BSP_STACK_SIZE_32K 32768
+
+#define CORE0_STACK_SIZE 16384
+#define CORE1_STACK_SIZE 4096
+
+#define AMD_MTRR_FIX4K_BASE 0x268
+#define AMD_MTRR_VARIABLE_BASE6 0x20C
+#define AMD_MTRR_VARIABLE_BASE7 0x20E
+
+#define WP_IO 0x0505050505050505ull
+
+#define AGESA_CACHE_SIZE_REDUCED 1
+#define AGESA_CACHE_REGIONS_ACROSS_1MB 2
+#define AGESA_CACHE_REGIONS_ACROSS_4GB 3
+#define AGESA_REGION_NOT_ALIGNED_ON_BOUNDARY 4
+#define AGESA_CACHE_START_ADDRESS_LESS_D0000 5
+#define AGESA_THREE_CACHE_REGIONS_ABOVE_1MB 6
+#define AGESA_DEALLOCATE_CACHE_REGIONS 7
+
+/*----------------------------------------------------------------------------
+ * TYPEDEFS, STRUCTURES, ENUMS
+ *
+ *----------------------------------------------------------------------------
+ */
+/// Cache-As-Ram Executable region allocation modes
+typedef enum {
+ LimitedByL2Size, ///< Execution space must be allocated from L2
+ InfiniteExe, ///< Family can support unlimited Execution space
+ MaxCarExeMode ///< Used as limit or bounds check
+} CAR_EXE_MODE;
+
+/// Cache Information
+typedef struct {
+ IN UINT32 BspStackSize; ///< Stack size of BSP
+ IN UINT32 Core0StackSize; ///< Stack size of primary cores
+ IN UINT32 Core1StackSize; ///< Stack size of all non primary cores
+ IN UINT32 MemTrainingBufferSize; ///< Memory training buffer size
+ IN UINT32 SharedMemSize; ///< Shared memory size
+ IN UINT64 VariableMtrrMask; ///< Mask to apply before variable MTRR writes
+ IN UINT64 VariableMtrrHeapMask; ///< Mask to apply before variable MTRR writes for use in heap init.
+ IN UINT64 HeapBaseMask; ///< Mask used for the heap MTRR settings
+ IN CAR_EXE_MODE CarExeType; ///< Indicates which algorithm to use when allocating EXE space
+} CACHE_INFO;
+
+/// Merged memory region overlap type
+typedef enum {
+ EmptySet, ///< One of the regions is zero length
+ Disjoint, ///< The two regions do not touch
+ Adjacent, ///< one region is next to the other, no gap
+ CommonEnd, ///< regions overlap with a common end point
+ Extending, ///< the 2nd region is extending the size of the 1st
+ Contained, ///< the 2nd region is wholely contained inside the 1st
+ CommonStartContained, ///< the 2nd region is contained in the 1st with a common start
+ Identity, ///< the two regions are the same
+ CommonStartExtending, ///< the 2nd region has same start as 1st, but is larger size
+ NotCombinable ///< the combined regions do not follow the cache block rules
+} OVERLAP_TYPE;
+
+/// Result of merging two memory regions for cache coverage
+typedef struct {
+ IN OUT UINT32 MergedStartAddr; ///< Start address of the merged regions
+ IN OUT UINT32 MergedSize; ///< Size of the merged regions
+ OUT UINT32 OverlapAmount; ///< the size of the overlapping section
+ OUT OVERLAP_TYPE OverlapType; ///< indicates how the two regions overlap
+} MERGED_CACHE_REGION;
+
+/*----------------------------------------------------------------------------
+ * FUNCTIONS PROTOTYPE
+ *
+ *----------------------------------------------------------------------------
+ */
+AGESA_STATUS
+AllocateExecutionCache (
+ IN AMD_CONFIG_PARAMS *StdHeader,
+ IN EXECUTION_CACHE_REGION *AmdExeAddrMapPtr
+ );
+
+#endif // _CPU_CACHE_INIT_H_
+
diff --git a/src/vendorcode/amd/pi/00630F01/Proc/CPU/cpuApicUtilities.h b/src/vendorcode/amd/pi/00630F01/Proc/CPU/cpuApicUtilities.h
new file mode 100644
index 0000000..ec4ad28
--- /dev/null
+++ b/src/vendorcode/amd/pi/00630F01/Proc/CPU/cpuApicUtilities.h
@@ -0,0 +1,303 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD CPU APIC related utility functions and structures
+ *
+ * Contains code that provides mechanism to invoke and control APIC communication.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: CPU
+ * @e \$Revision: 281181 $ @e \$Date: 2013-12-18 02:18:55 -0600 (Wed, 18 Dec 2013) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ ******************************************************************************
+ */
+
+#ifndef _CPU_APIC_UTILITIES_H_
+#define _CPU_APIC_UTILITIES_H_
+
+
+/*---------------------------------------------------------------------------------------
+ * M I X E D (Definitions And Macros / Typedefs, Structures, Enums)
+ *---------------------------------------------------------------------------------------
+ */
+
+
+/*---------------------------------------------------------------------------------------
+ * D E F I N I T I O N S A N D M A C R O S
+ *---------------------------------------------------------------------------------------
+ */
+#define APIC_CTRL_DWORD 0xF
+#define APIC_CTRL_REG (APIC_CTRL_DWORD << 4)
+#define APIC_CTRL_MASK 0xFF
+#define APIC_CTRL_SHIFT 0
+
+#define APIC_DATA_DWORD 0x38
+#define APIC_DATA_REG (APIC_DATA_DWORD << 4)
+
+#define APIC_REMOTE_READ_REG 0xC0
+#define APIC_CMD_LO_REG 0x300
+#define APIC_CMD_HI_REG 0x310
+
+// APIC_CMD_LO_REG bits
+#define CMD_REG_DELIVERY_STATUS 0x1000
+#define CMD_REG_TO_READ 0x300
+#define CMD_REG_REMOTE_RD_STS_MSK 0x30000ul
+#define CMD_REG_REMOTE_DELIVERY_PENDING 0x10000ul
+#define CMD_REG_REMOTE_DELIVERY_DONE 0x20000ul
+#define CMD_REG_TO_NMI 0x400
+
+// ExeFlags bits
+#define WAIT_FOR_CORE 0x00000001ul
+#define TASK_HAS_OUTPUT 0x00000002ul
+#define RETURN_PARAMS 0x00000004ul
+#define END_AT_HLT 0x00000008ul
+#define PASS_EARLY_PARAMS 0x00000010ul
+
+// Control Byte Values
+// bit 7 indicates the type of message
+// 1 - control message
+// 0 - launch + APIC ID = message to go
+//
+#define CORE_UNAVAILABLE 0xFF
+#define CORE_IDLE 0xFE
+#define CORE_IDLE_HLT 0xFD
+#define CORE_ACTIVE 0xFC
+#define CORE_NEEDS_PTR 0xFB
+#define CORE_NEEDS_DATA_SIZE 0xFA
+#define CORE_STS_DATA_READY_1 0xF9
+#define CORE_STS_DATA_READY_0 0xF8
+#define CORE_DATA_FLAGS_READY 0xF7
+#define CORE_DATA_FLAGS_ACKNOWLEDGE 0xF6
+#define CORE_DATA_PTR_READY 0xF5
+
+// Macro used to determine the number of dwords to transmit to the AP as input
+#define SIZE_IN_DWORDS(sInput) ((UINT32) (((sizeof (sInput)) + 3) >> 2))
+
+// IDT table
+#define IDT_DESC_PRESENT 0x80
+
+#define IDT_DESC_TYPE_LDT 0x02
+#define IDT_DESC_TYPE_CALL16 0x04
+#define IDT_DESC_TYPE_TASK 0x05
+#define IDT_DESC_TYPE_INT16 0x06
+#define IDT_DESC_TYPE_TRAP16 0x07
+#define IDT_DESC_TYPE_CALL32 0x0C
+#define IDT_DESC_TYPE_INT32 0x0E
+#define IDT_DESC_TYPE_TRAP32 0x0F
+/*---------------------------------------------------------------------------------------
+ * T Y P E D E F S, S T R U C T U R E S, E N U M S
+ *---------------------------------------------------------------------------------------
+ */
+typedef VOID (*PF_AP_TASK) (AMD_CONFIG_PARAMS *StdHeader);
+typedef VOID (*PF_AP_TASK_I) (VOID *, AMD_CONFIG_PARAMS *StdHeader);
+typedef VOID (*PF_AP_TASK_C) (AMD_CONFIG_PARAMS *StdHeader, AMD_CPU_EARLY_PARAMS *);
+typedef VOID (*PF_AP_TASK_IC) (VOID *, AMD_CONFIG_PARAMS *StdHeader, AMD_CPU_EARLY_PARAMS *);
+typedef UINT32 (*PF_AP_TASK_O) (AMD_CONFIG_PARAMS *StdHeader);
+typedef UINT32 (*PF_AP_TASK_IO) (VOID *, AMD_CONFIG_PARAMS *StdHeader);
+typedef UINT32 (*PF_AP_TASK_OC) (AMD_CONFIG_PARAMS *StdHeader, AMD_CPU_EARLY_PARAMS *);
+typedef UINT32 (*PF_AP_TASK_IOC) (VOID *, AMD_CONFIG_PARAMS *StdHeader, AMD_CPU_EARLY_PARAMS *);
+
+/// Function pointer union representing the eight different
+/// types of functions that an AP can be asked to perform.
+typedef union {
+ PF_AP_TASK PfApTask; ///< AMD_CONFIG_PARAMS * input with no output
+ PF_AP_TASK_I PfApTaskI; ///< VOID * + AMD_CONFIG_PARAMS * input with no output
+ PF_AP_TASK_C PfApTaskC; ///< AMD_CONFIG_PARAMS * + AMD_CPU_EARLY_PARAMS * input with no output
+ PF_AP_TASK_IC PfApTaskIC; ///< VOID * + AMD_CONFIG_PARAMS * + AMD_CPU_EARLY_PARAMS * input with no output
+ PF_AP_TASK_O PfApTaskO; ///< AMD_CONFIG_PARAMS * input with UINT32 output
+ PF_AP_TASK_IO PfApTaskIO; ///< VOID * + AMD_CONFIG_PARAMS * input with UINT32 output
+ PF_AP_TASK_OC PfApTaskOC; ///< AMD_CONFIG_PARAMS * + AMD_CPU_EARLY_PARAMS * input with UINT32 output
+ PF_AP_TASK_IOC PfApTaskIOC; ///< VOID * + AMD_CONFIG_PARAMS * + AMD_CPU_EARLY_PARAMS * input with UINT32 output
+} AP_FUNCTION_PTR;
+
+/// Input structure for ApUtilTransmitBuffer and ApUtilReceiveBuffer
+/// containing information about the data transfer from one core
+/// to another.
+typedef struct {
+ IN OUT UINT16 DataSizeInDwords; ///< Size of the data to be transferred rounded up to the nearest dword
+ IN OUT VOID *DataPtr; ///< Pointer to the data
+ IN UINT32 DataTransferFlags; ///< Flags dictating certain aspects of the data transfer
+} AP_DATA_TRANSFER;
+
+/// Input structure for ApUtilRunCodeOnSocketCore.
+typedef struct _AP_TASK {
+ AP_FUNCTION_PTR FuncAddress; ///< Pointer to the function that the AP will run
+ AP_DATA_TRANSFER DataTransfer; ///< Data transfer struct for optionally passing data that the AP should use as input to the function
+ UINT32 ExeFlags; ///< Flags dictating certain aspects of the AP tasking sequence
+} AP_TASK;
+
+/// Input structure for ApUtilWaitForCoreStatus.
+typedef struct {
+ IN UINT8 *Status; ///< Pointer to the 1st element of an array of values to wait for
+ IN UINT8 NumberOfElements; ///< Number of elements in the array
+ IN UINT32 RetryCount; ///< Number of remote read cycles to complete before quitting
+ IN UINT32 WaitForStatusFlags; ///< Flags dictating certain aspects of ApUtilWaitForCoreStatus
+} AP_WAIT_FOR_STATUS;
+
+/// Interrupt Descriptor Table entry
+typedef struct {
+ UINT16 OffsetLo; ///< Lower 16 bits of the interrupt handler routine's offset
+ UINT16 Selector; ///< Interrupt handler routine's selector
+ UINT8 Rsvd; ///< Reserved
+ UINT8 Flags; ///< Interrupt flags
+ UINT16 OffsetHi; ///< Upper 16 bits of the interrupt handler routine's offset
+ UINT32 Offset64; ///< High order 32 bits of the handler's offset needed when in 64 bit mode
+ UINT32 Rsvd64; ///< Reserved
+} IDT_DESCRIPTOR;
+
+/// Structure needed to load the IDTR using the lidt instruction
+typedef struct {
+ UINT16 Limit; ///< Interrupt Descriptor Table size
+ UINT64 Base; ///< Interrupt Descriptor Table base address
+} IDT_BASE_LIMIT;
+
+#define WAIT_STATUS_EQUALITY 0x00000001ul
+#define WAIT_INFINITELY 0
+
+// Data Transfer Flags
+#define DATA_IN_MEMORY 0x00000001ul
+
+
+/*---------------------------------------------------------------------------------------
+ * F U N C T I O N P R O T O T Y P E
+ *---------------------------------------------------------------------------------------
+ */
+// These are P U B L I C functions, used by AGESA
+UINT8
+ApUtilReadRemoteControlByte (
+ IN UINT32 TargetApicId,
+ IN AMD_CONFIG_PARAMS *StdHeader
+ );
+
+VOID
+ApUtilWriteControlByte (
+ IN UINT8 Value,
+ IN AMD_CONFIG_PARAMS *StdHeader
+ );
+
+UINT32
+ApUtilReadRemoteDataDword (
+ IN UINT32 TargetApicId,
+ IN AMD_CONFIG_PARAMS *StdHeader
+ );
+
+VOID
+ApUtilWriteDataDword (
+ IN UINT32 Value,
+ IN AMD_CONFIG_PARAMS *StdHeader
+ );
+
+UINT32
+ApUtilRunCodeOnSocketCore (
+ IN UINT8 Socket,
+ IN UINT8 Core,
+ IN AP_TASK *TaskPtr,
+ IN AMD_CONFIG_PARAMS *StdHeader
+ );
+
+UINT8
+ApUtilWaitForCoreStatus (
+ IN UINT32 TargetApicId,
+ IN AP_WAIT_FOR_STATUS *WaitParamsPtr,
+ IN AMD_CONFIG_PARAMS *StdHeader
+ );
+
+VOID
+ApEntry (
+ IN AMD_CONFIG_PARAMS *StdHeader,
+ IN AMD_CPU_EARLY_PARAMS *CpuEarlyParams
+ );
+
+UINT32
+ApUtilTaskOnExecutingCore (
+ IN AP_TASK *TaskPtr,
+ IN AMD_CONFIG_PARAMS *StdHeader,
+ IN VOID *ConfigParams
+ );
+
+VOID
+ApUtilTransmitBuffer (
+ IN UINT8 Socket,
+ IN UINT8 Core,
+ IN AP_DATA_TRANSFER *BufferInfo,
+ IN AMD_CONFIG_PARAMS *StdHeader
+ );
+
+AGESA_STATUS
+ApUtilReceiveBuffer (
+ IN UINT8 Socket,
+ IN UINT8 Core,
+ IN OUT AP_DATA_TRANSFER *BufferInfo,
+ IN AMD_CONFIG_PARAMS *StdHeader
+ );
+
+VOID
+GetLocalApicIdForCore (
+ IN UINT32 TargetSocket,
+ IN UINT32 TargetCore,
+ OUT UINT32 *LocalApicId,
+ IN AMD_CONFIG_PARAMS *StdHeader
+ );
+
+VOID
+ApUtilRunCodeOnAllLocalCoresAtEarly (
+ IN AP_TASK *TaskPtr,
+ IN AMD_CONFIG_PARAMS *StdHeader,
+ IN AMD_CPU_EARLY_PARAMS *CpuEarlyParamsPtr
+ );
+
+VOID
+RelinquishControlOfAllAPs (
+ IN AMD_CONFIG_PARAMS *StdHeader
+ );
+
+VOID
+GetCsSelector (
+ IN UINT16 *Selector,
+ IN AMD_CONFIG_PARAMS *StdHeader
+ );
+
+VOID
+SetIdtr (
+ IN IDT_BASE_LIMIT *IdtInfo,
+ IN AMD_CONFIG_PARAMS *StdHeader
+ );
+
+VOID
+GetIdtr (
+ IN IDT_BASE_LIMIT *IdtInfo,
+ IN AMD_CONFIG_PARAMS *StdHeader
+ );
+
+#endif /* _CPU_APIC_UTILITIES_H_ */
+
diff --git a/src/vendorcode/amd/pi/00630F01/Proc/CPU/cpuEarlyInit.h b/src/vendorcode/amd/pi/00630F01/Proc/CPU/cpuEarlyInit.h
new file mode 100644
index 0000000..6512a21
--- /dev/null
+++ b/src/vendorcode/amd/pi/00630F01/Proc/CPU/cpuEarlyInit.h
@@ -0,0 +1,290 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD CPU Reset API, and related functions and structures.
+ *
+ * Contains code that initialized the CPU after early reset.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: CPU
+ * @e \$Revision: 281181 $ @e \$Date: 2013-12-18 02:18:55 -0600 (Wed, 18 Dec 2013) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ ******************************************************************************
+ */
+
+#ifndef _CPU_EARLY_INIT_H_
+#define _CPU_EARLY_INIT_H_
+
+
+/*---------------------------------------------------------------------------------------
+ * M I X E D (Definitions And Macros / Typedefs, Structures, Enums)
+ *---------------------------------------------------------------------------------------
+ */
+AGESA_FORWARD_DECLARATION (CPU_CORE_LEVELING_FAMILY_SERVICES);
+
+/*---------------------------------------------------------------------------------------
+ * D E F I N I T I O N S A N D M A C R O S
+ *---------------------------------------------------------------------------------------
+ */
+//----------------------------------------------------------------------------
+// CPU BRAND ID TYPEDEFS, STRUCTURES, ENUMS
+//
+//----------------------------------------------------------------------------
+#define CPU_BRAND_ID_LENGTH 48 // Total number of characters supported
+#define LOW_NODE_DEVICEID 24
+#define NB_CAPABILITIES 0xE8 //Function 3 Registers
+//----------------------------------------------------------------------------
+// CPU MICROCODE PATCH TYPEDEFS, STRUCTURES, ENUMS
+//
+//----------------------------------------------------------------------------
+/* All lengths are in bytes */
+#define MICROCODE_TRIADE_SIZE 28
+#define MICROCODE_HEADER_LENGTH 64
+
+/**
+ * @page ucodeflag Microcode Patches Signature Guide
+ *
+ * We mark patches in the ROM with a signature so that they can be easily found
+ *
+ * @anchor Microcode Patch Signature
+ * @li @e Microcode Patch Signature @n
+ * Microcode patches are marked by adding a signature before patches in the ROM image to
+ * help identify where they are located.
+ * There're two kind of signatures. One is '$UCODE2K', it indicates there's a following patch with 2K size.
+ * The other is '$UCODE4K', it indicates there's a following patch with 4K size.
+ * If you want to know the patch level / equivalent ID, please consult the BKDG for patch header format.
+ *
+ *
+ */
+/// Microcode patch flag for replacement
+typedef struct {
+ IN UINT8 MicrocodePatchesFlag[8]; ///< a flag followed by microcode
+} MICROCODE_PATCHES_FLAG;
+
+#define UCODE_2K_FLAG(x) STATIC CONST MICROCODE_PATCHES_FLAG ROMDATA UcodeFlag##x = {{'$', 'U', 'C', 'O', 'D', 'E', '2', 'K'}};
+#define UCODE_4K_FLAG(x) STATIC CONST MICROCODE_PATCHES_FLAG ROMDATA UcodeFlag##x = {{'$', 'U', 'C', 'O', 'D', 'E', '4', 'K'}};
+#define UCODE_VS_FLAG(x) STATIC CONST MICROCODE_PATCHES_FLAG ROMDATA UcodeFlag##x = {{'$', 'U', 'C', 'O', 'D', 'E', 'V', 'S'}};
+
+/* Offsets in UCODE PATCH Header */
+/* Note: Header is 64 bytes */
+#define DATE_CODE_OFFSET 0 // 4 bytes
+#define PATCH_ID 4 // 4 bytes
+#define MICROCODE_PATH_DATA_ID 8 // 2 bytes
+#define MICROCODE_PATCH_DATA_LENGTH 10 // 1 byte
+#define MICROCODE_PATCH_DATA_CHECKSUM 12 // 4 bytes
+#define CHIPSET_1_DEVICE_ID 16 // 4 bytes
+#define CHIPSET_2_DEVICE_ID 20 // 4 bytes
+#define PROCESSOR_REV_ID 24 // 2 bytes
+#define CHIPSET_1_REV_ID 26 // 1 byte
+#define CHIPSET_2_REV_ID 27 // 1 byte
+
+#define MICROCODE_PATCH_2K_SIZE 2048
+#define MICROCODE_PATCH_4K_SIZE 4096
+/*---------------------------------------------------------------------------------------
+ * T Y P E D E F S, S T R U C T U R E S, E N U M S
+ *---------------------------------------------------------------------------------------
+ */
+//----------------------------------------------------------------------------
+// CPU BRAND ID TYPEDEFS, STRUCTURES, ENUMS
+//
+//----------------------------------------------------------------------------
+/// A structure representing BrandId[15:0] from
+/// CPUID Fn8000_0001_EBX
+typedef struct {
+ UINT8 String1:4; ///< An index to a string value used to create the name string
+ UINT8 String2:4; ///< An index to a string value used to create the name string
+ UINT8 Page:1; ///< An index to the appropriate page for the String1, String2, and Model values
+ UINT8 Model:7; ///< A field used to create the model number in the name string
+ UINT8 Socket:4; ///< Specifies the package type
+ UINT8 Cores:4; ///< Identifies how many physical cores are present
+} AMD_CPU_BRAND_DATA;
+
+/// A structure containing string1 and string2 values
+/// as well as information pertaining to their usage
+typedef struct {
+ IN UINT8 Cores; ///< Appropriate number of physical cores
+ IN UINT8 Page; ///< This string's page number
+ IN UINT8 Index; ///< String index
+ IN UINT8 Socket; ///< Package type information
+ IN CONST CHAR8 *Stringstart; ///< The literal string
+ IN UINT8 Stringlength; ///< Number of characters in the string
+} AMD_CPU_BRAND;
+
+/// An entire CPU brand table.
+typedef struct {
+ UINT8 NumberOfEntries; ///< The number of entries in the table.
+ CONST AMD_CPU_BRAND *Table; ///< The table entries.
+} CPU_BRAND_TABLE;
+
+//----------------------------------------------------------------------------
+// CPU MICROCODE PATCH TYPEDEFS, STRUCTURES, ENUMS
+//
+//----------------------------------------------------------------------------
+/// Microcode patch field definitions
+typedef struct {
+ UINT32 DateCode; ///< Date of patch creation
+ UINT32 PatchID; ///< Patch level
+ UINT16 MicrocodePatchDataID; ///< Internal use only
+ UINT8 MicrocodePatchDataLength; ///< Internal use only
+ UINT8 InitializationFlag; ///< Internal use only
+ UINT32 MicrocodePatchDataChecksum; ///< Doubleword sum of data block
+ UINT32 Chipset1DeviceID; ///< Device ID of 1st Chipset device to match
+ UINT32 Chipset2DeviceID; ///< Device ID of 2nd Chipset device to match
+ UINT16 ProcessorRevisionID; ///< Equivalent ID
+ UINT8 Chipset1RevisionID; ///< Revision level of 1st Chipset device to match
+ UINT8 Chipset2RevisionID; ///< Revision level of 2nd Chipset device to match
+ UINT8 BiosApiRevision; ///< BIOS INT 15 API revision required
+ UINT8 Reserved1[3]; ///< Reserved
+ UINT32 MatchRegister0; ///< Internal use only
+ UINT32 MatchRegister1; ///< Internal use only
+ UINT32 MatchRegister2; ///< Internal use only
+ UINT32 MatchRegister3; ///< Internal use only
+ UINT32 MatchRegister4; ///< Internal use only
+ UINT32 MatchRegister5; ///< Internal use only
+ UINT32 MatchRegister6; ///< Internal use only
+ UINT32 MatchRegister7; ///< Internal use only
+ UINT8 PatchDataBlock[896]; ///< Raw patch data
+ UINT8 Reserved2[896]; ///< Reserved
+ UINT8 X86CodePresent; ///< Boolean to determine if executable code exists
+ UINT8 X86CodeEntry[191]; ///< Code to execute if X86CodePresent != 0
+} MICROCODE_PATCH;
+
+/// Two kilobyte array containing the raw
+/// microcode patch binary data
+typedef struct {
+ IN UINT8 MicrocodePatches[MICROCODE_PATCH_2K_SIZE]; ///< 2k UINT8 elements
+} MICROCODE_PATCHES;
+
+/// Four kilobyte array containing the raw
+/// microcode patch binary data
+typedef struct {
+ IN UINT8 MicrocodePatches[MICROCODE_PATCH_4K_SIZE]; ///< 4k UINT8 elements
+} MICROCODE_PATCHES_4K;
+
+/**
+ * Set down core register
+ *
+ * @CpuServiceInstances
+ *
+ * @param[in] FamilySpecificServices The current Family Specific Services.
+ * @param[in] Socket Socket ID.
+ * @param[in] Module Module ID in socket.
+ * @param[in] LeveledCores Number of core.
+ * @param[in] CoreLevelMode Core level mode.
+ * @param[in] StdHeader Header for library and services.
+ *
+ * @retval TRUE Down Core register is updated.
+ * @retval FALSE Down Core register is not updated.
+ */
+typedef BOOLEAN (F_CPU_SET_DOWN_CORE_REGISTER) (
+ IN CPU_CORE_LEVELING_FAMILY_SERVICES *FamilySpecificServices,
+ IN UINT32 *Socket,
+ IN UINT32 *Module,
+ IN UINT32 *LeveledCores,
+ IN CORE_LEVELING_TYPE CoreLevelMode,
+ IN AMD_CONFIG_PARAMS *StdHeader
+ );
+
+/// Reference to a method
+typedef F_CPU_SET_DOWN_CORE_REGISTER *PF_CPU_SET_DOWN_CORE_REGISTER;
+
+/**
+ * Provide the interface to the Core Leveling Family Specific Services.
+ *
+ * Use the methods or data in this struct to adapt the feature code to a specific cpu family or model (or stepping!).
+ * Each supported Family must provide an implementation for all methods in this interface, even if the
+ * implementation is a CommonReturn().
+ */
+struct _CPU_CORE_LEVELING_FAMILY_SERVICES { // See Forward Declaration above
+ UINT16 Revision; ///< Interface version
+ // Public Methods.
+ PF_CPU_SET_DOWN_CORE_REGISTER SetDownCoreRegister; ///< Method: Set down core register.
+};
+
+/*---------------------------------------------------------------------------------------
+ * F U N C T I O N P R O T O T Y P E
+ *---------------------------------------------------------------------------------------
+ */
+
+// These are P U B L I C functions, used by IBVs
+AGESA_STATUS
+AmdCpuEarly (
+ IN AMD_CONFIG_PARAMS *StdHeader,
+ IN PLATFORM_CONFIGURATION *PlatformConfig
+ );
+
+// These are P U B L I C functions, used by AGESA
+AGESA_STATUS
+PmInitializationAtEarly (
+ IN AMD_CPU_EARLY_PARAMS *CpuEarlyParams,
+ IN AMD_CONFIG_PARAMS *StdHeader
+ );
+
+BOOLEAN
+LoadMicrocodePatch (
+ IN OUT AMD_CONFIG_PARAMS *StdHeader
+ );
+
+BOOLEAN
+GetPatchEquivalentId (
+ IN OUT UINT16 *ProcessorEquivalentId,
+ IN OUT AMD_CONFIG_PARAMS *StdHeader
+ );
+
+BOOLEAN
+ValidateMicrocode (
+ IN MICROCODE_PATCH *MicrocodePatchPtr,
+ IN UINT16 ProcessorEquivalentId,
+ IN OUT AMD_CONFIG_PARAMS *StdHeader
+ );
+
+VOID
+GetMicrocodeVersion (
+ OUT UINT32 *pMicrocodeVersion,
+ IN OUT AMD_CONFIG_PARAMS *StdHeader
+ );
+
+VOID
+AmdCpuEarlyInitializer (
+ IN AMD_CONFIG_PARAMS *StdHeader,
+ IN PLATFORM_CONFIGURATION *PlatformConfig,
+ IN OUT AMD_CPU_EARLY_PARAMS *CpuEarlyParamsPtr
+ );
+
+VOID
+McaInitialization (
+ IN AMD_CONFIG_PARAMS *StdHeader
+ );
+
+#endif // _CPU_EARLY_INIT_H_
+
diff --git a/src/vendorcode/amd/pi/00630F01/Proc/CPU/cpuLateInit.h b/src/vendorcode/amd/pi/00630F01/Proc/CPU/cpuLateInit.h
new file mode 100644
index 0000000..844b343
--- /dev/null
+++ b/src/vendorcode/amd/pi/00630F01/Proc/CPU/cpuLateInit.h
@@ -0,0 +1,1141 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD CPU Late Init API functions Prototypes.
+ *
+ * Contains code for doing any late CPU initialization
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: CPU
+ * @e \$Revision: 281181 $ @e \$Date: 2013-12-18 02:18:55 -0600 (Wed, 18 Dec 2013) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ ******************************************************************************
+ */
+
+#ifndef _CPU_LATE_INIT_H_
+#define _CPU_LATE_INIT_H_
+
+#include "Filecode.h"
+
+// Forward declaration needed for multi-structure mutual references.
+AGESA_FORWARD_DECLARATION (PROC_FAMILY_TABLE);
+/*----------------------------------------------------------------------------------------
+ * M I X E D (Definitions And Macros / Typedefs, Structures, Enums)
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ * D E F I N I T I O N S A N D M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+//----------------------------------------------------------------------------
+// DMI DEFINITIONS AND MACROS
+//
+//----------------------------------------------------------------------------
+#define AP_LATE_TASK_GET_TYPE4_TYPE7 (PROC_CPU_FEATURE_CPUDMI_FILECODE)
+// SMBIOS constant definition
+#define CENTRAL_PROCESSOR 0x03
+#define EXTERNAL_CLOCK_DFLT 200
+#define EXTERNAL_CLOCK_100MHZ 100
+#define P_FAMILY_UNKNOWN 0x02
+#define P_ENGINEERING_SAMPLE 0x00
+#define P_CHARACTERISTICS 0x4
+#define CACHE_CFG_L1 0x180
+#define CACHE_CFG_L2 0x181
+#define CACHE_CFG_L3 0x182
+#define SRAM_TYPE 0x10
+#define ERR_CORRECT_TYPE 0x06
+#define CACHE_TYPE 0x05
+#define DMI_ASSOCIATIVE_OTHER 0x01
+#define DMI_ASSOCIATIVE_UNKNOWN 0x02
+#define DMI_ASSOCIATIVE_DIRECT_MAPPED 0x03
+#define DMI_ASSOCIATIVE_2_WAY 0x04
+#define DMI_ASSOCIATIVE_4_WAY 0x05
+#define DMI_ASSOCIATIVE_FULLY 0x06
+#define DMI_ASSOCIATIVE_8_WAY 0x07
+#define DMI_ASSOCIATIVE_16_WAY 0x08
+#define DMI_ASSOCIATIVE_12_WAY 0x09
+#define DMI_ASSOCIATIVE_24_WAY 0x0A
+#define DMI_ASSOCIATIVE_32_WAY 0x0B
+#define DMI_ASSOCIATIVE_48_WAY 0x0C
+#define DMI_ASSOCIATIVE_64_WAY 0x0D
+#define DMI_ASSOCIATIVE_20_WAY 0x0E
+#define SOCKET_POPULATED 0x40
+#define CPU_STATUS_UNKNOWN 0x00
+#define CPU_STATUS_ENABLED 0x01
+
+// Processor Upgrade Definition
+#define P_UPGRADE_UNKNOWN 0x02
+#define P_UPGRADE_NONE 0x06
+#define P_UPGRADE_S1GX 0x16
+#define P_UPGRADE_AM2 0x17
+#define P_UPGRADE_F1207 0x18
+#define P_UPGRADE_G34 0x1A
+#define P_UPGRADE_AM3 0x1B
+#define P_UPGRADE_C32 0x1C
+#define P_UPGRADE_FS1 0x27
+#define P_UPGRADE_FM1 0x29
+#define P_UPGRADE_FM2 0x2A
+
+//----------------------------------------------------------------------------
+// SRAT DEFINITIONS AND MACROS
+//
+//----------------------------------------------------------------------------
+#define NorthbridgeCapabilities 0xE8
+#define DRAMBase0 0x40
+#define MMIOBase0 0x80
+#define TOP_MEM 0xC001001Aul
+#define LOW_NODE_DEVICEID 24
+#define LOW_APICID 0
+
+
+// Miscellaneous AMD related values
+#define MAX_NUMBER_NODES 8
+
+// Flags
+#define ENABLED 1 // Bit 0
+#define DISABLED 0 // Bit 0
+#define HOTPLUGGABLE 2 // Bit 1
+
+// Affinity Entry Structures
+#define AE_APIC 0
+#define AE_MEMORY 1
+
+
+// Memory Types
+#define TYPE_MEMORY 1
+#define TYPE_RESERVED 2
+#define TYPE_ACPI 3
+#define TYPE_NVS 4
+
+//----------------------------------------------------------------------------
+// SLIT DEFINITIONS AND MACROS
+//
+//----------------------------------------------------------------------------
+#define AMD_ACPI_SLIT_SOCKET_NUM_LENGTH 8
+
+//----------------------------------------------------------------------------
+// CDIT DEFINITIONS AND MACROS
+//
+//----------------------------------------------------------------------------
+#define AMD_ACPI_CDIT_NUM_DOMAINS_LENGTH 4 // Num domains is a 4-bytes unsigned integer
+
+
+//----------------------------------------------------------------------------
+// P-STATE DEFINITIONS AND MACROS
+//
+//----------------------------------------------------------------------------
+//-------------------------------------
+// ERROR Codes
+//-------------------------------------
+#define NO_ERROR 0x0
+#define USER_DISABLE_ERROR 0x01 // User disabled SSDT generation
+#define CORES_MISSMATCH_PSS_ERROR 0x02 // No PSS match
+#define PNOW_SUPPORT_ERROR 0x04 // One of the Cores do not support PNOW!
+#define PWR_FREQ_MATCH_ERROR 0x08 // FREQ and PWR mismatch
+#define NO_PSS_SIZE_ERROR 0x10 // Error in PSS Size
+#define INVALID_PSTATE_ERROR 0x20 // Invalid Max or only 1 P-State available
+#define NO_PSS_ENTRY 0x0FFFFul
+#define INVALID_FREQ 0x0FFFFFFFFul
+
+//-------------------------
+// Default definitions
+// AMD BKDG default values
+//-------------------------
+#define DEFAULT_ISOCH_RELIEF_TIME IRT_80uS
+#define DEFAULT_RAMP_VOLTAGE_OFFSET RVO_50mV
+#define DEFAULT_MAX_VOLTAGE_STEP MVS_25mV
+#define DEFAULT_PERF_PRESENT_CAP 0 // default for Desktop
+#define DEFAULT_VOLTAGE_STABLE_TIME (100 / 20) // 100uS
+#define DEFAULT_PLL_LOCK_TIME 2 // 2uS
+#define DEFAULT_TRANSITION_LATENCY 100 // 100uS
+#define DEFAULT_BUS_MASTER_LATENCY 9 // 9uS
+#define DEFAULT_CPU_SCOPE_NUMBER "0UPC"
+
+// Defines for Common ACPI
+// -----------------------------
+#define SCOPE_OPCODE 0x10
+#define NAME_OPCODE 0x08
+#define METHOD_OPCODE 0x14
+#define PACKAGE_OPCODE 0x12
+#define BUFFER_OPCODE 0x11
+#define BYTE_PREFIX_OPCODE 0x0A
+#define WORD_PREFIX_OPCODE 0x0B
+#define DWORD_PREFIX_OPCODE 0x0C
+#define RETURN_OPCODE 0xA4
+#define ACPI_BUFFER 0x080A0B11ul
+
+// Generic Register Descriptor (GDR) Fields
+#define GDR_ASI_SYSTEM_IO 0x01 // Address Space ID
+#define GDR_ASZ_BYTE_ACCESS 0x01 // Address Size
+
+// Defines for ACPI Scope Table
+// ----------------------------
+#define SCOPE_LENGTH (SCOPE_STRUCT_SIZE + \
+ PCT_STRUCT_SIZE + \
+ PSS_HEADER_STRUCT_SIZE + \
+ PSS_BODY_STRUCT_SIZE + \
+ PPC_HEADER_BODY_STRUCT_SIZE)
+#define SCOPE_VALUE1 0x5C
+#define SCOPE_VALUE2 0x2E
+#define SCOPE_NAME__ '_'
+#define SCOPE_NAME_P 'P'
+#define SCOPE_NAME_R 'R'
+#define SCOPE_NAME_S 'S'
+#define SCOPE_NAME_B 'B'
+#define SCOPE_NAME_C 'C'
+#define SCOPE_NAME_U 'U'
+#define SCOPE_NAME_0 '0'
+#define SCOPE_NAME_1 '1'
+#define SCOPE_NAME_2 '2'
+#define SCOPE_NAME_3 '3'
+#define SCOPE_NAME_A 'A'
+
+#ifdef OEM_SCOPE_NAME
+ #if (OEM_SCOPE_NAME > 'Z') || (OEM_SCOPE_NAME < 'A')
+ #error "OEM_SCOPE_NAME: it should be only one char long AND a valid letter (A~Z)"
+ #endif
+ #define SCOPE_NAME_VALUE OEM_SCOPE_NAME
+#else
+ #define SCOPE_NAME_VALUE SCOPE_NAME_C
+#endif // OEM_SCOPE_NAME
+
+#ifdef OEM_SCOPE_NAME1
+ #if (!(((OEM_SCOPE_NAME1 >= 'A') && (OEM_SCOPE_NAME1 <= 'Z')) || \
+ ((OEM_SCOPE_NAME1 >= '0') && (OEM_SCOPE_NAME1 <= '9')) || \
+ (OEM_SCOPE_NAME1 == '_')))
+ #error "OEM_SCOPE_NAME1: it should be only one char long AND a valid letter (0~9, A~F)"
+ #endif
+ #define SCOPE_NAME_VALUE1 OEM_SCOPE_NAME1
+#else
+ #define SCOPE_NAME_VALUE1 SCOPE_NAME_0
+#endif // OEM_SCOPE_NAME
+
+// Defines for PCT Control and Status Table
+// ----------------------------------------
+#define PCT_NAME__ '_'
+#define PCT_NAME_P 'P'
+#define PCT_NAME_C 'C'
+#define PCT_NAME_T 'T'
+#define PCT_VALUE1 0x11022C12ul
+#define PCT_VALUE2 0x0A14
+#define PCT_VALUE3 0x11
+#define GENERIC_REG_DESCRIPTION 0x82
+#define PCT_LENGTH 0x0C
+#define PCT_ADDRESS_SPACE_ID 0x7F
+#define PCT_REGISTER_BIT_WIDTH 0x40
+#define PCT_REGISTER_BIT_OFFSET 0x00
+#define PCT_RESERVED 0x00
+#define PCT_CONTROL_REG_LO 0xC0010062ul
+#define PCT_CONTROL_REG_HI 0x00
+#define PCT_VALUE4 0x14110079ul
+#define PCT_VALUE5 0x110A
+#define PCT_STATUS_REG_LO 0x00
+#define PCT_STATUS_REG_HI 0x00
+#define PCT_VALUE6 0x0079
+
+
+// Defines for PSS Header Table
+// ----------------------------
+#define PSS_NAME__ '_'
+#define PSS_NAME_X 'X'
+#define PSS_NAME_P 'P'
+#define PSS_NAME_S 'S'
+#define PSS_LENGTH (sizeof pssBodyStruct + 3)
+#define NUM_OF_ITEMS_IN_PSS 0x00
+
+
+// Defines for PSS Header Table
+// ----------------------------
+#define PSS_PKG_LENGTH 0x20 // PSS_BODY_STRUCT_SIZE - 1
+#define PSS_NUM_OF_ELEMENTS 0x06
+#define PSS_FREQUENCY 0x00
+#define PSS_POWER 0x00
+#define PSS_TRANSITION_LATENCY DEFAULT_TRANSITION_LATENCY
+#define PSS_BUS_MASTER_LATENCY DEFAULT_BUS_MASTER_LATENCY
+#define PSS_CONTROL ((DEFAULT_ISOCH_RELIEF_TIME << 30) + \
+ (DEFAULT_RAMP_VOLTAGE_OFFSET << 28) + \
+ (DEFAULT_EXT_TYPE << 27) + \
+ (DEFAULT_PLL_LOCK_TIME << 20) + \
+ (DEFAULT_MAX_VOLTAGE_STEP << 18) + \
+ (DEFAULT_VOLTAGE_STABLE_TIME << 11) + \
+ (PSS_VID << 6) + PSS_FID)
+#define PSS_STATUS (DEFAULT_EXTENDED_TYPE << 11) + (PSS_VID << 6) + (PSS_FID)
+
+// Defines for XPSS Header Table
+// ----------------------------
+#define XPSS_PKG_LENGTH 0x47 // XPSS_BODY_STRUCT_SIZE - 1
+#define XPSS_NUM_OF_ELEMENTS 0x08
+#define XPSS_ACPI_BUFFER 0x080A0B11ul
+
+
+// Defines for PPC Header Table
+// ----------------------------
+#define PPC_NAME__ '_'
+#define PPC_NAME_P 'P'
+#define PPC_NAME_C 'C'
+#define PPC_NAME_V 'V'
+#define PPC_METHOD_FLAGS 0x00;
+#define PPC_VALUE1 0x0A;
+
+// Defines for PSD Header Table
+// ----------------------------
+#define PSD_NAME__ '_'
+#define PSD_NAME_P 'P'
+#define PSD_NAME_S 'S'
+#define PSD_NAME_D 'D'
+#define PSD_HEADER_LENGTH (PSD_BODY_STRUCT_SIZE + 2)
+#define PSD_VALUE1 0x01
+
+
+// Defines for PSD Header Table
+// ----------------------------
+#define PSD_PKG_LENGTH (PSD_BODY_STRUCT_SIZE - 1)
+#define NUM_OF_ENTRIES 0x05
+#define PSD_NUM_OF_ENTRIES 0x05
+#define PSD_REVISION 0x00
+#define PSD_DEPENDENCY_DOMAIN 0x00
+#define PSD_COORDINATION_TYPE_HW_ALL 0xFE
+#define PSD_COORDINATION_TYPE_SW_ANY 0xFD
+#define PSD_COORDINATION_TYPE_SW_ALL 0xFC
+#define PSD_NUM_OF_PROCESSORS 0x01
+#define PSD_TWO_CORES_PER_COMPUTE_UNIT 0x02
+#define PSD_THREE_CORES_PER_COMPUTE_UNIT 0x03
+#define PSD_FOUR_CORES_PER_COMPUTE_UNIT 0x04
+
+
+#define CUSTOM_PSTATE_FLAG 0x55
+#define PSTATE_FLAG_1 0x55
+#define TARGET_PSTATE_FLAG 0xAA
+#define PSTATE_FLAG_2 0xAA
+
+/*----------------------------------------------------------------------------------------
+ * T Y P E D E F S, S T R U C T U R E S, E N U M S
+ *----------------------------------------------------------------------------------------
+ */
+//----------------------------------------------------------------------------
+// ACPI P-States AML TYPEDEFS, STRUCTURES, ENUMS
+//
+//----------------------------------------------------------------------------
+
+//--------------------------------------------
+// AML code definition
+// (Scope)
+//---------------------------------------------
+/// SCOPE
+typedef struct _SCOPE {
+ UINT8 ScopeOpcode; ///< Opcode
+ UINT16 ScopeLength; ///< Scope Length
+ UINT8 ScopeValue1; ///< Value1
+ UINT8 ScopeValue2; ///< Value2
+ UINT8 ScopeNamePt1a__; ///< Name Pointer
+ UINT8 ScopeNamePt1a_P; ///< Name Pointer
+ UINT8 ScopeNamePt1a_R; ///< Name Pointer
+ UINT8 ScopeNamePt1b__; ///< Name Pointer
+ UINT8 ScopeNamePt2a_C; ///< Name Pointer
+ UINT8 ScopeNamePt2a_P; ///< Name Pointer
+ UINT8 ScopeNamePt2a_U; ///< Name Pointer
+ UINT8 ScopeNamePt2a_0; ///< Name Pointer
+} SCOPE;
+#define SCOPE_STRUCT_SIZE 13 // 13 Bytes
+
+//--------------------------------------------
+// AML code definition
+// (PCT Header and Body)
+//---------------------------------------------
+
+///Performance Control Header
+typedef struct _PCT_HEADER_BODY {
+ UINT8 NameOpcode; ///< Opcode
+ UINT8 PctName_a__; ///< String "_"
+ UINT8 PctName_a_P; ///< String "P"
+ UINT8 PctName_a_C; ///< String "C"
+ UINT8 PctName_a_T; ///< String "T"
+ UINT32 Value1; ///< Value1
+ UINT16 Value2; ///< Value2
+ UINT8 Value3; ///< Value3
+ UINT8 GenericRegDescription1; ///< Generic Reg Description
+ UINT16 Length1; ///< Length1
+ UINT8 AddressSpaceId1; ///< PCT Address Space ID
+ UINT8 RegisterBitWidth1; ///< PCT Register Bit Width
+ UINT8 RegisterBitOffset1; ///< PCT Register Bit Offset
+ UINT8 Reserved1; ///< Reserved
+ UINT32 ControlRegAddressLo; ///< Control Register Address Low
+ UINT32 ControlRegAddressHi; ///< Control Register Address High
+ UINT32 Value4; ///< Value4
+ UINT16 Value5; ///< Value 5
+ UINT8 GenericRegDescription2; ///< Generic Reg Description
+ UINT16 Length2; ///< Length2
+ UINT8 AddressSpaceId2; ///< PCT Address Space ID
+ UINT8 RegisterBitWidth2; ///< PCT Register Bit Width
+ UINT8 RegisterBitOffset2; ///< PCT Register Bit Offset
+ UINT8 Reserved2; ///< Reserved
+ UINT32 StatusRegAddressLo; ///< Control Register Address Low
+ UINT32 StatusRegAddressHi; ///< Control Register Address High
+ UINT16 Value6; ///< Values
+} PCT_HEADER_BODY;
+#define PCT_STRUCT_SIZE 50 // 50 Bytes
+
+
+//--------------------------------------------
+// AML code definition
+// (PSS Header)
+//--------------------------------------------
+///Performance Supported States Header
+typedef struct _PSS_HEADER {
+ UINT8 NameOpcode; ///< Opcode
+ UINT8 PssName_a__; ///< String "_"
+ UINT8 PssName_a_P; ///< String "P"
+ UINT8 PssName_a_S; ///< String "S"
+ UINT8 PssName_b_S; ///< String "S"
+ UINT8 PkgOpcode; ///< Package Opcode
+ UINT16 PssLength; ///< PSS Length
+ UINT8 NumOfItemsInPss; ///< Number of Items in PSS
+} PSS_HEADER;
+#define PSS_HEADER_STRUCT_SIZE 9 // 9 Bytes
+
+
+//--------------------------------------------
+// AML code definition
+// (PSS Body)
+//--------------------------------------------
+///Performance Supported States Body
+typedef struct _PSS_BODY {
+ UINT8 PkgOpcode; ///< Package Opcode
+ UINT8 PkgLength; ///< Package Length
+ UINT8 NumOfElements; ///< Number of Elements
+ UINT8 DwordPrefixOpcode1; ///< Prefix Opcode1
+ UINT32 Frequency; ///< Frequency
+ UINT8 DwordPrefixOpcode2; ///< Prefix Opcode2
+ UINT32 Power; ///< Power
+ UINT8 DwordPrefixOpcode3; ///< Prefix Opcode3
+ UINT32 TransitionLatency; ///< Transition Latency
+ UINT8 DwordPrefixOpcode4; ///< Prefix Opcode4
+ UINT32 BusMasterLatency; ///< Bus Master Latency
+ UINT8 DwordPrefixOpcode5; ///< Prefix Opcode5
+ UINT32 Control; ///< Control
+ UINT8 DwordPrefixOpcode6; ///< Prefix Opcode6
+ UINT32 Status; ///< Status
+} PSS_BODY;
+#define PSS_BODY_STRUCT_SIZE 33 // 33 Bytes
+
+
+/*--------------------------------------------
+ * AML code definition
+ * (XPSS Header)
+ *--------------------------------------------
+ */
+/// Extended PSS Header
+typedef struct _XPSS_HEADER {
+ UINT8 NameOpcode; ///< 08h
+ UINT8 XpssName_a_X; ///< String "X"
+ UINT8 XpssName_a_P; ///< String "P"
+ UINT8 XpssName_a_S; ///< String "S"
+ UINT8 XpssName_b_S; ///< String "S"
+ UINT8 PkgOpcode; ///< 12h
+ UINT16 XpssLength; ///< XPSS Length
+ UINT8 NumOfItemsInXpss; ///< Number of Items in XPSS
+} XPSS_HEADER;
+#define XPSS_HEADER_STRUCT_SIZE 9 // 9 Bytes
+
+/*--------------------------------------------
+ * AML code definition
+ * (XPSS Body)
+ *--------------------------------------------
+ */
+/// Extended PSS Body
+typedef struct _XPSS_BODY {
+ UINT8 PkgOpcode; ///< 12h
+ UINT8 PkgLength; ///< Package Length
+ UINT8 XpssValueTbd; ///< XPSS Value
+ UINT8 NumOfElements; ///< Number of Elements
+ UINT8 DwordPrefixOpcode1; ///< Prefix Opcode1
+ UINT32 Frequency; ///< Frequency
+ UINT8 DwordPrefixOpcode2; ///< Prefix Opcode2
+ UINT32 Power; ///< Power
+ UINT8 DwordPrefixOpcode3; ///< Prefix Opcode3
+ UINT32 TransitionLatency; ///< Transition Latency
+ UINT8 DwordPrefixOpcode4; ///< Prefix Opcode4
+ UINT32 BusMasterLatency; ///< Bus Master Latency
+ UINT32 ControlBuffer; ///< Control Buffer
+ UINT32 ControlLo; ///< Control Low
+ UINT32 ControlHi; ///< Control High
+ UINT32 StatusBuffer; ///< Status Buffer
+ UINT32 StatusLo; ///< Status Low
+ UINT32 StatusHi; ///< Status High
+ UINT32 ControlMaskBuffer; ///< Control Mask Buffer
+ UINT32 ControlMaskLo; ///< Control Mask Low
+ UINT32 ControlMaskHi; ///< Control Mask High
+ UINT32 StatusMaskBuffer; ///< Status Mask Buffer
+ UINT32 StatusMaskLo; ///< Status Mask Low
+ UINT32 StatusMaskHi; ///< Status Mask High
+} XPSS_BODY;
+#define XPSS_BODY_STRUCT_SIZE 72 // 72 Bytes
+
+/*--------------------------------------------
+ * AML code definition
+ * (PPC Header and Body)
+ *--------------------------------------------
+ */
+/// Performance Present Capabilities Header
+typedef struct _PPC_HEADER_BODY {
+ UINT8 NameOpcode; ///< Name Opcode
+ UINT8 PpcName_a_P; ///< String "P"
+ UINT8 PpcName_b_P; ///< String "P"
+ UINT8 PpcName_a_C; ///< String "C"
+ UINT8 PpcName_a_V; ///< String "V"
+ UINT8 Value1; ///< Value
+ UINT8 DefaultPerfPresentCap; ///< Default Perf Present Cap
+ UINT8 MethodOpcode; ///< Method Opcode
+ UINT8 PpcLength; ///< Method Length
+ UINT8 PpcName_a__; ///< String "_"
+ UINT8 PpcName_c_P; ///< String "P"
+ UINT8 PpcName_d_P; ///< String "P"
+ UINT8 PpcName_b_C; ///< String "C"
+ UINT8 MethodFlags; ///< Method Flags
+ UINT8 ReturnOpcode; ///< Return Opcoce
+ UINT8 PpcName_e_P; ///< String "P"
+ UINT8 PpcName_f_P; ///< String "P"
+ UINT8 PpcName_c_C; ///< String "C"
+ UINT8 PpcName_b_V; ///< String "V"
+
+} PPC_HEADER_BODY;
+#define PPC_HEADER_BODY_STRUCT_SIZE 19 // 19 Bytes
+#define PPC_METHOD_LENGTH 11 // 11 Bytes
+
+
+/*--------------------------------------------
+ * AML code definition
+ * (PSD Header)
+ *--------------------------------------------
+ */
+/// P-State Dependency Header
+typedef struct _PSD_HEADER {
+ UINT8 NameOpcode; ///< Name Opcode
+ UINT8 PsdName_a__; ///< String "_"
+ UINT8 PsdName_a_P; ///< String "P"
+ UINT8 PsdName_a_S; ///< String "S"
+ UINT8 PsdName_a_D; ///< String "D"
+ UINT8 PkgOpcode; ///< Package Opcode
+ UINT8 PsdLength; ///< PSD Length
+ UINT8 Value1; ///< Value
+} PSD_HEADER;
+#define PSD_HEADER_STRUCT_SIZE 8 // 8 Bytes
+
+/*--------------------------------------------
+ * AML code definition
+ * (PSD Body)
+ *--------------------------------------------
+ */
+/// P-State Dependency Body
+typedef struct _PSD_BODY {
+ UINT8 PkgOpcode; ///< Package Opcode
+ UINT8 PkgLength; ///< Package Length
+ UINT8 NumOfEntries; ///< Number of Entries
+ UINT8 BytePrefixOpcode1; ///< Prefix Opcode1 in Byte
+ UINT8 PsdNumOfEntries; ///< PSD Number of Entries
+ UINT8 BytePrefixOpcode2; ///< Prefix Opcode2 in Byte
+ UINT8 PsdRevision; ///< PSD Revision
+ UINT8 DwordPrefixOpcode1; ///< Prefix Opcode1 in DWord
+ UINT32 DependencyDomain; ///< Dependency Domain
+ UINT8 DwordPrefixOpcode2; ///< Prefix Opcode2 in DWord
+ UINT32 CoordinationType; ///< (0xFC = SW_ALL, 0xFD = SW_ANY, 0xFE = HW_ALL)
+ UINT8 DwordPrefixOpcode3; ///< Prefix Opcode3 in DWord
+ UINT32 NumOfProcessors; ///< Number of Processors
+} PSD_BODY;
+#define PSD_BODY_STRUCT_SIZE 22 // 22 Bytes
+
+//----------------------------------------------------------------------------
+// WHEA TYPEDEFS, STRUCTURES, ENUMS
+//
+//----------------------------------------------------------------------------
+
+/// HEST MCE TABLE
+typedef struct _AMD_HEST_MCE_TABLE {
+ UINT16 TblLength; ///< Length, in bytes, of entire AMD_HEST_MCE structure.
+ UINT32 GlobCapInitDataLSD; ///< Holds the value that the OS will program into
+ UINT32 GlobCapInitDataMSD; ///< the machine check global capability register(MCG_CAP).
+ UINT32 GlobCtrlInitDataLSD; ///< Holds the value that the OS will program into
+ UINT32 GlobCtrlInitDataMSD; ///< the machine check global control register(MCG_CTL).
+ UINT8 NumHWBanks; ///< The number of hardware error reporting banks.
+ UINT8 Rsvd[7]; ///< reserve 7 bytes as spec's required
+} AMD_HEST_MCE_TABLE;
+
+/// HEST CMC TABLE
+typedef struct _AMD_HEST_CMC_TABLE {
+ UINT16 TblLength; ///< Length, in bytes, of entire AMD_HEST_CMC structure.
+ UINT8 NumHWBanks; ///< The number of hardware error reporting banks.
+ UINT8 Rsvd[3]; ///< reserve 3 bytes as spec's required
+} AMD_HEST_CMC_TABLE;
+
+/// HEST BANK
+typedef struct _AMD_HEST_BANK {
+ UINT8 BankNum; ///< Zero-based index identifies the machine check error bank.
+ UINT8 ClrStatusOnInit; ///< Indicates if the status information in this machine check bank
+ ///< is to be cleared during system initialization.
+ UINT8 StatusDataFormat; ///< Indicates the format of the data in the status register
+ UINT8 ConfWriteEn; ///< This field indicates whether configuration parameters may be
+ ///< modified by the OS. If the bit for the associated parameter is
+ ///< set, the parameter is writable by the OS.
+ UINT32 CtrlRegMSRAddr; ///< Address of the hardware bank's control MSR. Ignored if zero.
+
+ UINT32 CtrlInitDataLSD; ///< This is the value the OS will program into the machine check
+ UINT32 CtrlInitDataMSD; ///< bank's control register
+ UINT32 StatRegMSRAddr; ///< Address of the hardware bank's MCi_STAT MSR. Ignored if zero.
+ UINT32 AddrRegMSRAddr; ///< Address of the hardware bank's MCi_ADDR MSR. Ignored if zero.
+ UINT32 MiscRegMSRAddr; ///< Address of the hardware bank's MCi_MISC MSR. Ignored if zero.
+} AMD_HEST_BANK;
+
+/// Initial data of AMD_HEST_BANK
+typedef struct _AMD_HEST_BANK_INIT_DATA {
+ UINT32 CtrlInitDataLSD; ///< Initial data of CtrlInitDataLSD
+ UINT32 CtrlInitDataMSD; ///< Initial data of CtrlInitDataMSD
+ UINT32 CtrlRegMSRAddr; ///< Initial data of CtrlRegMSRAddr
+ UINT32 StatRegMSRAddr; ///< Initial data of StatRegMSRAddr
+ UINT32 AddrRegMSRAddr; ///< Initial data of AddrRegMSRAddr
+ UINT32 MiscRegMSRAddr; ///< Initial data of MiscRegMSRAddr
+} AMD_HEST_BANK_INIT_DATA;
+
+/// MSR179 Global Machine Check Capabilities data struct
+typedef struct _MSR_MCG_CAP_STRUCT {
+ UINT64 Count:8; ///< Indicates the number of
+ ///< error-reporting banks visible to each core
+ UINT64 McgCtlP:1; ///< 1=The machine check control registers
+ UINT64 Rsvd:55; ///< reserved
+} MSR_MCG_CAP_STRUCT;
+
+/// Initial data of WHEA
+typedef struct _AMD_WHEA_INIT_DATA {
+ UINT32 GlobCapInitDataLSD; ///< Holds the value that the OS will program into the machine
+ UINT32 GlobCapInitDataMSD; ///< Check global capability register
+ UINT32 GlobCtrlInitDataLSD; ///< Holds the value that the OS will grogram into the machine
+ UINT32 GlobCtrlInitDataMSD; ///< Check global control register
+ UINT8 ClrStatusOnInit; ///< Indicates if the status information in this machine check
+ ///< bank is to be cleared during system initialization
+ UINT8 StatusDataFormat; ///< Indicates the format of the data in the status register
+ UINT8 ConfWriteEn; ///< This field indicates whether configuration parameters may be
+ ///< modified by the OS. If the bit for the associated parameter is
+ ///< set, the parameter is writable by the OS.
+ UINT8 HestBankNum; ///< Number of HEST Bank
+ AMD_HEST_BANK_INIT_DATA *HestBankInitData; ///< Pointer to Initial data of HEST Bank
+} AMD_WHEA_INIT_DATA;
+
+//----------------------------------------------------------------------------
+// DMI TYPEDEFS, STRUCTURES, ENUMS
+//
+//----------------------------------------------------------------------------
+/// DMI brand information
+typedef struct {
+ UINT16 String1:4; ///< String1
+ UINT16 String2:4; ///< String2
+ UINT16 Model:7; ///< Model
+ UINT16 Pg:1; ///< Page
+} BRAND_ID;
+
+/// DMI cache information
+typedef struct {
+ UINT32 L1CacheSize; ///< L1 cache size
+ UINT8 L1CacheAssoc; ///< L1 cache associativity
+ UINT32 L2CacheSize; ///< L2 cache size
+ UINT8 L2CacheAssoc; ///< L2 cache associativity
+ UINT32 L3CacheSize; ///< L3 cache size
+ UINT8 L3CacheAssoc; ///< L3 cache associativity
+} CPU_CACHE_INFO;
+
+/// DMI processor information
+typedef struct {
+ UINT8 ExtendedFamily; ///< Extended Family
+ UINT8 ExtendedModel; ///< Extended Model
+ UINT8 BaseFamily; ///< Base Family
+ UINT8 BaseModel; ///< Base Model
+ UINT8 Stepping; ///< Stepping
+ UINT8 PackageType; ///< PackageType
+ BRAND_ID BrandId; ///< BrandId which contains information about String1, String2, Model and Page
+ UINT8 TotalCoreNumber; ///< Number of total cores
+ UINT8 EnabledCoreNumber; ///< Number of enabled cores
+ UINT8 ProcUpgrade; ///< ProcUpdrade
+ CPU_CACHE_INFO CacheInfo; ///< CPU cache info
+} CPU_TYPE_INFO;
+
+/// A structure containing processor name string and
+/// the value that should be provide to DMI type 4 processor family
+typedef struct {
+ IN CONST CHAR8 *Stringstart; ///< The literal string
+ IN UINT8 T4ProcFamilySetting; ///< The value set to DMI type 4 processor family
+} CPU_T4_PROC_FAMILY;
+
+/// DMI ECC information
+typedef struct {
+ BOOLEAN EccCapable; ///< ECC Capable
+} CPU_GET_MEM_INFO;
+
+/* Transfer vectors for DMI family specific routines */
+typedef VOID OPTION_DMI_GET_CPU_INFO (
+ IN OUT CPU_TYPE_INFO *CpuInfoPtr,
+ IN AMD_CONFIG_PARAMS *StdHeader
+ );
+
+typedef VOID OPTION_DMI_GET_PROC_FAMILY (
+ IN OUT UINT8 *T4ProcFamily,
+ IN PROC_FAMILY_TABLE *CpuDmiProcFamilyTable,
+ IN CPU_TYPE_INFO *CpuInfo,
+ IN AMD_CONFIG_PARAMS *StdHeader
+ );
+
+typedef UINT8 OPTION_DMI_GET_VOLTAGE (
+ IN AMD_CONFIG_PARAMS *StdHeader
+ );
+
+typedef UINT16 OPTION_DMI_GET_MAX_SPEED (
+ IN AMD_CONFIG_PARAMS *StdHeader
+ );
+
+typedef UINT16 OPTION_DMI_GET_EXT_CLOCK (
+ IN AMD_CONFIG_PARAMS *StdHeader
+ );
+
+typedef VOID OPTION_DMI_GET_MEM_INFO (
+ IN OUT CPU_GET_MEM_INFO *CpuGetMemInfoPtr,
+ IN AMD_CONFIG_PARAMS *StdHeader
+ );
+
+/// Brand table entry format
+typedef struct {
+ UINT8 PackageType; ///< Package type
+ UINT8 PgOfBrandId; ///< Page
+ UINT8 NumberOfCores; ///< Number of cores
+ UINT8 String1ofBrandId; ///< String1
+ UINT8 ValueSetToDmiTable; ///< The value which will should be set to DMI table
+} DMI_BRAND_ENTRY;
+
+/// Family specific data table structure
+struct _PROC_FAMILY_TABLE {
+ UINT64 ProcessorFamily; ///< processor
+ OPTION_DMI_GET_CPU_INFO *DmiGetCpuInfo; ///< transfer vectors
+ OPTION_DMI_GET_PROC_FAMILY *DmiGetT4ProcFamily; ///< Get DMI type 4 processor family information
+ OPTION_DMI_GET_VOLTAGE *DmiGetVoltage; ///< vector for reading voltage
+ OPTION_DMI_GET_MAX_SPEED *DmiGetMaxSpeed; ///< vector for reading speed
+ OPTION_DMI_GET_EXT_CLOCK *DmiGetExtClock; ///< vector for reading external clock speed
+ OPTION_DMI_GET_MEM_INFO *DmiGetMemInfo; ///< Get memory information
+ UINT8 LenBrandList; ///< size of brand table
+ CONST DMI_BRAND_ENTRY *DmiBrandList; ///< translate brand info to DMI identifier
+};
+
+//----------------------------------------------------------------------------
+// SLIT TYPEDEFS, STRUCTURES, ENUMS
+//
+//----------------------------------------------------------------------------
+/// Format for SRAT Header
+typedef struct {
+ UINT8 Sign[4]; ///< Signature
+ UINT32 TableLength; ///< Table Length
+ UINT8 Revision; ///< Revision
+ UINT8 Checksum; ///< Checksum
+ UINT8 OemId[6]; ///< OEM ID
+ UINT8 OemTableId[8]; ///< OEM Tabled ID
+ UINT32 OemRev; ///< OEM Revision
+ UINT8 CreatorId[4]; ///< Creator ID
+ UINT32 CreatorRev; ///< Creator Revision
+} ACPI_TABLE_HEADER;
+
+//----------------------------------------------------------------------------
+// SRAT TYPEDEFS, STRUCTURES, ENUMS
+//
+//----------------------------------------------------------------------------
+/// Format for SRAT Header
+typedef struct _CPU_SRAT_HEADER {
+ UINT8 Sign[4]; ///< Signature
+ UINT32 TableLength; ///< Table Length
+ UINT8 Revision; ///< Revision
+ UINT8 Checksum; ///< Checksum
+ UINT8 OemId[6]; ///< OEM ID
+ UINT8 OemTableId[8]; ///< OEM Tabled ID
+ UINT32 OemRev; ///< OEM Revision
+ UINT8 CreatorId[4]; ///< Creator ID
+ UINT32 CreatorRev; ///< Creator Revision
+ UINT32 TableRev; ///< Table Revision
+ UINT8 Reserved[8]; ///< Reserved
+} CPU_SRAT_HEADER;
+
+
+/// Format for SRAT APIC Affinity Entry
+typedef struct _CPU_SRAT_APIC_ENTRY {
+ UINT8 Type; ///< Type
+ UINT8 Length; ///< Length
+ UINT8 Domain; ///< Domain
+ UINT8 ApicId; ///< Apic ID
+ UINT32 Flags; ///< Flags
+ UINT8 LSApicEid; ///< Local SAPIC EID
+ UINT8 Reserved[7]; ///< Reserved
+} CPU_SRAT_APIC_ENTRY;
+
+
+/// Format for SRAT Memory Affinity Entry
+typedef struct _CPU_SRAT_MEMORY_ENTRY {
+ UINT8 Type; ///< 0: Memory affinity = 1
+ UINT8 Length; ///< 1: Length = 40 bytes
+ UINT32 Domain; ///< 2: Proximity domain
+ UINT8 Reserved1[2]; ///< 6: Reserved
+ UINT32 BaseAddrLow; ///< 8: Low 32bits address base
+ UINT32 BaseAddrHigh; ///< 12: High 32bits address base
+ UINT32 LengthAddrLow; ///< 16: Low 32bits address limit
+ UINT32 LengthAddrHigh; ///< 20: High 32bits address limit
+ UINT8 Reserved2[4]; ///< 24: Memory Type
+ UINT32 Flags; ///< 28: Flags
+ UINT8 Reserved3[8]; ///< 32: Reserved
+} CPU_SRAT_MEMORY_ENTRY;
+
+//----------------------------------------------------------------------------
+// CRAT TYPEDEFS, STRUCTURES, ENUMS
+// Component Resource Affinity Table
+//----------------------------------------------------------------------------
+/// Format for CRAT Header
+typedef struct {
+ UINT8 Sign[4]; ///< CRAT, Signature for the Component Resource Affinity Table.
+ UINT32 Length; ///< Length, in bytes, of the entire CRAT
+ UINT8 Revision; ///< 0
+ UINT8 Checksum; ///< Entire table must sum to zero.
+ UINT8 OemId[6]; ///< OEM ID
+ UINT8 OemTableId[8]; ///< OEM Tabled ID
+ UINT32 OemRev; ///< OEM Revision
+ UINT8 CreatorId[4]; ///< Creator ID
+ UINT32 CreatorRev; ///< Creator Revision
+ UINT32 TotalEntries; ///< total number[n] of entries in the CRAT
+ UINT16 NumDomains; ///< Number of HSA proximity domains
+ UINT8 Reserved[6]; ///< Reserved
+} CRAT_HEADER;
+
+/// Flags field of the CRAT HSA Processing Unit Affinity Structure
+typedef struct {
+ UINT32 Enabled:1; ///< Enabled
+ UINT32 HotPluggable:1; ///< Hot Pluggable
+ UINT32 CpuPresent:1; ///< Cpu Present
+ UINT32 GpuPresent:1; ///< Gpu Present
+ UINT32 IommuPresent:1; ///< IOMMU Present
+ UINT32 :27; ///< Reserved
+} CRAT_HSA_PROCESSING_UNIT_FLAG;
+
+/// CRAT HSA Processing Unit Affinity Structure
+typedef struct {
+ UINT8 Type; ///< 0 - CRAT HSA Processing Unit Structure
+ UINT8 Length; ///< 40
+ UINT16 Reserved; ///< Reserved
+ CRAT_HSA_PROCESSING_UNIT_FLAG Flags; ///< Flags - HSA Processing Unit Affinity Structure
+ UINT32 ProximityDomain; ///< Integer that represents the proximity domain to which the node belongs to
+ UINT32 ProcessorIdLow; ///< Low value of the logical processor included in this HSA proximity domain
+ UINT16 NumCPUCores; ///< Indicates count of CCompute execution units present in this APU node.
+ UINT16 NumSIMDCores; ///< Indicates maximum count of HCompute SIMD cores present in this node.
+ UINT16 MaxWavesSIMD; ///< This identifies the max. number of launched waves per SIMD.
+ UINT16 IoCount; ///< Number of discoverable IO Interfaces connecting this node to other components.
+ UINT16 HSACapability; ///< Must be 0
+ UINT16 LDSSizeInKB; ///< Size of LDS memory per SIMD Wavefront
+ UINT8 WaveFrontSize; ///< 64, may be 32 for some FSA based architectures
+ UINT8 NumBanks; ///< Number of Banks or "Shader Engines", typically 1 or 2
+ UINT16 uEngineIdentifier; ///< Identifier (Rev) of the GPU uEngine or firmware
+ UINT8 NumArrays; ///< Number of SIMD Arrays per Engine
+ UINT8 NumCUPerArray; ///< Number of Compute Units (CU) per SIMD Array
+ UINT8 NumSIMDPerCU; ///< Number of SIMD representing a Compute Unit
+ UINT8 MaxSlotsScratchCU; ///< Max. Number of temp. memory ("scratch") wave slots
+ ///< available to access, may be 0 if HW has no restrictions
+ UINT8 Reserved1[4]; ///< Reserved
+} CRAT_HSA_PROCESSING_UNIT;
+
+/// Flags field of the CRAT Memory Affinity Structure
+typedef struct {
+ UINT32 Enabled:1; ///< Enabled
+ UINT32 HotPluggable:1; ///< Hot Pluggable
+ UINT32 NonVolatile:1; ///< If set, the memory region represents Non-Volatile memory
+ UINT32 :29; ///< Reserved
+} CRAT_MEMORY_FLAG;
+
+/// CRAT Memory Affinity Structure
+typedef struct {
+ UINT8 Type; ///< 1 - CRAT Memory Affinity Structure
+ UINT8 Length; ///< 40
+ UINT16 Reserved; ///< Reserved
+ CRAT_MEMORY_FLAG Flags; ///< Flags - Memory Affinity Structure. Indicates whether the region of memory is enabled and can be hot plugged
+ UINT32 ProximityDomain; ///< Integer that represents the proximity domain to which the node belongs to
+ UINT32 BaseAddressLow; ///< Low 32Bits of the Base Address of the memory range
+ UINT32 BaseAddressHigh; ///< High 32Bits of the Base Address of the memory range
+ UINT32 LengthLow; ///< Low 32Bits of the length of the memory range
+ UINT32 LengthHigh; ///< High 32Bits of the length of the memory range
+ UINT32 Width; ///< Memory width - Specifies the number of parallel bits of the memory interface
+ UINT8 Reserved1[8]; ///< Reserved
+} CRAT_MEMORY;
+
+/// Flags field of the CRAT Cache Affinity structure
+typedef struct {
+ UINT32 Enabled:1; ///< Enabled
+ UINT32 DataCache:1; ///< 1 if cache includes data
+ UINT32 InstructionCache:1; ///< 1 if cache includes instructions
+ UINT32 CpuCache:1; ///< 1 if cache is part of CPU functionality
+ UINT32 SimdCache:1; ///< 1 if cache is part of SIMD functionality
+ UINT32 :27; ///< Reserved
+} CRAT_CACHE_FLAG;
+
+/// CRAT Cache Affinity Structure
+typedef struct {
+ UINT8 Type; ///< 2 - CRAT Cache Affinity Structure
+ UINT8 Length; ///< 64
+ UINT16 Reserved; ///< Reserved
+ CRAT_CACHE_FLAG Flags; ///< Flags - Cache Affinity Structure. Indicates whether the region of cache is enabled
+ UINT32 ProcessorIdLow; ///< Low value of a logical processor which includes this component
+ UINT8 SiblingMap[32]; ///< Bitmask of Processor Id sharing this component. 1 bit per logical processor
+ UINT32 CacheSize; ///< Cache size in KB
+ UINT8 CacheLevel; ///< Integer representing level: 1, 2, 3, 4, etc.
+ UINT8 LinesPerTag; ///< Cache Lines per tag
+ UINT16 CacheLineSize; ///< Cache line size in bytes
+ UINT8 Associativity; ///< Cache associativity
+ ///< The associativity fields are encoded as follows:
+ ///< 00h: Reserved.
+ ///< 01h: Direct mapped.
+ ///< 02h-FEh: Associativity. (e.g., 04h = 4-way associative.)
+ ///< FFh: Fully associative
+ UINT8 CacheProperties; ///< Cache Properties bits [2:0] represent Inclusive/Exclusive property encoded.
+ ///< 0: Cache is strictly exclusive to lower level caches.
+ ///< 1: Cache is mostly exclusive to lower level caches.
+ ///< 2: Cache is strictly inclusive to lower level caches.
+ ///< 3: Cache is mostly inclusive to lower level caches.
+ ///< 4: Cache is a "constant cache" (= explicit update)
+ ///< 5: Cache is a "specialty cache" (e.g. Texture cache)
+ ///< 6-7: Reserved
+ ///< CacheProperties bits [7:3] are reserved
+ UINT16 CacheLatency; ///< Cost of time to access cache described in nanoseconds.
+ UINT8 Reserved1[8]; ///< Reserved
+} CRAT_CACHE;
+
+/// Flags field of the CRAT TLB Affinity structure
+typedef struct {
+ UINT32 Enabled:1; ///< Enabled
+ UINT32 DataTLB:1; ///< 1 if TLB includes translation information for data.
+ UINT32 InstructionTLB:1; ///< 1 if TLB includes translation information for instructions.
+ UINT32 CpuTLB:1; ///< 1 if TLB is part of CPU functionality
+ UINT32 SimdTLB:1; ///< 1 if TLB is part of SIMD functionality
+ UINT32 TLB4KBase256:1; ///< 1 if value in table is factored by 256 to get number of 4K entries
+ UINT32 :1; ///< Reserved
+ UINT32 TLB2MBase256:1; ///< 1 if value in table is factored by 256 to get number of 2M entries
+ UINT32 :1; ///< Reserved
+ UINT32 TLB1GBase256:1; ///< 1 if value in table is factored by 256 to get number of 1G entries
+ UINT32 :22; ///< Reserved
+} CRAT_TLB_FLAG;
+
+/// CRAT TLB Affinity Structure
+typedef struct {
+ UINT8 Type; ///< 3 - CRAT TLB Affinity Structure
+ UINT8 Length; ///< 64
+ UINT16 Reserved; ///< Reserved
+ CRAT_TLB_FLAG Flags; ///< Flags - TLB Affinity Structure. Indicates whether the TLB is enabled and defined
+ UINT32 ProcessorIdLow; ///< Low value of a logical processor which includes this component.
+ UINT8 SiblingMap[32]; ///< Bitmask of Processor Id sharing this component. 1 bit per logical processor
+ UINT32 TlbLevel; ///< Integer representing level: 1, 2, 3, 4, etc.
+ UINT8 DataTlbAssociativity2MB; ///< Data TLB associativity for 2MB pages
+ ///< The associativity fields are encoded as follows:
+ ///< 00h: Reserved.
+ ///< 01h: Direct mapped.
+ ///< 02h-FEh: Associativity. (e.g., 04h = 4-way associative.)
+ ///< FFh: Fully associative.
+ UINT8 DataTlbSize2MB; ///< Data TLB number of entries for 2MB.
+ UINT8 InstructionTlbAssociativity2MB; ///< Instruction TLB associativity for 2MB pages
+ ///< The associativity fields are encoded as follows:
+ ///< 00h: Reserved.
+ ///< 01h: Direct mapped.
+ ///< 02h-FEh: Associativity. (e.g., 04h = 4-way associative.)
+ ///< FFh: Fully associative.
+ UINT8 InstructionTlbSize2MB; ///< Instruction TLB number of entries for 2MB pages.
+ UINT8 DataTlbAssociativity4K; ///< Data TLB Associativity for 4KB pages
+ UINT8 DataTlbSize4K; ///< Data TLB number of entries for 4KB pages
+ UINT8 InstructionTlbAssociativity4K; ///< Instruction TLB Associativity for 4KB pages
+ UINT8 InstructionTlbSize4K; ///< Instruction TLB number of entries for 4KB pages
+ UINT8 DataTlbAssociativity1G; ///< Data TLB Associativity for 1GB pages
+ UINT8 DataTlbSize1G; ///< Data TLB number of entries for 1GB pages
+ UINT8 InstructionTlbAssociativity1G; ///< Instruction TLB Associativity for 1GB pages
+ UINT8 InstructionTlbSize1G; ///< Instruction TLB number of entries for 1GB pages
+ UINT8 Reserved1[4]; ///< Reserved
+} CRAT_TLB;
+
+/// Flags field of the CRAT FPU Affinity structure
+typedef struct {
+ UINT32 Enabled:1; ///< Enabled
+ UINT32 :31; ///< Reserved
+} CRAT_FPU_FLAG;
+
+/// CRAT FPU Affinity Structure
+typedef struct {
+ UINT8 Type; ///< 4 - CRAT FPU Affinity Structure
+ UINT8 Length; ///< 64
+ UINT16 Reserved; ///< Reserved
+ CRAT_FPU_FLAG Flags; ///< Flags - FPU Affinity Structure. Indicates whether the region of FPU affinity structure is enabled and defined
+ UINT32 ProcessorIdLow; ///< Low value of a logical processor which includes this component.
+ UINT8 SiblingMap[32]; ///< Bitmask of Processor Id sharing this component. 1 bit per logical processor
+ UINT32 FPUSize; ///< Product specific
+ UINT8 Reserved1[16]; ///< Reserved
+} CRAT_FPU;
+
+/// Flags field of the CRAT IO Affinity structure
+typedef struct {
+ UINT32 Enabled:1; ///< Enabled
+ UINT32 Coherency:1; ///< If set, IO interface supports coherent transactions (natively or through protocol extensions)
+ UINT32 :30; ///< Reserved
+} CRAT_IO_FLAG;
+
+/// CRAT IO Affinity Structure
+typedef struct {
+ UINT8 Type; ///< 5 - CRAT IO Affinity Structure
+ UINT8 Length; ///< 64
+ UINT16 Reserved; ///< Reserved
+ CRAT_IO_FLAG Flags; ///< Flags - IO Affinity Structure. Indicates whether the region of IO affinity structure is enabled and defined.
+ UINT32 ProximityDomainFrom; ///< Integer that represents the proximity domain to which the IO Interface belongs to
+ UINT32 ProximityDomainTo; ///< Integer that represents the other proximity domain to which the IO Interface belongs to
+ UINT8 IoType; ///< IO Interface type. Values defined are
+ ///< 0: Undefined
+ ///< 1: Hypertransport
+ ///< 2: PCI Express
+ ///< 3: Other (e.g. internal)
+ ///< 4-255: Reserved
+ UINT8 VersionMajor; ///< Major version of the Bus interface
+ UINT16 VersionMinor; ///< Minor version of the Bus interface ((optional)
+ UINT32 MinimumLatency; ///< Cost of time to transfer, described in nanoseconds.
+ UINT32 MaximumLatency; ///< Cost of time to transfer, described in nanoseconds.
+ UINT32 MinimumBandwidth; ///< Minimum interface Bandwidth in MB/s
+ UINT32 MaximumBandwidth; ///< Maximum interface Bandwidth in MB/s
+ UINT32 RecommendedTransferSize; ///< Recommended transfer size to reach maximum interface bandwidth in Bytes
+ UINT8 Reserved1[24]; ///< Reserved
+} CRAT_IO;
+
+#define CRAT_MAX_LENGTH 0x800ul ///< Reserve 2K for CRAT
+/// CRAT entry type
+typedef enum {
+ CRAT_TYPE_HSA_PROC_UNIT = 0, ///< 0 - CRAT HSA Processing Unit Structure
+ CRAT_TYPE_MEMORY, ///< 1 - CRAT Memory Affinity Structure
+ CRAT_TYPE_CACHE, ///< 2 - CRAT Cache Affinity Structure
+ CRAT_TYPE_TLB, ///< 3 - CRAT TLB Affinity Structure
+ CRAT_TYPE_FPU, ///< 4 - CRAT FPU Affinity Structure
+ CRAT_TYPE_IO, ///< 5 - CRAT IO Affinity Structure
+} CRAT_ENTRY_TYPE;
+
+/*----------------------------------------------------------------------------------------
+ * F U N C T I O N P R O T O T Y P E
+ *----------------------------------------------------------------------------------------
+ */
+
+AGESA_STATUS
+AmdCpuLate (
+ IN AMD_CONFIG_PARAMS *StdHeader,
+ IN PLATFORM_CONFIGURATION *PlatformConfig
+ );
+
+AGESA_STATUS
+CreateAcpiWhea (
+ IN OUT AMD_CONFIG_PARAMS *StdHeader,
+ IN OUT VOID **WheaMcePtr,
+ IN OUT VOID **WheaCmcPtr
+ );
+
+AGESA_STATUS
+CreateDmiRecords (
+ IN OUT AMD_CONFIG_PARAMS *StdHeader,
+ IN OUT DMI_INFO **DmiTable
+ );
+
+AGESA_STATUS
+GetType4Type7Info (
+ IN AP_EXE_PARAMS *ApExeParams
+ );
+
+VOID
+DmiGetT4ProcFamilyFromBrandId (
+ IN OUT UINT8 *T4ProcFamily,
+ IN PROC_FAMILY_TABLE *CpuDmiProcFamilyTable,
+ IN CPU_TYPE_INFO *CpuInfo,
+ IN AMD_CONFIG_PARAMS *StdHeader
+ );
+
+VOID
+GetNameString (
+ IN OUT CHAR8 *String,
+ IN OUT AMD_CONFIG_PARAMS *StdHeader
+ );
+
+BOOLEAN
+IsSourceStrContainTargetStr (
+ IN OUT CHAR8 *SourceStr,
+ IN OUT CONST CHAR8 *TargetStr,
+ IN OUT AMD_CONFIG_PARAMS *StdHeader
+ );
+
+AGESA_STATUS
+CreateAcpiCrat (
+ IN OUT AMD_CONFIG_PARAMS *StdHeader,
+ OUT VOID **CratPtr
+ );
+
+AGESA_STATUS
+CreateAcpiCdit (
+ IN OUT AMD_CONFIG_PARAMS *StdHeader,
+ IN PLATFORM_CONFIGURATION *PlatformConfig,
+ OUT VOID **CditPtr
+ );
+
+AGESA_STATUS
+CreateAcpiSrat (
+ IN OUT AMD_CONFIG_PARAMS *StdHeader,
+ IN OUT VOID **SratPtr
+ );
+
+AGESA_STATUS
+CreateAcpiSlit (
+ IN OUT AMD_CONFIG_PARAMS *StdHeader,
+ IN PLATFORM_CONFIGURATION *PlatformConfig,
+ IN OUT VOID **SlitPtr
+ );
+
+VOID
+ChecksumAcpiTable (
+ IN OUT ACPI_TABLE_HEADER *Table,
+ IN AMD_CONFIG_PARAMS *StdHeader
+ );
+
+AGESA_STATUS
+RunLateApTaskOnAllAPs (
+ IN AP_EXE_PARAMS *ApParams,
+ IN AMD_CONFIG_PARAMS *StdHeader
+ );
+
+AGESA_STATUS
+RunLateApTaskOnAllCore0s (
+ IN AP_EXE_PARAMS *ApParams,
+ IN AMD_CONFIG_PARAMS *StdHeader
+ );
+
+#endif // _CPU_LATE_INIT_H_
diff --git a/src/vendorcode/amd/pi/00630F01/Proc/CPU/cpuRegisters.h b/src/vendorcode/amd/pi/00630F01/Proc/CPU/cpuRegisters.h
new file mode 100644
index 0000000..e41226a
--- /dev/null
+++ b/src/vendorcode/amd/pi/00630F01/Proc/CPU/cpuRegisters.h
@@ -0,0 +1,479 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD CPU Register Table Related Functions
+ *
+ * Contains the definition of the CPU CPUID MSRs and PCI registers with BKDG recommended values
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: CPU
+ * @e \$Revision: 284995 $ @e \$Date: 2014-02-17 11:17:41 -0600 (Mon, 17 Feb 2014) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright (c) 2008 - 2014, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ ******************************************************************************
+ */
+
+#ifndef _CPU_REGISTERS_H_
+#define _CPU_REGISTERS_H_
+
+#include "cpuFamRegisters.h"
+/*
+ *--------------------------------------------------------------
+ *
+ * M O D U L E S U S E D
+ *
+ *---------------------------------------------------------------
+ */
+
+/*
+ *--------------------------------------------------------------
+ *
+ * D E F I N I T I O N S / M A C R O S
+ *
+ *---------------------------------------------------------------
+ */
+
+#undef BIT0
+#undef BIT1
+#undef BIT2
+#undef BIT3
+#undef BIT4
+#undef BIT5
+#undef BIT6
+#undef BIT7
+#undef BIT8
+#undef BIT9
+#undef BIT10
+#undef BIT10
+#undef BIT11
+#undef BIT12
+#undef BIT13
+#undef BIT14
+#undef BIT15
+#undef BIT16
+#undef BIT17
+#undef BIT18
+#undef BIT19
+#undef BIT20
+#undef BIT21
+#undef BIT22
+#undef BIT23
+#undef BIT24
+#undef BIT25
+#undef BIT26
+#undef BIT27
+#undef BIT28
+#undef BIT29
+#undef BIT30
+#undef BIT31
+#undef BIT32
+#undef BIT33
+#undef BIT34
+#undef BIT35
+#undef BIT36
+#undef BIT37
+#undef BIT38
+#undef BIT39
+#undef BIT40
+#undef BIT41
+#undef BIT42
+#undef BIT43
+#undef BIT44
+#undef BIT45
+#undef BIT46
+#undef BIT47
+#undef BIT48
+#undef BIT49
+#undef BIT40
+#undef BIT41
+#undef BIT42
+#undef BIT43
+#undef BIT44
+#undef BIT45
+#undef BIT46
+#undef BIT47
+#undef BIT48
+#undef BIT49
+#undef BIT50
+#undef BIT51
+#undef BIT52
+#undef BIT53
+#undef BIT54
+#undef BIT55
+#undef BIT56
+#undef BIT57
+#undef BIT58
+#undef BIT59
+#undef BIT60
+#undef BIT61
+#undef BIT62
+#undef BIT63
+
+#define BIT0 0x0000000000000001ull
+#define BIT1 0x0000000000000002ull
+#define BIT2 0x0000000000000004ull
+#define BIT3 0x0000000000000008ull
+#define BIT4 0x0000000000000010ull
+#define BIT5 0x0000000000000020ull
+#define BIT6 0x0000000000000040ull
+#define BIT7 0x0000000000000080ull
+#define BIT8 0x0000000000000100ull
+#define BIT9 0x0000000000000200ull
+#define BIT10 0x0000000000000400ull
+#define BIT11 0x0000000000000800ull
+#define BIT12 0x0000000000001000ull
+#define BIT13 0x0000000000002000ull
+#define BIT14 0x0000000000004000ull
+#define BIT15 0x0000000000008000ull
+#define BIT16 0x0000000000010000ull
+#define BIT17 0x0000000000020000ull
+#define BIT18 0x0000000000040000ull
+#define BIT19 0x0000000000080000ull
+#define BIT20 0x0000000000100000ull
+#define BIT21 0x0000000000200000ull
+#define BIT22 0x0000000000400000ull
+#define BIT23 0x0000000000800000ull
+#define BIT24 0x0000000001000000ull
+#define BIT25 0x0000000002000000ull
+#define BIT26 0x0000000004000000ull
+#define BIT27 0x0000000008000000ull
+#define BIT28 0x0000000010000000ull
+#define BIT29 0x0000000020000000ull
+#define BIT30 0x0000000040000000ull
+#define BIT31 0x0000000080000000ull
+#define BIT32 0x0000000100000000ull
+#define BIT33 0x0000000200000000ull
+#define BIT34 0x0000000400000000ull
+#define BIT35 0x0000000800000000ull
+#define BIT36 0x0000001000000000ull
+#define BIT37 0x0000002000000000ull
+#define BIT38 0x0000004000000000ull
+#define BIT39 0x0000008000000000ull
+#define BIT40 0x0000010000000000ull
+#define BIT41 0x0000020000000000ull
+#define BIT42 0x0000040000000000ull
+#define BIT43 0x0000080000000000ull
+#define BIT44 0x0000100000000000ull
+#define BIT45 0x0000200000000000ull
+#define BIT46 0x0000400000000000ull
+#define BIT47 0x0000800000000000ull
+#define BIT48 0x0001000000000000ull
+#define BIT49 0x0002000000000000ull
+#define BIT50 0x0004000000000000ull
+#define BIT51 0x0008000000000000ull
+#define BIT52 0x0010000000000000ull
+#define BIT53 0x0020000000000000ull
+#define BIT54 0x0040000000000000ull
+#define BIT55 0x0080000000000000ull
+#define BIT56 0x0100000000000000ull
+#define BIT57 0x0200000000000000ull
+#define BIT58 0x0400000000000000ull
+#define BIT59 0x0800000000000000ull
+#define BIT60 0x1000000000000000ull
+#define BIT61 0x2000000000000000ull
+#define BIT62 0x4000000000000000ull
+#define BIT63 0x8000000000000000ull
+
+/// CPUID related registers
+#define AMD_CPUID_FMF 0x80000001ul // Family Model Features information
+#define AMD_CPUID_APICID_LPC_BID 0x00000001ul // Local APIC ID, Logical Processor Count, Brand ID
+#define AMD_CPUID_L2L3Cache_L2TLB 0x80000006ul
+#define CPUID_ASSOCIATIVITY_DISABLED 0x00
+#define CPUID_ASSOCIATIVITY_1_WAY 0x01
+#define CPUID_ASSOCIATIVITY_2_WAY 0x02
+#define CPUID_ASSOCIATIVITY_4_WAY 0x04
+#define CPUID_ASSOCIATIVITY_8_WAY 0x06
+#define CPUID_ASSOCIATIVITY_16_WAY 0x08
+#define CPUID_ASSOCIATIVITY_32_WAY 0x0A
+#define CPUID_ASSOCIATIVITY_48_WAY 0x0B
+#define CPUID_ASSOCIATIVITY_64_WAY 0x0C
+#define CPUID_ASSOCIATIVITY_96_WAY 0x0D
+#define CPUID_ASSOCIATIVITY_128_WAY 0x0E
+#define CPUID_ASSOCIATIVITY_FULLY 0x0F
+#define AMD_CPUID_TLB_L1Cache 0x80000005ul
+#define AMD_CPUID_L1L2Tlb1GIdentifiers 0x80000019ul
+#define AMD_CPUID_APM 0x80000007ul
+#define LOCAL_APIC_ID 24
+#define LOGICAL_PROCESSOR_COUNT 16
+#define AMD_CPUID_ASIZE_PCCOUNT 0x80000008ul // Address Size, Physical Core Count
+
+/// CPU Logical ID Transfer
+typedef struct {
+ UINT32 RawId; ///< RawID
+ UINT64 LogicalId; ///< LogicalID
+} CPU_LOGICAL_ID_XLAT;
+
+/// Logical CPU ID Table
+typedef struct {
+ IN UINT32 Elements; ///< Number of Elements
+ IN CPU_LOGICAL_ID_XLAT *LogicalIdTable; ///< CPU Logical ID Transfer table Pointer
+} LOGICAL_ID_TABLE;
+
+// MSRs
+// ------------------------
+#define MCG_CTL_P 0x00000100ul // bit 8 for MCG_CTL_P under MSRR
+#define MSR_MCG_CAP 0x00000179ul
+#define DBG_CTL_MSR 0x000001D9ul
+#define MSR_MC0_CTL 0x00000400ul
+#define MSR_MC0_STATUS 0x00000401ul
+#define MSR_MC0_MISC 0x00000403ul
+#define MSR_MC1_MISC 0x00000407ul
+#define MSR_MC2_MISC 0x0000040Bul
+#define MSR_MC4_CTL 0x00000410ul
+#define MSR_MC4_MISC0 0x00000413ul
+#define MSR_MC5_MISC 0x00000417ul
+#define MSR_MC4_MISC1 0xC0000408ul
+#define MSR_MC5_STATUS 0x00000415ul
+#define MSR_MC6_STATUS 0x00000419ul
+
+#define MSR_APIC_BAR 0x0000001Bul
+#define MSR_PATCH_LEVEL 0x0000008Bul
+
+#define CPUID_LONG_MODE_ADDR 0x80000008ul
+
+#define MSR_EXTENDED_FEATURE_EN 0xC0000080ul
+#define MSR_MC_MISC_LINK_THRESHOLD 0xC0000408ul
+#define MSR_MC_MISC_L3_THRESHOLD 0xC0000409ul
+#define MSR_PATCH_LOADER 0xC0010020ul
+
+/// Patch Loader Register
+typedef struct {
+ UINT64 PatchBase:32; ///< Linear address of patch header address block
+ UINT64 SBZ:32; ///< Should be zero
+} PATCH_LOADER_MSR;
+
+#define MSR_SYS_CFG 0xC0010010ul // SYSCFG - F15 Shared
+#define MSR_TOM2 0xC001001Dul // TOP_MEM2 - F15 Shared
+#define MSR_MC0_CTL_MASK 0xC0010044ul // MC0 Control Mask
+#define MSR_MC1_CTL_MASK 0xC0010045ul // MC1 Control Mask
+#define MSR_MC2_CTL_MASK 0xC0010046ul // MC2 Control Mask
+#define MSR_MC4_CTL_MASK 0xC0010048ul // MC4 Control Mask
+
+#define MSR_CPUID_FEATS 0xC0011004ul // CPUID Features
+#define MSR_CPUID_EXT_FEATS 0xC0011005ul // CPUID Extended Features
+#define MSR_HDT_CFG 0xC001100Aul
+#define MSR_HWCR 0xC0010015ul
+#define MSR_NB_CFG 0xC001001Ful // NB Config
+#define CPU_WDT_CFG 0xC0010074ul
+#define ENABLE_CF8_EXT_CFG 0x00004000ul // [46]
+#define INIT_APIC_CPUID_LO 0x00400000ul // [54]
+#define MSR_CU_SPMCTL 0xC0010281ul
+#define MSR_CpuWdtCfg 0xC0010074ul // CPU Watchdog Timer
+#define MSR_LS_CFG 0xC0011020ul
+#define MSR_IC_CFG 0xC0011021ul // ICache Config - F15 Shared
+#define MSR_DC_CFG 0xC0011022ul
+#define MSR_ME_CFG 0xC0011029ul
+#define MSR_BU_CFG 0xC0011023ul
+#define MSR_CU_CFG 0xC0011023ul // F15 Shared
+#define MSR_DE_CFG 0xC0011029ul // F15 Shared
+#define MSR_BU_CFG2 0xC001102Aul
+#define MSR_CU_CFG2 0xC001102Aul // F15 Shared
+#define MSR_BU_CFG3 0xC001102Bul
+#define MSR_CU_CFG3 0xC001102Bul // F15 Shared
+#define MSR_LS_CFG2 0xC001102Dul
+#define MSR_CU_PFTCFG 0xC001102Ful
+#define MSR_IBS_OP_DATA3 0xC0011037ul
+#define MSR_C001_1070 0xC0011070ul // F15 Shared
+
+
+#define MSR_CPUID_NAME_STRING0 0xC0010030ul // First CPUID namestring register
+#define MSR_CPUID_NAME_STRING1 0xC0010031ul
+#define MSR_CPUID_NAME_STRING2 0XC0010032ul
+#define MSR_CPUID_NAME_STRING3 0xC0010033ul
+#define MSR_CPUID_NAME_STRING4 0xC0010034ul
+#define MSR_CPUID_NAME_STRING5 0xC0010035ul // Last CPUID namestring register
+#define MSR_MMIO_Cfg_Base 0xC0010058ul // MMIO Configuration Base Address Register
+#define MSR_BIST 0xC0010060ul // BIST Results register
+#define MSR_OSVW_ID_Length 0xC0010140ul
+#define MSR_OSVW_Status 0xC0010141ul
+#define MSR_NB_PERF_CTL0 0xC0010240ul
+#define MSR_NB_PERF_CTR0 0xC0010241ul
+#define MSR_NB_PERF_CTL1 0xC0010242ul
+#define MSR_NB_PERF_CTR1 0xC0010243ul
+#define MSR_NB_PERF_CTL2 0xC0010244ul
+#define MSR_NB_PERF_CTR2 0xC0010245ul
+#define MSR_NB_PERF_CTL3 0xC0010246ul
+#define MSR_NB_PERF_CTR3 0xC0010247ul
+#define CU_SPMCTL 0xC0010281ul // Streaming Performance Monitor Control
+#define MSR_PERF_CONTROL3 0xC0010003ul // Performance control register number 3
+#define MSR_PERF_COUNTER3 0xC0010007ul // Performance counter register number 3
+#define PERF_RESERVE_BIT_MASK 0x030FFFDFFFFFull // Mask of the Performance control Reserve bits
+#define PERF_CAR_CORRUPTION_EVENT 0x040040F0E2ul // Configure the controller to capture the
+ // CAR Corruption
+// FUNC_0 registers
+// ----------------
+#define LINK_INIT_CTRL 0x6C
+#define LINK_INIT_CTRL_REQ_DIS 0x02 // [1] = ReqDis
+#define LINK_INIT_COLD_RST_DET BIT4
+#define LINK_INIT_BIOS_RST_DET_0 BIT5
+#define LINK_INIT_BIOS_RST_DET_1 BIT9
+#define LINK_INIT_BIOS_RST_DET_2 BIT10
+#define LINK_INIT_BIOS_RST_DET BIT9 | BIT10
+#define EXTENDED_NODE_ID 0x160
+
+#define CORE_CTRL 0x1DC
+#define CORE_CTRL_CORE1_EN 0x00000002ul
+#define CORE_CTRL_CORE2_EN 0x00000004ul
+#define CORE_CTRL_CORE3_EN 0x00000008ul
+#define CORE_CTRL_CORE4_EN 0x00000010ul
+#define CORE_CTRL_CORE5_EN 0x00000020ul
+#define CORE_CTRL_CORE6_EN 0x00000040ul
+#define CORE_CTRL_CORE7_EN 0x00000080ul
+#define CORE_CTRL_CORE8_EN 0x00000100ul
+#define CORE_CTRL_CORE9_EN 0x00000200ul
+
+// FUNC_3 registers
+// ----------------
+#define HARDWARE_THERMAL_CTRL_REG 0x64
+#define SOFTWARE_THERMAL_CTRL_REG 0x68
+
+#define ACPI_PSC_0_REG 0x80 // ACPI Power State Control Registers
+#define ACPI_PSC_4_REG 0x84
+
+#define NB_CFG_HIGH_REG 0x8C
+#define POWER_CTRL_MISCELLANEOUS_REG 0xA0
+#define CLOCK_POWER_TIMING_CTRL2_REG 0xDC
+#define NORTH_BRIDGE_CAPABILITIES_REG 0xE8
+#define MULTI_NODE_CPU 29
+#define CPUID_FMR 0xFC // Family / Model registers
+#define DOWNCORE_CTRL 0x190 // Downcore Control Register
+
+#define LINK_TO_XCS_TOKEN_COUNT_REG_3X148 0x148
+#define REG_HT4_PHY_OFFSET_BASE_4X180 0x180
+#define REG_HT4_PHY_DATA_PORT_BASE_4X184 0x184
+
+// FUNC_4 registers
+// ----------------
+/* Native Die CPUID Register F4x160 */
+#define NATIVE_DIE_CPUID_REG 0x160
+#define NATIVE_DIE_CPUID_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_4, NATIVE_DIE_CPUID_REG))
+
+/// Native Die CPUID PCI Register
+typedef struct {
+ UINT32 Stepping:4; ///< Stepping
+ UINT32 BaseModel:4; ///< Base Model
+ UINT32 BaseFamily:4; ///< Base Family
+ UINT32 :4; ///< Reserved
+ UINT32 ExtModel:4; ///< Extended Model
+ UINT32 ExtFamily:8; ///< Extended Family
+ UINT32 :4; ///< Reserved
+} NATIVE_DIE_CPUID_REGISTER;
+
+// FUNC_5 registers
+// ----------------
+#define COMPUTE_UNIT_STATUS 0x80
+#define NORTH_BRIDGE_CAPABILITIES_2_REG 0x84
+
+
+// Misc. defines.
+#define PCI_DEV_BASE 24
+
+#define CPUID_STEPPING_MASK 0x0000000Ful
+#define CPUID_BASE_MODEL_MASK 0x000000F0ul
+#define CPUID_BASE_FAMILY_MASK 0x00000F00ul
+#define CPUID_EXT_MODEL_MASK 0x000F0000ul
+#define CPUID_EXT_FAMILY_MASK 0x0FF00000ul
+
+#define TN_SOCKET_FP2 0
+#define TN_SOCKET_FS1 1
+#define TN_SOCKET_FM2 2
+#define KV_SOCKET_FP3 0
+#define KV_SOCKET_FM2r2 1
+#define SOCKET_IGNORE 0xF
+
+#define LAPIC_BASE_ADDR_MASK 0x0000FFFFFFFFF000ull
+#define APIC_EXT_BRDCST_MASK 0x000E0000ul
+#define APIC_ENABLE_BIT 0x00000800ul
+#define LOCAL_APIC_ADDR 0xFEE00000ul
+#define INT_CMD_REG_LO 0x300
+#define INT_CMD_REG_HI 0x310
+#define REMOTE_MSG_REG 0x380
+#define REMOTE_READ_REG 0xC0
+#define APIC_ID_REG 0x20
+#define APIC20_ApicId 24
+#define CMD_REG_TO_READ_DATA 0x338
+
+#define MAX_CORE_ID_SIZE 8
+#define MAX_CORE_ID_MASK ((1 << MAX_CORE_ID_SIZE) - 1)
+
+/*-------------------------
+ * Default definitions
+ *-------------------------
+ */
+#define DOWNCORE_MASK_SINGLE 0xFFFFFFFEul
+#define DOWNCORE_MASK_DUAL 0xFFFFFFFCul
+#define DOWNCORE_MASK_TRI 0xFFFFFFF8ul
+#define DOWNCORE_MASK_FOUR 0xFFFFFFF0ul
+#define DOWNCORE_MASK_FIVE 0xFFFFFFE0ul
+#define DOWNCORE_MASK_SIX 0xFFFFFFC0ul
+#define DOWNCORE_MASK_SEVEN 0xFFFFFF80ul
+#define DOWNCORE_MASK_EIGHT 0xFFFFFF00ul
+#define DOWNCORE_MASK_TEN 0xFFFFFC00ul
+#define DOWNCORE_MASK_TWELVE 0xFFFFF000ul
+#define DOWNCORE_MASK_FOURTEEN 0xFFFFC000ul
+#define DOWNCORE_MASK_DUAL_COMPUTE_UNIT 0xFFFFFFFAul
+#define DOWNCORE_MASK_TRI_COMPUTE_UNIT 0xFFFFFFEAul
+#define DOWNCORE_MASK_FOUR_COMPUTE_UNIT 0xFFFFFFAAul
+#define DOWNCORE_MASK_FIVE_COMPUTE_UNIT 0xFFFFFEAAul
+#define DOWNCORE_MASK_SIX_COMPUTE_UNIT 0xFFFFFAAAul
+#define DOWNCORE_MASK_SEVEN_COMPUTE_UNIT 0xFFFFEAAAul
+#define DOWNCORE_MASK_EIGHT_COMPUTE_UNIT 0xFFFFAAAAul
+
+#define DELIVERY_STATUS BIT13
+#define REMOTE_READ_STAT_MASK 0x00030000ul
+#define REMOTE_DELIVERY_PENDING 0x00010000ul
+#define REMOTE_DELIVERY_DONE 0x00020000ul
+
+/*
+ * --------------------------------------------------------------------------------------
+ *
+ * D E F I N E S / T Y P E D E F S / S T R U C T U R E S
+ *
+ * --------------------------------------------------------------------------------------
+ */
+
+/// CpuEarly param type
+typedef struct {
+ IN UINT8 MemInitPState; ///< Pstate value during memory initial
+ IN PLATFORM_CONFIGURATION PlatformConfig; ///< Runtime configurable user options
+} AMD_CPU_EARLY_PARAMS;
+
+/// CPUID
+typedef enum {
+ REG_EAX, ///< EAX
+ REG_EBX, ///< EBX
+ REG_ECX, ///< ECX
+ REG_EDX ///< EDX
+} CPUID_REG;
+
+#endif // _CPU_REGISTERS_H_
+
diff --git a/src/vendorcode/amd/pi/00630F01/Proc/CPU/heapManager.h b/src/vendorcode/amd/pi/00630F01/Proc/CPU/heapManager.h
new file mode 100644
index 0000000..7a68ed5
--- /dev/null
+++ b/src/vendorcode/amd/pi/00630F01/Proc/CPU/heapManager.h
@@ -0,0 +1,258 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD Heap Manager and Heap Allocation APIs, and related functions.
+ *
+ * Contains code that initialize, maintain, and allocate the heap space.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: CPU
+ * @e \$Revision: 296129 $ @e \$Date: 2014-06-23 09:45:14 -0500 (Mon, 23 Jun 2014) $
+ *
+ */
+/*
+ ******************************************************************************
+ *
+ * Copyright 2008 - 2014 ADVANCED MICRO DEVICES, INC. All Rights Reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ ******************************************************************************
+ */
+
+#ifndef _HEAP_MANAGER_H_
+#define _HEAP_MANAGER_H_
+
+/*---------------------------------------------------------------------------------------
+ * M I X E D (Definitions And Macros / Typedefs, Structures, Enums)
+ *---------------------------------------------------------------------------------------
+ */
+
+
+/*---------------------------------------------------------------------------------------
+ * D E F I N I T I O N S A N D M A C R O S
+ *---------------------------------------------------------------------------------------
+ */
+#define AMD_MTRR_VARIABLE_BASE0 0x200
+#define AMD_MTRR_VARIABLE_HEAP_BASE 0x20A
+#define AMD_MTRR_VARIABLE_HEAP_MASK (AMD_MTRR_VARIABLE_HEAP_BASE + 1)
+
+#define AMD_HEAP_START_ADDRESS 0x400000ul
+#define AMD_HEAP_REGION_END_ADDRESS 0xBFFFFFul
+#define AMD_HEAP_SIZE_PER_CORE 0x010000ul
+#define AMD_HEAP_INVALID_HEAP_OFFSET 0xFFFFFFFFul
+#define AMD_HEAP_MTRR_MASK ((0xFFFFFFFFFFFFF800ull & (((UINT64)AMD_HEAP_SIZE_PER_CORE ^ (-1)) + 1)) | 0x800)
+#define AMD_HEAP_SIZE_DWORD_PER_CORE (AMD_HEAP_SIZE_PER_CORE / 4)
+
+#define AMD_TEMP_TOM 0x20000000ul // Set TOM to 512 MB (temporary value)
+#define AMD_VAR_MTRR_ENABLE_BIT 0x100000ul // bit 20
+
+#define AMD_HEAP_RAM_ADDRESS 0xB0000ul
+
+#define HEAP_SIGNATURE_VALID 0x50414548ul // Signature: 'HEAP'
+#define HEAP_SIGNATURE_INVALID 0x00000000ul // Signature cleared
+
+///Heap Manager Life cycle
+#define HEAP_DO_NOT_EXIST_YET 1
+#define HEAP_LOCAL_CACHE 2
+#define HEAP_TEMP_MEM 3
+#define HEAP_SYSTEM_MEM 4
+#define HEAP_DO_NOT_EXIST_ANYMORE 5
+#define HEAP_S3_RESUME 6
+#define HEAP_RUNTIME_SYSTEM_MEM 7
+
+///Heap callout
+#define HEAP_CALLOUT_BOOTTIME 0
+#define HEAP_CALLOUT_RUNTIME 1
+
+#define AMD_MTRR_FIX64k_00000 0x250
+#define AMD_MTRR_FIX16k_80000 0x258
+#define AMD_MTRR_FIX16k_A0000 0x259
+#define AMD_MTRR_FIX4k_C0000 0x268
+#define AMD_MTRR_FIX4k_C8000 0x269
+#define AMD_MTRR_FIX4k_D0000 0x26A
+#define AMD_MTRR_FIX4k_D8000 0x26B
+#define AMD_MTRR_FIX4k_E0000 0x26C
+#define AMD_MTRR_FIX4k_E8000 0x26D
+#define AMD_MTRR_FIX4k_F0000 0x26E
+#define AMD_MTRR_FIX4k_F8000 0x26F
+
+#define AMD_MTRR_FIX64K_WB_DRAM 0x1E
+#define AMD_MTRR_FIX64K_WT_DRAM 0x1C
+#define AMD_MTRR_FIX64K_UC_DRAM 0x18
+#define AMD_MTRR_FIX16K_WB_DRAM 0x1E1E1E1E1E1E1E1Eull
+#define AMD_MTRR_FIX16K_WT_DRAM 0x1C1C1C1C1C1C1C1Cull
+#define AMD_MTRR_FIX16K_UC_DRAM 0x1818181818181818ull
+#define AMD_MTRR_FIX4K_WB_DRAM 0x1E1E1E1E1E1E1E1Eull
+#define AMD_MTRR_FIX4K_WT_DRAM 0x1C1C1C1C1C1C1C1Cull
+#define AMD_MTRR_FIX4K_UC_DRAM 0x1818181818181818ull
+
+/*---------------------------------------------------------------------------------------
+ * T Y P E D E F S, S T R U C T U R E S, E N U M S
+ *---------------------------------------------------------------------------------------
+ */
+/// Allocate Heap Parameters
+typedef struct _ALLOCATE_HEAP_PARAMS {
+ UINT32 RequestedBufferSize; ///< Size of buffer.
+ UINT32 BufferHandle; ///< An unique ID of buffer.
+ UINT8 Persist; ///< A flag. If marked, to be stored and passed to AmdInitLate.
+ UINT8 *BufferPtr; ///< Pointer to buffer.
+} ALLOCATE_HEAP_PARAMS;
+
+/// Locate Heap Parameters
+typedef struct _LOCATE_HEAP_PTR {
+ UINT32 BufferHandle; ///< An unique ID of buffer.
+ UINT32 BufferSize; ///< Data buffer size.
+ UINT8 *BufferPtr; ///< Pointer to buffer.
+} LOCATE_HEAP_PTR;
+
+/// Heap Node Header
+typedef struct _BUFFER_NODE {
+ UINT32 BufferHandle; ///< An unique ID of buffer.
+ UINT32 BufferSize; ///< Size of buffer.
+ UINT8 Persist; ///< A flag. If marked, to be stored and passed to AmdInitLate.
+ UINT8 PadSize; ///< Size of pad.
+ UINT32 OffsetOfNextNode; ///< Offset of next node (relative to the base).
+} BUFFER_NODE;
+
+/// Heap Manager
+typedef struct _HEAP_MANAGER {
+ UINT32 Signature; ///< a signature to indicate if the heap is valid.
+ UINT32 UsedSize; ///< Used size of heap.
+ UINT32 FirstActiveBufferOffset; ///< Offset of the first active buffer.
+ UINT32 FirstFreeSpaceOffset; ///< Offset of the first free space.
+} HEAP_MANAGER;
+
+/// AGESA Buffer Handles (These are reserved)
+typedef enum {
+ AMD_INIT_RESET_HANDLE = 0x000A000, ///< Assign 0x000A000 buffer handle to AmdInitReset routine.
+ AMD_INIT_EARLY_HANDLE, ///< Assign 0x000A001 buffer handle to AmdInitEarly routine.
+ AMD_INIT_POST_HANDLE, ///< Assign 0x000A002 buffer handle to AmdInitPost routine.
+ AMD_INIT_ENV_HANDLE, ///< Assign 0x000A003 buffer handle to AmdInitEnv routine.
+ AMD_INIT_MID_HANDLE, ///< Assign 0x000A004 buffer handle to AmdInitMid routine.
+ AMD_INIT_LATE_HANDLE, ///< Assign 0x000A005 buffer handle to AmdInitLate routine.
+ AMD_INIT_RESUME_HANDLE, ///< Assign 0x000A006 buffer handle to AmdInitResume routine.
+ AMD_LATE_RUN_AP_TASK_HANDLE, ///< Assign 0x000A007 buffer handle to AmdLateRunApTask routine.
+ AMD_S3_SAVE_HANDLE, ///< Assign 0x000A008 buffer handle to AmdS3Save routine.
+ AMD_S3_LATE_RESTORE_HANDLE, ///< Assign 0x000A009 buffer handle to AmdS3LateRestore routine.
+ AMD_S3_SCRIPT_SAVE_TABLE_HANDLE, ///< Assign 0x000A00A buffer handle to be used for S3 save table
+ AMD_S3_SCRIPT_TEMP_BUFFER_HANDLE, ///< Assign 0x000A00B buffer handle to be used for S3 save table
+ AMD_CPU_AP_TASKING_HANDLE, ///< Assign 0x000A00C buffer handle to AP tasking input parameters.
+ AMD_REC_MEM_SOCKET_HANDLE, ///< Assign 0x000A00D buffer handle to save socket with memory in memory recovery mode.
+ AMD_MEM_AUTO_HANDLE, ///< Assign 0x000A00E buffer handle to AmdMemAuto routine.
+ AMD_MEM_SPD_HANDLE, ///< Assign 0x000A00F buffer handle to AmdMemSpd routine.
+ AMD_MEM_DATA_HANDLE, ///< Assign 0x000A010 buffer handle to MemData
+ AMD_MEM_TRAIN_BUFFER_HANDLE, ///< Assign 0x000A011 buffer handle to allocate buffer for training
+ AMD_MEM_S3_DATA_HANDLE, ///< Assign 0x000A012 buffer handle to special case register for S3
+ AMD_MEM_S3_NB_HANDLE, ///< Assign 0x000A013 buffer handle to NB block for S3
+ AMD_MEM_S3_MR0_DATA_HANDLE, ///< Assign 0x000A014 buffer handle to MR0 data block for S3
+ AMD_UMA_INFO_HANDLE, ///< Assign 0x000A015 buffer handle to be used for Uma information
+ AMD_DMI_MEM_DEV_INFO_HANDLE, ///< Assign 0x000A016 buffer handle to DMI Type16 17 19 20 information
+ EVENT_LOG_BUFFER_HANDLE, ///< Assign 0x000A017 buffer handle to Event Log
+ IDS_CONTROL_HANDLE, ///< Assign 0x000A018 buffer handle to AmdIds routine.
+ IDS_HDT_OUT_BUFFER_HANDLE, ///< Assign 0x000A019 buffer handle to be used for HDTOUT support.
+ IDS_CHECK_POINT_PERF_HANDLE, ///< Assign 0x000A01A buffer handle to Performance analysis
+ AMD_PCIE_COMPLEX_DATA_HANDLE, ///< Assign 0x000A01B buffer handle to be used for PCIe support
+ AMD_MEM_SYS_DATA_HANDLE, ///< Assign 0x000A01C buffer handle to be used for memory data structure
+ AMD_GNB_SMU_CONFIG_HANDLE, ///< Assign 0x000A01D buffer handle to be used for GNB SMU configuration
+ AMD_PP_FUSE_TABLE_HANDLE, ///< Assign 0x000A01E buffer handle to be used for TT fuse table
+ AMD_GFX_PLATFORM_CONFIG_HANDLE, ///< Assign 0x000A01F buffer handle to be used for Gfx platform configuration
+ AMD_GNB_TEMP_DATA_HANDLE, ///< Assign 0x000A020 buffer handle for GNB general purpose data block
+ AMD_MEM_2D_RDQS_HANDLE, ///< Assign 0x000A021 buffer handle for 2D training
+ AMD_MEM_2D_RD_WR_HANDLE, ///< Assign 0x000A022 buffer handle for 2D Read/Write training
+ AMD_GNB_IOMMU_SCRATCH_MEM_HANDLE, ///< Assign 0x000A023 buffer handle to be used for GNB IOMMU scratch memory
+ AMD_MEM_S3_SAVE_HANDLE, ///< Assign 0x000A024 buffer handle for memory data saved right after memory init
+ AMD_MEM_2D_RDQS_RIM_HANDLE, ///< Assign 0x000A025 buffer handle for 2D training Eye RIM Search
+ AMD_MEM_2D_RD_WR_RIM_HANDLE, ///< Assign 0x000A026 buffer handle for 2D Read/Write training Eye RIM Search
+ AMD_CPU_NB_PSTATE_FIXUP_HANDLE, ///< Assign 0x000A027 buffer handle for an NB P-state workaround
+ AMD_MEM_CRAT_INFO_BUFFER_HANDLE, ///< Assign 0x000A028 buffer handle for CRAT Memory affinity component structure
+ AMD_SKIP_MEM_S3_SAVE, ///< Assign 0x000A029 buffer handle for the flag to skip memory S3 save
+ AMD_SCS_SMU_RAM_INFO, ///< Assign 0x000A02A buffer handle for keeping the result of SMU SCS service
+ AMD_SCS_HWP0_FREQ, ///< Assign 0x000A02B buffer handler for keeping frequency of HWP0
+ AMD_IS_FEATURE_ENABLED, ///< Assign 0x000A02C buffer handle for keeping the result of IsFeatureEnabled
+ AMD_MEM_DATAEYE_WORK_AREA_HANDLE, ///< Assign 0x000A02D buffer handle for Composite Data Eye Compression Work Area
+ AMD_GNB_SAMU_PATCH_HANDLE, ///< Assign 0x000A02E buffer handle for Samu patch buffer
+ AMD_GNB_SAMU_BOOT_CONTROL_HANDLE, ///< Assign 0x000A02F buffer handle for Samu boot control buffer
+ AMD_GNB_ACP_ENGINE_HANDLE, ///< Assign 0x000A030 buffer handle for GNB ACP engine buffer
+ AMD_MEM_PMU_SRAM_MSG_BLOCK_HANDLE, ///< Assign 0x000A031 buffer handle for PMU SRAM Message Block buffer
+ AMD_GNB_SMU_TABLE_HANDLE, ///< Assign 0x000A032 buffer handle for GNB SMU table buffer
+ AMD_GNB_CRAT_HSA_TABLE_HANDLE, ///< Assign 0x000A033 buffer handle for GNB CRAT HSA unit table
+ AMD_GNB_BUILD_OPTIONS_HANDLE, ///< Assign 0x000A034 buffer handle for GNB build options
+ AMD_S3_FINAL_RESTORE_HANDLE, ///< Assign 0x000A035 buffer handle to AmdS3FinalRestore routine.
+ AMD_MEM_MISC_HANDLES_START = 0x1000000, ///< Reserve 0x1000000 to 0x1FFFFFF buffer handle
+ AMD_MEM_MISC_HANDLES_END = 0x1FFFFFF, ///< miscellaneous memory init tasks' buffers.
+ AMD_HEAP_IN_MAIN_MEMORY_HANDLE = 0x8000000, ///< Assign 0x8000000 to AMD_HEAP_IN_MAIN_MEMORY_HANDLE.
+ SOCKET_DIE_MAP_HANDLE = 0x534F4B54, ///< 'sokt'
+ NODE_ID_MAP_HANDLE = 0x4E4F4445, ///< 'node'
+ HOP_COUNT_TABLE_HANDLE = 0x484F5053, ///< 'hops'
+ AMD_FCH_RESET_DATA_BLOCK_HANDLE = 0x46434852, ///< 'FCHR' Buffer handle for FCH private data block at InitReset
+ AMD_FCH_DATA_BLOCK_HANDLE = 0x46434845, ///< 'FCHE' Buffer handle for FCH private data block at InitEnv
+ IDS_TRAP_TABLE_HANDLE = 0x49524547, ///< 'IREG' Handle for IDS register table
+ IDS_SAVE_IDTR_HANDLE = 0x49445452, ///< 'IDTR'
+ IDS_BSC_IDT_HANDLE = 0x42534349, ///< 'BSCI' BSC Idt table
+ IDS_NV_TO_CMOS_HANDLE = 0x534D4349, ///< 'ICMS' Handle for IDS CMOS save
+ IDS_GRA_HANDLE = 0x41524749, ///< 'IGRA' Handle for IDS GRA save
+ IDS_EXTEND_HANDLE = 0x54584549, ///< 'IEXT' Handle for IDS extend module
+ IDS_TEMP_DATA_HANDLE = 0x504D5459, ///< 'ITMP' Handle for IDS temp data
+} AGESA_BUFFER_HANDLE;
+
+
+/*---------------------------------------------------------------------------------------
+ * F U N C T I O N P R O T O T Y P E
+ *---------------------------------------------------------------------------------------
+ */
+
+AGESA_STATUS
+HeapManagerInit (
+ IN AMD_CONFIG_PARAMS *StdHeader
+ );
+
+AGESA_STATUS
+HeapAllocateBuffer (
+ IN OUT ALLOCATE_HEAP_PARAMS *AllocateHeapParams,
+ IN OUT AMD_CONFIG_PARAMS *StdHeader
+ );
+
+AGESA_STATUS
+HeapDeallocateBuffer (
+ IN UINT32 BufferHandle,
+ IN AMD_CONFIG_PARAMS *StdHeader
+ );
+
+AGESA_STATUS
+HeapLocateBuffer (
+ IN OUT LOCATE_HEAP_PTR *LocateHeap,
+ IN AMD_CONFIG_PARAMS *StdHeader
+ );
+
+UINT64
+HeapGetBaseAddress (
+ IN AMD_CONFIG_PARAMS *StdHeader
+ );
+
+AGESA_STATUS
+EventLogInitialization (
+ IN AMD_CONFIG_PARAMS *StdHeader
+ );
+#endif // _HEAP_MANAGER_H_
diff --git a/src/vendorcode/amd/pi/00630F01/Proc/Common/AmdFch.h b/src/vendorcode/amd/pi/00630F01/Proc/Common/AmdFch.h
new file mode 100644
index 0000000..469d5af
--- /dev/null
+++ b/src/vendorcode/amd/pi/00630F01/Proc/Common/AmdFch.h
@@ -0,0 +1,65 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD FCH Component
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: FCH
+ * @e \$Revision: 281181 $ @e \$Date: 2013-12-18 02:18:55 -0600 (Wed, 18 Dec 2013) $
+ *
+ */
+/*
+*****************************************************************************
+*
+ * Copyright (c) 2008 - 2014, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+* ***************************************************************************
+*
+*/
+
+#ifndef _AMD_FCH_H_
+#define _AMD_FCH_H_
+
+typedef AGESA_STATUS FCH_INIT (IN VOID *DataPtr);
+typedef VOID FCH_TASK_ENTRY (IN VOID *FchCfg);
+
+
+/// FCH API build options
+typedef struct {
+ FCH_INIT *InitReset; ///< InitReset
+ FCH_INIT *InitResetConstructor; ///< InitResetConstructor
+ FCH_INIT *InitEnv; ///< InitEnv
+ FCH_INIT *InitEnvConstructor; ///< InitEnvConstructor
+ FCH_INIT *InitMid; ///< InitMid
+ FCH_INIT *InitMidConstructor; ///< InitMidConstructor
+ FCH_INIT *InitLate; ///< InitLate
+ FCH_INIT *InitLateConstructor; ///< InitLateConstructor
+} BLDOPT_FCH_FUNCTION;
+
+#endif
diff --git a/src/vendorcode/amd/pi/00630F01/Proc/Fch/Common/AcpiLib.h b/src/vendorcode/amd/pi/00630F01/Proc/Fch/Common/AcpiLib.h
new file mode 100644
index 0000000..d18fb12
--- /dev/null
+++ b/src/vendorcode/amd/pi/00630F01/Proc/Fch/Common/AcpiLib.h
@@ -0,0 +1,91 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * FCH ACPI lib
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: FCH
+ * @e \$Revision: 281181 $ @e \$Date: 2013-12-18 02:18:55 -0600 (Wed, 18 Dec 2013) $
+ *
+ */
+/*
+*****************************************************************************
+*
+ * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+****************************************************************************
+*/
+#ifndef _FCH_ACPILIB_H_
+#define _FCH_ACPILIB_H_
+///
+/// RSDP - ACPI 2.0 table RSDP
+///
+typedef struct _RSDP_HEADER {
+ UINT64 Signature; ///< RSDP signature "RSD PTR"
+ UINT8 CheckSum; ///< checksum of the first 20 bytes
+ UINT8 OEMID[6]; ///< OEM ID
+ UINT8 Revision; ///< 0 for APCI 1.0, 2 for ACPI 2.0
+ UINT32 RsdtAddress; ///< physical address of RSDT
+ UINT32 Length; ///< total length of RSDP (including extended part)
+ UINT64 XsdtAddress; ///< physical address of XSDT
+ UINT8 ExtendedCheckSum; ///< chechsum of whole table
+ UINT8 Reserved[3]; ///< Reserved
+} RSDP_HEADER;
+
+///
+/// DESCRIPTION_HEADER - ACPI common table header
+///
+typedef struct _DESCRIPTION_HEADER {
+ UINT32 Signature; ///< ACPI signature (4 ASCII characters)
+ UINT32 Length; ///< Length of table, in bytes, including header
+ UINT8 Revision; ///< ACPI Specification minor version #
+ UINT8 CheckSum; ///< To make sum of entire table == 0
+ UINT8 OemId[6]; ///< OEM identification
+ UINT8 OemTableId[8]; ///< OEM table identification
+ UINT32 OemRevision; ///< OEM revision number
+ UINT32 CreatorId; ///< ASL compiler vendor ID
+ UINT32 CreatorRevision; ///< ASL compiler revision number
+} DESCRIPTION_HEADER;
+
+///
+/// _AcpiRegWrite - ACPI MMIO register R/W structure
+///
+typedef struct _ACPI_REG_WRITE {
+ UINT8 MmioBase; /// MmioBase: Index of Fch block (For instance GPIO_BASE:0x01 SMI_BASE:0x02)
+ UINT8 MmioReg; /// MmioReg : Register index
+ UINT8 DataAndMask; /// DataANDMask : AND Register Data
+ UINT8 DataOrMask; /// DataOrMask : Or Register Data
+} ACPI_REG_WRITE;
+
+VOID* AcpiLocateTable (IN UINT32 Signature);
+VOID AcpiSetTableCheckSum (IN VOID *TablePtr);
+UINT8 AcpiGetTableCheckSum (IN VOID *TablePtr);
+UINT8 GetByteSum (IN VOID *DataPtr, IN UINT32 Length);
+
+#endif
diff --git a/src/vendorcode/amd/pi/00630F01/Proc/Fch/Common/FchBiosRamUsage.h b/src/vendorcode/amd/pi/00630F01/Proc/Fch/Common/FchBiosRamUsage.h
new file mode 100644
index 0000000..82dd750
--- /dev/null
+++ b/src/vendorcode/amd/pi/00630F01/Proc/Fch/Common/FchBiosRamUsage.h
@@ -0,0 +1,67 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * FCH BIOS Ram usage
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: FCH
+ * @e \$Revision: 281181 $ @e \$Date: 2013-12-18 02:18:55 -0600 (Wed, 18 Dec 2013) $
+ *
+ */
+/*
+*****************************************************************************
+*
+ * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+****************************************************************************
+*/
+#ifndef _FCH_BIOS_RAM_USAGE_H_
+#define _FCH_BIOS_RAM_USAGE_H_
+
+#define RESTORE_MEMORY_CONTROLLER_START 0
+#define XHCI_REGISTER_BAR00 0xD0
+#define XHCI_REGISTER_BAR01 0xD1
+#define XHCI_REGISTER_BAR02 0xD2
+#define XHCI_REGISTER_BAR03 0xD3
+#define XHCI_REGISTER_04H 0xD4
+#define XHCI_REGISTER_0CH 0xD5
+#define XHCI_REGISTER_3CH 0xD6
+#define XHCI1_REGISTER_BAR00 0xE0
+#define XHCI1_REGISTER_BAR01 0xE1
+#define XHCI1_REGISTER_BAR02 0xE2
+#define XHCI1_REGISTER_BAR03 0xE3
+#define XHCI1_REGISTER_04H 0xE4
+#define XHCI1_REGISTER_0CH 0xE5
+#define XHCI1_REGISTER_3CH 0xE6
+#define RTC_WORKAROUND_DATA_START 0xF0
+#define BOOT_TIME_FLAG_SEC 0xF8
+#define BOOT_TIME_FLAG_INT19 0xFC
+
+#endif
+
diff --git a/src/vendorcode/amd/pi/00630F01/Proc/Fch/Common/FchCommonCfg.h b/src/vendorcode/amd/pi/00630F01/Proc/Fch/Common/FchCommonCfg.h
new file mode 100644
index 0000000..39a11ba
--- /dev/null
+++ b/src/vendorcode/amd/pi/00630F01/Proc/Fch/Common/FchCommonCfg.h
@@ -0,0 +1,1282 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * FCH Function Support Definition
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: FCH
+ * @e \$Revision: 302381 $ @e \$Date: 2014-08-29 16:59:06 -0500 (Fri, 29 Aug 2014) $
+ *
+ */
+/*********************************************************************************
+ *
+ * Copyright 2008 - 2014 ADVANCED MICRO DEVICES, INC. All Rights Reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *********************************************************************************/
+#ifndef _FCH_COMMON_CFG_H_
+#define _FCH_COMMON_CFG_H_
+
+#pragma pack (push, 1)
+
+//-----------------------------------------------------------------------------
+// FCH DEFINITIONS AND MACROS
+//-----------------------------------------------------------------------------
+
+//
+// FCH Component Data Structure Definitions
+//
+
+/// PCI_ADDRESS - PCI access structure
+#define PCI_ADDRESS(bus, dev, func, reg) \
+ (UINT32) ( (((UINT32)bus) << 24) + (((UINT32)dev) << 19) + (((UINT32)func) << 16) + ((UINT32)reg) )
+
+#define CPUID_FMF 0x80000001ul // Family Model Features information
+///
+/// - Byte Register R/W structure
+///
+typedef struct _REG8_MASK {
+ UINT8 RegIndex; /// RegIndex - Reserved
+ UINT8 AndMask; /// AndMask - Reserved
+ UINT8 OrMask; /// OrMask - Reserved
+} REG8_MASK;
+
+
+///
+/// PCIE Reset Block
+///
+typedef enum {
+ NbBlock, ///< Reset for NB PCIE
+ FchBlock ///< Reset for FCH GPP
+} RESET_BLOCK;
+
+///
+/// PCIE Reset Operation
+///
+typedef enum {
+ DeassertReset, ///< DeassertRese - Deassert reset
+ AssertReset ///< AssertReset - Assert reset
+} RESET_OP;
+
+
+///
+/// SD structure
+///
+typedef struct {
+ SD_MODE SdConfig; ///< SD Mode configuration
+ /// @li <b>00</b> - Disabled
+ /// @li <b>00</b> - AMDA
+ /// @li <b>01</b> - DMA
+ /// @li <b>10</b> - PIO
+ ///
+ UINT8 SdSpeed; ///< SD Speed
+ /// @li <b>0</b> - Low speed
+ /// @li <b>1</b> - High speed
+ ///
+ UINT8 SdBitWidth; ///< SD Bit Width
+ /// @li <b>0</b> - 32BIT clear 23
+ /// @li <b>1</b> - 64BIT, set 23,default
+ ///
+ UINT32 SdSsid; ///< SD Subsystem ID
+ SD_CLOCK_CONTROL SdClockControl; ///< SD Clock Control
+ BOOLEAN SdClockMultiplier; ///< SD Clock Multiplier enable/disable
+ UINT8 SdReTuningMode; ///< SD Re-tuning modes select
+ /// @li <b>0</b> - mode 1
+ /// @li <b>1</b> - mode 2
+ /// @li <b>2</b> - mode 3
+ UINT8 SdHostControllerVersion; ///< SD controller Version
+ /// @li <b>1</b> - SD 2.0
+ /// @li <b>2</b> - SD 3.0
+ UINT8 SdrCapabilities; ///< SDR Capability mode select
+ /// @li <b>00</b> - SDR25/15
+ /// @li <b>01</b> - SDR50
+ /// @li <b>11</b> - SDR104
+ UINT8 SdSlotType; ///< SDR Slot Type select
+ /// @li <b>00</b> - Removable Card Slot
+ /// @li <b>01</b> - Embedded Slot for One Device
+ /// @li <b>10</b> - Shared Bus Slot
+} FCH_SD;
+
+///
+/// CODEC_ENTRY - Fch HD Audio OEM Codec structure
+///
+typedef struct _CODEC_ENTRY {
+ UINT8 Nid; /// Nid - Reserved
+ UINT32 Byte40; /// Byte40 - Reserved
+} CODEC_ENTRY;
+
+///
+/// CODEC_TBL_LIST - Fch HD Audio Codec table list
+///
+typedef struct _CODEC_TBL_LIST {
+ UINT32 CodecId; /// CodecID - Codec ID
+ CONST CODEC_ENTRY* CodecTablePtr; /// CodecTablePtr - Codec table pointer
+} CODEC_TBL_LIST;
+
+///
+/// AZALIA_PIN - HID Azalia or GPIO define structure.
+///
+typedef struct _AZALIA_PIN {
+ UINT8 AzaliaSdin0; ///< AzaliaSdin0
+ /// @par
+ /// @li <b>00</b> - GPIO PIN
+ /// @li <b>10</b> - As a Azalia SDIN pin
+
+ UINT8 AzaliaSdin1; ///< AzaliaSdin1
+ /// @par
+ /// SDIN1 is define at BIT2 & BIT3
+ /// @li <b>00</b> - GPIO PIN
+ /// @li <b>10</b> - As a Azalia SDIN pin
+
+ UINT8 AzaliaSdin2; ///< AzaliaSdin2
+ /// @par
+ /// SDIN2 is define at BIT4 & BIT5
+ /// @li <b>00</b> - GPIO PIN
+ /// @li <b>10</b> - As a Azalia SDIN pin
+
+ UINT8 AzaliaSdin3; ///< AzaliaSdin3
+ /// @par
+ /// SDIN3 is define at BIT6 & BIT7
+ /// @li <b>00</b> - GPIO PIN
+ /// @li <b>10</b> - As a Azalia SDIN pin
+} AZALIA_PIN;
+
+///
+/// Azalia structure
+///
+typedef struct {
+ HDA_CONFIG AzaliaEnable; ///< AzaliaEnable - Azalia function configuration
+ BOOLEAN AzaliaMsiEnable; ///< AzaliaMsiEnable - Azalia MSI capability
+ UINT32 AzaliaSsid; ///< AzaliaSsid - Azalia Subsystem ID
+ UINT8 AzaliaPinCfg; ///< AzaliaPinCfg - Azalia Controller SDIN pin Configuration
+ /// @par
+ /// @li <b>0</b> - disable
+ /// @li <b>1</b> - enable
+
+ UINT8 AzaliaFrontPanel; ///< AzaliaFrontPanel - Azalia Controller Front Panel Configuration
+ /// @par
+ /// Support Front Panel configuration
+ /// @li <b>0</b> - Auto
+ /// @li <b>1</b> - disable
+ /// @li <b>2</b> - enable
+
+ UINT8 FrontPanelDetected; ///< FrontPanelDetected - Force Azalia Controller Front Panel Configuration
+ /// @par
+ /// Force Front Panel configuration
+ /// @li <b>0</b> - Not Detected
+ /// @li <b>1</b> - Detected
+
+ UINT8 AzaliaSnoop; ///< AzaliaSnoop - Azalia Controller Snoop feature Configuration
+ /// @par
+ /// Azalia Controller Snoop feature Configuration
+ /// @li <b>0</b> - disable
+ /// @li <b>1</b> - enable
+
+ UINT8 AzaliaDummy; /// AzaliaDummy - Reserved */
+
+ AZALIA_PIN AzaliaConfig; /// AzaliaConfig - Azaliz Pin Configuration
+
+///
+/// AZOEMTBL - Azalia Controller OEM Codec Table Pointer
+///
+ CONST CODEC_TBL_LIST *AzaliaOemCodecTablePtr; /// AzaliaOemCodecTablePtr - Oem Azalia Codec Table Pointer
+
+///
+/// AZOEMFPTBL - Azalia Controller Front Panel OEM Table Pointer
+///
+ CONST VOID *AzaliaOemFpCodecTablePtr; /// AzaliaOemFpCodecTablePtr - Oem Front Panel Codec Table Pointer
+} FCH_AZALIA;
+
+///
+/// _SPI_DEVICE_PROFILE Spi Device Profile structure
+///
+typedef struct _SPI_DEVICE_PROFILE {
+ UINT32 JEDEC_ID; /// JEDEC ID
+ UINT32 RomSize; /// ROM Size
+ UINT32 SectorSize; /// Sector Size
+ UINT16 MaxNormalSpeed; /// Max Normal Speed
+ UINT16 MaxFastSpeed; /// Max Fast Speed
+ UINT16 MaxDualSpeed; /// Max Dual Speed
+ UINT16 MaxQuadSpeed; /// Max Quad Speed
+ UINT8 QeReadRegister; /// QE Read Register
+ UINT8 QeWriteRegister; /// QE Write Register
+ UINT8 QeOperateSize; /// QE Operate Size 1byte/2bytes
+ UINT16 QeLocation; // QE Location in the register
+} SPI_DEVICE_PROFILE;
+
+///
+/// _SPI_CONTROLLER_PROFILE Spi Device Profile structure
+///
+typedef struct _SPI_CONTROLLER_PROFILE {
+// UINT32 SPI_CONTROLLER_ID; /// SPI Controller ID
+ UINT16 FifoSize; /// FIFO Size
+ UINT16 MaxNormalSpeed; /// Max Normal Speed
+ UINT16 MaxFastSpeed; /// Max Fast Speed
+ UINT16 MaxDualSpeed; /// Max Dual Speed
+ UINT16 MaxQuadSpeed; /// Max Quad Speed
+} SPI_CONTROLLER_PROFILE;
+
+///
+/// SPI structure
+///
+typedef struct {
+ BOOLEAN LpcMsiEnable; ///< LPC MSI capability
+ UINT32 LpcSsid; ///< LPC Subsystem ID
+ UINT32 RomBaseAddress; ///< SpiRomBaseAddress
+ /// @par
+ /// SPI ROM BASE Address
+ ///
+ UINT8 SpiSpeed; ///< SpiSpeed - Spi Frequency
+ /// @par
+ /// SPI Speed [1.0] - the clock speed for non-fast read command
+ /// @li <b>00</b> - 66Mhz
+ /// @li <b>01</b> - 33Mhz
+ /// @li <b>10</b> - 22Mhz
+ /// @li <b>11</b> - 16.5Mhz
+ ///
+ UINT8 SpiFastSpeed; ///< FastSpeed - Spi Fast Speed feature
+ /// SPIFastSpeed [1.0] - the clock speed for Fast Speed Feature
+ /// @li <b>00</b> - 66Mhz
+ /// @li <b>01</b> - 33Mhz
+ /// @li <b>10</b> - 22Mhz
+ /// @li <b>11</b> - 16.5Mhz
+ ///
+ UINT8 WriteSpeed; ///< WriteSpeed - Spi Write Speed
+ /// @par
+ /// WriteSpeed [1.0] - the clock speed for Spi write command
+ /// @li <b>00</b> - 66Mhz
+ /// @li <b>01</b> - 33Mhz
+ /// @li <b>10</b> - 22Mhz
+ /// @li <b>11</b> - 16.5Mhz
+ ///
+ UINT8 SpiMode; ///< SpiMode - Spi Mode Setting
+ /// @par
+ /// @li <b>101</b> - Qual-io 1-4-4
+ /// @li <b>100</b> - Dual-io 1-2-2
+ /// @li <b>011</b> - Qual-io 1-1-4
+ /// @li <b>010</b> - Dual-io 1-1-2
+ /// @li <b>111</b> - FastRead
+ /// @li <b>110</b> - Normal
+ ///
+ UINT8 AutoMode; ///< AutoMode - Spi Auto Mode
+ /// @par
+ /// SPI Auto Mode
+ /// @li <b>0</b> - Disabled
+ /// @li <b>1</b> - Enabled
+ ///
+ UINT8 SpiBurstWrite; ///< SpiBurstWrite - Spi Burst Write Mode
+ /// @par
+ /// SPI Burst Write
+ /// @li <b>0</b> - Disabled
+ /// @li <b>1</b> - Enabled
+ BOOLEAN LpcClk0; ///< Lclk0En - LPCCLK0
+ /// @par
+ /// LPC Clock 0 mode
+ /// @li <b>0</b> - forced to stop
+ /// @li <b>1</b> - functioning with CLKRUN protocol
+ BOOLEAN LpcClk1; ///< Lclk1En - LPCCLK1
+ /// @par
+ /// LPC Clock 1 mode
+ /// @li <b>0</b> - forced to stop
+ /// @li <b>1</b> - functioning with CLKRUN protocol
+// UINT32 SPI100_RX_Timing_Config_Register_38; ///< SPI100_RX_Timing_Config_Register_38
+// UINT16 SPI100_RX_Timing_Config_Register_3C; ///< SPI100_RX_Timing_Config_Register_3C
+// UINT8 SpiProtectEn0_1d_34; ///
+ UINT8 SPI100_Enable; ///
+ SPI_DEVICE_PROFILE SpiDeviceProfile; /// Spi Device Profile
+} FCH_SPI;
+
+
+///
+/// IDE structure
+///
+typedef struct {
+ BOOLEAN IdeEnable; ///< IDE function switch
+ BOOLEAN IdeMsiEnable; ///< IDE MSI capability
+ UINT32 IdeSsid; ///< IDE controller Subsystem ID
+} FCH_IDE;
+
+///
+/// IR Structure
+///
+typedef struct {
+ IR_CONFIG IrConfig; ///< IrConfig
+ UINT8 IrPinControl; ///< IrPinControl
+} FCH_IR;
+
+
+///
+/// PCI Bridge Structure
+///
+typedef struct {
+ BOOLEAN PcibMsiEnable; ///< PCI-PCI Bridge MSI capability
+ UINT32 PcibSsid; ///< PCI-PCI Bridge Subsystem ID
+ UINT8 PciClks; ///< 33MHz PCICLK0/1/2/3 Enable, bits [0:3] used
+ /// @li <b>0</b> - disable
+ /// @li <b>1</b> - enable
+ ///
+ UINT16 PcibClkStopOverride; ///< PCIB_CLK_Stop Override
+ BOOLEAN PcibClockRun; ///< Enable the auto clkrun functionality
+ /// @li <b>0</b> - disable
+ /// @li <b>1</b> - enable
+ ///
+} FCH_PCIB;
+
+
+///
+/// - SATA Phy setting structure
+///
+typedef struct _SATA_PHY_SETTING {
+ UINT16 PhyCoreControlWord; /// PhyCoreControlWord - Reserved
+ UINT32 PhyFineTuneDword; /// PhyFineTuneDword - Reserved
+} SATA_PHY_SETTING;
+
+///
+/// SATA main setting structure
+///
+typedef struct _SATA_ST {
+ UINT8 SataModeReg; ///< SataModeReg - Sata Controller Mode
+ BOOLEAN SataEnable; ///< SataEnable - Sata Controller Function
+ /// @par
+ /// Sata Controller
+ /// @li <b>0</b> - disable
+ /// @li <b>1</b> - enable
+ ///
+ UINT8 Sata6AhciCap; ///< Sata6AhciCap - Reserved */
+ BOOLEAN SataSetMaxGen2; ///< SataSetMaxGen2 - Set Sata Max Gen2 mode
+ /// @par
+ /// Sata Controller Set to Max Gen2 mode
+ /// @li <b>0</b> - disable
+ /// @li <b>1</b> - enable
+ ///
+ BOOLEAN IdeEnable; ///< IdeEnable - Hidden IDE
+ /// @par
+ /// Sata IDE Controller Combined Mode
+ /// Enable - SATA controller has control over Port0 through Port3,
+ /// IDE controller has control over Port4 and Port7.
+ /// Disable - SATA controller has full control of all 8 Ports
+ /// when operating in non-IDE mode.
+ /// @li <b>0</b> - enable
+ /// @li <b>1</b> - disable
+ ///
+ UINT8 SataClkMode; /// SataClkMode - Reserved
+} SATA_ST;
+
+///
+/// SATA_PORT_ST - SATA PORT structure
+///
+typedef struct _SATA_PORT_ST {
+ UINT8 SataPortReg; ///< SATA Port bit map - bits[0:7] for ports 0 ~ 7
+ /// @li <b>0</b> - disable
+ /// @li <b>1</b> - enable
+ ///
+ BOOLEAN Port0; ///< PORT0 - 0:disable, 1:enable
+ BOOLEAN Port1; ///< PORT1 - 0:disable, 1:enable
+ BOOLEAN Port2; ///< PORT2 - 0:disable, 1:enable
+ BOOLEAN Port3; ///< PORT3 - 0:disable, 1:enable
+ BOOLEAN Port4; ///< PORT4 - 0:disable, 1:enable
+ BOOLEAN Port5; ///< PORT5 - 0:disable, 1:enable
+ BOOLEAN Port6; ///< PORT6 - 0:disable, 1:enable
+ BOOLEAN Port7; ///< PORT7 - 0:disable, 1:enable
+} SATA_PORT_ST;
+
+///
+///< _SATA_PORT_MD - Force Each PORT to GEN1/GEN2 mode
+///
+typedef struct _SATA_PORT_MD {
+ UINT16 SataPortMode; ///< SATA Port GEN1/GEN2 mode bit map - bits [0:15] for ports 0 ~ 7
+ UINT8 Port0; ///< PORT0 - set BIT0 to GEN1, BIT1 - PORT0 set to GEN2
+ UINT8 Port1; ///< PORT1 - set BIT2 to GEN1, BIT3 - PORT1 set to GEN2
+ UINT8 Port2; ///< PORT2 - set BIT4 to GEN1, BIT5 - PORT2 set to GEN2
+ UINT8 Port3; ///< PORT3 - set BIT6 to GEN1, BIT7 - PORT3 set to GEN2
+ UINT8 Port4; ///< PORT4 - set BIT8 to GEN1, BIT9 - PORT4 set to GEN2
+ UINT8 Port5; ///< PORT5 - set BIT10 to GEN1, BIT11 - PORT5 set to GEN2
+ UINT8 Port6; ///< PORT6 - set BIT12 to GEN1, BIT13 - PORT6 set to GEN2
+ UINT8 Port7; ///< PORT7 - set BIT14 to GEN1, BIT15 - PORT7 set to GEN2
+} SATA_PORT_MD;
+///
+/// SATA structure
+///
+typedef struct {
+ BOOLEAN SataMsiEnable; ///< SATA MSI capability
+ UINT32 SataIdeSsid; ///< SATA IDE mode SSID
+ UINT32 SataRaidSsid; ///< SATA RAID mode SSID
+ UINT32 SataRaid5Ssid; ///< SATA RAID 5 mode SSID
+ UINT32 SataAhciSsid; ///< SATA AHCI mode SSID
+
+ SATA_ST SataMode; /// SataMode - Reserved
+ SATA_CLASS SataClass; ///< SataClass - SATA Controller mode [2:0]
+ UINT8 SataIdeMode; ///< SataIdeMode - Sata IDE Controller mode
+ /// @par
+ /// @li <b>0</b> - Legacy IDE mode
+ /// @li <b>1</b> - Native IDE mode
+ ///
+ UINT8 SataDisUnusedIdePChannel; ///< SataDisUnusedIdePChannel-Disable Unused IDE Primary Channel
+ /// @par
+ /// @li <b>0</b> - Channel Enable
+ /// @li <b>1</b> - Channel Disable
+ ///
+ UINT8 SataDisUnusedIdeSChannel; ///< SataDisUnusedIdeSChannel - Disable Unused IDE Secondary Channel
+ /// @par
+ /// @li <b>0</b> - Channel Enable
+ /// @li <b>1</b> - Channel Disable
+ ///
+ UINT8 IdeDisUnusedIdePChannel; ///< IdeDisUnusedIdePChannel-Disable Unused IDE Primary Channel
+ /// @par
+ /// @li <b>0</b> - Channel Enable
+ /// @li <b>1</b> - Channel Disable
+ ///
+ UINT8 IdeDisUnusedIdeSChannel; ///< IdeDisUnusedIdeSChannel-Disable Unused IDE Secondary Channel
+ /// @par
+ /// @li <b>0</b> - Channel Enable
+ /// @li <b>1</b> - Channel Disable
+ ///
+ UINT8 SataOptionReserved; /// SataOptionReserved - Reserved
+
+ SATA_PORT_ST SataEspPort; ///< SataEspPort - SATA port is external accessible on a signal only connector (eSATA:)
+
+ SATA_PORT_ST SataPortPower; ///< SataPortPower - Port Power configuration
+
+ SATA_PORT_MD SataPortMd; ///< SataPortMd - Port Mode
+
+ UINT8 SataAggrLinkPmCap; /// SataAggrLinkPmCap - 0:OFF 1:ON
+ UINT8 SataPortMultCap; /// SataPortMultCap - 0:OFF 1:ON
+ UINT8 SataClkAutoOff; /// SataClkAutoOff - AutoClockOff 0:Disabled, 1:Enabled
+ UINT8 SataPscCap; /// SataPscCap 1:Enable PSC, 0:Disable PSC capability
+ UINT8 BiosOsHandOff; /// BiosOsHandOff - Reserved
+ UINT8 SataFisBasedSwitching; /// SataFisBasedSwitching - Reserved
+ UINT8 SataCccSupport; /// SataCccSupport - Reserved
+ UINT8 SataSscCap; /// SataSscCap - 1:Enable, 0:Disable SSC capability
+ UINT8 SataMsiCapability; /// SataMsiCapability 0:Hidden 1:Visible
+ UINT8 SataForceRaid; /// SataForceRaid 0:No function 1:Force RAID
+ UINT8 SataInternal100Spread; /// SataInternal100Spread - Reserved
+ UINT8 SataDebugDummy; /// SataDebugDummy - Reserved
+ UINT8 SataTargetSupport8Device; /// SataTargetSupport8Device - Reserved
+ UINT8 SataDisableGenericMode; /// SataDisableGenericMode - Reserved
+ BOOLEAN SataAhciEnclosureManagement; /// SataAhciEnclosureManagement - Reserved
+ UINT8 SataSgpio0; /// SataSgpio0 - Reserved
+ UINT8 SataSgpio1; /// SataSgpio1 - Reserved
+ UINT8 SataPhyPllShutDown; /// SataPhyPllShutDown - Reserved
+ BOOLEAN SataHotRemovalEnh; /// SataHotRemovalEnh - Reserved
+
+ SATA_PORT_ST SataHotRemovalEnhPort; ///< SataHotRemovalEnhPort - Hot Remove
+
+ BOOLEAN SataOobDetectionEnh; /// SataOobDetectionEnh - TRUE
+ BOOLEAN SataPowerSavingEnh; /// SataPowerSavingEnh - TRUE
+ UINT8 SataMemoryPowerSaving; /// SataMemoryPowerSaving - 0-3 Default [3]
+ BOOLEAN SataRasSupport; /// SataRasSupport - Support RAS function TRUE: Enable FALSE: Disable
+ BOOLEAN SataAhciDisPrefetchFunction; /// SataAhciDisPrefetchFunction - Disable AHCI Prefetch Function Support
+ BOOLEAN SataDevSlpPort0; /// SataDevSlpPort0 - Reserved
+ BOOLEAN SataDevSlpPort1; /// SataDevSlpPort1 - Reserved
+ UINT32 TempMmio; /// TempMmio - Reserved
+} FCH_SATA;
+
+
+//
+// IMC Message Register Software Interface
+//
+#define CPU_MISC_BUS_DEV_FUN ((0x18 << 3) + 3)
+
+#define MSG_SYS_TO_IMC 0x80
+#define Fun_80 0x80
+#define Fun_81 0x81
+#define Fun_82 0x82
+#define Fun_83 0x83
+#define Fun_84 0x84
+#define Fun_85 0x85
+#define Fun_86 0x86
+#define Fun_87 0x87
+#define Fun_88 0x88
+#define Fun_89 0x89
+#define Fun_90 0x90
+#define MSG_IMC_TO_SYS 0x81
+#define MSG_REG0 0x82
+#define MSG_REG1 0x83
+#define MSG_REG2 0x84
+#define MSG_REG3 0x85
+#define MSG_REG4 0x86
+#define MSG_REG5 0x87
+#define MSG_REG6 0x88
+#define MSG_REG7 0x89
+#define MSG_REG8 0x8A
+#define MSG_REG9 0x8B
+#define MSG_REGA 0x8C
+#define MSG_REGB 0x8D
+#define MSG_REGC 0x8E
+#define MSG_REGD 0x8F
+
+#define DISABLED 0
+#define ENABLED 1
+
+
+
+///
+/// EC structure
+///
+typedef struct _FCH_EC {
+ UINT8 MsgFun81Zone0MsgReg0; ///<Thermal zone
+ UINT8 MsgFun81Zone0MsgReg1; ///<Thermal zone
+ UINT8 MsgFun81Zone0MsgReg2; ///<Thermal zone control byte 1
+ UINT8 MsgFun81Zone0MsgReg3; ///<Thermal zone control byte 2
+ UINT8 MsgFun81Zone0MsgReg4; ///<Bit[3:0] - Thermal diode offset adjustment in degrees Celsius.
+ UINT8 MsgFun81Zone0MsgReg5; ///<Hysteresis information
+ UINT8 MsgFun81Zone0MsgReg6; ///<SMBUS Address for SMBUS based temperature sensor such as SB-TSI and ADM1032
+ UINT8 MsgFun81Zone0MsgReg7; ///<Bit[1:0]: 0 - 2, SMBUS bus number where the SMBUS based temperature sensor is located.
+ UINT8 MsgFun81Zone0MsgReg8; ///<Fan PWM stepping rate in unit of PWM level percentage
+ UINT8 MsgFun81Zone0MsgReg9; ///<Fan PWM ramping rate in 5ms unit
+//
+// EC LDN9 function 81 zone 1
+//
+ UINT8 MsgFun81Zone1MsgReg0; ///<Thermal zone
+ UINT8 MsgFun81Zone1MsgReg1; ///<Thermal zone
+ UINT8 MsgFun81Zone1MsgReg2; ///<Thermal zone control byte 1
+ UINT8 MsgFun81Zone1MsgReg3; ///<Thermal zone control byte 2
+ UINT8 MsgFun81Zone1MsgReg4; ///<Bit[3:0] - Thermal diode offset adjustment in degrees Celsius.
+ UINT8 MsgFun81Zone1MsgReg5; ///<Hysteresis information
+ UINT8 MsgFun81Zone1MsgReg6; ///<SMBUS Address for SMBUS based temperature sensor such as SB-TSI and ADM1032
+ UINT8 MsgFun81Zone1MsgReg7; ///<Bit[1:0]: 0 - 2, SMBUS bus number where the SMBUS based temperature sensor is located.
+ UINT8 MsgFun81Zone1MsgReg8; ///<Fan PWM stepping rate in unit of PWM level percentage
+ UINT8 MsgFun81Zone1MsgReg9; ///<Fan PWM ramping rate in 5ms unit
+//
+//EC LDN9 function 81 zone 2
+//
+ UINT8 MsgFun81Zone2MsgReg0; ///<Thermal zone
+ UINT8 MsgFun81Zone2MsgReg1; ///<Thermal zone
+ UINT8 MsgFun81Zone2MsgReg2; ///<Thermal zone control byte 1
+ UINT8 MsgFun81Zone2MsgReg3; ///<Thermal zone control byte 2
+ UINT8 MsgFun81Zone2MsgReg4; ///<Bit[3:0] - Thermal diode offset adjustment in degrees Celsius.
+ UINT8 MsgFun81Zone2MsgReg5; ///<Hysteresis information
+ UINT8 MsgFun81Zone2MsgReg6; ///<SMBUS Address for SMBUS based temperature sensor such as SB-TSI and ADM1032
+ UINT8 MsgFun81Zone2MsgReg7; ///<Bit[1:0]: 0 - 2, SMBUS bus number where the SMBUS based temperature sensor is located.
+ UINT8 MsgFun81Zone2MsgReg8; ///<Fan PWM stepping rate in unit of PWM level percentage
+ UINT8 MsgFun81Zone2MsgReg9; ///<Fan PWM ramping rate in 5ms unit
+//
+//EC LDN9 function 81 zone 3
+//
+ UINT8 MsgFun81Zone3MsgReg0; ///<Thermal zone
+ UINT8 MsgFun81Zone3MsgReg1; ///<Thermal zone
+ UINT8 MsgFun81Zone3MsgReg2; ///<Thermal zone control byte 1
+ UINT8 MsgFun81Zone3MsgReg3; ///<Thermal zone control byte 2
+ UINT8 MsgFun81Zone3MsgReg4; ///<Bit[3:0] - Thermal diode offset adjustment in degrees Celsius.
+ UINT8 MsgFun81Zone3MsgReg5; ///<Hysteresis information
+ UINT8 MsgFun81Zone3MsgReg6; ///<SMBUS Address for SMBUS based temperature sensor such as SB-TSI and ADM1032
+ UINT8 MsgFun81Zone3MsgReg7; ///<Bit[1:0]: 0 - 2, SMBUS bus number where the SMBUS based temperature sensor is located.
+ UINT8 MsgFun81Zone3MsgReg8; ///<Fan PWM stepping rate in unit of PWM level percentage
+ UINT8 MsgFun81Zone3MsgReg9; ///<Fan PWM ramping rate in 5ms unit
+//
+//EC LDN9 function 83 zone 0
+//
+ UINT8 MsgFun83Zone0MsgReg0; ///<Thermal zone
+ UINT8 MsgFun83Zone0MsgReg1; ///<Thermal zone
+ UINT8 MsgFun83Zone0MsgReg2; ///<_AC0
+ UINT8 MsgFun83Zone0MsgReg3; ///<_AC1
+ UINT8 MsgFun83Zone0MsgReg4; ///<_AC2
+ UINT8 MsgFun83Zone0MsgReg5; ///<_AC3
+ UINT8 MsgFun83Zone0MsgReg6; ///<_AC4
+ UINT8 MsgFun83Zone0MsgReg7; ///<_AC5
+ UINT8 MsgFun83Zone0MsgReg8; ///<_AC6
+ UINT8 MsgFun83Zone0MsgReg9; ///<_AC7
+ UINT8 MsgFun83Zone0MsgRegA; ///<_CRT
+ UINT8 MsgFun83Zone0MsgRegB; ///<_PSV
+//
+//EC LDN9 function 83 zone 1
+//
+ UINT8 MsgFun83Zone1MsgReg0; ///<Thermal zone
+ UINT8 MsgFun83Zone1MsgReg1; ///<Thermal zone
+ UINT8 MsgFun83Zone1MsgReg2; ///<_AC0
+ UINT8 MsgFun83Zone1MsgReg3; ///<_AC1
+ UINT8 MsgFun83Zone1MsgReg4; ///<_AC2
+ UINT8 MsgFun83Zone1MsgReg5; ///<_AC3
+ UINT8 MsgFun83Zone1MsgReg6; ///<_AC4
+ UINT8 MsgFun83Zone1MsgReg7; ///<_AC5
+ UINT8 MsgFun83Zone1MsgReg8; ///<_AC6
+ UINT8 MsgFun83Zone1MsgReg9; ///<_AC7
+ UINT8 MsgFun83Zone1MsgRegA; ///<_CRT
+ UINT8 MsgFun83Zone1MsgRegB; ///<_PSV
+//
+//EC LDN9 function 83 zone 2
+//
+ UINT8 MsgFun83Zone2MsgReg0; ///<Thermal zone
+ UINT8 MsgFun83Zone2MsgReg1; ///<Thermal zone
+ UINT8 MsgFun83Zone2MsgReg2; ///<_AC0
+ UINT8 MsgFun83Zone2MsgReg3; ///<_AC1
+ UINT8 MsgFun83Zone2MsgReg4; ///<_AC2
+ UINT8 MsgFun83Zone2MsgReg5; ///<_AC3
+ UINT8 MsgFun83Zone2MsgReg6; ///<_AC4
+ UINT8 MsgFun83Zone2MsgReg7; ///<_AC5
+ UINT8 MsgFun83Zone2MsgReg8; ///<_AC6
+ UINT8 MsgFun83Zone2MsgReg9; ///<_AC7
+ UINT8 MsgFun83Zone2MsgRegA; ///<_CRT
+ UINT8 MsgFun83Zone2MsgRegB; ///<_PSV
+//
+//EC LDN9 function 83 zone 3
+//
+ UINT8 MsgFun83Zone3MsgReg0; ///<Thermal zone
+ UINT8 MsgFun83Zone3MsgReg1; ///<Thermal zone
+ UINT8 MsgFun83Zone3MsgReg2; ///<_AC0
+ UINT8 MsgFun83Zone3MsgReg3; ///<_AC1
+ UINT8 MsgFun83Zone3MsgReg4; ///<_AC2
+ UINT8 MsgFun83Zone3MsgReg5; ///<_AC3
+ UINT8 MsgFun83Zone3MsgReg6; ///<_AC4
+ UINT8 MsgFun83Zone3MsgReg7; ///<_AC5
+ UINT8 MsgFun83Zone3MsgReg8; ///<_AC6
+ UINT8 MsgFun83Zone3MsgReg9; ///<_AC7
+ UINT8 MsgFun83Zone3MsgRegA; ///<_CRT
+ UINT8 MsgFun83Zone3MsgRegB; ///<_PSV
+//
+//EC LDN9 function 85 zone 0
+//
+ UINT8 MsgFun85Zone0MsgReg0; ///<Thermal zone
+ UINT8 MsgFun85Zone0MsgReg1; ///<Thermal zone
+ UINT8 MsgFun85Zone0MsgReg2; ///<AL0 PWM level in percentage (0 - 100%)
+ UINT8 MsgFun85Zone0MsgReg3; ///<AL1 PWM level in percentage (0 - 100%)
+ UINT8 MsgFun85Zone0MsgReg4; ///<AL2 PWM level in percentage (0 - 100%)
+ UINT8 MsgFun85Zone0MsgReg5; ///<AL3 PWM level in percentage (0 - 100%)
+ UINT8 MsgFun85Zone0MsgReg6; ///<AL4 PWM level in percentage (0 - 100%)
+ UINT8 MsgFun85Zone0MsgReg7; ///<AL5 PWM level in percentage (0 - 100%)
+ UINT8 MsgFun85Zone0MsgReg8; ///<AL6 PWM level in percentage (0 - 100%)
+ UINT8 MsgFun85Zone0MsgReg9; ///<AL7 PWM level in percentage (0 - 100%)
+//
+//EC LDN9 function 85 zone 1
+//
+ UINT8 MsgFun85Zone1MsgReg0; ///<Thermal zone
+ UINT8 MsgFun85Zone1MsgReg1; ///<Thermal zone
+ UINT8 MsgFun85Zone1MsgReg2; ///<AL0 PWM level in percentage (0 - 100%)
+ UINT8 MsgFun85Zone1MsgReg3; ///<AL1 PWM level in percentage (0 - 100%)
+ UINT8 MsgFun85Zone1MsgReg4; ///<AL2 PWM level in percentage (0 - 100%)
+ UINT8 MsgFun85Zone1MsgReg5; ///<AL3 PWM level in percentage (0 - 100%)
+ UINT8 MsgFun85Zone1MsgReg6; ///<AL4 PWM level in percentage (0 - 100%)
+ UINT8 MsgFun85Zone1MsgReg7; ///<AL5 PWM level in percentage (0 - 100%)
+ UINT8 MsgFun85Zone1MsgReg8; ///<AL6 PWM level in percentage (0 - 100%)
+ UINT8 MsgFun85Zone1MsgReg9; ///<AL7 PWM level in percentage (0 - 100%)
+//
+//EC LDN9 function 85 zone 2
+//
+ UINT8 MsgFun85Zone2MsgReg0; ///<Thermal zone
+ UINT8 MsgFun85Zone2MsgReg1; ///<Thermal zone
+ UINT8 MsgFun85Zone2MsgReg2; ///<AL0 PWM level in percentage (0 - 100%)
+ UINT8 MsgFun85Zone2MsgReg3; ///<AL1 PWM level in percentage (0 - 100%)
+ UINT8 MsgFun85Zone2MsgReg4; ///<AL2 PWM level in percentage (0 - 100%)
+ UINT8 MsgFun85Zone2MsgReg5; ///<AL3 PWM level in percentage (0 - 100%)
+ UINT8 MsgFun85Zone2MsgReg6; ///<AL4 PWM level in percentage (0 - 100%)
+ UINT8 MsgFun85Zone2MsgReg7; ///<AL5 PWM level in percentage (0 - 100%)
+ UINT8 MsgFun85Zone2MsgReg8; ///<AL6 PWM level in percentage (0 - 100%)
+ UINT8 MsgFun85Zone2MsgReg9; ///<AL7 PWM level in percentage (0 - 100%)
+//
+//EC LDN9 function 85 zone 3
+//
+ UINT8 MsgFun85Zone3MsgReg0; ///<Thermal zone
+ UINT8 MsgFun85Zone3MsgReg1; ///<Thermal zone
+ UINT8 MsgFun85Zone3MsgReg2; ///<AL0 PWM level in percentage (0 - 100%)
+ UINT8 MsgFun85Zone3MsgReg3; ///<AL1 PWM level in percentage (0 - 100%)
+ UINT8 MsgFun85Zone3MsgReg4; ///<AL2 PWM level in percentage (0 - 100%)
+ UINT8 MsgFun85Zone3MsgReg5; ///<AL3 PWM level in percentage (0 - 100%)
+ UINT8 MsgFun85Zone3MsgReg6; ///<AL4 PWM level in percentage (0 - 100%)
+ UINT8 MsgFun85Zone3MsgReg7; ///<AL5 PWM level in percentage (0 - 100%)
+ UINT8 MsgFun85Zone3MsgReg8; ///<AL6 PWM level in percentage (0 - 100%)
+ UINT8 MsgFun85Zone3MsgReg9; ///<AL7 PWM level in percentage (0 - 100%)
+//
+//EC LDN9 function 89 TEMPIN channel 0
+//
+ UINT8 MsgFun89Zone0MsgReg0; ///<Thermal zone
+ UINT8 MsgFun89Zone0MsgReg1; ///<Thermal zone
+ UINT8 MsgFun89Zone0MsgReg2; ///<At DWORD bit 0-7
+ UINT8 MsgFun89Zone0MsgReg3; ///<At DWORD bit 15-8
+ UINT8 MsgFun89Zone0MsgReg4; ///<At DWORD bit 23-16
+ UINT8 MsgFun89Zone0MsgReg5; ///<At DWORD bit 31-24
+ UINT8 MsgFun89Zone0MsgReg6; ///<Ct DWORD bit 0-7
+ UINT8 MsgFun89Zone0MsgReg7; ///<Ct DWORD bit 15-8
+ UINT8 MsgFun89Zone0MsgReg8; ///<Ct DWORD bit 23-16
+ UINT8 MsgFun89Zone0MsgReg9; ///<Ct DWORD bit 31-24
+ UINT8 MsgFun89Zone0MsgRegA; ///<Mode bit 0-7
+//
+//EC LDN9 function 89 TEMPIN channel 1
+//
+ UINT8 MsgFun89Zone1MsgReg0; ///<Thermal zone
+ UINT8 MsgFun89Zone1MsgReg1; ///<Thermal zone
+ UINT8 MsgFun89Zone1MsgReg2; ///<At DWORD bit 0-7
+ UINT8 MsgFun89Zone1MsgReg3; ///<At DWORD bit 15-8
+ UINT8 MsgFun89Zone1MsgReg4; ///<At DWORD bit 23-16
+ UINT8 MsgFun89Zone1MsgReg5; ///<At DWORD bit 31-24
+ UINT8 MsgFun89Zone1MsgReg6; ///<Ct DWORD bit 0-7
+ UINT8 MsgFun89Zone1MsgReg7; ///<Ct DWORD bit 15-8
+ UINT8 MsgFun89Zone1MsgReg8; ///<Ct DWORD bit 23-16
+ UINT8 MsgFun89Zone1MsgReg9; ///<Ct DWORD bit 31-24
+ UINT8 MsgFun89Zone1MsgRegA; ///<Mode bit 0-7
+//
+//EC LDN9 function 89 TEMPIN channel 2
+//
+ UINT8 MsgFun89Zone2MsgReg0; ///<Thermal zone
+ UINT8 MsgFun89Zone2MsgReg1; ///<Thermal zone
+ UINT8 MsgFun89Zone2MsgReg2; ///<At DWORD bit 0-7
+ UINT8 MsgFun89Zone2MsgReg3; ///<At DWORD bit 15-8
+ UINT8 MsgFun89Zone2MsgReg4; ///<At DWORD bit 23-16
+ UINT8 MsgFun89Zone2MsgReg5; ///<At DWORD bit 31-24
+ UINT8 MsgFun89Zone2MsgReg6; ///<Ct DWORD bit 0-7
+ UINT8 MsgFun89Zone2MsgReg7; ///<Ct DWORD bit 15-8
+ UINT8 MsgFun89Zone2MsgReg8; ///<Ct DWORD bit 23-16
+ UINT8 MsgFun89Zone2MsgReg9; ///<Ct DWORD bit 31-24
+ UINT8 MsgFun89Zone2MsgRegA; ///<Mode bit 0-7
+//
+//EC LDN9 function 89 TEMPIN channel 3
+//
+ UINT8 MsgFun89Zone3MsgReg0; ///<Thermal zone
+ UINT8 MsgFun89Zone3MsgReg1; ///<Thermal zone
+ UINT8 MsgFun89Zone3MsgReg2; ///<At DWORD bit 0-7
+ UINT8 MsgFun89Zone3MsgReg3; ///<At DWORD bit 15-8
+ UINT8 MsgFun89Zone3MsgReg4; ///<At DWORD bit 23-16
+ UINT8 MsgFun89Zone3MsgReg5; ///<At DWORD bit 31-24
+ UINT8 MsgFun89Zone3MsgReg6; ///<Ct DWORD bit 0-7
+ UINT8 MsgFun89Zone3MsgReg7; ///<Ct DWORD bit 15-8
+ UINT8 MsgFun89Zone3MsgReg8; ///<Ct DWORD bit 23-16
+ UINT8 MsgFun89Zone3MsgReg9; ///<Ct DWORD bit 31-24
+ UINT8 MsgFun89Zone3MsgRegA; ///<Mode bit 0-7
+//
+// FLAG for Fun83/85/89 support
+//
+ UINT16 IMCFUNSupportBitMap; ///< Bit0=81FunZone0 support(1=On;0=Off); bit1-3=81FunZone1-Zone3;Bit4-7=83FunZone0-Zone3;Bit8-11=85FunZone0-Zone3;Bit11-15=89FunZone0-Zone3;
+} FCH_EC;
+
+///
+/// IMC structure
+///
+typedef struct _FCH_IMC {
+ UINT8 ImcEnable; ///< ImcEnable - IMC Enable
+ UINT8 ImcEnabled; ///< ImcEnabled - IMC Enable
+ UINT8 ImcSureBootTimer; ///< ImcSureBootTimer - IMc SureBootTimer function
+ FCH_EC EcStruct; ///< EC structure
+ UINT8 ImcEnableOverWrite; ///< OverWrite IMC with the EC structure
+ /// @li <b>00</b> - by default strapping
+ /// @li <b>01</b> - enable
+ /// @li <b>10</b> - disable
+ ///
+} FCH_IMC;
+
+
+///
+/// Hpet structure
+///
+typedef struct {
+ BOOLEAN HpetEnable; ///< HPET function switch
+
+ BOOLEAN HpetMsiDis; ///< HpetMsiDis - South Bridge HPET MSI Configuration
+ /// @par
+ /// @li <b>1</b> - disable
+ /// @li <b>0</b> - enable
+
+ UINT32 HpetBase; ///< HpetBase
+ /// @par
+ /// HPET Base address
+} FCH_HPET;
+
+
+///
+/// GCPU related parameters
+///
+typedef struct {
+ UINT8 AcDcMsg; ///< Send a message to CPU to indicate the power mode (AC vs battery)
+ /// @li <b>1</b> - disable
+ /// @li <b>0</b> - enable
+
+ UINT8 TimerTickTrack; ///< Send a message to CPU to indicate the latest periodic timer interval
+ /// @li <b>1</b> - disable
+ /// @li <b>0</b> - enable
+
+ UINT8 ClockInterruptTag; ///< Mark the periodic timer interrupt
+ /// @li <b>1</b> - disable
+ /// @li <b>0</b> - enable
+
+ UINT8 OhciTrafficHanding; ///< Cause CPU to break out from C state when USB OHCI has pending traffic
+ /// @li <b>1</b> - disable
+ /// @li <b>0</b> - enable
+
+ UINT8 EhciTrafficHanding; ///< Cause CPU to break out from C state when USB EHCI has pending traffic
+ /// @li <b>1</b> - disable
+ /// @li <b>0</b> - enable
+
+ UINT8 GcpuMsgCMultiCore; ///< Track of CPU C state by monitoring each core's C state message
+ /// @li <b>1</b> - disable
+ /// @li <b>0</b> - enable
+
+ UINT8 GcpuMsgCStage; ///< Enable the FCH C state coordination logic
+ /// @li <b>1</b> - disable
+ /// @li <b>0</b> - enable
+} FCH_GCPU;
+
+
+///
+/// Timer
+///
+typedef struct {
+ BOOLEAN Enable; ///< Whether to register timer SMI in POST
+ BOOLEAN StartNow; ///< Whether to start the SMI immediately during registration
+ UINT16 CycleDuration; ///< [14:0] - Actual cycle duration = CycleDuration + 1
+} TIMER_SMI;
+
+///
+/// CS support
+///
+typedef struct {
+ BOOLEAN FchCsD3Cold; ///< FCH Cs D3 Cold function
+ BOOLEAN FchCsHwReduced; ///< FCH Cs hardware reduced ACPI flag
+ BOOLEAN FchCsPwrBtn; ///< FCH Cs Power Button function
+ BOOLEAN FchCsAcDc; ///< FCH Cs AcDc function
+ BOOLEAN AsfNfcEnable; ///< FCH Cs NFC function
+ UINT8 AsfNfcInterruptPin; ///< NFC Interrupt pin define
+ UINT8 AsfNfcRegPuPin; ///< NFC RegPu pin define
+ UINT8 AsfNfcWakePin; ///< NFC Wake Pin define
+ UINT8 PowerButtonGpe; ///< GPE# used by Power Button device
+ UINT8 AcDcTimerGpe; ///< GPE# used by Timer device
+} FCH_CS;
+
+
+///
+/// MISC structure
+///
+typedef struct {
+ BOOLEAN NativePcieSupport; /// PCIe NativePcieSupport - Debug function. 1:Enabled, 0:Disabled
+ BOOLEAN S3Resume; /// S3Resume - Flag of ACPI S3 Resume.
+ BOOLEAN RebootRequired; /// RebootRequired - Flag of Reboot system is required.
+ UINT8 FchVariant; /// FchVariant - FCH Variant value.
+ UINT8 Cg2Pll; ///< CG2 PLL - 0:disable, 1:enable
+ TIMER_SMI LongTimer; ///< Long Timer SMI
+ TIMER_SMI ShortTimer; ///< Short Timer SMI
+ UINT32 FchCpuId; ///< Saving CpuId for FCH Module.
+ BOOLEAN NoneSioKbcSupport; ///< NoneSioKbcSupport - No KBC/SIO controller ( Turn on Inchip KBC emulation function )
+ FCH_CS FchCsSupport; ///< FCH Cs function structure
+} FCH_MISC;
+
+
+///
+/// SMBus structure
+///
+typedef struct {
+ UINT32 SmbusSsid; ///< SMBUS controller Subsystem ID
+} FCH_SMBUS;
+
+
+///
+/// Acpi structure
+///
+typedef struct {
+ UINT16 Smbus0BaseAddress; ///< Smbus0BaseAddress
+ /// @par
+ /// Smbus BASE Address
+ ///
+ UINT16 Smbus1BaseAddress; ///< Smbus1BaseAddress
+ /// @par
+ /// Smbus1 (ASF) BASE Address
+ ///
+ UINT16 SioPmeBaseAddress; ///< SioPmeBaseAddress
+ /// @par
+ /// SIO PME BASE Address
+ ///
+ UINT32 WatchDogTimerBase; ///< WatchDogTimerBase
+ /// @par
+ /// Watch Dog Timer Address
+ ///
+ UINT16 AcpiPm1EvtBlkAddr; ///< AcpiPm1EvtBlkAddr
+ /// @par
+ /// ACPI PM1 event block Address
+ ///
+ UINT16 AcpiPm1CntBlkAddr; ///< AcpiPm1CntBlkAddr
+ /// @par
+ /// ACPI PM1 Control block Address
+ ///
+ UINT16 AcpiPmTmrBlkAddr; ///< AcpiPmTmrBlkAddr
+ /// @par
+ /// ACPI PM timer block Address
+ ///
+ UINT16 CpuControlBlkAddr; ///< CpuControlBlkAddr
+ /// @par
+ /// ACPI CPU control block Address
+ ///
+ UINT16 AcpiGpe0BlkAddr; ///< AcpiGpe0BlkAddr
+ /// @par
+ /// ACPI GPE0 block Address
+ ///
+ UINT16 SmiCmdPortAddr; ///< SmiCmdPortAddr
+ /// @par
+ /// SMI command port Address
+ ///
+ UINT16 AcpiPmaCntBlkAddr; ///< AcpiPmaCntBlkAddr
+ /// @par
+ /// ACPI PMA Control block Address
+ ///
+ BOOLEAN AnyHt200MhzLink; ///< AnyHt200MhzLink
+ /// @par
+ /// HT Link Speed on 200MHz option for each CPU specific LDTSTP# (Force enable)
+ ///
+ BOOLEAN SpreadSpectrum; ///< SpreadSpectrum
+ /// @par
+ /// Spread Spectrum function
+ /// @li <b>0</b> - disable
+ /// @li <b>1</b> - enable
+ ///
+ POWER_FAIL PwrFailShadow; ///< PwrFailShadow = PM_Reg: 5Bh [3:0]
+ /// @par
+ /// @li <b>00</b> - Always off
+ /// @li <b>01</b> - Always on
+ /// @li <b>11</b> - Use previous
+ ///
+ UINT8 StressResetMode; ///< StressResetMode 01-10
+ /// @li <b>00</b> - Disabed
+ /// @li <b>01</b> - Io Write 0x64 with 0xfe
+ /// @li <b>10</b> - Io Write 0xcf9 with 0x06
+ /// @li <b>11</b> - Io Write 0xcf9 with 0x0e
+ ///
+ BOOLEAN MtC1eEnable; /// MtC1eEnable - Enable MtC1e
+ VOID* OemProgrammingTablePtr; /// Pointer of ACPI OEM table
+ UINT8 SpreadSpectrumOptions; /// SpreadSpectrumOptions - Spread Spectrum Option
+ BOOLEAN PwrDownDisp2ClkPcieR; /// Power down DISP2_CLK and PCIE_RCLK_Output for power savings
+} FCH_ACPI;
+
+
+///
+/// HWM temp parameter structure
+///
+typedef struct _FCH_HWM_TEMP_PAR {
+ UINT16 At; ///< At
+ UINT16 Ct; ///< Ct
+ UINT8 Mode; ///< Mode BIT0:HiRatio BIT1:HiCurrent
+} FCH_HWM_TEMP_PAR;
+
+///
+/// HWM Current structure
+///
+typedef struct _FCH_HWM_CUR {
+ UINT16 FanSpeed[5]; ///< FanSpeed - fan Speed
+ UINT16 Temperature[5]; ///< Temperature - temperature
+ UINT16 Voltage[8]; ///< Voltage - voltage
+} FCH_HWM_CUR;
+
+///
+/// HWM fan control structure
+///
+typedef struct _FCH_HWM_FAN_CTR {
+ UINT8 InputControlReg00; /// Fan Input Control register, PM2 offset [0:4]0
+ UINT8 ControlReg01; /// Fan control register, PM2 offset [0:4]1
+ UINT8 FreqReg02; /// Fan frequency register, PM2 offset [0:4]2
+ UINT8 LowDutyReg03; /// Low Duty register, PM2 offset [0:4]3
+ UINT8 MedDutyReg04; /// Med Duty register, PM2 offset [0:4]4
+ UINT8 MultiplierReg05; /// Multiplier register, PM2 offset [0:4]5
+ UINT16 LowTempReg06; /// Low Temp register, PM2 offset [0:4]6
+ UINT16 MedTempReg08; /// Med Temp register, PM2 offset [0:4]8
+ UINT16 HighTempReg0A; /// High Temp register, PM2 offset [0:4]A
+ UINT8 LinearRangeReg0C; /// Linear Range register, PM2 offset [0:4]C
+ UINT8 LinearHoldCountReg0D; /// Linear Hold Count register, PM2 offset [0:4]D
+} FCH_HWM_FAN_CTR;
+
+///
+/// Hwm structure
+///
+typedef struct _FCH_HWM {
+ UINT8 HwMonitorEnable; ///< HwMonitorEnable
+ UINT32 HwmControl; ///< hwmControl
+ /// @par
+ /// HWM control configuration
+ /// @li <b>0</b> - HWM is Enabled
+ /// @li <b>1</b> - IMC is Enabled
+ ///
+ UINT8 FanSampleFreqDiv; ///< Sampling rate of Fan Speed
+ /// @li <b>00</b> - Base(22.5KHz)
+ /// @li <b>01</b> - Base(22.5KHz)/2
+ /// @li <b>10</b> - Base(22.5KHz)/4
+ /// @li <b>11</b> - Base(22.5KHz)/8
+ ///
+ UINT8 HwmFchtsiAutoPoll; ///< TSI Auto Polling
+ /// @li <b>0</b> - disable
+ /// @li <b>1</b> - enable
+ ///
+ UINT8 HwmFchtsiAutoPollStarted; ///< HwmSbtsiAutoPollStarted
+ UINT8 FanLinearEnhanceEn; ///< FanLinearEnhanceEn
+ UINT8 FanLinearHoldFix; ///< FanLinearHoldFix
+ UINT8 FanLinearRangeOutLimit; ///< FanLinearRangeOutLimit
+ UINT16 HwmCalibrationFactor; /// Calibration Factor
+ FCH_HWM_CUR HwmCurrent; /// HWM Current structure
+ FCH_HWM_CUR HwmCurrentRaw; /// HWM Current Raw structure
+ FCH_HWM_TEMP_PAR HwmTempPar[5]; /// HWM Temp parameter structure
+ FCH_HWM_FAN_CTR HwmFanControl[5]; /// HWM Fan Control structure
+ FCH_HWM_FAN_CTR HwmFanControlCooked[5]; /// HWM Fan Control structure
+} FCH_HWM;
+
+
+///
+/// Gec structure
+///
+typedef struct {
+ BOOLEAN GecEnable; ///< GecEnable - GEC function switch
+ UINT8 GecPhyStatus; /// GEC PHY Status
+ UINT8 GecPowerPolicy; /// GEC Power Policy
+ /// @li <b>00</b> - GEC is powered down in S3 and S5
+ /// @li <b>01</b> - GEC is powered down only in S5
+ /// @li <b>10</b> - GEC is powered down only in S3
+ /// @li <b>11</b> - GEC is never powered down
+ ///
+ UINT8 GecDebugBus; /// GEC Debug Bus
+ /// @li <b>0</b> - disable
+ /// @li <b>1</b> - enable
+ ///
+ UINT32 GecShadowRomBase; ///< GecShadowRomBase
+ /// @par
+ /// GEC (NIC) SHADOWROM BASE Address
+ ///
+ VOID *PtrDynamicGecRomAddress; /// Pointer of Dynamic GEC ROM Address
+} FCH_GEC;
+
+
+///
+/// _ABTblEntry - AB link register table R/W structure
+///
+typedef struct _AB_TBL_ENTRY {
+ UINT8 RegType; /// RegType : AB Register Type (ABCFG, AXCFG and so on)
+ UINT32 RegIndex; /// RegIndex : AB Register Index
+ UINT32 RegMask; /// RegMask : AB Register Mask
+ UINT32 RegData; /// RegData : AB Register Data
+} AB_TBL_ENTRY;
+
+///
+/// AB structure
+///
+typedef struct {
+ BOOLEAN AbMsiEnable; ///< ABlink MSI capability
+ UINT8 ALinkClkGateOff; /// Alink Clock Gate-Off function - 0:disable, 1:enable *KR
+ UINT8 BLinkClkGateOff; /// Blink Clock Gate-Off function - 0:disable, 1:enable *KR
+ UINT8 AbClockGating; /// AB Clock Gating - 0:disable, 1:enable *KR
+ UINT8 GppClockGating; /// GPP Clock Gating - 0:disable, 1:enable
+ UINT8 UmiL1TimerOverride; /// UMI L1 inactivity timer overwrite value
+ UINT8 UmiLinkWidth; /// UMI Link Width
+ UINT8 UmiDynamicSpeedChange; /// UMI Dynamic Speed Change - 0:disable, 1:enable
+ UINT8 PcieRefClockOverClocking; /// PCIe Ref Clock OverClocking value
+ UINT8 UmiGppTxDriverStrength; /// UMI GPP TX Driver Strength
+ BOOLEAN NbSbGen2; /// UMI link Gen2 - 0:Gen1, 1:Gen2
+ UINT8 PcieOrderRule; /// PCIe Order Rule - 0:disable, 1:enable *KR AB Posted Pass Non-Posted
+ UINT8 SlowSpeedAbLinkClock; /// Slow Speed AB Link Clock - 0:disable, 1:enable *KR
+ BOOLEAN ResetCpuOnSyncFlood; /// Reset Cpu On Sync Flood - 0:disable, 1:enable *KR
+ BOOLEAN AbDmaMemoryWrtie3264B; /// AB DMA Memory Write 32/64 BYTE Support *KR only
+ BOOLEAN AbMemoryPowerSaving; /// AB Memory Power Saving *KR only
+ BOOLEAN SbgDmaMemoryWrtie3264ByteCount; /// SBG DMA Memory Write 32/64 BYTE Count Support *KR only
+ BOOLEAN SbgMemoryPowerSaving; /// SBG Memory Power Saving *KR only
+} FCH_AB;
+
+
+/**
+ * PCIE_CAP_ID - PCIe Cap ID
+ *
+ */
+#define PCIE_CAP_ID 0x10
+
+///
+/// FCH_GPP_PORT_CONFIG - Fch GPP port config structure
+///
+typedef struct {
+ BOOLEAN PortPresent; ///< Port connection
+ /// @par
+ /// @li <b>0</b> - Port doesn't have slot. No need to train the link
+ /// @li <b>1</b> - Port connection defined and needs to be trained
+ ///
+ BOOLEAN PortDetected; ///< Link training status
+ /// @par
+ /// @li <b>0</b> - EP not detected
+ /// @li <b>1</b> - EP detected
+ ///
+ BOOLEAN PortIsGen2; ///< Port link speed configuration
+ /// @par
+ /// @li <b>00</b> - Auto
+ /// @li <b>01</b> - Forced GEN1
+ /// @li <b>10</b> - Forced GEN2
+ /// @li <b>11</b> - Reserved
+ ///
+ BOOLEAN PortHotPlug; ///< Support hot plug?
+ /// @par
+ /// @li <b>0</b> - No support
+ /// @li <b>1</b> - support
+ ///
+ UINT8 PortMisc; /// PortMisc - Reserved
+} FCH_GPP_PORT_CONFIG;
+
+///
+/// GPP structure
+///
+typedef struct {
+ FCH_GPP_PORT_CONFIG PortCfg[4]; /// GPP port configuration structure
+ GPP_LINKMODE GppLinkConfig; ///< GppLinkConfig - PCIE_GPP_Enable[3:0]
+ /// @li <b>0000</b> - Port ABCD -> 4:0:0:0
+ /// @li <b>0010</b> - Port ABCD -> 2:2:0:0
+ /// @li <b>0011</b> - Port ABCD -> 2:1:1:0
+ /// @li <b>0100</b> - Port ABCD -> 1:1:1:1
+ ///
+ BOOLEAN GppFunctionEnable; ///< GPP Function - 0:disable, 1:enable
+ BOOLEAN GppToggleReset; ///< Toggle GPP core reset
+ UINT8 GppHotPlugGeventNum; ///< Hotplug GEVENT # - valid value 0-31
+ UINT8 GppFoundGfxDev; ///< Gpp Found Gfx Device
+ /// @li <b>0</b> - Not found
+ /// @li <b>1</b> - Found
+ ///
+ BOOLEAN GppGen2; ///< GPP Gen2 - 0:disable, 1:enable
+ UINT8 GppGen2Strap; ///< GPP Gen2 Strap - 0:disable, 1:enable, FCH itself uses this
+ BOOLEAN GppMemWrImprove; ///< GPP Memory Write Improve - 0:disable, 1:enable
+ BOOLEAN GppUnhidePorts; ///< GPP Unhide Ports - 0:disable, 1:enable
+ UINT8 GppPortAspm; ///< GppPortAspm - ASPM state for all GPP ports
+ /// @li <b>01</b> - Disabled
+ /// @li <b>01</b> - L0s
+ /// @li <b>10</b> - L1
+ /// @li <b>11</b> - L0s + L1
+ ///
+ BOOLEAN GppLaneReversal; ///< GPP Lane Reversal - 0:disable, 1:enable
+ BOOLEAN GppPhyPllPowerDown; ///< GPP PHY PLL Power Down - 0:disable, 1:enable
+ BOOLEAN GppDynamicPowerSaving; ///< GPP Dynamic Power Saving - 0:disable, 1:enable
+ BOOLEAN PcieAer; ///< PcieAer - Advanced Error Report: 0/1-disable/enable
+ BOOLEAN PcieRas; ///< PCIe RAS - 0:disable, 1:enable
+ BOOLEAN PcieCompliance; ///< PCIe Compliance - 0:disable, 1:enable
+ BOOLEAN PcieSoftwareDownGrade; ///< PCIe Software Down Grade
+ BOOLEAN UmiPhyPllPowerDown; ///< UMI PHY PLL Power Down - 0:disable, 1:enable
+ BOOLEAN SerialDebugBusEnable; ///< Serial Debug Bus Enable
+ UINT8 GppHardwareDownGrade; ///< GppHardwareDownGrade - Gpp HW Down Grade function 0:Disable, 1-4: portA-D
+ UINT8 GppL1ImmediateAck; ///< GppL1ImmediateAck - Gpp L1 Immediate ACK 0: enable, 1: disable
+ BOOLEAN NewGppAlgorithm; ///< NewGppAlgorithm - New GPP procedure
+ UINT8 HotPlugPortsStatus; ///< HotPlugPortsStatus - Save Hot-Plug Ports Status
+ UINT8 FailPortsStatus; ///< FailPortsStatus - Save Failure Ports Status
+ UINT8 GppPortMinPollingTime; ///< GppPortMinPollingTime - Min. Polling time for Gpp Port Training
+ BOOLEAN IsCapsuleMode; ///< IsCapsuleMode - Support Capsule Mode in FCH
+} FCH_GPP;
+
+
+///
+/// FCH USB sturcture
+///
+typedef struct {
+ BOOLEAN Ohci1Enable; ///< OHCI1 controller enable
+ BOOLEAN Ohci2Enable; ///< OHCI2 controller enable
+ BOOLEAN Ohci3Enable; ///< OHCI3 controller enable
+ BOOLEAN Ohci4Enable; ///< OHCI4 controller enable
+ BOOLEAN Ehci1Enable; ///< EHCI1 controller enable
+ BOOLEAN Ehci2Enable; ///< EHCI2 controller enable
+ BOOLEAN Ehci3Enable; ///< EHCI3 controller enable
+ BOOLEAN Xhci0Enable; ///< XHCI0 controller enable
+ BOOLEAN Xhci1Enable; ///< XHCI1 controller enable
+ BOOLEAN UsbMsiEnable; ///< USB MSI capability
+ UINT32 OhciSsid; ///< OHCI SSID
+ UINT32 Ohci4Ssid; ///< OHCI 4 SSID
+ UINT32 EhciSsid; ///< EHCI SSID
+ UINT32 XhciSsid; ///< XHCI SSID
+ BOOLEAN UsbPhyPowerDown; ///< USB PHY Power Down - 0:disable, 1:enable
+ UINT32 UserDefineXhciRomAddr; ///< XHCI ROM address define by platform BIOS
+ UINT8 Ehci1Phy[5]; ///< EHCI1 USB PHY Driving Strength value table
+ UINT8 Ehci2Phy[5]; ///< EHCI2 USB PHY Driving Strength value table
+ UINT8 Ehci3Phy[4]; ///< EHCI3 USB PHY Driving Strength value table
+ UINT8 Xhci20Phy[4]; ///< XHCI USB 2.0 PHY Driving Strength value table
+ UINT8 Ehci1DebugPortSel; ///< DebugPortSel for Ehci1 Hub
+ /// @li <b>000</b> - Disable
+ /// @li <b>001</b> - HubDownStreamPort0
+ /// @li <b>010</b> - HubDownStreamPort1
+ /// @li <b>011</b> - HubDownStreamPort2
+ /// @li <b>100</b> - HubDownStreamPort3
+ UINT8 Ehci2DebugPortSel; ///< DebugPortSel for Ehci2 Hub
+ /// @li <b>000</b> - Disable
+ /// @li <b>001</b> - HubDownStreamPort0
+ /// @li <b>010</b> - HubDownStreamPort1
+ /// @li <b>011</b> - HubDownStreamPort2
+ /// @li <b>100</b> - HubDownStreamPort3
+ UINT8 Ehci3DebugPortSel; ///< DebugPortSel for Ehci3 Hub
+ /// @li <b>000</b> - Disable
+ /// @li <b>001</b> - HubDownStreamPort0
+ /// @li <b>010</b> - HubDownStreamPort1
+ /// @li <b>011</b> - HubDownStreamPort2
+ /// @li <b>100</b> - HubDownStreamPort3
+} FCH_USB;
+
+
+/// Private: FCH_DATA_BLOCK_RESET
+typedef struct _FCH_RESET_DATA_BLOCK {
+ AMD_CONFIG_PARAMS *StdHeader; ///< Header structure
+ FCH_RESET_INTERFACE FchReset; ///< Reset interface
+
+ UINT8 FastSpeed; ///< SPI FastSpeed: 1-66MHz, 2-33MHz, 3-22MHz, 4-16.5MHz, 5-100Mhz
+ UINT8 WriteSpeed; ///< SPI Write Speed: 1-66MHz, 2-33MHz, 3-22MHz, 4-16.5MHz, 5-100Mhz
+ UINT8 Mode; ///< SPI Mode
+ /// @li <b>101</b> - Qual-io 1-4-4
+ /// @li <b>100</b> - Dual-io 1-2-2
+ /// @li <b>011</b> - Qual-io 1-1-4
+ /// @li <b>010</b> - Dual-io 1-1-2
+ /// @li <b>111</b> - FastRead
+ /// @li <b>110</b> - Normal
+ ///
+ UINT8 AutoMode; ///< SPI Auto Mode - 0:disable, 1:enable
+ UINT8 BurstWrite; ///< SPI Burst Write - 0:disable, 1:enable
+ BOOLEAN Sata6AhciCap; ///< SATA 6 AHCI Capability - TRUE:enable, FALSE:disable
+ UINT8 Cg2Pll; ///< CG2 PLL - 0:disable, 1:enable
+ BOOLEAN EcKbd; ///< EC KBD - 0:disable, 1:enable
+ BOOLEAN LegacyFree; ///< Legacy Free - 0:disable, 1:enable
+ BOOLEAN SataSetMaxGen2; ///< SATA enable maximum GEN2
+ UINT8 SataClkMode; ///< SATA reference clock selector and divider
+ UINT8 SataModeReg; ///< Output: SATAConfig PMIO:0xDA
+ BOOLEAN SataInternal100Spread; ///< SATA internal 100MHz spread ON/OFF
+ UINT8 SpiSpeed; ///< SPI NormSpeed: 1-66MHz, 2-33MHz, 3-22MHz, 4-16.5MHz, 5-100Mhz
+// UINT32 SPI100_RX_Timing_Config_Register_38; ///< SPI100_RX_Timing_Config_Register_38
+// UINT16 SPI100_RX_Timing_Config_Register_3C; ///< SPI100_RX_Timing_Config_Register_3C
+// UINT8 SpiProtectEn0_1d_34; ///
+ UINT8 SPI100_Enable; ///
+ BOOLEAN EcChannel0; ///< Enable EC channel 0
+ FCH_GPP Gpp; ///< GPP subsystem
+ FCH_SPI Spi; ///< SPI subsystem
+ BOOLEAN QeEnabled; /// Quad Mode Enabled
+ BOOLEAN FchOscout1ClkContinous; ///< FCH OSCOUT1_CLK Continous
+ VOID* EarlyOemGpioTable; /// Pointer of Early OEM GPIO table
+// VOID* OemSpiDeviceTable; /// Pointer of OEM Spi Device table
+ VOID* OemResetProgrammingTablePtr; /// Pointer of ACPI OEM table
+} FCH_RESET_DATA_BLOCK;
+
+
+/// Private: FCH_DATA_BLOCK
+typedef struct _FCH_DATA_BLOCK {
+ AMD_CONFIG_PARAMS *StdHeader; ///< Header structure
+
+ FCH_ACPI HwAcpi; ///< ACPI structure
+ FCH_AB Ab; ///< AB structure
+ FCH_GPP Gpp; ///< GPP structure
+ FCH_USB Usb; ///< USB structure
+ FCH_SATA Sata; ///< SATA structure
+ FCH_SMBUS Smbus; ///< SMBus structure
+ FCH_IDE Ide; ///< IDE structure
+ FCH_AZALIA Azalia; ///< Azalia structure
+ FCH_SPI Spi; ///< SPI structure
+ FCH_PCIB Pcib; ///< PCIB structure
+ FCH_GEC Gec; ///< GEC structure
+ FCH_SD Sd; ///< SD structure
+ FCH_HWM Hwm; ///< Hardware Moniter structure
+ FCH_IR Ir; ///< IR structure
+ FCH_HPET Hpet; ///< HPET structure
+ FCH_GCPU Gcpu; ///< GCPU structure
+ FCH_IMC Imc; ///< IMC structure
+ FCH_MISC Misc; ///< MISC structure
+ VOID* PostOemGpioTable; /// Pointer of Post OEM GPIO table
+} FCH_DATA_BLOCK;
+
+#pragma pack (pop)
+
+#endif
diff --git a/src/vendorcode/amd/pi/00630F01/Proc/Fch/Common/FchDef.h b/src/vendorcode/amd/pi/00630F01/Proc/Fch/Common/FchDef.h
new file mode 100644
index 0000000..d8317b9
--- /dev/null
+++ b/src/vendorcode/amd/pi/00630F01/Proc/Fch/Common/FchDef.h
@@ -0,0 +1,477 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * FCH routine definition
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: FCH
+ * @e \$Revision: 281181 $ @e \$Date: 2013-12-18 02:18:55 -0600 (Wed, 18 Dec 2013) $
+ *
+ */
+/*****************************************************************************
+ *
+ * Copyright 2008 - 2014 ADVANCED MICRO DEVICES, INC. All Rights Reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *****************************************************************************/
+#ifndef _FCH_DEF_H_
+#define _FCH_DEF_H_
+
+
+UINT32 ReadAlink (IN UINT32 Index, IN AMD_CONFIG_PARAMS *StdHeader);
+VOID WriteAlink (IN UINT32 Index, IN UINT32 Data, IN AMD_CONFIG_PARAMS *StdHeader);
+VOID RwAlink (IN UINT32 Index, IN UINT32 AndMask, IN UINT32 OrMask, IN AMD_CONFIG_PARAMS *StdHeader);
+VOID ReadMem (IN UINT32 Address, IN UINT8 OpFlag, IN VOID *ValuePtr);
+VOID WriteMem (IN UINT32 Address, IN UINT8 OpFlag, IN VOID *ValuePtr);
+VOID RwMem (IN UINT32 Address, IN UINT8 OpFlag, IN UINT32 Mask, IN UINT32 Data);
+VOID ReadPci (IN UINT32 Address, IN UINT8 OpFlag, IN VOID *Value, IN AMD_CONFIG_PARAMS *StdHeader);
+VOID WritePci (IN UINT32 Address, IN UINT8 OpFlag, IN VOID *Value, IN AMD_CONFIG_PARAMS *StdHeader);
+VOID RwPci (IN UINT32 Address, IN UINT8 OpFlag, IN UINT32 Mask, IN UINT32 Data, IN AMD_CONFIG_PARAMS *StdHeader);
+VOID ProgramPciByteTable (IN REG8_MASK* pPciByteTable, IN UINT16 dwTableSize, IN AMD_CONFIG_PARAMS *StdHeader);
+VOID ProgramFchAcpiMmioTbl (IN ACPI_REG_WRITE *pAcpiTbl, IN AMD_CONFIG_PARAMS *StdHeader);
+VOID ProgramFchSciMapTbl (IN SCI_MAP_CONTROL *pSciMapTbl, IN FCH_RESET_DATA_BLOCK *FchResetDataBlock);
+VOID ProgramFchGpioTbl (IN GPIO_CONTROL *pGpioTbl);
+VOID ProgramFchSataPhyTbl (IN SATA_PHY_CONTROL *pSataPhyTbl, IN FCH_RESET_DATA_BLOCK *FchResetDataBlock);
+VOID GetChipSysMode (IN VOID *Value, IN AMD_CONFIG_PARAMS *StdHeader);
+BOOLEAN IsImcEnabled (IN AMD_CONFIG_PARAMS *StdHeader);
+VOID ReadPmio (IN UINT8 Address, IN UINT8 OpFlag, IN VOID *Value, IN AMD_CONFIG_PARAMS *StdHeader);
+VOID WritePmio (IN UINT8 Address, IN UINT8 OpFlag, IN VOID *Value, IN AMD_CONFIG_PARAMS *StdHeader);
+VOID RwPmio (IN UINT8 Address, IN UINT8 OpFlag, IN UINT32 AndMask, IN UINT32 OrMask, IN AMD_CONFIG_PARAMS *StdHeader);
+VOID ReadPmio2 (IN UINT8 Address, IN UINT8 OpFlag, IN VOID *Value, IN AMD_CONFIG_PARAMS *StdHeader);
+VOID WritePmio2 (IN UINT8 Address, IN UINT8 OpFlag, IN VOID *Value, IN AMD_CONFIG_PARAMS *StdHeader);
+VOID RwPmio2 (IN UINT8 Address, IN UINT8 OpFlag, IN UINT32 AndMask, IN UINT32 OrMask, IN AMD_CONFIG_PARAMS *StdHeader);
+VOID ReadBiosram (IN UINT8 Address, IN UINT8 OpFlag, IN VOID *Value, IN AMD_CONFIG_PARAMS *StdHeader);
+VOID WriteBiosram (IN UINT8 Address, IN UINT8 OpFlag, IN VOID *Value, IN AMD_CONFIG_PARAMS *StdHeader);
+VOID GetFchAcpiMmioBase (OUT UINT32 *AcpiMmioBase, IN AMD_CONFIG_PARAMS *StdHeader);
+VOID GetFchAcpiPmBase (OUT UINT16 *AcpiPmBase, IN AMD_CONFIG_PARAMS *StdHeader);
+UINT8 ReadFchSleepType (IN AMD_CONFIG_PARAMS *StdHeader);
+UINT8 ReadFchChipsetRevision (IN AMD_CONFIG_PARAMS *StdHeader);
+
+///
+/// Fch Ab Routines
+///
+/// Pei Phase
+///
+VOID FchInitResetAb (IN VOID* FchDataPtr);
+VOID FchProgramAbPowerOnReset (IN VOID* FchDataPtr);
+///
+/// Dxe Phase
+///
+VOID FchInitEnvAb (IN VOID* FchDataPtr);
+VOID FchInitEnvAbSpecial (IN VOID* FchDataPtr);
+VOID FchInitMidAb (IN VOID* FchDataPtr);
+VOID FchInitLateAb (IN VOID* FchDataPtr);
+///
+/// Other Public Routines
+///
+VOID FchInitEnvAbLinkInit (IN VOID* FchDataPtr);
+BOOLEAN IsUmiOneLaneGen1Mode (IN AMD_CONFIG_PARAMS *StdHeader);
+VOID FchAbLateProgram (IN VOID* FchDataPtr);
+
+///
+/// Fch Pcie Routines
+///
+/// Pei Phase
+///
+VOID FchInitResetPcie (IN VOID* FchDataPtr);
+///
+/// Dxe Phase
+///
+VOID FchInitEnvPcie (IN VOID* FchDataPtr);
+VOID FchInitMidPcie (IN VOID* FchDataPtr);
+VOID FchInitLatePcie (IN VOID* FchDataPtr);
+VOID ProgramPcieNativeMode (IN VOID* FchDataPtr);
+
+///
+/// Fch Gpp Routines
+///
+/// Pei Phase
+///
+VOID FchInitResetGpp (IN VOID* FchDataPtr);
+VOID ProgramFchGppInitReset (IN FCH_GPP *FchGpp, IN AMD_CONFIG_PARAMS *StdHeader);
+VOID FchResetPcie (IN RESET_BLOCK ResetBlock, IN RESET_OP ResetOp, IN AMD_CONFIG_PARAMS *StdHeader);
+
+///
+/// Dxe Phase
+///
+VOID FchInitEnvGpp (IN VOID* FchDataPtr);
+VOID FchInitMidGpp (IN VOID* FchDataPtr);
+VOID FchInitLateGpp (IN VOID* FchDataPtr);
+
+///
+/// Common Gpp Routines
+///
+VOID ProgramGppTogglePcieReset (IN BOOLEAN DoToggling, IN AMD_CONFIG_PARAMS *StdHeader);
+VOID FchGppForceGen1 (IN FCH_GPP *FchGpp, IN CONST UINT8 ActivePorts, IN AMD_CONFIG_PARAMS *StdHeader);
+VOID FchGppForceGen2 (IN FCH_GPP *FchGpp, IN CONST UINT8 ActivePorts, IN AMD_CONFIG_PARAMS *StdHeader);
+VOID FchGppDynamicPowerSaving (IN FCH_GPP *FchGpp, IN AMD_CONFIG_PARAMS *StdHeader);
+UINT8 GppPortPollingLtssm (IN FCH_GPP *FchGpp, IN UINT8 ActivePorts, IN BOOLEAN IsGen2, IN AMD_CONFIG_PARAMS *StdHeader);
+VOID GppGen2Workaround (IN FCH_GPP *FchGpp, IN AMD_CONFIG_PARAMS *StdHeader);
+UINT8 FchFindPciCap (IN UINT32 PciAddress, IN UINT8 TargetCapId, IN AMD_CONFIG_PARAMS *StdHeader);
+VOID FchGppPortInit (IN FCH_GPP *FchGpp, IN AMD_CONFIG_PARAMS *StdHeader);
+VOID FchGppPortInitPhaseII (IN FCH_GPP *FchGpp, IN AMD_CONFIG_PARAMS *StdHeader);
+VOID FchGppPortInitS3Phase (IN FCH_GPP *FchGpp, IN AMD_CONFIG_PARAMS *StdHeader);
+UINT32 GppGetFchTempBus (IN AMD_CONFIG_PARAMS *StdHeader);
+
+///
+/// Fch Azalia Routines
+///
+/// Pei Phase
+///
+VOID FchInitResetAzalia (IN VOID *FchDataPtr);
+///
+/// Dxe Phase
+///
+VOID FchInitEnvAzalia (IN VOID *FchDataPtr);
+VOID FchInitMidAzalia (IN VOID *FchDataPtr);
+VOID FchInitLateAzalia (IN VOID *FchDataPtr);
+
+
+///
+/// Fch GEC Routines
+///
+/// Pei Phase
+///
+VOID FchInitResetGec (IN VOID* FchDataPtr);
+///
+/// Dxe Phase
+///
+VOID FchInitEnvGec (IN VOID* FchDataPtr);
+VOID FchInitMidGec (IN VOID* FchDataPtr);
+VOID FchInitLateGec (IN VOID* FchDataPtr);
+///
+/// Other Public Routines
+///
+VOID FchInitGecController (IN VOID* FchDataPtr);
+VOID FchSwInitGecBootRom (IN VOID* FchDataPtr);
+
+///
+/// Fch HwAcpi Routines
+///
+/// Pei Phase
+///
+VOID FchInitResetHwAcpiP (IN VOID *FchDataPtr);
+VOID FchInitResetHwAcpi (IN VOID *FchDataPtr);
+VOID ProgramFchHwAcpiResetP (IN VOID *FchDataPtr);
+///
+/// Dxe Phase
+///
+VOID FchInitEnvHwAcpiP (IN VOID *FchDataPtr);
+VOID FchInitEnvHwAcpi (IN VOID *FchDataPtr);
+VOID ProgramEnvPFchAcpiMmio (IN VOID *FchDataPtr);
+VOID ProgramFchEnvHwAcpiPciReg (IN VOID *FchDataPtr);
+VOID ProgramSpecificFchInitEnvAcpiMmio (IN VOID *FchDataPtr);
+VOID ProgramFchEnvSpreadSpectrum (IN VOID *FchDataPtr);
+VOID FchInitMidHwAcpi (IN VOID *FchDataPtr);
+VOID FchInitLateHwAcpi (IN VOID *FchDataPtr);
+
+///
+/// Other Public Routines
+///
+VOID HpetInit (IN VOID *FchDataPtr);
+VOID C3PopupSetting (IN VOID *FchDataPtr);
+VOID MtC1eEnable (IN VOID *FchDataPtr);
+VOID GcpuRelatedSetting (IN VOID *FchDataPtr);
+VOID StressResetModeLate (IN VOID *FchDataPtr);
+
+///
+/// Fch Hwm Routines
+///
+/// Pei Phase
+///
+VOID FchInitResetHwm (IN VOID* FchDataPtr);
+///
+/// Dxe Phase
+///
+VOID FchInitEnvHwm (IN VOID* FchDataPtr);
+VOID FchInitMidHwm (IN VOID* FchDataPtr);
+VOID FchInitLateHwm (IN VOID* FchDataPtr);
+///
+/// Other Public Routines
+///
+VOID HwmInitRegister (IN VOID* FchDataPtr);
+VOID HwmProcessParameter (IN VOID* FchDataPtr);
+VOID HwmSetRegister (IN VOID* FchDataPtr);
+VOID HwmGetCalibrationFactor (IN VOID* FchDataPtr);
+VOID HwmFchtsiAutoPolling (IN VOID* FchDataPtr);
+VOID HwmGetRawData (IN VOID* FchDataPtr);
+VOID HwmCaculate (IN VOID* FchDataPtr);
+VOID HwmFchtsiAutoPollingOff (IN VOID* FchDataPtr);
+VOID FchECfancontrolservice (IN VOID* FchDataPtr);
+
+
+///
+/// Fch Ide Routines
+///
+VOID FchInitEnvIde (IN VOID* FchDataPtr);
+VOID FchInitMidIde (IN VOID* FchDataPtr);
+VOID FchInitLateIde (IN VOID* FchDataPtr);
+
+
+///
+/// Fch Imc Routines
+///
+/// Pei Phase
+///
+VOID FchInitResetImc (IN VOID *FchDataPtr);
+VOID FchInitResetEc (IN VOID *FchDataPtr);
+///
+/// Dxe Phase
+///
+VOID FchInitEnvImc (IN VOID *FchDataPtr);
+VOID FchInitMidImc (IN VOID *FchDataPtr);
+VOID FchInitLateImc (IN VOID *FchDataPtr);
+VOID FchInitEnvEc (IN VOID *FchDataPtr);
+VOID FchInitMidEc (IN VOID *FchDataPtr);
+VOID FchInitLateEc (IN VOID *FchDataPtr);
+///
+/// Other Public Routines
+///
+VOID EnterEcConfig (IN AMD_CONFIG_PARAMS *StdHeader);
+VOID ExitEcConfig (IN AMD_CONFIG_PARAMS *StdHeader);
+VOID ReadEc8 (IN UINT8 Address, IN UINT8* Value, IN AMD_CONFIG_PARAMS *StdHeader);
+VOID WriteEc8 (IN UINT8 Address, IN UINT8* Value, IN AMD_CONFIG_PARAMS *StdHeader);
+VOID RwEc8 (IN UINT8 Address, IN UINT8 AndMask, IN UINT8 OrMask, IN AMD_CONFIG_PARAMS *StdHeader);
+VOID WriteECmsg (IN UINT8 Address, IN UINT8 OpFlag, IN VOID* Value, IN AMD_CONFIG_PARAMS *StdHeader);
+VOID ReadECmsg (IN UINT8 Address, IN UINT8 OpFlag, OUT VOID* Value, IN AMD_CONFIG_PARAMS *StdHeader);
+VOID WaitForEcLDN9MailboxCmdAck (IN AMD_CONFIG_PARAMS *StdHeader);
+
+VOID ImcSleep (IN VOID *FchDataPtr);
+VOID ImcEnableSurebootTimer (IN VOID *FchDataPtr);
+VOID ImcDisarmSurebootTimer (IN VOID *FchDataPtr);
+VOID ImcDisableSurebootTimer (IN VOID *FchDataPtr);
+VOID ImcWakeup (IN VOID *FchDataPtr);
+VOID ImcIdle (IN VOID *FchDataPtr);
+BOOLEAN ValidateImcFirmware (IN VOID *FchDataPtr);
+VOID SoftwareToggleImcStrapping (IN VOID *FchDataPtr);
+VOID ImcCrashReset (IN VOID *FchDataPtr);
+VOID SoftwareDisableImc (IN VOID *FchDataPtr);
+
+
+///
+/// Fch Ir Routines
+///
+/// Dxe Phase
+///
+VOID FchInitEnvIr (IN VOID* FchDataPtr);
+VOID FchInitMidIr (IN VOID* FchDataPtr);
+VOID FchInitLateIr (IN VOID* FchDataPtr);
+
+///
+/// Fch Pcib Routines
+///
+/// Pei Phase
+///
+VOID FchInitResetPcib (IN VOID* FchDataPtr);
+VOID FchInitResetPcibPort80Enable (IN VOID* FchDataPtr);
+
+///
+/// Dxe Phase
+///
+VOID FchInitEnvPcib (IN VOID* FchDataPtr);
+VOID FchInitMidPcib (IN VOID* FchDataPtr);
+VOID FchInitLatePcib (IN VOID* FchDataPtr);
+
+
+///
+/// Fch SATA Routines
+///
+/// Pei Phase
+///
+VOID FchInitResetSata (IN VOID *FchDataPtr);
+VOID FchInitResetSataProgram (IN VOID *FchDataPtr);
+///
+/// Dxe Phase
+///
+VOID FchInitMidSata (IN VOID *FchDataPtr);
+VOID FchInitEnvSata (IN VOID *FchDataPtr);
+VOID FchInitEnvProgramSataPciRegs (IN VOID *FchDataPtr);
+VOID FchInitMidProgramSataRegs (IN VOID *FchDataPtr);
+VOID FchInitLateProgramSataRegs (IN VOID *FchDataPtr);
+
+VOID FchInitLateSata (IN VOID *FchDataPtr);
+VOID FchInitEnvSataIde (IN VOID *FchDataPtr);
+VOID FchInitMidSataIde (IN VOID *FchDataPtr);
+VOID FchInitLateSataIde (IN VOID *FchDataPtr);
+VOID FchInitEnvSataAhci (IN VOID *FchDataPtr);
+VOID FchInitMidSataAhci (IN VOID *FchDataPtr);
+VOID FchInitLateSataAhci (IN VOID *FchDataPtr);
+VOID FchInitEnvSataRaid (IN VOID *FchDataPtr);
+VOID FchInitMidSataRaid (IN VOID *FchDataPtr);
+VOID FchInitLateSataRaid (IN VOID *FchDataPtr);
+VOID FchInitEnvSataIde2Ahci (IN VOID *FchDataPtr);
+VOID FchInitMidSataIde2Ahci (IN VOID *FchDataPtr);
+VOID FchInitLateSataIde2Ahci (IN VOID *FchDataPtr);
+
+VOID SataAhciSetDeviceNumMsi (IN VOID *FchDataPtr);
+VOID SataRaidSetDeviceNumMsi (IN VOID *FchDataPtr);
+VOID SataIde2AhciSetDeviceNumMsi (IN VOID *FchDataPtr);
+VOID SataSetIrqIntResource (IN VOID *FchDataPtr, IN AMD_CONFIG_PARAMS *StdHeader);
+VOID SataBar5setting (IN VOID *FchDataPtr, IN UINT32 *Bar5Ptr);
+VOID SataEnableWriteAccess (IN AMD_CONFIG_PARAMS *StdHeader);
+VOID SataDisableWriteAccess (IN AMD_CONFIG_PARAMS *StdHeader);
+VOID SataSetDeviceNumMsi (IN VOID *FchDataPtr);
+VOID FchSataSetDeviceNumMsi (IN VOID *FchDataPtr);
+VOID ShutdownUnconnectedSataPortClock (IN VOID *FchDataPtr, IN UINT32 Bar5);
+VOID FchShutdownUnconnectedSataPortClock (IN VOID *FchDataPtr, IN UINT32 Bar5);
+VOID SataDriveDetection (IN VOID *FchDataPtr, IN UINT32 *Bar5Ptr);
+VOID FchSataDriveDetection (IN VOID *FchDataPtr, IN UINT32 *Bar5Ptr);
+VOID FchSataGpioInitial (IN VOID *FchDataPtr);
+VOID SataBar5RegSet (IN VOID *FchDataPtr);
+VOID SataSetPortGenMode (IN VOID *FchDataPtr);
+VOID FchSataSetPortGenMode (IN VOID *FchDataPtr);
+VOID FchProgramSataPhy (IN AMD_CONFIG_PARAMS *StdHeader);
+VOID FchSataDriveFpga (IN VOID *FchDataPtr);
+VOID FchInitEnvSataRaidProgram (IN VOID *FchDataPtr);
+
+///
+/// FCH USB Controller Public Function
+///
+/// Pei Phase
+///
+VOID FchInitResetUsb (IN VOID *FchDataPtr);
+VOID FchInitResetOhci (IN VOID *FchDataPtr);
+VOID FchInitResetEhci (IN VOID *FchDataPtr);
+VOID FchInitResetXhci (IN VOID *FchDataPtr);
+VOID FchInitResetXhciProgram (IN VOID *FchDataPtr);
+///
+/// Dxe Phase
+///
+VOID FchInitEnvUsb (IN VOID *FchDataPtr);
+VOID FchInitMidUsb (IN VOID *FchDataPtr);
+VOID FchInitLateUsb (IN VOID *FchDataPtr);
+VOID FchInitEnvUsbOhci (IN VOID *FchDataPtr);
+VOID FchInitMidUsbOhci (IN VOID *FchDataPtr);
+VOID FchInitLateUsbOhci (IN VOID *FchDataPtr);
+VOID FchInitEnvUsbEhci (IN VOID *FchDataPtr);
+VOID FchInitMidUsbEhci (IN VOID *FchDataPtr);
+VOID FchInitLateUsbEhci (IN VOID *FchDataPtr);
+VOID FchInitEnvUsbXhci (IN VOID *FchDataPtr);
+VOID FchInitMidUsbXhci (IN VOID *FchDataPtr);
+VOID FchInitLateUsbXhci (IN VOID *FchDataPtr);
+VOID FchInitMidUsbOhci1 (IN VOID *FchDataPtr);
+VOID FchInitMidUsbOhci2 (IN VOID *FchDataPtr);
+VOID FchInitMidUsbOhci3 (IN VOID *FchDataPtr);
+VOID FchInitMidUsbOhci4 (IN VOID *FchDataPtr);
+VOID FchInitMidUsbEhci1 (IN FCH_DATA_BLOCK *FchDataPtr);
+VOID FchInitMidUsbEhci2 (IN FCH_DATA_BLOCK *FchDataPtr);
+VOID FchInitMidUsbEhci3 (IN FCH_DATA_BLOCK *FchDataPtr);
+///
+/// Other Public Routines
+///
+VOID FchSetUsbEnableReg (IN FCH_DATA_BLOCK *FchDataPtr);
+VOID FchOhciInitAfterPciInit (IN UINT32 Value, IN FCH_DATA_BLOCK* FchDataPtr);
+VOID FchEhciInitAfterPciInit (IN UINT32 Value, IN FCH_DATA_BLOCK* FchDataPtr);
+VOID FchXhciInitBeforePciInit (IN FCH_DATA_BLOCK* FchDataPtr);
+VOID FchXhciInitIndirectReg (IN FCH_DATA_BLOCK* FchDataPtr);
+VOID FchInitLateUsbXhciProgram (IN VOID *FchDataPtr);
+VOID FchXhciPowerSavingProgram (IN FCH_DATA_BLOCK* FchDataPtr);
+VOID FchXhciUsbPhyCalibrated (IN FCH_DATA_BLOCK* FchDataPtr);
+
+///
+/// Fch Sd Routines
+///
+VOID FchInitEnvSd (IN VOID *FchDataPtr);
+VOID FchInitMidSd (IN VOID *FchDataPtr);
+VOID FchInitLateSd (IN VOID *FchDataPtr);
+
+///
+/// Other Public Routines
+///
+
+VOID FchInitEnvSdProgram (IN VOID *FchDataPtr);
+
+///
+/// Fch Spi Routines
+///
+/// Pei Phase
+///
+VOID FchInitResetSpi (IN VOID *FchDataPtr);
+VOID FchInitResetLpc (IN VOID *FchDataPtr);
+VOID FchInitResetLpcProgram (IN VOID *FchDataPtr);
+///
+/// Dxe Phase
+///
+VOID FchInitEnvSpi (IN VOID *FchDataPtr);
+VOID FchInitMidSpi (IN VOID *FchDataPtr);
+VOID FchInitLateSpi (IN VOID *FchDataPtr);
+VOID FchInitEnvLpc (IN VOID *FchDataPtr);
+VOID FchInitMidLpc (IN VOID *FchDataPtr);
+VOID FchInitLateLpc (IN VOID *FchDataPtr);
+VOID FchInitEnvLpcProgram (IN VOID *FchDataPtr);
+///
+/// Other Public Routines
+///
+VOID FchSpiUnlock (IN VOID *FchDataPtr);
+VOID FchSpiLock (IN VOID *FchDataPtr);
+
+/*--------------------------- Documentation Pages ---------------------------*/
+VOID FchStall (IN UINT32 uSec, IN AMD_CONFIG_PARAMS *StdHeader);
+VOID CimFchStall (IN UINT32 uSec, IN AMD_CONFIG_PARAMS *StdHeader);
+VOID FchPciReset (IN AMD_CONFIG_PARAMS *StdHeader);
+VOID OutPort80 (IN UINT32 pcode, IN AMD_CONFIG_PARAMS *StdHeader);
+VOID OutPort1080 (IN UINT32 pcode, IN AMD_CONFIG_PARAMS *StdHeader);
+VOID GetEfuseStatus (IN VOID* Value, IN AMD_CONFIG_PARAMS *StdHeader);
+VOID TurnOffCG2 (OUT VOID);
+VOID BackUpCG2 (OUT VOID);
+VOID FchCopyMem (IN VOID* pDest, IN VOID* pSource, IN UINTN Length);
+VOID* GetRomSigPtr (IN UINTN* RomSigPtr, IN AMD_CONFIG_PARAMS *StdHeader);
+VOID RwXhciIndReg (IN UINT32 Index, IN UINT32 AndMask, IN UINT32 OrMask, IN AMD_CONFIG_PARAMS *StdHeader);
+VOID RwXhci0IndReg (IN UINT32 Index, IN UINT32 AndMask, IN UINT32 OrMask, IN AMD_CONFIG_PARAMS *StdHeader);
+VOID RwXhci1IndReg (IN UINT32 Index, IN UINT32 AndMask, IN UINT32 OrMask, IN AMD_CONFIG_PARAMS *StdHeader);
+VOID ReadXhci0Phy (IN UINT32 Port, IN UINT32 Address, IN UINT32 *Value, IN AMD_CONFIG_PARAMS *StdHeader);
+VOID ReadXhci1Phy (IN UINT32 Port, IN UINT32 Address, IN UINT32 *Value, IN AMD_CONFIG_PARAMS *StdHeader);
+VOID AcLossControl (IN UINT8 AcLossControlValue);
+VOID FchVgaInit (OUT VOID);
+VOID RecordFchConfigPtr (IN UINT32 FchConfigPtr);
+VOID ValidateFchVariant (IN VOID *FchDataPtr);
+VOID RecordSmiStatus (IN AMD_CONFIG_PARAMS *StdHeader);
+VOID ClearAllSmiStatus (IN AMD_CONFIG_PARAMS *StdHeader);
+BOOLEAN IsGCPU (IN VOID *FchDataPtr);
+BOOLEAN IsExternalClockMode (IN VOID *FchDataPtr);
+VOID SbSleepTrapControl (IN BOOLEAN SleepTrap);
+
+AGESA_STATUS
+FchSpiTransfer (
+ IN UINT8 PrefixCode,
+ IN UINT8 Opcode,
+ IN OUT UINT8 *DataPtr,
+ IN UINT8 *AddressPtr,
+ IN UINT8 Length,
+ IN BOOLEAN WriteFlag,
+ IN BOOLEAN AddressFlag,
+ IN BOOLEAN DataFlag,
+ IN BOOLEAN FinishedFlag
+ );
+
+BOOLEAN
+FchPlatformSpiQe (
+ IN VOID *FchDataPtr
+ );
+
+#endif
+
diff --git a/src/vendorcode/amd/pi/00630F01/Proc/Fch/Fch.h b/src/vendorcode/amd/pi/00630F01/Proc/Fch/Fch.h
new file mode 100644
index 0000000..6685c67
--- /dev/null
+++ b/src/vendorcode/amd/pi/00630F01/Proc/Fch/Fch.h
@@ -0,0 +1,2285 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * FCH registers definition
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: FCH
+ * @e \$Revision: 281181 $ @e \$Date: 2013-12-18 02:18:55 -0600 (Wed, 18 Dec 2013) $
+ *
+ */
+/*
+*****************************************************************************
+*
+ * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+****************************************************************************
+*/
+#define FCH_REVISION "0.0.5.0"
+#define FCH_ID "FCH_A05"
+#define FCH_VERSION 0x0000
+
+/**
+ * @page fchinitguide FCH implement phase in AGESA
+ *
+ * FCH provides below access to supported FCH service functions
+ * and data.
+ * - @subpage fchreset "FCH_INIT_RESET"
+ * - @subpage fchenv "FCH_INIT_ENV"
+ * - @subpage fchmid "FCH_INIT_MID"
+ * - @subpage fchlate "FCH_INIT_LATE"
+ * - @subpage fchs3early "FCH_INIT_S3_EARLY_RESTORE"
+ * - @subpage fchs3late "FCH_INIT_S3_LATE_RESTORE"
+ * - @subpage fchsmm "FCH_SMM_SERVICE"
+ * - @subpage fchsmmacpion "FCH_SMM_ACPION"
+ */
+
+/*--------------------------- Documentation Pages ---------------------------*/
+/**
+ * @page fchreset FCH_INIT_RESET
+ * @section FCH_INIT_RESET Interface Call
+ * @par
+ * Initialize structure referenced by FCH_RESET_DATA_BLOCK to default recommended value.
+ * @subsection FCH_INIT_RESET_CallIn Call Prototype
+ * @par
+ * AGESA_STATUS FchInitReset (IN AMD_RESET_PARAMS *ResetParams);
+ * @subsection FCH_INIT_RESET_CallOut Prepare for Callout
+ * @par
+ * Not Applicable (Not necessary for the current implementation)
+ * @subsection FCH_INIT_RESET_Config Prepare for Configuration Data.
+ * @par
+ * <TABLE border="0">
+ * <TR><TD class="indexkey" width=380> BUILD_OPT_CFG::CfgSmbus0BaseAddress </TD><TD class="indexvalue"><B>Required </B></TD></TR>
+ * <TR><TD class="indexkey" width=380> BUILD_OPT_CFG::CfgSmbus1BaseAddress </TD><TD class="indexvalue"><B>Required </B></TD></TR>
+ * <TR><TD class="indexkey" width=380> BUILD_OPT_CFG::CfgSioPmeBaseAddress </TD><TD class="indexvalue"><B>Required </B></TD></TR>
+ * <TR><TD class="indexkey" width=380> BUILD_OPT_CFG::CfgWatchDogTimerBase </TD><TD class="indexvalue"><B>Required </B></TD></TR>
+ * <TR><TD class="indexkey" width=380> BUILD_OPT_CFG::CfgGecShadowRomBase </TD><TD class="indexvalue"><B>Required </B></TD></TR>
+ * <TR><TD class="indexkey" width=380> BUILD_OPT_CFG::CfgSpiRomBaseAddress </TD><TD class="indexvalue"><B>Required </B></TD></TR>
+ * <TR><TD class="indexkey" width=380> BUILD_OPT_CFG::CfgAcpiPm1EvtBlkAddr </TD><TD class="indexvalue"><B>Required </B></TD></TR>
+ * <TR><TD class="indexkey" width=380> BUILD_OPT_CFG::CfgAcpiPm1CntBlkAddr </TD><TD class="indexvalue"><B>Required </B></TD></TR>
+ * <TR><TD class="indexkey" width=380> BUILD_OPT_CFG::CfgAcpiPmTmrBlkAddr </TD><TD class="indexvalue"><B>Required </B></TD></TR>
+ * <TR><TD class="indexkey" width=380> BUILD_OPT_CFG::CfgCpuControlBlkAddr </TD><TD class="indexvalue"><B>Required </B></TD></TR>
+ * <TR><TD class="indexkey" width=380> BUILD_OPT_CFG::CfgAcpiGpe0BlkAddr </TD><TD class="indexvalue"><B>Required </B></TD></TR>
+ * <TR><TD class="indexkey" width=380> BUILD_OPT_CFG::CfgSmiCmdPortAddr </TD><TD class="indexvalue"><B>Required </B></TD></TR>
+ * <TR><TD class="indexkey" width=380> BUILD_OPT_CFG::CfgAcpiPmaCntBlkAddr </TD><TD class="indexvalue"><B>Required </B></TD></TR>
+ * <TR><TD class="indexkey" width=380> FCH_RESET_INTERFACE::SataEnable </TD><TD class="indexvalue"><B>Optional </B></TD></TR>
+ * <TR><TD class="indexkey" width=380> FCH_RESET_INTERFACE::IdeEnable </TD><TD class="indexvalue"><B>Optional </B></TD></TR>
+ * </TABLE>
+ *
+ */
+
+/*--------------------------- Documentation Pages ---------------------------*/
+/**
+ * @page fchenv FCH_INIT_ENV
+ * @section FCH_INIT_ENV Interface Call
+ * @par
+ * Initialize structure referenced by FCH_DATA_BLOCK to default recommended value.
+ * @subsection FCH_INIT_ENV_CallIn Call Prototype
+ * @par
+ * AGESA_STATUS FchInitEnv (IN AMD_ENV_PARAMS *EnvParams);
+ * @subsection FCH_INIT_ENV_CallOut Prepare for Callout
+ * @par
+ * Not Applicable (Not necessary for the current implementation)
+ * @subsection FCH_INIT_ENV_Config Prepare for Configuration Data.
+ * @par
+ * <TABLE border="0">
+ * <TR><TD class="indexkey" width=380> FCH_INTERFACE::SdConfig </TD><TD class="indexvalue"><B>Optional </B></TD></TR>
+ * <TR><TD class="indexkey" width=380> FCH_INTERFACE::AzaliaController </TD><TD class="indexvalue"><B>Optional </B></TD></TR>
+ * <TR><TD class="indexkey" width=380> FCH_INTERFACE::IrConfig </TD><TD class="indexvalue"><B>Optional </B></TD></TR>
+ * <TR><TD class="indexkey" width=380> FCH_INTERFACE::SataClass </TD><TD class="indexvalue"><B>Optional </B></TD></TR>
+ * <TR><TD class="indexkey" width=380> FCH_INTERFACE::SataEnable </TD><TD class="indexvalue"><B>Optional </B></TD></TR>
+ * <TR><TD class="indexkey" width=380> FCH_INTERFACE::SataIdeMode </TD><TD class="indexvalue"><B>Optional </B></TD></TR>
+ * <TR><TD class="indexkey" width=380> FCH_INTERFACE::Ohci1Enable </TD><TD class="indexvalue"><B>Optional </B></TD></TR>
+ * <TR><TD class="indexkey" width=380> FCH_INTERFACE::Ohci2Enable </TD><TD class="indexvalue"><B>Optional </B></TD></TR>
+ * <TR><TD class="indexkey" width=380> FCH_INTERFACE::Ohci3Enable </TD><TD class="indexvalue"><B>Optional </B></TD></TR>
+ * <TR><TD class="indexkey" width=380> FCH_INTERFACE::Ohci4Enable </TD><TD class="indexvalue"><B>Optional </B></TD></TR>
+ * </TABLE>
+ *
+ */
+
+/*--------------------------- Documentation Pages ---------------------------*/
+/**
+ * @page fchmid FCH_INIT_MID
+ * @section FCH_INIT_MID Interface Call
+ * @par
+ * Initialize structure referenced by FCH_DATA_BLOCK to default recommended value.
+ * @subsection FCH_INIT_MID_CallIn Call Prototype
+ * @par
+ * AGESA_STATUS FchInitMid (IN AMD_MID_PARAMS *MidParams);
+ * @subsection FCH_INIT_MID_CallOut Prepare for Callout
+ * @par
+ * Not Applicable (Not necessary for the current implementation)
+ * @subsection FCH_INIT_MID_Config Prepare for Configuration Data.
+ * @par
+ * <TABLE border="0">
+ * <TR><TD class="indexkey" width=380> FCH_INTERFACE::AzaliaController </TD><TD class="indexvalue"><B>Optional </B></TD></TR>
+ * <TR><TD class="indexkey" width=380> FCH_INTERFACE::SataClass </TD><TD class="indexvalue"><B>Optional </B></TD></TR>
+ * <TR><TD class="indexkey" width=380> FCH_INTERFACE::SataEnable </TD><TD class="indexvalue"><B>Optional </B></TD></TR>
+ * <TR><TD class="indexkey" width=380> FCH_INTERFACE::IdeEnable </TD><TD class="indexvalue"><B>Optional </B></TD></TR>
+ * </TABLE>
+ *
+ */
+
+/*--------------------------- Documentation Pages ---------------------------*/
+/**
+ * @page fchlate FCH_INIT_LATE
+ * @section FCH_INIT_LATE Interface Call
+ * @par
+ * Initialize structure referenced by FCH_DATA_BLOCK to default recommended value.
+ * @subsection FCH_INIT_LATE_CallIn Call Prototype
+ * @par
+ * AGESA_STATUS FchInitLate (IN AMD_S3SAVE_PARAMS *LateParams);
+ * @subsection FCH_INIT_LATE_CallOut Prepare for Callout
+ * @par
+ * Not Applicable (Not necessary for the current implementation)
+ * @subsection FCH_INIT_LATE_Config Prepare for Configuration Data.
+ * @par
+ * <TABLE border="0">
+ * <TR><TD class="indexkey" width=380> FCH_INTERFACE::SataClass </TD><TD class="indexvalue"><B>Optional </B></TD></TR>
+ * <TR><TD class="indexkey" width=380> FCH_INTERFACE::SataEnable </TD><TD class="indexvalue"><B>Optional </B></TD></TR>
+ * <TR><TD class="indexkey" width=380> BUILD_OPT_CFG::CfgSpiRomBaseAddress </TD><TD class="indexvalue"><B>Required </B></TD></TR>
+ * </TABLE>
+ *
+ */
+
+/*--------------------------- Documentation Pages ---------------------------*/
+/**
+ * @page fchs3early FCH_INIT_S3_EARLY_RESTORE
+ * @section FCH_INIT_S3_EARLY_RESTORE Interface Call
+ * @par
+ * Initialize structure referenced by FCH_DATA_BLOCK to default recommended value.
+ * @subsection FCH_INIT_S3_EARLY_RESTORE_CallIn Call Prototype
+ * @par
+ * VOID FchInitS3EarlyRestore (IN FCH_DATA_BLOCK *FchDataPtr);
+ * @subsection FCH_INIT_S3_EARLY_RESTORE_CallOut Prepare for Callout
+ * @par
+ * Not Applicable (Not necessary for the current implementation)
+ * @subsection FCH_INIT_S3_EARLY_RESTORE_Config Prepare for Configuration Data.
+ * @par
+ * <TABLE border="0">
+ * <TR><TD class="indexkey" width=380> FCH_INTERFACE::SdConfig </TD><TD class="indexvalue"><B>Optional </B></TD></TR>
+ * <TR><TD class="indexkey" width=380> FCH_INTERFACE::AzaliaController </TD><TD class="indexvalue"><B>Optional </B></TD></TR>
+ * <TR><TD class="indexkey" width=380> FCH_INTERFACE::IrConfig </TD><TD class="indexvalue"><B>Optional </B></TD></TR>
+ * <TR><TD class="indexkey" width=380> FCH_INTERFACE::SataClass </TD><TD class="indexvalue"><B>Optional </B></TD></TR>
+ * <TR><TD class="indexkey" width=380> FCH_INTERFACE::SataEnable </TD><TD class="indexvalue"><B>Optional </B></TD></TR>
+ * <TR><TD class="indexkey" width=380> FCH_INTERFACE::SataIdeMode </TD><TD class="indexvalue"><B>Optional </B></TD></TR>
+ * <TR><TD class="indexkey" width=380> FCH_INTERFACE::Ohci1Enable </TD><TD class="indexvalue"><B>Optional </B></TD></TR>
+ * <TR><TD class="indexkey" width=380> FCH_INTERFACE::Ohci2Enable </TD><TD class="indexvalue"><B>Optional </B></TD></TR>
+ * <TR><TD class="indexkey" width=380> FCH_INTERFACE::Ohci3Enable </TD><TD class="indexvalue"><B>Optional </B></TD></TR>
+ * <TR><TD class="indexkey" width=380> FCH_INTERFACE::Ohci4Enable </TD><TD class="indexvalue"><B>Optional </B></TD></TR>
+ * </TABLE>
+ *
+ */
+
+/*--------------------------- Documentation Pages ---------------------------*/
+/**
+ * @page fchs3late FCH_INIT_S3_LATE_RESTORE
+ * @section FCH_INIT_S3_LATE_RESTORE Interface Call
+ * @par
+ * Initialize structure referenced by FCH_DATA_BLOCK to default recommended value.
+ * @subsection FCH_INIT_S3_LATE_RESTORE_CallIn Call Prototype
+ * @par
+ * VOID FchInitS3LateRestore (IN FCH_DATA_BLOCK *FchDataPtr);
+ * @subsection FCH_INIT_S3_LATE_RESTORE_CallOut Prepare for Callout
+ * @par
+ * Not Applicable (Not necessary for the current implementation)
+ * @subsection FCH_INIT_S3_LATE_RESTORE_Config Prepare for Configuration Data.
+ * @par
+ * <TABLE border="0">
+ * <TR><TD class="indexkey" width=380> FCH_INTERFACE::AzaliaController </TD><TD class="indexvalue"><B>Optional </B></TD></TR>
+ * <TR><TD class="indexkey" width=380> FCH_INTERFACE::SataClass </TD><TD class="indexvalue"><B>Optional </B></TD></TR>
+ * <TR><TD class="indexkey" width=380> FCH_INTERFACE::SataEnable </TD><TD class="indexvalue"><B>Optional </B></TD></TR>
+ * <TR><TD class="indexkey" width=380> FCH_INTERFACE::IdeEnable </TD><TD class="indexvalue"><B>Optional </B></TD></TR>
+ * <TR><TD class="indexkey" width=380> BUILD_OPT_CFG::CfgSpiRomBaseAddress </TD><TD class="indexvalue"><B>Required </B></TD></TR>
+ * </TABLE>
+ *
+ */
+
+/*--------------------------- Documentation Pages ---------------------------*/
+/**
+ * @page fchsmm FCH_SMM_SERVICE
+ * @section FCH_SMM_SERVICE Interface Call
+ * Initialize structure referenced by FCHCFG to default recommended value.
+ * @subsection FCH_SMM_SERVICE_CallIn Call Prototype
+ * @par
+ * FchSmmService ((FCHCFG*)pConfig) (Followed PH Interface)
+ * @subsection FCH_SMM_SERVICE_CallID Service ID
+ * @par
+ * <TABLE border="0">
+ * <TR><TD class="indexkey" width=380> FCH_SMM_SERVICE --> 0x00010060 </TD></TR>
+ * </TABLE>
+ * @subsection FCH_SMM_SERVICE_CallOut Prepare for Callout
+ * @par
+ * Not Applicable (Not necessary for the current implementation)
+ * @subsection FCH_SMM_SERVICE_Config Prepare for Configuration Data.
+ * @par
+ * Not necessary on current implementation
+ *
+ */
+#define FCH_SMM_SERVICE 0x00010060ul
+/*--------------------------- Documentation Pages ---------------------------*/
+/**
+ * @page fchsmmacpion FCH_SMM_ACPION
+ * @section FCH_SMM_ACPION Interface Call
+ * Initialize structure referenced by FCHCFG to default recommended value.
+ * @subsection FCH_SMM_ACPION_CallIn Call Prototype
+ * @par
+ * FchSmmAcpiOn ((FCHCFG*)pConfig) (Followed PH Interface)
+ * @subsection FCH_SMM_ACPION_CallID Service ID
+ * @par
+ * <TABLE border="0">
+ * <TR><TD class="indexkey" width=380> FCH_SMM_ACPION --> 0x00010061 </TD></TR>
+ * </TABLE>
+ * @subsection FCH_SMM_ACPION_CallOut Prepare for Callout
+ * @par
+ * Not Applicable (Not necessary for the current implementation)
+ * @subsection FCH_SMM_ACPION_Config Prepare for Configuration Data.
+ * @par
+ * Not necessary on current implementation
+ *
+ */
+#define FCH_SMM_ACPION 0x00010061ul
+
+#ifndef OEM_CALLBACK_BASE
+ #define OEM_CALLBACK_BASE 0x00010100ul
+#endif
+
+//0x00 - 0x0F callback functions are reserved for bootblock
+#define SATA_PHY_PROGRAMMING OEM_CALLBACK_BASE + 0x10
+#define PULL_UP_PULL_DOWN_SETTINGS OEM_CALLBACK_BASE + 0x20
+/*--------------------------- Documentation Pages ---------------------------*/
+/**
+ * @page CB_SBGPP_RESET_ASSERT_Page CB_SBGPP_RESET_ASSERT
+ * @section CB_SBGPP_RESET_ASSERT Interface Call
+ * Initialize structure referenced by FCHCFG to default recommended value.
+ * @subsection CB_SBGPP_RESET_ASSERT_CallID Service ID
+ * @par
+ * <TABLE border="0">
+ * <TR><TD class="indexkey" width=380> CB_SBGPP_RESET_ASSERT --> 0x00010130 </TD></TR>
+ * </TABLE>
+ * @subsection CB_SBGPP_RESET_ASSERT_Config Prepare for Configuration Data.
+ * @par
+ * Not necessary on current implementation
+ *
+ */
+#define CB_SBGPP_RESET_ASSERT OEM_CALLBACK_BASE + 0x30
+/*--------------------------- Documentation Pages ---------------------------*/
+/**
+ * @page CB_SBGPP_RESET_DEASSERT_Page CB_SBGPP_RESET_DEASSERT
+ * @section CB_SBGPP_RESET_DEASSERT Interface Call
+ * Initialize structure referenced by FCHCFG to default recommended value.
+ * @subsection CB_SBGPP_RESET_DEASSERT _CallID Service ID
+ * @par
+ * <TABLE border="0">
+ * <TR><TD class="indexkey" width=380> CB_SBGPP_RESET_DEASSERT --> 0x00010131 </TD></TR>
+ * </TABLE>
+ * @subsection CB_SBGPP_RESET_DEASSERT _Config Prepare for Configuration Data.
+ * @par
+ * Not necessary on current implementation
+ *
+ */
+#define CB_SBGPP_RESET_DEASSERT OEM_CALLBACK_BASE + 0x31
+
+#define CFG_ADDR_PORT 0xCF8
+#define CFG_DATA_PORT 0xCFC
+
+#define ALINK_ACCESS_INDEX 0x0CD8
+#define ALINK_ACCESS_DATA ALINK_ACCESS_INDEX + 4
+
+/*------------------------------------------------------------------
+; I/O Base Address - Should be set by host BIOS
+;------------------------------------------------------------------ */
+#define DELAY_PORT 0x0E0
+
+#define FCH_8259_CONTROL_REG_MASTER 0x20
+#define FCH_8259_MASK_REG_MASTER 0x21
+
+/*------------------------------------------------------------------
+; DEBUG_PORT = 8-bit I/O Port Address for POST Code Display
+;------------------------------------------------------------------ */
+// ASIC VendorID and DeviceIDs
+#define ATI_VID 0x1002
+#define AMD_FCH_VID 0x1022
+#define FCH_DEVICE_ID 0x780B
+#define FCH_SATA_VID AMD_FCH_VID // Dev 17 Func 0
+#define FCH_SATA_DID 0x7800
+#define FCH_SATA_AHCI_DID 0x7801
+#define FCH_SATA_RAID_DID 0x7802
+#define FCH_SATA_RAID5_DID 0x7803
+#define FCH_SATA_AMDAHCI_DID 0x7804
+#define FCH_SATA_RAID_DOTHILL_DID 0x7805
+#define FCH_SATA_RAID5_DOTHILL_DID 0x780A
+#define FCH_USB_OHCI_VID AMD_FCH_VID // Dev 18 Func 0, Dev 19 Func 0
+#define FCH_USB_OHCI_DID 0x7807
+#define FCH_USB_EHCI_VID AMD_FCH_VID // Dev 18 Func 2, Dev 19 Func 2
+#define FCH_USB_EHCI_DID 0x7808
+#define FCH_USB_XHCI_VID AMD_FCH_VID // Dev 10 Func 0, Dev 10 Func 1
+#define FCH_USB_XHCI_DID 0x7812
+#define FCH_USB_XHCI_DID_BOLTON 0x7814
+#define FCH_SMBUS_VID AMD_FCH_VID // Dev 20 Func 0
+#define FCH_SMBUS_DID 0x780B
+#define FCH_IDE_VID AMD_FCH_VID // Dev 20 Func 1
+#define FCH_IDE_DID 0x780C
+#define FCH_AZALIA_VID AMD_FCH_VID // Dev 20 Func 2
+#define FCH_AZALIA_DID 0x780D
+#define FCH_LPC_VID AMD_FCH_VID // Dev 20 Func 3
+#define FCH_LPC_DID 0x780E
+#define FCH_PCIB_VID AMD_FCH_VID // Dev 20 Func 4
+#define FCH_PCIB_DID 0x780F
+#define FCH_USB_OHCIF_VID AMD_FCH_VID // dev 20 Func 5
+#define FCH_USB_OHCIF_DID 0x7809
+#define FCH_NIC_VID 0x14E4 // Dev 20 Func 6
+#define FCH_NIC_DID 0x1699
+#define FCH_SD_VID AMD_FCH_VID // Dev 20 Func 7
+#define FCH_SD_DID 0x7806
+
+//FCH Variant
+#define FCH_Variant_EFUSE_LOCATION 0x1E // EFUSE bit 240-247
+
+#define FCH_M2 0x01
+#define FCH_M3 0x03
+#define FCH_M3T 0x07
+#define FCH_D2 0x0F
+#define FCH_D3 0x1F
+#define FCH_D4 0x3F
+#define FCH_BOLTON 0x15
+#define FCH_YANGTZE 0x39
+#define FCH_YANGTZEA1 0x3A
+//Misc
+#define R_FCH_ACPI_PM1_STATUS 0x00
+#define R_FCH_ACPI_PM1_ENABLE 0x02
+#define R_FCH_ACPI_PM_CONTROL 0x04
+#define R_FCH_ACPI_EVENT_STATUS 0x20
+#define R_FCH_ACPI_EVENT_ENABLE 0x24
+#define R_FCH_PM_ACPI_PMA_CNT_BLK_LO 0x2C
+
+// ACPI Sleep Type
+#define ACPI_SLPTYP_S0 0
+#define ACPI_SLPTYP_S1 1
+#define ACPI_SLPTYP_S3 3
+#define ACPI_SLPTYP_S4 4
+#define ACPI_SLPTYP_S5 5
+
+//#define SATA_BUS_DEV_FUN_FPGA 0x228
+#define SATA_BUS_DEV_FUN ((0x11 << 3) + 0)
+#define FCH_SATA1_BUS 0
+#define FCH_SATA1_DEV 17
+#define FCH_SATA1_FUNC 0
+
+#define FC_BUS_DEV_FUN ((0x11 << 3) + 1)
+#define FCH_XHCI_BUS 0
+#define FCH_XHCI_DEV 16
+#define FCH_XHCI_FUNC 0
+#define USB_XHCI_BUS_DEV_FUN ((FCH_XHCI_DEV << 3) + FCH_XHCI_FUNC)
+#define FCH_XHCI1_BUS 0
+#define FCH_XHCI1_DEV 16
+#define FCH_XHCI1_FUNC 1
+#define USB_XHCI1_BUS_DEV_FUN ((FCH_XHCI1_DEV << 3) + FCH_XHCI1_FUNC)
+#define USB1_OHCI_BUS_DEV_FUN ((0x12 << 3) + 0) // PORT 0-4
+#define FCH_OHCI1_BUS 0
+#define FCH_OHCI1_DEV 18
+#define FCH_OHCI1_FUNC 0
+#define USB2_OHCI_BUS_DEV_FUN ((0x13 << 3) + 0) // PORT 5-9
+#define FCH_OHCI2_BUS 0
+#define FCH_OHCI2_DEV 19
+#define FCH_OHCI2_FUNC 0
+#define USB3_OHCI_BUS_DEV_FUN ((0x16 << 3) + 0) // PORT 10-13
+#define FCH_OHCI3_BUS 0
+#define FCH_OHCI3_DEV 22
+#define FCH_OHCI3_FUNC 0
+#define USB1_EHCI_BUS_DEV_FUN ((0x12 << 3) + 2) // PORT 0-4
+#define FCH_EHCI1_BUS 0
+#define FCH_EHCI1_DEV 18
+#define FCH_EHCI1_FUNC 2
+#define USB2_EHCI_BUS_DEV_FUN ((0x13 << 3) + 2) // PORT 5-9
+#define FCH_EHCI2_BUS 0
+#define FCH_EHCI2_DEV 19
+#define FCH_EHCI2_FUNC 2
+#define USB3_EHCI_BUS_DEV_FUN ((0x16 << 3) + 2) // PORT 10-13
+#define FCH_EHCI3_BUS 0
+#define FCH_EHCI3_DEV 22
+#define FCH_EHCI3_FUNC 2
+#define SMBUS_BUS_DEV_FUN ((0x14 << 3) + 0)
+#define FCH_ISA_BUS 0
+#define FCH_ISA_DEV 20
+#define FCH_ISA_FUNC 0
+#define IDE_BUS_DEV_FUN ((0x14 << 3) + 1)
+#define FCH_IDE_BUS 0
+#define FCH_IDE_DEV 20
+#define FCH_IDE_FUNC 1
+#define AZALIA_BUS_DEV_FUN ((0x14 << 3) + 2)
+#define FCH_AZALIA_BUS 0
+#define FCH_AZALIA_DEV 20
+#define FCH_AZALIA_FUNC 2
+#define LPC_BUS_DEV_FUN ((0x14 << 3) + 3)
+#define FCH_LPC_BUS 0
+#define FCH_LPC_DEV 20
+#define FCH_LPC_FUNC 3
+#define PCIB_BUS_DEV_FUN ((0x14 << 3) + 4) // P2P in SB700
+#define FCH_PCI_BUS 0
+#define FCH_PCI_DEV 20
+#define FCH_PCI_FUNC 4
+#define USB4_OHCI_BUS_DEV_FUN ((0x14 << 3) + 5) // PORT FL0 - FL1
+#define FCH_OHCI4_BUS 0
+#define FCH_OHCI4_DEV 20
+#define FCH_OHCI4_FUNC 5
+//Gigabyte Ethernet Controller
+#define GEC_BUS_DEV_FUN ((0x14 << 3) + 6)
+#define FCH_GBEC_BUS 0
+#define FCH_GBEC_DEV 20
+#define FCH_GBEC_FUNC 6
+
+#define SD_BUS_DEV_FUN ((0x14 << 3) + 7) // SD Controller
+#define SD_PCI_BUS 0
+#define SD_PCI_DEV 20
+#define SD_PCI_FUNC 7
+
+
+#define FCH_GPP_BUS 0
+#define FCH_GPP_DEV 21
+#define FCH_GPP_FUNC 0
+#define GPP0_BUS_DEV_FUN ((0x15 << 3) + 0) // GPP P2P bridge PORT0
+#define GPP1_BUS_DEV_FUN ((0x15 << 3) + 1) // GPP P2P bridge PORT1
+#define GPP2_BUS_DEV_FUN ((0x15 << 3) + 2) // GPP P2P bridge PORT2
+#define GPP3_BUS_DEV_FUN ((0x15 << 3) + 3) // GPP P2P bridge PORT3
+
+#define ACPI_MMIO_BASE 0xFED80000ul
+#define FCH_CFG_BASE 0x000 // DWORD
+#define GPIO_BASE 0x100 // BYTE
+#define SMI_BASE 0x200 // DWORD
+#define PMIO_BASE 0x300 // DWORD
+#define PMIO2_BASE 0x400 // BYTE
+#define BIOS_RAM_BASE 0x500 // BYTE
+#define CMOS_RAM_BASE 0x600 // BYTE
+#define CMOS_BASE 0x700 // BYTE
+#define ASF_BASE 0x900 // DWORD
+#define SMBUS_BASE 0xA00 // DWORD
+#define WATCHDOG_BASE 0xB00 //
+#define HPET_BASE 0xC00 // DWORD
+#define IOMUX_BASE 0xD00 // BYTE
+#define MISC_BASE 0xE00
+#define SERIAL_DEBUG_BASE 0x1000
+#define GFX_DAC_BASE 0x1400
+#define GPIO_BANK0_BASE 0x1500 // DWORD
+//#define GPIO_BANK1_BASE 0x1600 // DWORD
+//#define GPIO_BANK2_BASE 0x1700 // DWORD
+#define CEC_BASE 0x1800
+#define XHCI_BASE 0x1C00
+#define ACDC_BASE 0x1D00
+#define AOAC_BASE 0x1E00
+
+
+// Chip type definition
+#define CHIPTYPE_HUDSON2 (1 << 0)
+#define CHIPTYPE_YUBA (1 << 1)
+
+//
+// ROM SIG type definition
+//
+#define NUM_OF_ROMSIG_FILED 0x04
+#define XHCI_FILED_NUM 0x03
+#define ROMSIG_CFG_MASK 0x07
+#define XHCI_BOOT_RAM_OFFSET 0x8000
+#define INSTRUCTION_RAM_SIG 0x55AA
+#define ROMSIG_SIG 0x55AA55AAul
+
+// RegSpace field (AB_INDEX[31:29]
+#define AXINDC 0 // AXINDC
+#define AXINDP 2 // AXINDP
+#define ABCFG 6 // ABCFG
+#define AXCFG 4 // AXCFG
+#define RCINDXC 1 // PCIEIND
+#define RCINDXP 3 // PCIEIND_P
+
+#define GPP_DEV_NUM 21 //
+#define MAX_GPP_PORTS 4
+
+#define PCIE_FORCE_GEN1_EFUSE_LOCATION 0x14 // EFUSE bit 160
+//
+// ABCFG Registers
+//
+#define FCH_ABCFG_REG00 0x00 // VENDOR ID
+#define FCH_ABCFG_REG08 0x08 // REVISION ID
+#define FCH_ABCFG_REG40 0x40 // BL_EVENTCNT0LO
+#define FCH_ABCFG_REG44 0x44 // BL_EVENTCNT1LO
+#define FCH_ABCFG_REG48 0x48 // BL_EVENTCNTSEL
+#define FCH_ABCFG_REG4A 0x4A // BL_EVENTCNT0HI
+#define FCH_ABCFG_REG4B 0x4B // BL_EVENTCNT1HI
+#define FCH_ABCFG_REG4C 0x4C // BL_EVENTCNTCTL
+#define FCH_ABCFG_REG50 0x50 // MISCCTL_50
+#define FCH_ABCFG_REG54 0x54 // MISCCTL_54
+#define FCH_ABCFG_REG58 0x58 // BL RAB CONTROL
+
+#define FCH_ABCFG_REG60 0x60 // LINKWIDTH_CTL
+#define FCH_ABCFG_REG64 0x64 // LINKWIDTH_UP_INTERVAL
+#define FCH_ABCFG_REG68 0x68 // LINKWIDTH_DN_INVERVAL
+#define FCH_ABCFG_REG6C 0x6C // LINKWIDTH_UPSTREAM_DWORDS
+#define FCH_ABCFG_REG70 0x70 // LINKWIDTH_DOWNSTREAM_DWORDS
+#define FCH_ABCFG_REG74 0x74 // LINKWIDTH_THRESHOLD_INCREASE
+#define FCH_ABCFG_REG78 0x78 // LINKWIDTH_THRESHOLD_DECREASE
+
+#define FCH_ABCFG_REG80 0x80 // BL DMA PREFETCH CONTROL
+#define FCH_ABCFG_REG88 0x88 //
+#define FCH_ABCFG_REG8C 0x8C //
+#define FCH_ABCFG_REG90 0x90 // BIF CONTROL 0
+#define FCH_ABCFG_REG94 0x94 // MSI CONTROL
+#define FCH_ABCFG_REG98 0x98 // BIF CONTROL 1
+#define FCH_ABCFG_REG9C 0x9C // MISCCTL_9C
+#define FCH_ABCFG_REGA0 0xA0 // BIF PHY CONTROL ENABLE
+#define FCH_ABCFG_REGA4 0xA4 // BIF PHY CONTROL A4
+#define FCH_ABCFG_REGA8 0xA8 // BIF PHY CONTROL A8
+#define FCH_ABCFG_REGB0 0xB0 // HYPERFLASH-PCIE PORT MAPPING
+#define FCH_ABCFG_REGB8 0xB8 //
+#define FCH_ABCFG_REGB4 0xB4 //
+#define FCH_ABCFG_REGBC 0xBC //
+#define FCH_ABCFG_REGC0 0xC0 // PCIE_GPP_ENABLE
+#define FCH_ABCFG_REGC4 0xC4 // PCIE_P2P_INT_MAP
+#define FCH_ABCFG_REGD0 0xD0 // MCTP_VDM_TX_FIFO_DATA
+#define FCH_ABCFG_REGD4 0xD4 // MCTP_VMD_TX_CONTROL
+#define FCH_ABCFG_REGE0 0xE0 // MCTP_VDM_RX_FIFO_DATA
+#define FCH_ABCFG_REGE4 0xE4 // MCTP_VDM_RX_FIFO_STATUS
+#define FCH_ABCFG_REGEC 0xEC // MCTP_VDM_CONTROL
+#define FCH_ABCFG_REGF0 0xF0 // GPP_UPSTREAM_CONTROL
+#define FCH_ABCFG_REGF4 0xF4 // GPP_SYSTEM_ERROR_CONTROL
+#define FCH_ABCFG_REGFC 0xFC // FCH_TRAP_CONTROL
+#define FCH_ABCFG_REG100 0x100 // FCH_TRAP0_ADDRL
+#define FCH_ABCFG_REG104 0x104 // FCH_TRAP0_ADDRH
+#define FCH_ABCFG_REG108 0x108 // FCH_TRAP0_CMD
+#define FCH_ABCFG_REG10C 0x10C // FCH_TRAP1_DATA
+#define FCH_ABCFG_REG110 0x110 // FCH_TRAP1_ADDRL
+#define FCH_ABCFG_REG114 0x114 // FCH_TRAP1_ADDRH
+#define FCH_ABCFG_REG118 0x118 // FCH_TRAP1_CMD
+#define FCH_ABCFG_REG11C 0x11C // FCH_TRAP1_DATA
+#define FCH_ABCFG_REG120 0x120 // FCH_TRAP2_ADDRL
+#define FCH_ABCFG_REG124 0x124 // FCH_TRAP2_ADDRH
+#define FCH_ABCFG_REG128 0x128 // FCH_TRAP2_CMD
+#define FCH_ABCFG_REG12C 0x12C // FCH_TRAP2_DATA
+#define FCH_ABCFG_REG130 0x130 // FCH_TRAP3_ADDRL
+#define FCH_ABCFG_REG134 0x134 // FCH_TRAP3_ADDRH
+#define FCH_ABCFG_REG138 0x138 // FCH_TRAP3_CMD
+#define FCH_ABCFG_REG13C 0x13C // FCH_TRAP3_DATA
+#define FCH_ABCFG_REG208 0x208 // KR New
+#define FCH_ABCFG_REG300 0x300 // MCTP_VDM_RX_SMI_CONTROL
+#define FCH_ABCFG_REG310 0x310 // BIF_GPP_STRAP_SYSTEM_0
+#define FCH_ABCFG_REG314 0x314 // BIF_GPP_STRAP_SYSTEM_1
+#define FCH_ABCFG_REG31C 0x31C // BIF_GPP_STRAP_LINK_CONTROL_0
+#define FCH_ABCFG_REG320 0x320 // BIF_GPP_STRAP_LINK_CONTROL_LANE_A
+#define FCH_ABCFG_REG324 0x324 // BIF_GPP_STRAP_LINK_CONTROL_LANE_B
+#define FCH_ABCFG_REG328 0x328 // BIF_GPP_STRAP_LINK_CONTROL_LANE_C
+#define FCH_ABCFG_REG32C 0x32C // BIF_GPP_STRAP_LINK_CONTROL_LANE_D
+#define FCH_ABCFG_REG330 0x330 // BIF_GPP_STRAP_BIF_0
+#define FCH_ABCFG_REG334 0x334 // BIF_GPP_STRAP_BIF_1
+#define FCH_ABCFG_REG338 0x338 // BIF_GPP_STRAP_BIF_2
+#define FCH_ABCFG_REG340 0x340 // BIF_GPP_STRAP_BIF_LANE_A
+#define FCH_ABCFG_REG344 0x344 // BIF_GPP_STRAP_BIF_LANE_B
+#define FCH_ABCFG_REG348 0x348 // BIF_GPP_STRAP_BIF_LANE_C
+#define FCH_ABCFG_REG34C 0x34C // BIF_GPP_STRAP_BIF_LANE_D
+#define FCH_ABCFG_REG350 0x350 // BIF_GPP_STRAP_PHY_LOGICAL _0
+#define FCH_ABCFG_REG354 0x354 // BIF_GPP_STRAP_PHY_LOGICAL _1
+#define FCH_ABCFG_REG404 0x404 // GPP0_SHADOW_COMMAND
+#define FCH_ABCFG_REG418 0x418 // GPP0_SHADOW_BUS_NUMBER
+#define FCH_ABCFG_REG41C 0x41C // GPP0_SHADOW_IO_LIMIT_BASE
+#define FCH_ABCFG_REG420 0x420 // GPP0_SHADOW_MEM_LIMIT_BASE
+#define FCH_ABCFG_REG424 0x424 // GPP0_SHADOW_PREF_MEM_LIMIT_BASE
+#define FCH_ABCFG_REG428 0x428 // GPP0_SHADOW_PREF_MEM_BASE_UPPER
+#define FCH_ABCFG_REG42C 0x42C // GPP0_SHADOW_PREF_MEM_LIMIT_UPPER
+#define FCH_ABCFG_REG430 0x430 // GPP0_SHADOW_IO_LIMIT_BASE_UPPER
+#define FCH_ABCFG_REG43C 0x43C // GPP0_SHADOW_BRIDGE_CONTROL
+#define FCH_ABCFG_REG444 0x444 // GPP1_SHADOW_COMMAND
+#define FCH_ABCFG_REG458 0x458 // GPP1_SHADOW_BUS_NUMBER
+#define FCH_ABCFG_REG45C 0x45C // GPP1_SHADOW_IO_LIMIT_BASE
+#define FCH_ABCFG_REG460 0x460 // GPP1_SHADOW_MEM_LIMIT_BASE
+#define FCH_ABCFG_REG464 0x464 // GPP1_SHADOW_PREF_MEM_LIMIT_BASE
+#define FCH_ABCFG_REG468 0x468 // GPP1_SHADOW_PREF_MEM_BASE_UPPER
+#define FCH_ABCFG_REG46C 0x46C // GPP1_SHADOW_PREF_MEM_LIMIT_UPPER
+#define FCH_ABCFG_REG470 0x470 // GPP1_SHADOW_IO_LIMIT_BASE_UPPER
+#define FCH_ABCFG_REG47C 0x47C // GPP1_SHADOW_BRIDGE_CONTROL
+#define FCH_ABCFG_REG484 0x484 // GPP2_SHADOW_COMMAND
+#define FCH_ABCFG_REG498 0x498 // GPP2_SHADOW_BUS_NUMBER
+#define FCH_ABCFG_REG49C 0x49C // GPP2_SHADOW_IO_LIMIT_BASE
+#define FCH_ABCFG_REG4A0 0x4A0 // GPP2_SHADOW_MEM_LIMIT_BASE
+#define FCH_ABCFG_REG4A4 0x4A4 // GPP2_SHADOW_PREF_MEM_LIMIT_BASE
+#define FCH_ABCFG_REG4A8 0x4A8 // GPP2_SHADOW_PREF_MEM_BASE_UPPER
+#define FCH_ABCFG_REG4AC 0x4AC // GPP2_SHADOW_PREF_MEM_LIMIT_UPPER
+#define FCH_ABCFG_REG4B0 0x4B0 // GPP2_SHADOW_IO_LIMIT_BASE_UPPER
+#define FCH_ABCFG_REG4BC 0x4BC // GPP2_SHADOW_BRIDGE_CONTROL
+#define FCH_ABCFG_REG4C4 0x4C4 // GPP3_SHADOW_COMMAND
+#define FCH_ABCFG_REG4D8 0x4D8 // GPP3_SHADOW_BUS_NUMBER
+#define FCH_ABCFG_REG4DC 0x4DC // GPP3_SHADOW_IO_LIMIT_BASE
+#define FCH_ABCFG_REG4E0 0x4E0 // GPP3_SHADOW_MEM_LIMIT_BASE
+#define FCH_ABCFG_REG4E4 0x4E4 // GPP3_SHADOW_PREF_MEM_LIMIT_BASE
+#define FCH_ABCFG_REG4E8 0x4E8 // GPP3_SHADOW_PREF_MEM_BASE_UPPER
+#define FCH_ABCFG_REG4EC 0x4EC // GPP3_SHADOW_PREF_MEM_LIMIT_UPPER
+#define FCH_ABCFG_REG4F0 0x4F0 // GPP3_SHADOW_IO_LIMIT_BASE_UPPER
+#define FCH_ABCFG_REG4FC 0x4FC // GPP3_SHADOW_BRIDGE_CONTROL
+#define FCH_ABCFG_REG10040 0x10040ul // AL_EVENTCNT0LO
+#define FCH_ABCFG_REG10044 0x10044ul // AL_EVENTCNT1LO
+#define FCH_ABCFG_REG10048 0x10048ul // AL_EVENTCNTSEL
+#define FCH_ABCFG_REG1004A 0x1004Aul // AL_EVENTCNT0HI
+#define FCH_ABCFG_REG1004B 0x1004Bul // AL_EVENTCNT1HI
+#define FCH_ABCFG_REG1004C 0x1004Cul // AL_EVENTCNTCTL
+#define FCH_ABCFG_REG10050 0x10050ul // MISCCTL_10050
+#define FCH_ABCFG_REG10054 0x10054ul // AL_ARB_CTL
+#define FCH_ABCFG_REG10056 0x10056ul // AL_CLK_CTL
+#define FCH_ABCFG_REG10058 0x10058ul // AL RAB CONTROL
+#define FCH_ABCFG_REG1005C 0x1005Cul // AL MLT CONTROL
+#define FCH_ABCFG_REG10060 0x10060ul // AL DMA PREFETCH ENABLE
+#define FCH_ABCFG_REG10064 0x10064ul // AL DMA PREFETCH FLUSH CONTROL
+#define FCH_ABCFG_REG10068 0x10068ul // AL PREFETCH LIMIT
+#define FCH_ABCFG_REG1006C 0x1006Cul // AL DMA PREFETCH CONTROL
+#define FCH_ABCFG_REG10070 0x10070ul // MISCCTL_10070
+#define FCH_ABCFG_REG10080 0x10080ul // CLKMUXSTATUS
+#define FCH_ABCFG_REG10090 0x10090ul // BIF CONTROL 0
+#define FCH_ABCFG_REG1009C 0x1009Cul // MISCCTL_1009C
+
+//
+// RCINDX_P Registers
+//
+#define FCH_RCINDXP_REG01 0x01 | RCINDXP << 29 // PCIEP_SCRATCH
+#define FCH_RCINDXP_REG02 0x02 | RCINDXP << 29 //
+#define FCH_RCINDXP_REG10 0x10 | RCINDXP << 29 //
+#define FCH_RCINDXP_REG20 0x20 | RCINDXP << 29 // PCIE_TX_CNTL
+#define FCH_RCINDXP_REG21 0x21 | RCINDXP << 29 // PCIE_TX_REQUESTER_ID
+#define FCH_RCINDXP_REG50 0x50 | RCINDXP << 29 // PCIE_P_PORT_LANE_STATUS
+#define FCH_RCINDXP_REG6A 0x6A | RCINDXP << 29 //
+#define FCH_RCINDXP_REG70 0x70 | RCINDXP << 29 // PCIE_RX_CNTL
+#define FCH_RCINDXP_REGA0 0xA0 | RCINDXP << 29 // PCIE_LC_CNTL
+#define FCH_RCINDXP_REGA1 0xA1 | RCINDXP << 29 // PCIE_LC_TRAINING_CNTL
+#define FCH_RCINDXP_REGA2 0xA2 | RCINDXP << 29 //
+#define FCH_RCINDXP_REGA4 0xA4 | RCINDXP << 29 //
+#define FCH_RCINDXP_REGA5 0xA5 | RCINDXP << 29 // PCIE_LC_STATE0
+#define FCH_RCINDXP_REGC0 0xC0 | RCINDXP << 29 //
+
+//
+// RCINDX_C Registers
+//
+#define FCH_RCINDXC_REG02 0x02 | RCINDXC << 29 // PCIE_HW_DEBUG
+#define FCH_RCINDXC_REG10 0x10 | RCINDXC << 29 // PCIE_CNTL
+#define FCH_RCINDXC_REG40 0x40 | RCINDXC << 29 // PCIE_P_CNTL
+#define FCH_RCINDXC_REG65 0x65 | RCINDXC << 29 // PCIE_P_PAD_FORCE_DIS
+#define FCH_RCINDXC_REGC0 0xC0 | RCINDXC << 29 // PCIE_STRAP_MISC
+#define FCH_RCINDXC_REGC1 0xC1 | RCINDXC << 29 // PCIE_STRAP_MISC2
+
+
+//
+// AXINDC Registers
+//
+#define FCH_AX_INDXC_REG02 0x02 // PCIEP_HW_DEBUG
+#define FCH_AX_INDXC_REG10 0x10
+#define FCH_AX_INDXC_REG30 0x30
+#define FCH_AX_DATAC_REG34 0x34
+#define FCH_AX_INDXP_REG38 0x38
+#define FCH_AX_DATAP_REG3C 0x3C
+#define FCH_AX_INDXC_REG40 0x40 | AXINDC << 29
+#define FCH_AX_INDXC_REGA4 0xA4 | AXINDC << 29
+
+#define FCH_AX_INDXP_REG02 0x02 | AXINDP << 29
+#define FCH_AX_INDXP_REGA0 0xA0 | AXINDP << 29
+#define FCH_AX_INDXP_REGA4 0xA4 | AXINDP << 29
+#define FCH_AX_INDXP_REGB1 0xB1 | AXINDP << 29
+
+#define FCH_AX_CFG_REG68 0x68 | AXCFG << 29
+#define FCH_AX_CFG_REG88 0x88 | AXCFG << 29
+
+#define FCH_AB_REG04 0x04
+#define FCH_AB_REG40 0x40
+
+//Sata Port Configuration
+#define SIX_PORTS 0
+#define FOUR_PORTS 1
+
+#define SATA_EFUSE_LOCATION 0x10 // EFUSE bit 133
+#define SATA_DH_EFUSE_LOCATION 0x11 // EFUSE bit 138
+#define SATA_FIS_BASE_EFUSE_LOC 0x15 // EFUSE bit 169
+#define SATA_EFUSE_BIT 0x20 //
+#define SATA_DH_EFUSE_BIT 0x04 //
+#define FCH_SATA_REG00 0x000 // Vendor ID - R- 16 bits
+#define FCH_SATA_REG02 0x002 // Device ID - RW -16 bits
+#define FCH_SATA_REG04 0x004 // PCI Command - RW - 16 bits
+#define FCH_SATA_REG06 0x006 // PCI Status - RW - 16 bits
+#define FCH_SATA_REG08 0x008 // Revision ID/PCI Class Code - R - 32 bits - Offset: 08
+#define FCH_SATA_REG0C 0x00C // Cache Line Size - R/W - 8bits
+#define FCH_SATA_REG0D 0x00D // Latency Timer - RW - 8 bits
+#define FCH_SATA_REG0E 0x00E // Header Type - R - 8 bits
+#define FCH_SATA_REG0F 0x00F // BIST - R - 8 bits
+#define FCH_SATA_REG10 0x010 // Base Address Register 0 - RW - 32 bits
+#define FCH_SATA_REG14 0x014 // Base Address Register 1 - RW- 32 bits
+#define FCH_SATA_REG18 0x018 // Base Address Register 2 - RW - 32 bits
+#define FCH_SATA_REG1C 0x01C // Base Address Register 3 - RW - 32 bits
+#define FCH_SATA_REG20 0x020 // Base Address Register 4 - RW - 32 bits
+#define FCH_SATA_REG24 0x024 // Base Address Register 5 - RW - 32 bits
+#define FCH_SATA_REG2C 0x02C // Subsystem Vendor ID - R - 16 bits
+#define FCH_SATA_REG2D 0x02D // Subsystem ID - R - 16 bits
+#define FCH_SATA_REG30 0x030 // Expansion ROM Base Address - 32 bits
+#define FCH_SATA_REG34 0x034 // Capabilities Pointer - R - 32 bits
+#define FCH_SATA_REG3C 0x03C // Interrupt Line - RW - 8 bits
+#define FCH_SATA_REG3D 0x03D // Interrupt Pin - R - 8 bits
+#define FCH_SATA_REG3E 0x03E // Min Grant - R - 8 bits
+#define FCH_SATA_REG3F 0x03F // Max Latency - R - 8 bits
+#define FCH_SATA_REG40 0x040 // Configuration - RW - 32 bits
+#define FCH_SATA_REG44 0x044 // Software Data Register - RW - 32 bits
+#define FCH_SATA_REG48 0x048
+#define FCH_SATA_REG4C 0x04C
+#define FCH_SATA_REG50 0x050 // Message Capability - R - 16 bits
+#define FCH_SATA_REG52 0x052 // Message Control - R/W - 16 bits
+#define FCH_SATA_REG54 0x054 // Message Address - R/W - 32 bits
+#define FCH_SATA_REG58 0x058 // Message Data - R/W - 16 bits
+#define FCH_SATA_REG5C 0x05C // RAMBIST Control Register - R/W - 8 bits
+#define FCH_SATA_REG5D 0x05D // RAMBIST Status0 Register - R - 8 bits
+#define FCH_SATA_REG5E 0x05E // RAMBIST Status1 Register - R - 8 bits
+#define FCH_SATA_REG60 0x060 // Power Management Capabilities - R - 32 bits
+#define FCH_SATA_REG64 0x064 // Power Management Control + Status - RW - 32 bits
+#define FCH_SATA_REG68 0x068 // MSI Program - R/W - 8 bits
+#define FCH_SATA_REG69 0x069 // PCI Burst Timer - R/W - 8 bits
+#define FCH_SATA_REG70 0x070 // PCI Bus Master - IDE0 - RW - 32 bits
+#define FCH_SATA_REG74 0x074 // PRD Table Address - IDE0 - RW - 32 bits
+#define FCH_SATA_REG78 0x078 // PCI Bus Master - IDE1 - RW - 32 bits
+#define FCH_SATA_REG7C 0x07C // PRD Table Address - IDE1 - RW - 32 bits
+#define FCH_SATA_REG80 0x080 // Data Transfer Mode - IDE0 - RW - 32 bits
+#define FCH_SATA_REG84 0x084 // Data Transfer Mode - IDE1 - RW - 32 bits
+#define FCH_SATA_REG86 0x086 // PY Global Control
+#define FCH_SATA_REG87 0x087
+#define FCH_SATA_REG88 0x088 // PHY Port0 Control - Port0 PY fine tune (0:23)
+#define FCH_SATA_REG8A 0x08A
+#define FCH_SATA_REG8C 0x08C // PHY Port1 Control - Port0 PY fine tune (0:23)
+#define FCH_SATA_REG8E 0x08E
+#define FCH_SATA_REG90 0x090 // PHY Port2 Control - Port0 PY fine tune (0:23)
+#define FCH_SATA_REG92 0x092
+#define FCH_SATA_REG94 0x094 // PHY Port3 Control - Port0 PY fine tune (0:23)
+#define FCH_SATA_REG96 0x096
+#define FCH_SATA_REG98 0x098 // EEPROM Memory Address - Command + Status - RW - 32 bits
+#define FCH_SATA_REG9C 0x09C // EEPROM Memory Data - RW - 32 bits
+#define FCH_SATA_REGA0 0x0A0 //
+#define FCH_SATA_REGA4 0x0A4 //
+#define FCH_SATA_REGA5 0x0A5 //;
+#define FCH_SATA_REGA8 0x0A8 //
+#define FCH_SATA_REGAD 0x0AD //;
+#define FCH_SATA_REGB0 0x0B0 // IDE1 Task File Configuration + Status - RW - 32 bits
+#define FCH_SATA_REGB5 0x0B5 //;
+#define FCH_SATA_REGBD 0x0BD //;
+#define FCH_SATA_REGC0 0x0C0 // BA5 Indirect Address - RW - 32 bits
+#define FCH_SATA_REGC4 0x0C4 // BA5 Indirect Access - RW - 32 bits
+
+#define FCH_SATA_BAR5_REG00 0x000 // PCI Bus Master - IDE0 - RW - 32 bits
+#define FCH_SATA_BAR5_REG04 0x004 // PRD Table Address - IDE0 - RW - 32 bits
+#define FCH_SATA_BAR5_REG08 0x008 // PCI Bus Master - IDE1 - RW - 32 bits
+#define FCH_SATA_BAR5_REG0C 0x00C // PRD Table Address - IDE1 - RW - 32 bits
+#define FCH_SATA_BAR5_REG10 0x010 // PCI Bus Master2 - IDE0 - RW - 32 bits
+#define FCH_SATA_BAR5_REG1C 0x01C
+#define FCH_SATA_BAR5_REG18 0x018 // PCI Bus Master2 - IDE1 - RW - 32 bits
+#define FCH_SATA_BAR5_REG20 0x020 // PRD Address - IDE0 - RW - 32 bits
+#define FCH_SATA_BAR5_REG24 0x024 // PCI Bus Master Byte Count - IDE0- RW - 32 bits
+#define FCH_SATA_BAR5_REG28 0x028 // PRD Address - IDE1 - RW - 32 bits
+#define FCH_SATA_BAR5_REG2C 0x02C // PCI Bus Master Byte Count - IDE1 - RW - 32 bits
+#define FCH_SATA_BAR5_REG40 0x040 // FIFO Valid Byte Count and Control - IDE0 - RW - 32 bits
+#define FCH_SATA_BAR5_REG44 0x044 // FIFO Valid Byte Count and Control - IDE1 - RW - 32 bits
+#define FCH_SATA_BAR5_REG48 0x048 // System Configuration Status - Command - RW - 32 bits
+#define FCH_SATA_BAR5_REG4C 0x04C // System Software Data Register - RW - 32 bits
+#define FCH_SATA_BAR5_REG50 0x050 // FLAS Memory Address - Command + Status - RW - 32 bits
+#define FCH_SATA_BAR5_REG54 0x054 // FLAS Memory Data - RW - 32 bits
+#define FCH_SATA_BAR5_REG58 0x058 // EEPROM Memory Address - Command + Status - RW - 32 bits
+#define FCH_SATA_BAR5_REG5C 0x05C // EEPROM Memory Data - RW - 32 bits
+#define FCH_SATA_BAR5_REG60 0x060 // FIFO Port - IDE0 - RW - 32 bits
+#define FCH_SATA_BAR5_REG68 0x068 // FIFO Pointers1- IDE0 - RW - 32 bits
+#define FCH_SATA_BAR5_REG6C 0x06C // FIFO Pointers2- IDE0 - RW - 32 bits
+#define FCH_SATA_BAR5_REG70 0x070 // FIFO Port - IDE1- RW - 32 bits
+#define FCH_SATA_BAR5_REG78 0x078 // FIFO Pointers1- IDE1- RW - 32 bits
+#define FCH_SATA_BAR5_REG7C 0x07C // FIFO Pointers2- IDE1- RW - 32 bits
+#define FCH_SATA_BAR5_REG80 0x080 // IDE0 Task File Register 0- RW - 32 bits
+#define FCH_SATA_BAR5_REG84 0x084 // IDE0 Task File Register 1- RW - 32 bits
+#define FCH_SATA_BAR5_REG88 0x088 // IDE0 Task File Register 2- RW - 32 bits
+#define FCH_SATA_BAR5_REG8C 0x08C // IDE0 Read Data - RW - 32 bits
+#define FCH_SATA_BAR5_REG90 0x090 // IDE0 Task File Register 0 - Command Buffering - RW - 32 bits
+#define FCH_SATA_BAR5_REG94 0x094 // IDE0 Task File Register 1 - Command Buffering - RW - 32 bits
+#define FCH_SATA_BAR5_REG9C 0x09C // IDE0 Virtual DMA/PIO Read Byte Count - RW - 32 bits
+#define FCH_SATA_BAR5_REGA0 0x0A0 // IDE0 Task File Configuration + Status - RW - 32 bits
+#define FCH_SATA_BAR5_REGB4 0x0B4 // Data Transfer Mode -IDE0 - RW - 32 bits
+#define FCH_SATA_BAR5_REGC0 0x0C0 // IDE1 Task File Register 0 - RW - 32 bits
+#define FCH_SATA_BAR5_REGC4 0x0C4 // IDE1 Task File Register 1 - RW - 32 bits
+#define FCH_SATA_BAR5_REGC8 0x0C8 // IDE1 Task File Register 2 - RW - 32 bits
+#define FCH_SATA_BAR5_REGCC 0x0CC // Read/Write Data - RW - 32 bits
+#define FCH_SATA_BAR5_REGD0 0x0D0 // IDE1 Task File Register 0 - Command Buffering - RW - 32 bits
+#define FCH_SATA_BAR5_REGD4 0x0D4 // IDE1 Task File Register 1 - Command Buffering - RW - 32 bits
+#define FCH_SATA_BAR5_REGDC 0x0DC // IDE1 Virtual DMA/PIO Read Byte Count - RW - 32 bits
+#define FCH_SATA_BAR5_REGE0 0x0E0 // IDE1 Task File Configuration + Status - RW - 32 bits
+#define FCH_SATA_BAR5_REGF4 0x0F4 // Data Transfer Mode - IDE1 - RW - 32 bits
+#define FCH_SATA_BAR5_REGF8 0x0F8 // PORT Configuration
+#define FCH_SATA_BAR5_REGFC 0x0FC
+#define FCH_SATA_BAR5_REG100 0x0100 // Serial ATA SControl - RW - 32 bits - [Offset: 100h (channel 1) / 180
+#define FCH_SATA_BAR5_REG104 0x0104 // Serial ATA Sstatus - RW - 32 bits - [Offset: 104h (channel 1) / 184h (cannel
+#define FCH_SATA_BAR5_REG108 0x0108 // Serial ATA Serror - RW - 32 bits - [Offset: 108h (channel 1) / 188h (cannel
+#define FCH_SATA_BAR5_REG10C 0x010C // Serial ATA Sdevice - RW - 32 bits - [Offset: 10Ch (channel 1) / 18Ch (cannel
+#define FCH_SATA_BAR5_REG144 0x0144 // Serial ATA PY Configuration - RW - 32 bits
+#define FCH_SATA_BAR5_REG148 0x0148 // SIEN - RW - 32 bits - [Offset: 148 (channel 1) / 1C8 (cannel 2)]
+#define FCH_SATA_BAR5_REG14C 0x014C // SFISCfg - RW - 32 bits - [Offset: 14C (channel 1) / 1CC (cannel 2)]
+#define FCH_SATA_BAR5_REG120 0x0120 //
+#define FCH_SATA_BAR5_REG128 0x0128 // Port Serial ATA Status
+#define FCH_SATA_BAR5_REG12C 0x012C // Port Serial ATA Control
+#define FCH_SATA_BAR5_REG130 0x0130
+#define FCH_SATA_BAR5_REG1B0 0x01B0
+#define FCH_SATA_BAR5_REG230 0x0230
+#define FCH_SATA_BAR5_REG2B0 0x02B0
+#define FCH_SATA_BAR5_REG330 0x0330
+#define FCH_SATA_BAR5_REG3B0 0x03B0
+#define FCH_SATA_BAR5_REG430 0x0430
+#define FCH_SATA_BAR5_REG4B0 0x04B0
+
+
+// USB ports
+#define NUM_USB1_PORTS 5
+#define NUM_USB2_PORTS 5
+#define NUM_USB3_PORTS 4
+#define NUM_USB4_PORTS 2
+#define NUM_XHC0_PORTS 2
+#define NUM_XHC1_PORTS 2
+
+
+//
+// USB OHCI Device 0x7807
+// Device 18 (0x11)/Device 19 (0x12)/Device 22 (0x16) Func 0
+// Device 20 (0x14) Func 5 (FL) 0x7809
+//
+#define FCH_OHCI_REG00 0x00 // Device/Vendor ID - R (0x43971002ul)
+#define FCH_OHCI_REG04 0x04 // Command - RW
+#define FCH_OHCI_REG06 0x06 // Status - R
+#define FCH_OHCI_REG08 0x08 // Revision ID/Class Code - R
+#define FCH_OHCI_REG0C 0x0C // Miscellaneous - RW
+#define FCH_OHCI_REG10 0x10 // Bar_OCI - RW
+#define FCH_OHCI_REG2C 0x2C // Subsystem Vendor ID/ Subsystem ID - RW
+#define FCH_OHCI_REG34 0x34 // Capability Pointer - R
+#define FCH_OHCI_REG3C 0x3C // Interrupt Line - RW
+#define FCH_OHCI_REG3D 0x3D // Interrupt Line - RW
+#define FCH_OHCI_REG40 0x40 // Config Timers - RW
+#define FCH_OHCI_REG42 0x42 // Port Disable Control - RW (800)
+#define FCH_OHCI_REG46 0x46 // USB PHY Battery Charger - RW (800)
+#define FCH_OHCI_REG48 0x48 // Port Force Reset - RW (800)
+#define FCH_OHCI_REG4C 0x4C // MSI - RW (800)
+#define FCH_OHCI_REG50 0x50 // Misc Control - RW
+#define FCH_OHCI_REG51 0x51
+#define FCH_OHCI_REG52 0x52
+#define FCH_OHCI_REG58 0x58 // Over Current Control - RW
+#define FCH_OHCI_REG5C 0x5C // Over Current Control - RW
+#define FCH_OHCI_REG60 0x60 // Serial Bus Release Number - RW
+#define FCH_OHCI_REG68 0x68 // Over Current PME Enable - RW
+#define FCH_OHCI_REG74 0x74 // Target Timeout Control - RW
+#define FCH_OHCI_REG80 0x80 //
+#define FCH_OHCI_REGD0 0x0D0 // MSI Control - RW
+#define FCH_OHCI_REGD4 0x0D4 // MSI Address - RW
+#define FCH_OHCI_REGD8 0x0D8 // MSI Data - RW
+#define FCH_OHCI_REGE4 0x0E4 // HT MSI Support
+#define FCH_OHCI_REGF0 0x0F0 // Function Level Reset Capability
+#define FCH_OHCI_REGF4 0x0F4 // Function Level Reset Control
+
+#define FCH_OHCI_BAR_REG00 0x00 // cRevision - R
+#define FCH_OHCI_BAR_REG04 0x04 // cControl
+#define FCH_OHCI_BAR_REG08 0x08 // cCommandStatus
+#define FCH_OHCI_BAR_REG0C 0x0C // cInterruptStatus RW
+#define FCH_OHCI_BAR_REG10 0x10 // cInterruptEnable
+#define FCH_OHCI_BAR_REG14 0x14 // cInterruptDisable
+#define FCH_OHCI_BAR_REG18 0x18 // HcCCA
+#define FCH_OHCI_BAR_REG1C 0x1C // cPeriodCurrentED
+#define FCH_OHCI_BAR_REG20 0x20 // HcControleadED
+#define FCH_OHCI_BAR_REG24 0x24 // cControlCurrentED RW
+#define FCH_OHCI_BAR_REG28 0x28 // HcBulkeadED
+#define FCH_OHCI_BAR_REG2C 0x2C // cBulkCurrentED- RW
+#define FCH_OHCI_BAR_REG30 0x30 // HcDoneead
+#define FCH_OHCI_BAR_REG34 0x34 // cFmInterval
+#define FCH_OHCI_BAR_REG38 0x38 // cFmRemaining
+#define FCH_OHCI_BAR_REG3C 0x3C // cFmNumber
+#define FCH_OHCI_BAR_REG40 0x40 // cPeriodicStart
+#define FCH_OHCI_BAR_REG44 0x44 // HcLSThresold
+#define FCH_OHCI_BAR_REG48 0x48 // HcRDescriptorA
+#define FCH_OHCI_BAR_REG4C 0x4C // HcRDescriptorB
+#define FCH_OHCI_BAR_REG50 0x50 // HcRStatus
+#define FCH_OHCI_BAR_REG54 0x54 // HcRhPortStatus (800)
+#define FCH_OHCI_BAR_REG58 0x58 // HcRhPortStatus NPD (800)
+#define FCH_OHCI_BAR_REGF0 0xF0 // OHCI Loop Back feature Support (800)
+
+#define FCH_OHCI_PORTSC_CCS 0x1 // HcRhPortStatus
+#define FCH_OHCI_PORTSC_PES 0x2 // HcRhPortStatus
+#define FCH_OHCI_PORTSC_PSS 0x4 // HcRhPortStatus
+#define FCH_OHCI_PORTSC_PPS 0x100 // HcRhPortStatus
+#define FCH_OHCI_PORTSC_LSDA 0x200 // HcRhPortStatus
+#define FCH_OHCI_PORTSC_PRS 0x10 // HcRhPortStatus
+
+//
+// USB EHCI Device 0x7808
+// Device 18 (0x11)/Device 19 (0x12)/Device 22 (0x16) Func 2
+//
+#define FCH_EHCI_REG00 0x00 // DEVICE/VENDOR ID - R
+#define FCH_EHCI_REG04 0x04 // Command - RW
+#define FCH_EHCI_REG06 0x06 // Status - R
+#define FCH_EHCI_REG08 0x08 // Revision ID/Class Code - R
+#define FCH_EHCI_REG0C 0x0C // Miscellaneous - RW
+#define FCH_EHCI_REG10 0x10 // BAR - RW
+#define FCH_EHCI_REG2C 0x2C // Subsystem ID/Subsystem Vendor ID - RW
+#define FCH_EHCI_REG34 0x34 // Capability Pointer - R
+#define FCH_EHCI_REG3C 0x3C // Interrupt Line - RW
+#define FCH_EHCI_REG3D 0x3D // Interrupt Line - RW
+#define FCH_EHCI_REG40 0x40 // Config Timers - RW
+#define FCH_EHCI_REG4C 0x4C // MSI - RW
+#define FCH_EHCI_REG50 0x50 // EHCI Misc Control - RW
+#define FCH_EHCI_REG54 0x54 // EHCI Misc Control - RW
+#define FCH_EHCI_REG60 0x60 // SBRN - R
+#define FCH_EHCI_REG61 0x61 // FLADJ - RW
+#define FCH_EHCI_REG62 0x62 // PORTWAKECAP - RW
+#define FCH_EHCI_REG74 0x74 // EHCI Misc Control2 - RW
+#define FCH_EHCI_REG84 0x84 // HUB Configure 1 - RW
+#define FCH_EHCI_REG88 0x88 // - RW
+#define FCH_EHCI_REG90 0x90 // HUB Configure 4 - RW
+#define FCH_EHCI_REGC0 0x0C0 // PME control - RW (800)
+#define FCH_EHCI_REGC4 0x0C4 // PME Data /Status - RW (800)
+#define FCH_EHCI_REGD0 0x0D0 // MSI Control - RW
+#define FCH_EHCI_REGD4 0x0D4 // MSI Address - RW
+#define FCH_EHCI_REGD8 0x0D8 // MSI Data - RW
+#define FCH_EHCI_REGE4 0x0E4 // EHCI Debug Port Support - RW (800)
+#define FCH_EHCI_REGF0 0x0F0 // Function Level Reset Capability - R (800)
+#define FCH_EHCI_REGF4 0x0F4 // Function Level Reset Capability - R (800)
+
+#define FCH_EHCI_BAR_REG00 0x00 // CAPLENGT - R
+#define FCH_EHCI_BAR_REG02 0x002 // CIVERSION- R
+#define FCH_EHCI_BAR_REG04 0x004 // CSPARAMS - R
+#define FCH_EHCI_BAR_REG08 0x008 // CCPARAMS - R
+#define FCH_EHCI_BAR_REG0C 0x00C // CSP-PORTROUTE - R
+
+#define FCH_EHCI_BAR_REG20 0x020 // USBCMD - RW - 32 bits
+#define FCH_EHCI_BAR_REG24 0x024 // USBSTS - RW - 32 bits
+#define FCH_EHCI_BAR_REG28 0x028 // USBINTR -RW - 32 bits
+#define FCH_EHCI_BAR_REG2C 0x02C // FRINDEX -RW - 32 bits
+#define FCH_EHCI_BAR_REG30 0x030 // CTRLDSSEGMENT -RW - 32 bits
+#define FCH_EHCI_BAR_REG34 0x034 // PERIODICLISTBASE -RW - 32 bits
+#define FCH_EHCI_BAR_REG38 0x038 // ASYNCLISTADDR -RW - 32 bits
+#define FCH_EHCI_BAR_REG60 0x060 // CONFIGFLAG -RW - 32 bits
+#define FCH_EHCI_BAR_REG64 0x064 // PORTSC (1-N_PORTS) -RW - 32 bits
+#define FCH_EHCI_BAR_REGA0 0x0A0 // DebugPort MISC Control - RW - 32 bits (800)
+#define FCH_EHCI_BAR_REGA4 0x0A4 // Packet Buffer Threshold Values - RW - 32 bits
+#define FCH_EHCI_BAR_REGA8 0x0A8 // USB PHY Status 0 - R
+#define FCH_EHCI_BAR_REGAC 0x0AC // USB PHY Status 1 - R
+#define FCH_EHCI_BAR_REGB0 0x0B0 // USB PHY Status 2 - R
+#define FCH_EHCI_BAR_REGB4 0x0B4 // UTMI Control - RW (800)
+#define FCH_EHCI_BAR_REGB8 0x0B8 // Loopback Test
+#define FCH_EHCI_BAR_REGBC 0x0BC // EHCI MISC Control
+#define FCH_EHCI_BAR_REGC0 0x0C0 // USB PHY Calibration
+#define FCH_EHCI_BAR_REGC4 0x0C4 // USB Common PHY Control
+#define FCH_EHCI_BAR_REGC8 0x0C8 // EHCI Debug Purpose
+#define FCH_EHCI_BAR_REGCC 0x0CC // Ehci Spare 1 (800) **
+#define FCH_EHCI_BAR_REGD0 0x0D0
+#define FCH_EHCI_BAR_REGD4 0x0D4
+#define FCH_EHCI_BAR_REG100 0x100 // USB debug port
+
+//
+// USB XHCI Device 0x7812/0x7814
+// Device 16 (0x10) Func 0/1
+//
+#define FCH_XHCI_REG00 0x00 // DEVICE/VENDOR ID - R
+#define FCH_XHCI_REG04 0x04 // Command - RW
+#define FCH_XHCI_REG10 0x10 // Bar0
+#define FCH_XHCI_REG2C 0x2C // Sub System ID
+#define FCH_XHCI_REG40 0x40 // Index0
+#define FCH_XHCI_REG44 0x44 // Data0
+#define FCH_XHCI_REG48 0x48 // Index1
+#define FCH_XHCI_REG4C 0x4C // Data0
+#define FCH_XHCI_REG54 0x54 // PME Control/Status
+#define XHCI_EFUSE_LOCATION 0x18 // EFUSE bit 192, 193
+
+#define FCH_XHCI_BAR_REG420 0x420 // Port Status and Control
+#define FCH_XHCI_PORTSC_CCS 0x1 // Port Status and Control
+#define FCH_XHCI_PORTSC_PED 0x2 // Port Status and Control
+#define FCH_XHCI_PORTSC_PLS 0x1E0 // Port Status and Control
+#define FCH_XHCI_PORTSC_SPEED 0x3C00 // Port Status and Control
+#define FCH_XHCI_PORTSC_PR 0x10 // Port Status and Control
+
+//
+// FCH CFG device 0x780B
+// Device 20 (0x14) Func 0
+//
+#define FCH_CFG_REG00 0x000 // VendorID - R
+#define FCH_CFG_REG02 0x002 // DeviceID - R
+#define FCH_CFG_REG04 0x004 // Command- RW
+#define FCH_CFG_REG05 0x005 // Command- RW
+#define FCH_CFG_REG06 0x006 // STATUS- RW
+#define FCH_CFG_REG08 0x008 // Revision ID/Class Code- R
+#define FCH_CFG_REG0A 0x00A //
+#define FCH_CFG_REG0B 0x00B //
+#define FCH_CFG_REG0C 0x00C // Cache Line Size- R
+#define FCH_CFG_REG0D 0x00D // Latency Timer- R
+#define FCH_CFG_REG0E 0x00E // Header Type- R
+#define FCH_CFG_REG0F 0x00F // BIST- R
+#define FCH_CFG_REG10 0x010 // Base Address 0- R
+#define FCH_CFG_REG11 0x011 //;
+#define FCH_CFG_REG12 0x012 //;
+#define FCH_CFG_REG13 0x013 //;
+#define FCH_CFG_REG14 0x014 // Base Address 1- R
+#define FCH_CFG_REG18 0x018 // Base Address 2- R
+#define FCH_CFG_REG1C 0x01C // Base Address 3- R
+#define FCH_CFG_REG20 0x020 // Base Address 4- R
+#define FCH_CFG_REG24 0x024 // Base Address 5- R
+#define FCH_CFG_REG28 0x028 // Cardbus CIS Pointer- R
+#define FCH_CFG_REG2C 0x02C // Subsystem Vendor ID- W
+#define FCH_CFG_REG2E 0x02E // Subsystem ID- W
+#define FCH_CFG_REG30 0x030 // Expansion ROM Base Address - R
+#define FCH_CFG_REG34 0x034 // Capability Pointer - R (800) default changed as 0x00
+#define FCH_CFG_REG3C 0x03C // Interrupt Line - R
+#define FCH_CFG_REG3D 0x03D // Interrupt Pin - R
+#define FCH_CFG_REG3E 0x03E // Min_Gnt - R
+#define FCH_CFG_REG3F 0x03F // Max_Lat - R
+#define FCH_CFG_REG90 0x090 // Smbus Base Address - R
+#define FCH_CFG_REG9C 0x09C // SBResourceMMIO_BASE
+
+//
+// FCH SATA IDE device
+// Device 20 (0x14) Func 1
+//
+
+#define FCH_IDE_REG00 0x00 // Vendor ID
+#define FCH_IDE_REG02 0x02 // Device ID
+#define FCH_IDE_REG04 0x04 // Command
+#define FCH_IDE_REG06 0x06 // Status
+#define FCH_IDE_REG08 0x08 // Revision ID/Class Code
+#define FCH_IDE_REG09 0x09 // Class Code
+#define FCH_IDE_REG2C 0x2C // Subsystem ID and Subsystem Vendor ID
+#define FCH_IDE_REG40 0x40 // Configuration - RW - 32 bits
+#define FCH_IDE_REG34 0x34
+#define FCH_IDE_REG62 0x62 // IDE Internal Control
+#define FCH_IDE_REG63 0x63 // IDE Internal Control
+//
+// FCH AZALIA device 0x780D
+// Device 20 (0x14) Func 2
+//
+#define ATI_AZALIA_ExtBlk_Addr 0x0F8
+#define ATI_AZALIA_ExtBlk_DATA 0x0FC
+
+#define FCH_AZ_REG00 0x00 // Vendor ID - R
+#define FCH_AZ_REG02 0x02 // Device ID - R/W
+#define FCH_AZ_REG04 0x04 // PCI Command
+#define FCH_AZ_REG06 0x06 // PCI Status - R/W
+#define FCH_AZ_REG08 0x08 // Revision ID
+#define FCH_AZ_REG09 0x09 // Programming Interface
+#define FCH_AZ_REG0A 0x0A // Sub Class Code
+#define FCH_AZ_REG0B 0x0B // Base Class Code
+#define FCH_AZ_REG0C 0x0C // Cache Line Size - R/W
+#define FCH_AZ_REG0D 0x0D // Latency Timer
+#define FCH_AZ_REG0E 0x0E // Header Type
+#define FCH_AZ_REG0F 0x0F // BIST
+#define FCH_AZ_REG10 0x10 // Lower Base Address Register
+#define FCH_AZ_REG14 0x14 // Upper Base Address Register
+#define FCH_AZ_REG2C 0x2C // Subsystem Vendor ID
+#define FCH_AZ_REG2D 0x2D // Subsystem ID
+#define FCH_AZ_REG34 0x34 // Capabilities Pointer
+#define FCH_AZ_REG3C 0x3C // Interrupt Line
+#define FCH_AZ_REG3D 0x3D // Interrupt Pin
+#define FCH_AZ_REG3E 0x3E // Minimum Grant
+#define FCH_AZ_REG3F 0x3F // Maximum Latency
+#define FCH_AZ_REG40 0x40 // Misc Control 1
+#define FCH_AZ_REG42 0x42 // Misc Control 2 Register
+#define FCH_AZ_REG43 0x43 // Misc Control 3 Register
+#define FCH_AZ_REG44 0x44 // Interrupt Pin Control Register
+#define FCH_AZ_REG46 0x46 // Debug Control Register
+#define FCH_AZ_REG4C 0x4C
+#define FCH_AZ_REG50 0x50 // Power Management Capability ID
+#define FCH_AZ_REG52 0x52 // Power Management Capabilities
+#define FCH_AZ_REG54 0x54 // Power Management Control/Status
+#define FCH_AZ_REG60 0x60 // MSI Capability ID
+#define FCH_AZ_REG62 0x62 // MSI Message Control
+#define FCH_AZ_REG64 0x64 // MSI Message Lower Address
+#define FCH_AZ_REG68 0x68 // MSI Message Upper Address
+#define FCH_AZ_REG6C 0x6C // MSI Message Data
+
+#define FCH_AZ_BAR_REG00 0x00 // Global Capabilities - R
+#define FCH_AZ_BAR_REG02 0x02 // Minor Version - R
+#define FCH_AZ_BAR_REG03 0x03 // Major Version - R
+#define FCH_AZ_BAR_REG04 0x04 // Output Payload Capability - R
+#define FCH_AZ_BAR_REG06 0x06 // Input Payload Capability - R
+#define FCH_AZ_BAR_REG08 0x08 // Global Control - R/W
+#define FCH_AZ_BAR_REG0C 0x0C // Wake Enable - R/W
+#define FCH_AZ_BAR_REG0E 0x0E // State Change Status - R/W
+#define FCH_AZ_BAR_REG10 0x10 // Global Status - R/W
+#define FCH_AZ_BAR_REG18 0x18 // Output Stream Payload Capability - R
+#define FCH_AZ_BAR_REG1A 0x1A // Input Stream Payload Capability - R
+#define FCH_AZ_BAR_REG20 0x20 // Interrupt Control - R/W
+#define FCH_AZ_BAR_REG24 0x24 // Interrupt Status - R/W
+#define FCH_AZ_BAR_REG30 0x30 // Wall Clock Counter - R
+#define FCH_AZ_BAR_REG38 0x38 // Stream Synchronization - R/W
+#define FCH_AZ_BAR_REG40 0x40 // CORB Lower Base Address - R/W
+#define FCH_AZ_BAR_REG44 0x44 // CORB Upper Base Address - RW
+#define FCH_AZ_BAR_REG48 0x48 // CORB Write Pointer - R/W
+#define FCH_AZ_BAR_REG4A 0x4A // CORB Read Pointer - R/W
+#define FCH_AZ_BAR_REG4C 0x4C // CORB Control - R/W
+#define FCH_AZ_BAR_REG4D 0x4D // CORB Status - R/W
+#define FCH_AZ_BAR_REG4E 0x4E // CORB Size - R/W
+#define FCH_AZ_BAR_REG50 0x50 // RIRB Lower Base Address - RW
+#define FCH_AZ_BAR_REG54 0x54 // RIRB Upper Address - RW
+#define FCH_AZ_BAR_REG58 0x58 // RIRB Write Pointer - RW
+#define FCH_AZ_BAR_REG5A 0x5A // RIRB Response Interrupt Count - R/W
+#define FCH_AZ_BAR_REG5C 0x5C // RIRB Control - R/W
+#define FCH_AZ_BAR_REG5D 0x5D // RIRB Status - R/W
+#define FCH_AZ_BAR_REG5E 0x5E // RIRB Size - R/W
+#define FCH_AZ_BAR_REG60 0x60 // Immediate Command Output Interface - R/W
+#define FCH_AZ_BAR_REG64 0x64 // Immediate Command Input Interface - R/W
+#define FCH_AZ_BAR_REG68 0x68 // Immediate Command Input Interface - R/W
+#define FCH_AZ_BAR_REG70 0x70 // DMA Position Lower Base Address - R/W
+#define FCH_AZ_BAR_REG74 0x74 // DMA Position Upper Base Address - R/W
+#define FCH_AZ_BAR_REG2030 0x2030 // Wall Clock Counter Alias - R
+
+//
+// FCH LPC Device 0x780E
+// Device 20 (0x14) Func 3
+//
+#define FCH_LPC_REG00 0x00 // VID- R
+#define FCH_LPC_REG02 0x02 // DID- R
+#define FCH_LPC_REG04 0x04 // CMD- RW
+#define FCH_LPC_REG06 0x06 // STATUS- RW
+#define FCH_LPC_REG08 0x08 // Revision ID/Class Code - R
+#define FCH_LPC_REG0C 0x0C // Cache Line Size - R
+#define FCH_LPC_REG0D 0x0D // Latency Timer - R
+#define FCH_LPC_REG0E 0x0E // Header Type - R
+#define FCH_LPC_REG0F 0x0F // BIST- R
+#define FCH_LPC_REG10 0x10 // Base Address Reg 0- RW*
+#define FCH_LPC_REG2C 0x2C // Subsystem ID & Subsystem Vendor ID - Wo/Ro
+#define FCH_LPC_REG34 0x34 // Capabilities Pointer - Ro
+#define FCH_LPC_REG40 0x40 // PCI Control - RW
+#define FCH_LPC_REG44 0x44 // IO Port Decode Enable Register 1- RW
+#define FCH_LPC_REG45 0x45 // IO Port Decode Enable Register 2- RW
+#define FCH_LPC_REG46 0x46 // IO Port Decode Enable Register 3- RW
+#define FCH_LPC_REG47 0x47 // IO Port Decode Enable Register 4- RW
+#define FCH_LPC_REG48 0x48 // IO/Mem Port Decode Enable Register 5- RW
+#define FCH_LPC_REG49 0x49 // LPC Sync Timeout Count - RW
+#define FCH_LPC_REG4A 0x4A // IO/Mem Port Decode Enable Register 6- RW
+#define FCH_LPC_REG4C 0x4C // Memory Range Register - RW
+#define FCH_LPC_REG50 0x50 // Rom Protect 0 - RW
+#define FCH_LPC_REG54 0x54 // Rom Protect 1 - RW
+#define FCH_LPC_REG58 0x58 // Rom Protect 2 - RW
+#define FCH_LPC_REG5C 0x5C // Rom Protect 3 - RW
+#define FCH_LPC_REG60 0x60 // PCI Memory Start Address of LPC Target Cycles -
+#define FCH_LPC_REG62 0x62 // PCI Memory End Address of LPC Target Cycles -
+#define FCH_LPC_REG64 0x64 // PCI IO base Address of Wide Generic Port - RW
+#define FCH_LPC_REG65 0x65
+#define FCH_LPC_REG66 0x66
+#define FCH_LPC_REG67 0x67
+#define FCH_LPC_REG68 0x68 // LPC ROM Address Range 1 (Start Address) - RW
+#define FCH_LPC_REG69 0x69
+#define FCH_LPC_REG6A 0x6A // LPC ROM Address Range 1 (End Address) - RW
+#define FCH_LPC_REG6B 0x6B
+#define FCH_LPC_REG6C 0x6C // LPC ROM Address Range 2 (Start Address)- RW
+#define FCH_LPC_REG6D 0x6D
+#define FCH_LPC_REG6E 0x6E // LPC ROM Address Range 2 (End Address) - RW
+#define FCH_LPC_REG6F 0x6F
+#define FCH_LPC_REG70 0x70 // Firmware ub Select - RW*
+#define FCH_LPC_REG71 0x71
+#define FCH_LPC_REG72 0x72
+#define FCH_LPC_REG73 0x73
+#define FCH_LPC_REG74 0x74 // Alternative Wide IO Range Enable- W/R
+#define FCH_LPC_REG78 0x78 // Miscellaneous Control Bits- W/R
+#define FCH_LPC_REG7C 0x7C // TPM (trusted plant form module) reg- W/R
+#define FCH_LPC_REG9C 0x9C
+#define FCH_LPC_REG80 0x80 // MSI Capability Register- R
+#define FCH_LPC_REGA0 0x0A0 // SPI base address
+#define FCH_LPC_REGA1 0x0A1 // SPI base address
+#define FCH_LPC_REGA2 0x0A2 // SPI base address
+#define FCH_LPC_REGA3 0x0A3 // SPI base address
+#define FCH_LPC_REGA4 0x0A4
+#define FCH_LPC_REGB8 0x0B8
+#define FCH_LPC_REGBA 0x0BA // EcControl
+#define FCH_LPC_REGBB 0x0BB // HostControl
+#define FCH_LPC_REGC8 0x0C8
+#define FCH_LPC_REGCC 0x0CC // AutoRomCfg
+#define FCH_LPC_REGD0 0x0D0
+#define FCH_LPC_REGD3 0x0D3
+#define FCH_LPC_REGD4 0x0D4
+
+//
+// FCH PCIB 0x780F
+// Device 20 (0x14) Func 4
+//
+#define FCH_PCIB_REG04 0x04 // Command
+#define FCH_PCIB_REG0D 0x0D // Primary Master Latency Timer
+#define FCH_PCIB_REG1B 0x1B // Secondary Latency Timer
+#define FCH_PCIB_REG1C 0x1C // IO Base
+#define FCH_PCIB_REG1D 0x1D // IO Limit
+#define FCH_PCIB_REG40 0x40 // CPCTRL
+#define FCH_PCIB_REG42 0x42 // CLKCTRL
+#define FCH_PCIB_REG48 0x48 //
+#define FCH_PCIB_REG4A 0x4A // PCICLK Enable Bits
+#define FCH_PCIB_REG4B 0x4B // Misc Control
+#define FCH_PCIB_REG4C 0x4C // AutoClockRun Control
+#define FCH_PCIB_REG50 0x50 // Dual Address Cycle Enable and PCIB_CLK_Stop Override
+#define FCH_PCIB_REG65 0x65 // Misc Control
+#define FCH_PCIB_REG66 0x66 // Misc Control
+//
+// FCH GEC 0x14E4 0x1699
+// Device 20 (0x14) Func 6
+//
+#define FCH_GEC_REG10 0x10 // GEC BAR
+
+//
+// FCH SD
+// Device 20 (0x14) Func 7
+//
+#define SD_PCI_REG10 0x10
+#define SD_PCI_REG2C 0x2C
+#define SD_PCI_REGA4 0xA4
+#define SD_PCI_REGA8 0xA8
+#define SD_PCI_REGAC 0xAC
+#define SD_PCI_REGB0 0xB0
+#define SD_PCI_REGB8 0xB8
+#define SD_PCI_REGBC 0xBC
+#define SD_PCI_REGD0 0xD0
+#define SD_PCI_REGF0 0xF0
+#define SD_PCI_REGF4 0xF4
+#define SD_PCI_REGF8 0xF8
+#define SD_PCI_REGFC 0xFC
+#define FCH_SD_BAR_REG28 0x28 // SDHC_CTRL1
+#define SD_CARD_PRESENT BIT0
+#define FCH_SD_BAR_REG2C 0x2C // SDHC_CTRL2
+#define FCH_SD_FREQUENCY_SLT BIT2
+#define FCH_SD_BAR_REG3C 0x3C // SDHC_HOST_CTRL2
+#define FCH_SD_1_8V BIT3
+
+//
+// FCH MMIO Base (SMI)
+// offset : 0x200
+//
+#define FCH_SMI_REG00 0x00 // EventStatus
+#define FCH_SMI_REG04 0x04 // EventEnable
+#define FCH_SMI_REG08 0x08 // SciTrig
+#define FCH_SMI_REG0C 0x0C // SciLevl
+#define FCH_SMI_REG10 0x10 // SmiSciStatus
+#define FCH_SMI_REG14 0x14 // SmiSciEn
+#define FCH_SMI_REG18 0x18 // ForceSciEn
+#define FCH_SMI_REG1C 0x1C // SciRwData
+#define FCH_SMI_REG3C 0x3C // DataErrorStatus
+#define FCH_SMI_REG20 0x20 // SciS0En
+#define FCH_SMI_Gevent0 0x40 // SciMap0
+#define FCH_SMI_Gevent1 0x41 // SciMap1
+#define FCH_SMI_Gevent2 0x42 // SciMap2
+#define FCH_SMI_Gevent3 0x43 // SciMap3
+#define FCH_SMI_Gevent4 0x44 // SciMap4
+#define FCH_SMI_Gevent5 0x45 // SciMap5
+#define FCH_SMI_Gevent6 0x46 // SciMap6
+#define FCH_SMI_Gevent7 0x47 // SciMap7
+#define FCH_SMI_Gevent8 0x48 // SciMap8
+#define FCH_SMI_Gevent9 0x49 // SciMap9
+#define FCH_SMI_Gevent10 0x4A // SciMap10
+#define FCH_SMI_Gevent11 0x4B // SciMap11
+#define FCH_SMI_Gevent12 0x4C // SciMap12
+#define FCH_SMI_Gevent13 0x4D // SciMap13
+#define FCH_SMI_Gevent14 0x4E // SciMap14
+#define FCH_SMI_Gevent15 0x4F // SciMap15
+#define FCH_SMI_Gevent16 0x50 // SciMap16
+#define FCH_SMI_Gevent17 0x51 // SciMap17
+#define FCH_SMI_Gevent18 0x52 // SciMap18
+#define FCH_SMI_Gevent19 0x53 // SciMap19
+#define FCH_SMI_Gevent20 0x54 // SciMap20
+#define FCH_SMI_Gevent21 0x55 // SciMap21
+#define FCH_SMI_Gevent22 0x56 // SciMap22
+#define FCH_SMI_Gevent23 0x57 // SciMap23
+#define FCH_SMI_Usbwakup0 0x58 // SciMap24
+#define FCH_SMI_Usbwakup1 0x59 // SciMap25
+#define FCH_SMI_Usbwakup2 0x5A // SciMap26
+#define FCH_SMI_Usbwakup3 0x5B // SciMap27
+#define FCH_SMI_SBGppPme0 0x5C // SciMap28
+#define FCH_SMI_SBGppPme1 0x5D // SciMap29
+#define FCH_SMI_SBGppPme2 0x5E // SciMap30
+#define FCH_SMI_SBGppPme3 0x5F // SciMap31
+#define FCH_SMI_SBGppHp0 0x60 // SciMap32
+#define FCH_SMI_SBGppHp1 0x61 // SciMap33
+#define FCH_SMI_SBGppHp2 0x62 // SciMap34
+#define FCH_SMI_SBGppHp3 0x63 // SciMap35
+#define FCH_SMI_AzaliaPme 0x64 // SciMap36
+#define FCH_SMI_SataGevent0 0x65 // SciMap37
+#define FCH_SMI_SataGevent1 0x66 // SciMap38
+#define FCH_SMI_GecPme 0x67 // SciMap39
+#define FCH_SMI_IMCGevent0 0x68 // SciMap40
+#define FCH_SMI_IMCGevent1 0x69 // SciMap41
+#define FCH_SMI_CIRPme 0x6A // SciMap42
+#define FCH_SMI_WakePinGevent 0x6B // SciMap43
+#define FCH_SMI_FanThGevent 0x6C // SciMap44 //FanThermalGevent
+#define FCH_SMI_ASFMasterIntr 0x6D // SciMap45
+#define FCH_SMI_ASFSlaveIntr 0x6E // SciMap46
+#define FCH_SMI_SMBUS0 0x6F // SciMap47
+#define FCH_SMI_TWARN 0x70 // SciMap48
+#define FCH_SMI_TMI 0x71 // SciMap49 // TrafficMonitorIntr
+#define FCH_SMI_iLLB 0x72 // SciMap50
+#define FCH_SMI_PowerButton 0x73 // SciMap51
+#define FCH_SMI_ProcHot 0x74 // SciMap52
+#define FCH_SMI_APUHwAssertion 0x75 // SciMap53
+#define FCH_SMI_APUSciAssertion 0x76 // SciMap54
+#define FCH_SMI_RAS 0x77 // SciMap55
+#define FCH_SMI_xHC0Pme 0x78 // SciMap56
+#define FCH_SMI_xHC1Pme 0x79 // SciMap57
+#define FCH_SMI_AcDcWake 0x7A // SciMap58
+
+// Empty from 0x72-0x7F
+//#Define FCH_SMI_REG7C 0x7F // SciMap63 ***
+
+#define FCH_SMI_REG80 0x80 // SmiStatus0
+#define FCH_SMI_REG84 0x84 // SmiStatus1
+#define FCH_SMI_REG88 0x88 // SmiStatus2
+#define FCH_SMI_REG8C 0x8C // SmiStatus3
+#define FCH_SMI_REG90 0x90 // SmiStatus4
+#define FCH_SMI_REG94 0x94 // SmiPointer
+#define FCH_SMI_REG96 0x96 // SmiTimer
+#define FCH_SMI_REG98 0x98 // SmiTrig
+#define FCH_SMI_REG9C 0x9C // SmiTrig
+#define FCH_SMI_REGA0 0xA0
+#define FCH_SMI_REGA1 0xA1
+#define FCH_SMI_REGA2 0xA2
+#define FCH_SMI_REGA3 0xA3
+#define FCH_SMI_REGA4 0xA4
+#define FCH_SMI_REGA5 0xA5
+#define FCH_SMI_REGA6 0xA6
+#define FCH_SMI_REGA7 0xA7
+#define FCH_SMI_REGA8 0xA8
+#define FCH_SMI_REGA9 0xA9
+#define FCH_SMI_REGAA 0xAA
+#define FCH_SMI_REGAB 0xAB
+#define FCH_SMI_REGAC 0xAC
+#define FCH_SMI_REGAD 0xAD
+#define FCH_SMI_REGAE 0xAE
+#define FCH_SMI_REGAF 0xAF
+#define FCH_SMI_REGB0 0xB0
+#define FCH_SMI_REGB1 0xB1
+#define FCH_SMI_REGB2 0xB2
+#define FCH_SMI_REGB3 0xB3
+#define FCH_SMI_REGB4 0xB4
+#define FCH_SMI_REGB5 0xB5
+#define FCH_SMI_REGB6 0xB6
+#define FCH_SMI_REGB7 0xB7
+#define FCH_SMI_REGB8 0xB8
+#define FCH_SMI_REGB9 0xB9
+#define FCH_SMI_REGBA 0xBA
+#define FCH_SMI_REGBB 0xBB
+#define FCH_SMI_REGBC 0xBC
+#define FCH_SMI_REGBD 0xBD
+#define FCH_SMI_REGBE 0xBE
+#define FCH_SMI_REGBF 0xBF
+#define FCH_SMI_REGC0 0xC0
+#define FCH_SMI_REGC1 0xC1
+#define FCH_SMI_REGC2 0xC2
+#define FCH_SMI_REGC3 0xC3
+#define FCH_SMI_REGC4 0xC4
+#define FCH_SMI_REGC5 0xC5
+#define FCH_SMI_REGC6 0xC6
+#define FCH_SMI_REGC7 0xC7
+#define FCH_SMI_REGC8 0xC8
+#define FCH_SMI_REGCA 0xCA // IoTrapping1
+#define FCH_SMI_REGCC 0xCC // IoTrapping2
+#define FCH_SMI_REGCE 0xCE // IoTrapping3
+#define FCH_SMI_TRAPPING_WRITE 0x01
+#define FCH_SMI_REGD0 0xD0 // MemTrapping0
+#define FCH_SMI_REGD4 0xD4 // MemRdOvrData0
+#define FCH_SMI_REGD8 0xD8 // MemTrapping1
+#define FCH_SMI_REGDC 0xDC // MemRdOvrData1
+#define FCH_SMI_REGE0 0xE0 // MemTrapping2
+#define FCH_SMI_REGE4 0xE4 // MemRdOvrData2
+#define FCH_SMI_REGE8 0xE8 // MemTrapping3
+#define FCH_SMI_REGEC 0xEC // MemRdOvrData3
+#define FCH_SMI_REGF0 0xF0 // CfgTrapping0
+#define FCH_SMI_REGF4 0xF4 // CfgTrapping1
+#define FCH_SMI_REGF8 0xF8 // CfgTrapping2
+#define FCH_SMI_REGFC 0xFC // CfgTrapping3
+
+//
+// FCH MMIO Base (PMIO)
+// offset : 0x300
+//
+#define FCH_PMIOA_REG00 0x00 // ISA Decode
+#define FCH_PMIOA_REG04 0x04 // ISA Control
+#define FCH_PMIOA_REG08 0x08 // PCI Control
+#define FCH_PMIOA_REG0C 0x0C // StpClkSmaf
+#define FCH_PMIOA_REG10 0x10 // RetryDetect
+#define FCH_PMIOA_REG14 0x14 // StuckDetect
+#define FCH_PMIOA_REG20 0x20 // BiosRamEn
+#define FCH_PMIOA_REG24 0x24 // AcpiMmioEn
+#define FCH_PMIOA_REG28 0x28 // AsfEn
+#define FCH_PMIOA_REG2C 0x2C // Smbus0En
+#define FCH_PMIOA_REG2E 0x2E // Smbus0Sel
+#define FCH_PMIOA_REG34 0x34 // IoApicEn
+#define FCH_PMIOA_REG3C 0x3C // SmartVoltEn
+#define FCH_PMIOA_REG40 0x40 // SmartVolt2En
+#define FCH_PMIOA_REG44 0x44 // BootTimerEn
+#define FCH_PMIOA_REG48 0x48 // WatchDogTimerEn
+#define FCH_PMIOA_REG4C 0x4C // WatchDogTimerConfig
+#define FCH_PMIOA_REG50 0x50 // HPETEn
+#define FCH_PMIOA_REG54 0x54 // SerialIrqConfig
+#define FCH_PMIOA_REG56 0x56 // RtcControl
+#define FCH_PMIOA_REG58 0x58 // VRT_T1
+#define FCH_PMIOA_REG59 0x59 // VRT_T2
+#define FCH_PMIOA_REG5A 0x5A // IntruderControl
+#define FCH_PMIOA_REG5B 0x5B // RtcShadow
+#define FCH_PMIOA_REG5C 0x5C
+#define FCH_PMIOA_REG5D 0x5D
+#define FCH_PMIOA_REG5E 0x5E // RtcExtIndex
+#define FCH_PMIOA_REG5F 0x5F // RtcExtData
+#define FCH_PMIOA_REG60 0x60 // AcpiPm1EvtBlk
+#define FCH_PMIOA_REG62 0x62 // AcpiPm1CntBlk
+#define FCH_PMIOA_REG64 0x64 // AcpiPmTmrBlk
+#define FCH_PMIOA_REG66 0x66 // P_CNTBlk
+#define FCH_PMIOA_REG68 0x68 // AcpiGpe0Blk
+#define FCH_PMIOA_REG6A 0x6A // AcpiSmiCmd
+#define FCH_PMIOA_REG6C 0x6C // AcpiPm2CntBlk
+#define FCH_PMIOA_REG6E 0x6E // AcpiPmaCntBlk
+#define FCH_PMIOA_REG74 0x74 // AcpiConfig
+#define FCH_PMIOA_REG78 0x78 // WakeIoAddr
+#define FCH_PMIOA_REG7A 0x7A // HaltCountEn
+#define FCH_PMIOA_REG7C 0x7C // C1eWrPortAdr
+#define FCH_PMIOA_REG7E 0x7E // CStateEn
+#define FCH_PMIOA_REG7F 0x7F // CStateEn
+#define FCH_PMIOA_REG80 0x80 // BreakEvent
+#define FCH_PMIOA_REG84 0x84 // AutoArbEn
+#define FCH_PMIOA_REG88 0x88 // CStateControl
+#define FCH_PMIOA_REG89 0x89 //
+#define FCH_PMIOA_REG8C 0x8C // StpClkHoldTime
+#define FCH_PMIOA_REG8E 0x8E // PopUpEndTime
+#define FCH_PMIOA_REG90 0x90 // C4Control
+#define FCH_PMIOA_REG94 0x94 // CStateTiming0
+#define FCH_PMIOA_REG96 0x96 //
+#define FCH_PMIOA_REG97 0x97 //
+#define FCH_PMIOA_REG98 0x98 // CStateTiming1
+#define FCH_PMIOA_REG99 0x99 //
+#define FCH_PMIOA_REG9B 0x9B //
+#define FCH_PMIOA_REG9C 0x9C // C2Count
+#define FCH_PMIOA_REG9D 0x9D // C3Count
+#define FCH_PMIOA_REG9E 0x9E // C4Count
+#define FCH_PMIOA_REGA0 0xA0 // MessageCState
+#define FCH_PMIOA_REGA4 0xA4 //
+#define FCH_PMIOA_REGA8 0xA8 // TrafficMonitorIdleTime
+#define FCH_PMIOA_REGAA 0xAA // TrafficMonitorIntTime
+#define FCH_PMIOA_REGAC 0xAC // TrafficMonitorTrafficCount
+#define FCH_PMIOA_REGAE 0xAE // TrafficMonitorIntrCount
+#define FCH_PMIOA_REGB0 0xB0 // TrafficMonitorTimeTick
+#define FCH_PMIOA_REGB4 0xB4 // FidVidControl
+#define FCH_PMIOA_REGB6 0xB6 // TPRESET1
+#define FCH_PMIOA_REGB7 0xB7 // Tpreset1b
+#define FCH_PMIOA_REGB8 0xB8 // TPRESET2
+#define FCH_PMIOA_REGB9 0xB9 // Test0
+#define FCH_PMIOA_REGBA 0xBA // S_StateControl
+#define FCH_PMIOA_REGBB 0xBB //
+#define FCH_PMIOA_REGBC 0xBC // ThrottlingControl
+#define FCH_PMIOA_REGBE 0xBE // ResetControl
+#define FCH_PMIOA_REGBF 0xBF // ResetControl
+#define FCH_PMIOA_REGC0 0xC0 // S5Status
+#define FCH_PMIOA_REGC2 0xC2 // ResetStatus
+#define FCH_PMIOA_REGC4 0xC4 // ResetCommand
+#define FCH_PMIOA_REGC5 0xC5 // CF9Shadow
+#define FCH_PMIOA_REGC6 0xC6 // HTControl
+#define FCH_PMIOA_REGC8 0xC8 // Misc
+#define FCH_PMIOA_REGCC 0xCC // IoDrvSth
+#define FCH_PMIOA_REGD0 0xD0 // CLKRunEn
+#define FCH_PMIOA_REGD2 0xD2 // PmioDebug
+#define FCH_PMIOA_REGD3 0xD3 // SD
+#define FCH_PMIOA_REGD6 0xD6 // IMCGating
+#define FCH_PMIOA_REGD7 0xD7 //
+#define FCH_PMIOA_REGD8 0xD8 // MiscIndex
+#define FCH_PMIOA_REGD9 0xD9 // MiscData
+#define FCH_PMIOA_REGDA 0xDA // SataConfig
+#define FCH_PMIOA_REGDC 0xDC // HyperFlashConfig
+#define FCH_PMIOA_REGDE 0xDE // ABConfig
+#define FCH_PMIOA_REGE0 0xE0 // ABRegBar
+#define FCH_PMIOA_REGE4 0xE4
+#define FCH_PMIOA_REGE6 0xE6 // FcEn
+#define FCH_PMIOA_REGE7 0xE7
+#define FCH_PMIOA_REGE8 0xE8
+#define FCH_PMIOA_REGEA 0xEA // PcibConfig
+#define FCH_PMIOA_REGEB 0xEB // AzEn
+#define FCH_PMIOA_REGEC 0xEC // LpcGating
+#define FCH_PMIOA_REGED 0xED // UsbGating
+#define FCH_PMIOA_REGEE 0xEE // UsbCntrl
+#define FCH_PMIOA_REGEF 0xEF // UsbEnable
+#define FCH_PMIOA_REGF0 0xF0 // UsbControl
+#define FCH_PMIOA_REGF2 0xF2 // UsbControl2
+#define FCH_PMIOA_REGF3 0xF3 // UsbDebug
+#define FCH_PMIOA_REGF4 0xF4 // UsbDebug
+#define FCH_PMIOA_REGF6 0xF6 // GecEn
+#define FCH_PMIOA_REGF8 0xF8 // GecConfig
+#define FCH_PMIOA_REGFC 0xFC // TraceMemoryEn
+
+//
+// FCH MMIO Base (PMIO2)
+// offset : 0x400
+//
+#define FCH_PMIO2_REG00 0x00 // Fan0InputControl
+#define FCH_PMIO2_REG01 0x01 // Fan0Control
+#define FCH_PMIO2_REG02 0x02 // Fan0Freq
+#define FCH_PMIO2_REG03 0x03 // LowDuty0
+#define FCH_PMIO2_REG04 0x04 // MidDuty0
+
+#define FCH_PMIO2_REG10 0x00 // Fan1InputControl
+#define FCH_PMIO2_REG11 0x01 // Fan1Control
+#define FCH_PMIO2_REG12 0x02 // Fan1Freq
+#define FCH_PMIO2_REG13 0x03 // LowDuty1
+#define FCH_PMIO2_REG14 0x04 // MidDuty1
+
+#define FCH_PMIO2_REG63 0x63 // SampleFreqDiv
+#define FCH_PMIO2_REG69 0x69 // Fan0 Speed
+#define FCH_PMIO2_REG95 0x95 // Temperature
+#define FCH_PMIO2_REGB8 0xB8 // Voltage
+#define FCH_PMIO2_REGEA 0xEA // Hwm_Calibration
+
+#define FCH_PMIO2_REG92 0x92 //
+#define FCH_PMIO2_REGF8 0xF8 // VoltageSamleSel
+#define FCH_PMIO2_REGF9 0xF9 // TempSampleSel
+
+#define FCH_PMIO2_REG 0xFC // TraceMemoryEn
+
+
+//
+// FCH MMIO Base (GPIO/IoMux)
+// offset : 0x100/0xD00
+//
+/*
+GPIO from 0 ~ 67, (GEVENT 0-23) 128 ~ 150, 160 ~ 226.
+*/
+#define FCH_GPIO_REG00 0x00
+#define FCH_GPIO_REG06 0x06
+#define FCH_GPIO_REG09 0x09
+#define FCH_GPIO_REG10 0x0A
+#define FCH_GPIO_REG17 0x11
+#define FCH_GPIO_REG21 0x15
+#define FCH_GPIO_REG28 0x1C
+#define FCH_GPIO_REG32 0x20
+#define FCH_GPIO_REG33 0x21
+#define FCH_GPIO_REG34 0x22
+#define FCH_GPIO_REG35 0x23
+#define FCH_GPIO_REG36 0x24
+#define FCH_GPIO_REG37 0x25
+#define FCH_GPIO_REG38 0x26
+#define FCH_GPIO_REG39 0x27
+#define FCH_GPIO_REG40 0x28
+#define FCH_GPIO_REG41 0x29
+#define FCH_GPIO_REG42 0x2A
+#define FCH_GPIO_REG43 0x2B
+#define FCH_GPIO_REG44 0x2C
+#define FCH_GPIO_REG45 0x2D
+#define FCH_GPIO_REG46 0x2E
+#define FCH_GPIO_REG47 0x2F
+#define FCH_GPIO_REG48 0x30
+#define FCH_GPIO_REG49 0x31
+#define FCH_GPIO_REG50 0x32
+#define FCH_GPIO_REG51 0x33
+#define FCH_GPIO_REG52 0x34
+#define FCH_GPIO_REG53 0x35
+#define FCH_GPIO_REG54 0x36
+#define FCH_GPIO_REG55 0x37
+#define FCH_GPIO_REG56 0x38
+#define FCH_GPIO_REG57 0x39
+#define FCH_GPIO_REG58 0x3A
+#define FCH_GPIO_REG59 0x3B
+#define FCH_GPIO_REG60 0x3C
+#define FCH_GPIO_REG61 0x3D
+#define FCH_GPIO_REG62 0x3E
+#define FCH_GPIO_REG63 0x3F
+#define FCH_GPIO_REG64 0x40
+#define FCH_GPIO_REG65 0x41
+#define FCH_GPIO_REG66 0x42
+#define FCH_GPIO_REG67 0x43
+#define FCH_GPIO_REG68 0x44
+#define FCH_GPIO_REG69 0x45
+#define FCH_GPIO_REG70 0x46
+#define FCH_GPIO_REG71 0x47
+#define FCH_GPIO_REG72 0x48
+#define FCH_GPIO_REG73 0x49
+#define FCH_GPIO_REG74 0x4A
+#define FCH_GPIO_REG75 0x4B
+#define FCH_GPIO_REG76 0x4C
+#define FCH_GPIO_REG77 0x4D
+#define FCH_GPIO_REG78 0x4E
+#define FCH_GPIO_REG79 0x4F
+#define FCH_GPIO_REG80 0x50
+
+#define FCH_GEVENT_REG00 0x60
+#define FCH_GEVENT_REG01 0x61
+#define FCH_GEVENT_REG02 0x62
+#define FCH_GEVENT_REG03 0x63
+#define FCH_GEVENT_REG04 0x64
+#define FCH_GEVENT_REG05 0x65
+#define FCH_GEVENT_REG06 0x66
+#define FCH_GEVENT_REG07 0x67
+#define FCH_GEVENT_REG08 0x68
+#define FCH_GEVENT_REG09 0x69
+#define FCH_GEVENT_REG10 0x6A
+#define FCH_GEVENT_REG11 0x6B
+#define FCH_GEVENT_REG12 0x6C
+#define FCH_GEVENT_REG13 0x6D
+#define FCH_GEVENT_REG14 0x6E
+#define FCH_GEVENT_REG15 0x6F
+#define FCH_GEVENT_REG16 0x70
+#define FCH_GEVENT_REG17 0x71
+#define FCH_GEVENT_REG18 0x72
+#define FCH_GEVENT_REG19 0x73
+#define FCH_GEVENT_REG20 0x74
+#define FCH_GEVENT_REG21 0x75
+#define FCH_GEVENT_REG22 0x76
+#define FCH_GEVENT_REG23 0x77
+// S5-DOMAIN GPIO
+#define FCH_GPIO_REG160 0xA0
+#define FCH_GPIO_REG161 0xA1
+#define FCH_GPIO_REG162 0xA2
+#define FCH_GPIO_REG163 0xA3
+#define FCH_GPIO_REG164 0xA4
+#define FCH_GPIO_REG165 0xA5
+#define FCH_GPIO_REG166 0xA6
+#define FCH_GPIO_REG167 0xA7
+#define FCH_GPIO_REG168 0xA8
+#define FCH_GPIO_REG169 0xA9
+#define FCH_GPIO_REG170 0xAA
+#define FCH_GPIO_REG171 0xAB
+#define FCH_GPIO_REG172 0xAC
+#define FCH_GPIO_REG173 0xAD
+#define FCH_GPIO_REG174 0xAE
+#define FCH_GPIO_REG175 0xAF
+#define FCH_GPIO_REG176 0xB0
+#define FCH_GPIO_REG177 0xB1
+#define FCH_GPIO_REG178 0xB2
+#define FCH_GPIO_REG179 0xB3
+#define FCH_GPIO_REG180 0xB4
+#define FCH_GPIO_REG181 0xB5
+#define FCH_GPIO_REG182 0xB6
+#define FCH_GPIO_REG183 0xB7
+#define FCH_GPIO_REG184 0xB8
+#define FCH_GPIO_REG185 0xB9
+#define FCH_GPIO_REG186 0xBA
+#define FCH_GPIO_REG187 0xBB
+#define FCH_GPIO_REG188 0xBC
+#define FCH_GPIO_REG189 0xBD
+#define FCH_GPIO_REG190 0xBE
+#define FCH_GPIO_REG191 0xBF
+#define FCH_GPIO_REG192 0xC0
+#define FCH_GPIO_REG193 0xC1
+#define FCH_GPIO_REG194 0xC2
+#define FCH_GPIO_REG195 0xC3
+#define FCH_GPIO_REG196 0xC4
+#define FCH_GPIO_REG197 0xC5
+#define FCH_GPIO_REG198 0xC6
+#define FCH_GPIO_REG199 0xC7
+#define FCH_GPIO_REG200 0xC8
+#define FCH_GPIO_REG201 0xC9
+#define FCH_GPIO_REG202 0xCA
+#define FCH_GPIO_REG203 0xCB
+#define FCH_GPIO_REG204 0xCC
+#define FCH_GPIO_REG205 0xCD
+#define FCH_GPIO_REG206 0xCE
+#define FCH_GPIO_REG207 0xCF
+#define FCH_GPIO_REG208 0xD0
+#define FCH_GPIO_REG209 0xD1
+#define FCH_GPIO_REG210 0xD2
+#define FCH_GPIO_REG211 0xD3
+#define FCH_GPIO_REG212 0xD4
+#define FCH_GPIO_REG213 0xD5
+#define FCH_GPIO_REG214 0xD6
+#define FCH_GPIO_REG215 0xD7
+#define FCH_GPIO_REG216 0xD8
+#define FCH_GPIO_REG217 0xD9
+#define FCH_GPIO_REG218 0xDA
+#define FCH_GPIO_REG219 0xDB
+#define FCH_GPIO_REG220 0xDC
+#define FCH_GPIO_REG221 0xDD
+#define FCH_GPIO_REG222 0xDE
+#define FCH_GPIO_REG223 0xDF
+#define FCH_GPIO_REG224 0xF0
+#define FCH_GPIO_REG225 0xF1
+#define FCH_GPIO_REG226 0xF2
+#define FCH_GPIO_REG227 0xF3
+#define FCH_GPIO_REG228 0xF4
+
+//
+// FCH MMIO Base (GPIO BANK0)
+// offset : 0x1500
+//
+#define FCH_GPIO_PULL_UP_ENABLE BIT4
+#define FCH_GPIO_PULL_DOWN_ENABLE BIT5
+#define FCH_GPIO_OUTPUT_VALUE BIT6
+#define FCH_GPIO_OUTPUT_ENABLE (1 << 7)
+
+#define FCH_GPIO_068_AZ_SDIN0_GPIO26 0x68
+#define FCH_GPIO_06C_AZ_SDIN1_GPIO27 0x6C
+#define FCH_GPIO_070_AZ_SDIN2_GPIO28 0x70
+#define FCH_GPIO_074_AZ_SDIN3_GPIO29 0x74
+
+#define FCH_GPIO_10C_GPIO55_AGPI067 0x10C
+#define FCH_GPIO_118_GPIO59_AGPI070 0x118
+
+//
+// FCH MMIO Base (IoMux)
+// offset : 0xD00
+//
+#define FCH_IOMUX_1A_AZ_SDIN0_EGPIO26 0x1A
+#define FCH_IOMUX_1B_AZ_SDIN1_EGPIO27 0x1B
+#define FCH_IOMUX_1C_AZ_SDIN2_EGPIO28 0x1C
+#define FCH_IOMUX_1D_AZ_SDIN3_EGPIO29 0x1D
+
+//
+// FCH MMIO Base (SMBUS)
+// offset : 0xA00
+//
+#define FCH_SMBUS_REG12 0x12 // I2CbusConfig
+
+//
+// FCH MMIO Base (MISC)
+// offset : 0xE00
+//
+#define FCH_MISC_REG00 0x00 // ClkCntrl0
+/*
+FCH_MISC_REG00 EQU 000h
+ ClkCntrl0 EQU 0FFFFFFFFh
+*/
+#define FCH_MISC_REG04 0x04 // ClkCntrl1
+/*
+FCH_MISC_REG04 EQU 004h
+ ClkCntrl1 EQU 0FFFFFFFFh
+*/
+#define FCH_MISC_REG08 0x08 // ClkCntrl2
+/*
+FCH_MISC_REG08 EQU 008h
+ ClkCntrl2 EQU 0FFFFFFFFh
+*/
+#define FCH_MISC_REG0C 0x0C // ClkCntrl3
+/*
+FCH_MISC_REG0C EQU 00Ch
+ ClkCntrl3 EQU 0FFFFFFFFh
+*/
+#define FCH_MISC_REG10 0x10 // ClkCntrl4
+/*
+FCH_MISC_REG10 EQU 010h
+ ClkCntrl4 EQU 0FFFFFFFFh
+*/
+#define FCH_MISC_REG14 0x14 // ClkCntrl5
+/*
+FCH_MISC_REG14 EQU 014h
+ ClkCntrl5 EQU 0FFFFFFFFh
+*/
+#define FCH_MISC_REG18 0x18 // ClkCntrl6
+/*
+FCH_MISC_REG18 EQU 018h
+ ClkCntrl6 EQU 0FFFFFFFFh
+*/
+#define FCH_MISC_REG1C 0x1C
+#define FCH_MISC_REG30 0x30 // OscFreqCounter
+/*
+FCH_MISC_REG30 EQU 030h
+ OscCounter EQU 0FFFFFFFFh ; The 32bit register shows the number of OSC clock per second.
+*/
+#define FCH_MISC_REG34 0x34 // HpetClkPeriod
+/*
+FCH_MISC_REG34 EQU 034h
+ HpetClkPeriod EQU 0FFFFFFFFh ; default - 0x429B17Eh (14.31818M).
+*/
+#define FCH_MISC_REG28 0x28 // ClkDrvSth2
+#define FCH_MISC_REG2C 0x2C
+#define FCH_MISC_REG40 0x40 // MiscCntrl for clock only
+#define FCH_MISC_REG41 0x41 // MiscCntr2
+#define FCH_MISC_REG42 0x42 // MiscCntr3
+#define FCH_MISC_REG44 0x44 // ValueOnPort80
+#define FCH_MISC_REG50 0x50 //
+#define FCH_MISCx50_JTAG_CONTROL_ECO 0xFED80E50ul //
+#define FCH_MISCx68_MEMORY_POWER_SAVING_CONTROL 0xFED80E68ul //
+
+#define FCH_MISC_REG6C 0x6C // EcoBit2
+/*
+FCH_MISC_REG40 EQU 040h
+*/
+
+#define FCH_MISC_REG80 0x80 /**< FCH_MISC_REG80
+ * @par
+ * StrapStatus [15.0] - FCH chip Strap Status
+ * @li <b>0001</b> - Not USED FWH
+ * @li <b>0002</b> - Not USED LPC ROM
+ * @li <b>0004</b> - EC enabled
+ * @li <b>0008</b> - Reserved
+ * @li <b>0010</b> - Internal Clock mode
+ */
+#define FCH_MISC_REGB6 0xB6 //
+
+#define ChipSysNotUseFWHRom 0x0001 // EcPwm3 pad
+#define ChipSysNotUseLpcRom 0x0002 // Inverted version from EcPwm2 pad (default - 1)
+ // Note: Both EcPwm3 and EcPwm2 straps pins are used to select boot ROM type.
+#define ChipSysEcEnable 0x0004 // Enable Embedded Controller (EC)
+#define ChipSysBootFailTmrEn 0x0008 // Enable Watchdog function
+#define ChipSysIntClkGen 0x0010 // Select 25Mhz crystal clock or 100Mhz PCI-E clock **
+
+#define FCH_MISC_REG84 0x84 // StrapOverride
+/*
+FCH_MISC_REG84 EQU 084h
+ Override FWHDisableStrap EQU BIT0 ; Override FWHDiableStrap value from external pin.
+ Override UseLpcRomStrap EQU BIT1 ; Override UseLpcRomStrap value from external pin.
+ Override EcEnableStrap EQU BIT2 ; Override EcEnableStrap value from external pin.
+ Override BootFailTmrEnStrap EQU BIT3 ; Override BootFailTmrEnStrap value from external pin.
+ Override DefaultModeStrap EQU BIT5 ; Override DefaultModeStrap value from external pin.
+ Override I2CRomStrap EQU BIT7 ; Override I2CRomStrap value from external pin.
+ Override ILAAutorunEnBStrap EQU BIT8 ; Override ILAAutorunEnBStrap value from external pin.
+ Override FcPllBypStrap EQU BIT9 ; Override FcPllBypStrap value from external pin.
+ Override PciPllBypStrap EQU BIT10 ; Override PciPllBypStrap value from external pin.
+ Override ShortResetStrap EQU BIT11 ; Override ShortResetStrap value from external pin.
+ Override FastBif2ClkStrap EQU BIT13 ; Override FastBif2ClkStrap value from external pin
+ PciRomBootStrap EQU BIT15 ; Override PCI Rom Boot Strap value from external pin
+ BlinkSlowModestrap EQU BIT16 ; Override Blink Slow mode (100Mhz) from external pin
+ ClkGenStrap EQU BIT17 ; Override CLKGEN from external pin.
+ BIF_GEN2_COMPL_Strap EQU BIT18 ; Override BIF_ GEN2_COMPLIANCE strap from external pin.
+ StrapOverrideEn EQU BIT31 ; Enable override strapping feature.
+*/
+#define FCH_MISC_REGC0 0xC0 // CPU_Pstate0
+/*
+FCH_MISC_REGC0 EQU 0C0h
+ Core0_PState EQU BIT0+BIT1+BIT2 ; 000: P0 001: P1 010: P2 011: P3 100: P4 101: P5 110: P6 111: P7
+ Core1_PState EQU BIT4+BIT5+BIT6
+ Core2_PState EQU BIT8+BIT9+BIT10
+ Core3_PState EQU BIT12+BIT13+BIT14
+ Core4_PState EQU BIT16++BIT17+BIT18
+ Core5_PState EQU BIT20+BIT21+BIT22
+ Core6_PState EQU BIT24+BIT25+BIT26
+ Core7_PState EQU BIT28+BIT29+BIT30
+*/
+#define FCH_MISC_REGC4 0xC4 // CPU_Pstate1
+/*
+FCH_MISC_REGC4 EQU 0C4h
+ Core8_PState EQU BIT0+BIT1+BIT2 ; 000: P0 001: P1 010: P2 011: P3 100: P4 101: P5 110: P6 111: P7
+ Core9_PState EQU BIT4+BIT5+BIT6
+ Core10_PState EQU BIT8+BIT9+BIT10
+ Core11_PState EQU BIT12+BIT13+BIT14
+ Core12_PState EQU BIT16++BIT17+BIT18
+ Core13_PState EQU BIT20+BIT21+BIT22
+ Core14_PState EQU BIT24+BIT25+BIT26
+ Core15_PState EQU BIT28+BIT29+BIT30
+*/
+#define FCH_MISC_REGD0 0xD0 // CPU_Cstate0
+/*
+FCH_MISC_REGD0 EQU 0D0h
+ Core0_CState EQU BIT0+BIT1+BIT2 ; 000: C0 001: C1 010: C2 011: C3 100: C4 101: C5 110: C6 111: C7
+ Core1_CState EQU BIT4+BIT5+BIT6
+ Core2_CState EQU BIT8+BIT9+BIT10
+ Core3_CState EQU BIT12+BIT13+BIT14
+ Core4_CState EQU BIT16++BIT17+BIT18
+ Core5_CState EQU BIT20+BIT21+BIT22
+ Core6_CState EQU BIT24+BIT25+BIT26
+ Core7_CState EQU BIT28+BIT29+BIT30
+*/
+#define FCH_MISC_REGD4 0xD4 // CPU_Cstate1
+/*
+FCH_MISC_REGD4 EQU 0D4h
+ Core8_CState EQU BIT0+BIT1+BIT2 ; 000: C0 001: C1 010: C2 011: C3 100: C4 101: C5 110: C6 111: C7
+ Core9_CState EQU BIT4+BIT5+BIT6
+ Core10_CState EQU BIT8+BIT9+BIT10
+ Core11_CState EQU BIT12+BIT13+BIT14
+ Core12_CState EQU BIT16++BIT17+BIT18
+ Core13_CState EQU BIT20+BIT21+BIT22
+ Core14_CState EQU BIT24+BIT25+BIT26
+ Core15_CState EQU BIT28+BIT29+BIT30
+*/
+#define FCH_MISC_REGF0 0xF0 // SataPortSts
+/*
+FCH_MISC_REGF0 EQU 0F0h
+ Port0Sts EQU BIT0 ; The selected status of Port 0.
+ Port1Sts EQU BIT1 ; The selected status of Port 1
+ Port2Sts EQU BIT2 ; The selected status of Port 2.
+ Port3Sts EQU BIT3 ; The selected status of Port 3
+ Port4Sts EQU BIT4 ; The selected status of Port 4.
+ Port5Sts EQU BIT5 ; The selected status of Port 5
+ SataPortSel EQU BIT24+BIT25 ; 00 - Select "led" for Port 0 to 5
+ ; 01 - Select "delete" for Port 0 to 5
+ ; 10 - Select "err" for Port 0 to 5
+ ; 11 - Select "led" for Port 0 to 5
+*/
+
+//
+// FCH MMIO Base (SERIAL_DEBUG_BASE)
+// offset : 0x1000
+//
+#define FCH_SDB_REG00 0x00 //
+#define FCH_SDB_REG74 0x74
+
+#define FCH_RTC_REG00 0x00 // Seconds - RW
+#define FCH_RTC_REG01 0x01 // Seconds Alarm - RW
+#define FCH_RTC_REG02 0x02 // Minutes - RW
+#define FCH_RTC_REG03 0x03 // Minutes Alarm - RW
+#define FCH_RTC_REG04 0x04 // ours - RW
+#define FCH_RTC_REG05 0x05 // ours Alarm- RW
+#define FCH_RTC_REG06 0x06 // Day of Week - RW
+#define FCH_RTC_REG07 0x07 // Date of Mont - RW
+#define FCH_RTC_REG08 0x08 // Mont - RW
+#define FCH_RTC_REG09 0x09 // Year - RW
+#define FCH_RTC_REG0A 0x0A // Register A - RW
+#define FCH_RTC_REG0B 0x0B // Register B - RW
+#define FCH_RTC_REG0C 0x0C // Register C - R
+#define FCH_RTC_REG0D 0x0D // DateAlarm - RW
+#define FCH_RTC_REG32 0x32 // AltCentury - RW
+#define FCH_RTC_REG48 0x48 // Century - RW
+#define FCH_RTC_REG50 0x50 // Extended RAM Address Port - RW
+#define FCH_RTC_REG53 0x53 // Extended RAM Data Port - RW
+#define FCH_RTC_REG7E 0x7E // RTC Time Clear - RW
+#define FCH_RTC_REG7F 0x7F // RTC RAM Enable - RW
+
+#define FCH_ECMOS_REG00 0x00 // scratch - reg
+//;BIT0=0 AsicDebug is enabled
+//;BIT1=0 SLT S3 runs
+#define FCH_ECMOS_REG01 0x01
+#define FCH_ECMOS_REG02 0x02
+#define FCH_ECMOS_REG03 0x03
+#define FCH_ECMOS_REG04 0x04
+#define FCH_ECMOS_REG05 0x05
+#define FCH_ECMOS_REG06 0x06
+#define FCH_ECMOS_REG07 0x07
+#define FCH_ECMOS_REG08 0x08 // save 32BIT Physical address of Config structure
+#define FCH_ECMOS_REG09 0x09
+#define FCH_ECMOS_REG0A 0x0A
+#define FCH_ECMOS_REG0B 0x0B
+
+#define FCH_ECMOS_REG0C 0x0C //;save MODULE_ID
+#define FCH_ECMOS_REG0D 0x0D //;Reserve for NB
+
+//
+// FCH AOAC Base (FCH_AOAC_BASE)
+// offset : 0x1E00
+//
+#define FCH_AOACx94S013_CONTROL 0xFED81E94ul //
+#define FCH_AOACx94S013_CONTROL_ARBITER_DIS (1 << 14)
+#define FCH_AOACx94S013_CONTROL_INTERRUPT_DIS (1 << 15)
+
+#define FCH_IOMAP_REG00 0x000 // Dma_C 0
+#define FCH_IOMAP_REG02 0x002 // Dma_C 1
+#define FCH_IOMAP_REG04 0x004 // Dma_C 2
+#define FCH_IOMAP_REG06 0x006 // Dma_C 3
+#define FCH_IOMAP_REG08 0x008 // Dma_Status
+#define FCH_IOMAP_REG09 0x009 // Dma_WriteRest
+#define FCH_IOMAP_REG0A 0x00A // Dma_WriteMask
+#define FCH_IOMAP_REG0B 0x00B // Dma_WriteMode
+#define FCH_IOMAP_REG0C 0x00C // Dma_Clear
+#define FCH_IOMAP_REG0D 0x00D // Dma_MasterClr
+#define FCH_IOMAP_REG0E 0x00E // Dma_ClrMask
+#define FCH_IOMAP_REG0F 0x00F // Dma_AllMask
+#define FCH_IOMAP_REG20 0x020 // IntrCntrlReg1
+#define FCH_IOMAP_REG21 0x021 // IntrCntrlReg2
+#define FCH_IOMAP_REG40 0x040 // TimerC0
+#define FCH_IOMAP_REG41 0x041 // TimerC1
+#define FCH_IOMAP_REG42 0x042 // TimerC2
+#define FCH_IOMAP_REG43 0x043 // Tmr1CntrlWord
+#define FCH_IOMAP_REG61 0x061 // Nmi_Status
+#define FCH_IOMAP_REG70 0x070 // Nmi_Enable
+#define FCH_IOMAP_REG71 0x071 // RtcDataPort
+#define FCH_IOMAP_REG72 0x072 // AlternatRtcAddrPort
+#define FCH_IOMAP_REG73 0x073 // AlternatRtcDataPort
+#define FCH_IOMAP_REG80 0x080 // Dma_Page_Reserved0
+#define FCH_IOMAP_REG81 0x081 // Dma_PageC2
+#define FCH_IOMAP_REG82 0x082 // Dma_PageC3
+#define FCH_IOMAP_REG83 0x083 // Dma_PageC1
+#define FCH_IOMAP_REG84 0x084 // Dma_Page_Reserved1
+#define FCH_IOMAP_REG85 0x085 // Dma_Page_Reserved2
+#define FCH_IOMAP_REG86 0x086 // Dma_Page_Reserved3
+#define FCH_IOMAP_REG87 0x087 // Dma_PageC0
+#define FCH_IOMAP_REG88 0x088 // Dma_Page_Reserved4
+#define FCH_IOMAP_REG89 0x089 // Dma_PageC6
+#define FCH_IOMAP_REG8A 0x08A // Dma_PageC7
+#define FCH_IOMAP_REG8B 0x08B // Dma_PageC5
+#define FCH_IOMAP_REG8C 0x08C // Dma_Page_Reserved5
+#define FCH_IOMAP_REG8D 0x08D // Dma_Page_Reserved6
+#define FCH_IOMAP_REG8E 0x08E // Dma_Page_Reserved7
+#define FCH_IOMAP_REG8F 0x08F // Dma_Refres
+#define FCH_IOMAP_REG92 0x092 // FastInit
+#define FCH_IOMAP_REGA0 0x0A0 // IntrCntrl2Reg1
+#define FCH_IOMAP_REGA1 0x0A1 // IntrCntrl2Reg2
+#define FCH_IOMAP_REGC0 0x0C0 // Dma2_C4Addr
+#define FCH_IOMAP_REGC2 0x0C2 // Dma2_C4Cnt
+#define FCH_IOMAP_REGC4 0x0C4 // Dma2_C5Addr
+#define FCH_IOMAP_REGC6 0x0C6 // Dma2_C5Cnt
+#define FCH_IOMAP_REGC8 0x0C8 // Dma2_C6Addr
+#define FCH_IOMAP_REGCA 0x0CA // Dma2_C6Cnt
+#define FCH_IOMAP_REGCC 0x0CC // Dma2_C7Addr
+#define FCH_IOMAP_REGCE 0x0CE // Dma2_C7Cnt
+#define FCH_IOMAP_REGD0 0x0D0 // Dma_Status
+#define FCH_IOMAP_REGD2 0x0D2 // Dma_WriteRest
+#define FCH_IOMAP_REGD4 0x0D4 // Dma_WriteMask
+#define FCH_IOMAP_REGD6 0x0D6 // Dma_WriteMode
+#define FCH_IOMAP_REGD8 0x0D8 // Dma_Clear
+#define FCH_IOMAP_REGDA 0x0DA // Dma_Clear
+#define FCH_IOMAP_REGDC 0x0DC // Dma_ClrMask
+#define FCH_IOMAP_REGDE 0x0DE // Dma_ClrMask
+#define FCH_IOMAP_REGF0 0x0F0 // NCP_Error
+#define FCH_IOMAP_REG40B 0x040B // DMA1_Extend
+#define FCH_IOMAP_REG4D0 0x04D0 // IntrEdgeControl
+#define FCH_IOMAP_REG4D6 0x04D6 // DMA2_Extend
+#define FCH_IOMAP_REGC00 0x0C00 // Pci_Intr_Index
+#define FCH_IOMAP_REGC01 0x0C01 // Pci_Intr_Data
+#define FCH_IOMAP_REGC14 0x0C14 // Pci_Error
+#define FCH_IOMAP_REGC50 0x0C50 // CMIndex
+#define FCH_IOMAP_REGC51 0x0C51 // CMData
+#define FCH_IOMAP_REGC52 0x0C52 // GpmPort
+#define FCH_IOMAP_REGC6F 0x0C6F // Isa_Misc
+#define FCH_IOMAP_REGCD0 0x0CD0 // PMio2_Index
+#define FCH_IOMAP_REGCD1 0x0CD1 // PMio2_Data
+#define FCH_IOMAP_REGCD4 0x0CD4 // BIOSRAM_Index
+#define FCH_IOMAP_REGCD5 0x0CD5 // BIOSRAM_Data
+#define FCH_IOMAP_REGCD6 0x0CD6 // PM_Index
+#define FCH_IOMAP_REGCD7 0x0CD7 // PM_Data
+#define FCH_IOMAP_REGCF9 0x0CF9 // CF9Rst reg
+
+#define FCH_IRQ_INTA 0x00 // INTA#
+#define FCH_IRQ_INTB 0x01 // INTB#
+#define FCH_IRQ_INTC 0x02 // INTC#
+#define FCH_IRQ_INTD 0x03 // INTD#
+#define FCH_IRQ_INTE 0x04 // INTE#
+#define FCH_IRQ_INTF 0x05 // INTF#
+#define FCH_IRQ_INTG 0x06 // INTG#
+#define FCH_IRQ_INTH 0x07 // INTH#
+#define FCH_IRQ_SCI 0x10 // SCI
+#define FCH_IRQ_SMBUS0 0x11 // SMBUS0
+#define FCH_IRQ_ASF 0x12 // ASF
+#define FCH_IRQ_HDAUDIO 0x13 // HD Audio
+#define FCH_IRQ_FC 0x14 // FC
+#define FCH_IRQ_GEC 0x15 // GEC
+#define FCH_IRQ_SD 0x17 // SD
+#define FCH_IRQ_IMCINT0 0x20 // IMC INT0
+#define FCH_IRQ_IMCINT1 0x21 // IMC INT1
+#define FCH_IRQ_IMCINT2 0x22 // IMC INT2
+#define FCH_IRQ_IMCINT3 0x23 // IMC INT3
+#define FCH_IRQ_IMCINT4 0x24 // IMC INT4
+#define FCH_IRQ_IMCINT5 0x25 // IMC INT5
+#define FCH_IRQ_USB18INTA 0x30 // Dev 18 (USB) INTA#
+#define FCH_IRQ_USB18INTB 0x31 // Dev 18 (USB) INTB#
+#define FCH_IRQ_USB19INTA 0x32 // Dev 19 (USB) INTA#
+#define FCH_IRQ_USB19INTB 0x33 // Dev 19 (USB) INTB#
+#define FCH_IRQ_USB22INTA 0x34 // Dev 22 (USB) INTA#
+#define FCH_IRQ_USB22INTB 0x35 // Dev 22 (USB) INTB#
+#define FCH_IRQ_USB20INTC 0x36 // Dev 20 (USB) INTC#
+#define FCH_IRQ_IDE 0x40 // IDE pci interrupt
+#define FCH_IRQ_SATA 0x41 // SATA pci interrupt
+#define FCH_IRQ_GPPINT0 0x50 // Gpp Int0
+#define FCH_IRQ_GPPINT1 0x51 // Gpp Int1
+#define FCH_IRQ_GPPINT2 0x52 // Gpp Int2
+#define FCH_IRQ_GPPINT3 0x53 // Gpp Int3
+#define FCH_IRQ_GPIO 0x62 // GPIO Controller
+#define FCH_IRQ_IOAPIC 0x80 // Select IRQ routing to IoApic mode
+#define FCH_IRQ_PIC 0x00 // Select IRQ routing to PIC mode
+
+#define FCH_SPI_MMIO_REG00 0x00 //SPI_
+#define FCH_SPI_OPCODE 0x000000FFl //
+#define FCH_SPI_TX_COUNT 0x00000F00l //
+#define FCH_SPI_RX_COUNT 0x0000F000l //
+#define FCH_SPI_EXEC_OPCODE 0x00010000l //
+#define FCH_SPI_FIFO_PTR_CRL 0x00100000l //
+#define FCH_SPI_FIFO_PTR_INC 0x00200000l //
+#define FCH_SPI_BUSY 0x80000000l //
+#define FCH_SPI_MMIO_REG0C 0x0C //SPI_Cntrl1 Register
+#define FCH_SPI_PARAMETER 0x000000FFl //
+#define FCH_SPI_FIFO_PTR 0x00000700l //
+#define FCH_SPI_BYTE_PROGRAM 0xFF000000l //
+#define FCH_SPI_MMIO_REG1C 0x1C //
+#define FCH_SPI_RETRY_TIMES 0x3 //
+
+#define FCH_SPI_MMIO_REG1D 0x1D //
+#define FCH_SPI_MMIO_REG1E 0x1E //
+#define FCH_SPI_MMIO_REG1F 0x1F //
+#define FCH_SPI_MMIO_REG4E 0x4E //
+
+#define FCH_SPI_MMIO_REG1F_X05_TX_BYTE_COUNT 0x05 //
+#define FCH_SPI_MMIO_REG1F_X06_RX_BYTE_COUNT 0x06 //
+
+#define FCH_SPI_MMIO_REG20 0x20 //
+#define FCH_SPI_MMIO_REG22 0x22 //
+#define FCH_SPI_MMIO_REG38 0x38 //
+#define FCH_SPI_MMIO_REG3C 0x3C //
+
+#define FCH_SPI_MMIO_REG45_CMDCODE 0x45 //
+#define FCH_SPI_MMIO_REG47_CMDTRIGGER 0x47 //
+#define FCH_SPI_MMIO_REG48_TXBYTECOUNT 0x48 //
+#define FCH_SPI_MMIO_REG4B_RXBYTECOUNT 0x4B //
+#define FCH_SPI_MMIO_REG4C_SPISTATUS 0x4C //
+#define FCH_SPI_MMIO_REG80_FIFO 0x80 //
+
+#define FCH_SPI_MODE_FAST 0x7 //
+#define FCH_SPI_MODE_NORMAL 0x6 //
+#define FCH_SPI_MODE_QUAL_144 0x5 //
+#define FCH_SPI_MODE_QUAL_122 0x4 //
+#define FCH_SPI_MODE_QUAL_114 0x3 //
+#define FCH_SPI_MODE_QUAL_112 0x2 //
+
+#define FCH_SPI_DEVICE_MODE_DIS 0x7 //
+#define FCH_SPI_DEVICE_MODE_144 0x4 //
+#define FCH_SPI_DEVICE_MODE_114 0x3 //
+#define FCH_SPI_DEVICE_MODE_122 0x2 //
+#define FCH_SPI_DEVICE_MODE_112 0x1 //
+#define FCH_SPI_DEVICE_MODE_FAST 0x0 //
+
+#define FCH_SPI_SPEED_16M 0x4 //
+#define FCH_SPI_SPEED_22M 0x3 //
+#define FCH_SPI_SPEED_33M 0x2 //
+#define FCH_SPI_SPEED_66M 0x1 //
+#define FCH_SPI_SPEED_100M 0x5 //
+
+#define AMD_NB_REG78 0x78
+#define AMD_NB_SCRATCH AMD_NB_REG78
+#define MailBoxPort 0x3E
+
+#define MAX_LT_POLLINGS 0x4000
+#define SMI_TIMER_ENABLE BIT15
+
+
+#define ACPIMMIO32(x) (*(volatile UINT32*)(UINTN)(x))
+#define ACPIMMIO16(x) (*(volatile UINT16*)(UINTN)(x))
+#define ACPIMMIO8(x) (*(volatile UINT8*)(UINTN)(x))
+
+#define U3PLL_LOCK BIT7
+#define U3PLL_RESET BIT8
+#define U3PHY_RESET BIT9
+#define U3CORE_RESET BIT10
+#define XHC0_FUNC_RESET BIT11
+#define XHC1_FUNC_RESET BIT12
+
+#define XHCI_ACPI_MMIO_AMD_REG00 0x00
+#define XHCI_ACPI_MMIO_AMD_REG04 0x04
+#define XHCI_ACPI_MMIO_AMD_REG08 0x08
+#define XHCI_ACPI_MMIO_AMD_REG10 0x10
+#define XHCI_ACPI_MMIO_AMD_REG14 0x14
+#define XHCI_ACPI_MMIO_AMD_REG20 0x20
+#define XHCI_ACPI_MMIO_AMD_REG24 0x24
+#define XHCI_ACPI_MMIO_AMD_REG28 0x28
+#define XHCI_ACPI_MMIO_AMD_REG30 0x30
+#define XHCI_ACPI_MMIO_AMD_REG40 0x40
+#define XHCI_ACPI_MMIO_AMD_REG48 0x48 // USB3.0_Ind_REG Index
+#define XHCI_ACPI_MMIO_AMD_REG4C 0x4C // USB2.0_Ind_REG Data
+#define XHCI_ACPI_MMIO_AMD_REG8C 0x8C
+#define XHCI_ACPI_MMIO_AMD_REG90 0x90 // adaptation timer settings
+#define XHCI_ACPI_MMIO_AMD_REG98 0x98
+#define XHCI_ACPI_MMIO_AMD_REGA0 0xA0 // BAR 0
+#define XHCI_ACPI_MMIO_AMD_REGA4 0xA4 // BAR 1
+#define XHCI_ACPI_MMIO_AMD_REGA8 0xA8 // BAR 2
+#define XHCI_ACPI_MMIO_AMD_REGB0 0xB0 // SPI_Valid_Base.
+#define XHCI_ACPI_MMIO_AMD_REGC0 0xC0 // Firmware starting offset for coping
+#define XHCI_ACPI_MMIO_AMD_REGB4 0xB4
+#define XHCI_ACPI_MMIO_AMD_REGD0 0xD0
+
+#define FCH_XHCI_REG48 0x48 // XHCI IND_REG Index registers
+#define FCH_XHCI_REG4C 0x4C // XHCI IND_REG Data registers
+
+#define FCH_XHCI_IND60_BASE 0x40000000ul //
+
+#define FCH_XHCI_IND60_REG00 FCH_XHCI_IND60_BASE + 0x00 //
+#define FCH_XHCI_IND60_REG04 FCH_XHCI_IND60_BASE + 0x04 //
+#define FCH_XHCI_IND60_REG08 FCH_XHCI_IND60_BASE + 0x08 //
+#define FCH_XHCI_IND60_REG0C FCH_XHCI_IND60_BASE + 0x0C //
+#define FCH_XHCI_IND60_REG18 FCH_XHCI_IND60_BASE + 0x18 //
+#define FCH_XHCI_IND60_REG48 FCH_XHCI_IND60_BASE + 0x48 //
+#define FCH_XHCI_IND60_REG50 FCH_XHCI_IND60_BASE + 0x50 //
+#define FCH_XHCI_IND60_REG54 FCH_XHCI_IND60_BASE + 0x54 //
+
+#define FCH_XHCI_IND_REG00 0x00 //
+#define FCH_XHCI_IND_REG04 0x04 //
+#define FCH_XHCI_IND_REG48 0x48 //
+#define FCH_XHCI_IND_REG54 0x54 //
+#define FCH_XHCI_IND_REG88 0x88 //
+#define FCH_XHCI_IND_REG94 0x94 // adaptation mode settings
+#define FCH_XHCI_IND_REG98 0x98 // CR phase and frequency filter settings
+#define FCH_XHCI_IND_REGC8 0xC8 //
+#define FCH_XHCI_IND_REGD4 0xD4 // adaptation mode settings
+#define FCH_XHCI_IND_REGD8 0xD8 // CR phase and frequency filter settings
+#define FCH_XHCI_IND_REG100 0x100 //
+#define FCH_XHCI_IND_REG120 0x120 //
+#define FCH_XHCI_IND_REG128 0x128 //
+#define MAX_XHCI_PORTS 0x04
+
+//SMBUS
+#define FCH_SMB_IOREG00 0x00 // SMBusStatus
+#define FCH_SMB_IOREG01 0x01 // SMBusSlaveStatus
+#define FCH_SMB_IOREG02 0x02 // SMBusControl
+#define FCH_SMB_IOREG03 0x03 // SMBusHostCmd
+#define FCH_SMB_IOREG04 0x04 // SMBusAddress
+#define FCH_SMB_IOREG05 0x05 // SMBusData0
+#define FCH_SMB_IOREG06 0x06 // SMBusData1
+#define FCH_SMB_IOREG07 0x07 // SMBusBlockData
+#define FCH_SMB_IOREG08 0x08 // SMBusSlaveControl
+#define FCH_SMB_IOREG14 0x14 // SMBusAutoPoll
+#define FCH_SMB_IOREG16 0x16 // SMBusPausePoll
+#define FCH_SMB_IOREG17 0x17 // SMBusHostCmd2
+
+#define FCH_SMB_CMD_QUICK 0x00 << 2 // Quick Read or Write
+#define FCH_SMB_CMD_BYTE 0x01 << 2 // Byte Read or Write
+#define FCH_SMB_CMD_BYTE_DATA 0x02 << 2 // Byte Data Read or Write
+#define FCH_SMB_CMD_WORD_DATA 0x03 << 2 // Word Data Read or Write
+#define FCH_SMB_CMD_BLOCK 0x05 << 2 // Block Read or Write
+
+#define FCH_SMB_ALL_HOST_STATUS 0x1f // HostBusy+SMBInterrupt+DeviceErr+BusCollision+Failed
+#define FCH_SMB_CMD_BYTE_DATA_START 0x48 // Byte Data Read or Write
+#define FCH_SMB_CMD_START BIT6
+#define FCH_SMB_READ_ENABLE BIT0
+#define FCH_SMB_AUTO_POLL_EN BIT0
+#define FCH_SMB_POLL2BYTE BIT7
+
+#define SBTSI_ADDR 0x98
+#define SBTSI_REG01 0x01
+#define SBTSI_REG09 0x09
+#define SBTSI_REG10 0x10
+#define SBTSI_READORDER BIT5
+
+#define FCH_EC_ENTER_CONFIG 0X5A
+#define FCH_EC_EXIT_CONFIG 0XA5
+#define FCH_EC_REG07 0X07
+#define FCH_EC_REG30 0X30
+#define FCH_EC_REG60 0X60
+#define FCH_EC_REG61 0X61
+
+#define FCH_IMC_ROMSIG 0x55aa55aaul
+
+#define SPI_HEAD_LENGTH 0x0E
+#define SPI_BAR0_VLD 0x01
+#define SPI_BASE0 (0x00 << 7)
+#define SPI_BAR1_VLD (0x01 << 8)
+#define SPI_BASE1 (SPI_HEAD_LENGTH << 10)
+#define SPI_BAR2_VLD (0x01 << 16)
+#define SPI_BASE2(x) ((SPI_HEAD_LENGTH + ACPIMMIO16(x)) << 18)
+
+#define FW_TO_SIGADDR_OFFSET 0x0C
+#define BCD_ADDR_OFFSET 0x02
+#define BCD_SIZE_OFFSET 0x04
+#define FW_ADDR_OFFSET 0x06
+#define FW_SIZE_OFFSET 0x08
+#define ACD_ADDR_OFFSET 0x0A
+#define ACD_SIZE_OFFSET 0x0C
+#define XHC_BOOT_RAM_SIZE 0x8000
+
+#define PKT_DATA_REG ACPI_MMIO_BASE + GFX_DAC_BASE + 0x00
+#define PKT_LEN_REG ACPI_MMIO_BASE + GFX_DAC_BASE + 0x14
+#define PKT_CTRL_REG ACPI_MMIO_BASE + GFX_DAC_BASE + 0x15
+#define EFUS_DAC_ADJUSTMENT_CONTROL 0x850A8ul
+#define BGADJ 0x1F
+#define DACADJ 0x1B
+#define EFUS_DAC_ADJUSTMENT_CONTROL_DATA (BGADJ + (DACADJ << 8) + BIT16 )
+
+#define KABINI_OSC_OUT_CLOCK_SEL_48MHz 0x02
+#define KABINI_OSC_OUT_CLOCK_SEL_25MHz 0x01
+
+#define RTC_WORKAROUND_SECOND 0x00
+#define RTC_VALID_SECOND_VALUE 0x59
+#define RTC_SECOND_RESET_VALUE 0x30
+#define RTC_SECOND_LOWER_NIBBLE 0x0F
+#define RTC_VALID_SECOND_VALUE_LN 0x09
+
+#ifndef FCH_DEADLOOP
+ #define FCH_DEADLOOP() { volatile UINTN __i; __i = 1; while (__i); }
+#endif
+
+#define OHCI_ARB_REGQ_VLD_EN BIT2
+
diff --git a/src/vendorcode/amd/pi/00630F01/Proc/Fch/FchPlatform.h b/src/vendorcode/amd/pi/00630F01/Proc/Fch/FchPlatform.h
new file mode 100644
index 0000000..3306fd5
--- /dev/null
+++ b/src/vendorcode/amd/pi/00630F01/Proc/Fch/FchPlatform.h
@@ -0,0 +1,118 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * FCH platform definition
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: FCH
+ * @e \$Revision: 281181 $ @e \$Date: 2013-12-18 02:18:55 -0600 (Wed, 18 Dec 2013) $
+ *
+ */
+/*
+*****************************************************************************
+*
+ * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+****************************************************************************
+*/
+#ifndef _FCH_PLATFORM_H_
+#define _FCH_PLATFORM_H_
+
+#define MAX_SATA_PORTS 8
+
+#include "AGESA.h"
+
+#ifndef FCHOEM_ACPI_RESTORE_SWSMI
+ #define FCHOEM_BEFORE_PCI_RESTORE_SWSMI 0xD3
+ #define FCHOEM_AFTER_PCI_RESTORE_SWSMI 0xD4
+ #define FCHOEM_ENABLE_ACPI_SWSMI 0xA0
+ #define FCHOEM_DISABLE_ACPI_SWSMI 0xA1
+ #define FCHOEM_START_TIMER_SMI 0xBC
+ #define FCHOEM_STOP_TIMER_SMI 0xBD
+#endif
+
+#ifndef FCHOEM_SPI_UNLOCK_SWSMI
+ #define FCHOEM_SPI_UNLOCK_SWSMI 0xAA
+#endif
+#ifndef FCHOEM_SPI_LOCK_SWSMI
+ #define FCHOEM_SPI_LOCK_SWSMI 0xAB
+#endif
+
+#ifndef FCHOEM_ACPI_TABLE_RANGE_LOW
+ #define FCHOEM_ACPI_TABLE_RANGE_LOW 0xE0000ul
+#endif
+
+#ifndef FCHOEM_ACPI_TABLE_RANGE_HIGH
+ #define FCHOEM_ACPI_TABLE_RANGE_HIGH 0xFFFF0ul
+#endif
+
+#ifndef FCHOEM_ACPI_BYTE_CHECHSUM
+ #define FCHOEM_ACPI_BYTE_CHECHSUM 0x100
+#endif
+
+#ifndef FCHOEM_IO_DELAY_PORT
+ #define FCHOEM_IO_DELAY_PORT 0x80
+#endif
+
+#ifndef FCHOEM_OUTPUT_DEBUG_PORT
+ #define FCHOEM_OUTPUT_DEBUG_PORT 0x80
+#endif
+
+#define FCH_PCIRST_BASE_IO 0xCF9
+#define FCH_PCI_RESET_COMMAND06 0x06
+#define FCH_PCI_RESET_COMMAND0E 0x0E
+#define FCH_KBDRST_BASE_IO 0x64
+#define FCH_KBC_RESET_COMMAND 0xFE
+#define FCH_ROMSIG_BASE_IO 0x20000l
+#define FCH_ROMSIG_SIGNATURE 0x55AA55AAul
+#define FCH_MAX_TIMER 0xFFFFFFFFul
+#define FCH_GEC_INTERNAL_REG 0x6804
+#define FCH_HPET_REG_MASK 0xFFFFF800ul
+#define FCH_FAKE_USB_BAR_ADDRESS 0x58830000ul
+
+
+#ifndef FCHOEM_ELAPSED_TIME_UNIT
+ #define FCHOEM_ELAPSED_TIME_UNIT 28
+#endif
+
+#ifndef FCHOEM_ELAPSED_TIME_DIVIDER
+ #define FCHOEM_ELAPSED_TIME_DIVIDER 100
+#endif
+
+#include "Fch.h"
+#include "amdlib.h"
+#include "FchCommonCfg.h"
+#include "AcpiLib.h"
+#include "FchDef.h"
+#include "FchBiosRamUsage.h"
+#include "AmdFch.h"
+
+extern BUILD_OPT_CFG UserOptions;
+
+#endif // _FCH_PLATFORM_H_
diff --git a/src/vendorcode/amd/pi/00630F01/Proc/IDS/Debug/IdsDebugPrint.h b/src/vendorcode/amd/pi/00630F01/Proc/IDS/Debug/IdsDebugPrint.h
new file mode 100644
index 0000000..352e709
--- /dev/null
+++ b/src/vendorcode/amd/pi/00630F01/Proc/IDS/Debug/IdsDebugPrint.h
@@ -0,0 +1,80 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD Integrated Debug Print Routines
+ *
+ * Contains all functions related to IDS Debug Print
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: IDS
+ * @e \$Revision: 281181 $ @e \$Date: 2013-12-18 02:18:55 -0600 (Wed, 18 Dec 2013) $
+ */
+/*****************************************************************************
+ *
+ * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ***************************************************************************/
+
+#ifndef _IDS_DEBUGPRINT_H_
+#define _IDS_DEBUGPRINT_H_
+
+///Debug String End flag
+#define DEBUG_STRING_END_FLAG (0x0)
+/// return status for debug print
+typedef enum {
+ IDS_DEBUG_PRINT_SUCCESS = 0, ///< success
+ IDS_DEBUG_PRINT_BUFFER_OVERFLOW, ///< Bufer overflow
+} IDS_DEBUG_PRINT_STATUS;
+
+/// Private datas for debug print
+typedef struct _IDS_DEBUG_PRINT_PRIVATE_DATA {
+ BOOLEAN saveContext; /// save context
+} IDS_DEBUG_PRINT_PRIVATE_DATA;
+
+typedef BOOLEAN (*PF_IDS_DEBUG_PRINT_SUPPORT) (VOID);
+typedef BOOLEAN (*PF_IDS_DEBUG_PRINT_FILTER) (UINT64 *Filter);
+typedef VOID (*PF_IDS_DEBUG_PRINT_PRINT) (CHAR8 *Buffer, UINTN BufferSize, IDS_DEBUG_PRINT_PRIVATE_DATA *debugPrintPrivate);
+typedef VOID (*PF_IDS_DEBUG_INIT_PRIVATE_DATA) (UINT64 flag, IDS_DEBUG_PRINT_PRIVATE_DATA *debugPrintPrivate);
+
+/// Debug print Hw layer service class
+typedef struct _IDS_DEBUG_PRINT {
+ PF_IDS_DEBUG_PRINT_SUPPORT support; ///Check if support
+ PF_IDS_DEBUG_PRINT_FILTER customfilter; ///Get if any customize filters
+ PF_IDS_DEBUG_INIT_PRIVATE_DATA InitPrivateData; ///Init private data
+ PF_IDS_DEBUG_PRINT_PRINT print; ///Print data to Hw layer
+} IDS_DEBUG_PRINT;
+
+
+VOID
+GetDebugPrintList (
+ IN OUT CONST IDS_DEBUG_PRINT ***pIdsDebugPrintListPtr
+ );
+
+
+#endif //_IDS_DEBUGPRINT_H_
+
diff --git a/src/vendorcode/amd/pi/00630F01/Proc/IDS/Debug/IdsDpHdtout.h b/src/vendorcode/amd/pi/00630F01/Proc/IDS/Debug/IdsDpHdtout.h
new file mode 100644
index 0000000..982f513
--- /dev/null
+++ b/src/vendorcode/amd/pi/00630F01/Proc/IDS/Debug/IdsDpHdtout.h
@@ -0,0 +1,119 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD Integrated Debug Debug_library Routines
+ *
+ * Contains all functions related to HDTOUT
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: IDS
+ * @e \$Revision: 281181 $ @e \$Date: 2013-12-18 02:18:55 -0600 (Wed, 18 Dec 2013) $
+ */
+/*****************************************************************************
+ *
+ * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ***************************************************************************/
+
+#ifndef _IDS_HDTOUT_H_
+#define _IDS_HDTOUT_H_
+
+#define HDTOUT_VERSION 0x0200
+
+/// HDTOUT command
+#define HDTOUT_COMMAND 0x99cc
+#define HDTOUT_INIT (0x10BF0000ul | HDTOUT_COMMAND)
+#define HDTOUT_ASSERT (0xA0BF0000ul | HDTOUT_COMMAND)
+#define HDTOUT_EXIT (0xE0BF0000ul | HDTOUT_COMMAND)
+#define HDTOUT_PRINT (0xC0BF0000ul | HDTOUT_COMMAND)
+#define HDTOUT_TIME_ANALYSE (0xD0BF0000ul | HDTOUT_COMMAND)
+#define HDTOUT_BREAKPOINT (0xB0BF0000ul | HDTOUT_COMMAND)
+#define HDTOUT_ERROR (0x1EBF0000ul | HDTOUT_COMMAND)
+
+
+#define HDTOUT_ERROR_HEAP_ALLOCATION 0x1
+#define HDTOUT_ERROR_HEAP_AllOCATE_FAIL 0x2
+
+#define HDTOUT_PRINTCTRL_OFF 0
+#define HDTOUT_PRINTCTRL_ON 1
+#define HDTOUT_ALL_CORES 0
+#define HDTOUT_BSP_ONLY 1
+#define HDTOUT_BUFFER_MODE_OFF 0
+#define HDTOUT_BUFFER_MODE_ON 1
+
+#define HDTOUT_HEADER_SIGNATURE 0xDB1099CCul
+#define HDTOUT_DEFAULT_BUFFER_SIZE 0x1000
+/// HDTOUT Header.
+typedef struct _HDTOUT_HEADER {
+ UINT32 Signature; ///< 0xDB1099CC
+ UINT16 Version; ///< HDTOUT version.
+ UINT16 BufferSize; ///< Size in bytes.
+ UINT16 DataIndex; ///< Data Index.
+ UINT8 PrintCtrl; ///< 0 off no print 1 on print
+ UINT8 NumBreakpointUnit; ///< default 0 no bp unit others number of bp unit
+ UINT32 FuncListAddr; ///< 32 bit address to the list of functions that script can execute
+ UINT8 ConsoleType; ///< Console type - deprecated
+ UINT8 Event; ///< Event type. - deprecated
+ UINT8 OutBufferMode; ///< Off:stack mode, On: heap mode - deprecated
+ UINT32 EnableMask; ///< Bitmap to select which part should be streamed out
+ UINT64 ConsoleFilter; ///< Filter use to select which part should be streamed out
+ UINT8 BspOnlyFlag; ///< 1 Only Enable Bsp output, 0 enable On All cores
+ UINT8 Reserved[56 - 32]; ///< Reserved for header expansion
+
+ CHAR8 BreakpointList[300]; ///< Breakpoint list
+ CHAR8 StatusStr[156]; ///< Shows current node, DCT, CS,...
+ CHAR8 Data[2]; ///< HDTOUT content. Its size will be determined by BufferSize.
+} HDTOUT_HEADER;
+
+#define IDS_HDTOUT_BP_AND_OFF 0
+#define IDS_HDTOUT_BP_AND_ON 1
+
+#define IDS_HDTOUT_BPFLAG_FORMAT_STR 0
+#define IDS_HDTOUT_BPFLAG_STATUS_STR 1
+
+#define HDTOUT_BP_ACTION_HALT 1
+#define HDTOUT_BP_ACTION_PRINTON 2
+#define HDTOUT_BP_ACTION_PRINTONE 3
+#define HDTOUT_BP_ACTION_PRINTOFF 4
+
+///breakpoint unit of HDTOUT
+typedef struct _BREAKPOINT_UNIT {
+ UINT8 AndFlag : 1; ///< Next string is ANDed to current string
+ UINT8 BpFlag : 1; ///< Format string or Status string
+ UINT8 Action : 4; ///< Halt, start HDTOUT, or stop HDT,...
+ UINT8 BpStrOffset; ///< Offset from BreakpointList to the breakpoint string
+} BREAKPOINT_UNIT;
+
+
+BOOLEAN
+AmdIdsHdtOutSupport (
+ VOID
+ );
+
+#endif //_IDS_HDTOUT_H_
+
diff --git a/src/vendorcode/amd/pi/00630F01/Proc/IDS/Debug/IdsDpRam.h b/src/vendorcode/amd/pi/00630F01/Proc/IDS/Debug/IdsDpRam.h
new file mode 100644
index 0000000..cec4527
--- /dev/null
+++ b/src/vendorcode/amd/pi/00630F01/Proc/IDS/Debug/IdsDpRam.h
@@ -0,0 +1,73 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD Integrated Debug Print Routines
+ *
+ * Contains all functions related to IDS Debug Print
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: IDS
+ * @e \$Revision: 281181 $ @e \$Date: 2013-12-18 02:18:55 -0600 (Wed, 18 Dec 2013) $
+ */
+/*****************************************************************************
+ *
+ * Copyright (c) 2008 - 2014, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ***************************************************************************/
+
+#ifndef _IDS_DP_RAM_H_
+#define _IDS_DP_RAM_H_
+
+#pragma pack (push, 1)
+
+///Debug Print RAM signature
+#define DEBUG_PRINT_RAM_SIG MAKE_SIGNATURE ('D','P','R','M')
+
+/// Debug Print Ram Header
+typedef struct _IDS_DEBUG_PRINT_RAM_HEADER {
+ SIGNATURE DpRamSig; /// 00 'D','P','R','M'
+ UINT32 LatestIdx; /// 04 Latest Index
+ UINT8 Reserved[8]; /// Reserved
+} IDS_DEBUG_PRINT_RAM_HEADER;
+
+///Debug Print RAM Signature Offset
+#define DEBUG_PRINT_RAM_SIG_ADDR ((UINTN) IDS_DPRAM_BASE + (UINTN) &(((IDS_DEBUG_PRINT_RAM_HEADER *) 0)->DpRamSig))
+///Debug Print RAM Latest Index Offset
+#define DEBUG_PRINT_RAM_LATESTIDX_ADDR ((UINTN) IDS_DPRAM_BASE + (UINTN) &(((IDS_DEBUG_PRINT_RAM_HEADER *) 0)->LatestIdx))
+
+///Print Buffer start
+#define DEBUG_PRINT_BUFFER_START ((UINTN) IDS_DPRAM_BASE + sizeof (IDS_DEBUG_PRINT_RAM_HEADER))
+///Print Buffer Size
+#define DEBUG_PRINT_BUFFER_SIZE ((UINT32) IDS_DPRAM_SIZE - sizeof (IDS_DEBUG_PRINT_RAM_HEADER))
+///Debug Print RAM default Value
+#define DEBUG_PRINT_BUFFER_DFT_VALUE ((UINT8) 0xCC)
+
+#pragma pack (pop)
+
+#endif //_IDS_DP_RAM_H_
+
diff --git a/src/vendorcode/amd/pi/00630F01/Proc/IDS/Family/0x15/IdsF15AllService.h b/src/vendorcode/amd/pi/00630F01/Proc/IDS/Family/0x15/IdsF15AllService.h
new file mode 100644
index 0000000..8f0aa65
--- /dev/null
+++ b/src/vendorcode/amd/pi/00630F01/Proc/IDS/Family/0x15/IdsF15AllService.h
@@ -0,0 +1,49 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD IDS Routines
+ *
+ * Contains AMD AGESA IDS Translation
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: IDS
+ * @e \$Revision: 281181 $ @e \$Date: 2013-12-18 02:18:55 -0600 (Wed, 18 Dec 2013) $
+ */
+/*****************************************************************************
+ *
+ * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ***************************************************************************/
+#ifndef _IDS_F15_ALLSERVICE_H_
+#define _IDS_F15_ALLSERVICE_H_
+#ifdef __IDS_EXTENDED__
+ #include IDS_EXT_INCLUDE_F15 (IdsIntF15AllService)
+#endif
+
+#endif
+
diff --git a/src/vendorcode/amd/pi/00630F01/Proc/IDS/Family/0x15/KV/IdsF15KvAllService.h b/src/vendorcode/amd/pi/00630F01/Proc/IDS/Family/0x15/KV/IdsF15KvAllService.h
new file mode 100644
index 0000000..1d7a680
--- /dev/null
+++ b/src/vendorcode/amd/pi/00630F01/Proc/IDS/Family/0x15/KV/IdsF15KvAllService.h
@@ -0,0 +1,49 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD IDS Routines
+ *
+ * Contains AMD AGESA IDS Translation
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: IDS
+ * @e \$Revision: 281181 $ @e \$Date: 2013-12-18 02:18:55 -0600 (Wed, 18 Dec 2013) $
+ */
+/*****************************************************************************
+ *
+ * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ***************************************************************************/
+ #ifndef _IDS_F15_KV_ALLSERVICE_H_
+#define _IDS_F15_KV_ALLSERVICE_H_
+#ifdef __IDS_EXTENDED__
+ #include IDS_EXT_INCLUDE_F15_KV (IdsIntF15KvAllService)
+#endif
+
+#endif //_IDS_F15_KV_ALLSERVICE_H_
+
diff --git a/src/vendorcode/amd/pi/00630F01/Proc/IDS/Family/0x15/KV/IdsF15KvNvDef.h b/src/vendorcode/amd/pi/00630F01/Proc/IDS/Family/0x15/KV/IdsF15KvNvDef.h
new file mode 100644
index 0000000..b10c1c3
--- /dev/null
+++ b/src/vendorcode/amd/pi/00630F01/Proc/IDS/Family/0x15/KV/IdsF15KvNvDef.h
@@ -0,0 +1,287 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * IDS NV definition for F15Kv
+ *
+ * Auto generated from CBS XML file
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: IDS F15Kv
+ * @e \$Revision: 281181 $ @e \$Date: 2013-12-18 02:18:55 -0600 (Wed, 18 Dec 2013) $
+ */
+/*****************************************************************************
+ *
+ * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ***************************************************************************/
+
+
+#ifndef _IDSF15KVNVDEF_H_
+#define _IDSF15KVNVDEF_H_
+///HTC Enable
+///Enable or disable Hardware Thermal Control. D18F3x64[0]
+typedef enum {
+ IdsNvThermalHTCEnDisabled = 0,///<Disabled
+ IdsNvThermalHTCEnEnabled = 1,///<Enabled
+ IdsNvThermalHTCEnAuto = 3,///<Auto
+} IdsNvThermalHTCEn;
+
+///HTC Override
+///Enable or disable Thermal Control Override
+typedef enum {
+ IdsNvThermalHTCOverrideDisabled = 0,///<Disabled
+ IdsNvThermalHTCOverrideEnabled = 1,///<Enabled
+} IdsNvThermalHTCOverride;
+
+///HTC P-state limit select
+///Specifies the P-state limit of all cores when in the P-state based HTC-active state
+#define IdsNvThermalHtcPstateLimitMin 0
+#define IdsNvThermalHtcPstateLimitMax 7
+
+///HTC Temperature Hysteresis
+///Sets the temperature hysteresis for HTC. D18F3x64[27:24]
+#define IdsNvThermalHTCTempHysMin 0
+#define IdsNvThermalHTCTempHysMax 0xF
+
+///HTC Activation Temp
+///Sets the HTC temperature limit. D18F3x64[22:16]
+#define IdsNvThermalHTCActTempMin 0
+#define IdsNvThermalHTCActTempMax 0x7F
+
+///Bank Interleave
+///Interleave memory blocks across the DRAM chip selects for node 0.
+typedef enum {
+ IdsNvMemMappingBankInterleaveDisabled = 0,///<Disabled
+ IdsNvMemMappingBankInterleaveAuto = 1,///<Auto
+} IdsNvMemMappingBankInterleave;
+
+///DRAM Channel Interleave
+///Interleave between two DCTs when they are in unganged mode.
+typedef enum {
+ IdsNvMemMappingChlInterleaveAddress_bit_6 = 0,///<Address bit 6
+ IdsNvMemMappingChlInterleaveAddress_bit_12 = 1,///<Address bit 12
+ IdsNvMemMappingChlInterleaveHash__exclusive_OR_of_address_bits_20_16__6_ = 2,///<Hash: exclusive OR of address bits[20:16, 6]
+ IdsNvMemMappingChlInterleaveHash__excluseive_OR_of_address_bits_20_16__9_ = 3,///<Hash: excluseive OR of address bits[20:16, 9]
+ IdsNvMemMappingChlInterleaveAddress_bit_8 = 4,///<Address bit 8
+ IdsNvMemMappingChlInterleaveAddress_bit_9 = 5,///<Address bit 9
+ IdsNvMemMappingChlInterleaveDisabled = 0xF,///<Disabled
+ IdsNvMemMappingChlInterleaveAuto = 0xFF,///<Auto
+} IdsNvMemMappingChlInterleave;
+
+///ECC Symbol Size
+///ECC symbol size and code selection. D18F3x180[25]
+typedef enum {
+ IdsNvEccSymbolSizex4 = 0,///<x4
+ IdsNvEccSymbolSizex8 = 1,///<x8
+ IdsNvEccSymbolSizeAuto = 3,///<Auto
+} IdsNvEccSymbolSize;
+
+///DRAM prefetches triggered from CPU requests
+///Enable or disable DRAM prefetches Prefetch triggered by CPU requests.
+typedef enum {
+ IdsNvPrefetchPrefCpuDis0 = 0,///<0
+ IdsNvPrefetchPrefCpuDis1 = 1,///<1
+ IdsNvPrefetchPrefCpuDisAuto = 3,///<Auto
+} IdsNvPrefetchPrefCpuDis;
+
+///HW prefetch training on SW Prefetches
+///Enable or disable Hardware Prefetch training on Software Prefetches
+typedef enum {
+ IdsNvPrefetchDisHWPFforSWPF0 = 0,///<0
+ IdsNvPrefetchDisHWPFforSWPF1 = 1,///<1
+ IdsNvPrefetchDisHWPFforSWPFAuto = 3,///<Auto
+} IdsNvPrefetchDisHWPFforSWPF;
+
+///Hardware Prefetches
+///Enable or disable Hardware Prefetches.
+typedef enum {
+ IdsNvPrefetchDisHWPF0 = 0,///<0
+ IdsNvPrefetchDisHWPF1 = 1,///<1
+ IdsNvPrefetchDisHWPFAuto = 3,///<Auto
+} IdsNvPrefetchDisHWPF;
+
+///UMI Gen2
+///Enable or disable UMI link Gen2
+typedef enum {
+ IdsNvFchGppUmiGen2Disabled = 0,///<Disabled
+ IdsNvFchGppUmiGen2Enabled = 1,///<Enabled
+} IdsNvFchGppUmiGen2;
+
+///SATA Controller
+///Disable or enable OnChip SATA controller
+typedef enum {
+ IdsNvFchSataEnableDisabled = 0,///<Disabled
+ IdsNvFchSataEnableEnabled = 1,///<Enabled
+} IdsNvFchSataEnable;
+
+///SATA Mode
+///Select OnChip SATA Type
+typedef enum {
+ IdsNvFchSataClassNative_IDE = 0,///<Native IDE
+ IdsNvFchSataClassRAID = 1,///<RAID
+ IdsNvFchSataClassAHCI = 3,///<AHCI
+ IdsNvFchSataClassLegacy_IDE = 3,///<Legacy IDE
+ IdsNvFchSataClassIDE__AHCI = 4,///<IDE->AHCI
+ IdsNvFchSataClassAHCI_as_ID_0x7804 = 5,///<AHCI as ID 0x7804
+ IdsNvFchSataClassIDE__AHCI_as_ID_0x7804 = 6,///<IDE->AHCI as ID 0x7804
+} IdsNvFchSataClass;
+
+///OnChip IDE
+///Select OnChip IDE controller mode
+typedef enum {
+ IdsNvFchSataIdeModeLegacy_IDE = 0,///<Legacy IDE
+ IdsNvFchSataIdeModeNative_IDE = 1,///<Native IDE
+} IdsNvFchSataIdeMode;
+
+///IDE Controller
+///Disable or enable OnChip IDE controller
+typedef enum {
+ IdsNvFchSataIdeEnableDisabled = 0,///<Disabled
+ IdsNvFchSataIdeEnableEnabled = 1,///<Enabled
+} IdsNvFchSataIdeEnable;
+
+///XHC Switch (Bus 0 Dev 16 Fn 0/1)
+///Select disable or enable XHCI HCs (Bus 0 Dev 16 Fn 0/1)
+typedef enum {
+ IdsNvFchUsbXhciSwitchDisabled = 0,///<Disabled
+ IdsNvFchUsbXhciSwitchEnabled = 1,///<Enabled
+} IdsNvFchUsbXhciSwitch;
+
+///USB1(Bus 0 Dev 18 Fn 0/2)
+///Select disable or enable USB1 HCs (Bus 0 Dev 18 Fn 0/2)
+typedef enum {
+ IdsNvFchUsbOhci1EnableDisabled = 0,///<Disabled
+ IdsNvFchUsbOhci1EnableEnabled = 1,///<Enabled
+} IdsNvFchUsbOhci1Enable;
+
+///USB2 (Bus 0 Dev 19 Fn 0/2)
+///Select disable or enable USB2 HCs (Bus 0 Dev 19 Fn 0/2)
+typedef enum {
+ IdsNvFchUsbOhci2EnableDisabled = 0,///<Disabled
+ IdsNvFchUsbOhci2EnableEnabled = 1,///<Enabled
+} IdsNvFchUsbOhci2Enable;
+
+///USB3 (Bus 0 Dev 22 Fn 0/2)
+///Select disable or enable USB3 HCs (Bus 0 Dev 22 Fn 0/2)
+typedef enum {
+ IdsNvFchUsbOhci3EnableDisabled = 0,///<Disabled
+ IdsNvFchUsbOhci3EnableEnabled = 1,///<Enabled
+} IdsNvFchUsbOhci3Enable;
+
+///USB4 (Bus 0 Dev 20 Fn 5)
+///Select disable or enable USB4 HC (Bus 0 Dev 20 Fn 5)
+typedef enum {
+ IdsNvFchUsbOhci4EnableDisabled = 0,///<Disabled
+ IdsNvFchUsbOhci4EnableEnabled = 1,///<Enabled
+} IdsNvFchUsbOhci4Enable;
+
+///Hardware Monitor Enable
+///Master switch to enable or disable hardware monitor function
+typedef enum {
+ IdsNvFchHwmEnableDisabled = 0,///<Disabled
+ IdsNvFchHwmEnableEnabled = 1,///<Enabled
+} IdsNvFchHwmEnable;
+
+///In-Chip IR
+///Enable or disable the In-Chip IR
+typedef enum {
+ IdsNvFchIrConfigDisabled = 0,///<Disabled
+ IdsNvFchIrConfigRX_TX0_Only = 1,///<RX_TX0 Only
+ IdsNvFchIrConfigRX_TX1_Only = 2,///<RX_TX1 Only
+ IdsNvFchIrConfigRX__TX0__and_TX1 = 3,///<RX, TX0, and TX1
+} IdsNvFchIrConfig;
+
+///SD Configuration Mode
+///Select SD Mode
+typedef enum {
+ IdsNvFchSdConfigDisabled = 0,///<Disabled
+ IdsNvFchSdConfigADMA = 1,///<ADMA
+ IdsNvFchSdConfigDMA = 2,///<DMA
+ IdsNvFchSdConfigPIO = 3,///<PIO
+} IdsNvFchSdConfig;
+
+///Azalia Device
+///Select disable or enable Azalia Device
+typedef enum {
+ IdsNvFchAzaliaControlAuto = 0,///<Auto
+ IdsNvFchAzaliaControlDisabled = 1,///<Disabled
+ IdsNvFchAzaliaControlEnabled = 2,///<Enabled
+ IdsNvFchAzaliaControlReserved = 3,///<Reserved
+} IdsNvFchAzaliaControl;
+
+///Integrated Graphics Controller
+///Enable Integrate Graphics controller
+typedef enum {
+ IdsNvGnbGfxiGPU_CONTROLAuto = 0,///<Auto
+ IdsNvGnbGfxiGPU_CONTROLDisabled = 1,///<Disabled
+ IdsNvGnbGfxiGPU_CONTROLForces = 2,///<Forces
+} IdsNvGnbGfxiGPU_CONTROL;
+
+///UMA Frame buffer Size
+///Set UMA FB size
+typedef enum {
+ IdsNvGnbGfxUmaFrameBufferSizeAuto = 0,///<Auto
+ IdsNvGnbGfxUmaFrameBufferSize32M = 1,///<32M
+ IdsNvGnbGfxUmaFrameBufferSize64M = 2,///<64M
+ IdsNvGnbGfxUmaFrameBufferSize128M = 3,///<128M
+ IdsNvGnbGfxUmaFrameBufferSize256M = 4,///<256M
+ IdsNvGnbGfxUmaFrameBufferSize384M = 5,///<384M
+ IdsNvGnbGfxUmaFrameBufferSize512M = 6,///<512M
+ IdsNvGnbGfxUmaFrameBufferSize1G = 7,///<1G
+ IdsNvGnbGfxUmaFrameBufferSize2G = 8,///<2G
+ IdsNvGnbGfxUmaFrameBufferSize4G = 9,///<4G
+} IdsNvGnbGfxUmaFrameBufferSize;
+
+///NB Azalia
+///Enable Integrate HD Audio controller
+typedef enum {
+ IdsNvGnbGfxNbAzaliaDisabled = 0,///<Disabled
+ IdsNvGnbGfxNbAzaliaEnabled = 1,///<Enabled
+ IdsNvGnbGfxNbAzaliaAuto = 0xf,///<Auto
+} IdsNvGnbGfxNbAzalia;
+
+///PSPP Policy
+///PCIe speed power policy
+typedef enum {
+ IdsNvGnbPciePsppPolicyDisabled = 0,///<Disabled
+ IdsNvGnbPciePsppPolicyPerformance = 1,///<Performance
+ IdsNvGnbPciePsppPolicyBalanced_High = 2,///<Balanced-High
+ IdsNvGnbPciePsppPolicyBalanced_Low = 3,///<Balanced-Low
+ IdsNvGnbPciePsppPolicyPower_Saving = 4,///<Power Saving
+ IdsNvGnbPciePsppPolicyAuto = 5,///<Auto
+} IdsNvGnbPciePsppPolicy;
+
+///IOMMU
+///
+typedef enum {
+ IdsNvGnbNbIOMMUDisabled = 0,///<Disabled
+ IdsNvGnbNbIOMMUEnabled = 1,///<Enabled
+} IdsNvGnbNbIOMMU;
+
+#endif // _IDSF15KVNVDEF_H_
+
diff --git a/src/vendorcode/amd/pi/00630F01/Proc/IDS/Family/0x15/TN/IdsF15TnAllService.h b/src/vendorcode/amd/pi/00630F01/Proc/IDS/Family/0x15/TN/IdsF15TnAllService.h
new file mode 100644
index 0000000..9e99f32
--- /dev/null
+++ b/src/vendorcode/amd/pi/00630F01/Proc/IDS/Family/0x15/TN/IdsF15TnAllService.h
@@ -0,0 +1,49 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD IDS Routines
+ *
+ * Contains AMD AGESA IDS Translation
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: IDS
+ * @e \$Revision: 281181 $ @e \$Date: 2013-12-18 02:18:55 -0600 (Wed, 18 Dec 2013) $
+ */
+/*****************************************************************************
+ *
+ * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ***************************************************************************/
+#ifndef _IDS_F15_TN_ALLSERVICE_H_
+#define _IDS_F15_TN_ALLSERVICE_H_
+#ifdef __IDS_EXTENDED__
+ #include IDS_EXT_INCLUDE_F15_TN (IdsIntF15TnAllService)
+#endif
+
+#endif //_IDS_F15_TN_ALLSERVICE_H_
+
diff --git a/src/vendorcode/amd/pi/00630F01/Proc/IDS/Family/0x15/TN/IdsF15TnNvDef.h b/src/vendorcode/amd/pi/00630F01/Proc/IDS/Family/0x15/TN/IdsF15TnNvDef.h
new file mode 100644
index 0000000..bdc7ac1
--- /dev/null
+++ b/src/vendorcode/amd/pi/00630F01/Proc/IDS/Family/0x15/TN/IdsF15TnNvDef.h
@@ -0,0 +1,287 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * IDS NV definition for F15Tn
+ *
+ * Auto generated from CBS XML file
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: IDS F15Tn
+ * @e \$Revision: 281181 $ @e \$Date: 2013-12-18 02:18:55 -0600 (Wed, 18 Dec 2013) $
+ */
+/*****************************************************************************
+ *
+ * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ***************************************************************************/
+
+
+#ifndef _IDSF15TNNVDEF_H_
+#define _IDSF15TNNVDEF_H_
+///HTC Enable
+///Enable or disable Hardware Thermal Control. D18F3x64[0]
+typedef enum {
+ IdsNvThermalHTCEnDisabled = 0,///<Disabled
+ IdsNvThermalHTCEnEnabled = 1,///<Enabled
+ IdsNvThermalHTCEnAuto = 3,///<Auto
+} IdsNvThermalHTCEn;
+
+///HTC Override
+///Enable or disable Thermal Control Override
+typedef enum {
+ IdsNvThermalHTCOverrideDisabled = 0,///<Disabled
+ IdsNvThermalHTCOverrideEnabled = 1,///<Enabled
+} IdsNvThermalHTCOverride;
+
+///HTC P-state limit select
+///Specifies the P-state limit of all cores when in the P-state based HTC-active state
+#define IdsNvThermalHtcPstateLimitMin 0
+#define IdsNvThermalHtcPstateLimitMax 7
+
+///HTC Temperature Hysteresis
+///Sets the temperature hysteresis for HTC. D18F3x64[27:24]
+#define IdsNvThermalHTCTempHysMin 0
+#define IdsNvThermalHTCTempHysMax 0xF
+
+///HTC Activation Temp
+///Sets the HTC temperature limit. D18F3x64[22:16]
+#define IdsNvThermalHTCActTempMin 0
+#define IdsNvThermalHTCActTempMax 0x7F
+
+///Bank Interleave
+///Interleave memory blocks across the DRAM chip selects for node 0.
+typedef enum {
+ IdsNvMemMappingBankInterleaveDisabled = 0,///<Disabled
+ IdsNvMemMappingBankInterleaveAuto = 1,///<Auto
+} IdsNvMemMappingBankInterleave;
+
+///DRAM Channel Interleave
+///Interleave between two DCTs when they are in unganged mode.
+typedef enum {
+ IdsNvMemMappingChlInterleaveAddress_bit_6 = 0,///<Address bit 6
+ IdsNvMemMappingChlInterleaveAddress_bit_12 = 1,///<Address bit 12
+ IdsNvMemMappingChlInterleaveHash__exclusive_OR_of_address_bits_20_16__6_ = 2,///<Hash: exclusive OR of address bits[20:16, 6]
+ IdsNvMemMappingChlInterleaveHash__excluseive_OR_of_address_bits_20_16__9_ = 3,///<Hash: excluseive OR of address bits[20:16, 9]
+ IdsNvMemMappingChlInterleaveAddress_bit_8 = 4,///<Address bit 8
+ IdsNvMemMappingChlInterleaveAddress_bit_9 = 5,///<Address bit 9
+ IdsNvMemMappingChlInterleaveDisabled = 0xF,///<Disabled
+ IdsNvMemMappingChlInterleaveAuto = 0xFF,///<Auto
+} IdsNvMemMappingChlInterleave;
+
+///ECC Symbol Size
+///ECC symbol size and code selection. D18F3x180[25]
+typedef enum {
+ IdsNvEccSymbolSizex4 = 0,///<x4
+ IdsNvEccSymbolSizex8 = 1,///<x8
+ IdsNvEccSymbolSizeAuto = 3,///<Auto
+} IdsNvEccSymbolSize;
+
+///DRAM prefetches triggered from CPU requests
+///Enable or disable DRAM prefetches Prefetch triggered by CPU requests.
+typedef enum {
+ IdsNvPrefetchPrefCpuDis0 = 0,///<0
+ IdsNvPrefetchPrefCpuDis1 = 1,///<1
+ IdsNvPrefetchPrefCpuDisAuto = 3,///<Auto
+} IdsNvPrefetchPrefCpuDis;
+
+///HW prefetch training on SW Prefetches
+///Enable or disable Hardware Prefetch training on Software Prefetches
+typedef enum {
+ IdsNvPrefetchDisHWPFforSWPF0 = 0,///<0
+ IdsNvPrefetchDisHWPFforSWPF1 = 1,///<1
+ IdsNvPrefetchDisHWPFforSWPFAuto = 3,///<Auto
+} IdsNvPrefetchDisHWPFforSWPF;
+
+///Hardware Prefetches
+///Enable or disable Hardware Prefetches.
+typedef enum {
+ IdsNvPrefetchDisHWPF0 = 0,///<0
+ IdsNvPrefetchDisHWPF1 = 1,///<1
+ IdsNvPrefetchDisHWPFAuto = 3,///<Auto
+} IdsNvPrefetchDisHWPF;
+
+///UMI Gen2
+///Enable or disable UMI link Gen2
+typedef enum {
+ IdsNvFchGppUmiGen2Disabled = 0,///<Disabled
+ IdsNvFchGppUmiGen2Enabled = 1,///<Enabled
+} IdsNvFchGppUmiGen2;
+
+///SATA Controller
+///Disable or enable OnChip SATA controller
+typedef enum {
+ IdsNvFchSataEnableDisabled = 0,///<Disabled
+ IdsNvFchSataEnableEnabled = 1,///<Enabled
+} IdsNvFchSataEnable;
+
+///SATA Mode
+///Select OnChip SATA Type
+typedef enum {
+ IdsNvFchSataClassNative_IDE = 0,///<Native IDE
+ IdsNvFchSataClassRAID = 1,///<RAID
+ IdsNvFchSataClassAHCI = 3,///<AHCI
+ IdsNvFchSataClassLegacy_IDE = 3,///<Legacy IDE
+ IdsNvFchSataClassIDE__AHCI = 4,///<IDE->AHCI
+ IdsNvFchSataClassAHCI_as_ID_0x7804 = 5,///<AHCI as ID 0x7804
+ IdsNvFchSataClassIDE__AHCI_as_ID_0x7804 = 6,///<IDE->AHCI as ID 0x7804
+} IdsNvFchSataClass;
+
+///OnChip IDE
+///Select OnChip IDE controller mode
+typedef enum {
+ IdsNvFchSataIdeModeLegacy_IDE = 0,///<Legacy IDE
+ IdsNvFchSataIdeModeNative_IDE = 1,///<Native IDE
+} IdsNvFchSataIdeMode;
+
+///IDE Controller
+///Disable or enable OnChip IDE controller
+typedef enum {
+ IdsNvFchSataIdeEnableDisabled = 0,///<Disabled
+ IdsNvFchSataIdeEnableEnabled = 1,///<Enabled
+} IdsNvFchSataIdeEnable;
+
+///XHC Switch (Bus 0 Dev 16 Fn 0/1)
+///Select disable or enable XHCI HCs (Bus 0 Dev 16 Fn 0/1)
+typedef enum {
+ IdsNvFchUsbXhciSwitchDisabled = 0,///<Disabled
+ IdsNvFchUsbXhciSwitchEnabled = 1,///<Enabled
+} IdsNvFchUsbXhciSwitch;
+
+///USB1(Bus 0 Dev 18 Fn 0/2)
+///Select disable or enable USB1 HCs (Bus 0 Dev 18 Fn 0/2)
+typedef enum {
+ IdsNvFchUsbOhci1EnableDisabled = 0,///<Disabled
+ IdsNvFchUsbOhci1EnableEnabled = 1,///<Enabled
+} IdsNvFchUsbOhci1Enable;
+
+///USB2 (Bus 0 Dev 19 Fn 0/2)
+///Select disable or enable USB2 HCs (Bus 0 Dev 19 Fn 0/2)
+typedef enum {
+ IdsNvFchUsbOhci2EnableDisabled = 0,///<Disabled
+ IdsNvFchUsbOhci2EnableEnabled = 1,///<Enabled
+} IdsNvFchUsbOhci2Enable;
+
+///USB3 (Bus 0 Dev 22 Fn 0/2)
+///Select disable or enable USB3 HCs (Bus 0 Dev 22 Fn 0/2)
+typedef enum {
+ IdsNvFchUsbOhci3EnableDisabled = 0,///<Disabled
+ IdsNvFchUsbOhci3EnableEnabled = 1,///<Enabled
+} IdsNvFchUsbOhci3Enable;
+
+///USB4 (Bus 0 Dev 20 Fn 5)
+///Select disable or enable USB4 HC (Bus 0 Dev 20 Fn 5)
+typedef enum {
+ IdsNvFchUsbOhci4EnableDisabled = 0,///<Disabled
+ IdsNvFchUsbOhci4EnableEnabled = 1,///<Enabled
+} IdsNvFchUsbOhci4Enable;
+
+///Hardware Monitor Enable
+///Master switch to enable or disable hardware monitor function
+typedef enum {
+ IdsNvFchHwmEnableDisabled = 0,///<Disabled
+ IdsNvFchHwmEnableEnabled = 1,///<Enabled
+} IdsNvFchHwmEnable;
+
+///In-Chip IR
+///Enable or disable the In-Chip IR
+typedef enum {
+ IdsNvFchIrConfigDisabled = 0,///<Disabled
+ IdsNvFchIrConfigRX_TX0_Only = 1,///<RX_TX0 Only
+ IdsNvFchIrConfigRX_TX1_Only = 2,///<RX_TX1 Only
+ IdsNvFchIrConfigRX__TX0__and_TX1 = 3,///<RX, TX0, and TX1
+} IdsNvFchIrConfig;
+
+///SD Configuration Mode
+///Select SD Mode
+typedef enum {
+ IdsNvFchSdConfigDisabled = 0,///<Disabled
+ IdsNvFchSdConfigADMA = 1,///<ADMA
+ IdsNvFchSdConfigDMA = 2,///<DMA
+ IdsNvFchSdConfigPIO = 3,///<PIO
+} IdsNvFchSdConfig;
+
+///Azalia Device
+///Select disable or enable Azalia Device
+typedef enum {
+ IdsNvFchAzaliaControlAuto = 0,///<Auto
+ IdsNvFchAzaliaControlDisabled = 1,///<Disabled
+ IdsNvFchAzaliaControlEnabled = 2,///<Enabled
+ IdsNvFchAzaliaControlReserved = 3,///<Reserved
+} IdsNvFchAzaliaControl;
+
+///Integrated Graphics Controller
+///Enable Integrate Graphics controller
+typedef enum {
+ IdsNvGnbGfxiGPU_CONTROLAuto = 0,///<Auto
+ IdsNvGnbGfxiGPU_CONTROLDisabled = 1,///<Disabled
+ IdsNvGnbGfxiGPU_CONTROLForces = 2,///<Forces
+} IdsNvGnbGfxiGPU_CONTROL;
+
+///UMA Frame buffer Size
+///Set UMA FB size
+typedef enum {
+ IdsNvGnbGfxUmaFrameBufferSizeAuto = 0,///<Auto
+ IdsNvGnbGfxUmaFrameBufferSize32M = 1,///<32M
+ IdsNvGnbGfxUmaFrameBufferSize64M = 2,///<64M
+ IdsNvGnbGfxUmaFrameBufferSize128M = 3,///<128M
+ IdsNvGnbGfxUmaFrameBufferSize256M = 4,///<256M
+ IdsNvGnbGfxUmaFrameBufferSize384M = 5,///<384M
+ IdsNvGnbGfxUmaFrameBufferSize512M = 6,///<512M
+ IdsNvGnbGfxUmaFrameBufferSize1G = 7,///<1G
+ IdsNvGnbGfxUmaFrameBufferSize2G = 8,///<2G
+ IdsNvGnbGfxUmaFrameBufferSize4G = 9,///<4G
+} IdsNvGnbGfxUmaFrameBufferSize;
+
+///NB Azalia
+///Enable Integrate HD Audio controller
+typedef enum {
+ IdsNvGnbGfxNbAzaliaDisabled = 0,///<Disabled
+ IdsNvGnbGfxNbAzaliaEnabled = 1,///<Enabled
+ IdsNvGnbGfxNbAzaliaAuto = 0xf,///<Auto
+} IdsNvGnbGfxNbAzalia;
+
+///PSPP Policy
+///PCIe speed power policy
+typedef enum {
+ IdsNvGnbPciePsppPolicyDisabled = 0,///<Disabled
+ IdsNvGnbPciePsppPolicyPerformance = 1,///<Performance
+ IdsNvGnbPciePsppPolicyBalanced_High = 2,///<Balanced-High
+ IdsNvGnbPciePsppPolicyBalanced_Low = 3,///<Balanced-Low
+ IdsNvGnbPciePsppPolicyPower_Saving = 4,///<Power Saving
+ IdsNvGnbPciePsppPolicyAuto = 5,///<Auto
+} IdsNvGnbPciePsppPolicy;
+
+///IOMMU
+///
+typedef enum {
+ IdsNvGnbNbIOMMUDisabled = 0,///<Disabled
+ IdsNvGnbNbIOMMUEnabled = 1,///<Enabled
+} IdsNvGnbNbIOMMU;
+
+#endif // _IDSF15TNNVDEF_H_
+
diff --git a/src/vendorcode/amd/pi/00630F01/Proc/IDS/IdsLib.h b/src/vendorcode/amd/pi/00630F01/Proc/IDS/IdsLib.h
new file mode 100644
index 0000000..2aec84a
--- /dev/null
+++ b/src/vendorcode/amd/pi/00630F01/Proc/IDS/IdsLib.h
@@ -0,0 +1,381 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD IDS Routines
+ *
+ * Contains AMD AGESA Integrated Debug Macros
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: IDS
+ * @e \$Revision: 281181 $ @e \$Date: 2013-12-18 02:18:55 -0600 (Wed, 18 Dec 2013) $
+ */
+/*****************************************************************************
+ *
+ * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ***************************************************************************/
+
+#ifndef _IDS_LIB_H_
+#define _IDS_LIB_H_
+#include "OptionsIds.h"
+#include "cpuRegisters.h"
+#include "cpuApicUtilities.h"
+#include "Table.h"
+///Specific time stamp performance analysis which need ids control support
+#if IDSOPT_CONTROL_ENABLED == TRUE
+ #define PERF_SPEC_TS_ANALYSE(StdHeader) IdsPerfSpecTsAnalyse(StdHeader)
+#else
+ #define PERF_SPEC_TS_ANALYSE(StdHeader)
+#endif
+
+#define IDS_NV_READ(NvValue, Nvid, IdsNvPtr, StdHeader)\
+ NvValue = AmdIdsNvReader ((Nvid), (IdsNvPtr), (StdHeader));
+
+#define IDS_NV_READ_SKIP(NvValue, Nvid, IdsNvPtr, StdHeader)\
+ if (((NvValue) = AmdIdsNvReader ((Nvid), (IdsNvPtr), (StdHeader))) != IDS_UNSUPPORTED)
+#define IDS_GET_MASK32(HighBit, LowBit) ((((UINT32) 1 << (HighBit - LowBit + 1)) - 1) << LowBit)
+
+#define IDS_MAX_MEM_ITEMS 80 ///< Maximum IDS Mem Table Size in Heap.
+///Macro for Ids family feat
+#define MAKE_IDS_FAMILY_FEAT_ALL_CORES(FEAT_ID, FAMILY, FUNCTION) \
+ {IDS_FEAT_COMMON, IDS_ALL_CORES, FEAT_ID, FAMILY, FUNCTION}
+
+///Macro for signature
+#define MAKE_SIGNATURE(a, b, c, d) ((UINT32) ((d << 24) | (c << 16) | (b << 8) | a))
+typedef UINT32 SIGNATURE;
+
+// TYPEDEFS, STRUCTURES, ENUMS
+//
+
+typedef AGESA_STATUS (*PF_IDS_AP_TASK) (VOID *AptaskPara, AMD_CONFIG_PARAMS *StdHeader);
+
+///Structure define for IdsAgesaRunFcnOnApLate
+typedef struct _IDSAPLATETASK {
+ PF_IDS_AP_TASK ApTask; ///< Point function which AP need to do
+ VOID *ApTaskPara; ///< Point to Ap function parameter1
+} IDSAPLATETASK;
+
+/// Data Structure defining IDS Data in HEAP
+/// This data structure contains information that is stored in HEAP and will be
+/// used in IDS backend function. It includes the size of memory to be allocated
+/// for IDS, the relative offsets of the mapping table IDS setup options, the GRA
+/// table and the register table to override mem setting. It also includes a base
+/// address of IDS override image which will be used to control the behavior of
+/// AGESA testpoint if this feature is enabled.
+typedef struct {
+ BOOLEAN IgnoreIdsDefault; ///< Control ignore Default value of IDS NV list specified by IdsNvTableOffset
+ UINT64 IdsImageBase; ///< IDS Override Image Base Address
+ UINT32 IdsHeapMemSize; ///< IDS Total Memory Size in Heap
+ UINT32 IdsNvTableOffset; ///< Offset of IDS NV Table
+ UINT32 IdsMemTableOffset; ///< Offset of IDS Mem Table
+ UINT32 IdsExtendOffset; ///< Offset of Ids extend heap
+} IDS_CONTROL_STRUCT;
+
+/// Data Structure of Parameters for TestPoint_TSC.
+typedef struct {
+ UINT32 LineInFile; ///< Line of current time counter
+ UINT64 Description; ///<Description ID
+ UINT64 StartTsc; ///< The StartTimer of TestPoint_TSC
+} TestPoint_TSC;
+
+#define MAX_PERFORMANCE_UNIT_NUM (IDS_TP_END - TP_BEGINPROCAMDINITEARLY)
+/// Data Structure of Parameters for TP_Perf_STRUCT.
+typedef struct {
+ UINT32 Signature; ///< "PERF"
+ UINT32 Version; ///< version
+ UINT32 Index; ///< The Index of TP_Perf_STRUCT
+ UINT32 TscInMhz; ///< Tsc counter in 1 mhz
+ TestPoint_TSC TP[MAX_PERFORMANCE_UNIT_NUM]; ///< The TP of TP_Perf_STRUCT
+} TP_Perf_STRUCT;
+
+///Bus speed Optimization
+typedef enum {
+ IDS_POWER_POLICY_PERFORMANCE = 0, ///< Performance
+ IDS_POWER_POLICY_POWER = 1, ///< Power
+ IDS_POWER_POLICY_AUTO = 3, ///< Auto
+} IDS_NV_AMDBUSSPEEDOPTIMIZATION;
+
+///IDS early AP task
+typedef struct _IDS_EARLY_AP_TASK0 {
+ UINT8 Core; ///< Core to run Aptask
+ AP_TASK ApTask; ///< Speicify task property
+} IDS_EARLY_AP_TASK0;
+
+#define IDS_EARLY_AP_TASK_PARA_NUM 100
+///IDS early AP task
+typedef struct _IDS_EARLY_AP_TASK {
+ IDS_EARLY_AP_TASK0 Ap_Task0; ///< Ap Task exclude parameter buffer
+ UINT8 Parameters[IDS_EARLY_AP_TASK_PARA_NUM]; ///< Parameter buffer
+} IDS_EARLY_AP_TASK;
+
+///AP service Time Point
+typedef enum {
+ IDS_AP_RUN_CODE_EARLY, ///< Amdinitearly
+ IDS_AP_RUN_CODE_POST, ///< Amdinitpost
+ IDS_AP_RUN_CODE_LATE, ///< After AmdInitPost
+ IDS_AP_RUN_CODE_END ///< Last element
+} IDS_AP_RUN_CODE_TIMEPOINT;
+
+/// Parameters for IdsRunCodeOnCores
+typedef struct _IDS_RUNCODE_PARAMS {
+ IDS_AP_RUN_CODE_TIMEPOINT TimePoint; ///< TimePoint
+ UINT8 Socket; ///< IDS_ALL_SOCKET: all sockets
+ UINT8 Core; ///< IDS_ALL_CORE: all cores
+ PF_AP_TASK_IO ApTask; ///< Only support this type function
+ UINT16 ParamsDataSizeInDwords; ///< Size of the data to be transferred rounded up to the nearest dword
+ VOID *ParamsDataPtr; ///< Pointer to the parameter
+} IDS_RUNCODE_PARAMS;
+
+
+#define IDS_ALL_SOCKET 0xFF
+#define IDS_ALL_MODULE 0xFF
+#define IDS_ALL_CORE 0xFF
+#define IDS_ALL_DCT 0xFF
+
+/*----------------------------------------------------------------------------------------
+ * F U N C T I O N P R O T O T Y P E
+ *----------------------------------------------------------------------------------------
+ */
+
+IDS_STATUS
+IdsSubUCode (
+ IN OUT VOID *DataPtr,
+ IN OUT AMD_CONFIG_PARAMS *StdHeader,
+ IN IDS_NV_ITEM *IdsNvPtr
+ );
+
+IDS_STATUS
+IdsSubGangingMode (
+ IN OUT VOID *DataPtr,
+ IN OUT AMD_CONFIG_PARAMS *StdHeader,
+ IN IDS_NV_ITEM *IdsNvPtr
+ );
+
+IDS_STATUS
+IdsSubPowerDownMode (
+ IN OUT VOID *DataPtr,
+ IN OUT AMD_CONFIG_PARAMS *StdHeader,
+ IN IDS_NV_ITEM *IdsNvPtr
+ );
+
+IDS_STATUS
+IdsSubAllMemClkEn (
+ IN OUT VOID *DataPtr,
+ IN OUT AMD_CONFIG_PARAMS *StdHeader,
+ IN IDS_NV_ITEM *IdsNvPtr
+ );
+
+IDS_STATUS
+IdsSubPostPState (
+ IN OUT VOID *DataPtr,
+ IN OUT AMD_CONFIG_PARAMS *StdHeader,
+ IN IDS_NV_ITEM *IdsNvPtr
+ );
+
+IDS_STATUS
+IdsSubPowerPolicyOverride (
+ IN OUT VOID *DataPtr,
+ IN OUT AMD_CONFIG_PARAMS *StdHeader,
+ IN IDS_NV_ITEM *IdsNvPtr
+ );
+
+AGESA_STATUS
+AmdIdsCtrlInitialize (
+ IN OUT AMD_CONFIG_PARAMS *StdHeader
+ );
+
+IDS_STATUS
+AmdIdsNvReader (
+ IN UINT16 IdsNvId,
+ IN IDS_NV_ITEM *NvTablePtr,
+ IN OUT AMD_CONFIG_PARAMS *StdHeader
+ );
+
+AGESA_STATUS
+AmdGetIdsNvTable (
+ IN OUT VOID **IdsNvTable,
+ IN OUT AMD_CONFIG_PARAMS *StdHeader
+ );
+
+VOID
+IdsOutPort (
+ IN UINT32 Addr,
+ IN UINT32 Value,
+ IN UINT32 Flag
+ );
+
+IDS_STATUS
+IdsCommonReturn (
+ IN OUT VOID *DataPtr,
+ IN OUT AMD_CONFIG_PARAMS *StdHeader,
+ IN IDS_NV_ITEM *IdsNvPtr
+ );
+
+AGESA_STATUS
+IdsAgesaRunFcnOnApLate (
+ IN UINTN ApicIdOfCore,
+ IN IDSAPLATETASK *ApLateTaskPtr,
+ IN OUT AMD_CONFIG_PARAMS *StdHeader
+ );
+
+VOID
+IdsRunCodeOnCores (
+ IN IDS_RUNCODE_PARAMS *PIdsRuncodeParams,
+ IN OUT AMD_CONFIG_PARAMS *StdHeader
+ );
+
+AGESA_STATUS
+IdsAgesaRunFcnOnAllCoresLate (
+ IN IDSAPLATETASK *ApLateTaskPtr,
+ IN OUT AMD_CONFIG_PARAMS *StdHeader
+ );
+
+IDS_STATUS
+IdsParseFeatTbl (
+ IN AGESA_IDS_OPTION IdsOption,
+ IN CONST IDS_FAMILY_FEAT_STRUCT * PIdsFeatTbl[],
+ IN OUT VOID *DataPtr,
+ IN IDS_NV_ITEM *IdsNvPtr,
+ IN OUT AMD_CONFIG_PARAMS *StdHeader
+ );
+
+IDS_STATUS
+IdsSubPowerDownCtrl (
+ IN OUT VOID *DataPtr,
+ IN OUT AMD_CONFIG_PARAMS *StdHeader,
+ IN IDS_NV_ITEM *IdsNvPtr
+ );
+
+IDS_STATUS
+IdsSubHdtOut (
+ IN OUT VOID *DataPtr,
+ IN OUT AMD_CONFIG_PARAMS *StdHeader,
+ IN IDS_NV_ITEM *IdsNvPtr
+ );
+
+UINT8
+IdsGetNumPstatesFamCommon (
+ IN OUT AMD_CONFIG_PARAMS *StdHeader
+ );
+
+VOID
+IdsApRunCodeOnAllLocalCores (
+ IN AP_TASK *TaskPtr,
+ IN OUT AMD_CONFIG_PARAMS *StdHeader
+ );
+IDS_STATUS
+IdsSubTargetPstate (
+ IN OUT VOID *DataPtr,
+ IN OUT AMD_CONFIG_PARAMS *StdHeader,
+ IN IDS_NV_ITEM *IdsNvPtr
+ );
+
+VOID
+IdsMakePciRegEntry (
+ IN OUT TABLE_ENTRY_FIELDS **TableEntry,
+ IN UINT64 Family,
+ IN UINT64 Revision,
+ IN UINT32 PciAddr,
+ IN UINT32 Data,
+ IN UINT32 Mask
+ );
+
+VOID
+IdsLibPciWriteBitsToAllNode (
+ IN PCI_ADDR PciAddress,
+ IN UINT8 Highbit,
+ IN UINT8 Lowbit,
+ IN UINT32 *Value,
+ IN OUT AMD_CONFIG_PARAMS *StdHeader
+ );
+VOID
+IdsRunCodeOnCoreEarly (
+ IN UINT8 Socket,
+ IN UINT8 Core,
+ IN AP_TASK* ApTask,
+ IN OUT AMD_CONFIG_PARAMS *StdHeader
+ );
+
+VOID
+IdsGetMask64bits (
+ IN UINT64 RegVal,
+ IN UINT8 Highbit,
+ IN UINT8 Lowbit,
+ IN OUT UINT64 *AndMask,
+ IN OUT UINT64 *OrMask
+ );
+
+VOID
+IdsGetMask32bits (
+ IN UINT32 RegVal,
+ IN UINT8 Highbit,
+ IN UINT8 Lowbit,
+ IN OUT UINT32 *AndMask,
+ IN OUT UINT32 *OrMask
+ );
+
+VOID
+IdsGetMask16bits (
+ IN UINT16 RegVal,
+ IN UINT8 Highbit,
+ IN UINT8 Lowbit,
+ IN OUT UINT32 *AndMask,
+ IN OUT UINT32 *OrMask
+ );
+
+VOID
+IdsGetStartEndModule (
+ IN UINT8 ModuleId,
+ IN OUT UINT8 *StartModule,
+ IN OUT UINT8 *EndModule
+ );
+
+
+VOID
+IdsGetStartEndSocket (
+ IN UINT8 SocketId,
+ IN OUT UINT8 *StartSocket,
+ IN OUT UINT8 *EndSocket
+ );
+
+BOOLEAN
+IdsCheckPciExist (
+ IN PCI_ADDR PciAddr,
+ IN OUT AMD_CONFIG_PARAMS *StdHeader
+ );
+
+VOID
+IdsLibDataMaskSet32 (
+ IN OUT UINT32 *Value,
+ IN UINT32 AndMask,
+ IN UINT32 OrMask
+ );
+#define IDS_CPB_BOOST_DIS_IGNORE 0xFFFFFFFFul
+
+#endif //_IDS_LIB_H_
+
diff --git a/src/vendorcode/amd/pi/00630F01/Proc/IDS/OptionsIds.h b/src/vendorcode/amd/pi/00630F01/Proc/IDS/OptionsIds.h
new file mode 100644
index 0000000..0d58e7e
--- /dev/null
+++ b/src/vendorcode/amd/pi/00630F01/Proc/IDS/OptionsIds.h
@@ -0,0 +1,92 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * IDS Option File
+ *
+ * This file is used to switch on/off IDS features.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: Core
+ * @e \$Revision: 281181 $ @e \$Date: 2013-12-18 02:18:55 -0600 (Wed, 18 Dec 2013) $
+ */
+/*****************************************************************************
+ *
+ * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ***************************************************************************/
+#ifndef _OPTION_IDS_H_
+#define _OPTION_IDS_H_
+
+/**
+ *
+ * This file generates the defaults tables for the Integrated Debug Support
+ * Module. The documented build options are imported from a user controlled
+ * file for processing. The build options for the Integrated Debug Support
+ * Module are listed below:
+ *
+ * IDSOPT_IDS_ENABLED
+ * IDSOPT_ERROR_TRAP_ENABLED
+ * IDSOPT_CONTROL_ENABLED
+ *
+ * Warning: When you enable the IDSOPT_CONTROL_NV_TO_CMOS feature.
+ * please make the cmos region defined by IDS_OPT_CMOS_REGION_START &
+ * IDS_OPT_CMOS_REGION_END can be touched between IDS HOOK point
+ * IDS_CPU_Early_Override and IDS_BEFORE_AP_EARLY_HALT of BSP
+ *
+ * IDSOPT_CONTROL_NV_TO_CMOS
+ * IDS_OPT_CMOS_INDEX_PORT
+ * IDS_OPT_CMOS_DATA_PORT
+ * IDS_OPT_CMOS_REGION_START
+ * IDS_OPT_CMOS_REGION_END
+ *
+ * IDSOPT_TRACING_ENABLED
+ * IDSOPT_TRACING_CONSOLE_HDTOUT
+ * IDSOPT_TRACING_CONSOLE_SERIALPORT
+ * IDSOPT_SERIAL_PORT (default 0x3F8)
+ * IDSOPT_TRACING_CONSOLE_REDIRECT_IO
+ * IDSOPT_DEBUG_PRINT_IO_PORT (default 0x80)
+ * IDSOPT_TRACING_CONSOLE_RAM
+ * IDSOPT_DPRAM_BASE
+ * IDSOPT_DPRAM_SIZE
+ * IDSOPT_DPRAM_STOP_LOGGING_WHEN_BUFFER_FULL (default FALSE)
+ * IDSOPT_CUSTOMIZE_TRACING_SERVICE
+ * IDSOPT_CUSTOMIZE_TRACING_SERVICE_INIT
+ * IDSOPT_CUSTOMIZE_TRACING_SERVICE_EXIT
+ *
+ * IDSOPT_TRACE_BLD_CFG
+ * IDSOPT_PERF_ANALYSIS
+ * IDSOPT_ASSERT_ENABLED
+ * IDS_DEBUG_PORT
+ * IDSOPT_CAR_CORRUPTION_CHECK_ENABLED
+ * IDSOPT_DEBUG_CODE_ENABLED
+ * IDSOPT_IDT_EXCEPTION_TRAP
+ * IDSOPT_C_OPTIMIZATION_DISABLED
+ *
+ **/
+
+#endif
diff --git a/src/vendorcode/amd/pi/00630F01/binaryPI/AGESA.c b/src/vendorcode/amd/pi/00630F01/binaryPI/AGESA.c
new file mode 100644
index 0000000..7a6851d
--- /dev/null
+++ b/src/vendorcode/amd/pi/00630F01/binaryPI/AGESA.c
@@ -0,0 +1,696 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Agesa structures and definitions
+ *
+ * Contains AMD AGESA core interface
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: Include
+ * @e \$Revision: 85818 $ @e \$Date: 2013-01-11 17:04:21 -0600 (Fri, 11 Jan 2013) $
+ */
+/*****************************************************************************
+ *
+ * Copyright (c) 2008 - 2014, Advanced Micro Devices, Inc.
+ * 2013 - 2014, Sage Electronic Engineering, LLC
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ***************************************************************************/
+#include <AGESA.h>
+#include <agesawrapper.h>
+#include <AcpiLib.h>
+#include <amdlib.h>
+#include <cbfs.h>
+#include <FchCommonCfg.h>
+#include <Fch.h>
+#include <FchDef.h>
+#include <FieldAccessors.h>
+
+#define CONFIG_CBFS_AGESA_NAME "AGESA"
+
+AGESA_STATUS
+HeapAllocateBuffer (
+ IN OUT VOID *AllocateHeapParams,
+ IN OUT VOID *StdHeader
+ );
+
+AGESA_STATUS
+HeapDeallocateBuffer (
+ IN UINT32 BufferHandle,
+ IN VOID *StdHeader
+ );
+
+CONST UINT32 ImageSignature = IMAGE_SIGNATURE;
+CONST UINT32 ModuleSignature = MODULE_SIGNATURE;
+CONST CHAR8 ModuleIdentifier[] = AGESA_ID;
+
+/************************************************************************
+ *
+ * AGESA Basic Level interface structure definition and function prototypes
+ *
+ ***********************************************************************/
+
+
+/**********************************************************************
+ * Interface call: AmdCreateStruct
+ **********************************************************************/
+AGESA_STATUS
+AmdCreateStruct (
+ IN OUT AMD_INTERFACE_PARAMS *InterfaceParams
+ )
+{
+ MODULE_ENTRY Dispatcher = NULL;
+ const AMD_MODULE_HEADER* module = agesawrapper_locate_module(ModuleIdentifier);
+ InterfaceParams->StdHeader.Func = AMD_CREATE_STRUCT;
+ if (!module) return AGESA_UNSUPPORTED;
+ Dispatcher = module->ModuleDispatcher;
+ return Dispatcher(InterfaceParams);
+}
+
+/**********************************************************************
+ * Interface call: AmdReleaseStruct
+ **********************************************************************/
+AGESA_STATUS
+AmdReleaseStruct (
+ IN OUT AMD_INTERFACE_PARAMS *InterfaceParams
+ )
+{
+ MODULE_ENTRY Dispatcher = NULL;
+ const AMD_MODULE_HEADER* module = agesawrapper_locate_module(ModuleIdentifier);
+ InterfaceParams->StdHeader.Func = AMD_RELEASE_STRUCT;
+ if (!module) return AGESA_UNSUPPORTED;
+ Dispatcher = module->ModuleDispatcher;
+ return Dispatcher(InterfaceParams);
+}
+
+/**********************************************************************
+ * Interface call: AmdInitReset
+ **********************************************************************/
+AGESA_STATUS
+AmdInitReset (
+ IN OUT AMD_RESET_PARAMS *ResetParams
+ )
+{
+ MODULE_ENTRY Dispatcher = NULL;
+ const AMD_MODULE_HEADER* module = agesawrapper_locate_module(ModuleIdentifier);
+ ResetParams->StdHeader.Func = AMD_INIT_RESET;
+ if (!module) return AGESA_UNSUPPORTED;
+ Dispatcher = module->ModuleDispatcher;
+ return Dispatcher(ResetParams);
+}
+
+/**********************************************************************
+ * Interface call: AmdInitEarly
+ **********************************************************************/
+AGESA_STATUS
+AmdInitEarly (
+ IN OUT AMD_EARLY_PARAMS *EarlyParams
+ )
+{
+ MODULE_ENTRY Dispatcher = NULL;
+ const AMD_MODULE_HEADER* module = agesawrapper_locate_module(ModuleIdentifier);
+ EarlyParams->StdHeader.Func = AMD_INIT_EARLY;
+ if (!module) return AGESA_UNSUPPORTED;
+ Dispatcher = module->ModuleDispatcher;
+ return Dispatcher(EarlyParams);
+}
+
+/**********************************************************************
+ * Interface call: AmdInitPost
+ **********************************************************************/
+AGESA_STATUS
+AmdInitPost (
+ IN OUT AMD_POST_PARAMS *PostParams ///< Amd Cpu init param
+ )
+{
+ MODULE_ENTRY Dispatcher = NULL;
+ const AMD_MODULE_HEADER* module = agesawrapper_locate_module(ModuleIdentifier);
+ PostParams->StdHeader.Func = AMD_INIT_POST;
+ if (!module) return AGESA_UNSUPPORTED;
+ Dispatcher = module->ModuleDispatcher;
+ return Dispatcher(PostParams);
+}
+
+/**********************************************************************
+ * Interface call: AmdInitEnv
+ **********************************************************************/
+AGESA_STATUS
+AmdInitEnv (
+ IN OUT AMD_ENV_PARAMS *EnvParams
+ )
+{
+ MODULE_ENTRY Dispatcher = NULL;
+ const AMD_MODULE_HEADER* module = agesawrapper_locate_module(ModuleIdentifier);
+ EnvParams->StdHeader.Func = AMD_INIT_ENV;
+ if (!module) return AGESA_UNSUPPORTED;
+ Dispatcher = module->ModuleDispatcher;
+ return Dispatcher(EnvParams);
+}
+
+/**********************************************************************
+ * Interface call: AmdInitMid
+ **********************************************************************/
+AGESA_STATUS
+AmdInitMid (
+ IN OUT AMD_MID_PARAMS *MidParams
+ )
+{
+ MODULE_ENTRY Dispatcher = NULL;
+ const AMD_MODULE_HEADER* module = agesawrapper_locate_module(ModuleIdentifier);
+ MidParams->StdHeader.Func = AMD_INIT_MID;
+ if (!module) return AGESA_UNSUPPORTED;
+ Dispatcher = module->ModuleDispatcher;
+ return Dispatcher(MidParams);
+}
+
+/**********************************************************************
+ * Interface call: AmdInitLate
+ **********************************************************************/
+AGESA_STATUS
+AmdInitLate (
+ IN OUT AMD_LATE_PARAMS *LateParams
+ )
+{
+ MODULE_ENTRY Dispatcher = NULL;
+ const AMD_MODULE_HEADER* module = agesawrapper_locate_module(ModuleIdentifier);
+ LateParams->StdHeader.Func = AMD_INIT_LATE;
+ if (!module) return AGESA_UNSUPPORTED;
+ Dispatcher = module->ModuleDispatcher;
+ return Dispatcher(LateParams);
+}
+
+/**********************************************************************
+ * Interface call: AmdInitRecovery
+ **********************************************************************/
+AGESA_STATUS
+AmdInitRecovery (
+ IN OUT AMD_RECOVERY_PARAMS *RecoveryParams
+ )
+{
+ MODULE_ENTRY Dispatcher = NULL;
+ const AMD_MODULE_HEADER* module = agesawrapper_locate_module(ModuleIdentifier);
+ RecoveryParams->StdHeader.Func = AMD_INIT_RECOVERY;
+ if (!module) return AGESA_UNSUPPORTED;
+ Dispatcher = module->ModuleDispatcher;
+ return Dispatcher(RecoveryParams);
+}
+
+/**********************************************************************
+ * Interface call: AmdInitResume
+ **********************************************************************/
+AGESA_STATUS
+AmdInitResume (
+ IN AMD_RESUME_PARAMS *ResumeParams
+ )
+{
+ MODULE_ENTRY Dispatcher = NULL;
+ const AMD_MODULE_HEADER* module = agesawrapper_locate_module(ModuleIdentifier);
+ ResumeParams->StdHeader.Func = AMD_INIT_RESUME;
+ if (!module) return AGESA_UNSUPPORTED;
+ Dispatcher = module->ModuleDispatcher;
+ return Dispatcher(ResumeParams);
+}
+
+/**********************************************************************
+ * Interface call: AmdS3LateRestore
+ **********************************************************************/
+AGESA_STATUS
+AmdS3LateRestore (
+ IN OUT AMD_S3LATE_PARAMS *S3LateParams
+ )
+{
+ MODULE_ENTRY Dispatcher = NULL;
+ const AMD_MODULE_HEADER* module = agesawrapper_locate_module(ModuleIdentifier);
+ S3LateParams->StdHeader.Func = AMD_S3LATE_RESTORE;
+ if (!module) return AGESA_UNSUPPORTED;
+ Dispatcher = module->ModuleDispatcher;
+ return Dispatcher(S3LateParams);
+}
+
+/**********************************************************************
+ * Interface call: AmdS3Save
+ **********************************************************************/
+AGESA_STATUS
+AmdS3Save (
+ IN OUT AMD_S3SAVE_PARAMS *AmdS3SaveParams
+ )
+{
+ MODULE_ENTRY Dispatcher = NULL;
+ const AMD_MODULE_HEADER* module = agesawrapper_locate_module(ModuleIdentifier);
+ AmdS3SaveParams->StdHeader.Func = AMD_S3_SAVE;
+ if (!module) return AGESA_UNSUPPORTED;
+ Dispatcher = module->ModuleDispatcher;
+ return Dispatcher(AmdS3SaveParams);
+}
+
+/**********************************************************************
+ * Interface call: AmdLateRunApTask
+ **********************************************************************/
+AGESA_STATUS
+AmdLateRunApTask (
+ IN AP_EXE_PARAMS *AmdApExeParams
+)
+{
+ MODULE_ENTRY Dispatcher = NULL;
+ const AMD_MODULE_HEADER* module = agesawrapper_locate_module(ModuleIdentifier);
+ AmdApExeParams->StdHeader.Func = AMD_LATE_RUN_AP_TASK;
+ if (!module) return AGESA_UNSUPPORTED;
+ Dispatcher = module->ModuleDispatcher;
+ return Dispatcher(AmdApExeParams);
+}
+
+/**********************************************************************
+ * Interface service call: AmdGetApicId
+ **********************************************************************/
+AGESA_STATUS
+AmdGetApicId (
+ IN OUT AMD_APIC_PARAMS *AmdParamApic
+)
+{
+ MODULE_ENTRY Dispatcher = NULL;
+ const AMD_MODULE_HEADER* module = agesawrapper_locate_module(ModuleIdentifier);
+ AmdParamApic->StdHeader.Func = AMD_GET_APIC_ID;
+ if (!module) return AGESA_UNSUPPORTED;
+ Dispatcher = module->ModuleDispatcher;
+ return Dispatcher(AmdParamApic);
+}
+
+/**********************************************************************
+ * Interface service call: AmdGetPciAddress
+ **********************************************************************/
+AGESA_STATUS
+AmdGetPciAddress (
+ IN OUT AMD_GET_PCI_PARAMS *AmdParamGetPci
+)
+{
+ MODULE_ENTRY Dispatcher = NULL;
+ const AMD_MODULE_HEADER* module = agesawrapper_locate_module(ModuleIdentifier);
+ AmdParamGetPci->StdHeader.Func = AMD_GET_PCI_ADDRESS;
+ if (!module) return AGESA_UNSUPPORTED;
+ Dispatcher = module->ModuleDispatcher;
+ return Dispatcher(AmdParamGetPci);
+}
+
+/**********************************************************************
+ * Interface service call: AmdIdentifyCore
+ **********************************************************************/
+AGESA_STATUS
+AmdIdentifyCore (
+ IN OUT AMD_IDENTIFY_PARAMS *AmdParamIdentify
+)
+{
+ MODULE_ENTRY Dispatcher = NULL;
+ const AMD_MODULE_HEADER* module = agesawrapper_locate_module(ModuleIdentifier);
+ AmdParamIdentify->StdHeader.Func = AMD_IDENTIFY_CORE;
+ if (!module) return AGESA_UNSUPPORTED;
+ Dispatcher = module->ModuleDispatcher;
+ return Dispatcher(AmdParamIdentify);
+}
+
+/**********************************************************************
+ * Interface service call: AmdReadEventLog
+ **********************************************************************/
+AGESA_STATUS
+AmdReadEventLog (
+ IN EVENT_PARAMS *Event
+)
+{
+ MODULE_ENTRY Dispatcher = NULL;
+ const AMD_MODULE_HEADER* module = agesawrapper_locate_module(ModuleIdentifier);
+ Event->StdHeader.Func = AMD_READ_EVENT_LOG;
+ if (!module) return AGESA_UNSUPPORTED;
+ Dispatcher = module->ModuleDispatcher;
+ return Dispatcher(Event);
+}
+
+/**********************************************************************
+ * Interface service call: AmdIdentifyDimm
+ **********************************************************************/
+AGESA_STATUS
+AmdIdentifyDimm (
+ IN OUT AMD_IDENTIFY_DIMM *AmdDimmIdentify
+)
+{
+ MODULE_ENTRY Dispatcher = NULL;
+ const AMD_MODULE_HEADER* module = agesawrapper_locate_module(ModuleIdentifier);
+ AmdDimmIdentify->StdHeader.Func = AMD_IDENTIFY_DIMMS;
+ if (!module) return AGESA_UNSUPPORTED;
+ Dispatcher = module->ModuleDispatcher;
+ return Dispatcher(AmdDimmIdentify);
+}
+
+AGESA_STATUS
+AmdIdsRunApTaskLate (
+ IN AP_EXE_PARAMS *AmdApExeParams
+ )
+{
+ MODULE_ENTRY Dispatcher = NULL;
+ const AMD_MODULE_HEADER* module = agesawrapper_locate_module(ModuleIdentifier);
+ AmdApExeParams->StdHeader.Func = -1;
+ return AGESA_UNSUPPORTED;
+ if (!module) return AGESA_UNSUPPORTED;
+ Dispatcher = module->ModuleDispatcher;
+ return Dispatcher(AmdApExeParams);
+}
+
+/**********************************************************************
+ * Interface service call: AmdGet2DDataEye
+ **********************************************************************/
+AGESA_STATUS
+AmdGet2DDataEye (
+ IN OUT AMD_GET_DATAEYE *AmdGetDataEye
+ )
+{
+ MODULE_ENTRY Dispatcher = NULL;
+ const AMD_MODULE_HEADER* module = agesawrapper_locate_module(ModuleIdentifier);
+ AmdGetDataEye->StdHeader.Func = AMD_GET_2D_DATA_EYE;
+ if (!module) return AGESA_UNSUPPORTED;
+ Dispatcher = module->ModuleDispatcher;
+ return Dispatcher(AmdGetDataEye);
+}
+
+/**********************************************************************
+ * FCH Functions
+ **********************************************************************/
+
+VOID FchInitS3LateRestore (IN FCH_DATA_BLOCK *FchDataPtr);
+VOID FchInitS3EarlyRestore (IN FCH_DATA_BLOCK *FchDataPtr);
+
+VOID
+FchInitS3EarlyRestore (
+ IN FCH_DATA_BLOCK *FchDataPtr
+ )
+{
+ MODULE_ENTRY Dispatcher = NULL;
+ const AMD_MODULE_HEADER* module = agesawrapper_locate_module(ModuleIdentifier);
+ FchDataPtr->StdHeader->Func = FCH_INIT_S3_EARLY_RESTORE;
+ if (!module) return;
+ Dispatcher = module->ModuleDispatcher;
+ Dispatcher(FchDataPtr);
+}
+
+VOID
+FchInitS3LateRestore (
+ IN FCH_DATA_BLOCK *FchDataPtr
+ )
+{
+ MODULE_ENTRY Dispatcher = NULL;
+ const AMD_MODULE_HEADER* module = agesawrapper_locate_module(ModuleIdentifier);
+ FchDataPtr->StdHeader->Func = FCH_INIT_S3_LATE_RESTORE;
+ if (!module) return;
+ Dispatcher = module->ModuleDispatcher;
+ Dispatcher(FchDataPtr);
+}
+
+/**
+ * WaitForEcLDN9MailboxCmdAck
+ *
+ *
+ * @param[in] StdHeader
+ *
+ */
+VOID
+WaitForEcLDN9MailboxCmdAck (
+ IN AMD_CONFIG_PARAMS *StdHeader
+ )
+{
+ MODULE_ENTRY Dispatcher = NULL;
+ const AMD_MODULE_HEADER* module = agesawrapper_locate_module(ModuleIdentifier);
+ StdHeader->Func = 0;
+ return;
+ if (!module) return;
+ Dispatcher = module->ModuleDispatcher;
+ Dispatcher(StdHeader);
+}
+
+/**
+ * ImcSleep - IMC Sleep.
+ *
+ *
+ * @param[in] FchDataPtr Fch configuration structure pointer.
+ *
+ */
+VOID
+ImcSleep (
+ IN VOID *FchDataPtr
+ )
+{
+ MODULE_ENTRY Dispatcher = NULL;
+ const AMD_MODULE_HEADER* module = agesawrapper_locate_module(ModuleIdentifier);
+ ((FCH_DATA_BLOCK*)FchDataPtr)->StdHeader->Func = 0;
+ return;
+ if (!module) return;
+ Dispatcher = module->ModuleDispatcher;
+ Dispatcher(FchDataPtr);
+}
+
+/**
+ * SoftwareDisableImc - Software disable IMC strap
+ *
+ *
+ * @param[in] FchDataPtr Fch configuration structure pointer.
+ *
+ */
+VOID
+SoftwareDisableImc (
+ IN VOID *FchDataPtr
+ )
+{
+ MODULE_ENTRY Dispatcher = NULL;
+ const AMD_MODULE_HEADER* module = agesawrapper_locate_module(ModuleIdentifier);
+ ((FCH_DATA_BLOCK*)FchDataPtr)->StdHeader->Func = 0;
+ return;
+ if (!module) return;
+ Dispatcher = module->ModuleDispatcher;
+ Dispatcher(FchDataPtr);
+}
+
+/**
+ * ImcEnableSurebootTimer - IMC Enable Sureboot Timer.
+ *
+ *
+ * @param[in] FchDataPtr Fch configuration structure pointer.
+ *
+ */
+VOID
+ImcEnableSurebootTimer (
+ IN VOID *FchDataPtr
+ )
+{
+ MODULE_ENTRY Dispatcher = NULL;
+ const AMD_MODULE_HEADER* module = agesawrapper_locate_module(ModuleIdentifier);
+ ((FCH_DATA_BLOCK*)FchDataPtr)->StdHeader->Func = 0;
+ return;
+ if (!module) return;
+ Dispatcher = module->ModuleDispatcher;
+ Dispatcher(FchDataPtr);
+}
+
+/**
+ * ImcDisableSurebootTimer - IMC Disable Sureboot Timer.
+ *
+ *
+ * @param[in] FchDataPtr Fch configuration structure pointer.
+ *
+ */
+VOID
+ImcDisableSurebootTimer (
+ IN VOID *FchDataPtr
+ )
+{
+ MODULE_ENTRY Dispatcher = NULL;
+ const AMD_MODULE_HEADER* module = agesawrapper_locate_module(ModuleIdentifier);
+ ((FCH_DATA_BLOCK*)FchDataPtr)->StdHeader->Func = 0;
+ return;
+ if (!module) return;
+ Dispatcher = module->ModuleDispatcher;
+ Dispatcher(FchDataPtr);
+}
+
+/**
+ * ImcWakeup - IMC Wakeup.
+ *
+ *
+ * @param[in] FchDataPtr Fch configuration structure pointer.
+ *
+ */
+VOID
+ImcWakeup (
+ IN VOID *FchDataPtr
+ )
+{
+ MODULE_ENTRY Dispatcher = NULL;
+ const AMD_MODULE_HEADER* module = agesawrapper_locate_module(ModuleIdentifier);
+ ((FCH_DATA_BLOCK*)FchDataPtr)->StdHeader->Func = 0;
+ return;
+ if (!module) return;
+ Dispatcher = module->ModuleDispatcher;
+ Dispatcher(FchDataPtr);
+}
+
+/**
+ * ImcIdle - IMC Idle.
+ *
+ *
+ * @param[in] FchDataPtr Fch configuration structure pointer.
+ *
+ */
+VOID
+ImcIdle (
+ IN VOID *FchDataPtr
+ )
+{
+ MODULE_ENTRY Dispatcher = NULL;
+ const AMD_MODULE_HEADER* module = agesawrapper_locate_module(ModuleIdentifier);
+ ((FCH_DATA_BLOCK*)FchDataPtr)->StdHeader->Func = 0;
+ return;
+ if (!module) return;
+ Dispatcher = module->ModuleDispatcher;
+ Dispatcher(FchDataPtr);
+}
+
+// TODO This has to be removed
+AGESA_STATUS
+HeapAllocateBuffer (
+ IN OUT VOID *AllocateHeapParams,
+ IN OUT VOID *StdHeader
+ )
+{
+ MODULE_ENTRY Dispatcher = NULL;
+ const AMD_MODULE_HEADER* module = agesawrapper_locate_module(ModuleIdentifier);
+
+ AMD_INTERFACE_PARAMS InterfaceParams = {};
+
+ if (!module) return AGESA_UNSUPPORTED;
+ Dispatcher = module->ModuleDispatcher;
+
+ InterfaceParams.StdHeader = *(AMD_CONFIG_PARAMS*)StdHeader;
+ InterfaceParams.StdHeader.Func = AMD_HEAP_ALLOCATE_BUFFER;
+
+ InterfaceParams.AllocationMethod = PreMemHeap;
+ InterfaceParams.NewStructPtr = AllocateHeapParams;
+
+ return Dispatcher(&InterfaceParams);
+}
+
+// TODO This has to be removed
+AGESA_STATUS
+HeapDeallocateBuffer (
+ IN UINT32 BufferHandle,
+ IN VOID *StdHeader
+ )
+{
+ MODULE_ENTRY Dispatcher = NULL;
+ const AMD_MODULE_HEADER* module = agesawrapper_locate_module(ModuleIdentifier);
+
+ AMD_INTERFACE_PARAMS InterfaceParams = {};
+
+ if (!module) return AGESA_UNSUPPORTED;
+ Dispatcher = module->ModuleDispatcher;
+
+ InterfaceParams.StdHeader = *(AMD_CONFIG_PARAMS*)StdHeader;
+ InterfaceParams.StdHeader.Func = AMD_HEAP_DEALLOCATE_BUFFER;
+
+ InterfaceParams.NewStructPtr = &BufferHandle;
+
+ return Dispatcher(&InterfaceParams);
+}
+
+/**********************************************************************
+ * Interface call: AmdSetValue
+ **********************************************************************/
+AGESA_STATUS
+AmdSetValue (
+ IN CONST AGESA_FIELD_NAME name,
+ IN OUT VOID* value,
+ IN UINT32 size
+ )
+{
+ AGESA_STATUS status = AGESA_UNSUPPORTED;
+
+ MODULE_ENTRY Dispatcher = NULL;
+ const AMD_MODULE_HEADER* module = agesawrapper_locate_module(ModuleIdentifier);
+
+ AMD_ACCESSOR_PARAMS AccessorParams = {};
+
+ if (!module) return status;
+ Dispatcher = module->ModuleDispatcher;
+
+ AccessorParams.StdHeader.AltImageBasePtr = 0;
+ AccessorParams.StdHeader.CalloutPtr = NULL;
+ AccessorParams.StdHeader.Func = AMD_SET_VALUE;
+ AccessorParams.StdHeader.ImageBasePtr = 0;
+
+ AccessorParams.AllocationMethod = ByHost;
+ AccessorParams.FieldName = name;
+ AccessorParams.FieldValue = value;
+ AccessorParams.FieldSize = size;
+
+ status = Dispatcher(&AccessorParams);
+ return status;
+}
+
+/**********************************************************************
+ * Interface call: AmdGetValue
+ **********************************************************************/
+AGESA_STATUS
+AmdGetValue (
+ IN CONST AGESA_FIELD_NAME name,
+ IN OUT VOID** value,
+ IN UINT32 size
+ )
+{
+ AGESA_STATUS status = AGESA_UNSUPPORTED;
+
+ MODULE_ENTRY Dispatcher = NULL;
+ const AMD_MODULE_HEADER* module = agesawrapper_locate_module(ModuleIdentifier);
+
+ AMD_ACCESSOR_PARAMS AccessorParams = {};
+
+ ASSERT(module);
+ if (!module) return status;
+ Dispatcher = module->ModuleDispatcher;
+ ASSERT(Dispatcher);
+
+ AccessorParams.StdHeader.AltImageBasePtr = 0;
+ AccessorParams.StdHeader.CalloutPtr = NULL;
+ AccessorParams.StdHeader.Func = AMD_GET_VALUE;
+ AccessorParams.StdHeader.ImageBasePtr = 0;
+
+ AccessorParams.AllocationMethod = ByHost;
+ AccessorParams.FieldName = name;
+ AccessorParams.FieldValue = *value;
+ AccessorParams.FieldSize = size;
+
+ status = Dispatcher(&AccessorParams);
+ ASSERT(AGESA_SUCCESS == status);
+
+ *value = AccessorParams.FieldValue;
+ size = AccessorParams.FieldSize;
+
+ return status;
+}
diff --git a/src/vendorcode/amd/pi/00630F01/binaryPI/FieldAccessors.h b/src/vendorcode/amd/pi/00630F01/binaryPI/FieldAccessors.h
new file mode 100644
index 0000000..bfbccbe
--- /dev/null
+++ b/src/vendorcode/amd/pi/00630F01/binaryPI/FieldAccessors.h
@@ -0,0 +1,111 @@
+/*****************************************************************************
+ *
+ * Copyright (c) 2013 - 2014, Sage Electronic Engineering, LLC
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ***************************************************************************/
+#ifndef _FIELDACCESSORS_H_
+#define _FIELDACCESSORS_H_
+
+#include "AGESA.h"
+
+/// AGESA value name
+typedef enum {
+ AMD_GLOBAL_USER_OPTIONS = 0x00020000,
+ AMD_GLOBAL_NUM_SOCKETS = 0x00020001,
+ AMD_GLOBAL_NUM_MODULES = 0x00020002,
+} AGESA_FIELD_NAME;
+
+typedef AGESA_STATUS (*SETTER_ENTRY) (
+ IN OUT VOID* value,
+ IN UINT32 size
+ );
+
+typedef AGESA_STATUS (*GETTER_ENTRY) (
+ IN OUT VOID** value,
+ IN UINT32 size
+ );
+
+/// Accessor Interface.
+typedef struct {
+ IN AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header
+ IN AGESA_FIELD_NAME FieldName; ///< The service to init
+ IN ALLOCATION_METHOD AllocationMethod; ///< For pointers, how to allocate space for copied data
+ IN OUT VOID *Struct; ///< The struct for the service.
+ IN OUT UINT32 FieldSize; ///< The size of the data value.
+ IN OUT VOID *FieldValue; ///< The value retrieved or set into the target structure.
+} AMD_ACCESSOR_PARAMS;
+
+
+/**********************************************************************
+ * Interface call: AmdSetValue
+ **********************************************************************/
+AGESA_STATUS
+AmdGetValue (
+ IN CONST AGESA_FIELD_NAME name,
+ IN OUT VOID** value,
+ IN UINT32 size
+ );
+
+/**********************************************************************
+ * Interface call: AmdSetValue
+ **********************************************************************/
+AGESA_STATUS
+AmdSetValue (
+ IN CONST AGESA_FIELD_NAME name,
+ IN OUT VOID* value,
+ IN UINT32 size
+ );
+
+/**
+ * Dispatch Table.
+ *
+ * The push high dispatcher uses this table to find what entries are currently in the build image.
+ */
+typedef struct {
+ UINT32 FunctionId;
+ SETTER_ENTRY SetValueEntryPoint;
+ GETTER_ENTRY GetValueEntryPoint;
+} ACCESSOR_DISPATCH_TABLE;
+
+AGESA_STATUS
+GetUserOptions(
+ IN OUT VOID** value,
+ IN UINT32 size
+ );
+
+AGESA_STATUS
+GetNumSockets(
+ IN OUT VOID** value,
+ IN UINT32 size
+ );
+
+AGESA_STATUS
+GetNumModules(
+ IN OUT VOID** value,
+ IN UINT32 size
+ );
+
+#endif /* _FIELDACCESSORS_H_ */
diff --git a/src/vendorcode/amd/pi/00630F01/binaryPI/gcc-intrin.h b/src/vendorcode/amd/pi/00630F01/binaryPI/gcc-intrin.h
new file mode 100644
index 0000000..a637715
--- /dev/null
+++ b/src/vendorcode/amd/pi/00630F01/binaryPI/gcc-intrin.h
@@ -0,0 +1,833 @@
+/*
+ Compatibility <intrin_x86.h> header for GCC -- GCC equivalents of intrinsic
+ Microsoft Visual C++ functions. Originally developed for the ReactOS
+ (<http://www.reactos.org/>) and TinyKrnl (<http://www.tinykrnl.org/>)
+ projects.
+
+ Copyright (c) 2006 KJK::Hyperion <hackbunny(a)reactos.com>
+ 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com>
+ 2014 Sage Electronic Engineering, LLC
+ All rights reserved.
+
+ Permission is hereby granted, free of charge, to any person obtaining a
+ copy of this software and associated documentation files (the "Software"),
+ to deal in the Software without restriction, including without limitation
+ the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ and/or sell copies of the Software, and to permit persons to whom the
+ Software is furnished to do so, subject to the following conditions:
+
+ The above copyright notice and this permission notice shall be included in
+ all copies or substantial portions of the Software.
+
+ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ DEALINGS IN THE SOFTWARE.
+*/
+
+#if defined (__GNUC__)
+
+#if !defined(AMDLIB_OPTIMIZE)
+ #define AMDLIB_OPTIMIZE
+#endif
+
+/* I/O intrin functions. */
+static
+AMDLIB_OPTIMIZE
+__inline__ __attribute__((always_inline))
+unsigned char __inbyte(unsigned short Port)
+{
+ unsigned char value;
+
+ __asm__ __volatile__ (
+ "in %1, %0"
+ : "=a" (value)
+ : "Nd" (Port)
+ );
+
+ return value;
+}
+
+static
+AMDLIB_OPTIMIZE
+__inline__ __attribute__((always_inline))
+unsigned short __inword(unsigned short Port)
+{
+ unsigned short value;
+
+ __asm__ __volatile__ (
+ "in %1, %0"
+ : "=a" (value)
+ : "Nd" (Port)
+ );
+
+ return value;
+}
+
+static
+AMDLIB_OPTIMIZE
+__inline__ __attribute__((always_inline))
+unsigned long __indword(unsigned short Port)
+{
+ unsigned long value;
+
+ __asm__ __volatile__ (
+ "in %1, %0"
+ : "=a" (value)
+ : "Nd" (Port)
+ );
+ return value;
+
+}
+
+static
+AMDLIB_OPTIMIZE
+__inline__ __attribute__((always_inline))
+void __outbyte(unsigned short Port,unsigned char Data)
+{
+ __asm__ __volatile__ (
+ "out %0, %1"
+ :
+ : "a" (Data), "Nd" (Port)
+ );
+}
+
+static
+AMDLIB_OPTIMIZE
+__inline__ __attribute__((always_inline))
+void __outword(unsigned short Port,unsigned short Data)
+{
+ __asm__ __volatile__ (
+ "out %0, %1"
+ :
+ : "a" (Data), "Nd" (Port)
+ );
+}
+
+static
+AMDLIB_OPTIMIZE
+__inline__ __attribute__((always_inline))
+void __outdword(unsigned short Port,unsigned long Data)
+{
+ __asm__ __volatile__ (
+ "out %0, %1"
+ :
+ : "a" (Data), "Nd" (Port)
+ );
+}
+
+static
+AMDLIB_OPTIMIZE
+__inline__ __attribute__((always_inline))
+void __inbytestring(unsigned short Port,unsigned char *Buffer,unsigned long Count)
+{
+ __asm__ __volatile__ (
+ "rep ; insb"
+ : "+D" (Buffer), "+c" (Count)
+ : "d"(Port)
+ );
+}
+
+static
+AMDLIB_OPTIMIZE
+__inline__ __attribute__((always_inline))
+void __inwordstring(unsigned short Port,unsigned short *Buffer,unsigned long Count)
+{
+ __asm__ __volatile__ (
+ "rep ; insw"
+ : "+D" (Buffer), "+c" (Count)
+ : "d"(Port)
+ );
+}
+
+static
+AMDLIB_OPTIMIZE
+__inline__ __attribute__((always_inline))
+void __indwordstring(unsigned short Port,unsigned long *Buffer,unsigned long Count)
+{
+ __asm__ __volatile__ (
+ "rep ; insl"
+ : "+D" (Buffer), "+c" (Count)
+ : "d"(Port)
+ );
+}
+
+static
+AMDLIB_OPTIMIZE
+__inline__ __attribute__((always_inline))
+void __outbytestring(unsigned short Port,unsigned char *Buffer,unsigned long Count)
+{
+ __asm__ __volatile__ (
+ "rep ; outsb"
+ : "+S" (Buffer), "+c" (Count)
+ : "d"(Port)
+ );
+}
+
+static
+AMDLIB_OPTIMIZE
+__inline__ __attribute__((always_inline))
+void __outwordstring(unsigned short Port,unsigned short *Buffer,unsigned long Count)
+{
+ __asm__ __volatile__ (
+ "rep ; outsw"
+ : "+S" (Buffer), "+c" (Count)
+ : "d"(Port)
+ );
+}
+
+static
+AMDLIB_OPTIMIZE
+__inline__ __attribute__((always_inline))
+void __outdwordstring(unsigned short Port,unsigned long *Buffer,unsigned long Count)
+{
+ __asm__ __volatile__ (
+ "rep ; outsl"
+ : "+S" (Buffer), "+c" (Count)
+ : "d"(Port)
+ );
+}
+
+static
+AMDLIB_OPTIMIZE
+__inline__ __attribute__((always_inline))
+unsigned long __readdr0(void)
+{
+ unsigned long value;
+ __asm__ __volatile__ (
+ "mov %%dr0, %[value]"
+ : [value] "=r" (value)
+ );
+ return value;
+}
+
+static
+AMDLIB_OPTIMIZE
+__inline__ __attribute__((always_inline))
+unsigned long __readdr1(void)
+{
+ unsigned long value;
+ __asm__ __volatile__ (
+ "mov %%dr1, %[value]"
+ : [value] "=r" (value)
+ );
+ return value;
+}
+
+static
+AMDLIB_OPTIMIZE
+__inline__ __attribute__((always_inline))
+unsigned long __readdr2(void)
+{
+ unsigned long value;
+ __asm__ __volatile__ (
+ "mov %%dr2, %[value]"
+ : [value] "=r" (value)
+ );
+ return value;
+}
+
+static
+AMDLIB_OPTIMIZE
+__inline__ __attribute__((always_inline))
+unsigned long __readdr3(void)
+{
+ unsigned long value;
+ __asm__ __volatile__ (
+ "mov %%dr3, %[value]"
+ : [value] "=r" (value)
+ );
+ return value;
+}
+
+static
+AMDLIB_OPTIMIZE
+__inline__ __attribute__((always_inline))
+unsigned long __readdr7(void)
+{
+ unsigned long value;
+ __asm__ __volatile__ (
+ "mov %%dr7, %[value]"
+ : [value] "=r" (value)
+ );
+ return value;
+}
+
+static
+AMDLIB_OPTIMIZE
+__inline__ __attribute__((always_inline))
+unsigned long __readdr(unsigned long reg)
+{
+ switch (reg){
+ case 0:
+ return __readdr0 ();
+ break;
+
+ case 1:
+ return __readdr1 ();
+ break;
+
+ case 2:
+ return __readdr2 ();
+ break;
+
+ case 3:
+ return __readdr3 ();
+ break;
+
+ case 7:
+ return __readdr7 ();
+ break;
+
+ default:
+ return -1;
+ break;
+ }
+}
+
+static
+AMDLIB_OPTIMIZE
+__inline__ __attribute__((always_inline))
+void __writedr0(unsigned long Data)
+{
+ __asm__ __volatile__ (
+ "mov %0, %%dr0"
+ :
+ : "r" (Data)
+ );
+}
+
+static
+AMDLIB_OPTIMIZE
+__inline__ __attribute__((always_inline))
+void __writedr1(unsigned long Data)
+{
+ __asm__ __volatile__ (
+ "mov %0, %%dr1"
+ :
+ : "r" (Data)
+ );
+}
+
+static
+AMDLIB_OPTIMIZE
+__inline__ __attribute__((always_inline))
+void __writedr2(unsigned long Data)
+{
+ __asm__ __volatile__ (
+ "mov %0, %%dr2"
+ :
+ : "r" (Data)
+ );
+}
+
+static
+AMDLIB_OPTIMIZE
+__inline__ __attribute__((always_inline))
+void __writedr3(unsigned long Data)
+{
+ __asm__ __volatile__ (
+ "mov %0, %%dr3"
+ :
+ : "r" (Data)
+ );
+}
+
+static
+AMDLIB_OPTIMIZE
+__inline__ __attribute__((always_inline))
+void __writedr7(unsigned long Data)
+{
+ __asm__ __volatile__ (
+ "mov %0, %%dr7"
+ :
+ : "r" (Data)
+ );
+}
+
+static
+AMDLIB_OPTIMIZE
+__inline__ __attribute__((always_inline))
+void __writedr(unsigned long reg, unsigned long Data)
+{
+ switch (reg){
+ case 0:
+ __writedr0 (Data);
+ break;
+
+ case 1:
+ __writedr1 (Data);
+ break;
+
+ case 2:
+ __writedr2 (Data);
+ break;
+
+ case 3:
+ __writedr3 (Data);
+ break;
+
+ case 7:
+ __writedr7 (Data);
+ break;
+
+ default:
+ break;
+ }
+}
+
+static
+AMDLIB_OPTIMIZE
+__inline__ __attribute__((always_inline))
+unsigned long __readcr0(void)
+{
+ unsigned long value;
+ __asm__ __volatile__ (
+ "mov %%cr0, %[value]"
+ : [value] "=r" (value));
+ return value;
+}
+
+static
+AMDLIB_OPTIMIZE
+__inline__ __attribute__((always_inline))
+unsigned long __readcr2(void)
+{
+ unsigned long value;
+ __asm__ __volatile__ (
+ "mov %%cr2, %[value]"
+ : [value] "=r" (value));
+ return value;
+}
+
+static
+AMDLIB_OPTIMIZE
+__inline__ __attribute__((always_inline))
+unsigned long __readcr3(void)
+{
+ unsigned long value;
+ __asm__ __volatile__ (
+ "mov %%cr3, %[value]"
+ : [value] "=r" (value));
+ return value;
+}
+
+static
+AMDLIB_OPTIMIZE
+__inline__ __attribute__((always_inline))
+unsigned long __readcr4(void)
+{
+ unsigned long value;
+ __asm__ __volatile__ (
+ "mov %%cr4, %[value]"
+ : [value] "=r" (value));
+ return value;
+}
+
+static
+AMDLIB_OPTIMIZE
+__inline__ __attribute__((always_inline))
+unsigned long __readcr8(void)
+{
+ unsigned long value;
+ __asm__ __volatile__ (
+ "mov %%cr8, %[value]"
+ : [value] "=r" (value));
+ return value;
+}
+
+static
+AMDLIB_OPTIMIZE
+__inline__ __attribute__((always_inline))
+unsigned long __readcr(unsigned long reg)
+{
+ switch (reg){
+ case 0:
+ return __readcr0 ();
+ break;
+
+ case 2:
+ return __readcr2 ();
+ break;
+
+ case 3:
+ return __readcr3 ();
+ break;
+
+ case 4:
+ return __readcr4 ();
+ break;
+
+ case 8:
+ return __readcr8 ();
+ break;
+
+ default:
+ return -1;
+ break;
+ }
+}
+
+static
+AMDLIB_OPTIMIZE
+__inline__ __attribute__((always_inline))
+void __writecr0(unsigned long Data)
+{
+ __asm__ __volatile__ (
+ "mov %0, %%cr0"
+ :
+ : "r" (Data)
+ : "memory"
+ );
+}
+
+static
+AMDLIB_OPTIMIZE
+__inline__ __attribute__((always_inline))
+void __writecr2(unsigned long Data)
+{
+ __asm__ __volatile__ (
+ "mov %0, %%cr2"
+ :
+ : "r" (Data)
+ );
+}
+
+static
+AMDLIB_OPTIMIZE
+__inline__ __attribute__((always_inline))
+void __writecr3(unsigned long Data)
+{
+ __asm__ __volatile__ (
+ "mov %0, %%cr3"
+ :
+ : "r" (Data)
+ );
+}
+
+static
+AMDLIB_OPTIMIZE
+__inline__ __attribute__((always_inline))
+void __writecr4(unsigned long Data)
+{
+ __asm__ __volatile__ (
+ "mov %0, %%cr4"
+ :
+ : "r" (Data)
+ );
+}
+
+static
+AMDLIB_OPTIMIZE
+__inline__ __attribute__((always_inline))
+void __writecr8(unsigned long Data)
+{
+ __asm__ __volatile__ (
+ "mov %0, %%cr8"
+ :
+ : "r" (Data)
+ );
+}
+
+static
+AMDLIB_OPTIMIZE
+__inline__ __attribute__((always_inline))
+void __writecr(unsigned long reg, unsigned long Data)
+{
+ switch (reg){
+ case 0:
+ __writecr0 (Data);
+ break;
+
+ case 2:
+ __writecr2 (Data);
+ break;
+
+ case 3:
+ __writecr3 (Data);
+ break;
+
+ case 4:
+ __writecr4 (Data);
+ break;
+
+ case 8:
+ __writecr8 (Data);
+ break;
+
+ default:
+ break;
+ }
+}
+
+static
+AMDLIB_OPTIMIZE
+__inline__ __attribute__((always_inline))
+UINT64 __readmsr(UINT32 msr)
+{
+ UINT64 retval;
+ __asm__ __volatile__(
+ "rdmsr"
+ : "=A" (retval)
+ : "c" (msr)
+ );
+ return retval;
+}
+
+static
+AMDLIB_OPTIMIZE
+__inline__ __attribute__((always_inline))
+void __writemsr (UINT32 msr, UINT64 Value)
+{
+ __asm__ __volatile__ (
+ "wrmsr"
+ :
+ : "c" (msr), "A" (Value)
+ );
+}
+
+static
+AMDLIB_OPTIMIZE
+__inline__ __attribute__((always_inline))
+UINT64 __rdtsc(void)
+{
+ UINT64 retval;
+ __asm__ __volatile__ (
+ "rdtsc"
+ : "=A" (retval));
+ return retval;
+}
+
+static
+AMDLIB_OPTIMIZE
+__inline__ __attribute__((always_inline))
+void __cpuid(int CPUInfo[], const int InfoType)
+{
+ __asm__ __volatile__(
+ "cpuid"
+ :"=a" (CPUInfo[0]), "=b" (CPUInfo[1]), "=c" (CPUInfo[2]), "=d" (CPUInfo[3])
+ : "a" (InfoType)
+ );
+}
+
+static
+AMDLIB_OPTIMIZE
+__inline__ __attribute__((always_inline))
+void _disable(void)
+{
+ __asm__ __volatile__ ("cli");
+}
+
+static
+AMDLIB_OPTIMIZE
+__inline__ __attribute__((always_inline))
+void _enable(void)
+{
+ __asm__ __volatile__ ("sti");
+}
+
+static
+AMDLIB_OPTIMIZE
+__inline__ __attribute__((always_inline))
+void __halt(void)
+{
+ __asm__ __volatile__ ("hlt");
+}
+
+static
+AMDLIB_OPTIMIZE
+__inline__ __attribute__((always_inline))
+void __debugbreak(void)
+{
+ __asm__ __volatile__ ("int3");
+}
+
+static
+AMDLIB_OPTIMIZE
+__inline__ __attribute__((always_inline))
+void __invd(void)
+{
+ __asm__ __volatile__ ("invd");
+}
+
+static
+AMDLIB_OPTIMIZE
+__inline__ __attribute__((always_inline))
+void __wbinvd(void)
+{
+ __asm__ __volatile__ ("wbinvd");
+}
+
+static
+AMDLIB_OPTIMIZE
+__inline__ __attribute__((always_inline))
+void __lidt(void *Source)
+{
+ __asm__ __volatile__("lidt %0" : : "m"(*(short*)Source));
+}
+
+static
+AMDLIB_OPTIMIZE
+__inline__ __attribute__((always_inline))
+void __writefsbyte(const unsigned long Offset, const unsigned char Data)
+{
+ __asm__ ("movb %[Data], %%fs:%a[Offset]"
+ :
+ : [Offset] "ir" (Offset), [Data] "iq" (Data));
+}
+
+static
+AMDLIB_OPTIMIZE
+__inline__ __attribute__((always_inline))
+void __writefsword(const unsigned long Offset, const unsigned short Data)
+{
+ __asm__ ("movw %[Data], %%fs:%a[Offset]"
+ :
+ : [Offset] "ir" (Offset), [Data] "ir" (Data));
+}
+
+static
+AMDLIB_OPTIMIZE
+__inline__ __attribute__((always_inline))
+void __writefsdword(const unsigned long Offset, const unsigned long Data)
+{
+ __asm__ ("movl %[Data], %%fs:%a[Offset]"
+ :
+ : [Offset] "ir" (Offset), [Data] "ir" (Data));
+}
+
+static
+AMDLIB_OPTIMIZE
+__inline__ __attribute__((always_inline))
+unsigned char __readfsbyte(const unsigned long Offset)
+{
+ unsigned char value;
+ __asm__ ("movb %%fs:%a[Offset], %[value]"
+ : [value] "=q" (value)
+ : [Offset] "ir" (Offset));
+ return value;
+}
+
+static
+AMDLIB_OPTIMIZE
+__inline__ __attribute__((always_inline))
+unsigned short __readfsword(const unsigned long Offset)
+{
+ unsigned short value;
+ __asm__ ("movw %%fs:%a[Offset], %[value]"
+ : [value] "=q" (value)
+ : [Offset] "ir" (Offset));
+ return value;
+}
+
+static
+AMDLIB_OPTIMIZE
+__inline__ __attribute__((always_inline))
+unsigned long __readfsdword(unsigned long Offset)
+{
+ unsigned long value;
+ __asm__ ("movl %%fs:%a[Offset], %[value]"
+ : [value] "=r" (value)
+ : [Offset] "ir" (Offset));
+ return value;
+}
+
+#ifdef __SSE3__
+typedef long long __v2di __attribute__ ((__vector_size__ (16)));
+typedef long long __m128i __attribute__ ((__vector_size__ (16), __may_alias__));
+
+static
+AMDLIB_OPTIMIZE
+__inline__ __attribute__((always_inline))
+void _mm_stream_si128_fs2 (void *__A, __m128i __B)
+{
+ __asm__(".byte 0x64"); // fs prefix
+ __builtin_ia32_movntdq ((__v2di *)__A, (__v2di)__B);
+}
+
+static
+AMDLIB_OPTIMIZE
+__inline__ __attribute__((always_inline))
+void _mm_stream_si128_fs (void *__A, void *__B)
+{
+ __m128i data;
+ data = (__m128i) __builtin_ia32_lddqu ((char const *)__B);
+ _mm_stream_si128_fs2 (__A, data);
+}
+
+static
+AMDLIB_OPTIMIZE
+__inline__ __attribute__((always_inline))
+void _mm_clflush_fs (void *__A)
+{
+ __asm__(".byte 0x64"); // fs prefix
+ __builtin_ia32_clflush (__A);
+}
+
+static
+AMDLIB_OPTIMIZE
+__inline__ __attribute__((always_inline))
+void _mm_mfence (void)
+{
+ __builtin_ia32_mfence ();
+}
+
+static
+AMDLIB_OPTIMIZE
+__inline__ __attribute__((always_inline))
+void _mm_sfence (void)
+{
+ __builtin_ia32_sfence ();
+}
+#endif /* __SSE3__ */
+
+static
+AMDLIB_OPTIMIZE
+__inline__ __attribute__((always_inline))
+void __stosb(unsigned char *dest, unsigned char data, size_t count)
+{
+ __asm__ __volatile__ (
+ "rep ; stosb "
+ : "+D" (dest), "+c" (count)
+ : "a"(data)
+ );
+}
+
+static
+AMDLIB_OPTIMIZE
+__inline__ __attribute__((always_inline))
+void __movsb(unsigned char *dest, unsigned char *data, size_t count)
+{
+ __asm__ __volatile__ (
+ "movsb "
+ : "+D" (dest), "+S"(data), "+c" (count)
+ );
+}
+
+static
+AMDLIB_OPTIMIZE
+__inline__ __attribute__((always_inline))
+void debug_point ( unsigned short Port, unsigned long Data )
+{
+ __outdword (Port, Data);
+ __asm__ __volatile__ (".word 0xfeeb");
+
+}
+
+static
+AMDLIB_OPTIMIZE
+__inline__ __attribute__((always_inline))
+void delay_point ( unsigned short Port, unsigned long Data, unsigned long delayTime )
+{
+ UINTN Index;
+ Index = 0;
+ __outdword (Port, Data);
+ while (Index < delayTime * 600000) {
+ __outdword (0xE0, 0);
+ Index ++;
+ }
+}
+#endif /* defined (__GNUC__) */
diff --git a/src/vendorcode/amd/pi/00630F01/binaryPI/gcccar.inc b/src/vendorcode/amd/pi/00630F01/binaryPI/gcccar.inc
new file mode 100644
index 0000000..2707cab
--- /dev/null
+++ b/src/vendorcode/amd/pi/00630F01/binaryPI/gcccar.inc
@@ -0,0 +1,1596 @@
+/*
+ * Copyright (c) 2012, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/******************************************************************************
+* AMD Generic Encapsulated Software Architecture
+*
+* $Workfile:: GccCar.inc $Revision:: 32932 $
+*
+* Description: GccCar.inc - AGESA cache-as-RAM setup Include File for GCC complier
+*
+******************************************************************************/
+
+.altmacro
+
+BSP_STACK_BASE_ADDR = 0x30000 /* Base address for primary cores stack */
+BSP_STACK_SIZE = 0x10000 /* 64KB for BSP core */
+CORE0_STACK_BASE_ADDR = 0x80000 /* Base address for primary cores stack */
+CORE0_STACK_SIZE = 0x4000 /* 16KB for primary cores */
+CORE1_STACK_BASE_ADDR = 0x40000 /* Base address for AP cores */
+CORE1_STACK_SIZE = 0x1000 /* 4KB for each AP cores */
+
+APIC_BASE_ADDRESS = 0x0000001B
+ APIC_BSC = 8 /* Boot Strap Core */
+
+APIC_MSG_REG = 0x380 # Location of BSC message
+ APIC_MSG = 0x00DE00AD # Message data
+APIC_CMD_LO_REG = 0x300 # APIC command low
+APIC_CMD_HI_REG = 0x310 # APIC command high
+ CMD_REG_TO_READ_DATA = 0x00000338 # APIC command for remote read of APIC_MSG_REG
+ REMOTE_READ_STS = 0x00030000 # Remote read status mask
+ REMOTE_DELIVERY_PEND = 0x00010000 # Remote read is pending
+ REMOTE_DELIVERY_DONE = 0x00020000 # Remote read is complete
+ DELIVERY_STS_BIT = 12 #Delivery status valid bit
+APIC_ID_REG = 0x0020 # Local APIC ID offset
+ APIC20_APICID = 24
+APIC_REMOTE_READ_REG = 0x00C0 # Remote read offset
+
+# Flags can only run from bits 31 to 24. Bits 23:0 are in use.
+AMD_CU_NEED_TO_WAIT = 31
+AMD_CU_SEND_INVD_MSG = 30
+AMD_CU_RESTORE_ES = 29
+
+AMD_MTRR_VARIABLE_BASE0 = 0x0200
+AMD_MTRR_VARIABLE_BASE6 = 0x020C
+AMD_MTRR_VARIABLE_BASE7 = 0x020E
+ VMTRR_VALID = 11
+ MTRR_TYPE_WB = 0x06
+ MTRR_TYPE_WP = 0x05
+ MTRR_TYPE_WT = 0x04
+ MTRR_TYPE_UC = 0x00
+AMD_MTRR_VARIABLE_MASK7 = 0x020F
+AMD_MTRR_FIX64k_00000 = 0x0250
+AMD_MTRR_FIX16k_80000 = 0x0258
+AMD_MTRR_FIX16k_A0000 = 0x0259
+AMD_MTRR_FIX4k_C0000 = 0x0268
+AMD_MTRR_FIX4k_C8000 = 0x0269
+AMD_MTRR_FIX4k_D0000 = 0x026A
+AMD_MTRR_FIX4k_D8000 = 0x026B
+AMD_MTRR_FIX4k_E0000 = 0x026C
+AMD_MTRR_FIX4k_E8000 = 0x026D
+AMD_MTRR_FIX4k_F0000 = 0x026E
+AMD_MTRR_FIX4k_F8000 = 0x026F
+
+/* Reproduced from AGESA.h */
+AMD_AP_MTRR_FIX64k_00000 = 0x00000250
+AMD_AP_MTRR_FIX16k_80000 = 0x00000258
+AMD_AP_MTRR_FIX16k_A0000 = 0x00000259
+AMD_AP_MTRR_FIX4k_C0000 = 0x00000268
+AMD_AP_MTRR_FIX4k_C8000 = 0x00000269
+AMD_AP_MTRR_FIX4k_D0000 = 0x0000026A
+AMD_AP_MTRR_FIX4k_D8000 = 0x0000026B
+AMD_AP_MTRR_FIX4k_E0000 = 0x0000026C
+AMD_AP_MTRR_FIX4k_E8000 = 0x0000026D
+AMD_AP_MTRR_FIX4k_F0000 = 0x0000026E
+AMD_AP_MTRR_FIX4k_F8000 = 0x0000026F
+CPU_LIST_TERMINAL = 0xFFFFFFFF
+
+AMD_MTRR_DEFTYPE = 0x02FF
+ WB_DRAM_TYPE = 0x1E /* MemType - memory type */
+ MTRR_DEF_TYPE_EN = 11 /* MtrrDefTypeEn - variable and fixed MTRRs default enabled */
+ MTRR_DEF_TYPE_FIX_EN = 10 /* MtrrDefTypeEn - fixed MTRRs default enabled */
+
+HWCR = 0x0C0010015 /* Hardware Configuration */
+ INVD_WBINVD = 0x04 /* INVD to WBINVD conversion */
+
+IORR_BASE = 0x0C0010016 /* IO Range Regusters Base/Mask, 2 pairs */
+ /* uses 16h - 19h */
+TOP_MEM = 0x0C001001A /* Top of Memory */
+TOP_MEM2 = 0x0C001001D /* Top of Memory2 */
+
+LS_CFG = 0x0C0011020 /* Load-Store Configuration */
+ DIS_SS = 28 /* Family 10h,12h,15h:Disable Streng Store functionality */
+ DIS_STREAM_ST = 28 /* Family 14h:DisStreamSt - Disable Streaming Store functionality */
+
+IC_CFG = 0x0C0011021 /* Instruction Cache Config Register */
+ IC_DIS_SPEC_TLB_RLD = 9 /* Disable speculative TLB reloads */
+ DIS_IND = 14 /* Family 10-14h:Disable Indirect Branch Predictor */
+ DIS_I_CACHE = 14 /* Family 15h:DisICache - Disable Indirect Branch Predictor */
+
+DC_CFG = 0x0C0011022 /* Data Cache Configuration */
+ DC_DIS_SPEC_TLB_RLD = 4 /* Disable speculative TLB reloads */
+ DIS_CLR_WBTOL2_SMC_HIT = 8 /* self modifying code check buffer bit */
+ DIS_HW_PF = 13 /* Hardware prefetches bit */
+
+CU_CFG = 0x0C0011023 /* Family 15h: Combined Unit Configuration */
+ L2_WAY_LOCK_EN = 23 /* L2WayLock - L2 way lock enable */
+ L2_FIRST_LOCKED_WAY = 19 /* L2FirstLockedWay - first L2 way lockedh */
+ L2_FIRST_LOCKED_WAY_OR_MASK = 0x000780000
+
+DE_CFG = 0x0C0011029 /* Decode Configuration */
+ CL_FLUSH_SERIALIZE = 23 /* Family 12h,15h: CL Flush Serialization */
+
+BU_CFG2 = 0x0C001102A /* Family 10h: Bus Unit Configuration 2 */
+CU_CFG2 = 0x0C001102A /* Family 15h: Combined Unit Configuration 2 */
+ F10_CL_LINES_TO_NB_DIS = 15 /* ClLinesToNbDis - allows WP code to be cached in L2 */
+ IC_DIS_SPEC_TLB_WR = 35 /* IcDisSpecTlbWr - ITLB speculative writes */
+
+CU_CFG3 = 0x0C001102B /* Combined Unit Configuration 3 */
+ COMBINE_CR0_CD = 49 /* Combine CR0.CD for both cores of a compute unit */
+
+CR0_PE = 0 # Protection Enable
+CR0_NW = 29 # Not Write-through
+CR0_CD = 30 # Cache Disable
+CR0_PG = 31 # Paging Enable
+
+/* CPUID Functions */
+
+CPUID_MODEL = 1
+AMD_CPUID_FMF = 0x80000001 /* Family Model Features information */
+AMD_CPUID_L2Cache = 0X80000006 /* L2/L3 cache info */
+AMD_CPUID_APIC = 0x80000008 /* Long Mode and APIC info., core count */
+ APIC_ID_CORE_ID_SIZE = 12 /* ApicIdCoreIdSize bit position */
+
+NB_CFG = 0x0C001001F /* Northbridge Configuration Register */
+ INIT_APIC_ID_CPU_ID_LO = 54 /* InitApicIdCpuIdLo - is core# in high or low half of APIC ID? */
+ ENABLE_CF8_EXT_CFG = 46 /* EnableCf8ExtCfg - enable CF8 extended configuration cycles */
+
+MTRR_SYS_CFG = 0x0C0010010 /* System Configuration Register */
+ CHX_TO_DIRTY_DIS = 16 /* ChxToDirtyDis Change to dirty disable */
+ SYS_UC_LOCK_EN = 17 /* SysUcLockEn System lock command enable */
+ MTRR_FIX_DRAM_EN = 18 /* MtrrFixDramEn MTRR fixed RdDram and WrDram attributes enable */
+ MTRR_FIX_DRAM_MOD_EN = 19 /* MtrrFixDramModEn MTRR fixed RdDram and WrDram modification enable */
+ MTRR_VAR_DRAM_EN = 20 /* MtrrVarDramEn MTRR variable DRAM enable */
+ MTRR_TOM2_EN = 21 /* MtrrTom2En MTRR top of memory 2 enable */
+
+PERF_CONTROL3 = 0x0C0010003 /* Performance event control three */
+ PERF_CONTROL3_RESERVE_L = 0x00200000 /* Preserve the reserved bits */
+ PERF_CONTROL3_RESERVE_H = 0x0FCF0 /* Preserve the reserved bits */
+ CONFIG_EVENT_L = 0x0F0E2 /* All cores with level detection */
+ CONFIG_EVENT_H = 4 /* Increment count by number of event */
+ /* occured in clock cycle */
+ EVENT_ENABLE = 22 /* Enable the event */
+PERF_COUNTER3 = 0x0C0010007 /* Performance event counter three */
+
+FUNC_3 = 3
+MCA_NB_CFG = 0x44 /* MCA NB Configuration */
+CPU_ERR_DIS = 6 /* CPU error response disable */
+PRODUCT_INFO_REG1 = 0x1FC /* Product Information Register 1 */
+
+# Local use flags, in upper most byte if ESI
+FLAG_UNKNOWN_FAMILY = 24 # Signals that the family# of the installed processor is not recognized
+FLAG_STACK_REENTRY = 25 # Signals that the environment has made a re-entry (2nd) call to set up the stack
+FLAG_IS_PRIMARY = 26 # Signals that this core is the primary within the comoute unit
+FLAG_CORE_NOT_IDENTIFIED = 27 # Signals that the cores/compute units of the installed processor is not recognized
+FLAG_FORCE_32K_STACK = 28 # Signals that to force 32KB stack size for BSP core
+CR0_MASK = ((1 << CR0_CD) | (1 << CR0_NW))
+MSR_MASK = ((1 << MTRR_DEF_TYPE_EN)+(1 << MTRR_DEF_TYPE_FIX_EN))
+
+/****************************************************************************
+ *
+ * CPU MACROS - PUBLIC
+ *
+ ****************************************************************************/
+.macro _WRMSR
+ .byte 0x0f, 0x30
+.endm
+
+.macro _RDMSR
+ .byte 0x0F, 0x32
+.endm
+
+.macro AMD_CPUID arg0
+ .ifb \arg0
+ mov $0x1, %eax
+ .byte 0x0F, 0x0A2 /* Execute instruction */
+ bswap %eax
+ xchg %ah, %al /* Ext model in al now */
+ rol $0x08, %eax /* Ext model in ah, model in al */
+ and $0x0FFCF, ax /* Keep 23:16, 7:6, 3:0 */
+ .else
+ mov \arg0, %eax
+ .byte 0x0F, 0x0A2
+ .endif
+.endm
+
+.macro MAKE_EXT_PCI_ADDR Seg, Bus, Dev, Func, Offset
+ mov $(1 << 31 | (Seg) << 28 | (((Offset) & (0x0F00)) >> 8) << 24 | (Bus) << 16 | (Dev) << 11 | (Func) << 8) | ((Offset) & (0xFC)), %eax
+.endm
+/****************************************************************************
+*
+* AMD_ENABLE_STACK_FAMILY_HOOK Macro - Stackless
+*
+* Set any family specific controls needed to enable the use of
+* cache as general storage before main memory is available.
+*
+* Inputs:
+* none
+* Outputs:
+* none
+ ****************************************************************************/
+.macro AMD_ENABLE_STACK_FAMILY_HOOK
+
+// AMD_ENABLE_STACK_FAMILY_HOOK_F10
+// AMD_ENABLE_STACK_FAMILY_HOOK_F12
+ AMD_ENABLE_STACK_FAMILY_HOOK_F14
+ AMD_ENABLE_STACK_FAMILY_HOOK_F15
+.endm
+
+/****************************************************************************
+*
+* AMD_DISABLE_STACK_FAMILY_HOOK Macro - Stackless
+*
+* Return any family specific controls to their 'standard'
+* settings for using cache with main memory.
+*
+* Inputs:
+* none
+* Outputs:
+* none
+ ****************************************************************************/
+.macro AMD_DISABLE_STACK_FAMILY_HOOK
+
+ //AMD_DISABLE_STACK_FAMILY_HOOK_F10
+ //AMD_DISABLE_STACK_FAMILY_HOOK_F12
+ AMD_DISABLE_STACK_FAMILY_HOOK_F14
+ AMD_DISABLE_STACK_FAMILY_HOOK_F15
+
+.endm
+
+/****************************************************************************
+*
+* GET_NODE_ID_CORE_ID Macro - Stackless
+*
+* Read family specific values to determine the node and core
+* numbers for the core executing this code.
+*
+* Inputs:
+* none
+* Outputs:
+* SI[7:0] = Core# (0..N, relative to node)
+* SI[15:8]= Node# (0..N)
+* SI[23:16]= reserved
+* SI[24]= flag: 1=Family Unrecognized
+* SI[25]= flag: 1=Interface re-entry call
+* SI[26]= flag: 1=Core is primary of compute unit
+* SI[31:27]= reserved, =0
+****************************************************************************/
+.macro GET_NODE_ID_CORE_ID
+ LOCAL node_core_exit
+
+ mov $-1, %si
+ //GET_NODE_ID_CORE_ID_F10
+ //GET_NODE_ID_CORE_ID_F12
+ //GET_NODE_ID_CORE_ID_F14
+ GET_NODE_ID_CORE_ID_F15
+ /*
+ * Check for unrecognized Family
+ */
+ cmp $-1, %si # Has family (node/core) already been discovered?
+ jnz node_core_exit # Br if yes
+
+ mov $((1 << FLAG_UNKNOWN_FAMILY)+(1 << FLAG_IS_PRIMARY)), %esi # No, Set error code, Only let BSP continue
+
+ mov $APIC_BASE_ADDRESS, %ecx # MSR:0000_001B
+ _RDMSR
+ bt $APIC_BSC, %eax # Is this the BSC?
+ jc node_core_exit # Br if yes
+ hlt # Kill APs
+node_core_exit:
+
+.endm
+
+/****************************************************************************
+## Family 10h MACROS
+##***************************************************************************
+#---------------------------------------------------
+#
+# AMD_ENABLE_STACK_FAMILY_HOOK_F10 Macro - Stackless
+#
+# Set any family specific controls needed to enable the use of
+# cache as general storage before main memory is available.
+#
+# Inputs:
+# ESI - node#, core#, flags from GET_NODE_ID_CORE_ID
+# Outputs:
+# none
+#
+# Family 10h requirements (BKDG section 2.3.3):
+# * Paging disabled
+# * MSRC001_0015[INVDWBINVD]=0
+# * MSRC001_1021[DIS_IND]=1
+# * MSRC001_1021[DIS_SPEC_TLB_RLD]=1
+# * MSRC001_1022[DIS_SPEC_TLB_RLD]=1
+# * MSRC001_1022[DIS_CLR_WBTOL2_SMC_HIT]=1
+# * MSRC001_1022[DIS_HW_PF]=1
+# * MSRC001_102A[IcDisSpecTlbWr]=1
+# * MSRC001_102A[ClLinesToNbDis]=1
+# * No INVD or WBINVD, no exceptions, page faults or interrupts
+****************************************************************************/
+.macro AMD_ENABLE_STACK_FAMILY_HOOK_F10
+ LOCAL fam10_enable_stack_hook_exit
+
+ AMD_CPUID $CPUID_MODEL
+ shr $20, %eax # AL = cpu extended family
+ cmp $0x01, %al # Is this family 10h?
+ jnz fam10_enable_stack_hook_exit # Br if no
+
+ mov $DC_CFG, %ecx # MSR:C001_1022
+ _RDMSR
+ bts $DC_DIS_SPEC_TLB_RLD, %eax # Turn on Disable speculative DTLB reloads bit
+ bts $DIS_CLR_WBTOL2_SMC_HIT, %eax # Turn on Disable the self modifying code check buffer bit
+ bts $DIS_HW_PF, %eax # Turn on Disable hardware prefetches bit
+ _WRMSR
+
+ dec %cx # MSR:C001_1021
+ _RDMSR
+ bts $IC_DIS_SPEC_TLB_RLD, %eax # Turn on Disable speculative TLB reloads bit
+ bts $DIS_IND, %eax # Turn on Disable indirect branch predictor
+ _WRMSR
+
+ mov $BU_CFG2, %ecx # MSR C001_102A
+ _RDMSR
+ bts $F10_CL_LINES_TO_NB_DIS, %eax # Allow BIOS ROM to be cached in the IC
+ bts $(IC_DIS_SPEC_TLB_WR-32), %edx #Disable speculative writes to the ITLB
+ _WRMSR
+
+ mov $HWCR, %ecx # MSR C001_0015
+ _RDMSR
+ bt $FLAG_STACK_REENTRY, %esi # Check if stack has already been set
+ jc fam10_skipClearingBit4
+ btr $INVD_WBINVD, %eax # disable INVD -> WBINVD conversion
+ _WRMSR
+
+fam10_skipClearingBit4:
+ mov %esi, %eax # load core#
+ or %al, %al # If (BSP)
+ jne fam10_enable_stack_hook_exit
+ mov $PERF_COUNTER3, %ecx # Select performance counter three
+ # to count number of CAR evictions
+ xor %eax, %eax # Initialize the lower part of the counter to zero
+ xor %edx, %edx # Initializa the upper part of the counter to zero
+ _WRMSR # Save it
+ mov $PERF_CONTROL3, %ecx # Select the event control three
+ _RDMSR # Get the current setting
+ and $PERF_CONTROL3_RESERVE_L, %eax # Preserve the reserved bits
+ or $CONFIG_EVENT_L, %eax # Set the lower part of event register to
+ # select CAR Corruption occurred by any cores
+ and $PERF_CONTROL3_RESERVE_H, %dx # Preserve the reserved bits
+ or $CONFIG_EVENT_H, %dx # Set the upper part of event register
+ _WRMSR # Save it
+ bts $EVENT_ENABLE, %eax # Enable it
+ _WRMSR # Save it
+
+fam10_enable_stack_hook_exit:
+.endm
+
+/*****************************************************************************
+** Family 14h MACROS
+*****************************************************************************/
+/*****************************************************************************
+*
+* AMD_ENABLE_STACK_FAMILY_HOOK_F14 Macro - Stackless
+*
+* Set any family specific controls needed to enable the use of
+* cache as general storage before main memory is available.
+*
+* Inputs:
+* ESI - node#, core#, flags from GET_NODE_ID_CORE_ID
+* Outputs:
+* none
+*
+* Family 14h requirements (BKDG section 2.3.3):
+* * Paging must be disabled.
+* * MSRC001_0015[INVD_WBINVD]=0.
+* * MSRC001_1020[DisStreamSt]=1.
+* * MSRC001_1021[DIS_SPEC_TLB_RLD]=1. Disable speculative ITLB reloads.
+* * MSRC001_1022[DIS_HW_PF]=1.
+* * No INVD or WBINVD, no exceptions, page faults or interrupts
+*****************************************************************************/
+.macro AMD_ENABLE_STACK_FAMILY_HOOK_F14
+ LOCAL fam14_enable_stack_hook_exit
+
+ AMD_CPUID $CPUID_MODEL
+ shr $20, %eax # AL = cpu extended family
+ cmp $0x05, %al # Is this family 14h?
+ jnz fam14_enable_stack_hook_exit # Br if no
+
+ mov $DC_CFG, %ecx # MSR:C001_1022
+ _RDMSR
+ bts $DIS_HW_PF, %eax # Disable hardware prefetches
+ _WRMSR
+
+ dec %cx #IC_CFG # MSR:C001_1021
+ _RDMSR
+ bts $IC_DIS_SPEC_TLB_RLD, %eax # Disable speculative TLB reloads
+ _WRMSR
+
+ dec %cx #LS_CFG # MSR:C001_1020
+ _RDMSR
+ bts $DIS_STREAM_ST, %eax # Disabled Streaming store functionality
+ _WRMSR
+
+ mov $HWCR, %ecx # MSR C001_0015
+ _RDMSR
+ bt $FLAG_STACK_REENTRY, %esi # Check if stack has already been set
+ jc fam14_skipClearingBit4
+ btr $INVD_WBINVD, %eax # Disable INVD -> WBINVD conversion
+ _WRMSR
+fam14_skipClearingBit4: # Keeping this label
+
+fam14_enable_stack_hook_exit:
+.endm
+
+/*****************************************************************************
+*
+* AMD_DISABLE_STACK_FAMILY_HOOK_F14 Macro - Stackless
+*
+* Return any family specific controls to their 'standard'
+* settings for using cache with main memory.
+*
+* Inputs:
+* ESI - [31:24] flags; [15,8]= Node#; [7,0]= core#
+* Outputs:
+* none
+*
+* Family 14h requirements:
+* * INVD or WBINVD
+* * MSRC001_0015[INVD_WBINVD]=1.
+* * MSRC001_1020[DisStreamSt]=0.
+* * MSRC001_1021[DIS_SPEC_TLB_RLD]=0.
+* * MSRC001_1022[DIS_HW_PF]=0.
+*****************************************************************************/
+.macro AMD_DISABLE_STACK_FAMILY_HOOK_F14
+ LOCAL fam14_disable_stack_hook_exit
+
+ AMD_CPUID $CPUID_MODEL
+ shr $20, %eax # AL = cpu extended family
+ cmp $0x05, %al # Is this family 14h?
+ jnz fam14_disable_stack_hook_exit # Br if no
+
+ mov $LS_CFG, %ecx # MSR:C001_1020
+ _RDMSR
+ btr $DIS_STREAM_ST, %eax # Turn on Streaming store functionality
+ _WRMSR
+
+ inc %cx #IC_CFG # MSR:C001_1021
+ _RDMSR
+ btr $IC_DIS_SPEC_TLB_RLD, %eax # Turn on speculative DC-TLB reloads
+ _WRMSR
+
+ inc %cx #DC_CFG # MSR:C001_1022
+ _RDMSR
+ btr $DIS_HW_PF, %eax # Turn on hardware prefetches
+ _WRMSR
+
+ #--------------------------------------------------------------------------
+ # Begin critical sequence in which EAX, BX, ECX, and EDX must be preserved.
+ #--------------------------------------------------------------------------
+
+ mov $HWCR, %ecx # MSR:C001_0015h
+ _RDMSR
+ btr $INVD_WBINVD, %eax # Disable INVD -> WBINVD conversion
+ _WRMSR
+ invd # Clear the cache tag RAMs
+ bts $INVD_WBINVD, %eax # Turn on Conversion of INVD to WBINVD
+ _WRMSR
+
+ #--------------------------------------------------------------------------
+ # End critical sequence in which EAX, BX, ECX, and EDX must be preserved.
+ #--------------------------------------------------------------------------
+
+fam14_disable_stack_hook_exit:
+.endm
+
+/*****************************************************************************
+*
+* GET_NODE_ID_CORE_ID_F14 Macro - Stackless
+*
+* Read family specific values to determine the node and core
+* numbers for the core executing this code.
+*
+* Inputs:
+* none
+* Outputs:
+* SI = core#, node# & flags (see GET_NODE_ID_CORE_ID macro above)
+*****************************************************************************/
+.macro GET_NODE_ID_CORE_ID_F14
+
+ LOCAL node_core_f14_exit
+
+ cmp $0x-1, %si # Has node/core already been discovered?
+ jnz node_core_f14_exit # Br if yes
+
+ AMD_CPUID $CPUID_MODEL
+ shr $20, %eax # AL = cpu extended family
+ cmp $0x05, %al # Is this family 14h?
+ jnz node_core_f14_exit # Br if no
+
+ xor %esi, %esi # Node must be 0
+ bts $FLAG_IS_PRIMARY, %esi # all family 14h cores are primary
+ mov $APIC_BASE_ADDRESS, %ecx # MSR:0000_001B
+ _RDMSR
+ bt $APIC_BSC, %eax # Is this the BSC?
+ jc node_core_f14_exit # Br if yes
+ inc %si # Set core to 1
+node_core_f14_exit:
+.endm
+
+/*****************************************************************************
+** Family 15h MACROS
+*****************************************************************************/
+/*****************************************************************************
+*
+* AMD_ENABLE_STACK_FAMILY_HOOK_F15 Macro - Stackless
+*
+* Set any family specific controls needed to enable the use of
+* cache as general storage before main memory is available.
+*
+* Inputs:
+* ESI - node#, core#, flags from GET_NODE_ID_CORE_ID
+* Outputs:
+* none
+*
+* Family 15h requirements (BKDG #42301 section 2.3.3):
+* * Paging must be disabled.
+* * MSRC001_0015[INVD_WBINVD]=0
+* * MSRC001_1020[DisSS]=1
+* * MSRC001_1021[DIS_SPEC_TLB_RLD]=1
+* * MSRC001_1022[DIS_SPEC_TLB_RLD]=1
+* * MSRC001_1022[DisHwPf]=1
+* * No INVD or WBINVD, no exceptions, page faults or interrupts
+*****************************************************************************/
+.macro AMD_ENABLE_STACK_FAMILY_HOOK_F15
+ LOCAL fam15_enable_stack_hook_exit
+ GET_NODE_ID_CORE_ID
+ mov %esi, %eax
+ bt $FLAG_IS_PRIMARY, %eax # Is this a 2nd entry?
+ jnc 1f
+ MAKE_EXT_PCI_ADDR 0, 0, 24, FUNC_3, 0x44 //MCA_NB_CFG
+ mov $0xCF8, %dx
+ out %eax, %dx
+ add $4, %dx
+ in %dx, %eax
+ bts $CPU_ERR_DIS, %eax
+ out %eax, %dx
+1:
+ AMD_CPUID $CPUID_MODEL
+ mov %eax, %ebx # Save revision info to EBX
+ shr $20, %eax # AL = cpu extended family
+ cmp $0x06, %al # Is this family 15h?
+ jnz fam15_enable_stack_hook_exit # Br if no
+
+ bt $FLAG_STACK_REENTRY , %esi # Check if stack has already been set
+ jc fam15_skipClearingBit4
+ mov $HWCR, %ecx # MSR C001_0015
+ _RDMSR
+ btr $INVD_WBINVD, %eax # disable INVD -> WBINVD conversion
+ _WRMSR
+
+fam15_skipClearingBit4:
+ mov $LS_CFG, %ecx # MSR:C001_1020
+ _RDMSR
+ bts $DIS_SS, %eax # Turn on Streaming store functionality disabled bit
+ _WRMSR
+
+ inc %ecx #IC_CFG # MSR:C001_1021
+ _RDMSR
+ bts $IC_DIS_SPEC_TLB_RLD, %eax # Turn on Disable speculative IC-TLB reloads bit
+ _WRMSR
+
+ //mov %ebx, %eax # Restore revision info to EAX
+ //shr $16, %eax
+ //and $0x0F, %al # AL = cpu extended model
+
+ inc %ecx #DC_CFG # MSR:C001_1022
+ _RDMSR
+ bts $DC_DIS_SPEC_TLB_RLD, %eax # Turn on Disable speculative DC-TLB reloads bit
+ bts $DIS_HW_PF, %eax # Turn on Disable hardware prefetches bit
+ _WRMSR # Remove KM in PI 1.1.0.0
+
+ mov %ebx, %eax # Restore revision info to EAX
+ shr $16, %eax
+ and $0xF, %al
+ #.if (al == 01h) Is this TN or KV?
+ cmp $1, %eax
+ jz 1f
+ cmp $3, %eax
+ jz 3f # Skip if it is KV, it is only for TN from Label 1 to 3
+ jmp 2f
+1: #.if (al == 01h) # TN only
+ #Enable MSRC001_001F[EnableCf8ExtCfg]
+ mov $NB_CFG, %ecx # MSR:C001_001F
+ _rdmsr
+ bts $(ENABLE_CF8_EXT_CFG - 32), %edx
+ _wrmsr
+ # Set F3x44[6, CpuErrDis] = 1
+// MAKE_EXT_PCI_ADDR 0, 0, 24, FUNC_3, 0x44 //MCA_NB_CFG
+ //mov $(1 << 31 | 2 << 28 | (((MCA_NB_CFG) & (0x0F00)) >> 8) << 24 | 2 << 16 | 1 << 11 | FUNC_3 << 8), %eax
+
+// mov $0xCF8, %dx
+// out %eax, %dx
+// add $4, %dx
+// in %dx, %eax
+// bts $CPU_ERR_DIS, %eax
+// out %eax, %dx
+
+3:
+// MAKE_EXT_PCI_ADDR 0, 0, 24, FUNC_3, 0x44 //MCA_NB_CFG
+// mov $0xCF8, %dx
+// out %eax, %dx
+// add $4, %dx
+// in %dx, %eax
+// bts $CPU_ERR_DIS, %eax
+// out %eax, %dx
+
+ mov $CU_CFG, %ecx # TN or KV
+ _RDMSR
+ bt $L2_WAY_LOCK_EN, %eax
+ #.if (!carry?)
+ jc 2f
+ bts $L2_WAY_LOCK_EN, %eax
+ or $L2_FIRST_LOCKED_WAY_OR_MASK, %eax
+ _WRMSR
+ #.endif
+ #.endif
+2:
+ mov %ebx, %eax # Restore revision info to EAX
+ xchg %ah, %al
+ shr $8, %eax
+ //and $0xF, %al
+ #.if (ax == 6100h) ; Is this TN-A0?
+ cmp $0x6100, %ax
+ jnz 2f
+ MAKE_EXT_PCI_ADDR 0, 0, 24, FUNC_3, PRODUCT_INFO_REG1
+ mov $0xCF8, %dx
+ out %eax, %dx
+ add $4, %dx
+ in %dx, %eax
+ bt $21, %eax
+ jc 2f
+ mov $CU_CFG2, %ecx #MSR:C001_102A
+ _RDMSR
+ bts $8, %eax
+ _WRMSR
+ # .endif
+
+2: # Do Standard Family 15 work
+
+ mov $CU_CFG3, %ecx # MSR:C001_102B
+ _RDMSR
+ btr $(COMBINE_CR0_CD - 32), %edx # Clear CombineCr0Cd bit
+ _WRMSR
+
+fam15_enable_stack_hook_exit:
+.endm
+
+/*****************************************************************************
+*
+* AMD_DISABLE_STACK_FAMILY_HOOK_F15 Macro - Stackless
+*
+* Return any family specific controls to their 'standard'
+* settings for using cache with main memory.
+*
+* Inputs:
+* ESI - [31:24] flags; [15,8]= Node#; [7,0]= core#
+* Outputs:
+* none
+*
+* Family 15h requirements:
+* * INVD or WBINVD
+* * MSRC001_0015[INVD_WBINVD]=1
+* * MSRC001_1020[DisSS]=0
+* * MSRC001_1021[DIS_SPEC_TLB_RLD]=0
+* * MSRC001_1022[DIS_SPEC_TLB_RLD]=0
+* * MSRC001_1022[DIS_HW_PF]=0
+*****************************************************************************/
+.macro AMD_DISABLE_STACK_FAMILY_HOOK_F15
+ LOCAL fam15_disable_stack_hook_exit
+ LOCAL fam15_disable_stack_remote_read_exit
+
+ AMD_CPUID $CPUID_MODEL
+ mov %eax, %ebx # Save revision info to EBX
+ shr $20, %eax # AL = cpu extended family
+ cmp $0x06, %al # Is this family 15h?
+ jnz fam15_disable_stack_hook_exit # Br if no
+
+ mov %ebx, %edi # Save revision info to EDI
+ AMD_CPUID $AMD_CPUID_APIC
+ mov %cl, %al # AL = number of cores - 1
+ shr $APIC_ID_CORE_ID_SIZE, %cx # CL = ApicIdCoreIdSize
+ mov $1, %bx
+ shl %cl, %bl # BL = theoretical number of cores on socket
+ dec %bx # BL = core number on socket mask
+ mov %bl, %ah # AH = core number on socket mask
+ mov %edi, %ebx # Restore revision info to EBX
+ mov %ax, %di # DI[15:8] = core number mask, DI[7:0] = number of cores - 1
+
+ and $0x0F00FF, %ebx
+ mov %ebx, %eax
+ shr $8, %eax
+ or %ax, %bx # Save Extended Model, Model and Stepping to BX
+ # [11:8] = Extended Model, [7:4] = Model, [3:0] = Stepping (bx=0000000000010100, ok)
+
+ mov $APIC_BASE_ADDRESS, %ecx
+ _RDMSR # dx=0 ax=fee00800
+ mov %bx, %dx # Save Extended Model, Model and Stepping to DX
+ shl $16, %edx #EDX[31:16] = Extended Model, Model and Stepping
+ mov %eax ,%ebx # EBX = LAPIC base
+ xor %ecx ,%ecx # Zero out CU flags
+ bts $AMD_CU_NEED_TO_WAIT, %ecx # Default to waiting
+ bts $AMD_CU_SEND_INVD_MSG, %ecx # Default to signaling
+ mov %cr0, %eax
+ bt $CR0_PE, %ax # Are we in protected mode?
+ # .if (!carry?)
+ jc 1f
+ bts $AMD_CU_RESTORE_ES, %ecx # Indicate ES restore is required
+ mov %es, %cx # Save ES segment register to CX
+ xor %ax, %ax
+ mov %ax, %es # Set ES to big real mode selector for 4GB access
+ # .endif
+
+1:
+ and $0x0F000, %bx # EBX = LAPIC base, offset 0
+ or $APIC_ID_REG, %bl #
+ mov %es:(%ebx), %eax # EAX[31:24] = APIC ID
+ shr $APIC20_APICID, %eax # AL = APIC ID
+ mov %al, %ah # AH = APIC ID
+ mov %di, %dx # DH = core mask
+ and %dh, %ah # AH = core number # ax=111 dx=01000F03
+
+ # .if (zero?)
+ jnz 1f
+ # Core 0 of a socket
+ btr $AMD_CU_SEND_INVD_MSG, %ecx # No need to signal after INVD
+ #.if (dl != 0)
+ cmp $0, %dl
+ jz 2f
+ # This socket has multiple cores
+ and $0xf000, %bx # EBX = LAPIC base, offset 0
+ or $APIC_MSG_REG, %bx
+ mov $APIC_MSG, %edi
+ mov %edi, %es:(%ebx) # Signal for non core 0s to complete CAR breakdown
+ jmp 1f
+ #.else
+2: btr $AMD_CU_NEED_TO_WAIT, %ecx # No need to wait on a single core CPU
+ #.endif
+ # .endif
+1:
+
+ bt $AMD_CU_NEED_TO_WAIT, %ecx #cx = c0000000
+ #.if (carry?)
+ jnc 1f
+ #.if (ah == dl)
+ cmp %dl, %ah
+ jnz 2f
+ # This is the highest numbered core on this socket -- wait on core 0
+ not %dh # Flip the mask to determine local core 0's APID ID
+ and %dh, %al # AL = target APIC ID # ax=310
+ jmp 3f
+2: #.else
+ # All other cores (including core 0) wait on the next highest core.
+ # In this way, cores will halt in a cascading fashion down to 0.
+ inc %al
+ #.endif
+3:
+ shl $APIC20_APICID, %eax
+ and $0x0F000, %bx
+ or $APIC_CMD_HI_REG, %bx
+ mov %eax, %es:(%ebx) # Set target APIC ID
+
+ # Use bits 23:16 as a timeout for unresponsive cores
+ ror $8, %ecx
+ mov $0xFF, %ch
+ stc
+
+ #.while (carry?)
+5: jnc 4f
+ and $0xF000, %bx #EBX = LAPIC base, offset 0
+ or $APIC_CMD_LO_REG, %bx # bx = 00000000FEE00300
+ mov $CMD_REG_TO_READ_DATA, %eax
+ mov %eax, %es:(%ebx) #Fire remove read IPI
+ inc %ch #Pre increment the timeout
+ stc
+ #.while (carry?)
+7: jnc 6f
+ dec %ch #Check the timeout
+ jz fam15_disable_stack_remote_read_exit
+ mov %es:(%ebx), %eax # ax = 0000000000020338
+ bt $DELIVERY_STS_BIT, %eax
+ jmp 7b
+6: #.endw
+ stc
+ #.while (carry?)
+7: jnc 6f
+ mov %es:(%ebx), %eax
+ and $REMOTE_READ_STS, %eax
+ #.if (eax == REMOTE_DELIVERY_PEND)
+ cmp $REMOTE_DELIVERY_PEND, %eax
+ jnz 8f
+ dec %ch # Check the timeout
+ jz fam15_disable_stack_hook_exit # Branch if there is an unreponsive core
+ stc
+ jmp 9f
+8: #.else
+ clc
+9: #.endif
+ jmp 7b
+6: #.endw
+ #.if (eax == REMOTE_DELIVERY_DONE)
+ cmp $REMOTE_DELIVERY_DONE, %eax
+ jnz 6f
+ and $0x0F000, %bx #EBX = LAPIC base, offset 0
+ or $APIC_REMOTE_READ_REG, %bl
+ mov %es:(%ebx), %eax
+ #.if (eax == APIC_MSG)
+ cmp $APIC_MSG, %eax # ax=00000000FFC5BBB2
+ jnz 8f
+ clc
+ jmp 9f
+ #.else
+8: stc
+9: #.endif
+ jmp 7f
+6: #.else
+ dec %ch
+ jz fam15_disable_stack_remote_read_exit
+ stc
+7: #.endif
+ jmp 5b
+4: #.endw
+
+fam15_disable_stack_remote_read_exit:
+ rol $8, %ecx # Restore ECX
+
+1: #.endif
+
+ bt $AMD_CU_RESTORE_ES, %ecx
+ #.if (carry?)
+ jnc 1f
+ mov %cx, %es
+1:
+ mov %ecx, %edi
+ shr $16, %edx
+ mov %dx, %bx
+
+ #Handshaking complete. Continue tearing down CAR.
+
+ mov $LS_CFG, %ecx # MSR:C001_1020
+ _RDMSR
+ btr $DIS_SS, %eax # Turn on Streaming store functionality
+ _WRMSR
+
+ inc %ecx #IC_CFG # MSR:C001_1021
+ _RDMSR
+ btr $IC_DIS_SPEC_TLB_RLD, %eax # Turn on speculative TLB reloads
+ _WRMSR
+
+ inc %ecx #DC_CFG # MSR:C001_1022
+ _RDMSR
+ btr $DC_DIS_SPEC_TLB_RLD, %eax # Turn on speculative TLB reloads
+ btr $DIS_HW_PF, %eax # Turn on hardware prefetches
+ _WRMSR
+ #--------------------------------------------------------------------------
+ # Begin critical sequence in which EAX, BX, ECX, and EDX must be preserved.
+ #--------------------------------------------------------------------------
+
+ mov $HWCR, %ecx # MSR:C001_0015h
+ _RDMSR
+ btr $INVD_WBINVD, %eax # Disable INVD -> WBINVD conversion
+ _WRMSR
+ wbinvd # Clear the cache tag RAMs
+ #.if (bh == 01h) || (bh == 03h) ; Is this TN or KV?
+ cmp $01, %bh
+ jz 4f
+ cmp $03, %bh
+ jnz 1f
+4: mov $CU_CFG, %ecx # MSR:C001_1023
+ _RDMSR
+ shr $L2_FIRST_LOCKED_WAY, %eax
+ and $0x1F, %eax
+ #.if (eax == 01Fh)
+ cmp $0x1F, %eax #Check if way 15 of the L2 needs to be reserved
+ jnz 3f
+ _RDMSR
+ btr $L2_WAY_LOCK_EN, %eax
+ _WRMSR
+3: #.endif
+
+1: #.endif
+ #Do Standard Family 15 work
+ mov $HWCR, %ecx # MSR:C001_0015h
+ _RDMSR
+ bts $INVD_WBINVD, %eax # Turn on Conversion of INVD to WBINVD
+ _WRMSR
+ #.endif # end
+ 0:
+//
+// #--------------------------------------------------------------------------
+// # End critical sequence in which EAX, BX, ECX, and EDX must be preserved.
+// #--------------------------------------------------------------------------
+//
+ mov $CU_CFG3, %ecx # MSR:C001_102B
+ _RDMSR
+ bts $(COMBINE_CR0_CD - 32), %edx # Set CombineCr0Cd bit
+ _WRMSR
+
+ bt $AMD_CU_SEND_INVD_MSG, %edi
+ #.if (carry?)
+ jnc 1f
+ # Non core zero needs to signal to core 0 to proceed
+ mov $APIC_BASE_ADDRESS, %ecx
+ _RDMSR
+ mov %eax, %ebx # EBX = LAPIC base
+ and $0x0F000, %bx # EBX = LAPIC base, offset 0
+ or $APIC_MSG_REG, %bx
+ mov $APIC_MSG, %eax
+ mov %eax, %es:(%ebx) # Signal for core 0 to complete CAR breakdown
+
+1: #.endif
+
+fam15_disable_stack_hook_exit:
+.endm
+
+/*****************************************************************************
+*
+* GET_NODE_ID_CORE_ID_F15 Macro - Stackless
+*
+* Read family specific values to determine the node and core
+* numbers for the core executing this code.
+*
+* Inputs:
+* none
+* Outputs:
+* SI = core#, node# & flags (see GET_NODE_ID_CORE_ID macro above)
+*****************************************************************************/
+.macro GET_NODE_ID_CORE_ID_F15
+
+ LOCAL node_core_f15_exit
+ LOCAL node_core_f15_AP
+ LOCAL node_core_f15_shared
+ LOCAL node_core_f15_AP_not_TN
+
+#define F15_L2Size 512
+#define F15_ShareCores 2
+#define F15_AllocMem 0
+#define F15_AllocExe 0
+#define F15_SzAddrBus 48
+#define F15_pad 0
+ cmp $-1, %si # Has node/core already been discovered?
+ jnz node_core_f15_exit # Br if yes
+
+ AMD_CPUID $CPUID_MODEL
+ shr $12, %eax # AL = cpu extended family
+ cmp $06, %ah # Is this family 15h?
+ jnz node_core_f15_exit # Br if no
+ shr $4, %al # AL = cpu extended model
+ shr $16, %ebx # BH = LocalApicId
+ mov %al, %bl # BL = cpu extended model
+
+ # LoadTableAddress(FAM15H_INFO_STRUCT)
+ # movd mm5, eax # load pointer to Family Info Struc
+
+ xor %esi, %esi # Assume BSC, clear local flags
+ mov $APIC_BASE_ADDRESS, %ecx # MSR:0000_001B
+ _RDMSR
+ bt $APIC_BSC, %eax # Is this the BSC?
+ jnc node_core_f15_AP # Br if no
+
+ # This is the BSP.
+ # Enable routing tables on BSP (just in case the HT init code has not yet enabled them)
+ mov $0x8000C06C, %eax # PCI address for D18F0x6C Link Initialization Control Register
+ mov $0x0CF8, %dx
+ out %eax, %dx
+ add $4, %dx
+ in %dx, %eax
+ btr $0, %eax # Set LinkInitializationControl[RouteTblDis] = 0
+ out %eax, %dx
+ jmp node_core_f15_shared #
+
+node_core_f15_AP:
+ mov %bl, %al # AL = cpu extended model
+ shr $8, %bx # BL = CPUID Fn0000_0001_EBX[LocalApicId]
+// cmp $1, %al # Is This TN?
+// jz 4f
+// cmp $3, %al
+// jnz node_core_f15_AP_not_TN
+4: mov %bx, %si
+ jmp node_core_f15_shared
+ #
+ # This is an AP. Routing tables have been enabled by the HT Init process.
+ # Also, the MailBox register was set by the BSP during early init
+ # The Mailbox register content is formatted as follows:
+ # UINT32 Node:4; // The node id of Core's node.
+ # UINT32 Socket:4; // The socket of this Core's node.
+ # UINT32 Module:2; // The internal module number for Core's node.
+ # UINT32 ModuleType:2; // Single Module = 0, Multi-module = 1.
+ # UINT32 :20; // Reserved
+ #
+node_core_f15_AP_not_TN:
+// mov $0x0C0000408, %ecx # Read the family 15h mailbox
+// _RDMSR # MC4_MISC1[63:32]
+// mov %dx, %si # SI = raw mailbox contents (will extract node# from this)
+// shr $24, %ebx # BL = CPUID Fn0000_0001_EBX[LocalApicId]
+// mov %bx, %di # DI = Initial APIC ID (will extract core# from this)
+//
+// AMD_CPUID $AMD_CPUID_APIC #
+// shr $4, %ch # CH = ApicIdSize, #bits in APIC ID that show core#
+// inc %cl # CL = Number of enabled cores in the socket
+// mov %cx, %bx
+//
+// mov $NB_CFG, %ecx
+// _RDMSR # EDX has InitApicIdCpuIdLo bit
+//
+// mov %bh, %cl # CL = APIC ID size
+// mov $1, %al # Convert APIC ID size to an AND mask
+// shl %cl, %al # AL = 2^APIC ID size
+// dec %al # AL = mask for relative core number
+// xor %ah, %ah # AX = mask for relative core number
+// bt $(INIT_APIC_ID_CPU_ID_LO-32), %edx # InitApicIdCpuIdLo == 1?
+// #.if (!carry?) # Br if yes
+// jc 0f
+// mov $8, %ch # Calculate core number shift count
+// sub %cl, %ch # CH = core shift count
+// mov %ch, %cl
+// shr %cl, %di # Right justify core number
+// #.endif
+// 0:
+// and %ax, %di # DI = socket-relative core number
+//
+// mov %si, %cx # CX = raw mailbox value
+// shr $10, %cx # CL[1:0] = ModuleType or #nodes per socket (0-SCM, 1-MCM)
+// and $3, %cl # Isolate ModuleType
+// xor %bh, %bh # BX = Number of enabled cores in the socket
+// shr %cl, %bx # BX = Number of enabled cores per node
+// xor %dx, %dx # Clear upper word for div
+// mov %di, %ax # AX = socket-relative core number
+// div %bx # DX = node-relative core number
+// movzx %si, %eax # Prepare return value
+// and $0x000F, %ax # AX = node number
+// shl $8,%ax # [15:8]=node#
+// mov %dl, %al # [7:0]=core# (relative to node)
+// mov %eax, %esi # ESI = node-relative core number
+
+ #
+ # determine if this core shares MTRRs
+ #
+node_core_f15_shared:
+ mov $0x8000C580, %eax # Compute Unit Status
+ mov %si, %bx
+ shl $3, %bh # Move node# to PCI Dev# field
+ add %bh, %ah # Adjust for node number
+ mov $0x0CF8, %dx
+ out %eax, %dx
+ add $4, %dx
+ in %dx, %eax # [3:0]=Enabled# [19:16]=DualCore
+
+ # BL is MyCore#
+ mov $0x06, %cx # Use CH as 'first of pair' core#
+ #.while (cl > 0)
+ jmp 0f
+ 8:
+ bt $0, %eax # Is pair enabled?
+ #.if (carry?) #
+ jnc 1f
+ mov $0x01, %bh # flag core as primary
+ bt $16, %eax # Is there a 2nd in the pair?
+ #.if (carry?) #
+ jnc 4f
+ #.break .if (ch == bl) # Does 1st match MyCore#?
+ cmp %bl, %ch
+ je 9f
+ inc %ch
+ xor %bh, %bh # flag core as NOT primary
+ #.break .if (ch == bl) # Does 2nd match MyCore#?
+ cmp %bl, %ch
+ je 9f
+ jmp 2f
+ #.else # No 2nd core
+ 4:
+ #.break .if (ch == bl) # Does 1st match MyCore#?
+ cmp %bl, %ch
+ je 9f
+ #.endif
+ 2:
+ inc %ch
+ #.endif
+ 1:
+ shr $1, %eax
+ dec %cl
+ #.endw
+ 0:
+ #.if (cl == 0)
+ cmp $0x0, %cl
+ ja 8b
+ 9:
+ or %cl, %cl
+ jne 1f
+ #Error - core# didn't match Compute Unit Status content
+ bts $FLAG_CORE_NOT_IDENTIFIED, %esi
+ bts $FLAG_IS_PRIMARY, %esi # Set Is_Primary for unknowns
+ #.endif
+ 1:
+ #.if (bh != 0) # Check state of primary for the matched core
+ or %bh, %bh
+ je 2f
+ bts $FLAG_IS_PRIMARY, %esi # Set shared flag into return value
+ #.endif
+ 2:
+
+node_core_f15_exit:
+
+.endm
+
+/*****************************************************************************
+* AMD_ENABLE_STACK: Setup a stack
+*
+* In:
+* EBX = Return address (preserved)
+*
+* Out:
+* SS:ESP - Our new private stack location
+*
+* EAX = AGESA_STATUS
+*
+* ECX = Stack size in bytes
+*
+* Requirements:
+* * This routine presently is limited to a max of 64 processor cores
+* Preserved:
+* ebx ebp
+* Destroyed:
+* eax, ecx, edx, edi, esi, ds, es, ss, esp
+* mmx0, mmx1
+*
+* Description:
+* Fixed MTRR address allocation to cores:
+* The BSP gets 64K of stack, Core0 of each node gets 16K of stack, all other cores get 4K.
+* There is a max of 1 BSP, 7 core0s and 56 other cores.
+* Although each core has it's own cache storage, they share the address space. Each core must
+* be assigned a private and unique address space for its stack. To support legacy systems,
+* the stack needs to be within the legacy address space (1st 1Meg). Room must also be reserved
+* for the other legacy elements (Interrupt vectors, BIOS ROM, video buffer, etc.)
+*
+* 80000h 40000h 00000h
+* +----------+----------+----------+----------+----------+----------+----------+----------+
+* 64K | | | | | | | | | 64K ea
+* ea +----------+----------+----------+----------+----------+----------+----------+----------+
+* | MTRR 0000_0250 MTRRfix64K_00000 |
+* +----------+----------+----------+----------+----------+----------+----------+----------+
+* | 7 , 6 | 5 , 4 | 3 , 2 | 1 , 0 | 0 | | | | <-node
+* |7..1,7..1 |7..1,7..1 |7..1,7..1 |7..1,7..1 | 0 | | | | <-core
+* +----------+----------+----------+----------+----------+----------+----------+----------+
+*
+* C0000h B0000h A0000h 90000h 80000h
+* +------+------+------+------+------+------+------+------+------+------+------+------+------+------+------+------+
+*16K | | | | | | | | | | | | | | | | |
+* ea +------+------+------+------+------+------+------+------+------+------+------+------+------+------+------+------+
+* | MTRR 0259 MTRRfix16K_A0000 | MTRR 0258 MTRRfix16K_80000 |
+* +------+------+------+------+------+------+------+------+------+------+------+------+------+------+------+------+
+* | > Dis|play B|uffer | < | | | | | 7 | 6 | 5 | 4 | 3 | 2 | 1 | | <-node
+* | > T| e m |p o r |a r y | B u |f f e |r A |r e a<| 0 | 0 | 0 | 0 | 0 | 0 | 0 | | <-core
+* +------+------+------+------+------+------+------+------+------+------+------+------+------+------+------+------+
+*
+* E0000h D0000h C0000h
+* +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
+* 4K | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 4K ea
+* ea +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
+* | 026B MTRRfix4K_D8000 | 026A MTRRfix4K_D0000 | 0269 MTRRfix4K_C8000 | 0268 MTRRfix4K_C0000 |
+* +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
+* | | | | | | | | | | | | | | | | | >| V| I| D| E| O| |B |I |O |S | |A |r |e |a<|
+* +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
+*
+* 100000h F0000h E0000h
+* +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
+* | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 4K ea
+* +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
+* | 026F MTRRfix4K_F8000 | 026E MTRRfix4K_F0000 | 026D MTRRfix4K_E8000 | 026C MTRRfix4K_E0000 |
+* +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
+* | >|MA|IN| B|IO|S |RA|NG|E | | | | | | |< | >|EX|TE|ND|ED| B|IO|S |ZO|NE| | | | | |< |
+* +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
+*****************************************************************************/
+.macro AMD_ENABLE_STACK
+
+# These are local labels. Declared so linker doesn't cause 'redefined label' errors
+ LOCAL SetupStack
+ LOCAL Real16bMode
+ LOCAL Protected32Mode
+ LOCAL ClearTheStack
+
+# Note that SS:ESP will be default stack. Note that this stack
+# routine will not be used after memory has been initialized. Because
+# of its limited lifetime, it will not conflict with typical PCI devices.
+ movd %ebx, %mm0 # Put return address in a safe place
+ movd %ebp, %mm1 # Save some other user registers
+
+ # get node id and core id of current executing core
+ GET_NODE_ID_CORE_ID # Sets ESI[23:16]=Shared core## SI[15,8]= Node## SI[7,0]= core# (relative to node)
+ # Note: ESI[31:24] are used for flags: Unrecognized Family, Is_Primary core, Stack already established
+
+ # determine if stack is already enabled. We are using the DefType MSR for this determination.
+ # It is =0 after reset; CAR setup sets it to enable the MTRRs
+ mov %cr0, %eax
+ test $CR0_MASK, %eax # Is cache disabled? (CD & NW bits)
+ jnz SetupStack # Jump if yes
+ mov $AMD_MTRR_DEFTYPE, %ecx # MSR:0000_02FF
+ _RDMSR
+ test $MSR_MASK, %eax # Are the default types enabled? (MTRR_DEF_TYPE_EN + MTRR_DEF_TYPE_FIX_EN)
+ jz SetupStack # Jump if no
+ or $FLAG_STACK_REENTRY, %esi # Bit25, indicate stack has already been initialized
+
+SetupStack:
+ # Set node to map the first 16MB to node 0# 0000_0000 to 00FF_FFFF as DRAM
+ mov %esi, %ebx # Get my Node/Core info
+ xor %bl, %bl
+ shl $3, %bh # Isolate my node#, match alignment for PCI Dev#
+ mov $0x8000C144, %eax # D18F1x44:DRAM Base/Limit# N is Base, N+4 is Limit
+ add %bh, %ah
+ mov %eax, %ebx # Save PCI address for Base/Limit pair
+
+ mov $0x0CF8, %dx
+ out %eax, %dx
+ add $4, %dx
+ xor %eax, %eax # Least Significant bit is AD24 so 0 sets mask of 00FF_FFFF (16MB)
+ out %eax, %dx # DRAM Limit = node0, no interleave
+
+ mov %ebx, %eax
+ sub $4, %eax # Now point to the Base register
+ mov $0x0CF8, %dx
+ out %eax, %dx
+ add $4, %dx
+ mov $0x00000003, %eax # Set the read and write enable bits
+ out %eax, %dx # DRAM Base = 0x0000, R/W
+
+ AMD_ENABLE_STACK_FAMILY_HOOK
+
+ # Init CPU MSRs for our init routines
+ mov $MTRR_SYS_CFG, %ecx # SYS_CFG
+ _RDMSR
+ bts $MTRR_FIX_DRAM_MOD_EN, %eax # Turn on modification enable bit
+ _WRMSR
+
+ mov %esi, %eax
+ bt $FLAG_STACK_REENTRY, %eax # Is this a 2nd entry?
+ #.if (!carry?) # On a re-entry, do not clear MTRRs or reset TOM; just reset the stack SS:ESP
+ jc 0f
+ bt $FLAG_IS_PRIMARY, %eax # Is this core the primary in a compute unit?
+ #.if (carry?) # Families using shared groups do not need to clear the MTRRs since that is done at power-on reset
+ # Note: Relying on MSRs to be cleared to 0's at reset for families w/shared cores
+ # Clear all variable and Fixed MTRRs for non-shared cores
+ jnc 0f
+ mov $AMD_MTRR_VARIABLE_BASE0, %ecx
+ xor %eax, %eax
+ xor %edx, %edx
+ #.while (cl != 10h) # Variable MTRRphysBase[n] and MTRRphysMask[n]
+ jmp 1f
+ 2:
+ _WRMSR
+ inc %cl
+ #.endw
+ 1:
+ cmp $0x10, %cl
+ jne 2b
+ mov $AMD_MTRR_FIX64k_00000, %cx # MSR:0000_0250
+ _WRMSR
+ mov $AMD_MTRR_FIX16k_80000, %cx # MSR:0000_0258
+ _WRMSR
+ mov $AMD_MTRR_FIX16k_A0000, %cx # MSR:0000_0259
+ _WRMSR
+ mov $AMD_MTRR_FIX4k_C0000, %cx # Fixed 4Ks: MTRRfix4K_C0000 to MTRRfix4K_F8000
+ #.while (cl != 70h)
+ jmp 3f
+ 4:
+ _WRMSR
+ inc %cl
+ #.endw
+ 3:
+ cmp $0x70, %cl
+ jne 4b
+ # Set TOP_MEM (C001_001A) for non-shared cores to 16M. This will be increased at heap init.
+ # - not strictly needed since the FixedMTRRs take presedence.
+ mov $(16 * 1024 * 1024), %eax
+ mov $TOP_MEM, %ecx # MSR:C001_001A
+ _WRMSR
+ #.endif # End Is_Primary
+ #.endif # End Stack_ReEntry
+ 0:
+ # Clear IORRs (C001_0016-19) and TOM2(C001_001D) for all cores
+ xor %eax, %eax
+ xor %edx, %edx
+ mov $IORR_BASE, %ecx # MSR:C001_0016 - 0019
+ #.while (cl != 1Ah)
+ jmp 1f
+ 2:
+ _WRMSR
+ inc %cl
+ #.endw
+ 1:
+ cmp $0x1A, %cl
+ jne 2b
+ mov $TOP_MEM2, %ecx # MSR:C001_001D
+ _WRMSR
+
+ # setup MTTRs for stacks
+ # A speculative read can be generated by a speculative fetch mis-aligned in a code zone
+ # or due to a data zone being interpreted as code. When a speculative read occurs outside a
+ # controlled region (intentionally used by software), it could cause an unwanted cache eviction.
+ # To prevent speculative reads from causing an eviction, the unused cache ranges are set
+ # to UC type. Only the actively used regions (stack, heap) are reflected in the MTRRs.
+ # Note: some core stack regions will share an MTRR since the control granularity is much
+ # larger than the allocated stack zone. The allocation algorithm must account for this 'extra'
+ # space covered by the MTRR when parseling out cache space for the various uses. In some cases
+ # this could reduce the amount of EXE cache available to a core. see cpuCacheInit.c
+ #
+ # Outcome of this block is that: (Note the MTRR map at the top of the file)
+ # ebp - start address of stack block
+ # ebx - [31:16] - MTRR MSR address
+ # - [15:8] - slot# in MTRR register
+ # - [7:0] - block size in #4K blocks
+ # review: ESI[31:24]=Flags; SI[15,8]= Node#; SI[7,0]= core# (relative to node)
+ #
+
+ mov %si, %ax # Load node, core
+ #.if (al == 0) # Is a core 0?
+ or %al, %al
+ jne 1f
+ #.if (ah == 0) # Is Node 0? (BSP)
+ or %ah, %ah
+ jne 2f
+ # Is BSP, assign a 64K stack
+ mov $((AMD_MTRR_FIX64k_00000 << 16) + (3 << 8) + (BSP_STACK_SIZE >> 12)), %ebx
+ mov $BSP_STACK_BASE_ADDR, %ebp
+ jmp 0f
+ #.else # node 1 to 7, core0
+ 2:
+ # Is a Core0 of secondary node, assign 16K stacks
+ mov $AMD_MTRR_FIX16k_80000, %bx
+ shl $16, %ebx #
+ mov %ah, %bh # Node# is used as slot#
+ mov $(CORE0_STACK_SIZE >> 12), %bl
+ mov %ah, %al # Base = (Node# * Size)#
+ mul %bl #
+ movzx %ax, %eax #
+ shl $12, %eax # Expand back to full byte count (* 4K)
+ add $CORE0_STACK_BASE_ADDR, %eax
+ mov %eax, %ebp
+ #.endif
+ jmp 0f
+ #.else #core 1 thru core 7
+ 1:
+ # Is core 1-7 of any node, assign 4K stacks
+ mov $8, %al # CoreIndex = ( (Node# * 8) ...
+ mul %ah #
+ mov %si, %bx #
+ add %bl, %al # ... + Core#)#
+
+ mov $AMD_MTRR_FIX64k_00000, %bx
+ shl $16, %ebx #
+ mov %al, %bh # Slot# = (CoreIndex / 16) + 4#
+ shr $4, %bh #
+ add $4, %bh #
+ mov $(CORE1_STACK_SIZE >> 12), %bl
+
+ mul %bl # Base = ( (CoreIndex * Size) ...
+ movzx %ax, %eax #
+ shl $12, %eax # Expand back to full byte count (* 4K)
+ add $CORE1_STACK_BASE_ADDR, %eax # ... + Base_Addr)#
+ mov %eax, %ebp
+ #.endif
+ 0:
+
+ # Now set the MTRR. Add this to already existing settings (don't clear any MTRR)
+ mov $WB_DRAM_TYPE, %edi # Load Cache type in 1st slot
+ mov %bh, %cl # ShiftCount = ((slot# ...
+ and $0x03, %cl # ... % 4) ...
+ shl $0x03, %cl # ... * 8)#
+ shl %cl, %edi # Cache type is now in correct position
+ ror $16, %ebx # Get the MTRR address
+ movzx %bx, %ecx #
+ rol $16, %ebx # Put slot# & size back in BX
+ _RDMSR # Read-modify-write the MSR
+ #.if (bh < 4) # Is value in lower or upper half of MSR?
+ cmp $4, %bh
+ jae 1f
+ or %edi, %eax #
+ jmp 0f
+ #.else
+ 1: #
+ or %edi, %edx #
+ #.endif #
+ 0:
+ _WRMSR #
+
+ # Enable MTRR defaults as UC type
+ mov $AMD_MTRR_DEFTYPE, %ecx # MSR:0000_02FF
+ _RDMSR # Read-modify-write the MSR
+ bts $MTRR_DEF_TYPE_EN, %eax # MtrrDefTypeEn
+ bts $MTRR_DEF_TYPE_FIX_EN, %eax # MtrrDefTypeFixEn
+ _WRMSR
+
+ # Close the modification window on the Fixed MTRRs
+ mov $MTRR_SYS_CFG, %ecx # MSR:0C001_0010
+ _RDMSR
+ bts $MTRR_FIX_DRAM_EN, %eax # MtrrFixDramEn
+ bts $MTRR_VAR_DRAM_EN, %eax # variable MTRR enable bit
+ btr $MTRR_FIX_DRAM_MOD_EN, %eax # Turn off modification enable bit
+ _WRMSR
+
+ # Enable caching in CR0
+ mov %cr0, %eax # Enable WT/WB cache
+ btr $CR0_PG, %eax # Make sure paging is disabled
+ btr $CR0_CD, %eax # Clear CR0 NW and CD
+ btr $CR0_NW, %eax
+ mov %eax, %cr0
+
+ # Use the Stack Base & size to calculate SS and ESP values
+ # review:
+ # esi[31:24]=Flags; esi[15,8]= Node#; esi[7,0]= core# (relative to node)
+ # ebp - start address of stack block
+ # ebx - [31:16] - MTRR MSR address
+ # - [15:8] - slot# in MTRR register
+ # - [7:0] - block size in #4K blocks
+ #
+ mov %ebp, %esp # Initialize the stack pointer
+ mov %esp, %edi # Copy the stack start to edi
+ movzx %bl, %bx
+ movzx %bx, %ebx # Clear upper ebx, don't need MSR addr anymore
+ shl $12, %ebx # Make size full byte count (* 4K)
+ add %ebx, %esp # Set the Stack Pointer as full linear address
+ sub $4, %esp
+ mov %esp,%ebp
+ #
+ # review:
+ # esi[31:24]=Flags; esi[15,8]= Node#; esi[7,0]= core# (relative to node)
+ # edi - 32b start address of stack block
+ # ebx - size of stack block
+ # esp - 32b linear stack pointer
+ #
+
+ # Determine mode for SS base;
+ mov %cr0, %ecx # Check for 32-bit protect mode
+ bt $CR0_PE, %ecx #
+ #.if (!carry?) # PE=0 means real mode
+ jc Protected32Mode
+ mov %cs, %cx # PE=1
+ cmp $0x0D000, %cx # Check for CS
+ jb Protected32Mode # If CS < D000, it is a selector instead of a segment
+ # alter SS:ESP for 16b Real Mode:
+Real16bMode:
+ mov %edi, %eax
+ shr $4, %eax # Create a Real Mode segment for ss, ds, es
+ mov %ax, %ss
+ mov %ax, %ds
+ mov %ax, %es
+ shl $4, %eax
+ sub %eax, %edi # Adjust the clearing pointer for Seg:Offset mode
+ mov %ebx, %esp # Make SP an offset from SS
+ sub $4, %esp #
+ mov %esp,%ebp
+ # .endif # endif
+ # #else
+ # Default is to use Protected 32b Mode
+ #.endif
+ ;
+Protected32Mode:
+ #
+ # Clear The Stack
+ # Now that we have set the location and the MTRRs, initialize the cache by
+ # reading then writing to zero all of the stack area.
+ # review:
+ # ss - Stack base
+ # esp - stack pointer
+ # ebx - size of stack block
+ # esi[31:24]=Flags; esi[15,8]= Node#; esi[7,0]= core# (relative to node)
+ # edi - address of start of stack block
+ #
+
+ClearTheStack: # Stack base is in SS, stack pointer is in ESP
+ shr $2, %ebx # ebx = stack block size in dwords
+ mov %bx, %cx #
+ # Check our flags - Don't clear an existing stack
+ #.if ( !(esi & 0FF000000h)) # Check our flags
+ test $(1 << FLAG_STACK_REENTRY), %esi
+ jne 1f
+ cld
+ mov %edi, %esi
+ rep lodsl (%esi) # Pre-load the range
+ xor %eax, %eax
+ mov %bx, %cx
+ mov %edi, %esi # Preserve base for push on stack
+ rep stosl (%edi) # Clear the range
+ movl $0x0ABCDDCBA, (%esp) # Put marker in top stack dword
+ shl $2, %ebx # Put stack size and base
+ push %ebx # in top of stack
+ push %esi
+
+ mov %ebx, %ecx # Return size of stack in bytes
+ xor %eax, %eax # eax = 0 : no error return code
+ jmp 0f
+ #.else
+ 1:
+ movzx %cx, %ecx
+ shl $2, %ecx # Return size of stack in bytes
+ mov %esi, %eax
+ shr $24, %eax # Keep the flags as part of the error report
+ or $0x40000000, %eax # eax = AGESA_WARNING (Stack has already been set up)
+ #.endif
+ 0:
+
+ movd %mm0, %ebx # Restore return address
+ movd %mm1, %ebp
+.endm
+
+/*****************************************************************************
+* AMD_DISABLE_STACK: Destroy the stack inside the cache. This routine
+* should only be executed on the BSP
+*
+* In:
+* none
+*
+* Out:
+* EAX = AGESA_SUCCESS
+*
+* Preserved:
+* ebx
+* Destroyed:
+* eax, ecx, edx, esp
+*****************************************************************************/
+.macro AMD_DISABLE_STACK
+
+ mov %ebx, %esp # Save return address
+
+ # get node/core/flags of current executing core
+ GET_NODE_ID_CORE_ID # Sets ESI[15,8]= Node#; ESI[7,0]= core# (relative to node)
+
+ # Turn on modification enable bit
+ mov $MTRR_SYS_CFG, %ecx # MSR:C001_0010
+ _RDMSR
+ bts $MTRR_FIX_DRAM_MOD_EN, %eax # Enable modifications
+ _WRMSR
+
+ # Set lower 640K MTRRs for Write-Back memory caching
+ mov $AMD_MTRR_FIX64k_00000, %ecx
+ mov $0x1E1E1E1E, %eax
+ mov %eax, %edx
+ _WRMSR # 0 - 512K = WB Mem
+ mov $AMD_MTRR_FIX16k_80000, %ecx
+ _WRMSR # 512K - 640K = WB Mem
+
+ # Turn off modification enable bit
+ mov $MTRR_SYS_CFG, %ecx # MSR:C001_0010
+ _RDMSR
+ btr $MTRR_FIX_DRAM_MOD_EN, %eax # Disable modification
+ _WRMSR
+
+ AMD_DISABLE_STACK_FAMILY_HOOK # Re-Enable 'normal' cache operations
+
+ mov %esp, %ebx
+ xor %eax, %eax
+
+.endm
+
diff --git a/src/vendorcode/amd/pi/00660F01/AGESA.h b/src/vendorcode/amd/pi/00660F01/AGESA.h
new file mode 100644
index 0000000..17205b1
--- /dev/null
+++ b/src/vendorcode/amd/pi/00660F01/AGESA.h
@@ -0,0 +1,3889 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Agesa structures and definitions
+ *
+ * Contains AMD AGESA core interface
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: Include
+ * @e \$Revision: 314282 $ @e \$Date: 2015-03-08 04:44:40 -0500 (Sun, 08 Mar 2015) $
+ */
+ /*****************************************************************************
+ *
+ * Copyright (c) 2008 - 2015, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ***************************************************************************/
+
+
+#ifndef _AGESA_H_
+#define _AGESA_H_
+
+#include "Porting.h"
+#include "AMD.h"
+
+//
+//
+// AGESA Types and Definitions
+//
+//
+
+// AGESA BASIC CALLOUTS
+#define AGESA_MEM_RELEASE 0x00028000ul
+
+// AGESA ADVANCED CALLOUTS, Processor
+#define AGESA_CHECK_UMA 0x00028100ul
+#define AGESA_DO_RESET 0x00028101ul
+#define AGESA_ALLOCATE_BUFFER 0x00028102ul
+#define AGESA_DEALLOCATE_BUFFER 0x00028103ul
+#define AGESA_LOCATE_BUFFER 0x00028104ul
+#define AGESA_RUNFUNC_ONAP 0x00028105ul
+#define AGESA_RUNFUNC_ON_ALL_APS 0x00028106ul
+#define AGESA_IDLE_AN_AP 0x00028107ul
+#define AGESA_WAIT_FOR_ALL_APS 0x00028108ul
+
+// AGESA ADVANCED CALLOUTS, Memory
+#define AGESA_READ_SPD 0x00028140ul
+#define AGESA_HOOKBEFORE_DRAM_INIT 0x00028141ul
+#define AGESA_HOOKBEFORE_DQS_TRAINING 0x00028142ul
+#define AGESA_READ_SPD_RECOVERY 0x00028143ul
+#define AGESA_HOOKBEFORE_EXIT_SELF_REF 0x00028144ul
+#define AGESA_HOOKBEFORE_DRAM_INIT_RECOVERY 0x00028145ul
+#define AGESA_EXTERNAL_2D_TRAIN_VREF_CHANGE 0x00028146ul
+#define AGESA_EXTERNAL_VOLTAGE_ADJUST 0x00028147ul
+
+// AGESA IDS CALLOUTS
+#define AGESA_GET_IDS_INIT_DATA 0x00028200ul
+
+// AGESA GNB CALLOUTS
+#define AGESA_GNB_PCIE_SLOT_RESET 0x00028301ul
+#define AGESA_GNB_GFX_GET_VBIOS_IMAGE 0x00028302ul
+#define AGESA_GNB_PCIE_CLK_REQ 0x00028303ul
+
+// AGESA FCH CALLOUTS
+#define AGESA_FCH_OEM_CALLOUT 0x00028401ul
+
+//-----------------------------------------------------------------------------
+// FCH DEFINITIONS AND MACROS
+//
+//-----------------------------------------------------------------------------
+
+/// Configuration values for SdConfig
+typedef enum {
+ SdDisable = 0, ///< Disabled
+ SdVer2, ///< Version 2.0
+ SdVer3, ///< Version 3.0
+ SdV3SDR50, ///< V3 SdSDR50
+ SdV3SDR104, ///< V3 SdSDR104
+ SdV3DDR50, ///< V3 SdDDR50
+ SdDump ///< SD DUMP, don't touch SD
+} SD_MODE;
+
+/// Configuration values for SdClockControl
+typedef enum {
+ Sd50MhzTraceCableLengthWithinSixInches = 4, ///< 50Mhz, default
+ Sd40MhzTraceCableLengthSix2ElevenInches = 6, ///< 40Mhz
+ Sd25MhzTraceCableLengthEleven2TwentyfourInches = 7, ///< 25Mhz
+} SD_CLOCK_CONTROL;
+
+/// Configuration values for AzaliaController
+typedef enum {
+ AzAuto = 0, ///< Auto - Detect Azalia controller automatically
+ AzDisable, ///< Diable - Disable Azalia controller
+ AzEnable ///< Enable - Enable Azalia controller
+} HDA_CONFIG;
+
+/// Configuration values for IrConfig
+typedef enum {
+ IrDisable = 0, ///< Disable
+ IrRxTx0 = 1, ///< Rx and Tx0
+ IrRxTx1 = 2, ///< Rx and Tx1
+ IrRxTx0Tx1 = 3 ///< Rx and both Tx0,Tx1
+} IR_CONFIG;
+
+/// Configuration values for SataClass
+typedef enum {
+ SataNativeIde = 0, ///< Native IDE mode
+ SataRaid, ///< RAID mode
+ SataAhci, ///< AHCI mode
+ SataLegacyIde, ///< Legacy IDE mode
+ SataIde2Ahci, ///< IDE->AHCI mode
+ SataAhci7804, ///< AHCI mode as 7804 ID (AMD driver)
+ SataIde2Ahci7804 ///< IDE->AHCI mode as 7804 ID (AMD driver)
+} SATA_CLASS;
+
+/// Configuration values for BLDCFG_FCH_GPP_LINK_CONFIG
+typedef enum {
+ PortA4 = 0, ///< 4:0:0:0
+ PortA2B2 = 2, ///< 2:2:0:0
+ PortA2B1C1 = 3, ///< 2:1:1:0
+ PortA1B1C1D1 = 4 ///< 1:1:1:1
+} GPP_LINKMODE;
+
+/// Configuration values for FchPowerFail
+typedef enum {
+ AlwaysOff = 0, ///< Always power off after power resumes
+ AlwaysOn = 1, ///< Always power on after power resumes
+ UsePrevious = 3, ///< Resume to same setting when power fails
+} POWER_FAIL;
+
+
+/// Configuration values for SATA Link Speed
+typedef enum {
+ Gen1 = 1, ///< SATA port GEN1 speed
+ Gen2 = 2, ///< SATA port GEN2 speed
+ Gen3 = 3, ///< SATA port GEN3 speed
+} SATA_SPEED;
+
+
+/// Configuration values for GPIO function
+typedef enum {
+ Function0 = 0, ///< GPIO Function 1
+ Function1 = 1, ///< GPIO Function 1
+ Function2 = 2, ///< GPIO Function 2
+ Function3 = 3, ///< GPIO Function 3
+} GPIO_FUN;
+
+/// Configuration values for memory phy voltage (VDDR)
+#define VOLT0_95 0 ///< VDDR 0.95V
+#define VOLT1_05 1 ///< VDDR 1.05V
+#define MAX_VDDR 2 ///< Maxmum value for this enum definition
+
+/// Configuration values for GPIO_CFG
+typedef enum {
+ OwnedByEc = 1 << 0, ///< This bit can only be written by EC
+ OwnedByHost = 1 << 1, ///< This bit can only be written by host (BIOS)
+ Sticky = 1 << 2, ///< If set, [6:3] are sticky
+ PullUpB = 1 << 3, ///< 0: Pullup enable; 1: Pullup disabled
+ PullDown = 1 << 4, ///< 0: Pulldown disabled; 1: Pulldown enable
+ GpioOutEnB = 1 << 5, ///< 0: Output enable; 1: Output disable
+ GpioOut = 1 << 6, ///< Output state when GpioOutEnB is 0
+ GpioIn = 1 << 7, ///< This bit is read only - current pin state
+} CFG_BYTE;
+
+/// Configuration values for GPIO_CFG2
+typedef enum {
+ DrvStrengthSel_4mA = 0 << 1, ///< 18:17 DrvStrengthSel.
+ DrvStrengthSel_8mA = 1 << 1, ///< 18:17 DrvStrengthSel.
+ DrvStrengthSel_12mA = 2 << 1, ///< 18:17 DrvStrengthSel.
+ DrvStrengthSel_16mA = 3 << 1, ///< 18:17 DrvStrengthSel.
+ PullUpSel_8K = 1 << 3, ///< 19 PullUpSel. Read-write. 0=4 K pull-up is selected. 1=8 K pull-up is selected.
+ PullUpEnable = 1 << 4, ///< 20 PullUpEnable. Read-write. 0=Pull-up is disabled on the pin. 1=Pull-up is enabled on the pin.
+ PullDownEnable = 1 << 5, ///< 21 PullDownEnable. Read-write. 0=Pull-down is disabled on the pin. 1=Pull-down is enabled on thepin.
+ OutputValue = 1 << 6, ///< 22 OutputValue. Read-write. 0=low. 1=high.
+ OutputEnable = 1 << 7, ///< 23 OutputEnable. Read-write. 0=Output is disabled on the pin. 1=Output is enabled on the pin.
+} CFG2_BYTE;
+
+/// FCH GPIO CONTROL
+typedef struct {
+ IN UINT8 GpioPin; ///< Gpio Pin, valid range: 0-67, 128-150, 160-228
+ IN GPIO_FUN PinFunction; ///< Multi-function selection
+ IN CFG_BYTE CfgByte; ///< GPIO Register value
+} GPIO_CONTROL;
+
+///
+/// FCH SCI MAP CONTROL
+///
+typedef struct {
+ IN UINT8 InputPin; ///< Input Pin, valid range 0-63
+ IN UINT8 GpeMap; ///< Gpe Map, valid range 0-31
+} SCI_MAP_CONTROL;
+
+///
+/// FCH SATA PHY CONTROL
+///
+typedef struct {
+ IN BOOLEAN CommonPhy; ///< Common PHY or not
+ ///< @li <b>FALSE</b> - Only applied to specified port
+ ///< @li <b>TRUE</b> - Apply to all SATA ports
+ IN SATA_SPEED Gen; ///< SATA speed
+ IN UINT8 Port; ///< Port number, valid range: 0-7
+ IN UINT32 PhyData; ///< SATA PHY data, valid range: 0-0xFFFFFFFF
+} SATA_PHY_CONTROL;
+
+///
+/// FCH Component Data Structure in InitReset stage
+///
+typedef struct {
+ IN BOOLEAN UmiGen2; ///< Enable Gen2 data rate of UMI
+ ///< @li <b>FALSE</b> - Disable Gen2
+ ///< @li <b>TRUE</b> - Enable Gen2
+
+ IN BOOLEAN SataEnable; ///< SATA controller function
+ ///< @li <b>FALSE</b> - SATA controller is disabled
+ ///< @li <b>TRUE</b> - SATA controller is enabled
+
+ IN BOOLEAN IdeEnable; ///< SATA IDE controller mode enabled/disabled
+ ///< @li <b>FALSE</b> - IDE controller is disabled
+ ///< @li <b>TRUE</b> - IDE controller is enabled
+
+ IN BOOLEAN GppEnable; ///< Master switch of GPP function
+ ///< @li <b>FALSE</b> - GPP disabled
+ ///< @li <b>TRUE</b> - GPP enabled
+
+ IN BOOLEAN Xhci0Enable; ///< XHCI0 controller function
+ ///< @li <b>FALSE</b> - XHCI0 controller disabled
+ ///< @li <b>TRUE</b> - XHCI0 controller enabled
+
+ IN BOOLEAN Xhci1Enable; ///< XHCI1 controller function
+ ///< @li <b>FALSE</b> - XHCI1 controller disabled
+ ///< @li <b>TRUE</b> - XHCI1 controller enabled
+} FCH_RESET_INTERFACE;
+
+
+///
+/// FCH Component Data Structure from InitEnv stage
+///
+typedef struct {
+ IN SD_MODE SdConfig; ///< Secure Digital (SD) controller mode
+ IN HDA_CONFIG AzaliaController; ///< Azalia HD Audio Controller
+
+ IN IR_CONFIG IrConfig; ///< Infrared (IR) Configuration
+ IN BOOLEAN UmiGen2; ///< Enable Gen2 data rate of UMI
+ ///< @li <b>FALSE</b> - Disable Gen2
+ ///< @li <b>TRUE</b> - Enable Gen2
+
+ IN SATA_CLASS SataClass; ///< SATA controller mode
+ IN BOOLEAN SataEnable; ///< SATA controller function
+ ///< @li <b>FALSE</b> - SATA controller is disabled
+ ///< @li <b>TRUE</b> - SATA controller is enabled
+
+ IN BOOLEAN IdeEnable; ///< SATA IDE controller mode enabled/disabled
+ ///< @li <b>FALSE</b> - IDE controller is disabled
+ ///< @li <b>TRUE</b> - IDE controller is enabled
+
+ IN BOOLEAN SataIdeMode; ///< Native mode of SATA IDE controller
+ ///< @li <b>FALSE</b> - Legacy IDE mode
+ ///< @li <b>TRUE</b> - Native IDE mode
+
+ IN BOOLEAN Ohci1Enable; ///< OHCI controller #1 Function
+ ///< @li <b>FALSE</b> - OHCI1 is disabled
+ ///< @li <b>TRUE</b> - OHCI1 is enabled
+
+ IN BOOLEAN Ohci2Enable; ///< OHCI controller #2 Function
+ ///< @li <b>FALSE</b> - OHCI2 is disabled
+ ///< @li <b>TRUE</b> - OHCI2 is enabled
+
+ IN BOOLEAN Ohci3Enable; ///< OHCI controller #3 Function
+ ///< @li <b>FALSE</b> - OHCI3 is disabled
+ ///< @li <b>TRUE</b> - OHCI3 is enabled
+
+ IN BOOLEAN Ohci4Enable; ///< OHCI controller #4 Function
+ ///< @li <b>FALSE</b> - OHCI4 is disabled
+ ///< @li <b>TRUE</b> - OHCI4 is enabled
+
+ IN BOOLEAN GppEnable; ///< Master switch of GPP function
+ ///< @li <b>FALSE</b> - GPP disabled
+ ///< @li <b>TRUE</b> - GPP enabled
+
+ IN POWER_FAIL FchPowerFail; ///< FCH power failure option
+} FCH_INTERFACE;
+
+
+/*----------------------------------------------------------------------------
+ * CPU Feature related info
+ *----------------------------------------------------------------------------
+ */
+/// Build Configuration values for BLDCFG_PLATFORM_CONNECTED_STANDBY_MODE
+typedef enum {
+ ConnectedStandbyAuto = 0, ///< Auto
+ ConnectedStandbyDisabled = 1, ///< Disabled
+ MaxConnectedStandbyMode = 2 ///< Not a valid value, used for verifying input
+} PLATFORM_CONNECTED_STANDBY_MODES;
+
+/// Build Configuration values for BLDCFG_PLATFORM_CSTATE_MODE
+typedef enum {
+ CStateModeDisabled = 0, ///< Disabled
+ CStateModeC6 = 1, ///< C6 State
+ MaxCStateMode = 2 ///< Not a valid value, used for verifying input
+} PLATFORM_CSTATE_MODES;
+
+/// Build Configuration values for BLDCFG_PLATFORM_CPB_MODE
+typedef enum {
+ CpbModeAuto = 0, ///< Auto
+ CpbModeDisabled = 1, ///< Disabled
+ MaxCpbMode = 2 ///< Not a valid value, used for verifying input
+} PLATFORM_CPB_MODES;
+
+
+/// Build Configuration values for BLDCFG_ACPI_PSTATES_PSD_POLICY
+#define PsdPolicyProcessorDefault 0 ///< PSD is dependent or independent per processor default
+#define PsdPolicyDependent 1 ///< PSD is forced dependent
+#define PsdPolicyIndependent 2 ///< PSD is forced independent
+#define PsdPolicyMax 3 ///< Not a valid value, used for verifying input
+
+/*----------------------------------------------------------------------------
+ * GNB PCIe configuration info
+ *----------------------------------------------------------------------------
+ */
+
+// Event definitions
+
+#define GNB_EVENT_INVALID_CONFIGURATION 0x20010000ul // User configuration invalid
+#define GNB_EVENT_INVALID_PCIE_TOPOLOGY_CONFIGURATION 0x20010001ul // Requested lane allocation for PCIe port can not be supported
+#define GNB_EVENT_INVALID_PCIE_PORT_CONFIGURATION 0x20010002ul // Requested incorrect PCIe port device address
+#define GNB_EVENT_INVALID_DDI_LINK_CONFIGURATION 0x20010003ul // Incorrect parameter in DDI link configuration
+#define GNB_EVENT_INVALID_LINK_WIDTH_CONFIGURATION 0x20010004ul // Invalid with for PCIe port or DDI link
+#define GNB_EVENT_INVALID_LANES_CONFIGURATION 0x20010005ul // Lane double subscribe lanes
+#define GNB_EVENT_INVALID_DDI_TOPOLOGY_CONFIGURATION 0x20010006ul // Requested lane allocation for DDI link(s) can not be supported
+#define GNB_EVENT_LINK_TRAINING_FAIL 0x20020000ul // PCIe Link training fail
+#define GNB_EVENT_BROKEN_LANE_RECOVERY 0x20030000ul // Broken lane workaround applied to recover link training
+#define GNB_EVENT_GEN2_SUPPORT_RECOVERY 0x20040000ul // Scale back to GEN1 to recover link training
+
+
+#define DESCRIPTOR_TERMINATE_LIST 0x80000000ull
+#define DESCRIPTOR_IGNORE 0x40000000ull
+
+/// PCIe link initialization
+typedef enum {
+ EndpointDetect = 0, ///< Detect endpoint presence
+ EndpointNotPresent ///< Endpoint not present (or connected). Used in case there is alternative way to determine
+ ///< if device present on board or in slot. For example GPIO can be used to determine device presence.
+} PCIE_ENDPOINT_STATUS;
+
+
+/// PCIe port misc extended controls
+typedef struct {
+ IN UINT8 LinkComplianceMode :1; ///< Force port into compliance mode (device will not be trained, port output compliance pattern)
+ IN UINT8 LinkSafeMode :2; /**< Safe mode PCIe capability. (Parameter may limit PCIe speed requested through PCIe_PORT_DATA::LinkSpeedCapability)
+ * @li @b 0 - port can advertize muximum supported capability
+ * @li @b 1 - port limit advertized capability and speed to PCIe Gen1
+ */
+ IN UINT8 SbLink :1; /**< PCIe link type
+ * @li @b 0 - General purpose port
+ * @li @b 1 - Port connected to SB
+ */
+ IN UINT8 ClkPmSupport :1; /**< Clock Power Management Support
+ * @li @b 0 - Clock Power Management not configured
+ * @li @b 1 - Clock Power Management configured according to PCIe device capability
+ */
+} PCIe_PORT_MISC_CONTROL;
+
+/// The IO APIC Interrupt Mapping Info
+typedef struct {
+ IN UINT8 GroupMap; /**< Group mapping for slot or endpoint device (connected to PCIE port) interrupts .
+ * @li <b>0</b> - IGNORE THIS STRUCTURE AND USE RECOMMENDED SETTINGS
+ * @li <b>1</b> - mapped to Grp 0 (Interrupts 0..3 of IO APIC redirection table)
+ * @li <b>2</b> - mapped to Grp 1 (Interrupts 4..7 of IO APIC redirection table)
+ * @li ...
+ * @li <b>8</b> - mapped to Grp 7 (Interrupts 28..31 of IO APIC redirection table)
+ */
+ IN UINT8 Swizzle; /**< Swizzle interrupt in the Group.
+ * @li <b>0</b> - ABCD
+ * @li <b>1</b> - BCDA
+ * @li <b>2</b> - CDAB
+ * @li <b>3</b> - DABC
+ */
+ IN UINT8 BridgeInt; /**< IOAPIC redirection table entry for PCIE bridge interrupt
+ * @li <b>0</b> - Entry 0 of IO APIC redirection table
+ * @li <b>1</b> - Entry 1 of IO APIC redirection table
+ * @li ...
+ * @li <b>31</b> - Entry 31 of IO APIC redirection table
+ */
+} APIC_DEVICE_INFO;
+
+/// Initial Offset Calibration Control
+typedef enum {
+ ADAPT_IOC_DISABLED = 0, ///< Initial Offset Calibration Disabled
+ ADAPT_IOC_ENABLED ///< Initial Offset Calibration Enabled
+} ADAPT_IOC_CONTROL;
+
+/// DFE Control values
+typedef enum {
+ ADAPT_DFE_CONTROL_DISABLED = 0, ///< DFE Disabled
+ ADAPD_DFE_CONTROL_1TAP_DFE = 4, ///< 1-tap DFE
+ ADAPD_DFE_CONTROL_1TAP_DFE_FBF, ///< 1-tap DFE with Future Bit Filtering
+ ADAPD_DFE_CONTROL_2TAP_DFE, ///< 2-tap DFE
+ ADAPD_DFE_CONTROL_2TAP_DFE_FBF ///< 2-tap DFE with Future Bit Filtering
+} ADAPT_DFE_CONTROL;
+
+/// LEQ Control values
+typedef enum {
+ ADAPT_LEQ_CONTROL_DISABLED = 0, ///< LEQ Disabled
+ ADAPT_LEQ_CONTROL_DC_GAIN = 2, ///< DC Gain Adaptation
+ ADAPT_LEQ_CONTROL_DC_GAIN_POLE ///< DC Gain and Pole Adaptation
+} ADAPT_LEQ_CONTROL;
+
+/// Dynamic Offset Calibration Control
+typedef enum {
+ ADAPT_DOC_DISABLED = 0, ///< Dynamic Offset Calibration Disabled
+ ADAPT_DOC_ENABLED ///< Dynamic Offset Calibration Enabled
+} ADAPT_DOC_CONTROL;
+
+/// FOM Calculation Control
+typedef enum {
+ ADAPT_FOMC_DISABLED = 0, ///< FOM Calculation Disabled
+ ADAPT_FOMC_ENABLED ///< FOM Calculation Enabled
+} ADAPT_FOMC_CONTROL;
+
+/// PI Offset Calibration Control
+typedef enum {
+ ADAPT_PIOC_DISABLED = 0, ///< PI Offset Calibration Disabled
+ ADAPT_PIOC_ENABLED ///< PI Offset Calibration Enabled
+} ADAPT_PIOC_CONTROL;
+
+/// GEN3 RxAdaptMode Configuration Structure
+typedef struct {
+ IN BOOLEAN InitOffsetCancellation; ///< Initial Offset Cancellation Enable
+ IN UINT8 DFEControl; ///< DFE Control
+ IN UINT8 LEQControl; ///< LEQ Control
+ IN BOOLEAN DynamicOffsetCalibration; ///< Dynamic Offset Calibration Enable
+ IN BOOLEAN FOMCalculation; ///< FOM Calculation Enable
+ IN BOOLEAN PIOffsetCalibration; ///< PI Offset Calibratino Enable
+} RX_ADAPT_MODE;
+
+/// PCIe port configuration data
+typedef struct {
+ IN UINT8 PortPresent; ///< Enable PCIe port for initialization.
+ IN UINT8 ChannelType; /**< Channel type.
+ * @li @b 0 - "lowLoss",
+ * @li @b 1 - "highLoss",
+ * @li @b 2 - "mob0db",
+ * @li @b 3 - "mob3db",
+ * @li @b 4 - "extnd6db"
+ * @li @b 5 - "extnd8db"
+ */
+ IN UINT8 DeviceNumber; /**< PCI Device number for port.
+ * @li @b 0 - Native port device number
+ * @li @b N - Port device number (See available configurations in BKDG
+ */
+ IN UINT8 FunctionNumber; ///< Reserved for future use
+ IN UINT8 LinkSpeedCapability; /**< PCIe link speed/
+ * @li @b 0 - Maximum supported by silicon
+ * @li @b 1 - Gen1
+ * @li @b 2 - Gen2
+ * @li @b 3 - Gen3
+ */
+ IN UINT8 LinkAspm; /**< ASPM control. (see AgesaPcieLinkAspm for additional option to control ASPM)
+ * @li @b 0 - Disabled
+ * @li @b 1 - L0s only
+ * @li @b 2 - L1 only
+ * @li @b 3 - L0s and L1
+ */
+ IN UINT8 LinkHotplug; /**< Hotplug control.
+ * @li @b 0 - Disabled
+ * @li @b 1 - Basic
+ * @li @b 2 - Server
+ * @li @b 3 - Enhanced
+ */
+ IN UINT8 ResetId; /**< Arbitrary number greater than 0 assigned by platform firmware for GPIO
+ * identification which control reset for given port.
+ * Each port with unique GPIO should have unique ResetId assigned.
+ * All ports use same GPIO to control reset should have same ResetId assigned.
+ * see AgesaPcieSlotResetContol.
+ */
+ IN PCIe_PORT_MISC_CONTROL MiscControls; ///< Misc extended controls
+ IN APIC_DEVICE_INFO ApicDeviceInfo; ///< IOAPIC device programming info
+ IN PCIE_ENDPOINT_STATUS EndpointStatus; ///< PCIe endpoint (device connected to PCIe port) status
+ IN RX_ADAPT_MODE RxAdaptMode; ///< Gen3 RxAdaptMode configuration
+} PCIe_PORT_DATA;
+
+/// DDI channel lane mapping
+typedef struct { ///< Structure that discribe lane mapping
+ IN UINT8 Lane0 :2; /**< Lane 0 mapping
+ * @li @b 0 - Map to lane 0
+ * @li @b 1 - Map to lane 1
+ * @li @b 2 - Map to lane 2
+ * @li @b 2 - Map to lane 3
+ */
+ IN UINT8 Lane1 :2; ///< Lane 1 mapping (see "Lane 0 mapping")
+ IN UINT8 Lane2 :2; ///< Lane 2 mapping (see "Lane 0 mapping")
+ IN UINT8 Lane3 :2; ///< Lane 3 mapping (see "Lane 0 mapping")
+} CHANNEL_MAPPING; ///< Lane mapping
+
+/// Common Channel Mapping
+typedef union {
+ IN UINT8 ChannelMappingValue; ///< Raw lane mapping
+ IN CHANNEL_MAPPING ChannelMapping; ///< Channel mapping
+} CONN_CHANNEL_MAPPING;
+
+/// DDI Configuration data
+typedef struct {
+ IN UINT8 ConnectorType; /**< Display Connector Type
+ * @li @b 0 - DP
+ * @li @b 1 - eDP
+ * @li @b 2 - Single Link DVI-D
+ * @li @b 3 - Dual Link DVI-D (see @ref DualLinkDviDescription "Example Dual Link DVI connector description")
+ * @li @b 4 - HDMI
+ * @li @b 5 - DP-to-VGA
+ * @li @b 6 - DP-to-LVDS
+ * @li @b 7 - Hudson-2 NutMeg DP-to-VGA
+ * @li @b 8 - Single Link DVI-I
+ * @li @b 9 - Native CRT (Family 0x14)
+ * @li @b 10 - Native LVDS (Family 0x14)
+ * @li @b 11 - Auto detect LCD panel connector type. VBIOS is able to auto detect the LVDS connector type: native LVDS, eDP or DP-to-LVDS
+ * The auto detection method only support panel with EDID.
+ */
+ IN UINT8 AuxIndex; /**< Indicates which AUX or DDC Line is used
+ * @li @b 0 - AUX1
+ * @li @b 1 - AUX2
+ * @li @b 2 - AUX3
+ * @li @b 3 - AUX4
+ * @li @b 4 - AUX5
+ * @li @b 5 - AUX6
+ */
+ IN UINT8 HdpIndex; /**< Indicates which HDP pin is used
+ * @li @b 0 - HDP1
+ * @li @b 1 - HDP2
+ * @li @b 2 - HDP3
+ * @li @b 3 - HDP4
+ * @li @b 4 - HDP5
+ * @li @b 5 - HDP6
+ */
+ IN CONN_CHANNEL_MAPPING Mapping[2]; /**< Set specific mapping of lanes to connector pins
+ * @li Mapping[0] define mapping for group of 4 lanes starting at PCIe_ENGINE_DATA.StartLane
+ * @li Mapping[1] define mapping for group of 4 lanes ending at PCIe_ENGINE_DATA.EndLane (only applicable for Dual DDI link)
+ * if Mapping[x] set to 0 than default mapping assumed
+ */
+ IN UINT8 LanePnInversionMask; /**< Specifies whether to invert the state of P and N for each lane. Each bit represents a PCIe lane on the DDI port.
+ * @li 0 - Do not invert (default)
+ * @li 1 - Invert P and N on this lane
+ */
+ IN UINT8 Flags; /**< Capabilities flags
+ * @li Flags bit[0] DDI_DATA_FLAGS_DP1_1_ONLY Selects downgrade PHY link to DP1.1
+ * @li Flags bit[7:1] Reserved
+ */
+} PCIe_DDI_DATA;
+
+/// Engine Configuration
+typedef struct {
+ IN UINT8 EngineType; /**< Engine type
+ * @li @b 0 - Ignore engine configuration
+ * @li @b 1 - PCIe port
+ * @li @b 2 - DDI
+ */
+ IN UINT16 StartLane; /**< Start Lane ID (in reversed configuration StartLane > EndLane)
+ * Refer to lane descriptions and supported configurations in BKDG
+ */
+ IN UINT16 EndLane; /**< End lane ID (in reversed configuration StartLane > EndLane)
+ * Refer to lane descriptions and supported configurations in BKDG
+ */
+
+} PCIe_ENGINE_DATA;
+
+/// PCIe port descriptor
+typedef struct {
+ IN UINT32 Flags; /**< Descriptor flags
+ * @li @b Bit31 - last descriptor in complex
+ */
+ IN PCIe_ENGINE_DATA EngineData; ///< Engine data
+ IN PCIe_PORT_DATA Port; ///< PCIe port specific configuration info
+} PCIe_PORT_DESCRIPTOR;
+
+/// DDI descriptor
+typedef struct {
+ IN UINT32 Flags; /**< Descriptor flags
+ * @li @b Bit31 - last descriptor in complex
+ */
+ IN PCIe_ENGINE_DATA EngineData; ///< Engine data
+ IN PCIe_DDI_DATA Ddi; ///< DDI port specific configuration info
+} PCIe_DDI_DESCRIPTOR;
+
+/// PCIe Complex descriptor
+typedef struct {
+ IN UINT32 Flags; /**< Descriptor flags
+ * @li @b Bit31 - last descriptor in topology
+ */
+ IN UINT32 SocketId; ///< Socket Id
+ IN const PCIe_PORT_DESCRIPTOR *PciePortList; ///< Pointer to array of PCIe port descriptors or NULL (Last element of array must be terminated with DESCRIPTOR_TERMINATE_LIST).
+ IN const PCIe_DDI_DESCRIPTOR *DdiLinkList; ///< Pointer to array DDI link descriptors (Last element of array must be terminated with DESCRIPTOR_TERMINATE_LIST).
+ IN VOID *Reserved; ///< Reserved for future use
+} PCIe_COMPLEX_DESCRIPTOR;
+
+/// Action to control PCIe slot reset
+typedef enum {
+ AssertSlotReset, ///< Assert slot reset
+ DeassertSlotReset ///< Deassert slot reset
+} PCIE_RESET_CONTROL;
+
+///Slot Reset Info
+typedef struct {
+ IN AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header
+ IN UINT8 ResetId; ///< Slot reset ID as specified in PCIe_PORT_DESCRIPTOR
+ IN UINT8 ResetControl; ///< Reset control as in PCIE_RESET_CONTROL
+} PCIe_SLOT_RESET_INFO;
+
+#define GFX_VBIOS_IMAGE_FLAG_SPECIAL_POST 0x1
+
+///VBIOS image info
+typedef struct {
+ IN AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header
+ OUT VOID *ImagePtr; ///< Pointer to VBIOS image
+ IN PCI_ADDR GfxPciAddress; ///< PCI address of integrated graphics controller
+ IN UINT32 Flags; ///< BIT[0] - special repost requred
+} GFX_VBIOS_IMAGE_INFO;
+
+/// Engine descriptor type
+typedef enum {
+ PcieUnusedEngine = 0, ///< Unused descriptor
+ PciePortEngine = 1, ///< PCIe port
+ PcieDdiEngine = 2, ///< DDI
+ MaxPcieEngine ///< Max engine type for boundary check.
+} PCIE_ENGINE_TYPE;
+
+/// PCIe link capability/speed
+typedef enum {
+ PcieGenMaxSupported, ///< Maximum supported
+ PcieGen1 = 1, ///< Gen1
+ PcieGen2, ///< Gen2
+ PcieGen3, ///< Gen3
+ MaxPcieGen ///< Max Gen for boundary check
+} PCIE_LINK_SPEED_CAP;
+
+/// PCIe PSPP Power policy
+typedef enum {
+ PsppDisabled, ///< PSPP disabled
+ PsppPerformance = 1, ///< Performance
+ PsppBalanceHigh, ///< Balance-High
+ PsppBalanceLow, ///< Balance-Low
+ PsppPowerSaving, ///< Power Saving
+ MaxPspp ///< Max Pspp for boundary check
+} PCIE_PSPP_POLICY;
+
+/// DDI display connector type
+typedef enum {
+ ConnectorTypeDP, ///< DP
+ ConnectorTypeEDP, ///< eDP
+ ConnectorTypeSingleLinkDVI, ///< Single Link DVI-D
+ ConnectorTypeDualLinkDVI, ///< Dual Link DVI-D
+ ConnectorTypeHDMI, ///< HDMI
+ ConnectorTypeDpToVga, ///< DP-to-VGA
+ ConnectorTypeDpToLvds, ///< DP-to-LVDS
+ ConnectorTypeNutmegDpToVga, ///< Hudson-2 NutMeg DP-to-VGA
+ ConnectorTypeSingleLinkDviI, ///< Single Link DVI-I
+ ConnectorTypeCrt, ///< CRT (VGA)
+ ConnectorTypeLvds, ///< LVDS
+ ConnectorTypeEDPToLvds, ///< 3rd party common eDP-to-LVDS translator chip without AMD SW init
+ ConnectorTypeEDPToLvdsSwInit, ///< 3rd party eDP-to-LVDS translator which requires AMD SW init
+ ConnectorTypeAutoDetect, ///< VBIOS auto detect connector type (native LVDS, eDP or DP-to-LVDS)
+ MaxConnectorType ///< Not valid value, used to verify input
+} PCIE_CONNECTOR_TYPE;
+
+/// PCIe link channel type
+typedef enum {
+ ChannelTypeLowLoss, ///< Low Loss
+ ChannelTypeHighLoss, ///< High Loss
+ ChannelTypeMob0db, ///< Mobile 0dB
+ ChannelTypeMob3db, ///< Mobile 3dB
+ ChannelTypeExt6db, ///< Extended 6dB
+ ChannelTypeExt8db, ///< Extended 8dB
+ MaxChannelType ///< Not valid value, used to verify input
+} PCIE_CHANNEL_TYPE;
+
+/// PCIe link ASPM
+typedef enum {
+ AspmDisabled, ///< Disabled
+ AspmL0s, ///< PCIe L0s link state
+ AspmL1, ///< PCIe L1 link state
+ AspmL0sL1, ///< PCIe L0s & L1 link state
+ MaxAspm ///< Not valid value, used to verify input
+} PCIE_ASPM_TYPE;
+
+/// PCIe link hotplug support
+typedef enum {
+ HotplugDisabled, ///< Hotplug disable
+ HotplugBasic, ///< Basic Hotplug
+ HotplugServer, ///< Server Hotplug
+ HotplugEnhanced, ///< Enhanced
+ HotplugInboard, ///< Inboard
+ MaxHotplug ///< Not valid value, used to verify input
+} PCIE_HOTPLUG_TYPE;
+
+/// PCIe link initialization
+typedef enum {
+ PortDisabled, ///< Disable
+ PortEnabled ///< Enable
+} PCIE_PORT_ENABLE;
+
+/// PCIe ACS capability - Access Control Services
+typedef enum {
+ PcieAcsDisabled, ///< Disabled
+ PcieAcsEnabled, ///< Enabled
+} PCIE_ACS_CAP;
+
+/// PCIe ClkPmSupport initialization
+typedef enum {
+ ClkPmSupportDisabled, ///< Disable
+ ClkPmSupportEnabled ///< Enable
+} CLKPM_SUPPORT_ENABLE;
+
+/// DDI Aux channel
+typedef enum {
+ Aux1, ///< Aux1
+ Aux2, ///< Aux2
+ Aux3, ///< Aux3
+ Aux4, ///< Aux4
+ Aux5, ///< Aux5
+ Aux6, ///< Aux6
+ MaxAux ///< Not valid value, used to verify input
+} PCIE_AUX_TYPE;
+
+/// DDI Hdp Index
+typedef enum {
+ Hdp1, ///< Hdp1
+ Hdp2, ///< Hdp2
+ Hdp3, ///< Hdp3
+ Hdp4, ///< Hdp4
+ Hdp5, ///< Hdp5
+ Hdp6, ///< Hdp6
+ MaxHdp ///< Not valid value, used to verify input
+} PCIE_HDP_TYPE;
+
+/// PCIe_DDI_DATA.Flags definitions
+#define DDI_DATA_FLAGS_DP1_1_ONLY 0x01 ///< BIT[0] Selects downgrade PHY link to DP1.1
+#define EXT_DISPLAY_PATH_CAPS_DP_FIXED_VS_EN 0x02 ///< BIT[1] VBIOS will always output fixed voltage swing during DP link training
+#define EXT_DISPLAY_PATH_CAPS_HDMI20_PI3EQX1204 0x04 ///< BIT[2] HDMI 2.0 connector
+#define EXT_DISPLAY_PATH_CAPS_HDMI20_TISN65DP159RSBT 0x08 ///< BIT[3] HDMI 2.0 connector
+
+/// DP receiver definitions with fixed voltage swing
+typedef enum {
+ DP_VS_0_4V_0DB, ///< 0x00
+ DP_VS_0_6V_0DB, ///< 0x01
+ DP_VS_0_8V_0DB, ///< 0x02
+ DP_VS_1_2V_0DB, ///< 0x03
+ DP_VS_0_4V_3_5DB = 0x8, ///< 0x08
+ DP_VS_0_6V_3_5DB, ///< 0x09
+ DP_VS_0_8V_3_5DB, ///< 0x0a
+ DP_VS_0_4V_6DB = 0x10, ///< 0x10
+ DP_VS_0_6V_6DB, ///< 0x11
+ DP_VS_0_4V_9_5DB = 0x18 ///< 0x18
+} DP_FIXED_VOLT_SWING_TYPE;
+
+// definition for eDP 1.4 VSMode
+#define EDP_VS_LEGACY_MODE 0 ///< Legacy Mode
+#define EDP_VS_LOW_VDIFF_MODE 1 ///< Low Vdiff Training Mode
+#define EDP_VS_HIGH_VDIFF_MODE 2 ///< High Vdiff Training Mode
+#define EDP_VS_STRETCH_MODE 3 ///< Stretched DP training mode
+#define EDP_VS_SINGLE_VDIFF_MODE 4 ///< Single Vdiff Training Mode
+#define EDP_VS_VARIABLE_PREM_MODE 5 ///< Single Vdiff Training with Variable Transition Vdiff
+
+/// HDMI re-driver register/value
+typedef struct _HDMI_RE_DRIVER_I2C_REG_INFO {
+ IN UINT8 RegIndex; ///< HDMI re-driver Register Index
+ IN UINT8 RegVal; ///< HDMI re-driver Register Value
+} HDMI_RE_DRIVER_I2C_REG_INFO;
+
+/// AZ I2SBUS select
+typedef enum {
+ GnbAcpI2sBus, ///< I2sBus
+ GnbAcpAzalia, ///< Azalia
+ MaxAcp ///< Not valid value, used to verify input
+} GNB_ACP_TYPE;
+
+/// AZ I2SBUS pin configuration
+typedef enum {
+ GnbAcp4Tx4RxBluetooth, ///< 4Tx4Rx and Bluetooth
+ GnbAcp2Tx4RxBluetooth, ///< 2Tx4Rx and Bluetooth
+ GnbAcp6Tx4RxBluetooth, ///< 6Tx4Rx and Bluetooth
+ GnbAcpPinNotConfigured ///< Not valid value, used to verify input
+} GNB_ACP_AZ_I2SBUS_PIN;
+
+/// Alternative DRAM MAC
+typedef enum {
+ MAC_UNTESTEDMAC, ///< Assign 0 to Untested MAC
+ MAC_700k, ///< Assign 1 to 700k
+ MAC_600k, ///< Assign 2 to 600k
+ MAC_500k, ///< Assign 3 to 500k
+ MAC_400k, ///< Assign 4 to 400k
+ MAC_300k, ///< Assign 5 to 300k
+ MAC_200k, ///< Assign 6 to 200k
+ MAC_UNRESTRICTEDMAC = 8, ///< Assign 8 to Unrestricted MAC
+} DRAM_MAXIMUM_ACTIVATE_COUNT;
+
+// Macro for statically initializing various structures
+#define PCIE_ENGINE_DATA_INITIALIZER(mType, mStartLane, mEndLane) {mType, mStartLane, mEndLane}
+#define PCIE_PORT_DATA_INITIALIZER(mPortPresent, mChannelType, mDevAddress, mHotplug, mMaxLinkSpeed, mMaxLinkCap, mAspm, mResetId) \
+{mPortPresent, mChannelType, mDevAddress, 0, mMaxLinkSpeed, mAspm, mHotplug, mResetId, {0, mMaxLinkCap, 0, 0}, {0, 0, 0}, EndpointDetect, \
+{ADAPT_IOC_ENABLED, ADAPT_DFE_CONTROL_DISABLED, ADAPT_LEQ_CONTROL_DC_GAIN_POLE, ADAPT_DOC_DISABLED, ADAPT_FOMC_ENABLED, ADAPT_PIOC_DISABLED}}
+#define PCIE_PORT_DATA_INITIALIZER_V2(mPortPresent, mChannelType, mDevAddress, mDevFunction, mHotplug, mMaxLinkSpeed, mMaxLinkCap, mAspm, mResetId, mClkPmSupport) \
+{mPortPresent, mChannelType, mDevAddress, mDevFunction, mMaxLinkSpeed, mAspm, mHotplug, mResetId, {0, mMaxLinkCap, 0, mClkPmSupport}, {0, 0, 0}, EndpointDetect, \
+{ADAPT_IOC_ENABLED, ADAPT_DFE_CONTROL_DISABLED, ADAPT_LEQ_CONTROL_DC_GAIN_POLE, ADAPT_DOC_DISABLED, ADAPT_FOMC_ENABLED, ADAPT_PIOC_DISABLED}}
+#define PCIE_PORT_DATA_INITIALIZER_GEN3(mPortPresent, mChannelType, mDevAddress, mDevFunction, mHotplug, mMaxLinkSpeed, mMaxLinkCap, mAspm, mResetId, mClkPmSupport, \
+mInitOffsetCancellation, mDFEControl, mLEQControl, mDynamicOffsetCalibration, mFOMCalculation, mPIOffsetCalibration) \
+{mPortPresent, mChannelType, mDevAddress, mDevFunction, mMaxLinkSpeed, mAspm, mHotplug, mResetId, {0, mMaxLinkCap, 0, mClkPmSupport}, {0, 0, 0}, EndpointDetect, \
+{mInitOffsetCancellation, mDFEControl, mLEQControl, mDynamicOffsetCalibration, mFOMCalculation, mPIOffsetCalibration}}
+#define PCIE_DDI_DATA_INITIALIZER(mConnectorType, mAuxIndex, mHpdIndex ) \
+{mConnectorType, mAuxIndex, mHpdIndex, {{0}, {0}}, 0, 0}
+#define PCIE_DDI_DATA_INITIALIZER_V1(mConnectorType, mAuxIndex, mHpdIndex, mMapping0, mMapping1, mPNInversion) \
+{mConnectorType, mAuxIndex, mHpdIndex, {mMapping0, mMapping1}, mPNInversion, 0}
+#define PCIE_DDI_DATA_INITIALIZER_V2(mConnectorType, mAuxIndex, mHpdIndex, mMapping0, mMapping1, mPNInversion, mFlags) \
+{mConnectorType, mAuxIndex, mHpdIndex, {mMapping0, mMapping1}, mPNInversion, mFlags}
+
+///IOMMU requestor ID
+typedef struct {
+ IN UINT16 Bus :8; ///< Bus
+ IN UINT16 Device :5; ///< Device
+ IN UINT16 Function :3; ///< Function
+} IOMMU_REQUESTOR_ID;
+
+/// IVMD exclusion range descriptor
+typedef struct {
+ IN UINT32 Flags; /**< Descriptor flags
+ * @li @b Flags[31] - Terminate descriptor array.
+ * @li @b Flags[30] - Ignore descriptor.
+ */
+ IN IOMMU_REQUESTOR_ID RequestorIdStart; ///< Requestor ID start
+ IN IOMMU_REQUESTOR_ID RequestorIdEnd; ///< Requestor ID end (use same as start for single ID)
+ IN UINT64 RangeBaseAddress; ///< Phisical base address of exclusion range
+ IN UINT64 RangeLength; ///< Length of exclusion range in bytes
+} IOMMU_EXCLUSION_RANGE_DESCRIPTOR;
+
+/*----------------------------------------------------------------------------
+ * GNB configuration info
+ *----------------------------------------------------------------------------
+ */
+
+/// LVDS Misc Control Field
+typedef struct {
+ IN UINT8 FpdiMode:1; ///< This item configures LVDS 888bit panel mode
+ ///< @li FALSE = LVDS 888 panel in LDI mode
+ ///< @li TRUE = LVDS 888 panel in FPDI mode
+ ///< @BldCfgItem{BLDCFG_LVDS_MISC_888_FPDI_MODE}
+ IN UINT8 DlChSwap:1; ///< This item configures LVDS panel lower and upper link mapping
+ ///< @li FALSE = Lower link and upper link not swap
+ ///< @li TRUE = Lower link and upper link are swapped
+ ///< @BldCfgItem{BLDCFG_LVDS_MISC_DL_CH_SWAP}
+ IN UINT8 BitDepth:1; ///< Customer may use 888 bit LVDS panel, but the LVDS panel EDID does not support v1.4 so that VBIOS can not decide the panel bit per color
+ ///< @li FALSE = LCD 666 18bit panel
+ ///< @li TRUE = LCD 888 24bit panel
+ ///< @BldCfgItem{BLDCFG_LVDS_BIT_DEPTH}
+ IN UINT8 ParamOverwriteEn:1; ///< LVDS parameter overwrite enable
+ ///< @li FALSE = LVDS parameter overwrite disable
+ ///< @li TRUE = LVDS parameter overwrite enable
+ ///< @BldCfgItem{BLDCFG_LVDS_PARAM_OVERWRITE_EN}
+ IN UINT8 BLONActiveLow:1; ///< This item configures polarity of signal sent to digital BLON output pin
+ ///< @li FALSE = Not inverted(active high)
+ ///< @li TRUE = Inverted (active low)
+ ///< @BldCfgItem{BLDCFG_LVDS_MISC_BLON_ACTIVE_LOW}
+ IN UINT8 LvdsVoltOverwriteEn:1; ///< This item configures polarity of DP-to-LVDS output voltage overwrite
+ ///< @li FALSE = DP-to-LVDS output voltage overwrite disable, use VBIOS default setting.
+ ///< @li TRUE = Use ucLVDSVolAdjust value to program register LVDS_CTRL_4
+ ///< @BldCfgItem{BLDCFG_LVDS_MISC_VOLT_OVERWRITE_ENABLE}
+ IN UINT8 Reserved:2; ///< Reserved
+} LVDS_MISC_CONTROL_FIELD;
+
+/// LVDS Misc Control
+typedef union _LVDS_MISC_CONTROL {
+ IN LVDS_MISC_CONTROL_FIELD Field; ///< LVDS_MISC_CONTROL_FIELD
+ IN UINT8 Value; ///< LVDS Misc Control Value
+} LVDS_MISC_CONTROL;
+
+/// Display Misc Control Field
+typedef struct {
+ IN UINT8 Reserved1:3; ///< Reserved
+ IN UINT8 VbiosFastBootEn:1; ///< This item configures VBIOS skip display device detection in every set mode if LCD panel is connect and LID is open.
+ ///< @li FALSE = VBIOS fast boot is disable.
+ ///< @li TRUE = VBIOS fast boot is enable.
+ ///< @BldCfgItem{BLDCFG_DISPLAY_MISC_VBIOS_FAST_BOOT_ENABLE}
+ IN UINT8 Reserved2:4; ///< Reserved
+} DISPLAY_MISC_CONTROL_FIELD;
+
+/// LVDS Misc Control
+typedef union _DISPLAY_MISC_CONTROL {
+ IN DISPLAY_MISC_CONTROL_FIELD Field; ///< DISPLAY_MISC_CONTROL_FIELD
+ IN UINT8 Value; ///< Display Misc Control Value
+} DISPLAY_MISC_CONTROL;
+
+/// HD Audio Codec table list
+typedef struct _CODEC_VERB_TABLE_LIST {
+ IN UINT32 CodecId; ///< CodecID - Codec ID
+ IN UINT32 CodecTablePtr; ///< CodecTablePtr - Codec table pointer
+} CODEC_VERB_TABLE_LIST;
+
+/// POST Configuration settings for GNB.
+typedef struct {
+ IN UINT8 IgpuEnableDisablePolicy; ///< This item defines the iGPU Enable/Disable policy
+ ///< @li 0 = Auto - use existing default -
+ ///< @li 1 = Disable iGPU if any PCIe/PCI graphics card present
+ ///< @BldCfgItem{BLDCFG_IGPU_ENABLE_DISABLE_POLICY}
+} GNB_POST_CONFIGURATION;
+
+/// iGPU Enable/Disable Policy values
+#define IGPU_DISABLE_AUTO 0 ///< Auto setting - disable iGPU if ANY PCI graphics or non-AMD PCIe graphics
+#define IGPU_DISABLE_ANY_PCIE 1 ///< Disable iGPU if any PCI or PCIE graphics card is present
+
+/// ENV Configuration settings for GNB.
+typedef struct {
+ IN UINT8 Gnb3dStereoPinIndex; ///< 3D Stereo Pin ID.
+ ///< @li 0 = Stereo 3D is disabled (default).
+ ///< @li 1 = Use processor pin HPD1.
+ ///< @li 2 = Use processor pin HPD2
+ ///< @li 3 = Use processor pin HPD3
+ ///< @li 4 = Use processor pin HPD4
+ ///< @li 5 = Use processor pin HPD5
+ ///< @li 6 = Use processor pin HPD6
+ ///< @BldCfgItem{BLDCFG_STEREO_3D_PINOUT}
+ IN BOOLEAN IommuSupport; ///< IOMMU support.
+ ///< @li FALSE = Disabled. Disable and hide IOMMU device.
+ ///< @li TRUE = Initialize IOMMU subsystem. Generate ACPI IVRS table.
+ ///< BldCfgItem{BLDCFG_IOMMU_SUPPORT}
+ IN UINT16 LvdsSpreadSpectrum; ///< Spread spectrum value in 0.01 %
+ ///< BldCfgItem{BLDCFG_GFX_LVDS_SPREAD_SPECTRUM}
+ IN UINT16 LvdsSpreadSpectrumRate; ///< Spread spectrum frequency used by SS hardware logic in unit of 10Hz, 0 - default frequency 40kHz
+ ///< BldCfgItem{BLDCFG_GFX_LVDS_SPREAD_SPECTRUM_RATE}
+ IN UINT8 LvdsPowerOnSeqDigonToDe; ///< This item configures panel initialization timing.
+ ///< @BldCfgItem{BLDCFG_LVDS_POWER_ON_SEQ_DIGON_TO_DE}
+ IN UINT8 LvdsPowerOnSeqDeToVaryBl; ///< This item configures panel initialization timing.
+ ///< @BldCfgItem{BLDCFG_LVDS_POWER_ON_SEQ_DE_TO_VARY_BL}
+ IN UINT8 LvdsPowerOnSeqDeToDigon; ///< This item configures panel initialization timing.
+ ///< @BldCfgItem{BLDCFG_LVDS_POWER_ON_SEQ_DE_TO_DIGON}
+ IN UINT8 LvdsPowerOnSeqVaryBlToDe; ///< This item configures panel initialization timing.
+ ///< @BldCfgItem{BLDCFG_LVDS_POWERS_ON_SEQ_VARY_BL_TO_DE}
+ IN UINT8 LvdsPowerOnSeqOnToOffDelay; ///< This item configures panel initialization timing.
+ ///< @BldCfgItem{BLDCFG_LVDS_POWER_ON_SEQ_ON_TO_OFF_DELAY}
+ IN UINT8 LvdsPowerOnSeqVaryBlToBlon; ///< This item configures panel initialization timing.
+ ///< @BldCfgItem{BLDCFG_LVDS_POWER_ON_SEQ_VARY_BL_TO_BLON}
+ IN UINT8 LvdsPowerOnSeqBlonToVaryBl; ///< This item configures panel initialization timing.
+ ///< @BldCfgItem{BLDCFG_LVDS_POWER_ON_SEQ_BLON_TO_VARY_BL}
+ IN UINT16 LvdsMaxPixelClockFreq; ///< This item configures the maximum pixel clock frequency supported.
+ ///< @BldCfgItem{BLDCFG_LVDS_MAX_PIXEL_CLOCK_FREQ}
+ IN UINT32 LcdBitDepthControlValue; ///< This item configures the LCD bit depth control settings.
+ ///< @BldCfgItem{BLDCFG_LCD_BIT_DEPTH_CONTROL_VALUE}
+ IN UINT8 Lvds24bbpPanelMode; ///< This item configures the LVDS 24 BBP mode.
+ ///< @BldCfgItem{BLDCFG_LVDS_24BBP_PANEL_MODE}
+ IN LVDS_MISC_CONTROL LvdsMiscControl;///< This item configures LVDS swap/Hsync/Vsync/BLON
+ IN UINT16 PcieRefClkSpreadSpectrum; ///< Spread spectrum value in 0.01 %
+ ///< @BldCfgItem{BLDCFG_PCIE_REFCLK_SPREAD_SPECTRUM}
+ IN BOOLEAN GnbRemoteDisplaySupport; ///< This item enables Wireless Display Support
+ ///< @li TRUE = Enable Wireless Display Support
+ ///< @li FALSE = Disable Wireless Display Support
+ ///< @BldCfgItem{BLDCFG_REMOTE_DISPLAY_SUPPORT}
+ IN UINT8 LvdsMiscVoltAdjustment; ///< Register LVDS_CTRL_4 to adjust LVDS output voltage
+ ///< @BldCfgItem{BLDCFG_LVDS_MISC_VOL_ADJUSTMENT}
+ IN DISPLAY_MISC_CONTROL DisplayMiscControl;///< This item configures display misc control
+ IN DP_FIXED_VOLT_SWING_TYPE DpFixedVoltSwingType;///< To indicate fixed voltage swing value
+ ///< @BldCfgItem{BLDCFG_DP_FIXED_VOLT_SWING}
+ IN UINT32 GpuFrequencyLimit; ///< GNB GPU Max Frequency(NULL if platform configured)
+ ///< @BldCfgItem{BLDCFG_GPU_FREQUENCY_LIMIT}
+ IN UINT8 EDPv1_4VSMode; ///< @BldCfgItem{BLDCFG_EDP_V1_4_VS_MODE}
+ IN UINT8 ExtHDMIReDrvSlvAddr; ///< @BldCfgItem{BLDCFG_EXT_HDMI_RE_DRIVE_SLAVE_ADDR}
+ IN UINT8 ExtHDMIReDrvRegNum; ///< @BldCfgItem{BLDCFG_EXT_HDMI_RE_DRIVE_REG_NUM}
+ IN UINT64 ExtHDMIRegSetting; ///< @BldCfgItem{BLDCFG_EXT_HDMI_RE_DRIVE_REG_INFO}
+} GNB_ENV_CONFIGURATION;
+
+/// Configuration settings for GNB.
+typedef struct {
+ IN UINT8 iGpuVgaMode; ///< VGA resources decoding configuration for iGPU
+ ///< @li 0 = iGPU decode all VGA resources (must be primary VGA adapter)
+ ///< @li 1 = iGPU will not decode any VGA resources (must be secondary graphics adapter)
+ IN UINT8 PcieAcsCapability; ///< Pcie ACS Capability support
+ ///< @li 0 = Disabled
+ ///< @li 1 = Enabled
+ IN UINT64 GnbIoapicAddress; ///< GNB IOAPIC Base Address(NULL if platform configured)
+ ///< @BldCfgItem{BLDCFG_GNB_IOAPIC_ADDRESS}
+ IN UINT8 MaxNumAudioEndpoints; ///< Max number of audio endpoints
+ ///< @BldCfgItem{BLDCFG_MAX_NUM_AUDIO_ENDPOINTS}
+} GNB_MID_CONFIGURATION;
+
+/// GNB configuration info
+typedef struct {
+ IN const PCIe_COMPLEX_DESCRIPTOR *PcieComplexList; /**< Pointer to array of structures describe PCIe topology on each processor package or NULL.
+ * Last element of array must be terminated with DESCRIPTOR_TERMINATE_LIST
+ * Example of topology definition for single socket system:
+ * @code
+ * PCIe_PORT_DESCRIPTOR PortList [] = {
+ * // Initialize Port descriptor (PCIe port, Lanes 8:15, PCI Device Number 2, ...)
+ * {
+ * 0, //Descriptor flags
+ * PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 8, 15),
+ * PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 2, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0)
+ * },
+ * // Initialize Port descriptor (PCIe port, Lanes 16:19, PCI Device Number 3, ...)
+ * {
+ * 0, //Descriptor flags
+ * PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 16, 19),
+ * PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 3, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0)
+ * },
+ * // Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...)
+ * {
+ * DESCRIPTOR_TERMINATE_LIST, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array
+ * PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 4),
+ * PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 4, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0)
+ * }
+ * };
+ * PCIe_PORT_DESCRIPTOR DdiList [] = {
+ * // Initialize Ddi descriptor (DDI interface Lanes 24:27, Display Port Connector, ...)
+ * {
+ * 0, //Descriptor flags
+ * PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 24, 27),
+ * PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux1, Hdp1, 0)
+ * },
+ * // Initialize Ddi descriptor (DDI interface Lanes 28:31, HDMI, ...)
+ * {
+ * DESCRIPTOR_TERMINATE_LIST, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array
+ * PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 28, 31),
+ * PCIE_DDI_DATA_INITIALIZER (ConnectorTypeHDMI, Aux2, Hdp2, 0)
+ * }
+ * };
+ * PCIe_COMPLEX_DESCRIPTOR PlatformTopology = {
+ * DESCRIPTOR_TERMINATE_LIST, //Descriptor flags !!!IMPORTANT!!! Terminate complexes list
+ * 0, //Socket ID
+ * &PortList[0],
+ * &DdiList[0],
+ * }
+ * @endcode
+ */
+ IN UINT8 PsppPolicy; /**< PSPP (PCIe Speed Power Policy)
+ * @li @b 0 - Disabled
+ * @li @b 1 - Performance
+ * @li @b 2 - Balance-High
+ * @li @b 3 - Balance-Low
+ * @li @b 4 - Power Saving
+ */
+
+} GNB_CONFIGURATION;
+
+/// Late Configuration settings for GNB.
+typedef struct {
+ IN BOOLEAN Reserved; ///< Reserved -- Docked TDP headroom
+ IN UINT8 GnbIoapicId; ///< GNB IOAPIC ID, platform BIOS needs to pass correct id number, default is 0xFF.
+ ///< If BLDCFG_GNB_IOAPIC_ADDRESS == NULL or BLDCFG_IOMMU_SUPPORT == NULL or GnbIoapicId == default(0xFF), AGESA will skip it anyway.
+ ///< @li 0~n = IOAPIC ID number for IVRS which should be matched with MADT
+ IN UINT8 FchIoapicId; ///< Fch IOAPIC ID, platform BIOS needs to pass correct id number, default is 0xFF.
+ ///< If BLDCFG_IOMMU_SUPPORT == NULL or or FchIoapicId == default(0xFF), AGESA will skip it anyway.
+ ///< @li 0~n = IOAPIC ID number for IVRS which should be matched with MADT
+
+} GNB_LATE_CONFIGURATION;
+
+//
+// MEMORY-SPECIFIC DATA STRUCTURES
+//
+//
+//
+//
+// AGESA MAXIMIUM VALUES
+//
+// These Max values are used to define array sizes and associated loop
+// counts in the code. They reflect the maximum values that AGESA
+// currently supports and does not necessarily reflect the hardware
+// capabilities of configuration.
+//
+
+#define MAX_SOCKETS_SUPPORTED 1 ///< Max number of sockets in system
+#define MAX_CHANNELS_PER_SOCKET 4 ///< Max Channels per sockets
+#define MAX_DIMMS_PER_CHANNEL 4 ///< Max DIMMs on a memory channel (independent of platform)
+#define NUMBER_OF_DELAY_TABLES 9 ///< Number of tables defined in CH_DEF_STRUCT.
+ ///< Eg: UINT16 *RcvEnDlys;
+ ///< UINT8 *WrDqsDlys;
+ ///< UINT8 *RdDqsDlys;
+ ///< UINT8 *WrDatDlys;
+ ///< UINT8 *RdDqsMinDlys;
+ ///< UINT8 *RdDqsMaxDlys;
+ ///< UINT8 *WrDatMinDlys;
+ ///< UINT8 *WrDatMaxDlys;
+#define NUMBER_OF_FAILURE_MASK_TABLES 1 ///< Number of failure mask tables
+
+#define MAX_PLATFORM_TYPES 16 ///< Platform types per system
+
+#define MCT_TRNG_KEEPOUT_START 0x00004000ul ///< base [39:8]
+#define MCT_TRNG_KEEPOUT_END 0x00007FFFul ///< base [39:8]
+#define DATAEYE_VREF_RANGE 31 ///< Number of VREF steps in Data Eye Bitmap
+
+#define UMA_ATTRIBUTE_INTERLEAVE 0x80000000ul ///< Uma Region is interleaved
+#define UMA_ATTRIBUTE_ON_DCT0 0x40000000ul ///< UMA resides on memory that belongs to DCT0
+#define UMA_ATTRIBUTE_ON_DCT1 0x20000000ul ///< UMA resides on memory that belongs to DCT1
+#define UMA_ATTRIBUTE_ON_DCT2 0x10000000ul ///< UMA resides on memory that belongs to DCT2
+#define UMA_ATTRIBUTE_ON_DCT3 0x08000000ul ///< UMA resides on memory that belongs to DCT3
+
+typedef UINT8 PSO_TABLE; ///< Platform Configuration Table
+
+// AGESA DEFINITIONS
+//
+// Many of these are derived from the platform and hardware specific definitions
+
+/// EccSymbolSize override value
+#define ECCSYMBOLSIZE_USE_BKDG 0 ///< Use BKDG Recommended Value
+#define ECCSYMBOLSIZE_FORCE_X4 4 ///< Force to x4
+#define ECCSYMBOLSIZE_FORCE_X8 8 ///< Force to x8
+/// CPU Package Type
+#define PT_L1 0 ///< L1 Package type
+#define PT_M2 1 ///< AM Package type
+#define PT_S1 2 ///< S1 Package type
+
+/// Build Configuration values for BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT & BLDCFG_MEMORY_CLOCK_SELECT
+#define DDR400_FREQUENCY 200 ///< DDR 400
+#define DDR533_FREQUENCY 266 ///< DDR 533
+#define DDR667_FREQUENCY 333 ///< DDR 667
+#define DDR800_FREQUENCY 400 ///< DDR 800
+#define DDR1066_FREQUENCY 533 ///< DDR 1066
+#define DDR1333_FREQUENCY 667 ///< DDR 1333
+#define DDR1600_FREQUENCY 800 ///< DDR 1600
+#define DDR1866_FREQUENCY 933 ///< DDR 1866
+#define DDR2100_FREQUENCY 1050 ///< DDR 2100
+#define DDR2133_FREQUENCY 1066 ///< DDR 2133
+#define DDR2400_FREQUENCY 1200 ///< DDR 2400
+#define UNSUPPORTED_DDR_FREQUENCY 1201 ///< Highest limit of DDR frequency
+
+/// Build Configuration values for BLDCFG_TIMING_MODE_SELECT
+#define TIMING_MODE_AUTO 0 ///< Use best rate possible
+#define TIMING_MODE_LIMITED 1 ///< Set user top limit
+#define TIMING_MODE_SPECIFIC 2 ///< Set user specified speed
+
+/// Build Configuration values for BLDCFG_MEMORY_QUADRANK_TYPE
+#define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM
+#define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM
+
+/// Build Configuration values for BLDCFG_POWER_DOWN_MODE
+#define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode
+#define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode
+#define POWER_DOWN_MODE_AUTO 2 ///< AGESA to select power down mode
+
+/// Build Configuration limit for BLDCFG_GNB_GPU_MAX_FREQUENCY
+#define UNSUPPORTED_GPU_FREQUENCY 901 ///< Highest limit of GPU frequency
+
+/// Structures use to pass system Logical CPU-ID
+typedef struct {
+ IN OUT UINT16 Family; ///< Indicates logical ID Family
+ IN OUT UINT16 Revision; ///< Indicates logical ID Family
+} CPU_LOGICAL_ID;
+
+/// Structures use to report AMP status
+typedef struct {
+ OUT BOOLEAN AmpVoltageValid; ///< Indicates if Amp voltage is valid
+ OUT BOOLEAN AmpSupportDetectedButNotEnabled; ///< Indicates if Amp support is detected but not enabled
+ OUT BOOLEAN AmpSelectedButNotEnabled; ///< Indicates if Amp is selected but not enabled
+} AMP_STATUS;
+
+/// Normalized Critical Composite Data Eye
+/// Bit 15 represents trained eye Center
+/// Bit 0 represents eye center -15 delay steps
+/// Bit 31 represents eye center +16 delay steps
+/// Offset 0 represents +15 Vref Steps
+/// Offset 31 represents -15 Vref Steps
+typedef UINT32 COMPOSITE_DATAEYE[DATAEYE_VREF_RANGE];
+
+/// Build Configuration values for BLDCFG_AMD_PLATFORM_TYPE
+typedef enum {
+ AMD_PLATFORM_SERVER = 0x8000, ///< Server
+ AMD_PLATFORM_DESKTOP = 0x10000, ///< Desktop
+ AMD_PLATFORM_MOBILE = 0x20000, ///< Mobile
+} AMD_PLATFORM_TYPE;
+
+/// Dram technology type
+typedef enum {
+ DDR2_TECHNOLOGY, ///< DDR2 technology
+ DDR3_TECHNOLOGY, ///< DDR3 technology
+ GDDR5_TECHNOLOGY, ///< GDDR5 technology
+ UNSUPPORTED_TECHNOLOGY, ///< Unsupported technology
+} TECHNOLOGY_TYPE;
+
+/// Low voltage support
+typedef enum {
+ VOLT_INITIAL, ///< Initial value for VDDIO
+ VOLT1_5, ///< 1.5 Volt
+ VOLT1_35, ///< 1.35 Volt
+ VOLT1_25, ///< 1.25 Volt
+ VOLT_UNSUPPORTED = 0xFF ///< No common voltage found
+} DIMM_VOLTAGE;
+
+/// AMP voltage support
+typedef enum {
+ AMP_VOLT_RSVD, ///< Reserved
+ AMP_VOLT1_5, ///< 1.5 Volt
+ AMP_VOLT1_55, ///< 1.55 Volt
+ AMP_VOLT1_6, ///< 1.6 Volt
+ AMP_VOLT1_65, ///< 1.65 Volt
+ AMP_VOLT1_7, ///< 1.7 Volt
+ AMP_VOLT1_75, ///< 1.75 Volt
+ AMP_VOLT1_8, ///< 1.8 Volt
+ AMP_VOLT1_85, ///< 1.85 Volt
+ AMP_VOLT1_9, ///< 1.9 Volt
+ AMP_VOLT1_45 = 0x10, ///< 1.45 Volt
+ AMP_VOLT1_4 = 0x20, ///< 1.4 Volt
+ AMP_VOLT1_35 = 0x30, ///< 1.35 Volt
+ AMP_VOLT1_3 = 0x40, ///< 1.3 Volt
+ AMP_VOLT1_25 = 0x50, ///< 1.25 Volt
+ AMP_VOLT1_2 = 0x60 ///< 1.2 Volt
+} AMP_DIMM_VOLTAGE;
+
+/// Build Configuration values for BLDCFG_RESOLUTION
+typedef enum {
+ DISPLAY_1920x1080_And_Below = 0, ///< 1920x1080 and below
+ DISPLAY_2560x1600 = 1, ///< 2560x1600
+ DISPLAY_3840x2160 = 2 ///< 3840x2160
+} DISPLAY_RESOLUTION;
+
+/// Build Configuration values for BLDCFG_ACP_SIZE
+typedef enum {
+ NO_ACP_SIZE = 0x00, ///< NO ACP
+ ACP_SIZE_2MB = 0x20, ///< UMA 4MB aligned
+ ACP_SIZE_4MB = 0x40, ///< UMA 128MB aligned
+} ACP_SIZE;
+
+/// UMA Version
+typedef enum {
+ UMA_LEGACY = 0, ///< UMA Legacy Version
+ UMA_NON_LEGACY = 1 ///< UMA Non Legacy Version
+} UMA_VERSION;
+
+/// UMA Mode
+typedef enum {
+ UMA_NONE = 0, ///< UMA None
+ UMA_SPECIFIED = 1, ///< UMA Specified
+ UMA_AUTO = 2 ///< UMA Auto
+} UMA_MODE;
+
+/// Force Training Mode
+typedef enum {
+ FORCE_TRAIN_1D = 0, ///< 1D Training only
+ FORCE_TRAIN_2D = 1, ///< 2D Training only
+ FORCE_TRAIN_AUTO = 2 ///< Auto - 1D or 2D depending on configuration
+} FORCE_TRAIN_MODE;
+
+/// PMU Training Mode
+typedef enum {
+ PMU_TRAIN_1D = 0, ///< PMU 1D Training only
+ PMU_TRAIN_1D_2D_READ = 1, ///< PMU 1D and 2D Training read only
+ PMU_TRAIN_1D_2D = 2, ///< PMU 1D and 2D Training
+ PMU_TRAIN_AUTO = 3 ///< Auto - PMU Training depend on configuration
+} PMU_TRAIN_MODE;
+
+/// The possible DRAM prefetch mode settings.
+typedef enum {
+ DRAM_PREFETCHER_AUTO, ///< Use the recommended setting for the processor. In most cases, the recommended setting is enabled.
+ DISABLE_DRAM_PREFETCH_FOR_IO, ///< Disable DRAM prefetching for I/O requests only.
+ DISABLE_DRAM_PREFETCH_FOR_CPU, ///< Disable DRAM prefetching for requests from processor cores only.
+ DISABLE_DRAM_PREFETCHER, ///< Disable DRAM prefetching.
+ MAX_DRAM_FREFETCH_MODE ///< Not a DRAM prefetch mode, use for limit checking.
+} DRAM_PREFETCH_MODE;
+
+/// Build Configuration values for BLDCFG_UMA_ALIGNMENT
+typedef enum {
+ NO_UMA_ALIGNED = 0x00FFFFFF, ///< NO UMA aligned
+ UMA_4MB_ALIGNED = 0x00FFFFC0, ///< UMA 4MB aligned
+ UMA_128MB_ALIGNED = 0x00FFF800, ///< UMA 128MB aligned
+ UMA_256MB_ALIGNED = 0x00FFF000, ///< UMA 256MB aligned
+ UMA_512MB_ALIGNED = 0x00FFE000, ///< UMA 512MB aligned
+} UMA_ALIGNMENT;
+
+///
+/// Global MCT Configuration Status Word (GStatus)
+///
+typedef enum {
+ GsbMTRRshort, ///< Ran out of MTRRs while mapping memory
+ GsbAllECCDimms, ///< All banks of all Nodes are ECC capable
+ GsbDramECCDis, ///< Dram ECC requested but not enabled.
+ GsbSoftHole, ///< A Node Base gap was created
+ GsbHWHole, ///< A HW dram remap was created
+ GsbNodeIntlv, ///< Node Memory interleaving was enabled
+ GsbSpIntRemapHole, ///< Special condition for Node Interleave and HW remapping
+ GsbEnDIMMSpareNW, ///< Indicates that DIMM Spare can be used without a warm reset
+
+ GsbEOL ///< End of list
+} GLOBAL_STATUS_FIELD;
+
+///
+/// Local Error Status (DIE_STRUCT.ErrStatus[31:0])
+///
+typedef enum {
+ EsbNoDimms, ///< No DIMMs
+ EsbSpdChkSum, ///< SPD Checksum fail
+ EsbDimmMismatchM, ///< dimm module type(buffer) mismatch
+ EsbDimmMismatchT, ///< dimm CL/T mismatch
+ EsbDimmMismatchO, ///< dimm organization mismatch (128-bit)
+ EsbNoTrcTrfc, ///< SPD missing Trc or Trfc info
+ EsbNoCycTime, ///< SPD missing byte 23 or 25
+ EsbBkIntDis, ///< Bank interleave requested but not enabled
+ EsbDramECCDis, ///< Dram ECC requested but not enabled
+ EsbSpareDis, ///< Online spare requested but not enabled
+ EsbMinimumMode, ///< Running in Minimum Mode
+ EsbNoRcvrEn, ///< No DQS Receiver Enable pass window found
+ EsbSmallRcvr, ///< DQS Rcvr En pass window too small (far right of dynamic range)
+ EsbNoDqsPos, ///< No DQS-DQ passing positions
+ EsbSmallDqs, ///< DQS-DQ passing window too small
+ EsbDCBKScrubDis, ///< DCache scrub requested but not enabled
+
+ EsbEMPNotSupported, ///< Processor is not capable for EMP.
+ EsbEMPConflict, ///< EMP requested but cannot be enabled since
+ ///< channel interleaving, bank interleaving, or bank swizzle is enabled.
+ EsbEMPDis, ///< EMP requested but cannot be enabled since
+ ///< memory size of each DCT is not a power of two.
+
+ EsbEOL ///< End of list
+} ERROR_STATUS_FIELD;
+
+///
+/// Local Configuration Status (DIE_STRUCT.Status[31:0])
+///
+typedef enum {
+ SbRegistered, ///< All DIMMs are Registered
+ SbEccDimms, ///< All banks ECC capable
+ SbParDimms, ///< All banks Addr/CMD Parity capable
+ SbDiagClks, ///< Jedec ALL slots clock enable diag mode
+ Sb128bitmode, ///< DCT in 128-bit mode operation
+ Sb64MuxedMode, ///< DCT in 64-bit mux'ed mode.
+ Sb2TMode, ///< 2T CMD timing mode is enabled.
+ SbSWNodeHole, ///< Remapping of Node Base on this Node to create a gap.
+ SbHWHole, ///< Memory Hole created on this Node using HW remapping.
+ SbOver400Mhz, ///< DCT freq greater than or equal to 400MHz flag
+ SbDQSPosPass2, ///< Used for TrainDQSPos DIMM0/1, when freq greater than or equal to 400MHz
+ SbDQSRcvLimit, ///< Used for DQSRcvEnTrain to know we have reached the upper bound.
+ SbExtConfig, ///< Indicate the default setting for extended PCI configuration support
+ SbLrdimms, ///< All DIMMs are LRDIMMs
+
+ SbEOL ///< End of list
+} LOCAL_STATUS_FIELD;
+
+
+///< CPU MSR Register definitions ------------------------------------------
+#define SYS_CFG 0xC0010010ul
+#define TOP_MEM 0xC001001Aul
+#define TOP_MEM2 0xC001001Dul
+#define HWCR 0xC0010015ul
+#define NB_CFG 0xC001001Ful
+
+#define FS_BASE 0xC0000100ul
+#define IORR0_BASE 0xC0010016ul
+#define IORR0_MASK 0xC0010017ul
+#define BU_CFG 0xC0011023ul
+#define BU_CFG2 0xC001102Aul
+#define COFVID_STAT 0xC0010071ul
+#define TSC 0x10
+
+//-----------------------------------------------------------------------------
+///
+/// SPD Data for each DIMM.
+///
+typedef struct _SPD_DEF_STRUCT_DX {
+ IN BOOLEAN SpdValid; ///< Indicates that the SPD is valid
+ IN BOOLEAN DimmPresent; ///< Indicates that the DIMM is present and Data is valid
+ IN UINT32 Adderess; ///< SMBus Address
+ IN UINT8 Data[512]; ///< Buffer for 256 Bytes of SPD data from DIMM
+} SPD_DEF_STRUCT_DX;
+
+//-----------------------------------------------------------------------------
+///
+/// SPD Data for each DIMM.
+///
+typedef struct _SPD_DEF_STRUCT {
+ IN BOOLEAN DimmPresent; ///< Indicates that the DIMM is present and Data is valid
+ IN UINT8 Data[256]; ///< Buffer for 256 Bytes of SPD data from DIMM
+} SPD_DEF_STRUCT;
+
+//-----------------------------------------------------------------------------
+///
+/// VDDP_VDDR Voltage Info for Low Power DIMM
+///
+typedef struct _VDDP_VDDR_VOLTAGE {
+ IN BOOLEAN IsValid; ///< Indicates if daata is valid
+ IN UINT8 Voltage; ///< VDDP VDDR Voltage Value
+} VDDP_VDDR_VOLTAGE;
+
+///
+/// Channel Definition Structure.
+/// This data structure defines entries that are specific to the channel initialization
+///
+typedef struct _CH_DEF_STRUCT {
+ OUT UINT8 ChannelID; ///< Physical channel ID of a socket(0 = CH A, 1 = CH B, 2 = CH C, 3 = CH D)
+ OUT TECHNOLOGY_TYPE TechType; ///< Technology type of this channel
+ OUT UINT8 ChDimmPresent; ///< For each bit n 0..7, 1 = DIMM n is present.
+ ///< DIMM# Select Signal
+ ///< 0 MA0_CS_L[0, 1]
+ ///< 1 MB0_CS_L[0, 1]
+ ///< 2 MA1_CS_L[0, 1]
+ ///< 3 MB1_CS_L[0, 1]
+ ///< 4 MA2_CS_L[0, 1]
+ ///< 5 MB2_CS_L[0, 1]
+ ///< 6 MA3_CS_L[0, 1]
+ ///< 7 MB3_CS_L[0, 1]
+
+ OUT struct _DCT_STRUCT *DCTPtr; ///< Pointer to the DCT data of this channel.
+ OUT struct _DIE_STRUCT *MCTPtr; ///< Pointer to the node data of this channel.
+ OUT SPD_DEF_STRUCT *SpdPtr; ///< Pointer to the SPD data for this channel. (Setup by NB Constructor)
+ OUT SPD_DEF_STRUCT *DimmSpdPtr[MAX_DIMMS_PER_CHANNEL]; ///< Array of pointers to
+ ///< SPD Data for each Dimm. (Setup by Tech Block Constructor)
+ OUT UINT8 ChDimmValid; ///< For each bit n 0..3, 1 = DIMM n is valid and is/will be configured where 4..7 are reserved.
+ ///<
+ OUT UINT8 RegDimmPresent; ///< For each bit n 0..3, 1 = DIMM n is a registered DIMM where 4..7 are reserved.
+ OUT UINT8 LrDimmPresent; ///< For each bit n 0..3, 1 = DIMM n is Load Reduced DIMM where 4..7 are reserved.
+ OUT UINT8 SODimmPresent; ///< For each bit n 0..3, 1 = DIMM n is a SO-DIMM, where 4..7 are reserved.
+ OUT UINT8 Loads; ///< Number of devices loading bus
+ OUT UINT8 Dimms; ///< Number of DIMMs loading Channel
+ OUT UINT8 Ranks; ///< Number of ranks loading Channel DATA
+ OUT BOOLEAN SlowMode; ///< 1T or 2T CMD mode (slow access mode)
+ OUT BOOLEAN SlowModePs1; ///< 1T or 2T CMD mode (slow access mode) for Mem Pstate 1
+ ///< FALSE = 1T
+ ///< TRUE = 2T
+ ///< The following pointers will be pointed to dynamically allocated buffers.
+ ///< Each buffer is two dimensional (RowCount x ColumnCount) and is lay-outed as in below.
+ ///< Example: If DIMM and Byte based training, then
+ ///< XX is a value in Hex
+ ///< BYTE 0, BYTE 1, BYTE 2, BYTE 3, BYTE 4, BYTE 5, BYTE 6, BYTE 7, ECC BYTE
+ ///< Row1 - Logical DIMM0 XX XX XX XX XX XX XX XX XX
+ ///< Row2 - Logical DIMM1 XX XX XX XX XX XX XX XX XX
+ OUT UINT16 *RcvEnDlys; ///< DQS Receiver Enable Delays
+ OUT UINT8 *WrDqsDlys; ///< Write DQS delays (only valid for DDR3)
+ OUT UINT8 *RdDqsDlys; ///< Read Dqs delays
+ OUT UINT8 *WrDatDlys; ///< Write Data delays
+ OUT UINT8 *RdDqs2dDlys; ///< 2d Read DQS data
+ OUT UINT8 *RdDqsMinDlys; ///< Minimum Window for Read DQS
+ OUT UINT8 *RdDqsMaxDlys; ///< Maximum Window for Read DQS
+ OUT UINT8 *WrDatMinDlys; ///< Minimum Window for Write data
+ OUT UINT8 *WrDatMaxDlys; ///< Maximum Window for Write data
+ OUT UINT16 *RcvEnDlysMemPs1; ///< DQS Receiver Enable Delays for Mem Pstate 1
+ OUT UINT8 *WrDqsDlysMemPs1; ///< Write DQS delays (only valid for DDR3) for Mem Pstate 1
+ OUT UINT8 *RdDqsDlysMemPs1; ///< Read Dqs delays for Memory Pstate 1
+ OUT UINT8 *WrDatDlysMemPs1; ///< Write Data delays for Memory Pstate 1
+ OUT UINT8 *RdDqs2dDlysMemPs1; ///< 2d Read DQS data for Memory Pstate 1
+ OUT UINT8 *RdDqsMinDlysMemPs1; ///< Minimum Window for Read DQS for Memory Pstate 1
+ OUT UINT8 *RdDqsMaxDlysMemPs1; ///< Maximum Window for Read DQS for Memory Pstate 1
+ OUT UINT8 *WrDatMinDlysMemPs1; ///< Minimum Window for Write data for Memory Pstate 1
+ OUT UINT8 *WrDatMaxDlysMemPs1; ///< Maximum Window for Write data for Memory Pstate 1
+ OUT UINT8 RowCount; ///< Number of rows of the allocated buffer.
+ OUT UINT8 ColumnCount; ///< Number of columns of the allocated buffer.
+ OUT UINT8 *FailingBitMask; ///< Table of masks to Track Failing bits
+ OUT UINT8 *FailingBitMaskMemPs1; ///< Table of masks to Track Failing bits for Memory Pstate 1
+ OUT VOID *RdDataEyes; ///< Pointer to Read Data Eye Bitmaps
+ OUT VOID *WrDataEyes; ///< Pointer to Write Data Eye Bitmaps
+ OUT UINT32 DctOdcCtl; ///< Output Driver Strength (see BKDG FN2:Offset 9Ch, index 00h)
+ OUT UINT32 DctAddrTmg; ///< Address Bus Timing (see BKDG FN2:Offset 9Ch, index 04h)
+ OUT UINT32 DctAddrTmgPs1; ///< Address Bus Timing (see BKDG FN2:Offset 9Ch, index 04h) for Mem Pstate 1
+ OUT UINT32 PhyRODTCSLow; ///< Phy Read ODT Pattern Chip Select low (see BKDG FN2:Offset 9Ch, index 180h)
+ OUT UINT32 PhyRODTCSHigh; ///< Phy Read ODT Pattern Chip Select high (see BKDG FN2:Offset 9Ch, index 181h)
+ OUT UINT32 PhyWODTCSLow; ///< Phy Write ODT Pattern Chip Select low (see BKDG FN2:Offset 9Ch, index 182h)
+ OUT UINT32 PhyWODTCSHigh; ///< Phy Write ODT Pattern Chip Select high (see BKDG FN2:Offset 9Ch, index 183)
+ OUT UINT8 PhyWLODT[4]; ///< Write Levelization ODT Pattern for Dimm 0-3 or CS 0-7(see BKDG FN2:Offset 9Ch, index 0x8[11:8])
+ OUT UINT16 DctEccDqsLike; ///< DCT DQS ECC UINT8 like...
+ OUT UINT8 DctEccDqsScale; ///< DCT DQS ECC UINT8 scale
+ OUT UINT16 PtrPatternBufA; ///< Ptr on stack to aligned DQS testing pattern
+ OUT UINT16 PtrPatternBufB; ///< Ptr on stack to aligned DQS testing pattern
+ OUT UINT8 ByteLane; ///< Current UINT8 Lane (0..7)
+ OUT UINT8 Direction; ///< Current DQS-DQ training write direction (0=read, 1=write)
+ OUT UINT8 Pattern; ///< Current pattern
+ OUT UINT8 DqsDelay; ///< Current DQS delay value
+ OUT UINT16 HostBiosSrvc1; ///< UINT16 sized general purpose field for use by host BIOS. Scratch space.
+ OUT UINT32 HostBiosSrvc2; ///< UINT32 sized general purpose field for use by host BIOS. Scratch space.
+ OUT UINT16 DctMaxRdLat[4]; ///< Max Read Latency (ns) for the DCT
+ ///< DctMaxRdLat [i] is for NBPstate i
+ OUT UINT8 DIMMValidCh; ///< DIMM# in CH
+ OUT UINT8 MaxCh; ///< Max number of CH in system
+ OUT UINT8 Dct; ///< Dct pointer
+ OUT UINT8 WrDatGrossH; ///< Write Data Gross delay high value
+ OUT UINT8 DqsRcvEnGrossL; ///< DQS Receive Enable Gross Delay low
+
+ OUT UINT8 TrwtWB; ///< Non-SPD timing value for TrwtWB
+ OUT UINT8 CurrRcvrDctADelay; ///< for keep current RcvrEnDly
+ OUT UINT16 T1000; ///< get the T1000 figure (cycle time (ns) * 1K)
+ OUT UINT8 DqsRcvEnPass; ///< for TrainRcvrEn UINT8 lane pass flag
+ OUT UINT8 DqsRcvEnSaved; ///< for TrainRcvrEn UINT8 lane saved flag
+ OUT UINT8 SeedPass1Remainder; ///< for Phy assisted DQS receiver enable training
+
+ OUT UINT8 ClToNbFlag; ///< is used to restore ClLinesToNbDis bit after memory
+ OUT UINT32 NodeSysBase; ///< for channel interleave usage
+ OUT UINT8 RefRawCard[MAX_DIMMS_PER_CHANNEL]; ///< Array of rawcards detected
+ OUT UINT8 CtrlWrd02[MAX_DIMMS_PER_CHANNEL]; ///< Control Word 2 values per DIMM
+ OUT UINT8 CtrlWrd03[MAX_DIMMS_PER_CHANNEL]; ///< Control Word 3 values per DIMM
+ OUT UINT8 CtrlWrd04[MAX_DIMMS_PER_CHANNEL]; ///< Control Word 4 values per DIMM
+ OUT UINT8 CtrlWrd05[MAX_DIMMS_PER_CHANNEL]; ///< Control Word 5 values per DIMM
+ OUT UINT8 CtrlWrd08[MAX_DIMMS_PER_CHANNEL]; ///< Control Word 8 values per DIMM
+
+ OUT UINT16 CsPresentDCT; ///< For each bit n 0..7, 1 = Chip-select n is present
+ OUT UINT8 DimmMirrorPresent; ///< For each bit n 0..3, 1 = DIMM n is OnDimmMirror capable where 4..7 are reserved.
+ OUT UINT8 DimmSpdCse; ///< For each bit n 0..3, 1 = DIMM n SPD checksum error where 4..7 are reserved.
+ OUT UINT8 DimmExclude; ///< For each bit n 0..3, 1 = DIMM n gets excluded where 4..7 are reserved.
+ OUT UINT8 DimmYr06; ///< Bitmap indicating which Dimms have a manufacturer's year code <= 2006
+ OUT UINT8 DimmWk2406; ///< Bitmap indicating which Dimms have a manufacturer's week code <= 24 of 2006 (June)
+ OUT UINT8 DimmPlPresent; ///< Bitmap indicating that Planar (1) or Stacked (0) Dimms are present.
+ OUT UINT8 DimmQrPresent; ///< QuadRank DIMM present?
+ OUT UINT8 DimmDrPresent; ///< Bitmap indicating that Dual Rank Dimms are present
+ OUT UINT8 DimmSRPresent; ///< Bitmap indicating that Single Rank Dimms are present
+ OUT UINT8 Dimmx4Present; ///< For each bit n 0..3, 1 = DIMM n contains x4 data devices. where 4..7 are reserved.
+ OUT UINT8 Dimmx8Present; ///< For each bit n 0..3, 1 = DIMM n contains x8 data devices. where 4..7 are reserved.
+ OUT UINT8 Dimmx16Present; ///< For each bit n 0..3, 1 = DIMM n contains x16 data devices. where 4..7 are reserved.
+ OUT UINT8 LrdimmPhysicalRanks[MAX_DIMMS_PER_CHANNEL];///< Number of Physical Ranks for LRDIMMs
+ OUT UINT8 LrDimmLogicalRanks[MAX_DIMMS_PER_CHANNEL];///< Number of LRDIMM Logical ranks in this configuration
+ OUT UINT8 LrDimmRankMult[MAX_DIMMS_PER_CHANNEL];///< Rank Multipication factor per dimm.
+ OUT UINT8 DimmNibbleAccess; ///< For each bit n 0..3, 1 = DIMM n will use nibble signaling. Where 4..7 are reserved.
+ OUT UINT8 *MemClkDisMap; ///< This pointer will be set to point to an array that describes
+ ///< the routing of M[B,A]_CLK pins to the DIMMs' ranks. AGESA will
+ ///< base on this array to disable unused MemClk to save power.
+ ///<
+ ///< The array must have 8 entries. Each entry, which associates with
+ ///< one MemClkDis bit, is a bitmap of 8 CS that that MemClk is routed to.
+ ///< Example:
+ ///< BKDG definition of Fn2x88[MemClkDis] bitmap for AM3 package
+ ///< is like below:
+ ///< Bit AM3/S1g3 pin name
+ ///< 0 M[B,A]_CLK_H/L[0]
+ ///< 1 M[B,A]_CLK_H/L[1]
+ ///< 2 M[B,A]_CLK_H/L[2]
+ ///< 3 M[B,A]_CLK_H/L[3]
+ ///< 4 M[B,A]_CLK_H/L[4]
+ ///< 5 M[B,A]_CLK_H/L[5]
+ ///< 6 M[B,A]_CLK_H/L[6]
+ ///< 7 M[B,A]_CLK_H/L[7]
+ ///< And platform has the following routing:
+ ///< CS0 M[B,A]_CLK_H/L[4]
+ ///< CS1 M[B,A]_CLK_H/L[2]
+ ///< CS2 M[B,A]_CLK_H/L[3]
+ ///< CS3 M[B,A]_CLK_H/L[5]
+ ///< Then MemClkDisMap should be pointed to the following array:
+ ///< CLK_2 CLK_3 CLK_4 CLK_5
+ ///< 0x00, 0x00, 0x02, 0x04, 0x01, 0x08, 0x00, 0x00
+ ///< Each entry of the array is the bitmask of 8 chip selects.
+
+ OUT UINT8 *CKETriMap; ///< This pointer will be set to point to an array that describes
+ ///< the routing of CKE pins to the DIMMs' ranks.
+ ///< The array must have 2 entries. Each entry, which associates with
+ ///< one CKE pin, is a bitmap of 8 CS that that CKE is routed to.
+ ///< AGESA will base on this array to disable unused CKE pins to save power.
+
+ OUT UINT8 *ODTTriMap; ///< This pointer will be set to point to an array that describes
+ ///< the routing of ODT pins to the DIMMs' ranks.
+ ///< The array must have 4 entries. Each entry, which associates with
+ ///< one ODT pin, is a bitmap of 8 CS that that ODT is routed to.
+ ///< AGESA will base on this array to disable unused ODT pins to save power.
+
+ OUT UINT8 *ChipSelTriMap; ///< This pointer will be set to point to an array that describes
+ ///< the routing of chip select pins to the DIMMs' ranks.
+ ///< The array must have 8 entries. Each entry is a bitmap of 8 CS.
+ ///< AGESA will base on this array to disable unused Chip select pins to save power.
+
+ OUT UINT8 DimmSRTPresent; ///< For each bit n 0..3, 1 = DIMM n supports Extended Temperature Range where 4..7 are reserved
+ OUT UINT8 DimmASRPresent; ///< For each bit n 0..3, 1 = DIMM n supports Auto Self Refresh where 4..7 are reserved
+
+ OUT BOOLEAN ExtendTmp; ///< If extended temperature is supported on all dimms on a channel.
+
+ OUT UINT8 MaxVref; ///< Maximum Vref Value for channel
+
+ OUT UINT8 Reserved[100]; ///< Reserved
+} CH_DEF_STRUCT;
+
+///
+/// DCT Channel Timing Parameters.
+/// This data structure sets timings that are specific to the channel.
+///
+typedef struct _CH_TIMING_STRUCT {
+ OUT UINT16 DctDimmValid; ///< For each bit n 0..3, 1=DIMM n is valid and is/will be configured where 4..7 are reserved.
+ OUT UINT16 DimmMirrorPresent; ///< For each bit n 0..3, 1=DIMM n is OnDimmMirror capable where 4..7 are reserved.
+ OUT UINT16 DimmSpdCse; ///< For each bit n 0..3, 1=DIMM n SPD checksum error where 4..7 are reserved.
+ OUT UINT16 DimmExclude; ///< For each bit n 0..3, 1 = DIMM n gets excluded where 4..7 are reserved.
+ OUT UINT16 CsPresent; ///< For each bit n 0..7, 1=Chip-select n is present
+ OUT UINT16 CsEnabled; ///< For each bit n 0..7, 1=Chip-select n is enabled
+ OUT UINT16 CsTestFail; ///< For each bit n 0..7, 1=Chip-select n is present but disabled
+ OUT UINT16 CsTrainFail; ///< Bitmap showing which chipselects failed training
+ OUT UINT16 DIMM1KPage; ///< For each bit n 0..3, 1=DIMM n contains 1K page devices. where 4..7 are reserved
+ OUT UINT16 DimmQrPresent; ///< QuadRank DIMM present?
+ OUT UINT16 DimmDrPresent; ///< Bitmap indicating that Dual Rank Dimms are present , where 4..7 are reserved
+ OUT UINT8 DimmSRPresent; ///< Bitmap indicating that Single Rank Dimms are present, where 4..7 are reserved
+ OUT UINT16 Dimmx4Present; ///< For each bit n 0..3, 1=DIMM n contains x4 data devices. where 4..7 are reserved
+ OUT UINT16 Dimmx8Present; ///< For each bit n 0..3, 1=DIMM n contains x8 data devices. where 4..7 are reserved
+ OUT UINT16 Dimmx16Present; ///< For each bit n 0..3, 1=DIMM n contains x16 data devices. where 4..7 are reserved
+
+ OUT UINT16 DIMMTrcd; ///< Minimax Trcd*40 (ns) of DIMMs
+ OUT UINT16 DIMMTrp; ///< Minimax Trp*40 (ns) of DIMMs
+ OUT UINT16 DIMMTrtp; ///< Minimax Trtp*40 (ns) of DIMMs
+ OUT UINT16 DIMMTras; ///< Minimax Tras*40 (ns) of DIMMs
+ OUT UINT16 DIMMTrc; ///< Minimax Trc*40 (ns) of DIMMs
+ OUT UINT16 DIMMTwr; ///< Minimax Twr*40 (ns) of DIMMs
+ OUT UINT16 DIMMTrrd; ///< Minimax Trrd*40 (ns) of DIMMs
+ OUT UINT16 DIMMTwtr; ///< Minimax Twtr*40 (ns) of DIMMs
+ OUT UINT16 DIMMTfaw; ///< Minimax Tfaw*40 (ns) of DIMMs
+ OUT UINT16 TargetSpeed; ///< Target DRAM bus speed in MHz
+ OUT UINT16 Speed; ///< DRAM bus speed in MHz
+ ///< 400 (MHz)
+ ///< 533 (MHz)
+ ///< 667 (MHz)
+ ///< 800 (MHz)
+ ///< and so on...
+ OUT UINT8 Trcpage; ///< DCT Trcpage (10 ns)
+ OUT UINT8 CasL; ///< CAS latency DCT setting (busclocks)
+ OUT UINT8 Trcd; ///< DCT Trcd (busclocks)
+ OUT UINT8 Trp; ///< DCT Trp (busclocks)
+ OUT UINT8 Trtp; ///< DCT Trtp (busclocks)
+ OUT UINT8 Tras; ///< DCT Tras (busclocks)
+ OUT UINT8 Trc; ///< DCT Trc (busclocks)
+ OUT UINT8 Twr; ///< DCT Twr (busclocks)
+ OUT UINT8 Trrd; ///< DCT Trrd (busclocks)
+ OUT UINT8 Twtr; ///< DCT Twtr (busclocks)
+ OUT UINT8 Tfaw; ///< DCT Tfaw (busclocks)
+ OUT UINT16 Trfc0; ///< DCT Logical DIMM0 Trfc (in ns)
+ OUT UINT16 Trfc1; ///< DCT Logical DIMM1 Trfc (in ns)
+ OUT UINT16 Trfc2; ///< DCT Logical DIMM2 Trfc (in ns)
+ OUT UINT16 Trfc3; ///< DCT Logical DIMM3 Trfc (in ns)
+ OUT UINT32 DctMemSize; ///< Base[47:16], total DRAM size controlled by this DCT.
+ ///<
+ OUT BOOLEAN SlowMode; ///< 1T or 2T CMD mode (slow access mode)
+ ///< FALSE = 1T
+ ///< TRUE = 2T
+ OUT UINT8 TrwtTO; ///< DCT TrwtTO (busclocks)
+ OUT UINT8 Twrrd; ///< DCT Twrrd (busclocks)
+ OUT UINT8 Twrwr; ///< DCT Twrwr (busclocks)
+ OUT UINT8 Trdrd; ///< DCT Trdrd (busclocks)
+ OUT UINT8 TrwtWB; ///< DCT TrwtWB (busclocks)
+ OUT UINT8 TrdrdSD; ///< DCT TrdrdSD (busclocks)
+ OUT UINT8 TwrwrSD; ///< DCT TwrwrSD (busclocks)
+ OUT UINT8 TwrrdSD; ///< DCT TwrrdSD (busclocks)
+ OUT UINT16 MaxRdLat0; ///< Max Read Latency 0
+ OUT UINT16 MaxRdLat1; ///< Max Read Latency 1
+ OUT UINT16 MaxRdLat2; ///< Max Read Latency 2
+ OUT UINT16 MaxRdLat3; ///< Max Read Latency 3
+ OUT UINT8 WrDatGrossH; ///< Temporary variables must be removed
+ OUT UINT8 DqsRcvEnGrossL; ///< Temporary variables must be removed
+} CH_TIMING_STRUCT;
+
+///
+/// Data for each DCT.
+/// This data structure defines data used to configure each DRAM controller.
+///
+typedef struct _DCT_STRUCT {
+ OUT UINT8 Dct; ///< Current Dct
+ OUT CH_TIMING_STRUCT Timings; ///< Channel Timing structure
+ OUT CH_TIMING_STRUCT *TimingsMemPs1; ///< Pointed to channel timing structure for memory Pstate 1
+ OUT CH_DEF_STRUCT *ChData; ///< Pointed to a dynamically allocated array of Channel structures
+ OUT UINT8 ChannelCount; ///< Number of channel per this DCT
+ OUT BOOLEAN BkIntDis; ///< Bank interleave requested but not enabled on current DCT
+ OUT UINT8 BankAddrMap; ///< Bank Address Mapping
+ OUT UINT8 EnabledChipSels; ///< Number of enabled chip selects on current DCT
+} DCT_STRUCT;
+
+
+///
+/// Data Structure defining each Die.
+/// This data structure contains information that is used to configure each Die.
+///
+typedef struct _DIE_STRUCT {
+
+ /// Advanced:
+
+ OUT UINT8 NodeId; ///< Node ID of current controller
+ OUT UINT8 SocketId; ///< Socket ID of this Die
+ OUT UINT8 DieId; ///< ID of this die relative to the socket
+ OUT PCI_ADDR PciAddr; ///< Pci bus and device number of this controller.
+ OUT AGESA_STATUS ErrCode; ///< Current error condition of Node
+ ///< 0x0 = AGESA_SUCCESS
+ ///< 0x1 = AGESA_UNSUPPORTED
+ ///< 0x2 = AGESA_BOUNDS_CHK
+ ///< 0x3 = AGESA_ALERT
+ ///< 0x4 = AGESA_WARNING
+ ///< 0x5 = AGESA_ERROR
+ ///< 0x6 = AGESA_CRITICAL
+ ///< 0x7 = AGESA_FATAL
+ ///<
+ OUT BOOLEAN ErrStatus[EsbEOL]; ///< Error Status bit Field
+ ///<
+ OUT BOOLEAN Status[SbEOL]; ///< Status bit Field
+ ///<
+ OUT UINT32 NodeMemSize; ///< Base[47:16], total DRAM size controlled by both DCT0 and DCT1 of this Node.
+ ///<
+ OUT UINT32 NodeSysBase; ///< Base[47:16] (system address) DRAM base address of this Node.
+ ///<
+ OUT UINT32 NodeHoleBase; ///< If not zero, Base[47:16] (system address) of dram hole for HW remapping. Dram hole exists on this Node
+ ///<
+ OUT UINT32 NodeSysLimit; ///< Base[47:16] (system address) DRAM limit address of this Node.
+ ///<
+ OUT UINT32 DimmPresent; ///< For each bit n 0..7, 1 = DIMM n is present.
+ ///< DIMM# Select Signal
+ ///< 0 MA0_CS_L[0, 1]
+ ///< 1 MB0_CS_L[0, 1]
+ ///< 2 MA1_CS_L[0, 1]
+ ///< 3 MB1_CS_L[0, 1]
+ ///< 4 MA2_CS_L[0, 1]
+ ///< 5 MB2_CS_L[0, 1]
+ ///< 6 MA3_CS_L[0, 1]
+ ///< 7 MB3_CS_L[0, 1]
+ ///<
+ OUT UINT32 DimmValid; ///< For each bit n 0..7, 1 = DIMM n is valid and is / will be configured
+ OUT UINT32 RegDimmPresent; ///< For each bit n 0..7, 1 = DIMM n is registered DIMM
+ OUT UINT32 LrDimmPresent; ///< For each bit n 0..7, 1 = DIMM n is Load Reduced DIMM
+ OUT UINT32 DimmEccPresent; ///< For each bit n 0..7, 1 = DIMM n is ECC capable.
+ OUT UINT32 DimmParPresent; ///< For each bit n 0..7, 1 = DIMM n is ADR/CMD Parity capable.
+ ///<
+ OUT UINT16 DimmTrainFail; ///< Bitmap showing which dimms failed training
+ OUT UINT16 ChannelTrainFail; ///< Bitmap showing the channel information about failed Chip Selects
+ ///< 0 in any bit field indicates Channel 0
+ ///< 1 in any bit field indicates Channel 1
+ OUT UINT8 Dct; ///< Need to be removed
+ ///< DCT pointer
+ OUT BOOLEAN GangedMode; ///< Ganged mode
+ ///< 0 = disabled
+ ///< 1 = enabled
+ OUT CPU_LOGICAL_ID LogicalCpuid; ///< The logical CPUID of the node
+ ///<
+ OUT UINT16 HostBiosSrvc1; ///< UINT16 sized general purpose field for use by host BIOS. Scratch space.
+ ///<
+ OUT UINT32 HostBiosSrvc2; ///< UINT32 sized general purpose field for use by host BIOS. Scratch space.
+ ///<
+ OUT UINT8 MLoad; ///< Need to be removed
+ ///< Number of devices loading MAA bus
+ ///<
+ OUT UINT8 MaxAsyncLat; ///< Legacy wrapper
+ ///<
+ OUT UINT8 ChbD3Rcvrdly; ///< Legacy wrapper
+ ///<
+ OUT UINT16 ChaMaxRdLat; ///< Max Read Latency (ns) for DCT 0
+ ///<
+ OUT UINT8 ChbD3BcRcvrdly; ///< CHB DIMM 3 Check UINT8 Receiver Enable Delay
+
+ OUT DCT_STRUCT *DctData; ///< Pointed to a dynamically allocated array of DCT_STRUCTs
+ OUT UINT8 DctCount; ///< Number of DCTs per this Die
+ OUT UINT8 Reserved[16]; ///< Reserved
+} DIE_STRUCT;
+
+/**********************************************************************
+ * S3 data block structure
+ **********************************************************************/
+/// AmdInitResume, AmdS3LateRestore, and AmdInitRtb param structure
+typedef struct {
+ OUT UINT32 Signature; ///< "ASTR" for AMD Suspend-To-RAM
+ OUT UINT16 Version; ///< S3 Params version number
+ IN OUT UINT32 Flags; ///< Indicates operation
+ IN OUT VOID *NvStorage; ///< Pointer to memory critical save state data
+ IN OUT UINT32 NvStorageSize; ///< Size in bytes of the NvStorage region
+ IN OUT VOID *VolatileStorage; ///< Pointer to remaining AMD save state data
+ IN OUT UINT32 VolatileStorageSize; ///< Size in bytes of the VolatileStorage region
+} S3_DATA_BLOCK;
+
+/// Header at the beginning of a context save buffer.
+typedef struct {
+ _2BYTE_ALIGN UINT16 Version; ///< Version of header
+ _4BYTE_ALIGN UINT32 Revision; ///< Revision of the S3 data blob
+ _2BYTE_ALIGN UINT16 NumDevices; ///< Number of devices in the list
+ _2BYTE_ALIGN UINT16 RelativeOrMaskOffset; ///< Size of device list + header
+ _4BYTE_ALIGN UINT32 BlobSize; ///<Size of the whole S3 data blob (including the header)
+ _4BYTE_ALIGN UINT32 NextBlockOffset; ///< Size of the whole device save context
+} DEVICE_BLOCK_HEADER;
+
+///===============================================================================
+/// MEM_PARAMETER_STRUCT
+/// This data structure is used to pass wrapper parameters to the memory configuration code
+///
+typedef struct _MEM_PARAMETER_STRUCT {
+
+ // Basic (Return parameters)
+ // (This section contains the outbound parameters from the memory init code)
+
+ OUT BOOLEAN GStatus[GsbEOL]; ///< Global Status bitfield.
+ ///<
+ OUT UINT32 HoleBase; ///< If not zero Base[47:16] (system address) of sub 4GB dram hole for HW remapping.
+ ///<
+ OUT UINT32 Sub4GCacheTop; ///< If not zero, the 32-bit top of cacheable memory.
+ ///<
+ OUT UINT32 Sub1THoleBase; ///< If not zero Base[47:16] (system address) of sub 1TB dram hole.
+ ///<
+ OUT UINT32 SysLimit; ///< Limit[47:16] (system address).
+ ///<
+ OUT DIMM_VOLTAGE DDR3Voltage; ///< Find support voltage and send back to platform BIOS.
+ ///<
+ OUT VDDP_VDDR_VOLTAGE VddpVddrVoltage; ///< For a given configuration, request is made to change the VDDP/VDDR
+ ///< voltage in platform BIOS via AgesaHookBeforeDramInit callout and
+ ///< MEM_PARAMETER_STRUCT.VddpVddrVoltage.Voltage parameter if
+ ///< MEM_PARAMETER_STRUCT.VddpVddrVoltage.IsValid is TRUE. The
+ ///< MEM_PARAMETER_STRUCT.VddpVddrVoltage.Voltage is defined in
+ ///< MEMORY_PHY_VOLTAGE
+ OUT UINT8 ExternalVrefValue; ///< Target reference voltage for external Vref for 2D training
+ ///<
+ OUT struct _MEM_DATA_STRUCT *MemData; ///< Access to global memory init data.
+
+ // Advanced (Optional parameters)
+ // Optional (all defaults values will be initialized by the
+ // 'AmdMemInitDataStructDef' based on AMD defaults. It is up
+ // to the IBV/OEM to change the defaults after initialization
+ // but prior to the main entry to the memory code):
+
+ // Memory Map/Mgt.
+
+ IN UINT16 BottomIo; ///< Bottom of 32-bit IO space (8-bits).
+ ///< NV_BOTTOM_IO[7:0]=Addr[31:24]
+ ///<
+ IN BOOLEAN MemHoleRemapping; ///< Memory Hole Remapping (1-bit).
+ ///< FALSE = disable
+ ///< TRUE = enable
+ ///<
+ IN BOOLEAN LimitMemoryToBelow1Tb; ///< Limit memory address space to below 1 TB
+ ///< FALSE = disable
+ ///< TRUE = enable
+ ///<
+ ///< @BldCfgItem{BLDCFG_LIMIT_MEMORY_TO_BELOW_1TB}
+
+ // Dram Timing
+
+ IN UINT32 UserTimingMode; ///< User Memclock Mode.
+ ///< @BldCfgItem{BLDCFG_TIMING_MODE_SELECT}
+
+ IN UINT32 MemClockValue; ///< Memory Clock Value.
+ ///< @BldCfgItem{BLDCFG_MEMORY_CLOCK_SELECT}
+
+ // Dram Configuration
+
+ IN BOOLEAN EnableBankSwapOnly; ///< Bank Swap Only
+ ///< - FALSE =disable (default)
+ ///< - TRUE = enable
+ ///<
+ ///< @BldCfgItem{BLDCFG_MEMORY_ENABLE_BANK_SWAP_ONLY}
+
+ IN BOOLEAN EnableBankIntlv; ///< Dram Bank (chip-select) Interleaving (1-bit).
+ ///< - FALSE =disable (default)
+ ///< - TRUE = enable
+ ///<
+ ///< @BldCfgItem{BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING}
+
+ IN BOOLEAN EnableNodeIntlv; ///< Node Memory Interleaving (1-bit).
+ ///< - FALSE = disable (default)
+ ///< - TRUE = enable
+ ///<
+ ///< @BldCfgItem{BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING}
+
+ IN BOOLEAN EnableChannelIntlv; ///< Channel Interleaving (1-bit).
+ ///< - FALSE = disable (default)
+ ///< - TRUE = enable
+ ///<
+ ///< @BldCfgItem{BLDCFG_MEMORY_CHANNEL_INTERLEAVING}
+ // DllPDBypassMode
+
+ IN BOOLEAN EnableDllPDBypassMode; ///< Enable low-power DDR phy operation. This feature is used for low-power
+ ///< solder-down DRAM motherboard designs with route matched CK/DQS/DQ signals.
+ ///< It limits maximim achieveable DDR rates on the platform and should not be
+ ///< enabled for systems requiring high DDR rate operation and/or DIMM-based systems.
+ ///< - FALSE = disable
+ ///< - TRUE = enable (default)
+ ///<
+ ///< @BldCfgItem{BLDCFG_DDR_PHY_DLL_BYPASS_MODE}
+ // ECC
+
+ IN BOOLEAN EnableEccFeature; ///< enable ECC error to go into MCE.
+ ///< - FALSE = disable (default)
+ ///< - TRUE = enable
+ ///<
+ ///< @BldCfgItem{BLDCFG_ENABLE_ECC_FEATURE}
+ // Dram Power
+
+ IN BOOLEAN EnablePowerDown; ///< CKE based power down mode (1-bit).
+ ///< - FALSE =disable (default)
+ ///< - TRUE =enable
+ ///<
+ ///< @BldCfgItem{BLDCFG_MEMORY_POWER_DOWN}
+
+ // Dram Mac Default
+
+ IN UINT8 DramMacDefault; ///< Default Maximum Activate Count
+ ///<
+ ///< @BldCfgItem{BLDCFG_MEMORY_ALTERNATIVE_MAX_ACTIVATE_COUNT}
+
+ // Dram Extended Temperature Range
+
+ IN BOOLEAN EnableExtendedTemperatureRange; ///< enable extended temperature support.
+ ///< - FALSE =disable (default)
+ ///< - TRUE =enable
+ ///<
+ ///< @BldCfgItem{BLDCFG_MEMORY_EXTENDED_TEMPERATURE_RANGE}
+ // Extended temperature range
+
+ // Online Spare
+
+ IN BOOLEAN EnableOnLineSpareCtl; ///< Chip Select Spare Control bit 0.
+ ///< - FALSE = disable Spare (default)
+ ///< - TRUE = enable Spare
+ ///<
+ ///< @BldCfgItem{BLDCFG_ONLINE_SPARE}
+
+ IN UINT8 *TableBasedAlterations; ///< Desired modifications to register settings.
+
+ IN PSO_TABLE *PlatformMemoryConfiguration;
+ ///< A table that contains platform specific settings.
+ ///< For example, MemClk routing, the number of DIMM slots per channel, ....
+ ///< AGESA initializes this pointer with DefaultPlatformMemoryConfiguration that
+ ///< contains default conservative settings. Platform BIOS can either tweak
+ ///< DefaultPlatformMemoryConfiguration or reassign this pointer to its own table.
+ ///<
+ IN BOOLEAN EnableParity; ///< Parity control.
+ ///< - TRUE = enable
+ ///< - FALSE = disable (default)
+ ///<
+ ///< @BldCfgItem{BLDCFG_MEMORY_PARITY_ENABLE}
+
+ IN BOOLEAN EnableBankSwizzle; ///< BankSwizzle control.
+ ///< - FALSE = disable
+ ///< - TRUE = enable (default)
+ ///<
+ ///< @BldCfgItem{BLDCFG_BANK_SWIZZLE}
+ ///<
+
+ IN BOOLEAN EnableMemClr; ///< Memory Clear functionality control.
+ ///< - FALSE = disable
+ ///< - TRUE = enable (default)
+ ///<
+ // Uma Configuration
+
+ IN UMA_VERSION UmaVersion; ///< Uma Version
+ ///< 0 = Legacy Version
+ ///< 1 = Non-Legacy Version
+ IN UMA_MODE UmaMode; ///< Uma Mode
+ ///< 0 = None
+ ///< 1 = Specified
+ ///< 2 = Auto
+ IN OUT UINT32 UmaSize; ///< The size of shared graphics dram (16-bits)
+ ///< NV_UMA_Size[31:0]=Addr[47:16]
+ ///<
+ OUT UINT32 UmaBase; ///< The allocated Uma base address (32-bits)
+ ///< NV_UMA_Base[31:0]=Addr[47:16]
+ ///<
+
+ /// Memory Restore Feature
+
+ IN BOOLEAN MemRestoreCtl; ///< Memory context restore control
+ ///< FALSE = perform memory init as normal (AMD default)
+ ///< TRUE = restore memory context and skip training. This requires
+ ///< MemContext is valid before AmdInitPost
+ ///<
+ IN BOOLEAN SaveMemContextCtl; ///< Control switch to save memory context at the end of MemAuto
+ ///< TRUE = AGESA will setup MemContext block before exit AmdInitPost
+ ///< FALSE = AGESA will not setup MemContext block. Platform is
+ ///< expected to call S3Save later in POST if it wants to
+ ///< use memory context restore feature.
+ ///<
+ IN OUT S3_DATA_BLOCK MemContext; ///< Memory context block describes the data that platform needs to
+ ///< save and restore for memory context restore feature to work.
+ ///< It uses the subset of S3Save block to save/restore. Hence platform
+ ///< may save only S3 block and uses it for both S3 resume and
+ ///< memory context restore.
+ ///< - If MemRestoreCtl is TRUE, platform needs to pass in MemContext
+ ///< before AmdInitPost.
+ ///< - If SaveMemContextCtl is TRUE, platform needs to save MemContext
+ ///< right after AmdInitPost.
+ ///<
+ IN BOOLEAN IsCapsuleMode; ///< Capsule reboot control
+ ///< FALSE = This is not a capsule reboot.
+ ///< TRUE = This is a capsule reboot.
+ ///<
+ IN BOOLEAN ExternalVrefCtl; ///< Control the use of external Vref
+ ///< TRUE = AGESA will use the function defined in "AGESA_EXTERNAL_VREF_CHANGE" in function list
+ ///< to change the vref
+ ///< FALSE = AGESA will will use the internal vref control.
+ ///< @BldCfgItem{BLDCFG_ENABLE_EXTERNAL_VREF_FEATURE}
+ ///<
+ IN FORCE_TRAIN_MODE ForceTrainMode; ///< Training Mode
+ ///< 0 = Force 1D Training for all configurations
+ ///< 1 = Force 2D Training for all configurations
+ ///< 2 = Auto - AGESA will control 1D or 2D
+ IN TECHNOLOGY_TYPE DimmTypeUsedInMixedConfig; ///< Select the preferred technology type that AGESA will enable
+ ///< when it is mixed with other technology types.
+ ///< DDR3_TECHNOLOGY = Use DDR3 DIMMs
+ ///< GDDR5_TECHNOLOGY = Use GDDR5 DIMMs
+ ///< UNSUPPORTED_TECHNOLOGY = Exit with fatal error when DDR3 and GDDR5 DIMMs
+ ///< are installed on the same system
+ ///< @BldCfgItem{BLDCFG_DIMM_TYPE_USED_IN_MIXED_CONFIG}
+ IN BOOLEAN AmpEnable; ///< AMP functionality control
+ ///< TRUE = Enable, platform BIOS requests to enable memory overclocking function, and AGESA
+ ///< detects if memory is capable of it
+ ///< FALSE = Disable, there is no request to enable memory overclocking function
+ ///<
+ IN BOOLEAN AmpWarningMsgEnable; ///< AMP warning messages control
+ ///< TRUE = Enable to log the warning messages of AMP
+ ///< FALSE = Disable
+ ///<
+ OUT AMP_STATUS AmpStatus; ///< AMP status allows platform BIOS to check which voltage or warning message it should
+ ///< use/apply.
+ ///<
+ ///< AmpVoltageValid :
+ ///< TRUE - AGESA does enable AMP function, so use AmpVoltage for voltage adjustment
+ ///< FALSE - AGESA does not enable AMP function, so use DDRVoltage for voltage adjustment
+ ///<
+ ///< AmpSupportDetectedButNotEnabled :
+ ///< TRUE - Display warning message of "AMP support detected but not enabled"
+ ///< FALSE - No corresponding message should be displayed
+ ///<
+ ///< AmpSelectedButNotEnabled :
+ ///< TRUE - Display warning message of "AMP selected but not enabled"
+ ///< FALSE - No corresponding message should be displayed
+ ///<
+ ///< Note that both of warning message status reports are controlled by AmpWarningMsgEnable
+ ///<
+ OUT AMP_DIMM_VOLTAGE AmpVoltage; ///< AMP voltage which will be sent back to platform BIOS, and
+ ///< the value in AmpVoltage is valid only if AmpStatus is TRUE returned
+ IN BOOLEAN DataEyeEn; ///< Get 2D training data eye
+ ///< TRUE = Enable to get the 2D data eye
+ ///< FALSE = The 2D data eye is not enabled
+ ///< @BldCfgItem{BLDCFG_ENABLE_DATA_EYE}
+ IN BOOLEAN DramDoubleRefreshRate; ///< Specify the average time between refresh requests to all DRAM devices.
+ ///< TRUE = 2x refresh rate.
+ ///< FALSE = 1x refresh rate.
+ ///< @BldCfgItem{BLDCFG_DRAM_DOUBLE_REFRESH_RATE}
+ IN PMU_TRAIN_MODE PmuTrainMode; ///< PMU Training Mode
+ ///< @BldCfgItem{BLDCFG_PMU_TRAINING_MODE}
+ ///< 0 = PMU 1D Training only for all configurations
+ ///< 1 = PMU 1D and 2D Training read only for all configurations
+ ///< 2 = PMU 1D and 2D Training for all configurations
+ ///< 3 = AGESA control type of training depend on configurations
+ IN BOOLEAN CfgEccRedirection; ///< ECC Redirection.
+ ///< Build-time customizable only - @BldCfgItem{BLDCFG_ECC_REDIRECTION}
+ IN UINT16 CfgScrubDramRate; ///< Scrub Dram Rate.
+ ///< Build-time customizable only - @BldCfgItem{BLDCFG_SCRUB_DRAM_RATE}
+ IN UINT16 CfgScrubL2Rate; ///< Scrub L2Rate.
+ ///< Build-time customizable only - @BldCfgItem{BLDCFG_SCRUB_L2_RATE}
+ IN UINT16 CfgScrubL3Rate; ///< Scrub L3Rate.
+ ///< Build-time customizable only - @BldCfgItem{BLDCFG_SCRUB_L3_RATE}
+ IN UINT16 CfgScrubIcRate; ///< Scrub Ic Rate.
+ ///< Build-time customizable only - @BldCfgItem{BLDCFG_SCRUB_IC_RATE}
+ IN UINT16 CfgScrubDcRate; ///< Scrub Dc Rate.
+ ///< Build-time customizable only - @BldCfgItem{BLDCFG_SCRUB_DC_RATE}
+ IN BOOLEAN CfgEccSyncFlood; ///< ECC Sync Flood.
+ ///< Build-time customizable only - @BldCfgItem{BLDCFG_ECC_SYNC_FLOOD}
+ IN UINT16 CfgEccSymbolSize; ///< ECC Symbol Size.
+ ///< Build-time customizable only - @BldCfgItem{BLDCFG_ECC_SYMBOL_SIZE}
+ IN BOOLEAN CfgDqsTrainingControl; ///< Dqs Training Control.
+ ///< Build-time customizable only - @BldCfgItem{BLDCFG_DQS_TRAINING_CONTROL}
+ IN BOOLEAN CfgUmaAbove4G; ///< Uma Above 4G Support
+ IN UMA_ALIGNMENT CfgUmaAlignment; ///< Uma alignment
+ IN BOOLEAN CfgMemoryAllClocksOn; ///< Memory All Clocks On.
+ ///< Build-time customizable only - @BldCfgItem{BLDCFG_MEMORY_ALL_CLOCKS_ON}
+ IN UINT32 CfgMemoryBusFrequencyLimit; ///< Memory Bus Frequency Limit.
+ ///< Build-time customizable only - @BldCfgItem{BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT}
+ IN UINT32 CfgPowerDownMode; ///< Power Down Mode.
+ IN BOOLEAN CfgIgnoreSpdChecksum; ///< Ignore Spd Checksum.
+ ///< Build-time customizable only - @BldCfgItem{BLDCFG_IGNORE_SPD_CHECKSUM}
+ IN BOOLEAN CfgMemoryModeUnganged; ///< Memory Mode Unganged.
+ ///< Build-time customizable only - @BldCfgItem{BLDCFG_MEMORY_MODE_UNGANGED}
+ IN BOOLEAN CfgMemoryQuadRankCapable; ///< Memory Quad Rank Capable.
+ IN BOOLEAN CfgMemoryRDimmCapable; ///< Memory RDIMM Capable.
+ IN BOOLEAN CfgMemoryLRDimmCapable; ///< Memory LRDIMM Capable.
+ IN BOOLEAN CfgMemoryUDimmCapable; ///< Memory UDIMM Capable.
+ IN BOOLEAN CfgMemorySODimmCapable; ///< Memory SODimm Capable.
+ ///< Build-time customizable only - @BldCfgItem{BLDCFG_MEMORY_SODIMM_CAPABLE}
+ ///< Build-time customizable only - @BldCfgItem{BLDCFG_MEMORY_QUAD_RANK_CAPABLE}
+ IN TECHNOLOGY_TYPE CfgDimmTypeUsedInMixedConfig; // Dimm Type Used In Mized Config
+ IN BOOLEAN CfgDramDoubleRefreshRateEn; ///< Double DRAM refresh rate
+ IN BOOLEAN DimmTypeDddr4Capable; ///< Indicates that the system is DDR4 Capable
+ ///< TRUE = Enable, platfrom BIOS requests support for DDR4
+ ///< FALSE = Disable, platform BIOS requests no DDR4 support
+ ///< @BldCfgItem{BLDCFG_DIMM_TYPE_DDR4_CAPABLE}
+ IN BOOLEAN DimmTypeDddr3Capable; ///< Indicates that the system is DDR3 Capable
+ ///< TRUE = Enable, platfrom BIOS requests support for DDR3
+ ///< FALSE = Disable, platform BIOS requests no DDR3 support
+ ///< @BldCfgItem{BLDCFG_DIMM_TYPE_DDR3_CAPABLE}
+ IN UINT16 CustomVddioSupport; ///< CustomVddioSupport
+ ///< @BldCfgItem{BLDCFG_CUSTOM_VDDIO_VOLTAGE}
+
+} MEM_PARAMETER_STRUCT;
+
+
+///
+/// Function definition.
+/// This data structure passes function pointers to the memory configuration code.
+/// The wrapper can use this structure with customized versions.
+///
+typedef struct _MEM_FUNCTION_STRUCT {
+
+ // PUBLIC required Internal functions
+
+ IN OUT BOOLEAN (*amdMemGetPsCfgU) ( VOID *pMemData); ///< Proc for Unbuffered DIMMs, platform specific
+ IN OUT BOOLEAN (*amdMemGetPsCfgR) (VOID *pMemData); ///< Proc for Registered DIMMs, platform specific
+
+ // PUBLIC optional functions
+
+ IN OUT VOID (*amdMemEccInit) (VOID *pMemData); ///< NB proc for ECC feature
+ IN OUT VOID (*amdMemChipSelectInterleaveInit) (VOID *pMemData); ///< NB proc for CS interleave feature
+ IN OUT VOID (*amdMemDctInterleavingInit) (VOID *pMemData); ///< NB proc for Channel interleave feature
+ IN OUT VOID (*amdMemMctInterleavingInit) (VOID *pMemData); ///< NB proc for Node interleave feature
+ IN OUT VOID (*amdMemParallelTraining) (VOID *pMemData); ///< NB proc for parallel training feature
+ IN OUT VOID (*amdMemEarlySampleSupport) (VOID *pMemData); ///< NB code for early sample support feature
+ IN OUT VOID (*amdMemMultiPartInitSupport) (VOID *pMemData); ///< NB code for 'multi-part'
+ IN OUT VOID (*amdMemOnlineSpareSupport) (VOID *pMemData); ///< NB code for On-Line Spare feature
+ IN OUT VOID (*amdMemUDimmInit) (VOID *pMemData); ///< NB code for UDIMMs
+ IN OUT VOID (*amdMemRDimmInit) (VOID *pMemData); ///< NB code for RDIMMs
+ IN OUT VOID (*amdMemLrDimmInit) (VOID *pMemData); ///< NB code for LRDIMMs
+ IN OUT UINT32 Reserved[100]; ///< Reserved for later function definition
+} MEM_FUNCTION_STRUCT;
+
+///
+/// Socket Structure
+///
+///
+typedef struct _MEM_SOCKET_STRUCT {
+ OUT VOID *ChannelPtr[MAX_CHANNELS_PER_SOCKET]; ///< Pointers to each channels training data
+
+ OUT VOID *TimingsPtr[MAX_CHANNELS_PER_SOCKET]; ///< Pointers to each channels timing data
+} MEM_SOCKET_STRUCT;
+
+///
+/// Contains all data relevant to Memory Initialization.
+///
+typedef struct _MEM_DATA_STRUCT {
+ IN AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header
+
+ IN MEM_PARAMETER_STRUCT *ParameterListPtr; ///< List of input Parameters
+
+ OUT MEM_FUNCTION_STRUCT FunctionList; ///< List of function Pointers
+
+ IN OUT AGESA_STATUS (*GetPlatformCfg[MAX_PLATFORM_TYPES]) (struct _MEM_DATA_STRUCT *MemData, UINT8 SocketID, CH_DEF_STRUCT *CurrentChannel); ///< look-up platform info
+
+ IN OUT BOOLEAN (*ErrorHandling)(struct _DIE_STRUCT *MCTPtr, UINT8 DCT, UINT16 ChipSelMask, AMD_CONFIG_PARAMS *StdHeader); ///< Error Handling
+
+
+ OUT MEM_SOCKET_STRUCT SocketList[MAX_SOCKETS_SUPPORTED]; ///< Socket list for memory code.
+ ///< SocketList is a shortcut for IBVs to retrieve training
+ ///< and timing data for each channel indexed by socket/channel,
+ ///< eliminating their need to parse die/dct/channel etc.
+ ///< It contains pointers to the populated data structures for
+ ///< each channel and skips the channel structures that are
+ ///< unpopulated. In the case of channels sharing the same DCT,
+ ///< the pTimings pointers will point to the same DCT Timing data.
+
+ OUT DIE_STRUCT *DiesPerSystem; ///< Pointed to an array of DIE_STRUCTs
+ OUT UINT8 DieCount; ///< Number of MCTs in the system.
+
+ IN SPD_DEF_STRUCT *SpdDataStructure; ///< Pointer to SPD Data structure
+
+ IN OUT struct _PLATFORM_CONFIGURATION *PlatFormConfig; ///< Platform profile/build option config structure
+
+ IN OUT BOOLEAN IsFlowControlSupported; ///< Indicates if flow control is supported
+
+ OUT UINT32 TscRate; ///< The rate at which the TSC increments in megahertz.
+ IN BOOLEAN PhyReceiverLowPower; ///< Force PHY receiver in low power.
+ ///< TRUE = PHY receiver low power
+ ///< FALSE = PHY receiver high power
+} MEM_DATA_STRUCT;
+
+///
+/// Uma Structure
+///
+///
+typedef struct _UMA_INFO {
+ OUT UINT64 UmaBase; ///< UmaBase[63:0] = Addr[63:0]
+ OUT UINT32 UmaSize; ///< UmaSize[31:0] = Addr[31:0]
+ OUT UINT32 UmaAttributes; ///< Indicate the attribute of Uma
+ OUT UINT8 UmaMode; ///< Indicate the mode of Uma
+ OUT UINT16 MemClock; ///< Indicate memory running speed in MHz
+ OUT UINT8 MemType; ///< Indicate the DRAM technology type that is being used
+ OUT UINT8 Reserved[2]; ///< Reserved for future usage
+} UMA_INFO;
+
+
+/// Bitfield for ID
+typedef struct {
+ OUT UINT16 SocketId:8; ///< Socket ID
+ OUT UINT16 ModuleId:8; ///< Module ID
+} ID_FIELD;
+///
+/// Union for ID of socket and module that will be passed out in call out
+///
+typedef union {
+ OUT ID_FIELD IdField; ///< Bitfield for ID
+ OUT UINT16 IdInformation; ///< ID information for call out
+} ID_INFO;
+
+// AGESA MEMORY ERRORS
+
+// AGESA_SUCCESS memory events
+#define MEM_EVENT_CAPSULE_IN_EFFECT 0x04013600ul ///< Capsule is in effect
+#define MEM_EVENT_CONTEXT_RESTORE_IN_EFFECT 0x04023600ul ///< Context restore is in effect
+
+// AGESA_ALERT Memory Errors
+#define MEM_ALERT_USER_TMG_MODE_OVERRULED 0x04010000ul ///< TIMING_MODE_SPECIFIC is requested but
+ ///< cannot be applied to current configurations.
+#define MEM_ALERT_ORG_MISMATCH_DIMM 0x04010100ul ///< DIMM organization miss-match
+#define MEM_ALERT_BK_INT_DIS 0x04010200ul ///< Bank interleaving disable for internal issue
+
+// AGESA_ERROR Memory Errors
+#define MEM_ERROR_NO_DQS_POS_RD_WINDOW 0x04010300ul ///< No DQS Position window for RD DQS
+#define MEM_ERROR_SMALL_DQS_POS_RD_WINDOW 0x04020300ul ///< Small DQS Position window for RD DQS
+#define MEM_ERROR_NO_DQS_POS_WR_WINDOW 0x04030300ul ///< No DQS Position window for WR DQS
+#define MEM_ERROR_SMALL_DQS_POS_WR_WINDOW 0x04040300ul ///< Small DQS Position window for WR DQS
+#define MEM_ERROR_DIMM_SPARING_NOT_ENABLED 0x04010500ul ///< DIMM sparing has not been enabled for an internal issues
+#define MEM_ERROR_RCVR_EN_VALUE_TOO_LARGE 0x04050300ul ///< Receive Enable value is too large
+#define MEM_ERROR_RCVR_EN_NO_PASSING_WINDOW 0x04060300ul ///< There is no DQS receiver enable window
+#define MEM_ERROR_DRAM_ENABLED_TIME_OUT 0x04010600ul ///< Time out when polling DramEnabled bit
+#define MEM_ERROR_DCT_ACCESS_DONE_TIME_OUT 0x04010700ul ///< Time out when polling DctAccessDone bit
+#define MEM_ERROR_SEND_CTRL_WORD_TIME_OUT 0x04010800ul ///< Time out when polling SendCtrlWord bit
+#define MEM_ERROR_PREF_DRAM_TRAIN_MODE_TIME_OUT 0x04010900ul ///< Time out when polling PrefDramTrainMode bit
+#define MEM_ERROR_ENTER_SELF_REF_TIME_OUT 0x04010A00ul ///< Time out when polling EnterSelfRef bit
+#define MEM_ERROR_FREQ_CHG_IN_PROG_TIME_OUT 0x04010B00ul ///< Time out when polling FreqChgInProg bit
+#define MEM_ERROR_EXIT_SELF_REF_TIME_OUT 0x04020A00ul ///< Time out when polling ExitSelfRef bit
+#define MEM_ERROR_SEND_MRS_CMD_TIME_OUT 0x04010C00ul ///< Time out when polling SendMrsCmd bit
+#define MEM_ERROR_SEND_ZQ_CMD_TIME_OUT 0x04010D00ul ///< Time out when polling SendZQCmd bit
+#define MEM_ERROR_DCT_EXTRA_ACCESS_DONE_TIME_OUT 0x04010E00ul ///< Time out when polling DctExtraAccessDone bit
+#define MEM_ERROR_MEM_CLR_BUSY_TIME_OUT 0x04010F00ul ///< Time out when polling MemClrBusy bit
+#define MEM_ERROR_MEM_CLEARED_TIME_OUT 0x04020F00ul ///< Time out when polling MemCleared bit
+#define MEM_ERROR_FLUSH_WR_TIME_OUT 0x04011000ul ///< Time out when polling FlushWr bit
+#define MEM_ERROR_NBPSTATE_TRANSITION_TIME_OUT 0x04012600ul ///< Time out when polling CurNBPstate bit
+#define MEM_ERROR_MAX_LAT_NO_WINDOW 0x04070300ul ///< Fail to find pass during Max Rd Latency training
+#define MEM_ERROR_PARALLEL_TRAINING_LAUNCH_FAIL 0x04080300ul ///< Fail to launch training code on an AP
+#define MEM_ERROR_PARALLEL_TRAINING_TIME_OUT 0x04090300ul ///< Fail to finish parallel training
+#define MEM_ERROR_NO_ADDRESS_MAPPING 0x04011100ul ///< No address mapping found for a dimm
+#define MEM_ERROR_RCVR_EN_NO_PASSING_WINDOW_EQUAL_LIMIT 0x040A0300ul ///< There is no DQS receiver enable window and the value is equal to the largest value
+#define MEM_ERROR_RCVR_EN_VALUE_TOO_LARGE_LIMIT_LESS_ONE 0x040B0300ul ///< Receive Enable value is too large and is 1 less than limit
+#define MEM_ERROR_CHECKSUM_NV_SPDCHK_RESTRT_ERROR 0x04011200ul ///< SPD Checksum error for NV_SPDCHK_RESTRT
+#define MEM_ERROR_NO_CHIPSELECT 0x04011300ul ///< No chipselects found
+#define MEM_ERROR_UNSUPPORTED_333MHZ_UDIMM 0x04011500ul ///< Unbuffered dimm is not supported at 333MHz
+#define MEM_ERROR_WL_PRE_OUT_OF_RANGE 0x040C0300ul ///< Returned PRE value during write levelizzation was out of range
+#define MEM_ERROR_NO_2D_RDDQS_WINDOW 0x040D0300ul ///< No 2D RdDqs Window
+#define MEM_ERROR_NO_2D_RDDQS_HEIGHT 0x040E0300ul ///< No 2D RdDqs Height
+#define MEM_ERROR_2D_DQS_ERROR 0x040F0300ul ///< 2d RdDqs Error
+#define MEM_ERROR_INVALID_2D_RDDQS_VALUE 0x04022400ul ///< 2d RdDqs invalid value found
+#define MEM_ERROR_2D_DQS_VREF_MARGIN_ERROR 0x04023400ul ///< 2d RdDqs Vef Margin error found
+#define MEM_ERROR_LR_IBT_NOT_FOUND 0x04013500ul ///< No LR dimm IBT value is found
+#define MEM_ERROR_MR0_NOT_FOUND 0x04023500ul ///< No MR0 value is found
+#define MEM_ERROR_ODT_PATTERN_NOT_FOUND 0x04033500ul ///< No odt pattern value is found
+#define MEM_ERROR_RC2_IBT_NOT_FOUND 0x04043500ul ///< No RC2 IBT value is found
+#define MEM_ERROR_RC10_OP_SPEED_NOT_FOUND 0x04053500ul ///< No RC10 op speed is found
+#define MEM_ERROR_RTT_NOT_FOUND 0x04063500ul ///< No RTT value is found
+#define MEM_ERROR_P2D_NOT_FOUND 0x04073500ul ///< No 2D training config value is found
+#define MEM_ERROR_SAO_NOT_FOUND 0x04083500ul ///< No slow access mode, Address timing and Output driver compensation value is found
+#define MEM_ERROR_CLK_DIS_MAP_NOT_FOUND 0x04093500ul ///< No CLK disable map is found
+#define MEM_ERROR_CKE_TRI_MAP_NOT_FOUND 0x040A3500ul ///< No CKE tristate map is found
+#define MEM_ERROR_ODT_TRI_MAP_NOT_FOUND 0x040B3500ul ///< No ODT tristate map is found
+#define MEM_ERROR_CS_TRI_MAP_NOT_FOUND 0x040C3500ul ///< No CS tristate map is found
+#define MEM_ERROR_TRAINING_SEED_NOT_FOUND 0x040D3500ul ///< No training seed is found
+#define MEM_ERROR_NO_2D_WRDAT_WINDOW 0x040D0400ul ///< No 2D WrDat Window
+#define MEM_ERROR_NO_2D_WRDAT_HEIGHT 0x040E0400ul ///< No 2D WrDat Height
+#define MEM_ERROR_2D_WRDAT_ERROR 0x040F0400ul ///< 2d WrDat Error
+#define MEM_ERROR_INVALID_2D_WRDAT_VALUE 0x04100400ul ///< 2d WrDat invalid value found
+#define MEM_ERROR_2D_WRDAT_VREF_MARGIN_ERROR 0x04110400ul ///< 2d WrDat Vef Margin error found
+#define MEM_ERROR_PMU_TRAINING 0x04120400ul ///< Fail PMU training.
+
+// AGESA_WARNING Memory Errors
+#define MEM_WARNING_UNSUPPORTED_QRDIMM 0x04011600ul ///< QR DIMMs detected but not supported
+#define MEM_WARNING_UNSUPPORTED_UDIMM 0x04021600ul ///< U DIMMs detected but not supported
+#define MEM_WARNING_UNSUPPORTED_SODIMM 0x04031600ul ///< SO-DIMMs detected but not supported
+#define MEM_WARNING_UNSUPPORTED_X4DIMM 0x04041600ul ///< x4 DIMMs detected but not supported
+#define MEM_WARNING_UNSUPPORTED_RDIMM 0x04051600ul ///< R DIMMs detected but not supported
+#define MEM_WARNING_UNSUPPORTED_LRDIMM 0x04061600ul ///< LR DIMMs detected but not supported
+#define MEM_WARNING_EMP_NOT_SUPPORTED 0x04011700ul ///< Processor is not capable for EMP
+#define MEM_WARNING_EMP_CONFLICT 0x04021700ul ///< EMP cannot be enabled if channel interleaving,
+#define MEM_WARNING_EMP_NOT_ENABLED 0x04031700ul ///< Memory size is not power of two.
+#define MEM_WARNING_ECC_DIS 0x04041700ul ///< ECC has been disabled as a result of an internal issue
+#define MEM_WARNING_PERFORMANCE_ENABLED_BATTERY_LIFE_PREFERRED 0x04011800ul ///< Performance has been enabled, but battery life is preferred.
+ ///< bank interleaving, or bank swizzle is enabled.
+#define MEM_WARNING_NO_SPDTRC_FOUND 0x04011900ul ///< No Trc timing value found in SPD of a dimm.
+#define MEM_WARNING_NODE_INTERLEAVING_NOT_ENABLED 0x04012000ul ///< Node Interleaveing Requested, but could not be enabled
+#define MEM_WARNING_CHANNEL_INTERLEAVING_NOT_ENABLED 0x04012100ul ///< Channel Interleaveing Requested, but could not be enabled
+#define MEM_WARNING_BANK_INTERLEAVING_NOT_ENABLED 0x04012200ul ///< Bank Interleaveing Requested, but could not be enabled
+#define MEM_WARNING_VOLTAGE_1_35_NOT_SUPPORTED 0x04012300ul ///< Voltage 1.35 determined, but could not be supported
+#define MEM_WARNING_INITIAL_DDR3VOLT_NONZERO 0x04012400ul ///< DDR3 voltage initial value is not 0
+#define MEM_WARNING_NO_COMMONLY_SUPPORTED_VDDIO 0x04012500ul ///< Cannot find a commonly supported VDDIO
+#define MEM_WARNING_AMP_SUPPORT_DETECTED_BUT_NOT_ENABLED 0x04012900ul ///< AMP support detected but not enabled
+#define MEM_WARNING_AMP_SELECTED_BUT_NOT_ENABLED 0x04022900ul ///< AMP selected but not enabled
+
+// AGESA_FATAL Memory Errors
+#define MEM_ERROR_MINIMUM_MODE 0x04011A00ul ///< Running in minimum mode
+#define MEM_ERROR_MODULE_TYPE_MISMATCH_DIMM 0x04011B00ul ///< DIMM modules are miss-matched
+#define MEM_ERROR_NO_DIMM_FOUND_ON_SYSTEM 0x04011C00ul ///< No DIMMs have been found
+#define MEM_ERROR_MISMATCH_DIMM_CLOCKS 0x04011D00ul ///< DIMM clocks miss-matched
+#define MEM_ERROR_NO_CYC_TIME 0x04011E00ul ///< No cycle time found
+#define MEM_ERROR_HEAP_ALLOCATE_DYN_STORING_OF_TRAINED_TIMINGS 0x04011F00ul ///< Heap allocation error with dynamic storing of trained timings
+#define MEM_ERROR_HEAP_ALLOCATE_FOR_DCT_STRUCT_AND_CH_DEF_STRUCTs 0x04021F00ul ///< Heap allocation error for DCT_STRUCT and CH_DEF_STRUCT
+#define MEM_ERROR_HEAP_ALLOCATE_FOR_REMOTE_TRAINING_ENV 0x04031F00ul ///< Heap allocation error with REMOTE_TRAINING_ENV
+#define MEM_ERROR_HEAP_ALLOCATE_FOR_SPD 0x04041F00ul ///< Heap allocation error for SPD data
+#define MEM_ERROR_HEAP_ALLOCATE_FOR_RECEIVED_DATA 0x04051F00ul ///< Heap allocation error for RECEIVED_DATA during parallel training
+#define MEM_ERROR_HEAP_ALLOCATE_FOR_S3_SPECIAL_CASE_REGISTERS 0x04061F00ul ///< Heap allocation error for S3 "SPECIAL_CASE_REGISTER"
+#define MEM_ERROR_HEAP_ALLOCATE_FOR_TRAINING_DATA 0x04071F00ul ///< Heap allocation error for Training Data
+#define MEM_ERROR_HEAP_ALLOCATE_FOR_IDENTIFY_DIMM_MEM_NB_BLOCK 0x04081F00ul ///< Heap allocation error for DIMM Identify "MEM_NB_BLOCK
+#define MEM_ERROR_NO_CONSTRUCTOR_FOR_IDENTIFY_DIMM 0x04022300ul ///< No Constructor for DIMM Identify
+#define MEM_ERROR_VDDIO_UNSUPPORTED 0x04022500ul ///< VDDIO of the dimms on the board is not supported
+#define MEM_ERROR_VDDPVDDR_UNSUPPORTED 0x04032500ul ///< VDDP/VDDR value indicated by the platform BIOS is not supported
+#define MEM_ERROR_HEAP_ALLOCATE_FOR_2D 0x040B1F00ul ///< Heap allocation error for 2D training data
+#define MEM_ERROR_HEAP_DEALLOCATE_FOR_2D 0x040C1F00ul ///< Heap de-allocation error for 2D training data
+#define MEM_ERROR_HEAP_ALLOCATE_FOR_DATAEYE 0x040F1F00ul ///< Heap allocation error for DATAEYE Storage
+#define MEM_ERROR_HEAP_DEALLOCATE_FOR_DATAEYE 0x040E1F00ul ///< Heap de-allocation error for DATAEYE Storage
+#define MEM_ERROR_HEAP_ALLOCATE_FOR_PMU_SRAM_MSG_BLOCK 0x04101F00ul ///< Heap allocation error for PMU SRAM Message Block Storage
+#define MEM_ERROR_HEAP_DEALLOCATE_FOR_PMU_SRAM_MSG_BLOCK 0x04111F00ul ///< Heap de-allocation error for PMU SRAM Message Block Storage
+#define MEM_ERROR_HEAP_LOCATE_FOR_PMU_SRAM_MSG_BLOCK 0x04121F00ul ///< Heap location error for PMU SRAM Message Block Storage
+
+// AGESA_CRITICAL Memory Errors
+#define MEM_ERROR_HEAP_ALLOCATE_FOR_DMI_TABLE_DDR3 0x04091F00ul ///< Heap allocation error for DMI table for DDR3
+#define MEM_ERROR_HEAP_ALLOCATE_FOR_DMI_TABLE_DDR2 0x040A1F00ul ///< Heap allocation error for DMI table for DDR2
+#define MEM_ERROR_UNSUPPORTED_DIMM_CONFIG 0x04011400ul ///< Dimm population is not supported
+#define MEM_ERROR_HEAP_ALLOCATE_FOR_CRAT_MEM_AFFINITY 0x040D1F00ul ///< Heap allocation error for CRAT memory affinity info
+
+
+
+/*----------------------------------------------------------------------------
+ *
+ * END OF MEMORY-SPECIFIC DATA STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+
+/*----------------------------------------------------------------------------
+ *
+ * CPU RELATED DEFINITIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+// CPU Event definitions.
+
+// Defines used to filter CPU events based on functional blocks
+#define CPU_EVENT_PM_EVENT_MASK 0xFF00FF00ul
+#define CPU_EVENT_PM_EVENT_CLASS 0x08000400ul
+
+//================================================================
+// CPU General events
+// Heap allocation (AppFunction = 01h)
+#define CPU_ERROR_HEAP_BUFFER_IS_NOT_PRESENT 0x08000100ul
+#define CPU_ERROR_HEAP_IS_ALREADY_INITIALIZED 0x08010100ul
+#define CPU_ERROR_HEAP_IS_FULL 0x08020100ul
+#define CPU_ERROR_HEAP_BUFFER_HANDLE_IS_ALREADY_USED 0x08030100ul
+#define CPU_ERROR_HEAP_BUFFER_HANDLE_IS_NOT_PRESENT 0x08040100ul
+// BrandId (AppFunction = 02h)
+#define CPU_ERROR_BRANDID_HEAP_NOT_AVAILABLE 0x08000200ul
+// Micro code patch (AppFunction = 03h)
+#define CPU_ERROR_MICRO_CODE_PATCH_IS_NOT_LOADED 0x08000300ul
+// Power management (AppFunction = 04h)
+#define CPU_EVENT_PM_PSTATE_OVERCURRENT 0x08000400ul
+#define CPU_EVENT_PM_ALL_PSTATE_OVERCURRENT 0x08010400ul
+#define CPU_ERROR_PSTATE_HEAP_NOT_AVAILABLE 0x08020400ul
+#define CPU_ERROR_PM_NB_PSTATE_MISMATCH 0x08030400ul
+#define CPU_ERROR_PM_ALL_PSTATE_OVER_FREQUENCY_LIMIT 0x08040400ul
+#define CPU_EVENT_PM_PSTATE_FREQUENCY_LIMIT 0x08050400ul
+// Other CPU events (AppFunction = 05h)
+#define CPU_EVENT_BIST_ERROR 0x08000500ul
+#define CPU_EVENT_UNKNOWN_PROCESSOR_FAMILY 0x08010500ul
+#define CPU_EVENT_STACK_REENTRY 0x08020500ul
+#define CPU_EVENT_CORE_NOT_IDENTIFIED 0x08030500ul
+
+//=================================================================
+// CPU Feature events
+// Execution cache (AppFunction = 21h)
+// AGESA_CACHE_SIZE_REDUCED 2101
+// AGESA_CACHE_REGIONS_ACROSS_1MB 2102
+// AGESA_CACHE_REGIONS_ACROSS_4GB 2103
+// AGESA_REGION_NOT_ALIGNED_ON_BOUNDARY 2104
+// AGESA_CACHE_START_ADDRESS_LESS_D0000 2105
+// AGESA_THREE_CACHE_REGIONS_ABOVE_1MB 2106
+// AGESA_DEALLOCATE_CACHE_REGIONS 2107
+#define CPU_EVENT_EXECUTION_CACHE_ALLOCATION_ERROR 0x08002100ul
+// Core Leveling (AppFunction = 22h)
+#define CPU_WARNING_ADJUSTED_LEVELING_MODE 0x08002200ul
+// SCS initialization (AppFunction = 24h)
+// AGESA_SCS_HEAP_ENTRY_MISSING 2401
+// AGESA_SCS_BUFFER_EMPTY 2402
+// AGESA_SCS_WEIGHTS_MISMATCH 2403
+#define CPU_EVENT_SCS_INITIALIZATION_ERROR 0x08002400ul
+// BTC vid adjustment error
+#define CPU_EVENT_BTC_INITIALIZATION_ERROR 0x08002500ul
+
+// CPU Build Configuration structures and definitions
+
+/// Build Configuration structure for BLDCFG_AP_MTRR_SETTINGS
+typedef struct {
+ IN UINT32 MsrAddr; ///< Fixed-Sized MTRR address
+ IN UINT64 MsrData; ///< MTRR Settings
+} AP_MTRR_SETTINGS;
+
+#define AMD_AP_MTRR_FIX64k_00000 0x00000250ul
+#define AMD_AP_MTRR_FIX16k_80000 0x00000258ul
+#define AMD_AP_MTRR_FIX16k_A0000 0x00000259ul
+#define AMD_AP_MTRR_FIX4k_C0000 0x00000268ul
+#define AMD_AP_MTRR_FIX4k_C8000 0x00000269ul
+#define AMD_AP_MTRR_FIX4k_D0000 0x0000026Aul
+#define AMD_AP_MTRR_FIX4k_D8000 0x0000026Bul
+#define AMD_AP_MTRR_FIX4k_E0000 0x0000026Cul
+#define AMD_AP_MTRR_FIX4k_E8000 0x0000026Dul
+#define AMD_AP_MTRR_FIX4k_F0000 0x0000026Eul
+#define AMD_AP_MTRR_FIX4k_F8000 0x0000026Ful
+#define CPU_LIST_TERMINAL 0xFFFFFFFFul
+
+/// Data structure for the Mapping Item between Unified ID for IDS Setup Option
+/// and the option value.
+///
+typedef struct {
+ IN UINT16 IdsNvId; ///< Unified ID for IDS Setup Option.
+ OUT UINT16 IdsNvValue; ///< The value of IDS Setup Option.
+} IDS_NV_ITEM;
+
+/// Data Structure for IDS CallOut Function
+typedef struct {
+ IN AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header
+ IN IDS_NV_ITEM *IdsNvPtr; ///< Memory Pointer of IDS NV Table
+ IN OUT UINTN Reserved; ///< reserved
+} IDS_CALLOUT_STRUCT;
+
+/// Data Structure for Connected Standby Function
+typedef struct {
+ IN AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header
+ IN VOID *CsRestoreTable; ///< Pointer to the CsRestoreTable
+ IN UINT32 CsRestoreTableSize; ///< Size in bytes of the CsRestoreTable
+} CS_CALLOUT_STRUCT;
+
+/************************************************************************
+ *
+ * AGESA interface Call-Out function parameter structures
+ *
+ ***********************************************************************/
+
+/// Parameters structure for interface call-out AgesaAllocateBuffer
+typedef struct {
+ IN OUT AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header
+ IN OUT UINT32 BufferLength; ///< Size of buffer to allocate
+ IN UINT32 BufferHandle; ///< Identifier or name for the buffer
+ OUT VOID *BufferPointer; ///< location of the created buffer
+} AGESA_BUFFER_PARAMS;
+
+/// Parameters structure for interface call-out AgesaHeapRebase
+typedef struct {
+ IN OUT AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header
+ OUT UINTN HeapAddress; ///< The address which heap content will be temporarily stored in
+} AGESA_REBASE_PARAMS;
+
+/// Parameters structure for interface call-out AgesaRunCodeOnAp
+typedef struct {
+ IN OUT AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header
+ IN UINT32 FunctionNumber; ///< Index of the procedure to execute
+ IN VOID *RelatedDataBlock; ///< Location of data structure the procedure will use
+ IN UINT32 RelatedBlockLength; ///< Size of the related data block
+ IN BOOLEAN AllAPs; ///< run on all Aps or on one only
+} AP_EXE_PARAMS;
+
+/// Parameters structure for the interface call-out AgesaReadSpd & AgesaReadSpdRecovery
+typedef struct {
+ IN OUT AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header
+ IN UINT8 SocketId; ///< Address of SPD - socket ID
+ IN UINT8 MemChannelId; ///< Address of SPD - memory channel ID
+ IN UINT8 DimmId; ///< Address of SPD - DIMM ID
+ IN OUT UINT8 *Buffer; ///< Location where to place the SPD content
+ IN OUT MEM_DATA_STRUCT *MemData; ///< Location of the MemData structure, for reference
+} AGESA_READ_SPD_PARAMS;
+
+/// VoltageType values
+typedef enum {
+ VTYPE_CPU_VREF, ///< Cpu side Vref
+ VTYPE_DIMM_VREF, ///< Dimm Side Vref
+ VTYPE_VDDIO ///< Vddio
+} VTYPE;
+
+/// Parameters structure for the interface call-out AgesaExternalVoltageAdjust
+typedef struct _VOLTAGE_ADJUST {
+ IN OUT AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header
+ IN OUT MEM_DATA_STRUCT *MemData; ///< Location of the MemData structure, for reference
+ IN VTYPE VoltageType; ///< Which Voltage Type to adjust
+ IN INT8 AdjustValue; ///< Positive/Negative Adjust Value
+} VOLTAGE_ADJUST;
+
+/// Buffer Handles
+typedef enum {
+ AMD_DMI_INFO_BUFFER_HANDLE = 0x000D000, ///< Assign 0x000D000 buffer handle to DMI function
+ AMD_PSTATE_DATA_BUFFER_HANDLE, ///< Assign 0x000D001 buffer handle to Pstate data
+ AMD_PSTATE_ACPI_BUFFER_HANDLE, ///< Assign 0x000D002 buffer handle to Pstate table
+ AMD_BRAND_ID_BUFFER_HANDLE, ///< Assign 0x000D003 buffer handle to Brand ID
+ AMD_WHEA_BUFFER_HANDLE, ///< Assign 0x000D004 buffer handle to WHEA function
+ AMD_S3_INFO_BUFFER_HANDLE, ///< Assign 0x000D005 buffer handle to S3 function
+ AMD_S3_NB_INFO_BUFFER_HANDLE, ///< Assign 0x000D006 buffer handle to S3 NB device info
+ AMD_ACPI_ALIB_BUFFER_HANDLE, ///< Assign 0x000D007 buffer handle to ALIB SSDT table
+ AMD_ACPI_IVRS_BUFFER_HANDLE, ///< Assign 0x000D008 buffer handle to IOMMU IVRS table
+ AMD_CRAT_INFO_BUFFER_HANDLE, ///< Assign 0x000D009 buffer handle to CRAT function
+ AMD_ACPI_CDIT_BUFFER_HANDLE, ///< Assign 0x000D00A buffer handle to CDIT function
+ AMD_GNB_SMU_MEMORY_INFO_BUFFER_HANDLE ///< Assign 0x000D00B buffer handle to SMU memory parameters function
+} AMD_BUFFER_HANDLE;
+
+
+/************************************************************************
+ *
+ * AGESA interface Call-Out function prototypes
+ *
+ ***********************************************************************/
+
+VOID
+AgesaDoReset (
+ IN UINTN ResetType,
+ IN OUT AMD_CONFIG_PARAMS *StdHeader
+ );
+
+AGESA_STATUS
+AgesaAllocateBuffer (
+ IN UINTN FcnData,
+ IN OUT AGESA_BUFFER_PARAMS *AllocParams
+ );
+
+AGESA_STATUS
+AgesaDeallocateBuffer (
+ IN UINTN FcnData,
+ IN OUT AGESA_BUFFER_PARAMS *DeallocParams
+ );
+
+AGESA_STATUS
+AgesaLocateBuffer (
+ IN UINTN FcnData,
+ IN OUT AGESA_BUFFER_PARAMS *LocateParams
+ );
+
+AGESA_STATUS
+AgesaHeapRebase (
+ IN UINTN FcnData,
+ IN OUT AGESA_REBASE_PARAMS *RebaseParams
+ );
+
+AGESA_STATUS
+AgesaReadSpd (
+ IN UINTN FcnData,
+ IN OUT AGESA_READ_SPD_PARAMS *ReadSpd
+ );
+
+AGESA_STATUS
+AgesaReadSpdRecovery (
+ IN UINTN FcnData,
+ IN OUT AGESA_READ_SPD_PARAMS *ReadSpd
+ );
+
+AGESA_STATUS
+AgesaHookBeforeDramInitRecovery (
+ IN UINTN FcnData,
+ IN OUT MEM_DATA_STRUCT *MemData
+ );
+
+AGESA_STATUS
+AgesaRunFcnOnAp (
+ IN UINTN ApicIdOfCore,
+ IN AP_EXE_PARAMS *LaunchApParams
+ );
+
+AGESA_STATUS
+AgesaRunFcnOnAllAps (
+ IN UINTN FcnData,
+ IN AP_EXE_PARAMS *LaunchApParams
+ );
+
+AGESA_STATUS
+AgesaWaitForAllApsFinished (
+ IN UINTN FcnData,
+ IN AMD_CONFIG_PARAMS *StdHeader
+ );
+
+AGESA_STATUS
+AgesaIdleAnAp (
+ IN UINTN ApicIdOfCore,
+ IN AMD_CONFIG_PARAMS *StdHeader
+ );
+
+AGESA_STATUS
+AgesaHookBeforeDramInit (
+ IN UINTN SocketIdModuleId,
+ IN OUT MEM_DATA_STRUCT *MemData
+ );
+
+AGESA_STATUS
+AgesaHookBeforeDQSTraining (
+ IN UINTN SocketIdModuleId,
+ IN OUT MEM_DATA_STRUCT *MemData
+ );
+
+AGESA_STATUS
+AgesaHookBeforeExitSelfRefresh (
+ IN UINTN FcnData,
+ IN OUT MEM_DATA_STRUCT *MemData
+ );
+
+AGESA_STATUS
+AgesaPcieSlotResetControl (
+ IN UINTN FcnData,
+ IN PCIe_SLOT_RESET_INFO *ResetInfo
+ );
+
+AGESA_STATUS
+AgesaGetVbiosImage (
+ IN UINTN FcnData,
+ IN OUT GFX_VBIOS_IMAGE_INFO *VbiosImageInfo
+ );
+
+AGESA_STATUS
+AgesaFchOemCallout (
+ IN VOID *FchData
+ );
+
+AGESA_STATUS
+AgesaExternal2dTrainVrefChange (
+ IN UINTN SocketIdModuleId,
+ IN OUT MEM_DATA_STRUCT *MemData
+ );
+
+AGESA_STATUS
+AgesaGetIdsData (
+ IN UINTN Data,
+ IN OUT IDS_CALLOUT_STRUCT *IdsCalloutData
+ );
+
+AGESA_STATUS
+AgesaExternalVoltageAdjust (
+ IN UINTN SocketIdModuleId,
+ IN OUT VOLTAGE_ADJUST *AdjustValue
+ );
+
+AGESA_STATUS
+AgesaGnbOemCallout (
+ IN AMD_CONFIG_PARAMS *StdHeader,
+ IN UINTN FcnData,
+ IN OUT VOID *GnbCalloutData
+ );
+
+/************************************************************************
+ *
+ * AGESA interface structure definition and function prototypes
+ *
+ ***********************************************************************/
+
+/**********************************************************************
+ * Platform Configuration: The parameters in boot branch function
+ **********************************************************************/
+
+/// The possible platform control flow settings.
+typedef enum {
+ Nfcm, ///< Normal Flow Control Mode.
+ UmaDr, ///< UMA using Display Refresh flow control.
+ UmaIfcm, ///< UMA using Isochronous Flow Control.
+ Ifcm, ///< Isochronous Flow Control Mode (other than for UMA).
+ Iommu, ///< An IOMMU is in use in the system.
+ MaxControlFlow ///< Not a control flow mode, use for limit checking.
+} PLATFORM_CONTROL_FLOW;
+
+/// The possible hardware prefetch mode settings.
+typedef enum {
+ HARDWARE_PREFETCHER_AUTO, ///< Use the recommended setting for the processor. In most cases, the recommended setting is enabled.
+ DISABLE_HW_PREFETCHER_TRAINING_ON_SOFTWARE_PREFETCHES, ///< Use the recommended setting for the hardware prefetcher, but disable training on software prefetches.
+ DISABLE_L1_PREFETCHER, ///< Use the recommended settings for the hardware prefetcher, but disable L1 prefetching and above.
+ DISABLE_L2_STRIDE_PREFETCHER, ///< Use the recommended settings for the hardware prefetcher, but disable the L2 stride prefetcher and above
+ DISABLE_HARDWARE_PREFETCH, ///< Disable hardware prefetching.
+ MAX_HARDWARE_PREFETCH_MODE ///< Not a hardware prefetch mode, use for limit checking.
+} HARDWARE_PREFETCH_MODE;
+
+/// The possible software prefetch mode settings.
+typedef enum {
+ SOFTWARE_PREFETCHES_AUTO, ///< Use the recommended setting for the processor. In most cases, the recommended setting is enabled.
+ DISABLE_SOFTWARE_PREFETCHES, ///< Disable software prefetches (convert software prefetch instructions to NOP).
+ MAX_SOFTWARE_PREFETCH_MODE ///< Not a software prefetch mode, use for limit checking.
+} SOFTWARE_PREFETCH_MODE;
+
+/// Advanced performance tunings, prefetchers.
+/// These settings provide for performance tuning to optimize for specific workloads.
+typedef struct {
+ IN HARDWARE_PREFETCH_MODE HardwarePrefetchMode; ///< This value provides for advanced performance tuning by controlling the hardware prefetcher setting.
+ IN SOFTWARE_PREFETCH_MODE SoftwarePrefetchMode; ///< This value provides for advanced performance tuning by controlling the software prefetch instructions.
+ IN DRAM_PREFETCH_MODE DramPrefetchMode; ///< This value provides for advanced performance tuning by controlling the DRAM prefetcher setting.
+} ADVANCED_PERFORMANCE_PROFILE;
+
+/// The possible memory power policy settings.
+typedef enum {
+ Performance, ///< Optimize for performance.
+ BatteryLife, ///< Optimize for battery life.
+ Auto, ///< Auto
+ MaxPowerPolicy ///< Not a power policy mode, use for limit checking.
+} MEMORY_POWER_POLICY;
+
+/// Platform performance settings for optimized settings.
+/// Several configuration settings for the processor depend upon other parts and
+/// general designer choices for the system. The determination of these data points
+/// is not standard for all platforms, so the host environment needs to provide these
+/// to specify how the system is to be configured.
+typedef struct {
+ IN PLATFORM_CONTROL_FLOW PlatformControlFlowMode; ///< The platform's control flow mode for optimum platform performance.
+ ///< @BldCfgItem{BLDCFG_PLATFORM_CONTROL_FLOW_MODE}
+ IN BOOLEAN Use32ByteRefresh; ///< Display Refresh traffic generates 32 byte requests.
+ ///< @BldCfgItem{BLDCFG_USE_32_BYTE_REFRESH}
+ IN BOOLEAN UseVariableMctIsocPriority; ///< The Memory controller will be set to Variable Isoc Priority.
+ ///< @BldCfgItem{BLDCFG_USE_VARIABLE_MCT_ISOC_PRIORITY}
+ IN ADVANCED_PERFORMANCE_PROFILE AdvancedPerformanceProfile; ///< The advanced platform performance settings.
+ IN MEMORY_POWER_POLICY MemoryPowerPolicy; ///< The memory's desired power policy
+ ///< @BldCfgItem{BLDCFG_MEMORY_POWER_POLICY_MODE}
+ IN BOOLEAN NbPstatesSupported; ///< The Nb-Pstates is supported or not
+ ///< @BldCfgItem{BLDCFG_NB_PSTATES_SUPPORTED}
+} PERFORMANCE_PROFILE;
+
+/// Platform settings that describe the voltage regulator modules of the system.
+/// Many power management settings are dependent upon the characteristics of the
+/// on-board voltage regulator module (VRM). The host environment needs to provide
+/// these to specify how the system is to be configured.
+typedef struct {
+ IN UINT32 CurrentLimit; ///< Vrm Current Limit.
+ ///< @BldCfgItem{BLDCFG_VRM_CURRENT_LIMIT}
+ ///< @BldCfgItem{BLDCFG_VRM_NB_CURRENT_LIMIT}
+ ///< @BldCfgItem{BLDCFG_VRM_GFX_CURRENT_LIMIT}
+ IN UINT32 LowPowerThreshold; ///< Vrm Low Power Threshold.
+ ///< @BldCfgItem{BLDCFG_VRM_LOW_POWER_THRESHOLD}
+ ///< @BldCfgItem{BLDCFG_VRM_NB_LOW_POWER_THRESHOLD}
+ ///< @BldCfgItem{BLDCFG_VRM_GFX_LOW_POWER_THRESHOLD}
+ IN UINT32 SlewRate; ///< Vrm Slew Rate.
+ ///< @BldCfgItem{BLDCFG_VRM_SLEW_RATE}
+ ///< @BldCfgItem{BLDCFG_VRM_NB_SLEW_RATE}
+ ///< @BldCfgItem{BLDCFG_VRM_GFX_SLEW_RATE}
+ IN BOOLEAN HiSpeedEnable; ///< Select high speed VRM.
+ ///< @BldCfgItem{BLDCFG_VRM_HIGH_SPEED_ENABLE}
+ ///< @BldCfgItem{BLDCFG_VRM_NB_HIGH_SPEED_ENABLE}
+ ///< @BldCfgItem{BLDCFG_VRM_GFX_HIGH_SPEED_ENABLE}
+ IN UINT32 MaximumCurrentLimit; ///< Vrm Maximum Current Limit.
+ ///< @BldCfgItem{BLDCFG_VRM_MAXIMUM_CURRENT_LIMIT}
+ ///< @BldCfgItem{BLDCFG_VRM_NB_MAXIMUM_CURRENT_LIMIT}
+ ///< @BldCfgItem{BLDCFG_VRM_GFX_MAXIMUM_CURRENT_LIMIT}
+ IN UINT32 SviOcpLevel; ///< SVI OCP Level.
+ ///< @BldCfgItem{BLDCFG_VRM_SVI_OCP_LEVEL}
+ ///< @BldCfgItem{BLDCFG_VRM_NB_SVI_OCP_LEVEL}
+ ///< @BldCfgItem{BLDCFG_VRM_GFX_SVI_OCP_LEVEL}
+} PLATFORM_VRM_CONFIGURATION;
+
+/// The VRM types to characterize.
+typedef enum {
+ CoreVrm, ///< VDD plane.
+ NbVrm, ///< VDDNB plane.
+ GfxVrm, ///< GFX plane.
+ MaxVrmType ///< Not a valid VRM type, use for limit checking.
+} PLATFORM_VRM_TYPE;
+
+/// The StapmBoost settings.
+typedef enum {
+ StapmBoostDisabled, ///< Disable Stapm Boost
+ StapmBoostEnabled, ///< Enable Stapm Boost
+ StapmBoostSystemConfig ///< Default setting uses IRM programming setting
+} STAPM_BOOST_TYPE;
+
+
+/// These to specify how the system is to be configured for STAPM
+typedef struct {
+ IN UINT32 CfgStapmScalar; ///< Specify a % scalar to adjust this. Leave this unused for now until it is figured out.
+ ///< @BldCfgItem{BLDCFG_STAPM_SCALAR}
+ IN UINT32 CfgStapmBoost; ///< If STAPM boost is enabled. System will actively track skin temperature and will allow higher performance till Skin temperature is below the limit
+ ///< @BldCfgItem{BLDCFG_STAPM_BOOST}
+ IN UINT32 CfgStapmTimeConstant; ///< Maximum power that the APU is allowed to consume when STAPM is enabled and Skin temperature is below the limit.
+ ///< Specified time in seconds.
+ ///< @BldCfgItem{BLDCFG_STAPM_TIME_CONSTANT}
+} PLATFORM_STAPM_CONFIGURATION;
+
+/// FCH Platform Configuration Policy
+typedef struct {
+ IN UINT16 CfgSmbus0BaseAddress; ///< SMBUS0 Controller Base Address
+ IN UINT16 CfgSmbus1BaseAddress; ///< SMBUS1 Controller Base Address
+ IN UINT16 CfgSioPmeBaseAddress; ///< I/O base address for LPC I/O target range
+ IN UINT16 CfgAcpiPm1EvtBlkAddr; ///< I/O base address of ACPI power management Event Block
+ IN UINT16 CfgAcpiPm1CntBlkAddr; ///< I/O base address of ACPI power management Control Block
+ IN UINT16 CfgAcpiPmTmrBlkAddr; ///< I/O base address of ACPI power management Timer Block
+ IN UINT16 CfgCpuControlBlkAddr; ///< I/O base address of ACPI power management CPU Control Block
+ IN UINT16 CfgAcpiGpe0BlkAddr; ///< I/O base address of ACPI power management General Purpose Event Block
+ IN UINT16 CfgSmiCmdPortAddr; ///< I/O base address of ACPI SMI Command Block
+ IN UINT16 CfgAcpiPmaCntBlkAddr; ///< I/O base address of ACPI power management additional control block
+ IN UINT32 CfgGecShadowRomBase; ///< 32-bit base address to the GEC shadow ROM
+ IN UINT32 CfgWatchDogTimerBase; ///< Watchdog Timer base address
+ IN UINT32 CfgSpiRomBaseAddress; ///< Base address for the SPI ROM controller
+ IN UINT32 CfgHpetBaseAddress; ///< HPET MMIO base address
+ IN UINT32 CfgAzaliaSsid; ///< Subsystem ID of HD Audio controller
+ IN UINT32 CfgSmbusSsid; ///< Subsystem ID of SMBUS controller
+ IN UINT32 CfgIdeSsid; ///< Subsystem ID of IDE controller
+ IN UINT32 CfgSataAhciSsid; ///< Subsystem ID of SATA controller in AHCI mode
+ IN UINT32 CfgSataIdeSsid; ///< Subsystem ID of SATA controller in IDE mode
+ IN UINT32 CfgSataRaid5Ssid; ///< Subsystem ID of SATA controller in RAID5 mode
+ IN UINT32 CfgSataRaidSsid; ///< Subsystem ID of SATA controller in RAID mode
+ IN UINT32 CfgEhciSsid; ///< Subsystem ID of EHCI
+ IN UINT32 CfgOhciSsid; ///< Subsystem ID of OHCI
+ IN UINT32 CfgLpcSsid; ///< Subsystem ID of LPC ISA Bridge
+ IN UINT32 CfgSdSsid; ///< Subsystem ID of SecureDigital controller
+ IN UINT32 CfgXhciSsid; ///< Subsystem ID of XHCI
+ IN BOOLEAN CfgFchPort80BehindPcib; ///< Is port80 cycle going to the PCI bridge
+ IN BOOLEAN CfgFchEnableAcpiSleepTrap; ///< ACPI sleep SMI enable/disable
+ IN GPP_LINKMODE CfgFchGppLinkConfig; ///< GPP link configuration
+ IN BOOLEAN CfgFchGppPort0Present; ///< Is FCH GPP port 0 present
+ IN BOOLEAN CfgFchGppPort1Present; ///< Is FCH GPP port 1 present
+ IN BOOLEAN CfgFchGppPort2Present; ///< Is FCH GPP port 2 present
+ IN BOOLEAN CfgFchGppPort3Present; ///< Is FCH GPP port 3 present
+ IN BOOLEAN CfgFchGppPort0HotPlug; ///< Is FCH GPP port 0 hotplug capable
+ IN BOOLEAN CfgFchGppPort1HotPlug; ///< Is FCH GPP port 1 hotplug capable
+ IN BOOLEAN CfgFchGppPort2HotPlug; ///< Is FCH GPP port 2 hotplug capable
+ IN BOOLEAN CfgFchGppPort3HotPlug; ///< Is FCH GPP port 3 hotplug capable
+
+ IN UINT8 CfgFchEsataPortBitMap; ///< ESATA Port definition, eg: [0]=1, means port 0 is ESATA capable
+ IN UINT8 CfgFchIrPinControl; ///< Register bitfield describing Infrared Pin Control:
+ ///< [0] - IR Enable 0
+ ///< [1] - IR Enable 1
+ ///< [2] - IR Tx0
+ ///< [3] - IR Tx1
+ ///< [4] - IR Open Drain
+ ///< [5] - IR Enable LED
+ IN SD_CLOCK_CONTROL CfgFchSdClockControl; ///< FCH SD Clock Control
+ IN SCI_MAP_CONTROL *CfgFchSciMapControl; ///< FCH SCI Mapping Control
+ IN SATA_PHY_CONTROL *CfgFchSataPhyControl; ///< FCH SATA PHY Control
+ IN GPIO_CONTROL *CfgFchGpioControl; ///< FCH GPIO Control
+ IN BOOLEAN CfgFchRtcWorkAround; ///< FCH RTC Workaround
+ IN BOOLEAN CfgFchUsbPortDisWorkAround; ///< FCH USB Workaround
+} FCH_PLATFORM_POLICY;
+
+
+/// Build Option/Configuration Boolean Structure.
+typedef struct {
+ IN AMD_CODE_HEADER VersionString; ///< AMD embedded code version string
+
+ //Build Option Area
+ IN BOOLEAN OptionUDimms; ///< @ref BLDOPT_REMOVE_UDIMMS_SUPPORT "BLDOPT_REMOVE_UDIMMS_SUPPORT"
+ IN BOOLEAN OptionRDimms; ///< @ref BLDOPT_REMOVE_RDIMMS_SUPPORT "BLDOPT_REMOVE_RDIMMS_SUPPORT"
+ IN BOOLEAN OptionLrDimms; ///< @ref BLDOPT_REMOVE_LRDIMMS_SUPPORT "BLDOPT_REMOVE_LRDIMMS_SUPPORT"
+ IN BOOLEAN OptionEcc; ///< @ref BLDOPT_REMOVE_ECC_SUPPORT "BLDOPT_REMOVE_ECC_SUPPORT"
+ IN BOOLEAN OptionBankInterleave; ///< @ref BLDOPT_REMOVE_BANK_INTERLEAVE "BLDOPT_REMOVE_BANK_INTERLEAVE"
+ IN BOOLEAN OptionDctInterleave; ///< @ref BLDOPT_REMOVE_DCT_INTERLEAVE "BLDOPT_REMOVE_DCT_INTERLEAVE"
+ IN BOOLEAN OptionNodeInterleave; ///< @ref BLDOPT_REMOVE_NODE_INTERLEAVE "BLDOPT_REMOVE_NODE_INTERLEAVE"
+ IN BOOLEAN OptionParallelTraining; ///< @ref BLDOPT_REMOVE_PARALLEL_TRAINING "BLDOPT_REMOVE_PARALLEL_TRAINING"
+ IN BOOLEAN OptionOnlineSpare; ///< @ref BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT "BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT"
+ IN BOOLEAN OptionMemRestore; ///< @ref BLDOPT_REMOVE_MEM_RESTORE_SUPPORT "BLDOPT_REMOVE_MEM_RESTORE_SUPPORT"
+ IN BOOLEAN OptionAcpiPstates; ///< @ref BLDOPT_REMOVE_ACPI_PSTATES "BLDOPT_REMOVE_ACPI_PSTATES"
+ IN BOOLEAN OptionCrat; ///< @ref BLDOPT_REMOVE_CRAT "BLDOPT_REMOVE_CRAT"
+ IN BOOLEAN OptionCdit; ///< @ref BLDOPT_REMOVE_CDIT "BLDOPT_REMOVE_CDIT"
+ IN BOOLEAN OptionWhea; ///< @ref BLDOPT_REMOVE_WHEA "BLDOPT_REMOVE_WHEA"
+ IN BOOLEAN OptionDmi; ///< @ref BLDOPT_REMOVE_DMI "BLDOPT_REMOVE_DMI"
+ IN BOOLEAN OptionEarlySamples; ///< @ref BLDOPT_REMOVE_EARLY_SAMPLES "BLDOPT_REMOVE_EARLY_SAMPLES"
+ IN BOOLEAN OptionAddrToCsTranslator; ///< ADDR_TO_CS_TRANSLATOR
+
+ //Build Configuration Area
+ IN UINT64 CfgPciMmioAddress; ///< Pci Mmio Base Address to use for PCI Config accesses.
+ ///< Build-time customizable only - @BldCfgItem{BLDCFG_PCI_MMIO_BASE}
+ IN UINT32 CfgPciMmioSize; ///< Pci Mmio region Size.
+ ///< Build-time customizable only - @BldCfgItem{BLDCFG_PCI_MMIO_SIZE}
+ IN PLATFORM_VRM_CONFIGURATION CfgPlatVrmCfg[MaxVrmType]; ///< Several configuration settings for the voltage regulator modules.
+ IN UINT32 CfgCpuFrequencyLimit; ///< CPU frequency limit
+ IN PLATFORM_CONNECTED_STANDBY_MODES CfgPlatformConnectedStandbyMode; ///< Enable or disable connected standby
+ IN UINT32 CfgPlatNumIoApics; ///< The number of IO APICS for the platform.
+ IN UINT32 CfgMemInitPstate; ///< Memory Init Pstate.
+ IN PLATFORM_CSTATE_MODES CfgPlatformCStateMode; ///< Select the C-State Mode that will used.
+ IN UINT32 CfgPlatformCStateOpData; ///< An IO port or additional C-State setup data, depends on C-State mode.
+ IN UINT16 CfgPlatformCStateIoBaseAddress; ///< Specifies I/O ports that can be used to allow CPU to enter CStates
+ IN PLATFORM_CPB_MODES CfgPlatformCpbMode; ///< Enable or disable core performance boost
+ IN UINT32 CfgCoreLevelingMode; ///< Apply any downcoring or core count leveling as specified.
+ IN PERFORMANCE_PROFILE CfgPerformanceProfile; ///< The platform's control flow mode and platform performance settings.
+
+ IN UINT32 CfgAmdPlatformType; ///< Designate the platform as a Server, Desktop, or Mobile.
+ IN UINT32 CfgAmdPowerCeiling; ///< PowerCeiling, specifies a maximum power usage limit for the platform
+ IN UINT16 CfgHtcTemperatureLimit; ///< Hardware Thermal Control temperature limit in tenths of degrees Celsius.
+ IN UINT16 CfgLhtcTemperatureLimit; ///< Local Hardware Thermal Control temperature limit in tenths of degrees Celsius.
+
+ IN UINT32 CfgMemoryBusFrequencyLimit; ///< Memory Bus Frequency Limit.
+ ///< Build-time customizable only - @BldCfgItem{BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT}
+ IN BOOLEAN CfgMemoryModeUnganged; ///< Memory Mode Unganged.
+ ///< Build-time customizable only - @BldCfgItem{BLDCFG_MEMORY_MODE_UNGANGED}
+ IN BOOLEAN CfgMemoryQuadRankCapable; ///< Memory Quad Rank Capable.
+ ///< Build-time customizable only - @BldCfgItem{BLDCFG_MEMORY_QUAD_RANK_CAPABLE}
+ IN UINT32 CfgMemoryQuadrankType; ///< Memory Quadrank Type.
+ ///< Build-time customizable only - @BldCfgItem{BLDCFG_MEMORY_QUADRANK_TYPE}
+ IN BOOLEAN CfgMemoryRDimmCapable; ///< Memory RDIMM Capable.
+ IN BOOLEAN CfgMemoryLRDimmCapable; ///< Memory LRDIMM Capable.
+ IN BOOLEAN CfgMemoryUDimmCapable; ///< Memory UDIMM Capable.
+ IN BOOLEAN CfgMemorySODimmCapable; ///< Memory SODimm Capable.
+ ///< Build-time customizable only - @BldCfgItem{BLDCFG_MEMORY_SODIMM_CAPABLE}
+ IN BOOLEAN CfgLimitMemoryToBelow1Tb; ///< Limit memory address space to below 1TB
+ IN BOOLEAN CfgMemoryEnableBankSwapOnly; ///< Memory Enable Bank Swap Only @BldCfgItem{BLDCFG_MEMORY_ENABLE_BANK_SWAP_ONLY}
+ IN BOOLEAN CfgMemoryEnableBankInterleaving; ///< Memory Enable Bank Interleaving.
+ IN BOOLEAN CfgMemoryEnableNodeInterleaving; ///< Memory Enable Node Interleaving.
+ IN BOOLEAN CfgMemoryChannelInterleaving; ///< Memory Channel Interleaving.
+ IN BOOLEAN CfgMemoryPowerDown; ///< Memory Power Down.
+ IN UINT8 CfgMemoryMacDefault; ///< Memory DRAM MAC Default
+ IN BOOLEAN CfgMemoryExtendedTemperatureRange; ///< Memory Extended Temperature Range
+ IN UINT32 CfgPowerDownMode; ///< Power Down Mode.
+ IN BOOLEAN CfgOnlineSpare; ///< Online Spare.
+ IN BOOLEAN CfgMemoryParityEnable; ///< Memory Parity Enable.
+ IN BOOLEAN CfgBankSwizzle; ///< Bank Swizzle.
+ IN UINT32 CfgTimingModeSelect; ///< Timing Mode Select.
+ IN UINT32 CfgMemoryClockSelect; ///< Memory Clock Select.
+ IN BOOLEAN CfgDqsTrainingControl; ///< Dqs Training Control.
+ ///< Build-time customizable only - @BldCfgItem{BLDCFG_DQS_TRAINING_CONTROL}
+ IN BOOLEAN CfgIgnoreSpdChecksum; ///< Ignore Spd Checksum.
+ ///< Build-time customizable only - @BldCfgItem{BLDCFG_IGNORE_SPD_CHECKSUM}
+ IN BOOLEAN CfgUseBurstMode; ///< Use Burst Mode.
+ ///< Build-time customizable only - @BldCfgItem{BLDCFG_USE_BURST_MODE}
+ IN BOOLEAN CfgMemoryAllClocksOn; ///< Memory All Clocks On.
+ ///< Build-time customizable only - @BldCfgItem{BLDCFG_MEMORY_ALL_CLOCKS_ON}
+ IN BOOLEAN CfgDdrPhyDllBypassMode; ///< Enable DllPDBypassMode
+ IN BOOLEAN CfgEnableEccFeature; ///< Enable ECC Feature.
+ IN BOOLEAN CfgEccRedirection; ///< ECC Redirection.
+ ///< Build-time customizable only - @BldCfgItem{BLDCFG_ECC_REDIRECTION}
+ IN UINT16 CfgScrubDramRate; ///< Scrub Dram Rate.
+ ///< Build-time customizable only - @BldCfgItem{BLDCFG_SCRUB_DRAM_RATE}
+ IN UINT16 CfgScrubL2Rate; ///< Scrub L2Rate.
+ ///< Build-time customizable only - @BldCfgItem{BLDCFG_SCRUB_L2_RATE}
+ IN UINT16 CfgScrubL3Rate; ///< Scrub L3Rate.
+ ///< Build-time customizable only - @BldCfgItem{BLDCFG_SCRUB_L3_RATE}
+ IN UINT16 CfgScrubIcRate; ///< Scrub Ic Rate.
+ ///< Build-time customizable only - @BldCfgItem{BLDCFG_SCRUB_IC_RATE}
+ IN UINT16 CfgScrubDcRate; ///< Scrub Dc Rate.
+ ///< Build-time customizable only - @BldCfgItem{BLDCFG_SCRUB_DC_RATE}
+ IN BOOLEAN CfgEccSyncFlood; ///< ECC Sync Flood.
+ ///< Build-time customizable only - @BldCfgItem{BLDCFG_ECC_SYNC_FLOOD}
+ IN UINT16 CfgEccSymbolSize; ///< ECC Symbol Size.
+ ///< Build-time customizable only - @BldCfgItem{BLDCFG_ECC_SYMBOL_SIZE}
+ IN UINT64 CfgHeapDramAddress; ///< Heap contents will be temporarily stored in this address during the transition.
+ ///< Build-time customizable only - @BldCfgItem{BLDCFG_HEAP_DRAM_ADDRESS}
+ IN BOOLEAN CfgNodeMem1GBAlign; ///< Node Mem 1GB boundary Alignment
+ IN BOOLEAN CfgS3LateRestore; ///< S3 Late Restore
+ IN BOOLEAN CfgAcpiPstateIndependent; ///< PSD method dependent/Independent
+ IN UINT32 CfgAcpiPstatesPsdPolicy; ///< PSD policy
+ IN AP_MTRR_SETTINGS *CfgApMtrrSettingsList; ///< The AP's MTRR settings before final halt
+ ///< Build-time customizable only - @BldCfgItem{BLDCFG_AP_MTRR_SETTINGS_LIST}
+ IN UMA_VERSION CfgUmaVersion; ///< Uma Version
+ IN UMA_MODE CfgUmaMode; ///< Uma Mode
+ IN UINT32 CfgUmaSize; ///< Uma Size [31:0]=Addr[47:16]
+ IN BOOLEAN CfgUmaAbove4G; ///< Uma Above 4G Support
+ IN UMA_ALIGNMENT CfgUmaAlignment; ///< Uma alignment
+ IN BOOLEAN CfgProcessorScopeInSb; ///< ACPI Processor Object in \\_SB scope
+ IN CHAR8 CfgProcessorScopeName0; ///< OEM specific 1st character of processor scope name.
+ IN CHAR8 CfgProcessorScopeName1; ///< OEM specific 2nd character of processor scope name.
+ IN UINT8 CfgGnbHdAudio; ///< GNB HD Audio
+ IN UINT8 CfgAbmSupport; ///< Abm Support
+ IN UINT8 CfgDynamicRefreshRate; ///< DRR Dynamic Refresh Rate
+ IN UINT16 CfgLcdBackLightControl; ///< LCD Backlight Control
+ IN UINT8 CfgGnb3dStereoPinIndex; ///< 3D Stereo Pin ID.
+ IN UINT32 CfgTempPcieMmioBaseAddress; ///< Temp pcie MMIO base Address
+ ///< Build-time customizable only - @BldCfgItem{BLDCFG_TEMP_PCIE_MMIO_BASE_ADDRESS}
+ IN UINT32 CfgGnbIGPUSSID; ///< Gnb internal GPU SSID
+ ///< Build-time customizable only - @BldCfgItem{BLDCFG_IGPU_SUBSYSTEM_ID}
+ IN UINT32 CfgGnbHDAudioSSID; ///< Gnb HD Audio SSID
+ ///< Build-time customizable only - @BldCfgItem{BLDCFG_IGPU_HD_AUDIO_SUBSYSTEM_ID}
+ IN UINT32 CfgGnbPcieSSID; ///< Gnb PCIe SSID
+ ///< Build-time customizable only - @BldCfgItem{BLDCFG_APU_PCIE_PORTS_SUBSYSTEM_ID}
+ IN UINT16 CfgLvdsSpreadSpectrum; ///< Lvds Spread Spectrum
+ ///< Build-time customizable only - @BldCfgItem{BLDCFG_GFX_LVDS_SPREAD_SPECTRUM}
+ IN UINT16 CfgLvdsSpreadSpectrumRate; ///< Lvds Spread Spectrum Rate
+ ///< Build-time customizable only - @BldCfgItem{BLDCFG_GFX_LVDS_SPREAD_SPECTRUM_RATE}
+ IN FCH_PLATFORM_POLICY *FchBldCfg; ///< FCH platform build configuration policy
+
+ IN BOOLEAN CfgIommuSupport; ///< IOMMU support
+ IN UINT8 CfgLvdsPowerOnSeqDigonToDe; ///< Panel initialization timing
+ IN UINT8 CfgLvdsPowerOnSeqDeToVaryBl; ///< Panel initialization timing
+ IN UINT8 CfgLvdsPowerOnSeqDeToDigon; ///< Panel initialization timing
+ IN UINT8 CfgLvdsPowerOnSeqVaryBlToDe; ///< Panel initialization timing
+ IN UINT8 CfgLvdsPowerOnSeqOnToOffDelay; ///< Panel initialization timing
+ IN UINT8 CfgLvdsPowerOnSeqVaryBlToBlon; ///< Panel initialization timing
+ IN UINT8 CfgLvdsPowerOnSeqBlonToVaryBl; ///< Panel initialization timing
+ IN UINT16 CfgLvdsMaxPixelClockFreq; ///< The maximum pixel clock frequency supported
+ IN UINT32 CfgLcdBitDepthControlValue; ///< The LCD bit depth control settings
+ IN UINT8 CfgLvds24bbpPanelMode; ///< The LVDS 24 BBP mode
+ IN LVDS_MISC_CONTROL CfgLvdsMiscControl; ///< THe LVDS Misc control
+ IN UINT16 CfgPcieRefClkSpreadSpectrum; ///< PCIe Reference Clock Spread Spectrum
+ ///< Build-time customizable only - @BldCfgItem{BLDCFG_PCIE_REFCLK_SPREAD_SPECTRUM}
+ IN BOOLEAN CfgExternalVrefCtlFeature; ///< External Vref control
+ IN FORCE_TRAIN_MODE CfgForceTrainMode; ///< Force Train Mode
+ IN BOOLEAN CfgGnbRemoteDisplaySupport; ///< Wireless Display Support
+ IN IOMMU_EXCLUSION_RANGE_DESCRIPTOR *CfgIvrsExclusionRangeList;
+ IN BOOLEAN CfgGnbSyncFloodPinAsNmi; ///< @ref BLDCFG_USE_SYNCFLOOD_AS_NMI "BLDCFG_USE_SYNCFLOOD_AS_NMI"
+ IN UINT8 CfgIgpuEnableDisablePolicy; ///< This item defines the iGPU Enable/Disable policy
+ ///< @li 0 = Auto - use current default
+ ///< @li 2 = Disable iGPU if ANY PCI or PCIe Graphics card is present
+ ///< @BldCfgItem{BLDCFG_IGPU_ENABLE_DISABLE_POLICY}
+ IN UINT8 CfgGnbSwTjOffset; ///< Software-writeable TjOffset to account for changes in junction temperature
+ ///< Build-time customizable only - @BldCfgItem{BLDCFG_GNB_THERMAL_SENSOR_CORRECTION}
+ IN UINT8 CfgLvdsMiscVoltAdjustment; ///< Register LVDS_CTRL_4 to adjust LVDS output voltage
+ ///< Build-time customizable only - @BldCfgItem{BLDCFG_LVDS_MISC_VOL_ADJUSTMENT}
+ IN DISPLAY_MISC_CONTROL CfgDisplayMiscControl; ///< The Display Misc control
+ IN DP_FIXED_VOLT_SWING_TYPE CfgDpFixedVoltSwingType;///< To indicate fixed voltage swing value
+ ///< @BldCfgItem{BLDCFG_DP_FIXED_VOLT_SWING}
+ IN TECHNOLOGY_TYPE CfgDimmTypeUsedInMixedConfig; ///< Select the preferred technology type that AGESA will enable
+ ///< when it is mixed with other technology types.
+ IN BOOLEAN CfgHybridBoostEnable; ///< HyBrid Boost support
+ ///< @BldCfgItem{BLDCFG_HYBRID_BOOST_ENABLE}
+ IN UINT64 CfgGnbIoapicAddress; ///< GNB IOAPIC Base Address(NULL if platform configured)
+ ///< @BldCfgItem{BLDCFG_GNB_IOAPIC_ADDRESS}
+ IN BOOLEAN CfgDataEyeEn; ///< Enable get 2D Data Eye
+ IN UINT32 CfgBatteryBoostTune; ///< @BldCfgItem{BLDCFG_BATTERY_BOOST_TUNE}
+ IN BOOLEAN CfgDramDoubleRefreshRateEn; ///< Double DRAM refresh rate
+ IN DISPLAY_RESOLUTION CfgGnbResolution; ///< Display Resolution
+ ///< @BldCfgItem{BLDCFG_RESOLUTION}
+ IN ACP_SIZE CfgGnbAcpSize; ///< ACP size [31:0]=Addr[47:16]
+ ///< @BldCfgItem{BLDCFG_ACP_SIZE}
+ IN PMU_TRAIN_MODE CfgPmuTrainMode; ///< Force Train Mode
+ ///< @BldCfgItem{BLDCFG_PMU_TRAINING_MODE}
+ IN UINT8 CfgMemoryPhyVoltage; ///< Memory Phy voltage (VDDR)
+ ///< @BldCfgItem{BLDCFG_MEMORY_PHY_VOLTAGE}
+ IN UINT32 CfgGpuFrequencyLimit; ///< @BldCfgItem{BLDCFG_GPU_FREQUENCY_LIMIT}
+ IN UINT8 CfgMaxNumAudioEndpoints; ///< @BldCfgItem{BLDCFG_MAX_NUM_AUDIO_ENDPOINTS}
+ IN BOOLEAN CfgBapmEnable; ///< @BldCfgItem{BLDCFG_BAPM_ENABLE}
+ IN UINT32 CfgGnbAzI2sBusSelect; ///< Acp AZ/I2sBus select
+ ///< @BldCfgItem{BLDCFG_GNB_AZ_I2SBUS_SELECT}
+ IN UINT32 CfgGnbAzI2sBusPinConfig; ///< Acp AZ/I2sBus pin configuration
+ ///< @BldCfgItem{BLDCFG_GNB_AZ_I2SBUS_PIN_CONFIG}
+ IN UINT32 CfgPkgPwrLimitAC; ///< Package Power Limit under AC
+ ///< @BldCfgItem{BLDCFG_PPT_LIMIT_AC}
+ IN UINT32 CfgPkgPwrLimitDC; ///< Package Power Limit under DC
+ ///< @BldCfgItem{BLDCFG_PPT_LIMIT_DC}
+ IN UINT32 CfgSystemConfiguration; ///< SMU System Configuration
+ ///< @BldCfgItem{BLDCFG_SYSTEM_CONFIGURATION}
+ IN PLATFORM_STAPM_CONFIGURATION CfgPlatStapmConfig; ///< Several configuration settings for the STAPM.
+ IN UINT8 CfgEDPv1_4VSMode; ///< @BldCfgItem{BLDCFG_EDP_V1_4_VS_MODE}
+ IN UINT8 CfgExtHDMIReDrvSlvAddr; ///< @BldCfgItem{BLDCFG_EXT_HDMI_RE_DRIVE_SLAVE_ADDR}
+ IN UINT8 CfgExtHDMIReDrvRegNum; ///< @BldCfgItem{BLDCFG_EXT_HDMI_RE_DRIVE_REG_NUM}
+ IN UINT64 CfgExtHDMIRegSetting; ///< @BldCfgItem{BLDCFG_EXT_HDMI_RE_DRIVE_REG_INFO}
+ IN UINT32 CfgThermCtlLimit; ///< @BldCfgItem{BLDCFG_THERMCTL_LIMIT}
+ IN UINT32 CfgCodecVerbTable; ///< @BldCfgItem{BLDCFG_CODEC_VERB_TABLE}
+ IN UINT32 CfgGnbAzSsid; ///< @BldCfgItem{BLDCFG_GNB_AZ_SSID}
+ IN UINT16 CfgCustomVddioVoltage; ///< Custom VDDIO voltage
+ ///< @BldCfgItem{BLDCFG_CUSTOM_VDDIO_VOLTAGE}
+ IN BOOLEAN CfgAcpPowerGating; ///< @BldCfgItem{BLDCFG_ACP_POWER_GATING}
+ IN BOOLEAN Reserved; ///< reserved...
+} BUILD_OPT_CFG;
+
+/// A structure containing platform specific operational characteristics. This
+/// structure is initially populated by the initializer with a copy of the same
+/// structure that was created at build time using the build configuration controls.
+typedef struct _PLATFORM_CONFIGURATION {
+ IN PERFORMANCE_PROFILE PlatformProfile; ///< Several configuration settings for the processor.
+ IN UINT8 CoreLevelingMode; ///< Indicates how to balance the number of cores per processor.
+ ///< @BldCfgItem{BLDCFG_CORE_LEVELING_MODE}
+ IN PLATFORM_CSTATE_MODES CStateMode; ///< Specifies the method of C-State enablement - Disabled, or C6.
+ ///< @BldCfgItem{BLDCFG_PLATFORM_CSTATE_MODE}
+ IN UINT32 CStatePlatformData; ///< This element specifies some pertinent data needed for the operation of the Cstate feature
+ ///< If CStateMode is CStateModeC6, this item is reserved
+ ///< @BldCfgItem{BLDCFG_PLATFORM_CSTATE_OPDATA}
+ IN UINT16 CStateIoBaseAddress; ///< This item specifies a free block of 8 consecutive bytes of I/O ports that
+ ///< can be used to allow the CPU to enter Cstates.
+ ///< @BldCfgItem{BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS}
+ IN PLATFORM_CPB_MODES CpbMode; ///< Specifies the method of core performance boost enablement - Disabled, or Auto.
+ ///< @BldCfgItem{BLDCFG_PLATFORM_CPB_MODE}
+ IN BOOLEAN UserOptionDmi; ///< When set to TRUE, the DMI data table is generated.
+ IN BOOLEAN UserOptionPState; ///< When set to TRUE, the PState data tables are generated.
+ IN BOOLEAN UserOptionCrat; ///< When set to TRUE, the CRAT data table is generated.
+ IN BOOLEAN UserOptionCdit; ///< When set to TRUE, the CDIT data table is generated.
+ IN BOOLEAN UserOptionWhea; ///< When set to TRUE, the WHEA data table is generated.
+ IN UINT32 PowerCeiling; ///< P-State Ceiling Enabling Deck - Max power milli-watts.
+ IN BOOLEAN ForcePstateIndependent; ///< Deprecated in favor of PstatesPsdPolicy.
+ ///< P-State _PSD is forced independent.
+ ///< @BldCfgItem{BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT}
+ IN UINT32 PstatesPsdPolicy; ///< PSD policy
+ ///< @BldCfgItem{BLDCFG_ACPI_PSTATES_PSD_POLICY}
+ IN UINT32 CpuFrequencyLimit; ///< @BldCfgItem{BLDCFG_CPU_FREQUENCY_LIMIT}
+ IN PLATFORM_CONNECTED_STANDBY_MODES CfgPlatformConnectedStandbyMode; ///< @BldCfgItem{BLDCFG_CPU_CONNECTED_STANDBY_MODE}
+ IN UINT32 NumberOfIoApics; ///< Number of I/O APICs in the system
+ ///< @BldCfgItem{BLDCFG_PLATFORM_NUM_IO_APICS}
+ IN PLATFORM_VRM_CONFIGURATION VrmProperties[MaxVrmType]; ///< Several configuration settings for the voltage regulator modules.
+ IN BOOLEAN ProcessorScopeInSb; ///< ACPI Processor Object in \\_SB scope
+ ///< @BldCfgItem{BLDCFG_PROCESSOR_SCOPE_IN_SB}
+ IN CHAR8 ProcessorScopeName0; ///< OEM specific 1st character of processor scope name.
+ ///< @BldCfgItem{BLDCFG_PROCESSOR_SCOPE_NAME0}
+ IN CHAR8 ProcessorScopeName1; ///< OEM specific 2nd character of processor scope name.
+ ///< @BldCfgItem{BLDCFG_PROCESSOR_SCOPE_NAME1}
+ IN UINT8 GnbHdAudio; ///< Control GFX HD Audio controller(Used for HDMI and DP display output),
+ ///< essentially it enables function 1 of graphics device.
+ ///< @li 0 = HD Audio disable
+ ///< @li 1 = HD Audio enable
+ ///< @BldCfgItem{BLDCFG_CFG_GNB_HD_AUDIO}
+ IN UINT8 AbmSupport; ///< Automatic adjust LVDS/eDP Back light level support.It is
+ ///< characteristic specific to display panel which used by platform design.
+ ///< @li 0 = ABM support disabled
+ ///< @li 1 = ABM support enabled
+ ///< @BldCfgItem{BLDCFG_CFG_ABM_SUPPORT}
+ IN UINT8 DynamicRefreshRate; ///< Adjust refresh rate on LVDS/eDP.
+ ///< @BldCfgItem{BLDCFG_CFG_DYNAMIC_REFRESH_RATE}
+ IN UINT16 LcdBackLightControl; ///< The PWM frequency to LCD backlight control.
+ ///< If equal to 0 backlight not controlled by iGPU
+ ///< @BldCfgItem{BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL}
+ IN UINT16 HtcTemperatureLimit; ///< The Hardware Thermal Control temperature limit in tenths of degrees Celsius.
+ ///< If equal to 0, use hardware defaults.
+ ///< @BldCfgItem{BLDCFG_HTC_TEMPERATURE_LIMIT}
+ IN UINT16 LhtcTemperatureLimit; ///< The Local Hardware Thermal Control temperature limit in tenths of degrees Celsius.
+ ///< If equal to 0, use hardware defaults.
+ ///< @BldCfgItem{BLDCFG_LHTC_TEMPERATURE_LIMIT}
+ IN DISPLAY_RESOLUTION Resolution; ///< Display Resolution
+ ///< @BldCfgItem{BLDCFG_RESOLUTION}
+ IN ACP_SIZE AcpSize; ///< The size of ACP dram
+ ///< ACP_Size[31:0]=Addr[47:16]
+ ///< @BldCfgItem{BLDCFG_ACP_SIZE}
+ IN UINT32 BatteryBoostTune; ///< @BldCfgItem{BLDCFG_BATTERY_BOOST_TUNE}
+ IN UINT32 PkgPwrLimitAC; ///< Package Power Limit under AC
+ ///< @BldCfgItem{BLDCFG_PPT_LIMIT_AC}
+ IN UINT32 PkgPwrLimitDC; ///< Package Power Limit under DC
+ ///< @BldCfgItem{BLDCFG_PPT_LIMIT_DC}
+ IN UINT32 SystemConfiguration; ///< SMU System Configuration
+ ///< @BldCfgItem{BLDCFG_SYSTEM_CONFIGURATION}
+ IN PLATFORM_STAPM_CONFIGURATION PlatStapmConfig; ///< Several configuration settings for the STAPM.
+ IN UINT32 ThermCtlLimit; ///< @BldCfgItem{BLDCFG_THERMCTL_LIMIT}
+ IN UINT64 AzaliaCodecVerbTable; ///< @BldCfgItem{BLDCFG_CODEC_VERB_TABLE}
+ IN UINT32 AzaliaSsid; ///< @BldCfgItem{BLDCFG_GNB_AZ_SSID}
+ IN UINT32 GnbAzI2sBusSelect; ///< @BldCfgItem{BLDCFG_GNB_AZ_I2SBUS_SELECT}
+ IN UINT32 GnbAzI2sBusPinConfig; ///< @BldCfgItem{BLDCFG_GNB_AZ_I2SBUS_PIN_CONFIG}
+ IN BOOLEAN AcpPowerGating; ///< @BldCfgItem{BLDCFG_ACP_POWER_GATING}
+} PLATFORM_CONFIGURATION;
+
+
+/**********************************************************************
+ * Structures for: AmdInitLate
+ **********************************************************************/
+#define PROC_VERSION_LENGTH 48
+#define MAX_DIMMS_PER_SOCKET 16
+#define PROC_MANU_LENGTH 29
+
+/* Interface Parameter Structures */
+/// DMI Type4 - Processor ID
+typedef struct {
+ OUT UINT32 ProcIdLsd; ///< Lower half of 64b ID
+ OUT UINT32 ProcIdMsd; ///< Upper half of 64b ID
+} TYPE4_PROC_ID;
+
+/// DMI Type 4 - Processor information
+typedef struct {
+ OUT UINT8 T4ProcType; ///< CPU Type
+ OUT UINT8 T4ProcFamily; ///< Family 1
+ OUT TYPE4_PROC_ID T4ProcId; ///< Id
+ OUT UINT8 T4Voltage; ///< Voltage
+ OUT UINT16 T4ExternalClock; ///< External clock
+ OUT UINT16 T4MaxSpeed; ///< Max speed
+ OUT UINT16 T4CurrentSpeed; ///< Current speed
+ OUT UINT8 T4Status; ///< Status
+ OUT UINT8 T4ProcUpgrade; ///< Up grade
+ OUT UINT8 T4CoreCount; ///< Core count
+ OUT UINT8 T4CoreEnabled; ///< Core Enable
+ OUT UINT8 T4ThreadCount; ///< Thread count
+ OUT UINT16 T4ProcCharacteristics; ///< Characteristics
+ OUT UINT16 T4ProcFamily2; ///< Family 2
+ OUT CHAR8 T4ProcVersion[PROC_VERSION_LENGTH]; ///< Cpu version
+ OUT CHAR8 T4ProcManufacturer[PROC_MANU_LENGTH]; ///< Manufacturer
+} TYPE4_DMI_INFO;
+
+/// DMI Type 7 - Cache information
+typedef struct _TYPE7_DMI_INFO {
+ OUT UINT16 T7CacheCfg; ///< Cache cfg
+ OUT UINT16 T7MaxCacheSize; ///< Max size
+ OUT UINT16 T7InstallSize; ///< Install size
+ OUT UINT16 T7SupportedSramType; ///< Supported Sram Type
+ OUT UINT16 T7CurrentSramType; ///< Current type
+ OUT UINT8 T7CacheSpeed; ///< Speed
+ OUT UINT8 T7ErrorCorrectionType; ///< ECC type
+ OUT UINT8 T7SystemCacheType; ///< Cache type
+ OUT UINT8 T7Associativity; ///< Associativity
+} TYPE7_DMI_INFO;
+
+/// DMI Type 16 offset 04h - Location
+typedef enum {
+ OtherLocation = 0x01, ///< Assign 01 to Other
+ UnknownLocation, ///< Assign 02 to Unknown
+ SystemboardOrMotherboard, ///< Assign 03 to systemboard or motherboard
+ IsaAddonCard, ///< Assign 04 to ISA add-on card
+ EisaAddonCard, ///< Assign 05 to EISA add-on card
+ PciAddonCard, ///< Assign 06 to PCI add-on card
+ McaAddonCard, ///< Assign 07 to MCA add-on card
+ PcmciaAddonCard, ///< Assign 08 to PCMCIA add-on card
+ ProprietaryAddonCard, ///< Assign 09 to proprietary add-on card
+ NuBus, ///< Assign 0A to NuBus
+ Pc98C20AddonCard, ///< Assign 0A0 to PC-98/C20 add-on card
+ Pc98C24AddonCard, ///< Assign 0A1 to PC-98/C24 add-on card
+ Pc98EAddoncard, ///< Assign 0A2 to PC-98/E add-on card
+ Pc98LocalBusAddonCard ///< Assign 0A3 to PC-98/Local bus add-on card
+} DMI_T16_LOCATION;
+
+/// DMI Type 16 offset 05h - Memory Error Correction
+typedef enum {
+ OtherUse = 0x01, ///< Assign 01 to Other
+ UnknownUse, ///< Assign 02 to Unknown
+ SystemMemory, ///< Assign 03 to system memory
+ VideoMemory, ///< Assign 04 to video memory
+ FlashMemory, ///< Assign 05 to flash memory
+ NonvolatileRam, ///< Assign 06 to non-volatile RAM
+ CacheMemory ///< Assign 07 to cache memory
+} DMI_T16_USE;
+
+/// DMI Type 16 offset 07h - Maximum Capacity
+typedef enum {
+ Dmi16OtherErrCorrection = 0x01, ///< Assign 01 to Other
+ Dmi16UnknownErrCorrection, ///< Assign 02 to Unknown
+ Dmi16NoneErrCorrection, ///< Assign 03 to None
+ Dmi16Parity, ///< Assign 04 to parity
+ Dmi16SingleBitEcc, ///< Assign 05 to Single-bit ECC
+ Dmi16MultiBitEcc, ///< Assign 06 to Multi-bit ECC
+ Dmi16Crc ///< Assign 07 to CRC
+} DMI_T16_ERROR_CORRECTION;
+
+/// DMI Type 16 - Physical Memory Array
+typedef struct {
+ OUT DMI_T16_LOCATION Location; ///< The physical location of the Memory Array,
+ ///< whether on the system board or an add-in board.
+ OUT DMI_T16_USE Use; ///< Identifies the function for which the array
+ ///< is used.
+ OUT DMI_T16_ERROR_CORRECTION MemoryErrorCorrection; ///< The primary hardware error correction or
+ ///< detection method supported by this memory array.
+ OUT UINT16 NumberOfMemoryDevices; ///< The number of slots or sockets available
+ ///< for memory devices in this array.
+} TYPE16_DMI_INFO;
+
+/// DMI Type 17 offset 0Eh - Form Factor
+typedef enum {
+ OtherFormFactor = 0x01, ///< Assign 01 to Other
+ UnknowFormFactor, ///< Assign 02 to Unknown
+ SimmFormFactor, ///< Assign 03 to SIMM
+ SipFormFactor, ///< Assign 04 to SIP
+ ChipFormFactor, ///< Assign 05 to Chip
+ DipFormFactor, ///< Assign 06 to DIP
+ ZipFormFactor, ///< Assign 07 to ZIP
+ ProprietaryCardFormFactor, ///< Assign 08 to Proprietary Card
+ DimmFormFactorFormFactor, ///< Assign 09 to DIMM
+ TsopFormFactor, ///< Assign 10 to TSOP
+ RowOfChipsFormFactor, ///< Assign 11 to Row of chips
+ RimmFormFactor, ///< Assign 12 to RIMM
+ SodimmFormFactor, ///< Assign 13 to SODIMM
+ SrimmFormFactor, ///< Assign 14 to SRIMM
+ FbDimmFormFactor ///< Assign 15 to FB-DIMM
+} DMI_T17_FORM_FACTOR;
+
+/// DMI Type 17 offset 12h - Memory Type
+typedef enum {
+ OtherMemType = 0x01, ///< Assign 01 to Other
+ UnknownMemType, ///< Assign 02 to Unknown
+ DramMemType, ///< Assign 03 to DRAM
+ EdramMemType, ///< Assign 04 to EDRAM
+ VramMemType, ///< Assign 05 to VRAM
+ SramMemType, ///< Assign 06 to SRAM
+ RamMemType, ///< Assign 07 to RAM
+ RomMemType, ///< Assign 08 to ROM
+ FlashMemType, ///< Assign 09 to Flash
+ EepromMemType, ///< Assign 10 to EEPROM
+ FepromMemType, ///< Assign 11 to FEPROM
+ EpromMemType, ///< Assign 12 to EPROM
+ CdramMemType, ///< Assign 13 to CDRAM
+ ThreeDramMemType, ///< Assign 14 to 3DRAM
+ SdramMemType, ///< Assign 15 to SDRAM
+ SgramMemType, ///< Assign 16 to SGRAM
+ RdramMemType, ///< Assign 17 to RDRAM
+ DdrMemType, ///< Assign 18 to DDR
+ Ddr2MemType, ///< Assign 19 to DDR2
+ Ddr2FbdimmMemType, ///< Assign 20 to DDR2 FB-DIMM
+ Ddr3MemType = 0x18, ///< Assign 24 to DDR3
+ Fbd2MemType ///< Assign 25 to FBD2
+} DMI_T17_MEMORY_TYPE;
+
+/// DMI Type 17 offset 13h - Type Detail
+typedef struct {
+ OUT UINT16 Reserved1:1; ///< Reserved
+ OUT UINT16 Other:1; ///< Other
+ OUT UINT16 Unknown:1; ///< Unknown
+ OUT UINT16 FastPaged:1; ///< Fast-Paged
+ OUT UINT16 StaticColumn:1; ///< Static column
+ OUT UINT16 PseudoStatic:1; ///< Pseudo-static
+ OUT UINT16 Rambus:1; ///< RAMBUS
+ OUT UINT16 Synchronous:1; ///< Synchronous
+ OUT UINT16 Cmos:1; ///< CMOS
+ OUT UINT16 Edo:1; ///< EDO
+ OUT UINT16 WindowDram:1; ///< Window DRAM
+ OUT UINT16 CacheDram:1; ///< Cache Dram
+ OUT UINT16 NonVolatile:1; ///< Non-volatile
+ OUT UINT16 Registered:1; ///< Registered (Buffered)
+ OUT UINT16 Unbuffered:1; ///< Unbuffered (Unregistered)
+ OUT UINT16 Reserved2:1; ///< Reserved
+} DMI_T17_TYPE_DETAIL;
+
+/// DMI Type 17 - Memory Device
+typedef struct {
+ OUT UINT16 Handle; ///< The temporary handle, or instance number, associated with the structure
+ OUT UINT16 TotalWidth; ///< Total Width, in bits, of this memory device, including any check or error-correction bits.
+ OUT UINT16 DataWidth; ///< Data Width, in bits, of this memory device.
+ OUT UINT16 MemorySize; ///< The size of the memory device.
+ OUT DMI_T17_FORM_FACTOR FormFactor; ///< The implementation form factor for this memory device.
+ OUT UINT8 DeviceSet; ///< Identifies when the Memory Device is one of a set of
+ ///< Memory Devices that must be populated with all devices of
+ ///< the same type and size, and the set to which this device belongs.
+ OUT CHAR8 DeviceLocator[8]; ///< The string number of the string that identifies the physically labeled socket or board position where the memory device is located.
+ OUT CHAR8 BankLocator[10]; ///< The string number of the string that identifies the physically labeled bank where the memory device is located.
+ OUT DMI_T17_MEMORY_TYPE MemoryType; ///< The type of memory used in this device.
+ OUT DMI_T17_TYPE_DETAIL TypeDetail; ///< Additional detail on the memory device type
+ OUT UINT16 Speed; ///< Identifies the speed of the device, in megahertz (MHz).
+ OUT UINT64 ManufacturerIdCode; ///< Manufacturer ID code.
+ OUT CHAR8 SerialNumber[9]; ///< Serial Number.
+ OUT CHAR8 PartNumber[19]; ///< Part Number.
+ OUT UINT8 Attributes; ///< Bits 7-4: Reserved, Bits 3-0: rank.
+ OUT UINT32 ExtSize; ///< Extended Size.
+ OUT UINT16 ConfigSpeed; ///< Configured memory clock speed
+ OUT UINT16 MinimumVoltage; ///< Minimum operating voltage for this device, in millivolts
+ OUT UINT16 MaximumVoltage; ///< Maximum operating voltage for this device, in millivolts
+ OUT UINT16 ConfiguredVoltage; ///< Configured voltage for this device, in millivolts
+} TYPE17_DMI_INFO;
+
+/// Memory DMI Type 17 - for memory use
+typedef struct {
+ OUT UINT8 Socket:3; ///< Socket ID
+ OUT UINT8 Channel:2; ///< Channel ID
+ OUT UINT8 Dimm:2; ///< DIMM ID
+ OUT UINT8 DimmPresent:1; ///< Dimm Present
+ OUT UINT16 Handle; ///< The temporary handle, or instance number, associated with the structure
+ OUT UINT16 TotalWidth; ///< Total Width, in bits, of this memory device, including any check or error-correction bits.
+ OUT UINT16 DataWidth; ///< Data Width, in bits, of this memory device.
+ OUT UINT16 MemorySize; ///< The size of the memory device.
+ OUT DMI_T17_FORM_FACTOR FormFactor; ///< The implementation form factor for this memory device.
+ OUT UINT8 DeviceLocator; ///< The string number of the string that identifies the physically labeled socket or board position where the memory device is located.
+ OUT UINT8 BankLocator; ///< The string number of the string that identifies the physically labeled bank where the memory device is located.
+ OUT UINT16 Speed; ///< Identifies the speed of the device, in megahertz (MHz).
+ OUT UINT64 ManufacturerIdCode; ///< Manufacturer ID code.
+ OUT UINT8 SerialNumber[4]; ///< Serial Number.
+ OUT UINT8 PartNumber[18]; ///< Part Number.
+ OUT UINT8 Attributes; ///< Bits 7-4: Reserved, Bits 3-0: rank.
+ OUT UINT32 ExtSize; ///< Extended Size.
+ OUT UINT16 ConfigSpeed; ///< Configured memory clock speed
+ OUT UINT16 MinimumVoltage; ///< Minimum operating voltage for this device, in millivolts
+ OUT UINT16 MaximumVoltage; ///< Maximum operating voltage for this device, in millivolts
+ OUT UINT16 ConfiguredVoltage; ///< Configured voltage for this device, in millivolts
+} MEM_DMI_PHYSICAL_DIMM_INFO;
+
+/// Memory DMI Type 20 - for memory use
+typedef struct {
+ OUT UINT8 Socket:3; ///< Socket ID
+ OUT UINT8 Channel:2; ///< Channel ID
+ OUT UINT8 Dimm:2; ///< DIMM ID
+ OUT UINT8 DimmPresent:1; ///< Dimm Present
+ OUT UINT32 StartingAddr; ///< The physical address, in kilobytes, of a range
+ ///< of memory mapped to the referenced Memory Device.
+ OUT UINT32 EndingAddr; ///< The handle, or instance number, associated with
+ ///< the Memory Device structure to which this address
+ ///< range is mapped.
+ OUT UINT16 MemoryDeviceHandle; ///< The handle, or instance number, associated with
+ ///< the Memory Device structure to which this address
+ ///< range is mapped.
+ OUT UINT64 ExtStartingAddr; ///< The physical address, in bytes, of a range of
+ ///< memory mapped to the referenced Memory Device.
+ OUT UINT64 ExtEndingAddr; ///< The physical ending address, in bytes, of the last of
+ ///< a range of addresses mapped to the referenced Memory Device.
+} MEM_DMI_LOGICAL_DIMM_INFO;
+
+/// DMI Type 19 - Memory Array Mapped Address
+typedef struct {
+ OUT UINT32 StartingAddr; ///< The physical address, in kilobytes,
+ ///< of a range of memory mapped to the
+ ///< specified physical memory array.
+ OUT UINT32 EndingAddr; ///< The physical ending address of the
+ ///< last kilobyte of a range of addresses
+ ///< mapped to the specified physical memory array.
+ OUT UINT16 MemoryArrayHandle; ///< The handle, or instance number, associated
+ ///< with the physical memory array to which this
+ ///< address range is mapped.
+ OUT UINT8 PartitionWidth; ///< Identifies the number of memory devices that
+ ///< form a single row of memory for the address
+ ///< partition defined by this structure.
+ OUT UINT64 ExtStartingAddr; ///< The physical address, in bytes, of a range of
+ ///< memory mapped to the specified Physical Memory Array.
+ OUT UINT64 ExtEndingAddr; ///< The physical address, in bytes, of a range of
+ ///< memory mapped to the specified Physical Memory Array.
+} TYPE19_DMI_INFO;
+
+///DMI Type 20 - Memory Device Mapped Address
+typedef struct {
+ OUT UINT32 StartingAddr; ///< The physical address, in kilobytes, of a range
+ ///< of memory mapped to the referenced Memory Device.
+ OUT UINT32 EndingAddr; ///< The handle, or instance number, associated with
+ ///< the Memory Device structure to which this address
+ ///< range is mapped.
+ OUT UINT16 MemoryDeviceHandle; ///< The handle, or instance number, associated with
+ ///< the Memory Device structure to which this address
+ ///< range is mapped.
+ OUT UINT16 MemoryArrayMappedAddressHandle; ///< The handle, or instance number, associated
+ ///< with the Memory Array Mapped Address structure to
+ ///< which this device address range is mapped.
+ OUT UINT8 PartitionRowPosition; ///< Identifies the position of the referenced Memory
+ ///< Device in a row of the address partition.
+ OUT UINT8 InterleavePosition; ///< The position of the referenced Memory Device in
+ ///< an interleave.
+ OUT UINT8 InterleavedDataDepth; ///< The maximum number of consecutive rows from the
+ ///< referenced Memory Device that are accessed in a
+ ///< single interleaved transfer.
+ OUT UINT64 ExtStartingAddr; ///< The physical address, in bytes, of a range of
+ ///< memory mapped to the referenced Memory Device.
+ OUT UINT64 ExtEndingAddr; ///< The physical ending address, in bytes, of the last of
+ ///< a range of addresses mapped to the referenced Memory Device.
+} TYPE20_DMI_INFO;
+
+/// Collection of pointers to the DMI records
+typedef struct {
+ OUT TYPE4_DMI_INFO T4[MAX_SOCKETS_SUPPORTED]; ///< Type 4 struc
+ OUT TYPE7_DMI_INFO T7L1[MAX_SOCKETS_SUPPORTED]; ///< Type 7 struc 1
+ OUT TYPE7_DMI_INFO T7L2[MAX_SOCKETS_SUPPORTED]; ///< Type 7 struc 2
+ OUT TYPE7_DMI_INFO T7L3[MAX_SOCKETS_SUPPORTED]; ///< Type 7 struc 3
+ OUT TYPE16_DMI_INFO T16; ///< Type 16 struc
+ OUT TYPE17_DMI_INFO T17[MAX_SOCKETS_SUPPORTED][MAX_CHANNELS_PER_SOCKET][MAX_DIMMS_PER_CHANNEL]; ///< Type 17 struc
+ OUT TYPE19_DMI_INFO T19; ///< Type 19 struc
+ OUT TYPE20_DMI_INFO T20[MAX_SOCKETS_SUPPORTED][MAX_CHANNELS_PER_SOCKET][MAX_DIMMS_PER_CHANNEL]; ///< Type 20 struc
+} DMI_INFO;
+
+/**********************************************************************
+ * Interface call: AllocateExecutionCache
+ **********************************************************************/
+#define MAX_CACHE_REGIONS 3
+
+/// AllocateExecutionCache sub param structure for cached memory region
+typedef struct {
+ IN OUT UINT32 ExeCacheStartAddr; ///< Start address
+ IN OUT UINT32 ExeCacheSize; ///< Size
+} EXECUTION_CACHE_REGION;
+
+/**********************************************************************
+ * Interface call: AmdGetAvailableExeCacheSize
+ **********************************************************************/
+/// Get available Cache remain
+typedef struct {
+ IN OUT AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header
+ OUT UINT32 AvailableExeCacheSize; ///< Remain size
+} AMD_GET_EXE_SIZE_PARAMS;
+
+AGESA_STATUS
+AmdGetAvailableExeCacheSize (
+ IN OUT AMD_GET_EXE_SIZE_PARAMS *AmdGetExeSizeParams
+ );
+
+/// Selection type for core leveling
+typedef enum {
+ CORE_LEVEL_LOWEST, ///< Level to lowest common denominator
+ CORE_LEVEL_TWO, ///< Level to 2 cores
+ CORE_LEVEL_POWER_OF_TWO, ///< Level to 1,2,4 or 8
+ CORE_LEVEL_NONE, ///< Do no leveling
+ CORE_LEVEL_COMPUTE_UNIT, ///< Level cores to one core per compute unit
+ CORE_LEVEL_COMPUTE_UNIT_TWO, ///< Level cores to two cores per compute unit
+ CORE_LEVEL_COMPUTE_UNIT_THREE, ///< Level cores to three cores per compute unit
+ CORE_LEVEL_ONE, ///< Level to 1 core
+ CORE_LEVEL_THREE, ///< Level to 3 cores
+ CORE_LEVEL_FOUR, ///< Level to 4 cores
+ CORE_LEVEL_FIVE, ///< Level to 5 cores
+ CORE_LEVEL_SIX, ///< Level to 6 cores
+ CORE_LEVEL_SEVEN, ///< Level to 7 cores
+ CORE_LEVEL_EIGHT, ///< Level to 8 cores
+ CORE_LEVEL_NINE, ///< Level to 9 cores
+ CORE_LEVEL_TEN, ///< Level to 10 cores
+ CORE_LEVEL_ELEVEN, ///< Level to 11 cores
+ CORE_LEVEL_TWELVE, ///< Level to 12 cores
+ CORE_LEVEL_THIRTEEN, ///< Level to 13 cores
+ CORE_LEVEL_FOURTEEN, ///< Level to 14 cores
+ CORE_LEVEL_FIFTEEN, ///< Level to 15 cores
+ CoreLevelModeMax ///< Used for bounds checking
+} CORE_LEVELING_TYPE;
+
+
+
+
+
+/************************************************************************
+ *
+ * AGESA Basic Level interface structure definition and function prototypes
+ *
+ ***********************************************************************/
+
+/**********************************************************************
+ * Interface call: AmdCreateStruct
+ **********************************************************************/
+AGESA_STATUS
+AmdCreateStruct (
+ IN OUT AMD_INTERFACE_PARAMS *InterfaceParams
+ );
+
+/**********************************************************************
+ * Interface call: AmdReleaseStruct
+ **********************************************************************/
+AGESA_STATUS
+AmdReleaseStruct (
+ IN OUT AMD_INTERFACE_PARAMS *InterfaceParams
+ );
+
+/**********************************************************************
+ * Interface call: AmdInitReset
+ **********************************************************************/
+/// AmdInitReset param structure
+typedef struct {
+ IN AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header
+ IN EXECUTION_CACHE_REGION CacheRegion[3]; ///< The cached memory region
+ IN FCH_RESET_INTERFACE FchInterface; ///< Interface for FCH configuration
+} AMD_RESET_PARAMS;
+
+AGESA_STATUS
+AmdInitReset (
+ IN OUT AMD_RESET_PARAMS *ResetParams
+ );
+
+
+/**********************************************************************
+ * Interface call: AmdInitEarly
+ **********************************************************************/
+/// InitEarly param structure
+///
+/// Provide defaults or customizations to each service performed in AmdInitEarly.
+///
+typedef struct {
+ IN OUT AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header
+ IN EXECUTION_CACHE_REGION CacheRegion[3]; ///< Execution Map Interface
+ IN PLATFORM_CONFIGURATION PlatformConfig; ///< platform operational characteristics.
+ IN GNB_CONFIGURATION GnbConfig; ///< GNB configuration
+} AMD_EARLY_PARAMS;
+
+AGESA_STATUS
+AmdInitEarly (
+ IN OUT AMD_EARLY_PARAMS *EarlyParams
+ );
+
+
+/**********************************************************************
+ * Interface call: AmdInitPost
+ **********************************************************************/
+/// AmdInitPost param structure
+typedef struct {
+ IN OUT AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header
+ IN PLATFORM_CONFIGURATION PlatformConfig; ///< platform operational characteristics.
+ IN MEM_PARAMETER_STRUCT MemConfig; ///< Memory post param
+ IN GNB_POST_CONFIGURATION GnbPostConfig; ///< GNB post param
+} AMD_POST_PARAMS;
+
+AGESA_STATUS
+AmdInitPost (
+ IN OUT AMD_POST_PARAMS *PostParams ///< Amd Cpu init param
+ );
+
+
+/**********************************************************************
+ * Interface call: AmdInitEnv
+ **********************************************************************/
+/// AmdInitEnv param structure
+typedef struct {
+ IN OUT AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header
+ IN PLATFORM_CONFIGURATION PlatformConfig; ///< platform operational characteristics.
+ IN GNB_ENV_CONFIGURATION GnbEnvConfiguration; ///< GNB configuration
+ IN FCH_INTERFACE FchInterface; ///< FCH configuration
+} AMD_ENV_PARAMS;
+
+AGESA_STATUS
+AmdInitEnv (
+ IN OUT AMD_ENV_PARAMS *EnvParams
+ );
+
+
+/**********************************************************************
+ * Interface call: AmdInitMid
+ **********************************************************************/
+/// AmdInitMid param structure
+typedef struct {
+ IN OUT AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header
+ IN PLATFORM_CONFIGURATION PlatformConfig; ///< platform operational characteristics.
+ IN GNB_MID_CONFIGURATION GnbMidConfiguration; ///< GNB configuration
+ IN FCH_INTERFACE FchInterface; ///< FCH configuration
+} AMD_MID_PARAMS;
+
+AGESA_STATUS
+AmdInitMid (
+ IN OUT AMD_MID_PARAMS *MidParams
+ );
+
+
+/**********************************************************************
+ * Interface call: AmdInitLate
+ **********************************************************************/
+/// AmdInitLate param structure
+typedef struct {
+ IN OUT AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header
+ IN PLATFORM_CONFIGURATION PlatformConfig; ///< platform operational characteristics.
+ IN IOMMU_EXCLUSION_RANGE_DESCRIPTOR *IvrsExclusionRangeList; ///< Pointer to array of exclusion ranges
+ OUT DMI_INFO *DmiTable; ///< DMI Interface
+ OUT VOID *AcpiPState; ///< Acpi Pstate SSDT Table
+ OUT VOID *AcpiWheaMce; ///< WHEA MCE Table
+ OUT VOID *AcpiWheaCmc; ///< WHEA CMC Table
+ OUT VOID *AcpiAlib; ///< ACPI SSDT table with ALIB implementation
+ OUT VOID *AcpiIvrs; ///< IOMMU ACPI IVRS(I/O Virtualization Reporting Structure) table
+ OUT VOID *AcpiCrat; ///< Component Resource Affinity Table table
+ OUT VOID *AcpiCdit; ///< Component Locality Distance Information table
+ IN GNB_LATE_CONFIGURATION GnbLateConfiguration; ///< GNB configuration
+} AMD_LATE_PARAMS;
+
+AGESA_STATUS
+AmdInitLate (
+ IN OUT AMD_LATE_PARAMS *LateParams
+ );
+
+/**********************************************************************
+ * Interface call: AmdInitRecovery
+ **********************************************************************/
+/// CPU Recovery Parameters
+typedef struct {
+ IN OUT AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header
+ IN PLATFORM_CONFIGURATION PlatformConfig; ///< platform operational characteristics.
+} AMD_CPU_RECOVERY_PARAMS;
+
+/// AmdInitRecovery param structure
+typedef struct {
+ IN OUT AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header
+ IN MEM_PARAMETER_STRUCT MemConfig; ///< Memory post param
+ IN EXECUTION_CACHE_REGION CacheRegion[3]; ///< The cached memory region. And the max cache region is 3
+ IN AMD_CPU_RECOVERY_PARAMS CpuRecoveryParams; ///< Params for CPU related recovery init.
+} AMD_RECOVERY_PARAMS;
+
+AGESA_STATUS
+AmdInitRecovery (
+ IN OUT AMD_RECOVERY_PARAMS *RecoveryParams
+ );
+
+/**********************************************************************
+ * Interface call: AmdInitResume
+ **********************************************************************/
+/// AmdInitResume param structure
+typedef struct {
+ IN OUT AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header
+ IN PLATFORM_CONFIGURATION PlatformConfig; ///< Platform operational characteristics
+ IN S3_DATA_BLOCK S3DataBlock; ///< Save state data
+} AMD_RESUME_PARAMS;
+
+AGESA_STATUS
+AmdInitResume (
+ IN AMD_RESUME_PARAMS *ResumeParams
+ );
+
+
+/**********************************************************************
+ * Interface call: AmdS3LateRestore
+ **********************************************************************/
+/// AmdS3LateRestore param structure
+typedef struct {
+ IN OUT AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header
+ IN PLATFORM_CONFIGURATION PlatformConfig; ///< Platform operational characteristics.
+ IN S3_DATA_BLOCK S3DataBlock; ///< Save state data
+} AMD_S3LATE_PARAMS;
+
+AGESA_STATUS
+AmdS3LateRestore (
+ IN OUT AMD_S3LATE_PARAMS *S3LateParams
+ );
+
+
+/**********************************************************************
+ * Interface call: AmdS3FinalRestore
+ **********************************************************************/
+/// AmdS3FinalRestore param structure
+typedef struct {
+ IN OUT AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header
+ IN PLATFORM_CONFIGURATION PlatformConfig; ///< Platform operational characteristics.
+ IN S3_DATA_BLOCK S3DataBlock; ///< Save state data
+} AMD_S3FINAL_PARAMS;
+
+AGESA_STATUS
+AmdS3FinalRestore (
+ IN OUT AMD_S3FINAL_PARAMS *S3FinalParams
+ );
+
+/**********************************************************************
+ * Interface call: AmdInitRtb
+ **********************************************************************/
+/// AmdInitRtb param structure
+typedef struct {
+ IN OUT AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header
+ IN PLATFORM_CONFIGURATION PlatformConfig; ///< platform operational characteristics.
+ OUT S3_DATA_BLOCK S3DataBlock; ///< Save state data
+ IN FCH_INTERFACE FchInterface; ///< FCH configuration
+} AMD_RTB_PARAMS;
+
+AGESA_STATUS
+AmdInitRtb (
+ IN OUT AMD_RTB_PARAMS *AmdInitRtbParams
+ );
+
+
+/**********************************************************************
+ * Interface call: AmdLateRunApTask
+ **********************************************************************/
+/**
+ * Entry point for AP tasking.
+ */
+AGESA_STATUS
+AmdLateRunApTask (
+ IN AP_EXE_PARAMS *AmdApExeParams
+);
+
+//
+// General Services API
+//
+
+/**********************************************************************
+ * Interface service call: AmdGetApicId
+ **********************************************************************/
+/// Request the APIC ID of a particular core.
+
+typedef struct {
+ IN AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header
+ IN UINT8 Socket; ///< The Core's Socket.
+ IN UINT8 Core; ///< The Core id.
+ OUT BOOLEAN IsPresent; ///< The Core is present, and ApicAddress is valid.
+ OUT UINT8 ApicAddress; ///< The Core's APIC ID.
+} AMD_APIC_PARAMS;
+
+/**
+ * Get a specified Core's APIC ID.
+ */
+AGESA_STATUS
+AmdGetApicId (
+ IN OUT AMD_APIC_PARAMS *AmdParamApic
+);
+
+/**********************************************************************
+ * Interface service call: AmdGetPciAddress
+ **********************************************************************/
+/// Request the PCI Address of a Processor Module (that is, its Northbridge)
+
+typedef struct {
+ IN AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header
+ IN UINT8 Socket; ///< The Processor's socket
+ IN UINT8 Module; ///< The Module in that Processor
+ OUT BOOLEAN IsPresent; ///< The Core is present, and PciAddress is valid.
+ OUT PCI_ADDR PciAddress; ///< The Processor's PCI Config Space address (Function 0, Register 0)
+} AMD_GET_PCI_PARAMS;
+
+/**
+ * Get Processor Module's PCI Config Space address.
+ */
+AGESA_STATUS
+AmdGetPciAddress (
+ IN OUT AMD_GET_PCI_PARAMS *AmdParamGetPci
+);
+
+/**********************************************************************
+ * Interface service call: AmdIdentifyCore
+ **********************************************************************/
+/// Request the identity (Socket, Module, Core) of the current Processor Core
+
+typedef struct {
+ IN AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header
+ OUT UINT8 Socket; ///< The current Core's Socket
+ OUT UINT8 Module; ///< The current Core's Processor Module
+ OUT UINT8 Core; ///< The current Core's core id.
+} AMD_IDENTIFY_PARAMS;
+
+/**
+ * "Who am I" for the current running core.
+ */
+AGESA_STATUS
+AmdIdentifyCore (
+ IN OUT AMD_IDENTIFY_PARAMS *AmdParamIdentify
+);
+
+/**********************************************************************
+ * Interface service call: AmdReadEventLog
+ **********************************************************************/
+/// An Event Log Entry.
+typedef struct {
+ IN AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header
+ OUT UINT32 EventClass; ///< The severity of this event, matches AGESA_STATUS.
+ OUT UINT32 EventInfo; ///< The unique event identifier, zero means "no event".
+ OUT UINT32 DataParam1; ///< Data specific to the Event.
+ OUT UINT32 DataParam2; ///< Data specific to the Event.
+ OUT UINT32 DataParam3; ///< Data specific to the Event.
+ OUT UINT32 DataParam4; ///< Data specific to the Event.
+} EVENT_PARAMS;
+
+/**
+ * Read an Event from the Event Log.
+ */
+AGESA_STATUS
+AmdReadEventLog (
+ IN EVENT_PARAMS *Event
+);
+
+/**********************************************************************
+ * Interface service call: AmdIdentifyDimm
+ **********************************************************************/
+/// Request the identity of dimm from system address
+
+typedef struct {
+ IN OUT AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header
+ IN UINT64 MemoryAddress; ///< System Address that needs to be translated to dimm identification.
+ OUT UINT8 SocketId; ///< The socket on which the targeted address locates.
+ OUT UINT8 MemChannelId; ///< The channel on which the targeted address locates.
+ OUT UINT8 DimmId; ///< The dimm on which the targeted address locates.
+ OUT UINT8 ChipSelect; ///< The chip select on which the targeted address locates.
+ OUT UINT8 Bank; ///< The Bank for which the error address resides
+ OUT UINT32 Row; ///< The Row for which the error address resides
+ OUT UINT16 Column; ///< The Column for which the error address resides
+} AMD_IDENTIFY_DIMM;
+
+/**
+ * Get the dimm identification for the address.
+ */
+AGESA_STATUS
+AmdIdentifyDimm (
+ IN OUT AMD_IDENTIFY_DIMM *AmdDimmIdentify
+);
+
+AGESA_STATUS
+AmdIdsRunApTaskLate (
+ IN AP_EXE_PARAMS *AmdApExeParams
+ );
+
+/// Request the 2D Data Eye Training Data
+#define RD_DATAEYE 0
+#define WR_DATAEYE 1
+
+/**********************************************************************
+ * Interface service call: AmdGet2DDataEye
+ **********************************************************************/
+/// Request the training data eye on Socket, Channel, Dimm.
+
+typedef struct _AMD_GET_DATAEYE {
+ IN OUT AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header
+ IN OUT AMD_POST_PARAMS *PostParamsPtr; ///< Pointer to AMD_POST_PARAMS
+ IN UINT8 SocketId; ///< The socket number to get the 2D data eye
+ IN UINT8 MemChannelId; ///< The channel number to get the 2D data eye
+ IN UINT8 DimmId; ///< The dimm number to get the 2D data eye
+ IN UINT8 DataEyeType; ///< Get the 2D data eye on read or write training
+ OUT UINT8* DataEyeBuffer; ///< The buffer to stores the 2D data eye
+} AMD_GET_DATAEYE;
+
+AGESA_STATUS
+AmdGet2DDataEye (
+ IN OUT AMD_GET_DATAEYE *AmdGetDataEye
+ );
+
+#define AGESA_IDS_DFT_VAL 0xFFFF ///< Default value of every uninitlized NV item, the action for it will be ignored
+#define AGESA_IDS_NV_END 0xFFFF ///< Flag specify end of option structure
+/// WARNING: Don't change the comment below, it used as signature for script
+/// AGESA IDS NV ID Definitions
+typedef enum {
+ AGESA_IDS_EXT_ID_START = 0x0000,///< 0x0000 specify the start of external NV id
+
+ AGESA_IDS_NV_UCODE, ///< 0x0001 Enable or disable microcode patching
+
+ AGESA_IDS_NV_TARGET_PSTATE, ///< 0x0002 Set the P-state required to be activated
+ AGESA_IDS_NV_POSTPSTATE, ///< 0x0003 Set the P-state required to be activated through POST
+
+ AGESA_IDS_NV_BANK_INTERLEAVE, ///< 0x0004 Enable or disable Bank Interleave
+ AGESA_IDS_NV_CHANNEL_INTERLEAVE, ///< 0x0005 Enable or disable Channel Interleave
+ AGESA_IDS_NV_NODE_INTERLEAVE, ///< 0x0006 Enable or disable Node Interleave
+ AGESA_IDS_NV_MEMHOLE, ///< 0x0007 Enables or disable memory hole
+
+ AGESA_IDS_NV_SCRUB_REDIRECTION, ///< 0x0008 Enable or disable a write to dram with corrected data
+ AGESA_IDS_NV_DRAM_SCRUB, ///< 0x0009 Set the rate of background scrubbing for DRAM
+ AGESA_IDS_NV_DCACHE_SCRUB, ///< 0x000A Set the rate of background scrubbing for the DCache.
+ AGESA_IDS_NV_L2_SCRUB, ///< 0x000B Set the rate of background scrubbing for the L2 cache
+ AGESA_IDS_NV_L3_SCRUB, ///< 0x000C Set the rate of background scrubbing for the L3 cache
+ AGESA_IDS_NV_ICACHE_SCRUB, ///< 0x000D Set the rate of background scrubbing for the Icache
+ AGESA_IDS_NV_SYNC_ON_ECC_ERROR, ///< 0x000E Enable or disable the sync flood on un-correctable ECC error
+ AGESA_IDS_NV_ECC_SYMBOL_SIZE, ///< 0x000F Set ECC symbol size
+
+ AGESA_IDS_NV_ALL_MEMCLKS, ///< 0x0010 Enable or disable all memory clocks enable
+ AGESA_IDS_NV_DCT_GANGING_MODE, ///< 0x0011 Set the Ganged mode
+ AGESA_IDS_NV_DRAM_BURST_LENGTH32, ///< 0x0012 Set the DRAM Burst Length 32
+ AGESA_IDS_NV_MEMORY_POWER_DOWN, ///< 0x0013 Enable or disable Memory power down mode
+ AGESA_IDS_NV_MEMORY_POWER_DOWN_MODE, ///< 0x0014 Set the Memory power down mode
+ AGESA_IDS_NV_DLL_SHUT_DOWN, ///< 0x0015 Enable or disable DLLShutdown
+ AGESA_IDS_NV_ONLINE_SPARE, ///< 0x0016 Enable or disable the Dram controller to designate a DIMM bank as a spare for logical swap
+
+ AGESA_IDS_NV_HDTOUT, ///< 0x0017 Enable or disable HDTOUT feature
+
+ AGESA_IDS_NV_GNBHDAUDIOEN, ///< 0x0018 Enable or disable GNB HD Audio
+
+ AGESA_IDS_NV_CPB_EN, ///< 0x0019 Core Performance Boost
+
+ AGESA_IDS_NV_HTC_EN, ///< 0x001A HTC Enable
+ AGESA_IDS_NV_HTC_OVERRIDE, ///< 0x001B HTC Override
+ AGESA_IDS_NV_HTC_PSTATE_LIMIT, ///< 0x001C HTC P-state limit select
+ AGESA_IDS_NV_HTC_TEMP_HYS, ///< 0x001D HTC Temperature Hysteresis
+ AGESA_IDS_NV_HTC_ACT_TEMP, ///< 0x001E HTC Activation Temp
+
+ AGESA_IDS_NV_DRAMCON, ///< 0x001F Specify the mode for controller initialization
+ AGESA_IDS_NV_ALL_CKE, ///< 0x0020 Enable or disable all CKE
+ AGESA_IDS_NV_ALL_CS, ///< 0x0021 Enable or disable all CS
+ AGESA_IDS_NV_MSR_DE_CFG_BIT16, ///< 0x0022 Workaround GCC/C000005 issue for XV Core on CZ A0
+ AGESA_IDS_EXT_ID_END, ///< 0x0023 specify the end of external NV ID
+} IDS_EX_NV_ID;
+
+
+#define IDS_NUM_EXT_NV_ITEM (AGESA_IDS_EXT_ID_END - AGESA_IDS_EXT_ID_START + 1)
+
+
+#endif // _AGESA_H_
diff --git a/src/vendorcode/amd/pi/00660F01/AMD.h b/src/vendorcode/amd/pi/00660F01/AMD.h
new file mode 100644
index 0000000..aa68204
--- /dev/null
+++ b/src/vendorcode/amd/pi/00660F01/AMD.h
@@ -0,0 +1,476 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Agesa structures and definitions
+ *
+ * Contains AMD AGESA core interface
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: Include
+ * @e \$Revision: 309090 $ @e \$Date: 2014-12-09 12:28:05 -0600 (Tue, 09 Dec 2014) $
+ */
+ /*****************************************************************************
+ *
+ * Copyright (c) 2008 - 2015, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ***************************************************************************/
+
+
+#ifndef _AMD_H_
+#define _AMD_H_
+
+#define Int16FromChar(a,b) (UINT16)((a) << 0 | (b) << 8)
+#define Int32FromChar(a,b,c,d) (UINT32)((a) << 0 | (b) << 8 | (c) << 16 | (d) << 24)
+#define Int64FromChar(a,b,c,d,e,f,g,h) ((UINT64)(Int32FromChar(a,b,c,d)<<32) | (UINT64)Int32FromChar(e,f,g,h))
+
+#define AGESA_REVISION "Arch2008"
+#define AGESA_ID {'A', 'G', 'E', 'S', 'A', 0x00, 0x00, 0x00}
+
+//
+//
+// AGESA Types and Definitions
+//
+//
+#define LAST_ENTRY 0xFFFFFFFFul
+#define IMAGE_SIGNATURE Int32FromChar ('$', 'A', 'M', 'D')
+#define MODULE_SIGNATURE Int32FromChar ('$', 'M', 'O', 'D')
+#define IOCF8 0xCF8
+#define IOCFC 0xCFC
+
+/// The return status for all AGESA public services.
+///
+/// Services return the most severe status of any logged event. Status other than SUCCESS, UNSUPPORTED, and BOUNDS_CHK
+/// will have log entries with more detail.
+///
+typedef enum {
+ AGESA_SUCCESS = 0, ///< The service completed normally. Info may be logged.
+ AGESA_UNSUPPORTED, ///< The dispatcher or create struct had an unimplemented function requested.
+ ///< Not logged.
+ AGESA_BOUNDS_CHK, ///< A dynamic parameter was out of range and the service was not provided.
+ ///< Example, memory address not installed, heap buffer handle not found.
+ ///< Not Logged.
+ // AGESA_STATUS of greater severity (the ones below this line), always have a log entry available.
+ AGESA_ALERT, ///< An observed condition, but no loss of function. See Log.
+ AGESA_WARNING, ///< Possible or minor loss of function. See Log.
+ AGESA_ERROR, ///< Significant loss of function, boot may be possible. See Log.
+ AGESA_CRITICAL, ///< Continue boot only to notify user. See Log.
+ AGESA_FATAL, ///< Halt booting. See Log, however Fatal errors pertaining to heap problems
+ ///< may not be able to reliably produce log events.
+ AgesaStatusMax ///< Not a status, for limit checking.
+} AGESA_STATUS;
+
+/// For checking whether a status is at or above the mandatory log level.
+#define AGESA_STATUS_LOG_LEVEL AGESA_ALERT
+
+/**
+ * Callout method to the host environment.
+ *
+ * Callout using a dispatch with appropriate thunk layer, which is determined by the host environment.
+ *
+ * @param[in] Function The specific callout function being invoked.
+ * @param[in] FcnData Function specific data item.
+ * @param[in,out] ConfigPtr Reference to Callout params.
+ */
+typedef AGESA_STATUS (*CALLOUT_ENTRY) (
+ IN UINT32 Function,
+ IN UINTN FcnData,
+ IN OUT VOID *ConfigPtr
+ );
+
+typedef AGESA_STATUS (*IMAGE_ENTRY) (VOID *ConfigPtr);
+typedef AGESA_STATUS (*MODULE_ENTRY) (VOID *ConfigPtr);
+
+///This allocation type is used by the AmdCreateStruct entry point
+typedef enum {
+ PreMemHeap = 0, ///< Create heap in cache.
+ PostMemDram, ///< Create heap in memory.
+ ByHost ///< Create heap by Host.
+} ALLOCATION_METHOD;
+
+/// These width descriptors are used by the library function, and others, to specify the data size
+typedef enum ACCESS_WIDTH {
+ AccessWidthNone = 0, ///< dummy access width
+ AccessWidth8 = 1, ///< Access width is 8 bits.
+ AccessWidth16, ///< Access width is 16 bits.
+ AccessWidth32, ///< Access width is 32 bits.
+ AccessWidth64, ///< Access width is 64 bits.
+
+ AccessS3SaveWidth8 = 0x81, ///< Save 8 bits data.
+ AccessS3SaveWidth16, ///< Save 16 bits data.
+ AccessS3SaveWidth32, ///< Save 32 bits data.
+ AccessS3SaveWidth64, ///< Save 64 bits data.
+} ACCESS_WIDTH;
+
+/// AGESA struct name
+typedef enum {
+ // AGESA BASIC FUNCTIONS
+ AMD_INIT_RECOVERY = 0x00021000, ///< AmdInitRecovery entry point handle
+ AMD_CREATE_STRUCT = 0x00022000, ///< AmdCreateStruct handle
+ AMD_INIT_EARLY = 0x00023000, ///< AmdInitEarly entry point handle
+ AMD_INIT_ENV = 0x00024000, ///< AmdInitEnv entry point handle
+ AMD_INIT_LATE = 0x00025000, ///< AmdInitLate entry point handle
+ AMD_INIT_MID = 0x00026000, ///< AmdInitMid entry point handle
+ AMD_INIT_POST = 0x00027000, ///< AmdInitPost entry point handle
+ AMD_INIT_RESET = 0x00028000, ///< AmdInitReset entry point handle
+ AMD_INIT_RESUME = 0x00029000, ///< AmdInitResume entry point handle
+ AMD_RELEASE_STRUCT = 0x0002A000, ///< AmdReleaseStruct handle
+ AMD_S3LATE_RESTORE = 0x0002B000, ///< AmdS3LateRestore entry point handle
+ AMD_GET_APIC_ID = 0x0002C000, ///< AmdGetApicId entry point handle
+ AMD_GET_PCI_ADDRESS = 0x0002D000, ///< AmdGetPciAddress entry point handle
+ AMD_IDENTIFY_CORE = 0x0002E000, ///< AmdIdentifyCore general service handle
+ AMD_READ_EVENT_LOG = 0x0002F000, ///< AmdReadEventLog general service handle
+ AMD_GET_EXECACHE_SIZE = 0x00030000, ///< AmdGetAvailableExeCacheSize general service handle
+ AMD_LATE_RUN_AP_TASK = 0x00031000, ///< AmdLateRunApTask entry point handle
+ AMD_IDENTIFY_DIMMS = 0x00032000, ///< AmdIdentifyDimm general service handle
+ AMD_GET_2D_DATA_EYE = 0x00033000, ///< AmdGet2DDataEye general service handle
+ AMD_S3FINAL_RESTORE = 0x00034000, ///< AmdS3FinalRestore entry point handle
+ AMD_INIT_RTB = 0x00035000, ///< AmdInitRtb entry point handle
+ // Add
+ AMD_HEAP_ALLOCATE_BUFFER = 0x00038000,
+ AMD_HEAP_DEALLOCATE_BUFFER = 0x00039000,
+ FCH_INIT_RESET = 0x00040000,
+ FCH_INIT_ENV = 0x00041000,
+ FCH_INIT_MID = 0x00042000,
+ FCH_INIT_LATE = 0x00043000,
+ FCH_INIT_S3_EARLY_RESTORE = 0x00044000,
+ FCH_INIT_S3_LATE_RESTORE = 0x00045000,
+ AMD_SET_VALUE = 0x00081000,
+ AMD_GET_VALUE = 0x00082000
+} AGESA_STRUCT_NAME;
+
+ /* ResetType constant values */
+#define WARM_RESET_WHENEVER 1
+#define COLD_RESET_WHENEVER 2
+#define WARM_RESET_IMMEDIATELY 3
+#define COLD_RESET_IMMEDIATELY 4
+
+
+// AGESA Structures
+
+/// The standard header for all AGESA services.
+/// For internal AGESA naming conventions, see @ref amdconfigparamname .
+typedef struct {
+ IN VOID * ImageBasePtr; ///< The AGESA Image base address.
+ IN UINT32 Func; ///< The service desired
+ IN VOID * AltImageBasePtr; ///< Alternate Image location
+ IN CALLOUT_ENTRY CalloutPtr; ///< For Callout from AGESA
+ IN UINT8 HeapStatus; ///< For heap status from boot time slide.
+ IN UINT64 HeapBasePtr; ///< Location of the heap
+ IN OUT UINT8 Reserved[7]; ///< This space is reserved for future use.
+} AMD_CONFIG_PARAMS;
+
+
+/// Create Struct Interface.
+typedef struct {
+ IN AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header
+ IN AGESA_STRUCT_NAME AgesaFunctionName; ///< The service to init
+ IN ALLOCATION_METHOD AllocationMethod; ///< How to handle buffer allocation
+ IN OUT UINT32 NewStructSize; ///< The size of the allocated data, in for ByHost, else out only.
+ IN OUT VOID *NewStructPtr; ///< The struct for the service.
+ ///< The struct to init for ByHost allocation,
+ ///< the initialized struct on return.
+} AMD_INTERFACE_PARAMS;
+
+#define FUNC_0 0 // bit-placed for PCI address creation
+#define FUNC_1 1
+#define FUNC_2 2
+#define FUNC_3 3
+#define FUNC_4 4
+#define FUNC_5 5
+#define FUNC_6 6
+#define FUNC_7 7
+
+/// AGESA Binary module header structure
+typedef struct {
+ IN UINT32 Signature; ///< Binary Signature
+ IN CHAR8 CreatorID[8]; ///< 8 characters ID
+ IN CHAR8 Version[12]; ///< 12 characters version
+ IN UINT32 ModuleInfoOffset; ///< Offset of module
+ IN UINT32 EntryPointAddress; ///< Entry address
+ IN UINT32 ImageBase; ///< Image base
+ IN UINT32 RelocTableOffset; ///< Relocate Table offset
+ IN UINT32 ImageSize; ///< Size
+ IN UINT16 Checksum; ///< Checksum
+ IN UINT8 ImageType; ///< Type
+ IN UINT8 V_Reserved; ///< Reserved
+} AMD_IMAGE_HEADER;
+/// AGESA Binary module header structure
+typedef struct _AMD_MODULE_HEADER {
+ IN UINT32 ModuleHeaderSignature; ///< Module signature
+ IN CHAR8 ModuleIdentifier[8]; ///< 8 characters ID
+ IN CHAR8 ModuleVersion[12]; ///< 12 characters version
+ IN VOID *ModuleDispatcher; ///< A pointer point to dispatcher
+ IN struct _AMD_MODULE_HEADER *NextBlock; ///< Next module header link
+} AMD_MODULE_HEADER;
+
+// AMD_CODE_HEADER Signatures.
+#define AGESA_CODE_SIGNATURE {'!', '!', '!', 'A', 'G', 'E', 'S', 'A'}
+#define CIMXNB_CODE_SIGNATURE {'!', '!', 'C', 'I', 'M', 'X', 'N', 'B'}
+#define CIMXSB_CODE_SIGNATURE {'!', '!', 'C', 'I', 'M', 'X', 'S', 'B'}
+
+/// AGESA_CODE_SIGNATURE
+typedef struct {
+ IN CHAR8 Signature[8]; ///< code header Signature
+ IN CHAR8 ComponentName[16]; ///< 16 character name of the code module
+ IN CHAR8 Version[12]; ///< 12 character version string
+ IN CHAR8 TerminatorNull; ///< null terminated string
+ IN CHAR8 VerReserved[7]; ///< reserved space
+} AMD_CODE_HEADER;
+
+/// Extended PCI address format
+typedef struct {
+ IN OUT UINT32 Register:12; ///< Register offset
+ IN OUT UINT32 Function:3; ///< Function number
+ IN OUT UINT32 Device:5; ///< Device number
+ IN OUT UINT32 Bus:8; ///< Bus number
+ IN OUT UINT32 Segment:4; ///< Segment
+} EXT_PCI_ADDR;
+
+/// Union type for PCI address
+typedef union _PCI_ADDR {
+ IN UINT32 AddressValue; ///< Formal address
+ IN EXT_PCI_ADDR Address; ///< Extended address
+} PCI_ADDR;
+
+// SBDFO - Segment Bus Device Function Offset
+// 31:28 Segment (4-bits)
+// 27:20 Bus (8-bits)
+// 19:15 Device (5-bits)
+// 14:12 Function(3-bits)
+// 11:00 Offset (12-bits)
+
+#define MAKE_SBDFO(Seg, Bus, Dev, Fun, Off) ((((UINT32) (Seg)) << 28) | (((UINT32) (Bus)) << 20) | \
+ (((UINT32)(Dev)) << 15) | (((UINT32)(Fun)) << 12) | ((UINT32)(Off)))
+#define ILLEGAL_SBDFO 0xFFFFFFFFul
+
+/// CPUID data received registers format
+typedef struct {
+ OUT UINT32 EAX_Reg; ///< CPUID instruction result in EAX
+ OUT UINT32 EBX_Reg; ///< CPUID instruction result in EBX
+ OUT UINT32 ECX_Reg; ///< CPUID instruction result in ECX
+ OUT UINT32 EDX_Reg; ///< CPUID instruction result in EDX
+} CPUID_DATA;
+
+// Topology Services definitions and macros
+#define TOPOLOGY_LIST_TERMINAL 0xFF ///< End of list.
+
+
+#ifndef BIT0
+ #define BIT0 0x0000000000000001ull
+#endif
+#ifndef BIT1
+ #define BIT1 0x0000000000000002ull
+#endif
+#ifndef BIT2
+ #define BIT2 0x0000000000000004ull
+#endif
+#ifndef BIT3
+ #define BIT3 0x0000000000000008ull
+#endif
+#ifndef BIT4
+ #define BIT4 0x0000000000000010ull
+#endif
+#ifndef BIT5
+ #define BIT5 0x0000000000000020ull
+#endif
+#ifndef BIT6
+ #define BIT6 0x0000000000000040ull
+#endif
+#ifndef BIT7
+ #define BIT7 0x0000000000000080ull
+#endif
+#ifndef BIT8
+ #define BIT8 0x0000000000000100ull
+#endif
+#ifndef BIT9
+ #define BIT9 0x0000000000000200ull
+#endif
+#ifndef BIT10
+ #define BIT10 0x0000000000000400ull
+#endif
+#ifndef BIT11
+ #define BIT11 0x0000000000000800ull
+#endif
+#ifndef BIT12
+ #define BIT12 0x0000000000001000ull
+#endif
+#ifndef BIT13
+ #define BIT13 0x0000000000002000ull
+#endif
+#ifndef BIT14
+ #define BIT14 0x0000000000004000ull
+#endif
+#ifndef BIT15
+ #define BIT15 0x0000000000008000ull
+#endif
+#ifndef BIT16
+ #define BIT16 0x0000000000010000ull
+#endif
+#ifndef BIT17
+ #define BIT17 0x0000000000020000ull
+#endif
+#ifndef BIT18
+ #define BIT18 0x0000000000040000ull
+#endif
+#ifndef BIT19
+ #define BIT19 0x0000000000080000ull
+#endif
+#ifndef BIT20
+ #define BIT20 0x0000000000100000ull
+#endif
+#ifndef BIT21
+ #define BIT21 0x0000000000200000ull
+#endif
+#ifndef BIT22
+ #define BIT22 0x0000000000400000ull
+#endif
+#ifndef BIT23
+ #define BIT23 0x0000000000800000ull
+#endif
+#ifndef BIT24
+ #define BIT24 0x0000000001000000ull
+#endif
+#ifndef BIT25
+ #define BIT25 0x0000000002000000ull
+#endif
+#ifndef BIT26
+ #define BIT26 0x0000000004000000ull
+#endif
+#ifndef BIT27
+ #define BIT27 0x0000000008000000ull
+#endif
+#ifndef BIT28
+ #define BIT28 0x0000000010000000ull
+#endif
+#ifndef BIT29
+ #define BIT29 0x0000000020000000ull
+#endif
+#ifndef BIT30
+ #define BIT30 0x0000000040000000ull
+#endif
+#ifndef BIT31
+ #define BIT31 0x0000000080000000ull
+#endif
+#ifndef BIT32
+ #define BIT32 0x0000000100000000ull
+#endif
+#ifndef BIT33
+ #define BIT33 0x0000000200000000ull
+#endif
+#ifndef BIT34
+ #define BIT34 0x0000000400000000ull
+#endif
+#ifndef BIT35
+ #define BIT35 0x0000000800000000ull
+#endif
+#ifndef BIT36
+ #define BIT36 0x0000001000000000ull
+#endif
+#ifndef BIT37
+ #define BIT37 0x0000002000000000ull
+#endif
+#ifndef BIT38
+ #define BIT38 0x0000004000000000ull
+#endif
+#ifndef BIT39
+ #define BIT39 0x0000008000000000ull
+#endif
+#ifndef BIT40
+ #define BIT40 0x0000010000000000ull
+#endif
+#ifndef BIT41
+ #define BIT41 0x0000020000000000ull
+#endif
+#ifndef BIT42
+ #define BIT42 0x0000040000000000ull
+#endif
+#ifndef BIT43
+ #define BIT43 0x0000080000000000ull
+#endif
+#ifndef BIT44
+ #define BIT44 0x0000100000000000ull
+#endif
+#ifndef BIT45
+ #define BIT45 0x0000200000000000ull
+#endif
+#ifndef BIT46
+ #define BIT46 0x0000400000000000ull
+#endif
+#ifndef BIT47
+ #define BIT47 0x0000800000000000ull
+#endif
+#ifndef BIT48
+ #define BIT48 0x0001000000000000ull
+#endif
+#ifndef BIT49
+ #define BIT49 0x0002000000000000ull
+#endif
+#ifndef BIT50
+ #define BIT50 0x0004000000000000ull
+#endif
+#ifndef BIT51
+ #define BIT51 0x0008000000000000ull
+#endif
+#ifndef BIT52
+ #define BIT52 0x0010000000000000ull
+#endif
+#ifndef BIT53
+ #define BIT53 0x0020000000000000ull
+#endif
+#ifndef BIT54
+ #define BIT54 0x0040000000000000ull
+#endif
+#ifndef BIT55
+ #define BIT55 0x0080000000000000ull
+#endif
+#ifndef BIT56
+ #define BIT56 0x0100000000000000ull
+#endif
+#ifndef BIT57
+ #define BIT57 0x0200000000000000ull
+#endif
+#ifndef BIT58
+ #define BIT58 0x0400000000000000ull
+#endif
+#ifndef BIT59
+ #define BIT59 0x0800000000000000ull
+#endif
+#ifndef BIT60
+ #define BIT60 0x1000000000000000ull
+#endif
+#ifndef BIT61
+ #define BIT61 0x2000000000000000ull
+#endif
+#ifndef BIT62
+ #define BIT62 0x4000000000000000ull
+#endif
+#ifndef BIT63
+ #define BIT63 0x8000000000000000ull
+#endif
+
+#endif // _AMD_H_
diff --git a/src/vendorcode/amd/pi/00660F01/Dispatcher.h b/src/vendorcode/amd/pi/00660F01/Dispatcher.h
new file mode 100644
index 0000000..777f05c
--- /dev/null
+++ b/src/vendorcode/amd/pi/00660F01/Dispatcher.h
@@ -0,0 +1,51 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD Pushhigh Interface
+ *
+ * Contains interface to Pushhigh entry
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: Legacy
+ * @e \$Revision: 281175 $ @e \$Date: 2013-12-18 15:53:00 +0800 (Wed, 18 Dec 2013) $
+ *
+ */
+ /*****************************************************************************
+ *
+ * Copyright (c) 2008 - 2015, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ***************************************************************************/
+
+#ifndef _DISPATCHER_H_
+#define _DISPATCHER_H_
+
+// AGESA function prototypes
+AGESA_STATUS CALLCONV AmdAgesaDispatcher ( IN OUT VOID *ConfigPtr );
+AGESA_STATUS CALLCONV AmdAgesaCallout ( IN UINT32 Func, IN UINT32 Data, IN OUT VOID *ConfigPtr );
+
+#endif // _DISPATCHER_H_
diff --git a/src/vendorcode/amd/pi/00660F01/Include/Filecode.h b/src/vendorcode/amd/pi/00660F01/Include/Filecode.h
new file mode 100644
index 0000000..0e01812
--- /dev/null
+++ b/src/vendorcode/amd/pi/00660F01/Include/Filecode.h
@@ -0,0 +1,648 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Collectively assign unique filecodes for assert and debug to each source file.
+ *
+ * Publish values for decorated filenames, which can be used for
+ * ASSERT and debug support using a preprocessor define like:
+ * @n <tt> \#define FILECODE MY_C_FILENAME_FILECODE </tt> @n
+ * This file serves as a reference for debugging to associate the code and filename.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: Include
+ * @e \$Revision: 309899 $ @e \$Date: 2014-12-23 02:21:13 -0600 (Tue, 23 Dec 2014) $
+ */
+ /*****************************************************************************
+ *
+ * Copyright (c) 2008 - 2015, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ***************************************************************************/
+
+#ifndef _FILECODE_H_
+#define _FILECODE_H_
+
+#define UNASSIGNED_FILE_FILECODE (0xFFFF)
+
+/// For debug use in any Platform's options C file.
+/// Can be reused for platforms and image builds, since only one options file can be built.
+#define PLATFORM_SPECIFIC_OPTIONS_FILECODE (0xBBBB)
+
+
+#define PROC_GNB_COMMON_GNBLIBFEATURES_FILECODE (0xA001)
+#define PROC_GNB_GNBINITATEARLY_FILECODE (0xA017)
+#define PROC_GNB_GNBINITATENV_FILECODE (0xA020)
+#define PROC_GNB_GNBINITATLATE_FILECODE (0xA021)
+#define PROC_GNB_GNBINITATMID_FILECODE (0xA022)
+#define PROC_GNB_GNBINITATPOST_FILECODE (0xA023)
+#define PROC_GNB_GNBINITATRESET_FILECODE (0xA024)
+#define PROC_GNB_MODULES_GNBCOMMONLIB_GNBLIB_FILECODE (0xA025)
+#define PROC_GNB_MODULES_GNBCOMMONLIB_GNBLIBCPUACC_FILECODE (0xA026)
+#define PROC_GNB_MODULES_GNBCOMMONLIB_GNBLIBHEAP_FILECODE (0xA027)
+#define PROC_GNB_MODULES_GNBCOMMONLIB_GNBLIBIOACC_FILECODE (0xA028)
+#define PROC_GNB_MODULES_GNBCOMMONLIB_GNBLIBMEMACC_FILECODE (0xA029)
+#define PROC_GNB_MODULES_GNBCOMMONLIB_GNBLIBPCI_FILECODE (0xA02A)
+#define PROC_GNB_MODULES_GNBCOMMONLIB_GNBLIBPCIACC_FILECODE (0xA030)
+#define PROC_GNB_MODULES_GNBGFXINITLIBV1_GFXCARDINFO_FILECODE (0xA031)
+#define PROC_GNB_MODULES_GNBGFXINITLIBV1_GFXENUMCONNECTORS_FILECODE (0xA032)
+#define PROC_GNB_MODULES_GNBGFXINITLIBV1_GNBGFXINITLIBV1_FILECODE (0xA033)
+#define PROC_GNB_MODULES_GNBPCIECONFIG_PCIECONFIGDATA_FILECODE (0xA036)
+#define PROC_GNB_MODULES_GNBPCIECONFIG_PCIECONFIGLIB_FILECODE (0xA037)
+#define PROC_GNB_MODULES_GNBPCIECONFIG_PCIEINPUTPARSER_FILECODE (0xA038)
+#define PROC_GNB_MODULES_GNBPCIECONFIG_PCIEMAPTOPOLOGY_FILECODE (0xA039)
+#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEASPMBLACKLIST_FILECODE (0xA03B)
+#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEASPMEXITLATENCY_FILECODE (0xA03C)
+#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEPHYSERVICES_FILECODE (0xA03D)
+#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEPIFSERVICES_FILECODE (0xA03E)
+#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEPORTREGACC_FILECODE (0xA03F)
+#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEPORTSERVICES_FILECODE (0xA041)
+#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEPOWERMGMT_FILECODE (0xA043)
+#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIESILICONSERVICES_FILECODE (0xA045)
+#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIETIMER_FILECODE (0xA046)
+#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIETOPOLOGYSERVICES_FILECODE (0xA047)
+#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEUTILITYLIB_FILECODE (0xA048)
+#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEWRAPPERREGACC_FILECODE (0xA049)
+#define PROC_GNB_MODULES_GNBPCIECOMMCLKCFG_PCIECOMMCLKCFG_FILECODE (0xA04C)
+
+#define PROC_GNB_MODULES_GNBGFXCONFIG_GFXCONFIGENV_FILECODE (0xA08E)
+#define PROC_GNB_MODULES_GNBGFXCONFIG_GFXCONFIGPOST_FILECODE (0xA08F)
+#define PROC_GNB_MODULES_GNBTABLE_GNBTABLE_FILECODE (0xA090)
+#define PROC_GNB_MODULES_GNBGFXCONFIG_GFXCONFIGLIB_FILECODE (0xA093)
+#define PROC_GNB_MODULES_GNBPCIEINITLIBV4_PCIEWRAPPERSERVICESV4_FILECODE (0xA0A6)
+#define PROC_GNB_MODULES_GNBIOMMUIVRS_GNBIOMMUIVRS_FILECODE (0xA0A7)
+#define PROC_GNB_MODULES_GNBIVRSLIB_GNBIVRSLIB_FILECODE (0xA0A8)
+#define PROC_GNB_MODULES_GNBNBINITLIBV4_GNBNBINITLIBV4_FILECODE (0xA0A9)
+#define PROC_GNB_MODULES_GNBFAMTRANSLATION_GNBPCIETRANSLATION_FILECODE (0xA0AA)
+
+#define PROC_GNB_MODULES_GNBSBLIB_GNBSBPCIE_FILECODE (0xA0BA)
+#define PROC_GNB_MODULES_GNBSBLIB_GNBSBLIB_FILECODE (0xA0BB)
+#define PROC_GNB_MODULES_GNBSBIOMMULIB_GNBSBIOMMULIB_FILECODE (0xA0BC)
+#define PROC_GNB_MODULES_GNBCOMMONLIB_GNBTIMERLIB_FILECODE (0xA0BD)
+#define PROC_GNB_MODULES_GNBSSOCKETLIB_GNBSSOCKETLIB_FILECODE (0xA0BF)
+#define PROC_GNB_MODULES_GNBPCIECONFIG_GNBHANDLELIB_FILECODE (0xA0C0)
+#define PROC_GNB_MODULES_GNBPCIEASPM_PCIEASPM_FILECODE (0xA0C2)
+
+#define PROC_GNB_MODULES_GNBPCIEINITLIBV5_PCIEASPMEXITLATENCYV5_FILECODE (0xA0C5)
+#define PROC_GNB_MODULES_GNBPCIEINITLIBV5_PCIEPIFSERVICESV5_FILECODE (0xA0C6)
+#define PROC_GNB_MODULES_GNBPCIEINITLIBV5_PCIEPORTSERVICESV5_FILECODE (0xA0C7)
+#define PROC_GNB_MODULES_GNBPCIEINITLIBV5_PCIEPOWERMGMTV5_FILECODE (0xA0C8)
+#define PROC_GNB_MODULES_GNBPCIEINITLIBV5_PCIESILICONSERVICESV5_FILECODE (0xA0C9)
+#define PROC_GNB_MODULES_GNBPCIEINITLIBV5_PCIEWRAPPERSERVICESV5_FILECODE (0xA0CA)
+#define PROC_GNB_MODULES_GNBNBINITLIBV5_GNBNBINITLIBV5_FILECODE (0xA0CB)
+
+#define PROC_GNB_MODULES_GNBFAMTRANSLATION_GNBTRANSLATION_FILECODE (0xA0DB)
+#define PROC_GNB_MODULES_GNBPCIEINITLIBV4_PCIEPOWERMGMTV4_FILECODE (0xA0DC)
+#define PROC_GNB_MODULES_GNBPCIEINITLIBV4_PCIEPORTSERVICESV4_FILECODE (0xA0DD)
+
+#define PROC_GNB_MODULES_GNBGFXCONFIG_GFXCONFIGMID_FILECODE (0xA0E0)
+
+#define PROC_GNB_MODULES_GNBIOAPIC_GNBIOAPIC_FILECODE (0xA0EE)
+
+#define PROC_GNB_MODULES_GNBPCIEMAXPAYLOAD_PCIEMAXPAYLOAD_FILECODE (0xA0F4)
+#define PROC_GNB_MODULES_GNBPCIECLKPM_PCIECLKPM_FILECODE (0xA0F5)
+
+#define PROC_GNB_MODULES_GNBPCIEINITLIBV5_PCIETOPOLOGYSERVICESV5_FILECODE (0xA100)
+#define PROC_GNB_MODULES_GNBPCIETRAININGV2_PCIETRAININGV2_FILECODE (0xA101)
+#define PROC_GNB_MODULES_GNBPCIETRAININGV2_PCIEWORKAROUNDSV2_FILECODE (0xA102)
+
+#define PROC_GNB_MODULES_GNBINITCZ_ALIBCZ_FILECODE (0xA202)
+#define PROC_GNB_MODULES_GNBINITCZ_GFXENVINITCZ_FILECODE (0xA203)
+#define PROC_GNB_MODULES_GNBINITCZ_GFXGMCINITCZ_FILECODE (0xA204)
+#define PROC_GNB_MODULES_GNBINITCZ_GFXINTEGRATEDINFOTABLECZ_FILECODE (0xA205)
+#define PROC_GNB_MODULES_GNBINITCZ_GFXLIBCZ_FILECODE (0xA206)
+#define PROC_GNB_MODULES_GNBINITCZ_GFXMIDINITCZ_FILECODE (0xA207)
+#define PROC_GNB_MODULES_GNBINITCZ_GFXPOSTINITCZ_FILECODE (0xA208)
+#define PROC_GNB_MODULES_GNBINITCZ_GNBEARLYINITCZ_FILECODE (0xA209)
+#define PROC_GNB_MODULES_GNBINITCZ_GNBENVINITCZ_FILECODE (0xA20A)
+#define PROC_GNB_MODULES_GNBINITCZ_GNBFUSETABLECZ_FILECODE (0xA20B)
+#define PROC_GNB_MODULES_GNBINITCZ_GNBIOMMUIVRSCZ_FILECODE (0xA20C)
+#define PROC_GNB_MODULES_GNBINITCZ_GNBMIDINITCZ_FILECODE (0xA20D)
+#define PROC_GNB_MODULES_GNBINITCZ_GNBPOSTINITCZ_FILECODE (0xA20E)
+#define PROC_GNB_MODULES_GNBINITCZ_GNBREGISTERACCCZ_FILECODE (0xA20F)
+#define PROC_GNB_MODULES_GNBINITCZ_GNBURATOKENMAPCZ_FILECODE (0xA211)
+#define PROC_GNB_MODULES_GNBINITCZ_PCIECOMPLEXDATACZ_FILECODE (0xA212)
+#define PROC_GNB_MODULES_GNBINITCZ_PCIECONFIGCZ_FILECODE (0xA213)
+#define PROC_GNB_MODULES_GNBINITCZ_PCIEEARLYINITCZ_FILECODE (0xA214)
+#define PROC_GNB_MODULES_GNBINITCZ_PCIEENVINITCZ_FILECODE (0xA215)
+#define PROC_GNB_MODULES_GNBINITCZ_PCIELIBCZ_FILECODE (0xA216)
+#define PROC_GNB_MODULES_GNBINITCZ_PCIEMIDINITCZ_FILECODE (0xA217)
+#define PROC_GNB_MODULES_GNBINITCZ_PCIEPOSTINITCZ_FILECODE (0xA218)
+#define PROC_GNB_MODULES_GNBINITCZ_PCIEPOWERGATECZ_FILECODE (0xA219)
+#define PROC_GNB_MODULES_GNBINITCZ_GNBURACZ_FILECODE (0xA21A)
+#define PROC_GNB_MODULES_GNBSMULIBV8_GNBSMUINITLIBV8_FILECODE (0xA21B)
+#define PROC_GNB_MODULES_GNBINITCZ_PCIEARIINITCZ_FILECODE (0xA21C)
+#define PROC_GNB_MODULES_GNBINITCZ_GNBBOOTTIMECALCZ_FILECODE (0xA21D)
+#define PROC_GNB_MODULES_GNBINITCZ_GNBPSPCZ_FILECODE (0xA21E)
+#define PROC_GNB_MODULES_GNBINITCZ_GNBSMUINITCZ_FILECODE (0xA21F)
+
+#define PROC_RECOVERY_GNB_GNBRECOVERY_FILECODE (0xAE01)
+#define PROC_RECOVERY_GNB_NBINITRECOVERY_FILECODE (0xAE02)
+#define PROC_GNB_GNBINITATRTB_FILECODE (0xAE03)
+#define PROC_GNB_MODULES_GNBSVIEW_GNBSVIEW_FILECODE (0xAE04)
+
+#define PROC_GNB_MODULES_GNBIOMMUSCRATCH_GNBIOMMUSCRATCH_FILECODE (0xAE18)
+
+#define PROC_GNB_MODULES_GNBPCIEALIBV2_PCIEALIBV2_FILECODE (0xAE33)
+#define PROC_GNB_MODULES_GNBURALIBV1_GNBURALIBV1_FILECODE (0xAE3A)
+#define PROC_GNB_MODULES_GNBGFXINTTABLEV5_GFXLIBV5_FILECODE (0xAE41)
+#define PROC_GNB_MODULES_GNBGFXINTTABLEV5_GFXINTEGRATEDINFOTABLEV5_FILECODE (0xAE42)
+#define PROC_GNB_MODULES_GNBGFXINTTABLEV5_GFXPWRPLAYTABLEV5_FILECODE (0xAE43)
+#define PROC_GNB_MODULES_GNBAZALIALIB_GNBAZALIALIB_FILECODE (0xAE44)
+
+// FCH
+#define PROC_FCH_COMMON_ACPILIB_FILECODE (0xB010)
+#define PROC_FCH_COMMON_FCHLIB_FILECODE (0xB011)
+#define PROC_FCH_COMMON_FCHCOMMON_FILECODE (0xB012)
+#define PROC_FCH_COMMON_FCHCOMMONSMM_FILECODE (0xB013)
+#define PROC_FCH_COMMON_MEMLIB_FILECODE (0xB014)
+#define PROC_FCH_COMMON_PCILIB_FILECODE (0xB015)
+#define PROC_FCH_COMMON_FCHPELIB_FILECODE (0xB016)
+
+#define UEFI_SMM_MEMSMMLIB_MEMSMMLIB_FILECODE (0xB2C1)
+#define UEFI_SMM_MEMSMMLIB_CZ_DRAMMAPCZ_FILECODE (0xB2C3)
+#define PROC_FCH_KERN_KERNAZALIA_KERNAZALIARESET_FILECODE (0xB400)
+#define PROC_FCH_KERN_KERNAZALIA_KERNAZALIAENV_FILECODE (0xB401)
+#define PROC_FCH_KERN_KERNAZALIA_KERNAZALIAMID_FILECODE (0xB402)
+#define PROC_FCH_KERN_KERNAZALIA_KERNAZALIALATE_FILECODE (0xB403)
+#define PROC_FCH_KERN_KERNHWACPI_KERNHWACPIRESET_FILECODE (0xB410)
+#define PROC_FCH_KERN_KERNHWACPI_KERNHWACPIENV_FILECODE (0xB411)
+#define PROC_FCH_KERN_KERNHWACPI_KERNHWACPIMID_FILECODE (0xB412)
+#define PROC_FCH_KERN_KERNHWACPI_KERNHWACPILATE_FILECODE (0xB413)
+#define PROC_FCH_KERN_KERNHWACPI_KERNSSSERVICE_FILECODE (0xB414)
+#define PROC_FCH_KERN_KERNHWACPI_KERNHWACPIENVSERVICE_FILECODE (0xB415)
+#define PROC_FCH_KERN_KERNHWACPI_KERNHWACPIMIDSERVICE_FILECODE (0xB416)
+#define PROC_FCH_KERN_KERNHWACPI_KERNHWACPILATESERVICE_FILECODE (0xB417)
+#define PROC_FCH_KERN_KERNHWM_KERNHWMRESET_FILECODE (0xB420)
+#define PROC_FCH_KERN_KERNHWM_KERNHWMENV_FILECODE (0xB421)
+#define PROC_FCH_KERN_KERNHWM_KERNHWMMID_FILECODE (0xB422)
+#define PROC_FCH_KERN_KERNHWM_KERNHWMLATE_FILECODE (0xB423)
+#define PROC_FCH_KERN_KERNHWM_KERNHWMENVSERVICE_FILECODE (0xB424)
+#define PROC_FCH_KERN_KERNHWM_KERNHWMMIDSERVICE_FILECODE (0xB425)
+#define PROC_FCH_KERN_KERNHWM_KERNHWMLATESERVICE_FILECODE (0xB426)
+#define PROC_FCH_KERN_KERNINTERFACE_KERNFCHINITRESET_FILECODE (0xB427)
+#define PROC_FCH_KERN_KERNINTERFACE_KERNFCHINITENV_FILECODE (0xB428)
+#define PROC_FCH_KERN_KERNINTERFACE_KERNFCHINITMID_FILECODE (0xB429)
+#define PROC_FCH_KERN_KERNINTERFACE_KERNFCHINITLATE_FILECODE (0xB42A)
+#define PROC_FCH_KERN_KERNINTERFACE_KERNFCHINITS3_FILECODE (0xB42B)
+#define PROC_FCH_KERN_KERNINTERFACE_KERNINITRESETDEF_FILECODE (0xB42C)
+#define PROC_FCH_KERN_KERNINTERFACE_KERNINITENVDEF_FILECODE (0xB42D)
+#define PROC_FCH_KERN_KERNINTERFACE_KERNFCHTASKLAUNCHER_FILECODE (0xB42E)
+#define PROC_FCH_KERN_KERNIMC_KERNIMCRESET_FILECODE (0xB430)
+#define PROC_FCH_KERN_KERNIMC_KERNIMCENV_FILECODE (0xB431)
+#define PROC_FCH_KERN_KERNIMC_KERNIMCMID_FILECODE (0xB432)
+#define PROC_FCH_KERN_KERNIMC_KERNIMCLATE_FILECODE (0xB433)
+#define PROC_FCH_KERN_KERNIMC_KERNFCHECRESET_FILECODE (0xB434)
+#define PROC_FCH_KERN_KERNIMC_KERNFCHECENV_FILECODE (0xB435)
+#define PROC_FCH_KERN_KERNIMC_KERNFCHECMID_FILECODE (0xB436)
+#define PROC_FCH_KERN_KERNIMC_KERNFCHECLATE_FILECODE (0xB437)
+#define PROC_FCH_KERN_KERNIMC_KERNIMCLIB_FILECODE (0xB438)
+#define PROC_FCH_KERN_KERNIMC_KERNIMCSERVICE_FILECODE (0xB439)
+#define PROC_FCH_KERN_KERNIR_KERNIRENV_FILECODE (0xB43A)
+#define PROC_FCH_KERN_KERNIR_KERNIRMID_FILECODE (0xB43B)
+#define PROC_FCH_KERN_KERNIR_KERNIRLATE_FILECODE (0xB43C)
+#define PROC_FCH_KERN_KERNPCIE_KERNABRESET_FILECODE (0xB440)
+#define PROC_FCH_KERN_KERNPCIE_KERNABENV_FILECODE (0xB441)
+#define PROC_FCH_KERN_KERNPCIE_KERNABMID_FILECODE (0xB442)
+#define PROC_FCH_KERN_KERNPCIE_KERNABLATE_FILECODE (0xB443)
+#define PROC_FCH_KERN_KERNPCIE_KERNABENVSERVICE_FILECODE (0xB44C)
+#define PROC_FCH_KERN_KERNPCIE_KERNABRESETSERVICE_FILECODE (0xB44D)
+#define PROC_FCH_KERN_KERNPCIE_KERNABSERVICE_FILECODE (0xB44E)
+#define PROC_FCH_KERN_KERNSATA_KERNSATARESET_FILECODE (0xB460)
+#define PROC_FCH_KERN_KERNSATA_KERNSATAENV_FILECODE (0xB461)
+#define PROC_FCH_KERN_KERNSATA_KERNSATAMID_FILECODE (0xB462)
+#define PROC_FCH_KERN_KERNSATA_KERNSATALATE_FILECODE (0xB463)
+#define PROC_FCH_KERN_KERNSATA_KERNSATARESETSERVICE_FILECODE (0xB464)
+#define PROC_FCH_KERN_KERNSATA_KERNSATAENVSERVICE_FILECODE (0xB465)
+#define PROC_FCH_KERN_KERNSATA_KERNSATASERVICE_FILECODE (0xB466)
+#define PROC_FCH_KERN_KERNSATA_KERNSATALIB_FILECODE (0xB467)
+#define PROC_FCH_KERN_KERNSATA_KERNSATAENVLIB_FILECODE (0xB468)
+#define PROC_FCH_KERN_KERNSATA_KERNAHCILIB_FILECODE (0xB469)
+#define PROC_FCH_KERN_KERNSATA_KERNAHCIENV_FILECODE (0xB46A)
+#define PROC_FCH_KERN_KERNSATA_KERNAHCIMID_FILECODE (0xB46B)
+#define PROC_FCH_KERN_KERNSATA_KERNAHCILATE_FILECODE (0xB46C)
+#define PROC_FCH_KERN_KERNSATA_KERNRAIDLIB_FILECODE (0xB46D)
+#define PROC_FCH_KERN_KERNSATA_KERNRAIDENV_FILECODE (0xB46E)
+#define PROC_FCH_KERN_KERNSATA_KERNRAIDMID_FILECODE (0xB46F)
+#define PROC_FCH_KERN_KERNSATA_KERNRAIDLATE_FILECODE (0xB470)
+#define PROC_FCH_KERN_KERNSATA_KERNIDE2AHCILIB_FILECODE (0xB471)
+#define PROC_FCH_KERN_KERNSATA_KERNIDE2AHCIENV_FILECODE (0xB472)
+#define PROC_FCH_KERN_KERNSATA_KERNIDE2AHCIMID_FILECODE (0xB473)
+#define PROC_FCH_KERN_KERNSATA_KERNIDE2AHCILATE_FILECODE (0xB474)
+#define PROC_FCH_KERN_KERNSATA_KERNSATAIDELIB_FILECODE (0xB475)
+#define PROC_FCH_KERN_KERNSATA_KERNSATAIDEENV_FILECODE (0xB476)
+#define PROC_FCH_KERN_KERNSATA_KERNSATAIDEMID_FILECODE (0xB477)
+#define PROC_FCH_KERN_KERNSATA_KERNSATAIDELATE_FILECODE (0xB478)
+#define PROC_FCH_KERN_KERNSD_KERNSDENV_FILECODE (0xB481)
+#define PROC_FCH_KERN_KERNSD_KERNSDMID_FILECODE (0xB482)
+#define PROC_FCH_KERN_KERNSD_KERNSDLATE_FILECODE (0xB483)
+#define PROC_FCH_KERN_KERNSD_KERNSDRESETSERVICE_FILECODE (0xB484)
+#define PROC_FCH_KERN_KERNSD_KERNSDENVSERVICE_FILECODE (0xB485)
+#define PROC_FCH_KERN_KERNSD_KERNSDSERVICE_FILECODE (0xB486)
+#define PROC_FCH_KERN_KERNSPI_KERNSPIRESET_FILECODE (0xB490)
+#define PROC_FCH_KERN_KERNSPI_KERNSPIENV_FILECODE (0xB491)
+#define PROC_FCH_KERN_KERNSPI_KERNSPIMID_FILECODE (0xB492)
+#define PROC_FCH_KERN_KERNSPI_KERNSPILATE_FILECODE (0xB493)
+#define PROC_FCH_KERN_KERNSPI_KERNLPCRESET_FILECODE (0xB494)
+#define PROC_FCH_KERN_KERNSPI_KERNLPCENV_FILECODE (0xB495)
+#define PROC_FCH_KERN_KERNSPI_KERNLPCMID_FILECODE (0xB496)
+#define PROC_FCH_KERN_KERNSPI_KERNLPCLATE_FILECODE (0xB497)
+#define PROC_FCH_KERN_KERNSPI_KERNLPCRESETSERVICE_FILECODE (0xB498)
+#define PROC_FCH_KERN_KERNSPI_KERNLPCENVSERVICE_FILECODE (0xB499)
+#define PROC_FCH_KERN_KERNUSB_KERNUSBRESET_FILECODE (0xB4A0)
+#define PROC_FCH_KERN_KERNUSB_KERNUSBENV_FILECODE (0xB4A1)
+#define PROC_FCH_KERN_KERNUSB_KERNUSBMID_FILECODE (0xB4A2)
+#define PROC_FCH_KERN_KERNUSB_KERNUSBLATE_FILECODE (0xB4A3)
+#define PROC_FCH_KERN_KERNUSB_KERNEHCIRESET_FILECODE (0xB4A4)
+#define PROC_FCH_KERN_KERNUSB_KERNEHCIENV_FILECODE (0xB4A5)
+#define PROC_FCH_KERN_KERNUSB_KERNEHCIMID_FILECODE (0xB4A6)
+#define PROC_FCH_KERN_KERNUSB_KERNEHCILATE_FILECODE (0xB4A7)
+#define PROC_FCH_KERN_KERNUSB_KERNEHCIMIDSERVICE_FILECODE (0xB4A8)
+#define PROC_FCH_KERN_KERNUSB_KERNEHCIENVSERVICE_FILECODE (0xB4A9)
+#define PROC_FCH_KERN_KERNUSB_KERNEHCILATESERVICE_FILECODE (0xB4AA)
+#define PROC_FCH_KERN_KERNUSB_KERNXHCIRESET_FILECODE (0xB4B2)
+#define PROC_FCH_KERN_KERNUSB_KERNXHCIENV_FILECODE (0xB4B3)
+#define PROC_FCH_KERN_KERNUSB_KERNXHCIMID_FILECODE (0xB4B4)
+#define PROC_FCH_KERN_KERNUSB_KERNXHCILATE_FILECODE (0xB4B5)
+#define PROC_FCH_KERN_KERNUSB_KERNXHCIRESETSERVICE_FILECODE (0xB4B6)
+#define PROC_FCH_KERN_KERNUSB_KERNXHCIENVSERVICE_FILECODE (0xB4B7)
+#define PROC_FCH_KERN_KERNUSB_KERNXHCIMIDSERVICE_FILECODE (0xB4B8)
+#define PROC_FCH_KERN_KERNUSB_KERNXHCILATESERVICE_FILECODE (0xB4B9)
+#define PROC_FCH_KERN_KERNUSB_KERNXHCIRECOVERY_FILECODE (0xB4BA)
+#define UEFI_FCH_KERN_DXE_FCHACPICS_FCHACPICS_FILECODE (0xB408)
+#define UEFI_FCH_KERN_DXE_FCHACPICS_FCHACPICSAML_FILECODE (0xB409)
+#define UEFI_FCH_KERN_DXE_FCHACPICS_FCHACPICSCONTROL_FILECODE (0xB40A)
+#define UEFI_FCH_KERN_DXE_FCHACPICS_FUNCTIONS_FCHD3COLD_FCHD3COLD_FILECODE (0xB40B)
+#define UEFI_FCH_KERN_DXE_AMDFCHHWM_AMDFCHHWM_FILECODE (0xB4C1)
+#define UEFI_FCH_KERN_DXE_AMDFCHWHEA_AMDFCHWHEA_FILECODE (0xB4C2)
+#define UEFI_FCH_KERN_DXE_AMDFCHWHEA_AMDFCHWHEAEINJ_FILECODE (0xB4C3)
+#define UEFI_FCH_KERN_DXE_AMDFCHWHEA_AMDFCHWHEAHEST_FILECODE (0xB4C4)
+#define UEFI_FCH_KERN_DXE_CF9RESET_CF9RESET_FILECODE (0xB4C5)
+#define UEFI_FCH_KERN_DXE_CF9RESET_IA32_IA32CF9RESET_FILECODE (0xB4C6)
+#define UEFI_FCH_KERN_DXE_CF9RESET_X64_X64CF9RESET_FILECODE (0xB4C7)
+#define UEFI_FCH_KERN_DXE_FCHDXE_FCHDXE_FILECODE (0xB4C8)
+#define UEFI_FCH_KERN_DXE_FCHDXE_USBOC_FILECODE (0xB4C9)
+#define UEFI_FCH_KERN_DXE_FCHDXEAUX_DXEBOOTTIMER_FILECODE (0xB4CA)
+#define UEFI_FCH_KERN_DXE_FCHDXEAUX_DXEDISUSBPORT_FILECODE (0xB4CB)
+#define UEFI_FCH_KERN_DXE_FCHDXEAUX_DXEESATAPORT_FILECODE (0xB4CC)
+#define UEFI_FCH_KERN_DXE_FCHDXEAUX_DXEGPIO_FILECODE (0xB4CD)
+#define UEFI_FCH_KERN_DXE_FCHDXEAUX_DXEGPIOREAD_FILECODE (0xB4CE)
+#define UEFI_FCH_KERN_DXE_FCHDXEAUX_FCHDXEAUX_FILECODE (0xB4CF)
+#define UEFI_FCH_KERN_DXE_FCHDXELIB_FCHDXELIB_FILECODE (0xB4D0)
+#define UEFI_FCH_KERN_DXE_FCHDXELPCCLKRUN_FCHDXELPCCLKRUN_FILECODE (0xB4D1)
+#define UEFI_FCH_KERN_DXE_FCHDXEMMIO_FCHDXEMMIO_FILECODE (0xB4D2)
+#define UEFI_FCH_KERN_DXE_LEGACYINTERRUPT_LEGACYINTERRUPT_FILECODE (0xB4D3)
+#define UEFI_FCH_KERN_DXE_SMBUS_SMBUSLIGHT_FILECODE (0xB4D4)
+#define UEFI_FCH_KERN_DXE_SMMCONTROL_SMMCONTROL_FILECODE (0xB4D5)
+#define UEFI_FCH_KERN_PEI_FCHPEI_FCHEHCIRECOVERY_FILECODE (0xB4D6)
+#define UEFI_FCH_KERN_PEI_FCHPEI_FCHPEI_FILECODE (0xB4D8)
+#define UEFI_FCH_KERN_PEI_FCHPEI_FCHRESET_FILECODE (0xB4D9)
+#define UEFI_FCH_KERN_PEI_FCHPEI_FCHSATARECOVERY_FILECODE (0xB4DA)
+#define UEFI_FCH_KERN_PEI_FCHPEI_FCHSTALL_FILECODE (0xB4DB)
+#define UEFI_FCH_KERN_PEI_FCHPEI_FCHXHCIRECOVERY_FILECODE (0xB4DC)
+#define UEFI_FCH_KERN_PEI_FCHPEIAUX_FCHPEIAUX_FILECODE (0xB4DD)
+#define UEFI_FCH_KERN_PEI_FCHPEIAUX_PEIBOOTTIMER_FILECODE (0xB4DE)
+#define UEFI_FCH_KERN_PEI_FCHPEIAUX_PEIDISUSBPORT_FILECODE (0xB4DF)
+#define UEFI_FCH_KERN_PEI_FCHPEIAUX_PEIGPIO_FILECODE (0xB4E0)
+#define UEFI_FCH_KERN_PEI_FCHPEIAUX_PEIGPIOREAD_FILECODE (0xB4E1)
+#define UEFI_FCH_KERN_PEI_FCHPEIAUX_PEIOSCOUTCLOCK_FILECODE (0xB4E2)
+#define UEFI_FCH_KERN_PEI_FCHPEILIB_FCHPEILIB_FILECODE (0xB4E3)
+#define UEFI_FCH_KERN_PEI_FCHPEILIB_LIBAMDPEI_FILECODE (0xB4E4)
+#define UEFI_FCH_KERN_PEI_SMBUS_SMBUS_FILECODE (0xB4E5)
+#define UEFI_FCH_KERN_SMM_FCHSMM_FCHSMM_FILECODE (0xB4E6)
+#define UEFI_FCH_KERN_SMM_FCHSMM_GPESMI_FILECODE (0xB4E7)
+#define UEFI_FCH_KERN_SMM_FCHSMM_IOTRAPSMI_FILECODE (0xB4E8)
+#define UEFI_FCH_KERN_SMM_FCHSMM_MISCSMI_FILECODE (0xB4E9)
+#define UEFI_FCH_KERN_SMM_FCHSMM_PERIODICTIMERSMI_FILECODE (0xB4EA)
+#define UEFI_FCH_KERN_SMM_FCHSMM_POWERBUTTONSMI_FILECODE (0xB4EB)
+#define UEFI_FCH_KERN_SMM_FCHSMM_SWSMI_FILECODE (0xB4EC)
+#define UEFI_FCH_KERN_SMM_FCHSMM_SXSMI_FILECODE (0xB4ED)
+#define UEFI_FCH_KERN_SMM_FCHSMMCOMPLEMENT_IMCCONTROL_IMCCONTROL_FILECODE (0xB4F0)
+#define UEFI_FCH_KERN_SMM_FCHSMMCOMPLEMENT_IMCCONTROL_IMCCONTROLLIB_FILECODE (0xB4F1)
+#define UEFI_FCH_KERN_SMM_FCHSMMLIB_FCHDXECOMMON_FILECODE (0xB4F5)
+#define UEFI_FCH_KERN_SMM_FCHSMMLIB_FCHSMMLIB_FILECODE (0xB4F6)
+#define UEFI_FCH_KERN_SMM_FCHSMMDISPATCHER_FCHSMMDISPATCHER_FILECODE (0xB4F7)
+#define UEFI_FCH_KERN_SMM_FCHSMMDISPATCHER_FCHSMMGPEDISPATCHER_FCHSMMGPEDISPATCHER_FILECODE (0xB4F8)
+#define UEFI_FCH_KERN_SMM_FCHSMMDISPATCHER_FCHSMMIOTRAPDISPATCHER_FCHSMMIOTRAPDISPATCHER_FILECODE (0xB4F9)
+#define UEFI_FCH_KERN_SMM_FCHSMMDISPATCHER_FCHSMMMISCDISPATCHER_FCHSMMMISCDISPATCHER_FILECODE (0xB4FA)
+#define UEFI_FCH_KERN_SMM_FCHSMMDISPATCHER_FCHSMMPERIODICALDISPATCHER_FCHSMMPERIODICALDISPATCHER_FILECODE (0xB4FB)
+#define UEFI_FCH_KERN_SMM_FCHSMMDISPATCHER_FCHSMMPWRBTNDISPATCHER_FCHSMMPWRBTNDISPATCHER_FILECODE (0xB4FC)
+#define UEFI_FCH_KERN_SMM_FCHSMMDISPATCHER_FCHSMMSWDISPATCHER_FCHSMMSWDISPATCHER_FILECODE (0xB4FE)
+#define UEFI_FCH_KERN_SMM_FCHSMMDISPATCHER_FCHSMMSXDISPATCHER_FCHSMMSXDISPATCHER_FILECODE (0xB4FF)
+#define UEFI_FCH_KERN_SMM_FCHSMMDISPATCHER_FCHSMMUSBDISPATCHER_FCHSMMUSBDISPATCHER_FILECODE (0xB4F2)
+
+
+#define LIB_AMDLIB_FILECODE (0xC001)
+#define LEGACY_PROC_AGESACALLOUTS_FILECODE (0xC010)
+#define LEGACY_PROC_HOBTRANSFER_FILECODE (0xC011)
+#define LEGACY_PROC_DISPATCHER_FILECODE (0xC012)
+
+#define UEFI_DXE_AMDAGESADXEDRIVER_AMDAGESADXEDRIVER_FILECODE (0xC120)
+
+#define UEFI_PEI_AMDINITPOSTPEIM_AMDINITPOSTPEIM_FILECODE (0xC140)
+#define UEFI_PEI_AMDPROCESSORINITPEIM_AMDPROCESSORINITPEIM_FILECODE (0xC141)
+#define UEFI_PEI_AMDRESETMANAGER_AMDRESETMANAGER_FILECODE (0xC142)
+#define UEFI_PROC_COMMON_HOBTRANSFERUEFI_FILECODE (0xC160)
+#define UEFI_PROC_DXE_HOBTRANSFERUEFIDXE_FILECODE (0xC161)
+#define UEFI_PROC_PEI_HOBTRANSFERUEFIPEI_FILECODE (0xC162)
+
+#define PROC_COMMON_AMDINITEARLY_FILECODE (0xC020)
+#define PROC_COMMON_AMDINITENV_FILECODE (0xC021)
+#define PROC_COMMON_AMDINITLATE_FILECODE (0xC022)
+#define PROC_COMMON_AMDINITMID_FILECODE (0xC023)
+#define PROC_COMMON_AMDINITPOST_FILECODE (0xC024)
+#define PROC_COMMON_AMDINITRECOVERY_FILECODE (0xC025)
+#define PROC_COMMON_AMDINITRESET_FILECODE (0xC026)
+#define PROC_COMMON_AMDINITRESUME_FILECODE (0xC027)
+#define PROC_COMMON_AMDS3LATERESTORE_FILECODE (0xC028)
+#define PROC_COMMON_AMDINITRTB_FILECODE (0xC029)
+#define PROC_COMMON_AMDLATERUNAPTASK_FILECODE (0xC02A)
+#define PROC_COMMON_AMDS3FINALRESTORE_FILECODE (0xC02B)
+
+#define PROC_COMMON_COMMONRETURNS_FILECODE (0xC0C0)
+#define PROC_COMMON_CREATESTRUCT_FILECODE (0xC0D0)
+#define PROC_COMMON_COMMONINITS_FILECODE (0xC0F0)
+#define PROC_COMMON_S3RESTORESTATE_FILECODE (0xC0F8)
+#define PROC_COMMON_S3SAVESTATE_FILECODE (0xC0F9)
+#define PROC_COMMON_S3INIT_FILECODE (0xC0FA)
+
+#define PROC_CPU_CPUAPCOMM_FILECODE (0xC401)
+#define PROC_CPU_CPUAPCOMMAPIC_FILECODE (0xC402)
+#define PROC_CPU_CPUAPCOMMPCI_FILECODE (0xC403)
+#define PROC_CPU_TABLE_FILECODE (0xC404)
+#define PROC_CPU_CPUEARLYINIT_FILECODE (0xC405)
+#define PROC_CPU_CPUEVENTLOG_FILECODE (0xC406)
+#define PROC_CPU_CPUFAMILYTRANSLATION_FILECODE (0xC407)
+#define PROC_CPU_CPUGENERALSERVICES_FILECODE (0xC408)
+#define PROC_CPU_CPULATEINIT_FILECODE (0xC40A)
+#define PROC_CPU_CPUMICROCODEPATCH_FILECODE (0xC40B)
+#define PROC_CPU_CPUWARMRESET_FILECODE (0xC40C)
+#define PROC_CPU_HEAPMANAGER_FILECODE (0xC40D)
+#define PROC_CPU_CPUBIST_FILECODE (0xC40E)
+#define PROC_CPU_MMIOMAPMANAGER_FILECODE (0xC40F)
+#define PROC_CPU_CPUINITEARLYTABLE_FILECODE (0xC410)
+#define PROC_CPU_CPURESETINIT_FILECODE (0xC411)
+#define PROC_CPU_CPUPOSTINIT_FILECODE (0xC420)
+#define PROC_CPU_CPUMIDINIT_FILECODE (0xC421)
+#define PROC_CPU_CPUPOWERMGMT_FILECODE (0xC430)
+#define PROC_CPU_S3_FILECODE (0xC460)
+
+// Family 15h
+#define PROC_CPU_FAMILY_0X15_CPUCOMMONF15UTILITIES_FILECODE (0xCB01)
+#define PROC_CPU_FAMILY_0X15_CPUF15BRANDID_FILECODE (0xCB02)
+#define PROC_CPU_FAMILY_0X15_CPUF15CACHEDEFAULTS_FILECODE (0xCB03)
+#define PROC_CPU_FAMILY_0X15_CPUF15DMI_FILECODE (0xCB04)
+#define PROC_CPU_FAMILY_0X15_CPUF15UTILITIES_FILECODE (0xCB08)
+#define PROC_CPU_FAMILY_0X15_CPUF15WHEAINITDATATABLES_FILECODE (0xCB09)
+#define PROC_CPU_FAMILY_0X15_CPUF15APM_FILECODE (0xCB0A)
+#define PROC_CPU_FAMILY_0X15_CPUF15CRAT_FILECODE (0xCB0B)
+#define PROC_CPU_FAMILY_0X15_CPUF15MMIOMAP_FILECODE (0xCB0C)
+#define PROC_CPU_FAMILY_0X15_CPUF15PREFETCHMODE_FILECODE (0xCB0D)
+
+#define PROC_CPU_FAMILY_0X15_CZ_CPUF15CZCOREAFTERRESET_FILECODE (0xCB70)
+#define PROC_CPU_FAMILY_0X15_CZ_CPUF15CZDMI_FILECODE (0xCB71)
+#define PROC_CPU_FAMILY_0X15_CZ_CPUF15CZNBAFTERRESET_FILECODE (0xCB72)
+#define PROC_CPU_FAMILY_0X15_CZ_CPUF15CZPSTATE_FILECODE (0xCB73)
+#define PROC_CPU_FAMILY_0X15_CZ_CPUF15CZLOGICALIDTABLES_FILECODE (0xCB74)
+#define PROC_CPU_FAMILY_0X15_CZ_CPUF15CZMICROCODEPATCHTABLES_FILECODE (0xCB75)
+#define PROC_CPU_FAMILY_0X15_CZ_CPUF15CZALLCORETABLES_FILECODE (0xCB76)
+#define PROC_CPU_FAMILY_0X15_CZ_CPUF15CZCOMPUTEUNITTABLES_FILECODE (0xCB77)
+#define PROC_CPU_FAMILY_0X15_CZ_CPUF15CZEQUIVALENCETABLE_FILECODE (0xCB78)
+#define PROC_CPU_FAMILY_0X15_CZ_CPUF15CZPRIMARYCORETABLES_FILECODE (0xCB79)
+#define PROC_CPU_FAMILY_0X15_CZ_CPUF15CZPOWERMGMTSYSTEMTABLES_FILECODE (0xCB7A)
+#define PROC_CPU_FAMILY_0X15_CZ_CPUF15CZUTILITIES_FILECODE (0xCB7C)
+#define PROC_CPU_FAMILY_0X15_CZ_CPUF15CZC6STATE_FILECODE (0xCB7D)
+#define PROC_CPU_FAMILY_0X15_CZ_CPUF15CZCPB_FILECODE (0xCB7E)
+#define PROC_CPU_FAMILY_0X15_CZ_CPUF15CZIOCSTATE_FILECODE (0xCB7F)
+#define PROC_CPU_FAMILY_0X15_CZ_CPUF15CZCACHEFLUSHONHALT_FILECODE (0xCB80)
+#define PROC_CPU_FAMILY_0X15_CZ_CPUF15CZHTC_FILECODE (0xCB81)
+#define PROC_CPU_FAMILY_0X15_CZ_CPUF15CZINITEARLYTABLE_FILECODE (0xCB82)
+#define PROC_CPU_FAMILY_0X15_CZ_CPUF15CZEARLYSAMPLES_FILECODE (0xCB83)
+#define PROC_CPU_FAMILY_0X15_CZ_CPUF15CZPSI_FILECODE (0xCB85)
+#define PROC_CPU_FAMILY_0X15_CZ_CPUF15CZWORKAROUNDTABLE_FILECODE (0xCB87)
+#define PROC_CPU_FAMILY_0X15_CZ_CPUF15CZCC6EXITCONTROL_FILECODE (0xCB88)
+#define PROC_CPU_FAMILY_0X15_CZ_CPUF15CZCONNECTEDSTANDBY_FILECODE (0xCB89)
+#define PROC_CPU_FAMILY_0X15_CZ_CPUF15CZBTC_FILECODE (0xCB8A)
+
+#define PROC_CPU_FEATURE_CPUCACHEFLUSHONHALT_FILECODE (0xDC01)
+#define PROC_CPU_FEATURE_CPUCACHEINIT_FILECODE (0xDC02)
+#define PROC_CPU_FEATURE_CPUDMI_FILECODE (0xDC10)
+#define PROC_CPU_FEATURE_CPUPSTATETABLES_FILECODE (0xDC43)
+#define PROC_CPU_FEATURE_CPUWHEA_FILECODE (0xDC70)
+#define PROC_CPU_FEATURE_CPUC6STATE_FILECODE (0xDC82)
+#define PROC_CPU_FEATURE_CPUCPB_FILECODE (0xDC83)
+#define PROC_CPU_FEATURE_CPUIOCSTATE_FILECODE (0xDC85)
+#define PROC_CPU_FEATURE_CPUAPM_FILECODE (0xDC86)
+#define PROC_CPU_FEATURE_CPUFEATURES_FILECODE (0xDC90)
+#define PROC_CPU_FEATURE_CPUCORELEVELING_FILECODE (0xDCB0)
+#define PROC_CPU_FEATURE_CPUPSI_FILECODE (0xDCC0)
+#define PROC_CPU_FEATURE_CPUHTC_FILECODE (0xDCC1)
+#define PROC_CPU_FEATURE_CPUCRAT_FILECODE (0xDCD0)
+#define PROC_CPU_FEATURE_CPUCDIT_FILECODE (0xDCD1)
+#define PROC_CPU_FEATURE_CPUPREFETCHMODE_FILECODE (0xDCD3)
+#define PROC_CPU_FEATURE_CPUCONNECTEDSTANDBY_FILECODE (0xDCD5)
+#define PROC_CPU_FEATURE_CPUCC6EXITCONTROL_FILECODE (0xDCD6)
+
+#define PROC_RECOVERY_CPU_CPURECOVERY_FILECODE (0xDE01)
+
+#define PROC_TOPOLOGY_TOPOMAIN_FILECODE (0xE001)
+#define PROC_TOPOLOGY_TOPONB_FILECODE (0xE002)
+#define PROC_TOPOLOGY_FAM15_TOPONBFAM15_FILECODE (0xE087)
+#define PROC_TOPOLOGY_FAM15_TOPONBUTILITIESFAM15_FILECODE (0xE088)
+
+#define PROC_RECOVERY_TOPOLOGY_TOPOINITRECOVERY_FILECODE (0xE0FF)
+
+#define PROC_IDS_CONTROL_IDSCTRL_FILECODE (0xE801)
+#define PROC_IDS_LIBRARY_IDSLIB_FILECODE (0xE802)
+#define PROC_IDS_DEBUG_IDSDEBUG_FILECODE (0xE803)
+#define PROC_IDS_PERF_IDSPERF_FILECODE (0xE804)
+#define PROC_IDS_FAMILY_0X15_IDSF15ALLSERVICE_FILECODE (0xE80C)
+
+#define PROC_IDS_LIBRARY_IDSREGACC_FILECODE (0xE810)
+#define PROC_IDS_DEBUG_IDSDPHDTOUT_FILECODE (0xE811)
+#define PROC_IDS_DEBUG_IDSDEBUGPRINT_FILECODE (0xE812)
+#define PROC_IDS_DEBUG_IDSDPSERIAL_FILECODE (0xE813)
+#define PROC_IDS_DEBUG_IDSDPREDIRECTIO_FILECODE (0xE814)
+#define PROC_IDS_DEBUG_IDSDPRAM_FILECODE (0xE815)
+
+#define PROC_IDS_DEBUG_IDSIDTTABLE_FILECODE (0xE81E)
+#define PROC_IDS_CONTROL_IDSNVTOCMOS_FILECODE (0xE81F)
+#define PROC_IDS_FAMILY_0X15_CZ_IDSF15CZALLSERVICE_FILECODE (0xE821)
+
+
+///0xE820 ~ 0xE840 is reserved for ids extend module
+
+#define PROC_MEM_ARDK_MA_FILECODE (0xF001)
+
+#define PROC_MEM_FEAT_CHINTLV_MFCHI_FILECODE (0xF081)
+#define PROC_MEM_FEAT_CSINTLV_MFCSI_FILECODE (0xF082)
+#define PROC_MEM_FEAT_ECC_MFECC_FILECODE (0xF083)
+#define PROC_MEM_FEAT_ECC_MFEMP_FILECODE (0xF085)
+#define PROC_MEM_FEAT_EXCLUDIMM_MFDIMMEXCLUD_FILECODE (0xF086)
+#define PROC_MEM_FEAT_IDENDIMM_MFIDENDIMM_FILECODE (0xF088)
+#define PROC_MEM_FEAT_INTLVRN_MFINTLVRN_FILECODE (0xF089)
+#define PROC_MEM_FEAT_LVDDR3_MFLVDDR3_FILECODE (0xF08A)
+#define PROC_MEM_FEAT_MEMCLR_MFMEMCLR_FILECODE (0xF08B)
+#define PROC_MEM_FEAT_NDINTLV_MFNDI_FILECODE (0xF08C)
+#define PROC_MEM_FEAT_ODTHERMAL_MFODTHERMAL_FILECODE (0xF08D)
+#define PROC_MEM_FEAT_OLSPARE_MFSPR_FILECODE (0xF08E)
+#define PROC_MEM_FEAT_PARTRN_MFSTANDARDTRAINING_FILECODE (0xF091)
+#define PROC_MEM_FEAT_S3_MFS3_FILECODE (0xF092)
+#define PROC_MEM_FEAT_TABLE_MFTDS_FILECODE (0xF093)
+#define PROC_MEM_FEAT_CHINTLV_MFMCHI_FILECODE (0xF094)
+#define PROC_MEM_FEAT_CRAT_MFCRAT_FILECODE (0xF095)
+#define PROC_MEM_FEAT_AMP_MFAMP_FILECODE (0xF096)
+#define PROC_MEM_FEAT_DATAEYE_MF2DDATAEYE_FILECODE (0xF097)
+#define PROC_MEM_FEAT_RDWR2DTRAINING_MFWRDAT2DTRAINING_FILECODE (0xF098)
+#define PROC_MEM_FEAT_RDWR2DTRAINING_MFRDWR2DEYERIMSEARCH_FILECODE (0xF099)
+#define PROC_MEM_FEAT_RDWR2DTRAINING_MFRDDQS2DTRAINING_FILECODE (0xF09A)
+#define PROC_MEM_FEAT_RDWR2DTRAINING_MFRDWR2DTRAINING_FILECODE (0xF09B)
+#define PROC_MEM_FEAT_RDWR2DTRAINING_MFRDWR2DPATTERNGENERATION_FILECODE (0xF09C)
+#define PROC_MEM_FEAT_AGGRESSOR_MFAGGRESSOR_FILECODE (0xF09F)
+#define PROC_MEM_FEAT_DLLPDBYPASS_MFDLLPDBYPASS_FILECODE (0xF0A0)
+
+#define PROC_MEM_MAIN_MDEF_FILECODE (0xF101)
+#define PROC_MEM_MAIN_MINIT_FILECODE (0xF102)
+#define PROC_MEM_MAIN_MM_FILECODE (0xF103)
+#define PROC_MEM_FEAT_DMI_MFDMI_FILECODE (0xF104)
+#define PROC_MEM_MAIN_MMECC_FILECODE (0xF105)
+#define PROC_MEM_MAIN_MMEXCLUDEDIMM_FILECODE (0xF106)
+#define PROC_MEM_MAIN_MMNODEINTERLEAVE_FILECODE (0xF10B)
+#define PROC_MEM_MAIN_MMONLINESPARE_FILECODE (0xF10C)
+#define PROC_MEM_MAIN_MMPARALLELTRAINING_FILECODE (0xF10D)
+#define PROC_MEM_MAIN_MMSTANDARDTRAINING_FILECODE (0xF10E)
+#define PROC_MEM_MAIN_MUC_FILECODE (0xF10F)
+#define PROC_MEM_MAIN_MMMEMCLR_FILECODE (0xF110)
+#define PROC_MEM_MAIN_MMFLOW_FILECODE (0xF112)
+#define PROC_MEM_MAIN_MERRHDL_FILECODE (0xF113)
+#define PROC_MEM_MAIN_MMLVDDR3_FILECODE (0xF115)
+#define PROC_MEM_MAIN_MMUMAALLOC_FILECODE (0xF116)
+#define PROC_MEM_MAIN_MMMEMRESTORE_FILECODE (0xF117)
+#define PROC_MEM_MAIN_MMCONDITIONALPSO_FILECODE (0xF118)
+#define PROC_MEM_MAIN_MMAGGRESSOR_FILECODE (0xF119)
+#define PROC_MEM_MAIN_CZ_MMFLOWD3CZ_FILECODE (0xF127)
+
+#define PROC_MEM_NB_MN_FILECODE (0XF27C)
+#define PROC_MEM_NB_MNDCT_FILECODE (0XF27D)
+#define PROC_MEM_NB_MNPHY_FILECODE (0XF27E)
+#define PROC_MEM_NB_MNMCT_FILECODE (0XF27F)
+#define PROC_MEM_NB_MNS3_FILECODE (0XF280)
+#define PROC_MEM_NB_MNFLOW_FILECODE (0XF281)
+#define PROC_MEM_NB_MNFEAT_FILECODE (0XF282)
+#define PROC_MEM_NB_MNTRAIN3_FILECODE (0XF284)
+#define PROC_MEM_NB_MNREG_FILECODE (0XF285)
+#define PROC_MEM_NB_MNPMU_FILECODE (0xF2B7)
+#define PROC_MEM_NB_CZ_MNCZ_FILECODE (0xF2D8)
+#define PROC_MEM_NB_CZ_MNDCTCZ_FILECODE (0xF2D9)
+#define PROC_MEM_NB_CZ_MNIDENDIMMCZ_FILECODE (0xF2DA)
+#define PROC_MEM_NB_CZ_MNMCTCZ_FILECODE (0xF2DB)
+#define PROC_MEM_NB_CZ_MNPHYCZ_FILECODE (0xF2DC)
+#define PROC_MEM_NB_CZ_MNPMUCZ_FILECODE (0xF2DD)
+#define PROC_MEM_NB_CZ_MNPMUSRAMMSGBLOCKCZ_FILECODE (0xF2DE)
+#define PROC_MEM_NB_CZ_MNPROTOCZ_FILECODE (0xF2DF)
+#define PROC_MEM_NB_CZ_MNREGCZ_FILECODE (0xF2E0)
+#define PROC_MEM_NB_CZ_MNS3CZ_FILECODE (0xF2E1)
+#define PROC_MEM_NB_CZ_MNPSPCZ_FILECODE (0XF2E3)
+
+
+#define PROC_MEM_PS_MP_FILECODE (0XF401)
+#define PROC_MEM_PS_MPRTT_FILECODE (0XF422)
+#define PROC_MEM_PS_MPMAXFREQ_FILECODE (0XF423)
+#define PROC_MEM_PS_MPODTPAT_FILECODE (0XF424)
+#define PROC_MEM_PS_MPSAO_FILECODE (0XF425)
+#define PROC_MEM_PS_MPMR0_FILECODE (0XF426)
+#define PROC_MEM_PS_MPRC2IBT_FILECODE (0XF427)
+#define PROC_MEM_PS_MPRC10OPSPD_FILECODE (0XF428)
+#define PROC_MEM_PS_MPLRIBT_FILECODE (0XF429)
+#define PROC_MEM_PS_MPLRNPR_FILECODE (0XF42A)
+#define PROC_MEM_PS_MPLRNLR_FILECODE (0XF42B)
+#define PROC_MEM_PS_MPS2D_FILECODE (0XF436)
+#define PROC_MEM_PS_MPSEEDS_FILECODE (0XF437)
+#define PROC_MEM_PS_MPCADCFG_FILECODE (0XF43C)
+#define PROC_MEM_PS_MPDATACFG_FILECODE (0XF43D)
+#define PROC_MEM_PS_CZ_MPCZ3_FILECODE (0XF445)
+#define PROC_MEM_PS_CZ_MPSCZ3_FILECODE (0XF446)
+#define PROC_MEM_PS_CZ_MPUCZ3_FILECODE (0XF447)
+#define PROC_MEM_PS_CZ_FP4_MPSCZFP4_FILECODE (0XF44A)
+#define PROC_MEM_PS_CZ_FP4_MPUCZFP4_FILECODE (0XF44B)
+
+
+#define PROC_MEM_TECH_MT_FILECODE (0XF501)
+#define PROC_MEM_TECH_MTHDI_FILECODE (0XF502)
+#define PROC_MEM_TECH_MTTDIMBT_FILECODE (0XF504)
+#define PROC_MEM_TECH_MTTECC_FILECODE (0XF505)
+#define PROC_MEM_TECH_MTTHRC_FILECODE (0XF506)
+#define PROC_MEM_TECH_MTTML_FILECODE (0XF507)
+#define PROC_MEM_TECH_MTTOPTSRC_FILECODE (0XF509)
+#define PROC_MEM_TECH_MTTSRC_FILECODE (0XF50B)
+#define PROC_MEM_TECH_MTTEDGEDETECT_FILECODE (0XF50C)
+#define PROC_MEM_TECH_DDR3_MT3_FILECODE (0XF581)
+#define PROC_MEM_TECH_DDR3_MTOT3_FILECODE (0XF583)
+#define PROC_MEM_TECH_DDR3_MTRCI3_FILECODE (0XF584)
+#define PROC_MEM_TECH_DDR3_MTSDI3_FILECODE (0XF585)
+#define PROC_MEM_TECH_DDR3_MTSPD3_FILECODE (0XF586)
+#define PROC_MEM_TECH_DDR3_MTTWL3_FILECODE (0XF587)
+#define PROC_MEM_TECH_DDR3_MTTECC3_FILECODE (0XF588)
+#define PROC_MEM_TECH_DDR3_MTLRDIMM3_FILECODE (0XF589)
+#define PROC_MEM_TECH_MTTHRCSEEDTRAIN_FILECODE (0XF58A)
+#define PROC_MEM_TECH_MTTRDDQS2DTRAINING_FILECODE (0XF58B)
+#define PROC_MEM_TECH_MTTRDDQS2DEYERIMSEARCH_FILECODE (0XF58C)
+
+#define PROC_MEM_X86_MEMINITLIBX86_FILECODE (0xF590)
+#define PROC_MEM_A57_MEMINITLIBA57_FILECODE (0xF591)
+
+#define PROC_RECOVERY_MEM_MRDEF_FILECODE (0XF801)
+#define PROC_RECOVERY_MEM_MRINIT_FILECODE (0XF802)
+#define PROC_RECOVERY_MEM_MRM_FILECODE (0XF803)
+#define PROC_RECOVERY_MEM_MRUC_FILECODE (0XF804)
+#define PROC_RECOVERY_MEM_TECH_MRTTPOS_FILECODE (0XF8C1)
+#define PROC_RECOVERY_MEM_TECH_MRTTSRC_FILECODE (0XF8C2)
+#define PROC_RECOVERY_MEM_TECH_DDR3_MRT3_FILECODE (0XF8C3)
+#define PROC_RECOVERY_MEM_TECH_DDR3_MRTRCI3_FILECODE (0XF8C4)
+#define PROC_RECOVERY_MEM_TECH_DDR3_MRTSDI3_FILECODE (0XF8C5)
+#define PROC_RECOVERY_MEM_TECH_DDR3_MRTSPD3_FILECODE (0XF8C6)
+#define PROC_RECOVERY_MEM_TECH_DDR3_MRTTWL3_FILECODE (0XF8C7)
+#define PROC_RECOVERY_MEM_NB_MRN_FILECODE (0XF8C8)
+#define PROC_RECOVERY_MEM_NB_MRNDCT_FILECODE (0XF8C9)
+#define PROC_RECOVERY_MEM_NB_MRNMCT_FILECODE (0XF8CA)
+#define PROC_RECOVERY_MEM_NB_MRNTRAIN3_FILECODE (0XF8CB)
+#define PROC_RECOVERY_MEM_TECH_MRTTHRC_FILECODE (0XF8CC)
+#define PROC_RECOVERY_MEM_PS_MRP_FILECODE (0XF8E0)
+#define PROC_RECOVERY_MEM_PS_MRPRTT_FILECODE (0XF8E1)
+#define PROC_RECOVERY_MEM_PS_MRPODTPAT_FILECODE (0XF8E2)
+#define PROC_RECOVERY_MEM_PS_MRPSAO_FILECODE (0XF8E3)
+#define PROC_RECOVERY_MEM_PS_MRPMR0_FILECODE (0XF8E4)
+#define PROC_RECOVERY_MEM_PS_MRPRC2IBT_FILECODE (0XF8E5)
+#define PROC_RECOVERY_MEM_PS_MRPRC10OPSPD_FILECODE (0XF8E6)
+#define PROC_RECOVERY_MEM_PS_MRPLRIBT_FILECODE (0XF8E7)
+#define PROC_RECOVERY_MEM_PS_MRPLRNPR_FILECODE (0XF8E8)
+#define PROC_RECOVERY_MEM_PS_MRPLRNLR_FILECODE (0XF8E9)
+#define PROC_RECOVERY_MEM_TECH_MRTTHRCSEEDTRAIN_FILECODE (0XF8FA)
+
+//Psp
+#define PROC_PSP_PSPBASELIB_PSPBASELIB_FILECODE (0xFA20)
+
+#endif // _FILECODE_H_
diff --git a/src/vendorcode/amd/pi/00660F01/Include/GeneralServices.h b/src/vendorcode/amd/pi/00660F01/Include/GeneralServices.h
new file mode 100644
index 0000000..aea946a
--- /dev/null
+++ b/src/vendorcode/amd/pi/00660F01/Include/GeneralServices.h
@@ -0,0 +1,222 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * General Services
+ *
+ * Provides Services similar to the external General Services API, except
+ * suited to use within AGESA components. Socket, Core and PCI identification.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: Common
+ * @e \$Revision: 309090 $ @e \$Date: 2014-12-09 12:28:05 -0600 (Tue, 09 Dec 2014) $
+ *
+ */
+ /*****************************************************************************
+ *
+ * Copyright (c) 2008 - 2015, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ***************************************************************************/
+
+#ifndef _GENERAL_SERVICES_H_
+#define _GENERAL_SERVICES_H_
+
+/*----------------------------------------------------------------------------------------
+ * M I X E D (Definitions And Macros / Typedefs, Structures, Enums)
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ * D E F I N I T I O N S A N D M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+#define NUMBER_OF_EVENT_DATA_PARAMS 4
+
+/**
+ * AMD Device id for MMIO check.
+ */
+#define AMD_DEV_VEN_ID 0x1022
+#define AMD_DEV_VEN_ID_ADDRESS 0
+
+/*----------------------------------------------------------------------------------------
+ * T Y P E D E F S, S T R U C T U R E S, E N U M S
+ *----------------------------------------------------------------------------------------
+ */
+
+/**
+ * An AGESA Event Log entry.
+ */
+typedef struct {
+ AGESA_STATUS EventClass; ///< The severity of the event, its associated AGESA_STATUS.
+ UINT32 EventInfo; ///< Uniquely identifies the event.
+ UINT32 DataParam1; ///< Event specific additional data
+ UINT32 DataParam2; ///< Event specific additional data
+ UINT32 DataParam3; ///< Event specific additional data
+ UINT32 DataParam4; ///< Event specific additional data
+} AGESA_EVENT;
+
+/*----------------------------------------------------------------------------------------
+ * F U N C T I O N P R O T O T Y P E
+ *----------------------------------------------------------------------------------------
+ */
+
+/**
+ * Get a specified Core's APIC ID.
+ *
+ * @param[in] StdHeader Header for library and services.
+ * @param[in] Socket The Core's Socket.
+ * @param[in] Core The Core id.
+ * @param[out] ApicAddress The Core's APIC ID.
+ * @param[out] AgesaStatus Aggregates AGESA_STATUS for external interface, Always Succeeds.
+ *
+ * @retval TRUE The core is present, APIC Id valid
+ * @retval FALSE The core is not present, APIC Id not valid.
+ */
+BOOLEAN
+GetApicId (
+ IN AMD_CONFIG_PARAMS *StdHeader,
+ IN UINT32 Socket,
+ IN UINT32 Core,
+ OUT UINT8 *ApicAddress,
+ OUT AGESA_STATUS *AgesaStatus
+);
+
+/**
+ * Get Processor Module's PCI Config Space address.
+ *
+ * @param[in] StdHeader Header for library and services.
+ * @param[in] Socket The Core's Socket.
+ * @param[in] Module The Module in that Processor
+ * @param[out] PciAddress The Processor's PCI Config Space address (Function 0, Register 0)
+ * @param[out] AgesaStatus Aggregates AGESA_STATUS for external interface, Always Succeeds.
+ *
+ * @retval TRUE The core is present, PCI Address valid
+ * @retval FALSE The core is not present, PCI Address not valid.
+ */
+BOOLEAN
+GetPciAddress (
+ IN AMD_CONFIG_PARAMS *StdHeader,
+ IN UINT32 Socket,
+ IN UINT32 Module,
+ OUT PCI_ADDR *PciAddress,
+ OUT AGESA_STATUS *AgesaStatus
+);
+
+/**
+ * "Who am I" for the current running core.
+ *
+ * @param[in] StdHeader Header for library and services.
+ * @param[out] Socket The current Core's Socket
+ * @param[out] Module The current Core's Processor Module
+ * @param[out] Core The current Core's core id.
+ * @param[out] AgesaStatus Aggregates AGESA_STATUS for external interface, Always Succeeds.
+ *
+ */
+VOID
+IdentifyCore (
+ IN AMD_CONFIG_PARAMS *StdHeader,
+ OUT UINT32 *Socket,
+ OUT UINT32 *Module,
+ OUT UINT32 *Core,
+ OUT AGESA_STATUS *AgesaStatus
+);
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Is this the BSP core?
+ *
+ * @param[in,out] StdHeader Header for library and services
+ *
+ * @retval TRUE Is BSP core
+ * @retval FALSE Is not BSP Core
+ *
+ */
+BOOLEAN
+IsBsp (
+ IN OUT AMD_CONFIG_PARAMS *StdHeader
+ );
+
+/**
+ * This function logs AGESA events into the event log.
+ */
+VOID
+PutEventLog (
+ IN AGESA_STATUS EventClass,
+ IN UINT32 EventInfo,
+ IN UINT32 DataParam1,
+ IN UINT32 DataParam2,
+ IN UINT32 DataParam3,
+ IN UINT32 DataParam4,
+ IN AMD_CONFIG_PARAMS *StdHeader
+ );
+
+/**
+ * This function gets event logs from the circular buffer.
+ */
+AGESA_STATUS
+GetEventLog (
+ OUT AGESA_EVENT *EventRecord,
+ IN AMD_CONFIG_PARAMS *StdHeader
+ );
+
+/**
+ * This function gets event logs from the circular buffer without flushing the entry.
+ */
+BOOLEAN
+PeekEventLog (
+ OUT AGESA_EVENT *EventRecord,
+ IN UINT16 Index,
+ IN AMD_CONFIG_PARAMS *StdHeader
+ );
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * This routine programs the registers necessary to get the PCI MMIO mechanism
+ * up and functioning.
+ */
+VOID
+InitializePciMmio (
+ IN AMD_CONFIG_PARAMS *StdHeader
+ );
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ *
+ * Is it SecureS3
+ *
+ * @param[in] StdHeader Header for library and services
+ *
+ * @retval TRUE It's SecureS3
+ * @retval FALSE It's NOT SecureS3
+ *
+ */
+BOOLEAN
+IsSecureS3 (
+ IN AMD_CONFIG_PARAMS *StdHeader
+ );
+
+#endif // _GENERAL_SERVICES_H_
diff --git a/src/vendorcode/amd/pi/00660F01/Include/Ids.h b/src/vendorcode/amd/pi/00660F01/Include/Ids.h
new file mode 100644
index 0000000..cb10186
--- /dev/null
+++ b/src/vendorcode/amd/pi/00660F01/Include/Ids.h
@@ -0,0 +1,1484 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD IDS Routines
+ *
+ * Contains AMD AGESA Integrated Debug Macros
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: IDS
+ * @e \$Revision: 309899 $ @e \$Date: 2014-12-23 02:21:13 -0600 (Tue, 23 Dec 2014) $
+ */
+ /*****************************************************************************
+ *
+ * Copyright (c) 2008 - 2015, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ***************************************************************************/
+
+ /* Macros to aid debugging */
+ /* These definitions expand to zero (0) bytes of code when disabled */
+
+#ifndef _IDS_H_
+#define _IDS_H_
+
+#undef FALSE
+#undef TRUE
+#define FALSE 0
+#define TRUE 1
+// Proto type for optionsids.h
+typedef UINT32 IDS_STATUS; ///< Status of IDS function.
+#define IDS_SUCCESS ((IDS_STATUS) 0x00000000ul) ///< IDS Function is Successful.
+#define IDS_UNSUPPORTED ((IDS_STATUS) 0xFFFFFFFFul) ///< IDS Function is not existed.
+
+#define IDS_STRINGIZE(a) #a ///< for define stringize macro
+#ifndef IDS_DEADLOOP
+ #define IDS_DEADLOOP() { volatile UINTN __i; __i = 1; while (__i); }
+#endif
+/**
+ * IDS Option Hook Points
+ *
+ * These are the values to indicate hook point in AGESA for IDS Options.
+ *
+ */
+typedef enum { //vv- for debug reference only
+ IDS_INIT_EARLY_BEFORE, ///< 00 Option Hook Point before AGESA function AMD_INIT_EARLY.
+ ///< IDS Object is initialized.
+ ///< Override CPU Core Leveling Mode.
+ ///< Set P-State in Post
+ IDS_INIT_EARLY_AFTER, ///< 01 Option Hook Point after AGESA function AMD_INIT_EARLY.
+ IDS_INIT_LATE_BEFORE, ///< 02 Option Hook Point before AGESA function AMD_INIT_LATE.
+ ///< It will be used to control the following tables.
+ ///< ACPI P-State Table (_PSS, XPSS, _PCT, _PSD, _PPC)
+ ///< ACPI WHEA Table
+ ///< DMI Table
+ IDS_INIT_LATE_AFTER, ///< 03 Option Hook Point after AGESA function AMD_INIT_LATE.
+ IDS_INIT_MID_BEFORE, ///< 04 Option Hook Point before AGESA function AMD_INIT_MID.
+ IDS_INIT_MID_AFTER, ///< 05 Option Hook Point after AGESA function AMD_INIT_MID.
+ IDS_INIT_POST_BEFORE, ///< 06 Option Hook Point before AGESA function AMD_INIT_POST.
+ ///< Control Interleaving and DRAM memory hole
+ ///< Override the setting of ECC Control
+ ///< Override the setting of Online Spare Rank
+ IDS_INIT_POST_AFTER, ///< 07 Option Hook Point after AGESA function AMD_INIT_POST.
+ IDS_INIT_RESET_BEFORE, ///< 08 Option Hook Point before AGESA function AMD_INIT_RESET.
+ IDS_INIT_RESET_AFTER, ///< 09 Option Hook Point after AGESA function AMD_INIT_RESET.
+ IDS_INIT_POST_MID, ///< 0a Option Hook Point after AGESA function AMD_INIT_POST.
+ IDS_BEFORE_S3_SAVE, ///< 0b override any settings before S3 save.
+ IDS_BEFORE_S3_RESTORE, ///< 0c override any settings before S3 restore
+ IDS_AFTER_S3_SAVE, ///< 0d Override any settings after S3 save
+ IDS_AFTER_S3_RESTORE, ///< 0e Override any settings after S3 restore
+ IDS_BEFORE_DQS_TRAINING, ///< 0f override any settings before DQS training
+ IDS_BEFORE_DRAM_INIT, ///< 10 override any settings before Dram initialization
+ IDS_BEFORE_MEM_FREQ_CHG, ///< 11 override settings before MemClk frequency change
+ IDS_BEFORE_WARM_RESET , ///< 12 Override PCI or MSR Registers Before Warm Reset
+ IDS_BEFORE_PCI_INIT, ///< 13 Override PCI or MSR Registers Before PCI Init
+ IDS_BEFORE_AP_EARLY_HALT, ///< 14 Option Hook Point before AP early halt
+ IDS_BEFORE_S3_RESUME, ///< 15 Option Hook Point before s3 resume
+ IDS_AFTER_S3_RESUME, ///< 16 Option Hook Point after s3 resume
+ IDS_BEFORE_PM_INIT, ///< 17 Option Hook Point Before Pm Init
+
+ IDS_INIT_RTB_BEFORE, ///< 18 Option Hook Point before AGESA function AMD_INIT_RTB.
+ IDS_INIT_RTB_AFTER, ///< 19 Option Hook Point after AGESA function AMD_INIT_RTB.
+
+ IDS_MT_BASE = 0x20, ///< 0x20 ~ 0x38 24 time points reserved for MTTime
+
+ IDS_PLATFORM_RSVD1 = 0x38, ///< from 0x38 to 0x3f will reserved for platform used
+ IDS_PLATFORM_RSVD2 = 0x39, ///< from 0x38 to 0x3f will reserved for platform used
+ IDS_PLATFORM_RSVD3 = 0x3a, ///< from 0x38 to 0x3f will reserved for platform used
+ IDS_PLATFORM_RSVD4 = 0x3b, ///< from 0x38 to 0x3f will reserved for platform used
+ IDS_PLATFORM_RSVD5 = 0x3c, ///< from 0x38 to 0x3f will reserved for platform used
+ IDS_PLATFORM_RSVD6 = 0x3d, ///< from 0x38 to 0x3f will reserved for platform used
+ IDS_PLATFORM_RSVD7 = 0x3e, ///< from 0x38 to 0x3f will reserved for platform used
+ IDS_PLATFORM_RSVD8 = 0x3f, ///< from 0x38 to 0x3f will reserved for platform used
+
+ // All the above timing point is used by BVM, their value should never be changed
+ IDS_INIT_DRAM_TABLE, ///< 40 Generate override table for Dram Timing
+ ///< Dram Controller, Drive Strength and DQS Timing
+ IDS_GET_DRAM_TABLE, ///< 41 Generate override table for Dram Timing
+ IDS_GANGING_MODE, ///< 42 override Memory Mode Unganged
+ IDS_POWERDOWN_MODE, ///< 43 override Power Down Mode
+ IDS_BURST_LENGTH32, ///< 44 override Burst Length32
+ IDS_ALL_MEMORY_CLOCK, ///< 45 override All Memory Clks Enable
+ IDS_ECC, ///< 46 override ECC parameter
+ IDS_ECCSYMBOLSIZE, ///< 47 override ECC symbol size
+ IDS_CPU_Early_Override, ///< 48 override CPU early parameter
+ IDS_CACHE_FLUSH_HLT, ///< 49 override Cache Flush Hlt
+ IDS_CHANNEL_INTERLEAVE, ///< 4a override Channel Interleave
+ IDS_MEM_ERROR_RECOVERY, ///< 4b override memory error recovery
+ IDS_MEM_RETRAIN_TIMES, ///< 4c override memory retrain times
+ IDS_MEM_SIZE_OVERLAY, ///< 4d Override the syslimit
+ IDS_CHECK_NEGATIVE_WL, ///< 4e Check for negative write leveling result
+ IDS_DLL_SHUT_DOWN, ///< 4f Check for Dll Shut Down
+ IDS_POR_MEM_FREQ, ///< 50 Entry to enable/disable MemClk frequency enforcement
+ IDS_PHY_DLL_STANDBY_CTRL, ///< 51 Enable/Disable Phy DLL standby feature
+ IDS_PLATFORMCFG_OVERRIDE, ///< 52 Hook for Override PlatformConfig structure
+ IDS_LOADCARD_ERROR_RECOVERY, ///< 53 Special error handling for load card support
+ IDS_MEM_IGNORE_ERROR, ///< 54 Ignore error and do not do fatal exit in memory
+ IDS_GNB_SMU_SERVICE_CONFIG, ///< 55 Config GNB SMU service
+ IDS_GNB_ORBDYNAMIC_WAKE, ///< 56 config GNB dynamic wake
+ IDS_GNB_PLATFORMCFG_OVERRIDE, ///< 57 override ids gnb platform config
+ IDS_GNB_LCLK_DPM_EN, ///< 58 override GNB LCLK DPM configuration
+ IDS_GNB_LCLK_DEEP_SLEEP, ///< 59 override GNB LCLK DPM deep sleep
+ IDS_GNB_CLOCK_GATING, ///< 5a Override GNB Clock gating config
+ IDS_NB_PSTATE_DIDVID, ///< 5b Override NB P-state settings
+ IDS_CPB_CTRL, ///< 5c Config the Core peformance boost feature
+ IDS_HTC_CTRL, ///< 5d Hook for Hardware Thermal Control
+ IDS_CC6_WORKAROUND, ///< 5e Hook for skip CC6 work around
+ IDS_MEM_MR0, ///< 5f Hook for override Memory Mr0 register
+ IDS_TRAP_TABLE, ///< 60 Hook for add IDS register table to the loop
+ IDS_NBBUFFERALLOCATIONATEARLY, ///< 61 Hook for override North bridge bufer allocation
+ IDS_BEFORE_S3_SPECIAL, ///< 62 Hook to bypass S3 special functions
+ IDS_SET_PCI_REGISTER_ENTRY, ///< 63 Hook to SetRegisterForPciEntry
+ IDS_ERRATUM463_WORKAROUND, ///< 64 Hook to Erratum 463 workaround
+ IDS_BEFORE_MEMCLR, ///< 65 Hook before set Memclr bit
+ IDS_OVERRIDE_IO_CSTATE, ///< 66 Hook for override io C-state setting
+ IDS_NBPSDIS_OVERRIDE, ///< 67 Hook for override NB pstate disable setting
+ IDS_NBPS_REG_OVERRIDE, ///< 68 Hook for override Memory NBps reg
+ IDS_MEM_PHY_POWER_SAVING, ///< 69 Hook to bypass DRAM Phy power savings
+ IDS_CST_CREATE, ///< 6a Hook for create _CST
+ IDS_CST_SIZE, ///< 6b Hook for get _CST size
+ IDS_ENFORCE_VDDIO, ///< 6c Hook to override VDDIO
+ IDS_STRETCH_FREQUENCY_LIMIT, ///< 6d Hook for enforcing memory stretch frequency limit
+ IDS_INIT_MEM_REG_TABLE, ///< 6e Hook for init memory register table
+ IDS_SKIP_FUSED_MAX_RATE, ///< 6f Hook to skip fused max rate cap
+ IDS_FCH_INIT_AT_RESET, ///< 70 Hook for FCH reset parameter
+ IDS_FCH_INIT_AT_ENV, ///< 71 Hook for FCH ENV parameter
+ IDS_ENFORCE_PLAT_TABLES, ///< 72 Hook to enforce platform specific tables
+ IDS_NBPS_MIN_FREQ, ///< 73 Hook for override MIN nb ps freq
+ IDS_GNB_FORCE_CABLESAFE, ///< 74 Hook for override Force Cable Safe
+ IDS_SKIP_PM_TRANSITION_STEP, ///< 75 Hook for provide IDS ability to skip this PM step
+ IDS_GNB_PROPERTY, ///< 76 Hook for GNB Property
+ IDS_GNB_PCIE_POWER_GATING, ///< 77 Hook for GNB PCIe Power Gating
+ IDS_MEM_DYN_DRAM_TERM, ///< 78 Hook for Override Dynamic Dram Term
+ IDS_MEM_DRAM_TERM, ///< 79 Hook for Override Dram Term
+ IDS_GNB_ALTVDDNB, ///< 7a Hook for Override AltVddNB
+ IDS_UCODE, ///< 7b Enable or Disable microcode patching
+ IDS_FAM_REG_GMMX, ///< 7c GMMX register access
+ IDS_MEMORY_POWER_POLICY, ///< 7d Memory power policy
+ IDS_GET_STRETCH_FREQUENCY_LIMIT, ///< 7e Hook for enforcing memory stretch frequency limit
+ IDS_CPU_FEAT, ///< 7f Hook for runtime force cpu feature disable
+ IDS_AFTER_DCT_PHY_ACCESS, ///< 80 Hook for DctAccessDone check
+ IDS_FORCE_PHY_TO_M0, ///< 81 Hook to bypass M0 enforcement
+ IDS_GNB_PMM_SWTJOFFSET, ///< 82 Hook to GNBSWTJOFFSET
+ IDS_LOCK_DRAM_CFG, ///< 83 Hook to BFLockDramCfg
+ IDS_BEFORE_GEN2_INIT, ///< 84 Hook to Before Gen2 Init
+ IDS_BEFORE_GPP_TRAINING, ///< 85 Hook to Before Gpp training
+ IDS_BEFORE_RECONFIGURATION, ///< 86 Hook to Before Reconfiguration
+ IDS_BEFORE_GEN3_INIT, ///< 87 Hook to Before Gen3 Init
+ IDS_BEFORE_POWER_GATING, ///< 88 Hook to Before Power Gating
+ IDS_AFTER_EARLY_INIT_ONCORE, ///< 89 Hook to after EarlyInit On Core
+ IDS_GNB_PCIE_PORT_REMAP, ///< 8a Hook to change mapping of PCIe devices
+ IDS_ECC_CONTROL, ///< 8b Enable/Disable ECC feature
+ IDS_GNB_PCIE_PHY_ISOLATION, ///< 8c Enable/Disable PCIE PHY ISOLATION
+ IDS_AFTER_RESTORING_PCI_REG, ///< 8d Hook after restoring PCI register during S3 resume
+ IDS_MSR_ACCESS_OVERRIDE, ///< 8e Hook to disable MSR access
+ IDS_REPORT_SMU_FW_VERSION, ///< 8f Hook to report SMU firmware version
+ IDS_GNB_LOAD_SAMU_PATCH, ///< 90 Hook to Load SAMU patch
+ IDS_DLLSTAGGERDLY_OVERRIDE, ///< 91 Hook to skip Dll Stagger Delay
+ IDS_CSAMPLE_TIMER, ///< 92 Hook to override CSampleTimer
+ IDS_PIPE_THROTTLE, ///< 93 Hook to override PipeThrottle
+ IDS_GNB_PMM_NATIVEGEN1PLL, ///< 94 Enable/Disable Native Gen1 PLL
+ IDS_BEFORE_PLAT_TABLES, ///< 95 Hook before processing platform specific tables
+ IDS_GNB_PCIE_MASTERPLL_SELECTION, ///< 96 Hook to override PCIe Master PLL selection
+ IDS_GNB_PCIE_PHYLANE_CONFIG, ///< 97 Hook to override PCIe PhyLane configuration
+ IDS_DSM_LP_SELECTION, ///< 98 Set Dsm low power mode
+ IDS_GNB_EQUAL_PRESET, ///< 99 Set equalization preset
+ IDS_GNB_GEN1_LOOPBACK, ///< 9a Override Gen 1 loopback mode
+ IDS_GNB_SMU_SERVICE_MASK, ///< 9b Override SMU service enablement mask
+ IDS_BEFORE_HT_MEM_MAP, ///< 9c Hook before mapping memory address space among DCTs
+ IDS_GNB_GEN3_SETTINGS_OVERRIDE, ///< 9d Hook to override Gen3 Adapt PI Offset Bypass Enable
+ IDS_GNB_TARGET_TDP, ///< 9e Hook to override Target TDP
+ IDS_GNB_SMU_PORT80_PARAMS, ///< 9f Hook to override gnb smu port80 values
+ IDS_CPU_OVERRIDE_REG_AFTER_AP_LAUNCH, ///< a0 Hook to override registers after AP lauch
+ IDS_AFTER_FEAT_MID_INIT, ///< a1 Hook to override feature setting after cpuMidInit
+ IDS_MEM_MCLK_ABOVE_NCLK, ///< a2 Hook to bypass system bandwidth for memory clock
+ IDS_ALL_MEMORY_CKE, ///< a3 override All Memory CKE
+ IDS_ALL_MEMORY_CS, ///< a4 override All Memory CS
+ IDS_NPST, ///< a5 cTDP NbPstate Selection Table
+ IDS_MEM_MRL_RETRAIN_TIMES, ///< a6 override memory MRL retrain times
+ IDS_AFTER_DQS_TRAINING, ///< a7 override any settings after DQS training
+ IDS_OVERRIDE_DIMM_MASK, ///< a8 override DimmMask for S3 data blob creation
+ IDS_BYPASS_S3_REGISTERS, ///< a9 bypass restoring certain registers
+ IDS_OPTION_END ///< AA End of IDS option
+} AGESA_IDS_OPTION;
+
+#include "OptionsIds.h"
+#include "Filecode.h"
+#include "IdsPerf.h"
+
+/* Initialize IDS controls */
+#ifndef IDSOPT_IDS_ENABLED
+ #define IDSOPT_IDS_ENABLED FALSE
+#endif
+
+#ifndef IDSOPT_CONTROL_ENABLED
+ #define IDSOPT_CONTROL_ENABLED FALSE
+#endif
+
+#ifndef IDSOPT_CONTROL_NV_TO_CMOS
+ #define IDSOPT_CONTROL_NV_TO_CMOS FALSE
+#endif
+
+#ifndef IDSOPT_TRACING_ENABLED
+ #define IDSOPT_TRACING_ENABLED FALSE
+#endif
+
+#ifndef IDSOPT_TRACE_USER_OPTIONS
+ #define IDSOPT_TRACE_USER_OPTIONS TRUE
+#endif
+
+#ifndef IDSOPT_PERF_ANALYSIS
+ #define IDSOPT_PERF_ANALYSIS FALSE
+#endif
+
+#ifndef IDSOPT_HEAP_CHECKING
+ #define IDSOPT_HEAP_CHECKING FALSE
+#endif
+
+#ifndef IDSOPT_ASSERT_ENABLED
+ #define IDSOPT_ASSERT_ENABLED FALSE
+#endif
+
+#ifndef IDSOPT_ERROR_TRAP_ENABLED
+ #define IDSOPT_ERROR_TRAP_ENABLED FALSE
+#endif
+
+#ifndef IDSOPT_CAR_CORRUPTION_CHECK_ENABLED
+ #define IDSOPT_CAR_CORRUPTION_CHECK_ENABLED FALSE
+#endif
+
+#ifndef IDSOPT_DEBUG_CODE_ENABLED
+ #define IDSOPT_DEBUG_CODE_ENABLED FALSE
+#endif
+
+#ifndef IDSOPT_IDT_EXCEPTION_TRAP
+ #define IDSOPT_IDT_EXCEPTION_TRAP FALSE
+#endif
+
+#ifndef IDSOPT_C_OPTIMIZATION_DISABLED
+ #define IDSOPT_C_OPTIMIZATION_DISABLED FALSE
+#endif
+
+#ifndef IDSOPT_TRACING_CONSOLE_HDTOUT
+ #define IDSOPT_TRACING_CONSOLE_HDTOUT TRUE
+#endif
+
+#ifndef IDSOPT_TRACING_CONSOLE_SERIALPORT
+ #define IDSOPT_TRACING_CONSOLE_SERIALPORT FALSE
+#endif
+
+#ifndef IDSOPT_TRACING_CONSOLE_REDIRECT_IO
+ #define IDSOPT_TRACING_CONSOLE_REDIRECT_IO FALSE
+#endif
+
+#ifndef IDSOPT_TRACING_CONSOLE_RAM
+ #define IDSOPT_TRACING_CONSOLE_RAM FALSE
+#endif
+
+#if IDSOPT_IDS_ENABLED == FALSE
+ #undef IDSOPT_CONTROL_ENABLED
+ #undef IDSOPT_TRACING_ENABLED
+ #undef IDSOPT_PERF_ANALYSIS
+ #undef IDSOPT_HEAP_CHECKING
+ #undef IDSOPT_ASSERT_ENABLED
+ #undef IDSOPT_ERROR_TRAP_ENABLED
+ #undef IDSOPT_CAR_CORRUPTION_CHECK_ENABLED
+ #undef IDSOPT_DEBUG_CODE_ENABLED
+ #undef IDSOPT_TRACE_USER_OPTIONS
+ #undef IDSOPT_TRACING_CONSOLE_HDTOUT
+ #undef IDSOPT_TRACING_CONSOLE_SERIALPORT
+ #undef IDSOPT_TRACING_CONSOLE_REDIRECT_IO
+ #undef IDSOPT_TRACING_CONSOLE_RAM
+
+ #define IDSOPT_CONTROL_ENABLED FALSE
+ #define IDSOPT_TRACING_ENABLED FALSE
+ #define IDSOPT_PERF_ANALYSIS FALSE
+ #define IDSOPT_HEAP_CHECKING FALSE
+ #define IDSOPT_ASSERT_ENABLED FALSE
+ #define IDSOPT_ERROR_TRAP_ENABLED FALSE
+ #define IDSOPT_CAR_CORRUPTION_CHECK_ENABLED FALSE
+ #define IDSOPT_DEBUG_CODE_ENABLED FALSE
+ #define IDSOPT_TRACE_USER_OPTIONS FALSE
+ #define IDSOPT_TRACING_CONSOLE_HDTOUT FALSE
+ #define IDSOPT_TRACING_CONSOLE_SERIALPORT FALSE
+ #define IDSOPT_TRACING_CONSOLE_REDIRECT_IO FALSE
+ #define IDSOPT_TRACING_CONSOLE_RAM FALSE
+#endif
+
+//Disable when master token Tracing is set to FALSE
+#if (IDSOPT_TRACING_ENABLED == FALSE) || (defined (IDSOPT_CUSTOMIZE_TRACING_SERVICE))
+ #undef IDSOPT_TRACING_CONSOLE_HDTOUT
+ #define IDSOPT_TRACING_CONSOLE_HDTOUT FALSE
+
+ #undef IDSOPT_TRACING_CONSOLE_SERIALPORT
+ #define IDSOPT_TRACING_CONSOLE_SERIALPORT FALSE
+
+ #undef IDSOPT_TRACING_CONSOLE_REDIRECT_IO
+ #define IDSOPT_TRACING_CONSOLE_REDIRECT_IO FALSE
+
+ #undef IDSOPT_TRACING_CONSOLE_RAM
+ #define IDSOPT_TRACING_CONSOLE_RAM FALSE
+#endif
+
+//Disable Tracing if all support HW layer set to FALSE
+#if ((IDSOPT_TRACING_CONSOLE_HDTOUT == FALSE) && (IDSOPT_TRACING_CONSOLE_SERIALPORT == FALSE) && (IDSOPT_TRACING_CONSOLE_REDIRECT_IO == FALSE) && (IDSOPT_TRACING_CONSOLE_RAM == FALSE))
+ #ifndef IDSOPT_CUSTOMIZE_TRACING_SERVICE
+ #undef IDSOPT_TRACING_ENABLED
+ #define IDSOPT_TRACING_ENABLED FALSE
+ #endif
+#endif
+/**
+ * Make a Progress Report to the User.
+ *
+ * This Macro is always enabled. The default action is to write the TestPoint value
+ * to an I/O port. The I/O port is 8 bits in size and the default address is 0x80.
+ * IBVs can change AGESA's default port by defining IDS_DEBUG_PORT to desired port
+ * in OptionsIds.h in their build tip.
+ *
+ * @param[in] TestPoint The value for display indicating progress
+ * @param[in,out] StdHeader Pointer of AMD_CONFIG_PARAMS
+ *
+ **/
+
+#define AGESA_TESTPOINT(TestPoint, StdHeader) IdsAgesaTestPoint ((TestPoint), (StdHeader))
+
+#ifndef IDS_DEBUG_PORT
+ #define IDS_DEBUG_PORT 0x80
+#endif
+
+#if IDS_DEBUG_PORT > 0xFFFFul
+ #error "Invalid debug port defined. IDS_DEBUG_PORT address must not be larger than 16 bits."
+#endif
+
+#ifndef IDS_DEBUG_PORT_SIZE_IN_BYTES
+ #define IDS_DEBUG_PORT_SIZE_IN_BYTES 4
+#endif
+
+#if IDS_DEBUG_PORT_SIZE_IN_BYTES == 1
+ #define IDS_DEBUG_PORT_ACCESSWIDTH AccessWidth8
+ #ifndef IDS_DEBUG_TP_PREFIX
+ #define IDS_DEBUG_TP_PREFIX 0x00ul
+ #endif
+ #if IDS_DEBUG_TP_PREFIX != 0
+ #error "Invalid debug port prefix defined. IDS_DEBUG_TP_PREFIX << 8 must not exceed IDS_DEBUG_PORT_SIZE_IN_BYTES."
+ #endif
+#else
+ #if IDS_DEBUG_PORT_SIZE_IN_BYTES == 2
+ #define IDS_DEBUG_PORT_ACCESSWIDTH AccessWidth16
+ #ifndef IDS_DEBUG_TP_PREFIX
+ #define IDS_DEBUG_TP_PREFIX 0xA0ul
+ #endif
+ #if IDS_DEBUG_TP_PREFIX > 0xFFul
+ #error "Invalid debug port prefix defined. IDS_DEBUG_TP_PREFIX << 8 must not exceed IDS_DEBUG_PORT_SIZE_IN_BYTES."
+ #endif
+ #else
+ #if IDS_DEBUG_PORT_SIZE_IN_BYTES == 4
+ #define IDS_DEBUG_PORT_ACCESSWIDTH AccessWidth32
+ #ifndef IDS_DEBUG_TP_PREFIX
+ #define IDS_DEBUG_TP_PREFIX 0xA9E5A0ul
+ #endif
+ #if IDS_DEBUG_TP_PREFIX > 0xFFFFFFul
+ #error "Invalid debug port prefix defined. IDS_DEBUG_TP_PREFIX << 8 must not exceed IDS_DEBUG_PORT_SIZE_IN_BYTES."
+ #endif
+ #else
+ #error "Invalid debug port size defined. Acceptable values of IDS_DEBUG_PORT_SIZE_IN_BYTES are 1, 2, or 4."
+ #endif
+ #endif
+#endif
+
+#if (IDS_DEBUG_PORT & (IDS_DEBUG_PORT_SIZE_IN_BYTES - 1)) != 0
+ #error "IDS_DEBUG_PORT must be aligned on IDS_DEBUG_PORT_SIZE_IN_BYTES boundary."
+#endif
+
+/**
+ * @def STOP_HERE
+ * (macro) - Causes program to halt. This is @b only for use during active debugging .
+ *
+ * Causes the program to halt and display the file number of the source of the
+ * halt (displayed in decimal).
+ *
+ **/
+#if IDSOPT_IDS_ENABLED == TRUE
+ #ifdef STOP_CODE
+ #undef STOP_CODE
+ #endif
+ #define STOP_CODE (((UINT32)FILECODE)*0x10000ul + \
+ ((__LINE__) % 10) + (((__LINE__ / 10) % 10)*0x10) + \
+ (((__LINE__ / 100) % 10)*0x100) + (((__LINE__ / 1000) % 10)*0x1000))
+ #define STOP_HERE IdsErrorStop (STOP_CODE);
+#else
+ #define STOP_HERE STOP_HERE_Needs_To_Be_Removed //"WARNING: Debug code needs to be removed for production builds."
+#endif
+
+/**
+ * @def ASSERT
+ * Test an assertion that the given statement is True.
+ *
+ * The statement is evaluated to a boolean value. If the statement is True,
+ * then no action is taken (no error). If the statement is False, a error stop
+ * is generated to halt the program. Used for testing for fatal errors that
+ * must be resolved before production. This is used to do parameter checks,
+ * bounds checking, range checks and 'sanity' checks.
+ *
+ * @param[in] conditional Assert that evaluating this conditional results in TRUE.
+ *
+ **/
+#ifndef ASSERT
+ #if IDSOPT_ASSERT_ENABLED == TRUE
+ #ifdef STOP_CODE
+ #undef STOP_CODE
+ #endif
+ #define STOP_CODE (((UINT32)FILECODE)*0x10000ul + \
+ ((__LINE__) % 10) + (((__LINE__ / 10) % 10)*0x10) + \
+ (((__LINE__ / 100) % 10)*0x100) + (((__LINE__ / 1000) % 10)*0x1000))
+
+ #define ASSERT(conditional) ((conditional) ? 0 : IdsAssert (STOP_CODE));
+ #else
+ #define ASSERT(conditional)
+ #endif
+#endif
+
+#if IDSOPT_CAR_CORRUPTION_CHECK_ENABLED == TRUE
+ #undef IDSOPT_ERROR_TRAP_ENABLED
+ #define IDSOPT_ERROR_TRAP_ENABLED TRUE
+ #define IDS_CAR_CORRUPTION_CHECK(StdHeader) IdsCarCorruptionCheck(StdHeader)
+#else
+ #define IDS_CAR_CORRUPTION_CHECK(StdHeader)
+#endif
+/**
+ * @def DEBUG_CODE
+ * Make the code active when IDSOPT_DEBUG_CODE_ENABLED enable
+ *
+ */
+#ifndef DEBUG_CODE
+ #if IDSOPT_DEBUG_CODE_ENABLED == TRUE
+ #define DEBUG_CODE(Code) Code
+ #else
+ #define DEBUG_CODE(Code)
+ #endif
+#endif
+
+/**
+ * @def IDS_ERROR_TRAP
+ * Trap AGESA Error events with stop code display.
+ *
+ * Works similarly to use of "ASSERT (FALSE);"
+ *
+ */
+#if IDSOPT_ERROR_TRAP_ENABLED == TRUE
+ #ifdef STOP_CODE
+ #undef STOP_CODE
+ #endif
+ #define STOP_CODE (((UINT32)FILECODE)*0x10000ul + \
+ ((__LINE__) % 10) + (((__LINE__ / 10) % 10)*0x10) + \
+ (((__LINE__ / 100) % 10)*0x100) + (((__LINE__ / 1000) % 10)*0x1000))
+
+ #define IDS_ERROR_TRAP IdsErrorStop (STOP_CODE)
+#else
+ #define IDS_ERROR_TRAP
+#endif
+
+///give the extended Macro default value
+#ifndef __IDS_EXTENDED__
+ #define IDS_EXTENDED_HOOK(idsoption, dataptr, idsnvptr, stdheader) IDS_SUCCESS
+ #define IDS_TRACE_DEFAULT (0)
+ #define IDS_INITIAL_F15_CZ_PM_STEP
+ #define IDS_F15_CZ_PM_CUSTOM_STEP
+ #define IDS_EXTENDED_GET_DATA_EARLY(data, StdHeader)
+ #define IDS_EXTENDED_GET_DATA_LATE(data, StdHeader)
+ #define IDS_EXTENDED_HEAP_SIZE 0
+ #define IDS_EXT_INCLUDE_F15(file)
+ #define IDS_EXT_INCLUDE(file)
+ #define IDS_PAD_4K
+ #define IDS_EXTENDED_CODE(code)
+ #define SMU_FIRMWARE_PADS_1K
+#endif
+
+#ifndef IDS_NUM_NV_ITEM
+ #define IDS_NUM_NV_ITEM (IDS_NUM_EXT_NV_ITEM)
+#endif
+
+#define IDS_CMOS_INDEX_PORT 0x70
+#define IDS_CMOS_DATA_PORT 0x71
+#define IDS_CMOS_REGION_START 0x20
+#define IDS_CMOS_REGION_END 0x7F
+#define IDS_AP_GET_NV_FROM_CMOS(x) FALSE
+
+#if IDSOPT_CONTROL_ENABLED == TRUE
+ #define IDS_OPTION_HOOK(IdsOption, DataPtr, StdHeader) \
+ AmdIdsCtrlDispatcher ((IdsOption), (DataPtr), (StdHeader))
+
+ #define IDS_OPTION_CALLOUT(CallOutId, DataPtr, StdHeader) \
+ IdsOptionCallout ((CallOutId), (DataPtr), (StdHeader))
+ #if IDSOPT_CONTROL_NV_TO_CMOS == TRUE
+ #undef IDS_AP_GET_NV_FROM_CMOS
+ #define IDS_AP_GET_NV_FROM_CMOS(x) AmdIdsApGetNvFromCmos(x)
+ #ifdef IDS_OPT_CMOS_INDEX_PORT
+ #undef IDS_CMOS_INDEX_PORT
+ #define IDS_CMOS_INDEX_PORT IDS_OPT_CMOS_INDEX_PORT
+ #endif
+
+ #ifdef IDS_OPT_CMOS_DATA_PORT
+ #undef IDS_CMOS_DATA_PORT
+ #define IDS_CMOS_DATA_PORT IDS_OPT_CMOS_DATA_PORT
+ #endif
+
+ #ifdef IDS_OPT_CMOS_REGION_START
+ #undef IDS_CMOS_REGION_START
+ #define IDS_CMOS_REGION_START IDS_OPT_CMOS_REGION_START
+ #endif
+
+ #ifdef IDS_OPT_CMOS_REGION_END
+ #undef IDS_CMOS_REGION_END
+ #define IDS_CMOS_REGION_END IDS_OPT_CMOS_REGION_END
+ #endif
+ #endif
+#else
+ #define IDS_OPTION_HOOK(IdsOption, DataPtr, StdHeader)
+
+ #define IDS_OPTION_CALLOUT(CallOutId, DataPtr, StdHeader) AGESA_SUCCESS
+#endif
+
+/**
+ * Macro to add a *skip* hook for IDS options
+ *
+ * The default minimal action is to do nothing and there is no any code to increase.
+ * For debug environments, IDS dispatcher function will be called to perform
+ * the detailed action and to skip AGESA code if necessary.
+ *
+ * @param[in] IdsOption IDS Option ID for this hook point
+ * @param[in, out] DataPtr Data Pointer to override
+ * @param[in, out] StdHeader Pointer of AMD_CONFIG_PARAMS
+ *
+ *
+ **/
+
+#if IDSOPT_CONTROL_ENABLED == TRUE
+ #define IDS_SKIP_HOOK(IdsOption, DataPtr, StdHeader) \
+ if (AmdIdsCtrlDispatcher (IdsOption, DataPtr, StdHeader) == IDS_SUCCESS)
+#else
+ #define IDS_SKIP_HOOK(IdsOption, DataPtr, StdHeader)
+#endif
+
+/**
+ * Macro to add a heap manager routine
+ *
+ * when memory is allocated the heap manager actually allocates two extra dwords of data,
+ * one dword buffer before the actual memory, and one dword afterwards.
+ * a complete heap walk and check to be performed at any time.
+ * it would ASSERT if the heap is corrupt
+ *
+ * @param[in] StdHeader Pointer of AMD_CONFIG_PARAMS
+ *
+ *
+ **/
+
+// Heap debug feature
+#define SENTINEL_BEFORE_VALUE 0x64616548ul // "Head"
+#define SENTINEL_AFTER_VALUE 0x6C696154ul // "Tail"
+#if IDSOPT_IDS_ENABLED == TRUE
+ #if IDSOPT_HEAP_CHECKING == TRUE
+ #define SIZE_OF_SENTINEL 4
+ #define NUM_OF_SENTINEL 2 // Before ("Head") and After ("Tail")
+ #define SET_SENTINEL_BEFORE(NodePtr, AlignTo16Byte) (*(UINT32 *) ((UINT8 *) NodePtr + sizeof (BUFFER_NODE) + AlignTo16Byte) = SENTINEL_BEFORE_VALUE);
+ #define SET_SENTINEL_AFTER(NodePtr) (*(UINT32 *) ((UINT8 *) NodePtr + sizeof (BUFFER_NODE) + NodePtr->BufferSize - SIZE_OF_SENTINEL) = SENTINEL_AFTER_VALUE);
+ #define Heap_Check(stdheader) AmdHeapIntactCheck(stdheader)
+ #else
+ #define SIZE_OF_SENTINEL 0
+ #define NUM_OF_SENTINEL 0
+ #define SET_SENTINEL_BEFORE(NodePtr, AlignTo16Byte)
+ #define SET_SENTINEL_AFTER(NodePtr)
+ #define Heap_Check(stdheader)
+ #endif
+#else
+ #define SIZE_OF_SENTINEL 0
+ #define NUM_OF_SENTINEL 0
+ #define SET_SENTINEL_BEFORE(NodePtr, AlignTo16Byte)
+ #define SET_SENTINEL_AFTER(NodePtr)
+ #define Heap_Check(stdheader)
+#endif
+
+/**
+ * Macro to add IDT for debugging exception.
+ *
+ * A debug feature. Adding a 'jmp $' into every exception handler.
+ * So debugger could use HDT to skip 'jmp $' and execute the iret,
+ * then they could find which instruction cause the exception.
+ *
+ * @param[in] FunctionId IDS Function ID for this hook point
+ * @param[in, out] DataPtr Data Pointer to override
+ * @param[in, out] StdHeader Pointer of AMD_CONFIG_PARAMS
+ *
+ *
+ **/
+#if IDSOPT_IDS_ENABLED == TRUE
+ #if IDSOPT_IDT_EXCEPTION_TRAP == TRUE
+ #define IDS_EXCEPTION_TRAP(FunctionId, DataPtr, StdHeader) IdsExceptionTrap (FunctionId, DataPtr, StdHeader)
+ #else
+ #define IDS_EXCEPTION_TRAP(FunctionId, DataPtr, StdHeader)
+ #endif
+#else
+ #define IDS_EXCEPTION_TRAP(FunctionId, DataPtr, StdHeader)
+#endif
+
+
+ //Note a is from 0 to 63
+#define DEBUG_PRINT_SHIFT(a) ((UINT64)1 << a)
+//If you change the Bitmap definition below, please change the Hash in ParseFilter of hdtout2008.pl accordingly
+//Memory Masks
+#define MEM_SETREG DEBUG_PRINT_SHIFT (0)
+#define MEM_GETREG DEBUG_PRINT_SHIFT (1)
+#define MEM_FLOW DEBUG_PRINT_SHIFT (2)
+#define MEM_STATUS DEBUG_PRINT_SHIFT (3)
+#define MEM_UNDEF_BF DEBUG_PRINT_SHIFT (4)
+#define MEMORY_TRACE_RSV2 DEBUG_PRINT_SHIFT (5)
+#define MEMORY_TRACE_RSV3 DEBUG_PRINT_SHIFT (6)
+#define MEMORY_TRACE_RSV4 DEBUG_PRINT_SHIFT (7)
+#define MEMORY_TRACE_RSV5 DEBUG_PRINT_SHIFT (8)
+#define MEMORY_TRACE_RSV6 DEBUG_PRINT_SHIFT (9)
+
+//CPU Masks
+#define CPU_TRACE DEBUG_PRINT_SHIFT (10)
+#define CPU_TRACE_RSV1 DEBUG_PRINT_SHIFT (11)
+#define CPU_TRACE_RSV2 DEBUG_PRINT_SHIFT (12)
+#define CPU_TRACE_RSV3 DEBUG_PRINT_SHIFT (13)
+#define CPU_TRACE_RSV4 DEBUG_PRINT_SHIFT (14)
+#define CPU_TRACE_RSV5 DEBUG_PRINT_SHIFT (15)
+#define CPU_TRACE_RSV6 DEBUG_PRINT_SHIFT (16)
+#define CPU_TRACE_RSV7 DEBUG_PRINT_SHIFT (17)
+#define CPU_TRACE_RSV8 DEBUG_PRINT_SHIFT (18)
+#define CPU_TRACE_RSV9 DEBUG_PRINT_SHIFT (19)
+
+//GNB Masks
+#define GNB_TRACE DEBUG_PRINT_SHIFT (20)
+#define PCIE_MISC DEBUG_PRINT_SHIFT (21)
+#define PCIE_PORTREG_TRACE DEBUG_PRINT_SHIFT (22)
+#define PCIE_HOSTREG_TRACE DEBUG_PRINT_SHIFT (23)
+#define GNB_TRACE_RSV2 DEBUG_PRINT_SHIFT (24)
+#define NB_MISC DEBUG_PRINT_SHIFT (25)
+#define GNB_TRACE_RSV3 DEBUG_PRINT_SHIFT (26)
+#define GFX_MISC DEBUG_PRINT_SHIFT (27)
+#define NB_SMUREG_TRACE DEBUG_PRINT_SHIFT (28)
+#define GNB_TRACE_RSV1 DEBUG_PRINT_SHIFT (29)
+
+//Topology Masks
+#define TOPO_TRACE DEBUG_PRINT_SHIFT (30)
+#define TOPO_TRACE_RSV1 DEBUG_PRINT_SHIFT (31)
+#define TOPO_TRACE_RSV2 DEBUG_PRINT_SHIFT (32)
+#define TOPO_TRACE_RSV3 DEBUG_PRINT_SHIFT (33)
+#define TOPO_TRACE_RSV4 DEBUG_PRINT_SHIFT (34)
+#define TOPO_TRACE_RSV5 DEBUG_PRINT_SHIFT (35)
+#define TOPO_TRACE_RSV6 DEBUG_PRINT_SHIFT (36)
+#define TOPO_TRACE_RSV7 DEBUG_PRINT_SHIFT (37)
+#define TOPO_TRACE_RSV8 DEBUG_PRINT_SHIFT (38)
+#define TOPO_TRACE_RSV9 DEBUG_PRINT_SHIFT (39)
+
+//FCH Masks
+#define FCH_TRACE DEBUG_PRINT_SHIFT (40)
+#define FCH_TRACE_RSV1 DEBUG_PRINT_SHIFT (41)
+#define FCH_TRACE_RSV2 DEBUG_PRINT_SHIFT (42)
+#define FCH_TRACE_RSV3 DEBUG_PRINT_SHIFT (43)
+#define FCH_TRACE_RSV4 DEBUG_PRINT_SHIFT (44)
+#define FCH_TRACE_RSV5 DEBUG_PRINT_SHIFT (45)
+#define FCH_TRACE_RSV6 DEBUG_PRINT_SHIFT (46)
+#define FCH_TRACE_RSV7 DEBUG_PRINT_SHIFT (47)
+#define FCH_TRACE_RSV8 DEBUG_PRINT_SHIFT (48)
+#define FCH_TRACE_RSV9 DEBUG_PRINT_SHIFT (49)
+
+//Other Masks
+#define MAIN_FLOW DEBUG_PRINT_SHIFT (50)
+#define EVENT_LOG DEBUG_PRINT_SHIFT (51)
+#define PERFORMANCE_ANALYSE DEBUG_PRINT_SHIFT (52)
+
+//Ids Masks
+#define IDS_TRACE DEBUG_PRINT_SHIFT (53)
+#define BVM_TRACE DEBUG_PRINT_SHIFT (54)
+#define IDS_TRACE_RSV2 DEBUG_PRINT_SHIFT (55)
+#define IDS_TRACE_RSV3 DEBUG_PRINT_SHIFT (56)
+
+//S3
+#define S3_TRACE DEBUG_PRINT_SHIFT (57)
+
+//Library function to read/write PCI/MSR registers
+#define LIB_PCI_RD DEBUG_PRINT_SHIFT (58)
+#define LIB_PCI_WR DEBUG_PRINT_SHIFT (59)
+
+//AGESA test points
+#define TEST_POINT DEBUG_PRINT_SHIFT (60)
+
+//Reserved for platform log
+#define PLAT_RSV1 DEBUG_PRINT_SHIFT (61)
+#define PLAT_RSV2 DEBUG_PRINT_SHIFT (62)
+#define PLAT_RSV3 DEBUG_PRINT_SHIFT (63)
+
+#define GNB_TRACE_DEFAULT\
+ (\
+ GNB_TRACE | PCIE_MISC | NB_MISC | GFX_MISC \
+ )
+
+#define GNB_TRACE_REG\
+ (\
+ PCIE_PORTREG_TRACE | PCIE_HOSTREG_TRACE | \
+ NB_SMUREG_TRACE | GNB_TRACE_RSV1 \
+ )
+
+#define GNB_TRACE_ALL\
+ (\
+ GNB_TRACE_DEFAULT | GNB_TRACE_REG \
+ )
+
+#define CPU_TRACE_ALL\
+ (\
+ CPU_TRACE | CPU_TRACE_RSV1 | CPU_TRACE_RSV2 | CPU_TRACE_RSV3 | \
+ CPU_TRACE_RSV4 | CPU_TRACE_RSV5 | CPU_TRACE_RSV6 | CPU_TRACE_RSV7 | \
+ CPU_TRACE_RSV8 | CPU_TRACE_RSV9\
+ )
+
+#define MEMORY_TRACE_ALL\
+ (\
+ MEM_FLOW | MEM_GETREG | MEM_SETREG | MEM_STATUS | \
+ MEMORY_TRACE_RSV1 | MEMORY_TRACE_RSV2 | MEMORY_TRACE_RSV3 | MEMORY_TRACE_RSV4 | \
+ MEMORY_TRACE_RSV5 | MEMORY_TRACE_RSV6\
+ )
+
+#define TOPO_TRACE_ALL\
+ (\
+ TOPO_TRACE | TOPO_TRACE_RSV1 | TOPO_TRACE_RSV2 | TOPO_TRACE_RSV3 | \
+ TOPO_TRACE_RSV4 | TOPO_TRACE_RSV5 | TOPO_TRACE_RSV6 | TOPO_TRACE_RSV7 | \
+ TOPO_TRACE_RSV8 | TOPO_TRACE_RSV9\
+ )
+
+#define FCH_TRACE_ALL\
+ (\
+ FCH_TRACE | FCH_TRACE_RSV1 | FCH_TRACE_RSV2 | FCH_TRACE_RSV3 | \
+ FCH_TRACE_RSV4 | FCH_TRACE_RSV5 | FCH_TRACE_RSV6 | FCH_TRACE_RSV7 | \
+ FCH_TRACE_RSV8 | FCH_TRACE_RSV9\
+ )
+
+#define IDS_TRACE_ALL\
+ (\
+ IDS_TRACE | BVM_TRACE | IDS_TRACE_RSV2 | IDS_TRACE_RSV3\
+ )
+
+#define OTHER_TRACE_ALL\
+ (\
+ MAIN_FLOW | EVENT_LOG | PERFORMANCE_ANALYSE\
+ )
+
+
+#define TRACE_MASK_ALL (0xFFFFFFFFFFFFFFFFull)
+#ifndef IDS_DEBUG_PRINT_MASK
+ #define IDS_DEBUG_PRINT_MASK (GNB_TRACE_DEFAULT | CPU_TRACE_ALL | MEM_FLOW | MEM_STATUS | TOPO_TRACE_ALL | FCH_TRACE_ALL | MAIN_FLOW | IDS_TRACE_DEFAULT | TEST_POINT | MEM_GETREG)
+#endif
+
+/// if no specific define INIT & EXIT will be NULL
+#define IDS_HDT_CONSOLE_INIT(x)
+#define IDS_HDT_CONSOLE_EXIT(x)
+
+/// AGESA tracing service
+#if IDSOPT_TRACING_ENABLED == TRUE
+ #ifdef VA_ARGS_SUPPORTED
+ #if IDSOPT_C_OPTIMIZATION_DISABLED == TRUE
+ #define IDS_HDT_CONSOLE(f, s, ...) AmdIdsDebugPrint (f, s, __VA_ARGS__)
+ #else
+ #pragma warning(disable: 4127)
+ #define IDS_HDT_CONSOLE(f, s, ...) if (f == MEM_FLOW) AmdIdsDebugPrintMem (s, __VA_ARGS__); \
+ else if (f == CPU_TRACE) AmdIdsDebugPrintCpu (s, __VA_ARGS__); \
+ else if (f == TOPO_TRACE) AmdIdsDebugPrintTopology (s, __VA_ARGS__); \
+ else if (f == GNB_TRACE) AmdIdsDebugPrintGnb (s, __VA_ARGS__); \
+ else AmdIdsDebugPrint (f, s, __VA_ARGS__)
+ #endif
+ #else
+ #define IDS_HDT_CONSOLE AmdIdsDebugPrint
+ #endif
+ #define CONSOLE AmdIdsDebugPrintAll
+ #define IDS_HDT_CONSOLE_DEBUG_CODE(Code) Code
+ #define IDS_TIMEOUT_CTL(t) IdsMemTimeOut (t)
+#else
+ #define IDS_HDT_CONSOLE 1 ? (VOID) 0 : AmdIdsDebugPrint
+ #define IDS_HDT_CONSOLE_DEBUG_CODE(Code)
+ #define CONSOLE CONSOLE_Needs_To_Be_Removed_For_Production_Build //"WARNING: CONSOLE needs to be removed for production builds."
+ #define IDS_TIMEOUT_CTL(t)
+#endif
+
+/// Macros for serial port tracing
+#ifdef IDSOPT_SERIAL_PORT
+ #define IDS_SERIAL_PORT IDSOPT_SERIAL_PORT
+#endif
+
+#ifndef IDS_SERIAL_PORT
+ #define IDS_SERIAL_PORT 0x3F8
+#endif
+
+// Macros for redirect IO tracing
+#ifdef IDSOPT_DEBUG_PRINT_IO_PORT
+ #define IDS_DEBUG_PRINT_IO_PORT IDSOPT_DEBUG_PRINT_IO_PORT
+#endif
+
+#ifndef IDS_DEBUG_PRINT_IO_PORT
+ #define IDS_DEBUG_PRINT_IO_PORT 0x80
+#endif
+
+#define IDS_DPRAM_BASE 0
+#define IDS_DPRAM_SIZE 0
+///Default policy, shift the old data when buffer full
+#define IDS_DPRAM_STOP_LOGGING_WHEN_BUFFER_FULL FALSE
+#if IDSOPT_TRACING_CONSOLE_RAM == TRUE
+ #ifdef IDSOPT_DPRAM_BASE
+ #undef IDS_DPRAM_BASE
+ #define IDS_DPRAM_BASE IDSOPT_DPRAM_BASE
+ #else
+ #error "Debug Print Ram Base not specified, please define IDSOPT_DPRAM_BASE in optionsids.h"
+ #endif
+
+ #ifdef IDSOPT_DPRAM_SIZE
+ #undef IDS_DPRAM_SIZE
+ #define IDS_DPRAM_SIZE IDSOPT_DPRAM_SIZE
+ #else
+ #error "Debug Print Ram size not specified, please define IDSOPT_DPRAM_SIZE in optionsids.h"
+ #endif
+
+ #ifdef IDSOPT_DPRAM_STOP_LOGGING_WHEN_BUFFER_FULL
+ #define IDS_DPRAM_STOP_LOGGING_WHEN_BUFFER_FULL IDSOPT_DPRAM_STOP_LOGGING_WHEN_BUFFER_FULL
+ #endif
+#endif
+/**
+ * Macros to add HDT OUT
+ *
+ * The default minimal action is to do nothing and there is no any code to increase.
+ * For debug environments, the debug information can be displayed in HDT or other
+ * devices.
+ *
+ **/
+#if IDSOPT_TRACING_CONSOLE_HDTOUT == TRUE
+ #undef IDS_HDT_CONSOLE_INIT
+ #undef IDS_HDT_CONSOLE_EXIT
+ #define IDS_HDT_CONSOLE_INIT(x) AmdIdsHdtOutInit (x)
+ #define IDS_HDT_CONSOLE_EXIT(x) AmdIdsHdtOutExit (x)
+ #define IDS_HDT_CONSOLE_S3_EXIT(x) AmdIdsHdtOutS3Exit (x)
+ #define IDS_HDT_CONSOLE_S3_AP_EXIT(x) AmdIdsHdtOutS3ApExit (x)
+
+ #define IDS_HDT_CONSOLE_FLUSH_BUFFER(x) AmdIdsHdtOutBufferFlush (x)
+ #define IDS_HDT_CONSOLE_ASSERT(x) AmdIdsDebugPrintAssert (x)
+ #define IDS_FUNCLIST_ADDR ScriptFuncList
+ #define IDS_FUNCLIST_EXTERN() extern SCRIPT_FUNCTION ScriptFuncList[]
+#else
+ #define IDS_HDT_CONSOLE_S3_EXIT(x)
+ #define IDS_HDT_CONSOLE_S3_AP_EXIT(x)
+ #define IDS_HDT_CONSOLE_FLUSH_BUFFER(x)
+ #define IDS_HDT_CONSOLE_ASSERT(x)
+ #define IDS_FUNCLIST_ADDR NULL
+ #define IDS_FUNCLIST_EXTERN()
+#endif
+
+#if IDSOPT_TRACING_ENABLED == TRUE
+ #ifdef IDSOPT_CUSTOMIZE_TRACING_SERVICE
+ #undef IDS_HDT_CONSOLE
+ #define IDS_HDT_CONSOLE IDSOPT_CUSTOMIZE_TRACING_SERVICE
+ #endif
+ #ifdef IDSOPT_CUSTOMIZE_TRACING_SERVICE_INIT
+ #undef IDS_HDT_CONSOLE_INIT
+ #define IDS_HDT_CONSOLE_INIT(x) IDSOPT_CUSTOMIZE_TRACING_SERVICE_INIT (x)
+ #endif
+ #ifdef IDSOPT_CUSTOMIZE_TRACING_SERVICE_EXIT
+ #undef IDS_HDT_CONSOLE_EXIT
+ #define IDS_HDT_CONSOLE_EXIT(x) IDSOPT_CUSTOMIZE_TRACING_SERVICE_EXIT (x)
+ #endif
+#endif
+
+#define IDS_TRACE_SHOW_BLD_OPT_CFG IDSOPT_TRACE_USER_OPTIONS
+
+#if IDSOPT_PERF_ANALYSIS == TRUE
+ #include "IdsPerf.h"
+ #ifdef STOP_CODE
+ #undef STOP_CODE
+ #endif
+ #define STOP_CODE (((UINT32)FILECODE)*0x10000ul + \
+ ((__LINE__) % 10) + (((__LINE__ / 10) % 10)*0x10) + \
+ (((__LINE__ / 100) % 10)*0x100) + (((__LINE__ / 1000) % 10)*0x1000))
+
+ #define IDS_PERF_TIMESTAMP(ID, StdHeader) IdsPerfTimestamp (STOP_CODE, ID, (StdHeader))
+ #define IDS_PERF_ANALYSE(StdHeader) IdsPerfAnalyseTimestamp (StdHeader)
+#else
+ #define IDS_PERF_TIMESTAMP(ID, StdHeader)
+ #define IDS_PERF_ANALYSE(StdHeader)
+#endif
+
+///For IDS feat use
+#define IDS_FAMILY_ALL 0xFFFFFFFFFFFFFFFFull
+#define IDS_BSP_ONLY TRUE
+#define IDS_ALL_CORES FALSE
+
+#define IDS_LATE_RUN_AP_TASK_ID PROC_IDS_LIBRARY_IDSLIB_FILECODE
+
+#define IDS_CALLOUT_INIT 0x01 ///< The function data of IDS callout function of initialization.
+
+#define IDS_CALLOUT_GNB_PPFUSE_OVERRIDE 0x83 ///< The function data of IDS callout function of GNB pp fuse table.
+#define IDS_CALLOUT_GNB_INTEGRATED_TABLE_CONFIG 0x84 ///< The function data of IDS callout function of GNB integrated table.
+#define IDS_CALLOUT_GNB_NB_POWERGATE_CONFIG 0x85 ///< The function data of IDS callout function of GNB NB power gate config.
+#define IDS_CALLOUT_GNB_PCIE_POWERGATE_CONFIG 0x86 ///< The function data of IDS callout function of GNB PCIE power gateconfig.
+#define IDS_CALLOUT_GNB_PCIE_PLATFORM_CONFIG 0x87 ///< The function data of IDS callout function of GNB pcie platform config.
+#define IDS_CALLOUT_GNB_PCIE_PHY_CONFIG 0x88 ///< The function data of IDS callout function of GNB pcie PHY config.
+#define IDS_CALLOUT_GNB_GMM_REGISTER_OVERRIDE 0x89 ///< The function data of IDS callout function of GNB GMM register override
+#define IDS_CALLOUT_FCH_INIT_RESET 0x8A ///< The function data of IDS callout function of FchInitReset
+#define IDS_CALLOUT_FCH_INIT_ENV 0x8B ///< The function data of IDS callout function of FchInitEnv.
+#define IDS_CALLOUT_POWER_PLAN_INIT 0x8C ///< The function data of IDS callout function of Override Power Plan Init
+#define IDS_CALLOUT_GET_PERF_BUFFER 0x8D ///< The function data of IDS callout function of get platform performance buffer.
+#define IDS_CALLOUT_GNB_PACKAGE_POWER_CONFIG 0x8E ///< The function data of IDS callout function of Bapm Package Power.
+#define IDS_CALLOUT_SMU_PORT80_LOGGING_BUFFER 0x8F ///< The function data of IDS callout function of SMU port80 logging buffer.
+#define IDS_CALLOUT_GNB_BEFORE_EARLY_INIT 0x90 ///< The function data of IDS callout function of GNB before early init.
+#define IDS_CALLOUT_GNB_SMUBIOSTABLE_OVERRIDE 0x91 ///< The function data of IDS callout function of GNB smu bios table.
+#define IDS_CALLOUT_GNB_PCIE_AER_CONFIG 0x92 ///< The function data of IDS callout function of GNB PCIE AER config.
+#define IDS_CALLOUT_GNB_PCIE_EARLY_PORT_CONFIG 0x93 ///< The function data of IDS callout function of GNB pcie early port config.
+#define IDS_CALLOUT_GNB_BUILDOPTIONS_OVERRIDE 0x94 ///< The function data of IDS callout function of GNB build options override.
+#define IDS_CALLOUT_GNB_SMUFEATURES_MASK_OVERRIDE 0x95 ///< The function data of IDS callout function of GNB SMU Features MASK override.
+#define IDS_CALLOUT_GNB_BEFORE_TXPRESET_LOADING 0x96 ///< The function data of IDS callout function of GNB pcie Tx preset loading sequence.
+
+/// Function entry for HDT script to call
+typedef struct _SCRIPT_FUNCTION {
+ UINT32 FuncAddr; ///< Function address in ROM
+ CHAR8 FuncName[40]; ///< Function name
+} SCRIPT_FUNCTION;
+
+/// Data Structure for Mem ECC parameter override
+typedef struct {
+ IN BOOLEAN CfgEccRedirection; ///< ECC Redirection
+ IN UINT16 CfgScrubDramRate; ///< Scrub Dram Rate
+ IN UINT16 CfgScrubL2Rate; ///< Scrub L2Rate
+ IN UINT16 CfgScrubL3Rate; ///< Scrub L3Rate
+ IN UINT16 CfgScrubIcRate; ///< Scrub Ic Rate
+ IN UINT16 CfgScrubDcRate; ///< Scrub Dc Rate
+ IN BOOLEAN CfgEccSyncFlood; ///< ECC Sync Flood
+} ECC_OVERRIDE_STRUCT;
+
+
+
+
+/**
+ * AGESA Test Points
+ *
+ * These are the values displayed to the user to indicate progress through boot.
+ * These can be used in a debug environment to stop the debugger at a specific
+ * test point:
+ * For SimNow!, this command
+ * bi 81 w vb 49
+ * will stop the debugger on one of the TracePoints (49 is the TP value in this example).
+ *
+ */
+typedef enum {
+ StartProcessorTestPoints, ///< 00 Entry used for range testing for @b Processor related TPs
+
+ // Memory test points
+ TpProcMemBeforeMemDataInit, ///< 01 .. Memory structure initialization (Public interface)
+ TpProcMemBeforeSpdProcessing, ///< 02 .. SPD Data processing (Public interface)
+ TpProcMemAmdMemAuto, ///< 03 .. Memory configuration (Public interface)
+ TpProcMemDramInit, ///< 04 .. DRAM initialization
+ TpProcMemSPDChecking, ///< 05 ..
+ TpProcMemModeChecking, ///< 06 ..
+ TpProcMemSpeedTclConfig, ///< 07 .. Speed and TCL configuration
+ TpProcMemSpdTiming, ///< 08 ..
+ TpProcMemDramMapping, ///< 09 ..
+ TpProcMemPlatformSpecificConfig, ///< 0A ..
+ TPProcMemPhyCompensation, ///< 0B ..
+ TpProcMemStartDcts, ///< 0C ..
+ TpProcMemBeforeDramInit, ///< 0D .. (Public interface)
+ TpProcMemPhyFenceTraining, ///< 0E ..
+ TpProcMemSynchronizeDcts, ///< 0F ..
+ TpProcMemSystemMemoryMapping, ///< 10 ..
+ TpProcMemMtrrConfiguration, ///< 11 ..
+ TpProcMemDramTraining, ///< 12 ..
+ TpProcMemBeforeAnyTraining, ///< 13 .. (Public interface)
+ TpProcMemWriteLevelizationTraining, ///< 14 ..
+ TpProcMemWlFirstPass, ///< 15 .. Below 800Mhz first pass start
+ TpProcMemWlSecondPass, ///< 16 .. Above 800Mhz second pass start
+ TpProcMemWlTrainTargetDimm, ///< 17 .. Target DIMM configured
+ TpProcMemWlPrepDimms, ///< 18 .. Prepare DIMMS for WL
+ TpProcMemWlConfigDimms, ///< 19 .. Configure DIMMS for WL
+ TpProcMemReceiverEnableTraining, ///< 1A ..
+ TpProcMemRcvrStartSweep, ///< 1B .. Start sweep loop
+ TpProcMemRcvrSetDelay, ///< 1C .. Set receiver Delay
+ TpProcMemRcvrWritePattern, ///< 1D .. Write test pattern
+ TpProcMemRcvrReadPattern, ///< 1E .. Read test pattern
+ TpProcMemRcvrTestPattern, ///< 1F .. Compare test pattern
+ TpProcMemRcvrCalcLatency, ///< 20 .. Calculate MaxRdLatency per channel
+ TpProcMemReceiveDqsTraining, ///< 21 ..
+ TpProcMemRcvDqsSetDelay, ///< 22 .. Set Write Data delay
+ TpProcMemRcvDqsWritePattern, ///< 23 .. Write test pattern
+ TpProcMemRcvDqsStartSweep, ///< 24 .. Start read sweep
+ TpProcMemRcvDqsSetRcvDelay, ///< 25 .. Set Receive DQS delay
+ TpProcMemRcvDqsReadPattern, ///< 26 .. Read Test pattern
+ TpProcMemRcvDqsTstPattern, ///< 27 .. Compare Test pattern
+ TpProcMemRcvDqsResults, ///< 28 .. Update results
+ TpProcMemRcvDqsFindWindow, ///< 29 .. Start Find passing window
+ TpProcMemTransmitDqsTraining, ///< 2A ..
+ TpProcMemTxDqStartSweep, ///< 2B .. Start write sweep
+ TpProcMemTxDqSetDelay, ///< 2C .. Set Transmit DQ delay
+ TpProcMemTxDqWritePattern, ///< 2D .. Write test pattern
+ TpProcMemTxDqReadPattern, ///< 2E .. Read Test pattern
+ TpProcMemTxDqTestPattern, ///< 2F .. Compare Test pattern
+ TpProcMemTxDqResults, ///< 30 .. Update results
+ TpProcMemTxDqFindWindow, ///< 31 .. Start Find passing window
+ TpProcMemMaxRdLatencyTraining, ///< 32 ..
+ TpProcMemMaxRdLatStartSweep, ///< 33 .. Start sweep
+ TpProcMemMaxRdLatSetDelay, ///< 34 .. Set delay
+ TpProcMemMaxRdLatWritePattern, ///< 35 .. Write test pattern
+ TpProcMemMaxRdLatReadPattern, ///< 36 .. Read Test pattern
+ TpProcMemMaxRdLatTestPattern, ///< 37 .. Compare Test pattern
+ TpProcMemOnlineSpareInit, ///< 38 .. Online Spare init
+ TpProcMemBankInterleaveInit, ///< 39 .. Bank Interleave Init
+ TpProcMemNodeInterleaveInit, ///< 3A .. Node Interleave Init
+ TpProcMemChannelInterleaveInit, ///< 3B .. Channel Interleave Init
+ TpProcMemEccInitialization, ///< 3C .. ECC initialization
+ TpProcMemPlatformSpecificInit, ///< 3D .. Platform Specific Init
+ TpProcMemBeforeAgesaReadSpd, ///< 3E .. Before callout for "AgesaReadSpd"
+ TpProcMemAfterAgesaReadSpd, ///< 3F .. After callout for "AgesaReadSpd"
+ TpProcMemBeforeAgesaHookBeforeDramInit, ///< 40 .. Before optional callout "AgesaHookBeforeDramInit"
+ TpProcMemAfterAgesaHookBeforeDramInit, ///< 41 .. After optional callout "AgesaHookBeforeDramInit"
+ TpProcMemBeforeAgesaHookBeforeDQSTraining, ///< 42 .. Before optional callout "AgesaHookBeforeDQSTraining"
+ TpProcMemAfterAgesaHookBeforeDQSTraining, ///< 43 .. After optional callout "AgesaHookBeforeDQSTraining"
+ TpProcMemBeforeAgesaHookBeforeExitSelfRef, ///< 44 .. Before optional callout "AgesaHookBeforeDramInit"
+ TpProcMemAfterAgesaHookBeforeExitSelfRef, ///< 45 .. After optional callout "AgesaHookBeforeDramInit"
+ TpProcMemAfterMemDataInit, ///< 46 .. After MemDataInit
+ TpProcMemInitializeMCT, ///< 47 .. Before InitializeMCT
+ TpProcMemLvDdr3, ///< 48 .. Before LV DDR3
+ TpProcMemInitMCT, ///< 49 .. Before InitMCT
+ TpProcMemOtherTiming, ///< 4A.. Before OtherTiming
+ TpProcMemUMAMemTyping, ///< 4B .. Before UMAMemTyping
+ TpProcMemSetDqsEccTmgs, ///< 4C .. Before SetDqsEccTmgs
+ TpProcMemMemClr, ///< 4D .. Before MemClr
+ TpProcMemOnDimmThermal, ///< 4E .. Before On DIMM Thermal
+ TpProcMemDmi, ///< 4F .. Before DMI
+ TpProcMemEnd, ///< 50 .. End of memory code
+
+ // CPU test points
+ TpProcCpuEntryDmi, ///< 51 .. Entry point CreateDmiRecords
+ TpProcCpuEntryPstate, ///< 52 .. Entry point GenerateSsdt
+ TpProcCpuEntryPstateLeveling, ///< 53 .. Entry point PStateLeveling
+ TpProcCpuEntryPstateGather, ///< 54 .. Entry point PStateGatherData
+ TpProcCpuEntryWhea, ///< 55 .. Entry point CreateAcpiWhea
+ TpProcS3Init, ///< 56 Entry point S3Init
+ TpProcCpuProcessRegisterTables = 0X58, ///< 58 .. Register table processing
+ TpProcCpuSetBrandID, ///< 59 .. Set brand ID
+ TpProcCpuLocalApicInit, ///< 5A .. Initialize local APIC
+ TpProcCpuLoadUcode, ///< 5B .. Load microcode patch
+ TpProcCpuBeforePMFeatureInit, ///< 5C .. BeforePM feature dispatch point
+ TpProcCpuPowerMgmtInit, ///< 5D .. Power Management table processing
+ TpProcCpuEarlyFeatureInit, ///< 5E .. Early feature dispatch point
+ TpProcCpuCoreLeveling, ///< 5F .. Core Leveling
+ TpProcCpuApMtrrSync, ///< 60 .. AP MTRR sync up
+ TpProcCpuPostFeatureInit, ///< 61 .. POST feature dispatch point
+ TpProcCpuBeforeRelinquishAPsFeatureInit = 0x63, ///< 63 .. Before Relinquishing control of APs feature dispatch point
+ TpProcCpuBeforeAllocateWheaBuffer, ///< 64 .. Before the WHEA init code calls out to allocate a buffer
+ TpProcCpuAfterAllocateWheaBuffer, ///< 65 .. After the WHEA init code calls out to allocate a buffer
+ TpProcCpuBeforeAllocateSsdtBuffer = 0x6A, ///< 6A .. Before the P-state init code calls out to allocate a buffer
+ TpProcCpuAfterAllocateSsdtBuffer, ///< 6B .. After the P-state init code calls out to allocate a buffer
+ TpProcCpuEntryCrat, ///< 6C .. Entry point CreateAcpiCrat
+ TpProcCpuEntryCdit, ///< 6D .. Entry point CreateAcpiCdit
+ TpProcCpuEntryScs, ///< 6E .. Entry point InitializeScsFeature
+ TpProcCpuRunBtc, ///< 6F .. Start of Btc run
+ TpProcCpuEndBtc, ///< 70 .. End of Btc run
+
+ // Topology test points
+ TpProcTopologyEntry = 0x71, ///< 71 .. Topology Init begin
+ TpProcTopologyDone = 0x7C, ///< 7C .. Topology Init complete
+
+ // Extended memory test point
+ TpProcMemSendMRS2 = 0x80, ///< 80 .. Sending MRS2
+ TpProcMemSendMRS3, ///< 81 .. Sedding MRS3
+ TpProcMemSendMRS1, ///< 82 .. Sending MRS1
+ TpProcMemSendMRS0, ///< 83 .. Sending MRS0
+ TpProcMemContinPatternGenRead, ///< 84 .. Continuous Pattern Read
+ TpProcMemContinPatternGenWrite, ///< 85 .. Continuous Pattern Write
+ TpProcMem2dRdDqsTraining, ///< 86 .. Mem: 2d RdDqs Training begin
+ TpProcMemBefore2dTrainExtVrefChange,///< 87 .. Mem: Before optional callout to platform BIOS to change External Vref during 2d Training
+ TpProcMemAfter2dTrainExtVrefChange, ///< 88 .. Mem: After optional callout to platform BIOS to change External Vref during 2d Training
+ TpProcMemConfigureDCTForGeneral, ///< 89 .. Configure DCT For General use begin
+ TpProcMemProcConfigureDCTForTraining, ///< 8A .. Configure DCT For training begin
+ TpProcMemConfigureDCTNonExplicitSeq,///< 8B .. Configure DCT For Non-Explicit
+ TpProcMemSynchronizeChannels, ///< 8C .. Configure to Sync channels
+ TpProcMemC6StorageAllocation, ///< 8D .. Allocate C6 Storage
+
+ // Gnb Earlier init
+ TpGnbEarlierPcieConfigurationInit = 0x90, ///< 90 .. GNB earlier PCIE configuration init
+ TpGnbEarlierInterface = 0x91, ///< 91 .. GNB earlier interface
+ // Gnb Early init
+ TpGnbEarlyInterface = 0x92, ///< 92 .. GNB early interface
+ TpGnbPcieConfigurationMap, ///< 93 .. GNB early PCIE configuration map
+ TpGnbPcieEarlyInterface, ///< 94 .. GNB early PCIE interface
+ //Gnb post init
+ TpGnbPciePostEarlyInterface = 0x95, ///< 95 .. GNB post early interface
+ TpGnbGfxConfigPostInterface, ///< 96 .. GNB post GFX config interface
+ TpGnbGfxPostInterface, ///< 97 .. GNB post GFX interface
+ // Gnb post after DRAM init
+ TpGnbPostInterface = 0x98, ///< 98 .. GNB post after DRAM interface
+ TpGnbPciePostInterface, ///< 99 .. GNB post after DRAM PCIE interface
+ // Gnb Env init
+ TpGnbEnvInterface, ///< 9A .. GNB Env Nb interface
+ TpGnbPcieEnvInterface, ///< 9B .. GNB Env PCIE interface
+ TpGnbGfxConfigEnvInterface, ///< 9C .. GNB Env GFX Config interface
+ TpGnbGfxEnvInterface, ///< 9D .. GNB Env GFX interface
+ // Gnb Mid init
+ TpGnbGfxConfigMidInterface = 0x9E, ///< 9E .. GNB Mid GFX config interface
+ TpGnbGfxMidInterface, ///< 9F .. GNB Mid GFX interface
+ TpPcieMidInterface, ///< A0 .. GNB Mid PCIE interface
+ TpGnbMidInterface, ///< A1 .. GNB Mid interface
+ TpGnbSmuMidInterface, ///< A2 .. GNB Mid SMU feature
+ TpPciePowerGateFeature, ///< A3 .. GNB Mid pcie power gate feature
+ TpGnbPcieMaxPayloadInterface, ///< A4 .. GNB Mid pcie max payload interface
+ TpGnbPcieClkPmInterface, ///< A5 .. GNB Mid pcie clk pm port interface
+ TpGnbPcieAspmInterface, ///< A6 .. GNB Mid pcie ASPM interface
+ TpGnbNbIoapicInterface, ///< A7 .. GNB Mid IOAPIC interface
+ // Gnb Late init
+ TpGnbPcieAlibFeature = 0xA8, ///< A8 .. GNB Late pcie ALIB feature
+ TpGnbIommuIvrsTable, ///< A9 .. GNB Late pcie IOMMU
+ TpGnbBtcRun, ///< AA .. GNB Late run BTC
+ // Gnb S3 Save
+ TpGnbGfxInitSview = 0xAE, ///< AD .. GNB S3SAVE GFX sview init
+ TpGnbAlibDispatchFeature = 0xAE, ///< AE .. GNB ALIB dispatch feature
+ EndGnbTestPoints = 0xAF, ///< AF End of TP range for GNB
+
+ StartFchTestPoints = 0xB0, ///< B0 Entry used for range testing for @b FCH related TPs
+ TpFchInitResetDispatching, ///< B1 .. FCH InitReset dispatch point
+ TpFchGppBeforePortTraining, ///< B2 .. Before FCH GPP port training
+ TpFchGppGen1PortPolling, ///< B3 .. FCH GPP port polling with GEN1 speed
+ TpFchGppGen2PortPolling, ///< B4 .. FCH GPP port polling with GEN2 speed
+ TpFchGppAfterPortTraining, ///< B5 .. After FCH GPP port training
+ TpFchInitEnvDispatching, ///< B6 .. FCH InitEnv dispatch point
+ TpFchInitMidDispatching, ///< B7 .. FCH InitMid dispatch point
+ TpFchInitLateDispatching, ///< B8 .. FCH InitLate dispatch point
+ TpFchGppHotPlugging, ///< B9 .. FCH GPP hot plug event
+ TpFchGppHotUnplugging, ///< BA .. AFCH GPP hot unplug event
+ TpFchInitS3EarlyDispatching, ///< BB .. FCH InitS3Early dispatch point
+ TpFchInitS3LateDispatching, ///< BC .. FCH InitS3Late dispatch point
+ EndFchTestPoints, ///< BF End of TP range for FCH
+
+ // Interface test points
+ TpIfAmdInitResetEntry = 0xC0, ///< C0 .. Entry to AmdInitReset
+ TpIfAmdInitResetExit, ///< C1 .. Exiting from AmdInitReset
+ TpIfAmdInitRecoveryEntry, ///< C2 .. Entry to AmdInitRecovery
+ TpIfAmdInitRecoveryExit, ///< C3 .. Exiting from AmdInitRecovery
+ TpIfAmdInitEarlyEntry, ///< C4 .. Entry to AmdInitEarly
+ TpIfAmdInitEarlyExit, ///< C5 .. Exiting from AmdInitEarly
+ TpIfAmdInitPostEntry, ///< C6 .. Entry to AmdInitPost
+ TpIfAmdInitPostExit, ///< C7 .. Exiting from AmdInitPost
+ TpIfAmdInitEnvEntry, ///< C8 .. Entry to AmdInitEnv
+ TpIfAmdInitEnvExit, ///< C9 .. Exiting from AmdInitEnv
+ TpIfAmdInitMidEntry, ///< CA .. Entry to AmdInitMid
+ TpIfAmdInitMidExit, ///< CB .. Exiting from AmdInitMid
+ TpIfAmdInitLateEntry, ///< CC .. Entry to AmdInitLate
+ TpIfAmdInitLateExit, ///< CD .. Exiting from AmdInitLate
+ TpIfAmdInitRtbEntry, ///< CE .. Entry to AmdInitRtb
+ TpIfAmdInitRtbExit, ///< CF .. Exiting from AmdInitRtb
+ TpIfAmdInitResumeEntry, ///< D0 .. Entry to AmdInitResume
+ TpIfAmdInitResumeExit, ///< D1 .. Exiting from AmdInitResume
+ TpIfAmdS3LateRestoreEntry, ///< D2 .. Entry to AmdS3LateRestore
+ TpIfAmdS3LateRestoreExit, ///< D3 .. Exiting from AmdS3LateRestore
+ TpIfAmdLateRunApTaskEntry, ///< D4 .. Entry to AmdS3LateRestore
+ TpIfAmdLateRunApTaskExit, ///< D5 .. Exiting from AmdS3LateRestore
+ TpIfAmdReadEventLogEntry, ///< D6 .. Entry to AmdReadEventLog
+ TpIfAmdReadEventLogExit, ///< D7 .. Exiting from AmdReadEventLog
+ TpIfAmdGetApicIdEntry, ///< D8 .. Entry to AmdGetApicId
+ TpIfAmdGetApicIdExit, ///< D9 .. Exiting from AmdGetApicId
+ TpIfAmdGetPciAddressEntry, ///< DA .. Entry to AmdGetPciAddress
+ TpIfAmdGetPciAddressExit, ///< DB .. Exiting from AmdGetPciAddress
+ TpIfAmdIdentifyCoreEntry, ///< DC .. Entry to AmdIdentifyCore
+ TpIfAmdIdentifyCoreExit, ///< DD .. Exiting from AmdIdentifyCore
+ TpIfBeforeRunApFromIds, ///< DE .. After IDS calls out to run code on an AP
+ TpIfAfterRunApFromIds, ///< DF .. After IDS calls out to run code on an AP
+ TpIfBeforeGetIdsData, ///< E0 .. Before IDS calls out to get IDS data
+ TpIfAfterGetIdsData, ///< E1 .. After IDS calls out to get IDS data
+ TpIfBeforeAllocateHeapBuffer, ///< E2 .. Before the heap manager calls out to allocate a buffer
+ TpIfAfterAllocateHeapBuffer, ///< E3 .. After the heap manager calls out to allocate a buffer
+ TpIfBeforeDeallocateHeapBuffer, ///< E4 .. Before the heap manager calls out to deallocate a buffer
+ TpIfAfterDeallocateHeapBuffer, ///< E5 .. After the heap manager calls out to deallocate a buffer
+ TpIfBeforeLocateHeapBuffer, ///< E6 .. Before the heap manager calls out to locate a buffer
+ TpIfAfterLocateHeapBuffer, ///< E7 .. After the heap manager calls out to locate a buffer
+ TpIfBeforeRunApFromAllAps, ///< E8 .. Before the BSP calls out to run code on an AP
+ TpIfAfterRunApFromAllAps, ///< E9 .. After the BSP calls out to run code on an AP
+ TpIfBeforeRunApFromAllCore0s, ///< EA .. Before the BSP calls out to run code on an AP
+ TpIfAfterRunApFromAllCore0s, ///< EB .. After the BSP calls out to run code on an AP
+ TpIfBeforeAllocateS3SaveBuffer, ///< EC .. Before the S3 save code calls out to allocate a buffer
+ TpIfAfterAllocateS3SaveBuffer, ///< ED .. After the S3 save code calls out to allocate a buffer
+ TpIfBeforeAllocateMemoryS3SaveBuffer, ///< EE .. Before the memory S3 save code calls out to allocate a buffer
+ TpIfAfterAllocateMemoryS3SaveBuffer, ///< EF .. After the memory S3 save code calls out to allocate a buffer
+ TpIfBeforeLocateS3PciBuffer, ///< F0 .. Before the memory code calls out to locate a buffer
+ TpIfAfterLocateS3PciBuffer, ///< F1 .. After the memory code calls out to locate a buffer
+ TpIfBeforeLocateS3CPciBuffer, ///< F2 .. Before the memory code calls out to locate a buffer
+ TpIfAfterLocateS3CPciBuffer, ///< F3 .. After the memory code calls out to locate a buffer
+ TpIfBeforeLocateS3MsrBuffer, ///< F4 .. Before the memory code calls out to locate a buffer
+ TpIfAfterLocateS3MsrBuffer, ///< F5 .. After the memory code calls out to locate a buffer
+ TpIfBeforeLocateS3CMsrBuffer, ///< F6 .. Before the memory code calls out to locate a buffer
+ TpIfAfterLocateS3CMsrBuffer, ///< F7 .. After the memory code calls out to locate a buffer
+ TpReadyToBoot, ///< F8 .. Ready to boot event
+ // PMU test points
+ TpProcMemPmuFailed, ///< F9 .. Failed PMU training.
+ TpIfAmdS3FinalRestoreEntry, ///< FA .. Entry to AmdS3FinalRestore
+ TpIfAmdS3FinalRestoreExit, ///< FB .. Exiting from AmdS3FinalRestore
+
+ EndAgesaTps = 0xFF, ///< Last defined AGESA TP
+} AGESA_TP;
+
+///Ids Feat description
+typedef enum {
+ IDS_FEAT_UCODE_UPDATE = 0x0000, ///< Feat for Ucode Update
+ IDS_FEAT_TARGET_PSTATE, ///< Feat for Target Pstate
+ IDS_FEAT_POSTPSTATE, ///< Feat for Post Pstate
+ IDS_FEAT_ECC_CTRL, ///< Feat for Ecc Control
+ IDS_FEAT_ECC_SYMBOL_SIZE, ///< Feat for Ecc symbol size
+ IDS_FEAT_DCT_ALLMEMCLK, ///< Feat for all memory clock
+ IDS_FEAT_DCT_ALLCKE, ///< Feat for all CKE
+ IDS_FEAT_DCT_ALLCS, ///< Feat for all CS
+ IDS_FEAT_DCT_GANGMODE, ///< Feat for Dct gang mode
+ IDS_FEAT_DCT_BURSTLENGTH, ///< Feat for dct burst length
+ IDS_FEAT_DCT_POWERDOWN, ///< Feat for dct power down
+ IDS_FEAT_DCT_DLLSHUTDOWN, ///< Feat for dct dll shut down
+ IDS_FEAT_HDTOUT, ///< Feat for hdt out
+ IDS_FEAT_GNB_PLATFORMCFG, ///< Feat for override GNB platform config
+ IDS_FEAT_CPB_CTRL, ///< Feat for Config the Core peformance boost feature
+ IDS_FEAT_HTC_CTRL, ///< Feat for Hardware Thermal Control
+ IDS_FEAT_MEMORY_MAPPING, ///< Feat for Memory Mapping
+ IDS_FEAT_NV_TO_CMOS, ///< Feat for Save BSP Nv to CMOS
+ IDS_FEAT_COMMON, ///< Common Feat
+ IDS_FEAT_END = 0xFF ///< End of Common feat
+} IDS_FEAT;
+
+///Ids IDT table function ID
+typedef enum {
+ IDS_IDT_REPLACE_IDTR_FOR_BSC = 0x0000, ///< Function ID for saving IDTR for BSC
+ IDS_IDT_RESTORE_IDTR_FOR_BSC, ///< Function ID for restoring IDTR for BSC
+ IDS_IDT_UPDATE_EXCEPTION_VECTOR_FOR_AP, ///< Function ID for updating exception vector
+} IDS_IDT_FUNC_ID;
+
+typedef IDS_STATUS IDS_COMMON_FUNC (
+ IN OUT VOID *DataPtr,
+ IN OUT AMD_CONFIG_PARAMS *StdHeader,
+ IN IDS_NV_ITEM *IdsNvPtr
+ );
+
+typedef IDS_COMMON_FUNC *PIDS_COMMON_FUNC;
+
+/// Data Structure of IDS Feature block
+typedef struct _IDS_FAMILY_FEAT_STRUCT {
+ IDS_FEAT IdsFeat; ///< Ids Feat ID
+ BOOLEAN IsBsp; ///< swith for Bsp check
+ AGESA_IDS_OPTION IdsOption; ///< IDS option
+ UINT64 CpuFamily; ///<
+ PIDS_COMMON_FUNC pf_idsoption; ///<pointer to function
+} IDS_FAMILY_FEAT_STRUCT;
+
+
+/// Data Structure of IDS option
+typedef struct _IDS_OPTION_STRUCT {
+ AGESA_IDS_OPTION idsoption; ///< IDS option
+ PIDS_COMMON_FUNC pf_idsoption; ///<pointer to function
+} IDS_OPTION_STRUCT;
+
+/// Data Structure of IDS option table
+typedef struct _IDS_OPTION_STRUCT_TBL {
+ UINT8 version; ///<Version of IDS option table
+ UINT16 size; ///<Size of IDS option table
+ CONST IDS_OPTION_STRUCT *pIdsOptionStruct; ///<pointer to array of structure
+} IDS_OPTION_STRUCT_TBL;
+
+#define IDS_NV_TO_CMOS_LEN_BYTE 1
+#define IDS_NV_TO_CMOS_LEN_WORD 2
+#define IDS_NV_TO_CMOS_LEN_END 0xFF
+#define IDS_NV_TO_CMOS_ID_END 0xFFFF
+
+/// Data struct of set/get NV to/from CMOS
+typedef struct _IDS_NV_TO_CMOS {
+ UINT8 Length; ///< Length of NV
+ UINT16 IDS_NV_ID; ///< IDS id
+} IDS_NV_TO_CMOS;
+
+IDS_STATUS
+AmdIdsCtrlDispatcher (
+ IN AGESA_IDS_OPTION IdsOption,
+ IN OUT VOID *DataPtr,
+ IN OUT AMD_CONFIG_PARAMS *StdHeader
+ );
+
+AGESA_STATUS
+IdsOptionCallout (
+ IN UINTN CallOutId,
+ IN OUT VOID *DataPtr,
+ IN OUT AMD_CONFIG_PARAMS *StdHeader
+ );
+
+VOID
+AmdIdsHdtOutInit (
+ IN OUT AMD_CONFIG_PARAMS *StdHeader
+ );
+
+VOID
+AmdIdsHdtOutExit (
+ IN OUT AMD_CONFIG_PARAMS *StdHeader
+ );
+
+VOID
+AmdIdsHdtOutS3Exit (
+ IN OUT AMD_CONFIG_PARAMS *StdHeader
+ );
+
+VOID
+AmdIdsHdtOutS3ApExit (
+ IN OUT AMD_CONFIG_PARAMS *StdHeader
+ );
+
+VOID
+AmdIdsDebugPrint (
+ IN UINT64 Flag,
+ IN CONST CHAR8 *Format,
+ IN ...
+ );
+
+VOID
+AmdIdsDebugPrintTopology (
+ IN CONST CHAR8 *Format,
+ IN ...
+ );
+
+VOID
+AmdIdsDebugPrintCpu (
+ IN CONST CHAR8 *Format,
+ IN ...
+ );
+
+VOID
+AmdIdsDebugPrintMem (
+ IN CONST CHAR8 *Format,
+ IN ...
+ );
+
+VOID
+AmdIdsDebugPrintGnb (
+ IN CONST CHAR8 *Format,
+ IN ...
+ );
+
+VOID
+AmdIdsDebugPrintAll (
+ IN CONST CHAR8 *Format,
+ IN ...
+ );
+
+VOID
+AmdIdsHdtOutBufferFlush (
+ IN OUT AMD_CONFIG_PARAMS *StdHeader
+ );
+
+VOID
+IdsMemTimeOut (
+ IN OUT VOID *DataPtr
+ );
+
+VOID
+IdsAgesaTestPoint (
+ IN AGESA_TP TestPoint,
+ IN OUT AMD_CONFIG_PARAMS *StdHeader
+ );
+
+/**
+ * IDS Backend Function for ASSERT
+ *
+ * Halt execution with stop code display. Stop Code is displayed on port 80, with rotation so that
+ * it is visible on 8, 16, or 32 bit display. The stop code is alternated with 0xDEAD on the display,
+ * to help distinguish the stop code from a post code loop.
+ * Additional features may be available if using simulation.
+ *
+ * @param[in] FileCode File code(define in FILECODE.h) mix with assert Line num.
+ *
+ * @retval TRUE No error
+**/
+BOOLEAN
+IdsAssert (
+ IN UINT32 FileCode
+ );
+
+/**
+ * The engine code for ASSERT MACRO
+ *
+ * Halt execution with stop code display. Stop Code is displayed on port 80, with rotation so that
+ * it is visible on 8, 16, or 32 bit display. The stop code is alternated with 0xDEAD on the display,
+ * to help distinguish the stop code from a post code loop.
+ * Additional features may be available if using simulation.
+ *
+ * @param[in] FileCode File code(define in FILECODE.h) mix with assert Line num.
+ *
+ */
+BOOLEAN
+IdsErrorStop (
+ IN UINT32 FileCode
+ );
+
+VOID
+IdsDelay (
+ VOID
+);
+
+BOOLEAN
+AmdHeapIntactCheck (
+ IN AMD_CONFIG_PARAMS *StdHeader
+ );
+
+VOID
+IdsCarCorruptionCheck (
+ IN OUT AMD_CONFIG_PARAMS *StdHeader
+ );
+
+IDS_STATUS
+IdsExceptionTrap (
+ IN IDS_IDT_FUNC_ID IdsIdtFuncId,
+ IN VOID *DataPtr,
+ IN OUT AMD_CONFIG_PARAMS *StdHeader
+ );
+
+AGESA_STATUS
+IdsPerfTimestamp (
+ IN UINT32 LineInFile,
+ IN UINT32 Description,
+ IN OUT AMD_CONFIG_PARAMS *StdHeader
+ );
+
+AGESA_STATUS
+IdsPerfAnalyseTimestamp (
+ IN OUT AMD_CONFIG_PARAMS *StdHeader
+ );
+
+
+#if IDSOPT_IDS_ENABLED == FALSE
+ #undef IEM_SKIP_CODE
+ #undef IEM_INSERT_CODE
+#endif
+#ifndef IEM_SKIP_CODE
+ #define IEM_SKIP_CODE(L)
+#endif
+#ifndef IEM_INSERT_CODE
+ #define IEM_INSERT_CODE(L, Fn, Parm)
+#endif
+
+#endif // _IDS_H_
diff --git a/src/vendorcode/amd/pi/00660F01/Include/IdsPerf.h b/src/vendorcode/amd/pi/00660F01/Include/IdsPerf.h
new file mode 100644
index 0000000..0ec8a49
--- /dev/null
+++ b/src/vendorcode/amd/pi/00660F01/Include/IdsPerf.h
@@ -0,0 +1,145 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD Integrated Debug Routines for performance analysis
+ *
+ * Contains AMD AGESA debug macros and functions for performance analysis
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: IDS
+ * @e \$Revision: 309090 $ @e \$Date: 2014-12-09 12:28:05 -0600 (Tue, 09 Dec 2014) $
+ */
+ /*****************************************************************************
+ *
+ * Copyright (c) 2008 - 2015, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ***************************************************************************/
+#ifndef _IDS_PERFORMANCE_DATA_POINT
+
+ #define _IDS_PERFORMANCE_DATA_POINT
+ #define IDS_PERF_VERSION 0x00010001ul //version number 0.1.0.1
+/// Time points performance function used
+/// N O T E: NEVER change below defination, any new TP MUST be appended to the end of this enum
+ typedef enum {
+ TP_BEGINPROCAMDINITEARLY = 0x100, ///< BeginProcAmdInitEarly
+ TP_ENDPROCAMDINITEARLY = 0x101, ///< EndProcAmdInitEarly
+ TP_BEGINAMDTOPOINITIALIZE = 0x102, ///< BeginAmdTopoInitialize
+ TP_ENDAMDTOPOINITIALIZE = 0x103, ///< EndAmdTopoInitialize
+ TP_BEGINGNBINITATEARLIER = 0x104, ///< BeginGnbInitAtEarlier
+ TP_ENDGNBINITATEARLIER = 0x105, ///< EndGnbInitAtEarlier
+ TP_BEGINAMDCPUEARLY = 0x106, ///< BeginAmdCpuEarly
+ TP_ENDAMDCPUEARLY = 0x107, ///< EndAmdCpuEarly
+ TP_BEGINGNBINITATEARLY = 0x108, ///< BeginGnbInitAtEarly
+ TP_ENDGNBINITATEARLY = 0x109, ///< EndGnbInitAtEarly
+ TP_BEGINPROCAMDINITENV = 0x10A, ///< BeginProcAmdInitEnv
+ TP_ENDPROCAMDINITENV = 0x10B, ///< EndProcAmdInitEnv
+ TP_BEGININITENV = 0x10C, ///< BeginInitEnv
+ TP_ENDINITENV = 0x10D, ///< EndInitEnv
+ TP_BEGINGNBINITATENV = 0x10E, ///< BeginGnbInitAtEnv
+ TP_ENDGNBINITATENV = 0x10F, ///< EndGnbInitAtEnv
+ TP_BEGINPROCAMDINITLATE = 0x110, ///< BeginProcAmdInitLate
+ TP_ENDPROCAMDINITLATE = 0x111, ///< EndProcAmdInitLate
+ TP_BEGINCREATSYSTEMTABLE = 0x112, ///< BeginCreatSystemTable
+ TP_ENDCREATSYSTEMTABLE = 0x113, ///< EndCreatSystemTable
+ TP_BEGINDISPATCHCPUFEATURESLATE = 0x114, ///< BeginDispatchCpuFeaturesLate
+ TP_ENDDISPATCHCPUFEATURESLATE = 0x115, ///< EndDispatchCpuFeaturesLate
+ TP_BEGINAMDCPULATE = 0x116, ///< BeginAmdCpuLate
+ TP_ENDAMDCPULATE = 0x117, ///< EndAmdCpuLate
+ TP_BEGINGNBINITATLATE = 0x118, ///< BeginGnbInitAtLate
+ TP_ENDGNBINITATLATE = 0x119, ///< EndGnbInitAtLate
+ TP_BEGINPROCAMDINITMID = 0x11A, ///< BeginProcAmdInitMid
+ TP_ENDPROCAMDINITMID = 0x11B, ///< EndProcAmdInitMid
+ TP_BEGININITMID = 0x11E, ///< BeginInitMid
+ TP_ENDINITMID = 0x11F, ///< EndInitMid
+ TP_BEGINGNBINITATMID = 0x120, ///< BeginGnbInitAtMid
+ TP_ENDGNBINITATMID = 0x121, ///< EndGnbInitAtMid
+ TP_BEGINPROCAMDINITPOST = 0x122, ///< BeginProcAmdInitPost
+ TP_ENDPROCAMDINITPOST = 0x123, ///< EndProcAmdInitPost
+ TP_BEGINGNBINITATPOST = 0x124, ///< BeginGnbInitAtPost
+ TP_ENDGNBINITATPOST = 0x125, ///< EndGnbInitAtPost
+ TP_BEGINAMDMEMAUTO = 0x126, ///< BeginAmdMemAuto
+ TP_ENDAMDMEMAUTO = 0x127, ///< EndAmdMemAuto
+ TP_BEGINAMDCPUPOST = 0x128, ///< BeginAmdCpuPost
+ TP_ENDAMDCPUPOST = 0x129, ///< EndAmdCpuPost
+ TP_BEGINGNBINITATPOSTAFTERDRAM = 0x12A, ///< BeginGnbInitAtPostAfterDram
+ TP_ENDGNBINITATPOSTAFTERDRAM = 0x12B, ///< EndGnbInitAtPostAfterDram
+ TP_BEGINPROCAMDINITRESET = 0x12C, ///< BeginProcAmdInitReset
+ TP_ENDPROCAMDINITRESET = 0x12D, ///< EndProcAmdInitReset
+ TP_BEGININITRESET = 0x12E, ///< BeginInitReset
+ TP_ENDINITRESET = 0x12F, ///< EndInitReset
+ TP_BEGINHTINITRESET = 0x130, ///< BeginHtInitReset
+ TP_ENDHTINITRESET = 0x131, ///< EndHtInitReset
+ TP_BEGINPROCAMDINITRESUME = 0x132, ///< BeginProcAmdInitResume
+ TP_ENDPROCAMDINITRESUME = 0x133, ///< EndProcAmdInitResume
+ TP_BEGINAMDMEMS3RESUME = 0x134, ///< BeginAmdMemS3Resume
+ TP_ENDAMDMEMS3RESUME = 0x135, ///< EndAmdMemS3Resume
+ TP_BEGINDISPATCHCPUFEATURESS3RESUME = 0x136, ///< BeginDispatchCpuFeaturesS3Resume
+ TP_ENDDISPATCHCPUFEATURESS3RESUME = 0x137, ///< EndDispatchCpuFeaturesS3Resume
+ TP_BEGINSETCORESTSCFREQSEL = 0x138, ///< BeginSetCoresTscFreqSel
+ TP_ENDSETCORESTSCFREQSEL = 0x139, ///< EndSetCoresTscFreqSel
+ TP_BEGINMEMFMCTMEMCLR_INIT = 0x13A, ///< BeginMemFMctMemClr_Init
+ TP_ENDNMEMFMCTMEMCLR_INIT = 0x13B, ///< EndnMemFMctMemClr_Init
+ TP_BEGINMEMBEFOREMEMDATAINIT = 0x13C, ///< BeginMemBeforeMemDataInit
+ TP_ENDMEMBEFOREMEMDATAINIT = 0x13D, ///< EndMemBeforeMemDataInit
+ TP_BEGINPROCAMDMEMAUTO = 0x13E, ///< BeginProcAmdMemAuto
+ TP_ENDPROCAMDMEMAUTO = 0x13F, ///< EndProcAmdMemAuto
+ TP_BEGINMEMMFLOWC32 = 0x140, ///< BeginMemMFlowC32
+ TP_ENDMEMMFLOWC32 = 0x141, ///< EndMemMFlowC32
+ TP_BEGINMEMINITIALIZEMCT = 0x142, ///< BeginMemInitializeMCT
+ TP_ENDMEMINITIALIZEMCT = 0x143, ///< EndMemInitializeMCT
+ TP_BEGINMEMSYSTEMMEMORYMAPPING = 0x144, ///< BeginMemSystemMemoryMapping
+ TP_ENDMEMSYSTEMMEMORYMAPPING = 0x145, ///< EndMemSystemMemoryMapping
+ TP_BEGINMEMDRAMTRAINING = 0x146, ///< BeginMemDramTraining
+ TP_ENDMEMDRAMTRAINING = 0x147, ///< EndMemDramTraining
+ TP_BEGINMEMOTHERTIMING = 0x148, ///< BeginMemOtherTiming
+ TP_ENDMEMOTHERTIMING = 0x149, ///< EndMemOtherTiming
+ TP_BEGINMEMUMAMEMTYPING = 0x14A, ///< BeginMemUMAMemTyping
+ TP_ENDMEMUMAMEMTYPING = 0x14B, ///< EndMemUMAMemTyping
+ TP_BEGINMEMMEMCLR = 0x14C, ///< BeginMemMemClr
+ TP_ENDMEMMEMCLR = 0x14D, ///< EndMemMemClr
+ TP_BEGINMEMMFLOWTN = 0x14E, ///< BeginMemMFlowTN
+ TP_ENDMEMMFLOWTN = 0x14F, ///< EndMemMFlowTN
+ TP_BEGINAGESAHOOKBEFOREDRAMINIT = 0x150, ///< BeginAgesaHookBeforeDramInit
+ TP_ENDAGESAHOOKBEFOREDRAMINIT = 0x151, ///< EndAgesaHookBeforeDramInit
+ TP_BEGINPROCMEMDRAMTRAINING = 0x152, ///< BeginProcMemDramTraining
+ TP_ENDPROCMEMDRAMTRAINING = 0x153, ///< EndProcMemDramTraining
+ TP_BEGINGNBINITATRTB = 0x154, ///< BeginGnbInitAtRtb
+ TP_ENDGNBINITATRTB = 0x155, ///< EndGnbInitAtRtb
+ TP_BEGINGNBLOADSCSDATA = 0x156, ///< BeginGnbLoadScsData
+ TP_ENDGNBLOADSCSDATA = 0x157, ///< EndGnbLoadScsData
+ TP_BEGINGNBPCIETRAINING = 0x158, ///< BeginGnbPcieTraining
+ TP_ENDGNBPCIETRAINING = 0x159, ///< EndGnbPcieTraining
+ TP_BEGINDISPATCHCPUFEATURESINITRTB = 0x15A, ///< BeginDispatchCpuFeaturesInitRtb
+ TP_ENDDISPATCHCPUFEATURESINITRTB = 0x15B, ///< EndDispatchCpuFeaturesInitRtb
+ TP_BEGINAMDCPUMID = 0x15C, ///< BeginAmdCpuEarly
+ TP_ENDAMDCPUMID = 0x15D, ///< EndAmdCpuEarly
+ TP_BEGINAMDGNBMIDLATE = 0x15E, ///< BeginAmdGnbMidLate
+ TP_ENDAMDAMDGNBMIDLATE = 0x15F, ///< EndAmdGnbMidLate
+ IDS_TP_END ///< End of IDS TP list
+ } IDS_PERF_DATA;
+#endif
diff --git a/src/vendorcode/amd/pi/00660F01/Include/Options.h b/src/vendorcode/amd/pi/00660F01/Include/Options.h
new file mode 100644
index 0000000..70c39f8
--- /dev/null
+++ b/src/vendorcode/amd/pi/00660F01/Include/Options.h
@@ -0,0 +1,68 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AGESA options structures
+ *
+ * Contains options control structures for the AGESA build options
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: Core
+ * @e \$Revision: 309090 $ @e \$Date: 2014-12-09 12:28:05 -0600 (Tue, 09 Dec 2014) $
+ */
+ /*****************************************************************************
+ *
+ * Copyright (c) 2008 - 2015, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ***************************************************************************/
+
+
+#ifndef _OPTIONS_H_
+#define _OPTIONS_H_
+
+/**
+ * Provide topology limits for loops and runtime, based on supported families.
+ */
+typedef struct {
+ UINT32 PlatformNumberOfSockets; ///< The limit to the number of processors based on
+ ///< supported families and other build options.
+ UINT32 PlatformNumberOfModules; ///< The limit to the number of modules in a processor, based
+ ///< on supported families.
+} OPTIONS_CONFIG_TOPOLOGY;
+
+/**
+ * Dispatch Table.
+ *
+ * The push high dispatcher uses this table to find what entries are currently in the build image.
+ */
+typedef struct {
+ UINT32 FunctionId; ///< The function id specified.
+ IMAGE_ENTRY EntryPoint; ///< The corresponding entry point to call.
+} DISPATCH_TABLE;
+
+
+#endif // _OPTIONS_H_
diff --git a/src/vendorcode/amd/pi/00660F01/Include/PlatformMemoryConfiguration.h b/src/vendorcode/amd/pi/00660F01/Include/PlatformMemoryConfiguration.h
new file mode 100644
index 0000000..38f7f05
--- /dev/null
+++ b/src/vendorcode/amd/pi/00660F01/Include/PlatformMemoryConfiguration.h
@@ -0,0 +1,530 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD Platform Specific Memory Configuration
+ *
+ * Contains Definitions and Macros for control of AGESA Memory code on a per platform basis
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: OPTION
+ * @e \$Revision: 309090 $ @e \$Date: 2014-12-09 12:28:05 -0600 (Tue, 09 Dec 2014) $
+ *
+ */
+ /*****************************************************************************
+ *
+ * Copyright (c) 2008 - 2015, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ***************************************************************************/
+
+#ifndef _PLATFORM_MEMORY_CONFIGURATION_H_
+#define _PLATFORM_MEMORY_CONFIGURATION_H_
+
+/*----------------------------------------------------------------------------------------
+ * M I X E D (Definitions And Macros / Typedefs, Structures, Enums)
+ *----------------------------------------------------------------------------------------
+ */
+#ifndef PSO_ENTRY
+ #define PSO_ENTRY UINT8
+#endif
+
+/*----------------------------------------------------------------------------------------
+ * D E F I N I T I O N S A N D M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+/*----------------------------------------------------------------------------------------
+ * T Y P E D E F S, S T R U C T U R E S, E N U M S
+ *----------------------------------------------------------------------------------------
+ */
+/*----------------------------------------------------------------------------------------
+ * PLATFORM SPECIFIC MEMORY DEFINITIONS
+ *----------------------------------------------------------------------------------------
+ */
+///
+/// Memory Speed and DIMM Population Masks
+///
+///< DDR Speed Masks
+///< Specifies the DDR Speed on a memory channel
+///
+#define ANY_SPEED 0xFFFFFFFFul
+#define DDR400 ((UINT32) 1 << (DDR400_FREQUENCY / 66))
+#define DDR533 ((UINT32) 1 << (DDR533_FREQUENCY / 66))
+#define DDR667 ((UINT32) 1 << (DDR667_FREQUENCY / 66))
+#define DDR800 ((UINT32) 1 << (DDR800_FREQUENCY / 66))
+#define DDR1066 ((UINT32) 1 << (DDR1066_FREQUENCY / 66))
+#define DDR1333 ((UINT32) 1 << (DDR1333_FREQUENCY / 66))
+#define DDR1600 ((UINT32) 1 << (DDR1600_FREQUENCY / 66))
+#define DDR1866 ((UINT32) 1 << (DDR1866_FREQUENCY / 66))
+#define DDR2133 ((UINT32) 1 << (DDR2133_FREQUENCY / 66))
+#define DDR2400 ((UINT32) 1 << (DDR2400_FREQUENCY / 66))
+///
+///< DIMM POPULATION MASKS
+///< Specifies the DIMM Population on a channel (can be added together to specify configuration).
+///< ex. SR_DIMM0 + SR_DIMM1 : Single Rank Dimm in slot 0 AND Slot 1
+///< SR_DIMM0 + DR_DIMM0 + SR_DIMM1 +DR_DIMM1 : Single OR Dual rank in Slot 0 AND Single OR Dual rank in Slot 1
+///
+#define ANY_ 0xFF ///< Any dimm configuration the current channel
+#define SR_DIMM0 0x0001 ///< Single rank dimm in slot 0 on the current channel
+#define SR_DIMM1 0x0010 ///< Single rank dimm in slot 1 on the current channel
+#define SR_DIMM2 0x0100 ///< Single rank dimm in slot 2 on the current channel
+#define SR_DIMM3 0x1000 ///< Single rank dimm in slot 3 on the current channel
+#define DR_DIMM0 0x0002 ///< Dual rank dimm in slot 0 on the current channel
+#define DR_DIMM1 0x0020 ///< Dual rank dimm in slot 1 on the current channel
+#define DR_DIMM2 0x0200 ///< Dual rank dimm in slot 2 on the current channel
+#define DR_DIMM3 0x2000 ///< Dual rank dimm in slot 3 on the current channel
+#define QR_DIMM0 0x0004 ///< Quad rank dimm in slot 0 on the current channel
+#define QR_DIMM1 0x0040 ///< Quad rank dimm in slot 1 on the current channel
+#define QR_DIMM2 0x0400 ///< Quad rank dimm in slot 2 on the current channel
+#define QR_DIMM3 0x4000 ///< Quad rank dimm in slot 3 on the current channel
+#define LR_DIMM0 0x0001 ///< Lrdimm in slot 0 on the current channel
+#define LR_DIMM1 0x0010 ///< Lrdimm in slot 1 on the current channel
+#define LR_DIMM2 0x0100 ///< Lrdimm in slot 2 on the current channel
+#define LR_DIMM3 0x1000 ///< Lrdimm in slot 3 on the current channel
+#define ANY_DIMM0 0x000F ///< Any Dimm combination in slot 0 on the current channel
+#define ANY_DIMM1 0x00F0 ///< Any Dimm combination in slot 1 on the current channel
+#define ANY_DIMM2 0x0F00 ///< Any Dimm combination in slot 2 on the current channel
+#define ANY_DIMM3 0xF000 ///< Any Dimm combination in slot 3 on the current channel
+///
+///< CS POPULATION MASKS
+///< Specifies the CS Population on a channel (can be added together to specify configuration).
+///< ex. CS0 + CS1 : CS0 and CS1 apply to the setting
+///
+#define CS_ANY_ 0xFF ///< Any CS configuration
+#define CS0_ 0x01 ///< CS0 bit map mask
+#define CS1_ 0x02 ///< CS1 bit map mask
+#define CS2_ 0x04 ///< CS2 bit map mask
+#define CS3_ 0x08 ///< CS3 bit map mask
+#define CS4_ 0x10 ///< CS4 bit map mask
+#define CS5_ 0x20 ///< CS5 bit map mask
+#define CS6_ 0x40 ///< CS6 bit map mask
+#define CS7_ 0x80 ///< CS7 bit map mask
+///
+///< Number of Dimms on the current channel
+///< This is a mask used to indicate the number of dimms in a channel
+///< They can be added to indicate multiple conditions (i.e 1 OR 2 Dimms)
+///
+#define ANY_NUM 0xFF ///< Any number of Dimms
+#define NO_DIMM 0x00 ///< No Dimms present
+#define ONE_DIMM 0x01 ///< One dimm Poulated on the current channel
+#define TWO_DIMM 0x02 ///< Two dimms Poulated on the current channel
+#define THREE_DIMM 0x04 ///< Three dimms Poulated on the current channel
+#define FOUR_DIMM 0x08 ///< Four dimms Poulated on the current channel
+
+///
+///< DIMM VOLTAGE MASKS
+///
+#define VOLT_ANY_ 0xFF ///< Any voltage configuration
+#define VOLT1_5_ 0x01 ///< Voltage 1.5V bit map mask
+#define VOLT1_35_ 0x02 ///< Voltage 1.35V bit map mask
+#define VOLT1_25_ 0x04 ///< Voltage 1.25V bit map mask
+
+//
+// < Not applicable
+//
+#define NA_ 0 ///< Not applicable
+
+/*----------------------------------------------------------------------------------------
+ *
+ * Platform Specific Override Definitions for Socket, Channel and Dimm
+ * This indicates where a platform override will be applied.
+ *
+ *----------------------------------------------------------------------------------------
+ */
+///
+///< SOCKET MASKS
+///< Indicates associated processor sockets to apply override settings
+///
+#define ANY_SOCKET 0xFF ///< Apply to all sockets
+#define SOCKET0 0x01 ///< Apply to socket 0
+#define SOCKET1 0x02 ///< Apply to socket 1
+#define SOCKET2 0x04 ///< Apply to socket 2
+#define SOCKET3 0x08 ///< Apply to socket 3
+#define SOCKET4 0x10 ///< Apply to socket 4
+#define SOCKET5 0x20 ///< Apply to socket 5
+#define SOCKET6 0x40 ///< Apply to socket 6
+#define SOCKET7 0x80 ///< Apply to socket 7
+///
+///< CHANNEL MASKS
+///< Indicates Memory channels where override should be applied
+///
+#define ANY_CHANNEL 0xFF ///< Apply to all Memory channels
+#define CHANNEL_A 0x01 ///< Apply to Channel A
+#define CHANNEL_B 0x02 ///< Apply to Channel B
+#define CHANNEL_C 0x04 ///< Apply to Channel C
+#define CHANNEL_D 0x08 ///< Apply to Channel D
+///
+/// DIMM MASKS
+/// Indicates Dimm Slots where override should be applied
+///
+#define ALL_DIMMS 0xFF ///< Apply to all dimm slots
+#define DIMM0 0x01 ///< Apply to Dimm Slot 0
+#define DIMM1 0x02 ///< Apply to Dimm Slot 1
+#define DIMM2 0x04 ///< Apply to Dimm Slot 2
+#define DIMM3 0x08 ///< Apply to Dimm Slot 3
+///
+/// REGISTER ACCESS MASKS
+/// Not supported as an at this time
+///
+#define ACCESS_NB0 0x0
+#define ACCESS_NB1 0x1
+#define ACCESS_NB2 0x2
+#define ACCESS_NB3 0x3
+#define ACCESS_NB4 0x4
+#define ACCESS_PHY 0x5
+#define ACCESS_DCT_XT 0x6
+///
+/// MOTHER BOARD DESIGN LAYERS MASKS
+/// Indicates the layer design of mother board
+///
+#define LAYERS_4 0x0
+#define LAYERS_6 0x1
+/*----------------------------------------------------------------------------------------
+ *
+ * Platform Specific Overriding Table Definitions
+ *
+ *----------------------------------------------------------------------------------------
+ */
+
+#define PSO_END 0 ///< Table End
+#define PSO_CKE_TRI 1 ///< CKE Tristate Map
+#define PSO_ODT_TRI 2 ///< ODT Tristate Map
+#define PSO_CS_TRI 3 ///< CS Tristate Map
+#define PSO_MAX_DIMMS 4 ///< Max Dimms per channel
+#define PSO_CLK_SPEED 5 ///< Clock Speed
+#define PSO_DIMM_TYPE 6 ///< Dimm Type
+#define PSO_MEMCLK_DIS 7 ///< MEMCLK Disable Map
+#define PSO_MAX_CHNLS 8 ///< Max Channels per Socket
+#define PSO_BUS_SPEED 9 ///< Max Memory Bus Speed
+#define PSO_MAX_CHIPSELS 10 ///< Max Chipsel per Channel
+#define PSO_MEM_TECH 11 ///< Channel Memory Type
+#define PSO_WL_SEED 12 ///< DDR3 Write Levelization Seed delay
+#define PSO_RXEN_SEED 13 ///< Hardwared based RxEn seed
+#define PSO_NO_LRDIMM_CS67_ROUTING 14 ///< CS6 and CS7 are not Routed to all Memoy slots on a channel for LRDIMMs
+#define PSO_SOLDERED_DOWN_SODIMM_TYPE 15 ///< Soldered down SODIMM type
+#define PSO_LVDIMM_VOLT1_5_SUPPORT 16 ///< Force LvDimm voltage to 1.5V
+#define PSO_MIN_RD_WR_DATAEYE_WIDTH 17 ///< Min RD/WR dataeye width
+#define PSO_CPU_FAMILY_TO_OVERRIDE 18 ///< CPU family signature to tell following PSO macros are CPU family dependent
+#define PSO_MAX_SOLDERED_DOWN_DIMMS 19 ///< Max Soldered-down Dimms per channel
+#define PSO_MOTHER_BOARD_LAYERS 20 ///< Mother board layer design
+
+/*----------------------------------
+ * CONDITIONAL PSO SPECIFIC ENTRIES
+ *---------------------------------*/
+// Condition Types
+#define CONDITIONAL_PSO_MIN 100 ///< Start of Conditional Entry Types
+#define PSO_CONDITION_AND 100 ///< And Block - Start of Conditional block
+#define PSO_CONDITION_LOC 101 ///< Location - Specify Socket, Channel, Dimms to be affected
+#define PSO_CONDITION_SPD 102 ///< SPD - Specify a specific SPD value on a Dimm on the channel
+#define PSO_CONDITION_REG 103 // Reserved
+#define PSO_CONDITION_MAX 103 ///< End Of Condition Entry Types
+// Action Types
+#define PSO_ACTION_MIN 120 ///< Start of Action Entry Types
+#define PSO_ACTION_ODT 120 ///< ODT values to override
+#define PSO_ACTION_ADDRTMG 121 ///< Address/Timing values to override
+#define PSO_ACTION_ODCCONTROL 122 ///< ODC Control values to override
+#define PSO_ACTION_SLEWRATE 123 ///< Slew Rate value to override
+#define PSO_ACTION_REG 124 // Reserved
+#define PSO_ACTION_SPEEDLIMIT 125 ///< Memory Bus speed Limit based on configuration
+#define PSO_ACTION_MAX 125 ///< End of Action Entry Types
+#define CONDITIONAL_PSO_MAX 139 ///< End of Conditional Entry Types
+
+/*----------------------------------
+ * TABLE DRIVEN PSO SPECIFIC ENTRIES
+ *---------------------------------*/
+// Condition descriptor
+#define PSO_TBLDRV_CONFIG 200 ///< Configuration Descriptor
+
+// Overriding entry types
+#define PSO_TBLDRV_START 210 ///< Start of Table Driven Overriding Entry Types
+#define PSO_TBLDRV_SPEEDLIMIT 210 ///< Speed Limit
+#define PSO_TBLDRV_ODT_RTTNOM 211 ///< RttNom
+#define PSO_TBLDRV_ODT_RTTWR 212 ///< RttWr
+#define PSO_TBLDRV_ODTPATTERN 213 ///< Odt Patterns
+#define PSO_TBLDRV_ADDRTMG 214 ///< Address/Timing values
+#define PSO_TBLDRV_ODCCTRL 215 ///< ODC Control values
+#define PSO_TBLDRV_SLOWACCMODE 216 ///< Slow Access Mode
+#define PSO_TBLDRV_MR0_CL 217 ///< MR0[CL]
+#define PSO_TBLDRV_MR0_WR 218 ///< MR0[WR]
+#define PSO_TBLDRV_RC2_IBT 219 ///< RC2[IBT]
+#define PSO_TBLDRV_RC10_OPSPEED 220 ///< RC10[Opearting Speed]
+#define PSO_TBLDRV_LRDIMM_IBT 221 ///< LrDIMM IBT
+#define PSO_TBLDRV_2D_TRAINING 222 ///< 2D training
+#define PSO_TBLDRV_INVALID_TYPE 223 ///< Invalid Type
+#define PSO_TBLDRV_END 223 ///< End of Table Driven Overriding Entry Types
+
+/*----------------------------------------------------------------------------------------
+ * CONDITIONAL OVERRIDE TABLE MACROS
+ *----------------------------------------------------------------------------------------
+ */
+#define CPU_FAMILY_TO_OVERRIDE(CpuFamilyRevision) \
+ PSO_CPU_FAMILY_TO_OVERRIDE, 4, \
+ ((CpuFamilyRevision) & 0x0FF), (((CpuFamilyRevision) >> 8)& 0x0FF), (((CpuFamilyRevision) >> 16)& 0x0FF), (((CpuFamilyRevision) >> 24)& 0x0FF)
+
+#define MEMCLK_DIS_MAP(SocketID, ChannelID, Bit0Map, Bit1Map, Bit2Map, Bit3Map, Bit4Map, Bit5Map, Bit6Map, Bit7Map) \
+ PSO_MEMCLK_DIS, 11, SocketID, ChannelID, ALL_DIMMS, Bit0Map, Bit1Map, Bit2Map, Bit3Map, Bit4Map, Bit5Map, Bit6Map \
+ , Bit7Map
+
+#define CKE_TRI_MAP(SocketID, ChannelID, Bit0Map, Bit1Map, Bit2Map, Bit3Map) \
+ PSO_CKE_TRI, 7, SocketID, ChannelID, ALL_DIMMS, Bit0Map, Bit1Map, Bit2Map, Bit3Map
+
+#define ODT_TRI_MAP(SocketID, ChannelID, Bit0Map, Bit1Map, Bit2Map, Bit3Map) \
+ PSO_ODT_TRI, 7, SocketID, ChannelID, ALL_DIMMS, Bit0Map, Bit1Map, Bit2Map, Bit3Map
+
+#define CS_TRI_MAP(SocketID, ChannelID, Bit0Map, Bit1Map, Bit2Map, Bit3Map, Bit4Map, Bit5Map, Bit6Map, Bit7Map) \
+ PSO_CS_TRI, 11, SocketID, ChannelID, ALL_DIMMS, Bit0Map, Bit1Map, Bit2Map, Bit3Map, Bit4Map, Bit5Map, Bit6Map, Bit7Map
+
+#define NUMBER_OF_DIMMS_SUPPORTED(SocketID, ChannelID, NumberOfDimmSlotsPerChannel) \
+ PSO_MAX_DIMMS, 4, SocketID, ChannelID, ALL_DIMMS, NumberOfDimmSlotsPerChannel
+
+#define NUMBER_OF_SOLDERED_DOWN_DIMMS_SUPPORTED(SocketID, ChannelID, NumberOfSolderedDownDimmsPerChannel) \
+ PSO_MAX_SOLDERED_DOWN_DIMMS, 4, SocketID, ChannelID, ALL_DIMMS, NumberOfSolderedDownDimmsPerChannel
+
+#define NUMBER_OF_CHIP_SELECTS_SUPPORTED(SocketID, ChannelID, NumberOfChipSelectsPerChannel) \
+ PSO_MAX_CHIPSELS, 4, SocketID, ChannelID, ALL_DIMMS, NumberOfChipSelectsPerChannel
+
+#define NUMBER_OF_CHANNELS_SUPPORTED(SocketID, NumberOfChannelsPerSocket) \
+ PSO_MAX_CHNLS, 4, SocketID, ANY_CHANNEL, ALL_DIMMS, NumberOfChannelsPerSocket
+
+#define OVERRIDE_DDR_BUS_SPEED(SocketID, ChannelID, TimingMode, BusSpeed) \
+ PSO_BUS_SPEED, 11, SocketID, ChannelID, ALL_DIMMS, TimingMode, (TimingMode >> 8), (TimingMode >> 16), (TimingMode >> 24), \
+ BusSpeed, (BusSpeed >> 8), (BusSpeed >> 16), (BusSpeed >> 24)
+
+#define DRAM_TECHNOLOGY(SocketID, MemTechType) \
+ PSO_MEM_TECH, 7, SocketID, ANY_CHANNEL, ALL_DIMMS, MemTechType, (MemTechType >> 8), (MemTechType >> 16), (MemTechType >> 24)
+
+#define WRITE_LEVELING_SEED(SocketID, ChannelID, DimmID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed, \
+ Byte6Seed, Byte7Seed, ByteEccSeed) \
+ PSO_WL_SEED, 12, SocketID, ChannelID, DimmID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed, \
+ Byte6Seed, Byte7Seed, ByteEccSeed
+
+#define HW_RXEN_SEED(SocketID, ChannelID, DimmID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed, \
+ Byte6Seed, Byte7Seed, ByteEccSeed) \
+ PSO_RXEN_SEED, 21, SocketID, ChannelID, DimmID, Byte0Seed, (Byte0Seed >> 8), Byte1Seed, (Byte1Seed >> 8), Byte2Seed, (Byte2Seed >> 8), \
+ Byte3Seed, (Byte3Seed >> 8), Byte4Seed, (Byte4Seed >> 8), Byte5Seed, (Byte5Seed >> 8), Byte6Seed, (Byte6Seed >> 8), \
+ Byte7Seed, (Byte7Seed >> 8), ByteEccSeed, (ByteEccSeed >> 8)
+
+#define NO_LRDIMM_CS67_ROUTING(SocketID, ChannelID) \
+ PSO_NO_LRDIMM_CS67_ROUTING, 4, SocketID, ChannelID, ALL_DIMMS, TRUE
+
+#define SOLDERED_DOWN_SODIMM_TYPE(SocketID, ChannelID) \
+ PSO_SOLDERED_DOWN_SODIMM_TYPE, 4, SocketID, ChannelID, ALL_DIMMS, TRUE
+
+#define LVDIMM_FORCE_VOLT1_5_FOR_D0 \
+ PSO_LVDIMM_VOLT1_5_SUPPORT, 4, ANY_SOCKET, ANY_CHANNEL, ALL_DIMMS, TRUE
+
+#define MIN_RD_WR_DATAEYE_WIDTH(SocketID, ChannelID, MinRdDataeyeWidth, MinWrDataeyeWidth) \
+ PSO_MIN_RD_WR_DATAEYE_WIDTH, 5, SocketID, ChannelID, ALL_DIMMS, MinRdDataeyeWidth, MinWrDataeyeWidth
+
+#define MOTHER_BOARD_LAYERS(Layers) \
+ PSO_MOTHER_BOARD_LAYERS, 4, ANY_SOCKET, ANY_CHANNEL, ALL_DIMMS, Layers
+
+#define MAX_NUMBER_PSO_TABLES 13
+/*----------------------------------------------------------------------------------------
+ * CONDITIONAL OVERRIDE TABLE MACROS
+ *----------------------------------------------------------------------------------------
+ */
+#define CONDITION_AND \
+ PSO_CONDITION_AND, 0
+
+#define COND_LOC(SocketMsk, ChannelMsk, DimmMsk) \
+ PSO_CONDITION_LOC, 3, SocketMsk, ChannelMsk, DimmMsk
+
+#define COND_SPD(Byte, Mask, Value) \
+ PSO_CONDITION_SPD, 3, Byte, Mask, Value
+
+#define COND_REG(Access, Offset, Mask, Value) \
+ PSO_CONDITION_REG, 11, Access, (Offset & 0x0FF), (Offset >> 8), \
+ ((Mask) & 0x0FF), (((Mask) >> 8) & 0x0FF), (((Mask) >> 16) & 0x0FF), (((Mask) >> 24) & 0x0FF), \
+ ((Value) & 0x0FF), (((Value) >> 8) & 0x0FF), (((Value) >> 16) & 0x0FF), (((Value) >> 24) & 0x0FF)
+
+#define ACTION_ODT(Frequency, Dimms, QrDimms, DramOdt, QrDramOdt, DramDynOdt) \
+ PSO_ACTION_ODT, 9, \
+ ((Frequency) & 0x0FF), (((Frequency) >> 8)& 0x0FF), (((Frequency) >> 16)& 0x0FF), ((Frequency >> 24)& 0x0FF), \
+ Dimms, QrDimms, DramOdt, QrDramOdt, DramDynOdt
+
+#define ACTION_ADDRTMG(Frequency, DimmConfig, AddrTmg) \
+ PSO_ACTION_ADDRTMG, 10, \
+ ((Frequency) & 0x0FF), (((Frequency) >> 8)& 0x0FF), (((Frequency) >> 16)& 0x0FF), (((Frequency) >> 24)& 0x0FF), \
+ ((DimmConfig) & 0x0FF), (((DimmConfig) >> 8) & 0x0FF), \
+ (AddrTmg & 0x0FF), ((AddrTmg >> 8)& 0x0FF), ((AddrTmg >> 16)& 0x0FF), ((AddrTmg >> 24)& 0x0FF)
+
+#define ACTION_ODCCTRL(Frequency, DimmConfig, OdcCtrl) \
+ PSO_ACTION_ODCCONTROL, 10, \
+ ((Frequency) & 0x0FF), (((Frequency) >> 8)& 0x0FF), (((Frequency) >> 16)& 0x0FF), (((Frequency) >> 24)& 0x0FF), \
+ ((DimmConfig) & 0x0FF), (((DimmConfig) >> 8) & 0x0FF), \
+ (OdcCtrl & 0x0FF), ((OdcCtrl >> 8)& 0x0FF), ((OdcCtrl >> 16)& 0x0FF), ((OdcCtrl >> 24)& 0x0FF)
+
+#define ACTION_SLEWRATE(Frequency, DimmConfig, SlewRate) \
+ PSO_ACTION_SLEWRATE, 10, \
+ ((Frequency) & 0x0FF), (((Frequency) >> 8)& 0x0FF), (((Frequency) >> 16)& 0x0FF), (((Frequency) >> 24)& 0x0FF), \
+ ((DimmConfig) & 0x0FF), (((DimmConfig) >> 8) & 0x0FF), \
+ (SlewRate & 0x0FF), ((SlewRate >> 8)& 0x0FF), ((SlewRate >> 16)& 0x0FF), ((SlewRate >> 24)& 0x0FF)
+
+#define ACTION_SPEEDLIMIT(DimmConfig, Dimms, SpeedLimit15, SpeedLimit135, SpeedLimit125) \
+ PSO_ACTION_SPEEDLIMIT, 9, \
+ ((DimmConfig) & 0x0FF), (((DimmConfig) >> 8) & 0x0FF), Dimms, \
+ (SpeedLimit15 & 0x0FF), ((SpeedLimit15 >> 8)& 0x0FF), \
+ (SpeedLimit135 & 0x0FF), ((SpeedLimit135 >> 8)& 0x0FF), \
+ (SpeedLimit125 & 0x0FF), ((SpeedLimit125 >> 8)& 0x0FF)
+
+
+#define MEMCLK_DIS_MAP_SIZE 13
+#define CKE_TRI_MAP_SIZE 9
+#define ODT_TRI_MAP_SIZE 9
+#define CS_TRI_MAP_SIZE 13
+#define NUMBER_OF_DIMMS_SUPPORTED_SIZE 6
+#define NUMBER_OF_SOLDERED_DOWN_DIMMS_SUPPORTED_SIZE 6
+#define NUMBER_OF_CHIP_SELECTS_SUPPORTED_SIZE 6
+#define NUMBER_OF_CHANNELS_SUPPORTED_SIZE 6
+#define OVERRIDE_DDR_BUS_SPEED_SIZE 13
+#define DRAM_TECHNOLOGY_SIZE 9
+#define SOLDERED_DOWN_SODIMM_TYPE_SIZE 6
+#define MEMORY_POWER_POLICY_OVERRIDE_SIZE 6
+#define MOTHER_BOARD_LAYERS_SIZE 6
+
+
+
+/*----------------------------------------------------------------------------------------
+ * END OF CONDITIONAL OVERRIDE TABLE MACROS
+ *----------------------------------------------------------------------------------------
+ */
+/*----------------------------------------------------------------------------------------
+ * TABLE DRIVEN OVERRIDE MACROS
+ *----------------------------------------------------------------------------------------
+ */
+/// Configuration sub-descriptors
+typedef enum {
+ CONFIG_GENERAL, ///< CONFIG_GENERAL
+ CONFIG_SPEEDLIMIT, ///< CONFIG_SPEEDLIMIT
+ CONFIG_RC2IBT, ///< CONFIG_RC2IBT
+ CONFIG_DONT_CARE, ///< CONFIG_DONT_CARE
+} Config_Type;
+
+// ====================
+// Configuration Macros
+// ====================
+#define TBLDRV_CONFIG_TO_OVERRIDE(DimmPerCH, Frequency, DimmVolt, DimmConfig) \
+ PSO_TBLDRV_CONFIG, 9, \
+ CONFIG_GENERAL, \
+ DimmPerCH, DimmVolt, \
+ ((Frequency) & 0x0FF), (((Frequency) >> 8)& 0x0FF), (((Frequency) >> 16)& 0x0FF), (((Frequency) >> 24)& 0x0FF), \
+ ((DimmConfig) & 0x0FF), (((DimmConfig) >> 8) & 0x0FF)
+
+#define TBLDRV_SPEEDLIMIT_CONFIG_TO_OVERRIDE(DimmPerCH, Dimms, NumOfSR, NumOfDR, NumOfQR, NumOfLRDimm) \
+ PSO_TBLDRV_CONFIG, 7, \
+ CONFIG_SPEEDLIMIT, \
+ DimmPerCH, Dimms, NumOfSR, NumOfDR, NumOfQR, NumOfLRDimm
+
+#define TBLDRV_RC2IBT_CONFIG_TO_OVERRIDE(DimmPerCH, Frequency, DimmVolt, DimmConfig, NumOfReg) \
+ PSO_TBLDRV_CONFIG, 10, \
+ CONFIG_RC2IBT, \
+ DimmPerCH, DimmVolt, \
+ ((Frequency) & 0x0FF), (((Frequency) >> 8)& 0x0FF), (((Frequency) >> 16)& 0x0FF), (((Frequency) >> 24)& 0x0FF), \
+ ((DimmConfig) & 0x0FF), (((DimmConfig) >> 8) & 0x0FF), \
+ NumOfReg
+
+//==================
+// Overriding Macros
+//==================
+#define TBLDRV_CONFIG_ENTRY_SPEEDLIMIT(SpeedLimit1_5, SpeedLimit1_35, SpeedLimit1_25) \
+ PSO_TBLDRV_SPEEDLIMIT, 6, \
+ (SpeedLimit1_5 & 0x0FF), ((SpeedLimit1_5 >> 8)& 0x0FF), \
+ (SpeedLimit1_35 & 0x0FF), ((SpeedLimit1_35 >> 8)& 0x0FF), \
+ (SpeedLimit1_25 & 0x0FF), ((SpeedLimit1_25 >> 8)& 0x0FF)
+
+#define TBLDRV_CONFIG_ENTRY_ODT_RTTNOM(TgtCS, RttNom) \
+ PSO_TBLDRV_ODT_RTTNOM, 2, \
+ TgtCS, RttNom
+
+#define TBLDRV_CONFIG_ENTRY_ODT_RTTWR(TgtCS, RttWr) \
+ PSO_TBLDRV_ODT_RTTWR, 2, \
+ TgtCS, RttWr
+
+#define TBLDRV_CONFIG_ENTRY_ODTPATTERN(RdODTCSHigh, RdODTCSLow, WrODTCSHigh, WrODTCSLow) \
+ PSO_TBLDRV_ODTPATTERN, 16, \
+ ((RdODTCSHigh) & 0x0FF), (((RdODTCSHigh) >> 8)& 0x0FF), (((RdODTCSHigh) >> 16)& 0x0FF), (((RdODTCSHigh) >> 24)& 0x0FF), \
+ ((RdODTCSLow) & 0x0FF), (((RdODTCSLow) >> 8)& 0x0FF), (((RdODTCSLow) >> 16)& 0x0FF), (((RdODTCSLow) >> 24)& 0x0FF), \
+ ((WrODTCSHigh) & 0x0FF), (((WrODTCSHigh) >> 8)& 0x0FF), (((WrODTCSHigh) >> 16)& 0x0FF), (((WrODTCSHigh) >> 24)& 0x0FF), \
+ ((WrODTCSLow) & 0x0FF), (((WrODTCSLow) >> 8)& 0x0FF), (((WrODTCSLow) >> 16)& 0x0FF), (((WrODTCSLow) >> 24)& 0x0FF)
+
+#define TBLDRV_CONFIG_ENTRY_ADDRTMG(AddrTmg) \
+ PSO_TBLDRV_ADDRTMG, 4, \
+ ((AddrTmg) & 0x0FF), (((AddrTmg) >> 8)& 0x0FF), (((AddrTmg) >> 16)& 0x0FF), (((AddrTmg) >> 24)& 0x0FF)
+
+#define TBLDRV_CONFIG_ENTRY_ODCCTRL(OdcCtrl) \
+ PSO_TBLDRV_ODCCTRL, 4, \
+ ((OdcCtrl) & 0x0FF), (((OdcCtrl) >> 8)& 0x0FF), (((OdcCtrl) >> 16)& 0x0FF), (((OdcCtrl) >> 24)& 0x0FF)
+
+#define TBLDRV_CONFIG_ENTRY_SLOWACCMODE(SlowAccMode) \
+ PSO_TBLDRV_SLOWACCMODE, 1, \
+ SlowAccMode
+
+#define TBLDRV_CONFIG_ENTRY_RC2_IBT(TgtDimm, IBT) \
+ PSO_TBLDRV_RC2_IBT, 2, \
+ TgtDimm, IBT
+
+#define TBLDRV_OVERRIDE_MR0_CL(RegValOfTcl, MR0CL13, MR0CL0) \
+ PSO_TBLDRV_CONFIG, 1, \
+ CONFIG_DONT_CARE, \
+ PSO_TBLDRV_MR0_CL, 3, \
+ RegValOfTcl, MR0CL13, MR0CL0
+
+#define TBLDRV_OVERRIDE_MR0_WR(RegValOfTwr, MR0WR) \
+ PSO_TBLDRV_CONFIG, 1, \
+ CONFIG_DONT_CARE, \
+ PSO_TBLDRV_MR0_WR, 2, \
+ RegValOfTwr, MR0WR
+
+#define TBLDRV_OVERRIDE_RC10_OPSPEED(Frequency, MR10OPSPEED) \
+ PSO_TBLDRV_CONFIG, 1, \
+ CONFIG_DONT_CARE, \
+ PSO_TBLDRV_RC10_OPSPEED, 5, \
+ ((Frequency) & 0x0FF), (((Frequency) >> 8)& 0x0FF), (((Frequency) >> 16)& 0x0FF), (((Frequency) >> 24)& 0x0FF), \
+ MR10OPSPEED
+
+#define TBLDRV_CONFIG_ENTRY_LRDMM_IBT(F0RC8, F1RC0, F1RC1, F1RC2) \
+ PSO_TBLDRV_LRDIMM_IBT, 4, \
+ F0RC8, F1RC0, F1RC1, F1RC2
+
+#define TBLDRV_CONFIG_ENTRY_2D_TRAINING(Training2dMode) \
+ PSO_TBLDRV_2D_TRAINING, 1, \
+ Training2dMode
+
+//============================
+// Macros for removing entries
+//============================
+#define INVALID_CONFIG_FLAG 0x8000
+
+#define TBLDRV_INVALID_CONFIG \
+ PSO_TBLDRV_INVALID_TYPE, 0
+
+/*----------------------------------------------------------------------------------------
+ * END OF TABLE DRIVEN OVERRIDE MACROS
+ *----------------------------------------------------------------------------------------
+ */
+
+#endif // _PLATFORM_MEMORY_CONFIGURATION_H_
diff --git a/src/vendorcode/amd/pi/00660F01/Include/Topology.h b/src/vendorcode/amd/pi/00660F01/Include/Topology.h
new file mode 100644
index 0000000..099142e
--- /dev/null
+++ b/src/vendorcode/amd/pi/00660F01/Include/Topology.h
@@ -0,0 +1,86 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Topology interface definitions.
+ *
+ * Contains AMD AGESA internal interface for topology related data which
+ * is consumed by code other than Topology Services init.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: Core
+ * @e \$Revision: 309090 $ @e \$Date: 2014-12-09 12:28:05 -0600 (Tue, 09 Dec 2014) $
+ */
+ /*****************************************************************************
+ *
+ * Copyright (c) 2008 - 2015, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ***************************************************************************/
+
+#ifndef _TOPOLOGY_H_
+#define _TOPOLOGY_H_
+
+// Defines for limiting data structure maximum allocation and limit checking.
+#define MAX_NODES 1
+#define MAX_SOCKETS MAX_NODES
+#define MAX_DIES 1
+
+/**
+ * Socket and Module to Node Map Item.
+ * Provide the Node Id and core id range for each module in each processor.
+ */
+typedef struct {
+ UINT8 Node; ///< The module's Node id.
+ UINT8 LowCore; ///< The lowest processor core id for this module.
+ UINT8 HighCore; ///< The highest processor core id for this module.
+ UINT8 EnabledComputeUnits; ///< The value of Enabled for this processor module.
+ UINT8 DualCoreComputeUnits; ///< The value of DualCore for this processor module.
+ UINT8 TripleCoreComputeUnits;///< The value of TripleCore for this processor module.
+ UINT8 QuadCoreComputeUnits; ///< The value of QuadCore for this processor module.
+} SOCKET_DIE_TO_NODE_ITEM;
+
+/**
+ * Socket and Module to Node Map.
+ * This type is a pointer to the actual map, it can be used for a struct item or
+ * for typecasting a heap buffer pointer.
+ */
+typedef SOCKET_DIE_TO_NODE_ITEM (*SOCKET_DIE_TO_NODE_MAP)[MAX_SOCKETS][MAX_DIES];
+
+/**
+ * Node id to Socket Die Map Item.
+ */
+typedef struct {
+ UINT8 Socket; ///< socket of the processor containing the Node.
+ UINT8 Die; ///< the module in the processor which is Node.
+} NODE_TO_SOCKET_DIE_ITEM;
+
+/**
+ * Node id to Socket Die Map.
+ */
+typedef NODE_TO_SOCKET_DIE_ITEM (*NODE_TO_SOCKET_DIE_MAP)[MAX_NODES];
+
+#endif // _TOPOLOGY_H_
diff --git a/src/vendorcode/amd/pi/00660F01/Porting.h b/src/vendorcode/amd/pi/00660F01/Porting.h
new file mode 100644
index 0000000..f23f309
--- /dev/null
+++ b/src/vendorcode/amd/pi/00660F01/Porting.h
@@ -0,0 +1,286 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Describes compiler dependencies - to support several compile time environments
+ *
+ * Contains compiler environment porting descriptions
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: Includes
+ * @e \$Revision: 309090 $ @e \$Date: 2014-12-09 12:28:05 -0600 (Tue, 09 Dec 2014) $
+ */
+/*****************************************************************************
+ *
+ * Copyright 2008 - 2015 ADVANCED MICRO DEVICES, INC. All Rights Reserved.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ***************************************************************************/
+
+#ifndef _PORTING_H_
+#define _PORTING_H_
+
+#if defined (_MSC_VER)
+ #include <intrin.h>
+ void _disable (void);
+ void _enable (void);
+ #pragma warning(disable: 4103 4001 4733)
+ #pragma intrinsic (_disable, _enable)
+ #pragma warning(push)
+ // -----------------------------------------------------------------------
+ // Define a code_seg MACRO
+ //
+ #define MAKE_AS_A_STRING(arg) #arg
+
+ #define CODE_GROUP(arg) __pragma (code_seg (MAKE_AS_A_STRING (.t##arg)))
+
+ #define RDATA_GROUP(arg) __pragma (const_seg (MAKE_AS_A_STRING (.d##arg)))
+ #define FUNC_ATTRIBUTE(arg) __declspec(arg)
+ //#include <intrin.h> // MS has built-in functions
+
+ #if _MSC_VER < 900
+ // -----------------------------------------------------------------------
+ // Assume MSVC 1.52C (16-bit)
+ //
+ // NOTE: When using MSVC 1.52C use the following command line:
+ //
+ // CL.EXE /G3 /AL /O1i /Fa <FILENAME.C>
+ //
+ // This will produce 32-bit code in USE16 segment that is optimized for code
+ // size.
+ typedef void VOID;
+
+ // Create the universal 32, 16, and 8-bit data types
+ typedef unsigned long UINTN;
+ typedef long INT32;
+ typedef unsigned long UINT32;
+ typedef int INT16;
+ typedef unsigned int UINT16;
+ typedef char INT8;
+ typedef unsigned char UINT8;
+ typedef char CHAR8;
+ typedef unsigned short CHAR16;
+
+ /// struct for 16-bit environment handling of 64-bit value
+ typedef struct _UINT64 {
+ IN OUT UINT32 lo; ///< lower 32-bits of 64-bit value
+ IN OUT UINT32 hi; ///< highest 32-bits of 64-bit value
+ } UINT64;
+
+ // Create the Boolean type
+ #define TRUE 1
+ #define FALSE 0
+ typedef unsigned char BOOLEAN;
+
+ #define CONST const
+ #define STATIC static
+ #define VOLATILE volatile
+ #define CALLCONV __pascal
+ #define ROMDATA __based( __segname( "_CODE" ) )
+ #define _16BYTE_ALIGN __declspec(align(16))
+
+ // Force tight packing of structures
+ // Note: Entire AGESA (Project / Solution) will be using pragma pack 1
+ #pragma warning( disable : 4103 ) // Disable '#pragma pack' in .h warning
+ #pragma pack(1)
+
+ // Disable WORD->BYTE automatic conversion warnings. Example:
+ // BYTE LocalByte;
+ // void MyFunc(BYTE val);
+ //
+ // MyFunc(LocalByte*2+1); // Warning, automatic conversion
+ //
+ // The problem is any time math is performed on a BYTE, it is converted to a
+ // WORD by MSVC 1.52c, and then when it is converted back to a BYTE, a warning
+ // is generated. Disable warning C4761
+ #pragma warning( disable : 4761 )
+
+ #else
+ // -----------------------------------------------------------------------
+ // Assume a 32-bit MSVC++
+ //
+ // Disable the following warnings:
+ // 4100 - 'identifier' : unreferenced formal parameter
+ // 4276 - 'function' : no prototype provided; assumed no parameters
+ // 4214 - non standard extension used : bit field types other than int
+ // 4001 - nonstandard extension 'single line comment' was used
+ // 4142 - benign redefinition of type for following declaration
+ // - typedef char INT8
+ #if defined (_M_IX86)
+ #pragma warning (disable: 4100 4276 4214 4001 4142 4305 4306)
+
+ #ifndef VOID
+ typedef void VOID;
+ #endif
+ // Create the universal 32, 16, and 8-bit data types
+ #ifndef UINTN
+ typedef unsigned __w64 UINTN;
+ #endif
+ typedef __int64 INT64;
+ typedef unsigned __int64 UINT64;
+ typedef int INT32;
+ typedef unsigned int UINT32;
+ typedef short INT16;
+ typedef unsigned short UINT16;
+ typedef char INT8;
+ typedef unsigned char UINT8;
+ typedef char CHAR8;
+ typedef unsigned short CHAR16;
+
+ // Create the Boolean type
+ #ifndef TRUE
+ #define TRUE 1
+ #endif
+ #ifndef FALSE
+ #define FALSE 0
+ #endif
+ typedef unsigned char BOOLEAN;
+
+ // Force tight packing of structures
+ // Note: Entire AGESA (Project / Solution) will be using pragma pack 1
+ #pragma pack(1)
+
+ #define CONST const
+ #define STATIC static
+ #define VOLATILE volatile
+ #define CALLCONV
+ #define ROMDATA
+ #define _16BYTE_ALIGN __declspec(align(64))
+ // 64 bit of compiler
+ #else
+ #pragma warning (disable: 4100 4276 4214 4001 4142 4305 4306 4366)
+
+ #ifndef VOID
+ typedef void VOID;
+ #endif
+ // Create the universal 32, 16, and 8-bit data types
+ #ifndef UINTN
+ typedef unsigned __int64 UINTN;
+ #endif
+ typedef __int64 INT64;
+ typedef unsigned __int64 UINT64;
+ typedef int INT32;
+ typedef unsigned int UINT32;
+ typedef short INT16;
+ typedef unsigned short UINT16;
+ typedef char INT8;
+ typedef unsigned char UINT8;
+ typedef char CHAR8;
+ typedef unsigned short CHAR16;
+
+ // Create the Boolean type
+ #ifndef TRUE
+ #define TRUE 1
+ #endif
+ #ifndef FALSE
+ #define FALSE 0
+ #endif
+ typedef unsigned char BOOLEAN;
+
+ // Force tight packing of structures
+ // Note: Entire AGESA (Project / Solution) will be using pragma pack 1
+ #pragma pack(1)
+
+ #define CONST const
+ #define STATIC static
+ #define VOLATILE volatile
+ #define CALLCONV
+ #define ROMDATA
+ #endif
+ #endif
+ // -----------------------------------------------------------------------
+ // End of MS compiler versions
+
+#elif defined __GNUC__
+
+ #define IN
+ #define OUT
+ #define STATIC static
+ #define VOLATILE volatile
+ #define TRUE 1
+ #define FALSE 0
+// #undef CONST
+ #define CONST const
+ #define ROMDATA
+ #define CALLCONV
+ #define _16BYTE_ALIGN __attribute__ ((aligned (16)))
+ #define _8BYTE_ALIGN __attribute__ ((aligned (8)))
+ #define _4BYTE_ALIGN __attribute__ ((aligned (4)))
+ #define _2BYTE_ALIGN __attribute__ ((aligned (2)))
+ #define _1BYTE_ALIGN __attribute__ ((aligned (1)))
+
+ typedef unsigned char BOOLEAN;
+ typedef signed char INT8;
+ typedef signed short INT16;
+ typedef signed long INT32;
+ typedef char CHAR8;
+ typedef unsigned char UINT8;
+ typedef unsigned short UINT16;
+ typedef unsigned long UINT32;
+ typedef unsigned long UINTN;
+ typedef unsigned long long UINT64;
+ typedef long long INT64;
+ typedef void VOID;
+ //typedef unsigned long size_t;
+
+ //#include <intrin.h> // MingW-w64 library header
+#pragma pack(1)
+
+#define CODE_GROUP(arg)
+#define RDATA_GROUP(arg)
+
+#define FUNC_ATTRIBUTE(arg) __attribute__((arg))
+#define MAKE_AS_A_STRING(arg) #arg
+#include <stddef.h>
+#include "gcc-intrin.h"
+
+#include <assert.h>
+#include <console/console.h>
+#include <console/loglevel.h>
+
+#ifndef NULL
+ #define NULL (void *)0
+#endif
+
+#else
+ // -----------------------------------------------------------------------
+ // Unknown or unsupported compiler
+ //
+ #error "Unknown compiler in use"
+#endif
+
+// -----------------------------------------------------------------------
+// Common definitions for all compilers
+//
+
+//Support forward reference construct
+#define AGESA_FORWARD_DECLARATION(x) typedef struct _##x x
+
+// The following are use in conformance to the UEFI style guide
+#define IN
+#define OUT
+
+#endif // _PORTING_H_
diff --git a/src/vendorcode/amd/pi/00660F01/Proc/CPU/Family/cpuFamRegisters.h b/src/vendorcode/amd/pi/00660F01/Proc/CPU/Family/cpuFamRegisters.h
new file mode 100644
index 0000000..c4be628
--- /dev/null
+++ b/src/vendorcode/amd/pi/00660F01/Proc/CPU/Family/cpuFamRegisters.h
@@ -0,0 +1,92 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD CPU Register Table Related Functions
+ *
+ * Contains the definition of the CPU CPUID MSRs and PCI registers with BKDG recommended values
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: CPU
+ * @e \$Revision: 309899 $ @e \$Date: 2014-12-23 02:21:13 -0600 (Tue, 23 Dec 2014) $
+ *
+ */
+ /*****************************************************************************
+ *
+ * Copyright (c) 2008 - 2015, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ***************************************************************************/
+
+#ifndef _CPU_FAM_REGISTERS_H_
+#define _CPU_FAM_REGISTERS_H_
+
+/*
+ *--------------------------------------------------------------
+ *
+ * M O D U L E S U S E D
+ *
+ *---------------------------------------------------------------
+ */
+
+/*
+ *--------------------------------------------------------------
+ *
+ * D E F I N I T I O N S / M A C R O S
+ *
+ *---------------------------------------------------------------
+ */
+
+// This define should be equal to the total number of families
+// in the cpuFamily enum.
+#define MAX_CPU_FAMILIES 15
+#define MAX_CPU_REVISIONS 15 // Max Cpu Revisions Per Family
+
+// CPU_LOGICAL_ID.Family equates
+// Family 15h equates
+#define AMD_FAMILY_15_CZ 0x0004u
+#define AMD_FAMILY_CZ (AMD_FAMILY_15_CZ)
+#define AMD_FAMILY_15 AMD_FAMILY_15_CZ
+
+// Family Unknown
+#define AMD_FAMILY_UNKNOWN 0x8000u
+
+
+// Family 15h CPU_LOGICAL_ID.Revision equates
+// -------------------------------------
+
+ // Family 15h CZ steppings
+#define AMD_F15_CZ_A0 0x0001u
+#define AMD_F15_CZ_A1 0x0002u
+ // Family 15h Unknown stepping
+#define AMD_F15_UNKNOWN 0x8000u
+#define AMD_F15_CZ_Ax (AMD_F15_CZ_A0 | AMD_F15_CZ_A1)
+#define AMD_F15_CZ_ALL (AMD_F15_CZ_Ax)
+
+#define AMD_F15_ALL AMD_F15_CZ_ALL
+
+#endif // _CPU_FAM_REGISTERS_H_
+
diff --git a/src/vendorcode/amd/pi/00660F01/Proc/CPU/Feature/cpuCacheInit.h b/src/vendorcode/amd/pi/00660F01/Proc/CPU/Feature/cpuCacheInit.h
new file mode 100644
index 0000000..3ee71cd
--- /dev/null
+++ b/src/vendorcode/amd/pi/00660F01/Proc/CPU/Feature/cpuCacheInit.h
@@ -0,0 +1,137 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD CPU Execution Cache Allocation functions.
+ *
+ * Contains code for doing Execution Cache Allocation for ROM space
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: CPU
+ * @e \$Revision: 309090 $ @e \$Date: 2014-12-09 12:28:05 -0600 (Tue, 09 Dec 2014) $
+ *
+ */
+ /*****************************************************************************
+ *
+ * Copyright (c) 2008 - 2015, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ***************************************************************************/
+
+#ifndef _CPU_CACHE_INIT_H_
+#define _CPU_CACHE_INIT_H_
+
+/*----------------------------------------------------------------------------
+ * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*-----------------------------------------------------------------------------
+ * DEFINITIONS AND MACROS
+ *
+ *-----------------------------------------------------------------------------
+ */
+#define BSP_STACK_SIZE_64K 65536
+#define BSP_STACK_SIZE_32K 32768
+
+#define CORE0_STACK_SIZE 16384
+#define CORE1_STACK_SIZE 4096
+
+#define AMD_MTRR_FIX4K_BASE 0x268
+#define AMD_MTRR_VARIABLE_BASE6 0x20C
+#define AMD_MTRR_VARIABLE_BASE7 0x20E
+
+#define WP_IO 0x0505050505050505ull
+
+#define AGESA_CACHE_SIZE_REDUCED 1
+#define AGESA_CACHE_REGIONS_ACROSS_1MB 2
+#define AGESA_CACHE_REGIONS_ACROSS_4GB 3
+#define AGESA_REGION_NOT_ALIGNED_ON_BOUNDARY 4
+#define AGESA_CACHE_START_ADDRESS_LESS_D0000 5
+#define AGESA_THREE_CACHE_REGIONS_ABOVE_1MB 6
+#define AGESA_DEALLOCATE_CACHE_REGIONS 7
+
+/*----------------------------------------------------------------------------
+ * TYPEDEFS, STRUCTURES, ENUMS
+ *
+ *----------------------------------------------------------------------------
+ */
+/// Cache-As-Ram Executable region allocation modes
+typedef enum {
+ LimitedByL2Size, ///< Execution space must be allocated from L2
+ InfiniteExe, ///< Family can support unlimited Execution space
+ MaxCarExeMode ///< Used as limit or bounds check
+} CAR_EXE_MODE;
+
+/// Cache Information
+typedef struct {
+ IN UINT32 BspStackSize; ///< Stack size of BSP
+ IN UINT32 Core0StackSize; ///< Stack size of primary cores
+ IN UINT32 Core1StackSize; ///< Stack size of all non primary cores
+ IN UINT32 MemTrainingBufferSize; ///< Memory training buffer size
+ IN UINT32 SharedMemSize; ///< Shared memory size
+ IN UINT64 VariableMtrrMask; ///< Mask to apply before variable MTRR writes
+ IN UINT64 VariableMtrrHeapMask; ///< Mask to apply before variable MTRR writes for use in heap init.
+ IN UINT64 HeapBaseMask; ///< Mask used for the heap MTRR settings
+ IN CAR_EXE_MODE CarExeType; ///< Indicates which algorithm to use when allocating EXE space
+} CACHE_INFO;
+
+/// Merged memory region overlap type
+typedef enum {
+ EmptySet, ///< One of the regions is zero length
+ Disjoint, ///< The two regions do not touch
+ Adjacent, ///< one region is next to the other, no gap
+ CommonEnd, ///< regions overlap with a common end point
+ Extending, ///< the 2nd region is extending the size of the 1st
+ Contained, ///< the 2nd region is wholely contained inside the 1st
+ CommonStartContained, ///< the 2nd region is contained in the 1st with a common start
+ Identity, ///< the two regions are the same
+ CommonStartExtending, ///< the 2nd region has same start as 1st, but is larger size
+ NotCombinable ///< the combined regions do not follow the cache block rules
+} OVERLAP_TYPE;
+
+/// Result of merging two memory regions for cache coverage
+typedef struct {
+ IN OUT UINT32 MergedStartAddr; ///< Start address of the merged regions
+ IN OUT UINT32 MergedSize; ///< Size of the merged regions
+ OUT UINT32 OverlapAmount; ///< the size of the overlapping section
+ OUT OVERLAP_TYPE OverlapType; ///< indicates how the two regions overlap
+} MERGED_CACHE_REGION;
+
+/*----------------------------------------------------------------------------
+ * FUNCTIONS PROTOTYPE
+ *
+ *----------------------------------------------------------------------------
+ */
+AGESA_STATUS
+AllocateExecutionCache (
+ IN AMD_CONFIG_PARAMS *StdHeader,
+ IN EXECUTION_CACHE_REGION *AmdExeAddrMapPtr
+ );
+
+#endif // _CPU_CACHE_INIT_H_
+
diff --git a/src/vendorcode/amd/pi/00660F01/Proc/CPU/cpuEarlyInit.h b/src/vendorcode/amd/pi/00660F01/Proc/CPU/cpuEarlyInit.h
new file mode 100644
index 0000000..7efbc52
--- /dev/null
+++ b/src/vendorcode/amd/pi/00660F01/Proc/CPU/cpuEarlyInit.h
@@ -0,0 +1,213 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD CPU Reset API, and related functions and structures.
+ *
+ * Contains code that initialized the CPU after early reset.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: CPU
+ * @e \$Revision: 309090 $ @e \$Date: 2014-12-09 12:28:05 -0600 (Tue, 09 Dec 2014) $
+ *
+ */
+ /*****************************************************************************
+ *
+ * Copyright (c) 2008 - 2015, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ***************************************************************************/
+
+#ifndef _CPU_EARLY_INIT_H_
+#define _CPU_EARLY_INIT_H_
+
+
+/*---------------------------------------------------------------------------------------
+ * M I X E D (Definitions And Macros / Typedefs, Structures, Enums)
+ *---------------------------------------------------------------------------------------
+ */
+AGESA_FORWARD_DECLARATION (CPU_CORE_LEVELING_FAMILY_SERVICES);
+
+/*---------------------------------------------------------------------------------------
+ * D E F I N I T I O N S A N D M A C R O S
+ *---------------------------------------------------------------------------------------
+ */
+//----------------------------------------------------------------------------
+// CPU BRAND ID TYPEDEFS, STRUCTURES, ENUMS
+//
+//----------------------------------------------------------------------------
+#define CPU_BRAND_ID_LENGTH 48 // Total number of characters supported
+#define LOW_NODE_DEVICEID 24
+#define NB_CAPABILITIES 0xE8 //Function 3 Registers
+//----------------------------------------------------------------------------
+// CPU MICROCODE PATCH TYPEDEFS, STRUCTURES, ENUMS
+//
+//----------------------------------------------------------------------------
+/* All lengths are in bytes */
+#define MICROCODE_TRIADE_SIZE 28
+#define MICROCODE_HEADER_LENGTH 64
+
+/**
+ * @page ucodeflag Microcode Patches Signature Guide
+ *
+ * We mark patches in the ROM with a signature so that they can be easily found
+ *
+ * @anchor Microcode Patch Signature
+ * @li @e Microcode Patch Signature @n
+ * Microcode patches are marked by adding a signature before patches in the ROM image to
+ * help identify where they are located.
+ * There're two kind of signatures. One is '$UCODE2K', it indicates there's a following patch with 2K size.
+ * The other is '$UCODE4K', it indicates there's a following patch with 4K size.
+ * If you want to know the patch level / equivalent ID, please consult the BKDG for patch header format.
+ *
+ *
+ */
+/// Microcode patch flag for replacement
+typedef struct {
+ IN UINT8 MicrocodePatchesFlag[8]; ///< a flag followed by microcode
+} MICROCODE_PATCHES_FLAG;
+
+#define UCODE_2K_FLAG(x) STATIC CONST MICROCODE_PATCHES_FLAG ROMDATA UcodeFlag##x = {{'$', 'U', 'C', 'O', 'D', 'E', '2', 'K'}};
+#define UCODE_4K_FLAG(x) STATIC CONST MICROCODE_PATCHES_FLAG ROMDATA UcodeFlag##x = {{'$', 'U', 'C', 'O', 'D', 'E', '4', 'K'}};
+#define UCODE_VS_FLAG(x) STATIC CONST MICROCODE_PATCHES_FLAG ROMDATA UcodeFlag##x = {{'$', 'U', 'C', 'O', 'D', 'E', 'V', 'S'}};
+
+/* Offsets in UCODE PATCH Header */
+/* Note: Header is 64 bytes */
+#define DATE_CODE_OFFSET 0 // 4 bytes
+#define PATCH_ID 4 // 4 bytes
+#define MICROCODE_PATH_DATA_ID 8 // 2 bytes
+#define MICROCODE_PATCH_DATA_LENGTH 10 // 1 byte
+#define MICROCODE_PATCH_DATA_CHECKSUM 12 // 4 bytes
+#define CHIPSET_1_DEVICE_ID 16 // 4 bytes
+#define CHIPSET_2_DEVICE_ID 20 // 4 bytes
+#define PROCESSOR_REV_ID 24 // 2 bytes
+#define CHIPSET_1_REV_ID 26 // 1 byte
+#define CHIPSET_2_REV_ID 27 // 1 byte
+
+/*---------------------------------------------------------------------------------------
+ * T Y P E D E F S, S T R U C T U R E S, E N U M S
+ *---------------------------------------------------------------------------------------
+ */
+//----------------------------------------------------------------------------
+// CPU BRAND ID TYPEDEFS, STRUCTURES, ENUMS
+//
+//----------------------------------------------------------------------------
+/// A structure representing BrandId[15:0] from
+/// CPUID Fn8000_0001_EBX
+typedef struct {
+ UINT8 String1:4; ///< An index to a string value used to create the name string
+ UINT8 String2:4; ///< An index to a string value used to create the name string
+ UINT8 Page:1; ///< An index to the appropriate page for the String1, String2, and Model values
+ UINT8 Model:7; ///< A field used to create the model number in the name string
+ UINT8 Socket:4; ///< Specifies the package type
+ UINT8 Cores:4; ///< Identifies how many physical cores are present
+} AMD_CPU_BRAND_DATA;
+
+/// A structure containing string1 and string2 values
+/// as well as information pertaining to their usage
+typedef struct {
+ IN UINT8 Cores; ///< Appropriate number of physical cores
+ IN UINT8 Page; ///< This string's page number
+ IN UINT8 Index; ///< String index
+ IN UINT8 Socket; ///< Package type information
+ IN CONST CHAR8 *Stringstart; ///< The literal string
+ IN UINT8 Stringlength; ///< Number of characters in the string
+} AMD_CPU_BRAND;
+
+/// An entire CPU brand table.
+typedef struct {
+ UINT8 NumberOfEntries; ///< The number of entries in the table.
+ CONST AMD_CPU_BRAND *Table; ///< The table entries.
+} CPU_BRAND_TABLE;
+
+/**
+ * Set down core register
+ *
+ * @CpuServiceInstances
+ *
+ * @param[in] FamilySpecificServices The current Family Specific Services.
+ * @param[in] Socket Socket ID.
+ * @param[in] Module Module ID in socket.
+ * @param[in] LeveledCores Number of core.
+ * @param[in] CoreLevelMode Core level mode.
+ * @param[in] StdHeader Header for library and services.
+ *
+ * @retval TRUE Down Core register is updated.
+ * @retval FALSE Down Core register is not updated.
+ */
+typedef BOOLEAN (F_CPU_SET_DOWN_CORE_REGISTER) (
+ IN CPU_CORE_LEVELING_FAMILY_SERVICES *FamilySpecificServices,
+ IN UINT32 *Socket,
+ IN UINT32 *Module,
+ IN UINT32 *LeveledCores,
+ IN CORE_LEVELING_TYPE CoreLevelMode,
+ IN AMD_CONFIG_PARAMS *StdHeader
+ );
+
+/// Reference to a method
+typedef F_CPU_SET_DOWN_CORE_REGISTER *PF_CPU_SET_DOWN_CORE_REGISTER;
+
+/**
+ * Provide the interface to the Core Leveling Family Specific Services.
+ *
+ * Use the methods or data in this struct to adapt the feature code to a specific cpu family or model (or stepping!).
+ * Each supported Family must provide an implementation for all methods in this interface, even if the
+ * implementation is a CommonReturn().
+ */
+struct _CPU_CORE_LEVELING_FAMILY_SERVICES { // See Forward Declaration above
+ UINT16 Revision; ///< Interface version
+ // Public Methods.
+ PF_CPU_SET_DOWN_CORE_REGISTER SetDownCoreRegister; ///< Method: Set down core register.
+};
+
+/*---------------------------------------------------------------------------------------
+ * F U N C T I O N P R O T O T Y P E
+ *---------------------------------------------------------------------------------------
+ */
+
+// These are P U B L I C functions, used by IBVs
+AGESA_STATUS
+AmdCpuEarly (
+ IN AMD_CONFIG_PARAMS *StdHeader,
+ IN PLATFORM_CONFIGURATION *PlatformConfig
+ );
+
+// These are P U B L I C functions, used by AGESA
+AGESA_STATUS
+PmInitializationAtEarly (
+ IN AMD_CPU_EARLY_PARAMS *CpuEarlyParams,
+ IN AMD_CONFIG_PARAMS *StdHeader
+ );
+
+VOID
+AmdCpuEarlyInitializer (
+ IN AMD_CONFIG_PARAMS *StdHeader,
+ IN PLATFORM_CONFIGURATION *PlatformConfig,
+ IN OUT AMD_CPU_EARLY_PARAMS *CpuEarlyParamsPtr
+ );
+
+#endif // _CPU_EARLY_INIT_H_
+
diff --git a/src/vendorcode/amd/pi/00660F01/Proc/CPU/cpuLateInit.h b/src/vendorcode/amd/pi/00660F01/Proc/CPU/cpuLateInit.h
new file mode 100644
index 0000000..7cef71d
--- /dev/null
+++ b/src/vendorcode/amd/pi/00660F01/Proc/CPU/cpuLateInit.h
@@ -0,0 +1,1045 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD CPU Late Init API functions Prototypes.
+ *
+ * Contains code for doing any late CPU initialization
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: CPU
+ * @e \$Revision: 309090 $ @e \$Date: 2014-12-09 12:28:05 -0600 (Tue, 09 Dec 2014) $
+ *
+ */
+ /*****************************************************************************
+ *
+ * Copyright (c) 2008 - 2015, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ***************************************************************************/
+
+#ifndef _CPU_LATE_INIT_H_
+#define _CPU_LATE_INIT_H_
+
+#include "Filecode.h"
+
+// Forward declaration needed for multi-structure mutual references.
+AGESA_FORWARD_DECLARATION (PROC_FAMILY_TABLE);
+/*----------------------------------------------------------------------------------------
+ * M I X E D (Definitions And Macros / Typedefs, Structures, Enums)
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ * D E F I N I T I O N S A N D M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+//----------------------------------------------------------------------------
+// DMI DEFINITIONS AND MACROS
+//
+//----------------------------------------------------------------------------
+#define AP_LATE_TASK_GET_TYPE4_TYPE7 (PROC_CPU_FEATURE_CPUDMI_FILECODE)
+// SMBIOS constant definition
+#define CENTRAL_PROCESSOR 0x03
+#define EXTERNAL_CLOCK_DFLT 200
+#define EXTERNAL_CLOCK_100MHZ 100
+#define P_FAMILY_UNKNOWN 0x02
+#define P_ENGINEERING_SAMPLE 0x00
+#define P_CHARACTERISTICS 0x4
+#define CACHE_CFG_L1 0x180
+#define CACHE_CFG_L2 0x181
+#define CACHE_CFG_L3 0x182
+#define SRAM_TYPE 0x10
+#define ERR_CORRECT_TYPE 0x06
+#define CACHE_TYPE 0x05
+#define DMI_ASSOCIATIVE_OTHER 0x01
+#define DMI_ASSOCIATIVE_UNKNOWN 0x02
+#define DMI_ASSOCIATIVE_DIRECT_MAPPED 0x03
+#define DMI_ASSOCIATIVE_2_WAY 0x04
+#define DMI_ASSOCIATIVE_4_WAY 0x05
+#define DMI_ASSOCIATIVE_FULLY 0x06
+#define DMI_ASSOCIATIVE_8_WAY 0x07
+#define DMI_ASSOCIATIVE_16_WAY 0x08
+#define DMI_ASSOCIATIVE_12_WAY 0x09
+#define DMI_ASSOCIATIVE_24_WAY 0x0A
+#define DMI_ASSOCIATIVE_32_WAY 0x0B
+#define DMI_ASSOCIATIVE_48_WAY 0x0C
+#define DMI_ASSOCIATIVE_64_WAY 0x0D
+#define DMI_ASSOCIATIVE_20_WAY 0x0E
+#define SOCKET_POPULATED 0x40
+#define CPU_STATUS_UNKNOWN 0x00
+#define CPU_STATUS_ENABLED 0x01
+
+// Processor Upgrade Definition
+#define P_UPGRADE_UNKNOWN 0x02
+#define P_UPGRADE_NONE 0x06
+
+//----------------------------------------------------------------------------
+// CDIT DEFINITIONS AND MACROS
+//
+//----------------------------------------------------------------------------
+#define AMD_ACPI_CDIT_NUM_DOMAINS_LENGTH 4 // Num domains is a 4-bytes unsigned integer
+
+
+//----------------------------------------------------------------------------
+// P-STATE DEFINITIONS AND MACROS
+//
+//----------------------------------------------------------------------------
+//-------------------------------------
+// ERROR Codes
+//-------------------------------------
+#define NO_ERROR 0x0
+#define USER_DISABLE_ERROR 0x01 // User disabled SSDT generation
+#define CORES_MISSMATCH_PSS_ERROR 0x02 // No PSS match
+#define PNOW_SUPPORT_ERROR 0x04 // One of the Cores do not support PNOW!
+#define PWR_FREQ_MATCH_ERROR 0x08 // FREQ and PWR mismatch
+#define NO_PSS_SIZE_ERROR 0x10 // Error in PSS Size
+#define INVALID_PSTATE_ERROR 0x20 // Invalid Max or only 1 P-State available
+#define NO_PSS_ENTRY 0x0FFFFul
+#define INVALID_FREQ 0x0FFFFFFFFul
+
+//-------------------------
+// Default definitions
+// AMD BKDG default values
+//-------------------------
+#define DEFAULT_ISOCH_RELIEF_TIME IRT_80uS
+#define DEFAULT_RAMP_VOLTAGE_OFFSET RVO_50mV
+#define DEFAULT_MAX_VOLTAGE_STEP MVS_25mV
+#define DEFAULT_PERF_PRESENT_CAP 0 // default for Desktop
+#define DEFAULT_VOLTAGE_STABLE_TIME (100 / 20) // 100uS
+#define DEFAULT_PLL_LOCK_TIME 2 // 2uS
+#define DEFAULT_TRANSITION_LATENCY 100 // 100uS
+#define DEFAULT_BUS_MASTER_LATENCY 9 // 9uS
+#define DEFAULT_CPU_SCOPE_NUMBER "0UPC"
+
+// Defines for Common ACPI
+// -----------------------------
+#define SCOPE_OPCODE 0x10
+#define NAME_OPCODE 0x08
+#define METHOD_OPCODE 0x14
+#define PACKAGE_OPCODE 0x12
+#define BUFFER_OPCODE 0x11
+#define BYTE_PREFIX_OPCODE 0x0A
+#define WORD_PREFIX_OPCODE 0x0B
+#define DWORD_PREFIX_OPCODE 0x0C
+#define RETURN_OPCODE 0xA4
+#define ACPI_BUFFER 0x080A0B11ul
+
+// Generic Register Descriptor (GDR) Fields
+#define GDR_ASI_SYSTEM_IO 0x01 // Address Space ID
+#define GDR_ASZ_BYTE_ACCESS 0x01 // Address Size
+
+// Defines for ACPI Scope Table
+// ----------------------------
+#define SCOPE_LENGTH (SCOPE_STRUCT_SIZE + \
+ PCT_STRUCT_SIZE + \
+ PSS_HEADER_STRUCT_SIZE + \
+ PSS_BODY_STRUCT_SIZE + \
+ PPC_HEADER_BODY_STRUCT_SIZE)
+#define SCOPE_VALUE1 0x5C
+#define SCOPE_VALUE2 0x2E
+#define SCOPE_NAME__ '_'
+#define SCOPE_NAME_P 'P'
+#define SCOPE_NAME_R 'R'
+#define SCOPE_NAME_S 'S'
+#define SCOPE_NAME_B 'B'
+#define SCOPE_NAME_C 'C'
+#define SCOPE_NAME_U 'U'
+#define SCOPE_NAME_0 '0'
+#define SCOPE_NAME_1 '1'
+#define SCOPE_NAME_2 '2'
+#define SCOPE_NAME_3 '3'
+#define SCOPE_NAME_A 'A'
+
+#ifdef OEM_SCOPE_NAME
+ #if (OEM_SCOPE_NAME > 'Z') || (OEM_SCOPE_NAME < 'A')
+ #error "OEM_SCOPE_NAME: it should be only one char long AND a valid letter (A~Z)"
+ #endif
+ #define SCOPE_NAME_VALUE OEM_SCOPE_NAME
+#else
+ #define SCOPE_NAME_VALUE SCOPE_NAME_C
+#endif // OEM_SCOPE_NAME
+
+#ifdef OEM_SCOPE_NAME1
+ #if (!(((OEM_SCOPE_NAME1 >= 'A') && (OEM_SCOPE_NAME1 <= 'Z')) || \
+ ((OEM_SCOPE_NAME1 >= '0') && (OEM_SCOPE_NAME1 <= '9')) || \
+ (OEM_SCOPE_NAME1 == '_')))
+ #error "OEM_SCOPE_NAME1: it should be only one char long AND a valid letter (0~9, A~F)"
+ #endif
+ #define SCOPE_NAME_VALUE1 OEM_SCOPE_NAME1
+#else
+ #define SCOPE_NAME_VALUE1 SCOPE_NAME_0
+#endif // OEM_SCOPE_NAME
+
+// Defines for PCT Control and Status Table
+// ----------------------------------------
+#define PCT_NAME__ '_'
+#define PCT_NAME_P 'P'
+#define PCT_NAME_C 'C'
+#define PCT_NAME_T 'T'
+#define PCT_VALUE1 0x11022C12ul
+#define PCT_VALUE2 0x0A14
+#define PCT_VALUE3 0x11
+#define GENERIC_REG_DESCRIPTION 0x82
+#define PCT_LENGTH 0x0C
+#define PCT_ADDRESS_SPACE_ID 0x7F
+#define PCT_REGISTER_BIT_WIDTH 0x40
+#define PCT_REGISTER_BIT_OFFSET 0x00
+#define PCT_RESERVED 0x00
+#define PCT_CONTROL_REG_LO 0xC0010062ul
+#define PCT_CONTROL_REG_HI 0x00
+#define PCT_VALUE4 0x14110079ul
+#define PCT_VALUE5 0x110A
+#define PCT_STATUS_REG_LO 0x00
+#define PCT_STATUS_REG_HI 0x00
+#define PCT_VALUE6 0x0079
+
+
+// Defines for PSS Header Table
+// ----------------------------
+#define PSS_NAME__ '_'
+#define PSS_NAME_X 'X'
+#define PSS_NAME_P 'P'
+#define PSS_NAME_S 'S'
+#define PSS_LENGTH (sizeof pssBodyStruct + 3)
+#define NUM_OF_ITEMS_IN_PSS 0x00
+
+
+// Defines for PSS Header Table
+// ----------------------------
+#define PSS_PKG_LENGTH 0x20 // PSS_BODY_STRUCT_SIZE - 1
+#define PSS_NUM_OF_ELEMENTS 0x06
+#define PSS_FREQUENCY 0x00
+#define PSS_POWER 0x00
+#define PSS_TRANSITION_LATENCY DEFAULT_TRANSITION_LATENCY
+#define PSS_BUS_MASTER_LATENCY DEFAULT_BUS_MASTER_LATENCY
+#define PSS_CONTROL ((DEFAULT_ISOCH_RELIEF_TIME << 30) + \
+ (DEFAULT_RAMP_VOLTAGE_OFFSET << 28) + \
+ (DEFAULT_EXT_TYPE << 27) + \
+ (DEFAULT_PLL_LOCK_TIME << 20) + \
+ (DEFAULT_MAX_VOLTAGE_STEP << 18) + \
+ (DEFAULT_VOLTAGE_STABLE_TIME << 11) + \
+ (PSS_VID << 6) + PSS_FID)
+#define PSS_STATUS (DEFAULT_EXTENDED_TYPE << 11) + (PSS_VID << 6) + (PSS_FID)
+
+// Defines for XPSS Header Table
+// ----------------------------
+#define XPSS_PKG_LENGTH 0x47 // XPSS_BODY_STRUCT_SIZE - 1
+#define XPSS_NUM_OF_ELEMENTS 0x08
+#define XPSS_ACPI_BUFFER 0x080A0B11ul
+
+
+// Defines for PPC Header Table
+// ----------------------------
+#define PPC_NAME__ '_'
+#define PPC_NAME_P 'P'
+#define PPC_NAME_C 'C'
+#define PPC_NAME_V 'V'
+#define PPC_METHOD_FLAGS 0x00;
+#define PPC_VALUE1 0x0A;
+
+// Defines for PSD Header Table
+// ----------------------------
+#define PSD_NAME__ '_'
+#define PSD_NAME_P 'P'
+#define PSD_NAME_S 'S'
+#define PSD_NAME_D 'D'
+#define PSD_HEADER_LENGTH (PSD_BODY_STRUCT_SIZE + 2)
+#define PSD_VALUE1 0x01
+
+
+// Defines for PSD Header Table
+// ----------------------------
+#define PSD_PKG_LENGTH (PSD_BODY_STRUCT_SIZE - 1)
+#define NUM_OF_ENTRIES 0x05
+#define PSD_NUM_OF_ENTRIES 0x05
+#define PSD_REVISION 0x00
+#define PSD_DEPENDENCY_DOMAIN 0x00
+#define PSD_COORDINATION_TYPE_HW_ALL 0xFE
+#define PSD_COORDINATION_TYPE_SW_ANY 0xFD
+#define PSD_COORDINATION_TYPE_SW_ALL 0xFC
+#define PSD_NUM_OF_PROCESSORS 0x01
+#define PSD_TWO_CORES_PER_COMPUTE_UNIT 0x02
+#define PSD_THREE_CORES_PER_COMPUTE_UNIT 0x03
+#define PSD_FOUR_CORES_PER_COMPUTE_UNIT 0x04
+
+
+#define CUSTOM_PSTATE_FLAG 0x55
+#define PSTATE_FLAG_1 0x55
+#define TARGET_PSTATE_FLAG 0xAA
+#define PSTATE_FLAG_2 0xAA
+
+/*----------------------------------------------------------------------------------------
+ * T Y P E D E F S, S T R U C T U R E S, E N U M S
+ *----------------------------------------------------------------------------------------
+ */
+//----------------------------------------------------------------------------
+// ACPI P-States AML TYPEDEFS, STRUCTURES, ENUMS
+//
+//----------------------------------------------------------------------------
+
+//--------------------------------------------
+// AML code definition
+// (Scope)
+//---------------------------------------------
+/// SCOPE
+typedef struct _SCOPE {
+ UINT8 ScopeOpcode; ///< Opcode
+ UINT16 ScopeLength; ///< Scope Length
+ UINT8 ScopeValue1; ///< Value1
+ UINT8 ScopeValue2; ///< Value2
+ UINT8 ScopeNamePt1a__; ///< Name Pointer
+ UINT8 ScopeNamePt1a_P; ///< Name Pointer
+ UINT8 ScopeNamePt1a_R; ///< Name Pointer
+ UINT8 ScopeNamePt1b__; ///< Name Pointer
+ UINT8 ScopeNamePt2a_C; ///< Name Pointer
+ UINT8 ScopeNamePt2a_P; ///< Name Pointer
+ UINT8 ScopeNamePt2a_U; ///< Name Pointer
+ UINT8 ScopeNamePt2a_0; ///< Name Pointer
+} SCOPE;
+#define SCOPE_STRUCT_SIZE 13 // 13 Bytes
+
+//--------------------------------------------
+// AML code definition
+// (PCT Header and Body)
+//---------------------------------------------
+
+///Performance Control Header
+typedef struct _PCT_HEADER_BODY {
+ UINT8 NameOpcode; ///< Opcode
+ UINT8 PctName_a__; ///< String "_"
+ UINT8 PctName_a_P; ///< String "P"
+ UINT8 PctName_a_C; ///< String "C"
+ UINT8 PctName_a_T; ///< String "T"
+ UINT32 Value1; ///< Value1
+ UINT16 Value2; ///< Value2
+ UINT8 Value3; ///< Value3
+ UINT8 GenericRegDescription1; ///< Generic Reg Description
+ UINT16 Length1; ///< Length1
+ UINT8 AddressSpaceId1; ///< PCT Address Space ID
+ UINT8 RegisterBitWidth1; ///< PCT Register Bit Width
+ UINT8 RegisterBitOffset1; ///< PCT Register Bit Offset
+ UINT8 Reserved1; ///< Reserved
+ UINT32 ControlRegAddressLo; ///< Control Register Address Low
+ UINT32 ControlRegAddressHi; ///< Control Register Address High
+ UINT32 Value4; ///< Value4
+ UINT16 Value5; ///< Value 5
+ UINT8 GenericRegDescription2; ///< Generic Reg Description
+ UINT16 Length2; ///< Length2
+ UINT8 AddressSpaceId2; ///< PCT Address Space ID
+ UINT8 RegisterBitWidth2; ///< PCT Register Bit Width
+ UINT8 RegisterBitOffset2; ///< PCT Register Bit Offset
+ UINT8 Reserved2; ///< Reserved
+ UINT32 StatusRegAddressLo; ///< Control Register Address Low
+ UINT32 StatusRegAddressHi; ///< Control Register Address High
+ UINT16 Value6; ///< Values
+} PCT_HEADER_BODY;
+#define PCT_STRUCT_SIZE 50 // 50 Bytes
+
+
+//--------------------------------------------
+// AML code definition
+// (PSS Header)
+//--------------------------------------------
+///Performance Supported States Header
+typedef struct _PSS_HEADER {
+ UINT8 NameOpcode; ///< Opcode
+ UINT8 PssName_a__; ///< String "_"
+ UINT8 PssName_a_P; ///< String "P"
+ UINT8 PssName_a_S; ///< String "S"
+ UINT8 PssName_b_S; ///< String "S"
+ UINT8 PkgOpcode; ///< Package Opcode
+ UINT16 PssLength; ///< PSS Length
+ UINT8 NumOfItemsInPss; ///< Number of Items in PSS
+} PSS_HEADER;
+#define PSS_HEADER_STRUCT_SIZE 9 // 9 Bytes
+
+
+//--------------------------------------------
+// AML code definition
+// (PSS Body)
+//--------------------------------------------
+///Performance Supported States Body
+typedef struct _PSS_BODY {
+ UINT8 PkgOpcode; ///< Package Opcode
+ UINT8 PkgLength; ///< Package Length
+ UINT8 NumOfElements; ///< Number of Elements
+ UINT8 DwordPrefixOpcode1; ///< Prefix Opcode1
+ UINT32 Frequency; ///< Frequency
+ UINT8 DwordPrefixOpcode2; ///< Prefix Opcode2
+ UINT32 Power; ///< Power
+ UINT8 DwordPrefixOpcode3; ///< Prefix Opcode3
+ UINT32 TransitionLatency; ///< Transition Latency
+ UINT8 DwordPrefixOpcode4; ///< Prefix Opcode4
+ UINT32 BusMasterLatency; ///< Bus Master Latency
+ UINT8 DwordPrefixOpcode5; ///< Prefix Opcode5
+ UINT32 Control; ///< Control
+ UINT8 DwordPrefixOpcode6; ///< Prefix Opcode6
+ UINT32 Status; ///< Status
+} PSS_BODY;
+#define PSS_BODY_STRUCT_SIZE 33 // 33 Bytes
+
+
+/*--------------------------------------------
+ * AML code definition
+ * (XPSS Header)
+ *--------------------------------------------
+ */
+/// Extended PSS Header
+typedef struct _XPSS_HEADER {
+ UINT8 NameOpcode; ///< 08h
+ UINT8 XpssName_a_X; ///< String "X"
+ UINT8 XpssName_a_P; ///< String "P"
+ UINT8 XpssName_a_S; ///< String "S"
+ UINT8 XpssName_b_S; ///< String "S"
+ UINT8 PkgOpcode; ///< 12h
+ UINT16 XpssLength; ///< XPSS Length
+ UINT8 NumOfItemsInXpss; ///< Number of Items in XPSS
+} XPSS_HEADER;
+#define XPSS_HEADER_STRUCT_SIZE 9 // 9 Bytes
+
+/*--------------------------------------------
+ * AML code definition
+ * (XPSS Body)
+ *--------------------------------------------
+ */
+/// Extended PSS Body
+typedef struct _XPSS_BODY {
+ UINT8 PkgOpcode; ///< 12h
+ UINT8 PkgLength; ///< Package Length
+ UINT8 XpssValueTbd; ///< XPSS Value
+ UINT8 NumOfElements; ///< Number of Elements
+ UINT8 DwordPrefixOpcode1; ///< Prefix Opcode1
+ UINT32 Frequency; ///< Frequency
+ UINT8 DwordPrefixOpcode2; ///< Prefix Opcode2
+ UINT32 Power; ///< Power
+ UINT8 DwordPrefixOpcode3; ///< Prefix Opcode3
+ UINT32 TransitionLatency; ///< Transition Latency
+ UINT8 DwordPrefixOpcode4; ///< Prefix Opcode4
+ UINT32 BusMasterLatency; ///< Bus Master Latency
+ UINT32 ControlBuffer; ///< Control Buffer
+ UINT32 ControlLo; ///< Control Low
+ UINT32 ControlHi; ///< Control High
+ UINT32 StatusBuffer; ///< Status Buffer
+ UINT32 StatusLo; ///< Status Low
+ UINT32 StatusHi; ///< Status High
+ UINT32 ControlMaskBuffer; ///< Control Mask Buffer
+ UINT32 ControlMaskLo; ///< Control Mask Low
+ UINT32 ControlMaskHi; ///< Control Mask High
+ UINT32 StatusMaskBuffer; ///< Status Mask Buffer
+ UINT32 StatusMaskLo; ///< Status Mask Low
+ UINT32 StatusMaskHi; ///< Status Mask High
+} XPSS_BODY;
+#define XPSS_BODY_STRUCT_SIZE 72 // 72 Bytes
+
+/*--------------------------------------------
+ * AML code definition
+ * (PPC Header and Body)
+ *--------------------------------------------
+ */
+/// Performance Present Capabilities Header
+typedef struct _PPC_HEADER_BODY {
+ UINT8 NameOpcode; ///< Name Opcode
+ UINT8 PpcName_a_P; ///< String "P"
+ UINT8 PpcName_b_P; ///< String "P"
+ UINT8 PpcName_a_C; ///< String "C"
+ UINT8 PpcName_a_V; ///< String "V"
+ UINT8 Value1; ///< Value
+ UINT8 DefaultPerfPresentCap; ///< Default Perf Present Cap
+ UINT8 MethodOpcode; ///< Method Opcode
+ UINT8 PpcLength; ///< Method Length
+ UINT8 PpcName_a__; ///< String "_"
+ UINT8 PpcName_c_P; ///< String "P"
+ UINT8 PpcName_d_P; ///< String "P"
+ UINT8 PpcName_b_C; ///< String "C"
+ UINT8 MethodFlags; ///< Method Flags
+ UINT8 ReturnOpcode; ///< Return Opcoce
+ UINT8 PpcName_e_P; ///< String "P"
+ UINT8 PpcName_f_P; ///< String "P"
+ UINT8 PpcName_c_C; ///< String "C"
+ UINT8 PpcName_b_V; ///< String "V"
+
+} PPC_HEADER_BODY;
+#define PPC_HEADER_BODY_STRUCT_SIZE 19 // 19 Bytes
+#define PPC_METHOD_LENGTH 11 // 11 Bytes
+
+
+/*--------------------------------------------
+ * AML code definition
+ * (PSD Header)
+ *--------------------------------------------
+ */
+/// P-State Dependency Header
+typedef struct _PSD_HEADER {
+ UINT8 NameOpcode; ///< Name Opcode
+ UINT8 PsdName_a__; ///< String "_"
+ UINT8 PsdName_a_P; ///< String "P"
+ UINT8 PsdName_a_S; ///< String "S"
+ UINT8 PsdName_a_D; ///< String "D"
+ UINT8 PkgOpcode; ///< Package Opcode
+ UINT8 PsdLength; ///< PSD Length
+ UINT8 Value1; ///< Value
+} PSD_HEADER;
+#define PSD_HEADER_STRUCT_SIZE 8 // 8 Bytes
+
+/*--------------------------------------------
+ * AML code definition
+ * (PSD Body)
+ *--------------------------------------------
+ */
+/// P-State Dependency Body
+typedef struct _PSD_BODY {
+ UINT8 PkgOpcode; ///< Package Opcode
+ UINT8 PkgLength; ///< Package Length
+ UINT8 NumOfEntries; ///< Number of Entries
+ UINT8 BytePrefixOpcode1; ///< Prefix Opcode1 in Byte
+ UINT8 PsdNumOfEntries; ///< PSD Number of Entries
+ UINT8 BytePrefixOpcode2; ///< Prefix Opcode2 in Byte
+ UINT8 PsdRevision; ///< PSD Revision
+ UINT8 DwordPrefixOpcode1; ///< Prefix Opcode1 in DWord
+ UINT32 DependencyDomain; ///< Dependency Domain
+ UINT8 DwordPrefixOpcode2; ///< Prefix Opcode2 in DWord
+ UINT32 CoordinationType; ///< (0xFC = SW_ALL, 0xFD = SW_ANY, 0xFE = HW_ALL)
+ UINT8 DwordPrefixOpcode3; ///< Prefix Opcode3 in DWord
+ UINT32 NumOfProcessors; ///< Number of Processors
+} PSD_BODY;
+#define PSD_BODY_STRUCT_SIZE 22 // 22 Bytes
+
+//----------------------------------------------------------------------------
+// WHEA TYPEDEFS, STRUCTURES, ENUMS
+//
+//----------------------------------------------------------------------------
+
+/// HEST MCE TABLE
+typedef struct _AMD_HEST_MCE_TABLE {
+ UINT16 TblLength; ///< Length, in bytes, of entire AMD_HEST_MCE structure.
+ UINT32 GlobCapInitDataLSD; ///< Holds the value that the OS will program into
+ UINT32 GlobCapInitDataMSD; ///< the machine check global capability register(MCG_CAP).
+ UINT32 GlobCtrlInitDataLSD; ///< Holds the value that the OS will program into
+ UINT32 GlobCtrlInitDataMSD; ///< the machine check global control register(MCG_CTL).
+ UINT8 NumHWBanks; ///< The number of hardware error reporting banks.
+ UINT8 Rsvd[7]; ///< reserve 7 bytes as spec's required
+} AMD_HEST_MCE_TABLE;
+
+/// HEST CMC TABLE
+typedef struct _AMD_HEST_CMC_TABLE {
+ UINT16 TblLength; ///< Length, in bytes, of entire AMD_HEST_CMC structure.
+ UINT8 NumHWBanks; ///< The number of hardware error reporting banks.
+ UINT8 Rsvd[3]; ///< reserve 3 bytes as spec's required
+} AMD_HEST_CMC_TABLE;
+
+/// HEST BANK
+typedef struct _AMD_HEST_BANK {
+ UINT8 BankNum; ///< Zero-based index identifies the machine check error bank.
+ UINT8 ClrStatusOnInit; ///< Indicates if the status information in this machine check bank
+ ///< is to be cleared during system initialization.
+ UINT8 StatusDataFormat; ///< Indicates the format of the data in the status register
+ UINT8 ConfWriteEn; ///< This field indicates whether configuration parameters may be
+ ///< modified by the OS. If the bit for the associated parameter is
+ ///< set, the parameter is writable by the OS.
+ UINT32 CtrlRegMSRAddr; ///< Address of the hardware bank's control MSR. Ignored if zero.
+
+ UINT32 CtrlInitDataLSD; ///< This is the value the OS will program into the machine check
+ UINT32 CtrlInitDataMSD; ///< bank's control register
+ UINT32 StatRegMSRAddr; ///< Address of the hardware bank's MCi_STAT MSR. Ignored if zero.
+ UINT32 AddrRegMSRAddr; ///< Address of the hardware bank's MCi_ADDR MSR. Ignored if zero.
+ UINT32 MiscRegMSRAddr; ///< Address of the hardware bank's MCi_MISC MSR. Ignored if zero.
+} AMD_HEST_BANK;
+
+/// Initial data of AMD_HEST_BANK
+typedef struct _AMD_HEST_BANK_INIT_DATA {
+ UINT32 CtrlInitDataLSD; ///< Initial data of CtrlInitDataLSD
+ UINT32 CtrlInitDataMSD; ///< Initial data of CtrlInitDataMSD
+ UINT32 CtrlRegMSRAddr; ///< Initial data of CtrlRegMSRAddr
+ UINT32 StatRegMSRAddr; ///< Initial data of StatRegMSRAddr
+ UINT32 AddrRegMSRAddr; ///< Initial data of AddrRegMSRAddr
+ UINT32 MiscRegMSRAddr; ///< Initial data of MiscRegMSRAddr
+} AMD_HEST_BANK_INIT_DATA;
+
+/// MSR179 Global Machine Check Capabilities data struct
+typedef struct _MSR_MCG_CAP_STRUCT {
+ UINT64 Count:8; ///< Indicates the number of
+ ///< error-reporting banks visible to each core
+ UINT64 McgCtlP:1; ///< 1=The machine check control registers
+ UINT64 Rsvd:55; ///< reserved
+} MSR_MCG_CAP_STRUCT;
+
+/// Initial data of WHEA
+typedef struct _AMD_WHEA_INIT_DATA {
+ UINT32 GlobCapInitDataLSD; ///< Holds the value that the OS will program into the machine
+ UINT32 GlobCapInitDataMSD; ///< Check global capability register
+ UINT32 GlobCtrlInitDataLSD; ///< Holds the value that the OS will grogram into the machine
+ UINT32 GlobCtrlInitDataMSD; ///< Check global control register
+ UINT8 ClrStatusOnInit; ///< Indicates if the status information in this machine check
+ ///< bank is to be cleared during system initialization
+ UINT8 StatusDataFormat; ///< Indicates the format of the data in the status register
+ UINT8 ConfWriteEn; ///< This field indicates whether configuration parameters may be
+ ///< modified by the OS. If the bit for the associated parameter is
+ ///< set, the parameter is writable by the OS.
+ UINT8 HestBankNum; ///< Number of HEST Bank
+ AMD_HEST_BANK_INIT_DATA *HestBankInitData; ///< Pointer to Initial data of HEST Bank
+} AMD_WHEA_INIT_DATA;
+
+//----------------------------------------------------------------------------
+// DMI TYPEDEFS, STRUCTURES, ENUMS
+//
+//----------------------------------------------------------------------------
+/// DMI brand information
+typedef struct {
+ UINT16 String1:4; ///< String1
+ UINT16 String2:4; ///< String2
+ UINT16 Model:7; ///< Model
+ UINT16 Pg:1; ///< Page
+} BRAND_ID;
+
+/// DMI cache information
+typedef struct {
+ UINT32 L1CacheSize; ///< L1 cache size
+ UINT8 L1CacheAssoc; ///< L1 cache associativity
+ UINT32 L2CacheSize; ///< L2 cache size
+ UINT8 L2CacheAssoc; ///< L2 cache associativity
+ UINT32 L3CacheSize; ///< L3 cache size
+ UINT8 L3CacheAssoc; ///< L3 cache associativity
+} CPU_CACHE_INFO;
+
+/// DMI processor information
+typedef struct {
+ UINT8 ExtendedFamily; ///< Extended Family
+ UINT8 ExtendedModel; ///< Extended Model
+ UINT8 BaseFamily; ///< Base Family
+ UINT8 BaseModel; ///< Base Model
+ UINT8 Stepping; ///< Stepping
+ UINT8 PackageType; ///< PackageType
+ BRAND_ID BrandId; ///< BrandId which contains information about String1, String2, Model and Page
+ UINT8 TotalCoreNumber; ///< Number of total cores
+ UINT8 EnabledCoreNumber; ///< Number of enabled cores
+ UINT8 ProcUpgrade; ///< ProcUpdrade
+ CPU_CACHE_INFO CacheInfo; ///< CPU cache info
+} CPU_TYPE_INFO;
+
+/// A structure containing processor name string and
+/// the value that should be provide to DMI type 4 processor family
+typedef struct {
+ IN CONST CHAR8 *Stringstart; ///< The literal string
+ IN UINT8 T4ProcFamilySetting; ///< The value set to DMI type 4 processor family
+} CPU_T4_PROC_FAMILY;
+
+/// DMI ECC information
+typedef struct {
+ BOOLEAN EccCapable; ///< ECC Capable
+} CPU_GET_MEM_INFO;
+
+/* Transfer vectors for DMI family specific routines */
+typedef VOID OPTION_DMI_GET_CPU_INFO (
+ IN OUT CPU_TYPE_INFO *CpuInfoPtr,
+ IN AMD_CONFIG_PARAMS *StdHeader
+ );
+
+typedef VOID OPTION_DMI_GET_PROC_FAMILY (
+ IN OUT UINT8 *T4ProcFamily,
+ IN PROC_FAMILY_TABLE *CpuDmiProcFamilyTable,
+ IN CPU_TYPE_INFO *CpuInfo,
+ IN AMD_CONFIG_PARAMS *StdHeader
+ );
+
+typedef UINT8 OPTION_DMI_GET_VOLTAGE (
+ IN AMD_CONFIG_PARAMS *StdHeader
+ );
+
+typedef UINT16 OPTION_DMI_GET_MAX_SPEED (
+ IN AMD_CONFIG_PARAMS *StdHeader
+ );
+
+typedef UINT16 OPTION_DMI_GET_EXT_CLOCK (
+ IN AMD_CONFIG_PARAMS *StdHeader
+ );
+
+typedef VOID OPTION_DMI_GET_MEM_INFO (
+ IN OUT CPU_GET_MEM_INFO *CpuGetMemInfoPtr,
+ IN AMD_CONFIG_PARAMS *StdHeader
+ );
+
+/// Brand table entry format
+typedef struct {
+ UINT8 PackageType; ///< Package type
+ UINT8 PgOfBrandId; ///< Page
+ UINT8 NumberOfCores; ///< Number of cores
+ UINT8 String1ofBrandId; ///< String1
+ UINT8 ValueSetToDmiTable; ///< The value which will should be set to DMI table
+} DMI_BRAND_ENTRY;
+
+/// Family specific data table structure
+struct _PROC_FAMILY_TABLE {
+ UINT64 ProcessorFamily; ///< processor
+ OPTION_DMI_GET_CPU_INFO *DmiGetCpuInfo; ///< transfer vectors
+ OPTION_DMI_GET_PROC_FAMILY *DmiGetT4ProcFamily; ///< Get DMI type 4 processor family information
+ OPTION_DMI_GET_VOLTAGE *DmiGetVoltage; ///< vector for reading voltage
+ OPTION_DMI_GET_MAX_SPEED *DmiGetMaxSpeed; ///< vector for reading speed
+ OPTION_DMI_GET_EXT_CLOCK *DmiGetExtClock; ///< vector for reading external clock speed
+ OPTION_DMI_GET_MEM_INFO *DmiGetMemInfo; ///< Get memory information
+ UINT8 LenBrandList; ///< size of brand table
+ CONST DMI_BRAND_ENTRY *DmiBrandList; ///< translate brand info to DMI identifier
+};
+
+//----------------------------------------------------------------------------
+// TYPEDEFS, STRUCTURES, ENUMS
+//
+//----------------------------------------------------------------------------
+/// Format for Header
+typedef struct {
+ UINT8 Sign[4]; ///< Signature
+ UINT32 TableLength; ///< Table Length
+ UINT8 Revision; ///< Revision
+ UINT8 Checksum; ///< Checksum
+ UINT8 OemId[6]; ///< OEM ID
+ UINT8 OemTableId[8]; ///< OEM Tabled ID
+ UINT32 OemRev; ///< OEM Revision
+ UINT8 CreatorId[4]; ///< Creator ID
+ UINT32 CreatorRev; ///< Creator Revision
+} ACPI_TABLE_HEADER;
+
+//----------------------------------------------------------------------------
+// CRAT TYPEDEFS, STRUCTURES, ENUMS
+// Component Resource Affinity Table
+//----------------------------------------------------------------------------
+/// Format for CRAT Header
+typedef struct {
+ UINT8 Sign[4]; ///< CRAT, Signature for the Component Resource Affinity Table.
+ UINT32 Length; ///< Length, in bytes, of the entire CRAT
+ UINT8 Revision; ///< 0
+ UINT8 Checksum; ///< Entire table must sum to zero.
+ UINT8 OemId[6]; ///< OEM ID
+ UINT8 OemTableId[8]; ///< OEM Tabled ID
+ UINT32 OemRev; ///< OEM Revision
+ UINT8 CreatorId[4]; ///< Creator ID
+ UINT32 CreatorRev; ///< Creator Revision
+ UINT32 TotalEntries; ///< total number[n] of entries in the CRAT
+ UINT16 NumDomains; ///< Number of HSA proximity domains
+ UINT8 Reserved[6]; ///< Reserved
+} CRAT_HEADER;
+
+/// Flags field of the CRAT HSA Processing Unit Affinity Structure
+typedef struct {
+ UINT32 Enabled:1; ///< Enabled
+ UINT32 HotPluggable:1; ///< Hot Pluggable
+ UINT32 CpuPresent:1; ///< Cpu Present
+ UINT32 GpuPresent:1; ///< Gpu Present
+ UINT32 IommuPresent:1; ///< IOMMU Present
+ UINT32 :27; ///< Reserved
+} CRAT_HSA_PROCESSING_UNIT_FLAG;
+
+/// CRAT HSA Processing Unit Affinity Structure
+typedef struct {
+ UINT8 Type; ///< 0 - CRAT HSA Processing Unit Structure
+ UINT8 Length; ///< 40
+ UINT16 Reserved; ///< Reserved
+ CRAT_HSA_PROCESSING_UNIT_FLAG Flags; ///< Flags - HSA Processing Unit Affinity Structure
+ UINT32 ProximityDomain; ///< Integer that represents the proximity domain to which the node belongs to
+ UINT32 ProcessorIdLow; ///< Low value of the logical processor included in this HSA proximity domain
+ UINT16 NumCPUCores; ///< Indicates count of CCompute execution units present in this APU node.
+ UINT16 NumSIMDCores; ///< Indicates maximum count of HCompute SIMD cores present in this node.
+ UINT16 MaxWavesSIMD; ///< This identifies the max. number of launched waves per SIMD.
+ UINT16 IoCount; ///< Number of discoverable IO Interfaces connecting this node to other components.
+ UINT16 HSACapability; ///< Must be 0
+ UINT16 LDSSizeInKB; ///< Size of LDS memory per SIMD Wavefront
+ UINT8 WaveFrontSize; ///< 64, may be 32 for some FSA based architectures
+ UINT8 NumBanks; ///< Number of Banks or "Shader Engines", typically 1 or 2
+ UINT16 uEngineIdentifier; ///< Identifier (Rev) of the GPU uEngine or firmware
+ UINT8 NumArrays; ///< Number of SIMD Arrays per Engine
+ UINT8 NumCUPerArray; ///< Number of Compute Units (CU) per SIMD Array
+ UINT8 NumSIMDPerCU; ///< Number of SIMD representing a Compute Unit
+ UINT8 MaxSlotsScratchCU; ///< Max. Number of temp. memory ("scratch") wave slots
+ ///< available to access, may be 0 if HW has no restrictions
+ UINT8 Reserved1[4]; ///< Reserved
+} CRAT_HSA_PROCESSING_UNIT;
+
+/// Flags field of the CRAT Memory Affinity Structure
+typedef struct {
+ UINT32 Enabled:1; ///< Enabled
+ UINT32 HotPluggable:1; ///< Hot Pluggable
+ UINT32 NonVolatile:1; ///< If set, the memory region represents Non-Volatile memory
+ UINT32 :29; ///< Reserved
+} CRAT_MEMORY_FLAG;
+
+/// CRAT Memory Affinity Structure
+typedef struct {
+ UINT8 Type; ///< 1 - CRAT Memory Affinity Structure
+ UINT8 Length; ///< 40
+ UINT16 Reserved; ///< Reserved
+ CRAT_MEMORY_FLAG Flags; ///< Flags - Memory Affinity Structure. Indicates whether the region of memory is enabled and can be hot plugged
+ UINT32 ProximityDomain; ///< Integer that represents the proximity domain to which the node belongs to
+ UINT32 BaseAddressLow; ///< Low 32Bits of the Base Address of the memory range
+ UINT32 BaseAddressHigh; ///< High 32Bits of the Base Address of the memory range
+ UINT32 LengthLow; ///< Low 32Bits of the length of the memory range
+ UINT32 LengthHigh; ///< High 32Bits of the length of the memory range
+ UINT32 Width; ///< Memory width - Specifies the number of parallel bits of the memory interface
+ UINT8 Reserved1[8]; ///< Reserved
+} CRAT_MEMORY;
+
+/// Flags field of the CRAT Cache Affinity structure
+typedef struct {
+ UINT32 Enabled:1; ///< Enabled
+ UINT32 DataCache:1; ///< 1 if cache includes data
+ UINT32 InstructionCache:1; ///< 1 if cache includes instructions
+ UINT32 CpuCache:1; ///< 1 if cache is part of CPU functionality
+ UINT32 SimdCache:1; ///< 1 if cache is part of SIMD functionality
+ UINT32 :27; ///< Reserved
+} CRAT_CACHE_FLAG;
+
+/// CRAT Cache Affinity Structure
+typedef struct {
+ UINT8 Type; ///< 2 - CRAT Cache Affinity Structure
+ UINT8 Length; ///< 64
+ UINT16 Reserved; ///< Reserved
+ CRAT_CACHE_FLAG Flags; ///< Flags - Cache Affinity Structure. Indicates whether the region of cache is enabled
+ UINT32 ProcessorIdLow; ///< Low value of a logical processor which includes this component
+ UINT8 SiblingMap[32]; ///< Bitmask of Processor Id sharing this component. 1 bit per logical processor
+ UINT32 CacheSize; ///< Cache size in KB
+ UINT8 CacheLevel; ///< Integer representing level: 1, 2, 3, 4, etc.
+ UINT8 LinesPerTag; ///< Cache Lines per tag
+ UINT16 CacheLineSize; ///< Cache line size in bytes
+ UINT8 Associativity; ///< Cache associativity
+ ///< The associativity fields are encoded as follows:
+ ///< 00h: Reserved.
+ ///< 01h: Direct mapped.
+ ///< 02h-FEh: Associativity. (e.g., 04h = 4-way associative.)
+ ///< FFh: Fully associative
+ UINT8 CacheProperties; ///< Cache Properties bits [2:0] represent Inclusive/Exclusive property encoded.
+ ///< 0: Cache is strictly exclusive to lower level caches.
+ ///< 1: Cache is mostly exclusive to lower level caches.
+ ///< 2: Cache is strictly inclusive to lower level caches.
+ ///< 3: Cache is mostly inclusive to lower level caches.
+ ///< 4: Cache is a "constant cache" (= explicit update)
+ ///< 5: Cache is a "specialty cache" (e.g. Texture cache)
+ ///< 6-7: Reserved
+ ///< CacheProperties bits [7:3] are reserved
+ UINT16 CacheLatency; ///< Cost of time to access cache described in nanoseconds.
+ UINT8 Reserved1[8]; ///< Reserved
+} CRAT_CACHE;
+
+/// Flags field of the CRAT TLB Affinity structure
+typedef struct {
+ UINT32 Enabled:1; ///< Enabled
+ UINT32 DataTLB:1; ///< 1 if TLB includes translation information for data.
+ UINT32 InstructionTLB:1; ///< 1 if TLB includes translation information for instructions.
+ UINT32 CpuTLB:1; ///< 1 if TLB is part of CPU functionality
+ UINT32 SimdTLB:1; ///< 1 if TLB is part of SIMD functionality
+ UINT32 TLB4KBase256:1; ///< 1 if value in table is factored by 256 to get number of 4K entries
+ UINT32 :1; ///< Reserved
+ UINT32 TLB2MBase256:1; ///< 1 if value in table is factored by 256 to get number of 2M entries
+ UINT32 :1; ///< Reserved
+ UINT32 TLB1GBase256:1; ///< 1 if value in table is factored by 256 to get number of 1G entries
+ UINT32 :22; ///< Reserved
+} CRAT_TLB_FLAG;
+
+/// CRAT TLB Affinity Structure
+typedef struct {
+ UINT8 Type; ///< 3 - CRAT TLB Affinity Structure
+ UINT8 Length; ///< 64
+ UINT16 Reserved; ///< Reserved
+ CRAT_TLB_FLAG Flags; ///< Flags - TLB Affinity Structure. Indicates whether the TLB is enabled and defined
+ UINT32 ProcessorIdLow; ///< Low value of a logical processor which includes this component.
+ UINT8 SiblingMap[32]; ///< Bitmask of Processor Id sharing this component. 1 bit per logical processor
+ UINT32 TlbLevel; ///< Integer representing level: 1, 2, 3, 4, etc.
+ UINT8 DataTlbAssociativity2MB; ///< Data TLB associativity for 2MB pages
+ ///< The associativity fields are encoded as follows:
+ ///< 00h: Reserved.
+ ///< 01h: Direct mapped.
+ ///< 02h-FEh: Associativity. (e.g., 04h = 4-way associative.)
+ ///< FFh: Fully associative.
+ UINT8 DataTlbSize2MB; ///< Data TLB number of entries for 2MB.
+ UINT8 InstructionTlbAssociativity2MB; ///< Instruction TLB associativity for 2MB pages
+ ///< The associativity fields are encoded as follows:
+ ///< 00h: Reserved.
+ ///< 01h: Direct mapped.
+ ///< 02h-FEh: Associativity. (e.g., 04h = 4-way associative.)
+ ///< FFh: Fully associative.
+ UINT8 InstructionTlbSize2MB; ///< Instruction TLB number of entries for 2MB pages.
+ UINT8 DataTlbAssociativity4K; ///< Data TLB Associativity for 4KB pages
+ UINT8 DataTlbSize4K; ///< Data TLB number of entries for 4KB pages
+ UINT8 InstructionTlbAssociativity4K; ///< Instruction TLB Associativity for 4KB pages
+ UINT8 InstructionTlbSize4K; ///< Instruction TLB number of entries for 4KB pages
+ UINT8 DataTlbAssociativity1G; ///< Data TLB Associativity for 1GB pages
+ UINT8 DataTlbSize1G; ///< Data TLB number of entries for 1GB pages
+ UINT8 InstructionTlbAssociativity1G; ///< Instruction TLB Associativity for 1GB pages
+ UINT8 InstructionTlbSize1G; ///< Instruction TLB number of entries for 1GB pages
+ UINT8 Reserved1[4]; ///< Reserved
+} CRAT_TLB;
+
+/// Flags field of the CRAT FPU Affinity structure
+typedef struct {
+ UINT32 Enabled:1; ///< Enabled
+ UINT32 :31; ///< Reserved
+} CRAT_FPU_FLAG;
+
+/// CRAT FPU Affinity Structure
+typedef struct {
+ UINT8 Type; ///< 4 - CRAT FPU Affinity Structure
+ UINT8 Length; ///< 64
+ UINT16 Reserved; ///< Reserved
+ CRAT_FPU_FLAG Flags; ///< Flags - FPU Affinity Structure. Indicates whether the region of FPU affinity structure is enabled and defined
+ UINT32 ProcessorIdLow; ///< Low value of a logical processor which includes this component.
+ UINT8 SiblingMap[32]; ///< Bitmask of Processor Id sharing this component. 1 bit per logical processor
+ UINT32 FPUSize; ///< Product specific
+ UINT8 Reserved1[16]; ///< Reserved
+} CRAT_FPU;
+
+/// Flags field of the CRAT IO Affinity structure
+typedef struct {
+ UINT32 Enabled:1; ///< Enabled
+ UINT32 Coherency:1; ///< If set, IO interface supports coherent transactions (natively or through protocol extensions)
+ UINT32 :30; ///< Reserved
+} CRAT_IO_FLAG;
+
+/// CRAT IO Affinity Structure
+typedef struct {
+ UINT8 Type; ///< 5 - CRAT IO Affinity Structure
+ UINT8 Length; ///< 64
+ UINT16 Reserved; ///< Reserved
+ CRAT_IO_FLAG Flags; ///< Flags - IO Affinity Structure. Indicates whether the region of IO affinity structure is enabled and defined.
+ UINT32 ProximityDomainFrom; ///< Integer that represents the proximity domain to which the IO Interface belongs to
+ UINT32 ProximityDomainTo; ///< Integer that represents the other proximity domain to which the IO Interface belongs to
+ UINT8 IoType; ///< IO Interface type. Values defined are
+ ///< 0: Undefined
+ ///< 1: Hypertransport
+ ///< 2: PCI Express
+ ///< 3: Other (e.g. internal)
+ ///< 4-255: Reserved
+ UINT8 VersionMajor; ///< Major version of the Bus interface
+ UINT16 VersionMinor; ///< Minor version of the Bus interface ((optional)
+ UINT32 MinimumLatency; ///< Cost of time to transfer, described in nanoseconds.
+ UINT32 MaximumLatency; ///< Cost of time to transfer, described in nanoseconds.
+ UINT32 MinimumBandwidth; ///< Minimum interface Bandwidth in MB/s
+ UINT32 MaximumBandwidth; ///< Maximum interface Bandwidth in MB/s
+ UINT32 RecommendedTransferSize; ///< Recommended transfer size to reach maximum interface bandwidth in Bytes
+ UINT8 Reserved1[24]; ///< Reserved
+} CRAT_IO;
+
+#define CRAT_MAX_LENGTH 0x800ul ///< Reserve 2K for CRAT
+#define LOW_NODE_DEVICEID 24
+/// CRAT entry type
+typedef enum {
+ CRAT_TYPE_HSA_PROC_UNIT = 0, ///< 0 - CRAT HSA Processing Unit Structure
+ CRAT_TYPE_MEMORY, ///< 1 - CRAT Memory Affinity Structure
+ CRAT_TYPE_CACHE, ///< 2 - CRAT Cache Affinity Structure
+ CRAT_TYPE_TLB, ///< 3 - CRAT TLB Affinity Structure
+ CRAT_TYPE_FPU, ///< 4 - CRAT FPU Affinity Structure
+ CRAT_TYPE_IO, ///< 5 - CRAT IO Affinity Structure
+} CRAT_ENTRY_TYPE;
+
+/*----------------------------------------------------------------------------------------
+ * F U N C T I O N P R O T O T Y P E
+ *----------------------------------------------------------------------------------------
+ */
+
+AGESA_STATUS
+AmdCpuLate (
+ IN AMD_CONFIG_PARAMS *StdHeader,
+ IN PLATFORM_CONFIGURATION *PlatformConfig
+ );
+
+AGESA_STATUS
+CreateAcpiWhea (
+ IN OUT AMD_CONFIG_PARAMS *StdHeader,
+ IN OUT VOID **WheaMcePtr,
+ IN OUT VOID **WheaCmcPtr
+ );
+
+AGESA_STATUS
+CreateDmiRecords (
+ IN AMD_CONFIG_PARAMS *StdHeader,
+ IN OUT DMI_INFO **DmiTable
+ );
+
+AGESA_STATUS
+GetType4Type7Info (
+ IN AMD_CONFIG_PARAMS *StdHeader,
+ IN DMI_INFO *DmiBufferPtr
+ );
+
+VOID
+DmiGetT4ProcFamilyFromBrandId (
+ IN OUT UINT8 *T4ProcFamily,
+ IN PROC_FAMILY_TABLE *CpuDmiProcFamilyTable,
+ IN CPU_TYPE_INFO *CpuInfo,
+ IN AMD_CONFIG_PARAMS *StdHeader
+ );
+
+VOID
+GetNameString (
+ IN OUT CHAR8 *String,
+ IN AMD_CONFIG_PARAMS *StdHeader
+ );
+
+BOOLEAN
+IsSourceStrContainTargetStr (
+ IN OUT CHAR8 *SourceStr,
+ IN OUT CONST CHAR8 *TargetStr,
+ IN AMD_CONFIG_PARAMS *StdHeader
+ );
+
+AGESA_STATUS
+CreateAcpiCrat (
+ IN OUT AMD_CONFIG_PARAMS *StdHeader,
+ OUT VOID **CratPtr
+ );
+
+AGESA_STATUS
+CreateAcpiCdit (
+ IN OUT AMD_CONFIG_PARAMS *StdHeader,
+ IN PLATFORM_CONFIGURATION *PlatformConfig,
+ OUT VOID **CditPtr
+ );
+
+VOID
+ChecksumAcpiTable (
+ IN OUT ACPI_TABLE_HEADER *Table,
+ IN AMD_CONFIG_PARAMS *StdHeader
+ );
+
+AGESA_STATUS
+RunLateApTaskOnAllAPs (
+ IN AP_EXE_PARAMS *ApParams,
+ IN AMD_CONFIG_PARAMS *StdHeader
+ );
+
+AGESA_STATUS
+IdleAllAps (
+ IN AMD_CONFIG_PARAMS *StdHeader
+ );
+
+UINT32
+InterlockedIncrement (
+ IN UINT32 *Value
+ );
+
+UINT32
+InterlockedDecrement (
+ IN UINT32 *Value
+ );
+
+#endif // _CPU_LATE_INIT_H_
diff --git a/src/vendorcode/amd/pi/00660F01/Proc/CPU/cpuRegisters.h b/src/vendorcode/amd/pi/00660F01/Proc/CPU/cpuRegisters.h
new file mode 100644
index 0000000..e51a01f
--- /dev/null
+++ b/src/vendorcode/amd/pi/00660F01/Proc/CPU/cpuRegisters.h
@@ -0,0 +1,502 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD CPU Register Table Related Functions
+ *
+ * Contains the definition of the CPU CPUID MSRs and PCI registers with BKDG recommended values
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: CPU
+ * @e \$Revision: 309899 $ @e \$Date: 2014-12-23 02:21:13 -0600 (Tue, 23 Dec 2014) $
+ *
+ */
+ /*****************************************************************************
+ *
+ * Copyright (c) 2008 - 2015, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ***************************************************************************/
+
+#ifndef _CPU_REGISTERS_H_
+#define _CPU_REGISTERS_H_
+
+#include "cpuFamRegisters.h"
+/*
+ *--------------------------------------------------------------
+ *
+ * M O D U L E S U S E D
+ *
+ *---------------------------------------------------------------
+ */
+
+/*
+ *--------------------------------------------------------------
+ *
+ * D E F I N I T I O N S / M A C R O S
+ *
+ *---------------------------------------------------------------
+ */
+
+#undef BIT0
+#undef BIT1
+#undef BIT2
+#undef BIT3
+#undef BIT4
+#undef BIT5
+#undef BIT6
+#undef BIT7
+#undef BIT8
+#undef BIT9
+#undef BIT10
+#undef BIT10
+#undef BIT11
+#undef BIT12
+#undef BIT13
+#undef BIT14
+#undef BIT15
+#undef BIT16
+#undef BIT17
+#undef BIT18
+#undef BIT19
+#undef BIT20
+#undef BIT21
+#undef BIT22
+#undef BIT23
+#undef BIT24
+#undef BIT25
+#undef BIT26
+#undef BIT27
+#undef BIT28
+#undef BIT29
+#undef BIT30
+#undef BIT31
+#undef BIT32
+#undef BIT33
+#undef BIT34
+#undef BIT35
+#undef BIT36
+#undef BIT37
+#undef BIT38
+#undef BIT39
+#undef BIT40
+#undef BIT41
+#undef BIT42
+#undef BIT43
+#undef BIT44
+#undef BIT45
+#undef BIT46
+#undef BIT47
+#undef BIT48
+#undef BIT49
+#undef BIT40
+#undef BIT41
+#undef BIT42
+#undef BIT43
+#undef BIT44
+#undef BIT45
+#undef BIT46
+#undef BIT47
+#undef BIT48
+#undef BIT49
+#undef BIT50
+#undef BIT51
+#undef BIT52
+#undef BIT53
+#undef BIT54
+#undef BIT55
+#undef BIT56
+#undef BIT57
+#undef BIT58
+#undef BIT59
+#undef BIT60
+#undef BIT61
+#undef BIT62
+#undef BIT63
+
+#define BIT0 0x0000000000000001ull
+#define BIT1 0x0000000000000002ull
+#define BIT2 0x0000000000000004ull
+#define BIT3 0x0000000000000008ull
+#define BIT4 0x0000000000000010ull
+#define BIT5 0x0000000000000020ull
+#define BIT6 0x0000000000000040ull
+#define BIT7 0x0000000000000080ull
+#define BIT8 0x0000000000000100ull
+#define BIT9 0x0000000000000200ull
+#define BIT10 0x0000000000000400ull
+#define BIT11 0x0000000000000800ull
+#define BIT12 0x0000000000001000ull
+#define BIT13 0x0000000000002000ull
+#define BIT14 0x0000000000004000ull
+#define BIT15 0x0000000000008000ull
+#define BIT16 0x0000000000010000ull
+#define BIT17 0x0000000000020000ull
+#define BIT18 0x0000000000040000ull
+#define BIT19 0x0000000000080000ull
+#define BIT20 0x0000000000100000ull
+#define BIT21 0x0000000000200000ull
+#define BIT22 0x0000000000400000ull
+#define BIT23 0x0000000000800000ull
+#define BIT24 0x0000000001000000ull
+#define BIT25 0x0000000002000000ull
+#define BIT26 0x0000000004000000ull
+#define BIT27 0x0000000008000000ull
+#define BIT28 0x0000000010000000ull
+#define BIT29 0x0000000020000000ull
+#define BIT30 0x0000000040000000ull
+#define BIT31 0x0000000080000000ull
+#define BIT32 0x0000000100000000ull
+#define BIT33 0x0000000200000000ull
+#define BIT34 0x0000000400000000ull
+#define BIT35 0x0000000800000000ull
+#define BIT36 0x0000001000000000ull
+#define BIT37 0x0000002000000000ull
+#define BIT38 0x0000004000000000ull
+#define BIT39 0x0000008000000000ull
+#define BIT40 0x0000010000000000ull
+#define BIT41 0x0000020000000000ull
+#define BIT42 0x0000040000000000ull
+#define BIT43 0x0000080000000000ull
+#define BIT44 0x0000100000000000ull
+#define BIT45 0x0000200000000000ull
+#define BIT46 0x0000400000000000ull
+#define BIT47 0x0000800000000000ull
+#define BIT48 0x0001000000000000ull
+#define BIT49 0x0002000000000000ull
+#define BIT50 0x0004000000000000ull
+#define BIT51 0x0008000000000000ull
+#define BIT52 0x0010000000000000ull
+#define BIT53 0x0020000000000000ull
+#define BIT54 0x0040000000000000ull
+#define BIT55 0x0080000000000000ull
+#define BIT56 0x0100000000000000ull
+#define BIT57 0x0200000000000000ull
+#define BIT58 0x0400000000000000ull
+#define BIT59 0x0800000000000000ull
+#define BIT60 0x1000000000000000ull
+#define BIT61 0x2000000000000000ull
+#define BIT62 0x4000000000000000ull
+#define BIT63 0x8000000000000000ull
+
+/// CPUID related registers
+#define AMD_CPUID_FMF 0x80000001ul // Family Model Features information
+#define AMD_CPUID_APICID_LPC_BID 0x00000001ul // Local APIC ID, Logical Processor Count, Brand ID
+#define AMD_CPUID_L2L3Cache_L2TLB 0x80000006ul
+#define CPUID_ASSOCIATIVITY_DISABLED 0x00
+#define CPUID_ASSOCIATIVITY_1_WAY 0x01
+#define CPUID_ASSOCIATIVITY_2_WAY 0x02
+#define CPUID_ASSOCIATIVITY_4_WAY 0x04
+#define CPUID_ASSOCIATIVITY_8_WAY 0x06
+#define CPUID_ASSOCIATIVITY_16_WAY 0x08
+#define CPUID_ASSOCIATIVITY_32_WAY 0x0A
+#define CPUID_ASSOCIATIVITY_48_WAY 0x0B
+#define CPUID_ASSOCIATIVITY_64_WAY 0x0C
+#define CPUID_ASSOCIATIVITY_96_WAY 0x0D
+#define CPUID_ASSOCIATIVITY_128_WAY 0x0E
+#define CPUID_ASSOCIATIVITY_FULLY 0x0F
+#define AMD_CPUID_TLB_L1Cache 0x80000005ul
+#define AMD_CPUID_L1L2Tlb1GIdentifiers 0x80000019ul
+#define AMD_CPUID_APM 0x80000007ul
+#define LOCAL_APIC_ID 24
+#define LOGICAL_PROCESSOR_COUNT 16
+#define AMD_CPUID_ASIZE_PCCOUNT 0x80000008ul // Address Size, Physical Core Count
+
+/// CPU Logical ID Transfer
+typedef struct {
+ UINT32 RawId; ///< RawID
+ UINT16 LogicalId; ///< LogicalID
+} CPU_LOGICAL_ID_XLAT;
+
+/// Logical CPU ID Table
+typedef struct {
+ IN UINT32 Elements; ///< Number of Elements
+ IN CPU_LOGICAL_ID_XLAT *LogicalIdTable; ///< CPU Logical ID Transfer table Pointer
+} LOGICAL_ID_TABLE;
+
+// MSRs
+// ------------------------
+#define MCG_CTL_P 0x00000100ul // bit 8 for MCG_CTL_P under MSRR
+#define MSR_MCG_CAP 0x00000179ul
+#define DBG_CTL_MSR 0x000001D9ul
+#define MSR_MC0_CTL 0x00000400ul
+#define MSR_MC0_STATUS 0x00000401ul
+#define MSR_MC0_MISC 0x00000403ul
+#define MSR_MC1_MISC 0x00000407ul
+#define MSR_MC2_MISC 0x0000040Bul
+#define MSR_MC4_MISC0 0x00000413ul
+#define MSR_MC5_MISC 0x00000417ul
+#define MSR_MC4_MISC1 0xC0000408ul
+#define MSR_MC5_STATUS 0x00000415ul
+#define MSR_MC6_STATUS 0x00000419ul
+
+#define MSR_APIC_BAR 0x0000001Bul
+#define MSR_PATCH_LEVEL 0x0000008Bul
+
+#define CPUID_LONG_MODE_ADDR 0x80000008ul
+
+#define MSR_EXTENDED_FEATURE_EN 0xC0000080ul
+#define MSR_MC_MISC_LINK_THRESHOLD 0xC0000408ul
+#define MSR_MC_MISC_L3_THRESHOLD 0xC0000409ul
+#define MSR_PATCH_LOADER 0xC0010020ul
+
+/// Patch Loader Register
+typedef struct {
+ UINT64 PatchBase:32; ///< Linear address of patch header address block
+ UINT64 SBZ:32; ///< Should be zero
+} PATCH_LOADER_MSR;
+
+#define AMD_MTRR_VARIABLE_BASE0 0x200
+#define AMD_MTRR_VARIABLE_BASE6 0x20C
+#define AMD_MTRR_FIX64k_00000 0x250
+#define AMD_MTRR_FIX16k_80000 0x258
+#define AMD_MTRR_FIX16k_A0000 0x259
+#define AMD_MTRR_FIX4k_C0000 0x268
+#define AMD_MTRR_FIX4k_C8000 0x269
+#define AMD_MTRR_FIX4k_D0000 0x26A
+#define AMD_MTRR_FIX4k_D8000 0x26B
+#define AMD_MTRR_FIX4k_E0000 0x26C
+#define AMD_MTRR_FIX4k_E8000 0x26D
+#define AMD_MTRR_FIX4k_F0000 0x26E
+#define AMD_MTRR_FIX4k_F8000 0x26F
+
+#define AMD_MTRR_FIX64K_WB_DRAM 0x1E1E1E1E1E1E1E1Eull
+#define AMD_MTRR_FIX64K_WT_DRAM 0x1C1C1C1C1C1C1C1Cull
+#define AMD_MTRR_FIX64K_UC_DRAM 0x1818181818181818ull
+#define AMD_MTRR_FIX16K_WB_DRAM 0x1E1E1E1E1E1E1E1Eull
+#define AMD_MTRR_FIX16K_WT_DRAM 0x1C1C1C1C1C1C1C1Cull
+#define AMD_MTRR_FIX16K_UC_DRAM 0x1818181818181818ull
+#define AMD_MTRR_FIX4K_WB_DRAM 0x1E1E1E1E1E1E1E1Eull
+#define AMD_MTRR_FIX4K_WT_DRAM 0x1C1C1C1C1C1C1C1Cull
+#define AMD_MTRR_FIX4K_UC_DRAM 0x1818181818181818ull
+
+
+#define MSR_SYS_CFG 0xC0010010ul // SYSCFG
+#define MSR_TOM 0xC001001Aul // TOP_MEM
+#define MSR_TOM2 0xC001001Dul // TOP_MEM2
+#define MSR_MC0_CTL_MASK 0xC0010044ul // MC0 Control Mask
+#define MSR_MC1_CTL_MASK 0xC0010045ul // MC1 Control Mask
+#define MSR_MC2_CTL_MASK 0xC0010046ul // MC2 Control Mask
+#define MSR_MC4_CTL_MASK 0xC0010048ul // MC4 Control Mask
+
+#define MSR_CPUID_FEATS 0xC0011004ul // CPUID Features
+#define MSR_CPUID_EXT_FEATS 0xC0011005ul // CPUID Extended Features
+#define MSR_HDT_CFG 0xC001100Aul
+#define MSR_HWCR 0xC0010015ul
+#define MSR_NB_CFG 0xC001001Ful // NB Config
+#define MSR_HTC 0xC001003Eul
+#define CPU_WDT_CFG 0xC0010074ul
+#define ENABLE_CF8_EXT_CFG 0x00004000ul // [46]
+#define INIT_APIC_CPUID_LO 0x00400000ul // [54]
+#define MSR_CU_SPMCTL 0xC0010281ul
+#define MSR_LS_CFG 0xC0011020ul
+#define MSR_IC_CFG 0xC0011021ul // ICache Config - F15 Shared
+#define MSR_DC_CFG 0xC0011022ul
+#define MSR_ME_CFG 0xC0011029ul
+#define MSR_BU_CFG 0xC0011023ul
+#define MSR_CU_CFG 0xC0011023ul // F15 Shared
+#define MSR_DE_CFG 0xC0011029ul // F15 Shared
+#define MSR_BU_CFG2 0xC001102Aul
+#define MSR_CU_CFG2 0xC001102Aul // F15 Shared
+#define MSR_BU_CFG3 0xC001102Bul
+#define MSR_CU_CFG3 0xC001102Bul // F15 Shared
+#define MSR_LS_CFG2 0xC001102Dul
+#define MSR_CU_PFTCFG 0xC001102Ful
+#define MSR_IBS_OP_DATA3 0xC0011037ul
+#define MSR_C001_1070 0xC0011070ul // F15 Shared
+#define MSR_CU_CBBCFG 0xC00110A1ul // F15 CZ
+
+
+#define MSR_CPUID_NAME_STRING0 0xC0010030ul // First CPUID namestring register
+#define MSR_CPUID_NAME_STRING1 0xC0010031ul
+#define MSR_CPUID_NAME_STRING2 0XC0010032ul
+#define MSR_CPUID_NAME_STRING3 0xC0010033ul
+#define MSR_CPUID_NAME_STRING4 0xC0010034ul
+#define MSR_CPUID_NAME_STRING5 0xC0010035ul // Last CPUID namestring register
+#define MSR_MMIO_Cfg_Base 0xC0010058ul // MMIO Configuration Base Address Register
+#define MSR_BIST 0xC0010060ul // BIST Results register
+#define MSR_OSVW_ID_Length 0xC0010140ul
+#define MSR_OSVW_Status 0xC0010141ul
+#define MSR_NB_PERF_CTL0 0xC0010240ul
+#define MSR_NB_PERF_CTR0 0xC0010241ul
+#define MSR_NB_PERF_CTL1 0xC0010242ul
+#define MSR_NB_PERF_CTR1 0xC0010243ul
+#define MSR_NB_PERF_CTL2 0xC0010244ul
+#define MSR_NB_PERF_CTR2 0xC0010245ul
+#define MSR_NB_PERF_CTL3 0xC0010246ul
+#define MSR_NB_PERF_CTR3 0xC0010247ul
+#define CU_SPMCTL 0xC0010281ul // Streaming Performance Monitor Control
+#define MSR_PERF_CONTROL3 0xC0010003ul // Performance control register number 3
+#define MSR_PERF_COUNTER3 0xC0010007ul // Performance counter register number 3
+#define PERF_RESERVE_BIT_MASK 0x030FFFDFFFFFull // Mask of the Performance control Reserve bits
+#define PERF_CAR_CORRUPTION_EVENT 0x040040F0E2ul // Configure the controller to capture the
+ // CAR Corruption
+// FUNC_0 registers
+// ----------------
+#define LINK_INIT_CTRL 0x6C
+#define LINK_INIT_CTRL_REQ_DIS 0x02 // [1] = ReqDis
+#define LINK_INIT_COLD_RST_DET BIT4
+#define LINK_INIT_BIOS_RST_DET_0 BIT5
+#define LINK_INIT_BIOS_RST_DET_1 BIT9
+#define LINK_INIT_BIOS_RST_DET_2 BIT10
+#define LINK_INIT_BIOS_RST_DET BIT9 | BIT10
+#define EXTENDED_NODE_ID 0x160
+
+#define CORE_CTRL 0x1DC
+#define CORE_CTRL_CORE1_EN 0x00000002ul
+#define CORE_CTRL_CORE2_EN 0x00000004ul
+#define CORE_CTRL_CORE3_EN 0x00000008ul
+#define CORE_CTRL_CORE4_EN 0x00000010ul
+#define CORE_CTRL_CORE5_EN 0x00000020ul
+#define CORE_CTRL_CORE6_EN 0x00000040ul
+#define CORE_CTRL_CORE7_EN 0x00000080ul
+#define CORE_CTRL_CORE8_EN 0x00000100ul
+#define CORE_CTRL_CORE9_EN 0x00000200ul
+
+// FUNC_3 registers
+// ----------------
+#define HARDWARE_THERMAL_CTRL_REG 0x64
+#define SOFTWARE_THERMAL_CTRL_REG 0x68
+
+#define ACPI_PSC_0_REG 0x80 // ACPI Power State Control Registers
+#define ACPI_PSC_4_REG 0x84
+
+#define NB_CFG_HIGH_REG 0x8C
+#define POWER_CTRL_MISCELLANEOUS_REG 0xA0
+#define CLOCK_POWER_TIMING_CTRL2_REG 0xDC
+#define NORTH_BRIDGE_CAPABILITIES_REG 0xE8
+#define MULTI_NODE_CPU 29
+#define CPUID_FMR 0xFC // Family / Model registers
+#define DOWNCORE_CTRL 0x190 // Downcore Control Register
+
+#define LINK_TO_XCS_TOKEN_COUNT_REG_3X148 0x148
+#define REG_HT4_PHY_OFFSET_BASE_4X180 0x180
+#define REG_HT4_PHY_DATA_PORT_BASE_4X184 0x184
+
+// FUNC_4 registers
+// ----------------
+/* Native Die CPUID Register F4x160 */
+#define NATIVE_DIE_CPUID_REG 0x160
+#define NATIVE_DIE_CPUID_PCI_ADDR (MAKE_SBDFO (0, 0, 0x18, FUNC_4, NATIVE_DIE_CPUID_REG))
+
+/// Native Die CPUID PCI Register
+typedef struct {
+ UINT32 Stepping:4; ///< Stepping
+ UINT32 BaseModel:4; ///< Base Model
+ UINT32 BaseFamily:4; ///< Base Family
+ UINT32 :4; ///< Reserved
+ UINT32 ExtModel:4; ///< Extended Model
+ UINT32 ExtFamily:8; ///< Extended Family
+ UINT32 :4; ///< Reserved
+} NATIVE_DIE_CPUID_REGISTER;
+
+// FUNC_5 registers
+// ----------------
+#define COMPUTE_UNIT_STATUS 0x80
+#define NORTH_BRIDGE_CAPABILITIES_2_REG 0x84
+
+
+// Misc. defines.
+#define PCI_DEV_BASE 24
+
+#define CPUID_STEPPING_MASK 0x0000000Ful
+#define CPUID_BASE_MODEL_MASK 0x000000F0ul
+#define CPUID_BASE_FAMILY_MASK 0x00000F00ul
+#define CPUID_EXT_MODEL_MASK 0x000F0000ul
+#define CPUID_EXT_FAMILY_MASK 0x0FF00000ul
+
+#define CZ_SOCKET_FP4 0
+#define SOCKET_IGNORE 0xF
+
+#define LAPIC_BASE_ADDR_MASK 0x0000FFFFFFFFF000ull
+#define APIC_EXT_BRDCST_MASK 0x000E0000ul
+#define APIC_ENABLE_BIT 0x00000800ul
+#ifndef LOCAL_APIC_ADDR
+#define LOCAL_APIC_ADDR 0xFEE00000ul
+#endif
+#define INT_CMD_REG_LO 0x300
+#define INT_CMD_REG_HI 0x310
+#define REMOTE_MSG_REG 0x380
+#define REMOTE_READ_REG 0xC0
+#define APIC_ID_REG 0x20
+#define APIC20_ApicId 24
+#define CMD_REG_TO_READ_DATA 0x338
+
+#define MAX_CORE_ID_SIZE 8
+#define MAX_CORE_ID_MASK ((1 << MAX_CORE_ID_SIZE) - 1)
+
+/*-------------------------
+ * Default definitions
+ *-------------------------
+ */
+#define DOWNCORE_MASK_SINGLE 0xFFFFFFFEul
+#define DOWNCORE_MASK_DUAL 0xFFFFFFFCul
+#define DOWNCORE_MASK_TRI 0xFFFFFFF8ul
+#define DOWNCORE_MASK_FOUR 0xFFFFFFF0ul
+#define DOWNCORE_MASK_FIVE 0xFFFFFFE0ul
+#define DOWNCORE_MASK_SIX 0xFFFFFFC0ul
+#define DOWNCORE_MASK_SEVEN 0xFFFFFF80ul
+#define DOWNCORE_MASK_EIGHT 0xFFFFFF00ul
+#define DOWNCORE_MASK_TEN 0xFFFFFC00ul
+#define DOWNCORE_MASK_TWELVE 0xFFFFF000ul
+#define DOWNCORE_MASK_FOURTEEN 0xFFFFC000ul
+#define DOWNCORE_MASK_DUAL_COMPUTE_UNIT 0xFFFFFFFAul
+#define DOWNCORE_MASK_TRI_COMPUTE_UNIT 0xFFFFFFEAul
+#define DOWNCORE_MASK_FOUR_COMPUTE_UNIT 0xFFFFFFAAul
+#define DOWNCORE_MASK_FIVE_COMPUTE_UNIT 0xFFFFFEAAul
+#define DOWNCORE_MASK_SIX_COMPUTE_UNIT 0xFFFFFAAAul
+#define DOWNCORE_MASK_SEVEN_COMPUTE_UNIT 0xFFFFEAAAul
+#define DOWNCORE_MASK_EIGHT_COMPUTE_UNIT 0xFFFFAAAAul
+
+#define DELIVERY_STATUS BIT13
+#define REMOTE_READ_STAT_MASK 0x00030000ul
+#define REMOTE_DELIVERY_PENDING 0x00010000ul
+#define REMOTE_DELIVERY_DONE 0x00020000ul
+
+/*
+ * --------------------------------------------------------------------------------------
+ *
+ * D E F I N E S / T Y P E D E F S / S T R U C T U R E S
+ *
+ * --------------------------------------------------------------------------------------
+ */
+
+/// CpuEarly param type
+typedef struct {
+ IN UINT8 MemInitPState; ///< Pstate value during memory initial
+ IN PLATFORM_CONFIGURATION PlatformConfig; ///< Runtime configurable user options
+} AMD_CPU_EARLY_PARAMS;
+
+/// CPUID
+typedef enum {
+ REG_EAX, ///< EAX
+ REG_EBX, ///< EBX
+ REG_ECX, ///< ECX
+ REG_EDX ///< EDX
+} CPUID_REG;
+
+#endif // _CPU_REGISTERS_H_
+
diff --git a/src/vendorcode/amd/pi/00660F01/Proc/CPU/heapManager.h b/src/vendorcode/amd/pi/00660F01/Proc/CPU/heapManager.h
new file mode 100644
index 0000000..915144f
--- /dev/null
+++ b/src/vendorcode/amd/pi/00660F01/Proc/CPU/heapManager.h
@@ -0,0 +1,241 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD Heap Manager and Heap Allocation APIs, and related functions.
+ *
+ * Contains code that initialize, maintain, and allocate the heap space.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: CPU
+ * @e \$Revision: 309090 $ @e \$Date: 2014-12-09 12:28:05 -0600 (Tue, 09 Dec 2014) $
+ *
+ */
+ /*****************************************************************************
+ *
+ * Copyright (c) 2008 - 2015, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ***************************************************************************/
+
+#ifndef _HEAP_MANAGER_H_
+#define _HEAP_MANAGER_H_
+
+/*---------------------------------------------------------------------------------------
+ * M I X E D (Definitions And Macros / Typedefs, Structures, Enums)
+ *---------------------------------------------------------------------------------------
+ */
+
+
+/*---------------------------------------------------------------------------------------
+ * D E F I N I T I O N S A N D M A C R O S
+ *---------------------------------------------------------------------------------------
+ */
+#define AMD_MTRR_VARIABLE_BASE0 0x200
+#define AMD_MTRR_VARIABLE_HEAP_BASE 0x20A
+#define AMD_MTRR_VARIABLE_HEAP_MASK (AMD_MTRR_VARIABLE_HEAP_BASE + 1)
+
+#define AMD_HEAP_START_ADDRESS 0x400000ul
+#define AMD_HEAP_REGION_END_ADDRESS 0xBFFFFFul
+#define AMD_HEAP_SIZE_PER_CORE 0x010000ul
+#define AMD_HEAP_INVALID_HEAP_OFFSET 0xFFFFFFFFul
+#define AMD_HEAP_MTRR_MASK ((0xFFFFFFFFFFFFF800ull & (((UINT64)AMD_HEAP_SIZE_PER_CORE ^ (-1)) + 1)) | 0x800)
+#define AMD_HEAP_SIZE_DWORD_PER_CORE (AMD_HEAP_SIZE_PER_CORE / 4)
+
+#define AMD_TEMP_TOM 0x20000000ul // Set TOM to 512 MB (temporary value)
+#define AMD_VAR_MTRR_ENABLE_BIT 0x100000ul // bit 20
+
+#define AMD_HEAP_RAM_ADDRESS 0xB0000ul
+
+#define HEAP_SIGNATURE_VALID 0x50414548ul // Signature: 'HEAP'
+#define HEAP_SIGNATURE_INVALID 0x00000000ul // Signature cleared
+
+///Heap Manager Life cycle
+#define HEAP_DO_NOT_EXIST_YET 1
+#define HEAP_LOCAL_CACHE 2
+#define HEAP_TEMP_MEM 3
+#define HEAP_SYSTEM_MEM 4
+#define HEAP_DO_NOT_EXIST_ANYMORE 5
+#define HEAP_S3_RESUME 6
+#define HEAP_RUNTIME_SYSTEM_MEM 7
+
+///Heap callout
+#define HEAP_CALLOUT_BOOTTIME 0
+#define HEAP_CALLOUT_RUNTIME 1
+
+/*---------------------------------------------------------------------------------------
+ * T Y P E D E F S, S T R U C T U R E S, E N U M S
+ *---------------------------------------------------------------------------------------
+ */
+/// Allocate Heap Parameters
+typedef struct _ALLOCATE_HEAP_PARAMS {
+ UINT32 RequestedBufferSize; ///< Size of buffer.
+ UINT32 BufferHandle; ///< An unique ID of buffer.
+ UINT8 Persist; ///< A flag. If marked, to be stored and passed to AmdInitLate.
+ UINT8 *BufferPtr; ///< Pointer to buffer.
+} ALLOCATE_HEAP_PARAMS;
+
+/// Locate Heap Parameters
+typedef struct _LOCATE_HEAP_PTR {
+ UINT32 BufferHandle; ///< An unique ID of buffer.
+ UINT32 BufferSize; ///< Data buffer size.
+ UINT8 *BufferPtr; ///< Pointer to buffer.
+} LOCATE_HEAP_PTR;
+
+/// Heap Node Header
+typedef struct _BUFFER_NODE {
+ UINT32 BufferHandle; ///< An unique ID of buffer.
+ UINT32 BufferSize; ///< Size of buffer.
+ UINT8 Persist; ///< A flag. If marked, to be stored and passed to AmdInitLate.
+ UINT8 PadSize; ///< Size of pad.
+ UINT32 OffsetOfNextNode; ///< Offset of next node (relative to the base).
+} BUFFER_NODE;
+
+/// Heap Manager
+typedef struct _HEAP_MANAGER {
+ UINT32 Signature; ///< a signature to indicate if the heap is valid.
+ UINT32 UsedSize; ///< Used size of heap.
+ UINT32 FirstActiveBufferOffset; ///< Offset of the first active buffer.
+ UINT32 FirstFreeSpaceOffset; ///< Offset of the first free space.
+} HEAP_MANAGER;
+
+/// AGESA Buffer Handles (These are reserved)
+typedef enum {
+ AMD_INIT_RESET_HANDLE = 0x000A000, ///< Assign 0x000A000 buffer handle to AmdInitReset routine.
+ AMD_INIT_EARLY_HANDLE, ///< Assign 0x000A001 buffer handle to AmdInitEarly routine.
+ AMD_INIT_POST_HANDLE, ///< Assign 0x000A002 buffer handle to AmdInitPost routine.
+ AMD_INIT_ENV_HANDLE, ///< Assign 0x000A003 buffer handle to AmdInitEnv routine.
+ AMD_INIT_MID_HANDLE, ///< Assign 0x000A004 buffer handle to AmdInitMid routine.
+ AMD_INIT_LATE_HANDLE, ///< Assign 0x000A005 buffer handle to AmdInitLate routine.
+ AMD_INIT_RESUME_HANDLE, ///< Assign 0x000A006 buffer handle to AmdInitResume routine.
+ AMD_LATE_RUN_AP_TASK_HANDLE, ///< Assign 0x000A007 buffer handle to AmdLateRunApTask routine.
+ AMD_INIT_RTB_HANDLE, ///< Assign 0x000A008 buffer handle to AmdInitRtb routine.
+ AMD_S3_LATE_RESTORE_HANDLE, ///< Assign 0x000A009 buffer handle to AmdS3LateRestore routine.
+ AMD_S3_SCRIPT_SAVE_TABLE_HANDLE, ///< Assign 0x000A00A buffer handle to be used for S3 save table
+ AMD_S3_SCRIPT_TEMP_BUFFER_HANDLE, ///< Assign 0x000A00B buffer handle to be used for S3 save table
+ AMD_CPU_AP_TASKING_HANDLE, ///< Assign 0x000A00C buffer handle to AP tasking input parameters.
+ AMD_REC_MEM_SOCKET_HANDLE, ///< Assign 0x000A00D buffer handle to save socket with memory in memory recovery mode.
+ AMD_MEM_AUTO_HANDLE, ///< Assign 0x000A00E buffer handle to AmdMemAuto routine.
+ AMD_MEM_SPD_HANDLE, ///< Assign 0x000A00F buffer handle to AmdMemSpd routine.
+ AMD_MEM_DATA_HANDLE, ///< Assign 0x000A010 buffer handle to MemData
+ AMD_MEM_TRAIN_BUFFER_HANDLE, ///< Assign 0x000A011 buffer handle to allocate buffer for training
+ AMD_MEM_S3_DATA_HANDLE, ///< Assign 0x000A012 buffer handle to special case register for S3
+ AMD_MEM_S3_NB_HANDLE, ///< Assign 0x000A013 buffer handle to NB block for S3
+ AMD_MEM_S3_MR0_DATA_HANDLE, ///< Assign 0x000A014 buffer handle to MR0 data block for S3
+ AMD_UMA_INFO_HANDLE, ///< Assign 0x000A015 buffer handle to be used for Uma information
+ AMD_DMI_MEM_DEV_INFO_HANDLE, ///< Assign 0x000A016 buffer handle to DMI Type16 17 19 20 information
+ EVENT_LOG_BUFFER_HANDLE, ///< Assign 0x000A017 buffer handle to Event Log
+ IDS_CONTROL_HANDLE, ///< Assign 0x000A018 buffer handle to AmdIds routine.
+ IDS_HDT_OUT_BUFFER_HANDLE, ///< Assign 0x000A019 buffer handle to be used for HDTOUT support.
+ IDS_CHECK_POINT_PERF_HANDLE, ///< Assign 0x000A01A buffer handle to Performance analysis
+ AMD_PCIE_COMPLEX_DATA_HANDLE, ///< Assign 0x000A01B buffer handle to be used for PCIe support
+ AMD_MEM_SYS_DATA_HANDLE, ///< Assign 0x000A01C buffer handle to be used for memory data structure
+ AMD_GNB_SMU_CONFIG_HANDLE, ///< Assign 0x000A01D buffer handle to be used for GNB SMU configuration
+ AMD_PP_FUSE_TABLE_HANDLE, ///< Assign 0x000A01E buffer handle to be used for TT fuse table
+ AMD_GFX_PLATFORM_CONFIG_HANDLE, ///< Assign 0x000A01F buffer handle to be used for Gfx platform configuration
+ AMD_GNB_TEMP_DATA_HANDLE, ///< Assign 0x000A020 buffer handle for GNB general purpose data block
+ AMD_MEM_2D_RDQS_HANDLE, ///< Assign 0x000A021 buffer handle for 2D training
+ AMD_MEM_2D_RD_WR_HANDLE, ///< Assign 0x000A022 buffer handle for 2D Read/Write training
+ AMD_GNB_IOMMU_SCRATCH_MEM_HANDLE, ///< Assign 0x000A023 buffer handle to be used for GNB IOMMU scratch memory
+ AMD_MEM_S3_SAVE_HANDLE, ///< Assign 0x000A024 buffer handle for memory data saved right after memory init
+ AMD_MEM_2D_RDQS_RIM_HANDLE, ///< Assign 0x000A025 buffer handle for 2D training Eye RIM Search
+ AMD_MEM_2D_RD_WR_RIM_HANDLE, ///< Assign 0x000A026 buffer handle for 2D Read/Write training Eye RIM Search
+ AMD_CPU_NB_PSTATE_FIXUP_HANDLE, ///< Assign 0x000A027 buffer handle for an NB P-state workaround
+ AMD_MEM_CRAT_INFO_BUFFER_HANDLE, ///< Assign 0x000A028 buffer handle for CRAT Memory affinity component structure
+ AMD_SKIP_MEM_S3_SAVE, ///< Assign 0x000A029 buffer handle for the flag to skip memory S3 save
+ AMD_IS_FEATURE_ENABLED, ///< Assign 0x000A02A buffer handle for keeping the result of IsFeatureEnabled
+ AMD_MEM_DATAEYE_WORK_AREA_HANDLE, ///< Assign 0x000A02B buffer handle for Composite Data Eye Compression Work Area
+ AMD_GNB_SAMU_PATCH_HANDLE, ///< Assign 0x000A02C buffer handle for Samu patch buffer
+ AMD_GNB_SAMU_BOOT_CONTROL_HANDLE, ///< Assign 0x000A02D buffer handle for Samu boot control buffer
+ AMD_GNB_ACP_ENGINE_HANDLE, ///< Assign 0x000A02E buffer handle for GNB ACP engine buffer
+ AMD_MEM_PMU_SRAM_MSG_BLOCK_HANDLE, ///< Assign 0x000A02F buffer handle for PMU SRAM Message Block buffer
+ AMD_MEM_DRAM_CAD_BUS_CONFIG_HANDLE, ///< Assign 0x000A030 buffer handle for DRAM CAD Bus Configuration
+ AMD_GNB_SMU_TABLE_HANDLE, ///< Assign 0x000A031 buffer handle for GNB SMU table buffer
+ AMD_GNB_CRAT_HSA_TABLE_HANDLE, ///< Assign 0x000A032 buffer handle for GNB CRAT HSA unit table
+ AMD_GNB_BUILD_OPTIONS_HANDLE, ///< Assign 0x000A033 buffer handle for GNB build options
+ AMD_S3_FINAL_RESTORE_HANDLE, ///< Assign 0x000A034 buffer handle to AmdS3FinalRestore routine.
+ AMD_GNB_PCIE_AER_CONFIG_HANDLE, ///< Assign 0x000A035 buffer handle for GNB PCIE AER configuration.
+ AMD_BTC_SCRATCH_HANDLE, ///< Assign 0x000A036 buffer handle for boot time calibration workloads
+ AMD_BTC_XMM_SAVE_HANDLE, ///< Assign 0x000A037 buffer handle for boot time calibration xmm register save
+ AMD_S3_SAVE_HANDLE, ///< Assign 0x000A038 buffer handle to memory context data
+ AMD_MEM_DDR_MAX_RATE_HANDLE, ///< Assign 0x000A039 buffer handle to memory DDR max rate
+ AMD_GNB_TDP_HANDLE, ///< Assign 0x000A03A buffer handle to GNB TDP
+ AMD_MEM_MISC_HANDLES_START = 0x1000000, ///< Reserve 0x1000000 to 0x1FFFFFF buffer handle
+ AMD_MEM_MISC_HANDLES_END = 0x1FFFFFF, ///< miscellaneous memory init tasks' buffers.
+ AMD_HEAP_IN_MAIN_MEMORY_HANDLE = 0x8000000, ///< Assign 0x8000000 to AMD_HEAP_IN_MAIN_MEMORY_HANDLE.
+ SOCKET_DIE_MAP_HANDLE = 0x534F4B54, ///< 'sokt'
+ NODE_ID_MAP_HANDLE = 0x4E4F4445, ///< 'node'
+ HOP_COUNT_TABLE_HANDLE = 0x484F5053, ///< 'hops'
+ AMD_FCH_RESET_DATA_BLOCK_HANDLE = 0x46434852, ///< 'FCHR' Buffer handle for FCH private data block at InitReset
+ AMD_FCH_DATA_BLOCK_HANDLE = 0x46434845, ///< 'FCHE' Buffer handle for FCH private data block at InitEnv
+ IDS_TRAP_TABLE_HANDLE = 0x49524547, ///< 'IREG' Handle for IDS register table
+ IDS_SAVE_IDTR_HANDLE = 0x49445452, ///< 'IDTR'
+ IDS_BSC_IDT_HANDLE = 0x42534349, ///< 'BSCI' BSC Idt table
+ IDS_NV_TO_CMOS_HANDLE = 0x534D4349, ///< 'ICMS' Handle for IDS CMOS save
+ IDS_GRA_HANDLE = 0x41524749, ///< 'IGRA' Handle for IDS GRA save
+ IDS_EXTEND_HANDLE = 0x54584549, ///< 'IEXT' Handle for IDS extend module
+ IDS_TEMP_DATA_HANDLE = 0x504D5459, ///< 'ITMP' Handle for IDS temp data
+} AGESA_BUFFER_HANDLE;
+
+
+/*---------------------------------------------------------------------------------------
+ * F U N C T I O N P R O T O T Y P E
+ *---------------------------------------------------------------------------------------
+ */
+
+AGESA_STATUS
+HeapManagerInit (
+ IN AMD_CONFIG_PARAMS *StdHeader
+ );
+
+AGESA_STATUS
+HeapAllocateBuffer (
+ IN OUT ALLOCATE_HEAP_PARAMS *AllocateHeapParams,
+ IN OUT AMD_CONFIG_PARAMS *StdHeader
+ );
+
+AGESA_STATUS
+HeapDeallocateBuffer (
+ IN UINT32 BufferHandle,
+ IN AMD_CONFIG_PARAMS *StdHeader
+ );
+
+AGESA_STATUS
+HeapLocateBuffer (
+ IN OUT LOCATE_HEAP_PTR *LocateHeap,
+ IN AMD_CONFIG_PARAMS *StdHeader
+ );
+
+UINT64
+HeapGetBaseAddress (
+ IN AMD_CONFIG_PARAMS *StdHeader
+ );
+
+AGESA_STATUS
+EventLogInitialization (
+ IN AMD_CONFIG_PARAMS *StdHeader
+ );
+#endif // _HEAP_MANAGER_H_
diff --git a/src/vendorcode/amd/pi/00660F01/Proc/Common/AmdFch.h b/src/vendorcode/amd/pi/00660F01/Proc/Common/AmdFch.h
new file mode 100644
index 0000000..f75f881
--- /dev/null
+++ b/src/vendorcode/amd/pi/00660F01/Proc/Common/AmdFch.h
@@ -0,0 +1,63 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD FCH Component
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: FCH
+ * @e \$Revision: 309090 $ @e \$Date: 2014-12-09 12:28:05 -0600 (Tue, 09 Dec 2014) $
+ *
+ */
+ /*****************************************************************************
+ *
+ * Copyright (c) 2008 - 2015, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ***************************************************************************/
+
+#ifndef _AMD_FCH_H_
+#define _AMD_FCH_H_
+
+typedef AGESA_STATUS FCH_INIT (IN VOID *DataPtr);
+typedef VOID FCH_TASK_ENTRY (IN VOID *FchCfg);
+
+
+/// FCH API build options
+typedef struct {
+ FCH_INIT *InitReset; ///< InitReset
+ FCH_INIT *InitResetConstructor; ///< InitResetConstructor
+ FCH_INIT *InitEnv; ///< InitEnv
+ FCH_INIT *InitEnvConstructor; ///< InitEnvConstructor
+ FCH_INIT *InitMid; ///< InitMid
+ FCH_INIT *InitMidConstructor; ///< InitMidConstructor
+ FCH_INIT *InitLate; ///< InitLate
+ FCH_INIT *InitLateConstructor; ///< InitLateConstructor
+} BLDOPT_FCH_FUNCTION;
+
+#endif
diff --git a/src/vendorcode/amd/pi/00660F01/Proc/Fch/Common/AcpiLib.h b/src/vendorcode/amd/pi/00660F01/Proc/Fch/Common/AcpiLib.h
new file mode 100644
index 0000000..6f87842
--- /dev/null
+++ b/src/vendorcode/amd/pi/00660F01/Proc/Fch/Common/AcpiLib.h
@@ -0,0 +1,90 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * FCH ACPI lib
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: FCH
+ * @e \$Revision: 309090 $ @e \$Date: 2014-12-09 12:28:05 -0600 (Tue, 09 Dec 2014) $
+ *
+ */
+ /*****************************************************************************
+ *
+ * Copyright (c) 2008 - 2015, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ***************************************************************************/
+#ifndef _FCH_ACPILIB_H_
+#define _FCH_ACPILIB_H_
+///
+/// RSDP - ACPI 2.0 table RSDP
+///
+typedef struct _RSDP_HEADER {
+ UINT64 Signature; ///< RSDP signature "RSD PTR"
+ UINT8 CheckSum; ///< checksum of the first 20 bytes
+ UINT8 OEMID[6]; ///< OEM ID
+ UINT8 Revision; ///< 0 for APCI 1.0, 2 for ACPI 2.0
+ UINT32 RsdtAddress; ///< physical address of RSDT
+ UINT32 Length; ///< total length of RSDP (including extended part)
+ UINT64 XsdtAddress; ///< physical address of XSDT
+ UINT8 ExtendedCheckSum; ///< chechsum of whole table
+ UINT8 Reserved[3]; ///< Reserved
+} RSDP_HEADER;
+
+///
+/// DESCRIPTION_HEADER - ACPI common table header
+///
+typedef struct _DESCRIPTION_HEADER {
+ UINT32 Signature; ///< ACPI signature (4 ASCII characters)
+ UINT32 Length; ///< Length of table, in bytes, including header
+ UINT8 Revision; ///< ACPI Specification minor version #
+ UINT8 CheckSum; ///< To make sum of entire table == 0
+ UINT8 OemId[6]; ///< OEM identification
+ UINT8 OemTableId[8]; ///< OEM table identification
+ UINT32 OemRevision; ///< OEM revision number
+ UINT32 CreatorId; ///< ASL compiler vendor ID
+ UINT32 CreatorRevision; ///< ASL compiler revision number
+} DESCRIPTION_HEADER;
+
+///
+/// _AcpiRegWrite - ACPI MMIO register R/W structure
+///
+typedef struct _ACPI_REG_WRITE {
+ UINT8 MmioBase; /// MmioBase: Index of Fch block (For instance GPIO_BASE:0x01 SMI_BASE:0x02)
+ UINT8 MmioReg; /// MmioReg : Register index
+ UINT8 DataAndMask; /// DataANDMask : AND Register Data
+ UINT8 DataOrMask; /// DataOrMask : Or Register Data
+} ACPI_REG_WRITE;
+
+VOID* AcpiLocateTable (IN UINT32 Signature);
+VOID AcpiSetTableCheckSum (IN VOID *TablePtr);
+UINT8 AcpiGetTableCheckSum (IN VOID *TablePtr);
+UINT8 GetByteSum (IN VOID *DataPtr, IN UINT32 Length);
+
+#endif
diff --git a/src/vendorcode/amd/pi/00660F01/Proc/Fch/Common/FchBiosRamUsage.h b/src/vendorcode/amd/pi/00660F01/Proc/Fch/Common/FchBiosRamUsage.h
new file mode 100644
index 0000000..a694d11
--- /dev/null
+++ b/src/vendorcode/amd/pi/00660F01/Proc/Fch/Common/FchBiosRamUsage.h
@@ -0,0 +1,66 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * FCH BIOS Ram usage
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: FCH
+ * @e \$Revision: 309090 $ @e \$Date: 2014-12-09 12:28:05 -0600 (Tue, 09 Dec 2014) $
+ *
+ */
+ /*****************************************************************************
+ *
+ * Copyright (c) 2008 - 2015, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ***************************************************************************/
+#ifndef _FCH_BIOS_RAM_USAGE_H_
+#define _FCH_BIOS_RAM_USAGE_H_
+
+#define RESTORE_MEMORY_CONTROLLER_START 0
+#define XHCI_REGISTER_BAR00 0xD0
+#define XHCI_REGISTER_BAR01 0xD1
+#define XHCI_REGISTER_BAR02 0xD2
+#define XHCI_REGISTER_BAR03 0xD3
+#define XHCI_REGISTER_04H 0xD4
+#define XHCI_REGISTER_0CH 0xD5
+#define XHCI_REGISTER_3CH 0xD6
+#define XHCI1_REGISTER_BAR00 0xE0
+#define XHCI1_REGISTER_BAR01 0xE1
+#define XHCI1_REGISTER_BAR02 0xE2
+#define XHCI1_REGISTER_BAR03 0xE3
+#define XHCI1_REGISTER_04H 0xE4
+#define XHCI1_REGISTER_0CH 0xE5
+#define XHCI1_REGISTER_3CH 0xE6
+#define RTC_WORKAROUND_DATA_START 0xF0
+#define BOOT_TIME_FLAG_SEC 0xF8
+#define BOOT_TIME_FLAG_INT19 0xFC
+
+#endif
+
diff --git a/src/vendorcode/amd/pi/00660F01/Proc/Fch/Common/FchCommonCfg.h b/src/vendorcode/amd/pi/00660F01/Proc/Fch/Common/FchCommonCfg.h
new file mode 100644
index 0000000..fb2bae2
--- /dev/null
+++ b/src/vendorcode/amd/pi/00660F01/Proc/Fch/Common/FchCommonCfg.h
@@ -0,0 +1,1359 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * FCH Function Support Definition
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: FCH
+ * @e \$Revision: 311507 $ @e \$Date: 2015-01-22 06:57:51 +0800 (Thu, 22 Jan 2015) $
+ *
+ */
+ /*****************************************************************************
+ *
+ * Copyright (c) 2008 - 2015, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ***************************************************************************/
+#ifndef _FCH_COMMON_CFG_H_
+#define _FCH_COMMON_CFG_H_
+
+#pragma pack (push, 1)
+
+//-----------------------------------------------------------------------------
+// FCH DEFINITIONS AND MACROS
+//-----------------------------------------------------------------------------
+
+//
+// FCH Component Data Structure Definitions
+//
+
+/// PCI_ADDRESS - PCI access structure
+#define PCI_ADDRESS(bus, dev, func, reg) \
+ (UINT32) ( (((UINT32)bus) << 24) + (((UINT32)dev) << 19) + (((UINT32)func) << 16) + ((UINT32)reg) )
+
+#define CPUID_FMF 0x80000001ul // Family Model Features information
+///
+/// - Byte Register R/W structure
+///
+typedef struct _REG8_MASK {
+ UINT8 RegIndex; /// RegIndex - Reserved
+ UINT8 AndMask; /// AndMask - Reserved
+ UINT8 OrMask; /// OrMask - Reserved
+} REG8_MASK;
+
+
+///
+/// PCIE Reset Block
+///
+typedef enum {
+ NbBlock, ///< Reset for NB PCIE
+ FchBlock ///< Reset for FCH GPP
+} RESET_BLOCK;
+
+///
+/// PCIE Reset Operation
+///
+typedef enum {
+ DeassertReset, ///< DeassertRese - Deassert reset
+ AssertReset ///< AssertReset - Assert reset
+} RESET_OP;
+
+
+///
+/// Fch Run Time Parameters
+///
+typedef struct {
+ UINT32 PcieMmioBase; ///< PcieMmioBase
+ UINT32 FchDeviceEnableMap; ///< FchDeviceEnableMap
+ UINT32 FchDeviceD3ColdMap; ///< FchDeviceD3ColdMap
+ UINT16 XHCI_PMx04_XhciFwRomAddr_Rom; ///< XHCI_PMx04_XhciFwRomAddr_Rom
+ UINT32 XHCI_PMx08_xHCI_Firmware_Addr_1_Rom; ///< XHCI_PMx08_xHCI_Firmware_Addr_1_Ram
+ UINT16 XHCI_PMx04_XhciFwRomAddr_Ram; ///< XHCI_PMx04_XhciFwRomAddr_Rom
+ UINT32 XHCI_PMx08_xHCI_Firmware_Addr_1_Ram; ///< XHCI_PMx08_xHCI_Firmware_Addr_1_Ram
+ UINT8 SataDevSlpPort0S5Pin; ///< SataDevSlpPort0S5Pin - Reserved
+ UINT8 SataDevSlpPort1S5Pin; ///< SataDevSlpPort1S5Pin - Reserved
+ UINT16 Dummy16; ///< Dummy16 - Reserved
+ UINT32 SdMmioBase; ///< Sd Mmio Base - Reserved
+ UINT32 EhciMmioBase; ///< Ehci Mmio Base - Reserved
+ UINT32 XhciMmioBase; ///< Xhci Mmio Base - Reserved
+ UINT32 SataMmioBase; ///< Sata Mmio Base - Reserved
+} FCH_RUNTIME;
+
+///
+/// SD structure
+///
+typedef struct {
+ SD_MODE SdConfig; ///< SD Mode configuration
+ /// @li <b>00</b> - Disabled
+ /// @li <b>00</b> - AMDA
+ /// @li <b>01</b> - DMA
+ /// @li <b>10</b> - PIO
+ ///
+ UINT8 SdSpeed; ///< SD Speed
+ /// @li <b>0</b> - Low speed
+ /// @li <b>1</b> - High speed
+ ///
+ UINT8 SdBitWidth; ///< SD Bit Width
+ /// @li <b>0</b> - 32BIT clear 23
+ /// @li <b>1</b> - 64BIT, set 23,default
+ ///
+ UINT32 SdSsid; ///< SD Subsystem ID
+ SD_CLOCK_CONTROL SdClockControl; ///< SD Clock Control
+ BOOLEAN SdClockMultiplier; ///< SD Clock Multiplier enable/disable
+ UINT8 SdReTuningMode; ///< SD Re-tuning modes select
+ /// @li <b>0</b> - mode 1
+ /// @li <b>1</b> - mode 2
+ /// @li <b>2</b> - mode 3
+ UINT8 SdHostControllerVersion; ///< SD controller Version
+ /// @li <b>1</b> - SD 2.0
+ /// @li <b>2</b> - SD 3.0
+ UINT8 SdrCapabilities; ///< SDR Capability mode select
+ /// @li <b>00</b> - SDR25/15
+ /// @li <b>01</b> - SDR50
+ /// @li <b>11</b> - SDR104
+ UINT8 SdSlotType; ///< SDR Slot Type select
+ /// @li <b>00</b> - Removable Card Slot
+ /// @li <b>01</b> - Embedded Slot for One Device
+ /// @li <b>10</b> - Shared Bus Slot
+ BOOLEAN SdForce18; ///< SD Force18
+ UINT8 SdDbgConfig; ///< SD Mode configuration
+ /// @li <b>00</b> - Disabled
+ /// @li <b>00</b> - AMDA
+ /// @li <b>01</b> - DMA
+ /// @li <b>10</b> - PIO
+ ///
+} FCH_SD;
+
+///
+/// CODEC_ENTRY - Fch HD Audio OEM Codec structure
+///
+typedef struct _CODEC_ENTRY {
+ UINT8 Nid; /// Nid - Reserved
+ UINT32 Byte40; /// Byte40 - Reserved
+} CODEC_ENTRY;
+
+///
+/// CODEC_TBL_LIST - Fch HD Audio Codec table list
+///
+typedef struct _CODEC_TBL_LIST {
+ UINT32 CodecId; /// CodecID - Codec ID
+ CODEC_ENTRY* CodecTablePtr; /// CodecTablePtr - Codec table pointer
+} CODEC_TBL_LIST;
+
+///
+/// AZALIA_PIN - HID Azalia or GPIO define structure.
+///
+typedef struct _AZALIA_PIN {
+ UINT8 AzaliaSdin0; ///< AzaliaSdin0
+ /// @par
+ /// @li <b>00</b> - GPIO PIN
+ /// @li <b>10</b> - As a Azalia SDIN pin
+
+ UINT8 AzaliaSdin1; ///< AzaliaSdin1
+ /// @par
+ /// SDIN1 is define at BIT2 & BIT3
+ /// @li <b>00</b> - GPIO PIN
+ /// @li <b>10</b> - As a Azalia SDIN pin
+
+ UINT8 AzaliaSdin2; ///< AzaliaSdin2
+ /// @par
+ /// SDIN2 is define at BIT4 & BIT5
+ /// @li <b>00</b> - GPIO PIN
+ /// @li <b>10</b> - As a Azalia SDIN pin
+
+ UINT8 AzaliaSdin3; ///< AzaliaSdin3
+ /// @par
+ /// SDIN3 is define at BIT6 & BIT7
+ /// @li <b>00</b> - GPIO PIN
+ /// @li <b>10</b> - As a Azalia SDIN pin
+} AZALIA_PIN;
+
+///
+/// Azalia structure
+///
+typedef struct {
+ HDA_CONFIG AzaliaEnable; ///< AzaliaEnable - Azalia function configuration
+ BOOLEAN AzaliaMsiEnable; ///< AzaliaMsiEnable - Azalia MSI capability
+ UINT32 AzaliaSsid; ///< AzaliaSsid - Azalia Subsystem ID
+ UINT8 AzaliaPinCfg; ///< AzaliaPinCfg - Azalia Controller SDIN pin Configuration
+ /// @par
+ /// @li <b>0</b> - disable
+ /// @li <b>1</b> - enable
+
+ UINT8 AzaliaFrontPanel; ///< AzaliaFrontPanel - Azalia Controller Front Panel Configuration
+ /// @par
+ /// Support Front Panel configuration
+ /// @li <b>0</b> - Auto
+ /// @li <b>1</b> - disable
+ /// @li <b>2</b> - enable
+
+ UINT8 FrontPanelDetected; ///< FrontPanelDetected - Force Azalia Controller Front Panel Configuration
+ /// @par
+ /// Force Front Panel configuration
+ /// @li <b>0</b> - Not Detected
+ /// @li <b>1</b> - Detected
+
+ UINT8 AzaliaSnoop; ///< AzaliaSnoop - Azalia Controller Snoop feature Configuration
+ /// @par
+ /// Azalia Controller Snoop feature Configuration
+ /// @li <b>0</b> - disable
+ /// @li <b>1</b> - enable
+
+ UINT8 AzaliaDummy; /// AzaliaDummy - Reserved */
+
+ AZALIA_PIN AzaliaConfig; /// AzaliaConfig - Azaliz Pin Configuration
+
+///
+/// AZOEMTBL - Azalia Controller OEM Codec Table Pointer
+///
+ CODEC_TBL_LIST *AzaliaOemCodecTablePtr; /// AzaliaOemCodecTablePtr - Oem Azalia Codec Table Pointer
+
+///
+/// AZOEMFPTBL - Azalia Controller Front Panel OEM Table Pointer
+///
+ VOID *AzaliaOemFpCodecTablePtr; /// AzaliaOemFpCodecTablePtr - Oem Front Panel Codec Table Pointer
+} FCH_AZALIA;
+
+///
+/// _SPI_DEVICE_PROFILE Spi Device Profile structure
+///
+typedef struct _SPI_DEVICE_PROFILE {
+ UINT32 JEDEC_ID; /// JEDEC ID
+ UINT32 RomSize; /// ROM Size
+ UINT32 SectorSize; /// Sector Size
+ UINT16 MaxNormalSpeed; /// Max Normal Speed
+ UINT16 MaxFastSpeed; /// Max Fast Speed
+ UINT16 MaxDualSpeed; /// Max Dual Speed
+ UINT16 MaxQuadSpeed; /// Max Quad Speed
+ UINT8 QeReadRegister; /// QE Read Register
+ UINT8 QeWriteRegister; /// QE Write Register
+ UINT8 QeOperateSize; /// QE Operate Size 1byte/2bytes
+ UINT16 QeLocation; // QE Location in the register
+} SPI_DEVICE_PROFILE;
+
+///
+/// _SPI_CONTROLLER_PROFILE Spi Device Profile structure
+///
+typedef struct _SPI_CONTROLLER_PROFILE {
+// UINT32 SPI_CONTROLLER_ID; /// SPI Controller ID
+ UINT16 FifoSize; /// FIFO Size
+ UINT16 MaxNormalSpeed; /// Max Normal Speed
+ UINT16 MaxFastSpeed; /// Max Fast Speed
+ UINT16 MaxDualSpeed; /// Max Dual Speed
+ UINT16 MaxQuadSpeed; /// Max Quad Speed
+} SPI_CONTROLLER_PROFILE;
+
+///
+/// SPI structure
+///
+typedef struct {
+ BOOLEAN LpcMsiEnable; ///< LPC MSI capability
+ UINT32 LpcSsid; ///< LPC Subsystem ID
+ UINT32 RomBaseAddress; ///< SpiRomBaseAddress
+ /// @par
+ /// SPI ROM BASE Address
+ ///
+ UINT8 SpiSpeed; ///< SpiSpeed - Spi Frequency
+ /// @par
+ /// SPI Speed [1.0] - the clock speed for non-fast read command
+ /// @li <b>00</b> - 66Mhz
+ /// @li <b>01</b> - 33Mhz
+ /// @li <b>10</b> - 22Mhz
+ /// @li <b>11</b> - 16.5Mhz
+ ///
+ UINT8 SpiFastSpeed; ///< FastSpeed - Spi Fast Speed feature
+ /// SPIFastSpeed [1.0] - the clock speed for Fast Speed Feature
+ /// @li <b>00</b> - 66Mhz
+ /// @li <b>01</b> - 33Mhz
+ /// @li <b>10</b> - 22Mhz
+ /// @li <b>11</b> - 16.5Mhz
+ ///
+ UINT8 WriteSpeed; ///< WriteSpeed - Spi Write Speed
+ /// @par
+ /// WriteSpeed [1.0] - the clock speed for Spi write command
+ /// @li <b>00</b> - 66Mhz
+ /// @li <b>01</b> - 33Mhz
+ /// @li <b>10</b> - 22Mhz
+ /// @li <b>11</b> - 16.5Mhz
+ ///
+ UINT8 SpiMode; ///< SpiMode - Spi Mode Setting
+ /// @par
+ /// @li <b>101</b> - Qual-io 1-4-4
+ /// @li <b>100</b> - Dual-io 1-2-2
+ /// @li <b>011</b> - Qual-io 1-1-4
+ /// @li <b>010</b> - Dual-io 1-1-2
+ /// @li <b>111</b> - FastRead
+ /// @li <b>110</b> - Normal
+ ///
+ UINT8 AutoMode; ///< AutoMode - Spi Auto Mode
+ /// @par
+ /// SPI Auto Mode
+ /// @li <b>0</b> - Disabled
+ /// @li <b>1</b> - Enabled
+ ///
+ UINT8 SpiBurstWrite; ///< SpiBurstWrite - Spi Burst Write Mode
+ /// @par
+ /// SPI Burst Write
+ /// @li <b>0</b> - Disabled
+ /// @li <b>1</b> - Enabled
+ BOOLEAN LpcClk0; ///< Lclk0En - LPCCLK0
+ /// @par
+ /// LPC Clock 0 mode
+ /// @li <b>0</b> - forced to stop
+ /// @li <b>1</b> - functioning with CLKRUN protocol
+ BOOLEAN LpcClk1; ///< Lclk1En - LPCCLK1
+ /// @par
+ /// LPC Clock 1 mode
+ /// @li <b>0</b> - forced to stop
+ /// @li <b>1</b> - functioning with CLKRUN protocol
+// UINT32 SPI100_RX_Timing_Config_Register_38; ///< SPI100_RX_Timing_Config_Register_38
+// UINT16 SPI100_RX_Timing_Config_Register_3C; ///< SPI100_RX_Timing_Config_Register_3C
+// UINT8 SpiProtectEn0_1d_34; ///
+ UINT8 SPI100_Enable; ///< Spi 100 Enable
+ SPI_DEVICE_PROFILE SpiDeviceProfile; ///< Spi Device Profile
+} FCH_SPI;
+
+
+///
+/// IDE structure
+///
+typedef struct {
+ BOOLEAN IdeEnable; ///< IDE function switch
+ BOOLEAN IdeMsiEnable; ///< IDE MSI capability
+ UINT32 IdeSsid; ///< IDE controller Subsystem ID
+} FCH_IDE;
+
+///
+/// IR Structure
+///
+typedef struct {
+ IR_CONFIG IrConfig; ///< IrConfig
+ UINT8 IrPinControl; ///< IrPinControl
+} FCH_IR;
+
+
+///
+/// PCI Bridge Structure
+///
+typedef struct {
+ BOOLEAN PcibMsiEnable; ///< PCI-PCI Bridge MSI capability
+ UINT32 PcibSsid; ///< PCI-PCI Bridge Subsystem ID
+ UINT8 PciClks; ///< 33MHz PCICLK0/1/2/3 Enable, bits [0:3] used
+ /// @li <b>0</b> - disable
+ /// @li <b>1</b> - enable
+ ///
+ UINT16 PcibClkStopOverride; ///< PCIB_CLK_Stop Override
+ BOOLEAN PcibClockRun; ///< Enable the auto clkrun functionality
+ /// @li <b>0</b> - disable
+ /// @li <b>1</b> - enable
+ ///
+} FCH_PCIB;
+
+
+///
+/// - SATA Phy setting structure
+///
+typedef struct _SATA_PHY_SETTING {
+ UINT16 PhyCoreControlWord; /// PhyCoreControlWord - Reserved
+ UINT32 PhyFineTuneDword; /// PhyFineTuneDword - Reserved
+} SATA_PHY_SETTING;
+
+///
+/// SATA main setting structure
+///
+typedef struct _SATA_ST {
+ UINT8 SataModeReg; ///< SataModeReg - Sata Controller Mode
+ BOOLEAN SataEnable; ///< SataEnable - Sata Controller Function
+ /// @par
+ /// Sata Controller
+ /// @li <b>0</b> - disable
+ /// @li <b>1</b> - enable
+ ///
+ UINT8 Sata6AhciCap; ///< Sata6AhciCap - Reserved */
+ BOOLEAN SataSetMaxGen2; ///< SataSetMaxGen2 - Set Sata Max Gen2 mode
+ /// @par
+ /// Sata Controller Set to Max Gen2 mode
+ /// @li <b>0</b> - disable
+ /// @li <b>1</b> - enable
+ ///
+ BOOLEAN IdeEnable; ///< IdeEnable - Hidden IDE
+ /// @par
+ /// Sata IDE Controller Combined Mode
+ /// Enable - SATA controller has control over Port0 through Port3,
+ /// IDE controller has control over Port4 and Port7.
+ /// Disable - SATA controller has full control of all 8 Ports
+ /// when operating in non-IDE mode.
+ /// @li <b>0</b> - enable
+ /// @li <b>1</b> - disable
+ ///
+ UINT8 SataClkMode; /// SataClkMode - Reserved
+} SATA_ST;
+
+///
+/// SATA_PORT_ST - SATA PORT structure
+///
+typedef struct _SATA_PORT_ST {
+ UINT8 SataPortReg; ///< SATA Port bit map - bits[0:7] for ports 0 ~ 7
+ /// @li <b>0</b> - disable
+ /// @li <b>1</b> - enable
+ ///
+ BOOLEAN Port0; ///< PORT0 - 0:disable, 1:enable
+ BOOLEAN Port1; ///< PORT1 - 0:disable, 1:enable
+ BOOLEAN Port2; ///< PORT2 - 0:disable, 1:enable
+ BOOLEAN Port3; ///< PORT3 - 0:disable, 1:enable
+ BOOLEAN Port4; ///< PORT4 - 0:disable, 1:enable
+ BOOLEAN Port5; ///< PORT5 - 0:disable, 1:enable
+ BOOLEAN Port6; ///< PORT6 - 0:disable, 1:enable
+ BOOLEAN Port7; ///< PORT7 - 0:disable, 1:enable
+} SATA_PORT_ST;
+
+///
+///< _SATA_PORT_MD - Force Each PORT to GEN1/GEN2 mode
+///
+typedef struct _SATA_PORT_MD {
+ UINT16 SataPortMode; ///< SATA Port GEN1/GEN2 mode bit map - bits [0:15] for ports 0 ~ 7
+ UINT8 Port0; ///< PORT0 - set BIT0 to GEN1, BIT1 - PORT0 set to GEN2
+ UINT8 Port1; ///< PORT1 - set BIT2 to GEN1, BIT3 - PORT1 set to GEN2
+ UINT8 Port2; ///< PORT2 - set BIT4 to GEN1, BIT5 - PORT2 set to GEN2
+ UINT8 Port3; ///< PORT3 - set BIT6 to GEN1, BIT7 - PORT3 set to GEN2
+ UINT8 Port4; ///< PORT4 - set BIT8 to GEN1, BIT9 - PORT4 set to GEN2
+ UINT8 Port5; ///< PORT5 - set BIT10 to GEN1, BIT11 - PORT5 set to GEN2
+ UINT8 Port6; ///< PORT6 - set BIT12 to GEN1, BIT13 - PORT6 set to GEN2
+ UINT8 Port7; ///< PORT7 - set BIT14 to GEN1, BIT15 - PORT7 set to GEN2
+} SATA_PORT_MD;
+///
+/// SATA structure
+///
+typedef struct {
+ BOOLEAN SataMsiEnable; ///< SATA MSI capability
+ UINT32 SataIdeSsid; ///< SATA IDE mode SSID
+ UINT32 SataRaidSsid; ///< SATA RAID mode SSID
+ UINT32 SataRaid5Ssid; ///< SATA RAID 5 mode SSID
+ UINT32 SataAhciSsid; ///< SATA AHCI mode SSID
+
+ SATA_ST SataMode; /// SataMode - Reserved
+ SATA_CLASS SataClass; ///< SataClass - SATA Controller mode [2:0]
+ UINT8 SataIdeMode; ///< SataIdeMode - Sata IDE Controller mode
+ /// @par
+ /// @li <b>0</b> - Legacy IDE mode
+ /// @li <b>1</b> - Native IDE mode
+ ///
+ UINT8 SataDisUnusedIdePChannel; ///< SataDisUnusedIdePChannel-Disable Unused IDE Primary Channel
+ /// @par
+ /// @li <b>0</b> - Channel Enable
+ /// @li <b>1</b> - Channel Disable
+ ///
+ UINT8 SataDisUnusedIdeSChannel; ///< SataDisUnusedIdeSChannel - Disable Unused IDE Secondary Channel
+ /// @par
+ /// @li <b>0</b> - Channel Enable
+ /// @li <b>1</b> - Channel Disable
+ ///
+ UINT8 IdeDisUnusedIdePChannel; ///< IdeDisUnusedIdePChannel-Disable Unused IDE Primary Channel
+ /// @par
+ /// @li <b>0</b> - Channel Enable
+ /// @li <b>1</b> - Channel Disable
+ ///
+ UINT8 IdeDisUnusedIdeSChannel; ///< IdeDisUnusedIdeSChannel-Disable Unused IDE Secondary Channel
+ /// @par
+ /// @li <b>0</b> - Channel Enable
+ /// @li <b>1</b> - Channel Disable
+ ///
+ UINT8 SataOptionReserved; /// SataOptionReserved - Reserved
+
+ SATA_PORT_ST SataEspPort; ///< SataEspPort - SATA port is external accessible on a signal only connector (eSATA:)
+
+ SATA_PORT_ST SataPortPower; ///< SataPortPower - Port Power configuration
+
+ SATA_PORT_MD SataPortMd; ///< SataPortMd - Port Mode
+
+ UINT8 SataAggrLinkPmCap; /// SataAggrLinkPmCap - 0:OFF 1:ON
+ UINT8 SataPortMultCap; /// SataPortMultCap - 0:OFF 1:ON
+ UINT8 SataClkAutoOff; /// SataClkAutoOff - AutoClockOff 0:Disabled, 1:Enabled
+ UINT8 SataPscCap; /// SataPscCap 1:Enable PSC, 0:Disable PSC capability
+ UINT8 BiosOsHandOff; /// BiosOsHandOff - Reserved
+ UINT8 SataFisBasedSwitching; /// SataFisBasedSwitching - Reserved
+ UINT8 SataCccSupport; /// SataCccSupport - Reserved
+ UINT8 SataSscCap; /// SataSscCap - 1:Enable, 0:Disable SSC capability
+ UINT8 SataMsiCapability; /// SataMsiCapability 0:Hidden 1:Visible
+ UINT8 SataForceRaid; /// SataForceRaid 0:No function 1:Force RAID
+ UINT8 SataInternal100Spread; /// SataInternal100Spread - Reserved
+ UINT8 SataDebugDummy; /// SataDebugDummy - Reserved
+ UINT8 SataTargetSupport8Device; /// SataTargetSupport8Device - Reserved
+ UINT8 SataDisableGenericMode; /// SataDisableGenericMode - Reserved
+ BOOLEAN SataAhciEnclosureManagement; /// SataAhciEnclosureManagement - Reserved
+ UINT8 SataSgpio0; /// SataSgpio0 - Reserved
+ UINT8 SataSgpio1; /// SataSgpio1 - Reserved
+ UINT8 SataPhyPllShutDown; /// SataPhyPllShutDown - Reserved
+ BOOLEAN SataHotRemovalEnh; /// SataHotRemovalEnh - Reserved
+
+ SATA_PORT_ST SataHotRemovalEnhPort; ///< SataHotRemovalEnhPort - Hot Remove
+
+ BOOLEAN SataOobDetectionEnh; /// SataOobDetectionEnh - TRUE
+ BOOLEAN SataPowerSavingEnh; /// SataPowerSavingEnh - TRUE
+ UINT8 SataMemoryPowerSaving; /// SataMemoryPowerSaving - 0-3 Default [3]
+ BOOLEAN SataRasSupport; /// SataRasSupport - Support RAS function TRUE: Enable FALSE: Disable
+ BOOLEAN SataAhciDisPrefetchFunction; /// SataAhciDisPrefetchFunction - Disable AHCI Prefetch Function Support
+ BOOLEAN SataDevSlpPort0; /// SataDevSlpPort0 - Reserved
+ BOOLEAN SataDevSlpPort1; /// SataDevSlpPort1 - Reserved
+// UINT8 SataDevSlpPort0S5Pin; /// SataDevSlpPort0S5Pin - Reserved
+// UINT8 SataDevSlpPort1S5Pin; /// SataDevSlpPort1S5Pin - Reserved
+ UINT8 SataDbgTX_DRV_STR ; /// TX_DRV_STR - Reserved
+ UINT8 SataDbgTX_DE_EMPH_STR ; /// TX_DE_EMPH_STR - Reserved
+ UINT32 TempMmio; /// TempMmio - Reserved
+} FCH_SATA;
+
+
+//
+// IMC Message Register Software Interface
+//
+#define CPU_MISC_BUS_DEV_FUN ((0x18 << 3) + 3)
+
+#define MSG_SYS_TO_IMC 0x80
+#define Fun_80 0x80
+#define Fun_81 0x81
+#define Fun_82 0x82
+#define Fun_83 0x83
+#define Fun_84 0x84
+#define Fun_85 0x85
+#define Fun_86 0x86
+#define Fun_87 0x87
+#define Fun_88 0x88
+#define Fun_89 0x89
+#define Fun_90 0x90
+#define MSG_IMC_TO_SYS 0x81
+#define MSG_REG0 0x82
+#define MSG_REG1 0x83
+#define MSG_REG2 0x84
+#define MSG_REG3 0x85
+#define MSG_REG4 0x86
+#define MSG_REG5 0x87
+#define MSG_REG6 0x88
+#define MSG_REG7 0x89
+#define MSG_REG8 0x8A
+#define MSG_REG9 0x8B
+#define MSG_REGA 0x8C
+#define MSG_REGB 0x8D
+#define MSG_REGC 0x8E
+#define MSG_REGD 0x8F
+
+#define DISABLED 0
+#define ENABLED 1
+
+
+
+///
+/// EC structure
+///
+typedef struct _FCH_EC {
+ UINT8 MsgFun81Zone0MsgReg0; ///<Thermal zone
+ UINT8 MsgFun81Zone0MsgReg1; ///<Thermal zone
+ UINT8 MsgFun81Zone0MsgReg2; ///<Thermal zone control byte 1
+ UINT8 MsgFun81Zone0MsgReg3; ///<Thermal zone control byte 2
+ UINT8 MsgFun81Zone0MsgReg4; ///<Bit[3:0] - Thermal diode offset adjustment in degrees Celsius.
+ UINT8 MsgFun81Zone0MsgReg5; ///<Hysteresis information
+ UINT8 MsgFun81Zone0MsgReg6; ///<SMBUS Address for SMBUS based temperature sensor such as SB-TSI and ADM1032
+ UINT8 MsgFun81Zone0MsgReg7; ///<Bit[1:0]: 0 - 2, SMBUS bus number where the SMBUS based temperature sensor is located.
+ UINT8 MsgFun81Zone0MsgReg8; ///<Fan PWM stepping rate in unit of PWM level percentage
+ UINT8 MsgFun81Zone0MsgReg9; ///<Fan PWM ramping rate in 5ms unit
+//
+// EC LDN9 function 81 zone 1
+//
+ UINT8 MsgFun81Zone1MsgReg0; ///<Thermal zone
+ UINT8 MsgFun81Zone1MsgReg1; ///<Thermal zone
+ UINT8 MsgFun81Zone1MsgReg2; ///<Thermal zone control byte 1
+ UINT8 MsgFun81Zone1MsgReg3; ///<Thermal zone control byte 2
+ UINT8 MsgFun81Zone1MsgReg4; ///<Bit[3:0] - Thermal diode offset adjustment in degrees Celsius.
+ UINT8 MsgFun81Zone1MsgReg5; ///<Hysteresis information
+ UINT8 MsgFun81Zone1MsgReg6; ///<SMBUS Address for SMBUS based temperature sensor such as SB-TSI and ADM1032
+ UINT8 MsgFun81Zone1MsgReg7; ///<Bit[1:0]: 0 - 2, SMBUS bus number where the SMBUS based temperature sensor is located.
+ UINT8 MsgFun81Zone1MsgReg8; ///<Fan PWM stepping rate in unit of PWM level percentage
+ UINT8 MsgFun81Zone1MsgReg9; ///<Fan PWM ramping rate in 5ms unit
+//
+//EC LDN9 function 81 zone 2
+//
+ UINT8 MsgFun81Zone2MsgReg0; ///<Thermal zone
+ UINT8 MsgFun81Zone2MsgReg1; ///<Thermal zone
+ UINT8 MsgFun81Zone2MsgReg2; ///<Thermal zone control byte 1
+ UINT8 MsgFun81Zone2MsgReg3; ///<Thermal zone control byte 2
+ UINT8 MsgFun81Zone2MsgReg4; ///<Bit[3:0] - Thermal diode offset adjustment in degrees Celsius.
+ UINT8 MsgFun81Zone2MsgReg5; ///<Hysteresis information
+ UINT8 MsgFun81Zone2MsgReg6; ///<SMBUS Address for SMBUS based temperature sensor such as SB-TSI and ADM1032
+ UINT8 MsgFun81Zone2MsgReg7; ///<Bit[1:0]: 0 - 2, SMBUS bus number where the SMBUS based temperature sensor is located.
+ UINT8 MsgFun81Zone2MsgReg8; ///<Fan PWM stepping rate in unit of PWM level percentage
+ UINT8 MsgFun81Zone2MsgReg9; ///<Fan PWM ramping rate in 5ms unit
+//
+//EC LDN9 function 81 zone 3
+//
+ UINT8 MsgFun81Zone3MsgReg0; ///<Thermal zone
+ UINT8 MsgFun81Zone3MsgReg1; ///<Thermal zone
+ UINT8 MsgFun81Zone3MsgReg2; ///<Thermal zone control byte 1
+ UINT8 MsgFun81Zone3MsgReg3; ///<Thermal zone control byte 2
+ UINT8 MsgFun81Zone3MsgReg4; ///<Bit[3:0] - Thermal diode offset adjustment in degrees Celsius.
+ UINT8 MsgFun81Zone3MsgReg5; ///<Hysteresis information
+ UINT8 MsgFun81Zone3MsgReg6; ///<SMBUS Address for SMBUS based temperature sensor such as SB-TSI and ADM1032
+ UINT8 MsgFun81Zone3MsgReg7; ///<Bit[1:0]: 0 - 2, SMBUS bus number where the SMBUS based temperature sensor is located.
+ UINT8 MsgFun81Zone3MsgReg8; ///<Fan PWM stepping rate in unit of PWM level percentage
+ UINT8 MsgFun81Zone3MsgReg9; ///<Fan PWM ramping rate in 5ms unit
+//
+//EC LDN9 function 83 zone 0
+//
+ UINT8 MsgFun83Zone0MsgReg0; ///<Thermal zone
+ UINT8 MsgFun83Zone0MsgReg1; ///<Thermal zone
+ UINT8 MsgFun83Zone0MsgReg2; ///<_AC0
+ UINT8 MsgFun83Zone0MsgReg3; ///<_AC1
+ UINT8 MsgFun83Zone0MsgReg4; ///<_AC2
+ UINT8 MsgFun83Zone0MsgReg5; ///<_AC3
+ UINT8 MsgFun83Zone0MsgReg6; ///<_AC4
+ UINT8 MsgFun83Zone0MsgReg7; ///<_AC5
+ UINT8 MsgFun83Zone0MsgReg8; ///<_AC6
+ UINT8 MsgFun83Zone0MsgReg9; ///<_AC7
+ UINT8 MsgFun83Zone0MsgRegA; ///<_CRT
+ UINT8 MsgFun83Zone0MsgRegB; ///<_PSV
+//
+//EC LDN9 function 83 zone 1
+//
+ UINT8 MsgFun83Zone1MsgReg0; ///<Thermal zone
+ UINT8 MsgFun83Zone1MsgReg1; ///<Thermal zone
+ UINT8 MsgFun83Zone1MsgReg2; ///<_AC0
+ UINT8 MsgFun83Zone1MsgReg3; ///<_AC1
+ UINT8 MsgFun83Zone1MsgReg4; ///<_AC2
+ UINT8 MsgFun83Zone1MsgReg5; ///<_AC3
+ UINT8 MsgFun83Zone1MsgReg6; ///<_AC4
+ UINT8 MsgFun83Zone1MsgReg7; ///<_AC5
+ UINT8 MsgFun83Zone1MsgReg8; ///<_AC6
+ UINT8 MsgFun83Zone1MsgReg9; ///<_AC7
+ UINT8 MsgFun83Zone1MsgRegA; ///<_CRT
+ UINT8 MsgFun83Zone1MsgRegB; ///<_PSV
+//
+//EC LDN9 function 83 zone 2
+//
+ UINT8 MsgFun83Zone2MsgReg0; ///<Thermal zone
+ UINT8 MsgFun83Zone2MsgReg1; ///<Thermal zone
+ UINT8 MsgFun83Zone2MsgReg2; ///<_AC0
+ UINT8 MsgFun83Zone2MsgReg3; ///<_AC1
+ UINT8 MsgFun83Zone2MsgReg4; ///<_AC2
+ UINT8 MsgFun83Zone2MsgReg5; ///<_AC3
+ UINT8 MsgFun83Zone2MsgReg6; ///<_AC4
+ UINT8 MsgFun83Zone2MsgReg7; ///<_AC5
+ UINT8 MsgFun83Zone2MsgReg8; ///<_AC6
+ UINT8 MsgFun83Zone2MsgReg9; ///<_AC7
+ UINT8 MsgFun83Zone2MsgRegA; ///<_CRT
+ UINT8 MsgFun83Zone2MsgRegB; ///<_PSV
+//
+//EC LDN9 function 83 zone 3
+//
+ UINT8 MsgFun83Zone3MsgReg0; ///<Thermal zone
+ UINT8 MsgFun83Zone3MsgReg1; ///<Thermal zone
+ UINT8 MsgFun83Zone3MsgReg2; ///<_AC0
+ UINT8 MsgFun83Zone3MsgReg3; ///<_AC1
+ UINT8 MsgFun83Zone3MsgReg4; ///<_AC2
+ UINT8 MsgFun83Zone3MsgReg5; ///<_AC3
+ UINT8 MsgFun83Zone3MsgReg6; ///<_AC4
+ UINT8 MsgFun83Zone3MsgReg7; ///<_AC5
+ UINT8 MsgFun83Zone3MsgReg8; ///<_AC6
+ UINT8 MsgFun83Zone3MsgReg9; ///<_AC7
+ UINT8 MsgFun83Zone3MsgRegA; ///<_CRT
+ UINT8 MsgFun83Zone3MsgRegB; ///<_PSV
+//
+//EC LDN9 function 85 zone 0
+//
+ UINT8 MsgFun85Zone0MsgReg0; ///<Thermal zone
+ UINT8 MsgFun85Zone0MsgReg1; ///<Thermal zone
+ UINT8 MsgFun85Zone0MsgReg2; ///<AL0 PWM level in percentage (0 - 100%)
+ UINT8 MsgFun85Zone0MsgReg3; ///<AL1 PWM level in percentage (0 - 100%)
+ UINT8 MsgFun85Zone0MsgReg4; ///<AL2 PWM level in percentage (0 - 100%)
+ UINT8 MsgFun85Zone0MsgReg5; ///<AL3 PWM level in percentage (0 - 100%)
+ UINT8 MsgFun85Zone0MsgReg6; ///<AL4 PWM level in percentage (0 - 100%)
+ UINT8 MsgFun85Zone0MsgReg7; ///<AL5 PWM level in percentage (0 - 100%)
+ UINT8 MsgFun85Zone0MsgReg8; ///<AL6 PWM level in percentage (0 - 100%)
+ UINT8 MsgFun85Zone0MsgReg9; ///<AL7 PWM level in percentage (0 - 100%)
+//
+//EC LDN9 function 85 zone 1
+//
+ UINT8 MsgFun85Zone1MsgReg0; ///<Thermal zone
+ UINT8 MsgFun85Zone1MsgReg1; ///<Thermal zone
+ UINT8 MsgFun85Zone1MsgReg2; ///<AL0 PWM level in percentage (0 - 100%)
+ UINT8 MsgFun85Zone1MsgReg3; ///<AL1 PWM level in percentage (0 - 100%)
+ UINT8 MsgFun85Zone1MsgReg4; ///<AL2 PWM level in percentage (0 - 100%)
+ UINT8 MsgFun85Zone1MsgReg5; ///<AL3 PWM level in percentage (0 - 100%)
+ UINT8 MsgFun85Zone1MsgReg6; ///<AL4 PWM level in percentage (0 - 100%)
+ UINT8 MsgFun85Zone1MsgReg7; ///<AL5 PWM level in percentage (0 - 100%)
+ UINT8 MsgFun85Zone1MsgReg8; ///<AL6 PWM level in percentage (0 - 100%)
+ UINT8 MsgFun85Zone1MsgReg9; ///<AL7 PWM level in percentage (0 - 100%)
+//
+//EC LDN9 function 85 zone 2
+//
+ UINT8 MsgFun85Zone2MsgReg0; ///<Thermal zone
+ UINT8 MsgFun85Zone2MsgReg1; ///<Thermal zone
+ UINT8 MsgFun85Zone2MsgReg2; ///<AL0 PWM level in percentage (0 - 100%)
+ UINT8 MsgFun85Zone2MsgReg3; ///<AL1 PWM level in percentage (0 - 100%)
+ UINT8 MsgFun85Zone2MsgReg4; ///<AL2 PWM level in percentage (0 - 100%)
+ UINT8 MsgFun85Zone2MsgReg5; ///<AL3 PWM level in percentage (0 - 100%)
+ UINT8 MsgFun85Zone2MsgReg6; ///<AL4 PWM level in percentage (0 - 100%)
+ UINT8 MsgFun85Zone2MsgReg7; ///<AL5 PWM level in percentage (0 - 100%)
+ UINT8 MsgFun85Zone2MsgReg8; ///<AL6 PWM level in percentage (0 - 100%)
+ UINT8 MsgFun85Zone2MsgReg9; ///<AL7 PWM level in percentage (0 - 100%)
+//
+//EC LDN9 function 85 zone 3
+//
+ UINT8 MsgFun85Zone3MsgReg0; ///<Thermal zone
+ UINT8 MsgFun85Zone3MsgReg1; ///<Thermal zone
+ UINT8 MsgFun85Zone3MsgReg2; ///<AL0 PWM level in percentage (0 - 100%)
+ UINT8 MsgFun85Zone3MsgReg3; ///<AL1 PWM level in percentage (0 - 100%)
+ UINT8 MsgFun85Zone3MsgReg4; ///<AL2 PWM level in percentage (0 - 100%)
+ UINT8 MsgFun85Zone3MsgReg5; ///<AL3 PWM level in percentage (0 - 100%)
+ UINT8 MsgFun85Zone3MsgReg6; ///<AL4 PWM level in percentage (0 - 100%)
+ UINT8 MsgFun85Zone3MsgReg7; ///<AL5 PWM level in percentage (0 - 100%)
+ UINT8 MsgFun85Zone3MsgReg8; ///<AL6 PWM level in percentage (0 - 100%)
+ UINT8 MsgFun85Zone3MsgReg9; ///<AL7 PWM level in percentage (0 - 100%)
+//
+//EC LDN9 function 89 TEMPIN channel 0
+//
+ UINT8 MsgFun89Zone0MsgReg0; ///<Thermal zone
+ UINT8 MsgFun89Zone0MsgReg1; ///<Thermal zone
+ UINT8 MsgFun89Zone0MsgReg2; ///<At DWORD bit 0-7
+ UINT8 MsgFun89Zone0MsgReg3; ///<At DWORD bit 15-8
+ UINT8 MsgFun89Zone0MsgReg4; ///<At DWORD bit 23-16
+ UINT8 MsgFun89Zone0MsgReg5; ///<At DWORD bit 31-24
+ UINT8 MsgFun89Zone0MsgReg6; ///<Ct DWORD bit 0-7
+ UINT8 MsgFun89Zone0MsgReg7; ///<Ct DWORD bit 15-8
+ UINT8 MsgFun89Zone0MsgReg8; ///<Ct DWORD bit 23-16
+ UINT8 MsgFun89Zone0MsgReg9; ///<Ct DWORD bit 31-24
+ UINT8 MsgFun89Zone0MsgRegA; ///<Mode bit 0-7
+//
+//EC LDN9 function 89 TEMPIN channel 1
+//
+ UINT8 MsgFun89Zone1MsgReg0; ///<Thermal zone
+ UINT8 MsgFun89Zone1MsgReg1; ///<Thermal zone
+ UINT8 MsgFun89Zone1MsgReg2; ///<At DWORD bit 0-7
+ UINT8 MsgFun89Zone1MsgReg3; ///<At DWORD bit 15-8
+ UINT8 MsgFun89Zone1MsgReg4; ///<At DWORD bit 23-16
+ UINT8 MsgFun89Zone1MsgReg5; ///<At DWORD bit 31-24
+ UINT8 MsgFun89Zone1MsgReg6; ///<Ct DWORD bit 0-7
+ UINT8 MsgFun89Zone1MsgReg7; ///<Ct DWORD bit 15-8
+ UINT8 MsgFun89Zone1MsgReg8; ///<Ct DWORD bit 23-16
+ UINT8 MsgFun89Zone1MsgReg9; ///<Ct DWORD bit 31-24
+ UINT8 MsgFun89Zone1MsgRegA; ///<Mode bit 0-7
+//
+//EC LDN9 function 89 TEMPIN channel 2
+//
+ UINT8 MsgFun89Zone2MsgReg0; ///<Thermal zone
+ UINT8 MsgFun89Zone2MsgReg1; ///<Thermal zone
+ UINT8 MsgFun89Zone2MsgReg2; ///<At DWORD bit 0-7
+ UINT8 MsgFun89Zone2MsgReg3; ///<At DWORD bit 15-8
+ UINT8 MsgFun89Zone2MsgReg4; ///<At DWORD bit 23-16
+ UINT8 MsgFun89Zone2MsgReg5; ///<At DWORD bit 31-24
+ UINT8 MsgFun89Zone2MsgReg6; ///<Ct DWORD bit 0-7
+ UINT8 MsgFun89Zone2MsgReg7; ///<Ct DWORD bit 15-8
+ UINT8 MsgFun89Zone2MsgReg8; ///<Ct DWORD bit 23-16
+ UINT8 MsgFun89Zone2MsgReg9; ///<Ct DWORD bit 31-24
+ UINT8 MsgFun89Zone2MsgRegA; ///<Mode bit 0-7
+//
+//EC LDN9 function 89 TEMPIN channel 3
+//
+ UINT8 MsgFun89Zone3MsgReg0; ///<Thermal zone
+ UINT8 MsgFun89Zone3MsgReg1; ///<Thermal zone
+ UINT8 MsgFun89Zone3MsgReg2; ///<At DWORD bit 0-7
+ UINT8 MsgFun89Zone3MsgReg3; ///<At DWORD bit 15-8
+ UINT8 MsgFun89Zone3MsgReg4; ///<At DWORD bit 23-16
+ UINT8 MsgFun89Zone3MsgReg5; ///<At DWORD bit 31-24
+ UINT8 MsgFun89Zone3MsgReg6; ///<Ct DWORD bit 0-7
+ UINT8 MsgFun89Zone3MsgReg7; ///<Ct DWORD bit 15-8
+ UINT8 MsgFun89Zone3MsgReg8; ///<Ct DWORD bit 23-16
+ UINT8 MsgFun89Zone3MsgReg9; ///<Ct DWORD bit 31-24
+ UINT8 MsgFun89Zone3MsgRegA; ///<Mode bit 0-7
+//
+// FLAG for Fun83/85/89 support
+//
+ UINT16 IMCFUNSupportBitMap; ///< Bit0=81FunZone0 support(1=On;0=Off); bit1-3=81FunZone1-Zone3;Bit4-7=83FunZone0-Zone3;Bit8-11=85FunZone0-Zone3;Bit11-15=89FunZone0-Zone3;
+} FCH_EC;
+
+///
+/// IMC structure
+///
+typedef struct _FCH_IMC {
+ UINT8 ImcEnable; ///< ImcEnable - IMC Enable
+ UINT8 ImcEnabled; ///< ImcEnabled - IMC Enable
+ UINT8 ImcSureBootTimer; ///< ImcSureBootTimer - IMc SureBootTimer function
+ FCH_EC EcStruct; ///< EC structure
+ UINT8 ImcEnableOverWrite; ///< OverWrite IMC with the EC structure
+ /// @li <b>00</b> - by default strapping
+ /// @li <b>01</b> - enable
+ /// @li <b>10</b> - disable
+ ///
+} FCH_IMC;
+
+
+///
+/// Hpet structure
+///
+typedef struct {
+ BOOLEAN HpetEnable; ///< HPET function switch
+
+ BOOLEAN HpetMsiDis; ///< HpetMsiDis - South Bridge HPET MSI Configuration
+ /// @par
+ /// @li <b>1</b> - disable
+ /// @li <b>0</b> - enable
+
+ UINT32 HpetBase; ///< HpetBase
+ /// @par
+ /// HPET Base address
+} FCH_HPET;
+
+
+///
+/// GCPU related parameters
+///
+typedef struct {
+ UINT8 AcDcMsg; ///< Send a message to CPU to indicate the power mode (AC vs battery)
+ /// @li <b>1</b> - disable
+ /// @li <b>0</b> - enable
+
+ UINT8 TimerTickTrack; ///< Send a message to CPU to indicate the latest periodic timer interval
+ /// @li <b>1</b> - disable
+ /// @li <b>0</b> - enable
+
+ UINT8 ClockInterruptTag; ///< Mark the periodic timer interrupt
+ /// @li <b>1</b> - disable
+ /// @li <b>0</b> - enable
+
+ UINT8 OhciTrafficHanding; ///< Cause CPU to break out from C state when USB OHCI has pending traffic
+ /// @li <b>1</b> - disable
+ /// @li <b>0</b> - enable
+
+ UINT8 EhciTrafficHanding; ///< Cause CPU to break out from C state when USB EHCI has pending traffic
+ /// @li <b>1</b> - disable
+ /// @li <b>0</b> - enable
+
+ UINT8 GcpuMsgCMultiCore; ///< Track of CPU C state by monitoring each core's C state message
+ /// @li <b>1</b> - disable
+ /// @li <b>0</b> - enable
+
+ UINT8 GcpuMsgCStage; ///< Enable the FCH C state coordination logic
+ /// @li <b>1</b> - disable
+ /// @li <b>0</b> - enable
+} FCH_GCPU;
+
+
+///
+/// Timer
+///
+typedef struct {
+ BOOLEAN Enable; ///< Whether to register timer SMI in POST
+ BOOLEAN StartNow; ///< Whether to start the SMI immediately during registration
+ UINT16 CycleDuration; ///< [14:0] - Actual cycle duration = CycleDuration + 1
+} TIMER_SMI;
+
+///
+/// CS support
+///
+typedef struct {
+ BOOLEAN FchCsD3Cold; ///< FCH Cs D3 Cold function
+ BOOLEAN FchCsHwReduced; ///< FCH Cs hardware reduced ACPI flag
+ BOOLEAN FchCsPwrBtn; ///< FCH Cs Power Button function
+ BOOLEAN FchCsAcDc; ///< FCH Cs AcDc function
+ BOOLEAN AsfNfcEnable; ///< FCH Cs NFC function
+ UINT8 AsfNfcInterruptPin; ///< NFC Interrupt pin define
+ UINT8 AsfNfcRegPuPin; ///< NFC RegPu pin define
+ UINT8 AsfNfcWakePin; ///< NFC Wake Pin define
+ UINT8 PowerButtonGpe; ///< GPE# used by Power Button device
+ UINT8 AcDcTimerGpe; ///< GPE# used by Timer device
+} FCH_CS;
+
+
+///
+/// MISC structure
+///
+typedef struct {
+ BOOLEAN NativePcieSupport; /// PCIe NativePcieSupport - Debug function. 1:Enabled, 0:Disabled
+ BOOLEAN S3Resume; /// S3Resume - Flag of ACPI S3 Resume.
+ BOOLEAN RebootRequired; /// RebootRequired - Flag of Reboot system is required.
+ UINT8 FchVariant; /// FchVariant - FCH Variant value.
+ UINT8 Cg2Pll; ///< CG2 PLL - 0:disable, 1:enable
+ TIMER_SMI LongTimer; ///< Long Timer SMI
+ TIMER_SMI ShortTimer; ///< Short Timer SMI
+ UINT32 FchCpuId; ///< Saving CpuId for FCH Module.
+ BOOLEAN NoneSioKbcSupport; ///< NoneSioKbcSupport - No KBC/SIO controller ( Turn on Inchip KBC emulation function )
+ FCH_CS FchCsSupport; ///< FCH Cs function structure
+} FCH_MISC;
+
+
+///
+/// SMBus structure
+///
+typedef struct {
+ UINT32 SmbusSsid; ///< SMBUS controller Subsystem ID
+} FCH_SMBUS;
+
+
+///
+/// Acpi structure
+///
+typedef struct {
+ UINT16 Smbus0BaseAddress; ///< Smbus0BaseAddress
+ /// @par
+ /// Smbus BASE Address
+ ///
+ UINT16 Smbus1BaseAddress; ///< Smbus1BaseAddress
+ /// @par
+ /// Smbus1 (ASF) BASE Address
+ ///
+ UINT16 SioPmeBaseAddress; ///< SioPmeBaseAddress
+ /// @par
+ /// SIO PME BASE Address
+ ///
+ UINT32 WatchDogTimerBase; ///< WatchDogTimerBase
+ /// @par
+ /// Watch Dog Timer Address
+ ///
+ UINT16 AcpiPm1EvtBlkAddr; ///< AcpiPm1EvtBlkAddr
+ /// @par
+ /// ACPI PM1 event block Address
+ ///
+ UINT16 AcpiPm1CntBlkAddr; ///< AcpiPm1CntBlkAddr
+ /// @par
+ /// ACPI PM1 Control block Address
+ ///
+ UINT16 AcpiPmTmrBlkAddr; ///< AcpiPmTmrBlkAddr
+ /// @par
+ /// ACPI PM timer block Address
+ ///
+ UINT16 CpuControlBlkAddr; ///< CpuControlBlkAddr
+ /// @par
+ /// ACPI CPU control block Address
+ ///
+ UINT16 AcpiGpe0BlkAddr; ///< AcpiGpe0BlkAddr
+ /// @par
+ /// ACPI GPE0 block Address
+ ///
+ UINT16 SmiCmdPortAddr; ///< SmiCmdPortAddr
+ /// @par
+ /// SMI command port Address
+ ///
+ UINT16 AcpiPmaCntBlkAddr; ///< AcpiPmaCntBlkAddr
+ /// @par
+ /// ACPI PMA Control block Address
+ ///
+ BOOLEAN AnyHt200MhzLink; ///< AnyHt200MhzLink
+ /// @par
+ /// HT Link Speed on 200MHz option for each CPU specific LDTSTP# (Force enable)
+ ///
+ BOOLEAN SpreadSpectrum; ///< SpreadSpectrum
+ /// @par
+ /// Spread Spectrum function
+ /// @li <b>0</b> - disable
+ /// @li <b>1</b> - enable
+ ///
+ POWER_FAIL PwrFailShadow; ///< PwrFailShadow = PM_Reg: 5Bh [3:0]
+ /// @par
+ /// @li <b>00</b> - Always off
+ /// @li <b>01</b> - Always on
+ /// @li <b>11</b> - Use previous
+ ///
+ UINT8 StressResetMode; ///< StressResetMode 01-10
+ /// @li <b>00</b> - Disabed
+ /// @li <b>01</b> - Io Write 0x64 with 0xfe
+ /// @li <b>10</b> - Io Write 0xcf9 with 0x06
+ /// @li <b>11</b> - Io Write 0xcf9 with 0x0e
+ ///
+ BOOLEAN MtC1eEnable; /// MtC1eEnable - Enable MtC1e
+ VOID* OemProgrammingTablePtr; /// Pointer of ACPI OEM table
+ UINT8 SpreadSpectrumOptions; /// SpreadSpectrumOptions - Spread Spectrum Option
+ BOOLEAN PwrDownDisp2ClkPcieR; /// Power down DISP2_CLK and PCIE_RCLK_Output for power savings
+} FCH_ACPI;
+
+
+///
+/// HWM temp parameter structure
+///
+typedef struct _FCH_HWM_TEMP_PAR {
+ UINT16 At; ///< At
+ UINT16 Ct; ///< Ct
+ UINT8 Mode; ///< Mode BIT0:HiRatio BIT1:HiCurrent
+} FCH_HWM_TEMP_PAR;
+
+///
+/// HWM Current structure
+///
+typedef struct _FCH_HWM_CUR {
+ UINT16 FanSpeed[5]; ///< FanSpeed - fan Speed
+ UINT16 Temperature[5]; ///< Temperature - temperature
+ UINT16 Voltage[8]; ///< Voltage - voltage
+} FCH_HWM_CUR;
+
+///
+/// HWM fan control structure
+///
+typedef struct _FCH_HWM_FAN_CTR {
+ UINT8 InputControlReg00; /// Fan Input Control register, PM2 offset [0:4]0
+ UINT8 ControlReg01; /// Fan control register, PM2 offset [0:4]1
+ UINT8 FreqReg02; /// Fan frequency register, PM2 offset [0:4]2
+ UINT8 LowDutyReg03; /// Low Duty register, PM2 offset [0:4]3
+ UINT8 MedDutyReg04; /// Med Duty register, PM2 offset [0:4]4
+ UINT8 MultiplierReg05; /// Multiplier register, PM2 offset [0:4]5
+ UINT16 LowTempReg06; /// Low Temp register, PM2 offset [0:4]6
+ UINT16 MedTempReg08; /// Med Temp register, PM2 offset [0:4]8
+ UINT16 HighTempReg0A; /// High Temp register, PM2 offset [0:4]A
+ UINT8 LinearRangeReg0C; /// Linear Range register, PM2 offset [0:4]C
+ UINT8 LinearHoldCountReg0D; /// Linear Hold Count register, PM2 offset [0:4]D
+} FCH_HWM_FAN_CTR;
+
+///
+/// Hwm structure
+///
+typedef struct _FCH_HWM {
+ UINT8 HwMonitorEnable; ///< HwMonitorEnable
+ UINT32 HwmControl; ///< hwmControl
+ /// @par
+ /// HWM control configuration
+ /// @li <b>0</b> - HWM is Enabled
+ /// @li <b>1</b> - IMC is Enabled
+ ///
+ UINT8 FanSampleFreqDiv; ///< Sampling rate of Fan Speed
+ /// @li <b>00</b> - Base(22.5KHz)
+ /// @li <b>01</b> - Base(22.5KHz)/2
+ /// @li <b>10</b> - Base(22.5KHz)/4
+ /// @li <b>11</b> - Base(22.5KHz)/8
+ ///
+ UINT8 HwmFchtsiAutoPoll; ///< TSI Auto Polling
+ /// @li <b>0</b> - disable
+ /// @li <b>1</b> - enable
+ ///
+ UINT8 HwmFchtsiAutoPollStarted; ///< HwmSbtsiAutoPollStarted
+ UINT8 FanLinearEnhanceEn; ///< FanLinearEnhanceEn
+ UINT8 FanLinearHoldFix; ///< FanLinearHoldFix
+ UINT8 FanLinearRangeOutLimit; ///< FanLinearRangeOutLimit
+ UINT16 HwmCalibrationFactor; /// Calibration Factor
+ FCH_HWM_CUR HwmCurrent; /// HWM Current structure
+ FCH_HWM_CUR HwmCurrentRaw; /// HWM Current Raw structure
+ FCH_HWM_TEMP_PAR HwmTempPar[5]; /// HWM Temp parameter structure
+ FCH_HWM_FAN_CTR HwmFanControl[5]; /// HWM Fan Control structure
+ FCH_HWM_FAN_CTR HwmFanControlCooked[5]; /// HWM Fan Control structure
+} FCH_HWM;
+
+
+///
+/// Gec structure
+///
+typedef struct {
+ BOOLEAN GecEnable; ///< GecEnable - GEC function switch
+ UINT8 GecPhyStatus; /// GEC PHY Status
+ UINT8 GecPowerPolicy; /// GEC Power Policy
+ /// @li <b>00</b> - GEC is powered down in S3 and S5
+ /// @li <b>01</b> - GEC is powered down only in S5
+ /// @li <b>10</b> - GEC is powered down only in S3
+ /// @li <b>11</b> - GEC is never powered down
+ ///
+ UINT8 GecDebugBus; /// GEC Debug Bus
+ /// @li <b>0</b> - disable
+ /// @li <b>1</b> - enable
+ ///
+ UINT32 GecShadowRomBase; ///< GecShadowRomBase
+ /// @par
+ /// GEC (NIC) SHADOWROM BASE Address
+ ///
+ VOID *PtrDynamicGecRomAddress; /// Pointer of Dynamic GEC ROM Address
+} FCH_GEC;
+
+
+///
+/// _ABTblEntry - AB link register table R/W structure
+///
+typedef struct _AB_TBL_ENTRY {
+ UINT8 RegType; /// RegType : AB Register Type (ABCFG, AXCFG and so on)
+ UINT32 RegIndex; /// RegIndex : AB Register Index
+ UINT32 RegMask; /// RegMask : AB Register Mask
+ UINT32 RegData; /// RegData : AB Register Data
+} AB_TBL_ENTRY;
+
+///
+/// AB structure
+///
+typedef struct {
+ BOOLEAN AbMsiEnable; ///< ABlink MSI capability
+ UINT8 ALinkClkGateOff; /// Alink Clock Gate-Off function - 0:disable, 1:enable *KR
+ UINT8 BLinkClkGateOff; /// Blink Clock Gate-Off function - 0:disable, 1:enable *KR
+ UINT8 GppClockRequest0; /// GPP Clock Request.
+ UINT8 GppClockRequest1; /// GPP Clock Request.
+ UINT8 GppClockRequest2; /// GPP Clock Request.
+ UINT8 GppClockRequest3; /// GPP Clock Request.
+ UINT8 GfxClockRequest; /// GPP Clock Request.
+ UINT8 AbClockGating; /// AB Clock Gating - 0:disable, 1:enable *KR *CZ
+ UINT8 GppClockGating; /// GPP Clock Gating - 0:disable, 1:enable
+ UINT8 UmiL1TimerOverride; /// UMI L1 inactivity timer overwrite value
+ UINT8 UmiLinkWidth; /// UMI Link Width
+ UINT8 UmiDynamicSpeedChange; /// UMI Dynamic Speed Change - 0:disable, 1:enable
+ UINT8 PcieRefClockOverClocking; /// PCIe Ref Clock OverClocking value
+ UINT8 UmiGppTxDriverStrength; /// UMI GPP TX Driver Strength
+ BOOLEAN NbSbGen2; /// UMI link Gen2 - 0:Gen1, 1:Gen2
+ UINT8 PcieOrderRule; /// PCIe Order Rule - 0:disable, 1:enable *KR AB Posted Pass Non-Posted
+ UINT8 SlowSpeedAbLinkClock; /// Slow Speed AB Link Clock - 0:disable, 1:enable *KR
+ BOOLEAN ResetCpuOnSyncFlood; /// Reset Cpu On Sync Flood - 0:disable, 1:enable *KR
+ BOOLEAN AbDmaMemoryWrtie3264B; /// AB DMA Memory Write 32/64 BYTE Support *KR only
+ BOOLEAN AbMemoryPowerSaving; /// AB Memory Power Saving *KR *CZ
+ BOOLEAN SbgDmaMemoryWrtie3264ByteCount; /// SBG DMA Memory Write 32/64 BYTE Count Support *KR only
+ BOOLEAN SbgMemoryPowerSaving; /// SBG Memory Power Saving *KR *CZ
+ BOOLEAN SbgClockGating; /// SBG Clock Gate *CZ
+ BOOLEAN XdmaDmaWrite16ByteMode; /// XDMA DMA Write 16 byte mode *CZ
+ BOOLEAN XdmaMemoryPowerSaving; /// XDMA memory power saving *CZ
+ UINT8 XdmaPendingNprThreshold; /// XDMA PENDING NPR THRESHOLD *CZ
+ BOOLEAN XdmaDncplOrderDis; /// XDMA DNCPL ORDER DIS *CZ
+} FCH_AB;
+
+
+/**
+ * PCIE_CAP_ID - PCIe Cap ID
+ *
+ */
+#define PCIE_CAP_ID 0x10
+
+///
+/// FCH_GPP_PORT_CONFIG - Fch GPP port config structure
+///
+typedef struct {
+ BOOLEAN PortPresent; ///< Port connection
+ /// @par
+ /// @li <b>0</b> - Port doesn't have slot. No need to train the link
+ /// @li <b>1</b> - Port connection defined and needs to be trained
+ ///
+ BOOLEAN PortDetected; ///< Link training status
+ /// @par
+ /// @li <b>0</b> - EP not detected
+ /// @li <b>1</b> - EP detected
+ ///
+ BOOLEAN PortIsGen2; ///< Port link speed configuration
+ /// @par
+ /// @li <b>00</b> - Auto
+ /// @li <b>01</b> - Forced GEN1
+ /// @li <b>10</b> - Forced GEN2
+ /// @li <b>11</b> - Reserved
+ ///
+ BOOLEAN PortHotPlug; ///< Support hot plug?
+ /// @par
+ /// @li <b>0</b> - No support
+ /// @li <b>1</b> - support
+ ///
+ UINT8 PortMisc; /// PortMisc - Reserved
+} FCH_GPP_PORT_CONFIG;
+
+///
+/// GPP structure
+///
+typedef struct {
+ FCH_GPP_PORT_CONFIG PortCfg[4]; /// GPP port configuration structure
+ GPP_LINKMODE GppLinkConfig; ///< GppLinkConfig - PCIE_GPP_Enable[3:0]
+ /// @li <b>0000</b> - Port ABCD -> 4:0:0:0
+ /// @li <b>0010</b> - Port ABCD -> 2:2:0:0
+ /// @li <b>0011</b> - Port ABCD -> 2:1:1:0
+ /// @li <b>0100</b> - Port ABCD -> 1:1:1:1
+ ///
+ BOOLEAN GppFunctionEnable; ///< GPP Function - 0:disable, 1:enable
+ BOOLEAN GppToggleReset; ///< Toggle GPP core reset
+ UINT8 GppHotPlugGeventNum; ///< Hotplug GEVENT # - valid value 0-31
+ UINT8 GppFoundGfxDev; ///< Gpp Found Gfx Device
+ /// @li <b>0</b> - Not found
+ /// @li <b>1</b> - Found
+ ///
+ BOOLEAN GppGen2; ///< GPP Gen2 - 0:disable, 1:enable
+ UINT8 GppGen2Strap; ///< GPP Gen2 Strap - 0:disable, 1:enable, FCH itself uses this
+ BOOLEAN GppMemWrImprove; ///< GPP Memory Write Improve - 0:disable, 1:enable
+ BOOLEAN GppUnhidePorts; ///< GPP Unhide Ports - 0:disable, 1:enable
+ UINT8 GppPortAspm; ///< GppPortAspm - ASPM state for all GPP ports
+ /// @li <b>01</b> - Disabled
+ /// @li <b>01</b> - L0s
+ /// @li <b>10</b> - L1
+ /// @li <b>11</b> - L0s + L1
+ ///
+ BOOLEAN GppLaneReversal; ///< GPP Lane Reversal - 0:disable, 1:enable
+ BOOLEAN GppPhyPllPowerDown; ///< GPP PHY PLL Power Down - 0:disable, 1:enable
+ BOOLEAN GppDynamicPowerSaving; ///< GPP Dynamic Power Saving - 0:disable, 1:enable
+ BOOLEAN PcieAer; ///< PcieAer - Advanced Error Report: 0/1-disable/enable
+ BOOLEAN PcieRas; ///< PCIe RAS - 0:disable, 1:enable
+ BOOLEAN PcieCompliance; ///< PCIe Compliance - 0:disable, 1:enable
+ BOOLEAN PcieSoftwareDownGrade; ///< PCIe Software Down Grade
+ BOOLEAN UmiPhyPllPowerDown; ///< UMI PHY PLL Power Down - 0:disable, 1:enable
+ BOOLEAN SerialDebugBusEnable; ///< Serial Debug Bus Enable
+ UINT8 GppHardwareDownGrade; ///< GppHardwareDownGrade - Gpp HW Down Grade function 0:Disable, 1-4: portA-D
+ UINT8 GppL1ImmediateAck; ///< GppL1ImmediateAck - Gpp L1 Immediate ACK 0: enable, 1: disable
+ BOOLEAN NewGppAlgorithm; ///< NewGppAlgorithm - New GPP procedure
+ UINT8 HotPlugPortsStatus; ///< HotPlugPortsStatus - Save Hot-Plug Ports Status
+ UINT8 FailPortsStatus; ///< FailPortsStatus - Save Failure Ports Status
+ UINT8 GppPortMinPollingTime; ///< GppPortMinPollingTime - Min. Polling time for Gpp Port Training
+ BOOLEAN IsCapsuleMode; ///< IsCapsuleMode - Support Capsule Mode in FCH
+} FCH_GPP;
+
+
+///
+/// FCH USB3 Debug Sturcture
+///
+typedef struct {
+ BOOLEAN ServiceIntervalEnable; ///< Service Interval Enable
+ BOOLEAN BandwidthExpandEnable; ///< Bandwidth Expand Enable
+ BOOLEAN AoacEnable; ///< Aoac Enable
+ BOOLEAN HwLpmEnable; ///< HwLpm Enable
+ BOOLEAN DbcEnable; ///< DBC Enable
+ BOOLEAN MiscPlusEnable; ///< Misc Plus Enable
+ BOOLEAN EcoFixEnable; ///< Eco Fix Enable
+ BOOLEAN SsifEnable; ///< SSIF Enable
+ BOOLEAN U2ifEnable; ///< U2IF Enable
+ BOOLEAN FseEnable; ///< FSE Enable
+ BOOLEAN XhcPmeEnable; ///< Xhc Pme Enable
+} USB3_DEBUG;
+
+///
+/// FCH IoMux Sturcture
+///
+typedef struct {
+ UINT8 CbsDbgFchSmbusI2c2Egpio; ///< SMBUS/I2C_2/EGPIO_113_114
+ UINT8 CbsDbgFchAsfI2c3Egpio; ///< ASF/I2C_3/EGPIO_019_020
+} FCH_IOMUX;
+
+///
+/// FCH USB sturcture
+///
+typedef struct {
+ BOOLEAN Ohci1Enable; ///< OHCI1 controller enable
+ BOOLEAN Ohci2Enable; ///< OHCI2 controller enable
+ BOOLEAN Ohci3Enable; ///< OHCI3 controller enable
+ BOOLEAN Ohci4Enable; ///< OHCI4 controller enable
+ BOOLEAN Ehci1Enable; ///< EHCI1 controller enable
+ BOOLEAN Ehci2Enable; ///< EHCI2 controller enable
+ BOOLEAN Ehci3Enable; ///< EHCI3 controller enable
+ BOOLEAN Xhci0Enable; ///< XHCI0 controller enable
+ BOOLEAN Xhci1Enable; ///< XHCI1 controller enable
+ BOOLEAN UsbMsiEnable; ///< USB MSI capability
+ UINT32 OhciSsid; ///< OHCI SSID
+ UINT32 Ohci4Ssid; ///< OHCI 4 SSID
+ UINT32 EhciSsid; ///< EHCI SSID
+ UINT32 XhciSsid; ///< XHCI SSID
+ BOOLEAN UsbPhyPowerDown; ///< USB PHY Power Down - 0:disable, 1:enable
+ UINT32 UserDefineXhciRomAddr; ///< XHCI ROM address define by platform BIOS
+ UINT8 Ehci1Phy[5]; ///< EHCI1 USB PHY Driving Strength value table
+ UINT8 Ehci2Phy[5]; ///< EHCI2 USB PHY Driving Strength value table
+ UINT8 Ehci3Phy[4]; ///< EHCI3 USB PHY Driving Strength value table
+ UINT8 Xhci20Phy[4]; ///< XHCI USB 2.0 PHY Driving Strength value table
+ UINT8 Ehci1DebugPortSel; ///< DebugPortSel for Ehci1 Hub
+ /// @li <b>000</b> - Disable
+ /// @li <b>001</b> - HubDownStreamPort0
+ /// @li <b>010</b> - HubDownStreamPort1
+ /// @li <b>011</b> - HubDownStreamPort2
+ /// @li <b>100</b> - HubDownStreamPort3
+ UINT8 Ehci2DebugPortSel; ///< DebugPortSel for Ehci2 Hub
+ /// @li <b>000</b> - Disable
+ /// @li <b>001</b> - HubDownStreamPort0
+ /// @li <b>010</b> - HubDownStreamPort1
+ /// @li <b>011</b> - HubDownStreamPort2
+ /// @li <b>100</b> - HubDownStreamPort3
+ UINT8 Ehci3DebugPortSel; ///< DebugPortSel for Ehci3 Hub
+ /// @li <b>000</b> - Disable
+ /// @li <b>001</b> - HubDownStreamPort0
+ /// @li <b>010</b> - HubDownStreamPort1
+ /// @li <b>011</b> - HubDownStreamPort2
+ /// @li <b>100</b> - HubDownStreamPort3
+ UINT8 Ehci1NPort; ///< N_Port for Ehci1, 2 to 4
+ UINT8 Ehci2NPort; ///< N_Port for Ehci2, 2 to 4
+ USB3_DEBUG Usb3Debug; ///< Usb3 Debug Options
+ BOOLEAN EhciSimpleDebugPort; ///< Ehci Simple Debug Port
+ BOOLEAN UsbBatteryChargeEnable; ///< USB Battery Charge Enable
+ BOOLEAN ReduceUSB3PortToLastTwo; ///< Reduce USB3.0 ports to last 2
+ UINT8 USB30PortInit; ///< USB 3.0 Port Init
+} FCH_USB;
+
+
+/// Private: FCH_DATA_BLOCK_RESET
+typedef struct _FCH_RESET_DATA_BLOCK {
+ AMD_CONFIG_PARAMS *StdHeader; ///< Header structure
+ FCH_RESET_INTERFACE FchReset; ///< Reset interface
+
+ UINT8 FastSpeed; ///< SPI FastSpeed: 1-66MHz, 2-33MHz, 3-22MHz, 4-16.5MHz, 5-100Mhz
+ UINT8 WriteSpeed; ///< SPI Write Speed: 1-66MHz, 2-33MHz, 3-22MHz, 4-16.5MHz, 5-100Mhz
+ UINT8 Mode; ///< SPI Mode
+ /// @li <b>101</b> - Qual-io 1-4-4
+ /// @li <b>100</b> - Dual-io 1-2-2
+ /// @li <b>011</b> - Qual-io 1-1-4
+ /// @li <b>010</b> - Dual-io 1-1-2
+ /// @li <b>111</b> - FastRead
+ /// @li <b>110</b> - Normal
+ ///
+ UINT8 AutoMode; ///< SPI Auto Mode - 0:disable, 1:enable
+ UINT8 BurstWrite; ///< SPI Burst Write - 0:disable, 1:enable
+ BOOLEAN Sata6AhciCap; ///< SATA 6 AHCI Capability - TRUE:enable, FALSE:disable
+ UINT8 Cg2Pll; ///< CG2 PLL - 0:disable, 1:enable
+ BOOLEAN EcKbd; ///< EC KBD - 0:disable, 1:enable
+ BOOLEAN LegacyFree; ///< Legacy Free - 0:disable, 1:enable
+ BOOLEAN SataSetMaxGen2; ///< SATA enable maximum GEN2
+ UINT8 SataClkMode; ///< SATA reference clock selector and divider
+ UINT8 SataModeReg; ///< Output: SATAConfig PMIO:0xDA
+ BOOLEAN SataInternal100Spread; ///< SATA internal 100MHz spread ON/OFF
+ UINT8 SpiSpeed; ///< SPI NormSpeed: 1-66MHz, 2-33MHz, 3-22MHz, 4-16.5MHz, 5-100Mhz
+// UINT32 SPI100_RX_Timing_Config_Register_38; ///< SPI100_RX_Timing_Config_Register_38
+// UINT16 SPI100_RX_Timing_Config_Register_3C; ///< SPI100_RX_Timing_Config_Register_3C
+// UINT8 SpiProtectEn0_1d_34; ///
+ UINT8 SPI100_Enable; ///
+ BOOLEAN EcChannel0; ///< Enable EC channel 0
+ FCH_GPP Gpp; ///< GPP subsystem
+ FCH_SPI Spi; ///< SPI subsystem
+ BOOLEAN QeEnabled; /// Quad Mode Enabled
+ BOOLEAN FchOscout1ClkContinous; ///< FCH OSCOUT1_CLK Continous
+ UINT8 LpcClockDriveStrength; ///< Lpc Clock Drive Strength
+ const VOID* EarlyOemGpioTable; /// Pointer of Early OEM GPIO table
+// VOID* OemSpiDeviceTable; /// Pointer of OEM Spi Device table
+} FCH_RESET_DATA_BLOCK;
+
+
+/// Private: FCH_DATA_BLOCK
+typedef struct _FCH_DATA_BLOCK {
+ AMD_CONFIG_PARAMS *StdHeader; ///< Header structure
+ FCH_RUNTIME FchRunTime; ///< FCH Run Time Parameters
+
+ FCH_ACPI HwAcpi; ///< ACPI structure
+ FCH_AB Ab; ///< AB structure
+ FCH_GPP Gpp; ///< GPP structure
+ FCH_USB Usb; ///< USB structure
+ FCH_SATA Sata; ///< SATA structure
+ FCH_SMBUS Smbus; ///< SMBus structure
+ FCH_IDE Ide; ///< IDE structure
+ FCH_AZALIA Azalia; ///< Azalia structure
+ FCH_SPI Spi; ///< SPI structure
+ FCH_PCIB Pcib; ///< PCIB structure
+ FCH_GEC Gec; ///< GEC structure
+ FCH_SD Sd; ///< SD structure
+ FCH_HWM Hwm; ///< Hardware Moniter structure
+ FCH_IR Ir; ///< IR structure
+ FCH_HPET Hpet; ///< HPET structure
+ FCH_GCPU Gcpu; ///< GCPU structure
+ FCH_IMC Imc; ///< IMC structure
+ FCH_MISC Misc; ///< MISC structure
+ FCH_IOMUX IoMux; ///< MISC structure
+ VOID* PostOemGpioTable; /// Pointer of Post OEM GPIO table
+} FCH_DATA_BLOCK;
+
+#pragma pack (pop)
+
+#endif
diff --git a/src/vendorcode/amd/pi/00660F01/Proc/Fch/Common/FchDef.h b/src/vendorcode/amd/pi/00660F01/Proc/Fch/Common/FchDef.h
new file mode 100644
index 0000000..d0063a4
--- /dev/null
+++ b/src/vendorcode/amd/pi/00660F01/Proc/Fch/Common/FchDef.h
@@ -0,0 +1,421 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * FCH routine definition
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: FCH
+ * @e \$Revision: 309090 $ @e \$Date: 2014-12-09 12:28:05 -0600 (Tue, 09 Dec 2014) $
+ *
+ */
+ /*****************************************************************************
+ *
+ * Copyright (c) 2008 - 2015, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ***************************************************************************/
+#ifndef _FCH_DEF_H_
+#define _FCH_DEF_H_
+
+
+UINT32 ReadAlink (IN UINT32 Index, IN AMD_CONFIG_PARAMS *StdHeader);
+VOID WriteAlink (IN UINT32 Index, IN UINT32 Data, IN AMD_CONFIG_PARAMS *StdHeader);
+VOID RwAlink (IN UINT32 Index, IN UINT32 AndMask, IN UINT32 OrMask, IN AMD_CONFIG_PARAMS *StdHeader);
+VOID ReadMem (IN UINT32 Address, IN UINT8 OpFlag, IN VOID *ValuePtr);
+VOID WriteMem (IN UINT32 Address, IN UINT8 OpFlag, IN VOID *ValuePtr);
+VOID RwMem (IN UINT32 Address, IN UINT8 OpFlag, IN UINT32 Mask, IN UINT32 Data);
+VOID ReadPci (IN UINT32 Address, IN UINT8 OpFlag, IN VOID *Value, IN AMD_CONFIG_PARAMS *StdHeader);
+VOID WritePci (IN UINT32 Address, IN UINT8 OpFlag, IN VOID *Value, IN AMD_CONFIG_PARAMS *StdHeader);
+VOID RwPci (IN UINT32 Address, IN UINT8 OpFlag, IN UINT32 Mask, IN UINT32 Data, IN AMD_CONFIG_PARAMS *StdHeader);
+VOID ProgramPciByteTable (IN REG8_MASK* pPciByteTable, IN UINT16 dwTableSize, IN AMD_CONFIG_PARAMS *StdHeader);
+VOID ProgramFchAcpiMmioTbl (IN ACPI_REG_WRITE *pAcpiTbl, IN AMD_CONFIG_PARAMS *StdHeader);
+VOID ProgramFchSciMapTbl (IN SCI_MAP_CONTROL *pSciMapTbl, IN FCH_RESET_DATA_BLOCK *FchResetDataBlock);
+VOID ProgramFchGpioTbl (IN GPIO_CONTROL *pGpioTbl);
+VOID ProgramFchSataPhyTbl (IN SATA_PHY_CONTROL *pSataPhyTbl, IN FCH_RESET_DATA_BLOCK *FchResetDataBlock);
+VOID GetChipSysMode (IN VOID *Value, IN AMD_CONFIG_PARAMS *StdHeader);
+BOOLEAN IsImcEnabled (IN AMD_CONFIG_PARAMS *StdHeader);
+VOID ReadPmio (IN UINT8 Address, IN UINT8 OpFlag, IN VOID *Value, IN AMD_CONFIG_PARAMS *StdHeader);
+VOID WritePmio (IN UINT8 Address, IN UINT8 OpFlag, IN VOID *Value, IN AMD_CONFIG_PARAMS *StdHeader);
+VOID RwPmio (IN UINT8 Address, IN UINT8 OpFlag, IN UINT32 AndMask, IN UINT32 OrMask, IN AMD_CONFIG_PARAMS *StdHeader);
+VOID ReadPmio2 (IN UINT8 Address, IN UINT8 OpFlag, IN VOID *Value, IN AMD_CONFIG_PARAMS *StdHeader);
+VOID WritePmio2 (IN UINT8 Address, IN UINT8 OpFlag, IN VOID *Value, IN AMD_CONFIG_PARAMS *StdHeader);
+VOID RwPmio2 (IN UINT8 Address, IN UINT8 OpFlag, IN UINT32 AndMask, IN UINT32 OrMask, IN AMD_CONFIG_PARAMS *StdHeader);
+VOID ReadBiosram (IN UINT8 Address, IN UINT8 OpFlag, IN VOID *Value, IN AMD_CONFIG_PARAMS *StdHeader);
+VOID WriteBiosram (IN UINT8 Address, IN UINT8 OpFlag, IN VOID *Value, IN AMD_CONFIG_PARAMS *StdHeader);
+VOID GetFchAcpiMmioBase (OUT UINT32 *AcpiMmioBase, IN AMD_CONFIG_PARAMS *StdHeader);
+VOID GetFchAcpiPmBase (OUT UINT16 *AcpiPmBase, IN AMD_CONFIG_PARAMS *StdHeader);
+UINT8 ReadFchSleepType (IN AMD_CONFIG_PARAMS *StdHeader);
+UINT8 ReadFchChipsetRevision (IN AMD_CONFIG_PARAMS *StdHeader);
+
+///
+/// Fch Ab Routines
+///
+/// Pei Phase
+///
+VOID FchInitResetAb (IN VOID* FchDataPtr);
+VOID FchProgramAbPowerOnReset (IN VOID* FchDataPtr);
+///
+/// Dxe Phase
+///
+VOID FchInitEnvAb (IN VOID* FchDataPtr);
+VOID FchInitEnvAbSpecial (IN VOID* FchDataPtr);
+VOID FchInitMidAb (IN VOID* FchDataPtr);
+VOID FchInitLateAb (IN VOID* FchDataPtr);
+///
+/// Other Public Routines
+///
+VOID FchInitEnvAbLinkInit (IN VOID* FchDataPtr);
+BOOLEAN IsUmiOneLaneGen1Mode (IN AMD_CONFIG_PARAMS *StdHeader);
+VOID FchAbLateProgram (IN VOID* FchDataPtr);
+
+///
+/// Fch Pcie Routines
+///
+///
+/// Dxe Phase
+///
+VOID ProgramPcieNativeMode (IN VOID* FchDataPtr);
+
+///
+/// Fch Gpp Routines
+///
+
+///
+/// Common Gpp Routines
+///
+VOID FchGppDynamicPowerSaving (IN FCH_GPP *FchGpp, IN AMD_CONFIG_PARAMS *StdHeader);
+
+///
+/// Fch Azalia Routines
+///
+/// Pei Phase
+///
+VOID FchInitResetAzalia (IN VOID *FchDataPtr);
+///
+/// Dxe Phase
+///
+VOID FchInitEnvAzalia (IN VOID *FchDataPtr);
+VOID FchInitMidAzalia (IN VOID *FchDataPtr);
+VOID FchInitLateAzalia (IN VOID *FchDataPtr);
+
+
+///
+/// Fch HwAcpi Routines
+///
+/// Pei Phase
+///
+VOID FchInitResetHwAcpiP (IN VOID *FchDataPtr);
+VOID FchInitResetHwAcpi (IN VOID *FchDataPtr);
+VOID ProgramFchHwAcpiResetP (IN VOID *FchDataPtr);
+///
+/// Dxe Phase
+///
+VOID FchInitEnvHwAcpiP (IN VOID *FchDataPtr);
+VOID FchInitEnvHwAcpi (IN VOID *FchDataPtr);
+VOID ProgramEnvPFchAcpiMmio (IN VOID *FchDataPtr);
+VOID ProgramFchEnvHwAcpiPciReg (IN VOID *FchDataPtr);
+VOID ProgramSpecificFchInitEnvAcpiMmio (IN VOID *FchDataPtr);
+VOID ProgramFchEnvSpreadSpectrum (IN VOID *FchDataPtr);
+VOID FchInitMidHwAcpi (IN VOID *FchDataPtr);
+VOID FchInitLateHwAcpi (IN VOID *FchDataPtr);
+
+///
+/// Other Public Routines
+///
+VOID HpetInit (IN VOID *FchDataPtr);
+VOID MtC1eEnable (IN VOID *FchDataPtr);
+VOID GcpuRelatedSetting (IN VOID *FchDataPtr);
+VOID StressResetModeLate (IN VOID *FchDataPtr);
+
+///
+/// Fch Hwm Routines
+///
+/// Pei Phase
+///
+VOID FchInitResetHwm (IN VOID* FchDataPtr);
+///
+/// Dxe Phase
+///
+VOID FchInitEnvHwm (IN VOID* FchDataPtr);
+VOID FchInitMidHwm (IN VOID* FchDataPtr);
+VOID FchInitLateHwm (IN VOID* FchDataPtr);
+///
+/// Other Public Routines
+///
+VOID HwmInitRegister (IN VOID* FchDataPtr);
+VOID FchECfancontrolservice (IN VOID* FchDataPtr);
+
+
+///
+/// Fch Imc Routines
+///
+/// Pei Phase
+///
+VOID FchInitResetImc (IN VOID *FchDataPtr);
+VOID FchInitResetEc (IN VOID *FchDataPtr);
+///
+/// Dxe Phase
+///
+VOID FchInitEnvImc (IN VOID *FchDataPtr);
+VOID FchInitMidImc (IN VOID *FchDataPtr);
+VOID FchInitLateImc (IN VOID *FchDataPtr);
+VOID FchInitEnvEc (IN VOID *FchDataPtr);
+VOID FchInitMidEc (IN VOID *FchDataPtr);
+VOID FchInitLateEc (IN VOID *FchDataPtr);
+///
+/// Other Public Routines
+///
+VOID EnterEcConfig (IN AMD_CONFIG_PARAMS *StdHeader);
+VOID ExitEcConfig (IN AMD_CONFIG_PARAMS *StdHeader);
+VOID ReadEc8 (IN UINT8 Address, IN UINT8* Value, IN AMD_CONFIG_PARAMS *StdHeader);
+VOID WriteEc8 (IN UINT8 Address, IN UINT8* Value, IN AMD_CONFIG_PARAMS *StdHeader);
+VOID RwEc8 (IN UINT8 Address, IN UINT8 AndMask, IN UINT8 OrMask, IN AMD_CONFIG_PARAMS *StdHeader);
+VOID WriteECmsg (IN UINT8 Address, IN UINT8 OpFlag, IN VOID* Value, IN AMD_CONFIG_PARAMS *StdHeader);
+VOID ReadECmsg (IN UINT8 Address, IN UINT8 OpFlag, OUT VOID* Value, IN AMD_CONFIG_PARAMS *StdHeader);
+VOID WaitForEcLDN9MailboxCmdAck (IN AMD_CONFIG_PARAMS *StdHeader);
+
+VOID ImcSleep (IN VOID *FchDataPtr);
+VOID ImcDisarmSurebootTimer (IN VOID *FchDataPtr);
+VOID ImcDisableSurebootTimer (IN VOID *FchDataPtr);
+VOID ImcWakeup (IN VOID *FchDataPtr);
+VOID ImcIdle (IN VOID *FchDataPtr);
+BOOLEAN ValidateImcFirmware (IN VOID *FchDataPtr);
+VOID SoftwareToggleImcStrapping (IN VOID *FchDataPtr);
+VOID ImcCrashReset (IN VOID *FchDataPtr);
+VOID SoftwareDisableImc (IN VOID *FchDataPtr);
+
+
+///
+/// Fch Ir Routines
+///
+/// Dxe Phase
+///
+VOID FchInitEnvIr (IN VOID* FchDataPtr);
+VOID FchInitMidIr (IN VOID* FchDataPtr);
+VOID FchInitLateIr (IN VOID* FchDataPtr);
+
+///
+/// Fch SATA Routines
+///
+/// Pei Phase
+///
+VOID FchInitResetSata (IN VOID *FchDataPtr);
+VOID FchInitResetSataProgram (IN VOID *FchDataPtr);
+///
+/// Dxe Phase
+///
+VOID FchInitMidSata (IN VOID *FchDataPtr);
+VOID FchInitEnvSata (IN VOID *FchDataPtr);
+VOID FchInitEnvProgramSataPciRegs (IN VOID *FchDataPtr);
+VOID FchInitMidProgramSataRegs (IN VOID *FchDataPtr);
+VOID FchInitLateProgramSataRegs (IN VOID *FchDataPtr);
+
+VOID FchInitLateSata (IN VOID *FchDataPtr);
+VOID FchInitEnvSataIde (IN VOID *FchDataPtr);
+VOID FchInitMidSataIde (IN VOID *FchDataPtr);
+VOID FchInitLateSataIde (IN VOID *FchDataPtr);
+VOID FchInitEnvSataAhci (IN VOID *FchDataPtr);
+VOID FchInitMidSataAhci (IN VOID *FchDataPtr);
+VOID FchInitLateSataAhci (IN VOID *FchDataPtr);
+VOID FchInitEnvSataRaid (IN VOID *FchDataPtr);
+VOID FchInitMidSataRaid (IN VOID *FchDataPtr);
+VOID FchInitLateSataRaid (IN VOID *FchDataPtr);
+VOID FchInitEnvSataIde2Ahci (IN VOID *FchDataPtr);
+VOID FchInitMidSataIde2Ahci (IN VOID *FchDataPtr);
+VOID FchInitLateSataIde2Ahci (IN VOID *FchDataPtr);
+
+VOID SataAhciSetDeviceNumMsi (IN VOID *FchDataPtr);
+VOID SataRaidSetDeviceNumMsi (IN VOID *FchDataPtr);
+VOID SataIde2AhciSetDeviceNumMsi (IN VOID *FchDataPtr);
+VOID SataSetIrqIntResource (IN VOID *FchDataPtr, IN AMD_CONFIG_PARAMS *StdHeader);
+VOID SataBar5setting (IN VOID *FchDataPtr, IN UINT32 *Bar5Ptr);
+VOID SataEnableWriteAccess (IN AMD_CONFIG_PARAMS *StdHeader);
+VOID SataDisableWriteAccess (IN AMD_CONFIG_PARAMS *StdHeader);
+VOID SataSetDeviceNumMsi (IN VOID *FchDataPtr);
+VOID FchSataSetDeviceNumMsi (IN VOID *FchDataPtr);
+VOID ShutdownUnconnectedSataPortClock (IN VOID *FchDataPtr, IN UINT32 Bar5);
+VOID FchShutdownUnconnectedSataPortClock (IN VOID *FchDataPtr, IN UINT32 Bar5);
+VOID SataDriveDetection (IN VOID *FchDataPtr, IN UINT32 *Bar5Ptr);
+VOID FchSataDriveDetection (IN VOID *FchDataPtr, IN UINT32 *Bar5Ptr);
+VOID SataBar5RegSet (IN VOID *FchDataPtr);
+VOID SataSetPortGenMode (IN VOID *FchDataPtr);
+VOID FchSataSetPortGenMode (IN VOID *FchDataPtr);
+VOID FchProgramSataPhy (IN VOID *FchDataPtr);
+VOID FchInitEnvSataRaidProgram (IN VOID *FchDataPtr);
+
+///
+/// FCH USB Controller Public Function
+///
+/// Pei Phase
+///
+VOID FchInitResetUsb (IN VOID *FchDataPtr);
+VOID FchInitResetEhci (IN VOID *FchDataPtr);
+VOID FchInitResetXhci (IN VOID *FchDataPtr);
+VOID FchInitResetXhciProgram (IN VOID *FchDataPtr);
+///
+/// Dxe Phase
+///
+VOID FchInitEnvUsb (IN VOID *FchDataPtr);
+VOID FchInitMidUsb (IN VOID *FchDataPtr);
+VOID FchInitLateUsb (IN VOID *FchDataPtr);
+VOID FchInitEnvUsbEhci (IN VOID *FchDataPtr);
+VOID FchInitMidUsbEhci (IN VOID *FchDataPtr);
+VOID FchInitLateUsbEhci (IN VOID *FchDataPtr);
+VOID FchEhciDebugPortService (IN VOID *FchDataPtr);
+VOID FchInitEnvUsbXhci (IN VOID *FchDataPtr);
+VOID FchInitMidUsbXhci (IN VOID *FchDataPtr);
+VOID FchInitLateUsbXhci (IN VOID *FchDataPtr);
+VOID FchInitMidUsbEhci1 (IN FCH_DATA_BLOCK *FchDataPtr);
+///
+/// Other Public Routines
+///
+VOID FchSetUsbEnableReg (IN FCH_DATA_BLOCK *FchDataPtr);
+VOID FchEhciInitAfterPciInit (IN UINT32 Value, IN FCH_DATA_BLOCK* FchDataPtr);
+VOID FchXhciInitBeforePciInit (IN FCH_DATA_BLOCK* FchDataPtr);
+VOID FchXhciInitIndirectReg (IN FCH_DATA_BLOCK* FchDataPtr);
+VOID FchInitLateUsbXhciProgram (IN VOID *FchDataPtr);
+VOID FchXhciPowerSavingProgram (IN FCH_DATA_BLOCK* FchDataPtr);
+VOID FchXhciUsbPhyCalibrated (IN FCH_DATA_BLOCK* FchDataPtr);
+UINT8 FchUsbCommonPhyCalibration (IN FCH_DATA_BLOCK* FchDataPtr);
+
+///
+/// Fch Sd Routines
+///
+VOID FchInitEnvSd (IN VOID *FchDataPtr);
+VOID FchInitMidSd (IN VOID *FchDataPtr);
+VOID FchInitLateSd (IN VOID *FchDataPtr);
+
+///
+/// Other Public Routines
+///
+
+VOID FchInitEnvSdProgram (IN VOID *FchDataPtr);
+
+///
+/// Fch Spi Routines
+///
+/// Pei Phase
+///
+VOID FchInitResetSpi (IN VOID *FchDataPtr);
+VOID FchInitResetLpc (IN VOID *FchDataPtr);
+VOID FchInitResetLpcProgram (IN VOID *FchDataPtr);
+///
+/// Dxe Phase
+///
+VOID FchInitEnvSpi (IN VOID *FchDataPtr);
+VOID FchInitMidSpi (IN VOID *FchDataPtr);
+VOID FchInitLateSpi (IN VOID *FchDataPtr);
+VOID FchInitEnvLpc (IN VOID *FchDataPtr);
+VOID FchInitMidLpc (IN VOID *FchDataPtr);
+VOID FchInitLateLpc (IN VOID *FchDataPtr);
+VOID FchInitEnvLpcProgram (IN VOID *FchDataPtr);
+///
+/// Other Public Routines
+///
+VOID FchSpiUnlock (IN VOID *FchDataPtr);
+VOID FchSpiLock (IN VOID *FchDataPtr);
+
+/*--------------------------- Documentation Pages ---------------------------*/
+VOID FchStall (IN UINT32 uSec, IN AMD_CONFIG_PARAMS *StdHeader);
+VOID CimFchStall (IN UINT32 uSec, IN AMD_CONFIG_PARAMS *StdHeader);
+VOID FchPciReset (IN AMD_CONFIG_PARAMS *StdHeader);
+VOID OutPort80 (IN UINT32 pcode, IN AMD_CONFIG_PARAMS *StdHeader);
+VOID OutPort1080 (IN UINT32 pcode, IN AMD_CONFIG_PARAMS *StdHeader);
+VOID GetEfuseStatus (IN VOID* Value, IN AMD_CONFIG_PARAMS *StdHeader);
+VOID TurnOffCG2 (OUT VOID);
+VOID BackUpCG2 (OUT VOID);
+VOID FchCopyMem (IN VOID* pDest, IN VOID* pSource, IN UINTN Length);
+VOID* GetRomSigPtr (IN UINTN* RomSigPtr, IN AMD_CONFIG_PARAMS *StdHeader);
+VOID RwXhciIndReg (IN UINT32 Index, IN UINT32 AndMask, IN UINT32 OrMask, IN AMD_CONFIG_PARAMS *StdHeader);
+VOID RwXhci0IndReg (IN UINT32 Index, IN UINT32 AndMask, IN UINT32 OrMask, IN AMD_CONFIG_PARAMS *StdHeader);
+VOID RwXhci1IndReg (IN UINT32 Index, IN UINT32 AndMask, IN UINT32 OrMask, IN AMD_CONFIG_PARAMS *StdHeader);
+VOID ReadXhci0Phy (IN UINT32 Port, IN UINT32 Address, IN UINT32 *Value, IN AMD_CONFIG_PARAMS *StdHeader);
+VOID ReadXhci1Phy (IN UINT32 Port, IN UINT32 Address, IN UINT32 *Value, IN AMD_CONFIG_PARAMS *StdHeader);
+VOID AcLossControl (IN UINT8 AcLossControlValue);
+VOID FchVgaInit (OUT VOID);
+VOID RecordFchConfigPtr (IN UINT32 FchConfigPtr);
+VOID ValidateFchVariant (IN VOID *FchDataPtr);
+VOID RecordSmiStatus (IN AMD_CONFIG_PARAMS *StdHeader);
+VOID ClearAllSmiStatus (IN AMD_CONFIG_PARAMS *StdHeader);
+BOOLEAN IsExternalClockMode (IN VOID *FchDataPtr);
+VOID SbSleepTrapControl (IN BOOLEAN SleepTrap);
+
+AGESA_STATUS
+FchSpiTransfer (
+ IN UINT8 PrefixCode,
+ IN UINT8 Opcode,
+ IN OUT UINT8 *DataPtr,
+ IN UINT8 *AddressPtr,
+ IN UINT8 Length,
+ IN BOOLEAN WriteFlag,
+ IN BOOLEAN AddressFlag,
+ IN BOOLEAN DataFlag,
+ IN BOOLEAN FinishedFlag
+ );
+
+BOOLEAN
+FchConfigureSpiDeviceDummyCycle (
+ IN UINT32 DeviceID,
+ IN UINT8 SpiMode
+ );
+
+UINT32
+FchReadSpiId (
+ IN BOOLEAN Flag
+ );
+
+BOOLEAN
+FchPlatformSpiQe (
+ IN VOID *FchDataPtr
+ );
+
+FCH_DATA_BLOCK*
+FchInitLoadDataBlock (
+ IN FCH_INTERFACE *FchInterface,
+ IN AMD_CONFIG_PARAMS *StdHeader
+ );
+
+FCH_DATA_BLOCK*
+FchInitEnvCreatePrivateData (
+ IN AMD_ENV_PARAMS *EnvParams
+ );
+
+FCH_RESET_DATA_BLOCK*
+FchInitResetLoadPrivateDefault (
+ IN AMD_RESET_PARAMS *ResetParams
+ );
+
+VOID
+RetrieveDataBlockFromInitReset (
+ IN FCH_DATA_BLOCK *FchParams
+ );
+
+
+#endif
+
diff --git a/src/vendorcode/amd/pi/00660F01/Proc/Fch/Common/FchLib.c b/src/vendorcode/amd/pi/00660F01/Proc/Fch/Common/FchLib.c
new file mode 100644
index 0000000..dfdab59
--- /dev/null
+++ b/src/vendorcode/amd/pi/00660F01/Proc/Fch/Common/FchLib.c
@@ -0,0 +1,672 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * FCH IO access common routine
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: FCH
+ * @e \$Revision: 309090 $ @e \$Date: 2014-12-09 12:28:05 -0600 (Tue, 09 Dec 2014) $
+ *
+ */
+ /*****************************************************************************
+ *
+ * Copyright (c) 2008 - 2015, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ***************************************************************************/
+#include "FchPlatform.h"
+#define FILECODE PROC_FCH_COMMON_FCHLIB_FILECODE
+
+/**< FchStall - Reserved */
+VOID
+FchStall (
+ IN UINT32 uSec,
+ IN AMD_CONFIG_PARAMS *StdHeader
+ )
+{
+ UINT16 timerAddr;
+ UINT32 startTime;
+ UINT32 elapsedTime;
+
+ LibAmdMemRead (AccessWidth16, (UINT64) (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG64), &timerAddr, StdHeader);
+ if ( timerAddr == 0 ) {
+ uSec = uSec / 2;
+ while ( uSec != 0 ) {
+ LibAmdIoRead (AccessWidth8, FCHOEM_IO_DELAY_PORT, (UINT8 *) (&startTime), StdHeader);
+ uSec--;
+ }
+ } else {
+ LibAmdIoRead (AccessWidth32, timerAddr, &startTime, StdHeader);
+ for ( ;; ) {
+ LibAmdIoRead (AccessWidth32, timerAddr, &elapsedTime, StdHeader);
+ if ( elapsedTime < startTime ) {
+ elapsedTime = elapsedTime + FCH_MAX_TIMER - startTime;
+ } else {
+ elapsedTime = elapsedTime - startTime;
+ }
+ if ( (elapsedTime * FCHOEM_ELAPSED_TIME_UNIT / FCHOEM_ELAPSED_TIME_DIVIDER) > uSec ) {
+ break;
+ }
+ }
+ }
+}
+
+/**< cimFchStall - Reserved */
+VOID
+CimFchStall (
+ IN UINT32 uSec,
+ IN AMD_CONFIG_PARAMS *StdHeader
+ )
+{
+ UINT16 timerAddr;
+ UINT32 startTime;
+ UINT32 elapsedTime;
+
+ LibAmdMemRead (AccessWidth16, (UINT64) (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG64), &timerAddr, StdHeader);
+ if ( timerAddr == 0 ) {
+ uSec = uSec / 2;
+ while ( uSec != 0 ) {
+ LibAmdIoRead (AccessWidth8, FCHOEM_IO_DELAY_PORT, (UINT8*)&elapsedTime, StdHeader);
+ uSec--;
+ }
+ } else {
+ LibAmdIoRead (AccessWidth32, timerAddr, &startTime, StdHeader);
+ for ( ;; ) {
+ LibAmdIoRead (AccessWidth32, timerAddr, &elapsedTime, StdHeader);
+ if ( elapsedTime < startTime ) {
+ elapsedTime = elapsedTime + FCH_MAX_TIMER - startTime;
+ } else {
+ elapsedTime = elapsedTime - startTime;
+ }
+ if ( (elapsedTime * FCHOEM_ELAPSED_TIME_UNIT / FCHOEM_ELAPSED_TIME_DIVIDER) > uSec ) {
+ break;
+ }
+ }
+ }
+}
+
+/**< FchReset - Reserved */
+VOID
+FchPciReset (
+ IN AMD_CONFIG_PARAMS *StdHeader
+ )
+{
+ UINT8 PciRstValue;
+
+ PciRstValue = 0x06;
+ LibAmdIoWrite (AccessWidth8, FCH_PCIRST_BASE_IO, &PciRstValue, StdHeader);
+}
+
+/**< outPort80 - Reserved */
+VOID
+OutPort80 (
+ IN UINT32 pcode,
+ IN AMD_CONFIG_PARAMS *StdHeader
+ )
+{
+ LibAmdIoWrite (AccessWidth8, FCHOEM_OUTPUT_DEBUG_PORT, &pcode, StdHeader);
+ return;
+}
+
+/**< outPort1080 - Reserved */
+VOID
+OutPort1080 (
+ IN UINT32 pcode,
+ IN AMD_CONFIG_PARAMS *StdHeader
+ )
+{
+ LibAmdIoWrite (AccessWidth32, 0x1080, &pcode, StdHeader);
+ return;
+}
+
+/**< FchCopyMem - Reserved */
+VOID
+FchCopyMem (
+ IN VOID* pDest,
+ IN VOID* pSource,
+ IN UINTN Length
+ )
+{
+ UINTN i;
+ UINT8 *Ptr;
+ UINT8 *Source;
+ Ptr = (UINT8*)pDest;
+ Source = (UINT8*)pSource;
+ for (i = 0; i < Length; i++) {
+ *Ptr = *Source;
+ Source++;
+ Ptr++;
+ }
+}
+
+/** GetRomSigPtr - Reserved **/
+VOID*
+GetRomSigPtr (
+ IN UINTN *RomSigPtr,
+ IN AMD_CONFIG_PARAMS *StdHeader
+ )
+{
+ UINT32 RomPtr;
+ UINT32 RomSig;
+ UINT16 MswAddr;
+
+ *RomSigPtr = 0;
+ MswAddr = 0xFF00;
+ do {
+ RomPtr = (MswAddr << 16) + FCH_ROMSIG_BASE_IO;
+ LibAmdMemRead (AccessWidth32, (UINT64) RomPtr, &RomSig, StdHeader);
+ if (RomSig == FCH_ROMSIG_SIGNATURE) {
+ *RomSigPtr = RomPtr;
+ break;
+ }
+ MswAddr >>= 1;
+ MswAddr |= BIT15;
+ } while (MswAddr != 0xFFF8);
+ return RomSigPtr;
+}
+
+/** RwXhciIndReg - Reserved **/
+VOID
+RwXhciIndReg (
+ IN UINT32 Index,
+ IN UINT32 AndMask,
+ IN UINT32 OrMask,
+ IN AMD_CONFIG_PARAMS *StdHeader
+ )
+{
+ UINT32 RevReg;
+ PCI_ADDR PciAddress;
+
+ PciAddress.AddressValue = (USB_XHCI_BUS_DEV_FUN << 12) + 0x48;
+ LibAmdPciWrite (AccessWidth32, PciAddress, &Index, StdHeader);
+ PciAddress.AddressValue = (USB_XHCI_BUS_DEV_FUN << 12) + 0x4C;
+ RevReg = ~AndMask;
+ LibAmdPciRMW (AccessWidth32, PciAddress, &OrMask, &RevReg, StdHeader);
+
+ PciAddress.AddressValue = (USB_XHCI1_BUS_DEV_FUN << 12) + 0x48;
+ LibAmdPciWrite (AccessWidth32, PciAddress, &Index, StdHeader);
+ PciAddress.AddressValue = (USB_XHCI1_BUS_DEV_FUN << 12) + 0x4C;
+ RevReg = ~AndMask;
+ LibAmdPciRMW (AccessWidth32, PciAddress, &OrMask, &RevReg, StdHeader);
+}
+
+/** RwXhci0IndReg - Reserved **/
+VOID
+RwXhci0IndReg (
+ IN UINT32 Index,
+ IN UINT32 AndMask,
+ IN UINT32 OrMask,
+ IN AMD_CONFIG_PARAMS *StdHeader
+ )
+{
+ UINT32 RevReg;
+ PCI_ADDR PciAddress;
+
+ PciAddress.AddressValue = (USB_XHCI_BUS_DEV_FUN << 12) + 0x48;
+ LibAmdPciWrite (AccessWidth32, PciAddress, &Index, StdHeader);
+ PciAddress.AddressValue = (USB_XHCI_BUS_DEV_FUN << 12) + 0x4C;
+ RevReg = ~AndMask;
+ LibAmdPciRMW (AccessWidth32, PciAddress, &OrMask, &RevReg, StdHeader);
+}
+
+/** RwXhci1IndReg - Reserved **/
+VOID
+RwXhci1IndReg (
+ IN UINT32 Index,
+ IN UINT32 AndMask,
+ IN UINT32 OrMask,
+ IN AMD_CONFIG_PARAMS *StdHeader
+ )
+{
+ UINT32 RevReg;
+ PCI_ADDR PciAddress;
+
+ PciAddress.AddressValue = (USB_XHCI1_BUS_DEV_FUN << 12) + 0x48;
+ LibAmdPciWrite (AccessWidth32, PciAddress, &Index, StdHeader);
+ PciAddress.AddressValue = (USB_XHCI1_BUS_DEV_FUN << 12) + 0x4C;
+ RevReg = ~AndMask;
+ LibAmdPciRMW (AccessWidth32, PciAddress, &OrMask, &RevReg, StdHeader);
+}
+
+/** ReadXhci0Phy - Reserved **/
+VOID
+ReadXhci0Phy (
+ IN UINT32 Port,
+ IN UINT32 Address,
+ IN UINT32 *Value,
+ IN AMD_CONFIG_PARAMS *StdHeader
+ )
+{
+ UINT32 RegIndex;
+ UINT32 RegValue;
+ PCI_ADDR PciAddress;
+
+ RwXhci0IndReg ( FCH_XHCI_IND60_REG00, 0xFFFFC000, (Port << 13) + BIT12 + Address, StdHeader);
+
+ RegIndex = FCH_XHCI_IND60_REG04;
+ PciAddress.AddressValue = (USB_XHCI_BUS_DEV_FUN << 12) + 0x48;
+ LibAmdPciWrite (AccessWidth32, PciAddress, &RegIndex, StdHeader);
+ PciAddress.AddressValue = (USB_XHCI_BUS_DEV_FUN << 12) + 0x4C;
+ LibAmdPciRead (AccessWidth32, PciAddress, &RegValue, StdHeader);
+
+ (*Value) = ( RegValue >> (Port * 8)) & 0x000000FF;
+}
+
+/** ReadXhci1Phy - Reserved **/
+VOID
+ReadXhci1Phy (
+ IN UINT32 Port,
+ IN UINT32 Address,
+ IN UINT32 *Value,
+ IN AMD_CONFIG_PARAMS *StdHeader
+ )
+{
+ UINT32 RegIndex;
+ UINT32 RegValue;
+ PCI_ADDR PciAddress;
+
+ RwXhci1IndReg ( FCH_XHCI_IND60_REG00, 0xFFFFC000, (Port << 13) + BIT12 + Address, StdHeader);
+
+ RegIndex = FCH_XHCI_IND60_REG04;
+ PciAddress.AddressValue = (USB_XHCI1_BUS_DEV_FUN << 12) + 0x48;
+ LibAmdPciWrite (AccessWidth32, PciAddress, &RegIndex, StdHeader);
+ PciAddress.AddressValue = (USB_XHCI1_BUS_DEV_FUN << 12) + 0x4C;
+ LibAmdPciRead (AccessWidth32, PciAddress, &RegValue, StdHeader);
+
+ (*Value) = ( RegValue >> (Port * 8)) & 0x000000FF;
+}
+
+/** AcLossControl - Reserved **/
+VOID
+AcLossControl (
+ IN UINT8 AcLossControlValue
+ )
+{
+ AcLossControlValue &= 0x03;
+ AcLossControlValue |= BIT2;
+ RwMem (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REG5B, AccessWidth8, 0xF0, AcLossControlValue);
+}
+
+/** RecordFchConfigPtr - Reserved **/
+VOID
+RecordFchConfigPtr (
+ IN UINT32 FchConfigPtr
+ )
+{
+ RwMem (ACPI_MMIO_BASE + CMOS_RAM_BASE + 0x08, AccessWidth8, 0, (UINT8) ((FchConfigPtr >> 0) & 0xFF) );
+ RwMem (ACPI_MMIO_BASE + CMOS_RAM_BASE + 0x09, AccessWidth8, 0, (UINT8) ((FchConfigPtr >> 8) & 0xFF) );
+ RwMem (ACPI_MMIO_BASE + CMOS_RAM_BASE + 0x0A, AccessWidth8, 0, (UINT8) ((FchConfigPtr >> 16) & 0xFF) );
+ RwMem (ACPI_MMIO_BASE + CMOS_RAM_BASE + 0x0B, AccessWidth8, 0, (UINT8) ((FchConfigPtr >> 24) & 0xFF) );
+}
+
+/** ReadAlink - Reserved **/
+UINT32
+ReadAlink (
+ IN UINT32 Index,
+ IN AMD_CONFIG_PARAMS *StdHeader
+ )
+{
+ UINT32 Data;
+ LibAmdIoWrite (AccessWidth32, ALINK_ACCESS_INDEX, &Index, StdHeader);
+ LibAmdIoRead (AccessWidth32, ALINK_ACCESS_DATA, &Data, StdHeader);
+ //Clear Index
+ Index = 0;
+ LibAmdIoWrite (AccessWidth32, ALINK_ACCESS_INDEX, &Index, StdHeader);
+ return Data;
+}
+
+/** WriteAlink - Reserved **/
+VOID
+WriteAlink (
+ IN UINT32 Index,
+ IN UINT32 Data,
+ IN AMD_CONFIG_PARAMS *StdHeader
+ )
+{
+ LibAmdIoWrite (AccessWidth32, ALINK_ACCESS_INDEX, &Index, StdHeader);
+ LibAmdIoWrite (AccessWidth32, ALINK_ACCESS_DATA, &Data, StdHeader);
+ //Clear Index
+ Index = 0;
+ LibAmdIoWrite (AccessWidth32, ALINK_ACCESS_INDEX, &Index, StdHeader);
+}
+
+/** RwAlink - Reserved **/
+VOID
+RwAlink (
+ IN UINT32 Index,
+ IN UINT32 AndMask,
+ IN UINT32 OrMask,
+ IN AMD_CONFIG_PARAMS *StdHeader
+ )
+{
+ UINT32 AccessType;
+
+ AccessType = Index & 0xE0000000;
+ if (AccessType == (AXINDC << 29)) {
+ WriteAlink ((FCH_AX_INDXC_REG30 | AccessType), Index & 0x1FFFFFFF, StdHeader);
+ Index = FCH_AX_DATAC_REG34 | AccessType;
+ } else if (AccessType == (AXINDP << 29)) {
+ WriteAlink ((FCH_AX_INDXP_REG38 | AccessType), Index & 0x1FFFFFFF, StdHeader);
+ Index = FCH_AX_DATAP_REG3C | AccessType;
+ }
+ WriteAlink (Index, (ReadAlink (Index, StdHeader) & AndMask) | OrMask, StdHeader);
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Read PMIO
+ *
+ *
+ *
+ * @param[in] Address - PMIO Offset value
+ * @param[in] OpFlag - Access sizes
+ * @param[in] Value - Read Data Buffer
+ * @param[in] StdHeader
+ *
+ */
+VOID
+ReadPmio (
+ IN UINT8 Address,
+ IN UINT8 OpFlag,
+ IN VOID *Value,
+ IN AMD_CONFIG_PARAMS *StdHeader
+ )
+{
+ UINT8 i;
+
+ OpFlag = OpFlag & 0x7f;
+ OpFlag = 1 << (OpFlag - 1);
+ for (i = 0; i < OpFlag; i++) {
+ LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REGCD6, &Address, StdHeader);
+ Address++;
+ LibAmdIoRead (AccessWidth8, FCH_IOMAP_REGCD7, (UINT8 *)Value + i, StdHeader);
+ }
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Write PMIO
+ *
+ *
+ *
+ * @param[in] Address - PMIO Offset value
+ * @param[in] OpFlag - Access sizes
+ * @param[in] Value - Write Data Buffer
+ * @param[in] StdHeader
+ *
+ */
+VOID
+WritePmio (
+ IN UINT8 Address,
+ IN UINT8 OpFlag,
+ IN VOID *Value,
+ IN AMD_CONFIG_PARAMS *StdHeader
+ )
+{
+ UINT8 i;
+
+ OpFlag = OpFlag & 0x7f;
+ OpFlag = 1 << (OpFlag - 1);
+ for (i = 0; i < OpFlag; i++) {
+ LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REGCD6, &Address, StdHeader);
+ Address++;
+ LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REGCD7, (UINT8 *)Value + i, StdHeader);
+ }
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * RwPmio - Read/Write PMIO
+ *
+ *
+ *
+ * @param[in] Address - PMIO Offset value
+ * @param[in] OpFlag - Access sizes
+ * @param[in] AndMask - Data And Mask 32 bits
+ * @param[in] OrMask - Data OR Mask 32 bits
+ * @param[in] StdHeader
+ *
+ */
+VOID
+RwPmio (
+ IN UINT8 Address,
+ IN UINT8 OpFlag,
+ IN UINT32 AndMask,
+ IN UINT32 OrMask,
+ IN AMD_CONFIG_PARAMS *StdHeader
+ )
+{
+ UINT32 Result;
+
+ ReadPmio (Address, OpFlag, &Result, StdHeader);
+ Result = (Result & AndMask) | OrMask;
+ WritePmio (Address, OpFlag, &Result, StdHeader);
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Read PMIO2
+ *
+ *
+ *
+ * @param[in] Address - PMIO2 Offset value
+ * @param[in] OpFlag - Access sizes
+ * @param[in] Value - Read Data Buffer
+ * @param[in] StdHeader
+ *
+ */
+VOID
+ReadPmio2 (
+ IN UINT8 Address,
+ IN UINT8 OpFlag,
+ IN VOID *Value,
+ IN AMD_CONFIG_PARAMS *StdHeader
+ )
+{
+ UINT8 i;
+
+ OpFlag = OpFlag & 0x7f;
+ OpFlag = 1 << (OpFlag - 1);
+ for ( i = 0; i < OpFlag; i++ ) {
+ LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REGCD0, &Address, StdHeader);
+ Address++;
+ LibAmdIoRead (AccessWidth8, FCH_IOMAP_REGCD1, (UINT8 *) Value + i, StdHeader);
+ }
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Write PMIO 2
+ *
+ *
+ *
+ * @param[in] Address - PMIO2 Offset value
+ * @param[in] OpFlag - Access sizes
+ * @param[in] Value - Write Data Buffer
+ * @param[in] StdHeader
+ *
+ */
+VOID
+WritePmio2 (
+ IN UINT8 Address,
+ IN UINT8 OpFlag,
+ IN VOID *Value,
+ IN AMD_CONFIG_PARAMS *StdHeader
+ )
+{
+ UINT8 i;
+
+ OpFlag = OpFlag & 0x7f;
+ OpFlag = 1 << (OpFlag - 1);
+
+ for ( i = 0; i < OpFlag; i++ ) {
+ LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REGCD0, &Address, StdHeader);
+ Address++;
+ LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REGCD1, (UINT8 *) Value + i, StdHeader);
+ }
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * RwPmio2 - Read/Write PMIO2
+ *
+ *
+ *
+ * @param[in] Address - PMIO2 Offset value
+ * @param[in] OpFlag - Access sizes
+ * @param[in] AndMask - Data And Mask 32 bits
+ * @param[in] OrMask - Data OR Mask 32 bits
+ * @param[in] StdHeader
+ *
+ */
+VOID
+RwPmio2 (
+ IN UINT8 Address,
+ IN UINT8 OpFlag,
+ IN UINT32 AndMask,
+ IN UINT32 OrMask,
+ IN AMD_CONFIG_PARAMS *StdHeader
+ )
+{
+ UINT32 Result;
+
+ ReadPmio2 (Address, OpFlag, &Result, StdHeader);
+ Result = (Result & AndMask) | OrMask;
+ WritePmio2 (Address, OpFlag, &Result, StdHeader);
+}
+
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Read BIOSRAM
+ *
+ *
+ *
+ * @param[in] Address - BIOSRAM Offset value
+ * @param[in] OpFlag - Access sizes
+ * @param[in] Value - Read Data Buffer
+ * @param[in] StdHeader
+ *
+ */
+VOID
+ReadBiosram (
+ IN UINT8 Address,
+ IN UINT8 OpFlag,
+ IN VOID *Value,
+ IN AMD_CONFIG_PARAMS *StdHeader
+ )
+{
+ UINT8 i;
+
+ OpFlag = OpFlag & 0x7f;
+ OpFlag = 1 << (OpFlag - 1);
+ for (i = 0; i < OpFlag; i++) {
+ LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REGCD4, &Address, StdHeader);
+ Address++;
+ LibAmdIoRead (AccessWidth8, FCH_IOMAP_REGCD5, (UINT8 *)Value + i, StdHeader);
+ }
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Write BIOSRAM
+ *
+ *
+ *
+ * @param[in] Address - BIOSRAM Offset value
+ * @param[in] OpFlag - Access sizes
+ * @param[in] Value - Write Data Buffer
+ * @param[in] StdHeader
+ *
+ */
+VOID
+WriteBiosram (
+ IN UINT8 Address,
+ IN UINT8 OpFlag,
+ IN VOID *Value,
+ IN AMD_CONFIG_PARAMS *StdHeader
+ )
+{
+ UINT8 i;
+
+ OpFlag = OpFlag & 0x7f;
+ OpFlag = 1 << (OpFlag - 1);
+ for (i = 0; i < OpFlag; i++) {
+ LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REGCD4, &Address, StdHeader);
+ Address++;
+ LibAmdIoWrite (AccessWidth8, FCH_IOMAP_REGCD5, (UINT8 *)Value + i, StdHeader);
+ }
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Record SMI Status
+ *
+ *
+ * @param[in] StdHeader
+ *
+ */
+VOID
+RecordSmiStatus (
+ IN AMD_CONFIG_PARAMS *StdHeader
+ )
+{
+ UINTN Index;
+ UINT8 SwSmiValue;
+
+ ACPIMMIO8 (0xfed80320) |= 0x01;
+ for ( Index = 0; Index < 20; Index++ ) {
+ ACPIMMIO8 (0xfed10020 + Index) = ACPIMMIO8 (0xfed80280 + Index);
+ }
+ LibAmdIoRead (AccessWidth8, 0xB0, &SwSmiValue, StdHeader);
+ ACPIMMIO8 (0xfed10040) = SwSmiValue;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Clear All SMI Status
+ *
+ *
+ * @param[in] StdHeader
+ *
+ */
+VOID
+ClearAllSmiStatus (
+ IN AMD_CONFIG_PARAMS *StdHeader
+ )
+{
+ UINTN Index;
+
+ for ( Index = 0; Index < 20; Index++ ) {
+ ACPIMMIO8 (0xfed80280 + Index) |= 0;
+ }
+}
diff --git a/src/vendorcode/amd/pi/00660F01/Proc/Fch/Common/FchPeLib.c b/src/vendorcode/amd/pi/00660F01/Proc/Fch/Common/FchPeLib.c
new file mode 100644
index 0000000..171ea0f
--- /dev/null
+++ b/src/vendorcode/amd/pi/00660F01/Proc/Fch/Common/FchPeLib.c
@@ -0,0 +1,310 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * FCH IO access common routine
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: FCH
+ * @e \$Revision: 309090 $ @e \$Date: 2014-12-09 12:28:05 -0600 (Tue, 09 Dec 2014) $
+ *
+ */
+ /*****************************************************************************
+ *
+ * Copyright (c) 2008 - 2015, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ***************************************************************************/
+#include "FchPlatform.h"
+#define FILECODE PROC_FCH_COMMON_FCHPELIB_FILECODE
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * ProgramPciByteTable - Program PCI register by table (8 bits data)
+ *
+ *
+ *
+ * @param[in] pPciByteTable - Table data pointer
+ * @param[in] dwTableSize - Table length
+ * @param[in] StdHeader
+ *
+ */
+VOID
+ProgramPciByteTable (
+ IN REG8_MASK *pPciByteTable,
+ IN UINT16 dwTableSize,
+ IN AMD_CONFIG_PARAMS *StdHeader
+ )
+{
+ UINT8 i;
+ UINT8 dbBusNo;
+ UINT8 dbDevFnNo;
+ UINT8 Or8;
+ UINT8 Mask8;
+ PCI_ADDR PciAddress;
+
+ dbBusNo = pPciByteTable->RegIndex;
+ dbDevFnNo = pPciByteTable->AndMask;
+ pPciByteTable++;
+
+ for ( i = 1; i < dwTableSize; i++ ) {
+ if ( (pPciByteTable->RegIndex == 0xFF) && (pPciByteTable->AndMask == 0xFF) && (pPciByteTable->OrMask == 0xFF) ) {
+ pPciByteTable++;
+ dbBusNo = pPciByteTable->RegIndex;
+ dbDevFnNo = pPciByteTable->AndMask;
+ pPciByteTable++;
+ i++;
+ } else {
+ PciAddress.AddressValue = (dbBusNo << 20) + (dbDevFnNo << 12) + pPciByteTable->RegIndex;
+ Or8 = pPciByteTable->OrMask;
+ Mask8 = ~pPciByteTable->AndMask;
+ LibAmdPciRMW (AccessWidth8, PciAddress, &Or8, &Mask8, StdHeader);
+ pPciByteTable++;
+ }
+ }
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * ProgramFchAcpiMmioTbl - Program FCH ACPI MMIO register by table (8 bits data)
+ *
+ *
+ *
+ * @param[in] pAcpiTbl - Table data pointer
+ * @param[in] StdHeader
+ *
+ */
+VOID
+ProgramFchAcpiMmioTbl (
+ IN ACPI_REG_WRITE *pAcpiTbl,
+ IN AMD_CONFIG_PARAMS *StdHeader
+ )
+{
+ UINT8 i;
+ UINT8 Or8;
+ UINT8 Mask8;
+ UINT32 ddtempVar;
+
+ if (pAcpiTbl != NULL) {
+ if ((pAcpiTbl->MmioReg == 0) && (pAcpiTbl->MmioBase == 0) && (pAcpiTbl->DataAndMask == 0xB0) && (pAcpiTbl->DataOrMask == 0xAC)) {
+ // Signature Checking
+ pAcpiTbl++;
+ for ( i = 1; pAcpiTbl->MmioBase < 0x1D; i++ ) {
+ ddtempVar = ACPI_MMIO_BASE | (pAcpiTbl->MmioBase) << 8 | pAcpiTbl->MmioReg;
+ Or8 = pAcpiTbl->DataOrMask;
+ Mask8 = ~pAcpiTbl->DataAndMask;
+ LibAmdMemRMW (AccessWidth8, (UINT64) ddtempVar, &Or8, &Mask8, StdHeader);
+ pAcpiTbl++;
+ }
+ }
+ }
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * ProgramFchSciMapTbl - Program FCH SCI Map table (8 bits data)
+ *
+ *
+ *
+ * @param[in] pSciMapTbl - Table data pointer
+ * @param[in] FchResetDataBlock
+ *
+ */
+VOID
+ProgramFchSciMapTbl (
+ IN SCI_MAP_CONTROL *pSciMapTbl,
+ IN FCH_RESET_DATA_BLOCK *FchResetDataBlock
+ )
+{
+ AMD_CONFIG_PARAMS *StdHeader;
+
+ UINT32 ddtempVar;
+ StdHeader = FchResetDataBlock->StdHeader;
+
+ if (pSciMapTbl != NULL) {
+ while (pSciMapTbl->InputPin != 0xFF) {
+ if ((pSciMapTbl->InputPin >= 0x40) && (pSciMapTbl->InputPin < 0x80) && (pSciMapTbl->GpeMap < 0x20)) {
+ ddtempVar = ACPI_MMIO_BASE | SMI_BASE | pSciMapTbl->InputPin;
+ if (((pSciMapTbl->InputPin == FCH_SMI_xHC0Pme) && (FchResetDataBlock->FchReset.Xhci0Enable == 0)) || \
+ ((pSciMapTbl->InputPin == FCH_SMI_xHC1Pme) && (FchResetDataBlock->FchReset.Xhci1Enable == 0))) {
+ } else {
+ LibAmdMemWrite (AccessWidth8, (UINT64) ddtempVar, &pSciMapTbl->GpeMap, StdHeader);
+ }
+ } else {
+ //Assert Warning "SCI map is invalid"
+ }
+ pSciMapTbl++;
+ }
+ }
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * ProgramFchGpioTbl - Program FCH Gpio table (8 bits data)
+ *
+ *
+ *
+ * @param[in] pGpioTbl - Table data pointer
+ *
+ */
+VOID
+ProgramFchGpioTbl (
+ IN GPIO_CONTROL *pGpioTbl
+ )
+{
+ if (pGpioTbl != NULL) {
+ while (pGpioTbl->GpioPin != 0xFF) {
+ ACPIMMIO8 (ACPI_MMIO_BASE | IOMUX_BASE | pGpioTbl->GpioPin) = (UINT8) (pGpioTbl->PinFunction);
+ ACPIMMIO8 (ACPI_MMIO_BASE + GPIO_BANK0_BASE + ((UINT32)pGpioTbl->GpioPin << 2) + 2) = (UINT8) (pGpioTbl->CfgByte);
+ pGpioTbl++;
+ }
+ }
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * ProgramSataPhyTbl - Program FCH Sata Phy table (8 bits data)
+ *
+ *
+ *
+ * @param[in] pSataPhyTbl - Table data pointer
+ * @param[in] FchResetDataBlock
+ *
+ */
+VOID
+ProgramFchSataPhyTbl (
+ IN SATA_PHY_CONTROL *pSataPhyTbl,
+ IN FCH_RESET_DATA_BLOCK *FchResetDataBlock
+ )
+{
+ if (pSataPhyTbl != NULL) {
+ while (pSataPhyTbl->PhyData != 0xFFFFFFFF) {
+ //to be implemented
+ pSataPhyTbl++;
+ }
+ }
+}
+
+/**
+ * GetChipSysMode - Get Chip status
+ *
+ *
+ * @param[in] Value - Return Chip strap status
+ * StrapStatus [15.0] - Hudson-2 chip Strap Status
+ * @li <b>0001</b> - Not USED FWH
+ * @li <b>0002</b> - Not USED LPC ROM
+ * @li <b>0004</b> - EC enabled
+ * @li <b>0008</b> - Reserved
+ * @li <b>0010</b> - Internal Clock mode
+ * @param[in] StdHeader
+ *
+ */
+VOID
+GetChipSysMode (
+ IN VOID *Value,
+ IN AMD_CONFIG_PARAMS *StdHeader
+ )
+{
+ LibAmdMemRead (AccessWidth8, (UINT64) (ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG80), Value, StdHeader);
+}
+
+/**
+ * IsImcEnabled - Is IMC Enabled
+ * @retval TRUE for IMC Enabled; FALSE for IMC Disabled
+ */
+BOOLEAN
+IsImcEnabled (
+ IN AMD_CONFIG_PARAMS *StdHeader
+ )
+{
+ UINT8 dbSysConfig;
+ GetChipSysMode (&dbSysConfig, StdHeader);
+ if (dbSysConfig & ChipSysEcEnable) {
+ return TRUE;
+ } else {
+ return FALSE;
+ }
+}
+
+
+/**
+ * GetEfuseStatue - Get Efuse status
+ *
+ *
+ * @param[in] Value - Return Chip strap status
+ * @param[in] StdHeader
+ *
+ */
+VOID
+GetEfuseStatus (
+ IN VOID *Value,
+ IN AMD_CONFIG_PARAMS *StdHeader
+ )
+{
+ UINT8 Or8;
+ UINT8 Mask8;
+
+ Or8 = BIT5;
+ Mask8 = BIT5;
+ LibAmdMemRMW (AccessWidth8, (UINT64) (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGC8), &Or8, &Mask8, StdHeader);
+ LibAmdMemWrite (AccessWidth8, (UINT64) (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGD8), Value, StdHeader);
+ LibAmdMemRead (AccessWidth8, (UINT64) (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGD8 + 1), Value, StdHeader);
+ Or8 = 0;
+ Mask8 = BIT5;
+ LibAmdMemRMW (AccessWidth8, (UINT64) (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGC8), &Or8, &Mask8, StdHeader);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * SbSleepTrapControl - SB Sleep Trap Control
+ *
+ *
+ *
+ * @param[in] SleepTrap - Whether sleep trap is enabled
+ *
+ */
+VOID
+SbSleepTrapControl (
+ IN BOOLEAN SleepTrap
+ )
+{
+ if (SleepTrap) {
+ ACPIMMIO32 (ACPI_MMIO_BASE + SMI_BASE + FCH_SMI_REGB0) &= ~(BIT2 + BIT3);
+ ACPIMMIO32 (ACPI_MMIO_BASE + SMI_BASE + FCH_SMI_REGB0) |= BIT2;
+
+ ACPIMMIO8 (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGBE) &= ~ (BIT5);
+ ACPIMMIO8 (ACPI_MMIO_BASE + PMIO_BASE + 0xB) &= ~ (BIT0 + BIT1);
+ ACPIMMIO8 (ACPI_MMIO_BASE + PMIO_BASE + 0xB) |= BIT1;
+ } else {
+ ACPIMMIO8 (ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGBE) |= BIT5;
+ ACPIMMIO8 (ACPI_MMIO_BASE + PMIO_BASE + 0xB) &= ~ (BIT0 + BIT1);
+ ACPIMMIO8 (ACPI_MMIO_BASE + PMIO_BASE + 0xB) |= BIT0;
+
+ ACPIMMIO32 (ACPI_MMIO_BASE + SMI_BASE + FCH_SMI_REGB0) &= ~(BIT2 + BIT3);
+ }
+}
diff --git a/src/vendorcode/amd/pi/00660F01/Proc/Fch/Common/MemLib.c b/src/vendorcode/amd/pi/00660F01/Proc/Fch/Common/MemLib.c
new file mode 100644
index 0000000..656f768
--- /dev/null
+++ b/src/vendorcode/amd/pi/00660F01/Proc/Fch/Common/MemLib.c
@@ -0,0 +1,144 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * FCH memory access lib
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: FCH
+ * @e \$Revision: 309090 $ @e \$Date: 2014-12-09 12:28:05 -0600 (Tue, 09 Dec 2014) $
+ *
+ */
+ /*****************************************************************************
+ *
+ * Copyright (c) 2008 - 2015, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ***************************************************************************/
+#include "FchPlatform.h"
+#include "Ids.h"
+#define FILECODE PROC_FCH_COMMON_MEMLIB_FILECODE
+
+
+/**
+ * ReadMem - Read FCH BAR Memory
+ *
+ * @param[in] Address - Memory BAR address
+ * @param[in] OpFlag - Access width
+ * @param[in] *ValuePtr - In/Out value pointer
+ *
+ */
+VOID
+ReadMem (
+ IN UINT32 Address,
+ IN UINT8 OpFlag,
+ IN VOID *ValuePtr
+ )
+{
+ OpFlag = OpFlag & 0x7f;
+
+ switch ( OpFlag ) {
+ case AccessWidth8:
+ *((UINT8*)ValuePtr) = *((volatile UINT8*) ((UINTN)Address));
+ break;
+
+ case AccessWidth16:
+ *((UINT16*)ValuePtr) = *((volatile UINT16*) ((UINTN)Address));
+ break;
+
+ case AccessWidth32:
+ *((UINT32*)ValuePtr) = *((volatile UINT32*) ((UINTN)Address));
+ break;
+
+ default:
+ ASSERT (FALSE);
+ break;
+ }
+}
+
+/**
+ * WriteMem - Write FCH BAR Memory
+ *
+ * @param[in] Address - Memory BAR address
+ * @param[in] OpFlag - Access width
+ * @param[in] *ValuePtr - In/Out Value pointer
+ *
+ */
+VOID
+WriteMem (
+ IN UINT32 Address,
+ IN UINT8 OpFlag,
+ IN VOID *ValuePtr
+ )
+{
+ OpFlag = OpFlag & 0x7f;
+
+ switch ( OpFlag ) {
+ case AccessWidth8 :
+ *((volatile UINT8*) ((UINTN)Address)) = *((UINT8*)ValuePtr);
+ break;
+
+ case AccessWidth16:
+ *((volatile UINT16*) ((UINTN)Address)) = *((UINT16*)ValuePtr);
+ break;
+
+ case AccessWidth32:
+ *((volatile UINT32*) ((UINTN)Address)) = *((UINT32*)ValuePtr);
+ break;
+
+ default:
+ ASSERT (FALSE);
+ break;
+ }
+}
+
+/**
+ * RwMem - Read & Write FCH BAR Memory
+ *
+ * @param[in] Address - Memory BAR address
+ * @param[in] OpFlag - Access width
+ * @param[in] Mask - Mask Value of data
+ * @param[in] Data - Write data
+ *
+ */
+VOID
+RwMem (
+ IN UINT32 Address,
+ IN UINT8 OpFlag,
+ IN UINT32 Mask,
+ IN UINT32 Data
+ )
+{
+ UINT32 Result;
+
+ ReadMem (Address, OpFlag, &Result);
+ Result = (Result & Mask) | Data;
+ WriteMem (Address, OpFlag, &Result);
+ ReadMem (Address, OpFlag, &Result);
+}
+
diff --git a/src/vendorcode/amd/pi/00660F01/Proc/Fch/Common/PciLib.c b/src/vendorcode/amd/pi/00660F01/Proc/Fch/Common/PciLib.c
new file mode 100644
index 0000000..ed8bb81
--- /dev/null
+++ b/src/vendorcode/amd/pi/00660F01/Proc/Fch/Common/PciLib.c
@@ -0,0 +1,93 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * FCH PCI access lib
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: FCH
+ * @e \$Revision: 309090 $ @e \$Date: 2014-12-09 12:28:05 -0600 (Tue, 09 Dec 2014) $
+ *
+ */
+ /*****************************************************************************
+ *
+ * Copyright (c) 2008 - 2015, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ***************************************************************************/
+#include "FchPlatform.h"
+#define FILECODE PROC_FCH_COMMON_PCILIB_FILECODE
+
+VOID
+ReadPci (
+ IN UINT32 Address,
+ IN UINT8 OpFlag,
+ IN VOID* Value,
+ IN AMD_CONFIG_PARAMS *StdHeader
+ )
+{
+ PCI_ADDR PciAddress;
+
+ PciAddress.AddressValue = ((Address >> 4) & ~0xFFF) + (Address & 0xFFF);
+ LibAmdPciRead ((ACCESS_WIDTH) OpFlag, PciAddress, Value, StdHeader);
+}
+
+
+VOID
+WritePci (
+ IN UINT32 Address,
+ IN UINT8 OpFlag,
+ IN VOID *Value,
+ IN AMD_CONFIG_PARAMS *StdHeader
+ )
+{
+ PCI_ADDR PciAddress;
+
+ PciAddress.AddressValue = ((Address >> 4) & ~0xFFF) + (Address & 0xFFF);
+ LibAmdPciWrite ((ACCESS_WIDTH) OpFlag, PciAddress, Value, StdHeader);
+}
+
+
+VOID
+RwPci (
+ IN UINT32 Address,
+ IN UINT8 OpFlag,
+ IN UINT32 Mask,
+ IN UINT32 Data,
+ IN AMD_CONFIG_PARAMS *StdHeader
+ )
+{
+ PCI_ADDR PciAddress;
+ UINT32 rMask;
+
+ PciAddress.AddressValue = ((Address >> 4) & ~0xFFF) + (Address & 0xFFF);
+ rMask = ~Mask;
+ LibAmdPciRMW ((ACCESS_WIDTH) OpFlag, PciAddress, &Data, &rMask, StdHeader);
+}
+
+
diff --git a/src/vendorcode/amd/pi/00660F01/Proc/Fch/Fch.h b/src/vendorcode/amd/pi/00660F01/Proc/Fch/Fch.h
new file mode 100644
index 0000000..7576cad
--- /dev/null
+++ b/src/vendorcode/amd/pi/00660F01/Proc/Fch/Fch.h
@@ -0,0 +1,2603 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * FCH registers definition
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: FCH
+ * @e \$Revision: 314274 $ @e \$Date: 2015-03-08 03:53:49 -0500 (Sun, 08 Mar 2015) $
+ *
+ */
+ /*****************************************************************************
+ *
+ * Copyright (c) 2008 - 2015, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ***************************************************************************/
+#define FCH_REVISION "0.0.5.0"
+#define FCH_ID "FCH_A05"
+#define FCH_VERSION 0x0000
+
+/**
+ * @page fchinitguide FCH implement phase in AGESA
+ *
+ * FCH provides below access to supported FCH service functions
+ * and data.
+ * - @subpage fchreset "FCH_INIT_RESET"
+ * - @subpage fchenv "FCH_INIT_ENV"
+ * - @subpage fchmid "FCH_INIT_MID"
+ * - @subpage fchlate "FCH_INIT_LATE"
+ * - @subpage fchs3early "FCH_INIT_S3_EARLY_RESTORE"
+ * - @subpage fchs3late "FCH_INIT_S3_LATE_RESTORE"
+ * - @subpage fchsmm "FCH_SMM_SERVICE"
+ * - @subpage fchsmmacpion "FCH_SMM_ACPION"
+ */
+
+/*--------------------------- Documentation Pages ---------------------------*/
+/**
+ * @page fchreset FCH_INIT_RESET
+ * @section FCH_INIT_RESET Interface Call
+ * @par
+ * Initialize structure referenced by FCH_RESET_DATA_BLOCK to default recommended value.
+ * @subsection FCH_INIT_RESET_CallIn Call Prototype
+ * @par
+ * AGESA_STATUS FchInitReset (IN AMD_RESET_PARAMS *ResetParams);
+ * @subsection FCH_INIT_RESET_CallOut Prepare for Callout
+ * @par
+ * Not Applicable (Not necessary for the current implementation)
+ * @subsection FCH_INIT_RESET_Config Prepare for Configuration Data.
+ * @par
+ * <TABLE border="0">
+ * <TR><TD class="indexkey" width=380> BUILD_OPT_CFG::CfgSmbus0BaseAddress </TD><TD class="indexvalue"><B>Required </B></TD></TR>
+ * <TR><TD class="indexkey" width=380> BUILD_OPT_CFG::CfgSmbus1BaseAddress </TD><TD class="indexvalue"><B>Required </B></TD></TR>
+ * <TR><TD class="indexkey" width=380> BUILD_OPT_CFG::CfgSioPmeBaseAddress </TD><TD class="indexvalue"><B>Required </B></TD></TR>
+ * <TR><TD class="indexkey" width=380> BUILD_OPT_CFG::CfgWatchDogTimerBase </TD><TD class="indexvalue"><B>Required </B></TD></TR>
+ * <TR><TD class="indexkey" width=380> BUILD_OPT_CFG::CfgGecShadowRomBase </TD><TD class="indexvalue"><B>Required </B></TD></TR>
+ * <TR><TD class="indexkey" width=380> BUILD_OPT_CFG::CfgSpiRomBaseAddress </TD><TD class="indexvalue"><B>Required </B></TD></TR>
+ * <TR><TD class="indexkey" width=380> BUILD_OPT_CFG::CfgAcpiPm1EvtBlkAddr </TD><TD class="indexvalue"><B>Required </B></TD></TR>
+ * <TR><TD class="indexkey" width=380> BUILD_OPT_CFG::CfgAcpiPm1CntBlkAddr </TD><TD class="indexvalue"><B>Required </B></TD></TR>
+ * <TR><TD class="indexkey" width=380> BUILD_OPT_CFG::CfgAcpiPmTmrBlkAddr </TD><TD class="indexvalue"><B>Required </B></TD></TR>
+ * <TR><TD class="indexkey" width=380> BUILD_OPT_CFG::CfgCpuControlBlkAddr </TD><TD class="indexvalue"><B>Required </B></TD></TR>
+ * <TR><TD class="indexkey" width=380> BUILD_OPT_CFG::CfgAcpiGpe0BlkAddr </TD><TD class="indexvalue"><B>Required </B></TD></TR>
+ * <TR><TD class="indexkey" width=380> BUILD_OPT_CFG::CfgSmiCmdPortAddr </TD><TD class="indexvalue"><B>Required </B></TD></TR>
+ * <TR><TD class="indexkey" width=380> BUILD_OPT_CFG::CfgAcpiPmaCntBlkAddr </TD><TD class="indexvalue"><B>Required </B></TD></TR>
+ * <TR><TD class="indexkey" width=380> FCH_RESET_INTERFACE::SataEnable </TD><TD class="indexvalue"><B>Optional </B></TD></TR>
+ * <TR><TD class="indexkey" width=380> FCH_RESET_INTERFACE::IdeEnable </TD><TD class="indexvalue"><B>Optional </B></TD></TR>
+ * </TABLE>
+ *
+ */
+
+/*--------------------------- Documentation Pages ---------------------------*/
+/**
+ * @page fchenv FCH_INIT_ENV
+ * @section FCH_INIT_ENV Interface Call
+ * @par
+ * Initialize structure referenced by FCH_DATA_BLOCK to default recommended value.
+ * @subsection FCH_INIT_ENV_CallIn Call Prototype
+ * @par
+ * AGESA_STATUS FchInitEnv (IN AMD_ENV_PARAMS *EnvParams);
+ * @subsection FCH_INIT_ENV_CallOut Prepare for Callout
+ * @par
+ * Not Applicable (Not necessary for the current implementation)
+ * @subsection FCH_INIT_ENV_Config Prepare for Configuration Data.
+ * @par
+ * <TABLE border="0">
+ * <TR><TD class="indexkey" width=380> FCH_INTERFACE::SdConfig </TD><TD class="indexvalue"><B>Optional </B></TD></TR>
+ * <TR><TD class="indexkey" width=380> FCH_INTERFACE::AzaliaController </TD><TD class="indexvalue"><B>Optional </B></TD></TR>
+ * <TR><TD class="indexkey" width=380> FCH_INTERFACE::IrConfig </TD><TD class="indexvalue"><B>Optional </B></TD></TR>
+ * <TR><TD class="indexkey" width=380> FCH_INTERFACE::SataClass </TD><TD class="indexvalue"><B>Optional </B></TD></TR>
+ * <TR><TD class="indexkey" width=380> FCH_INTERFACE::SataEnable </TD><TD class="indexvalue"><B>Optional </B></TD></TR>
+ * <TR><TD class="indexkey" width=380> FCH_INTERFACE::SataIdeMode </TD><TD class="indexvalue"><B>Optional </B></TD></TR>
+ * <TR><TD class="indexkey" width=380> FCH_INTERFACE::Ohci1Enable </TD><TD class="indexvalue"><B>Optional </B></TD></TR>
+ * <TR><TD class="indexkey" width=380> FCH_INTERFACE::Ohci2Enable </TD><TD class="indexvalue"><B>Optional </B></TD></TR>
+ * <TR><TD class="indexkey" width=380> FCH_INTERFACE::Ohci3Enable </TD><TD class="indexvalue"><B>Optional </B></TD></TR>
+ * <TR><TD class="indexkey" width=380> FCH_INTERFACE::Ohci4Enable </TD><TD class="indexvalue"><B>Optional </B></TD></TR>
+ * </TABLE>
+ *
+ */
+
+/*--------------------------- Documentation Pages ---------------------------*/
+/**
+ * @page fchmid FCH_INIT_MID
+ * @section FCH_INIT_MID Interface Call
+ * @par
+ * Initialize structure referenced by FCH_DATA_BLOCK to default recommended value.
+ * @subsection FCH_INIT_MID_CallIn Call Prototype
+ * @par
+ * AGESA_STATUS FchInitMid (IN AMD_MID_PARAMS *MidParams);
+ * @subsection FCH_INIT_MID_CallOut Prepare for Callout
+ * @par
+ * Not Applicable (Not necessary for the current implementation)
+ * @subsection FCH_INIT_MID_Config Prepare for Configuration Data.
+ * @par
+ * <TABLE border="0">
+ * <TR><TD class="indexkey" width=380> FCH_INTERFACE::AzaliaController </TD><TD class="indexvalue"><B>Optional </B></TD></TR>
+ * <TR><TD class="indexkey" width=380> FCH_INTERFACE::SataClass </TD><TD class="indexvalue"><B>Optional </B></TD></TR>
+ * <TR><TD class="indexkey" width=380> FCH_INTERFACE::SataEnable </TD><TD class="indexvalue"><B>Optional </B></TD></TR>
+ * <TR><TD class="indexkey" width=380> FCH_INTERFACE::IdeEnable </TD><TD class="indexvalue"><B>Optional </B></TD></TR>
+ * </TABLE>
+ *
+ */
+
+/*--------------------------- Documentation Pages ---------------------------*/
+/**
+ * @page fchlate FCH_INIT_LATE
+ * @section FCH_INIT_LATE Interface Call
+ * @par
+ * Initialize structure referenced by FCH_DATA_BLOCK to default recommended value.
+ * @subsection FCH_INIT_LATE_CallIn Call Prototype
+ * @par
+ * AGESA_STATUS FchInitLate (IN FCH_DATA_BLOCK *LateParams);
+ * @subsection FCH_INIT_LATE_CallOut Prepare for Callout
+ * @par
+ * Not Applicable (Not necessary for the current implementation)
+ * @subsection FCH_INIT_LATE_Config Prepare for Configuration Data.
+ * @par
+ * <TABLE border="0">
+ * <TR><TD class="indexkey" width=380> FCH_INTERFACE::SataClass </TD><TD class="indexvalue"><B>Optional </B></TD></TR>
+ * <TR><TD class="indexkey" width=380> FCH_INTERFACE::SataEnable </TD><TD class="indexvalue"><B>Optional </B></TD></TR>
+ * <TR><TD class="indexkey" width=380> BUILD_OPT_CFG::CfgSpiRomBaseAddress </TD><TD class="indexvalue"><B>Required </B></TD></TR>
+ * </TABLE>
+ *
+ */
+
+/*--------------------------- Documentation Pages ---------------------------*/
+/**
+ * @page fchs3early FCH_INIT_S3_EARLY_RESTORE
+ * @section FCH_INIT_S3_EARLY_RESTORE Interface Call
+ * @par
+ * Initialize structure referenced by FCH_DATA_BLOCK to default recommended value.
+ * @subsection FCH_INIT_S3_EARLY_RESTORE_CallIn Call Prototype
+ * @par
+ * VOID FchInitS3EarlyRestore (IN FCH_DATA_BLOCK *FchDataPtr);
+ * @subsection FCH_INIT_S3_EARLY_RESTORE_CallOut Prepare for Callout
+ * @par
+ * Not Applicable (Not necessary for the current implementation)
+ * @subsection FCH_INIT_S3_EARLY_RESTORE_Config Prepare for Configuration Data.
+ * @par
+ * <TABLE border="0">
+ * <TR><TD class="indexkey" width=380> FCH_INTERFACE::SdConfig </TD><TD class="indexvalue"><B>Optional </B></TD></TR>
+ * <TR><TD class="indexkey" width=380> FCH_INTERFACE::AzaliaController </TD><TD class="indexvalue"><B>Optional </B></TD></TR>
+ * <TR><TD class="indexkey" width=380> FCH_INTERFACE::IrConfig </TD><TD class="indexvalue"><B>Optional </B></TD></TR>
+ * <TR><TD class="indexkey" width=380> FCH_INTERFACE::SataClass </TD><TD class="indexvalue"><B>Optional </B></TD></TR>
+ * <TR><TD class="indexkey" width=380> FCH_INTERFACE::SataEnable </TD><TD class="indexvalue"><B>Optional </B></TD></TR>
+ * <TR><TD class="indexkey" width=380> FCH_INTERFACE::SataIdeMode </TD><TD class="indexvalue"><B>Optional </B></TD></TR>
+ * <TR><TD class="indexkey" width=380> FCH_INTERFACE::Ohci1Enable </TD><TD class="indexvalue"><B>Optional </B></TD></TR>
+ * <TR><TD class="indexkey" width=380> FCH_INTERFACE::Ohci2Enable </TD><TD class="indexvalue"><B>Optional </B></TD></TR>
+ * <TR><TD class="indexkey" width=380> FCH_INTERFACE::Ohci3Enable </TD><TD class="indexvalue"><B>Optional </B></TD></TR>
+ * <TR><TD class="indexkey" width=380> FCH_INTERFACE::Ohci4Enable </TD><TD class="indexvalue"><B>Optional </B></TD></TR>
+ * </TABLE>
+ *
+ */
+
+/*--------------------------- Documentation Pages ---------------------------*/
+/**
+ * @page fchs3late FCH_INIT_S3_LATE_RESTORE
+ * @section FCH_INIT_S3_LATE_RESTORE Interface Call
+ * @par
+ * Initialize structure referenced by FCH_DATA_BLOCK to default recommended value.
+ * @subsection FCH_INIT_S3_LATE_RESTORE_CallIn Call Prototype
+ * @par
+ * VOID FchInitS3LateRestore (IN FCH_DATA_BLOCK *FchDataPtr);
+ * @subsection FCH_INIT_S3_LATE_RESTORE_CallOut Prepare for Callout
+ * @par
+ * Not Applicable (Not necessary for the current implementation)
+ * @subsection FCH_INIT_S3_LATE_RESTORE_Config Prepare for Configuration Data.
+ * @par
+ * <TABLE border="0">
+ * <TR><TD class="indexkey" width=380> FCH_INTERFACE::AzaliaController </TD><TD class="indexvalue"><B>Optional </B></TD></TR>
+ * <TR><TD class="indexkey" width=380> FCH_INTERFACE::SataClass </TD><TD class="indexvalue"><B>Optional </B></TD></TR>
+ * <TR><TD class="indexkey" width=380> FCH_INTERFACE::SataEnable </TD><TD class="indexvalue"><B>Optional </B></TD></TR>
+ * <TR><TD class="indexkey" width=380> FCH_INTERFACE::IdeEnable </TD><TD class="indexvalue"><B>Optional </B></TD></TR>
+ * <TR><TD class="indexkey" width=380> BUILD_OPT_CFG::CfgSpiRomBaseAddress </TD><TD class="indexvalue"><B>Required </B></TD></TR>
+ * </TABLE>
+ *
+ */
+
+/*--------------------------- Documentation Pages ---------------------------*/
+/**
+ * @page fchsmm FCH_SMM_SERVICE
+ * @section FCH_SMM_SERVICE Interface Call
+ * Initialize structure referenced by FCHCFG to default recommended value.
+ * @subsection FCH_SMM_SERVICE_CallIn Call Prototype
+ * @par
+ * FchSmmService ((FCHCFG*)pConfig) (Followed PH Interface)
+ * @subsection FCH_SMM_SERVICE_CallID Service ID
+ * @par
+ * <TABLE border="0">
+ * <TR><TD class="indexkey" width=380> FCH_SMM_SERVICE --> 0x00010060 </TD></TR>
+ * </TABLE>
+ * @subsection FCH_SMM_SERVICE_CallOut Prepare for Callout
+ * @par
+ * Not Applicable (Not necessary for the current implementation)
+ * @subsection FCH_SMM_SERVICE_Config Prepare for Configuration Data.
+ * @par
+ * Not necessary on current implementation
+ *
+ */
+#define FCH_SMM_SERVICE 0x00010060ul
+/*--------------------------- Documentation Pages ---------------------------*/
+/**
+ * @page fchsmmacpion FCH_SMM_ACPION
+ * @section FCH_SMM_ACPION Interface Call
+ * Initialize structure referenced by FCHCFG to default recommended value.
+ * @subsection FCH_SMM_ACPION_CallIn Call Prototype
+ * @par
+ * FchSmmAcpiOn ((FCHCFG*)pConfig) (Followed PH Interface)
+ * @subsection FCH_SMM_ACPION_CallID Service ID
+ * @par
+ * <TABLE border="0">
+ * <TR><TD class="indexkey" width=380> FCH_SMM_ACPION --> 0x00010061 </TD></TR>
+ * </TABLE>
+ * @subsection FCH_SMM_ACPION_CallOut Prepare for Callout
+ * @par
+ * Not Applicable (Not necessary for the current implementation)
+ * @subsection FCH_SMM_ACPION_Config Prepare for Configuration Data.
+ * @par
+ * Not necessary on current implementation
+ *
+ */
+#define FCH_SMM_ACPION 0x00010061ul
+
+#ifndef OEM_CALLBACK_BASE
+ #define OEM_CALLBACK_BASE 0x00010100ul
+#endif
+
+//0x00 - 0x0F callback functions are reserved for bootblock
+#define SATA_PHY_PROGRAMMING OEM_CALLBACK_BASE + 0x10
+#define PULL_UP_PULL_DOWN_SETTINGS OEM_CALLBACK_BASE + 0x20
+/*--------------------------- Documentation Pages ---------------------------*/
+/**
+ * @page CB_SBGPP_RESET_ASSERT_Page CB_SBGPP_RESET_ASSERT
+ * @section CB_SBGPP_RESET_ASSERT Interface Call
+ * Initialize structure referenced by FCHCFG to default recommended value.
+ * @subsection CB_SBGPP_RESET_ASSERT_CallID Service ID
+ * @par
+ * <TABLE border="0">
+ * <TR><TD class="indexkey" width=380> CB_SBGPP_RESET_ASSERT --> 0x00010130 </TD></TR>
+ * </TABLE>
+ * @subsection CB_SBGPP_RESET_ASSERT_Config Prepare for Configuration Data.
+ * @par
+ * Not necessary on current implementation
+ *
+ */
+#define CB_SBGPP_RESET_ASSERT OEM_CALLBACK_BASE + 0x30
+/*--------------------------- Documentation Pages ---------------------------*/
+/**
+ * @page CB_SBGPP_RESET_DEASSERT_Page CB_SBGPP_RESET_DEASSERT
+ * @section CB_SBGPP_RESET_DEASSERT Interface Call
+ * Initialize structure referenced by FCHCFG to default recommended value.
+ * @subsection CB_SBGPP_RESET_DEASSERT _CallID Service ID
+ * @par
+ * <TABLE border="0">
+ * <TR><TD class="indexkey" width=380> CB_SBGPP_RESET_DEASSERT --> 0x00010131 </TD></TR>
+ * </TABLE>
+ * @subsection CB_SBGPP_RESET_DEASSERT _Config Prepare for Configuration Data.
+ * @par
+ * Not necessary on current implementation
+ *
+ */
+#define CB_SBGPP_RESET_DEASSERT OEM_CALLBACK_BASE + 0x31
+
+#define CFG_ADDR_PORT 0xCF8
+#define CFG_DATA_PORT 0xCFC
+
+#define ALINK_ACCESS_INDEX 0x0CD8
+#define ALINK_ACCESS_DATA ALINK_ACCESS_INDEX + 4
+
+/*------------------------------------------------------------------
+; I/O Base Address - Should be set by host BIOS
+;------------------------------------------------------------------ */
+#define DELAY_PORT 0x0E0
+
+#define FCH_8259_CONTROL_REG_MASTER 0x20
+#define FCH_8259_MASK_REG_MASTER 0x21
+
+/*------------------------------------------------------------------
+; DEBUG_PORT = 8-bit I/O Port Address for POST Code Display
+;------------------------------------------------------------------ */
+// ASIC VendorID and DeviceIDs
+#define ATI_VID 0x1002
+#define AMD_FCH_VID 0x1022
+#define FCH_DEVICE_ID 0x780B
+#define FCH_SATA_VID AMD_FCH_VID // Dev 17 Func 0
+#define FCH_SATA_DID 0x7800
+#define FCH_SATA_AHCI_DID 0x7801
+#define FCH_SATA_RAID_DID 0x7802
+#define FCH_SATA_RAID5_DID 0x7803
+#define FCH_SATA_AMDAHCI_DID 0x7804
+#define FCH_SATA_RAID_DOTHILL_DID 0x7805
+#define FCH_SATA_RAID5_DOTHILL_DID 0x780A
+#define FCH_USB_OHCI_VID AMD_FCH_VID // Dev 18 Func 0, Dev 19 Func 0
+#define FCH_USB_OHCI_DID 0x7807
+#define FCH_USB_EHCI_VID AMD_FCH_VID // Dev 18 Func 2, Dev 19 Func 2
+#define FCH_USB_EHCI_DID 0x7808
+#define FCH_USB_XHCI_VID AMD_FCH_VID // Dev 10 Func 0, Dev 10 Func 1
+#define FCH_USB_XHCI_DID 0x7812
+#define FCH_USB_XHCI_DID_BOLTON 0x7814
+#define FCH_USB_XHCI_DID_KABINI 0x7814
+#define FCH_SMBUS_VID AMD_FCH_VID // Dev 20 Func 0
+#define FCH_SMBUS_DID 0x780B
+#define FCH_IDE_VID AMD_FCH_VID // Dev 20 Func 1
+#define FCH_IDE_DID 0x780C
+#define FCH_AZALIA_VID AMD_FCH_VID // Dev 20 Func 2
+#define FCH_AZALIA_DID 0x157a
+#define FCH_LPC_VID AMD_FCH_VID // Dev 20 Func 3
+#define FCH_LPC_DID 0x780E
+#define FCH_PCIB_VID AMD_FCH_VID // Dev 20 Func 4
+#define FCH_PCIB_DID 0x780F
+#define FCH_USB_OHCIF_VID AMD_FCH_VID // dev 20 Func 5
+#define FCH_USB_OHCIF_DID 0x7809
+#define FCH_NIC_VID 0x14E4 // Dev 20 Func 6
+#define FCH_NIC_DID 0x1699
+#define FCH_SD_VID AMD_FCH_VID // Dev 20 Func 7
+#define FCH_SD_DID 0x7806
+
+//FCH Variant
+#define FCH_Variant_EFUSE_LOCATION 0x1E // EFUSE bit 240-247
+
+#define FCH_M2 0x01
+#define FCH_M3 0x03
+#define FCH_M3T 0x07
+#define FCH_D2 0x0F
+#define FCH_D3 0x1F
+#define FCH_D4 0x3F
+#define FCH_BOLTON 0x15
+#define FCH_YANGTZE 0x39
+#define FCH_YANGTZEA1 0x3A
+#define FCH_AVALONA0 0x41
+#define FCH_AVALONA1 0x42
+//Misc
+#define R_FCH_ACPI_PM1_STATUS 0x00
+#define R_FCH_ACPI_PM1_ENABLE 0x02
+#define R_FCH_ACPI_PM_CONTROL 0x04
+#define R_FCH_ACPI_EVENT_STATUS 0x20
+#define R_FCH_ACPI_EVENT_ENABLE 0x24
+#define R_FCH_PM_ACPI_PMA_CNT_BLK_LO 0x2C
+
+// ACPI Sleep Type
+#define ACPI_SLPTYP_S0 0
+#define ACPI_SLPTYP_S1 1
+#define ACPI_SLPTYP_S3 3
+#define ACPI_SLPTYP_S4 4
+#define ACPI_SLPTYP_S5 5
+
+//#define SATA_BUS_DEV_FUN_FPGA 0x228
+#define SATA_BUS_DEV_FUN ((0x11 << 3) + 0)
+#define FCH_SATA1_BUS 0
+#define FCH_SATA1_DEV 17
+#define FCH_SATA1_FUNC 0
+
+#define FC_BUS_DEV_FUN ((0x11 << 3) + 1)
+#define FCH_XHCI_BUS 0
+#define FCH_XHCI_DEV 16
+#define FCH_XHCI_FUNC 0
+#define USB_XHCI_BUS_DEV_FUN ((FCH_XHCI_DEV << 3) + FCH_XHCI_FUNC)
+#define FCH_XHCI1_BUS 0
+#define FCH_XHCI1_DEV 16
+#define FCH_XHCI1_FUNC 1
+#define USB_XHCI1_BUS_DEV_FUN ((FCH_XHCI1_DEV << 3) + FCH_XHCI1_FUNC)
+#define USB1_OHCI_BUS_DEV_FUN ((0x12 << 3) + 0) // PORT 0-4
+#define FCH_OHCI1_BUS 0
+#define FCH_OHCI1_DEV 18
+#define FCH_OHCI1_FUNC 0
+#define USB2_OHCI_BUS_DEV_FUN ((0x13 << 3) + 0) // PORT 5-9
+#define FCH_OHCI2_BUS 0
+#define FCH_OHCI2_DEV 19
+#define FCH_OHCI2_FUNC 0
+#define USB3_OHCI_BUS_DEV_FUN ((0x16 << 3) + 0) // PORT 10-13
+#define FCH_OHCI3_BUS 0
+#define FCH_OHCI3_DEV 22
+#define FCH_OHCI3_FUNC 0
+#define USB1_EHCI_BUS_DEV_FUN ((0x12 << 3) + 2) // PORT 0-4
+#define FCH_EHCI1_BUS 0
+#define FCH_EHCI1_DEV 18
+#define FCH_EHCI1_FUNC 2
+#define USB2_EHCI_BUS_DEV_FUN ((0x13 << 3) + 2) // PORT 5-9
+#define FCH_EHCI2_BUS 0
+#define FCH_EHCI2_DEV 19
+#define FCH_EHCI2_FUNC 2
+#define USB3_EHCI_BUS_DEV_FUN ((0x16 << 3) + 2) // PORT 10-13
+#define FCH_EHCI3_BUS 0
+#define FCH_EHCI3_DEV 22
+#define FCH_EHCI3_FUNC 2
+#define SMBUS_BUS_DEV_FUN ((0x14 << 3) + 0)
+#define FCH_ISA_BUS 0
+#define FCH_ISA_DEV 20
+#define FCH_ISA_FUNC 0
+#define IDE_BUS_DEV_FUN ((0x14 << 3) + 1)
+#define FCH_IDE_BUS 0
+#define FCH_IDE_DEV 20
+#define FCH_IDE_FUNC 1
+#define AZALIA_BUS_DEV_FUN ((0x9 << 3) + 2)
+#define FCH_AZALIA_BUS 0
+#define FCH_AZALIA_DEV 9
+#define FCH_AZALIA_FUNC 2
+#define LPC_BUS_DEV_FUN ((0x14 << 3) + 3)
+#define FCH_LPC_BUS 0
+#define FCH_LPC_DEV 20
+#define FCH_LPC_FUNC 3
+#define PCIB_BUS_DEV_FUN ((0x14 << 3) + 4) // P2P in SB700
+#define FCH_PCI_BUS 0
+#define FCH_PCI_DEV 20
+#define FCH_PCI_FUNC 4
+#define USB4_OHCI_BUS_DEV_FUN ((0x14 << 3) + 5) // PORT FL0 - FL1
+#define FCH_OHCI4_BUS 0
+#define FCH_OHCI4_DEV 20
+#define FCH_OHCI4_FUNC 5
+//Gigabyte Ethernet Controller
+#define GEC_BUS_DEV_FUN ((0x14 << 3) + 6)
+#define FCH_GBEC_BUS 0
+#define FCH_GBEC_DEV 20
+#define FCH_GBEC_FUNC 6
+
+#define SD_BUS_DEV_FUN ((0x14 << 3) + 7) // SD Controller
+#define SD_PCI_BUS 0
+#define SD_PCI_DEV 20
+#define SD_PCI_FUNC 7
+
+
+#define FCH_GPP_BUS 0
+#define FCH_GPP_DEV 21
+#define FCH_GPP_FUNC 0
+#define GPP0_BUS_DEV_FUN ((0x15 << 3) + 0) // GPP P2P bridge PORT0
+#define GPP1_BUS_DEV_FUN ((0x15 << 3) + 1) // GPP P2P bridge PORT1
+#define GPP2_BUS_DEV_FUN ((0x15 << 3) + 2) // GPP P2P bridge PORT2
+#define GPP3_BUS_DEV_FUN ((0x15 << 3) + 3) // GPP P2P bridge PORT3
+
+#define ACPI_MMIO_BASE 0xFED80000ul
+#define FCH_CFG_BASE 0x000 // DWORD
+#define GPIO_BASE 0x100 // BYTE
+#define SMI_BASE 0x200 // DWORD
+#define PMIO_BASE 0x300 // DWORD
+#define PMIO2_BASE 0x400 // BYTE
+#define BIOS_RAM_BASE 0x500 // BYTE
+#define CMOS_RAM_BASE 0x600 // BYTE
+#define CMOS_BASE 0x700 // BYTE
+#define ASF_BASE 0x900 // DWORD
+#define SMBUS_BASE 0xA00 // DWORD
+#define WATCHDOG_BASE 0xB00 //
+#define HPET_BASE 0xC00 // DWORD
+#define IOMUX_BASE 0xD00 // BYTE
+#define MISC_BASE 0xE00
+#define SERIAL_DEBUG_BASE 0x1000
+#define GFX_DAC_BASE 0x1400
+#define GPIO_BANK0_BASE 0x1500 // DWORD
+//#define GPIO_BANK1_BASE 0x1600 // DWORD
+//#define GPIO_BANK2_BASE 0x1700 // DWORD
+#define CEC_BASE 0x1800
+#define XHCI_BASE 0x1C00
+#define ACDC_BASE 0x1D00
+#define AOAC_BASE 0x1E00
+
+
+// Chip type definition
+#define CHIPTYPE_HUDSON2 (1 << 0)
+#define CHIPTYPE_YUBA (1 << 1)
+
+//
+// ROM SIG type definition
+//
+#define NUM_OF_ROMSIG_FILED 0x04
+#define XHCI_FILED_NUM 0x03
+#define ROMSIG_CFG_MASK 0x07
+#define XHCI_BOOT_RAM_OFFSET 0x8000
+#define INSTRUCTION_RAM_SIG 0x55AA
+#define ROMSIG_SIG 0x55AA55AAul
+
+// RegSpace field (AB_INDEX[31:29]
+#define AXINDC 0 // AXINDC
+#define AXINDP 2 // AXINDP
+#define ABCFG 6 // ABCFG
+#define AXCFG 4 // AXCFG
+#define RCINDXC 1 // PCIEIND
+#define RCINDXP 3 // PCIEIND_P
+
+#define GPP_DEV_NUM 21 //
+#define MAX_GPP_PORTS 4
+
+#define PCIE_FORCE_GEN1_EFUSE_LOCATION 0x14 // EFUSE bit 160
+//
+// ABCFG Registers
+//
+#define FCH_ABCFG_REG00 0x00 // VENDOR ID
+#define FCH_ABCFG_REG08 0x08 // REVISION ID
+#define FCH_ABCFG_REG40 0x40 // BL_EVENTCNT0LO
+#define FCH_ABCFG_REG44 0x44 // BL_EVENTCNT1LO
+#define FCH_ABCFG_REG48 0x48 // BL_EVENTCNTSEL
+#define FCH_ABCFG_REG4A 0x4A // BL_EVENTCNT0HI
+#define FCH_ABCFG_REG4B 0x4B // BL_EVENTCNT1HI
+#define FCH_ABCFG_REG4C 0x4C // BL_EVENTCNTCTL
+#define FCH_ABCFG_REG50 0x50 // MISCCTL_50
+#define FCH_ABCFG_REG54 0x54 // MISCCTL_54
+#define FCH_ABCFG_REG58 0x58 // BL RAB CONTROL
+
+#define FCH_ABCFG_REG60 0x60 // LINKWIDTH_CTL
+#define FCH_ABCFG_REG64 0x64 // LINKWIDTH_UP_INTERVAL
+#define FCH_ABCFG_REG68 0x68 // LINKWIDTH_DN_INVERVAL
+#define FCH_ABCFG_REG6C 0x6C // LINKWIDTH_UPSTREAM_DWORDS
+#define FCH_ABCFG_REG70 0x70 // LINKWIDTH_DOWNSTREAM_DWORDS
+#define FCH_ABCFG_REG74 0x74 // LINKWIDTH_THRESHOLD_INCREASE
+#define FCH_ABCFG_REG78 0x78 // LINKWIDTH_THRESHOLD_DECREASE
+
+#define FCH_ABCFG_REG80 0x80 // BL DMA PREFETCH CONTROL
+#define FCH_ABCFG_REG88 0x88 //
+#define FCH_ABCFG_REG8C 0x8C //
+#define FCH_ABCFG_REG90 0x90 // BIF CONTROL 0
+#define FCH_ABCFG_REG94 0x94 // MSI CONTROL
+#define FCH_ABCFG_REG98 0x98 // BIF CONTROL 1
+#define FCH_ABCFG_REG9C 0x9C // MISCCTL_9C
+#define FCH_ABCFG_REGA0 0xA0 // BIF PHY CONTROL ENABLE
+#define FCH_ABCFG_REGA4 0xA4 // BIF PHY CONTROL A4
+#define FCH_ABCFG_REGA8 0xA8 // BIF PHY CONTROL A8
+#define FCH_ABCFG_REGB0 0xB0 // HYPERFLASH-PCIE PORT MAPPING
+#define FCH_ABCFG_REGB8 0xB8 //
+#define FCH_ABCFG_REGB4 0xB4 //
+#define FCH_ABCFG_REGBC 0xBC //
+#define FCH_ABCFG_REGC0 0xC0 // PCIE_GPP_ENABLE
+#define FCH_ABCFG_REGC4 0xC4 // PCIE_P2P_INT_MAP
+#define FCH_ABCFG_REGD0 0xD0 // MCTP_VDM_TX_FIFO_DATA
+#define FCH_ABCFG_REGD4 0xD4 // MCTP_VMD_TX_CONTROL
+#define FCH_ABCFG_REGE0 0xE0 // MCTP_VDM_RX_FIFO_DATA
+#define FCH_ABCFG_REGE4 0xE4 // MCTP_VDM_RX_FIFO_STATUS
+#define FCH_ABCFG_REGEC 0xEC // MCTP_VDM_CONTROL
+#define FCH_ABCFG_REGF0 0xF0 // GPP_UPSTREAM_CONTROL
+#define FCH_ABCFG_REGF4 0xF4 // GPP_SYSTEM_ERROR_CONTROL
+#define FCH_ABCFG_REGFC 0xFC // FCH_TRAP_CONTROL
+#define FCH_ABCFG_REG100 0x100 // FCH_TRAP0_ADDRL
+#define FCH_ABCFG_REG104 0x104 // FCH_TRAP0_ADDRH
+#define FCH_ABCFG_REG108 0x108 // FCH_TRAP0_CMD
+#define FCH_ABCFG_REG10C 0x10C // FCH_TRAP1_DATA
+#define FCH_ABCFG_REG110 0x110 // FCH_TRAP1_ADDRL
+#define FCH_ABCFG_REG114 0x114 // FCH_TRAP1_ADDRH
+#define FCH_ABCFG_REG118 0x118 // FCH_TRAP1_CMD
+#define FCH_ABCFG_REG11C 0x11C // FCH_TRAP1_DATA
+#define FCH_ABCFG_REG120 0x120 // FCH_TRAP2_ADDRL
+#define FCH_ABCFG_REG124 0x124 // FCH_TRAP2_ADDRH
+#define FCH_ABCFG_REG128 0x128 // FCH_TRAP2_CMD
+#define FCH_ABCFG_REG12C 0x12C // FCH_TRAP2_DATA
+#define FCH_ABCFG_REG130 0x130 // FCH_TRAP3_ADDRL
+#define FCH_ABCFG_REG134 0x134 // FCH_TRAP3_ADDRH
+#define FCH_ABCFG_REG138 0x138 // FCH_TRAP3_CMD
+#define FCH_ABCFG_REG13C 0x13C // FCH_TRAP3_DATA
+#define FCH_ABCFG_REG180 0x180 // FCH_DMA_TRAFFIC_CONTROL
+#define FCH_ABCFG_REG184 0x184 // FCH_AXI_DMA_MEMORY_POWER_SAVING
+#define FCH_ABCFG_REG208 0x208 // SBG_MISC
+#define FCH_ABCFG_REG300 0x300 // MCTP_VDM_RX_SMI_CONTROL
+#define FCH_ABCFG_REG310 0x310 // BIF_GPP_STRAP_SYSTEM_0
+#define FCH_ABCFG_REG314 0x314 // BIF_GPP_STRAP_SYSTEM_1
+#define FCH_ABCFG_REG31C 0x31C // BIF_GPP_STRAP_LINK_CONTROL_0
+#define FCH_ABCFG_REG320 0x320 // BIF_GPP_STRAP_LINK_CONTROL_LANE_A
+#define FCH_ABCFG_REG324 0x324 // BIF_GPP_STRAP_LINK_CONTROL_LANE_B
+#define FCH_ABCFG_REG328 0x328 // BIF_GPP_STRAP_LINK_CONTROL_LANE_C
+#define FCH_ABCFG_REG32C 0x32C // BIF_GPP_STRAP_LINK_CONTROL_LANE_D
+#define FCH_ABCFG_REG330 0x330 // BIF_GPP_STRAP_BIF_0
+#define FCH_ABCFG_REG334 0x334 // BIF_GPP_STRAP_BIF_1
+#define FCH_ABCFG_REG338 0x338 // BIF_GPP_STRAP_BIF_2
+#define FCH_ABCFG_REG340 0x340 // BIF_GPP_STRAP_BIF_LANE_A
+#define FCH_ABCFG_REG344 0x344 // BIF_GPP_STRAP_BIF_LANE_B
+#define FCH_ABCFG_REG348 0x348 // BIF_GPP_STRAP_BIF_LANE_C
+#define FCH_ABCFG_REG34C 0x34C // BIF_GPP_STRAP_BIF_LANE_D
+#define FCH_ABCFG_REG350 0x350 // BIF_GPP_STRAP_PHY_LOGICAL _0
+#define FCH_ABCFG_REG354 0x354 // BIF_GPP_STRAP_PHY_LOGICAL _1
+#define FCH_ABCFG_REG404 0x404 // GPP0_SHADOW_COMMAND
+#define FCH_ABCFG_REG418 0x418 // GPP0_SHADOW_BUS_NUMBER
+#define FCH_ABCFG_REG41C 0x41C // GPP0_SHADOW_IO_LIMIT_BASE
+#define FCH_ABCFG_REG420 0x420 // GPP0_SHADOW_MEM_LIMIT_BASE
+#define FCH_ABCFG_REG424 0x424 // GPP0_SHADOW_PREF_MEM_LIMIT_BASE
+#define FCH_ABCFG_REG428 0x428 // GPP0_SHADOW_PREF_MEM_BASE_UPPER
+#define FCH_ABCFG_REG42C 0x42C // GPP0_SHADOW_PREF_MEM_LIMIT_UPPER
+#define FCH_ABCFG_REG430 0x430 // GPP0_SHADOW_IO_LIMIT_BASE_UPPER
+#define FCH_ABCFG_REG43C 0x43C // GPP0_SHADOW_BRIDGE_CONTROL
+#define FCH_ABCFG_REG444 0x444 // GPP1_SHADOW_COMMAND
+#define FCH_ABCFG_REG458 0x458 // GPP1_SHADOW_BUS_NUMBER
+#define FCH_ABCFG_REG45C 0x45C // GPP1_SHADOW_IO_LIMIT_BASE
+#define FCH_ABCFG_REG460 0x460 // GPP1_SHADOW_MEM_LIMIT_BASE
+#define FCH_ABCFG_REG464 0x464 // GPP1_SHADOW_PREF_MEM_LIMIT_BASE
+#define FCH_ABCFG_REG468 0x468 // GPP1_SHADOW_PREF_MEM_BASE_UPPER
+#define FCH_ABCFG_REG46C 0x46C // GPP1_SHADOW_PREF_MEM_LIMIT_UPPER
+#define FCH_ABCFG_REG470 0x470 // GPP1_SHADOW_IO_LIMIT_BASE_UPPER
+#define FCH_ABCFG_REG47C 0x47C // GPP1_SHADOW_BRIDGE_CONTROL
+#define FCH_ABCFG_REG484 0x484 // GPP2_SHADOW_COMMAND
+#define FCH_ABCFG_REG498 0x498 // GPP2_SHADOW_BUS_NUMBER
+#define FCH_ABCFG_REG49C 0x49C // GPP2_SHADOW_IO_LIMIT_BASE
+#define FCH_ABCFG_REG4A0 0x4A0 // GPP2_SHADOW_MEM_LIMIT_BASE
+#define FCH_ABCFG_REG4A4 0x4A4 // GPP2_SHADOW_PREF_MEM_LIMIT_BASE
+#define FCH_ABCFG_REG4A8 0x4A8 // GPP2_SHADOW_PREF_MEM_BASE_UPPER
+#define FCH_ABCFG_REG4AC 0x4AC // GPP2_SHADOW_PREF_MEM_LIMIT_UPPER
+#define FCH_ABCFG_REG4B0 0x4B0 // GPP2_SHADOW_IO_LIMIT_BASE_UPPER
+#define FCH_ABCFG_REG4BC 0x4BC // GPP2_SHADOW_BRIDGE_CONTROL
+#define FCH_ABCFG_REG4C4 0x4C4 // GPP3_SHADOW_COMMAND
+#define FCH_ABCFG_REG4D8 0x4D8 // GPP3_SHADOW_BUS_NUMBER
+#define FCH_ABCFG_REG4DC 0x4DC // GPP3_SHADOW_IO_LIMIT_BASE
+#define FCH_ABCFG_REG4E0 0x4E0 // GPP3_SHADOW_MEM_LIMIT_BASE
+#define FCH_ABCFG_REG4E4 0x4E4 // GPP3_SHADOW_PREF_MEM_LIMIT_BASE
+#define FCH_ABCFG_REG4E8 0x4E8 // GPP3_SHADOW_PREF_MEM_BASE_UPPER
+#define FCH_ABCFG_REG4EC 0x4EC // GPP3_SHADOW_PREF_MEM_LIMIT_UPPER
+#define FCH_ABCFG_REG4F0 0x4F0 // GPP3_SHADOW_IO_LIMIT_BASE_UPPER
+#define FCH_ABCFG_REG4FC 0x4FC // GPP3_SHADOW_BRIDGE_CONTROL
+#define FCH_ABCFG_REG10040 0x10040ul // AL_EVENTCNT0LO
+#define FCH_ABCFG_REG10044 0x10044ul // AL_EVENTCNT1LO
+#define FCH_ABCFG_REG10048 0x10048ul // AL_EVENTCNTSEL
+#define FCH_ABCFG_REG1004A 0x1004Aul // AL_EVENTCNT0HI
+#define FCH_ABCFG_REG1004B 0x1004Bul // AL_EVENTCNT1HI
+#define FCH_ABCFG_REG1004C 0x1004Cul // AL_EVENTCNTCTL
+#define FCH_ABCFG_REG10050 0x10050ul // MISCCTL_10050
+#define FCH_ABCFG_REG10054 0x10054ul // AL_ARB_CTL
+#define FCH_ABCFG_REG10056 0x10056ul // AL_CLK_CTL
+#define FCH_ABCFG_REG10058 0x10058ul // AL RAB CONTROL
+#define FCH_ABCFG_REG1005C 0x1005Cul // AL MLT CONTROL
+#define FCH_ABCFG_REG10060 0x10060ul // AL DMA PREFETCH ENABLE
+#define FCH_ABCFG_REG10064 0x10064ul // AL DMA PREFETCH FLUSH CONTROL
+#define FCH_ABCFG_REG10068 0x10068ul // AL PREFETCH LIMIT
+#define FCH_ABCFG_REG1006C 0x1006Cul // AL DMA PREFETCH CONTROL
+#define FCH_ABCFG_REG10070 0x10070ul // MISCCTL_10070
+#define FCH_ABCFG_REG10080 0x10080ul // CLKMUXSTATUS
+#define FCH_ABCFG_REG10090 0x10090ul // BIF CONTROL 0
+#define FCH_ABCFG_REG1009C 0x1009Cul // MISCCTL_1009C
+
+//
+// RCINDX_P Registers
+//
+#define FCH_RCINDXP_REG01 0x01 | RCINDXP << 29 // PCIEP_SCRATCH
+#define FCH_RCINDXP_REG02 0x02 | RCINDXP << 29 //
+#define FCH_RCINDXP_REG10 0x10 | RCINDXP << 29 //
+#define FCH_RCINDXP_REG20 0x20 | RCINDXP << 29 // PCIE_TX_CNTL
+#define FCH_RCINDXP_REG21 0x21 | RCINDXP << 29 // PCIE_TX_REQUESTER_ID
+#define FCH_RCINDXP_REG50 0x50 | RCINDXP << 29 // PCIE_P_PORT_LANE_STATUS
+#define FCH_RCINDXP_REG6A 0x6A | RCINDXP << 29 //
+#define FCH_RCINDXP_REG70 0x70 | RCINDXP << 29 // PCIE_RX_CNTL
+#define FCH_RCINDXP_REGA0 0xA0 | RCINDXP << 29 // PCIE_LC_CNTL
+#define FCH_RCINDXP_REGA1 0xA1 | RCINDXP << 29 // PCIE_LC_TRAINING_CNTL
+#define FCH_RCINDXP_REGA2 0xA2 | RCINDXP << 29 //
+#define FCH_RCINDXP_REGA4 0xA4 | RCINDXP << 29 //
+#define FCH_RCINDXP_REGA5 0xA5 | RCINDXP << 29 // PCIE_LC_STATE0
+#define FCH_RCINDXP_REGC0 0xC0 | RCINDXP << 29 //
+
+//
+// RCINDX_C Registers
+//
+#define FCH_RCINDXC_REG02 0x02 | RCINDXC << 29 // PCIE_HW_DEBUG
+#define FCH_RCINDXC_REG10 0x10 | RCINDXC << 29 // PCIE_CNTL
+#define FCH_RCINDXC_REG40 0x40 | RCINDXC << 29 // PCIE_P_CNTL
+#define FCH_RCINDXC_REG65 0x65 | RCINDXC << 29 // PCIE_P_PAD_FORCE_DIS
+#define FCH_RCINDXC_REGC0 0xC0 | RCINDXC << 29 // PCIE_STRAP_MISC
+#define FCH_RCINDXC_REGC1 0xC1 | RCINDXC << 29 // PCIE_STRAP_MISC2
+
+
+//
+// AXINDC Registers
+//
+#define FCH_AX_INDXC_REG02 0x02 // PCIEP_HW_DEBUG
+#define FCH_AX_INDXC_REG10 0x10
+#define FCH_AX_INDXC_REG30 0x30
+#define FCH_AX_DATAC_REG34 0x34
+#define FCH_AX_INDXP_REG38 0x38
+#define FCH_AX_DATAP_REG3C 0x3C
+#define FCH_AX_INDXC_REG40 0x40 | AXINDC << 29
+#define FCH_AX_INDXC_REGA4 0xA4 | AXINDC << 29
+
+#define FCH_AX_INDXP_REG02 0x02 | AXINDP << 29
+#define FCH_AX_INDXP_REGA0 0xA0 | AXINDP << 29
+#define FCH_AX_INDXP_REGA4 0xA4 | AXINDP << 29
+#define FCH_AX_INDXP_REGB1 0xB1 | AXINDP << 29
+
+#define FCH_AX_CFG_REG68 0x68 | AXCFG << 29
+#define FCH_AX_CFG_REG88 0x88 | AXCFG << 29
+
+#define FCH_AB_REG04 0x04
+#define FCH_AB_REG40 0x40
+
+//Sata Port Configuration
+#define SIX_PORTS 0
+#define FOUR_PORTS 1
+
+#define SATA_EFUSE_LOCATION 0x10 // EFUSE bit 133
+#define SATA_DH_EFUSE_LOCATION 0x11 // EFUSE bit 138
+#define SATA_FIS_BASE_EFUSE_LOC 0x15 // EFUSE bit 169
+#define SATA_EFUSE_BIT 0x20 //
+#define SATA_DH_EFUSE_BIT 0x04 //
+#define FCH_SATA_REG00 0x000 // Vendor ID - R- 16 bits
+#define FCH_SATA_REG02 0x002 // Device ID - RW -16 bits
+#define FCH_SATA_REG04 0x004 // PCI Command - RW - 16 bits
+#define FCH_SATA_REG06 0x006 // PCI Status - RW - 16 bits
+#define FCH_SATA_REG08 0x008 // Revision ID/PCI Class Code - R - 32 bits - Offset: 08
+#define FCH_SATA_REG0C 0x00C // Cache Line Size - R/W - 8bits
+#define FCH_SATA_REG0D 0x00D // Latency Timer - RW - 8 bits
+#define FCH_SATA_REG0E 0x00E // Header Type - R - 8 bits
+#define FCH_SATA_REG0F 0x00F // BIST - R - 8 bits
+#define FCH_SATA_REG10 0x010 // Base Address Register 0 - RW - 32 bits
+#define FCH_SATA_REG14 0x014 // Base Address Register 1 - RW- 32 bits
+#define FCH_SATA_REG18 0x018 // Base Address Register 2 - RW - 32 bits
+#define FCH_SATA_REG1C 0x01C // Base Address Register 3 - RW - 32 bits
+#define FCH_SATA_REG20 0x020 // Base Address Register 4 - RW - 32 bits
+#define FCH_SATA_REG24 0x024 // Base Address Register 5 - RW - 32 bits
+#define FCH_SATA_REG2C 0x02C // Subsystem Vendor ID - R - 16 bits
+#define FCH_SATA_REG2D 0x02D // Subsystem ID - R - 16 bits
+#define FCH_SATA_REG30 0x030 // Expansion ROM Base Address - 32 bits
+#define FCH_SATA_REG34 0x034 // Capabilities Pointer - R - 32 bits
+#define FCH_SATA_REG3C 0x03C // Interrupt Line - RW - 8 bits
+#define FCH_SATA_REG3D 0x03D // Interrupt Pin - R - 8 bits
+#define FCH_SATA_REG3E 0x03E // Min Grant - R - 8 bits
+#define FCH_SATA_REG3F 0x03F // Max Latency - R - 8 bits
+#define FCH_SATA_REG40 0x040 // Configuration - RW - 32 bits
+#define FCH_SATA_REG44 0x044 // Software Data Register - RW - 32 bits
+#define FCH_SATA_REG48 0x048
+#define FCH_SATA_REG4C 0x04C
+#define FCH_SATA_REG50 0x050 // Message Capability - R - 16 bits
+#define FCH_SATA_REG52 0x052 // Message Control - R/W - 16 bits
+#define FCH_SATA_REG54 0x054 // Message Address - R/W - 32 bits
+#define FCH_SATA_REG58 0x058 // Message Data - R/W - 16 bits
+#define FCH_SATA_REG5C 0x05C // RAMBIST Control Register - R/W - 8 bits
+#define FCH_SATA_REG5D 0x05D // RAMBIST Status0 Register - R - 8 bits
+#define FCH_SATA_REG5E 0x05E // RAMBIST Status1 Register - R - 8 bits
+#define FCH_SATA_REG60 0x060 // Power Management Capabilities - R - 32 bits
+#define FCH_SATA_REG64 0x064 // Power Management Control + Status - RW - 32 bits
+#define FCH_SATA_REG68 0x068 // MSI Program - R/W - 8 bits
+#define FCH_SATA_REG69 0x069 // PCI Burst Timer - R/W - 8 bits
+#define FCH_SATA_REG70 0x070 // PCI Bus Master - IDE0 - RW - 32 bits
+#define FCH_SATA_REG74 0x074 // PRD Table Address - IDE0 - RW - 32 bits
+#define FCH_SATA_REG78 0x078 // PCI Bus Master - IDE1 - RW - 32 bits
+#define FCH_SATA_REG7C 0x07C // PRD Table Address - IDE1 - RW - 32 bits
+#define FCH_SATA_REG80 0x080 // Data Transfer Mode - IDE0 - RW - 32 bits
+#define FCH_SATA_REG84 0x084 // Data Transfer Mode - IDE1 - RW - 32 bits
+#define FCH_SATA_REG86 0x086 // PY Global Control
+#define FCH_SATA_REG87 0x087
+#define FCH_SATA_REG88 0x088 // PHY Port0 Control - Port0 PY fine tune (0:23)
+#define FCH_SATA_REG8A 0x08A
+#define FCH_SATA_REG8C 0x08C // PHY Port1 Control - Port0 PY fine tune (0:23)
+#define FCH_SATA_REG8E 0x08E
+#define FCH_SATA_REG90 0x090 // PHY Port2 Control - Port0 PY fine tune (0:23)
+#define FCH_SATA_REG92 0x092
+#define FCH_SATA_REG94 0x094 // PHY Port3 Control - Port0 PY fine tune (0:23)
+#define FCH_SATA_REG96 0x096
+#define FCH_SATA_REG98 0x098 // EEPROM Memory Address - Command + Status - RW - 32 bits
+#define FCH_SATA_REG9C 0x09C // EEPROM Memory Data - RW - 32 bits
+#define FCH_SATA_REGA0 0x0A0 //
+#define FCH_SATA_REGA4 0x0A4 //
+#define FCH_SATA_REGA5 0x0A5 //;
+#define FCH_SATA_REGA8 0x0A8 //
+#define FCH_SATA_REGAD 0x0AD //;
+#define FCH_SATA_REGB0 0x0B0 // IDE1 Task File Configuration + Status - RW - 32 bits
+#define FCH_SATA_REGB5 0x0B5 //;
+#define FCH_SATA_REGBD 0x0BD //;
+#define FCH_SATA_REGC0 0x0C0 // BA5 Indirect Address - RW - 32 bits
+#define FCH_SATA_REGC4 0x0C4 // BA5 Indirect Access - RW - 32 bits
+
+#define FCH_SATA_BAR5_REG00 0x000 // PCI Bus Master - IDE0 - RW - 32 bits
+#define FCH_SATA_BAR5_REG04 0x004 // PRD Table Address - IDE0 - RW - 32 bits
+#define FCH_SATA_BAR5_REG08 0x008 // PCI Bus Master - IDE1 - RW - 32 bits
+#define FCH_SATA_BAR5_REG0C 0x00C // PRD Table Address - IDE1 - RW - 32 bits
+#define FCH_SATA_BAR5_REG10 0x010 // PCI Bus Master2 - IDE0 - RW - 32 bits
+#define FCH_SATA_BAR5_REG1C 0x01C
+#define FCH_SATA_BAR5_REG18 0x018 // PCI Bus Master2 - IDE1 - RW - 32 bits
+#define FCH_SATA_BAR5_REG20 0x020 // PRD Address - IDE0 - RW - 32 bits
+#define FCH_SATA_BAR5_REG24 0x024 // PCI Bus Master Byte Count - IDE0- RW - 32 bits
+#define FCH_SATA_BAR5_REG28 0x028 // PRD Address - IDE1 - RW - 32 bits
+#define FCH_SATA_BAR5_REG2C 0x02C // PCI Bus Master Byte Count - IDE1 - RW - 32 bits
+#define FCH_SATA_BAR5_REG40 0x040 // FIFO Valid Byte Count and Control - IDE0 - RW - 32 bits
+#define FCH_SATA_BAR5_REG44 0x044 // FIFO Valid Byte Count and Control - IDE1 - RW - 32 bits
+#define FCH_SATA_BAR5_REG48 0x048 // System Configuration Status - Command - RW - 32 bits
+#define FCH_SATA_BAR5_REG4C 0x04C // System Software Data Register - RW - 32 bits
+#define FCH_SATA_BAR5_REG50 0x050 // FLAS Memory Address - Command + Status - RW - 32 bits
+#define FCH_SATA_BAR5_REG54 0x054 // FLAS Memory Data - RW - 32 bits
+#define FCH_SATA_BAR5_REG58 0x058 // EEPROM Memory Address - Command + Status - RW - 32 bits
+#define FCH_SATA_BAR5_REG5C 0x05C // EEPROM Memory Data - RW - 32 bits
+#define FCH_SATA_BAR5_REG60 0x060 // FIFO Port - IDE0 - RW - 32 bits
+#define FCH_SATA_BAR5_REG68 0x068 // FIFO Pointers1- IDE0 - RW - 32 bits
+#define FCH_SATA_BAR5_REG6C 0x06C // FIFO Pointers2- IDE0 - RW - 32 bits
+#define FCH_SATA_BAR5_REG70 0x070 // FIFO Port - IDE1- RW - 32 bits
+#define FCH_SATA_BAR5_REG78 0x078 // FIFO Pointers1- IDE1- RW - 32 bits
+#define FCH_SATA_BAR5_REG7C 0x07C // FIFO Pointers2- IDE1- RW - 32 bits
+#define FCH_SATA_BAR5_REG80 0x080 // IDE0 Task File Register 0- RW - 32 bits
+#define FCH_SATA_BAR5_REG84 0x084 // IDE0 Task File Register 1- RW - 32 bits
+#define FCH_SATA_BAR5_REG88 0x088 // IDE0 Task File Register 2- RW - 32 bits
+#define FCH_SATA_BAR5_REG8C 0x08C // IDE0 Read Data - RW - 32 bits
+#define FCH_SATA_BAR5_REG90 0x090 // IDE0 Task File Register 0 - Command Buffering - RW - 32 bits
+#define FCH_SATA_BAR5_REG94 0x094 // IDE0 Task File Register 1 - Command Buffering - RW - 32 bits
+#define FCH_SATA_BAR5_REG9C 0x09C // IDE0 Virtual DMA/PIO Read Byte Count - RW - 32 bits
+#define FCH_SATA_BAR5_REGA0 0x0A0 // IDE0 Task File Configuration + Status - RW - 32 bits
+#define FCH_SATA_BAR5_REGB4 0x0B4 // Data Transfer Mode -IDE0 - RW - 32 bits
+#define FCH_SATA_BAR5_REGC0 0x0C0 // IDE1 Task File Register 0 - RW - 32 bits
+#define FCH_SATA_BAR5_REGC4 0x0C4 // IDE1 Task File Register 1 - RW - 32 bits
+#define FCH_SATA_BAR5_REGC8 0x0C8 // IDE1 Task File Register 2 - RW - 32 bits
+#define FCH_SATA_BAR5_REGCC 0x0CC // Read/Write Data - RW - 32 bits
+#define FCH_SATA_BAR5_REGD0 0x0D0 // IDE1 Task File Register 0 - Command Buffering - RW - 32 bits
+#define FCH_SATA_BAR5_REGD4 0x0D4 // IDE1 Task File Register 1 - Command Buffering - RW - 32 bits
+#define FCH_SATA_BAR5_REGDC 0x0DC // IDE1 Virtual DMA/PIO Read Byte Count - RW - 32 bits
+#define FCH_SATA_BAR5_REGE0 0x0E0 // IDE1 Task File Configuration + Status - RW - 32 bits
+#define FCH_SATA_BAR5_REGF4 0x0F4 // Data Transfer Mode - IDE1 - RW - 32 bits
+#define FCH_SATA_BAR5_REGF8 0x0F8 // PORT Configuration
+#define FCH_SATA_BAR5_REGFC 0x0FC
+#define FCH_SATA_BAR5_REG100 0x0100 // Serial ATA SControl - RW - 32 bits - [Offset: 100h (channel 1) / 180
+#define FCH_SATA_BAR5_REG104 0x0104 // Serial ATA Sstatus - RW - 32 bits - [Offset: 104h (channel 1) / 184h (cannel
+#define FCH_SATA_BAR5_REG108 0x0108 // Serial ATA Serror - RW - 32 bits - [Offset: 108h (channel 1) / 188h (cannel
+#define FCH_SATA_BAR5_REG10C 0x010C // Serial ATA Sdevice - RW - 32 bits - [Offset: 10Ch (channel 1) / 18Ch (cannel
+#define FCH_SATA_BAR5_REG144 0x0144 // Serial ATA PY Configuration - RW - 32 bits
+#define FCH_SATA_BAR5_REG148 0x0148 // SIEN - RW - 32 bits - [Offset: 148 (channel 1) / 1C8 (cannel 2)]
+#define FCH_SATA_BAR5_REG14C 0x014C // SFISCfg - RW - 32 bits - [Offset: 14C (channel 1) / 1CC (cannel 2)]
+#define FCH_SATA_BAR5_REG120 0x0120 //
+#define FCH_SATA_BAR5_REG128 0x0128 // Port Serial ATA Status
+#define FCH_SATA_BAR5_REG12C 0x012C // Port Serial ATA Control
+#define FCH_SATA_BAR5_REG130 0x0130
+#define FCH_SATA_BAR5_REG1B0 0x01B0
+#define FCH_SATA_BAR5_REG230 0x0230
+#define FCH_SATA_BAR5_REG2B0 0x02B0
+#define FCH_SATA_BAR5_REG330 0x0330
+#define FCH_SATA_BAR5_REG3B0 0x03B0
+#define FCH_SATA_BAR5_REG430 0x0430
+#define FCH_SATA_BAR5_REG4B0 0x04B0
+
+
+// USB ports
+#define NUM_USB1_PORTS 5
+#define NUM_USB2_PORTS 5
+#define NUM_USB3_PORTS 4
+#define NUM_USB4_PORTS 2
+#define NUM_XHC0_PORTS 2
+#define NUM_XHC1_PORTS 2
+
+
+//
+// USB OHCI Device 0x7807
+// Device 18 (0x11)/Device 19 (0x12)/Device 22 (0x16) Func 0
+// Device 20 (0x14) Func 5 (FL) 0x7809
+//
+#define FCH_OHCI_REG00 0x00 // Device/Vendor ID - R (0x43971002ul)
+#define FCH_OHCI_REG04 0x04 // Command - RW
+#define FCH_OHCI_REG06 0x06 // Status - R
+#define FCH_OHCI_REG08 0x08 // Revision ID/Class Code - R
+#define FCH_OHCI_REG0C 0x0C // Miscellaneous - RW
+#define FCH_OHCI_REG10 0x10 // Bar_OCI - RW
+#define FCH_OHCI_REG2C 0x2C // Subsystem Vendor ID/ Subsystem ID - RW
+#define FCH_OHCI_REG34 0x34 // Capability Pointer - R
+#define FCH_OHCI_REG3C 0x3C // Interrupt Line - RW
+#define FCH_OHCI_REG3D 0x3D // Interrupt Line - RW
+#define FCH_OHCI_REG40 0x40 // Config Timers - RW
+#define FCH_OHCI_REG42 0x42 // Port Disable Control - RW (800)
+#define FCH_OHCI_REG46 0x46 // USB PHY Battery Charger - RW (800)
+#define FCH_OHCI_REG48 0x48 // Port Force Reset - RW (800)
+#define FCH_OHCI_REG4C 0x4C // MSI - RW (800)
+#define FCH_OHCI_REG50 0x50 // Misc Control - RW
+#define FCH_OHCI_REG51 0x51
+#define FCH_OHCI_REG52 0x52
+#define FCH_OHCI_REG58 0x58 // Over Current Control - RW
+#define FCH_OHCI_REG5C 0x5C // Over Current Control - RW
+#define FCH_OHCI_REG60 0x60 // Serial Bus Release Number - RW
+#define FCH_OHCI_REG68 0x68 // Over Current PME Enable - RW
+#define FCH_OHCI_REG74 0x74 // Target Timeout Control - RW
+#define FCH_OHCI_REG80 0x80 //
+#define FCH_OHCI_REGD0 0x0D0 // MSI Control - RW
+#define FCH_OHCI_REGD4 0x0D4 // MSI Address - RW
+#define FCH_OHCI_REGD8 0x0D8 // MSI Data - RW
+#define FCH_OHCI_REGE4 0x0E4 // HT MSI Support
+#define FCH_OHCI_REGF0 0x0F0 // Function Level Reset Capability
+#define FCH_OHCI_REGF4 0x0F4 // Function Level Reset Control
+
+#define FCH_OHCI_BAR_REG00 0x00 // cRevision - R
+#define FCH_OHCI_BAR_REG04 0x04 // cControl
+#define FCH_OHCI_BAR_REG08 0x08 // cCommandStatus
+#define FCH_OHCI_BAR_REG0C 0x0C // cInterruptStatus RW
+#define FCH_OHCI_BAR_REG10 0x10 // cInterruptEnable
+#define FCH_OHCI_BAR_REG14 0x14 // cInterruptDisable
+#define FCH_OHCI_BAR_REG18 0x18 // HcCCA
+#define FCH_OHCI_BAR_REG1C 0x1C // cPeriodCurrentED
+#define FCH_OHCI_BAR_REG20 0x20 // HcControleadED
+#define FCH_OHCI_BAR_REG24 0x24 // cControlCurrentED RW
+#define FCH_OHCI_BAR_REG28 0x28 // HcBulkeadED
+#define FCH_OHCI_BAR_REG2C 0x2C // cBulkCurrentED- RW
+#define FCH_OHCI_BAR_REG30 0x30 // HcDoneead
+#define FCH_OHCI_BAR_REG34 0x34 // cFmInterval
+#define FCH_OHCI_BAR_REG38 0x38 // cFmRemaining
+#define FCH_OHCI_BAR_REG3C 0x3C // cFmNumber
+#define FCH_OHCI_BAR_REG40 0x40 // cPeriodicStart
+#define FCH_OHCI_BAR_REG44 0x44 // HcLSThresold
+#define FCH_OHCI_BAR_REG48 0x48 // HcRDescriptorA
+#define FCH_OHCI_BAR_REG4C 0x4C // HcRDescriptorB
+#define FCH_OHCI_BAR_REG50 0x50 // HcRStatus
+#define FCH_OHCI_BAR_REG54 0x54 // HcRhPortStatus (800)
+#define FCH_OHCI_BAR_REG58 0x58 // HcRhPortStatus NPD (800)
+#define FCH_OHCI_BAR_REGF0 0xF0 // OHCI Loop Back feature Support (800)
+
+#define FCH_OHCI_PORTSC_CCS 0x1 // HcRhPortStatus
+#define FCH_OHCI_PORTSC_PES 0x2 // HcRhPortStatus
+#define FCH_OHCI_PORTSC_PSS 0x4 // HcRhPortStatus
+#define FCH_OHCI_PORTSC_PPS 0x100 // HcRhPortStatus
+#define FCH_OHCI_PORTSC_LSDA 0x200 // HcRhPortStatus
+#define FCH_OHCI_PORTSC_PRS 0x10 // HcRhPortStatus
+
+//
+// USB EHCI Device 0x7808
+// Device 18 (0x11)/Device 19 (0x12)/Device 22 (0x16) Func 2
+//
+#define FCH_EHCI_REG00 0x00 // DEVICE/VENDOR ID - R
+#define FCH_EHCI_REG04 0x04 // Command - RW
+#define FCH_EHCI_REG06 0x06 // Status - R
+#define FCH_EHCI_REG08 0x08 // Revision ID/Class Code - R
+#define FCH_EHCI_REG0C 0x0C // Miscellaneous - RW
+#define FCH_EHCI_REG10 0x10 // BAR - RW
+#define FCH_EHCI_REG2C 0x2C // Subsystem ID/Subsystem Vendor ID - RW
+#define FCH_EHCI_REG34 0x34 // Capability Pointer - R
+#define FCH_EHCI_REG3C 0x3C // Interrupt Line - RW
+#define FCH_EHCI_REG3D 0x3D // Interrupt Line - RW
+#define FCH_EHCI_REG40 0x40 // Config Timers - RW
+#define FCH_EHCI_REG4C 0x4C // MSI - RW
+#define FCH_EHCI_REG50 0x50 // EHCI Misc Control - RW
+#define FCH_EHCI_REG54 0x54 // EHCI Misc Control - RW
+#define FCH_EHCI_REG60 0x60 // SBRN - R
+#define FCH_EHCI_REG61 0x61 // FLADJ - RW
+#define FCH_EHCI_REG62 0x62 // PORTWAKECAP - RW
+#define FCH_EHCI_REG64 0x64 // Misc Control 2 - RW
+#define FCH_EHCI_REG70 0x70 // Over Current Control - RW
+#define FCH_EHCI_REG74 0x74 // EHCI Misc Control2 - RW
+#define FCH_EHCI_REG84 0x84 // HUB Configure 1 - RW
+#define FCH_EHCI_REG88 0x88 // - RW
+#define FCH_EHCI_REG90 0x90 // HUB Configure 4 - RW
+#define FCH_EHCI_REGA0 0xA0 //
+#define FCH_EHCI_REGA4 0xA4 //
+#define FCH_EHCI_REGC0 0x0C0 // PME control - RW (800)
+#define FCH_EHCI_REGC4 0x0C4 // PME Data /Status - RW (800)
+#define FCH_EHCI_REGD0 0x0D0 // MSI Control - RW
+#define FCH_EHCI_REGD4 0x0D4 // MSI Address - RW
+#define FCH_EHCI_REGD8 0x0D8 // MSI Data - RW
+#define FCH_EHCI_REGE4 0x0E4 // EHCI Debug Port Support - RW (800)
+#define FCH_EHCI_REGF0 0x0F0 // Function Level Reset Capability - R (800)
+#define FCH_EHCI_REGF4 0x0F4 // Function Level Reset Capability - R (800)
+
+#define FCH_EHCI_BAR_REG00 0x00 // CAPLENGT - R
+#define FCH_EHCI_BAR_REG02 0x002 // CIVERSION- R
+#define FCH_EHCI_BAR_REG04 0x004 // CSPARAMS - R
+#define FCH_EHCI_BAR_REG08 0x008 // CCPARAMS - R
+#define FCH_EHCI_BAR_REG0C 0x00C // CSP-PORTROUTE - R
+
+#define FCH_EHCI_BAR_REG20 0x020 // USBCMD - RW - 32 bits
+#define FCH_EHCI_BAR_REG24 0x024 // USBSTS - RW - 32 bits
+#define FCH_EHCI_BAR_REG28 0x028 // USBINTR -RW - 32 bits
+#define FCH_EHCI_BAR_REG2C 0x02C // FRINDEX -RW - 32 bits
+#define FCH_EHCI_BAR_REG30 0x030 // CTRLDSSEGMENT -RW - 32 bits
+#define FCH_EHCI_BAR_REG34 0x034 // PERIODICLISTBASE -RW - 32 bits
+#define FCH_EHCI_BAR_REG38 0x038 // ASYNCLISTADDR -RW - 32 bits
+#define FCH_EHCI_BAR_REG60 0x060 // CONFIGFLAG -RW - 32 bits
+#define FCH_EHCI_BAR_REG64 0x064 // PORTSC (1-N_PORTS) -RW - 32 bits
+#define FCH_EHCI_BAR_REGA0 0x0A0 // DebugPort MISC Control - RW - 32 bits (800)
+#define FCH_EHCI_BAR_REGA4 0x0A4 // Packet Buffer Threshold Values - RW - 32 bits
+#define FCH_EHCI_BAR_REGA8 0x0A8 // USB PHY Status 0 - R
+#define FCH_EHCI_BAR_REGAC 0x0AC // USB PHY Status 1 - R
+#define FCH_EHCI_BAR_REGB0 0x0B0 // USB PHY Status 2 - R
+#define FCH_EHCI_BAR_REGB4 0x0B4 // UTMI Control - RW (800)
+#define FCH_EHCI_BAR_REGB8 0x0B8 // Loopback Test
+#define FCH_EHCI_BAR_REGBC 0x0BC // EHCI MISC Control
+#define FCH_EHCI_BAR_REGC0 0x0C0 // USB PHY Calibration
+#define FCH_EHCI_BAR_REGC4 0x0C4 // USB Common PHY Control
+#define FCH_EHCI_BAR_REGC8 0x0C8 // EHCI Debug Purpose
+#define FCH_EHCI_BAR_REGCC 0x0CC // Ehci Spare 1 (800) **
+#define FCH_EHCI_BAR_REGD0 0x0D0
+#define FCH_EHCI_BAR_REGD4 0x0D4
+#define FCH_EHCI_BAR_REGDC 0x0DC
+#define FCH_EHCI_BAR_REG100 0x100 // USB debug port
+
+//
+// USB XHCI Device 0x7812/0x7814
+// Device 16 (0x10) Func 0/1
+//
+#define FCH_XHCI_REG00 0x00 // DEVICE/VENDOR ID - R
+#define FCH_XHCI_REG04 0x04 // Command - RW
+#define FCH_XHCI_REG10 0x10 // Bar0
+#define FCH_XHCI_REG2C 0x2C // Sub System ID
+#define FCH_XHCI_REG40 0x40 // Index0
+#define FCH_XHCI_REG44 0x44 // Data0
+#define FCH_XHCI_REG48 0x48 // Index1
+#define FCH_XHCI_REG4C 0x4C // Data0
+#define FCH_XHCI_REG54 0x54 // PME Control/Status
+#define XHCI_EFUSE_LOCATION 0x18 // EFUSE bit 192, 193
+
+#define FCH_XHCI_BAR_REG420 0x420 // Port Status and Control
+#define FCH_XHCI_PORTSC_CCS 0x1 // Port Status and Control
+#define FCH_XHCI_PORTSC_PED 0x2 // Port Status and Control
+#define FCH_XHCI_PORTSC_PLS 0x1E0 // Port Status and Control
+#define FCH_XHCI_PORTSC_SPEED 0x3C00 // Port Status and Control
+#define FCH_XHCI_PORTSC_PR 0x10 // Port Status and Control
+
+//
+// FCH CFG device 0x780B
+// Device 20 (0x14) Func 0
+//
+#define FCH_CFG_REG00 0x000 // VendorID - R
+#define FCH_CFG_REG02 0x002 // DeviceID - R
+#define FCH_CFG_REG04 0x004 // Command- RW
+#define FCH_CFG_REG05 0x005 // Command- RW
+#define FCH_CFG_REG06 0x006 // STATUS- RW
+#define FCH_CFG_REG08 0x008 // Revision ID/Class Code- R
+#define FCH_CFG_REG0A 0x00A //
+#define FCH_CFG_REG0B 0x00B //
+#define FCH_CFG_REG0C 0x00C // Cache Line Size- R
+#define FCH_CFG_REG0D 0x00D // Latency Timer- R
+#define FCH_CFG_REG0E 0x00E // Header Type- R
+#define FCH_CFG_REG0F 0x00F // BIST- R
+#define FCH_CFG_REG10 0x010 // Base Address 0- R
+#define FCH_CFG_REG11 0x011 //;
+#define FCH_CFG_REG12 0x012 //;
+#define FCH_CFG_REG13 0x013 //;
+#define FCH_CFG_REG14 0x014 // Base Address 1- R
+#define FCH_CFG_REG18 0x018 // Base Address 2- R
+#define FCH_CFG_REG1C 0x01C // Base Address 3- R
+#define FCH_CFG_REG20 0x020 // Base Address 4- R
+#define FCH_CFG_REG24 0x024 // Base Address 5- R
+#define FCH_CFG_REG28 0x028 // Cardbus CIS Pointer- R
+#define FCH_CFG_REG2C 0x02C // Subsystem Vendor ID- W
+#define FCH_CFG_REG2E 0x02E // Subsystem ID- W
+#define FCH_CFG_REG30 0x030 // Expansion ROM Base Address - R
+#define FCH_CFG_REG34 0x034 // Capability Pointer - R (800) default changed as 0x00
+#define FCH_CFG_REG3C 0x03C // Interrupt Line - R
+#define FCH_CFG_REG3D 0x03D // Interrupt Pin - R
+#define FCH_CFG_REG3E 0x03E // Min_Gnt - R
+#define FCH_CFG_REG3F 0x03F // Max_Lat - R
+#define FCH_CFG_REG90 0x090 // Smbus Base Address - R
+#define FCH_CFG_REG9C 0x09C // SBResourceMMIO_BASE
+
+//
+// FCH SATA IDE device
+// Device 20 (0x14) Func 1
+//
+
+#define FCH_IDE_REG00 0x00 // Vendor ID
+#define FCH_IDE_REG02 0x02 // Device ID
+#define FCH_IDE_REG04 0x04 // Command
+#define FCH_IDE_REG06 0x06 // Status
+#define FCH_IDE_REG08 0x08 // Revision ID/Class Code
+#define FCH_IDE_REG09 0x09 // Class Code
+#define FCH_IDE_REG2C 0x2C // Subsystem ID and Subsystem Vendor ID
+#define FCH_IDE_REG40 0x40 // Configuration - RW - 32 bits
+#define FCH_IDE_REG34 0x34
+#define FCH_IDE_REG62 0x62 // IDE Internal Control
+#define FCH_IDE_REG63 0x63 // IDE Internal Control
+//
+// FCH AZALIA device 0x780D
+// Device 20 (0x14) Func 2
+//
+#define ATI_AZALIA_ExtBlk_Addr 0x0F8
+#define ATI_AZALIA_ExtBlk_DATA 0x0FC
+
+#define FCH_AZ_REG00 0x00 // Vendor ID - R
+#define FCH_AZ_REG02 0x02 // Device ID - R/W
+#define FCH_AZ_REG04 0x04 // PCI Command
+#define FCH_AZ_REG06 0x06 // PCI Status - R/W
+#define FCH_AZ_REG08 0x08 // Revision ID
+#define FCH_AZ_REG09 0x09 // Programming Interface
+#define FCH_AZ_REG0A 0x0A // Sub Class Code
+#define FCH_AZ_REG0B 0x0B // Base Class Code
+#define FCH_AZ_REG0C 0x0C // Cache Line Size - R/W
+#define FCH_AZ_REG0D 0x0D // Latency Timer
+#define FCH_AZ_REG0E 0x0E // Header Type
+#define FCH_AZ_REG0F 0x0F // BIST
+#define FCH_AZ_REG10 0x10 // Lower Base Address Register
+#define FCH_AZ_REG14 0x14 // Upper Base Address Register
+#define FCH_AZ_REG2C 0x2C // Subsystem Vendor ID
+#define FCH_AZ_REG2D 0x2D // Subsystem ID
+#define FCH_AZ_REG34 0x34 // Capabilities Pointer
+#define FCH_AZ_REG3C 0x3C // Interrupt Line
+#define FCH_AZ_REG3D 0x3D // Interrupt Pin
+#define FCH_AZ_REG3E 0x3E // Minimum Grant
+#define FCH_AZ_REG3F 0x3F // Maximum Latency
+#define FCH_AZ_REG40 0x40 // Misc Control 1
+#define FCH_AZ_REG42 0x42 // Misc Control 2 Register
+#define FCH_AZ_REG43 0x43 // Misc Control 3 Register
+#define FCH_AZ_REG44 0x44 // Interrupt Pin Control Register
+#define FCH_AZ_REG46 0x46 // Debug Control Register
+#define FCH_AZ_REG4C 0x4C
+#define FCH_AZ_REG50 0x50 // Power Management Capability ID
+#define FCH_AZ_REG52 0x52 // Power Management Capabilities
+#define FCH_AZ_REG54 0x54 // Power Management Control/Status
+#define FCH_AZ_REG60 0x60 // MSI Capability ID
+#define FCH_AZ_REG62 0x62 // MSI Message Control
+#define FCH_AZ_REG64 0x64 // MSI Message Lower Address
+#define FCH_AZ_REG68 0x68 // MSI Message Upper Address
+#define FCH_AZ_REG6C 0x6C // MSI Message Data
+
+#define FCH_AZ_BAR_REG00 0x00 // Global Capabilities - R
+#define FCH_AZ_BAR_REG02 0x02 // Minor Version - R
+#define FCH_AZ_BAR_REG03 0x03 // Major Version - R
+#define FCH_AZ_BAR_REG04 0x04 // Output Payload Capability - R
+#define FCH_AZ_BAR_REG06 0x06 // Input Payload Capability - R
+#define FCH_AZ_BAR_REG08 0x08 // Global Control - R/W
+#define FCH_AZ_BAR_REG0C 0x0C // Wake Enable - R/W
+#define FCH_AZ_BAR_REG0E 0x0E // State Change Status - R/W
+#define FCH_AZ_BAR_REG10 0x10 // Global Status - R/W
+#define FCH_AZ_BAR_REG18 0x18 // Output Stream Payload Capability - R
+#define FCH_AZ_BAR_REG1A 0x1A // Input Stream Payload Capability - R
+#define FCH_AZ_BAR_REG20 0x20 // Interrupt Control - R/W
+#define FCH_AZ_BAR_REG24 0x24 // Interrupt Status - R/W
+#define FCH_AZ_BAR_REG30 0x30 // Wall Clock Counter - R
+#define FCH_AZ_BAR_REG38 0x38 // Stream Synchronization - R/W
+#define FCH_AZ_BAR_REG40 0x40 // CORB Lower Base Address - R/W
+#define FCH_AZ_BAR_REG44 0x44 // CORB Upper Base Address - RW
+#define FCH_AZ_BAR_REG48 0x48 // CORB Write Pointer - R/W
+#define FCH_AZ_BAR_REG4A 0x4A // CORB Read Pointer - R/W
+#define FCH_AZ_BAR_REG4C 0x4C // CORB Control - R/W
+#define FCH_AZ_BAR_REG4D 0x4D // CORB Status - R/W
+#define FCH_AZ_BAR_REG4E 0x4E // CORB Size - R/W
+#define FCH_AZ_BAR_REG50 0x50 // RIRB Lower Base Address - RW
+#define FCH_AZ_BAR_REG54 0x54 // RIRB Upper Address - RW
+#define FCH_AZ_BAR_REG58 0x58 // RIRB Write Pointer - RW
+#define FCH_AZ_BAR_REG5A 0x5A // RIRB Response Interrupt Count - R/W
+#define FCH_AZ_BAR_REG5C 0x5C // RIRB Control - R/W
+#define FCH_AZ_BAR_REG5D 0x5D // RIRB Status - R/W
+#define FCH_AZ_BAR_REG5E 0x5E // RIRB Size - R/W
+#define FCH_AZ_BAR_REG60 0x60 // Immediate Command Output Interface - R/W
+#define FCH_AZ_BAR_REG64 0x64 // Immediate Command Input Interface - R/W
+#define FCH_AZ_BAR_REG68 0x68 // Immediate Command Input Interface - R/W
+#define FCH_AZ_BAR_REG70 0x70 // DMA Position Lower Base Address - R/W
+#define FCH_AZ_BAR_REG74 0x74 // DMA Position Upper Base Address - R/W
+#define FCH_AZ_BAR_REG2030 0x2030 // Wall Clock Counter Alias - R
+
+//
+// FCH LPC Device 0x780E
+// Device 20 (0x14) Func 3
+//
+#define FCH_LPC_REG00 0x00 // VID- R
+#define FCH_LPC_REG02 0x02 // DID- R
+#define FCH_LPC_REG04 0x04 // CMD- RW
+#define FCH_LPC_REG06 0x06 // STATUS- RW
+#define FCH_LPC_REG08 0x08 // Revision ID/Class Code - R
+#define FCH_LPC_REG0C 0x0C // Cache Line Size - R
+#define FCH_LPC_REG0D 0x0D // Latency Timer - R
+#define FCH_LPC_REG0E 0x0E // Header Type - R
+#define FCH_LPC_REG0F 0x0F // BIST- R
+#define FCH_LPC_REG10 0x10 // Base Address Reg 0- RW*
+#define FCH_LPC_REG2C 0x2C // Subsystem ID & Subsystem Vendor ID - Wo/Ro
+#define FCH_LPC_REG34 0x34 // Capabilities Pointer - Ro
+#define FCH_LPC_REG40 0x40 // PCI Control - RW
+#define FCH_LPC_REG44 0x44 // IO Port Decode Enable Register 1- RW
+#define FCH_LPC_REG45 0x45 // IO Port Decode Enable Register 2- RW
+#define FCH_LPC_REG46 0x46 // IO Port Decode Enable Register 3- RW
+#define FCH_LPC_REG47 0x47 // IO Port Decode Enable Register 4- RW
+#define FCH_LPC_REG48 0x48 // IO/Mem Port Decode Enable Register 5- RW
+#define FCH_LPC_REG49 0x49 // LPC Sync Timeout Count - RW
+#define FCH_LPC_REG4A 0x4A // IO/Mem Port Decode Enable Register 6- RW
+#define FCH_LPC_REG4C 0x4C // Memory Range Register - RW
+#define FCH_LPC_REG50 0x50 // Rom Protect 0 - RW
+#define FCH_LPC_REG54 0x54 // Rom Protect 1 - RW
+#define FCH_LPC_REG58 0x58 // Rom Protect 2 - RW
+#define FCH_LPC_REG5C 0x5C // Rom Protect 3 - RW
+#define FCH_LPC_REG60 0x60 // PCI Memory Start Address of LPC Target Cycles -
+#define FCH_LPC_REG62 0x62 // PCI Memory End Address of LPC Target Cycles -
+#define FCH_LPC_REG64 0x64 // PCI IO base Address of Wide Generic Port - RW
+#define FCH_LPC_REG65 0x65
+#define FCH_LPC_REG66 0x66
+#define FCH_LPC_REG67 0x67
+#define FCH_LPC_REG68 0x68 // LPC ROM Address Range 1 (Start Address) - RW
+#define FCH_LPC_REG69 0x69
+#define FCH_LPC_REG6A 0x6A // LPC ROM Address Range 1 (End Address) - RW
+#define FCH_LPC_REG6B 0x6B
+#define FCH_LPC_REG6C 0x6C // LPC ROM Address Range 2 (Start Address)- RW
+#define FCH_LPC_REG6D 0x6D
+#define FCH_LPC_REG6E 0x6E // LPC ROM Address Range 2 (End Address) - RW
+#define FCH_LPC_REG6F 0x6F
+#define FCH_LPC_REG70 0x70 // Firmware ub Select - RW*
+#define FCH_LPC_REG71 0x71
+#define FCH_LPC_REG72 0x72
+#define FCH_LPC_REG73 0x73
+#define FCH_LPC_REG74 0x74 // Alternative Wide IO Range Enable- W/R
+#define FCH_LPC_REG78 0x78 // Miscellaneous Control Bits- W/R
+#define FCH_LPC_REG79 0x79 // Miscellaneous Control Bits- W/R
+#define FCH_LPC_REG7C 0x7C // TPM (trusted plant form module) reg- W/R
+#define FCH_LPC_REG9C 0x9C
+#define FCH_LPC_REG80 0x80 // MSI Capability Register- R
+#define FCH_LPC_REGA0 0x0A0 // SPI base address
+#define FCH_LPC_REGA1 0x0A1 // SPI base address
+#define FCH_LPC_REGA2 0x0A2 // SPI base address
+#define FCH_LPC_REGA3 0x0A3 // SPI base address
+#define FCH_LPC_REGA4 0x0A4
+#define FCH_LPC_REGB8 0x0B8
+#define FCH_LPC_REGBA 0x0BA // EcControl
+#define FCH_LPC_REGBB 0x0BB // HostControl
+#define FCH_LPC_REGC8 0x0C8
+#define FCH_LPC_REGCC 0x0CC // AutoRomCfg
+#define FCH_LPC_REGD0 0x0D0
+#define FCH_LPC_REGD3 0x0D3
+#define FCH_LPC_REGD4 0x0D4
+
+//
+// FCH PCIB 0x780F
+// Device 20 (0x14) Func 4
+//
+#define FCH_PCIB_REG04 0x04 // Command
+#define FCH_PCIB_REG0D 0x0D // Primary Master Latency Timer
+#define FCH_PCIB_REG1B 0x1B // Secondary Latency Timer
+#define FCH_PCIB_REG1C 0x1C // IO Base
+#define FCH_PCIB_REG1D 0x1D // IO Limit
+#define FCH_PCIB_REG40 0x40 // CPCTRL
+#define FCH_PCIB_REG42 0x42 // CLKCTRL
+#define FCH_PCIB_REG48 0x48 //
+#define FCH_PCIB_REG4A 0x4A // PCICLK Enable Bits
+#define FCH_PCIB_REG4B 0x4B // Misc Control
+#define FCH_PCIB_REG4C 0x4C // AutoClockRun Control
+#define FCH_PCIB_REG50 0x50 // Dual Address Cycle Enable and PCIB_CLK_Stop Override
+#define FCH_PCIB_REG65 0x65 // Misc Control
+#define FCH_PCIB_REG66 0x66 // Misc Control
+//
+// FCH GEC 0x14E4 0x1699
+// Device 20 (0x14) Func 6
+//
+#define FCH_GEC_REG10 0x10 // GEC BAR
+
+//
+// FCH SD
+// Device 20 (0x14) Func 7
+//
+#define SD_PCI_REG10 0x10
+#define SD_PCI_REG2C 0x2C
+#define SD_PCI_REGA4 0xA4
+#define SD_PCI_REGA8 0xA8
+#define SD_PCI_REGAC 0xAC
+#define SD_PCI_REGB0 0xB0
+#define SD_PCI_REGB8 0xB8
+#define SD_PCI_REGBC 0xBC
+#define SD_PCI_REGD0 0xD0
+#define SD_PCI_REGF0 0xF0
+#define SD_PCI_REGF4 0xF4
+#define SD_PCI_REGF8 0xF8
+#define SD_PCI_REGFC 0xFC
+#define FCH_SD_BAR_REG28 0x28 // SDHC_CTRL1
+#define SD_CARD_PRESENT BIT0
+#define FCH_SD_BAR_REG2C 0x2C // SDHC_CTRL2
+#define FCH_SD_FREQUENCY_SLT BIT2
+#define FCH_SD_BAR_REG3C 0x3C // SDHC_HOST_CTRL2
+#define FCH_SD_1_8V BIT3
+
+//
+// FCH MMIO Base (SMI)
+// offset : 0x200
+//
+#define FCH_SMI_REG00 0x00 // EventStatus
+#define FCH_SMI_REG04 0x04 // EventEnable
+#define FCH_SMI_REG08 0x08 // SciTrig
+#define FCH_SMI_REG0C 0x0C // SciLevl
+#define FCH_SMI_REG10 0x10 // SmiSciStatus
+#define FCH_SMI_REG14 0x14 // SmiSciEn
+#define FCH_SMI_REG18 0x18 // ForceSciEn
+#define FCH_SMI_REG1C 0x1C // SciRwData
+#define FCH_SMI_REG3C 0x3C // DataErrorStatus
+#define FCH_SMI_REG20 0x20 // SciS0En
+#define FCH_SMI_Gevent0 0x40 // SciMap0
+#define FCH_SMI_Gevent1 0x41 // SciMap1
+#define FCH_SMI_Gevent2 0x42 // SciMap2
+#define FCH_SMI_Gevent3 0x43 // SciMap3
+#define FCH_SMI_Gevent4 0x44 // SciMap4
+#define FCH_SMI_Gevent5 0x45 // SciMap5
+#define FCH_SMI_Gevent6 0x46 // SciMap6
+#define FCH_SMI_Gevent7 0x47 // SciMap7
+#define FCH_SMI_Gevent8 0x48 // SciMap8
+#define FCH_SMI_Gevent9 0x49 // SciMap9
+#define FCH_SMI_Gevent10 0x4A // SciMap10
+#define FCH_SMI_Gevent11 0x4B // SciMap11
+#define FCH_SMI_Gevent12 0x4C // SciMap12
+#define FCH_SMI_Gevent13 0x4D // SciMap13
+#define FCH_SMI_Gevent14 0x4E // SciMap14
+#define FCH_SMI_Gevent15 0x4F // SciMap15
+#define FCH_SMI_Gevent16 0x50 // SciMap16
+#define FCH_SMI_Gevent17 0x51 // SciMap17
+#define FCH_SMI_Gevent18 0x52 // SciMap18
+#define FCH_SMI_Gevent19 0x53 // SciMap19
+#define FCH_SMI_Gevent20 0x54 // SciMap20
+#define FCH_SMI_Gevent21 0x55 // SciMap21
+#define FCH_SMI_Gevent22 0x56 // SciMap22
+#define FCH_SMI_Gevent23 0x57 // SciMap23
+#define FCH_SMI_Usbwakup0 0x58 // SciMap24
+#define FCH_SMI_Usbwakup1 0x59 // SciMap25
+#define FCH_SMI_Usbwakup2 0x5A // SciMap26
+#define FCH_SMI_Usbwakup3 0x5B // SciMap27
+#define FCH_SMI_SBGppPme0 0x5C // SciMap28
+#define FCH_SMI_SBGppPme1 0x5D // SciMap29
+#define FCH_SMI_SBGppPme2 0x5E // SciMap30
+#define FCH_SMI_SBGppPme3 0x5F // SciMap31
+#define FCH_SMI_SBGppHp0 0x60 // SciMap32
+#define FCH_SMI_SBGppHp1 0x61 // SciMap33
+#define FCH_SMI_SBGppHp2 0x62 // SciMap34
+#define FCH_SMI_SBGppHp3 0x63 // SciMap35
+#define FCH_SMI_AzaliaPme 0x64 // SciMap36
+#define FCH_SMI_SataGevent0 0x65 // SciMap37
+#define FCH_SMI_SataGevent1 0x66 // SciMap38
+#define FCH_SMI_GecPme 0x67 // SciMap39
+#define FCH_SMI_IMCGevent0 0x68 // SciMap40
+#define FCH_SMI_IMCGevent1 0x69 // SciMap41
+#define FCH_SMI_CIRPme 0x6A // SciMap42
+#define FCH_SMI_WakePinGevent 0x6B // SciMap43
+#define FCH_SMI_FanThGevent 0x6C // SciMap44 //FanThermalGevent
+#define FCH_SMI_ASFMasterIntr 0x6D // SciMap45
+#define FCH_SMI_ASFSlaveIntr 0x6E // SciMap46
+#define FCH_SMI_SMBUS0 0x6F // SciMap47
+#define FCH_SMI_TWARN 0x70 // SciMap48
+#define FCH_SMI_TMI 0x71 // SciMap49 // TrafficMonitorIntr
+#define FCH_SMI_iLLB 0x72 // SciMap50
+#define FCH_SMI_PowerButton 0x73 // SciMap51
+#define FCH_SMI_ProcHot 0x74 // SciMap52
+#define FCH_SMI_APUHwAssertion 0x75 // SciMap53
+#define FCH_SMI_APUSciAssertion 0x76 // SciMap54
+#define FCH_SMI_RAS 0x77 // SciMap55
+#define FCH_SMI_xHC0Pme 0x78 // SciMap56
+#define FCH_SMI_xHC1Pme 0x79 // SciMap57
+#define FCH_SMI_AcDcWake 0x7A // SciMap58
+
+// Empty from 0x72-0x7F
+//#Define FCH_SMI_REG7C 0x7F // SciMap63 ***
+
+#define FCH_SMI_REG80 0x80 // SmiStatus0
+#define FCH_SMI_REG84 0x84 // SmiStatus1
+#define FCH_SMI_REG88 0x88 // SmiStatus2
+#define FCH_SMI_REG8C 0x8C // SmiStatus3
+#define FCH_SMI_REG90 0x90 // SmiStatus4
+#define FCH_SMI_REG94 0x94 // SmiPointer
+#define FCH_SMI_REG96 0x96 // SmiTimer
+#define FCH_SMI_REG98 0x98 // SmiTrig
+#define FCH_SMI_REG9C 0x9C // SmiTrig
+#define FCH_SMI_REGA0 0xA0
+#define FCH_SMI_REGA1 0xA1
+#define FCH_SMI_REGA2 0xA2
+#define FCH_SMI_REGA3 0xA3
+#define FCH_SMI_REGA4 0xA4
+#define FCH_SMI_REGA5 0xA5
+#define FCH_SMI_REGA6 0xA6
+#define FCH_SMI_REGA7 0xA7
+#define FCH_SMI_REGA8 0xA8
+#define FCH_SMI_REGA9 0xA9
+#define FCH_SMI_REGAA 0xAA
+#define FCH_SMI_REGAB 0xAB
+#define FCH_SMI_REGAC 0xAC
+#define FCH_SMI_REGAD 0xAD
+#define FCH_SMI_REGAE 0xAE
+#define FCH_SMI_REGAF 0xAF
+#define FCH_SMI_REGB0 0xB0
+#define FCH_SMI_REGB1 0xB1
+#define FCH_SMI_REGB2 0xB2
+#define FCH_SMI_REGB3 0xB3
+#define FCH_SMI_REGB4 0xB4
+#define FCH_SMI_REGB5 0xB5
+#define FCH_SMI_REGB6 0xB6
+#define FCH_SMI_REGB7 0xB7
+#define FCH_SMI_REGB8 0xB8
+#define FCH_SMI_REGB9 0xB9
+#define FCH_SMI_REGBA 0xBA
+#define FCH_SMI_REGBB 0xBB
+#define FCH_SMI_REGBC 0xBC
+#define FCH_SMI_REGBD 0xBD
+#define FCH_SMI_REGBE 0xBE
+#define FCH_SMI_REGBF 0xBF
+#define FCH_SMI_REGC0 0xC0
+#define FCH_SMI_REGC1 0xC1
+#define FCH_SMI_REGC2 0xC2
+#define FCH_SMI_REGC3 0xC3
+#define FCH_SMI_REGC4 0xC4
+#define FCH_SMI_REGC5 0xC5
+#define FCH_SMI_REGC6 0xC6
+#define FCH_SMI_REGC7 0xC7
+#define FCH_SMI_REGC8 0xC8
+#define FCH_SMI_REGCA 0xCA // IoTrapping1
+#define FCH_SMI_REGCC 0xCC // IoTrapping2
+#define FCH_SMI_REGCE 0xCE // IoTrapping3
+#define FCH_SMI_TRAPPING_WRITE 0x01
+#define FCH_SMI_REGD0 0xD0 // MemTrapping0
+#define FCH_SMI_REGD4 0xD4 // MemRdOvrData0
+#define FCH_SMI_REGD8 0xD8 // MemTrapping1
+#define FCH_SMI_REGDC 0xDC // MemRdOvrData1
+#define FCH_SMI_REGE0 0xE0 // MemTrapping2
+#define FCH_SMI_REGE4 0xE4 // MemRdOvrData2
+#define FCH_SMI_REGE8 0xE8 // MemTrapping3
+#define FCH_SMI_REGEC 0xEC // MemRdOvrData3
+#define FCH_SMI_REGF0 0xF0 // CfgTrapping0
+#define FCH_SMI_REGF4 0xF4 // CfgTrapping1
+#define FCH_SMI_REGF8 0xF8 // CfgTrapping2
+#define FCH_SMI_REGFC 0xFC // CfgTrapping3
+
+//
+// FCH MMIO Base (PMIO)
+// offset : 0x300
+//
+#define FCH_PMIOA_REG00 0x00 // ISA Decode
+#define FCH_PMIOA_REG04 0x04 // ISA Control
+#define FCH_PMIOA_REG08 0x08 // PCI Control
+#define FCH_PMIOA_REG0C 0x0C // StpClkSmaf
+#define FCH_PMIOA_REG10 0x10 // RetryDetect
+#define FCH_PMIOA_REG14 0x14 // StuckDetect
+#define FCH_PMIOA_REG20 0x20 // BiosRamEn
+#define FCH_PMIOA_REG24 0x24 // AcpiMmioEn
+#define FCH_PMIOA_REG28 0x28 // AsfEn
+#define FCH_PMIOA_REG2C 0x2C // Smbus0En
+#define FCH_PMIOA_REG2E 0x2E // Smbus0Sel
+#define FCH_PMIOA_REG34 0x34 // IoApicEn
+#define FCH_PMIOA_REG3C 0x3C // SmartVoltEn
+#define FCH_PMIOA_REG40 0x40 // SmartVolt2En
+#define FCH_PMIOA_REG44 0x44 // BootTimerEn
+#define FCH_PMIOA_REG48 0x48 // WatchDogTimerEn
+#define FCH_PMIOA_REG4C 0x4C // WatchDogTimerConfig
+#define FCH_PMIOA_REG50 0x50 // HPETEn
+#define FCH_PMIOA_REG54 0x54 // SerialIrqConfig
+#define FCH_PMIOA_REG56 0x56 // RtcControl
+#define FCH_PMIOA_REG58 0x58 // VRT_T1
+#define FCH_PMIOA_REG59 0x59 // VRT_T2
+#define FCH_PMIOA_REG5A 0x5A // IntruderControl
+#define FCH_PMIOA_REG5B 0x5B // RtcShadow
+#define FCH_PMIOA_REG5C 0x5C
+#define FCH_PMIOA_REG5D 0x5D
+#define FCH_PMIOA_REG5E 0x5E // RtcExtIndex
+#define FCH_PMIOA_REG5F 0x5F // RtcExtData
+#define FCH_PMIOA_REG60 0x60 // AcpiPm1EvtBlk
+#define FCH_PMIOA_REG62 0x62 // AcpiPm1CntBlk
+#define FCH_PMIOA_REG64 0x64 // AcpiPmTmrBlk
+#define FCH_PMIOA_REG66 0x66 // P_CNTBlk
+#define FCH_PMIOA_REG68 0x68 // AcpiGpe0Blk
+#define FCH_PMIOA_REG6A 0x6A // AcpiSmiCmd
+#define FCH_PMIOA_REG6C 0x6C // AcpiPm2CntBlk
+#define FCH_PMIOA_REG6E 0x6E // AcpiPmaCntBlk
+#define FCH_PMIOA_REG74 0x74 // AcpiConfig
+#define FCH_PMIOA_REG78 0x78 // WakeIoAddr
+#define FCH_PMIOA_REG7A 0x7A // HaltCountEn
+#define FCH_PMIOA_REG7C 0x7C // C1eWrPortAdr
+#define FCH_PMIOA_REG7E 0x7E // CStateEn
+#define FCH_PMIOA_REG7F 0x7F // CStateEn
+#define FCH_PMIOA_REG80 0x80 // BreakEvent
+#define FCH_PMIOA_REG84 0x84 // AutoArbEn
+#define FCH_PMIOA_REG88 0x88 // CStateControl
+#define FCH_PMIOA_REG89 0x89 //
+#define FCH_PMIOA_REG8C 0x8C // StpClkHoldTime
+#define FCH_PMIOA_REG8E 0x8E // PopUpEndTime
+#define FCH_PMIOA_REG90 0x90 // C4Control
+#define FCH_PMIOA_REG94 0x94 // CStateTiming0
+#define FCH_PMIOA_REG96 0x96 //
+#define FCH_PMIOA_REG97 0x97 //
+#define FCH_PMIOA_REG98 0x98 // CStateTiming1
+#define FCH_PMIOA_REG99 0x99 //
+#define FCH_PMIOA_REG9B 0x9B //
+#define FCH_PMIOA_REG9C 0x9C // C2Count
+#define FCH_PMIOA_REG9D 0x9D // C3Count
+#define FCH_PMIOA_REG9E 0x9E // C4Count
+#define FCH_PMIOA_REGA0 0xA0 // MessageCState
+#define FCH_PMIOA_REGA4 0xA4 //
+#define FCH_PMIOA_REGA8 0xA8 // TrafficMonitorIdleTime
+#define FCH_PMIOA_REGAA 0xAA // TrafficMonitorIntTime
+#define FCH_PMIOA_REGAC 0xAC // TrafficMonitorTrafficCount
+#define FCH_PMIOA_REGAE 0xAE // TrafficMonitorIntrCount
+#define FCH_PMIOA_REGB0 0xB0 // TrafficMonitorTimeTick
+#define FCH_PMIOA_REGB4 0xB4 // FidVidControl
+#define FCH_PMIOA_REGB6 0xB6 // TPRESET1
+#define FCH_PMIOA_REGB7 0xB7 // Tpreset1b
+#define FCH_PMIOA_REGB8 0xB8 // TPRESET2
+#define FCH_PMIOA_REGB9 0xB9 // Test0
+#define FCH_PMIOA_REGBA 0xBA // S_StateControl
+#define FCH_PMIOA_REGBB 0xBB //
+#define FCH_PMIOA_REGBC 0xBC // ThrottlingControl
+#define FCH_PMIOA_REGBE 0xBE // ResetControl
+#define FCH_PMIOA_REGBF 0xBF // ResetControl
+#define FCH_PMIOA_REGC0 0xC0 // S5Status
+#define FCH_PMIOA_REGC2 0xC2 // ResetStatus
+#define FCH_PMIOA_REGC4 0xC4 // ResetCommand
+#define FCH_PMIOA_REGC5 0xC5 // CF9Shadow
+#define FCH_PMIOA_REGC6 0xC6 // HTControl
+#define FCH_PMIOA_REGC8 0xC8 // Misc
+#define FCH_PMIOA_REGCC 0xCC // IoDrvSth
+#define FCH_PMIOA_REGD0 0xD0 // CLKRunEn
+#define FCH_PMIOA_REGD2 0xD2 // PmioDebug
+#define FCH_PMIOA_REGD3 0xD3 // SD
+#define FCH_PMIOA_REGD6 0xD6 // IMCGating
+#define FCH_PMIOA_REGD7 0xD7 //
+#define FCH_PMIOA_REGD8 0xD8 // MiscIndex
+#define FCH_PMIOA_REGD9 0xD9 // MiscData
+#define FCH_PMIOA_REGDA 0xDA // SataConfig
+#define FCH_PMIOA_REGDC 0xDC // HyperFlashConfig
+#define FCH_PMIOA_REGDE 0xDE // ABConfig
+#define FCH_PMIOA_REGE0 0xE0 // ABRegBar
+#define FCH_PMIOA_REGE4 0xE4
+#define FCH_PMIOA_REGE6 0xE6 // FcEn
+#define FCH_PMIOA_REGE7 0xE7
+#define FCH_PMIOA_REGE8 0xE8
+#define FCH_PMIOA_REGEA 0xEA // PcibConfig
+#define FCH_PMIOA_REGEB 0xEB // AzEn
+#define FCH_PMIOA_REGEC 0xEC // LpcGating
+#define FCH_PMIOA_REGED 0xED // UsbGating
+#define FCH_PMIOA_REGEE 0xEE // UsbCntrl
+#define FCH_PMIOA_REGEF 0xEF // UsbEnable
+#define FCH_PMIOA_REGF0 0xF0 // UsbControl
+#define FCH_PMIOA_REGF2 0xF2 // UsbControl2
+#define FCH_PMIOA_REGF3 0xF3 // UsbDebug
+#define FCH_PMIOA_REGF4 0xF4 // UsbDebug
+#define FCH_PMIOA_REGF6 0xF6 // GecEn
+#define FCH_PMIOA_REGF8 0xF8 // GecConfig
+#define FCH_PMIOA_REGFC 0xFC // TraceMemoryEn
+
+#define FCH_PMx00_DecodeEn 0xFED80300ul //
+#define FCH_PMxC0_ResetStatus 0xFED803C0ul //
+#define FCH_PMxC0_ResetStatus_Mask 0x3fff0000ul //
+#define FCH_PMxC4_ResetCommand 0xFED803C4ul //
+#define FCH_PMxDC_SataConfig2 0xFED803DCul //
+
+//
+// FCH MMIO Base (PMIO2)
+// offset : 0x400
+//
+#define FCH_PMIO2_REG00 0x00 // Fan0InputControl
+#define FCH_PMIO2_REG01 0x01 // Fan0Control
+#define FCH_PMIO2_REG02 0x02 // Fan0Freq
+#define FCH_PMIO2_REG03 0x03 // LowDuty0
+#define FCH_PMIO2_REG04 0x04 // MidDuty0
+
+#define FCH_PMIO2_REG10 0x00 // Fan1InputControl
+#define FCH_PMIO2_REG11 0x01 // Fan1Control
+#define FCH_PMIO2_REG12 0x02 // Fan1Freq
+#define FCH_PMIO2_REG13 0x03 // LowDuty1
+#define FCH_PMIO2_REG14 0x04 // MidDuty1
+
+#define FCH_PMIO2_REG63 0x63 // SampleFreqDiv
+#define FCH_PMIO2_REG69 0x69 // Fan0 Speed
+#define FCH_PMIO2_REG95 0x95 // Temperature
+#define FCH_PMIO2_REGB8 0xB8 // Voltage
+#define FCH_PMIO2_REGEA 0xEA // Hwm_Calibration
+
+#define FCH_PMIO2_REG92 0x92 //
+#define FCH_PMIO2_REGF8 0xF8 // VoltageSamleSel
+#define FCH_PMIO2_REGF9 0xF9 // TempSampleSel
+
+#define FCH_PMIO2_REG 0xFC // TraceMemoryEn
+
+
+//
+// FCH MMIO Base (GPIO/IoMux)
+// offset : 0x100/0xD00
+//
+/*
+GPIO from 0 ~ 67, (GEVENT 0-23) 128 ~ 150, 160 ~ 226.
+*/
+#define FCH_GPIO_REG00 0x00
+#define FCH_GPIO_REG06 0x06
+#define FCH_GPIO_REG09 0x09
+#define FCH_GPIO_REG10 0x0A
+#define FCH_GPIO_REG17 0x11
+#define FCH_GPIO_REG21 0x15
+#define FCH_GPIO_REG28 0x1C
+#define FCH_GPIO_REG32 0x20
+#define FCH_GPIO_REG33 0x21
+#define FCH_GPIO_REG34 0x22
+#define FCH_GPIO_REG35 0x23
+#define FCH_GPIO_REG36 0x24
+#define FCH_GPIO_REG37 0x25
+#define FCH_GPIO_REG38 0x26
+#define FCH_GPIO_REG39 0x27
+#define FCH_GPIO_REG40 0x28
+#define FCH_GPIO_REG41 0x29
+#define FCH_GPIO_REG42 0x2A
+#define FCH_GPIO_REG43 0x2B
+#define FCH_GPIO_REG44 0x2C
+#define FCH_GPIO_REG45 0x2D
+#define FCH_GPIO_REG46 0x2E
+#define FCH_GPIO_REG47 0x2F
+#define FCH_GPIO_REG48 0x30
+#define FCH_GPIO_REG49 0x31
+#define FCH_GPIO_REG50 0x32
+#define FCH_GPIO_REG51 0x33
+#define FCH_GPIO_REG52 0x34
+#define FCH_GPIO_REG53 0x35
+#define FCH_GPIO_REG54 0x36
+#define FCH_GPIO_REG55 0x37
+#define FCH_GPIO_REG56 0x38
+#define FCH_GPIO_REG57 0x39
+#define FCH_GPIO_REG58 0x3A
+#define FCH_GPIO_REG59 0x3B
+#define FCH_GPIO_REG60 0x3C
+#define FCH_GPIO_REG61 0x3D
+#define FCH_GPIO_REG62 0x3E
+#define FCH_GPIO_REG63 0x3F
+#define FCH_GPIO_REG64 0x40
+#define FCH_GPIO_REG65 0x41
+#define FCH_GPIO_REG66 0x42
+#define FCH_GPIO_REG67 0x43
+#define FCH_GPIO_REG68 0x44
+#define FCH_GPIO_REG69 0x45
+#define FCH_GPIO_REG70 0x46
+#define FCH_GPIO_REG71 0x47
+#define FCH_GPIO_REG72 0x48
+#define FCH_GPIO_REG73 0x49
+#define FCH_GPIO_REG74 0x4A
+#define FCH_GPIO_REG75 0x4B
+#define FCH_GPIO_REG76 0x4C
+#define FCH_GPIO_REG77 0x4D
+#define FCH_GPIO_REG78 0x4E
+#define FCH_GPIO_REG79 0x4F
+#define FCH_GPIO_REG80 0x50
+
+#define FCH_GEVENT_REG00 0x60
+#define FCH_GEVENT_REG01 0x61
+#define FCH_GEVENT_REG02 0x62
+#define FCH_GEVENT_REG03 0x63
+#define FCH_GEVENT_REG04 0x64
+#define FCH_GEVENT_REG05 0x65
+#define FCH_GEVENT_REG06 0x66
+#define FCH_GEVENT_REG07 0x67
+#define FCH_GEVENT_REG08 0x68
+#define FCH_GEVENT_REG09 0x69
+#define FCH_GEVENT_REG10 0x6A
+#define FCH_GEVENT_REG11 0x6B
+#define FCH_GEVENT_REG12 0x6C
+#define FCH_GEVENT_REG13 0x6D
+#define FCH_GEVENT_REG14 0x6E
+#define FCH_GEVENT_REG15 0x6F
+#define FCH_GEVENT_REG16 0x70
+#define FCH_GEVENT_REG17 0x71
+#define FCH_GEVENT_REG18 0x72
+#define FCH_GEVENT_REG19 0x73
+#define FCH_GEVENT_REG20 0x74
+#define FCH_GEVENT_REG21 0x75
+#define FCH_GEVENT_REG22 0x76
+#define FCH_GEVENT_REG23 0x77
+// S5-DOMAIN GPIO
+#define FCH_GPIO_REG160 0xA0
+#define FCH_GPIO_REG161 0xA1
+#define FCH_GPIO_REG162 0xA2
+#define FCH_GPIO_REG163 0xA3
+#define FCH_GPIO_REG164 0xA4
+#define FCH_GPIO_REG165 0xA5
+#define FCH_GPIO_REG166 0xA6
+#define FCH_GPIO_REG167 0xA7
+#define FCH_GPIO_REG168 0xA8
+#define FCH_GPIO_REG169 0xA9
+#define FCH_GPIO_REG170 0xAA
+#define FCH_GPIO_REG171 0xAB
+#define FCH_GPIO_REG172 0xAC
+#define FCH_GPIO_REG173 0xAD
+#define FCH_GPIO_REG174 0xAE
+#define FCH_GPIO_REG175 0xAF
+#define FCH_GPIO_REG176 0xB0
+#define FCH_GPIO_REG177 0xB1
+#define FCH_GPIO_REG178 0xB2
+#define FCH_GPIO_REG179 0xB3
+#define FCH_GPIO_REG180 0xB4
+#define FCH_GPIO_REG181 0xB5
+#define FCH_GPIO_REG182 0xB6
+#define FCH_GPIO_REG183 0xB7
+#define FCH_GPIO_REG184 0xB8
+#define FCH_GPIO_REG185 0xB9
+#define FCH_GPIO_REG186 0xBA
+#define FCH_GPIO_REG187 0xBB
+#define FCH_GPIO_REG188 0xBC
+#define FCH_GPIO_REG189 0xBD
+#define FCH_GPIO_REG190 0xBE
+#define FCH_GPIO_REG191 0xBF
+#define FCH_GPIO_REG192 0xC0
+#define FCH_GPIO_REG193 0xC1
+#define FCH_GPIO_REG194 0xC2
+#define FCH_GPIO_REG195 0xC3
+#define FCH_GPIO_REG196 0xC4
+#define FCH_GPIO_REG197 0xC5
+#define FCH_GPIO_REG198 0xC6
+#define FCH_GPIO_REG199 0xC7
+#define FCH_GPIO_REG200 0xC8
+#define FCH_GPIO_REG201 0xC9
+#define FCH_GPIO_REG202 0xCA
+#define FCH_GPIO_REG203 0xCB
+#define FCH_GPIO_REG204 0xCC
+#define FCH_GPIO_REG205 0xCD
+#define FCH_GPIO_REG206 0xCE
+#define FCH_GPIO_REG207 0xCF
+#define FCH_GPIO_REG208 0xD0
+#define FCH_GPIO_REG209 0xD1
+#define FCH_GPIO_REG210 0xD2
+#define FCH_GPIO_REG211 0xD3
+#define FCH_GPIO_REG212 0xD4
+#define FCH_GPIO_REG213 0xD5
+#define FCH_GPIO_REG214 0xD6
+#define FCH_GPIO_REG215 0xD7
+#define FCH_GPIO_REG216 0xD8
+#define FCH_GPIO_REG217 0xD9
+#define FCH_GPIO_REG218 0xDA
+#define FCH_GPIO_REG219 0xDB
+#define FCH_GPIO_REG220 0xDC
+#define FCH_GPIO_REG221 0xDD
+#define FCH_GPIO_REG222 0xDE
+#define FCH_GPIO_REG223 0xDF
+#define FCH_GPIO_REG224 0xF0
+#define FCH_GPIO_REG225 0xF1
+#define FCH_GPIO_REG226 0xF2
+#define FCH_GPIO_REG227 0xF3
+#define FCH_GPIO_REG228 0xF4
+
+#define FCH_IOMUXx0D_IR_TX0_USB_OC5_L_AGPIO13 0xFED80D0Dul //
+#define FCH_IOMUXx0E_IR_TX1_USB_OC6_L_AGPIO14 0xFED80D0Eul //
+#define FCH_IOMUXx13_SCL1_I2C3_SCL_EGPIO19 0xFED80D13ul //
+#define FCH_IOMUXx14_SDA1_I2C3_SDA_EGPIO20 0xFED80D14ul //
+#define FCH_IOMUX_55_FANOUT0_AGPIO85 0xFED80D55ul // FANOUT0_AGPIO85
+#define FCH_IOMUXx66_SD0_PWR_CTRL_AGPIO102 0xFED80D66ul //
+#define FCH_IOMUXx71_SCL0_I2C2_SCL_EGPIO113 0xFED80D71ul //
+#define FCH_IOMUXx72_SDA0_I2C2_SDA_EGPIO114 0xFED80D72ul //
+#define FCH_IOMUXx89_UART0_RTS_L_EGPIO137 0xFED80D89ul //
+#define FCH_IOMUXx8A_UART0_TXD_EGPIO138 0xFED80D8Aul //
+#define FCH_IOMUXx8E_UART1_RTS_L_EGPIO142 0xFED80D8Eul //
+#define FCH_IOMUXx8F_UART1_TXD_EGPIO143 0xFED80D8Ful //
+
+//
+// FCH MMIO Base (GPIO BANK0)
+// offset : 0x1500
+//
+#define FCH_GPIO_PULL_UP_ENABLE BIT4
+#define FCH_GPIO_PULL_DOWN_ENABLE BIT5
+#define FCH_GPIO_OUTPUT_VALUE BIT6
+#define FCH_GPIO_OUTPUT_ENABLE (1 << 7)
+
+#define FCH_GPIO_068_AZ_SDIN0_GPIO26 0x68
+#define FCH_GPIO_06C_AZ_SDIN1_GPIO27 0x6C
+#define FCH_GPIO_070_AZ_SDIN2_GPIO28 0x70
+#define FCH_GPIO_074_AZ_SDIN3_GPIO29 0x74
+
+#define FCH_GPIO_10C_GPIO55_AGPI067 0x10C
+#define FCH_GPIO_118_GPIO59_AGPI070 0x118
+
+//
+// FCH MMIO Base (IoMux)
+// offset : 0xD00
+//
+#define FCH_IOMUX_1A_AZ_SDIN0_EGPIO26 0x1A
+#define FCH_IOMUX_1B_AZ_SDIN1_EGPIO27 0x1B
+#define FCH_IOMUX_1C_AZ_SDIN2_EGPIO28 0x1C
+#define FCH_IOMUX_1D_AZ_SDIN3_EGPIO29 0x1D
+
+//
+// FCH MMIO Base (SMBUS)
+// offset : 0xA00
+//
+#define FCH_SMBUS_REG12 0x12 // I2CbusConfig
+
+//
+// FCH MMIO Base (MISC)
+// offset : 0xE00
+//
+#define FCH_MISC_REG00 0x00 // ClkCntrl0
+/*
+FCH_MISC_REG00 EQU 000h
+ ClkCntrl0 EQU 0FFFFFFFFh
+*/
+#define FCH_MISC_REG04 0x04 // ClkCntrl1
+/*
+FCH_MISC_REG04 EQU 004h
+ ClkCntrl1 EQU 0FFFFFFFFh
+*/
+#define FCH_MISC_REG08 0x08 // ClkCntrl2
+/*
+FCH_MISC_REG08 EQU 008h
+ ClkCntrl2 EQU 0FFFFFFFFh
+*/
+#define FCH_MISC_REG0C 0x0C // ClkCntrl3
+/*
+FCH_MISC_REG0C EQU 00Ch
+ ClkCntrl3 EQU 0FFFFFFFFh
+*/
+#define FCH_MISC_REG10 0x10 // ClkCntrl4
+/*
+FCH_MISC_REG10 EQU 010h
+ ClkCntrl4 EQU 0FFFFFFFFh
+*/
+#define FCH_MISC_REG14 0x14 // ClkCntrl5
+/*
+FCH_MISC_REG14 EQU 014h
+ ClkCntrl5 EQU 0FFFFFFFFh
+*/
+#define FCH_MISC_REG18 0x18 // ClkCntrl6
+/*
+FCH_MISC_REG18 EQU 018h
+ ClkCntrl6 EQU 0FFFFFFFFh
+*/
+#define FCH_MISC_REG1C 0x1C
+#define FCH_MISC_REG20 0x20
+#define FCH_MISC_REG30 0x30 // OscFreqCounter
+/*
+FCH_MISC_REG30 EQU 030h
+ OscCounter EQU 0FFFFFFFFh ; The 32bit register shows the number of OSC clock per second.
+*/
+#define FCH_MISC_REG34 0x34 // HpetClkPeriod
+/*
+FCH_MISC_REG34 EQU 034h
+ HpetClkPeriod EQU 0FFFFFFFFh ; default - 0x429B17Eh (14.31818M).
+*/
+#define FCH_MISC_REG28 0x28 // ClkDrvSth2
+#define FCH_MISC_REG2C 0x2C
+#define FCH_MISC_REG40 0x40 // MiscCntrl for clock only
+#define FCH_MISC_REG41 0x41 // MiscCntr2
+#define FCH_MISC_REG42 0x42 // MiscCntr3
+#define FCH_MISC_REG44 0x44 // ValueOnPort80
+#define FCH_MISC_REG50 0x50 //
+#define FCH_MISCx50_JTAG_CONTROL_ECO 0xFED80E50ul //
+#define FCH_MISCx68_MEMORY_POWER_SAVING_CONTROL 0xFED80E68ul //
+
+#define FCH_MISC_REG6C 0x6C // EcoBit2
+/*
+FCH_MISC_REG40 EQU 040h
+*/
+
+#define FCH_MISC_REG80 0x80 /**< FCH_MISC_REG80
+ * @par
+ * StrapStatus [15.0] - FCH chip Strap Status
+ * @li <b>0001</b> - Not USED FWH
+ * @li <b>0002</b> - Not USED LPC ROM
+ * @li <b>0004</b> - EC enabled
+ * @li <b>0008</b> - Reserved
+ * @li <b>0010</b> - Internal Clock mode
+ */
+#define FCH_MISC_REGB6 0xB6 //
+
+#define ChipSysNotUseFWHRom 0x0001 // EcPwm3 pad
+#define ChipSysNotUseLpcRom 0x0002 // Inverted version from EcPwm2 pad (default - 1)
+ // Note: Both EcPwm3 and EcPwm2 straps pins are used to select boot ROM type.
+#define ChipSysEcEnable 0x0004 // Enable Embedded Controller (EC)
+#define ChipSysBootFailTmrEn 0x0008 // Enable Watchdog function
+#define ChipSysIntClkGen 0x0010 // Select 25Mhz crystal clock or 100Mhz PCI-E clock **
+
+#define FCH_MISC_REG84 0x84 // StrapOverride
+/*
+FCH_MISC_REG84 EQU 084h
+ Override FWHDisableStrap EQU BIT0 ; Override FWHDiableStrap value from external pin.
+ Override UseLpcRomStrap EQU BIT1 ; Override UseLpcRomStrap value from external pin.
+ Override EcEnableStrap EQU BIT2 ; Override EcEnableStrap value from external pin.
+ Override BootFailTmrEnStrap EQU BIT3 ; Override BootFailTmrEnStrap value from external pin.
+ Override DefaultModeStrap EQU BIT5 ; Override DefaultModeStrap value from external pin.
+ Override I2CRomStrap EQU BIT7 ; Override I2CRomStrap value from external pin.
+ Override ILAAutorunEnBStrap EQU BIT8 ; Override ILAAutorunEnBStrap value from external pin.
+ Override FcPllBypStrap EQU BIT9 ; Override FcPllBypStrap value from external pin.
+ Override PciPllBypStrap EQU BIT10 ; Override PciPllBypStrap value from external pin.
+ Override ShortResetStrap EQU BIT11 ; Override ShortResetStrap value from external pin.
+ Override FastBif2ClkStrap EQU BIT13 ; Override FastBif2ClkStrap value from external pin
+ PciRomBootStrap EQU BIT15 ; Override PCI Rom Boot Strap value from external pin
+ BlinkSlowModestrap EQU BIT16 ; Override Blink Slow mode (100Mhz) from external pin
+ ClkGenStrap EQU BIT17 ; Override CLKGEN from external pin.
+ BIF_GEN2_COMPL_Strap EQU BIT18 ; Override BIF_ GEN2_COMPLIANCE strap from external pin.
+ StrapOverrideEn EQU BIT31 ; Enable override strapping feature.
+*/
+#define FCH_MISC_REGC0 0xC0 // CPU_Pstate0
+/*
+FCH_MISC_REGC0 EQU 0C0h
+ Core0_PState EQU BIT0+BIT1+BIT2 ; 000: P0 001: P1 010: P2 011: P3 100: P4 101: P5 110: P6 111: P7
+ Core1_PState EQU BIT4+BIT5+BIT6
+ Core2_PState EQU BIT8+BIT9+BIT10
+ Core3_PState EQU BIT12+BIT13+BIT14
+ Core4_PState EQU BIT16++BIT17+BIT18
+ Core5_PState EQU BIT20+BIT21+BIT22
+ Core6_PState EQU BIT24+BIT25+BIT26
+ Core7_PState EQU BIT28+BIT29+BIT30
+*/
+#define FCH_MISC_REGC4 0xC4 // CPU_Pstate1
+/*
+FCH_MISC_REGC4 EQU 0C4h
+ Core8_PState EQU BIT0+BIT1+BIT2 ; 000: P0 001: P1 010: P2 011: P3 100: P4 101: P5 110: P6 111: P7
+ Core9_PState EQU BIT4+BIT5+BIT6
+ Core10_PState EQU BIT8+BIT9+BIT10
+ Core11_PState EQU BIT12+BIT13+BIT14
+ Core12_PState EQU BIT16++BIT17+BIT18
+ Core13_PState EQU BIT20+BIT21+BIT22
+ Core14_PState EQU BIT24+BIT25+BIT26
+ Core15_PState EQU BIT28+BIT29+BIT30
+*/
+#define FCH_MISC_REGD0 0xD0 // CPU_Cstate0
+/*
+FCH_MISC_REGD0 EQU 0D0h
+ Core0_CState EQU BIT0+BIT1+BIT2 ; 000: C0 001: C1 010: C2 011: C3 100: C4 101: C5 110: C6 111: C7
+ Core1_CState EQU BIT4+BIT5+BIT6
+ Core2_CState EQU BIT8+BIT9+BIT10
+ Core3_CState EQU BIT12+BIT13+BIT14
+ Core4_CState EQU BIT16++BIT17+BIT18
+ Core5_CState EQU BIT20+BIT21+BIT22
+ Core6_CState EQU BIT24+BIT25+BIT26
+ Core7_CState EQU BIT28+BIT29+BIT30
+*/
+#define FCH_MISC_REGD4 0xD4 // CPU_Cstate1
+/*
+FCH_MISC_REGD4 EQU 0D4h
+ Core8_CState EQU BIT0+BIT1+BIT2 ; 000: C0 001: C1 010: C2 011: C3 100: C4 101: C5 110: C6 111: C7
+ Core9_CState EQU BIT4+BIT5+BIT6
+ Core10_CState EQU BIT8+BIT9+BIT10
+ Core11_CState EQU BIT12+BIT13+BIT14
+ Core12_CState EQU BIT16++BIT17+BIT18
+ Core13_CState EQU BIT20+BIT21+BIT22
+ Core14_CState EQU BIT24+BIT25+BIT26
+ Core15_CState EQU BIT28+BIT29+BIT30
+*/
+#define FCH_MISC_REGF0 0xF0 // SataPortSts
+/*
+FCH_MISC_REGF0 EQU 0F0h
+ Port0Sts EQU BIT0 ; The selected status of Port 0.
+ Port1Sts EQU BIT1 ; The selected status of Port 1
+ Port2Sts EQU BIT2 ; The selected status of Port 2.
+ Port3Sts EQU BIT3 ; The selected status of Port 3
+ Port4Sts EQU BIT4 ; The selected status of Port 4.
+ Port5Sts EQU BIT5 ; The selected status of Port 5
+ SataPortSel EQU BIT24+BIT25 ; 00 - Select "led" for Port 0 to 5
+ ; 01 - Select "delete" for Port 0 to 5
+ ; 10 - Select "err" for Port 0 to 5
+ ; 11 - Select "led" for Port 0 to 5
+*/
+
+//
+// FCH MMIO Base (SERIAL_DEBUG_BASE)
+// offset : 0x1000
+//
+#define FCH_SDB_REG00 0x00 //
+#define FCH_SDB_REG74 0x74
+
+#define FCH_RTC_REG00 0x00 // Seconds - RW
+#define FCH_RTC_REG01 0x01 // Seconds Alarm - RW
+#define FCH_RTC_REG02 0x02 // Minutes - RW
+#define FCH_RTC_REG03 0x03 // Minutes Alarm - RW
+#define FCH_RTC_REG04 0x04 // ours - RW
+#define FCH_RTC_REG05 0x05 // ours Alarm- RW
+#define FCH_RTC_REG06 0x06 // Day of Week - RW
+#define FCH_RTC_REG07 0x07 // Date of Mont - RW
+#define FCH_RTC_REG08 0x08 // Mont - RW
+#define FCH_RTC_REG09 0x09 // Year - RW
+#define FCH_RTC_REG0A 0x0A // Register A - RW
+#define FCH_RTC_REG0B 0x0B // Register B - RW
+#define FCH_RTC_REG0C 0x0C // Register C - R
+#define FCH_RTC_REG0D 0x0D // DateAlarm - RW
+#define FCH_RTC_REG32 0x32 // AltCentury - RW
+#define FCH_RTC_REG48 0x48 // Century - RW
+#define FCH_RTC_REG50 0x50 // Extended RAM Address Port - RW
+#define FCH_RTC_REG53 0x53 // Extended RAM Data Port - RW
+#define FCH_RTC_REG7E 0x7E // RTC Time Clear - RW
+#define FCH_RTC_REG7F 0x7F // RTC RAM Enable - RW
+
+#define FCH_ECMOS_REG00 0x00 // scratch - reg
+//;BIT0=0 AsicDebug is enabled
+//;BIT1=0 SLT S3 runs
+#define FCH_ECMOS_REG01 0x01
+#define FCH_ECMOS_REG02 0x02
+#define FCH_ECMOS_REG03 0x03
+#define FCH_ECMOS_REG04 0x04
+#define FCH_ECMOS_REG05 0x05
+#define FCH_ECMOS_REG06 0x06
+#define FCH_ECMOS_REG07 0x07
+#define FCH_ECMOS_REG08 0x08 // save 32BIT Physical address of Config structure
+#define FCH_ECMOS_REG09 0x09
+#define FCH_ECMOS_REG0A 0x0A
+#define FCH_ECMOS_REG0B 0x0B
+
+#define FCH_ECMOS_REG0C 0x0C //;save MODULE_ID
+#define FCH_ECMOS_REG0D 0x0D //;Reserve for NB
+
+//
+// FCH SMI Base (FCH_SMI_BASE)
+// offset : 0x0200
+//
+#define FCH_SMIx0C_Level 0xFED8020Cul // Level
+#define FCH_SMIx58_EHCI_WAKE 0xFED80258ul // EHCI WAKE
+#define FCH_SMIx78_XHCI_WAKE 0xFED80278ul // XHCI WAKE
+
+#define FCH_SMIx88_SmiStatus2 0xFED80288ul // SmiStatus2
+#define FCH_SMIx88_SmiStatus2_UsbSmiEvent76 ( 1 << 12 )
+
+//
+// FCH PMIO Base (FCH_PMIO_BASE)
+// offset : 0x0300
+//
+#define FCH_PMIOx10_Power_Reset_Config 0xFED80310ul //Power Reset Config
+#define FCH_PMIOx10_Power_Reset_Config_ToggleAllPwrGoodOnCf9 (1 << 1)
+
+#define FCH_PMIOx74_AcpiConfig 0xFED80374ul // AcpiConfig
+#define FCH_PMIOx74_AcpiConfig_PwnBtnEn (1 << 8)
+#define FCH_PMIOx74_AcpiConfig_AcpiReducedHwEn (1 << 9)
+
+#define FCH_PMIOxC0_S5ResetStatus 0xFED803C0ul // S5ResetStatus
+#define FCH_PMIOxC0_S5ResetStatus_ThermalTrip (1 << 0)
+#define FCH_PMIOxC0_S5ResetStatus_FourSecondPwrBtn (1 << 1)
+#define FCH_PMIOxC0_S5ResetStatus_S_Status (0x3ff | (1 << 20))
+#define FCH_PMIOxC0_S5ResetStatus_All_Status 0x3FFF03FFul
+
+#define FCH_PMxC8_Misc 0xFED803C8ul // Misc
+#define FCH_PMxC8_Misc_UseAcpiStraps (1 << 4)
+
+#define FCH_PMxE8_SDFlashCntrl 0xFED803E8ul // SDFlashCntrl
+#define FCH_PMxE8_SDFlashCntrl_SdCd2Acpi (1 << 5)
+//
+// FCH MISC Base (FCH_MISC_BASE)
+// offset : 0x0E00
+//
+#define FCH_MISCx28_ClkDrvStr2 0xFED80E28ul // ClkDrvStr2
+
+#define FCH_MISCx40_MiscClkCntl1 0xFED80E40ul // MiscClkCntl1
+#define FCH_MISCx40_MiscClkCntl1_CG1PLL_FBDIV_Test (1 << 26)
+
+#define FCH_MISCx50_JTAG_Control_ECO_bits 0xFED80E50ul // JTAG_Control_ECO_bits
+#define FCH_MISCx50_JTAG_Control_ECO_bits_BIT12 (1 << 12)
+#define FCH_MISCx50_JTAG_Control_ECO_bits_BIT16 (1 << 16)
+
+// FCH GPIO
+// offset : 0x1500
+//
+#define FCH_GPIOx018_AGPIO6_LDT_RST_L 0xFED81518ul //
+#define FCH_GPIOx10C_DEVSLP0_EGPIO67 0xFED8160Cul //
+
+// FCH XHC PM (FCH_XHC_PM)
+// offset : 0x1C00
+//
+#define FCH_XHC_PMx00_Configure0 0xFED81C00ul //
+#define FCH_XHC_PMx00_Configure0_XHC_SMIB_EN BIT21
+#define FCH_XHC_PMx10_Xhc_Memory_Configure 0xFED81C10ul //
+#define FCH_XHC_PMx18_Usb20_Link_Status 0xFED81C18ul //
+#define FCH_XHC_PMx20_Usb20_Wake_Control 0xFED81C20ul //
+#define FCH_XHC_PMx24_Misc0 0xFED81C24ul //
+#define FCH_XHC_PMx28_Misc1 0xFED81C28ul //
+#define FCH_XHC_PMx2C_Misc2 0xFED81C2Cul //
+#define FCH_XHC_PMx30_Xhci10_Enable 0xFED81C30ul //
+#define FCH_XHC_PMx60_xHC_Battery_Charger_Enable 0xFED81C60ul //
+
+
+
+
+// FCH AOAC Base (FCH_AOAC_BASE)
+// offset : 0x1E00
+//
+#define FCH_AOACx40_D3_CONTROL 0xFED81E40ul //
+#define FCH_AOACx41_D3_STATUS 0xFED81E40ul //
+#define FCH_AOACx5E_SATA_D3_CONTROL 0xFED81E5Eul //
+#define FCH_AOACx6E_USB3_D3_CONTROL 0xFED81E6Eul //
+#define FCH_AOACx70_SD_D3_CONTROL 0xFED81E70ul //
+#define FCH_AOACx7A_IMC_D3_CONTROL 0xFED81E7Aul //
+#define FCH_AOACx88Shadow_Register_SRAM_Addr 0xFED81E88ul //
+#define FCH_AOACx8CShadow_Register_SRAM_Data 0xFED81E8Cul //
+#define FCH_AOACx94S013_CONTROL 0xFED81E94ul //
+#define FCH_AOACx94S013_CONTROL_ARBITER_DIS (1 << 14)
+#define FCH_AOACx94S013_CONTROL_INTERRUPT_DIS (1 << 15)
+#define FCH_AOACx9C_Shadow_Timer_Control 0xFED81E9Cul //
+#define FCH_AOACx9C_Shadow_Timer_Control_ShadowHpetEn (1 << 0) //
+#define FCH_AOACx9C_Shadow_Timer_Control_ShadowAcpiTimerEn (1 << 1) //
+
+#define FCH_AOACxA0_PwrGood_Control 0xFED81EA0ul //
+
+#define FCH_AOAC_REG00 0x00 // PerfMonControl
+#define FCH_AOAC_REG04 0x04 // PerfMonTimeLimit
+#define FCH_AOAC_REG08 0x08 // PerfMonWeight[3:0]
+#define FCH_AOAC_REG0C 0x0C // PerfMonWeight[7:4]
+#define FCH_AOAC_REG10 0x10 // PerfMonTrafficCnt[1:0]
+#define FCH_AOAC_REG14 0x14 // PerfMonTrafficCnt[3:2]
+#define FCH_AOAC_REG18 0x18 // PerfMonTrafficCnt[5:4]
+#define FCH_AOAC_REG1C 0x1C // PerfMonTrafficCnt[7:6]
+#define FCH_AOAC_REG20 0x20 // PerfMonTrafficCntAll
+#define FCH_AOAC_REG24 0x24 // PerfMonIntrCnt
+#define FCH_AOAC_REG28 0x28 //
+#define FCH_AOAC_REG2C 0x2C //
+#define FCH_AOAC_REG30 0x30 // Alternative HPET Timer
+#define FCH_AOAC_REG34 0x34 // Alternative HPET Timer (HIGH 32BITS)
+#define FCH_AOAC_REG38 0x38 // Alternative HPET Alarm
+#define FCH_AOAC_REG3C 0x3C // Alternative HPET Alarm (HIGH 32BITS)
+/*
+FCH_AOAC_REG4X-7x Control field
+*/
+#define AOAC_TARGET_DEVICE_STATE (BIT0 + BIT1) // TargetedDeviceState -
+ // 00 - D0 un-initialized
+ // 01 - D0 initialized
+ // 10 - D1/D2/D3hot
+ // 11 - D3cold
+ //
+#define AOAC_DEVICE_STATE BIT2 // DeviceState
+ // 0 - Device power is removed
+ // 1 - Device power is applied
+#define AOAC_PWR_ON_DEV BIT3 // PwrOnDev -
+ // If IsSwControl==0, software can write this bit to trigger a HW
+ // controlled power-down or reset sequence to the device.
+ // 0 - Power down the device.
+ // 1 - Power up the device.
+ //
+#define AOAC_SW_PWR_ON_RSTB BIT4 // SwPwrOnRstB -
+ //
+ // 0 - PwrRstB is asserted to the device if IsSwControl==1.
+ // 1 - 1=PwrRstB is de-asserted to the device if IsSwControl==1.
+ //
+#define AOAC_SW_REF_CLK_OK BIT5 // SwRefClkOk -
+ //
+ // 0 - 0=RefClkOk is de-asserted to the device if IsSwControl==1.
+ // 1 - RefClkOk is asserted to the device if IsSwControl==1.
+ //
+#define AOAC_SW_RST_B BIT6 // SwRstB -
+ // 0 - RstB is asserted to the device if IsSwControl==1.
+ // 1 - RstB is deasserted to the device if IsSwControl==1.
+ //
+#define AOAC_IS_SW_CONTROL BIT7 // IsSwControl
+ // To avoid glitch on the reset signals, software must set bit IsSwControl first before programming bit
+ // SwPwrOnRstB, SwRefClkOk and SwRstB.
+ // 0 - Hardware controls control signals (PwrRstB, RefClkOk, RstB) to the device.
+ // 1 - Software controls control signals (PwrRstB, RefClkOk, RstB) to the device.
+ //
+/*
+FCH_AOAC_REG4X-7x State field
+*/
+#define A0AC_PWR_RST_STATE BIT0
+#define AOAC_RST_CLK_OK_STATE BIT1
+#define AOAC_RST_B_STATE BIT2
+#define AOAC_DEV_OFF_GATING_STATE BIT3
+#define AOAC_D3COLD BIT4
+#define AOAC_CLK_OK_STATE BIT5
+#define AOAC_STAT0 BIT6
+#define AOAC_STAT1 BIT7
+#define FCH_AOAC_REG40 0x40 // ClkGen Control
+#define FCH_AOAC_REG41 0x41 // ClkGen State
+#define FCH_AOAC_REG42 0x42 // AB Control
+#define FCH_AOAC_REG43 0x43 // AB State
+#define FCH_AOAC_REG44 0x44 // ACPI S0 Control
+#define FCH_AOAC_REG45 0x45 // ACPI S0 State
+#define FCH_AOAC_REG46 0x46 // ACPI S5 Control
+#define FCH_AOAC_REG47 0x47 // ACPI S5 State
+#define FCH_AOAC_REG48 0x48 // LPC Control
+#define FCH_AOAC_REG49 0x49 // LPC State
+#define FCH_AOAC_REG4A 0x4A // I_2_C 0 Control
+#define FCH_AOAC_REG4B 0x4B // I_2_C 0 State
+#define FCH_AOAC_REG4C 0x4C // I_2_C 1 Control
+#define FCH_AOAC_REG4D 0x4D // I_2_C 1 State
+#define FCH_AOAC_REG4E 0x4E // I_2_C 2 Control
+#define FCH_AOAC_REG4F 0x4F // I_2_C 2 State
+#define FCH_AOAC_REG50 0x50 // I_2_C 3 Control
+#define FCH_AOAC_REG51 0x51 // I_2_C 3 State
+
+#define FCH_AOAC_REG56 0x56 // UART0 Control
+#define FCH_AOAC_REG57 0x57 // UART0 State
+#define FCH_AOAC_REG58 0x58 // UART1 Control
+#define FCH_AOAC_REG59 0x59 // UART1 State
+
+#define FCH_AOAC_REG5E 0x5E // SATA Control
+#define FCH_AOAC_REG5F 0x5F // SATA State
+
+#define FCH_AOAC_REG62 0x62 // AMBA Control
+#define FCH_AOAC_REG63 0x63 // AMBA State
+#define FCH_AOAC_REG64 0x64 // USB2 Control
+#define FCH_AOAC_REG65 0x65 // USB2 State
+
+#define FCH_AOAC_REG6E 0x6E // USB3 Control
+#define FCH_AOAC_REG6F 0x6F // USB3 State
+#define FCH_AOAC_REG70 0x70 // SD Control
+#define FCH_AOAC_REG71 0x71 // SD State
+
+#define FCH_AOAC_REG76 0x76 // eSPI Control
+#define FCH_AOAC_REG77 0x77 // eSPI State
+
+#define FCH_AOAC_REG7A 0x7A // IMC Control
+#define FCH_AOAC_REG7B 0x7B // IMC State
+#define FCH_AOAC_REG7C 0x7C // NB Control
+#define FCH_AOAC_REG7D 0x7D // NB State
+#define FCH_AOAC_REG7E 0x7E // APU Control
+#define FCH_AOAC_REG7F 0x7F // APU State
+#define FCH_AOAC_REG80 0x80 //
+#define FCH_AOAC_REG84 0x84 //
+#define FCH_AOAC_REG88 0x88 //
+#define FCH_AOAC_REG8C 0x8C //
+#define FCH_AOAC_REG90 0x90 //
+#define FCH_AOAC_REG94 0x94 //
+#define FCH_AOAC_REG98 0x98 //
+#define FCH_AOAC_REG9C 0x9C //
+#define FCH_AOAC_REGA0 0xA0 //
+#define FCH_AOAC_REGA4 0xA4 //
+#define FCH_AOAC_REGA8 0xA8 //
+#define FCH_AOAC_REGAC 0xAC //
+#define FCH_AOAC_REGB0 0xB0 //
+#define FCH_AOAC_REGB4 0xB4 //
+#define FCH_AOAC_REGB8 0xB8 //
+#define FCH_AOAC_REGBC 0xBC //
+#define FCH_AOAC_REGC0 0xC0 //
+#define FCH_AOAC_REGC4 0xC4 //
+#define FCH_AOAC_REGC8 0xC8 //
+#define FCH_AOAC_REGCC 0xCC //
+#define FCH_AOAC_REGD0 0xD0 //
+#define FCH_AOAC_REGD4 0xD4 //
+#define FCH_AOAC_REGD8 0xD8 //
+#define FCH_AOAC_REGDC 0xDC //
+#define FCH_AOAC_REGE0 0xE0 //
+#define FCH_AOAC_REGE4 0xE4 //
+#define FCH_AOAC_REGE8 0xE8 //
+#define FCH_AOAC_REGEC 0xEC //
+#define FCH_AOAC_REGF0 0xF0 //
+#define FCH_AOAC_REGF4 0xF4 //
+#define FCH_AOAC_REGF8 0xF8 //
+#define FCH_AOAC_REGFC 0xFC //
+#define FCH_AOACx98S013_DEBUG 0xFED81E98ul //
+#define FCH_AOACx98S013_DEBUG_BYPASS_SHDW_TMR (1 << 8)
+#define FCH_AOACx98S013_DEBUG_BYPASS_SHDW_REG (1 << 9)
+//Set S0I3_BypassShdwTmr in AOAC offset 0x98 bit 8 to 0
+//Set S0I3_BypassShdwReg in AOAC offset 0x98 bit 9 to 1
+
+#define FCH_AOACx9CS013_TIMER_CONTROL 0xFED81E9Cul //
+#define FCH_AOACx9CS013_TIMER_CONTROL_SHADOW_HPET_EN (1 << 0)
+#define FCH_AOACx9CS013_TIMER_CONTROL_EARLY_COUNT_UNIT (1 << 2)
+#define FCH_AOACx9CS013_TIMER_CONTROL_EARLY_COUNT_MASK (0xff << 8)
+#define FCH_AOACx9CS013_TIMER_CONTROL_EARLY_COUNT_VALUE (0x23 << 8)
+//Set ShadowHPETEn in AOAC offset 0x9C bit 0 to 1
+//Set EarlyCountUnit in AOAC offset 0x9C bit 2 to 1
+//Program EarlyCount in AOAC offset 0x9C bit[15:8]. (please set 0x23 for now)
+
+
+#define FCH_AL2AHBx10_CONTROL 0xFEDC0010ul //
+#define FCH_AL2AHBx10_CONTROL_CLOCK_GATE_EN (1 << 1)
+
+#define FCH_AL2AHBx30_HCLK_CONTROL 0xFEDC0030ul //
+#define FCH_AL2AHBx30_HCLK_CONTROL_CLOCK_GATE_EN (1 << 1)
+
+#define FCH_IOMAP_REG00 0x000 // Dma_C 0
+#define FCH_IOMAP_REG02 0x002 // Dma_C 1
+#define FCH_IOMAP_REG04 0x004 // Dma_C 2
+#define FCH_IOMAP_REG06 0x006 // Dma_C 3
+#define FCH_IOMAP_REG08 0x008 // Dma_Status
+#define FCH_IOMAP_REG09 0x009 // Dma_WriteRest
+#define FCH_IOMAP_REG0A 0x00A // Dma_WriteMask
+#define FCH_IOMAP_REG0B 0x00B // Dma_WriteMode
+#define FCH_IOMAP_REG0C 0x00C // Dma_Clear
+#define FCH_IOMAP_REG0D 0x00D // Dma_MasterClr
+#define FCH_IOMAP_REG0E 0x00E // Dma_ClrMask
+#define FCH_IOMAP_REG0F 0x00F // Dma_AllMask
+#define FCH_IOMAP_REG20 0x020 // IntrCntrlReg1
+#define FCH_IOMAP_REG21 0x021 // IntrCntrlReg2
+#define FCH_IOMAP_REG40 0x040 // TimerC0
+#define FCH_IOMAP_REG41 0x041 // TimerC1
+#define FCH_IOMAP_REG42 0x042 // TimerC2
+#define FCH_IOMAP_REG43 0x043 // Tmr1CntrlWord
+#define FCH_IOMAP_REG61 0x061 // Nmi_Status
+#define FCH_IOMAP_REG70 0x070 // Nmi_Enable
+#define FCH_IOMAP_REG71 0x071 // RtcDataPort
+#define FCH_IOMAP_REG72 0x072 // AlternatRtcAddrPort
+#define FCH_IOMAP_REG73 0x073 // AlternatRtcDataPort
+#define FCH_IOMAP_REG80 0x080 // Dma_Page_Reserved0
+#define FCH_IOMAP_REG81 0x081 // Dma_PageC2
+#define FCH_IOMAP_REG82 0x082 // Dma_PageC3
+#define FCH_IOMAP_REG83 0x083 // Dma_PageC1
+#define FCH_IOMAP_REG84 0x084 // Dma_Page_Reserved1
+#define FCH_IOMAP_REG85 0x085 // Dma_Page_Reserved2
+#define FCH_IOMAP_REG86 0x086 // Dma_Page_Reserved3
+#define FCH_IOMAP_REG87 0x087 // Dma_PageC0
+#define FCH_IOMAP_REG88 0x088 // Dma_Page_Reserved4
+#define FCH_IOMAP_REG89 0x089 // Dma_PageC6
+#define FCH_IOMAP_REG8A 0x08A // Dma_PageC7
+#define FCH_IOMAP_REG8B 0x08B // Dma_PageC5
+#define FCH_IOMAP_REG8C 0x08C // Dma_Page_Reserved5
+#define FCH_IOMAP_REG8D 0x08D // Dma_Page_Reserved6
+#define FCH_IOMAP_REG8E 0x08E // Dma_Page_Reserved7
+#define FCH_IOMAP_REG8F 0x08F // Dma_Refres
+#define FCH_IOMAP_REG92 0x092 // FastInit
+#define FCH_IOMAP_REGA0 0x0A0 // IntrCntrl2Reg1
+#define FCH_IOMAP_REGA1 0x0A1 // IntrCntrl2Reg2
+#define FCH_IOMAP_REGC0 0x0C0 // Dma2_C4Addr
+#define FCH_IOMAP_REGC2 0x0C2 // Dma2_C4Cnt
+#define FCH_IOMAP_REGC4 0x0C4 // Dma2_C5Addr
+#define FCH_IOMAP_REGC6 0x0C6 // Dma2_C5Cnt
+#define FCH_IOMAP_REGC8 0x0C8 // Dma2_C6Addr
+#define FCH_IOMAP_REGCA 0x0CA // Dma2_C6Cnt
+#define FCH_IOMAP_REGCC 0x0CC // Dma2_C7Addr
+#define FCH_IOMAP_REGCE 0x0CE // Dma2_C7Cnt
+#define FCH_IOMAP_REGD0 0x0D0 // Dma_Status
+#define FCH_IOMAP_REGD2 0x0D2 // Dma_WriteRest
+#define FCH_IOMAP_REGD4 0x0D4 // Dma_WriteMask
+#define FCH_IOMAP_REGD6 0x0D6 // Dma_WriteMode
+#define FCH_IOMAP_REGD8 0x0D8 // Dma_Clear
+#define FCH_IOMAP_REGDA 0x0DA // Dma_Clear
+#define FCH_IOMAP_REGDC 0x0DC // Dma_ClrMask
+#define FCH_IOMAP_REGDE 0x0DE // Dma_ClrMask
+#define FCH_IOMAP_REGED 0x0ED // DUMMY IO PORT
+#define FCH_IOMAP_REGF0 0x0F0 // NCP_Error
+#define FCH_IOMAP_REG40B 0x040B // DMA1_Extend
+#define FCH_IOMAP_REG4D0 0x04D0 // IntrEdgeControl
+#define FCH_IOMAP_REG4D6 0x04D6 // DMA2_Extend
+#define FCH_IOMAP_REGC00 0x0C00 // Pci_Intr_Index
+#define FCH_IOMAP_REGC01 0x0C01 // Pci_Intr_Data
+#define FCH_IOMAP_REGC14 0x0C14 // Pci_Error
+#define FCH_IOMAP_REGC50 0x0C50 // CMIndex
+#define FCH_IOMAP_REGC51 0x0C51 // CMData
+#define FCH_IOMAP_REGC52 0x0C52 // GpmPort
+#define FCH_IOMAP_REGC6F 0x0C6F // Isa_Misc
+#define FCH_IOMAP_REGCD0 0x0CD0 // PMio2_Index
+#define FCH_IOMAP_REGCD1 0x0CD1 // PMio2_Data
+#define FCH_IOMAP_REGCD4 0x0CD4 // BIOSRAM_Index
+#define FCH_IOMAP_REGCD5 0x0CD5 // BIOSRAM_Data
+#define FCH_IOMAP_REGCD6 0x0CD6 // PM_Index
+#define FCH_IOMAP_REGCD7 0x0CD7 // PM_Data
+#define FCH_IOMAP_REGCF9 0x0CF9 // CF9Rst reg
+
+#define FCH_IRQ_INTA 0x00 // INTA#
+#define FCH_IRQ_INTB 0x01 // INTB#
+#define FCH_IRQ_INTC 0x02 // INTC#
+#define FCH_IRQ_INTD 0x03 // INTD#
+#define FCH_IRQ_INTE 0x04 // INTE#
+#define FCH_IRQ_INTF 0x05 // INTF#
+#define FCH_IRQ_INTG 0x06 // INTG#
+#define FCH_IRQ_INTH 0x07 // INTH#
+#define FCH_IRQ_SCI 0x10 // SCI
+#define FCH_IRQ_SMBUS0 0x11 // SMBUS0
+#define FCH_IRQ_ASF 0x12 // ASF
+#define FCH_IRQ_HDAUDIO 0x13 // HD Audio
+#define FCH_IRQ_FC 0x14 // FC
+#define FCH_IRQ_GEC 0x15 // GEC
+#define FCH_IRQ_SD 0x17 // SD
+#define FCH_IRQ_IMCINT0 0x20 // IMC INT0
+#define FCH_IRQ_IMCINT1 0x21 // IMC INT1
+#define FCH_IRQ_IMCINT2 0x22 // IMC INT2
+#define FCH_IRQ_IMCINT3 0x23 // IMC INT3
+#define FCH_IRQ_IMCINT4 0x24 // IMC INT4
+#define FCH_IRQ_IMCINT5 0x25 // IMC INT5
+#define FCH_IRQ_USB18INTA 0x30 // Dev 18 (USB) INTA#
+#define FCH_IRQ_USB18INTB 0x31 // Dev 18 (USB) INTB#
+#define FCH_IRQ_USB19INTA 0x32 // Dev 19 (USB) INTA#
+#define FCH_IRQ_USB19INTB 0x33 // Dev 19 (USB) INTB#
+#define FCH_IRQ_USB22INTA 0x34 // Dev 22 (USB) INTA#
+#define FCH_IRQ_USB22INTB 0x35 // Dev 22 (USB) INTB#
+#define FCH_IRQ_USB20INTC 0x36 // Dev 20 (USB) INTC#
+#define FCH_IRQ_IDE 0x40 // IDE pci interrupt
+#define FCH_IRQ_SATA 0x41 // SATA pci interrupt
+#define FCH_IRQ_GPPINT0 0x50 // Gpp Int0
+#define FCH_IRQ_GPPINT1 0x51 // Gpp Int1
+#define FCH_IRQ_GPPINT2 0x52 // Gpp Int2
+#define FCH_IRQ_GPPINT3 0x53 // Gpp Int3
+#define FCH_IRQ_GPIO 0x62 // GPIO Controller
+#define FCH_IRQ_I2C0 0x70 // I2C0 Controller
+#define FCH_IRQ_I2C1 0x71 // I2C1 Controller
+#define FCH_IRQ_I2C2 0x72 // I2C2 Controller
+#define FCH_IRQ_I2C3 0x73 // I2C3 Controller
+#define FCH_IRQ_UART0 0x74 // UART0 Controller
+#define FCH_IRQ_UART1 0x75 // UART1 Controller
+#define FCH_IRQ_IOAPIC 0x80 // Select IRQ routing to IoApic mode
+#define FCH_IRQ_PIC 0x00 // Select IRQ routing to PIC mode
+
+#define FCH_IRQ_INTERNAL_SHARE 0x07 // Fch Internal Shared IRQ
+#define FCH_IRQ_GPIO_IRQ FCH_IRQ_INTERNAL_SHARE
+#define FCH_IRQ_I2C0_IRQ 3
+#define FCH_IRQ_I2C1_IRQ 15
+#define FCH_IRQ_I2C2_IRQ 6
+#define FCH_IRQ_I2C3_IRQ 14
+#define FCH_IRQ_UART0_IRQ 10
+#define FCH_IRQ_UART1_IRQ 11
+
+
+#define FCH_SPI_MMIO_REG00 0x00 //SPI_
+#define FCH_SPI_OPCODE 0x000000FFl //
+#define FCH_SPI_TX_COUNT 0x00000F00l //
+#define FCH_SPI_RX_COUNT 0x0000F000l //
+#define FCH_SPI_EXEC_OPCODE 0x00010000l //
+#define FCH_SPI_FIFO_PTR_CRL 0x00100000l //
+#define FCH_SPI_FIFO_PTR_INC 0x00200000l //
+#define FCH_SPI_BUSY 0x80000000l //
+#define FCH_SPI_MMIO_REG0C 0x0C //SPI_Cntrl1 Register
+#define FCH_SPI_PARAMETER 0x000000FFl //
+#define FCH_SPI_FIFO_PTR 0x00000700l //
+#define FCH_SPI_BYTE_PROGRAM 0xFF000000l //
+#define FCH_SPI_MMIO_REG1C 0x1C //
+#define FCH_SPI_RETRY_TIMES 0x3 //
+
+#define FCH_SPI_MMIO_REG1D 0x1D //
+#define FCH_SPI_MMIO_REG1E 0x1E //
+#define FCH_SPI_MMIO_REG1F 0x1F //
+#define FCH_SPI_MMIO_REG4E 0x4E //
+
+#define FCH_SPI_MMIO_REG1F_X05_TX_BYTE_COUNT 0x05 //
+#define FCH_SPI_MMIO_REG1F_X06_RX_BYTE_COUNT 0x06 //
+
+#define FCH_SPI_MMIO_REG20 0x20 //
+#define FCH_SPI_MMIO_REG22 0x22 //
+#define FCH_SPI_MMIO_REG2C 0x2C //
+#define FCH_SPI_MMIO_REG38 0x38 //
+#define FCH_SPI_MMIO_REG3C 0x3C //
+
+#define FCH_SPI_MMIO_REG45_CMDCODE 0x45 //
+#define FCH_SPI_MMIO_REG47_CMDTRIGGER 0x47 //
+#define FCH_SPI_MMIO_REG48_TXBYTECOUNT 0x48 //
+#define FCH_SPI_MMIO_REG4B_RXBYTECOUNT 0x4B //
+#define FCH_SPI_MMIO_REG4C_SPISTATUS 0x4C //
+#define FCH_SPI_MMIO_REG80_FIFO 0x80 //
+
+#define FCH_SPI_MODE_FAST 0x7 //
+#define FCH_SPI_MODE_NORMAL 0x6 //
+#define FCH_SPI_MODE_QUAL_144 0x5 //
+#define FCH_SPI_MODE_QUAL_122 0x4 //
+#define FCH_SPI_MODE_QUAL_114 0x3 //
+#define FCH_SPI_MODE_QUAL_112 0x2 //
+
+#define FCH_SPI_DEVICE_MODE_DIS 0x7 //
+#define FCH_SPI_DEVICE_MODE_144 0x4 //
+#define FCH_SPI_DEVICE_MODE_114 0x3 //
+#define FCH_SPI_DEVICE_MODE_122 0x2 //
+#define FCH_SPI_DEVICE_MODE_112 0x1 //
+#define FCH_SPI_DEVICE_MODE_FAST 0x0 //
+
+#define FCH_SPI_SPEED_16M 0x4 //
+#define FCH_SPI_SPEED_22M 0x3 //
+#define FCH_SPI_SPEED_33M 0x2 //
+#define FCH_SPI_SPEED_66M 0x1 //
+#define FCH_SPI_SPEED_100M 0x5 //
+
+#define AMD_NB_REG78 0x78
+#define AMD_NB_SCRATCH AMD_NB_REG78
+#define MailBoxPort 0x3E
+
+#define MAX_LT_POLLINGS 0x4000
+#define SMI_TIMER_ENABLE BIT15
+
+#define ACPIMMIO32(x) (*(volatile UINT32*)(UINTN)(x))
+#define ACPIMMIO16(x) (*(volatile UINT16*)(UINTN)(x))
+#define ACPIMMIO8(x) (*(volatile UINT8*)(UINTN)(x))
+
+#define U3PLL_LOCK BIT7
+#define U3PLL_RESET BIT8
+#define U3PHY_RESET BIT9
+#define U3CORE_RESET BIT10
+#define XHC0_FUNC_RESET BIT11
+#define XHC1_FUNC_RESET BIT12
+
+#define XHCI_ACPI_MMIO_AMD_REG00 0x00
+#define XHCI_ACPI_MMIO_AMD_REG04 0x04
+#define XHCI_ACPI_MMIO_AMD_REG08 0x08
+#define XHCI_ACPI_MMIO_AMD_REG10 0x10
+#define XHCI_ACPI_MMIO_AMD_REG14 0x14
+#define XHCI_ACPI_MMIO_AMD_REG20 0x20
+#define XHCI_ACPI_MMIO_AMD_REG24 0x24
+#define XHCI_ACPI_MMIO_AMD_REG28 0x28
+#define XHCI_ACPI_MMIO_AMD_REG30 0x30
+#define XHCI_ACPI_MMIO_AMD_REG40 0x40
+#define XHCI_ACPI_MMIO_AMD_REG48 0x48 // USB3.0_Ind_REG Index
+#define XHCI_ACPI_MMIO_AMD_REG4C 0x4C // USB2.0_Ind_REG Data
+#define XHCI_ACPI_MMIO_AMD_REG8C 0x8C
+#define XHCI_ACPI_MMIO_AMD_REG90 0x90 // adaptation timer settings
+#define XHCI_ACPI_MMIO_AMD_REG98 0x98
+#define XHCI_ACPI_MMIO_AMD_REGA0 0xA0 // BAR 0
+#define XHCI_ACPI_MMIO_AMD_REGA4 0xA4 // BAR 1
+#define XHCI_ACPI_MMIO_AMD_REGA8 0xA8 // BAR 2
+#define XHCI_ACPI_MMIO_AMD_REGB0 0xB0 // SPI_Valid_Base.
+#define XHCI_ACPI_MMIO_AMD_REGC0 0xC0 // Firmware starting offset for coping
+#define XHCI_ACPI_MMIO_AMD_REGB4 0xB4
+#define XHCI_ACPI_MMIO_AMD_REGD0 0xD0
+
+#define FCH_XHCI_REG48 0x48 // XHCI IND_REG Index registers
+#define FCH_XHCI_REG4C 0x4C // XHCI IND_REG Data registers
+
+#define FCH_XHCI_IND60_BASE 0x40000000ul //
+
+#define FCH_XHCI_IND60_REG00 FCH_XHCI_IND60_BASE + 0x00 //
+#define FCH_XHCI_IND60_REG04 FCH_XHCI_IND60_BASE + 0x04 //
+#define FCH_XHCI_IND60_REG08 FCH_XHCI_IND60_BASE + 0x08 //
+#define FCH_XHCI_IND60_REG0C FCH_XHCI_IND60_BASE + 0x0C //
+#define FCH_XHCI_IND60_REG18 FCH_XHCI_IND60_BASE + 0x18 //
+#define FCH_XHCI_IND60_REG48 FCH_XHCI_IND60_BASE + 0x48 //
+#define FCH_XHCI_IND60_REG50 FCH_XHCI_IND60_BASE + 0x50 //
+#define FCH_XHCI_IND60_REG54 FCH_XHCI_IND60_BASE + 0x54 //
+#define FCH_XHCI_IND60_REG58 FCH_XHCI_IND60_BASE + 0x58 //
+#define FCH_XHCI_IND60_REG5C FCH_XHCI_IND60_BASE + 0x5C //
+#define FCH_XHCI_IND60_REG68 FCH_XHCI_IND60_BASE + 0x68 //
+#define FCH_XHCI_IND60_REG6C FCH_XHCI_IND60_BASE + 0x6C //
+
+#define FCH_XHCI_IND_REG00 0x00 //
+#define FCH_XHCI_IND_REG04 0x04 //
+#define FCH_XHCI_IND_REG48 0x48 //
+#define FCH_XHCI_IND_REG54 0x54 //
+#define FCH_XHCI_IND_REG88 0x88 //
+#define FCH_XHCI_IND_REG94 0x94 // adaptation mode settings
+#define FCH_XHCI_IND_REG98 0x98 // CR phase and frequency filter settings
+#define FCH_XHCI_IND_REGC8 0xC8 //
+#define FCH_XHCI_IND_REGD4 0xD4 // adaptation mode settings
+#define FCH_XHCI_IND_REGD8 0xD8 // CR phase and frequency filter settings
+#define FCH_XHCI_IND_REG100 0x100 //
+#define FCH_XHCI_IND_REG120 0x120 //
+#define FCH_XHCI_IND_REG128 0x128 //
+#define FCH_XHCI_IND_REG200 0x200 //
+#define FCH_XHCI_IND_REG240 0x240 //
+#define FCH_XHCI_IND_REG280 0x280 //
+#define FCH_XHCI_IND_REG2C0 0x2C0 //
+#define MAX_XHCI_PORTS 0x04
+
+//SMBUS
+#define FCH_SMB_IOREG00 0x00 // SMBusStatus
+#define FCH_SMB_IOREG01 0x01 // SMBusSlaveStatus
+#define FCH_SMB_IOREG02 0x02 // SMBusControl
+#define FCH_SMB_IOREG03 0x03 // SMBusHostCmd
+#define FCH_SMB_IOREG04 0x04 // SMBusAddress
+#define FCH_SMB_IOREG05 0x05 // SMBusData0
+#define FCH_SMB_IOREG06 0x06 // SMBusData1
+#define FCH_SMB_IOREG07 0x07 // SMBusBlockData
+#define FCH_SMB_IOREG08 0x08 // SMBusSlaveControl
+#define FCH_SMB_IOREG14 0x14 // SMBusAutoPoll
+#define FCH_SMB_IOREG16 0x16 // SMBusPausePoll
+#define FCH_SMB_IOREG17 0x17 // SMBusHostCmd2
+
+#define FCH_SMB_CMD_QUICK 0x00 << 2 // Quick Read or Write
+#define FCH_SMB_CMD_BYTE 0x01 << 2 // Byte Read or Write
+#define FCH_SMB_CMD_BYTE_DATA 0x02 << 2 // Byte Data Read or Write
+#define FCH_SMB_CMD_WORD_DATA 0x03 << 2 // Word Data Read or Write
+#define FCH_SMB_CMD_BLOCK 0x05 << 2 // Block Read or Write
+
+#define FCH_SMB_ALL_HOST_STATUS 0x1f // HostBusy+SMBInterrupt+DeviceErr+BusCollision+Failed
+#define FCH_SMB_CMD_BYTE_DATA_START 0x48 // Byte Data Read or Write
+#define FCH_SMB_CMD_START BIT6
+#define FCH_SMB_READ_ENABLE BIT0
+#define FCH_SMB_AUTO_POLL_EN BIT0
+#define FCH_SMB_POLL2BYTE BIT7
+
+#define SBTSI_ADDR 0x98
+#define SBTSI_REG01 0x01
+#define SBTSI_REG09 0x09
+#define SBTSI_REG10 0x10
+#define SBTSI_READORDER BIT5
+
+#define FCH_EC_ENTER_CONFIG 0X5A
+#define FCH_EC_EXIT_CONFIG 0XA5
+#define FCH_EC_REG07 0X07
+#define FCH_EC_REG30 0X30
+#define FCH_EC_REG60 0X60
+#define FCH_EC_REG61 0X61
+
+#define FCH_IMC_ROMSIG 0x55aa55aaul
+
+#define SPI_HEAD_LENGTH 0x0E
+#define SPI_BAR0_VLD 0x01
+#define SPI_BASE0 (0x00 << 7)
+#define SPI_BAR1_VLD (0x01 << 8)
+#define SPI_BASE1 (SPI_HEAD_LENGTH << 10)
+#define SPI_BAR2_VLD (0x01 << 16)
+#define SPI_BASE2(x) ((SPI_HEAD_LENGTH + ACPIMMIO16(x)) << 18)
+
+#define FW_TO_SIGADDR_OFFSET 0x0C
+#define BCD_ADDR_OFFSET 0x02
+#define BCD_SIZE_OFFSET 0x04
+#define FW_ADDR_OFFSET 0x06
+#define FW_SIZE_OFFSET 0x08
+#define ACD_ADDR_OFFSET 0x0A
+#define ACD_SIZE_OFFSET 0x0C
+#define XHC_BOOT_RAM_SIZE 0x8000
+
+#define PKT_DATA_REG ACPI_MMIO_BASE + GFX_DAC_BASE + 0x00
+#define PKT_LEN_REG ACPI_MMIO_BASE + GFX_DAC_BASE + 0x14
+#define PKT_CTRL_REG ACPI_MMIO_BASE + GFX_DAC_BASE + 0x15
+#define EFUS_DAC_ADJUSTMENT_CONTROL 0x850A8ul
+#define BGADJ 0x1F
+#define DACADJ 0x1B
+#define EFUS_DAC_ADJUSTMENT_CONTROL_DATA (BGADJ + (DACADJ << 8) + BIT16 )
+
+#define KABINI_OSC_OUT_CLOCK_SEL_48MHz 0x02
+#define KABINI_OSC_OUT_CLOCK_SEL_25MHz 0x01
+
+#define KERN_OSC_OUT_CLOCK_SEL_48MHz 0x02
+#define KERN_OSC_OUT_CLOCK_SEL_25MHz 0x01
+
+#define RTC_WORKAROUND_SECOND 0x00
+#define RTC_VALID_SECOND_VALUE 0x59
+#define RTC_SECOND_RESET_VALUE 0x30
+#define RTC_SECOND_LOWER_NIBBLE 0x0F
+#define RTC_VALID_SECOND_VALUE_LN 0x09
+
+#ifndef FCH_DEADLOOP
+ #define FCH_DEADLOOP() { volatile UINTN __i; __i = 1; while (__i); }
+#endif
+
+#define OHCI_ARB_REGQ_VLD_EN BIT2
+
+#define HCEx40_Control 0xFED80040ul
+#define HCEx44_Input 0xFED80044ul
+#define HCEx48_Output 0xFED80048ul
+#define HCEx4C_Status 0xFED8004Cul
+#define HCEx50_IntrEn 0xFED80050ul
+#define EmulationSmiEn BIT4
+
+#define FCH_PMx08_PciControl 0xFED80308ul // PCI Control
+#define FCH_PMx08_PciControl_ShutDownOption BIT20
+
+#define FCH_PMxD2_PmioDebug 0xFED803D2ul // Pmio Debug
+#define FCH_PMxD6_Imc_Gating 0xFED803D6ul // IMC Gating
+#define FCH_PMxEC_LpcGating 0xFED803ECul // LPC Gating
+
diff --git a/src/vendorcode/amd/pi/00660F01/Proc/Fch/FchPlatform.h b/src/vendorcode/amd/pi/00660F01/Proc/Fch/FchPlatform.h
new file mode 100644
index 0000000..ca2a8d8
--- /dev/null
+++ b/src/vendorcode/amd/pi/00660F01/Proc/Fch/FchPlatform.h
@@ -0,0 +1,117 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * FCH platform definition
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: FCH
+ * @e \$Revision: 309090 $ @e \$Date: 2014-12-09 12:28:05 -0600 (Tue, 09 Dec 2014) $
+ *
+ */
+ /*****************************************************************************
+ *
+ * Copyright (c) 2008 - 2015, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ***************************************************************************/
+#ifndef _FCH_PLATFORM_H_
+#define _FCH_PLATFORM_H_
+
+#define MAX_SATA_PORTS 8
+
+#include "AGESA.h"
+
+#ifndef FCHOEM_ACPI_RESTORE_SWSMI
+ #define FCHOEM_BEFORE_PCI_RESTORE_SWSMI 0xD3
+ #define FCHOEM_AFTER_PCI_RESTORE_SWSMI 0xD4
+ #define FCHOEM_ENABLE_ACPI_SWSMI 0xA0
+ #define FCHOEM_DISABLE_ACPI_SWSMI 0xA1
+ #define FCHOEM_START_TIMER_SMI 0xBC
+ #define FCHOEM_STOP_TIMER_SMI 0xBD
+#endif
+
+#ifndef FCHOEM_SPI_UNLOCK_SWSMI
+ #define FCHOEM_SPI_UNLOCK_SWSMI 0xAA
+#endif
+#ifndef FCHOEM_SPI_LOCK_SWSMI
+ #define FCHOEM_SPI_LOCK_SWSMI 0xAB
+#endif
+
+#ifndef FCHOEM_ACPI_TABLE_RANGE_LOW
+ #define FCHOEM_ACPI_TABLE_RANGE_LOW 0xE0000ul
+#endif
+
+#ifndef FCHOEM_ACPI_TABLE_RANGE_HIGH
+ #define FCHOEM_ACPI_TABLE_RANGE_HIGH 0xFFFF0ul
+#endif
+
+#ifndef FCHOEM_ACPI_BYTE_CHECHSUM
+ #define FCHOEM_ACPI_BYTE_CHECHSUM 0x100
+#endif
+
+#ifndef FCHOEM_IO_DELAY_PORT
+ #define FCHOEM_IO_DELAY_PORT 0x80
+#endif
+
+#ifndef FCHOEM_OUTPUT_DEBUG_PORT
+ #define FCHOEM_OUTPUT_DEBUG_PORT 0x80
+#endif
+
+#define FCH_PCIRST_BASE_IO 0xCF9
+#define FCH_PCI_RESET_COMMAND06 0x06
+#define FCH_PCI_RESET_COMMAND0E 0x0E
+#define FCH_KBDRST_BASE_IO 0x64
+#define FCH_KBC_RESET_COMMAND 0xFE
+#define FCH_ROMSIG_BASE_IO 0x20000l
+#define FCH_ROMSIG_SIGNATURE 0x55AA55AAul
+#define FCH_MAX_TIMER 0xFFFFFFFFul
+#define FCH_GEC_INTERNAL_REG 0x6804
+#define FCH_HPET_REG_MASK 0xFFFFF800ul
+#define FCH_FAKE_USB_BAR_ADDRESS 0x58830000ul
+
+
+#ifndef FCHOEM_ELAPSED_TIME_UNIT
+ #define FCHOEM_ELAPSED_TIME_UNIT 28
+#endif
+
+#ifndef FCHOEM_ELAPSED_TIME_DIVIDER
+ #define FCHOEM_ELAPSED_TIME_DIVIDER 100
+#endif
+
+#include "Fch.h"
+#include "amdlib.h"
+#include "FchCommonCfg.h"
+#include "AcpiLib.h"
+#include "FchDef.h"
+#include "FchBiosRamUsage.h"
+#include "AmdFch.h"
+
+extern BUILD_OPT_CFG UserOptions;
+
+#endif // _FCH_PLATFORM_H_
diff --git a/src/vendorcode/amd/pi/00660F01/Proc/Fch/Kern/KernFch.h b/src/vendorcode/amd/pi/00660F01/Proc/Fch/Kern/KernFch.h
new file mode 100644
index 0000000..a20ec19
--- /dev/null
+++ b/src/vendorcode/amd/pi/00660F01/Proc/Fch/Kern/KernFch.h
@@ -0,0 +1,200 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * FCH registers definition
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: FCH
+ * @e \$Revision: 309090 $ @e \$Date: 2014-12-09 12:28:05 -0600 (Tue, 09 Dec 2014) $
+ *
+ */
+ /*****************************************************************************
+ *
+ * Copyright (c) 2008 - 2015, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ***************************************************************************/
+
+#define KERN_FCH_SATA_DID 0x7900
+#define KERN_FCH_SATA_AHCI_DID 0x7901
+#define KERN_FCH_SATA_AMDAHCI_DID 0x7904
+
+#define KERN_FCH_USB_XHCI_DID 0x7914 // Dev 0x10 Func 0
+#define KERN_FCH_USB_EHCI_DID 0x7908 // Dev 0x12 Func 0
+#define KERN_FCH_SMBUS_DID 0x790B // Dev 0x14 Func 0
+#define KERN_FCH_LPC_DID 0x790E // Dev 0x14 Func 3
+#define KERN_FCH_SD_DID 0x7906 // Dev 0x14 Func 7
+
+#define KERN_EHCI1_BUS_DEV_FUN ((0x12 << 3) + 0)
+#define KERN_EHCI1_BUS 0
+#define KERN_EHCI1_DEV 18
+#define KERN_EHCI1_FUNC 0
+#define KERN_EHCI2_BUS_DEV_FUN ((0x13 << 3) + 0)
+#define KERN_EHCI2_BUS 0
+#define KERN_EHCI2_DEV 19
+#define KERN_EHCI2_FUNC 0
+#define KERN_EHCI3_BUS_DEV_FUN ((0x16 << 3) + 0)
+#define KERN_EHCI3_BUS 0
+#define KERN_EHCI3_DEV 22
+#define KERN_EHCI3_FUNC 0
+
+// Specific FCH register for Kern
+#define FCH_EHCI_REG64 0x64
+#define FCH_EHCI_REGA4 0xA4
+
+// HD Audio/Azalia
+#define KERN_EVENT_HD_AUDIO_MSI_ENABLE 0x02010100ul // HD Audio/Azalia MSI enable.
+#define KERN_EVENT_HD_AUDIO_DISABLE 0x02010101ul // HD Audio/Azalia Disable.
+#define KERN_EVENT_HD_AUDIO_CONFIG_CODEC 0x02010102ul // HD Audio/Azalia Configure CODEC.
+#define KERN_EVENT_HD_AUDIO_CONFIG_CODEC_BUSY 0x02010103ul // HD Audio/Azalia Configure CODEC Reset.
+#define KERN_ERROR_HD_AUDIO_RESET 0x02030100ul // HD Audio/Azalia Reset Failure.
+#define KERN_ERROR_HD_AUDIO_CODEC 0x02030101ul // HD Audio/Azalia Codec Not Found.
+// HW ACPI
+#define KERN_EVENT_HWACPI_PROG_ACPI_PMTBL 0x02010200ul // FCH program ACPI PM Controller Base Address.
+#define KERN_EVENT_HWACPI_PROG_ACPI_MMIO_IN_RESET 0x02010201ul // FCH program ACPIMMIO registers in RESET.
+#define KERN_EVENT_HWACPI_PROG_SCI_MAP 0x02010202ul // FCH program SCI map by OEM table (ACPIMMIO 0xFED803xx).
+#define KERN_EVENT_HWACPI_PROG_GPIO_MAP 0x02010203ul // FCH program GPIO setting by OEM table (ACPIMMIO 0xFED801xx).
+#define KERN_EVENT_HWACPI_PROG_SATA_PHY 0x02010204ul // FCH program SATA PHY by OEM table.
+#define KERN_EVENT_RTC_DAYLIGHT_SAVING_TIME 0x02010205ul // FCH RTC DayLight Saving Workaround.
+#define KERN_EVENT_RTC_CLEAR_BANK_SELECTION 0x02010206ul // FCH RTC clear BankSelection 0x0A Bit4 prevent error.
+#define KERN_EVENT_RTC_WA 0x02010207ul // FCH RTC workaround is set.
+#define KERN_EVENT_KBD_CONNECTED_THRU_USB 0x02010208ul // FCH IRQ1/IRQ12 connected to USB controller.
+#define KERN_EVENT_LEGACY_FREE_SET 0x02010209ul // FCH None Legacy IO setting.
+#define KERN_EVENT_ENABLED_ASF_REMOTE_CTRL 0x0201020Aul // FCH Enable ASF remote control function.
+#define KERN_EVENT_PCIEXP_WAKESTATUS_WA 0x0201020Bul // FCH PciExp Wake Status Workaround.
+#define KERN_EVENT_HWACPI_PROG_OEM_MMIOTBL_IN_RESET 0x0201020Cul // FCH program OEM/Platform BIOS ACPIMMIO registers.
+#define KERN_EVENT_HWACPI_PROG_MMIOTBL 0x02010200ul // FCH program ACPIMMIO registers. (1st.)
+#define KERN_EVENT_HWACPI_NO_SIOKBC_ENABLE 0x02010201ul // FCH No SIO/KBC function is enabled.
+#define KERN_EVENT_HWACPI_NO_SIOKBC_DISABLE 0x02010202ul // FCH No SIO/KBC function is disabled.
+#define KERN_EVENT_HWACPI_PROG_SPECIFIC_MMIOTBL 0x02010203ul // FCH program Specific ACPIMMIO registers. (2nd.)
+#define KERN_EVENT_HWACPI_PROG_OEM_MMIOTBL 0x02010204ul // FCH program OEM/Platform BIOS ACPIMMIO registers (3rd.)
+#define KERN_EVENT_HWACPI_SPREAD_SPECTRUM 0x02010205ul // FCH Enable Spread Spectrum function.
+#define KERN_EVENT_HWACPI_INT_CLK_SET 0x02010206ul // FCH Set Intermal Clock Display as 48Mhz.
+#define KERN_EVENT_HPET_TIMER_TICK_INTERVAL_WA_SET 0x02010207ul // FCH HPET timer tick interval workaround is set.
+#define KERN_EVENT_C1E_ENABLE 0x02010208ul // FCH C1e Enabled.
+#define KERN_EVENT_NATIVEPCIE_MODE_SET 0x02010208ul // FCH Native PCIe mode is set.
+#define KERN_ERROR_HPET_TBL_NOT_FOUND 0x02030200ul // FCH HPET Table does not found.
+// HWM
+#define KERN_EVENT_IMC_DISABLE 0x02010300ul // FCH HWM/IMC is disabled.
+#define KERN_EVENT_IMC_ENABLE 0x02010301ul // FCH HWM/IMC is enabled.
+// IMC
+#define KERN_EVENT_IMC_SW_TOGGLE_EVENT 0x02010302ul // FCH IMC Software Toggle Strapping. (IMC statement change)
+#define KERN_EVENT_EC_ENABLE 0x02020303ul // FCH EC enabled.
+#define KERN_EVENT_EC_KBD_ENABLE 0x02010304ul // FCH IMC EC KBD enabled.
+#define KERN_EVENT_EC_CHANNEL0_ENABLE 0x02010305ul // FCH IMC EC channel0 function enabled.
+#define KERN_EVENT_IMC_INTO_SLEEP_MODE 0x02010306ul // FCH IMC goes into sleep mode.
+#define KERN_EVENT_IMC_CRASH_RESET 0x02010307ul // FCH IMC Crash Reset to prevent repeating the reset forever.
+#define KERN_EVENT_IMC_SW_DISABLE_IMC 0x02010308ul // FCH Software disable IMC thru mailbox command.
+#define KERN_EVENT_IMC_DISABLE_SUREBOOT_TIMMER 0x02010309ul // FCH Disable SureBoot Timmer.
+#define KERN_EVENT_IMC_WAKEUP 0x0201030Aul // FCH IMC wakeup command.
+#define KERN_EVENT_IMC_IDLE 0x0201030Bul // FCH IMC idle command.
+#define KERN_EVENT_EC_DISABLE 0x0201030Cul // FCH EC disable by jumper setting or board config.
+#define KERN_ERROR_IMC_FW_VALIDATE_FAILED 0x02030300ul // FCH IMC firmware validation failure.
+// PCIE/AB
+#define KERN_EVENT_AB_SLOW_SPEED_ABLINK_CLOCK 0x02010400ul // FCH Set Low Speed AB link clock.
+#define KERN_EVENT_AB_RESET_CPU_ON_SYNC_FLOOD 0x02010401ul // FCH set AB reset CPU on sync flood enabled.
+#define KERN_EVENT_AB_CLOCK_GATING_ENABLE 0x02010402ul // FCH set AB Clock Gating function enabled.
+#define KERN_EVENT_AB_CLOCK_GATING_DISABLE 0x02010403ul // FCH set AB clock Gating function disabled.
+#define KERN_EVENT_AB_DMA_MEMORY_W3264B_ENABLE 0x02010404ul // FCH set AB DMA MEMORY Write 32/64B enabled.
+#define KERN_EVENT_AB_DMA_MEMORY_W3264B_DISABLED 0x02010405ul // FCH set AB DMA MEMORY Write 32/64B disabled.
+#define KERN_EVENT_AB_MEMORY_POWERSAVING_ENABLED 0x02010406ul // FCH Set AB Memory Power Saving enabled.
+#define KERN_EVENT_AB_MEMORY_POWERSAVING_DISABLED 0x02010407ul // FCH Set AB Memory Power Saving disabled.
+#define KERN_EVENT_AB_ALINK_CLK_GATEOFF_ENABLED 0x02010408ul // FHC set ALink clock Gate-off enabled.
+#define KERN_EVENT_AB_ALINK_CLK_GATEOFF_DISABLED 0x02010409ul // FHC set ALink clock Gate-off disabled.
+#define KERN_EVENT_AB_BLINK_CLK_GATEOFF_ENABLED 0x0201040Aul // FHC set BLink clock Gate-off enabled.
+#define KERN_EVENT_AB_BLINK_CLK_GATEOFF_DISABLED 0x0201040Bul // FHC set BLink clock Gate-off disabled.
+// SATA
+#define KERN_EVENT_SATA_ENABLE 0x02010500ul // FCH set SATA controller enabled.
+#define KERN_EVENT_SATA_MAX_GEN2_MODE_ENABLE 0x02010501ul // FCH set SATA support only Max. GEN2 mode.
+#define KERN_EVENT_SATA_SET_CLK_SOURCE_ORG_EXT 0x02010502ul // FCH set SATA clock source as external 48Mhz.
+#define KERN_EVENT_SATA_SET_CLK_SOURCE_ORG_INT 0x02010502ul // FCH set SATA clock source as internal 48Mhz.
+#define KERN_EVENT_SATA_SET_CLK_SOURCE_100_INT 0x02010503ul // FCH set SATA clock source as internal 100Mhz.
+#define KERN_EVENT_SATA_STABLE_MEM_SHUTDOWN_ENABLE 0x02010504ul // FCH set SATA stable memory sutdown enable * Misc.
+#define KERN_EVENT_SATA_PROG_SATA_PORT_PHY 0x02010505ul // FCH programming SATA port's PHY.
+#define KERN_EVENT_SATA_READ_SQUELCH_FROM_EFUSE 0x02010506ul // FCH programming SATA squelch value from eFuse.
+#define KERN_EVENT_SATA_DISABLE 0x02010507ul // FCH set SATA controller disabled.
+#define KERN_EVENT_SATA_AHCI_MODE 0x02010508ul // FCH set SATA as AHCI mode.
+#define KERN_EVENT_SATA_IDE_2_AHCI_MODE 0x02010509ul // FCH set SATA as IDE_2_AHCI mode.
+#define KERN_EVENT_SATA_IDE_MODE 0x0201050Aul // FCH set SATA as IDE mode.
+#define KERN_EVENT_SATA_RAID_MODE 0x0201050Bul // FCH set SATA as RAID mode.
+#define KERN_EVENT_SATA_MSI_CAP_ENABLE 0x0201050Cul // FCH set SATA MSI Capability Enabled.
+#define KERN_EVENT_SATA_SUPPORT_8_DEVICE 0x0201050Dul // FCH set SATA support 8 device mode.
+#define KERN_EVENT_SATA_DISABLED_GENERIC_MODE 0x0201050Eul // FCH set SATA disable generic mode.
+#define KERN_EVENT_SATA_PHY_PLL_SHUTDOWN 0x0201050Ful // FCH set SATA PHY PLL shutdown.
+#define KERN_EVENT_SATA_OOB_DETECTION_ENH 0x02010510ul // FCH set SATA OOB Detection Enhance Mode.
+#define KERN_EVENT_SATA_MEM_POWER_SAVING 0x02010511ul // FCH set SATA memory power saving.
+#define KERN_EVENT_SATA_DEV_SLP_PORT0 0x02010512ul // FCH set SATA Deep Sleep Mode on Port0.
+#define KERN_EVENT_SATA_DEV_SLP_PORT1 0x02010513ul // FCH set SATA Deep Sleep Mode on Port1.
+#define KERN_EVENT_SATA_AHCI_DIS_PREFETCH 0x02010514ul // FCH set SATA AHCI disable Prefetch.
+#define KERN_EVENT_SATA_PORT_MULT_CAP 0x02010515ul // FCH set SATA Port Mult Capability Enabled.
+#define KERN_EVENT_SATA_FIS_BASE_SWITCHING 0x02010516ul // FCH set SATA support FIS-based switching.
+#define KERN_EVENT_SATA_AGGR_LINK_PM_CAP 0x02010517ul // FCH set SATA aggressive link power management.
+#define KERN_EVENT_SATA_PSC_CAP 0x02010518ul // FCH set SATA support partial state.
+#define KERN_EVENT_SATA_SSC_CAP 0x02010519ul // FCH set SATA support Slumber mode.
+#define KERN_EVENT_SATA_CCC_CAP 0x0201051Aul // FCH set SATA support command completion coalescing.
+#define KERN_EVENT_SATA_AHCI_ENCLOSURE_MANAGEMENT 0x0201051Bul // FCH set SATA support Enclosure Management.
+#define KERN_EVENT_SATA_ESP_PORT_ENABLE 0x0201051Cul // FCH set SATA ESP ports (one of ESP ports are set).
+#define KERN_EVENT_SATA_BIOS_OS_HANDOFF 0x0201051Dul // FCH set SATA HBA supports the BIOS/OS handoff mechanism.
+#define KERN_EVENT_SATA_DRIVE_DETECTION 0x0201051Eul // FCH SATA is excuting SATA drive detection.
+#define KERN_EVENT_SATA_CLK_AUTO_OFF 0x0201051Ful // FCH set SATA Auto Clock off function.
+#define KERN_EVENT_SATA_PORT_GEN_MODE 0x02010520ul // FCH set SATA port GEN mode.
+#define KERN_EVENT_SATA_HOT_REMOVAL_ENH 0x02010521ul // FCH set SATA hot removal enhance mode.
+// SD
+#define KERN_EVENT_SD_ENABLE 0x02010600ul // FCH set SD controller to enable.
+#define KERN_EVENT_SD_AS_DMA_MODE 0x02010601ul // FCH set SD as DMA mode.
+#define KERN_EVENT_SD_AS_PIO_MODE 0x02010602ul // FCH set SD as PIO mode.
+#define KERN_EVENT_SD_AS_2_0_MODE 0x02010603ul // FCH set SD as 2.0 mode.
+#define KERN_EVENT_SD_AS_3_0_MODE 0x02010604ul // FCH set SD as 3.0 mode.
+#define KERN_EVENT_SD_CLOCK_MULTIPLIER 0x02010605ul // FCH set SD clock multiplier.
+#define KERN_EVENT_SD_DISABLE 0x02010606ul // FCH set SD controller to disable.
+// LPC/SPI
+#define KERN_EVENT_LPC_CLK0_DISABLE 0x02010700ul // FCH set LPC0 clock disabled.
+#define KERN_EVENT_LPC_CLK1_DISABLE 0x02010701ul // FCH set LPC1 clock disabled.
+#define KERN_EVENT_LPC_LEGACY_FREE_MODE 0x02010702ul // FCH set LPC as legacy free mode.
+#define KERN_EVENT_SPI_QUAL_MODE 0x02010703ul // FCH SPI Qual Mode is enabled (by user selection).
+#define KERN_EVENT_SPI_SPEED 0x02010704ul // FCH SPI speed is set by user selection.
+#define KERN_EVENT_SPI_FAST_SPEED 0x02010705ul // FCH SPI fast speed is set.
+#define KERN_EVENT_SPI_QUALIFY_QUAL_MODE 0x02010706ul // FCH SPI Qual Mode is validated.
+// USB
+#define KERN_ERROR_USB_ROMSIG_NOT_FOUND 0x02030800ul // FCH ROMSIG not found.
+#define KERN_ERROR_USB_XHCI_FW_FOUND 0x02030801ul // FCH XHCI firmware does not exist.
+#define KERN_EVENT_USB_EHCI1_ENABLE 0x02010800ul // FCH set EHCI1 enable.
+#define KERN_EVENT_USB_EHCI2_ENABLE 0x02010801ul // FCH set EHCI2 enable.
+#define KERN_EVENT_USB_EHCI3_ENABLE 0x02010802ul // FCH set EHCI3 enable.
+#define KERN_EVENT_USB_XHCI_DISABLE 0x02010803ul // FCH set XHCI disable.
+#define KERN_EVENT_USB_PHY_POWER_DOWN 0x02010804ul // FCH set USB PHY powerdown enable.
+#define KERN_EVENT_USB_PHY_CALIBRATED 0x02010805ul // FCH set USB PHY calibrated.
+#define KERN_EVENT_USB_PORT_PHY_SETTING 0x02010806ul // FCH set USB Port PHY setting.
+#define KERN_EVENT_USB_PORT_PHY_CLK_GATING 0x02010807ul // FCH set USB Port PHY Clock Gating.
+#define KERN_EVENT_USB_XHCI_USED_PREDEFINE_ADDRESS 0x02010808ul // FCH XHCI ROM location is used user-define address.
+#define KERN_EVENT_USB_XHCI_BOOTRAM_PRELOAD 0x02010809ul // FCH XHCI preload its BOOTRAM.
+#define KERN_EVENT_USB_XHCI_INSTRUCTRAM_PRELOAD 0x0201080Aul // FCH XHCI preload its InstructionRAM.
+#define KERN_EVENT_USB_XHCI_ROM_PREINIT_COMPLETED 0x0201080Bul // FCH XHCI preinit completed.
+#define KERN_EVENT_USB_XHCI0_ENABLE 0x0201080Cul // FCH set XHCI0 enable.
+#define KERN_EVENT_USB_XHCI1_ENABLE 0x0201080Dul // FCH set XHCI1 enable.
diff --git a/src/vendorcode/amd/pi/00660F01/Proc/Psp/PspBaseLib/PspBaseLib.c b/src/vendorcode/amd/pi/00660F01/Proc/Psp/PspBaseLib/PspBaseLib.c
new file mode 100644
index 0000000..20a359a
--- /dev/null
+++ b/src/vendorcode/amd/pi/00660F01/Proc/Psp/PspBaseLib/PspBaseLib.c
@@ -0,0 +1,464 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * PSP Base Library
+ *
+ * Contains interface to the PSP library
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: PSP
+ * @e \$Revision: 309090 $ @e \$Date: 2014-12-09 12:28:05 -0600 (Tue, 09 Dec 2014) $
+ *
+ */
+ /*****************************************************************************
+ *
+ * Copyright (c) 2008 - 2015, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ***************************************************************************/
+
+
+/*----------------------------------------------------------------------------------------
+ * M O D U L E S U S E D
+ *----------------------------------------------------------------------------------------
+ */
+#include "AGESA.h"
+#include "Filecode.h"
+#include "PspBaseLib.h"
+
+#define FILECODE PROC_PSP_PSPBASELIB_PSPBASELIB_FILECODE
+#define PSP_BAR1_TMP_BASE 0xFEA00000ul
+
+#define GET_PCI_BUS(Reg) (((UINT32) Reg >> 16) & 0xFF)
+#define GET_PCI_DEV(Reg) (((UINT32) Reg >> 11) & 0x1F)
+#define GET_PCI_FUNC(Reg) (((UINT32) Reg >> 8) & 0x7)
+#define GET_PCI_OFFSET(Reg) ((UINT32)Reg & 0xFF)
+
+#define PCI_CONFIG_SMU_INDIRECT_INDEX 0xB8 ///< Gnb Offset index for SMU mbox
+#define PCI_CONFIG_SMU_INDIRECT_DATA 0xBC ///< Gnb Offset data for SMU mbox
+
+#define SMU_CC_PSP_FUSES_STATUS 0xC0018000ul ///< offset in GNB to find PSP fusing
+#define SMU_CC_PSP_FUSES_SECURE BIT0 ///< BIT0
+#define SMU_CC_PSP_FUSES_FRA_ENABLE BIT1 ///< BIT1
+#define SMU_CC_PSP_FUSES_PROTO BIT2 ///< BIT2
+#define PLATFORM_SECURE_BOOT_EN BIT4 ///< BIT4
+
+
+#define PSP_BLANK_PART 0 ///< Blank part
+#define PSP_PROTO_PART SMU_CC_PSP_FUSES_PROTO ///< Proto Part
+#define PSP_NON_SECURE_PART (SMU_CC_PSP_FUSES_PROTO + SMU_CC_PSP_FUSES_PCPU_DIS) ///< Non Secure Part
+#define PSP_SECURE_PART (SMU_CC_PSP_FUSES_PROTO + SMU_CC_PSP_FUSES_SECURE) ///< Secure Part
+#define PSP_FRA_MODE (SMU_CC_PSP_FUSES_FRA_ENABLE + SMU_CC_PSP_FUSES_PROTO + SMU_CC_PSP_FUSES_SECURE) ///< FRA Part
+
+/*----------------------------------------------------------------------------------------
+ * D E F I N I T I O N S A N D M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ * T Y P E D E F S A N D S T R U C T U R E S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+/*----------------------------------------------------------------------------------------
+ * P R O T O T Y P E S O F L O C A L F U N C T I O N S
+ *----------------------------------------------------------------------------------------
+ */
+
+
+
+UINT32
+PspLibPciReadConfig (
+ IN UINT32 Register
+ )
+{
+ UINT32 Value;
+ PCI_ADDR PciAddr;
+
+ Value = 0;
+ PciAddr.AddressValue = MAKE_SBDFO (0, GET_PCI_BUS (Register), GET_PCI_DEV (Register), GET_PCI_FUNC (Register), GET_PCI_OFFSET (Register));
+
+ LibAmdPciRead (AccessWidth32, PciAddr, &Value, NULL);
+
+ return Value;
+}
+
+VOID
+PspLibPciWriteConfig (
+ IN UINT32 Register,
+ IN UINT32 Value
+ )
+{
+ PCI_ADDR PciAddr;
+ PciAddr.AddressValue = MAKE_SBDFO (0, GET_PCI_BUS (Register), GET_PCI_DEV (Register), GET_PCI_FUNC (Register), GET_PCI_OFFSET (Register));
+
+ LibAmdPciWrite (AccessWidth32, PciAddr, &Value, NULL);
+
+}
+
+UINT32
+PspLibPciReadPspConfig (
+ IN UINT16 Offset
+ )
+{
+ return (PspLibPciReadConfig ((UINT32) (PSP_PCI_BDA + Offset)));
+}
+
+VOID
+PspLibPciWritePspConfig (
+ IN UINT16 Offset,
+ IN UINT32 Value
+ )
+{
+ PspLibPciWriteConfig ((UINT32) (PSP_PCI_BDA + Offset), Value);
+}
+
+BOOLEAN
+GetPspDirBase (
+ IN OUT UINT32 *Address
+ )
+{
+ UINTN i;
+ FIRMWARE_ENTRY_TABLE *FirmwareTableBase;
+ CONST UINT32 RomSigAddrTable[] =
+ {
+ 0xFFFA0000, // --> 512KB base
+ 0xFFF20000, // --> 1MB base
+ 0xFFE20000, // --> 2MB base
+ 0xFFC20000, // --> 4MB base
+ 0xFF820000, // --> 8MB base
+ 0xFF020000 // --> 16MB base
+ };
+
+ for (i = 0; i < sizeof (RomSigAddrTable) / sizeof (UINT32); i++) {
+ FirmwareTableBase = (FIRMWARE_ENTRY_TABLE *) (UINTN) RomSigAddrTable[i];
+ // Search flash for unique signature 0x55AA55AA
+ if (FirmwareTableBase->Signature == FIRMWARE_TABLE_SIGNATURE) {
+ *Address = FirmwareTableBase->PspDirBase;
+ return TRUE;
+ }
+ }
+
+ return (FALSE);
+}
+
+BOOLEAN
+PSPEntryInfo (
+ IN PSP_DIRECTORY_ENTRY_TYPE EntryType,
+ IN OUT UINT64 *EntryAddress,
+ IN UINT32 *EntrySize
+ )
+{
+ PSP_DIRECTORY *PspDir;
+ UINTN i;
+
+ if (GetPspDirBase ((UINT32 *)&PspDir ) != TRUE) {
+ return FALSE;
+ }
+
+ for (i = 0; i < PspDir->Header.TotalEntries; i++) {
+ if (PspDir->PspEntry[i].Type == EntryType) {
+ *EntryAddress = PspDir->PspEntry[i].Location;
+ *EntrySize = PspDir->PspEntry[i].Size;
+ return (TRUE);
+ }
+ }
+
+ return (FALSE);
+}
+
+/**
+ Check if PSP device is present
+
+ @retval BOOLEAN 0: PSP Disabled, 1: PSP Enabled
+
+**/
+BOOLEAN
+CheckPspDevicePresent (
+ VOID
+ )
+{
+ UINT32 SecureFuseReg;
+ PspLibPciWriteConfig ( (UINT32)PCI_CONFIG_SMU_INDIRECT_INDEX, (UINT32)SMU_CC_PSP_FUSES_STATUS);
+ SecureFuseReg = PspLibPciReadConfig ( (UINT32)PCI_CONFIG_SMU_INDIRECT_DATA);
+
+ if (SecureFuseReg &= SMU_CC_PSP_FUSES_PROTO) {
+ return (TRUE);
+ }
+ return (FALSE);
+}
+
+/**
+ Check PSP Platform Seucre Enable State
+ HVB & Secure S3 (Resume vector set to Dram, & core content will restore by uCode)
+ will be applied if Psp Plaform Secure is enabled
+
+ @retval BOOLEAN 0: PSP Platform Secure Disabled, 1: PSP Platform Secure Enabled
+
+**/
+BOOLEAN
+CheckPspPlatformSecureEnable (
+ VOID
+ )
+{
+ UINT32 SecureFuseReg;
+ PspLibPciWriteConfig ( (UINT32)PCI_CONFIG_SMU_INDIRECT_INDEX, (UINT32)SMU_CC_PSP_FUSES_STATUS);
+ SecureFuseReg = PspLibPciReadConfig ( (UINT32)PCI_CONFIG_SMU_INDIRECT_DATA);
+
+ if (SecureFuseReg &= PLATFORM_SECURE_BOOT_EN) {
+ return (TRUE);
+ }
+ return (FALSE);
+}
+
+/**
+ Check PSP Recovery Flag
+ Target will set Recovery flag if some PSP entry point by PSP directory has been corrupted.
+
+ @retval BOOLEAN 0: Recovery Flag is cleared, 1: Recovery Flag has been set
+
+**/
+BOOLEAN
+CheckPspRecoveryFlag (
+ VOID
+ )
+{
+ MBOX_STATUS *MboxStatus;
+
+ //Init PSP MMIO
+ PspBarInitEarly ();
+
+ GetPspMboxStatus (&MboxStatus);
+
+ return (BOOLEAN) (MboxStatus->Recovery);
+}
+
+/**
+ Return the PspMbox MMIO location
+
+
+ @retval BOOLEAN FALSE: ERROR, TRUE: SUCCEED
+
+**/
+BOOLEAN
+GetPspMboxStatus (
+ IN OUT MBOX_STATUS **MboxStatus
+ )
+{
+ UINT32 PspMmio;
+
+ if (GetPspBar1Addr (&PspMmio) == FALSE) {
+ return (FALSE);
+ }
+
+ *MboxStatus = (MBOX_STATUS *)( (UINTN)PspMmio + PSP_MAILBOX_BASE + PSP_MAILBOX_STATUS_OFFSET); // PSPMbox base is at offset CP2MSG_28 ie. offset 28*4 = 0x70
+
+ return (TRUE);
+}
+
+BOOLEAN
+PspBarInitEarly (void)
+{
+ UINT32 PspMmioSize;
+ UINT32 Value32;
+
+ if (PspLibPciReadPspConfig (PSP_PCI_DEVID_REG) == 0xffffffff) {
+ return (FALSE);
+ }
+
+ //Check if PSP BAR has been assigned, if not do the PSP BAR initialation
+ if (PspLibPciReadPspConfig (PSP_PCI_BAR1_REG) == 0) {
+ /// Get PSP BAR1 Size
+ PspLibPciWritePspConfig (PSP_PCI_BAR1_REG, 0xFFFFFFFF);
+ PspMmioSize = PspLibPciReadPspConfig (PSP_PCI_BAR1_REG);
+ PspMmioSize = ~PspMmioSize + 1;
+ /// Assign BAR1 Temporary Address
+ PspLibPciWritePspConfig (PSP_PCI_BAR1_REG, PSP_BAR1_TMP_BASE);
+ PspLibPciWritePspConfig ( PSP_PCI_CMD_REG, 0x06);
+
+ /// Enable GNB redirection to this space @todo use equate & also find proper fix
+ PspLibPciWriteConfig ( ( (0x18 << 11) + (1 << 8) + 0xBC), ((PSP_BAR1_TMP_BASE + PspMmioSize -1) >> 8) & ~0xFF);
+ PspLibPciWriteConfig ( ( (0x18 << 11) + (1 << 8) + 0xB8), (PSP_BAR1_TMP_BASE >> 8) | 3);
+ /// Enable MsixBarEn, Bar1En, Bar3En
+ PspLibPciWritePspConfig ( PSP_PCI_EXTRAPCIHDR_REG, 0x34);
+ /// Capability chain update
+ Value32 = PspLibPciReadPspConfig (PSP_PCI_MIRRORCTRL1_REG);
+ Value32 &= ~D8F0x44_PmNxtPtrW_MASK;
+ Value32 |= 0xA4;
+ PspLibPciWritePspConfig (PSP_PCI_MIRRORCTRL1_REG, Value32);
+ }
+
+ return (TRUE);
+}
+
+/**
+ Return the PspMMIO MMIO location
+
+ @param[in] PspMmio Pointer to Psp MMIO address
+
+ @retval BOOLEAN 0: Error, 1 Success
+**/
+BOOLEAN
+GetPspBar1Addr (
+ IN OUT UINT32 *PspMmio
+ )
+{
+ if (CheckPspDevicePresent () == FALSE) {
+ return (FALSE);
+ }
+
+ *PspMmio = PspLibPciReadPspConfig (PSP_PCI_BAR1_REG);
+
+ if ((*PspMmio) == 0xffffffff) {
+ return (FALSE);
+ }
+
+ return (TRUE);
+}
+
+/**
+ Return the PspMMIO MMIO location
+
+ @param[in] PspMmio Pointer to Psp MMIO address
+
+ @retval BOOLEAN 0: Error, 1 Success
+**/
+BOOLEAN
+GetPspBar3Addr (
+ IN OUT UINT32 *PspMmio
+ )
+{
+ if (CheckPspDevicePresent () == FALSE) {
+ return (FALSE);
+ }
+
+ *PspMmio = PspLibPciReadPspConfig (PSP_PCI_BAR3_REG);
+
+ if ((*PspMmio) == 0xffffffff) {
+ return (FALSE);
+ }
+
+ return (TRUE);
+}
+
+/*---------------------------------------------------------------------------------------*/
+/**
+ * Returns the access width mask for the processor
+ *
+ *
+ * @param[in] AccessWidth Access width
+ * @retval Width in number of bytes
+ */
+
+
+UINT8
+PspLibAccessWidth (
+ IN ACCESS_WIDTH AccessWidth
+ )
+{
+ UINT8 Width;
+
+ switch (AccessWidth) {
+ case AccessWidth8:
+ case AccessS3SaveWidth8:
+ Width = 1;
+ break;
+ case AccessWidth16:
+ case AccessS3SaveWidth16:
+ Width = 2;
+ break;
+ case AccessWidth32:
+ case AccessS3SaveWidth32:
+ Width = 4;
+ break;
+ case AccessWidth64:
+ case AccessS3SaveWidth64:
+ Width = 8;
+ break;
+ default:
+ Width = 0;
+ }
+ return Width;
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Read GNB indirect registers
+ *
+ *
+ *
+ * @param[in] Address PCI address of indirect register
+ * @param[in] IndirectAddress Offset of indirect register
+ * @param[in] Width Width
+ * @param[out] Value Pointer to value
+ */
+VOID
+PspLibPciIndirectRead (
+ IN PCI_ADDR Address,
+ IN UINT32 IndirectAddress,
+ IN ACCESS_WIDTH Width,
+ OUT VOID *Value
+ )
+{
+ UINT32 IndexOffset;
+
+ IndexOffset = PspLibAccessWidth (Width);
+ LibAmdPciWrite (Width, Address, &IndirectAddress, NULL);
+ Address.AddressValue += IndexOffset;
+ LibAmdPciRead (Width, Address, Value, NULL);
+}
+
+/*----------------------------------------------------------------------------------------*/
+/**
+ * Write GNB indirect registers
+ *
+ *
+ *
+ * @param[in] Address PCI address of indirect register
+ * @param[in] IndirectAddress Offset of indirect register
+ * @param[in] Width Width
+ * @param[in] Value Pointer to value
+ */
+VOID
+PspLibPciIndirectWrite (
+ IN PCI_ADDR Address,
+ IN UINT32 IndirectAddress,
+ IN ACCESS_WIDTH Width,
+ IN VOID *Value
+ )
+{
+ UINT32 IndexOffset;
+
+ IndexOffset = PspLibAccessWidth (Width);
+ LibAmdPciWrite (Width, Address, &IndirectAddress, NULL);
+ Address.AddressValue += IndexOffset;
+ LibAmdPciWrite (Width, Address, Value, NULL);
+}
+
+
diff --git a/src/vendorcode/amd/pi/00660F01/Proc/Psp/PspBaseLib/PspBaseLib.h b/src/vendorcode/amd/pi/00660F01/Proc/Psp/PspBaseLib/PspBaseLib.h
new file mode 100644
index 0000000..c18e191
--- /dev/null
+++ b/src/vendorcode/amd/pi/00660F01/Proc/Psp/PspBaseLib/PspBaseLib.h
@@ -0,0 +1,187 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * PSP Base Library
+ *
+ * Contains interface to the PSP library
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: PSP
+ * @e \$Revision: 309090 $ @e \$Date: 2014-12-09 12:28:05 -0600 (Tue, 09 Dec 2014) $
+ *
+ */
+ /*****************************************************************************
+ *
+ * Copyright (c) 2008 - 2015, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ***************************************************************************/
+
+#ifndef _PSP_BASE_LIB_H_
+#define _PSP_BASE_LIB_H_
+
+#include "AMD.h"
+#include "amdlib.h"
+#include "PspDirectory.h"
+
+#define PSP_PCI_SEG 0x00 ///< PSP Seg address
+#define PSP_PCI_BUS 0x00 ///< PSP Bus address
+#define PSP_PCI_DEV 0x08 ///< PSP Device address
+#define PSP_PCI_FN 0x00 ///< PSP Fn address
+#define PSP_PCI_BDA ((PSP_PCI_DEV << 11) + (PSP_PCI_FN << 8))
+#define GET_PSP_PCI_ADDR (Offset) MAKE_SBDFO (PSP_PCI_SEG, PSP_PCI_BUS, PSP_PCI_DEV, PSP_PCI_FN, Offset)
+
+#define PSP_PCI_DEVID_REG 0x00 ///< DevId
+#define PSP_PCI_CMD_REG 0x04 ///< CmdReg
+#define PSP_PCI_BAR1_REG 0x18 ///< Pci Bar1
+#define PSP_PCI_BAR3_REG 0x20 ///< Pci Bar3
+#define PSP_PCI_MIRRORCTRL1_REG 0x44 ///< PSP Mirror Reg Ctrl 1
+#define PSP_PCI_EXTRAPCIHDR_REG 0x48 ///< Extra PCI Header Ctr
+#define PSP_PCI_HTMSICAP_REG 0x5C ///< HT MSI Capability
+
+#define D8F0x44_PmNxtPtrW_MASK 0xff
+
+#define PSP_MAILBOX_BASE 0x70 ///< Mailbox base offset on PCIe BAR
+#define PSP_MAILBOX_STATUS_OFFSET 0x4 ///< Staus Offset
+
+//======================================================================================
+//
+// Define Mailbox Status field
+//
+//======================================================================================
+//
+/// MBox Status MMIO space
+///
+typedef struct {
+ UINT32 MboxInitialized:1; ///< Target will set this to 1 to indicate it is initialized (for ex. PSP/TPM ready)
+ UINT32 Error:1; ///< Target in adddtion to Done bit will also set this bit to indicate success/error on last command
+ UINT32 Terminated:1; ///< Target will set this bit if it aborted the command due to abort request
+ UINT32 Halt:1; ///< Target will set this error if there is critical error that require reset etc
+ UINT32 Recovery:1; ///< Target will set this error if some PSP entry point by PSP directory has been corrupted.
+ UINT32 Reserved:27; ///< Reserved
+} MBOX_STATUS;
+
+//
+// Above defined as bitmap
+#define MBOX_STATUS_INITIALIZED 0x00000001ul ///< Mailbox Status: Initialized
+#define MBOX_STATUS_ERROR 0x00000002ul ///< Mailbox Status: Error
+#define MBOX_STATUS_ABORT 0x00000004ul ///< Mailbox Status: Abort
+#define MBOX_STATUS_HALT 0x00000008ul ///< Mailbox Status: Halt
+#define MBOX_STATUS_RECOVERY 0x00000010ul ///< Mailbox Status: Recovery required
+
+
+
+UINT32
+PspLibPciReadConfig (
+ IN UINT32 Register
+ );
+
+VOID
+PspLibPciWriteConfig (
+ IN UINT32 Register,
+ IN UINT32 Value
+ );
+
+UINT32
+PspLibPciReadPspConfig (
+ IN UINT16 Offset
+ );
+
+VOID
+PspLibPciWritePspConfig (
+ IN UINT16 Offset,
+ IN UINT32 Value
+ );
+
+BOOLEAN
+GetPspDirBase (
+ IN OUT UINT32 *Address
+);
+
+BOOLEAN
+PSPEntryInfo (
+ IN PSP_DIRECTORY_ENTRY_TYPE EntryType,
+ IN OUT UINT64 *EntryAddress,
+ IN UINT32 *EntrySize
+ );
+
+BOOLEAN
+CheckPspDevicePresent (
+ VOID
+ );
+
+BOOLEAN
+CheckPspPlatformSecureEnable (
+ VOID
+ );
+
+BOOLEAN
+CheckPspRecoveryFlag (
+ VOID
+ );
+
+BOOLEAN
+GetPspBar1Addr (
+ IN OUT UINT32 *PspMmio
+ );
+
+BOOLEAN
+GetPspBar3Addr (
+ IN OUT UINT32 *PspMmio
+ );
+
+
+BOOLEAN
+GetPspMboxStatus (
+ IN OUT MBOX_STATUS **MboxStatus
+ );
+
+
+BOOLEAN
+PspBarInitEarly (void);
+
+VOID
+PspLibPciIndirectRead (
+ IN PCI_ADDR Address,
+ IN UINT32 IndirectAddress,
+ IN ACCESS_WIDTH Width,
+ OUT VOID *Value
+ );
+
+VOID
+PspLibPciIndirectWrite (
+ IN PCI_ADDR Address,
+ IN UINT32 IndirectAddress,
+ IN ACCESS_WIDTH Width,
+ IN VOID *Value
+ );
+
+UINT8
+PspLibAccessWidth (
+ IN ACCESS_WIDTH AccessWidth
+ );
+#endif // _AMD_LIB_H_
diff --git a/src/vendorcode/amd/pi/00660F01/Proc/Psp/PspBaseLib/PspDirectory.h b/src/vendorcode/amd/pi/00660F01/Proc/Psp/PspBaseLib/PspDirectory.h
new file mode 100644
index 0000000..193cc65
--- /dev/null
+++ b/src/vendorcode/amd/pi/00660F01/Proc/Psp/PspBaseLib/PspDirectory.h
@@ -0,0 +1,94 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * PSP directory related functions Prototype definition
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: PSP
+ * @e \$Revision: 309090 $ @e \$Date: 2014-12-09 12:28:05 -0600 (Tue, 09 Dec 2014) $
+ */
+ /*****************************************************************************
+ *
+ * Copyright (c) 2008 - 2015, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ***************************************************************************/
+
+#ifndef _PSP_DIRECTORY_H_
+#define _PSP_DIRECTORY_H_
+
+
+#define FIRMWARE_TABLE_SIGNATURE 0x55AA55AAul
+/// Define the structure OEM signature table
+typedef struct _FIRMWARE_ENTRY_TABLE {
+ UINT32 Signature; ///< Signature should be 0x55AA55AAul
+ UINT32 ImcRomBase; ///< Base Address for Imc Firmware
+ UINT32 GecRomBase; ///< Base Address for Gmc Firmware
+ UINT32 XHCRomBase; ///< Base Address for XHCI Firmware
+ UINT32 PspDirBase; ///< Base Address for PSP directory
+} FIRMWARE_ENTRY_TABLE;
+
+/// Define structure for PSP directory
+typedef struct {
+ UINT32 PspCookie; ///< "$PSP"
+ UINT32 Checksum; ///< 32 bit CRC of header items below and the entire table
+ UINT32 TotalEntries; ///< Number of PSP Entries
+ UINT32 Reserved; ///< Unused
+} PSP_DIRECTORY_HEADER;
+
+
+/// define various enum type for PSP entry type
+enum _PSP_DIRECTORY_ENTRY_TYPE {
+ AMD_PUBLIC_KEY = 0, ///< PSP entry pointer to AMD public key
+ PSP_FW_BOOT_LOADER = 1, ///< PSP entry points to PSP boot loader in SPI space
+ PSP_FW_TRUSTED_OS = 2, ///< PSP entry points to PSP Firmware region in SPI space
+ PSP_FW_RECOVERY_BOOT_LOADER = 3, ///< PSP entry point to PSP recovery region.
+ PSP_NV_DATA = 4, ///< PSP entry points to PSP data region in SPI space
+ BIOS_PUBLIC_KEY = 5, ///< PSP entry points to BIOS public key stored in SPI space
+ BIOS_RTM_FIRMWARE = 6, ///< PSP entry points to BIOS RTM code (PEI volume) in SPI space
+ BIOS_RTM_SIGNATURE = 7, ///< PSP entry points to signed BIOS RTM hash stored in SPI space
+ SMU_OFFCHIP_FW = 8 ///< PSP entry points to SMU image
+};
+typedef UINT32 PSP_DIRECTORY_ENTRY_TYPE;
+
+/// Structure for PSP Entry
+typedef struct {
+ PSP_DIRECTORY_ENTRY_TYPE Type; ///< Type of PSP entry; 32 bit long
+ UINT32 Size; ///< Size of PSP Entry in bytes
+ UINT64 Location; ///< Location of PSP Entry (byte offset from start of SPI-ROM)
+} PSP_DIRECTORY_ENTRY;
+
+/// Structure for PSP directory
+typedef struct {
+ PSP_DIRECTORY_HEADER Header; ///< PSP directory header
+ PSP_DIRECTORY_ENTRY PspEntry[1]; ///< Array of PSP entries each pointing to a binary in SPI flash
+ ///< The actual size of this array comes from the
+ ///< header (PSP_DIRECTORY.Header.TotalEntries)
+} PSP_DIRECTORY;
+
+#endif //_PSP_DIRECTORY_H_
diff --git a/src/vendorcode/amd/pi/00660F01/binaryPI/AGESA.c b/src/vendorcode/amd/pi/00660F01/binaryPI/AGESA.c
new file mode 100644
index 0000000..4352901
--- /dev/null
+++ b/src/vendorcode/amd/pi/00660F01/binaryPI/AGESA.c
@@ -0,0 +1,543 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Agesa structures and definitions
+ *
+ * Contains AMD AGESA core interface
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: Include
+ * @e \$Revision: 85818 $ @e \$Date: 2013-01-11 17:04:21 -0600 (Fri, 11 Jan 2013) $
+ */
+/*****************************************************************************
+ *
+ * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ***************************************************************************/
+// TODO This list needs to be pruned of anything that is not API
+#include "AGESA.h"
+#include "agesawrapper.h"
+#include "FieldAccessors.h"
+#include "AcpiLib.h"
+#include "FchCommonCfg.h"
+#include "Fch.h"
+#include "FchDef.h"
+#include "amdlib.h"
+#include "cbfs.h"
+#include <console/console.h>
+#include <console/loglevel.h>
+
+// TODO Add a kconfig option to name the AGESA ROM file in CBFS
+#define CONFIG_CBFS_AGESA_NAME "AGESA"
+
+// TODO These need to be replaced with calls to CreateStruct()
+AGESA_STATUS
+HeapAllocateBuffer (
+ IN OUT VOID *AllocateHeapParams,
+ IN OUT VOID *StdHeader
+ );
+
+AGESA_STATUS
+HeapDeallocateBuffer (
+ IN UINT32 BufferHandle,
+ IN VOID *StdHeader
+ );
+
+CONST UINT32 ImageSignature = IMAGE_SIGNATURE;
+CONST UINT32 ModuleSignature = MODULE_SIGNATURE;
+CONST CHAR8 ModuleIdentifier[] = AGESA_ID;
+
+/**********************************************************************
+ * Interface call: AmdCreateStruct
+ **********************************************************************/
+AGESA_STATUS
+AmdCreateStruct (
+ IN OUT AMD_INTERFACE_PARAMS *InterfaceParams
+ )
+{
+ MODULE_ENTRY Dispatcher = NULL;
+ const AMD_MODULE_HEADER* module = agesawrapper_locate_module(ModuleIdentifier);
+ InterfaceParams->StdHeader.Func = AMD_CREATE_STRUCT;
+ if (!module) return AGESA_UNSUPPORTED;
+ Dispatcher = module->ModuleDispatcher;
+ return Dispatcher(InterfaceParams);
+}
+
+/**********************************************************************
+ * Interface call: AmdReleaseStruct
+ **********************************************************************/
+AGESA_STATUS
+AmdReleaseStruct (
+ IN OUT AMD_INTERFACE_PARAMS *InterfaceParams
+ )
+{
+ MODULE_ENTRY Dispatcher = NULL;
+ const AMD_MODULE_HEADER* module = agesawrapper_locate_module(ModuleIdentifier);
+ InterfaceParams->StdHeader.Func = AMD_RELEASE_STRUCT;
+ if (!module) return AGESA_UNSUPPORTED;
+ Dispatcher = module->ModuleDispatcher;
+ return Dispatcher(InterfaceParams);
+}
+
+/**********************************************************************
+ * Interface call: AmdInitReset
+ **********************************************************************/
+AGESA_STATUS
+AmdInitReset (
+ IN OUT AMD_RESET_PARAMS *ResetParams
+ )
+{
+ MODULE_ENTRY Dispatcher = NULL;
+ const AMD_MODULE_HEADER* module = agesawrapper_locate_module(ModuleIdentifier);
+ ResetParams->StdHeader.Func = AMD_INIT_RESET;
+ if (!module) return AGESA_UNSUPPORTED;
+ Dispatcher = module->ModuleDispatcher;
+ return Dispatcher(ResetParams);
+}
+
+/**********************************************************************
+ * Interface call: AmdInitEarly
+ **********************************************************************/
+AGESA_STATUS
+AmdInitEarly (
+ IN OUT AMD_EARLY_PARAMS *EarlyParams
+ )
+{
+ MODULE_ENTRY Dispatcher = NULL;
+ const AMD_MODULE_HEADER* module = agesawrapper_locate_module(ModuleIdentifier);
+ EarlyParams->StdHeader.Func = AMD_INIT_EARLY;
+ if (!module) return AGESA_UNSUPPORTED;
+ Dispatcher = module->ModuleDispatcher;
+ return Dispatcher(EarlyParams);
+}
+
+/**********************************************************************
+ * Interface call: AmdInitPost
+ **********************************************************************/
+AGESA_STATUS
+AmdInitPost (
+ IN OUT AMD_POST_PARAMS *PostParams ///< Amd Cpu init param
+ )
+{
+ MODULE_ENTRY Dispatcher = NULL;
+ const AMD_MODULE_HEADER* module = agesawrapper_locate_module(ModuleIdentifier);
+ PostParams->StdHeader.Func = AMD_INIT_POST;
+ if (!module) return AGESA_UNSUPPORTED;
+ Dispatcher = module->ModuleDispatcher;
+ return Dispatcher(PostParams);
+}
+
+/**********************************************************************
+ * Interface call: AmdInitEnv
+ **********************************************************************/
+AGESA_STATUS
+AmdInitEnv (
+ IN OUT AMD_ENV_PARAMS *EnvParams
+ )
+{
+ MODULE_ENTRY Dispatcher = NULL;
+ const AMD_MODULE_HEADER* module = agesawrapper_locate_module(ModuleIdentifier);
+ EnvParams->StdHeader.Func = AMD_INIT_ENV;
+ if (!module) return AGESA_UNSUPPORTED;
+ Dispatcher = module->ModuleDispatcher;
+ return Dispatcher(EnvParams);
+}
+
+/**********************************************************************
+ * Interface call: AmdInitMid
+ **********************************************************************/
+AGESA_STATUS
+AmdInitMid (
+ IN OUT AMD_MID_PARAMS *MidParams
+ )
+{
+ MODULE_ENTRY Dispatcher = NULL;
+ const AMD_MODULE_HEADER* module = agesawrapper_locate_module(ModuleIdentifier);
+ MidParams->StdHeader.Func = AMD_INIT_MID;
+ if (!module) return AGESA_UNSUPPORTED;
+ Dispatcher = module->ModuleDispatcher;
+ return Dispatcher(MidParams);
+}
+
+/**********************************************************************
+ * Interface call: AmdInitLate
+ **********************************************************************/
+AGESA_STATUS
+AmdInitLate (
+ IN OUT AMD_LATE_PARAMS *LateParams
+ )
+{
+ MODULE_ENTRY Dispatcher = NULL;
+ const AMD_MODULE_HEADER* module = agesawrapper_locate_module(ModuleIdentifier);
+ LateParams->StdHeader.Func = AMD_INIT_LATE;
+ if (!module) return AGESA_UNSUPPORTED;
+ Dispatcher = module->ModuleDispatcher;
+ return Dispatcher(LateParams);
+}
+
+/**********************************************************************
+ * Interface call: AmdInitRecovery
+ **********************************************************************/
+AGESA_STATUS
+AmdInitRecovery (
+ IN OUT AMD_RECOVERY_PARAMS *RecoveryParams
+ )
+{
+ MODULE_ENTRY Dispatcher = NULL;
+ const AMD_MODULE_HEADER* module = agesawrapper_locate_module(ModuleIdentifier);
+ RecoveryParams->StdHeader.Func = AMD_INIT_RECOVERY;
+ if (!module) return AGESA_UNSUPPORTED;
+ Dispatcher = module->ModuleDispatcher;
+ return Dispatcher(RecoveryParams);
+}
+
+/**********************************************************************
+ * Interface call: AmdInitResume
+ **********************************************************************/
+AGESA_STATUS
+AmdInitResume (
+ IN AMD_RESUME_PARAMS *ResumeParams
+ )
+{
+ MODULE_ENTRY Dispatcher = NULL;
+ const AMD_MODULE_HEADER* module = agesawrapper_locate_module(ModuleIdentifier);
+ ResumeParams->StdHeader.Func = AMD_INIT_RESUME;
+ if (!module) return AGESA_UNSUPPORTED;
+ Dispatcher = module->ModuleDispatcher;
+ return Dispatcher(ResumeParams);
+}
+
+/**********************************************************************
+ * Interface call: AmdS3LateRestore
+ **********************************************************************/
+AGESA_STATUS
+AmdS3LateRestore (
+ IN OUT AMD_S3LATE_PARAMS *S3LateParams
+ )
+{
+ MODULE_ENTRY Dispatcher = NULL;
+ const AMD_MODULE_HEADER* module = agesawrapper_locate_module(ModuleIdentifier);
+ S3LateParams->StdHeader.Func = AMD_S3LATE_RESTORE;
+ if (!module) return AGESA_UNSUPPORTED;
+ Dispatcher = module->ModuleDispatcher;
+ return Dispatcher(S3LateParams);
+}
+
+/**********************************************************************
+ * Interface call: AmdInitRtb
+ **********************************************************************/
+AGESA_STATUS
+AmdInitRtb (
+ IN OUT AMD_RTB_PARAMS *AmdInitRtbParams
+ )
+{
+ MODULE_ENTRY Dispatcher = NULL;
+ const AMD_MODULE_HEADER* module = agesawrapper_locate_module(ModuleIdentifier);
+ AmdInitRtbParams->StdHeader.Func = AMD_INIT_RTB;
+ if (!module) return AGESA_UNSUPPORTED;
+ Dispatcher = module->ModuleDispatcher;
+ return Dispatcher(AmdInitRtbParams);
+}
+
+/**********************************************************************
+ * Interface call: AmdLateRunApTask
+ **********************************************************************/
+AGESA_STATUS
+AmdLateRunApTask (
+ IN AP_EXE_PARAMS *AmdApExeParams
+)
+{
+ MODULE_ENTRY Dispatcher = NULL;
+ const AMD_MODULE_HEADER* module = agesawrapper_locate_module(ModuleIdentifier);
+ AmdApExeParams->StdHeader.Func = AMD_LATE_RUN_AP_TASK;
+ if (!module) return AGESA_UNSUPPORTED;
+ Dispatcher = module->ModuleDispatcher;
+ return Dispatcher(AmdApExeParams);
+}
+
+/**********************************************************************
+ * Interface service call: AmdGetApicId
+ **********************************************************************/
+AGESA_STATUS
+AmdGetApicId (
+ IN OUT AMD_APIC_PARAMS *AmdParamApic
+)
+{
+ MODULE_ENTRY Dispatcher = NULL;
+ const AMD_MODULE_HEADER* module = agesawrapper_locate_module(ModuleIdentifier);
+ AmdParamApic->StdHeader.Func = AMD_GET_APIC_ID;
+ if (!module) return AGESA_UNSUPPORTED;
+ Dispatcher = module->ModuleDispatcher;
+ return Dispatcher(AmdParamApic);
+}
+
+/**********************************************************************
+ * Interface service call: AmdGetPciAddress
+ **********************************************************************/
+AGESA_STATUS
+AmdGetPciAddress (
+ IN OUT AMD_GET_PCI_PARAMS *AmdParamGetPci
+)
+{
+ MODULE_ENTRY Dispatcher = NULL;
+ const AMD_MODULE_HEADER* module = agesawrapper_locate_module(ModuleIdentifier);
+ AmdParamGetPci->StdHeader.Func = AMD_GET_PCI_ADDRESS;
+ if (!module) return AGESA_UNSUPPORTED;
+ Dispatcher = module->ModuleDispatcher;
+ return Dispatcher(AmdParamGetPci);
+}
+
+/**********************************************************************
+ * Interface service call: AmdIdentifyCore
+ **********************************************************************/
+AGESA_STATUS
+AmdIdentifyCore (
+ IN OUT AMD_IDENTIFY_PARAMS *AmdParamIdentify
+)
+{
+ MODULE_ENTRY Dispatcher = NULL;
+ const AMD_MODULE_HEADER* module = agesawrapper_locate_module(ModuleIdentifier);
+ AmdParamIdentify->StdHeader.Func = AMD_IDENTIFY_CORE;
+ if (!module) return AGESA_UNSUPPORTED;
+ Dispatcher = module->ModuleDispatcher;
+ return Dispatcher(AmdParamIdentify);
+}
+
+/**********************************************************************
+ * Interface service call: AmdReadEventLog
+ **********************************************************************/
+AGESA_STATUS
+AmdReadEventLog (
+ IN EVENT_PARAMS *Event
+)
+{
+ MODULE_ENTRY Dispatcher = NULL;
+ const AMD_MODULE_HEADER* module = agesawrapper_locate_module(ModuleIdentifier);
+ Event->StdHeader.Func = AMD_READ_EVENT_LOG;
+ if (!module) return AGESA_UNSUPPORTED;
+ Dispatcher = module->ModuleDispatcher;
+ return Dispatcher(Event);
+}
+
+/**********************************************************************
+ * Interface service call: AmdIdentifyDimm
+ **********************************************************************/
+AGESA_STATUS
+AmdIdentifyDimm (
+ IN OUT AMD_IDENTIFY_DIMM *AmdDimmIdentify
+)
+{
+ MODULE_ENTRY Dispatcher = NULL;
+ const AMD_MODULE_HEADER* module = agesawrapper_locate_module(ModuleIdentifier);
+ AmdDimmIdentify->StdHeader.Func = AMD_IDENTIFY_DIMMS;
+ if (!module) return AGESA_UNSUPPORTED;
+ Dispatcher = module->ModuleDispatcher;
+ return Dispatcher(AmdDimmIdentify);
+}
+
+AGESA_STATUS
+AmdIdsRunApTaskLate (
+ IN AP_EXE_PARAMS *AmdApExeParams
+ )
+{
+ MODULE_ENTRY Dispatcher = NULL;
+ const AMD_MODULE_HEADER* module = agesawrapper_locate_module(ModuleIdentifier);
+ AmdApExeParams->StdHeader.Func = -1;
+ return AGESA_UNSUPPORTED;
+ if (!module) return AGESA_UNSUPPORTED;
+ Dispatcher = module->ModuleDispatcher;
+ return Dispatcher(AmdApExeParams);
+}
+
+/**********************************************************************
+ * Interface service call: AmdGet2DDataEye
+ **********************************************************************/
+AGESA_STATUS
+AmdGet2DDataEye (
+ IN OUT AMD_GET_DATAEYE *AmdGetDataEye
+ )
+{
+ MODULE_ENTRY Dispatcher = NULL;
+ const AMD_MODULE_HEADER* module = agesawrapper_locate_module(ModuleIdentifier);
+ AmdGetDataEye->StdHeader.Func = AMD_GET_2D_DATA_EYE;
+ if (!module) return AGESA_UNSUPPORTED;
+ Dispatcher = module->ModuleDispatcher;
+ return Dispatcher(AmdGetDataEye);
+}
+
+/**********************************************************************
+ * FCH Functions
+ **********************************************************************/
+
+VOID FchInitS3LateRestore (IN FCH_DATA_BLOCK *FchDataPtr);
+VOID FchInitS3EarlyRestore (IN FCH_DATA_BLOCK *FchDataPtr);
+
+VOID
+FchInitS3EarlyRestore (
+ IN FCH_DATA_BLOCK *FchDataPtr
+ )
+{
+ MODULE_ENTRY Dispatcher = NULL;
+ const AMD_MODULE_HEADER* module = agesawrapper_locate_module(ModuleIdentifier);
+ FchDataPtr->StdHeader->Func = FCH_INIT_S3_EARLY_RESTORE;
+ if (!module) return;
+ Dispatcher = module->ModuleDispatcher;
+ Dispatcher(FchDataPtr);
+}
+
+VOID
+FchInitS3LateRestore (
+ IN FCH_DATA_BLOCK *FchDataPtr
+ )
+{
+ MODULE_ENTRY Dispatcher = NULL;
+ const AMD_MODULE_HEADER* module = agesawrapper_locate_module(ModuleIdentifier);
+ FchDataPtr->StdHeader->Func = FCH_INIT_S3_LATE_RESTORE;
+ if (!module) return;
+ Dispatcher = module->ModuleDispatcher;
+ Dispatcher(FchDataPtr);
+}
+
+// TODO This has to be removed
+AGESA_STATUS
+HeapAllocateBuffer (
+ IN OUT VOID *AllocateHeapParams,
+ IN OUT VOID *StdHeader
+ )
+{
+ MODULE_ENTRY Dispatcher = NULL;
+ const AMD_MODULE_HEADER* module = agesawrapper_locate_module(ModuleIdentifier);
+
+ AMD_INTERFACE_PARAMS InterfaceParams = {};
+
+ if (!module) return AGESA_UNSUPPORTED;
+ Dispatcher = module->ModuleDispatcher;
+
+ InterfaceParams.StdHeader = *(AMD_CONFIG_PARAMS*)StdHeader;
+ InterfaceParams.StdHeader.Func = AMD_HEAP_ALLOCATE_BUFFER;
+
+ InterfaceParams.AllocationMethod = PreMemHeap;
+ InterfaceParams.NewStructPtr = AllocateHeapParams;
+
+ return Dispatcher(&InterfaceParams);
+}
+
+// TODO This has to be removed
+AGESA_STATUS
+HeapDeallocateBuffer (
+ IN UINT32 BufferHandle,
+ IN VOID *StdHeader
+ )
+{
+ MODULE_ENTRY Dispatcher = NULL;
+ const AMD_MODULE_HEADER* module = agesawrapper_locate_module(ModuleIdentifier);
+
+ AMD_INTERFACE_PARAMS InterfaceParams = {};
+
+ if (!module) return AGESA_UNSUPPORTED;
+ Dispatcher = module->ModuleDispatcher;
+
+ InterfaceParams.StdHeader = *(AMD_CONFIG_PARAMS*)StdHeader;
+ InterfaceParams.StdHeader.Func = AMD_HEAP_DEALLOCATE_BUFFER;
+
+ InterfaceParams.NewStructPtr = &BufferHandle;
+
+ return Dispatcher(&InterfaceParams);
+}
+
+/**********************************************************************
+ * Interface call: AmdSetValue
+ **********************************************************************/
+AGESA_STATUS
+AmdSetValue (
+ IN CONST AGESA_FIELD_NAME name,
+ IN OUT VOID* value,
+ IN UINT32 size
+ )
+{
+ AGESA_STATUS status = AGESA_UNSUPPORTED;
+
+ MODULE_ENTRY Dispatcher = NULL;
+ const AMD_MODULE_HEADER* module = agesawrapper_locate_module(ModuleIdentifier);
+
+ AMD_ACCESSOR_PARAMS AccessorParams = {};
+
+ if (!module) return status;
+ Dispatcher = module->ModuleDispatcher;
+
+ AccessorParams.StdHeader.AltImageBasePtr = 0;
+ AccessorParams.StdHeader.CalloutPtr = NULL;
+ AccessorParams.StdHeader.Func = AMD_SET_VALUE;
+ AccessorParams.StdHeader.ImageBasePtr = 0;
+
+ AccessorParams.AllocationMethod = ByHost;
+ AccessorParams.FieldName = name;
+ AccessorParams.FieldValue = value;
+ AccessorParams.FieldSize = size;
+
+ status = Dispatcher(&AccessorParams);
+ return status;
+}
+
+/**********************************************************************
+ * Interface call: AmdGetValue
+ **********************************************************************/
+AGESA_STATUS
+AmdGetValue (
+ IN CONST AGESA_FIELD_NAME name,
+ IN OUT VOID** value,
+ IN UINT32 size
+ )
+{
+ AGESA_STATUS status = AGESA_UNSUPPORTED;
+
+ MODULE_ENTRY Dispatcher = NULL;
+ const AMD_MODULE_HEADER* module = agesawrapper_locate_module(ModuleIdentifier);
+
+ AMD_ACCESSOR_PARAMS AccessorParams = {};
+
+ if (!module) return status;
+ Dispatcher = module->ModuleDispatcher;
+
+ AccessorParams.StdHeader.AltImageBasePtr = 0;
+ AccessorParams.StdHeader.CalloutPtr = NULL;
+ AccessorParams.StdHeader.Func = AMD_GET_VALUE;
+ AccessorParams.StdHeader.ImageBasePtr = 0;
+
+ AccessorParams.AllocationMethod = ByHost;
+ AccessorParams.FieldName = name;
+ AccessorParams.FieldValue = *value;
+ AccessorParams.FieldSize = size;
+
+ status = Dispatcher(&AccessorParams);
+
+ *value = AccessorParams.FieldValue;
+ size = AccessorParams.FieldSize;
+
+ return status;
+}
diff --git a/src/vendorcode/amd/pi/00660F01/binaryPI/FieldAccessors.h b/src/vendorcode/amd/pi/00660F01/binaryPI/FieldAccessors.h
new file mode 100644
index 0000000..2d860c5
--- /dev/null
+++ b/src/vendorcode/amd/pi/00660F01/binaryPI/FieldAccessors.h
@@ -0,0 +1,118 @@
+/*****************************************************************************
+ *
+ * Copyright (c) 2013 - 2014, Sage Electronic Engineering, LLC
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ***************************************************************************/
+#ifndef _FIELDACCESSORS_H_
+#define _FIELDACCESSORS_H_
+
+/// AGESA value name
+typedef enum {
+ AMD_GLOBAL_USER_OPTIONS = 0x00020000,
+ AMD_GLOBAL_NUM_SOCKETS = 0x00020001,
+ AMD_GLOBAL_NUM_MODULES = 0x00020002,
+} AGESA_FIELD_NAME;
+
+typedef AGESA_STATUS (*SETTER_ENTRY) (
+ IN OUT VOID* value,
+ IN UINT32 size
+ );
+
+typedef AGESA_STATUS (*GETTER_ENTRY) (
+ IN OUT VOID** value,
+ IN UINT32 size
+ );
+
+/// Accessor Interface.
+typedef struct {
+ IN AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header
+ IN AGESA_FIELD_NAME FieldName; ///< The service to init
+ IN ALLOCATION_METHOD AllocationMethod; ///< For pointers, how to allocate space for copied data
+ IN OUT VOID *Struct; ///< The struct for the service.
+ IN OUT UINT32 FieldSize; ///< The size of the data value.
+ IN OUT VOID *FieldValue; ///< The value retrieved or set into the target structure.
+} AMD_ACCESSOR_PARAMS;
+
+/**********************************************************************
+ * Interface call: AmdSetValue
+ **********************************************************************/
+AGESA_STATUS
+AmdSetValueDispatch (
+ IN OUT AMD_ACCESSOR_PARAMS *AccessorParams
+ );
+
+AGESA_STATUS
+AmdSetValue (
+ IN CONST AGESA_FIELD_NAME name,
+ IN OUT VOID* value,
+ IN UINT32 size
+ );
+
+/**********************************************************************
+ * Interface call: AmdGetValue
+ **********************************************************************/
+AGESA_STATUS
+AmdGetValueDispatch (
+ IN OUT AMD_ACCESSOR_PARAMS *AccessorParams
+ );
+
+AGESA_STATUS
+AmdGetValue (
+ IN CONST AGESA_FIELD_NAME name,
+ IN OUT VOID** value,
+ IN UINT32 size
+ );
+
+/**
+ * Dispatch Table.
+ *
+ * The push high dispatcher uses this table to find what entries are currently in the build image.
+ */
+typedef struct {
+ UINT32 FunctionId;
+ SETTER_ENTRY SetValueEntryPoint;
+ GETTER_ENTRY GetValueEntryPoint;
+} ACCESSOR_DISPATCH_TABLE;
+
+AGESA_STATUS
+GetUserOptions(
+ IN OUT VOID** value,
+ IN UINT32 size
+ );
+
+AGESA_STATUS
+GetNumSockets(
+ IN OUT VOID** value,
+ IN UINT32 size
+ );
+
+AGESA_STATUS
+GetNumModules(
+ IN OUT VOID** value,
+ IN UINT32 size
+ );
+
+#endif /* _FIELDACCESSORS_H_ */
diff --git a/src/vendorcode/amd/pi/00660F01/binaryPI/OptionsIds.h b/src/vendorcode/amd/pi/00660F01/binaryPI/OptionsIds.h
new file mode 100644
index 0000000..bd39fce
--- /dev/null
+++ b/src/vendorcode/amd/pi/00660F01/binaryPI/OptionsIds.h
@@ -0,0 +1,124 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * IDS Option File
+ *
+ * This file is used to switch on/off IDS features.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: Core
+ * @e \$Revision: 192403 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
+ */
+ /*****************************************************************************
+ *
+ * Copyright (c) 2008 - 2015, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ***************************************************************************/
+#include "Ids.h"
+
+#ifndef _OPTION_IDS_H_
+#define _OPTION_IDS_H_
+
+/**
+ *
+ * This file generates the defaults tables for the Integrated Debug Support
+ * Module. The documented build options are imported from a user controlled
+ * file for processing. The build options for the Integrated Debug Support
+ * Module are listed below:
+ *
+ * IDSOPT_IDS_ENABLED
+ * IDSOPT_ERROR_TRAP_ENABLED
+ * IDSOPT_CONTROL_ENABLED
+ *
+ * Warning: When you enable the IDSOPT_CONTROL_NV_TO_CMOS feature.
+ * please make the cmos region defined by IDS_OPT_CMOS_REGION_START &
+ * IDS_OPT_CMOS_REGION_END can be touched between IDS HOOK point
+ * IDS_CPU_Early_Override and IDS_BEFORE_AP_EARLY_HALT of BSP
+ *
+ * IDSOPT_CONTROL_NV_TO_CMOS
+ * IDS_OPT_CMOS_INDEX_PORT
+ * IDS_OPT_CMOS_DATA_PORT
+ * IDS_OPT_CMOS_REGION_START
+ * IDS_OPT_CMOS_REGION_END
+ *
+ * IDSOPT_TRACING_ENABLED
+ * IDSOPT_TRACING_CONSOLE_HDTOUT
+ * IDSOPT_TRACING_CONSOLE_SERIALPORT
+ * IDSOPT_SERIAL_PORT (default 0x3F8)
+ * IDSOPT_TRACING_CONSOLE_REDIRECT_IO
+ * IDSOPT_DEBUG_PRINT_IO_PORT (default 0x80)
+ * IDSOPT_TRACING_CONSOLE_RAM
+ * IDSOPT_DPRAM_BASE
+ * IDSOPT_DPRAM_SIZE
+ * IDSOPT_DPRAM_STOP_LOGGING_WHEN_BUFFER_FULL (default FALSE)
+ * IDSOPT_CUSTOMIZE_TRACING_SERVICE
+ * IDSOPT_CUSTOMIZE_TRACING_SERVICE_INIT
+ * IDSOPT_CUSTOMIZE_TRACING_SERVICE_EXIT
+ *
+ * IDSOPT_TRACE_BLD_CFG
+ * IDSOPT_PERF_ANALYSIS
+ * IDSOPT_ASSERT_ENABLED
+ * IDS_DEBUG_PORT
+ * IDSOPT_CAR_CORRUPTION_CHECK_ENABLED
+ * IDSOPT_DEBUG_CODE_ENABLED
+ * IDSOPT_IDT_EXCEPTION_TRAP
+ * IDSOPT_C_OPTIMIZATION_DISABLED
+ *
+ **/
+
+
+
+//#include "Ids.h"
+
+#define IDSOPT_ERROR_TRAP_ENABLED FALSE
+
+#ifdef DEBUG
+#define IDSOPT_IDS_ENABLED TRUE
+//#define IDSOPT_CONTROL_ENABLED FALSE
+#define IDSOPT_TRACING_ENABLED TRUE
+#define IDSOPT_TRACING_CONSOLE_SERIALPORT TRUE
+#ifdef IDS_DEBUG_PRINT_MASK
+#undef IDS_DEBUG_PRINT_MASK
+#endif
+#define IDS_DEBUG_PRINT_MASK (GNB_TRACE_ALL | GFX_MISC | CPU_TRACE_ALL | MEM_STATUS | TOPO_TRACE_ALL | FCH_TRACE_ALL | MAIN_FLOW | IDS_TRACE_DEFAULT | TEST_POINT)
+#define IDSOPT_SERIAL_PORT 0x3F8
+#define IDSOPT_HEAP_CHECKING TRUE
+#define IDSOPT_TRACE_BLD_CFG TRUE
+#define IDSOPT_CAR_CORRUPTION_CHECK_ENABLED FALSE
+#define IDSOPT_DEBUG_CODE_ENABLED TRUE
+#define IDSOPT_C_OPTIMIZATION_DISABLED TRUE
+#else
+#define IDSOPT_IDS_ENABLED FALSE
+//#define IDSOPT_ERROR_TRAP_ENABLED FALSE
+//#define IDSOPT_CONTROL_ENABLED FALSE
+#define IDSOPT_TRACING_ENABLED FALSE
+#define IDSOPT_TRACING_CONSOLE_SERIALPORT TRUE
+#define IDS_DEBUG_PRINT_MASK (0)
+#endif
+
+#endif
diff --git a/src/vendorcode/amd/pi/00660F01/binaryPI/gcc-intrin.h b/src/vendorcode/amd/pi/00660F01/binaryPI/gcc-intrin.h
new file mode 100644
index 0000000..c6b5c63
--- /dev/null
+++ b/src/vendorcode/amd/pi/00660F01/binaryPI/gcc-intrin.h
@@ -0,0 +1,744 @@
+/*
+ Compatibility <intrin_x86.h> header for GCC -- GCC equivalents of intrinsic
+ Microsoft Visual C++ functions. Originally developed for the ReactOS
+ (<http://www.reactos.org/>) and TinyKrnl (<http://www.tinykrnl.org/>)
+ projects.
+
+ Copyright (c) 2006 KJK::Hyperion <hackbunny(a)reactos.com>
+ 2014 Sage Electronic Engineering, LLC
+
+ Permission is hereby granted, free of charge, to any person obtaining a
+ copy of this software and associated documentation files (the "Software"),
+ to deal in the Software without restriction, including without limitation
+ the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ and/or sell copies of the Software, and to permit persons to whom the
+ Software is furnished to do so, subject to the following conditions:
+
+ The above copyright notice and this permission notice shall be included in
+ all copies or substantial portions of the Software.
+
+ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ DEALINGS IN THE SOFTWARE.
+*/
+
+#if defined (__GNUC__)
+
+/* I/O intrin functions. */
+static
+__inline__ __attribute__((always_inline))
+unsigned char __inbyte(unsigned short Port)
+{
+ unsigned char value;
+
+ __asm__ __volatile__ (
+ "in %%dx, %%al"
+ : "=a" (value)
+ : "d" (Port)
+ );
+
+ return value;
+}
+
+static
+__inline__ __attribute__((always_inline))
+unsigned short __inword(unsigned short Port)
+{
+ unsigned short value;
+
+ __asm__ __volatile__ (
+ "in %%dx, %%ax"
+ : "=a" (value)
+ : "d" (Port)
+ );
+
+ return value;
+}
+
+static
+__inline__ __attribute__((always_inline))
+unsigned long __indword(unsigned short Port)
+{
+ unsigned long value;
+
+ __asm__ __volatile__ (
+ "in %%dx, %%eax"
+ : "=a" (value)
+ : "d" (Port)
+ );
+ return value;
+
+}
+
+static
+__inline__ __attribute__((always_inline))
+void __outbyte(unsigned short Port,unsigned char Data)
+{
+ __asm__ __volatile__ (
+ "out %%al, %%dx"
+ :
+ : "a" (Data), "d" (Port)
+ );
+}
+
+static
+__inline__ __attribute__((always_inline))
+void __outword(unsigned short Port,unsigned short Data)
+{
+ __asm__ __volatile__ (
+ "out %%ax, %%dx"
+ :
+ : "a" (Data), "d" (Port)
+ );
+}
+
+static
+__inline__ __attribute__((always_inline))
+void __outdword(unsigned short Port,unsigned long Data)
+{
+ __asm__ __volatile__ (
+ "out %%eax, %%dx"
+ :
+ : "a" (Data), "d" (Port)
+ );
+}
+
+static
+__inline__ __attribute__((always_inline))
+void __inbytestring(unsigned short Port,unsigned char *Buffer,unsigned long Count)
+{
+ __asm__ __volatile__ (
+ "cld ; rep ; insb "
+ : "=D" (Buffer), "=c" (Count)
+ : "d"(Port), "0"(Buffer), "1" (Count)
+ );
+}
+
+static
+__inline__ __attribute__((always_inline))
+void __inwordstring(unsigned short Port,unsigned short *Buffer,unsigned long Count)
+{
+ __asm__ __volatile__ (
+ "cld ; rep ; insw "
+ : "=D" (Buffer), "=c" (Count)
+ : "d"(Port), "0"(Buffer), "1" (Count)
+ );
+}
+
+static
+__inline__ __attribute__((always_inline))
+void __indwordstring(unsigned short Port,unsigned long *Buffer,unsigned long Count)
+{
+ __asm__ __volatile__ (
+ "cld ; rep ; insl "
+ : "=D" (Buffer), "=c" (Count)
+ : "d"(Port), "0"(Buffer), "1" (Count)
+ );
+}
+
+static
+__inline__ __attribute__((always_inline))
+void __outbytestring(unsigned short Port,unsigned char *Buffer,unsigned long Count)
+{
+ __asm__ __volatile__ (
+ "cld ; rep ; outsb "
+ : "=S" (Buffer), "=c" (Count)
+ : "d"(Port), "0"(Buffer), "1" (Count)
+ );
+}
+
+static
+__inline__ __attribute__((always_inline))
+void __outwordstring(unsigned short Port,unsigned short *Buffer,unsigned long Count)
+{
+ __asm__ __volatile__ (
+ "cld ; rep ; outsw "
+ : "=S" (Buffer), "=c" (Count)
+ : "d"(Port), "0"(Buffer), "1" (Count)
+ );
+}
+
+static
+__inline__ __attribute__((always_inline))
+void __outdwordstring(unsigned short Port,unsigned long *Buffer,unsigned long Count)
+{
+ __asm__ __volatile__ (
+ "cld ; rep ; outsl "
+ : "=S" (Buffer), "=c" (Count)
+ : "d"(Port), "0"(Buffer), "1" (Count)
+ );
+}
+
+static
+__inline__ __attribute__((always_inline))
+unsigned long __readdr0(void)
+{
+ unsigned long value;
+ __asm__ __volatile__ (
+ "mov %%dr0, %[value]"
+ : [value] "=a" (value)
+ );
+ return value;
+}
+
+static
+__inline__ __attribute__((always_inline))
+unsigned long __readdr1(void)
+{
+ unsigned long value;
+ __asm__ __volatile__ (
+ "mov %%dr1, %[value]"
+ : [value] "=a" (value)
+ );
+ return value;
+}
+
+static
+__inline__ __attribute__((always_inline))
+unsigned long __readdr2(void)
+{
+ unsigned long value;
+ __asm__ __volatile__ (
+ "mov %%dr2, %[value]"
+ : [value] "=a" (value)
+ );
+ return value;
+}
+
+static
+__inline__ __attribute__((always_inline))
+unsigned long __readdr3(void)
+{
+ unsigned long value;
+ __asm__ __volatile__ (
+ "mov %%dr3, %[value]"
+ : [value] "=a" (value)
+ );
+ return value;
+}
+
+static
+__inline__ __attribute__((always_inline))
+unsigned long __readdr7(void)
+{
+ unsigned long value;
+ __asm__ __volatile__ (
+ "mov %%dr7, %[value]"
+ : [value] "=a" (value)
+ );
+ return value;
+}
+
+static
+__inline__ __attribute__((always_inline))
+unsigned long __readdr(unsigned long reg)
+{
+ switch (reg){
+ case 0:
+ return __readdr0 ();
+ break;
+
+ case 1:
+ return __readdr1 ();
+ break;
+
+ case 2:
+ return __readdr2 ();
+ break;
+
+ case 3:
+ return __readdr3 ();
+ break;
+
+ case 7:
+ return __readdr7 ();
+ break;
+
+ default:
+ return -1;
+ }
+}
+
+static
+__inline__ __attribute__((always_inline))
+void __writedr0(unsigned long Data)
+{
+ __asm__ __volatile__ (
+ "mov %%eax, %%dr0"
+ :
+ : "a" (Data)
+ );
+}
+
+static
+__inline__ __attribute__((always_inline))
+void __writedr1(unsigned long Data)
+{
+ __asm__ __volatile__ (
+ "mov %%eax, %%dr1"
+ :
+ : "a" (Data)
+ );
+}
+
+static
+__inline__ __attribute__((always_inline))
+void __writedr2(unsigned long Data)
+{
+ __asm__ __volatile__ (
+ "mov %%eax, %%dr2"
+ :
+ : "a" (Data)
+ );
+}
+
+static
+__inline__ __attribute__((always_inline))
+void __writedr3(unsigned long Data)
+{
+ __asm__ __volatile__ (
+ "mov %%eax, %%dr3"
+ :
+ : "a" (Data)
+ );
+}
+
+static
+__inline__ __attribute__((always_inline))
+void __writedr7(unsigned long Data)
+{
+ __asm__ __volatile__ (
+ "mov %%eax, %%dr7"
+ :
+ : "a" (Data)
+ );
+}
+
+static
+__inline__ __attribute__((always_inline))
+void __writedr(unsigned long reg, unsigned long Data)
+{
+ switch (reg){
+ case 0:
+ __writedr0 (Data);
+ break;
+
+ case 1:
+ __writedr1 (Data);
+ break;
+
+ case 2:
+ __writedr2 (Data);
+ break;
+
+ case 3:
+ __writedr3 (Data);
+ break;
+
+ case 7:
+ __writedr7 (Data);
+ break;
+
+ default:
+ ;
+ }
+}
+
+static
+__inline__ __attribute__((always_inline))
+unsigned long __readcr0(void)
+{
+ unsigned long value;
+ __asm__ __volatile__ (
+ "mov %%cr0, %[value]"
+ : [value] "=a" (value));
+ return value;
+}
+
+static
+__inline__ __attribute__((always_inline))
+unsigned long __readcr2(void)
+{
+ unsigned long value;
+ __asm__ __volatile__ (
+ "mov %%cr2, %[value]"
+ : [value] "=a" (value));
+ return value;
+}
+
+static
+__inline__ __attribute__((always_inline))
+unsigned long __readcr3(void)
+{
+ unsigned long value;
+ __asm__ __volatile__ (
+ "mov %%cr3, %[value]"
+ : [value] "=a" (value));
+ return value;
+}
+
+static
+__inline__ __attribute__((always_inline))
+unsigned long __readcr4(void)
+{
+ unsigned long value;
+ __asm__ __volatile__ (
+ "mov %%cr4, %[value]"
+ : [value] "=a" (value));
+ return value;
+}
+
+static
+__inline__ __attribute__((always_inline))
+unsigned long __readcr8(void)
+{
+ unsigned long value;
+ __asm__ __volatile__ (
+ "mov %%cr8, %[value]"
+ : [value] "=a" (value));
+ return value;
+}
+
+static
+__inline__ __attribute__((always_inline))
+unsigned long __readcr(unsigned long reg)
+{
+ switch (reg){
+ case 0:
+ return __readcr0 ();
+ break;
+
+ case 2:
+ return __readcr2 ();
+ break;
+
+ case 3:
+ return __readcr3 ();
+ break;
+
+ case 4:
+ return __readcr4 ();
+ break;
+
+ case 8:
+ return __readcr8 ();
+ break;
+
+ default:
+ return -1;
+ }
+}
+
+static
+__inline__ __attribute__((always_inline))
+void __writecr0(unsigned long Data)
+{
+ __asm__ __volatile__ (
+ "mov %%eax, %%cr0"
+ :
+ : "a" (Data)
+ );
+}
+
+static
+__inline__ __attribute__((always_inline))
+void __writecr2(unsigned long Data)
+{
+ __asm__ __volatile__ (
+ "mov %%eax, %%cr2"
+ :
+ : "a" (Data)
+ );
+}
+
+static
+__inline__ __attribute__((always_inline))
+void __writecr3(unsigned long Data)
+{
+ __asm__ __volatile__ (
+ "mov %%eax, %%cr3"
+ :
+ : "a" (Data)
+ );
+}
+
+static
+__inline__ __attribute__((always_inline))
+void __writecr4(unsigned long Data)
+{
+ __asm__ __volatile__ (
+ "mov %%eax, %%cr4"
+ :
+ : "a" (Data)
+ );
+}
+
+static
+__inline__ __attribute__((always_inline))
+void __writecr8(unsigned long Data)
+{
+ __asm__ __volatile__ (
+ "mov %%eax, %%cr8"
+ :
+ : "a" (Data)
+ );
+}
+
+static
+__inline__ __attribute__((always_inline))
+void __writecr(unsigned long reg, unsigned long Data)
+{
+ switch (reg){
+ case 0:
+ __writecr0 (Data);
+ break;
+
+ case 2:
+ __writecr2 (Data);
+ break;
+
+ case 3:
+ __writecr3 (Data);
+ break;
+
+ case 4:
+ __writecr4 (Data);
+ break;
+
+ case 8:
+ __writecr8 (Data);
+ break;
+
+ default:
+ ;
+ }
+}
+
+static
+__inline__ __attribute__((always_inline))
+UINT64 __readmsr(UINT32 msr)
+{
+ UINT64 retval;
+ __asm__ __volatile__(
+ "rdmsr\n\t"
+ : "=A" (retval)
+ : "c" (msr)
+ );
+ return retval;
+}
+
+static
+__inline__ __attribute__((always_inline))
+void __writemsr (UINT32 msr, UINT64 Value)
+{
+ __asm__ __volatile__ (
+ "wrmsr\n\t"
+ :
+ : "c" (msr), "A" (Value)
+ );
+}
+
+static
+__inline__ __attribute__((always_inline))
+UINT64 __rdtsc(void)
+{
+ UINT64 retval;
+ __asm__ __volatile__ (
+ "rdtsc"
+ : "=A" (retval));
+ return retval;
+}
+
+static
+__inline__ __attribute__((always_inline))
+void __cpuid(int CPUInfo[], const int InfoType)
+{
+ __asm__ __volatile__(
+ "cpuid"
+ :"=a" (CPUInfo[0]), "=b" (CPUInfo[1]), "=c" (CPUInfo[2]), "=d" (CPUInfo[3])
+ : "a" (InfoType)
+ );
+}
+
+static
+__inline__ __attribute__((always_inline))
+void _disable(void)
+{
+ __asm__ __volatile__ ("cli");
+}
+
+static
+__inline__ __attribute__((always_inline))
+void _enable(void)
+{
+ __asm__ __volatile__ ("sti");
+}
+
+static
+__inline__ __attribute__((always_inline))
+void __halt(void)
+{
+ __asm__ __volatile__ ("hlt");
+}
+
+static
+__inline__ __attribute__((always_inline))
+void __debugbreak(void)
+{
+ __asm__ __volatile__ ("int3");
+}
+
+static
+__inline__ __attribute__((always_inline))
+void __wbinvd(void)
+{
+ __asm__ __volatile__ ("wbinvd");
+}
+
+static
+__inline__ __attribute__((always_inline))
+void __lidt(void *Source)
+{
+ __asm__ __volatile__("lidt %0" : : "m"(*(short*)Source));
+}
+
+static
+__inline__ __attribute__((always_inline))
+void __writefsbyte(const unsigned long Offset, const unsigned char Data)
+{
+ __asm__("movb %b[Data], %%fs:%a[Offset]" : : [Offset] "ir" (Offset), [Data] "iq" (Data));
+}
+
+static
+__inline__ __attribute__((always_inline))
+void __writefsword(const unsigned long Offset, const unsigned short Data)
+{
+ __asm__("movw %w[Data], %%fs:%a[Offset]" : : [Offset] "ir" (Offset), [Data] "iq" (Data));
+}
+
+static
+__inline__ __attribute__((always_inline))
+void __writefsdword(const unsigned long Offset, const unsigned long Data)
+{
+ __asm__("movl %k[Data], %%fs:%a[Offset]" : : [Offset] "ir" (Offset), [Data] "iq" (Data));
+}
+
+static
+__inline__ __attribute__((always_inline))
+unsigned char __readfsbyte(const unsigned long Offset)
+{
+ unsigned char value;
+ __asm__("movb %%fs:%a[Offset], %b[value]" : [value] "=q" (value) : [Offset] "irm" (Offset));
+ return value;
+}
+
+static
+__inline__ __attribute__((always_inline))
+unsigned short __readfsword(const unsigned long Offset)
+{
+ unsigned short value;
+ __asm__("movw %%fs:%a[Offset], %w[value]" : [value] "=q" (value) : [Offset] "irm" (Offset));
+ return value;
+}
+
+static
+__inline__ __attribute__((always_inline))
+unsigned long __readfsdword(const unsigned long Offset)
+{
+ unsigned long value;
+ __asm__("movl %%fs:%a[Offset], %k[value]" : [value] "=q" (value) : [Offset] "irm" (Offset));
+ return value;
+}
+
+#ifdef __SSE3__
+typedef long long __v2di __attribute__ ((__vector_size__ (16)));
+typedef long long __m128i __attribute__ ((__vector_size__ (16), __may_alias__));
+
+static
+__inline__ __attribute__((always_inline))
+void _mm_stream_si128_fs2 (void *__A, __m128i __B)
+{
+ __asm__(".byte 0x64"); // fs prefix
+ __builtin_ia32_movntdq ((__v2di *)__A, (__v2di)__B);
+}
+
+static
+__inline__ __attribute__((always_inline))
+void _mm_stream_si128_fs (void *__A, void *__B)
+{
+ __m128i data;
+ data = (__m128i) __builtin_ia32_lddqu ((char const *)__B);
+ _mm_stream_si128_fs2 (__A, data);
+}
+
+static
+__inline__ __attribute__((always_inline))
+void _mm_clflush_fs (void *__A)
+{
+ __asm__(".byte 0x64"); // fs prefix
+ __builtin_ia32_clflush (__A);
+}
+
+static
+__inline__ __attribute__((always_inline))
+void _mm_mfence (void)
+{
+ __builtin_ia32_mfence ();
+}
+
+static
+__inline__ __attribute__((always_inline))
+void _mm_sfence (void)
+{
+ __builtin_ia32_sfence ();
+}
+#endif
+
+static
+__inline__ __attribute__((always_inline))
+void __stosb(unsigned char *dest, unsigned char data, size_t count)
+{
+ __asm__ __volatile__ (
+ "cld ; rep ; stosb "
+ : "=D" (dest), "=c" (count)
+ : "a"(data), "0"(dest), "1" (count)
+ );
+}
+
+static
+__inline__ __attribute__((always_inline))
+void __movsb(unsigned char *dest, unsigned char *data, size_t count)
+{
+ __asm__ __volatile__ (
+ "cld ; rep ; movsb "
+ : "=D" (dest), "=S"(data), "=c" (count)
+ : "S"(data), "0"(dest), "1" (count)
+ );
+}
+
+static
+__inline__ __attribute__((always_inline))
+void debug_point ( unsigned short Port, unsigned long Data )
+{
+ __outdword (Port, Data);
+ __asm__ __volatile__ (".word 0xfeeb");
+
+}
+
+static
+__inline__ __attribute__((always_inline))
+void delay_point ( unsigned short Port, unsigned long Data, unsigned long delayTime )
+{
+ UINTN Index;
+ Index = 0;
+ __outdword (Port, Data);
+ while (Index < delayTime * 600000) {
+ __outdword (0xE0, 0);
+ Index ++;
+ }
+}
+#endif // defined (__GNUC__)
diff --git a/src/vendorcode/amd/pi/00660F01/binaryPI/gcccar.inc b/src/vendorcode/amd/pi/00660F01/binaryPI/gcccar.inc
new file mode 100644
index 0000000..d6782a3
--- /dev/null
+++ b/src/vendorcode/amd/pi/00660F01/binaryPI/gcccar.inc
@@ -0,0 +1,1335 @@
+/*
+ * Copyright (c) 2012, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/******************************************************************************
+* AMD Generic Encapsulated Software Architecture
+*
+* $Workfile:: GccCar.inc $Revision:: 32932 $
+*
+* Description: GccCar.inc - AGESA cache-as-RAM setup Include File for GCC complier
+*
+******************************************************************************/
+
+.altmacro
+
+BSP_STACK_BASE_ADDR = 0x30000 /* Base address for primary cores stack */
+BSP_STACK_SIZE = 0x10000 /* 64KB for BSP core */
+BSP_STACK_SIZE_64K = 0x10000 /*64KB for BSP core */
+BSP_STACK_SIZE_32K = 0x8000 /*32KB for BSP core*/
+
+CORE0_STACK_BASE_ADDR = 0x80000 /* Base address for primary cores stack */
+CORE0_STACK_SIZE = 0x4000 /* 16KB for primary cores */
+CORE1_STACK_BASE_ADDR = 0x40000 /* Base address for AP cores */
+CORE1_STACK_SIZE = 0x1000 /* 4KB for each AP cores */
+
+APIC_BASE_ADDRESS = 0x0000001B
+ APIC_BSC = 8 /* Boot Strap Core */
+
+APIC_MSG_REG = 0x380 # Location of BSC message
+ APIC_MSG = 0x00DE00AD # Message data
+APIC_CMD_LO_REG = 0x300 # APIC command low
+APIC_CMD_HI_REG = 0x310 # APIC command high
+ CMD_REG_TO_READ_DATA = 0x00000338 # APIC command for remote read of APIC_MSG_REG
+ REMOTE_READ_STS = 0x00030000 # Remote read status mask
+ REMOTE_DELIVERY_PEND = 0x00010000 # Remote read is pending
+ REMOTE_DELIVERY_DONE = 0x00020000 # Remote read is complete
+ DELIVERY_STS_BIT = 12 #Delivery status valid bit
+APIC_ID_REG = 0x0020 # Local APIC ID offset
+ APIC20_APICID = 24
+APIC_REMOTE_READ_REG = 0x00C0 # Remote read offset
+
+# Flags can only run from bits 31 to 24. Bits 23:0 are in use.
+AMD_CU_NEED_TO_WAIT = 31
+AMD_CU_SEND_INVD_MSG = 30
+AMD_CU_RESTORE_ES = 29
+
+AMD_MTRR_VARIABLE_BASE0 = 0x0200
+AMD_MTRR_VARIABLE_BASE6 = 0x020C
+AMD_MTRR_VARIABLE_BASE7 = 0x020E
+ VMTRR_VALID = 11
+ MTRR_TYPE_WB = 0x06
+ MTRR_TYPE_WP = 0x05
+ MTRR_TYPE_WT = 0x04
+ MTRR_TYPE_UC = 0x00
+AMD_MTRR_VARIABLE_MASK7 = 0x020F
+AMD_MTRR_FIX64k_00000 = 0x0250
+AMD_MTRR_FIX16k_80000 = 0x0258
+AMD_MTRR_FIX16k_A0000 = 0x0259
+AMD_MTRR_FIX4k_C0000 = 0x0268
+AMD_MTRR_FIX4k_C8000 = 0x0269
+AMD_MTRR_FIX4k_D0000 = 0x026A
+AMD_MTRR_FIX4k_D8000 = 0x026B
+AMD_MTRR_FIX4k_E0000 = 0x026C
+AMD_MTRR_FIX4k_E8000 = 0x026D
+AMD_MTRR_FIX4k_F0000 = 0x026E
+AMD_MTRR_FIX4k_F8000 = 0x026F
+
+/* Reproduced from AGESA.h */
+AMD_AP_MTRR_FIX64k_00000 = 0x00000250
+AMD_AP_MTRR_FIX16k_80000 = 0x00000258
+AMD_AP_MTRR_FIX16k_A0000 = 0x00000259
+AMD_AP_MTRR_FIX4k_C0000 = 0x00000268
+AMD_AP_MTRR_FIX4k_C8000 = 0x00000269
+AMD_AP_MTRR_FIX4k_D0000 = 0x0000026A
+AMD_AP_MTRR_FIX4k_D8000 = 0x0000026B
+AMD_AP_MTRR_FIX4k_E0000 = 0x0000026C
+AMD_AP_MTRR_FIX4k_E8000 = 0x0000026D
+AMD_AP_MTRR_FIX4k_F0000 = 0x0000026E
+AMD_AP_MTRR_FIX4k_F8000 = 0x0000026F
+CPU_LIST_TERMINAL = 0xFFFFFFFF
+
+AMD_MTRR_DEFTYPE = 0x02FF
+ WB_DRAM_TYPE = 0x1E /* MemType - memory type */
+ MTRR_DEF_TYPE_EN = 11 /* MtrrDefTypeEn - variable and fixed MTRRs default enabled */
+ MTRR_DEF_TYPE_FIX_EN = 10 /* MtrrDefTypeEn - fixed MTRRs default enabled */
+
+HWCR = 0x0C0010015 /* Hardware Configuration */
+ INVD_WBINVD = 0x04 /* INVD to WBINVD conversion */
+
+IORR_BASE = 0x0C0010016 /* IO Range Regusters Base/Mask, 2 pairs */
+ /* uses 16h - 19h */
+TOP_MEM = 0x0C001001A /* Top of Memory */
+TOP_MEM2 = 0x0C001001D /* Top of Memory2 */
+
+LS_CFG3 = 0x0C001101C /* Load-Store Configuration 3 */
+ DIS_SS_F15CZ = 7 /* Disable Streaming Store functionality*/
+ DC_DIS_SPEC_TLB_RLD_F15CZ = 20 /* Disable speculative TLB reloads*/
+ DC_DIS_HW_PF_F15CZ = 23 /* Hardware prefetches bit*/
+
+
+LS_CFG = 0x0C0011020 /* Load-Store Configuration */
+ DIS_SS = 28 /* Family 10h,12h,15h:Disable Streng Store functionality */
+ DIS_STREAM_ST = 28 /* Family 14h:DisStreamSt - Disable Streaming Store functionality */
+
+IC_CFG = 0x0C0011021 /* Instruction Cache Config Register */
+ IC_DIS_SPEC_TLB_RLD = 9 /* Disable speculative TLB reloads */
+ DIS_IND = 14 /* Family 10-14h:Disable Indirect Branch Predictor */
+ DIS_I_CACHE = 14 /* Family 15h:DisICache - Disable Indirect Branch Predictor */
+
+DC_CFG = 0x0C0011022 /* Data Cache Configuration */
+ DC_DIS_SPEC_TLB_RLD = 4 /* Disable speculative TLB reloads */
+ DIS_CLR_WBTOL2_SMC_HIT = 8 /* self modifying code check buffer bit */
+ DIS_HW_PF = 13 /* Hardware prefetches bit */
+
+CU_CFG = 0x0C0011023 /* Family 15h: Combined Unit Configuration */
+ L2_WAY_LOCK_EN = 23 /* L2WayLock - L2 way lock enable */
+ L2_FIRST_LOCKED_WAY = 19 /* L2FirstLockedWay - first L2 way lockedh */
+ L2_FIRST_LOCKED_WAY_OR_MASK = 0x000780000
+
+DE_CFG = 0x0C0011029 /* Decode Configuration */
+ CL_FLUSH_SERIALIZE = 23 /* Family 12h,15h: CL Flush Serialization */
+
+BU_CFG2 = 0x0C001102A /* Family 10h: Bus Unit Configuration 2 */
+CU_CFG2 = 0x0C001102A /* Family 15h: Combined Unit Configuration 2 */
+ F10_CL_LINES_TO_NB_DIS = 15 /* ClLinesToNbDis - allows WP code to be cached in L2 */
+ IC_DIS_SPEC_TLB_WR = 35 /* IcDisSpecTlbWr - ITLB speculative writes */
+
+CU_CFG3 = 0x0C001102B /* Combined Unit Configuration 3 */
+ COMBINE_CR0_CD = 49 /* Combine CR0.CD for both cores of a compute unit */
+
+CR0_PE = 0 # Protection Enable
+CR0_NW = 29 # Not Write-through
+CR0_CD = 30 # Cache Disable
+CR0_PG = 31 # Paging Enable
+
+/* CPUID Functions */
+
+CPUID_MODEL = 1
+AMD_CPUID_FMF = 0x80000001 /* Family Model Features information */
+AMD_CPUID_L2Cache = 0X80000006 /* L2/L3 cache info */
+AMD_CPUID_APIC = 0x80000008 /* Long Mode and APIC info., core count */
+ APIC_ID_CORE_ID_SIZE = 12 /* ApicIdCoreIdSize bit position */
+
+NB_CFG = 0x0C001001F /* Northbridge Configuration Register */
+ INIT_APIC_ID_CPU_ID_LO = 54 /* InitApicIdCpuIdLo - is core# in high or low half of APIC ID? */
+ ENABLE_CF8_EXT_CFG = 46 /* EnableCf8ExtCfg - enable CF8 extended configuration cycles */
+
+MTRR_SYS_CFG = 0x0C0010010 /* System Configuration Register */
+ CHX_TO_DIRTY_DIS = 16 /* ChxToDirtyDis Change to dirty disable */
+ SYS_UC_LOCK_EN = 17 /* SysUcLockEn System lock command enable */
+ MTRR_FIX_DRAM_EN = 18 /* MtrrFixDramEn MTRR fixed RdDram and WrDram attributes enable */
+ MTRR_FIX_DRAM_MOD_EN = 19 /* MtrrFixDramModEn MTRR fixed RdDram and WrDram modification enable */
+ MTRR_VAR_DRAM_EN = 20 /* MtrrVarDramEn MTRR variable DRAM enable */
+ MTRR_TOM2_EN = 21 /* MtrrTom2En MTRR top of memory 2 enable */
+
+PERF_CONTROL3 = 0x0C0010003 /* Performance event control three */
+ PERF_CONTROL3_RESERVE_L = 0x00200000 /* Preserve the reserved bits */
+ PERF_CONTROL3_RESERVE_H = 0x0FCF0 /* Preserve the reserved bits */
+ CONFIG_EVENT_L = 0x0F0E2 /* All cores with level detection */
+ CONFIG_EVENT_H = 4 /* Increment count by number of event */
+ /* occured in clock cycle */
+ EVENT_ENABLE = 22 /* Enable the event */
+PERF_COUNTER3 = 0x0C0010007 /* Performance event counter three */
+
+FUNC_3 = 3
+MCA_NB_CFG = 0x44 /* MCA NB Configuration */
+CPU_ERR_DIS = 6 /* CPU error response disable */
+PRODUCT_INFO_REG1 = 0x1FC /* Product Information Register 1 */
+
+# Local use flags, in upper most byte if ESI
+FLAG_UNKNOWN_FAMILY = 24 # Signals that the family# of the installed processor is not recognized
+FLAG_STACK_REENTRY = 25 # Signals that the environment has made a re-entry (2nd) call to set up the stack
+FLAG_IS_PRIMARY = 26 # Signals that this core is the primary within the comoute unit
+FLAG_CORE_NOT_IDENTIFIED = 27 # Signals that the cores/compute units of the installed processor is not recognized
+FLAG_FORCE_32K_STACK = 28 # Signals that to force 32KB stack size for BSP core
+CR0_MASK = ((1 << CR0_CD) | (1 << CR0_NW))
+MSR_MASK = ((1 << MTRR_DEF_TYPE_EN)+(1 << MTRR_DEF_TYPE_FIX_EN))
+
+/****************************************************************************
+ *
+ * CPU MACROS - PUBLIC
+ *
+ ****************************************************************************/
+.macro _WRMSR
+ .byte 0x0f, 0x30
+.endm
+
+.macro _RDMSR
+ .byte 0x0F, 0x32
+.endm
+
+.macro AMD_CPUID arg0
+ .ifb \arg0
+ mov $0x1, %eax
+ .byte 0x0F, 0x0A2 /* Execute instruction */
+ bswap %eax
+ xchg %ah, %al /* Ext model in al now */
+ rol $0x08, %eax /* Ext model in ah, model in al */
+ and $0x0FFCF, ax /* Keep 23:16, 7:6, 3:0 */
+ .else
+ mov \arg0, %eax
+ .byte 0x0F, 0x0A2
+ .endif
+.endm
+
+.macro MAKE_EXT_PCI_ADDR Seg, Bus, Dev, Func, Offset
+ mov $(1 << 31 | (Seg) << 28 | (((Offset) & (0x0F00)) >> 8) << 24 | (Bus) << 16 | (Dev) << 11 | (Func) << 8) | ((Offset) & (0xFC)), %eax
+.endm
+/****************************************************************************
+*
+* AMD_ENABLE_STACK_FAMILY_HOOK Macro - Stackless
+*
+* Set any family specific controls needed to enable the use of
+* cache as general storage before main memory is available.
+*
+* Inputs:
+* none
+* Outputs:
+* none
+ ****************************************************************************/
+.macro AMD_ENABLE_STACK_FAMILY_HOOK
+
+// AMD_ENABLE_STACK_FAMILY_HOOK_F10
+// AMD_ENABLE_STACK_FAMILY_HOOK_F12
+// AMD_ENABLE_STACK_FAMILY_HOOK_F14
+ AMD_ENABLE_STACK_FAMILY_HOOK_F15
+.endm
+
+/****************************************************************************
+*
+* AMD_DISABLE_STACK_FAMILY_HOOK Macro - Stackless
+*
+* Return any family specific controls to their 'standard'
+* settings for using cache with main memory.
+*
+* Inputs:
+* none
+* Outputs:
+* none
+ ****************************************************************************/
+.macro AMD_DISABLE_STACK_FAMILY_HOOK
+
+ //AMD_DISABLE_STACK_FAMILY_HOOK_F10
+ //AMD_DISABLE_STACK_FAMILY_HOOK_F12
+ //AMD_DISABLE_STACK_FAMILY_HOOK_F14
+ AMD_DISABLE_STACK_FAMILY_HOOK_F15
+
+.endm
+
+/****************************************************************************
+*
+* GET_NODE_ID_CORE_ID Macro - Stackless
+*
+* Read family specific values to determine the node and core
+* numbers for the core executing this code.
+*
+* Inputs:
+* none
+* Outputs:
+* SI[7:0] = Core# (0..N, relative to node)
+* SI[15:8]= Node# (0..N)
+* SI[23:16]= reserved
+* SI[24]= flag: 1=Family Unrecognized
+* SI[25]= flag: 1=Interface re-entry call
+* SI[26]= flag: 1=Core is primary of compute unit
+* SI[31:27]= reserved, =0
+****************************************************************************/
+.macro GET_NODE_ID_CORE_ID
+ LOCAL node_core_exit
+
+ mov $-1, %si
+ //GET_NODE_ID_CORE_ID_F10
+ //GET_NODE_ID_CORE_ID_F12
+ //GET_NODE_ID_CORE_ID_F14
+ GET_NODE_ID_CORE_ID_F15
+ /*
+ * Check for unrecognized Family
+ */
+ cmp $-1, %si # Has family (node/core) already been discovered?
+ jnz node_core_exit # Br if yes
+
+ mov $((1 << FLAG_UNKNOWN_FAMILY)+(1 << FLAG_IS_PRIMARY)), %esi # No, Set error code, Only let BSP continue
+
+ mov $APIC_BASE_ADDRESS, %ecx # MSR:0000_001B
+ _RDMSR
+ bt $APIC_BSC, %eax # Is this the BSC?
+ jc node_core_exit # Br if yes
+ hlt # Kill APs
+node_core_exit:
+
+.endm
+
+
+/*****************************************************************************
+** Family 15h MACROS
+*****************************************************************************/
+/*****************************************************************************
+*
+* AMD_ENABLE_STACK_FAMILY_HOOK_F15 Macro - Stackless
+*
+* Set any family specific controls needed to enable the use of
+* cache as general storage before main memory is available.
+*
+* Inputs:
+* ESI - node#, core#, flags from GET_NODE_ID_CORE_ID
+* Outputs:
+* none
+*
+* Family 15h requirements (BKDG #42301 section 2.3.3):
+* * Paging must be disabled.
+* * MSRC001_0015[INVD_WBINVD]=0
+* * MSRC001_1020[DisSS]=1
+* * MSRC001_1021[DIS_SPEC_TLB_RLD]=1
+* * MSRC001_1022[DIS_SPEC_TLB_RLD]=1
+* * MSRC001_1022[DisHwPf]=1
+* * No INVD or WBINVD, no exceptions, page faults or interrupts
+*****************************************************************************/
+.macro AMD_ENABLE_STACK_FAMILY_HOOK_F15
+ LOCAL fam15_enable_stack_hook_exit
+
+ AMD_CPUID $CPUID_MODEL
+ mov %eax, %ebx # Save revision info to EBX
+ shr $20, %eax # AL = cpu extended family
+ cmp $0x06, %al # Is this family 15h?
+ jnz fam15_enable_stack_hook_exit # Br if no
+
+ bt $FLAG_STACK_REENTRY , %esi # Check if stack has already been set
+ jc fam15_skipClearingBit4
+ mov $HWCR, %ecx # MSR C001_0015
+ _RDMSR
+ btr $INVD_WBINVD, %eax # disable INVD -> WBINVD conversion
+ _WRMSR
+
+fam15_skipClearingBit4:
+ #cz
+ mov $LS_CFG3, %ecx # MSR:C001_101C
+ _RDMSR
+ bts $DIS_SS_F15CZ, %eax # Turn on Streaming store functionality disabled bit
+ _WRMSR
+
+ mov $IC_CFG, %ecx # MSR:C001_1021
+ _RDMSR
+ bts $IC_DIS_SPEC_TLB_RLD, %eax # Turn on Disable speculative IC-TLB reloads bit
+ _WRMSR
+
+ mov $LS_CFG3, %ecx # MSR:C001_101C
+ _RDMSR
+ bts $DC_DIS_SPEC_TLB_RLD_F15CZ, %eax # Turn on Disable speculative DC-TLB reloads bit
+ bts $DC_DIS_HW_PF_F15CZ, %eax
+ _WRMSR
+ # Do CZ enable stack special
+
+ mov $CU_CFG, %ecx #MSR:C001_1023
+ _RDMSR
+ bt $L2_WAY_LOCK_EN, %eax
+ #.if (!carry?)
+ jc dofamily15w
+ bts $L2_WAY_LOCK_EN, %eax
+ or $L2_FIRST_LOCKED_WAY_OR_MASK, %eax
+ _WRMSR
+ #.endif
+
+dofamily15w: # Do Standard Family 15 work
+
+ mov $CU_CFG3, %ecx # MSR:C001_102B
+ _RDMSR
+ btr $(COMBINE_CR0_CD - 32), %edx # Clear CombineCr0Cd bit
+ _WRMSR
+
+fam15_enable_stack_hook_exit:
+.endm
+
+/*****************************************************************************
+*
+* AMD_DISABLE_STACK_FAMILY_HOOK_F15 Macro - Stackless
+*
+* Return any family specific controls to their 'standard'
+* settings for using cache with main memory.
+*
+* Inputs:
+* ESI - [31:24] flags; [15,8]= Node#; [7,0]= core#
+* Outputs:
+* none
+*
+* Family 15h requirements:
+* * INVD or WBINVD
+* * MSRC001_0015[INVD_WBINVD]=1
+* * MSRC001_1020[DisSS]=0
+* * MSRC001_1021[DIS_SPEC_TLB_RLD]=0
+* * MSRC001_1022[DIS_SPEC_TLB_RLD]=0
+* * MSRC001_1022[DIS_HW_PF]=0
+*****************************************************************************/
+.macro AMD_DISABLE_STACK_FAMILY_HOOK_F15
+ LOCAL fam15_disable_stack_hook_exit
+ LOCAL fam15_disable_stack_remote_read_exit
+
+ AMD_CPUID $CPUID_MODEL
+ mov %eax, %ebx # Save revision info to EBX
+ shr $20, %eax # AL = cpu extended family
+ cmp $0x06, %al # Is this family 15h?
+ jnz fam15_disable_stack_hook_exit # Br if no
+
+ mov %ebx, %edi # Save revision info to EDI
+ AMD_CPUID $AMD_CPUID_APIC
+ mov %cl, %al # AL = number of cores - 1
+ shr $APIC_ID_CORE_ID_SIZE, %cx # CL = ApicIdCoreIdSize
+ mov $1, %bx
+ shl %cl, %bl # BL = theoretical number of cores on socket
+ dec %bx # BL = core number on socket mask
+ mov %bl, %ah # AH = core number on socket mask
+ mov %edi, %ebx # Restore revision info to EBX
+ mov %ax, %di # DI[15:8] = core number mask, DI[7:0] = number of cores - 1
+
+ and $0x0F00FF, %ebx
+ mov %ebx, %eax
+ shr $8, %eax
+ or %ax, %bx # Save Extended Model, Model and Stepping to BX
+ # [11:8] = Extended Model, [7:4] = Model, [3:0] = Stepping (bx=0000000000010100, ok)
+
+ mov $APIC_BASE_ADDRESS, %ecx
+ _RDMSR # dx=0 ax=fee00800
+ mov %bx, %dx # Save Extended Model, Model and Stepping to DX
+ shl $16, %edx #EDX[31:16] = Extended Model, Model and Stepping
+ mov %eax ,%ebx # EBX = LAPIC base
+ xor %ecx ,%ecx # Zero out CU flags
+ bts $AMD_CU_NEED_TO_WAIT, %ecx # Default to waiting
+ bts $AMD_CU_SEND_INVD_MSG, %ecx # Default to signaling
+ mov %cr0, %eax
+ bt $CR0_PE, %ax # Are we in protected mode?
+ # .if (!carry?)
+ jc 1f
+ bts $AMD_CU_RESTORE_ES, %ecx # Indicate ES restore is required
+ mov %es, %cx # Save ES segment register to CX
+ xor %ax, %ax
+ mov %ax, %es # Set ES to big real mode selector for 4GB access
+ # .endif
+
+1:
+ and $0x0F000, %bx # EBX = LAPIC base, offset 0
+ or $APIC_ID_REG, %bl #
+ mov %es:(%ebx), %eax # EAX[31:24] = APIC ID
+ shr $APIC20_APICID, %eax # AL = APIC ID
+ mov %al, %ah # AH = APIC ID
+ mov %di, %dx # DH = core mask
+ and %dh, %ah # AH = core number # ax=111 dx=01000F03
+
+//1: jmp 1b
+ # .if (zero?)
+ jnz 1f
+ # Core 0 of a socket
+ btr $AMD_CU_SEND_INVD_MSG, %ecx # No need to signal after INVD
+ #.if (dl != 0)
+ cmp $0, %dl
+ jz 2f
+ # This socket has multiple cores
+ and $0xf000, %bx # EBX = LAPIC base, offset 0
+ or $APIC_MSG_REG, %bx
+ mov $APIC_MSG, %edi
+ mov %edi, %es:(%ebx) # Signal for non core 0s to complete CAR breakdown
+ jmp 1f
+ #.else
+2: btr $AMD_CU_NEED_TO_WAIT, %ecx # No need to wait on a single core CPU
+ #.endif
+ # .endif
+1:
+
+ bt $AMD_CU_NEED_TO_WAIT, %ecx #cx = c0000000
+ #.if (carry?)
+ jnc 1f
+ #.if (ah == dl)
+ cmp %dl, %ah
+ jnz 2f
+ # This is the highest numbered core on this socket -- wait on core 0
+ not %dh # Flip the mask to determine local core 0's APID ID
+ and %dh, %al # AL = target APIC ID # ax=310
+ jmp 3f
+2: #.else
+ # All other cores (including core 0) wait on the next highest core.
+ # In this way, cores will halt in a cascading fashion down to 0.
+ inc %al
+ #.endif
+3:
+ shl $APIC20_APICID, %eax
+ and $0x0F000, %bx
+ or $APIC_CMD_HI_REG, %bx
+ mov %eax, %es:(%ebx) # Set target APIC ID
+
+ # Use bits 23:16 as a timeout for unresponsive cores
+ ror $8, %ecx
+ mov $0xFF, %ch
+ stc
+
+ #.while (carry?)
+5: jnc 4f
+ and $0xF000, %bx #EBX = LAPIC base, offset 0
+ or $APIC_CMD_LO_REG, %bx # bx = 00000000FEE00300
+ mov $CMD_REG_TO_READ_DATA, %eax
+ mov %eax, %es:(%ebx) #Fire remove read IPI
+ inc %ch #Pre increment the timeout
+ stc
+ #.while (carry?)
+7: jnc 6f
+ dec %ch #Check the timeout
+ jz fam15_disable_stack_remote_read_exit
+ mov %es:(%ebx), %eax # ax = 0000000000020338
+ bt $DELIVERY_STS_BIT, %eax
+ jmp 7b
+6: #.endw
+ stc
+ #.while (carry?)
+7: jnc 6f
+ mov %es:(%ebx), %eax
+ and $REMOTE_READ_STS, %eax
+ #.if (eax == REMOTE_DELIVERY_PEND)
+ cmp $REMOTE_DELIVERY_PEND, %eax
+ jnz 8f
+ dec %ch # Check the timeout
+ jz fam15_disable_stack_hook_exit # Branch if there is an unreponsive core
+ stc
+ jmp 9f
+8: #.else
+ clc
+9: #.endif
+ jmp 7b
+6: #.endw
+ #.if (eax == REMOTE_DELIVERY_DONE)
+ cmp $REMOTE_DELIVERY_DONE, %eax
+ jnz 6f
+ and $0x0F000, %bx #EBX = LAPIC base, offset 0
+ or $APIC_REMOTE_READ_REG, %bl
+ mov %es:(%ebx), %eax
+ #.if (eax == APIC_MSG)
+ cmp $APIC_MSG, %eax # ax=00000000FFC5BBB2
+ jnz 8f
+ clc
+ jmp 9f
+ #.else
+8: stc
+9: #.endif
+ jmp 7f
+6: #.else
+ dec %ch
+ jz fam15_disable_stack_remote_read_exit
+ stc
+7: #.endif
+ jmp 5b
+4: #.endw
+
+fam15_disable_stack_remote_read_exit:
+ rol $8, %ecx # Restore ECX
+
+1: #.endif
+# jmp 1b
+ bt $AMD_CU_RESTORE_ES, %ecx
+ #.if (carry?)
+ jnc 1f
+ mov %cx, %es
+1:
+ mov %ecx, %edi
+ shr $16, %edx
+ //mov %dx, %bx
+
+ #Handshaking complete. Continue tearing down CAR.
+
+#cz
+ mov $LS_CFG3, %ecx # MSR:C001_101C
+ _RDMSR
+ btr $DIS_SS_F15CZ, %eax # Turn on Streaming store functionality
+ _WRMSR
+
+ mov $IC_CFG, %ecx # MSR:C001_1021
+ _RDMSR
+ btr $IC_DIS_SPEC_TLB_RLD, %eax # Turn on speculative TLB reloads
+ _WRMSR
+
+ mov $LS_CFG3, %ecx # MSR:C001_101C
+ _RDMSR
+ btr $DC_DIS_SPEC_TLB_RLD_F15CZ, %eax # Turn on speculative TLB reloads
+ btr $DC_DIS_HW_PF_F15CZ, %eax # Turn on hardware prefetches
+ _WRMSR
+
+#not cz
+// mov $LS_CFG, %ecx # MSR:C001_1020
+// #.if (bx != 0) ; Is this OR A0?
+// cmp $0x0, %bx
+// jz 0f
+// _RDMSR
+// btr $DIS_SS, %eax # Turn on Streaming store functionality
+// _WRMSR
+// #.endif
+//0: # End workaround for errata 495 and 496
+//
+// inc %ecx #IC_CFG # MSR:C001_1021
+// _RDMSR
+// btr $IC_DIS_SPEC_TLB_RLD, %eax # Turn on speculative TLB reloads
+// _WRMSR
+//
+// inc %ecx #DC_CFG # MSR:C001_1022
+// _RDMSR
+// btr $DC_DIS_SPEC_TLB_RLD, %eax # Turn on speculative TLB reloads
+// #.if (bx != 0) # Is this rev A0?
+// cmp $0, %bx
+// jz 0f
+// btr $DIS_HW_PF, %eax # Turn on hardware prefetches
+// #.endif # End workaround for erratum 498
+// 0:
+// _WRMSR
+# end of not cz
+ #--------------------------------------------------------------------------
+ # Begin critical sequence in which EAX, BX, ECX, and EDX must be preserved.
+ #--------------------------------------------------------------------------
+
+ mov $HWCR, %ecx # MSR:C001_0015h
+ _RDMSR
+ btr $INVD_WBINVD, %eax # Disable INVD -> WBINVD conversion
+ _WRMSR
+ wbinvd #bao # Clear the cache tag RAMs
+# #.if (bh == 01h) || (bh == 03h) ; Is this TN or KM?
+# cmp $01, %bh
+# jz 4f
+# cmp $03, %bh
+# jnz 1f
+#4:
+ mov $CU_CFG, %ecx # MSR:C001_1023
+ _RDMSR
+ shr $L2_FIRST_LOCKED_WAY, %eax
+ and $0x1F, %eax
+ #.if (eax == 01Fh)
+ cmp $0x1F, %eax #Check if way 15 of the L2 needs to be reserved
+ jnz 3f
+ _RDMSR
+ btr $L2_WAY_LOCK_EN, %eax
+ _WRMSR
+3: #.endif
+
+1: #.endif
+ #Do Standard Family 15 work
+ mov $HWCR, %ecx # MSR:C001_0015h
+ _RDMSR
+ bts $INVD_WBINVD, %eax # Turn on Conversion of INVD to WBINVD
+ _WRMSR
+ #.endif # end
+ 0:
+//
+// #--------------------------------------------------------------------------
+// # End critical sequence in which EAX, BX, ECX, and EDX must be preserved.
+// #--------------------------------------------------------------------------
+//
+ mov $CU_CFG3, %ecx # MSR:C001_102B
+ _RDMSR
+ bts $(COMBINE_CR0_CD - 32), %edx # Set CombineCr0Cd bit
+ _WRMSR
+
+ bt $AMD_CU_SEND_INVD_MSG, %edi
+ #.if (carry?)
+ jnc 1f
+ # Non core zero needs to signal to core 0 to proceed
+ mov $APIC_BASE_ADDRESS, %ecx
+ _RDMSR
+ mov %eax, %ebx # EBX = LAPIC base
+ and $0x0F000, %bx # EBX = LAPIC base, offset 0
+ or $APIC_MSG_REG, %bx
+ mov $APIC_MSG, %eax
+ mov %eax, %es:(%ebx) # Signal for core 0 to complete CAR breakdown
+
+1: #.endif
+
+fam15_disable_stack_hook_exit:
+.endm
+
+/*****************************************************************************
+*
+* GET_NODE_ID_CORE_ID_F15 Macro - Stackless
+*
+* Read family specific values to determine the node and core
+* numbers for the core executing this code.
+*
+* Inputs:
+* none
+* Outputs:
+* SI = core#, node# & flags (see GET_NODE_ID_CORE_ID macro above)
+*****************************************************************************/
+.macro GET_NODE_ID_CORE_ID_F15
+
+ LOCAL node_core_f15_exit
+ LOCAL node_core_f15_AP
+ LOCAL node_core_f15_shared
+
+#define F15_L2Size 512
+#define F15_ShareCores 2
+#define F15_AllocMem 0
+#define F15_AllocExe 0
+#define F15_SzAddrBus 48
+#define F15_pad 0
+ cmp $-1, %si # Has node/core already been discovered?
+ jnz node_core_f15_exit # Br if yes
+
+ AMD_CPUID $CPUID_MODEL
+ shr $12, %eax # AL = cpu extended family
+ cmp $06, %ah # Is this family 15h?
+ jnz node_core_f15_exit # Br if no
+ shr $4, %al # AL = cpu extended model
+ shr $16, %ebx # BH = LocalApicId
+ mov %al, %bl # BL = cpu extended model
+
+ # LoadTableAddress(FAM15H_INFO_STRUCT)
+ # movd mm5, eax # load pointer to Family Info Struc
+
+ xor %esi, %esi # Assume BSC, clear local flags
+ mov $APIC_BASE_ADDRESS, %ecx # MSR:0000_001B
+ _RDMSR
+ bt $APIC_BSC, %eax # Is this the BSC?
+ jnc node_core_f15_AP # Br if no
+
+ # This is the BSP.
+ # Enable routing tables on BSP (just in case the HT init code has not yet enabled them)
+ mov $0x8000C06C, %eax # PCI address for D18F0x6C Link Initialization Control Register
+ mov $0x0CF8, %dx
+ out %eax, %dx
+ add $4, %dx
+ in %dx, %eax
+ btr $0, %eax # Set LinkInitializationControl[RouteTblDis] = 0
+ out %eax, %dx
+ jmp node_core_f15_shared #
+
+node_core_f15_AP:
+//1: jmp 1b # not crash
+ mov %bl, %al # AL = cpu extended model
+ shr $8, %bx # BL = CPUID Fn0000_0001_EBX[LocalApicId]
+// cmp $1, %al # Is This TN?
+// jz 4f
+// cmp $3, %al
+// jnz node_core_f15_AP_not_TN
+ mov %bx, %si
+ jmp node_core_f15_shared
+ #
+ # This is an AP. Routing tables have been enabled by the HT Init process.
+ # Also, the MailBox register was set by the BSP during early init
+ # The Mailbox register content is formatted as follows:
+ # UINT32 Node:4; // The node id of Core's node.
+ # UINT32 Socket:4; // The socket of this Core's node.
+ # UINT32 Module:2; // The internal module number for Core's node.
+ # UINT32 ModuleType:2; // Single Module = 0, Multi-module = 1.
+ # UINT32 :20; // Reserved
+ #
+#node_core_f15_AP_not_TN:
+# mov $0x0C0000408, %ecx # Read the family 15h mailbox
+# _RDMSR # MC4_MISC1[63:32]
+# mov %dx, %si # SI = raw mailbox contents (will extract node# from this)
+# shr $24, %ebx # BL = CPUID Fn0000_0001_EBX[LocalApicId]
+# mov %bx, %di # DI = Initial APIC ID (will extract core# from this)
+#
+# AMD_CPUID $AMD_CPUID_APIC #
+# shr $4, %ch # CH = ApicIdSize, #bits in APIC ID that show core#
+# inc %cl # CL = Number of enabled cores in the socket
+# mov %cx, %bx
+#
+# mov $NB_CFG, %ecx
+# _RDMSR # EDX has InitApicIdCpuIdLo bit
+#
+# mov %bh, %cl # CL = APIC ID size
+# mov $1, %al # Convert APIC ID size to an AND mask
+# shl %cl, %al # AL = 2^APIC ID size
+# dec %al # AL = mask for relative core number
+# xor %ah, %ah # AX = mask for relative core number
+# bt $(INIT_APIC_ID_CPU_ID_LO-32), %edx # InitApicIdCpuIdLo == 1?
+# #.if (!carry?) # Br if yes
+# jc 0f
+# mov $8, %ch # Calculate core number shift count
+# sub %cl, %ch # CH = core shift count
+# mov %ch, %cl
+# shr %cl, %di # Right justify core number
+# #.endif
+# 0:
+# and %ax, %di # DI = socket-relative core number
+#
+# mov %si, %cx # CX = raw mailbox value
+# shr $10, %cx # CL[1:0] = ModuleType or #nodes per socket (0-SCM, 1-MCM)
+# and $3, %cl # Isolate ModuleType
+# xor %bh, %bh # BX = Number of enabled cores in the socket
+# shr %cl, %bx # BX = Number of enabled cores per node
+# xor %dx, %dx # Clear upper word for div
+# mov %di, %ax # AX = socket-relative core number
+# div %bx # DX = node-relative core number
+# movzx %si, %eax # Prepare return value
+# and $0x000F, %ax # AX = node number
+# shl $8,%ax # [15:8]=node#
+# mov %dl, %al # [7:0]=core# (relative to node)
+# mov %eax, %esi # ESI = node-relative core number
+#
+ #
+ # determine if this core shares MTRRs
+ #
+node_core_f15_shared:
+ mov $0x8000C580, %eax # Compute Unit Status
+ mov %si, %bx
+ shl $3, %bh # Move node# to PCI Dev# field
+ add %bh, %ah # Adjust for node number
+ mov $0x0CF8, %dx
+ out %eax, %dx
+ add $4, %dx
+ in %dx, %eax # [3:0]=Enabled# [19:16]=DualCore
+
+ # BL is MyCore#
+ mov $0x08, %cx # Use CH as 'first of pair' core#
+ #.while (cl > 0)
+ jmp 0f
+ 8:
+ bt $0, %eax # Is pair enabled?
+ #.if (carry?) #
+ jnc 1f
+ mov $0x01, %bh # flag core as primary
+ bt $16, %eax # Is there a 2nd in the pair?
+ #.if (carry?) #
+ jnc 4f
+ #.break .if (ch == bl) # Does 1st match MyCore#?
+ cmp %bl, %ch
+ je 9f
+ inc %ch
+ xor %bh, %bh # flag core as NOT primary
+ #.break .if (ch == bl) # Does 2nd match MyCore#?
+ cmp %bl, %ch
+ je 9f
+ jmp 2f
+ #.else # No 2nd core
+ 4:
+ #.break .if (ch == bl) # Does 1st match MyCore#?
+ cmp %bl, %ch
+ je 9f
+ #.endif
+ 2:
+ inc %ch
+ #.endif
+ 1:
+ shr $1, %eax
+ dec %cl
+ #.endw
+ 0:
+ #.if (cl == 0)
+ cmp $0x0, %cl
+ ja 8b
+ 9:
+ or %cl, %cl
+ jne 1f
+ #Error - core# didn't match Compute Unit Status content
+ bts $FLAG_CORE_NOT_IDENTIFIED, %esi
+ bts $FLAG_IS_PRIMARY, %esi # Set Is_Primary for unknowns
+ #.endif
+ 1:
+ #.if (bh != 0) # Check state of primary for the matched core
+ or %bh, %bh
+ je 2f
+ bts $FLAG_IS_PRIMARY, %esi # Set shared flag into return value
+ #.endif
+ 2:
+
+node_core_f15_exit:
+
+.endm
+
+/*****************************************************************************
+* AMD_ENABLE_STACK: Setup a stack
+*
+* In:
+* EBX = Return address (preserved)
+*
+* Out:
+* SS:ESP - Our new private stack location
+*
+* EAX = AGESA_STATUS
+*
+* ECX = Stack size in bytes
+*
+* Requirements:
+* * This routine presently is limited to a max of 64 processor cores
+* Preserved:
+* ebx ebp
+* Destroyed:
+* eax, ecx, edx, edi, esi, ds, es, ss, esp
+* mmx0, mmx1
+*
+* Description:
+* Fixed MTRR address allocation to cores:
+* The BSP gets 64K of stack, Core0 of each node gets 16K of stack, all other cores get 4K.
+* There is a max of 1 BSP, 7 core0s and 56 other cores.
+* Although each core has it's own cache storage, they share the address space. Each core must
+* be assigned a private and unique address space for its stack. To support legacy systems,
+* the stack needs to be within the legacy address space (1st 1Meg). Room must also be reserved
+* for the other legacy elements (Interrupt vectors, BIOS ROM, video buffer, etc.)
+*
+* 80000h 40000h 00000h
+* +----------+----------+----------+----------+----------+----------+----------+----------+
+* 64K | | | | | | | | | 64K ea
+* ea +----------+----------+----------+----------+----------+----------+----------+----------+
+* | MTRR 0000_0250 MTRRfix64K_00000 |
+* +----------+----------+----------+----------+----------+----------+----------+----------+
+* | 7 , 6 | 5 , 4 | 3 , 2 | 1 , 0 | 0 | | | | <-node
+* |7..1,7..1 |7..1,7..1 |7..1,7..1 |7..1,7..1 | 0 | | | | <-core
+* +----------+----------+----------+----------+----------+----------+----------+----------+
+*
+* C0000h B0000h A0000h 90000h 80000h
+* +------+------+------+------+------+------+------+------+------+------+------+------+------+------+------+------+
+*16K | | | | | | | | | | | | | | | | |
+* ea +------+------+------+------+------+------+------+------+------+------+------+------+------+------+------+------+
+* | MTRR 0259 MTRRfix16K_A0000 | MTRR 0258 MTRRfix16K_80000 |
+* +------+------+------+------+------+------+------+------+------+------+------+------+------+------+------+------+
+* | > Dis|play B|uffer | < | | | | | 7 | 6 | 5 | 4 | 3 | 2 | 1 | | <-node
+* | > T| e m |p o r |a r y | B u |f f e |r A |r e a<| 0 | 0 | 0 | 0 | 0 | 0 | 0 | | <-core
+* +------+------+------+------+------+------+------+------+------+------+------+------+------+------+------+------+
+*
+* E0000h D0000h C0000h
+* +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
+* 4K | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 4K ea
+* ea +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
+* | 026B MTRRfix4K_D8000 | 026A MTRRfix4K_D0000 | 0269 MTRRfix4K_C8000 | 0268 MTRRfix4K_C0000 |
+* +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
+* | | | | | | | | | | | | | | | | | >| V| I| D| E| O| |B |I |O |S | |A |r |e |a<|
+* +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
+*
+* 100000h F0000h E0000h
+* +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
+* | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 4K ea
+* +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
+* | 026F MTRRfix4K_F8000 | 026E MTRRfix4K_F0000 | 026D MTRRfix4K_E8000 | 026C MTRRfix4K_E0000 |
+* +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
+* | >|MA|IN| B|IO|S |RA|NG|E | | | | | | |< | >|EX|TE|ND|ED| B|IO|S |ZO|NE| | | | | |< |
+* +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
+*****************************************************************************/
+.macro AMD_ENABLE_STACK
+
+# These are local labels. Declared so linker doesn't cause 'redefined label' errors
+ LOCAL SetupStack
+ LOCAL Real16bMode
+ LOCAL Protected32Mode
+ LOCAL ClearTheStack
+
+# Note that SS:ESP will be default stack. Note that this stack
+# routine will not be used after memory has been initialized. Because
+# of its limited lifetime, it will not conflict with typical PCI devices.
+ movd %ebx, %mm0 # Put return address in a safe place
+ movd %ebp, %mm1 # Save some other user registers
+
+ # get node id and core id of current executing core
+ GET_NODE_ID_CORE_ID # Sets ESI[23:16]=Shared core## SI[15,8]= Node## SI[7,0]= core# (relative to node)
+ # Note: ESI[31:24] are used for flags: Unrecognized Family, Is_Primary core, Stack already established
+
+ # determine if stack is already enabled. We are using the DefType MSR for this determination.
+ # It is =0 after reset; CAR setup sets it to enable the MTRRs
+ mov %cr0, %eax
+ test $CR0_MASK, %eax # Is cache disabled? (CD & NW bits)
+ jnz SetupStack # Jump if yes
+ mov $AMD_MTRR_DEFTYPE, %ecx # MSR:0000_02FF
+ _RDMSR
+ test $MSR_MASK, %eax # Are the default types enabled? (MTRR_DEF_TYPE_EN + MTRR_DEF_TYPE_FIX_EN)
+ jz SetupStack # Jump if no
+ or $FLAG_STACK_REENTRY, %esi # Bit25, indicate stack has already been initialized
+
+SetupStack:
+ # Set node to map the first 16MB to node 0# 0000_0000 to 00FF_FFFF as DRAM
+ mov %esi, %ebx # Get my Node/Core info
+ xor %bl, %bl
+ shl $3, %bh # Isolate my node#, match alignment for PCI Dev#
+ mov $0x8000C144, %eax # D18F1x44:DRAM Base/Limit# N is Base, N+4 is Limit
+ add %bh, %ah
+ mov %eax, %ebx # Save PCI address for Base/Limit pair
+
+ mov $0x0CF8, %dx
+ out %eax, %dx
+ add $4, %dx
+ xor %eax, %eax # Least Significant bit is AD24 so 0 sets mask of 00FF_FFFF (16MB)
+ out %eax, %dx # DRAM Limit = node0, no interleave
+
+ mov %ebx, %eax
+ sub $4, %eax # Now point to the Base register
+ mov $0x0CF8, %dx
+ out %eax, %dx
+ add $4, %dx
+ mov $0x00000003, %eax # Set the read and write enable bits
+ out %eax, %dx # DRAM Base = 0x0000, R/W
+
+ AMD_ENABLE_STACK_FAMILY_HOOK
+
+ # Init CPU MSRs for our init routines
+ mov $MTRR_SYS_CFG, %ecx # SYS_CFG
+ _RDMSR
+ bts $MTRR_FIX_DRAM_MOD_EN, %eax # Turn on modification enable bit
+ _WRMSR
+
+ mov %esi, %eax
+ bt $FLAG_STACK_REENTRY, %eax # Is this a 2nd entry?
+ #.if (!carry?) # On a re-entry, do not clear MTRRs or reset TOM; just reset the stack SS:ESP
+ jc 0f
+ bt $FLAG_IS_PRIMARY, %eax # Is this core the primary in a compute unit?
+ #.if (carry?) # Families using shared groups do not need to clear the MTRRs since that is done at power-on reset
+ # Note: Relying on MSRs to be cleared to 0's at reset for families w/shared cores
+ # Clear all variable and Fixed MTRRs for non-shared cores
+ jnc 0f
+ mov $AMD_MTRR_VARIABLE_BASE0, %ecx
+ xor %eax, %eax
+ xor %edx, %edx
+ #.while (cl != 10h) # Variable MTRRphysBase[n] and MTRRphysMask[n]
+ jmp 1f
+ 2:
+ _WRMSR
+ inc %cl
+ #.endw
+ 1:
+ cmp $0x10, %cl
+ jne 2b
+ mov $AMD_MTRR_FIX64k_00000, %cx # MSR:0000_0250
+ _WRMSR
+ mov $AMD_MTRR_FIX16k_80000, %cx # MSR:0000_0258
+ _WRMSR
+ mov $AMD_MTRR_FIX16k_A0000, %cx # MSR:0000_0259
+ _WRMSR
+ mov $AMD_MTRR_FIX4k_C0000, %cx # Fixed 4Ks: MTRRfix4K_C0000 to MTRRfix4K_F8000
+ #.while (cl != 70h)
+ jmp 3f
+ 4:
+ _WRMSR
+ inc %cl
+ #.endw
+ 3:
+ cmp $0x70, %cl
+ jne 4b
+ # Set TOP_MEM (C001_001A) for non-shared cores to 16M. This will be increased at heap init.
+ # - not strictly needed since the FixedMTRRs take presedence.
+ mov $(16 * 1024 * 1024), %eax
+ mov $TOP_MEM, %ecx # MSR:C001_001A
+ _WRMSR
+ #.endif # End Is_Primary
+ #.endif # End Stack_ReEntry
+ 0:
+ # Clear IORRs (C001_0016-19) and TOM2(C001_001D) for all cores
+ xor %eax, %eax
+ xor %edx, %edx
+ mov $IORR_BASE, %ecx # MSR:C001_0016 - 0019
+ #.while (cl != 1Ah)
+ jmp 1f
+ 2:
+ _WRMSR
+ inc %cl
+ #.endw
+ 1:
+ cmp $0x1A, %cl
+ jne 2b
+ mov $TOP_MEM2, %ecx # MSR:C001_001D
+ _WRMSR
+
+ # setup MTTRs for stacks
+ # A speculative read can be generated by a speculative fetch mis-aligned in a code zone
+ # or due to a data zone being interpreted as code. When a speculative read occurs outside a
+ # controlled region (intentionally used by software), it could cause an unwanted cache eviction.
+ # To prevent speculative reads from causing an eviction, the unused cache ranges are set
+ # to UC type. Only the actively used regions (stack, heap) are reflected in the MTRRs.
+ # Note: some core stack regions will share an MTRR since the control granularity is much
+ # larger than the allocated stack zone. The allocation algorithm must account for this 'extra'
+ # space covered by the MTRR when parseling out cache space for the various uses. In some cases
+ # this could reduce the amount of EXE cache available to a core. see cpuCacheInit.c
+ #
+ # Outcome of this block is that: (Note the MTRR map at the top of the file)
+ # ebp - start address of stack block
+ # ebx - [31:16] - MTRR MSR address
+ # - [15:8] - slot# in MTRR register
+ # - [7:0] - block size in #4K blocks
+ # review: ESI[31:24]=Flags; SI[15,8]= Node#; SI[7,0]= core# (relative to node)
+ #
+
+ mov %esi, %eax # Load Flags,node, core
+ #.if (al == 0) # Is a core 0?
+ or %al, %al
+ jne 1f
+ #.if (ah == 0) # Is Node 0? (BSP)
+ or %ah, %ah
+ jne 2f
+ # Is BSP, assign a 64K stack
+ mov $((AMD_MTRR_FIX64k_00000 << 16) + (3 << 8) + (BSP_STACK_SIZE >> 12)), %ebx
+ bt $FLAG_FORCE_32K_STACK, %eax
+ jnc w64k_here # Br if no
+ mov $((AMD_MTRR_FIX64k_00000 << 16) + (3 << 8) + (BSP_STACK_SIZE_32K >> 12)), %ebx
+w64k_here:
+ mov $BSP_STACK_BASE_ADDR, %ebp
+ jmp 0f
+ #.else # node 1 to 7, core0
+ 2:
+ # Is a Core0 of secondary node, assign 16K stacks
+ mov $AMD_MTRR_FIX16k_80000, %bx
+ shl $16, %ebx #
+ dec %ah #index from 0
+ mov %ah, %bh # Node# is used as slot#
+ mov $(CORE0_STACK_SIZE >> 12), %bl
+ mov %ah, %al # Base = (Node# * Size)#
+ mul %bl #
+ movzx %ax, %eax #
+ shl $12, %eax # Expand back to full byte count (* 4K)
+ add $CORE0_STACK_BASE_ADDR, %eax
+ mov %eax, %ebp
+ #.endif
+ jmp 0f
+ #.else #core 1 thru core 7
+ 1:
+ # Is core 1-7 of any node, assign 4K stacks
+ mov $8, %al # CoreIndex = ( (Node# * 8) ...
+ mul %ah #
+ mov %si, %bx #
+ add %bl, %al # ... + Core#)#
+
+ mov $AMD_MTRR_FIX64k_00000, %bx
+ shl $16, %ebx #
+ mov %al, %bh # Slot# = (CoreIndex / 16) + 4#
+ shr $4, %bh #
+ add $4, %bh #
+ mov $(CORE1_STACK_SIZE >> 12), %bl
+
+ mul %bl # Base = ( (CoreIndex * Size) ...
+ movzx %ax, %eax #
+ shl $12, %eax # Expand back to full byte count (* 4K)
+ add $CORE1_STACK_BASE_ADDR, %eax # ... + Base_Addr)#
+ mov %eax, %ebp
+ #.endif
+ 0:
+
+ # Now set the MTRR. Add this to already existing settings (don't clear any MTRR)
+ mov $WB_DRAM_TYPE, %edi # Load Cache type in 1st slot
+ mov %bh, %cl # ShiftCount = ((slot# ...
+ and $0x03, %cl # ... % 4) ...
+ shl $0x03, %cl # ... * 8)#
+ shl %cl, %edi # Cache type is now in correct position
+ ror $16, %ebx # Get the MTRR address
+ movzx %bx, %ecx #
+ rol $16, %ebx # Put slot# & size back in BX
+ _RDMSR # Read-modify-write the MSR
+ #.if (bh < 4) # Is value in lower or upper half of MSR?
+ cmp $4, %bh
+ jae 1f
+ or %edi, %eax #
+ jmp 0f
+ #.else
+ 1: #
+ or %edi, %edx #
+ #.endif #
+ 0:
+ _WRMSR #
+
+ # Enable MTRR defaults as UC type
+ mov $AMD_MTRR_DEFTYPE, %ecx # MSR:0000_02FF
+ _RDMSR # Read-modify-write the MSR
+ bts $MTRR_DEF_TYPE_EN, %eax # MtrrDefTypeEn
+ bts $MTRR_DEF_TYPE_FIX_EN, %eax # MtrrDefTypeFixEn
+ _WRMSR
+
+ # Close the modification window on the Fixed MTRRs
+ mov $MTRR_SYS_CFG, %ecx # MSR:0C001_0010
+ _RDMSR
+ bts $MTRR_FIX_DRAM_EN, %eax # MtrrFixDramEn
+ bts $MTRR_VAR_DRAM_EN, %eax # variable MTRR enable bit
+ btr $MTRR_FIX_DRAM_MOD_EN, %eax # Turn off modification enable bit
+ _WRMSR
+
+ # Enable caching in CR0
+ mov %cr0, %eax # Enable WT/WB cache
+ btr $CR0_PG, %eax # Make sure paging is disabled
+ btr $CR0_CD, %eax # Clear CR0 NW and CD
+ btr $CR0_NW, %eax
+ mov %eax, %cr0
+
+ # Use the Stack Base & size to calculate SS and ESP values
+ # review:
+ # esi[31:24]=Flags; esi[15,8]= Node#; esi[7,0]= core# (relative to node)
+ # ebp - start address of stack block
+ # ebx - [31:16] - MTRR MSR address
+ # - [15:8] - slot# in MTRR register
+ # - [7:0] - block size in #4K blocks
+ #
+ mov %ebp, %esp # Initialize the stack pointer
+ mov %esp, %edi # Copy the stack start to edi
+ movzx %bl, %bx
+ movzx %bx, %ebx # Clear upper ebx, don't need MSR addr anymore
+ shl $12, %ebx # Make size full byte count (* 4K)
+ add %ebx, %esp # Set the Stack Pointer as full linear address
+ sub $4, %esp
+ #
+ # review:
+ # esi[31:24]=Flags; esi[15,8]= Node#; esi[7,0]= core# (relative to node)
+ # edi - 32b start address of stack block
+ # ebx - size of stack block
+ # esp - 32b linear stack pointer
+ #
+
+ # Determine mode for SS base;
+ mov %cr0, %ecx # Check for 32-bit protect mode
+ bt $CR0_PE, %ecx #
+ #.if (!carry?) # PE=0 means real mode
+ jc Protected32Mode
+ mov %cs, %cx # PE=1
+ cmp $0x0D000, %cx # Check for CS
+ jb Protected32Mode # If CS < D000, it is a selector instead of a segment
+ # alter SS:ESP for 16b Real Mode:
+Real16bMode:
+ mov %edi, %eax
+ shr $4, %eax # Create a Real Mode segment for ss, ds, es
+ mov %ax, %ss
+ mov %ax, %ds
+ mov %ax, %es
+ shl $4, %eax
+ sub %eax, %edi # Adjust the clearing pointer for Seg:Offset mode
+ mov %ebx, %esp # Make SP an offset from SS
+ sub $4, %esp #
+ # .endif # endif
+ # #else
+ # Default is to use Protected 32b Mode
+ #.endif
+ ;
+Protected32Mode:
+ #
+ # Clear The Stack
+ # Now that we have set the location and the MTRRs, initialize the cache by
+ # reading then writing to zero all of the stack area.
+ # review:
+ # ss - Stack base
+ # esp - stack pointer
+ # ebx - size of stack block
+ # esi[31:24]=Flags; esi[15,8]= Node#; esi[7,0]= core# (relative to node)
+ # edi - address of start of stack block
+ #
+
+ClearTheStack: # Stack base is in SS, stack pointer is in ESP
+ shr $2, %ebx # ebx = stack block size in dwords
+ mov %bx, %cx #
+ # Check our flags - Don't clear an existing stack
+ #.if ( !(esi & 0FF000000h)) # Check our flags
+ test $(1 << FLAG_STACK_REENTRY), %esi
+ jne 1f
+ cld
+ mov %edi, %esi
+ rep lodsl (%esi) # Pre-load the range
+ xor %eax, %eax
+ mov %bx, %cx
+ mov %edi, %esi # Preserve base for push on stack
+ rep stosl (%edi) # Clear the range
+ movl $0x0ABCDDCBA, (%esp) # Put marker in top stack dword
+ shl $2, %ebx # Put stack size and base
+ push %ebx # in top of stack
+ push %esi
+
+ mov %ebx, %ecx # Return size of stack in bytes
+ xor %eax, %eax # eax = 0 : no error return code
+ jmp 0f
+ #.else
+ 1:
+ movzx %cx, %ecx
+ shl $2, %ecx # Return size of stack in bytes
+ mov %esi, %eax
+ shr $24, %eax # Keep the flags as part of the error report
+ or $0x40000000, %eax # eax = AGESA_WARNING (Stack has already been set up)
+ #.endif
+ 0:
+
+ movd %mm0, %ebx # Restore return address
+ movd %mm1, %ebp
+.endm
+
+/*****************************************************************************
+* AMD_DISABLE_STACK: Destroy the stack inside the cache. This routine
+* should only be executed on the BSP
+*
+* In:
+* none
+*
+* Out:
+* EAX = AGESA_SUCCESS
+*
+* Preserved:
+* ebx
+* Destroyed:
+* eax, ecx, edx, esp
+*****************************************************************************/
+.macro AMD_DISABLE_STACK
+
+ mov %ebx, %esp # Save return address
+
+ # get node/core/flags of current executing core
+ GET_NODE_ID_CORE_ID # Sets ESI[15,8]= Node#; ESI[7,0]= core# (relative to node)
+#1: jmp 1b
+ # Turn on modification enable bit
+ mov $MTRR_SYS_CFG, %ecx # MSR:C001_0010
+ _RDMSR
+ bts $MTRR_FIX_DRAM_MOD_EN, %eax # Enable modifications
+ _WRMSR
+
+ # Set lower 640K MTRRs for Write-Back memory caching
+ mov $AMD_MTRR_FIX64k_00000, %ecx
+ mov $0x1E1E1E1E, %eax
+ mov %eax, %edx
+ _WRMSR # 0 - 512K = WB Mem
+ mov $AMD_MTRR_FIX16k_80000, %ecx
+ _WRMSR # 512K - 640K = WB Mem
+
+ # Turn off modification enable bit
+ mov $MTRR_SYS_CFG, %ecx # MSR:C001_0010
+ _RDMSR
+ btr $MTRR_FIX_DRAM_MOD_EN, %eax # Disable modification
+ _WRMSR
+
+ AMD_DISABLE_STACK_FAMILY_HOOK # Re-Enable 'normal' cache operations
+
+ mov %esp, %ebx
+ xor %eax, %eax
+
+.endm
+
diff --git a/src/vendorcode/amd/pi/00730F01/AGESA.h b/src/vendorcode/amd/pi/00730F01/AGESA.h
new file mode 100644
index 0000000..8132c61
--- /dev/null
+++ b/src/vendorcode/amd/pi/00730F01/AGESA.h
@@ -0,0 +1,3657 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Agesa structures and definitions
+ *
+ * Contains AMD AGESA core interface
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: Include
+ * @e \$Revision: 281178 $ @e \$Date: 2013-12-18 02:14:15 -0600 (Wed, 18 Dec 2013) $
+ */
+/*****************************************************************************
+ *
+ * Copyright (c) 2008 - 2014, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ***************************************************************************/
+
+
+#ifndef _AGESA_H_
+#define _AGESA_H_
+
+#include "Porting.h"
+#include "AMD.h"
+
+//
+//
+// AGESA Types and Definitions
+//
+//
+
+// AGESA BASIC CALLOUTS
+#define AGESA_MEM_RELEASE 0x00028000ul
+
+// AGESA ADVANCED CALLOUTS, Processor
+#define AGESA_CHECK_UMA 0x00028100ul
+#define AGESA_DO_RESET 0x00028101ul
+#define AGESA_ALLOCATE_BUFFER 0x00028102ul
+#define AGESA_DEALLOCATE_BUFFER 0x00028103ul
+#define AGESA_LOCATE_BUFFER 0x00028104ul
+#define AGESA_RUNFUNC_ONAP 0x00028105ul
+#define AGESA_PUBLISH_CS_RESTORATION_DATA 0x00028106ul
+
+// AGESA ADVANCED CALLOUTS, Memory
+#define AGESA_READ_SPD 0x00028140ul
+#define AGESA_HOOKBEFORE_DRAM_INIT 0x00028141ul
+#define AGESA_HOOKBEFORE_DQS_TRAINING 0x00028142ul
+#define AGESA_READ_SPD_RECOVERY 0x00028143ul
+#define AGESA_HOOKBEFORE_EXIT_SELF_REF 0x00028144ul
+#define AGESA_HOOKBEFORE_DRAM_INIT_RECOVERY 0x00028145ul
+#define AGESA_EXTERNAL_2D_TRAIN_VREF_CHANGE 0x00028146ul
+#define AGESA_EXTERNAL_VOLTAGE_ADJUST 0x00028147ul
+
+// AGESA IDS CALLOUTS
+#define AGESA_GET_IDS_INIT_DATA 0x00028200ul
+
+// AGESA GNB CALLOUTS
+#define AGESA_GNB_PCIE_SLOT_RESET 0x00028301ul
+#define AGESA_GNB_GFX_GET_VBIOS_IMAGE 0x00028302ul
+#define AGESA_GNB_PCIE_CLK_REQ 0x00028303ul
+
+// AGESA FCH CALLOUTS
+#define AGESA_FCH_OEM_CALLOUT 0x00028401ul
+
+//-----------------------------------------------------------------------------
+// FCH DEFINITIONS AND MACROS
+//
+//-----------------------------------------------------------------------------
+
+/// Configuration values for SdConfig
+typedef enum {
+ SdDisable = 0, ///< Disabled
+ SdAmda, ///< AMDA, set 24,18,16, default
+ SdDma, ///< DMA clear 24, 16, set 18
+ SdPio, ///< PIO clear 24,18,16
+ SdDump ///< SD DUMP, don't touch SD
+} SD_MODE;
+
+/// Configuration values for SdClockControl
+typedef enum {
+ Sd50MhzTraceCableLengthWithinSixInches = 4, ///< 50Mhz, default
+ Sd40MhzTraceCableLengthSix2ElevenInches = 6, ///< 40Mhz
+ Sd25MhzTraceCableLengthEleven2TwentyfourInches = 7, ///< 25Mhz
+} SD_CLOCK_CONTROL;
+
+/// Configuration values for AzaliaController
+typedef enum {
+ AzAuto = 0, ///< Auto - Detect Azalia controller automatically
+ AzDisable, ///< Diable - Disable Azalia controller
+ AzEnable ///< Enable - Enable Azalia controller
+} HDA_CONFIG;
+
+/// Configuration values for IrConfig
+typedef enum {
+ IrDisable = 0, ///< Disable
+ IrRxTx0 = 1, ///< Rx and Tx0
+ IrRxTx1 = 2, ///< Rx and Tx1
+ IrRxTx0Tx1 = 3 ///< Rx and both Tx0,Tx1
+} IR_CONFIG;
+
+/// Configuration values for SataClass
+typedef enum {
+ SataNativeIde = 0, ///< Native IDE mode
+ SataRaid, ///< RAID mode
+ SataAhci, ///< AHCI mode
+ SataLegacyIde, ///< Legacy IDE mode
+ SataIde2Ahci, ///< IDE->AHCI mode
+ SataAhci7804, ///< AHCI mode as 7804 ID (AMD driver)
+ SataIde2Ahci7804 ///< IDE->AHCI mode as 7804 ID (AMD driver)
+} SATA_CLASS;
+
+/// Configuration values for BLDCFG_FCH_GPP_LINK_CONFIG
+typedef enum {
+ PortA4 = 0, ///< 4:0:0:0
+ PortA2B2 = 2, ///< 2:2:0:0
+ PortA2B1C1 = 3, ///< 2:1:1:0
+ PortA1B1C1D1 = 4 ///< 1:1:1:1
+} GPP_LINKMODE;
+
+/// Configuration values for FchPowerFail
+typedef enum {
+ AlwaysOff = 0, ///< Always power off after power resumes
+ AlwaysOn = 1, ///< Always power on after power resumes
+ UsePrevious = 3, ///< Resume to same setting when power fails
+} POWER_FAIL;
+
+
+/// Configuration values for SATA Link Speed
+typedef enum {
+ Gen1 = 1, ///< SATA port GEN1 speed
+ Gen2 = 2, ///< SATA port GEN2 speed
+ Gen3 = 3, ///< SATA port GEN3 speed
+} SATA_SPEED;
+
+
+/// Configuration values for GPIO function
+typedef enum {
+ Function0 = 0, ///< GPIO Function 1
+ Function1 = 1, ///< GPIO Function 1
+ Function2 = 2, ///< GPIO Function 2
+ Function3 = 3, ///< GPIO Function 3
+} GPIO_FUN;
+
+/// Configuration values for memory phy voltage (VDDR)
+typedef enum {
+ VOLT0_95, ///< VDDR 0.95V
+ VOLT1_05, ///< VDDR 1.05V
+ MAX_VDDR ///< Maxmum value for this enum definition
+} MEMORY_PHY_VOLTAGE;
+
+/// Configuration values for GPIO_CFG
+typedef enum {
+ OwnedByEc = 1 << 0, ///< This bit can only be written by EC
+ OwnedByHost = 1 << 1, ///< This bit can only be written by host (BIOS)
+ Sticky = 1 << 2, ///< If set, [6:3] are sticky
+ PullUpB = 1 << 3, ///< 0: Pullup enable; 1: Pullup disabled
+ PullDown = 1 << 4, ///< 0: Pulldown disabled; 1: Pulldown enable
+ GpioOutEnB = 1 << 5, ///< 0: Output enable; 1: Output disable
+ GpioOut = 1 << 6, ///< Output state when GpioOutEnB is 0
+ GpioIn = 1 << 7, ///< This bit is read only - current pin state
+} CFG_BYTE;
+
+/// Configuration values for GPIO_CFG2
+typedef enum {
+ DrvStrengthSel_4mA = 0 << 1, ///< 18:17 DrvStrengthSel.
+ DrvStrengthSel_8mA = 1 << 1, ///< 18:17 DrvStrengthSel.
+ DrvStrengthSel_12mA = 2 << 1, ///< 18:17 DrvStrengthSel.
+ DrvStrengthSel_16mA = 3 << 1, ///< 18:17 DrvStrengthSel.
+ PullUpSel_8K = 1 << 3, ///< 19 PullUpSel. Read-write. 0=4 K pull-up is selected. 1=8 K pull-up is selected.
+ PullUpEnable = 1 << 4, ///< 20 PullUpEnable. Read-write. 0=Pull-up is disabled on the pin. 1=Pull-up is enabled on the pin.
+ PullDownEnable = 1 << 5, ///< 21 PullDownEnable. Read-write. 0=Pull-down is disabled on the pin. 1=Pull-down is enabled on thepin.
+ OutputValue = 1 << 6, ///< 22 OutputValue. Read-write. 0=low. 1=high.
+ OutputEnable = 1 << 7, ///< 23 OutputEnable. Read-write. 0=Output is disabled on the pin. 1=Output is enabled on the pin.
+} CFG2_BYTE;
+
+/// FCH GPIO CONTROL
+typedef struct {
+ IN UINT8 GpioPin; ///< Gpio Pin, valid range: 0-67, 128-150, 160-228
+ IN GPIO_FUN PinFunction; ///< Multi-function selection
+ IN CFG_BYTE CfgByte; ///< GPIO Register value
+} GPIO_CONTROL;
+
+///
+/// FCH SCI MAP CONTROL
+///
+typedef struct {
+ IN UINT8 InputPin; ///< Input Pin, valid range 0-63
+ IN UINT8 GpeMap; ///< Gpe Map, valid range 0-31
+} SCI_MAP_CONTROL;
+
+///
+/// FCH SATA PHY CONTROL
+///
+typedef struct {
+ IN BOOLEAN CommonPhy; ///< Common PHY or not
+ ///< @li <b>FALSE</b> - Only applied to specified port
+ ///< @li <b>TRUE</b> - Apply to all SATA ports
+ IN SATA_SPEED Gen; ///< SATA speed
+ IN UINT8 Port; ///< Port number, valid range: 0-7
+ IN UINT32 PhyData; ///< SATA PHY data, valid range: 0-0xFFFFFFFF
+} SATA_PHY_CONTROL;
+
+///
+/// FCH Component Data Structure in InitReset stage
+///
+typedef struct {
+ IN BOOLEAN UmiGen2; ///< Enable Gen2 data rate of UMI
+ ///< @li <b>FALSE</b> - Disable Gen2
+ ///< @li <b>TRUE</b> - Enable Gen2
+
+ IN BOOLEAN SataEnable; ///< SATA controller function
+ ///< @li <b>FALSE</b> - SATA controller is disabled
+ ///< @li <b>TRUE</b> - SATA controller is enabled
+
+ IN BOOLEAN IdeEnable; ///< SATA IDE controller mode enabled/disabled
+ ///< @li <b>FALSE</b> - IDE controller is disabled
+ ///< @li <b>TRUE</b> - IDE controller is enabled
+
+ IN BOOLEAN GppEnable; ///< Master switch of GPP function
+ ///< @li <b>FALSE</b> - GPP disabled
+ ///< @li <b>TRUE</b> - GPP enabled
+
+ IN BOOLEAN Xhci0Enable; ///< XHCI0 controller function
+ ///< @li <b>FALSE</b> - XHCI0 controller disabled
+ ///< @li <b>TRUE</b> - XHCI0 controller enabled
+
+ IN BOOLEAN Xhci1Enable; ///< XHCI1 controller function
+ ///< @li <b>FALSE</b> - XHCI1 controller disabled
+ ///< @li <b>TRUE</b> - XHCI1 controller enabled
+} FCH_RESET_INTERFACE;
+
+
+///
+/// FCH Component Data Structure from InitEnv stage
+///
+typedef struct {
+ IN SD_MODE SdConfig; ///< Secure Digital (SD) controller mode
+ IN HDA_CONFIG AzaliaController; ///< Azalia HD Audio Controller
+
+ IN IR_CONFIG IrConfig; ///< Infrared (IR) Configuration
+ IN BOOLEAN UmiGen2; ///< Enable Gen2 data rate of UMI
+ ///< @li <b>FALSE</b> - Disable Gen2
+ ///< @li <b>TRUE</b> - Enable Gen2
+
+ IN SATA_CLASS SataClass; ///< SATA controller mode
+ IN BOOLEAN SataEnable; ///< SATA controller function
+ ///< @li <b>FALSE</b> - SATA controller is disabled
+ ///< @li <b>TRUE</b> - SATA controller is enabled
+
+ IN BOOLEAN IdeEnable; ///< SATA IDE controller mode enabled/disabled
+ ///< @li <b>FALSE</b> - IDE controller is disabled
+ ///< @li <b>TRUE</b> - IDE controller is enabled
+
+ IN BOOLEAN SataIdeMode; ///< Native mode of SATA IDE controller
+ ///< @li <b>FALSE</b> - Legacy IDE mode
+ ///< @li <b>TRUE</b> - Native IDE mode
+
+ IN BOOLEAN Ohci1Enable; ///< OHCI controller #1 Function
+ ///< @li <b>FALSE</b> - OHCI1 is disabled
+ ///< @li <b>TRUE</b> - OHCI1 is enabled
+
+ IN BOOLEAN Ohci2Enable; ///< OHCI controller #2 Function
+ ///< @li <b>FALSE</b> - OHCI2 is disabled
+ ///< @li <b>TRUE</b> - OHCI2 is enabled
+
+ IN BOOLEAN Ohci3Enable; ///< OHCI controller #3 Function
+ ///< @li <b>FALSE</b> - OHCI3 is disabled
+ ///< @li <b>TRUE</b> - OHCI3 is enabled
+
+ IN BOOLEAN Ohci4Enable; ///< OHCI controller #4 Function
+ ///< @li <b>FALSE</b> - OHCI4 is disabled
+ ///< @li <b>TRUE</b> - OHCI4 is enabled
+
+ IN BOOLEAN GppEnable; ///< Master switch of GPP function
+ ///< @li <b>FALSE</b> - GPP disabled
+ ///< @li <b>TRUE</b> - GPP enabled
+
+ IN POWER_FAIL FchPowerFail; ///< FCH power failure option
+} FCH_INTERFACE;
+
+
+/*----------------------------------------------------------------------------
+ * CPU Feature related info
+ *----------------------------------------------------------------------------
+ */
+/// Build Configuration values for BLDCFG_PLATFORM_CONNECTED_STANDBY_MODE
+typedef enum {
+ ConnectedStandbyAuto = 0, ///< Auto
+ ConnectedStandbyDisabled = 1, ///< Disabled
+ MaxConnectedStandbyMode = 2 ///< Not a valid value, used for verifying input
+} PLATFORM_CONNECTED_STANDBY_MODES;
+
+/// Build Configuration values for BLDCFG_PLATFORM_CSTATE_MODE
+typedef enum {
+ CStateModeDisabled = 0, ///< Disabled
+ CStateModeC6 = 1, ///< C6 State
+ MaxCStateMode = 2 ///< Not a valid value, used for verifying input
+} PLATFORM_CSTATE_MODES;
+
+/// Build Configuration values for BLDCFG_PLATFORM_CPB_MODE
+typedef enum {
+ CpbModeAuto = 0, ///< Auto
+ CpbModeDisabled = 1, ///< Disabled
+ MaxCpbMode = 2 ///< Not a valid value, used for verifying input
+} PLATFORM_CPB_MODES;
+
+/// Build Configuration values for BLDCFG_LOW_POWER_PSTATE_FOR_PROCHOT_MODE
+typedef enum {
+ LOW_POWER_PSTATE_FOR_PROCHOT_AUTO = 0, ///< Auto
+ LOW_POWER_PSTATE_FOR_PROCHOT_DISABLE = 1, ///< Disabled
+ MAX_LOW_POWER_PSTATE_FOR_PROCHOT_MODE = 2 ///< Not a valid value, used for verifying input
+} PLATFORM_LOW_POWER_PSTATE_MODES;
+
+/// Build Configuration values for BLDCFG_ACPI_PSTATES_PSD_POLICY
+#define PsdPolicyProcessorDefault 0 ///< PSD is dependent or independent per processor default
+#define PsdPolicyDependent 1 ///< PSD is forced dependent
+#define PsdPolicyIndependent 2 ///< PSD is forced independent
+#define PsdPolicyMax 3 ///< Not a valid value, used for verifying input
+
+/*----------------------------------------------------------------------------
+ * GNB PCIe configuration info
+ *----------------------------------------------------------------------------
+ */
+
+// Event definitions
+
+#define GNB_EVENT_INVALID_CONFIGURATION 0x20010000ul // User configuration invalid
+#define GNB_EVENT_INVALID_PCIE_TOPOLOGY_CONFIGURATION 0x20010001ul // Requested lane allocation for PCIe port can not be supported
+#define GNB_EVENT_INVALID_PCIE_PORT_CONFIGURATION 0x20010002ul // Requested incorrect PCIe port device address
+#define GNB_EVENT_INVALID_DDI_LINK_CONFIGURATION 0x20010003ul // Incorrect parameter in DDI link configuration
+#define GNB_EVENT_INVALID_LINK_WIDTH_CONFIGURATION 0x20010004ul // Invalid with for PCIe port or DDI link
+#define GNB_EVENT_INVALID_LANES_CONFIGURATION 0x20010005ul // Lane double subscribe lanes
+#define GNB_EVENT_INVALID_DDI_TOPOLOGY_CONFIGURATION 0x20010006ul // Requested lane allocation for DDI link(s) can not be supported
+#define GNB_EVENT_LINK_TRAINING_FAIL 0x20020000ul // PCIe Link training fail
+#define GNB_EVENT_BROKEN_LANE_RECOVERY 0x20030000ul // Broken lane workaround applied to recover link training
+#define GNB_EVENT_GEN2_SUPPORT_RECOVERY 0x20040000ul // Scale back to GEN1 to recover link training
+
+
+#define DESCRIPTOR_TERMINATE_LIST 0x80000000ull
+#define DESCRIPTOR_IGNORE 0x40000000ull
+
+/// PCIe link initialization
+typedef enum {
+ EndpointDetect = 0, ///< Detect endpoint presence
+ EndpointNotPresent ///< Endpoint not present (or connected). Used in case there is alternative way to determine
+ ///< if device present on board or in slot. For example GPIO can be used to determine device presence.
+} PCIE_ENDPOINT_STATUS;
+
+
+/// PCIe port misc extended controls
+typedef struct {
+ IN UINT8 LinkComplianceMode :1; ///< Force port into compliance mode (device will not be trained, port output compliance pattern)
+ IN UINT8 LinkSafeMode :2; /**< Safe mode PCIe capability. (Parameter may limit PCIe speed requested through PCIe_PORT_DATA::LinkSpeedCapability)
+ * @li @b 0 - port can advertize muximum supported capability
+ * @li @b 1 - port limit advertized capability and speed to PCIe Gen1
+ */
+ IN UINT8 SbLink :1; /**< PCIe link type
+ * @li @b 0 - General purpose port
+ * @li @b 1 - Port connected to SB
+ */
+ IN UINT8 ClkPmSupport :1; /**< Clock Power Management Support
+ * @li @b 0 - Clock Power Management not configured
+ * @li @b 1 - Clock Power Management configured according to PCIe device capability
+ */
+} PCIe_PORT_MISC_CONTROL;
+
+/// The IO APIC Interrupt Mapping Info
+typedef struct {
+ IN UINT8 GroupMap; /**< Group mapping for slot or endpoint device (connected to PCIE port) interrupts .
+ * @li <b>0</b> - IGNORE THIS STRUCTURE AND USE RECOMMENDED SETTINGS
+ * @li <b>1</b> - mapped to Grp 0 (Interrupts 0..3 of IO APIC redirection table)
+ * @li <b>2</b> - mapped to Grp 1 (Interrupts 4..7 of IO APIC redirection table)
+ * @li ...
+ * @li <b>8</b> - mapped to Grp 7 (Interrupts 28..31 of IO APIC redirection table)
+ */
+ IN UINT8 Swizzle; /**< Swizzle interrupt in the Group.
+ * @li <b>0</b> - ABCD
+ * @li <b>1</b> - BCDA
+ * @li <b>2</b> - CDAB
+ * @li <b>3</b> - DABC
+ */
+ IN UINT8 BridgeInt; /**< IOAPIC redirection table entry for PCIE bridge interrupt
+ * @li <b>0</b> - Entry 0 of IO APIC redirection table
+ * @li <b>1</b> - Entry 1 of IO APIC redirection table
+ * @li ...
+ * @li <b>31</b> - Entry 31 of IO APIC redirection table
+ */
+} APIC_DEVICE_INFO;
+
+/// Initial Offset Calibration Control
+typedef enum {
+ ADAPT_IOC_DISABLED = 0, ///< Initial Offset Calibration Disabled
+ ADAPT_IOC_ENABLED ///< Initial Offset Calibration Enabled
+} ADAPT_IOC_CONTROL;
+
+/// DFE Control values
+typedef enum {
+ ADAPT_DFE_CONTROL_DISABLED = 0, ///< DFE Disabled
+ ADAPD_DFE_CONTROL_1TAP_DFE = 4, ///< 1-tap DFE
+ ADAPD_DFE_CONTROL_1TAP_DFE_FBF, ///< 1-tap DFE with Future Bit Filtering
+ ADAPD_DFE_CONTROL_2TAP_DFE, ///< 2-tap DFE
+ ADAPD_DFE_CONTROL_2TAP_DFE_FBF ///< 2-tap DFE with Future Bit Filtering
+} ADAPT_DFE_CONTROL;
+
+/// LEQ Control values
+typedef enum {
+ ADAPT_LEQ_CONTROL_DISABLED = 0, ///< LEQ Disabled
+ ADAPT_LEQ_CONTROL_DC_GAIN = 2, ///< DC Gain Adaptation
+ ADAPT_LEQ_CONTROL_DC_GAIN_POLE ///< DC Gain and Pole Adaptation
+} ADAPT_LEQ_CONTROL;
+
+/// Dynamic Offset Calibration Control
+typedef enum {
+ ADAPT_DOC_DISABLED = 0, ///< Dynamic Offset Calibration Disabled
+ ADAPT_DOC_ENABLED ///< Dynamic Offset Calibration Enabled
+} ADAPT_DOC_CONTROL;
+
+/// FOM Calculation Control
+typedef enum {
+ ADAPT_FOMC_DISABLED = 0, ///< FOM Calculation Disabled
+ ADAPT_FOMC_ENABLED ///< FOM Calculation Enabled
+} ADAPT_FOMC_CONTROL;
+
+/// PI Offset Calibration Control
+typedef enum {
+ ADAPT_PIOC_DISABLED = 0, ///< PI Offset Calibration Disabled
+ ADAPT_PIOC_ENABLED ///< PI Offset Calibration Enabled
+} ADAPT_PIOC_CONTROL;
+
+/// GEN3 RxAdaptMode Configuration Structure
+typedef struct {
+ IN BOOLEAN InitOffsetCancellation; ///< Initial Offset Cancellation Enable
+ IN UINT8 DFEControl; ///< DFE Control
+ IN UINT8 LEQControl; ///< LEQ Control
+ IN BOOLEAN DynamicOffsetCalibration; ///< Dynamic Offset Calibration Enable
+ IN BOOLEAN FOMCalculation; ///< FOM Calculation Enable
+ IN BOOLEAN PIOffsetCalibration; ///< PI Offset Calibratino Enable
+} RX_ADAPT_MODE;
+
+/// PCIe port configuration data
+typedef struct {
+ IN UINT8 PortPresent; ///< Enable PCIe port for initialization.
+ IN UINT8 ChannelType; /**< Channel type.
+ * @li @b 0 - "lowLoss",
+ * @li @b 1 - "highLoss",
+ * @li @b 2 - "mob0db",
+ * @li @b 3 - "mob3db",
+ * @li @b 4 - "extnd6db"
+ * @li @b 5 - "extnd8db"
+ */
+ IN UINT8 DeviceNumber; /**< PCI Device number for port.
+ * @li @b 0 - Native port device number
+ * @li @b N - Port device number (See available configurations in BKDG
+ */
+ IN UINT8 FunctionNumber; ///< Reserved for future use
+ IN UINT8 LinkSpeedCapability; /**< PCIe link speed/
+ * @li @b 0 - Maximum supported by silicon
+ * @li @b 1 - Gen1
+ * @li @b 2 - Gen2
+ * @li @b 3 - Gen3
+ */
+ IN UINT8 LinkAspm; /**< ASPM control. (see AgesaPcieLinkAspm for additional option to control ASPM)
+ * @li @b 0 - Disabled
+ * @li @b 1 - L0s only
+ * @li @b 2 - L1 only
+ * @li @b 3 - L0s and L1
+ */
+ IN UINT8 LinkHotplug; /**< Hotplug control.
+ * @li @b 0 - Disabled
+ * @li @b 1 - Basic
+ * @li @b 2 - Server
+ * @li @b 3 - Enhanced
+ */
+ IN UINT8 ResetId; /**< Arbitrary number greater than 0 assigned by platform firmware for GPIO
+ * identification which control reset for given port.
+ * Each port with unique GPIO should have unique ResetId assigned.
+ * All ports use same GPIO to control reset should have same ResetId assigned.
+ * see AgesaPcieSlotResetContol.
+ */
+ IN PCIe_PORT_MISC_CONTROL MiscControls; ///< Misc extended controls
+ IN APIC_DEVICE_INFO ApicDeviceInfo; ///< IOAPIC device programming info
+ IN PCIE_ENDPOINT_STATUS EndpointStatus; ///< PCIe endpoint (device connected to PCIe port) status
+ IN RX_ADAPT_MODE RxAdaptMode; ///< Gen3 RxAdaptMode configuration
+} PCIe_PORT_DATA;
+
+/// DDI channel lane mapping
+typedef struct { ///< Structure that discribe lane mapping
+ IN UINT8 Lane0 :2; /**< Lane 0 mapping
+ * @li @b 0 - Map to lane 0
+ * @li @b 1 - Map to lane 1
+ * @li @b 2 - Map to lane 2
+ * @li @b 3 - Map to lane 3
+ */
+ IN UINT8 Lane1 :2; ///< Lane 1 mapping (see "Lane 0 mapping")
+ IN UINT8 Lane2 :2; ///< Lane 2 mapping (see "Lane 0 mapping")
+ IN UINT8 Lane3 :2; ///< Lane 3 mapping (see "Lane 0 mapping")
+} CHANNEL_MAPPING; ///< Lane mapping
+
+/// Common Channel Mapping
+typedef union {
+ IN UINT8 ChannelMappingValue; ///< Raw lane mapping
+ IN CHANNEL_MAPPING ChannelMapping; ///< Channel mapping
+} CONN_CHANNEL_MAPPING;
+
+/// DDI Configuration data
+typedef struct {
+ IN UINT8 ConnectorType; /**< Display Connector Type
+ * @li @b 0 - DP
+ * @li @b 1 - eDP
+ * @li @b 2 - Single Link DVI-D
+ * @li @b 3 - Dual Link DVI-D (see @ref DualLinkDviDescription "Example Dual Link DVI connector description")
+ * @li @b 4 - HDMI
+ * @li @b 5 - DP-to-VGA
+ * @li @b 6 - DP-to-LVDS
+ * @li @b 7 - Hudson-2 NutMeg DP-to-VGA
+ * @li @b 8 - Single Link DVI-I
+ * @li @b 9 - Native CRT (Family 0x14)
+ * @li @b 10 - Native LVDS (Family 0x14)
+ * @li @b 11 - Auto detect LCD panel connector type. VBIOS is able to auto detect the LVDS connector type: native LVDS, eDP or DP-to-LVDS
+ * The auto detection method only support panel with EDID.
+ */
+ IN UINT8 AuxIndex; /**< Indicates which AUX or DDC Line is used
+ * @li @b 0 - AUX1
+ * @li @b 1 - AUX2
+ * @li @b 2 - AUX3
+ * @li @b 3 - AUX4
+ * @li @b 4 - AUX5
+ * @li @b 5 - AUX6
+ */
+ IN UINT8 HdpIndex; /**< Indicates which HDP pin is used
+ * @li @b 0 - HDP1
+ * @li @b 1 - HDP2
+ * @li @b 2 - HDP3
+ * @li @b 3 - HDP4
+ * @li @b 4 - HDP5
+ * @li @b 5 - HDP6
+ */
+ IN CONN_CHANNEL_MAPPING Mapping[2]; /**< Set specific mapping of lanes to connector pins
+ * @li Mapping[0] define mapping for group of 4 lanes starting at PCIe_ENGINE_DATA.StartLane
+ * @li Mapping[1] define mapping for group of 4 lanes ending at PCIe_ENGINE_DATA.EndLane (only applicable for Dual DDI link)
+ * if Mapping[x] set to 0 than default mapping assumed
+ */
+ IN UINT8 LanePnInversionMask; /**< Specifies whether to invert the state of P and N for each lane. Each bit represents a PCIe lane on the DDI port.
+ * @li 0 - Do not invert (default)
+ * @li 1 - Invert P and N on this lane
+ */
+ IN UINT8 Flags; /**< Capabilities flags
+ * @li Flags bit[0] DDI_DATA_FLAGS_DP1_1_ONLY Selects downgrade PHY link to DP1.1
+ * @li Flags bit[7:1] Reserved
+ */
+} PCIe_DDI_DATA;
+
+/// Engine Configuration
+typedef struct {
+ IN UINT8 EngineType; /**< Engine type
+ * @li @b 0 - Ignore engine configuration
+ * @li @b 1 - PCIe port
+ * @li @b 2 - DDI
+ */
+ IN UINT16 StartLane; /**< Start Lane ID (in reversed configuration StartLane > EndLane)
+ * Refer to lane descriptions and supported configurations in BKDG
+ */
+ IN UINT16 EndLane; /**< End lane ID (in reversed configuration StartLane > EndLane)
+ * Refer to lane descriptions and supported configurations in BKDG
+ */
+
+} PCIe_ENGINE_DATA;
+
+/// PCIe port descriptor
+typedef struct {
+ IN UINT32 Flags; /**< Descriptor flags
+ * @li @b Bit31 - last descriptor in complex
+ */
+ IN PCIe_ENGINE_DATA EngineData; ///< Engine data
+ IN PCIe_PORT_DATA Port; ///< PCIe port specific configuration info
+} PCIe_PORT_DESCRIPTOR;
+
+/// DDI descriptor
+typedef struct {
+ IN UINT32 Flags; /**< Descriptor flags
+ * @li @b Bit31 - last descriptor in complex
+ */
+ IN PCIe_ENGINE_DATA EngineData; ///< Engine data
+ IN PCIe_DDI_DATA Ddi; ///< DDI port specific configuration info
+} PCIe_DDI_DESCRIPTOR;
+
+/// PCIe Complex descriptor
+typedef struct {
+ IN UINT32 Flags; /**< Descriptor flags
+ * @li @b Bit31 - last descriptor in topology
+ */
+ IN UINT32 SocketId; ///< Socket Id
+ IN const PCIe_PORT_DESCRIPTOR *PciePortList; ///< Pointer to array of PCIe port descriptors or NULL (Last element of array must be terminated with DESCRIPTOR_TERMINATE_LIST).
+ IN const PCIe_DDI_DESCRIPTOR *DdiLinkList; ///< Pointer to array DDI link descriptors (Last element of array must be terminated with DESCRIPTOR_TERMINATE_LIST).
+ IN VOID *Reserved; ///< Reserved for future use
+} PCIe_COMPLEX_DESCRIPTOR;
+
+/// Action to control PCIe slot reset
+typedef enum {
+ AssertSlotReset, ///< Assert slot reset
+ DeassertSlotReset ///< Deassert slot reset
+} PCIE_RESET_CONTROL;
+
+///Slot Reset Info
+typedef struct {
+ IN AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header
+ IN UINT8 ResetId; ///< Slot reset ID as specified in PCIe_PORT_DESCRIPTOR
+ IN UINT8 ResetControl; ///< Reset control as in PCIE_RESET_CONTROL
+} PCIe_SLOT_RESET_INFO;
+
+#define GFX_VBIOS_IMAGE_FLAG_SPECIAL_POST 0x1
+
+///VBIOS image info
+typedef struct {
+ IN AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header
+ OUT VOID *ImagePtr; ///< Pointer to VBIOS image
+ IN PCI_ADDR GfxPciAddress; ///< PCI address of integrated graphics controller
+ IN UINT32 Flags; ///< BIT[0] - special repost requred
+} GFX_VBIOS_IMAGE_INFO;
+
+/// Engine descriptor type
+typedef enum {
+ PcieUnusedEngine = 0, ///< Unused descriptor
+ PciePortEngine = 1, ///< PCIe port
+ PcieDdiEngine = 2, ///< DDI
+ MaxPcieEngine ///< Max engine type for boundary check.
+} PCIE_ENGINE_TYPE;
+
+/// PCIe link capability/speed
+typedef enum {
+ PcieGenMaxSupported, ///< Maximum supported
+ PcieGen1 = 1, ///< Gen1
+ PcieGen2, ///< Gen2
+ PcieGen3, ///< Gen3
+ MaxPcieGen ///< Max Gen for boundary check
+} PCIE_LINK_SPEED_CAP;
+
+/// PCIe PSPP Power policy
+typedef enum {
+ PsppDisabled, ///< PSPP disabled
+ PsppPerformance = 1, ///< Performance
+ PsppBalanceHigh, ///< Balance-High
+ PsppBalanceLow, ///< Balance-Low
+ PsppPowerSaving, ///< Power Saving
+ MaxPspp ///< Max Pspp for boundary check
+} PCIE_PSPP_POLICY;
+
+/// DDI display connector type
+typedef enum {
+ ConnectorTypeDP, ///< DP
+ ConnectorTypeEDP, ///< eDP
+ ConnectorTypeSingleLinkDVI, ///< Single Link DVI-D
+ ConnectorTypeDualLinkDVI, ///< Dual Link DVI-D
+ ConnectorTypeHDMI, ///< HDMI
+ ConnectorTypeDpToVga, ///< DP-to-VGA
+ ConnectorTypeDpToLvds, ///< DP-to-LVDS
+ ConnectorTypeNutmegDpToVga, ///< Hudson-2 NutMeg DP-to-VGA
+ ConnectorTypeSingleLinkDviI, ///< Single Link DVI-I
+ ConnectorTypeCrt, ///< CRT (VGA)
+ ConnectorTypeLvds, ///< LVDS
+ ConnectorTypeEDPToLvds, ///< 3rd party common eDP-to-LVDS translator chip without AMD SW init
+ ConnectorTypeEDPToLvdsSwInit, ///< 3rd party eDP-to-LVDS translator which requires AMD SW init
+ ConnectorTypeAutoDetect, ///< VBIOS auto detect connector type (native LVDS, eDP or DP-to-LVDS)
+ MaxConnectorType ///< Not valid value, used to verify input
+} PCIE_CONNECTOR_TYPE;
+
+/// PCIe link channel type
+typedef enum {
+ ChannelTypeLowLoss, ///< Low Loss
+ ChannelTypeHighLoss, ///< High Loss
+ ChannelTypeMob0db, ///< Mobile 0dB
+ ChannelTypeMob3db, ///< Mobile 3dB
+ ChannelTypeExt6db, ///< Extended 6dB
+ ChannelTypeExt8db, ///< Extended 8dB
+ MaxChannelType ///< Not valid value, used to verify input
+} PCIE_CHANNEL_TYPE;
+
+/// PCIe link ASPM
+typedef enum {
+ AspmDisabled, ///< Disabled
+ AspmL0s, ///< PCIe L0s link state
+ AspmL1, ///< PCIe L1 link state
+ AspmL0sL1, ///< PCIe L0s & L1 link state
+ MaxAspm ///< Not valid value, used to verify input
+} PCIE_ASPM_TYPE;
+
+/// PCIe link hotplug support
+typedef enum {
+ HotplugDisabled, ///< Hotplug disable
+ HotplugBasic, ///< Basic Hotplug
+ HotplugServer, ///< Server Hotplug
+ HotplugEnhanced, ///< Enhanced
+ HotplugInboard, ///< Inboard
+ MaxHotplug ///< Not valid value, used to verify input
+} PCIE_HOTPLUG_TYPE;
+
+/// PCIe link initialization
+typedef enum {
+ PortDisabled, ///< Disable
+ PortEnabled ///< Enable
+} PCIE_PORT_ENABLE;
+
+/// PCIe ACS capability - Access Control Services
+typedef enum {
+ PcieAcsDisabled, ///< Disabled
+ PcieAcsEnabled, ///< Enabled
+} PCIE_ACS_CAP;
+
+/// PCIe ClkPmSupport initialization
+typedef enum {
+ ClkPmSupportDisabled, ///< Disable
+ ClkPmSupportEnabled ///< Enable
+} CLKPM_SUPPORT_ENABLE;
+
+/// DDI Aux channel
+typedef enum {
+ Aux1, ///< Aux1
+ Aux2, ///< Aux2
+ Aux3, ///< Aux3
+ Aux4, ///< Aux4
+ Aux5, ///< Aux5
+ Aux6, ///< Aux6
+ MaxAux ///< Not valid value, used to verify input
+} PCIE_AUX_TYPE;
+
+/// DDI Hdp Index
+typedef enum {
+ Hdp1, ///< Hdp1
+ Hdp2, ///< Hdp2
+ Hdp3, ///< Hdp3
+ Hdp4, ///< Hdp4
+ Hdp5, ///< Hdp5
+ Hdp6, ///< Hdp6
+ MaxHdp ///< Not valid value, used to verify input
+} PCIE_HDP_TYPE;
+
+/// PCIe_DDI_DATA.Flags definitions
+#define DDI_DATA_FLAGS_DP1_1_ONLY 0x01 ///< BIT[0] Selects downgrade PHY link to DP1.1
+#define EXT_DISPLAY_PATH_CAPS_DP_FIXED_VS_EN 0x02 ///< BIT[1] VBIOS will always output fixed voltage swing during DP link training
+/// DP receiver definitions with fixed voltage swing
+typedef enum {
+ DP_VS_0_4V_0DB, ///< 0x00
+ DP_VS_0_6V_0DB, ///< 0x01
+ DP_VS_0_8V_0DB, ///< 0x02
+ DP_VS_1_2V_0DB, ///< 0x03
+ DP_VS_0_4V_3_5DB = 0x8, ///< 0x08
+ DP_VS_0_6V_3_5DB, ///< 0x09
+ DP_VS_0_8V_3_5DB, ///< 0x0a
+ DP_VS_0_4V_6DB = 0x10, ///< 0x10
+ DP_VS_0_6V_6DB, ///< 0x11
+ DP_VS_0_4V_9_5DB = 0x18 ///< 0x18
+} DP_FIXED_VOLT_SWING_TYPE;
+
+// Macro for statically initializing various structures
+#define PCIE_ENGINE_DATA_INITIALIZER(mType, mStartLane, mEndLane) {mType, mStartLane, mEndLane}
+#define PCIE_PORT_DATA_INITIALIZER(mPortPresent, mChannelType, mDevAddress, mHotplug, mMaxLinkSpeed, mMaxLinkCap, mAspm, mResetId) \
+{mPortPresent, mChannelType, mDevAddress, 0, mMaxLinkSpeed, mAspm, mHotplug, mResetId, {0, mMaxLinkCap, 0, 0}, {0, 0, 0}, EndpointDetect, \
+{ADAPT_IOC_ENABLED, ADAPT_DFE_CONTROL_DISABLED, ADAPT_LEQ_CONTROL_DC_GAIN_POLE, ADAPT_DOC_DISABLED, ADAPT_FOMC_ENABLED, ADAPT_PIOC_DISABLED}}
+#define PCIE_PORT_DATA_INITIALIZER_V2(mPortPresent, mChannelType, mDevAddress, mDevFunction, mHotplug, mMaxLinkSpeed, mMaxLinkCap, mAspm, mResetId, mClkPmSupport) \
+{mPortPresent, mChannelType, mDevAddress, mDevFunction, mMaxLinkSpeed, mAspm, mHotplug, mResetId, {0, mMaxLinkCap, 0, mClkPmSupport}, {0, 0, 0}, EndpointDetect, \
+{ADAPT_IOC_ENABLED, ADAPT_DFE_CONTROL_DISABLED, ADAPT_LEQ_CONTROL_DC_GAIN_POLE, ADAPT_DOC_DISABLED, ADAPT_FOMC_ENABLED, ADAPT_PIOC_DISABLED}}
+#define PCIE_PORT_DATA_INITIALIZER_GEN3(mPortPresent, mChannelType, mDevAddress, mDevFunction, mHotplug, mMaxLinkSpeed, mMaxLinkCap, mAspm, mResetId, mClkPmSupport, \
+mInitOffsetCancellation, mDFEControl, mLEQControl, mDynamicOffsetCalibration, mFOMCalculation, mPIOffsetCalibration) \
+{mPortPresent, mChannelType, mDevAddress, mDevFunction, mMaxLinkSpeed, mAspm, mHotplug, mResetId, {0, mMaxLinkCap, 0, mClkPmSupport}, {0, 0, 0}, EndpointDetect, \
+{mInitOffsetCancellation, mDFEControl, mLEQControl, mDynamicOffsetCalibration, mFOMCalculation, mPIOffsetCalibration}}
+#define PCIE_DDI_DATA_INITIALIZER(mConnectorType, mAuxIndex, mHpdIndex ) \
+{mConnectorType, mAuxIndex, mHpdIndex, {{0}, {0}}, 0, 0}
+#define PCIE_DDI_DATA_INITIALIZER_V1(mConnectorType, mAuxIndex, mHpdIndex, mMapping0, mMapping1, mPNInversion) \
+{mConnectorType, mAuxIndex, mHpdIndex, {mMapping0, mMapping1}, mPNInversion, 0}
+#define PCIE_DDI_DATA_INITIALIZER_V2(mConnectorType, mAuxIndex, mHpdIndex, mMapping0, mMapping1, mPNInversion, mFlags) \
+{mConnectorType, mAuxIndex, mHpdIndex, {mMapping0, mMapping1}, mPNInversion, mFlags}
+
+///IOMMU requestor ID
+typedef struct {
+ IN UINT16 Bus :8; ///< Bus
+ IN UINT16 Device :5; ///< Device
+ IN UINT16 Function :3; ///< Function
+} IOMMU_REQUESTOR_ID;
+
+/// IVMD exclusion range descriptor
+typedef struct {
+ IN UINT32 Flags; /**< Descriptor flags
+ * @li @b Flags[31] - Terminate descriptor array.
+ * @li @b Flags[30] - Ignore descriptor.
+ */
+ IN IOMMU_REQUESTOR_ID RequestorIdStart; ///< Requestor ID start
+ IN IOMMU_REQUESTOR_ID RequestorIdEnd; ///< Requestor ID end (use same as start for single ID)
+ IN UINT64 RangeBaseAddress; ///< Phisical base address of exclusion range
+ IN UINT64 RangeLength; ///< Length of exclusion range in bytes
+} IOMMU_EXCLUSION_RANGE_DESCRIPTOR;
+
+/*----------------------------------------------------------------------------
+ * GNB configuration info
+ *----------------------------------------------------------------------------
+ */
+
+/// LVDS Misc Control Field
+typedef struct {
+ IN UINT8 FpdiMode:1; ///< This item configures LVDS 888bit panel mode
+ ///< @li FALSE = LVDS 888 panel in LDI mode
+ ///< @li TRUE = LVDS 888 panel in FPDI mode
+ ///< @BldCfgItem{BLDCFG_LVDS_MISC_888_FPDI_MODE}
+ IN UINT8 DlChSwap:1; ///< This item configures LVDS panel lower and upper link mapping
+ ///< @li FALSE = Lower link and upper link not swap
+ ///< @li TRUE = Lower link and upper link are swapped
+ ///< @BldCfgItem{BLDCFG_LVDS_MISC_DL_CH_SWAP}
+ IN UINT8 VsyncActiveLow:1; ///< This item configures polarity of frame pulse encoded in lvds data stream
+ ///< @li FALSE = Active high Frame Pulse/Vsync
+ ///< @li TRUE = Active low Frame Pulse/Vsync
+ ///< @BldCfgItem{BLDCFG_LVDS_MISC_VSYNC_ACTIVE_LOW}
+ IN UINT8 HsyncActiveLow:1; ///< This item configures polarity of line pulse encoded in lvds data
+ ///< @li FALSE = Active high Line Pulse
+ ///< @li TRUE = Active low Line Pulse / Hsync
+ ///< @BldCfgItem{BLDCFG_LVDS_MISC_HSYNC_ACTIVE_LOW}
+ IN UINT8 BLONActiveLow:1; ///< This item configures polarity of signal sent to digital BLON output pin
+ ///< @li FALSE = Not inverted(active high)
+ ///< @li TRUE = Inverted (active low)
+ ///< @BldCfgItem{BLDCFG_LVDS_MISC_BLON_ACTIVE_LOW}
+ IN UINT8 LvdsVoltOverwriteEn:1; ///< This item configures polarity of DP-to-LVDS output voltage overwrite
+ ///< @li FALSE = DP-to-LVDS output voltage overwrite disable, use VBIOS default setting.
+ ///< @li TRUE = Use ucLVDSVolAdjust value to program register LVDS_CTRL_4
+ ///< @BldCfgItem{BLDCFG_LVDS_MISC_VOLT_OVERWRITE_ENABLE}
+ IN UINT8 Reserved:2; ///< Reserved
+} LVDS_MISC_CONTROL_FIELD;
+
+/// LVDS Misc Control
+typedef union _LVDS_MISC_CONTROL {
+ IN LVDS_MISC_CONTROL_FIELD Field; ///< LVDS_MISC_CONTROL_FIELD
+ IN UINT8 Value; ///< LVDS Misc Control Value
+} LVDS_MISC_CONTROL;
+
+/// Display Misc Control Field
+typedef struct {
+ IN UINT8 Reserved1:3; ///< Reserved
+ IN UINT8 VbiosFastBootEn:1; ///< This item configures VBIOS skip display device detection in every set mode if LCD panel is connect and LID is open.
+ ///< @li FALSE = VBIOS fast boot is disable.
+ ///< @li TRUE = VBIOS fast boot is enable.
+ ///< @BldCfgItem{BLDCFG_DISPLAY_MISC_VBIOS_FAST_BOOT_ENABLE}
+ IN UINT8 Reserved2:4; ///< Reserved
+} DISPLAY_MISC_CONTROL_FIELD;
+
+/// LVDS Misc Control
+typedef union _DISPLAY_MISC_CONTROL {
+ IN DISPLAY_MISC_CONTROL_FIELD Field; ///< DISPLAY_MISC_CONTROL_FIELD
+ IN UINT8 Value; ///< Display Misc Control Value
+} DISPLAY_MISC_CONTROL;
+
+/// POST Configuration settings for GNB.
+typedef struct {
+ IN UINT8 IgpuEnableDisablePolicy; ///< This item defines the iGPU Enable/Disable policy
+ ///< @li 0 = Auto - use existing default -
+ ///< @li 1 = Disable iGPU if any PCIe/PCI graphics card present
+ ///< @BldCfgItem{BLDCFG_IGPU_ENABLE_DISABLE_POLICY}
+} GNB_POST_CONFIGURATION;
+
+/// iGPU Enable/Disable Policy values
+#define IGPU_DISABLE_AUTO 0 ///< Auto setting - disable iGPU if ANY PCI graphics or non-AMD PCIe graphics
+#define IGPU_DISABLE_ANY_PCIE 1 ///< Disable iGPU if any PCI or PCIE graphics card is present
+
+/// ENV Configuration settings for GNB.
+typedef struct {
+ IN UINT8 Gnb3dStereoPinIndex; ///< 3D Stereo Pin ID.
+ ///< @li 0 = Stereo 3D is disabled (default).
+ ///< @li 1 = Use processor pin HPD1.
+ ///< @li 2 = Use processor pin HPD2
+ ///< @li 3 = Use processor pin HPD3
+ ///< @li 4 = Use processor pin HPD4
+ ///< @li 5 = Use processor pin HPD5
+ ///< @li 6 = Use processor pin HPD6
+ ///< @BldCfgItem{BLDCFG_STEREO_3D_PINOUT}
+ IN BOOLEAN IommuSupport; ///< IOMMU support.
+ ///< @li FALSE = Disabled. Disable and hide IOMMU device.
+ ///< @li TRUE = Initialize IOMMU subsystem. Generate ACPI IVRS table.
+ ///< BldCfgItem{BLDCFG_IOMMU_SUPPORT}
+ IN UINT16 LvdsSpreadSpectrum; ///< Spread spectrum value in 0.01 %
+ ///< BldCfgItem{BLDCFG_GFX_LVDS_SPREAD_SPECTRUM}
+ IN UINT16 LvdsSpreadSpectrumRate; ///< Spread spectrum frequency used by SS hardware logic in unit of 10Hz, 0 - default frequency 40kHz
+ ///< BldCfgItem{BLDCFG_GFX_LVDS_SPREAD_SPECTRUM_RATE}
+ IN UINT8 LvdsPowerOnSeqDigonToDe; ///< This item configures panel initialization timing.
+ ///< @BldCfgItem{BLDCFG_LVDS_POWER_ON_SEQ_DIGON_TO_DE}
+ IN UINT8 LvdsPowerOnSeqDeToVaryBl; ///< This item configures panel initialization timing.
+ ///< @BldCfgItem{BLDCFG_LVDS_POWER_ON_SEQ_DE_TO_VARY_BL}
+ IN UINT8 LvdsPowerOnSeqDeToDigon; ///< This item configures panel initialization timing.
+ ///< @BldCfgItem{BLDCFG_LVDS_POWER_ON_SEQ_DE_TO_DIGON}
+ IN UINT8 LvdsPowerOnSeqVaryBlToDe; ///< This item configures panel initialization timing.
+ ///< @BldCfgItem{BLDCFG_LVDS_POWERS_ON_SEQ_VARY_BL_TO_DE}
+ IN UINT8 LvdsPowerOnSeqOnToOffDelay; ///< This item configures panel initialization timing.
+ ///< @BldCfgItem{BLDCFG_LVDS_POWER_ON_SEQ_ON_TO_OFF_DELAY}
+ IN UINT8 LvdsPowerOnSeqVaryBlToBlon; ///< This item configures panel initialization timing.
+ ///< @BldCfgItem{BLDCFG_LVDS_POWER_ON_SEQ_VARY_BL_TO_BLON}
+ IN UINT8 LvdsPowerOnSeqBlonToVaryBl; ///< This item configures panel initialization timing.
+ ///< @BldCfgItem{BLDCFG_LVDS_POWER_ON_SEQ_BLON_TO_VARY_BL}
+ IN UINT16 LvdsMaxPixelClockFreq; ///< This item configures the maximum pixel clock frequency supported.
+ ///< @BldCfgItem{BLDCFG_LVDS_MAX_PIXEL_CLOCK_FREQ}
+ IN UINT32 LcdBitDepthControlValue; ///< This item configures the LCD bit depth control settings.
+ ///< @BldCfgItem{BLDCFG_LCD_BIT_DEPTH_CONTROL_VALUE}
+ IN UINT8 Lvds24bbpPanelMode; ///< This item configures the LVDS 24 BBP mode.
+ ///< @BldCfgItem{BLDCFG_LVDS_24BBP_PANEL_MODE}
+ IN LVDS_MISC_CONTROL LvdsMiscControl;///< This item configures LVDS swap/Hsync/Vsync/BLON
+ IN UINT16 PcieRefClkSpreadSpectrum; ///< Spread spectrum value in 0.01 %
+ ///< @BldCfgItem{BLDCFG_PCIE_REFCLK_SPREAD_SPECTRUM}
+ IN BOOLEAN GnbRemoteDisplaySupport; ///< This item enables Wireless Display Support
+ ///< @li TRUE = Enable Wireless Display Support
+ ///< @li FALSE = Disable Wireless Display Support
+ ///< @BldCfgItem{BLDCFG_REMOTE_DISPLAY_SUPPORT}
+ IN UINT8 LvdsMiscVoltAdjustment; ///< Register LVDS_CTRL_4 to adjust LVDS output voltage
+ ///< @BldCfgItem{BLDCFG_LVDS_MISC_VOL_ADJUSTMENT}
+ IN DISPLAY_MISC_CONTROL DisplayMiscControl;///< This item configures display misc control
+ IN DP_FIXED_VOLT_SWING_TYPE DpFixedVoltSwingType;///< To indicate fixed voltage swing value
+ ///< @BldCfgItem{BLDCFG_DP_FIXED_VOLT_SWING}
+ IN UINT32 GpuFrequencyLimit; ///< GNB GPU Max Frequency(NULL if platform configured)
+ ///< @BldCfgItem{BLDCFG_GPU_FREQUENCY_LIMIT}
+} GNB_ENV_CONFIGURATION;
+
+/// Configuration settings for GNB.
+typedef struct {
+ IN UINT8 iGpuVgaMode; ///< VGA resources decoding configuration for iGPU
+ ///< @li 0 = iGPU decode all VGA resources (must be primary VGA adapter)
+ ///< @li 1 = iGPU will not decode any VGA resources (must be secondary graphics adapter)
+ IN UINT8 PcieAcsCapability; ///< Pcie ACS Capability support
+ ///< @li 0 = Disabled
+ ///< @li 1 = Enabled
+ IN UINT64 GnbIoapicAddress; ///< GNB IOAPIC Base Address(NULL if platform configured)
+ ///< @BldCfgItem{BLDCFG_GNB_IOAPIC_ADDRESS}
+ IN UINT8 MaxNumAudioEndpoints; ///< Max number of audio endpoints
+ ///< @BldCfgItem{BLDCFG_MAX_NUM_AUDIO_ENDPOINTS}
+} GNB_MID_CONFIGURATION;
+
+/// GNB configuration info
+typedef struct {
+ IN const PCIe_COMPLEX_DESCRIPTOR *PcieComplexList; /**< Pointer to array of structures describe PCIe topology on each processor package or NULL.
+ * Last element of array must be terminated with DESCRIPTOR_TERMINATE_LIST
+ * Example of topology definition for single socket system:
+ * @code
+ * PCIe_PORT_DESCRIPTOR PortList [] = {
+ * // Initialize Port descriptor (PCIe port, Lanes 8:15, PCI Device Number 2, ...)
+ * {
+ * 0, //Descriptor flags
+ * PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 8, 15),
+ * PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 2, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0)
+ * },
+ * // Initialize Port descriptor (PCIe port, Lanes 16:19, PCI Device Number 3, ...)
+ * {
+ * 0, //Descriptor flags
+ * PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 16, 19),
+ * PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 3, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0)
+ * },
+ * // Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...)
+ * {
+ * DESCRIPTOR_TERMINATE_LIST, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array
+ * PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 4),
+ * PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 4, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0)
+ * }
+ * };
+ * PCIe_PORT_DESCRIPTOR DdiList [] = {
+ * // Initialize Ddi descriptor (DDI interface Lanes 24:27, Display Port Connector, ...)
+ * {
+ * 0, //Descriptor flags
+ * PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 24, 27),
+ * PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux1, Hdp1, 0)
+ * },
+ * // Initialize Ddi descriptor (DDI interface Lanes 28:31, HDMI, ...)
+ * {
+ * DESCRIPTOR_TERMINATE_LIST, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array
+ * PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 28, 31),
+ * PCIE_DDI_DATA_INITIALIZER (ConnectorTypeHDMI, Aux2, Hdp2, 0)
+ * }
+ * };
+ * PCIe_COMPLEX_DESCRIPTOR PlatformTopology = {
+ * DESCRIPTOR_TERMINATE_LIST, //Descriptor flags !!!IMPORTANT!!! Terminate complexes list
+ * 0, //Socket ID
+ * &PortList[0],
+ * &DdiList[0],
+ * }
+ * @endcode
+ */
+ IN UINT8 PsppPolicy; /**< PSPP (PCIe Speed Power Policy)
+ * @li @b 0 - Disabled
+ * @li @b 1 - Performance
+ * @li @b 2 - Balance-High
+ * @li @b 3 - Balance-Low
+ * @li @b 4 - Power Saving
+ */
+
+} GNB_CONFIGURATION;
+
+/// Late Configuration settings for GNB.
+typedef struct {
+ IN BOOLEAN DockedTdpHeadroom; ///< Docked TDP headroom
+ ///< @li TRUE = Enable docked TDP headroom
+ ///< @li FALSE = Disable docked TDP headroom
+ ///< @BldCfgItem{BLDCFG_DOCKED_TDP_HEADROOM}
+ IN UINT8 GnbIoapicId; ///< GNB IOAPIC ID, platform BIOS needs to pass correct id number, default is 0xFF.
+ ///< If BLDCFG_GNB_IOAPIC_ADDRESS == NULL or BLDCFG_IOMMU_SUPPORT == NULL or GnbIoapicId == default(0xFF), AGESA will skip it anyway.
+ ///< @li 0~n = IOAPIC ID number for IVRS which should be matched with MADT
+ IN UINT8 FchIoapicId; ///< Fch IOAPIC ID, platform BIOS needs to pass correct id number, default is 0xFF.
+ ///< If BLDCFG_IOMMU_SUPPORT == NULL or or FchIoapicId == default(0xFF), AGESA will skip it anyway.
+ ///< @li 0~n = IOAPIC ID number for IVRS which should be matched with MADT
+
+} GNB_LATE_CONFIGURATION;
+
+//
+// MEMORY-SPECIFIC DATA STRUCTURES
+//
+//
+//
+//
+// AGESA MAXIMIUM VALUES
+//
+// These Max values are used to define array sizes and associated loop
+// counts in the code. They reflect the maximum values that AGESA
+// currently supports and does not necessarily reflect the hardware
+// capabilities of configuration.
+//
+
+#define MAX_SOCKETS_SUPPORTED 1 ///< Max number of sockets in system
+#define MAX_CHANNELS_PER_SOCKET 4 ///< Max Channels per sockets
+#define MAX_DIMMS_PER_CHANNEL 4 ///< Max DIMMs on a memory channel (independent of platform)
+#define NUMBER_OF_DELAY_TABLES 9 ///< Number of tables defined in CH_DEF_STRUCT.
+ ///< Eg: UINT16 *RcvEnDlys;
+ ///< UINT8 *WrDqsDlys;
+ ///< UINT8 *RdDqsDlys;
+ ///< UINT8 *WrDatDlys;
+ ///< UINT8 *RdDqsMinDlys;
+ ///< UINT8 *RdDqsMaxDlys;
+ ///< UINT8 *WrDatMinDlys;
+ ///< UINT8 *WrDatMaxDlys;
+#define NUMBER_OF_FAILURE_MASK_TABLES 1 ///< Number of failure mask tables
+
+#define MAX_PLATFORM_TYPES 16 ///< Platform types per system
+
+#define MCT_TRNG_KEEPOUT_START 0x00004000ul ///< base [39:8]
+#define MCT_TRNG_KEEPOUT_END 0x00007FFFul ///< base [39:8]
+#define DATAEYE_VREF_RANGE 31 ///< Number of VREF steps in Data Eye Bitmap
+
+#define UMA_ATTRIBUTE_INTERLEAVE 0x80000000ul ///< Uma Region is interleaved
+#define UMA_ATTRIBUTE_ON_DCT0 0x40000000ul ///< UMA resides on memory that belongs to DCT0
+#define UMA_ATTRIBUTE_ON_DCT1 0x20000000ul ///< UMA resides on memory that belongs to DCT1
+#define UMA_ATTRIBUTE_ON_DCT2 0x10000000ul ///< UMA resides on memory that belongs to DCT2
+#define UMA_ATTRIBUTE_ON_DCT3 0x08000000ul ///< UMA resides on memory that belongs to DCT3
+
+typedef UINT8 PSO_TABLE; ///< Platform Configuration Table
+
+// AGESA DEFINITIONS
+//
+// Many of these are derived from the platform and hardware specific definitions
+
+/// EccSymbolSize override value
+#define ECCSYMBOLSIZE_USE_BKDG 0 ///< Use BKDG Recommended Value
+#define ECCSYMBOLSIZE_FORCE_X4 4 ///< Force to x4
+#define ECCSYMBOLSIZE_FORCE_X8 8 ///< Force to x8
+/// CPU Package Type
+#define PT_L1 0 ///< L1 Package type
+#define PT_M2 1 ///< AM Package type
+#define PT_S1 2 ///< S1 Package type
+
+/// Build Configuration values for BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT & BLDCFG_MEMORY_CLOCK_SELECT
+#define DDR400_FREQUENCY 200 ///< DDR 400
+#define DDR533_FREQUENCY 266 ///< DDR 533
+#define DDR667_FREQUENCY 333 ///< DDR 667
+#define DDR800_FREQUENCY 400 ///< DDR 800
+#define DDR1066_FREQUENCY 533 ///< DDR 1066
+#define DDR1333_FREQUENCY 667 ///< DDR 1333
+#define DDR1600_FREQUENCY 800 ///< DDR 1600
+#define DDR1866_FREQUENCY 933 ///< DDR 1866
+#define DDR2100_FREQUENCY 1050 ///< DDR 2100
+#define DDR2133_FREQUENCY 1066 ///< DDR 2133
+#define DDR2400_FREQUENCY 1200 ///< DDR 2400
+#define UNSUPPORTED_DDR_FREQUENCY 1201 ///< Highest limit of DDR frequency
+
+/// Build Configuration values for BLDCFG_TIMING_MODE_SELECT
+#define TIMING_MODE_AUTO 0 ///< Use best rate possible
+#define TIMING_MODE_LIMITED 1 ///< Set user top limit
+#define TIMING_MODE_SPECIFIC 2 ///< Set user specified speed
+
+/// Build Configuration values for BLDCFG_MEMORY_QUADRANK_TYPE
+#define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM
+#define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM
+
+/// Build Configuration values for BLDCFG_POWER_DOWN_MODE
+#define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode
+#define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode
+#define POWER_DOWN_MODE_AUTO 2 ///< AGESA to select power down mode
+
+/// Build Configuration limit for BLDCFG_GNB_GPU_MAX_FREQUENCY
+#define UNSUPPORTED_GPU_FREQUENCY 901 ///< Highest limit of GPU frequency
+
+/// Structures use to pass system Logical CPU-ID
+typedef struct {
+ IN OUT UINT64 Family; ///< Indicates logical ID Family
+ IN OUT UINT64 Revision; ///< Indicates logical ID Family
+} CPU_LOGICAL_ID;
+
+/// Structures use to report AMP status
+typedef struct {
+ OUT BOOLEAN AmpVoltageValid; ///< Indicates if Amp voltage is valid
+ OUT BOOLEAN AmpSupportDetectedButNotEnabled; ///< Indicates if Amp support is detected but not enabled
+ OUT BOOLEAN AmpSelectedButNotEnabled; ///< Indicates if Amp is selected but not enabled
+} AMP_STATUS;
+
+/// Normalized Critical Composite Data Eye
+/// Bit 15 represents trained eye Center
+/// Bit 0 represents eye center -15 delay steps
+/// Bit 31 represents eye center +16 delay steps
+/// Offset 0 represents +15 Vref Steps
+/// Offset 31 represents -15 Vref Steps
+typedef UINT32 COMPOSITE_DATAEYE[DATAEYE_VREF_RANGE];
+
+/// Build Configuration values for BLDCFG_AMD_PLATFORM_TYPE
+typedef enum {
+ AMD_PLATFORM_SERVER = 0x8000, ///< Server
+ AMD_PLATFORM_DESKTOP = 0x10000, ///< Desktop
+ AMD_PLATFORM_MOBILE = 0x20000, ///< Mobile
+} AMD_PLATFORM_TYPE;
+
+/// Dram technology type
+typedef enum {
+ DDR2_TECHNOLOGY, ///< DDR2 technology
+ DDR3_TECHNOLOGY, ///< DDR3 technology
+ GDDR5_TECHNOLOGY, ///< GDDR5 technology
+ UNSUPPORTED_TECHNOLOGY, ///< Unsupported technology
+} TECHNOLOGY_TYPE;
+
+/// Low voltage support
+typedef enum {
+ VOLT_INITIAL, ///< Initial value for VDDIO
+ VOLT1_5, ///< 1.5 Volt
+ VOLT1_35, ///< 1.35 Volt
+ VOLT1_25, ///< 1.25 Volt
+ VOLT_UNSUPPORTED = 0xFF ///< No common voltage found
+} DIMM_VOLTAGE;
+
+/// AMP voltage support
+typedef enum {
+ AMP_VOLT_RSVD, ///< Reserved
+ AMP_VOLT1_5, ///< 1.5 Volt
+ AMP_VOLT1_55, ///< 1.55 Volt
+ AMP_VOLT1_6, ///< 1.6 Volt
+ AMP_VOLT1_65, ///< 1.65 Volt
+ AMP_VOLT1_7, ///< 1.7 Volt
+ AMP_VOLT1_75, ///< 1.75 Volt
+ AMP_VOLT1_8, ///< 1.8 Volt
+ AMP_VOLT1_85, ///< 1.85 Volt
+ AMP_VOLT1_9, ///< 1.9 Volt
+ AMP_VOLT1_45 = 0x10, ///< 1.45 Volt
+ AMP_VOLT1_4 = 0x20, ///< 1.4 Volt
+ AMP_VOLT1_35 = 0x30, ///< 1.35 Volt
+ AMP_VOLT1_3 = 0x40, ///< 1.3 Volt
+ AMP_VOLT1_25 = 0x50, ///< 1.25 Volt
+ AMP_VOLT1_2 = 0x60 ///< 1.2 Volt
+} AMP_DIMM_VOLTAGE;
+
+/// Build Configuration values for BLDCFG_ACP_SIZE
+typedef enum {
+ NO_ACP_SIZE = 0x00, ///< NO ACP
+ ACP_SIZE_2MB = 0x20, ///< UMA 4MB aligned
+ ACP_SIZE_4MB = 0x40, ///< UMA 128MB aligned
+} ACP_SIZE;
+
+/// UMA Mode
+typedef enum {
+ UMA_NONE = 0, ///< UMA None
+ UMA_SPECIFIED = 1, ///< UMA Specified
+ UMA_AUTO = 2 ///< UMA Auto
+} UMA_MODE;
+
+/// Force Training Mode
+typedef enum {
+ FORCE_TRAIN_1D = 0, ///< 1D Training only
+ FORCE_TRAIN_2D = 1, ///< 2D Training only
+ FORCE_TRAIN_AUTO = 2 ///< Auto - 1D or 2D depending on configuration
+} FORCE_TRAIN_MODE;
+
+/// PMU Training Mode
+typedef enum {
+ PMU_TRAIN_1D = 0, ///< PMU 1D Training only
+ PMU_TRAIN_1D_2D_READ = 1, ///< PMU 1D and 2D Training read only
+ PMU_TRAIN_1D_2D = 2, ///< PMU 1D and 2D Training
+ PMU_TRAIN_AUTO = 3 ///< Auto - PMU Training depend on configuration
+} PMU_TRAIN_MODE;
+
+/// The possible DRAM prefetch mode settings.
+typedef enum {
+ DRAM_PREFETCHER_AUTO, ///< Use the recommended setting for the processor. In most cases, the recommended setting is enabled.
+ DISABLE_DRAM_PREFETCH_FOR_IO, ///< Disable DRAM prefetching for I/O requests only.
+ DISABLE_DRAM_PREFETCH_FOR_CPU, ///< Disable DRAM prefetching for requests from processor cores only.
+ DISABLE_DRAM_PREFETCHER, ///< Disable DRAM prefetching.
+ MAX_DRAM_FREFETCH_MODE ///< Not a DRAM prefetch mode, use for limit checking.
+} DRAM_PREFETCH_MODE;
+
+/// Build Configuration values for BLDCFG_UMA_ALIGNMENT
+typedef enum {
+ NO_UMA_ALIGNED = 0x00FFFFFF, ///< NO UMA aligned
+ UMA_4MB_ALIGNED = 0x00FFFFC0, ///< UMA 4MB aligned
+ UMA_128MB_ALIGNED = 0x00FFF800, ///< UMA 128MB aligned
+ UMA_256MB_ALIGNED = 0x00FFF000, ///< UMA 256MB aligned
+ UMA_512MB_ALIGNED = 0x00FFE000, ///< UMA 512MB aligned
+} UMA_ALIGNMENT;
+
+///
+/// Global MCT Configuration Status Word (GStatus)
+///
+typedef enum {
+ GsbMTRRshort, ///< Ran out of MTRRs while mapping memory
+ GsbAllECCDimms, ///< All banks of all Nodes are ECC capable
+ GsbDramECCDis, ///< Dram ECC requested but not enabled.
+ GsbSoftHole, ///< A Node Base gap was created
+ GsbHWHole, ///< A HW dram remap was created
+ GsbNodeIntlv, ///< Node Memory interleaving was enabled
+ GsbSpIntRemapHole, ///< Special condition for Node Interleave and HW remapping
+ GsbEnDIMMSpareNW, ///< Indicates that DIMM Spare can be used without a warm reset
+
+ GsbEOL ///< End of list
+} GLOBAL_STATUS_FIELD;
+
+///
+/// Local Error Status (DIE_STRUCT.ErrStatus[31:0])
+///
+typedef enum {
+ EsbNoDimms, ///< No DIMMs
+ EsbSpdChkSum, ///< SPD Checksum fail
+ EsbDimmMismatchM, ///< dimm module type(buffer) mismatch
+ EsbDimmMismatchT, ///< dimm CL/T mismatch
+ EsbDimmMismatchO, ///< dimm organization mismatch (128-bit)
+ EsbNoTrcTrfc, ///< SPD missing Trc or Trfc info
+ EsbNoCycTime, ///< SPD missing byte 23 or 25
+ EsbBkIntDis, ///< Bank interleave requested but not enabled
+ EsbDramECCDis, ///< Dram ECC requested but not enabled
+ EsbSpareDis, ///< Online spare requested but not enabled
+ EsbMinimumMode, ///< Running in Minimum Mode
+ EsbNoRcvrEn, ///< No DQS Receiver Enable pass window found
+ EsbSmallRcvr, ///< DQS Rcvr En pass window too small (far right of dynamic range)
+ EsbNoDqsPos, ///< No DQS-DQ passing positions
+ EsbSmallDqs, ///< DQS-DQ passing window too small
+ EsbDCBKScrubDis, ///< DCache scrub requested but not enabled
+
+ EsbEMPNotSupported, ///< Processor is not capable for EMP.
+ EsbEMPConflict, ///< EMP requested but cannot be enabled since
+ ///< channel interleaving, bank interleaving, or bank swizzle is enabled.
+ EsbEMPDis, ///< EMP requested but cannot be enabled since
+ ///< memory size of each DCT is not a power of two.
+
+ EsbEOL ///< End of list
+} ERROR_STATUS_FIELD;
+
+///
+/// Local Configuration Status (DIE_STRUCT.Status[31:0])
+///
+typedef enum {
+ SbRegistered, ///< All DIMMs are Registered
+ SbEccDimms, ///< All banks ECC capable
+ SbParDimms, ///< All banks Addr/CMD Parity capable
+ SbDiagClks, ///< Jedec ALL slots clock enable diag mode
+ Sb128bitmode, ///< DCT in 128-bit mode operation
+ Sb64MuxedMode, ///< DCT in 64-bit mux'ed mode.
+ Sb2TMode, ///< 2T CMD timing mode is enabled.
+ SbSWNodeHole, ///< Remapping of Node Base on this Node to create a gap.
+ SbHWHole, ///< Memory Hole created on this Node using HW remapping.
+ SbOver400Mhz, ///< DCT freq greater than or equal to 400MHz flag
+ SbDQSPosPass2, ///< Used for TrainDQSPos DIMM0/1, when freq greater than or equal to 400MHz
+ SbDQSRcvLimit, ///< Used for DQSRcvEnTrain to know we have reached the upper bound.
+ SbExtConfig, ///< Indicate the default setting for extended PCI configuration support
+ SbLrdimms, ///< All DIMMs are LRDIMMs
+
+ SbEOL ///< End of list
+} LOCAL_STATUS_FIELD;
+
+
+///< CPU MSR Register definitions ------------------------------------------
+#define SYS_CFG 0xC0010010ul
+#define TOP_MEM 0xC001001Aul
+#define TOP_MEM2 0xC001001Dul
+#define HWCR 0xC0010015ul
+#define NB_CFG 0xC001001Ful
+
+#define FS_BASE 0xC0000100ul
+#define IORR0_BASE 0xC0010016ul
+#define IORR0_MASK 0xC0010017ul
+#define BU_CFG 0xC0011023ul
+#define BU_CFG2 0xC001102Aul
+#define COFVID_STAT 0xC0010071ul
+#define TSC 0x10
+
+//-----------------------------------------------------------------------------
+///
+/// SPD Data for each DIMM.
+///
+typedef struct _SPD_DEF_STRUCT {
+ IN BOOLEAN DimmPresent; ///< Indicates that the DIMM is present and Data is valid
+ IN UINT8 Data[256]; ///< Buffer for 256 Bytes of SPD data from DIMM
+} SPD_DEF_STRUCT;
+
+
+//-----------------------------------------------------------------------------
+///
+/// VDDP_VDDR Voltage Info for Low Power DIMM
+///
+typedef struct _VDDP_VDDR_VOLTAGE {
+ IN BOOLEAN IsValid; ///< Indicates if daata is valid
+ IN MEMORY_PHY_VOLTAGE Voltage; ///< VDDP VDDR Voltage Value
+} VDDP_VDDR_VOLTAGE;
+
+///
+/// Channel Definition Structure.
+/// This data structure defines entries that are specific to the channel initialization
+///
+typedef struct _CH_DEF_STRUCT {
+ OUT UINT8 ChannelID; ///< Physical channel ID of a socket(0 = CH A, 1 = CH B, 2 = CH C, 3 = CH D)
+ OUT TECHNOLOGY_TYPE TechType; ///< Technology type of this channel
+ OUT UINT8 ChDimmPresent; ///< For each bit n 0..7, 1 = DIMM n is present.
+ ///< DIMM# Select Signal
+ ///< 0 MA0_CS_L[0, 1]
+ ///< 1 MB0_CS_L[0, 1]
+ ///< 2 MA1_CS_L[0, 1]
+ ///< 3 MB1_CS_L[0, 1]
+ ///< 4 MA2_CS_L[0, 1]
+ ///< 5 MB2_CS_L[0, 1]
+ ///< 6 MA3_CS_L[0, 1]
+ ///< 7 MB3_CS_L[0, 1]
+
+ OUT struct _DCT_STRUCT *DCTPtr; ///< Pointer to the DCT data of this channel.
+ OUT struct _DIE_STRUCT *MCTPtr; ///< Pointer to the node data of this channel.
+ OUT SPD_DEF_STRUCT *SpdPtr; ///< Pointer to the SPD data for this channel. (Setup by NB Constructor)
+ OUT SPD_DEF_STRUCT *DimmSpdPtr[MAX_DIMMS_PER_CHANNEL]; ///< Array of pointers to
+ ///< SPD Data for each Dimm. (Setup by Tech Block Constructor)
+ OUT UINT8 ChDimmValid; ///< For each bit n 0..3, 1 = DIMM n is valid and is/will be configured where 4..7 are reserved.
+ ///<
+ OUT UINT8 RegDimmPresent; ///< For each bit n 0..3, 1 = DIMM n is a registered DIMM where 4..7 are reserved.
+ OUT UINT8 LrDimmPresent; ///< For each bit n 0..3, 1 = DIMM n is Load Reduced DIMM where 4..7 are reserved.
+ OUT UINT8 SODimmPresent; ///< For each bit n 0..3, 1 = DIMM n is a SO-DIMM, where 4..7 are reserved.
+ OUT UINT8 Loads; ///< Number of devices loading bus
+ OUT UINT8 Dimms; ///< Number of DIMMs loading Channel
+ OUT UINT8 Ranks; ///< Number of ranks loading Channel DATA
+ OUT BOOLEAN SlowMode; ///< 1T or 2T CMD mode (slow access mode)
+ ///< FALSE = 1T
+ ///< TRUE = 2T
+ ///< The following pointers will be pointed to dynamically allocated buffers.
+ ///< Each buffer is two dimensional (RowCount x ColumnCount) and is lay-outed as in below.
+ ///< Example: If DIMM and Byte based training, then
+ ///< XX is a value in Hex
+ ///< BYTE 0, BYTE 1, BYTE 2, BYTE 3, BYTE 4, BYTE 5, BYTE 6, BYTE 7, ECC BYTE
+ ///< Row1 - Logical DIMM0 XX XX XX XX XX XX XX XX XX
+ ///< Row2 - Logical DIMM1 XX XX XX XX XX XX XX XX XX
+ OUT UINT16 *RcvEnDlys; ///< DQS Receiver Enable Delays
+ OUT UINT8 *WrDqsDlys; ///< Write DQS delays (only valid for DDR3)
+ OUT UINT8 *RdDqsDlys; ///< Read Dqs delays
+ OUT UINT8 *WrDatDlys; ///< Write Data delays
+ OUT UINT8 *RdDqs2dDlys; ///< 2d Read DQS data
+ OUT UINT8 *RdDqsMinDlys; ///< Minimum Window for Read DQS
+ OUT UINT8 *RdDqsMaxDlys; ///< Maximum Window for Read DQS
+ OUT UINT8 *WrDatMinDlys; ///< Minimum Window for Write data
+ OUT UINT8 *WrDatMaxDlys; ///< Maximum Window for Write data
+ OUT UINT16 *RcvEnDlysMemPs1; ///< DQS Receiver Enable Delays for Mem Pstate 1
+ OUT UINT8 *WrDqsDlysMemPs1; ///< Write DQS delays (only valid for DDR3) for Mem Pstate 1
+ OUT UINT8 *RdDqsDlysMemPs1; ///< Read Dqs delays for Memory Pstate 1
+ OUT UINT8 *WrDatDlysMemPs1; ///< Write Data delays for Memory Pstate 1
+ OUT UINT8 *RdDqs2dDlysMemPs1; ///< 2d Read DQS data for Memory Pstate 1
+ OUT UINT8 *RdDqsMinDlysMemPs1; ///< Minimum Window for Read DQS for Memory Pstate 1
+ OUT UINT8 *RdDqsMaxDlysMemPs1; ///< Maximum Window for Read DQS for Memory Pstate 1
+ OUT UINT8 *WrDatMinDlysMemPs1; ///< Minimum Window for Write data for Memory Pstate 1
+ OUT UINT8 *WrDatMaxDlysMemPs1; ///< Maximum Window for Write data for Memory Pstate 1
+ OUT UINT8 RowCount; ///< Number of rows of the allocated buffer.
+ OUT UINT8 ColumnCount; ///< Number of columns of the allocated buffer.
+ OUT UINT8 *FailingBitMask; ///< Table of masks to Track Failing bits
+ OUT UINT8 *FailingBitMaskMemPs1; ///< Table of masks to Track Failing bits for Memory Pstate 1
+ OUT VOID *RdDataEyes; ///< Pointer to Read Data Eye Bitmaps
+ OUT VOID *WrDataEyes; ///< Pointer to Write Data Eye Bitmaps
+ OUT UINT32 DctOdcCtl; ///< Output Driver Strength (see BKDG FN2:Offset 9Ch, index 00h)
+ OUT UINT32 DctAddrTmg; ///< Address Bus Timing (see BKDG FN2:Offset 9Ch, index 04h)
+ OUT UINT32 PhyRODTCSLow; ///< Phy Read ODT Pattern Chip Select low (see BKDG FN2:Offset 9Ch, index 180h)
+ OUT UINT32 PhyRODTCSHigh; ///< Phy Read ODT Pattern Chip Select high (see BKDG FN2:Offset 9Ch, index 181h)
+ OUT UINT32 PhyWODTCSLow; ///< Phy Write ODT Pattern Chip Select low (see BKDG FN2:Offset 9Ch, index 182h)
+ OUT UINT32 PhyWODTCSHigh; ///< Phy Write ODT Pattern Chip Select high (see BKDG FN2:Offset 9Ch, index 183)
+ OUT UINT8 PhyWLODT[4]; ///< Write Levelization ODT Pattern for Dimm 0-3 or CS 0-7(see BKDG FN2:Offset 9Ch, index 0x8[11:8])
+ OUT UINT16 DctEccDqsLike; ///< DCT DQS ECC UINT8 like...
+ OUT UINT8 DctEccDqsScale; ///< DCT DQS ECC UINT8 scale
+ OUT UINT16 PtrPatternBufA; ///< Ptr on stack to aligned DQS testing pattern
+ OUT UINT16 PtrPatternBufB; ///< Ptr on stack to aligned DQS testing pattern
+ OUT UINT8 ByteLane; ///< Current UINT8 Lane (0..7)
+ OUT UINT8 Direction; ///< Current DQS-DQ training write direction (0=read, 1=write)
+ OUT UINT8 Pattern; ///< Current pattern
+ OUT UINT8 DqsDelay; ///< Current DQS delay value
+ OUT UINT16 HostBiosSrvc1; ///< UINT16 sized general purpose field for use by host BIOS. Scratch space.
+ OUT UINT32 HostBiosSrvc2; ///< UINT32 sized general purpose field for use by host BIOS. Scratch space.
+ OUT UINT16 DctMaxRdLat[4]; ///< Max Read Latency (ns) for the DCT
+ ///< DctMaxRdLat [i] is for NBPstate i
+ OUT UINT8 DIMMValidCh; ///< DIMM# in CH
+ OUT UINT8 MaxCh; ///< Max number of CH in system
+ OUT UINT8 Dct; ///< Dct pointer
+ OUT UINT8 WrDatGrossH; ///< Write Data Gross delay high value
+ OUT UINT8 DqsRcvEnGrossL; ///< DQS Receive Enable Gross Delay low
+
+ OUT UINT8 TrwtWB; ///< Non-SPD timing value for TrwtWB
+ OUT UINT8 CurrRcvrDctADelay; ///< for keep current RcvrEnDly
+ OUT UINT16 T1000; ///< get the T1000 figure (cycle time (ns) * 1K)
+ OUT UINT8 DqsRcvEnPass; ///< for TrainRcvrEn UINT8 lane pass flag
+ OUT UINT8 DqsRcvEnSaved; ///< for TrainRcvrEn UINT8 lane saved flag
+ OUT UINT8 SeedPass1Remainder; ///< for Phy assisted DQS receiver enable training
+
+ OUT UINT8 ClToNbFlag; ///< is used to restore ClLinesToNbDis bit after memory
+ OUT UINT32 NodeSysBase; ///< for channel interleave usage
+ OUT UINT8 RefRawCard[MAX_DIMMS_PER_CHANNEL]; ///< Array of rawcards detected
+ OUT UINT8 CtrlWrd02[MAX_DIMMS_PER_CHANNEL]; ///< Control Word 2 values per DIMM
+ OUT UINT8 CtrlWrd03[MAX_DIMMS_PER_CHANNEL]; ///< Control Word 3 values per DIMM
+ OUT UINT8 CtrlWrd04[MAX_DIMMS_PER_CHANNEL]; ///< Control Word 4 values per DIMM
+ OUT UINT8 CtrlWrd05[MAX_DIMMS_PER_CHANNEL]; ///< Control Word 5 values per DIMM
+ OUT UINT8 CtrlWrd08[MAX_DIMMS_PER_CHANNEL]; ///< Control Word 8 values per DIMM
+
+ OUT UINT16 CsPresentDCT; ///< For each bit n 0..7, 1 = Chip-select n is present
+ OUT UINT8 DimmMirrorPresent; ///< For each bit n 0..3, 1 = DIMM n is OnDimmMirror capable where 4..7 are reserved.
+ OUT UINT8 DimmSpdCse; ///< For each bit n 0..3, 1 = DIMM n SPD checksum error where 4..7 are reserved.
+ OUT UINT8 DimmExclude; ///< For each bit n 0..3, 1 = DIMM n gets excluded where 4..7 are reserved.
+ OUT UINT8 DimmYr06; ///< Bitmap indicating which Dimms have a manufacturer's year code <= 2006
+ OUT UINT8 DimmWk2406; ///< Bitmap indicating which Dimms have a manufacturer's week code <= 24 of 2006 (June)
+ OUT UINT8 DimmPlPresent; ///< Bitmap indicating that Planar (1) or Stacked (0) Dimms are present.
+ OUT UINT8 DimmQrPresent; ///< QuadRank DIMM present?
+ OUT UINT8 DimmDrPresent; ///< Bitmap indicating that Dual Rank Dimms are present
+ OUT UINT8 DimmSRPresent; ///< Bitmap indicating that Single Rank Dimms are present
+ OUT UINT8 Dimmx4Present; ///< For each bit n 0..3, 1 = DIMM n contains x4 data devices. where 4..7 are reserved.
+ OUT UINT8 Dimmx8Present; ///< For each bit n 0..3, 1 = DIMM n contains x8 data devices. where 4..7 are reserved.
+ OUT UINT8 Dimmx16Present; ///< For each bit n 0..3, 1 = DIMM n contains x16 data devices. where 4..7 are reserved.
+ OUT UINT8 LrdimmPhysicalRanks[MAX_DIMMS_PER_CHANNEL];///< Number of Physical Ranks for LRDIMMs
+ OUT UINT8 LrDimmLogicalRanks[MAX_DIMMS_PER_CHANNEL];///< Number of LRDIMM Logical ranks in this configuration
+ OUT UINT8 LrDimmRankMult[MAX_DIMMS_PER_CHANNEL];///< Rank Multipication factor per dimm.
+ OUT UINT8 DimmNibbleAccess; ///< For each bit n 0..3, 1 = DIMM n will use nibble signaling. Where 4..7 are reserved.
+ OUT UINT8 *MemClkDisMap; ///< This pointer will be set to point to an array that describes
+ ///< the routing of M[B,A]_CLK pins to the DIMMs' ranks. AGESA will
+ ///< base on this array to disable unused MemClk to save power.
+ ///<
+ ///< The array must have 8 entries. Each entry, which associates with
+ ///< one MemClkDis bit, is a bitmap of 8 CS that that MemClk is routed to.
+ ///< Example:
+ ///< BKDG definition of Fn2x88[MemClkDis] bitmap for AM3 package
+ ///< is like below:
+ ///< Bit AM3/S1g3 pin name
+ ///< 0 M[B,A]_CLK_H/L[0]
+ ///< 1 M[B,A]_CLK_H/L[1]
+ ///< 2 M[B,A]_CLK_H/L[2]
+ ///< 3 M[B,A]_CLK_H/L[3]
+ ///< 4 M[B,A]_CLK_H/L[4]
+ ///< 5 M[B,A]_CLK_H/L[5]
+ ///< 6 M[B,A]_CLK_H/L[6]
+ ///< 7 M[B,A]_CLK_H/L[7]
+ ///< And platform has the following routing:
+ ///< CS0 M[B,A]_CLK_H/L[4]
+ ///< CS1 M[B,A]_CLK_H/L[2]
+ ///< CS2 M[B,A]_CLK_H/L[3]
+ ///< CS3 M[B,A]_CLK_H/L[5]
+ ///< Then MemClkDisMap should be pointed to the following array:
+ ///< CLK_2 CLK_3 CLK_4 CLK_5
+ ///< 0x00, 0x00, 0x02, 0x04, 0x01, 0x08, 0x00, 0x00
+ ///< Each entry of the array is the bitmask of 8 chip selects.
+
+ OUT UINT8 *CKETriMap; ///< This pointer will be set to point to an array that describes
+ ///< the routing of CKE pins to the DIMMs' ranks.
+ ///< The array must have 2 entries. Each entry, which associates with
+ ///< one CKE pin, is a bitmap of 8 CS that that CKE is routed to.
+ ///< AGESA will base on this array to disable unused CKE pins to save power.
+
+ OUT UINT8 *ODTTriMap; ///< This pointer will be set to point to an array that describes
+ ///< the routing of ODT pins to the DIMMs' ranks.
+ ///< The array must have 4 entries. Each entry, which associates with
+ ///< one ODT pin, is a bitmap of 8 CS that that ODT is routed to.
+ ///< AGESA will base on this array to disable unused ODT pins to save power.
+
+ OUT UINT8 *ChipSelTriMap; ///< This pointer will be set to point to an array that describes
+ ///< the routing of chip select pins to the DIMMs' ranks.
+ ///< The array must have 8 entries. Each entry is a bitmap of 8 CS.
+ ///< AGESA will base on this array to disable unused Chip select pins to save power.
+
+ OUT BOOLEAN ExtendTmp; ///< If extended temperature is supported on all dimms on a channel.
+
+ OUT UINT8 MaxVref; ///< Maximum Vref Value for channel
+
+ OUT UINT8 Reserved[100]; ///< Reserved
+} CH_DEF_STRUCT;
+
+///
+/// DCT Channel Timing Parameters.
+/// This data structure sets timings that are specific to the channel.
+///
+typedef struct _CH_TIMING_STRUCT {
+ OUT UINT16 DctDimmValid; ///< For each bit n 0..3, 1=DIMM n is valid and is/will be configured where 4..7 are reserved.
+ OUT UINT16 DimmMirrorPresent; ///< For each bit n 0..3, 1=DIMM n is OnDimmMirror capable where 4..7 are reserved.
+ OUT UINT16 DimmSpdCse; ///< For each bit n 0..3, 1=DIMM n SPD checksum error where 4..7 are reserved.
+ OUT UINT16 DimmExclude; ///< For each bit n 0..3, 1 = DIMM n gets excluded where 4..7 are reserved.
+ OUT UINT16 CsPresent; ///< For each bit n 0..7, 1=Chip-select n is present
+ OUT UINT16 CsEnabled; ///< For each bit n 0..7, 1=Chip-select n is enabled
+ OUT UINT16 CsTestFail; ///< For each bit n 0..7, 1=Chip-select n is present but disabled
+ OUT UINT16 CsTrainFail; ///< Bitmap showing which chipselects failed training
+ OUT UINT16 DIMM1KPage; ///< For each bit n 0..3, 1=DIMM n contains 1K page devices. where 4..7 are reserved
+ OUT UINT16 DimmQrPresent; ///< QuadRank DIMM present?
+ OUT UINT16 DimmDrPresent; ///< Bitmap indicating that Dual Rank Dimms are present , where 4..7 are reserved
+ OUT UINT8 DimmSRPresent; ///< Bitmap indicating that Single Rank Dimms are present, where 4..7 are reserved
+ OUT UINT16 Dimmx4Present; ///< For each bit n 0..3, 1=DIMM n contains x4 data devices. where 4..7 are reserved
+ OUT UINT16 Dimmx8Present; ///< For each bit n 0..3, 1=DIMM n contains x8 data devices. where 4..7 are reserved
+ OUT UINT16 Dimmx16Present; ///< For each bit n 0..3, 1=DIMM n contains x16 data devices. where 4..7 are reserved
+
+ OUT UINT16 DIMMTrcd; ///< Minimax Trcd*40 (ns) of DIMMs
+ OUT UINT16 DIMMTrp; ///< Minimax Trp*40 (ns) of DIMMs
+ OUT UINT16 DIMMTrtp; ///< Minimax Trtp*40 (ns) of DIMMs
+ OUT UINT16 DIMMTras; ///< Minimax Tras*40 (ns) of DIMMs
+ OUT UINT16 DIMMTrc; ///< Minimax Trc*40 (ns) of DIMMs
+ OUT UINT16 DIMMTwr; ///< Minimax Twr*40 (ns) of DIMMs
+ OUT UINT16 DIMMTrrd; ///< Minimax Trrd*40 (ns) of DIMMs
+ OUT UINT16 DIMMTwtr; ///< Minimax Twtr*40 (ns) of DIMMs
+ OUT UINT16 DIMMTfaw; ///< Minimax Tfaw*40 (ns) of DIMMs
+ OUT UINT16 TargetSpeed; ///< Target DRAM bus speed in MHz
+ OUT UINT16 Speed; ///< DRAM bus speed in MHz
+ ///< 400 (MHz)
+ ///< 533 (MHz)
+ ///< 667 (MHz)
+ ///< 800 (MHz)
+ ///< and so on...
+ OUT UINT8 CasL; ///< CAS latency DCT setting (busclocks)
+ OUT UINT8 Trcd; ///< DCT Trcd (busclocks)
+ OUT UINT8 Trp; ///< DCT Trp (busclocks)
+ OUT UINT8 Trtp; ///< DCT Trtp (busclocks)
+ OUT UINT8 Tras; ///< DCT Tras (busclocks)
+ OUT UINT8 Trc; ///< DCT Trc (busclocks)
+ OUT UINT8 Twr; ///< DCT Twr (busclocks)
+ OUT UINT8 Trrd; ///< DCT Trrd (busclocks)
+ OUT UINT8 Twtr; ///< DCT Twtr (busclocks)
+ OUT UINT8 Tfaw; ///< DCT Tfaw (busclocks)
+ OUT UINT8 Trfc0; ///< DCT Logical DIMM0 Trfc
+ ///< 0 = 75ns (for 256Mb devs)
+ ///< 1 = 105ns (for 512Mb devs)
+ ///< 2 = 127.5ns (for 1Gb devs)
+ ///< 3 = 195ns (for 2Gb devs)
+ ///< 4 = 327.5ns (for 4Gb devs)
+ OUT UINT8 Trfc1; ///< DCT Logical DIMM1 Trfc (see Trfc0 for format)
+ OUT UINT8 Trfc2; ///< DCT Logical DIMM2 Trfc (see Trfc0 for format)
+ OUT UINT8 Trfc3; ///< DCT Logical DIMM3 Trfc (see Trfc0 for format)
+ OUT UINT32 DctMemSize; ///< Base[47:16], total DRAM size controlled by this DCT.
+ ///<
+ OUT BOOLEAN SlowMode; ///< 1T or 2T CMD mode (slow access mode)
+ ///< FALSE = 1T
+ ///< TRUE = 2T
+ OUT UINT8 TrwtTO; ///< DCT TrwtTO (busclocks)
+ OUT UINT8 Twrrd; ///< DCT Twrrd (busclocks)
+ OUT UINT8 Twrwr; ///< DCT Twrwr (busclocks)
+ OUT UINT8 Trdrd; ///< DCT Trdrd (busclocks)
+ OUT UINT8 TrwtWB; ///< DCT TrwtWB (busclocks)
+ OUT UINT8 TrdrdSD; ///< DCT TrdrdSD (busclocks)
+ OUT UINT8 TwrwrSD; ///< DCT TwrwrSD (busclocks)
+ OUT UINT8 TwrrdSD; ///< DCT TwrrdSD (busclocks)
+ OUT UINT16 MaxRdLat; ///< Max Read Latency
+ OUT UINT8 WrDatGrossH; ///< Temporary variables must be removed
+ OUT UINT8 DqsRcvEnGrossL; ///< Temporary variables must be removed
+} CH_TIMING_STRUCT;
+
+///
+/// Data for each DCT.
+/// This data structure defines data used to configure each DRAM controller.
+///
+typedef struct _DCT_STRUCT {
+ OUT UINT8 Dct; ///< Current Dct
+ OUT CH_TIMING_STRUCT Timings; ///< Channel Timing structure
+ OUT CH_TIMING_STRUCT *TimingsMemPs1; ///< Pointed to channel timing structure for memory Pstate 1
+ OUT CH_DEF_STRUCT *ChData; ///< Pointed to a dynamically allocated array of Channel structures
+ OUT UINT8 ChannelCount; ///< Number of channel per this DCT
+ OUT BOOLEAN BkIntDis; ///< Bank interleave requested but not enabled on current DCT
+ OUT UINT8 BankAddrMap; ///< Bank Address Mapping
+ OUT UINT8 EnabledChipSels; ///< Number of enabled chip selects on current DCT
+} DCT_STRUCT;
+
+
+///
+/// Data Structure defining each Die.
+/// This data structure contains information that is used to configure each Die.
+///
+typedef struct _DIE_STRUCT {
+
+ /// Advanced:
+
+ OUT UINT8 NodeId; ///< Node ID of current controller
+ OUT UINT8 SocketId; ///< Socket ID of this Die
+ OUT UINT8 DieId; ///< ID of this die relative to the socket
+ OUT PCI_ADDR PciAddr; ///< Pci bus and device number of this controller.
+ OUT AGESA_STATUS ErrCode; ///< Current error condition of Node
+ ///< 0x0 = AGESA_SUCCESS
+ ///< 0x1 = AGESA_UNSUPPORTED
+ ///< 0x2 = AGESA_BOUNDS_CHK
+ ///< 0x3 = AGESA_ALERT
+ ///< 0x4 = AGESA_WARNING
+ ///< 0x5 = AGESA_ERROR
+ ///< 0x6 = AGESA_CRITICAL
+ ///< 0x7 = AGESA_FATAL
+ ///<
+ OUT BOOLEAN ErrStatus[EsbEOL]; ///< Error Status bit Field
+ ///<
+ OUT BOOLEAN Status[SbEOL]; ///< Status bit Field
+ ///<
+ OUT UINT32 NodeMemSize; ///< Base[47:16], total DRAM size controlled by both DCT0 and DCT1 of this Node.
+ ///<
+ OUT UINT32 NodeSysBase; ///< Base[47:16] (system address) DRAM base address of this Node.
+ ///<
+ OUT UINT32 NodeHoleBase; ///< If not zero, Base[47:16] (system address) of dram hole for HW remapping. Dram hole exists on this Node
+ ///<
+ OUT UINT32 NodeSysLimit; ///< Base[47:16] (system address) DRAM limit address of this Node.
+ ///<
+ OUT UINT32 DimmPresent; ///< For each bit n 0..7, 1 = DIMM n is present.
+ ///< DIMM# Select Signal
+ ///< 0 MA0_CS_L[0, 1]
+ ///< 1 MB0_CS_L[0, 1]
+ ///< 2 MA1_CS_L[0, 1]
+ ///< 3 MB1_CS_L[0, 1]
+ ///< 4 MA2_CS_L[0, 1]
+ ///< 5 MB2_CS_L[0, 1]
+ ///< 6 MA3_CS_L[0, 1]
+ ///< 7 MB3_CS_L[0, 1]
+ ///<
+ OUT UINT32 DimmValid; ///< For each bit n 0..7, 1 = DIMM n is valid and is / will be configured
+ OUT UINT32 RegDimmPresent; ///< For each bit n 0..7, 1 = DIMM n is registered DIMM
+ OUT UINT32 LrDimmPresent; ///< For each bit n 0..7, 1 = DIMM n is Load Reduced DIMM
+ OUT UINT32 DimmEccPresent; ///< For each bit n 0..7, 1 = DIMM n is ECC capable.
+ OUT UINT32 DimmParPresent; ///< For each bit n 0..7, 1 = DIMM n is ADR/CMD Parity capable.
+ ///<
+ OUT UINT16 DimmTrainFail; ///< Bitmap showing which dimms failed training
+ OUT UINT16 ChannelTrainFail; ///< Bitmap showing the channel information about failed Chip Selects
+ ///< 0 in any bit field indicates Channel 0
+ ///< 1 in any bit field indicates Channel 1
+ OUT UINT8 Dct; ///< Need to be removed
+ ///< DCT pointer
+ OUT BOOLEAN GangedMode; ///< Ganged mode
+ ///< 0 = disabled
+ ///< 1 = enabled
+ OUT CPU_LOGICAL_ID LogicalCpuid; ///< The logical CPUID of the node
+ ///<
+ OUT UINT16 HostBiosSrvc1; ///< UINT16 sized general purpose field for use by host BIOS. Scratch space.
+ ///<
+ OUT UINT32 HostBiosSrvc2; ///< UINT32 sized general purpose field for use by host BIOS. Scratch space.
+ ///<
+ OUT UINT8 MLoad; ///< Need to be removed
+ ///< Number of devices loading MAA bus
+ ///<
+ OUT UINT8 MaxAsyncLat; ///< Legacy wrapper
+ ///<
+ OUT UINT8 ChbD3Rcvrdly; ///< Legacy wrapper
+ ///<
+ OUT UINT16 ChaMaxRdLat; ///< Max Read Latency (ns) for DCT 0
+ ///<
+ OUT UINT8 ChbD3BcRcvrdly; ///< CHB DIMM 3 Check UINT8 Receiver Enable Delay
+
+ OUT DCT_STRUCT *DctData; ///< Pointed to a dynamically allocated array of DCT_STRUCTs
+ OUT UINT8 DctCount; ///< Number of DCTs per this Die
+ OUT UINT8 Reserved[16]; ///< Reserved
+} DIE_STRUCT;
+
+/**********************************************************************
+ * S3 Support structure
+ **********************************************************************/
+/// AmdInitResume, AmdS3LateRestore, and AmdS3Save param structure
+typedef struct {
+ OUT UINT32 Signature; ///< "ASTR" for AMD Suspend-To-RAM
+ OUT UINT16 Version; ///< S3 Params version number
+ IN OUT UINT32 Flags; ///< Indicates operation
+ IN OUT VOID *NvStorage; ///< Pointer to memory critical save state data
+ IN OUT UINT32 NvStorageSize; ///< Size in bytes of the NvStorage region
+ IN OUT VOID *VolatileStorage; ///< Pointer to remaining AMD save state data
+ IN OUT UINT32 VolatileStorageSize; ///< Size in bytes of the VolatileStorage region
+} AMD_S3_PARAMS;
+
+///===============================================================================
+/// MEM_PARAMETER_STRUCT
+/// This data structure is used to pass wrapper parameters to the memory configuration code
+///
+typedef struct _MEM_PARAMETER_STRUCT {
+
+ // Basic (Return parameters)
+ // (This section contains the outbound parameters from the memory init code)
+
+ OUT BOOLEAN GStatus[GsbEOL]; ///< Global Status bitfield.
+ ///<
+ OUT UINT32 HoleBase; ///< If not zero Base[47:16] (system address) of sub 4GB dram hole for HW remapping.
+ ///<
+ OUT UINT32 Sub4GCacheTop; ///< If not zero, the 32-bit top of cacheable memory.
+ ///<
+ OUT UINT32 Sub1THoleBase; ///< If not zero Base[47:16] (system address) of sub 1TB dram hole.
+ ///<
+ OUT UINT32 SysLimit; ///< Limit[47:16] (system address).
+ ///<
+ OUT DIMM_VOLTAGE DDR3Voltage; ///< Find support voltage and send back to platform BIOS.
+ ///<
+ OUT VDDP_VDDR_VOLTAGE VddpVddrVoltage; ///< For a given configuration, request is made to change the VDDP/VDDR
+ ///< voltage in platform BIOS via AgesaHookBeforeDramInit callout and
+ ///< MEM_PARAMETER_STRUCT.VddpVddrVoltage.Voltage parameter if
+ ///< MEM_PARAMETER_STRUCT.VddpVddrVoltage.IsValid is TRUE. The
+ ///< MEM_PARAMETER_STRUCT.VddpVddrVoltage.Voltage is defined in
+ ///< MEMORY_PHY_VOLTAGE
+ OUT UINT8 ExternalVrefValue; ///< Target reference voltage for external Vref for 2D training
+ ///<
+ OUT struct _MEM_DATA_STRUCT *MemData; ///< Access to global memory init data.
+
+ // Advanced (Optional parameters)
+ // Optional (all defaults values will be initialized by the
+ // 'AmdMemInitDataStructDef' based on AMD defaults. It is up
+ // to the IBV/OEM to change the defaults after initialization
+ // but prior to the main entry to the memory code):
+
+ // Memory Map/Mgt.
+
+ IN UINT16 BottomIo; ///< Bottom of 32-bit IO space (8-bits).
+ ///< NV_BOTTOM_IO[7:0]=Addr[31:24]
+ ///<
+ IN BOOLEAN MemHoleRemapping; ///< Memory Hole Remapping (1-bit).
+ ///< FALSE = disable
+ ///< TRUE = enable
+ ///<
+ IN BOOLEAN LimitMemoryToBelow1Tb;///< Limit memory address space to below 1 TB
+ ///< FALSE = disable
+ ///< TRUE = enable
+ ///<
+ ///< @BldCfgItem{BLDCFG_LIMIT_MEMORY_TO_BELOW_1TB}
+
+
+ // Dram Timing
+
+ IN UINT32 UserTimingMode; ///< User Memclock Mode.
+ ///< @BldCfgItem{BLDCFG_TIMING_MODE_SELECT}
+
+ IN UINT32 MemClockValue; ///< Memory Clock Value.
+ ///< @BldCfgItem{BLDCFG_MEMORY_CLOCK_SELECT}
+
+
+ // Dram Configuration
+
+ IN BOOLEAN EnableBankIntlv; ///< Dram Bank (chip-select) Interleaving (1-bit).
+ ///< - FALSE =disable (default)
+ ///< - TRUE = enable
+ ///<
+ ///< @BldCfgItem{BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING}
+
+ IN BOOLEAN EnableNodeIntlv; ///< Node Memory Interleaving (1-bit).
+ ///< - FALSE = disable (default)
+ ///< - TRUE = enable
+ ///<
+ ///< @BldCfgItem{BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING}
+
+ IN BOOLEAN EnableChannelIntlv; ///< Channel Interleaving (1-bit).
+ ///< - FALSE = disable (default)
+ ///< - TRUE = enable
+ ///<
+ ///< @BldCfgItem{BLDCFG_MEMORY_CHANNEL_INTERLEAVING}
+ // DllPDBypassMode
+
+ IN BOOLEAN EnableDllPDBypassMode;///< Enable low-power DDR phy operation. This feature is used for low-power
+ ///< solder-down DRAM motherboard designs with route matched CK/DQS/DQ signals.
+ ///< It limits maximim achieveable DDR rates on the platform and should not be
+ ///< enabled for systems requiring high DDR rate operation and/or DIMM-based systems.
+ ///< - FALSE = disable
+ ///< - TRUE = enable (default)
+ ///<
+ ///< @BldCfgItem{BLDCFG_DDR_PHY_DLL_BYPASS_MODE}
+ // ECC
+
+ IN BOOLEAN EnableEccFeature; ///< enable ECC error to go into MCE.
+ ///< - FALSE = disable (default)
+ ///< - TRUE = enable
+ ///<
+ ///< @BldCfgItem{BLDCFG_ENABLE_ECC_FEATURE}
+ // Dram Power
+
+ IN BOOLEAN EnablePowerDown; ///< CKE based power down mode (1-bit).
+ ///< - FALSE =disable (default)
+ ///< - TRUE =enable
+ ///<
+ ///< @BldCfgItem{BLDCFG_MEMORY_POWER_DOWN}
+
+ // Online Spare
+
+ IN BOOLEAN EnableOnLineSpareCtl; ///< Chip Select Spare Control bit 0.
+ ///< - FALSE = disable Spare (default)
+ ///< - TRUE = enable Spare
+ ///<
+ ///< @BldCfgItem{BLDCFG_ONLINE_SPARE}
+
+ IN UINT8 *TableBasedAlterations; ///< Desired modifications to register settings.
+
+ IN PSO_TABLE *PlatformMemoryConfiguration;
+ ///< A table that contains platform specific settings.
+ ///< For example, MemClk routing, the number of DIMM slots per channel, ....
+ ///< AGESA initializes this pointer with DefaultPlatformMemoryConfiguration that
+ ///< contains default conservative settings. Platform BIOS can either tweak
+ ///< DefaultPlatformMemoryConfiguration or reassign this pointer to its own table.
+ ///<
+ IN BOOLEAN EnableParity; ///< Parity control.
+ ///< - TRUE = enable
+ ///< - FALSE = disable (default)
+ ///<
+ ///< @BldCfgItem{BLDCFG_MEMORY_PARITY_ENABLE}
+
+ IN BOOLEAN EnableBankSwizzle; ///< BankSwizzle control.
+ ///< - FALSE = disable
+ ///< - TRUE = enable (default)
+ ///<
+ ///< @BldCfgItem{BLDCFG_BANK_SWIZZLE}
+
+ ///<
+
+ IN BOOLEAN EnableMemClr; ///< Memory Clear functionality control.
+ ///< - FALSE = disable
+ ///< - TRUE = enable (default)
+ ///<
+
+ // Uma Configuration
+
+ IN UMA_MODE UmaMode; ///< Uma Mode
+ ///< 0 = None
+ ///< 1 = Specified
+ ///< 2 = Auto
+ IN OUT UINT32 UmaSize; ///< The size of shared graphics dram (16-bits)
+ ///< NV_UMA_Size[31:0]=Addr[47:16]
+ ///<
+ OUT UINT32 UmaBase; ///< The allocated Uma base address (32-bits)
+ ///< NV_UMA_Base[31:0]=Addr[47:16]
+ ///<
+
+ /// Memory Restore Feature
+
+ IN BOOLEAN MemRestoreCtl; ///< Memory context restore control
+ ///< FALSE = perform memory init as normal (AMD default)
+ ///< TRUE = restore memory context and skip training. This requires
+ ///< MemContext is valid before AmdInitPost
+ ///<
+ IN BOOLEAN SaveMemContextCtl; ///< Control switch to save memory context at the end of MemAuto
+ ///< TRUE = AGESA will setup MemContext block before exit AmdInitPost
+ ///< FALSE = AGESA will not setup MemContext block. Platform is
+ ///< expected to call S3Save later in POST if it wants to
+ ///< use memory context restore feature.
+ ///<
+ IN OUT AMD_S3_PARAMS MemContext; ///< Memory context block describes the data that platform needs to
+ ///< save and restore for memory context restore feature to work.
+ ///< It uses the subset of S3Save block to save/restore. Hence platform
+ ///< may save only S3 block and uses it for both S3 resume and
+ ///< memory context restore.
+ ///< - If MemRestoreCtl is TRUE, platform needs to pass in MemContext
+ ///< before AmdInitPost.
+ ///< - If SaveMemContextCtl is TRUE, platform needs to save MemContext
+ ///< right after AmdInitPost.
+ ///<
+ IN BOOLEAN IsCapsuleMode; ///< Capsule reboot control
+ ///< FALSE = This is not a capsule reboot.
+ ///< TRUE = This is a capsule reboot.
+ ///<
+ IN BOOLEAN ExternalVrefCtl; ///< Control the use of external Vref
+ ///< TRUE = AGESA will use the function defined in "AGESA_EXTERNAL_VREF_CHANGE" in function list
+ ///< to change the vref
+ ///< FALSE = AGESA will will use the internal vref control.
+ ///< @BldCfgItem{BLDCFG_ENABLE_EXTERNAL_VREF_FEATURE}
+ ///<
+ IN FORCE_TRAIN_MODE ForceTrainMode; ///< Training Mode
+ ///< 0 = Force 1D Training for all configurations
+ ///< 1 = Force 2D Training for all configurations
+ ///< 2 = Auto - AGESA will control 1D or 2D
+ IN TECHNOLOGY_TYPE DimmTypeUsedInMixedConfig; ///< Select the preferred technology type that AGESA will enable
+ ///< when it is mixed with other technology types.
+ ///< DDR3_TECHNOLOGY = Use DDR3 DIMMs
+ ///< GDDR5_TECHNOLOGY = Use GDDR5 DIMMs
+ ///< UNSUPPORTED_TECHNOLOGY = Exit with fatal error when DDR3 and GDDR5 DIMMs
+ ///< are installed on the same system
+ ///< @BldCfgItem{BLDCFG_DIMM_TYPE_USED_IN_MIXED_CONFIG}
+ IN BOOLEAN AmpEnable; ///< AMP functionality control
+ ///< TRUE = Enable, platform BIOS requests to enable memory overclocking function, and AGESA
+ ///< detects if memory is capable of it
+ ///< FALSE = Disable, there is no request to enable memory overclocking function
+ ///<
+ IN BOOLEAN AmpWarningMsgEnable; ///< AMP warning messages control
+ ///< TRUE = Enable to log the warning messages of AMP
+ ///< FALSE = Disable
+ ///<
+ OUT AMP_STATUS AmpStatus; ///< AMP status allows platform BIOS to check which voltage or warning message it should
+ ///< use/apply.
+ ///<
+ ///< AmpVoltageValid :
+ ///< TRUE - AGESA does enable AMP function, so use AmpVoltage for voltage adjustment
+ ///< FALSE - AGESA does not enable AMP function, so use DDR3Voltage for voltage adjustment
+ ///<
+ ///< AmpSupportDetectedButNotEnabled :
+ ///< TRUE - Display warning message of "AMP support detected but not enabled"
+ ///< FALSE - No corresponding message should be displayed
+ ///<
+ ///< AmpSelectedButNotEnabled :
+ ///< TRUE - Display warning message of "AMP selected but not enabled"
+ ///< FALSE - No corresponding message should be displayed
+ ///<
+ ///< Note that both of warning message status reports are controlled by AmpWarningMsgEnable
+ ///<
+ OUT AMP_DIMM_VOLTAGE AmpVoltage; ///< AMP voltage which will be sent back to platform BIOS, and
+ ///< the value in AmpVoltage is valid only if AmpStatus is TRUE returned
+ IN BOOLEAN DataEyeEn; ///< Get 2D training data eye
+ ///< TRUE = Enable to get the 2D data eye
+ ///< FALSE = The 2D data eye is not enabled
+ ///< @BldCfgItem{BLDCFG_ENABLE_DATA_EYE}
+ IN BOOLEAN DramDoubleRefreshRate;///< Specify the average time between refresh requests to all DRAM devices.
+ ///< TRUE = 2x refresh rate.
+ ///< FALSE = 1x refresh rate.
+ ///< @BldCfgItem{BLDCFG_DRAM_DOUBLE_REFRESH_RATE}
+ IN PMU_TRAIN_MODE PmuTrainMode; ///< PMU Training Mode
+ ///< @BldCfgItem{BLDCFG_PMU_TRAINING_MODE}
+ ///< 0 = PMU 1D Training only for all configurations
+ ///< 1 = PMU 1D and 2D Training read only for all configurations
+ ///< 2 = PMU 1D and 2D Training for all configurations
+ ///< 3 = AGESA control type of training depend on configurations
+} MEM_PARAMETER_STRUCT;
+
+
+///
+/// Function definition.
+/// This data structure passes function pointers to the memory configuration code.
+/// The wrapper can use this structure with customized versions.
+///
+typedef struct _MEM_FUNCTION_STRUCT {
+
+ // PUBLIC required Internal functions
+
+ IN OUT BOOLEAN (*amdMemGetPsCfgU) ( VOID *pMemData); ///< Proc for Unbuffered DIMMs, platform specific
+ IN OUT BOOLEAN (*amdMemGetPsCfgR) (VOID *pMemData); ///< Proc for Registered DIMMs, platform specific
+
+ // PUBLIC optional functions
+
+ IN OUT VOID (*amdMemEccInit) (VOID *pMemData); ///< NB proc for ECC feature
+ IN OUT VOID (*amdMemChipSelectInterleaveInit) (VOID *pMemData); ///< NB proc for CS interleave feature
+ IN OUT VOID (*amdMemDctInterleavingInit) (VOID *pMemData); ///< NB proc for Channel interleave feature
+ IN OUT VOID (*amdMemMctInterleavingInit) (VOID *pMemData); ///< NB proc for Node interleave feature
+ IN OUT VOID (*amdMemParallelTraining) (VOID *pMemData); ///< NB proc for parallel training feature
+ IN OUT VOID (*amdMemEarlySampleSupport) (VOID *pMemData); ///< NB code for early sample support feature
+ IN OUT VOID (*amdMemMultiPartInitSupport) (VOID *pMemData); ///< NB code for 'multi-part'
+ IN OUT VOID (*amdMemOnlineSpareSupport) (VOID *pMemData); ///< NB code for On-Line Spare feature
+ IN OUT VOID (*amdMemUDimmInit) (VOID *pMemData); ///< NB code for UDIMMs
+ IN OUT VOID (*amdMemRDimmInit) (VOID *pMemData); ///< NB code for RDIMMs
+ IN OUT VOID (*amdMemLrDimmInit) (VOID *pMemData); ///< NB code for LRDIMMs
+ IN OUT UINT32 Reserved[100]; ///< Reserved for later function definition
+} MEM_FUNCTION_STRUCT;
+
+///
+/// Socket Structure
+///
+///
+typedef struct _MEM_SOCKET_STRUCT {
+ OUT VOID *ChannelPtr[MAX_CHANNELS_PER_SOCKET]; ///< Pointers to each channels training data
+
+ OUT VOID *TimingsPtr[MAX_CHANNELS_PER_SOCKET]; ///< Pointers to each channels timing data
+} MEM_SOCKET_STRUCT;
+
+///
+/// Contains all data relevant to Memory Initialization.
+///
+typedef struct _MEM_DATA_STRUCT {
+ IN AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header
+
+ IN MEM_PARAMETER_STRUCT *ParameterListPtr; ///< List of input Parameters
+
+ OUT MEM_FUNCTION_STRUCT FunctionList; ///< List of function Pointers
+
+ IN OUT AGESA_STATUS (*GetPlatformCfg[MAX_PLATFORM_TYPES]) (struct _MEM_DATA_STRUCT *MemData, UINT8 SocketID, CH_DEF_STRUCT *CurrentChannel); ///< look-up platform info
+
+ IN OUT BOOLEAN (*ErrorHandling)(struct _DIE_STRUCT *MCTPtr, UINT8 DCT, UINT16 ChipSelMask, AMD_CONFIG_PARAMS *StdHeader); ///< Error Handling
+
+
+ OUT MEM_SOCKET_STRUCT SocketList[MAX_SOCKETS_SUPPORTED]; ///< Socket list for memory code.
+ ///< SocketList is a shortcut for IBVs to retrieve training
+ ///< and timing data for each channel indexed by socket/channel,
+ ///< eliminating their need to parse die/dct/channel etc.
+ ///< It contains pointers to the populated data structures for
+ ///< each channel and skips the channel structures that are
+ ///< unpopulated. In the case of channels sharing the same DCT,
+ ///< the pTimings pointers will point to the same DCT Timing data.
+
+ OUT DIE_STRUCT *DiesPerSystem; ///< Pointed to an array of DIE_STRUCTs
+ OUT UINT8 DieCount; ///< Number of MCTs in the system.
+
+ IN SPD_DEF_STRUCT *SpdDataStructure; ///< Pointer to SPD Data structure
+
+ IN OUT struct _PLATFORM_CONFIGURATION *PlatFormConfig; ///< Platform profile/build option config structure
+
+ IN OUT BOOLEAN IsFlowControlSupported; ///< Indicates if flow control is supported
+
+ OUT UINT32 TscRate; ///< The rate at which the TSC increments in megahertz.
+ IN BOOLEAN PhyReceiverLowPower; ///< Force PHY receiver in low power.
+ ///< TRUE = PHY receiver low power
+ ///< FALSE = PHY receiver high power
+} MEM_DATA_STRUCT;
+
+///
+/// Uma Structure
+///
+///
+typedef struct _UMA_INFO {
+ OUT UINT64 UmaBase; ///< UmaBase[63:0] = Addr[63:0]
+ OUT UINT32 UmaSize; ///< UmaSize[31:0] = Addr[31:0]
+ OUT UINT32 UmaAttributes; ///< Indicate the attribute of Uma
+ OUT UINT8 UmaMode; ///< Indicate the mode of Uma
+ OUT UINT16 MemClock; ///< Indicate memory running speed in MHz
+ OUT UINT8 MemType; ///< Indicate the DRAM technology type that is being used
+ OUT UINT8 Reserved[2]; ///< Reserved for future usage
+} UMA_INFO;
+
+
+/// Bitfield for ID
+typedef struct {
+ OUT UINT16 SocketId:8; ///< Socket ID
+ OUT UINT16 ModuleId:8; ///< Module ID
+} ID_FIELD;
+///
+/// Union for ID of socket and module that will be passed out in call out
+///
+typedef union {
+ OUT ID_FIELD IdField; ///< Bitfield for ID
+ OUT UINT16 IdInformation; ///< ID information for call out
+} ID_INFO;
+
+// AGESA MEMORY ERRORS
+
+// AGESA_SUCCESS memory events
+#define MEM_EVENT_CAPSULE_IN_EFFECT 0x04013600ul ///< Capsule is in effect
+#define MEM_EVENT_CONTEXT_RESTORE_IN_EFFECT 0x04023600ul ///< Context restore is in effect
+
+// AGESA_ALERT Memory Errors
+#define MEM_ALERT_USER_TMG_MODE_OVERRULED 0x04010000ul ///< TIMING_MODE_SPECIFIC is requested but
+ ///< cannot be applied to current configurations.
+#define MEM_ALERT_ORG_MISMATCH_DIMM 0x04010100ul ///< DIMM organization miss-match
+#define MEM_ALERT_BK_INT_DIS 0x04010200ul ///< Bank interleaving disable for internal issue
+
+// AGESA_ERROR Memory Errors
+#define MEM_ERROR_NO_DQS_POS_RD_WINDOW 0x04010300ul ///< No DQS Position window for RD DQS
+#define MEM_ERROR_SMALL_DQS_POS_RD_WINDOW 0x04020300ul ///< Small DQS Position window for RD DQS
+#define MEM_ERROR_NO_DQS_POS_WR_WINDOW 0x04030300ul ///< No DQS Position window for WR DQS
+#define MEM_ERROR_SMALL_DQS_POS_WR_WINDOW 0x04040300ul ///< Small DQS Position window for WR DQS
+#define MEM_ERROR_DIMM_SPARING_NOT_ENABLED 0x04010500ul ///< DIMM sparing has not been enabled for an internal issues
+#define MEM_ERROR_RCVR_EN_VALUE_TOO_LARGE 0x04050300ul ///< Receive Enable value is too large
+#define MEM_ERROR_RCVR_EN_NO_PASSING_WINDOW 0x04060300ul ///< There is no DQS receiver enable window
+#define MEM_ERROR_DRAM_ENABLED_TIME_OUT 0x04010600ul ///< Time out when polling DramEnabled bit
+#define MEM_ERROR_DCT_ACCESS_DONE_TIME_OUT 0x04010700ul ///< Time out when polling DctAccessDone bit
+#define MEM_ERROR_SEND_CTRL_WORD_TIME_OUT 0x04010800ul ///< Time out when polling SendCtrlWord bit
+#define MEM_ERROR_PREF_DRAM_TRAIN_MODE_TIME_OUT 0x04010900ul ///< Time out when polling PrefDramTrainMode bit
+#define MEM_ERROR_ENTER_SELF_REF_TIME_OUT 0x04010A00ul ///< Time out when polling EnterSelfRef bit
+#define MEM_ERROR_FREQ_CHG_IN_PROG_TIME_OUT 0x04010B00ul ///< Time out when polling FreqChgInProg bit
+#define MEM_ERROR_EXIT_SELF_REF_TIME_OUT 0x04020A00ul ///< Time out when polling ExitSelfRef bit
+#define MEM_ERROR_SEND_MRS_CMD_TIME_OUT 0x04010C00ul ///< Time out when polling SendMrsCmd bit
+#define MEM_ERROR_SEND_ZQ_CMD_TIME_OUT 0x04010D00ul ///< Time out when polling SendZQCmd bit
+#define MEM_ERROR_DCT_EXTRA_ACCESS_DONE_TIME_OUT 0x04010E00ul ///< Time out when polling DctExtraAccessDone bit
+#define MEM_ERROR_MEM_CLR_BUSY_TIME_OUT 0x04010F00ul ///< Time out when polling MemClrBusy bit
+#define MEM_ERROR_MEM_CLEARED_TIME_OUT 0x04020F00ul ///< Time out when polling MemCleared bit
+#define MEM_ERROR_FLUSH_WR_TIME_OUT 0x04011000ul ///< Time out when polling FlushWr bit
+#define MEM_ERROR_NBPSTATE_TRANSITION_TIME_OUT 0x04012600ul ///< Time out when polling CurNBPstate bit
+#define MEM_ERROR_MAX_LAT_NO_WINDOW 0x04070300ul ///< Fail to find pass during Max Rd Latency training
+#define MEM_ERROR_PARALLEL_TRAINING_LAUNCH_FAIL 0x04080300ul ///< Fail to launch training code on an AP
+#define MEM_ERROR_PARALLEL_TRAINING_TIME_OUT 0x04090300ul ///< Fail to finish parallel training
+#define MEM_ERROR_NO_ADDRESS_MAPPING 0x04011100ul ///< No address mapping found for a dimm
+#define MEM_ERROR_RCVR_EN_NO_PASSING_WINDOW_EQUAL_LIMIT 0x040A0300ul ///< There is no DQS receiver enable window and the value is equal to the largest value
+#define MEM_ERROR_RCVR_EN_VALUE_TOO_LARGE_LIMIT_LESS_ONE 0x040B0300ul ///< Receive Enable value is too large and is 1 less than limit
+#define MEM_ERROR_CHECKSUM_NV_SPDCHK_RESTRT_ERROR 0x04011200ul ///< SPD Checksum error for NV_SPDCHK_RESTRT
+#define MEM_ERROR_NO_CHIPSELECT 0x04011300ul ///< No chipselects found
+#define MEM_ERROR_UNSUPPORTED_333MHZ_UDIMM 0x04011500ul ///< Unbuffered dimm is not supported at 333MHz
+#define MEM_ERROR_WL_PRE_OUT_OF_RANGE 0x040C0300ul ///< Returned PRE value during write levelizzation was out of range
+#define MEM_ERROR_NO_2D_RDDQS_WINDOW 0x040D0300ul ///< No 2D RdDqs Window
+#define MEM_ERROR_NO_2D_RDDQS_HEIGHT 0x040E0300ul ///< No 2D RdDqs Height
+#define MEM_ERROR_2D_DQS_ERROR 0x040F0300ul ///< 2d RdDqs Error
+#define MEM_ERROR_INVALID_2D_RDDQS_VALUE 0x04022400ul ///< 2d RdDqs invalid value found
+#define MEM_ERROR_2D_DQS_VREF_MARGIN_ERROR 0x04023400ul ///< 2d RdDqs Vef Margin error found
+#define MEM_ERROR_LR_IBT_NOT_FOUND 0x04013500ul ///< No LR dimm IBT value is found
+#define MEM_ERROR_MR0_NOT_FOUND 0x04023500ul ///< No MR0 value is found
+#define MEM_ERROR_ODT_PATTERN_NOT_FOUND 0x04033500ul ///< No odt pattern value is found
+#define MEM_ERROR_RC2_IBT_NOT_FOUND 0x04043500ul ///< No RC2 IBT value is found
+#define MEM_ERROR_RC10_OP_SPEED_NOT_FOUND 0x04053500ul ///< No RC10 op speed is found
+#define MEM_ERROR_RTT_NOT_FOUND 0x04063500ul ///< No RTT value is found
+#define MEM_ERROR_P2D_NOT_FOUND 0x04073500ul ///< No 2D training config value is found
+#define MEM_ERROR_SAO_NOT_FOUND 0x04083500ul ///< No slow access mode, Address timing and Output driver compensation value is found
+#define MEM_ERROR_CLK_DIS_MAP_NOT_FOUND 0x04093500ul ///< No CLK disable map is found
+#define MEM_ERROR_CKE_TRI_MAP_NOT_FOUND 0x040A3500ul ///< No CKE tristate map is found
+#define MEM_ERROR_ODT_TRI_MAP_NOT_FOUND 0x040B3500ul ///< No ODT tristate map is found
+#define MEM_ERROR_CS_TRI_MAP_NOT_FOUND 0x040C3500ul ///< No CS tristate map is found
+#define MEM_ERROR_TRAINING_SEED_NOT_FOUND 0x040D3500ul ///< No training seed is found
+#define MEM_ERROR_NO_2D_WRDAT_WINDOW 0x040D0400ul ///< No 2D WrDat Window
+#define MEM_ERROR_NO_2D_WRDAT_HEIGHT 0x040E0400ul ///< No 2D WrDat Height
+#define MEM_ERROR_2D_WRDAT_ERROR 0x040F0400ul ///< 2d WrDat Error
+#define MEM_ERROR_INVALID_2D_WRDAT_VALUE 0x04100400ul ///< 2d WrDat invalid value found
+#define MEM_ERROR_2D_WRDAT_VREF_MARGIN_ERROR 0x04110400ul ///< 2d WrDat Vef Margin error found
+#define MEM_ERROR_PMU_TRAINING 0x04120400ul ///< Fail PMU training.
+
+// AGESA_WARNING Memory Errors
+#define MEM_WARNING_UNSUPPORTED_QRDIMM 0x04011600ul ///< QR DIMMs detected but not supported
+#define MEM_WARNING_UNSUPPORTED_UDIMM 0x04021600ul ///< U DIMMs detected but not supported
+#define MEM_WARNING_UNSUPPORTED_SODIMM 0x04031600ul ///< SO-DIMMs detected but not supported
+#define MEM_WARNING_UNSUPPORTED_X4DIMM 0x04041600ul ///< x4 DIMMs detected but not supported
+#define MEM_WARNING_UNSUPPORTED_RDIMM 0x04051600ul ///< R DIMMs detected but not supported
+#define MEM_WARNING_UNSUPPORTED_LRDIMM 0x04061600ul ///< LR DIMMs detected but not supported
+#define MEM_WARNING_EMP_NOT_SUPPORTED 0x04011700ul ///< Processor is not capable for EMP
+#define MEM_WARNING_EMP_CONFLICT 0x04021700ul ///< EMP cannot be enabled if channel interleaving,
+#define MEM_WARNING_EMP_NOT_ENABLED 0x04031700ul ///< Memory size is not power of two.
+#define MEM_WARNING_ECC_DIS 0x04041700ul ///< ECC has been disabled as a result of an internal issue
+#define MEM_WARNING_PERFORMANCE_ENABLED_BATTERY_LIFE_PREFERRED 0x04011800ul ///< Performance has been enabled, but battery life is preferred.
+ ///< bank interleaving, or bank swizzle is enabled.
+#define MEM_WARNING_NO_SPDTRC_FOUND 0x04011900ul ///< No Trc timing value found in SPD of a dimm.
+#define MEM_WARNING_NODE_INTERLEAVING_NOT_ENABLED 0x04012000ul ///< Node Interleaveing Requested, but could not be enabled
+#define MEM_WARNING_CHANNEL_INTERLEAVING_NOT_ENABLED 0x04012100ul ///< Channel Interleaveing Requested, but could not be enabled
+#define MEM_WARNING_BANK_INTERLEAVING_NOT_ENABLED 0x04012200ul ///< Bank Interleaveing Requested, but could not be enabled
+#define MEM_WARNING_VOLTAGE_1_35_NOT_SUPPORTED 0x04012300ul ///< Voltage 1.35 determined, but could not be supported
+#define MEM_WARNING_INITIAL_DDR3VOLT_NONZERO 0x04012400ul ///< DDR3 voltage initial value is not 0
+#define MEM_WARNING_NO_COMMONLY_SUPPORTED_VDDIO 0x04012500ul ///< Cannot find a commonly supported VDDIO
+#define MEM_WARNING_AMP_SUPPORT_DETECTED_BUT_NOT_ENABLED 0x04012900ul ///< AMP support detected but not enabled
+#define MEM_WARNING_AMP_SELECTED_BUT_NOT_ENABLED 0x04022900ul ///< AMP selected but not enabled
+
+// AGESA_FATAL Memory Errors
+#define MEM_ERROR_MINIMUM_MODE 0x04011A00ul ///< Running in minimum mode
+#define MEM_ERROR_MODULE_TYPE_MISMATCH_DIMM 0x04011B00ul ///< DIMM modules are miss-matched
+#define MEM_ERROR_NO_DIMM_FOUND_ON_SYSTEM 0x04011C00ul ///< No DIMMs have been found
+#define MEM_ERROR_MISMATCH_DIMM_CLOCKS 0x04011D00ul ///< DIMM clocks miss-matched
+#define MEM_ERROR_NO_CYC_TIME 0x04011E00ul ///< No cycle time found
+#define MEM_ERROR_HEAP_ALLOCATE_DYN_STORING_OF_TRAINED_TIMINGS 0x04011F00ul ///< Heap allocation error with dynamic storing of trained timings
+#define MEM_ERROR_HEAP_ALLOCATE_FOR_DCT_STRUCT_AND_CH_DEF_STRUCTs 0x04021F00ul ///< Heap allocation error for DCT_STRUCT and CH_DEF_STRUCT
+#define MEM_ERROR_HEAP_ALLOCATE_FOR_REMOTE_TRAINING_ENV 0x04031F00ul ///< Heap allocation error with REMOTE_TRAINING_ENV
+#define MEM_ERROR_HEAP_ALLOCATE_FOR_SPD 0x04041F00ul ///< Heap allocation error for SPD data
+#define MEM_ERROR_HEAP_ALLOCATE_FOR_RECEIVED_DATA 0x04051F00ul ///< Heap allocation error for RECEIVED_DATA during parallel training
+#define MEM_ERROR_HEAP_ALLOCATE_FOR_S3_SPECIAL_CASE_REGISTERS 0x04061F00ul ///< Heap allocation error for S3 "SPECIAL_CASE_REGISTER"
+#define MEM_ERROR_HEAP_ALLOCATE_FOR_TRAINING_DATA 0x04071F00ul ///< Heap allocation error for Training Data
+#define MEM_ERROR_HEAP_ALLOCATE_FOR_IDENTIFY_DIMM_MEM_NB_BLOCK 0x04081F00ul ///< Heap allocation error for DIMM Identify "MEM_NB_BLOCK
+#define MEM_ERROR_NO_CONSTRUCTOR_FOR_IDENTIFY_DIMM 0x04022300ul ///< No Constructor for DIMM Identify
+#define MEM_ERROR_VDDIO_UNSUPPORTED 0x04022500ul ///< VDDIO of the dimms on the board is not supported
+#define MEM_ERROR_HEAP_ALLOCATE_FOR_2D 0x040B1F00ul ///< Heap allocation error for 2D training data
+#define MEM_ERROR_HEAP_DEALLOCATE_FOR_2D 0x040C1F00ul ///< Heap de-allocation error for 2D training data
+#define MEM_ERROR_HEAP_ALLOCATE_FOR_DATAEYE 0x040F1F00ul ///< Heap allocation error for DATAEYE Storage
+#define MEM_ERROR_HEAP_DEALLOCATE_FOR_DATAEYE 0x040E1F00ul ///< Heap de-allocation error for DATAEYE Storage
+#define MEM_ERROR_HEAP_ALLOCATE_FOR_PMU_SRAM_MSG_BLOCK 0x04101F00ul ///< Heap allocation error for PMU SRAM Message Block Storage
+#define MEM_ERROR_HEAP_DEALLOCATE_FOR_PMU_SRAM_MSG_BLOCK 0x04111F00ul ///< Heap de-allocation error for PMU SRAM Message Block Storage
+#define MEM_ERROR_HEAP_LOCATE_FOR_PMU_SRAM_MSG_BLOCK 0x04121F00ul ///< Heap location error for PMU SRAM Message Block Storage
+
+// AGESA_CRITICAL Memory Errors
+#define MEM_ERROR_HEAP_ALLOCATE_FOR_DMI_TABLE_DDR3 0x04091F00ul ///< Heap allocation error for DMI table for DDR3
+#define MEM_ERROR_HEAP_ALLOCATE_FOR_DMI_TABLE_DDR2 0x040A1F00ul ///< Heap allocation error for DMI table for DDR2
+#define MEM_ERROR_UNSUPPORTED_DIMM_CONFIG 0x04011400ul ///< Dimm population is not supported
+#define MEM_ERROR_HEAP_ALLOCATE_FOR_CRAT_MEM_AFFINITY 0x040D1F00ul ///< Heap allocation error for CRAT memory affinity info
+
+
+
+/*----------------------------------------------------------------------------
+ *
+ * END OF MEMORY-SPECIFIC DATA STRUCTURES
+ *
+ *----------------------------------------------------------------------------
+ */
+
+
+
+
+/*----------------------------------------------------------------------------
+ *
+ * CPU RELATED DEFINITIONS
+ *
+ *----------------------------------------------------------------------------
+ */
+
+// CPU Event definitions.
+
+// Defines used to filter CPU events based on functional blocks
+#define CPU_EVENT_PM_EVENT_MASK 0xFF00FF00ul
+#define CPU_EVENT_PM_EVENT_CLASS 0x08000400ul
+
+//================================================================
+// CPU General events
+// Heap allocation (AppFunction = 01h)
+#define CPU_ERROR_HEAP_BUFFER_IS_NOT_PRESENT 0x08000100ul
+#define CPU_ERROR_HEAP_IS_ALREADY_INITIALIZED 0x08010100ul
+#define CPU_ERROR_HEAP_IS_FULL 0x08020100ul
+#define CPU_ERROR_HEAP_BUFFER_HANDLE_IS_ALREADY_USED 0x08030100ul
+#define CPU_ERROR_HEAP_BUFFER_HANDLE_IS_NOT_PRESENT 0x08040100ul
+// BrandId (AppFunction = 02h)
+#define CPU_ERROR_BRANDID_HEAP_NOT_AVAILABLE 0x08000200ul
+// Micro code patch (AppFunction = 03h)
+#define CPU_ERROR_MICRO_CODE_PATCH_IS_NOT_LOADED 0x08000300ul
+// Power management (AppFunction = 04h)
+#define CPU_EVENT_PM_PSTATE_OVERCURRENT 0x08000400ul
+#define CPU_EVENT_PM_ALL_PSTATE_OVERCURRENT 0x08010400ul
+#define CPU_ERROR_PSTATE_HEAP_NOT_AVAILABLE 0x08020400ul
+#define CPU_ERROR_PM_NB_PSTATE_MISMATCH 0x08030400ul
+#define CPU_ERROR_PM_ALL_PSTATE_OVER_FREQUENCY_LIMIT 0x08040400ul
+#define CPU_EVENT_PM_PSTATE_FREQUENCY_LIMIT 0x08050400ul
+// Other CPU events (AppFunction = 05h)
+#define CPU_EVENT_BIST_ERROR 0x08000500ul
+#define CPU_EVENT_UNKNOWN_PROCESSOR_FAMILY 0x08010500ul
+#define CPU_EVENT_STACK_REENTRY 0x08020500ul
+#define CPU_EVENT_CORE_NOT_IDENTIFIED 0x08030500ul
+
+//=================================================================
+// CPU Feature events
+// Execution cache (AppFunction = 21h)
+// AGESA_CACHE_SIZE_REDUCED 2101
+// AGESA_CACHE_REGIONS_ACROSS_1MB 2102
+// AGESA_CACHE_REGIONS_ACROSS_4GB 2103
+// AGESA_REGION_NOT_ALIGNED_ON_BOUNDARY 2104
+// AGESA_CACHE_START_ADDRESS_LESS_D0000 2105
+// AGESA_THREE_CACHE_REGIONS_ABOVE_1MB 2106
+// AGESA_DEALLOCATE_CACHE_REGIONS 2107
+#define CPU_EVENT_EXECUTION_CACHE_ALLOCATION_ERROR 0x08002100ul
+// Core Leveling (AppFunction = 22h)
+#define CPU_WARNING_ADJUSTED_LEVELING_MODE 0x08002200ul
+// SCS initialization (AppFunction = 24h)
+// AGESA_SCS_HEAP_ENTRY_MISSING 2401
+// AGESA_SCS_BUFFER_EMPTY 2402
+// AGESA_SCS_WEIGHTS_MISMATCH 2403
+#define CPU_EVENT_SCS_INITIALIZATION_ERROR 0x08002400ul
+
+// CPU Build Configuration structures and definitions
+
+/// Build Configuration structure for BLDCFG_AP_MTRR_SETTINGS
+typedef struct {
+ IN UINT32 MsrAddr; ///< Fixed-Sized MTRR address
+ IN UINT64 MsrData; ///< MTRR Settings
+} AP_MTRR_SETTINGS;
+
+#define AMD_AP_MTRR_FIX64k_00000 0x00000250ul
+#define AMD_AP_MTRR_FIX16k_80000 0x00000258ul
+#define AMD_AP_MTRR_FIX16k_A0000 0x00000259ul
+#define AMD_AP_MTRR_FIX4k_C0000 0x00000268ul
+#define AMD_AP_MTRR_FIX4k_C8000 0x00000269ul
+#define AMD_AP_MTRR_FIX4k_D0000 0x0000026Aul
+#define AMD_AP_MTRR_FIX4k_D8000 0x0000026Bul
+#define AMD_AP_MTRR_FIX4k_E0000 0x0000026Cul
+#define AMD_AP_MTRR_FIX4k_E8000 0x0000026Dul
+#define AMD_AP_MTRR_FIX4k_F0000 0x0000026Eul
+#define AMD_AP_MTRR_FIX4k_F8000 0x0000026Ful
+#define CPU_LIST_TERMINAL 0xFFFFFFFFul
+
+/// Data structure for the Mapping Item between Unified ID for IDS Setup Option
+/// and the option value.
+///
+typedef struct {
+ IN UINT16 IdsNvId; ///< Unified ID for IDS Setup Option.
+ OUT UINT16 IdsNvValue; ///< The value of IDS Setup Option.
+} IDS_NV_ITEM;
+
+/// Data Structure for IDS CallOut Function
+typedef struct {
+ IN AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header
+ IN IDS_NV_ITEM *IdsNvPtr; ///< Memory Pointer of IDS NV Table
+ IN OUT UINTN Reserved; ///< reserved
+} IDS_CALLOUT_STRUCT;
+
+/// Data Structure for Connected Standby Function
+typedef struct {
+ IN AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header
+ IN VOID *CsRestoreTable; ///< Pointer to the CsRestoreTable
+ IN UINT32 CsRestoreTableSize; ///< Size in bytes of the CsRestoreTable
+} CS_CALLOUT_STRUCT;
+
+/************************************************************************
+ *
+ * AGESA interface Call-Out function parameter structures
+ *
+ ***********************************************************************/
+
+/// Parameters structure for interface call-out AgesaAllocateBuffer
+typedef struct {
+ IN OUT AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header
+ IN OUT UINT32 BufferLength; ///< Size of buffer to allocate
+ IN UINT32 BufferHandle; ///< Identifier or name for the buffer
+ OUT VOID *BufferPointer; ///< location of the created buffer
+} AGESA_BUFFER_PARAMS;
+
+/// Parameters structure for interface call-out AgesaHeapRebase
+typedef struct {
+ IN OUT AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header
+ OUT UINTN HeapAddress; ///< The address which heap content will be temporarily stored in
+} AGESA_REBASE_PARAMS;
+
+/// Parameters structure for interface call-out AgesaRunCodeOnAp
+typedef struct {
+ IN OUT AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header
+ IN UINT32 FunctionNumber; ///< Index of the procedure to execute
+ IN VOID *RelatedDataBlock; ///< Location of data structure the procedure will use
+ IN UINT32 RelatedBlockLength; ///< Size of the related data block
+} AP_EXE_PARAMS;
+
+/// Parameters structure for the interface call-out AgesaReadSpd & AgesaReadSpdRecovery
+typedef struct {
+ IN OUT AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header
+ IN UINT8 SocketId; ///< Address of SPD - socket ID
+ IN UINT8 MemChannelId; ///< Address of SPD - memory channel ID
+ IN UINT8 DimmId; ///< Address of SPD - DIMM ID
+ IN OUT UINT8 *Buffer; ///< Location where to place the SPD content
+ IN OUT MEM_DATA_STRUCT *MemData; ///< Location of the MemData structure, for reference
+} AGESA_READ_SPD_PARAMS;
+
+/// VoltageType values
+typedef enum {
+ VTYPE_CPU_VREF, ///< Cpu side Vref
+ VTYPE_DIMM_VREF, ///< Dimm Side Vref
+ VTYPE_VDDIO ///< Vddio
+} VTYPE;
+
+/// Parameters structure for the interface call-out AgesaExternalVoltageAdjust
+typedef struct _VOLTAGE_ADJUST {
+ IN OUT AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header
+ IN OUT MEM_DATA_STRUCT *MemData; ///< Location of the MemData structure, for reference
+ IN VTYPE VoltageType; ///< Which Voltage Type to adjust
+ IN INT8 AdjustValue; ///< Positive/Negative Adjust Value
+} VOLTAGE_ADJUST;
+
+/// Buffer Handles
+typedef enum {
+ AMD_DMI_INFO_BUFFER_HANDLE = 0x000D000, ///< Assign 0x000D000 buffer handle to DMI function
+ AMD_PSTATE_DATA_BUFFER_HANDLE, ///< Assign 0x000D001 buffer handle to Pstate data
+ AMD_PSTATE_ACPI_BUFFER_HANDLE, ///< Assign 0x000D002 buffer handle to Pstate table
+ AMD_BRAND_ID_BUFFER_HANDLE, ///< Assign 0x000D003 buffer handle to Brand ID
+ AMD_ACPI_SLIT_BUFFER_HANDLE, ///< Assign 0x000D004 buffer handle to SLIT function
+ AMD_SRAT_INFO_BUFFER_HANDLE, ///< Assign 0x000D005 buffer handle to SRAT function
+ AMD_WHEA_BUFFER_HANDLE, ///< Assign 0x000D006 buffer handle to WHEA function
+ AMD_S3_INFO_BUFFER_HANDLE, ///< Assign 0x000D007 buffer handle to S3 function
+ AMD_S3_NB_INFO_BUFFER_HANDLE, ///< Assign 0x000D008 buffer handle to S3 NB device info
+ AMD_ACPI_ALIB_BUFFER_HANDLE, ///< Assign 0x000D009 buffer handle to ALIB SSDT table
+ AMD_ACPI_IVRS_BUFFER_HANDLE, ///< Assign 0x000D00A buffer handle to IOMMU IVRS table
+ AMD_CRAT_INFO_BUFFER_HANDLE, ///< Assign 0x000D00B buffer handle to CRAT function
+ AMD_ACPI_CDIT_BUFFER_HANDLE ///< Assign 0x000D00C buffer handle to CDIT function
+} AMD_BUFFER_HANDLE;
+
+
+/************************************************************************
+ *
+ * AGESA interface Call-Out function prototypes
+ *
+ ***********************************************************************/
+
+VOID
+AgesaDoReset (
+ IN UINTN ResetType,
+ IN OUT AMD_CONFIG_PARAMS *StdHeader
+ );
+
+AGESA_STATUS
+AgesaAllocateBuffer (
+ IN UINTN FcnData,
+ IN OUT AGESA_BUFFER_PARAMS *AllocParams
+ );
+
+AGESA_STATUS
+AgesaDeallocateBuffer (
+ IN UINTN FcnData,
+ IN OUT AGESA_BUFFER_PARAMS *DeallocParams
+ );
+
+AGESA_STATUS
+AgesaLocateBuffer (
+ IN UINTN FcnData,
+ IN OUT AGESA_BUFFER_PARAMS *LocateParams
+ );
+
+AGESA_STATUS
+AgesaHeapRebase (
+ IN UINTN FcnData,
+ IN OUT AGESA_REBASE_PARAMS *RebaseParams
+ );
+
+AGESA_STATUS
+AgesaReadSpd (
+ IN UINTN FcnData,
+ IN OUT AGESA_READ_SPD_PARAMS *ReadSpd
+ );
+
+AGESA_STATUS
+AgesaReadSpdRecovery (
+ IN UINTN FcnData,
+ IN OUT AGESA_READ_SPD_PARAMS *ReadSpd
+ );
+
+AGESA_STATUS
+AgesaHookBeforeDramInitRecovery (
+ IN UINTN FcnData,
+ IN OUT MEM_DATA_STRUCT *MemData
+ );
+
+AGESA_STATUS
+AgesaRunFcnOnAp (
+ IN UINTN ApicIdOfCore,
+ IN AP_EXE_PARAMS *LaunchApParams
+ );
+
+AGESA_STATUS
+AgesaHookBeforeDramInit (
+ IN UINTN SocketIdModuleId,
+ IN OUT MEM_DATA_STRUCT *MemData
+ );
+
+AGESA_STATUS
+AgesaHookBeforeDQSTraining (
+ IN UINTN SocketIdModuleId,
+ IN OUT MEM_DATA_STRUCT *MemData
+ );
+
+AGESA_STATUS
+AgesaHookBeforeExitSelfRefresh (
+ IN UINTN FcnData,
+ IN OUT MEM_DATA_STRUCT *MemData
+ );
+
+AGESA_STATUS
+AgesaPcieSlotResetControl (
+ IN UINTN FcnData,
+ IN PCIe_SLOT_RESET_INFO *ResetInfo
+ );
+
+AGESA_STATUS
+AgesaGetVbiosImage (
+ IN UINTN FcnData,
+ IN OUT GFX_VBIOS_IMAGE_INFO *VbiosImageInfo
+ );
+
+AGESA_STATUS
+AgesaFchOemCallout (
+ IN VOID *FchData
+ );
+
+AGESA_STATUS
+AgesaExternal2dTrainVrefChange (
+ IN UINTN SocketIdModuleId,
+ IN OUT MEM_DATA_STRUCT *MemData
+ );
+
+AGESA_STATUS
+AgesaGetIdsData (
+ IN UINTN Data,
+ IN OUT IDS_CALLOUT_STRUCT *IdsCalloutData
+ );
+
+AGESA_STATUS
+AgesaExternalVoltageAdjust (
+ IN UINTN SocketIdModuleId,
+ IN OUT VOLTAGE_ADJUST *AdjustValue
+ );
+
+AGESA_STATUS
+AgesaPublishCsRestorationData (
+ IN UINTN Reserved,
+ IN OUT CS_CALLOUT_STRUCT *AdjustValue
+ );
+
+AGESA_STATUS
+AgesaGnbOemCallout (
+ IN AMD_CONFIG_PARAMS *StdHeader,
+ IN UINTN FcnData,
+ IN OUT VOID *GnbCalloutData
+ );
+
+/************************************************************************
+ *
+ * AGESA interface structure definition and function prototypes
+ *
+ ***********************************************************************/
+
+/**********************************************************************
+ * Platform Configuration: The parameters in boot branch function
+ **********************************************************************/
+
+/// The possible platform control flow settings.
+typedef enum {
+ Nfcm, ///< Normal Flow Control Mode.
+ UmaDr, ///< UMA using Display Refresh flow control.
+ UmaIfcm, ///< UMA using Isochronous Flow Control.
+ Ifcm, ///< Isochronous Flow Control Mode (other than for UMA).
+ Iommu, ///< An IOMMU is in use in the system.
+ MaxControlFlow ///< Not a control flow mode, use for limit checking.
+} PLATFORM_CONTROL_FLOW;
+
+/// The possible hardware prefetch mode settings.
+typedef enum {
+ HARDWARE_PREFETCHER_AUTO, ///< Use the recommended setting for the processor. In most cases, the recommended setting is enabled.
+ DISABLE_HW_PREFETCHER_TRAINING_ON_SOFTWARE_PREFETCHES, ///< Use the recommended setting for the hardware prefetcher, but disable training on software prefetches.
+ DISABLE_L1_PREFETCHER, ///< Use the recommended settings for the hardware prefetcher, but disable L1 prefetching and above.
+ DISABLE_L1_PREFETCHER_AND_HW_PREFETCHER_TRAINING_ON_SOFTWARE_PREFETCHES, ///< (deprecated) - This setting is deprecated; it has the same effect as DISABLE_L1_PREFETCHER
+ DISABLE_L2_STRIDE_PREFETCHER, ///< Use the recommended settings for the hardware prefetcher, but disable the L2 stride prefetcher and above
+ DISABLE_HARDWARE_PREFETCH, ///< Disable hardware prefetching.
+ MAX_HARDWARE_PREFETCH_MODE ///< Not a hardware prefetch mode, use for limit checking.
+} HARDWARE_PREFETCH_MODE;
+
+/// The possible software prefetch mode settings.
+typedef enum {
+ SOFTWARE_PREFETCHES_AUTO, ///< Use the recommended setting for the processor. In most cases, the recommended setting is enabled.
+ DISABLE_SOFTWARE_PREFETCHES, ///< Disable software prefetches (convert software prefetch instructions to NOP).
+ MAX_SOFTWARE_PREFETCH_MODE ///< Not a software prefetch mode, use for limit checking.
+} SOFTWARE_PREFETCH_MODE;
+
+/// Advanced performance tunings, prefetchers.
+/// These settings provide for performance tuning to optimize for specific workloads.
+typedef struct {
+ IN HARDWARE_PREFETCH_MODE HardwarePrefetchMode; ///< This value provides for advanced performance tuning by controlling the hardware prefetcher setting.
+ IN SOFTWARE_PREFETCH_MODE SoftwarePrefetchMode; ///< This value provides for advanced performance tuning by controlling the software prefetch instructions.
+ IN DRAM_PREFETCH_MODE DramPrefetchMode; ///< This value provides for advanced performance tuning by controlling the DRAM prefetcher setting.
+} ADVANCED_PERFORMANCE_PROFILE;
+
+/// The possible platform power policy settings.
+typedef enum {
+ Performance, ///< Optimize for performance.
+ BatteryLife, ///< Optimize for battery life.
+ MaxPowerPolicy ///< Not a power policy mode, use for limit checking.
+} PLATFORM_POWER_POLICY;
+
+/// Platform performance settings for optimized settings.
+/// Several configuration settings for the processor depend upon other parts and
+/// general designer choices for the system. The determination of these data points
+/// is not standard for all platforms, so the host environment needs to provide these
+/// to specify how the system is to be configured.
+typedef struct {
+ IN PLATFORM_CONTROL_FLOW PlatformControlFlowMode; ///< The platform's control flow mode for optimum platform performance.
+ ///< @BldCfgItem{BLDCFG_PLATFORM_CONTROL_FLOW_MODE}
+ IN BOOLEAN Use32ByteRefresh; ///< Display Refresh traffic generates 32 byte requests.
+ ///< @BldCfgItem{BLDCFG_USE_32_BYTE_REFRESH}
+ IN BOOLEAN UseVariableMctIsocPriority; ///< The Memory controller will be set to Variable Isoc Priority.
+ ///< @BldCfgItem{BLDCFG_USE_VARIABLE_MCT_ISOC_PRIORITY}
+ IN ADVANCED_PERFORMANCE_PROFILE AdvancedPerformanceProfile; ///< The advanced platform performance settings.
+ IN PLATFORM_POWER_POLICY PlatformPowerPolicy; ///< The platform's desired power policy
+ ///< @BldCfgItem{BLDCFG_PLATFORM_POWER_POLICY_MODE}
+ IN BOOLEAN NbPstatesSupported; ///< The Nb-Pstates is supported or not
+ ///< @BldCfgItem{BLDCFG_NB_PSTATES_SUPPORTED}
+} PERFORMANCE_PROFILE;
+
+/// Platform settings that describe the voltage regulator modules of the system.
+/// Many power management settings are dependent upon the characteristics of the
+/// on-board voltage regulator module (VRM). The host environment needs to provide
+/// these to specify how the system is to be configured.
+typedef struct {
+ IN UINT32 CurrentLimit; ///< Vrm Current Limit.
+ ///< @BldCfgItem{BLDCFG_VRM_CURRENT_LIMIT}
+ ///< @BldCfgItem{BLDCFG_VRM_NB_CURRENT_LIMIT}
+ IN UINT32 LowPowerThreshold; ///< Vrm Low Power Threshold.
+ ///< @BldCfgItem{BLDCFG_VRM_LOW_POWER_THRESHOLD}
+ ///< @BldCfgItem{BLDCFG_VRM_NB_LOW_POWER_THRESHOLD}
+ IN UINT32 SlewRate; ///< Vrm Slew Rate.
+ ///< @BldCfgItem{BLDCFG_VRM_SLEW_RATE}
+ ///< @BldCfgItem{BLDCFG_VRM_NB_SLEW_RATE}
+ IN BOOLEAN HiSpeedEnable; ///< Select high speed VRM.
+ ///< @BldCfgItem{BLDCFG_VRM_HIGH_SPEED_ENABLE}
+ ///< @BldCfgItem{BLDCFG_VRM_NB_HIGH_SPEED_ENABLE}
+ IN UINT32 MaximumCurrentLimit; ///< Vrm Maximum Current Limit.
+ ///< @BldCfgItem{BLDCFG_VRM_MAXIMUM_CURRENT_LIMIT}
+ ///< @BldCfgItem{BLDCFG_VRM_NB_MAXIMUM_CURRENT_LIMIT}
+ IN UINT32 SviOcpLevel; ///< SVI OCP Level.
+ ///< @BldCfgItem{BLDCFG_VRM_SVI_OCP_LEVEL}
+ ///< @BldCfgItem{BLDCFG_VRM_NB_SVI_OCP_LEVEL}
+} PLATFORM_VRM_CONFIGURATION;
+
+/// The VRM types to characterize.
+typedef enum {
+ CoreVrm, ///< VDD plane.
+ NbVrm, ///< VDDNB plane.
+ MaxVrmType ///< Not a valid VRM type, use for limit checking.
+} PLATFORM_VRM_TYPE;
+
+
+/// FCH Platform Configuration Policy
+typedef struct {
+ IN UINT16 CfgSmbus0BaseAddress; ///< SMBUS0 Controller Base Address
+ IN UINT16 CfgSmbus1BaseAddress; ///< SMBUS1 Controller Base Address
+ IN UINT16 CfgSioPmeBaseAddress; ///< I/O base address for LPC I/O target range
+ IN UINT16 CfgAcpiPm1EvtBlkAddr; ///< I/O base address of ACPI power management Event Block
+ IN UINT16 CfgAcpiPm1CntBlkAddr; ///< I/O base address of ACPI power management Control Block
+ IN UINT16 CfgAcpiPmTmrBlkAddr; ///< I/O base address of ACPI power management Timer Block
+ IN UINT16 CfgCpuControlBlkAddr; ///< I/O base address of ACPI power management CPU Control Block
+ IN UINT16 CfgAcpiGpe0BlkAddr; ///< I/O base address of ACPI power management General Purpose Event Block
+ IN UINT16 CfgSmiCmdPortAddr; ///< I/O base address of ACPI SMI Command Block
+ IN UINT16 CfgAcpiPmaCntBlkAddr; ///< I/O base address of ACPI power management additional control block
+ IN UINT32 CfgGecShadowRomBase; ///< 32-bit base address to the GEC shadow ROM
+ IN UINT32 CfgWatchDogTimerBase; ///< Watchdog Timer base address
+ IN UINT32 CfgSpiRomBaseAddress; ///< Base address for the SPI ROM controller
+ IN UINT32 CfgHpetBaseAddress; ///< HPET MMIO base address
+ IN UINT32 CfgAzaliaSsid; ///< Subsystem ID of HD Audio controller
+ IN UINT32 CfgSmbusSsid; ///< Subsystem ID of SMBUS controller
+ IN UINT32 CfgIdeSsid; ///< Subsystem ID of IDE controller
+ IN UINT32 CfgSataAhciSsid; ///< Subsystem ID of SATA controller in AHCI mode
+ IN UINT32 CfgSataIdeSsid; ///< Subsystem ID of SATA controller in IDE mode
+ IN UINT32 CfgSataRaid5Ssid; ///< Subsystem ID of SATA controller in RAID5 mode
+ IN UINT32 CfgSataRaidSsid; ///< Subsystem ID of SATA controller in RAID mode
+ IN UINT32 CfgEhciSsid; ///< Subsystem ID of EHCI
+ IN UINT32 CfgOhciSsid; ///< Subsystem ID of OHCI
+ IN UINT32 CfgLpcSsid; ///< Subsystem ID of LPC ISA Bridge
+ IN UINT32 CfgSdSsid; ///< Subsystem ID of SecureDigital controller
+ IN UINT32 CfgXhciSsid; ///< Subsystem ID of XHCI
+ IN BOOLEAN CfgFchPort80BehindPcib; ///< Is port80 cycle going to the PCI bridge
+ IN BOOLEAN CfgFchEnableAcpiSleepTrap; ///< ACPI sleep SMI enable/disable
+ IN GPP_LINKMODE CfgFchGppLinkConfig; ///< GPP link configuration
+ IN BOOLEAN CfgFchGppPort0Present; ///< Is FCH GPP port 0 present
+ IN BOOLEAN CfgFchGppPort1Present; ///< Is FCH GPP port 1 present
+ IN BOOLEAN CfgFchGppPort2Present; ///< Is FCH GPP port 2 present
+ IN BOOLEAN CfgFchGppPort3Present; ///< Is FCH GPP port 3 present
+ IN BOOLEAN CfgFchGppPort0HotPlug; ///< Is FCH GPP port 0 hotplug capable
+ IN BOOLEAN CfgFchGppPort1HotPlug; ///< Is FCH GPP port 1 hotplug capable
+ IN BOOLEAN CfgFchGppPort2HotPlug; ///< Is FCH GPP port 2 hotplug capable
+ IN BOOLEAN CfgFchGppPort3HotPlug; ///< Is FCH GPP port 3 hotplug capable
+
+ IN UINT8 CfgFchEsataPortBitMap; ///< ESATA Port definition, eg: [0]=1, means port 0 is ESATA capable
+ IN UINT8 CfgFchIrPinControl; ///< Register bitfield describing Infrared Pin Control:
+ ///< [0] - IR Enable 0
+ ///< [1] - IR Enable 1
+ ///< [2] - IR Tx0
+ ///< [3] - IR Tx1
+ ///< [4] - IR Open Drain
+ ///< [5] - IR Enable LED
+ IN SD_CLOCK_CONTROL CfgFchSdClockControl; ///< FCH SD Clock Control
+ IN SCI_MAP_CONTROL *CfgFchSciMapControl; ///< FCH SCI Mapping Control
+ IN SATA_PHY_CONTROL *CfgFchSataPhyControl; ///< FCH SATA PHY Control
+ IN GPIO_CONTROL *CfgFchGpioControl; ///< FCH GPIO Control
+ IN BOOLEAN CfgFchRtcWorkAround; ///< FCH RTC Workaround
+ IN BOOLEAN CfgFchUsbPortDisWorkAround; ///< FCH USB Workaround
+} FCH_PLATFORM_POLICY;
+
+
+/// Build Option/Configuration Boolean Structure.
+typedef struct {
+ IN AMD_CODE_HEADER VersionString; ///< AMD embedded code version string
+
+ //Build Option Area
+ IN BOOLEAN OptionUDimms; ///< @ref BLDOPT_REMOVE_UDIMMS_SUPPORT "BLDOPT_REMOVE_UDIMMS_SUPPORT"
+ IN BOOLEAN OptionRDimms; ///< @ref BLDOPT_REMOVE_RDIMMS_SUPPORT "BLDOPT_REMOVE_RDIMMS_SUPPORT"
+ IN BOOLEAN OptionLrDimms; ///< @ref BLDOPT_REMOVE_LRDIMMS_SUPPORT "BLDOPT_REMOVE_LRDIMMS_SUPPORT"
+ IN BOOLEAN OptionEcc; ///< @ref BLDOPT_REMOVE_ECC_SUPPORT "BLDOPT_REMOVE_ECC_SUPPORT"
+ IN BOOLEAN OptionBankInterleave; ///< @ref BLDOPT_REMOVE_BANK_INTERLEAVE "BLDOPT_REMOVE_BANK_INTERLEAVE"
+ IN BOOLEAN OptionDctInterleave; ///< @ref BLDOPT_REMOVE_DCT_INTERLEAVE "BLDOPT_REMOVE_DCT_INTERLEAVE"
+ IN BOOLEAN OptionNodeInterleave; ///< @ref BLDOPT_REMOVE_NODE_INTERLEAVE "BLDOPT_REMOVE_NODE_INTERLEAVE"
+ IN BOOLEAN OptionParallelTraining; ///< @ref BLDOPT_REMOVE_PARALLEL_TRAINING "BLDOPT_REMOVE_PARALLEL_TRAINING"
+ IN BOOLEAN OptionOnlineSpare; ///< @ref BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT "BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT"
+ IN BOOLEAN OptionMemRestore; ///< @ref BLDOPT_REMOVE_MEM_RESTORE_SUPPORT "BLDOPT_REMOVE_MEM_RESTORE_SUPPORT"
+ IN BOOLEAN OptionMultisocket; ///< @ref BLDOPT_REMOVE_MULTISOCKET_SUPPORT "BLDOPT_REMOVE_MULTISOCKET_SUPPORT"
+ IN BOOLEAN OptionAcpiPstates; ///< @ref BLDOPT_REMOVE_ACPI_PSTATES "BLDOPT_REMOVE_ACPI_PSTATES"
+ IN BOOLEAN OptionCrat; ///< @ref BLDOPT_REMOVE_CRAT "BLDOPT_REMOVE_CRAT"
+ IN BOOLEAN OptionCdit; ///< @ref BLDOPT_REMOVE_CDIT "BLDOPT_REMOVE_CDIT"
+ IN BOOLEAN OptionSrat; ///< @ref BLDOPT_REMOVE_SRAT "BLDOPT_REMOVE_SRAT"
+ IN BOOLEAN OptionSlit; ///< @ref BLDOPT_REMOVE_SLIT "BLDOPT_REMOVE_SLIT"
+ IN BOOLEAN OptionWhea; ///< @ref BLDOPT_REMOVE_WHEA "BLDOPT_REMOVE_WHEA"
+ IN BOOLEAN OptionDmi; ///< @ref BLDOPT_REMOVE_DMI "BLDOPT_REMOVE_DMI"
+ IN BOOLEAN OptionEarlySamples; ///< @ref BLDOPT_REMOVE_EARLY_SAMPLES "BLDOPT_REMOVE_EARLY_SAMPLES"
+ IN BOOLEAN OptionAddrToCsTranslator; ///< ADDR_TO_CS_TRANSLATOR
+
+ //Build Configuration Area
+ IN UINT64 CfgPciMmioAddress; ///< Pci Mmio Base Address to use for PCI Config accesses.
+ ///< Build-time customizable only - @BldCfgItem{BLDCFG_PCI_MMIO_BASE}
+ IN UINT32 CfgPciMmioSize; ///< Pci Mmio region Size.
+ ///< Build-time customizable only - @BldCfgItem{BLDCFG_PCI_MMIO_SIZE}
+ IN PLATFORM_VRM_CONFIGURATION CfgPlatVrmCfg[MaxVrmType]; ///< Several configuration settings for the voltage regulator modules.
+ IN UINT32 CfgCpuFrequencyLimit; ///< CPU frequency limit
+ IN PLATFORM_CONNECTED_STANDBY_MODES CfgPlatformConnectedStandbyMode; ///< Enable or disable connected standby
+ IN UINT32 CfgPlatNumIoApics; ///< The number of IO APICS for the platform.
+ IN UINT32 CfgMemInitPstate; ///< Memory Init Pstate.
+ IN PLATFORM_CSTATE_MODES CfgPlatformCStateMode; ///< Select the C-State Mode that will used.
+ IN UINT32 CfgPlatformCStateOpData; ///< An IO port or additional C-State setup data, depends on C-State mode.
+ IN UINT16 CfgPlatformCStateIoBaseAddress; ///< Specifies I/O ports that can be used to allow CPU to enter CStates
+ IN PLATFORM_CPB_MODES CfgPlatformCpbMode; ///< Enable or disable core performance boost
+ IN PLATFORM_LOW_POWER_PSTATE_MODES CfgLowPowerPstateForProcHot; ///< Low power Pstate for PROCHOT mode
+ IN UINT32 CfgCoreLevelingMode; ///< Apply any downcoring or core count leveling as specified.
+ IN PERFORMANCE_PROFILE CfgPerformanceProfile; ///< The platform's control flow mode and platform performance settings.
+
+ IN UINT32 CfgAmdPlatformType; ///< Designate the platform as a Server, Desktop, or Mobile.
+ IN UINT32 CfgAmdPowerCeiling; ///< PowerCeiling, specifies a maximum power usage limit for the platform
+ IN UINT16 CfgHtcTemperatureLimit; ///< Hardware Thermal Control temperature limit in tenths of degrees Celsius.
+ IN UINT16 CfgLhtcTemperatureLimit; ///< Local Hardware Thermal Control temperature limit in tenths of degrees Celsius.
+
+ IN UINT32 CfgMemoryBusFrequencyLimit; ///< Memory Bus Frequency Limit.
+ ///< Build-time customizable only - @BldCfgItem{BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT}
+ IN BOOLEAN CfgMemoryModeUnganged; ///< Memory Mode Unganged.
+ ///< Build-time customizable only - @BldCfgItem{BLDCFG_MEMORY_MODE_UNGANGED}
+ IN BOOLEAN CfgMemoryQuadRankCapable; ///< Memory Quad Rank Capable.
+ ///< Build-time customizable only - @BldCfgItem{BLDCFG_MEMORY_QUAD_RANK_CAPABLE}
+ IN UINT32 CfgMemoryQuadrankType; ///< Memory Quadrank Type.
+ ///< Build-time customizable only - @BldCfgItem{BLDCFG_MEMORY_QUADRANK_TYPE}
+ IN BOOLEAN CfgMemoryRDimmCapable; ///< Memory RDIMM Capable.
+ IN BOOLEAN CfgMemoryLRDimmCapable; ///< Memory LRDIMM Capable.
+ IN BOOLEAN CfgMemoryUDimmCapable; ///< Memory UDIMM Capable.
+ IN BOOLEAN CfgMemorySODimmCapable; ///< Memory SODimm Capable.
+ ///< Build-time customizable only - @BldCfgItem{BLDCFG_MEMORY_SODIMM_CAPABLE}
+ IN BOOLEAN CfgLimitMemoryToBelow1Tb; ///< Limit memory address space to below 1TB
+ IN BOOLEAN CfgMemoryEnableBankInterleaving; ///< Memory Enable Bank Interleaving.
+ IN BOOLEAN CfgMemoryEnableNodeInterleaving; ///< Memory Enable Node Interleaving.
+ IN BOOLEAN CfgMemoryChannelInterleaving; ///< Memory Channel Interleaving.
+ IN BOOLEAN CfgMemoryPowerDown; ///< Memory Power Down.
+ IN UINT32 CfgPowerDownMode; ///< Power Down Mode.
+ IN BOOLEAN CfgOnlineSpare; ///< Online Spare.
+ IN BOOLEAN CfgMemoryParityEnable; ///< Memory Parity Enable.
+ IN BOOLEAN CfgBankSwizzle; ///< Bank Swizzle.
+ IN UINT32 CfgTimingModeSelect; ///< Timing Mode Select.
+ IN UINT32 CfgMemoryClockSelect; ///< Memory Clock Select.
+ IN BOOLEAN CfgDqsTrainingControl; ///< Dqs Training Control.
+ ///< Build-time customizable only - @BldCfgItem{BLDCFG_DQS_TRAINING_CONTROL}
+ IN BOOLEAN CfgIgnoreSpdChecksum; ///< Ignore Spd Checksum.
+ ///< Build-time customizable only - @BldCfgItem{BLDCFG_IGNORE_SPD_CHECKSUM}
+ IN BOOLEAN CfgUseBurstMode; ///< Use Burst Mode.
+ ///< Build-time customizable only - @BldCfgItem{BLDCFG_USE_BURST_MODE}
+ IN BOOLEAN CfgMemoryAllClocksOn; ///< Memory All Clocks On.
+ ///< Build-time customizable only - @BldCfgItem{BLDCFG_MEMORY_ALL_CLOCKS_ON}
+ IN BOOLEAN CfgDdrPhyDllBypassMode; ///< Enable DllPDBypassMode
+ IN BOOLEAN CfgEnableEccFeature; ///< Enable ECC Feature.
+ IN BOOLEAN CfgEccRedirection; ///< ECC Redirection.
+ ///< Build-time customizable only - @BldCfgItem{BLDCFG_ECC_REDIRECTION}
+ IN UINT16 CfgScrubDramRate; ///< Scrub Dram Rate.
+ ///< Build-time customizable only - @BldCfgItem{BLDCFG_SCRUB_DRAM_RATE}
+ IN UINT16 CfgScrubL2Rate; ///< Scrub L2Rate.
+ ///< Build-time customizable only - @BldCfgItem{BLDCFG_SCRUB_L2_RATE}
+ IN UINT16 CfgScrubL3Rate; ///< Scrub L3Rate.
+ ///< Build-time customizable only - @BldCfgItem{BLDCFG_SCRUB_L3_RATE}
+ IN UINT16 CfgScrubIcRate; ///< Scrub Ic Rate.
+ ///< Build-time customizable only - @BldCfgItem{BLDCFG_SCRUB_IC_RATE}
+ IN UINT16 CfgScrubDcRate; ///< Scrub Dc Rate.
+ ///< Build-time customizable only - @BldCfgItem{BLDCFG_SCRUB_DC_RATE}
+ IN BOOLEAN CfgEccSyncFlood; ///< ECC Sync Flood.
+ ///< Build-time customizable only - @BldCfgItem{BLDCFG_ECC_SYNC_FLOOD}
+ IN UINT16 CfgEccSymbolSize; ///< ECC Symbol Size.
+ ///< Build-time customizable only - @BldCfgItem{BLDCFG_ECC_SYMBOL_SIZE}
+ IN UINT64 CfgHeapDramAddress; ///< Heap contents will be temporarily stored in this address during the transition.
+ ///< Build-time customizable only - @BldCfgItem{BLDCFG_HEAP_DRAM_ADDRESS}
+ IN BOOLEAN CfgNodeMem1GBAlign; ///< Node Mem 1GB boundary Alignment
+ IN BOOLEAN CfgS3LateRestore; ///< S3 Late Restore
+ IN BOOLEAN CfgAcpiPstateIndependent; ///< PSD method dependent/Independent
+ IN UINT32 CfgAcpiPstatesPsdPolicy; ///< PSD policy
+ IN AP_MTRR_SETTINGS *CfgApMtrrSettingsList; ///< The AP's MTRR settings before final halt
+ ///< Build-time customizable only - @BldCfgItem{BLDCFG_AP_MTRR_SETTINGS_LIST}
+ IN UMA_MODE CfgUmaMode; ///< Uma Mode
+ IN UINT32 CfgUmaSize; ///< Uma Size [31:0]=Addr[47:16]
+ IN BOOLEAN CfgUmaAbove4G; ///< Uma Above 4G Support
+ IN UMA_ALIGNMENT CfgUmaAlignment; ///< Uma alignment
+ IN BOOLEAN CfgProcessorScopeInSb; ///< ACPI Processor Object in \\_SB scope
+ IN CHAR8 CfgProcessorScopeName0; ///< OEM specific 1st character of processor scope name.
+ IN CHAR8 CfgProcessorScopeName1; ///< OEM specific 2nd character of processor scope name.
+ IN UINT8 CfgGnbHdAudio; ///< GNB HD Audio
+ IN UINT8 CfgAbmSupport; ///< Abm Support
+ IN UINT8 CfgDynamicRefreshRate; ///< DRR Dynamic Refresh Rate
+ IN UINT16 CfgLcdBackLightControl; ///< LCD Backlight Control
+ IN UINT8 CfgGnb3dStereoPinIndex; ///< 3D Stereo Pin ID.
+ IN UINT32 CfgTempPcieMmioBaseAddress; ///< Temp pcie MMIO base Address
+ ///< Build-time customizable only - @BldCfgItem{BLDCFG_TEMP_PCIE_MMIO_BASE_ADDRESS}
+ IN UINT32 CfgGnbIGPUSSID; ///< Gnb internal GPU SSID
+ ///< Build-time customizable only - @BldCfgItem{BLDCFG_IGPU_SUBSYSTEM_ID}
+ IN UINT32 CfgGnbHDAudioSSID; ///< Gnb HD Audio SSID
+ ///< Build-time customizable only - @BldCfgItem{BLDCFG_IGPU_HD_AUDIO_SUBSYSTEM_ID}
+ IN UINT32 CfgGnbPcieSSID; ///< Gnb PCIe SSID
+ ///< Build-time customizable only - @BldCfgItem{BLDCFG_APU_PCIE_PORTS_SUBSYSTEM_ID}
+ IN UINT16 CfgLvdsSpreadSpectrum; ///< Lvds Spread Spectrum
+ ///< Build-time customizable only - @BldCfgItem{BLDCFG_GFX_LVDS_SPREAD_SPECTRUM}
+ IN UINT16 CfgLvdsSpreadSpectrumRate; ///< Lvds Spread Spectrum Rate
+ ///< Build-time customizable only - @BldCfgItem{BLDCFG_GFX_LVDS_SPREAD_SPECTRUM_RATE}
+ IN FCH_PLATFORM_POLICY *FchBldCfg; ///< FCH platform build configuration policy
+
+ IN BOOLEAN CfgIommuSupport; ///< IOMMU support
+ IN UINT8 CfgLvdsPowerOnSeqDigonToDe; ///< Panel initialization timing
+ IN UINT8 CfgLvdsPowerOnSeqDeToVaryBl; ///< Panel initialization timing
+ IN UINT8 CfgLvdsPowerOnSeqDeToDigon; ///< Panel initialization timing
+ IN UINT8 CfgLvdsPowerOnSeqVaryBlToDe; ///< Panel initialization timing
+ IN UINT8 CfgLvdsPowerOnSeqOnToOffDelay; ///< Panel initialization timing
+ IN UINT8 CfgLvdsPowerOnSeqVaryBlToBlon; ///< Panel initialization timing
+ IN UINT8 CfgLvdsPowerOnSeqBlonToVaryBl; ///< Panel initialization timing
+ IN UINT16 CfgLvdsMaxPixelClockFreq; ///< The maximum pixel clock frequency supported
+ IN UINT32 CfgLcdBitDepthControlValue; ///< The LCD bit depth control settings
+ IN UINT8 CfgLvds24bbpPanelMode; ///< The LVDS 24 BBP mode
+ IN LVDS_MISC_CONTROL CfgLvdsMiscControl; ///< THe LVDS Misc control
+ IN UINT16 CfgPcieRefClkSpreadSpectrum; ///< PCIe Reference Clock Spread Spectrum
+ ///< Build-time customizable only - @BldCfgItem{BLDCFG_PCIE_REFCLK_SPREAD_SPECTRUM}
+ IN BOOLEAN CfgExternalVrefCtlFeature; ///< External Vref control
+ IN FORCE_TRAIN_MODE CfgForceTrainMode; ///< Force Train Mode
+ IN BOOLEAN CfgGnbRemoteDisplaySupport; ///< Wireless Display Support
+ IN IOMMU_EXCLUSION_RANGE_DESCRIPTOR *CfgIvrsExclusionRangeList;
+ IN BOOLEAN CfgGnbSyncFloodPinAsNmi; ///< @ref BLDCFG_USE_SYNCFLOOD_AS_NMI "BLDCFG_USE_SYNCFLOOD_AS_NMI"
+ IN UINT8 CfgIgpuEnableDisablePolicy; ///< This item defines the iGPU Enable/Disable policy
+ ///< @li 0 = Auto - use current default
+ ///< @li 2 = Disable iGPU if ANY PCI or PCIe Graphics card is present
+ ///< @BldCfgItem{BLDCFG_IGPU_ENABLE_DISABLE_POLICY}
+ IN UINT8 CfgGnbSwTjOffset; ///< Software-writeable TjOffset to account for changes in junction temperature
+ ///< Build-time customizable only - @BldCfgItem{BLDCFG_GNB_THERMAL_SENSOR_CORRECTION}
+ IN UINT8 CfgLvdsMiscVoltAdjustment; ///< Register LVDS_CTRL_4 to adjust LVDS output voltage
+ ///< Build-time customizable only - @BldCfgItem{BLDCFG_LVDS_MISC_VOL_ADJUSTMENT}
+ IN DISPLAY_MISC_CONTROL CfgDisplayMiscControl; ///< The Display Misc control
+ IN DP_FIXED_VOLT_SWING_TYPE CfgDpFixedVoltSwingType;///< To indicate fixed voltage swing value
+ ///< @BldCfgItem{BLDCFG_DP_FIXED_VOLT_SWING}
+ IN TECHNOLOGY_TYPE CfgDimmTypeUsedInMixedConfig; ///< Select the preferred technology type that AGESA will enable
+ ///< when it is mixed with other technology types.
+ IN BOOLEAN CfgHybridBoostEnable; ///< HyBrid Boost support
+ ///< @BldCfgItem{BLDCFG_HYBRID_BOOST_ENABLE}
+ IN UINT64 CfgGnbIoapicAddress; ///< GNB IOAPIC Base Address(NULL if platform configured)
+ ///< @BldCfgItem{BLDCFG_GNB_IOAPIC_ADDRESS}
+ IN BOOLEAN CfgDataEyeEn; ///< Enable get 2D Data Eye
+ IN BOOLEAN CfgDockedTdpHeadroom; ///< @BldCfgItem{BLDCFG_DOCKED_TDP_HEADROOM}
+ IN BOOLEAN CfgBatteryBoostEn; ///< @BldCfgItem{BLDCFG_BATTERY_BOOST_EN}
+ IN UINT32 CfgBatteryBoostTune; ///< @BldCfgItem{BLDCFG_BATTERY_BOOST_TUNE}
+ IN UINT32 CfgNumGfxCoresEnabled; ///< @BldCfgItem{BLDCFG_NUM_GFX_CORES_ENABLED}
+ IN UINT32 CfgTdpAcDocked; ///< @BldCfgItem{BLDCFG_TDP_AC_DOCKED}
+ IN UINT32 CfgTdpDcDocked; ///< @BldCfgItem{BLDCFG_TDP_DC_DOCKED}
+ IN UINT32 CfgTdpAcUnDocked; ///< @BldCfgItem{BLDCFG_TDP_AC_UNDOCKED}
+ IN UINT32 CfgTdpDcUnDocked; ///< @BldCfgItem{BLDCFG_TDP_DC_UNDOCKED}
+ IN UINT32 CfgTspAcDocked; ///< @BldCfgItem{BLDCFG_TSP_AC_DOCKED}
+ IN UINT32 CfgTspDcDocked; ///< @BldCfgItem{BLDCFG_TSP_DC_DOCKED}
+ IN UINT32 CfgTspAcUnDocked; ///< @BldCfgItem{BLDCFG_TSP_AC_UNDOCKED}
+ IN UINT32 CfgTspDcUnDocked; ///< @BldCfgItem{BLDCFG_TSP_DC_UNDOCKED}
+ IN BOOLEAN CfgStapmEnAcDocked; ///< @BldCfgItem{BLDCFG_STAPM_EN_AC_DOCKED}
+ IN BOOLEAN CfgStapmEnDcDocked; ///< @BldCfgItem{BLDCFG_STAPM_EN_DC_DOCKED}
+ IN BOOLEAN CfgStapmEnAcUnDocked; ///< @BldCfgItem{BLDCFG_STAPM_EN_AC_UNDOCKED}
+ IN BOOLEAN CfgStapmEnDcUnDocked; ///< @BldCfgItem{BLDCFG_STAPM_EN_DC_UNDOCKED}
+ IN UINT32 CfgStapmPowerAcDocked; ///< @BldCfgItem{BLDCFG_STAPM_POWER_AC_DOCKED}
+ IN UINT32 CfgStapmPowerDcDocked; ///< @BldCfgItem{BLDCFG_STAPM_POWER_DC_DOCKED}
+ IN UINT32 CfgStapmPowerAcUnDocked; ///< @BldCfgItem{BLDCFG_STAPM_POWER_AC_UNDOCKED}
+ IN UINT32 CfgStapmPowerDcUnDocked; ///< @BldCfgItem{BLDCFG_STAPM_POWER_DC_UNDOCKED}
+ IN BOOLEAN CfgDramDoubleRefreshRateEn; ///< Double DRAM refresh rate
+ IN ACP_SIZE CfgGnbAcpSize; ///< ACP size [31:0]=Addr[47:16]
+ ///< @BldCfgItem{BLDCFG_ACP_SIZE}
+ IN PMU_TRAIN_MODE CfgPmuTrainMode; ///< Force Train Mode
+ ///< @BldCfgItem{BLDCFG_PMU_TRAINING_MODE}
+ IN MEMORY_PHY_VOLTAGE CfgMemoryPhyVoltage; ///< Memory Phy voltage (VDDR)
+ ///< @BldCfgItem{BLDCFG_MEMORY_PHY_VOLTAGE}
+ IN UINT32 CfgGpuFrequencyLimit; ///< @BldCfgItem{BLDCFG_GPU_FREQUENCY_LIMIT}
+ IN UINT8 CfgMaxNumAudioEndpoints; ///< @BldCfgItem{BLDCFG_MAX_NUM_AUDIO_ENDPOINTS}
+ IN BOOLEAN Reserved; ///< reserved...
+} BUILD_OPT_CFG;
+
+/// A structure containing platform specific operational characteristics. This
+/// structure is initially populated by the initializer with a copy of the same
+/// structure that was created at build time using the build configuration controls.
+typedef struct _PLATFORM_CONFIGURATION {
+ IN PERFORMANCE_PROFILE PlatformProfile; ///< Several configuration settings for the processor.
+ IN UINT8 CoreLevelingMode; ///< Indicates how to balance the number of cores per processor.
+ ///< @BldCfgItem{BLDCFG_CORE_LEVELING_MODE}
+ IN PLATFORM_CSTATE_MODES CStateMode; ///< Specifies the method of C-State enablement - Disabled, or C6.
+ ///< @BldCfgItem{BLDCFG_PLATFORM_CSTATE_MODE}
+ IN UINT32 CStatePlatformData; ///< This element specifies some pertinent data needed for the operation of the Cstate feature
+ ///< If CStateMode is CStateModeC6, this item is reserved
+ ///< @BldCfgItem{BLDCFG_PLATFORM_CSTATE_OPDATA}
+ IN UINT16 CStateIoBaseAddress; ///< This item specifies a free block of 8 consecutive bytes of I/O ports that
+ ///< can be used to allow the CPU to enter Cstates.
+ ///< @BldCfgItem{BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS}
+ IN PLATFORM_CPB_MODES CpbMode; ///< Specifies the method of core performance boost enablement - Disabled, or Auto.
+ ///< @BldCfgItem{BLDCFG_PLATFORM_CPB_MODE}
+ IN BOOLEAN UserOptionDmi; ///< When set to TRUE, the DMI data table is generated.
+ IN BOOLEAN UserOptionPState; ///< When set to TRUE, the PState data tables are generated.
+ IN BOOLEAN UserOptionCrat; ///< When set to TRUE, the CRAT data table is generated.
+ IN BOOLEAN UserOptionCdit; ///< When set to TRUE, the CDIT data table is generated.
+ IN BOOLEAN UserOptionSrat; ///< When set to TRUE, the SRAT data table is generated.
+ IN BOOLEAN UserOptionSlit; ///< When set to TRUE, the SLIT data table is generated.
+ IN BOOLEAN UserOptionWhea; ///< When set to TRUE, the WHEA data table is generated.
+ IN PLATFORM_LOW_POWER_PSTATE_MODES LowPowerPstateForProcHot; ///< Specifies the method of low power Pstate for PROCHOT enablement - Disabled, or Auto.
+ IN UINT32 PowerCeiling; ///< P-State Ceiling Enabling Deck - Max power milli-watts.
+ IN BOOLEAN ForcePstateIndependent; ///< Deprecated in favor of PstatesPsdPolicy.
+ ///< P-State _PSD is forced independent.
+ ///< @BldCfgItem{BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT}
+ IN UINT32 PstatesPsdPolicy; ///< PSD policy
+ ///< @BldCfgItem{BLDCFG_ACPI_PSTATES_PSD_POLICY}
+ IN UINT32 CpuFrequencyLimit; ///< @BldCfgItem{BLDCFG_CPU_FREQUENCY_LIMIT}
+ IN PLATFORM_CONNECTED_STANDBY_MODES CfgPlatformConnectedStandbyMode; ///< @BldCfgItem{BLDCFG_CPU_CONNECTED_STANDBY_MODE}
+ IN UINT32 NumberOfIoApics; ///< Number of I/O APICs in the system
+ ///< @BldCfgItem{BLDCFG_PLATFORM_NUM_IO_APICS}
+ IN PLATFORM_VRM_CONFIGURATION VrmProperties[MaxVrmType]; ///< Several configuration settings for the voltage regulator modules.
+ IN BOOLEAN ProcessorScopeInSb; ///< ACPI Processor Object in \\_SB scope
+ ///< @BldCfgItem{BLDCFG_PROCESSOR_SCOPE_IN_SB}
+ IN CHAR8 ProcessorScopeName0; ///< OEM specific 1st character of processor scope name.
+ ///< @BldCfgItem{BLDCFG_PROCESSOR_SCOPE_NAME0}
+ IN CHAR8 ProcessorScopeName1; ///< OEM specific 2nd character of processor scope name.
+ ///< @BldCfgItem{BLDCFG_PROCESSOR_SCOPE_NAME1}
+ IN UINT8 GnbHdAudio; ///< Control GFX HD Audio controller(Used for HDMI and DP display output),
+ ///< essentially it enables function 1 of graphics device.
+ ///< @li 0 = HD Audio disable
+ ///< @li 1 = HD Audio enable
+ ///< @BldCfgItem{BLDCFG_CFG_GNB_HD_AUDIO}
+ IN UINT8 AbmSupport; ///< Automatic adjust LVDS/eDP Back light level support.It is
+ ///< characteristic specific to display panel which used by platform design.
+ ///< @li 0 = ABM support disabled
+ ///< @li 1 = ABM support enabled
+ ///< @BldCfgItem{BLDCFG_CFG_ABM_SUPPORT}
+ IN UINT8 DynamicRefreshRate; ///< Adjust refresh rate on LVDS/eDP.
+ ///< @BldCfgItem{BLDCFG_CFG_DYNAMIC_REFRESH_RATE}
+ IN UINT16 LcdBackLightControl; ///< The PWM frequency to LCD backlight control.
+ ///< If equal to 0 backlight not controlled by iGPU
+ ///< @BldCfgItem{BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL}
+ IN UINT16 HtcTemperatureLimit; ///< The Hardware Thermal Control temperature limit in tenths of degrees Celsius.
+ ///< If equal to 0, use hardware defaults.
+ ///< @BldCfgItem{BLDCFG_HTC_TEMPERATURE_LIMIT}
+ IN UINT16 LhtcTemperatureLimit; ///< The Local Hardware Thermal Control temperature limit in tenths of degrees Celsius.
+ ///< If equal to 0, use hardware defaults.
+ ///< @BldCfgItem{BLDCFG_LHTC_TEMPERATURE_LIMIT}
+ IN ACP_SIZE AcpSize; ///< The size of ACP dram
+ ///< ACP_Size[31:0]=Addr[47:16]
+ ///< @BldCfgItem{BLDCFG_ACP_SIZE}
+} PLATFORM_CONFIGURATION;
+
+
+/**********************************************************************
+ * Structures for: AmdInitLate
+ **********************************************************************/
+#define PROC_VERSION_LENGTH 48
+#define MAX_DIMMS_PER_SOCKET 16
+#define PROC_MANU_LENGTH 29
+
+/* Interface Parameter Structures */
+/// DMI Type4 - Processor ID
+typedef struct {
+ OUT UINT32 ProcIdLsd; ///< Lower half of 64b ID
+ OUT UINT32 ProcIdMsd; ///< Upper half of 64b ID
+} TYPE4_PROC_ID;
+
+/// DMI Type 4 - Processor information
+typedef struct {
+ OUT UINT8 T4ProcType; ///< CPU Type
+ OUT UINT8 T4ProcFamily; ///< Family 1
+ OUT TYPE4_PROC_ID T4ProcId; ///< Id
+ OUT UINT8 T4Voltage; ///< Voltage
+ OUT UINT16 T4ExternalClock; ///< External clock
+ OUT UINT16 T4MaxSpeed; ///< Max speed
+ OUT UINT16 T4CurrentSpeed; ///< Current speed
+ OUT UINT8 T4Status; ///< Status
+ OUT UINT8 T4ProcUpgrade; ///< Up grade
+ OUT UINT8 T4CoreCount; ///< Core count
+ OUT UINT8 T4CoreEnabled; ///< Core Enable
+ OUT UINT8 T4ThreadCount; ///< Thread count
+ OUT UINT16 T4ProcCharacteristics; ///< Characteristics
+ OUT UINT16 T4ProcFamily2; ///< Family 2
+ OUT CHAR8 T4ProcVersion[PROC_VERSION_LENGTH]; ///< Cpu version
+ OUT CHAR8 T4ProcManufacturer[PROC_MANU_LENGTH]; ///< Manufacturer
+} TYPE4_DMI_INFO;
+
+/// DMI Type 7 - Cache information
+typedef struct _TYPE7_DMI_INFO {
+ OUT UINT16 T7CacheCfg; ///< Cache cfg
+ OUT UINT16 T7MaxCacheSize; ///< Max size
+ OUT UINT16 T7InstallSize; ///< Install size
+ OUT UINT16 T7SupportedSramType; ///< Supported Sram Type
+ OUT UINT16 T7CurrentSramType; ///< Current type
+ OUT UINT8 T7CacheSpeed; ///< Speed
+ OUT UINT8 T7ErrorCorrectionType; ///< ECC type
+ OUT UINT8 T7SystemCacheType; ///< Cache type
+ OUT UINT8 T7Associativity; ///< Associativity
+} TYPE7_DMI_INFO;
+
+/// DMI Type 16 offset 04h - Location
+typedef enum {
+ OtherLocation = 0x01, ///< Assign 01 to Other
+ UnknownLocation, ///< Assign 02 to Unknown
+ SystemboardOrMotherboard, ///< Assign 03 to systemboard or motherboard
+ IsaAddonCard, ///< Assign 04 to ISA add-on card
+ EisaAddonCard, ///< Assign 05 to EISA add-on card
+ PciAddonCard, ///< Assign 06 to PCI add-on card
+ McaAddonCard, ///< Assign 07 to MCA add-on card
+ PcmciaAddonCard, ///< Assign 08 to PCMCIA add-on card
+ ProprietaryAddonCard, ///< Assign 09 to proprietary add-on card
+ NuBus, ///< Assign 0A to NuBus
+ Pc98C20AddonCard, ///< Assign 0A0 to PC-98/C20 add-on card
+ Pc98C24AddonCard, ///< Assign 0A1 to PC-98/C24 add-on card
+ Pc98EAddoncard, ///< Assign 0A2 to PC-98/E add-on card
+ Pc98LocalBusAddonCard ///< Assign 0A3 to PC-98/Local bus add-on card
+} DMI_T16_LOCATION;
+
+/// DMI Type 16 offset 05h - Memory Error Correction
+typedef enum {
+ OtherUse = 0x01, ///< Assign 01 to Other
+ UnknownUse, ///< Assign 02 to Unknown
+ SystemMemory, ///< Assign 03 to system memory
+ VideoMemory, ///< Assign 04 to video memory
+ FlashMemory, ///< Assign 05 to flash memory
+ NonvolatileRam, ///< Assign 06 to non-volatile RAM
+ CacheMemory ///< Assign 07 to cache memory
+} DMI_T16_USE;
+
+/// DMI Type 16 offset 07h - Maximum Capacity
+typedef enum {
+ Dmi16OtherErrCorrection = 0x01, ///< Assign 01 to Other
+ Dmi16UnknownErrCorrection, ///< Assign 02 to Unknown
+ Dmi16NoneErrCorrection, ///< Assign 03 to None
+ Dmi16Parity, ///< Assign 04 to parity
+ Dmi16SingleBitEcc, ///< Assign 05 to Single-bit ECC
+ Dmi16MultiBitEcc, ///< Assign 06 to Multi-bit ECC
+ Dmi16Crc ///< Assign 07 to CRC
+} DMI_T16_ERROR_CORRECTION;
+
+/// DMI Type 16 - Physical Memory Array
+typedef struct {
+ OUT DMI_T16_LOCATION Location; ///< The physical location of the Memory Array,
+ ///< whether on the system board or an add-in board.
+ OUT DMI_T16_USE Use; ///< Identifies the function for which the array
+ ///< is used.
+ OUT DMI_T16_ERROR_CORRECTION MemoryErrorCorrection; ///< The primary hardware error correction or
+ ///< detection method supported by this memory array.
+ OUT UINT16 NumberOfMemoryDevices; ///< The number of slots or sockets available
+ ///< for memory devices in this array.
+} TYPE16_DMI_INFO;
+
+/// DMI Type 17 offset 0Eh - Form Factor
+typedef enum {
+ OtherFormFactor = 0x01, ///< Assign 01 to Other
+ UnknowFormFactor, ///< Assign 02 to Unknown
+ SimmFormFactor, ///< Assign 03 to SIMM
+ SipFormFactor, ///< Assign 04 to SIP
+ ChipFormFactor, ///< Assign 05 to Chip
+ DipFormFactor, ///< Assign 06 to DIP
+ ZipFormFactor, ///< Assign 07 to ZIP
+ ProprietaryCardFormFactor, ///< Assign 08 to Proprietary Card
+ DimmFormFactorFormFactor, ///< Assign 09 to DIMM
+ TsopFormFactor, ///< Assign 10 to TSOP
+ RowOfChipsFormFactor, ///< Assign 11 to Row of chips
+ RimmFormFactor, ///< Assign 12 to RIMM
+ SodimmFormFactor, ///< Assign 13 to SODIMM
+ SrimmFormFactor, ///< Assign 14 to SRIMM
+ FbDimmFormFactor ///< Assign 15 to FB-DIMM
+} DMI_T17_FORM_FACTOR;
+
+/// DMI Type 17 offset 12h - Memory Type
+typedef enum {
+ OtherMemType = 0x01, ///< Assign 01 to Other
+ UnknownMemType, ///< Assign 02 to Unknown
+ DramMemType, ///< Assign 03 to DRAM
+ EdramMemType, ///< Assign 04 to EDRAM
+ VramMemType, ///< Assign 05 to VRAM
+ SramMemType, ///< Assign 06 to SRAM
+ RamMemType, ///< Assign 07 to RAM
+ RomMemType, ///< Assign 08 to ROM
+ FlashMemType, ///< Assign 09 to Flash
+ EepromMemType, ///< Assign 10 to EEPROM
+ FepromMemType, ///< Assign 11 to FEPROM
+ EpromMemType, ///< Assign 12 to EPROM
+ CdramMemType, ///< Assign 13 to CDRAM
+ ThreeDramMemType, ///< Assign 14 to 3DRAM
+ SdramMemType, ///< Assign 15 to SDRAM
+ SgramMemType, ///< Assign 16 to SGRAM
+ RdramMemType, ///< Assign 17 to RDRAM
+ DdrMemType, ///< Assign 18 to DDR
+ Ddr2MemType, ///< Assign 19 to DDR2
+ Ddr2FbdimmMemType, ///< Assign 20 to DDR2 FB-DIMM
+ Ddr3MemType = 0x18, ///< Assign 24 to DDR3
+ Fbd2MemType ///< Assign 25 to FBD2
+} DMI_T17_MEMORY_TYPE;
+
+/// DMI Type 17 offset 13h - Type Detail
+typedef struct {
+ OUT UINT16 Reserved1:1; ///< Reserved
+ OUT UINT16 Other:1; ///< Other
+ OUT UINT16 Unknown:1; ///< Unknown
+ OUT UINT16 FastPaged:1; ///< Fast-Paged
+ OUT UINT16 StaticColumn:1; ///< Static column
+ OUT UINT16 PseudoStatic:1; ///< Pseudo-static
+ OUT UINT16 Rambus:1; ///< RAMBUS
+ OUT UINT16 Synchronous:1; ///< Synchronous
+ OUT UINT16 Cmos:1; ///< CMOS
+ OUT UINT16 Edo:1; ///< EDO
+ OUT UINT16 WindowDram:1; ///< Window DRAM
+ OUT UINT16 CacheDram:1; ///< Cache Dram
+ OUT UINT16 NonVolatile:1; ///< Non-volatile
+ OUT UINT16 Registered:1; ///< Registered (Buffered)
+ OUT UINT16 Unbuffered:1; ///< Unbuffered (Unregistered)
+ OUT UINT16 Reserved2:1; ///< Reserved
+} DMI_T17_TYPE_DETAIL;
+
+/// DMI Type 17 - Memory Device
+typedef struct {
+ OUT UINT16 Handle; ///< The temporary handle, or instance number, associated with the structure
+ OUT UINT16 TotalWidth; ///< Total Width, in bits, of this memory device, including any check or error-correction bits.
+ OUT UINT16 DataWidth; ///< Data Width, in bits, of this memory device.
+ OUT UINT16 MemorySize; ///< The size of the memory device.
+ OUT DMI_T17_FORM_FACTOR FormFactor; ///< The implementation form factor for this memory device.
+ OUT UINT8 DeviceSet; ///< Identifies when the Memory Device is one of a set of
+ ///< Memory Devices that must be populated with all devices of
+ ///< the same type and size, and the set to which this device belongs.
+ OUT CHAR8 DeviceLocator[8]; ///< The string number of the string that identifies the physically labeled socket or board position where the memory device is located.
+ OUT CHAR8 BankLocator[10]; ///< The string number of the string that identifies the physically labeled bank where the memory device is located.
+ OUT DMI_T17_MEMORY_TYPE MemoryType; ///< The type of memory used in this device.
+ OUT DMI_T17_TYPE_DETAIL TypeDetail; ///< Additional detail on the memory device type
+ OUT UINT16 Speed; ///< Identifies the speed of the device, in megahertz (MHz).
+ OUT UINT64 ManufacturerIdCode; ///< Manufacturer ID code.
+ OUT CHAR8 SerialNumber[9]; ///< Serial Number.
+ OUT CHAR8 PartNumber[19]; ///< Part Number.
+ OUT UINT8 Attributes; ///< Bits 7-4: Reserved, Bits 3-0: rank.
+ OUT UINT32 ExtSize; ///< Extended Size.
+ OUT UINT16 ConfigSpeed; ///< Configured memory clock speed
+} TYPE17_DMI_INFO;
+
+/// Memory DMI Type 17 - for memory use
+typedef struct {
+ OUT UINT8 Socket:3; ///< Socket ID
+ OUT UINT8 Channel:2; ///< Channel ID
+ OUT UINT8 Dimm:2; ///< DIMM ID
+ OUT UINT8 DimmPresent:1; ///< Dimm Present
+ OUT UINT16 Handle; ///< The temporary handle, or instance number, associated with the structure
+ OUT UINT16 TotalWidth; ///< Total Width, in bits, of this memory device, including any check or error-correction bits.
+ OUT UINT16 DataWidth; ///< Data Width, in bits, of this memory device.
+ OUT UINT16 MemorySize; ///< The size of the memory device.
+ OUT DMI_T17_FORM_FACTOR FormFactor; ///< The implementation form factor for this memory device.
+ OUT UINT8 DeviceLocator; ///< The string number of the string that identifies the physically labeled socket or board position where the memory device is located.
+ OUT UINT8 BankLocator; ///< The string number of the string that identifies the physically labeled bank where the memory device is located.
+ OUT UINT16 Speed; ///< Identifies the speed of the device, in megahertz (MHz).
+ OUT UINT64 ManufacturerIdCode; ///< Manufacturer ID code.
+ OUT UINT8 SerialNumber[4]; ///< Serial Number.
+ OUT UINT8 PartNumber[18]; ///< Part Number.
+ OUT UINT8 Attributes; ///< Bits 7-4: Reserved, Bits 3-0: rank.
+ OUT UINT32 ExtSize; ///< Extended Size.
+ OUT UINT16 ConfigSpeed; ///< Configured memory clock speed
+} MEM_DMI_PHYSICAL_DIMM_INFO;
+
+/// Memory DMI Type 20 - for memory use
+typedef struct {
+ OUT UINT8 Socket:3; ///< Socket ID
+ OUT UINT8 Channel:2; ///< Channel ID
+ OUT UINT8 Dimm:2; ///< DIMM ID
+ OUT UINT8 DimmPresent:1; ///< Dimm Present
+ OUT UINT32 StartingAddr; ///< The physical address, in kilobytes, of a range
+ ///< of memory mapped to the referenced Memory Device.
+ OUT UINT32 EndingAddr; ///< The handle, or instance number, associated with
+ ///< the Memory Device structure to which this address
+ ///< range is mapped.
+ OUT UINT16 MemoryDeviceHandle; ///< The handle, or instance number, associated with
+ ///< the Memory Device structure to which this address
+ ///< range is mapped.
+ OUT UINT64 ExtStartingAddr; ///< The physical address, in bytes, of a range of
+ ///< memory mapped to the referenced Memory Device.
+ OUT UINT64 ExtEndingAddr; ///< The physical ending address, in bytes, of the last of
+ ///< a range of addresses mapped to the referenced Memory Device.
+} MEM_DMI_LOGICAL_DIMM_INFO;
+
+/// DMI Type 19 - Memory Array Mapped Address
+typedef struct {
+ OUT UINT32 StartingAddr; ///< The physical address, in kilobytes,
+ ///< of a range of memory mapped to the
+ ///< specified physical memory array.
+ OUT UINT32 EndingAddr; ///< The physical ending address of the
+ ///< last kilobyte of a range of addresses
+ ///< mapped to the specified physical memory array.
+ OUT UINT16 MemoryArrayHandle; ///< The handle, or instance number, associated
+ ///< with the physical memory array to which this
+ ///< address range is mapped.
+ OUT UINT8 PartitionWidth; ///< Identifies the number of memory devices that
+ ///< form a single row of memory for the address
+ ///< partition defined by this structure.
+ OUT UINT64 ExtStartingAddr; ///< The physical address, in bytes, of a range of
+ ///< memory mapped to the specified Physical Memory Array.
+ OUT UINT64 ExtEndingAddr; ///< The physical address, in bytes, of a range of
+ ///< memory mapped to the specified Physical Memory Array.
+} TYPE19_DMI_INFO;
+
+///DMI Type 20 - Memory Device Mapped Address
+typedef struct {
+ OUT UINT32 StartingAddr; ///< The physical address, in kilobytes, of a range
+ ///< of memory mapped to the referenced Memory Device.
+ OUT UINT32 EndingAddr; ///< The handle, or instance number, associated with
+ ///< the Memory Device structure to which this address
+ ///< range is mapped.
+ OUT UINT16 MemoryDeviceHandle; ///< The handle, or instance number, associated with
+ ///< the Memory Device structure to which this address
+ ///< range is mapped.
+ OUT UINT16 MemoryArrayMappedAddressHandle; ///< The handle, or instance number, associated
+ ///< with the Memory Array Mapped Address structure to
+ ///< which this device address range is mapped.
+ OUT UINT8 PartitionRowPosition; ///< Identifies the position of the referenced Memory
+ ///< Device in a row of the address partition.
+ OUT UINT8 InterleavePosition; ///< The position of the referenced Memory Device in
+ ///< an interleave.
+ OUT UINT8 InterleavedDataDepth; ///< The maximum number of consecutive rows from the
+ ///< referenced Memory Device that are accessed in a
+ ///< single interleaved transfer.
+ OUT UINT64 ExtStartingAddr; ///< The physical address, in bytes, of a range of
+ ///< memory mapped to the referenced Memory Device.
+ OUT UINT64 ExtEndingAddr; ///< The physical ending address, in bytes, of the last of
+ ///< a range of addresses mapped to the referenced Memory Device.
+} TYPE20_DMI_INFO;
+
+/// Collection of pointers to the DMI records
+typedef struct {
+ OUT TYPE4_DMI_INFO T4[MAX_SOCKETS_SUPPORTED]; ///< Type 4 struc
+ OUT TYPE7_DMI_INFO T7L1[MAX_SOCKETS_SUPPORTED]; ///< Type 7 struc 1
+ OUT TYPE7_DMI_INFO T7L2[MAX_SOCKETS_SUPPORTED]; ///< Type 7 struc 2
+ OUT TYPE7_DMI_INFO T7L3[MAX_SOCKETS_SUPPORTED]; ///< Type 7 struc 3
+ OUT TYPE16_DMI_INFO T16; ///< Type 16 struc
+ OUT TYPE17_DMI_INFO T17[MAX_SOCKETS_SUPPORTED][MAX_CHANNELS_PER_SOCKET][MAX_DIMMS_PER_CHANNEL]; ///< Type 17 struc
+ OUT TYPE19_DMI_INFO T19; ///< Type 19 struc
+ OUT TYPE20_DMI_INFO T20[MAX_SOCKETS_SUPPORTED][MAX_CHANNELS_PER_SOCKET][MAX_DIMMS_PER_CHANNEL]; ///< Type 20 struc
+} DMI_INFO;
+
+/**********************************************************************
+ * Interface call: AllocateExecutionCache
+ **********************************************************************/
+#define MAX_CACHE_REGIONS 3
+
+/// AllocateExecutionCache sub param structure for cached memory region
+typedef struct {
+ IN OUT UINT32 ExeCacheStartAddr; ///< Start address
+ IN OUT UINT32 ExeCacheSize; ///< Size
+} EXECUTION_CACHE_REGION;
+
+/**********************************************************************
+ * Interface call: AmdGetAvailableExeCacheSize
+ **********************************************************************/
+/// Get available Cache remain
+typedef struct {
+ IN OUT AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header
+ OUT UINT32 AvailableExeCacheSize; ///< Remain size
+} AMD_GET_EXE_SIZE_PARAMS;
+
+AGESA_STATUS
+AmdGetAvailableExeCacheSize (
+ IN OUT AMD_GET_EXE_SIZE_PARAMS *AmdGetExeSizeParams
+ );
+
+/// Selection type for core leveling
+typedef enum {
+ CORE_LEVEL_LOWEST, ///< Level to lowest common denominator
+ CORE_LEVEL_TWO, ///< Level to 2 cores
+ CORE_LEVEL_POWER_OF_TWO, ///< Level to 1,2,4 or 8
+ CORE_LEVEL_NONE, ///< Do no leveling
+ CORE_LEVEL_COMPUTE_UNIT, ///< Level cores to one core per compute unit
+ CORE_LEVEL_COMPUTE_UNIT_TWO, ///< Level cores to two cores per compute unit
+ CORE_LEVEL_COMPUTE_UNIT_THREE, ///< Level cores to three cores per compute unit
+ CORE_LEVEL_ONE, ///< Level to 1 core
+ CORE_LEVEL_THREE, ///< Level to 3 cores
+ CORE_LEVEL_FOUR, ///< Level to 4 cores
+ CORE_LEVEL_FIVE, ///< Level to 5 cores
+ CORE_LEVEL_SIX, ///< Level to 6 cores
+ CORE_LEVEL_SEVEN, ///< Level to 7 cores
+ CORE_LEVEL_EIGHT, ///< Level to 8 cores
+ CORE_LEVEL_NINE, ///< Level to 9 cores
+ CORE_LEVEL_TEN, ///< Level to 10 cores
+ CORE_LEVEL_ELEVEN, ///< Level to 11 cores
+ CORE_LEVEL_TWELVE, ///< Level to 12 cores
+ CORE_LEVEL_THIRTEEN, ///< Level to 13 cores
+ CORE_LEVEL_FOURTEEN, ///< Level to 14 cores
+ CORE_LEVEL_FIFTEEN, ///< Level to 15 cores
+ CoreLevelModeMax ///< Used for bounds checking
+} CORE_LEVELING_TYPE;
+
+
+
+
+
+/************************************************************************
+ *
+ * AGESA Basic Level interface structure definition and function prototypes
+ *
+ ***********************************************************************/
+
+/**********************************************************************
+ * Interface call: AmdCreateStruct
+ **********************************************************************/
+AGESA_STATUS
+AmdCreateStruct (
+ IN OUT AMD_INTERFACE_PARAMS *InterfaceParams
+ );
+
+/**********************************************************************
+ * Interface call: AmdReleaseStruct
+ **********************************************************************/
+AGESA_STATUS
+AmdReleaseStruct (
+ IN OUT AMD_INTERFACE_PARAMS *InterfaceParams
+ );
+
+/**********************************************************************
+ * Interface call: AmdInitReset
+ **********************************************************************/
+/// AmdInitReset param structure
+typedef struct {
+ IN AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header
+ IN EXECUTION_CACHE_REGION CacheRegion[3]; ///< The cached memory region
+ IN FCH_RESET_INTERFACE FchInterface; ///< Interface for FCH configuration
+} AMD_RESET_PARAMS;
+
+AGESA_STATUS
+AmdInitReset (
+ IN OUT AMD_RESET_PARAMS *ResetParams
+ );
+
+
+/**********************************************************************
+ * Interface call: AmdInitEarly
+ **********************************************************************/
+/// InitEarly param structure
+///
+/// Provide defaults or customizations to each service performed in AmdInitEarly.
+///
+typedef struct {
+ IN OUT AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header
+ IN EXECUTION_CACHE_REGION CacheRegion[3]; ///< Execution Map Interface
+ IN PLATFORM_CONFIGURATION PlatformConfig; ///< platform operational characteristics.
+ IN GNB_CONFIGURATION GnbConfig; ///< GNB configuration
+} AMD_EARLY_PARAMS;
+
+AGESA_STATUS
+AmdInitEarly (
+ IN OUT AMD_EARLY_PARAMS *EarlyParams
+ );
+
+
+/**********************************************************************
+ * Interface call: AmdInitPost
+ **********************************************************************/
+/// AmdInitPost param structure
+typedef struct {
+ IN OUT AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header
+ IN PLATFORM_CONFIGURATION PlatformConfig; ///< platform operational characteristics.
+ IN MEM_PARAMETER_STRUCT MemConfig; ///< Memory post param
+ IN GNB_POST_CONFIGURATION GnbPostConfig; ///< GNB post param
+} AMD_POST_PARAMS;
+
+AGESA_STATUS
+AmdInitPost (
+ IN OUT AMD_POST_PARAMS *PostParams ///< Amd Cpu init param
+ );
+
+
+/**********************************************************************
+ * Interface call: AmdInitEnv
+ **********************************************************************/
+/// AmdInitEnv param structure
+typedef struct {
+ IN OUT AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header
+ IN PLATFORM_CONFIGURATION PlatformConfig; ///< platform operational characteristics.
+ IN GNB_ENV_CONFIGURATION GnbEnvConfiguration; ///< GNB configuration
+ IN FCH_INTERFACE FchInterface; ///< FCH configuration
+} AMD_ENV_PARAMS;
+
+AGESA_STATUS
+AmdInitEnv (
+ IN OUT AMD_ENV_PARAMS *EnvParams
+ );
+
+
+/**********************************************************************
+ * Interface call: AmdInitMid
+ **********************************************************************/
+/// AmdInitMid param structure
+typedef struct {
+ IN OUT AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header
+ IN PLATFORM_CONFIGURATION PlatformConfig; ///< platform operational characteristics.
+ IN GNB_MID_CONFIGURATION GnbMidConfiguration; ///< GNB configuration
+ IN FCH_INTERFACE FchInterface; ///< FCH configuration
+} AMD_MID_PARAMS;
+
+AGESA_STATUS
+AmdInitMid (
+ IN OUT AMD_MID_PARAMS *MidParams
+ );
+
+
+/**********************************************************************
+ * Interface call: AmdInitLate
+ **********************************************************************/
+/// AmdInitLate param structure
+typedef struct {
+ IN OUT AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header
+ IN PLATFORM_CONFIGURATION PlatformConfig; ///< platform operational characteristics.
+ IN IOMMU_EXCLUSION_RANGE_DESCRIPTOR *IvrsExclusionRangeList; ///< Pointer to array of exclusion ranges
+ OUT DMI_INFO *DmiTable; ///< DMI Interface
+ OUT VOID *AcpiPState; ///< Acpi Pstate SSDT Table
+ OUT VOID *AcpiSrat; ///< SRAT Table
+ OUT VOID *AcpiSlit; ///< SLIT Table
+ OUT VOID *AcpiWheaMce; ///< WHEA MCE Table
+ OUT VOID *AcpiWheaCmc; ///< WHEA CMC Table
+ OUT VOID *AcpiAlib; ///< ACPI SSDT table with ALIB implementation
+ OUT VOID *AcpiIvrs; ///< IOMMU ACPI IVRS(I/O Virtualization Reporting Structure) table
+ OUT VOID *AcpiCrat; ///< Component Resource Affinity Table table
+ OUT VOID *AcpiCdit; ///< Component Locality Distance Information table
+ IN GNB_LATE_CONFIGURATION GnbLateConfiguration; ///< GNB configuration
+} AMD_LATE_PARAMS;
+
+AGESA_STATUS
+AmdInitLate (
+ IN OUT AMD_LATE_PARAMS *LateParams
+ );
+
+/**********************************************************************
+ * Interface call: AmdInitRecovery
+ **********************************************************************/
+/// CPU Recovery Parameters
+typedef struct {
+ IN OUT AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header
+ IN PLATFORM_CONFIGURATION PlatformConfig; ///< platform operational characteristics.
+} AMD_CPU_RECOVERY_PARAMS;
+
+/// AmdInitRecovery param structure
+typedef struct {
+ IN OUT AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header
+ IN MEM_PARAMETER_STRUCT MemConfig; ///< Memory post param
+ IN EXECUTION_CACHE_REGION CacheRegion[3]; ///< The cached memory region. And the max cache region is 3
+ IN AMD_CPU_RECOVERY_PARAMS CpuRecoveryParams; ///< Params for CPU related recovery init.
+} AMD_RECOVERY_PARAMS;
+
+AGESA_STATUS
+AmdInitRecovery (
+ IN OUT AMD_RECOVERY_PARAMS *RecoveryParams
+ );
+
+/**********************************************************************
+ * Interface call: AmdInitResume
+ **********************************************************************/
+/// AmdInitResume param structure
+typedef struct {
+ IN OUT AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header
+ IN PLATFORM_CONFIGURATION PlatformConfig; ///< Platform operational characteristics
+ IN AMD_S3_PARAMS S3DataBlock; ///< Save state data
+} AMD_RESUME_PARAMS;
+
+AGESA_STATUS
+AmdInitResume (
+ IN AMD_RESUME_PARAMS *ResumeParams
+ );
+
+
+/**********************************************************************
+ * Interface call: AmdS3LateRestore
+ **********************************************************************/
+/// AmdS3LateRestore param structure
+typedef struct {
+ IN OUT AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header
+ IN PLATFORM_CONFIGURATION PlatformConfig; ///< platform operational characteristics.
+ IN AMD_S3_PARAMS S3DataBlock; ///< Save state data
+} AMD_S3LATE_PARAMS;
+
+AGESA_STATUS
+AmdS3LateRestore (
+ IN OUT AMD_S3LATE_PARAMS *S3LateParams
+ );
+
+
+/**********************************************************************
+ * Interface call: AmdS3Save
+ **********************************************************************/
+/// AmdS3Save param structure
+typedef struct {
+ IN OUT AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header
+ IN PLATFORM_CONFIGURATION PlatformConfig; ///< platform operational characteristics.
+ OUT AMD_S3_PARAMS S3DataBlock; ///< Standard header
+ IN FCH_INTERFACE FchInterface; ///< FCH configuration
+} AMD_S3SAVE_PARAMS;
+
+AGESA_STATUS
+AmdS3Save (
+ IN OUT AMD_S3SAVE_PARAMS *AmdS3SaveParams
+ );
+
+
+/**********************************************************************
+ * Interface call: AmdLateRunApTask
+ **********************************************************************/
+/**
+ * Entry point for AP tasking.
+ */
+AGESA_STATUS
+AmdLateRunApTask (
+ IN AP_EXE_PARAMS *AmdApExeParams
+);
+
+//
+// General Services API
+//
+
+/**********************************************************************
+ * Interface service call: AmdGetApicId
+ **********************************************************************/
+/// Request the APIC ID of a particular core.
+
+typedef struct {
+ IN AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header
+ IN UINT8 Socket; ///< The Core's Socket.
+ IN UINT8 Core; ///< The Core id.
+ OUT BOOLEAN IsPresent; ///< The Core is present, and ApicAddress is valid.
+ OUT UINT8 ApicAddress; ///< The Core's APIC ID.
+} AMD_APIC_PARAMS;
+
+/**
+ * Get a specified Core's APIC ID.
+ */
+AGESA_STATUS
+AmdGetApicId (
+ IN OUT AMD_APIC_PARAMS *AmdParamApic
+);
+
+/**********************************************************************
+ * Interface service call: AmdGetPciAddress
+ **********************************************************************/
+/// Request the PCI Address of a Processor Module (that is, its Northbridge)
+
+typedef struct {
+ IN AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header
+ IN UINT8 Socket; ///< The Processor's socket
+ IN UINT8 Module; ///< The Module in that Processor
+ OUT BOOLEAN IsPresent; ///< The Core is present, and PciAddress is valid.
+ OUT PCI_ADDR PciAddress; ///< The Processor's PCI Config Space address (Function 0, Register 0)
+} AMD_GET_PCI_PARAMS;
+
+/**
+ * Get Processor Module's PCI Config Space address.
+ */
+AGESA_STATUS
+AmdGetPciAddress (
+ IN OUT AMD_GET_PCI_PARAMS *AmdParamGetPci
+);
+
+/**********************************************************************
+ * Interface service call: AmdIdentifyCore
+ **********************************************************************/
+/// Request the identity (Socket, Module, Core) of the current Processor Core
+
+typedef struct {
+ IN AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header
+ OUT UINT8 Socket; ///< The current Core's Socket
+ OUT UINT8 Module; ///< The current Core's Processor Module
+ OUT UINT8 Core; ///< The current Core's core id.
+} AMD_IDENTIFY_PARAMS;
+
+/**
+ * "Who am I" for the current running core.
+ */
+AGESA_STATUS
+AmdIdentifyCore (
+ IN OUT AMD_IDENTIFY_PARAMS *AmdParamIdentify
+);
+
+/**********************************************************************
+ * Interface service call: AmdReadEventLog
+ **********************************************************************/
+/// An Event Log Entry.
+typedef struct {
+ IN AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header
+ OUT UINT32 EventClass; ///< The severity of this event, matches AGESA_STATUS.
+ OUT UINT32 EventInfo; ///< The unique event identifier, zero means "no event".
+ OUT UINT32 DataParam1; ///< Data specific to the Event.
+ OUT UINT32 DataParam2; ///< Data specific to the Event.
+ OUT UINT32 DataParam3; ///< Data specific to the Event.
+ OUT UINT32 DataParam4; ///< Data specific to the Event.
+} EVENT_PARAMS;
+
+/**
+ * Read an Event from the Event Log.
+ */
+AGESA_STATUS
+AmdReadEventLog (
+ IN EVENT_PARAMS *Event
+);
+
+/**********************************************************************
+ * Interface service call: AmdIdentifyDimm
+ **********************************************************************/
+/// Request the identity of dimm from system address
+
+typedef struct {
+ IN OUT AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header
+ IN UINT64 MemoryAddress; ///< System Address that needs to be translated to dimm identification.
+ OUT UINT8 SocketId; ///< The socket on which the targeted address locates.
+ OUT UINT8 MemChannelId; ///< The channel on which the targeted address locates.
+ OUT UINT8 DimmId; ///< The dimm on which the targeted address locates.
+ OUT UINT8 ChipSelect; ///< The chip select on which the targeted address locates.
+ OUT UINT8 Bank; ///< The Bank for which the error address resides
+ OUT UINT32 Row; ///< The Row for which the error address resides
+ OUT UINT16 Column; ///< The Column for which the error address resides
+} AMD_IDENTIFY_DIMM;
+
+/**
+ * Get the dimm identification for the address.
+ */
+AGESA_STATUS
+AmdIdentifyDimm (
+ IN OUT AMD_IDENTIFY_DIMM *AmdDimmIdentify
+);
+
+AGESA_STATUS
+AmdIdsRunApTaskLate (
+ IN AP_EXE_PARAMS *AmdApExeParams
+ );
+
+/// Request the 2D Data Eye Training Data
+#define RD_DATAEYE 0
+#define WR_DATAEYE 1
+
+/**********************************************************************
+ * Interface service call: AmdGet2DDataEye
+ **********************************************************************/
+/// Request the training data eye on Socket, Channel, Dimm.
+
+typedef struct _AMD_GET_DATAEYE {
+ IN OUT AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header
+ IN OUT AMD_POST_PARAMS *PostParamsPtr; ///< Pointer to AMD_POST_PARAMS
+ IN UINT8 SocketId; ///< The socket number to get the 2D data eye
+ IN UINT8 MemChannelId; ///< The channel number to get the 2D data eye
+ IN UINT8 DimmId; ///< The dimm number to get the 2D data eye
+ IN UINT8 DataEyeType; ///< Get the 2D data eye on read or write training
+ OUT UINT8* DataEyeBuffer; ///< The buffer to stores the 2D data eye
+} AMD_GET_DATAEYE;
+
+AGESA_STATUS
+AmdGet2DDataEye (
+ IN OUT AMD_GET_DATAEYE *AmdGetDataEye
+ );
+
+#define AGESA_IDS_DFT_VAL 0xFFFF ///< Default value of every uninitlized NV item, the action for it will be ignored
+#define AGESA_IDS_NV_END 0xFFFF ///< Flag specify end of option structure
+/// WARNING: Don't change the comment below, it used as signature for script
+/// AGESA IDS NV ID Definitions
+typedef enum {
+ AGESA_IDS_EXT_ID_START = 0x0000,///< 0x0000 specify the start of external NV id
+
+ AGESA_IDS_NV_UCODE, ///< 0x0001 Enable or disable microcode patching
+
+ AGESA_IDS_NV_TARGET_PSTATE, ///< 0x0002 Set the P-state required to be activated
+ AGESA_IDS_NV_POSTPSTATE, ///< 0x0003 Set the P-state required to be activated through POST
+
+ AGESA_IDS_NV_BANK_INTERLEAVE, ///< 0x0004 Enable or disable Bank Interleave
+ AGESA_IDS_NV_CHANNEL_INTERLEAVE, ///< 0x0005 Enable or disable Channel Interleave
+ AGESA_IDS_NV_NODE_INTERLEAVE, ///< 0x0006 Enable or disable Node Interleave
+ AGESA_IDS_NV_MEMHOLE, ///< 0x0007 Enables or disable memory hole
+
+ AGESA_IDS_NV_SCRUB_REDIRECTION, ///< 0x0008 Enable or disable a write to dram with corrected data
+ AGESA_IDS_NV_DRAM_SCRUB, ///< 0x0009 Set the rate of background scrubbing for DRAM
+ AGESA_IDS_NV_DCACHE_SCRUB, ///< 0x000A Set the rate of background scrubbing for the DCache.
+ AGESA_IDS_NV_L2_SCRUB, ///< 0x000B Set the rate of background scrubbing for the L2 cache
+ AGESA_IDS_NV_L3_SCRUB, ///< 0x000C Set the rate of background scrubbing for the L3 cache
+ AGESA_IDS_NV_ICACHE_SCRUB, ///< 0x000D Set the rate of background scrubbing for the Icache
+ AGESA_IDS_NV_SYNC_ON_ECC_ERROR, ///< 0x000E Enable or disable the sync flood on un-correctable ECC error
+ AGESA_IDS_NV_ECC_SYMBOL_SIZE, ///< 0x000F Set ECC symbol size
+
+ AGESA_IDS_NV_ALL_MEMCLKS, ///< 0x0010 Enable or disable all memory clocks enable
+ AGESA_IDS_NV_DCT_GANGING_MODE, ///< 0x0011 Set the Ganged mode
+ AGESA_IDS_NV_DRAM_BURST_LENGTH32, ///< 0x0012 Set the DRAM Burst Length 32
+ AGESA_IDS_NV_MEMORY_POWER_DOWN, ///< 0x0013 Enable or disable Memory power down mode
+ AGESA_IDS_NV_MEMORY_POWER_DOWN_MODE, ///< 0x0014 Set the Memory power down mode
+ AGESA_IDS_NV_DLL_SHUT_DOWN, ///< 0x0015 Enable or disable DLLShutdown
+ AGESA_IDS_NV_ONLINE_SPARE, ///< 0x0016 Enable or disable the Dram controller to designate a DIMM bank as a spare for logical swap
+
+ AGESA_IDS_NV_HDTOUT, ///< 0x0017 Enable or disable HDTOUT feature
+
+ AGESA_IDS_NV_GNBHDAUDIOEN, ///< 0x0018 Enable or disable GNB HD Audio
+
+ AGESA_IDS_NV_CPB_EN, ///< 0x0019 Core Performance Boost
+
+ AGESA_IDS_NV_HTC_EN, ///< 0x001A HTC Enable
+ AGESA_IDS_NV_HTC_OVERRIDE, ///< 0x001B HTC Override
+ AGESA_IDS_NV_HTC_PSTATE_LIMIT, ///< 0x001C HTC P-state limit select
+ AGESA_IDS_NV_HTC_TEMP_HYS, ///< 0x001D HTC Temperature Hysteresis
+ AGESA_IDS_NV_HTC_ACT_TEMP, ///< 0x001E HTC Activation Temp
+
+ AGESA_IDS_NV_POWER_POLICY, ///< 0x001F Select Platform Power Policy
+ AGESA_IDS_NV_DRAMCON, ///< 0x0020 Specify the mode for controller initialization
+ AGESA_IDS_EXT_ID_END, ///< 0x0021 specify the end of external NV ID
+} IDS_EX_NV_ID;
+
+
+#define IDS_NUM_EXT_NV_ITEM (AGESA_IDS_EXT_ID_END - AGESA_IDS_EXT_ID_START + 1)
+
+
+#endif // _AGESA_H_
diff --git a/src/vendorcode/amd/pi/00730F01/AMD.h b/src/vendorcode/amd/pi/00730F01/AMD.h
new file mode 100644
index 0000000..1b6fdb2
--- /dev/null
+++ b/src/vendorcode/amd/pi/00730F01/AMD.h
@@ -0,0 +1,474 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Agesa structures and definitions
+ *
+ * Contains AMD AGESA core interface
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: Include
+ * @e \$Revision: 281178 $ @e \$Date: 2013-12-18 02:14:15 -0600 (Wed, 18 Dec 2013) $
+ */
+/*****************************************************************************
+ *
+ * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ***************************************************************************/
+
+
+#ifndef _AMD_H_
+#define _AMD_H_
+
+#define Int16FromChar(a,b) (UINT16)((a) << 0 | (b) << 8)
+#define Int32FromChar(a,b,c,d) (UINT32)((a) << 0 | (b) << 8 | (c) << 16 | (d) << 24)
+#define Int64FromChar(a,b,c,d,e,f,g,h) ((UINT64)(Int32FromChar(a,b,c,d)<<32) | (UINT64)Int32FromChar(e,f,g,h))
+
+#define AGESA_REVISION "Arch2008"
+#define AGESA_ID {'A', 'G', 'E', 'S', 'A', 0x00, 0x00, 0x00}
+
+//
+//
+// AGESA Types and Definitions
+//
+//
+#define LAST_ENTRY 0xFFFFFFFFul
+#define IMAGE_SIGNATURE Int32FromChar ('$', 'A', 'M', 'D')
+#define MODULE_SIGNATURE Int32FromChar ('$', 'M', 'O', 'D')
+#define IOCF8 0xCF8
+#define IOCFC 0xCFC
+
+/// The return status for all AGESA public services.
+///
+/// Services return the most severe status of any logged event. Status other than SUCCESS, UNSUPPORTED, and BOUNDS_CHK
+/// will have log entries with more detail.
+///
+typedef enum {
+ AGESA_SUCCESS = 0, ///< The service completed normally. Info may be logged.
+ AGESA_UNSUPPORTED, ///< The dispatcher or create struct had an unimplemented function requested.
+ ///< Not logged.
+ AGESA_BOUNDS_CHK, ///< A dynamic parameter was out of range and the service was not provided.
+ ///< Example, memory address not installed, heap buffer handle not found.
+ ///< Not Logged.
+ // AGESA_STATUS of greater severity (the ones below this line), always have a log entry available.
+ AGESA_ALERT, ///< An observed condition, but no loss of function. See Log.
+ AGESA_WARNING, ///< Possible or minor loss of function. See Log.
+ AGESA_ERROR, ///< Significant loss of function, boot may be possible. See Log.
+ AGESA_CRITICAL, ///< Continue boot only to notify user. See Log.
+ AGESA_FATAL, ///< Halt booting. See Log, however Fatal errors pertaining to heap problems
+ ///< may not be able to reliably produce log events.
+ AgesaStatusMax ///< Not a status, for limit checking.
+} AGESA_STATUS;
+
+/// For checking whether a status is at or above the mandatory log level.
+#define AGESA_STATUS_LOG_LEVEL AGESA_ALERT
+
+/**
+ * Callout method to the host environment.
+ *
+ * Callout using a dispatch with appropriate thunk layer, which is determined by the host environment.
+ *
+ * @param[in] Function The specific callout function being invoked.
+ * @param[in] FcnData Function specific data item.
+ * @param[in,out] ConfigPtr Reference to Callout params.
+ */
+typedef AGESA_STATUS (*CALLOUT_ENTRY) (
+ IN UINT32 Function,
+ IN UINTN FcnData,
+ IN OUT VOID *ConfigPtr
+ );
+
+typedef AGESA_STATUS (*IMAGE_ENTRY) (VOID *ConfigPtr);
+typedef AGESA_STATUS (*MODULE_ENTRY) (VOID *ConfigPtr);
+
+///This allocation type is used by the AmdCreateStruct entry point
+typedef enum {
+ PreMemHeap = 0, ///< Create heap in cache.
+ PostMemDram, ///< Create heap in memory.
+ ByHost ///< Create heap by Host.
+} ALLOCATION_METHOD;
+
+/// These width descriptors are used by the library function, and others, to specify the data size
+typedef enum ACCESS_WIDTH {
+ AccessWidth8 = 1, ///< Access width is 8 bits.
+ AccessWidth16, ///< Access width is 16 bits.
+ AccessWidth32, ///< Access width is 32 bits.
+ AccessWidth64, ///< Access width is 64 bits.
+
+ AccessS3SaveWidth8 = 0x81, ///< Save 8 bits data.
+ AccessS3SaveWidth16, ///< Save 16 bits data.
+ AccessS3SaveWidth32, ///< Save 32 bits data.
+ AccessS3SaveWidth64, ///< Save 64 bits data.
+} ACCESS_WIDTH;
+
+/// AGESA struct name
+typedef enum {
+ // AGESA BASIC FUNCTIONS
+ AMD_INIT_RECOVERY = 0x00021000, ///< AmdInitRecovery entry point handle
+ AMD_CREATE_STRUCT = 0x00022000, ///< AmdCreateStruct handle
+ AMD_INIT_EARLY = 0x00023000, ///< AmdInitEarly entry point handle
+ AMD_INIT_ENV = 0x00024000, ///< AmdInitEnv entry point handle
+ AMD_INIT_LATE = 0x00025000, ///< AmdInitLate entry point handle
+ AMD_INIT_MID = 0x00026000, ///< AmdInitMid entry point handle
+ AMD_INIT_POST = 0x00027000, ///< AmdInitPost entry point handle
+ AMD_INIT_RESET = 0x00028000, ///< AmdInitReset entry point handle
+ AMD_INIT_RESUME = 0x00029000, ///< AmdInitResume entry point handle
+ AMD_RELEASE_STRUCT = 0x0002A000, ///< AmdReleaseStruct handle
+ AMD_S3LATE_RESTORE = 0x0002B000, ///< AmdS3LateRestore entry point handle
+ AMD_S3_SAVE = 0x0002C000, ///< AmdS3Save entry point handle
+ AMD_GET_APIC_ID = 0x0002D000, ///< AmdGetApicId entry point handle
+ AMD_GET_PCI_ADDRESS = 0x0002E000, ///< AmdGetPciAddress entry point handle
+ AMD_IDENTIFY_CORE = 0x0002F000, ///< AmdIdentifyCore general service handle
+ AMD_READ_EVENT_LOG = 0x00030000, ///< AmdReadEventLog general service handle
+ AMD_GET_EXECACHE_SIZE = 0x00031000, ///< AmdGetAvailableExeCacheSize general service handle
+ AMD_LATE_RUN_AP_TASK = 0x00032000, ///< AmdLateRunApTask entry point handle
+ AMD_IDENTIFY_DIMMS = 0x00033000, ///< AmdIdentifyDimm general service handle
+ AMD_GET_2D_DATA_EYE = 0x00034000, ///< AmdGet2DDataEye general service handle
+ AMD_HEAP_ALLOCATE_BUFFER = 0x00038000,
+ AMD_HEAP_DEALLOCATE_BUFFER = 0x00039000,
+ FCH_INIT_RESET = 0x00040000,
+ FCH_INIT_ENV = 0x00041000,
+ FCH_INIT_MID = 0x00042000,
+ FCH_INIT_LATE = 0x00043000,
+ FCH_INIT_S3_EARLY_RESTORE = 0x00044000,
+ FCH_INIT_S3_LATE_RESTORE = 0x00045000,
+ AMD_SET_VALUE = 0x00081000,
+ AMD_GET_VALUE = 0x00082000,
+} AGESA_STRUCT_NAME;
+
+ /* ResetType constant values */
+#define WARM_RESET_WHENEVER 1
+#define COLD_RESET_WHENEVER 2
+#define WARM_RESET_IMMEDIATELY 3
+#define COLD_RESET_IMMEDIATELY 4
+
+
+// AGESA Structures
+
+/// The standard header for all AGESA services.
+/// For internal AGESA naming conventions, see @ref amdconfigparamname .
+typedef struct {
+ IN VOID * ImageBasePtr; ///< The AGESA Image base address.
+ IN UINT32 Func; ///< The service desired
+ IN VOID * AltImageBasePtr; ///< Alternate Image location
+ IN CALLOUT_ENTRY CalloutPtr; ///< For Callout from AGESA
+ IN UINT8 HeapStatus; ///< For heap status from boot time slide.
+ IN UINT64 HeapBasePtr; ///< Location of the heap
+ IN OUT UINT8 Reserved[7]; ///< This space is reserved for future use.
+} AMD_CONFIG_PARAMS;
+
+
+/// Create Struct Interface.
+typedef struct {
+ IN AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header
+ IN AGESA_STRUCT_NAME AgesaFunctionName; ///< The service to init
+ IN ALLOCATION_METHOD AllocationMethod; ///< How to handle buffer allocation
+ IN OUT UINT32 NewStructSize; ///< The size of the allocated data, in for ByHost, else out only.
+ IN OUT VOID *NewStructPtr; ///< The struct for the service.
+ ///< The struct to init for ByHost allocation,
+ ///< the initialized struct on return.
+} AMD_INTERFACE_PARAMS;
+
+#define FUNC_0 0 // bit-placed for PCI address creation
+#define FUNC_1 1
+#define FUNC_2 2
+#define FUNC_3 3
+#define FUNC_4 4
+#define FUNC_5 5
+#define FUNC_6 6
+#define FUNC_7 7
+
+/// AGESA Binary module header structure
+typedef struct {
+ IN UINT32 Signature; ///< Binary Signature
+ IN CHAR8 CreatorID[8]; ///< 8 characters ID
+ IN CHAR8 Version[12]; ///< 12 characters version
+ IN UINT32 ModuleInfoOffset; ///< Offset of module
+ IN UINT32 EntryPointAddress; ///< Entry address
+ IN UINT32 ImageBase; ///< Image base
+ IN UINT32 RelocTableOffset; ///< Relocate Table offset
+ IN UINT32 ImageSize; ///< Size
+ IN UINT16 Checksum; ///< Checksum
+ IN UINT8 ImageType; ///< Type
+ IN UINT8 V_Reserved; ///< Reserved
+} AMD_IMAGE_HEADER;
+
+/// AGESA Binary module header structure
+typedef struct _AMD_MODULE_HEADER {
+ IN UINT32 ModuleHeaderSignature; ///< Module signature
+ IN CHAR8 ModuleIdentifier[8]; ///< 8 characters ID
+ IN CHAR8 ModuleVersion[12]; ///< 12 characters version
+ IN VOID *ModuleDispatcher; ///< A pointer point to dispatcher
+ IN struct _AMD_MODULE_HEADER *NextBlock; ///< Next module header link
+} AMD_MODULE_HEADER;
+
+// AMD_CODE_HEADER Signatures.
+#define AGESA_CODE_SIGNATURE {'!', '!', '!', 'A', 'G', 'E', 'S', 'A'}
+#define CIMXNB_CODE_SIGNATURE {'!', '!', 'C', 'I', 'M', 'X', 'N', 'B'}
+#define CIMXSB_CODE_SIGNATURE {'!', '!', 'C', 'I', 'M', 'X', 'S', 'B'}
+
+/// AGESA_CODE_SIGNATURE
+typedef struct {
+ IN CHAR8 Signature[8]; ///< code header Signature
+ IN CHAR8 ComponentName[16]; ///< 16 character name of the code module
+ IN CHAR8 Version[12]; ///< 12 character version string
+ IN CHAR8 TerminatorNull; ///< null terminated string
+ IN CHAR8 VerReserved[7]; ///< reserved space
+} AMD_CODE_HEADER;
+
+/// Extended PCI address format
+typedef struct {
+ IN OUT UINT32 Register:12; ///< Register offset
+ IN OUT UINT32 Function:3; ///< Function number
+ IN OUT UINT32 Device:5; ///< Device number
+ IN OUT UINT32 Bus:8; ///< Bus number
+ IN OUT UINT32 Segment:4; ///< Segment
+} EXT_PCI_ADDR;
+
+/// Union type for PCI address
+typedef union _PCI_ADDR {
+ IN UINT32 AddressValue; ///< Formal address
+ IN EXT_PCI_ADDR Address; ///< Extended address
+} PCI_ADDR;
+
+// SBDFO - Segment Bus Device Function Offset
+// 31:28 Segment (4-bits)
+// 27:20 Bus (8-bits)
+// 19:15 Device (5-bits)
+// 14:12 Function(3-bits)
+// 11:00 Offset (12-bits)
+
+#define MAKE_SBDFO(Seg, Bus, Dev, Fun, Off) ((((UINT32) (Seg)) << 28) | (((UINT32) (Bus)) << 20) | \
+ (((UINT32)(Dev)) << 15) | (((UINT32)(Fun)) << 12) | ((UINT32)(Off)))
+#define ILLEGAL_SBDFO 0xFFFFFFFFul
+
+/// CPUID data received registers format
+typedef struct {
+ OUT UINT32 EAX_Reg; ///< CPUID instruction result in EAX
+ OUT UINT32 EBX_Reg; ///< CPUID instruction result in EBX
+ OUT UINT32 ECX_Reg; ///< CPUID instruction result in ECX
+ OUT UINT32 EDX_Reg; ///< CPUID instruction result in EDX
+} CPUID_DATA;
+
+// Topology Services definitions and macros
+#define TOPOLOGY_LIST_TERMINAL 0xFF ///< End of list.
+
+
+#ifndef BIT0
+ #define BIT0 0x0000000000000001ull
+#endif
+#ifndef BIT1
+ #define BIT1 0x0000000000000002ull
+#endif
+#ifndef BIT2
+ #define BIT2 0x0000000000000004ull
+#endif
+#ifndef BIT3
+ #define BIT3 0x0000000000000008ull
+#endif
+#ifndef BIT4
+ #define BIT4 0x0000000000000010ull
+#endif
+#ifndef BIT5
+ #define BIT5 0x0000000000000020ull
+#endif
+#ifndef BIT6
+ #define BIT6 0x0000000000000040ull
+#endif
+#ifndef BIT7
+ #define BIT7 0x0000000000000080ull
+#endif
+#ifndef BIT8
+ #define BIT8 0x0000000000000100ull
+#endif
+#ifndef BIT9
+ #define BIT9 0x0000000000000200ull
+#endif
+#ifndef BIT10
+ #define BIT10 0x0000000000000400ull
+#endif
+#ifndef BIT11
+ #define BIT11 0x0000000000000800ull
+#endif
+#ifndef BIT12
+ #define BIT12 0x0000000000001000ull
+#endif
+#ifndef BIT13
+ #define BIT13 0x0000000000002000ull
+#endif
+#ifndef BIT14
+ #define BIT14 0x0000000000004000ull
+#endif
+#ifndef BIT15
+ #define BIT15 0x0000000000008000ull
+#endif
+#ifndef BIT16
+ #define BIT16 0x0000000000010000ull
+#endif
+#ifndef BIT17
+ #define BIT17 0x0000000000020000ull
+#endif
+#ifndef BIT18
+ #define BIT18 0x0000000000040000ull
+#endif
+#ifndef BIT19
+ #define BIT19 0x0000000000080000ull
+#endif
+#ifndef BIT20
+ #define BIT20 0x0000000000100000ull
+#endif
+#ifndef BIT21
+ #define BIT21 0x0000000000200000ull
+#endif
+#ifndef BIT22
+ #define BIT22 0x0000000000400000ull
+#endif
+#ifndef BIT23
+ #define BIT23 0x0000000000800000ull
+#endif
+#ifndef BIT24
+ #define BIT24 0x0000000001000000ull
+#endif
+#ifndef BIT25
+ #define BIT25 0x0000000002000000ull
+#endif
+#ifndef BIT26
+ #define BIT26 0x0000000004000000ull
+#endif
+#ifndef BIT27
+ #define BIT27 0x0000000008000000ull
+#endif
+#ifndef BIT28
+ #define BIT28 0x0000000010000000ull
+#endif
+#ifndef BIT29
+ #define BIT29 0x0000000020000000ull
+#endif
+#ifndef BIT30
+ #define BIT30 0x0000000040000000ull
+#endif
+#ifndef BIT31
+ #define BIT31 0x0000000080000000ull
+#endif
+#ifndef BIT32
+ #define BIT32 0x0000000100000000ull
+#endif
+#ifndef BIT33
+ #define BIT33 0x0000000200000000ull
+#endif
+#ifndef BIT34
+ #define BIT34 0x0000000400000000ull
+#endif
+#ifndef BIT35
+ #define BIT35 0x0000000800000000ull
+#endif
+#ifndef BIT36
+ #define BIT36 0x0000001000000000ull
+#endif
+#ifndef BIT37
+ #define BIT37 0x0000002000000000ull
+#endif
+#ifndef BIT38
+ #define BIT38 0x0000004000000000ull
+#endif
+#ifndef BIT39
+ #define BIT39 0x0000008000000000ull
+#endif
+#ifndef BIT40
+ #define BIT40 0x0000010000000000ull
+#endif
+#ifndef BIT41
+ #define BIT41 0x0000020000000000ull
+#endif
+#ifndef BIT42
+ #define BIT42 0x0000040000000000ull
+#endif
+#ifndef BIT43
+ #define BIT43 0x0000080000000000ull
+#endif
+#ifndef BIT44
+ #define BIT44 0x0000100000000000ull
+#endif
+#ifndef BIT45
+ #define BIT45 0x0000200000000000ull
+#endif
+#ifndef BIT46
+ #define BIT46 0x0000400000000000ull
+#endif
+#ifndef BIT47
+ #define BIT47 0x0000800000000000ull
+#endif
+#ifndef BIT48
+ #define BIT48 0x0001000000000000ull
+#endif
+#ifndef BIT49
+ #define BIT49 0x0002000000000000ull
+#endif
+#ifndef BIT50
+ #define BIT50 0x0004000000000000ull
+#endif
+#ifndef BIT51
+ #define BIT51 0x0008000000000000ull
+#endif
+#ifndef BIT52
+ #define BIT52 0x0010000000000000ull
+#endif
+#ifndef BIT53
+ #define BIT53 0x0020000000000000ull
+#endif
+#ifndef BIT54
+ #define BIT54 0x0040000000000000ull
+#endif
+#ifndef BIT55
+ #define BIT55 0x0080000000000000ull
+#endif
+#ifndef BIT56
+ #define BIT56 0x0100000000000000ull
+#endif
+#ifndef BIT57
+ #define BIT57 0x0200000000000000ull
+#endif
+#ifndef BIT58
+ #define BIT58 0x0400000000000000ull
+#endif
+#ifndef BIT59
+ #define BIT59 0x0800000000000000ull
+#endif
+#ifndef BIT60
+ #define BIT60 0x1000000000000000ull
+#endif
+#ifndef BIT61
+ #define BIT61 0x2000000000000000ull
+#endif
+#ifndef BIT62
+ #define BIT62 0x4000000000000000ull
+#endif
+#ifndef BIT63
+ #define BIT63 0x8000000000000000ull
+#endif
+
+#endif // _AMD_H_
diff --git a/src/vendorcode/amd/pi/00730F01/Dispatcher.h b/src/vendorcode/amd/pi/00730F01/Dispatcher.h
new file mode 100644
index 0000000..eecdd0e
--- /dev/null
+++ b/src/vendorcode/amd/pi/00730F01/Dispatcher.h
@@ -0,0 +1,51 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD Pushhigh Interface
+ *
+ * Contains interface to Pushhigh entry
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: Legacy
+ * @e \$Revision: 84150 $ @e \$Date: 2012-12-12 15:46:25 -0600 (Wed, 12 Dec 2012) $
+ *
+ */
+/*****************************************************************************
+ *
+ * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ***************************************************************************
+ */
+
+#ifndef _DISPATCHER_H_
+#define _DISPATCHER_H_
+
+// AGESA function prototypes
+AGESA_STATUS CALLCONV AmdAgesaDispatcher ( IN OUT VOID *ConfigPtr );
+AGESA_STATUS CALLCONV AmdAgesaCallout ( IN UINT32 Func, IN UINT32 Data, IN OUT VOID *ConfigPtr );
+
+#endif // _DISPATCHER_H_
diff --git a/src/vendorcode/amd/pi/00730F01/Include/Filecode.h b/src/vendorcode/amd/pi/00730F01/Include/Filecode.h
new file mode 100644
index 0000000..c2893a7
--- /dev/null
+++ b/src/vendorcode/amd/pi/00730F01/Include/Filecode.h
@@ -0,0 +1,823 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Collectively assign unique filecodes for assert and debug to each source file.
+ *
+ * Publish values for decorated filenames, which can be used for
+ * ASSERT and debug support using a preprocessor define like:
+ * @n <tt> \#define FILECODE MY_C_FILENAME_FILECODE </tt> @n
+ * This file serves as a reference for debugging to associate the code and filename.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: Include
+ * @e \$Revision: 282320 $ @e \$Date: 2014-01-09 20:13:34 -0600 (Thu, 09 Jan 2014) $
+ */
+/*****************************************************************************
+ *
+ * Copyright (c) 2008 - 2014, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ***************************************************************************/
+
+#ifndef _FILECODE_H_
+#define _FILECODE_H_
+
+#define UNASSIGNED_FILE_FILECODE (0xFFFF)
+
+/// For debug use in any Platform's options C file.
+/// Can be reused for platforms and image builds, since only one options file can be built.
+#define PLATFORM_SPECIFIC_OPTIONS_FILECODE (0xBBBB)
+
+
+#define PROC_GNB_COMMON_GNBLIBFEATURES_FILECODE (0xA001)
+#define PROC_GNB_GNBINITATEARLY_FILECODE (0xA017)
+#define PROC_GNB_GNBINITATENV_FILECODE (0xA020)
+#define PROC_GNB_GNBINITATLATE_FILECODE (0xA021)
+#define PROC_GNB_GNBINITATMID_FILECODE (0xA022)
+#define PROC_GNB_GNBINITATPOST_FILECODE (0xA023)
+#define PROC_GNB_GNBINITATRESET_FILECODE (0xA024)
+#define PROC_GNB_MODULES_GNBCOMMONLIB_GNBLIB_FILECODE (0xA025)
+#define PROC_GNB_MODULES_GNBCOMMONLIB_GNBLIBCPUACC_FILECODE (0xA026)
+#define PROC_GNB_MODULES_GNBCOMMONLIB_GNBLIBHEAP_FILECODE (0xA027)
+#define PROC_GNB_MODULES_GNBCOMMONLIB_GNBLIBIOACC_FILECODE (0xA028)
+#define PROC_GNB_MODULES_GNBCOMMONLIB_GNBLIBMEMACC_FILECODE (0xA029)
+#define PROC_GNB_MODULES_GNBCOMMONLIB_GNBLIBPCI_FILECODE (0xA02A)
+#define PROC_GNB_MODULES_GNBCOMMONLIB_GNBLIBPCIACC_FILECODE (0xA030)
+#define PROC_GNB_MODULES_GNBGFXINITLIBV1_GFXCARDINFO_FILECODE (0xA031)
+#define PROC_GNB_MODULES_GNBGFXINITLIBV1_GFXENUMCONNECTORS_FILECODE (0xA032)
+#define PROC_GNB_MODULES_GNBGFXINITLIBV1_GFXPOWERPLAYTABLE_FILECODE (0xA033)
+#define PROC_GNB_MODULES_GNBNBINITLIBV1_GNBNBINITLIBV1_FILECODE (0xA034)
+#define PROC_GNB_MODULES_GNBPCIECONFIG_PCIECONFIGDATA_FILECODE (0xA036)
+#define PROC_GNB_MODULES_GNBPCIECONFIG_PCIECONFIGLIB_FILECODE (0xA037)
+#define PROC_GNB_MODULES_GNBPCIECONFIG_PCIEINPUTPARSER_FILECODE (0xA038)
+#define PROC_GNB_MODULES_GNBPCIECONFIG_PCIEMAPTOPOLOGY_FILECODE (0xA039)
+#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEASPMBLACKLIST_FILECODE (0xA03B)
+#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEASPMEXITLATENCY_FILECODE (0xA03C)
+#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEPHYSERVICES_FILECODE (0xA03D)
+#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEPIFSERVICES_FILECODE (0xA03E)
+#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEPORTREGACC_FILECODE (0xA03F)
+#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEPORTSERVICES_FILECODE (0xA041)
+#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEPOWERMGMT_FILECODE (0xA043)
+#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIESILICONSERVICES_FILECODE (0xA045)
+#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIETIMER_FILECODE (0xA046)
+#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIETOPOLOGYSERVICES_FILECODE (0xA047)
+#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEUTILITYLIB_FILECODE (0xA048)
+#define PROC_GNB_MODULES_GNBPCIEINITLIBV1_PCIEWRAPPERREGACC_FILECODE (0xA049)
+#define PROC_GNB_MODULES_GNBPCIETRAININGV1_PCIETRAINING_FILECODE (0xA04A)
+#define PROC_GNB_MODULES_GNBPCIETRAININGV1_PCIEWORKAROUNDS_FILECODE (0xA04B)
+#define PROC_GNB_MODULES_GNBPCIECOMMCLKCFG_PCIECOMMCLKCFG_FILECODE (0xA04C)
+
+#define PROC_GNB_MODULES_GNBGFXCONFIG_GFXCONFIGENV_FILECODE (0xA08E)
+#define PROC_GNB_MODULES_GNBGFXCONFIG_GFXCONFIGPOST_FILECODE (0xA08F)
+#define PROC_GNB_MODULES_GNBTABLE_GNBTABLE_FILECODE (0xA090)
+#define PROC_GNB_MODULES_GNBGFXINITLIBV1_GNBGFXINITLIBV1_FILECODE (0xA091)
+#define PROC_GNB_MODULES_GNBGFXCONFIG_GFXCONFIGLIB_FILECODE (0xA093)
+#define PROC_GNB_MODULES_GNBPCIEINITLIBV4_PCIEWRAPPERSERVICESV4_FILECODE (0xA0A6)
+#define PROC_GNB_MODULES_GNBIOMMUIVRS_GNBIOMMUIVRS_FILECODE (0xA0A7)
+#define PROC_GNB_MODULES_GNBIVRSLIB_GNBIVRSLIB_FILECODE (0xA0A8)
+#define PROC_GNB_MODULES_GNBNBINITLIBV4_GNBNBINITLIBV4_FILECODE (0xA0A9)
+#define PROC_GNB_MODULES_GNBFAMTRANSLATION_GNBPCIETRANSLATION_FILECODE (0xA0AA)
+
+#define PROC_GNB_MODULES_GNBSBLIB_GNBSBPCIE_FILECODE (0xA0BA)
+#define PROC_GNB_MODULES_GNBSBLIB_GNBSBLIB_FILECODE (0xA0BB)
+#define PROC_GNB_MODULES_GNBSBIOMMULIB_GNBSBIOMMULIB_FILECODE (0xA0BC)
+#define PROC_GNB_MODULES_GNBCOMMONLIB_GNBTIMERLIB_FILECODE (0xA0BD)
+#define PROC_GNB_MODULES_GNBSSOCKETLIB_GNBSSOCKETLIB_FILECODE (0xA0BF)
+#define PROC_GNB_MODULES_GNBPCIECONFIG_GNBHANDLELIB_FILECODE (0xA0C0)
+#define PROC_GNB_MODULES_GNBPCIEASPM_PCIEASPM_FILECODE (0xA0C2)
+
+#define PROC_GNB_MODULES_GNBPCIEINITLIBV5_PCIEASPMEXITLATENCYV5_FILECODE (0xA0C5)
+#define PROC_GNB_MODULES_GNBPCIEINITLIBV5_PCIEPIFSERVICESV5_FILECODE (0xA0C6)
+#define PROC_GNB_MODULES_GNBPCIEINITLIBV5_PCIEPORTSERVICESV5_FILECODE (0xA0C7)
+#define PROC_GNB_MODULES_GNBPCIEINITLIBV5_PCIEPOWERMGMTV5_FILECODE (0xA0C8)
+#define PROC_GNB_MODULES_GNBPCIEINITLIBV5_PCIESILICONSERVICESV5_FILECODE (0xA0C9)
+#define PROC_GNB_MODULES_GNBPCIEINITLIBV5_PCIEWRAPPERSERVICESV5_FILECODE (0xA0CA)
+#define PROC_GNB_MODULES_GNBNBINITLIBV5_GNBNBINITLIBV5_FILECODE (0xA0CB)
+
+#define PROC_GNB_MODULES_GNBFAMTRANSLATION_GNBTRANSLATION_FILECODE (0xA0DB)
+#define PROC_GNB_MODULES_GNBPCIEINITLIBV4_PCIEPOWERMGMTV4_FILECODE (0xA0DC)
+#define PROC_GNB_MODULES_GNBPCIEINITLIBV4_PCIEPORTSERVICESV4_FILECODE (0xA0DD)
+
+#define PROC_GNB_MODULES_GNBGFXCONFIG_GFXCONFIGMID_FILECODE (0xA0E0)
+
+#define PROC_GNB_MODULES_GNBIOAPIC_GNBIOAPIC_FILECODE (0xA0EE)
+
+#define PROC_GNB_MODULES_GNBPCIEMAXPAYLOAD_PCIEMAXPAYLOAD_FILECODE (0xA0F4)
+#define PROC_GNB_MODULES_GNBPCIECLKPM_PCIECLKPM_FILECODE (0xA0F5)
+
+#define PROC_GNB_MODULES_GNBPCIEINITLIBV5_PCIETOPOLOGYSERVICESV5_FILECODE (0xA100)
+#define PROC_GNB_MODULES_GNBPCIETRAININGV2_PCIETRAININGV2_FILECODE (0xA101)
+#define PROC_GNB_MODULES_GNBPCIETRAININGV2_PCIEWORKAROUNDSV2_FILECODE (0xA102)
+
+#define PROC_RECOVERY_GNB_GNBRECOVERY_FILECODE (0xAE01)
+#define PROC_RECOVERY_GNB_NBINITRECOVERY_FILECODE (0xAE02)
+#define PROC_GNB_GNBINITATS3SAVE_FILECODE (0xAE03)
+#define PROC_GNB_MODULES_GNBSVIEW_GNBSVIEW_FILECODE (0xAE04)
+
+#define PROC_GNB_MODULES_GNBIOMMUSCRATCH_GNBIOMMUSCRATCH_FILECODE (0xAE18)
+#define PROC_GNB_MODULES_GNBSMULIBV7_GNBSMUINITLIBV7_FILECODE (0xAE1A)
+
+#define PROC_GNB_MODULES_GNBPCIEALIBV2_PCIEALIBV2_FILECODE (0xAE33)
+#define PROC_GNB_MODULES_GNBURALIBV1_GNBURALIBV1_FILECODE (0xAE3A)
+#define PROC_GNB_MODULES_GNBGFXINTTABLEV3_GFXLIBV3_FILECODE (0xAE41)
+#define PROC_GNB_MODULES_GNBGFXINTTABLEV3_GFXINTEGRATEDINFOTABLE_FILECODE (0xAE42)
+#define PROC_GNB_MODULES_GNBGFXINTTABLEV3_GFXPWRPLAYTABLE_FILECODE (0xAE43)
+#define PROC_GNB_MODULES_GNBSCSLIBV1_GNBSCSLIBV1_FILECODE (0xAE44)
+
+#define PROC_GNB_MODULES_GNBINITML_GFXENVINITML_FILECODE (0xAE50)
+#define PROC_GNB_MODULES_GNBINITML_GFXINTEGRATEDINFOTABLEML_FILECODE (0xAE51)
+#define PROC_GNB_MODULES_GNBINITML_GFXMIDINITML_FILECODE (0xAE52)
+#define PROC_GNB_MODULES_GNBINITML_GFXPOSTINITML_FILECODE (0xAE53)
+#define PROC_GNB_MODULES_GNBINITML_GFXLIBML_FILECODE (0xAE54)
+#define PROC_GNB_MODULES_GNBINITML_GNBEARLYINITML_FILECODE (0xAE55)
+#define PROC_GNB_MODULES_GNBINITML_GNBENVINITML_FILECODE (0xAE56)
+#define PROC_GNB_MODULES_GNBINITML_GNBMIDINITML_FILECODE (0xAE57)
+#define PROC_GNB_MODULES_GNBINITML_GNBPOSTINITML_FILECODE (0xAE58)
+#define PROC_GNB_MODULES_GNBINITML_GNBREGISTERACCML_FILECODE (0xAE59)
+#define PROC_GNB_MODULES_GNBINITML_PCIECOMPLEXDATAML_FILECODE (0xAE5A)
+#define PROC_GNB_MODULES_GNBINITML_PCIECONFIGML_FILECODE (0xAE5B)
+#define PROC_GNB_MODULES_GNBINITML_PCIEEARLYINITML_FILECODE (0xAE5C)
+#define PROC_GNB_MODULES_GNBINITML_PCIEENVINITML_FILECODE (0xAE5D)
+#define PROC_GNB_MODULES_GNBINITML_PCIEMIDINITML_FILECODE (0xAE5F)
+#define PROC_GNB_MODULES_GNBINITML_PCIEPOSTINITML_FILECODE (0xAE60)
+#define PROC_GNB_MODULES_GNBINITML_PCIELIBML_FILECODE (0xAE61)
+#define PROC_GNB_MODULES_GNBINITML_GFXGMCINITML_FILECODE (0xAE62)
+#define PROC_GNB_MODULES_GNBINITML_ALIBML_FILECODE (0xAE63)
+#define PROC_GNB_MODULES_GNBINITML_GNBFUSETABLEML_FILECODE (0xAE64)
+#define PROC_GNB_MODULES_GNBINITML_GFXSAMUINITML_FILECODE (0xAE65)
+#define PROC_GNB_MODULES_GNBINITML_GNBURAML_FILECODE (0xAE66)
+#define PROC_GNB_MODULES_GNBINITML_GNBURATOKENMAPML_FILECODE (0xAE67)
+#define PROC_GNB_MODULES_GNBINITML_GNBIOMMUIVRSML_FILECODE (0xAE68)
+#define PROC_GNB_MODULES_GNBINITML_GNBPSPML_FILECODE (0xAE69)
+#define PROC_GNB_MODULES_GNBINITML_GNBSMUBIOSTABLEML_FILECODE (0xAE6A)
+
+// FCH
+#define PROC_FCH_COMMON_ACPILIB_FILECODE (0xB010)
+#define PROC_FCH_COMMON_FCHLIB_FILECODE (0xB011)
+#define PROC_FCH_COMMON_FCHCOMMON_FILECODE (0xB012)
+#define PROC_FCH_COMMON_FCHCOMMONSMM_FILECODE (0xB013)
+#define PROC_FCH_COMMON_MEMLIB_FILECODE (0xB014)
+#define PROC_FCH_COMMON_PCILIB_FILECODE (0xB015)
+#define PROC_FCH_COMMON_FCHPELIB_FILECODE (0xB016)
+#define UEFI_DXE_AMDIGPUVGACONTROLDXE_AMDIGPUVGACONTROLDXE_FILECODE (0xB218)
+#define UEFI_SMM_MEMSMMLIB_MEMSMMLIB_FILECODE (0xB2C1)
+#define UEFI_SMM_MEMSMMLIB_ML_DRAMMAPML_FILECODE (0xB2C4)
+#define PROC_FCH_AVALON_AVALONAZALIA_AVALONAZALIARESET_FILECODE (0xB300)
+#define PROC_FCH_AVALON_AVALONAZALIA_AVALONAZALIAENV_FILECODE (0xB301)
+#define PROC_FCH_AVALON_AVALONAZALIA_AVALONAZALIAMID_FILECODE (0xB302)
+#define PROC_FCH_AVALON_AVALONAZALIA_AVALONAZALIALATE_FILECODE (0xB303)
+#define PROC_FCH_AVALON_AVALONHWACPI_AVALONHWACPIRESET_FILECODE (0xB310)
+#define PROC_FCH_AVALON_AVALONHWACPI_AVALONHWACPIENV_FILECODE (0xB311)
+#define PROC_FCH_AVALON_AVALONHWACPI_AVALONHWACPIMID_FILECODE (0xB312)
+#define PROC_FCH_AVALON_AVALONHWACPI_AVALONHWACPILATE_FILECODE (0xB313)
+#define PROC_FCH_AVALON_AVALONHWACPI_AVALONSSSERVICE_FILECODE (0xB314)
+#define PROC_FCH_AVALON_AVALONHWACPI_AVALONHWACPIENVSERVICE_FILECODE (0xB315)
+#define PROC_FCH_AVALON_AVALONHWACPI_AVALONHWACPIMIDSERVICE_FILECODE (0xB316)
+#define PROC_FCH_AVALON_AVALONHWACPI_AVALONHWACPILATESERVICE_FILECODE (0xB317)
+#define PROC_FCH_AVALON_AVALONHWM_AVALONHWMRESET_FILECODE (0xB320)
+#define PROC_FCH_AVALON_AVALONHWM_AVALONHWMENV_FILECODE (0xB321)
+#define PROC_FCH_AVALON_AVALONHWM_AVALONHWMMID_FILECODE (0xB322)
+#define PROC_FCH_AVALON_AVALONHWM_AVALONHWMLATE_FILECODE (0xB323)
+#define PROC_FCH_AVALON_AVALONHWM_AVALONHWMENVSERVICE_FILECODE (0xB324)
+#define PROC_FCH_AVALON_AVALONHWM_AVALONHWMMIDSERVICE_FILECODE (0xB325)
+#define PROC_FCH_AVALON_AVALONHWM_AVALONHWMLATESERVICE_FILECODE (0xB326)
+#define PROC_FCH_AVALON_AVALONINTERFACE_AVALONFCHINITRESET_FILECODE (0xB327)
+#define PROC_FCH_AVALON_AVALONINTERFACE_AVALONFCHINITENV_FILECODE (0xB328)
+#define PROC_FCH_AVALON_AVALONINTERFACE_AVALONFCHINITMID_FILECODE (0xB329)
+#define PROC_FCH_AVALON_AVALONINTERFACE_AVALONFCHINITLATE_FILECODE (0xB32A)
+#define PROC_FCH_AVALON_AVALONINTERFACE_AVALONFCHINITS3_FILECODE (0xB32B)
+#define PROC_FCH_AVALON_AVALONINTERFACE_AVALONINITRESETDEF_FILECODE (0xB32C)
+#define PROC_FCH_AVALON_AVALONINTERFACE_AVALONINITENVDEF_FILECODE (0xB32D)
+#define PROC_FCH_AVALON_AVALONINTERFACE_AVALONFCHTASKLAUNCHER_FILECODE (0xB32E)
+#define PROC_FCH_AVALON_AVALONIMC_AVALONIMCRESET_FILECODE (0xB330)
+#define PROC_FCH_AVALON_AVALONIMC_AVALONIMCENV_FILECODE (0xB331)
+#define PROC_FCH_AVALON_AVALONIMC_AVALONIMCMID_FILECODE (0xB332)
+#define PROC_FCH_AVALON_AVALONIMC_AVALONIMCLATE_FILECODE (0xB333)
+#define PROC_FCH_AVALON_AVALONIMC_AVALONFCHECRESET_FILECODE (0xB334)
+#define PROC_FCH_AVALON_AVALONIMC_AVALONFCHECENV_FILECODE (0xB335)
+#define PROC_FCH_AVALON_AVALONIMC_AVALONFCHECMID_FILECODE (0xB336)
+#define PROC_FCH_AVALON_AVALONIMC_AVALONFCHECLATE_FILECODE (0xB337)
+#define PROC_FCH_AVALON_AVALONIMC_AVALONIMCLIB_FILECODE (0xB338)
+#define PROC_FCH_AVALON_AVALONIMC_AVALONIMCSERVICE_FILECODE (0xB339)
+#define PROC_FCH_AVALON_AVALONIR_AVALONIRENV_FILECODE (0xB33A)
+#define PROC_FCH_AVALON_AVALONIR_AVALONIRMID_FILECODE (0xB33B)
+#define PROC_FCH_AVALON_AVALONIR_AVALONIRLATE_FILECODE (0xB33C)
+#define PROC_FCH_AVALON_AVALONPCIE_AVALONABRESET_FILECODE (0xB340)
+#define PROC_FCH_AVALON_AVALONPCIE_AVALONABENV_FILECODE (0xB341)
+#define PROC_FCH_AVALON_AVALONPCIE_AVALONABMID_FILECODE (0xB342)
+#define PROC_FCH_AVALON_AVALONPCIE_AVALONABLATE_FILECODE (0xB343)
+#define PROC_FCH_AVALON_AVALONPCIE_AVALONABENVSERVICE_FILECODE (0xB34C)
+#define PROC_FCH_AVALON_AVALONPCIE_AVALONABRESETSERVICE_FILECODE (0xB34D)
+#define PROC_FCH_AVALON_AVALONPCIE_AVALONABSERVICE_FILECODE (0xB34E)
+#define PROC_FCH_AVALON_AVALONSATA_AVALONSATARESET_FILECODE (0xB360)
+#define PROC_FCH_AVALON_AVALONSATA_AVALONSATAENV_FILECODE (0xB361)
+#define PROC_FCH_AVALON_AVALONSATA_AVALONSATAMID_FILECODE (0xB362)
+#define PROC_FCH_AVALON_AVALONSATA_AVALONSATALATE_FILECODE (0xB363)
+#define PROC_FCH_AVALON_AVALONSATA_AVALONSATARESETSERVICE_FILECODE (0xB364)
+#define PROC_FCH_AVALON_AVALONSATA_AVALONSATAENVSERVICE_FILECODE (0xB365)
+#define PROC_FCH_AVALON_AVALONSATA_AVALONSATASERVICE_FILECODE (0xB366)
+#define PROC_FCH_AVALON_AVALONSATA_AVALONSATALIB_FILECODE (0xB367)
+#define PROC_FCH_AVALON_AVALONSATA_AVALONSATAENVLIB_FILECODE (0xB368)
+#define PROC_FCH_AVALON_AVALONSATA_AVALONAHCILIB_FILECODE (0xB369)
+#define PROC_FCH_AVALON_AVALONSATA_AVALONAHCIENV_FILECODE (0xB36A)
+#define PROC_FCH_AVALON_AVALONSATA_AVALONAHCIMID_FILECODE (0xB36B)
+#define PROC_FCH_AVALON_AVALONSATA_AVALONAHCILATE_FILECODE (0xB36C)
+#define PROC_FCH_AVALON_AVALONSATA_AVALONRAIDLIB_FILECODE (0xB36D)
+#define PROC_FCH_AVALON_AVALONSATA_AVALONRAIDENV_FILECODE (0xB36E)
+#define PROC_FCH_AVALON_AVALONSATA_AVALONRAIDMID_FILECODE (0xB36F)
+#define PROC_FCH_AVALON_AVALONSATA_AVALONRAIDLATE_FILECODE (0xB370)
+#define PROC_FCH_AVALON_AVALONSATA_AVALONIDE2AHCILIB_FILECODE (0xB371)
+#define PROC_FCH_AVALON_AVALONSATA_AVALONIDE2AHCIENV_FILECODE (0xB372)
+#define PROC_FCH_AVALON_AVALONSATA_AVALONIDE2AHCIMID_FILECODE (0xB373)
+#define PROC_FCH_AVALON_AVALONSATA_AVALONIDE2AHCILATE_FILECODE (0xB374)
+#define PROC_FCH_AVALON_AVALONSATA_AVALONSATAIDELIB_FILECODE (0xB375)
+#define PROC_FCH_AVALON_AVALONSATA_AVALONSATAIDEENV_FILECODE (0xB376)
+#define PROC_FCH_AVALON_AVALONSATA_AVALONSATAIDEMID_FILECODE (0xB377)
+#define PROC_FCH_AVALON_AVALONSATA_AVALONSATAIDELATE_FILECODE (0xB378)
+#define PROC_FCH_AVALON_AVALONSD_AVALONSDENV_FILECODE (0xB381)
+#define PROC_FCH_AVALON_AVALONSD_AVALONSDMID_FILECODE (0xB382)
+#define PROC_FCH_AVALON_AVALONSD_AVALONSDLATE_FILECODE (0xB383)
+#define PROC_FCH_AVALON_AVALONSD_AVALONSDRESETSERVICE_FILECODE (0xB384)
+#define PROC_FCH_AVALON_AVALONSD_AVALONSDENVSERVICE_FILECODE (0xB385)
+#define PROC_FCH_AVALON_AVALONSD_AVALONSDSERVICE_FILECODE (0xB386)
+#define PROC_FCH_AVALON_AVALONSPI_AVALONSPIRESET_FILECODE (0xB390)
+#define PROC_FCH_AVALON_AVALONSPI_AVALONSPIENV_FILECODE (0xB391)
+#define PROC_FCH_AVALON_AVALONSPI_AVALONSPIMID_FILECODE (0xB392)
+#define PROC_FCH_AVALON_AVALONSPI_AVALONSPILATE_FILECODE (0xB393)
+#define PROC_FCH_AVALON_AVALONSPI_AVALONLPCRESET_FILECODE (0xB394)
+#define PROC_FCH_AVALON_AVALONSPI_AVALONLPCENV_FILECODE (0xB395)
+#define PROC_FCH_AVALON_AVALONSPI_AVALONLPCMID_FILECODE (0xB396)
+#define PROC_FCH_AVALON_AVALONSPI_AVALONLPCLATE_FILECODE (0xB397)
+#define PROC_FCH_AVALON_AVALONSPI_AVALONLPCRESETSERVICE_FILECODE (0xB398)
+#define PROC_FCH_AVALON_AVALONSPI_AVALONLPCENVSERVICE_FILECODE (0xB399)
+#define PROC_FCH_AVALON_AVALONUSB_AVALONUSBRESET_FILECODE (0xB3A0)
+#define PROC_FCH_AVALON_AVALONUSB_AVALONUSBENV_FILECODE (0xB3A1)
+#define PROC_FCH_AVALON_AVALONUSB_AVALONUSBMID_FILECODE (0xB3A2)
+#define PROC_FCH_AVALON_AVALONUSB_AVALONUSBLATE_FILECODE (0xB3A3)
+#define PROC_FCH_AVALON_AVALONUSB_AVALONEHCIRESET_FILECODE (0xB3A4)
+#define PROC_FCH_AVALON_AVALONUSB_AVALONEHCIENV_FILECODE (0xB3A5)
+#define PROC_FCH_AVALON_AVALONUSB_AVALONEHCIMID_FILECODE (0xB3A6)
+#define PROC_FCH_AVALON_AVALONUSB_AVALONEHCILATE_FILECODE (0xB3A7)
+#define PROC_FCH_AVALON_AVALONUSB_AVALONEHCIMIDSERVICE_FILECODE (0xB3A8)
+#define PROC_FCH_AVALON_AVALONUSB_AVALONEHCIENVSERVICE_FILECODE (0xB3A9)
+#define PROC_FCH_AVALON_AVALONUSB_AVALONEHCILATESERVICE_FILECODE (0xB3AA)
+#define PROC_FCH_AVALON_AVALONUSB_AVALONXHCIRESET_FILECODE (0xB3B2)
+#define PROC_FCH_AVALON_AVALONUSB_AVALONXHCIENV_FILECODE (0xB3B3)
+#define PROC_FCH_AVALON_AVALONUSB_AVALONXHCIMID_FILECODE (0xB3B4)
+#define PROC_FCH_AVALON_AVALONUSB_AVALONXHCILATE_FILECODE (0xB3B5)
+#define PROC_FCH_AVALON_AVALONUSB_AVALONXHCIRESETSERVICE_FILECODE (0xB3B6)
+#define PROC_FCH_AVALON_AVALONUSB_AVALONXHCIENVSERVICE_FILECODE (0xB3B7)
+#define PROC_FCH_AVALON_AVALONUSB_AVALONXHCIMIDSERVICE_FILECODE (0xB3B8)
+#define PROC_FCH_AVALON_AVALONUSB_AVALONXHCILATESERVICE_FILECODE (0xB3B9)
+#define PROC_FCH_AVALON_AVALONUSB_AVALONXHCIRECOVERY_FILECODE (0xB3BA)
+#define UEFI_FCH_AVALON_DXE_FCHACPICS_FCHACPICS_FILECODE (0xB308)
+#define UEFI_FCH_AVALON_DXE_FCHACPICS_FCHACPICSAML_FILECODE (0xB309)
+#define UEFI_FCH_AVALON_DXE_FCHACPICS_FCHACPICSCONTROL_FILECODE (0xB30A)
+#define UEFI_FCH_AVALON_DXE_FCHACPICS_FUNCTIONS_FCHD3COLD_FCHD3COLD_FILECODE (0xB30B)
+#define UEFI_FCH_AVALON_DXE_AMDFCHHWM_AMDFCHHWM_FILECODE (0xB3C1)
+#define UEFI_FCH_AVALON_DXE_AMDFCHWHEA_AMDFCHWHEA_FILECODE (0xB3C2)
+#define UEFI_FCH_AVALON_DXE_AMDFCHWHEA_AMDFCHWHEAEINJ_FILECODE (0xB3C3)
+#define UEFI_FCH_AVALON_DXE_AMDFCHWHEA_AMDFCHWHEAHEST_FILECODE (0xB3C4)
+#define UEFI_FCH_AVALON_DXE_CF9RESET_CF9RESET_FILECODE (0xB3C5)
+#define UEFI_FCH_AVALON_DXE_CF9RESET_IA32_IA32CF9RESET_FILECODE (0xB3C6)
+#define UEFI_FCH_AVALON_DXE_CF9RESET_X64_X64CF9RESET_FILECODE (0xB3C7)
+#define UEFI_FCH_AVALON_DXE_FCHDXE_FCHDXE_FILECODE (0xB3C8)
+#define UEFI_FCH_AVALON_DXE_FCHDXE_USBOC_FILECODE (0xB3C9)
+#define UEFI_FCH_AVALON_DXE_FCHDXEAUX_DXEBOOTTIMER_FILECODE (0xB3CA)
+#define UEFI_FCH_AVALON_DXE_FCHDXEAUX_DXEDISUSBPORT_FILECODE (0xB3CB)
+#define UEFI_FCH_AVALON_DXE_FCHDXEAUX_DXEESATAPORT_FILECODE (0xB3CC)
+#define UEFI_FCH_AVALON_DXE_FCHDXEAUX_DXEGPIO_FILECODE (0xB3CD)
+#define UEFI_FCH_AVALON_DXE_FCHDXEAUX_DXEGPIOREAD_FILECODE (0xB3CE)
+#define UEFI_FCH_AVALON_DXE_FCHDXEAUX_FCHDXEAUX_FILECODE (0xB3CF)
+#define UEFI_FCH_AVALON_DXE_FCHDXELIB_FCHDXELIB_FILECODE (0xB3D0)
+#define UEFI_FCH_AVALON_DXE_FCHDXELPCCLKRUN_FCHDXELPCCLKRUN_FILECODE (0xB3D1)
+#define UEFI_FCH_AVALON_DXE_FCHDXEMMIO_FCHDXEMMIO_FILECODE (0xB3D2)
+#define UEFI_FCH_AVALON_DXE_LEGACYINTERRUPT_LEGACYINTERRUPT_FILECODE (0xB3D3)
+#define UEFI_FCH_AVALON_DXE_SMBUS_SMBUSLIGHT_FILECODE (0xB3D4)
+#define UEFI_FCH_AVALON_DXE_SMMCONTROL_SMMCONTROL_FILECODE (0xB3D5)
+#define UEFI_FCH_AVALON_PEI_FCHPEI_FCHEHCIRECOVERY_FILECODE (0xB3D6)
+#define UEFI_FCH_AVALON_PEI_FCHPEI_FCHPEI_FILECODE (0xB3D8)
+#define UEFI_FCH_AVALON_PEI_FCHPEI_FCHRESET_FILECODE (0xB3D9)
+#define UEFI_FCH_AVALON_PEI_FCHPEI_FCHSATARECOVERY_FILECODE (0xB3DA)
+#define UEFI_FCH_AVALON_PEI_FCHPEI_FCHSTALL_FILECODE (0xB3DB)
+#define UEFI_FCH_AVALON_PEI_FCHPEI_FCHXHCIRECOVERY_FILECODE (0xB3DC)
+#define UEFI_FCH_AVALON_PEI_FCHPEIAUX_FCHPEIAUX_FILECODE (0xB3DD)
+#define UEFI_FCH_AVALON_PEI_FCHPEIAUX_PEIBOOTTIMER_FILECODE (0xB3DE)
+#define UEFI_FCH_AVALON_PEI_FCHPEIAUX_PEIDISUSBPORT_FILECODE (0xB3DF)
+#define UEFI_FCH_AVALON_PEI_FCHPEIAUX_PEIGPIO_FILECODE (0xB3E0)
+#define UEFI_FCH_AVALON_PEI_FCHPEIAUX_PEIGPIOREAD_FILECODE (0xB3E1)
+#define UEFI_FCH_AVALON_PEI_FCHPEIAUX_PEIOSCOUTCLOCK_FILECODE (0xB3E2)
+#define UEFI_FCH_AVALON_PEI_FCHPEILIB_FCHPEILIB_FILECODE (0xB3E3)
+#define UEFI_FCH_AVALON_PEI_FCHPEILIB_LIBAMDPEI_FILECODE (0xB3E4)
+#define UEFI_FCH_AVALON_PEI_SMBUS_SMBUS_FILECODE (0xB3E5)
+#define UEFI_FCH_AVALON_SMM_FCHSMM_FCHSMM_FILECODE (0xB3E6)
+#define UEFI_FCH_AVALON_SMM_FCHSMM_GPESMI_FILECODE (0xB3E7)
+#define UEFI_FCH_AVALON_SMM_FCHSMM_IOTRAPSMI_FILECODE (0xB3E8)
+#define UEFI_FCH_AVALON_SMM_FCHSMM_MISCSMI_FILECODE (0xB3E9)
+#define UEFI_FCH_AVALON_SMM_FCHSMM_PERIODICTIMERSMI_FILECODE (0xB3EA)
+#define UEFI_FCH_AVALON_SMM_FCHSMM_POWERBUTTONSMI_FILECODE (0xB3EB)
+#define UEFI_FCH_AVALON_SMM_FCHSMM_SWSMI_FILECODE (0xB3EC)
+#define UEFI_FCH_AVALON_SMM_FCHSMM_SXSMI_FILECODE (0xB3ED)
+#define UEFI_FCH_AVALON_SMM_FCHSMMCOMPLEMENT_IMCCONTROL_IMCCONTROL_FILECODE (0xB3F0)
+#define UEFI_FCH_AVALON_SMM_FCHSMMCOMPLEMENT_IMCCONTROL_IMCCONTROLLIB_FILECODE (0xB3F1)
+#define UEFI_FCH_AVALON_SMM_FCHSMMLIB_FCHDXECOMMON_FILECODE (0xB3F5)
+#define UEFI_FCH_AVALON_SMM_FCHSMMLIB_FCHSMMLIB_FILECODE (0xB3F6)
+#define UEFI_FCH_AVALON_SMM_FCHSMMDISPATCHER_FCHSMMDISPATCHER_FILECODE (0xB3F7)
+#define UEFI_FCH_AVALON_SMM_FCHSMMDISPATCHER_FCHSMMGPEDISPATCHER_FCHSMMGPEDISPATCHER_FILECODE (0xB3F8)
+#define UEFI_FCH_AVALON_SMM_FCHSMMDISPATCHER_FCHSMMIOTRAPDISPATCHER_FCHSMMIOTRAPDISPATCHER_FILECODE (0xB3F9)
+#define UEFI_FCH_AVALON_SMM_FCHSMMDISPATCHER_FCHSMMMISCDISPATCHER_FCHSMMMISCDISPATCHER_FILECODE (0xB3FA)
+#define UEFI_FCH_AVALON_SMM_FCHSMMDISPATCHER_FCHSMMPERIODICALDISPATCHER_FCHSMMPERIODICALDISPATCHER_FILECODE (0xB3FB)
+#define UEFI_FCH_AVALON_SMM_FCHSMMDISPATCHER_FCHSMMPWRBTNDISPATCHER_FCHSMMPWRBTNDISPATCHER_FILECODE (0xB3FC)
+#define UEFI_FCH_AVALON_SMM_FCHSMMDISPATCHER_FCHSMMSWDISPATCHER_FCHSMMSWDISPATCHER_FILECODE (0xB3FE)
+#define UEFI_FCH_AVALON_SMM_FCHSMMDISPATCHER_FCHSMMSXDISPATCHER_FCHSMMSXDISPATCHER_FILECODE (0xB3FF)
+#define UEFI_FCH_AVALON_SMM_FCHSMMDISPATCHER_FCHSMMUSBDISPATCHER_FCHSMMUSBDISPATCHER_FILECODE (0xB3F2)
+
+#define PROC_FCH_KERN_KERNAZALIA_KERNAZALIARESET_FILECODE (0xB400)
+#define PROC_FCH_KERN_KERNAZALIA_KERNAZALIAENV_FILECODE (0xB401)
+#define PROC_FCH_KERN_KERNAZALIA_KERNAZALIAMID_FILECODE (0xB402)
+#define PROC_FCH_KERN_KERNAZALIA_KERNAZALIALATE_FILECODE (0xB403)
+#define PROC_FCH_KERN_KERNHWACPI_KERNHWACPIRESET_FILECODE (0xB410)
+#define PROC_FCH_KERN_KERNHWACPI_KERNHWACPIENV_FILECODE (0xB411)
+#define PROC_FCH_KERN_KERNHWACPI_KERNHWACPIMID_FILECODE (0xB412)
+#define PROC_FCH_KERN_KERNHWACPI_KERNHWACPILATE_FILECODE (0xB413)
+#define PROC_FCH_KERN_KERNHWACPI_KERNSSSERVICE_FILECODE (0xB414)
+#define PROC_FCH_KERN_KERNHWACPI_KERNHWACPIENVSERVICE_FILECODE (0xB415)
+#define PROC_FCH_KERN_KERNHWACPI_KERNHWACPIMIDSERVICE_FILECODE (0xB416)
+#define PROC_FCH_KERN_KERNHWACPI_KERNHWACPILATESERVICE_FILECODE (0xB417)
+#define PROC_FCH_KERN_KERNHWM_KERNHWMRESET_FILECODE (0xB420)
+#define PROC_FCH_KERN_KERNHWM_KERNHWMENV_FILECODE (0xB421)
+#define PROC_FCH_KERN_KERNHWM_KERNHWMMID_FILECODE (0xB422)
+#define PROC_FCH_KERN_KERNHWM_KERNHWMLATE_FILECODE (0xB423)
+#define PROC_FCH_KERN_KERNHWM_KERNHWMENVSERVICE_FILECODE (0xB424)
+#define PROC_FCH_KERN_KERNHWM_KERNHWMMIDSERVICE_FILECODE (0xB425)
+#define PROC_FCH_KERN_KERNHWM_KERNHWMLATESERVICE_FILECODE (0xB426)
+#define PROC_FCH_KERN_KERNINTERFACE_KERNFCHINITRESET_FILECODE (0xB427)
+#define PROC_FCH_KERN_KERNINTERFACE_KERNFCHINITENV_FILECODE (0xB428)
+#define PROC_FCH_KERN_KERNINTERFACE_KERNFCHINITMID_FILECODE (0xB429)
+#define PROC_FCH_KERN_KERNINTERFACE_KERNFCHINITLATE_FILECODE (0xB42A)
+#define PROC_FCH_KERN_KERNINTERFACE_KERNFCHINITS3_FILECODE (0xB42B)
+#define PROC_FCH_KERN_KERNINTERFACE_KERNINITRESETDEF_FILECODE (0xB42C)
+#define PROC_FCH_KERN_KERNINTERFACE_KERNINITENVDEF_FILECODE (0xB42D)
+#define PROC_FCH_KERN_KERNINTERFACE_KERNFCHTASKLAUNCHER_FILECODE (0xB42E)
+#define PROC_FCH_KERN_KERNIMC_KERNIMCRESET_FILECODE (0xB430)
+#define PROC_FCH_KERN_KERNIMC_KERNIMCENV_FILECODE (0xB431)
+#define PROC_FCH_KERN_KERNIMC_KERNIMCMID_FILECODE (0xB432)
+#define PROC_FCH_KERN_KERNIMC_KERNIMCLATE_FILECODE (0xB433)
+#define PROC_FCH_KERN_KERNIMC_KERNFCHECRESET_FILECODE (0xB434)
+#define PROC_FCH_KERN_KERNIMC_KERNFCHECENV_FILECODE (0xB435)
+#define PROC_FCH_KERN_KERNIMC_KERNFCHECMID_FILECODE (0xB436)
+#define PROC_FCH_KERN_KERNIMC_KERNFCHECLATE_FILECODE (0xB437)
+#define PROC_FCH_KERN_KERNIMC_KERNIMCLIB_FILECODE (0xB438)
+#define PROC_FCH_KERN_KERNIMC_KERNIMCSERVICE_FILECODE (0xB439)
+#define PROC_FCH_KERN_KERNPCIE_KERNABRESET_FILECODE (0xB440)
+#define PROC_FCH_KERN_KERNPCIE_KERNABENV_FILECODE (0xB441)
+#define PROC_FCH_KERN_KERNPCIE_KERNABMID_FILECODE (0xB442)
+#define PROC_FCH_KERN_KERNPCIE_KERNABLATE_FILECODE (0xB443)
+#define PROC_FCH_KERN_KERNPCIE_KERNABENVSERVICE_FILECODE (0xB44C)
+#define PROC_FCH_KERN_KERNPCIE_KERNABRESETSERVICE_FILECODE (0xB44D)
+#define PROC_FCH_KERN_KERNPCIE_KERNABSERVICE_FILECODE (0xB44E)
+#define PROC_FCH_KERN_KERNSATA_KERNSATARESET_FILECODE (0xB460)
+#define PROC_FCH_KERN_KERNSATA_KERNSATAENV_FILECODE (0xB461)
+#define PROC_FCH_KERN_KERNSATA_KERNSATAMID_FILECODE (0xB462)
+#define PROC_FCH_KERN_KERNSATA_KERNSATALATE_FILECODE (0xB463)
+#define PROC_FCH_KERN_KERNSATA_KERNSATARESETSERVICE_FILECODE (0xB464)
+#define PROC_FCH_KERN_KERNSATA_KERNSATAENVSERVICE_FILECODE (0xB465)
+#define PROC_FCH_KERN_KERNSATA_KERNSATASERVICE_FILECODE (0xB466)
+#define PROC_FCH_KERN_KERNSATA_KERNSATALIB_FILECODE (0xB467)
+#define PROC_FCH_KERN_KERNSATA_KERNSATAENVLIB_FILECODE (0xB468)
+#define PROC_FCH_KERN_KERNSATA_KERNAHCILIB_FILECODE (0xB469)
+#define PROC_FCH_KERN_KERNSATA_KERNAHCIENV_FILECODE (0xB46A)
+#define PROC_FCH_KERN_KERNSATA_KERNAHCIMID_FILECODE (0xB46B)
+#define PROC_FCH_KERN_KERNSATA_KERNAHCILATE_FILECODE (0xB46C)
+#define PROC_FCH_KERN_KERNSATA_KERNRAIDLIB_FILECODE (0xB46D)
+#define PROC_FCH_KERN_KERNSATA_KERNRAIDENV_FILECODE (0xB46E)
+#define PROC_FCH_KERN_KERNSATA_KERNRAIDMID_FILECODE (0xB46F)
+#define PROC_FCH_KERN_KERNSATA_KERNRAIDLATE_FILECODE (0xB470)
+#define PROC_FCH_KERN_KERNSATA_KERNIDE2AHCILIB_FILECODE (0xB471)
+#define PROC_FCH_KERN_KERNSATA_KERNIDE2AHCIENV_FILECODE (0xB472)
+#define PROC_FCH_KERN_KERNSATA_KERNIDE2AHCIMID_FILECODE (0xB473)
+#define PROC_FCH_KERN_KERNSATA_KERNIDE2AHCILATE_FILECODE (0xB474)
+#define PROC_FCH_KERN_KERNSATA_KERNSATAIDELIB_FILECODE (0xB475)
+#define PROC_FCH_KERN_KERNSATA_KERNSATAIDEENV_FILECODE (0xB476)
+#define PROC_FCH_KERN_KERNSATA_KERNSATAIDEMID_FILECODE (0xB477)
+#define PROC_FCH_KERN_KERNSATA_KERNSATAIDELATE_FILECODE (0xB478)
+#define PROC_FCH_KERN_KERNSD_KERNSDENV_FILECODE (0xB481)
+#define PROC_FCH_KERN_KERNSD_KERNSDMID_FILECODE (0xB482)
+#define PROC_FCH_KERN_KERNSD_KERNSDLATE_FILECODE (0xB483)
+#define PROC_FCH_KERN_KERNSD_KERNSDRESETSERVICE_FILECODE (0xB484)
+#define PROC_FCH_KERN_KERNSD_KERNSDENVSERVICE_FILECODE (0xB485)
+#define PROC_FCH_KERN_KERNSD_KERNSDSERVICE_FILECODE (0xB486)
+#define PROC_FCH_KERN_KERNSPI_KERNSPIRESET_FILECODE (0xB490)
+#define PROC_FCH_KERN_KERNSPI_KERNSPIENV_FILECODE (0xB491)
+#define PROC_FCH_KERN_KERNSPI_KERNSPIMID_FILECODE (0xB492)
+#define PROC_FCH_KERN_KERNSPI_KERNSPILATE_FILECODE (0xB493)
+#define PROC_FCH_KERN_KERNSPI_KERNLPCRESET_FILECODE (0xB494)
+#define PROC_FCH_KERN_KERNSPI_KERNLPCENV_FILECODE (0xB495)
+#define PROC_FCH_KERN_KERNSPI_KERNLPCMID_FILECODE (0xB496)
+#define PROC_FCH_KERN_KERNSPI_KERNLPCLATE_FILECODE (0xB497)
+#define PROC_FCH_KERN_KERNSPI_KERNLPCRESETSERVICE_FILECODE (0xB498)
+#define PROC_FCH_KERN_KERNSPI_KERNLPCENVSERVICE_FILECODE (0xB499)
+#define PROC_FCH_KERN_KERNUSB_KERNUSBRESET_FILECODE (0xB4A0)
+#define PROC_FCH_KERN_KERNUSB_KERNUSBENV_FILECODE (0xB4A1)
+#define PROC_FCH_KERN_KERNUSB_KERNUSBMID_FILECODE (0xB4A2)
+#define PROC_FCH_KERN_KERNUSB_KERNUSBLATE_FILECODE (0xB4A3)
+#define PROC_FCH_KERN_KERNUSB_KERNEHCIRESET_FILECODE (0xB4A4)
+#define PROC_FCH_KERN_KERNUSB_KERNEHCIENV_FILECODE (0xB4A5)
+#define PROC_FCH_KERN_KERNUSB_KERNEHCIMID_FILECODE (0xB4A6)
+#define PROC_FCH_KERN_KERNUSB_KERNEHCILATE_FILECODE (0xB4A7)
+#define PROC_FCH_KERN_KERNUSB_KERNEHCIMIDSERVICE_FILECODE (0xB4A8)
+#define PROC_FCH_KERN_KERNUSB_KERNEHCIENVSERVICE_FILECODE (0xB4A9)
+#define PROC_FCH_KERN_KERNUSB_KERNEHCILATESERVICE_FILECODE (0xB4AA)
+#define PROC_FCH_KERN_KERNUSB_KERNXHCIRESET_FILECODE (0xB4B2)
+#define PROC_FCH_KERN_KERNUSB_KERNXHCIENV_FILECODE (0xB4B3)
+#define PROC_FCH_KERN_KERNUSB_KERNXHCIMID_FILECODE (0xB4B4)
+#define PROC_FCH_KERN_KERNUSB_KERNXHCILATE_FILECODE (0xB4B5)
+#define PROC_FCH_KERN_KERNUSB_KERNXHCIRESETSERVICE_FILECODE (0xB4B6)
+#define PROC_FCH_KERN_KERNUSB_KERNXHCIENVSERVICE_FILECODE (0xB4B7)
+#define PROC_FCH_KERN_KERNUSB_KERNXHCIMIDSERVICE_FILECODE (0xB4B8)
+#define PROC_FCH_KERN_KERNUSB_KERNXHCILATESERVICE_FILECODE (0xB4B9)
+#define PROC_FCH_KERN_KERNUSB_KERNXHCIRECOVERY_FILECODE (0xB4BA)
+#define UEFI_FCH_KERN_DXE_FCHACPICS_FCHACPICS_FILECODE (0xB408)
+#define UEFI_FCH_KERN_DXE_FCHACPICS_FCHACPICSAML_FILECODE (0xB409)
+#define UEFI_FCH_KERN_DXE_FCHACPICS_FCHACPICSCONTROL_FILECODE (0xB40A)
+#define UEFI_FCH_KERN_DXE_FCHACPICS_FUNCTIONS_FCHD3COLD_FCHD3COLD_FILECODE (0xB40B)
+#define UEFI_FCH_KERN_DXE_AMDFCHHWM_AMDFCHHWM_FILECODE (0xB4C1)
+#define UEFI_FCH_KERN_DXE_AMDFCHWHEA_AMDFCHWHEA_FILECODE (0xB4C2)
+#define UEFI_FCH_KERN_DXE_AMDFCHWHEA_AMDFCHWHEAEINJ_FILECODE (0xB4C3)
+#define UEFI_FCH_KERN_DXE_AMDFCHWHEA_AMDFCHWHEAHEST_FILECODE (0xB4C4)
+#define UEFI_FCH_KERN_DXE_CF9RESET_CF9RESET_FILECODE (0xB4C5)
+#define UEFI_FCH_KERN_DXE_CF9RESET_IA32_IA32CF9RESET_FILECODE (0xB4C6)
+#define UEFI_FCH_KERN_DXE_CF9RESET_X64_X64CF9RESET_FILECODE (0xB4C7)
+#define UEFI_FCH_KERN_DXE_FCHDXE_FCHDXE_FILECODE (0xB4C8)
+#define UEFI_FCH_KERN_DXE_FCHDXE_USBOC_FILECODE (0xB4C9)
+#define UEFI_FCH_KERN_DXE_FCHDXEAUX_DXEBOOTTIMER_FILECODE (0xB4CA)
+#define UEFI_FCH_KERN_DXE_FCHDXEAUX_DXEDISUSBPORT_FILECODE (0xB4CB)
+#define UEFI_FCH_KERN_DXE_FCHDXEAUX_DXEESATAPORT_FILECODE (0xB4CC)
+#define UEFI_FCH_KERN_DXE_FCHDXEAUX_DXEGPIO_FILECODE (0xB4CD)
+#define UEFI_FCH_KERN_DXE_FCHDXEAUX_DXEGPIOREAD_FILECODE (0xB4CE)
+#define UEFI_FCH_KERN_DXE_FCHDXEAUX_FCHDXEAUX_FILECODE (0xB4CF)
+#define UEFI_FCH_KERN_DXE_FCHDXELIB_FCHDXELIB_FILECODE (0xB4D0)
+#define UEFI_FCH_KERN_DXE_FCHDXELPCCLKRUN_FCHDXELPCCLKRUN_FILECODE (0xB4D1)
+#define UEFI_FCH_KERN_DXE_FCHDXEMMIO_FCHDXEMMIO_FILECODE (0xB4D2)
+#define UEFI_FCH_KERN_DXE_LEGACYINTERRUPT_LEGACYINTERRUPT_FILECODE (0xB4D3)
+#define UEFI_FCH_KERN_DXE_SMBUS_SMBUSLIGHT_FILECODE (0xB4D4)
+#define UEFI_FCH_KERN_DXE_SMMCONTROL_SMMCONTROL_FILECODE (0xB4D5)
+#define UEFI_FCH_KERN_PEI_FCHPEI_FCHEHCIRECOVERY_FILECODE (0xB4D6)
+#define UEFI_FCH_KERN_PEI_FCHPEI_FCHPEI_FILECODE (0xB4D8)
+#define UEFI_FCH_KERN_PEI_FCHPEI_FCHRESET_FILECODE (0xB4D9)
+#define UEFI_FCH_KERN_PEI_FCHPEI_FCHSATARECOVERY_FILECODE (0xB4DA)
+#define UEFI_FCH_KERN_PEI_FCHPEI_FCHSTALL_FILECODE (0xB4DB)
+#define UEFI_FCH_KERN_PEI_FCHPEI_FCHXHCIRECOVERY_FILECODE (0xB4DC)
+#define UEFI_FCH_KERN_PEI_FCHPEIAUX_FCHPEIAUX_FILECODE (0xB4DD)
+#define UEFI_FCH_KERN_PEI_FCHPEIAUX_PEIBOOTTIMER_FILECODE (0xB4DE)
+#define UEFI_FCH_KERN_PEI_FCHPEIAUX_PEIDISUSBPORT_FILECODE (0xB4DF)
+#define UEFI_FCH_KERN_PEI_FCHPEIAUX_PEIGPIO_FILECODE (0xB4E0)
+#define UEFI_FCH_KERN_PEI_FCHPEIAUX_PEIGPIOREAD_FILECODE (0xB4E1)
+#define UEFI_FCH_KERN_PEI_FCHPEIAUX_PEIOSCOUTCLOCK_FILECODE (0xB4E2)
+#define UEFI_FCH_KERN_PEI_FCHPEILIB_FCHPEILIB_FILECODE (0xB4E3)
+#define UEFI_FCH_KERN_PEI_FCHPEILIB_LIBAMDPEI_FILECODE (0xB4E4)
+#define UEFI_FCH_KERN_PEI_SMBUS_SMBUS_FILECODE (0xB4E5)
+#define UEFI_FCH_KERN_SMM_FCHSMM_FCHSMM_FILECODE (0xB4E6)
+#define UEFI_FCH_KERN_SMM_FCHSMM_GPESMI_FILECODE (0xB4E7)
+#define UEFI_FCH_KERN_SMM_FCHSMM_IOTRAPSMI_FILECODE (0xB4E8)
+#define UEFI_FCH_KERN_SMM_FCHSMM_MISCSMI_FILECODE (0xB4E9)
+#define UEFI_FCH_KERN_SMM_FCHSMM_PERIODICTIMERSMI_FILECODE (0xB4EA)
+#define UEFI_FCH_KERN_SMM_FCHSMM_POWERBUTTONSMI_FILECODE (0xB4EB)
+#define UEFI_FCH_KERN_SMM_FCHSMM_SWSMI_FILECODE (0xB4EC)
+#define UEFI_FCH_KERN_SMM_FCHSMM_SXSMI_FILECODE (0xB4ED)
+#define UEFI_FCH_KERN_SMM_FCHSMMCOMPLEMENT_IMCCONTROL_IMCCONTROL_FILECODE (0xB4F0)
+#define UEFI_FCH_KERN_SMM_FCHSMMCOMPLEMENT_IMCCONTROL_IMCCONTROLLIB_FILECODE (0xB4F1)
+#define UEFI_FCH_KERN_SMM_FCHSMMLIB_FCHDXECOMMON_FILECODE (0xB4F5)
+#define UEFI_FCH_KERN_SMM_FCHSMMLIB_FCHSMMLIB_FILECODE (0xB4F6)
+#define UEFI_FCH_KERN_SMM_FCHSMMDISPATCHER_FCHSMMDISPATCHER_FILECODE (0xB4F7)
+#define UEFI_FCH_KERN_SMM_FCHSMMDISPATCHER_FCHSMMGPEDISPATCHER_FCHSMMGPEDISPATCHER_FILECODE (0xB4F8)
+#define UEFI_FCH_KERN_SMM_FCHSMMDISPATCHER_FCHSMMIOTRAPDISPATCHER_FCHSMMIOTRAPDISPATCHER_FILECODE (0xB4F9)
+#define UEFI_FCH_KERN_SMM_FCHSMMDISPATCHER_FCHSMMMISCDISPATCHER_FCHSMMMISCDISPATCHER_FILECODE (0xB4FA)
+#define UEFI_FCH_KERN_SMM_FCHSMMDISPATCHER_FCHSMMPERIODICALDISPATCHER_FCHSMMPERIODICALDISPATCHER_FILECODE (0xB4FB)
+#define UEFI_FCH_KERN_SMM_FCHSMMDISPATCHER_FCHSMMPWRBTNDISPATCHER_FCHSMMPWRBTNDISPATCHER_FILECODE (0xB4FC)
+#define UEFI_FCH_KERN_SMM_FCHSMMDISPATCHER_FCHSMMSWDISPATCHER_FCHSMMSWDISPATCHER_FILECODE (0xB4FE)
+#define UEFI_FCH_KERN_SMM_FCHSMMDISPATCHER_FCHSMMSXDISPATCHER_FCHSMMSXDISPATCHER_FILECODE (0xB4FF)
+#define UEFI_FCH_KERN_SMM_FCHSMMDISPATCHER_FCHSMMUSBDISPATCHER_FCHSMMUSBDISPATCHER_FILECODE (0xB4F2)
+
+#define LIB_AMDLIB_FILECODE (0xC001)
+
+#define LEGACY_PROC_AGESACALLOUTS_FILECODE (0xC010)
+#define LEGACY_PROC_HOBTRANSFER_FILECODE (0xC011)
+#define LEGACY_PROC_DISPATCHER_FILECODE (0xC012)
+
+#define UEFI_DXE_AMDAGESADXEDRIVER_AMDAGESADXEDRIVER_FILECODE (0xC120)
+
+#define UEFI_PEI_AMDINITPOSTPEIM_AMDINITPOSTPEIM_FILECODE (0xC140)
+#define UEFI_PEI_AMDPROCESSORINITPEIM_AMDPROCESSORINITPEIM_FILECODE (0xC141)
+#define UEFI_PEI_AMDRESETMANAGER_AMDRESETMANAGER_FILECODE (0xC142)
+#define UEFI_PROC_COMMON_HOBTRANSFERUEFI_FILECODE (0xC160)
+#define UEFI_PROC_DXE_HOBTRANSFERUEFIDXE_FILECODE (0xC161)
+#define UEFI_PROC_PEI_HOBTRANSFERUEFIPEI_FILECODE (0xC162)
+
+#define PROC_COMMON_AMDINITEARLY_FILECODE (0xC020)
+#define PROC_COMMON_AMDINITENV_FILECODE (0xC021)
+#define PROC_COMMON_AMDINITLATE_FILECODE (0xC022)
+#define PROC_COMMON_AMDINITMID_FILECODE (0xC023)
+#define PROC_COMMON_AMDINITPOST_FILECODE (0xC024)
+#define PROC_COMMON_AMDINITRECOVERY_FILECODE (0xC025)
+#define PROC_COMMON_AMDINITRESET_FILECODE (0xC026)
+#define PROC_COMMON_AMDINITRESUME_FILECODE (0xC027)
+#define PROC_COMMON_AMDS3LATERESTORE_FILECODE (0xC028)
+#define PROC_COMMON_AMDS3SAVE_FILECODE (0xC029)
+#define PROC_COMMON_AMDLATERUNAPTASK_FILECODE (0xC02A)
+
+#define PROC_COMMON_COMMONRETURNS_FILECODE (0xC0C0)
+#define PROC_COMMON_CREATESTRUCT_FILECODE (0xC0D0)
+#define PROC_COMMON_COMMONINITS_FILECODE (0xC0F0)
+#define PROC_COMMON_S3RESTORESTATE_FILECODE (0xC0F8)
+#define PROC_COMMON_S3SAVESTATE_FILECODE (0xC0F9)
+
+#define PROC_CPU_CPUAPICUTILITIES_FILECODE (0xC401)
+#define PROC_CPU_TABLE_FILECODE (0xC403)
+#define PROC_CPU_CPUEARLYINIT_FILECODE (0xC405)
+#define PROC_CPU_CPUEVENTLOG_FILECODE (0xC406)
+#define PROC_CPU_CPUFAMILYTRANSLATION_FILECODE (0xC407)
+#define PROC_CPU_CPUGENERALSERVICES_FILECODE (0xC408)
+#define PROC_CPU_CPULATEINIT_FILECODE (0xC40A)
+#define PROC_CPU_CPUMICROCODEPATCH_FILECODE (0xC40B)
+#define PROC_CPU_CPUWARMRESET_FILECODE (0xC40C)
+#define PROC_CPU_HEAPMANAGER_FILECODE (0xC40D)
+#define PROC_CPU_CPUBIST_FILECODE (0xC40E)
+#define PROC_CPU_MMIOMAPMANAGER_FILECODE (0xC40F)
+
+#define PROC_CPU_CPUPOSTINIT_FILECODE (0xC420)
+#define PROC_CPU_CPUPOWERMGMT_FILECODE (0xC430)
+#define PROC_CPU_CPUPOWERMGMTSINGLESOCKET_FILECODE (0xC432)
+#define PROC_CPU_S3_FILECODE (0xC460)
+
+// Family 16h
+#define PROC_CPU_FAMILY_0X16_CPUF16BRANDID_FILECODE (0xCC00)
+#define PROC_CPU_FAMILY_0X16_CPUF16UTILITIES_FILECODE (0xCC01)
+#define PROC_CPU_FAMILY_0X16_CPUF16WHEAINITDATATABLES_FILECODE (0xCC02)
+#define PROC_CPU_FAMILY_0X16_CPUF16CACHEDEFAULTS_FILECODE (0xCC03)
+#define PROC_CPU_FAMILY_0X16_CPUF16DMI_FILECODE (0xCC04)
+#define PROC_CPU_FAMILY_0X16_CPUF16PCIUNKNOWNTABLES_FILECODE (0xCC05)
+#define PROC_CPU_FAMILY_0X16_CPUF16MSRUNKNOWNTABLES_FILECODE (0xCC06)
+#define PROC_CPU_FAMILY_0X16_CPUF16MMIOMAP_FILECODE (0xCC07)
+#define PROC_CPU_FAMILY_0X16_CPUF16APM_FILECODE (0xCC09)
+#define PROC_CPU_FAMILY_0X16_CPUF16CRAT_FILECODE (0xCC0A)
+
+#define PROC_CPU_FAMILY_0X16_ML_F16MLLOGICALIDTABLES_FILECODE (0xCC40)
+#define PROC_CPU_FAMILY_0X16_ML_F16MLINITEARLYTABLE_FILECODE (0xCC41)
+#define PROC_CPU_FAMILY_0X16_ML_F16MLEQUIVALENCETABLE_FILECODE (0xCC42)
+#define PROC_CPU_FAMILY_0X16_ML_F16MLMICROCODEPATCHTABLES_FILECODE (0xCC43)
+#define PROC_CPU_FAMILY_0X16_ML_F16MLPCITABLES_FILECODE (0xCC44)
+#define PROC_CPU_FAMILY_0X16_ML_F16MLMSRTABLES_FILECODE (0xCC45)
+#define PROC_CPU_FAMILY_0X16_ML_F16MLSHAREDMSRTABLE_FILECODE (0xCC46)
+#define PROC_CPU_FAMILY_0X16_ML_F16MLUTILITIES_FILECODE (0xCC47)
+#define PROC_CPU_FAMILY_0X16_ML_F16MLC6STATE_FILECODE (0xCC48)
+#define PROC_CPU_FAMILY_0X16_ML_F16MLCOREAFTERRESET_FILECODE (0xCC49)
+#define PROC_CPU_FAMILY_0X16_ML_F16MLCPB_FILECODE (0xCC4A)
+#define PROC_CPU_FAMILY_0X16_ML_F16MLDMI_FILECODE (0xCC4B)
+#define PROC_CPU_FAMILY_0X16_ML_F16MLIOCSTATE_FILECODE (0xCC4C)
+#define PROC_CPU_FAMILY_0X16_ML_F16MLNBAFTERRESET_FILECODE (0xCC4D)
+#define PROC_CPU_FAMILY_0X16_ML_F16MLPOWERCHECK_FILECODE (0xCC4E)
+#define PROC_CPU_FAMILY_0X16_ML_F16MLPSTATE_FILECODE (0xCC4F)
+#define PROC_CPU_FAMILY_0X16_ML_F16MLPSI_FILECODE (0xCC50)
+#define PROC_CPU_FAMILY_0X16_ML_F16MLHTC_FILECODE (0xCC51)
+#define PROC_CPU_FAMILY_0X16_ML_F16MLPOWERMGMTSYSTEMTABLES_FILECODE (0xCC52)
+#define PROC_CPU_FAMILY_0X16_ML_F16MLSCS_FILECODE (0xCC53)
+#define PROC_CPU_FAMILY_0X16_ML_F16MLCACHEFLUSHONHALT_FILECODE (0xCC54)
+#define PROC_CPU_FAMILY_0X16_ML_F16MLCONNECTEDSTANDBY_FILECODE (0xCC55)
+#define UEFI_PSP_LIBRARY_CSRESUMESMMLIB_ML_CSRESUMESMMLIBML_FILECODE (0xCC56)
+
+#define PROC_CPU_FEATURE_CPUCACHEFLUSHONHALT_FILECODE (0xDC01)
+#define PROC_CPU_FEATURE_CPUCACHEINIT_FILECODE (0xDC02)
+#define PROC_CPU_FEATURE_CPUDMI_FILECODE (0xDC10)
+#define PROC_CPU_FEATURE_CPUPSTATEGATHER_FILECODE (0xDC41)
+#define PROC_CPU_FEATURE_CPUPSTATELEVELING_FILECODE (0xDC42)
+#define PROC_CPU_FEATURE_CPUPSTATETABLES_FILECODE (0xDC43)
+#define PROC_CPU_FEATURE_CPUSLIT_FILECODE (0xDC50)
+#define PROC_CPU_FEATURE_CPUSRAT_FILECODE (0xDC60)
+#define PROC_CPU_FEATURE_CPUWHEA_FILECODE (0xDC70)
+#define PROC_CPU_FEATURE_CPUC6STATE_FILECODE (0xDC82)
+#define PROC_CPU_FEATURE_CPUCPB_FILECODE (0xDC83)
+#define PROC_CPU_FEATURE_CPUIOCSTATE_FILECODE (0xDC85)
+#define PROC_CPU_FEATURE_CPUAPM_FILECODE (0xDC86)
+#define PROC_CPU_FEATURE_CPUFEATURES_FILECODE (0xDC90)
+#define PROC_CPU_FEATURE_CPUCORELEVELING_FILECODE (0xDCB0)
+#define PROC_CPU_FEATURE_CPUPSI_FILECODE (0xDCC0)
+#define PROC_CPU_FEATURE_CPUHTC_FILECODE (0xDCC1)
+#define PROC_CPU_FEATURE_CPUCRAT_FILECODE (0xDCD0)
+#define PROC_CPU_FEATURE_CPUCDIT_FILECODE (0xDCD1)
+#define PROC_CPU_FEATURE_CPUSCS_FILECODE (0xDCD4)
+#define PROC_CPU_FEATURE_CPUCONNECTEDSTANDBY_FILECODE (0xDCD5)
+
+#define PROC_RECOVERY_CPU_CPURECOVERY_FILECODE (0xDE01)
+
+#define PROC_TOPOLOGY_TOPOMAIN_FILECODE (0xE001)
+#define PROC_TOPOLOGY_TOPONB_FILECODE (0xE002)
+#define PROC_TOPOLOGY_FAM16_TOPONBFAM16_FILECODE (0xE097)
+#define PROC_TOPOLOGY_FAM16_TOPONBUTILITIESFAM16_FILECODE (0xE098)
+
+#define PROC_RECOVERY_TOPOLOGY_TOPOINITRECOVERY_FILECODE (0xE0FF)
+
+#define PROC_IDS_CONTROL_IDSCTRL_FILECODE (0xE801)
+#define PROC_IDS_LIBRARY_IDSLIB_FILECODE (0xE802)
+#define PROC_IDS_DEBUG_IDSDEBUG_FILECODE (0xE803)
+#define PROC_IDS_PERF_IDSPERF_FILECODE (0xE804)
+#define PROC_IDS_LIBRARY_IDSREGACC_FILECODE (0xE810)
+#define PROC_IDS_DEBUG_IDSDPHDTOUT_FILECODE (0xE811)
+#define PROC_IDS_DEBUG_IDSDEBUGPRINT_FILECODE (0xE812)
+#define PROC_IDS_DEBUG_IDSDPSERIAL_FILECODE (0xE813)
+#define PROC_IDS_DEBUG_IDSDPREDIRECTIO_FILECODE (0xE814)
+#define PROC_IDS_DEBUG_IDSDPRAM_FILECODE (0xE815)
+
+#define PROC_IDS_DEBUG_IDSIDTTABLE_FILECODE (0xE81E)
+#define PROC_IDS_CONTROL_IDSNVTOCMOS_FILECODE (0xE81F)
+#define PROC_IDS_FAMILY_0X16_ML_IDSF16MLALLSERVICE_FILECODE (0xE823)
+
+///0xE820 ~ 0xE840 is reserved for ids extend module
+
+#define PROC_MEM_ARDK_MA_FILECODE (0xF001)
+
+#define PROC_MEM_FEAT_CSINTLV_MFCSI_FILECODE (0xF082)
+#define PROC_MEM_FEAT_ECC_MFECC_FILECODE (0xF083)
+#define PROC_MEM_FEAT_ECC_MFEMP_FILECODE (0xF085)
+#define PROC_MEM_FEAT_EXCLUDIMM_MFDIMMEXCLUD_FILECODE (0xF086)
+#define PROC_MEM_FEAT_IDENDIMM_MFIDENDIMM_FILECODE (0xF088)
+#define PROC_MEM_FEAT_LVDDR3_MFLVDDR3_FILECODE (0xF08A)
+#define PROC_MEM_FEAT_MEMCLR_MFMEMCLR_FILECODE (0xF08B)
+#define PROC_MEM_FEAT_ODTHERMAL_MFODTHERMAL_FILECODE (0xF08D)
+#define PROC_MEM_FEAT_PARTRN_MFPARALLELTRAINING_FILECODE (0xF08F)
+#define PROC_MEM_FEAT_PARTRN_MFSTANDARDTRAINING_FILECODE (0xF091)
+#define PROC_MEM_FEAT_S3_MFS3_FILECODE (0xF092)
+#define PROC_MEM_FEAT_TABLE_MFTDS_FILECODE (0xF093)
+#define PROC_MEM_FEAT_CRAT_MFCRAT_FILECODE (0xF095)
+#define PROC_MEM_FEAT_DATAEYE_MF2DDATAEYE_FILECODE (0xF097)
+#define PROC_MEM_FEAT_RDWR2DTRAINING_MFWRDAT2DTRAINING_FILECODE (0xF098)
+#define PROC_MEM_FEAT_RDWR2DTRAINING_MFRDWR2DEYERIMSEARCH_FILECODE (0xF099)
+#define PROC_MEM_FEAT_RDWR2DTRAINING_MFRDDQS2DTRAINING_FILECODE (0xF09A)
+#define PROC_MEM_FEAT_RDWR2DTRAINING_MFRDWR2DTRAINING_FILECODE (0xF09B)
+#define PROC_MEM_FEAT_RDWR2DTRAINING_MFRDWR2DPATTERNGENERATION_FILECODE (0xF09C)
+#define PROC_MEM_FEAT_RDWR2DTRAINING_ML_MFRDWR2DML_FILECODE (0xF09E)
+#define PROC_MEM_FEAT_DLLPDBYPASS_MFDLLPDBYPASS_FILECODE (0xF0A0)
+
+#define PROC_MEM_MAIN_MDEF_FILECODE (0xF101)
+#define PROC_MEM_MAIN_MINIT_FILECODE (0xF102)
+#define PROC_MEM_MAIN_MM_FILECODE (0xF103)
+#define PROC_MEM_FEAT_DMI_MFDMI_FILECODE (0xF104)
+#define PROC_MEM_MAIN_MMECC_FILECODE (0xF105)
+#define PROC_MEM_MAIN_MMEXCLUDEDIMM_FILECODE (0xF106)
+#define PROC_MEM_MAIN_MMNODEINTERLEAVE_FILECODE (0xF10B)
+#define PROC_MEM_MAIN_MMONLINESPARE_FILECODE (0xF10C)
+#define PROC_MEM_MAIN_MMPARALLELTRAINING_FILECODE (0xF10D)
+#define PROC_MEM_MAIN_MMSTANDARDTRAINING_FILECODE (0xF10E)
+#define PROC_MEM_MAIN_MUC_FILECODE (0xF10F)
+#define PROC_MEM_MAIN_MMMEMCLR_FILECODE (0xF110)
+#define PROC_MEM_MAIN_MMFLOW_FILECODE (0xF112)
+#define PROC_MEM_MAIN_MERRHDL_FILECODE (0xF113)
+#define PROC_MEM_MAIN_MMLVDDR3_FILECODE (0xF115)
+#define PROC_MEM_MAIN_MMUMAALLOC_FILECODE (0xF116)
+#define PROC_MEM_MAIN_MMMEMRESTORE_FILECODE (0xF117)
+#define PROC_MEM_MAIN_MMCONDITIONALPSO_FILECODE (0xF118)
+#define PROC_MEM_MAIN_MMAGGRESSOR_FILECODE (0xF119)
+#define PROC_MEM_MAIN_ML_MMFLOWML_FILECODE (0xF126)
+
+#define PROC_MEM_NB_MN_FILECODE (0XF27C)
+#define PROC_MEM_NB_MNDCT_FILECODE (0XF27D)
+#define PROC_MEM_NB_MNPHY_FILECODE (0XF27E)
+#define PROC_MEM_NB_MNMCT_FILECODE (0XF27F)
+#define PROC_MEM_NB_MNS3_FILECODE (0XF280)
+#define PROC_MEM_NB_MNFLOW_FILECODE (0XF281)
+#define PROC_MEM_NB_MNFEAT_FILECODE (0XF282)
+#define PROC_MEM_NB_MNTRAIN3_FILECODE (0XF284)
+#define PROC_MEM_NB_MNREG_FILECODE (0XF285)
+#define PROC_MEM_NB_MNPMU_FILECODE (0xF2B7)
+#define PROC_MEM_NB_ML_MNREGML_FILECODE (0XF2CD)
+#define PROC_MEM_NB_ML_MNML_FILECODE (0XF2CE)
+#define PROC_MEM_NB_ML_MNMCTML_FILECODE (0XF2CF)
+#define PROC_MEM_NB_ML_MNOTML_FILECODE (0XF2D0)
+#define PROC_MEM_NB_ML_MNDCTML_FILECODE (0XF2D1)
+#define PROC_MEM_NB_ML_MNPHYML_FILECODE (0XF2D2)
+#define PROC_MEM_NB_ML_MNS3ML_FILECODE (0XF2D3)
+#define PROC_MEM_NB_ML_MNIDENDIMMML_FILECODE (0XF2D4)
+#define PROC_MEM_NB_ML_MNFLOWML_FILECODE (0XF2D5)
+#define PROC_MEM_NB_ML_MNPROTOML_FILECODE (0XF2D6)
+#define PROC_MEM_NB_ML_MNPSPML_FILECODE (0XF2E2)
+
+
+
+#define PROC_MEM_PS_MP_FILECODE (0XF401)
+#define PROC_MEM_PS_MPRTT_FILECODE (0XF422)
+#define PROC_MEM_PS_MPMAXFREQ_FILECODE (0XF423)
+#define PROC_MEM_PS_MPODTPAT_FILECODE (0XF424)
+#define PROC_MEM_PS_MPSAO_FILECODE (0XF425)
+#define PROC_MEM_PS_MPMR0_FILECODE (0XF426)
+#define PROC_MEM_PS_MPRC2IBT_FILECODE (0XF427)
+#define PROC_MEM_PS_MPRC10OPSPD_FILECODE (0XF428)
+#define PROC_MEM_PS_MPLRIBT_FILECODE (0XF429)
+#define PROC_MEM_PS_MPLRNPR_FILECODE (0XF42A)
+#define PROC_MEM_PS_MPLRNLR_FILECODE (0XF42B)
+#define PROC_MEM_PS_MPS2D_FILECODE (0XF436)
+#define PROC_MEM_PS_MPSEEDS_FILECODE (0XF437)
+#define PROC_MEM_PS_MPCADCFG_FILECODE (0XF43C)
+#define PROC_MEM_PS_MPDATACFG_FILECODE (0XF43D)
+#define PROC_MEM_PS_ML_MPSML3_FILECODE (0XF441)
+#define PROC_MEM_PS_ML_MPML3_FILECODE (0XF442)
+#define PROC_MEM_PS_ML_MPUML3_FILECODE (0XF443)
+#define PROC_MEM_PS_ML_FT3_MPSMLFT3_FILECODE (0XF444)
+
+#define PROC_MEM_TECH_MT_FILECODE (0XF501)
+#define PROC_MEM_TECH_MTHDI_FILECODE (0XF502)
+#define PROC_MEM_TECH_MTTDIMBT_FILECODE (0XF504)
+#define PROC_MEM_TECH_MTTECC_FILECODE (0XF505)
+#define PROC_MEM_TECH_MTTHRC_FILECODE (0XF506)
+#define PROC_MEM_TECH_MTTML_FILECODE (0XF507)
+#define PROC_MEM_TECH_MTTOPTSRC_FILECODE (0XF509)
+#define PROC_MEM_TECH_MTTSRC_FILECODE (0XF50B)
+#define PROC_MEM_TECH_MTTEDGEDETECT_FILECODE (0XF50C)
+#define PROC_MEM_TECH_DDR3_MT3_FILECODE (0XF581)
+#define PROC_MEM_TECH_DDR3_MTOT3_FILECODE (0XF583)
+#define PROC_MEM_TECH_DDR3_MTRCI3_FILECODE (0XF584)
+#define PROC_MEM_TECH_DDR3_MTSDI3_FILECODE (0XF585)
+#define PROC_MEM_TECH_DDR3_MTSPD3_FILECODE (0XF586)
+#define PROC_MEM_TECH_DDR3_MTTWL3_FILECODE (0XF587)
+#define PROC_MEM_TECH_DDR3_MTTECC3_FILECODE (0XF588)
+#define PROC_MEM_TECH_DDR3_MTLRDIMM3_FILECODE (0XF589)
+#define PROC_MEM_TECH_MTTHRCSEEDTRAIN_FILECODE (0XF58A)
+#define PROC_MEM_TECH_MTTRDDQS2DTRAINING_FILECODE (0XF58B)
+#define PROC_MEM_TECH_MTTRDDQS2DEYERIMSEARCH_FILECODE (0XF58C)
+
+#define PROC_RECOVERY_MEM_MRDEF_FILECODE (0XF801)
+#define PROC_RECOVERY_MEM_MRINIT_FILECODE (0XF802)
+#define PROC_RECOVERY_MEM_MRM_FILECODE (0XF803)
+#define PROC_RECOVERY_MEM_MRUC_FILECODE (0XF804)
+#define PROC_RECOVERY_MEM_TECH_MRTTPOS_FILECODE (0XF8C1)
+#define PROC_RECOVERY_MEM_TECH_MRTTSRC_FILECODE (0XF8C2)
+#define PROC_RECOVERY_MEM_TECH_DDR3_MRT3_FILECODE (0XF8C3)
+#define PROC_RECOVERY_MEM_TECH_DDR3_MRTRCI3_FILECODE (0XF8C4)
+#define PROC_RECOVERY_MEM_TECH_DDR3_MRTSDI3_FILECODE (0XF8C5)
+#define PROC_RECOVERY_MEM_TECH_DDR3_MRTSPD3_FILECODE (0XF8C6)
+#define PROC_RECOVERY_MEM_TECH_DDR3_MRTTWL3_FILECODE (0XF8C7)
+#define PROC_RECOVERY_MEM_NB_MRN_FILECODE (0XF8C8)
+#define PROC_RECOVERY_MEM_NB_MRNDCT_FILECODE (0XF8C9)
+#define PROC_RECOVERY_MEM_NB_MRNMCT_FILECODE (0XF8CA)
+#define PROC_RECOVERY_MEM_NB_MRNTRAIN3_FILECODE (0XF8CB)
+#define PROC_RECOVERY_MEM_TECH_MRTTHRC_FILECODE (0XF8CC)
+#define PROC_RECOVERY_MEM_PS_MRP_FILECODE (0XF8E0)
+#define PROC_RECOVERY_MEM_PS_MRPRTT_FILECODE (0XF8E1)
+#define PROC_RECOVERY_MEM_PS_MRPODTPAT_FILECODE (0XF8E2)
+#define PROC_RECOVERY_MEM_PS_MRPSAO_FILECODE (0XF8E3)
+#define PROC_RECOVERY_MEM_PS_MRPMR0_FILECODE (0XF8E4)
+#define PROC_RECOVERY_MEM_PS_MRPRC2IBT_FILECODE (0XF8E5)
+#define PROC_RECOVERY_MEM_PS_MRPRC10OPSPD_FILECODE (0XF8E6)
+#define PROC_RECOVERY_MEM_PS_MRPLRIBT_FILECODE (0XF8E7)
+#define PROC_RECOVERY_MEM_PS_MRPLRNPR_FILECODE (0XF8E8)
+#define PROC_RECOVERY_MEM_PS_MRPLRNLR_FILECODE (0XF8E9)
+#define PROC_RECOVERY_MEM_TECH_MRTTHRCSEEDTRAIN_FILECODE (0XF8FA)
+#define PROC_RECOVERY_MEM_NB_ML_MRNDCTML_FILECODE (0XF902)
+#define PROC_RECOVERY_MEM_NB_ML_MRNML_FILECODE (0XF903)
+#define PROC_RECOVERY_MEM_NB_ML_MRNMCTML_FILECODE (0XF904)
+#define PROC_RECOVERY_MEM_NB_ML_MRNPROTOML_FILECODE (0XF905)
+#define PROC_RECOVERY_MEM_PS_ML_MRPSML3_FILECODE (0XF906)
+#define PROC_RECOVERY_MEM_PS_ML_MRPML3_FILECODE (0XF907)
+#define PROC_RECOVERY_MEM_PS_ML_MRPUML3_FILECODE (0XF908)
+
+//Psp
+#define UEFI_PSP_DRIVERS_ITPMDXE_ITPMDXE_FILECODE (0xFA00)
+#define UEFI_PSP_DRIVERS_ITPMPEI_ITPMPEI_FILECODE (0xFA01)
+#define UEFI_PSP_DRIVERS_PSPP2CMBOX_PSPP2CMBOXCMD_FILECODE (0xFA02)
+#define UEFI_PSP_DRIVERS_PSPP2CMBOX_PSPP2CMBOX_FILECODE (0xFA03)
+#define UEFI_PSP_DRIVERS_PSPPEI_PSPPEI_FILECODE (0xFA04)
+#define UEFI_PSP_DRIVERS_PSPSMM_PSPRESUMEHANDLING_FILECODE (0xFA05)
+#define UEFI_PSP_DRIVERS_PSPSMM_PSPRESUMESERVICES_FILECODE (0xFA06)
+#define UEFI_PSP_DRIVERS_PSPSMM_PSPSMM_FILECODE (0xFA07)
+#define UEFI_PSP_DRIVERS_CSRESUMESMM_CSRESUMESMM_FILECODE (0xFA08)
+#define UEFI_PSP_LIBRARY_PSPBASELIB_PSPBASELIB_FILECODE (0xFA09)
+#define UEFI_PSP_LIBRARY_PSPMBOX_PSPMBOX_FILECODE (0xFA0A)
+#define UEFI_PSP_LIBRARY_SMMLOAD_SMMLOAD_FILECODE (0xFA0B)
+#define UEFI_PSP_DRIVERS_PSPDXE_PSPDXE_FILECODE (0xFA0C)
+#define UEFI_PSP_LIBRARY_PSPFTPMLIB_PSPFTPMLIB_FILECODE (0xFA0D)
+#define UEFI_PSP_LIBRARY_CCPSHALIB_CCPSHALIB_FILECODE (0xFA0E)
+#define UEFI_PSP_LIBRARY_CSRESUMESMMLIB_CSRESUMESMMLIB_FILECODE (0xFA0F)
+#endif // _FILECODE_H_
diff --git a/src/vendorcode/amd/pi/00730F01/Include/Ids.h b/src/vendorcode/amd/pi/00730F01/Include/Ids.h
new file mode 100644
index 0000000..854b915
--- /dev/null
+++ b/src/vendorcode/amd/pi/00730F01/Include/Ids.h
@@ -0,0 +1,1433 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD IDS Routines
+ *
+ * Contains AMD AGESA Integrated Debug Macros
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: IDS
+ * @e \$Revision: 281178 $ @e \$Date: 2013-12-18 02:14:15 -0600 (Wed, 18 Dec 2013) $
+ */
+/*****************************************************************************
+ *
+ * Copyright (c) 2008 - 2014, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ***************************************************************************/
+
+ /* Macros to aid debugging */
+ /* These definitions expand to zero (0) bytes of code when disabled */
+
+#ifndef _IDS_H_
+#define _IDS_H_
+
+#undef FALSE
+#undef TRUE
+#define FALSE 0
+#define TRUE 1
+// Proto type for optionsids.h
+typedef UINT32 IDS_STATUS; ///< Status of IDS function.
+#define IDS_SUCCESS ((IDS_STATUS) 0x00000000ul) ///< IDS Function is Successful.
+#define IDS_UNSUPPORTED ((IDS_STATUS) 0xFFFFFFFFul) ///< IDS Function is not existed.
+
+#define IDS_STRINGIZE(a) #a ///< for define stringize macro
+#ifndef IDS_DEADLOOP
+ #define IDS_DEADLOOP() { volatile UINTN __i; __i = 1; while (__i); }
+#endif
+/**
+ * IDS Option Hook Points
+ *
+ * These are the values to indicate hook point in AGESA for IDS Options.
+ *
+ */
+typedef enum { //vv- for debug reference only
+ IDS_INIT_EARLY_BEFORE, ///< 00 Option Hook Point before AGESA function AMD_INIT_EARLY.
+ ///< IDS Object is initialized.
+ ///< Override CPU Core Leveling Mode.
+ ///< Set P-State in Post
+ IDS_INIT_EARLY_AFTER, ///< 01 Option Hook Point after AGESA function AMD_INIT_EARLY.
+ IDS_INIT_LATE_BEFORE, ///< 02 Option Hook Point before AGESA function AMD_INIT_LATE.
+ ///< It will be used to control the following tables.
+ ///< ACPI P-State Table (_PSS, XPSS, _PCT, _PSD, _PPC)
+ ///< ACPI SRAT Table
+ ///< ACPI SLIT Table
+ ///< ACPI WHEA Table
+ ///< DMI Table
+ IDS_INIT_LATE_AFTER, ///< 03 Option Hook Point after AGESA function AMD_INIT_LATE.
+ IDS_INIT_MID_BEFORE, ///< 04 Option Hook Point before AGESA function AMD_INIT_MID.
+ IDS_INIT_MID_AFTER, ///< 05 Option Hook Point after AGESA function AMD_INIT_MID.
+ IDS_INIT_POST_BEFORE, ///< 06 Option Hook Point before AGESA function AMD_INIT_POST.
+ ///< Control Interleaving and DRAM memory hole
+ ///< Override the setting of ECC Control
+ ///< Override the setting of Online Spare Rank
+ IDS_INIT_POST_AFTER, ///< 07 Option Hook Point after AGESA function AMD_INIT_POST.
+ IDS_INIT_RESET_BEFORE, ///< 08 Option Hook Point before AGESA function AMD_INIT_RESET.
+ IDS_INIT_RESET_AFTER, ///< 09 Option Hook Point after AGESA function AMD_INIT_RESET.
+ IDS_INIT_POST_MID, ///< 0a Option Hook Point after AGESA function AMD_INIT_POST.
+ IDS_BEFORE_S3_SAVE, ///< 0b override any settings before S3 save.
+ IDS_BEFORE_S3_RESTORE, ///< 0c override any settings before S3 restore
+ IDS_AFTER_S3_SAVE, ///< 0d Override any settings after S3 save
+ IDS_AFTER_S3_RESTORE, ///< 0e Override any settings after S3 restore
+ IDS_BEFORE_DQS_TRAINING, ///< 0f override any settings before DQS training
+ IDS_BEFORE_DRAM_INIT, ///< 10 override any settings before Dram initialization
+ IDS_BEFORE_MEM_FREQ_CHG, ///< 11 override settings before MemClk frequency change
+ IDS_BEFORE_WARM_RESET , ///< 12 Override PCI or MSR Registers Before Warm Reset
+ IDS_BEFORE_PCI_INIT, ///< 13 Override PCI or MSR Registers Before PCI Init
+ IDS_BEFORE_AP_EARLY_HALT, ///< 14 Option Hook Point before AP early halt
+ IDS_BEFORE_S3_RESUME, ///< 15 Option Hook Point before s3 resume
+ IDS_AFTER_S3_RESUME, ///< 16 Option Hook Point after s3 resume
+ IDS_BEFORE_PM_INIT, ///< 17 Option Hook Point Before Pm Init
+
+ IDS_MT_BASE = 0x20, ///< 0x20 ~ 0x38 24 time points reserved for MTTime
+
+ IDS_PLATFORM_RSVD1 = 0x38, ///< from 0x38 to 0x3f will reserved for platform used
+ IDS_PLATFORM_RSVD2 = 0x39, ///< from 0x38 to 0x3f will reserved for platform used
+ IDS_PLATFORM_RSVD3 = 0x3a, ///< from 0x38 to 0x3f will reserved for platform used
+ IDS_PLATFORM_RSVD4 = 0x3b, ///< from 0x38 to 0x3f will reserved for platform used
+ IDS_PLATFORM_RSVD5 = 0x3c, ///< from 0x38 to 0x3f will reserved for platform used
+ IDS_PLATFORM_RSVD6 = 0x3d, ///< from 0x38 to 0x3f will reserved for platform used
+ IDS_PLATFORM_RSVD7 = 0x3e, ///< from 0x38 to 0x3f will reserved for platform used
+ IDS_PLATFORM_RSVD8 = 0x3f, ///< from 0x38 to 0x3f will reserved for platform used
+
+ // All the above timing point is used by BVM, their value should never be changed
+ IDS_INIT_DRAM_TABLE, ///< 40 Generate override table for Dram Timing
+ ///< Dram Controller, Drive Strength and DQS Timing
+ IDS_GET_DRAM_TABLE, ///< 41 Generate override table for Dram Timing
+ IDS_GANGING_MODE, ///< 42 override Memory Mode Unganged
+ IDS_POWERDOWN_MODE, ///< 43 override Power Down Mode
+ IDS_BURST_LENGTH32, ///< 44 override Burst Length32
+ IDS_ALL_MEMORY_CLOCK, ///< 45 override All Memory Clks Enable
+ IDS_ECC, ///< 46 override ECC parameter
+ IDS_ECCSYMBOLSIZE, ///< 47 override ECC symbol size
+ IDS_CPU_Early_Override, ///< 48 override CPU early parameter
+ IDS_CACHE_FLUSH_HLT, ///< 49 override Cache Flush Hlt
+ IDS_CHANNEL_INTERLEAVE, ///< 4a override Channel Interleave
+ IDS_MEM_ERROR_RECOVERY, ///< 4b override memory error recovery
+ IDS_MEM_RETRAIN_TIMES, ///< 4c override memory retrain times
+ IDS_MEM_SIZE_OVERLAY, ///< 4d Override the syslimit
+ IDS_CHECK_NEGATIVE_WL, ///< 4e Check for negative write leveling result
+ IDS_DLL_SHUT_DOWN, ///< 4f Check for Dll Shut Down
+ IDS_POR_MEM_FREQ, ///< 50 Entry to enable/disable MemClk frequency enforcement
+ IDS_PHY_DLL_STANDBY_CTRL, ///< 51 Enable/Disable Phy DLL standby feature
+ IDS_PLATFORMCFG_OVERRIDE, ///< 52 Hook for Override PlatformConfig structure
+ IDS_LOADCARD_ERROR_RECOVERY, ///< 53 Special error handling for load card support
+ IDS_MEM_IGNORE_ERROR, ///< 54 Ignore error and do not do fatal exit in memory
+ IDS_GNB_SMU_SERVICE_CONFIG, ///< 55 Config GNB SMU service
+ IDS_GNB_ORBDYNAMIC_WAKE, ///< 56 config GNB dynamic wake
+ IDS_GNB_PLATFORMCFG_OVERRIDE, ///< 57 override ids gnb platform config
+ IDS_GNB_LCLK_DPM_EN, ///< 58 override GNB LCLK DPM configuration
+ IDS_GNB_LCLK_DEEP_SLEEP, ///< 59 override GNB LCLK DPM deep sleep
+ IDS_GNB_CLOCK_GATING, ///< 5a Override GNB Clock gating config
+ IDS_NB_PSTATE_DIDVID, ///< 5b Override NB P-state settings
+ IDS_CPB_CTRL, ///< 5c Config the Core peformance boost feature
+ IDS_HTC_CTRL, ///< 5d Hook for Hardware Thermal Control
+ IDS_CC6_WORKAROUND, ///< 5e Hook for skip CC6 work around
+ IDS_MEM_MR0, ///< 5f Hook for override Memory Mr0 register
+ IDS_TRAP_TABLE, ///< 60 Hook for add IDS register table to the loop
+ IDS_NBBUFFERALLOCATIONATEARLY, ///< 61 Hook for override North bridge bufer allocation
+ IDS_BEFORE_S3_SPECIAL, ///< 62 Hook to bypass S3 special functions
+ IDS_SET_PCI_REGISTER_ENTRY, ///< 63 Hook to SetRegisterForPciEntry
+ IDS_ERRATUM463_WORKAROUND, ///< 64 Hook to Erratum 463 workaround
+ IDS_BEFORE_MEMCLR, ///< 65 Hook before set Memclr bit
+ IDS_OVERRIDE_IO_CSTATE, ///< 66 Hook for override io C-state setting
+ IDS_NBPSDIS_OVERRIDE, ///< 67 Hook for override NB pstate disable setting
+ IDS_NBPS_REG_OVERRIDE, ///< 68 Hook for override Memory NBps reg
+ IDS_LOW_POWER_PSTATE, ///< 69 Hook for disable Low power_Pstates feature
+ IDS_CST_CREATE, ///< 6a Hook for create _CST
+ IDS_CST_SIZE, ///< 6b Hook for get _CST size
+ IDS_ENFORCE_VDDIO, ///< 6c Hook to override VDDIO
+ IDS_STRETCH_FREQUENCY_LIMIT, ///< 6d Hook for enforcing memory stretch frequency limit
+ IDS_INIT_MEM_REG_TABLE, ///< 6e Hook for init memory register table
+ IDS_SKIP_FUSED_MAX_RATE, ///< 6f Hook to skip fused max rate cap
+ IDS_FCH_INIT_AT_RESET, ///< 70 Hook for FCH reset parameter
+ IDS_FCH_INIT_AT_ENV, ///< 71 Hook for FCH ENV parameter
+ IDS_ENFORCE_PLAT_TABLES, ///< 72 Hook to enforce platform specific tables
+ IDS_NBPS_MIN_FREQ, ///< 73 Hook for override MIN nb ps freq
+ IDS_GNB_FORCE_CABLESAFE, ///< 74 Hook for override Force Cable Safe
+ IDS_SKIP_PM_TRANSITION_STEP, ///< 75 Hook for provide IDS ability to skip this PM step
+ IDS_GNB_PROPERTY, ///< 76 Hook for GNB Property
+ IDS_GNB_PCIE_POWER_GATING, ///< 77 Hook for GNB PCIe Power Gating
+ IDS_MEM_DYN_DRAM_TERM, ///< 78 Hook for Override Dynamic Dram Term
+ IDS_MEM_DRAM_TERM, ///< 79 Hook for Override Dram Term
+ IDS_GNB_ALTVDDNB, ///< 7a Hook for Override AltVddNB
+ IDS_UCODE, ///< 7b Enable or Disable microcode patching
+ IDS_FAM_REG_GMMX, ///< 7c GMMX register access
+ IDS_MEMORY_POWER_POLICY, ///< 7d Memory power policy
+ IDS_GET_STRETCH_FREQUENCY_LIMIT, ///< 7e Hook for enforcing memory stretch frequency limit
+ IDS_CPU_FEAT, ///< 7f Hook for runtime force cpu feature disable
+ IDS_AFTER_DCT_PHY_ACCESS, ///< 80 Hook for DctAccessDone check
+ IDS_FORCE_PHY_TO_M0, ///< 81 Hook to bypass M0 enforcement
+ IDS_GNB_PMM_SWTJOFFSET, ///< 82 Hook to GNBSWTJOFFSET
+ IDS_LOCK_DRAM_CFG, ///< 83 Hook to BFLockDramCfg
+ IDS_BEFORE_GEN2_INIT, ///< 84 Hook to Before Gen2 Init
+ IDS_BEFORE_GPP_TRAINING, ///< 85 Hook to Before Gpp training
+ IDS_BEFORE_RECONFIGURATION, ///< 86 Hook to Before Reconfiguration
+ IDS_BEFORE_GEN3_INIT, ///< 87 Hook to Before Gen3 Init
+ IDS_BEFORE_POWER_GATING, ///< 88 Hook to Before Power Gating
+ IDS_AFTER_EARLY_INIT_ONCORE, ///< 89 Hook to after EarlyInit On Core
+ IDS_GNB_PCIE_PORT_REMAP, ///< 8a Hook to change mapping of PCIe devices
+ IDS_ECC_CONTROL, ///< 8b Enable/Disable ECC feature
+ IDS_GNB_PCIE_PHY_ISOLATION, ///< 8c Enable/Disable PCIE PHY ISOLATION
+ IDS_AFTER_RESTORING_PCI_REG, ///< 8d Hook after restoring PCI register during S3 resume
+ IDS_MSR_ACCESS_OVERRIDE, ///< 8e Hook to disable MSR access
+ IDS_REPORT_SMU_FW_VERSION, ///< 8f Hook to report SMU firmware version
+ IDS_GNB_LOAD_SAMU_PATCH, ///< 90 Hook to Load SAMU patch
+ IDS_DLLSTAGGERDLY_OVERRIDE, ///< 91 Hook to skip Dll Stagger Delay
+ IDS_CSAMPLE_TIMER, ///< 92 Hook to override CSampleTimer
+ IDS_PIPE_THROTTLE, ///< 93 Hook to override PipeThrottle
+ IDS_GNB_PMM_NATIVEGEN1PLL, ///< 94 Enable/Disable Native Gen1 PLL
+ IDS_BEFORE_PLAT_TABLES, ///< 95 Hook before processing platform specific tables
+ IDS_GNB_PCIE_MASTERPLL_SELECTION, ///< 96 Hook to override PCIe Master PLL selection
+ IDS_GNB_PCIE_PHYLANE_CONFIG, ///< 97 Hook to override PCIe PhyLane configuration
+ IDS_DSM_LP_SELECTION, ///< 98 Set Dsm low power mode
+ IDS_GNB_EQUAL_PRESET, ///< 99 Set equalization preset
+ IDS_GNB_GEN1_LOOPBACK, ///< 9a Override Gen 1 loopback mode
+ IDS_GNB_SMU_SERVICE_MASK, ///< 9b Override SMU service enablement mask
+ IDS_BEFORE_HT_MEM_MAP, ///< 9c Hook before mapping memory address space among DCTs
+ IDS_GNB_GEN3_SETTINGS_OVERRIDE, ///< 9d Hook to override Gen3 Adapt PI Offset Bypass Enable
+ IDS_GNB_TARGET_TDP, ///< 9e Hook to override Target TDP
+ IDS_GNB_LOAD_BUILD_OPTIONS, ///< 9f Hook to override gnb build options
+ IDS_GNB_SMU_BIOS_TABLE, ///< A0 Hook to override gnb smu bios table
+ IDS_LOW_POWER_RCVR_EN_CTRL, ///< A1 Hook to override LowPowerRcvrEn mode
+ IDS_OPTION_END ///< A2 End of IDS option
+} AGESA_IDS_OPTION;
+
+#include "OptionsIds.h"
+#include "Filecode.h"
+#include "IdsPerf.h"
+
+/* Initialize IDS controls */
+#ifndef IDSOPT_IDS_ENABLED
+ #define IDSOPT_IDS_ENABLED FALSE
+#endif
+
+#ifndef IDSOPT_CONTROL_ENABLED
+ #define IDSOPT_CONTROL_ENABLED FALSE
+#endif
+
+#ifndef IDSOPT_CONTROL_NV_TO_CMOS
+ #define IDSOPT_CONTROL_NV_TO_CMOS FALSE
+#endif
+
+#ifndef IDSOPT_TRACING_ENABLED
+ #define IDSOPT_TRACING_ENABLED FALSE
+#endif
+
+#ifndef IDSOPT_TRACE_USER_OPTIONS
+ #define IDSOPT_TRACE_USER_OPTIONS TRUE
+#endif
+
+#ifndef IDSOPT_PERF_ANALYSIS
+ #define IDSOPT_PERF_ANALYSIS FALSE
+#endif
+
+#ifndef IDSOPT_HEAP_CHECKING
+ #define IDSOPT_HEAP_CHECKING FALSE
+#endif
+
+#ifndef IDSOPT_ASSERT_ENABLED
+ #define IDSOPT_ASSERT_ENABLED FALSE
+#endif
+
+#ifndef IDSOPT_ERROR_TRAP_ENABLED
+ #define IDSOPT_ERROR_TRAP_ENABLED FALSE
+#endif
+
+#ifndef IDSOPT_CAR_CORRUPTION_CHECK_ENABLED
+ #define IDSOPT_CAR_CORRUPTION_CHECK_ENABLED FALSE
+#endif
+
+#ifndef IDSOPT_DEBUG_CODE_ENABLED
+ #define IDSOPT_DEBUG_CODE_ENABLED FALSE
+#endif
+
+#ifndef IDSOPT_IDT_EXCEPTION_TRAP
+ #define IDSOPT_IDT_EXCEPTION_TRAP FALSE
+#endif
+
+#ifndef IDSOPT_C_OPTIMIZATION_DISABLED
+ #define IDSOPT_C_OPTIMIZATION_DISABLED FALSE
+#endif
+
+#ifndef IDSOPT_TRACING_CONSOLE_HDTOUT
+ #define IDSOPT_TRACING_CONSOLE_HDTOUT TRUE
+#endif
+
+#ifndef IDSOPT_TRACING_CONSOLE_SERIALPORT
+ #define IDSOPT_TRACING_CONSOLE_SERIALPORT FALSE
+#endif
+
+#ifndef IDSOPT_TRACING_CONSOLE_REDIRECT_IO
+ #define IDSOPT_TRACING_CONSOLE_REDIRECT_IO FALSE
+#endif
+
+#ifndef IDSOPT_TRACING_CONSOLE_RAM
+ #define IDSOPT_TRACING_CONSOLE_RAM FALSE
+#endif
+
+#if IDSOPT_IDS_ENABLED == FALSE
+ #undef IDSOPT_CONTROL_ENABLED
+ #undef IDSOPT_TRACING_ENABLED
+ #undef IDSOPT_PERF_ANALYSIS
+ #undef IDSOPT_HEAP_CHECKING
+ #undef IDSOPT_ASSERT_ENABLED
+ #undef IDSOPT_ERROR_TRAP_ENABLED
+ #undef IDSOPT_CAR_CORRUPTION_CHECK_ENABLED
+ #undef IDSOPT_DEBUG_CODE_ENABLED
+ #undef IDSOPT_TRACE_USER_OPTIONS
+ #undef IDSOPT_TRACING_CONSOLE_HDTOUT
+ #undef IDSOPT_TRACING_CONSOLE_SERIALPORT
+ #undef IDSOPT_TRACING_CONSOLE_REDIRECT_IO
+ #undef IDSOPT_TRACING_CONSOLE_RAM
+
+ #define IDSOPT_CONTROL_ENABLED FALSE
+ #define IDSOPT_TRACING_ENABLED FALSE
+ #define IDSOPT_PERF_ANALYSIS FALSE
+ #define IDSOPT_HEAP_CHECKING FALSE
+ #define IDSOPT_ASSERT_ENABLED FALSE
+ #define IDSOPT_ERROR_TRAP_ENABLED FALSE
+ #define IDSOPT_CAR_CORRUPTION_CHECK_ENABLED FALSE
+ #define IDSOPT_DEBUG_CODE_ENABLED FALSE
+ #define IDSOPT_TRACE_USER_OPTIONS FALSE
+ #define IDSOPT_TRACING_CONSOLE_HDTOUT FALSE
+ #define IDSOPT_TRACING_CONSOLE_SERIALPORT FALSE
+ #define IDSOPT_TRACING_CONSOLE_REDIRECT_IO FALSE
+ #define IDSOPT_TRACING_CONSOLE_RAM FALSE
+#endif
+
+//Disable when master token Tracing is set to FALSE
+#if (IDSOPT_TRACING_ENABLED == FALSE) || (defined (IDSOPT_CUSTOMIZE_TRACING_SERVICE))
+ #undef IDSOPT_TRACING_CONSOLE_HDTOUT
+ #define IDSOPT_TRACING_CONSOLE_HDTOUT FALSE
+
+ #undef IDSOPT_TRACING_CONSOLE_SERIALPORT
+ #define IDSOPT_TRACING_CONSOLE_SERIALPORT FALSE
+
+ #undef IDSOPT_TRACING_CONSOLE_REDIRECT_IO
+ #define IDSOPT_TRACING_CONSOLE_REDIRECT_IO FALSE
+
+ #undef IDSOPT_TRACING_CONSOLE_RAM
+ #define IDSOPT_TRACING_CONSOLE_RAM FALSE
+#endif
+
+//Disable Tracing if all support HW layer set to FALSE
+#if ((IDSOPT_TRACING_CONSOLE_HDTOUT == FALSE) && (IDSOPT_TRACING_CONSOLE_SERIALPORT == FALSE) && (IDSOPT_TRACING_CONSOLE_REDIRECT_IO == FALSE) && (IDSOPT_TRACING_CONSOLE_RAM == FALSE))
+ #ifndef IDSOPT_CUSTOMIZE_TRACING_SERVICE
+ #undef IDSOPT_TRACING_ENABLED
+ #define IDSOPT_TRACING_ENABLED FALSE
+ #endif
+#endif
+/**
+ * Make a Progress Report to the User.
+ *
+ * This Macro is always enabled. The default action is to write the TestPoint value
+ * to an I/O port. The I/O port is 8 bits in size and the default address is 0x80.
+ * IBVs can change AGESA's default port by defining IDS_DEBUG_PORT to desired port
+ * in OptionsIds.h in their build tip.
+ *
+ * @param[in] TestPoint The value for display indicating progress
+ * @param[in,out] StdHeader Pointer of AMD_CONFIG_PARAMS
+ *
+ **/
+
+#define AGESA_TESTPOINT(TestPoint, StdHeader) IdsAgesaTestPoint ((TestPoint), (StdHeader))
+
+#ifndef IDS_DEBUG_PORT
+ #define IDS_DEBUG_PORT 0x80
+#endif
+
+/**
+ * @def STOP_HERE
+ * (macro) - Causes program to halt. This is @b only for use during active debugging .
+ *
+ * Causes the program to halt and display the file number of the source of the
+ * halt (displayed in decimal).
+ *
+ **/
+#if IDSOPT_IDS_ENABLED == TRUE
+ #ifdef STOP_CODE
+ #undef STOP_CODE
+ #endif
+ #define STOP_CODE (((UINT32)FILECODE)*0x10000ul + \
+ ((__LINE__) % 10) + (((__LINE__ / 10) % 10)*0x10) + \
+ (((__LINE__ / 100) % 10)*0x100) + (((__LINE__ / 1000) % 10)*0x1000))
+ #define STOP_HERE IdsErrorStop (STOP_CODE);
+#else
+ #define STOP_HERE STOP_HERE_Needs_To_Be_Removed //"WARNING: Debug code needs to be removed for production builds."
+#endif
+
+/**
+ * @def ASSERT
+ * Test an assertion that the given statement is True.
+ *
+ * The statement is evaluated to a boolean value. If the statement is True,
+ * then no action is taken (no error). If the statement is False, a error stop
+ * is generated to halt the program. Used for testing for fatal errors that
+ * must be resolved before production. This is used to do parameter checks,
+ * bounds checking, range checks and 'sanity' checks.
+ *
+ * @param[in] conditional Assert that evaluating this conditional results in TRUE.
+ *
+ **/
+#ifndef ASSERT
+ #if IDSOPT_ASSERT_ENABLED == TRUE
+ #ifdef STOP_CODE
+ #undef STOP_CODE
+ #endif
+ #define STOP_CODE (((UINT32)FILECODE)*0x10000ul + \
+ ((__LINE__) % 10) + (((__LINE__ / 10) % 10)*0x10) + \
+ (((__LINE__ / 100) % 10)*0x100) + (((__LINE__ / 1000) % 10)*0x1000))
+
+ #define ASSERT(conditional) ((conditional) ? 0 : IdsAssert (STOP_CODE));
+ #else
+ #define ASSERT(conditional)
+ #endif
+#endif
+
+#if IDSOPT_CAR_CORRUPTION_CHECK_ENABLED == TRUE
+ #undef IDSOPT_ERROR_TRAP_ENABLED
+ #define IDSOPT_ERROR_TRAP_ENABLED TRUE
+ #define IDS_CAR_CORRUPTION_CHECK(StdHeader) IdsCarCorruptionCheck(StdHeader)
+#else
+ #define IDS_CAR_CORRUPTION_CHECK(StdHeader)
+#endif
+/**
+ * @def DEBUG_CODE
+ * Make the code active when IDSOPT_DEBUG_CODE_ENABLED enable
+ *
+ */
+#ifndef DEBUG_CODE
+ #if IDSOPT_DEBUG_CODE_ENABLED == TRUE
+ #define DEBUG_CODE(Code) Code
+ #else
+ #define DEBUG_CODE(Code)
+ #endif
+#endif
+
+/**
+ * @def IDS_ERROR_TRAP
+ * Trap AGESA Error events with stop code display.
+ *
+ * Works similarly to use of "ASSERT (FALSE);"
+ *
+ */
+#if IDSOPT_ERROR_TRAP_ENABLED == TRUE
+ #ifdef STOP_CODE
+ #undef STOP_CODE
+ #endif
+ #define STOP_CODE (((UINT32)FILECODE)*0x10000ul + \
+ ((__LINE__) % 10) + (((__LINE__ / 10) % 10)*0x10) + \
+ (((__LINE__ / 100) % 10)*0x100) + (((__LINE__ / 1000) % 10)*0x1000))
+
+ #define IDS_ERROR_TRAP IdsErrorStop (STOP_CODE)
+#else
+ #define IDS_ERROR_TRAP
+#endif
+
+///give the extended Macro default value
+#ifndef __IDS_EXTENDED__
+ #define IDS_EXTENDED_HOOK(idsoption, dataptr, idsnvptr, stdheader) IDS_SUCCESS
+ #define IDS_TRACE_DEFAULT (0)
+ #define IDS_INITIAL_F15_TN_PM_STEP
+ #define IDS_INITIAL_F15_KV_PM_STEP
+ #define IDS_INITIAL_F15_CZ_PM_STEP
+ #define IDS_INITIAL_F16_KB_PM_STEP
+ #define IDS_INITIAL_F16_ML_PM_STEP
+ #define IDS_F15_TN_PM_CUSTOM_STEP
+ #define IDS_F15_KV_PM_CUSTOM_STEP
+ #define IDS_F15_CZ_PM_CUSTOM_STEP
+ #define IDS_F16_KB_PM_CUSTOM_STEP
+ #define IDS_F16_ML_PM_CUSTOM_STEP
+ #define IDS_EXTENDED_GET_DATA_EARLY(data, StdHeader)
+ #define IDS_EXTENDED_GET_DATA_LATE(data, StdHeader)
+ #define IDS_EXTENDED_HEAP_SIZE 0
+ #define IDS_EXT_INCLUDE_F15(file)
+ #define IDS_EXT_INCLUDE(file)
+ #define IDS_PAD_4K
+ #define IDS_EXTENDED_CODE(code)
+ #define SMU_FIRMWARE_PADS_1K
+#endif
+
+#ifndef IDS_NUM_NV_ITEM
+ #define IDS_NUM_NV_ITEM (IDS_NUM_EXT_NV_ITEM)
+#endif
+
+#define IDS_CMOS_INDEX_PORT 0x70
+#define IDS_CMOS_DATA_PORT 0x71
+#define IDS_CMOS_REGION_START 0x20
+#define IDS_CMOS_REGION_END 0x7F
+#define IDS_AP_GET_NV_FROM_CMOS(x) FALSE
+
+#if IDSOPT_CONTROL_ENABLED == TRUE
+ #define IDS_OPTION_HOOK(IdsOption, DataPtr, StdHeader) \
+ AmdIdsCtrlDispatcher ((IdsOption), (DataPtr), (StdHeader))
+
+ #define IDS_OPTION_CALLOUT(CallOutId, DataPtr, StdHeader) \
+ IdsOptionCallout ((CallOutId), (DataPtr), (StdHeader))
+ #if IDSOPT_CONTROL_NV_TO_CMOS == TRUE
+ #undef IDS_AP_GET_NV_FROM_CMOS
+ #define IDS_AP_GET_NV_FROM_CMOS(x) AmdIdsApGetNvFromCmos(x)
+ #ifdef IDS_OPT_CMOS_INDEX_PORT
+ #undef IDS_CMOS_INDEX_PORT
+ #define IDS_CMOS_INDEX_PORT IDS_OPT_CMOS_INDEX_PORT
+ #endif
+
+ #ifdef IDS_OPT_CMOS_DATA_PORT
+ #undef IDS_CMOS_DATA_PORT
+ #define IDS_CMOS_DATA_PORT IDS_OPT_CMOS_DATA_PORT
+ #endif
+
+ #ifdef IDS_OPT_CMOS_REGION_START
+ #undef IDS_CMOS_REGION_START
+ #define IDS_CMOS_REGION_START IDS_OPT_CMOS_REGION_START
+ #endif
+
+ #ifdef IDS_OPT_CMOS_REGION_END
+ #undef IDS_CMOS_REGION_END
+ #define IDS_CMOS_REGION_END IDS_OPT_CMOS_REGION_END
+ #endif
+ #endif
+#else
+ #define IDS_OPTION_HOOK(IdsOption, DataPtr, StdHeader)
+
+ #define IDS_OPTION_CALLOUT(CallOutId, DataPtr, StdHeader) AGESA_SUCCESS
+#endif
+
+/**
+ * Macro to add a *skip* hook for IDS options
+ *
+ * The default minimal action is to do nothing and there is no any code to increase.
+ * For debug environments, IDS dispatcher function will be called to perform
+ * the detailed action and to skip AGESA code if necessary.
+ *
+ * @param[in] IdsOption IDS Option ID for this hook point
+ * @param[in, out] DataPtr Data Pointer to override
+ * @param[in, out] StdHeader Pointer of AMD_CONFIG_PARAMS
+ *
+ *
+ **/
+
+#if IDSOPT_CONTROL_ENABLED == TRUE
+ #define IDS_SKIP_HOOK(IdsOption, DataPtr, StdHeader) \
+ if (AmdIdsCtrlDispatcher (IdsOption, DataPtr, StdHeader) == IDS_SUCCESS)
+#else
+ #define IDS_SKIP_HOOK(IdsOption, DataPtr, StdHeader)
+#endif
+
+/**
+ * Macro to add a heap manager routine
+ *
+ * when memory is allocated the heap manager actually allocates two extra dwords of data,
+ * one dword buffer before the actual memory, and one dword afterwards.
+ * a complete heap walk and check to be performed at any time.
+ * it would ASSERT if the heap is corrupt
+ *
+ * @param[in] StdHeader Pointer of AMD_CONFIG_PARAMS
+ *
+ *
+ **/
+
+// Heap debug feature
+#define SENTINEL_BEFORE_VALUE 0x64616548ul // "Head"
+#define SENTINEL_AFTER_VALUE 0x6C696154ul // "Tail"
+#if IDSOPT_IDS_ENABLED == TRUE
+ #if IDSOPT_HEAP_CHECKING == TRUE
+ #define SIZE_OF_SENTINEL 4
+ #define NUM_OF_SENTINEL 2 // Before ("Head") and After ("Tail")
+ #define SET_SENTINEL_BEFORE(NodePtr, AlignTo16Byte) (*(UINT32 *) ((UINT8 *) NodePtr + sizeof (BUFFER_NODE) + AlignTo16Byte) = SENTINEL_BEFORE_VALUE);
+ #define SET_SENTINEL_AFTER(NodePtr) (*(UINT32 *) ((UINT8 *) NodePtr + sizeof (BUFFER_NODE) + NodePtr->BufferSize - SIZE_OF_SENTINEL) = SENTINEL_AFTER_VALUE);
+ #define Heap_Check(stdheader) AmdHeapIntactCheck(stdheader)
+ #else
+ #define SIZE_OF_SENTINEL 0
+ #define NUM_OF_SENTINEL 0
+ #define SET_SENTINEL_BEFORE(NodePtr, AlignTo16Byte)
+ #define SET_SENTINEL_AFTER(NodePtr)
+ #define Heap_Check(stdheader)
+ #endif
+#else
+ #define SIZE_OF_SENTINEL 0
+ #define NUM_OF_SENTINEL 0
+ #define SET_SENTINEL_BEFORE(NodePtr, AlignTo16Byte)
+ #define SET_SENTINEL_AFTER(NodePtr)
+ #define Heap_Check(stdheader)
+#endif
+
+/**
+ * Macro to add IDT for debugging exception.
+ *
+ * A debug feature. Adding a 'jmp $' into every exception handler.
+ * So debugger could use HDT to skip 'jmp $' and execute the iret,
+ * then they could find which instruction cause the exception.
+ *
+ * @param[in] FunctionId IDS Function ID for this hook point
+ * @param[in, out] DataPtr Data Pointer to override
+ * @param[in, out] StdHeader Pointer of AMD_CONFIG_PARAMS
+ *
+ *
+ **/
+#if IDSOPT_IDS_ENABLED == TRUE
+ #if IDSOPT_IDT_EXCEPTION_TRAP == TRUE
+ #define IDS_EXCEPTION_TRAP(FunctionId, DataPtr, StdHeader) IdsExceptionTrap (FunctionId, DataPtr, StdHeader)
+ #else
+ #define IDS_EXCEPTION_TRAP(FunctionId, DataPtr, StdHeader)
+ #endif
+#else
+ #define IDS_EXCEPTION_TRAP(FunctionId, DataPtr, StdHeader)
+#endif
+
+
+ //Note a is from 0 to 63
+#define DEBUG_PRINT_SHIFT(a) ((UINT64)1 << a)
+//If you change the Bitmap definition below, please change the Hash in ParseFilter of hdtout2008.pl accordingly
+//Memory Masks
+#define MEM_SETREG DEBUG_PRINT_SHIFT (0)
+#define MEM_GETREG DEBUG_PRINT_SHIFT (1)
+#define MEM_FLOW DEBUG_PRINT_SHIFT (2)
+#define MEM_STATUS DEBUG_PRINT_SHIFT (3)
+#define MEM_UNDEF_BF DEBUG_PRINT_SHIFT (4)
+#define MEMORY_TRACE_RSV2 DEBUG_PRINT_SHIFT (5)
+#define MEMORY_TRACE_RSV3 DEBUG_PRINT_SHIFT (6)
+#define MEMORY_TRACE_RSV4 DEBUG_PRINT_SHIFT (7)
+#define MEMORY_TRACE_RSV5 DEBUG_PRINT_SHIFT (8)
+#define MEMORY_TRACE_RSV6 DEBUG_PRINT_SHIFT (9)
+
+//CPU Masks
+#define CPU_TRACE DEBUG_PRINT_SHIFT (10)
+#define CPU_TRACE_RSV1 DEBUG_PRINT_SHIFT (11)
+#define CPU_TRACE_RSV2 DEBUG_PRINT_SHIFT (12)
+#define CPU_TRACE_RSV3 DEBUG_PRINT_SHIFT (13)
+#define CPU_TRACE_RSV4 DEBUG_PRINT_SHIFT (14)
+#define CPU_TRACE_RSV5 DEBUG_PRINT_SHIFT (15)
+#define CPU_TRACE_RSV6 DEBUG_PRINT_SHIFT (16)
+#define CPU_TRACE_RSV7 DEBUG_PRINT_SHIFT (17)
+#define CPU_TRACE_RSV8 DEBUG_PRINT_SHIFT (18)
+#define CPU_TRACE_RSV9 DEBUG_PRINT_SHIFT (19)
+
+//GNB Masks
+#define GNB_TRACE DEBUG_PRINT_SHIFT (20)
+#define PCIE_MISC DEBUG_PRINT_SHIFT (21)
+#define PCIE_PORTREG_TRACE DEBUG_PRINT_SHIFT (22)
+#define PCIE_HOSTREG_TRACE DEBUG_PRINT_SHIFT (23)
+#define GNB_TRACE_RSV2 DEBUG_PRINT_SHIFT (24)
+#define NB_MISC DEBUG_PRINT_SHIFT (25)
+#define GNB_TRACE_RSV3 DEBUG_PRINT_SHIFT (26)
+#define GFX_MISC DEBUG_PRINT_SHIFT (27)
+#define NB_SMUREG_TRACE DEBUG_PRINT_SHIFT (28)
+#define GNB_TRACE_RSV1 DEBUG_PRINT_SHIFT (29)
+
+//Topology Masks
+#define TOPO_TRACE DEBUG_PRINT_SHIFT (30)
+#define TOPO_TRACE_RSV1 DEBUG_PRINT_SHIFT (31)
+#define TOPO_TRACE_RSV2 DEBUG_PRINT_SHIFT (32)
+#define TOPO_TRACE_RSV3 DEBUG_PRINT_SHIFT (33)
+#define TOPO_TRACE_RSV4 DEBUG_PRINT_SHIFT (34)
+#define TOPO_TRACE_RSV5 DEBUG_PRINT_SHIFT (35)
+#define TOPO_TRACE_RSV6 DEBUG_PRINT_SHIFT (36)
+#define TOPO_TRACE_RSV7 DEBUG_PRINT_SHIFT (37)
+#define TOPO_TRACE_RSV8 DEBUG_PRINT_SHIFT (38)
+#define TOPO_TRACE_RSV9 DEBUG_PRINT_SHIFT (39)
+
+//FCH Masks
+#define FCH_TRACE DEBUG_PRINT_SHIFT (40)
+#define FCH_TRACE_RSV1 DEBUG_PRINT_SHIFT (41)
+#define FCH_TRACE_RSV2 DEBUG_PRINT_SHIFT (42)
+#define FCH_TRACE_RSV3 DEBUG_PRINT_SHIFT (43)
+#define FCH_TRACE_RSV4 DEBUG_PRINT_SHIFT (44)
+#define FCH_TRACE_RSV5 DEBUG_PRINT_SHIFT (45)
+#define FCH_TRACE_RSV6 DEBUG_PRINT_SHIFT (46)
+#define FCH_TRACE_RSV7 DEBUG_PRINT_SHIFT (47)
+#define FCH_TRACE_RSV8 DEBUG_PRINT_SHIFT (48)
+#define FCH_TRACE_RSV9 DEBUG_PRINT_SHIFT (49)
+
+//Other Masks
+#define MAIN_FLOW DEBUG_PRINT_SHIFT (50)
+#define EVENT_LOG DEBUG_PRINT_SHIFT (51)
+#define PERFORMANCE_ANALYSE DEBUG_PRINT_SHIFT (52)
+
+//Ids Masks
+#define IDS_TRACE DEBUG_PRINT_SHIFT (53)
+#define BVM_TRACE DEBUG_PRINT_SHIFT (54)
+#define IDS_TRACE_RSV2 DEBUG_PRINT_SHIFT (55)
+#define IDS_TRACE_RSV3 DEBUG_PRINT_SHIFT (56)
+
+//S3
+#define S3_TRACE DEBUG_PRINT_SHIFT (57)
+
+//Library function to read/write PCI/MSR registers
+#define LIB_PCI_RD DEBUG_PRINT_SHIFT (58)
+#define LIB_PCI_WR DEBUG_PRINT_SHIFT (59)
+
+//AGESA test points
+#define TEST_POINT DEBUG_PRINT_SHIFT (60)
+
+//Reserved for platform log
+#define PLAT_RSV1 DEBUG_PRINT_SHIFT (61)
+#define PLAT_RSV2 DEBUG_PRINT_SHIFT (62)
+#define PLAT_RSV3 DEBUG_PRINT_SHIFT (63)
+
+#define GNB_TRACE_DEFAULT\
+ (\
+ GNB_TRACE | PCIE_MISC | NB_MISC | GFX_MISC \
+ )
+
+#define GNB_TRACE_REG\
+ (\
+ PCIE_PORTREG_TRACE | PCIE_HOSTREG_TRACE | \
+ NB_SMUREG_TRACE | GNB_TRACE_RSV1 \
+ )
+
+#define GNB_TRACE_ALL\
+ (\
+ GNB_TRACE_DEFAULT | GNB_TRACE_REG \
+ )
+
+#define CPU_TRACE_ALL\
+ (\
+ CPU_TRACE | CPU_TRACE_RSV1 | CPU_TRACE_RSV2 | CPU_TRACE_RSV3 | \
+ CPU_TRACE_RSV4 | CPU_TRACE_RSV5 | CPU_TRACE_RSV6 | CPU_TRACE_RSV7 | \
+ CPU_TRACE_RSV8 | CPU_TRACE_RSV9\
+ )
+
+#define MEMORY_TRACE_ALL\
+ (\
+ MEM_FLOW | MEM_GETREG | MEM_SETREG | MEM_STATUS | \
+ MEMORY_TRACE_RSV1 | MEMORY_TRACE_RSV2 | MEMORY_TRACE_RSV3 | MEMORY_TRACE_RSV4 | \
+ MEMORY_TRACE_RSV5 | MEMORY_TRACE_RSV6\
+ )
+
+#define TOPO_TRACE_ALL\
+ (\
+ TOPO_TRACE | TOPO_TRACE_RSV1 | TOPO_TRACE_RSV2 | TOPO_TRACE_RSV3 | \
+ TOPO_TRACE_RSV4 | TOPO_TRACE_RSV5 | TOPO_TRACE_RSV6 | TOPO_TRACE_RSV7 | \
+ TOPO_TRACE_RSV8 | TOPO_TRACE_RSV9\
+ )
+
+#define FCH_TRACE_ALL\
+ (\
+ FCH_TRACE | FCH_TRACE_RSV1 | FCH_TRACE_RSV2 | FCH_TRACE_RSV3 | \
+ FCH_TRACE_RSV4 | FCH_TRACE_RSV5 | FCH_TRACE_RSV6 | FCH_TRACE_RSV7 | \
+ FCH_TRACE_RSV8 | FCH_TRACE_RSV9\
+ )
+
+#define IDS_TRACE_ALL\
+ (\
+ IDS_TRACE | BVM_TRACE | IDS_TRACE_RSV2 | IDS_TRACE_RSV3\
+ )
+
+#define OTHER_TRACE_ALL\
+ (\
+ MAIN_FLOW | EVENT_LOG | PERFORMANCE_ANALYSE\
+ )
+
+
+#define TRACE_MASK_ALL (0xFFFFFFFFFFFFFFFFull)
+#ifndef IDS_DEBUG_PRINT_MASK
+ #define IDS_DEBUG_PRINT_MASK (GNB_TRACE_DEFAULT | CPU_TRACE_ALL | MEM_FLOW | MEM_STATUS | TOPO_TRACE_ALL | FCH_TRACE_ALL | MAIN_FLOW | IDS_TRACE_DEFAULT | TEST_POINT)
+#endif
+
+/// if no specific define INIT & EXIT will be NULL
+#define IDS_HDT_CONSOLE_INIT(x)
+#define IDS_HDT_CONSOLE_EXIT(x)
+
+/// AGESA tracing service
+#if IDSOPT_TRACING_ENABLED == TRUE
+ #ifdef VA_ARGS_SUPPORTED
+ #if IDSOPT_C_OPTIMIZATION_DISABLED == TRUE
+ #define IDS_HDT_CONSOLE(f, s, ...) AmdIdsDebugPrint (f, s, __VA_ARGS__)
+ #else
+ #pragma warning(disable: 4127)
+ #define IDS_HDT_CONSOLE(f, s, ...) if (f == MEM_FLOW) AmdIdsDebugPrintMem (s, __VA_ARGS__); \
+ else if (f == CPU_TRACE) AmdIdsDebugPrintCpu (s, __VA_ARGS__); \
+ else if (f == TOPO_TRACE) AmdIdsDebugPrintTopology (s, __VA_ARGS__); \
+ else if (f == GNB_TRACE) AmdIdsDebugPrintGnb (s, __VA_ARGS__); \
+ else AmdIdsDebugPrint (f, s, __VA_ARGS__)
+ #endif
+ #else
+ #define IDS_HDT_CONSOLE AmdIdsDebugPrint
+ #endif
+ #define CONSOLE AmdIdsDebugPrintAll
+ #define IDS_HDT_CONSOLE_DEBUG_CODE(Code) Code
+ #define IDS_TIMEOUT_CTL(t) IdsMemTimeOut (t)
+#else
+ #define IDS_HDT_CONSOLE 1 ? (VOID) 0 : AmdIdsDebugPrint
+ #define IDS_HDT_CONSOLE_DEBUG_CODE(Code)
+ #define CONSOLE CONSOLE_Needs_To_Be_Removed_For_Production_Build //"WARNING: CONSOLE needs to be removed for production builds."
+ #define IDS_TIMEOUT_CTL(t)
+#endif
+
+/// Macros for serial port tracing
+#ifdef IDSOPT_SERIAL_PORT
+ #define IDS_SERIAL_PORT IDSOPT_SERIAL_PORT
+#endif
+
+#ifndef IDS_SERIAL_PORT
+ #define IDS_SERIAL_PORT 0x3F8
+#endif
+
+// Macros for redirect IO tracing
+#ifdef IDSOPT_DEBUG_PRINT_IO_PORT
+ #define IDS_DEBUG_PRINT_IO_PORT IDSOPT_DEBUG_PRINT_IO_PORT
+#endif
+
+#ifndef IDS_DEBUG_PRINT_IO_PORT
+ #define IDS_DEBUG_PRINT_IO_PORT 0x80
+#endif
+
+#define IDS_DPRAM_BASE 0
+#define IDS_DPRAM_SIZE 0
+///Default policy, shift the old data when buffer full
+#define IDS_DPRAM_STOP_LOGGING_WHEN_BUFFER_FULL FALSE
+#if IDSOPT_TRACING_CONSOLE_RAM == TRUE
+ #ifdef IDSOPT_DPRAM_BASE
+ #undef IDS_DPRAM_BASE
+ #define IDS_DPRAM_BASE IDSOPT_DPRAM_BASE
+ #else
+ #error "Debug Print Ram Base not specified, please define IDSOPT_DPRAM_BASE in optionsids.h"
+ #endif
+
+ #ifdef IDSOPT_DPRAM_SIZE
+ #undef IDS_DPRAM_SIZE
+ #define IDS_DPRAM_SIZE IDSOPT_DPRAM_SIZE
+ #else
+ #error "Debug Print Ram size not specified, please define IDSOPT_DPRAM_SIZE in optionsids.h"
+ #endif
+
+ #ifdef IDSOPT_DPRAM_STOP_LOGGING_WHEN_BUFFER_FULL
+ #define IDS_DPRAM_STOP_LOGGING_WHEN_BUFFER_FULL IDSOPT_DPRAM_STOP_LOGGING_WHEN_BUFFER_FULL
+ #endif
+#endif
+/**
+ * Macros to add HDT OUT
+ *
+ * The default minimal action is to do nothing and there is no any code to increase.
+ * For debug environments, the debug information can be displayed in HDT or other
+ * devices.
+ *
+ **/
+#if IDSOPT_TRACING_CONSOLE_HDTOUT == TRUE
+ #undef IDS_HDT_CONSOLE_INIT
+ #undef IDS_HDT_CONSOLE_EXIT
+ #define IDS_HDT_CONSOLE_INIT(x) AmdIdsHdtOutInit (x)
+ #define IDS_HDT_CONSOLE_EXIT(x) AmdIdsHdtOutExit (x)
+ #define IDS_HDT_CONSOLE_S3_EXIT(x) AmdIdsHdtOutS3Exit (x)
+ #define IDS_HDT_CONSOLE_S3_AP_EXIT(x) AmdIdsHdtOutS3ApExit (x)
+
+ #define IDS_HDT_CONSOLE_FLUSH_BUFFER(x) AmdIdsHdtOutBufferFlush (x)
+ #define IDS_HDT_CONSOLE_ASSERT(x) AmdIdsDebugPrintAssert (x)
+ #define IDS_FUNCLIST_ADDR ScriptFuncList
+ #define IDS_FUNCLIST_EXTERN() extern SCRIPT_FUNCTION ScriptFuncList[]
+#else
+ #define IDS_HDT_CONSOLE_S3_EXIT(x)
+ #define IDS_HDT_CONSOLE_S3_AP_EXIT(x)
+ #define IDS_HDT_CONSOLE_FLUSH_BUFFER(x)
+ #define IDS_HDT_CONSOLE_ASSERT(x)
+ #define IDS_FUNCLIST_ADDR NULL
+ #define IDS_FUNCLIST_EXTERN()
+#endif
+
+#if IDSOPT_TRACING_ENABLED == TRUE
+ #ifdef IDSOPT_CUSTOMIZE_TRACING_SERVICE
+ #undef IDS_HDT_CONSOLE
+ #define IDS_HDT_CONSOLE IDSOPT_CUSTOMIZE_TRACING_SERVICE
+ #endif
+ #ifdef IDSOPT_CUSTOMIZE_TRACING_SERVICE_INIT
+ #undef IDS_HDT_CONSOLE_INIT
+ #define IDS_HDT_CONSOLE_INIT(x) IDSOPT_CUSTOMIZE_TRACING_SERVICE_INIT (x)
+ #endif
+ #ifdef IDSOPT_CUSTOMIZE_TRACING_SERVICE_EXIT
+ #undef IDS_HDT_CONSOLE_EXIT
+ #define IDS_HDT_CONSOLE_EXIT(x) IDSOPT_CUSTOMIZE_TRACING_SERVICE_EXIT (x)
+ #endif
+#endif
+
+#define IDS_TRACE_SHOW_BLD_OPT_CFG IDSOPT_TRACE_USER_OPTIONS
+
+#if IDSOPT_PERF_ANALYSIS == TRUE
+ #include "IdsPerf.h"
+ #ifdef STOP_CODE
+ #undef STOP_CODE
+ #endif
+ #define STOP_CODE (((UINT32)FILECODE)*0x10000ul + \
+ ((__LINE__) % 10) + (((__LINE__ / 10) % 10)*0x10) + \
+ (((__LINE__ / 100) % 10)*0x100) + (((__LINE__ / 1000) % 10)*0x1000))
+
+ #define IDS_PERF_TIMESTAMP(ID, StdHeader) IdsPerfTimestamp (STOP_CODE, ID, (StdHeader))
+ #define IDS_PERF_ANALYSE(StdHeader) IdsPerfAnalyseTimestamp (StdHeader)
+#else
+ #define IDS_PERF_TIMESTAMP(ID, StdHeader)
+ #define IDS_PERF_ANALYSE(StdHeader)
+#endif
+
+///For IDS feat use
+#define IDS_FAMILY_ALL 0xFFFFFFFFFFFFFFFFull
+#define IDS_BSP_ONLY TRUE
+#define IDS_ALL_CORES FALSE
+
+#define IDS_LATE_RUN_AP_TASK_ID PROC_IDS_LIBRARY_IDSLIB_FILECODE
+
+#define IDS_CALLOUT_INIT 0x01 ///< The function data of IDS callout function of initialization.
+
+#define IDS_CALLOUT_GNB_PPFUSE_OVERRIDE 0x83 ///< The function data of IDS callout function of GNB pp fuse table.
+#define IDS_CALLOUT_GNB_INTEGRATED_TABLE_CONFIG 0x84 ///< The function data of IDS callout function of GNB integrated table.
+#define IDS_CALLOUT_GNB_NB_POWERGATE_CONFIG 0x85 ///< The function data of IDS callout function of GNB NB power gate config.
+#define IDS_CALLOUT_GNB_PCIE_POWERGATE_CONFIG 0x86 ///< The function data of IDS callout function of GNB PCIE power gateconfig.
+#define IDS_CALLOUT_GNB_PCIE_PLATFORM_CONFIG 0x87 ///< The function data of IDS callout function of GNB pcie platform config.
+#define IDS_CALLOUT_GNB_PCIE_PHY_CONFIG 0x88 ///< The function data of IDS callout function of GNB pcie PHY config.
+#define IDS_CALLOUT_GNB_GMM_REGISTER_OVERRIDE 0x89 ///< The function data of IDS callout function of GNB GMM register override
+#define IDS_CALLOUT_FCH_INIT_RESET 0x8A ///< The function data of IDS callout function of FchInitReset
+#define IDS_CALLOUT_FCH_INIT_ENV 0x8B ///< The function data of IDS callout function of FchInitEnv.
+#define IDS_CALLOUT_POWER_PLAN_INIT 0x8C ///< The function data of IDS callout function of Override Power Plan Init
+#define IDS_CALLOUT_GET_PERF_BUFFER 0x8D ///< The function data of IDS callout function of get platform performance buffer.
+#define IDS_CALLOUT_GNB_PACKAGE_POWER_CONFIG 0x8E ///< The function data of IDS callout function of Bapm Package Power.
+#define IDS_CALLOUT_SMU_PORT80_LOGGING_BUFFER 0x8F ///< The function data of IDS callout function of SMU port80 logging buffer.
+#define IDS_CALLOUT_GNB_BEFORE_EARLY_INIT 0x90 ///< The function data of IDS callout function of GNB before early init.
+#define IDS_CALLOUT_GNB_SMUBIOSTABLE_OVERRIDE 0x91 ///< The function data of IDS callout function of GNB smu bios table.
+
+/// Function entry for HDT script to call
+typedef struct _SCRIPT_FUNCTION {
+ UINT32 FuncAddr; ///< Function address in ROM
+ CHAR8 FuncName[40]; ///< Function name
+} SCRIPT_FUNCTION;
+
+/// Data Structure for Mem ECC parameter override
+typedef struct {
+ IN BOOLEAN CfgEccRedirection; ///< ECC Redirection
+ IN UINT16 CfgScrubDramRate; ///< Scrub Dram Rate
+ IN UINT16 CfgScrubL2Rate; ///< Scrub L2Rate
+ IN UINT16 CfgScrubL3Rate; ///< Scrub L3Rate
+ IN UINT16 CfgScrubIcRate; ///< Scrub Ic Rate
+ IN UINT16 CfgScrubDcRate; ///< Scrub Dc Rate
+ IN BOOLEAN CfgEccSyncFlood; ///< ECC Sync Flood
+} ECC_OVERRIDE_STRUCT;
+
+
+
+
+/**
+ * AGESA Test Points
+ *
+ * These are the values displayed to the user to indicate progress through boot.
+ * These can be used in a debug environment to stop the debugger at a specific
+ * test point:
+ * For SimNow!, this command
+ * bi 81 w vb 49
+ * will stop the debugger on one of the TracePoints (49 is the TP value in this example).
+ *
+ */
+typedef enum {
+ StartProcessorTestPoints, ///< 00 Entry used for range testing for @b Processor related TPs
+
+ // Memory test points
+ TpProcMemBeforeMemDataInit, ///< 01 .. Memory structure initialization (Public interface)
+ TpProcMemBeforeSpdProcessing, ///< 02 .. SPD Data processing (Public interface)
+ TpProcMemAmdMemAuto, ///< 03 .. Memory configuration (Public interface)
+ TpProcMemDramInit, ///< 04 .. DRAM initialization
+ TpProcMemSPDChecking, ///< 05 ..
+ TpProcMemModeChecking, ///< 06 ..
+ TpProcMemSpeedTclConfig, ///< 07 .. Speed and TCL configuration
+ TpProcMemSpdTiming, ///< 08 ..
+ TpProcMemDramMapping, ///< 09 ..
+ TpProcMemPlatformSpecificConfig, ///< 0A ..
+ TPProcMemPhyCompensation, ///< 0B ..
+ TpProcMemStartDcts, ///< 0C ..
+ TpProcMemBeforeDramInit, ///< 0D .. (Public interface)
+ TpProcMemPhyFenceTraining, ///< 0E ..
+ TpProcMemSynchronizeDcts, ///< 0F ..
+ TpProcMemSystemMemoryMapping, ///< 10 ..
+ TpProcMemMtrrConfiguration, ///< 11 ..
+ TpProcMemDramTraining, ///< 12 ..
+ TpProcMemBeforeAnyTraining, ///< 13 .. (Public interface)
+ TpProcMemWriteLevelizationTraining, ///< 14 ..
+ TpProcMemWlFirstPass, ///< 15 .. Below 800Mhz first pass start
+ TpProcMemWlSecondPass, ///< 16 .. Above 800Mhz second pass start
+ TpProcMemWlTrainTargetDimm, ///< 17 .. Target DIMM configured
+ TpProcMemWlPrepDimms, ///< 18 .. Prepare DIMMS for WL
+ TpProcMemWlConfigDimms, ///< 19 .. Configure DIMMS for WL
+ TpProcMemReceiverEnableTraining, ///< 1A ..
+ TpProcMemRcvrStartSweep, ///< 1B .. Start sweep loop
+ TpProcMemRcvrSetDelay, ///< 1C .. Set receiver Delay
+ TpProcMemRcvrWritePattern, ///< 1D .. Write test pattern
+ TpProcMemRcvrReadPattern, ///< 1E .. Read test pattern
+ TpProcMemRcvrTestPattern, ///< 1F .. Compare test pattern
+ TpProcMemRcvrCalcLatency, ///< 20 .. Calculate MaxRdLatency per channel
+ TpProcMemReceiveDqsTraining, ///< 21 ..
+ TpProcMemRcvDqsSetDelay, ///< 22 .. Set Write Data delay
+ TpProcMemRcvDqsWritePattern, ///< 23 .. Write test pattern
+ TpProcMemRcvDqsStartSweep, ///< 24 .. Start read sweep
+ TpProcMemRcvDqsSetRcvDelay, ///< 25 .. Set Receive DQS delay
+ TpProcMemRcvDqsReadPattern, ///< 26 .. Read Test pattern
+ TpProcMemRcvDqsTstPattern, ///< 27 .. Compare Test pattern
+ TpProcMemRcvDqsResults, ///< 28 .. Update results
+ TpProcMemRcvDqsFindWindow, ///< 29 .. Start Find passing window
+ TpProcMemTransmitDqsTraining, ///< 2A ..
+ TpProcMemTxDqStartSweep, ///< 2B .. Start write sweep
+ TpProcMemTxDqSetDelay, ///< 2C .. Set Transmit DQ delay
+ TpProcMemTxDqWritePattern, ///< 2D .. Write test pattern
+ TpProcMemTxDqReadPattern, ///< 2E .. Read Test pattern
+ TpProcMemTxDqTestPattern, ///< 2F .. Compare Test pattern
+ TpProcMemTxDqResults, ///< 30 .. Update results
+ TpProcMemTxDqFindWindow, ///< 31 .. Start Find passing window
+ TpProcMemMaxRdLatencyTraining, ///< 32 ..
+ TpProcMemMaxRdLatStartSweep, ///< 33 .. Start sweep
+ TpProcMemMaxRdLatSetDelay, ///< 34 .. Set delay
+ TpProcMemMaxRdLatWritePattern, ///< 35 .. Write test pattern
+ TpProcMemMaxRdLatReadPattern, ///< 36 .. Read Test pattern
+ TpProcMemMaxRdLatTestPattern, ///< 37 .. Compare Test pattern
+ TpProcMemOnlineSpareInit, ///< 38 .. Online Spare init
+ TpProcMemBankInterleaveInit, ///< 39 .. Bank Interleave Init
+ TpProcMemNodeInterleaveInit, ///< 3A .. Node Interleave Init
+ TpProcMemChannelInterleaveInit, ///< 3B .. Channel Interleave Init
+ TpProcMemEccInitialization, ///< 3C .. ECC initialization
+ TpProcMemPlatformSpecificInit, ///< 3D .. Platform Specific Init
+ TpProcMemBeforeAgesaReadSpd, ///< 3E .. Before callout for "AgesaReadSpd"
+ TpProcMemAfterAgesaReadSpd, ///< 3F .. After callout for "AgesaReadSpd"
+ TpProcMemBeforeAgesaHookBeforeDramInit, ///< 40 .. Before optional callout "AgesaHookBeforeDramInit"
+ TpProcMemAfterAgesaHookBeforeDramInit, ///< 41 .. After optional callout "AgesaHookBeforeDramInit"
+ TpProcMemBeforeAgesaHookBeforeDQSTraining, ///< 42 .. Before optional callout "AgesaHookBeforeDQSTraining"
+ TpProcMemAfterAgesaHookBeforeDQSTraining, ///< 43 .. After optional callout "AgesaHookBeforeDQSTraining"
+ TpProcMemBeforeAgesaHookBeforeExitSelfRef, ///< 44 .. Before optional callout "AgesaHookBeforeDramInit"
+ TpProcMemAfterAgesaHookBeforeExitSelfRef, ///< 45 .. After optional callout "AgesaHookBeforeDramInit"
+ TpProcMemAfterMemDataInit, ///< 46 .. After MemDataInit
+ TpProcMemInitializeMCT, ///< 47 .. Before InitializeMCT
+ TpProcMemLvDdr3, ///< 48 .. Before LV DDR3
+ TpProcMemInitMCT, ///< 49 .. Before InitMCT
+ TpProcMemOtherTiming, ///< 4A.. Before OtherTiming
+ TpProcMemUMAMemTyping, ///< 4B .. Before UMAMemTyping
+ TpProcMemSetDqsEccTmgs, ///< 4C .. Before SetDqsEccTmgs
+ TpProcMemMemClr, ///< 4D .. Before MemClr
+ TpProcMemOnDimmThermal, ///< 4E .. Before On DIMM Thermal
+ TpProcMemDmi, ///< 4F .. Before DMI
+ TpProcMemEnd, ///< 50 .. End of memory code
+
+ // CPU test points
+ TpProcCpuEntryDmi, ///< 51 .. Entry point CreateDmiRecords
+ TpProcCpuEntryPstate, ///< 52 .. Entry point GenerateSsdt
+ TpProcCpuEntryPstateLeveling, ///< 53 .. Entry point PStateLeveling
+ TpProcCpuEntryPstateGather, ///< 54 .. Entry point PStateGatherData
+ TpProcCpuEntryWhea, ///< 55 .. Entry point CreateAcpiWhea
+ TpProcCpuEntrySrat, ///< 56 .. Entry point CreateAcpiSrat
+ TpProcCpuEntrySlit, ///< 57 .. Entry point CreateAcpiSlit
+ TpProcCpuProcessRegisterTables, ///< 58 .. Register table processing
+ TpProcCpuSetBrandID, ///< 59 .. Set brand ID
+ TpProcCpuLocalApicInit, ///< 5A .. Initialize local APIC
+ TpProcCpuLoadUcode, ///< 5B .. Load microcode patch
+ TpProcCpuBeforePMFeatureInit, ///< 5C .. BeforePM feature dispatch point
+ TpProcCpuPowerMgmtInit, ///< 5D .. Power Management table processing
+ TpProcCpuEarlyFeatureInit, ///< 5E .. Early feature dispatch point
+ TpProcCpuCoreLeveling, ///< 5F .. Core Leveling
+ TpProcCpuApMtrrSync, ///< 60 .. AP MTRR sync up
+ TpProcCpuPostFeatureInit, ///< 61 .. POST feature dispatch point
+ TpProcCpuBeforeRelinquishAPsFeatureInit = 0x63, ///< 63 .. Before Relinquishing control of APs feature dispatch point
+ TpProcCpuBeforeAllocateWheaBuffer, ///< 64 .. Before the WHEA init code calls out to allocate a buffer
+ TpProcCpuAfterAllocateWheaBuffer, ///< 65 .. After the WHEA init code calls out to allocate a buffer
+ TpProcCpuBeforeAllocateSratBuffer, ///< 66 .. Before the SRAT init code calls out to allocate a buffer
+ TpProcCpuAfterAllocateSratBuffer, ///< 67 .. After the SRAT init code calls out to allocate a buffer
+ TpProcCpuBeforeLocateSsdtBuffer, ///< 68 .. Before the P-state init code calls out to locate a buffer
+ TpProcCpuAfterLocateSsdtBuffer, ///< 69 .. After the P-state init code calls out to locate a buffer
+ TpProcCpuBeforeAllocateSsdtBuffer, ///< 6A .. Before the P-state init code calls out to allocate a buffer
+ TpProcCpuAfterAllocateSsdtBuffer, ///< 6B .. After the P-state init code calls out to allocate a buffer
+ TpProcCpuEntryCrat, ///< 6C .. Entry point CreateAcpiCrat
+ TpProcCpuEntryCdit, ///< 6D .. Entry point CreateAcpiCdit
+ TpProcCpuEntryScs, ///< 6E .. Entry point InitializeScsFeature
+
+ // Topology test points
+ TpProcTopologyEntry = 0x71, ///< 71 .. Topology Init begin
+ TpProcTopologyDone = 0x7C, ///< 7C .. Topology Init complete
+
+ // Extended memory test point
+ TpProcMemSendMRS2 = 0x80, ///< 80 .. Sending MRS2
+ TpProcMemSendMRS3, ///< 81 .. Sedding MRS3
+ TpProcMemSendMRS1, ///< 82 .. Sending MRS1
+ TpProcMemSendMRS0, ///< 83 .. Sending MRS0
+ TpProcMemContinPatternGenRead, ///< 84 .. Continuous Pattern Read
+ TpProcMemContinPatternGenWrite, ///< 85 .. Continuous Pattern Write
+ TpProcMem2dRdDqsTraining, ///< 86 .. Mem: 2d RdDqs Training begin
+ TpProcMemBefore2dTrainExtVrefChange,///< 87 .. Mem: Before optional callout to platform BIOS to change External Vref during 2d Training
+ TpProcMemAfter2dTrainExtVrefChange, ///< 88 .. Mem: After optional callout to platform BIOS to change External Vref during 2d Training
+ TpProcMemConfigureDCTForGeneral, ///< 89 .. Configure DCT For General use begin
+ TpProcMemProcConfigureDCTForTraining, ///< 8A .. Configure DCT For training begin
+ TpProcMemConfigureDCTNonExplicitSeq,///< 8B .. Configure DCT For Non-Explicit
+ TpProcMemSynchronizeChannels, ///< 8C .. Configure to Sync channels
+ TpProcMemC6StorageAllocation, ///< 8D .. Allocate C6 Storage
+
+ // Gnb Earlier init
+ TpGnbEarlierPcieConfigurationInit = 0x90, ///< 90 .. GNB earlier PCIE configuration init
+ TpGnbEarlierInterface = 0x91, ///< 91 .. GNB earlier interface
+ // Gnb Early init
+ TpGnbEarlyInterface = 0x92, ///< 92 .. GNB early interface
+ TpGnbPcieConfigurationMap, ///< 93 .. GNB early PCIE configuration map
+ TpGnbPcieEarlyInterface, ///< 94 .. GNB early PCIE interface
+ //Gnb post init
+ TpGnbPciePostEarlyInterface = 0x95, ///< 95 .. GNB post early interface
+ TpGnbGfxConfigPostInterface, ///< 96 .. GNB post GFX config interface
+ TpGnbGfxPostInterface, ///< 97 .. GNB post GFX interface
+ // Gnb post after DRAM init
+ TpGnbPostInterface = 0x98, ///< 98 .. GNB post after DRAM interface
+ TpGnbPciePostInterface, ///< 99 .. GNB post after DRAM PCIE interface
+ // Gnb Env init
+ TpGnbEnvInterface, ///< 9A .. GNB Env Nb interface
+ TpGnbPcieEnvInterface, ///< 9B .. GNB Env PCIE interface
+ TpGnbGfxConfigEnvInterface, ///< 9C .. GNB Env GFX Config interface
+ TpGnbGfxEnvInterface, ///< 9D .. GNB Env GFX interface
+ // Gnb Mid init
+ TpGnbGfxConfigMidInterface = 0xA1, ///< A1 .. GNB Mid GFX config interface
+ TpGnbGfxMidInterface, ///< A2 .. GNB Mid GFX interface
+ TpPcieMidInterface, ///< A3 .. GNB Mid PCIE interface
+ TpGnbMidInterface, ///< A4 .. GNB Mid interface
+ TpNbLclkFeature, ///< A5 .. GNB Mid Nclk feature
+ TpPciePowerGateFeature, ///< A6 .. GNB Mid pcie power gate feature
+ TpGnbPcieMaxPayloadInterface, ///< A7 .. GNB Mid pcie max payload interface
+ TpGnbPcieClkPmInterface, ///< A8 .. GNB Mid pcie clk pm port interface
+ TpGnbPcieAspmInterface, ///< A9 .. GNB Mid pcie ASPM interface
+ TpGnbNbIoapicInterface, ///< AA .. GNB Mid IOAPIC interface
+ // Gnb Late init
+ TpGnbPcieAlibFeature = 0xAB, ///< AB .. GNB Late pcie ALIB feature
+ TpGnbIommuIvrsTable, ///< AC .. GNB Late pcie IOMMU
+ // Gnb S3 Save
+ TpGnbGfxInitSview = 0xAD, ///< AD .. GNB S3SAVE GFX sview init
+ TpGnbAlibDispatchFeature = 0xAE, ///< AE .. GNB ALIB dispatch feature
+ EndGnbTestPoints = 0xAF, ///< AF End of TP range for GNB
+
+ StartFchTestPoints = 0xB0, ///< B0 Entry used for range testing for @b FCH related TPs
+ TpFchInitResetDispatching, ///< B1 .. FCH InitReset dispatch point
+ TpFchGppBeforePortTraining, ///< B2 .. Before FCH GPP port training
+ TpFchGppGen1PortPolling, ///< B3 .. FCH GPP port polling with GEN1 speed
+ TpFchGppGen2PortPolling, ///< B4 .. FCH GPP port polling with GEN2 speed
+ TpFchGppAfterPortTraining, ///< B5 .. After FCH GPP port training
+ TpFchInitEnvDispatching, ///< B6 .. FCH InitEnv dispatch point
+ TpFchInitMidDispatching, ///< B7 .. FCH InitMid dispatch point
+ TpFchInitLateDispatching, ///< B8 .. FCH InitLate dispatch point
+ TpFchGppHotPlugging, ///< B9 .. FCH GPP hot plug event
+ TpFchGppHotUnplugging, ///< BA .. AFCH GPP hot unplug event
+ TpFchInitS3EarlyDispatching, ///< BB .. FCH InitS3Early dispatch point
+ TpFchInitS3LateDispatching, ///< BC .. FCH InitS3Late dispatch point
+ EndFchTestPoints, ///< BF End of TP range for FCH
+
+ // Interface test points
+ TpIfAmdInitResetEntry = 0xC0, ///< C0 .. Entry to AmdInitReset
+ TpIfAmdInitResetExit, ///< C1 .. Exiting from AmdInitReset
+ TpIfAmdInitRecoveryEntry, ///< C2 .. Entry to AmdInitRecovery
+ TpIfAmdInitRecoveryExit, ///< C3 .. Exiting from AmdInitRecovery
+ TpIfAmdInitEarlyEntry, ///< C4 .. Entry to AmdInitEarly
+ TpIfAmdInitEarlyExit, ///< C5 .. Exiting from AmdInitEarly
+ TpIfAmdInitPostEntry, ///< C6 .. Entry to AmdInitPost
+ TpIfAmdInitPostExit, ///< C7 .. Exiting from AmdInitPost
+ TpIfAmdInitEnvEntry, ///< C8 .. Entry to AmdInitEnv
+ TpIfAmdInitEnvExit, ///< C9 .. Exiting from AmdInitEnv
+ TpIfAmdInitMidEntry, ///< CA .. Entry to AmdInitMid
+ TpIfAmdInitMidExit, ///< CB .. Exiting from AmdInitMid
+ TpIfAmdInitLateEntry, ///< CC .. Entry to AmdInitLate
+ TpIfAmdInitLateExit, ///< CD .. Exiting from AmdInitLate
+ TpIfAmdS3SaveEntry, ///< CE .. Entry to AmdS3Save
+ TpIfAmdS3SaveExit, ///< CF .. Exiting from AmdS3Save
+ TpIfAmdInitResumeEntry, ///< D0 .. Entry to AmdInitResume
+ TpIfAmdInitResumeExit, ///< D1 .. Exiting from AmdInitResume
+ TpIfAmdS3LateRestoreEntry, ///< D2 .. Entry to AmdS3LateRestore
+ TpIfAmdS3LateRestoreExit, ///< D3 .. Exiting from AmdS3LateRestore
+ TpIfAmdLateRunApTaskEntry, ///< D4 .. Entry to AmdS3LateRestore
+ TpIfAmdLateRunApTaskExit, ///< D5 .. Exiting from AmdS3LateRestore
+ TpIfAmdReadEventLogEntry, ///< D6 .. Entry to AmdReadEventLog
+ TpIfAmdReadEventLogExit, ///< D7 .. Exiting from AmdReadEventLog
+ TpIfAmdGetApicIdEntry, ///< D8 .. Entry to AmdGetApicId
+ TpIfAmdGetApicIdExit, ///< D9 .. Exiting from AmdGetApicId
+ TpIfAmdGetPciAddressEntry, ///< DA .. Entry to AmdGetPciAddress
+ TpIfAmdGetPciAddressExit, ///< DB .. Exiting from AmdGetPciAddress
+ TpIfAmdIdentifyCoreEntry, ///< DC .. Entry to AmdIdentifyCore
+ TpIfAmdIdentifyCoreExit, ///< DD .. Exiting from AmdIdentifyCore
+ TpIfBeforeRunApFromIds, ///< DE .. After IDS calls out to run code on an AP
+ TpIfAfterRunApFromIds, ///< DF .. After IDS calls out to run code on an AP
+ TpIfBeforeGetIdsData, ///< E0 .. Before IDS calls out to get IDS data
+ TpIfAfterGetIdsData, ///< E1 .. After IDS calls out to get IDS data
+ TpIfBeforeAllocateHeapBuffer, ///< E2 .. Before the heap manager calls out to allocate a buffer
+ TpIfAfterAllocateHeapBuffer, ///< E3 .. After the heap manager calls out to allocate a buffer
+ TpIfBeforeDeallocateHeapBuffer, ///< E4 .. Before the heap manager calls out to deallocate a buffer
+ TpIfAfterDeallocateHeapBuffer, ///< E5 .. After the heap manager calls out to deallocate a buffer
+ TpIfBeforeLocateHeapBuffer, ///< E6 .. Before the heap manager calls out to locate a buffer
+ TpIfAfterLocateHeapBuffer, ///< E7 .. After the heap manager calls out to locate a buffer
+ TpIfBeforeRunApFromAllAps, ///< E8 .. Before the BSP calls out to run code on an AP
+ TpIfAfterRunApFromAllAps, ///< E9 .. After the BSP calls out to run code on an AP
+ TpIfBeforeRunApFromAllCore0s, ///< EA .. Before the BSP calls out to run code on an AP
+ TpIfAfterRunApFromAllCore0s, ///< EB .. After the BSP calls out to run code on an AP
+ TpIfBeforeAllocateS3SaveBuffer, ///< EC .. Before the S3 save code calls out to allocate a buffer
+ TpIfAfterAllocateS3SaveBuffer, ///< ED .. After the S3 save code calls out to allocate a buffer
+ TpIfBeforeAllocateMemoryS3SaveBuffer, ///< EE .. Before the memory S3 save code calls out to allocate a buffer
+ TpIfAfterAllocateMemoryS3SaveBuffer, ///< EF .. After the memory S3 save code calls out to allocate a buffer
+ TpIfBeforeLocateS3PciBuffer, ///< F0 .. Before the memory code calls out to locate a buffer
+ TpIfAfterLocateS3PciBuffer, ///< F1 .. After the memory code calls out to locate a buffer
+ TpIfBeforeLocateS3CPciBuffer, ///< F2 .. Before the memory code calls out to locate a buffer
+ TpIfAfterLocateS3CPciBuffer, ///< F3 .. After the memory code calls out to locate a buffer
+ TpIfBeforeLocateS3MsrBuffer, ///< F4 .. Before the memory code calls out to locate a buffer
+ TpIfAfterLocateS3MsrBuffer, ///< F5 .. After the memory code calls out to locate a buffer
+ TpIfBeforeLocateS3CMsrBuffer, ///< F6 .. Before the memory code calls out to locate a buffer
+ TpIfAfterLocateS3CMsrBuffer, ///< F7 .. After the memory code calls out to locate a buffer
+ TpReadyToBoot, ///< F8 .. Ready to boot event
+ // PMU test points
+ TpProcMemPmuFailed, ///< F9 .. Failed PMU training.
+
+ EndAgesaTps = 0xFF, ///< Last defined AGESA TP
+} AGESA_TP;
+
+///Ids Feat description
+typedef enum {
+ IDS_FEAT_UCODE_UPDATE = 0x0000, ///< Feat for Ucode Update
+ IDS_FEAT_TARGET_PSTATE, ///< Feat for Target Pstate
+ IDS_FEAT_POSTPSTATE, ///< Feat for Post Pstate
+ IDS_FEAT_ECC_CTRL, ///< Feat for Ecc Control
+ IDS_FEAT_ECC_SYMBOL_SIZE, ///< Feat for Ecc symbol size
+ IDS_FEAT_DCT_ALLMEMCLK, ///< Feat for all memory clock
+ IDS_FEAT_DCT_GANGMODE, ///< Feat for Dct gang mode
+ IDS_FEAT_DCT_BURSTLENGTH, ///< Feat for dct burst length
+ IDS_FEAT_DCT_POWERDOWN, ///< Feat for dct power down
+ IDS_FEAT_DCT_DLLSHUTDOWN, ///< Feat for dct dll shut down
+ IDS_FEAT_HDTOUT, ///< Feat for hdt out
+ IDS_FEAT_GNB_PLATFORMCFG, ///< Feat for override GNB platform config
+ IDS_FEAT_CPB_CTRL, ///< Feat for Config the Core peformance boost feature
+ IDS_FEAT_HTC_CTRL, ///< Feat for Hardware Thermal Control
+ IDS_FEAT_MEMORY_MAPPING, ///< Feat for Memory Mapping
+ IDS_FEAT_POWER_POLICY, ///< Feat for Power Policy
+ IDS_FEAT_NV_TO_CMOS, ///< Feat for Save BSP Nv to CMOS
+ IDS_FEAT_COMMON, ///< Common Feat
+ IDS_FEAT_END = 0xFF ///< End of Common feat
+} IDS_FEAT;
+
+///Ids IDT table function ID
+typedef enum {
+ IDS_IDT_REPLACE_IDTR_FOR_BSC = 0x0000, ///< Function ID for saving IDTR for BSC
+ IDS_IDT_RESTORE_IDTR_FOR_BSC, ///< Function ID for restoring IDTR for BSC
+ IDS_IDT_UPDATE_EXCEPTION_VECTOR_FOR_AP, ///< Function ID for updating exception vector
+} IDS_IDT_FUNC_ID;
+
+typedef IDS_STATUS IDS_COMMON_FUNC (
+ IN OUT VOID *DataPtr,
+ IN OUT AMD_CONFIG_PARAMS *StdHeader,
+ IN IDS_NV_ITEM *IdsNvPtr
+ );
+
+typedef IDS_COMMON_FUNC *PIDS_COMMON_FUNC;
+
+/// Data Structure of IDS Feature block
+typedef struct _IDS_FAMILY_FEAT_STRUCT {
+ IDS_FEAT IdsFeat; ///< Ids Feat ID
+ BOOLEAN IsBsp; ///< swith for Bsp check
+ AGESA_IDS_OPTION IdsOption; ///< IDS option
+ UINT64 CpuFamily; ///<
+ PIDS_COMMON_FUNC pf_idsoption; ///<pointer to function
+} IDS_FAMILY_FEAT_STRUCT;
+
+
+/// Data Structure of IDS option
+typedef struct _IDS_OPTION_STRUCT {
+ AGESA_IDS_OPTION idsoption; ///< IDS option
+ PIDS_COMMON_FUNC pf_idsoption; ///<pointer to function
+} IDS_OPTION_STRUCT;
+
+/// Data Structure of IDS option table
+typedef struct _IDS_OPTION_STRUCT_TBL {
+ UINT8 version; ///<Version of IDS option table
+ UINT16 size; ///<Size of IDS option table
+ CONST IDS_OPTION_STRUCT *pIdsOptionStruct; ///<pointer to array of structure
+} IDS_OPTION_STRUCT_TBL;
+
+#define IDS_NV_TO_CMOS_LEN_BYTE 1
+#define IDS_NV_TO_CMOS_LEN_WORD 2
+#define IDS_NV_TO_CMOS_LEN_END 0xFF
+#define IDS_NV_TO_CMOS_ID_END 0xFFFF
+
+/// Data struct of set/get NV to/from CMOS
+typedef struct _IDS_NV_TO_CMOS {
+ UINT8 Length; ///< Length of NV
+ UINT16 IDS_NV_ID; ///< IDS id
+} IDS_NV_TO_CMOS;
+
+IDS_STATUS
+AmdIdsCtrlDispatcher (
+ IN AGESA_IDS_OPTION IdsOption,
+ IN OUT VOID *DataPtr,
+ IN OUT AMD_CONFIG_PARAMS *StdHeader
+ );
+
+AGESA_STATUS
+IdsOptionCallout (
+ IN UINTN CallOutId,
+ IN OUT VOID *DataPtr,
+ IN OUT AMD_CONFIG_PARAMS *StdHeader
+ );
+
+VOID
+AmdIdsHdtOutInit (
+ IN OUT AMD_CONFIG_PARAMS *StdHeader
+ );
+
+VOID
+AmdIdsHdtOutExit (
+ IN OUT AMD_CONFIG_PARAMS *StdHeader
+ );
+
+VOID
+AmdIdsHdtOutS3Exit (
+ IN OUT AMD_CONFIG_PARAMS *StdHeader
+ );
+
+VOID
+AmdIdsHdtOutS3ApExit (
+ IN OUT AMD_CONFIG_PARAMS *StdHeader
+ );
+
+VOID
+AmdIdsDebugPrint (
+ IN UINT64 Flag,
+ IN const CHAR8 *Format,
+ IN ...
+ );
+
+VOID
+AmdIdsDebugPrintTopology (
+ IN CHAR8 *Format,
+ IN ...
+ );
+
+VOID
+AmdIdsDebugPrintCpu (
+ IN CHAR8 *Format,
+ IN ...
+ );
+
+VOID
+AmdIdsDebugPrintMem (
+ IN CHAR8 *Format,
+ IN ...
+ );
+
+VOID
+AmdIdsDebugPrintGnb (
+ IN CHAR8 *Format,
+ IN ...
+ );
+
+VOID
+AmdIdsDebugPrintAll (
+ IN CHAR8 *Format,
+ IN ...
+ );
+
+VOID
+AmdIdsHdtOutBufferFlush (
+ IN OUT AMD_CONFIG_PARAMS *StdHeader
+ );
+
+VOID
+IdsMemTimeOut (
+ IN OUT VOID *DataPtr
+ );
+
+VOID
+IdsAgesaTestPoint (
+ IN AGESA_TP TestPoint,
+ IN OUT AMD_CONFIG_PARAMS *StdHeader
+ );
+
+/**
+ * IDS Backend Function for ASSERT
+ *
+ * Halt execution with stop code display. Stop Code is displayed on port 80, with rotation so that
+ * it is visible on 8, 16, or 32 bit display. The stop code is alternated with 0xDEAD on the display,
+ * to help distinguish the stop code from a post code loop.
+ * Additional features may be available if using simulation.
+ *
+ * @param[in] FileCode File code(define in FILECODE.h) mix with assert Line num.
+ *
+ * @retval TRUE No error
+**/
+BOOLEAN
+IdsAssert (
+ IN UINT32 FileCode
+ );
+
+/**
+ * The engine code for ASSERT MACRO
+ *
+ * Halt execution with stop code display. Stop Code is displayed on port 80, with rotation so that
+ * it is visible on 8, 16, or 32 bit display. The stop code is alternated with 0xDEAD on the display,
+ * to help distinguish the stop code from a post code loop.
+ * Additional features may be available if using simulation.
+ *
+ * @param[in] FileCode File code(define in FILECODE.h) mix with assert Line num.
+ *
+ */
+BOOLEAN
+IdsErrorStop (
+ IN UINT32 FileCode
+ );
+
+VOID
+IdsDelay (
+ IN VOID
+ );
+
+BOOLEAN
+AmdHeapIntactCheck (
+ IN AMD_CONFIG_PARAMS *StdHeader
+ );
+
+VOID
+IdsCarCorruptionCheck (
+ IN OUT AMD_CONFIG_PARAMS *StdHeader
+ );
+
+IDS_STATUS
+IdsExceptionTrap (
+ IN IDS_IDT_FUNC_ID IdsIdtFuncId,
+ IN VOID *DataPtr,
+ IN OUT AMD_CONFIG_PARAMS *StdHeader
+ );
+
+AGESA_STATUS
+IdsPerfTimestamp (
+ IN UINT32 LineInFile,
+ IN UINT32 Description,
+ IN OUT AMD_CONFIG_PARAMS *StdHeader
+ );
+
+AGESA_STATUS
+IdsPerfAnalyseTimestamp (
+ IN OUT AMD_CONFIG_PARAMS *StdHeader
+ );
+
+
+#if IDSOPT_IDS_ENABLED == FALSE
+ #undef IEM_SKIP_CODE
+ #undef IEM_INSERT_CODE
+#endif
+#ifndef IEM_SKIP_CODE
+ #define IEM_SKIP_CODE(L)
+#endif
+#ifndef IEM_INSERT_CODE
+ #define IEM_INSERT_CODE(L, Fn, Parm)
+#endif
+
+#endif // _IDS_H_
diff --git a/src/vendorcode/amd/pi/00730F01/Include/IdsPerf.h b/src/vendorcode/amd/pi/00730F01/Include/IdsPerf.h
new file mode 100644
index 0000000..2067ebb
--- /dev/null
+++ b/src/vendorcode/amd/pi/00730F01/Include/IdsPerf.h
@@ -0,0 +1,141 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD Integrated Debug Routines for performance analysis
+ *
+ * Contains AMD AGESA debug macros and functions for performance analysis
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: IDS
+ * @e \$Revision: 281178 $ @e \$Date: 2013-12-18 02:14:15 -0600 (Wed, 18 Dec 2013) $
+ */
+/*****************************************************************************
+ *
+ * Copyright (c) 2008 - 2014, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ***************************************************************************/
+
+#ifndef _IDS_PERFORMANCE_DATA_POINT
+
+ #define _IDS_PERFORMANCE_DATA_POINT
+ #define IDS_PERF_VERSION 0x00010000ul //version number 0.1.0.0
+/// Time points performance function used
+ typedef enum {
+ TP_BEGINPROCAMDINITEARLY = 0x100, ///< BeginProcAmdInitEarly
+ TP_ENDPROCAMDINITEARLY = 0x101, ///< EndProcAmdInitEarly
+ TP_BEGINAMDTOPOINITIALIZE = 0x102, ///< BeginAmdTopoInitialize
+ TP_ENDAMDTOPOINITIALIZE = 0x103, ///< EndAmdTopoInitialize
+ TP_BEGINGNBINITATEARLIER = 0x104, ///< BeginGnbInitAtEarlier
+ TP_ENDGNBINITATEARLIER = 0x105, ///< EndGnbInitAtEarlier
+ TP_BEGINAMDCPUEARLY = 0x106, ///< BeginAmdCpuEarly
+ TP_ENDAMDCPUEARLY = 0x107, ///< EndAmdCpuEarly
+ TP_BEGINGNBINITATEARLY = 0x108, ///< BeginGnbInitAtEarly
+ TP_ENDGNBINITATEARLY = 0x109, ///< EndGnbInitAtEarly
+ TP_BEGINPROCAMDINITENV = 0x10A, ///< BeginProcAmdInitEnv
+ TP_ENDPROCAMDINITENV = 0x10B, ///< EndProcAmdInitEnv
+ TP_BEGININITENV = 0x10C, ///< BeginInitEnv
+ TP_ENDINITENV = 0x10D, ///< EndInitEnv
+ TP_BEGINGNBINITATENV = 0x10E, ///< BeginGnbInitAtEnv
+ TP_ENDGNBINITATENV = 0x10F, ///< EndGnbInitAtEnv
+ TP_BEGINPROCAMDINITLATE = 0x110, ///< BeginProcAmdInitLate
+ TP_ENDPROCAMDINITLATE = 0x111, ///< EndProcAmdInitLate
+ TP_BEGINCREATSYSTEMTABLE = 0x112, ///< BeginCreatSystemTable
+ TP_ENDCREATSYSTEMTABLE = 0x113, ///< EndCreatSystemTable
+ TP_BEGINDISPATCHCPUFEATURESLATE = 0x114, ///< BeginDispatchCpuFeaturesLate
+ TP_ENDDISPATCHCPUFEATURESLATE = 0x115, ///< EndDispatchCpuFeaturesLate
+ TP_BEGINAMDCPULATE = 0x116, ///< BeginAmdCpuLate
+ TP_ENDAMDCPULATE = 0x117, ///< EndAmdCpuLate
+ TP_BEGINGNBINITATLATE = 0x118, ///< BeginGnbInitAtLate
+ TP_ENDGNBINITATLATE = 0x119, ///< EndGnbInitAtLate
+ TP_BEGINPROCAMDINITMID = 0x11A, ///< BeginProcAmdInitMid
+ TP_ENDPROCAMDINITMID = 0x11B, ///< EndProcAmdInitMid
+ TP_BEGININITMID = 0x11E, ///< BeginInitMid
+ TP_ENDINITMID = 0x11F, ///< EndInitMid
+ TP_BEGINGNBINITATMID = 0x120, ///< BeginGnbInitAtMid
+ TP_ENDGNBINITATMID = 0x121, ///< EndGnbInitAtMid
+ TP_BEGINPROCAMDINITPOST = 0x122, ///< BeginProcAmdInitPost
+ TP_ENDPROCAMDINITPOST = 0x123, ///< EndProcAmdInitPost
+ TP_BEGINGNBINITATPOST = 0x124, ///< BeginGnbInitAtPost
+ TP_ENDGNBINITATPOST = 0x125, ///< EndGnbInitAtPost
+ TP_BEGINAMDMEMAUTO = 0x126, ///< BeginAmdMemAuto
+ TP_ENDAMDMEMAUTO = 0x127, ///< EndAmdMemAuto
+ TP_BEGINAMDCPUPOST = 0x128, ///< BeginAmdCpuPost
+ TP_ENDAMDCPUPOST = 0x129, ///< EndAmdCpuPost
+ TP_BEGINGNBINITATPOSTAFTERDRAM = 0x12A, ///< BeginGnbInitAtPostAfterDram
+ TP_ENDGNBINITATPOSTAFTERDRAM = 0x12B, ///< EndGnbInitAtPostAfterDram
+ TP_BEGINPROCAMDINITRESET = 0x12C, ///< BeginProcAmdInitReset
+ TP_ENDPROCAMDINITRESET = 0x12D, ///< EndProcAmdInitReset
+ TP_BEGININITRESET = 0x12E, ///< BeginInitReset
+ TP_ENDINITRESET = 0x12F, ///< EndInitReset
+ TP_BEGINHTINITRESET = 0x130, ///< BeginHtInitReset
+ TP_ENDHTINITRESET = 0x131, ///< EndHtInitReset
+ TP_BEGINPROCAMDINITRESUME = 0x132, ///< BeginProcAmdInitResume
+ TP_ENDPROCAMDINITRESUME = 0x133, ///< EndProcAmdInitResume
+ TP_BEGINAMDMEMS3RESUME = 0x134, ///< BeginAmdMemS3Resume
+ TP_ENDAMDMEMS3RESUME = 0x135, ///< EndAmdMemS3Resume
+ TP_BEGINDISPATCHCPUFEATURESS3RESUME = 0x136, ///< BeginDispatchCpuFeaturesS3Resume
+ TP_ENDDISPATCHCPUFEATURESS3RESUME = 0x137, ///< EndDispatchCpuFeaturesS3Resume
+ TP_BEGINSETCORESTSCFREQSEL = 0x138, ///< BeginSetCoresTscFreqSel
+ TP_ENDSETCORESTSCFREQSEL = 0x139, ///< EndSetCoresTscFreqSel
+ TP_BEGINMEMFMCTMEMCLR_INIT = 0x13A, ///< BeginMemFMctMemClr_Init
+ TP_ENDNMEMFMCTMEMCLR_INIT = 0x13B, ///< EndnMemFMctMemClr_Init
+ TP_BEGINMEMBEFOREMEMDATAINIT = 0x13C, ///< BeginMemBeforeMemDataInit
+ TP_ENDMEMBEFOREMEMDATAINIT = 0x13D, ///< EndMemBeforeMemDataInit
+ TP_BEGINPROCAMDMEMAUTO = 0x13E, ///< BeginProcAmdMemAuto
+ TP_ENDPROCAMDMEMAUTO = 0x13F, ///< EndProcAmdMemAuto
+ TP_BEGINMEMMFLOWC32 = 0x140, ///< BeginMemMFlowC32
+ TP_ENDMEMMFLOWC32 = 0x141, ///< EndMemMFlowC32
+ TP_BEGINMEMINITIALIZEMCT = 0x142, ///< BeginMemInitializeMCT
+ TP_ENDMEMINITIALIZEMCT = 0x143, ///< EndMemInitializeMCT
+ TP_BEGINMEMSYSTEMMEMORYMAPPING = 0x144, ///< BeginMemSystemMemoryMapping
+ TP_ENDMEMSYSTEMMEMORYMAPPING = 0x145, ///< EndMemSystemMemoryMapping
+ TP_BEGINMEMDRAMTRAINING = 0x146, ///< BeginMemDramTraining
+ TP_ENDMEMDRAMTRAINING = 0x147, ///< EndMemDramTraining
+ TP_BEGINMEMOTHERTIMING = 0x148, ///< BeginMemOtherTiming
+ TP_ENDMEMOTHERTIMING = 0x149, ///< EndMemOtherTiming
+ TP_BEGINMEMUMAMEMTYPING = 0x14A, ///< BeginMemUMAMemTyping
+ TP_ENDMEMUMAMEMTYPING = 0x14B, ///< EndMemUMAMemTyping
+ TP_BEGINMEMMEMCLR = 0x14C, ///< BeginMemMemClr
+ TP_ENDMEMMEMCLR = 0x14D, ///< EndMemMemClr
+ TP_BEGINMEMMFLOWTN = 0x14E, ///< BeginMemMFlowTN
+ TP_ENDMEMMFLOWTN = 0x14F, ///< EndMemMFlowTN
+ TP_BEGINAGESAHOOKBEFOREDRAMINIT = 0x150, ///< BeginAgesaHookBeforeDramInit
+ TP_ENDAGESAHOOKBEFOREDRAMINIT = 0x151, ///< EndAgesaHookBeforeDramInit
+ TP_BEGINPROCMEMDRAMTRAINING = 0x152, ///< BeginProcMemDramTraining
+ TP_ENDPROCMEMDRAMTRAINING = 0x153, ///< EndProcMemDramTraining
+ TP_BEGINGNBINITATS3SAVE = 0x154, ///< BeginGnbInitAtS3Save
+ TP_ENDGNBINITATS3SAVE = 0x155, ///< EndGnbInitAtS3Save
+ TP_BEGINGNBLOADSCSDATA = 0x156, ///< BeginGnbLoadScsData
+ TP_ENDGNBLOADSCSDATA = 0x157, ///< EndGnbLoadScsData
+ TP_BEGINGNBPCIETRAINING = 0x158, ///< BeginGnbPcieTraining
+ TP_ENDGNBPCIETRAINING = 0x159, ///< EndGnbPcieTraining
+ TP_BEGINDISPATCHCPUFEATURESS3SAVE = 0x15A, ///< BeginDispatchCpuFeaturesS3Save
+ TP_ENDDISPATCHCPUFEATURESS3SAVE = 0x15B, ///< EndDispatchCpuFeaturesS3Save
+ IDS_TP_END ///< End of IDS TP list
+ } IDS_PERF_DATA;
+#endif
diff --git a/src/vendorcode/amd/pi/00730F01/Include/Options.h b/src/vendorcode/amd/pi/00730F01/Include/Options.h
new file mode 100644
index 0000000..94a180c
--- /dev/null
+++ b/src/vendorcode/amd/pi/00730F01/Include/Options.h
@@ -0,0 +1,67 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AGESA options structures
+ *
+ * Contains options control structures for the AGESA build options
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: Core
+ * @e \$Revision: 281178 $ @e \$Date: 2013-12-18 02:14:15 -0600 (Wed, 18 Dec 2013) $
+ */
+/*****************************************************************************
+ *
+ * Copyright (c) 2008 - 2014, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ***************************************************************************/
+
+#ifndef _OPTIONS_H_
+#define _OPTIONS_H_
+
+/**
+ * Provide topology limits for loops and runtime, based on supported families.
+ */
+typedef struct {
+ UINT32 PlatformNumberOfSockets; ///< The limit to the number of processors based on
+ ///< supported families and other build options.
+ UINT32 PlatformNumberOfModules; ///< The limit to the number of modules in a processor, based
+ ///< on supported families.
+} OPTIONS_CONFIG_TOPOLOGY;
+
+/**
+ * Dispatch Table.
+ *
+ * The push high dispatcher uses this table to find what entries are currently in the build image.
+ */
+typedef struct {
+ UINT32 FunctionId; ///< The function id specified.
+ IMAGE_ENTRY EntryPoint; ///< The corresponding entry point to call.
+} DISPATCH_TABLE;
+
+
+#endif // _OPTIONS_H_
diff --git a/src/vendorcode/amd/pi/00730F01/Include/PlatformMemoryConfiguration.h b/src/vendorcode/amd/pi/00730F01/Include/PlatformMemoryConfiguration.h
new file mode 100755
index 0000000..53212b2
--- /dev/null
+++ b/src/vendorcode/amd/pi/00730F01/Include/PlatformMemoryConfiguration.h
@@ -0,0 +1,516 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD Platform Specific Memory Configuration
+ *
+ * Contains Definitions and Macros for control of AGESA Memory code on a per platform basis
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: OPTION
+ * @e \$Revision: 281178 $ @e \$Date: 2013-12-18 02:14:15 -0600 (Wed, 18 Dec 2013) $
+ *
+ */
+/*****************************************************************************
+ *
+ * Copyright (c) 2008 - 2014, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ***************************************************************************/
+
+#ifndef _PLATFORM_MEMORY_CONFIGURATION_H_
+#define _PLATFORM_MEMORY_CONFIGURATION_H_
+
+/*----------------------------------------------------------------------------------------
+ * M I X E D (Definitions And Macros / Typedefs, Structures, Enums)
+ *----------------------------------------------------------------------------------------
+ */
+#ifndef PSO_ENTRY
+ #define PSO_ENTRY UINT8
+#endif
+
+/*----------------------------------------------------------------------------------------
+ * D E F I N I T I O N S A N D M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+/*----------------------------------------------------------------------------------------
+ * T Y P E D E F S, S T R U C T U R E S, E N U M S
+ *----------------------------------------------------------------------------------------
+ */
+/*----------------------------------------------------------------------------------------
+ * PLATFORM SPECIFIC MEMORY DEFINITIONS
+ *----------------------------------------------------------------------------------------
+ */
+///
+/// Memory Speed and DIMM Population Masks
+///
+///< DDR Speed Masks
+///< Specifies the DDR Speed on a memory channel
+///
+#define ANY_SPEED 0xFFFFFFFFul
+#define DDR400 ((UINT32) 1 << (DDR400_FREQUENCY / 66))
+#define DDR533 ((UINT32) 1 << (DDR533_FREQUENCY / 66))
+#define DDR667 ((UINT32) 1 << (DDR667_FREQUENCY / 66))
+#define DDR800 ((UINT32) 1 << (DDR800_FREQUENCY / 66))
+#define DDR1066 ((UINT32) 1 << (DDR1066_FREQUENCY / 66))
+#define DDR1333 ((UINT32) 1 << (DDR1333_FREQUENCY / 66))
+#define DDR1600 ((UINT32) 1 << (DDR1600_FREQUENCY / 66))
+#define DDR1866 ((UINT32) 1 << (DDR1866_FREQUENCY / 66))
+#define DDR2133 ((UINT32) 1 << (DDR2133_FREQUENCY / 66))
+#define DDR2400 ((UINT32) 1 << (DDR2400_FREQUENCY / 66))
+///
+///< DIMM POPULATION MASKS
+///< Specifies the DIMM Population on a channel (can be added together to specify configuration).
+///< ex. SR_DIMM0 + SR_DIMM1 : Single Rank Dimm in slot 0 AND Slot 1
+///< SR_DIMM0 + DR_DIMM0 + SR_DIMM1 +DR_DIMM1 : Single OR Dual rank in Slot 0 AND Single OR Dual rank in Slot 1
+///
+#define ANY_ 0xFF ///< Any dimm configuration the current channel
+#define SR_DIMM0 0x0001 ///< Single rank dimm in slot 0 on the current channel
+#define SR_DIMM1 0x0010 ///< Single rank dimm in slot 1 on the current channel
+#define SR_DIMM2 0x0100 ///< Single rank dimm in slot 2 on the current channel
+#define SR_DIMM3 0x1000 ///< Single rank dimm in slot 3 on the current channel
+#define DR_DIMM0 0x0002 ///< Dual rank dimm in slot 0 on the current channel
+#define DR_DIMM1 0x0020 ///< Dual rank dimm in slot 1 on the current channel
+#define DR_DIMM2 0x0200 ///< Dual rank dimm in slot 2 on the current channel
+#define DR_DIMM3 0x2000 ///< Dual rank dimm in slot 3 on the current channel
+#define QR_DIMM0 0x0004 ///< Quad rank dimm in slot 0 on the current channel
+#define QR_DIMM1 0x0040 ///< Quad rank dimm in slot 1 on the current channel
+#define QR_DIMM2 0x0400 ///< Quad rank dimm in slot 2 on the current channel
+#define QR_DIMM3 0x4000 ///< Quad rank dimm in slot 3 on the current channel
+#define LR_DIMM0 0x0001 ///< Lrdimm in slot 0 on the current channel
+#define LR_DIMM1 0x0010 ///< Lrdimm in slot 1 on the current channel
+#define LR_DIMM2 0x0100 ///< Lrdimm in slot 2 on the current channel
+#define LR_DIMM3 0x1000 ///< Lrdimm in slot 3 on the current channel
+#define ANY_DIMM0 0x000F ///< Any Dimm combination in slot 0 on the current channel
+#define ANY_DIMM1 0x00F0 ///< Any Dimm combination in slot 1 on the current channel
+#define ANY_DIMM2 0x0F00 ///< Any Dimm combination in slot 2 on the current channel
+#define ANY_DIMM3 0xF000 ///< Any Dimm combination in slot 3 on the current channel
+///
+///< CS POPULATION MASKS
+///< Specifies the CS Population on a channel (can be added together to specify configuration).
+///< ex. CS0 + CS1 : CS0 and CS1 apply to the setting
+///
+#define CS_ANY_ 0xFF ///< Any CS configuration
+#define CS0_ 0x01 ///< CS0 bit map mask
+#define CS1_ 0x02 ///< CS1 bit map mask
+#define CS2_ 0x04 ///< CS2 bit map mask
+#define CS3_ 0x08 ///< CS3 bit map mask
+#define CS4_ 0x10 ///< CS4 bit map mask
+#define CS5_ 0x20 ///< CS5 bit map mask
+#define CS6_ 0x40 ///< CS6 bit map mask
+#define CS7_ 0x80 ///< CS7 bit map mask
+///
+///< Number of Dimms on the current channel
+///< This is a mask used to indicate the number of dimms in a channel
+///< They can be added to indicate multiple conditions (i.e 1 OR 2 Dimms)
+///
+#define ANY_NUM 0xFF ///< Any number of Dimms
+#define NO_DIMM 0x00 ///< No Dimms present
+#define ONE_DIMM 0x01 ///< One dimm Poulated on the current channel
+#define TWO_DIMM 0x02 ///< Two dimms Poulated on the current channel
+#define THREE_DIMM 0x04 ///< Three dimms Poulated on the current channel
+#define FOUR_DIMM 0x08 ///< Four dimms Poulated on the current channel
+
+///
+///< DIMM VOLTAGE MASKS
+///
+#define VOLT_ANY_ 0xFF ///< Any voltage configuration
+#define VOLT1_5_ 0x01 ///< Voltage 1.5V bit map mask
+#define VOLT1_35_ 0x02 ///< Voltage 1.35V bit map mask
+#define VOLT1_25_ 0x04 ///< Voltage 1.25V bit map mask
+
+//
+// < Not applicable
+//
+#define NA_ 0 ///< Not applicable
+
+/*----------------------------------------------------------------------------------------
+ *
+ * Platform Specific Override Definitions for Socket, Channel and Dimm
+ * This indicates where a platform override will be applied.
+ *
+ *----------------------------------------------------------------------------------------
+ */
+///
+///< SOCKET MASKS
+///< Indicates associated processor sockets to apply override settings
+///
+#define ANY_SOCKET 0xFF ///< Apply to all sockets
+#define SOCKET0 0x01 ///< Apply to socket 0
+#define SOCKET1 0x02 ///< Apply to socket 1
+#define SOCKET2 0x04 ///< Apply to socket 2
+#define SOCKET3 0x08 ///< Apply to socket 3
+#define SOCKET4 0x10 ///< Apply to socket 4
+#define SOCKET5 0x20 ///< Apply to socket 5
+#define SOCKET6 0x40 ///< Apply to socket 6
+#define SOCKET7 0x80 ///< Apply to socket 7
+///
+///< CHANNEL MASKS
+///< Indicates Memory channels where override should be applied
+///
+#define ANY_CHANNEL 0xFF ///< Apply to all Memory channels
+#define CHANNEL_A 0x01 ///< Apply to Channel A
+#define CHANNEL_B 0x02 ///< Apply to Channel B
+#define CHANNEL_C 0x04 ///< Apply to Channel C
+#define CHANNEL_D 0x08 ///< Apply to Channel D
+///
+/// DIMM MASKS
+/// Indicates Dimm Slots where override should be applied
+///
+#define ALL_DIMMS 0xFF ///< Apply to all dimm slots
+#define DIMM0 0x01 ///< Apply to Dimm Slot 0
+#define DIMM1 0x02 ///< Apply to Dimm Slot 1
+#define DIMM2 0x04 ///< Apply to Dimm Slot 2
+#define DIMM3 0x08 ///< Apply to Dimm Slot 3
+///
+/// REGISTER ACCESS MASKS
+/// Not supported as an at this time
+///
+#define ACCESS_NB0 0x0
+#define ACCESS_NB1 0x1
+#define ACCESS_NB2 0x2
+#define ACCESS_NB3 0x3
+#define ACCESS_NB4 0x4
+#define ACCESS_PHY 0x5
+#define ACCESS_DCT_XT 0x6
+///
+/// MOTHER BOARD DESIGN LAYERS MASKS
+/// Indicates the layer design of mother board
+///
+#define LAYERS_4 0x0
+#define LAYERS_6 0x1
+/*----------------------------------------------------------------------------------------
+ *
+ * Platform Specific Overriding Table Definitions
+ *
+ *----------------------------------------------------------------------------------------
+ */
+
+#define PSO_END 0 ///< Table End
+#define PSO_CKE_TRI 1 ///< CKE Tristate Map
+#define PSO_ODT_TRI 2 ///< ODT Tristate Map
+#define PSO_CS_TRI 3 ///< CS Tristate Map
+#define PSO_MAX_DIMMS 4 ///< Max Dimms per channel
+#define PSO_CLK_SPEED 5 ///< Clock Speed
+#define PSO_DIMM_TYPE 6 ///< Dimm Type
+#define PSO_MEMCLK_DIS 7 ///< MEMCLK Disable Map
+#define PSO_MAX_CHNLS 8 ///< Max Channels per Socket
+#define PSO_BUS_SPEED 9 ///< Max Memory Bus Speed
+#define PSO_MAX_CHIPSELS 10 ///< Max Chipsel per Channel
+#define PSO_MEM_TECH 11 ///< Channel Memory Type
+#define PSO_WL_SEED 12 ///< DDR3 Write Levelization Seed delay
+#define PSO_RXEN_SEED 13 ///< Hardwared based RxEn seed
+#define PSO_NO_LRDIMM_CS67_ROUTING 14 ///< CS6 and CS7 are not Routed to all Memoy slots on a channel for LRDIMMs
+#define PSO_SOLDERED_DOWN_SODIMM_TYPE 15 ///< Soldered down SODIMM type
+#define PSO_LVDIMM_VOLT1_5_SUPPORT 16 ///< Force LvDimm voltage to 1.5V
+#define PSO_MIN_RD_WR_DATAEYE_WIDTH 17 ///< Min RD/WR dataeye width
+#define PSO_CPU_FAMILY_TO_OVERRIDE 18 ///< CPU family signature to tell following PSO macros are CPU family dependent
+#define PSO_MAX_SOLDERED_DOWN_DIMMS 19 ///< Max Soldered-down Dimms per channel
+#define PSO_MEMORY_POWER_POLICY 20 ///< Memory power policy override
+#define PSO_MOTHER_BOARD_LAYERS 21 ///< Mother board layer design
+
+/*----------------------------------
+ * CONDITIONAL PSO SPECIFIC ENTRIES
+ *---------------------------------*/
+// Condition Types
+#define CONDITIONAL_PSO_MIN 100 ///< Start of Conditional Entry Types
+#define PSO_CONDITION_AND 100 ///< And Block - Start of Conditional block
+#define PSO_CONDITION_LOC 101 ///< Location - Specify Socket, Channel, Dimms to be affected
+#define PSO_CONDITION_SPD 102 ///< SPD - Specify a specific SPD value on a Dimm on the channel
+#define PSO_CONDITION_REG 103 // Reserved
+#define PSO_CONDITION_MAX 103 ///< End Of Condition Entry Types
+// Action Types
+#define PSO_ACTION_MIN 120 ///< Start of Action Entry Types
+#define PSO_ACTION_ODT 120 ///< ODT values to override
+#define PSO_ACTION_ADDRTMG 121 ///< Address/Timing values to override
+#define PSO_ACTION_ODCCONTROL 122 ///< ODC Control values to override
+#define PSO_ACTION_SLEWRATE 123 ///< Slew Rate value to override
+#define PSO_ACTION_REG 124 // Reserved
+#define PSO_ACTION_SPEEDLIMIT 125 ///< Memory Bus speed Limit based on configuration
+#define PSO_ACTION_MAX 125 ///< End of Action Entry Types
+#define CONDITIONAL_PSO_MAX 139 ///< End of Conditional Entry Types
+
+/*----------------------------------
+ * TABLE DRIVEN PSO SPECIFIC ENTRIES
+ *---------------------------------*/
+// Condition descriptor
+#define PSO_TBLDRV_CONFIG 200 ///< Configuration Descriptor
+
+// Overriding entry types
+#define PSO_TBLDRV_START 210 ///< Start of Table Driven Overriding Entry Types
+#define PSO_TBLDRV_SPEEDLIMIT 210 ///< Speed Limit
+#define PSO_TBLDRV_ODT_RTTNOM 211 ///< RttNom
+#define PSO_TBLDRV_ODT_RTTWR 212 ///< RttWr
+#define PSO_TBLDRV_ODTPATTERN 213 ///< Odt Patterns
+#define PSO_TBLDRV_ADDRTMG 214 ///< Address/Timing values
+#define PSO_TBLDRV_ODCCTRL 215 ///< ODC Control values
+#define PSO_TBLDRV_SLOWACCMODE 216 ///< Slow Access Mode
+#define PSO_TBLDRV_MR0_CL 217 ///< MR0[CL]
+#define PSO_TBLDRV_MR0_WR 218 ///< MR0[WR]
+#define PSO_TBLDRV_RC2_IBT 219 ///< RC2[IBT]
+#define PSO_TBLDRV_RC10_OPSPEED 220 ///< RC10[Opearting Speed]
+#define PSO_TBLDRV_LRDIMM_IBT 221 ///< LrDIMM IBT
+#define PSO_TBLDRV_2D_TRAINING 222 ///< 2D training
+#define PSO_TBLDRV_INVALID_TYPE 223 ///< Invalid Type
+#define PSO_TBLDRV_END 223 ///< End of Table Driven Overriding Entry Types
+
+/*----------------------------------------------------------------------------------------
+ * CONDITIONAL OVERRIDE TABLE MACROS
+ *----------------------------------------------------------------------------------------
+ */
+#define CPU_FAMILY_TO_OVERRIDE(CpuFamilyRevision) \
+ PSO_CPU_FAMILY_TO_OVERRIDE, 4, \
+ ((CpuFamilyRevision) & 0x0FF), (((CpuFamilyRevision) >> 8)& 0x0FF), (((CpuFamilyRevision) >> 16)& 0x0FF), (((CpuFamilyRevision) >> 24)& 0x0FF)
+
+#define MEMCLK_DIS_MAP(SocketID, ChannelID, Bit0Map, Bit1Map, Bit2Map, Bit3Map, Bit4Map, Bit5Map, Bit6Map, Bit7Map) \
+ PSO_MEMCLK_DIS, 11, SocketID, ChannelID, ALL_DIMMS, Bit0Map, Bit1Map, Bit2Map, Bit3Map, Bit4Map, Bit5Map, Bit6Map \
+ , Bit7Map
+
+#define CKE_TRI_MAP(SocketID, ChannelID, Bit0Map, Bit1Map, Bit2Map, Bit3Map) \
+ PSO_CKE_TRI, 7, SocketID, ChannelID, ALL_DIMMS, Bit0Map, Bit1Map, Bit2Map, Bit3Map
+
+#define ODT_TRI_MAP(SocketID, ChannelID, Bit0Map, Bit1Map, Bit2Map, Bit3Map) \
+ PSO_ODT_TRI, 7, SocketID, ChannelID, ALL_DIMMS, Bit0Map, Bit1Map, Bit2Map, Bit3Map
+
+#define CS_TRI_MAP(SocketID, ChannelID, Bit0Map, Bit1Map, Bit2Map, Bit3Map, Bit4Map, Bit5Map, Bit6Map, Bit7Map) \
+ PSO_CS_TRI, 11, SocketID, ChannelID, ALL_DIMMS, Bit0Map, Bit1Map, Bit2Map, Bit3Map, Bit4Map, Bit5Map, Bit6Map, Bit7Map
+
+#define NUMBER_OF_DIMMS_SUPPORTED(SocketID, ChannelID, NumberOfDimmSlotsPerChannel) \
+ PSO_MAX_DIMMS, 4, SocketID, ChannelID, ALL_DIMMS, NumberOfDimmSlotsPerChannel
+
+#define NUMBER_OF_SOLDERED_DOWN_DIMMS_SUPPORTED(SocketID, ChannelID, NumberOfSolderedDownDimmsPerChannel) \
+ PSO_MAX_SOLDERED_DOWN_DIMMS, 4, SocketID, ChannelID, ALL_DIMMS, NumberOfSolderedDownDimmsPerChannel
+
+#define NUMBER_OF_CHIP_SELECTS_SUPPORTED(SocketID, ChannelID, NumberOfChipSelectsPerChannel) \
+ PSO_MAX_CHIPSELS, 4, SocketID, ChannelID, ALL_DIMMS, NumberOfChipSelectsPerChannel
+
+#define NUMBER_OF_CHANNELS_SUPPORTED(SocketID, NumberOfChannelsPerSocket) \
+ PSO_MAX_CHNLS, 4, SocketID, ANY_CHANNEL, ALL_DIMMS, NumberOfChannelsPerSocket
+
+#define OVERRIDE_DDR_BUS_SPEED(SocketID, ChannelID, TimingMode, BusSpeed) \
+ PSO_BUS_SPEED, 11, SocketID, ChannelID, ALL_DIMMS, TimingMode, (TimingMode >> 8), (TimingMode >> 16), (TimingMode >> 24), \
+ BusSpeed, (BusSpeed >> 8), (BusSpeed >> 16), (BusSpeed >> 24)
+
+#define DRAM_TECHNOLOGY(SocketID, MemTechType) \
+ PSO_MEM_TECH, 7, SocketID, ANY_CHANNEL, ALL_DIMMS, MemTechType, (MemTechType >> 8), (MemTechType >> 16), (MemTechType >> 24)
+
+#define WRITE_LEVELING_SEED(SocketID, ChannelID, DimmID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed, \
+ Byte6Seed, Byte7Seed, ByteEccSeed) \
+ PSO_WL_SEED, 12, SocketID, ChannelID, DimmID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed, \
+ Byte6Seed, Byte7Seed, ByteEccSeed
+
+#define HW_RXEN_SEED(SocketID, ChannelID, DimmID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed, \
+ Byte6Seed, Byte7Seed, ByteEccSeed) \
+ PSO_RXEN_SEED, 21, SocketID, ChannelID, DimmID, Byte0Seed, (Byte0Seed >> 8), Byte1Seed, (Byte1Seed >> 8), Byte2Seed, (Byte2Seed >> 8), \
+ Byte3Seed, (Byte3Seed >> 8), Byte4Seed, (Byte4Seed >> 8), Byte5Seed, (Byte5Seed >> 8), Byte6Seed, (Byte6Seed >> 8), \
+ Byte7Seed, (Byte7Seed >> 8), ByteEccSeed, (ByteEccSeed >> 8)
+
+#define NO_LRDIMM_CS67_ROUTING(SocketID, ChannelID) \
+ PSO_NO_LRDIMM_CS67_ROUTING, 4, SocketID, ChannelID, ALL_DIMMS, TRUE
+
+#define SOLDERED_DOWN_SODIMM_TYPE(SocketID, ChannelID) \
+ PSO_SOLDERED_DOWN_SODIMM_TYPE, 4, SocketID, ChannelID, ALL_DIMMS, TRUE
+
+#define LVDIMM_FORCE_VOLT1_5_FOR_D0 \
+ PSO_LVDIMM_VOLT1_5_SUPPORT, 4, ANY_SOCKET, ANY_CHANNEL, ALL_DIMMS, TRUE
+
+#define MIN_RD_WR_DATAEYE_WIDTH(SocketID, ChannelID, MinRdDataeyeWidth, MinWrDataeyeWidth) \
+ PSO_MIN_RD_WR_DATAEYE_WIDTH, 5, SocketID, ChannelID, ALL_DIMMS, MinRdDataeyeWidth, MinWrDataeyeWidth
+
+#define MEMORY_POWER_POLICY_OVERRIDE(PowerPolicy) \
+ PSO_MEMORY_POWER_POLICY, 4, ANY_SOCKET, ANY_CHANNEL, ALL_DIMMS, PowerPolicy
+
+#define MOTHER_BOARD_LAYERS(Layers) \
+ PSO_MOTHER_BOARD_LAYERS, 4, ANY_SOCKET, ANY_CHANNEL, ALL_DIMMS, Layers
+
+/*----------------------------------------------------------------------------------------
+ * CONDITIONAL OVERRIDE TABLE MACROS
+ *----------------------------------------------------------------------------------------
+ */
+#define CONDITION_AND \
+ PSO_CONDITION_AND, 0
+
+#define COND_LOC(SocketMsk, ChannelMsk, DimmMsk) \
+ PSO_CONDITION_LOC, 3, SocketMsk, ChannelMsk, DimmMsk
+
+#define COND_SPD(Byte, Mask, Value) \
+ PSO_CONDITION_SPD, 3, Byte, Mask, Value
+
+#define COND_REG(Access, Offset, Mask, Value) \
+ PSO_CONDITION_REG, 11, Access, (Offset & 0x0FF), (Offset >> 8), \
+ ((Mask) & 0x0FF), (((Mask) >> 8) & 0x0FF), (((Mask) >> 16) & 0x0FF), (((Mask) >> 24) & 0x0FF), \
+ ((Value) & 0x0FF), (((Value) >> 8) & 0x0FF), (((Value) >> 16) & 0x0FF), (((Value) >> 24) & 0x0FF)
+
+#define ACTION_ODT(Frequency, Dimms, QrDimms, DramOdt, QrDramOdt, DramDynOdt) \
+ PSO_ACTION_ODT, 9, \
+ ((Frequency) & 0x0FF), (((Frequency) >> 8)& 0x0FF), (((Frequency) >> 16)& 0x0FF), ((Frequency >> 24)& 0x0FF), \
+ Dimms, QrDimms, DramOdt, QrDramOdt, DramDynOdt
+
+#define ACTION_ADDRTMG(Frequency, DimmConfig, AddrTmg) \
+ PSO_ACTION_ADDRTMG, 10, \
+ ((Frequency) & 0x0FF), (((Frequency) >> 8)& 0x0FF), (((Frequency) >> 16)& 0x0FF), (((Frequency) >> 24)& 0x0FF), \
+ ((DimmConfig) & 0x0FF), (((DimmConfig) >> 8) & 0x0FF), \
+ (AddrTmg & 0x0FF), ((AddrTmg >> 8)& 0x0FF), ((AddrTmg >> 16)& 0x0FF), ((AddrTmg >> 24)& 0x0FF)
+
+#define ACTION_ODCCTRL(Frequency, DimmConfig, OdcCtrl) \
+ PSO_ACTION_ODCCONTROL, 10, \
+ ((Frequency) & 0x0FF), (((Frequency) >> 8)& 0x0FF), (((Frequency) >> 16)& 0x0FF), (((Frequency) >> 24)& 0x0FF), \
+ ((DimmConfig) & 0x0FF), (((DimmConfig) >> 8) & 0x0FF), \
+ (OdcCtrl & 0x0FF), ((OdcCtrl >> 8)& 0x0FF), ((OdcCtrl >> 16)& 0x0FF), ((OdcCtrl >> 24)& 0x0FF)
+
+#define ACTION_SLEWRATE(Frequency, DimmConfig, SlewRate) \
+ PSO_ACTION_SLEWRATE, 10, \
+ ((Frequency) & 0x0FF), (((Frequency) >> 8)& 0x0FF), (((Frequency) >> 16)& 0x0FF), (((Frequency) >> 24)& 0x0FF), \
+ ((DimmConfig) & 0x0FF), (((DimmConfig) >> 8) & 0x0FF), \
+ (SlewRate & 0x0FF), ((SlewRate >> 8)& 0x0FF), ((SlewRate >> 16)& 0x0FF), ((SlewRate >> 24)& 0x0FF)
+
+#define ACTION_SPEEDLIMIT(DimmConfig, Dimms, SpeedLimit15, SpeedLimit135, SpeedLimit125) \
+ PSO_ACTION_SPEEDLIMIT, 9, \
+ ((DimmConfig) & 0x0FF), (((DimmConfig) >> 8) & 0x0FF), Dimms, \
+ (SpeedLimit15 & 0x0FF), ((SpeedLimit15 >> 8)& 0x0FF), \
+ (SpeedLimit135 & 0x0FF), ((SpeedLimit135 >> 8)& 0x0FF), \
+ (SpeedLimit125 & 0x0FF), ((SpeedLimit125 >> 8)& 0x0FF)
+
+/*----------------------------------------------------------------------------------------
+ * END OF CONDITIONAL OVERRIDE TABLE MACROS
+ *----------------------------------------------------------------------------------------
+ */
+/*----------------------------------------------------------------------------------------
+ * TABLE DRIVEN OVERRIDE MACROS
+ *----------------------------------------------------------------------------------------
+ */
+/// Configuration sub-descriptors
+typedef enum {
+ CONFIG_GENERAL, ///< CONFIG_GENERAL
+ CONFIG_SPEEDLIMIT, ///< CONFIG_SPEEDLIMIT
+ CONFIG_RC2IBT, ///< CONFIG_RC2IBT
+ CONFIG_DONT_CARE, ///< CONFIG_DONT_CARE
+} Config_Type;
+
+// ====================
+// Configuration Macros
+// ====================
+#define TBLDRV_CONFIG_TO_OVERRIDE(DimmPerCH, Frequency, DimmVolt, DimmConfig) \
+ PSO_TBLDRV_CONFIG, 9, \
+ CONFIG_GENERAL, \
+ DimmPerCH, DimmVolt, \
+ ((Frequency) & 0x0FF), (((Frequency) >> 8)& 0x0FF), (((Frequency) >> 16)& 0x0FF), (((Frequency) >> 24)& 0x0FF), \
+ ((DimmConfig) & 0x0FF), (((DimmConfig) >> 8) & 0x0FF)
+
+#define TBLDRV_SPEEDLIMIT_CONFIG_TO_OVERRIDE(DimmPerCH, Dimms, NumOfSR, NumOfDR, NumOfQR, NumOfLRDimm) \
+ PSO_TBLDRV_CONFIG, 7, \
+ CONFIG_SPEEDLIMIT, \
+ DimmPerCH, Dimms, NumOfSR, NumOfDR, NumOfQR, NumOfLRDimm
+
+#define TBLDRV_RC2IBT_CONFIG_TO_OVERRIDE(DimmPerCH, Frequency, DimmVolt, DimmConfig, NumOfReg) \
+ PSO_TBLDRV_CONFIG, 10, \
+ CONFIG_RC2IBT, \
+ DimmPerCH, DimmVolt, \
+ ((Frequency) & 0x0FF), (((Frequency) >> 8)& 0x0FF), (((Frequency) >> 16)& 0x0FF), (((Frequency) >> 24)& 0x0FF), \
+ ((DimmConfig) & 0x0FF), (((DimmConfig) >> 8) & 0x0FF), \
+ NumOfReg
+
+//==================
+// Overriding Macros
+//==================
+#define TBLDRV_CONFIG_ENTRY_SPEEDLIMIT(SpeedLimit1_5, SpeedLimit1_35, SpeedLimit1_25) \
+ PSO_TBLDRV_SPEEDLIMIT, 6, \
+ (SpeedLimit1_5 & 0x0FF), ((SpeedLimit1_5 >> 8)& 0x0FF), \
+ (SpeedLimit1_35 & 0x0FF), ((SpeedLimit1_35 >> 8)& 0x0FF), \
+ (SpeedLimit1_25 & 0x0FF), ((SpeedLimit1_25 >> 8)& 0x0FF)
+
+#define TBLDRV_CONFIG_ENTRY_ODT_RTTNOM(TgtCS, RttNom) \
+ PSO_TBLDRV_ODT_RTTNOM, 2, \
+ TgtCS, RttNom
+
+#define TBLDRV_CONFIG_ENTRY_ODT_RTTWR(TgtCS, RttWr) \
+ PSO_TBLDRV_ODT_RTTWR, 2, \
+ TgtCS, RttWr
+
+#define TBLDRV_CONFIG_ENTRY_ODTPATTERN(RdODTCSHigh, RdODTCSLow, WrODTCSHigh, WrODTCSLow) \
+ PSO_TBLDRV_ODTPATTERN, 16, \
+ ((RdODTCSHigh) & 0x0FF), (((RdODTCSHigh) >> 8)& 0x0FF), (((RdODTCSHigh) >> 16)& 0x0FF), (((RdODTCSHigh) >> 24)& 0x0FF), \
+ ((RdODTCSLow) & 0x0FF), (((RdODTCSLow) >> 8)& 0x0FF), (((RdODTCSLow) >> 16)& 0x0FF), (((RdODTCSLow) >> 24)& 0x0FF), \
+ ((WrODTCSHigh) & 0x0FF), (((WrODTCSHigh) >> 8)& 0x0FF), (((WrODTCSHigh) >> 16)& 0x0FF), (((WrODTCSHigh) >> 24)& 0x0FF), \
+ ((WrODTCSLow) & 0x0FF), (((WrODTCSLow) >> 8)& 0x0FF), (((WrODTCSLow) >> 16)& 0x0FF), (((WrODTCSLow) >> 24)& 0x0FF)
+
+#define TBLDRV_CONFIG_ENTRY_ADDRTMG(AddrTmg) \
+ PSO_TBLDRV_ADDRTMG, 4, \
+ ((AddrTmg) & 0x0FF), (((AddrTmg) >> 8)& 0x0FF), (((AddrTmg) >> 16)& 0x0FF), (((AddrTmg) >> 24)& 0x0FF)
+
+#define TBLDRV_CONFIG_ENTRY_ODCCTRL(OdcCtrl) \
+ PSO_TBLDRV_ODCCTRL, 4, \
+ ((OdcCtrl) & 0x0FF), (((OdcCtrl) >> 8)& 0x0FF), (((OdcCtrl) >> 16)& 0x0FF), (((OdcCtrl) >> 24)& 0x0FF)
+
+#define TBLDRV_CONFIG_ENTRY_SLOWACCMODE(SlowAccMode) \
+ PSO_TBLDRV_SLOWACCMODE, 1, \
+ SlowAccMode
+
+#define TBLDRV_CONFIG_ENTRY_RC2_IBT(TgtDimm, IBT) \
+ PSO_TBLDRV_RC2_IBT, 2, \
+ TgtDimm, IBT
+
+#define TBLDRV_OVERRIDE_MR0_CL(RegValOfTcl, MR0CL13, MR0CL0) \
+ PSO_TBLDRV_CONFIG, 1, \
+ CONFIG_DONT_CARE, \
+ PSO_TBLDRV_MR0_CL, 3, \
+ RegValOfTcl, MR0CL13, MR0CL0
+
+#define TBLDRV_OVERRIDE_MR0_WR(RegValOfTwr, MR0WR) \
+ PSO_TBLDRV_CONFIG, 1, \
+ CONFIG_DONT_CARE, \
+ PSO_TBLDRV_MR0_WR, 2, \
+ RegValOfTwr, MR0WR
+
+#define TBLDRV_OVERRIDE_RC10_OPSPEED(Frequency, MR10OPSPEED) \
+ PSO_TBLDRV_CONFIG, 1, \
+ CONFIG_DONT_CARE, \
+ PSO_TBLDRV_RC10_OPSPEED, 5, \
+ ((Frequency) & 0x0FF), (((Frequency) >> 8)& 0x0FF), (((Frequency) >> 16)& 0x0FF), (((Frequency) >> 24)& 0x0FF), \
+ MR10OPSPEED
+
+#define TBLDRV_CONFIG_ENTRY_LRDMM_IBT(F0RC8, F1RC0, F1RC1, F1RC2) \
+ PSO_TBLDRV_LRDIMM_IBT, 4, \
+ F0RC8, F1RC0, F1RC1, F1RC2
+
+#define TBLDRV_CONFIG_ENTRY_2D_TRAINING(Training2dMode) \
+ PSO_TBLDRV_2D_TRAINING, 1, \
+ Training2dMode
+
+//============================
+// Macros for removing entries
+//============================
+#define INVALID_CONFIG_FLAG 0x8000
+
+#define TBLDRV_INVALID_CONFIG \
+ PSO_TBLDRV_INVALID_TYPE, 0
+
+/*----------------------------------------------------------------------------------------
+ * END OF TABLE DRIVEN OVERRIDE MACROS
+ *----------------------------------------------------------------------------------------
+ */
+
+#endif // _PLATFORM_MEMORY_CONFIGURATION_H_
diff --git a/src/vendorcode/amd/pi/00730F01/Include/Topology.h b/src/vendorcode/amd/pi/00730F01/Include/Topology.h
new file mode 100644
index 0000000..3c50e34
--- /dev/null
+++ b/src/vendorcode/amd/pi/00730F01/Include/Topology.h
@@ -0,0 +1,86 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Topology interface definitions.
+ *
+ * Contains AMD AGESA internal interface for topology related data which
+ * is consumed by code other than Topology Services init.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: Core
+ * @e \$Revision: 281178 $ @e \$Date: 2013-12-18 02:14:15 -0600 (Wed, 18 Dec 2013) $
+ */
+/*****************************************************************************
+ *
+ * Copyright (c) 2008 - 2014, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ***************************************************************************/
+
+#ifndef _TOPOLOGY_H_
+#define _TOPOLOGY_H_
+
+// Defines for limiting data structure maximum allocation and limit checking.
+#define MAX_NODES 1
+#define MAX_SOCKETS MAX_NODES
+#define MAX_DIES 1
+
+/**
+ * Socket and Module to Node Map Item.
+ * Provide the Node Id and core id range for each module in each processor.
+ */
+typedef struct {
+ UINT8 Node; ///< The module's Node id.
+ UINT8 LowCore; ///< The lowest processor core id for this module.
+ UINT8 HighCore; ///< The highest processor core id for this module.
+ UINT8 EnabledComputeUnits; ///< The value of Enabled for this processor module.
+ UINT8 DualCoreComputeUnits; ///< The value of DualCore for this processor module.
+ UINT8 TripleCoreComputeUnits;///< The value of TripleCore for this processor module.
+ UINT8 QuadCoreComputeUnits; ///< The value of QuadCore for this processor module.
+} SOCKET_DIE_TO_NODE_ITEM;
+
+/**
+ * Socket and Module to Node Map.
+ * This type is a pointer to the actual map, it can be used for a struct item or
+ * for typecasting a heap buffer pointer.
+ */
+typedef SOCKET_DIE_TO_NODE_ITEM (*SOCKET_DIE_TO_NODE_MAP)[MAX_SOCKETS][MAX_DIES];
+
+/**
+ * Node id to Socket Die Map Item.
+ */
+typedef struct {
+ UINT8 Socket; ///< socket of the processor containing the Node.
+ UINT8 Die; ///< the module in the processor which is Node.
+} NODE_TO_SOCKET_DIE_ITEM;
+
+/**
+ * Node id to Socket Die Map.
+ */
+typedef NODE_TO_SOCKET_DIE_ITEM (*NODE_TO_SOCKET_DIE_MAP)[MAX_NODES];
+
+#endif // _TOPOLOGY_H_
diff --git a/src/vendorcode/amd/pi/00730F01/Porting.h b/src/vendorcode/amd/pi/00730F01/Porting.h
new file mode 100644
index 0000000..eb2f049
--- /dev/null
+++ b/src/vendorcode/amd/pi/00730F01/Porting.h
@@ -0,0 +1,307 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Describes compiler dependencies - to support several compile time environments
+ *
+ * Contains compiler environment porting descriptions
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: Includes
+ * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 03:16:51 -0600 (Wed, 22 Dec 2010) $
+ */
+/*****************************************************************************
+ *
+ * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ***************************************************************************/
+
+#ifndef _PORTING_H_
+#define _PORTING_H_
+
+#if defined (_MSC_VER)
+ #include <intrin.h>
+ void _disable (void);
+ void _enable (void);
+ #pragma warning(disable: 4103 4001 4733)
+ #pragma intrinsic (_disable, _enable)
+ #pragma warning(push)
+ // -----------------------------------------------------------------------
+ // Define a code_seg MACRO
+ //
+ #define MAKE_AS_A_STRING(arg) #arg
+
+ #define CODE_GROUP(arg) __pragma (code_seg (MAKE_AS_A_STRING (.t##arg)))
+
+ #define RDATA_GROUP(arg) __pragma (const_seg (MAKE_AS_A_STRING (.d##arg)))
+ #define FUNC_ATTRIBUTE(arg) __declspec(arg)
+ //#include <intrin.h> // MS has built-in functions
+
+ #if _MSC_VER < 900
+ // -----------------------------------------------------------------------
+ // Assume MSVC 1.52C (16-bit)
+ //
+ // NOTE: When using MSVC 1.52C use the following command line:
+ //
+ // CL.EXE /G3 /AL /O1i /Fa <FILENAME.C>
+ //
+ // This will produce 32-bit code in USE16 segment that is optimized for code
+ // size.
+ typedef void VOID;
+
+ // Create the universal 32, 16, and 8-bit data types
+ typedef unsigned long UINTN;
+ typedef long INT32;
+ typedef unsigned long UINT32;
+ typedef int INT16;
+ typedef unsigned int UINT16;
+ typedef char INT8;
+ typedef unsigned char UINT8;
+ typedef char CHAR8;
+ typedef unsigned short CHAR16;
+
+ /// struct for 16-bit environment handling of 64-bit value
+ typedef struct _UINT64 {
+ IN OUT UINT32 lo; ///< lower 32-bits of 64-bit value
+ IN OUT UINT32 hi; ///< highest 32-bits of 64-bit value
+ } UINT64;
+
+ // Create the Boolean type
+ #define TRUE 1
+ #define FALSE 0
+ typedef unsigned char BOOLEAN;
+
+ #define CONST const
+ #define STATIC static
+ #define VOLATILE volatile
+ #define CALLCONV __pascal
+ #define ROMDATA __based( __segname( "_CODE" ) )
+ #define _16BYTE_ALIGN __declspec(align(16))
+ #define _8BYTE_ALIGN __declspec(align(8))
+ #define _4BYTE_ALIGN __declspec(align(4))
+ #define _2BYTE_ALIGN __declspec(align(2))
+ #define _1BYTE_ALIGN __declspec(align(1))
+
+ // Force tight packing of structures
+ // Note: Entire AGESA (Project / Solution) will be using pragma pack 1
+ #pragma warning( disable : 4103 ) // Disable '#pragma pack' in .h warning
+ #pragma pack(1)
+
+ // Disable WORD->BYTE automatic conversion warnings. Example:
+ // BYTE LocalByte;
+ // void MyFunc(BYTE val);
+ //
+ // MyFunc(LocalByte*2+1); // Warning, automatic conversion
+ //
+ // The problem is any time math is performed on a BYTE, it is converted to a
+ // WORD by MSVC 1.52c, and then when it is converted back to a BYTE, a warning
+ // is generated. Disable warning C4761
+ #pragma warning( disable : 4761 )
+
+ #else
+ // -----------------------------------------------------------------------
+ // Assume a 32-bit MSVC++
+ //
+ // Disable the following warnings:
+ // 4100 - 'identifier' : unreferenced formal parameter
+ // 4276 - 'function' : no prototype provided; assumed no parameters
+ // 4214 - non standard extension used : bit field types other than int
+ // 4001 - nonstandard extension 'single line comment' was used
+ // 4142 - benign redefinition of type for following declaration
+ // - typedef char INT8
+ #if defined (_M_IX86)
+ #pragma warning (disable: 4100 4276 4214 4001 4142 4305 4306)
+
+ #ifndef VOID
+ typedef void VOID;
+ #endif
+ // Create the universal 32, 16, and 8-bit data types
+ #ifndef UINTN
+ typedef unsigned __w64 UINTN;
+ #endif
+ typedef __int64 INT64;
+ typedef unsigned __int64 UINT64;
+ typedef int INT32;
+ typedef unsigned int UINT32;
+ typedef short INT16;
+ typedef unsigned short UINT16;
+ typedef char INT8;
+ typedef unsigned char UINT8;
+ typedef char CHAR8;
+ typedef unsigned short CHAR16;
+
+ // Create the Boolean type
+ #ifndef TRUE
+ #define TRUE 1
+ #endif
+ #ifndef FALSE
+ #define FALSE 0
+ #endif
+ typedef unsigned char BOOLEAN;
+
+ // Force tight packing of structures
+ // Note: Entire AGESA (Project / Solution) will be using pragma pack 1
+ #pragma pack(1)
+
+ #define CONST const
+ #define STATIC static
+ #define VOLATILE volatile
+ #define CALLCONV
+ #define ROMDATA
+ #define _16BYTE_ALIGN __declspec(align(64))
+ #define _8BYTE_ALIGN __declspec(align(8))
+ #define _4BYTE_ALIGN __declspec(align(4))
+ #define _2BYTE_ALIGN __declspec(align(2))
+ #define _1BYTE_ALIGN __declspec(align(1))
+ //Support for variadic macros was introduced in Visual C++ 2005.
+ #if _MSC_VER >= 1400
+ #define VA_ARGS_SUPPORTED
+ #endif
+ // 64 bit of compiler
+ #else
+ #pragma warning (disable: 4100 4276 4214 4001 4142 4305 4306 4366)
+
+ #ifndef VOID
+ typedef void VOID;
+ #endif
+ // Create the universal 32, 16, and 8-bit data types
+ #ifndef UINTN
+ typedef unsigned __int64 UINTN;
+ #endif
+ typedef __int64 INT64;
+ typedef unsigned __int64 UINT64;
+ typedef int INT32;
+ typedef unsigned int UINT32;
+ typedef short INT16;
+ typedef unsigned short UINT16;
+ typedef char INT8;
+ typedef unsigned char UINT8;
+ typedef char CHAR8;
+ typedef unsigned short CHAR16;
+
+ // Create the Boolean type
+ #ifndef TRUE
+ #define TRUE 1
+ #endif
+ #ifndef FALSE
+ #define FALSE 0
+ #endif
+ typedef unsigned char BOOLEAN;
+ #define _16BYTE_ALIGN __declspec(align(16))
+ #define _8BYTE_ALIGN __declspec(align(8))
+ #define _4BYTE_ALIGN __declspec(align(4))
+ #define _2BYTE_ALIGN __declspec(align(2))
+ #define _1BYTE_ALIGN __declspec(align(1))
+ // Force tight packing of structures
+ // Note: Entire AGESA (Project / Solution) will be using pragma pack 1
+ #pragma pack(1)
+
+ #define CONST const
+ #define STATIC static
+ #define VOLATILE volatile
+ #define CALLCONV
+ #define ROMDATA
+ #endif
+ #endif
+ // -----------------------------------------------------------------------
+ // End of MS compiler versions
+
+#elif defined __GNUC__
+
+ #define IN
+ #define OUT
+ #define STATIC static
+ #define VOLATILE volatile
+ #define TRUE 1
+ #define FALSE 0
+// #undef CONST
+ #define CONST const
+ #define ROMDATA
+ #define CALLCONV
+ #define _16BYTE_ALIGN __attribute__ ((aligned (16)))
+ #define _8BYTE_ALIGN __attribute__ ((aligned (8)))
+ #define _4BYTE_ALIGN __attribute__ ((aligned (4)))
+ #define _2BYTE_ALIGN __attribute__ ((aligned (2)))
+ #define _1BYTE_ALIGN __attribute__ ((aligned (1)))
+
+ typedef unsigned char BOOLEAN;
+ typedef signed char INT8;
+ typedef signed short INT16;
+ typedef signed long INT32;
+ typedef signed long long INT64;
+ typedef char CHAR8;
+ typedef unsigned char UINT8;
+ typedef unsigned short UINT16;
+ typedef unsigned long UINT32;
+ typedef unsigned long UINTN;
+ typedef unsigned long long UINT64;
+ typedef void VOID;
+ //typedef unsigned long size_t;
+ //typedef unsigned int uintptr_t;
+ //#include <intrin.h> // MingW-w64 library header
+
+#define CODE_GROUP(arg)
+#define RDATA_GROUP(arg)
+
+ //#include <intrin.h> // MingW-w64 library header
+ //#include <MyIntrinsics.h> // AGESA temp file for GCC until support is added to MinGW
+
+#pragma pack(1)
+
+#define FUNC_ATTRIBUTE(arg) __attribute__((arg))
+#define MAKE_AS_A_STRING(arg) #arg
+#include <stddef.h>
+#include "gcc-intrin.h"
+
+#include <assert.h>
+#include <config.h>
+#include <console/console.h>
+#include <console/loglevel.h>
+
+#ifndef NULL
+ #define NULL ((void *)0)
+#endif
+
+#else
+ // -----------------------------------------------------------------------
+ // Unknown or unsupported compiler
+ //
+ #error "Unknown compiler in use"
+#endif
+
+// -----------------------------------------------------------------------
+// Common definitions for all compilers
+//
+
+//Support forward reference construct
+#define AGESA_FORWARD_DECLARATION(x) typedef struct _##x x
+
+// The following are use in conformance to the UEFI style guide
+#define IN
+#define OUT
+
+#endif // _PORTING_H_
diff --git a/src/vendorcode/amd/pi/00730F01/Proc/CPU/Family/cpuFamRegisters.h b/src/vendorcode/amd/pi/00730F01/Proc/CPU/Family/cpuFamRegisters.h
new file mode 100644
index 0000000..c92c57a
--- /dev/null
+++ b/src/vendorcode/amd/pi/00730F01/Proc/CPU/Family/cpuFamRegisters.h
@@ -0,0 +1,144 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD CPU Register Table Related Functions
+ *
+ * Contains the definition of the CPU CPUID MSRs and PCI registers with BKDG recommended values
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: CPU
+ * @e \$Revision: 281178 $ @e \$Date: 2013-12-18 02:14:15 -0600 (Wed, 18 Dec 2013) $
+ *
+ */
+/*****************************************************************************
+ *
+ * Copyright (c) 2008 - 2014, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ***************************************************************************/
+
+#ifndef _CPU_FAM_REGISTERS_H_
+#define _CPU_FAM_REGISTERS_H_
+
+/*
+ *--------------------------------------------------------------
+ *
+ * M O D U L E S U S E D
+ *
+ *---------------------------------------------------------------
+ */
+
+/*
+ *--------------------------------------------------------------
+ *
+ * D E F I N I T I O N S / M A C R O S
+ *
+ *---------------------------------------------------------------
+ */
+
+// This define should be equal to the total number of families
+// in the cpuFamily enum.
+#define MAX_CPU_FAMILIES 64
+#define MAX_CPU_REVISIONS 63 // Max Cpu Revisions Per Family
+
+// CPU_LOGICAL_ID.Family equates
+// Family 15h equates
+#define AMD_FAMILY_15_TN 0x0000000000000200ull
+#define AMD_FAMILY_TN (AMD_FAMILY_15_TN)
+#define AMD_FAMILY_15_RL (AMD_FAMILY_15_TN)
+#define AMD_FAMILY_RL (AMD_FAMILY_15_TN)
+#define AMD_FAMILY_15_KV 0x0000000000000400ull
+#define AMD_FAMILY_KV (AMD_FAMILY_15_KV)
+#define AMD_FAMILY_15_CZ 0x0000000000000800ull
+#define AMD_FAMILY_CZ (AMD_FAMILY_15_CZ)
+#define AMD_FAMILY_15 (AMD_FAMILY_15_TN | AMD_FAMILY_15_KV | AMD_FAMILY_15_CZ)
+
+// Family 16h equates
+#define AMD_FAMILY_16_KB 0x0000000000010000ull
+#define AMD_FAMILY_KB AMD_FAMILY_16_KB
+#define AMD_FAMILY_16_ML 0x0000000000020000ull
+#define AMD_FAMILY_ML AMD_FAMILY_16_ML
+#define AMD_FAMILY_16 (AMD_FAMILY_KB | AMD_FAMILY_ML)
+
+// Family Unknown
+#define AMD_FAMILY_UNKNOWN 0x8000000000000000ull
+
+
+// Family 15h CPU_LOGICAL_ID.Revision equates
+// -------------------------------------
+
+ // Family 15h TN steppings
+#define AMD_F15_TN_A0 0x0000000000000100ull
+#define AMD_F15_TN_A1 0x0000000000000200ull
+#define AMD_F15_RL_A1 0x0000000000000400ull
+ // Family 15h KV steppings
+#define AMD_F15_KV_A0 0x0000000000100000ull
+#define AMD_F15_KV_A1 0x0000000000200000ull
+ // Family 15h CZ steppings
+#define AMD_F15_CZ_A0 0x0000000001000000ull
+ // Family 15h Unknown stepping
+#define AMD_F15_UNKNOWN 0x8000000000000000ull
+
+#define AMD_F15_RL_Ax (AMD_F15_RL_A1)
+#define AMD_F15_RL_ALL (AMD_F15_RL_Ax)
+
+#define AMD_F15_TN_Ax (AMD_F15_TN_A0 | AMD_F15_TN_A1)
+#define AMD_F15_TN_GT_A0 (AMD_F15_TN_ALL & ~AMD_F15_TN_A0)
+#define AMD_F15_TN_ONLY (AMD_F15_TN_Ax)
+#define AMD_F15_TN_ALL (AMD_F15_TN_Ax | AMD_F15_RL_ALL)
+
+#define AMD_F15_KV_Ax (AMD_F15_KV_A0 | AMD_F15_KV_A1)
+#define AMD_F15_KV_ALL (AMD_F15_KV_Ax)
+
+#define AMD_F15_CZ_Ax (AMD_F15_CZ_A0)
+#define AMD_F15_CZ_ALL (AMD_F15_CZ_Ax)
+
+#define AMD_F15_ALL (AMD_F15_TN_ALL | AMD_F15_KV_ALL | AMD_F15_CZ_ALL)
+
+// Family 16h CPU_LOGICAL_ID.Revision equates
+// -------------------------------------
+
+ // Family 16h KB steppings
+#define AMD_F16_KB_A0 0x0000000000000001ull
+#define AMD_F16_KB_A1 0x0000000000000002ull
+ // Family 16h ML steppings
+#define AMD_F16_ML_A0 0x0000000000000100ull
+#define AMD_F16_ML_A1 0x0000000000000200ull
+ // Family 16h Unknown stepping
+#define AMD_F16_UNKNOWN 0x8000000000000000ull
+
+#define AMD_F16_KB_Ax (AMD_F16_KB_A0 | AMD_F16_KB_A1)
+#define AMD_F16_KB_ALL (AMD_F16_KB_Ax)
+
+#define AMD_F16_ML_Ax (AMD_F16_ML_A0 | AMD_F16_ML_A1)
+#define AMD_F16_ML_ALL (AMD_F16_ML_Ax)
+#define AMD_F16_ML_GT_A0 (AMD_F16_ML_ALL & ~AMD_F16_ML_A0)
+
+#define AMD_F16_ALL (AMD_F16_KB_ALL | AMD_F16_ML_ALL)
+
+#endif // _CPU_FAM_REGISTERS_H_
+
diff --git a/src/vendorcode/amd/pi/00730F01/Proc/CPU/Feature/cpuCacheInit.h b/src/vendorcode/amd/pi/00730F01/Proc/CPU/Feature/cpuCacheInit.h
new file mode 100644
index 0000000..86b38b3
--- /dev/null
+++ b/src/vendorcode/amd/pi/00730F01/Proc/CPU/Feature/cpuCacheInit.h
@@ -0,0 +1,137 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD CPU Execution Cache Allocation functions.
+ *
+ * Contains code for doing Execution Cache Allocation for ROM space
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: CPU
+ * @e \$Revision: 281178 $ @e \$Date: 2013-12-18 02:14:15 -0600 (Wed, 18 Dec 2013) $
+ *
+ */
+/*****************************************************************************
+ *
+ * Copyright (c) 2008 - 2014, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ***************************************************************************/
+
+#ifndef _CPU_CACHE_INIT_H_
+#define _CPU_CACHE_INIT_H_
+
+/*----------------------------------------------------------------------------
+ * Mixed (DEFINITIONS AND MACROS / TYPEDEFS, STRUCTURES, ENUMS)
+ *
+ *----------------------------------------------------------------------------
+ */
+
+/*-----------------------------------------------------------------------------
+ * DEFINITIONS AND MACROS
+ *
+ *-----------------------------------------------------------------------------
+ */
+#define BSP_STACK_SIZE_64K 65536
+#define BSP_STACK_SIZE_32K 32768
+
+#define CORE0_STACK_SIZE 16384
+#define CORE1_STACK_SIZE 4096
+
+#define AMD_MTRR_FIX4K_BASE 0x268
+#define AMD_MTRR_VARIABLE_BASE6 0x20C
+#define AMD_MTRR_VARIABLE_BASE7 0x20E
+
+#define WP_IO 0x0505050505050505ull
+
+#define AGESA_CACHE_SIZE_REDUCED 1
+#define AGESA_CACHE_REGIONS_ACROSS_1MB 2
+#define AGESA_CACHE_REGIONS_ACROSS_4GB 3
+#define AGESA_REGION_NOT_ALIGNED_ON_BOUNDARY 4
+#define AGESA_CACHE_START_ADDRESS_LESS_D0000 5
+#define AGESA_THREE_CACHE_REGIONS_ABOVE_1MB 6
+#define AGESA_DEALLOCATE_CACHE_REGIONS 7
+
+/*----------------------------------------------------------------------------
+ * TYPEDEFS, STRUCTURES, ENUMS
+ *
+ *----------------------------------------------------------------------------
+ */
+/// Cache-As-Ram Executable region allocation modes
+typedef enum {
+ LimitedByL2Size, ///< Execution space must be allocated from L2
+ InfiniteExe, ///< Family can support unlimited Execution space
+ MaxCarExeMode ///< Used as limit or bounds check
+} CAR_EXE_MODE;
+
+/// Cache Information
+typedef struct {
+ IN UINT32 BspStackSize; ///< Stack size of BSP
+ IN UINT32 Core0StackSize; ///< Stack size of primary cores
+ IN UINT32 Core1StackSize; ///< Stack size of all non primary cores
+ IN UINT32 MemTrainingBufferSize; ///< Memory training buffer size
+ IN UINT32 SharedMemSize; ///< Shared memory size
+ IN UINT64 VariableMtrrMask; ///< Mask to apply before variable MTRR writes
+ IN UINT64 VariableMtrrHeapMask; ///< Mask to apply before variable MTRR writes for use in heap init.
+ IN UINT64 HeapBaseMask; ///< Mask used for the heap MTRR settings
+ IN CAR_EXE_MODE CarExeType; ///< Indicates which algorithm to use when allocating EXE space
+} CACHE_INFO;
+
+/// Merged memory region overlap type
+typedef enum {
+ EmptySet, ///< One of the regions is zero length
+ Disjoint, ///< The two regions do not touch
+ Adjacent, ///< one region is next to the other, no gap
+ CommonEnd, ///< regions overlap with a common end point
+ Extending, ///< the 2nd region is extending the size of the 1st
+ Contained, ///< the 2nd region is wholely contained inside the 1st
+ CommonStartContained, ///< the 2nd region is contained in the 1st with a common start
+ Identity, ///< the two regions are the same
+ CommonStartExtending, ///< the 2nd region has same start as 1st, but is larger size
+ NotCombinable ///< the combined regions do not follow the cache block rules
+} OVERLAP_TYPE;
+
+/// Result of merging two memory regions for cache coverage
+typedef struct {
+ IN OUT UINT32 MergedStartAddr; ///< Start address of the merged regions
+ IN OUT UINT32 MergedSize; ///< Size of the merged regions
+ OUT UINT32 OverlapAmount; ///< the size of the overlapping section
+ OUT OVERLAP_TYPE OverlapType; ///< indicates how the two regions overlap
+} MERGED_CACHE_REGION;
+
+/*----------------------------------------------------------------------------
+ * FUNCTIONS PROTOTYPE
+ *
+ *----------------------------------------------------------------------------
+ */
+AGESA_STATUS
+AllocateExecutionCache (
+ IN AMD_CONFIG_PARAMS *StdHeader,
+ IN EXECUTION_CACHE_REGION *AmdExeAddrMapPtr
+ );
+
+#endif // _CPU_CACHE_INIT_H_
+
diff --git a/src/vendorcode/amd/pi/00730F01/Proc/CPU/cpuApicUtilities.h b/src/vendorcode/amd/pi/00730F01/Proc/CPU/cpuApicUtilities.h
new file mode 100644
index 0000000..536391b
--- /dev/null
+++ b/src/vendorcode/amd/pi/00730F01/Proc/CPU/cpuApicUtilities.h
@@ -0,0 +1,302 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD CPU APIC related utility functions and structures
+ *
+ * Contains code that provides mechanism to invoke and control APIC communication.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: CPU
+ * @e \$Revision: 281178 $ @e \$Date: 2013-12-18 02:14:15 -0600 (Wed, 18 Dec 2013) $
+ *
+ */
+/*****************************************************************************
+ *
+ * Copyright (c) 2008 - 2014, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ***************************************************************************/
+
+#ifndef _CPU_APIC_UTILITIES_H_
+#define _CPU_APIC_UTILITIES_H_
+
+
+/*---------------------------------------------------------------------------------------
+ * M I X E D (Definitions And Macros / Typedefs, Structures, Enums)
+ *---------------------------------------------------------------------------------------
+ */
+
+
+/*---------------------------------------------------------------------------------------
+ * D E F I N I T I O N S A N D M A C R O S
+ *---------------------------------------------------------------------------------------
+ */
+#define APIC_CTRL_DWORD 0xF
+#define APIC_CTRL_REG (APIC_CTRL_DWORD << 4)
+#define APIC_CTRL_MASK 0xFF
+#define APIC_CTRL_SHIFT 0
+
+#define APIC_DATA_DWORD 0x38
+#define APIC_DATA_REG (APIC_DATA_DWORD << 4)
+
+#define APIC_REMOTE_READ_REG 0xC0
+#define APIC_CMD_LO_REG 0x300
+#define APIC_CMD_HI_REG 0x310
+
+// APIC_CMD_LO_REG bits
+#define CMD_REG_DELIVERY_STATUS 0x1000
+#define CMD_REG_TO_READ 0x300
+#define CMD_REG_REMOTE_RD_STS_MSK 0x30000ul
+#define CMD_REG_REMOTE_DELIVERY_PENDING 0x10000ul
+#define CMD_REG_REMOTE_DELIVERY_DONE 0x20000ul
+#define CMD_REG_TO_NMI 0x400
+
+// ExeFlags bits
+#define WAIT_FOR_CORE 0x00000001ul
+#define TASK_HAS_OUTPUT 0x00000002ul
+#define RETURN_PARAMS 0x00000004ul
+#define END_AT_HLT 0x00000008ul
+#define PASS_EARLY_PARAMS 0x00000010ul
+
+// Control Byte Values
+// bit 7 indicates the type of message
+// 1 - control message
+// 0 - launch + APIC ID = message to go
+//
+#define CORE_UNAVAILABLE 0xFF
+#define CORE_IDLE 0xFE
+#define CORE_IDLE_HLT 0xFD
+#define CORE_ACTIVE 0xFC
+#define CORE_NEEDS_PTR 0xFB
+#define CORE_NEEDS_DATA_SIZE 0xFA
+#define CORE_STS_DATA_READY_1 0xF9
+#define CORE_STS_DATA_READY_0 0xF8
+#define CORE_DATA_FLAGS_READY 0xF7
+#define CORE_DATA_FLAGS_ACKNOWLEDGE 0xF6
+#define CORE_DATA_PTR_READY 0xF5
+
+// Macro used to determine the number of dwords to transmit to the AP as input
+#define SIZE_IN_DWORDS(sInput) ((UINT32) (((sizeof (sInput)) + 3) >> 2))
+
+// IDT table
+#define IDT_DESC_PRESENT 0x80
+
+#define IDT_DESC_TYPE_LDT 0x02
+#define IDT_DESC_TYPE_CALL16 0x04
+#define IDT_DESC_TYPE_TASK 0x05
+#define IDT_DESC_TYPE_INT16 0x06
+#define IDT_DESC_TYPE_TRAP16 0x07
+#define IDT_DESC_TYPE_CALL32 0x0C
+#define IDT_DESC_TYPE_INT32 0x0E
+#define IDT_DESC_TYPE_TRAP32 0x0F
+/*---------------------------------------------------------------------------------------
+ * T Y P E D E F S, S T R U C T U R E S, E N U M S
+ *---------------------------------------------------------------------------------------
+ */
+typedef VOID (*PF_AP_TASK) (AMD_CONFIG_PARAMS *StdHeader);
+typedef VOID (*PF_AP_TASK_I) (VOID *, AMD_CONFIG_PARAMS *StdHeader);
+typedef VOID (*PF_AP_TASK_C) (AMD_CONFIG_PARAMS *StdHeader, AMD_CPU_EARLY_PARAMS *);
+typedef VOID (*PF_AP_TASK_IC) (VOID *, AMD_CONFIG_PARAMS *StdHeader, AMD_CPU_EARLY_PARAMS *);
+typedef UINT32 (*PF_AP_TASK_O) (AMD_CONFIG_PARAMS *StdHeader);
+typedef UINT32 (*PF_AP_TASK_IO) (VOID *, AMD_CONFIG_PARAMS *StdHeader);
+typedef UINT32 (*PF_AP_TASK_OC) (AMD_CONFIG_PARAMS *StdHeader, AMD_CPU_EARLY_PARAMS *);
+typedef UINT32 (*PF_AP_TASK_IOC) (VOID *, AMD_CONFIG_PARAMS *StdHeader, AMD_CPU_EARLY_PARAMS *);
+
+/// Function pointer union representing the eight different
+/// types of functions that an AP can be asked to perform.
+typedef union {
+ PF_AP_TASK PfApTask; ///< AMD_CONFIG_PARAMS * input with no output
+ PF_AP_TASK_I PfApTaskI; ///< VOID * + AMD_CONFIG_PARAMS * input with no output
+ PF_AP_TASK_C PfApTaskC; ///< AMD_CONFIG_PARAMS * + AMD_CPU_EARLY_PARAMS * input with no output
+ PF_AP_TASK_IC PfApTaskIC; ///< VOID * + AMD_CONFIG_PARAMS * + AMD_CPU_EARLY_PARAMS * input with no output
+ PF_AP_TASK_O PfApTaskO; ///< AMD_CONFIG_PARAMS * input with UINT32 output
+ PF_AP_TASK_IO PfApTaskIO; ///< VOID * + AMD_CONFIG_PARAMS * input with UINT32 output
+ PF_AP_TASK_OC PfApTaskOC; ///< AMD_CONFIG_PARAMS * + AMD_CPU_EARLY_PARAMS * input with UINT32 output
+ PF_AP_TASK_IOC PfApTaskIOC; ///< VOID * + AMD_CONFIG_PARAMS * + AMD_CPU_EARLY_PARAMS * input with UINT32 output
+} AP_FUNCTION_PTR;
+
+/// Input structure for ApUtilTransmitBuffer and ApUtilReceiveBuffer
+/// containing information about the data transfer from one core
+/// to another.
+typedef struct {
+ IN OUT UINT16 DataSizeInDwords; ///< Size of the data to be transferred rounded up to the nearest dword
+ IN OUT VOID *DataPtr; ///< Pointer to the data
+ IN UINT32 DataTransferFlags; ///< Flags dictating certain aspects of the data transfer
+} AP_DATA_TRANSFER;
+
+/// Input structure for ApUtilRunCodeOnSocketCore.
+typedef struct _AP_TASK {
+ AP_FUNCTION_PTR FuncAddress; ///< Pointer to the function that the AP will run
+ AP_DATA_TRANSFER DataTransfer; ///< Data transfer struct for optionally passing data that the AP should use as input to the function
+ UINT32 ExeFlags; ///< Flags dictating certain aspects of the AP tasking sequence
+} AP_TASK;
+
+/// Input structure for ApUtilWaitForCoreStatus.
+typedef struct {
+ IN UINT8 *Status; ///< Pointer to the 1st element of an array of values to wait for
+ IN UINT8 NumberOfElements; ///< Number of elements in the array
+ IN UINT32 RetryCount; ///< Number of remote read cycles to complete before quitting
+ IN UINT32 WaitForStatusFlags; ///< Flags dictating certain aspects of ApUtilWaitForCoreStatus
+} AP_WAIT_FOR_STATUS;
+
+/// Interrupt Descriptor Table entry
+typedef struct {
+ UINT16 OffsetLo; ///< Lower 16 bits of the interrupt handler routine's offset
+ UINT16 Selector; ///< Interrupt handler routine's selector
+ UINT8 Rsvd; ///< Reserved
+ UINT8 Flags; ///< Interrupt flags
+ UINT16 OffsetHi; ///< Upper 16 bits of the interrupt handler routine's offset
+ UINT32 Offset64; ///< High order 32 bits of the handler's offset needed when in 64 bit mode
+ UINT32 Rsvd64; ///< Reserved
+} IDT_DESCRIPTOR;
+
+/// Structure needed to load the IDTR using the lidt instruction
+typedef struct {
+ UINT16 Limit; ///< Interrupt Descriptor Table size
+ UINT64 Base; ///< Interrupt Descriptor Table base address
+} IDT_BASE_LIMIT;
+
+#define WAIT_STATUS_EQUALITY 0x00000001ul
+#define WAIT_INFINITELY 0
+
+// Data Transfer Flags
+#define DATA_IN_MEMORY 0x00000001ul
+
+
+/*---------------------------------------------------------------------------------------
+ * F U N C T I O N P R O T O T Y P E
+ *---------------------------------------------------------------------------------------
+ */
+// These are P U B L I C functions, used by AGESA
+UINT8
+ApUtilReadRemoteControlByte (
+ IN UINT32 TargetApicId,
+ IN AMD_CONFIG_PARAMS *StdHeader
+ );
+
+VOID
+ApUtilWriteControlByte (
+ IN UINT8 Value,
+ IN AMD_CONFIG_PARAMS *StdHeader
+ );
+
+UINT32
+ApUtilReadRemoteDataDword (
+ IN UINT32 TargetApicId,
+ IN AMD_CONFIG_PARAMS *StdHeader
+ );
+
+VOID
+ApUtilWriteDataDword (
+ IN UINT32 Value,
+ IN AMD_CONFIG_PARAMS *StdHeader
+ );
+
+UINT32
+ApUtilRunCodeOnSocketCore (
+ IN UINT8 Socket,
+ IN UINT8 Core,
+ IN AP_TASK *TaskPtr,
+ IN AMD_CONFIG_PARAMS *StdHeader
+ );
+
+UINT8
+ApUtilWaitForCoreStatus (
+ IN UINT32 TargetApicId,
+ IN AP_WAIT_FOR_STATUS *WaitParamsPtr,
+ IN AMD_CONFIG_PARAMS *StdHeader
+ );
+
+VOID
+ApEntry (
+ IN AMD_CONFIG_PARAMS *StdHeader,
+ IN AMD_CPU_EARLY_PARAMS *CpuEarlyParams
+ );
+
+UINT32
+ApUtilTaskOnExecutingCore (
+ IN AP_TASK *TaskPtr,
+ IN AMD_CONFIG_PARAMS *StdHeader,
+ IN VOID *ConfigParams
+ );
+
+VOID
+ApUtilTransmitBuffer (
+ IN UINT8 Socket,
+ IN UINT8 Core,
+ IN AP_DATA_TRANSFER *BufferInfo,
+ IN AMD_CONFIG_PARAMS *StdHeader
+ );
+
+AGESA_STATUS
+ApUtilReceiveBuffer (
+ IN UINT8 Socket,
+ IN UINT8 Core,
+ IN OUT AP_DATA_TRANSFER *BufferInfo,
+ IN AMD_CONFIG_PARAMS *StdHeader
+ );
+
+VOID
+GetLocalApicIdForCore (
+ IN UINT32 TargetSocket,
+ IN UINT32 TargetCore,
+ OUT UINT32 *LocalApicId,
+ IN AMD_CONFIG_PARAMS *StdHeader
+ );
+
+VOID
+ApUtilRunCodeOnAllLocalCoresAtEarly (
+ IN AP_TASK *TaskPtr,
+ IN AMD_CONFIG_PARAMS *StdHeader,
+ IN AMD_CPU_EARLY_PARAMS *CpuEarlyParamsPtr
+ );
+
+VOID
+RelinquishControlOfAllAPs (
+ IN AMD_CONFIG_PARAMS *StdHeader
+ );
+
+VOID
+GetCsSelector (
+ IN UINT16 *Selector,
+ IN AMD_CONFIG_PARAMS *StdHeader
+ );
+
+VOID
+SetIdtr (
+ IN IDT_BASE_LIMIT *IdtInfo,
+ IN AMD_CONFIG_PARAMS *StdHeader
+ );
+
+VOID
+GetIdtr (
+ IN IDT_BASE_LIMIT *IdtInfo,
+ IN AMD_CONFIG_PARAMS *StdHeader
+ );
+
+#endif /* _CPU_APIC_UTILITIES_H_ */
+
diff --git a/src/vendorcode/amd/pi/00730F01/Proc/CPU/cpuEarlyInit.h b/src/vendorcode/amd/pi/00730F01/Proc/CPU/cpuEarlyInit.h
new file mode 100644
index 0000000..f0e49b7
--- /dev/null
+++ b/src/vendorcode/amd/pi/00730F01/Proc/CPU/cpuEarlyInit.h
@@ -0,0 +1,289 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD CPU Reset API, and related functions and structures.
+ *
+ * Contains code that initialized the CPU after early reset.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: CPU
+ * @e \$Revision: 281178 $ @e \$Date: 2013-12-18 02:14:15 -0600 (Wed, 18 Dec 2013) $
+ *
+ */
+/*****************************************************************************
+ *
+ * Copyright (c) 2008 - 2014, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ***************************************************************************/
+
+#ifndef _CPU_EARLY_INIT_H_
+#define _CPU_EARLY_INIT_H_
+
+
+/*---------------------------------------------------------------------------------------
+ * M I X E D (Definitions And Macros / Typedefs, Structures, Enums)
+ *---------------------------------------------------------------------------------------
+ */
+AGESA_FORWARD_DECLARATION (CPU_CORE_LEVELING_FAMILY_SERVICES);
+
+/*---------------------------------------------------------------------------------------
+ * D E F I N I T I O N S A N D M A C R O S
+ *---------------------------------------------------------------------------------------
+ */
+//----------------------------------------------------------------------------
+// CPU BRAND ID TYPEDEFS, STRUCTURES, ENUMS
+//
+//----------------------------------------------------------------------------
+#define CPU_BRAND_ID_LENGTH 48 // Total number of characters supported
+#define LOW_NODE_DEVICEID 24
+#define NB_CAPABILITIES 0xE8 //Function 3 Registers
+//----------------------------------------------------------------------------
+// CPU MICROCODE PATCH TYPEDEFS, STRUCTURES, ENUMS
+//
+//----------------------------------------------------------------------------
+/* All lengths are in bytes */
+#define MICROCODE_TRIADE_SIZE 28
+#define MICROCODE_HEADER_LENGTH 64
+
+/**
+ * @page ucodeflag Microcode Patches Signature Guide
+ *
+ * We mark patches in the ROM with a signature so that they can be easily found
+ *
+ * @anchor Microcode Patch Signature
+ * @li @e Microcode Patch Signature @n
+ * Microcode patches are marked by adding a signature before patches in the ROM image to
+ * help identify where they are located.
+ * There're two kind of signatures. One is '$UCODE2K', it indicates there's a following patch with 2K size.
+ * The other is '$UCODE4K', it indicates there's a following patch with 4K size.
+ * If you want to know the patch level / equivalent ID, please consult the BKDG for patch header format.
+ *
+ *
+ */
+/// Microcode patch flag for replacement
+typedef struct {
+ IN UINT8 MicrocodePatchesFlag[8]; ///< a flag followed by microcode
+} MICROCODE_PATCHES_FLAG;
+
+#define UCODE_2K_FLAG(x) STATIC CONST MICROCODE_PATCHES_FLAG ROMDATA UcodeFlag##x = {{'$', 'U', 'C', 'O', 'D', 'E', '2', 'K'}};
+#define UCODE_4K_FLAG(x) STATIC CONST MICROCODE_PATCHES_FLAG ROMDATA UcodeFlag##x = {{'$', 'U', 'C', 'O', 'D', 'E', '4', 'K'}};
+#define UCODE_VS_FLAG(x) STATIC CONST MICROCODE_PATCHES_FLAG ROMDATA UcodeFlag##x = {{'$', 'U', 'C', 'O', 'D', 'E', 'V', 'S'}};
+
+/* Offsets in UCODE PATCH Header */
+/* Note: Header is 64 bytes */
+#define DATE_CODE_OFFSET 0 // 4 bytes
+#define PATCH_ID 4 // 4 bytes
+#define MICROCODE_PATH_DATA_ID 8 // 2 bytes
+#define MICROCODE_PATCH_DATA_LENGTH 10 // 1 byte
+#define MICROCODE_PATCH_DATA_CHECKSUM 12 // 4 bytes
+#define CHIPSET_1_DEVICE_ID 16 // 4 bytes
+#define CHIPSET_2_DEVICE_ID 20 // 4 bytes
+#define PROCESSOR_REV_ID 24 // 2 bytes
+#define CHIPSET_1_REV_ID 26 // 1 byte
+#define CHIPSET_2_REV_ID 27 // 1 byte
+
+#define MICROCODE_PATCH_2K_SIZE 2048
+#define MICROCODE_PATCH_4K_SIZE 4096
+/*---------------------------------------------------------------------------------------
+ * T Y P E D E F S, S T R U C T U R E S, E N U M S
+ *---------------------------------------------------------------------------------------
+ */
+//----------------------------------------------------------------------------
+// CPU BRAND ID TYPEDEFS, STRUCTURES, ENUMS
+//
+//----------------------------------------------------------------------------
+/// A structure representing BrandId[15:0] from
+/// CPUID Fn8000_0001_EBX
+typedef struct {
+ UINT8 String1:4; ///< An index to a string value used to create the name string
+ UINT8 String2:4; ///< An index to a string value used to create the name string
+ UINT8 Page:1; ///< An index to the appropriate page for the String1, String2, and Model values
+ UINT8 Model:7; ///< A field used to create the model number in the name string
+ UINT8 Socket:4; ///< Specifies the package type
+ UINT8 Cores:4; ///< Identifies how many physical cores are present
+} AMD_CPU_BRAND_DATA;
+
+/// A structure containing string1 and string2 values
+/// as well as information pertaining to their usage
+typedef struct {
+ IN UINT8 Cores; ///< Appropriate number of physical cores
+ IN UINT8 Page; ///< This string's page number
+ IN UINT8 Index; ///< String index
+ IN UINT8 Socket; ///< Package type information
+ IN CONST CHAR8 *Stringstart; ///< The literal string
+ IN UINT8 Stringlength; ///< Number of characters in the string
+} AMD_CPU_BRAND;
+
+/// An entire CPU brand table.
+typedef struct {
+ UINT8 NumberOfEntries; ///< The number of entries in the table.
+ CONST AMD_CPU_BRAND *Table; ///< The table entries.
+} CPU_BRAND_TABLE;
+
+//----------------------------------------------------------------------------
+// CPU MICROCODE PATCH TYPEDEFS, STRUCTURES, ENUMS
+//
+//----------------------------------------------------------------------------
+/// Microcode patch field definitions
+typedef struct {
+ UINT32 DateCode; ///< Date of patch creation
+ UINT32 PatchID; ///< Patch level
+ UINT16 MicrocodePatchDataID; ///< Internal use only
+ UINT8 MicrocodePatchDataLength; ///< Internal use only
+ UINT8 InitializationFlag; ///< Internal use only
+ UINT32 MicrocodePatchDataChecksum; ///< Doubleword sum of data block
+ UINT32 Chipset1DeviceID; ///< Device ID of 1st Chipset device to match
+ UINT32 Chipset2DeviceID; ///< Device ID of 2nd Chipset device to match
+ UINT16 ProcessorRevisionID; ///< Equivalent ID
+ UINT8 Chipset1RevisionID; ///< Revision level of 1st Chipset device to match
+ UINT8 Chipset2RevisionID; ///< Revision level of 2nd Chipset device to match
+ UINT8 BiosApiRevision; ///< BIOS INT 15 API revision required
+ UINT8 Reserved1[3]; ///< Reserved
+ UINT32 MatchRegister0; ///< Internal use only
+ UINT32 MatchRegister1; ///< Internal use only
+ UINT32 MatchRegister2; ///< Internal use only
+ UINT32 MatchRegister3; ///< Internal use only
+ UINT32 MatchRegister4; ///< Internal use only
+ UINT32 MatchRegister5; ///< Internal use only
+ UINT32 MatchRegister6; ///< Internal use only
+ UINT32 MatchRegister7; ///< Internal use only
+ UINT8 PatchDataBlock[896]; ///< Raw patch data
+ UINT8 Reserved2[896]; ///< Reserved
+ UINT8 X86CodePresent; ///< Boolean to determine if executable code exists
+ UINT8 X86CodeEntry[191]; ///< Code to execute if X86CodePresent != 0
+} MICROCODE_PATCH;
+
+/// Two kilobyte array containing the raw
+/// microcode patch binary data
+typedef struct {
+ IN UINT8 MicrocodePatches[MICROCODE_PATCH_2K_SIZE]; ///< 2k UINT8 elements
+} MICROCODE_PATCHES;
+
+/// Four kilobyte array containing the raw
+/// microcode patch binary data
+typedef struct {
+ IN UINT8 MicrocodePatches[MICROCODE_PATCH_4K_SIZE]; ///< 4k UINT8 elements
+} MICROCODE_PATCHES_4K;
+
+/**
+ * Set down core register
+ *
+ * @CpuServiceInstances
+ *
+ * @param[in] FamilySpecificServices The current Family Specific Services.
+ * @param[in] Socket Socket ID.
+ * @param[in] Module Module ID in socket.
+ * @param[in] LeveledCores Number of core.
+ * @param[in] CoreLevelMode Core level mode.
+ * @param[in] StdHeader Header for library and services.
+ *
+ * @retval TRUE Down Core register is updated.
+ * @retval FALSE Down Core register is not updated.
+ */
+typedef BOOLEAN (F_CPU_SET_DOWN_CORE_REGISTER) (
+ IN CPU_CORE_LEVELING_FAMILY_SERVICES *FamilySpecificServices,
+ IN UINT32 *Socket,
+ IN UINT32 *Module,
+ IN UINT32 *LeveledCores,
+ IN CORE_LEVELING_TYPE CoreLevelMode,
+ IN AMD_CONFIG_PARAMS *StdHeader
+ );
+
+/// Reference to a method
+typedef F_CPU_SET_DOWN_CORE_REGISTER *PF_CPU_SET_DOWN_CORE_REGISTER;
+
+/**
+ * Provide the interface to the Core Leveling Family Specific Services.
+ *
+ * Use the methods or data in this struct to adapt the feature code to a specific cpu family or model (or stepping!).
+ * Each supported Family must provide an implementation for all methods in this interface, even if the
+ * implementation is a CommonReturn().
+ */
+struct _CPU_CORE_LEVELING_FAMILY_SERVICES { // See Forward Declaration above
+ UINT16 Revision; ///< Interface version
+ // Public Methods.
+ PF_CPU_SET_DOWN_CORE_REGISTER SetDownCoreRegister; ///< Method: Set down core register.
+};
+
+/*---------------------------------------------------------------------------------------
+ * F U N C T I O N P R O T O T Y P E
+ *---------------------------------------------------------------------------------------
+ */
+
+// These are P U B L I C functions, used by IBVs
+AGESA_STATUS
+AmdCpuEarly (
+ IN AMD_CONFIG_PARAMS *StdHeader,
+ IN PLATFORM_CONFIGURATION *PlatformConfig
+ );
+
+// These are P U B L I C functions, used by AGESA
+AGESA_STATUS
+PmInitializationAtEarly (
+ IN AMD_CPU_EARLY_PARAMS *CpuEarlyParams,
+ IN AMD_CONFIG_PARAMS *StdHeader
+ );
+
+BOOLEAN
+LoadMicrocodePatch (
+ IN OUT AMD_CONFIG_PARAMS *StdHeader
+ );
+
+BOOLEAN
+GetPatchEquivalentId (
+ IN OUT UINT16 *ProcessorEquivalentId,
+ IN OUT AMD_CONFIG_PARAMS *StdHeader
+ );
+
+BOOLEAN
+ValidateMicrocode (
+ IN MICROCODE_PATCH *MicrocodePatchPtr,
+ IN UINT16 ProcessorEquivalentId,
+ IN OUT AMD_CONFIG_PARAMS *StdHeader
+ );
+
+VOID
+GetMicrocodeVersion (
+ OUT UINT32 *pMicrocodeVersion,
+ IN OUT AMD_CONFIG_PARAMS *StdHeader
+ );
+
+VOID
+AmdCpuEarlyInitializer (
+ IN AMD_CONFIG_PARAMS *StdHeader,
+ IN PLATFORM_CONFIGURATION *PlatformConfig,
+ IN OUT AMD_CPU_EARLY_PARAMS *CpuEarlyParamsPtr
+ );
+
+VOID
+McaInitialization (
+ IN AMD_CONFIG_PARAMS *StdHeader
+ );
+
+#endif // _CPU_EARLY_INIT_H_
+
diff --git a/src/vendorcode/amd/pi/00730F01/Proc/CPU/cpuLateInit.h b/src/vendorcode/amd/pi/00730F01/Proc/CPU/cpuLateInit.h
new file mode 100644
index 0000000..da698d0
--- /dev/null
+++ b/src/vendorcode/amd/pi/00730F01/Proc/CPU/cpuLateInit.h
@@ -0,0 +1,1140 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD CPU Late Init API functions Prototypes.
+ *
+ * Contains code for doing any late CPU initialization
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: CPU
+ * @e \$Revision: 281178 $ @e \$Date: 2013-12-18 02:14:15 -0600 (Wed, 18 Dec 2013) $
+ *
+ */
+/*****************************************************************************
+ *
+ * Copyright (c) 2008 - 2014, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ***************************************************************************/
+
+#ifndef _CPU_LATE_INIT_H_
+#define _CPU_LATE_INIT_H_
+
+#include "Filecode.h"
+
+// Forward declaration needed for multi-structure mutual references.
+AGESA_FORWARD_DECLARATION (PROC_FAMILY_TABLE);
+/*----------------------------------------------------------------------------------------
+ * M I X E D (Definitions And Macros / Typedefs, Structures, Enums)
+ *----------------------------------------------------------------------------------------
+ */
+
+/*----------------------------------------------------------------------------------------
+ * D E F I N I T I O N S A N D M A C R O S
+ *----------------------------------------------------------------------------------------
+ */
+
+//----------------------------------------------------------------------------
+// DMI DEFINITIONS AND MACROS
+//
+//----------------------------------------------------------------------------
+#define AP_LATE_TASK_GET_TYPE4_TYPE7 (PROC_CPU_FEATURE_CPUDMI_FILECODE)
+// SMBIOS constant definition
+#define CENTRAL_PROCESSOR 0x03
+#define EXTERNAL_CLOCK_DFLT 200
+#define EXTERNAL_CLOCK_100MHZ 100
+#define P_FAMILY_UNKNOWN 0x02
+#define P_ENGINEERING_SAMPLE 0x00
+#define P_CHARACTERISTICS 0x4
+#define CACHE_CFG_L1 0x180
+#define CACHE_CFG_L2 0x181
+#define CACHE_CFG_L3 0x182
+#define SRAM_TYPE 0x10
+#define ERR_CORRECT_TYPE 0x06
+#define CACHE_TYPE 0x05
+#define DMI_ASSOCIATIVE_OTHER 0x01
+#define DMI_ASSOCIATIVE_UNKNOWN 0x02
+#define DMI_ASSOCIATIVE_DIRECT_MAPPED 0x03
+#define DMI_ASSOCIATIVE_2_WAY 0x04
+#define DMI_ASSOCIATIVE_4_WAY 0x05
+#define DMI_ASSOCIATIVE_FULLY 0x06
+#define DMI_ASSOCIATIVE_8_WAY 0x07
+#define DMI_ASSOCIATIVE_16_WAY 0x08
+#define DMI_ASSOCIATIVE_12_WAY 0x09
+#define DMI_ASSOCIATIVE_24_WAY 0x0A
+#define DMI_ASSOCIATIVE_32_WAY 0x0B
+#define DMI_ASSOCIATIVE_48_WAY 0x0C
+#define DMI_ASSOCIATIVE_64_WAY 0x0D
+#define DMI_ASSOCIATIVE_20_WAY 0x0E
+#define SOCKET_POPULATED 0x40
+#define CPU_STATUS_UNKNOWN 0x00
+#define CPU_STATUS_ENABLED 0x01
+
+// Processor Upgrade Definition
+#define P_UPGRADE_UNKNOWN 0x02
+#define P_UPGRADE_NONE 0x06
+#define P_UPGRADE_S1GX 0x16
+#define P_UPGRADE_AM2 0x17
+#define P_UPGRADE_F1207 0x18
+#define P_UPGRADE_G34 0x1A
+#define P_UPGRADE_AM3 0x1B
+#define P_UPGRADE_C32 0x1C
+#define P_UPGRADE_FS1 0x27
+#define P_UPGRADE_FM1 0x29
+#define P_UPGRADE_FM2 0x2A
+
+//----------------------------------------------------------------------------
+// SRAT DEFINITIONS AND MACROS
+//
+//----------------------------------------------------------------------------
+#define NorthbridgeCapabilities 0xE8
+#define DRAMBase0 0x40
+#define MMIOBase0 0x80
+#define TOP_MEM 0xC001001Aul
+#define LOW_NODE_DEVICEID 24
+#define LOW_APICID 0
+
+
+// Miscellaneous AMD related values
+#define MAX_NUMBER_NODES 8
+
+// Flags
+#define ENABLED 1 // Bit 0
+#define DISABLED 0 // Bit 0
+#define HOTPLUGGABLE 2 // Bit 1
+
+// Affinity Entry Structures
+#define AE_APIC 0
+#define AE_MEMORY 1
+
+
+// Memory Types
+#define TYPE_MEMORY 1
+#define TYPE_RESERVED 2
+#define TYPE_ACPI 3
+#define TYPE_NVS 4
+
+//----------------------------------------------------------------------------
+// SLIT DEFINITIONS AND MACROS
+//
+//----------------------------------------------------------------------------
+#define AMD_ACPI_SLIT_SOCKET_NUM_LENGTH 8
+
+//----------------------------------------------------------------------------
+// CDIT DEFINITIONS AND MACROS
+//
+//----------------------------------------------------------------------------
+#define AMD_ACPI_CDIT_NUM_DOMAINS_LENGTH 4 // Num domains is a 4-bytes unsigned integer
+
+
+//----------------------------------------------------------------------------
+// P-STATE DEFINITIONS AND MACROS
+//
+//----------------------------------------------------------------------------
+//-------------------------------------
+// ERROR Codes
+//-------------------------------------
+#define NO_ERROR 0x0
+#define USER_DISABLE_ERROR 0x01 // User disabled SSDT generation
+#define CORES_MISSMATCH_PSS_ERROR 0x02 // No PSS match
+#define PNOW_SUPPORT_ERROR 0x04 // One of the Cores do not support PNOW!
+#define PWR_FREQ_MATCH_ERROR 0x08 // FREQ and PWR mismatch
+#define NO_PSS_SIZE_ERROR 0x10 // Error in PSS Size
+#define INVALID_PSTATE_ERROR 0x20 // Invalid Max or only 1 P-State available
+#define NO_PSS_ENTRY 0x0FFFFul
+#define INVALID_FREQ 0x0FFFFFFFFul
+
+//-------------------------
+// Default definitions
+// AMD BKDG default values
+//-------------------------
+#define DEFAULT_ISOCH_RELIEF_TIME IRT_80uS
+#define DEFAULT_RAMP_VOLTAGE_OFFSET RVO_50mV
+#define DEFAULT_MAX_VOLTAGE_STEP MVS_25mV
+#define DEFAULT_PERF_PRESENT_CAP 0 // default for Desktop
+#define DEFAULT_VOLTAGE_STABLE_TIME (100 / 20) // 100uS
+#define DEFAULT_PLL_LOCK_TIME 2 // 2uS
+#define DEFAULT_TRANSITION_LATENCY 100 // 100uS
+#define DEFAULT_BUS_MASTER_LATENCY 9 // 9uS
+#define DEFAULT_CPU_SCOPE_NUMBER "0UPC"
+
+// Defines for Common ACPI
+// -----------------------------
+#define SCOPE_OPCODE 0x10
+#define NAME_OPCODE 0x08
+#define METHOD_OPCODE 0x14
+#define PACKAGE_OPCODE 0x12
+#define BUFFER_OPCODE 0x11
+#define BYTE_PREFIX_OPCODE 0x0A
+#define WORD_PREFIX_OPCODE 0x0B
+#define DWORD_PREFIX_OPCODE 0x0C
+#define RETURN_OPCODE 0xA4
+#define ACPI_BUFFER 0x080A0B11ul
+
+// Generic Register Descriptor (GDR) Fields
+#define GDR_ASI_SYSTEM_IO 0x01 // Address Space ID
+#define GDR_ASZ_BYTE_ACCESS 0x01 // Address Size
+
+// Defines for ACPI Scope Table
+// ----------------------------
+#define SCOPE_LENGTH (SCOPE_STRUCT_SIZE + \
+ PCT_STRUCT_SIZE + \
+ PSS_HEADER_STRUCT_SIZE + \
+ PSS_BODY_STRUCT_SIZE + \
+ PPC_HEADER_BODY_STRUCT_SIZE)
+#define SCOPE_VALUE1 0x5C
+#define SCOPE_VALUE2 0x2E
+#define SCOPE_NAME__ '_'
+#define SCOPE_NAME_P 'P'
+#define SCOPE_NAME_R 'R'
+#define SCOPE_NAME_S 'S'
+#define SCOPE_NAME_B 'B'
+#define SCOPE_NAME_C 'C'
+#define SCOPE_NAME_U 'U'
+#define SCOPE_NAME_0 '0'
+#define SCOPE_NAME_1 '1'
+#define SCOPE_NAME_2 '2'
+#define SCOPE_NAME_3 '3'
+#define SCOPE_NAME_A 'A'
+
+#ifdef OEM_SCOPE_NAME
+ #if (OEM_SCOPE_NAME > 'Z') || (OEM_SCOPE_NAME < 'A')
+ #error "OEM_SCOPE_NAME: it should be only one char long AND a valid letter (A~Z)"
+ #endif
+ #define SCOPE_NAME_VALUE OEM_SCOPE_NAME
+#else
+ #define SCOPE_NAME_VALUE SCOPE_NAME_C
+#endif // OEM_SCOPE_NAME
+
+#ifdef OEM_SCOPE_NAME1
+ #if (!(((OEM_SCOPE_NAME1 >= 'A') && (OEM_SCOPE_NAME1 <= 'Z')) || \
+ ((OEM_SCOPE_NAME1 >= '0') && (OEM_SCOPE_NAME1 <= '9')) || \
+ (OEM_SCOPE_NAME1 == '_')))
+ #error "OEM_SCOPE_NAME1: it should be only one char long AND a valid letter (0~9, A~F)"
+ #endif
+ #define SCOPE_NAME_VALUE1 OEM_SCOPE_NAME1
+#else
+ #define SCOPE_NAME_VALUE1 SCOPE_NAME_0
+#endif // OEM_SCOPE_NAME
+
+// Defines for PCT Control and Status Table
+// ----------------------------------------
+#define PCT_NAME__ '_'
+#define PCT_NAME_P 'P'
+#define PCT_NAME_C 'C'
+#define PCT_NAME_T 'T'
+#define PCT_VALUE1 0x11022C12ul
+#define PCT_VALUE2 0x0A14
+#define PCT_VALUE3 0x11
+#define GENERIC_REG_DESCRIPTION 0x82
+#define PCT_LENGTH 0x0C
+#define PCT_ADDRESS_SPACE_ID 0x7F
+#define PCT_REGISTER_BIT_WIDTH 0x40
+#define PCT_REGISTER_BIT_OFFSET 0x00
+#define PCT_RESERVED 0x00
+#define PCT_CONTROL_REG_LO 0xC0010062ul
+#define PCT_CONTROL_REG_HI 0x00
+#define PCT_VALUE4 0x14110079ul
+#define PCT_VALUE5 0x110A
+#define PCT_STATUS_REG_LO 0x00
+#define PCT_STATUS_REG_HI 0x00
+#define PCT_VALUE6 0x0079
+
+
+// Defines for PSS Header Table
+// ----------------------------
+#define PSS_NAME__ '_'
+#define PSS_NAME_X 'X'
+#define PSS_NAME_P 'P'
+#define PSS_NAME_S 'S'
+#define PSS_LENGTH (sizeof pssBodyStruct + 3)
+#define NUM_OF_ITEMS_IN_PSS 0x00
+
+
+// Defines for PSS Header Table
+// ----------------------------
+#define PSS_PKG_LENGTH 0x20 // PSS_BODY_STRUCT_SIZE - 1
+#define PSS_NUM_OF_ELEMENTS 0x06
+#define PSS_FREQUENCY 0x00
+#define PSS_POWER 0x00
+#define PSS_TRANSITION_LATENCY DEFAULT_TRANSITION_LATENCY
+#define PSS_BUS_MASTER_LATENCY DEFAULT_BUS_MASTER_LATENCY
+#define PSS_CONTROL ((DEFAULT_ISOCH_RELIEF_TIME << 30) + \
+ (DEFAULT_RAMP_VOLTAGE_OFFSET << 28) + \
+ (DEFAULT_EXT_TYPE << 27) + \
+ (DEFAULT_PLL_LOCK_TIME << 20) + \
+ (DEFAULT_MAX_VOLTAGE_STEP << 18) + \
+ (DEFAULT_VOLTAGE_STABLE_TIME << 11) + \
+ (PSS_VID << 6) + PSS_FID)
+#define PSS_STATUS (DEFAULT_EXTENDED_TYPE << 11) + (PSS_VID << 6) + (PSS_FID)
+
+// Defines for XPSS Header Table
+// ----------------------------
+#define XPSS_PKG_LENGTH 0x47 // XPSS_BODY_STRUCT_SIZE - 1
+#define XPSS_NUM_OF_ELEMENTS 0x08
+#define XPSS_ACPI_BUFFER 0x080A0B11ul
+
+
+// Defines for PPC Header Table
+// ----------------------------
+#define PPC_NAME__ '_'
+#define PPC_NAME_P 'P'
+#define PPC_NAME_C 'C'
+#define PPC_NAME_V 'V'
+#define PPC_METHOD_FLAGS 0x00;
+#define PPC_VALUE1 0x0A;
+
+// Defines for PSD Header Table
+// ----------------------------
+#define PSD_NAME__ '_'
+#define PSD_NAME_P 'P'
+#define PSD_NAME_S 'S'
+#define PSD_NAME_D 'D'
+#define PSD_HEADER_LENGTH (PSD_BODY_STRUCT_SIZE + 2)
+#define PSD_VALUE1 0x01
+
+
+// Defines for PSD Header Table
+// ----------------------------
+#define PSD_PKG_LENGTH (PSD_BODY_STRUCT_SIZE - 1)
+#define NUM_OF_ENTRIES 0x05
+#define PSD_NUM_OF_ENTRIES 0x05
+#define PSD_REVISION 0x00
+#define PSD_DEPENDENCY_DOMAIN 0x00
+#define PSD_COORDINATION_TYPE_HW_ALL 0xFE
+#define PSD_COORDINATION_TYPE_SW_ANY 0xFD
+#define PSD_COORDINATION_TYPE_SW_ALL 0xFC
+#define PSD_NUM_OF_PROCESSORS 0x01
+#define PSD_TWO_CORES_PER_COMPUTE_UNIT 0x02
+#define PSD_THREE_CORES_PER_COMPUTE_UNIT 0x03
+#define PSD_FOUR_CORES_PER_COMPUTE_UNIT 0x04
+
+
+#define CUSTOM_PSTATE_FLAG 0x55
+#define PSTATE_FLAG_1 0x55
+#define TARGET_PSTATE_FLAG 0xAA
+#define PSTATE_FLAG_2 0xAA
+
+/*----------------------------------------------------------------------------------------
+ * T Y P E D E F S, S T R U C T U R E S, E N U M S
+ *----------------------------------------------------------------------------------------
+ */
+//----------------------------------------------------------------------------
+// ACPI P-States AML TYPEDEFS, STRUCTURES, ENUMS
+//
+//----------------------------------------------------------------------------
+
+//--------------------------------------------
+// AML code definition
+// (Scope)
+//---------------------------------------------
+/// SCOPE
+typedef struct _SCOPE {
+ UINT8 ScopeOpcode; ///< Opcode
+ UINT16 ScopeLength; ///< Scope Length
+ UINT8 ScopeValue1; ///< Value1
+ UINT8 ScopeValue2; ///< Value2
+ UINT8 ScopeNamePt1a__; ///< Name Pointer
+ UINT8 ScopeNamePt1a_P; ///< Name Pointer
+ UINT8 ScopeNamePt1a_R; ///< Name Pointer
+ UINT8 ScopeNamePt1b__; ///< Name Pointer
+ UINT8 ScopeNamePt2a_C; ///< Name Pointer
+ UINT8 ScopeNamePt2a_P; ///< Name Pointer
+ UINT8 ScopeNamePt2a_U; ///< Name Pointer
+ UINT8 ScopeNamePt2a_0; ///< Name Pointer
+} SCOPE;
+#define SCOPE_STRUCT_SIZE 13 // 13 Bytes
+
+//--------------------------------------------
+// AML code definition
+// (PCT Header and Body)
+//---------------------------------------------
+
+///Performance Control Header
+typedef struct _PCT_HEADER_BODY {
+ UINT8 NameOpcode; ///< Opcode
+ UINT8 PctName_a__; ///< String "_"
+ UINT8 PctName_a_P; ///< String "P"
+ UINT8 PctName_a_C; ///< String "C"
+ UINT8 PctName_a_T; ///< String "T"
+ UINT32 Value1; ///< Value1
+ UINT16 Value2; ///< Value2
+ UINT8 Value3; ///< Value3
+ UINT8 GenericRegDescription1; ///< Generic Reg Description
+ UINT16 Length1; ///< Length1
+ UINT8 AddressSpaceId1; ///< PCT Address Space ID
+ UINT8 RegisterBitWidth1; ///< PCT Register Bit Width
+ UINT8 RegisterBitOffset1; ///< PCT Register Bit Offset
+ UINT8 Reserved1; ///< Reserved
+ UINT32 ControlRegAddressLo; ///< Control Register Address Low
+ UINT32 ControlRegAddressHi; ///< Control Register Address High
+ UINT32 Value4; ///< Value4
+ UINT16 Value5; ///< Value 5
+ UINT8 GenericRegDescription2; ///< Generic Reg Description
+ UINT16 Length2; ///< Length2
+ UINT8 AddressSpaceId2; ///< PCT Address Space ID
+ UINT8 RegisterBitWidth2; ///< PCT Register Bit Width
+ UINT8 RegisterBitOffset2; ///< PCT Register Bit Offset
+ UINT8 Reserved2; ///< Reserved
+ UINT32 StatusRegAddressLo; ///< Control Register Address Low
+ UINT32 StatusRegAddressHi; ///< Control Register Address High
+ UINT16 Value6; ///< Values
+} PCT_HEADER_BODY;
+#define PCT_STRUCT_SIZE 50 // 50 Bytes
+
+
+//--------------------------------------------
+// AML code definition
+// (PSS Header)
+//--------------------------------------------
+///Performance Supported States Header
+typedef struct _PSS_HEADER {
+ UINT8 NameOpcode; ///< Opcode
+ UINT8 PssName_a__; ///< String "_"
+ UINT8 PssName_a_P; ///< String "P"
+ UINT8 PssName_a_S; ///< String "S"
+ UINT8 PssName_b_S; ///< String "S"
+ UINT8 PkgOpcode; ///< Package Opcode
+ UINT16 PssLength; ///< PSS Length
+ UINT8 NumOfItemsInPss; ///< Number of Items in PSS
+} PSS_HEADER;
+#define PSS_HEADER_STRUCT_SIZE 9 // 9 Bytes
+
+
+//--------------------------------------------
+// AML code definition
+// (PSS Body)
+//--------------------------------------------
+///Performance Supported States Body
+typedef struct _PSS_BODY {
+ UINT8 PkgOpcode; ///< Package Opcode
+ UINT8 PkgLength; ///< Package Length
+ UINT8 NumOfElements; ///< Number of Elements
+ UINT8 DwordPrefixOpcode1; ///< Prefix Opcode1
+ UINT32 Frequency; ///< Frequency
+ UINT8 DwordPrefixOpcode2; ///< Prefix Opcode2
+ UINT32 Power; ///< Power
+ UINT8 DwordPrefixOpcode3; ///< Prefix Opcode3
+ UINT32 TransitionLatency; ///< Transition Latency
+ UINT8 DwordPrefixOpcode4; ///< Prefix Opcode4
+ UINT32 BusMasterLatency; ///< Bus Master Latency
+ UINT8 DwordPrefixOpcode5; ///< Prefix Opcode5
+ UINT32 Control; ///< Control
+ UINT8 DwordPrefixOpcode6; ///< Prefix Opcode6
+ UINT32 Status; ///< Status
+} PSS_BODY;
+#define PSS_BODY_STRUCT_SIZE 33 // 33 Bytes
+
+
+/*--------------------------------------------
+ * AML code definition
+ * (XPSS Header)
+ *--------------------------------------------
+ */
+/// Extended PSS Header
+typedef struct _XPSS_HEADER {
+ UINT8 NameOpcode; ///< 08h
+ UINT8 XpssName_a_X; ///< String "X"
+ UINT8 XpssName_a_P; ///< String "P"
+ UINT8 XpssName_a_S; ///< String "S"
+ UINT8 XpssName_b_S; ///< String "S"
+ UINT8 PkgOpcode; ///< 12h
+ UINT16 XpssLength; ///< XPSS Length
+ UINT8 NumOfItemsInXpss; ///< Number of Items in XPSS
+} XPSS_HEADER;
+#define XPSS_HEADER_STRUCT_SIZE 9 // 9 Bytes
+
+/*--------------------------------------------
+ * AML code definition
+ * (XPSS Body)
+ *--------------------------------------------
+ */
+/// Extended PSS Body
+typedef struct _XPSS_BODY {
+ UINT8 PkgOpcode; ///< 12h
+ UINT8 PkgLength; ///< Package Length
+ UINT8 XpssValueTbd; ///< XPSS Value
+ UINT8 NumOfElements; ///< Number of Elements
+ UINT8 DwordPrefixOpcode1; ///< Prefix Opcode1
+ UINT32 Frequency; ///< Frequency
+ UINT8 DwordPrefixOpcode2; ///< Prefix Opcode2
+ UINT32 Power; ///< Power
+ UINT8 DwordPrefixOpcode3; ///< Prefix Opcode3
+ UINT32 TransitionLatency; ///< Transition Latency
+ UINT8 DwordPrefixOpcode4; ///< Prefix Opcode4
+ UINT32 BusMasterLatency; ///< Bus Master Latency
+ UINT32 ControlBuffer; ///< Control Buffer
+ UINT32 ControlLo; ///< Control Low
+ UINT32 ControlHi; ///< Control High
+ UINT32 StatusBuffer; ///< Status Buffer
+ UINT32 StatusLo; ///< Status Low
+ UINT32 StatusHi; ///< Status High
+ UINT32 ControlMaskBuffer; ///< Control Mask Buffer
+ UINT32 ControlMaskLo; ///< Control Mask Low
+ UINT32 ControlMaskHi; ///< Control Mask High
+ UINT32 StatusMaskBuffer; ///< Status Mask Buffer
+ UINT32 StatusMaskLo; ///< Status Mask Low
+ UINT32 StatusMaskHi; ///< Status Mask High
+} XPSS_BODY;
+#define XPSS_BODY_STRUCT_SIZE 72 // 72 Bytes
+
+/*--------------------------------------------
+ * AML code definition
+ * (PPC Header and Body)
+ *--------------------------------------------
+ */
+/// Performance Present Capabilities Header
+typedef struct _PPC_HEADER_BODY {
+ UINT8 NameOpcode; ///< Name Opcode
+ UINT8 PpcName_a_P; ///< String "P"
+ UINT8 PpcName_b_P; ///< String "P"
+ UINT8 PpcName_a_C; ///< String "C"
+ UINT8 PpcName_a_V; ///< String "V"
+ UINT8 Value1; ///< Value
+ UINT8 DefaultPerfPresentCap; ///< Default Perf Present Cap
+ UINT8 MethodOpcode; ///< Method Opcode
+ UINT8 PpcLength; ///< Method Length
+ UINT8 PpcName_a__; ///< String "_"
+ UINT8 PpcName_c_P; ///< String "P"
+ UINT8 PpcName_d_P; ///< String "P"
+ UINT8 PpcName_b_C; ///< String "C"
+ UINT8 MethodFlags; ///< Method Flags
+ UINT8 ReturnOpcode; ///< Return Opcoce
+ UINT8 PpcName_e_P; ///< String "P"
+ UINT8 PpcName_f_P; ///< String "P"
+ UINT8 PpcName_c_C; ///< String "C"
+ UINT8 PpcName_b_V; ///< String "V"
+
+} PPC_HEADER_BODY;
+#define PPC_HEADER_BODY_STRUCT_SIZE 19 // 19 Bytes
+#define PPC_METHOD_LENGTH 11 // 11 Bytes
+
+
+/*--------------------------------------------
+ * AML code definition
+ * (PSD Header)
+ *--------------------------------------------
+ */
+/// P-State Dependency Header
+typedef struct _PSD_HEADER {
+ UINT8 NameOpcode; ///< Name Opcode
+ UINT8 PsdName_a__; ///< String "_"
+ UINT8 PsdName_a_P; ///< String "P"
+ UINT8 PsdName_a_S; ///< String "S"
+ UINT8 PsdName_a_D; ///< String "D"
+ UINT8 PkgOpcode; ///< Package Opcode
+ UINT8 PsdLength; ///< PSD Length
+ UINT8 Value1; ///< Value
+} PSD_HEADER;
+#define PSD_HEADER_STRUCT_SIZE 8 // 8 Bytes
+
+/*--------------------------------------------
+ * AML code definition
+ * (PSD Body)
+ *--------------------------------------------
+ */
+/// P-State Dependency Body
+typedef struct _PSD_BODY {
+ UINT8 PkgOpcode; ///< Package Opcode
+ UINT8 PkgLength; ///< Package Length
+ UINT8 NumOfEntries; ///< Number of Entries
+ UINT8 BytePrefixOpcode1; ///< Prefix Opcode1 in Byte
+ UINT8 PsdNumOfEntries; ///< PSD Number of Entries
+ UINT8 BytePrefixOpcode2; ///< Prefix Opcode2 in Byte
+ UINT8 PsdRevision; ///< PSD Revision
+ UINT8 DwordPrefixOpcode1; ///< Prefix Opcode1 in DWord
+ UINT32 DependencyDomain; ///< Dependency Domain
+ UINT8 DwordPrefixOpcode2; ///< Prefix Opcode2 in DWord
+ UINT32 CoordinationType; ///< (0xFC = SW_ALL, 0xFD = SW_ANY, 0xFE = HW_ALL)
+ UINT8 DwordPrefixOpcode3; ///< Prefix Opcode3 in DWord
+ UINT32 NumOfProcessors; ///< Number of Processors
+} PSD_BODY;
+#define PSD_BODY_STRUCT_SIZE 22 // 22 Bytes
+
+//----------------------------------------------------------------------------
+// WHEA TYPEDEFS, STRUCTURES, ENUMS
+//
+//----------------------------------------------------------------------------
+
+/// HEST MCE TABLE
+typedef struct _AMD_HEST_MCE_TABLE {
+ UINT16 TblLength; ///< Length, in bytes, of entire AMD_HEST_MCE structure.
+ UINT32 GlobCapInitDataLSD; ///< Holds the value that the OS will program into
+ UINT32 GlobCapInitDataMSD; ///< the machine check global capability register(MCG_CAP).
+ UINT32 GlobCtrlInitDataLSD; ///< Holds the value that the OS will program into
+ UINT32 GlobCtrlInitDataMSD; ///< the machine check global control register(MCG_CTL).
+ UINT8 NumHWBanks; ///< The number of hardware error reporting banks.
+ UINT8 Rsvd[7]; ///< reserve 7 bytes as spec's required
+} AMD_HEST_MCE_TABLE;
+
+/// HEST CMC TABLE
+typedef struct _AMD_HEST_CMC_TABLE {
+ UINT16 TblLength; ///< Length, in bytes, of entire AMD_HEST_CMC structure.
+ UINT8 NumHWBanks; ///< The number of hardware error reporting banks.
+ UINT8 Rsvd[3]; ///< reserve 3 bytes as spec's required
+} AMD_HEST_CMC_TABLE;
+
+/// HEST BANK
+typedef struct _AMD_HEST_BANK {
+ UINT8 BankNum; ///< Zero-based index identifies the machine check error bank.
+ UINT8 ClrStatusOnInit; ///< Indicates if the status information in this machine check bank
+ ///< is to be cleared during system initialization.
+ UINT8 StatusDataFormat; ///< Indicates the format of the data in the status register
+ UINT8 ConfWriteEn; ///< This field indicates whether configuration parameters may be
+ ///< modified by the OS. If the bit for the associated parameter is
+ ///< set, the parameter is writable by the OS.
+ UINT32 CtrlRegMSRAddr; ///< Address of the hardware bank's control MSR. Ignored if zero.
+
+ UINT32 CtrlInitDataLSD; ///< This is the value the OS will program into the machine check
+ UINT32 CtrlInitDataMSD; ///< bank's control register
+ UINT32 StatRegMSRAddr; ///< Address of the hardware bank's MCi_STAT MSR. Ignored if zero.
+ UINT32 AddrRegMSRAddr; ///< Address of the hardware bank's MCi_ADDR MSR. Ignored if zero.
+ UINT32 MiscRegMSRAddr; ///< Address of the hardware bank's MCi_MISC MSR. Ignored if zero.
+} AMD_HEST_BANK;
+
+/// Initial data of AMD_HEST_BANK
+typedef struct _AMD_HEST_BANK_INIT_DATA {
+ UINT32 CtrlInitDataLSD; ///< Initial data of CtrlInitDataLSD
+ UINT32 CtrlInitDataMSD; ///< Initial data of CtrlInitDataMSD
+ UINT32 CtrlRegMSRAddr; ///< Initial data of CtrlRegMSRAddr
+ UINT32 StatRegMSRAddr; ///< Initial data of StatRegMSRAddr
+ UINT32 AddrRegMSRAddr; ///< Initial data of AddrRegMSRAddr
+ UINT32 MiscRegMSRAddr; ///< Initial data of MiscRegMSRAddr
+} AMD_HEST_BANK_INIT_DATA;
+
+/// MSR179 Global Machine Check Capabilities data struct
+typedef struct _MSR_MCG_CAP_STRUCT {
+ UINT64 Count:8; ///< Indicates the number of
+ ///< error-reporting banks visible to each core
+ UINT64 McgCtlP:1; ///< 1=The machine check control registers
+ UINT64 Rsvd:55; ///< reserved
+} MSR_MCG_CAP_STRUCT;
+
+/// Initial data of WHEA
+typedef struct _AMD_WHEA_INIT_DATA {
+ UINT32 GlobCapInitDataLSD; ///< Holds the value that the OS will program into the machine
+ UINT32 GlobCapInitDataMSD; ///< Check global capability register
+ UINT32 GlobCtrlInitDataLSD; ///< Holds the value that the OS will grogram into the machine
+ UINT32 GlobCtrlInitDataMSD; ///< Check global control register
+ UINT8 ClrStatusOnInit; ///< Indicates if the status information in this machine check
+ ///< bank is to be cleared during system initialization
+ UINT8 StatusDataFormat; ///< Indicates the format of the data in the status register
+ UINT8 ConfWriteEn; ///< This field indicates whether configuration parameters may be
+ ///< modified by the OS. If the bit for the associated parameter is
+ ///< set, the parameter is writable by the OS.
+ UINT8 HestBankNum; ///< Number of HEST Bank
+ AMD_HEST_BANK_INIT_DATA *HestBankInitData; ///< Pointer to Initial data of HEST Bank
+} AMD_WHEA_INIT_DATA;
+
+//----------------------------------------------------------------------------
+// DMI TYPEDEFS, STRUCTURES, ENUMS
+//
+//----------------------------------------------------------------------------
+/// DMI brand information
+typedef struct {
+ UINT16 String1:4; ///< String1
+ UINT16 String2:4; ///< String2
+ UINT16 Model:7; ///< Model
+ UINT16 Pg:1; ///< Page
+} BRAND_ID;
+
+/// DMI cache information
+typedef struct {
+ UINT32 L1CacheSize; ///< L1 cache size
+ UINT8 L1CacheAssoc; ///< L1 cache associativity
+ UINT32 L2CacheSize; ///< L2 cache size
+ UINT8 L2CacheAssoc; ///< L2 cache associativity
+ UINT32 L3CacheSize; ///< L3 cache size
+ UINT8 L3CacheAssoc; ///< L3 cache associativity
+} CPU_CACHE_INFO;
+
+/// DMI processor information
+typedef struct {
+ UINT8 ExtendedFamily; ///< Extended Family
+ UINT8 ExtendedModel; ///< Extended Model
+ UINT8 BaseFamily; ///< Base Family
+ UINT8 BaseModel; ///< Base Model
+ UINT8 Stepping; ///< Stepping
+ UINT8 PackageType; ///< PackageType
+ BRAND_ID BrandId; ///< BrandId which contains information about String1, String2, Model and Page
+ UINT8 TotalCoreNumber; ///< Number of total cores
+ UINT8 EnabledCoreNumber; ///< Number of enabled cores
+ UINT8 ProcUpgrade; ///< ProcUpdrade
+ CPU_CACHE_INFO CacheInfo; ///< CPU cache info
+} CPU_TYPE_INFO;
+
+/// A structure containing processor name string and
+/// the value that should be provide to DMI type 4 processor family
+typedef struct {
+ IN CONST CHAR8 *Stringstart; ///< The literal string
+ IN UINT8 T4ProcFamilySetting; ///< The value set to DMI type 4 processor family
+} CPU_T4_PROC_FAMILY;
+
+/// DMI ECC information
+typedef struct {
+ BOOLEAN EccCapable; ///< ECC Capable
+} CPU_GET_MEM_INFO;
+
+/* Transfer vectors for DMI family specific routines */
+typedef VOID OPTION_DMI_GET_CPU_INFO (
+ IN OUT CPU_TYPE_INFO *CpuInfoPtr,
+ IN AMD_CONFIG_PARAMS *StdHeader
+ );
+
+typedef VOID OPTION_DMI_GET_PROC_FAMILY (
+ IN OUT UINT8 *T4ProcFamily,
+ IN PROC_FAMILY_TABLE *CpuDmiProcFamilyTable,
+ IN CPU_TYPE_INFO *CpuInfo,
+ IN AMD_CONFIG_PARAMS *StdHeader
+ );
+
+typedef UINT8 OPTION_DMI_GET_VOLTAGE (
+ IN AMD_CONFIG_PARAMS *StdHeader
+ );
+
+typedef UINT16 OPTION_DMI_GET_MAX_SPEED (
+ IN AMD_CONFIG_PARAMS *StdHeader
+ );
+
+typedef UINT16 OPTION_DMI_GET_EXT_CLOCK (
+ IN AMD_CONFIG_PARAMS *StdHeader
+ );
+
+typedef VOID OPTION_DMI_GET_MEM_INFO (
+ IN OUT CPU_GET_MEM_INFO *CpuGetMemInfoPtr,
+ IN AMD_CONFIG_PARAMS *StdHeader
+ );
+
+/// Brand table entry format
+typedef struct {
+ UINT8 PackageType; ///< Package type
+ UINT8 PgOfBrandId; ///< Page
+ UINT8 NumberOfCores; ///< Number of cores
+ UINT8 String1ofBrandId; ///< String1
+ UINT8 ValueSetToDmiTable; ///< The value which will should be set to DMI table
+} DMI_BRAND_ENTRY;
+
+/// Family specific data table structure
+struct _PROC_FAMILY_TABLE {
+ UINT64 ProcessorFamily; ///< processor
+ OPTION_DMI_GET_CPU_INFO *DmiGetCpuInfo; ///< transfer vectors
+ OPTION_DMI_GET_PROC_FAMILY *DmiGetT4ProcFamily; ///< Get DMI type 4 processor family information
+ OPTION_DMI_GET_VOLTAGE *DmiGetVoltage; ///< vector for reading voltage
+ OPTION_DMI_GET_MAX_SPEED *DmiGetMaxSpeed; ///< vector for reading speed
+ OPTION_DMI_GET_EXT_CLOCK *DmiGetExtClock; ///< vector for reading external clock speed
+ OPTION_DMI_GET_MEM_INFO *DmiGetMemInfo; ///< Get memory information
+ UINT8 LenBrandList; ///< size of brand table
+ CONST DMI_BRAND_ENTRY *DmiBrandList; ///< translate brand info to DMI identifier
+};
+
+//----------------------------------------------------------------------------
+// SLIT TYPEDEFS, STRUCTURES, ENUMS
+//
+//----------------------------------------------------------------------------
+/// Format for SRAT Header
+typedef struct {
+ UINT8 Sign[4]; ///< Signature
+ UINT32 TableLength; ///< Table Length
+ UINT8 Revision; ///< Revision
+ UINT8 Checksum; ///< Checksum
+ UINT8 OemId[6]; ///< OEM ID
+ UINT8 OemTableId[8]; ///< OEM Tabled ID
+ UINT32 OemRev; ///< OEM Revision
+ UINT8 CreatorId[4]; ///< Creator ID
+ UINT32 CreatorRev; ///< Creator Revision
+} ACPI_TABLE_HEADER;
+
+//----------------------------------------------------------------------------
+// SRAT TYPEDEFS, STRUCTURES, ENUMS
+//
+//----------------------------------------------------------------------------
+/// Format for SRAT Header
+typedef struct _CPU_SRAT_HEADER {
+ UINT8 Sign[4]; ///< Signature
+ UINT32 TableLength; ///< Table Length
+ UINT8 Revision; ///< Revision
+ UINT8 Checksum; ///< Checksum
+ UINT8 OemId[6]; ///< OEM ID
+ UINT8 OemTableId[8]; ///< OEM Tabled ID
+ UINT32 OemRev; ///< OEM Revision
+ UINT8 CreatorId[4]; ///< Creator ID
+ UINT32 CreatorRev; ///< Creator Revision
+ UINT32 TableRev; ///< Table Revision
+ UINT8 Reserved[8]; ///< Reserved
+} CPU_SRAT_HEADER;
+
+
+/// Format for SRAT APIC Affinity Entry
+typedef struct _CPU_SRAT_APIC_ENTRY {
+ UINT8 Type; ///< Type
+ UINT8 Length; ///< Length
+ UINT8 Domain; ///< Domain
+ UINT8 ApicId; ///< Apic ID
+ UINT32 Flags; ///< Flags
+ UINT8 LSApicEid; ///< Local SAPIC EID
+ UINT8 Reserved[7]; ///< Reserved
+} CPU_SRAT_APIC_ENTRY;
+
+
+/// Format for SRAT Memory Affinity Entry
+typedef struct _CPU_SRAT_MEMORY_ENTRY {
+ UINT8 Type; ///< 0: Memory affinity = 1
+ UINT8 Length; ///< 1: Length = 40 bytes
+ UINT32 Domain; ///< 2: Proximity domain
+ UINT8 Reserved1[2]; ///< 6: Reserved
+ UINT32 BaseAddrLow; ///< 8: Low 32bits address base
+ UINT32 BaseAddrHigh; ///< 12: High 32bits address base
+ UINT32 LengthAddrLow; ///< 16: Low 32bits address limit
+ UINT32 LengthAddrHigh; ///< 20: High 32bits address limit
+ UINT8 Reserved2[4]; ///< 24: Memory Type
+ UINT32 Flags; ///< 28: Flags
+ UINT8 Reserved3[8]; ///< 32: Reserved
+} CPU_SRAT_MEMORY_ENTRY;
+
+//----------------------------------------------------------------------------
+// CRAT TYPEDEFS, STRUCTURES, ENUMS
+// Component Resource Affinity Table
+//----------------------------------------------------------------------------
+/// Format for CRAT Header
+typedef struct {
+ UINT8 Sign[4]; ///< CRAT, Signature for the Component Resource Affinity Table.
+ UINT32 Length; ///< Length, in bytes, of the entire CRAT
+ UINT8 Revision; ///< 0
+ UINT8 Checksum; ///< Entire table must sum to zero.
+ UINT8 OemId[6]; ///< OEM ID
+ UINT8 OemTableId[8]; ///< OEM Tabled ID
+ UINT32 OemRev; ///< OEM Revision
+ UINT8 CreatorId[4]; ///< Creator ID
+ UINT32 CreatorRev; ///< Creator Revision
+ UINT32 TotalEntries; ///< total number[n] of entries in the CRAT
+ UINT16 NumDomains; ///< Number of HSA proximity domains
+ UINT8 Reserved[6]; ///< Reserved
+} CRAT_HEADER;
+
+/// Flags field of the CRAT HSA Processing Unit Affinity Structure
+typedef struct {
+ UINT32 Enabled:1; ///< Enabled
+ UINT32 HotPluggable:1; ///< Hot Pluggable
+ UINT32 CpuPresent:1; ///< Cpu Present
+ UINT32 GpuPresent:1; ///< Gpu Present
+ UINT32 IommuPresent:1; ///< IOMMU Present
+ UINT32 :27; ///< Reserved
+} CRAT_HSA_PROCESSING_UNIT_FLAG;
+
+/// CRAT HSA Processing Unit Affinity Structure
+typedef struct {
+ UINT8 Type; ///< 0 - CRAT HSA Processing Unit Structure
+ UINT8 Length; ///< 40
+ UINT16 Reserved; ///< Reserved
+ CRAT_HSA_PROCESSING_UNIT_FLAG Flags; ///< Flags - HSA Processing Unit Affinity Structure
+ UINT32 ProximityDomain; ///< Integer that represents the proximity domain to which the node belongs to
+ UINT32 ProcessorIdLow; ///< Low value of the logical processor included in this HSA proximity domain
+ UINT16 NumCPUCores; ///< Indicates count of CCompute execution units present in this APU node.
+ UINT16 NumSIMDCores; ///< Indicates maximum count of HCompute SIMD cores present in this node.
+ UINT16 MaxWavesSIMD; ///< This identifies the max. number of launched waves per SIMD.
+ UINT16 IoCount; ///< Number of discoverable IO Interfaces connecting this node to other components.
+ UINT16 HSACapability; ///< Must be 0
+ UINT16 LDSSizeInKB; ///< Size of LDS memory per SIMD Wavefront
+ UINT8 WaveFrontSize; ///< 64, may be 32 for some FSA based architectures
+ UINT8 NumBanks; ///< Number of Banks or "Shader Engines", typically 1 or 2
+ UINT16 uEngineIdentifier; ///< Identifier (Rev) of the GPU uEngine or firmware
+ UINT8 NumArrays; ///< Number of SIMD Arrays per Engine
+ UINT8 NumCUPerArray; ///< Number of Compute Units (CU) per SIMD Array
+ UINT8 NumSIMDPerCU; ///< Number of SIMD representing a Compute Unit
+ UINT8 MaxSlotsScratchCU; ///< Max. Number of temp. memory ("scratch") wave slots
+ ///< available to access, may be 0 if HW has no restrictions
+ UINT8 Reserved1[4]; ///< Reserved
+} CRAT_HSA_PROCESSING_UNIT;
+
+/// Flags field of the CRAT Memory Affinity Structure
+typedef struct {
+ UINT32 Enabled:1; ///< Enabled
+ UINT32 HotPluggable:1; ///< Hot Pluggable
+ UINT32 NonVolatile:1; ///< If set, the memory region represents Non-Volatile memory
+ UINT32 :29; ///< Reserved
+} CRAT_MEMORY_FLAG;
+
+/// CRAT Memory Affinity Structure
+typedef struct {
+ UINT8 Type; ///< 1 - CRAT Memory Affinity Structure
+ UINT8 Length; ///< 40
+ UINT16 Reserved; ///< Reserved
+ CRAT_MEMORY_FLAG Flags; ///< Flags - Memory Affinity Structure. Indicates whether the region of memory is enabled and can be hot plugged
+ UINT32 ProximityDomain; ///< Integer that represents the proximity domain to which the node belongs to
+ UINT32 BaseAddressLow; ///< Low 32Bits of the Base Address of the memory range
+ UINT32 BaseAddressHigh; ///< High 32Bits of the Base Address of the memory range
+ UINT32 LengthLow; ///< Low 32Bits of the length of the memory range
+ UINT32 LengthHigh; ///< High 32Bits of the length of the memory range
+ UINT32 Width; ///< Memory width - Specifies the number of parallel bits of the memory interface
+ UINT8 Reserved1[8]; ///< Reserved
+} CRAT_MEMORY;
+
+/// Flags field of the CRAT Cache Affinity structure
+typedef struct {
+ UINT32 Enabled:1; ///< Enabled
+ UINT32 DataCache:1; ///< 1 if cache includes data
+ UINT32 InstructionCache:1; ///< 1 if cache includes instructions
+ UINT32 CpuCache:1; ///< 1 if cache is part of CPU functionality
+ UINT32 SimdCache:1; ///< 1 if cache is part of SIMD functionality
+ UINT32 :27; ///< Reserved
+} CRAT_CACHE_FLAG;
+
+/// CRAT Cache Affinity Structure
+typedef struct {
+ UINT8 Type; ///< 2 - CRAT Cache Affinity Structure
+ UINT8 Length; ///< 64
+ UINT16 Reserved; ///< Reserved
+ CRAT_CACHE_FLAG Flags; ///< Flags - Cache Affinity Structure. Indicates whether the region of cache is enabled
+ UINT32 ProcessorIdLow; ///< Low value of a logical processor which includes this component
+ UINT8 SiblingMap[32]; ///< Bitmask of Processor Id sharing this component. 1 bit per logical processor
+ UINT32 CacheSize; ///< Cache size in KB
+ UINT8 CacheLevel; ///< Integer representing level: 1, 2, 3, 4, etc.
+ UINT8 LinesPerTag; ///< Cache Lines per tag
+ UINT16 CacheLineSize; ///< Cache line size in bytes
+ UINT8 Associativity; ///< Cache associativity
+ ///< The associativity fields are encoded as follows:
+ ///< 00h: Reserved.
+ ///< 01h: Direct mapped.
+ ///< 02h-FEh: Associativity. (e.g., 04h = 4-way associative.)
+ ///< FFh: Fully associative
+ UINT8 CacheProperties; ///< Cache Properties bits [2:0] represent Inclusive/Exclusive property encoded.
+ ///< 0: Cache is strictly exclusive to lower level caches.
+ ///< 1: Cache is mostly exclusive to lower level caches.
+ ///< 2: Cache is strictly inclusive to lower level caches.
+ ///< 3: Cache is mostly inclusive to lower level caches.
+ ///< 4: Cache is a "constant cache" (= explicit update)
+ ///< 5: Cache is a "specialty cache" (e.g. Texture cache)
+ ///< 6-7: Reserved
+ ///< CacheProperties bits [7:3] are reserved
+ UINT16 CacheLatency; ///< Cost of time to access cache described in nanoseconds.
+ UINT8 Reserved1[8]; ///< Reserved
+} CRAT_CACHE;
+
+/// Flags field of the CRAT TLB Affinity structure
+typedef struct {
+ UINT32 Enabled:1; ///< Enabled
+ UINT32 DataTLB:1; ///< 1 if TLB includes translation information for data.
+ UINT32 InstructionTLB:1; ///< 1 if TLB includes translation information for instructions.
+ UINT32 CpuTLB:1; ///< 1 if TLB is part of CPU functionality
+ UINT32 SimdTLB:1; ///< 1 if TLB is part of SIMD functionality
+ UINT32 TLB4KBase256:1; ///< 1 if value in table is factored by 256 to get number of 4K entries
+ UINT32 :1; ///< Reserved
+ UINT32 TLB2MBase256:1; ///< 1 if value in table is factored by 256 to get number of 2M entries
+ UINT32 :1; ///< Reserved
+ UINT32 TLB1GBase256:1; ///< 1 if value in table is factored by 256 to get number of 1G entries
+ UINT32 :22; ///< Reserved
+} CRAT_TLB_FLAG;
+
+/// CRAT TLB Affinity Structure
+typedef struct {
+ UINT8 Type; ///< 3 - CRAT TLB Affinity Structure
+ UINT8 Length; ///< 64
+ UINT16 Reserved; ///< Reserved
+ CRAT_TLB_FLAG Flags; ///< Flags - TLB Affinity Structure. Indicates whether the TLB is enabled and defined
+ UINT32 ProcessorIdLow; ///< Low value of a logical processor which includes this component.
+ UINT8 SiblingMap[32]; ///< Bitmask of Processor Id sharing this component. 1 bit per logical processor
+ UINT32 TlbLevel; ///< Integer representing level: 1, 2, 3, 4, etc.
+ UINT8 DataTlbAssociativity2MB; ///< Data TLB associativity for 2MB pages
+ ///< The associativity fields are encoded as follows:
+ ///< 00h: Reserved.
+ ///< 01h: Direct mapped.
+ ///< 02h-FEh: Associativity. (e.g., 04h = 4-way associative.)
+ ///< FFh: Fully associative.
+ UINT8 DataTlbSize2MB; ///< Data TLB number of entries for 2MB.
+ UINT8 InstructionTlbAssociativity2MB; ///< Instruction TLB associativity for 2MB pages
+ ///< The associativity fields are encoded as follows:
+ ///< 00h: Reserved.
+ ///< 01h: Direct mapped.
+ ///< 02h-FEh: Associativity. (e.g., 04h = 4-way associative.)
+ ///< FFh: Fully associative.
+ UINT8 InstructionTlbSize2MB; ///< Instruction TLB number of entries for 2MB pages.
+ UINT8 DataTlbAssociativity4K; ///< Data TLB Associativity for 4KB pages
+ UINT8 DataTlbSize4K; ///< Data TLB number of entries for 4KB pages
+ UINT8 InstructionTlbAssociativity4K; ///< Instruction TLB Associativity for 4KB pages
+ UINT8 InstructionTlbSize4K; ///< Instruction TLB number of entries for 4KB pages
+ UINT8 DataTlbAssociativity1G; ///< Data TLB Associativity for 1GB pages
+ UINT8 DataTlbSize1G; ///< Data TLB number of entries for 1GB pages
+ UINT8 InstructionTlbAssociativity1G; ///< Instruction TLB Associativity for 1GB pages
+ UINT8 InstructionTlbSize1G; ///< Instruction TLB number of entries for 1GB pages
+ UINT8 Reserved1[4]; ///< Reserved
+} CRAT_TLB;
+
+/// Flags field of the CRAT FPU Affinity structure
+typedef struct {
+ UINT32 Enabled:1; ///< Enabled
+ UINT32 :31; ///< Reserved
+} CRAT_FPU_FLAG;
+
+/// CRAT FPU Affinity Structure
+typedef struct {
+ UINT8 Type; ///< 4 - CRAT FPU Affinity Structure
+ UINT8 Length; ///< 64
+ UINT16 Reserved; ///< Reserved
+ CRAT_FPU_FLAG Flags; ///< Flags - FPU Affinity Structure. Indicates whether the region of FPU affinity structure is enabled and defined
+ UINT32 ProcessorIdLow; ///< Low value of a logical processor which includes this component.
+ UINT8 SiblingMap[32]; ///< Bitmask of Processor Id sharing this component. 1 bit per logical processor
+ UINT32 FPUSize; ///< Product specific
+ UINT8 Reserved1[16]; ///< Reserved
+} CRAT_FPU;
+
+/// Flags field of the CRAT IO Affinity structure
+typedef struct {
+ UINT32 Enabled:1; ///< Enabled
+ UINT32 Coherency:1; ///< If set, IO interface supports coherent transactions (natively or through protocol extensions)
+ UINT32 :30; ///< Reserved
+} CRAT_IO_FLAG;
+
+/// CRAT IO Affinity Structure
+typedef struct {
+ UINT8 Type; ///< 5 - CRAT IO Affinity Structure
+ UINT8 Length; ///< 64
+ UINT16 Reserved; ///< Reserved
+ CRAT_IO_FLAG Flags; ///< Flags - IO Affinity Structure. Indicates whether the region of IO affinity structure is enabled and defined.
+ UINT32 ProximityDomainFrom; ///< Integer that represents the proximity domain to which the IO Interface belongs to
+ UINT32 ProximityDomainTo; ///< Integer that represents the other proximity domain to which the IO Interface belongs to
+ UINT8 IoType; ///< IO Interface type. Values defined are
+ ///< 0: Undefined
+ ///< 1: Hypertransport
+ ///< 2: PCI Express
+ ///< 3: Other (e.g. internal)
+ ///< 4-255: Reserved
+ UINT8 VersionMajor; ///< Major version of the Bus interface
+ UINT16 VersionMinor; ///< Minor version of the Bus interface ((optional)
+ UINT32 MinimumLatency; ///< Cost of time to transfer, described in nanoseconds.
+ UINT32 MaximumLatency; ///< Cost of time to transfer, described in nanoseconds.
+ UINT32 MinimumBandwidth; ///< Minimum interface Bandwidth in MB/s
+ UINT32 MaximumBandwidth; ///< Maximum interface Bandwidth in MB/s
+ UINT32 RecommendedTransferSize; ///< Recommended transfer size to reach maximum interface bandwidth in Bytes
+ UINT8 Reserved1[24]; ///< Reserved
+} CRAT_IO;
+
+#define CRAT_MAX_LENGTH 0x800ul ///< Reserve 2K for CRAT
+/// CRAT entry type
+typedef enum {
+ CRAT_TYPE_HSA_PROC_UNIT = 0, ///< 0 - CRAT HSA Processing Unit Structure
+ CRAT_TYPE_MEMORY, ///< 1 - CRAT Memory Affinity Structure
+ CRAT_TYPE_CACHE, ///< 2 - CRAT Cache Affinity Structure
+ CRAT_TYPE_TLB, ///< 3 - CRAT TLB Affinity Structure
+ CRAT_TYPE_FPU, ///< 4 - CRAT FPU Affinity Structure
+ CRAT_TYPE_IO, ///< 5 - CRAT IO Affinity Structure
+} CRAT_ENTRY_TYPE;
+
+/*----------------------------------------------------------------------------------------
+ * F U N C T I O N P R O T O T Y P E
+ *----------------------------------------------------------------------------------------
+ */
+
+AGESA_STATUS
+AmdCpuLate (
+ IN AMD_CONFIG_PARAMS *StdHeader,
+ IN PLATFORM_CONFIGURATION *PlatformConfig
+ );
+
+AGESA_STATUS
+CreateAcpiWhea (
+ IN OUT AMD_CONFIG_PARAMS *StdHeader,
+ IN OUT VOID **WheaMcePtr,
+ IN OUT VOID **WheaCmcPtr
+ );
+
+AGESA_STATUS
+CreateDmiRecords (
+ IN OUT AMD_CONFIG_PARAMS *StdHeader,
+ IN OUT DMI_INFO **DmiTable
+ );
+
+AGESA_STATUS
+GetType4Type7Info (
+ IN AP_EXE_PARAMS *ApExeParams
+ );
+
+VOID
+DmiGetT4ProcFamilyFromBrandId (
+ IN OUT UINT8 *T4ProcFamily,
+ IN PROC_FAMILY_TABLE *CpuDmiProcFamilyTable,
+ IN CPU_TYPE_INFO *CpuInfo,
+ IN AMD_CONFIG_PARAMS *StdHeader
+ );
+
+VOID
+GetNameString (
+ IN OUT CHAR8 *String,
+ IN OUT AMD_CONFIG_PARAMS *StdHeader
+ );
+
+BOOLEAN
+IsSourceStrContainTargetStr (
+ IN OUT CHAR8 *SourceStr,
+ IN OUT CONST CHAR8 *TargetStr,
+ IN OUT AMD_CONFIG_PARAMS *StdHeader
+ );
+
+AGESA_STATUS
+CreateAcpiCrat (
+ IN OUT AMD_CONFIG_PARAMS *StdHeader,
+ OUT VOID **CratPtr
+ );
+
+AGESA_STATUS
+CreateAcpiCdit (
+ IN OUT AMD_CONFIG_PARAMS *StdHeader,
+ IN PLATFORM_CONFIGURATION *PlatformConfig,
+ OUT VOID **CditPtr
+ );
+
+AGESA_STATUS
+CreateAcpiSrat (
+ IN OUT AMD_CONFIG_PARAMS *StdHeader,
+ IN OUT VOID **SratPtr
+ );
+
+AGESA_STATUS
+CreateAcpiSlit (
+ IN OUT AMD_CONFIG_PARAMS *StdHeader,
+ IN PLATFORM_CONFIGURATION *PlatformConfig,
+ IN OUT VOID **SlitPtr
+ );
+
+VOID
+ChecksumAcpiTable (
+ IN OUT ACPI_TABLE_HEADER *Table,
+ IN AMD_CONFIG_PARAMS *StdHeader
+ );
+
+AGESA_STATUS
+RunLateApTaskOnAllAPs (
+ IN AP_EXE_PARAMS *ApParams,
+ IN AMD_CONFIG_PARAMS *StdHeader
+ );
+
+AGESA_STATUS
+RunLateApTaskOnAllCore0s (
+ IN AP_EXE_PARAMS *ApParams,
+ IN AMD_CONFIG_PARAMS *StdHeader
+ );
+
+#endif // _CPU_LATE_INIT_H_
diff --git a/src/vendorcode/amd/pi/00730F01/Proc/CPU/cpuRegisters.h b/src/vendorcode/amd/pi/00730F01/Proc/CPU/cpuRegisters.h
new file mode 100644
index 0000000..601a643
--- /dev/null
+++ b/src/vendorcode/amd/pi/00730F01/Proc/CPU/cpuRegisters.h
@@ -0,0 +1,467 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD CPU Register Table Related Functions
+ *
+ * Contains the definition of the CPU CPUID MSRs and PCI registers with BKDG recommended values
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: CPU
+ * @e \$Revision: 282320 $ @e \$Date: 2014-01-09 20:13:34 -0600 (Thu, 09 Jan 2014) $
+ *
+ */
+/*****************************************************************************
+ *
+ * Copyright (c) 2008 - 2014, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ***************************************************************************/
+
+#ifndef _CPU_REGISTERS_H_
+#define _CPU_REGISTERS_H_
+
+#include "cpuFamRegisters.h"
+/*
+ *--------------------------------------------------------------
+ *
+ * M O D U L E S U S E D
+ *
+ *---------------------------------------------------------------
+ */
+
+/*
+ *--------------------------------------------------------------
+ *
+ * D E F I N I T I O N S / M A C R O S
+ *
+ *---------------------------------------------------------------
+ */
+
+#undef BIT0
+#undef BIT1
+#undef BIT2
+#undef BIT3
+#undef BIT4
+#undef BIT5
+#undef BIT6
+#undef BIT7
+#undef BIT8
+#undef BIT9
+#undef BIT10
+#undef BIT10
+#undef BIT11
+#undef BIT12
+#undef BIT13
+#undef BIT14
+#undef BIT15
+#undef BIT16
+#undef BIT17
+#undef BIT18
+#undef BIT19
+#undef BIT20
+#undef BIT21
+#undef BIT22
+#undef BIT23
+#undef BIT24
+#undef BIT25
+#undef BIT26
+#undef BIT27
+#undef BIT28
+#undef BIT29
+#undef BIT30
+#undef BIT31
+#undef BIT32
+#undef BIT33
+#undef BIT34
+#undef BIT35
+#undef BIT36
+#undef BIT37
+#undef BIT38
+#undef BIT39
+#undef BIT40
+#undef BIT41
+#undef BIT42
+#undef BIT43
+#undef BIT44
+#undef BIT45
+#undef BIT46
+#undef BIT47
+#undef BIT48
+#undef BIT49
+#undef BIT40
+#undef BIT41
+#undef BIT42
+#undef BIT43
+#undef BIT44
+#undef BIT45
+#undef BIT46
+#undef BIT47
+#undef BIT48
+#undef BIT49
+#undef BIT50
+#undef BIT51
+#undef BIT52
+#undef BIT53
+#undef BIT54
+#undef BIT55
+#undef BIT56
+#undef BIT57
+#undef BIT58
+#undef BIT59
+#undef BIT60
+#undef BIT61
+#undef BIT62
+#undef BIT63
+
+#define BIT0 0x0000000000000001ull
+#define BIT1 0x0000000000000002ull
+#define BIT2 0x0000000000000004ull
+#define BIT3 0x0000000000000008ull
+#define BIT4 0x0000000000000010ull
+#define BIT5 0x0000000000000020ull
+#define BIT6 0x0000000000000040ull
+#define BIT7 0x0000000000000080ull
+#define BIT8 0x0000000000000100ull
+#define BIT9 0x0000000000000200ull
+#define BIT10 0x0000000000000400ull
+#define BIT11 0x0000000000000800ull
+#define BIT12 0x0000000000001000ull
+#define BIT13 0x0000000000002000ull
+#define BIT14 0x0000000000004000ull
+#define BIT15 0x0000000000008000ull
+#define BIT16 0x0000000000010000ull
+#define BIT17 0x0000000000020000ull
+#define BIT18 0x0000000000040000ull
+#define BIT19 0x0000000000080000ull
+#define BIT20 0x0000000000100000ull
+#define BIT21 0x0000000000200000ull
+#define BIT22 0x0000000000400000ull
+#define BIT23 0x0000000000800000ull
+#define BIT24 0x0000000001000000ull
+#define BIT25 0x0000000002000000ull
+#define BIT26 0x0000000004000000ull
+#define BIT27 0x0000000008000000ull
+#define BIT28 0x0000000010000000ull
+#define BIT29 0x0000000020000000ull
+#define BIT30 0x0000000040000000ull
+#define BIT31 0x0000000080000000ull
+#define BIT32 0x0000000100000000ull
+#define BIT33 0x0000000200000000ull
+#define BIT34 0x0000000400000000ull
+#define BIT35 0x0000000800000000ull
+#define BIT36 0x0000001000000000ull
+#define BIT37 0x0000002000000000ull
+#define BIT38 0x0000004000000000ull
+#define BIT39 0x0000008000000000ull
+#define BIT40 0x0000010000000000ull
+#define BIT41 0x0000020000000000ull
+#define BIT42 0x0000040000000000ull
+#define BIT43 0x0000080000000000ull
+#define BIT44 0x0000100000000000ull
+#define BIT45 0x0000200000000000ull
+#define BIT46 0x0000400000000000ull
+#define BIT47 0x0000800000000000ull
+#define BIT48 0x0001000000000000ull
+#define BIT49 0x0002000000000000ull
+#define BIT50 0x0004000000000000ull
+#define BIT51 0x0008000000000000ull
+#define BIT52 0x0010000000000000ull
+#define BIT53 0x0020000000000000ull
+#define BIT54 0x0040000000000000ull
+#define BIT55 0x0080000000000000ull
+#define BIT56 0x0100000000000000ull
+#define BIT57 0x0200000000000000ull
+#define BIT58 0x0400000000000000ull
+#define BIT59 0x0800000000000000ull
+#define BIT60 0x1000000000000000ull
+#define BIT61 0x2000000000000000ull
+#define BIT62 0x4000000000000000ull
+#define BIT63 0x8000000000000000ull
+
+/// CPUID related registers
+#define AMD_CPUID_FMF 0x80000001ul // Family Model Features information
+#define AMD_CPUID_APICID_LPC_BID 0x00000001ul // Local APIC ID, Logical Processor Count, Brand ID
+#define AMD_CPUID_L2L3Cache_L2TLB 0x80000006ul
+#define CPUID_ASSOCIATIVITY_DISABLED 0x00
+#define CPUID_ASSOCIATIVITY_1_WAY 0x01
+#define CPUID_ASSOCIATIVITY_2_WAY 0x02
+#define CPUID_ASSOCIATIVITY_4_WAY 0x04
+#define CPUID_ASSOCIATIVITY_8_WAY 0x06
+#define CPUID_ASSOCIATIVITY_16_WAY 0x08
+#define CPUID_ASSOCIATIVITY_32_WAY 0x0A
+#define CPUID_ASSOCIATIVITY_48_WAY 0x0B
+#define CPUID_ASSOCIATIVITY_64_WAY 0x0C
+#define CPUID_ASSOCIATIVITY_96_WAY 0x0D
+#define CPUID_ASSOCIATIVITY_128_WAY 0x0E
+#define CPUID_ASSOCIATIVITY_FULLY 0x0F
+#define AMD_CPUID_TLB_L1Cache 0x80000005ul
+#define AMD_CPUID_L1L2Tlb1GIdentifiers 0x80000019ul
+#define AMD_CPUID_APM 0x80000007ul
+#define LOCAL_APIC_ID 24
+#define LOGICAL_PROCESSOR_COUNT 16
+#define AMD_CPUID_ASIZE_PCCOUNT 0x80000008ul // Address Size, Physical Core Count
+
+/// CPU Logical ID Transfer
+typedef struct {
+ UINT32 RawId; ///< RawID
+ UINT64 LogicalId; ///< LogicalID
+} CPU_LOGICAL_ID_XLAT;
+
+/// Logical CPU ID Table
+typedef struct {
+ IN UINT32 Elements; ///< Number of Elements
+ IN CPU_LOGICAL_ID_XLAT *LogicalIdTable; ///< CPU Logical ID Transfer table Pointer
+} LOGICAL_ID_TABLE;
+
+// MSRs
+// ------------------------
+#define MCG_CTL_P 0x00000100ul // bit 8 for MCG_CTL_P under MSRR
+#define MSR_MCG_CAP 0x00000179ul
+#define DBG_CTL_MSR 0x000001D9ul
+#define MSR_MC0_CTL 0x00000400ul
+#define MSR_MC0_STATUS 0x00000401ul
+#define MSR_MC0_MISC 0x00000403ul
+#define MSR_MC1_MISC 0x00000407ul
+#define MSR_MC2_MISC 0x0000040Bul
+#define MSR_MC4_MISC0 0x00000413ul
+#define MSR_MC5_MISC 0x00000417ul
+#define MSR_MC4_MISC1 0xC0000408ul
+#define MSR_MC5_STATUS 0x00000415ul
+#define MSR_MC6_STATUS 0x00000419ul
+
+#define MSR_APIC_BAR 0x0000001Bul
+#define MSR_PATCH_LEVEL 0x0000008Bul
+
+#define CPUID_LONG_MODE_ADDR 0x80000008ul
+
+#define MSR_EXTENDED_FEATURE_EN 0xC0000080ul
+#define MSR_MC_MISC_LINK_THRESHOLD 0xC0000408ul
+#define MSR_MC_MISC_L3_THRESHOLD 0xC0000409ul
+#define MSR_PATCH_LOADER 0xC0010020ul
+
+/// Patch Loader Register
+typedef struct {
+ UINT64 PatchBase:32; ///< Linear address of patch header address block
+ UINT64 SBZ:32; ///< Should be zero
+} PATCH_LOADER_MSR;
+
+#define MSR_SYS_CFG 0xC0010010ul // SYSCFG - F15 Shared
+#define MSR_TOM2 0xC001001Dul // TOP_MEM2 - F15 Shared
+#define MSR_MC0_CTL_MASK 0xC0010044ul // MC0 Control Mask
+#define MSR_MC1_CTL_MASK 0xC0010045ul // MC1 Control Mask
+#define MSR_MC2_CTL_MASK 0xC0010046ul // MC2 Control Mask
+#define MSR_MC4_CTL_MASK 0xC0010048ul // MC4 Control Mask
+
+#define MSR_CPUID_FEATS 0xC0011004ul // CPUID Features
+#define MSR_CPUID_EXT_FEATS 0xC0011005ul // CPUID Extended Features
+#define MSR_HDT_CFG 0xC001100Aul
+#define MSR_HWCR 0xC0010015ul
+#define MSR_NB_CFG 0xC001001Ful // NB Config
+#define CPU_WDT_CFG 0xC0010074ul
+#define ENABLE_CF8_EXT_CFG 0x00004000ul // [46]
+#define INIT_APIC_CPUID_LO 0x00400000ul // [54]
+#define MSR_CU_SPMCTL 0xC0010281ul
+#define MSR_CpuWdtCfg 0xC0010074ul // CPU Watchdog Timer
+#define MSR_LS_CFG 0xC0011020ul
+#define MSR_IC_CFG 0xC0011021ul // ICache Config - F15 Shared
+#define MSR_DC_CFG 0xC0011022ul
+#define MSR_ME_CFG 0xC0011029ul
+#define MSR_BU_CFG 0xC0011023ul
+#define MSR_CU_CFG 0xC0011023ul // F15 Shared
+#define MSR_DE_CFG 0xC0011029ul // F15 Shared
+#define MSR_BU_CFG2 0xC001102Aul
+#define MSR_CU_CFG2 0xC001102Aul // F15 Shared
+#define MSR_BU_CFG3 0xC001102Bul
+#define MSR_CU_CFG3 0xC001102Bul // F15 Shared
+#define MSR_LS_CFG2 0xC001102Dul
+#define MSR_CU_PFTCFG 0xC001102Ful
+#define MSR_IBS_OP_DATA3 0xC0011037ul
+#define MSR_C001_1070 0xC0011070ul // F15 Shared
+#define MSR_L2I_CFG 0xC00110A0ul // F16 shared
+#define MSR_CU_CBBCFG 0xC00110A1ul // F15 CZ
+
+
+#define MSR_CPUID_NAME_STRING0 0xC0010030ul // First CPUID namestring register
+#define MSR_CPUID_NAME_STRING1 0xC0010031ul
+#define MSR_CPUID_NAME_STRING2 0XC0010032ul
+#define MSR_CPUID_NAME_STRING3 0xC0010033ul
+#define MSR_CPUID_NAME_STRING4 0xC0010034ul
+#define MSR_CPUID_NAME_STRING5 0xC0010035ul // Last CPUID namestring register
+#define MSR_MMIO_Cfg_Base 0xC0010058ul // MMIO Configuration Base Address Register
+#define MSR_BIST 0xC0010060ul // BIST Results register
+#define MSR_OSVW_ID_Length 0xC0010140ul
+#define MSR_OSVW_Status 0xC0010141ul
+#define MSR_NB_PERF_CTL0 0xC0010240ul
+#define MSR_NB_PERF_CTR0 0xC0010241ul
+#define MSR_NB_PERF_CTL1 0xC0010242ul
+#define MSR_NB_PERF_CTR1 0xC0010243ul
+#define MSR_NB_PERF_CTL2 0xC0010244ul
+#define MSR_NB_PERF_CTR2 0xC0010245ul
+#define MSR_NB_PERF_CTL3 0xC0010246ul
+#define MSR_NB_PERF_CTR3 0xC0010247ul
+#define CU_SPMCTL 0xC0010281ul // Streaming Performance Monitor Control
+#define MSR_PERF_CONTROL3 0xC0010003ul // Performance control register number 3
+#define MSR_PERF_COUNTER3 0xC0010007ul // Performance counter register number 3
+#define PERF_RESERVE_BIT_MASK 0x030FFFDFFFFFull // Mask of the Performance control Reserve bits
+#define PERF_CAR_CORRUPTION_EVENT 0x040040F0E2ul // Configure the controller to capture the
+ // CAR Corruption
+// FUNC_0 registers
+// ----------------
+#define LINK_INIT_CTRL 0x6C
+#define LINK_INIT_CTRL_REQ_DIS 0x02 // [1] = ReqDis
+#define LINK_INIT_COLD_RST_DET BIT4
+#define LINK_INIT_BIOS_RST_DET_0 BIT5
+#define LINK_INIT_BIOS_RST_DET_1 BIT9
+#define LINK_INIT_BIOS_RST_DET_2 BIT10
+#define LINK_INIT_BIOS_RST_DET BIT9 | BIT10
+#define EXTENDED_NODE_ID 0x160
+
+#define CORE_CTRL 0x1DC
+#define CORE_CTRL_CORE1_EN 0x00000002ul
+#define CORE_CTRL_CORE2_EN 0x00000004ul
+#define CORE_CTRL_CORE3_EN 0x00000008ul
+#define CORE_CTRL_CORE4_EN 0x00000010ul
+#define CORE_CTRL_CORE5_EN 0x00000020ul
+#define CORE_CTRL_CORE6_EN 0x00000040ul
+#define CORE_CTRL_CORE7_EN 0x00000080ul
+#define CORE_CTRL_CORE8_EN 0x00000100ul
+#define CORE_CTRL_CORE9_EN 0x00000200ul
+
+// FUNC_3 registers
+// ----------------
+#define HARDWARE_THERMAL_CTRL_REG 0x64
+#define SOFTWARE_THERMAL_CTRL_REG 0x68
+
+#define ACPI_PSC_0_REG 0x80 // ACPI Power State Control Registers
+#define ACPI_PSC_4_REG 0x84
+
+#define NB_CFG_HIGH_REG 0x8C
+#define POWER_CTRL_MISCELLANEOUS_REG 0xA0
+#define CLOCK_POWER_TIMING_CTRL2_REG 0xDC
+#define NORTH_BRIDGE_CAPABILITIES_REG 0xE8
+#define MULTI_NODE_CPU 29
+#define CPUID_FMR 0xFC // Family / Model registers
+#define DOWNCORE_CTRL 0x190 // Downcore Control Register
+
+#define LINK_TO_XCS_TOKEN_COUNT_REG_3X148 0x148
+#define REG_HT4_PHY_OFFSET_BASE_4X180 0x180
+#define REG_HT4_PHY_DATA_PORT_BASE_4X184 0x184
+
+// FUNC_5 registers
+// ----------------
+#define COMPUTE_UNIT_STATUS 0x80
+#define NORTH_BRIDGE_CAPABILITIES_2_REG 0x84
+
+
+// Misc. defines.
+#define PCI_DEV_BASE 24
+
+#define CPUID_STEPPING_MASK 0x0000000Ful
+#define CPUID_BASE_MODEL_MASK 0x000000F0ul
+#define CPUID_BASE_FAMILY_MASK 0x00000F00ul
+#define CPUID_EXT_MODEL_MASK 0x000F0000ul
+#define CPUID_EXT_FAMILY_MASK 0x0FF00000ul
+
+#define TN_SOCKET_FP2 0
+#define TN_SOCKET_FS1 1
+#define TN_SOCKET_FM2 2
+#define KV_SOCKET_FP3 0
+#define KV_SOCKET_FM2r2 1
+#define CZ_SOCKET_FP4 0 /// @todo : update value when BKDG updates
+#define CZ_SOCKET_FM2r2 1 /// @todo : update value when BKDG updates
+#define KB_SOCKET_FT3 0
+#define KB_SOCKET_FS1b 1
+#define ML_SOCKET_FT3b 0
+#define SOCKET_IGNORE 0xF
+
+#define LAPIC_BASE_ADDR_MASK 0x0000FFFFFFFFF000ull
+#define APIC_EXT_BRDCST_MASK 0x000E0000ul
+#define APIC_ENABLE_BIT 0x00000800ul
+#define LOCAL_APIC_ADDR 0xFEE00000ul
+#define INT_CMD_REG_LO 0x300
+#define INT_CMD_REG_HI 0x310
+#define REMOTE_MSG_REG 0x380
+#define REMOTE_READ_REG 0xC0
+#define APIC_ID_REG 0x20
+#define APIC20_ApicId 24
+#define CMD_REG_TO_READ_DATA 0x338
+
+#define MAX_CORE_ID_SIZE 8
+#define MAX_CORE_ID_MASK ((1 << MAX_CORE_ID_SIZE) - 1)
+
+/*-------------------------
+ * Default definitions
+ *-------------------------
+ */
+#define DOWNCORE_MASK_SINGLE 0xFFFFFFFEul
+#define DOWNCORE_MASK_DUAL 0xFFFFFFFCul
+#define DOWNCORE_MASK_TRI 0xFFFFFFF8ul
+#define DOWNCORE_MASK_FOUR 0xFFFFFFF0ul
+#define DOWNCORE_MASK_FIVE 0xFFFFFFE0ul
+#define DOWNCORE_MASK_SIX 0xFFFFFFC0ul
+#define DOWNCORE_MASK_SEVEN 0xFFFFFF80ul
+#define DOWNCORE_MASK_EIGHT 0xFFFFFF00ul
+#define DOWNCORE_MASK_TEN 0xFFFFFC00ul
+#define DOWNCORE_MASK_TWELVE 0xFFFFF000ul
+#define DOWNCORE_MASK_FOURTEEN 0xFFFFC000ul
+#define DOWNCORE_MASK_DUAL_COMPUTE_UNIT 0xFFFFFFFAul
+#define DOWNCORE_MASK_TRI_COMPUTE_UNIT 0xFFFFFFEAul
+#define DOWNCORE_MASK_FOUR_COMPUTE_UNIT 0xFFFFFFAAul
+#define DOWNCORE_MASK_FIVE_COMPUTE_UNIT 0xFFFFFEAAul
+#define DOWNCORE_MASK_SIX_COMPUTE_UNIT 0xFFFFFAAAul
+#define DOWNCORE_MASK_SEVEN_COMPUTE_UNIT 0xFFFFEAAAul
+#define DOWNCORE_MASK_EIGHT_COMPUTE_UNIT 0xFFFFAAAAul
+
+#define DELIVERY_STATUS BIT13
+#define REMOTE_READ_STAT_MASK 0x00030000ul
+#define REMOTE_DELIVERY_PENDING 0x00010000ul
+#define REMOTE_DELIVERY_DONE 0x00020000ul
+
+/*
+ * --------------------------------------------------------------------------------------
+ *
+ * D E F I N E S / T Y P E D E F S / S T R U C T U R E S
+ *
+ * --------------------------------------------------------------------------------------
+ */
+
+/// CpuEarly param type
+typedef struct {
+ IN UINT8 MemInitPState; ///< Pstate value during memory initial
+ IN PLATFORM_CONFIGURATION PlatformConfig; ///< Runtime configurable user options
+} AMD_CPU_EARLY_PARAMS;
+
+/// CPUID
+typedef enum {
+ REG_EAX, ///< EAX
+ REG_EBX, ///< EBX
+ REG_ECX, ///< ECX
+ REG_EDX ///< EDX
+} CPUID_REG;
+
+#endif // _CPU_REGISTERS_H_
+
diff --git a/src/vendorcode/amd/pi/00730F01/Proc/CPU/heapManager.h b/src/vendorcode/amd/pi/00730F01/Proc/CPU/heapManager.h
new file mode 100644
index 0000000..7a278ef
--- /dev/null
+++ b/src/vendorcode/amd/pi/00730F01/Proc/CPU/heapManager.h
@@ -0,0 +1,258 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD Heap Manager and Heap Allocation APIs, and related functions.
+ *
+ * Contains code that initialize, maintain, and allocate the heap space.
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: CPU
+ * @e \$Revision: 281178 $ @e \$Date: 2013-12-18 02:14:15 -0600 (Wed, 18 Dec 2013) $
+ *
+ */
+/*****************************************************************************
+ *
+ * Copyright (c) 2008 - 2014, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ***************************************************************************/
+
+#ifndef _HEAP_MANAGER_H_
+#define _HEAP_MANAGER_H_
+
+/*---------------------------------------------------------------------------------------
+ * M I X E D (Definitions And Macros / Typedefs, Structures, Enums)
+ *---------------------------------------------------------------------------------------
+ */
+
+
+/*---------------------------------------------------------------------------------------
+ * D E F I N I T I O N S A N D M A C R O S
+ *---------------------------------------------------------------------------------------
+ */
+#define AMD_MTRR_VARIABLE_BASE0 0x200
+#define AMD_MTRR_VARIABLE_HEAP_BASE 0x20A
+#define AMD_MTRR_VARIABLE_HEAP_MASK (AMD_MTRR_VARIABLE_HEAP_BASE + 1)
+
+#define AMD_HEAP_START_ADDRESS 0x400000ul
+#define AMD_HEAP_REGION_END_ADDRESS 0xBFFFFFul
+#define AMD_HEAP_SIZE_PER_CORE 0x010000ul
+#define AMD_HEAP_INVALID_HEAP_OFFSET 0xFFFFFFFFul
+#define AMD_HEAP_MTRR_MASK ((0xFFFFFFFFFFFFF800ull & (((UINT64)AMD_HEAP_SIZE_PER_CORE ^ (-1)) + 1)) | 0x800)
+#define AMD_HEAP_SIZE_DWORD_PER_CORE (AMD_HEAP_SIZE_PER_CORE / 4)
+
+#define AMD_TEMP_TOM 0x20000000ul // Set TOM to 512 MB (temporary value)
+#define AMD_VAR_MTRR_ENABLE_BIT 0x100000ul // bit 20
+
+#define AMD_HEAP_RAM_ADDRESS 0xB0000ul
+
+#define HEAP_SIGNATURE_VALID 0x50414548ul // Signature: 'HEAP'
+#define HEAP_SIGNATURE_INVALID 0x00000000ul // Signature cleared
+
+///Heap Manager Life cycle
+#define HEAP_DO_NOT_EXIST_YET 1
+#define HEAP_LOCAL_CACHE 2
+#define HEAP_TEMP_MEM 3
+#define HEAP_SYSTEM_MEM 4
+#define HEAP_DO_NOT_EXIST_ANYMORE 5
+#define HEAP_S3_RESUME 6
+#define HEAP_RUNTIME_SYSTEM_MEM 7
+
+///Heap callout
+#define HEAP_CALLOUT_BOOTTIME 0
+#define HEAP_CALLOUT_RUNTIME 1
+
+#define AMD_MTRR_FIX64k_00000 0x250
+#define AMD_MTRR_FIX16k_80000 0x258
+#define AMD_MTRR_FIX16k_A0000 0x259
+#define AMD_MTRR_FIX4k_C0000 0x268
+#define AMD_MTRR_FIX4k_C8000 0x269
+#define AMD_MTRR_FIX4k_D0000 0x26A
+#define AMD_MTRR_FIX4k_D8000 0x26B
+#define AMD_MTRR_FIX4k_E0000 0x26C
+#define AMD_MTRR_FIX4k_E8000 0x26D
+#define AMD_MTRR_FIX4k_F0000 0x26E
+#define AMD_MTRR_FIX4k_F8000 0x26F
+
+#define AMD_MTRR_FIX64K_WB_DRAM 0x1E
+#define AMD_MTRR_FIX64K_WT_DRAM 0x1C
+#define AMD_MTRR_FIX64K_UC_DRAM 0x18
+#define AMD_MTRR_FIX16K_WB_DRAM 0x1E1E1E1E1E1E1E1Eull
+#define AMD_MTRR_FIX16K_WT_DRAM 0x1C1C1C1C1C1C1C1Cull
+#define AMD_MTRR_FIX16K_UC_DRAM 0x1818181818181818ull
+#define AMD_MTRR_FIX4K_WB_DRAM 0x1E1E1E1E1E1E1E1Eull
+#define AMD_MTRR_FIX4K_WT_DRAM 0x1C1C1C1C1C1C1C1Cull
+#define AMD_MTRR_FIX4K_UC_DRAM 0x1818181818181818ull
+
+/*---------------------------------------------------------------------------------------
+ * T Y P E D E F S, S T R U C T U R E S, E N U M S
+ *---------------------------------------------------------------------------------------
+ */
+/// Allocate Heap Parameters
+typedef struct _ALLOCATE_HEAP_PARAMS {
+ UINT32 RequestedBufferSize; ///< Size of buffer.
+ UINT32 BufferHandle; ///< An unique ID of buffer.
+ UINT8 Persist; ///< A flag. If marked, to be stored and passed to AmdInitLate.
+ UINT8 *BufferPtr; ///< Pointer to buffer.
+} ALLOCATE_HEAP_PARAMS;
+
+/// Locate Heap Parameters
+typedef struct _LOCATE_HEAP_PTR {
+ UINT32 BufferHandle; ///< An unique ID of buffer.
+ UINT32 BufferSize; ///< Data buffer size.
+ UINT8 *BufferPtr; ///< Pointer to buffer.
+} LOCATE_HEAP_PTR;
+
+/// Heap Node Header
+typedef struct _BUFFER_NODE {
+ UINT32 BufferHandle; ///< An unique ID of buffer.
+ UINT32 BufferSize; ///< Size of buffer.
+ UINT8 Persist; ///< A flag. If marked, to be stored and passed to AmdInitLate.
+ UINT8 PadSize; ///< Size of pad.
+ UINT32 OffsetOfNextNode; ///< Offset of next node (relative to the base).
+} BUFFER_NODE;
+
+/// Heap Manager
+typedef struct _HEAP_MANAGER {
+ UINT32 Signature; ///< a signature to indicate if the heap is valid.
+ UINT32 UsedSize; ///< Used size of heap.
+ UINT32 FirstActiveBufferOffset; ///< Offset of the first active buffer.
+ UINT32 FirstFreeSpaceOffset; ///< Offset of the first free space.
+} HEAP_MANAGER;
+
+/// AGESA Buffer Handles (These are reserved)
+typedef enum {
+ AMD_INIT_RESET_HANDLE = 0x000A000, ///< Assign 0x000A000 buffer handle to AmdInitReset routine.
+ AMD_INIT_EARLY_HANDLE, ///< Assign 0x000A001 buffer handle to AmdInitEarly routine.
+ AMD_INIT_POST_HANDLE, ///< Assign 0x000A002 buffer handle to AmdInitPost routine.
+ AMD_INIT_ENV_HANDLE, ///< Assign 0x000A003 buffer handle to AmdInitEnv routine.
+ AMD_INIT_MID_HANDLE, ///< Assign 0x000A004 buffer handle to AmdInitMid routine.
+ AMD_INIT_LATE_HANDLE, ///< Assign 0x000A005 buffer handle to AmdInitLate routine.
+ AMD_INIT_RESUME_HANDLE, ///< Assign 0x000A006 buffer handle to AmdInitResume routine.
+ AMD_LATE_RUN_AP_TASK_HANDLE, ///< Assign 0x000A007 buffer handle to AmdLateRunApTask routine.
+ AMD_S3_SAVE_HANDLE, ///< Assign 0x000A008 buffer handle to AmdS3Save routine.
+ AMD_S3_LATE_RESTORE_HANDLE, ///< Assign 0x000A009 buffer handle to AmdS3LateRestore routine.
+ AMD_S3_SCRIPT_SAVE_TABLE_HANDLE, ///< Assign 0x000A00A buffer handle to be used for S3 save table
+ AMD_S3_SCRIPT_TEMP_BUFFER_HANDLE, ///< Assign 0x000A00B buffer handle to be used for S3 save table
+ AMD_CPU_AP_TASKING_HANDLE, ///< Assign 0x000A00C buffer handle to AP tasking input parameters.
+ AMD_REC_MEM_SOCKET_HANDLE, ///< Assign 0x000A00D buffer handle to save socket with memory in memory recovery mode.
+ AMD_MEM_AUTO_HANDLE, ///< Assign 0x000A00E buffer handle to AmdMemAuto routine.
+ AMD_MEM_SPD_HANDLE, ///< Assign 0x000A00F buffer handle to AmdMemSpd routine.
+ AMD_MEM_DATA_HANDLE, ///< Assign 0x000A010 buffer handle to MemData
+ AMD_MEM_TRAIN_BUFFER_HANDLE, ///< Assign 0x000A011 buffer handle to allocate buffer for training
+ AMD_MEM_S3_DATA_HANDLE, ///< Assign 0x000A012 buffer handle to special case register for S3
+ AMD_MEM_S3_NB_HANDLE, ///< Assign 0x000A013 buffer handle to NB block for S3
+ AMD_MEM_S3_MR0_DATA_HANDLE, ///< Assign 0x000A014 buffer handle to MR0 data block for S3
+ AMD_UMA_INFO_HANDLE, ///< Assign 0x000A015 buffer handle to be used for Uma information
+ AMD_DMI_MEM_DEV_INFO_HANDLE, ///< Assign 0x000A016 buffer handle to DMI Type16 17 19 20 information
+ EVENT_LOG_BUFFER_HANDLE, ///< Assign 0x000A017 buffer handle to Event Log
+ IDS_CONTROL_HANDLE, ///< Assign 0x000A018 buffer handle to AmdIds routine.
+ IDS_HDT_OUT_BUFFER_HANDLE, ///< Assign 0x000A019 buffer handle to be used for HDTOUT support.
+ IDS_CHECK_POINT_PERF_HANDLE, ///< Assign 0x000A01A buffer handle to Performance analysis
+ AMD_PCIE_COMPLEX_DATA_HANDLE, ///< Assign 0x000A01B buffer handle to be used for PCIe support
+ AMD_MEM_SYS_DATA_HANDLE, ///< Assign 0x000A01C buffer handle to be used for memory data structure
+ AMD_GNB_SMU_CONFIG_HANDLE, ///< Assign 0x000A01D buffer handle to be used for GNB SMU configuration
+ AMD_PP_FUSE_TABLE_HANDLE, ///< Assign 0x000A01E buffer handle to be used for TT fuse table
+ AMD_GFX_PLATFORM_CONFIG_HANDLE, ///< Assign 0x000A01F buffer handle to be used for Gfx platform configuration
+ AMD_GNB_TEMP_DATA_HANDLE, ///< Assign 0x000A020 buffer handle for GNB general purpose data block
+ AMD_MEM_2D_RDQS_HANDLE, ///< Assign 0x000A021 buffer handle for 2D training
+ AMD_MEM_2D_RD_WR_HANDLE, ///< Assign 0x000A022 buffer handle for 2D Read/Write training
+ AMD_GNB_IOMMU_SCRATCH_MEM_HANDLE, ///< Assign 0x000A023 buffer handle to be used for GNB IOMMU scratch memory
+ AMD_MEM_S3_SAVE_HANDLE, ///< Assign 0x000A024 buffer handle for memory data saved right after memory init
+ AMD_MEM_2D_RDQS_RIM_HANDLE, ///< Assign 0x000A025 buffer handle for 2D training Eye RIM Search
+ AMD_MEM_2D_RD_WR_RIM_HANDLE, ///< Assign 0x000A026 buffer handle for 2D Read/Write training Eye RIM Search
+ AMD_CPU_NB_PSTATE_FIXUP_HANDLE, ///< Assign 0x000A027 buffer handle for an NB P-state workaround
+ AMD_MEM_CRAT_INFO_BUFFER_HANDLE, ///< Assign 0x000A028 buffer handle for CRAT Memory affinity component structure
+ AMD_SKIP_MEM_S3_SAVE, ///< Assign 0x000A029 buffer handle for the flag to skip memory S3 save
+ AMD_SCS_SMU_RAM_INFO, ///< Assign 0x000A02A buffer handle for keeping the result of SMU SCS service
+ AMD_SCS_HWP0_FREQ, ///< Assign 0x000A02B buffer handler for keeping frequency of HWP0
+ AMD_IS_FEATURE_ENABLED, ///< Assign 0x000A02C buffer handle for keeping the result of IsFeatureEnabled
+ AMD_MEM_DATAEYE_WORK_AREA_HANDLE, ///< Assign 0x000A02D buffer handle for Composite Data Eye Compression Work Area
+ AMD_GNB_SAMU_PATCH_HANDLE, ///< Assign 0x000A02E buffer handle for Samu patch buffer
+ AMD_GNB_SAMU_BOOT_CONTROL_HANDLE, ///< Assign 0x000A02F buffer handle for Samu boot control buffer
+ AMD_GNB_ACP_ENGINE_HANDLE, ///< Assign 0x000A030 buffer handle for GNB ACP engine buffer
+ AMD_MEM_PMU_SRAM_MSG_BLOCK_HANDLE, ///< Assign 0x000A031 buffer handle for PMU SRAM Message Block buffer
+ AMD_MEM_DRAM_CAD_BUS_CONFIG_HANDLE, ///< Assign 0x000A033 buffer handle for DRAM CAD Bus Configuration
+ AMD_GNB_SMU_TABLE_HANDLE, ///< Assign 0x000A034 buffer handle for GNB SMU table buffer
+ AMD_GNB_CRAT_HSA_TABLE_HANDLE, ///< Assign 0x000A035 buffer handle for GNB CRAT HSA unit table
+ AMD_GNB_BUILD_OPTIONS_HANDLE, ///< Assign 0x000A036 buffer handle for GNB build options
+ AMD_MEM_MISC_HANDLES_START = 0x1000000, ///< Reserve 0x1000000 to 0x1FFFFFF buffer handle
+ AMD_MEM_MISC_HANDLES_END = 0x1FFFFFF, ///< miscellaneous memory init tasks' buffers.
+ AMD_HEAP_IN_MAIN_MEMORY_HANDLE = 0x8000000, ///< Assign 0x8000000 to AMD_HEAP_IN_MAIN_MEMORY_HANDLE.
+ SOCKET_DIE_MAP_HANDLE = 0x534F4B54, ///< 'sokt'
+ NODE_ID_MAP_HANDLE = 0x4E4F4445, ///< 'node'
+ HOP_COUNT_TABLE_HANDLE = 0x484F5053, ///< 'hops'
+ AMD_FCH_RESET_DATA_BLOCK_HANDLE = 0x46434852, ///< 'FCHR' Buffer handle for FCH private data block at InitReset
+ AMD_FCH_DATA_BLOCK_HANDLE = 0x46434845, ///< 'FCHE' Buffer handle for FCH private data block at InitEnv
+ IDS_TRAP_TABLE_HANDLE = 0x49524547, ///< 'IREG' Handle for IDS register table
+ IDS_SAVE_IDTR_HANDLE = 0x49445452, ///< 'IDTR'
+ IDS_BSC_IDT_HANDLE = 0x42534349, ///< 'BSCI' BSC Idt table
+ IDS_NV_TO_CMOS_HANDLE = 0x534D4349, ///< 'ICMS' Handle for IDS CMOS save
+ IDS_GRA_HANDLE = 0x41524749, ///< 'IGRA' Handle for IDS GRA save
+ IDS_EXTEND_HANDLE = 0x54584549, ///< 'IEXT' Handle for IDS extend module
+ IDS_TEMP_DATA_HANDLE = 0x504D5459, ///< 'ITMP' Handle for IDS temp data
+} AGESA_BUFFER_HANDLE;
+
+
+/*---------------------------------------------------------------------------------------
+ * F U N C T I O N P R O T O T Y P E
+ *---------------------------------------------------------------------------------------
+ */
+
+AGESA_STATUS
+HeapManagerInit (
+ IN AMD_CONFIG_PARAMS *StdHeader
+ );
+
+AGESA_STATUS
+HeapAllocateBuffer (
+ IN OUT ALLOCATE_HEAP_PARAMS *AllocateHeapParams,
+ IN OUT AMD_CONFIG_PARAMS *StdHeader
+ );
+
+AGESA_STATUS
+HeapDeallocateBuffer (
+ IN UINT32 BufferHandle,
+ IN AMD_CONFIG_PARAMS *StdHeader
+ );
+
+AGESA_STATUS
+HeapLocateBuffer (
+ IN OUT LOCATE_HEAP_PTR *LocateHeap,
+ IN AMD_CONFIG_PARAMS *StdHeader
+ );
+
+UINT64
+HeapGetBaseAddress (
+ IN AMD_CONFIG_PARAMS *StdHeader
+ );
+
+AGESA_STATUS
+EventLogInitialization (
+ IN AMD_CONFIG_PARAMS *StdHeader
+ );
+#endif // _HEAP_MANAGER_H_
diff --git a/src/vendorcode/amd/pi/00730F01/Proc/Common/AmdFch.h b/src/vendorcode/amd/pi/00730F01/Proc/Common/AmdFch.h
new file mode 100644
index 0000000..5edcf35
--- /dev/null
+++ b/src/vendorcode/amd/pi/00730F01/Proc/Common/AmdFch.h
@@ -0,0 +1,63 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * AMD FCH Component
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: FCH
+ * @e \$Revision: 281178 $ @e \$Date: 2013-12-18 02:14:15 -0600 (Wed, 18 Dec 2013) $
+ *
+ */
+/*****************************************************************************
+ *
+ * Copyright (c) 2008 - 2014, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ***************************************************************************/
+
+#ifndef _AMD_FCH_H_
+#define _AMD_FCH_H_
+
+typedef AGESA_STATUS FCH_INIT (IN VOID *DataPtr);
+typedef VOID FCH_TASK_ENTRY (IN VOID *FchCfg);
+
+
+/// FCH API build options
+typedef struct {
+ FCH_INIT *InitReset; ///< InitReset
+ FCH_INIT *InitResetConstructor; ///< InitResetConstructor
+ FCH_INIT *InitEnv; ///< InitEnv
+ FCH_INIT *InitEnvConstructor; ///< InitEnvConstructor
+ FCH_INIT *InitMid; ///< InitMid
+ FCH_INIT *InitMidConstructor; ///< InitMidConstructor
+ FCH_INIT *InitLate; ///< InitLate
+ FCH_INIT *InitLateConstructor; ///< InitLateConstructor
+} BLDOPT_FCH_FUNCTION;
+
+#endif
diff --git a/src/vendorcode/amd/pi/00730F01/Proc/Fch/Common/AcpiLib.h b/src/vendorcode/amd/pi/00730F01/Proc/Fch/Common/AcpiLib.h
new file mode 100644
index 0000000..23fb37c
--- /dev/null
+++ b/src/vendorcode/amd/pi/00730F01/Proc/Fch/Common/AcpiLib.h
@@ -0,0 +1,91 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * FCH ACPI lib
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: FCH
+ * @e \$Revision: 281178 $ @e \$Date: 2013-12-18 02:14:15 -0600 (Wed, 18 Dec 2013) $
+ *
+ */
+/*****************************************************************************
+ *
+ * Copyright (c) 2008 - 2014, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ***************************************************************************/
+
+#ifndef _FCH_ACPILIB_H_
+#define _FCH_ACPILIB_H_
+///
+/// RSDP - ACPI 2.0 table RSDP
+///
+typedef struct _RSDP_HEADER {
+ UINT64 Signature; ///< RSDP signature "RSD PTR"
+ UINT8 CheckSum; ///< checksum of the first 20 bytes
+ UINT8 OEMID[6]; ///< OEM ID
+ UINT8 Revision; ///< 0 for APCI 1.0, 2 for ACPI 2.0
+ UINT32 RsdtAddress; ///< physical address of RSDT
+ UINT32 Length; ///< total length of RSDP (including extended part)
+ UINT64 XsdtAddress; ///< physical address of XSDT
+ UINT8 ExtendedCheckSum; ///< chechsum of whole table
+ UINT8 Reserved[3]; ///< Reserved
+} RSDP_HEADER;
+
+///
+/// DESCRIPTION_HEADER - ACPI common table header
+///
+typedef struct _DESCRIPTION_HEADER {
+ UINT32 Signature; ///< ACPI signature (4 ASCII characters)
+ UINT32 Length; ///< Length of table, in bytes, including header
+ UINT8 Revision; ///< ACPI Specification minor version #
+ UINT8 CheckSum; ///< To make sum of entire table == 0
+ UINT8 OemId[6]; ///< OEM identification
+ UINT8 OemTableId[8]; ///< OEM table identification
+ UINT32 OemRevision; ///< OEM revision number
+ UINT32 CreatorId; ///< ASL compiler vendor ID
+ UINT32 CreatorRevision; ///< ASL compiler revision number
+} DESCRIPTION_HEADER;
+
+///
+/// _AcpiRegWrite - ACPI MMIO register R/W structure
+///
+typedef struct _ACPI_REG_WRITE {
+ UINT8 MmioBase; /// MmioBase: Index of Fch block (For instance GPIO_BASE:0x01 SMI_BASE:0x02)
+ UINT8 MmioReg; /// MmioReg : Register index
+ UINT8 DataAndMask; /// DataANDMask : AND Register Data
+ UINT8 DataOrMask; /// DataOrMask : Or Register Data
+} ACPI_REG_WRITE;
+
+VOID* AcpiLocateTable (IN UINT32 Signature);
+VOID AcpiSetTableCheckSum (IN VOID *TablePtr);
+UINT8 AcpiGetTableCheckSum (IN VOID *TablePtr);
+UINT8 GetByteSum (IN VOID *DataPtr, IN UINT32 Length);
+
+#endif
diff --git a/src/vendorcode/amd/pi/00730F01/Proc/Fch/Common/FchBiosRamUsage.h b/src/vendorcode/amd/pi/00730F01/Proc/Fch/Common/FchBiosRamUsage.h
new file mode 100644
index 0000000..dcd12be
--- /dev/null
+++ b/src/vendorcode/amd/pi/00730F01/Proc/Fch/Common/FchBiosRamUsage.h
@@ -0,0 +1,67 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * FCH BIOS Ram usage
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: FCH
+ * @e \$Revision: 281178 $ @e \$Date: 2013-12-18 02:14:15 -0600 (Wed, 18 Dec 2013) $
+ *
+ */
+/*****************************************************************************
+ *
+ * Copyright (c) 2008 - 2014, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ***************************************************************************/
+
+#ifndef _FCH_BIOS_RAM_USAGE_H_
+#define _FCH_BIOS_RAM_USAGE_H_
+
+#define RESTORE_MEMORY_CONTROLLER_START 0
+#define XHCI_REGISTER_BAR00 0xD0
+#define XHCI_REGISTER_BAR01 0xD1
+#define XHCI_REGISTER_BAR02 0xD2
+#define XHCI_REGISTER_BAR03 0xD3
+#define XHCI_REGISTER_04H 0xD4
+#define XHCI_REGISTER_0CH 0xD5
+#define XHCI_REGISTER_3CH 0xD6
+#define XHCI1_REGISTER_BAR00 0xE0
+#define XHCI1_REGISTER_BAR01 0xE1
+#define XHCI1_REGISTER_BAR02 0xE2
+#define XHCI1_REGISTER_BAR03 0xE3
+#define XHCI1_REGISTER_04H 0xE4
+#define XHCI1_REGISTER_0CH 0xE5
+#define XHCI1_REGISTER_3CH 0xE6
+#define RTC_WORKAROUND_DATA_START 0xF0
+#define BOOT_TIME_FLAG_SEC 0xF8
+#define BOOT_TIME_FLAG_INT19 0xFC
+
+#endif
+
diff --git a/src/vendorcode/amd/pi/00730F01/Proc/Fch/Common/FchCommonCfg.h b/src/vendorcode/amd/pi/00730F01/Proc/Fch/Common/FchCommonCfg.h
new file mode 100644
index 0000000..72e6aeb
--- /dev/null
+++ b/src/vendorcode/amd/pi/00730F01/Proc/Fch/Common/FchCommonCfg.h
@@ -0,0 +1,1296 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * FCH Function Support Definition
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: FCH
+ * @e \$Revision: 281178 $ @e \$Date: 2013-12-18 02:14:15 -0600 (Wed, 18 Dec 2013) $
+ *
+ */
+/*****************************************************************************
+ *
+ * Copyright (c) 2008 - 2014, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ***************************************************************************/
+
+#ifndef _FCH_COMMON_CFG_H_
+#define _FCH_COMMON_CFG_H_
+
+#pragma pack (push, 1)
+
+//-----------------------------------------------------------------------------
+// FCH DEFINITIONS AND MACROS
+//-----------------------------------------------------------------------------
+
+//
+// FCH Component Data Structure Definitions
+//
+
+/// PCI_ADDRESS - PCI access structure
+#define PCI_ADDRESS(bus, dev, func, reg) \
+ (UINT32) ( (((UINT32)bus) << 24) + (((UINT32)dev) << 19) + (((UINT32)func) << 16) + ((UINT32)reg) )
+
+#define CPUID_FMF 0x80000001ul // Family Model Features information
+///
+/// - Byte Register R/W structure
+///
+typedef struct _REG8_MASK {
+ UINT8 RegIndex; /// RegIndex - Reserved
+ UINT8 AndMask; /// AndMask - Reserved
+ UINT8 OrMask; /// OrMask - Reserved
+} REG8_MASK;
+
+
+///
+/// PCIE Reset Block
+///
+typedef enum {
+ NbBlock, ///< Reset for NB PCIE
+ FchBlock ///< Reset for FCH GPP
+} RESET_BLOCK;
+
+///
+/// PCIE Reset Operation
+///
+typedef enum {
+ DeassertReset, ///< DeassertRese - Deassert reset
+ AssertReset ///< AssertReset - Assert reset
+} RESET_OP;
+
+
+///
+/// SD structure
+///
+typedef struct {
+ SD_MODE SdConfig; ///< SD Mode configuration
+ /// @li <b>00</b> - Disabled
+ /// @li <b>00</b> - AMDA
+ /// @li <b>01</b> - DMA
+ /// @li <b>10</b> - PIO
+ ///
+ UINT8 SdSpeed; ///< SD Speed
+ /// @li <b>0</b> - Low speed
+ /// @li <b>1</b> - High speed
+ ///
+ UINT8 SdBitWidth; ///< SD Bit Width
+ /// @li <b>0</b> - 32BIT clear 23
+ /// @li <b>1</b> - 64BIT, set 23,default
+ ///
+ UINT32 SdSsid; ///< SD Subsystem ID
+ SD_CLOCK_CONTROL SdClockControl; ///< SD Clock Control
+ BOOLEAN SdClockMultiplier; ///< SD Clock Multiplier enable/disable
+ UINT8 SdReTuningMode; ///< SD Re-tuning modes select
+ /// @li <b>0</b> - mode 1
+ /// @li <b>1</b> - mode 2
+ /// @li <b>2</b> - mode 3
+ UINT8 SdHostControllerVersion; ///< SD controller Version
+ /// @li <b>1</b> - SD 2.0
+ /// @li <b>2</b> - SD 3.0
+ UINT8 SdrCapabilities; ///< SDR Capability mode select
+ /// @li <b>00</b> - SDR25/15
+ /// @li <b>01</b> - SDR50
+ /// @li <b>11</b> - SDR104
+ UINT8 SdSlotType; ///< SDR Slot Type select
+ /// @li <b>00</b> - Removable Card Slot
+ /// @li <b>01</b> - Embedded Slot for One Device
+ /// @li <b>10</b> - Shared Bus Slot
+ BOOLEAN SdForce18; ///< SD Force18
+} FCH_SD;
+
+///
+/// CODEC_ENTRY - Fch HD Audio OEM Codec structure
+///
+typedef struct _CODEC_ENTRY {
+ UINT8 Nid; /// Nid - Reserved
+ UINT32 Byte40; /// Byte40 - Reserved
+} CODEC_ENTRY;
+
+///
+/// CODEC_TBL_LIST - Fch HD Audio Codec table list
+///
+typedef struct _CODEC_TBL_LIST {
+ UINT32 CodecId; /// CodecID - Codec ID
+ CONST CODEC_ENTRY* CodecTablePtr; /// CodecTablePtr - Codec table pointer
+} CODEC_TBL_LIST;
+
+///
+/// AZALIA_PIN - HID Azalia or GPIO define structure.
+///
+typedef struct _AZALIA_PIN {
+ UINT8 AzaliaSdin0; ///< AzaliaSdin0
+ /// @par
+ /// @li <b>00</b> - GPIO PIN
+ /// @li <b>10</b> - As a Azalia SDIN pin
+
+ UINT8 AzaliaSdin1; ///< AzaliaSdin1
+ /// @par
+ /// SDIN1 is define at BIT2 & BIT3
+ /// @li <b>00</b> - GPIO PIN
+ /// @li <b>10</b> - As a Azalia SDIN pin
+
+ UINT8 AzaliaSdin2; ///< AzaliaSdin2
+ /// @par
+ /// SDIN2 is define at BIT4 & BIT5
+ /// @li <b>00</b> - GPIO PIN
+ /// @li <b>10</b> - As a Azalia SDIN pin
+
+ UINT8 AzaliaSdin3; ///< AzaliaSdin3
+ /// @par
+ /// SDIN3 is define at BIT6 & BIT7
+ /// @li <b>00</b> - GPIO PIN
+ /// @li <b>10</b> - As a Azalia SDIN pin
+} AZALIA_PIN;
+
+///
+/// Azalia structure
+///
+typedef struct {
+ HDA_CONFIG AzaliaEnable; ///< AzaliaEnable - Azalia function configuration
+ BOOLEAN AzaliaMsiEnable; ///< AzaliaMsiEnable - Azalia MSI capability
+ UINT32 AzaliaSsid; ///< AzaliaSsid - Azalia Subsystem ID
+ UINT8 AzaliaPinCfg; ///< AzaliaPinCfg - Azalia Controller SDIN pin Configuration
+ /// @par
+ /// @li <b>0</b> - disable
+ /// @li <b>1</b> - enable
+
+ UINT8 AzaliaFrontPanel; ///< AzaliaFrontPanel - Azalia Controller Front Panel Configuration
+ /// @par
+ /// Support Front Panel configuration
+ /// @li <b>0</b> - Auto
+ /// @li <b>1</b> - disable
+ /// @li <b>2</b> - enable
+
+ UINT8 FrontPanelDetected; ///< FrontPanelDetected - Force Azalia Controller Front Panel Configuration
+ /// @par
+ /// Force Front Panel configuration
+ /// @li <b>0</b> - Not Detected
+ /// @li <b>1</b> - Detected
+
+ UINT8 AzaliaSnoop; ///< AzaliaSnoop - Azalia Controller Snoop feature Configuration
+ /// @par
+ /// Azalia Controller Snoop feature Configuration
+ /// @li <b>0</b> - disable
+ /// @li <b>1</b> - enable
+
+ UINT8 AzaliaDummy; /// AzaliaDummy - Reserved */
+
+ AZALIA_PIN AzaliaConfig; /// AzaliaConfig - Azaliz Pin Configuration
+
+///
+/// AZOEMTBL - Azalia Controller OEM Codec Table Pointer
+///
+ CONST CODEC_TBL_LIST *AzaliaOemCodecTablePtr; /// AzaliaOemCodecTablePtr - Oem Azalia Codec Table Pointer
+
+///
+/// AZOEMFPTBL - Azalia Controller Front Panel OEM Table Pointer
+///
+ CONST VOID *AzaliaOemFpCodecTablePtr; /// AzaliaOemFpCodecTablePtr - Oem Front Panel Codec Table Pointer
+} FCH_AZALIA;
+
+///
+/// _SPI_DEVICE_PROFILE Spi Device Profile structure
+///
+typedef struct _SPI_DEVICE_PROFILE {
+ UINT32 JEDEC_ID; /// JEDEC ID
+ UINT32 RomSize; /// ROM Size
+ UINT32 SectorSize; /// Sector Size
+ UINT16 MaxNormalSpeed; /// Max Normal Speed
+ UINT16 MaxFastSpeed; /// Max Fast Speed
+ UINT16 MaxDualSpeed; /// Max Dual Speed
+ UINT16 MaxQuadSpeed; /// Max Quad Speed
+ UINT8 QeReadRegister; /// QE Read Register
+ UINT8 QeWriteRegister; /// QE Write Register
+ UINT8 QeOperateSize; /// QE Operate Size 1byte/2bytes
+ UINT16 QeLocation; // QE Location in the register
+} SPI_DEVICE_PROFILE;
+
+///
+/// _SPI_CONTROLLER_PROFILE Spi Device Profile structure
+///
+typedef struct _SPI_CONTROLLER_PROFILE {
+// UINT32 SPI_CONTROLLER_ID; /// SPI Controller ID
+ UINT16 FifoSize; /// FIFO Size
+ UINT16 MaxNormalSpeed; /// Max Normal Speed
+ UINT16 MaxFastSpeed; /// Max Fast Speed
+ UINT16 MaxDualSpeed; /// Max Dual Speed
+ UINT16 MaxQuadSpeed; /// Max Quad Speed
+} SPI_CONTROLLER_PROFILE;
+
+///
+/// SPI structure
+///
+typedef struct {
+ BOOLEAN LpcMsiEnable; ///< LPC MSI capability
+ UINT32 LpcSsid; ///< LPC Subsystem ID
+ UINT32 RomBaseAddress; ///< SpiRomBaseAddress
+ /// @par
+ /// SPI ROM BASE Address
+ ///
+ UINT8 SpiSpeed; ///< SpiSpeed - Spi Frequency
+ /// @par
+ /// SPI Speed [1.0] - the clock speed for non-fast read command
+ /// @li <b>00</b> - 66Mhz
+ /// @li <b>01</b> - 33Mhz
+ /// @li <b>10</b> - 22Mhz
+ /// @li <b>11</b> - 16.5Mhz
+ ///
+ UINT8 SpiFastSpeed; ///< FastSpeed - Spi Fast Speed feature
+ /// SPIFastSpeed [1.0] - the clock speed for Fast Speed Feature
+ /// @li <b>00</b> - 66Mhz
+ /// @li <b>01</b> - 33Mhz
+ /// @li <b>10</b> - 22Mhz
+ /// @li <b>11</b> - 16.5Mhz
+ ///
+ UINT8 WriteSpeed; ///< WriteSpeed - Spi Write Speed
+ /// @par
+ /// WriteSpeed [1.0] - the clock speed for Spi write command
+ /// @li <b>00</b> - 66Mhz
+ /// @li <b>01</b> - 33Mhz
+ /// @li <b>10</b> - 22Mhz
+ /// @li <b>11</b> - 16.5Mhz
+ ///
+ UINT8 SpiMode; ///< SpiMode - Spi Mode Setting
+ /// @par
+ /// @li <b>101</b> - Qual-io 1-4-4
+ /// @li <b>100</b> - Dual-io 1-2-2
+ /// @li <b>011</b> - Qual-io 1-1-4
+ /// @li <b>010</b> - Dual-io 1-1-2
+ /// @li <b>111</b> - FastRead
+ /// @li <b>110</b> - Normal
+ ///
+ UINT8 AutoMode; ///< AutoMode - Spi Auto Mode
+ /// @par
+ /// SPI Auto Mode
+ /// @li <b>0</b> - Disabled
+ /// @li <b>1</b> - Enabled
+ ///
+ UINT8 SpiBurstWrite; ///< SpiBurstWrite - Spi Burst Write Mode
+ /// @par
+ /// SPI Burst Write
+ /// @li <b>0</b> - Disabled
+ /// @li <b>1</b> - Enabled
+ BOOLEAN LpcClk0; ///< Lclk0En - LPCCLK0
+ /// @par
+ /// LPC Clock 0 mode
+ /// @li <b>0</b> - forced to stop
+ /// @li <b>1</b> - functioning with CLKRUN protocol
+ BOOLEAN LpcClk1; ///< Lclk1En - LPCCLK1
+ /// @par
+ /// LPC Clock 1 mode
+ /// @li <b>0</b> - forced to stop
+ /// @li <b>1</b> - functioning with CLKRUN protocol
+// UINT32 SPI100_RX_Timing_Config_Register_38; ///< SPI100_RX_Timing_Config_Register_38
+// UINT16 SPI100_RX_Timing_Config_Register_3C; ///< SPI100_RX_Timing_Config_Register_3C
+// UINT8 SpiProtectEn0_1d_34; ///
+ UINT8 SPI100_Enable; ///
+ SPI_DEVICE_PROFILE SpiDeviceProfile; /// Spi Device Profile
+} FCH_SPI;
+
+
+///
+/// IDE structure
+///
+typedef struct {
+ BOOLEAN IdeEnable; ///< IDE function switch
+ BOOLEAN IdeMsiEnable; ///< IDE MSI capability
+ UINT32 IdeSsid; ///< IDE controller Subsystem ID
+} FCH_IDE;
+
+///
+/// IR Structure
+///
+typedef struct {
+ IR_CONFIG IrConfig; ///< IrConfig
+ UINT8 IrPinControl; ///< IrPinControl
+} FCH_IR;
+
+
+///
+/// PCI Bridge Structure
+///
+typedef struct {
+ BOOLEAN PcibMsiEnable; ///< PCI-PCI Bridge MSI capability
+ UINT32 PcibSsid; ///< PCI-PCI Bridge Subsystem ID
+ UINT8 PciClks; ///< 33MHz PCICLK0/1/2/3 Enable, bits [0:3] used
+ /// @li <b>0</b> - disable
+ /// @li <b>1</b> - enable
+ ///
+ UINT16 PcibClkStopOverride; ///< PCIB_CLK_Stop Override
+ BOOLEAN PcibClockRun; ///< Enable the auto clkrun functionality
+ /// @li <b>0</b> - disable
+ /// @li <b>1</b> - enable
+ ///
+} FCH_PCIB;
+
+
+///
+/// - SATA Phy setting structure
+///
+typedef struct _SATA_PHY_SETTING {
+ UINT16 PhyCoreControlWord; /// PhyCoreControlWord - Reserved
+ UINT32 PhyFineTuneDword; /// PhyFineTuneDword - Reserved
+} SATA_PHY_SETTING;
+
+///
+/// SATA main setting structure
+///
+typedef struct _SATA_ST {
+ UINT8 SataModeReg; ///< SataModeReg - Sata Controller Mode
+ BOOLEAN SataEnable; ///< SataEnable - Sata Controller Function
+ /// @par
+ /// Sata Controller
+ /// @li <b>0</b> - disable
+ /// @li <b>1</b> - enable
+ ///
+ UINT8 Sata6AhciCap; ///< Sata6AhciCap - Reserved */
+ BOOLEAN SataSetMaxGen2; ///< SataSetMaxGen2 - Set Sata Max Gen2 mode
+ /// @par
+ /// Sata Controller Set to Max Gen2 mode
+ /// @li <b>0</b> - disable
+ /// @li <b>1</b> - enable
+ ///
+ BOOLEAN IdeEnable; ///< IdeEnable - Hidden IDE
+ /// @par
+ /// Sata IDE Controller Combined Mode
+ /// Enable - SATA controller has control over Port0 through Port3,
+ /// IDE controller has control over Port4 and Port7.
+ /// Disable - SATA controller has full control of all 8 Ports
+ /// when operating in non-IDE mode.
+ /// @li <b>0</b> - enable
+ /// @li <b>1</b> - disable
+ ///
+ UINT8 SataClkMode; /// SataClkMode - Reserved
+} SATA_ST;
+
+///
+/// SATA_PORT_ST - SATA PORT structure
+///
+typedef struct _SATA_PORT_ST {
+ UINT8 SataPortReg; ///< SATA Port bit map - bits[0:7] for ports 0 ~ 7
+ /// @li <b>0</b> - disable
+ /// @li <b>1</b> - enable
+ ///
+ BOOLEAN Port0; ///< PORT0 - 0:disable, 1:enable
+ BOOLEAN Port1; ///< PORT1 - 0:disable, 1:enable
+ BOOLEAN Port2; ///< PORT2 - 0:disable, 1:enable
+ BOOLEAN Port3; ///< PORT3 - 0:disable, 1:enable
+ BOOLEAN Port4; ///< PORT4 - 0:disable, 1:enable
+ BOOLEAN Port5; ///< PORT5 - 0:disable, 1:enable
+ BOOLEAN Port6; ///< PORT6 - 0:disable, 1:enable
+ BOOLEAN Port7; ///< PORT7 - 0:disable, 1:enable
+} SATA_PORT_ST;
+
+///
+///< _SATA_PORT_MD - Force Each PORT to GEN1/GEN2 mode
+///
+typedef struct _SATA_PORT_MD {
+ UINT16 SataPortMode; ///< SATA Port GEN1/GEN2 mode bit map - bits [0:15] for ports 0 ~ 7
+ UINT8 Port0; ///< PORT0 - set BIT0 to GEN1, BIT1 - PORT0 set to GEN2
+ UINT8 Port1; ///< PORT1 - set BIT2 to GEN1, BIT3 - PORT1 set to GEN2
+ UINT8 Port2; ///< PORT2 - set BIT4 to GEN1, BIT5 - PORT2 set to GEN2
+ UINT8 Port3; ///< PORT3 - set BIT6 to GEN1, BIT7 - PORT3 set to GEN2
+ UINT8 Port4; ///< PORT4 - set BIT8 to GEN1, BIT9 - PORT4 set to GEN2
+ UINT8 Port5; ///< PORT5 - set BIT10 to GEN1, BIT11 - PORT5 set to GEN2
+ UINT8 Port6; ///< PORT6 - set BIT12 to GEN1, BIT13 - PORT6 set to GEN2
+ UINT8 Port7; ///< PORT7 - set BIT14 to GEN1, BIT15 - PORT7 set to GEN2
+} SATA_PORT_MD;
+///
+/// SATA structure
+///
+typedef struct {
+ BOOLEAN SataMsiEnable; ///< SATA MSI capability
+ UINT32 SataIdeSsid; ///< SATA IDE mode SSID
+ UINT32 SataRaidSsid; ///< SATA RAID mode SSID
+ UINT32 SataRaid5Ssid; ///< SATA RAID 5 mode SSID
+ UINT32 SataAhciSsid; ///< SATA AHCI mode SSID
+
+ SATA_ST SataMode; /// SataMode - Reserved
+ SATA_CLASS SataClass; ///< SataClass - SATA Controller mode [2:0]
+ UINT8 SataIdeMode; ///< SataIdeMode - Sata IDE Controller mode
+ /// @par
+ /// @li <b>0</b> - Legacy IDE mode
+ /// @li <b>1</b> - Native IDE mode
+ ///
+ UINT8 SataDisUnusedIdePChannel; ///< SataDisUnusedIdePChannel-Disable Unused IDE Primary Channel
+ /// @par
+ /// @li <b>0</b> - Channel Enable
+ /// @li <b>1</b> - Channel Disable
+ ///
+ UINT8 SataDisUnusedIdeSChannel; ///< SataDisUnusedIdeSChannel - Disable Unused IDE Secondary Channel
+ /// @par
+ /// @li <b>0</b> - Channel Enable
+ /// @li <b>1</b> - Channel Disable
+ ///
+ UINT8 IdeDisUnusedIdePChannel; ///< IdeDisUnusedIdePChannel-Disable Unused IDE Primary Channel
+ /// @par
+ /// @li <b>0</b> - Channel Enable
+ /// @li <b>1</b> - Channel Disable
+ ///
+ UINT8 IdeDisUnusedIdeSChannel; ///< IdeDisUnusedIdeSChannel-Disable Unused IDE Secondary Channel
+ /// @par
+ /// @li <b>0</b> - Channel Enable
+ /// @li <b>1</b> - Channel Disable
+ ///
+ UINT8 SataOptionReserved; /// SataOptionReserved - Reserved
+
+ SATA_PORT_ST SataEspPort; ///< SataEspPort - SATA port is external accessible on a signal only connector (eSATA:)
+
+ SATA_PORT_ST SataPortPower; ///< SataPortPower - Port Power configuration
+
+ SATA_PORT_MD SataPortMd; ///< SataPortMd - Port Mode
+
+ UINT8 SataAggrLinkPmCap; /// SataAggrLinkPmCap - 0:OFF 1:ON
+ UINT8 SataPortMultCap; /// SataPortMultCap - 0:OFF 1:ON
+ UINT8 SataClkAutoOff; /// SataClkAutoOff - AutoClockOff 0:Disabled, 1:Enabled
+ UINT8 SataPscCap; /// SataPscCap 1:Enable PSC, 0:Disable PSC capability
+ UINT8 BiosOsHandOff; /// BiosOsHandOff - Reserved
+ UINT8 SataFisBasedSwitching; /// SataFisBasedSwitching - Reserved
+ UINT8 SataCccSupport; /// SataCccSupport - Reserved
+ UINT8 SataSscCap; /// SataSscCap - 1:Enable, 0:Disable SSC capability
+ UINT8 SataMsiCapability; /// SataMsiCapability 0:Hidden 1:Visible
+ UINT8 SataForceRaid; /// SataForceRaid 0:No function 1:Force RAID
+ UINT8 SataInternal100Spread; /// SataInternal100Spread - Reserved
+ UINT8 SataDebugDummy; /// SataDebugDummy - Reserved
+ UINT8 SataTargetSupport8Device; /// SataTargetSupport8Device - Reserved
+ UINT8 SataDisableGenericMode; /// SataDisableGenericMode - Reserved
+ BOOLEAN SataAhciEnclosureManagement; /// SataAhciEnclosureManagement - Reserved
+ UINT8 SataSgpio0; /// SataSgpio0 - Reserved
+ UINT8 SataSgpio1; /// SataSgpio1 - Reserved
+ UINT8 SataPhyPllShutDown; /// SataPhyPllShutDown - Reserved
+ BOOLEAN SataHotRemovalEnh; /// SataHotRemovalEnh - Reserved
+
+ SATA_PORT_ST SataHotRemovalEnhPort; ///< SataHotRemovalEnhPort - Hot Remove
+
+ BOOLEAN SataOobDetectionEnh; /// SataOobDetectionEnh - TRUE
+ BOOLEAN SataPowerSavingEnh; /// SataPowerSavingEnh - TRUE
+ UINT8 SataMemoryPowerSaving; /// SataMemoryPowerSaving - 0-3 Default [3]
+ BOOLEAN SataRasSupport; /// SataRasSupport - Support RAS function TRUE: Enable FALSE: Disable
+ BOOLEAN SataAhciDisPrefetchFunction; /// SataAhciDisPrefetchFunction - Disable AHCI Prefetch Function Support
+ BOOLEAN SataDevSlpPort0; /// SataDevSlpPort0 - Reserved
+ BOOLEAN SataDevSlpPort1; /// SataDevSlpPort1 - Reserved
+ UINT32 TempMmio; /// TempMmio - Reserved
+} FCH_SATA;
+
+
+//
+// IMC Message Register Software Interface
+//
+#define CPU_MISC_BUS_DEV_FUN ((0x18 << 3) + 3)
+
+#define MSG_SYS_TO_IMC 0x80
+#define Fun_80 0x80
+#define Fun_81 0x81
+#define Fun_82 0x82
+#define Fun_83 0x83
+#define Fun_84 0x84
+#define Fun_85 0x85
+#define Fun_86 0x86
+#define Fun_87 0x87
+#define Fun_88 0x88
+#define Fun_89 0x89
+#define Fun_90 0x90
+#define MSG_IMC_TO_SYS 0x81
+#define MSG_REG0 0x82
+#define MSG_REG1 0x83
+#define MSG_REG2 0x84
+#define MSG_REG3 0x85
+#define MSG_REG4 0x86
+#define MSG_REG5 0x87
+#define MSG_REG6 0x88
+#define MSG_REG7 0x89
+#define MSG_REG8 0x8A
+#define MSG_REG9 0x8B
+#define MSG_REGA 0x8C
+#define MSG_REGB 0x8D
+#define MSG_REGC 0x8E
+#define MSG_REGD 0x8F
+
+#define DISABLED 0
+#define ENABLED 1
+
+
+
+///
+/// EC structure
+///
+typedef struct _FCH_EC {
+ UINT8 MsgFun81Zone0MsgReg0; ///<Thermal zone
+ UINT8 MsgFun81Zone0MsgReg1; ///<Thermal zone
+ UINT8 MsgFun81Zone0MsgReg2; ///<Thermal zone control byte 1
+ UINT8 MsgFun81Zone0MsgReg3; ///<Thermal zone control byte 2
+ UINT8 MsgFun81Zone0MsgReg4; ///<Bit[3:0] - Thermal diode offset adjustment in degrees Celsius.
+ UINT8 MsgFun81Zone0MsgReg5; ///<Hysteresis information
+ UINT8 MsgFun81Zone0MsgReg6; ///<SMBUS Address for SMBUS based temperature sensor such as SB-TSI and ADM1032
+ UINT8 MsgFun81Zone0MsgReg7; ///<Bit[1:0]: 0 - 2, SMBUS bus number where the SMBUS based temperature sensor is located.
+ UINT8 MsgFun81Zone0MsgReg8; ///<Fan PWM stepping rate in unit of PWM level percentage
+ UINT8 MsgFun81Zone0MsgReg9; ///<Fan PWM ramping rate in 5ms unit
+//
+// EC LDN9 function 81 zone 1
+//
+ UINT8 MsgFun81Zone1MsgReg0; ///<Thermal zone
+ UINT8 MsgFun81Zone1MsgReg1; ///<Thermal zone
+ UINT8 MsgFun81Zone1MsgReg2; ///<Thermal zone control byte 1
+ UINT8 MsgFun81Zone1MsgReg3; ///<Thermal zone control byte 2
+ UINT8 MsgFun81Zone1MsgReg4; ///<Bit[3:0] - Thermal diode offset adjustment in degrees Celsius.
+ UINT8 MsgFun81Zone1MsgReg5; ///<Hysteresis information
+ UINT8 MsgFun81Zone1MsgReg6; ///<SMBUS Address for SMBUS based temperature sensor such as SB-TSI and ADM1032
+ UINT8 MsgFun81Zone1MsgReg7; ///<Bit[1:0]: 0 - 2, SMBUS bus number where the SMBUS based temperature sensor is located.
+ UINT8 MsgFun81Zone1MsgReg8; ///<Fan PWM stepping rate in unit of PWM level percentage
+ UINT8 MsgFun81Zone1MsgReg9; ///<Fan PWM ramping rate in 5ms unit
+//
+//EC LDN9 function 81 zone 2
+//
+ UINT8 MsgFun81Zone2MsgReg0; ///<Thermal zone
+ UINT8 MsgFun81Zone2MsgReg1; ///<Thermal zone
+ UINT8 MsgFun81Zone2MsgReg2; ///<Thermal zone control byte 1
+ UINT8 MsgFun81Zone2MsgReg3; ///<Thermal zone control byte 2
+ UINT8 MsgFun81Zone2MsgReg4; ///<Bit[3:0] - Thermal diode offset adjustment in degrees Celsius.
+ UINT8 MsgFun81Zone2MsgReg5; ///<Hysteresis information
+ UINT8 MsgFun81Zone2MsgReg6; ///<SMBUS Address for SMBUS based temperature sensor such as SB-TSI and ADM1032
+ UINT8 MsgFun81Zone2MsgReg7; ///<Bit[1:0]: 0 - 2, SMBUS bus number where the SMBUS based temperature sensor is located.
+ UINT8 MsgFun81Zone2MsgReg8; ///<Fan PWM stepping rate in unit of PWM level percentage
+ UINT8 MsgFun81Zone2MsgReg9; ///<Fan PWM ramping rate in 5ms unit
+//
+//EC LDN9 function 81 zone 3
+//
+ UINT8 MsgFun81Zone3MsgReg0; ///<Thermal zone
+ UINT8 MsgFun81Zone3MsgReg1; ///<Thermal zone
+ UINT8 MsgFun81Zone3MsgReg2; ///<Thermal zone control byte 1
+ UINT8 MsgFun81Zone3MsgReg3; ///<Thermal zone control byte 2
+ UINT8 MsgFun81Zone3MsgReg4; ///<Bit[3:0] - Thermal diode offset adjustment in degrees Celsius.
+ UINT8 MsgFun81Zone3MsgReg5; ///<Hysteresis information
+ UINT8 MsgFun81Zone3MsgReg6; ///<SMBUS Address for SMBUS based temperature sensor such as SB-TSI and ADM1032
+ UINT8 MsgFun81Zone3MsgReg7; ///<Bit[1:0]: 0 - 2, SMBUS bus number where the SMBUS based temperature sensor is located.
+ UINT8 MsgFun81Zone3MsgReg8; ///<Fan PWM stepping rate in unit of PWM level percentage
+ UINT8 MsgFun81Zone3MsgReg9; ///<Fan PWM ramping rate in 5ms unit
+//
+//EC LDN9 function 83 zone 0
+//
+ UINT8 MsgFun83Zone0MsgReg0; ///<Thermal zone
+ UINT8 MsgFun83Zone0MsgReg1; ///<Thermal zone
+ UINT8 MsgFun83Zone0MsgReg2; ///<_AC0
+ UINT8 MsgFun83Zone0MsgReg3; ///<_AC1
+ UINT8 MsgFun83Zone0MsgReg4; ///<_AC2
+ UINT8 MsgFun83Zone0MsgReg5; ///<_AC3
+ UINT8 MsgFun83Zone0MsgReg6; ///<_AC4
+ UINT8 MsgFun83Zone0MsgReg7; ///<_AC5
+ UINT8 MsgFun83Zone0MsgReg8; ///<_AC6
+ UINT8 MsgFun83Zone0MsgReg9; ///<_AC7
+ UINT8 MsgFun83Zone0MsgRegA; ///<_CRT
+ UINT8 MsgFun83Zone0MsgRegB; ///<_PSV
+//
+//EC LDN9 function 83 zone 1
+//
+ UINT8 MsgFun83Zone1MsgReg0; ///<Thermal zone
+ UINT8 MsgFun83Zone1MsgReg1; ///<Thermal zone
+ UINT8 MsgFun83Zone1MsgReg2; ///<_AC0
+ UINT8 MsgFun83Zone1MsgReg3; ///<_AC1
+ UINT8 MsgFun83Zone1MsgReg4; ///<_AC2
+ UINT8 MsgFun83Zone1MsgReg5; ///<_AC3
+ UINT8 MsgFun83Zone1MsgReg6; ///<_AC4
+ UINT8 MsgFun83Zone1MsgReg7; ///<_AC5
+ UINT8 MsgFun83Zone1MsgReg8; ///<_AC6
+ UINT8 MsgFun83Zone1MsgReg9; ///<_AC7
+ UINT8 MsgFun83Zone1MsgRegA; ///<_CRT
+ UINT8 MsgFun83Zone1MsgRegB; ///<_PSV
+//
+//EC LDN9 function 83 zone 2
+//
+ UINT8 MsgFun83Zone2MsgReg0; ///<Thermal zone
+ UINT8 MsgFun83Zone2MsgReg1; ///<Thermal zone
+ UINT8 MsgFun83Zone2MsgReg2; ///<_AC0
+ UINT8 MsgFun83Zone2MsgReg3; ///<_AC1
+ UINT8 MsgFun83Zone2MsgReg4; ///<_AC2
+ UINT8 MsgFun83Zone2MsgReg5; ///<_AC3
+ UINT8 MsgFun83Zone2MsgReg6; ///<_AC4
+ UINT8 MsgFun83Zone2MsgReg7; ///<_AC5
+ UINT8 MsgFun83Zone2MsgReg8; ///<_AC6
+ UINT8 MsgFun83Zone2MsgReg9; ///<_AC7
+ UINT8 MsgFun83Zone2MsgRegA; ///<_CRT
+ UINT8 MsgFun83Zone2MsgRegB; ///<_PSV
+//
+//EC LDN9 function 83 zone 3
+//
+ UINT8 MsgFun83Zone3MsgReg0; ///<Thermal zone
+ UINT8 MsgFun83Zone3MsgReg1; ///<Thermal zone
+ UINT8 MsgFun83Zone3MsgReg2; ///<_AC0
+ UINT8 MsgFun83Zone3MsgReg3; ///<_AC1
+ UINT8 MsgFun83Zone3MsgReg4; ///<_AC2
+ UINT8 MsgFun83Zone3MsgReg5; ///<_AC3
+ UINT8 MsgFun83Zone3MsgReg6; ///<_AC4
+ UINT8 MsgFun83Zone3MsgReg7; ///<_AC5
+ UINT8 MsgFun83Zone3MsgReg8; ///<_AC6
+ UINT8 MsgFun83Zone3MsgReg9; ///<_AC7
+ UINT8 MsgFun83Zone3MsgRegA; ///<_CRT
+ UINT8 MsgFun83Zone3MsgRegB; ///<_PSV
+//
+//EC LDN9 function 85 zone 0
+//
+ UINT8 MsgFun85Zone0MsgReg0; ///<Thermal zone
+ UINT8 MsgFun85Zone0MsgReg1; ///<Thermal zone
+ UINT8 MsgFun85Zone0MsgReg2; ///<AL0 PWM level in percentage (0 - 100%)
+ UINT8 MsgFun85Zone0MsgReg3; ///<AL1 PWM level in percentage (0 - 100%)
+ UINT8 MsgFun85Zone0MsgReg4; ///<AL2 PWM level in percentage (0 - 100%)
+ UINT8 MsgFun85Zone0MsgReg5; ///<AL3 PWM level in percentage (0 - 100%)
+ UINT8 MsgFun85Zone0MsgReg6; ///<AL4 PWM level in percentage (0 - 100%)
+ UINT8 MsgFun85Zone0MsgReg7; ///<AL5 PWM level in percentage (0 - 100%)
+ UINT8 MsgFun85Zone0MsgReg8; ///<AL6 PWM level in percentage (0 - 100%)
+ UINT8 MsgFun85Zone0MsgReg9; ///<AL7 PWM level in percentage (0 - 100%)
+//
+//EC LDN9 function 85 zone 1
+//
+ UINT8 MsgFun85Zone1MsgReg0; ///<Thermal zone
+ UINT8 MsgFun85Zone1MsgReg1; ///<Thermal zone
+ UINT8 MsgFun85Zone1MsgReg2; ///<AL0 PWM level in percentage (0 - 100%)
+ UINT8 MsgFun85Zone1MsgReg3; ///<AL1 PWM level in percentage (0 - 100%)
+ UINT8 MsgFun85Zone1MsgReg4; ///<AL2 PWM level in percentage (0 - 100%)
+ UINT8 MsgFun85Zone1MsgReg5; ///<AL3 PWM level in percentage (0 - 100%)
+ UINT8 MsgFun85Zone1MsgReg6; ///<AL4 PWM level in percentage (0 - 100%)
+ UINT8 MsgFun85Zone1MsgReg7; ///<AL5 PWM level in percentage (0 - 100%)
+ UINT8 MsgFun85Zone1MsgReg8; ///<AL6 PWM level in percentage (0 - 100%)
+ UINT8 MsgFun85Zone1MsgReg9; ///<AL7 PWM level in percentage (0 - 100%)
+//
+//EC LDN9 function 85 zone 2
+//
+ UINT8 MsgFun85Zone2MsgReg0; ///<Thermal zone
+ UINT8 MsgFun85Zone2MsgReg1; ///<Thermal zone
+ UINT8 MsgFun85Zone2MsgReg2; ///<AL0 PWM level in percentage (0 - 100%)
+ UINT8 MsgFun85Zone2MsgReg3; ///<AL1 PWM level in percentage (0 - 100%)
+ UINT8 MsgFun85Zone2MsgReg4; ///<AL2 PWM level in percentage (0 - 100%)
+ UINT8 MsgFun85Zone2MsgReg5; ///<AL3 PWM level in percentage (0 - 100%)
+ UINT8 MsgFun85Zone2MsgReg6; ///<AL4 PWM level in percentage (0 - 100%)
+ UINT8 MsgFun85Zone2MsgReg7; ///<AL5 PWM level in percentage (0 - 100%)
+ UINT8 MsgFun85Zone2MsgReg8; ///<AL6 PWM level in percentage (0 - 100%)
+ UINT8 MsgFun85Zone2MsgReg9; ///<AL7 PWM level in percentage (0 - 100%)
+//
+//EC LDN9 function 85 zone 3
+//
+ UINT8 MsgFun85Zone3MsgReg0; ///<Thermal zone
+ UINT8 MsgFun85Zone3MsgReg1; ///<Thermal zone
+ UINT8 MsgFun85Zone3MsgReg2; ///<AL0 PWM level in percentage (0 - 100%)
+ UINT8 MsgFun85Zone3MsgReg3; ///<AL1 PWM level in percentage (0 - 100%)
+ UINT8 MsgFun85Zone3MsgReg4; ///<AL2 PWM level in percentage (0 - 100%)
+ UINT8 MsgFun85Zone3MsgReg5; ///<AL3 PWM level in percentage (0 - 100%)
+ UINT8 MsgFun85Zone3MsgReg6; ///<AL4 PWM level in percentage (0 - 100%)
+ UINT8 MsgFun85Zone3MsgReg7; ///<AL5 PWM level in percentage (0 - 100%)
+ UINT8 MsgFun85Zone3MsgReg8; ///<AL6 PWM level in percentage (0 - 100%)
+ UINT8 MsgFun85Zone3MsgReg9; ///<AL7 PWM level in percentage (0 - 100%)
+//
+//EC LDN9 function 89 TEMPIN channel 0
+//
+ UINT8 MsgFun89Zone0MsgReg0; ///<Thermal zone
+ UINT8 MsgFun89Zone0MsgReg1; ///<Thermal zone
+ UINT8 MsgFun89Zone0MsgReg2; ///<At DWORD bit 0-7
+ UINT8 MsgFun89Zone0MsgReg3; ///<At DWORD bit 15-8
+ UINT8 MsgFun89Zone0MsgReg4; ///<At DWORD bit 23-16
+ UINT8 MsgFun89Zone0MsgReg5; ///<At DWORD bit 31-24
+ UINT8 MsgFun89Zone0MsgReg6; ///<Ct DWORD bit 0-7
+ UINT8 MsgFun89Zone0MsgReg7; ///<Ct DWORD bit 15-8
+ UINT8 MsgFun89Zone0MsgReg8; ///<Ct DWORD bit 23-16
+ UINT8 MsgFun89Zone0MsgReg9; ///<Ct DWORD bit 31-24
+ UINT8 MsgFun89Zone0MsgRegA; ///<Mode bit 0-7
+//
+//EC LDN9 function 89 TEMPIN channel 1
+//
+ UINT8 MsgFun89Zone1MsgReg0; ///<Thermal zone
+ UINT8 MsgFun89Zone1MsgReg1; ///<Thermal zone
+ UINT8 MsgFun89Zone1MsgReg2; ///<At DWORD bit 0-7
+ UINT8 MsgFun89Zone1MsgReg3; ///<At DWORD bit 15-8
+ UINT8 MsgFun89Zone1MsgReg4; ///<At DWORD bit 23-16
+ UINT8 MsgFun89Zone1MsgReg5; ///<At DWORD bit 31-24
+ UINT8 MsgFun89Zone1MsgReg6; ///<Ct DWORD bit 0-7
+ UINT8 MsgFun89Zone1MsgReg7; ///<Ct DWORD bit 15-8
+ UINT8 MsgFun89Zone1MsgReg8; ///<Ct DWORD bit 23-16
+ UINT8 MsgFun89Zone1MsgReg9; ///<Ct DWORD bit 31-24
+ UINT8 MsgFun89Zone1MsgRegA; ///<Mode bit 0-7
+//
+//EC LDN9 function 89 TEMPIN channel 2
+//
+ UINT8 MsgFun89Zone2MsgReg0; ///<Thermal zone
+ UINT8 MsgFun89Zone2MsgReg1; ///<Thermal zone
+ UINT8 MsgFun89Zone2MsgReg2; ///<At DWORD bit 0-7
+ UINT8 MsgFun89Zone2MsgReg3; ///<At DWORD bit 15-8
+ UINT8 MsgFun89Zone2MsgReg4; ///<At DWORD bit 23-16
+ UINT8 MsgFun89Zone2MsgReg5; ///<At DWORD bit 31-24
+ UINT8 MsgFun89Zone2MsgReg6; ///<Ct DWORD bit 0-7
+ UINT8 MsgFun89Zone2MsgReg7; ///<Ct DWORD bit 15-8
+ UINT8 MsgFun89Zone2MsgReg8; ///<Ct DWORD bit 23-16
+ UINT8 MsgFun89Zone2MsgReg9; ///<Ct DWORD bit 31-24
+ UINT8 MsgFun89Zone2MsgRegA; ///<Mode bit 0-7
+//
+//EC LDN9 function 89 TEMPIN channel 3
+//
+ UINT8 MsgFun89Zone3MsgReg0; ///<Thermal zone
+ UINT8 MsgFun89Zone3MsgReg1; ///<Thermal zone
+ UINT8 MsgFun89Zone3MsgReg2; ///<At DWORD bit 0-7
+ UINT8 MsgFun89Zone3MsgReg3; ///<At DWORD bit 15-8
+ UINT8 MsgFun89Zone3MsgReg4; ///<At DWORD bit 23-16
+ UINT8 MsgFun89Zone3MsgReg5; ///<At DWORD bit 31-24
+ UINT8 MsgFun89Zone3MsgReg6; ///<Ct DWORD bit 0-7
+ UINT8 MsgFun89Zone3MsgReg7; ///<Ct DWORD bit 15-8
+ UINT8 MsgFun89Zone3MsgReg8; ///<Ct DWORD bit 23-16
+ UINT8 MsgFun89Zone3MsgReg9; ///<Ct DWORD bit 31-24
+ UINT8 MsgFun89Zone3MsgRegA; ///<Mode bit 0-7
+//
+// FLAG for Fun83/85/89 support
+//
+ UINT16 IMCFUNSupportBitMap; ///< Bit0=81FunZone0 support(1=On;0=Off); bit1-3=81FunZone1-Zone3;Bit4-7=83FunZone0-Zone3;Bit8-11=85FunZone0-Zone3;Bit11-15=89FunZone0-Zone3;
+} FCH_EC;
+
+///
+/// IMC structure
+///
+typedef struct _FCH_IMC {
+ UINT8 ImcEnable; ///< ImcEnable - IMC Enable
+ UINT8 ImcEnabled; ///< ImcEnabled - IMC Enable
+ UINT8 ImcSureBootTimer; ///< ImcSureBootTimer - IMc SureBootTimer function
+ FCH_EC EcStruct; ///< EC structure
+ UINT8 ImcEnableOverWrite; ///< OverWrite IMC with the EC structure
+ /// @li <b>00</b> - by default strapping
+ /// @li <b>01</b> - enable
+ /// @li <b>10</b> - disable
+ ///
+} FCH_IMC;
+
+
+///
+/// Hpet structure
+///
+typedef struct {
+ BOOLEAN HpetEnable; ///< HPET function switch
+
+ BOOLEAN HpetMsiDis; ///< HpetMsiDis - South Bridge HPET MSI Configuration
+ /// @par
+ /// @li <b>1</b> - disable
+ /// @li <b>0</b> - enable
+
+ UINT32 HpetBase; ///< HpetBase
+ /// @par
+ /// HPET Base address
+} FCH_HPET;
+
+
+///
+/// GCPU related parameters
+///
+typedef struct {
+ UINT8 AcDcMsg; ///< Send a message to CPU to indicate the power mode (AC vs battery)
+ /// @li <b>1</b> - disable
+ /// @li <b>0</b> - enable
+
+ UINT8 TimerTickTrack; ///< Send a message to CPU to indicate the latest periodic timer interval
+ /// @li <b>1</b> - disable
+ /// @li <b>0</b> - enable
+
+ UINT8 ClockInterruptTag; ///< Mark the periodic timer interrupt
+ /// @li <b>1</b> - disable
+ /// @li <b>0</b> - enable
+
+ UINT8 OhciTrafficHanding; ///< Cause CPU to break out from C state when USB OHCI has pending traffic
+ /// @li <b>1</b> - disable
+ /// @li <b>0</b> - enable
+
+ UINT8 EhciTrafficHanding; ///< Cause CPU to break out from C state when USB EHCI has pending traffic
+ /// @li <b>1</b> - disable
+ /// @li <b>0</b> - enable
+
+ UINT8 GcpuMsgCMultiCore; ///< Track of CPU C state by monitoring each core's C state message
+ /// @li <b>1</b> - disable
+ /// @li <b>0</b> - enable
+
+ UINT8 GcpuMsgCStage; ///< Enable the FCH C state coordination logic
+ /// @li <b>1</b> - disable
+ /// @li <b>0</b> - enable
+} FCH_GCPU;
+
+
+///
+/// Timer
+///
+typedef struct {
+ BOOLEAN Enable; ///< Whether to register timer SMI in POST
+ BOOLEAN StartNow; ///< Whether to start the SMI immediately during registration
+ UINT16 CycleDuration; ///< [14:0] - Actual cycle duration = CycleDuration + 1
+} TIMER_SMI;
+
+///
+/// CS support
+///
+typedef struct {
+ BOOLEAN FchCsD3Cold; ///< FCH Cs D3 Cold function
+ BOOLEAN FchCsHwReduced; ///< FCH Cs hardware reduced ACPI flag
+ BOOLEAN FchCsPwrBtn; ///< FCH Cs Power Button function
+ BOOLEAN FchCsAcDc; ///< FCH Cs AcDc function
+ BOOLEAN AsfNfcEnable; ///< FCH Cs NFC function
+ UINT8 AsfNfcInterruptPin; ///< NFC Interrupt pin define
+ UINT8 AsfNfcRegPuPin; ///< NFC RegPu pin define
+ UINT8 AsfNfcWakePin; ///< NFC Wake Pin define
+ UINT8 PowerButtonGpe; ///< GPE# used by Power Button device
+ UINT8 AcDcTimerGpe; ///< GPE# used by Timer device
+} FCH_CS;
+
+
+///
+/// MISC structure
+///
+typedef struct {
+ BOOLEAN NativePcieSupport; /// PCIe NativePcieSupport - Debug function. 1:Enabled, 0:Disabled
+ BOOLEAN S3Resume; /// S3Resume - Flag of ACPI S3 Resume.
+ BOOLEAN RebootRequired; /// RebootRequired - Flag of Reboot system is required.
+ UINT8 FchVariant; /// FchVariant - FCH Variant value.
+ UINT8 Cg2Pll; ///< CG2 PLL - 0:disable, 1:enable
+ TIMER_SMI LongTimer; ///< Long Timer SMI
+ TIMER_SMI ShortTimer; ///< Short Timer SMI
+ UINT32 FchCpuId; ///< Saving CpuId for FCH Module.
+ BOOLEAN NoneSioKbcSupport; ///< NoneSioKbcSupport - No KBC/SIO controller ( Turn on Inchip KBC emulation function )
+ FCH_CS FchCsSupport; ///< FCH Cs function structure
+} FCH_MISC;
+
+
+///
+/// SMBus structure
+///
+typedef struct {
+ UINT32 SmbusSsid; ///< SMBUS controller Subsystem ID
+} FCH_SMBUS;
+
+
+///
+/// Acpi structure
+///
+typedef struct {
+ UINT16 Smbus0BaseAddress; ///< Smbus0BaseAddress
+ /// @par
+ /// Smbus BASE Address
+ ///
+ UINT16 Smbus1BaseAddress; ///< Smbus1BaseAddress
+ /// @par
+ /// Smbus1 (ASF) BASE Address
+ ///
+ UINT16 SioPmeBaseAddress; ///< SioPmeBaseAddress
+ /// @par
+ /// SIO PME BASE Address
+ ///
+ UINT32 WatchDogTimerBase; ///< WatchDogTimerBase
+ /// @par
+ /// Watch Dog Timer Address
+ ///
+ UINT16 AcpiPm1EvtBlkAddr; ///< AcpiPm1EvtBlkAddr
+ /// @par
+ /// ACPI PM1 event block Address
+ ///
+ UINT16 AcpiPm1CntBlkAddr; ///< AcpiPm1CntBlkAddr
+ /// @par
+ /// ACPI PM1 Control block Address
+ ///
+ UINT16 AcpiPmTmrBlkAddr; ///< AcpiPmTmrBlkAddr
+ /// @par
+ /// ACPI PM timer block Address
+ ///
+ UINT16 CpuControlBlkAddr; ///< CpuControlBlkAddr
+ /// @par
+ /// ACPI CPU control block Address
+ ///
+ UINT16 AcpiGpe0BlkAddr; ///< AcpiGpe0BlkAddr
+ /// @par
+ /// ACPI GPE0 block Address
+ ///
+ UINT16 SmiCmdPortAddr; ///< SmiCmdPortAddr
+ /// @par
+ /// SMI command port Address
+ ///
+ UINT16 AcpiPmaCntBlkAddr; ///< AcpiPmaCntBlkAddr
+ /// @par
+ /// ACPI PMA Control block Address
+ ///
+ BOOLEAN AnyHt200MhzLink; ///< AnyHt200MhzLink
+ /// @par
+ /// HT Link Speed on 200MHz option for each CPU specific LDTSTP# (Force enable)
+ ///
+ BOOLEAN SpreadSpectrum; ///< SpreadSpectrum
+ /// @par
+ /// Spread Spectrum function
+ /// @li <b>0</b> - disable
+ /// @li <b>1</b> - enable
+ ///
+ POWER_FAIL PwrFailShadow; ///< PwrFailShadow = PM_Reg: 5Bh [3:0]
+ /// @par
+ /// @li <b>00</b> - Always off
+ /// @li <b>01</b> - Always on
+ /// @li <b>11</b> - Use previous
+ ///
+ UINT8 StressResetMode; ///< StressResetMode 01-10
+ /// @li <b>00</b> - Disabed
+ /// @li <b>01</b> - Io Write 0x64 with 0xfe
+ /// @li <b>10</b> - Io Write 0xcf9 with 0x06
+ /// @li <b>11</b> - Io Write 0xcf9 with 0x0e
+ ///
+ BOOLEAN MtC1eEnable; /// MtC1eEnable - Enable MtC1e
+ VOID* OemProgrammingTablePtr; /// Pointer of ACPI OEM table
+ UINT8 SpreadSpectrumOptions; /// SpreadSpectrumOptions - Spread Spectrum Option
+} FCH_ACPI;
+
+
+///
+/// HWM temp parameter structure
+///
+typedef struct _FCH_HWM_TEMP_PAR {
+ UINT16 At; ///< At
+ UINT16 Ct; ///< Ct
+ UINT8 Mode; ///< Mode BIT0:HiRatio BIT1:HiCurrent
+} FCH_HWM_TEMP_PAR;
+
+///
+/// HWM Current structure
+///
+typedef struct _FCH_HWM_CUR {
+ UINT16 FanSpeed[5]; ///< FanSpeed - fan Speed
+ UINT16 Temperature[5]; ///< Temperature - temperature
+ UINT16 Voltage[8]; ///< Voltage - voltage
+} FCH_HWM_CUR;
+
+///
+/// HWM fan control structure
+///
+typedef struct _FCH_HWM_FAN_CTR {
+ UINT8 InputControlReg00; /// Fan Input Control register, PM2 offset [0:4]0
+ UINT8 ControlReg01; /// Fan control register, PM2 offset [0:4]1
+ UINT8 FreqReg02; /// Fan frequency register, PM2 offset [0:4]2
+ UINT8 LowDutyReg03; /// Low Duty register, PM2 offset [0:4]3
+ UINT8 MedDutyReg04; /// Med Duty register, PM2 offset [0:4]4
+ UINT8 MultiplierReg05; /// Multiplier register, PM2 offset [0:4]5
+ UINT16 LowTempReg06; /// Low Temp register, PM2 offset [0:4]6
+ UINT16 MedTempReg08; /// Med Temp register, PM2 offset [0:4]8
+ UINT16 HighTempReg0A; /// High Temp register, PM2 offset [0:4]A
+ UINT8 LinearRangeReg0C; /// Linear Range register, PM2 offset [0:4]C
+ UINT8 LinearHoldCountReg0D; /// Linear Hold Count register, PM2 offset [0:4]D
+} FCH_HWM_FAN_CTR;
+
+///
+/// Hwm structure
+///
+typedef struct _FCH_HWM {
+ UINT8 HwMonitorEnable; ///< HwMonitorEnable
+ UINT32 HwmControl; ///< hwmControl
+ /// @par
+ /// HWM control configuration
+ /// @li <b>0</b> - HWM is Enabled
+ /// @li <b>1</b> - IMC is Enabled
+ ///
+ UINT8 FanSampleFreqDiv; ///< Sampling rate of Fan Speed
+ /// @li <b>00</b> - Base(22.5KHz)
+ /// @li <b>01</b> - Base(22.5KHz)/2
+ /// @li <b>10</b> - Base(22.5KHz)/4
+ /// @li <b>11</b> - Base(22.5KHz)/8
+ ///
+ UINT8 HwmFchtsiAutoPoll; ///< TSI Auto Polling
+ /// @li <b>0</b> - disable
+ /// @li <b>1</b> - enable
+ ///
+ UINT8 HwmFchtsiAutoPollStarted; ///< HwmSbtsiAutoPollStarted
+ UINT8 FanLinearEnhanceEn; ///< FanLinearEnhanceEn
+ UINT8 FanLinearHoldFix; ///< FanLinearHoldFix
+ UINT8 FanLinearRangeOutLimit; ///< FanLinearRangeOutLimit
+ UINT16 HwmCalibrationFactor; /// Calibration Factor
+ FCH_HWM_CUR HwmCurrent; /// HWM Current structure
+ FCH_HWM_CUR HwmCurrentRaw; /// HWM Current Raw structure
+ FCH_HWM_TEMP_PAR HwmTempPar[5]; /// HWM Temp parameter structure
+ FCH_HWM_FAN_CTR HwmFanControl[5]; /// HWM Fan Control structure
+ FCH_HWM_FAN_CTR HwmFanControlCooked[5]; /// HWM Fan Control structure
+} FCH_HWM;
+
+
+///
+/// Gec structure
+///
+typedef struct {
+ BOOLEAN GecEnable; ///< GecEnable - GEC function switch
+ UINT8 GecPhyStatus; /// GEC PHY Status
+ UINT8 GecPowerPolicy; /// GEC Power Policy
+ /// @li <b>00</b> - GEC is powered down in S3 and S5
+ /// @li <b>01</b> - GEC is powered down only in S5
+ /// @li <b>10</b> - GEC is powered down only in S3
+ /// @li <b>11</b> - GEC is never powered down
+ ///
+ UINT8 GecDebugBus; /// GEC Debug Bus
+ /// @li <b>0</b> - disable
+ /// @li <b>1</b> - enable
+ ///
+ UINT32 GecShadowRomBase; ///< GecShadowRomBase
+ /// @par
+ /// GEC (NIC) SHADOWROM BASE Address
+ ///
+ VOID *PtrDynamicGecRomAddress; /// Pointer of Dynamic GEC ROM Address
+} FCH_GEC;
+
+
+///
+/// _ABTblEntry - AB link register table R/W structure
+///
+typedef struct _AB_TBL_ENTRY {
+ UINT8 RegType; /// RegType : AB Register Type (ABCFG, AXCFG and so on)
+ UINT32 RegIndex; /// RegIndex : AB Register Index
+ UINT32 RegMask; /// RegMask : AB Register Mask
+ UINT32 RegData; /// RegData : AB Register Data
+} AB_TBL_ENTRY;
+
+///
+/// AB structure
+///
+typedef struct {
+ BOOLEAN AbMsiEnable; ///< ABlink MSI capability
+ UINT8 ALinkClkGateOff; /// Alink Clock Gate-Off function - 0:disable, 1:enable *KR
+ UINT8 BLinkClkGateOff; /// Blink Clock Gate-Off function - 0:disable, 1:enable *KR
+ UINT8 AbClockGating; /// AB Clock Gating - 0:disable, 1:enable *KR
+ UINT8 GppClockGating; /// GPP Clock Gating - 0:disable, 1:enable
+ UINT8 UmiL1TimerOverride; /// UMI L1 inactivity timer overwrite value
+ UINT8 UmiLinkWidth; /// UMI Link Width
+ UINT8 UmiDynamicSpeedChange; /// UMI Dynamic Speed Change - 0:disable, 1:enable
+ UINT8 PcieRefClockOverClocking; /// PCIe Ref Clock OverClocking value
+ UINT8 UmiGppTxDriverStrength; /// UMI GPP TX Driver Strength
+ BOOLEAN NbSbGen2; /// UMI link Gen2 - 0:Gen1, 1:Gen2
+ UINT8 PcieOrderRule; /// PCIe Order Rule - 0:disable, 1:enable *KR AB Posted Pass Non-Posted
+ UINT8 SlowSpeedAbLinkClock; /// Slow Speed AB Link Clock - 0:disable, 1:enable *KR
+ BOOLEAN ResetCpuOnSyncFlood; /// Reset Cpu On Sync Flood - 0:disable, 1:enable *KR
+ BOOLEAN AbDmaMemoryWrtie3264B; /// AB DMA Memory Write 32/64 BYTE Support *KR only
+ BOOLEAN AbMemoryPowerSaving; /// AB Memory Power Saving *KR only
+ BOOLEAN SbgDmaMemoryWrtie3264ByteCount; /// SBG DMA Memory Write 32/64 BYTE Count Support *KR only
+ BOOLEAN SbgMemoryPowerSaving; /// SBG Memory Power Saving *KR only
+} FCH_AB;
+
+
+/**
+ * PCIE_CAP_ID - PCIe Cap ID
+ *
+ */
+#define PCIE_CAP_ID 0x10
+
+///
+/// FCH_GPP_PORT_CONFIG - Fch GPP port config structure
+///
+typedef struct {
+ BOOLEAN PortPresent; ///< Port connection
+ /// @par
+ /// @li <b>0</b> - Port doesn't have slot. No need to train the link
+ /// @li <b>1</b> - Port connection defined and needs to be trained
+ ///
+ BOOLEAN PortDetected; ///< Link training status
+ /// @par
+ /// @li <b>0</b> - EP not detected
+ /// @li <b>1</b> - EP detected
+ ///
+ BOOLEAN PortIsGen2; ///< Port link speed configuration
+ /// @par
+ /// @li <b>00</b> - Auto
+ /// @li <b>01</b> - Forced GEN1
+ /// @li <b>10</b> - Forced GEN2
+ /// @li <b>11</b> - Reserved
+ ///
+ BOOLEAN PortHotPlug; ///< Support hot plug?
+ /// @par
+ /// @li <b>0</b> - No support
+ /// @li <b>1</b> - support
+ ///
+ UINT8 PortMisc; /// PortMisc - Reserved
+} FCH_GPP_PORT_CONFIG;
+
+///
+/// GPP structure
+///
+typedef struct {
+ FCH_GPP_PORT_CONFIG PortCfg[4]; /// GPP port configuration structure
+ GPP_LINKMODE GppLinkConfig; ///< GppLinkConfig - PCIE_GPP_Enable[3:0]
+ /// @li <b>0000</b> - Port ABCD -> 4:0:0:0
+ /// @li <b>0010</b> - Port ABCD -> 2:2:0:0
+ /// @li <b>0011</b> - Port ABCD -> 2:1:1:0
+ /// @li <b>0100</b> - Port ABCD -> 1:1:1:1
+ ///
+ BOOLEAN GppFunctionEnable; ///< GPP Function - 0:disable, 1:enable
+ BOOLEAN GppToggleReset; ///< Toggle GPP core reset
+ UINT8 GppHotPlugGeventNum; ///< Hotplug GEVENT # - valid value 0-31
+ UINT8 GppFoundGfxDev; ///< Gpp Found Gfx Device
+ /// @li <b>0</b> - Not found
+ /// @li <b>1</b> - Found
+ ///
+ BOOLEAN GppGen2; ///< GPP Gen2 - 0:disable, 1:enable
+ UINT8 GppGen2Strap; ///< GPP Gen2 Strap - 0:disable, 1:enable, FCH itself uses this
+ BOOLEAN GppMemWrImprove; ///< GPP Memory Write Improve - 0:disable, 1:enable
+ BOOLEAN GppUnhidePorts; ///< GPP Unhide Ports - 0:disable, 1:enable
+ UINT8 GppPortAspm; ///< GppPortAspm - ASPM state for all GPP ports
+ /// @li <b>01</b> - Disabled
+ /// @li <b>01</b> - L0s
+ /// @li <b>10</b> - L1
+ /// @li <b>11</b> - L0s + L1
+ ///
+ BOOLEAN GppLaneReversal; ///< GPP Lane Reversal - 0:disable, 1:enable
+ BOOLEAN GppPhyPllPowerDown; ///< GPP PHY PLL Power Down - 0:disable, 1:enable
+ BOOLEAN GppDynamicPowerSaving; ///< GPP Dynamic Power Saving - 0:disable, 1:enable
+ BOOLEAN PcieAer; ///< PcieAer - Advanced Error Report: 0/1-disable/enable
+ BOOLEAN PcieRas; ///< PCIe RAS - 0:disable, 1:enable
+ BOOLEAN PcieCompliance; ///< PCIe Compliance - 0:disable, 1:enable
+ BOOLEAN PcieSoftwareDownGrade; ///< PCIe Software Down Grade
+ BOOLEAN UmiPhyPllPowerDown; ///< UMI PHY PLL Power Down - 0:disable, 1:enable
+ BOOLEAN SerialDebugBusEnable; ///< Serial Debug Bus Enable
+ UINT8 GppHardwareDownGrade; ///< GppHardwareDownGrade - Gpp HW Down Grade function 0:Disable, 1-4: portA-D
+ UINT8 GppL1ImmediateAck; ///< GppL1ImmediateAck - Gpp L1 Immediate ACK 0: enable, 1: disable
+ BOOLEAN NewGppAlgorithm; ///< NewGppAlgorithm - New GPP procedure
+ UINT8 HotPlugPortsStatus; ///< HotPlugPortsStatus - Save Hot-Plug Ports Status
+ UINT8 FailPortsStatus; ///< FailPortsStatus - Save Failure Ports Status
+ UINT8 GppPortMinPollingTime; ///< GppPortMinPollingTime - Min. Polling time for Gpp Port Training
+ BOOLEAN IsCapsuleMode; ///< IsCapsuleMode - Support Capsule Mode in FCH
+} FCH_GPP;
+
+/// FCH USB Over Current Data Block
+typedef struct {
+ UINT8 Usb1OcPinMap[5]; ///< USB1 over current pin mapping
+ UINT8 Usb2OcPinMap[5]; ///< USB2 over current pin mapping
+ UINT8 Usb3OcPinMap[4]; ///< USB3 over current pin mapping
+ UINT8 Usb4OcPinMap[2]; ///< USB4 over current pin mapping
+ UINT8 Xhci0OcPinMap[2]; ///< XHCI0 over current pin mapping
+ UINT8 Xhci1OcPinMap[2]; ///< XHCI1 over current pin mapping
+} FCH_USB_OC;
+
+
+///
+/// FCH USB sturcture
+///
+typedef struct {
+ BOOLEAN Ohci1Enable; ///< OHCI1 controller enable
+ BOOLEAN Ohci2Enable; ///< OHCI2 controller enable
+ BOOLEAN Ohci3Enable; ///< OHCI3 controller enable
+ BOOLEAN Ohci4Enable; ///< OHCI4 controller enable
+ BOOLEAN Ehci1Enable; ///< EHCI1 controller enable
+ BOOLEAN Ehci2Enable; ///< EHCI2 controller enable
+ BOOLEAN Ehci3Enable; ///< EHCI3 controller enable
+ BOOLEAN Xhci0Enable; ///< XHCI0 controller enable
+ BOOLEAN Xhci1Enable; ///< XHCI1 controller enable
+ BOOLEAN UsbMsiEnable; ///< USB MSI capability
+ UINT32 OhciSsid; ///< OHCI SSID
+ UINT32 Ohci4Ssid; ///< OHCI 4 SSID
+ UINT32 EhciSsid; ///< EHCI SSID
+ UINT32 XhciSsid; ///< XHCI SSID
+ BOOLEAN UsbPhyPowerDown; ///< USB PHY Power Down - 0:disable, 1:enable
+ UINT32 UserDefineXhciRomAddr; ///< XHCI ROM address define by platform BIOS
+ UINT8 Ehci1Phy[5]; ///< EHCI1 USB PHY Driving Strength value table
+ UINT8 Ehci2Phy[5]; ///< EHCI2 USB PHY Driving Strength value table
+ UINT8 Ehci3Phy[4]; ///< EHCI3 USB PHY Driving Strength value table
+ UINT8 Xhci20Phy[4]; ///< XHCI USB 2.0 PHY Driving Strength value table
+ UINT8 Ehci1DebugPortSel; ///< DebugPortSel for Ehci1 Hub
+ /// @li <b>000</b> - Disable
+ /// @li <b>001</b> - HubDownStreamPort0
+ /// @li <b>010</b> - HubDownStreamPort1
+ /// @li <b>011</b> - HubDownStreamPort2
+ /// @li <b>100</b> - HubDownStreamPort3
+ UINT8 Ehci2DebugPortSel; ///< DebugPortSel for Ehci2 Hub
+ /// @li <b>000</b> - Disable
+ /// @li <b>001</b> - HubDownStreamPort0
+ /// @li <b>010</b> - HubDownStreamPort1
+ /// @li <b>011</b> - HubDownStreamPort2
+ /// @li <b>100</b> - HubDownStreamPort3
+ UINT8 Ehci3DebugPortSel; ///< DebugPortSel for Ehci3 Hub
+ /// @li <b>000</b> - Disable
+ /// @li <b>001</b> - HubDownStreamPort0
+ /// @li <b>010</b> - HubDownStreamPort1
+ /// @li <b>011</b> - HubDownStreamPort2
+ /// @li <b>100</b> - HubDownStreamPort3
+ FCH_USB_OC FchUsbOcMap; ///< Fch USB OC Map
+} FCH_USB;
+
+
+/// Private: FCH_DATA_BLOCK_RESET
+typedef struct _FCH_RESET_DATA_BLOCK {
+ AMD_CONFIG_PARAMS *StdHeader; ///< Header structure
+ FCH_RESET_INTERFACE FchReset; ///< Reset interface
+
+ UINT8 FastSpeed; ///< SPI FastSpeed: 1-66MHz, 2-33MHz, 3-22MHz, 4-16.5MHz, 5-100Mhz
+ UINT8 WriteSpeed; ///< SPI Write Speed: 1-66MHz, 2-33MHz, 3-22MHz, 4-16.5MHz, 5-100Mhz
+ UINT8 Mode; ///< SPI Mode
+ /// @li <b>101</b> - Qual-io 1-4-4
+ /// @li <b>100</b> - Dual-io 1-2-2
+ /// @li <b>011</b> - Qual-io 1-1-4
+ /// @li <b>010</b> - Dual-io 1-1-2
+ /// @li <b>111</b> - FastRead
+ /// @li <b>110</b> - Normal
+ ///
+ UINT8 AutoMode; ///< SPI Auto Mode - 0:disable, 1:enable
+ UINT8 BurstWrite; ///< SPI Burst Write - 0:disable, 1:enable
+ BOOLEAN Sata6AhciCap; ///< SATA 6 AHCI Capability - TRUE:enable, FALSE:disable
+ UINT8 Cg2Pll; ///< CG2 PLL - 0:disable, 1:enable
+ BOOLEAN EcKbd; ///< EC KBD - 0:disable, 1:enable
+ BOOLEAN LegacyFree; ///< Legacy Free - 0:disable, 1:enable
+ BOOLEAN SataSetMaxGen2; ///< SATA enable maximum GEN2
+ UINT8 SataClkMode; ///< SATA reference clock selector and divider
+ UINT8 SataModeReg; ///< Output: SATAConfig PMIO:0xDA
+ BOOLEAN SataInternal100Spread; ///< SATA internal 100MHz spread ON/OFF
+ UINT8 SpiSpeed; ///< SPI NormSpeed: 1-66MHz, 2-33MHz, 3-22MHz, 4-16.5MHz, 5-100Mhz
+// UINT32 SPI100_RX_Timing_Config_Register_38; ///< SPI100_RX_Timing_Config_Register_38
+// UINT16 SPI100_RX_Timing_Config_Register_3C; ///< SPI100_RX_Timing_Config_Register_3C
+// UINT8 SpiProtectEn0_1d_34; ///
+ UINT8 SPI100_Enable; ///
+ BOOLEAN EcChannel0; ///< Enable EC channel 0
+ FCH_GPP Gpp; ///< GPP subsystem
+ FCH_SPI Spi; ///< SPI subsystem
+ BOOLEAN QeEnabled; /// Quad Mode Enabled
+ BOOLEAN FchOscout1ClkContinous; ///< FCH OSCOUT1_CLK Continous
+ VOID* EarlyOemGpioTable; /// Pointer of Early OEM GPIO table
+// VOID* OemSpiDeviceTable; /// Pointer of OEM Spi Device table
+ VOID* OemResetProgrammingTablePtr; /// Pointer of ACPI OEM table
+} FCH_RESET_DATA_BLOCK;
+
+
+/// Private: FCH_DATA_BLOCK
+typedef struct _FCH_DATA_BLOCK {
+ AMD_CONFIG_PARAMS *StdHeader; ///< Header structure
+
+ FCH_ACPI HwAcpi; ///< ACPI structure
+ FCH_AB Ab; ///< AB structure
+ FCH_GPP Gpp; ///< GPP structure
+ FCH_USB Usb; ///< USB structure
+ FCH_SATA Sata; ///< SATA structure
+ FCH_SMBUS Smbus; ///< SMBus structure
+ FCH_IDE Ide; ///< IDE structure
+ FCH_AZALIA Azalia; ///< Azalia structure
+ FCH_SPI Spi; ///< SPI structure
+ FCH_PCIB Pcib; ///< PCIB structure
+ FCH_GEC Gec; ///< GEC structure
+ FCH_SD Sd; ///< SD structure
+ FCH_HWM Hwm; ///< Hardware Moniter structure
+ FCH_IR Ir; ///< IR structure
+ FCH_HPET Hpet; ///< HPET structure
+ FCH_GCPU Gcpu; ///< GCPU structure
+ FCH_IMC Imc; ///< IMC structure
+ FCH_MISC Misc; ///< MISC structure
+ VOID* PostOemGpioTable; /// Pointer of Post OEM GPIO table
+} FCH_DATA_BLOCK;
+
+#pragma pack (pop)
+
+#endif
diff --git a/src/vendorcode/amd/pi/00730F01/Proc/Fch/Common/FchDef.h b/src/vendorcode/amd/pi/00730F01/Proc/Fch/Common/FchDef.h
new file mode 100644
index 0000000..13906c5
--- /dev/null
+++ b/src/vendorcode/amd/pi/00730F01/Proc/Fch/Common/FchDef.h
@@ -0,0 +1,400 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * FCH routine definition
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: FCH
+ * @e \$Revision: 281178 $ @e \$Date: 2013-12-18 02:14:15 -0600 (Wed, 18 Dec 2013) $
+ *
+ */
+/*****************************************************************************
+ *
+ * Copyright (c) 2008 - 2014, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ***************************************************************************/
+
+#ifndef _FCH_DEF_H_
+#define _FCH_DEF_H_
+
+
+UINT32 ReadAlink (IN UINT32 Index, IN AMD_CONFIG_PARAMS *StdHeader);
+VOID WriteAlink (IN UINT32 Index, IN UINT32 Data, IN AMD_CONFIG_PARAMS *StdHeader);
+VOID RwAlink (IN UINT32 Index, IN UINT32 AndMask, IN UINT32 OrMask, IN AMD_CONFIG_PARAMS *StdHeader);
+VOID ReadMem (IN UINT32 Address, IN UINT8 OpFlag, IN VOID *ValuePtr);
+VOID WriteMem (IN UINT32 Address, IN UINT8 OpFlag, IN VOID *ValuePtr);
+VOID RwMem (IN UINT32 Address, IN UINT8 OpFlag, IN UINT32 Mask, IN UINT32 Data);
+VOID ReadPci (IN UINT32 Address, IN UINT8 OpFlag, IN VOID *Value, IN AMD_CONFIG_PARAMS *StdHeader);
+VOID WritePci (IN UINT32 Address, IN UINT8 OpFlag, IN VOID *Value, IN AMD_CONFIG_PARAMS *StdHeader);
+VOID RwPci (IN UINT32 Address, IN UINT8 OpFlag, IN UINT32 Mask, IN UINT32 Data, IN AMD_CONFIG_PARAMS *StdHeader);
+VOID ProgramPciByteTable (IN REG8_MASK* pPciByteTable, IN UINT16 dwTableSize, IN AMD_CONFIG_PARAMS *StdHeader);
+VOID ProgramFchAcpiMmioTbl (IN ACPI_REG_WRITE *pAcpiTbl, IN AMD_CONFIG_PARAMS *StdHeader);
+VOID ProgramFchSciMapTbl (IN SCI_MAP_CONTROL *pSciMapTbl, IN FCH_RESET_DATA_BLOCK *FchResetDataBlock);
+VOID ProgramFchGpioTbl (IN GPIO_CONTROL *pGpioTbl);
+VOID ProgramFchSataPhyTbl (IN SATA_PHY_CONTROL *pSataPhyTbl, IN FCH_RESET_DATA_BLOCK *FchResetDataBlock);
+VOID GetChipSysMode (IN VOID *Value, IN AMD_CONFIG_PARAMS *StdHeader);
+BOOLEAN IsImcEnabled (IN AMD_CONFIG_PARAMS *StdHeader);
+VOID ReadPmio (IN UINT8 Address, IN UINT8 OpFlag, IN VOID *Value, IN AMD_CONFIG_PARAMS *StdHeader);
+VOID WritePmio (IN UINT8 Address, IN UINT8 OpFlag, IN VOID *Value, IN AMD_CONFIG_PARAMS *StdHeader);
+VOID RwPmio (IN UINT8 Address, IN UINT8 OpFlag, IN UINT32 AndMask, IN UINT32 OrMask, IN AMD_CONFIG_PARAMS *StdHeader);
+VOID ReadPmio2 (IN UINT8 Address, IN UINT8 OpFlag, IN VOID *Value, IN AMD_CONFIG_PARAMS *StdHeader);
+VOID WritePmio2 (IN UINT8 Address, IN UINT8 OpFlag, IN VOID *Value, IN AMD_CONFIG_PARAMS *StdHeader);
+VOID RwPmio2 (IN UINT8 Address, IN UINT8 OpFlag, IN UINT32 AndMask, IN UINT32 OrMask, IN AMD_CONFIG_PARAMS *StdHeader);
+VOID ReadBiosram (IN UINT8 Address, IN UINT8 OpFlag, IN VOID *Value, IN AMD_CONFIG_PARAMS *StdHeader);
+VOID WriteBiosram (IN UINT8 Address, IN UINT8 OpFlag, IN VOID *Value, IN AMD_CONFIG_PARAMS *StdHeader);
+VOID GetFchAcpiMmioBase (OUT UINT32 *AcpiMmioBase, IN AMD_CONFIG_PARAMS *StdHeader);
+VOID GetFchAcpiPmBase (OUT UINT16 *AcpiPmBase, IN AMD_CONFIG_PARAMS *StdHeader);
+UINT8 ReadFchSleepType (IN AMD_CONFIG_PARAMS *StdHeader);
+UINT8 ReadFchChipsetRevision (IN AMD_CONFIG_PARAMS *StdHeader);
+UINT8 GetFchRevision (IN AMD_CONFIG_PARAMS *StdHeader);
+BOOLEAN CheckAvalonRevisionA0 (IN AMD_CONFIG_PARAMS *StdHeader);
+
+///
+/// Fch Ab Routines
+///
+/// Pei Phase
+///
+VOID FchInitResetAb (IN VOID* FchDataPtr);
+VOID FchProgramAbPowerOnReset (IN VOID* FchDataPtr);
+///
+/// Dxe Phase
+///
+VOID FchInitEnvAb (IN VOID* FchDataPtr);
+VOID FchInitEnvAbSpecial (IN VOID* FchDataPtr);
+VOID FchInitMidAb (IN VOID* FchDataPtr);
+VOID FchInitLateAb (IN VOID* FchDataPtr);
+///
+/// Other Public Routines
+///
+VOID FchInitEnvAbLinkInit (IN VOID* FchDataPtr);
+BOOLEAN IsUmiOneLaneGen1Mode (IN AMD_CONFIG_PARAMS *StdHeader);
+VOID FchAbLateProgram (IN VOID* FchDataPtr);
+VOID ProgramPcieNativeMode (IN VOID* FchDataPtr);
+
+///
+/// Fch Azalia Routines
+///
+/// Pei Phase
+///
+VOID FchInitResetAzalia (IN VOID *FchDataPtr);
+///
+/// Dxe Phase
+///
+VOID FchInitEnvAzalia (IN VOID *FchDataPtr);
+VOID FchInitMidAzalia (IN VOID *FchDataPtr);
+VOID FchInitLateAzalia (IN VOID *FchDataPtr);
+
+///
+/// Fch HwAcpi Routines
+///
+/// Pei Phase
+///
+VOID FchInitResetHwAcpiP (IN VOID *FchDataPtr);
+VOID FchInitResetHwAcpi (IN VOID *FchDataPtr);
+VOID ProgramFchHwAcpiResetP (IN VOID *FchDataPtr);
+///
+/// Dxe Phase
+///
+VOID FchInitEnvHwAcpiP (IN VOID *FchDataPtr);
+VOID FchInitEnvHwAcpi (IN VOID *FchDataPtr);
+VOID ProgramEnvPFchAcpiMmio (IN VOID *FchDataPtr);
+VOID ProgramFchEnvHwAcpiPciReg (IN VOID *FchDataPtr);
+VOID ProgramSpecificFchInitEnvAcpiMmio (IN VOID *FchDataPtr);
+VOID ProgramFchEnvSpreadSpectrum (IN VOID *FchDataPtr);
+VOID FchInitMidHwAcpi (IN VOID *FchDataPtr);
+VOID FchInitLateHwAcpi (IN VOID *FchDataPtr);
+
+///
+/// Other Public Routines
+///
+VOID HpetInit (IN VOID *FchDataPtr);
+VOID C3PopupSetting (IN VOID *FchDataPtr);
+VOID MtC1eEnable (IN VOID *FchDataPtr);
+VOID GcpuRelatedSetting (IN VOID *FchDataPtr);
+VOID StressResetModeLate (IN VOID *FchDataPtr);
+
+///
+/// Fch Hwm Routines
+///
+/// Pei Phase
+///
+VOID FchInitResetHwm (IN VOID* FchDataPtr);
+///
+/// Dxe Phase
+///
+VOID FchInitEnvHwm (IN VOID* FchDataPtr);
+VOID FchInitMidHwm (IN VOID* FchDataPtr);
+VOID FchInitLateHwm (IN VOID* FchDataPtr);
+///
+/// Other Public Routines
+///
+VOID HwmInitRegister (IN VOID* FchDataPtr);
+VOID HwmProcessParameter (IN VOID* FchDataPtr);
+VOID HwmSetRegister (IN VOID* FchDataPtr);
+VOID HwmGetCalibrationFactor (IN VOID* FchDataPtr);
+VOID HwmFchtsiAutoPolling (IN VOID* FchDataPtr);
+VOID HwmGetRawData (IN VOID* FchDataPtr);
+VOID HwmCaculate (IN VOID* FchDataPtr);
+VOID HwmFchtsiAutoPollingOff (IN VOID* FchDataPtr);
+VOID FchECfancontrolservice (IN VOID* FchDataPtr);
+
+///
+/// Fch Imc Routines
+///
+/// Pei Phase
+///
+VOID FchInitResetImc (IN VOID *FchDataPtr);
+VOID FchInitResetEc (IN VOID *FchDataPtr);
+///
+/// Dxe Phase
+///
+VOID FchInitEnvImc (IN VOID *FchDataPtr);
+VOID FchInitMidImc (IN VOID *FchDataPtr);
+VOID FchInitLateImc (IN VOID *FchDataPtr);
+VOID FchInitEnvEc (IN VOID *FchDataPtr);
+VOID FchInitMidEc (IN VOID *FchDataPtr);
+VOID FchInitLateEc (IN VOID *FchDataPtr);
+///
+/// Other Public Routines
+///
+VOID EnterEcConfig (IN AMD_CONFIG_PARAMS *StdHeader);
+VOID ExitEcConfig (IN AMD_CONFIG_PARAMS *StdHeader);
+VOID ReadEc8 (IN UINT8 Address, IN UINT8* Value, IN AMD_CONFIG_PARAMS *StdHeader);
+VOID WriteEc8 (IN UINT8 Address, IN UINT8* Value, IN AMD_CONFIG_PARAMS *StdHeader);
+VOID RwEc8 (IN UINT8 Address, IN UINT8 AndMask, IN UINT8 OrMask, IN AMD_CONFIG_PARAMS *StdHeader);
+VOID WriteECmsg (IN UINT8 Address, IN UINT8 OpFlag, IN VOID* Value, IN AMD_CONFIG_PARAMS *StdHeader);
+VOID ReadECmsg (IN UINT8 Address, IN UINT8 OpFlag, OUT VOID* Value, IN AMD_CONFIG_PARAMS *StdHeader);
+VOID WaitForEcLDN9MailboxCmdAck (IN AMD_CONFIG_PARAMS *StdHeader);
+
+VOID ImcSleep (IN VOID *FchDataPtr);
+VOID ImcEnableSurebootTimer (IN VOID *FchDataPtr);
+VOID ImcDisarmSurebootTimer (IN VOID *FchDataPtr);
+VOID ImcDisableSurebootTimer (IN VOID *FchDataPtr);
+VOID ImcWakeup (IN VOID *FchDataPtr);
+VOID ImcIdle (IN VOID *FchDataPtr);
+BOOLEAN ValidateImcFirmware (IN VOID *FchDataPtr);
+VOID SoftwareToggleImcStrapping (IN VOID *FchDataPtr);
+VOID ImcCrashReset (IN VOID *FchDataPtr);
+VOID SoftwareDisableImc (IN VOID *FchDataPtr);
+
+
+///
+/// Fch Ir Routines
+///
+/// Dxe Phase
+///
+VOID FchInitEnvIr (IN VOID* FchDataPtr);
+VOID FchInitMidIr (IN VOID* FchDataPtr);
+VOID FchInitLateIr (IN VOID* FchDataPtr);
+
+///
+/// Fch SATA Routines
+///
+/// Pei Phase
+///
+VOID FchInitResetSata (IN VOID *FchDataPtr);
+VOID FchInitResetSataProgram (IN VOID *FchDataPtr);
+///
+/// Dxe Phase
+///
+VOID FchInitMidSata (IN VOID *FchDataPtr);
+VOID FchInitEnvSata (IN VOID *FchDataPtr);
+VOID FchInitEnvProgramSataPciRegs (IN VOID *FchDataPtr);
+VOID FchInitMidProgramSataRegs (IN VOID *FchDataPtr);
+VOID FchInitLateProgramSataRegs (IN VOID *FchDataPtr);
+
+VOID FchInitLateSata (IN VOID *FchDataPtr);
+VOID FchInitEnvSataIde (IN VOID *FchDataPtr);
+VOID FchInitMidSataIde (IN VOID *FchDataPtr);
+VOID FchInitLateSataIde (IN VOID *FchDataPtr);
+VOID FchInitEnvSataAhci (IN VOID *FchDataPtr);
+VOID FchInitMidSataAhci (IN VOID *FchDataPtr);
+VOID FchInitLateSataAhci (IN VOID *FchDataPtr);
+VOID FchInitEnvSataRaid (IN VOID *FchDataPtr);
+VOID FchInitMidSataRaid (IN VOID *FchDataPtr);
+VOID FchInitLateSataRaid (IN VOID *FchDataPtr);
+VOID FchInitEnvSataIde2Ahci (IN VOID *FchDataPtr);
+VOID FchInitMidSataIde2Ahci (IN VOID *FchDataPtr);
+VOID FchInitLateSataIde2Ahci (IN VOID *FchDataPtr);
+
+VOID SataAhciSetDeviceNumMsi (IN VOID *FchDataPtr);
+VOID SataRaidSetDeviceNumMsi (IN VOID *FchDataPtr);
+VOID SataIde2AhciSetDeviceNumMsi (IN VOID *FchDataPtr);
+VOID SataSetIrqIntResource (IN VOID *FchDataPtr, IN AMD_CONFIG_PARAMS *StdHeader);
+VOID SataBar5setting (IN VOID *FchDataPtr, IN UINT32 *Bar5Ptr);
+VOID SataEnableWriteAccess (IN AMD_CONFIG_PARAMS *StdHeader);
+VOID SataDisableWriteAccess (IN AMD_CONFIG_PARAMS *StdHeader);
+VOID SataSetDeviceNumMsi (IN VOID *FchDataPtr);
+VOID FchSataSetDeviceNumMsi (IN VOID *FchDataPtr);
+VOID ShutdownUnconnectedSataPortClock (IN VOID *FchDataPtr, IN UINT32 Bar5);
+VOID FchShutdownUnconnectedSataPortClock (IN VOID *FchDataPtr, IN UINT32 Bar5);
+VOID SataDriveDetection (IN VOID *FchDataPtr, IN UINT32 *Bar5Ptr);
+VOID FchSataDriveDetection (IN VOID *FchDataPtr, IN UINT32 *Bar5Ptr);
+VOID FchSataGpioInitial (IN VOID *FchDataPtr);
+VOID SataBar5RegSet (IN VOID *FchDataPtr);
+VOID SataSetPortGenMode (IN VOID *FchDataPtr);
+VOID FchSataSetPortGenMode (IN VOID *FchDataPtr);
+VOID FchProgramSataPhy (IN AMD_CONFIG_PARAMS *StdHeader);
+VOID FchSataDriveFpga (IN VOID *FchDataPtr);
+VOID FchInitEnvSataRaidProgram (IN VOID *FchDataPtr);
+
+///
+/// FCH USB Controller Public Function
+///
+/// Pei Phase
+///
+VOID FchInitResetUsb (IN VOID *FchDataPtr);
+VOID FchInitResetEhci (IN VOID *FchDataPtr);
+VOID FchInitResetXhci (IN VOID *FchDataPtr);
+VOID FchInitResetXhciProgram (IN VOID *FchDataPtr);
+///
+/// Dxe Phase
+///
+VOID FchInitEnvUsb (IN VOID *FchDataPtr);
+VOID FchInitMidUsb (IN VOID *FchDataPtr);
+VOID FchInitLateUsb (IN VOID *FchDataPtr);
+VOID FchInitEnvUsbEhci (IN VOID *FchDataPtr);
+VOID FchInitMidUsbEhci (IN VOID *FchDataPtr);
+VOID FchInitLateUsbEhci (IN VOID *FchDataPtr);
+VOID FchEhciDebugPortService (IN VOID *FchDataPtr);
+VOID FchInitEnvUsbXhci (IN VOID *FchDataPtr);
+VOID FchInitMidUsbXhci (IN VOID *FchDataPtr);
+VOID FchInitLateUsbXhci (IN VOID *FchDataPtr);
+VOID FchInitMidUsbEhci1 (IN FCH_DATA_BLOCK *FchDataPtr);
+VOID FchInitMidUsbEhci2 (IN FCH_DATA_BLOCK *FchDataPtr);
+VOID FchInitMidUsbEhci3 (IN FCH_DATA_BLOCK *FchDataPtr);
+///
+/// Other Public Routines
+///
+VOID FchSetUsbEnableReg (IN FCH_DATA_BLOCK *FchDataPtr);
+VOID FchEhciInitAfterPciInit (IN UINT32 Value, IN FCH_DATA_BLOCK* FchDataPtr);
+VOID FchXhciInitBeforePciInit (IN FCH_DATA_BLOCK* FchDataPtr);
+VOID FchXhciInitIndirectReg (IN FCH_DATA_BLOCK* FchDataPtr);
+VOID FchInitLateUsbXhciProgram (IN VOID *FchDataPtr);
+VOID FchXhciPowerSavingProgram (IN FCH_DATA_BLOCK* FchDataPtr);
+VOID FchXhciUsbPhyCalibrated (IN FCH_DATA_BLOCK* FchDataPtr);
+UINT8 FchUsbCommonPhyCalibration (IN FCH_DATA_BLOCK* FchDataPtr);
+VOID FchUsbOverCurrentControl (IN VOID *FchDataPtr);
+
+///
+/// Fch Sd Routines
+///
+VOID FchInitEnvSd (IN VOID *FchDataPtr);
+VOID FchInitMidSd (IN VOID *FchDataPtr);
+VOID FchInitLateSd (IN VOID *FchDataPtr);
+
+///
+/// Other Public Routines
+///
+
+VOID FchInitEnvSdProgram (IN VOID *FchDataPtr);
+
+///
+/// Fch Spi Routines
+///
+/// Pei Phase
+///
+VOID FchInitResetSpi (IN VOID *FchDataPtr);
+VOID FchInitResetLpc (IN VOID *FchDataPtr);
+VOID FchInitResetLpcProgram (IN VOID *FchDataPtr);
+///
+/// Dxe Phase
+///
+VOID FchInitEnvSpi (IN VOID *FchDataPtr);
+VOID FchInitMidSpi (IN VOID *FchDataPtr);
+VOID FchInitLateSpi (IN VOID *FchDataPtr);
+VOID FchInitEnvLpc (IN VOID *FchDataPtr);
+VOID FchInitMidLpc (IN VOID *FchDataPtr);
+VOID FchInitLateLpc (IN VOID *FchDataPtr);
+VOID FchInitEnvLpcProgram (IN VOID *FchDataPtr);
+///
+/// Other Public Routines
+///
+VOID FchSpiUnlock (IN VOID *FchDataPtr);
+VOID FchSpiLock (IN VOID *FchDataPtr);
+
+/*--------------------------- Documentation Pages ---------------------------*/
+VOID FchStall (IN UINT32 uSec, IN AMD_CONFIG_PARAMS *StdHeader);
+VOID CimFchStall (IN UINT32 uSec, IN AMD_CONFIG_PARAMS *StdHeader);
+VOID FchPciReset (IN AMD_CONFIG_PARAMS *StdHeader);
+VOID OutPort80 (IN UINT32 pcode, IN AMD_CONFIG_PARAMS *StdHeader);
+VOID OutPort1080 (IN UINT32 pcode, IN AMD_CONFIG_PARAMS *StdHeader);
+VOID GetEfuseStatus (IN VOID* Value, IN AMD_CONFIG_PARAMS *StdHeader);
+VOID TurnOffCG2 (OUT VOID);
+VOID BackUpCG2 (OUT VOID);
+VOID FchCopyMem (IN VOID* pDest, IN VOID* pSource, IN UINTN Length);
+VOID* GetRomSigPtr (IN UINTN* RomSigPtr, IN AMD_CONFIG_PARAMS *StdHeader);
+VOID RwXhciIndReg (IN UINT32 Index, IN UINT32 AndMask, IN UINT32 OrMask, IN AMD_CONFIG_PARAMS *StdHeader);
+VOID RwXhci0IndReg (IN UINT32 Index, IN UINT32 AndMask, IN UINT32 OrMask, IN AMD_CONFIG_PARAMS *StdHeader);
+VOID RwXhci1IndReg (IN UINT32 Index, IN UINT32 AndMask, IN UINT32 OrMask, IN AMD_CONFIG_PARAMS *StdHeader);
+VOID ReadXhci0Phy (IN UINT32 Port, IN UINT32 Address, IN UINT32 *Value, IN AMD_CONFIG_PARAMS *StdHeader);
+VOID ReadXhci1Phy (IN UINT32 Port, IN UINT32 Address, IN UINT32 *Value, IN AMD_CONFIG_PARAMS *StdHeader);
+VOID AcLossControl (IN UINT8 AcLossControlValue);
+VOID FchVgaInit (OUT VOID);
+VOID RecordFchConfigPtr (IN UINT32 FchConfigPtr);
+VOID ValidateFchVariant (IN VOID *FchDataPtr);
+VOID RecordSmiStatus (IN AMD_CONFIG_PARAMS *StdHeader);
+VOID ClearAllSmiStatus (IN AMD_CONFIG_PARAMS *StdHeader);
+BOOLEAN IsGCPU (IN VOID *FchDataPtr);
+BOOLEAN IsExternalClockMode (IN VOID *FchDataPtr);
+VOID SbSleepTrapControl (IN BOOLEAN SleepTrap);
+
+AGESA_STATUS
+FchSpiTransfer (
+ IN UINT8 PrefixCode,
+ IN UINT8 Opcode,
+ IN OUT UINT8 *DataPtr,
+ IN UINT8 *AddressPtr,
+ IN UINT8 Length,
+ IN BOOLEAN WriteFlag,
+ IN BOOLEAN AddressFlag,
+ IN BOOLEAN DataFlag,
+ IN BOOLEAN FinishedFlag
+ );
+
+BOOLEAN
+FchConfigureSpiDeviceDummyCycle (
+ IN UINT32 DeviceID,
+ IN UINT8 SpiMode
+ );
+
+UINT32
+FchReadSpiId (
+ IN BOOLEAN Flag
+ );
+
+
+BOOLEAN
+FchPlatformSpiQe (
+ IN VOID *FchDataPtr
+ );
+
+#endif
+
diff --git a/src/vendorcode/amd/pi/00730F01/Proc/Fch/Fch.h b/src/vendorcode/amd/pi/00730F01/Proc/Fch/Fch.h
new file mode 100644
index 0000000..ab6f3c0
--- /dev/null
+++ b/src/vendorcode/amd/pi/00730F01/Proc/Fch/Fch.h
@@ -0,0 +1,2318 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * FCH registers definition
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: FCH
+ * @e \$Revision: 281178 $ @e \$Date: 2013-12-18 02:14:15 -0600 (Wed, 18 Dec 2013) $
+ *
+ */
+/*****************************************************************************
+ *
+ * Copyright (c) 2008 - 2014, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ***************************************************************************/
+
+#define FCH_REVISION "0.0.5.0"
+#define FCH_ID "FCH_A05"
+#define FCH_VERSION 0x0000
+
+/**
+ * @page fchinitguide FCH implement phase in AGESA
+ *
+ * FCH provides below access to supported FCH service functions
+ * and data.
+ * - @subpage fchreset "FCH_INIT_RESET"
+ * - @subpage fchenv "FCH_INIT_ENV"
+ * - @subpage fchmid "FCH_INIT_MID"
+ * - @subpage fchlate "FCH_INIT_LATE"
+ * - @subpage fchs3early "FCH_INIT_S3_EARLY_RESTORE"
+ * - @subpage fchs3late "FCH_INIT_S3_LATE_RESTORE"
+ * - @subpage fchsmm "FCH_SMM_SERVICE"
+ * - @subpage fchsmmacpion "FCH_SMM_ACPION"
+ */
+
+/*--------------------------- Documentation Pages ---------------------------*/
+/**
+ * @page fchreset FCH_INIT_RESET
+ * @section FCH_INIT_RESET Interface Call
+ * @par
+ * Initialize structure referenced by FCH_RESET_DATA_BLOCK to default recommended value.
+ * @subsection FCH_INIT_RESET_CallIn Call Prototype
+ * @par
+ * AGESA_STATUS FchInitReset (IN AMD_RESET_PARAMS *ResetParams);
+ * @subsection FCH_INIT_RESET_CallOut Prepare for Callout
+ * @par
+ * Not Applicable (Not necessary for the current implementation)
+ * @subsection FCH_INIT_RESET_Config Prepare for Configuration Data.
+ * @par
+ * <TABLE border="0">
+ * <TR><TD class="indexkey" width=380> BUILD_OPT_CFG::CfgSmbus0BaseAddress </TD><TD class="indexvalue"><B>Required </B></TD></TR>
+ * <TR><TD class="indexkey" width=380> BUILD_OPT_CFG::CfgSmbus1BaseAddress </TD><TD class="indexvalue"><B>Required </B></TD></TR>
+ * <TR><TD class="indexkey" width=380> BUILD_OPT_CFG::CfgSioPmeBaseAddress </TD><TD class="indexvalue"><B>Required </B></TD></TR>
+ * <TR><TD class="indexkey" width=380> BUILD_OPT_CFG::CfgWatchDogTimerBase </TD><TD class="indexvalue"><B>Required </B></TD></TR>
+ * <TR><TD class="indexkey" width=380> BUILD_OPT_CFG::CfgGecShadowRomBase </TD><TD class="indexvalue"><B>Required </B></TD></TR>
+ * <TR><TD class="indexkey" width=380> BUILD_OPT_CFG::CfgSpiRomBaseAddress </TD><TD class="indexvalue"><B>Required </B></TD></TR>
+ * <TR><TD class="indexkey" width=380> BUILD_OPT_CFG::CfgAcpiPm1EvtBlkAddr </TD><TD class="indexvalue"><B>Required </B></TD></TR>
+ * <TR><TD class="indexkey" width=380> BUILD_OPT_CFG::CfgAcpiPm1CntBlkAddr </TD><TD class="indexvalue"><B>Required </B></TD></TR>
+ * <TR><TD class="indexkey" width=380> BUILD_OPT_CFG::CfgAcpiPmTmrBlkAddr </TD><TD class="indexvalue"><B>Required </B></TD></TR>
+ * <TR><TD class="indexkey" width=380> BUILD_OPT_CFG::CfgCpuControlBlkAddr </TD><TD class="indexvalue"><B>Required </B></TD></TR>
+ * <TR><TD class="indexkey" width=380> BUILD_OPT_CFG::CfgAcpiGpe0BlkAddr </TD><TD class="indexvalue"><B>Required </B></TD></TR>
+ * <TR><TD class="indexkey" width=380> BUILD_OPT_CFG::CfgSmiCmdPortAddr </TD><TD class="indexvalue"><B>Required </B></TD></TR>
+ * <TR><TD class="indexkey" width=380> BUILD_OPT_CFG::CfgAcpiPmaCntBlkAddr </TD><TD class="indexvalue"><B>Required </B></TD></TR>
+ * <TR><TD class="indexkey" width=380> FCH_RESET_INTERFACE::SataEnable </TD><TD class="indexvalue"><B>Optional </B></TD></TR>
+ * <TR><TD class="indexkey" width=380> FCH_RESET_INTERFACE::IdeEnable </TD><TD class="indexvalue"><B>Optional </B></TD></TR>
+ * </TABLE>
+ *
+ */
+
+/*--------------------------- Documentation Pages ---------------------------*/
+/**
+ * @page fchenv FCH_INIT_ENV
+ * @section FCH_INIT_ENV Interface Call
+ * @par
+ * Initialize structure referenced by FCH_DATA_BLOCK to default recommended value.
+ * @subsection FCH_INIT_ENV_CallIn Call Prototype
+ * @par
+ * AGESA_STATUS FchInitEnv (IN AMD_ENV_PARAMS *EnvParams);
+ * @subsection FCH_INIT_ENV_CallOut Prepare for Callout
+ * @par
+ * Not Applicable (Not necessary for the current implementation)
+ * @subsection FCH_INIT_ENV_Config Prepare for Configuration Data.
+ * @par
+ * <TABLE border="0">
+ * <TR><TD class="indexkey" width=380> FCH_INTERFACE::SdConfig </TD><TD class="indexvalue"><B>Optional </B></TD></TR>
+ * <TR><TD class="indexkey" width=380> FCH_INTERFACE::AzaliaController </TD><TD class="indexvalue"><B>Optional </B></TD></TR>
+ * <TR><TD class="indexkey" width=380> FCH_INTERFACE::IrConfig </TD><TD class="indexvalue"><B>Optional </B></TD></TR>
+ * <TR><TD class="indexkey" width=380> FCH_INTERFACE::SataClass </TD><TD class="indexvalue"><B>Optional </B></TD></TR>
+ * <TR><TD class="indexkey" width=380> FCH_INTERFACE::SataEnable </TD><TD class="indexvalue"><B>Optional </B></TD></TR>
+ * <TR><TD class="indexkey" width=380> FCH_INTERFACE::SataIdeMode </TD><TD class="indexvalue"><B>Optional </B></TD></TR>
+ * <TR><TD class="indexkey" width=380> FCH_INTERFACE::Ohci1Enable </TD><TD class="indexvalue"><B>Optional </B></TD></TR>
+ * <TR><TD class="indexkey" width=380> FCH_INTERFACE::Ohci2Enable </TD><TD class="indexvalue"><B>Optional </B></TD></TR>
+ * <TR><TD class="indexkey" width=380> FCH_INTERFACE::Ohci3Enable </TD><TD class="indexvalue"><B>Optional </B></TD></TR>
+ * <TR><TD class="indexkey" width=380> FCH_INTERFACE::Ohci4Enable </TD><TD class="indexvalue"><B>Optional </B></TD></TR>
+ * </TABLE>
+ *
+ */
+
+/*--------------------------- Documentation Pages ---------------------------*/
+/**
+ * @page fchmid FCH_INIT_MID
+ * @section FCH_INIT_MID Interface Call
+ * @par
+ * Initialize structure referenced by FCH_DATA_BLOCK to default recommended value.
+ * @subsection FCH_INIT_MID_CallIn Call Prototype
+ * @par
+ * AGESA_STATUS FchInitMid (IN AMD_MID_PARAMS *MidParams);
+ * @subsection FCH_INIT_MID_CallOut Prepare for Callout
+ * @par
+ * Not Applicable (Not necessary for the current implementation)
+ * @subsection FCH_INIT_MID_Config Prepare for Configuration Data.
+ * @par
+ * <TABLE border="0">
+ * <TR><TD class="indexkey" width=380> FCH_INTERFACE::AzaliaController </TD><TD class="indexvalue"><B>Optional </B></TD></TR>
+ * <TR><TD class="indexkey" width=380> FCH_INTERFACE::SataClass </TD><TD class="indexvalue"><B>Optional </B></TD></TR>
+ * <TR><TD class="indexkey" width=380> FCH_INTERFACE::SataEnable </TD><TD class="indexvalue"><B>Optional </B></TD></TR>
+ * <TR><TD class="indexkey" width=380> FCH_INTERFACE::IdeEnable </TD><TD class="indexvalue"><B>Optional </B></TD></TR>
+ * </TABLE>
+ *
+ */
+
+/*--------------------------- Documentation Pages ---------------------------*/
+/**
+ * @page fchlate FCH_INIT_LATE
+ * @section FCH_INIT_LATE Interface Call
+ * @par
+ * Initialize structure referenced by FCH_DATA_BLOCK to default recommended value.
+ * @subsection FCH_INIT_LATE_CallIn Call Prototype
+ * @par
+ * AGESA_STATUS FchInitLate (IN AMD_S3SAVE_PARAMS *LateParams);
+ * @subsection FCH_INIT_LATE_CallOut Prepare for Callout
+ * @par
+ * Not Applicable (Not necessary for the current implementation)
+ * @subsection FCH_INIT_LATE_Config Prepare for Configuration Data.
+ * @par
+ * <TABLE border="0">
+ * <TR><TD class="indexkey" width=380> FCH_INTERFACE::SataClass </TD><TD class="indexvalue"><B>Optional </B></TD></TR>
+ * <TR><TD class="indexkey" width=380> FCH_INTERFACE::SataEnable </TD><TD class="indexvalue"><B>Optional </B></TD></TR>
+ * <TR><TD class="indexkey" width=380> BUILD_OPT_CFG::CfgSpiRomBaseAddress </TD><TD class="indexvalue"><B>Required </B></TD></TR>
+ * </TABLE>
+ *
+ */
+
+/*--------------------------- Documentation Pages ---------------------------*/
+/**
+ * @page fchs3early FCH_INIT_S3_EARLY_RESTORE
+ * @section FCH_INIT_S3_EARLY_RESTORE Interface Call
+ * @par
+ * Initialize structure referenced by FCH_DATA_BLOCK to default recommended value.
+ * @subsection FCH_INIT_S3_EARLY_RESTORE_CallIn Call Prototype
+ * @par
+ * VOID FchInitS3EarlyRestore (IN FCH_DATA_BLOCK *FchDataPtr);
+ * @subsection FCH_INIT_S3_EARLY_RESTORE_CallOut Prepare for Callout
+ * @par
+ * Not Applicable (Not necessary for the current implementation)
+ * @subsection FCH_INIT_S3_EARLY_RESTORE_Config Prepare for Configuration Data.
+ * @par
+ * <TABLE border="0">
+ * <TR><TD class="indexkey" width=380> FCH_INTERFACE::SdConfig </TD><TD class="indexvalue"><B>Optional </B></TD></TR>
+ * <TR><TD class="indexkey" width=380> FCH_INTERFACE::AzaliaController </TD><TD class="indexvalue"><B>Optional </B></TD></TR>
+ * <TR><TD class="indexkey" width=380> FCH_INTERFACE::IrConfig </TD><TD class="indexvalue"><B>Optional </B></TD></TR>
+ * <TR><TD class="indexkey" width=380> FCH_INTERFACE::SataClass </TD><TD class="indexvalue"><B>Optional </B></TD></TR>
+ * <TR><TD class="indexkey" width=380> FCH_INTERFACE::SataEnable </TD><TD class="indexvalue"><B>Optional </B></TD></TR>
+ * <TR><TD class="indexkey" width=380> FCH_INTERFACE::SataIdeMode </TD><TD class="indexvalue"><B>Optional </B></TD></TR>
+ * <TR><TD class="indexkey" width=380> FCH_INTERFACE::Ohci1Enable </TD><TD class="indexvalue"><B>Optional </B></TD></TR>
+ * <TR><TD class="indexkey" width=380> FCH_INTERFACE::Ohci2Enable </TD><TD class="indexvalue"><B>Optional </B></TD></TR>
+ * <TR><TD class="indexkey" width=380> FCH_INTERFACE::Ohci3Enable </TD><TD class="indexvalue"><B>Optional </B></TD></TR>
+ * <TR><TD class="indexkey" width=380> FCH_INTERFACE::Ohci4Enable </TD><TD class="indexvalue"><B>Optional </B></TD></TR>
+ * </TABLE>
+ *
+ */
+
+/*--------------------------- Documentation Pages ---------------------------*/
+/**
+ * @page fchs3late FCH_INIT_S3_LATE_RESTORE
+ * @section FCH_INIT_S3_LATE_RESTORE Interface Call
+ * @par
+ * Initialize structure referenced by FCH_DATA_BLOCK to default recommended value.
+ * @subsection FCH_INIT_S3_LATE_RESTORE_CallIn Call Prototype
+ * @par
+ * VOID FchInitS3LateRestore (IN FCH_DATA_BLOCK *FchDataPtr);
+ * @subsection FCH_INIT_S3_LATE_RESTORE_CallOut Prepare for Callout
+ * @par
+ * Not Applicable (Not necessary for the current implementation)
+ * @subsection FCH_INIT_S3_LATE_RESTORE_Config Prepare for Configuration Data.
+ * @par
+ * <TABLE border="0">
+ * <TR><TD class="indexkey" width=380> FCH_INTERFACE::AzaliaController </TD><TD class="indexvalue"><B>Optional </B></TD></TR>
+ * <TR><TD class="indexkey" width=380> FCH_INTERFACE::SataClass </TD><TD class="indexvalue"><B>Optional </B></TD></TR>
+ * <TR><TD class="indexkey" width=380> FCH_INTERFACE::SataEnable </TD><TD class="indexvalue"><B>Optional </B></TD></TR>
+ * <TR><TD class="indexkey" width=380> FCH_INTERFACE::IdeEnable </TD><TD class="indexvalue"><B>Optional </B></TD></TR>
+ * <TR><TD class="indexkey" width=380> BUILD_OPT_CFG::CfgSpiRomBaseAddress </TD><TD class="indexvalue"><B>Required </B></TD></TR>
+ * </TABLE>
+ *
+ */
+
+/*--------------------------- Documentation Pages ---------------------------*/
+/**
+ * @page fchsmm FCH_SMM_SERVICE
+ * @section FCH_SMM_SERVICE Interface Call
+ * Initialize structure referenced by FCHCFG to default recommended value.
+ * @subsection FCH_SMM_SERVICE_CallIn Call Prototype
+ * @par
+ * FchSmmService ((FCHCFG*)pConfig) (Followed PH Interface)
+ * @subsection FCH_SMM_SERVICE_CallID Service ID
+ * @par
+ * <TABLE border="0">
+ * <TR><TD class="indexkey" width=380> FCH_SMM_SERVICE --> 0x00010060 </TD></TR>
+ * </TABLE>
+ * @subsection FCH_SMM_SERVICE_CallOut Prepare for Callout
+ * @par
+ * Not Applicable (Not necessary for the current implementation)
+ * @subsection FCH_SMM_SERVICE_Config Prepare for Configuration Data.
+ * @par
+ * Not necessary on current implementation
+ *
+ */
+#define FCH_SMM_SERVICE 0x00010060ul
+/*--------------------------- Documentation Pages ---------------------------*/
+/**
+ * @page fchsmmacpion FCH_SMM_ACPION
+ * @section FCH_SMM_ACPION Interface Call
+ * Initialize structure referenced by FCHCFG to default recommended value.
+ * @subsection FCH_SMM_ACPION_CallIn Call Prototype
+ * @par
+ * FchSmmAcpiOn ((FCHCFG*)pConfig) (Followed PH Interface)
+ * @subsection FCH_SMM_ACPION_CallID Service ID
+ * @par
+ * <TABLE border="0">
+ * <TR><TD class="indexkey" width=380> FCH_SMM_ACPION --> 0x00010061 </TD></TR>
+ * </TABLE>
+ * @subsection FCH_SMM_ACPION_CallOut Prepare for Callout
+ * @par
+ * Not Applicable (Not necessary for the current implementation)
+ * @subsection FCH_SMM_ACPION_Config Prepare for Configuration Data.
+ * @par
+ * Not necessary on current implementation
+ *
+ */
+#define FCH_SMM_ACPION 0x00010061ul
+
+#ifndef OEM_CALLBACK_BASE
+ #define OEM_CALLBACK_BASE 0x00010100ul
+#endif
+
+//0x00 - 0x0F callback functions are reserved for bootblock
+#define SATA_PHY_PROGRAMMING OEM_CALLBACK_BASE + 0x10
+#define PULL_UP_PULL_DOWN_SETTINGS OEM_CALLBACK_BASE + 0x20
+/*--------------------------- Documentation Pages ---------------------------*/
+/**
+ * @page CB_SBGPP_RESET_ASSERT_Page CB_SBGPP_RESET_ASSERT
+ * @section CB_SBGPP_RESET_ASSERT Interface Call
+ * Initialize structure referenced by FCHCFG to default recommended value.
+ * @subsection CB_SBGPP_RESET_ASSERT_CallID Service ID
+ * @par
+ * <TABLE border="0">
+ * <TR><TD class="indexkey" width=380> CB_SBGPP_RESET_ASSERT --> 0x00010130 </TD></TR>
+ * </TABLE>
+ * @subsection CB_SBGPP_RESET_ASSERT_Config Prepare for Configuration Data.
+ * @par
+ * Not necessary on current implementation
+ *
+ */
+#define CB_SBGPP_RESET_ASSERT OEM_CALLBACK_BASE + 0x30
+/*--------------------------- Documentation Pages ---------------------------*/
+/**
+ * @page CB_SBGPP_RESET_DEASSERT_Page CB_SBGPP_RESET_DEASSERT
+ * @section CB_SBGPP_RESET_DEASSERT Interface Call
+ * Initialize structure referenced by FCHCFG to default recommended value.
+ * @subsection CB_SBGPP_RESET_DEASSERT _CallID Service ID
+ * @par
+ * <TABLE border="0">
+ * <TR><TD class="indexkey" width=380> CB_SBGPP_RESET_DEASSERT --> 0x00010131 </TD></TR>
+ * </TABLE>
+ * @subsection CB_SBGPP_RESET_DEASSERT _Config Prepare for Configuration Data.
+ * @par
+ * Not necessary on current implementation
+ *
+ */
+#define CB_SBGPP_RESET_DEASSERT OEM_CALLBACK_BASE + 0x31
+
+#define CFG_ADDR_PORT 0xCF8
+#define CFG_DATA_PORT 0xCFC
+
+#define ALINK_ACCESS_INDEX 0x0CD8
+#define ALINK_ACCESS_DATA ALINK_ACCESS_INDEX + 4
+
+/*------------------------------------------------------------------
+; I/O Base Address - Should be set by host BIOS
+;------------------------------------------------------------------ */
+#define DELAY_PORT 0x0E0
+
+#define FCH_8259_CONTROL_REG_MASTER 0x20
+#define FCH_8259_MASK_REG_MASTER 0x21
+
+/*------------------------------------------------------------------
+; DEBUG_PORT = 8-bit I/O Port Address for POST Code Display
+;------------------------------------------------------------------ */
+// ASIC VendorID and DeviceIDs
+#define ATI_VID 0x1002
+#define AMD_FCH_VID 0x1022
+#define FCH_DEVICE_ID 0x780B
+#define FCH_SATA_VID AMD_FCH_VID // Dev 17 Func 0
+#define FCH_SATA_DID 0x7800
+#define FCH_SATA_AHCI_DID 0x7801
+#define FCH_SATA_RAID_DID 0x7802
+#define FCH_SATA_RAID5_DID 0x7803
+#define FCH_SATA_AMDAHCI_DID 0x7804
+#define FCH_SATA_RAID_DOTHILL_DID 0x7805
+#define FCH_SATA_RAID5_DOTHILL_DID 0x780A
+#define FCH_USB_OHCI_VID AMD_FCH_VID // Dev 18 Func 0, Dev 19 Func 0
+#define FCH_USB_OHCI_DID 0x7807
+#define FCH_USB_EHCI_VID AMD_FCH_VID // Dev 18 Func 2, Dev 19 Func 2
+#define FCH_USB_EHCI_DID 0x7808
+#define FCH_USB_XHCI_VID AMD_FCH_VID // Dev 10 Func 0, Dev 10 Func 1
+#define FCH_USB_XHCI_DID 0x7812
+#define FCH_USB_XHCI_DID_BOLTON 0x7814
+#define AVALON_USB_XHCI_DID 0x7814
+#define FCH_SMBUS_VID AMD_FCH_VID // Dev 20 Func 0
+#define FCH_SMBUS_DID 0x780B
+#define FCH_IDE_VID AMD_FCH_VID // Dev 20 Func 1
+#define FCH_IDE_DID 0x780C
+#define FCH_AZALIA_VID AMD_FCH_VID // Dev 20 Func 2
+#define FCH_AZALIA_DID 0x780D
+#define FCH_LPC_VID AMD_FCH_VID // Dev 20 Func 3
+#define FCH_LPC_DID 0x780E
+#define FCH_PCIB_VID AMD_FCH_VID // Dev 20 Func 4
+#define FCH_PCIB_DID 0x780F
+#define FCH_USB_OHCIF_VID AMD_FCH_VID // dev 20 Func 5
+#define FCH_USB_OHCIF_DID 0x7809
+#define FCH_NIC_VID 0x14E4 // Dev 20 Func 6
+#define FCH_NIC_DID 0x1699
+#define FCH_SD_VID AMD_FCH_VID // Dev 20 Func 7
+#define FCH_SD_DID 0x7806
+
+//FCH Variant
+#define FCH_Variant_EFUSE_LOCATION 0x1E // EFUSE bit 240-247
+
+#define FCH_M2 0x01
+#define FCH_M3 0x03
+#define FCH_M3T 0x07
+#define FCH_D2 0x0F
+#define FCH_D3 0x1F
+#define FCH_D4 0x3F
+#define FCH_BOLTON 0x15
+#define FCH_YANGTZE 0x39
+#define FCH_YANGTZEA1 0x3A
+#define FCH_AVALONA0 0x41
+#define FCH_AVALONA1 0x42
+//Misc
+#define R_FCH_ACPI_PM1_STATUS 0x00
+#define R_FCH_ACPI_PM1_ENABLE 0x02
+#define R_FCH_ACPI_PM_CONTROL 0x04
+#define R_FCH_ACPI_EVENT_STATUS 0x20
+#define R_FCH_ACPI_EVENT_ENABLE 0x24
+#define R_FCH_PM_ACPI_PMA_CNT_BLK_LO 0x2C
+
+// ACPI Sleep Type
+#define ACPI_SLPTYP_S0 0
+#define ACPI_SLPTYP_S1 1
+#define ACPI_SLPTYP_S3 3
+#define ACPI_SLPTYP_S4 4
+#define ACPI_SLPTYP_S5 5
+
+//#define SATA_BUS_DEV_FUN_FPGA 0x228
+#define SATA_BUS_DEV_FUN ((0x11 << 3) + 0)
+#define FCH_SATA1_BUS 0
+#define FCH_SATA1_DEV 17
+#define FCH_SATA1_FUNC 0
+
+#define FC_BUS_DEV_FUN ((0x11 << 3) + 1)
+#define FCH_XHCI_BUS 0
+#define FCH_XHCI_DEV 16
+#define FCH_XHCI_FUNC 0
+#define USB_XHCI_BUS_DEV_FUN ((FCH_XHCI_DEV << 3) + FCH_XHCI_FUNC)
+#define FCH_XHCI1_BUS 0
+#define FCH_XHCI1_DEV 16
+#define FCH_XHCI1_FUNC 1
+#define USB_XHCI1_BUS_DEV_FUN ((FCH_XHCI1_DEV << 3) + FCH_XHCI1_FUNC)
+#define USB1_OHCI_BUS_DEV_FUN ((0x12 << 3) + 0) // PORT 0-4
+#define FCH_OHCI1_BUS 0
+#define FCH_OHCI1_DEV 18
+#define FCH_OHCI1_FUNC 0
+#define USB2_OHCI_BUS_DEV_FUN ((0x13 << 3) + 0) // PORT 5-9
+#define FCH_OHCI2_BUS 0
+#define FCH_OHCI2_DEV 19
+#define FCH_OHCI2_FUNC 0
+#define USB3_OHCI_BUS_DEV_FUN ((0x16 << 3) + 0) // PORT 10-13
+#define FCH_OHCI3_BUS 0
+#define FCH_OHCI3_DEV 22
+#define FCH_OHCI3_FUNC 0
+#define USB1_EHCI_BUS_DEV_FUN ((0x12 << 3) + 2) // PORT 0-4
+#define FCH_EHCI1_BUS 0
+#define FCH_EHCI1_DEV 18
+#define FCH_EHCI1_FUNC 2
+#define USB2_EHCI_BUS_DEV_FUN ((0x13 << 3) + 2) // PORT 5-9
+#define FCH_EHCI2_BUS 0
+#define FCH_EHCI2_DEV 19
+#define FCH_EHCI2_FUNC 2
+#define USB3_EHCI_BUS_DEV_FUN ((0x16 << 3) + 2) // PORT 10-13
+#define FCH_EHCI3_BUS 0
+#define FCH_EHCI3_DEV 22
+#define FCH_EHCI3_FUNC 2
+#define SMBUS_BUS_DEV_FUN ((0x14 << 3) + 0)
+#define FCH_ISA_BUS 0
+#define FCH_ISA_DEV 20
+#define FCH_ISA_FUNC 0
+#define IDE_BUS_DEV_FUN ((0x14 << 3) + 1)
+#define FCH_IDE_BUS 0
+#define FCH_IDE_DEV 20
+#define FCH_IDE_FUNC 1
+#define AZALIA_BUS_DEV_FUN ((0x14 << 3) + 2)
+#define FCH_AZALIA_BUS 0
+#define FCH_AZALIA_DEV 20
+#define FCH_AZALIA_FUNC 2
+#define LPC_BUS_DEV_FUN ((0x14 << 3) + 3)
+#define FCH_LPC_BUS 0
+#define FCH_LPC_DEV 20
+#define FCH_LPC_FUNC 3
+#define PCIB_BUS_DEV_FUN ((0x14 << 3) + 4) // P2P in SB700
+#define FCH_PCI_BUS 0
+#define FCH_PCI_DEV 20
+#define FCH_PCI_FUNC 4
+#define USB4_OHCI_BUS_DEV_FUN ((0x14 << 3) + 5) // PORT FL0 - FL1
+#define FCH_OHCI4_BUS 0
+#define FCH_OHCI4_DEV 20
+#define FCH_OHCI4_FUNC 5
+//Gigabyte Ethernet Controller
+#define GEC_BUS_DEV_FUN ((0x14 << 3) + 6)
+#define FCH_GBEC_BUS 0
+#define FCH_GBEC_DEV 20
+#define FCH_GBEC_FUNC 6
+
+#define SD_BUS_DEV_FUN ((0x14 << 3) + 7) // SD Controller
+#define SD_PCI_BUS 0
+#define SD_PCI_DEV 20
+#define SD_PCI_FUNC 7
+
+
+#define FCH_GPP_BUS 0
+#define FCH_GPP_DEV 21
+#define FCH_GPP_FUNC 0
+#define GPP0_BUS_DEV_FUN ((0x15 << 3) + 0) // GPP P2P bridge PORT0
+#define GPP1_BUS_DEV_FUN ((0x15 << 3) + 1) // GPP P2P bridge PORT1
+#define GPP2_BUS_DEV_FUN ((0x15 << 3) + 2) // GPP P2P bridge PORT2
+#define GPP3_BUS_DEV_FUN ((0x15 << 3) + 3) // GPP P2P bridge PORT3
+
+#define ACPI_MMIO_BASE 0xFED80000ul
+#define FCH_CFG_BASE 0x000 // DWORD
+#define GPIO_BASE 0x100 // BYTE
+#define SMI_BASE 0x200 // DWORD
+#define PMIO_BASE 0x300 // DWORD
+#define PMIO2_BASE 0x400 // BYTE
+#define BIOS_RAM_BASE 0x500 // BYTE
+#define CMOS_RAM_BASE 0x600 // BYTE
+#define CMOS_BASE 0x700 // BYTE
+#define ASF_BASE 0x900 // DWORD
+#define SMBUS_BASE 0xA00 // DWORD
+#define WATCHDOG_BASE 0xB00 //
+#define HPET_BASE 0xC00 // DWORD
+#define IOMUX_BASE 0xD00 // BYTE
+#define MISC_BASE 0xE00
+#define SERIAL_DEBUG_BASE 0x1000
+#define GFX_DAC_BASE 0x1400
+#define GPIO_BANK0_BASE 0x1500 // DWORD
+//#define GPIO_BANK1_BASE 0x1600 // DWORD
+//#define GPIO_BANK2_BASE 0x1700 // DWORD
+#define CEC_BASE 0x1800
+#define XHCI_BASE 0x1C00
+#define ACDC_BASE 0x1D00
+#define AOAC_BASE 0x1E00
+
+
+// Chip type definition
+#define CHIPTYPE_HUDSON2 (1 << 0)
+#define CHIPTYPE_YUBA (1 << 1)
+
+//
+// ROM SIG type definition
+//
+#define NUM_OF_ROMSIG_FILED 0x04
+#define XHCI_FILED_NUM 0x03
+#define ROMSIG_CFG_MASK 0x07
+#define XHCI_BOOT_RAM_OFFSET 0x8000
+#define INSTRUCTION_RAM_SIG 0x55AA
+#define ROMSIG_SIG 0x55AA55AAul
+
+// RegSpace field (AB_INDEX[31:29]
+#define AXINDC 0 // AXINDC
+#define AXINDP 2 // AXINDP
+#define ABCFG 6 // ABCFG
+#define AXCFG 4 // AXCFG
+#define RCINDXC 1 // PCIEIND
+#define RCINDXP 3 // PCIEIND_P
+
+#define GPP_DEV_NUM 21 //
+#define MAX_GPP_PORTS 4
+
+#define PCIE_FORCE_GEN1_EFUSE_LOCATION 0x14 // EFUSE bit 160
+//
+// ABCFG Registers
+//
+#define FCH_ABCFG_REG00 0x00 // VENDOR ID
+#define FCH_ABCFG_REG08 0x08 // REVISION ID
+#define FCH_ABCFG_REG40 0x40 // BL_EVENTCNT0LO
+#define FCH_ABCFG_REG44 0x44 // BL_EVENTCNT1LO
+#define FCH_ABCFG_REG48 0x48 // BL_EVENTCNTSEL
+#define FCH_ABCFG_REG4A 0x4A // BL_EVENTCNT0HI
+#define FCH_ABCFG_REG4B 0x4B // BL_EVENTCNT1HI
+#define FCH_ABCFG_REG4C 0x4C // BL_EVENTCNTCTL
+#define FCH_ABCFG_REG50 0x50 // MISCCTL_50
+#define FCH_ABCFG_REG54 0x54 // MISCCTL_54
+#define FCH_ABCFG_REG58 0x58 // BL RAB CONTROL
+
+#define FCH_ABCFG_REG60 0x60 // LINKWIDTH_CTL
+#define FCH_ABCFG_REG64 0x64 // LINKWIDTH_UP_INTERVAL
+#define FCH_ABCFG_REG68 0x68 // LINKWIDTH_DN_INVERVAL
+#define FCH_ABCFG_REG6C 0x6C // LINKWIDTH_UPSTREAM_DWORDS
+#define FCH_ABCFG_REG70 0x70 // LINKWIDTH_DOWNSTREAM_DWORDS
+#define FCH_ABCFG_REG74 0x74 // LINKWIDTH_THRESHOLD_INCREASE
+#define FCH_ABCFG_REG78 0x78 // LINKWIDTH_THRESHOLD_DECREASE
+
+#define FCH_ABCFG_REG80 0x80 // BL DMA PREFETCH CONTROL
+#define FCH_ABCFG_REG88 0x88 //
+#define FCH_ABCFG_REG8C 0x8C //
+#define FCH_ABCFG_REG90 0x90 // BIF CONTROL 0
+#define FCH_ABCFG_REG94 0x94 // MSI CONTROL
+#define FCH_ABCFG_REG98 0x98 // BIF CONTROL 1
+#define FCH_ABCFG_REG9C 0x9C // MISCCTL_9C
+#define FCH_ABCFG_REGA0 0xA0 // BIF PHY CONTROL ENABLE
+#define FCH_ABCFG_REGA4 0xA4 // BIF PHY CONTROL A4
+#define FCH_ABCFG_REGA8 0xA8 // BIF PHY CONTROL A8
+#define FCH_ABCFG_REGB0 0xB0 // HYPERFLASH-PCIE PORT MAPPING
+#define FCH_ABCFG_REGB8 0xB8 //
+#define FCH_ABCFG_REGB4 0xB4 //
+#define FCH_ABCFG_REGBC 0xBC //
+#define FCH_ABCFG_REGC0 0xC0 // PCIE_GPP_ENABLE
+#define FCH_ABCFG_REGC4 0xC4 // PCIE_P2P_INT_MAP
+#define FCH_ABCFG_REGD0 0xD0 // MCTP_VDM_TX_FIFO_DATA
+#define FCH_ABCFG_REGD4 0xD4 // MCTP_VMD_TX_CONTROL
+#define FCH_ABCFG_REGE0 0xE0 // MCTP_VDM_RX_FIFO_DATA
+#define FCH_ABCFG_REGE4 0xE4 // MCTP_VDM_RX_FIFO_STATUS
+#define FCH_ABCFG_REGEC 0xEC // MCTP_VDM_CONTROL
+#define FCH_ABCFG_REGF0 0xF0 // GPP_UPSTREAM_CONTROL
+#define FCH_ABCFG_REGF4 0xF4 // GPP_SYSTEM_ERROR_CONTROL
+#define FCH_ABCFG_REGFC 0xFC // FCH_TRAP_CONTROL
+#define FCH_ABCFG_REG100 0x100 // FCH_TRAP0_ADDRL
+#define FCH_ABCFG_REG104 0x104 // FCH_TRAP0_ADDRH
+#define FCH_ABCFG_REG108 0x108 // FCH_TRAP0_CMD
+#define FCH_ABCFG_REG10C 0x10C // FCH_TRAP1_DATA
+#define FCH_ABCFG_REG110 0x110 // FCH_TRAP1_ADDRL
+#define FCH_ABCFG_REG114 0x114 // FCH_TRAP1_ADDRH
+#define FCH_ABCFG_REG118 0x118 // FCH_TRAP1_CMD
+#define FCH_ABCFG_REG11C 0x11C // FCH_TRAP1_DATA
+#define FCH_ABCFG_REG120 0x120 // FCH_TRAP2_ADDRL
+#define FCH_ABCFG_REG124 0x124 // FCH_TRAP2_ADDRH
+#define FCH_ABCFG_REG128 0x128 // FCH_TRAP2_CMD
+#define FCH_ABCFG_REG12C 0x12C // FCH_TRAP2_DATA
+#define FCH_ABCFG_REG130 0x130 // FCH_TRAP3_ADDRL
+#define FCH_ABCFG_REG134 0x134 // FCH_TRAP3_ADDRH
+#define FCH_ABCFG_REG138 0x138 // FCH_TRAP3_CMD
+#define FCH_ABCFG_REG13C 0x13C // FCH_TRAP3_DATA
+#define FCH_ABCFG_REG208 0x208 // KR New
+#define FCH_ABCFG_REG300 0x300 // MCTP_VDM_RX_SMI_CONTROL
+#define FCH_ABCFG_REG310 0x310 // BIF_GPP_STRAP_SYSTEM_0
+#define FCH_ABCFG_REG314 0x314 // BIF_GPP_STRAP_SYSTEM_1
+#define FCH_ABCFG_REG31C 0x31C // BIF_GPP_STRAP_LINK_CONTROL_0
+#define FCH_ABCFG_REG320 0x320 // BIF_GPP_STRAP_LINK_CONTROL_LANE_A
+#define FCH_ABCFG_REG324 0x324 // BIF_GPP_STRAP_LINK_CONTROL_LANE_B
+#define FCH_ABCFG_REG328 0x328 // BIF_GPP_STRAP_LINK_CONTROL_LANE_C
+#define FCH_ABCFG_REG32C 0x32C // BIF_GPP_STRAP_LINK_CONTROL_LANE_D
+#define FCH_ABCFG_REG330 0x330 // BIF_GPP_STRAP_BIF_0
+#define FCH_ABCFG_REG334 0x334 // BIF_GPP_STRAP_BIF_1
+#define FCH_ABCFG_REG338 0x338 // BIF_GPP_STRAP_BIF_2
+#define FCH_ABCFG_REG340 0x340 // BIF_GPP_STRAP_BIF_LANE_A
+#define FCH_ABCFG_REG344 0x344 // BIF_GPP_STRAP_BIF_LANE_B
+#define FCH_ABCFG_REG348 0x348 // BIF_GPP_STRAP_BIF_LANE_C
+#define FCH_ABCFG_REG34C 0x34C // BIF_GPP_STRAP_BIF_LANE_D
+#define FCH_ABCFG_REG350 0x350 // BIF_GPP_STRAP_PHY_LOGICAL _0
+#define FCH_ABCFG_REG354 0x354 // BIF_GPP_STRAP_PHY_LOGICAL _1
+#define FCH_ABCFG_REG404 0x404 // GPP0_SHADOW_COMMAND
+#define FCH_ABCFG_REG418 0x418 // GPP0_SHADOW_BUS_NUMBER
+#define FCH_ABCFG_REG41C 0x41C // GPP0_SHADOW_IO_LIMIT_BASE
+#define FCH_ABCFG_REG420 0x420 // GPP0_SHADOW_MEM_LIMIT_BASE
+#define FCH_ABCFG_REG424 0x424 // GPP0_SHADOW_PREF_MEM_LIMIT_BASE
+#define FCH_ABCFG_REG428 0x428 // GPP0_SHADOW_PREF_MEM_BASE_UPPER
+#define FCH_ABCFG_REG42C 0x42C // GPP0_SHADOW_PREF_MEM_LIMIT_UPPER
+#define FCH_ABCFG_REG430 0x430 // GPP0_SHADOW_IO_LIMIT_BASE_UPPER
+#define FCH_ABCFG_REG43C 0x43C // GPP0_SHADOW_BRIDGE_CONTROL
+#define FCH_ABCFG_REG444 0x444 // GPP1_SHADOW_COMMAND
+#define FCH_ABCFG_REG458 0x458 // GPP1_SHADOW_BUS_NUMBER
+#define FCH_ABCFG_REG45C 0x45C // GPP1_SHADOW_IO_LIMIT_BASE
+#define FCH_ABCFG_REG460 0x460 // GPP1_SHADOW_MEM_LIMIT_BASE
+#define FCH_ABCFG_REG464 0x464 // GPP1_SHADOW_PREF_MEM_LIMIT_BASE
+#define FCH_ABCFG_REG468 0x468 // GPP1_SHADOW_PREF_MEM_BASE_UPPER
+#define FCH_ABCFG_REG46C 0x46C // GPP1_SHADOW_PREF_MEM_LIMIT_UPPER
+#define FCH_ABCFG_REG470 0x470 // GPP1_SHADOW_IO_LIMIT_BASE_UPPER
+#define FCH_ABCFG_REG47C 0x47C // GPP1_SHADOW_BRIDGE_CONTROL
+#define FCH_ABCFG_REG484 0x484 // GPP2_SHADOW_COMMAND
+#define FCH_ABCFG_REG498 0x498 // GPP2_SHADOW_BUS_NUMBER
+#define FCH_ABCFG_REG49C 0x49C // GPP2_SHADOW_IO_LIMIT_BASE
+#define FCH_ABCFG_REG4A0 0x4A0 // GPP2_SHADOW_MEM_LIMIT_BASE
+#define FCH_ABCFG_REG4A4 0x4A4 // GPP2_SHADOW_PREF_MEM_LIMIT_BASE
+#define FCH_ABCFG_REG4A8 0x4A8 // GPP2_SHADOW_PREF_MEM_BASE_UPPER
+#define FCH_ABCFG_REG4AC 0x4AC // GPP2_SHADOW_PREF_MEM_LIMIT_UPPER
+#define FCH_ABCFG_REG4B0 0x4B0 // GPP2_SHADOW_IO_LIMIT_BASE_UPPER
+#define FCH_ABCFG_REG4BC 0x4BC // GPP2_SHADOW_BRIDGE_CONTROL
+#define FCH_ABCFG_REG4C4 0x4C4 // GPP3_SHADOW_COMMAND
+#define FCH_ABCFG_REG4D8 0x4D8 // GPP3_SHADOW_BUS_NUMBER
+#define FCH_ABCFG_REG4DC 0x4DC // GPP3_SHADOW_IO_LIMIT_BASE
+#define FCH_ABCFG_REG4E0 0x4E0 // GPP3_SHADOW_MEM_LIMIT_BASE
+#define FCH_ABCFG_REG4E4 0x4E4 // GPP3_SHADOW_PREF_MEM_LIMIT_BASE
+#define FCH_ABCFG_REG4E8 0x4E8 // GPP3_SHADOW_PREF_MEM_BASE_UPPER
+#define FCH_ABCFG_REG4EC 0x4EC // GPP3_SHADOW_PREF_MEM_LIMIT_UPPER
+#define FCH_ABCFG_REG4F0 0x4F0 // GPP3_SHADOW_IO_LIMIT_BASE_UPPER
+#define FCH_ABCFG_REG4FC 0x4FC // GPP3_SHADOW_BRIDGE_CONTROL
+#define FCH_ABCFG_REG10040 0x10040ul // AL_EVENTCNT0LO
+#define FCH_ABCFG_REG10044 0x10044ul // AL_EVENTCNT1LO
+#define FCH_ABCFG_REG10048 0x10048ul // AL_EVENTCNTSEL
+#define FCH_ABCFG_REG1004A 0x1004Aul // AL_EVENTCNT0HI
+#define FCH_ABCFG_REG1004B 0x1004Bul // AL_EVENTCNT1HI
+#define FCH_ABCFG_REG1004C 0x1004Cul // AL_EVENTCNTCTL
+#define FCH_ABCFG_REG10050 0x10050ul // MISCCTL_10050
+#define FCH_ABCFG_REG10054 0x10054ul // AL_ARB_CTL
+#define FCH_ABCFG_REG10056 0x10056ul // AL_CLK_CTL
+#define FCH_ABCFG_REG10058 0x10058ul // AL RAB CONTROL
+#define FCH_ABCFG_REG1005C 0x1005Cul // AL MLT CONTROL
+#define FCH_ABCFG_REG10060 0x10060ul // AL DMA PREFETCH ENABLE
+#define FCH_ABCFG_REG10064 0x10064ul // AL DMA PREFETCH FLUSH CONTROL
+#define FCH_ABCFG_REG10068 0x10068ul // AL PREFETCH LIMIT
+#define FCH_ABCFG_REG1006C 0x1006Cul // AL DMA PREFETCH CONTROL
+#define FCH_ABCFG_REG10070 0x10070ul // MISCCTL_10070
+#define FCH_ABCFG_REG10080 0x10080ul // CLKMUXSTATUS
+#define FCH_ABCFG_REG10090 0x10090ul // BIF CONTROL 0
+#define FCH_ABCFG_REG1009C 0x1009Cul // MISCCTL_1009C
+
+//
+// RCINDX_P Registers
+//
+#define FCH_RCINDXP_REG01 0x01 | RCINDXP << 29 // PCIEP_SCRATCH
+#define FCH_RCINDXP_REG02 0x02 | RCINDXP << 29 //
+#define FCH_RCINDXP_REG10 0x10 | RCINDXP << 29 //
+#define FCH_RCINDXP_REG20 0x20 | RCINDXP << 29 // PCIE_TX_CNTL
+#define FCH_RCINDXP_REG21 0x21 | RCINDXP << 29 // PCIE_TX_REQUESTER_ID
+#define FCH_RCINDXP_REG50 0x50 | RCINDXP << 29 // PCIE_P_PORT_LANE_STATUS
+#define FCH_RCINDXP_REG6A 0x6A | RCINDXP << 29 //
+#define FCH_RCINDXP_REG70 0x70 | RCINDXP << 29 // PCIE_RX_CNTL
+#define FCH_RCINDXP_REGA0 0xA0 | RCINDXP << 29 // PCIE_LC_CNTL
+#define FCH_RCINDXP_REGA1 0xA1 | RCINDXP << 29 // PCIE_LC_TRAINING_CNTL
+#define FCH_RCINDXP_REGA2 0xA2 | RCINDXP << 29 //
+#define FCH_RCINDXP_REGA4 0xA4 | RCINDXP << 29 //
+#define FCH_RCINDXP_REGA5 0xA5 | RCINDXP << 29 // PCIE_LC_STATE0
+#define FCH_RCINDXP_REGC0 0xC0 | RCINDXP << 29 //
+
+//
+// RCINDX_C Registers
+//
+#define FCH_RCINDXC_REG02 0x02 | RCINDXC << 29 // PCIE_HW_DEBUG
+#define FCH_RCINDXC_REG10 0x10 | RCINDXC << 29 // PCIE_CNTL
+#define FCH_RCINDXC_REG40 0x40 | RCINDXC << 29 // PCIE_P_CNTL
+#define FCH_RCINDXC_REG65 0x65 | RCINDXC << 29 // PCIE_P_PAD_FORCE_DIS
+#define FCH_RCINDXC_REGC0 0xC0 | RCINDXC << 29 // PCIE_STRAP_MISC
+#define FCH_RCINDXC_REGC1 0xC1 | RCINDXC << 29 // PCIE_STRAP_MISC2
+
+
+//
+// AXINDC Registers
+//
+#define FCH_AX_INDXC_REG02 0x02 // PCIEP_HW_DEBUG
+#define FCH_AX_INDXC_REG10 0x10
+#define FCH_AX_INDXC_REG30 0x30
+#define FCH_AX_DATAC_REG34 0x34
+#define FCH_AX_INDXP_REG38 0x38
+#define FCH_AX_DATAP_REG3C 0x3C
+#define FCH_AX_INDXC_REG40 0x40 | AXINDC << 29
+#define FCH_AX_INDXC_REGA4 0xA4 | AXINDC << 29
+
+#define FCH_AX_INDXP_REG02 0x02 | AXINDP << 29
+#define FCH_AX_INDXP_REGA0 0xA0 | AXINDP << 29
+#define FCH_AX_INDXP_REGA4 0xA4 | AXINDP << 29
+#define FCH_AX_INDXP_REGB1 0xB1 | AXINDP << 29
+
+#define FCH_AX_CFG_REG68 0x68 | AXCFG << 29
+#define FCH_AX_CFG_REG88 0x88 | AXCFG << 29
+
+#define FCH_AB_REG04 0x04
+#define FCH_AB_REG40 0x40
+
+//Sata Port Configuration
+#define SIX_PORTS 0
+#define FOUR_PORTS 1
+
+#define SATA_EFUSE_LOCATION 0x10 // EFUSE bit 133
+#define SATA_DH_EFUSE_LOCATION 0x11 // EFUSE bit 138
+#define SATA_FIS_BASE_EFUSE_LOC 0x15 // EFUSE bit 169
+#define SATA_EFUSE_BIT 0x20 //
+#define SATA_DH_EFUSE_BIT 0x04 //
+#define FCH_SATA_REG00 0x000 // Vendor ID - R- 16 bits
+#define FCH_SATA_REG02 0x002 // Device ID - RW -16 bits
+#define FCH_SATA_REG04 0x004 // PCI Command - RW - 16 bits
+#define FCH_SATA_REG06 0x006 // PCI Status - RW - 16 bits
+#define FCH_SATA_REG08 0x008 // Revision ID/PCI Class Code - R - 32 bits - Offset: 08
+#define FCH_SATA_REG0C 0x00C // Cache Line Size - R/W - 8bits
+#define FCH_SATA_REG0D 0x00D // Latency Timer - RW - 8 bits
+#define FCH_SATA_REG0E 0x00E // Header Type - R - 8 bits
+#define FCH_SATA_REG0F 0x00F // BIST - R - 8 bits
+#define FCH_SATA_REG10 0x010 // Base Address Register 0 - RW - 32 bits
+#define FCH_SATA_REG14 0x014 // Base Address Register 1 - RW- 32 bits
+#define FCH_SATA_REG18 0x018 // Base Address Register 2 - RW - 32 bits
+#define FCH_SATA_REG1C 0x01C // Base Address Register 3 - RW - 32 bits
+#define FCH_SATA_REG20 0x020 // Base Address Register 4 - RW - 32 bits
+#define FCH_SATA_REG24 0x024 // Base Address Register 5 - RW - 32 bits
+#define FCH_SATA_REG2C 0x02C // Subsystem Vendor ID - R - 16 bits
+#define FCH_SATA_REG2D 0x02D // Subsystem ID - R - 16 bits
+#define FCH_SATA_REG30 0x030 // Expansion ROM Base Address - 32 bits
+#define FCH_SATA_REG34 0x034 // Capabilities Pointer - R - 32 bits
+#define FCH_SATA_REG3C 0x03C // Interrupt Line - RW - 8 bits
+#define FCH_SATA_REG3D 0x03D // Interrupt Pin - R - 8 bits
+#define FCH_SATA_REG3E 0x03E // Min Grant - R - 8 bits
+#define FCH_SATA_REG3F 0x03F // Max Latency - R - 8 bits
+#define FCH_SATA_REG40 0x040 // Configuration - RW - 32 bits
+#define FCH_SATA_REG44 0x044 // Software Data Register - RW - 32 bits
+#define FCH_SATA_REG48 0x048
+#define FCH_SATA_REG4C 0x04C
+#define FCH_SATA_REG50 0x050 // Message Capability - R - 16 bits
+#define FCH_SATA_REG52 0x052 // Message Control - R/W - 16 bits
+#define FCH_SATA_REG54 0x054 // Message Address - R/W - 32 bits
+#define FCH_SATA_REG58 0x058 // Message Data - R/W - 16 bits
+#define FCH_SATA_REG5C 0x05C // RAMBIST Control Register - R/W - 8 bits
+#define FCH_SATA_REG5D 0x05D // RAMBIST Status0 Register - R - 8 bits
+#define FCH_SATA_REG5E 0x05E // RAMBIST Status1 Register - R - 8 bits
+#define FCH_SATA_REG60 0x060 // Power Management Capabilities - R - 32 bits
+#define FCH_SATA_REG64 0x064 // Power Management Control + Status - RW - 32 bits
+#define FCH_SATA_REG68 0x068 // MSI Program - R/W - 8 bits
+#define FCH_SATA_REG69 0x069 // PCI Burst Timer - R/W - 8 bits
+#define FCH_SATA_REG70 0x070 // PCI Bus Master - IDE0 - RW - 32 bits
+#define FCH_SATA_REG74 0x074 // PRD Table Address - IDE0 - RW - 32 bits
+#define FCH_SATA_REG78 0x078 // PCI Bus Master - IDE1 - RW - 32 bits
+#define FCH_SATA_REG7C 0x07C // PRD Table Address - IDE1 - RW - 32 bits
+#define FCH_SATA_REG80 0x080 // Data Transfer Mode - IDE0 - RW - 32 bits
+#define FCH_SATA_REG84 0x084 // Data Transfer Mode - IDE1 - RW - 32 bits
+#define FCH_SATA_REG86 0x086 // PY Global Control
+#define FCH_SATA_REG87 0x087
+#define FCH_SATA_REG88 0x088 // PHY Port0 Control - Port0 PY fine tune (0:23)
+#define FCH_SATA_REG8A 0x08A
+#define FCH_SATA_REG8C 0x08C // PHY Port1 Control - Port0 PY fine tune (0:23)
+#define FCH_SATA_REG8E 0x08E
+#define FCH_SATA_REG90 0x090 // PHY Port2 Control - Port0 PY fine tune (0:23)
+#define FCH_SATA_REG92 0x092
+#define FCH_SATA_REG94 0x094 // PHY Port3 Control - Port0 PY fine tune (0:23)
+#define FCH_SATA_REG96 0x096
+#define FCH_SATA_REG98 0x098 // EEPROM Memory Address - Command + Status - RW - 32 bits
+#define FCH_SATA_REG9C 0x09C // EEPROM Memory Data - RW - 32 bits
+#define FCH_SATA_REGA0 0x0A0 //
+#define FCH_SATA_REGA4 0x0A4 //
+#define FCH_SATA_REGA5 0x0A5 //;
+#define FCH_SATA_REGA8 0x0A8 //
+#define FCH_SATA_REGAD 0x0AD //;
+#define FCH_SATA_REGB0 0x0B0 // IDE1 Task File Configuration + Status - RW - 32 bits
+#define FCH_SATA_REGB5 0x0B5 //;
+#define FCH_SATA_REGBD 0x0BD //;
+#define FCH_SATA_REGC0 0x0C0 // BA5 Indirect Address - RW - 32 bits
+#define FCH_SATA_REGC4 0x0C4 // BA5 Indirect Access - RW - 32 bits
+
+#define FCH_SATA_BAR5_REG00 0x000 // PCI Bus Master - IDE0 - RW - 32 bits
+#define FCH_SATA_BAR5_REG04 0x004 // PRD Table Address - IDE0 - RW - 32 bits
+#define FCH_SATA_BAR5_REG08 0x008 // PCI Bus Master - IDE1 - RW - 32 bits
+#define FCH_SATA_BAR5_REG0C 0x00C // PRD Table Address - IDE1 - RW - 32 bits
+#define FCH_SATA_BAR5_REG10 0x010 // PCI Bus Master2 - IDE0 - RW - 32 bits
+#define FCH_SATA_BAR5_REG1C 0x01C
+#define FCH_SATA_BAR5_REG18 0x018 // PCI Bus Master2 - IDE1 - RW - 32 bits
+#define FCH_SATA_BAR5_REG20 0x020 // PRD Address - IDE0 - RW - 32 bits
+#define FCH_SATA_BAR5_REG24 0x024 // PCI Bus Master Byte Count - IDE0- RW - 32 bits
+#define FCH_SATA_BAR5_REG28 0x028 // PRD Address - IDE1 - RW - 32 bits
+#define FCH_SATA_BAR5_REG2C 0x02C // PCI Bus Master Byte Count - IDE1 - RW - 32 bits
+#define FCH_SATA_BAR5_REG40 0x040 // FIFO Valid Byte Count and Control - IDE0 - RW - 32 bits
+#define FCH_SATA_BAR5_REG44 0x044 // FIFO Valid Byte Count and Control - IDE1 - RW - 32 bits
+#define FCH_SATA_BAR5_REG48 0x048 // System Configuration Status - Command - RW - 32 bits
+#define FCH_SATA_BAR5_REG4C 0x04C // System Software Data Register - RW - 32 bits
+#define FCH_SATA_BAR5_REG50 0x050 // FLAS Memory Address - Command + Status - RW - 32 bits
+#define FCH_SATA_BAR5_REG54 0x054 // FLAS Memory Data - RW - 32 bits
+#define FCH_SATA_BAR5_REG58 0x058 // EEPROM Memory Address - Command + Status - RW - 32 bits
+#define FCH_SATA_BAR5_REG5C 0x05C // EEPROM Memory Data - RW - 32 bits
+#define FCH_SATA_BAR5_REG60 0x060 // FIFO Port - IDE0 - RW - 32 bits
+#define FCH_SATA_BAR5_REG68 0x068 // FIFO Pointers1- IDE0 - RW - 32 bits
+#define FCH_SATA_BAR5_REG6C 0x06C // FIFO Pointers2- IDE0 - RW - 32 bits
+#define FCH_SATA_BAR5_REG70 0x070 // FIFO Port - IDE1- RW - 32 bits
+#define FCH_SATA_BAR5_REG78 0x078 // FIFO Pointers1- IDE1- RW - 32 bits
+#define FCH_SATA_BAR5_REG7C 0x07C // FIFO Pointers2- IDE1- RW - 32 bits
+#define FCH_SATA_BAR5_REG80 0x080 // IDE0 Task File Register 0- RW - 32 bits
+#define FCH_SATA_BAR5_REG84 0x084 // IDE0 Task File Register 1- RW - 32 bits
+#define FCH_SATA_BAR5_REG88 0x088 // IDE0 Task File Register 2- RW - 32 bits
+#define FCH_SATA_BAR5_REG8C 0x08C // IDE0 Read Data - RW - 32 bits
+#define FCH_SATA_BAR5_REG90 0x090 // IDE0 Task File Register 0 - Command Buffering - RW - 32 bits
+#define FCH_SATA_BAR5_REG94 0x094 // IDE0 Task File Register 1 - Command Buffering - RW - 32 bits
+#define FCH_SATA_BAR5_REG9C 0x09C // IDE0 Virtual DMA/PIO Read Byte Count - RW - 32 bits
+#define FCH_SATA_BAR5_REGA0 0x0A0 // IDE0 Task File Configuration + Status - RW - 32 bits
+#define FCH_SATA_BAR5_REGB4 0x0B4 // Data Transfer Mode -IDE0 - RW - 32 bits
+#define FCH_SATA_BAR5_REGC0 0x0C0 // IDE1 Task File Register 0 - RW - 32 bits
+#define FCH_SATA_BAR5_REGC4 0x0C4 // IDE1 Task File Register 1 - RW - 32 bits
+#define FCH_SATA_BAR5_REGC8 0x0C8 // IDE1 Task File Register 2 - RW - 32 bits
+#define FCH_SATA_BAR5_REGCC 0x0CC // Read/Write Data - RW - 32 bits
+#define FCH_SATA_BAR5_REGD0 0x0D0 // IDE1 Task File Register 0 - Command Buffering - RW - 32 bits
+#define FCH_SATA_BAR5_REGD4 0x0D4 // IDE1 Task File Register 1 - Command Buffering - RW - 32 bits
+#define FCH_SATA_BAR5_REGDC 0x0DC // IDE1 Virtual DMA/PIO Read Byte Count - RW - 32 bits
+#define FCH_SATA_BAR5_REGE0 0x0E0 // IDE1 Task File Configuration + Status - RW - 32 bits
+#define FCH_SATA_BAR5_REGF4 0x0F4 // Data Transfer Mode - IDE1 - RW - 32 bits
+#define FCH_SATA_BAR5_REGF8 0x0F8 // PORT Configuration
+#define FCH_SATA_BAR5_REGFC 0x0FC
+#define FCH_SATA_BAR5_REG100 0x0100 // Serial ATA SControl - RW - 32 bits - [Offset: 100h (channel 1) / 180
+#define FCH_SATA_BAR5_REG104 0x0104 // Serial ATA Sstatus - RW - 32 bits - [Offset: 104h (channel 1) / 184h (cannel
+#define FCH_SATA_BAR5_REG108 0x0108 // Serial ATA Serror - RW - 32 bits - [Offset: 108h (channel 1) / 188h (cannel
+#define FCH_SATA_BAR5_REG10C 0x010C // Serial ATA Sdevice - RW - 32 bits - [Offset: 10Ch (channel 1) / 18Ch (cannel
+#define FCH_SATA_BAR5_REG144 0x0144 // Serial ATA PY Configuration - RW - 32 bits
+#define FCH_SATA_BAR5_REG148 0x0148 // SIEN - RW - 32 bits - [Offset: 148 (channel 1) / 1C8 (cannel 2)]
+#define FCH_SATA_BAR5_REG14C 0x014C // SFISCfg - RW - 32 bits - [Offset: 14C (channel 1) / 1CC (cannel 2)]
+#define FCH_SATA_BAR5_REG120 0x0120 //
+#define FCH_SATA_BAR5_REG128 0x0128 // Port Serial ATA Status
+#define FCH_SATA_BAR5_REG12C 0x012C // Port Serial ATA Control
+#define FCH_SATA_BAR5_REG130 0x0130
+#define FCH_SATA_BAR5_REG1B0 0x01B0
+#define FCH_SATA_BAR5_REG230 0x0230
+#define FCH_SATA_BAR5_REG2B0 0x02B0
+#define FCH_SATA_BAR5_REG330 0x0330
+#define FCH_SATA_BAR5_REG3B0 0x03B0
+#define FCH_SATA_BAR5_REG430 0x0430
+#define FCH_SATA_BAR5_REG4B0 0x04B0
+
+
+// USB ports
+#define NUM_USB1_PORTS 5
+#define NUM_USB2_PORTS 5
+#define NUM_USB3_PORTS 4
+#define NUM_USB4_PORTS 2
+#define NUM_XHC0_PORTS 2
+#define NUM_XHC1_PORTS 2
+
+
+//
+// USB OHCI Device 0x7807
+// Device 18 (0x11)/Device 19 (0x12)/Device 22 (0x16) Func 0
+// Device 20 (0x14) Func 5 (FL) 0x7809
+//
+#define FCH_OHCI_REG00 0x00 // Device/Vendor ID - R (0x43971002ul)
+#define FCH_OHCI_REG04 0x04 // Command - RW
+#define FCH_OHCI_REG06 0x06 // Status - R
+#define FCH_OHCI_REG08 0x08 // Revision ID/Class Code - R
+#define FCH_OHCI_REG0C 0x0C // Miscellaneous - RW
+#define FCH_OHCI_REG10 0x10 // Bar_OCI - RW
+#define FCH_OHCI_REG2C 0x2C // Subsystem Vendor ID/ Subsystem ID - RW
+#define FCH_OHCI_REG34 0x34 // Capability Pointer - R
+#define FCH_OHCI_REG3C 0x3C // Interrupt Line - RW
+#define FCH_OHCI_REG3D 0x3D // Interrupt Line - RW
+#define FCH_OHCI_REG40 0x40 // Config Timers - RW
+#define FCH_OHCI_REG42 0x42 // Port Disable Control - RW (800)
+#define FCH_OHCI_REG46 0x46 // USB PHY Battery Charger - RW (800)
+#define FCH_OHCI_REG48 0x48 // Port Force Reset - RW (800)
+#define FCH_OHCI_REG4C 0x4C // MSI - RW (800)
+#define FCH_OHCI_REG50 0x50 // Misc Control - RW
+#define FCH_OHCI_REG51 0x51
+#define FCH_OHCI_REG52 0x52
+#define FCH_OHCI_REG58 0x58 // Over Current Control - RW
+#define FCH_OHCI_REG5C 0x5C // Over Current Control - RW
+#define FCH_OHCI_REG60 0x60 // Serial Bus Release Number - RW
+#define FCH_OHCI_REG68 0x68 // Over Current PME Enable - RW
+#define FCH_OHCI_REG74 0x74 // Target Timeout Control - RW
+#define FCH_OHCI_REG80 0x80 //
+#define FCH_OHCI_REGD0 0x0D0 // MSI Control - RW
+#define FCH_OHCI_REGD4 0x0D4 // MSI Address - RW
+#define FCH_OHCI_REGD8 0x0D8 // MSI Data - RW
+#define FCH_OHCI_REGE4 0x0E4 // HT MSI Support
+#define FCH_OHCI_REGF0 0x0F0 // Function Level Reset Capability
+#define FCH_OHCI_REGF4 0x0F4 // Function Level Reset Control
+
+#define FCH_OHCI_BAR_REG00 0x00 // cRevision - R
+#define FCH_OHCI_BAR_REG04 0x04 // cControl
+#define FCH_OHCI_BAR_REG08 0x08 // cCommandStatus
+#define FCH_OHCI_BAR_REG0C 0x0C // cInterruptStatus RW
+#define FCH_OHCI_BAR_REG10 0x10 // cInterruptEnable
+#define FCH_OHCI_BAR_REG14 0x14 // cInterruptDisable
+#define FCH_OHCI_BAR_REG18 0x18 // HcCCA
+#define FCH_OHCI_BAR_REG1C 0x1C // cPeriodCurrentED
+#define FCH_OHCI_BAR_REG20 0x20 // HcControleadED
+#define FCH_OHCI_BAR_REG24 0x24 // cControlCurrentED RW
+#define FCH_OHCI_BAR_REG28 0x28 // HcBulkeadED
+#define FCH_OHCI_BAR_REG2C 0x2C // cBulkCurrentED- RW
+#define FCH_OHCI_BAR_REG30 0x30 // HcDoneead
+#define FCH_OHCI_BAR_REG34 0x34 // cFmInterval
+#define FCH_OHCI_BAR_REG38 0x38 // cFmRemaining
+#define FCH_OHCI_BAR_REG3C 0x3C // cFmNumber
+#define FCH_OHCI_BAR_REG40 0x40 // cPeriodicStart
+#define FCH_OHCI_BAR_REG44 0x44 // HcLSThresold
+#define FCH_OHCI_BAR_REG48 0x48 // HcRDescriptorA
+#define FCH_OHCI_BAR_REG4C 0x4C // HcRDescriptorB
+#define FCH_OHCI_BAR_REG50 0x50 // HcRStatus
+#define FCH_OHCI_BAR_REG54 0x54 // HcRhPortStatus (800)
+#define FCH_OHCI_BAR_REG58 0x58 // HcRhPortStatus NPD (800)
+#define FCH_OHCI_BAR_REGF0 0xF0 // OHCI Loop Back feature Support (800)
+
+#define FCH_OHCI_PORTSC_CCS 0x1 // HcRhPortStatus
+#define FCH_OHCI_PORTSC_PES 0x2 // HcRhPortStatus
+#define FCH_OHCI_PORTSC_PSS 0x4 // HcRhPortStatus
+#define FCH_OHCI_PORTSC_PPS 0x100 // HcRhPortStatus
+#define FCH_OHCI_PORTSC_LSDA 0x200 // HcRhPortStatus
+#define FCH_OHCI_PORTSC_PRS 0x10 // HcRhPortStatus
+
+//
+// USB EHCI Device 0x7808
+// Device 18 (0x11)/Device 19 (0x12)/Device 22 (0x16) Func 2
+//
+#define FCH_EHCI_REG00 0x00 // DEVICE/VENDOR ID - R
+#define FCH_EHCI_REG04 0x04 // Command - RW
+#define FCH_EHCI_REG06 0x06 // Status - R
+#define FCH_EHCI_REG08 0x08 // Revision ID/Class Code - R
+#define FCH_EHCI_REG0C 0x0C // Miscellaneous - RW
+#define FCH_EHCI_REG10 0x10 // BAR - RW
+#define FCH_EHCI_REG2C 0x2C // Subsystem ID/Subsystem Vendor ID - RW
+#define FCH_EHCI_REG34 0x34 // Capability Pointer - R
+#define FCH_EHCI_REG3C 0x3C // Interrupt Line - RW
+#define FCH_EHCI_REG3D 0x3D // Interrupt Line - RW
+#define FCH_EHCI_REG40 0x40 // Config Timers - RW
+#define FCH_EHCI_REG4C 0x4C // MSI - RW
+#define FCH_EHCI_REG50 0x50 // EHCI Misc Control - RW
+#define FCH_EHCI_REG54 0x54 // EHCI Misc Control - RW
+#define FCH_EHCI_REG60 0x60 // SBRN - R
+#define FCH_EHCI_REG61 0x61 // FLADJ - RW
+#define FCH_EHCI_REG62 0x62 // PORTWAKECAP - RW
+#define FCH_EHCI_REG64 0x64 // Misc Control 2 - RW
+#define FCH_EHCI_REG70 0x70 // Over Current Control - RW
+#define FCH_EHCI_REG74 0x74 // EHCI Misc Control2 - RW
+#define FCH_EHCI_REG84 0x84 // HUB Configure 1 - RW
+#define FCH_EHCI_REG88 0x88 // - RW
+#define FCH_EHCI_REG90 0x90 // HUB Configure 4 - RW
+#define FCH_EHCI_REGA0 0xA0 //
+#define FCH_EHCI_REGA4 0xA4 //
+#define FCH_EHCI_REGC0 0x0C0 // PME control - RW (800)
+#define FCH_EHCI_REGC4 0x0C4 // PME Data /Status - RW (800)
+#define FCH_EHCI_REGD0 0x0D0 // MSI Control - RW
+#define FCH_EHCI_REGD4 0x0D4 // MSI Address - RW
+#define FCH_EHCI_REGD8 0x0D8 // MSI Data - RW
+#define FCH_EHCI_REGE4 0x0E4 // EHCI Debug Port Support - RW (800)
+#define FCH_EHCI_REGF0 0x0F0 // Function Level Reset Capability - R (800)
+#define FCH_EHCI_REGF4 0x0F4 // Function Level Reset Capability - R (800)
+
+#define FCH_EHCI_BAR_REG00 0x00 // CAPLENGT - R
+#define FCH_EHCI_BAR_REG02 0x002 // CIVERSION- R
+#define FCH_EHCI_BAR_REG04 0x004 // CSPARAMS - R
+#define FCH_EHCI_BAR_REG08 0x008 // CCPARAMS - R
+#define FCH_EHCI_BAR_REG0C 0x00C // CSP-PORTROUTE - R
+
+#define FCH_EHCI_BAR_REG20 0x020 // USBCMD - RW - 32 bits
+#define FCH_EHCI_BAR_REG24 0x024 // USBSTS - RW - 32 bits
+#define FCH_EHCI_BAR_REG28 0x028 // USBINTR -RW - 32 bits
+#define FCH_EHCI_BAR_REG2C 0x02C // FRINDEX -RW - 32 bits
+#define FCH_EHCI_BAR_REG30 0x030 // CTRLDSSEGMENT -RW - 32 bits
+#define FCH_EHCI_BAR_REG34 0x034 // PERIODICLISTBASE -RW - 32 bits
+#define FCH_EHCI_BAR_REG38 0x038 // ASYNCLISTADDR -RW - 32 bits
+#define FCH_EHCI_BAR_REG60 0x060 // CONFIGFLAG -RW - 32 bits
+#define FCH_EHCI_BAR_REG64 0x064 // PORTSC (1-N_PORTS) -RW - 32 bits
+#define FCH_EHCI_BAR_REGA0 0x0A0 // DebugPort MISC Control - RW - 32 bits (800)
+#define FCH_EHCI_BAR_REGA4 0x0A4 // Packet Buffer Threshold Values - RW - 32 bits
+#define FCH_EHCI_BAR_REGA8 0x0A8 // USB PHY Status 0 - R
+#define FCH_EHCI_BAR_REGAC 0x0AC // USB PHY Status 1 - R
+#define FCH_EHCI_BAR_REGB0 0x0B0 // USB PHY Status 2 - R
+#define FCH_EHCI_BAR_REGB4 0x0B4 // UTMI Control - RW (800)
+#define FCH_EHCI_BAR_REGB8 0x0B8 // Loopback Test
+#define FCH_EHCI_BAR_REGBC 0x0BC // EHCI MISC Control
+#define FCH_EHCI_BAR_REGC0 0x0C0 // USB PHY Calibration
+#define FCH_EHCI_BAR_REGC4 0x0C4 // USB Common PHY Control
+#define FCH_EHCI_BAR_REGC8 0x0C8 // EHCI Debug Purpose
+#define FCH_EHCI_BAR_REGCC 0x0CC // Ehci Spare 1 (800) **
+#define FCH_EHCI_BAR_REGD0 0x0D0
+#define FCH_EHCI_BAR_REGD4 0x0D4
+#define FCH_EHCI_BAR_REGDC 0x0DC
+#define FCH_EHCI_BAR_REG100 0x100 // USB debug port
+
+//
+// USB XHCI Device 0x7812/0x7814
+// Device 16 (0x10) Func 0/1
+//
+#define FCH_XHCI_REG00 0x00 // DEVICE/VENDOR ID - R
+#define FCH_XHCI_REG04 0x04 // Command - RW
+#define FCH_XHCI_REG10 0x10 // Bar0
+#define FCH_XHCI_REG2C 0x2C // Sub System ID
+#define FCH_XHCI_REG40 0x40 // Index0
+#define FCH_XHCI_REG44 0x44 // Data0
+#define FCH_XHCI_REG48 0x48 // Index1
+#define FCH_XHCI_REG4C 0x4C // Data0
+#define FCH_XHCI_REG54 0x54 // PME Control/Status
+#define XHCI_EFUSE_LOCATION 0x18 // EFUSE bit 192, 193
+
+#define FCH_XHCI_BAR_REG420 0x420 // Port Status and Control
+#define FCH_XHCI_PORTSC_CCS 0x1 // Port Status and Control
+#define FCH_XHCI_PORTSC_PED 0x2 // Port Status and Control
+#define FCH_XHCI_PORTSC_PLS 0x1E0 // Port Status and Control
+#define FCH_XHCI_PORTSC_SPEED 0x3C00 // Port Status and Control
+#define FCH_XHCI_PORTSC_PR 0x10 // Port Status and Control
+
+//
+// FCH CFG device 0x780B
+// Device 20 (0x14) Func 0
+//
+#define FCH_CFG_REG00 0x000 // VendorID - R
+#define FCH_CFG_REG02 0x002 // DeviceID - R
+#define FCH_CFG_REG04 0x004 // Command- RW
+#define FCH_CFG_REG05 0x005 // Command- RW
+#define FCH_CFG_REG06 0x006 // STATUS- RW
+#define FCH_CFG_REG08 0x008 // Revision ID/Class Code- R
+#define FCH_CFG_REG0A 0x00A //
+#define FCH_CFG_REG0B 0x00B //
+#define FCH_CFG_REG0C 0x00C // Cache Line Size- R
+#define FCH_CFG_REG0D 0x00D // Latency Timer- R
+#define FCH_CFG_REG0E 0x00E // Header Type- R
+#define FCH_CFG_REG0F 0x00F // BIST- R
+#define FCH_CFG_REG10 0x010 // Base Address 0- R
+#define FCH_CFG_REG11 0x011 //;
+#define FCH_CFG_REG12 0x012 //;
+#define FCH_CFG_REG13 0x013 //;
+#define FCH_CFG_REG14 0x014 // Base Address 1- R
+#define FCH_CFG_REG18 0x018 // Base Address 2- R
+#define FCH_CFG_REG1C 0x01C // Base Address 3- R
+#define FCH_CFG_REG20 0x020 // Base Address 4- R
+#define FCH_CFG_REG24 0x024 // Base Address 5- R
+#define FCH_CFG_REG28 0x028 // Cardbus CIS Pointer- R
+#define FCH_CFG_REG2C 0x02C // Subsystem Vendor ID- W
+#define FCH_CFG_REG2E 0x02E // Subsystem ID- W
+#define FCH_CFG_REG30 0x030 // Expansion ROM Base Address - R
+#define FCH_CFG_REG34 0x034 // Capability Pointer - R (800) default changed as 0x00
+#define FCH_CFG_REG3C 0x03C // Interrupt Line - R
+#define FCH_CFG_REG3D 0x03D // Interrupt Pin - R
+#define FCH_CFG_REG3E 0x03E // Min_Gnt - R
+#define FCH_CFG_REG3F 0x03F // Max_Lat - R
+#define FCH_CFG_REG90 0x090 // Smbus Base Address - R
+#define FCH_CFG_REG9C 0x09C // SBResourceMMIO_BASE
+
+//
+// FCH SATA IDE device
+// Device 20 (0x14) Func 1
+//
+
+#define FCH_IDE_REG00 0x00 // Vendor ID
+#define FCH_IDE_REG02 0x02 // Device ID
+#define FCH_IDE_REG04 0x04 // Command
+#define FCH_IDE_REG06 0x06 // Status
+#define FCH_IDE_REG08 0x08 // Revision ID/Class Code
+#define FCH_IDE_REG09 0x09 // Class Code
+#define FCH_IDE_REG2C 0x2C // Subsystem ID and Subsystem Vendor ID
+#define FCH_IDE_REG40 0x40 // Configuration - RW - 32 bits
+#define FCH_IDE_REG34 0x34
+#define FCH_IDE_REG62 0x62 // IDE Internal Control
+#define FCH_IDE_REG63 0x63 // IDE Internal Control
+//
+// FCH AZALIA device 0x780D
+// Device 20 (0x14) Func 2
+//
+#define ATI_AZALIA_ExtBlk_Addr 0x0F8
+#define ATI_AZALIA_ExtBlk_DATA 0x0FC
+
+#define FCH_AZ_REG00 0x00 // Vendor ID - R
+#define FCH_AZ_REG02 0x02 // Device ID - R/W
+#define FCH_AZ_REG04 0x04 // PCI Command
+#define FCH_AZ_REG06 0x06 // PCI Status - R/W
+#define FCH_AZ_REG08 0x08 // Revision ID
+#define FCH_AZ_REG09 0x09 // Programming Interface
+#define FCH_AZ_REG0A 0x0A // Sub Class Code
+#define FCH_AZ_REG0B 0x0B // Base Class Code
+#define FCH_AZ_REG0C 0x0C // Cache Line Size - R/W
+#define FCH_AZ_REG0D 0x0D // Latency Timer
+#define FCH_AZ_REG0E 0x0E // Header Type
+#define FCH_AZ_REG0F 0x0F // BIST
+#define FCH_AZ_REG10 0x10 // Lower Base Address Register
+#define FCH_AZ_REG14 0x14 // Upper Base Address Register
+#define FCH_AZ_REG2C 0x2C // Subsystem Vendor ID
+#define FCH_AZ_REG2D 0x2D // Subsystem ID
+#define FCH_AZ_REG34 0x34 // Capabilities Pointer
+#define FCH_AZ_REG3C 0x3C // Interrupt Line
+#define FCH_AZ_REG3D 0x3D // Interrupt Pin
+#define FCH_AZ_REG3E 0x3E // Minimum Grant
+#define FCH_AZ_REG3F 0x3F // Maximum Latency
+#define FCH_AZ_REG40 0x40 // Misc Control 1
+#define FCH_AZ_REG42 0x42 // Misc Control 2 Register
+#define FCH_AZ_REG43 0x43 // Misc Control 3 Register
+#define FCH_AZ_REG44 0x44 // Interrupt Pin Control Register
+#define FCH_AZ_REG46 0x46 // Debug Control Register
+#define FCH_AZ_REG4C 0x4C
+#define FCH_AZ_REG50 0x50 // Power Management Capability ID
+#define FCH_AZ_REG52 0x52 // Power Management Capabilities
+#define FCH_AZ_REG54 0x54 // Power Management Control/Status
+#define FCH_AZ_REG60 0x60 // MSI Capability ID
+#define FCH_AZ_REG62 0x62 // MSI Message Control
+#define FCH_AZ_REG64 0x64 // MSI Message Lower Address
+#define FCH_AZ_REG68 0x68 // MSI Message Upper Address
+#define FCH_AZ_REG6C 0x6C // MSI Message Data
+
+#define FCH_AZ_BAR_REG00 0x00 // Global Capabilities - R
+#define FCH_AZ_BAR_REG02 0x02 // Minor Version - R
+#define FCH_AZ_BAR_REG03 0x03 // Major Version - R
+#define FCH_AZ_BAR_REG04 0x04 // Output Payload Capability - R
+#define FCH_AZ_BAR_REG06 0x06 // Input Payload Capability - R
+#define FCH_AZ_BAR_REG08 0x08 // Global Control - R/W
+#define FCH_AZ_BAR_REG0C 0x0C // Wake Enable - R/W
+#define FCH_AZ_BAR_REG0E 0x0E // State Change Status - R/W
+#define FCH_AZ_BAR_REG10 0x10 // Global Status - R/W
+#define FCH_AZ_BAR_REG18 0x18 // Output Stream Payload Capability - R
+#define FCH_AZ_BAR_REG1A 0x1A // Input Stream Payload Capability - R
+#define FCH_AZ_BAR_REG20 0x20 // Interrupt Control - R/W
+#define FCH_AZ_BAR_REG24 0x24 // Interrupt Status - R/W
+#define FCH_AZ_BAR_REG30 0x30 // Wall Clock Counter - R
+#define FCH_AZ_BAR_REG38 0x38 // Stream Synchronization - R/W
+#define FCH_AZ_BAR_REG40 0x40 // CORB Lower Base Address - R/W
+#define FCH_AZ_BAR_REG44 0x44 // CORB Upper Base Address - RW
+#define FCH_AZ_BAR_REG48 0x48 // CORB Write Pointer - R/W
+#define FCH_AZ_BAR_REG4A 0x4A // CORB Read Pointer - R/W
+#define FCH_AZ_BAR_REG4C 0x4C // CORB Control - R/W
+#define FCH_AZ_BAR_REG4D 0x4D // CORB Status - R/W
+#define FCH_AZ_BAR_REG4E 0x4E // CORB Size - R/W
+#define FCH_AZ_BAR_REG50 0x50 // RIRB Lower Base Address - RW
+#define FCH_AZ_BAR_REG54 0x54 // RIRB Upper Address - RW
+#define FCH_AZ_BAR_REG58 0x58 // RIRB Write Pointer - RW
+#define FCH_AZ_BAR_REG5A 0x5A // RIRB Response Interrupt Count - R/W
+#define FCH_AZ_BAR_REG5C 0x5C // RIRB Control - R/W
+#define FCH_AZ_BAR_REG5D 0x5D // RIRB Status - R/W
+#define FCH_AZ_BAR_REG5E 0x5E // RIRB Size - R/W
+#define FCH_AZ_BAR_REG60 0x60 // Immediate Command Output Interface - R/W
+#define FCH_AZ_BAR_REG64 0x64 // Immediate Command Input Interface - R/W
+#define FCH_AZ_BAR_REG68 0x68 // Immediate Command Input Interface - R/W
+#define FCH_AZ_BAR_REG70 0x70 // DMA Position Lower Base Address - R/W
+#define FCH_AZ_BAR_REG74 0x74 // DMA Position Upper Base Address - R/W
+#define FCH_AZ_BAR_REG2030 0x2030 // Wall Clock Counter Alias - R
+
+//
+// FCH LPC Device 0x780E
+// Device 20 (0x14) Func 3
+//
+#define FCH_LPC_REG00 0x00 // VID- R
+#define FCH_LPC_REG02 0x02 // DID- R
+#define FCH_LPC_REG04 0x04 // CMD- RW
+#define FCH_LPC_REG06 0x06 // STATUS- RW
+#define FCH_LPC_REG08 0x08 // Revision ID/Class Code - R
+#define FCH_LPC_REG0C 0x0C // Cache Line Size - R
+#define FCH_LPC_REG0D 0x0D // Latency Timer - R
+#define FCH_LPC_REG0E 0x0E // Header Type - R
+#define FCH_LPC_REG0F 0x0F // BIST- R
+#define FCH_LPC_REG10 0x10 // Base Address Reg 0- RW*
+#define FCH_LPC_REG2C 0x2C // Subsystem ID & Subsystem Vendor ID - Wo/Ro
+#define FCH_LPC_REG34 0x34 // Capabilities Pointer - Ro
+#define FCH_LPC_REG40 0x40 // PCI Control - RW
+#define FCH_LPC_REG44 0x44 // IO Port Decode Enable Register 1- RW
+#define FCH_LPC_REG45 0x45 // IO Port Decode Enable Register 2- RW
+#define FCH_LPC_REG46 0x46 // IO Port Decode Enable Register 3- RW
+#define FCH_LPC_REG47 0x47 // IO Port Decode Enable Register 4- RW
+#define FCH_LPC_REG48 0x48 // IO/Mem Port Decode Enable Register 5- RW
+#define FCH_LPC_REG49 0x49 // LPC Sync Timeout Count - RW
+#define FCH_LPC_REG4A 0x4A // IO/Mem Port Decode Enable Register 6- RW
+#define FCH_LPC_REG4C 0x4C // Memory Range Register - RW
+#define FCH_LPC_REG50 0x50 // Rom Protect 0 - RW
+#define FCH_LPC_REG54 0x54 // Rom Protect 1 - RW
+#define FCH_LPC_REG58 0x58 // Rom Protect 2 - RW
+#define FCH_LPC_REG5C 0x5C // Rom Protect 3 - RW
+#define FCH_LPC_REG60 0x60 // PCI Memory Start Address of LPC Target Cycles -
+#define FCH_LPC_REG62 0x62 // PCI Memory End Address of LPC Target Cycles -
+#define FCH_LPC_REG64 0x64 // PCI IO base Address of Wide Generic Port - RW
+#define FCH_LPC_REG65 0x65
+#define FCH_LPC_REG66 0x66
+#define FCH_LPC_REG67 0x67
+#define FCH_LPC_REG68 0x68 // LPC ROM Address Range 1 (Start Address) - RW
+#define FCH_LPC_REG69 0x69
+#define FCH_LPC_REG6A 0x6A // LPC ROM Address Range 1 (End Address) - RW
+#define FCH_LPC_REG6B 0x6B
+#define FCH_LPC_REG6C 0x6C // LPC ROM Address Range 2 (Start Address)- RW
+#define FCH_LPC_REG6D 0x6D
+#define FCH_LPC_REG6E 0x6E // LPC ROM Address Range 2 (End Address) - RW
+#define FCH_LPC_REG6F 0x6F
+#define FCH_LPC_REG70 0x70 // Firmware ub Select - RW*
+#define FCH_LPC_REG71 0x71
+#define FCH_LPC_REG72 0x72
+#define FCH_LPC_REG73 0x73
+#define FCH_LPC_REG74 0x74 // Alternative Wide IO Range Enable- W/R
+#define FCH_LPC_REG78 0x78 // Miscellaneous Control Bits- W/R
+#define FCH_LPC_REG7C 0x7C // TPM (trusted plant form module) reg- W/R
+#define FCH_LPC_REG9C 0x9C
+#define FCH_LPC_REG80 0x80 // MSI Capability Register- R
+#define FCH_LPC_REGA0 0x0A0 // SPI base address
+#define FCH_LPC_REGA1 0x0A1 // SPI base address
+#define FCH_LPC_REGA2 0x0A2 // SPI base address
+#define FCH_LPC_REGA3 0x0A3 // SPI base address
+#define FCH_LPC_REGA4 0x0A4
+#define FCH_LPC_REGB8 0x0B8
+#define FCH_LPC_REGBA 0x0BA // EcControl
+#define FCH_LPC_REGBB 0x0BB // HostControl
+#define FCH_LPC_REGC8 0x0C8
+#define FCH_LPC_REGCC 0x0CC // AutoRomCfg
+#define FCH_LPC_REGD0 0x0D0
+#define FCH_LPC_REGD3 0x0D3
+#define FCH_LPC_REGD4 0x0D4
+
+//
+// FCH PCIB 0x780F
+// Device 20 (0x14) Func 4
+//
+#define FCH_PCIB_REG04 0x04 // Command
+#define FCH_PCIB_REG0D 0x0D // Primary Master Latency Timer
+#define FCH_PCIB_REG1B 0x1B // Secondary Latency Timer
+#define FCH_PCIB_REG1C 0x1C // IO Base
+#define FCH_PCIB_REG1D 0x1D // IO Limit
+#define FCH_PCIB_REG40 0x40 // CPCTRL
+#define FCH_PCIB_REG42 0x42 // CLKCTRL
+#define FCH_PCIB_REG48 0x48 //
+#define FCH_PCIB_REG4A 0x4A // PCICLK Enable Bits
+#define FCH_PCIB_REG4B 0x4B // Misc Control
+#define FCH_PCIB_REG4C 0x4C // AutoClockRun Control
+#define FCH_PCIB_REG50 0x50 // Dual Address Cycle Enable and PCIB_CLK_Stop Override
+#define FCH_PCIB_REG65 0x65 // Misc Control
+#define FCH_PCIB_REG66 0x66 // Misc Control
+//
+// FCH GEC 0x14E4 0x1699
+// Device 20 (0x14) Func 6
+//
+#define FCH_GEC_REG10 0x10 // GEC BAR
+
+//
+// FCH SD
+// Device 20 (0x14) Func 7
+//
+#define SD_PCI_REG10 0x10
+#define SD_PCI_REG2C 0x2C
+#define SD_PCI_REGA4 0xA4
+#define SD_PCI_REGA8 0xA8
+#define SD_PCI_REGAC 0xAC
+#define SD_PCI_REGB0 0xB0
+#define SD_PCI_REGB8 0xB8
+#define SD_PCI_REGBC 0xBC
+#define SD_PCI_REGD0 0xD0
+#define SD_PCI_REGF0 0xF0
+#define SD_PCI_REGF4 0xF4
+#define SD_PCI_REGF8 0xF8
+#define SD_PCI_REGFC 0xFC
+#define FCH_SD_BAR_REG28 0x28 // SDHC_CTRL1
+#define SD_CARD_PRESENT BIT0
+#define FCH_SD_BAR_REG2C 0x2C // SDHC_CTRL2
+#define FCH_SD_FREQUENCY_SLT BIT2
+#define FCH_SD_BAR_REG3C 0x3C // SDHC_HOST_CTRL2
+#define FCH_SD_1_8V BIT3
+
+//
+// FCH MMIO Base (SMI)
+// offset : 0x200
+//
+#define FCH_SMI_REG00 0x00 // EventStatus
+#define FCH_SMI_REG04 0x04 // EventEnable
+#define FCH_SMI_REG08 0x08 // SciTrig
+#define FCH_SMI_REG0C 0x0C // SciLevl
+#define FCH_SMI_REG10 0x10 // SmiSciStatus
+#define FCH_SMI_REG14 0x14 // SmiSciEn
+#define FCH_SMI_REG18 0x18 // ForceSciEn
+#define FCH_SMI_REG1C 0x1C // SciRwData
+#define FCH_SMI_REG3C 0x3C // DataErrorStatus
+#define FCH_SMI_REG20 0x20 // SciS0En
+#define FCH_SMI_Gevent0 0x40 // SciMap0
+#define FCH_SMI_Gevent1 0x41 // SciMap1
+#define FCH_SMI_Gevent2 0x42 // SciMap2
+#define FCH_SMI_Gevent3 0x43 // SciMap3
+#define FCH_SMI_Gevent4 0x44 // SciMap4
+#define FCH_SMI_Gevent5 0x45 // SciMap5
+#define FCH_SMI_Gevent6 0x46 // SciMap6
+#define FCH_SMI_Gevent7 0x47 // SciMap7
+#define FCH_SMI_Gevent8 0x48 // SciMap8
+#define FCH_SMI_Gevent9 0x49 // SciMap9
+#define FCH_SMI_Gevent10 0x4A // SciMap10
+#define FCH_SMI_Gevent11 0x4B // SciMap11
+#define FCH_SMI_Gevent12 0x4C // SciMap12
+#define FCH_SMI_Gevent13 0x4D // SciMap13
+#define FCH_SMI_Gevent14 0x4E // SciMap14
+#define FCH_SMI_Gevent15 0x4F // SciMap15
+#define FCH_SMI_Gevent16 0x50 // SciMap16
+#define FCH_SMI_Gevent17 0x51 // SciMap17
+#define FCH_SMI_Gevent18 0x52 // SciMap18
+#define FCH_SMI_Gevent19 0x53 // SciMap19
+#define FCH_SMI_Gevent20 0x54 // SciMap20
+#define FCH_SMI_Gevent21 0x55 // SciMap21
+#define FCH_SMI_Gevent22 0x56 // SciMap22
+#define FCH_SMI_Gevent23 0x57 // SciMap23
+#define FCH_SMI_Usbwakup0 0x58 // SciMap24
+#define FCH_SMI_Usbwakup1 0x59 // SciMap25
+#define FCH_SMI_Usbwakup2 0x5A // SciMap26
+#define FCH_SMI_Usbwakup3 0x5B // SciMap27
+#define FCH_SMI_SBGppPme0 0x5C // SciMap28
+#define FCH_SMI_SBGppPme1 0x5D // SciMap29
+#define FCH_SMI_SBGppPme2 0x5E // SciMap30
+#define FCH_SMI_SBGppPme3 0x5F // SciMap31
+#define FCH_SMI_SBGppHp0 0x60 // SciMap32
+#define FCH_SMI_SBGppHp1 0x61 // SciMap33
+#define FCH_SMI_SBGppHp2 0x62 // SciMap34
+#define FCH_SMI_SBGppHp3 0x63 // SciMap35
+#define FCH_SMI_AzaliaPme 0x64 // SciMap36
+#define FCH_SMI_SataGevent0 0x65 // SciMap37
+#define FCH_SMI_SataGevent1 0x66 // SciMap38
+#define FCH_SMI_GecPme 0x67 // SciMap39
+#define FCH_SMI_IMCGevent0 0x68 // SciMap40
+#define FCH_SMI_IMCGevent1 0x69 // SciMap41
+#define FCH_SMI_CIRPme 0x6A // SciMap42
+#define FCH_SMI_WakePinGevent 0x6B // SciMap43
+#define FCH_SMI_FanThGevent 0x6C // SciMap44 //FanThermalGevent
+#define FCH_SMI_ASFMasterIntr 0x6D // SciMap45
+#define FCH_SMI_ASFSlaveIntr 0x6E // SciMap46
+#define FCH_SMI_SMBUS0 0x6F // SciMap47
+#define FCH_SMI_TWARN 0x70 // SciMap48
+#define FCH_SMI_TMI 0x71 // SciMap49 // TrafficMonitorIntr
+#define FCH_SMI_iLLB 0x72 // SciMap50
+#define FCH_SMI_PowerButton 0x73 // SciMap51
+#define FCH_SMI_ProcHot 0x74 // SciMap52
+#define FCH_SMI_APUHwAssertion 0x75 // SciMap53
+#define FCH_SMI_APUSciAssertion 0x76 // SciMap54
+#define FCH_SMI_RAS 0x77 // SciMap55
+#define FCH_SMI_xHC0Pme 0x78 // SciMap56
+#define FCH_SMI_xHC1Pme 0x79 // SciMap57
+#define FCH_SMI_AcDcWake 0x7A // SciMap58
+
+// Empty from 0x72-0x7F
+//#Define FCH_SMI_REG7C 0x7F // SciMap63 ***
+
+#define FCH_SMI_REG80 0x80 // SmiStatus0
+#define FCH_SMI_REG84 0x84 // SmiStatus1
+#define FCH_SMI_REG88 0x88 // SmiStatus2
+#define FCH_SMI_REG8C 0x8C // SmiStatus3
+#define FCH_SMI_REG90 0x90 // SmiStatus4
+#define FCH_SMI_REG94 0x94 // SmiPointer
+#define FCH_SMI_REG96 0x96 // SmiTimer
+#define FCH_SMI_REG98 0x98 // SmiTrig
+#define FCH_SMI_REG9C 0x9C // SmiTrig
+#define FCH_SMI_REGA0 0xA0
+#define FCH_SMI_REGA1 0xA1
+#define FCH_SMI_REGA2 0xA2
+#define FCH_SMI_REGA3 0xA3
+#define FCH_SMI_REGA4 0xA4
+#define FCH_SMI_REGA5 0xA5
+#define FCH_SMI_REGA6 0xA6
+#define FCH_SMI_REGA7 0xA7
+#define FCH_SMI_REGA8 0xA8
+#define FCH_SMI_REGA9 0xA9
+#define FCH_SMI_REGAA 0xAA
+#define FCH_SMI_REGAB 0xAB
+#define FCH_SMI_REGAC 0xAC
+#define FCH_SMI_REGAD 0xAD
+#define FCH_SMI_REGAE 0xAE
+#define FCH_SMI_REGAF 0xAF
+#define FCH_SMI_REGB0 0xB0
+#define FCH_SMI_REGB1 0xB1
+#define FCH_SMI_REGB2 0xB2
+#define FCH_SMI_REGB3 0xB3
+#define FCH_SMI_REGB4 0xB4
+#define FCH_SMI_REGB5 0xB5
+#define FCH_SMI_REGB6 0xB6
+#define FCH_SMI_REGB7 0xB7
+#define FCH_SMI_REGB8 0xB8
+#define FCH_SMI_REGB9 0xB9
+#define FCH_SMI_REGBA 0xBA
+#define FCH_SMI_REGBB 0xBB
+#define FCH_SMI_REGBC 0xBC
+#define FCH_SMI_REGBD 0xBD
+#define FCH_SMI_REGBE 0xBE
+#define FCH_SMI_REGBF 0xBF
+#define FCH_SMI_REGC0 0xC0
+#define FCH_SMI_REGC1 0xC1
+#define FCH_SMI_REGC2 0xC2
+#define FCH_SMI_REGC3 0xC3
+#define FCH_SMI_REGC4 0xC4
+#define FCH_SMI_REGC5 0xC5
+#define FCH_SMI_REGC6 0xC6
+#define FCH_SMI_REGC7 0xC7
+#define FCH_SMI_REGC8 0xC8
+#define FCH_SMI_REGCA 0xCA // IoTrapping1
+#define FCH_SMI_REGCC 0xCC // IoTrapping2
+#define FCH_SMI_REGCE 0xCE // IoTrapping3
+#define FCH_SMI_TRAPPING_WRITE 0x01
+#define FCH_SMI_REGD0 0xD0 // MemTrapping0
+#define FCH_SMI_REGD4 0xD4 // MemRdOvrData0
+#define FCH_SMI_REGD8 0xD8 // MemTrapping1
+#define FCH_SMI_REGDC 0xDC // MemRdOvrData1
+#define FCH_SMI_REGE0 0xE0 // MemTrapping2
+#define FCH_SMI_REGE4 0xE4 // MemRdOvrData2
+#define FCH_SMI_REGE8 0xE8 // MemTrapping3
+#define FCH_SMI_REGEC 0xEC // MemRdOvrData3
+#define FCH_SMI_REGF0 0xF0 // CfgTrapping0
+#define FCH_SMI_REGF4 0xF4 // CfgTrapping1
+#define FCH_SMI_REGF8 0xF8 // CfgTrapping2
+#define FCH_SMI_REGFC 0xFC // CfgTrapping3
+
+//
+// FCH MMIO Base (PMIO)
+// offset : 0x300
+//
+#define FCH_PMIOA_REG00 0x00 // ISA Decode
+#define FCH_PMIOA_REG04 0x04 // ISA Control
+#define FCH_PMIOA_REG08 0x08 // PCI Control
+#define FCH_PMIOA_REG0C 0x0C // StpClkSmaf
+#define FCH_PMIOA_REG10 0x10 // RetryDetect
+#define FCH_PMIOA_REG14 0x14 // StuckDetect
+#define FCH_PMIOA_REG20 0x20 // BiosRamEn
+#define FCH_PMIOA_REG24 0x24 // AcpiMmioEn
+#define FCH_PMIOA_REG28 0x28 // AsfEn
+#define FCH_PMIOA_REG2C 0x2C // Smbus0En
+#define FCH_PMIOA_REG2E 0x2E // Smbus0Sel
+#define FCH_PMIOA_REG34 0x34 // IoApicEn
+#define FCH_PMIOA_REG3C 0x3C // SmartVoltEn
+#define FCH_PMIOA_REG40 0x40 // SmartVolt2En
+#define FCH_PMIOA_REG44 0x44 // BootTimerEn
+#define FCH_PMIOA_REG48 0x48 // WatchDogTimerEn
+#define FCH_PMIOA_REG4C 0x4C // WatchDogTimerConfig
+#define FCH_PMIOA_REG50 0x50 // HPETEn
+#define FCH_PMIOA_REG54 0x54 // SerialIrqConfig
+#define FCH_PMIOA_REG56 0x56 // RtcControl
+#define FCH_PMIOA_REG58 0x58 // VRT_T1
+#define FCH_PMIOA_REG59 0x59 // VRT_T2
+#define FCH_PMIOA_REG5A 0x5A // IntruderControl
+#define FCH_PMIOA_REG5B 0x5B // RtcShadow
+#define FCH_PMIOA_REG5C 0x5C
+#define FCH_PMIOA_REG5D 0x5D
+#define FCH_PMIOA_REG5E 0x5E // RtcExtIndex
+#define FCH_PMIOA_REG5F 0x5F // RtcExtData
+#define FCH_PMIOA_REG60 0x60 // AcpiPm1EvtBlk
+#define FCH_PMIOA_REG62 0x62 // AcpiPm1CntBlk
+#define FCH_PMIOA_REG64 0x64 // AcpiPmTmrBlk
+#define FCH_PMIOA_REG66 0x66 // P_CNTBlk
+#define FCH_PMIOA_REG68 0x68 // AcpiGpe0Blk
+#define FCH_PMIOA_REG6A 0x6A // AcpiSmiCmd
+#define FCH_PMIOA_REG6C 0x6C // AcpiPm2CntBlk
+#define FCH_PMIOA_REG6E 0x6E // AcpiPmaCntBlk
+#define FCH_PMIOA_REG74 0x74 // AcpiConfig
+#define FCH_PMIOA_REG78 0x78 // WakeIoAddr
+#define FCH_PMIOA_REG7A 0x7A // HaltCountEn
+#define FCH_PMIOA_REG7C 0x7C // C1eWrPortAdr
+#define FCH_PMIOA_REG7E 0x7E // CStateEn
+#define FCH_PMIOA_REG7F 0x7F // CStateEn
+#define FCH_PMIOA_REG80 0x80 // BreakEvent
+#define FCH_PMIOA_REG84 0x84 // AutoArbEn
+#define FCH_PMIOA_REG88 0x88 // CStateControl
+#define FCH_PMIOA_REG89 0x89 //
+#define FCH_PMIOA_REG8C 0x8C // StpClkHoldTime
+#define FCH_PMIOA_REG8E 0x8E // PopUpEndTime
+#define FCH_PMIOA_REG90 0x90 // C4Control
+#define FCH_PMIOA_REG94 0x94 // CStateTiming0
+#define FCH_PMIOA_REG96 0x96 //
+#define FCH_PMIOA_REG97 0x97 //
+#define FCH_PMIOA_REG98 0x98 // CStateTiming1
+#define FCH_PMIOA_REG99 0x99 //
+#define FCH_PMIOA_REG9B 0x9B //
+#define FCH_PMIOA_REG9C 0x9C // C2Count
+#define FCH_PMIOA_REG9D 0x9D // C3Count
+#define FCH_PMIOA_REG9E 0x9E // C4Count
+#define FCH_PMIOA_REGA0 0xA0 // MessageCState
+#define FCH_PMIOA_REGA4 0xA4 //
+#define FCH_PMIOA_REGA8 0xA8 // TrafficMonitorIdleTime
+#define FCH_PMIOA_REGAA 0xAA // TrafficMonitorIntTime
+#define FCH_PMIOA_REGAC 0xAC // TrafficMonitorTrafficCount
+#define FCH_PMIOA_REGAE 0xAE // TrafficMonitorIntrCount
+#define FCH_PMIOA_REGB0 0xB0 // TrafficMonitorTimeTick
+#define FCH_PMIOA_REGB4 0xB4 // FidVidControl
+#define FCH_PMIOA_REGB6 0xB6 // TPRESET1
+#define FCH_PMIOA_REGB7 0xB7 // Tpreset1b
+#define FCH_PMIOA_REGB8 0xB8 // TPRESET2
+#define FCH_PMIOA_REGB9 0xB9 // Test0
+#define FCH_PMIOA_REGBA 0xBA // S_StateControl
+#define FCH_PMIOA_REGBB 0xBB //
+#define FCH_PMIOA_REGBC 0xBC // ThrottlingControl
+#define FCH_PMIOA_REGBE 0xBE // ResetControl
+#define FCH_PMIOA_REGBF 0xBF // ResetControl
+#define FCH_PMIOA_REGC0 0xC0 // S5Status
+#define FCH_PMIOA_REGC2 0xC2 // ResetStatus
+#define FCH_PMIOA_REGC4 0xC4 // ResetCommand
+#define FCH_PMIOA_REGC5 0xC5 // CF9Shadow
+#define FCH_PMIOA_REGC6 0xC6 // HTControl
+#define FCH_PMIOA_REGC8 0xC8 // Misc
+#define FCH_PMIOA_REGCC 0xCC // IoDrvSth
+#define FCH_PMIOA_REGD0 0xD0 // CLKRunEn
+#define FCH_PMIOA_REGD2 0xD2 // PmioDebug
+#define FCH_PMIOA_REGD3 0xD3 // SD
+#define FCH_PMIOA_REGD6 0xD6 // IMCGating
+#define FCH_PMIOA_REGD7 0xD7 //
+#define FCH_PMIOA_REGD8 0xD8 // MiscIndex
+#define FCH_PMIOA_REGD9 0xD9 // MiscData
+#define FCH_PMIOA_REGDA 0xDA // SataConfig
+#define FCH_PMIOA_REGDC 0xDC // HyperFlashConfig
+#define FCH_PMIOA_REGDE 0xDE // ABConfig
+#define FCH_PMIOA_REGE0 0xE0 // ABRegBar
+#define FCH_PMIOA_REGE4 0xE4
+#define FCH_PMIOA_REGE6 0xE6 // FcEn
+#define FCH_PMIOA_REGE7 0xE7
+#define FCH_PMIOA_REGE8 0xE8
+#define FCH_PMIOA_REGEA 0xEA // PcibConfig
+#define FCH_PMIOA_REGEB 0xEB // AzEn
+#define FCH_PMIOA_REGEC 0xEC // LpcGating
+#define FCH_PMIOA_REGED 0xED // UsbGating
+#define FCH_PMIOA_REGEE 0xEE // UsbCntrl
+#define FCH_PMIOA_REGEF 0xEF // UsbEnable
+#define FCH_PMIOA_REGF0 0xF0 // UsbControl
+#define FCH_PMIOA_REGF2 0xF2 // UsbControl2
+#define FCH_PMIOA_REGF3 0xF3 // UsbDebug
+#define FCH_PMIOA_REGF4 0xF4 // UsbDebug
+#define FCH_PMIOA_REGF6 0xF6 // GecEn
+#define FCH_PMIOA_REGF8 0xF8 // GecConfig
+#define FCH_PMIOA_REGFC 0xFC // TraceMemoryEn
+
+//
+// FCH MMIO Base (PMIO2)
+// offset : 0x400
+//
+#define FCH_PMIO2_REG00 0x00 // Fan0InputControl
+#define FCH_PMIO2_REG01 0x01 // Fan0Control
+#define FCH_PMIO2_REG02 0x02 // Fan0Freq
+#define FCH_PMIO2_REG03 0x03 // LowDuty0
+#define FCH_PMIO2_REG04 0x04 // MidDuty0
+
+#define FCH_PMIO2_REG10 0x00 // Fan1InputControl
+#define FCH_PMIO2_REG11 0x01 // Fan1Control
+#define FCH_PMIO2_REG12 0x02 // Fan1Freq
+#define FCH_PMIO2_REG13 0x03 // LowDuty1
+#define FCH_PMIO2_REG14 0x04 // MidDuty1
+
+#define FCH_PMIO2_REG63 0x63 // SampleFreqDiv
+#define FCH_PMIO2_REG69 0x69 // Fan0 Speed
+#define FCH_PMIO2_REG95 0x95 // Temperature
+#define FCH_PMIO2_REGB8 0xB8 // Voltage
+#define FCH_PMIO2_REGEA 0xEA // Hwm_Calibration
+
+#define FCH_PMIO2_REG92 0x92 //
+#define FCH_PMIO2_REGF8 0xF8 // VoltageSamleSel
+#define FCH_PMIO2_REGF9 0xF9 // TempSampleSel
+
+#define FCH_PMIO2_REG 0xFC // TraceMemoryEn
+
+
+//
+// FCH MMIO Base (GPIO/IoMux)
+// offset : 0x100/0xD00
+//
+/*
+GPIO from 0 ~ 67, (GEVENT 0-23) 128 ~ 150, 160 ~ 226.
+*/
+#define FCH_GPIO_REG00 0x00
+#define FCH_GPIO_REG06 0x06
+#define FCH_GPIO_REG09 0x09
+#define FCH_GPIO_REG10 0x0A
+#define FCH_GPIO_REG17 0x11
+#define FCH_GPIO_REG21 0x15
+#define FCH_GPIO_REG28 0x1C
+#define FCH_GPIO_REG32 0x20
+#define FCH_GPIO_REG33 0x21
+#define FCH_GPIO_REG34 0x22
+#define FCH_GPIO_REG35 0x23
+#define FCH_GPIO_REG36 0x24
+#define FCH_GPIO_REG37 0x25
+#define FCH_GPIO_REG38 0x26
+#define FCH_GPIO_REG39 0x27
+#define FCH_GPIO_REG40 0x28
+#define FCH_GPIO_REG41 0x29
+#define FCH_GPIO_REG42 0x2A
+#define FCH_GPIO_REG43 0x2B
+#define FCH_GPIO_REG44 0x2C
+#define FCH_GPIO_REG45 0x2D
+#define FCH_GPIO_REG46 0x2E
+#define FCH_GPIO_REG47 0x2F
+#define FCH_GPIO_REG48 0x30
+#define FCH_GPIO_REG49 0x31
+#define FCH_GPIO_REG50 0x32
+#define FCH_GPIO_REG51 0x33
+#define FCH_GPIO_REG52 0x34
+#define FCH_GPIO_REG53 0x35
+#define FCH_GPIO_REG54 0x36
+#define FCH_GPIO_REG55 0x37
+#define FCH_GPIO_REG56 0x38
+#define FCH_GPIO_REG57 0x39
+#define FCH_GPIO_REG58 0x3A
+#define FCH_GPIO_REG59 0x3B
+#define FCH_GPIO_REG60 0x3C
+#define FCH_GPIO_REG61 0x3D
+#define FCH_GPIO_REG62 0x3E
+#define FCH_GPIO_REG63 0x3F
+#define FCH_GPIO_REG64 0x40
+#define FCH_GPIO_REG65 0x41
+#define FCH_GPIO_REG66 0x42
+#define FCH_GPIO_REG67 0x43
+#define FCH_GPIO_REG68 0x44
+#define FCH_GPIO_REG69 0x45
+#define FCH_GPIO_REG70 0x46
+#define FCH_GPIO_REG71 0x47
+#define FCH_GPIO_REG72 0x48
+#define FCH_GPIO_REG73 0x49
+#define FCH_GPIO_REG74 0x4A
+#define FCH_GPIO_REG75 0x4B
+#define FCH_GPIO_REG76 0x4C
+#define FCH_GPIO_REG77 0x4D
+#define FCH_GPIO_REG78 0x4E
+#define FCH_GPIO_REG79 0x4F
+#define FCH_GPIO_REG80 0x50
+
+#define FCH_GEVENT_REG00 0x60
+#define FCH_GEVENT_REG01 0x61
+#define FCH_GEVENT_REG02 0x62
+#define FCH_GEVENT_REG03 0x63
+#define FCH_GEVENT_REG04 0x64
+#define FCH_GEVENT_REG05 0x65
+#define FCH_GEVENT_REG06 0x66
+#define FCH_GEVENT_REG07 0x67
+#define FCH_GEVENT_REG08 0x68
+#define FCH_GEVENT_REG09 0x69
+#define FCH_GEVENT_REG10 0x6A
+#define FCH_GEVENT_REG11 0x6B
+#define FCH_GEVENT_REG12 0x6C
+#define FCH_GEVENT_REG13 0x6D
+#define FCH_GEVENT_REG14 0x6E
+#define FCH_GEVENT_REG15 0x6F
+#define FCH_GEVENT_REG16 0x70
+#define FCH_GEVENT_REG17 0x71
+#define FCH_GEVENT_REG18 0x72
+#define FCH_GEVENT_REG19 0x73
+#define FCH_GEVENT_REG20 0x74
+#define FCH_GEVENT_REG21 0x75
+#define FCH_GEVENT_REG22 0x76
+#define FCH_GEVENT_REG23 0x77
+// S5-DOMAIN GPIO
+#define FCH_GPIO_REG160 0xA0
+#define FCH_GPIO_REG161 0xA1
+#define FCH_GPIO_REG162 0xA2
+#define FCH_GPIO_REG163 0xA3
+#define FCH_GPIO_REG164 0xA4
+#define FCH_GPIO_REG165 0xA5
+#define FCH_GPIO_REG166 0xA6
+#define FCH_GPIO_REG167 0xA7
+#define FCH_GPIO_REG168 0xA8
+#define FCH_GPIO_REG169 0xA9
+#define FCH_GPIO_REG170 0xAA
+#define FCH_GPIO_REG171 0xAB
+#define FCH_GPIO_REG172 0xAC
+#define FCH_GPIO_REG173 0xAD
+#define FCH_GPIO_REG174 0xAE
+#define FCH_GPIO_REG175 0xAF
+#define FCH_GPIO_REG176 0xB0
+#define FCH_GPIO_REG177 0xB1
+#define FCH_GPIO_REG178 0xB2
+#define FCH_GPIO_REG179 0xB3
+#define FCH_GPIO_REG180 0xB4
+#define FCH_GPIO_REG181 0xB5
+#define FCH_GPIO_REG182 0xB6
+#define FCH_GPIO_REG183 0xB7
+#define FCH_GPIO_REG184 0xB8
+#define FCH_GPIO_REG185 0xB9
+#define FCH_GPIO_REG186 0xBA
+#define FCH_GPIO_REG187 0xBB
+#define FCH_GPIO_REG188 0xBC
+#define FCH_GPIO_REG189 0xBD
+#define FCH_GPIO_REG190 0xBE
+#define FCH_GPIO_REG191 0xBF
+#define FCH_GPIO_REG192 0xC0
+#define FCH_GPIO_REG193 0xC1
+#define FCH_GPIO_REG194 0xC2
+#define FCH_GPIO_REG195 0xC3
+#define FCH_GPIO_REG196 0xC4
+#define FCH_GPIO_REG197 0xC5
+#define FCH_GPIO_REG198 0xC6
+#define FCH_GPIO_REG199 0xC7
+#define FCH_GPIO_REG200 0xC8
+#define FCH_GPIO_REG201 0xC9
+#define FCH_GPIO_REG202 0xCA
+#define FCH_GPIO_REG203 0xCB
+#define FCH_GPIO_REG204 0xCC
+#define FCH_GPIO_REG205 0xCD
+#define FCH_GPIO_REG206 0xCE
+#define FCH_GPIO_REG207 0xCF
+#define FCH_GPIO_REG208 0xD0
+#define FCH_GPIO_REG209 0xD1
+#define FCH_GPIO_REG210 0xD2
+#define FCH_GPIO_REG211 0xD3
+#define FCH_GPIO_REG212 0xD4
+#define FCH_GPIO_REG213 0xD5
+#define FCH_GPIO_REG214 0xD6
+#define FCH_GPIO_REG215 0xD7
+#define FCH_GPIO_REG216 0xD8
+#define FCH_GPIO_REG217 0xD9
+#define FCH_GPIO_REG218 0xDA
+#define FCH_GPIO_REG219 0xDB
+#define FCH_GPIO_REG220 0xDC
+#define FCH_GPIO_REG221 0xDD
+#define FCH_GPIO_REG222 0xDE
+#define FCH_GPIO_REG223 0xDF
+#define FCH_GPIO_REG224 0xF0
+#define FCH_GPIO_REG225 0xF1
+#define FCH_GPIO_REG226 0xF2
+#define FCH_GPIO_REG227 0xF3
+#define FCH_GPIO_REG228 0xF4
+
+//
+// FCH MMIO Base (GPIO BANK0)
+// offset : 0x1500
+//
+#define FCH_GPIO_PULL_UP_ENABLE BIT4
+#define FCH_GPIO_PULL_DOWN_ENABLE BIT5
+#define FCH_GPIO_OUTPUT_VALUE BIT6
+#define FCH_GPIO_OUTPUT_ENABLE (1 << 7)
+
+#define FCH_GPIO_068_AZ_SDIN0_GPIO26 0x68
+#define FCH_GPIO_06C_AZ_SDIN1_GPIO27 0x6C
+#define FCH_GPIO_070_AZ_SDIN2_GPIO28 0x70
+#define FCH_GPIO_074_AZ_SDIN3_GPIO29 0x74
+
+#define FCH_GPIO_10C_GPIO55_AGPI067 0x10C
+#define FCH_GPIO_118_GPIO59_AGPI070 0x118
+
+//
+// FCH MMIO Base (IoMux)
+// offset : 0xD00
+//
+#define FCH_IOMUX_1A_AZ_SDIN0_EGPIO26 0x1A
+#define FCH_IOMUX_1B_AZ_SDIN1_EGPIO27 0x1B
+#define FCH_IOMUX_1C_AZ_SDIN2_EGPIO28 0x1C
+#define FCH_IOMUX_1D_AZ_SDIN3_EGPIO29 0x1D
+
+//
+// FCH MMIO Base (SMBUS)
+// offset : 0xA00
+//
+#define FCH_SMBUS_REG12 0x12 // I2CbusConfig
+
+//
+// FCH MMIO Base (MISC)
+// offset : 0xE00
+//
+#define FCH_MISC_REG00 0x00 // ClkCntrl0
+/*
+FCH_MISC_REG00 EQU 000h
+ ClkCntrl0 EQU 0FFFFFFFFh
+*/
+#define FCH_MISC_REG04 0x04 // ClkCntrl1
+/*
+FCH_MISC_REG04 EQU 004h
+ ClkCntrl1 EQU 0FFFFFFFFh
+*/
+#define FCH_MISC_REG08 0x08 // ClkCntrl2
+/*
+FCH_MISC_REG08 EQU 008h
+ ClkCntrl2 EQU 0FFFFFFFFh
+*/
+#define FCH_MISC_REG0C 0x0C // ClkCntrl3
+/*
+FCH_MISC_REG0C EQU 00Ch
+ ClkCntrl3 EQU 0FFFFFFFFh
+*/
+#define FCH_MISC_REG10 0x10 // ClkCntrl4
+/*
+FCH_MISC_REG10 EQU 010h
+ ClkCntrl4 EQU 0FFFFFFFFh
+*/
+#define FCH_MISC_REG14 0x14 // ClkCntrl5
+/*
+FCH_MISC_REG14 EQU 014h
+ ClkCntrl5 EQU 0FFFFFFFFh
+*/
+#define FCH_MISC_REG18 0x18 // ClkCntrl6
+/*
+FCH_MISC_REG18 EQU 018h
+ ClkCntrl6 EQU 0FFFFFFFFh
+*/
+#define FCH_MISC_REG1C 0x1C
+#define FCH_MISC_REG30 0x30 // OscFreqCounter
+/*
+FCH_MISC_REG30 EQU 030h
+ OscCounter EQU 0FFFFFFFFh ; The 32bit register shows the number of OSC clock per second.
+*/
+#define FCH_MISC_REG34 0x34 // HpetClkPeriod
+/*
+FCH_MISC_REG34 EQU 034h
+ HpetClkPeriod EQU 0FFFFFFFFh ; default - 0x429B17Eh (14.31818M).
+*/
+#define FCH_MISC_REG28 0x28 // ClkDrvSth2
+#define FCH_MISC_REG2C 0x2C
+#define FCH_MISC_REG40 0x40 // MiscCntrl for clock only
+#define FCH_MISC_REG41 0x41 // MiscCntr2
+#define FCH_MISC_REG42 0x42 // MiscCntr3
+#define FCH_MISC_REG44 0x44 // ValueOnPort80
+#define FCH_MISC_REG50 0x50 //
+#define FCH_MISCx50_JTAG_CONTROL_ECO 0xFED80E50ul //
+#define FCH_MISCx68_MEMORY_POWER_SAVING_CONTROL 0xFED80E68ul //
+
+#define FCH_MISC_REG6C 0x6C // EcoBit2
+/*
+FCH_MISC_REG40 EQU 040h
+*/
+
+#define FCH_MISC_REG80 0x80 /**< FCH_MISC_REG80
+ * @par
+ * StrapStatus [15.0] - FCH chip Strap Status
+ * @li <b>0001</b> - Not USED FWH
+ * @li <b>0002</b> - Not USED LPC ROM
+ * @li <b>0004</b> - EC enabled
+ * @li <b>0008</b> - Reserved
+ * @li <b>0010</b> - Internal Clock mode
+ */
+#define FCH_MISC_REGB6 0xB6 //
+
+#define ChipSysNotUseFWHRom 0x0001 // EcPwm3 pad
+#define ChipSysNotUseLpcRom 0x0002 // Inverted version from EcPwm2 pad (default - 1)
+ // Note: Both EcPwm3 and EcPwm2 straps pins are used to select boot ROM type.
+#define ChipSysEcEnable 0x0004 // Enable Embedded Controller (EC)
+#define ChipSysBootFailTmrEn 0x0008 // Enable Watchdog function
+#define ChipSysIntClkGen 0x0010 // Select 25Mhz crystal clock or 100Mhz PCI-E clock **
+
+#define FCH_MISC_REG84 0x84 // StrapOverride
+/*
+FCH_MISC_REG84 EQU 084h
+ Override FWHDisableStrap EQU BIT0 ; Override FWHDiableStrap value from external pin.
+ Override UseLpcRomStrap EQU BIT1 ; Override UseLpcRomStrap value from external pin.
+ Override EcEnableStrap EQU BIT2 ; Override EcEnableStrap value from external pin.
+ Override BootFailTmrEnStrap EQU BIT3 ; Override BootFailTmrEnStrap value from external pin.
+ Override DefaultModeStrap EQU BIT5 ; Override DefaultModeStrap value from external pin.
+ Override I2CRomStrap EQU BIT7 ; Override I2CRomStrap value from external pin.
+ Override ILAAutorunEnBStrap EQU BIT8 ; Override ILAAutorunEnBStrap value from external pin.
+ Override FcPllBypStrap EQU BIT9 ; Override FcPllBypStrap value from external pin.
+ Override PciPllBypStrap EQU BIT10 ; Override PciPllBypStrap value from external pin.
+ Override ShortResetStrap EQU BIT11 ; Override ShortResetStrap value from external pin.
+ Override FastBif2ClkStrap EQU BIT13 ; Override FastBif2ClkStrap value from external pin
+ PciRomBootStrap EQU BIT15 ; Override PCI Rom Boot Strap value from external pin
+ BlinkSlowModestrap EQU BIT16 ; Override Blink Slow mode (100Mhz) from external pin
+ ClkGenStrap EQU BIT17 ; Override CLKGEN from external pin.
+ BIF_GEN2_COMPL_Strap EQU BIT18 ; Override BIF_ GEN2_COMPLIANCE strap from external pin.
+ StrapOverrideEn EQU BIT31 ; Enable override strapping feature.
+*/
+#define FCH_MISC_REGC0 0xC0 // CPU_Pstate0
+/*
+FCH_MISC_REGC0 EQU 0C0h
+ Core0_PState EQU BIT0+BIT1+BIT2 ; 000: P0 001: P1 010: P2 011: P3 100: P4 101: P5 110: P6 111: P7
+ Core1_PState EQU BIT4+BIT5+BIT6
+ Core2_PState EQU BIT8+BIT9+BIT10
+ Core3_PState EQU BIT12+BIT13+BIT14
+ Core4_PState EQU BIT16++BIT17+BIT18
+ Core5_PState EQU BIT20+BIT21+BIT22
+ Core6_PState EQU BIT24+BIT25+BIT26
+ Core7_PState EQU BIT28+BIT29+BIT30
+*/
+#define FCH_MISC_REGC4 0xC4 // CPU_Pstate1
+/*
+FCH_MISC_REGC4 EQU 0C4h
+ Core8_PState EQU BIT0+BIT1+BIT2 ; 000: P0 001: P1 010: P2 011: P3 100: P4 101: P5 110: P6 111: P7
+ Core9_PState EQU BIT4+BIT5+BIT6
+ Core10_PState EQU BIT8+BIT9+BIT10
+ Core11_PState EQU BIT12+BIT13+BIT14
+ Core12_PState EQU BIT16++BIT17+BIT18
+ Core13_PState EQU BIT20+BIT21+BIT22
+ Core14_PState EQU BIT24+BIT25+BIT26
+ Core15_PState EQU BIT28+BIT29+BIT30
+*/
+#define FCH_MISC_REGD0 0xD0 // CPU_Cstate0
+/*
+FCH_MISC_REGD0 EQU 0D0h
+ Core0_CState EQU BIT0+BIT1+BIT2 ; 000: C0 001: C1 010: C2 011: C3 100: C4 101: C5 110: C6 111: C7
+ Core1_CState EQU BIT4+BIT5+BIT6
+ Core2_CState EQU BIT8+BIT9+BIT10
+ Core3_CState EQU BIT12+BIT13+BIT14
+ Core4_CState EQU BIT16++BIT17+BIT18
+ Core5_CState EQU BIT20+BIT21+BIT22
+ Core6_CState EQU BIT24+BIT25+BIT26
+ Core7_CState EQU BIT28+BIT29+BIT30
+*/
+#define FCH_MISC_REGD4 0xD4 // CPU_Cstate1
+/*
+FCH_MISC_REGD4 EQU 0D4h
+ Core8_CState EQU BIT0+BIT1+BIT2 ; 000: C0 001: C1 010: C2 011: C3 100: C4 101: C5 110: C6 111: C7
+ Core9_CState EQU BIT4+BIT5+BIT6
+ Core10_CState EQU BIT8+BIT9+BIT10
+ Core11_CState EQU BIT12+BIT13+BIT14
+ Core12_CState EQU BIT16++BIT17+BIT18
+ Core13_CState EQU BIT20+BIT21+BIT22
+ Core14_CState EQU BIT24+BIT25+BIT26
+ Core15_CState EQU BIT28+BIT29+BIT30
+*/
+#define FCH_MISC_REGF0 0xF0 // SataPortSts
+/*
+FCH_MISC_REGF0 EQU 0F0h
+ Port0Sts EQU BIT0 ; The selected status of Port 0.
+ Port1Sts EQU BIT1 ; The selected status of Port 1
+ Port2Sts EQU BIT2 ; The selected status of Port 2.
+ Port3Sts EQU BIT3 ; The selected status of Port 3
+ Port4Sts EQU BIT4 ; The selected status of Port 4.
+ Port5Sts EQU BIT5 ; The selected status of Port 5
+ SataPortSel EQU BIT24+BIT25 ; 00 - Select "led" for Port 0 to 5
+ ; 01 - Select "delete" for Port 0 to 5
+ ; 10 - Select "err" for Port 0 to 5
+ ; 11 - Select "led" for Port 0 to 5
+*/
+
+//
+// FCH MMIO Base (SERIAL_DEBUG_BASE)
+// offset : 0x1000
+//
+#define FCH_SDB_REG00 0x00 //
+#define FCH_SDB_REG74 0x74
+
+#define FCH_RTC_REG00 0x00 // Seconds - RW
+#define FCH_RTC_REG01 0x01 // Seconds Alarm - RW
+#define FCH_RTC_REG02 0x02 // Minutes - RW
+#define FCH_RTC_REG03 0x03 // Minutes Alarm - RW
+#define FCH_RTC_REG04 0x04 // ours - RW
+#define FCH_RTC_REG05 0x05 // ours Alarm- RW
+#define FCH_RTC_REG06 0x06 // Day of Week - RW
+#define FCH_RTC_REG07 0x07 // Date of Mont - RW
+#define FCH_RTC_REG08 0x08 // Mont - RW
+#define FCH_RTC_REG09 0x09 // Year - RW
+#define FCH_RTC_REG0A 0x0A // Register A - RW
+#define FCH_RTC_REG0B 0x0B // Register B - RW
+#define FCH_RTC_REG0C 0x0C // Register C - R
+#define FCH_RTC_REG0D 0x0D // DateAlarm - RW
+#define FCH_RTC_REG32 0x32 // AltCentury - RW
+#define FCH_RTC_REG48 0x48 // Century - RW
+#define FCH_RTC_REG50 0x50 // Extended RAM Address Port - RW
+#define FCH_RTC_REG53 0x53 // Extended RAM Data Port - RW
+#define FCH_RTC_REG7E 0x7E // RTC Time Clear - RW
+#define FCH_RTC_REG7F 0x7F // RTC RAM Enable - RW
+
+#define FCH_ECMOS_REG00 0x00 // scratch - reg
+//;BIT0=0 AsicDebug is enabled
+//;BIT1=0 SLT S3 runs
+#define FCH_ECMOS_REG01 0x01
+#define FCH_ECMOS_REG02 0x02
+#define FCH_ECMOS_REG03 0x03
+#define FCH_ECMOS_REG04 0x04
+#define FCH_ECMOS_REG05 0x05
+#define FCH_ECMOS_REG06 0x06
+#define FCH_ECMOS_REG07 0x07
+#define FCH_ECMOS_REG08 0x08 // save 32BIT Physical address of Config structure
+#define FCH_ECMOS_REG09 0x09
+#define FCH_ECMOS_REG0A 0x0A
+#define FCH_ECMOS_REG0B 0x0B
+
+#define FCH_ECMOS_REG0C 0x0C //;save MODULE_ID
+#define FCH_ECMOS_REG0D 0x0D //;Reserve for NB
+
+//
+#define FCH_PMIOxC0_S5ResetStatus 0xFED803C0ul // S5ResetStatus
+#define FCH_PMIOxC0_S5ResetStatus_ThermalTrip (1 << 0)
+#define FCH_PMIOxC0_S5ResetStatus_FourSecondPwrBtn (1 << 1)
+#define FCH_PMIOxC0_S5ResetStatus_All_Status (0x3ff | (1 << 20))
+
+//
+// FCH MISC Base (FCH_MISC_BASE)
+// offset : 0x0E00
+//
+#define FCH_MISCx50_JTAG_Control_ECO_bits 0xFED80E50ul // JTAG_Control_ECO_bits
+#define FCH_MISCx50_JTAG_Control_ECO_bits_BIT12 (1 << 12)
+#define FCH_MISCx50_JTAG_Control_ECO_bits_BIT16 (1 << 16)
+
+// FCH AOAC Base (FCH_AOAC_BASE)
+// offset : 0x1E00
+//
+#define FCH_AOACx94S013_CONTROL 0xFED81E94ul //
+#define FCH_AOACx94S013_CONTROL_ARBITER_DIS (1 << 14)
+#define FCH_AOACx94S013_CONTROL_INTERRUPT_DIS (1 << 15)
+
+#define FCH_IOMAP_REG00 0x000 // Dma_C 0
+#define FCH_IOMAP_REG02 0x002 // Dma_C 1
+#define FCH_IOMAP_REG04 0x004 // Dma_C 2
+#define FCH_IOMAP_REG06 0x006 // Dma_C 3
+#define FCH_IOMAP_REG08 0x008 // Dma_Status
+#define FCH_IOMAP_REG09 0x009 // Dma_WriteRest
+#define FCH_IOMAP_REG0A 0x00A // Dma_WriteMask
+#define FCH_IOMAP_REG0B 0x00B // Dma_WriteMode
+#define FCH_IOMAP_REG0C 0x00C // Dma_Clear
+#define FCH_IOMAP_REG0D 0x00D // Dma_MasterClr
+#define FCH_IOMAP_REG0E 0x00E // Dma_ClrMask
+#define FCH_IOMAP_REG0F 0x00F // Dma_AllMask
+#define FCH_IOMAP_REG20 0x020 // IntrCntrlReg1
+#define FCH_IOMAP_REG21 0x021 // IntrCntrlReg2
+#define FCH_IOMAP_REG40 0x040 // TimerC0
+#define FCH_IOMAP_REG41 0x041 // TimerC1
+#define FCH_IOMAP_REG42 0x042 // TimerC2
+#define FCH_IOMAP_REG43 0x043 // Tmr1CntrlWord
+#define FCH_IOMAP_REG61 0x061 // Nmi_Status
+#define FCH_IOMAP_REG70 0x070 // Nmi_Enable
+#define FCH_IOMAP_REG71 0x071 // RtcDataPort
+#define FCH_IOMAP_REG72 0x072 // AlternatRtcAddrPort
+#define FCH_IOMAP_REG73 0x073 // AlternatRtcDataPort
+#define FCH_IOMAP_REG80 0x080 // Dma_Page_Reserved0
+#define FCH_IOMAP_REG81 0x081 // Dma_PageC2
+#define FCH_IOMAP_REG82 0x082 // Dma_PageC3
+#define FCH_IOMAP_REG83 0x083 // Dma_PageC1
+#define FCH_IOMAP_REG84 0x084 // Dma_Page_Reserved1
+#define FCH_IOMAP_REG85 0x085 // Dma_Page_Reserved2
+#define FCH_IOMAP_REG86 0x086 // Dma_Page_Reserved3
+#define FCH_IOMAP_REG87 0x087 // Dma_PageC0
+#define FCH_IOMAP_REG88 0x088 // Dma_Page_Reserved4
+#define FCH_IOMAP_REG89 0x089 // Dma_PageC6
+#define FCH_IOMAP_REG8A 0x08A // Dma_PageC7
+#define FCH_IOMAP_REG8B 0x08B // Dma_PageC5
+#define FCH_IOMAP_REG8C 0x08C // Dma_Page_Reserved5
+#define FCH_IOMAP_REG8D 0x08D // Dma_Page_Reserved6
+#define FCH_IOMAP_REG8E 0x08E // Dma_Page_Reserved7
+#define FCH_IOMAP_REG8F 0x08F // Dma_Refres
+#define FCH_IOMAP_REG92 0x092 // FastInit
+#define FCH_IOMAP_REGA0 0x0A0 // IntrCntrl2Reg1
+#define FCH_IOMAP_REGA1 0x0A1 // IntrCntrl2Reg2
+#define FCH_IOMAP_REGC0 0x0C0 // Dma2_C4Addr
+#define FCH_IOMAP_REGC2 0x0C2 // Dma2_C4Cnt
+#define FCH_IOMAP_REGC4 0x0C4 // Dma2_C5Addr
+#define FCH_IOMAP_REGC6 0x0C6 // Dma2_C5Cnt
+#define FCH_IOMAP_REGC8 0x0C8 // Dma2_C6Addr
+#define FCH_IOMAP_REGCA 0x0CA // Dma2_C6Cnt
+#define FCH_IOMAP_REGCC 0x0CC // Dma2_C7Addr
+#define FCH_IOMAP_REGCE 0x0CE // Dma2_C7Cnt
+#define FCH_IOMAP_REGD0 0x0D0 // Dma_Status
+#define FCH_IOMAP_REGD2 0x0D2 // Dma_WriteRest
+#define FCH_IOMAP_REGD4 0x0D4 // Dma_WriteMask
+#define FCH_IOMAP_REGD6 0x0D6 // Dma_WriteMode
+#define FCH_IOMAP_REGD8 0x0D8 // Dma_Clear
+#define FCH_IOMAP_REGDA 0x0DA // Dma_Clear
+#define FCH_IOMAP_REGDC 0x0DC // Dma_ClrMask
+#define FCH_IOMAP_REGDE 0x0DE // Dma_ClrMask
+#define FCH_IOMAP_REGED 0x0ED // DUMMY IO PORT
+#define FCH_IOMAP_REGF0 0x0F0 // NCP_Error
+#define FCH_IOMAP_REG40B 0x040B // DMA1_Extend
+#define FCH_IOMAP_REG4D0 0x04D0 // IntrEdgeControl
+#define FCH_IOMAP_REG4D6 0x04D6 // DMA2_Extend
+#define FCH_IOMAP_REGC00 0x0C00 // Pci_Intr_Index
+#define FCH_IOMAP_REGC01 0x0C01 // Pci_Intr_Data
+#define FCH_IOMAP_REGC14 0x0C14 // Pci_Error
+#define FCH_IOMAP_REGC50 0x0C50 // CMIndex
+#define FCH_IOMAP_REGC51 0x0C51 // CMData
+#define FCH_IOMAP_REGC52 0x0C52 // GpmPort
+#define FCH_IOMAP_REGC6F 0x0C6F // Isa_Misc
+#define FCH_IOMAP_REGCD0 0x0CD0 // PMio2_Index
+#define FCH_IOMAP_REGCD1 0x0CD1 // PMio2_Data
+#define FCH_IOMAP_REGCD4 0x0CD4 // BIOSRAM_Index
+#define FCH_IOMAP_REGCD5 0x0CD5 // BIOSRAM_Data
+#define FCH_IOMAP_REGCD6 0x0CD6 // PM_Index
+#define FCH_IOMAP_REGCD7 0x0CD7 // PM_Data
+#define FCH_IOMAP_REGCF9 0x0CF9 // CF9Rst reg
+
+#define FCH_IRQ_INTA 0x00 // INTA#
+#define FCH_IRQ_INTB 0x01 // INTB#
+#define FCH_IRQ_INTC 0x02 // INTC#
+#define FCH_IRQ_INTD 0x03 // INTD#
+#define FCH_IRQ_INTE 0x04 // INTE#
+#define FCH_IRQ_INTF 0x05 // INTF#
+#define FCH_IRQ_INTG 0x06 // INTG#
+#define FCH_IRQ_INTH 0x07 // INTH#
+#define FCH_IRQ_SCI 0x10 // SCI
+#define FCH_IRQ_SMBUS0 0x11 // SMBUS0
+#define FCH_IRQ_ASF 0x12 // ASF
+#define FCH_IRQ_HDAUDIO 0x13 // HD Audio
+#define FCH_IRQ_FC 0x14 // FC
+#define FCH_IRQ_GEC 0x15 // GEC
+#define FCH_IRQ_SD 0x17 // SD
+#define FCH_IRQ_IMCINT0 0x20 // IMC INT0
+#define FCH_IRQ_IMCINT1 0x21 // IMC INT1
+#define FCH_IRQ_IMCINT2 0x22 // IMC INT2
+#define FCH_IRQ_IMCINT3 0x23 // IMC INT3
+#define FCH_IRQ_IMCINT4 0x24 // IMC INT4
+#define FCH_IRQ_IMCINT5 0x25 // IMC INT5
+#define FCH_IRQ_USB18INTA 0x30 // Dev 18 (USB) INTA#
+#define FCH_IRQ_USB18INTB 0x31 // Dev 18 (USB) INTB#
+#define FCH_IRQ_USB19INTA 0x32 // Dev 19 (USB) INTA#
+#define FCH_IRQ_USB19INTB 0x33 // Dev 19 (USB) INTB#
+#define FCH_IRQ_USB22INTA 0x34 // Dev 22 (USB) INTA#
+#define FCH_IRQ_USB22INTB 0x35 // Dev 22 (USB) INTB#
+#define FCH_IRQ_USB20INTC 0x36 // Dev 20 (USB) INTC#
+#define FCH_IRQ_IDE 0x40 // IDE pci interrupt
+#define FCH_IRQ_SATA 0x41 // SATA pci interrupt
+#define FCH_IRQ_GPPINT0 0x50 // Gpp Int0
+#define FCH_IRQ_GPPINT1 0x51 // Gpp Int1
+#define FCH_IRQ_GPPINT2 0x52 // Gpp Int2
+#define FCH_IRQ_GPPINT3 0x53 // Gpp Int3
+#define FCH_IRQ_GPIO 0x62 // GPIO Controller
+#define FCH_IRQ_IOAPIC 0x80 // Select IRQ routing to IoApic mode
+#define FCH_IRQ_PIC 0x00 // Select IRQ routing to PIC mode
+
+#define FCH_SPI_MMIO_REG00 0x00 //SPI_
+#define FCH_SPI_OPCODE 0x000000FFl //
+#define FCH_SPI_TX_COUNT 0x00000F00l //
+#define FCH_SPI_RX_COUNT 0x0000F000l //
+#define FCH_SPI_EXEC_OPCODE 0x00010000l //
+#define FCH_SPI_FIFO_PTR_CRL 0x00100000l //
+#define FCH_SPI_FIFO_PTR_INC 0x00200000l //
+#define FCH_SPI_BUSY 0x80000000l //
+#define FCH_SPI_MMIO_REG0C 0x0C //SPI_Cntrl1 Register
+#define FCH_SPI_PARAMETER 0x000000FFl //
+#define FCH_SPI_FIFO_PTR 0x00000700l //
+#define FCH_SPI_BYTE_PROGRAM 0xFF000000l //
+#define FCH_SPI_MMIO_REG1C 0x1C //
+#define FCH_SPI_RETRY_TIMES 0x3 //
+
+#define FCH_SPI_MMIO_REG1D 0x1D //
+#define FCH_SPI_MMIO_REG1E 0x1E //
+#define FCH_SPI_MMIO_REG1F 0x1F //
+#define FCH_SPI_MMIO_REG4E 0x4E //
+
+#define FCH_SPI_MMIO_REG1F_X05_TX_BYTE_COUNT 0x05 //
+#define FCH_SPI_MMIO_REG1F_X06_RX_BYTE_COUNT 0x06 //
+
+#define FCH_SPI_MMIO_REG20 0x20 //
+#define FCH_SPI_MMIO_REG22 0x22 //
+#define FCH_SPI_MMIO_REG2C 0x2C //
+#define FCH_SPI_MMIO_REG38 0x38 //
+#define FCH_SPI_MMIO_REG3C 0x3C //
+
+#define FCH_SPI_MMIO_REG45_CMDCODE 0x45 //
+#define FCH_SPI_MMIO_REG47_CMDTRIGGER 0x47 //
+#define FCH_SPI_MMIO_REG48_TXBYTECOUNT 0x48 //
+#define FCH_SPI_MMIO_REG4B_RXBYTECOUNT 0x4B //
+#define FCH_SPI_MMIO_REG4C_SPISTATUS 0x4C //
+#define FCH_SPI_MMIO_REG80_FIFO 0x80 //
+
+#define FCH_SPI_MODE_FAST 0x7 //
+#define FCH_SPI_MODE_NORMAL 0x6 //
+#define FCH_SPI_MODE_QUAL_144 0x5 //
+#define FCH_SPI_MODE_QUAL_122 0x4 //
+#define FCH_SPI_MODE_QUAL_114 0x3 //
+#define FCH_SPI_MODE_QUAL_112 0x2 //
+
+#define FCH_SPI_DEVICE_MODE_DIS 0x7 //
+#define FCH_SPI_DEVICE_MODE_144 0x4 //
+#define FCH_SPI_DEVICE_MODE_114 0x3 //
+#define FCH_SPI_DEVICE_MODE_122 0x2 //
+#define FCH_SPI_DEVICE_MODE_112 0x1 //
+#define FCH_SPI_DEVICE_MODE_FAST 0x0 //
+
+#define FCH_SPI_SPEED_16M 0x4 //
+#define FCH_SPI_SPEED_22M 0x3 //
+#define FCH_SPI_SPEED_33M 0x2 //
+#define FCH_SPI_SPEED_66M 0x1 //
+#define FCH_SPI_SPEED_100M 0x5 //
+
+#define AMD_NB_REG78 0x78
+#define AMD_NB_SCRATCH AMD_NB_REG78
+#define MailBoxPort 0x3E
+
+#define MAX_LT_POLLINGS 0x4000
+#define SMI_TIMER_ENABLE BIT15
+
+
+#define ACPIMMIO32(x) (*(volatile UINT32*)(UINTN)(x))
+#define ACPIMMIO16(x) (*(volatile UINT16*)(UINTN)(x))
+#define ACPIMMIO8(x) (*(volatile UINT8*)(UINTN)(x))
+
+#define U3PLL_LOCK BIT7
+#define U3PLL_RESET BIT8
+#define U3PHY_RESET BIT9
+#define U3CORE_RESET BIT10
+#define XHC0_FUNC_RESET BIT11
+#define XHC1_FUNC_RESET BIT12
+
+#define XHCI_ACPI_MMIO_AMD_REG00 0x00
+#define XHCI_ACPI_MMIO_AMD_REG04 0x04
+#define XHCI_ACPI_MMIO_AMD_REG08 0x08
+#define XHCI_ACPI_MMIO_AMD_REG10 0x10
+#define XHCI_ACPI_MMIO_AMD_REG14 0x14
+#define XHCI_ACPI_MMIO_AMD_REG20 0x20
+#define XHCI_ACPI_MMIO_AMD_REG24 0x24
+#define XHCI_ACPI_MMIO_AMD_REG28 0x28
+#define XHCI_ACPI_MMIO_AMD_REG30 0x30
+#define XHCI_ACPI_MMIO_AMD_REG40 0x40
+#define XHCI_ACPI_MMIO_AMD_REG48 0x48 // USB3.0_Ind_REG Index
+#define XHCI_ACPI_MMIO_AMD_REG4C 0x4C // USB2.0_Ind_REG Data
+#define XHCI_ACPI_MMIO_AMD_REG8C 0x8C
+#define XHCI_ACPI_MMIO_AMD_REG90 0x90 // adaptation timer settings
+#define XHCI_ACPI_MMIO_AMD_REG98 0x98
+#define XHCI_ACPI_MMIO_AMD_REGA0 0xA0 // BAR 0
+#define XHCI_ACPI_MMIO_AMD_REGA4 0xA4 // BAR 1
+#define XHCI_ACPI_MMIO_AMD_REGA8 0xA8 // BAR 2
+#define XHCI_ACPI_MMIO_AMD_REGB0 0xB0 // SPI_Valid_Base.
+#define XHCI_ACPI_MMIO_AMD_REGC0 0xC0 // Firmware starting offset for coping
+#define XHCI_ACPI_MMIO_AMD_REGB4 0xB4
+#define XHCI_ACPI_MMIO_AMD_REGD0 0xD0
+
+#define FCH_XHCI_REG48 0x48 // XHCI IND_REG Index registers
+#define FCH_XHCI_REG4C 0x4C // XHCI IND_REG Data registers
+
+#define FCH_XHCI_IND60_BASE 0x40000000ul //
+
+#define FCH_XHCI_IND60_REG00 FCH_XHCI_IND60_BASE + 0x00 //
+#define FCH_XHCI_IND60_REG04 FCH_XHCI_IND60_BASE + 0x04 //
+#define FCH_XHCI_IND60_REG08 FCH_XHCI_IND60_BASE + 0x08 //
+#define FCH_XHCI_IND60_REG0C FCH_XHCI_IND60_BASE + 0x0C //
+#define FCH_XHCI_IND60_REG18 FCH_XHCI_IND60_BASE + 0x18 //
+#define FCH_XHCI_IND60_REG48 FCH_XHCI_IND60_BASE + 0x48 //
+#define FCH_XHCI_IND60_REG50 FCH_XHCI_IND60_BASE + 0x50 //
+#define FCH_XHCI_IND60_REG54 FCH_XHCI_IND60_BASE + 0x54 //
+
+#define FCH_XHCI_IND_REG00 0x00 //
+#define FCH_XHCI_IND_REG04 0x04 //
+#define FCH_XHCI_IND_REG48 0x48 //
+#define FCH_XHCI_IND_REG54 0x54 //
+#define FCH_XHCI_IND_REG88 0x88 //
+#define FCH_XHCI_IND_REG94 0x94 // adaptation mode settings
+#define FCH_XHCI_IND_REG98 0x98 // CR phase and frequency filter settings
+#define FCH_XHCI_IND_REGC8 0xC8 //
+#define FCH_XHCI_IND_REGD4 0xD4 // adaptation mode settings
+#define FCH_XHCI_IND_REGD8 0xD8 // CR phase and frequency filter settings
+#define FCH_XHCI_IND_REG100 0x100 //
+#define FCH_XHCI_IND_REG120 0x120 //
+#define FCH_XHCI_IND_REG128 0x128 //
+#define MAX_XHCI_PORTS 0x04
+
+//SMBUS
+#define FCH_SMB_IOREG00 0x00 // SMBusStatus
+#define FCH_SMB_IOREG01 0x01 // SMBusSlaveStatus
+#define FCH_SMB_IOREG02 0x02 // SMBusControl
+#define FCH_SMB_IOREG03 0x03 // SMBusHostCmd
+#define FCH_SMB_IOREG04 0x04 // SMBusAddress
+#define FCH_SMB_IOREG05 0x05 // SMBusData0
+#define FCH_SMB_IOREG06 0x06 // SMBusData1
+#define FCH_SMB_IOREG07 0x07 // SMBusBlockData
+#define FCH_SMB_IOREG08 0x08 // SMBusSlaveControl
+#define FCH_SMB_IOREG14 0x14 // SMBusAutoPoll
+#define FCH_SMB_IOREG16 0x16 // SMBusPausePoll
+#define FCH_SMB_IOREG17 0x17 // SMBusHostCmd2
+
+#define FCH_SMB_CMD_QUICK 0x00 << 2 // Quick Read or Write
+#define FCH_SMB_CMD_BYTE 0x01 << 2 // Byte Read or Write
+#define FCH_SMB_CMD_BYTE_DATA 0x02 << 2 // Byte Data Read or Write
+#define FCH_SMB_CMD_WORD_DATA 0x03 << 2 // Word Data Read or Write
+#define FCH_SMB_CMD_BLOCK 0x05 << 2 // Block Read or Write
+
+#define FCH_SMB_ALL_HOST_STATUS 0x1f // HostBusy+SMBInterrupt+DeviceErr+BusCollision+Failed
+#define FCH_SMB_CMD_BYTE_DATA_START 0x48 // Byte Data Read or Write
+#define FCH_SMB_CMD_START BIT6
+#define FCH_SMB_READ_ENABLE BIT0
+#define FCH_SMB_AUTO_POLL_EN BIT0
+#define FCH_SMB_POLL2BYTE BIT7
+
+#define SBTSI_ADDR 0x98
+#define SBTSI_REG01 0x01
+#define SBTSI_REG09 0x09
+#define SBTSI_REG10 0x10
+#define SBTSI_READORDER BIT5
+
+#define FCH_EC_ENTER_CONFIG 0X5A
+#define FCH_EC_EXIT_CONFIG 0XA5
+#define FCH_EC_REG07 0X07
+#define FCH_EC_REG30 0X30
+#define FCH_EC_REG60 0X60
+#define FCH_EC_REG61 0X61
+
+#define FCH_IMC_ROMSIG 0x55aa55aaul
+
+#define SPI_HEAD_LENGTH 0x0E
+#define SPI_BAR0_VLD 0x01
+#define SPI_BASE0 (0x00 << 7)
+#define SPI_BAR1_VLD (0x01 << 8)
+#define SPI_BASE1 (SPI_HEAD_LENGTH << 10)
+#define SPI_BAR2_VLD (0x01 << 16)
+#define SPI_BASE2(x) ((SPI_HEAD_LENGTH + ACPIMMIO16(x)) << 18)
+
+#define FW_TO_SIGADDR_OFFSET 0x0C
+#define BCD_ADDR_OFFSET 0x02
+#define BCD_SIZE_OFFSET 0x04
+#define FW_ADDR_OFFSET 0x06
+#define FW_SIZE_OFFSET 0x08
+#define ACD_ADDR_OFFSET 0x0A
+#define ACD_SIZE_OFFSET 0x0C
+#define XHC_BOOT_RAM_SIZE 0x8000
+
+#define PKT_DATA_REG ACPI_MMIO_BASE + GFX_DAC_BASE + 0x00
+#define PKT_LEN_REG ACPI_MMIO_BASE + GFX_DAC_BASE + 0x14
+#define PKT_CTRL_REG ACPI_MMIO_BASE + GFX_DAC_BASE + 0x15
+#define EFUS_DAC_ADJUSTMENT_CONTROL 0x850A8ul
+#define BGADJ 0x1F
+#define DACADJ 0x1B
+#define EFUS_DAC_ADJUSTMENT_CONTROL_DATA (BGADJ + (DACADJ << 8) + BIT16 )
+
+#define KABINI_OSC_OUT_CLOCK_SEL_48MHz 0x02
+#define KABINI_OSC_OUT_CLOCK_SEL_25MHz 0x01
+
+#define RTC_WORKAROUND_SECOND 0x00
+#define RTC_VALID_SECOND_VALUE 0x59
+#define RTC_SECOND_RESET_VALUE 0x30
+#define RTC_SECOND_LOWER_NIBBLE 0x0F
+#define RTC_VALID_SECOND_VALUE_LN 0x09
+
+#ifndef FCH_DEADLOOP
+ #define FCH_DEADLOOP() { volatile UINTN __i; __i = 1; while (__i); }
+#endif
+
+#define OHCI_ARB_REGQ_VLD_EN BIT2
+
+#define HCEx40_Control 0xFED80040ul
+#define HCEx44_Input 0xFED80044ul
+#define HCEx48_Output 0xFED80048ul
+#define HCEx4C_Status 0xFED8004Cul
+#define HCEx50_IntrEn 0xFED80050ul
+#define EmulationSmiEn BIT4
+
+#define FCH_PMx08_PciControl 0xFED80308ul // PCI Control
+#define FCH_PMx08_PciControl_ShutDownOption BIT20
+
diff --git a/src/vendorcode/amd/pi/00730F01/Proc/Fch/FchPlatform.h b/src/vendorcode/amd/pi/00730F01/Proc/Fch/FchPlatform.h
new file mode 100644
index 0000000..38c4e7e
--- /dev/null
+++ b/src/vendorcode/amd/pi/00730F01/Proc/Fch/FchPlatform.h
@@ -0,0 +1,118 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * FCH platform definition
+ *
+ *
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: FCH
+ * @e \$Revision: 281178 $ @e \$Date: 2013-12-18 02:14:15 -0600 (Wed, 18 Dec 2013) $
+ *
+ */
+/*****************************************************************************
+ *
+ * Copyright (c) 2008 - 2014, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ***************************************************************************/
+
+#ifndef _FCH_PLATFORM_H_
+#define _FCH_PLATFORM_H_
+
+#define MAX_SATA_PORTS 8
+
+#include "AGESA.h"
+
+#ifndef FCHOEM_ACPI_RESTORE_SWSMI
+ #define FCHOEM_BEFORE_PCI_RESTORE_SWSMI 0xD3
+ #define FCHOEM_AFTER_PCI_RESTORE_SWSMI 0xD4
+ #define FCHOEM_ENABLE_ACPI_SWSMI 0xA0
+ #define FCHOEM_DISABLE_ACPI_SWSMI 0xA1
+ #define FCHOEM_START_TIMER_SMI 0xBC
+ #define FCHOEM_STOP_TIMER_SMI 0xBD
+#endif
+
+#ifndef FCHOEM_SPI_UNLOCK_SWSMI
+ #define FCHOEM_SPI_UNLOCK_SWSMI 0xAA
+#endif
+#ifndef FCHOEM_SPI_LOCK_SWSMI
+ #define FCHOEM_SPI_LOCK_SWSMI 0xAB
+#endif
+
+#ifndef FCHOEM_ACPI_TABLE_RANGE_LOW
+ #define FCHOEM_ACPI_TABLE_RANGE_LOW 0xE0000ul
+#endif
+
+#ifndef FCHOEM_ACPI_TABLE_RANGE_HIGH
+ #define FCHOEM_ACPI_TABLE_RANGE_HIGH 0xFFFF0ul
+#endif
+
+#ifndef FCHOEM_ACPI_BYTE_CHECHSUM
+ #define FCHOEM_ACPI_BYTE_CHECHSUM 0x100
+#endif
+
+#ifndef FCHOEM_IO_DELAY_PORT
+ #define FCHOEM_IO_DELAY_PORT 0x80
+#endif
+
+#ifndef FCHOEM_OUTPUT_DEBUG_PORT
+ #define FCHOEM_OUTPUT_DEBUG_PORT 0x80
+#endif
+
+#define FCH_PCIRST_BASE_IO 0xCF9
+#define FCH_PCI_RESET_COMMAND06 0x06
+#define FCH_PCI_RESET_COMMAND0E 0x0E
+#define FCH_KBDRST_BASE_IO 0x64
+#define FCH_KBC_RESET_COMMAND 0xFE
+#define FCH_ROMSIG_BASE_IO 0x20000l
+#define FCH_ROMSIG_SIGNATURE 0x55AA55AAul
+#define FCH_MAX_TIMER 0xFFFFFFFFul
+#define FCH_GEC_INTERNAL_REG 0x6804
+#define FCH_HPET_REG_MASK 0xFFFFF800ul
+#define FCH_FAKE_USB_BAR_ADDRESS 0x58830000ul
+
+
+#ifndef FCHOEM_ELAPSED_TIME_UNIT
+ #define FCHOEM_ELAPSED_TIME_UNIT 28
+#endif
+
+#ifndef FCHOEM_ELAPSED_TIME_DIVIDER
+ #define FCHOEM_ELAPSED_TIME_DIVIDER 100
+#endif
+
+#include "Fch.h"
+#include "amdlib.h"
+#include "FchCommonCfg.h"
+#include "AcpiLib.h"
+#include "FchDef.h"
+#include "FchBiosRamUsage.h"
+#include "AmdFch.h"
+
+extern BUILD_OPT_CFG UserOptions;
+
+#endif // _FCH_PLATFORM_H_
diff --git a/src/vendorcode/amd/pi/00730F01/binaryPI/AGESA.c b/src/vendorcode/amd/pi/00730F01/binaryPI/AGESA.c
new file mode 100644
index 0000000..b58107c
--- /dev/null
+++ b/src/vendorcode/amd/pi/00730F01/binaryPI/AGESA.c
@@ -0,0 +1,691 @@
+/* $NoKeywords:$ */
+/**
+ * @file
+ *
+ * Agesa structures and definitions
+ *
+ * Contains AMD AGESA core interface
+ *
+ * @xrefitem bom "File Content Label" "Release Content"
+ * @e project: AGESA
+ * @e sub-project: Include
+ * @e \$Revision: 85818 $ @e \$Date: 2013-01-11 17:04:21 -0600 (Fri, 11 Jan 2013) $
+ */
+/*****************************************************************************
+ *
+ * Copyright (c) 2008 - 2013, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ***************************************************************************/
+// TODO This list needs to be pruned of anything that is not API
+#include "AGESA.h"
+#include <agesawrapper.h>
+#include "FieldAccessors.h"
+#include "AcpiLib.h"
+#include "FchCommonCfg.h"
+#include "Fch.h"
+#include "FchDef.h"
+#include "amdlib.h"
+
+// TODO These need to be replaced with calls to CreateStruct()
+AGESA_STATUS
+HeapAllocateBuffer (
+ IN OUT VOID *AllocateHeapParams,
+ IN OUT VOID *StdHeader
+ );
+
+AGESA_STATUS
+HeapDeallocateBuffer (
+ IN UINT32 BufferHandle,
+ IN VOID *StdHeader
+ );
+
+CONST UINT32 ImageSignature = IMAGE_SIGNATURE;
+CONST UINT32 ModuleSignature = MODULE_SIGNATURE;
+CONST CHAR8 ModuleIdentifier[] = AGESA_ID;
+
+/************************************************************************
+ *
+ * AGESA Basic Level interface structure definition and function prototypes
+ *
+ ***********************************************************************/
+
+
+/**********************************************************************
+ * Interface call: AmdCreateStruct
+ **********************************************************************/
+AGESA_STATUS
+AmdCreateStruct (
+ IN OUT AMD_INTERFACE_PARAMS *InterfaceParams
+ )
+{
+ MODULE_ENTRY Dispatcher = NULL;
+ const AMD_MODULE_HEADER* module = agesawrapper_locate_module(ModuleIdentifier);
+ InterfaceParams->StdHeader.Func = AMD_CREATE_STRUCT;
+ if (!module) return AGESA_UNSUPPORTED;
+ Dispatcher = module->ModuleDispatcher;
+ return Dispatcher(InterfaceParams);
+}
+
+/**********************************************************************
+ * Interface call: AmdReleaseStruct
+ **********************************************************************/
+AGESA_STATUS
+AmdReleaseStruct (
+ IN OUT AMD_INTERFACE_PARAMS *InterfaceParams
+ )
+{
+ MODULE_ENTRY Dispatcher = NULL;
+ const AMD_MODULE_HEADER* module = agesawrapper_locate_module(ModuleIdentifier);
+ InterfaceParams->StdHeader.Func = AMD_RELEASE_STRUCT;
+ if (!module) return AGESA_UNSUPPORTED;
+ Dispatcher = module->ModuleDispatcher;
+ return Dispatcher(InterfaceParams);
+}
+
+/**********************************************************************
+ * Interface call: AmdInitReset
+ **********************************************************************/
+AGESA_STATUS
+AmdInitReset (
+ IN OUT AMD_RESET_PARAMS *ResetParams
+ )
+{
+ MODULE_ENTRY Dispatcher = NULL;
+ const AMD_MODULE_HEADER* module = agesawrapper_locate_module(ModuleIdentifier);
+ ResetParams->StdHeader.Func = AMD_INIT_RESET;
+ if (!module) return AGESA_UNSUPPORTED;
+ Dispatcher = module->ModuleDispatcher;
+ return Dispatcher(ResetParams);
+}
+
+/**********************************************************************
+ * Interface call: AmdInitEarly
+ **********************************************************************/
+AGESA_STATUS
+AmdInitEarly (
+ IN OUT AMD_EARLY_PARAMS *EarlyParams
+ )
+{
+ MODULE_ENTRY Dispatcher = NULL;
+ const AMD_MODULE_HEADER* module = agesawrapper_locate_module(ModuleIdentifier);
+ EarlyParams->StdHeader.Func = AMD_INIT_EARLY;
+ if (!module) return AGESA_UNSUPPORTED;
+ Dispatcher = module->ModuleDispatcher;
+ return Dispatcher(EarlyParams);
+}
+
+/**********************************************************************
+ * Interface call: AmdInitPost
+ **********************************************************************/
+AGESA_STATUS
+AmdInitPost (
+ IN OUT AMD_POST_PARAMS *PostParams ///< Amd Cpu init param
+ )
+{
+ MODULE_ENTRY Dispatcher = NULL;
+ const AMD_MODULE_HEADER* module = agesawrapper_locate_module(ModuleIdentifier);
+ PostParams->StdHeader.Func = AMD_INIT_POST;
+ if (!module) return AGESA_UNSUPPORTED;
+ Dispatcher = module->ModuleDispatcher;
+ return Dispatcher(PostParams);
+}
+
+/**********************************************************************
+ * Interface call: AmdInitEnv
+ **********************************************************************/
+AGESA_STATUS
+AmdInitEnv (
+ IN OUT AMD_ENV_PARAMS *EnvParams
+ )
+{
+ MODULE_ENTRY Dispatcher = NULL;
+ const AMD_MODULE_HEADER* module = agesawrapper_locate_module(ModuleIdentifier);
+ EnvParams->StdHeader.Func = AMD_INIT_ENV;
+ if (!module) return AGESA_UNSUPPORTED;
+ Dispatcher = module->ModuleDispatcher;
+ return Dispatcher(EnvParams);
+}
+
+/**********************************************************************
+ * Interface call: AmdInitMid
+ **********************************************************************/
+AGESA_STATUS
+AmdInitMid (
+ IN OUT AMD_MID_PARAMS *MidParams
+ )
+{
+ MODULE_ENTRY Dispatcher = NULL;
+ const AMD_MODULE_HEADER* module = agesawrapper_locate_module(ModuleIdentifier);
+ MidParams->StdHeader.Func = AMD_INIT_MID;
+ if (!module) return AGESA_UNSUPPORTED;
+ Dispatcher = module->ModuleDispatcher;
+ return Dispatcher(MidParams);
+}
+
+/**********************************************************************
+ * Interface call: AmdInitLate
+ **********************************************************************/
+AGESA_STATUS
+AmdInitLate (
+ IN OUT AMD_LATE_PARAMS *LateParams
+ )
+{
+ MODULE_ENTRY Dispatcher = NULL;
+ const AMD_MODULE_HEADER* module = agesawrapper_locate_module(ModuleIdentifier);
+ LateParams->StdHeader.Func = AMD_INIT_LATE;
+ if (!module) return AGESA_UNSUPPORTED;
+ Dispatcher = module->ModuleDispatcher;
+ return Dispatcher(LateParams);
+}
+
+/**********************************************************************
+ * Interface call: AmdInitRecovery
+ **********************************************************************/
+AGESA_STATUS
+AmdInitRecovery (
+ IN OUT AMD_RECOVERY_PARAMS *RecoveryParams
+ )
+{
+ MODULE_ENTRY Dispatcher = NULL;
+ const AMD_MODULE_HEADER* module = agesawrapper_locate_module(ModuleIdentifier);
+ RecoveryParams->StdHeader.Func = AMD_INIT_RECOVERY;
+ if (!module) return AGESA_UNSUPPORTED;
+ Dispatcher = module->ModuleDispatcher;
+ return Dispatcher(RecoveryParams);
+}
+
+/**********************************************************************
+ * Interface call: AmdInitResume
+ **********************************************************************/
+AGESA_STATUS
+AmdInitResume (
+ IN AMD_RESUME_PARAMS *ResumeParams
+ )
+{
+ MODULE_ENTRY Dispatcher = NULL;
+ const AMD_MODULE_HEADER* module = agesawrapper_locate_module(ModuleIdentifier);
+ ResumeParams->StdHeader.Func = AMD_INIT_RESUME;
+ if (!module) return AGESA_UNSUPPORTED;
+ Dispatcher = module->ModuleDispatcher;
+ return Dispatcher(ResumeParams);
+}
+
+/**********************************************************************
+ * Interface call: AmdS3LateRestore
+ **********************************************************************/
+AGESA_STATUS
+AmdS3LateRestore (
+ IN OUT AMD_S3LATE_PARAMS *S3LateParams
+ )
+{
+ MODULE_ENTRY Dispatcher = NULL;
+ const AMD_MODULE_HEADER* module = agesawrapper_locate_module(ModuleIdentifier);
+ S3LateParams->StdHeader.Func = AMD_S3LATE_RESTORE;
+ if (!module) return AGESA_UNSUPPORTED;
+ Dispatcher = module->ModuleDispatcher;
+ return Dispatcher(S3LateParams);
+}
+
+/**********************************************************************
+ * Interface call: AmdS3Save
+ **********************************************************************/
+AGESA_STATUS
+AmdS3Save (
+ IN OUT AMD_S3SAVE_PARAMS *AmdS3SaveParams
+ )
+{
+ MODULE_ENTRY Dispatcher = NULL;
+ const AMD_MODULE_HEADER* module = agesawrapper_locate_module(ModuleIdentifier);
+ AmdS3SaveParams->StdHeader.Func = AMD_S3_SAVE;
+ if (!module) return AGESA_UNSUPPORTED;
+ Dispatcher = module->ModuleDispatcher;
+ return Dispatcher(AmdS3SaveParams);
+}
+
+/**********************************************************************
+ * Interface call: AmdLateRunApTask
+ **********************************************************************/
+AGESA_STATUS
+AmdLateRunApTask (
+ IN AP_EXE_PARAMS *AmdApExeParams
+)
+{
+ MODULE_ENTRY Dispatcher = NULL;
+ const AMD_MODULE_HEADER* module = agesawrapper_locate_module(ModuleIdentifier);
+ AmdApExeParams->StdHeader.Func = AMD_LATE_RUN_AP_TASK;
+ if (!module) return AGESA_UNSUPPORTED;
+ Dispatcher = module->ModuleDispatcher;
+ return Dispatcher(AmdApExeParams);
+}
+
+/**********************************************************************
+ * Interface service call: AmdGetApicId
+ **********************************************************************/
+AGESA_STATUS
+AmdGetApicId (
+ IN OUT AMD_APIC_PARAMS *AmdParamApic
+)
+{
+ MODULE_ENTRY Dispatcher = NULL;
+ const AMD_MODULE_HEADER* module = agesawrapper_locate_module(ModuleIdentifier);
+ AmdParamApic->StdHeader.Func = AMD_GET_APIC_ID;
+ if (!module) return AGESA_UNSUPPORTED;
+ Dispatcher = module->ModuleDispatcher;
+ return Dispatcher(AmdParamApic);
+}
+
+/**********************************************************************
+ * Interface service call: AmdGetPciAddress
+ **********************************************************************/
+AGESA_STATUS
+AmdGetPciAddress (
+ IN OUT AMD_GET_PCI_PARAMS *AmdParamGetPci
+)
+{
+ MODULE_ENTRY Dispatcher = NULL;
+ const AMD_MODULE_HEADER* module = agesawrapper_locate_module(ModuleIdentifier);
+ AmdParamGetPci->StdHeader.Func = AMD_GET_PCI_ADDRESS;
+ if (!module) return AGESA_UNSUPPORTED;
+ Dispatcher = module->ModuleDispatcher;
+ return Dispatcher(AmdParamGetPci);
+}
+
+/**********************************************************************
+ * Interface service call: AmdIdentifyCore
+ **********************************************************************/
+AGESA_STATUS
+AmdIdentifyCore (
+ IN OUT AMD_IDENTIFY_PARAMS *AmdParamIdentify
+)
+{
+ MODULE_ENTRY Dispatcher = NULL;
+ const AMD_MODULE_HEADER* module = agesawrapper_locate_module(ModuleIdentifier);
+ AmdParamIdentify->StdHeader.Func = AMD_IDENTIFY_CORE;
+ if (!module) return AGESA_UNSUPPORTED;
+ Dispatcher = module->ModuleDispatcher;
+ return Dispatcher(AmdParamIdentify);
+}
+
+/**********************************************************************
+ * Interface service call: AmdReadEventLog
+ **********************************************************************/
+AGESA_STATUS
+AmdReadEventLog (
+ IN EVENT_PARAMS *Event
+)
+{
+ MODULE_ENTRY Dispatcher = NULL;
+ const AMD_MODULE_HEADER* module = agesawrapper_locate_module(ModuleIdentifier);
+ Event->StdHeader.Func = AMD_READ_EVENT_LOG;
+ if (!module) return AGESA_UNSUPPORTED;
+ Dispatcher = module->ModuleDispatcher;
+ return Dispatcher(Event);
+}
+
+/**********************************************************************
+ * Interface service call: AmdIdentifyDimm
+ **********************************************************************/
+AGESA_STATUS
+AmdIdentifyDimm (
+ IN OUT AMD_IDENTIFY_DIMM *AmdDimmIdentify
+)
+{
+ MODULE_ENTRY Dispatcher = NULL;
+ const AMD_MODULE_HEADER* module = agesawrapper_locate_module(ModuleIdentifier);
+ AmdDimmIdentify->StdHeader.Func = AMD_IDENTIFY_DIMMS;
+ if (!module) return AGESA_UNSUPPORTED;
+ Dispatcher = module->ModuleDispatcher;
+ return Dispatcher(AmdDimmIdentify);
+}
+
+AGESA_STATUS
+AmdIdsRunApTaskLate (
+ IN AP_EXE_PARAMS *AmdApExeParams
+ )
+{
+ MODULE_ENTRY Dispatcher = NULL;
+ const AMD_MODULE_HEADER* module = agesawrapper_locate_module(ModuleIdentifier);
+ AmdApExeParams->StdHeader.Func = -1;
+ return AGESA_UNSUPPORTED;
+ if (!module) return AGESA_UNSUPPORTED;
+ Dispatcher = module->ModuleDispatcher;
+ return Dispatcher(AmdApExeParams);
+}
+
+/**********************************************************************
+ * Interface service call: AmdGet2DDataEye
+ **********************************************************************/
+AGESA_STATUS
+AmdGet2DDataEye (
+ IN OUT AMD_GET_DATAEYE *AmdGetDataEye
+ )
+{
+ MODULE_ENTRY Dispatcher = NULL;
+ const AMD_MODULE_HEADER* module = agesawrapper_locate_module(ModuleIdentifier);
+ AmdGetDataEye->StdHeader.Func = AMD_GET_2D_DATA_EYE;
+ if (!module) return AGESA_UNSUPPORTED;
+ Dispatcher = module->ModuleDispatcher;
+ return Dispatcher(AmdGetDataEye);
+}
+
+/**********************************************************************
+ * FCH Functions
+ **********************************************************************/
+
+VOID FchInitS3LateRestore (IN FCH_DATA_BLOCK *FchDataPtr);
+VOID FchInitS3EarlyRestore (IN FCH_DATA_BLOCK *FchDataPtr);
+
+VOID
+FchInitS3EarlyRestore (
+ IN FCH_DATA_BLOCK *FchDataPtr
+ )
+{
+ MODULE_ENTRY Dispatcher = NULL;
+ const AMD_MODULE_HEADER* module = agesawrapper_locate_module(ModuleIdentifier);
+ FchDataPtr->StdHeader->Func = FCH_INIT_S3_EARLY_RESTORE;
+ if (!module) return;
+ Dispatcher = module->ModuleDispatcher;
+ Dispatcher(FchDataPtr);
+}
+
+VOID
+FchInitS3LateRestore (
+ IN FCH_DATA_BLOCK *FchDataPtr
+ )
+{
+ MODULE_ENTRY Dispatcher = NULL;
+ const AMD_MODULE_HEADER* module = agesawrapper_locate_module(ModuleIdentifier);
+ FchDataPtr->StdHeader->Func = FCH_INIT_S3_LATE_RESTORE;
+ if (!module) return;
+ Dispatcher = module->ModuleDispatcher;
+ Dispatcher(FchDataPtr);
+}
+
+/**
+ * WaitForEcLDN9MailboxCmdAck
+ *
+ *
+ * @param[in] StdHeader
+ *
+ */
+VOID
+WaitForEcLDN9MailboxCmdAck (
+ IN AMD_CONFIG_PARAMS *StdHeader
+ )
+{
+ MODULE_ENTRY Dispatcher = NULL;
+ const AMD_MODULE_HEADER* module = agesawrapper_locate_module(ModuleIdentifier);
+ StdHeader->Func = 0;
+ return;
+ if (!module) return;
+ Dispatcher = module->ModuleDispatcher;
+ Dispatcher(StdHeader);
+}
+
+/**
+ * ImcSleep - IMC Sleep.
+ *
+ *
+ * @param[in] FchDataPtr Fch configuration structure pointer.
+ *
+ */
+VOID
+ImcSleep (
+ IN VOID *FchDataPtr
+ )
+{
+ MODULE_ENTRY Dispatcher = NULL;
+ const AMD_MODULE_HEADER* module = agesawrapper_locate_module(ModuleIdentifier);
+ ((FCH_DATA_BLOCK*)FchDataPtr)->StdHeader->Func = 0;
+ return;
+ if (!module) return;
+ Dispatcher = module->ModuleDispatcher;
+ Dispatcher(FchDataPtr);
+}
+
+/**
+ * SoftwareDisableImc - Software disable IMC strap
+ *
+ *
+ * @param[in] FchDataPtr Fch configuration structure pointer.
+ *
+ */
+VOID
+SoftwareDisableImc (
+ IN VOID *FchDataPtr
+ )
+{
+ MODULE_ENTRY Dispatcher = NULL;
+ const AMD_MODULE_HEADER* module = agesawrapper_locate_module(ModuleIdentifier);
+ ((FCH_DATA_BLOCK*)FchDataPtr)->StdHeader->Func = 0;
+ return;
+ if (!module) return;
+ Dispatcher = module->ModuleDispatcher;
+ Dispatcher(FchDataPtr);
+}
+
+/**
+ * ImcEnableSurebootTimer - IMC Enable Sureboot Timer.
+ *
+ *
+ * @param[in] FchDataPtr Fch configuration structure pointer.
+ *
+ */
+VOID
+ImcEnableSurebootTimer (
+ IN VOID *FchDataPtr
+ )
+{
+ MODULE_ENTRY Dispatcher = NULL;
+ const AMD_MODULE_HEADER* module = agesawrapper_locate_module(ModuleIdentifier);
+ ((FCH_DATA_BLOCK*)FchDataPtr)->StdHeader->Func = 0;
+ return;
+ if (!module) return;
+ Dispatcher = module->ModuleDispatcher;
+ Dispatcher(FchDataPtr);
+}
+
+/**
+ * ImcDisableSurebootTimer - IMC Disable Sureboot Timer.
+ *
+ *
+ * @param[in] FchDataPtr Fch configuration structure pointer.
+ *
+ */
+VOID
+ImcDisableSurebootTimer (
+ IN VOID *FchDataPtr
+ )
+{
+ MODULE_ENTRY Dispatcher = NULL;
+ const AMD_MODULE_HEADER* module = agesawrapper_locate_module(ModuleIdentifier);
+ ((FCH_DATA_BLOCK*)FchDataPtr)->StdHeader->Func = 0;
+ return;
+ if (!module) return;
+ Dispatcher = module->ModuleDispatcher;
+ Dispatcher(FchDataPtr);
+}
+
+/**
+ * ImcWakeup - IMC Wakeup.
+ *
+ *
+ * @param[in] FchDataPtr Fch configuration structure pointer.
+ *
+ */
+VOID
+ImcWakeup (
+ IN VOID *FchDataPtr
+ )
+{
+ MODULE_ENTRY Dispatcher = NULL;
+ const AMD_MODULE_HEADER* module = agesawrapper_locate_module(ModuleIdentifier);
+ ((FCH_DATA_BLOCK*)FchDataPtr)->StdHeader->Func = 0;
+ return;
+ if (!module) return;
+ Dispatcher = module->ModuleDispatcher;
+ Dispatcher(FchDataPtr);
+}
+
+/**
+ * ImcIdle - IMC Idle.
+ *
+ *
+ * @param[in] FchDataPtr Fch configuration structure pointer.
+ *
+ */
+VOID
+ImcIdle (
+ IN VOID *FchDataPtr
+ )
+{
+ MODULE_ENTRY Dispatcher = NULL;
+ const AMD_MODULE_HEADER* module = agesawrapper_locate_module(ModuleIdentifier);
+ ((FCH_DATA_BLOCK*)FchDataPtr)->StdHeader->Func = 0;
+ return;
+ if (!module) return;
+ Dispatcher = module->ModuleDispatcher;
+ Dispatcher(FchDataPtr);
+}
+
+// TODO This has to be removed
+AGESA_STATUS
+HeapAllocateBuffer (
+ IN OUT VOID *AllocateHeapParams,
+ IN OUT VOID *StdHeader
+ )
+{
+ MODULE_ENTRY Dispatcher = NULL;
+ const AMD_MODULE_HEADER* module = agesawrapper_locate_module(ModuleIdentifier);
+
+ AMD_INTERFACE_PARAMS InterfaceParams = {};
+
+ if (!module) return AGESA_UNSUPPORTED;
+ Dispatcher = module->ModuleDispatcher;
+
+ InterfaceParams.StdHeader = *(AMD_CONFIG_PARAMS*)StdHeader;
+ InterfaceParams.StdHeader.Func = AMD_HEAP_ALLOCATE_BUFFER;
+
+ InterfaceParams.AllocationMethod = PreMemHeap;
+ InterfaceParams.NewStructPtr = AllocateHeapParams;
+
+ return Dispatcher(&InterfaceParams);
+}
+
+// TODO This has to be removed
+AGESA_STATUS
+HeapDeallocateBuffer (
+ IN UINT32 BufferHandle,
+ IN VOID *StdHeader
+ )
+{
+ MODULE_ENTRY Dispatcher = NULL;
+ const AMD_MODULE_HEADER* module = agesawrapper_locate_module(ModuleIdentifier);
+
+ AMD_INTERFACE_PARAMS InterfaceParams = {};
+
+ if (!module) return AGESA_UNSUPPORTED;
+ Dispatcher = module->ModuleDispatcher;
+
+ InterfaceParams.StdHeader = *(AMD_CONFIG_PARAMS*)StdHeader;
+ InterfaceParams.StdHeader.Func = AMD_HEAP_DEALLOCATE_BUFFER;
+
+ InterfaceParams.NewStructPtr = &BufferHandle;
+
+ return Dispatcher(&InterfaceParams);
+}
+
+/**********************************************************************
+ * Interface call: AmdSetValue
+ **********************************************************************/
+AGESA_STATUS
+AmdSetValue (
+ IN CONST AGESA_FIELD_NAME name,
+ IN OUT VOID* value,
+ IN UINT32 size
+ )
+{
+ AGESA_STATUS status = AGESA_UNSUPPORTED;
+
+ MODULE_ENTRY Dispatcher = NULL;
+ const AMD_MODULE_HEADER* module = agesawrapper_locate_module(ModuleIdentifier);
+
+ AMD_ACCESSOR_PARAMS AccessorParams = {};
+
+ if (!module) return status;
+ Dispatcher = module->ModuleDispatcher;
+
+ AccessorParams.StdHeader.AltImageBasePtr = 0;
+ AccessorParams.StdHeader.CalloutPtr = NULL;
+ AccessorParams.StdHeader.Func = AMD_SET_VALUE;
+ AccessorParams.StdHeader.ImageBasePtr = 0;
+
+ AccessorParams.AllocationMethod = ByHost;
+ AccessorParams.FieldName = name;
+ AccessorParams.FieldValue = value;
+ AccessorParams.FieldSize = size;
+
+ status = Dispatcher(&AccessorParams);
+ return status;
+}
+
+/**********************************************************************
+ * Interface call: AmdGetValue
+ **********************************************************************/
+AGESA_STATUS
+AmdGetValue (
+ IN CONST AGESA_FIELD_NAME name,
+ IN OUT VOID** value,
+ IN UINT32 size
+ )
+{
+ AGESA_STATUS status = AGESA_UNSUPPORTED;
+
+ MODULE_ENTRY Dispatcher = NULL;
+ const AMD_MODULE_HEADER* module = agesawrapper_locate_module(ModuleIdentifier);
+
+ AMD_ACCESSOR_PARAMS AccessorParams = {};
+
+ if (!module) return status;
+ Dispatcher = module->ModuleDispatcher;
+
+ AccessorParams.StdHeader.AltImageBasePtr = 0;
+ AccessorParams.StdHeader.CalloutPtr = NULL;
+ AccessorParams.StdHeader.Func = AMD_GET_VALUE;
+ AccessorParams.StdHeader.ImageBasePtr = 0;
+
+ AccessorParams.AllocationMethod = ByHost;
+ AccessorParams.FieldName = name;
+ AccessorParams.FieldValue = *value;
+ AccessorParams.FieldSize = size;
+
+ status = Dispatcher(&AccessorParams);
+
+ *value = AccessorParams.FieldValue;
+ size = AccessorParams.FieldSize;
+
+ return status;
+}
diff --git a/src/vendorcode/amd/pi/00730F01/binaryPI/FieldAccessors.h b/src/vendorcode/amd/pi/00730F01/binaryPI/FieldAccessors.h
new file mode 100644
index 0000000..d50e8fc
--- /dev/null
+++ b/src/vendorcode/amd/pi/00730F01/binaryPI/FieldAccessors.h
@@ -0,0 +1,111 @@
+/*****************************************************************************
+ *
+ * Copyright (c) 2014, Sage Electronic Engineering, LLC
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ***************************************************************************/
+#ifndef _FIELDACCESSORS_H_
+#define _FIELDACCESSORS_H_
+
+#include "AGESA.h"
+
+/// AGESA value name
+typedef enum {
+ AMD_GLOBAL_USER_OPTIONS = 0x00020000,
+ AMD_GLOBAL_NUM_SOCKETS = 0x00020001,
+ AMD_GLOBAL_NUM_MODULES = 0x00020002,
+} AGESA_FIELD_NAME;
+
+typedef AGESA_STATUS (*SETTER_ENTRY) (
+ IN OUT VOID* value,
+ IN UINT32 size
+ );
+
+typedef AGESA_STATUS (*GETTER_ENTRY) (
+ IN OUT VOID** value,
+ IN UINT32 size
+ );
+
+/// Accessor Interface.
+typedef struct {
+ IN AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header
+ IN AGESA_FIELD_NAME FieldName; ///< The service to init
+ IN ALLOCATION_METHOD AllocationMethod; ///< For pointers, how to allocate space for copied data
+ IN OUT VOID *Struct; ///< The struct for the service.
+ IN OUT UINT32 FieldSize; ///< The size of the data value.
+ IN OUT VOID *FieldValue; ///< The value retrieved or set into the target structure.
+} AMD_ACCESSOR_PARAMS;
+
+
+/**********************************************************************
+ * Interface call: AmdSetValue
+ **********************************************************************/
+AGESA_STATUS
+AmdGetValue (
+ IN CONST AGESA_FIELD_NAME name,
+ IN OUT VOID** value,
+ IN UINT32 size
+ );
+
+/**********************************************************************
+ * Interface call: AmdSetValue
+ **********************************************************************/
+AGESA_STATUS
+AmdSetValue (
+ IN CONST AGESA_FIELD_NAME name,
+ IN OUT VOID* value,
+ IN UINT32 size
+ );
+
+/**
+ * Dispatch Table.
+ *
+ * The push high dispatcher uses this table to find what entries are currently in the build image.
+ */
+typedef struct {
+ UINT32 FunctionId;
+ SETTER_ENTRY SetValueEntryPoint;
+ GETTER_ENTRY GetValueEntryPoint;
+} ACCESSOR_DISPATCH_TABLE;
+
+AGESA_STATUS
+GetUserOptions(
+ IN OUT VOID** value,
+ IN UINT32 size
+ );
+
+AGESA_STATUS
+GetNumSockets(
+ IN OUT VOID** value,
+ IN UINT32 size
+ );
+
+AGESA_STATUS
+GetNumModules(
+ IN OUT VOID** value,
+ IN UINT32 size
+ );
+
+#endif /* _FIELDACCESSORS_H_ */
diff --git a/src/vendorcode/amd/pi/00730F01/binaryPI/OptionsIds.h b/src/vendorcode/amd/pi/00730F01/binaryPI/OptionsIds.h
new file mode 100644
index 0000000..53bded3
--- /dev/null
+++ b/src/vendorcode/amd/pi/00730F01/binaryPI/OptionsIds.h
@@ -0,0 +1,44 @@
+/*****************************************************************************
+ *
+ * Copyright (c) 2008 - 2014, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ***************************************************************************/
+#ifndef _OPTION_IDS_H_
+#define _OPTION_IDS_H_
+
+/**
+ *
+ * These options have no effect on the host side of the binary AGESA API.
+ */
+
+#define IDSOPT_IDS_ENABLED FALSE
+//#define IDSOPT_ERROR_TRAP_ENABLED FALSE
+//#define IDSOPT_CONTROL_ENABLED FALSE
+#define IDSOPT_TRACING_ENABLED FALSE
+#define IDSOPT_TRACING_CONSOLE_SERIALPORT TRUE
+#define IDS_DEBUG_PRINT_MASK (0)
+
+#endif //_OPTION_IDS_H_
diff --git a/src/vendorcode/amd/pi/00730F01/binaryPI/gcc-intrin.h b/src/vendorcode/amd/pi/00730F01/binaryPI/gcc-intrin.h
new file mode 100644
index 0000000..a637715
--- /dev/null
+++ b/src/vendorcode/amd/pi/00730F01/binaryPI/gcc-intrin.h
@@ -0,0 +1,833 @@
+/*
+ Compatibility <intrin_x86.h> header for GCC -- GCC equivalents of intrinsic
+ Microsoft Visual C++ functions. Originally developed for the ReactOS
+ (<http://www.reactos.org/>) and TinyKrnl (<http://www.tinykrnl.org/>)
+ projects.
+
+ Copyright (c) 2006 KJK::Hyperion <hackbunny(a)reactos.com>
+ 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com>
+ 2014 Sage Electronic Engineering, LLC
+ All rights reserved.
+
+ Permission is hereby granted, free of charge, to any person obtaining a
+ copy of this software and associated documentation files (the "Software"),
+ to deal in the Software without restriction, including without limitation
+ the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ and/or sell copies of the Software, and to permit persons to whom the
+ Software is furnished to do so, subject to the following conditions:
+
+ The above copyright notice and this permission notice shall be included in
+ all copies or substantial portions of the Software.
+
+ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ DEALINGS IN THE SOFTWARE.
+*/
+
+#if defined (__GNUC__)
+
+#if !defined(AMDLIB_OPTIMIZE)
+ #define AMDLIB_OPTIMIZE
+#endif
+
+/* I/O intrin functions. */
+static
+AMDLIB_OPTIMIZE
+__inline__ __attribute__((always_inline))
+unsigned char __inbyte(unsigned short Port)
+{
+ unsigned char value;
+
+ __asm__ __volatile__ (
+ "in %1, %0"
+ : "=a" (value)
+ : "Nd" (Port)
+ );
+
+ return value;
+}
+
+static
+AMDLIB_OPTIMIZE
+__inline__ __attribute__((always_inline))
+unsigned short __inword(unsigned short Port)
+{
+ unsigned short value;
+
+ __asm__ __volatile__ (
+ "in %1, %0"
+ : "=a" (value)
+ : "Nd" (Port)
+ );
+
+ return value;
+}
+
+static
+AMDLIB_OPTIMIZE
+__inline__ __attribute__((always_inline))
+unsigned long __indword(unsigned short Port)
+{
+ unsigned long value;
+
+ __asm__ __volatile__ (
+ "in %1, %0"
+ : "=a" (value)
+ : "Nd" (Port)
+ );
+ return value;
+
+}
+
+static
+AMDLIB_OPTIMIZE
+__inline__ __attribute__((always_inline))
+void __outbyte(unsigned short Port,unsigned char Data)
+{
+ __asm__ __volatile__ (
+ "out %0, %1"
+ :
+ : "a" (Data), "Nd" (Port)
+ );
+}
+
+static
+AMDLIB_OPTIMIZE
+__inline__ __attribute__((always_inline))
+void __outword(unsigned short Port,unsigned short Data)
+{
+ __asm__ __volatile__ (
+ "out %0, %1"
+ :
+ : "a" (Data), "Nd" (Port)
+ );
+}
+
+static
+AMDLIB_OPTIMIZE
+__inline__ __attribute__((always_inline))
+void __outdword(unsigned short Port,unsigned long Data)
+{
+ __asm__ __volatile__ (
+ "out %0, %1"
+ :
+ : "a" (Data), "Nd" (Port)
+ );
+}
+
+static
+AMDLIB_OPTIMIZE
+__inline__ __attribute__((always_inline))
+void __inbytestring(unsigned short Port,unsigned char *Buffer,unsigned long Count)
+{
+ __asm__ __volatile__ (
+ "rep ; insb"
+ : "+D" (Buffer), "+c" (Count)
+ : "d"(Port)
+ );
+}
+
+static
+AMDLIB_OPTIMIZE
+__inline__ __attribute__((always_inline))
+void __inwordstring(unsigned short Port,unsigned short *Buffer,unsigned long Count)
+{
+ __asm__ __volatile__ (
+ "rep ; insw"
+ : "+D" (Buffer), "+c" (Count)
+ : "d"(Port)
+ );
+}
+
+static
+AMDLIB_OPTIMIZE
+__inline__ __attribute__((always_inline))
+void __indwordstring(unsigned short Port,unsigned long *Buffer,unsigned long Count)
+{
+ __asm__ __volatile__ (
+ "rep ; insl"
+ : "+D" (Buffer), "+c" (Count)
+ : "d"(Port)
+ );
+}
+
+static
+AMDLIB_OPTIMIZE
+__inline__ __attribute__((always_inline))
+void __outbytestring(unsigned short Port,unsigned char *Buffer,unsigned long Count)
+{
+ __asm__ __volatile__ (
+ "rep ; outsb"
+ : "+S" (Buffer), "+c" (Count)
+ : "d"(Port)
+ );
+}
+
+static
+AMDLIB_OPTIMIZE
+__inline__ __attribute__((always_inline))
+void __outwordstring(unsigned short Port,unsigned short *Buffer,unsigned long Count)
+{
+ __asm__ __volatile__ (
+ "rep ; outsw"
+ : "+S" (Buffer), "+c" (Count)
+ : "d"(Port)
+ );
+}
+
+static
+AMDLIB_OPTIMIZE
+__inline__ __attribute__((always_inline))
+void __outdwordstring(unsigned short Port,unsigned long *Buffer,unsigned long Count)
+{
+ __asm__ __volatile__ (
+ "rep ; outsl"
+ : "+S" (Buffer), "+c" (Count)
+ : "d"(Port)
+ );
+}
+
+static
+AMDLIB_OPTIMIZE
+__inline__ __attribute__((always_inline))
+unsigned long __readdr0(void)
+{
+ unsigned long value;
+ __asm__ __volatile__ (
+ "mov %%dr0, %[value]"
+ : [value] "=r" (value)
+ );
+ return value;
+}
+
+static
+AMDLIB_OPTIMIZE
+__inline__ __attribute__((always_inline))
+unsigned long __readdr1(void)
+{
+ unsigned long value;
+ __asm__ __volatile__ (
+ "mov %%dr1, %[value]"
+ : [value] "=r" (value)
+ );
+ return value;
+}
+
+static
+AMDLIB_OPTIMIZE
+__inline__ __attribute__((always_inline))
+unsigned long __readdr2(void)
+{
+ unsigned long value;
+ __asm__ __volatile__ (
+ "mov %%dr2, %[value]"
+ : [value] "=r" (value)
+ );
+ return value;
+}
+
+static
+AMDLIB_OPTIMIZE
+__inline__ __attribute__((always_inline))
+unsigned long __readdr3(void)
+{
+ unsigned long value;
+ __asm__ __volatile__ (
+ "mov %%dr3, %[value]"
+ : [value] "=r" (value)
+ );
+ return value;
+}
+
+static
+AMDLIB_OPTIMIZE
+__inline__ __attribute__((always_inline))
+unsigned long __readdr7(void)
+{
+ unsigned long value;
+ __asm__ __volatile__ (
+ "mov %%dr7, %[value]"
+ : [value] "=r" (value)
+ );
+ return value;
+}
+
+static
+AMDLIB_OPTIMIZE
+__inline__ __attribute__((always_inline))
+unsigned long __readdr(unsigned long reg)
+{
+ switch (reg){
+ case 0:
+ return __readdr0 ();
+ break;
+
+ case 1:
+ return __readdr1 ();
+ break;
+
+ case 2:
+ return __readdr2 ();
+ break;
+
+ case 3:
+ return __readdr3 ();
+ break;
+
+ case 7:
+ return __readdr7 ();
+ break;
+
+ default:
+ return -1;
+ break;
+ }
+}
+
+static
+AMDLIB_OPTIMIZE
+__inline__ __attribute__((always_inline))
+void __writedr0(unsigned long Data)
+{
+ __asm__ __volatile__ (
+ "mov %0, %%dr0"
+ :
+ : "r" (Data)
+ );
+}
+
+static
+AMDLIB_OPTIMIZE
+__inline__ __attribute__((always_inline))
+void __writedr1(unsigned long Data)
+{
+ __asm__ __volatile__ (
+ "mov %0, %%dr1"
+ :
+ : "r" (Data)
+ );
+}
+
+static
+AMDLIB_OPTIMIZE
+__inline__ __attribute__((always_inline))
+void __writedr2(unsigned long Data)
+{
+ __asm__ __volatile__ (
+ "mov %0, %%dr2"
+ :
+ : "r" (Data)
+ );
+}
+
+static
+AMDLIB_OPTIMIZE
+__inline__ __attribute__((always_inline))
+void __writedr3(unsigned long Data)
+{
+ __asm__ __volatile__ (
+ "mov %0, %%dr3"
+ :
+ : "r" (Data)
+ );
+}
+
+static
+AMDLIB_OPTIMIZE
+__inline__ __attribute__((always_inline))
+void __writedr7(unsigned long Data)
+{
+ __asm__ __volatile__ (
+ "mov %0, %%dr7"
+ :
+ : "r" (Data)
+ );
+}
+
+static
+AMDLIB_OPTIMIZE
+__inline__ __attribute__((always_inline))
+void __writedr(unsigned long reg, unsigned long Data)
+{
+ switch (reg){
+ case 0:
+ __writedr0 (Data);
+ break;
+
+ case 1:
+ __writedr1 (Data);
+ break;
+
+ case 2:
+ __writedr2 (Data);
+ break;
+
+ case 3:
+ __writedr3 (Data);
+ break;
+
+ case 7:
+ __writedr7 (Data);
+ break;
+
+ default:
+ break;
+ }
+}
+
+static
+AMDLIB_OPTIMIZE
+__inline__ __attribute__((always_inline))
+unsigned long __readcr0(void)
+{
+ unsigned long value;
+ __asm__ __volatile__ (
+ "mov %%cr0, %[value]"
+ : [value] "=r" (value));
+ return value;
+}
+
+static
+AMDLIB_OPTIMIZE
+__inline__ __attribute__((always_inline))
+unsigned long __readcr2(void)
+{
+ unsigned long value;
+ __asm__ __volatile__ (
+ "mov %%cr2, %[value]"
+ : [value] "=r" (value));
+ return value;
+}
+
+static
+AMDLIB_OPTIMIZE
+__inline__ __attribute__((always_inline))
+unsigned long __readcr3(void)
+{
+ unsigned long value;
+ __asm__ __volatile__ (
+ "mov %%cr3, %[value]"
+ : [value] "=r" (value));
+ return value;
+}
+
+static
+AMDLIB_OPTIMIZE
+__inline__ __attribute__((always_inline))
+unsigned long __readcr4(void)
+{
+ unsigned long value;
+ __asm__ __volatile__ (
+ "mov %%cr4, %[value]"
+ : [value] "=r" (value));
+ return value;
+}
+
+static
+AMDLIB_OPTIMIZE
+__inline__ __attribute__((always_inline))
+unsigned long __readcr8(void)
+{
+ unsigned long value;
+ __asm__ __volatile__ (
+ "mov %%cr8, %[value]"
+ : [value] "=r" (value));
+ return value;
+}
+
+static
+AMDLIB_OPTIMIZE
+__inline__ __attribute__((always_inline))
+unsigned long __readcr(unsigned long reg)
+{
+ switch (reg){
+ case 0:
+ return __readcr0 ();
+ break;
+
+ case 2:
+ return __readcr2 ();
+ break;
+
+ case 3:
+ return __readcr3 ();
+ break;
+
+ case 4:
+ return __readcr4 ();
+ break;
+
+ case 8:
+ return __readcr8 ();
+ break;
+
+ default:
+ return -1;
+ break;
+ }
+}
+
+static
+AMDLIB_OPTIMIZE
+__inline__ __attribute__((always_inline))
+void __writecr0(unsigned long Data)
+{
+ __asm__ __volatile__ (
+ "mov %0, %%cr0"
+ :
+ : "r" (Data)
+ : "memory"
+ );
+}
+
+static
+AMDLIB_OPTIMIZE
+__inline__ __attribute__((always_inline))
+void __writecr2(unsigned long Data)
+{
+ __asm__ __volatile__ (
+ "mov %0, %%cr2"
+ :
+ : "r" (Data)
+ );
+}
+
+static
+AMDLIB_OPTIMIZE
+__inline__ __attribute__((always_inline))
+void __writecr3(unsigned long Data)
+{
+ __asm__ __volatile__ (
+ "mov %0, %%cr3"
+ :
+ : "r" (Data)
+ );
+}
+
+static
+AMDLIB_OPTIMIZE
+__inline__ __attribute__((always_inline))
+void __writecr4(unsigned long Data)
+{
+ __asm__ __volatile__ (
+ "mov %0, %%cr4"
+ :
+ : "r" (Data)
+ );
+}
+
+static
+AMDLIB_OPTIMIZE
+__inline__ __attribute__((always_inline))
+void __writecr8(unsigned long Data)
+{
+ __asm__ __volatile__ (
+ "mov %0, %%cr8"
+ :
+ : "r" (Data)
+ );
+}
+
+static
+AMDLIB_OPTIMIZE
+__inline__ __attribute__((always_inline))
+void __writecr(unsigned long reg, unsigned long Data)
+{
+ switch (reg){
+ case 0:
+ __writecr0 (Data);
+ break;
+
+ case 2:
+ __writecr2 (Data);
+ break;
+
+ case 3:
+ __writecr3 (Data);
+ break;
+
+ case 4:
+ __writecr4 (Data);
+ break;
+
+ case 8:
+ __writecr8 (Data);
+ break;
+
+ default:
+ break;
+ }
+}
+
+static
+AMDLIB_OPTIMIZE
+__inline__ __attribute__((always_inline))
+UINT64 __readmsr(UINT32 msr)
+{
+ UINT64 retval;
+ __asm__ __volatile__(
+ "rdmsr"
+ : "=A" (retval)
+ : "c" (msr)
+ );
+ return retval;
+}
+
+static
+AMDLIB_OPTIMIZE
+__inline__ __attribute__((always_inline))
+void __writemsr (UINT32 msr, UINT64 Value)
+{
+ __asm__ __volatile__ (
+ "wrmsr"
+ :
+ : "c" (msr), "A" (Value)
+ );
+}
+
+static
+AMDLIB_OPTIMIZE
+__inline__ __attribute__((always_inline))
+UINT64 __rdtsc(void)
+{
+ UINT64 retval;
+ __asm__ __volatile__ (
+ "rdtsc"
+ : "=A" (retval));
+ return retval;
+}
+
+static
+AMDLIB_OPTIMIZE
+__inline__ __attribute__((always_inline))
+void __cpuid(int CPUInfo[], const int InfoType)
+{
+ __asm__ __volatile__(
+ "cpuid"
+ :"=a" (CPUInfo[0]), "=b" (CPUInfo[1]), "=c" (CPUInfo[2]), "=d" (CPUInfo[3])
+ : "a" (InfoType)
+ );
+}
+
+static
+AMDLIB_OPTIMIZE
+__inline__ __attribute__((always_inline))
+void _disable(void)
+{
+ __asm__ __volatile__ ("cli");
+}
+
+static
+AMDLIB_OPTIMIZE
+__inline__ __attribute__((always_inline))
+void _enable(void)
+{
+ __asm__ __volatile__ ("sti");
+}
+
+static
+AMDLIB_OPTIMIZE
+__inline__ __attribute__((always_inline))
+void __halt(void)
+{
+ __asm__ __volatile__ ("hlt");
+}
+
+static
+AMDLIB_OPTIMIZE
+__inline__ __attribute__((always_inline))
+void __debugbreak(void)
+{
+ __asm__ __volatile__ ("int3");
+}
+
+static
+AMDLIB_OPTIMIZE
+__inline__ __attribute__((always_inline))
+void __invd(void)
+{
+ __asm__ __volatile__ ("invd");
+}
+
+static
+AMDLIB_OPTIMIZE
+__inline__ __attribute__((always_inline))
+void __wbinvd(void)
+{
+ __asm__ __volatile__ ("wbinvd");
+}
+
+static
+AMDLIB_OPTIMIZE
+__inline__ __attribute__((always_inline))
+void __lidt(void *Source)
+{
+ __asm__ __volatile__("lidt %0" : : "m"(*(short*)Source));
+}
+
+static
+AMDLIB_OPTIMIZE
+__inline__ __attribute__((always_inline))
+void __writefsbyte(const unsigned long Offset, const unsigned char Data)
+{
+ __asm__ ("movb %[Data], %%fs:%a[Offset]"
+ :
+ : [Offset] "ir" (Offset), [Data] "iq" (Data));
+}
+
+static
+AMDLIB_OPTIMIZE
+__inline__ __attribute__((always_inline))
+void __writefsword(const unsigned long Offset, const unsigned short Data)
+{
+ __asm__ ("movw %[Data], %%fs:%a[Offset]"
+ :
+ : [Offset] "ir" (Offset), [Data] "ir" (Data));
+}
+
+static
+AMDLIB_OPTIMIZE
+__inline__ __attribute__((always_inline))
+void __writefsdword(const unsigned long Offset, const unsigned long Data)
+{
+ __asm__ ("movl %[Data], %%fs:%a[Offset]"
+ :
+ : [Offset] "ir" (Offset), [Data] "ir" (Data));
+}
+
+static
+AMDLIB_OPTIMIZE
+__inline__ __attribute__((always_inline))
+unsigned char __readfsbyte(const unsigned long Offset)
+{
+ unsigned char value;
+ __asm__ ("movb %%fs:%a[Offset], %[value]"
+ : [value] "=q" (value)
+ : [Offset] "ir" (Offset));
+ return value;
+}
+
+static
+AMDLIB_OPTIMIZE
+__inline__ __attribute__((always_inline))
+unsigned short __readfsword(const unsigned long Offset)
+{
+ unsigned short value;
+ __asm__ ("movw %%fs:%a[Offset], %[value]"
+ : [value] "=q" (value)
+ : [Offset] "ir" (Offset));
+ return value;
+}
+
+static
+AMDLIB_OPTIMIZE
+__inline__ __attribute__((always_inline))
+unsigned long __readfsdword(unsigned long Offset)
+{
+ unsigned long value;
+ __asm__ ("movl %%fs:%a[Offset], %[value]"
+ : [value] "=r" (value)
+ : [Offset] "ir" (Offset));
+ return value;
+}
+
+#ifdef __SSE3__
+typedef long long __v2di __attribute__ ((__vector_size__ (16)));
+typedef long long __m128i __attribute__ ((__vector_size__ (16), __may_alias__));
+
+static
+AMDLIB_OPTIMIZE
+__inline__ __attribute__((always_inline))
+void _mm_stream_si128_fs2 (void *__A, __m128i __B)
+{
+ __asm__(".byte 0x64"); // fs prefix
+ __builtin_ia32_movntdq ((__v2di *)__A, (__v2di)__B);
+}
+
+static
+AMDLIB_OPTIMIZE
+__inline__ __attribute__((always_inline))
+void _mm_stream_si128_fs (void *__A, void *__B)
+{
+ __m128i data;
+ data = (__m128i) __builtin_ia32_lddqu ((char const *)__B);
+ _mm_stream_si128_fs2 (__A, data);
+}
+
+static
+AMDLIB_OPTIMIZE
+__inline__ __attribute__((always_inline))
+void _mm_clflush_fs (void *__A)
+{
+ __asm__(".byte 0x64"); // fs prefix
+ __builtin_ia32_clflush (__A);
+}
+
+static
+AMDLIB_OPTIMIZE
+__inline__ __attribute__((always_inline))
+void _mm_mfence (void)
+{
+ __builtin_ia32_mfence ();
+}
+
+static
+AMDLIB_OPTIMIZE
+__inline__ __attribute__((always_inline))
+void _mm_sfence (void)
+{
+ __builtin_ia32_sfence ();
+}
+#endif /* __SSE3__ */
+
+static
+AMDLIB_OPTIMIZE
+__inline__ __attribute__((always_inline))
+void __stosb(unsigned char *dest, unsigned char data, size_t count)
+{
+ __asm__ __volatile__ (
+ "rep ; stosb "
+ : "+D" (dest), "+c" (count)
+ : "a"(data)
+ );
+}
+
+static
+AMDLIB_OPTIMIZE
+__inline__ __attribute__((always_inline))
+void __movsb(unsigned char *dest, unsigned char *data, size_t count)
+{
+ __asm__ __volatile__ (
+ "movsb "
+ : "+D" (dest), "+S"(data), "+c" (count)
+ );
+}
+
+static
+AMDLIB_OPTIMIZE
+__inline__ __attribute__((always_inline))
+void debug_point ( unsigned short Port, unsigned long Data )
+{
+ __outdword (Port, Data);
+ __asm__ __volatile__ (".word 0xfeeb");
+
+}
+
+static
+AMDLIB_OPTIMIZE
+__inline__ __attribute__((always_inline))
+void delay_point ( unsigned short Port, unsigned long Data, unsigned long delayTime )
+{
+ UINTN Index;
+ Index = 0;
+ __outdword (Port, Data);
+ while (Index < delayTime * 600000) {
+ __outdword (0xE0, 0);
+ Index ++;
+ }
+}
+#endif /* defined (__GNUC__) */
diff --git a/src/vendorcode/amd/pi/00730F01/binaryPI/gcccar.inc b/src/vendorcode/amd/pi/00730F01/binaryPI/gcccar.inc
new file mode 100644
index 0000000..2c51eb1
--- /dev/null
+++ b/src/vendorcode/amd/pi/00730F01/binaryPI/gcccar.inc
@@ -0,0 +1,1311 @@
+/*
+ * Copyright (c) 2012, Advanced Micro Devices, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of Advanced Micro Devices, Inc. nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/******************************************************************************
+* AMD Generic Encapsulated Software Architecture
+*
+* $Workfile:: GccCar.inc $Revision:: 32932 $
+*
+* Description: GccCar.inc - AGESA cache-as-RAM setup Include File for GCC complier
+*
+******************************************************************************/
+
+.altmacro
+
+BSP_STACK_BASE_ADDR = 0x30000 /* Base address for primary cores stack */
+BSP_STACK_SIZE = 0x10000 /* 64KB for BSP core */
+CORE0_STACK_BASE_ADDR = 0x80000 /* Base address for primary cores stack */
+CORE0_STACK_SIZE = 0x4000 /* 16KB for primary cores */
+CORE1_STACK_BASE_ADDR = 0x40000 /* Base address for AP cores */
+CORE1_STACK_SIZE = 0x1000 /* 4KB for each AP cores */
+
+APIC_BASE_ADDRESS = 0x0000001B
+ APIC_BSC = 8 /* Boot Strap Core */
+
+APIC_MSG_REG = 0x380 # Location of BSC message
+ APIC_MSG = 0x00DE00AD # Message data
+ APIC_INVD_ALL_DONE_MSG = 0x00AD00DE /* Indicate all cores have invalidated */
+APIC_CMD_LO_REG = 0x300 # APIC command low
+APIC_CMD_HI_REG = 0x310 # APIC command high
+// del CMD_REG_TO_READ_DATA = 0x00000338 # APIC command for remote read of APIC_MSG_REG
+ REMOTE_READ_STS = 0x00030000 # Remote read status mask
+ REMOTE_DELIVERY_PEND = 0x00010000 # Remote read is pending
+ REMOTE_DELIVERY_DONE = 0x00020000 # Remote read is complete
+ DELIVERY_STS_BIT = 12 #Delivery status valid bit
+APIC_ID_REG = 0x0020 # Local APIC ID offset
+ APIC20_APICID = 24
+APIC_REMOTE_READ_REG = 0x00C0 # Remote read offset
+
+# Flags can only run from bits 31 to 24. Bits 23:0 are in use.
+AMD_CU_NEED_TO_WAIT = 31
+AMD_CU_SEND_INVD_MSG = 30
+AMD_CU_RESTORE_ES = 29
+
+AMD_MTRR_VARIABLE_BASE0 = 0x0200
+AMD_MTRR_VARIABLE_BASE6 = 0x020C
+AMD_MTRR_VARIABLE_BASE7 = 0x020E
+ VMTRR_VALID = 11
+ MTRR_TYPE_WB = 0x06
+ MTRR_TYPE_WP = 0x05
+ MTRR_TYPE_WT = 0x04
+ MTRR_TYPE_UC = 0x00
+AMD_MTRR_VARIABLE_MASK7 = 0x020F
+AMD_MTRR_FIX64k_00000 = 0x0250
+AMD_MTRR_FIX16k_80000 = 0x0258
+AMD_MTRR_FIX16k_A0000 = 0x0259
+AMD_MTRR_FIX4k_C0000 = 0x0268
+AMD_MTRR_FIX4k_C8000 = 0x0269
+AMD_MTRR_FIX4k_D0000 = 0x026A
+AMD_MTRR_FIX4k_D8000 = 0x026B
+AMD_MTRR_FIX4k_E0000 = 0x026C
+AMD_MTRR_FIX4k_E8000 = 0x026D
+AMD_MTRR_FIX4k_F0000 = 0x026E
+AMD_MTRR_FIX4k_F8000 = 0x026F
+
+/* Reproduced from AGESA.h */
+AMD_AP_MTRR_FIX64k_00000 = 0x00000250
+AMD_AP_MTRR_FIX16k_80000 = 0x00000258
+AMD_AP_MTRR_FIX16k_A0000 = 0x00000259
+AMD_AP_MTRR_FIX4k_C0000 = 0x00000268
+AMD_AP_MTRR_FIX4k_C8000 = 0x00000269
+AMD_AP_MTRR_FIX4k_D0000 = 0x0000026A
+AMD_AP_MTRR_FIX4k_D8000 = 0x0000026B
+AMD_AP_MTRR_FIX4k_E0000 = 0x0000026C
+AMD_AP_MTRR_FIX4k_E8000 = 0x0000026D
+AMD_AP_MTRR_FIX4k_F0000 = 0x0000026E
+AMD_AP_MTRR_FIX4k_F8000 = 0x0000026F
+CPU_LIST_TERMINAL = 0xFFFFFFFF
+
+AMD_MTRR_DEFTYPE = 0x02FF
+ WB_DRAM_TYPE = 0x1E /* MemType - memory type */
+ MTRR_DEF_TYPE_EN = 11 /* MtrrDefTypeEn - variable and fixed MTRRs default enabled */
+ MTRR_DEF_TYPE_FIX_EN = 10 /* MtrrDefTypeEn - fixed MTRRs default enabled */
+
+HWCR = 0x0C0010015 /* Hardware Configuration */
+ INVD_WBINVD = 0x04 /* INVD to WBINVD conversion */
+
+IORR_BASE = 0x0C0010016 /* IO Range Regusters Base/Mask, 2 pairs */
+ /* uses 16h - 19h */
+TOP_MEM = 0x0C001001A /* Top of Memory */
+TOP_MEM2 = 0x0C001001D /* Top of Memory2 */
+
+LS_CFG = 0x0C0011020 /* Load-Store Configuration */
+ DIS_SS = 28 /* Family 10h,12h,15h:Disable Streng Store functionality */
+ DIS_STREAM_ST = 28 /* Family 14h:DisStreamSt - Disable Streaming Store functionality */
+
+IC_CFG = 0x0C0011021 /* Instruction Cache Config Register */
+ IC_DIS_SPEC_TLB_RLD = 9 /* Disable speculative TLB reloads */
+ DIS_IND = 14 /* Family 10-14h:Disable Indirect Branch Predictor */
+ DIS_I_CACHE = 14 /* Family 15h:DisICache - Disable Indirect Branch Predictor */
+
+DC_CFG = 0x0C0011022 /* Data Cache Configuration */
+ DC_DIS_SPEC_TLB_WALK = 4 /* Disable speculative table-walks */
+ DIS_HW_PF = 13 /* Hardware prefetches bit */
+DE_CFG = 0x0C0011029 /* Decode Configuration */
+ CL_FLUSH_SERIALIZE = 23 /* Family 12h,15h: CL Flush Serialization */
+
+BU_CFG2 = 0x0C001102A /* Family 10h: Bus Unit Configuration 2 */
+CU_CFG2 = 0x0C001102A /* Family 15h: Combined Unit Configuration 2 */
+ F10_CL_LINES_TO_NB_DIS = 15 /* ClLinesToNbDis - allows WP code to be cached in L2 */
+ IC_DIS_SPEC_TLB_WR = 35 /* IcDisSpecTlbWr - ITLB speculative writes */
+ F16_CL_LINES_TO_L2_DIS = 15 /* ClLinesToL2Dis */
+
+//del CU_CFG3 = 0x0C001102B /* Combined Unit Configuration 3 */
+//del COMBINE_CR0_CD = 49 /* Combine CR0.CD for both cores of a compute unit */
+//del L2I_CFG = 0x0C00110A0 /* L2I Configuration */
+ L2_RINSER_DIS = 20 /* L2 rinser disable */
+ PREFETCHER_DIS = 7 /* L2 prefetcher disable*/
+ CACHE_IC_ATTR_DIS = 3 /* Inserting IC attributes into the L2 disable */
+
+CR0_PE = 0 # Protection Enable
+CR0_NW = 29 # Not Write-through
+CR0_CD = 30 # Cache Disable
+CR0_PG = 31 # Paging Enable
+
+/* CPUID Functions */
+
+CPUID_MODEL = 1
+AMD_CPUID_FMF = 0x80000001 /* Family Model Features information */
+AMD_CPUID_L2Cache = 0X80000006 /* L2/L3 cache info */
+AMD_CPUID_APIC = 0x80000008 /* Long Mode and APIC info., core count */
+ APIC_ID_CORE_ID_SIZE = 12 /* ApicIdCoreIdSize bit position */
+
+NB_CFG = 0x0C001001F /* Northbridge Configuration Register */
+ INIT_APIC_ID_CPU_ID_LO = 54 /* InitApicIdCpuIdLo - is core# in high or low half of APIC ID? */
+ ENABLE_CF8_EXT_CFG = 46 /* EnableCf8ExtCfg - enable CF8 extended configuration cycles */
+
+MTRR_SYS_CFG = 0x0C0010010 /* System Configuration Register */
+ CHX_TO_DIRTY_DIS = 16 /* ChxToDirtyDis Change to dirty disable */
+ SYS_UC_LOCK_EN = 17 /* SysUcLockEn System lock command enable */
+ MTRR_FIX_DRAM_EN = 18 /* MtrrFixDramEn MTRR fixed RdDram and WrDram attributes enable */
+ MTRR_FIX_DRAM_MOD_EN = 19 /* MtrrFixDramModEn MTRR fixed RdDram and WrDram modification enable */
+ MTRR_VAR_DRAM_EN = 20 /* MtrrVarDramEn MTRR variable DRAM enable */
+ MTRR_TOM2_EN = 21 /* MtrrTom2En MTRR top of memory 2 enable */
+
+PERF_CONTROL3 = 0x0C0010003 /* Performance event control three */
+ PERF_CONTROL3_RESERVE_L = 0x00200000 /* Preserve the reserved bits */
+ PERF_CONTROL3_RESERVE_H = 0x0FCF0 /* Preserve the reserved bits */
+ CONFIG_EVENT_L = 0x0F0E2 /* All cores with level detection */
+ CONFIG_EVENT_H = 4 /* Increment count by number of event */
+ /* occured in clock cycle */
+ EVENT_ENABLE = 22 /* Enable the event */
+PERF_COUNTER3 = 0x0C0010007 /* Performance event counter three */
+
+COMPUTE_UNIT_STATUS = 0x08000C580 /* Compute Unit Status Register */
+ QUAD_CORE = 24 /* QuadCore four cores of a compute unit are enabled */
+ DUAL_CORE = 16 /* DualCore two cores of a compute unit are enabled */
+ TRIPLE_CORE = 8 /* TripleCore three cores of a compute unit are enabled */
+ CU_ENABLED = 0 /* Enabled at least one core of a compute unit is enabled */
+
+FUNC_3 = 3
+MCA_NB_CFG = 0x44 /* MCA NB Configuration */
+CPU_ERR_DIS = 6 /* CPU error response disable */
+PRODUCT_INFO_REG1 = 0x1FC /* Product Information Register 1 */
+
+# Local use flags, in upper most byte if ESI
+FLAG_UNKNOWN_FAMILY = 24 # Signals that the family# of the installed processor is not recognized
+FLAG_STACK_REENTRY = 25 # Signals that the environment has made a re-entry (2nd) call to set up the stack
+FLAG_IS_PRIMARY = 26 # Signals that this core is the primary within the comoute unit
+FLAG_CORE_NOT_IDENTIFIED = 27 # Signals that the cores/compute units of the installed processor is not recognized
+FLAG_FORCE_32K_STACK = 28 # Signals that to force 32KB stack size for BSP core
+CR0_MASK = ((1 << CR0_CD) | (1 << CR0_NW))
+MSR_MASK = ((1 << MTRR_DEF_TYPE_EN)+(1 << MTRR_DEF_TYPE_FIX_EN))
+
+/****************************************************************************
+ *
+ * CPU MACROS - PUBLIC
+ *
+ ****************************************************************************/
+.macro _WRMSR
+ .byte 0x0f, 0x30
+.endm
+
+.macro _RDMSR
+ .byte 0x0F, 0x32
+.endm
+
+.macro AMD_CPUID arg0
+ .ifb \arg0
+ mov $0x1, %eax
+ .byte 0x0F, 0x0A2 /* Execute instruction */
+ bswap %eax
+ xchg %ah, %al /* Ext model in al now */
+ rol $0x08, %eax /* Ext model in ah, model in al */
+ and $0x0FFCF, ax /* Keep 23:16, 7:6, 3:0 */
+ .else
+ mov \arg0, %eax
+ .byte 0x0F, 0x0A2
+ .endif
+.endm
+
+.macro MAKE_EXT_PCI_ADDR Seg, Bus, Dev, Func, Offset
+ mov $(1 << 31 | (Seg) << 28 | (((Offset) & (0x0F00)) >> 8) << 24 | (Bus) << 16 | (Dev) << 11 | (Func) << 8) | ((Offset) & (0xFC)), %eax
+.endm
+/****************************************************************************
+*
+* AMD_ENABLE_STACK_FAMILY_HOOK Macro - Stackless
+*
+* Set any family specific controls needed to enable the use of
+* cache as general storage before main memory is available.
+*
+* Inputs:
+* none
+* Outputs:
+* none
+ ****************************************************************************/
+.macro AMD_ENABLE_STACK_FAMILY_HOOK
+
+ AMD_ENABLE_STACK_FAMILY_HOOK_F16
+
+.endm
+
+/****************************************************************************
+*
+* AMD_DISABLE_STACK_FAMILY_HOOK Macro - Stackless
+*
+* Return any family specific controls to their 'standard'
+* settings for using cache with main memory.
+*
+* Inputs:
+* none
+* Outputs:
+* none
+ ****************************************************************************/
+.macro AMD_DISABLE_STACK_FAMILY_HOOK
+
+ AMD_DISABLE_STACK_FAMILY_HOOK_F16
+
+.endm
+
+/****************************************************************************
+*
+* GET_NODE_ID_CORE_ID Macro - Stackless
+*
+* Read family specific values to determine the node and core
+* numbers for the core executing this code.
+*
+* Inputs:
+* none
+* Outputs:
+* SI[7:0] = Core# (0..N, relative to node)
+* SI[15:8]= Node# (0..N)
+* SI[23:16]= reserved
+* SI[24]= flag: 1=Family Unrecognized
+* SI[25]= flag: 1=Interface re-entry call
+* SI[26]= flag: 1=Core is primary of compute unit
+* SI[31:27]= reserved, =0
+****************************************************************************/
+.macro GET_NODE_ID_CORE_ID
+ LOCAL node_core_exit
+
+ mov $-1, %si
+ GET_NODE_ID_CORE_ID_F16
+
+ /*
+ * Check for unrecognized Family
+ */
+ cmp $-1, %si # Has family (node/core) already been discovered?
+ jnz node_core_exit # Br if yes
+
+ mov $((1 << FLAG_UNKNOWN_FAMILY)+(1 << FLAG_IS_PRIMARY)), %esi # No, Set error code, Only let BSP continue
+
+ mov $APIC_BASE_ADDRESS, %ecx # MSR:0000_001B
+ _RDMSR
+ bt $APIC_BSC, %eax # Is this the BSC?
+ jc node_core_exit # Br if yes
+ hlt # Kill APs
+node_core_exit:
+
+.endm
+
+/*
+***************************************************************************
+ Family 16h MACROS
+***************************************************************************/
+/*--------------------------------------------------
+
+AMD_ENABLE_STACK_FAMILY_HOOK_F16 Macro - Stackless
+
+ Set any family specific controls needed to enable the use of
+ cache as general storage before main memory is available.
+
+Inputs:
+ ESI - node#, core#, flags from GET_NODE_ID_CORE_ID
+Outputs:
+ none
+Destroyed:
+ eax, ebx, ecx, edx
+
+Family 16h requirements (BKDG #48751 section 2.3.3):
+ * Paging must be disabled.
+ * MSRC001_0015[INVD_WBINVD]=0
+ * MSRC001_1020[DisSS]=1
+ * MSRC001_1021[DIS_SPEC_TLB_RLD]=1
+ * MSRC001_1022[DIS_SPEC_TLB_RLD]=1
+ * MSRC001_1022[DisHwPf]=1
+ * If MSRC001_102B[CombineCr0Cd] == 1 then MSRC001_102B[CombineCroCd] = 0
+ * No INVD or WBINVD, no exceptions, page faults or interrupts
+--------------------------------------------------
+
+ */
+
+.macro AMD_ENABLE_STACK_FAMILY_HOOK_F16
+ LOCAL fam16_enable_stack_hook_exit
+
+ AMD_CPUID $CPUID_MODEL
+ mov %eax, %ebx # Save revision info to EBX
+ shr $20, %eax # AL = cpu extended family
+ cmp $0x07, %al # Is this family 16h?
+ jnz fam16_enable_stack_hook_exit # Br if no
+
+ bt $FLAG_STACK_REENTRY , %esi # Check if stack has already been set
+ jc fam16_skipClearingBit4
+ mov $HWCR, %ecx # MSR C001_0015
+ _RDMSR
+ btr $INVD_WBINVD, %eax # disable INVD -> WBINVD conversion
+ _WRMSR
+
+fam16_skipClearingBit4:
+ mov $IC_CFG, %ecx # MSR:C001_1021
+ _RDMSR
+ bts $IC_DIS_SPEC_TLB_RLD, %eax # Turn on Disable speculative IC-TLB reloads bit
+ _WRMSR
+
+# mov %ebx, %eax # Restore revision info to EAX
+# shr $16, %eax
+# and $0x0F, %al # AL = cpu extended model
+
+ mov $DC_CFG, %ecx # MSR:C001_1022
+ _RDMSR
+ bts $DC_DIS_SPEC_TLB_WALK, %eax # Turn on Disable speculative DC-TLB reloads bit
+ bts $DIS_HW_PF, %eax # Turn on Disable hardware prefetches bit
+ _WRMSR # Remove KM in PI 1.1.0.0
+
+ mov $0x0C00110A0, %ecx # MSR:C001_10A0
+ _RDMSR
+ bts $L2_RINSER_DIS, %eax #Do not search for the repair single bit errors in the background
+ bts $PREFETCHER_DIS, %eax
+ bts $CACHE_IC_ATTR_DIS, %eax
+ _WRMSR
+
+fam16_enable_stack_hook_exit:
+.endm
+
+/*
+;
+; AMD_DISABLE_STACK_FAMILY_HOOK_F16 Macro - Stackless
+;
+; Return any family specific controls to their 'standard'
+; settings for using cache with main memory.
+;
+; Inputs:
+; ESI - [31:24] flags; [15:8]= Node#; [7:0]= core#
+; Outputs:
+; none
+; Destroyed:
+; eax, ebx, ecx, edx
+;
+; Family 16h requirements:
+; * INVD or WBINVD
+; * MSRC001_0015[INVD_WBINVD]=1
+; * MSRC001_1020[DisSS]=0
+; * MSRC001_1021[DIS_SPEC_TLB_RLD]=0
+; * MSRC001_1022[DIS_SPEC_TLB_RLD]=0
+; * MSRC001_1022[DIS_HW_PF]=0
+;---------------------------------------------------
+*/
+.macro AMD_DISABLE_STACK_FAMILY_HOOK_F16
+ LOCAL fam16_disable_stack_hook_exit
+ LOCAL fam16_disable_stack_remote_read_exit
+# LOCAL fam16_invd_done_remote_read_exit
+
+ AMD_CPUID $CPUID_MODEL
+ mov %eax, %ebx # Save revision info to EBX
+ shr $20, %eax # AL = cpu extended family
+ cmp $0x07, %al # Is this family 16h?
+ jnz fam16_disable_stack_hook_exit # Br if no
+
+ mov %ebx, %edi # Save revision info to EDI
+ AMD_CPUID $AMD_CPUID_APIC
+ mov %cl, %al # AL = number of cores - 1
+ shr $APIC_ID_CORE_ID_SIZE, %cx # CL = ApicIdCoreIdSize
+ mov $1, %bx
+ shl %cl, %bl # BL = theoretical number of cores on socket
+ dec %bx # BL = core number on socket mask
+ mov %bl, %ah # AH = core number on socket mask
+ mov %edi, %ebx # Restore revision info to EBX
+ mov %ax, %di # DI[15:8] = core number mask, DI[7:0] = number of cores - 1
+
+ and $0x0F00FF, %ebx
+ mov %ebx, %eax
+ shr $8, %eax
+ or %ax, %bx # Save Extended Model, Model and Stepping to BX
+ # [11:8] = Extended Model, [7:4] = Model, [3:0] = Stepping (bx=0000000000010100, ok)
+
+ mov $APIC_BASE_ADDRESS, %ecx
+ _RDMSR # dx=0 ax=fee00800
+ mov %bx, %dx # Save Extended Model, Model and Stepping to DX
+ shl $16, %edx #EDX[31:16] = Extended Model, Model and Stepping
+ mov %eax ,%ebx # EBX = LAPIC base
+ xor %ecx ,%ecx # Zero out CU flags
+ bts $AMD_CU_NEED_TO_WAIT, %ecx # Default to waiting
+ bts $AMD_CU_SEND_INVD_MSG, %ecx # Default to signaling
+ mov %cr0, %eax
+ bt $CR0_PE, %ax # Are we in protected mode?
+ # .if (!carry?)
+ jc 1f
+ bts $AMD_CU_RESTORE_ES, %ecx # Indicate ES restore is required
+ mov %es, %cx # Save ES segment register to CX
+ xor %ax, %ax
+ mov %ax, %es # Set ES to big real mode selector for 4GB access
+ # .endif
+
+1:
+ and $0x0F000, %bx # EBX = LAPIC base, offset 0
+ or $APIC_ID_REG, %bl #
+ mov %es:(%ebx), %eax # EAX[31:24] = APIC ID
+ shr $APIC20_APICID, %eax # AL = APIC ID
+ mov %al, %ah # AH = APIC ID
+ mov %di, %dx # DH = core mask
+ and %dh, %ah # AH = core number # ax=111 dx=01000F03
+
+ # .if (zero?)
+ jnz 1f
+ # Core 0 of a socket
+ btr $AMD_CU_SEND_INVD_MSG, %ecx # No need to signal after INVD
+ #.if (dl != 0)
+ cmp $0, %dl
+ jz 2f
+ # This socket has multiple cores
+ and $0xf000, %bx # EBX = LAPIC base, offset 0
+ or $APIC_MSG_REG, %bx
+ mov $APIC_MSG, %edi
+ mov %edi, %es:(%ebx) # Signal for non core 0s to complete CAR breakdown
+ jmp 1f
+ #.else
+2: btr $AMD_CU_NEED_TO_WAIT, %ecx # No need to wait on a single core CPU
+ #.endif
+ # .endif
+1:
+
+ bt $AMD_CU_NEED_TO_WAIT, %ecx #cx = c0000000
+ #.if (carry?)
+ jnc 1f
+ #.if (ah == dl)
+ cmp %dl, %ah
+ jnz 2f
+ # This is the highest numbered core on this socket -- wait on core 0
+ not %dh # Flip the mask to determine local core 0's APID ID
+ and %dh, %al # AL = target APIC ID # ax=310
+ jmp 3f
+2: #.else
+ # All other cores (including core 0) wait on the next highest core.
+ # In this way, cores will halt in a cascading fashion down to 0.
+ inc %al
+ #.endif
+3:
+ shl $APIC20_APICID, %eax
+ and $0x0F000, %bx
+ or $APIC_CMD_HI_REG, %bx
+ mov %eax, %es:(%ebx) # Set target APIC ID
+
+ # Use bits 23:16 as a timeout for unresponsive cores
+ ror $8, %ecx
+ mov $0xFF, %ch
+ stc
+
+ #.while (carry?)
+5: jnc 4f
+ and $0xF000, %bx #EBX = LAPIC base, offset 0
+ or $APIC_CMD_LO_REG, %bx # bx = 00000000FEE00300
+ mov $0x338, %eax
+ mov %eax, %es:(%ebx) #Fire remove read IPI
+ inc %ch #Pre increment the timeout
+ stc
+ #.while (carry?)
+7: jnc 6f
+ dec %ch #Check the timeout
+ jz fam16_disable_stack_remote_read_exit
+ mov %es:(%ebx), %eax # ax = 0000000000020338
+ bt $DELIVERY_STS_BIT, %eax
+ jmp 7b
+6: #.endw
+ stc
+ #.while (carry?)
+7: jnc 6f
+ mov %es:(%ebx), %eax
+ and $REMOTE_READ_STS, %eax
+ #.if (eax == REMOTE_DELIVERY_PEND)
+ cmp $REMOTE_DELIVERY_PEND, %eax
+ jnz 8f
+ dec %ch # Check the timeout
+ jz fam16_disable_stack_hook_exit # Branch if there is an unreponsive core
+ stc
+ jmp 9f
+8: #.else
+ clc
+9: #.endif
+ jmp 7b
+6: #.endw
+ #.if (eax == REMOTE_DELIVERY_DONE)
+ cmp $REMOTE_DELIVERY_DONE, %eax
+ jnz 6f
+ and $0x0F000, %bx #EBX = LAPIC base, offset 0
+ or $APIC_REMOTE_READ_REG, %bl
+ mov %es:(%ebx), %eax
+ #.if (eax == APIC_MSG)
+ cmp $APIC_MSG, %eax # ax=00000000FFC5BBB2
+ jnz 8f
+ clc
+ jmp 9f
+ #.else
+8: stc
+9: #.endif
+ jmp 7f
+6: #.else
+ dec %ch
+ jz fam16_disable_stack_remote_read_exit
+ stc
+7: #.endif
+ jmp 5b
+4: #.endw
+
+fam16_disable_stack_remote_read_exit:
+ rol $8, %ecx # Restore ECX
+
+1: #.endif
+
+ bt $AMD_CU_RESTORE_ES, %ecx
+ #.if (carry?)
+ jnc 1f
+ mov %cx, %es
+1:
+ mov %ecx, %edi
+ shr $16, %edx
+ mov %dx, %bx
+
+ #Handshaking complete. Continue tearing down CAR.
+
+ mov $IC_CFG, %ecx # MSR:C001_1021
+ _RDMSR
+ btr $IC_DIS_SPEC_TLB_RLD, %eax # Turn on speculative TLB reloads
+ _WRMSR
+
+ mov $DC_CFG, %ecx # MSR:C001_1022
+ _RDMSR
+ btr $DC_DIS_SPEC_TLB_WALK, %eax # Turn on speculative table-walks
+ #.if (bx != 0) # Is this rev A0?
+ #cmp $0, %bx
+ #jz 0f
+ btr $DIS_HW_PF, %eax # Turn on hardware prefetches
+ #.endif # End workaround for erratum 498
+ #0:
+ _WRMSR
+
+ mov $0x0C00110A0, %ecx #MSR:C001_10A0
+ _RDMSR
+ btr $PREFETCHER_DIS, %eax
+ btr $CACHE_IC_ATTR_DIS, %eax
+ _WRMSR
+
+ mov $BU_CFG2, %ecx
+ _RDMSR
+ btr $F16_CL_LINES_TO_L2_DIS, %eax
+ _WRMSR
+
+ mov $HWCR, %ecx # MSR:C001_0015h
+ _RDMSR
+ btr $INVD_WBINVD, %eax # Disable INVD -> WBINVD conversion
+ _WRMSR
+ wbinvd # Clear the cache tag RAMs
+ #invd
+
+ #Do Standard Family 16 work
+ mov $HWCR, %ecx # MSR:C001_0015h
+ _RDMSR
+ bts $INVD_WBINVD, %eax # Turn on Conversion of INVD to WBINVD
+ _WRMSR
+ #.endif # end
+
+ bt $AMD_CU_SEND_INVD_MSG, %edi
+ #.if (carry?)
+ jnc 1f
+ AMD_CPUID $AMD_CPUID_APIC
+ shr $APIC_ID_CORE_ID_SIZE, %cx # CL = ApicIdCoreIdSize
+ mov $1, %di
+ shl %cl, %di #DI = theoretical number of cores on socket
+ dec %di # DI = core number on socket mask
+ # Non core zero needs to signal to core 0 to proceed
+ mov $APIC_BASE_ADDRESS, %ecx
+ _RDMSR
+ mov %eax, %ebx # EBX = LAPIC base
+ and $0x0F000, %bx # EBX = LAPIC base, offset 0
+ or $APIC_MSG_REG, %bx
+ mov $APIC_MSG, %eax
+ mov %eax, %es:(%ebx) # Signal for core 0 to complete CAR breakdown
+
+ #TODO: Non core zero needs to wait for core zero to do INVD
+ #A handshake is required to ensure that all cores on a node invalidate in sync.
+ and $0x0F000, %bx
+ or $APIC_ID_REG, %bl
+ mov %es:(%ebx), %eax # EAX[31:24] = APIC ID
+ shr $APIC20_APICID, %eax # AL = APIC ID
+ mov %di, %dx # Use DL as core mask
+ not %dl
+ and %dl, %al # Remote read message from core zero
+ shl $APIC20_APICID, %eax
+
+ and $0x0F000, %bx
+ or $APIC_CMD_HI_REG, %bx
+ mov %eax, %es:(%ebx) #
+ # Use bits 23:16 as a timeout for unresponsive cores
+ ror $8, %ecx
+ mov $0xFF, %ch
+ stc
+
+ #.while (carry?)
+5: jnc 4f
+ and $0xF000, %bx #EBX = LAPIC base, offset 0
+ or $APIC_CMD_LO_REG, %bx # bx = 00000000FEE00300
+ mov $0x338, %eax
+ mov %eax, %es:(%ebx) #Fire remove read IPI
+ inc %ch #Pre increment the timeout
+ stc
+ #.while (carry?)
+7: jnc 6f
+ dec %ch #Check the timeout
+ jz fam16_invd_done_remote_read_exit
+ mov %es:(%ebx), %eax # ax = 0000000000020338
+ bt $DELIVERY_STS_BIT, %eax
+ jmp 7b
+6: #.endw
+ stc
+ #.while (carry?)
+7: jnc 6f
+ mov %es:(%ebx), %eax
+ and $REMOTE_READ_STS, %eax
+ #.if (eax == REMOTE_DELIVERY_PEND)
+ cmp $REMOTE_DELIVERY_PEND, %eax
+ jnz 8f
+ dec %ch # Check the timeout
+ jz fam16_invd_done_remote_read_exit # Branch if there is an unreponsive core
+ stc
+ jmp 9f
+8: #.else
+ clc
+9: #.endif
+ jmp 7b
+6: #.endw
+ #.if (eax == REMOTE_DELIVERY_DONE)
+ cmp $REMOTE_DELIVERY_DONE, %eax
+ jnz 6f
+ and $0x0F000, %bx #EBX = LAPIC base, offset 0
+ or $APIC_REMOTE_READ_REG, %bl
+ mov %es:(%ebx), %eax
+ #.if (eax == APIC_MSG)
+ cmp $APIC_MSG, %eax # ax=00000000FFC5BBB2
+ jnz 8f
+ clc
+ jmp 9f
+ #.else
+8: stc
+9: #.endif
+ jmp 7f
+6: #.else
+ dec %ch
+ jz fam16_invd_done_remote_read_exit
+ stc
+7: #.endif
+ jmp 5b
+4: #.endw
+
+ jmp 2f
+fam16_invd_done_remote_read_exit:
+1: #.else
+ mov $APIC_BASE_ADDRESS, %ecx
+ _RDMSR
+ mov %eax, %ebx
+ and $0x0F000, %bx
+ or $APIC_MSG_REG, %bx
+ mov $APIC_INVD_ALL_DONE_MSG, %edi
+ mov %edi, %es:(%ebx)
+2: #.endif
+
+ mov $0xc0011004, %ecx
+ _RDMSR
+ btr $30, %edx
+ _WRMSR
+
+fam16_disable_stack_hook_exit:
+.endm
+
+/*
+*/
+.macro GET_NODE_ID_CORE_ID_F16
+
+ LOCAL node_core_f16_exit
+ LOCAL node_core_f16_AP
+ LOCAL node_core_f16_shared
+ LOCAL node_core_f16_AP_not_TN
+
+#define F16_L2Size 1024
+#define F16_ShareCores 4
+#define F16_AllocMem 0
+#define F16_AllocExe 0
+#define F16_SzAddrBus 40
+#define F16_pad 0
+ cmp $-1, %si # Has node/core already been discovered?
+ jnz node_core_f16_exit # Br if yes
+
+ AMD_CPUID $CPUID_MODEL
+ shr $12, %eax # AL = cpu extended family
+ cmp $07, %ah # Is this family 16h?
+ jnz node_core_f16_exit # Br if no
+ shr $4, %al # AL = cpu extended model
+ shr $16, %ebx # BH = LocalApicId
+ mov %al, %bl # BL = cpu extended model
+
+ # LoadTableAddress(FAM16H_INFO_STRUCT)
+ # movd mm5, eax # load pointer to Family Info Struc
+
+ xor %esi, %esi # Assume BSC, clear local flags
+ mov $APIC_BASE_ADDRESS, %ecx # MSR:0000_001B
+ _RDMSR
+ bt $APIC_BSC, %eax # Is this the BSC?
+ jnc node_core_f16_AP # Br if no
+
+ # This is the BSP.
+ # Enable routing tables on BSP (just in case the HT init code has not yet enabled them)
+ mov $0x8000C06C, %eax # PCI address for D18F0x6C Link Initialization Control Register
+ mov $0x0CF8, %dx
+ out %eax, %dx
+ add $4, %dx
+ in %dx, %eax
+ btr $0, %eax # Set LinkInitializationControl[RouteTblDis] = 0
+ out %eax, %dx
+ jmp 6f #node_core_f16_shared #
+
+node_core_f16_AP:
+ mov %bl, %al # AL = cpu extended model
+ shr $8, %bx # BL = CPUID Fn0000_0001_EBX[LocalApicId]
+ #.if (al == 0)
+ cmp $3, %al # Is This ML?
+ jnz 5f
+ #.else
+4: mov %bx, %si
+ jmp 6f
+5: #node_core_f16_AP_not_KB
+ bts $FLAG_CORE_NOT_IDENTIFIED, %esi
+ #.endif
+ #.endif
+ #
+ # determine if this core shares MTRRs
+ #
+6: #node_core_f16_shared
+ mov $COMPUTE_UNIT_STATUS, %eax # Compute Unit Status
+ mov %si, %bx
+ shl $3, %bh # Move node# to PCI Dev# field
+ add %bh, %ah # Adjust for node number
+ mov $0x0CF8, %dx
+ out %eax, %dx
+ add $4, %dx
+ in %dx, %eax # [3:0]=Enabled# [19:16]=DualCore
+
+ # BL is MyCore#
+ mov $0x04, %cx # Use CH as 'first of pair' core#
+ #.while (cl > 0)
+ jmp 0f
+ 8:
+ bt $CU_ENABLED, %eax # Is pair enabled?
+ #.if (carry?) #
+ jnc 1f
+ mov $0x01, %bh # flag core as primary
+ #.break .if (ch == bl) # Does 1st match MyCore#?
+ cmp %bl, %ch
+ je 9f
+ #inc %ch
+ xor %bh, %bh # flag core as NOT primary
+ #
+ bt $DUAL_CORE, %eax
+ #.if (carry?)
+ jnc 5f
+ add $1, %eax
+ #.endif
+ 5:
+ bt $TRIPLE_CORE, %eax
+ jnc 5f
+ #.if (carry?)
+ add $2, %eax
+ #.endif
+ 5:
+ bt $QUAD_CORE, %eax
+ jnc 5f
+ #.if (carry?)
+ add $3, %eax
+ #.endif
+ 5:
+ #.break .if (ch >= bl) #TODO:
+ cmp %bl, %ch
+ jae 9f
+ inc %ch
+ #.endif
+ 1:
+ shr $1, %eax
+ dec %cl
+ 0:
+ cmp $0x0, %cl
+ ja 8b
+
+ #.endw
+ 9:
+
+ #.if (cl == 0)
+ or %cl, %cl
+ jne 1f
+ #Error - core# didn't match Compute Unit Status content
+ bts $FLAG_CORE_NOT_IDENTIFIED, %esi
+ bts $FLAG_IS_PRIMARY, %esi # Set Is_Primary for unknowns
+ #.endif
+ 1:
+ #.if (bh != 0) # Check state of primary for the matched core
+ or %bh, %bh
+ je 2f
+ bts $FLAG_IS_PRIMARY, %esi # Set shared flag into return value
+ #.endif
+ 2:
+
+node_core_f16_exit:
+
+.endm
+
+/*****************************************************************************
+* AMD_ENABLE_STACK: Setup a stack
+*
+* In:
+* EBX = Return address (preserved)
+*
+* Out:
+* SS:ESP - Our new private stack location
+*
+* EAX = AGESA_STATUS
+*
+* ECX = Stack size in bytes
+*
+* Requirements:
+* * This routine presently is limited to a max of 64 processor cores
+* Preserved:
+* ebx ebp
+* Destroyed:
+* eax, ecx, edx, edi, esi, ds, es, ss, esp
+* mmx0, mmx1
+*
+* Description:
+* Fixed MTRR address allocation to cores:
+* The BSP gets 64K of stack, Core0 of each node gets 16K of stack, all other cores get 4K.
+* There is a max of 1 BSP, 7 core0s and 56 other cores.
+* Although each core has it's own cache storage, they share the address space. Each core must
+* be assigned a private and unique address space for its stack. To support legacy systems,
+* the stack needs to be within the legacy address space (1st 1Meg). Room must also be reserved
+* for the other legacy elements (Interrupt vectors, BIOS ROM, video buffer, etc.)
+*
+* 80000h 40000h 00000h
+* +----------+----------+----------+----------+----------+----------+----------+----------+
+* 64K | | | | | | | | | 64K ea
+* ea +----------+----------+----------+----------+----------+----------+----------+----------+
+* | MTRR 0000_0250 MTRRfix64K_00000 |
+* +----------+----------+----------+----------+----------+----------+----------+----------+
+* | 7 , 6 | 5 , 4 | 3 , 2 | 1 , 0 | 0 | | | | <-node
+* |7..1,7..1 |7..1,7..1 |7..1,7..1 |7..1,7..1 | 0 | | | | <-core
+* +----------+----------+----------+----------+----------+----------+----------+----------+
+*
+* C0000h B0000h A0000h 90000h 80000h
+* +------+------+------+------+------+------+------+------+------+------+------+------+------+------+------+------+
+*16K | | | | | | | | | | | | | | | | |
+* ea +------+------+------+------+------+------+------+------+------+------+------+------+------+------+------+------+
+* | MTRR 0259 MTRRfix16K_A0000 | MTRR 0258 MTRRfix16K_80000 |
+* +------+------+------+------+------+------+------+------+------+------+------+------+------+------+------+------+
+* | > Dis|play B|uffer | < | | | | | 7 | 6 | 5 | 4 | 3 | 2 | 1 | | <-node
+* | > T| e m |p o r |a r y | B u |f f e |r A |r e a<| 0 | 0 | 0 | 0 | 0 | 0 | 0 | | <-core
+* +------+------+------+------+------+------+------+------+------+------+------+------+------+------+------+------+
+*
+* E0000h D0000h C0000h
+* +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
+* 4K | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 4K ea
+* ea +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
+* | 026B MTRRfix4K_D8000 | 026A MTRRfix4K_D0000 | 0269 MTRRfix4K_C8000 | 0268 MTRRfix4K_C0000 |
+* +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
+* | | | | | | | | | | | | | | | | | >| V| I| D| E| O| |B |I |O |S | |A |r |e |a<|
+* +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
+*
+* 100000h F0000h E0000h
+* +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
+* | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 4K ea
+* +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
+* | 026F MTRRfix4K_F8000 | 026E MTRRfix4K_F0000 | 026D MTRRfix4K_E8000 | 026C MTRRfix4K_E0000 |
+* +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
+* | >|MA|IN| B|IO|S |RA|NG|E | | | | | | |< | >|EX|TE|ND|ED| B|IO|S |ZO|NE| | | | | |< |
+* +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
+*****************************************************************************/
+.macro AMD_ENABLE_STACK
+
+# These are local labels. Declared so linker doesn't cause 'redefined label' errors
+ LOCAL SetupStack
+ LOCAL Real16bMode
+ LOCAL Protected32Mode
+ LOCAL ClearTheStack
+
+# Note that SS:ESP will be default stack. Note that this stack
+# routine will not be used after memory has been initialized. Because
+# of its limited lifetime, it will not conflict with typical PCI devices.
+ movd %ebx, %mm0 # Put return address in a safe place
+ movd %ebp, %mm1 # Save some other user registers
+
+ # get node id and core id of current executing core
+ GET_NODE_ID_CORE_ID # Sets ESI[23:16]=Shared core## SI[15,8]= Node## SI[7,0]= core# (relative to node)
+ # Note: ESI[31:24] are used for flags: Unrecognized Family, Is_Primary core, Stack already established
+
+ # determine if stack is already enabled. We are using the DefType MSR for this determination.
+ # It is =0 after reset; CAR setup sets it to enable the MTRRs
+ mov %cr0, %eax
+ test $CR0_MASK, %eax # Is cache disabled? (CD & NW bits)
+ jnz SetupStack # Jump if yes
+ mov $AMD_MTRR_DEFTYPE, %ecx # MSR:0000_02FF
+ _RDMSR
+ test $MSR_MASK, %eax # Are the default types enabled? (MTRR_DEF_TYPE_EN + MTRR_DEF_TYPE_FIX_EN)
+ jz SetupStack # Jump if no
+ or $FLAG_STACK_REENTRY, %esi # Bit25, indicate stack has already been initialized
+
+SetupStack:
+ # Set node to map the first 16MB to node 0# 0000_0000 to 00FF_FFFF as DRAM
+ mov %esi, %ebx # Get my Node/Core info
+ xor %bl, %bl
+ shl $3, %bh # Isolate my node#, match alignment for PCI Dev#
+ mov $0x8000C144, %eax # D18F1x44:DRAM Base/Limit# N is Base, N+4 is Limit
+ add %bh, %ah
+ mov %eax, %ebx # Save PCI address for Base/Limit pair
+
+ mov $0x0CF8, %dx
+ out %eax, %dx
+ add $4, %dx
+ xor %eax, %eax # Least Significant bit is AD24 so 0 sets mask of 00FF_FFFF (16MB)
+ out %eax, %dx # DRAM Limit = node0, no interleave
+
+ mov %ebx, %eax
+ sub $4, %eax # Now point to the Base register
+ mov $0x0CF8, %dx
+ out %eax, %dx
+ add $4, %dx
+ mov $0x00000003, %eax # Set the read and write enable bits
+ out %eax, %dx # DRAM Base = 0x0000, R/W
+
+ AMD_ENABLE_STACK_FAMILY_HOOK
+
+ # Init CPU MSRs for our init routines
+ mov $MTRR_SYS_CFG, %ecx # SYS_CFG
+ _RDMSR
+ bts $MTRR_FIX_DRAM_MOD_EN, %eax # Turn on modification enable bit
+ _WRMSR
+
+ mov %esi, %eax
+ bt $FLAG_STACK_REENTRY, %eax # Is this a 2nd entry?
+ #.if (!carry?) # On a re-entry, do not clear MTRRs or reset TOM; just reset the stack SS:ESP
+ jc 0f
+ bt $FLAG_IS_PRIMARY, %eax # Is this core the primary in a compute unit?
+ #.if (carry?) # Families using shared groups do not need to clear the MTRRs since that is done at power-on reset
+ # Note: Relying on MSRs to be cleared to 0's at reset for families w/shared cores
+ # Clear all variable and Fixed MTRRs for non-shared cores
+ jnc 0f
+ mov $AMD_MTRR_VARIABLE_BASE0, %ecx
+ xor %eax, %eax
+ xor %edx, %edx
+ #.while (cl != 10h) # Variable MTRRphysBase[n] and MTRRphysMask[n]
+ jmp 1f
+ 2:
+ _WRMSR
+ inc %cl
+ #.endw
+ 1:
+ cmp $0x10, %cl
+ jne 2b
+ mov $AMD_MTRR_FIX64k_00000, %cx # MSR:0000_0250
+ _WRMSR
+ mov $AMD_MTRR_FIX16k_80000, %cx # MSR:0000_0258
+ _WRMSR
+ mov $AMD_MTRR_FIX16k_A0000, %cx # MSR:0000_0259
+ _WRMSR
+ mov $AMD_MTRR_FIX4k_C0000, %cx # Fixed 4Ks: MTRRfix4K_C0000 to MTRRfix4K_F8000
+ #.while (cl != 70h)
+ jmp 3f
+ 4:
+ _WRMSR
+ inc %cl
+ #.endw
+ 3:
+ cmp $0x70, %cl
+ jne 4b
+ # Set TOP_MEM (C001_001A) for non-shared cores to 16M. This will be increased at heap init.
+ # - not strictly needed since the FixedMTRRs take presedence.
+ mov $(16 * 1024 * 1024), %eax
+ mov $TOP_MEM, %ecx # MSR:C001_001A
+ _WRMSR
+ #.endif # End Is_Primary
+ #.endif # End Stack_ReEntry
+ 0:
+ # Clear IORRs (C001_0016-19) and TOM2(C001_001D) for all cores
+ xor %eax, %eax
+ xor %edx, %edx
+ mov $IORR_BASE, %ecx # MSR:C001_0016 - 0019
+ #.while (cl != 1Ah)
+ jmp 1f
+ 2:
+ _WRMSR
+ inc %cl
+ #.endw
+ 1:
+ cmp $0x1A, %cl
+ jne 2b
+ mov $TOP_MEM2, %ecx # MSR:C001_001D
+ _WRMSR
+
+ # setup MTTRs for stacks
+ # A speculative read can be generated by a speculative fetch mis-aligned in a code zone
+ # or due to a data zone being interpreted as code. When a speculative read occurs outside a
+ # controlled region (intentionally used by software), it could cause an unwanted cache eviction.
+ # To prevent speculative reads from causing an eviction, the unused cache ranges are set
+ # to UC type. Only the actively used regions (stack, heap) are reflected in the MTRRs.
+ # Note: some core stack regions will share an MTRR since the control granularity is much
+ # larger than the allocated stack zone. The allocation algorithm must account for this 'extra'
+ # space covered by the MTRR when parseling out cache space for the various uses. In some cases
+ # this could reduce the amount of EXE cache available to a core. see cpuCacheInit.c
+ #
+ # Outcome of this block is that: (Note the MTRR map at the top of the file)
+ # ebp - start address of stack block
+ # ebx - [31:16] - MTRR MSR address
+ # - [15:8] - slot# in MTRR register
+ # - [7:0] - block size in #4K blocks
+ # review: ESI[31:24]=Flags; SI[15,8]= Node#; SI[7,0]= core# (relative to node)
+ #
+
+ mov %si, %ax # Load node, core
+ #.if (al == 0) # Is a core 0?
+ or %al, %al
+ jne 1f
+ #.if (ah == 0) # Is Node 0? (BSP)
+ or %ah, %ah
+ jne 2f
+ # Is BSP, assign a 64K stack
+ mov $((AMD_MTRR_FIX64k_00000 << 16) + (3 << 8) + (BSP_STACK_SIZE >> 12)), %ebx
+ mov $BSP_STACK_BASE_ADDR, %ebp
+ jmp 0f
+ #.else # node 1 to 7, core0
+ 2:
+ # Is a Core0 of secondary node, assign 16K stacks
+ mov $AMD_MTRR_FIX16k_80000, %bx
+ shl $16, %ebx #
+ mov %ah, %bh # Node# is used as slot#
+ mov $(CORE0_STACK_SIZE >> 12), %bl
+ mov %ah, %al # Base = (Node# * Size)#
+ mul %bl #
+ movzx %ax, %eax #
+ shl $12, %eax # Expand back to full byte count (* 4K)
+ add $CORE0_STACK_BASE_ADDR, %eax
+ mov %eax, %ebp
+ #.endif
+ jmp 0f
+ #.else #core 1 thru core 7
+ 1:
+ # Is core 1-7 of any node, assign 4K stacks
+ mov $8, %al # CoreIndex = ( (Node# * 8) ...
+ mul %ah #
+ mov %si, %bx #
+ add %bl, %al # ... + Core#)#
+
+ mov $AMD_MTRR_FIX64k_00000, %bx
+ shl $16, %ebx #
+ mov %al, %bh # Slot# = (CoreIndex / 16) + 4#
+ shr $4, %bh #
+ add $4, %bh #
+ mov $(CORE1_STACK_SIZE >> 12), %bl
+
+ mul %bl # Base = ( (CoreIndex * Size) ...
+ movzx %ax, %eax #
+ shl $12, %eax # Expand back to full byte count (* 4K)
+ add $CORE1_STACK_BASE_ADDR, %eax # ... + Base_Addr)#
+ mov %eax, %ebp
+ #.endif
+ 0:
+
+ # Now set the MTRR. Add this to already existing settings (don't clear any MTRR)
+ mov $WB_DRAM_TYPE, %edi # Load Cache type in 1st slot
+ mov %bh, %cl # ShiftCount = ((slot# ...
+ and $0x03, %cl # ... % 4) ...
+ shl $0x03, %cl # ... * 8)#
+ shl %cl, %edi # Cache type is now in correct position
+ ror $16, %ebx # Get the MTRR address
+ movzx %bx, %ecx #
+ rol $16, %ebx # Put slot# & size back in BX
+ _RDMSR # Read-modify-write the MSR
+ #.if (bh < 4) # Is value in lower or upper half of MSR?
+ cmp $4, %bh
+ jae 1f
+ or %edi, %eax #
+ jmp 0f
+ #.else
+ 1: #
+ or %edi, %edx #
+ #.endif #
+ 0:
+ _WRMSR #
+
+ # Enable MTRR defaults as UC type
+ mov $AMD_MTRR_DEFTYPE, %ecx # MSR:0000_02FF
+ _RDMSR # Read-modify-write the MSR
+ bts $MTRR_DEF_TYPE_EN, %eax # MtrrDefTypeEn
+ bts $MTRR_DEF_TYPE_FIX_EN, %eax # MtrrDefTypeFixEn
+ _WRMSR
+
+ # Close the modification window on the Fixed MTRRs
+ mov $MTRR_SYS_CFG, %ecx # MSR:0C001_0010
+ _RDMSR
+ bts $MTRR_FIX_DRAM_EN, %eax # MtrrFixDramEn
+ bts $MTRR_VAR_DRAM_EN, %eax # variable MTRR enable bit
+ btr $MTRR_FIX_DRAM_MOD_EN, %eax # Turn off modification enable bit
+ _WRMSR
+
+ # Enable caching in CR0
+ mov %cr0, %eax # Enable WT/WB cache
+ btr $CR0_PG, %eax # Make sure paging is disabled
+ btr $CR0_CD, %eax # Clear CR0 NW and CD
+ btr $CR0_NW, %eax
+ mov %eax, %cr0
+
+ # Use the Stack Base & size to calculate SS and ESP values
+ # review:
+ # esi[31:24]=Flags; esi[15,8]= Node#; esi[7,0]= core# (relative to node)
+ # ebp - start address of stack block
+ # ebx - [31:16] - MTRR MSR address
+ # - [15:8] - slot# in MTRR register
+ # - [7:0] - block size in #4K blocks
+ #
+ mov %ebp, %esp # Initialize the stack pointer
+ mov %esp, %edi # Copy the stack start to edi
+ movzx %bl, %bx
+ movzx %bx, %ebx # Clear upper ebx, don't need MSR addr anymore
+ shl $12, %ebx # Make size full byte count (* 4K)
+ add %ebx, %esp # Set the Stack Pointer as full linear address
+ sub $4, %esp
+ #
+ # review:
+ # esi[31:24]=Flags; esi[15,8]= Node#; esi[7,0]= core# (relative to node)
+ # edi - 32b start address of stack block
+ # ebx - size of stack block
+ # esp - 32b linear stack pointer
+ #
+
+ # Determine mode for SS base;
+ mov %cr0, %ecx # Check for 32-bit protect mode
+ bt $CR0_PE, %ecx #
+ #.if (!carry?) # PE=0 means real mode
+ jc Protected32Mode
+ mov %cs, %cx # PE=1
+ cmp $0x0D000, %cx # Check for CS
+ jb Protected32Mode # If CS < D000, it is a selector instead of a segment
+ # alter SS:ESP for 16b Real Mode:
+Real16bMode:
+ mov %edi, %eax
+ shr $4, %eax # Create a Real Mode segment for ss, ds, es
+ mov %ax, %ss
+ mov %ax, %ds
+ mov %ax, %es
+ shl $4, %eax
+ sub %eax, %edi # Adjust the clearing pointer for Seg:Offset mode
+ mov %ebx, %esp # Make SP an offset from SS
+ sub $4, %esp #
+ # .endif # endif
+ # #else
+ # Default is to use Protected 32b Mode
+ #.endif
+ ;
+Protected32Mode:
+ #
+ # Clear The Stack
+ # Now that we have set the location and the MTRRs, initialize the cache by
+ # reading then writing to zero all of the stack area.
+ # review:
+ # ss - Stack base
+ # esp - stack pointer
+ # ebx - size of stack block
+ # esi[31:24]=Flags; esi[15,8]= Node#; esi[7,0]= core# (relative to node)
+ # edi - address of start of stack block
+ #
+
+ClearTheStack: # Stack base is in SS, stack pointer is in ESP
+ shr $2, %ebx # ebx = stack block size in dwords
+ mov %bx, %cx #
+ # Check our flags - Don't clear an existing stack
+ #.if ( !(esi & 0FF000000h)) # Check our flags
+ test $(1 << FLAG_STACK_REENTRY), %esi
+ jne 1f
+ cld
+ mov %edi, %esi
+ rep lodsl (%esi) # Pre-load the range
+ xor %eax, %eax
+ mov %bx, %cx
+ mov %edi, %esi # Preserve base for push on stack
+ rep stosl (%edi) # Clear the range
+ movl $0x0ABCDDCBA, (%esp) # Put marker in top stack dword
+ shl $2, %ebx # Put stack size and base
+ push %ebx # in top of stack
+ push %esi
+
+ mov %ebx, %ecx # Return size of stack in bytes
+ xor %eax, %eax # eax = 0 : no error return code
+ jmp 0f
+ #.else
+ 1:
+ movzx %cx, %ecx
+ shl $2, %ecx # Return size of stack in bytes
+ mov %esi, %eax
+ shr $24, %eax # Keep the flags as part of the error report
+ or $0x40000000, %eax # eax = AGESA_WARNING (Stack has already been set up)
+ #.endif
+ 0:
+
+ movd %mm0, %ebx # Restore return address
+ movd %mm1, %ebp
+.endm
+
+/*****************************************************************************
+* AMD_DISABLE_STACK: Destroy the stack inside the cache. This routine
+* should only be executed on the BSP
+*
+* In:
+* none
+*
+* Out:
+* EAX = AGESA_SUCCESS
+*
+* Preserved:
+* ebx
+* Destroyed:
+* eax, ecx, edx, esp
+*****************************************************************************/
+.macro AMD_DISABLE_STACK
+
+ mov %ebx, %esp # Save return address
+
+ # get node/core/flags of current executing core
+ GET_NODE_ID_CORE_ID # Sets ESI[15,8]= Node#; ESI[7,0]= core# (relative to node)
+
+ # Turn on modification enable bit
+ mov $MTRR_SYS_CFG, %ecx # MSR:C001_0010
+ _RDMSR
+ bts $MTRR_FIX_DRAM_MOD_EN, %eax # Enable modifications
+ _WRMSR
+
+ # Set lower 640K MTRRs for Write-Back memory caching
+ mov $AMD_MTRR_FIX64k_00000, %ecx
+ mov $0x1E1E1E1E, %eax
+ mov %eax, %edx
+ _WRMSR # 0 - 512K = WB Mem
+ mov $AMD_MTRR_FIX16k_80000, %ecx
+ _WRMSR # 512K - 640K = WB Mem
+
+ # Turn off modification enable bit
+ mov $MTRR_SYS_CFG, %ecx # MSR:C001_0010
+ _RDMSR
+ btr $MTRR_FIX_DRAM_MOD_EN, %eax # Disable modification
+ _WRMSR
+
+ AMD_DISABLE_STACK_FAMILY_HOOK # Re-Enable 'normal' cache operations
+
+ mov %esp, %ebx
+ xor %eax, %eax
+
+.endm
+
diff --git a/src/vendorcode/amd/pi/Kconfig b/src/vendorcode/amd/pi/Kconfig
index 5919b6b..892892d 100644
--- a/src/vendorcode/amd/pi/Kconfig
+++ b/src/vendorcode/amd/pi/Kconfig
@@ -27,20 +27,20 @@
if CPU_AMD_PI_00630F01 || CPU_AMD_PI_00730F01 || CPU_AMD_PI_00660F01
-config AGESA_BINARY_PI_PATH
+config AGESA_BINARY_PI_VENDORCODE_PATH
string "AGESA PI directory path"
- default "3rdparty/blobs/pi/amd/00630F01" if CPU_AMD_PI_00630F01
- default "3rdparty/blobs/pi/amd/00730F01" if CPU_AMD_PI_00730F01
- default "3rdparty/blobs/pi/amd/00660F01" if CPU_AMD_PI_00660F01
+ default "src/vendorcode/amd/pi/00630F01" if CPU_AMD_PI_00630F01
+ default "src/vendorcode/amd/pi/00730F01" if CPU_AMD_PI_00730F01
+ default "src/vendorcode/amd/pi/00660F01" if CPU_AMD_PI_00660F01
help
- Specify where to find the AGESA headers and binary file
+ Specify where to find the AGESA header files
for AMD platform initialization.
config AGESA_BINARY_PI_FILE
string "AGESA PI binary file name"
- default "FP3/AGESA.bin" if CPU_AMD_PI_00630F01
- default "FT3b/AGESA.bin" if CPU_AMD_PI_00730F01
- default "FP4/AGESA.bin" if CPU_AMD_PI_00660F01
+ default "3rdparty/blobs/pi/amd/00630F01/FP3/AGESA.bin" if CPU_AMD_PI_00630F01
+ default "3rdparty/blobs/pi/amd/00730F01/FT3b/AGESA.bin" if CPU_AMD_PI_00730F01
+ default "3rdparty/blobs/pi/amd/00660F01/FP4/AGESA.bin" if CPU_AMD_PI_00660F01
help
Specify the binary file to use for AMD platform initialization.
diff --git a/src/vendorcode/amd/pi/Makefile.inc b/src/vendorcode/amd/pi/Makefile.inc
index 9353b82..a3d7fc1 100644
--- a/src/vendorcode/amd/pi/Makefile.inc
+++ b/src/vendorcode/amd/pi/Makefile.inc
@@ -30,7 +30,7 @@
ifeq ($(CONFIG_CPU_AMD_PI_00630F01)$(CONFIG_CPU_AMD_PI_00730F01)$(CONFIG_CPU_AMD_PI_00660F01),y)
# AGESA V5 Files
-AGESA_ROOT = $(call strip_quotes,$(src)/../$(CONFIG_AGESA_BINARY_PI_PATH))
+AGESA_ROOT = $(call strip_quotes,$(CONFIG_AGESA_BINARY_PI_VENDORCODE_PATH))
AGESA_INC = -I$(obj)
@@ -134,7 +134,7 @@ ramstage-libs += $(obj)/agesa/libagesa.a
#######################################################################
cbfs-files-$(CONFIG_CPU_AMD_AGESA_BINARY_PI) += AGESA
-AGESA-file := $(CONFIG_AGESA_BINARY_PI_PATH)/$(CONFIG_AGESA_BINARY_PI_FILE)
+AGESA-file := $(CONFIG_AGESA_BINARY_PI_FILE)
AGESA-type := raw
AGESA-position := $(CONFIG_AGESA_BINARY_PI_LOCATION)
1
0
Patch merged into coreboot/master: vendorcode: Fixup AGESA PI Kconfig variables
by gerrit＠coreboot.org 05 Aug '15
by gerrit＠coreboot.org 05 Aug '15
05 Aug '15
the following patch was just integrated into master:
commit 74234ebd7b6029ef5a3f65dbdef17784a35055c6
Author: Marc Jones <marc.jones(a)se-eng.com>
Date: Sun Jul 19 16:20:41 2015 -0600
vendorcode: Fixup AGESA PI Kconfig variables
The *_SELECTED Kconfig variables are not needed with the
options contained within "if CPU_AMD_AGESA_BINARY_PI"
introduced in e4c17ce8. It also removes the need to
source and select the default prior to selecting the
AGESA source or AGESA PI option.
Change-Id: Iffa366f575f7f155bd6c7e7ece2a985f747c83be
Signed-off-by: Marc Jones <marc.jones(a)se-eng.com>
Reviewed-on: http://review.coreboot.org/10981
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org>
See http://review.coreboot.org/10981 for details.
-gerrit
1
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Patch set updated for coreboot: vendorcode: Fixup AGESA PI Kconfig variables
by Marc Jones 05 Aug '15
by Marc Jones 05 Aug '15
05 Aug '15
Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/10981
-gerrit
commit 290799ddc81caf1405eeefab2f27d56d71f903df
Author: Marc Jones <marc.jones(a)se-eng.com>
Date: Sun Jul 19 16:20:41 2015 -0600
vendorcode: Fixup AGESA PI Kconfig variables
The *_SELECTED Kconfig variables are not needed with the
options contained within "if CPU_AMD_AGESA_BINARY_PI"
introduced in e4c17ce8. It also removes the need to
source and select the default prior to selecting the
AGESA source or AGESA PI option.
Change-Id: Iffa366f575f7f155bd6c7e7ece2a985f747c83be
Signed-off-by: Marc Jones <marc.jones(a)se-eng.com>
---
src/vendorcode/amd/Kconfig | 36 +-----------------------------------
src/vendorcode/amd/pi/Kconfig | 29 +++++++++++------------------
2 files changed, 12 insertions(+), 53 deletions(-)
diff --git a/src/vendorcode/amd/Kconfig b/src/vendorcode/amd/Kconfig
index 9720c79..3c66eaf 100644
--- a/src/vendorcode/amd/Kconfig
+++ b/src/vendorcode/amd/Kconfig
@@ -21,8 +21,6 @@ if CPU_AMD_PI
menu "AMD Platform Initialization"
-source src/vendorcode/amd/pi/Kconfig
-
choice
prompt "AGESA source"
default CPU_AMD_AGESA_BINARY_PI if CPU_AMD_PI
@@ -50,39 +48,7 @@ config CPU_AMD_AGESA_OPENSOURCE
endchoice
if CPU_AMD_AGESA_BINARY_PI
-
-config AGESA_BINARY_PI_PATH_DEFAULT_SELECTED
- bool
- default n
-
-config AGESA_BINARY_PI_PATH
- string "AGESA PI directory path"
- default AGESA_BINARY_PI_PATH_DEFAULT if AGESA_BINARY_PI_PATH_DEFAULT_SELECTED
- help
- Specify where to find the AGESA headers and binary file
- for AMD platform initialization.
-
-config AGESA_BINARY_PI_FILE_DEFAULT_SELECTED
- bool
- default n
-
-config AGESA_BINARY_PI_FILE
- string "AGESA PI binary file name"
- default AGESA_BINARY_PI_FILE_DEFAULT if AGESA_BINARY_PI_FILE_DEFAULT_SELECTED
- help
- Specify the binary file to use for AMD platform initialization.
-
-config AGESA_BINARY_PI_LOCATION_DEFAULT_SELECTED
- bool
- default n
-
-config AGESA_BINARY_PI_LOCATION
- string "AGESA PI binary address in ROM"
- default AGESA_BINARY_PI_LOCATION_DEFAULT if AGESA_BINARY_PI_FILE_DEFAULT_SELECTED
- help
- Specify the ROM address at which to store the binary Platform
- Initialization code.
-
+source src/vendorcode/amd/pi/Kconfig
endif
endmenu
diff --git a/src/vendorcode/amd/pi/Kconfig b/src/vendorcode/amd/pi/Kconfig
index 4f7a952..5919b6b 100644
--- a/src/vendorcode/amd/pi/Kconfig
+++ b/src/vendorcode/amd/pi/Kconfig
@@ -27,35 +27,28 @@
if CPU_AMD_PI_00630F01 || CPU_AMD_PI_00730F01 || CPU_AMD_PI_00660F01
-config AGESA_BINARY_PI_DEFAULTS # dummy
- def_bool y
- select AGESA_BINARY_PI_LOCATION_DEFAULT_SELECTED
- select AGESA_BINARY_PI_PATH_DEFAULT_SELECTED
- select AGESA_BINARY_PI_FILE_DEFAULT_SELECTED
-
-config AGESA_BINARY_PI_PATH_DEFAULT
- string
+config AGESA_BINARY_PI_PATH
+ string "AGESA PI directory path"
default "3rdparty/blobs/pi/amd/00630F01" if CPU_AMD_PI_00630F01
default "3rdparty/blobs/pi/amd/00730F01" if CPU_AMD_PI_00730F01
default "3rdparty/blobs/pi/amd/00660F01" if CPU_AMD_PI_00660F01
help
- The default binary file name to use for AMD platform initialization.
+ Specify where to find the AGESA headers and binary file
+ for AMD platform initialization.
-config AGESA_BINARY_PI_FILE_DEFAULT
- string
+config AGESA_BINARY_PI_FILE
+ string "AGESA PI binary file name"
default "FP3/AGESA.bin" if CPU_AMD_PI_00630F01
default "FT3b/AGESA.bin" if CPU_AMD_PI_00730F01
default "FP4/AGESA.bin" if CPU_AMD_PI_00660F01
help
- The default binary file name to use for AMD platform initialization.
+ Specify the binary file to use for AMD platform initialization.
-config AGESA_BINARY_PI_LOCATION_DEFAULT
- hex
- default 0xFFE00000 if CPU_AMD_PI_00630F01
- default 0xFFE00000 if CPU_AMD_PI_00730F01
- default 0xFFE00000 if CPU_AMD_PI_00660F01
+config AGESA_BINARY_PI_LOCATION
+ string "AGESA PI binary address in ROM"
+ default 0xFFE00000
help
- The default ROM address at which to store the binary Platform
+ Specify the ROM address at which to store the binary Platform
Initialization code.
endif
1
0
New patch to review for coreboot: buildgcc: Deal with gmp on 32bit Cygwin on 64bit host
by Zheng Bao 05 Aug '15
by Zheng Bao 05 Aug '15
05 Aug '15
Zheng Bao (zheng.bao(a)amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11123
-gerrit
commit 80c12eb3501fc1f22c570a2e7e872136a76bf065
Author: zbao <fishbaozi(a)gmail.com>
Date: Wed Aug 5 09:00:26 2015 -0400
buildgcc: Deal with gmp on 32bit Cygwin on 64bit host
Similar to what the below change says,
http://review.coreboot.org/10792
building GMP can not detect Cygwin is 32bit if the
host which Cygwin is running is actually 64bit. Let ABI=32
if that happens.
And running `uname` on Cygwin gets "CYGWIN_NT-6.1-WOW"
instead of "Cygwin". Fix the $UNAME.
Change-Id: Ic53d75defebbe902325eb07f3d8631b2a53245ef
Signed-off-by: Zheng Bao <zheng.bao(a)amd.com>
Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com>
---
util/crossgcc/buildgcc | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc
index 590e1f8..b4eb69e 100755
--- a/util/crossgcc/buildgcc
+++ b/util/crossgcc/buildgcc
@@ -94,7 +94,7 @@ cyan='\033[0;36m'
CYAN='\033[1;36m'
NC='\033[0m' # No Color
-UNAME=$(uname)
+UNAME=$(uname | grep -iq cygwin && echo Cygwin || uname);
normalize_dirs()
{
@@ -622,7 +622,7 @@ if [ $UNAME = "Darwin" ]; then
if $CC -v 2>&1 | grep -q LLVM; then
CC=llvm-gcc
fi
-elif [ $UNAME = "Linux" ]; then
+elif [ $UNAME = "Linux" -o $UNAME = "Cygwin" ]; then
# gmp is overeager with detecting 64bit CPUs even if they run
# a 32bit kernel and userland.
if [ "$(uname -m 2>/dev/null)" = "i686" ]; then
1
0
New patch to review for coreboot: northbridge/gm45/raminit.c: enable GS45 high-performance mode
by Francis Rowe 04 Aug '15
by Francis Rowe 04 Aug '15
04 Aug '15
Francis Rowe (info(a)gluglug.org.uk) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11122
-gerrit
commit 1e2112041908366ef500b6b4df28ae147a9aeb11
Author: Francis Rowe <info(a)gluglug.org.uk>
Date: Tue Aug 4 22:48:24 2015 +0100
northbridge/gm45/raminit.c: enable GS45 high-performance mode
The datasheets for GS45 describe a high- and low-performance mode
for different CPUs. Coreboot currently disables GS45 altogether,
but forcing coreboot to treat high-performance GS45 as GM45 makes
the X200S and X200 Tablet boot if it has the right CPU type.
Hardcode-enable GS45 high-performance mode in coreboot, passing it
off as GM45. This is known to work with all CPUs except the SU
(low performance) models.
Change-Id: I6c5ab4d352c049ed907c7b727e9310f290fd3aa8
Signed-off-by: Francis Rowe <info(a)gluglug.org.uk>
---
3rdparty/blobs | 2 +-
src/northbridge/intel/gm45/raminit.c | 6 +++---
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/3rdparty/blobs b/3rdparty/blobs
index 61d663e..34b0926 160000
--- a/3rdparty/blobs
+++ b/3rdparty/blobs
@@ -1 +1 @@
-Subproject commit 61d663e39bc96530900c3232ccea7365ab9dad0b
+Subproject commit 34b09265063c19ea5d61bd5a2f057b47b5aa2232
diff --git a/src/northbridge/intel/gm45/raminit.c b/src/northbridge/intel/gm45/raminit.c
index 9c4fecd..9f5aa06 100644
--- a/src/northbridge/intel/gm45/raminit.c
+++ b/src/northbridge/intel/gm45/raminit.c
@@ -108,8 +108,8 @@ void get_gmch_info(sysinfo_t *sysinfo)
printk(BIOS_SPEW, "GMCH: GS40\n");
break;
case GMCH_GS45:
- printk(BIOS_SPEW, "GMCH: GS45, using low power mode by default\n");
- sysinfo->gs45_low_power_mode = 1;
+ printk(BIOS_SPEW, "GMCH: GS45, using high performance mode by default\n");
+ sysinfo->gs45_low_power_mode = 0;
break;
case GMCH_PM45:
printk(BIOS_SPEW, "GMCH: PM45\n");
@@ -1692,7 +1692,7 @@ void raminit(sysinfo_t *const sysinfo, const int s3resume)
{
const dimminfo_t *const dimms = sysinfo->dimms;
const timings_t *const timings = &sysinfo->selected_timings;
- const int sff = sysinfo->gfx_type == GMCH_GS45;
+ const int sff = (sysinfo->gfx_type == GMCH_GS45) && (sysinfo->gs45_low_power_mode == 1);
int ch;
u8 reg8;
1
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Patch merged into coreboot/master: x86: Make sure boot device is mapped below 4G
by gerrit＠coreboot.org 04 Aug '15
by gerrit＠coreboot.org 04 Aug '15
04 Aug '15
the following patch was just integrated into master:
commit fb82ebe9065e2160e662aee490d749ac31388fa6
Author: Stefan Reinauer <reinauer(a)chromium.org>
Date: Tue Aug 4 11:14:17 2015 -0700
x86: Make sure boot device is mapped below 4G
On x86-64 the current way of calculating the base address
of the boot device (SPI flash) gets an unwanted sign extension,
making it live somewhere at the end of 64bit address space.
Enforce rom_base to be at the upper end of the 4G address space.
Change-Id: Ia81e82094d3c51f6c10e02b4b0df2f3e1519d39e
Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org>
Reviewed-on: http://review.coreboot.org/11121
Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
Tested-by: build bot (Jenkins)
See http://review.coreboot.org/11121 for details.
-gerrit
1
0