coreboot-gerrit August 2015

coreboot-gerrit@coreboot.org

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814 discussions

Patch merged into coreboot/master: abuild: Make help text into a heredoc
by gerrit＠coreboot.org 08 Aug '15

08 Aug '15

the following patch was just integrated into master: commit 86980bb46afd6576a5f6bfbdf37555fb0ce5cd08 Author: Patrick Georgi <pgeorgi(a)google.com> Date: Fri Jul 31 16:14:43 2015 +0200 abuild: Make help text into a heredoc This simplifies editing. Change-Id: Iff7f0cb7e52788836adcc0813a7bfb6d69009eed Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> Reviewed-on: http://review.coreboot.org/11091 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/11091 for details. -gerrit

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Patch merged into coreboot/master: via/nano: Move CPU microcode to 3rdparty/blobs
by gerrit＠coreboot.org 07 Aug '15

07 Aug '15

the following patch was just integrated into master: commit 8a83b8bb6ffb838e6278c4bce0f2d9798af38209 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Thu Aug 6 15:57:50 2015 -0700 via/nano: Move CPU microcode to 3rdparty/blobs Change-Id: I5da2a9fc34d2108caa2f21c0883d209b03a6b872 Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Reviewed-on: http://review.coreboot.org/11132 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> See http://review.coreboot.org/11132 for details. -gerrit

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Patch merged into coreboot/master: documentation: Add documentation for timestamp library
by gerrit＠coreboot.org 07 Aug '15

07 Aug '15

the following patch was just integrated into master: commit 567a68e9480bef3a60bdcb3814a0b586de22ae47 Author: Furquan Shaikh <furquan(a)google.com> Date: Fri Nov 14 11:57:00 2014 -0800 documentation: Add documentation for timestamp library [pg: removed discussion of timestamp internals that isn't current anymore in favor of some notes for users: when to run which function, what _not_ to do. Also moved to markdown-ish layout. Will do further style cleanups later.] BUG=chrome-os-partner:32973 BRANCH=None TEST=None Change-Id: I6ea7237f2fa749ce3a493f378f9937e642f3b678 Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 97e2a3ebd9552c2a91d9ea62be515059428631cb Original-Change-Id: I4b184ffad6fcd93d63343a9bca34ad013e9d4263 Original-Signed-off-by: Furquan Shaikh <furquan(a)google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/229861 Original-Tested-by: Furquan Shaikh <furquan(a)chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan(a)chromium.org> Reviewed-on: http://review.coreboot.org/10741 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/10741 for details. -gerrit

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Patch merged into coreboot/master: vendorcode: Move AMD sources from blobs to vendorcode
by gerrit＠coreboot.org 07 Aug '15

07 Aug '15

the following patch was just integrated into master: commit 0b11bd0d028089288e52f9f08cdcfafc9910511b Author: Marc Jones <marc.jones(a)se-eng.com> Date: Sun Jul 19 15:20:17 2015 -0600 vendorcode: Move AMD sources from blobs to vendorcode The AMD AGESA binaryPI sources were incorrectly committed to 3rdparty/blobs. Move them from blobs to vendorcode and fix Kconfig and Makefile.inc to match. Change-Id: I55a777553c1203464d7f7f4293b361fedcfa3283 Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Reviewed-on: http://review.coreboot.org/10982 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/10982 for details. -gerrit

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Patch set updated for coreboot: northbridge/gm45/raminit.c: enable GS45 high-performance mode
by Francis Rowe 07 Aug '15

07 Aug '15

Francis Rowe (info(a)gluglug.org.uk) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11135 -gerrit commit eb23edf228b666dd9d14dc97d08df05acbd00424 Author: Steve Shenton <sgsit(a)libreboot.org> Date: Fri Aug 7 08:22:27 2015 +0100 northbridge/gm45/raminit.c: enable GS45 high-performance mode The datasheets for GS45 describe a high- and low-performance mode for different CPUs. Coreboot currently disables GS45 altogether, but forcing coreboot to treat high-performance GS45 as GM45 makes the X200S and X200 Tablet boot if it has the right CPU type. Hardcode-enable GS45 high-performance mode in coreboot, passing it off as GM45. This is known to work with all CPUs except the SU (low performance) models. The low-performance models are unsupported anyway, requiring extensive work on the raminit. For now, this patch increases compatibility to a whole new chipset (GS45), depending on the CPU. Change-Id: I2719385e93c37d254ce38e0f5f486262160234e1 Signed-off-by: Steve Shenton <sgsit(a)libreboot.org> Signed-off-by: Francis Rowe <info(a)gluglug.org.uk> --- src/northbridge/intel/gm45/raminit.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/northbridge/intel/gm45/raminit.c b/src/northbridge/intel/gm45/raminit.c index 9c4fecd..9f5aa06 100644 --- a/src/northbridge/intel/gm45/raminit.c +++ b/src/northbridge/intel/gm45/raminit.c @@ -108,8 +108,8 @@ void get_gmch_info(sysinfo_t *sysinfo) printk(BIOS_SPEW, "GMCH: GS40\n"); break; case GMCH_GS45: - printk(BIOS_SPEW, "GMCH: GS45, using low power mode by default\n"); - sysinfo->gs45_low_power_mode = 1; + printk(BIOS_SPEW, "GMCH: GS45, using high performance mode by default\n"); + sysinfo->gs45_low_power_mode = 0; break; case GMCH_PM45: printk(BIOS_SPEW, "GMCH: PM45\n"); @@ -1692,7 +1692,7 @@ void raminit(sysinfo_t *const sysinfo, const int s3resume) { const dimminfo_t *const dimms = sysinfo->dimms; const timings_t *const timings = &sysinfo->selected_timings; - const int sff = sysinfo->gfx_type == GMCH_GS45; + const int sff = (sysinfo->gfx_type == GMCH_GS45) && (sysinfo->gs45_low_power_mode == 1); int ch; u8 reg8;

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New patch to review for coreboot: northbridge/gm45/raminit.c: enable GS45 high-performance mode
by Francis Rowe 07 Aug '15

07 Aug '15

Francis Rowe (info(a)gluglug.org.uk) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11135 -gerrit commit 84d9adff2bbe80c03bb1eb3323a23d92f7fb8de1 Author: Steve Shenton <sgsit(a)libreboot.org> Date: Fri Aug 7 08:22:27 2015 +0100 northbridge/gm45/raminit.c: enable GS45 high-performance mode The datasheets for GS45 describe a high- and low-performance mode for different CPUs. Coreboot currently disables GS45 altogether, but forcing coreboot to treat high-performance GS45 as GM45 makes the X200S and X200 Tablet boot if it has the right CPU type. Hardcode-enable GS45 high-performance mode in coreboot, passing it off as GM45. This is known to work with all CPUs except the SU (low performance) models. Change-Id: I2719385e93c37d254ce38e0f5f486262160234e1 Signed-off-by: Steve Shenton <sgsit(a)libreboot.org> Signed-off-by: Francis Rowe <info(a)gluglug.org.uk> --- src/northbridge/intel/gm45/raminit.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/northbridge/intel/gm45/raminit.c b/src/northbridge/intel/gm45/raminit.c index 9c4fecd..9f5aa06 100644 --- a/src/northbridge/intel/gm45/raminit.c +++ b/src/northbridge/intel/gm45/raminit.c @@ -108,8 +108,8 @@ void get_gmch_info(sysinfo_t *sysinfo) printk(BIOS_SPEW, "GMCH: GS40\n"); break; case GMCH_GS45: - printk(BIOS_SPEW, "GMCH: GS45, using low power mode by default\n"); - sysinfo->gs45_low_power_mode = 1; + printk(BIOS_SPEW, "GMCH: GS45, using high performance mode by default\n"); + sysinfo->gs45_low_power_mode = 0; break; case GMCH_PM45: printk(BIOS_SPEW, "GMCH: PM45\n"); @@ -1692,7 +1692,7 @@ void raminit(sysinfo_t *const sysinfo, const int s3resume) { const dimminfo_t *const dimms = sysinfo->dimms; const timings_t *const timings = &sysinfo->selected_timings; - const int sff = sysinfo->gfx_type == GMCH_GS45; + const int sff = (sysinfo->gfx_type == GMCH_GS45) && (sysinfo->gs45_low_power_mode == 1); int ch; u8 reg8;

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Patch merged into coreboot/master: amd/model_fxx: Move CPU microcode to 3rdparty/blobs
by gerrit＠coreboot.org 07 Aug '15

07 Aug '15

the following patch was just integrated into master: commit 9b9400dc90906fddadc0303994422ec011a8f6e7 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Thu Aug 6 15:56:40 2015 -0700 amd/model_fxx: Move CPU microcode to 3rdparty/blobs Change-Id: I1a772be9d72aa6d6552f5ba21c20b28e400677e9 Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Reviewed-on: http://review.coreboot.org/11131 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> See http://review.coreboot.org/11131 for details. -gerrit

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Patch merged into coreboot/master: amd/model_10xxx: Move CPU microcode to 3rdparty/blobs
by gerrit＠coreboot.org 07 Aug '15

07 Aug '15

the following patch was just integrated into master: commit 916e4085262461a362e7329e0d888b986dc77cc6 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Thu Aug 6 15:46:32 2015 -0700 amd/model_10xxx: Move CPU microcode to 3rdparty/blobs Change-Id: Ib053bdec185eca2b45c95bec713cf0fb6d16c0bc Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Reviewed-on: http://review.coreboot.org/11130 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> See http://review.coreboot.org/11130 for details. -gerrit

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Patch merged into coreboot/master: Move blobs marker forward
by gerrit＠coreboot.org 07 Aug '15

07 Aug '15

the following patch was just integrated into master: commit e07e0441c282f376af6efa3349a31e28faa04ec7 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Thu Aug 6 16:00:02 2015 -0700 Move blobs marker forward b4ade40 via/nano: Move CPU microcode to 3rdparty/blobs 8921cc4 amd/model_fxx: Move CPU microcode to 3rdparty/blobs 1099605 amd/model_10xxx: Move CPU microcode to 3rdparty/blobs 5f5604e Convert microcode to binary Change-Id: I276537281a01f8497ed87108e66574ec45265f3a Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Reviewed-on: http://review.coreboot.org/11129 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> See http://review.coreboot.org/11129 for details. -gerrit

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New patch to review for coreboot: secimage: Use libz's crc32 function
by Stefan Reinauer 07 Aug '15

07 Aug '15

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11134 -gerrit commit 02578e2e8462c13ffcb18b3025c156299c6fe8d5 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Thu Aug 6 16:57:48 2015 -0700 secimage: Use libz's crc32 function This is to trick libreboot into not deleting misc.c when checking out coreboot. Change-Id: I8f0bb5cb3eb5681f99c616ae03de126efab852a9 Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- util/broadcom/secimage/Makefile | 2 +- util/broadcom/secimage/Makefile.inc | 2 +- util/broadcom/secimage/misc.c | 56 ------------------------------------- util/broadcom/secimage/sbi.c | 3 +- util/broadcom/secimage/secimage.h | 1 - 5 files changed, 4 insertions(+), 60 deletions(-) diff --git a/util/broadcom/secimage/Makefile b/util/broadcom/secimage/Makefile index 58f3bc1..9dd1396 100644 --- a/util/broadcom/secimage/Makefile +++ b/util/broadcom/secimage/Makefile @@ -17,7 +17,7 @@ CC = gcc RM = rm CFLAGS += -Wall -g -LIBS = -lssl -lcrypto +LIBS = -lssl -lcrypto -lz %.o : %.c $(CC) -c $(CFLAGS) -o $@ $< diff --git a/util/broadcom/secimage/Makefile.inc b/util/broadcom/secimage/Makefile.inc index a171a42..fefe576 100644 --- a/util/broadcom/secimage/Makefile.inc +++ b/util/broadcom/secimage/Makefile.inc @@ -4,7 +4,7 @@ secimageobj += io.o secimageobj += misc.o secimageobj += sbi.o -LIBS = -lssl -lcrypto +LIBS = -lssl -lcrypto -lz additional-dirs += $(objutil)/broadcom/secimage diff --git a/util/broadcom/secimage/misc.c b/util/broadcom/secimage/misc.c index e793ffc..a64c448 100644 --- a/util/broadcom/secimage/misc.c +++ b/util/broadcom/secimage/misc.c @@ -54,59 +54,3 @@ void FillHeaderFromConfigFile(char *h, char *ConfigFileName) } } } - -static const uint32_t crc32_table[256] = { - 0x00000000, 0x77073096, 0xee0e612c, 0x990951ba, 0x076dc419, 0x706af48f, - 0xe963a535, 0x9e6495a3, 0x0edb8832, 0x79dcb8a4, 0xe0d5e91e, 0x97d2d988, - 0x09b64c2b, 0x7eb17cbd, 0xe7b82d07, 0x90bf1d91, 0x1db71064, 0x6ab020f2, - 0xf3b97148, 0x84be41de, 0x1adad47d, 0x6ddde4eb, 0xf4d4b551, 0x83d385c7, - 0x136c9856, 0x646ba8c0, 0xfd62f97a, 0x8a65c9ec, 0x14015c4f, 0x63066cd9, - 0xfa0f3d63, 0x8d080df5, 0x3b6e20c8, 0x4c69105e, 0xd56041e4, 0xa2677172, - 0x3c03e4d1, 0x4b04d447, 0xd20d85fd, 0xa50ab56b, 0x35b5a8fa, 0x42b2986c, - 0xdbbbc9d6, 0xacbcf940, 0x32d86ce3, 0x45df5c75, 0xdcd60dcf, 0xabd13d59, - 0x26d930ac, 0x51de003a, 0xc8d75180, 0xbfd06116, 0x21b4f4b5, 0x56b3c423, - 0xcfba9599, 0xb8bda50f, 0x2802b89e, 0x5f058808, 0xc60cd9b2, 0xb10be924, - 0x2f6f7c87, 0x58684c11, 0xc1611dab, 0xb6662d3d, 0x76dc4190, 0x01db7106, - 0x98d220bc, 0xefd5102a, 0x71b18589, 0x06b6b51f, 0x9fbfe4a5, 0xe8b8d433, - 0x7807c9a2, 0x0f00f934, 0x9609a88e, 0xe10e9818, 0x7f6a0dbb, 0x086d3d2d, - 0x91646c97, 0xe6635c01, 0x6b6b51f4, 0x1c6c6162, 0x856530d8, 0xf262004e, - 0x6c0695ed, 0x1b01a57b, 0x8208f4c1, 0xf50fc457, 0x65b0d9c6, 0x12b7e950, - 0x8bbeb8ea, 0xfcb9887c, 0x62dd1ddf, 0x15da2d49, 0x8cd37cf3, 0xfbd44c65, - 0x4db26158, 0x3ab551ce, 0xa3bc0074, 0xd4bb30e2, 0x4adfa541, 0x3dd895d7, - 0xa4d1c46d, 0xd3d6f4fb, 0x4369e96a, 0x346ed9fc, 0xad678846, 0xda60b8d0, - 0x44042d73, 0x33031de5, 0xaa0a4c5f, 0xdd0d7cc9, 0x5005713c, 0x270241aa, - 0xbe0b1010, 0xc90c2086, 0x5768b525, 0x206f85b3, 0xb966d409, 0xce61e49f, - 0x5edef90e, 0x29d9c998, 0xb0d09822, 0xc7d7a8b4, 0x59b33d17, 0x2eb40d81, - 0xb7bd5c3b, 0xc0ba6cad, 0xedb88320, 0x9abfb3b6, 0x03b6e20c, 0x74b1d29a, - 0xead54739, 0x9dd277af, 0x04db2615, 0x73dc1683, 0xe3630b12, 0x94643b84, - 0x0d6d6a3e, 0x7a6a5aa8, 0xe40ecf0b, 0x9309ff9d, 0x0a00ae27, 0x7d079eb1, - 0xf00f9344, 0x8708a3d2, 0x1e01f268, 0x6906c2fe, 0xf762575d, 0x806567cb, - 0x196c3671, 0x6e6b06e7, 0xfed41b76, 0x89d32be0, 0x10da7a5a, 0x67dd4acc, - 0xf9b9df6f, 0x8ebeeff9, 0x17b7be43, 0x60b08ed5, 0xd6d6a3e8, 0xa1d1937e, - 0x38d8c2c4, 0x4fdff252, 0xd1bb67f1, 0xa6bc5767, 0x3fb506dd, 0x48b2364b, - 0xd80d2bda, 0xaf0a1b4c, 0x36034af6, 0x41047a60, 0xdf60efc3, 0xa867df55, - 0x316e8eef, 0x4669be79, 0xcb61b38c, 0xbc66831a, 0x256fd2a0, 0x5268e236, - 0xcc0c7795, 0xbb0b4703, 0x220216b9, 0x5505262f, 0xc5ba3bbe, 0xb2bd0b28, - 0x2bb45a92, 0x5cb36a04, 0xc2d7ffa7, 0xb5d0cf31, 0x2cd99e8b, 0x5bdeae1d, - 0x9b64c2b0, 0xec63f226, 0x756aa39c, 0x026d930a, 0x9c0906a9, 0xeb0e363f, - 0x72076785, 0x05005713, 0x95bf4a82, 0xe2b87a14, 0x7bb12bae, 0x0cb61b38, - 0x92d28e9b, 0xe5d5be0d, 0x7cdcefb7, 0x0bdbdf21, 0x86d3d2d4, 0xf1d4e242, - 0x68ddb3f8, 0x1fda836e, 0x81be16cd, 0xf6b9265b, 0x6fb077e1, 0x18b74777, - 0x88085ae6, 0xff0f6a70, 0x66063bca, 0x11010b5c, 0x8f659eff, 0xf862ae69, - 0x616bffd3, 0x166ccf45, 0xa00ae278, 0xd70dd2ee, 0x4e048354, 0x3903b3c2, - 0xa7672661, 0xd06016f7, 0x4969474d, 0x3e6e77db, 0xaed16a4a, 0xd9d65adc, - 0x40df0b66, 0x37d83bf0, 0xa9bcae53, 0xdebb9ec5, 0x47b2cf7f, 0x30b5ffe9, - 0xbdbdf21c, 0xcabac28a, 0x53b39330, 0x24b4a3a6, 0xbad03605, 0xcdd70693, - 0x54de5729, 0x23d967bf, 0xb3667a2e, 0xc4614ab8, 0x5d681b02, 0x2a6f2b94, - 0xb40bbe37, 0xc30c8ea1, 0x5a05df1b, 0x2d02ef8d -}; - -uint32_t calc_crc32(uint32_t initval, uint8_t *charArr, uint32_t arraySize) -{ - uint32_t cval = initval; - int ijk; - for (ijk = 0; ijk < arraySize; ijk++) - cval = (cval >> 8) ^ crc32_table[(cval & 0xFF) ^ *charArr++]; - - return cval; -} diff --git a/util/broadcom/secimage/sbi.c b/util/broadcom/secimage/sbi.c index b5d9a12..58d4a39 100644 --- a/util/broadcom/secimage/sbi.c +++ b/util/broadcom/secimage/sbi.c @@ -17,6 +17,7 @@ #include <sys/types.h> #include <sys/stat.h> #include <unistd.h> +#include <zlib.h> #include "secimage.h" #define MIN_SIZE (1024*120) @@ -150,7 +151,7 @@ int CreateSecureBootImage(int ac, char **av) if (!status) { ((HEADER *)buf)->Length = sbiLen; - ((HEADER *)buf)->crc = calc_crc32(0xFFFFFFFF, + ((HEADER *)buf)->crc = crc32(0xFFFFFFFF, (uint8_t *)buf, 12); printf("Generating Image file %s: %d bytes\n", diff --git a/util/broadcom/secimage/secimage.h b/util/broadcom/secimage/secimage.h index cea661c..395e66a 100644 --- a/util/broadcom/secimage/secimage.h +++ b/util/broadcom/secimage/secimage.h @@ -39,7 +39,6 @@ int DataRead(char *filename, uint8_t *buf, int *length); int AppendHMACSignature(uint8_t *data, uint32_t length, char *filename, uint32_t offset); int ReadBinaryFile(char *fname, uint8_t *buf, int maxlen); -uint32_t calc_crc32(uint32_t initval, uint8_t *charArr, uint32_t arraySize); void FillHeaderFromConfigFile(char *h, char *ConfigFileName); #endif /* _SECIMAGE_H_ */

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coreboot-gerrit August 2015