coreboot-gerrit August 2015

coreboot-gerrit@coreboot.org

1 participants
814 discussions

New patch to review for coreboot: x86: Make sure boot device is mapped below 4G
by Stefan Reinauer 04 Aug '15

04 Aug '15

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11121 -gerrit commit b09bead7d87e92a911ee33412452d406935755ef Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Tue Aug 4 11:14:17 2015 -0700 x86: Make sure boot device is mapped below 4G On x86-64 the current way of calculating the base address of the boot device (SPI flash) gets an unwanted sign extension, making it live somewhere at the end of 64bit address space. Enforce rom_base to be at the upper end of the 4G address space. Change-Id: Ia81e82094d3c51f6c10e02b4b0df2f3e1519d39e Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- src/arch/x86/mmap_boot.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/arch/x86/mmap_boot.c b/src/arch/x86/mmap_boot.c index 6c98954..53973f9 100644 --- a/src/arch/x86/mmap_boot.c +++ b/src/arch/x86/mmap_boot.c @@ -24,7 +24,7 @@ #include <stdlib.h> /* The ROM is memory mapped just below 4GiB. Form a pointer for the base. */ -#define rom_base ((void *)(uintptr_t)(-(int32_t)CONFIG_ROM_SIZE)) +#define rom_base ((void *)(uintptr_t)(0x100000000ULL-CONFIG_ROM_SIZE)) static const struct mem_region_device boot_dev = MEM_REGION_DEV_INIT(rom_base, CONFIG_ROM_SIZE);

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Patch merged into coreboot/master: libpayload: .xcompile target is an actual file
by gerrit＠coreboot.org 04 Aug '15

04 Aug '15

the following patch was just integrated into master: commit 5d5fcdd82b72c1fc621aab9fd6ff88cce9345d8e Author: Paul Kocialkowski <contact(a)paulk.fr> Date: Mon Aug 3 16:44:01 2015 +0200 libpayload: .xcompile target is an actual file Marking .xcompile as PHONY implies triggering the xcompile script each time make is invoked. This is particularly problematic, especially when the script cannot find the crossgcc toolchains on its own and has to be fed XGCCPATH. Change-Id: Icb5ae82b210bca1ee9cf56d76130eefde481f81e Signed-off-by: Paul Kocialkowski <contact(a)paulk.fr> Reviewed-on: http://review.coreboot.org/11118 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See http://review.coreboot.org/11118 for details. -gerrit

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Patch merged into coreboot/master: libpayload: Veyron configs unification
by gerrit＠coreboot.org 04 Aug '15

04 Aug '15

the following patch was just integrated into master: commit 8d829bf2cdd40c6f267586d390497ddc0900115b Author: Paul Kocialkowski <contact(a)paulk.fr> Date: Mon Aug 3 14:13:05 2015 +0200 libpayload: Veyron configs unification All the currently-provided configs for veyron boards are the same, so we might as well have a common one that can be used on all boards. Change-Id: I2e24f2d7a5206878381467b97f01d3e752a93289 Signed-off-by: Paul Kocialkowski <contact(a)paulk.fr> Reviewed-on: http://review.coreboot.org/11115 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/11115 for details. -gerrit

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New patch to review for coreboot: chromeos: vboot: Adaptations for using a separate object out directory
by Paul Kocialkowski 03 Aug '15

03 Aug '15

Paul Kocialkowski (contact(a)paulk.fr) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11120 -gerrit commit 246d57e5655afb6d31618fbd8c79c62e48aecde8 Author: Paul Kocialkowski <contact(a)paulk.fr> Date: Mon Aug 3 23:03:27 2015 +0200 chromeos: vboot: Adaptations for using a separate object out directory $(obj) might be defined either as a relative or an absolute path. This, it has to be filtered out before adding $(top) to it (in case of an absolute path) when building vboot. It is then provided separately in CFLAGS (as an absolute path). In addition, VB2_LIB inherits $(obj), so it might also already be an absolute path, and prefixing $(top) to it doesn't apply. Thus, the absolute path to it should be passed to the vboot make command. Change-Id: I13e893ebdf22c4513ee40d9331a30ac7de8f9788 Signed-off-by: Paul Kocialkowski <contact(a)paulk.fr> --- src/vendorcode/google/chromeos/vboot2/Makefile.inc | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/vendorcode/google/chromeos/vboot2/Makefile.inc b/src/vendorcode/google/chromeos/vboot2/Makefile.inc index 9026df6..b805993 100644 --- a/src/vendorcode/google/chromeos/vboot2/Makefile.inc +++ b/src/vendorcode/google/chromeos/vboot2/Makefile.inc @@ -55,10 +55,10 @@ endif endif # CONFIG_SEPARATE_VERSTAGE VB2_LIB = $(obj)/external/vboot_reference/vboot_fw20.a -VBOOT_CFLAGS += $(patsubst -I%,-I$(top)/%,$(filter-out -include $(src)/include/kconfig.h, $(CPPFLAGS_libverstage))) +VBOOT_CFLAGS += $(patsubst -I%,-I$(top)/%, $(filter-out -I$(obj), $(filter-out -include $(src)/include/kconfig.h, $(CPPFLAGS_libverstage)))) VBOOT_CFLAGS += $(CFLAGS_libverstage) VBOOT_CFLAGS += $(libverstage-c-ccopts) -VBOOT_CFLAGS += -include $(top)/src/include/kconfig.h -Wno-missing-prototypes +VBOOT_CFLAGS += -I$(abspath $(obj)) -include $(top)/src/include/kconfig.h -Wno-missing-prototypes VBOOT_CFLAGS += -DVBOOT_DEBUG $(VB2_LIB): $(obj)/config.h @@ -67,7 +67,7 @@ $(VB2_LIB): $(obj)/config.h CC="$(CC_verstage)" \ CFLAGS="$(VBOOT_CFLAGS)" VBOOT2="y" \ $(MAKE) -C $(VB_SOURCE) \ - BUILD=$(top)/$(dir $(VB2_LIB)) \ + BUILD=$(abspath $(dir $(VB2_LIB))) \ V=$(V) \ fwlib20

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Patch merged into coreboot/master: libpayload: Allow for KBUILD_DEFCONFIG override
by gerrit＠coreboot.org 03 Aug '15

03 Aug '15

the following patch was just integrated into master: commit db0c0c4a606852bd7e52ad88850e7b2441454050 Author: Paul Kocialkowski <contact(a)paulk.fr> Date: Mon Aug 3 14:05:33 2015 +0200 libpayload: Allow for KBUILD_DEFCONFIG override In order to specify a defconfig to libpayload, one might want to declare KBUILD_DEFCONFIG in the make command line and run the defconfig target. Change-Id: I2ade6f4ff2f0b6478a0831158028ebc79b5daa81 Signed-off-by: Paul Kocialkowski <contact(a)paulk.fr> Reviewed-on: http://review.coreboot.org/11112 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/11112 for details. -gerrit

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New patch to review for coreboot: xcompile: crossgcc lookup in parent paths, for painless libpayload support
by Paul Kocialkowski 03 Aug '15

03 Aug '15

Paul Kocialkowski (contact(a)paulk.fr) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11119 -gerrit commit 7144ee85fa7efbd9e21bdfbb80ae5f7912deb6c1 Author: Paul Kocialkowski <contact(a)paulk.fr> Date: Mon Aug 3 16:46:29 2015 +0200 xcompile: crossgcc lookup in parent paths, for painless libpayload support libpayload is calling the xcompile script from payloads/libpayload, so the script never finds the path on its own and has to be fed the right XGCCPATH by hand. This makes xcompile look for the parent path too, so that it can find the crossgcc toolchains when called from libpayload. Change-Id: Icc41bb68e3a43810f40f03ab1eb08af07a50a3de Signed-off-by: Paul Kocialkowski <contact(a)paulk.fr> --- util/xcompile/xcompile | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/util/xcompile/xcompile b/util/xcompile/xcompile index c1c42af..bc1a7e3 100755 --- a/util/xcompile/xcompile +++ b/util/xcompile/xcompile @@ -20,7 +20,18 @@ # TMPFILE="" -XGCCPATH=${1:-"`pwd`/util/crossgcc/xgcc/bin/"} + +# libpayload crossgcc path +if [ -d "`pwd`/../../util/crossgcc/xgcc/bin/" ] +then + XGCCPATH=${1:-"`pwd`/../../util/crossgcc/xgcc/bin/"} +fi + +# coreboot libgcc path +if [ -d "`pwd`/util/crossgcc/xgcc/bin/" ] +then + XGCCPATH=${1:-"`pwd`/util/crossgcc/xgcc/bin/"} +fi die() { echo "ERROR: $*" >&2

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New patch to review for coreboot: libpayload: .xcompile target is an actual file
by Paul Kocialkowski 03 Aug '15

03 Aug '15

Paul Kocialkowski (contact(a)paulk.fr) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11118 -gerrit commit 37dc65e5650d440e8fac7d9d10d472ac91e179ba Author: Paul Kocialkowski <contact(a)paulk.fr> Date: Mon Aug 3 16:44:01 2015 +0200 libpayload: .xcompile target is an actual file Marking .xcompile as PHONY implies triggering the xcompile script each time make is invoked. This is particularly problematic, especially when the script cannot find the crossgcc toolchains on its own and has to be fed XGCCPATH. Change-Id: Icb5ae82b210bca1ee9cf56d76130eefde481f81e Signed-off-by: Paul Kocialkowski <contact(a)paulk.fr> --- payloads/libpayload/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/payloads/libpayload/Makefile b/payloads/libpayload/Makefile index 206785c..ba883cc 100644 --- a/payloads/libpayload/Makefile +++ b/payloads/libpayload/Makefile @@ -312,4 +312,4 @@ distclean: clean-cscope rm -rf $(obj) rm -f .config .config.old ..config.tmp .kconfig.d .tmpconfig* .ccwrap .xcompile -.PHONY: $(PHONY) clean clean-cscope cscope distclean doxygen doxy .xcompile +.PHONY: $(PHONY) clean clean-cscope cscope distclean doxygen doxy

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New patch to review for coreboot: google: veryron_*: CBFS_SIZE to match the available size for coreboot
by Paul Kocialkowski 03 Aug '15

03 Aug '15

Paul Kocialkowski (contact(a)paulk.fr) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11117 -gerrit commit f7c3cd7785636f76c59b2e292d8482b19666172b Author: Paul Kocialkowski <contact(a)paulk.fr> Date: Mon Aug 3 14:24:09 2015 +0200 google: veryron_*: CBFS_SIZE to match the available size for coreboot Veyron boards come with a 4 MiB SPI flash chip. However, only 1 MiB of those is available for coreboot and the rest shouldn't be overriden by it. Change-Id: I168386a5011222866654a496d8d054faff7a9406 Signed-off-by: Paul Kocialkowski <contact(a)paulk.fr> --- src/mainboard/google/veyron_brain/Kconfig | 4 ++++ src/mainboard/google/veyron_danger/Kconfig | 4 ++++ src/mainboard/google/veyron_jerry/Kconfig | 4 ++++ src/mainboard/google/veyron_mickey/Kconfig | 4 ++++ src/mainboard/google/veyron_mighty/Kconfig | 4 ++++ src/mainboard/google/veyron_minnie/Kconfig | 4 ++++ src/mainboard/google/veyron_pinky/Kconfig | 4 ++++ src/mainboard/google/veyron_rialto/Kconfig | 4 ++++ src/mainboard/google/veyron_romy/Kconfig | 4 ++++ src/mainboard/google/veyron_shark/Kconfig | 4 ++++ src/mainboard/google/veyron_speedy/Kconfig | 4 ++++ 11 files changed, 44 insertions(+) diff --git a/src/mainboard/google/veyron_brain/Kconfig b/src/mainboard/google/veyron_brain/Kconfig index e76496b..f3fe59a 100644 --- a/src/mainboard/google/veyron_brain/Kconfig +++ b/src/mainboard/google/veyron_brain/Kconfig @@ -69,4 +69,8 @@ config PMIC_BUS int default 0 +config CBFS_SIZE + hex + default 0x100000 + endif # BOARD_GOOGLE_VEYRON_BRAIN diff --git a/src/mainboard/google/veyron_danger/Kconfig b/src/mainboard/google/veyron_danger/Kconfig index e2128eb..82671c0 100644 --- a/src/mainboard/google/veyron_danger/Kconfig +++ b/src/mainboard/google/veyron_danger/Kconfig @@ -68,4 +68,8 @@ config PMIC_BUS int default 0 +config CBFS_SIZE + hex + default 0x100000 + endif # BOARD_GOOGLE_VEYRON_DANGER diff --git a/src/mainboard/google/veyron_jerry/Kconfig b/src/mainboard/google/veyron_jerry/Kconfig index 3e65e67..107114e 100644 --- a/src/mainboard/google/veyron_jerry/Kconfig +++ b/src/mainboard/google/veyron_jerry/Kconfig @@ -79,4 +79,8 @@ config PMIC_BUS int default 0 +config CBFS_SIZE + hex + default 0x100000 + endif # BOARD_GOOGLE_VEYRON_JERRY diff --git a/src/mainboard/google/veyron_mickey/Kconfig b/src/mainboard/google/veyron_mickey/Kconfig index 9233a91..1d73ef2 100644 --- a/src/mainboard/google/veyron_mickey/Kconfig +++ b/src/mainboard/google/veyron_mickey/Kconfig @@ -69,4 +69,8 @@ config PMIC_BUS int default 0 +config CBFS_SIZE + hex + default 0x100000 + endif # BOARD_GOOGLE_VEYRON_MICKEY diff --git a/src/mainboard/google/veyron_mighty/Kconfig b/src/mainboard/google/veyron_mighty/Kconfig index 90cdbb5..0eead7f 100644 --- a/src/mainboard/google/veyron_mighty/Kconfig +++ b/src/mainboard/google/veyron_mighty/Kconfig @@ -79,4 +79,8 @@ config PMIC_BUS int default 0 +config CBFS_SIZE + hex + default 0x100000 + endif # BOARD_GOOGLE_VEYRON_MIGHTY diff --git a/src/mainboard/google/veyron_minnie/Kconfig b/src/mainboard/google/veyron_minnie/Kconfig index a2d4846..10dd91c 100644 --- a/src/mainboard/google/veyron_minnie/Kconfig +++ b/src/mainboard/google/veyron_minnie/Kconfig @@ -79,4 +79,8 @@ config PMIC_BUS int default 0 +config CBFS_SIZE + hex + default 0x100000 + endif # BOARD_GOOGLE_VEYRON_MINNIE diff --git a/src/mainboard/google/veyron_pinky/Kconfig b/src/mainboard/google/veyron_pinky/Kconfig index 4b0d471..d38f02d 100644 --- a/src/mainboard/google/veyron_pinky/Kconfig +++ b/src/mainboard/google/veyron_pinky/Kconfig @@ -79,4 +79,8 @@ config PMIC_BUS int default 0 +config CBFS_SIZE + hex + default 0x100000 + endif # BOARD_GOOGLE_VEYRON_PINKY diff --git a/src/mainboard/google/veyron_rialto/Kconfig b/src/mainboard/google/veyron_rialto/Kconfig index 0061bfa..3ff1c76 100644 --- a/src/mainboard/google/veyron_rialto/Kconfig +++ b/src/mainboard/google/veyron_rialto/Kconfig @@ -69,4 +69,8 @@ config PMIC_BUS int default 0 +config CBFS_SIZE + hex + default 0x100000 + endif # BOARD_GOOGLE_VEYRON_RIALTO diff --git a/src/mainboard/google/veyron_romy/Kconfig b/src/mainboard/google/veyron_romy/Kconfig index b7f05d7..4f54763 100644 --- a/src/mainboard/google/veyron_romy/Kconfig +++ b/src/mainboard/google/veyron_romy/Kconfig @@ -69,4 +69,8 @@ config PMIC_BUS int default 0 +config CBFS_SIZE + hex + default 0x100000 + endif # BOARD_GOOGLE_VEYRON_ROMY diff --git a/src/mainboard/google/veyron_shark/Kconfig b/src/mainboard/google/veyron_shark/Kconfig index 0cefbc6..f4462b9 100644 --- a/src/mainboard/google/veyron_shark/Kconfig +++ b/src/mainboard/google/veyron_shark/Kconfig @@ -79,4 +79,8 @@ config PMIC_BUS int default 0 +config CBFS_SIZE + hex + default 0x100000 + endif # BOARD_GOOGLE_VEYRON_SHARK diff --git a/src/mainboard/google/veyron_speedy/Kconfig b/src/mainboard/google/veyron_speedy/Kconfig index d4003dc..fbe5917 100644 --- a/src/mainboard/google/veyron_speedy/Kconfig +++ b/src/mainboard/google/veyron_speedy/Kconfig @@ -79,4 +79,8 @@ config PMIC_BUS int default 0 +config CBFS_SIZE + hex + default 0x100000 + endif # BOARD_GOOGLE_VEYRON_SPEEDY

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New patch to review for coreboot: chromeos: Allow for VB_SOURCE override
by Paul Kocialkowski 03 Aug '15

03 Aug '15

Paul Kocialkowski (contact(a)paulk.fr) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11116 -gerrit commit 614f62a5aaec9543a9ebd14263d1d38823d81363 Author: Paul Kocialkowski <contact(a)paulk.fr> Date: Mon Aug 3 14:11:54 2015 +0200 chromeos: Allow for VB_SOURCE override One may prefer to include vboot from another directory than 3rdparty for convenience. This is especially the case in Libreboot, where 3rdparty is not checked out at all. Change-Id: I13167eb604a777a2ba87c3567f134ef3ff9610e4 Signed-off-by: Paul Kocialkowski <contact(a)paulk.fr> --- src/vendorcode/google/chromeos/Makefile.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/vendorcode/google/chromeos/Makefile.inc b/src/vendorcode/google/chromeos/Makefile.inc index a61bfb6..612af41 100644 --- a/src/vendorcode/google/chromeos/Makefile.inc +++ b/src/vendorcode/google/chromeos/Makefile.inc @@ -53,6 +53,6 @@ else CFLAGS_common += -DMOCK_TPM=0 endif -VB_SOURCE := 3rdparty/vboot +VB_SOURCE ?= 3rdparty/vboot subdirs-$(CONFIG_VBOOT_VERIFY_FIRMWARE) += vboot2 CPPFLAGS_common += -I$(VB_SOURCE)/firmware/include

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New patch to review for coreboot: libpayload: Veyron configs unification
by Paul Kocialkowski 03 Aug '15

03 Aug '15

Paul Kocialkowski (contact(a)paulk.fr) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11115 -gerrit commit 72d973bda16c668077a74bbabb80d104b0701325 Author: Paul Kocialkowski <contact(a)paulk.fr> Date: Mon Aug 3 14:13:05 2015 +0200 libpayload: Veyron configs unification All the currently-provided configs for veyron boards are the same, so we might as well have a common one that can be used on all boards. Change-Id: I2e24f2d7a5206878381467b97f01d3e752a93289 Signed-off-by: Paul Kocialkowski <contact(a)paulk.fr> --- payloads/libpayload/configs/config.veyron | 81 ++++++++++++++++++++++++ payloads/libpayload/configs/config.veyron_brain | 81 ------------------------ payloads/libpayload/configs/config.veyron_danger | 81 ------------------------ 3 files changed, 81 insertions(+), 162 deletions(-) diff --git a/payloads/libpayload/configs/config.veyron b/payloads/libpayload/configs/config.veyron new file mode 100644 index 0000000..8843098 --- /dev/null +++ b/payloads/libpayload/configs/config.veyron @@ -0,0 +1,81 @@ +# +# Automatically generated file; DO NOT EDIT. +# Libpayload Configuration +# + +# +# Generic Options +# +CONFIG_LP_GPL=y +# CONFIG_LP_EXPERIMENTAL is not set +# CONFIG_LP_DEVELOPER is not set +CONFIG_LP_COMPILER_GCC=y +# CONFIG_LP_COMPILER_LLVM_CLANG is not set +# CONFIG_LP_REMOTEGDB is not set +CONFIG_LP_CHROMEOS=y + +# +# Architecture Options +# +CONFIG_LP_ARCH_ARM=y +# CONFIG_LP_ARCH_X86 is not set +# CONFIG_LP_ARCH_ARM64 is not set +# CONFIG_LP_ARCH_MIPS is not set +# CONFIG_LP_MEMMAP_RAM_ONLY is not set + +# +# Standard Libraries +# +CONFIG_LP_LIBC=y +# CONFIG_LP_CURSES is not set +CONFIG_LP_CBFS=y +CONFIG_LP_LZMA=y + +# +# Console Options +# +CONFIG_LP_SKIP_CONSOLE_INIT=y +CONFIG_LP_CBMEM_CONSOLE=y +CONFIG_LP_SERIAL_CONSOLE=y +# CONFIG_LP_8250_SERIAL_CONSOLE is not set +# CONFIG_LP_S5P_SERIAL_CONSOLE is not set +CONFIG_LP_8250_MMIO32_SERIAL_CONSOLE=y +# CONFIG_LP_IPQ806X_SERIAL_CONSOLE is not set +# CONFIG_LP_BG4CD_SERIAL_CONSOLE is not set +# CONFIG_LP_SERIAL_SET_SPEED is not set +# CONFIG_LP_SERIAL_ACS_FALLBACK is not set +CONFIG_LP_VIDEO_CONSOLE=y +CONFIG_LP_COREBOOT_VIDEO_CONSOLE=y +# CONFIG_LP_PC_KEYBOARD is not set + +# +# Drivers +# +# CONFIG_LP_RTC_PORT_EXTENDED_VIA is not set +# CONFIG_LP_STORAGE is not set +# CONFIG_LP_TIMER_NONE is not set +# CONFIG_LP_TIMER_MCT is not set +# CONFIG_LP_TIMER_TEGRA_1US is not set +# CONFIG_LP_TIMER_IPQ806X is not set +CONFIG_LP_TIMER_RK=y +# CONFIG_LP_TIMER_BG4CD is not set +# CONFIG_LP_TIMER_CYGNUS is not set +# CONFIG_LP_TIMER_IMG_PISTACHIO is not set +# CONFIG_LP_TIMER_MTK is not set +CONFIG_LP_TIMER_RK_ADDRESS=0xff810020 +CONFIG_LP_USB=y +# CONFIG_LP_USB_OHCI is not set +CONFIG_LP_USB_EHCI=y +# CONFIG_LP_USB_XHCI is not set +CONFIG_LP_USB_DWC2=y +# CONFIG_LP_USB_HID is not set +CONFIG_LP_USB_HUB=y +# CONFIG_LP_USB_EHCI_HOSTPC_ROOT_HUB_TT is not set +CONFIG_LP_USB_MSC=y +CONFIG_LP_USB_GEN_HUB=y +# CONFIG_LP_USB_PCI is not set +# CONFIG_LP_UDC is not set +# CONFIG_LP_BIG_ENDIAN is not set +CONFIG_LP_LITTLE_ENDIAN=y +# CONFIG_LP_IO_ADDRESS_SPACE is not set +CONFIG_LP_ARCH_SPECIFIC_OPTIONS=y diff --git a/payloads/libpayload/configs/config.veyron_brain b/payloads/libpayload/configs/config.veyron_brain deleted file mode 100644 index 8843098..0000000 --- a/payloads/libpayload/configs/config.veyron_brain +++ /dev/null @@ -1,81 +0,0 @@ -# -# Automatically generated file; DO NOT EDIT. -# Libpayload Configuration -# - -# -# Generic Options -# -CONFIG_LP_GPL=y -# CONFIG_LP_EXPERIMENTAL is not set -# CONFIG_LP_DEVELOPER is not set -CONFIG_LP_COMPILER_GCC=y -# CONFIG_LP_COMPILER_LLVM_CLANG is not set -# CONFIG_LP_REMOTEGDB is not set -CONFIG_LP_CHROMEOS=y - -# -# Architecture Options -# -CONFIG_LP_ARCH_ARM=y -# CONFIG_LP_ARCH_X86 is not set -# CONFIG_LP_ARCH_ARM64 is not set -# CONFIG_LP_ARCH_MIPS is not set -# CONFIG_LP_MEMMAP_RAM_ONLY is not set - -# -# Standard Libraries -# -CONFIG_LP_LIBC=y -# CONFIG_LP_CURSES is not set -CONFIG_LP_CBFS=y -CONFIG_LP_LZMA=y - -# -# Console Options -# -CONFIG_LP_SKIP_CONSOLE_INIT=y -CONFIG_LP_CBMEM_CONSOLE=y -CONFIG_LP_SERIAL_CONSOLE=y -# CONFIG_LP_8250_SERIAL_CONSOLE is not set -# CONFIG_LP_S5P_SERIAL_CONSOLE is not set -CONFIG_LP_8250_MMIO32_SERIAL_CONSOLE=y -# CONFIG_LP_IPQ806X_SERIAL_CONSOLE is not set -# CONFIG_LP_BG4CD_SERIAL_CONSOLE is not set -# CONFIG_LP_SERIAL_SET_SPEED is not set -# CONFIG_LP_SERIAL_ACS_FALLBACK is not set -CONFIG_LP_VIDEO_CONSOLE=y -CONFIG_LP_COREBOOT_VIDEO_CONSOLE=y -# CONFIG_LP_PC_KEYBOARD is not set - -# -# Drivers -# -# CONFIG_LP_RTC_PORT_EXTENDED_VIA is not set -# CONFIG_LP_STORAGE is not set -# CONFIG_LP_TIMER_NONE is not set -# CONFIG_LP_TIMER_MCT is not set -# CONFIG_LP_TIMER_TEGRA_1US is not set -# CONFIG_LP_TIMER_IPQ806X is not set -CONFIG_LP_TIMER_RK=y -# CONFIG_LP_TIMER_BG4CD is not set -# CONFIG_LP_TIMER_CYGNUS is not set -# CONFIG_LP_TIMER_IMG_PISTACHIO is not set -# CONFIG_LP_TIMER_MTK is not set -CONFIG_LP_TIMER_RK_ADDRESS=0xff810020 -CONFIG_LP_USB=y -# CONFIG_LP_USB_OHCI is not set -CONFIG_LP_USB_EHCI=y -# CONFIG_LP_USB_XHCI is not set -CONFIG_LP_USB_DWC2=y -# CONFIG_LP_USB_HID is not set -CONFIG_LP_USB_HUB=y -# CONFIG_LP_USB_EHCI_HOSTPC_ROOT_HUB_TT is not set -CONFIG_LP_USB_MSC=y -CONFIG_LP_USB_GEN_HUB=y -# CONFIG_LP_USB_PCI is not set -# CONFIG_LP_UDC is not set -# CONFIG_LP_BIG_ENDIAN is not set -CONFIG_LP_LITTLE_ENDIAN=y -# CONFIG_LP_IO_ADDRESS_SPACE is not set -CONFIG_LP_ARCH_SPECIFIC_OPTIONS=y diff --git a/payloads/libpayload/configs/config.veyron_danger b/payloads/libpayload/configs/config.veyron_danger deleted file mode 100644 index 8843098..0000000 --- a/payloads/libpayload/configs/config.veyron_danger +++ /dev/null @@ -1,81 +0,0 @@ -# -# Automatically generated file; DO NOT EDIT. -# Libpayload Configuration -# - -# -# Generic Options -# -CONFIG_LP_GPL=y -# CONFIG_LP_EXPERIMENTAL is not set -# CONFIG_LP_DEVELOPER is not set -CONFIG_LP_COMPILER_GCC=y -# CONFIG_LP_COMPILER_LLVM_CLANG is not set -# CONFIG_LP_REMOTEGDB is not set -CONFIG_LP_CHROMEOS=y - -# -# Architecture Options -# -CONFIG_LP_ARCH_ARM=y -# CONFIG_LP_ARCH_X86 is not set -# CONFIG_LP_ARCH_ARM64 is not set -# CONFIG_LP_ARCH_MIPS is not set -# CONFIG_LP_MEMMAP_RAM_ONLY is not set - -# -# Standard Libraries -# -CONFIG_LP_LIBC=y -# CONFIG_LP_CURSES is not set -CONFIG_LP_CBFS=y -CONFIG_LP_LZMA=y - -# -# Console Options -# -CONFIG_LP_SKIP_CONSOLE_INIT=y -CONFIG_LP_CBMEM_CONSOLE=y -CONFIG_LP_SERIAL_CONSOLE=y -# CONFIG_LP_8250_SERIAL_CONSOLE is not set -# CONFIG_LP_S5P_SERIAL_CONSOLE is not set -CONFIG_LP_8250_MMIO32_SERIAL_CONSOLE=y -# CONFIG_LP_IPQ806X_SERIAL_CONSOLE is not set -# CONFIG_LP_BG4CD_SERIAL_CONSOLE is not set -# CONFIG_LP_SERIAL_SET_SPEED is not set -# CONFIG_LP_SERIAL_ACS_FALLBACK is not set -CONFIG_LP_VIDEO_CONSOLE=y -CONFIG_LP_COREBOOT_VIDEO_CONSOLE=y -# CONFIG_LP_PC_KEYBOARD is not set - -# -# Drivers -# -# CONFIG_LP_RTC_PORT_EXTENDED_VIA is not set -# CONFIG_LP_STORAGE is not set -# CONFIG_LP_TIMER_NONE is not set -# CONFIG_LP_TIMER_MCT is not set -# CONFIG_LP_TIMER_TEGRA_1US is not set -# CONFIG_LP_TIMER_IPQ806X is not set -CONFIG_LP_TIMER_RK=y -# CONFIG_LP_TIMER_BG4CD is not set -# CONFIG_LP_TIMER_CYGNUS is not set -# CONFIG_LP_TIMER_IMG_PISTACHIO is not set -# CONFIG_LP_TIMER_MTK is not set -CONFIG_LP_TIMER_RK_ADDRESS=0xff810020 -CONFIG_LP_USB=y -# CONFIG_LP_USB_OHCI is not set -CONFIG_LP_USB_EHCI=y -# CONFIG_LP_USB_XHCI is not set -CONFIG_LP_USB_DWC2=y -# CONFIG_LP_USB_HID is not set -CONFIG_LP_USB_HUB=y -# CONFIG_LP_USB_EHCI_HOSTPC_ROOT_HUB_TT is not set -CONFIG_LP_USB_MSC=y -CONFIG_LP_USB_GEN_HUB=y -# CONFIG_LP_USB_PCI is not set -# CONFIG_LP_UDC is not set -# CONFIG_LP_BIG_ENDIAN is not set -CONFIG_LP_LITTLE_ENDIAN=y -# CONFIG_LP_IO_ADDRESS_SPACE is not set -CONFIG_LP_ARCH_SPECIFIC_OPTIONS=y

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coreboot-gerrit August 2015