the following patch was just integrated into master:
commit 9dd8f888418e75debb767fa799e5a4ce2b924bf6
Author: Stefan Reinauer <reinauer(a)chromium.org>
Date: Thu Aug 6 16:55:09 2015 -0700
secimage: reformat
Change-Id: Ibfa8b6b60b2b39212cef27bb2a5f8849218164bb
Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org>
Reviewed-on: http://review.coreboot.org/11133
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi(a)google.com>
See http://review.coreboot.org/11133 for details.
-gerrit
Paul Kocialkowski (contact(a)paulk.fr) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11144
-gerrit
commit 7a5ab2b45de46426164e08b7630ec6613e113316
Author: Paul Kocialkowski <contact(a)paulk.fr>
Date: Sun Aug 9 10:28:04 2015 +0200
chromeos: vboot_handoff_flag fallback value
vboot_handoff_flag shouldn't always return 0 when vboot handoff data is not
found, instead, it should be fed with a fallback value that is used when vboot
handoff data is missing. This way, each calls registers a fallback value that
implements the default behaviour when not using vboot.
This allows setting up the display when vboot is not enabled.
Change-Id: Icd986a37c8006acd92ad12ae136f721e1063ad95
Signed-off-by: Paul Kocialkowski <contact(a)paulk.fr>
---
src/vendorcode/google/chromeos/chromeos.c | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/src/vendorcode/google/chromeos/chromeos.c b/src/vendorcode/google/chromeos/chromeos.c
index 0737267..6b6b9c0 100644
--- a/src/vendorcode/google/chromeos/chromeos.c
+++ b/src/vendorcode/google/chromeos/chromeos.c
@@ -26,31 +26,31 @@
#include <console/console.h>
#include "vboot_handoff.h"
-static int vboot_handoff_flag(uint32_t flag)
+static int vboot_handoff_flag(uint32_t flag, int fallback)
{
struct vboot_handoff *vbho;
vbho = cbmem_find(CBMEM_ID_VBOOT_HANDOFF);
if (vbho == NULL)
- return 0;
+ return fallback;
return !!(vbho->init_params.out_flags & flag);
}
int vboot_skip_display_init(void)
{
- return !vboot_handoff_flag(VB_INIT_OUT_ENABLE_DISPLAY);
+ return !vboot_handoff_flag(VB_INIT_OUT_ENABLE_DISPLAY, 1);
}
int vboot_enable_developer(void)
{
- return vboot_handoff_flag(VB_INIT_OUT_ENABLE_DEVELOPER);
+ return vboot_handoff_flag(VB_INIT_OUT_ENABLE_DEVELOPER, 0);
}
int vboot_enable_recovery(void)
{
- return vboot_handoff_flag(VB_INIT_OUT_ENABLE_RECOVERY);
+ return vboot_handoff_flag(VB_INIT_OUT_ENABLE_RECOVERY, 0);
}
int __attribute__((weak)) clear_recovery_mode_switch(void)
Paul Kocialkowski (contact(a)paulk.fr) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11143
-gerrit
commit 935380ed10f1e5af95c216e2b2265192f1ae5ba5
Author: Paul Kocialkowski <contact(a)paulk.fr>
Date: Sun Aug 9 10:23:38 2015 +0200
chromeos: No dependency of ChromeOS bindings against vboot firmware verification
Some ChromeOS bindings might be wanted without using vboot verification, so the
CHROMEOS Kconfig option shouldn't depend on VBOOT_VERIFY_FIRMWARE.
This allows booting Coreboot all the way up to payload from the RO firmware
path, without jumping to a RW firmware along the way, during normal boot.
However, it makes sense to select it by default.
Change-Id: Ia4057a56838aa05dcf3cb250ae1a27fd91402ddb
Signed-off-by: Paul Kocialkowski <contact(a)paulk.fr>
---
src/vendorcode/google/chromeos/Kconfig | 7 +++++--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/src/vendorcode/google/chromeos/Kconfig b/src/vendorcode/google/chromeos/Kconfig
index 2f04f24..78a969a 100644
--- a/src/vendorcode/google/chromeos/Kconfig
+++ b/src/vendorcode/google/chromeos/Kconfig
@@ -31,7 +31,6 @@ config CHROMEOS
select BOOTMODE_STRAPS
select ELOG
select COLLECT_TIMESTAMPS
- select VBOOT_VERIFY_FIRMWARE
help
Enable ChromeOS specific features like the GPIO sub table in
the coreboot table. NOTE: Enabling this option on an unsupported
@@ -129,7 +128,7 @@ config VIRTUAL_DEV_SWITCH
config VBOOT_VERIFY_FIRMWARE
bool "Verify firmware with vboot."
- default n
+ default y
depends on HAVE_HARD_RESET
help
Enabling VBOOT_VERIFY_FIRMWARE will use vboot to verify the components
@@ -163,8 +162,12 @@ config WIPEOUT_SUPPORTED
signal the application the need for factory reset (a.k.a. wipe
out) of the device
+if VBOOT_VERIFY_FIRMWARE
+
source src/vendorcode/google/chromeos/vboot2/Kconfig
+endif # VBOOT_VERIFY_FIRMWARE
+
endif # CHROMEOS
if !CHROMEOS
config VIRTUAL_DEV_SWITCH
the following patch was just integrated into master:
commit 133108af2550ae3f6dc6eda14c03d2e195b81240
Author: Patrick Georgi <patrick(a)georgi-clan.de>
Date: Sat Aug 8 23:20:58 2015 +0200
acpi: Align FACS to 64 bytes
The spec states (5.2.10): "The BIOS aligns the FACS on a 64-byte boundary
anywhere within the system's memory address space."
Change-Id: Ie9415e505525dbdd418028d4954018c829921a18
Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de>
Found-by: fwts 15.08
Reviewed-on: http://review.coreboot.org/11141
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
See http://review.coreboot.org/11141 for details.
-gerrit
Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11141
-gerrit
commit ffce93ca7ee29cc1ebe565b0e17daca7c8caedd8
Author: Patrick Georgi <patrick(a)georgi-clan.de>
Date: Sat Aug 8 23:20:58 2015 +0200
acpi: Align FACS to 64 bytes
The spec states (5.2.10): "The BIOS aligns the FACS on a 64-byte boundary
anywhere within the system's memory address space."
Change-Id: Ie9415e505525dbdd418028d4954018c829921a18
Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de>
Found-by: fwts 15.08
---
src/arch/x86/acpi.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/arch/x86/acpi.c b/src/arch/x86/acpi.c
index 134e437..0439ab5 100644
--- a/src/arch/x86/acpi.c
+++ b/src/arch/x86/acpi.c
@@ -815,6 +815,7 @@ unsigned long write_acpi_tables(unsigned long start)
acpi_write_xsdt(xsdt, oem_id, oem_table_id);
printk(BIOS_DEBUG, "ACPI: * FACS\n");
+ current = (ALIGN(current, 64));
facs = (acpi_facs_t *) current;
current += sizeof(acpi_facs_t);
ALIGN_CURRENT;
Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11141
-gerrit
commit 7736e4e87643954e4344ab7026852819875e19b5
Author: Patrick Georgi <patrick(a)georgi-clan.de>
Date: Sat Aug 8 23:20:58 2015 +0200
acpi: Align FACS to 64 bytes
The spec states (5.2.10): "The BIOS aligns the FACS on a 64-byte boundary
anywhere within the system's memory address space."
Change-Id: Ie9415e505525dbdd418028d4954018c829921a18
Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de>
---
src/arch/x86/acpi.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/arch/x86/acpi.c b/src/arch/x86/acpi.c
index 134e437..0439ab5 100644
--- a/src/arch/x86/acpi.c
+++ b/src/arch/x86/acpi.c
@@ -815,6 +815,7 @@ unsigned long write_acpi_tables(unsigned long start)
acpi_write_xsdt(xsdt, oem_id, oem_table_id);
printk(BIOS_DEBUG, "ACPI: * FACS\n");
+ current = (ALIGN(current, 64));
facs = (acpi_facs_t *) current;
current += sizeof(acpi_facs_t);
ALIGN_CURRENT;
Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11140
-gerrit
commit 24d769f4b27a4b40a52651e17780c5f5d9d5ca05
Author: Patrick Georgi <patrick(a)georgi-clan.de>
Date: Sat Aug 8 22:07:10 2015 +0200
getac/p470: enable GPU devices in devicetree
This enables adding the GPU specific entries to the SSDT.
Change-Id: I04d0eb7bf6f3e28d89c9318b777875e8a78b1ab5
Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de>
---
src/mainboard/getac/p470/devicetree.cb | 7 +++----
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/src/mainboard/getac/p470/devicetree.cb b/src/mainboard/getac/p470/devicetree.cb
index cbf7651..edf165e 100644
--- a/src/mainboard/getac/p470/devicetree.cb
+++ b/src/mainboard/getac/p470/devicetree.cb
@@ -31,10 +31,9 @@ chip northbridge/intel/i945
device domain 0 on
device pci 00.0 on end # host bridge
- # autodetect:
- #device pci 01.0 off end # i945 PCIe root port
- #device pci 02.0 on end # vga controller
- #device pci 02.1 on end # display controller
+ device pci 01.0 off end # i945 PCIe root port
+ device pci 02.0 on end # vga controller
+ device pci 02.1 on end # display controller
chip southbridge/intel/i82801gx
register "pirqa_routing" = "0x0a"
Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11139
-gerrit
commit fafa83ca4839da333c096c6cc67d5e0f4ead1a0e
Author: Patrick Georgi <patrick(a)georgi-clan.de>
Date: Sat Aug 8 22:02:12 2015 +0200
intel/i945: don't read structs out of uninitialized pointers
Change-Id: I7f17cd1418f05ff3e8cd559eca6ec3ce7f9bfb79
Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de>
---
src/northbridge/intel/i945/gma.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c
index a2e5163..437b6ce 100644
--- a/src/northbridge/intel/i945/gma.c
+++ b/src/northbridge/intel/i945/gma.c
@@ -496,6 +496,9 @@ intel_gma_get_controller_info(void)
return NULL;
}
struct northbridge_intel_i945_config *chip = dev->chip_info;
+ if (!chip) {
+ return NULL;
+ }
return &chip->gfx;
}
Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11139
-gerrit
commit 539ab91d52228a6e7b662ae0555564ec13dcc7a0
Author: Patrick Georgi <patrick(a)georgi-clan.de>
Date: Sat Aug 8 22:02:12 2015 +0200
intel/i945: don't read structs out of uninitialized arrays
Change-Id: I7f17cd1418f05ff3e8cd559eca6ec3ce7f9bfb79
Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de>
---
src/northbridge/intel/i945/gma.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c
index a2e5163..437b6ce 100644
--- a/src/northbridge/intel/i945/gma.c
+++ b/src/northbridge/intel/i945/gma.c
@@ -496,6 +496,9 @@ intel_gma_get_controller_info(void)
return NULL;
}
struct northbridge_intel_i945_config *chip = dev->chip_info;
+ if (!chip) {
+ return NULL;
+ }
return &chip->gfx;
}