coreboot-gerrit August 2015

coreboot-gerrit@coreboot.org

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814 discussions

New patch to review for coreboot: seabios integration: fix interaction with ccache
by Patrick Georgi 08 Aug '15

08 Aug '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11138 -gerrit commit 21970e82aa239c134d3a5f0d9936040a5fd2d62c Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Sat Aug 8 21:35:38 2015 +0200 seabios integration: fix interaction with ccache SeaBIOS' build system doesn't like CC to be a compound command like "ccache gcc", so we strip things. Unfortunately with CCACHE enabled, we passed /usr/bin/ccache (or wherever it was found on the PATH). Instead use the second term in CCACHE mode. Change-Id: I905fcdc73d067e553e923e307fafceaacdefdc6c Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> --- payloads/external/Makefile.inc | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/payloads/external/Makefile.inc b/payloads/external/Makefile.inc index 33ed47f..7f4b4c8 100644 --- a/payloads/external/Makefile.inc +++ b/payloads/external/Makefile.inc @@ -19,10 +19,11 @@ ## Foundation, Inc. ## +SEABIOS_CC_OFFSET=$(if $(filter %ccache,$(HOSTCC)),2,1) seabios: $(MAKE) -C payloads/external/SeaBIOS -f Makefile.inc \ HOSTCC="$(HOSTCC)" \ - CC=$(word 1,$(CC_x86_32)) CFLAGS="$(patsubst $(word 1,$(CC_x86_32))%,,$(CC_x86_32))" \ + CC=$(word $(SEABIOS_CC_OFFSET),$(CC_x86_32)) CFLAGS="$(patsubst $(word $(SEABIOS_CC_OFFSET),$(CC_x86_32))%,,$(CC_x86_32))" \ LD=$(word 1,$(LD_x86_32)) LDFLAGS="$(patsubst $(word 1,$(LD_x86_32))%,,$(LD_x86_32))" \ OBJDUMP="$(OBJDUMP_x86_32)" \ OBJCOPY="$(OBJCOPY_x86_32)" STRIP="$(STRIP_x86_32)" \

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New patch to review for coreboot: libpayload: Fix compile error in time.c if nvram support is disabled
by Patrick Georgi 08 Aug '15

08 Aug '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11137 -gerrit commit 8b69bf09691a889418bacd1c932fc8e910504bd6 Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Sat Aug 8 11:52:06 2015 +0200 libpayload: Fix compile error in time.c if nvram support is disabled rdtsc() is only used for nvram access. Change-Id: I896116d6a5782e5e50aa3acfbe1831b080f55d34 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> --- payloads/libpayload/libc/time.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/payloads/libpayload/libc/time.c b/payloads/libpayload/libc/time.c index 4109eab..4ed788f 100644 --- a/payloads/libpayload/libc/time.c +++ b/payloads/libpayload/libc/time.c @@ -34,7 +34,7 @@ #include <libpayload-config.h> #include <libpayload.h> -#if IS_ENABLED(CONFIG_LP_ARCH_X86) +#if IS_ENABLED(CONFIG_LP_ARCH_X86) && IS_ENABLED(CONFIG_LP_NVRAM) #include <arch/rdtsc.h> #endif

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New patch to review for coreboot: getac/p470: use native VGA init
by Patrick Georgi 08 Aug '15

08 Aug '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11136 -gerrit commit b1d4a9c200a6d315e4b1f274e2b13c46d3e859dd Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Sat Sep 6 17:23:30 2014 +0200 getac/p470: use native VGA init Change-Id: I6c5a2324d1a9e21f4e052678be8f0e0dbfed6494 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> --- src/mainboard/getac/p470/Kconfig | 7 +++++++ src/mainboard/getac/p470/mainboard.c | 2 ++ 2 files changed, 9 insertions(+) diff --git a/src/mainboard/getac/p470/Kconfig b/src/mainboard/getac/p470/Kconfig index 3fdc67c..2bb7aeb 100644 --- a/src/mainboard/getac/p470/Kconfig +++ b/src/mainboard/getac/p470/Kconfig @@ -38,6 +38,13 @@ config BOARD_SPECIFIC_OPTIONS # dummy select UDELAY_LAPIC select BOARD_ROMSIZE_KB_1024 select CHANNEL_XOR_RANDOMIZATION + select EARLY_CBMEM_INIT + select VGA + select MAINBOARD_HAS_NATIVE_VGA_INIT + select MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG + select MAINBOARD_DO_EDID + select INTEL_EDID + select INTEL_INT15 config MAINBOARD_DIR string diff --git a/src/mainboard/getac/p470/mainboard.c b/src/mainboard/getac/p470/mainboard.c index 6ee17a0..226b9c0 100644 --- a/src/mainboard/getac/p470/mainboard.c +++ b/src/mainboard/getac/p470/mainboard.c @@ -23,6 +23,7 @@ #include <device/pci_def.h> #include <arch/io.h> #include <delay.h> +#include <drivers/intel/gma/int15.h> #include "ec_oem.c" @@ -81,6 +82,7 @@ static void pcie_limit_power(void) static void mainboard_init(device_t dev) { ec_enable(); + install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, GMA_INT15_PANEL_FIT_TXT_STRETCH, 0, 3); } // mainboard_enable is executed as first thing after

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Patch set updated for coreboot: northbridge/gm45/raminit.c: enable GS45 high-performance mode
by Francis Rowe 08 Aug '15

08 Aug '15

Francis Rowe (info(a)gluglug.org.uk) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11135 -gerrit commit 05a4160f6f062eae1309ac01af97d592672a5f8b Author: Steve Shenton <sgsit(a)libreboot.org> Date: Fri Aug 7 08:22:27 2015 +0100 northbridge/gm45/raminit.c: enable GS45 high-performance mode The datasheets for GS45 describe a high- and low-performance mode for different CPUs. Coreboot currently disables GS45 altogether, but forcing coreboot to treat high-performance GS45 as GM45 makes the X200S and X200 Tablet boot if it has the right CPU type. Hardcode-enable GS45 high-performance mode in coreboot, passing it off as GM45. This is known to work with all CPUs except the SU (low performance) models. The low-performance models are unsupported anyway, requiring extensive work on the raminit. For now, this patch increases compatibility to a whole new chipset (GS45), depending on the CPU. Change-Id: I2719385e93c37d254ce38e0f5f486262160234e1 Signed-off-by: Steve Shenton <sgsit(a)libreboot.org> Signed-off-by: Francis Rowe <info(a)gluglug.org.uk> --- src/northbridge/intel/gm45/raminit.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/src/northbridge/intel/gm45/raminit.c b/src/northbridge/intel/gm45/raminit.c index 9c4fecd..1614b7c 100644 --- a/src/northbridge/intel/gm45/raminit.c +++ b/src/northbridge/intel/gm45/raminit.c @@ -108,8 +108,7 @@ void get_gmch_info(sysinfo_t *sysinfo) printk(BIOS_SPEW, "GMCH: GS40\n"); break; case GMCH_GS45: - printk(BIOS_SPEW, "GMCH: GS45, using low power mode by default\n"); - sysinfo->gs45_low_power_mode = 1; + printk(BIOS_SPEW, "GMCH: GS45, using high performance mode by default\n"); break; case GMCH_PM45: printk(BIOS_SPEW, "GMCH: PM45\n"); @@ -1692,7 +1691,7 @@ void raminit(sysinfo_t *const sysinfo, const int s3resume) { const dimminfo_t *const dimms = sysinfo->dimms; const timings_t *const timings = &sysinfo->selected_timings; - const int sff = sysinfo->gfx_type == GMCH_GS45; + const int sff = (sysinfo->gfx_type == GMCH_GS45) && (sysinfo->gs45_low_power_mode == 1); int ch; u8 reg8;

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Patch merged into coreboot/master: samsung/exynos5250: Enable bootblock console
by gerrit＠coreboot.org 08 Aug '15

08 Aug '15

the following patch was just integrated into master: commit 6de27da32e100729108529e5c4824d87120522ef Author: Patrick Georgi <pgeorgi(a)google.com> Date: Fri Jul 31 17:27:23 2015 +0200 samsung/exynos5250: Enable bootblock console Change-Id: I7b177b4c57f8e304167610205196ecfe4beb4fea Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> Reviewed-on: http://review.coreboot.org/11102 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/11102 for details. -gerrit

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Patch merged into coreboot/master: google/urara: Stub out get_write_protect_state()
by gerrit＠coreboot.org 08 Aug '15

08 Aug '15

the following patch was just integrated into master: commit 4d7cf0bb47f776d0952058435854069cb64cd2da Author: Patrick Georgi <pgeorgi(a)google.com> Date: Fri Jul 31 17:21:15 2015 +0200 google/urara: Stub out get_write_protect_state() vboot2 requires it Change-Id: I63bc3f176af72da8ea172a09aa536a10f1184b14 Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> Reviewed-on: http://review.coreboot.org/11099 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/11099 for details. -gerrit

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Patch merged into coreboot/master: broadcom/cygnus: returning from verstage without having one is useless
by gerrit＠coreboot.org 08 Aug '15

08 Aug '15

the following patch was just integrated into master: commit 0c02eefe2bfaff878e7c13f71daabaffd6e727f0 Author: Patrick Georgi <pgeorgi(a)google.com> Date: Fri Jul 31 17:39:03 2015 +0200 broadcom/cygnus: returning from verstage without having one is useless Change-Id: I488b74b73a7654e97958a80fa7c83258fea3e959 Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> Reviewed-on: http://review.coreboot.org/11103 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/11103 for details. -gerrit

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Patch merged into coreboot/master: abuild: avoid hanging in oldconfig for parallel builds
by gerrit＠coreboot.org 08 Aug '15

08 Aug '15

the following patch was just integrated into master: commit 1d915cae2b946561515c1309000b284f08fb8b80 Author: Patrick Georgi <pgeorgi(a)google.com> Date: Fri Jul 31 16:46:55 2015 +0200 abuild: avoid hanging in oldconfig for parallel builds oldconfig may wait for some input. Since we don't care while building tools, just provide something. Change-Id: I1c6f1b46957301886a7645cfb6c6bd264437aa7e Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> Reviewed-on: http://review.coreboot.org/11094 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/11094 for details. -gerrit

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Patch merged into coreboot/master: abuild: in junit output, name chromeos builds different from normal ones
by gerrit＠coreboot.org 08 Aug '15

08 Aug '15

the following patch was just integrated into master: commit 58474df42a2193fa3bf980e05ff2f7b092d29eae Author: Patrick Georgi <pgeorgi(a)google.com> Date: Fri Jul 31 16:30:04 2015 +0200 abuild: in junit output, name chromeos builds different from normal ones This will allow building and reporting both in one pass. Change-Id: Id7dbe63c7628cb97d9cf190c151bf23c7b264a89 Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> Reviewed-on: http://review.coreboot.org/11093 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/11093 for details. -gerrit

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Patch merged into coreboot/master: abuild: when using --chromeos, skip boards with no Chrome OS support
by gerrit＠coreboot.org 08 Aug '15

08 Aug '15

the following patch was just integrated into master: commit f43b06d0eec1f7c67f46ca35122058bae50220e8 Author: Patrick Georgi <pgeorgi(a)google.com> Date: Fri Jul 31 16:26:19 2015 +0200 abuild: when using --chromeos, skip boards with no Chrome OS support Change-Id: Ic33b9311d5f194908b0a923ef5b342bfe992bdfc Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> Reviewed-on: http://review.coreboot.org/11092 Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Tested-by: build bot (Jenkins) See http://review.coreboot.org/11092 for details. -gerrit

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coreboot-gerrit August 2015