coreboot-gerrit August 2015

coreboot-gerrit@coreboot.org

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814 discussions

Patch set updated for coreboot: UNTESTED: drivers/intel/fsp1_1/fsp_util.c: Use ALIGN_UP_macro
by Alexandru Gagniuc 31 Aug '15

31 Aug '15

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11464 -gerrit commit b4c7fb65544d90b995cc894a69d366f2fc7dffbc Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Sat Aug 29 18:25:10 2015 -0700 UNTESTED: drivers/intel/fsp1_1/fsp_util.c: Use ALIGN_UP_macro Change-Id: Iac4f275c14646b40ffe04fc5a6f6e1402cebfddf Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- src/drivers/intel/fsp1_1/fsp_util.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/drivers/intel/fsp1_1/fsp_util.c b/src/drivers/intel/fsp1_1/fsp_util.c index e5624b3..09d1286 100644 --- a/src/drivers/intel/fsp1_1/fsp_util.c +++ b/src/drivers/intel/fsp1_1/fsp_util.c @@ -51,7 +51,7 @@ FSP_INFO_HEADER *find_fsp(void) /* Locate the file header which follows the FV header. */ fsp_ptr.u8 += fsp_ptr.fvh->ExtHeaderOffset; fsp_ptr.u8 += fsp_ptr.fveh->ExtHeaderSize; - fsp_ptr.u8 = (u8 *)((fsp_ptr.u32 + 7) & 0xFFFFFFF8); + fsp_ptr.u8 = (u8 *)ALIGN_UP(fsp_ptr.u32, 0x7); /* Check the FFS GUID */ if ((((u32 *)&fsp_ptr.ffh->Name)[0] != 0x912740BE)

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Patch set updated for coreboot: UNTESTED: drivers/intel/fsp1_1: Take platform ID as a string, not integers
by Alexandru Gagniuc 31 Aug '15

31 Aug '15

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11465 -gerrit commit fafe131d3045d495f672f5e33b99a0cef22442ea Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Sat Aug 29 18:53:43 2015 -0700 UNTESTED: drivers/intel/fsp1_1: Take platform ID as a string, not integers The platform ID is an 8 character ASCII string, so our config should take it in as a string, rather than a set of two 32-bit integers. Change-Id: I76da85fab59fe4891fbc3b5edf430f2791b70ffb Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- src/drivers/intel/fsp1_1/Kconfig | 14 ++++---------- src/drivers/intel/fsp1_1/fsp_util.c | 11 +++++++++-- 2 files changed, 13 insertions(+), 12 deletions(-) diff --git a/src/drivers/intel/fsp1_1/Kconfig b/src/drivers/intel/fsp1_1/Kconfig index af5920b..2d25b04 100644 --- a/src/drivers/intel/fsp1_1/Kconfig +++ b/src/drivers/intel/fsp1_1/Kconfig @@ -50,17 +50,11 @@ config FSP_FILE help The path and filename of the Intel FSP binary for this platform. -config FSP_IMAGE_ID_DWORD0 - hex "First 4 bytes of 8 byte platform string" +config FSP_IMAGE_ID_STRING + string "8 byte platform string identtifying the FSP platform" help - The first four bytes of the eight byte platform specific string - used to identify the FSP binary that should be used. - -config FSP_IMAGE_ID_DWORD1 - hex "Second 4 bytes of 8 byte platform string" - help - The second four bytes of the eight byte platform specific string - used to identify the FSP binary that should be used. + 8 ASCII character byte signature string that will help match the FSP + binary to a supported hardware configuration. config FSP_INCLUDE_PATH string "Path for FSP specific include files" diff --git a/src/drivers/intel/fsp1_1/fsp_util.c b/src/drivers/intel/fsp1_1/fsp_util.c index 09d1286..cb58d27 100644 --- a/src/drivers/intel/fsp1_1/fsp_util.c +++ b/src/drivers/intel/fsp1_1/fsp_util.c @@ -36,6 +36,13 @@ FSP_INFO_HEADER *find_fsp(void) u8 *u8; u32 u32; } fsp_ptr; + static const union { + char str_id[8]; + u32 int_id[2]; + } fsp_id = { + .str_id = CONFIG_FSP_IMAGE_ID_STRING + }; + u32 *image_id; for (;;) { @@ -87,8 +94,8 @@ FSP_INFO_HEADER *find_fsp(void) /* Verify the FSP ID */ image_id = (u32 *)&fsp_ptr.fih->ImageId[0]; - if ((image_id[0] != CONFIG_FSP_IMAGE_ID_DWORD0) - || (image_id[1] != CONFIG_FSP_IMAGE_ID_DWORD1)) + if ((image_id[0] != fsp_id.int_id[0]) + || (image_id[1] != fsp_id.int_id[1])) fsp_ptr.u8 = (u8 *)ERROR_FSP_SIG_MISMATCH; break; }

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Patch set updated for coreboot: UNTESTED: drivers/intel/fsp1_1: Do no run microcode updates via FSP
by Alexandru Gagniuc 31 Aug '15

31 Aug '15

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11463 -gerrit commit 5e28e23e5508b40c296cf976166e5ebd59a9cb1c Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Sat Aug 29 14:34:25 2015 -0700 UNTESTED: drivers/intel/fsp1_1: Do no run microcode updates via FSP Our bootblock already upgrades the CPU microcode before any call to FSP. As a result, the FSP microcode update will be a no-op. THIS IS TRUE FOR THE BSP. UNTESTED ON APs. Since we have to pass the microcode location to FSP via a stack, before CAR, this stack exists in flash, and needs the location hardcoded. If we remove this limitation, then we no longer need to hardcode the location of the microcode, and can use the standard rules for adding microcode. DO NOT MERGE: THIS HAS NOT BEEN TESTED ON REAL HARDWARE. FSP DOCUMENTATION SAYS IT WILL NOT UPGRADE MICROCODE IF A VALID MICROCODE UPDATE IS NOT FOUND, BUT IT IS UNCLEAR IF THE FSP TempRamInit WILL FAIL OR NOT UNDER THESE CONDITIONS. NEEDSTEST. NOTFORMERGE!!!! Change-Id: I47d11061a1cfb741a633102225b63715d1bfd382 Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- src/drivers/intel/fsp1_1/Kconfig | 13 ------------- src/drivers/intel/fsp1_1/cache_as_ram.inc | 4 ++-- src/soc/intel/braswell/microcode/Makefile.inc | 11 ----------- src/soc/intel/skylake/microcode/Makefile.inc | 11 ----------- 4 files changed, 2 insertions(+), 37 deletions(-) diff --git a/src/drivers/intel/fsp1_1/Kconfig b/src/drivers/intel/fsp1_1/Kconfig index 42c42c0..af5920b 100644 --- a/src/drivers/intel/fsp1_1/Kconfig +++ b/src/drivers/intel/fsp1_1/Kconfig @@ -45,19 +45,6 @@ config HAVE_FSP_BIN if HAVE_FSP_BIN -config CPU_MICROCODE_CBFS_LEN - hex "Microcode update region length in bytes" - default 0 - help - The length in bytes of the microcode update region. - -config CPU_MICROCODE_CBFS_LOC - hex "Microcode update base address in CBFS" - default 0 - help - The location (base address) in CBFS that contains the microcode update - binary. - config FSP_FILE string "Intel FSP binary path and filename" help diff --git a/src/drivers/intel/fsp1_1/cache_as_ram.inc b/src/drivers/intel/fsp1_1/cache_as_ram.inc index 6af30ce..1d35b14 100644 --- a/src/drivers/intel/fsp1_1/cache_as_ram.inc +++ b/src/drivers/intel/fsp1_1/cache_as_ram.inc @@ -344,8 +344,8 @@ fake_fsp_stack: .long find_fsp_ret CAR_init_params: - .long CONFIG_CPU_MICROCODE_CBFS_LOC /* Microcode Location */ - .long CONFIG_CPU_MICROCODE_CBFS_LEN /* Microcode Length */ + .long 0 /* Microcode Location */ + .long 0 /* Microcode Length */ .long 0xFFFFFFFF - CONFIG_CBFS_SIZE + 1 /* Firmware Location */ .long CONFIG_CBFS_SIZE /* Total Firmware Length */ diff --git a/src/soc/intel/braswell/microcode/Makefile.inc b/src/soc/intel/braswell/microcode/Makefile.inc index da25b8b..3497328 100644 --- a/src/soc/intel/braswell/microcode/Makefile.inc +++ b/src/soc/intel/braswell/microcode/Makefile.inc @@ -1,13 +1,2 @@ # Add CPU uCode source to list of files to build. cpu_microcode-y += microcode_blob.c - -# This section overrides the default build process for the microcode to place -# it at a known location in the CBFS. This only needs to be enabled if FSP is -# being used. -# Define the correct offset for the file in CBFS -fsp_ucode_cbfs_base = $(CONFIG_CPU_MICROCODE_CBFS_LOC) - -# Override the location that was supplied by the core code. -add-cpu-microcode-to-cbfs = \ - $(CBFSTOOL) $(1) add -n $(cpu_ucode_cbfs_name) -f $(cpu_ucode_cbfs_file) -t microcode -b $(fsp_ucode_cbfs_base) - diff --git a/src/soc/intel/skylake/microcode/Makefile.inc b/src/soc/intel/skylake/microcode/Makefile.inc index a5e8981..ba308f6 100644 --- a/src/soc/intel/skylake/microcode/Makefile.inc +++ b/src/soc/intel/skylake/microcode/Makefile.inc @@ -1,13 +1,2 @@ # Add CPU uCode source to list of files to build. cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c - -# This section overrides the default build process for the microcode to place -# it at a known location in the CBFS. This only needs to be enabled if FSP is -# being used. -# Define the correct offset for the file in CBFS -fsp_ucode_cbfs_base = $(CONFIG_CPU_MICROCODE_CBFS_LOC) - -# Override the location that was supplied by the core code. -add-cpu-microcode-to-cbfs = \ - $(CBFSTOOL) $(1) add -n $(cpu_ucode_cbfs_name) -f $(cpu_ucode_cbfs_file) -t microcode -b $(fsp_ucode_cbfs_base) -

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Patch merged into coreboot/master: soc/intel/braswell/Kconfig: Remove ENABLE_MRC_CACHE Kconfig
by gerrit＠coreboot.org 31 Aug '15

31 Aug '15

the following patch was just integrated into master: commit 1cb1c924c58d952ae197ba1508d0dc7c9bfda0b4 Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Sat Aug 29 19:08:28 2015 -0700 soc/intel/braswell/Kconfig: Remove ENABLE_MRC_CACHE Kconfig This option was removed in the following commit: * 80f5d5b fsp1_1: remove duplicate mrc caching mechanism Change-Id: I08ef4fc6029cc066e4f7b9c82b6b187a9794afdb Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Reviewed-on: http://review.coreboot.org/11462 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/11462 for details. -gerrit

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Patch merged into coreboot/master: drivers/intel/fsp_1_1: Remove useless #ifndef/#error pairs
by gerrit＠coreboot.org 31 Aug '15

31 Aug '15

the following patch was just integrated into master: commit 681012ab3d500bcbda3971d122e60587133df1cd Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Sat Aug 29 17:48:01 2015 -0700 drivers/intel/fsp_1_1: Remove useless #ifndef/#error pairs The #error messages only say that "CONFIG_* must be defined", which conveys no more information that the compiler or assembler failing when it encounters an undefined CONFIG_* symbol. Change-Id: I6058474d4cd454cfc20290650425d379f388abd9 Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Reviewed-on: http://review.coreboot.org/11461 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/11461 for details. -gerrit

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New patch to review for coreboot: util/cbmem: add -T option for machine parseable timestamps
by Aaron Durbin 31 Aug '15

31 Aug '15

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11471 -gerrit commit 1c76082a750d68fb760317d491b5f01a4fb7f3d6 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Sun Aug 30 22:00:12 2015 -0500 util/cbmem: add -T option for machine parseable timestamps In order to make analysis easier provide an option (-T) to print timestamps in a parseable format: ID<tab>raw timestamp<tab>time from previous entry<tab>description BUG=chrome-os-partner:44669 BRANCH=firmware-strago-7287.B TEST=Built and tested on glados. Used the following script: cbmem -T | awk 'BEGIN { FS="\t" } { tot += $3 } END { print tot }' Change-Id: I06dc0487d1462b6a78924130f0ad74b0d787d3f8 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- util/cbmem/cbmem.c | 79 +++++++++++++++++++++++++++++++++++++++++------------- 1 file changed, 61 insertions(+), 18 deletions(-) diff --git a/util/cbmem/cbmem.c b/util/cbmem/cbmem.c index 4f3dd1f..3f89278 100644 --- a/util/cbmem/cbmem.c +++ b/util/cbmem/cbmem.c @@ -481,19 +481,42 @@ static const struct timestamp_id_to_name { { TS_FSP_AFTER_FINALIZE, "returning from FspNotify(ReadyToBoot)" } }; -uint64_t timestamp_print_entry(uint32_t id, uint64_t stamp, uint64_t prev_stamp) +static const char *timestamp_name(uint32_t id) { int i; - const char *name; - uint64_t step_time; - name = "<unknown>"; for (i = 0; i < ARRAY_SIZE(timestamp_ids); i++) { - if (timestamp_ids[i].id == id) { - name = timestamp_ids[i].name; - break; - } + if (timestamp_ids[i].id == id) + return timestamp_ids[i].name; } + return "<unknown>"; +} + +static uint64_t timestamp_print_parseable_entry(uint32_t id, uint64_t stamp, + uint64_t prev_stamp) +{ + const char *name; + uint64_t step_time; + + name = timestamp_name(id); + + step_time = arch_convert_raw_ts_entry(stamp - prev_stamp); + + /* ID<tab>absolute time<tab>relative time<tab>description */ + printf("%d\t", id); + printf("%llu\t", (long long)arch_convert_raw_ts_entry(stamp)); + printf("%llu\t", (long long)step_time); + printf("%s\n", name); + + return step_time; +} + +uint64_t timestamp_print_entry(uint32_t id, uint64_t stamp, uint64_t prev_stamp) +{ + const char *name; + uint64_t step_time; + + name = timestamp_name(id); printf("%4d:", id); printf("%-50s", name); @@ -510,7 +533,7 @@ uint64_t timestamp_print_entry(uint32_t id, uint64_t stamp, uint64_t prev_stamp) } /* dump the timestamp table */ -static void dump_timestamps(void) +static void dump_timestamps(int mach_readable) { int i; struct timestamp_table *tst_p; @@ -528,7 +551,8 @@ static void dump_timestamps(void) timestamp_set_tick_freq(tst_p->tick_freq_mhz); - printf("%d entries total:\n\n", tst_p->num_entries); + if (!mach_readable) + printf("%d entries total:\n\n", tst_p->num_entries); size += tst_p->num_entries * sizeof(tst_p->entries[0]); unmap_memory(); @@ -536,7 +560,11 @@ static void dump_timestamps(void) /* Report the base time within the table. */ prev_stamp = 0; - timestamp_print_entry(0, tst_p->base_time, prev_stamp); + if (mach_readable) + timestamp_print_parseable_entry(0, tst_p->base_time, + prev_stamp); + else + timestamp_print_entry(0, tst_p->base_time, prev_stamp); prev_stamp = tst_p->base_time; total_time = 0; @@ -546,14 +574,21 @@ static void dump_timestamps(void) /* Make all timestamps absolute. */ stamp = tse->entry_stamp + tst_p->base_time; - total_time += timestamp_print_entry(tse->entry_id, + if (mach_readable) + total_time += + timestamp_print_parseable_entry(tse->entry_id, + stamp, prev_stamp); + else + total_time += timestamp_print_entry(tse->entry_id, stamp, prev_stamp); prev_stamp = stamp; } - printf("\nTotal Time: "); - print_norm(total_time); - printf("\n"); + if (!mach_readable) { + printf("\nTotal Time: "); + print_norm(total_time); + printf("\n"); + } unmap_memory(); } @@ -918,13 +953,14 @@ static void print_version(void) static void print_usage(const char *name) { - printf("usage: %s [-cCltxVvh?]\n", name); + printf("usage: %s [-cCltTxVvh?]\n", name); printf("\n" " -c | --console: print cbmem console\n" " -C | --coverage: dump coverage information\n" " -l | --list: print cbmem table of contents\n" " -x | --hexdump: print hexdump of cbmem area\n" " -t | --timestamps: print timestamp information\n" + " -T | --parseable-timestamps: print parseable timestamps\n" " -V | --verbose: verbose (debugging) output\n" " -v | --version: print the version\n" " -h | --help: print this help\n" @@ -1055,6 +1091,7 @@ int main(int argc, char** argv) int print_list = 0; int print_hexdump = 0; int print_timestamps = 0; + int machine_readable_timestamps = 0; int opt, option_index = 0; static struct option long_options[] = { @@ -1062,13 +1099,14 @@ int main(int argc, char** argv) {"coverage", 0, 0, 'C'}, {"list", 0, 0, 'l'}, {"timestamps", 0, 0, 't'}, + {"parseable-timestamps", 0, 0, 'T'}, {"hexdump", 0, 0, 'x'}, {"verbose", 0, 0, 'V'}, {"version", 0, 0, 'v'}, {"help", 0, 0, 'h'}, {0, 0, 0, 0} }; - while ((opt = getopt_long(argc, argv, "cCltxVvh?", + while ((opt = getopt_long(argc, argv, "cCltTxVvh?", long_options, &option_index)) != EOF) { switch (opt) { case 'c': @@ -1091,6 +1129,11 @@ int main(int argc, char** argv) print_timestamps = 1; print_defaults = 0; break; + case 'T': + print_timestamps = 1; + machine_readable_timestamps = 1; + print_defaults = 0; + break; case 'V': verbose = 1; break; @@ -1190,7 +1233,7 @@ int main(int argc, char** argv) dump_cbmem_hex(); if (print_defaults || print_timestamps) - dump_timestamps(); + dump_timestamps(machine_readable_timestamps); close(mem_fd); return 0;

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New patch to review for coreboot: timestamp: add tick frequency to exported table
by Aaron Durbin 31 Aug '15

31 Aug '15

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11470 -gerrit commit a3de6e275646efafa361a64eaaca12f342f71b8c Author: Aaron Durbin <adurbin(a)chromium.org> Date: Sun Aug 30 21:19:55 2015 -0500 timestamp: add tick frequency to exported table Add the timestamp tick frequency within the timestamp table so the cbmem utility doesn't try to figure it out on its own. Those paths still exist for x86 systems which don't provide tsc_freq_mhz(). All other non-x86 systems use the monotonic timer which has a 1us granularity or 1MHz. One of the main reasons is that Linux is reporting /sys/devices/system/cpu/cpu0/cpufreq/cpuinfo_max_freq as the true turbo frequency on turbo enables machines. This change also fixes the p-state values honored in cpufreq for turbo machines in that turbo p-pstates were reported as 100MHz greater than nominal. BUG=chrome-os-partner:44669 BRANCH=firmware-strago-7287.B TEST=Built and booted on glados. Confirmed table frequency honored. Change-Id: I763fe2d9a7b01d0ef5556e5abff36032062f5801 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/arch/x86/timestamp.c | 13 +++++++++++ src/include/cpu/x86/tsc.h | 3 +-- src/include/timestamp.h | 5 ++++- src/lib/timestamp.c | 10 +++++++++ util/cbmem/cbmem.c | 57 ++++++++++++++++++++++++++--------------------- 5 files changed, 60 insertions(+), 28 deletions(-) diff --git a/src/arch/x86/timestamp.c b/src/arch/x86/timestamp.c index 9df505a..d308146 100644 --- a/src/arch/x86/timestamp.c +++ b/src/arch/x86/timestamp.c @@ -24,3 +24,16 @@ uint64_t timestamp_get(void) { return rdtscll(); } + +unsigned long __attribute__((weak)) tsc_freq_mhz(void) +{ + /* Default to not knowing TSC frequency. cbmem will have to fallback + * on trying to determine it in userspace. */ + return 0; +} + +int timestamp_tick_freq_mhz(void) +{ + /* Chipsets that have a constant TSC provide this value correctly. */ + return tsc_freq_mhz(); +} diff --git a/src/include/cpu/x86/tsc.h b/src/include/cpu/x86/tsc.h index 71d253b..5cf4644 100644 --- a/src/include/cpu/x86/tsc.h +++ b/src/include/cpu/x86/tsc.h @@ -60,8 +60,7 @@ static inline uint64_t tsc_to_uint64(tsc_t tstamp) } #endif -#if CONFIG_TSC_CONSTANT_RATE +/* Provided by CPU/chipset code for the TSC rate in MHz. */ unsigned long tsc_freq_mhz(void); -#endif #endif /* CPU_X86_TSC_H */ diff --git a/src/include/timestamp.h b/src/include/timestamp.h index 54d69ce..be33b0a 100644 --- a/src/include/timestamp.h +++ b/src/include/timestamp.h @@ -29,7 +29,8 @@ struct timestamp_entry { struct timestamp_table { uint64_t base_time; - uint32_t max_entries; + uint16_t max_entries; + uint16_t tick_freq_mhz; uint32_t num_entries; struct timestamp_entry entries[0]; /* Variable number of entries */ } __attribute__((packed)); @@ -114,5 +115,7 @@ void timestamp_add_now(enum timestamp_id id); /* Implemented by the architecture code */ uint64_t timestamp_get(void); uint64_t get_initial_timestamp(void); +/* Returns timestamp tick frequency in MHz. */ +int timestamp_tick_freq_mhz(void); #endif diff --git a/src/lib/timestamp.c b/src/lib/timestamp.c index ca25093..21b3d29 100644 --- a/src/lib/timestamp.c +++ b/src/lib/timestamp.c @@ -278,6 +278,10 @@ static void timestamp_sync_cache_to_cbmem(int is_recovery) if (ts_cbmem_table->base_time == 0) ts_cbmem_table->base_time = ts_cache_table->base_time; + /* Seed the timestamp tick frequency in ramstage. */ + if (ENV_RAMSTAGE) + ts_cbmem_table->tick_freq_mhz = timestamp_tick_freq_mhz(); + /* Cache no longer required. */ ts_cache_table->num_entries = 0; ts_cache->cache_state = TIMESTAMP_CACHE_NOT_NEEDED; @@ -299,3 +303,9 @@ uint64_t __attribute__((weak)) timestamp_get(void) return mono_time_diff_microseconds(&t1, &t2); } + +/* Like timestamp_get() above this matches up with microsecond granularity. */ +int __attribute__((weak)) timestamp_tick_freq_mhz(void) +{ + return 1; +} diff --git a/util/cbmem/cbmem.c b/util/cbmem/cbmem.c index 6526384..4f3dd1f 100644 --- a/util/cbmem/cbmem.c +++ b/util/cbmem/cbmem.c @@ -304,7 +304,7 @@ static int parse_cbtable(u64 address, size_t table_size) * read CPU frequency from a sysfs file, return an frequency in Kilohertz as * an int or exit on any error. */ -static u64 get_cpu_freq_KHz(void) +static unsigned long arch_tick_frquency(void) { FILE *cpuf; char freqs[100]; @@ -338,44 +338,49 @@ static u64 get_cpu_freq_KHz(void) freqs, freq_file); exit(1); } - -/* On x86 platforms timestamps are stored - * in CPU cycles (from rdtsc). Hence the - * timestamp divider is the CPU frequency - * in MHz. - */ -u64 arch_convert_raw_ts_entry(u64 ts) -{ - static u64 cpu_freq_mhz = 0; - - if (!cpu_freq_mhz) - cpu_freq_mhz = get_cpu_freq_KHz() / 1000; - - return ts / cpu_freq_mhz; -} - #elif defined(__OpenBSD__) && (defined(__i386__) || defined(__x86_64__)) -u64 arch_convert_raw_ts_entry(u64 ts) +static unsigned long arch_tick_frquency(void) { int mib[2] = { CTL_HW, HW_CPUSPEED }; static int value = 0; size_t value_len = sizeof(value); + /* Return 1 MHz when sysctl fails. */ if ((value == 0) && (sysctl(mib, 2, &value, &value_len, NULL, 0) == -1)) - return ts; + return 1; - return ts / value; + return value; } #else +static unsigned long arch_tick_frquency(void) +{ + /* 1 MHz = 1us. */ + return 1; +} +#endif + +static unsigned long tick_freq_mhz; + +static void timestamp_set_tick_freq(unsigned long table_tick_freq_mhz) +{ + tick_freq_mhz = table_tick_freq_mhz; + + /* Honor table frequency. */ + if (tick_freq_mhz) + return; + + tick_freq_mhz = arch_tick_frquency(); + + if (!tick_freq_mhz) { + fprintf(stderr, "Cannot determine timestamp tick frequency.\n"); + exit(1); + } +} -/* On non-x86 platforms the timestamp entries - * are not in clock cycles but in usecs - */ u64 arch_convert_raw_ts_entry(u64 ts) { - return ts; + return ts / tick_freq_mhz; } -#endif /* * Print an integer in 'normalized' form - with commas separating every three @@ -521,6 +526,8 @@ static void dump_timestamps(void) size = sizeof(*tst_p); tst_p = map_memory_size((unsigned long)timestamps.cbmem_addr, size); + timestamp_set_tick_freq(tst_p->tick_freq_mhz); + printf("%d entries total:\n\n", tst_p->num_entries); size += tst_p->num_entries * sizeof(tst_p->entries[0]);

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New patch to review for coreboot: imgtec/pistachio: remove timestamp_get() implementation
by Aaron Durbin 31 Aug '15

31 Aug '15

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11469 -gerrit commit 1ebf4f876c34c60db4ac9c8b82363d5753dcb611 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Sun Aug 30 16:04:13 2015 -0500 imgtec/pistachio: remove timestamp_get() implementation As pistachio already provides timer_monotonic_get() let the generic timestamp_get() use that instead of having around another implementation of timestamp_get(). BUG=chrome-os-partner:44669 BRANCH=None TEST=None Change-Id: Iaa6db49f0055b7c2ef116f41453f838093e516e0 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/soc/imgtec/pistachio/monotonic_timer.c | 7 +------ 1 file changed, 1 insertion(+), 6 deletions(-) diff --git a/src/soc/imgtec/pistachio/monotonic_timer.c b/src/soc/imgtec/pistachio/monotonic_timer.c index 4f3aba9..0d74ae5 100644 --- a/src/soc/imgtec/pistachio/monotonic_timer.c +++ b/src/soc/imgtec/pistachio/monotonic_timer.c @@ -53,10 +53,5 @@ static int get_count_mhz_freq(void) void timer_monotonic_get(struct mono_time *mt) { - mt->microseconds = (long)timestamp_get(); -} - -uint64_t timestamp_get(void) -{ - return read_c0_count()/get_count_mhz_freq(); + mono_time_set_usecs(mt, read_c0_count() / get_count_mhz_freq()); }

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New patch to review for coreboot: armv7/arm64: remove timestamp.c
by Aaron Durbin 31 Aug '15

31 Aug '15

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11468 -gerrit commit 8559b9328f77a7e9eb8811c21e4c9133581a1e33 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Sun Aug 30 15:41:54 2015 -0500 armv7/arm64: remove timestamp.c The src/lib/timestamp.c already has an implementation using timer_monotonic_get() for timestamp_get(). Use that instead of duplicating the logic. BUG=chrome-os-partner:44669 BRANCH=None TEST=None Change-Id: If17be86143f217445bd64d67ceee4355fa482d39 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/arch/arm/armv7/Makefile.inc | 6 ------ src/arch/arm/armv7/timestamp.c | 28 ---------------------------- src/arch/arm64/Makefile.inc | 5 ----- src/arch/arm64/timestamp.c | 28 ---------------------------- 4 files changed, 67 deletions(-) diff --git a/src/arch/arm/armv7/Makefile.inc b/src/arch/arm/armv7/Makefile.inc index a46ef87..089ef79 100644 --- a/src/arch/arm/armv7/Makefile.inc +++ b/src/arch/arm/armv7/Makefile.inc @@ -59,8 +59,6 @@ bootblock-y += cache_m.c endif # CONFIG_ARCH_BOOTBLOCK_ARMV7 -bootblock-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c - ################################################################################ ## verification stage ################################################################################ @@ -85,8 +83,6 @@ verstage-S-ccopts += $(armv7-m_asm_flags) endif # CONFIG_ARCH_VERSTAGE_ARMV7_M -verstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c - ################################################################################ ## ROM stage ################################################################################ @@ -96,7 +92,6 @@ romstage-y += cpu.S romstage-y += exception.c romstage-y += exception_asm.S romstage-y += mmu.c -romstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c romstage-c-ccopts += $(armv7-a_flags) romstage-S-ccopts += $(armv7-a_asm_flags) @@ -117,7 +112,6 @@ ramstage-y += cpu.S ramstage-y += exception.c ramstage-y += exception_asm.S ramstage-y += mmu.c -ramstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c ramstage-c-ccopts += $(armv7-a_flags) ramstage-S-ccopts += $(armv7-a_asm_flags) diff --git a/src/arch/arm/armv7/timestamp.c b/src/arch/arm/armv7/timestamp.c deleted file mode 100644 index 1b3138f..0000000 --- a/src/arch/arm/armv7/timestamp.c +++ /dev/null @@ -1,28 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2013 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc. - */ - -#include <timestamp.h> -#include <timer.h> - -uint64_t timestamp_get(void) -{ - struct mono_time timestamp; - timer_monotonic_get(&timestamp); - return (uint64_t)timestamp.microseconds; -} diff --git a/src/arch/arm64/Makefile.inc b/src/arch/arm64/Makefile.inc index 3e14f8b..a625c7a 100644 --- a/src/arch/arm64/Makefile.inc +++ b/src/arch/arm64/Makefile.inc @@ -64,7 +64,6 @@ bootblock-y += cpu-stubs.c bootblock-y += stages.c bootblock-y += eabi_compat.c bootblock-y += transition.c transition_asm.S -bootblock-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c bootblock-y += memset.S bootblock-y += memcpy.S @@ -95,7 +94,6 @@ verstage-y += ../../lib/memset.c verstage-y += ../../lib/memcpy.c verstage-y += ../../lib/memmove.c verstage-y += stages.c -verstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c endif # CONFIG_ARCH_VERSTAGE_ARM64 @@ -115,7 +113,6 @@ romstage-y += eabi_compat.c romstage-y += memset.S romstage-y += memcpy.S romstage-y += memmove.S -romstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c romstage-y += transition.c transition_asm.S rmodules_arm64-y += memset.S @@ -169,8 +166,6 @@ secmon-y += memset.S secmon-y += memmove.S secmon-y += memcpy.S -ramstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c - ramstage-srcs += $(wildcard src/mainboard/$(MAINBOARDDIR)/mainboard.c) # Build the ramstage diff --git a/src/arch/arm64/timestamp.c b/src/arch/arm64/timestamp.c deleted file mode 100644 index 2962c7f..0000000 --- a/src/arch/arm64/timestamp.c +++ /dev/null @@ -1,28 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc. - */ - -#include <timestamp.h> -#include <timer.h> - -uint64_t timestamp_get(void) -{ - struct mono_time timestamp; - timer_monotonic_get(&timestamp); - return (uint64_t)timestamp.microseconds; -}

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Patch set updated for coreboot: southbridge/ibexpeak: use new ssdt sata port generator
by Alexander Couzens 31 Aug '15

31 Aug '15

Alexander Couzens (lynxis(a)fe80.eu) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9710 -gerrit commit 92580ad288a4301b40a4c62e1cd2a8aae363fdbe Author: Alexander Couzens <lynxis(a)fe80.eu> Date: Thu Apr 16 02:23:00 2015 +0200 southbridge/ibexpeak: use new ssdt sata port generator Drop old incomplete, broken and hardcoded sata.asl properties. The new sata acpi generator only needs a proper defined device. Change-Id: Id3eca5551a070dfdd6fa674e1d5b6627e28ab5a7 Signed-off-by: Alexander Couzens <lynxis(a)fe80.eu> --- src/southbridge/intel/ibexpeak/Kconfig | 1 + src/southbridge/intel/ibexpeak/sata.c | 7 +++++++ 2 files changed, 8 insertions(+) diff --git a/src/southbridge/intel/ibexpeak/Kconfig b/src/southbridge/intel/ibexpeak/Kconfig index ccd16bf..f31f83c 100644 --- a/src/southbridge/intel/ibexpeak/Kconfig +++ b/src/southbridge/intel/ibexpeak/Kconfig @@ -35,6 +35,7 @@ config SOUTH_BRIDGE_OPTIONS # dummy select SOUTHBRIDGE_INTEL_COMMON select HAVE_USBDEBUG_OPTIONS select COMMON_FADT + select ACPI_SATA_GENERATOR config EHCI_BAR hex diff --git a/src/southbridge/intel/ibexpeak/sata.c b/src/southbridge/intel/ibexpeak/sata.c index 29d9240..be2b961 100644 --- a/src/southbridge/intel/ibexpeak/sata.c +++ b/src/southbridge/intel/ibexpeak/sata.c @@ -26,6 +26,7 @@ #include <device/pci_ids.h> #include "pch.h" #include <pc80/mc146818rtc.h> +#include <acpi/sata.h> typedef struct southbridge_intel_ibexpeak_config config_t; @@ -249,6 +250,11 @@ static void sata_set_subsystem(device_t dev, unsigned vendor, unsigned device) } } +static void sata_fill_ssdt(device_t dev) { + config_t *config = dev->chip_info; + generate_sata_ssdt_ports("\\_SB_.PCI0.SATA", config->sata_port_map); +} + static struct pci_operations sata_pci_ops = { .set_subsystem = sata_set_subsystem, }; @@ -259,6 +265,7 @@ static struct device_operations sata_ops = { .enable_resources = pci_dev_enable_resources, .init = sata_init, .enable = sata_enable, + .acpi_fill_ssdt_generator = sata_fill_ssdt, .scan_bus = 0, .ops_pci = &sata_pci_ops, };

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coreboot-gerrit August 2015