coreboot-gerrit August 2015

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: southbridge/bd82x6x: use new ssdt sata port generator
by Alexander Couzens 31 Aug '15

31 Aug '15

Alexander Couzens (lynxis(a)fe80.eu) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/9709 -gerrit commit 14e85cc0776442694be54702500b79b4c09bec68 Author: Alexander Couzens <lynxis(a)fe80.eu> Date: Thu Apr 16 02:00:21 2015 +0200 southbridge/bd82x6x: use new ssdt sata port generator Drop old incomplete, broken and hardcoded sata.asl properties. The new sata acpi generator only needs a proper defined device. Change-Id: I2be76097ebd27f2529e3fbbecefd314a0eea3cb0 Signed-off-by: Alexander Couzens <lynxis(a)fe80.eu> --- src/southbridge/intel/bd82x6x/Kconfig | 1 + src/southbridge/intel/bd82x6x/acpi/sata.asl | 52 ----------------------------- src/southbridge/intel/bd82x6x/sata.c | 8 +++++ 3 files changed, 9 insertions(+), 52 deletions(-) diff --git a/src/southbridge/intel/bd82x6x/Kconfig b/src/southbridge/intel/bd82x6x/Kconfig index 6190879..3a68fec 100644 --- a/src/southbridge/intel/bd82x6x/Kconfig +++ b/src/southbridge/intel/bd82x6x/Kconfig @@ -37,6 +37,7 @@ config SOUTH_BRIDGE_OPTIONS # dummy select PCIEXP_COMMON_CLOCK select SPI_FLASH select COMMON_FADT + select ACPI_SATA_GENERATOR config EHCI_BAR hex diff --git a/src/southbridge/intel/bd82x6x/acpi/sata.asl b/src/southbridge/intel/bd82x6x/acpi/sata.asl index fb685a3..00d3010 100644 --- a/src/southbridge/intel/bd82x6x/acpi/sata.asl +++ b/src/southbridge/intel/bd82x6x/acpi/sata.asl @@ -26,56 +26,4 @@ Device (SATA) { Name (_ADR, 0x001f0002) - - Device (PRID) - { - Name (_ADR, 0) - - // Get Timing Mode - Method (_GTM) - { - Name(PBUF, Buffer(20) { - 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x00,0x00,0x00,0x00 }) - - CreateDwordField (PBUF, 0, PIO0) - CreateDwordField (PBUF, 4, DMA0) - CreateDwordField (PBUF, 8, PIO1) - CreateDwordField (PBUF, 12, DMA1) - CreateDwordField (PBUF, 16, FLAG) - - // TODO fill return structure - - Return (PBUF) - } - - // Set Timing Mode - Method (_STM, 3) - { - CreateDwordField (Arg0, 0, PIO0) - CreateDwordField (Arg0, 4, DMA0) - CreateDwordField (Arg0, 8, PIO1) - CreateDwordField (Arg0, 12, DMA1) - CreateDwordField (Arg0, 16, FLAG) - - // TODO: Do the deed - } - - Device (DSK0) - { - Name (_ADR, 0) - // TODO: _RMV ? - // TODO: _GTF ? - } - - Device (DSK1) - { - Name (_ADR, 1) - - // TODO: _RMV ? - // TODO: _GTF ? - } - - } } diff --git a/src/southbridge/intel/bd82x6x/sata.c b/src/southbridge/intel/bd82x6x/sata.c index 1cdc5e2..18e5a08 100644 --- a/src/southbridge/intel/bd82x6x/sata.c +++ b/src/southbridge/intel/bd82x6x/sata.c @@ -25,6 +25,7 @@ #include <device/pci_ids.h> #include "pch.h" #include <pc80/mc146818rtc.h> +#include <acpi/sata.h> typedef struct southbridge_intel_bd82x6x_config config_t; @@ -247,6 +248,11 @@ static void sata_set_subsystem(device_t dev, unsigned vendor, unsigned device) } } +static void sata_fill_ssdt(device_t dev) { + config_t *config = dev->chip_info; + generate_sata_ssdt_ports("\\_SB_.PCI0.SATA", config->sata_port_map); +} + static struct pci_operations sata_pci_ops = { .set_subsystem = sata_set_subsystem, }; @@ -255,6 +261,8 @@ static struct device_operations sata_ops = { .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, + .acpi_fill_ssdt_generator + = sata_fill_ssdt, .init = sata_init, .enable = sata_enable, .scan_bus = 0,

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New patch to review for coreboot: SeaBios: add stable release 1.8.2 as default SeaBios version
by Alexander Couzens 31 Aug '15

31 Aug '15

Alexander Couzens (lynxis(a)fe80.eu) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11467 -gerrit commit e57f042b1a29da3027f344acc0e0bc3336c9b3e3 Author: Alexander Couzens <lynxis(a)fe80.eu> Date: Mon Aug 31 03:27:08 2015 +0200 SeaBios: add stable release 1.8.2 as default SeaBios version 1.8 is a stable release and gains several fixes. The old stable release will be still available. Change-Id: I6c61490d25927128f53f2dcac733fcb4dba8ca94 Signed-off-by: Alexander Couzens <lynxis(a)fe80.eu> --- payloads/external/Makefile.inc | 1 + payloads/external/SeaBIOS/Kconfig | 6 +++++- payloads/external/SeaBIOS/Makefile.inc | 1 + 3 files changed, 7 insertions(+), 1 deletion(-) diff --git a/payloads/external/Makefile.inc b/payloads/external/Makefile.inc index f34223b..be4d5c4 100644 --- a/payloads/external/Makefile.inc +++ b/payloads/external/Makefile.inc @@ -54,6 +54,7 @@ seabios: AS="$(AS_x86_32)" IASL="$(IASL)" \ CONFIG_SEABIOS_MASTER=$(CONFIG_SEABIOS_MASTER) \ CONFIG_SEABIOS_1_7=$(CONFIG_SEABIOS_1_7) \ + CONFIG_SEABIOS_1_8=$(CONFIG_SEABIOS_1_8) \ CONFIG_SEABIOS_THREAD_OPTIONROMS=$(CONFIG_SEABIOS_THREAD_OPTIONROMS) \ CONFIG_SEABIOS_VGA_COREBOOT=$(CONFIG_SEABIOS_VGA_COREBOOT) \ CONFIG_CONSOLE_SERIAL=$(CONFIG_CONSOLE_SERIAL) \ diff --git a/payloads/external/SeaBIOS/Kconfig b/payloads/external/SeaBIOS/Kconfig index 5467c1a..40fe70b 100644 --- a/payloads/external/SeaBIOS/Kconfig +++ b/payloads/external/SeaBIOS/Kconfig @@ -2,12 +2,16 @@ if PAYLOAD_SEABIOS choice prompt "SeaBIOS version" - default SEABIOS_1_7 + default SEABIOS_1_8 config SEABIOS_1_7 bool "1.7.5" help Stable SeaBIOS version +config SEABIOS_1_8 + bool "1.8.2" + help + Stable SeaBIOS version config SEABIOS_MASTER bool "master" help diff --git a/payloads/external/SeaBIOS/Makefile.inc b/payloads/external/SeaBIOS/Makefile.inc index 2ccd181..642128c 100644 --- a/payloads/external/SeaBIOS/Makefile.inc +++ b/payloads/external/SeaBIOS/Makefile.inc @@ -1,5 +1,6 @@ TAG-$(CONFIG_SEABIOS_MASTER)=origin/master TAG-$(CONFIG_SEABIOS_1_7)=e51488c5f8800a52ac5c8da7a31b85cca5cc95d2 +TAG-$(CONFIG_SEABIOS_1_8)=33fbe13a3e2a01e0ba1087a8feed801a0451db21 unexport KCONFIG_AUTOHEADER unexport KCONFIG_AUTOCONFIG

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New patch to review for coreboot: SeaBios: rename config symbol SEABIOS_STABLE into SEABIOS_1_7
by Alexander Couzens 31 Aug '15

31 Aug '15

Alexander Couzens (lynxis(a)fe80.eu) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11466 -gerrit commit cdd81ca5caeddd32cc633276150e4861a84c8a26 Author: Alexander Couzens <lynxis(a)fe80.eu> Date: Mon Aug 31 03:21:42 2015 +0200 SeaBios: rename config symbol SEABIOS_STABLE into SEABIOS_1_7 This makes it's possible to choose a specific version even when the seabios stable version is moving to a new stable release. Change-Id: I3d4914f953d47d54f1babe34da862b6163f900c3 Signed-off-by: Alexander Couzens <lynxis(a)fe80.eu> --- payloads/external/Makefile.inc | 2 +- payloads/external/SeaBIOS/Kconfig | 4 ++-- payloads/external/SeaBIOS/Makefile.inc | 2 +- 3 files changed, 4 insertions(+), 4 deletions(-) diff --git a/payloads/external/Makefile.inc b/payloads/external/Makefile.inc index 4bda38a..f34223b 100644 --- a/payloads/external/Makefile.inc +++ b/payloads/external/Makefile.inc @@ -53,7 +53,7 @@ seabios: OBJCOPY="$(OBJCOPY_x86_32)" STRIP="$(STRIP_x86_32)" \ AS="$(AS_x86_32)" IASL="$(IASL)" \ CONFIG_SEABIOS_MASTER=$(CONFIG_SEABIOS_MASTER) \ - CONFIG_SEABIOS_STABLE=$(CONFIG_SEABIOS_STABLE) \ + CONFIG_SEABIOS_1_7=$(CONFIG_SEABIOS_1_7) \ CONFIG_SEABIOS_THREAD_OPTIONROMS=$(CONFIG_SEABIOS_THREAD_OPTIONROMS) \ CONFIG_SEABIOS_VGA_COREBOOT=$(CONFIG_SEABIOS_VGA_COREBOOT) \ CONFIG_CONSOLE_SERIAL=$(CONFIG_CONSOLE_SERIAL) \ diff --git a/payloads/external/SeaBIOS/Kconfig b/payloads/external/SeaBIOS/Kconfig index 699b986..5467c1a 100644 --- a/payloads/external/SeaBIOS/Kconfig +++ b/payloads/external/SeaBIOS/Kconfig @@ -2,9 +2,9 @@ if PAYLOAD_SEABIOS choice prompt "SeaBIOS version" - default SEABIOS_STABLE + default SEABIOS_1_7 -config SEABIOS_STABLE +config SEABIOS_1_7 bool "1.7.5" help Stable SeaBIOS version diff --git a/payloads/external/SeaBIOS/Makefile.inc b/payloads/external/SeaBIOS/Makefile.inc index 7fb63d4..2ccd181 100644 --- a/payloads/external/SeaBIOS/Makefile.inc +++ b/payloads/external/SeaBIOS/Makefile.inc @@ -1,5 +1,5 @@ TAG-$(CONFIG_SEABIOS_MASTER)=origin/master -TAG-$(CONFIG_SEABIOS_STABLE)=e51488c5f8800a52ac5c8da7a31b85cca5cc95d2 +TAG-$(CONFIG_SEABIOS_1_7)=e51488c5f8800a52ac5c8da7a31b85cca5cc95d2 unexport KCONFIG_AUTOHEADER unexport KCONFIG_AUTOCONFIG

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Patch merged into coreboot/master: inteltool: Add Intel 4-Series chipset detection
by gerrit＠coreboot.org 30 Aug '15

30 Aug '15

the following patch was just integrated into master: commit 9c98664480de39ecd9d615dc46d34a63aedd4280 Author: Damien Zammit <damien(a)zamaudio.com> Date: Mon Aug 17 21:04:41 2015 +1000 inteltool: Add Intel 4-Series chipset detection Previously, X4X was incorrectly named because it provides support for SKUs within XX4X range. This is renamed. This patch provides support for all X4X SKUs according to datasheet Intel 4 Series Chipset Family Specification Update, namely: Q45, Q43, P45, P43, G45, G43, G41 and B43 (both versions). Tested on Gigabyte GA-G41M-ES2L Change-Id: I032265e80d9ca51e2fef29201280832ea3210a0b Signed-off-by: Damien Zammit <damien(a)zamaudio.com> Reviewed-on: http://review.coreboot.org/11245 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> See http://review.coreboot.org/11245 for details. -gerrit

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Patch merged into coreboot/master: Kconfig: Remove EXPERT mode
by gerrit＠coreboot.org 30 Aug '15

30 Aug '15

the following patch was just integrated into master: commit fdbc1af5e2c43ef223cc11ff98ee970423ae7797 Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Wed Aug 26 10:11:02 2015 -0400 Kconfig: Remove EXPERT mode After much consideration, and many years of an EXPERT mode sitting almost completely unused, we've seen that it doesn't work for us. There is no standard on what constitutes EXPERT, and most of coreboot's options Kconfig are expert-level. We even joked that not selecting "EXPERT" should prevent coreboot from compiling: @echo $(shell whoami) is not permitted to compile coreboot Change-Id: Ic22dd54a48190b81d711625efb6b9f3078f41778 Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Reviewed-on: http://review.coreboot.org/11365 Tested-by: build bot (Jenkins) Reviewed-by: Alexander Couzens <lynxis(a)fe80.eu> See http://review.coreboot.org/11365 for details. -gerrit

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Patch merged into coreboot/master: Kconfig: Don't 'select' options based on PAYLOAD_SEABIOS
by gerrit＠coreboot.org 30 Aug '15

30 Aug '15

the following patch was just integrated into master: commit 4093148b260116ca8629ff9f7e335b4384247bd7 Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Thu Aug 20 16:25:02 2015 -0400 Kconfig: Don't 'select' options based on PAYLOAD_SEABIOS This is just wrong. PAYLOAD_SEABIOS tells us nothing about whether or not the payload will actually be SeaBIOS: 1. PAYLOAD_SEABIOS, but payload changed with cbfstool 2. !PAYLOAD_SEABIOS, but an elf payload was added which is SeaBIOS et. cetera. Change-Id: I4c17e8dde20bf21537f542fda2dad7d3a1894862 Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Reviewed-on: http://review.coreboot.org/11293 Tested-by: build bot (Jenkins) Reviewed-by: Alexander Couzens <lynxis(a)fe80.eu> Reviewed-by: Damien Zammit <damien(a)zamaudio.com> See http://review.coreboot.org/11293 for details. -gerrit

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New patch to review for coreboot: UNTESTED: drivers/intel/fsp1_1: Take platform ID as a string, not integers
by Alexandru Gagniuc 30 Aug '15

30 Aug '15

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11465 -gerrit commit 54572eaeed24c5f257ac4209a99e148b4e3ffd39 Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Sat Aug 29 18:53:43 2015 -0700 UNTESTED: drivers/intel/fsp1_1: Take platform ID as a string, not integers The platform ID is an 8 character ASCII string, so our config should take it in as a string, rather than a set of two 32-bit integers. Change-Id: I76da85fab59fe4891fbc3b5edf430f2791b70ffb Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- src/drivers/intel/fsp1_1/Kconfig | 14 ++++---------- src/drivers/intel/fsp1_1/fsp_util.c | 11 +++++++++-- 2 files changed, 13 insertions(+), 12 deletions(-) diff --git a/src/drivers/intel/fsp1_1/Kconfig b/src/drivers/intel/fsp1_1/Kconfig index af5920b..2d25b04 100644 --- a/src/drivers/intel/fsp1_1/Kconfig +++ b/src/drivers/intel/fsp1_1/Kconfig @@ -50,17 +50,11 @@ config FSP_FILE help The path and filename of the Intel FSP binary for this platform. -config FSP_IMAGE_ID_DWORD0 - hex "First 4 bytes of 8 byte platform string" +config FSP_IMAGE_ID_STRING + string "8 byte platform string identtifying the FSP platform" help - The first four bytes of the eight byte platform specific string - used to identify the FSP binary that should be used. - -config FSP_IMAGE_ID_DWORD1 - hex "Second 4 bytes of 8 byte platform string" - help - The second four bytes of the eight byte platform specific string - used to identify the FSP binary that should be used. + 8 ASCII character byte signature string that will help match the FSP + binary to a supported hardware configuration. config FSP_INCLUDE_PATH string "Path for FSP specific include files" diff --git a/src/drivers/intel/fsp1_1/fsp_util.c b/src/drivers/intel/fsp1_1/fsp_util.c index 09d1286..cb58d27 100644 --- a/src/drivers/intel/fsp1_1/fsp_util.c +++ b/src/drivers/intel/fsp1_1/fsp_util.c @@ -36,6 +36,13 @@ FSP_INFO_HEADER *find_fsp(void) u8 *u8; u32 u32; } fsp_ptr; + static const union { + char str_id[8]; + u32 int_id[2]; + } fsp_id = { + .str_id = CONFIG_FSP_IMAGE_ID_STRING + }; + u32 *image_id; for (;;) { @@ -87,8 +94,8 @@ FSP_INFO_HEADER *find_fsp(void) /* Verify the FSP ID */ image_id = (u32 *)&fsp_ptr.fih->ImageId[0]; - if ((image_id[0] != CONFIG_FSP_IMAGE_ID_DWORD0) - || (image_id[1] != CONFIG_FSP_IMAGE_ID_DWORD1)) + if ((image_id[0] != fsp_id.int_id[0]) + || (image_id[1] != fsp_id.int_id[1])) fsp_ptr.u8 = (u8 *)ERROR_FSP_SIG_MISMATCH; break; }

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New patch to review for coreboot: UNTESTED: drivers/intel/fsp1_1/fsp_util.c: Use ALIGN_UP_macro
by Alexandru Gagniuc 30 Aug '15

30 Aug '15

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11464 -gerrit commit 5f17d99607aa0bcd725f6e78eaab696478621e3d Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Sat Aug 29 18:25:10 2015 -0700 UNTESTED: drivers/intel/fsp1_1/fsp_util.c: Use ALIGN_UP_macro Change-Id: Iac4f275c14646b40ffe04fc5a6f6e1402cebfddf Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- src/drivers/intel/fsp1_1/fsp_util.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/drivers/intel/fsp1_1/fsp_util.c b/src/drivers/intel/fsp1_1/fsp_util.c index e5624b3..09d1286 100644 --- a/src/drivers/intel/fsp1_1/fsp_util.c +++ b/src/drivers/intel/fsp1_1/fsp_util.c @@ -51,7 +51,7 @@ FSP_INFO_HEADER *find_fsp(void) /* Locate the file header which follows the FV header. */ fsp_ptr.u8 += fsp_ptr.fvh->ExtHeaderOffset; fsp_ptr.u8 += fsp_ptr.fveh->ExtHeaderSize; - fsp_ptr.u8 = (u8 *)((fsp_ptr.u32 + 7) & 0xFFFFFFF8); + fsp_ptr.u8 = (u8 *)ALIGN_UP(fsp_ptr.u32, 0x7); /* Check the FFS GUID */ if ((((u32 *)&fsp_ptr.ffh->Name)[0] != 0x912740BE)

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New patch to review for coreboot: UNTESTED: drivers/intel/fsp1_1: Do no run microcode updates via FSP
by Alexandru Gagniuc 30 Aug '15

30 Aug '15

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11463 -gerrit commit f8b3cbfb4284fa5a867533cfc04e1b78e46956e8 Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Sat Aug 29 14:34:25 2015 -0700 UNTESTED: drivers/intel/fsp1_1: Do no run microcode updates via FSP Our bootblock already upgrades the CPU microcode before any call to FSP. As a result, the FSP microcode update will be a no-op. THIS IS TRUE FOR THE BSP. UNTESTED ON APs. Since we have to pass the microcode location to FSP via a stack, before CAR, this stack exists in flash, and needs the location hardcoded. If we remove this limitation, then we no longer need to hardcode the location of the microcode, and can use the standard rules for adding microcode. DO NOT MERGE: THIS HAS NOT BEEN TESTED ON REAL HARDWARE. FSP DOCUMENTATION SAYS IT WILL NOT UPGRADE MICROCODE IF A VALID MICROCODE UPDATE IS NOT FOUND, BUT IT IS UNCLEAR IF THE FSP TempRamInit WILL FAIL OR NOT UNDER THESE CONDITIONS. NEEDSTEST. NOTFORMERGE!!!! Change-Id: I47d11061a1cfb741a633102225b63715d1bfd382 Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- src/drivers/intel/fsp1_1/Kconfig | 13 ------------- src/drivers/intel/fsp1_1/cache_as_ram.inc | 4 ++-- src/soc/intel/braswell/microcode/Makefile.inc | 11 ----------- src/soc/intel/skylake/microcode/Makefile.inc | 11 ----------- 4 files changed, 2 insertions(+), 37 deletions(-) diff --git a/src/drivers/intel/fsp1_1/Kconfig b/src/drivers/intel/fsp1_1/Kconfig index 42c42c0..af5920b 100644 --- a/src/drivers/intel/fsp1_1/Kconfig +++ b/src/drivers/intel/fsp1_1/Kconfig @@ -45,19 +45,6 @@ config HAVE_FSP_BIN if HAVE_FSP_BIN -config CPU_MICROCODE_CBFS_LEN - hex "Microcode update region length in bytes" - default 0 - help - The length in bytes of the microcode update region. - -config CPU_MICROCODE_CBFS_LOC - hex "Microcode update base address in CBFS" - default 0 - help - The location (base address) in CBFS that contains the microcode update - binary. - config FSP_FILE string "Intel FSP binary path and filename" help diff --git a/src/drivers/intel/fsp1_1/cache_as_ram.inc b/src/drivers/intel/fsp1_1/cache_as_ram.inc index 6af30ce..1d35b14 100644 --- a/src/drivers/intel/fsp1_1/cache_as_ram.inc +++ b/src/drivers/intel/fsp1_1/cache_as_ram.inc @@ -344,8 +344,8 @@ fake_fsp_stack: .long find_fsp_ret CAR_init_params: - .long CONFIG_CPU_MICROCODE_CBFS_LOC /* Microcode Location */ - .long CONFIG_CPU_MICROCODE_CBFS_LEN /* Microcode Length */ + .long 0 /* Microcode Location */ + .long 0 /* Microcode Length */ .long 0xFFFFFFFF - CONFIG_CBFS_SIZE + 1 /* Firmware Location */ .long CONFIG_CBFS_SIZE /* Total Firmware Length */ diff --git a/src/soc/intel/braswell/microcode/Makefile.inc b/src/soc/intel/braswell/microcode/Makefile.inc index da25b8b..3497328 100644 --- a/src/soc/intel/braswell/microcode/Makefile.inc +++ b/src/soc/intel/braswell/microcode/Makefile.inc @@ -1,13 +1,2 @@ # Add CPU uCode source to list of files to build. cpu_microcode-y += microcode_blob.c - -# This section overrides the default build process for the microcode to place -# it at a known location in the CBFS. This only needs to be enabled if FSP is -# being used. -# Define the correct offset for the file in CBFS -fsp_ucode_cbfs_base = $(CONFIG_CPU_MICROCODE_CBFS_LOC) - -# Override the location that was supplied by the core code. -add-cpu-microcode-to-cbfs = \ - $(CBFSTOOL) $(1) add -n $(cpu_ucode_cbfs_name) -f $(cpu_ucode_cbfs_file) -t microcode -b $(fsp_ucode_cbfs_base) - diff --git a/src/soc/intel/skylake/microcode/Makefile.inc b/src/soc/intel/skylake/microcode/Makefile.inc index a5e8981..ba308f6 100644 --- a/src/soc/intel/skylake/microcode/Makefile.inc +++ b/src/soc/intel/skylake/microcode/Makefile.inc @@ -1,13 +1,2 @@ # Add CPU uCode source to list of files to build. cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c - -# This section overrides the default build process for the microcode to place -# it at a known location in the CBFS. This only needs to be enabled if FSP is -# being used. -# Define the correct offset for the file in CBFS -fsp_ucode_cbfs_base = $(CONFIG_CPU_MICROCODE_CBFS_LOC) - -# Override the location that was supplied by the core code. -add-cpu-microcode-to-cbfs = \ - $(CBFSTOOL) $(1) add -n $(cpu_ucode_cbfs_name) -f $(cpu_ucode_cbfs_file) -t microcode -b $(fsp_ucode_cbfs_base) -

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New patch to review for coreboot: soc/intel/braswell/Kconfig: Remove ENABLE_MRC_CACHE Kconfig
by Alexandru Gagniuc 30 Aug '15

30 Aug '15

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11462 -gerrit commit 7c9c0fe546627acbe00af503176ffcd5e7d4d1c5 Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Sat Aug 29 19:08:28 2015 -0700 soc/intel/braswell/Kconfig: Remove ENABLE_MRC_CACHE Kconfig This option was removed in the following commit: * 80f5d5b fsp1_1: remove duplicate mrc caching mechanism Change-Id: I08ef4fc6029cc066e4f7b9c82b6b187a9794afdb Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- src/soc/intel/braswell/Kconfig | 1 - 1 file changed, 1 deletion(-) diff --git a/src/soc/intel/braswell/Kconfig b/src/soc/intel/braswell/Kconfig index a3f6025..ab36056 100644 --- a/src/soc/intel/braswell/Kconfig +++ b/src/soc/intel/braswell/Kconfig @@ -17,7 +17,6 @@ config CPU_SPECIFIC_OPTIONS select COLLECT_TIMESTAMPS select SUPPORT_CPU_UCODE_IN_CBFS select CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED - select ENABLE_MRC_CACHE select HAS_PRECBMEM_TIMESTAMP_REGION select HAVE_MONOTONIC_TIMER select HAVE_SMI_HANDLER

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coreboot-gerrit August 2015