coreboot-gerrit September 2014

coreboot-gerrit@coreboot.org

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New patch to review for coreboot: 99cdcb5 TEGRA124: add a chip.h and use it in NYAN
by Isaac Christensen 09 Sep '14

09 Sep '14

Isaac Christensen (isaac.christensen(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6867 -gerrit commit 99cdcb51aa4aa8c476d81ef274e5ff25885dfb47 Author: Ronald G. Minnich <rminnich(a)google.com> Date: Fri Oct 11 11:22:08 2013 -0700 TEGRA124: add a chip.h and use it in NYAN For graphics we need a chip.h in tegra124. Add it. Set it in the nyan mainboard as a test. Change-Id: I1c5ccd5574d2e6b49bb4947035ccd10e99729458 Signed-off-by: Ronald G. Minnich <rminnich(a)google.com> Reviewed-on: https://chromium-review.googlesource.com/172773 Reviewed-by: David Hendricks <dhendrix(a)chromium.org> Commit-Queue: Ronald Minnich <rminnich(a)chromium.org> Tested-by: Ronald Minnich <rminnich(a)chromium.org> (cherry picked from commit 4dd5f1f091f2dcae5ce38203bb86c62994609f8f) Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com> --- src/mainboard/google/nyan/devicetree.cb | 3 +++ src/soc/nvidia/tegra124/chip.h | 31 +++++++++++++++++++++++++++++++ 2 files changed, 34 insertions(+) diff --git a/src/mainboard/google/nyan/devicetree.cb b/src/mainboard/google/nyan/devicetree.cb index 392a5ae..435e811 100644 --- a/src/mainboard/google/nyan/devicetree.cb +++ b/src/mainboard/google/nyan/devicetree.cb @@ -19,4 +19,7 @@ chip soc/nvidia/tegra124 device cpu_cluster 0 on end + register "xres" = "2560" + register "yres" = "1600" + register "framebuffer_bits_per_pixel" = "24" end diff --git a/src/soc/nvidia/tegra124/chip.h b/src/soc/nvidia/tegra124/chip.h new file mode 100644 index 0000000..5ccdd21 --- /dev/null +++ b/src/soc/nvidia/tegra124/chip.h @@ -0,0 +1,31 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef __SOC_NVIDIA_TEGRA124_CHIP_H__ +#define __SOC_NVIDIA_TEGRA124_CHIP_H__ + +struct soc_nvidia_tegra124_config { + int xres; + int yres; + int framebuffer_bits_per_pixel; + + u32 framebuffer_base; +}; + +#endif /* __SOC_NVIDIA_TEGRA124_CHIP_H__ */

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New patch to review for coreboot: 624f9af nyan: Initialize the i2c pins and controllers.
by Isaac Christensen 09 Sep '14

09 Sep '14

Isaac Christensen (isaac.christensen(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6866 -gerrit commit 624f9af237d3ce601c8fb81eac3d95f73718ec15 Author: Gabe Black <gabeblack(a)google.com> Date: Thu Oct 10 03:46:14 2013 -0700 nyan: Initialize the i2c pins and controllers. Set up the i2c controllers that are used on nyan. Old-Change-Id: Ibdd5685e3effdd13ca560b8f18db25e9edadc07b Signed-off-by: Gabe Black <gabeblack(a)google.com> Reviewed-on: https://chromium-review.googlesource.com/172584 Reviewed-by: Ronald Minnich <rminnich(a)chromium.org> Reviewed-by: Julius Werner <jwerner(a)chromium.org> Tested-by: Gabe Black <gabeblack(a)chromium.org> Commit-Queue: Gabe Black <gabeblack(a)chromium.org> (cherry picked from commit 9c10a3074ef834688fea46c03551c2e3e54e44a8) nyan: Initialize the PMIC. Add code which initializes the AS3722 PMIC based on the initialization sequence U-Boot uses. I wasn't able to find documentation which said what each register in the PMIC does, so the next best solution was to imitate another implementation which presumably sets things up correctly. The code is set up significantly differently than the U-Boot code, first because it uses the i2c driver through it's external interface instead of poking values into the controller's registers directly. The driver uses the packet mode of the controller while the U-Boot code does not. Second, it uses an array of register indices and values, a pattern established with Exynos, instead of having a sequence of calls to the i2c_write function. This change is also a practical test of the i2c driver's write capability. Old-Change-Id: Iab1f8d3b735b0737ce93ee3c9c7fdb2a1dcbbf8a Signed-off-by: Gabe Black <gabeblack(a)google.com> Reviewed-on: https://chromium-review.googlesource.com/172585 Reviewed-by: Ronald Minnich <rminnich(a)chromium.org> Reviewed-by: Julius Werner <jwerner(a)chromium.org> Tested-by: Gabe Black <gabeblack(a)chromium.org> Commit-Queue: Gabe Black <gabeblack(a)chromium.org> (cherry picked from commit f6be8b0e607e05b73b5e4a84afcf04c879eee88a) Squashed nyan i2c related commits. Change-Id: I04d7f770ed2ff62d43da637671d2f58d5c340fd6 Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com> --- src/mainboard/google/nyan/Makefile.inc | 1 + src/mainboard/google/nyan/bootblock.c | 38 +++++++++++++++++ src/mainboard/google/nyan/pmic.c | 78 ++++++++++++++++++++++++++++++++++ src/mainboard/google/nyan/pmic.h | 25 +++++++++++ 4 files changed, 142 insertions(+) diff --git a/src/mainboard/google/nyan/Makefile.inc b/src/mainboard/google/nyan/Makefile.inc index 2dfd2a3..f154a3b 100644 --- a/src/mainboard/google/nyan/Makefile.inc +++ b/src/mainboard/google/nyan/Makefile.inc @@ -28,6 +28,7 @@ $(obj)/generated/bct.cfg: subdirs-y += bct bootblock-y += bootblock.c +bootblock-y += pmic.c romstage-y += romstage.c diff --git a/src/mainboard/google/nyan/bootblock.c b/src/mainboard/google/nyan/bootblock.c index e193ab1..fe938b4 100644 --- a/src/mainboard/google/nyan/bootblock.c +++ b/src/mainboard/google/nyan/bootblock.c @@ -18,9 +18,47 @@ */ #include <bootblock_common.h> +#include <console/console.h> +#include <device/i2c.h> +#include <soc/nvidia/tegra/i2c.h> #include <soc/nvidia/tegra124/clock.h> +#include <soc/nvidia/tegra124/pinmux.h> + +#include "pmic.h" void bootblock_mainboard_init(void) { clock_config(); + + // I2C1 clock. + pinmux_set_config(PINMUX_GEN1_I2C_SCL_INDEX, + PINMUX_GEN1_I2C_SCL_FUNC_I2C1 | PINMUX_INPUT_ENABLE); + // I2C1 data. + pinmux_set_config(PINMUX_GEN1_I2C_SDA_INDEX, + PINMUX_GEN1_I2C_SDA_FUNC_I2C1 | PINMUX_INPUT_ENABLE); + // I2C2 clock. + pinmux_set_config(PINMUX_GEN2_I2C_SCL_INDEX, + PINMUX_GEN2_I2C_SCL_FUNC_I2C2 | PINMUX_INPUT_ENABLE); + // I2C2 data. + pinmux_set_config(PINMUX_GEN2_I2C_SDA_INDEX, + PINMUX_GEN2_I2C_SDA_FUNC_I2C2 | PINMUX_INPUT_ENABLE); + // I2C3 (cam) clock. + pinmux_set_config(PINMUX_CAM_I2C_SCL_INDEX, + PINMUX_CAM_I2C_SCL_FUNC_I2C3 | PINMUX_INPUT_ENABLE); + // I2C3 (cam) data. + pinmux_set_config(PINMUX_CAM_I2C_SDA_INDEX, + PINMUX_CAM_I2C_SDA_FUNC_I2C3 | PINMUX_INPUT_ENABLE); + // I2C5 (PMU) clock. + pinmux_set_config(PINMUX_PWR_I2C_SCL_INDEX, + PINMUX_PWR_I2C_SCL_FUNC_I2CPMU | PINMUX_INPUT_ENABLE); + // I2C5 (PMU) data. + pinmux_set_config(PINMUX_PWR_I2C_SDA_INDEX, + PINMUX_PWR_I2C_SDA_FUNC_I2CPMU | PINMUX_INPUT_ENABLE); + + i2c_init(0); + i2c_init(1); + i2c_init(2); + i2c_init(4); + + pmic_init(4); } diff --git a/src/mainboard/google/nyan/pmic.c b/src/mainboard/google/nyan/pmic.c new file mode 100644 index 0000000..ab951ea --- /dev/null +++ b/src/mainboard/google/nyan/pmic.c @@ -0,0 +1,78 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2013 Google Inc. + * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <delay.h> +#include <device/i2c.h> +#include <stdint.h> +#include <stdlib.h> + +#include "pmic.h" + +struct pmic_write +{ + uint8_t reg; // Register to write. + uint8_t val; // Value to write. +}; + +enum { + AS3722_I2C_ADDR = 0x40 +}; + +static struct pmic_write pmic_writes[] = +{ + /* Don't need to set up VDD_CORE - already done - by OTP */ + + /* First set VDD_CPU to 1.0V, then enable the VDD_CPU regulator. */ + { 0x00, 0x28 }, + + /* Don't write SDCONTROL - it's already 0x7F, i.e. all SDs enabled. */ + + /* First set VDD_GPU to 1.0V, then enable the VDD_GPU regulator. */ + { 0x06, 0x28 }, + + /* Don't write SDCONTROL - it's already 0x7F, i.e. all SDs enabled. */ + + /* First set VPP_FUSE to 1.2V, then enable the VPP_FUSE regulator. */ + { 0x12, 0x10 }, + + /* Don't write LDCONTROL - it's already 0xFF, i.e. all LDOs enabled. */ + + /* + * Bring up VDD_SDMMC via the AS3722 PMIC on the PWR I2C bus. + * First set it to bypass 3.3V straight thru, then enable the regulator + * + * NOTE: We do this early because doing it later seems to hose the CPU + * power rail/partition startup. Need to debug. + */ + { 0x16, 0x3f } + + /* Don't write LDCONTROL - it's already 0xFF, i.e. all LDOs enabled. */ +}; + +void pmic_init(unsigned bus) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(pmic_writes); i++) { + i2c_write(bus, AS3722_I2C_ADDR, pmic_writes[i].reg, 1, + &pmic_writes[i].val, 1); + udelay(10 * 1000); + } +} diff --git a/src/mainboard/google/nyan/pmic.h b/src/mainboard/google/nyan/pmic.h new file mode 100644 index 0000000..78c9f0d --- /dev/null +++ b/src/mainboard/google/nyan/pmic.h @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef __MAINBOARD_GOOGLE_NYAN_PMIC_H__ +#define __MAINBOARD_GOOGLE_NYAN_PMIC_H__ + +void pmic_init(unsigned bus); + +#endif /* __MAINBOARD_GOOGLE_NYAN_PMIC_H__ */

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New patch to review for coreboot: f1efa8c1 nyan: tegra124: Redestribute the clock code between the mainboard and soc.
by Isaac Christensen 09 Sep '14

09 Sep '14

Isaac Christensen (isaac.christensen(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6865 -gerrit commit f1efa8c16d149ddba0be759d2db6c0af94857278 Author: Gabe Black <gabeblack(a)google.com> Date: Thu Oct 10 02:48:15 2013 -0700 nyan: tegra124: Redestribute the clock code between the mainboard and soc. There's generic clock initialization that needs to be done for any mainboard using that soc. Other initialization depends on what peripherals are going to be used and what rate they should run at and should be done in the mainboard source. Change-Id: Idf79faac523bb99f3c7c29bac6947d2149fc3651 Signed-off-by: Gabe Black <gabeblack(a)google.com> Reviewed-on: https://chromium-review.googlesource.com/172583 Reviewed-by: Ronald Minnich <rminnich(a)chromium.org> Reviewed-by: Julius Werner <jwerner(a)chromium.org> Tested-by: Gabe Black <gabeblack(a)chromium.org> Commit-Queue: Gabe Black <gabeblack(a)chromium.org> (cherry picked from commit ea703137fc37befa7d5a65afc982e298a0daca1b) Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com> --- src/mainboard/google/nyan/bootblock.c | 2 ++ src/soc/nvidia/tegra124/bootblock.c | 4 +-- src/soc/nvidia/tegra124/clock.c | 53 ++++++++++++++++++----------------- src/soc/nvidia/tegra124/clock.h | 6 ++-- 4 files changed, 34 insertions(+), 31 deletions(-) diff --git a/src/mainboard/google/nyan/bootblock.c b/src/mainboard/google/nyan/bootblock.c index f0753d4..e193ab1 100644 --- a/src/mainboard/google/nyan/bootblock.c +++ b/src/mainboard/google/nyan/bootblock.c @@ -18,7 +18,9 @@ */ #include <bootblock_common.h> +#include <soc/nvidia/tegra124/clock.h> void bootblock_mainboard_init(void) { + clock_config(); } diff --git a/src/soc/nvidia/tegra124/bootblock.c b/src/soc/nvidia/tegra124/bootblock.c index cc246c3..f84e48a 100644 --- a/src/soc/nvidia/tegra124/bootblock.c +++ b/src/soc/nvidia/tegra124/bootblock.c @@ -29,9 +29,9 @@ void main(void) { void *entry; - set_avp_clock_to_clkm(); + clock_init(); - init_clocks(); + clock_uart_config(); // Serial out, tristate off. pinmux_set_config(PINMUX_KB_ROW9_INDEX, PINMUX_KB_ROW9_FUNC_UA3); diff --git a/src/soc/nvidia/tegra124/clock.c b/src/soc/nvidia/tegra124/clock.c index 563bdae..ff6a2f1 100644 --- a/src/soc/nvidia/tegra124/clock.c +++ b/src/soc/nvidia/tegra124/clock.c @@ -148,8 +148,7 @@ static int pllx_set_rate(struct clk_pll_simple *pll , u32 divn, u32 divm, return 0; } - -void init_pllx(void) +static void init_pllx(void) { int osc; struct clk_pll_table *sel; @@ -169,33 +168,41 @@ void init_pllx(void) adjust_pllp_out_freqs(); } -/* - * On poweron, AVP clock source (also called system clock) is set to PLLP_out0 - * with frequency set at 1MHz. Before initializing PLLP, we need to move the - * system clock's source to CLK_M temporarily. And then switch it to PLLP_out4 - * (204MHz) at a later time. - */ -void set_avp_clock_to_clkm(void) + +void clock_uart_config(void) { - u32 val; + /* Enable clocks to required peripherals. TBD - minimize this list */ + /* The UART is super special so Just Do It right here. */ - val = (SCLK_SOURCE_CLKM << SCLK_SWAKEUP_FIQ_SOURCE_SHIFT) | - (SCLK_SOURCE_CLKM << SCLK_SWAKEUP_IRQ_SOURCE_SHIFT) | - (SCLK_SOURCE_CLKM << SCLK_SWAKEUP_RUN_SOURCE_SHIFT) | - (SCLK_SOURCE_CLKM << SCLK_SWAKEUP_IDLE_SOURCE_SHIFT) | - (SCLK_SYS_STATE_RUN << SCLK_SYS_STATE_SHIFT); - writel(val, &clk_rst->crc_sclk_brst_pol); + setbits_le32(clkreset(CLK_UARTA_REG), CLK_UARTA_MASK); + setbits_le32(clkenable(CLK_UARTA_REG), CLK_UARTA_MASK); + clock_ll_set_source_divisor(&clk_rst->src_uarta, 0, 2); udelay(2); + clrbits_le32(clkreset(CLK_UARTA_REG), CLK_UARTA_MASK); } /** * The T124 requires some special clock initialization, including setting up * the DVC I2C, turning on MSELECT and selecting the G CPU cluster */ -void init_clocks(void) +void clock_init(void) { u32 val; + /* + * On poweron, AVP clock source (also called system clock) is set to + * PLLP_out0 with frequency set at 1MHz. Before initializing PLLP, we + * need to move the system clock's source to CLK_M temporarily. And + * then switch it to PLLP_out4 (204MHz) at a later time. + */ + val = (SCLK_SOURCE_CLKM << SCLK_SWAKEUP_FIQ_SOURCE_SHIFT) | + (SCLK_SOURCE_CLKM << SCLK_SWAKEUP_IRQ_SOURCE_SHIFT) | + (SCLK_SOURCE_CLKM << SCLK_SWAKEUP_RUN_SOURCE_SHIFT) | + (SCLK_SOURCE_CLKM << SCLK_SWAKEUP_IDLE_SOURCE_SHIFT) | + (SCLK_SYS_STATE_RUN << SCLK_SYS_STATE_SHIFT); + writel(val, &clk_rst->crc_sclk_brst_pol); + udelay(2); + /* Set active CPU cluster to G */ clrbits_le32(&flow->cluster_control, 1); @@ -220,16 +227,10 @@ void init_clocks(void) val = (1 << CLK_SYS_RATE_AHB_RATE_SHIFT); writel(val, &clk_rst->crc_clk_sys_rate); +} - /* Enable clocks to required peripherals. TBD - minimize this list */ - /* The UART is super special so Just Do It right here. */ - - setbits_le32(clkreset(CLK_UARTA_REG), CLK_UARTA_MASK); - setbits_le32(clkenable(CLK_UARTA_REG), CLK_UARTA_MASK); - clock_ll_set_source_divisor(&clk_rst->src_uarta, 0, 2); - udelay(2); - clrbits_le32(clkreset(CLK_UARTA_REG), CLK_UARTA_MASK); - +void clock_config(void) +{ /* fixme. The stupidity of all this ... we are reading and * writing the same register lots of times when we could just * one lousy write with a combined mask. Sigh. diff --git a/src/soc/nvidia/tegra124/clock.h b/src/soc/nvidia/tegra124/clock.h index 39abddb..b97560c 100644 --- a/src/soc/nvidia/tegra124/clock.h +++ b/src/soc/nvidia/tegra124/clock.h @@ -165,13 +165,13 @@ enum { /* make this a macro, rather than a function; let the C compiler find * the error for you if you use an out of range index.. Requires you * to declare a clk_rst pointer. */ -void init_pllx(void); #define clkreset(x) &clk_rst->crc_rst_dev[(x)] #define clkenable(x) &clk_rst->crc_clk_out_enb[(x)] #define clkresetvw(x) &clk_rst->crc_rst_dev_vw[(x)] #define clkenablevw(x) &clk_rst->crc_clk_out_enb_vw[(x)] -void set_avp_clock_to_clkm(void); -void init_clocks(void); +void clock_uart_config(void); +void clock_config(void); +void clock_init(void); #endif /* __SOC_NVIDIA_TEGRA124_CLOCK_H__ */

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New patch to review for coreboot: b6e847a tegra124: Call into the mainboard bootblock init if one exists.
by Isaac Christensen 09 Sep '14

09 Sep '14

Isaac Christensen (isaac.christensen(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6864 -gerrit commit b6e847a7a21276e01c2317c12e6a33b9072c2bf5 Author: Gabe Black <gabeblack(a)google.com> Date: Thu Oct 10 02:18:39 2013 -0700 tegra124: Call into the mainboard bootblock init if one exists. We should seperate out the mainboard specific parts of the bootblock so that they can be customized as necessary. Old-Change-Id: Ia633a68521725f6e88341608ccdbedc4f1ce8223 Signed-off-by: Gabe Black <gabeblack(a)google.com> Reviewed-on: https://chromium-review.googlesource.com/172581 Reviewed-by: Ronald Minnich <rminnich(a)chromium.org> Reviewed-by: Julius Werner <jwerner(a)chromium.org> Tested-by: Gabe Black <gabeblack(a)chromium.org> Commit-Queue: Gabe Black <gabeblack(a)chromium.org> (cherry picked from commit 3a0cd48a0d1a9ce6b32ed614cd81fb81f5f82aec) nyan: Add a mainboard specific bootblock. We need somewhere to put mainboard specific bootblock initialization. Old-Change-Id: Ief409baff5ae67871879291c7ff0533f19ea6e56 Signed-off-by: Gabe Black <gabeblack(a)google.com> Reviewed-on: https://chromium-review.googlesource.com/172582 Reviewed-by: Ronald Minnich <rminnich(a)chromium.org> Reviewed-by: Julius Werner <jwerner(a)chromium.org> Tested-by: Gabe Black <gabeblack(a)chromium.org> Commit-Queue: Gabe Black <gabeblack(a)chromium.org> (cherry picked from commit a83d065d660a26fe71ed79879c25f84a1b669f69) Squashed two commits for a nyan specific bootblock. Change-Id: I25808a19ffa744e439e677ac329a9c68b03bd7e7 Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com> --- src/mainboard/google/nyan/Kconfig | 1 + src/mainboard/google/nyan/Makefile.inc | 2 ++ src/mainboard/google/nyan/bootblock.c | 24 ++++++++++++++++++++++++ src/soc/nvidia/tegra124/bootblock.c | 3 +++ 4 files changed, 30 insertions(+) diff --git a/src/mainboard/google/nyan/Kconfig b/src/mainboard/google/nyan/Kconfig index 5ac58d3..3c066ac 100644 --- a/src/mainboard/google/nyan/Kconfig +++ b/src/mainboard/google/nyan/Kconfig @@ -22,6 +22,7 @@ if BOARD_GOOGLE_NYAN config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select SOC_NVIDIA_TEGRA124 + select MAINBOARD_HAS_BOOTBLOCK_INIT select BOARD_ROMSIZE_KB_1024 config MAINBOARD_DIR diff --git a/src/mainboard/google/nyan/Makefile.inc b/src/mainboard/google/nyan/Makefile.inc index 3cf7dd2..2dfd2a3 100644 --- a/src/mainboard/google/nyan/Makefile.inc +++ b/src/mainboard/google/nyan/Makefile.inc @@ -27,6 +27,8 @@ $(obj)/generated/bct.cfg: subdirs-y += bct +bootblock-y += bootblock.c + romstage-y += romstage.c ramstage-y += mainboard.c diff --git a/src/mainboard/google/nyan/bootblock.c b/src/mainboard/google/nyan/bootblock.c new file mode 100644 index 0000000..f0753d4 --- /dev/null +++ b/src/mainboard/google/nyan/bootblock.c @@ -0,0 +1,24 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <bootblock_common.h> + +void bootblock_mainboard_init(void) +{ +} diff --git a/src/soc/nvidia/tegra124/bootblock.c b/src/soc/nvidia/tegra124/bootblock.c index 07c9b16..cc246c3 100644 --- a/src/soc/nvidia/tegra124/bootblock.c +++ b/src/soc/nvidia/tegra124/bootblock.c @@ -18,6 +18,7 @@ */ #include <arch/hlt.h> +#include <bootblock_common.h> #include <cbfs.h> #include <console/console.h> @@ -42,6 +43,8 @@ void main(void) if (CONFIG_BOOTBLOCK_CONSOLE) console_init(); + bootblock_mainboard_init(); + entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, "fallback/romstage"); hlt();

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New patch to review for coreboot: 4993cca nyan: Clock setup.
by Isaac Christensen 09 Sep '14

09 Sep '14

Isaac Christensen (isaac.christensen(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6863 -gerrit commit 4993cca28608b8fcb8c12b9aaccbf1ecf76878f6 Author: Ronald G. Minnich <rminnich(a)google.com> Date: Mon Oct 7 11:42:41 2013 -0700 nyan: Clock setup. I cleaned up the clk_rst struct: no need to have an array for the source select because each thing is an individual entity. There is a bit of a trick in here. I'm using macros to index arrays in the clk_rst struct. Simple reason: if people use the constants we get compile-time checking for simple errors. init_pllx is fixed. The vendor table in u-boot was wrong. Change-Id: I4429b3e5c14c200db6b4dd129eff14261fe1f326 Signed-off-by: Ronald G. Minnich <rminnich(a)google.com> Reviewed-on: https://chromium-review.googlesource.com/172106 Tested-by: Gabe Black <gabeblack(a)chromium.org> Reviewed-by: Ronald Minnich <rminnich(a)chromium.org> Reviewed-by: Julius Werner <jwerner(a)chromium.org> Commit-Queue: Gabe Black <gabeblack(a)chromium.org> (cherry picked from commit 3697b6454c0aceebcf735436de90ba2441c9b7b1) Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com> --- src/soc/nvidia/tegra124/bootblock.c | 21 +- src/soc/nvidia/tegra124/clk_rst.h | 61 +++++- src/soc/nvidia/tegra124/clock.c | 257 +++++++++++++++++++++++- src/soc/nvidia/tegra124/clock.h | 155 +++++++++++++++ src/soc/nvidia/tegra124/flow.h | 49 +++++ src/soc/nvidia/tegra124/pmc.h | 377 ++++++++++++++++++++++++++++++++++++ 6 files changed, 893 insertions(+), 27 deletions(-) diff --git a/src/soc/nvidia/tegra124/bootblock.c b/src/soc/nvidia/tegra124/bootblock.c index a3bed23..07c9b16 100644 --- a/src/soc/nvidia/tegra124/bootblock.c +++ b/src/soc/nvidia/tegra124/bootblock.c @@ -18,38 +18,19 @@ */ #include <arch/hlt.h> -#include <arch/io.h> #include <cbfs.h> #include <console/console.h> -#include <delay.h> #include "clock.h" #include "pinmux.h" -static void hacky_hardcoded_uart_setup_function(void) -{ - // Assert UART reset and enable clock. - setbits_le32((void *)(0x60006000 + 4 + 0), 1 << 6); - - // Enable the clock. - setbits_le32((void *)(0x60006000 + 4 * 4 + 0), 1 << 6); - - // Set the clock source. - clrbits_le32((void *)(0x60006000 + 0x100 + 4 * 0x1e), 3 << 30); - - udelay(2); - - // De-assert reset to UART. - clrbits_le32((void *)(0x60006000 + 4 + 0), 1 << 6); -} - void main(void) { void *entry; set_avp_clock_to_clkm(); - hacky_hardcoded_uart_setup_function(); + init_clocks(); // Serial out, tristate off. pinmux_set_config(PINMUX_KB_ROW9_INDEX, PINMUX_KB_ROW9_FUNC_UA3); diff --git a/src/soc/nvidia/tegra124/clk_rst.h b/src/soc/nvidia/tegra124/clk_rst.h index badb58b..9db9aae 100644 --- a/src/soc/nvidia/tegra124/clk_rst.h +++ b/src/soc/nvidia/tegra124/clk_rst.h @@ -60,7 +60,7 @@ enum { }; /* Clock/Reset Controller (CLK_RST_CONTROLLER_) regs */ -struct clk_rst_ctlr { +struct __attribute__ ((__packed__)) clk_rst_ctlr { u32 crc_rst_src; /* _RST_SOURCE_0,0x00 */ u32 crc_rst_dev[TEGRA_CLK_REGS]; /* _RST_DEVICES_L/H/U_0 */ u32 crc_clk_out_enb[TEGRA_CLK_REGS]; /* _CLK_OUT_ENB_L/H/U_0 */ @@ -90,8 +90,63 @@ struct clk_rst_ctlr { u32 crc_reserved10; /* _reserved_10, 0xF8 */ u32 crc_reserved11; /* _reserved_11, 0xFC */ - - u32 crc_clk_src[TEGRA_CLK_SOURCES]; /*_I2S1_0... 0x100-1fc */ + /* 0x100 0x1fc */ + u32 src_i2s1; + u32 src_i2s2; + u32 src_spdif_out; + u32 src_spdif_in; + u32 src_pwm; + u32 _pad1; + u32 src_sbc2; + u32 src_sbc3; + u32 _pad2[2]; + u32 src_i2c1; + u32 src_i2c5; + u32 _pad[1]; + u32 src_sbc1; + u32 src_disp1; + u32 src_disp2; + u32 _pad4[2]; + u32 src_vi; + u32 _pad5; + u32 src_sdmmc1; + u32 src_sdmmc2; + u32 src_g3d; + u32 src_g2d; + u32 src_ndflash; + u32 src_sdmmc4 ; + u32 src_vfir; + u32 src_epp; + u32 src_mpe; + u32 src_hsi; + u32 src_uarta; + u32 src_uartb; + u32 src_host1x; + u32 _pad6[2]; + u32 src_hdmi; + u32 _pad7[2]; + u32 src_i2c2; + u32 src_emc0; /* not correctly documented as to address. */ + u32 src_uartc; + u32 _pad71; + u32 src_vi_sensor; + u32 _pad8[2]; + u32 src_sbc4; + u32 src_i2c3; + u32 src_sdmmc3; + u32 src_uartd; + u32 src_uarte; + u32 src_vde; + u32 src_owr; + u32 src_nor; + u32 src_csite; + u32 src_i2s0; + u32 src_dtv; + u32 pad9[4]; + u32 src_msenc; + u32 src_tsec; + u32 pad10; + u32 src_osc; u32 crc_reserved20[32]; /* _reserved_20, 0x200-27c */ diff --git a/src/soc/nvidia/tegra124/clock.c b/src/soc/nvidia/tegra124/clock.c index af01b56..563bdae 100644 --- a/src/soc/nvidia/tegra124/clock.c +++ b/src/soc/nvidia/tegra124/clock.c @@ -13,15 +13,162 @@ * You should have received a copy of the GNU General Public License * along with this program. If not, see <http://www.gnu.org/licenses/>. */ - +#include <console/console.h> #include <delay.h> #include <arch/io.h> #include <soc/addressmap.h> - #include "clk_rst.h" #include "clock.h" +#include "flow.h" +#include "pmc.h" static struct clk_rst_ctlr *clk_rst = (void *)TEGRA_CLK_RST_BASE; +static struct flow_ctlr *flow = (void *)TEGRA_FLOW_BASE; +static struct pmc_ctlr *pmc = (void*)TEGRA_PMC_BASE; + +/* only needed in this one place. Avoid namespace pollution. Be green .*/ +struct clk_pll_table { + u16 n; + u16 m; + u8 p; + u8 cpcon; +}; + +/* + * Timing tables + */ +struct clk_pll_table tegra_pll_x_table[16] = { + /* T124: 1.9 GHz */ + /* + * Field Bits Width + * n 15:8 8 + * m 7:0 8 + * p 23:20 4 + */ + [OSC_FREQ_OSC13]{216,13,1,8}, + [OSC_FREQ_OSC19P2]{180,16,1,4}, + [OSC_FREQ_OSC12]{216,12,1,8}, + [OSC_FREQ_OSC26]{216,26,1,8}, + [OSC_FREQ_OSC16P8]{180,14,1,4}, + [OSC_FREQ_OSC38P4]{180,16,1,4}, + [OSC_FREQ_OSC48]{216,12,1,8}, +}; + +/* one of the very few funcs we might move to common code. */ +static void clock_ll_set_source_divisor(u32 *reg, + unsigned source, unsigned divisor) +{ + u32 value; + + value = readl(reg); + + value &= ~OUT_CLK_SOURCE_MASK; + value |= source << OUT_CLK_SOURCE_SHIFT; + + value &= ~OUT_CLK_DIVISOR_MASK; + value |= divisor << OUT_CLK_DIVISOR_SHIFT; + + writel(value, reg); +} + + +/* Get the oscillator frequency, from the corresponding hardware + * configuration field. This is actually a per-soc thing. Avoid the + * temptation to make it common. + */ +static int clock_get_osc_freq(void) +{ + u32 reg; + reg = readl(&clk_rst->crc_osc_ctrl); + reg >>= OSC_CTRL_OSC_FREQ_SHIFT; + return reg; +} + +static void adjust_pllp_out_freqs(void) +{ + u32 reg; + struct clk_pll *pll = &clk_rst->crc_pll[2/*CLOCK_ID_PERIPH*/]; + /* Set T30 PLLP_OUT1, 2, 3 & 4 freqs to 9.6, 48, 102 & 204MHz */ + reg = readl(&pll->pll_out[0]); /* OUTA, contains OUT2 / OUT1 */ + reg |= (IN_408_OUT_48_DIVISOR << PLLP_OUT2_RATIO) | PLLP_OUT2_OVR + | (IN_408_OUT_9_6_DIVISOR << PLLP_OUT1_RATIO) | PLLP_OUT1_OVR; + writel(reg, &pll->pll_out[0]); + + reg = readl(&pll->pll_out[1]); /* OUTB, contains OUT4 / OUT3 */ + reg |= (IN_408_OUT_204_DIVISOR << PLLP_OUT4_RATIO) | PLLP_OUT4_OVR + | (IN_408_OUT_102_DIVISOR << PLLP_OUT3_RATIO) | PLLP_OUT3_OVR; + writel(reg, &pll->pll_out[1]); +} + +static int pllx_set_rate(struct clk_pll_simple *pll , u32 divn, u32 divm, + u32 divp, u32 cpcon) +{ + u32 reg; + + /* If PLLX is already enabled, just return */ + if (readl(&pll->pll_base) & PLL_ENABLE_MASK) { + return 0; + } + + + /* Disable IDDQ */ + reg = readl(&clk_rst->crc_pllx_misc3); + reg &= ~PLLX_IDDQ_MASK; + writel(reg, &clk_rst->crc_pllx_misc3); + udelay(2); + + /* Set BYPASS, m, n and p to PLLX_BASE */ + reg = PLL_BYPASS_MASK | (divm << PLL_DIVM_SHIFT); + reg |= ((divn << PLL_DIVN_SHIFT) | (divp << PLL_DIVP_SHIFT)); + writel(reg, &pll->pll_base); + + /* Set cpcon to PLLX_MISC */ + reg = (cpcon << PLL_CPCON_SHIFT); + + /* Set dccon to PLLX_MISC if freq > 600MHz - still needed for T124? */ + if (divn > 600) + reg |= (1 << PLL_DCCON_SHIFT); + writel(reg, &pll->pll_misc); + + /* Disable BYPASS */ + reg = readl(&pll->pll_base); + reg &= ~PLL_BYPASS_MASK; + writel(reg, &pll->pll_base); + + /* Set lock_enable to PLLX_MISC */ + reg = readl(&pll->pll_misc); + reg |= PLL_LOCK_ENABLE_MASK; + writel(reg, &pll->pll_misc); + + /* Enable PLLX last, as per JZ */ + reg = readl(&pll->pll_base); + reg |= PLL_ENABLE_MASK; + writel(reg, &pll->pll_base); + + return 0; +} + + +void init_pllx(void) +{ + int osc; + struct clk_pll_table *sel; + struct clk_pll_simple *pll = &clk_rst->crc_pll_simple[0/*SIMPLE_PLLX*/]; + + + /* get osc freq */ + osc = clock_get_osc_freq(); + + /* set pllx */ + sel = &tegra_pll_x_table[osc]; + if (sel->n == 0){ + return; + } + + pllx_set_rate(pll, sel->n, sel->m, sel->p, sel->cpcon); + + adjust_pllp_out_freqs(); +} /* * On poweron, AVP clock source (also called system clock) is set to PLLP_out0 * with frequency set at 1MHz. Before initializing PLLP, we need to move the @@ -38,6 +185,108 @@ void set_avp_clock_to_clkm(void) (SCLK_SOURCE_CLKM << SCLK_SWAKEUP_IDLE_SOURCE_SHIFT) | (SCLK_SYS_STATE_RUN << SCLK_SYS_STATE_SHIFT); writel(val, &clk_rst->crc_sclk_brst_pol); - /* Wait 2-3us for the clock to flush thru the logic as per the TRM */ - udelay(3); + udelay(2); +} + +/** + * The T124 requires some special clock initialization, including setting up + * the DVC I2C, turning on MSELECT and selecting the G CPU cluster + */ +void init_clocks(void) +{ + u32 val; + + /* Set active CPU cluster to G */ + clrbits_le32(&flow->cluster_control, 1); + + /* Change the oscillator drive strength */ + val = readl(&clk_rst->crc_osc_ctrl); + val &= ~OSC_XOFS_MASK; + val |= (OSC_DRIVE_STRENGTH << OSC_XOFS_SHIFT); + writel(val, &clk_rst->crc_osc_ctrl); + + /* Ambiguous quote from u-boot. TODO: what's this mean? + * "should update same value in PMC_OSC_EDPD_OVER XOFS + field for warmboot "*/ + val = readl(&pmc->pmc_osc_edpd_over); + val &= ~PMC_XOFS_MASK; + val |= (OSC_DRIVE_STRENGTH << PMC_XOFS_SHIFT); + writel(val, &pmc->pmc_osc_edpd_over); + + /* Set HOLD_CKE_LOW_EN to 1 */ + setbits_le32(&pmc->pmc_cntrl2, HOLD_CKE_LOW_EN); + + init_pllx(); + + val = (1 << CLK_SYS_RATE_AHB_RATE_SHIFT); + writel(val, &clk_rst->crc_clk_sys_rate); + + /* Enable clocks to required peripherals. TBD - minimize this list */ + /* The UART is super special so Just Do It right here. */ + + setbits_le32(clkreset(CLK_UARTA_REG), CLK_UARTA_MASK); + setbits_le32(clkenable(CLK_UARTA_REG), CLK_UARTA_MASK); + clock_ll_set_source_divisor(&clk_rst->src_uarta, 0, 2); + udelay(2); + clrbits_le32(clkreset(CLK_UARTA_REG), CLK_UARTA_MASK); + + /* fixme. The stupidity of all this ... we are reading and + * writing the same register lots of times when we could just + * one lousy write with a combined mask. Sigh. + */ + setbits_le32(clkenable(CLK_CACHE2_REG), CLK_CACHE2_MASK); + setbits_le32(clkenable(CLK_GPIO_REG), CLK_GPIO_MASK); + setbits_le32(clkenable(CLK_TMR_REG), CLK_TMR_MASK); + setbits_le32(clkenable(CLK_CPU_REG), CLK_CPU_MASK); + setbits_le32(clkenable(CLK_EMC_REG), CLK_EMC_MASK); + setbits_le32(clkenable(CLK_I2C1_REG), CLK_I2C1_MASK); + setbits_le32(clkenable(CLK_I2C2_REG), CLK_I2C2_MASK); + setbits_le32(clkenable(CLK_I2C3_REG), CLK_I2C3_MASK); + setbits_le32(clkenable(CLK_I2C5_REG), CLK_I2C5_MASK); + setbits_le32(clkenable(CLK_APBDMA_REG), CLK_APBDMA_MASK); + setbits_le32(clkenable(CLK_MEM_REG), CLK_MEM_MASK); + setbits_le32(clkenable(CLK_CSITE_REG), CLK_CSITE_MASK); + setbits_le32(clkenablevw(CLK_VW_MSELECT_REG), CLK_VW_MSELECT_MASK); + setbits_le32(clkenablevw(CLK_VW_DVFS_REG), CLK_VW_DVFS_MASK); + + /* + * Set MSELECT clock source as PLLP (00)_REG, and ask for a clock + * divider that would set the MSELECT clock at 102MHz for a + * PLLP base of 408MHz. + */ + clock_ll_set_source_divisor((void *)CLK_VW_MSELECT_REG, 0, + CLK_DIVIDER(NVBL_PLLP_KHZ, 102000)); + + /* Give clock time to stabilize */ + udelay(IO_STABILIZATION_DELAY); + + /* I2C1 gets CLK_M and a divisor of 17 */ + clock_ll_set_source_divisor(&clk_rst->src_i2c1, 3, 16); + /* I2C2 gets CLK_M and a divisor of 17 */ + clock_ll_set_source_divisor(&clk_rst->src_i2c2, 3, 16); + /* I2C3 (cam) gets CLK_M and a divisor of 17 */ + clock_ll_set_source_divisor(&clk_rst->src_i2c3, 3, 16); + /* I2C5 (PMU) gets CLK_M and a divisor of 17 */ + clock_ll_set_source_divisor(&clk_rst->src_i2c5, 3, 16); + + /* Give clock time to stabilize */ + udelay(IO_STABILIZATION_DELAY); + + /* Take required peripherals out of reset */ + + clrbits_le32(clkreset(CLK_CACHE2_REG), CLK_CACHE2_MASK); + clrbits_le32(clkreset(CLK_GPIO_REG), CLK_GPIO_MASK); + clrbits_le32(clkreset(CLK_TMR_REG), CLK_TMR_MASK); + clrbits_le32(clkreset(CLK_CPU_REG), CLK_CPU_MASK); + clrbits_le32(clkreset(CLK_EMC_REG), CLK_EMC_MASK); + clrbits_le32(clkreset(CLK_I2C5_REG), CLK_I2C5_MASK); + clrbits_le32(clkreset(CLK_I2C3_REG), CLK_I2C3_MASK); + clrbits_le32(clkreset(CLK_I2C2_REG), CLK_I2C2_MASK); + clrbits_le32(clkreset(CLK_I2C1_REG), CLK_I2C1_MASK); + clrbits_le32(clkreset(CLK_APBDMA_REG), CLK_APBDMA_MASK); + clrbits_le32(clkreset(CLK_MEM_REG), CLK_MEM_MASK); + clrbits_le32(clkreset(CLK_CSITE_REG), CLK_CSITE_MASK); + clrbits_le32(clkresetvw(CLK_VW_MSELECT_REG), CLK_VW_MSELECT_MASK); + clrbits_le32(clkresetvw(CLK_VW_DVFS_REG), CLK_VW_DVFS_MASK); + } diff --git a/src/soc/nvidia/tegra124/clock.h b/src/soc/nvidia/tegra124/clock.h index 688505a..39abddb 100644 --- a/src/soc/nvidia/tegra124/clock.h +++ b/src/soc/nvidia/tegra124/clock.h @@ -17,6 +17,161 @@ #ifndef __SOC_NVIDIA_TEGRA124_CLOCK_H__ #define __SOC_NVIDIA_TEGRA124_CLOCK_H__ +#define CLK_CONSTANTS(name, reg_index, reg_bit) \ + CLK_##name##_REG = reg_index, \ + CLK_##name##_MASK = (1 << reg_bit) + +enum { + CLK_CONSTANTS(CPU, 0, 0), + CLK_CONSTANTS(COP, 0, 1), + CLK_CONSTANTS(TRIG_SYS, 0, 2), + CLK_CONSTANTS(RTC, 0, 4), + CLK_CONSTANTS(TMR, 0, 5), + CLK_CONSTANTS(UARTA, 0, 6), + CLK_CONSTANTS(UARTB, 0, 7), + CLK_CONSTANTS(GPIO, 0, 8), + CLK_CONSTANTS(SDMMC2, 0, 9), + CLK_CONSTANTS(SPDIF, 0, 10), + CLK_CONSTANTS(I2S1, 0, 11), + CLK_CONSTANTS(I2C1, 0, 12), + CLK_CONSTANTS(NDFLASH, 0, 13), + CLK_CONSTANTS(SDMMC1, 0, 14), + CLK_CONSTANTS(SDMMC4, 0, 15), + CLK_CONSTANTS(PWM, 0, 17), + CLK_CONSTANTS(I2S2, 0, 18), + CLK_CONSTANTS(EPP, 0, 19), + CLK_CONSTANTS(VI, 0, 20), + CLK_CONSTANTS(2D, 0, 21), + CLK_CONSTANTS(USBD, 0, 22), + CLK_CONSTANTS(ISP, 0, 23), + CLK_CONSTANTS(3D, 0, 24), + CLK_CONSTANTS(DISP2, 0, 26), + CLK_CONSTANTS(DISP1, 0, 27), + CLK_CONSTANTS(HOST1X, 0, 28), + CLK_CONSTANTS(VCP, 0, 29), + CLK_CONSTANTS(I2S0, 0, 30), + CLK_CONSTANTS(CACHE2, 0, 31), + + CLK_CONSTANTS(MEM, 1, 0), + CLK_CONSTANTS(AHBDMA, 1, 1), + CLK_CONSTANTS(APBDMA, 1, 2), + CLK_CONSTANTS(KBC, 1, 4), + CLK_CONSTANTS(STAT_MON, 1, 5), + CLK_CONSTANTS(PMC, 1, 6), + CLK_CONSTANTS(FUSE, 1, 7), + CLK_CONSTANTS(KFUSE, 1, 8), + CLK_CONSTANTS(SBC1, 1, 9), + CLK_CONSTANTS(SNOR, 1, 10), + CLK_CONSTANTS(JTAG2TBC, 1, 11), + CLK_CONSTANTS(SBC2, 1, 12), + CLK_CONSTANTS(SBC3, 1, 14), + CLK_CONSTANTS(I2C5, 1, 15), + CLK_CONSTANTS(DSI, 1, 16), + CLK_CONSTANTS(HSI, 1, 18), + CLK_CONSTANTS(HDMI, 1, 19), + CLK_CONSTANTS(CSI, 1, 20), + CLK_CONSTANTS(I2C2, 1, 22), + CLK_CONSTANTS(UARTC, 1, 23), + CLK_CONSTANTS(MIPI_CAL, 1, 24), + CLK_CONSTANTS(EMC, 1, 25), + CLK_CONSTANTS(USB2, 1, 26), + CLK_CONSTANTS(USB3, 1, 27), + CLK_CONSTANTS(MPE, 1, 28), + CLK_CONSTANTS(VDE, 1, 29), + CLK_CONSTANTS(BSEA, 1, 30), + CLK_CONSTANTS(BSEV, 1, 31), + + CLK_CONSTANTS(UARTD, 2, 1), + CLK_CONSTANTS(UARTE, 2, 2), + CLK_CONSTANTS(I2C3, 2, 3), + CLK_CONSTANTS(SBC4, 2, 4), + CLK_CONSTANTS(SDMMC3, 2, 5), + CLK_CONSTANTS(PCIE, 2, 6), + CLK_CONSTANTS(OWR, 2, 7), + CLK_CONSTANTS(AFI, 2, 8), + CLK_CONSTANTS(CSITE, 2, 9), + CLK_CONSTANTS(PCIEXCLK, 2, 10), + CLK_CONSTANTS(AVPUCQ, 2, 11), + CLK_CONSTANTS(TRACECLKIN, 2, 13), + CLK_CONSTANTS(SOC_THERM, 2, 14), + CLK_CONSTANTS(DTV, 2, 15), + CLK_CONSTANTS(NAND_SPEED, 2, 16), + CLK_CONSTANTS(I2C_SLOW, 2, 17), + CLK_CONSTANTS(DSIB, 2, 18), + CLK_CONSTANTS(TSEC, 2, 19), + CLK_CONSTANTS(IRAMA, 2, 20), + CLK_CONSTANTS(IRAMB, 2, 21), + CLK_CONSTANTS(IRAMC, 2, 22), + + // Clock reset. + CLK_CONSTANTS(EMUCIF, 2, 23), + // Clock enable. + CLK_CONSTANTS(IRAMD, 2, 23), + + CLK_CONSTANTS(CRAM2, 2, 24), + CLK_CONSTANTS(XUSB_HOST, 2, 25), + CLK_CONSTANTS(MSENC, 2, 27), + CLK_CONSTANTS(SUS_OUT, 2, 28), + CLK_CONSTANTS(DEV2_OUT, 2, 29), + CLK_CONSTANTS(DEV1_OUT, 2, 30), + CLK_CONSTANTS(XUSB_DEV, 2, 31), + + CLK_CONSTANTS(VW_CPUG, 0, 0), + CLK_CONSTANTS(VW_CPULP, 0, 1), + CLK_CONSTANTS(VW_3D2, 0, 2), + CLK_CONSTANTS(VW_MSELECT, 0, 3), + CLK_CONSTANTS(VW_I2S3, 0, 5), + CLK_CONSTANTS(VW_I2S4, 0, 6), + CLK_CONSTANTS(VW_I2C4, 0, 7), + CLK_CONSTANTS(VW_SBC5, 0, 8), + CLK_CONSTANTS(VW_SBC6, 0, 9), + CLK_CONSTANTS(VW_AUDIO, 0, 10), + CLK_CONSTANTS(VW_APBIF, 0, 11), + CLK_CONSTANTS(VW_DAM0, 0, 12), + CLK_CONSTANTS(VW_DAM1, 0, 13), + CLK_CONSTANTS(VW_DAM2, 0, 14), + CLK_CONSTANTS(VW_HDA2CODEC_2X, 0, 15), + CLK_CONSTANTS(VW_ATOMICS, 0, 16), + CLK_CONSTANTS(VW_ACTMON, 0, 23), + CLK_CONSTANTS(VW_SATA, 0, 28), + CLK_CONSTANTS(VW_HDA, 0, 29), + + CLK_CONSTANTS(VW_HDA2HDMICODEC, 1, 0), + CLK_CONSTANTS(VW_SATACOLD, 1, 1), + CLK_CONSTANTS(VW_CEC, 1, 8), + CLK_CONSTANTS(VW_XUSB_PADCTL, 1, 14), + CLK_CONSTANTS(VW_ENTROPY, 1, 21), + CLK_CONSTANTS(VW_AMX0, 1, 25), + CLK_CONSTANTS(VW_ADX0, 1, 26), + CLK_CONSTANTS(VW_DVFS, 1, 27), + CLK_CONSTANTS(VW_XUSB_SS, 1, 28), + CLK_CONSTANTS(VW_MC1, 1, 30), + CLK_CONSTANTS(VW_EMC1, 1, 31), +}; + +/* PLL stabilization delay in usec */ +#define CLOCK_PLL_STABLE_DELAY_US 300 + +#define IO_STABILIZATION_DELAY (2) +/* Calculate clock fractional divider value from ref and target frequencies */ +#define CLK_DIVIDER(REF, FREQ) ((((REF) * 2) / FREQ) - 2) + +/* Calculate clock frequency value from reference and clock divider value */ +#define CLK_FREQUENCY(REF, REG) (((REF) * 2) / (REG + 2)) + +/* soc-specific */ +#define NVBL_PLLP_KHZ (408000) + +/* make this a macro, rather than a function; let the C compiler find + * the error for you if you use an out of range index.. Requires you + * to declare a clk_rst pointer. */ +void init_pllx(void); +#define clkreset(x) &clk_rst->crc_rst_dev[(x)] +#define clkenable(x) &clk_rst->crc_clk_out_enb[(x)] +#define clkresetvw(x) &clk_rst->crc_rst_dev_vw[(x)] +#define clkenablevw(x) &clk_rst->crc_clk_out_enb_vw[(x)] + void set_avp_clock_to_clkm(void); +void init_clocks(void); #endif /* __SOC_NVIDIA_TEGRA124_CLOCK_H__ */ diff --git a/src/soc/nvidia/tegra124/flow.h b/src/soc/nvidia/tegra124/flow.h new file mode 100644 index 0000000..a974f09 --- /dev/null +++ b/src/soc/nvidia/tegra124/flow.h @@ -0,0 +1,49 @@ +/* + * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef _TEGRA124_FLOW_H_ +#define _TEGRA124_FLOW_H_ + +struct flow_ctlr { + u32 halt_cpu_events; /* offset 0x00 */ + u32 halt_cop_events; /* offset 0x04 */ + u32 cpu_csr; /* offset 0x08 */ + u32 cop_csr; /* offset 0x0c */ + u32 xrq_events; /* offset 0x10 */ + u32 halt_cpu1_events; /* offset 0x14 */ + u32 cpu1_csr; /* offset 0x18 */ + u32 halt_cpu2_events; /* offset 0x1c */ + u32 cpu2_csr; /* offset 0x20 */ + u32 halt_cpu3_events; /* offset 0x24 */ + u32 cpu3_csr; /* offset 0x28 */ + u32 cluster_control; /* offset 0x2c */ + u32 halt_cop1_events; /* offset 0x30 */ + u32 halt_cop1_csr; /* offset 0x34 */ + u32 cpu_pwr_csr; /* offset 0x38 */ + u32 mpid; /* offset 0x3c */ + u32 ram_repair; /* offset 0x40 */ +}; + +/* HALT_COP_EVENTS_0, 0x04 */ +#define EVENT_MSEC (1 << 24) +#define EVENT_USEC (1 << 25) +#define EVENT_JTAG (1 << 28) +#define EVENT_MODE_STOP (2 << 29) + +/* FLOW_CTLR_CLUSTER_CONTROL_0 0x2c */ +#define ACTIVE_LP (1 << 0) + +#endif /* _TEGRA124_FLOW_H_ */ diff --git a/src/soc/nvidia/tegra124/pmc.h b/src/soc/nvidia/tegra124/pmc.h new file mode 100644 index 0000000..0e783fc --- /dev/null +++ b/src/soc/nvidia/tegra124/pmc.h @@ -0,0 +1,377 @@ +/* + * Copyright (c) 2010 - 2013, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef _TEGRA124_PMC_H_ +#define _TEGRA124_PMC_H_ + +/* Power Management Controller (APBDEV_PMC_) registers */ +struct pmc_ctlr { + u32 pmc_cntrl; /* _CNTRL_0, offset 00 */ + u32 pmc_sec_disable; /* _SEC_DISABLE_0, offset 04 */ + u32 pmc_pmc_swrst; /* _PMC_SWRST_0, offset 08 */ + u32 pmc_wake_mask; /* _WAKE_MASK_0, offset 0C */ + u32 pmc_wake_lvl; /* _WAKE_LVL_0, offset 10 */ + u32 pmc_wake_status; /* _WAKE_STATUS_0, offset 14 */ + u32 pmc_sw_wake_status; /* _SW_WAKE_STATUS_0, offset 18 */ + u32 pmc_dpd_pads_oride; /* _DPD_PADS_ORIDE_0, offset 1C */ + u32 pmc_dpd_sample; /* _DPD_PADS_SAMPLE_0, offset 20 */ + u32 pmc_dpd_enable; /* _DPD_PADS_ENABLE_0, offset 24 */ + u32 pmc_pwrgate_timer_off; /* _PWRGATE_TIMER_OFF_0, offset 28 */ + u32 pmc_clamp_status; /* _PMC_CLAMP_STATUS_0, offset 2C */ + u32 pmc_pwrgate_toggle; /* _PWRGATE_TOGGLE_0, offset 30 */ + u32 pmc_remove_clamping; /* _REMOVE_CLAMPING_CMD_0, offset 34 */ + u32 pmc_pwrgate_status; /* _PWRGATE_STATUS_0, offset 38 */ + u32 pmc_pwrgood_timer; /* _PWRGOOD_TIMER_0, offset 3C */ + u32 pmc_blink_timer; /* _BLINK_TIMER_0, offset 40 */ + u32 pmc_no_iopower; /* _NO_IOPOWER_0, offset 44 */ + u32 pmc_pwr_det; /* _PWR_DET_0, offset 48 */ + u32 pmc_pwr_det_latch; /* _PWR_DET_LATCH_0, offset 4C */ + + u32 pmc_scratch0; /* _SCRATCH0_0, offset 50 */ + u32 pmc_scratch1; /* _SCRATCH1_0, offset 54 */ + u32 pmc_scratch2; /* _SCRATCH2_0, offset 58 */ + u32 pmc_scratch3; /* _SCRATCH3_0, offset 5C */ + u32 pmc_scratch4; /* _SCRATCH4_0, offset 60 */ + u32 pmc_scratch5; /* _SCRATCH5_0, offset 64 */ + u32 pmc_scratch6; /* _SCRATCH6_0, offset 68 */ + u32 pmc_scratch7; /* _SCRATCH7_0, offset 6C */ + u32 pmc_scratch8; /* _SCRATCH8_0, offset 70 */ + u32 pmc_scratch9; /* _SCRATCH9_0, offset 74 */ + u32 pmc_scratch10; /* _SCRATCH10_0, offset 78 */ + u32 pmc_scratch11; /* _SCRATCH11_0, offset 7C */ + u32 pmc_scratch12; /* _SCRATCH12_0, offset 80 */ + u32 pmc_scratch13; /* _SCRATCH13_0, offset 84 */ + u32 pmc_scratch14; /* _SCRATCH14_0, offset 88 */ + u32 pmc_scratch15; /* _SCRATCH15_0, offset 8C */ + u32 pmc_scratch16; /* _SCRATCH16_0, offset 90 */ + u32 pmc_scratch17; /* _SCRATCH17_0, offset 94 */ + u32 pmc_scratch18; /* _SCRATCH18_0, offset 98 */ + u32 pmc_scratch19; /* _SCRATCH19_0, offset 9C */ + u32 pmc_scratch20; /* _SCRATCH20_0, offset A0 */ + u32 pmc_scratch21; /* _SCRATCH21_0, offset A4 */ + u32 pmc_scratch22; /* _SCRATCH22_0, offset A8 */ + u32 pmc_scratch23; /* _SCRATCH23_0, offset AC */ + + u32 pmc_secure_scratch0; /* _SECURE_SCRATCH0_0, offset B0 */ + u32 pmc_secure_scratch1; /* _SECURE_SCRATCH1_0, offset B4 */ + u32 pmc_secure_scratch2; /* _SECURE_SCRATCH2_0, offset B8 */ + u32 pmc_secure_scratch3; /* _SECURE_SCRATCH3_0, offset BC */ + u32 pmc_secure_scratch4; /* _SECURE_SCRATCH4_0, offset C0 */ + u32 pmc_secure_scratch5; /* _SECURE_SCRATCH5_0, offset C4 */ + + u32 pmc_cpupwrgood_timer; /* _CPUPWRGOOD_TIMER_0, offset C8 */ + u32 pmc_cpupwroff_timer; /* _CPUPWROFF_TIMER_0, offset CC */ + u32 pmc_pg_mask; /* _PG_MASK_0, offset D0 */ + u32 pmc_pg_mask_1; /* _PG_MASK_1_0, offset D4 */ + u32 pmc_auto_wake_lvl; /* _AUTO_WAKE_LVL_0, offset D8 */ + u32 pmc_auto_wake_lvl_mask; /* _AUTO_WAKE_LVL_MASK_0, offset DC */ + u32 pmc_wake_delay; /* _WAKE_DELAY_0, offset E0 */ + u32 pmc_pwr_det_val; /* _PWR_DET_VAL_0, offset E4 */ + u32 pmc_ddr_pwr; /* _DDR_PWR_0, offset E8 */ + u32 pmc_usb_debounce_del; /* _USB_DEBOUNCE_DEL_0, offset EC */ + u32 pmc_usb_ao; /* _USB_AO_0, offset F0 */ + u32 pmc_crypto_op; /* _CRYPTO_OP__0, offset F4 */ + u32 pmc_pllp_wb0_override; /* _PLLP_WB0_OVERRIDE_0, offset F8 */ + + u32 pmc_scratch24; /* _SCRATCH24_0, offset FC */ + u32 pmc_scratch25; /* _SCRATCH24_0, offset 100 */ + u32 pmc_scratch26; /* _SCRATCH24_0, offset 104 */ + u32 pmc_scratch27; /* _SCRATCH24_0, offset 108 */ + u32 pmc_scratch28; /* _SCRATCH24_0, offset 10C */ + u32 pmc_scratch29; /* _SCRATCH24_0, offset 110 */ + u32 pmc_scratch30; /* _SCRATCH24_0, offset 114 */ + u32 pmc_scratch31; /* _SCRATCH24_0, offset 118 */ + u32 pmc_scratch32; /* _SCRATCH24_0, offset 11C */ + u32 pmc_scratch33; /* _SCRATCH24_0, offset 120 */ + u32 pmc_scratch34; /* _SCRATCH24_0, offset 124 */ + u32 pmc_scratch35; /* _SCRATCH24_0, offset 128 */ + u32 pmc_scratch36; /* _SCRATCH24_0, offset 12C */ + u32 pmc_scratch37; /* _SCRATCH24_0, offset 130 */ + u32 pmc_scratch38; /* _SCRATCH24_0, offset 134 */ + u32 pmc_scratch39; /* _SCRATCH24_0, offset 138 */ + u32 pmc_scratch40; /* _SCRATCH24_0, offset 13C */ + u32 pmc_scratch41; /* _SCRATCH24_0, offset 140 */ + u32 pmc_scratch42; /* _SCRATCH24_0, offset 144 */ + + u32 pmc_bo_mirror0; /* _BOUNDOUT_MIRROR0_0, offset 148 */ + u32 pmc_bo_mirror1; /* _BOUNDOUT_MIRROR1_0, offset 14C */ + u32 pmc_bo_mirror2; /* _BOUNDOUT_MIRROR2_0, offset 150 */ + u32 pmc_sys_33v_en; /* _SYS_33V_EN_0, offset 154 */ + u32 pmc_bo_mirror_access; /* _BOUNDOUT_MIRROR_ACCESS_0, off158 */ + u32 pmc_gate; /* _GATE_0, offset 15C */ + u32 pmc_wake2_mask; /* _WAKE2_MASK_0, offset 160 */ + u32 pmc_wake2_lvl; /* _WAKE2_LVL_0, offset 164 */ + u32 pmc_wake2_stat; /* _WAKE2_STATUS_0, offset 168 */ + u32 pmc_sw_wake2_stat; /* _SW_WAKE2_STATUS_0, offset 16C */ + u32 pmc_auto_wake2_lvl_mask; /* _AUTO_WAKE2_LVL_MASK_0, offset 170 */ + u32 pmc_pg_mask2; /* _PG_MASK_2_0, offset 174 */ + u32 pmc_pg_mask_ce1; /* _PG_MASK_CE1_0, offset 178 */ + u32 pmc_pg_mask_ce2; /* _PG_MASK_CE2_0, offset 17C */ + u32 pmc_pg_mask_ce3; /* _PG_MASK_CE3_0, offset 180 */ + u32 pmc_pwrgate_timer_ce0; /* _PWRGATE_TIMER_CE_0_0, offset 184 */ + u32 pmc_pwrgate_timer_ce1; /* _PWRGATE_TIMER_CE_1_0, offset 188 */ + u32 pmc_pwrgate_timer_ce2; /* _PWRGATE_TIMER_CE_2_0, offset 18C */ + u32 pmc_pwrgate_timer_ce3; /* _PWRGATE_TIMER_CE_3_0, offset 190 */ + u32 pmc_pwrgate_timer_ce4; /* _PWRGATE_TIMER_CE_4_0, offset 194 */ + u32 pmc_pwrgate_timer_ce5; /* _PWRGATE_TIMER_CE_5_0, offset 198 */ + u32 pmc_pwrgate_timer_ce6; /* _PWRGATE_TIMER_CE_6_0, offset 19C */ + u32 pmc_pcx_edpd_cntrl; /* _PCX_EDPD_CNTRL_0, offset 1A0 */ + u32 pmc_osc_edpd_over; /* _OSC_EDPD_OVER_0, offset 1A4 */ + u32 pmc_clk_out_cntrl; /* _CLK_OUT_CNTRL_0, offset 1A8 */ + u32 pmc_sata_pwrgate; /* _SATA_PWRGT_0, offset 1AC */ + u32 pmc_sensor_ctrl; /* _SENSOR_CTRL_0, offset 1B0 */ + u32 pmc_reset_status; /* _RTS_STATUS_0, offset 1B4 */ + u32 pmc_io_dpd_req; /* _IO_DPD_REQ_0, offset 1B8 */ + u32 pmc_io_dpd_stat; /* _IO_DPD_STATUS_0, offset 1BC */ + u32 pmc_io_dpd2_req; /* _IO_DPD2_REQ_0, offset 1C0 */ + u32 pmc_io_dpd2_stat; /* _IO_DPD2_STATUS_0, offset 1C4 */ + u32 pmc_sel_dpd_tim; /* _SEL_DPD_TIM_0, offset 1C8 */ + u32 pmc_vddp_sel; /* _VDDP_SEL_0, offset 1CC */ + + u32 pmc_ddr_cfg; /* _DDR_CFG_0, offset 1D0 */ + u32 pmc_e_no_vttgen; /* _E_NO_VTTGEN_0, offset 1D4 */ + u32 pmc_reserved0; /* _RESERVED, offset 1D8 */ + u32 pmc_pllm_wb0_ovrride_frq; /* _PLLM_WB0_OVERRIDE_FREQ_0, off 1DC */ + u32 pmc_test_pwrgate; /* _TEST_PWRGATE_0, offset 1E0 */ + u32 pmc_pwrgate_timer_mult; /* _PWRGATE_TIMER_MULT_0, offset 1E4 */ + u32 pmc_dsi_sel_dpd; /* _DSI_SEL_DPD_0, offset 1E8 */ + u32 pmc_utmip_uhsic_triggers; /* _UTMIP_UHSIC_TRIGGERS_0, off 1EC */ + u32 pmc_utmip_uhsic_saved_st; /* _UTMIP_UHSIC_SAVED_STATE_0, off1F0 */ + u32 pmc_utmip_pad_cfg; /* _UTMIP_PAD_CFG_0, offset 1F4 */ + u32 pmc_utmip_term_pad_cfg; /* _UTMIP_TERM_PAD_CFG_0, offset 1F8 */ + u32 pmc_utmip_uhsic_sleep_cfg; /* _UTMIP_UHSIC_SLEEP_CFG_0, off 1FC */ + + u32 pmc_todo_0[9]; /* offset 200-220 */ + u32 pmc_secure_scratch6; /* _SECURE_SCRATCH6_0, offset 224 */ + u32 pmc_secure_scratch7; /* _SECURE_SCRATCH7_0, offset 228 */ + u32 pmc_scratch43; /* _SCRATCH43_0, offset 22C */ + u32 pmc_scratch44; /* _SCRATCH44_0, offset 230 */ + u32 pmc_scratch45; + u32 pmc_scratch46; + u32 pmc_scratch47; + u32 pmc_scratch48; + u32 pmc_scratch49; + u32 pmc_scratch50; + u32 pmc_scratch51; + u32 pmc_scratch52; + u32 pmc_scratch53; + u32 pmc_scratch54; + u32 pmc_scratch55; /* _SCRATCH55_0, offset 25C */ + u32 pmc_scratch0_eco; /* _SCRATCH0_ECO_0, offset 260 */ + u32 pmc_por_dpd_ctrl; /* _POR_DPD_CTRL_0, offset 264 */ + u32 pmc_scratch2_eco; /* _SCRATCH2_ECO_0, offset 268 */ + u32 pmc_todo_1[17]; /* TODO: 26C ~ 2AC */ + u32 pmc_pllm_wb0_override2; /* _PLLM_WB0_OVERRIDE2, offset 2B0 */ + u32 pmc_tsc_mult; /* _TSC_MULT_0, offset 2B4 */ + u32 pmc_cpu_vsense_override; /* _CPU_VSENSE_OVERRIDE_0, offset 2B8 */ + u32 pmc_glb_amap_cfg; /* _GLB_AMAP_CFG_0, offset 2BC */ + u32 pmc_sticky_bits; /* _STICKY_BITS_0, offset 2C0 */ + u32 pmc_sec_disable2; /* _SEC_DISALBE2, offset 2C4 */ + u32 pmc_weak_bias; /* _WEAK_BIAS_0, offset 2C8 */ + u32 pmc_todo_3[13]; /* TODO: 2CC ~ 2FC */ + u32 pmc_secure_scratch8; /* _SECURE_SCRATCH8_0, offset 300 */ + u32 pmc_secure_scratch9; + u32 pmc_secure_scratch10; + u32 pmc_secure_scratch11; + u32 pmc_secure_scratch12; + u32 pmc_secure_scratch13; + u32 pmc_secure_scratch14; + u32 pmc_secure_scratch15; + u32 pmc_secure_scratch16; + u32 pmc_secure_scratch17; + u32 pmc_secure_scratch18; + u32 pmc_secure_scratch19; + u32 pmc_secure_scratch20; + u32 pmc_secure_scratch21; + u32 pmc_secure_scratch22; + u32 pmc_secure_scratch23; + u32 pmc_secure_scratch24; /* _SECURE_SCRATCH24_0, offset 340 */ + u32 pmc_secure_scratch25; + u32 pmc_secure_scratch26; + u32 pmc_secure_scratch27; + u32 pmc_secure_scratch28; + u32 pmc_secure_scratch29; + u32 pmc_secure_scratch30; + u32 pmc_secure_scratch31; + u32 pmc_secure_scratch32; + u32 pmc_secure_scratch33; + u32 pmc_secure_scratch34; + u32 pmc_secure_scratch35; /* _SECURE_SCRATCH35_0, offset 36C */ + + u32 pmc_reserved1[52]; /* RESERVED: 370 ~ 43C */ + u32 pmc_cntrl2; /* _CNTRL2_0, offset 440 */ + u32 pmc_reserved2[6]; /* RESERVED: 444 ~ 458 */ + u32 pmc_io_dpd3_req; /* _IO_DPD3_REQ_0, offset 45c */ + u32 pmc_io_dpd3_stat; /* _IO_DPD3_STATUS_0, offset 460 */ + u32 pmc_strap_opt_a; /* _STRAPPING_OPT_A_0, offset 464 */ + u32 pmc_reserved3[102]; /* RESERVED: 468 ~ 5FC */ + + u32 pmc_scratch56; /* _SCRATCH56_0, offset 600 */ + u32 pmc_scratch57; + u32 pmc_scratch58; + u32 pmc_scratch59; + u32 pmc_scratch60; + u32 pmc_scratch61; + u32 pmc_scratch62; + u32 pmc_scratch63; + u32 pmc_scratch64; + u32 pmc_scratch65; + u32 pmc_scratch66; + u32 pmc_scratch67; + u32 pmc_scratch68; + u32 pmc_scratch69; + u32 pmc_scratch70; + u32 pmc_scratch71; + u32 pmc_scratch72; + u32 pmc_scratch73; + u32 pmc_scratch74; + u32 pmc_scratch75; + u32 pmc_scratch76; + u32 pmc_scratch77; + u32 pmc_scratch78; + u32 pmc_scratch79; + u32 pmc_scratch80; + u32 pmc_scratch81; + u32 pmc_scratch82; + u32 pmc_scratch83; + u32 pmc_scratch84; + u32 pmc_scratch85; + u32 pmc_scratch86; + u32 pmc_scratch87; + u32 pmc_scratch88; + u32 pmc_scratch89; + u32 pmc_scratch90; + u32 pmc_scratch91; + u32 pmc_scratch92; + u32 pmc_scratch93; + u32 pmc_scratch94; + u32 pmc_scratch95; + u32 pmc_scratch96; + u32 pmc_scratch97; + u32 pmc_scratch98; + u32 pmc_scratch99; + u32 pmc_scratch100; + u32 pmc_scratch101; + u32 pmc_scratch102; + u32 pmc_scratch103; + u32 pmc_scratch104; + u32 pmc_scratch105; + u32 pmc_scratch106; + u32 pmc_scratch107; + u32 pmc_scratch108; + u32 pmc_scratch109; + u32 pmc_scratch110; + u32 pmc_scratch111; + u32 pmc_scratch112; + u32 pmc_scratch113; + u32 pmc_scratch114; + u32 pmc_scratch115; + u32 pmc_scratch116; + u32 pmc_scratch117; + u32 pmc_scratch118; + u32 pmc_scratch119; + u32 pmc_scratch1_eco; /* offset 700 */ +}; + +#define CPU_PWRED 1 +#define CPU_CLMP 1 + +#define PARTID_CP 0xFFFFFFF8 +#define START_CP (1 << 8) + +#define CPUPWRREQ_OE (1 << 16) +#define CPUPWRREQ_POL (1 << 15) + +#define CRAILID (0) +#define CE0ID (14) +#define C0NCID (15) +#define CRAIL (1 << CRAILID) +#define CE0 (1 << CE0ID) +#define C0NC (1 << C0NCID) + +#define PMC_XOFS_SHIFT 1 +#define PMC_XOFS_MASK (0x3F << PMC_XOFS_SHIFT) + +#define TIMER_MULT_SHIFT 0 +#define TIMER_MULT_MASK (3 << TIMER_MULT_SHIFT) +#define TIMER_MULT_CPU_SHIFT 2 +#define TIMER_MULT_CPU_MASK (3 << TIMER_MULT_CPU_SHIFT) +#define MULT_1 0 +#define MULT_2 1 +#define MULT_4 2 +#define MULT_8 3 + +#define AMAP_WRITE_SHIFT 20 +#define AMAP_WRITE_ON (1 << AMAP_WRITE_SHIFT) + +/* SEC_DISABLE_0, 0x04 */ +#define SEC_DISABLE_WRITE0_ON (1 << 4) +#define SEC_DISABLE_READ0_ON (1 << 5) +#define SEC_DISABLE_WRITE1_ON (1 << 6) +#define SEC_DISABLE_READ1_ON (1 << 7) +#define SEC_DISABLE_WRITE2_ON (1 << 8) +#define SEC_DISABLE_READ2_ON (1 << 9) +#define SEC_DISABLE_WRITE3_ON (1 << 10) +#define SEC_DISABLE_READ3_ON (1 << 11) +#define SEC_DISABLE_AMAP_WRITE_ON (1 << 20) + +/* APBDEV_PMC_PWRGATE_TOGGLE_0 0x30 */ +#define PWRGATE_TOGGLE_PARTID_CRAIL 0 +#define PWRGATE_TOGGLE_PARTID_TD 1 +#define PWRGATE_TOGGLE_PARTID_VE 2 +#define PWRGATE_TOGGLE_PARTID_VDE 4 +#define PWRGATE_TOGGLE_PARTID_L2C 5 +#define PWRGATE_TOGGLE_PARTID_MPE 6 +#define PWRGATE_TOGGLE_PARTID_HEG 7 +#define PWRGATE_TOGGLE_PARTID_CE1 9 +#define PWRGATE_TOGGLE_PARTID_CE2 10 +#define PWRGATE_TOGGLE_PARTID_CE3 11 +#define PWRGATE_TOGGLE_PARTID_CELP 12 +#define PWRGATE_TOGGLE_PARTID_CE0 14 +#define PWRGATE_TOGGLE_PARTID_C0NC 15 +#define PWRGATE_TOGGLE_PARTID_C1NC 16 +#define PWRGATE_TOGGLE_PARTID_DIS 18 +#define PWRGATE_TOGGLE_PARTID_DISB 19 +#define PWRGATE_TOGGLE_PARTID_XUSBA 20 +#define PWRGATE_TOGGLE_PARTID_XUSBB 21 +#define PWRGATE_TOGGLE_PARTID_XUSBC 22 +#define PWRGATE_TOGGLE_START (1 << 8) + +/* APBDEV_PMC_PWRGATE_STATUS_0 0x38 */ +#define PWRGATE_STATUS_CRAIL_ENABLE (1 << 0) +#define PWRGATE_STATUS_TD_ENABLE (1 << 1) +#define PWRGATE_STATUS_VE_ENABLE (1 << 2) +#define PWRGATE_STATUS_VDE_ENABLE (1 << 4) +#define PWRGATE_STATUS_L2C_ENABLE (1 << 5) +#define PWRGATE_STATUS_MPE_ENABLE (1 << 6) +#define PWRGATE_STATUS_HEG_ENABLE (1 << 7) +#define PWRGATE_STATUS_CE1_ENABLE (1 << 9) +#define PWRGATE_STATUS_CE2_ENABLE (1 << 10) +#define PWRGATE_STATUS_CE3_ENABLE (1 << 11) +#define PWRGATE_STATUS_CELP_ENABLE (1 << 12) +#define PWRGATE_STATUS_CE0_ENABLE (1 << 14) +#define PWRGATE_STATUS_C0NC_ENABLE (1 << 15) +#define PWRGATE_STATUS_C1NC_ENABLE (1 << 16) +#define PWRGATE_STATUS_DIS_ENABLE (1 << 18) +#define PWRGATE_STATUS_DISB_ENABLE (1 << 19) +#define PWRGATE_STATUS_XUSBA_ENABLE (1 << 20) +#define PWRGATE_STATUS_XUSBB_ENABLE (1 << 21) +#define PWRGATE_STATUS_XUSBC_ENABLE (1 << 22) + +/* APBDEV_PMC_CNTRL2_0 0x440 */ +#define HOLD_CKE_LOW_EN (1 << 12) + +#endif /* _TEGRA124_PMC_H_ */

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New patch to review for coreboot: 7e3c16c tegra124: Make tegra124 compilable with serial turned off.
by Isaac Christensen 09 Sep '14

09 Sep '14

Isaac Christensen (isaac.christensen(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6862 -gerrit commit 7e3c16c7248fe326814af2a0c1d7961083c1952f Author: Gabe Black <gabeblack(a)google.com> Date: Wed Oct 9 23:45:07 2013 -0700 tegra124: Make tegra124 compilable with serial turned off. The bootblock and romstage UART consoles were being built in based only on whether or not the bootblock and romstage consoles were selected, ignoring whether serial console support was compiled in generally. Change-Id: I3866519c422a990c44ced66885108eff24894563 Signed-off-by: Gabe Black <gabeblack(a)google.com> Reviewed-on: https://chromium-review.googlesource.com/172580 Reviewed-by: Ronald Minnich <rminnich(a)chromium.org> Commit-Queue: Gabe Black <gabeblack(a)chromium.org> Tested-by: Gabe Black <gabeblack(a)chromium.org> (cherry picked from commit a4f2dd4902a05884693e6e350b6be29276d16981) Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com> --- src/soc/nvidia/tegra124/Makefile.inc | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/src/soc/nvidia/tegra124/Makefile.inc b/src/soc/nvidia/tegra124/Makefile.inc index a63eb35..4530ed6 100644 --- a/src/soc/nvidia/tegra124/Makefile.inc +++ b/src/soc/nvidia/tegra124/Makefile.inc @@ -11,17 +11,19 @@ bootblock-y += ../tegra/i2c.c bootblock-y += ../tegra/pingroup.c bootblock-y += ../tegra/pinmux.c bootblock-y += timer.c -bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += uart.c +ifeq ($(CONFIG_BOOTBLOCK_CONSOLE),y) +bootblock-$(CONFIG_CONSOLE_SERIAL) += uart.c +endif romstage-y += cbfs.c romstage-y += monotonic_timer.c romstage-y += timer.c -romstage-y += uart.c +romstage-$(CONFIG_CONSOLE_SERIAL) += uart.c ramstage-y += cbfs.c ramstage-y += monotonic_timer.c ramstage-y += timer.c -ramstage-y += uart.c +ramstage-$(CONFIG_CONSOLE_SERIAL) += uart.c CPPFLAGS_common += -Isrc/soc/nvidia/tegra124/include/

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New patch to review for coreboot: b7142cb nyan: Use the new pinmux functions as part of UART setup.
by Isaac Christensen 09 Sep '14

09 Sep '14

Isaac Christensen (isaac.christensen(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6861 -gerrit commit b7142cb796079e774ba8ef9faad9214c66f41344 Author: Gabe Black <gabeblack(a)google.com> Date: Fri Oct 4 06:17:22 2013 -0700 nyan: Use the new pinmux functions as part of UART setup. The pins for the UART had been configured manually using hardcoded offsets and values. Now that we have pinmux functions for that sort of thing, we should use that instead. This also provides a very simple test for the pinmux code. Ultimately this code should be wrapped in a function which handles setting up any of the UARTs which is appropriately parameterized and which would be called from the bootblock main instead of being in it, but for now this is sufficient. Old-Change-Id: I69e36fa5fc9b6f3f5ef7f1be3e9f18cdbfdd7fe9 Signed-off-by: Gabe Black <gabeblack(a)google.com> Reviewed-on: https://chromium-review.googlesource.com/171807 Reviewed-by: Ronald Minnich <rminnich(a)chromium.org> Reviewed-by: David Hendricks <dhendrix(a)chromium.org> Commit-Queue: Gabe Black <gabeblack(a)chromium.org> Tested-by: Gabe Black <gabeblack(a)chromium.org> (cherry picked from commit d29e655b68143e86199ab1d74f89e125b16b67cc) tegra124: Call the set_avp_clock_to_clkm function in the bootblock. We had a hardcoded version of the set_avp_clock_to_clkm function in the bootblock, and we had to use it until now because the real version uses udelay, and until now that hadn't been implemented. Also, replace the delay loop in the hacky_hardcoded_uart_setup_function with a call to the real thing. Old-Change-Id: I6df9421bcad484e0855c67649683d474d78e4883 Signed-off-by: Gabe Black <gabeblack(a)google.com> Reviewed-on: https://chromium-review.googlesource.com/172045 Reviewed-by: Gabe Black <gabeblack(a)chromium.org> Commit-Queue: Gabe Black <gabeblack(a)chromium.org> Tested-by: Gabe Black <gabeblack(a)chromium.org> (cherry picked from commit 4c6dd4c7cade7d922a258e0371e43972bce77249) Squashed two tegra124 bootblock related commits. Change-Id: I0ce6321a04b11b7f1250ef3816fe46732777988d Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com> --- src/soc/nvidia/tegra124/bootblock.c | 45 ++++++++++++------------------------- 1 file changed, 14 insertions(+), 31 deletions(-) diff --git a/src/soc/nvidia/tegra124/bootblock.c b/src/soc/nvidia/tegra124/bootblock.c index cd7ea34..a3bed23 100644 --- a/src/soc/nvidia/tegra124/bootblock.c +++ b/src/soc/nvidia/tegra124/bootblock.c @@ -21,37 +21,13 @@ #include <arch/io.h> #include <cbfs.h> #include <console/console.h> +#include <delay.h> + +#include "clock.h" +#include "pinmux.h" static void hacky_hardcoded_uart_setup_function(void) { - int i; - - /* - * On poweron, AVP clock source (also called system clock) is set to - * PLLP_out0 with frequency set at 1MHz. Before initializing PLLP, we - * need to move the system clock's source to CLK_M temporarily. And - * then switch it to PLLP_out4 (204MHz) at a later time. - */ - write32((0 << 12) | (0 << 8) | (0 << 4) | (0 << 0) | (2 << 28), - (void *)(0x60006000 + 0x28)); - - // wait a little bit (nominally 2-3 us) - for (i = 0; i < 0x10000; i++) - __asm__ __volatile__(""); - - // Set function. - setbits_le32((void *)(0x70000000 + 0x3000 + 0x2e0), 3 << 0); - setbits_le32((void *)(0x70000000 + 0x3000 + 0x2e4), 3 << 0); - - // Output. - clrbits_le32((void *)(0x70000000 + 0x3000 + 0x2e0), 1 << 5); - // Input. - setbits_le32((void *)(0x70000000 + 0x3000 + 0x2e4), 1 << 5); - - // Disable tristate. - clrbits_le32((void *)(0x70000000 + 0x3000 + 0x2e0), 1 << 4); - clrbits_le32((void *)(0x70000000 + 0x3000 + 0x2e4), 1 << 4); - // Assert UART reset and enable clock. setbits_le32((void *)(0x60006000 + 4 + 0), 1 << 6); @@ -61,9 +37,7 @@ static void hacky_hardcoded_uart_setup_function(void) // Set the clock source. clrbits_le32((void *)(0x60006000 + 0x100 + 4 * 0x1e), 3 << 30); - // wait a little bit (nominally 2us?) - for (i = 0; i < 0x10000; i++) - __asm__ __volatile__(""); + udelay(2); // De-assert reset to UART. clrbits_le32((void *)(0x60006000 + 4 + 0), 1 << 6); @@ -73,8 +47,17 @@ void main(void) { void *entry; + set_avp_clock_to_clkm(); + hacky_hardcoded_uart_setup_function(); + // Serial out, tristate off. + pinmux_set_config(PINMUX_KB_ROW9_INDEX, PINMUX_KB_ROW9_FUNC_UA3); + // Serial in, tristate_on. + pinmux_set_config(PINMUX_KB_ROW10_INDEX, PINMUX_KB_ROW10_FUNC_UA3 | + PINMUX_TRISTATE | + PINMUX_INPUT_ENABLE); + if (CONFIG_BOOTBLOCK_CONSOLE) console_init();

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New patch to review for coreboot: c366b9e nyan: Use the new pinmux functions as part of UART setup.
by Isaac Christensen 09 Sep '14

09 Sep '14

Isaac Christensen (isaac.christensen(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6860 -gerrit commit c366b9eb95409b25a113a25cff89c70aa3567883 Author: Gabe Black <gabeblack(a)google.com> Date: Fri Oct 4 06:17:22 2013 -0700 nyan: Use the new pinmux functions as part of UART setup. The pins for the UART had been configured manually using hardcoded offsets and values. Now that we have pinmux functions for that sort of thing, we should use that instead. This also provides a very simple test for the pinmux code. Ultimately this code should be wrapped in a function which handles setting up any of the UARTs which is appropriately parameterized and which would be called from the bootblock main instead of being in it, but for now this is sufficient. Change-Id: I69e36fa5fc9b6f3f5ef7f1be3e9f18cdbfdd7fe9 Signed-off-by: Gabe Black <gabeblack(a)google.com> Reviewed-on: https://chromium-review.googlesource.com/171807 Reviewed-by: Ronald Minnich <rminnich(a)chromium.org> Reviewed-by: David Hendricks <dhendrix(a)chromium.org> Commit-Queue: Gabe Black <gabeblack(a)chromium.org> Tested-by: Gabe Black <gabeblack(a)chromium.org> (cherry picked from commit d29e655b68143e86199ab1d74f89e125b16b67cc) Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com> --- src/soc/nvidia/tegra124/bootblock.c | 22 +++++++++------------- 1 file changed, 9 insertions(+), 13 deletions(-) diff --git a/src/soc/nvidia/tegra124/bootblock.c b/src/soc/nvidia/tegra124/bootblock.c index cd7ea34..3461c25 100644 --- a/src/soc/nvidia/tegra124/bootblock.c +++ b/src/soc/nvidia/tegra124/bootblock.c @@ -22,6 +22,8 @@ #include <cbfs.h> #include <console/console.h> +#include "pinmux.h" + static void hacky_hardcoded_uart_setup_function(void) { int i; @@ -39,19 +41,6 @@ static void hacky_hardcoded_uart_setup_function(void) for (i = 0; i < 0x10000; i++) __asm__ __volatile__(""); - // Set function. - setbits_le32((void *)(0x70000000 + 0x3000 + 0x2e0), 3 << 0); - setbits_le32((void *)(0x70000000 + 0x3000 + 0x2e4), 3 << 0); - - // Output. - clrbits_le32((void *)(0x70000000 + 0x3000 + 0x2e0), 1 << 5); - // Input. - setbits_le32((void *)(0x70000000 + 0x3000 + 0x2e4), 1 << 5); - - // Disable tristate. - clrbits_le32((void *)(0x70000000 + 0x3000 + 0x2e0), 1 << 4); - clrbits_le32((void *)(0x70000000 + 0x3000 + 0x2e4), 1 << 4); - // Assert UART reset and enable clock. setbits_le32((void *)(0x60006000 + 4 + 0), 1 << 6); @@ -75,6 +64,13 @@ void main(void) hacky_hardcoded_uart_setup_function(); + // Serial out, tristate off. + pinmux_set_config(PINMUX_KB_ROW9_INDEX, PINMUX_KB_ROW9_FUNC_UA3); + // Serial in, tristate_on. + pinmux_set_config(PINMUX_KB_ROW10_INDEX, PINMUX_KB_ROW10_FUNC_UA3 | + PINMUX_TRISTATE | + PINMUX_INPUT_ENABLE); + if (CONFIG_BOOTBLOCK_CONSOLE) console_init();

1 0

Patch set updated for coreboot: e9b9421 nvidia-cbootimage: integrate into coreboot make
by Isaac Christensen 09 Sep '14

09 Sep '14

Isaac Christensen (isaac.christensen(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6851 -gerrit commit e9b9421caf7ad3bf1af3433eb2735eca024000f5 Author: Isaac Christensen <isaac.christensen(a)se-eng.com> Date: Mon Sep 8 15:28:17 2014 -0600 nvidia-cbootimage: integrate into coreboot make Add rules for building the nvidia-cbootimage utility and add dependencies to the tegra124 platform. Change-Id: Ia9f26981bccd217fe79e1b5dd432ee7da868d22a Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com> --- Makefile.inc | 16 ++++++++++++++-- src/soc/nvidia/tegra124/Makefile.inc | 6 ++---- 2 files changed, 16 insertions(+), 6 deletions(-) diff --git a/Makefile.inc b/Makefile.inc index 00e1a6c..c41945a 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -228,7 +228,8 @@ endif CFLAGS_common += -fno-common -ffreestanding -fno-builtin -fomit-frame-pointer additional-dirs := $(objutil)/cbfstool $(objutil)/romcc $(objutil)/ifdtool \ - $(objutil)/ifdfake $(objutil)/options $(objutil)/fletcher + $(objutil)/ifdfake $(objutil)/options $(objutil)/fletcher \ + $(objutil)/cbootimage ####################################################################### # generate build support files @@ -305,6 +306,17 @@ $(FLETCHER): $(top)/util/fletcher/fletcher.c @printf " HOSTCC $(subst $(obj)/,,$(@))\n" $(HOSTCC) $(HOSTCFLAGS) -o $@ $< +CBOOTIMAGE:=$(objutil)/cbootimage/cbootimage + +$(CBOOTIMAGE): $(top)/util/nvidia-cbootimage/Makefile + @printf " MAKE $(subst $(obj)/,,$(@))\n" + $(MAKE) -C $(top)/util/nvidia-cbootimage + cp $(top)/util/nvidia-cbootimage/src/cbootimage $@ + +$(top)/util/nvidia-cbootimage/Makefile: + cd $(top)/util/nvidia-cbootimage/; \ + ./autogen.sh >/dev/null + ####################################################################### # needed objects that every mainboard uses # Creation of these is architecture and mainboard independent @@ -413,7 +425,7 @@ crosstools-arm: clean-for-update crossgcc-clean: clean-for-update $(MAKE) -C util/crossgcc clean -tools: $(objutil)/kconfig/conf $(objutil)/cbfstool/cbfstool $(objutil)/cbfstool/rmodtool $(objutil)/nvramtool/nvramtool $(ROMCC_BIN) $(objutil)/sconfig/sconfig $(IFDTOOL) $(IFDFAKE) +tools: $(objutil)/kconfig/conf $(objutil)/cbfstool/cbfstool $(objutil)/cbfstool/rmodtool $(objutil)/nvramtool/nvramtool $(ROMCC_BIN) $(objutil)/sconfig/sconfig $(IFDTOOL) $(IFDFAKE) $(CBOOTIMAGE) ########################################################################### # Common recipes for all stages diff --git a/src/soc/nvidia/tegra124/Makefile.inc b/src/soc/nvidia/tegra124/Makefile.inc index a63eb35..b1f5998 100644 --- a/src/soc/nvidia/tegra124/Makefile.inc +++ b/src/soc/nvidia/tegra124/Makefile.inc @@ -1,5 +1,3 @@ -CBOOTIMAGE = cbootimage - bootblock-y += bootblock.c bootblock-y += bootblock_asm.S bootblock-y += cbfs.c @@ -40,13 +38,13 @@ CPPFLAGS_common += -Isrc/soc/nvidia/tegra124/include/ $(objcbfs)/bootblock.raw.elf: $(objcbfs)/bootblock.elf cp $< $@ -$(obj)/generated/bct.bin: $(obj)/generated/bct.cfg +$(obj)/generated/bct.bin: $(obj)/generated/bct.cfg $(CBOOTIMAGE) @printf " CBOOTIMAGE $(subst $(obj)/,,$(@))\n" $(CBOOTIMAGE) -gbct --soc tegra124 $< $@ BCT_BIN = $(obj)/generated/bct.bin BCT_WRAPPER = $(obj)/generated/bct.wrapper -$(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw.bin $(BCT_BIN) +$(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw.bin $(BCT_BIN) $(CBOOTIMAGE) echo "Version = 1;" > $(BCT_WRAPPER) echo "Redundancy = 1;" >> $(BCT_WRAPPER) echo "Bctfile = $(BCT_BIN);" >> $(BCT_WRAPPER)

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Patch set updated for coreboot: f26a56b nyan: Add a stub mainboard.
by Isaac Christensen 09 Sep '14

09 Sep '14

Isaac Christensen (isaac.christensen(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6669 -gerrit commit f26a56b0dbf4ed9ce40322a8489046e3da8ad99b Author: Gabe Black <gabeblack(a)google.com> Date: Thu Sep 26 16:27:55 2013 -0700 nyan: Add a stub mainboard. Old-Change-Id: Icdde4cf5e1abb3ae1ad14279ebc129919ba30074 Signed-off-by: Gabe Black <gabeblack(a)google.com> Reviewed-on: https://chromium-review.googlesource.com/170837 Reviewed-by: Gabe Black <gabeblack(a)chromium.org> Commit-Queue: Gabe Black <gabeblack(a)chromium.org> Tested-by: Gabe Black <gabeblack(a)chromium.org> (cherry picked from commit e9d87534ccacb42d508f1902786470798a2dbaea) nyan: Add a "special-class" for aggregating BCT files into bct.cfg. The config file which cbootimage processes to create a BCT could come from multiple different files, individually selected based on config options, and/or split up into different files for organizational purposes. This change adds a special-class which collects those files and concatenates them all together in a bct.cfg which can be processed more easily by other parts of the build. While the BCT files themselves are potentially very board specific, for instance ones that hold memory timing information, this bit of code which collects them is not. It has to be in each board file instead of alongside the CPU, however, to ensure that the special class is set up before another Makefile tries to use it. If we end up with lots of Tegra based boards which duplicate this code over and over, we might want to revisit how this works. Old-Change-Id: I58e1373434f89e69298990ea4643a19d8afdc309 Signed-off-by: Gabe Black <gabeblack(a)google.com> Reviewed-on: https://chromium-review.googlesource.com/170922 Reviewed-by: Gabe Black <gabeblack(a)chromium.org> Commit-Queue: Gabe Black <gabeblack(a)chromium.org> Tested-by: Gabe Black <gabeblack(a)chromium.org> (cherry picked from commit 3ae44178b7084037a75e16ce161b1432abf4246a) nyan: Add bct files for nyan. There's a config option which selects between the emmc and spi config files depending on what the firmware is intended to boot from. These are copied from the files installed by the tegra-bct-nyan ebuild, except that the spi config file has been modified so that there's only one copy of the BCT and so that it only has one configuration. This is to save space in the final image. Old-Change-Id: Ibf1b895bb3ed060d394fc6ffcec67b6972bb21e3 Signed-off-by: Gabe Black <gabeblack(a)google.com> Reviewed-on: https://chromium-review.googlesource.com/170923 Reviewed-by: Gabe Black <gabeblack(a)chromium.org> Commit-Queue: Gabe Black <gabeblack(a)chromium.org> Tested-by: Gabe Black <gabeblack(a)chromium.org> (cherry picked from commit 6bbcffe04e8ae73c86bc05c577a67f909857e1c0) Squashed three commits required to get nyan building since some patches were out of order. Added a select to the nyan mainboard Kconfig to have a rom size of 1024K to match the saved config on the chromium side. Change-Id: I346dbb02d216adfea9707e40adf0a4d1e0fabf36 Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com> --- src/mainboard/google/Kconfig | 3 + src/mainboard/google/nyan/Kconfig | 57 +++++ src/mainboard/google/nyan/Makefile.inc | 32 +++ src/mainboard/google/nyan/bct/Makefile.inc | 23 ++ src/mainboard/google/nyan/bct/emmc.cfg | 13 ++ src/mainboard/google/nyan/bct/odmdata.cfg | 1 + src/mainboard/google/nyan/bct/sdram.cfg | 346 +++++++++++++++++++++++++++++ src/mainboard/google/nyan/bct/spi.cfg | 16 ++ src/mainboard/google/nyan/devicetree.cb | 22 ++ src/mainboard/google/nyan/mainboard.c | 36 +++ src/mainboard/google/nyan/romstage.c | 30 +++ 11 files changed, 579 insertions(+) diff --git a/src/mainboard/google/Kconfig b/src/mainboard/google/Kconfig index d38f080..538f0d8 100644 --- a/src/mainboard/google/Kconfig +++ b/src/mainboard/google/Kconfig @@ -29,6 +29,8 @@ config BOARD_GOOGLE_FALCO bool "Falco" config BOARD_GOOGLE_LINK bool "Link" +config BOARD_GOOGLE_NYAN + bool "Nyan" config BOARD_GOOGLE_PANTHER bool "Panther" config BOARD_GOOGLE_PARROT @@ -54,6 +56,7 @@ source "src/mainboard/google/bolt/Kconfig" source "src/mainboard/google/butterfly/Kconfig" source "src/mainboard/google/falco/Kconfig" source "src/mainboard/google/link/Kconfig" +source "src/mainboard/google/nyan/Kconfig" source "src/mainboard/google/panther/Kconfig" source "src/mainboard/google/parrot/Kconfig" source "src/mainboard/google/peppy/Kconfig" diff --git a/src/mainboard/google/nyan/Kconfig b/src/mainboard/google/nyan/Kconfig new file mode 100644 index 0000000..5ac58d3 --- /dev/null +++ b/src/mainboard/google/nyan/Kconfig @@ -0,0 +1,57 @@ +## +## This file is part of the coreboot project. +## +## Copyright 2013 Google Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +if BOARD_GOOGLE_NYAN + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select SOC_NVIDIA_TEGRA124 + select BOARD_ROMSIZE_KB_1024 + +config MAINBOARD_DIR + string + default google/nyan + +config MAINBOARD_PART_NUMBER + string + default "Nyan" + +config DRAM_SIZE_MB + int + default 2048 + +choice + prompt "BCT boot media" + default BCT_CFG_SPI + help + Which boot media to configure the BCT for. + +config BCT_CFG_SPI + bool "SPI" + help + Configure the BCT for booting from SPI. + +config BCT_CFG_EMMC + bool "eMMC" + help + Configure the BCT for booting from eMMC. + +endchoice + +endif # BOARD_GOOGLE_NYAN diff --git a/src/mainboard/google/nyan/Makefile.inc b/src/mainboard/google/nyan/Makefile.inc new file mode 100644 index 0000000..3cf7dd2 --- /dev/null +++ b/src/mainboard/google/nyan/Makefile.inc @@ -0,0 +1,32 @@ +## +## This file is part of the coreboot project. +## +## Copyright 2013 Google Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +# Add a handler for BCT config files +$(call add-special-class,bct-cfg) +bct-cfg-handler= $(eval $(obj)/generated/bct.cfg: $(1)$(2)) + +$(obj)/generated/bct.cfg: + @printf " CAT $(subst $(obj)/,,$(@))\n" + cat $^ > $@ + +subdirs-y += bct + +romstage-y += romstage.c + +ramstage-y += mainboard.c diff --git a/src/mainboard/google/nyan/bct/Makefile.inc b/src/mainboard/google/nyan/bct/Makefile.inc new file mode 100644 index 0000000..2442c53 --- /dev/null +++ b/src/mainboard/google/nyan/bct/Makefile.inc @@ -0,0 +1,23 @@ +## +## This file is part of the coreboot project. +## +## Copyright 2013 Google Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +bct-cfg-$(CONFIG_BCT_CFG_EMMC) += emmc.cfg +bct-cfg-$(CONFIG_BCT_CFG_SPI) += spi.cfg +bct-cfg-y += odmdata.cfg +bct-cfg-y += sdram.cfg diff --git a/src/mainboard/google/nyan/bct/emmc.cfg b/src/mainboard/google/nyan/bct/emmc.cfg new file mode 100644 index 0000000..be8f79f --- /dev/null +++ b/src/mainboard/google/nyan/bct/emmc.cfg @@ -0,0 +1,13 @@ +# Copyright (c) 2013 The Chromium OS Authors. All rights reserved. +# Distributed under the terms of the GNU General Public License v2 + +Version = 0x00350001; +BlockSize = 0x00004000; +PageSize = 0x00000200; +PartitionSize = 0x01000000; + +DevType[0] = NvBootDevType_Sdmmc; +DeviceParam[0].SdmmcParams.ClockDivider = 0x00000009; +DeviceParam[0].SdmmcParams.DataWidth = NvBootSdmmcDataWidth_8Bit; +DeviceParam[0].SdmmcParams.MaxPowerClassSupported = 0x00000000; +DeviceParam[0].SdmmcParams.MultiPageSupport = 0x00000000; diff --git a/src/mainboard/google/nyan/bct/odmdata.cfg b/src/mainboard/google/nyan/bct/odmdata.cfg new file mode 100644 index 0000000..d0ab2bf --- /dev/null +++ b/src/mainboard/google/nyan/bct/odmdata.cfg @@ -0,0 +1 @@ +OdmData = 0x80080000; diff --git a/src/mainboard/google/nyan/bct/sdram.cfg b/src/mainboard/google/nyan/bct/sdram.cfg new file mode 100644 index 0000000..fa3271a --- /dev/null +++ b/src/mainboard/google/nyan/bct/sdram.cfg @@ -0,0 +1,346 @@ +# CFG Version 11 +# Do not edit. Generated by gen_sdram_cfg V5.0.1. Command: +# gen_sdram_cfg -i ddr3_256Mx16x4_H5TC4G63AFR_RDA.par 1.082 -dram_board_cfg 10 -fly_by_time_ps 1650 +# -b PM358/PM358_924MHz_emc_reg.txt -o PM358_Hynix_2GB_H5TC4G63AFR_RDA_924Mhz.cfg +# Parameter file: ddr3_256Mx16x4_H5TC4G63AFR_RDA.par, tck = 1.08 ns (924.21 MHz) +# bkv file: PM358/PM358_924MHz_emc_reg.txt +SDRAM[0].MemoryType = NvBootMemoryType_Ddr3; +SDRAM[0].PllMInputDivider = 0x00000001; +SDRAM[0].PllMFeedbackDivider = 0x0000004d; +SDRAM[0].PllMStableTime = 0x0000012c; +SDRAM[0].PllMSetupControl = 0x00000000; +SDRAM[0].PllMSelectDiv2 = 0x00000000; +SDRAM[0].PllMPDLshiftPh45 = 0x00000001; +SDRAM[0].PllMPDLshiftPh90 = 0x00000001; +SDRAM[0].PllMPDLshiftPh135 = 0x00000001; +SDRAM[0].PllMKCP = 0x00000000; +SDRAM[0].PllMKVCO = 0x00000000; +SDRAM[0].EmcBctSpare0 = 0x00000000; +SDRAM[0].EmcBctSpare1 = 0x00000000; +SDRAM[0].EmcBctSpare2 = 0x00000000; +SDRAM[0].EmcBctSpare3 = 0x00000000; +SDRAM[0].EmcBctSpare4 = 0x00000000; +SDRAM[0].EmcBctSpare5 = 0x00000000; +SDRAM[0].EmcBctSpare6 = 0x00000000; +SDRAM[0].EmcBctSpare7 = 0x00000000; +SDRAM[0].EmcBctSpare8 = 0x00000000; +SDRAM[0].EmcBctSpare9 = 0x00000000; +SDRAM[0].EmcBctSpare10 = 0x00000000; +SDRAM[0].EmcBctSpare11 = 0x00000000; +SDRAM[0].EmcClockSource = 0x80000000; +SDRAM[0].EmcAutoCalInterval = 0x001fffff; +SDRAM[0].EmcAutoCalConfig = 0xa1430404; +SDRAM[0].EmcAutoCalConfig2 = 0x00000000; +SDRAM[0].EmcAutoCalConfig3 = 0x00000000; +SDRAM[0].EmcAutoCalWait = 0x00000190; +SDRAM[0].EmcAdrCfg = 0x00000000; +SDRAM[0].EmcPinProgramWait = 0x00000001; +SDRAM[0].EmcPinExtraWait = 0x00000000; +SDRAM[0].EmcTimingControlWait = 0x00000000; +SDRAM[0].EmcRc = 0x0000002b; +SDRAM[0].EmcRfc = 0x000000ef; +SDRAM[0].EmcRfcSlr = 0x00000000; +SDRAM[0].EmcRas = 0x0000001e; +SDRAM[0].EmcRp = 0x0000000b; +SDRAM[0].EmcR2r = 0x00000000; +SDRAM[0].EmcW2w = 0x00000000; +SDRAM[0].EmcR2w = 0x00000008; +SDRAM[0].EmcW2r = 0x0000000f; +SDRAM[0].EmcR2p = 0x00000005; +SDRAM[0].EmcW2p = 0x00000016; +SDRAM[0].EmcRdRcd = 0x0000000b; +SDRAM[0].EmcWrRcd = 0x0000000b; +SDRAM[0].EmcRrd = 0x00000004; +SDRAM[0].EmcRext = 0x00000002; +SDRAM[0].EmcWext = 0x00000000; +SDRAM[0].EmcWdv = 0x00000006; +SDRAM[0].EmcWdvMask = 0x00000006; +SDRAM[0].EmcQUse = 0x0000000c; +SDRAM[0].EmcQuseWidth = 0x00000002; +SDRAM[0].EmcIbdly = 0x00000000; +SDRAM[0].EmcEInput = 0x00000002; +SDRAM[0].EmcEInputDuration = 0x0000000e; +SDRAM[0].EmcPutermExtra = 0x000a0000; +SDRAM[0].EmcPutermWidth = 0x00000004; +SDRAM[0].EmcPutermAdj = 0x00000000; +SDRAM[0].EmcCdbCntl1 = 0x00000000; +SDRAM[0].EmcCdbCntl2 = 0x00000000; +SDRAM[0].EmcCdbCntl3 = 0x00000000; +SDRAM[0].EmcQRst = 0x00000001; +SDRAM[0].EmcQSafe = 0x00000015; +SDRAM[0].EmcRdv = 0x0000001b; +SDRAM[0].EmcRdvMask = 0x0000001d; +SDRAM[0].EmcQpop = 0x00000010; +SDRAM[0].EmcCtt = 0x00000000; +SDRAM[0].EmcCttDuration = 0x00000004; +SDRAM[0].EmcRefresh = 0x00001be9; +SDRAM[0].EmcBurstRefreshNum = 0x00000000; +SDRAM[0].EmcPreRefreshReqCnt = 0x000006fa; +SDRAM[0].EmcPdEx2Wr = 0x00000004; +SDRAM[0].EmcPdEx2Rd = 0x00000015; +SDRAM[0].EmcPChg2Pden = 0x00000001; +SDRAM[0].EmcAct2Pden = 0x00000000; +SDRAM[0].EmcAr2Pden = 0x000000e6; +SDRAM[0].EmcRw2Pden = 0x0000001b; +SDRAM[0].EmcTxsr = 0x000000fa; +SDRAM[0].EmcTxsrDll = 0x00000200; +SDRAM[0].EmcTcke = 0x00000006; +SDRAM[0].EmcTckesr = 0x00000007; +SDRAM[0].EmcTpd = 0x00000006; +SDRAM[0].EmcTfaw = 0x00000022; +SDRAM[0].EmcTrpab = 0x00000000; +SDRAM[0].EmcTClkStable = 0x0000000a; +SDRAM[0].EmcTClkStop = 0x0000000a; +SDRAM[0].EmcTRefBw = 0x00001c29; +SDRAM[0].EmcFbioCfg5 = 0x104ab898; +SDRAM[0].EmcFbioCfg6 = 0x00000002; +SDRAM[0].EmcFbioSpare = 0x00000000; +SDRAM[0].EmcCfgRsv = 0xff00ff00; +SDRAM[0].EmcMrs = 0x80000f15; +SDRAM[0].EmcEmrs = 0x80100002; +SDRAM[0].EmcEmrs2 = 0x80200020; +SDRAM[0].EmcEmrs3 = 0x80300000; +SDRAM[0].EmcMrw1 = 0x00000000; +SDRAM[0].EmcMrw2 = 0x00000000; +SDRAM[0].EmcMrw3 = 0x00000000; +SDRAM[0].EmcMrw4 = 0x00000000; +SDRAM[0].EmcMrwExtra = 0x00000000; +SDRAM[0].EmcWarmBootMrwExtra = 0x00000000; +SDRAM[0].EmcWarmBootExtraModeRegWriteEnable = 0x00000000; +SDRAM[0].EmcExtraModeRegWriteEnable = 0x00000000; +SDRAM[0].EmcMrwResetCommand = 0x00000000; +SDRAM[0].EmcMrwResetNInitWait = 0x00000000; +SDRAM[0].EmcMrsWaitCnt = 0x00ce000e; +SDRAM[0].EmcMrsWaitCnt2 = 0x00ce000e; +SDRAM[0].EmcCfg = 0x73300000; +SDRAM[0].EmcCfg2 = 0x000008a5; +SDRAM[0].EmcCfgPipe = 0x00000000; +SDRAM[0].EmcDbg = 0x01000c00; +SDRAM[0].EmcCmdQ = 0x10004408; +SDRAM[0].EmcMc2EmcQ = 0x06000404; +SDRAM[0].EmcDynSelfRefControl = 0x800037ed; +SDRAM[0].AhbArbitrationXbarCtrlMemInitDone = 0x00000001; +SDRAM[0].EmcCfgDigDll = 0xe00401b1; +SDRAM[0].EmcCfgDigDllPeriod = 0x00008000; +SDRAM[0].EmcDevSelect = 0x00000002; +SDRAM[0].EmcSelDpdCtrl = 0x00040000; +SDRAM[0].EmcDllXformDqs0 = 0x00000005; +SDRAM[0].EmcDllXformDqs1 = 0x00000005; +SDRAM[0].EmcDllXformDqs2 = 0x00000005; +SDRAM[0].EmcDllXformDqs3 = 0x00000005; +SDRAM[0].EmcDllXformDqs4 = 0x00000005; +SDRAM[0].EmcDllXformDqs5 = 0x00000005; +SDRAM[0].EmcDllXformDqs6 = 0x00000005; +SDRAM[0].EmcDllXformDqs7 = 0x00000005; +SDRAM[0].EmcDllXformDqs8 = 0x00000005; +SDRAM[0].EmcDllXformDqs9 = 0x00000005; +SDRAM[0].EmcDllXformDqs10 = 0x00000005; +SDRAM[0].EmcDllXformDqs11 = 0x00000005; +SDRAM[0].EmcDllXformDqs12 = 0x00000005; +SDRAM[0].EmcDllXformDqs13 = 0x00000005; +SDRAM[0].EmcDllXformDqs14 = 0x00000005; +SDRAM[0].EmcDllXformDqs15 = 0x00000005; +SDRAM[0].EmcDllXformQUse0 = 0x00000000; +SDRAM[0].EmcDllXformQUse1 = 0x00000000; +SDRAM[0].EmcDllXformQUse2 = 0x00000000; +SDRAM[0].EmcDllXformQUse3 = 0x00000000; +SDRAM[0].EmcDllXformQUse4 = 0x00000000; +SDRAM[0].EmcDllXformQUse5 = 0x00000000; +SDRAM[0].EmcDllXformQUse6 = 0x00000000; +SDRAM[0].EmcDllXformQUse7 = 0x00000000; +SDRAM[0].EmcDllXformAddr0 = 0x0000400e; +SDRAM[0].EmcDllXformAddr1 = 0x0000400e; +SDRAM[0].EmcDllXformAddr2 = 0x00000000; +SDRAM[0].EmcDllXformAddr3 = 0x0000400e; +SDRAM[0].EmcDllXformAddr4 = 0x0000400e; +SDRAM[0].EmcDllXformAddr5 = 0x00000000; +SDRAM[0].EmcDllXformQUse8 = 0x00000000; +SDRAM[0].EmcDllXformQUse9 = 0x00000000; +SDRAM[0].EmcDllXformQUse10 = 0x00000000; +SDRAM[0].EmcDllXformQUse11 = 0x00000000; +SDRAM[0].EmcDllXformQUse12 = 0x00000000; +SDRAM[0].EmcDllXformQUse13 = 0x00000000; +SDRAM[0].EmcDllXformQUse14 = 0x00000000; +SDRAM[0].EmcDllXformQUse15 = 0x00000000; +SDRAM[0].EmcDliTrimTxDqs0 = 0x00000000; +SDRAM[0].EmcDliTrimTxDqs1 = 0x00000000; +SDRAM[0].EmcDliTrimTxDqs2 = 0x00000000; +SDRAM[0].EmcDliTrimTxDqs3 = 0x00000000; +SDRAM[0].EmcDliTrimTxDqs4 = 0x00000000; +SDRAM[0].EmcDliTrimTxDqs5 = 0x00000000; +SDRAM[0].EmcDliTrimTxDqs6 = 0x00000000; +SDRAM[0].EmcDliTrimTxDqs7 = 0x00000000; +SDRAM[0].EmcDliTrimTxDqs8 = 0x00000000; +SDRAM[0].EmcDliTrimTxDqs9 = 0x00000000; +SDRAM[0].EmcDliTrimTxDqs10 = 0x00000000; +SDRAM[0].EmcDliTrimTxDqs11 = 0x00000000; +SDRAM[0].EmcDliTrimTxDqs12 = 0x00000000; +SDRAM[0].EmcDliTrimTxDqs13 = 0x00000000; +SDRAM[0].EmcDliTrimTxDqs14 = 0x00000000; +SDRAM[0].EmcDliTrimTxDqs15 = 0x00000000; +SDRAM[0].EmcDllXformDq0 = 0x00000006; +SDRAM[0].EmcDllXformDq1 = 0x00000006; +SDRAM[0].EmcDllXformDq2 = 0x00000006; +SDRAM[0].EmcDllXformDq3 = 0x00000006; +SDRAM[0].EmcDllXformDq4 = 0x00000006; +SDRAM[0].EmcDllXformDq5 = 0x00000006; +SDRAM[0].EmcDllXformDq6 = 0x00000006; +SDRAM[0].EmcDllXformDq7 = 0x00000006; +SDRAM[0].WarmBootWait = 0x00000002; +SDRAM[0].EmcCttTermCtrl = 0x00000802; +SDRAM[0].EmcOdtWrite = 0x00000000; +SDRAM[0].EmcOdtRead = 0x00000000; +SDRAM[0].EmcZcalInterval = 0x00020000; +SDRAM[0].EmcZcalWaitCnt = 0x0000004c; +SDRAM[0].EmcZcalMrwCmd = 0x80000000; +SDRAM[0].EmcMrsResetDll = 0x00000000; +SDRAM[0].EmcZcalInitDev0 = 0x80000011; +SDRAM[0].EmcZcalInitDev1 = 0x00000000; +SDRAM[0].EmcZcalInitWait = 0x00000001; +SDRAM[0].EmcZcalWarmColdBootEnables = 0x00000003; +SDRAM[0].EmcMrwLpddr2ZcalWarmBoot = 0x040a00ab; +SDRAM[0].EmcZqCalDdr3WarmBoot = 0x00000000; +SDRAM[0].EmcZcalWarmBootWait = 0x00000001; +SDRAM[0].EmcMrsWarmBootEnable = 0x00000001; +SDRAM[0].EmcMrsResetDllWait = 0x00000000; +SDRAM[0].EmcMrsExtra = 0x80000f15; +SDRAM[0].EmcWarmBootMrsExtra = 0x80100002; +SDRAM[0].EmcEmrsDdr2DllEnable = 0x00000000; +SDRAM[0].EmcMrsDdr2DllReset = 0x00000000; +SDRAM[0].EmcEmrsDdr2OcdCalib = 0x00000000; +SDRAM[0].EmcDdr2Wait = 0x00000000; +SDRAM[0].EmcClkenOverride = 0x00000000; +SDRAM[0].McDisExtraSnapLevels = 0x00000000; +SDRAM[0].EmcExtraRefreshNum = 0x00000002; +SDRAM[0].EmcClkenOverrideAllWarmBoot = 0x00000000; +SDRAM[0].McClkenOverrideAllWarmBoot = 0x00000000; +SDRAM[0].EmcCfgDigDllPeriodWarmBoot = 0x00000003; +SDRAM[0].PmcVddpSel = 0x00000002; +SDRAM[0].PmcVddpSelWait = 0x00000002; +SDRAM[0].PmcDdrPwr = 0x00000003; +SDRAM[0].PmcDdrCfg = 0x00002002; +SDRAM[0].PmcIoDpd3Req = 0x4fff2f97; +SDRAM[0].PmcIoDpd3ReqWait = 0x00000000; +SDRAM[0].PmcRegShort = 0x00000000; +SDRAM[0].PmcNoIoPower = 0x00000000; +SDRAM[0].PmcPorDpdCtrlWait = 0x00000000; +SDRAM[0].EmcXm2CmdPadCtrl = 0x100002a0; +SDRAM[0].EmcXm2CmdPadCtrl2 = 0x770c0000; +SDRAM[0].EmcXm2CmdPadCtrl3 = 0x050c0000; +SDRAM[0].EmcXm2CmdPadCtrl4 = 0x00000000; +SDRAM[0].EmcXm2CmdPadCtrl5 = 0x00111111; +SDRAM[0].EmcXm2DqsPadCtrl = 0x770c1414; +SDRAM[0].EmcXm2DqsPadCtrl2 = 0x0020013d; +SDRAM[0].EmcXm2DqsPadCtrl3 = 0x55555520; +SDRAM[0].EmcXm2DqsPadCtrl4 = 0x003cf3cf; +SDRAM[0].EmcXm2DqsPadCtrl5 = 0x003cf3cf; +SDRAM[0].EmcXm2DqsPadCtrl6 = 0x55555500; +SDRAM[0].EmcXm2DqPadCtrl = 0x770c2990; +SDRAM[0].EmcXm2DqPadCtrl2 = 0x00000000; +SDRAM[0].EmcXm2DqPadCtrl3 = 0x00000000; +SDRAM[0].EmcXm2ClkPadCtrl = 0x77ffc085; +SDRAM[0].EmcXm2ClkPadCtrl2 = 0x00000303; +SDRAM[0].EmcXm2CompPadCtrl = 0x81f1f108; +SDRAM[0].EmcXm2VttGenPadCtrl = 0x07070004; +SDRAM[0].EmcXm2VttGenPadCtrl2 = 0x00000000; +SDRAM[0].EmcXm2VttGenPadCtrl3 = 0x016eeeee; +SDRAM[0].EmcAcpdControl = 0x00000000; +SDRAM[0].EmcSwizzleRank0ByteCfg = 0x00003120; +SDRAM[0].EmcSwizzleRank0Byte0 = 0x25143067; +SDRAM[0].EmcSwizzleRank0Byte1 = 0x45367102; +SDRAM[0].EmcSwizzleRank0Byte2 = 0x47106253; +SDRAM[0].EmcSwizzleRank0Byte3 = 0x04362175; +SDRAM[0].EmcSwizzleRank1ByteCfg = 0x00003120; +SDRAM[0].EmcSwizzleRank1Byte0 = 0x71546032; +SDRAM[0].EmcSwizzleRank1Byte1 = 0x35104276; +SDRAM[0].EmcSwizzleRank1Byte2 = 0x27043615; +SDRAM[0].EmcSwizzleRank1Byte3 = 0x72306145; +SDRAM[0].EmcDsrVttgenDrv = 0x0606003f; +SDRAM[0].EmcTxdsrvttgen = 0x00000000; +SDRAM[0].EmcBgbiasCtl0 = 0x00000000; +SDRAM[0].McEmemAdrCfg = 0x00000000; +SDRAM[0].McEmemAdrCfgDev0 = 0x00080303; +SDRAM[0].McEmemAdrCfgDev1 = 0x00080303; +SDRAM[0].McEmemAdrCfgBankMask0 = 0x00001248; +SDRAM[0].McEmemAdrCfgBankMask1 = 0x00002490; +SDRAM[0].McEmemAdrCfgBankMask2 = 0x00000920; +SDRAM[0].McEmemAdrCfgBankSwizzle3 = 0x00000001; +SDRAM[0].McEmemCfg = 0x00000800; +SDRAM[0].McEmemArbCfg = 0x0e00000d; +SDRAM[0].McEmemArbOutstandingReq = 0x80000040; +SDRAM[0].McEmemArbTimingRcd = 0x00000005; +SDRAM[0].McEmemArbTimingRp = 0x00000006; +SDRAM[0].McEmemArbTimingRc = 0x00000016; +SDRAM[0].McEmemArbTimingRas = 0x0000000e; +SDRAM[0].McEmemArbTimingFaw = 0x00000011; +SDRAM[0].McEmemArbTimingRrd = 0x00000002; +SDRAM[0].McEmemArbTimingRap2Pre = 0x00000004; +SDRAM[0].McEmemArbTimingWap2Pre = 0x0000000e; +SDRAM[0].McEmemArbTimingR2R = 0x00000002; +SDRAM[0].McEmemArbTimingW2W = 0x00000002; +SDRAM[0].McEmemArbTimingR2W = 0x00000006; +SDRAM[0].McEmemArbTimingW2R = 0x00000009; +SDRAM[0].McEmemArbDaTurns = 0x09060202; +SDRAM[0].McEmemArbDaCovers = 0x001a1016; +SDRAM[0].McEmemArbMisc0 = 0x734e2a17; +SDRAM[0].McEmemArbMisc1 = 0x70000f02; +SDRAM[0].McEmemArbRing1Throttle = 0x001f0000; +SDRAM[0].McEmemArbOverride = 0x10000000; +SDRAM[0].McEmemArbOverride1 = 0x00000000; +SDRAM[0].McEmemArbRsv = 0xff00ff00; +SDRAM[0].McClkenOverride = 0x00000000; +SDRAM[0].McStatControl = 0x00000000; +SDRAM[0].McDisplaySnapRing = 0x00000003; +SDRAM[0].McVideoProtectBom = 0xfff00000; +SDRAM[0].McVideoProtectBomAdrHi = 0x00000000; +SDRAM[0].McVideoProtectSizeMb = 0x00000000; +SDRAM[0].McVideoProtectVprOverride = 0xe4bac743; +SDRAM[0].McVideoProtectVprOverride1 = 0x00000013; +SDRAM[0].McVideoProtectGpuOverride0 = 0x00000000; +SDRAM[0].McVideoProtectGpuOverride1 = 0x00000000; +SDRAM[0].McSecCarveoutBom = 0xfff00000; +SDRAM[0].McSecCarveoutAdrHi = 0x00000000; +SDRAM[0].McSecCarveoutSizeMb = 0x00000000; +SDRAM[0].McVideoProtectWriteAccess = 0x00000000; +SDRAM[0].McSecCarveoutProtectWriteAccess = 0x00000000; +SDRAM[0].EmcCaTrainingEnable = 0x00000000; +SDRAM[0].EmcCaTrainingTimingCntl1 = 0x1f7df7df; +SDRAM[0].EmcCaTrainingTimingCntl2 = 0x0000001f; +SDRAM[0].SwizzleRankByteEncode = 0x0000006f; +SDRAM[0].BootRomPatchControl = 0x00000000; +SDRAM[0].BootRomPatchData = 0x00000000; +SDRAM[0].McMtsCarveoutBom = 0xfff00000; +SDRAM[0].McMtsCarveoutAdrHi = 0x00000000; +SDRAM[0].McMtsCarveoutSizeMb = 0x00000000; +SDRAM[0].McMtsCarveoutRegCtrl = 0x00000000; +#@ MC_MLL_MPCORER_PTSA_RATE {0x7001944c} = 0x00000017; +#@ MC_PTSA_GRANT_DECREMENT {0x70019960} = 0x000001bb; +#@ MC_LATENCY_ALLOWANCE_XUSB_0 {0x7001937c} = 0x006e0038; +#@ MC_LATENCY_ALLOWANCE_XUSB_1 {0x70019380} = 0x006e0038; +#@ MC_LATENCY_ALLOWANCE_TSEC_0 {0x70019390} = 0x006e003c; +#@ MC_LATENCY_ALLOWANCE_SDMMCA_0 {0x700193b8} = 0x006e0090; +#@ MC_LATENCY_ALLOWANCE_SDMMCAA_0 {0x700193bc} = 0x006e0041; +#@ MC_LATENCY_ALLOWANCE_SDMMC_0 {0x700193c0} = 0x006e0090; +#@ MC_LATENCY_ALLOWANCE_SDMMCAB_0 {0x700193c4} = 0x006e0041; +#@ MC_LATENCY_ALLOWANCE_PPCS_0 {0x70019344} = 0x00270049; +#@ MC_LATENCY_ALLOWANCE_PPCS_1 {0x70019348} = 0x006e0080; +#@ MC_LATENCY_ALLOWANCE_MPCORE_0 {0x70019320} = 0x006e0004; +#@ MC_LATENCY_ALLOWANCE_MPCORELP_0 {0x70019324} = 0x006e0004; +#@ MC_LATENCY_ALLOWANCE_HC_0 {0x70019310} = 0x00080016; +#@ MC_LATENCY_ALLOWANCE_HC_1 {0x70019314} = 0x0000006e; +#@ MC_LATENCY_ALLOWANCE_AVPC_0 {0x700192e4} = 0x006e0004; +#@ MC_LATENCY_ALLOWANCE_GPU_0 {0x700193ac} = 0x006e0019; +#@ MC_LATENCY_ALLOWANCE_MSENC_0 {0x70019328} = 0x006e0018; +#@ MC_LATENCY_ALLOWANCE_HDA_0 {0x70019318} = 0x006e0024; +#@ MC_LATENCY_ALLOWANCE_VIC_0 {0x70019394} = 0x006e001b; +#@ MC_LATENCY_ALLOWANCE_VI2_0 {0x70019398} = 0x0000006e; +#@ MC_LATENCY_ALLOWANCE_ISP2_0 {0x70019370} = 0x00000036; +#@ MC_LATENCY_ALLOWANCE_ISP2_1 {0x70019374} = 0x006e006e; +#@ MC_LATENCY_ALLOWANCE_ISP2B_0 {0x70019384} = 0x00000036; +#@ MC_LATENCY_ALLOWANCE_ISP2B_1 {0x70019388} = 0x006e006e; +#@ MC_LATENCY_ALLOWANCE_VDE_0 {0x70019354} = 0x00d400ff; +#@ MC_LATENCY_ALLOWANCE_VDE_1 {0x70019358} = 0x00510029; +#@ MC_LATENCY_ALLOWANCE_VDE_2 {0x7001935c} = 0x006e006e; +#@ MC_LATENCY_ALLOWANCE_VDE_3 {0x70019360} = 0x006e006e; +#@ MC_LATENCY_ALLOWANCE_SATA_0 {0x70019350} = 0x006e0065; +#@ MC_LATENCY_ALLOWANCE_AFI_0 {0x700192e0} = 0x006e001c; diff --git a/src/mainboard/google/nyan/bct/spi.cfg b/src/mainboard/google/nyan/bct/spi.cfg new file mode 100644 index 0000000..b348ed8 --- /dev/null +++ b/src/mainboard/google/nyan/bct/spi.cfg @@ -0,0 +1,16 @@ +# Copyright (c) 2013 The Chromium OS Authors. All rights reserved. +# Distributed under the terms of the GNU General Public License v2 + +Version = 0x00350001; +BlockSize = 32768; +PageSize = 2048; +PartitionSize = 4194304; + +Bctcopy = 1; + +DevType[0] = NvBootDevType_Spi; +DeviceParam[0].SpiFlashParams.ReadCommandTypeFast = NV_FALSE; +DeviceParam[0].SpiFlashParams.ClockDivider = 0x16; +DeviceParam[0].SpiFlashParams.ClockSource = NvBootSpiClockSource_PllPOut0; +DeviceParam[0].SpiFlashParams.PageSize2kor16k = 0; + diff --git a/src/mainboard/google/nyan/devicetree.cb b/src/mainboard/google/nyan/devicetree.cb new file mode 100644 index 0000000..392a5ae --- /dev/null +++ b/src/mainboard/google/nyan/devicetree.cb @@ -0,0 +1,22 @@ +## +## This file is part of the coreboot project. +## +## Copyright 2013 Google Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +chip soc/nvidia/tegra124 + device cpu_cluster 0 on end +end diff --git a/src/mainboard/google/nyan/mainboard.c b/src/mainboard/google/nyan/mainboard.c new file mode 100644 index 0000000..9e08021 --- /dev/null +++ b/src/mainboard/google/nyan/mainboard.c @@ -0,0 +1,36 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <device/device.h> +#include <boot/coreboot_tables.h> + +/* this happens after cpu_init where exynos resources are set */ +static void mainboard_init(device_t dev) +{ +} + +static void mainboard_enable(device_t dev) +{ + dev->ops->init = &mainboard_init; +} + +struct chip_operations mainboard_ops = { + .name = "nyan", + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/google/nyan/romstage.c b/src/mainboard/google/nyan/romstage.c new file mode 100644 index 0000000..c52fbd2 --- /dev/null +++ b/src/mainboard/google/nyan/romstage.c @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/stages.h> +#include <cbfs.h> +#include <console/console.h> + +void main(void) +{ + void *entry; + + entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, "fallback/coreboot_ram"); + stage_exit(entry); +}

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coreboot-gerrit September 2014