New patch to review for coreboot: 6238321 libpayload: usb: Remove generic roothub reset port function
by Isaac Christensen 30 Sep '14
by Isaac Christensen 30 Sep '14
30 Sep '14
Isaac Christensen (isaac.christensen(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7001
-gerrit
commit 62383213530806a20d4250a80e810dfba8b40e56
Author: Shawn Nematbakhsh <shawnn(a)chromium.org>
Date: Mon Mar 10 14:12:29 2014 -0700
libpayload: usb: Remove generic roothub reset port function
The generic roothub reset port function is overly broad and does some
things which may be undesirable, such as issuing multiple resets to a
port if the reset is deemed to have finished too quickly. Remove the
generic function and replace it with a controller-specific function,
currently only implemented for xhci.
Change-Id: Id46f73ea3341d4d01d2b517c6bf687402022d272
Signed-off-by: Shawn Nematbakhsh <shawnn(a)chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/189495
Reviewed-by: Julius Werner <jwerner(a)chromium.org>
(cherry picked from commit 54e1da075b0106b0a1f736641fa52c39401d349d)
Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com>
---
payloads/libpayload/drivers/usb/generic_hub.c | 34 +--------------------------
payloads/libpayload/drivers/usb/generic_hub.h | 5 +++-
payloads/libpayload/drivers/usb/xhci_rh.c | 16 ++++++++++---
3 files changed, 18 insertions(+), 37 deletions(-)
diff --git a/payloads/libpayload/drivers/usb/generic_hub.c b/payloads/libpayload/drivers/usb/generic_hub.c
index fa95969..9f86705 100644
--- a/payloads/libpayload/drivers/usb/generic_hub.c
+++ b/payloads/libpayload/drivers/usb/generic_hub.c
@@ -93,7 +93,7 @@ generic_hub_debounce(usbdev_t *const dev, const int port)
return 0; /* ignore timeouts, try to always go on */
}
-static int
+int
generic_hub_wait_for_port(usbdev_t *const dev, const int port,
const int wait_for,
int (*const port_op)(usbdev_t *, int),
@@ -135,38 +135,6 @@ generic_hub_resetport(usbdev_t *const dev, const int port)
return 0; /* ignore timeouts, try to always go on */
}
-int
-generic_hub_rh_resetport(usbdev_t *const dev, const int port)
-{
- generic_hub_t *const hub = GEN_HUB(dev);
-
- /*
- * Resetting a root hub port should hold 50ms with pulses of at
- * least 10ms and gaps of at most 3ms (usb20 spec 7.1.7.5).
- * After reset, the port will be enabled automatically.
- */
- int total = 500; /* 500 * 100us = 50ms */
- while (total > 0) {
- if (hub->ops->start_port_reset(dev, port) < 0)
- return -1;
-
- /* wait 100ms for the hub to finish the reset pulse */
- const int timeout = generic_hub_wait_for_port(
- /* time out after 1000 * 100us = 100ms */
- dev, port, 0, hub->ops->port_in_reset, 1000, 100);
- const int reset_time = 1000 - timeout;
- if (timeout < 0)
- return -1;
- else if (!timeout)
- usb_debug("generic_hub: Reset timed out at port %d\n",
- port);
- else if (reset_time < 100) /* i.e. < 100 * 100us */
- usb_debug("generic_hub: Port reset too short\n");
- total -= reset_time;
- }
- return 0; /* ignore timeouts, try to always go on */
-}
-
static int
generic_hub_detach_dev(usbdev_t *const dev, const int port)
{
diff --git a/payloads/libpayload/drivers/usb/generic_hub.h b/payloads/libpayload/drivers/usb/generic_hub.h
index cd4ebb6..21536c0 100644
--- a/payloads/libpayload/drivers/usb/generic_hub.h
+++ b/payloads/libpayload/drivers/usb/generic_hub.h
@@ -72,8 +72,11 @@ typedef struct generic_hub {
} generic_hub_t;
void generic_hub_destroy(usbdev_t *);
+int generic_hub_wait_for_port(usbdev_t *const dev, const int port,
+ const int wait_for,
+ int (*const port_op)(usbdev_t *, int),
+ int timeout_steps, const int step_us);
int generic_hub_resetport(usbdev_t *, int port);
-int generic_hub_rh_resetport(usbdev_t *, int port); /* root hubs have different timing requirements */
int generic_hub_scanport(usbdev_t *, int port);
/* the provided generic_hub_ops struct has to be static */
int generic_hub_init(usbdev_t *, int num_ports, const generic_hub_ops_t *);
diff --git a/payloads/libpayload/drivers/usb/xhci_rh.c b/payloads/libpayload/drivers/usb/xhci_rh.c
index c4cbeea..26bb4f9 100644
--- a/payloads/libpayload/drivers/usb/xhci_rh.c
+++ b/payloads/libpayload/drivers/usb/xhci_rh.c
@@ -100,12 +100,22 @@ xhci_rh_port_speed(usbdev_t *const dev, const int port)
}
static int
-xhci_rh_start_port_reset(usbdev_t *const dev, const int port)
+xhci_rh_reset_port(usbdev_t *const dev, const int port)
{
xhci_t *const xhci = XHCI_INST(dev->controller);
volatile u32 *const portsc = &xhci->opreg->prs[port - 1].portsc;
+ /* Trigger port reset. */
*portsc = (*portsc & PORTSC_RW_MASK) | PORTSC_PR;
+
+ /* Wait for port_in_reset == 0, up to 150 * 1000us = 150ms */
+ if (generic_hub_wait_for_port(dev, port, 0, xhci_rh_port_in_reset,
+ 150, 1000) == 0)
+ usb_debug("xhci_rh: Reset timed out at port %d\n", port);
+ else
+ /* Clear reset status bits, since port is out of reset. */
+ *portsc = (*portsc & PORTSC_RW_MASK) | PORTSC_PRC | PORTSC_WRC;
+
return 0;
}
@@ -118,8 +128,8 @@ static const generic_hub_ops_t xhci_rh_ops = {
.port_speed = xhci_rh_port_speed,
.enable_port = NULL,
.disable_port = NULL,
- .start_port_reset = xhci_rh_start_port_reset,
- .reset_port = generic_hub_rh_resetport,
+ .start_port_reset = NULL,
+ .reset_port = xhci_rh_reset_port,
};
void
1
0
New patch to review for coreboot: fc426a8 baytrail: update C0 microcode
by Isaac Christensen 30 Sep '14
by Isaac Christensen 30 Sep '14
30 Sep '14
Isaac Christensen (isaac.christensen(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7000
-gerrit
commit fc426a88b940cbc43abb20c005ef40e99251c566
Author: Shawn Nematbakhsh <shawnn(a)chromium.org>
Date: Wed Mar 26 11:17:58 2014 -0700
baytrail: update C0 microcode
baytrail: Add 811 microcode for C0 parts
Incorporate 811 microcode version for C0 stepping parts.
Signed-off-by: Shawn Nematbakhsh <shawnn(a)chromium.org>
Old-Change-Id: Ic34c233df28fa2c94db3a886faad8239a05f475d
Reviewed-on: https://chromium-review.googlesource.com/191693
Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
(cherry picked from commit 57c9cbdb9e4bb1cf721849ace8958eb6ec032594)
baytrail: Add 813 microcode for C0 parts
Incorporate 813 microcode version for C0 stepping parts.
Old-Change-Id: I513ce5cc1470fa0154bee088547c5cb8a5902fb5
Signed-off-by: Shawn Nematbakhsh <shawnn(a)chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/195200
Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
(cherry picked from commit bf15a48c6bd71c2b0ab91530713afb26e139ad9c)
baytrail: Update microcode to version 816
Version 816 of microcode.
Old-Change-Id: I868702ec94a265013bb5e378a2345ff1cf0dc364
Original-Change-Id: I9a9cacf2d16bdabdb7ec84607bf6c96e4ac3f3c4
Signed-off-by: Shawn Nematbakhsh <shawnn(a)chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/197692
Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
(cherry picked from commit 16512b09e399c05cf42694854277aa7f1753e49e)
Squashed 3 successive updates for baytrail C0 microcode.
Change-Id: I76714ae636b119348e6bb9f8a4639c68be32ba3a
Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com>
---
.../intel/baytrail/microcode/M0C30678_0000080c.h | 12800 ------------------
.../intel/baytrail/microcode/M0C30678_00000816.h | 13056 +++++++++++++++++++
src/soc/intel/baytrail/microcode/microcode_blob.c | 2 +-
3 files changed, 13057 insertions(+), 12801 deletions(-)
diff --git a/src/soc/intel/baytrail/microcode/M0C30678_0000080c.h b/src/soc/intel/baytrail/microcode/M0C30678_0000080c.h
deleted file mode 100644
index 72abd4f..0000000
--- a/src/soc/intel/baytrail/microcode/M0C30678_0000080c.h
+++ /dev/null
@@ -1,12800 +0,0 @@
-0x000000001,
-0x00000080c,
-0x002142014,
-0x000030678,
-0x042164c4b,
-0x000000001,
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-0x000000000,
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-0x000000000,
-0x020140214,
-0x0000031f1,
-0x000000001,
-0x000030678,
-0x000000000,
-0x000000000,
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-0x000000000,
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-0x03cbea3b5,
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diff --git a/src/soc/intel/baytrail/microcode/M0C30678_00000816.h b/src/soc/intel/baytrail/microcode/M0C30678_00000816.h
new file mode 100644
index 0000000..3564279
--- /dev/null
+++ b/src/soc/intel/baytrail/microcode/M0C30678_00000816.h
@@ -0,0 +1,13056 @@
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+0x6ad6d126,
+0x65735f8b,
+0x79e790a4,
+0xe5b2c609,
+0x4c405fc1,
+0xdf71a90f,
+0x538b5aea,
+0xa49302a4,
+0xdda07264,
+0x46377766,
+0x4bc4e6f5,
+0x4b022a67,
+0x5063e761,
+0xdf35f293,
+0xeb2904d8,
+0x7f782621,
+0xdaae5736,
+0xc035f3ad,
+0xe3555473,
+0xaf66bdb5,
+0x51e02d75,
+0x685ecd76,
+0x1bf36d93,
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+0x887d4bd0,
+0xccb80de3,
+0x676e711d,
+0xca8c2c16,
+0xa73c6150,
+0xce8e9c79,
+0x9da98d75,
+0xc9febf0f,
+0x3ef420de,
+0x63a472b1,
+0x71bdd6c9,
+0x00ae571a,
+0x22a9f086,
+0x0431f024,
+0x6d05a611,
+0x3bb9c796,
+0xffe16d33,
+0x07b10f9e,
+0xf64a0249,
+0xcae28b90,
+0xdf37fdc9,
+0xce8d1307,
+0xcf9a52c3,
+0x81899a5c,
+0x21adb15c,
+0xdc00dfbd,
+0x5913596b,
+0x46a9d9c2,
+0x28cf3adb,
+0x30430ef5,
+0x460748c9,
+0x5aa772f3,
+0x9379f127,
+0x11a80f78,
+0xbe17153f,
+0x83fab05d,
+0xcc69cb18,
+0x77e2f97c,
+0x70ee9746,
+0x24a28520,
+0x51be98d2,
+0xc0b7f477,
+0x442f02c5,
+0xb732f939,
+0x7e72608c,
+0xcd38ff1a,
+0xe911a75a,
+0x9c7ce7fd,
+0x4858a071,
+0x56663646,
+0xc5c18a8a,
+0x86d248a8,
+0x69dd000a,
+0x5845728e,
+0x77e68fb8,
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+0x69012919,
+0x9a3b5fce,
+0x6c1d96d5,
+0xd505142c,
+0xf3024bfe,
+0xe542052f,
+0x1d9df782,
+0x98ceb6df,
+0xa1481349,
+0xd5ca5003,
+0x1f0b8cca,
+0x52beb066,
+0x8ccf84a1,
+0x8e5cae85,
+0x569f61af,
+0xe1aa4eaf,
+0x8d96f072,
+0x741588e6,
+0x4d74732f,
+0x50c78e79,
+0x8b7631a2,
+0x09c7ab38,
+0x53b23db7,
+0xb35bd1c3,
+0x78502482,
+0x62dbbd1d,
+0xb8badc7e,
diff --git a/src/soc/intel/baytrail/microcode/microcode_blob.c b/src/soc/intel/baytrail/microcode/microcode_blob.c
index 6ff383e..5875e6e 100644
--- a/src/soc/intel/baytrail/microcode/microcode_blob.c
+++ b/src/soc/intel/baytrail/microcode/microcode_blob.c
@@ -1,4 +1,4 @@
unsigned microcode[] = {
#include "M0C3067_0000031E.h"
-#include "M0C30678_0000080c.h"
+#include "M0C30678_00000816.h"
};
1
0
New patch to review for coreboot: dce6c49 reg_script: Fix bug in IO macros
by Isaac Christensen 29 Sep '14
by Isaac Christensen 29 Sep '14
29 Sep '14
Isaac Christensen (isaac.christensen(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6999
-gerrit
commit dce6c49f24be8a07a7bbf6c1380519ee8fb81cc5
Author: Duncan Laurie <dlaurie(a)chromium.org>
Date: Tue Apr 22 11:14:12 2014 -0700
reg_script: Fix bug in IO macros
These have apparently never been used because they are
incorrect.
Change-Id: I3624cb2548a0ee3da56a2cca62ed50b0dfbf7817
Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/196266
Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
(cherry picked from commit bc0187702061fe326422c070c592a18cd93de723)
Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com>
---
src/include/reg_script.h | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/src/include/reg_script.h b/src/include/reg_script.h
index 72e1e96..97b4fb0 100644
--- a/src/include/reg_script.h
+++ b/src/include/reg_script.h
@@ -179,11 +179,11 @@ struct reg_script {
#define REG_IO_RMW32(reg_, mask_, value_) \
REG_SCRIPT_IO(RMW, 32, reg_, mask_, value_, 0)
#define REG_IO_OR8(reg_, value_) \
- REG_SCRIPT_IO_RMW8(_reg, 0xff, value)
+ REG_IO_RMW8(reg_, 0xff, value_)
#define REG_IO_OR16(reg_, value_) \
- REG_SCRIPT_IO_RMW16(_reg, 0xffff, value)
+ REG_IO_RMW16(reg_, 0xffff, value_)
#define REG_IO_OR32(reg_, value_) \
- REG_SCRIPT_IO_RMW32(_reg, 0xffffffff, value)
+ REG_IO_RMW32(reg_, 0xffffffff, value_)
#define REG_IO_POLL8(reg_, mask_, value_, timeout_) \
REG_SCRIPT_IO(POLL, 8, reg_, mask_, value_, timeout_)
#define REG_IO_POLL16(reg_, mask_, value_, timeout_) \
1
0
Patch set updated for coreboot: 52559a3 edid: Fix extension parsing when EDID blob does not have any extensions.
by Paul Menzel 29 Sep '14
by Paul Menzel 29 Sep '14
29 Sep '14
Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6995
-gerrit
commit 52559a3989718502f71e2336ed0a2702db8d1844
Author: Hung-Te Lin <hungte(a)chromium.org>
Date: Thu Apr 3 18:35:58 2014 +0800
edid: Fix extension parsing when EDID blob does not have any extensions.
When parsing "extensions", we should skip the first EDID (main) block and start
from offset 128 (EDID may have only main block, so an EDID without any
extension is fine) because the header format for main block and extensions are
different.
Without this we will see "Unknown extension block" on all EDIDs, and seeing an
error (1) return value for EDIDs without extension.
Also, after the first "unknown" error is fixed, we can now collect all return
values from parse_extension, and return an error when any of the extensions are
wrong (not just last one).
Change-Id: I0ee029ac8ec6800687cd7749e23989399e721109
Signed-off-by: Hung-Te Lin <hungte(a)chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/193011
(cherry picked from commit fdf0cc2e9573c19b550fa2b5e4e06337b114f864)
Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com>
---
src/lib/edid.c | 10 ++++++++--
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/src/lib/edid.c b/src/lib/edid.c
index 0dc86d5..6bd471a 100644
--- a/src/lib/edid.c
+++ b/src/lib/edid.c
@@ -1261,8 +1261,14 @@ int decode_edid(unsigned char *edid, int size, struct edid *out)
printk(BIOS_SPEW, "Checksum\n");
do_checksum(edid);
- for(i = 0; i < size; i += 128)
- nonconformant_extension = parse_extension(out, &edid[i]);
+
+ /* EDID v2.0 has a larger blob (256 bytes) and may have some problem in
+ * the extension parsing loop below. Since v2.0 was quickly deprecated
+ * by v1.3 and we are unlikely to use any EDID 2.0 panels, we ignore
+ * that case now and can fix it when we need to use a real 2.0 panel.
+ */
+ for(i = 128; i < size; i += 128)
+ nonconformant_extension += parse_extension(out, &edid[i]);
/*
* x = edid;
* for (edid_lines /= 8; edid_lines > 1; edid_lines--) {
1
0
29 Sep '14
Isaac Christensen (isaac.christensen(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6998
-gerrit
commit b1186c60aaa0314436f276654ce47281f1ebc41f
Author: Hung-Te Lin <hungte(a)chromium.org>
Date: Thu Apr 3 21:13:11 2014 +0800
edid: Support EDID 1.4.
EDID v1.4 has changed some fields (0xfc - Monitor Name, 0xfd - Monitor Range
Limits) to optional so we need to list the requirements explicitly instead of
sharing v1.3 requirements.
Change-Id: I5c7ca06893bd20e178bc35164c4ca639c881e00b
Signed-off-by: Hung-Te Lin <hungte(a)chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/193013
(cherry picked from commit 2ad598b8bd620117e70e13347365d74a7c6b87ef)
Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com>
---
src/lib/edid.c | 19 ++++++++++++++++++-
1 file changed, 18 insertions(+), 1 deletion(-)
diff --git a/src/lib/edid.c b/src/lib/edid.c
index b171c8b..6efe6a9 100644
--- a/src/lib/edid.c
+++ b/src/lib/edid.c
@@ -1251,7 +1251,24 @@ int decode_edid(unsigned char *edid, int size, struct edid *out)
* }
*/
- if (claims_one_point_three) {
+ if (claims_one_point_four) {
+ if (nonconformant_digital_display ||
+ !has_valid_string_termination ||
+ !has_valid_descriptor_pad ||
+ !has_preferred_timing)
+ conformant = 0;
+ if (!conformant)
+ printk(BIOS_ERR, "EDID block does NOT conform to EDID 1.4!\n");
+ if (nonconformant_digital_display)
+ printk(BIOS_ERR, "\tDigital display field contains garbage: %x\n",
+ nonconformant_digital_display);
+ if (!has_valid_string_termination)
+ printk(BIOS_ERR, "\tDetailed block string not properly terminated\n");
+ if (!has_valid_descriptor_pad)
+ printk(BIOS_ERR, "\tInvalid descriptor block padding\n");
+ if (!has_preferred_timing)
+ printk(BIOS_ERR, "\tMissing preferred timing\n");
+ } else if (claims_one_point_three) {
if (nonconformant_digital_display ||
!has_valid_string_termination ||
!has_valid_descriptor_pad ||
1
0
New patch to review for coreboot: 3866ead edid: Accept valid detail blocks without timing descriptor.
by Isaac Christensen 29 Sep '14
by Isaac Christensen 29 Sep '14
29 Sep '14
Isaac Christensen (isaac.christensen(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6997
-gerrit
commit 3866ead22840b4301683a037eeb568e947c0cbbb
Author: Hung-Te Lin <hungte(a)chromium.org>
Date: Thu Apr 3 19:59:37 2014 +0800
edid: Accept valid detail blocks without timing descriptor.
The detail block may contain timing descriptor, or other fields like monitor
descriptor, so we should return 1 in detailed_block function when a valid
structure is found, otherwise for any EDID containing monitor descriptor we will
see following error messages:
EDID block does not conform at all!
Detailed blocks filled with garbage
Change-Id: Ib4e91d648741e5b54a558d53a1152273c7341427
Signed-off-by: Hung-Te Lin <hungte(a)chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/193002
(cherry picked from commit a1f212d6aaa14d5f795beeabdb8b7b8a79578c33)
Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com>
---
src/lib/edid.c | 22 +++++++++++-----------
1 file changed, 11 insertions(+), 11 deletions(-)
diff --git a/src/lib/edid.c b/src/lib/edid.c
index 3b312ba..b171c8b 100644
--- a/src/lib/edid.c
+++ b/src/lib/edid.c
@@ -208,7 +208,7 @@ detailed_block(struct edid *out, unsigned char *x, int in_extension)
* 0x0e is used by EPI: http://www.epi-standard.org/
*/
printk(BIOS_SPEW, "Manufacturer-specified data, tag %d\n", x[3]);
- return 0;
+ return 1;
}
switch (x[3]) {
case 0x10:
@@ -216,11 +216,11 @@ detailed_block(struct edid *out, unsigned char *x, int in_extension)
for (i = 5; i < 18; i++)
if (x[i] != 0x00)
has_valid_dummy_block = 0;
- return 0;
+ return 1;
case 0xF7:
/* TODO */
printk(BIOS_SPEW, "Established timings III\n");
- return 0;
+ return 1;
case 0xF8:
{
int valid_cvt = 1; /* just this block */
@@ -232,26 +232,26 @@ detailed_block(struct edid *out, unsigned char *x, int in_extension)
for (i = 0; i < 4; i++)
valid_cvt &= detailed_cvt_descriptor(out, x + 6 + (i * 3), (i == 0));
has_valid_cvt &= valid_cvt;
- return 0;
+ return 1;
}
case 0xF9:
/* TODO */
printk(BIOS_SPEW, "Color management data\n");
- return 0;
+ return 1;
case 0xFA:
/* TODO */
printk(BIOS_SPEW, "More standard timings\n");
- return 0;
+ return 1;
case 0xFB:
/* TODO */
printk(BIOS_SPEW, "Color point\n");
- return 0;
+ return 1;
case 0xFC:
printk(BIOS_SPEW, "Monitor name: %s\n",
extract_string(x + 5,
&has_valid_string_termination,
13));
- return 0;
+ return 1;
case 0xFD:
{
int h_max_offset = 0, h_min_offset = 0;
@@ -396,7 +396,7 @@ detailed_block(struct edid *out, unsigned char *x, int in_extension)
* Slightly weird to return a global, but I've never seen any
* EDID block wth two range descriptors, so it's harmless.
*/
- return 0;
+ return 1;
}
case 0xFE:
/*
@@ -405,11 +405,11 @@ detailed_block(struct edid *out, unsigned char *x, int in_extension)
*/
printk(BIOS_SPEW, "ASCII string: %s\n",
extract_string(x + 5, &has_valid_string_termination, 13));
- return 0;
+ return 1;
case 0xFF:
printk(BIOS_SPEW, "Serial number: %s\n",
extract_string(x + 5, &has_valid_string_termination, 13));
- return 0;
+ return 1;
default:
printk(BIOS_SPEW, "Unknown monitor description type %d\n", x[3]);
return 0;
1
0
New patch to review for coreboot: 79add71 edid: Fix string extraction in Monitor Descriptors.
by Isaac Christensen 29 Sep '14
by Isaac Christensen 29 Sep '14
29 Sep '14
Isaac Christensen (isaac.christensen(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6996
-gerrit
commit 79add71c033786ed4f7e695d64db11d6a291cf93
Author: Hung-Te Lin <hungte(a)chromium.org>
Date: Thu Apr 3 19:21:03 2014 +0800
edid: Fix string extraction in Monitor Descriptors.
The ASCII Data String in EDID Monitor Descriptor (3.10.3) is "Stored as ASCII,
code page #437" and may contain special characters like '-'. The isalnum check
should be removed.
Also, the "Monitor Name" (0xfc) does not need to always end with 0Ah, so the
name_descriptor_terminated should be replaced by has_valid_string_termination.
Change-Id: I12a670237e12577fc971c0fbd9b2a61c82040ad3
Signed-off-by: Hung-Te Lin <hungte(a)chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/193001
(cherry picked from commit 671f82fd5963e32e72d3886aa242cb3e8519f226)
Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com>
---
src/lib/edid.c | 61 +++++++++++++++-------------------------------------------
1 file changed, 16 insertions(+), 45 deletions(-)
diff --git a/src/lib/edid.c b/src/lib/edid.c
index 6bd471a..3b312ba 100644
--- a/src/lib/edid.c
+++ b/src/lib/edid.c
@@ -47,7 +47,6 @@ static int nonconformant_digital_display = 0;
static int nonconformant_extension = 0;
static int did_detailed_timing = 0;
static int has_name_descriptor = 0;
-static int name_descriptor_terminated = 0;
static int has_range_descriptor = 0;
static int has_preferred_timing = 0;
static int has_valid_checksum = 0;
@@ -146,18 +145,9 @@ detailed_cvt_descriptor(struct edid *out, unsigned char *x, int first)
return valid;
}
-static int isalnum(char x)
-{
- if (x >= 'a' && x <= 'z')
- return 1;
- if (x >= 'A' && x <= 'Z')
- return 1;
- if (x >= '0' && x <= '9')
- return 1;
- return 0;
-
-}
-/* extract a string from a detailed subblock, checking for termination */
+/* extract a CP437 string from a detailed subblock, checking for termination (if
+ * less than len of bytes) with LF and padded with SP.
+ */
static char *
extract_string(unsigned char *x, int *valid_termination, int len)
{
@@ -167,20 +157,16 @@ extract_string(unsigned char *x, int *valid_termination, int len)
memset(ret, 0, sizeof(ret));
for (i = 0; i < len; i++) {
- if (isalnum(x[i])) {
- ret[i] = x[i];
- } else if (!seen_newline) {
- if (x[i] == 0x0a) {
- seen_newline = 1;
- } else {
- *valid_termination = 0;
- return ret;
- }
- } else {
+ if (seen_newline) {
if (x[i] != 0x20) {
*valid_termination = 0;
return ret;
}
+ } else if (x[i] == 0x0a) {
+ seen_newline = 1;
+ } else {
+ /* normal characters */
+ ret[i] = x[i];
}
}
@@ -191,7 +177,6 @@ extract_string(unsigned char *x, int *valid_termination, int len)
static int
detailed_block(struct edid *out, unsigned char *x, int in_extension)
{
- static unsigned char name[53];
int i;
#if 1
printk(BIOS_SPEW, "Hex of detail: ");
@@ -262,21 +247,10 @@ detailed_block(struct edid *out, unsigned char *x, int in_extension)
printk(BIOS_SPEW, "Color point\n");
return 0;
case 0xFC:
- /* XXX should check for spaces after the \n */
- /* XXX check: terminated with 0x0A, padded with 0x20 */
- has_name_descriptor = 1;
- if (strchr((char *)name, '\n')) return 0;
- /* avoid strncat
- strncat((char *)name, (char *)x + 5, 13);
- */
- if (strchr((char *)name, '\n') || strchr((char *)x+5, '\n')) {
- name_descriptor_terminated = 1;
- /* later.
- printk(BIOS_SPEW, "Monitor name: %s\n",
- extract_string(name, &has_valid_string_termination,
- strlen((char *)name)));
- */
- }
+ printk(BIOS_SPEW, "Monitor name: %s\n",
+ extract_string(x + 5,
+ &has_valid_string_termination,
+ 13));
return 0;
case 0xFD:
{
@@ -1282,7 +1256,6 @@ int decode_edid(unsigned char *edid, int size, struct edid *out)
!has_valid_string_termination ||
!has_valid_descriptor_pad ||
!has_name_descriptor ||
- !name_descriptor_terminated ||
!has_preferred_timing ||
!has_range_descriptor)
conformant = 0;
@@ -1293,8 +1266,6 @@ int decode_edid(unsigned char *edid, int size, struct edid *out)
nonconformant_digital_display);
if (!has_name_descriptor)
printk(BIOS_ERR, "\tMissing name descriptor\n");
- else if (!name_descriptor_terminated)
- printk(BIOS_ERR, "\tName descriptor not terminated with a newline\n");
if (!has_preferred_timing)
printk(BIOS_ERR, "\tMissing preferred timing\n");
if (!has_range_descriptor)
@@ -1305,15 +1276,15 @@ int decode_edid(unsigned char *edid, int size, struct edid *out)
printk(BIOS_ERR, "\tDetailed block string not properly terminated\n");
} else if (claims_one_point_two) {
if (nonconformant_digital_display ||
- (has_name_descriptor && !name_descriptor_terminated))
+ !has_valid_string_termination)
conformant = 0;
if (!conformant)
printk(BIOS_ERR, "EDID block does NOT conform to EDID 1.2!\n");
if (nonconformant_digital_display)
printk(BIOS_ERR, "\tDigital display field contains garbage: %x\n",
nonconformant_digital_display);
- if (has_name_descriptor && !name_descriptor_terminated)
- printk(BIOS_ERR, "\tName descriptor not terminated with a newline\n");
+ if (!has_valid_string_termination)
+ printk(BIOS_ERR, "\tDetailed block string not properly terminated\n");
} else if (claims_one_point_oh) {
if (seen_non_detailed_descriptor)
conformant = 0;
1
0
New patch to review for coreboot: 095c784 edid: Fix extension parsing when EDID blob does not have any extensions.
by Isaac Christensen 29 Sep '14
by Isaac Christensen 29 Sep '14
29 Sep '14
Isaac Christensen (isaac.christensen(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6995
-gerrit
commit 095c784f66bb12647ea0eefe96782a3777d62088
Author: Hung-Te Lin <hungte(a)chromium.org>
Date: Thu Apr 3 18:35:58 2014 +0800
edid: Fix extension parsing when EDID blob does not have any extensions.
When parsing "extensions", we should skip the first EDID (main) block and start
from offset 128 (EDID may have only main block, so an EDID without any
extension is fine) because the header format for main block and extensions are
different.
Without this we will see "Unknown extension block" on all EDIDs, and seeing a
error (1) return value for EDIDs without extension.
Also, after the first "unknown" error is fixed, we can now collect all return
values from parse_extension, and give error when any of the extensions are wrong
(not just last one).
Change-Id: I0ee029ac8ec6800687cd7749e23989399e721109
Signed-off-by: Hung-Te Lin <hungte(a)chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/193011
(cherry picked from commit fdf0cc2e9573c19b550fa2b5e4e06337b114f864)
Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com>
---
src/lib/edid.c | 10 ++++++++--
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/src/lib/edid.c b/src/lib/edid.c
index 0dc86d5..6bd471a 100644
--- a/src/lib/edid.c
+++ b/src/lib/edid.c
@@ -1261,8 +1261,14 @@ int decode_edid(unsigned char *edid, int size, struct edid *out)
printk(BIOS_SPEW, "Checksum\n");
do_checksum(edid);
- for(i = 0; i < size; i += 128)
- nonconformant_extension = parse_extension(out, &edid[i]);
+
+ /* EDID v2.0 has a larger blob (256 bytes) and may have some problem in
+ * the extension parsing loop below. Since v2.0 was quickly deprecated
+ * by v1.3 and we are unlikely to use any EDID 2.0 panels, we ignore
+ * that case now and can fix it when we need to use a real 2.0 panel.
+ */
+ for(i = 128; i < size; i += 128)
+ nonconformant_extension += parse_extension(out, &edid[i]);
/*
* x = edid;
* for (edid_lines /= 8; edid_lines > 1; edid_lines--) {
1
0
29 Sep '14
Isaac Christensen (isaac.christensen(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6994
-gerrit
commit 40ab3cd6740446ff14c509e39afee1d078ab65aa
Author: Hung-Te Lin <hungte(a)chromium.org>
Date: Thu Apr 3 18:33:01 2014 +0800
edid: Fix source indent.
Some lines in decode_edid have incorrect indent levels.
Change-Id: Icc9cb57ff8dd2e2056599b3dc733fe5ac4e41c16
Signed-off-by: Hung-Te Lin <hungte(a)chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/193010
Reviewed-by: Gabe Black <gabeblack(a)chromium.org>
(cherry picked from commit 3211ac0a29a037c5414f9ed1736c8f7822ad116b)
Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com>
---
src/lib/edid.c | 462 ++++++++++++++++++++++++++++-----------------------------
1 file changed, 231 insertions(+), 231 deletions(-)
diff --git a/src/lib/edid.c b/src/lib/edid.c
index 1ad9fea..0dc86d5 100644
--- a/src/lib/edid.c
+++ b/src/lib/edid.c
@@ -1008,29 +1008,29 @@ int decode_edid(unsigned char *edid, int size, struct edid *out)
(unsigned short)(edid[0x0A] + (edid[0x0B] << 8)),
(unsigned int)(edid[0x0C] + (edid[0x0D] << 8)
+ (edid[0x0E] << 16) + (edid[0x0F] << 24)));
- /* XXX need manufacturer ID table */
-
- if (edid[0x10] < 55 || edid[0x10] == 0xff) {
- has_valid_week = 1;
- if (edid[0x11] > 0x0f) {
- if (edid[0x10] == 0xff) {
+ /* XXX need manufacturer ID table */
+
+ if (edid[0x10] < 55 || edid[0x10] == 0xff) {
+ has_valid_week = 1;
+ if (edid[0x11] > 0x0f) {
+ if (edid[0x10] == 0xff) {
+ has_valid_year = 1;
+ printk(BIOS_SPEW, "Made week %hhu of model year %hhu\n", edid[0x10],
+ edid[0x11]);
+ out->week = edid[0x10];
+ out->year = edid[0x11];
+ } else {
+ /* we know it's at least 2013, when this code was written */
+ if (edid[0x11] + 90 <= 2013) {
has_valid_year = 1;
- printk(BIOS_SPEW, "Made week %hhu of model year %hhu\n", edid[0x10],
- edid[0x11]);
+ printk(BIOS_SPEW, "Made week %hhu of %d\n",
+ edid[0x10], edid[0x11] + 1990);
out->week = edid[0x10];
- out->year = edid[0x11];
- } else {
- /* we know it's at least 2013, when this code was written */
- if (edid[0x11] + 90 <= 2013) {
- has_valid_year = 1;
- printk(BIOS_SPEW, "Made week %hhu of %d\n",
- edid[0x10], edid[0x11] + 1990);
- out->week = edid[0x10];
- out->year = edid[0x11] + 1990;
- }
+ out->year = edid[0x11] + 1990;
}
}
}
+ }
printk(BIOS_SPEW, "EDID version: %hhu.%hhu\n", edid[0x12], edid[0x13]);
@@ -1081,7 +1081,7 @@ int decode_edid(unsigned char *edid, int size, struct edid *out)
case 0x04: printk(BIOS_SPEW, "MDDI interface\n"); break;
case 0x05: printk(BIOS_SPEW, "DisplayPort interface\n"); break;
default:
- nonconformant_digital_display = 1;
+ nonconformant_digital_display = 1;
}
out->type = edid[0x14] & 0x0f;
} else if (claims_one_point_two) {
@@ -1129,243 +1129,243 @@ int decode_edid(unsigned char *edid, int size, struct edid *out)
}
- if (edid[0x15] && edid[0x16]) {
- printk(BIOS_SPEW, "Maximum image size: %d cm x %d cm\n",
- edid[0x15], edid[0x16]);
- out->xsize_cm = edid[0x15];
- out->ysize_cm = edid[0x16];
- } else if (claims_one_point_four && (edid[0x15] || edid[0x16])) {
- if (edid[0x15]) {
- printk(BIOS_SPEW, "Aspect ratio is %f (landscape)\n",
- 100.0/(edid[0x16] + 99));
- /* truncated to integer %. We try to avoid floating point */
- out->aspect_landscape = 10000 /(edid[0x16] + 99);
- } else {
- printk(BIOS_SPEW, "Aspect ratio is %f (portrait)\n",
- 100.0/(edid[0x15] + 99));
- out->aspect_portrait = 10000 /(edid[0x16] + 99);
- }
+ if (edid[0x15] && edid[0x16]) {
+ printk(BIOS_SPEW, "Maximum image size: %d cm x %d cm\n",
+ edid[0x15], edid[0x16]);
+ out->xsize_cm = edid[0x15];
+ out->ysize_cm = edid[0x16];
+ } else if (claims_one_point_four && (edid[0x15] || edid[0x16])) {
+ if (edid[0x15]) {
+ printk(BIOS_SPEW, "Aspect ratio is %f (landscape)\n",
+ 100.0/(edid[0x16] + 99));
+ /* truncated to integer %. We try to avoid floating point */
+ out->aspect_landscape = 10000 /(edid[0x16] + 99);
} else {
- /* Either or both can be zero for 1.3 and before */
- printk(BIOS_SPEW, "Image size is variable\n");
+ printk(BIOS_SPEW, "Aspect ratio is %f (portrait)\n",
+ 100.0/(edid[0x15] + 99));
+ out->aspect_portrait = 10000 /(edid[0x16] + 99);
}
+ } else {
+ /* Either or both can be zero for 1.3 and before */
+ printk(BIOS_SPEW, "Image size is variable\n");
+ }
- if (edid[0x17] == 0xff) {
- if (claims_one_point_four)
- printk(BIOS_SPEW, "Gamma is defined in an extension block\n");
- else
- /* XXX Technically 1.3 doesn't say this... */
- printk(BIOS_SPEW, "Gamma: 1.0\n");
- } else printk(BIOS_SPEW, "Gamma: %d%%\n", ((edid[0x17] + 100)));
- printk(BIOS_SPEW, "Check DPMS levels\n");
- if (edid[0x18] & 0xE0) {
- printk(BIOS_SPEW, "DPMS levels:");
- if (edid[0x18] & 0x80) printk(BIOS_SPEW, " Standby");
- if (edid[0x18] & 0x40) printk(BIOS_SPEW, " Suspend");
- if (edid[0x18] & 0x20) printk(BIOS_SPEW, " Off");
- printk(BIOS_SPEW, "\n");
- }
+ if (edid[0x17] == 0xff) {
+ if (claims_one_point_four)
+ printk(BIOS_SPEW, "Gamma is defined in an extension block\n");
+ else
+ /* XXX Technically 1.3 doesn't say this... */
+ printk(BIOS_SPEW, "Gamma: 1.0\n");
+ } else printk(BIOS_SPEW, "Gamma: %d%%\n", ((edid[0x17] + 100)));
+ printk(BIOS_SPEW, "Check DPMS levels\n");
+ if (edid[0x18] & 0xE0) {
+ printk(BIOS_SPEW, "DPMS levels:");
+ if (edid[0x18] & 0x80) printk(BIOS_SPEW, " Standby");
+ if (edid[0x18] & 0x40) printk(BIOS_SPEW, " Suspend");
+ if (edid[0x18] & 0x20) printk(BIOS_SPEW, " Off");
+ printk(BIOS_SPEW, "\n");
+ }
-/* FIXME: this is from 1.4 spec, check earlier */
- if (analog) {
- switch (edid[0x18] & 0x18) {
+ /* FIXME: this is from 1.4 spec, check earlier */
+ if (analog) {
+ switch (edid[0x18] & 0x18) {
case 0x00: printk(BIOS_SPEW, "Monochrome or grayscale display\n"); break;
case 0x08: printk(BIOS_SPEW, "RGB color display\n"); break;
case 0x10: printk(BIOS_SPEW, "Non-RGB color display\n"); break;
case 0x18: printk(BIOS_SPEW, "Undefined display color type\n");
- }
- } else {
- printk(BIOS_SPEW, "Supported color formats: RGB 4:4:4");
- if (edid[0x18] & 0x10)
- printk(BIOS_SPEW, ", YCrCb 4:4:4");
- if (edid[0x18] & 0x08)
- printk(BIOS_SPEW, ", YCrCb 4:2:2");
- printk(BIOS_SPEW, "\n");
}
+ } else {
+ printk(BIOS_SPEW, "Supported color formats: RGB 4:4:4");
+ if (edid[0x18] & 0x10)
+ printk(BIOS_SPEW, ", YCrCb 4:4:4");
+ if (edid[0x18] & 0x08)
+ printk(BIOS_SPEW, ", YCrCb 4:2:2");
+ printk(BIOS_SPEW, "\n");
+ }
- if (edid[0x18] & 0x04)
- printk(BIOS_SPEW, "Default (sRGB) color space is primary color space\n");
- if (edid[0x18] & 0x02) {
- printk(BIOS_SPEW, "First detailed timing is preferred timing\n");
- has_preferred_timing = 1;
- }
- if (edid[0x18] & 0x01)
- printk(BIOS_SPEW, "Supports GTF timings within operating range\n");
+ if (edid[0x18] & 0x04)
+ printk(BIOS_SPEW, "Default (sRGB) color space is primary color space\n");
+ if (edid[0x18] & 0x02) {
+ printk(BIOS_SPEW, "First detailed timing is preferred timing\n");
+ has_preferred_timing = 1;
+ }
+ if (edid[0x18] & 0x01)
+ printk(BIOS_SPEW, "Supports GTF timings within operating range\n");
- /* XXX color section */
+ /* XXX color section */
- printk(BIOS_SPEW, "Established timings supported:\n");
- /* it's not yet clear we want all this stuff in the edid struct.
- * Let's wait.
- */
- for (i = 0; i < 17; i++) {
- if (edid[0x23 + i / 8] & (1 << (7 - i % 8))) {
- printk(BIOS_SPEW, " %dx%d@%dHz\n", established_timings[i].x,
- established_timings[i].y, established_timings[i].refresh);
- }
+ printk(BIOS_SPEW, "Established timings supported:\n");
+ /* it's not yet clear we want all this stuff in the edid struct.
+ * Let's wait.
+ */
+ for (i = 0; i < 17; i++) {
+ if (edid[0x23 + i / 8] & (1 << (7 - i % 8))) {
+ printk(BIOS_SPEW, " %dx%d@%dHz\n", established_timings[i].x,
+ established_timings[i].y, established_timings[i].refresh);
}
+ }
- printk(BIOS_SPEW, "Standard timings supported:\n");
- for (i = 0; i < 8; i++) {
- uint8_t b1 = edid[0x26 + i * 2], b2 = edid[0x26 + i * 2 + 1];
- unsigned int x, y = 0, refresh;
+ printk(BIOS_SPEW, "Standard timings supported:\n");
+ for (i = 0; i < 8; i++) {
+ uint8_t b1 = edid[0x26 + i * 2], b2 = edid[0x26 + i * 2 + 1];
+ unsigned int x, y = 0, refresh;
- if (b1 == 0x01 && b2 == 0x01)
- continue;
+ if (b1 == 0x01 && b2 == 0x01)
+ continue;
- if (b1 == 0) {
- printk(BIOS_SPEW, "non-conformant standard timing (0 horiz)\n");
- continue;
- }
- x = (b1 + 31) * 8;
- switch ((b2 >> 6) & 0x3) {
- case 0x00:
- if (claims_one_point_three)
- y = x * 10 / 16;
- else
- y = x;
- break;
- case 0x01:
- y = x * 3 / 4;
- break;
- case 0x02:
- y = x * 4 / 5;
- break;
- case 0x03:
- y = x * 9 / 16;
- break;
- }
- refresh = 60 + (b2 & 0x3f);
-
- printk(BIOS_SPEW, " %dx%d@%dHz\n", x, y, refresh);
+ if (b1 == 0) {
+ printk(BIOS_SPEW, "non-conformant standard timing (0 horiz)\n");
+ continue;
}
+ x = (b1 + 31) * 8;
+ switch ((b2 >> 6) & 0x3) {
+ case 0x00:
+ if (claims_one_point_three)
+ y = x * 10 / 16;
+ else
+ y = x;
+ break;
+ case 0x01:
+ y = x * 3 / 4;
+ break;
+ case 0x02:
+ y = x * 4 / 5;
+ break;
+ case 0x03:
+ y = x * 9 / 16;
+ break;
+ }
+ refresh = 60 + (b2 & 0x3f);
- /* detailed timings */
- printk(BIOS_SPEW, "Detailed timings\n");
- has_valid_detailed_blocks = detailed_block(out, edid + 0x36, 0);
- if (has_preferred_timing && !did_detailed_timing)
- has_preferred_timing = 0; /* not really accurate... */
- has_valid_detailed_blocks &= detailed_block(out, edid + 0x48, 0);
- has_valid_detailed_blocks &= detailed_block(out, edid + 0x5A, 0);
- has_valid_detailed_blocks &= detailed_block(out, edid + 0x6C, 0);
-
- /* check this, 1.4 verification guide says otherwise */
- if (edid[0x7e]) {
- printk(BIOS_SPEW, "Has %d extension blocks\n", edid[0x7e]);
- /* 2 is impossible because of the block map */
- if (edid[0x7e] != 2)
- has_valid_extension_count = 1;
- } else {
+ printk(BIOS_SPEW, " %dx%d@%dHz\n", x, y, refresh);
+ }
+
+ /* detailed timings */
+ printk(BIOS_SPEW, "Detailed timings\n");
+ has_valid_detailed_blocks = detailed_block(out, edid + 0x36, 0);
+ if (has_preferred_timing && !did_detailed_timing)
+ has_preferred_timing = 0; /* not really accurate... */
+ has_valid_detailed_blocks &= detailed_block(out, edid + 0x48, 0);
+ has_valid_detailed_blocks &= detailed_block(out, edid + 0x5A, 0);
+ has_valid_detailed_blocks &= detailed_block(out, edid + 0x6C, 0);
+
+ /* check this, 1.4 verification guide says otherwise */
+ if (edid[0x7e]) {
+ printk(BIOS_SPEW, "Has %d extension blocks\n", edid[0x7e]);
+ /* 2 is impossible because of the block map */
+ if (edid[0x7e] != 2)
has_valid_extension_count = 1;
- }
+ } else {
+ has_valid_extension_count = 1;
+ }
- printk(BIOS_SPEW, "Checksum\n");
- do_checksum(edid);
- for(i = 0; i < size; i += 128)
- nonconformant_extension = parse_extension(out, &edid[i]);
-/*
- x = edid;
- for (edid_lines /= 8; edid_lines > 1; edid_lines--) {
- x += 128;
- nonconformant_extension += parse_extension(x);
- }
-*/
-
- if (claims_one_point_three) {
- if (nonconformant_digital_display ||
- !has_valid_string_termination ||
- !has_valid_descriptor_pad ||
- !has_name_descriptor ||
- !name_descriptor_terminated ||
- !has_preferred_timing ||
- !has_range_descriptor)
- conformant = 0;
- if (!conformant)
- printk(BIOS_ERR, "EDID block does NOT conform to EDID 1.3!\n");
- if (nonconformant_digital_display)
- printk(BIOS_ERR, "\tDigital display field contains garbage: %x\n",
- nonconformant_digital_display);
- if (!has_name_descriptor)
- printk(BIOS_ERR, "\tMissing name descriptor\n");
- else if (!name_descriptor_terminated)
- printk(BIOS_ERR, "\tName descriptor not terminated with a newline\n");
- if (!has_preferred_timing)
- printk(BIOS_ERR, "\tMissing preferred timing\n");
- if (!has_range_descriptor)
- printk(BIOS_ERR, "\tMissing monitor ranges\n");
- if (!has_valid_descriptor_pad) /* Might be more than just 1.3 */
- printk(BIOS_ERR, "\tInvalid descriptor block padding\n");
- if (!has_valid_string_termination) /* Likewise */
- printk(BIOS_ERR, "\tDetailed block string not properly terminated\n");
- } else if (claims_one_point_two) {
- if (nonconformant_digital_display ||
- (has_name_descriptor && !name_descriptor_terminated))
- conformant = 0;
- if (!conformant)
- printk(BIOS_ERR, "EDID block does NOT conform to EDID 1.2!\n");
- if (nonconformant_digital_display)
- printk(BIOS_ERR, "\tDigital display field contains garbage: %x\n",
- nonconformant_digital_display);
- if (has_name_descriptor && !name_descriptor_terminated)
- printk(BIOS_ERR, "\tName descriptor not terminated with a newline\n");
- } else if (claims_one_point_oh) {
- if (seen_non_detailed_descriptor)
- conformant = 0;
- if (!conformant)
- printk(BIOS_ERR, "EDID block does NOT conform to EDID 1.0!\n");
- if (seen_non_detailed_descriptor)
- printk(BIOS_ERR, "\tHas descriptor blocks other than detailed timings\n");
- }
+ printk(BIOS_SPEW, "Checksum\n");
+ do_checksum(edid);
+ for(i = 0; i < size; i += 128)
+ nonconformant_extension = parse_extension(out, &edid[i]);
+ /*
+ * x = edid;
+ * for (edid_lines /= 8; edid_lines > 1; edid_lines--) {
+ * x += 128;
+ * nonconformant_extension += parse_extension(x);
+ * }
+ */
- if (nonconformant_extension ||
- !has_valid_checksum ||
- !has_valid_cvt ||
- !has_valid_year ||
- !has_valid_week ||
- !has_valid_detailed_blocks ||
- !has_valid_dummy_block ||
- !has_valid_extension_count ||
- !has_valid_descriptor_ordering ||
- !has_valid_range_descriptor ||
- !manufacturer_name_well_formed) {
+ if (claims_one_point_three) {
+ if (nonconformant_digital_display ||
+ !has_valid_string_termination ||
+ !has_valid_descriptor_pad ||
+ !has_name_descriptor ||
+ !name_descriptor_terminated ||
+ !has_preferred_timing ||
+ !has_range_descriptor)
conformant = 0;
- printk(BIOS_ERR, "EDID block does not conform at all!\n");
- if (nonconformant_extension)
- printk(BIOS_ERR, "\tHas %d nonconformant extension block(s)\n",
- nonconformant_extension);
- if (!has_valid_checksum)
- printk(BIOS_ERR, "\tBlock has broken checksum\n");
- if (!has_valid_cvt)
- printk(BIOS_ERR, "\tBroken 3-byte CVT blocks\n");
- if (!has_valid_year)
- printk(BIOS_ERR, "\tBad year of manufacture\n");
- if (!has_valid_week)
- printk(BIOS_ERR, "\tBad week of manufacture\n");
- if (!has_valid_detailed_blocks)
- printk(BIOS_ERR, "\tDetailed blocks filled with garbage\n");
- if (!has_valid_dummy_block)
- printk(BIOS_ERR, "\tDummy block filled with garbage\n");
- if (!has_valid_extension_count)
- printk(BIOS_ERR, "\tImpossible extension block count\n");
- if (!manufacturer_name_well_formed)
- printk(BIOS_ERR, "\tManufacturer name field contains garbage\n");
- if (!has_valid_descriptor_ordering)
- printk(BIOS_ERR, "\tInvalid detailed timing descriptor ordering\n");
- if (!has_valid_range_descriptor)
- printk(BIOS_ERR, "\tRange descriptor contains garbage\n");
- if (!has_valid_max_dotclock)
- printk(BIOS_ERR, "\tEDID 1.4 block does not set max dotclock\n");
- }
+ if (!conformant)
+ printk(BIOS_ERR, "EDID block does NOT conform to EDID 1.3!\n");
+ if (nonconformant_digital_display)
+ printk(BIOS_ERR, "\tDigital display field contains garbage: %x\n",
+ nonconformant_digital_display);
+ if (!has_name_descriptor)
+ printk(BIOS_ERR, "\tMissing name descriptor\n");
+ else if (!name_descriptor_terminated)
+ printk(BIOS_ERR, "\tName descriptor not terminated with a newline\n");
+ if (!has_preferred_timing)
+ printk(BIOS_ERR, "\tMissing preferred timing\n");
+ if (!has_range_descriptor)
+ printk(BIOS_ERR, "\tMissing monitor ranges\n");
+ if (!has_valid_descriptor_pad) /* Might be more than just 1.3 */
+ printk(BIOS_ERR, "\tInvalid descriptor block padding\n");
+ if (!has_valid_string_termination) /* Likewise */
+ printk(BIOS_ERR, "\tDetailed block string not properly terminated\n");
+ } else if (claims_one_point_two) {
+ if (nonconformant_digital_display ||
+ (has_name_descriptor && !name_descriptor_terminated))
+ conformant = 0;
+ if (!conformant)
+ printk(BIOS_ERR, "EDID block does NOT conform to EDID 1.2!\n");
+ if (nonconformant_digital_display)
+ printk(BIOS_ERR, "\tDigital display field contains garbage: %x\n",
+ nonconformant_digital_display);
+ if (has_name_descriptor && !name_descriptor_terminated)
+ printk(BIOS_ERR, "\tName descriptor not terminated with a newline\n");
+ } else if (claims_one_point_oh) {
+ if (seen_non_detailed_descriptor)
+ conformant = 0;
+ if (!conformant)
+ printk(BIOS_ERR, "EDID block does NOT conform to EDID 1.0!\n");
+ if (seen_non_detailed_descriptor)
+ printk(BIOS_ERR, "\tHas descriptor blocks other than detailed timings\n");
+ }
- if (warning_excessive_dotclock_correction)
- printk(BIOS_ERR,
- "Warning: CVT block corrects dotclock by more than 9.75MHz\n");
- if (warning_zero_preferred_refresh)
- printk(BIOS_ERR,
- "Warning: CVT block does not set preferred refresh rate\n");
- return !conformant;
+ if (nonconformant_extension ||
+ !has_valid_checksum ||
+ !has_valid_cvt ||
+ !has_valid_year ||
+ !has_valid_week ||
+ !has_valid_detailed_blocks ||
+ !has_valid_dummy_block ||
+ !has_valid_extension_count ||
+ !has_valid_descriptor_ordering ||
+ !has_valid_range_descriptor ||
+ !manufacturer_name_well_formed) {
+ conformant = 0;
+ printk(BIOS_ERR, "EDID block does not conform at all!\n");
+ if (nonconformant_extension)
+ printk(BIOS_ERR, "\tHas %d nonconformant extension block(s)\n",
+ nonconformant_extension);
+ if (!has_valid_checksum)
+ printk(BIOS_ERR, "\tBlock has broken checksum\n");
+ if (!has_valid_cvt)
+ printk(BIOS_ERR, "\tBroken 3-byte CVT blocks\n");
+ if (!has_valid_year)
+ printk(BIOS_ERR, "\tBad year of manufacture\n");
+ if (!has_valid_week)
+ printk(BIOS_ERR, "\tBad week of manufacture\n");
+ if (!has_valid_detailed_blocks)
+ printk(BIOS_ERR, "\tDetailed blocks filled with garbage\n");
+ if (!has_valid_dummy_block)
+ printk(BIOS_ERR, "\tDummy block filled with garbage\n");
+ if (!has_valid_extension_count)
+ printk(BIOS_ERR, "\tImpossible extension block count\n");
+ if (!manufacturer_name_well_formed)
+ printk(BIOS_ERR, "\tManufacturer name field contains garbage\n");
+ if (!has_valid_descriptor_ordering)
+ printk(BIOS_ERR, "\tInvalid detailed timing descriptor ordering\n");
+ if (!has_valid_range_descriptor)
+ printk(BIOS_ERR, "\tRange descriptor contains garbage\n");
+ if (!has_valid_max_dotclock)
+ printk(BIOS_ERR, "\tEDID 1.4 block does not set max dotclock\n");
}
+ if (warning_excessive_dotclock_correction)
+ printk(BIOS_ERR,
+ "Warning: CVT block corrects dotclock by more than 9.75MHz\n");
+ if (warning_zero_preferred_refresh)
+ printk(BIOS_ERR,
+ "Warning: CVT block does not set preferred refresh rate\n");
+ return !conformant;
+}
+
/*
* Notes on panel extensions: (TODO, implement me in the code)
*
1
0
New patch to review for coreboot: 4cbf25f arm: Redesign, clarify and clean up cache related code
by Isaac Christensen 29 Sep '14
by Isaac Christensen 29 Sep '14
29 Sep '14
Isaac Christensen (isaac.christensen(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6993
-gerrit
commit 4cbf25f8eca3a12bbfec5b015953c0fc2b69c877
Author: Julius Werner <jwerner(a)chromium.org>
Date: Tue Jan 21 20:11:22 2014 -0800
arm: Redesign, clarify and clean up cache related code
This patch changes several cache-related pieces to be cleaner, faster or
more correct. The largest point is removing the old
arm_invalidate_caches() function and surrounding bootblock code to
initialize SCTLR and replace it with an all-assembly function that takes
care of cache and SCTLR initialization to bring the system to a known
state. It runs without stack and before coreboot makes any write
accesses to be as compatible as possible with whatever state the system
was left in by preceeding code. This also finally fixes the dreaded
icache bug that wasted hundreds of milliseconds during boot.
Old-Change-Id: I7bb4995af8184f6383f8e3b1b870b0662bde8bd4
Signed-off-by: Julius Werner <jwerner(a)chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/183890
(cherry picked from commit 07a35925dc957919bf88dfc90515971a36e81b97)
nyan_big: apply cache-related changes from nyan
This applies the same changes from 07a3592 that were applied to nyan.
Old-Change-Id: Idcbe85436d7a2f65fcd751954012eb5f4bec0b6c
Reviewed-on: https://chromium-review.googlesource.com/184551
Commit-Queue: David Hendricks <dhendrix(a)chromium.org>
Tested-by: David Hendricks <dhendrix(a)chromium.org>
Reviewed-by: David Hendricks <dhendrix(a)chromium.org>
(cherry picked from commit 4af27f02614da41c611aee2c6d175b1b948428ea)
Squashed the followup patch for nyan_big into the original patch.
Change-Id: Id14aef7846355ea2da496e55da227b635aca409e
Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com>
---
payloads/libpayload/arch/arm/cache.c | 78 ++++-----------------------
payloads/libpayload/include/arm/arch/cache.h | 19 +------
payloads/libpayload/include/x86/arch/cache.h | 2 +-
src/arch/arm/armv4/cache.c | 7 +--
src/arch/arm/armv7/bootblock.S | 2 +
src/arch/arm/armv7/bootblock_simple.c | 17 ------
src/arch/arm/armv7/cache.c | 79 ++++------------------------
src/arch/arm/armv7/cpu.S | 31 +++++++++++
src/arch/arm/armv7/mmu.c | 13 +++--
src/arch/arm/include/armv4/arch/cache.h | 7 +--
src/arch/arm/include/armv7/arch/cache.h | 19 +------
src/arch/arm/stages.c | 18 ++-----
src/mainboard/google/daisy/mainboard.c | 1 -
src/mainboard/google/nyan/romstage.c | 23 +++-----
src/mainboard/google/nyan_big/romstage.c | 23 +++-----
src/mainboard/google/peach_pit/mainboard.c | 1 -
src/soc/samsung/exynos5420/wakeup.c | 1 -
17 files changed, 94 insertions(+), 247 deletions(-)
diff --git a/payloads/libpayload/arch/arm/cache.c b/payloads/libpayload/arch/arm/cache.c
index defe640..63715bc 100644
--- a/payloads/libpayload/arch/arm/cache.c
+++ b/payloads/libpayload/arch/arm/cache.c
@@ -38,26 +38,9 @@
void tlb_invalidate_all(void)
{
- /*
- * FIXME: ARMv7 Architecture Ref. Manual claims that the distinction
- * instruction vs. data TLBs is deprecated in ARMv7, however this does
- * not seem to be the case as of Cortex-A15.
- */
+ /* TLBIALL includes dTLB and iTLB on systems that have them. */
tlbiall();
- dtlbiall();
- itlbiall();
- isb();
dsb();
-}
-
-void icache_invalidate_all(void)
-{
- /*
- * icache can be entirely invalidated with one operation.
- * Note: If branch predictors are architecturally-visible, ICIALLU
- * also performs a BPIALL operation (B2-1283 in arch manual)
- */
- iciallu();
isb();
}
@@ -135,6 +118,11 @@ void dcache_invalidate_by_mva(void const *addr, size_t len)
dcache_op_mva(addr, len, OP_DCIMVAC);
}
+/*
+ * CAUTION: This implementation assumes that coreboot never uses non-identity
+ * page tables for pages containing executed code. If you ever want to violate
+ * this assumption, have fun figuring out the associated problems on your own.
+ */
void dcache_mmu_disable(void)
{
uint32_t sctlr;
@@ -150,58 +138,14 @@ void dcache_mmu_enable(void)
uint32_t sctlr;
sctlr = read_sctlr();
- dcache_clean_invalidate_all();
sctlr |= SCTLR_C | SCTLR_M;
write_sctlr(sctlr);
}
-void arm_invalidate_caches(void)
+void cache_sync_instructions(void)
{
- uint32_t clidr;
- int level;
-
- /* Invalidate branch predictor */
- bpiall();
-
- /* Iterate thru each cache identified in CLIDR and invalidate */
- clidr = read_clidr();
- for (level = 0; level < 7; level++) {
- unsigned int ctype = (clidr >> (level * 3)) & 0x7;
- uint32_t csselr;
-
- switch(ctype) {
- case 0x0:
- /* no cache */
- break;
- case 0x1:
- /* icache only */
- csselr = (level << 1) | 1;
- write_csselr(csselr);
- icache_invalidate_all();
- break;
- case 0x2:
- case 0x4:
- /* dcache only or unified cache */
- csselr = level << 1;
- write_csselr(csselr);
- dcache_invalidate_all();
- break;
- case 0x3:
- /* separate icache and dcache */
- csselr = (level << 1) | 1;
- write_csselr(csselr);
- icache_invalidate_all();
-
- csselr = level << 1;
- write_csselr(csselr);
- dcache_invalidate_all();
- break;
- default:
- /* reserved */
- break;
- }
- }
-
- /* Invalidate TLB */
- tlb_invalidate_all();
+ dcache_clean_all(); /* includes trailing DSB (in assembly) */
+ iciallu(); /* includes BPIALLU (architecturally) */
+ dsb();
+ isb();
}
diff --git a/payloads/libpayload/include/arm/arch/cache.h b/payloads/libpayload/include/arm/arch/cache.h
index 5210dfe..470eb55 100644
--- a/payloads/libpayload/include/arm/arch/cache.h
+++ b/payloads/libpayload/include/arm/arch/cache.h
@@ -93,18 +93,6 @@ static inline void isb(void)
* Low-level TLB maintenance operations
*/
-/* invalidate entire data TLB */
-static inline void dtlbiall(void)
-{
- asm volatile ("mcr p15, 0, %0, c8, c6, 0" : : "r" (0) : "memory");
-}
-
-/* invalidate entire instruction TLB */
-static inline void itlbiall(void)
-{
- asm volatile ("mcr p15, 0, %0, c8, c5, 0" : : "r" (0));
-}
-
/* invalidate entire unified TLB */
static inline void tlbiall(void)
{
@@ -313,8 +301,8 @@ void dcache_mmu_disable(void);
/* dcache and MMU enable */
void dcache_mmu_enable(void);
-/* icache invalidate all (on current level given by CSSELR) */
-void icache_invalidate_all(void);
+/* perform all icache/dcache maintenance needed after loading new code */
+void cache_sync_instructions(void);
/* tlb invalidate all */
void tlb_invalidate_all(void);
@@ -323,9 +311,6 @@ void tlb_invalidate_all(void);
* Generalized setup/init functions
*/
-/* invalidate all caches on ARM */
-void arm_invalidate_caches(void);
-
/* mmu initialization (set page table address, set permissions, etc) */
void mmu_init(void);
diff --git a/payloads/libpayload/include/x86/arch/cache.h b/payloads/libpayload/include/x86/arch/cache.h
index 3960488..ffefcdb 100644
--- a/payloads/libpayload/include/x86/arch/cache.h
+++ b/payloads/libpayload/include/x86/arch/cache.h
@@ -41,6 +41,6 @@
#define dcache_invalidate_by_mva(addr, len)
#define dcache_clean_invalidate_all()
#define dcache_clean_invalidate_by_mva(addr, len)
-#define icache_invalidate_all()
+#define cache_sync_instructions()
#endif
diff --git a/src/arch/arm/armv4/cache.c b/src/arch/arm/armv4/cache.c
index e5cf293..140beee 100644
--- a/src/arch/arm/armv4/cache.c
+++ b/src/arch/arm/armv4/cache.c
@@ -39,10 +39,6 @@ void tlb_invalidate_all(void)
{
}
-void icache_invalidate_all(void)
-{
-}
-
void dcache_clean_all(void)
{
}
@@ -82,11 +78,10 @@ void dcache_mmu_disable(void)
{
}
-
void dcache_mmu_enable(void)
{
}
-void arm_invalidate_caches(void)
+void cache_sync_instructions(void)
{
}
diff --git a/src/arch/arm/armv7/bootblock.S b/src/arch/arm/armv7/bootblock.S
index 4258caf..9ed5d54 100644
--- a/src/arch/arm/armv7/bootblock.S
+++ b/src/arch/arm/armv7/bootblock.S
@@ -46,6 +46,8 @@ ENDPROC(_start)
.thumb
ENTRY(_thumb_start)
+ bl arm_init_caches
+
/*
* From Cortex-A Series Programmer's Guide:
* Only CPU 0 performs initialization. Other CPUs go into WFI
diff --git a/src/arch/arm/armv7/bootblock_simple.c b/src/arch/arm/armv7/bootblock_simple.c
index 5cd5970..248ea4e 100644
--- a/src/arch/arm/armv7/bootblock_simple.c
+++ b/src/arch/arm/armv7/bootblock_simple.c
@@ -32,23 +32,6 @@ void main(void)
{
const char *stage_name = "fallback/romstage";
void *entry;
- uint32_t sctlr;
-
- /* Globally disable MMU, caches, and branch prediction (these should
- * be disabled by default on reset) */
- sctlr = read_sctlr();
- sctlr &= ~(SCTLR_M | SCTLR_C | SCTLR_Z | SCTLR_I);
- write_sctlr(sctlr);
-
- arm_invalidate_caches();
-
- /*
- * Re-enable icache and branch prediction. MMU and dcache will be
- * set up later.
- */
- sctlr = read_sctlr();
- sctlr |= SCTLR_Z | SCTLR_I;
- write_sctlr(sctlr);
bootblock_cpu_init();
bootblock_mainboard_init();
diff --git a/src/arch/arm/armv7/cache.c b/src/arch/arm/armv7/cache.c
index 7db86c8..31819f7 100644
--- a/src/arch/arm/armv7/cache.c
+++ b/src/arch/arm/armv7/cache.c
@@ -37,26 +37,9 @@
void tlb_invalidate_all(void)
{
- /*
- * FIXME: ARMv7 Architecture Ref. Manual claims that the distinction
- * instruction vs. data TLBs is deprecated in ARMv7, however this does
- * not seem to be the case as of Cortex-A15.
- */
+ /* TLBIALL includes dTLB and iTLB on systems that have them. */
tlbiall();
- dtlbiall();
- itlbiall();
- isb();
dsb();
-}
-
-void icache_invalidate_all(void)
-{
- /*
- * icache can be entirely invalidated with one operation.
- * Note: If branch predictors are architecturally-visible, ICIALLU
- * also performs a BPIALL operation (B2-1283 in arch manual)
- */
- iciallu();
isb();
}
@@ -133,6 +116,11 @@ void dcache_invalidate_by_mva(void const *addr, size_t len)
dcache_op_mva(addr, len, OP_DCIMVAC);
}
+/*
+ * CAUTION: This implementation assumes that coreboot never uses non-identity
+ * page tables for pages containing executed code. If you ever want to violate
+ * this assumption, have fun figuring out the associated problems on your own.
+ */
void dcache_mmu_disable(void)
{
uint32_t sctlr;
@@ -143,64 +131,19 @@ void dcache_mmu_disable(void)
write_sctlr(sctlr);
}
-
void dcache_mmu_enable(void)
{
uint32_t sctlr;
sctlr = read_sctlr();
- dcache_clean_invalidate_all();
sctlr |= SCTLR_C | SCTLR_M;
write_sctlr(sctlr);
}
-void arm_invalidate_caches(void)
+void cache_sync_instructions(void)
{
- uint32_t clidr;
- int level;
-
- /* Invalidate branch predictor */
- bpiall();
-
- /* Iterate thru each cache identified in CLIDR and invalidate */
- clidr = read_clidr();
- for (level = 0; level < 7; level++) {
- unsigned int ctype = (clidr >> (level * 3)) & 0x7;
- uint32_t csselr;
-
- switch(ctype) {
- case 0x0:
- /* no cache */
- break;
- case 0x1:
- /* icache only */
- csselr = (level << 1) | 1;
- write_csselr(csselr);
- icache_invalidate_all();
- break;
- case 0x2:
- case 0x4:
- /* dcache only or unified cache */
- csselr = level << 1;
- write_csselr(csselr);
- dcache_invalidate_all();
- break;
- case 0x3:
- /* separate icache and dcache */
- csselr = (level << 1) | 1;
- write_csselr(csselr);
- icache_invalidate_all();
-
- csselr = level << 1;
- write_csselr(csselr);
- dcache_invalidate_all();
- break;
- default:
- /* reserved */
- break;
- }
- }
-
- /* Invalidate TLB */
- tlb_invalidate_all();
+ dcache_clean_all(); /* includes trailing DSB (in assembly) */
+ iciallu(); /* includes BPIALLU (architecturally) */
+ dsb();
+ isb();
}
diff --git a/src/arch/arm/armv7/cpu.S b/src/arch/arm/armv7/cpu.S
index 29a19e7..5738116 100644
--- a/src/arch/arm/armv7/cpu.S
+++ b/src/arch/arm/armv7/cpu.S
@@ -104,6 +104,37 @@
bx lr
.endm
+/*
+ * Bring an ARM processor we just gained control of (e.g. from IROM) into a
+ * known state regarding caches/SCTLR. Completely cleans and invalidates
+ * icache/dcache, disables MMU and dcache (if active), and enables unaligned
+ * accesses, icache and branch prediction (if inactive). Clobbers r4 and r5.
+ */
+ENTRY(arm_init_caches)
+ /* r4: SCTLR, return address: r5 (stay valid for the whole function) */
+ mov r5, lr
+ mrc p15, 0, r4, c1, c0, 0
+
+ /* Activate ICache (12) and Branch Prediction (11) already for speed */
+ orr r4, # (1 << 11) | (1 << 12)
+ mcr p15, 0, r4, c1, c0, 0
+
+ /* Flush and invalidate dcache in ascending order */
+ bl dcache_clean_invalidate_all
+
+ /* Deactivate MMU (0), Alignment Check (1) and DCache (2) */
+ and r4, # ~(1 << 0) & ~(1 << 1) & ~(1 << 2)
+ mcr p15, 0, r4, c1, c0, 0
+
+ /* Invalidate icache and TLB for good measure */
+ mcr p15, 0, r0, c7, c5, 0
+ mcr p15, 0, r0, c8, c7, 0
+ dsb
+ isb
+
+ bx r5
+ENDPROC(arm_init_caches)
+
ENTRY(dcache_invalidate_all)
dcache_apply_all crm=c6
ENDPROC(dcache_invalidate_all)
diff --git a/src/arch/arm/armv7/mmu.c b/src/arch/arm/armv7/mmu.c
index cc915a6..d710030 100644
--- a/src/arch/arm/armv7/mmu.c
+++ b/src/arch/arm/armv7/mmu.c
@@ -106,11 +106,18 @@ void mmu_config_range(unsigned long start_mb, unsigned long size_mb,
for (i = start_mb; i < start_mb + size_mb; i++)
writel((i << 20) | attr, &ttb_entry[i]);
- /* Flush the page table entries, and old translations from the TLB. */
- for (i = start_mb; i < start_mb + size_mb; i++) {
+ /* Flush the page table entries from the dcache. */
+ for (i = start_mb; i < start_mb + size_mb; i++)
dccmvac((uintptr_t)&ttb_entry[i]);
+
+ dsb();
+
+ /* Invalidate the TLB entries. */
+ for (i = start_mb; i < start_mb + size_mb; i++)
tlbimvaa(i*MiB);
- }
+
+ dsb();
+ isb();
}
void mmu_init(void)
diff --git a/src/arch/arm/include/armv4/arch/cache.h b/src/arch/arm/include/armv4/arch/cache.h
index 6a3f593..e41ff9a 100644
--- a/src/arch/arm/include/armv4/arch/cache.h
+++ b/src/arch/arm/include/armv4/arch/cache.h
@@ -66,8 +66,8 @@ void dcache_mmu_disable(void);
/* dcache and MMU enable */
void dcache_mmu_enable(void);
-/* icache invalidate all (on current level given by CSSELR) */
-void icache_invalidate_all(void);
+/* perform all icache/dcache maintenance needed after loading new code */
+void cache_sync_instructions(void);
/* tlb invalidate all */
void tlb_invalidate_all(void);
@@ -76,9 +76,6 @@ void tlb_invalidate_all(void);
* Generalized setup/init functions
*/
-/* invalidate all caches on ARM */
-void arm_invalidate_caches(void);
-
/* mmu initialization (set page table address, set permissions, etc) */
void mmu_init(void);
diff --git a/src/arch/arm/include/armv7/arch/cache.h b/src/arch/arm/include/armv7/arch/cache.h
index 5210dfe..470eb55 100644
--- a/src/arch/arm/include/armv7/arch/cache.h
+++ b/src/arch/arm/include/armv7/arch/cache.h
@@ -93,18 +93,6 @@ static inline void isb(void)
* Low-level TLB maintenance operations
*/
-/* invalidate entire data TLB */
-static inline void dtlbiall(void)
-{
- asm volatile ("mcr p15, 0, %0, c8, c6, 0" : : "r" (0) : "memory");
-}
-
-/* invalidate entire instruction TLB */
-static inline void itlbiall(void)
-{
- asm volatile ("mcr p15, 0, %0, c8, c5, 0" : : "r" (0));
-}
-
/* invalidate entire unified TLB */
static inline void tlbiall(void)
{
@@ -313,8 +301,8 @@ void dcache_mmu_disable(void);
/* dcache and MMU enable */
void dcache_mmu_enable(void);
-/* icache invalidate all (on current level given by CSSELR) */
-void icache_invalidate_all(void);
+/* perform all icache/dcache maintenance needed after loading new code */
+void cache_sync_instructions(void);
/* tlb invalidate all */
void tlb_invalidate_all(void);
@@ -323,9 +311,6 @@ void tlb_invalidate_all(void);
* Generalized setup/init functions
*/
-/* invalidate all caches on ARM */
-void arm_invalidate_caches(void);
-
/* mmu initialization (set page table address, set permissions, etc) */
void mmu_init(void);
diff --git a/src/arch/arm/stages.c b/src/arch/arm/stages.c
index 38d1b19..47f13fa 100644
--- a/src/arch/arm/stages.c
+++ b/src/arch/arm/stages.c
@@ -20,12 +20,7 @@
/*
* This file contains entry/exit functions for each stage during coreboot
* execution (bootblock entry and ramstage exit will depend on external
- * loading.
- *
- * Unlike other files, this one should be compiled with a -m option to
- * specify a pre-determined instruction set. This is to ensure consistency
- * in the CPU operating mode (ARM or Thumb) when hand-off between stages
- * occurs.
+ * loading).
*
* Entry points must be placed at the location the previous stage jumps
* to (the lowest address in the stage image). This is done by giving
@@ -49,13 +44,10 @@ void stage_entry(void)
void stage_exit(void *addr)
{
void (*doit)(void) = addr;
- /* make sure any code we installed is written to memory. Not all ARM have
- * unified caches.
- */
- dcache_clean_all();
- /* Because most stages copy code to memory, it's a safe and hygienic thing
- * to flush the icache here.
+ /*
+ * Most stages load code so we need to sync caches here. Should maybe
+ * go into cbfs_load_stage() instead...
*/
- icache_invalidate_all();
+ cache_sync_instructions();
doit();
}
diff --git a/src/mainboard/google/daisy/mainboard.c b/src/mainboard/google/daisy/mainboard.c
index 0adadb6..8a252b1 100644
--- a/src/mainboard/google/daisy/mainboard.c
+++ b/src/mainboard/google/daisy/mainboard.c
@@ -334,7 +334,6 @@ static void mainboard_enable(device_t dev)
mmu_config_range(DRAM_START, DRAM_SIZE, DCACHE_WRITEBACK);
mmu_config_range(DMA_START >> 20, DMA_SIZE >> 20, DCACHE_OFF);
mmu_config_range(DRAM_END, 4096 - DRAM_END, DCACHE_OFF);
- dcache_invalidate_all();
dcache_mmu_enable();
const unsigned epll_hz = 192000000;
diff --git a/src/mainboard/google/nyan/romstage.c b/src/mainboard/google/nyan/romstage.c
index ea40388..8d8e6a9 100644
--- a/src/mainboard/google/nyan/romstage.c
+++ b/src/mainboard/google/nyan/romstage.c
@@ -72,25 +72,12 @@ static void configure_l2actlr(void)
write_l2actlr(val);
}
-void main(void)
+static void __attribute__((noinline)) romstage(void)
{
#if CONFIG_COLLECT_TIMESTAMPS
uint64_t romstage_start_time = timestamp_get();
#endif
- // Globally disable MMU, caches and branch prediction (these should
- // already be disabled by default on reset).
- uint32_t sctlr = read_sctlr();
- sctlr &= ~(SCTLR_M | SCTLR_C | SCTLR_Z | SCTLR_I);
- write_sctlr(sctlr);
-
- arm_invalidate_caches();
-
- // Renable icache and branch prediction.
- sctlr = read_sctlr();
- sctlr |= SCTLR_Z | SCTLR_I;
- write_sctlr(sctlr);
-
configure_l2ctlr();
configure_l2actlr();
@@ -104,7 +91,6 @@ void main(void)
CONFIG_DRAM_DMA_SIZE >> 20, DCACHE_OFF);
mmu_config_range(DRAM_END, 4096 - DRAM_END, DCACHE_OFF);
mmu_disable_range(0, 1);
- dcache_invalidate_all();
dcache_mmu_enable();
/* For quality of the user experience, it's important to get
@@ -140,3 +126,10 @@ void main(void)
#endif
stage_exit(entry);
}
+
+/* Stub to force arm_init_caches to the top, before any stack/memory accesses */
+void main(void)
+{
+ asm ("bl arm_init_caches" ::: "r0","r1","r2","r3","r4","r5","ip");
+ romstage();
+}
diff --git a/src/mainboard/google/nyan_big/romstage.c b/src/mainboard/google/nyan_big/romstage.c
index 0e71020..c013d11 100644
--- a/src/mainboard/google/nyan_big/romstage.c
+++ b/src/mainboard/google/nyan_big/romstage.c
@@ -72,25 +72,12 @@ static void configure_l2actlr(void)
write_l2actlr(val);
}
-void main(void)
+static void __attribute__((noinline)) romstage(void)
{
#if CONFIG_COLLECT_TIMESTAMPS
uint64_t romstage_start_time = timestamp_get();
#endif
- // Globally disable MMU, caches and branch prediction (these should
- // already be disabled by default on reset).
- uint32_t sctlr = read_sctlr();
- sctlr &= ~(SCTLR_M | SCTLR_C | SCTLR_Z | SCTLR_I);
- write_sctlr(sctlr);
-
- arm_invalidate_caches();
-
- // Renable icache and branch prediction.
- sctlr = read_sctlr();
- sctlr |= SCTLR_Z | SCTLR_I;
- write_sctlr(sctlr);
-
configure_l2ctlr();
configure_l2actlr();
@@ -104,7 +91,6 @@ void main(void)
CONFIG_DRAM_DMA_SIZE >> 20, DCACHE_OFF);
mmu_config_range(DRAM_END, 4096 - DRAM_END, DCACHE_OFF);
mmu_disable_range(0, 1);
- dcache_invalidate_all();
dcache_mmu_enable();
/* For quality of the user experience, it's important to get
@@ -140,3 +126,10 @@ void main(void)
#endif
stage_exit(entry);
}
+
+/* Stub to force arm_init_caches to the top, before any stack/memory accesses */
+void main(void)
+{
+ asm ("bl arm_init_caches" ::: "r0","r1","r2","r3","r4","r5","ip");
+ romstage();
+}
diff --git a/src/mainboard/google/peach_pit/mainboard.c b/src/mainboard/google/peach_pit/mainboard.c
index 1fb441d..706447a 100644
--- a/src/mainboard/google/peach_pit/mainboard.c
+++ b/src/mainboard/google/peach_pit/mainboard.c
@@ -469,7 +469,6 @@ static void mainboard_enable(device_t dev)
/* set up caching for the DRAM */
mmu_config_range(DRAM_START, DRAM_SIZE, DCACHE_WRITEBACK);
mmu_config_range(DMA_START >> 20, DMA_SIZE >> 20, DCACHE_OFF);
- tlb_invalidate_all();
const unsigned epll_hz = 192000000;
const unsigned sample_rate = 48000;
diff --git a/src/soc/samsung/exynos5420/wakeup.c b/src/soc/samsung/exynos5420/wakeup.c
index 753afd9..a240717 100644
--- a/src/soc/samsung/exynos5420/wakeup.c
+++ b/src/soc/samsung/exynos5420/wakeup.c
@@ -29,7 +29,6 @@ void wakeup(void)
power_init(); /* Ensure ps_hold_setup() for early wakeup. */
dcache_mmu_disable();
- icache_invalidate_all();
power_exit_wakeup();
/* Should never return. If we do, reset. */
power_reset();
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