coreboot-gerrit September 2014

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Patch set updated for coreboot: 1ebdc51 arm: Thumb ALL the things!
by Isaac Christensen 29 Sep '14

29 Sep '14

Isaac Christensen (isaac.christensen(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6930 -gerrit commit 1ebdc517093face074f428dd07346f2e38d06491 Author: Julius Werner <jwerner(a)chromium.org> Date: Mon Jan 13 13:24:30 2014 -0800 arm: Thumb ALL the things! This patch switches every last part of Coreboot on ARM over to Thumb mode: libpayload, the internal libgcc, and assorted assembly files. In combination with the respective depthcharge patch, this will switch to Thumb mode right after the entry point of the bootblock and not switch back to ARM until the final assembly stub that jumps to the kernel. The required changes to make this work include some new headers and Makefile flags to handle assembly files (using the unified syntax and the same helper macros as Linux), modifying our custom-written libgcc code for 64-bit division to support Thumb (removing some stale old files that were never really used for clarity), and flipping the general CFLAGS to Thumb (some more cleanup there as well while I'm at it). Change-Id: I80c04281e3adbf74f9f477486a96b9fafeb455b3 Signed-off-by: Julius Werner <jwerner(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/182212 Reviewed-by: Gabe Black <gabeblack(a)chromium.org> (cherry picked from commit 5f65c17cbfae165a95354146ae79e06c512c2c5a) Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com> --- payloads/libpayload/arch/arm/Makefile.inc | 7 ++++++- payloads/libpayload/include/arm/arch/asm.h | 19 +++++++++++++------ src/arch/arm/Makefile.inc | 8 ++++---- src/arch/arm/armv7/Makefile.inc | 10 ++++++---- src/arch/arm/armv7/bootblock.S | 23 ++++++++++------------- src/arch/arm/include/arch/asm.h | 19 +++++++++++++------ src/soc/nvidia/tegra124/maincpu.S | 10 +++++----- 7 files changed, 57 insertions(+), 39 deletions(-) diff --git a/payloads/libpayload/arch/arm/Makefile.inc b/payloads/libpayload/arch/arm/Makefile.inc index 0078ffe..2f8da15 100644 --- a/payloads/libpayload/arch/arm/Makefile.inc +++ b/payloads/libpayload/arch/arm/Makefile.inc @@ -27,7 +27,8 @@ ## SUCH DAMAGE. ## -CFLAGS += -mfloat-abi=hard -marm -mabi=aapcs-linux -march=armv7-a +CFLAGS += -mthumb -march=armv7-a +arm_asm_flags = -Wa,-mthumb -Wa,-mimplicit-it=always -Wa,-mno-warn-deprecated head.o-y += head.S libc-y += main.c sysinfo.c @@ -37,3 +38,7 @@ libc-y += memcpy.S memset.S memmove.S libc-y += exception_asm.S exception.c libc-y += cache.c cpu.S libcbfs-$(CONFIG_LP_CBFS) += dummy_media.c + +# Add other classes here when you put assembly files into them! +head.o-S-ccopts += $(arm_asm_flags) +libc-S-ccopts += $(arm_asm_flags) diff --git a/payloads/libpayload/include/arm/arch/asm.h b/payloads/libpayload/include/arm/arch/asm.h index 2f88599..9e9e7ce 100644 --- a/payloads/libpayload/include/arm/arch/asm.h +++ b/payloads/libpayload/include/arm/arch/asm.h @@ -20,16 +20,17 @@ #ifndef __ARM_ASM_H #define __ARM_ASM_H -#if defined __arm__ -# define ARM(x...) x -# define THUMB(x...) -# define W(instr) instr -#elif defined __thumb__ +/* __arm__ is defined regardless of Thumb mode, so need to order this right */ +#if defined __thumb2__ # define ARM(x...) # define THUMB(x...) x # define W(instr) instr.w +#elif defined __thumb__ +# error You are not compiling Thumb2, this won't work! #else -# error Not in ARM or thumb mode! +# define ARM(x...) x +# define THUMB(x...) +# define W(instr) instr #endif #define ALIGN .align 0 @@ -46,4 +47,10 @@ #define END(name) \ .size name, .-name +/* Everything should go into the text section by default. */ + .text + +/* Thumb code uses the (new) unified assembly syntax. */ +THUMB( .syntax unified ) + #endif /* __ARM_ASM_H */ diff --git a/src/arch/arm/Makefile.inc b/src/arch/arm/Makefile.inc index 427e3a4..f10e371 100644 --- a/src/arch/arm/Makefile.inc +++ b/src/arch/arm/Makefile.inc @@ -2,7 +2,7 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2012 The ChromiumOS Authors +## Copyright (C) 2012-2013 The ChromiumOS Authors ## Copyright (C) 2012 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> ## Copyright (C) 2009-2010 coresystems GmbH ## Copyright (C) 2009 Ronald G. Minnich @@ -64,7 +64,7 @@ $(objcbfs)/bootblock.debug: $(src)/arch/arm/bootblock.ld $(obj)/ldoptions $$(boo ifeq ($(CONFIG_COMPILER_LLVM_CLANG),y) $(LD_bootblock) -m armelf_linux_eabi --gc-sections -static -o $@ -L$(obj) $< -T $(src)/arch/arm/bootblock.ld else - $(CC_bootblock) $(CFLAGS_bootblock) -nostartfiles -Wl,--gc-sections -static -o $@ -L$(obj) -T $(src)/arch/arm/bootblock.ld -Wl,--start-group $(bootblock-objs) $(LIBGCC_FILE_NAME_bootblock) -Wl,--end-group + $(CC_bootblock) $(CFLAGS_bootblock) -nostdlib -Wl,--gc-sections -static -o $@ -L$(obj) -T $(src)/arch/arm/bootblock.ld -Wl,--start-group $(bootblock-objs) $(LIBGCC_FILE_NAME_bootblock) -Wl,--end-group endif endif # CONFIG_ARCH_BOOTBLOCK_ARM @@ -87,9 +87,9 @@ VBOOT_STUB_DEPS += $(obj)/arch/arm/eabi_compat.rmodules_arm.o $(objcbfs)/romstage.debug: $$(romstage-objs) $(src)/arch/arm/romstage.ld $(obj)/ldoptions @printf " LINK $(subst $(obj)/,,$(@))\n" ifeq ($(CONFIG_COMPILER_LLVM_CLANG),y) - $(LD_romstage) -nostdlib -nostartfiles --gc-sections -static -o $@ -L$(obj) $(romstage-objs) -T $(src)/arch/arm/romstage.ld + $(LD_romstage) -nostdlib -nostdlib --gc-sections -static -o $@ -L$(obj) $(romstage-objs) -T $(src)/arch/arm/romstage.ld else - $(CC_romstage) $(CFLAGS_romstage) -nostartfiles -Wl,--gc-sections -static -o $@ -L$(obj) -T $(src)/arch/arm/romstage.ld -Wl,--start-group $(romstage-objs) $(LIBGCC_FILE_NAME_romstage) -Wl,--end-group + $(CC_romstage) $(CFLAGS_romstage) -nostdlib -Wl,--gc-sections -static -o $@ -L$(obj) -T $(src)/arch/arm/romstage.ld -Wl,--start-group $(romstage-objs) $(LIBGCC_FILE_NAME_romstage) -Wl,--end-group endif endif # CONFIG_ARCH_ROMSTAGE_ARM diff --git a/src/arch/arm/armv7/Makefile.inc b/src/arch/arm/armv7/Makefile.inc index c46fb39..b03879a 100644 --- a/src/arch/arm/armv7/Makefile.inc +++ b/src/arch/arm/armv7/Makefile.inc @@ -19,8 +19,10 @@ ## ############################################################################### -armv7_flags = -march=armv7-a -mthumb -mthumb-interwork \ +armv7_flags = -march=armv7-a -mthumb \ -I$(src)/arch/arm/include/armv7/ -D__COREBOOT_ARM_ARCH__=7 +armv7_asm_flags = $(armv7_flags) -Wa,-mthumb -Wa,-mimplicit-it=always \ + -Wa,-mno-warn-deprecated ############################################################################### # bootblock @@ -40,7 +42,7 @@ bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += exception_asm.S bootblock-y += mmu.c CFLAGS_bootblock += $(armv7_flags) -CPPFLAGS_bootblock += $(armv7_flags) +CPPFLAGS_bootblock += $(armv7_asm_flags) endif # CONFIG_ARCH_BOOTBLOCK_ARMV7 @@ -57,7 +59,7 @@ romstage-y += exception_asm.S romstage-y += mmu.c CFLAGS_romstage += $(armv7_flags) -CPPFLAGS_romstage += $(armv7_flags) +CPPFLAGS_romstage += $(armv7_asm_flags) endif # CONFIG_ARCH_ROMSTAGE_ARMV7 @@ -74,6 +76,6 @@ ramstage-y += exception_asm.S ramstage-y += mmu.c CFLAGS_ramstage += $(armv7_flags) -CPPFLAGS_ramstage += $(armv7_flags) +CPPFLAGS_ramstage += $(armv7_asm_flags) endif # CONFIG_ARCH_RAMSTAGE_ARMV7 diff --git a/src/arch/arm/armv7/bootblock.S b/src/arch/arm/armv7/bootblock.S index a8d0973..4258caf 100644 --- a/src/arch/arm/armv7/bootblock.S +++ b/src/arch/arm/armv7/bootblock.S @@ -32,6 +32,7 @@ #include <arch/asm.h> .section ".start", "a", %progbits +.arm ENTRY(_start) /* * Set the cpu to System mode with IRQ and FIQ disabled. Prefetch/Data @@ -40,7 +41,11 @@ ENTRY(_start) * causes it. */ msr cpsr_cxf, #0xdf + bl _thumb_start +ENDPROC(_start) +.thumb +ENTRY(_thumb_start) /* * From Cortex-A Series Programmer's Guide: * Only CPU 0 performs initialization. Other CPUs go into WFI @@ -72,25 +77,17 @@ call_bootblock: ldr sp, .Stack /* Set up stack pointer */ ldr r0,=0x00000000 /* - * The current design of cpu_info places the - * struct at the top of the stack. The number of - * words pushed must be at least as large as that - * struct. + * The current design of cpu_info places the struct at the top of the + * stack. Free enough space to accomodate for that, but make sure it's + * 8-byte aligned for ABI compliance. */ - push {r0-r2} - bic sp, sp, #7 /* 8-byte alignment for ABI compliance */ - /* - * Use "bl" instead of "b" even though we do not intend to return. - * "bl" gets compiled to "blx" if we're transitioning from ARM to - * Thumb. However, "b" will not and GCC may attempt to create a - * wrapper which is currently broken. - */ + sub sp, sp, #16 bl main wait_for_interrupt: wfi mov pc, lr @ back to my caller -ENDPROC(_start) +ENDPROC(_thumb_start) /* we do it this way because it's a 32-bit constant and * in some cases too far away to be loaded as just an offset diff --git a/src/arch/arm/include/arch/asm.h b/src/arch/arm/include/arch/asm.h index 5f3e55f..a57ce4d 100644 --- a/src/arch/arm/include/arch/asm.h +++ b/src/arch/arm/include/arch/asm.h @@ -20,19 +20,20 @@ #ifndef __ARM_ASM_H #define __ARM_ASM_H -#if defined __arm__ -# define ARM(x...) x -# define THUMB(x...) -# define W(instr) instr -#elif defined __thumb__ +/* __arm__ is defined regardless of Thumb mode, so need to order this right */ +#if defined __thumb2__ # define ARM(x...) # define THUMB(x...) x # define W(instr) instr.w # if __COREBOOT_ARM_ARCH__ < 7 # error thumb mode has not been tested with ARM < v7! # endif +#elif defined __thumb__ +# error You are not compiling Thumb2, this won't work! #else -# error Not in ARM or thumb mode! +# define ARM(x...) x +# define THUMB(x...) +# define W(instr) instr #endif #define ALIGN .align 0 @@ -49,4 +50,10 @@ #define END(name) \ .size name, .-name +/* Everything should go into the text section by default. */ + .text + +/* Thumb code uses the (new) unified assembly syntax. */ +THUMB( .syntax unified ) + #endif /* __ARM_ASM_H */ diff --git a/src/soc/nvidia/tegra124/maincpu.S b/src/soc/nvidia/tegra124/maincpu.S index 7b217d8..91981ac 100644 --- a/src/soc/nvidia/tegra124/maincpu.S +++ b/src/soc/nvidia/tegra124/maincpu.S @@ -27,8 +27,9 @@ * SUCH DAMAGE. */ +#include <arch/asm.h> + .align 2 - .arm .global maincpu_stack_pointer maincpu_stack_pointer: @@ -38,10 +39,8 @@ maincpu_stack_pointer: maincpu_entry_point: .word 0 - .global maincpu_setup - .type maincpu_setup, function - maincpu_setup: - +.arm +ENTRY(maincpu_setup) /* * Set the cpu to System mode with IRQ and FIQ disabled. Prefetch/Data * aborts may happen early and crash before the abort handlers are @@ -54,3 +53,4 @@ maincpu_entry_point: eor lr, lr ldr r0, maincpu_entry_point bx r0 +ENDPROC(maincpu_setup)

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New patch to review for coreboot: cad6c37 intel/i945: Another magic number
by Patrick Georgi 29 Sep '14

29 Sep '14

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6992 -gerrit commit cad6c37f7fb4732ea2700b7505f407c1d1c307d1 Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Mon Sep 29 20:42:33 2014 +0200 intel/i945: Another magic number Replace it with the existing #define Change-Id: I6e67ed1a455cd4f9eeed1865b9ef981e7ef0a874 Found-by: Idwer Vollering Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> --- src/northbridge/intel/i945/early_init.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c index a134683..24054bd 100644 --- a/src/northbridge/intel/i945/early_init.c +++ b/src/northbridge/intel/i945/early_init.c @@ -757,7 +757,7 @@ static void i945_setup_pci_express_x16(void) /* Set voltage specific parameters */ reg32 = pci_read_config32(PCI_DEV(0, 0x01, 0), 0xe80); reg32 &= (0xf << 4); /* Default case 1.05V */ - if ((MCHBAR32(0xe08) & (1 << 20)) == 0) { /* 1.50V */ + if ((MCHBAR32(DFT_STRAP1) & (1 << 20)) == 0) { /* 1.50V */ reg32 |= (7 << 4); } pci_write_config32(PCI_DEV(0, 0x01, 0), 0xe80, reg32);

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New patch to review for coreboot: 4a0e421 various AMD boards: fix buffer overflow
by Patrick Georgi 29 Sep '14

29 Sep '14

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6991 -gerrit commit 4a0e421ea8a5ca5e71524392448e4774f15cb9ee Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Mon Sep 29 20:23:29 2014 +0200 various AMD boards: fix buffer overflow "AMD\t " isn't 8 characters long. Change-Id: I47b2a39d7dca0201b7ee5dfd1f77e0714411257c Found-by: Coverity Scan Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> --- src/mainboard/gizmosphere/gizmo/mptable.c | 2 +- src/mainboard/lippert/frontrunner-af/mptable.c | 2 +- src/mainboard/lippert/toucan-af/mptable.c | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/src/mainboard/gizmosphere/gizmo/mptable.c b/src/mainboard/gizmosphere/gizmo/mptable.c index ed52722..b98598a 100755 --- a/src/mainboard/gizmosphere/gizmo/mptable.c +++ b/src/mainboard/gizmosphere/gizmo/mptable.c @@ -56,7 +56,7 @@ static void *smp_write_config_table(void *v) mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); mptable_init(mc, LOCAL_APIC_ADDR); - memcpy(mc->mpc_oem, "AMD ", 8); + memcpy(mc->mpc_oem, "AMD ", 8); smp_write_processors(mc); diff --git a/src/mainboard/lippert/frontrunner-af/mptable.c b/src/mainboard/lippert/frontrunner-af/mptable.c index de573b8..078601e 100644 --- a/src/mainboard/lippert/frontrunner-af/mptable.c +++ b/src/mainboard/lippert/frontrunner-af/mptable.c @@ -54,7 +54,7 @@ static void *smp_write_config_table(void *v) mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); mptable_init(mc, LOCAL_APIC_ADDR); - memcpy(mc->mpc_oem, "AMD ", 8); + memcpy(mc->mpc_oem, "AMD ", 8); smp_write_processors(mc); diff --git a/src/mainboard/lippert/toucan-af/mptable.c b/src/mainboard/lippert/toucan-af/mptable.c index de573b8..078601e 100644 --- a/src/mainboard/lippert/toucan-af/mptable.c +++ b/src/mainboard/lippert/toucan-af/mptable.c @@ -54,7 +54,7 @@ static void *smp_write_config_table(void *v) mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); mptable_init(mc, LOCAL_APIC_ADDR); - memcpy(mc->mpc_oem, "AMD ", 8); + memcpy(mc->mpc_oem, "AMD ", 8); smp_write_processors(mc);

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New patch to review for coreboot: aa529ba intel/i945: Fix "always false" statement
by Patrick Georgi 29 Sep '14

29 Sep '14

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6990 -gerrit commit aa529ba9926d645087de96543816d3d3db0b3cb8 Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Mon Sep 29 19:51:21 2014 +0200 intel/i945: Fix "always false" statement Also replace magic number with already existing #define Change-Id: I64d22aca185bf43ff0ac126584b41920182a1112 Found-by: Coverity Scan Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> --- src/northbridge/intel/i945/early_init.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c index 08ce10b..a134683 100644 --- a/src/northbridge/intel/i945/early_init.c +++ b/src/northbridge/intel/i945/early_init.c @@ -502,7 +502,7 @@ static void i945_setup_dmi_rcrb(void) DMIBAR32(0x338) = DMIBAR32(0x334); DMIBAR32(0x338) = DMIBAR32(0x338); - if (i945_silicon_revision() == 1 && ((MCHBAR8(0xe08) & (1 << 5)) == 1)) { + if (i945_silicon_revision() == 1 && (MCHBAR8(DFT_STRAP1) & (1 << 5))) { if ((MCHBAR32(0x214) & 0xf) != 0x3) { printk(BIOS_INFO, "DMI link requires A1 stepping workaround. Rebooting.\n"); reg32 = DMIBAR32(0x224);

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New patch to review for coreboot: 4eb2112 intel/i82801bx: Minor log fixes in IDE driver
by Patrick Georgi 29 Sep '14

29 Sep '14

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6989 -gerrit commit 4eb2112dae97f563345cb94cb004e3de643020cd Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Mon Sep 29 19:40:51 2014 +0200 intel/i82801bx: Minor log fixes in IDE driver Two issues: 1. without config, there were two NULL derefs 2. output for "Secondary" looked at ide0_enable Change-Id: I34ddbc0f9b27226981ccbc237e3d59e522076d55 Found-by: Coverity Scan Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> --- src/southbridge/intel/i82801bx/ide.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/southbridge/intel/i82801bx/ide.c b/src/southbridge/intel/i82801bx/ide.c index e24e693..7ce18f1 100644 --- a/src/southbridge/intel/i82801bx/ide.c +++ b/src/southbridge/intel/i82801bx/ide.c @@ -39,7 +39,7 @@ static void ide_init(struct device *dev) if (!conf || conf->ide0_enable) reg16 |= IDE_DECODE_ENABLE; printk(BIOS_DEBUG, "IDE: %s IDE interface: %s\n", "Primary", - conf->ide0_enable ? "on" : "off"); + (reg16 & IDE_DECODE_ENABLE) ? "on" : "off"); pci_write_config16(dev, IDE_TIM_PRI, reg16); reg16 = pci_read_config16(dev, IDE_TIM_SEC); @@ -47,7 +47,7 @@ static void ide_init(struct device *dev) if (!conf || conf->ide1_enable) reg16 |= IDE_DECODE_ENABLE; printk(BIOS_DEBUG, "IDE: %s IDE interface: %s\n", "Secondary", - conf->ide0_enable ? "on" : "off"); + (reg16 & IDE_DECODE_ENABLE) ? "on" : "off"); pci_write_config16(dev, IDE_TIM_SEC, reg16); }

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Patch merged into coreboot/master: 0e8e099 google/panther: add board_info.txt
by gerrit＠coreboot.org 29 Sep '14

29 Sep '14

the following patch was just integrated into master: commit 0e8e0991e2897b61cf7b3c49ab04826f1b7d7ee4 Author: Matt DeVillier <matt.devillier(a)gmail.com> Date: Thu Sep 11 12:06:19 2014 -0500 google/panther: add board_info.txt Change-Id: Iec0397a981c31c8af3def04b8c170884f79a50cc Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> Reviewed-on: http://review.coreboot.org/6871 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> See http://review.coreboot.org/6871 for details. -gerrit

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Patch merged into coreboot/master: f9f53eb intel/minnowmax: Enable S3 suspend/resume
by gerrit＠coreboot.org 29 Sep '14

29 Sep '14

the following patch was just integrated into master: commit f9f53eb72f37b71f2dad62157dd43ea31e392a17 Author: Mohan D'Costa <mohan(a)ndr.co.jp> Date: Thu Sep 25 18:17:08 2014 +0900 intel/minnowmax: Enable S3 suspend/resume This enables S3 Suspend / Resume support for MinnowMax board using Intel's Bay Trail FSP Tested resume from Power Button and Magic Packet. Change-Id: I021122a68c05f2e725cabb8f3946249afe802bbe Signed-off-by: Mohan D'Costa <mohan(a)ndr.co.jp> Reviewed-on: http://review.coreboot.org/6972 Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Martin Roth <gaumless(a)gmail.com> Tested-by: build bot (Jenkins) See http://review.coreboot.org/6972 for details. -gerrit

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Patch merged into coreboot/master: ed0c838 intel/fsp_baytrail: Add S3 suspend/resume Support
by gerrit＠coreboot.org 29 Sep '14

29 Sep '14

the following patch was just integrated into master: commit ed0c83877f453b94a5e68bef62d6dbba1b97f0d2 Author: Mohan D'Costa <mohan(a)ndr.co.jp> Date: Thu Sep 18 15:57:06 2014 +0900 intel/fsp_baytrail: Add S3 suspend/resume Support This adds S3 Suspend / Resume support to Intel's Bay Trail FSP It is based on the "src/soc/intel/baytrail/romstage/romstage.c" implementation. Change-Id: If0011068eb7290d1b764c5c4b12c17375fb69008 Signed-off-by: Mohan D'Costa <mohan(a)ndr.co.jp> Reviewed-on: http://review.coreboot.org/6937 Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Martin Roth <gaumless(a)gmail.com> Tested-by: build bot (Jenkins) See http://review.coreboot.org/6937 for details. -gerrit

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Patch merged into coreboot/master: bdae9be spi: Add support for Winbond W25Q128FW
by gerrit＠coreboot.org 29 Sep '14

29 Sep '14

the following patch was just integrated into master: commit bdae9bedcdf5650abee089564c47ecbf2ba70f79 Author: Mohan D'Costa <mohan(a)ndr.co.jp> Date: Thu Sep 25 14:40:44 2014 +0900 spi: Add support for Winbond W25Q128FW The W25Q128FW spi part is programatically equivalent to the other W25Q128 parts except it operates at 1.8V. Just add a new entry with the appropriate ID. Tested on a modified MinnowMax Board. Change-Id: Id6a426418a7f785a9d959b02a9e3d2ffc421804f Signed-off-by: Mohan D'Costa <mohan(a)ndr.co.jp> Reviewed-on: http://review.coreboot.org/6971 Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Martin Roth <gaumless(a)gmail.com> Tested-by: build bot (Jenkins) See http://review.coreboot.org/6971 for details. -gerrit

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Patch merged into coreboot/master: 02b5a74 asrock/imb-a180/BiosCallOuts.c: Fix typo in temperatu*re* in comment
by gerrit＠coreboot.org 29 Sep '14

29 Sep '14

the following patch was just integrated into master: commit 02b5a74d6cf7f0b5132b13363847098414eea9cf Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Sat Aug 16 07:31:19 2014 +0200 asrock/imb-a180/BiosCallOuts.c: Fix typo in temperatu*re* in comment Change-Id: If50685505143ccbd51098e92de72545c71b24892 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-on: http://review.coreboot.org/6684 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick(a)georgi-clan.de> See http://review.coreboot.org/6684 for details. -gerrit

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coreboot-gerrit September 2014