coreboot-gerrit September 2014

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New patch to review for coreboot: 541307b broadwell: ACPI, romstage, and other updates
by Isaac Christensen 26 Sep '14

26 Sep '14

Isaac Christensen (isaac.christensen(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6982 -gerrit commit 541307b63de66954851af9c29cbd4a35d879bf69 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Mon May 5 12:42:35 2014 -0500 broadwell: ACPI, romstage, and other updates broadwell: Add romstage usbdebug support Reviewed-on: https://chromium-review.googlesource.com/199412 (cherry picked from commit 1050e7d3be6ec1e4fe5aa2df408f4bb6d33a42b5) broadwell: Add romstage code to configure PCH UART for console Reviewed-on: https://chromium-review.googlesource.com/199807 (cherry picked from commit ecebda4eb5d6fe58473d25c2898ba1a2eac0f39a) broadwell: Expand the PCI device convenience macros Reviewed-on: https://chromium-review.googlesource.com/199891 (cherry picked from commit f8c54c70f136cd2cb8f977bc25661974d7e529ad) broadwell: Add ramstage driver for ADSP Reviewed-on: https://chromium-review.googlesource.com/199892 (cherry picked from commit e8e986b0ba52bbfc9923d71009fbd31e749ca43f) broadwell: Update ACPI devices Reviewed-on: https://chromium-review.googlesource.com/201080 (cherry picked from commit 2446b35578eb36e0009415bec340059135751549) broadwell: Reserve DPR region Reviewed-on: https://chromium-review.googlesource.com/201081 (cherry picked from commit 8ecd9d2096db2bded6f27ef6ee9a9b39ce2dfec6) broadwell: Remove old pei_data and add cpu function for romstage Reviewed-on: https://chromium-review.googlesource.com/201690 (cherry picked from commit d206c9cdd69519d502a90bb0595f0e3a7cb50274) broadwell: Fixes for graphics without executing VBIOS Reviewed-on: https://chromium-review.googlesource.com/202356 (cherry picked from commit 0c031df1ce92c875e95ddfd3f026f649c342c7fa) broadwell: Fix compilation failure when loglevel is lowered Reviewed-on: https://chromium-review.googlesource.com/202357 (cherry picked from commit 708ce78b2bfae5664b1238e17b086c88cac55bdc) broadwell: Disable GPIO controller interrupt Reviewed-on: https://chromium-review.googlesource.com/203645 (cherry picked from commit 2d17e98eded5958258ba5c0abf600284d8d03af9) broadwell: Add support for E0 stepping Reviewed-on: https://chromium-review.googlesource.com/205160 (cherry picked from commit 802e9d371418cc7a7fc7af131d7e5dda0ae5b273) broadwell: misc updates for CPU driver Reviewed-on: https://chromium-review.googlesource.com/205161 (cherry picked from commit ea1d403817ee193648f2c119fd45894e32e57e97) broadwell: Read power state earlier and store in romstage params Reviewed-on: https://chromium-review.googlesource.com/208151 (cherry picked from commit b2198d71084ad3c1360a0bfedc46c8dd3825bd0e) broadwell: Add parameters to pei_data structure Reviewed-on: https://chromium-review.googlesource.com/208153 (cherry picked from commit 423fbf67e497a907fbc8e12caf2929d4951858af) broadwell: Move platform report output after power state is read Reviewed-on: https://chromium-review.googlesource.com/208213 (cherry picked from commit acedf4146bf9377133433046dae1fa9c8bc69d78) Squashed 15 commits for broadwell support. Change-Id: I87e320d3d5376b84dd9c146b0b833e5ce53244aa Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com> --- src/soc/intel/broadwell/Kconfig | 18 ++ src/soc/intel/broadwell/Makefile.inc | 7 + src/soc/intel/broadwell/acpi.c | 5 - src/soc/intel/broadwell/acpi/adsp.asl | 63 +++++++ src/soc/intel/broadwell/acpi/device_nvs.asl | 3 + src/soc/intel/broadwell/acpi/gpio.asl | 17 +- src/soc/intel/broadwell/acpi/lpc.asl | 4 +- src/soc/intel/broadwell/acpi/pch.asl | 18 ++ src/soc/intel/broadwell/acpi/serialio.asl | 209 ++++++++++++++++++--- src/soc/intel/broadwell/adsp.c | 152 +++++++++++++++ src/soc/intel/broadwell/broadwell/adsp.h | 56 ++++++ src/soc/intel/broadwell/broadwell/cpu.h | 1 + src/soc/intel/broadwell/broadwell/device_nvs.h | 7 +- src/soc/intel/broadwell/broadwell/pci_devs.h | 92 ++++++--- src/soc/intel/broadwell/broadwell/pei_data.h | 7 +- src/soc/intel/broadwell/broadwell/romstage.h | 4 + src/soc/intel/broadwell/broadwell/systemagent.h | 4 + src/soc/intel/broadwell/cpu.c | 4 +- src/soc/intel/broadwell/ehci.c | 10 + src/soc/intel/broadwell/hda.c | 25 +++ src/soc/intel/broadwell/igd.c | 13 ++ src/soc/intel/broadwell/me_status.c | 3 + src/soc/intel/broadwell/memmap.c | 15 +- src/soc/intel/broadwell/pch.c | 71 +++---- src/soc/intel/broadwell/pei_data.h | 115 ------------ src/soc/intel/broadwell/romstage/Makefile.inc | 1 + src/soc/intel/broadwell/romstage/cpu.c | 6 + src/soc/intel/broadwell/romstage/raminit.c | 14 ++ src/soc/intel/broadwell/romstage/report_platform.c | 1 + src/soc/intel/broadwell/romstage/romstage.c | 15 +- src/soc/intel/broadwell/romstage/uart.c | 85 +++++++++ src/soc/intel/broadwell/serialio.c | 52 +++-- src/soc/intel/broadwell/systemagent.c | 22 ++- src/soc/intel/broadwell/usbdebug.c | 51 +++++ 34 files changed, 930 insertions(+), 240 deletions(-) diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig index 47b3116..e482ead 100644 --- a/src/soc/intel/broadwell/Kconfig +++ b/src/soc/intel/broadwell/Kconfig @@ -11,6 +11,7 @@ config CPU_SPECIFIC_OPTIONS select ARCH_ROMSTAGE_X86_32 select ARCH_RAMSTAGE_X86_32 select ALT_CBFS_LOAD_PAYLOAD + select ALWAYS_LOAD_OPROM select BACKUP_DEFAULT_SMM_REGION select CACHE_MRC_BIN select CACHE_MRC_SETTINGS @@ -175,6 +176,23 @@ config MONOTONIC_TIMER_MSR help Provide a monotonic timer using the 24MHz MSR counter. +config INTEL_PCH_UART_CONSOLE + bool "Use Serial IO UART for console" + default n + select HAVE_UART_MEMORY_MAPPED + select CONSOLE_SERIAL8250MEM + depends on !CONFIG_DRIVERS_OXFORD_OXPCIE + +config INTEL_PCH_UART_CONSOLE_NUMBER + hex "Serial IO UART number to use for console" + default "0x0" + depends on INTEL_PCH_UART_CONSOLE + +config TTYS0_BASE + hex + default 0xd6000000 + depends on INTEL_PCH_UART_CONSOLE + config EHCI_BAR hex default 0xd8000000 diff --git a/src/soc/intel/broadwell/Makefile.inc b/src/soc/intel/broadwell/Makefile.inc index 9d7ab1e..072ab1f 100644 --- a/src/soc/intel/broadwell/Makefile.inc +++ b/src/soc/intel/broadwell/Makefile.inc @@ -10,6 +10,7 @@ subdirs-y += ../../../cpu/intel/microcode subdirs-y += ../../../cpu/intel/turbo ramstage-y += acpi.c +ramstage-y += adsp.c ramstage-y += chip.c ramstage-y += cpu.c ramstage-y += elog.c @@ -62,6 +63,12 @@ ramstage-y += ehci.c ramstage-y += xhci.c smm-y += xhci.c +ifeq ($(CONFIG_USBDEBUG),y) +ramstage-y += usbdebug.c +romstage-y += usbdebug.c +smm-y += usbdebug.c +endif + INCLUDES += -Isrc/soc/intel/broadwell/ # Run an intermediate step when producing coreboot.rom diff --git a/src/soc/intel/broadwell/acpi.c b/src/soc/intel/broadwell/acpi.c index 782503e..f4cac7b 100644 --- a/src/soc/intel/broadwell/acpi.c +++ b/src/soc/intel/broadwell/acpi.c @@ -604,10 +604,5 @@ unsigned long acpi_madt_irq_overrides(unsigned long current) irqovr = (void *)current; current += acpi_create_madt_irqoverride(irqovr, 0, sci, sci, flags); - /* GPIO Controller */ - irqovr = (void *)current; - flags = MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH; - current += acpi_create_madt_irqoverride(irqovr, 0, 14, 14, flags); - return current; } diff --git a/src/soc/intel/broadwell/acpi/adsp.asl b/src/soc/intel/broadwell/acpi/adsp.asl new file mode 100644 index 0000000..d50dce6 --- /dev/null +++ b/src/soc/intel/broadwell/acpi/adsp.asl @@ -0,0 +1,63 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +Device (ADSP) +{ + Method (_HID, 0, Serialized) + { + If (\ISWP ()) { + // WildcatPoint + Return ("INT3438") + } + + // LynxPoint-LP + Return ("INT33C8") + } + Name (_UID, 1) + Name (_DDN, "Intel Smart Sound Technology") + + Name (RBUF, ResourceTemplate () + { + Memory32Fixed (ReadWrite, 0x00000000, 0x00100000, BAR0) + Memory32Fixed (ReadWrite, 0x00000000, 0x00001000, BAR1) + Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , , ) {3} + }) + + Method (_CRS, 0, NotSerialized) + { + // Update BAR0 address and length if set in NVS + If (LNotEqual (\S8B0, Zero)) { + CreateDwordField (^RBUF, ^BAR0._BAS, B8A0) + CreateDwordField (^RBUF, ^BAR1._BAS, B8A1) + Store (\S8B0, B8A0) + Store (\S8B1, B8A1) + } + + Return (RBUF) + } + + Method (_STA, 0, NotSerialized) + { + If (LEqual (\S8EN, 0)) { + Return (0x0) + } Else { + Return (0xF) + } + } +} diff --git a/src/soc/intel/broadwell/acpi/device_nvs.asl b/src/soc/intel/broadwell/acpi/device_nvs.asl index d5af2e8..1d2aa78 100644 --- a/src/soc/intel/broadwell/acpi/device_nvs.asl +++ b/src/soc/intel/broadwell/acpi/device_nvs.asl @@ -27,6 +27,7 @@ S4EN, 8, // SPI1 Enable S5EN, 8, // UART0 Enable S6EN, 8, // UART1 Enable S7EN, 8, // SDIO Enable +S8EN, 8, // ADSP Enable /* BAR 0 */ @@ -38,6 +39,7 @@ S4B0, 32, // SPI1 BAR0 S5B0, 32, // UART0 BAR0 S6B0, 32, // UART1 BAR0 S7B0, 32, // SDIO BAR0 +S8B0, 32, // ADSP BAR0 /* BAR 1 */ @@ -49,3 +51,4 @@ S4B1, 32, // SPI1 BAR1 S5B1, 32, // UART0 BAR1 S6B1, 32, // UART1 BAR1 S7B1, 32, // SDIO BAR1 +S8B1, 32, // ADSP BAR1 diff --git a/src/soc/intel/broadwell/acpi/gpio.asl b/src/soc/intel/broadwell/acpi/gpio.asl index 5df512e..c6d8753 100644 --- a/src/soc/intel/broadwell/acpi/gpio.asl +++ b/src/soc/intel/broadwell/acpi/gpio.asl @@ -20,8 +20,16 @@ Device (GPIO) { // GPIO Controller - Name (_HID, "INT33C7") - Name (_CID, "INT33C7") + Method (_HID) + { + If (\ISWP ()) { + // WildcatPoint + Return ("INT3437") + } + + // LynxPoint-LP + Return ("INT33C7") + } Name (_UID, 1) Name (RBUF, ResourceTemplate() @@ -39,8 +47,9 @@ Device (GPIO) , // ResourceSourceIndex , // ResourceSource BAR0) - Interrupt (ResourceConsumer, - Level, ActiveHigh, Shared, , , ) {14} + // Disabled due to IRQ storm: http://crosbug.com/p/29548 + //Interrupt (ResourceConsumer, + // Level, ActiveHigh, Shared, , , ) {14} }) Method (_CRS, 0, NotSerialized) diff --git a/src/soc/intel/broadwell/acpi/lpc.asl b/src/soc/intel/broadwell/acpi/lpc.asl index 2f27d9b..ae634a3 100644 --- a/src/soc/intel/broadwell/acpi/lpc.asl +++ b/src/soc/intel/broadwell/acpi/lpc.asl @@ -27,10 +27,12 @@ Device (LPCB) OperationRegion(LPC0, PCI_Config, 0x00, 0x100) Field (LPC0, AnyAcc, NoLock, Preserve) { + Offset (0x02), + PDID, 16, // Device ID Offset (0x40), PMBS, 16, // PMBASE Offset (0x48), - GPBS, 16, // GPIOBASE + GPBS, 16, // GPIOBASE Offset (0x60), // Interrupt Routing Registers PRTA, 8, PRTB, 8, diff --git a/src/soc/intel/broadwell/acpi/pch.asl b/src/soc/intel/broadwell/acpi/pch.asl index c484493..e40c042 100644 --- a/src/soc/intel/broadwell/acpi/pch.asl +++ b/src/soc/intel/broadwell/acpi/pch.asl @@ -39,11 +39,29 @@ Scope (\) , 5, HPTE, 1, // Address Enable } + + /* + * Check PCH type + * Return 1 if PCH is WildcatPoint + * Return 0 if PCH is LynxPoint + */ + Method (ISWP) + { + And (\_SB.PCI0.LPCB.PDID, 0xfff0, Local0) + If (LEqual (Local0, 0x9cc0)) { + Return (1) + } Else { + Return (0) + } + } } // High Definition Audio (Azalia) 0:1b.0 #include "hda.asl" +// ADSP/SST 0:13.0 +#include "adsp.asl" + // PCI Express Ports 0:1c.x #include "pcie.asl" diff --git a/src/soc/intel/broadwell/acpi/serialio.asl b/src/soc/intel/broadwell/acpi/serialio.asl index 532eb50..6b42d54 100644 --- a/src/soc/intel/broadwell/acpi/serialio.asl +++ b/src/soc/intel/broadwell/acpi/serialio.asl @@ -22,6 +22,46 @@ // Serial IO Device BAR0 and BAR1 is 4KB #define SIO_BAR_LEN 0x1000 +// Put SerialIO device in D0 state +// Arg0 - BAR1 of device +// Arg1 - Set if device is in ACPI mode +Method (LPD0, 2, Serialized) +{ + // PCI mode devices will be handled by OS PCI bus driver + If (LEqual (Arg1, 0)) { + Return + } + + OperationRegion (SPRT, SystemMemory, Add (Arg0, 0x84), 4) + Field (SPRT, DWordAcc, NoLock, Preserve) + { + SPCS, 32 + } + + And (SPCS, 0xFFFFFFFC, SPCS) + Store (SPCS, Local0) // Read back after writing +} + +// Put SerialIO device in D3 state +// Arg0 - BAR1 of device +// Arg1 - Set if device is in ACPI mode +Method (LPD3, 2, Serialized) +{ + // PCI mode devices will be handled by OS PCI bus driver + If (LEqual (Arg1, 0)) { + Return + } + + OperationRegion (SPRT, SystemMemory, Add (Arg0, 0x84), 4) + Field (SPRT, DWordAcc, NoLock, Preserve) + { + SPCS, 32 + } + + Or (SPCS, 0x3, SPCS) + Store (SPCS, Local0) // Read back after writing +} + // Serial IO Resource Consumption for BAR1 Device (SIOR) { @@ -152,11 +192,22 @@ Device (SDMA) Device (I2C0) { // Serial IO I2C0 Controller - Name (_HID, "INT33C2") - Name (_CID, "INT33C2") + Method (_HID) + { + If (\ISWP ()) { + // WildcatPoint + Return ("INT3432") + } + + // LynxPoint-LP + Return ("INT33C2") + } Name (_UID, 1) Name (_ADR, 0x00150001) + Name (SSCN, Package () { 432, 507, 9 }) + Name (FMCN, Package () { 72, 160, 9 }) + // BAR0 is assigned during PCI enumeration and saved into NVS Name (RBUF, ResourceTemplate () { @@ -167,9 +218,8 @@ Device (I2C0) // DMA channels are only used if Serial IO DMA controller is enabled Name (DBUF, ResourceTemplate () { - // TODO: Need to update IASL to support FixedDMA - //FixedDMA (0x18, 4, Width32Bit, DMA1) // Tx - //FixedDMA (0x19, 5, Width32Bit, DMA2) // Rx + FixedDMA (0x18, 4, Width32Bit, DMA1) // Tx + FixedDMA (0x19, 5, Width32Bit, DMA2) // Rx }) Method (_CRS, 0, NotSerialized) @@ -198,16 +248,37 @@ Device (I2C0) Return (0xF) } } + + Method (_PS0, 0, Serialized) + { + ^^LPD0 (\S1B1, \S1EN) + } + + Method (_PS3, 0, Serialized) + { + ^^LPD3 (\S1B1, \S1EN) + } } Device (I2C1) { // Serial IO I2C1 Controller - Name (_HID, "INT33C3") - Name (_CID, "INT33C3") + Method (_HID) + { + If (\ISWP ()) { + // WildcatPoint + Return ("INT3433") + } + + // LynxPoint-LP + Return ("INT33C3") + } Name (_UID, 1) Name (_ADR, 0x00150002) + Name (SSCN, Package () { 432, 507, 9 }) + Name (FMCN, Package () { 72, 160, 9 }) + // BAR0 is assigned during PCI enumeration and saved into NVS Name (RBUF, ResourceTemplate () { @@ -218,9 +289,8 @@ Device (I2C1) // DMA channels are only used if Serial IO DMA controller is enabled Name (DBUF, ResourceTemplate () { - // TODO: Need to update IASL to support FixedDMA - //FixedDMA (0x1A, 6, Width32Bit, DMA1) // Tx - //FixedDMA (0x1B, 7, Width32Bit, DMA2) // Rx + FixedDMA (0x1A, 6, Width32Bit, DMA1) // Tx + FixedDMA (0x1B, 7, Width32Bit, DMA2) // Rx }) Method (_CRS, 0, NotSerialized) @@ -249,13 +319,31 @@ Device (I2C1) Return (0xF) } } + + Method (_PS0, 0, Serialized) + { + ^^LPD0 (\S2B1, \S2EN) + } + + Method (_PS3, 0, Serialized) + { + ^^LPD3 (\S2B1, \S2EN) + } } Device (SPI0) { // Serial IO SPI0 Controller - Name (_HID, "INT33C0") - Name (_CID, "INT33C0") + Method (_HID) + { + If (\ISWP ()) { + // WildcatPoint + Return ("INT3430") + } + + // LynxPoint-LP + Return ("INT33C0") + } Name (_UID, 1) Name (_ADR, 0x00150003) @@ -287,13 +375,31 @@ Device (SPI0) Return (0xF) } } + + Method (_PS0, 0, Serialized) + { + ^^LPD0 (\S3B1, \S3EN) + } + + Method (_PS3, 0, Serialized) + { + ^^LPD3 (\S3B1, \S3EN) + } } Device (SPI1) { // Serial IO SPI1 Controller - Name (_HID, "INT33C1") - Name (_CID, "INT33C1") + Method (_HID) + { + If (\ISWP ()) { + // WildcatPoint + Return ("INT3431") + } + + // LynxPoint-LP + Return ("INT33C1") + } Name (_UID, 1) Name (_ADR, 0x00150004) @@ -307,9 +413,8 @@ Device (SPI1) // DMA channels are only used if Serial IO DMA controller is enabled Name (DBUF, ResourceTemplate () { - // TODO: Need to update IASL to support FixedDMA - //FixedDMA (0x10, 0, Width32Bit, DMA1) // Tx - //FixedDMA (0x11, 1, Width32Bit, DMA2) // Rx + FixedDMA (0x10, 0, Width32Bit, DMA1) // Tx + FixedDMA (0x11, 1, Width32Bit, DMA2) // Rx }) Method (_CRS, 0, NotSerialized) @@ -338,13 +443,31 @@ Device (SPI1) Return (0xF) } } + + Method (_PS0, 0, Serialized) + { + ^^LPD0 (\S4B1, \S4EN) + } + + Method (_PS3, 0, Serialized) + { + ^^LPD3 (\S4B1, \S4EN) + } } Device (UAR0) { // Serial IO UART0 Controller - Name (_HID, "INT33C4") - Name (_CID, "INT33C4") + Method (_HID) + { + If (\ISWP ()) { + // WildcatPoint + Return ("INT3434") + } + + // LynxPoint-LP + Return ("INT33C4") + } Name (_UID, 1) Name (_ADR, 0x00150005) @@ -358,9 +481,8 @@ Device (UAR0) // DMA channels are only used if Serial IO DMA controller is enabled Name (DBUF, ResourceTemplate () { - // TODO: Need to update IASL to support FixedDMA - //FixedDMA (0x16, 2, Width32Bit, DMA1) // Tx - //FixedDMA (0x17, 3, Width32Bit, DMA2) // Rx + FixedDMA (0x16, 2, Width32Bit, DMA1) // Tx + FixedDMA (0x17, 3, Width32Bit, DMA2) // Rx }) Method (_CRS, 0, NotSerialized) @@ -389,13 +511,31 @@ Device (UAR0) Return (0xF) } } + + Method (_PS0, 0, Serialized) + { + ^^LPD0 (\S5B1, \S5EN) + } + + Method (_PS3, 0, Serialized) + { + ^^LPD3 (\S5B1, \S5EN) + } } Device (UAR1) { // Serial IO UART1 Controller - Name (_HID, "INT33C5") - Name (_CID, "INT33C5") + Method (_HID) + { + If (\ISWP ()) { + // WildcatPoint + Return ("INT3435") + } + + // LynxPoint-LP + Return ("INT33C5") + } Name (_UID, 1) Name (_ADR, 0x00150006) @@ -427,12 +567,31 @@ Device (UAR1) Return (0xF) } } + + Method (_PS0, 0, Serialized) + { + ^^LPD0 (\S6B1, \S6EN) + } + + Method (_PS3, 0, Serialized) + { + ^^LPD3 (\S6B1, \S6EN) + } } Device (SDIO) { // Serial IO SDIO Controller - Name (_HID, "INT33C6") + Method (_HID) + { + If (\ISWP ()) { + // WildcatPoint + Return ("INT3436") + } + + // LynxPoint-LP + Return ("INT33C6") + } Name (_CID, "PNP0D40") Name (_UID, 1) Name (_ADR, 0x00170000) diff --git a/src/soc/intel/broadwell/adsp.c b/src/soc/intel/broadwell/adsp.c new file mode 100644 index 0000000..2a6dc17 --- /dev/null +++ b/src/soc/intel/broadwell/adsp.c @@ -0,0 +1,152 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <cbmem.h> +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <device/pci_ops.h> +#include <arch/io.h> +#include <delay.h> +#include <broadwell/adsp.h> +#include <broadwell/device_nvs.h> +#include <broadwell/iobp.h> +#include <broadwell/nvs.h> +#include <broadwell/pch.h> +#include <broadwell/ramstage.h> +#include <broadwell/rcba.h> +#include <chip.h> + +static void adsp_init(struct device *dev) +{ + config_t *config = dev->chip_info; + struct resource *bar0, *bar1; + u32 tmp32; + + /* Ensure memory and bus master are enabled */ + tmp32 = pci_read_config32(dev, PCI_COMMAND); + tmp32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; + pci_write_config32(dev, PCI_COMMAND, tmp32); + + /* Find BAR0 and BAR1 */ + bar0 = find_resource(dev, PCI_BASE_ADDRESS_0); + if (!bar0) + return; + bar1 = find_resource(dev, PCI_BASE_ADDRESS_1); + if (!bar1) + return; + + /* + * Set LTR value in DSP shim LTR control register to 3ms + * SNOOP_REQ[13]=1b SNOOP_SCALE[12:10]=100b (1ms) SNOOP_VAL[9:0]=3h + */ + tmp32 = pch_is_wpt() ? ADSP_SHIM_BASE_WPT : ADSP_SHIM_BASE_LPT; + write32(bar0->base + tmp32 + ADSP_SHIM_LTRC, ADSP_SHIM_LTRC_VALUE); + + /* Program VDRTCTL2 D19:F0:A8[31:0] = 0x00000fff */ + pci_write_config32(dev, ADSP_PCI_VDRTCTL2, ADSP_VDRTCTL2_VALUE); + + /* Program ADSP IOBP VDLDAT1 to 0x040100 */ + pch_iobp_write(ADSP_IOBP_VDLDAT1, ADSP_VDLDAT1_VALUE); + + /* Set D3 Power Gating Enable in D19:F0:A0 based on PCH type */ + tmp32 = pci_read_config32(dev, ADSP_PCI_VDRTCTL0); + if (pch_is_wpt()) { + tmp32 &= ~ADSP_VDRTCTL0_D3PGD_WPT; + tmp32 &= ~ADSP_VDRTCTL0_D3SRAMPGD_WPT; + } else { + tmp32 &= ~ADSP_VDRTCTL0_D3PGD_LPT; + tmp32 &= ~ADSP_VDRTCTL0_D3SRAMPGD_LPT; + } + pci_write_config32(dev, ADSP_PCI_VDRTCTL0, tmp32); + + /* Set PSF Snoop to SA, RCBA+0x3350[10]=1b */ + RCBA32_OR(0x3350, (1 << 10)); + + /* Set DSP IOBP PMCTL 0x1e0=0x3f */ + pch_iobp_write(ADSP_IOBP_PMCTL, ADSP_PMCTL_VALUE); + + if (config->sio_acpi_mode) { + /* Configure for ACPI mode */ + global_nvs_t *gnvs; + + printk(BIOS_INFO, "ADSP: Enable ACPI Mode IRQ3\n"); + + /* Find ACPI NVS to update BARs */ + gnvs = (global_nvs_t *)cbmem_find(CBMEM_ID_ACPI_GNVS); + if (!gnvs) { + printk(BIOS_ERR, "Unable to locate Global NVS\n"); + return; + } + + /* Save BAR0 and BAR1 to ACPI NVS */ + gnvs->dev.bar0[SIO_NVS_ADSP] = (u32)bar0->base; + gnvs->dev.bar1[SIO_NVS_ADSP] = (u32)bar1->base; + gnvs->dev.enable[SIO_NVS_ADSP] = 1; + + /* Set PCI Config Disable Bit */ + pch_iobp_update(ADSP_IOBP_PCICFGCTL, ~0, ADSP_PCICFGCTL_PCICD); + + /* Set interrupt de-assert/assert opcode override to IRQ3 */ + pch_iobp_write(ADSP_IOBP_VDLDAT2, ADSP_IOBP_ACPI_IRQ3); + + /* Enable IRQ3 in RCBA */ + RCBA32_OR(ACPIIRQEN, ADSP_ACPI_IRQEN); + + /* Set ACPI Interrupt Enable Bit */ + pch_iobp_update(ADSP_IOBP_PCICFGCTL, ~ADSP_PCICFGCTL_SPCBAD, + ADSP_PCICFGCTL_ACPIIE); + + /* Put ADSP in D3hot */ + tmp32 = read32(bar1->base + PCH_PCS); + tmp32 |= PCH_PCS_PS_D3HOT; + write32(bar1->base + PCH_PCS, tmp32); + } else { + printk(BIOS_INFO, "ADSP: Enable PCI Mode IRQ23\n"); + + /* Configure for PCI mode */ + pci_write_config32(dev, PCI_INTERRUPT_LINE, ADSP_PCI_IRQ); + + /* Clear ACPI Interrupt Enable Bit */ + pch_iobp_update(ADSP_IOBP_PCICFGCTL, + ~(ADSP_PCICFGCTL_SPCBAD | ADSP_PCICFGCTL_ACPIIE), 0); + } +} + +static struct device_operations adsp_ops = { + .read_resources = &pci_dev_read_resources, + .set_resources = &pci_dev_set_resources, + .enable_resources = &pci_dev_enable_resources, + .init = &adsp_init, + .ops_pci = &broadwell_pci_ops, +}; + +static const unsigned short pci_device_ids[] = { + 0x9c36, /* LynxPoint */ + 0x9cb6, /* WildcatPoint */ + 0 +}; + +static const struct pci_driver pch_adsp __pci_driver = { + .ops = &adsp_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .devices = pci_device_ids, +}; + diff --git a/src/soc/intel/broadwell/broadwell/adsp.h b/src/soc/intel/broadwell/broadwell/adsp.h new file mode 100644 index 0000000..747a123 --- /dev/null +++ b/src/soc/intel/broadwell/broadwell/adsp.h @@ -0,0 +1,56 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _BROADWELL_ADSP_H_ +#define _BROADWELL_ADSP_H_ + +#define ADSP_PCI_IRQ 23 +#define ADSP_ACPI_IRQ 3 +#define ADSP_ACPI_IRQEN (1 << 3) + +#define ADSP_SHIM_BASE_LPT 0xe7000 +#define ADSP_SHIM_BASE_WPT 0xfb000 +#define ADSP_SHIM_LTRC 0xe0 +#define ADSP_SHIM_LTRC_VALUE 0x3003 +#define ADSP_SHIM_IMC 0x28 +#define ADSP_SHIM_IPCD 0x40 + +#define ADSP_PCI_VDRTCTL0 0xa0 +#define ADSP_VDRTCTL0_D3PGD_LPT (1 << 1) +#define ADSP_VDRTCTL0_D3PGD_WPT (1 << 0) +#define ADSP_VDRTCTL0_D3SRAMPGD_LPT (1 << 2) +#define ADSP_VDRTCTL0_D3SRAMPGD_WPT (1 << 1) +#define ADSP_PCI_VDRTCTL1 0xa4 +#define ADSP_PCI_VDRTCTL2 0xa8 +#define ADSP_VDRTCTL2_VALUE 0x00000fff + +#define ADSP_IOBP_VDLDAT1 0xd7000624 +#define ADSP_VDLDAT1_VALUE 0x00040100 +#define ADSP_IOBP_VDLDAT2 0xd7000628 +#define ADSP_IOBP_ACPI_IRQ3 0xd9d8 +#define ADSP_IOBP_ACPI_IRQ3I 0xd8d9 +#define ADSP_IOBP_ACPI_IRQ4 0xdbda +#define ADSP_IOBP_PMCTL 0xd70001e0 +#define ADSP_PMCTL_VALUE 0x3f +#define ADSP_IOBP_PCICFGCTL 0xd7000500 +#define ADSP_PCICFGCTL_PCICD (1 << 0) +#define ADSP_PCICFGCTL_ACPIIE (1 << 1) +#define ADSP_PCICFGCTL_SPCBAD (1 << 7) + +#endif diff --git a/src/soc/intel/broadwell/broadwell/cpu.h b/src/soc/intel/broadwell/broadwell/cpu.h index 0f6f593..312532d 100644 --- a/src/soc/intel/broadwell/broadwell/cpu.h +++ b/src/soc/intel/broadwell/broadwell/cpu.h @@ -36,6 +36,7 @@ #define CPUID_HASWELL_HALO 0x40661 #define CPUID_BROADWELL_C0 0x306d2 #define CPUID_BROADWELL_D0 0x306d3 +#define CPUID_BROADWELL_E0 0x306d4 /* CPU bus clock is fixed at 100MHz */ #define CPU_BCLK 100 diff --git a/src/soc/intel/broadwell/broadwell/device_nvs.h b/src/soc/intel/broadwell/broadwell/device_nvs.h index f10f28d..7dab40d 100644 --- a/src/soc/intel/broadwell/broadwell/device_nvs.h +++ b/src/soc/intel/broadwell/broadwell/device_nvs.h @@ -33,11 +33,12 @@ #define SIO_NVS_UART0 5 #define SIO_NVS_UART1 6 #define SIO_NVS_SDIO 7 +#define SIO_NVS_ADSP 8 typedef struct { - u8 enable[8]; - u32 bar0[8]; - u32 bar1[8]; + u8 enable[9]; + u32 bar0[9]; + u32 bar1[9]; } __attribute__((packed)) device_nvs_t; #endif diff --git a/src/soc/intel/broadwell/broadwell/pci_devs.h b/src/soc/intel/broadwell/broadwell/pci_devs.h index 9c3dd06..76e3a68 100644 --- a/src/soc/intel/broadwell/broadwell/pci_devs.h +++ b/src/soc/intel/broadwell/broadwell/pci_devs.h @@ -20,6 +20,9 @@ #ifndef _BROADWELL_PCI_DEVS_H_ #define _BROADWELL_PCI_DEVS_H_ +#define _SA_DEVFN(slot) PCI_DEVFN(SA_DEV_SLOT_ ## slot, 0) +#define _PCH_DEVFN(slot,func) PCI_DEVFN(PCH_DEV_SLOT_ ## slot, func) + #if defined(__PRE_RAM__) || defined(__SMM__) || defined(__ROMCC__) #include <arch/io.h> #define _SA_DEV(slot) PCI_DEV(0, SA_DEV_SLOT_ ## slot, 0) @@ -27,43 +30,90 @@ #else #include <device/device.h> #include <device/pci_def.h> -#define _SA_DEV(slot) dev_find_slot(0, \ - PCI_DEVFN(SA_DEV_SLOT_ ## slot, 0)) -#define _PCH_DEV(slot,func) dev_find_slot(0, \ - PCI_DEVFN(PCH_DEV_SLOT_ ## slot, func)) +#define _SA_DEV(slot) dev_find_slot(0, _SA_DEVFN(slot)) +#define _PCH_DEV(slot,func) dev_find_slot(0, _PCH_DEVFN(slot, func)) #endif /* System Agent Devices */ #define SA_DEV_SLOT_ROOT 0x00 +#define SA_DEVFN_ROOT _SA_DEVFN(ROOT) +#define SA_DEV_ROOT _SA_DEV(ROOT) + #define SA_DEV_SLOT_IGD 0x02 -#define SA_DEV_SLOT_MINIHD 0x03 +#define SA_DEVFN_IGD _SA_DEVFN(IGD) +#define SA_DEV_IGD _SA_DEV(IGD) -#define SA_DEV_ROOT _SA_DEV(ROOT) -#define SA_DEV_IGD _SA_DEV(IGD) -#define SA_DEV_MINIHD _SA_DEV(MINIHD) +#define SA_DEV_SLOT_MINIHD 0x03 +#define SA_DEVFN_MINIHD _SA_DEVFN(MINIHD) +#define SA_DEV_MINIHD _SA_DEV(MINIHD) /* PCH Devices */ +#define PCH_DEV_SLOT_ADSP 0x13 +#define PCH_DEVFN_ADSP _PCH_DEVFN(ADSP, 0) +#define PCH_DEV_ADSP _PCH_DEV(ADSP, 0) + #define PCH_DEV_SLOT_XHCI 0x14 +#define PCH_DEVFN_XHCI _PCH_DEVFN(XHCI, 0) +#define PCH_DEV_XHCI _PCH_DEV(XHCI, 0) + #define PCH_DEV_SLOT_SIO 0x15 +#define PCH_DEV_SDMA _PCH_DEV(SIO, 0) +#define PCH_DEV_I2C0 _PCH_DEV(SIO, 1) +#define PCH_DEV_I2C1 _PCH_DEV(SIO, 2) +#define PCH_DEV_SPI0 _PCH_DEV(SIO, 3) +#define PCH_DEV_SPI1 _PCH_DEV(SIO, 4) +#define PCH_DEV_UART0 _PCH_DEV(SIO, 5) +#define PCH_DEV_UART1 _PCH_DEV(SIO, 6) +#define PCH_DEVFN_SDMA _PCH_DEVFN(SIO, 0) +#define PCH_DEVFN_I2C0 _PCH_DEVFN(SIO, 1) +#define PCH_DEVFN_I2C1 _PCH_DEVFN(SIO, 2) +#define PCH_DEVFN_SPI0 _PCH_DEVFN(SIO, 3) +#define PCH_DEVFN_SPI1 _PCH_DEVFN(SIO, 4) +#define PCH_DEVFN_UART0 _PCH_DEVFN(SIO, 5) +#define PCH_DEVFN_UART1 _PCH_DEVFN(SIO, 6) + #define PCH_DEV_SLOT_ME 0x16 +#define PCH_DEVFN_ME _PCH_DEVFN(ME, 0) +#define PCH_DEVFN_ME_2 _PCH_DEVFN(ME, 1) +#define PCH_DEVFN_ME_IDER _PCH_DEVFN(ME, 2) +#define PCH_DEVFN_ME_KT _PCH_DEVFN(ME, 3) +#define PCH_DEV_ME _PCH_DEV(ME, 0) +#define PCH_DEV_ME_2 _PCH_DEV(ME, 1) +#define PCH_DEV_ME_IDER _PCH_DEV(ME, 2) +#define PCH_DEV_ME_KT _PCH_DEV(ME, 3) + +#define PCH_DEV_SLOT_SDIO 0x17 +#define PCH_DEVFN_SDIO _PCH_DEVFN(SDIO, 0) +#define PCH_DEV_SDIO _PCH_DEV(SDIO, 0) + +#define PCH_DEV_SLOT_GBE 0x19 +#define PCH_DEVFN_GBE _PCH_DEVFN(GBE, 0) +#define PCH_DEV_GBE _PCH_DEV(GBE, 0) + #define PCH_DEV_SLOT_HDA 0x1b +#define PCH_DEVFN_HDA _PCH_DEVFN(HDA, 0) +#define PCH_DEV_HDA _PCH_DEV(HDA, 0) + #define PCH_DEV_SLOT_PCIE 0x1c + #define PCH_DEV_SLOT_EHCI 0x1d -#define PCH_DEV_SLOT_LPC 0x1f +#define PCH_DEVFN_EHCI _PCH_DEVFN(EHCI, 0) +#define PCH_DEV_EHCI _PCH_DEV(EHCI, 0) -#define PCH_DEV_XHCI _PCH_DEV(XHCI, 0) -#define PCH_DEV_UART0 _PCH_DEV(UART0, 0) -#define PCH_DEV_UART1 _PCH_DEV(UART1, 0) -#define PCH_DEV_ME _PCH_DEV(ME, 0) -#define PCH_DEV_HDA _PCH_DEV(HDA, 0) -#define PCH_DEV_EHCI _PCH_DEV(EHCI, 0) -#define PCH_DEV_LPC _PCH_DEV(LPC, 0) -#define PCH_DEV_IDE _PCH_DEV(LPC, 1) -#define PCH_DEV_SATA _PCH_DEV(LPC, 2) -#define PCH_DEV_SMBUS _PCH_DEV(LPC, 3) -#define PCH_DEV_SATA2 _PCH_DEV(LPC, 5) -#define PCH_DEV_THERMAL _PCH_DEV(LPC, 6) +#define PCH_DEV_SLOT_LPC 0x1f +#define PCH_DEVFN_LPC _PCH_DEVFN(LPC, 0) +#define PCH_DEVFN_IDE _PCH_DEVFN(LPC, 1) +#define PCH_DEVFN_SATA _PCH_DEVFN(LPC, 2) +#define PCH_DEVFN_SMBUS _PCH_DEVFN(LPC, 3) +#define PCH_DEVFN_SATA2 _PCH_DEVFN(LPC, 5) +#define PCH_DEVFN_THERMAL _PCH_DEVFN(LPC, 6) +#define PCH_DEV_LPC _PCH_DEV(LPC, 0) +#define PCH_DEV_IDE _PCH_DEV(LPC, 1) +#define PCH_DEV_SATA _PCH_DEV(LPC, 2) +#define PCH_DEV_SMBUS _PCH_DEV(LPC, 3) +#define PCH_DEV_SATA2 _PCH_DEV(LPC, 5) +#define PCH_DEV_THERMAL _PCH_DEV(LPC, 6) #endif diff --git a/src/soc/intel/broadwell/broadwell/pei_data.h b/src/soc/intel/broadwell/broadwell/pei_data.h index f8e6306..07b04d2 100644 --- a/src/soc/intel/broadwell/broadwell/pei_data.h +++ b/src/soc/intel/broadwell/broadwell/pei_data.h @@ -31,7 +31,7 @@ #include <types.h> -#define PEI_VERSION 20 +#define PEI_VERSION 21 #define ABI_X86 __attribute__((regparm(0))) @@ -122,6 +122,8 @@ struct pei_data int dq_pins_interleaved; /* Limit DDR3 frequency */ int max_ddr3_freq; + /* Disable self refresh */ + int disable_self_refresh; /* USB port configuration */ struct usb2_port_setting usb2_ports[MAX_USB2_PORTS]; @@ -167,6 +169,9 @@ struct pei_data const void *saved_data; int saved_data_size; + /* Disable use of saved data (can be set by mainboard) */ + int disable_saved_data; + /* Data from MRC that should be saved to flash */ void *data_to_save; int data_to_save_size; diff --git a/src/soc/intel/broadwell/broadwell/romstage.h b/src/soc/intel/broadwell/broadwell/romstage.h index d48ec13..d3702c7 100644 --- a/src/soc/intel/broadwell/broadwell/romstage.h +++ b/src/soc/intel/broadwell/broadwell/romstage.h @@ -29,9 +29,12 @@ struct romstage_timestamps { int count; }; +struct chipset_power_state; +struct pei_data; struct romstage_params { struct romstage_timestamps ts; unsigned long bist; + struct chipset_power_state *power_state; struct pei_data *pei_data; }; @@ -52,6 +55,7 @@ void set_max_freq(void); void systemagent_early_init(void); void pch_early_init(void); +void pch_uart_init(void); void intel_early_me_status(void); void enable_smbus(void); diff --git a/src/soc/intel/broadwell/broadwell/systemagent.h b/src/soc/intel/broadwell/broadwell/systemagent.h index 27c06f7..f95370b 100644 --- a/src/soc/intel/broadwell/broadwell/systemagent.h +++ b/src/soc/intel/broadwell/broadwell/systemagent.h @@ -52,6 +52,10 @@ #define DEVEN_D1F1EN (1 << 2) #define DEVEN_D1F2EN (1 << 1) #define DEVEN_D0EN (1 << 0) +#define DPR 0x5c +#define DPR_EPM (1 << 2) +#define DPR_PRS (1 << 1) +#define DPR_SIZE_MASK 0xff0 #define PAM0 0x80 #define PAM1 0x81 diff --git a/src/soc/intel/broadwell/cpu.c b/src/soc/intel/broadwell/cpu.c index 3676865..58f81fc 100644 --- a/src/soc/intel/broadwell/cpu.c +++ b/src/soc/intel/broadwell/cpu.c @@ -218,7 +218,7 @@ static void initialize_vr_config(void) msr.hi &= 0xc0000000; msr.hi |= (0x01 << (52 - 32)); /* PSI3 threshold - 1A. */ msr.hi |= (0x05 << (42 - 32)); /* PSI2 threshold - 5A. */ - msr.hi |= (0x0f << (32 - 32)); /* PSI1 threshold - 15A. */ + msr.hi |= (0x14 << (32 - 32)); /* PSI1 threshold - 20A. */ msr.hi |= (1 << (62 - 32)); /* Enable PSI4 */ /* Leave the max instantaneous current limit (12:0) to default. */ wrmsr(MSR_VR_CURRENT_CONFIG, msr); @@ -387,6 +387,7 @@ static void configure_c_states(void) msr_t msr; msr = rdmsr(MSR_PMG_CST_CONFIG_CONTROL); + msr.lo |= (1 << 31); // Timed MWAIT Enable msr.lo |= (1 << 30); // Package c-state Undemotion Enable msr.lo |= (1 << 29); // Package c-state Demotion Enable msr.lo |= (1 << 28); // C1 Auto Undemotion Enable @@ -661,6 +662,7 @@ static struct cpu_device_id cpu_table[] = { { X86_VENDOR_INTEL, CPUID_HASWELL_ULT }, { X86_VENDOR_INTEL, CPUID_BROADWELL_C0 }, { X86_VENDOR_INTEL, CPUID_BROADWELL_D0 }, + { X86_VENDOR_INTEL, CPUID_BROADWELL_E0 }, { 0, 0 }, }; diff --git a/src/soc/intel/broadwell/ehci.c b/src/soc/intel/broadwell/ehci.c index e27c8e5..a59d3c8 100644 --- a/src/soc/intel/broadwell/ehci.c +++ b/src/soc/intel/broadwell/ehci.c @@ -26,6 +26,7 @@ #include <usbdebug.h> #include <arch/io.h> #include <broadwell/ehci.h> +#include <broadwell/pch.h> static void usb_ehci_set_subsystem(device_t dev, unsigned vendor, unsigned device) { @@ -70,6 +71,14 @@ static void usb_ehci_set_resources(struct device *dev) #endif } +static void ehci_enable(struct device *dev) +{ + if (CONFIG_USBDEBUG) + dev->enabled = 1; + else + pch_disable_devfn(dev); +} + static struct pci_operations ehci_ops_pci = { .set_subsystem = &usb_ehci_set_subsystem, }; @@ -79,6 +88,7 @@ static struct device_operations usb_ehci_ops = { .set_resources = &usb_ehci_set_resources, .enable_resources = &pci_dev_enable_resources, .ops_pci = &ehci_ops_pci, + .enable = &ehci_enable, }; static const unsigned short pci_device_ids[] = { diff --git a/src/soc/intel/broadwell/hda.c b/src/soc/intel/broadwell/hda.c index 9a9225b..80caa2c 100644 --- a/src/soc/intel/broadwell/hda.c +++ b/src/soc/intel/broadwell/hda.c @@ -27,6 +27,7 @@ #include <arch/io.h> #include <delay.h> #include <soc/intel/common/hda_verb.h> +#include <broadwell/pch.h> #include <broadwell/ramstage.h> #include <broadwell/rcba.h> @@ -134,11 +135,35 @@ static void hda_init(struct device *dev) } } +static void hda_enable(struct device *dev) +{ + u32 reg32; + + if (!dev->enabled) { + /* Route I/O buffers to ADSP function */ + reg32 = pci_read_config32(dev, 0x42); + reg32 |= (1 << 7) | (1 << 6); + pci_write_config32(dev, 0x42, reg32); + + printk(BIOS_INFO, "HDA disabled, I/O buffers routed to ADSP\n"); + + /* Ensure memory, io, and bus master are all disabled */ + reg32 = pci_read_config32(dev, PCI_COMMAND); + reg32 &= ~(PCI_COMMAND_MASTER | + PCI_COMMAND_MEMORY | PCI_COMMAND_IO); + pci_write_config32(dev, PCI_COMMAND, reg32); + + /* Disable this device */ + pch_disable_devfn(dev); + } +} + static struct device_operations hda_ops = { .read_resources = &pci_dev_read_resources, .set_resources = &pci_dev_set_resources, .enable_resources = &pci_dev_enable_resources, .init = &hda_init, + .enable = &hda_enable, .ops_pci = &broadwell_pci_ops, }; diff --git a/src/soc/intel/broadwell/igd.c b/src/soc/intel/broadwell/igd.c index 8235b3f..eac9ac1 100644 --- a/src/soc/intel/broadwell/igd.c +++ b/src/soc/intel/broadwell/igd.c @@ -472,6 +472,7 @@ static void igd_init(struct device *dev) { int is_broadwell = !!(cpu_family_model() == BROADWELL_FAMILY_ULT); u32 rp1_gfx_freq; + extern int oprom_is_loaded; /* IGD needs to be Bus Master */ u32 reg32 = pci_read_config32(dev, PCI_COMMAND); @@ -510,6 +511,18 @@ static void igd_init(struct device *dev) igd_cdclk_init_haswell(dev); reg_script_run_on_dev(dev, haswell_late_init_script); } + + if (!oprom_is_loaded) { + /* + * Enable DDI-A if the Option ROM did not execute: + * + * bit 0: Display detected (RO) + * bit 4: DDI A supports 4 lanes and DDI E is not used + * bit 7: DDI buffer is idle + */ + gtt_write(DDI_BUF_CTL_A, DDI_BUF_IS_IDLE | DDI_A_4_LANES | + DDI_INIT_DISPLAY_DETECTED); + } } static void igd_read_resources(struct device *dev) diff --git a/src/soc/intel/broadwell/me_status.c b/src/soc/intel/broadwell/me_status.c index 476268f..40078b9 100644 --- a/src/soc/intel/broadwell/me_status.c +++ b/src/soc/intel/broadwell/me_status.c @@ -26,6 +26,8 @@ #include <broadwell/pci_devs.h> #include <broadwell/me.h> +#if (CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_DEBUG) + /* HFS1[3:0] Current Working State Values */ static const char *me_cws_values[] = { [ME_HFS_CWS_RESET] = "Reset", @@ -276,3 +278,4 @@ void intel_me_status(void) } printk(BIOS_DEBUG, "\n"); } +#endif diff --git a/src/soc/intel/broadwell/memmap.c b/src/soc/intel/broadwell/memmap.c index c960347..698ff6b 100644 --- a/src/soc/intel/broadwell/memmap.c +++ b/src/soc/intel/broadwell/memmap.c @@ -26,11 +26,18 @@ static unsigned long get_top_of_ram(void) { /* - * Base of TSEG is top of usable DRAM below 4GiB. The register has - * 1 MiB alignement. + * Base of DPR is top of usable DRAM below 4GiB. The register has + * 1 MiB alignment and reports the TOP of the range, the base + * must be calculated from the size in MiB in bits 11:4. */ - u32 tom = pci_read_config32(SA_DEV_ROOT, TSEG); - return (unsigned long) tom & ~((1 << 20) - 1); + u32 dpr = pci_read_config32(SA_DEV_ROOT, DPR); + u32 tom = dpr & ~((1 << 20) - 1); + + /* Subtract DMA Protected Range size if enabled */ + if (dpr & DPR_EPM) + tom -= (dpr & DPR_SIZE_MASK) << 16; + + return (unsigned long)tom; } void *cbmem_top(void) diff --git a/src/soc/intel/broadwell/pch.c b/src/soc/intel/broadwell/pch.c index 9ac8331..82390a4 100644 --- a/src/soc/intel/broadwell/pch.c +++ b/src/soc/intel/broadwell/pch.c @@ -92,91 +92,88 @@ static void pch_enable_d3hot(device_t dev) void pch_disable_devfn(device_t dev) { switch (dev->path.pci.devfn) { - case PCI_DEVFN(19, 0): /* Audio DSP */ + case PCH_DEVFN_ADSP: /* Audio DSP */ RCBA32_OR(FD, PCH_DISABLE_ADSPD); break; - case PCI_DEVFN(20, 0): /* XHCI */ + case PCH_DEVFN_XHCI: /* XHCI */ RCBA32_OR(FD, PCH_DISABLE_XHCI); break; - case PCI_DEVFN(21, 0): /* DMA */ + case PCH_DEVFN_SDMA: /* DMA */ pch_enable_d3hot(dev); pch_iobp_update(SIO_IOBP_FUNCDIS0, ~0UL, SIO_IOBP_FUNCDIS_DIS); break; - case PCI_DEVFN(21, 1): /* I2C0 */ + case PCH_DEVFN_I2C0: /* I2C0 */ pch_enable_d3hot(dev); pch_iobp_update(SIO_IOBP_FUNCDIS1, ~0UL, SIO_IOBP_FUNCDIS_DIS); break; - case PCI_DEVFN(21, 2): /* I2C1 */ + case PCH_DEVFN_I2C1: /* I2C1 */ pch_enable_d3hot(dev); pch_iobp_update(SIO_IOBP_FUNCDIS2, ~0UL, SIO_IOBP_FUNCDIS_DIS); break; - case PCI_DEVFN(21, 3): /* SPI0 */ + case PCH_DEVFN_SPI0: /* SPI0 */ pch_enable_d3hot(dev); pch_iobp_update(SIO_IOBP_FUNCDIS3, ~0UL, SIO_IOBP_FUNCDIS_DIS); break; - case PCI_DEVFN(21, 4): /* SPI1 */ + case PCH_DEVFN_SPI1: /* SPI1 */ pch_enable_d3hot(dev); pch_iobp_update(SIO_IOBP_FUNCDIS4, ~0UL, SIO_IOBP_FUNCDIS_DIS); break; - case PCI_DEVFN(21, 5): /* UART0 */ + case PCH_DEVFN_UART0: /* UART0 */ pch_enable_d3hot(dev); pch_iobp_update(SIO_IOBP_FUNCDIS5, ~0UL, SIO_IOBP_FUNCDIS_DIS); break; - case PCI_DEVFN(21, 6): /* UART1 */ + case PCH_DEVFN_UART1: /* UART1 */ pch_enable_d3hot(dev); pch_iobp_update(SIO_IOBP_FUNCDIS6, ~0UL, SIO_IOBP_FUNCDIS_DIS); break; - case PCI_DEVFN(22, 0): /* MEI #1 */ + case PCH_DEVFN_ME: /* MEI #1 */ RCBA32_OR(FD2, PCH_DISABLE_MEI1); break; - case PCI_DEVFN(22, 1): /* MEI #2 */ + case PCH_DEVFN_ME_2: /* MEI #2 */ RCBA32_OR(FD2, PCH_DISABLE_MEI2); break; - case PCI_DEVFN(22, 2): /* IDE-R */ + case PCH_DEVFN_ME_IDER: /* IDE-R */ RCBA32_OR(FD2, PCH_DISABLE_IDER); break; - case PCI_DEVFN(22, 3): /* KT */ + case PCH_DEVFN_ME_KT: /* KT */ RCBA32_OR(FD2, PCH_DISABLE_KT); break; - case PCI_DEVFN(23, 0): /* SDIO */ + case PCH_DEVFN_SDIO: /* SDIO */ pch_enable_d3hot(dev); pch_iobp_update(SIO_IOBP_FUNCDIS7, ~0UL, SIO_IOBP_FUNCDIS_DIS); break; - case PCI_DEVFN(25, 0): /* Gigabit Ethernet */ + case PCH_DEVFN_GBE: /* Gigabit Ethernet */ RCBA32_OR(BUC, PCH_DISABLE_GBE); break; - case PCI_DEVFN(26, 0): /* EHCI #2 */ - RCBA32_OR(FD, PCH_DISABLE_EHCI2); - break; - case PCI_DEVFN(27, 0): /* HD Audio Controller */ + case PCH_DEVFN_HDA: /* HD Audio Controller */ RCBA32_OR(FD, PCH_DISABLE_HD_AUDIO); break; - case PCI_DEVFN(28, 0): /* PCI Express Root Port 1 */ - case PCI_DEVFN(28, 1): /* PCI Express Root Port 2 */ - case PCI_DEVFN(28, 2): /* PCI Express Root Port 3 */ - case PCI_DEVFN(28, 3): /* PCI Express Root Port 4 */ - case PCI_DEVFN(28, 4): /* PCI Express Root Port 5 */ - case PCI_DEVFN(28, 5): /* PCI Express Root Port 6 */ - case PCI_DEVFN(28, 6): /* PCI Express Root Port 7 */ - case PCI_DEVFN(28, 7): /* PCI Express Root Port 8 */ + case PCI_DEVFN(PCH_DEV_SLOT_PCIE, 0): /* PCI Express Root Port 1 */ + case PCI_DEVFN(PCH_DEV_SLOT_PCIE, 1): /* PCI Express Root Port 2 */ + case PCI_DEVFN(PCH_DEV_SLOT_PCIE, 2): /* PCI Express Root Port 3 */ + case PCI_DEVFN(PCH_DEV_SLOT_PCIE, 3): /* PCI Express Root Port 4 */ + case PCI_DEVFN(PCH_DEV_SLOT_PCIE, 4): /* PCI Express Root Port 5 */ + case PCI_DEVFN(PCH_DEV_SLOT_PCIE, 5): /* PCI Express Root Port 6 */ + case PCI_DEVFN(PCH_DEV_SLOT_PCIE, 6): /* PCI Express Root Port 7 */ + case PCI_DEVFN(PCH_DEV_SLOT_PCIE, 7): /* PCI Express Root Port 8 */ RCBA32_OR(FD, PCH_DISABLE_PCIE(PCI_FUNC(dev->path.pci.devfn))); break; - case PCI_DEVFN(29, 0): /* EHCI #1 */ + case PCH_DEVFN_EHCI: /* EHCI #1 */ RCBA32_OR(FD, PCH_DISABLE_EHCI1); break; - case PCI_DEVFN(31, 0): /* LPC */ + case PCH_DEVFN_LPC: /* LPC */ RCBA32_OR(FD, PCH_DISABLE_LPC); break; - case PCI_DEVFN(31, 2): /* SATA #1 */ + case PCH_DEVFN_SATA: /* SATA #1 */ RCBA32_OR(FD, PCH_DISABLE_SATA1); break; - case PCI_DEVFN(31, 3): /* SMBUS */ + case PCH_DEVFN_SMBUS: /* SMBUS */ RCBA32_OR(FD, PCH_DISABLE_SMBUS); break; - case PCI_DEVFN(31, 5): /* SATA #2 */ + case PCH_DEVFN_SATA2: /* SATA #2 */ RCBA32_OR(FD, PCH_DISABLE_SATA2); break; - case PCI_DEVFN(31, 6): /* Thermal Subsystem */ + case PCH_DEVFN_THERMAL: /* Thermal Subsystem */ RCBA32_OR(FD, PCH_DISABLE_THERMAL); break; } @@ -186,9 +183,13 @@ void broadwell_pch_enable_dev(device_t dev) { u32 reg32; - /* PCH PCIe Root Ports are handled in PCIe driver. */ - if (PCI_SLOT(dev->path.pci.devfn) == PCH_DEV_SLOT_PCIE) + /* These devices need special enable/disable handling */ + switch (PCI_SLOT(dev->path.pci.devfn)) { + case PCH_DEV_SLOT_PCIE: + case PCH_DEV_SLOT_EHCI: + case PCH_DEV_SLOT_HDA: return; + } if (!dev->enabled) { printk(BIOS_DEBUG, "%s: Disabling device\n", dev_path(dev)); diff --git a/src/soc/intel/broadwell/pei_data.h b/src/soc/intel/broadwell/pei_data.h deleted file mode 100644 index f92c0a6..0000000 --- a/src/soc/intel/broadwell/pei_data.h +++ /dev/null @@ -1,115 +0,0 @@ -/* - * coreboot UEFI PEI wrapper - * - * Copyright (c) 2011, Google Inc. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * * Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * * Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * * Neither the name of Google Inc. nor the - * names of its contributors may be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL GOOGLE INC BE LIABLE FOR ANY DIRECT, - * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef PEI_DATA_H -#define PEI_DATA_H - -typedef void (*tx_byte_func)(unsigned char byte); -#define PEI_VERSION 15 - -#define MAX_USB2_PORTS 16 -#define MAX_USB3_PORTS 16 -#define USB_OC_PIN_SKIP 8 - -enum usb2_port_location { - USB_PORT_BACK_PANEL = 0, - USB_PORT_FRONT_PANEL, - USB_PORT_DOCK, - USB_PORT_MINI_PCIE, - USB_PORT_FLEX, - USB_PORT_INTERNAL, - USB_PORT_SKIP -}; - -/* Usb Port Length: - * [16:4] = length in inches in octal format - * [3:0] = decimal point - */ -struct usb2_port_setting { - uint16_t length; - uint8_t enable; - uint8_t over_current_pin; - uint8_t location; -} __attribute__((packed)); - -struct usb3_port_setting { - uint8_t enable; - uint8_t over_current_pin; -} __attribute__((packed)); - -struct pei_data -{ - uint32_t pei_version; - uint32_t mchbar; - uint32_t dmibar; - uint32_t epbar; - uint32_t pciexbar; - uint16_t smbusbar; - uint32_t wdbbar; - uint32_t wdbsize; - uint32_t hpet_address; - uint32_t rcba; - uint32_t pmbase; - uint32_t gpiobase; - uint32_t temp_mmio_base; - uint32_t system_type; // 0 Mobile, 1 Desktop/Server - uint32_t tseg_size; - uint8_t spd_addresses[4]; - int boot_mode; - int ec_present; - int gbe_enable; - // 0 = leave channel enabled - // 1 = disable dimm 0 on channel - // 2 = disable dimm 1 on channel - // 3 = disable dimm 0+1 on channel - int dimm_channel0_disabled; - int dimm_channel1_disabled; - /* Enable 2x Refresh Mode */ - int ddr_refresh_2x; - int dq_pins_interleaved; - /* Data read from flash and passed into MRC */ - unsigned char *mrc_input; - unsigned int mrc_input_len; - /* Data from MRC that should be saved to flash */ - unsigned char *mrc_output; - unsigned int mrc_output_len; - /* - * Max frequency DDR3 could be ran at. Could be one of four values: 800, - * 1067, 1333, 1600 - */ - uint32_t max_ddr3_freq; - /* Route all USB ports to XHCI controller in resume path */ - int usb_xhci_on_resume; - struct usb2_port_setting usb2_ports[MAX_USB2_PORTS]; - struct usb3_port_setting usb3_ports[MAX_USB3_PORTS]; - uint8_t spd_data[4][256]; - tx_byte_func tx_byte; -} __attribute__((packed)); - -#endif diff --git a/src/soc/intel/broadwell/romstage/Makefile.inc b/src/soc/intel/broadwell/romstage/Makefile.inc index 98d87a4..f8a9617 100644 --- a/src/soc/intel/broadwell/romstage/Makefile.inc +++ b/src/soc/intel/broadwell/romstage/Makefile.inc @@ -10,3 +10,4 @@ romstage-y += smbus.c romstage-y += spi.c romstage-y += stack.c romstage-y += systemagent.c +romstage-$(CONFIG_CONSOLE_SERIAL8250MEM) += uart.c diff --git a/src/soc/intel/broadwell/romstage/cpu.c b/src/soc/intel/broadwell/romstage/cpu.c index e7139b8..754bc31 100644 --- a/src/soc/intel/broadwell/romstage/cpu.c +++ b/src/soc/intel/broadwell/romstage/cpu.c @@ -17,6 +17,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include <arch/cpu.h> #include <stdlib.h> #include <console/console.h> #include <cpu/x86/msr.h> @@ -24,6 +25,11 @@ #include <broadwell/msr.h> #include <broadwell/romstage.h> +u32 cpu_family_model(void) +{ + return cpuid_eax(1) & 0x0fff0ff0; +} + void set_max_freq(void) { msr_t msr, perf_ctl, platform_info; diff --git a/src/soc/intel/broadwell/romstage/raminit.c b/src/soc/intel/broadwell/romstage/raminit.c index 870952f..a5f688e 100644 --- a/src/soc/intel/broadwell/romstage/raminit.c +++ b/src/soc/intel/broadwell/romstage/raminit.c @@ -24,6 +24,7 @@ #include <cbmem.h> #include <console/console.h> #include <device/pci_def.h> +#include <lib.h> #include <string.h> #if CONFIG_EC_GOOGLE_CHROMEEC #include <ec/google/chromeec/ec.h> @@ -73,6 +74,16 @@ void raminit(struct pei_data *pei_data) #endif } + /* + * Do not use saved pei data. Can be set by mainboard romstage + * to force a full train of memory on every boot. + */ + if (pei_data->disable_saved_data) { + printk(BIOS_DEBUG, "Disabling PEI saved data by request\n"); + pei_data->saved_data = NULL; + pei_data->saved_data_size = 0; + } + /* Determine if mrc.bin is in the cbfs. */ entry = (pei_wrapper_entry_t)cbfs_get_file_content( CBFS_DEFAULT_MEDIA, "mrc.bin", 0xab); @@ -95,6 +106,9 @@ void raminit(struct pei_data *pei_data) report_memory_config(); + /* Basic memory sanity test */ + quick_ram_check(); + if (pei_data->boot_mode != SLEEP_STATE_S3) { cbmem_initialize_empty(); } else if (cbmem_initialize()) { diff --git a/src/soc/intel/broadwell/romstage/report_platform.c b/src/soc/intel/broadwell/romstage/report_platform.c index 3c4016f..4e161dc 100644 --- a/src/soc/intel/broadwell/romstage/report_platform.c +++ b/src/soc/intel/broadwell/romstage/report_platform.c @@ -41,6 +41,7 @@ static struct { { CPUID_HASWELL_HALO, "Haswell Perf Halo" }, { CPUID_BROADWELL_C0, "Broadwell C0" }, { CPUID_BROADWELL_D0, "Broadwell D0" }, + { CPUID_BROADWELL_E0, "Broadwell E0" }, }; static struct { diff --git a/src/soc/intel/broadwell/romstage/romstage.c b/src/soc/intel/broadwell/romstage/romstage.c index 84d1f11..1d5ee89 100644 --- a/src/soc/intel/broadwell/romstage/romstage.c +++ b/src/soc/intel/broadwell/romstage/romstage.c @@ -73,6 +73,9 @@ void * asmlinkage romstage_main(unsigned long bist, /* Start console drivers */ console_init(); + /* Get power state */ + rp.power_state = fill_power_state(); + /* Print useful platform information */ report_platform_info(); @@ -96,19 +99,16 @@ static inline void chromeos_init(int prev_sleep_state) /* Entry from the mainboard. */ void romstage_common(struct romstage_params *params) { - struct chipset_power_state *ps; struct romstage_handoff *handoff; post_code(0x32); mark_ts(params, timestamp_get()); - /* Get power state */ - ps = fill_power_state(); - params->pei_data->boot_mode = ps->prev_sleep_state; + params->pei_data->boot_mode = params->power_state->prev_sleep_state; #if CONFIG_ELOG_BOOT_COUNT - if (ps->prev_sleep_state != SLEEP_STATE_S3) + if (params->power_state->prev_sleep_state != SLEEP_STATE_S3) boot_count_increment(); #endif @@ -121,11 +121,12 @@ void romstage_common(struct romstage_params *params) handoff = romstage_handoff_find_or_add(); if (handoff != NULL) - handoff->s3_resume = (ps->prev_sleep_state == SLEEP_STATE_S3); + handoff->s3_resume = (params->power_state->prev_sleep_state == + SLEEP_STATE_S3); else printk(BIOS_DEBUG, "Romstage handoff structure not added!\n"); - chromeos_init(ps->prev_sleep_state); + chromeos_init(params->power_state->prev_sleep_state); /* Save timestamp information. */ timestamp_init(params->ts.times[0]); diff --git a/src/soc/intel/broadwell/romstage/uart.c b/src/soc/intel/broadwell/romstage/uart.c new file mode 100644 index 0000000..8214a8a --- /dev/null +++ b/src/soc/intel/broadwell/romstage/uart.c @@ -0,0 +1,85 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/early_variables.h> +#include <arch/io.h> +#include <delay.h> +#include <device/pci_def.h> +#include <reg_script.h> +#include <stdint.h> +#include <uart8250.h> +#include <broadwell/iobp.h> +#include <broadwell/serialio.h> + +const struct reg_script uart_init[] = { + /* Set MMIO BAR */ + REG_PCI_WRITE32(PCI_BASE_ADDRESS_0, CONFIG_TTYS0_BASE), + /* Enable Memory access and Bus Master */ + REG_PCI_OR32(PCI_COMMAND, PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER), + /* Initialize LTR */ + REG_MMIO_RMW32(CONFIG_TTYS0_BASE + SIO_REG_PPR_GEN, + ~SIO_REG_PPR_GEN_LTR_MODE_MASK, 0), + REG_MMIO_RMW32(CONFIG_TTYS0_BASE + SIO_REG_PPR_RST, + ~(SIO_REG_PPR_RST_ASSERT), 0), + /* Take UART out of reset */ + REG_MMIO_OR32(CONFIG_TTYS0_BASE + SIO_REG_PPR_RST, + SIO_REG_PPR_RST_ASSERT), + /* Set M and N divisor inputs and enable clock */ + REG_MMIO_WRITE32(CONFIG_TTYS0_BASE + SIO_REG_PPR_CLOCK, + SIO_REG_PPR_CLOCK_EN | SIO_REG_PPR_CLOCK_UPDATE | + (SIO_REG_PPR_CLOCK_N_DIV << 16) | + (SIO_REG_PPR_CLOCK_M_DIV << 1)), + REG_SCRIPT_END +}; + +void pch_uart_init(void) +{ + /* Program IOBP CB000154h[12,9:8,4:0] = 1001100011111b */ + u32 gpiodf = 0x131f; + device_t dev; + + /* Put UART in byte access mode for 16550 compatibility */ + switch (CONFIG_INTEL_PCH_UART_CONSOLE_NUMBER) { + case 0: + dev = PCH_DEV_UART0; + gpiodf |= SIO_IOBP_GPIODF_UART0_BYTE_ACCESS; + break; + case 1: + dev = PCH_DEV_UART1; + gpiodf |= SIO_IOBP_GPIODF_UART1_BYTE_ACCESS; + break; + default: + return; + } + + /* Program IOBP GPIODF */ + pch_iobp_update(SIO_IOBP_GPIODF, ~gpiodf, gpiodf); + + /* Program IOBP CB000180h[5:0] = 111111b (undefined register) */ + pch_iobp_update(0xcb000180, ~0x0000003f, 0x0000003f); + + /* Initialize chipset uart interface */ + reg_script_run_on_dev(dev, uart_init); + + /* + * Perform standard UART initialization + * Divisor 1 is 115200 BAUD + */ + uart8250_mem_init(CONFIG_TTYS0_BASE, 1); +} diff --git a/src/soc/intel/broadwell/serialio.c b/src/soc/intel/broadwell/serialio.c index bbb018f..e2b17af 100644 --- a/src/soc/intel/broadwell/serialio.c +++ b/src/soc/intel/broadwell/serialio.c @@ -27,6 +27,7 @@ #include <stdlib.h> #include <broadwell/iobp.h> #include <broadwell/nvs.h> +#include <broadwell/pci_devs.h> #include <broadwell/pch.h> #include <broadwell/ramstage.h> #include <broadwell/rcba.h> @@ -34,11 +35,24 @@ #include <chip.h> /* Set D3Hot Power State in ACPI mode */ -static void serialio_enable_d3hot(struct device *dev) +static void serialio_enable_d3hot(struct resource *res) { - u32 reg32 = pci_read_config32(dev, PCH_PCS); + u32 reg32 = read32(res->base + PCH_PCS); reg32 |= PCH_PCS_PS_D3HOT; - pci_write_config32(dev, PCH_PCS, reg32); + write32(res->base + PCH_PCS, reg32); +} + +static int serialio_uart_is_debug(struct device *dev) +{ +#if CONFIG_INTEL_PCH_UART_CONSOLE + switch (dev->path.pci.devfn) { + case PCH_DEVFN_UART0: /* UART0 */ + return !!(CONFIG_INTEL_PCH_UART_CONSOLE_NUMBER == 0); + case PCH_DEVFN_UART1: /* UART1 */ + return !!(CONFIG_INTEL_PCH_UART_CONSOLE_NUMBER == 1); + } +#endif + return 0; } /* Enable clock in PCI mode */ @@ -182,55 +196,55 @@ static void serialio_init(struct device *dev) if (!config->sio_acpi_mode) serialio_enable_clock(bar0); - else if (dev->path.pci.devfn != PCI_DEVFN(21, 0)) - serialio_enable_d3hot(dev); /* all but SDMA */ switch (dev->path.pci.devfn) { - case PCI_DEVFN(21, 0): /* SDMA */ + case PCH_DEVFN_SDMA: /* SDMA */ sio_index = SIO_ID_SDMA; serialio_init_once(config->sio_acpi_mode); serialio_d21_mode(sio_index, SIO_PIN_INTB, config->sio_acpi_mode); break; - case PCI_DEVFN(21, 1): /* I2C0 */ + case PCH_DEVFN_I2C0: /* I2C0 */ sio_index = SIO_ID_I2C0; serialio_d21_ltr(bar0); serialio_i2c_voltage_sel(bar0, config->sio_i2c0_voltage); serialio_d21_mode(sio_index, SIO_PIN_INTC, config->sio_acpi_mode); break; - case PCI_DEVFN(21, 2): /* I2C1 */ + case PCH_DEVFN_I2C1: /* I2C1 */ sio_index = SIO_ID_I2C1; serialio_d21_ltr(bar0); serialio_i2c_voltage_sel(bar0, config->sio_i2c1_voltage); serialio_d21_mode(sio_index, SIO_PIN_INTC, config->sio_acpi_mode); break; - case PCI_DEVFN(21, 3): /* SPI0 */ + case PCH_DEVFN_SPI0: /* SPI0 */ sio_index = SIO_ID_SPI0; serialio_d21_ltr(bar0); serialio_d21_mode(sio_index, SIO_PIN_INTC, config->sio_acpi_mode); break; - case PCI_DEVFN(21, 4): /* SPI1 */ + case PCH_DEVFN_SPI1: /* SPI1 */ sio_index = SIO_ID_SPI1; serialio_d21_ltr(bar0); serialio_d21_mode(sio_index, SIO_PIN_INTC, config->sio_acpi_mode); break; - case PCI_DEVFN(21, 5): /* UART0 */ + case PCH_DEVFN_UART0: /* UART0 */ sio_index = SIO_ID_UART0; - serialio_d21_ltr(bar0); + if (!serialio_uart_is_debug(dev)) + serialio_d21_ltr(bar0); serialio_d21_mode(sio_index, SIO_PIN_INTD, config->sio_acpi_mode); break; - case PCI_DEVFN(21, 6): /* UART1 */ + case PCH_DEVFN_UART1: /* UART1 */ sio_index = SIO_ID_UART1; - serialio_d21_ltr(bar0); + if (!serialio_uart_is_debug(dev)) + serialio_d21_ltr(bar0); serialio_d21_mode(sio_index, SIO_PIN_INTD, config->sio_acpi_mode); break; - case PCI_DEVFN(23, 0): /* SDIO */ + case PCH_DEVFN_SDIO: /* SDIO */ sio_index = SIO_ID_SDIO; serialio_d23_ltr(bar0); serialio_d23_mode(config->sio_acpi_mode); @@ -252,6 +266,14 @@ static void serialio_init(struct device *dev) /* Save BAR0 and BAR1 to ACPI NVS */ gnvs->dev.bar0[sio_index] = (u32)bar0->base; gnvs->dev.bar1[sio_index] = (u32)bar1->base; + + /* Do not enable UART if it is used as debug port */ + if (!serialio_uart_is_debug(dev)) + gnvs->dev.enable[sio_index] = 1; + + /* Put device in D3hot state via BAR1 */ + if (dev->path.pci.devfn != PCH_DEVFN_SDMA) + serialio_enable_d3hot(bar1); /* all but SDMA */ } } diff --git a/src/soc/intel/broadwell/systemagent.c b/src/soc/intel/broadwell/systemagent.c index 56a44d9..787a62b 100644 --- a/src/soc/intel/broadwell/systemagent.c +++ b/src/soc/intel/broadwell/systemagent.c @@ -33,6 +33,7 @@ #include <vendorcode/google/chromeos/chromeos.h> #include <broadwell/cpu.h> #include <broadwell/iomap.h> +#include <broadwell/pci_devs.h> #include <broadwell/ramstage.h> #include <broadwell/systemagent.h> @@ -278,12 +279,26 @@ static void mc_add_dram_resources(device_t dev) unsigned long index; struct resource *resource; uint64_t mc_values[NUM_MAP_ENTRIES]; + unsigned long dpr_size = 0; + u32 dpr_reg; /* Read in the MAP registers and report their values. */ mc_read_map_entries(dev, &mc_values[0]); mc_report_map_entries(dev, &mc_values[0]); /* + * DMA Protected Range can be reserved below TSEG for PCODE patch + * or TXT/BootGuard related data. Rather than report a base address + * the DPR register reports the TOP of the region, which is the same + * as TSEG base. The region size is reported in MiB in bits 11:4. + */ + dpr_reg = pci_read_config32(SA_DEV_ROOT, DPR); + if (dpr_reg & DPR_EPM) { + dpr_size = (dpr_reg & DPR_SIZE_MASK) << 16; + printk(BIOS_INFO, "DPR SIZE: 0x%lx\n", dpr_size); + } + + /* * These are the host memory ranges that should be added: * - 0 -> 0xa0000: cacheable * - 0xc0000 -> TSEG : cacheable @@ -320,14 +335,15 @@ static void mc_add_dram_resources(device_t dev) size_k = (0xa0000 >> 10) - base_k; ram_resource(dev, index++, base_k, size_k); - /* 0xc0000 -> TSEG */ + /* 0xc0000 -> TSEG - DPR */ base_k = 0xc0000 >> 10; size_k = (unsigned long)(mc_values[TSEG_REG] >> 10) - base_k; + size_k -= dpr_size >> 10; ram_resource(dev, index++, base_k, size_k); - /* TSEG -> BGSM */ + /* TSEG - DPR -> BGSM */ resource = new_resource(dev, index++); - resource->base = mc_values[TSEG_REG]; + resource->base = mc_values[TSEG_REG] - dpr_size; resource->size = mc_values[BGSM_REG] - resource->base; resource->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_RESERVE | diff --git a/src/soc/intel/broadwell/usbdebug.c b/src/soc/intel/broadwell/usbdebug.c new file mode 100644 index 0000000..d462e89 --- /dev/null +++ b/src/soc/intel/broadwell/usbdebug.c @@ -0,0 +1,51 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stdint.h> +#include <arch/io.h> +#include <console/console.h> +#include <usbdebug.h> +#include <device/pci.h> +#include <device/pci_def.h> +#include <broadwell/pci_devs.h> + +void set_debug_port(unsigned int port) +{ + /* Hardcoded to physical port 1 */ +} + +void enable_usbdebug(unsigned int port) +{ + u32 tmp32; + + tmp32 = pci_read_config32(PCH_DEV_EHCI, PCI_VENDOR_ID); + if (tmp32 == 0xffffffff || tmp32 == 0) + return; + + /* Set the EHCI BAR address. */ + pci_write_config32(PCH_DEV_EHCI, EHCI_BAR_INDEX, CONFIG_EHCI_BAR); + + /* Enable access to the EHCI memory space registers. */ + pci_write_config8(PCH_DEV_EHCI, PCI_COMMAND, PCI_COMMAND_MEMORY); + + /* Force ownership of the Debug Port to the EHCI controller. */ + tmp32 = read32(CONFIG_EHCI_BAR + CONFIG_EHCI_DEBUG_OFFSET); + tmp32 |= (1 << 30); + write32(CONFIG_EHCI_BAR + CONFIG_EHCI_DEBUG_OFFSET, tmp32); +}

1 0

Patch set updated for coreboot: a95d199 vendorcode: Add ChromeOS VPD parser.
by Isaac Christensen 26 Sep '14

26 Sep '14

Isaac Christensen (isaac.christensen(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6959 -gerrit commit a95d199e9e0009ea7d0498cb58842d4221147b81 Author: Hung-Te Lin <hungte(a)chromium.org> Date: Fri Feb 21 16:21:00 2014 +0800 vendorcode: Add ChromeOS VPD parser. Copied (and unmodified) the minimal bits from ChromeOS libVPD: https://chromium.googlesource.com/chromiumos/platform/vpd Old-Change-Id: Id75d1bfd16263ac1b94c22979f9892cf7908d5e6 Signed-off-by: Hung-Te Lin <hungte(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/187411 Reviewed-by: Yung-chieh Lo <yjlou(a)chromium.org> (cherry picked from commit a10ca23686299f3fd5b639631242cadaa2ca9e8a) vendorcode: Update ChromeOS VPD Parser. Merge recent changes in ChromeOS VPD that allows non-memory-mapped firmware to load VPD easier and faster (ref: https://chromium-review.googlesource.com/188134 ). Old-Change-Id: I3ee0b89c703f476f3d77cdde52cc7588724f7686 Reviewed-on: https://chromium-review.googlesource.com/188743 Tested-by: Hung-Te Lin <hungte(a)chromium.org> Reviewed-by: Yung-chieh Lo <yjlou(a)chromium.org> Reviewed-by: David Hendricks <dhendrix(a)chromium.org> Commit-Queue: Hung-Te Lin <hungte(a)chromium.org> (cherry picked from commit 03f4d521a7fa711b963b0e1822e92eac16a691b1) vendorcode: Access to ChromeOS VPD on default CBFS media. The new function "cros_vpd_gets(key, buf, size)" provides an easy and quick way to retrieve values in ChromeOS VPD section. Old-Change-Id: I38e50615e515707ffaecdc4c4fae65043541b687 Signed-off-by: Hung-Te Lin <hungte(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/187430 Reviewed-by: Yung-chieh Lo <yjlou(a)chromium.org> (cherry picked from commit bcd3832c06e8ed357c50f19396da21a218dc4b39) Squashed 3 related commits for a ChromeOS VPD parser. Change-Id: I4ba8fce16ea123c78d7b543c8353ab9bc1e2aa9f Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com> --- src/vendorcode/google/chromeos/Makefile.inc | 2 + src/vendorcode/google/chromeos/cros_vpd.c | 140 +++++++++++++++++ src/vendorcode/google/chromeos/cros_vpd.h | 21 +++ src/vendorcode/google/chromeos/lib_vpd.h | 226 ++++++++++++++++++++++++++++ src/vendorcode/google/chromeos/vpd_decode.c | 89 +++++++++++ src/vendorcode/google/chromeos/vpd_tables.h | 114 ++++++++++++++ 6 files changed, 592 insertions(+) diff --git a/src/vendorcode/google/chromeos/Makefile.inc b/src/vendorcode/google/chromeos/Makefile.inc index b9e42da..d02c09f 100644 --- a/src/vendorcode/google/chromeos/Makefile.inc +++ b/src/vendorcode/google/chromeos/Makefile.inc @@ -28,6 +28,8 @@ romstage-y += fmap.c ramstage-y += fmap.c ramstage-$(CONFIG_CHROMEOS_RAMOOPS) += ramoops.c smm-y += fmap.c +romstage-y += vpd_decode.c cros_vpd.c +ramstage-y += vpd_decode.c cros_vpd.c ifeq ($(MOCK_TPM),1) CFLAGS_common += -DMOCK_TPM=1 diff --git a/src/vendorcode/google/chromeos/cros_vpd.c b/src/vendorcode/google/chromeos/cros_vpd.c new file mode 100644 index 0000000..26b01ee --- /dev/null +++ b/src/vendorcode/google/chromeos/cros_vpd.c @@ -0,0 +1,140 @@ +/* + * Copyright (c) 2014 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include <console/console.h> + +#include <cbfs.h> +#include <stdlib.h> +#include <string.h> + +#include "cros_vpd.h" +#include "fmap.h" +#include "lib_vpd.h" +#include "vpd_tables.h" + +/* + * Static variables are available in ramstage (all platforms), and romstage for + * some platforms (ex, ARM, which uses SRAM). + */ +#if defined(__PRE_RAM__) && CONFIG_ARCH_X86 +#define STATIC_VAR +#else +#define STATIC_VAR static +#endif + +/* Currently we only support Google VPD 2.0, which has a fixed offset. */ +enum { + GOOGLE_VPD_2_0_OFFSET = 0x600, +}; + +struct vpd_gets_arg { + const uint8_t *key; + const uint8_t *value; + int32_t key_len, value_len; + int matched; +}; + +static int cros_vpd_load(uint8_t **vpd_address, int32_t *vpd_size) +{ + STATIC_VAR int cached = 0; + STATIC_VAR uint8_t *cached_address = NULL; + STATIC_VAR int32_t cached_size = 0; + STATIC_VAR int result = -1; + struct google_vpd_info info; + int32_t base; + + const struct fmap_area *area; + struct cbfs_media media; + + if (cached) { + *vpd_address = cached_address; + *vpd_size = cached_size; + return result; + } + + cached = 1; + area = find_fmap_area(fmap_find(), "RO_VPD"); + if (!area) { + printk(BIOS_ERR, "%s: No RO_VPD FMAP section.\n", __func__); + return result; + } + if (area->size <= GOOGLE_VPD_2_0_OFFSET + sizeof(info)) { + printk(BIOS_ERR, "%s: Too small (%d) for Google VPD 2.0.\n", + __func__, area->size); + return result; + } + + base = area->offset + GOOGLE_VPD_2_0_OFFSET; + cached_size = area->size - GOOGLE_VPD_2_0_OFFSET; + init_default_cbfs_media(&media); + media.open(&media); + + /* Try if we can find a google_vpd_info, otherwise read whole VPD. */ + if (media.read(&media, &info, base, sizeof(info)) == sizeof(info) && + memcmp(info.header.magic, VPD_INFO_MAGIC, sizeof(info.header.magic)) + == 0 && cached_size >= info.size + sizeof(info)) { + base += sizeof(info); + cached_size = info.size; + } + + cached_address = media.map(&media, base, cached_size); + media.close(&media); + if (cached_address) { + *vpd_address = cached_address; + *vpd_size = cached_size; + printk(BIOS_DEBUG, "%s: Got VPD: %#x+%#x\n", __func__, base, + cached_size); + result = 0; + } + return result; +} + +static int vpd_gets_callback(const uint8_t *key, int32_t key_len, + const uint8_t *value, int32_t value_len, + void *arg) +{ + struct vpd_gets_arg *result = (struct vpd_gets_arg *)arg; + if (key_len != result->key_len || + memcmp(key, result->key, key_len) != 0) + /* Returns VPD_OK to continue parsing. */ + return VPD_OK; + + result->matched = 1; + result->value = value; + result->value_len = value_len; + /* Returns VPD_FAIL to stop parsing. */ + return VPD_FAIL; +} + +char *cros_vpd_gets(const char *key, char *buffer, int size) +{ + uint8_t *vpd_address = NULL; + int32_t vpd_size = 0; + struct vpd_gets_arg arg = {0}; + int consumed = 0; + + if (cros_vpd_load(&vpd_address, &vpd_size) != 0) { + return NULL; + } + + arg.key = (const uint8_t *)key; + arg.key_len = strlen(key); + + while (VPD_OK == decodeVpdString(vpd_size, vpd_address, &consumed, + vpd_gets_callback, &arg)) { + /* Iterate until found or no more entries. */ + } + + if (!arg.matched) + return NULL; + + if (size < arg.value_len + 1) + size = arg.value_len + 1; + memcpy(buffer, arg.value, size - 1); + buffer[size - 1] = '\0'; + return buffer; +} + diff --git a/src/vendorcode/google/chromeos/cros_vpd.h b/src/vendorcode/google/chromeos/cros_vpd.h new file mode 100644 index 0000000..674dbf6 --- /dev/null +++ b/src/vendorcode/google/chromeos/cros_vpd.h @@ -0,0 +1,21 @@ +/* + * Copyright (c) 2014 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#ifndef __CROS_VPD_H__ +#define __CROS_VPD_H__ + +/* + * Reads VPD string value by key. + * + * Reads in at most one less than size characters from VPD and stores them + * into buffer. A terminating null byte ('\0') is stored after the last + * character in the buffer. + * + * Returns NULL if key is not found, otherwise buffer. + */ +char *cros_vpd_gets(const char *key, char *buffer, int size); + +#endif /* __CROS_VPD_H__ */ diff --git a/src/vendorcode/google/chromeos/lib_vpd.h b/src/vendorcode/google/chromeos/lib_vpd.h new file mode 100644 index 0000000..e08cb3a --- /dev/null +++ b/src/vendorcode/google/chromeos/lib_vpd.h @@ -0,0 +1,226 @@ +/* + * Copyright (c) 2013 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + * + */ + +#ifndef __LIB_VPD__ +#define __LIB_VPD__ + +#include <inttypes.h> + +enum { + VPD_OK = 0, + VPD_FAIL, +}; + +enum { + VPD_TYPE_TERMINATOR = 0, + VPD_TYPE_STRING, + VPD_TYPE_INFO = 0xfe, + VPD_TYPE_IMPLICIT_TERMINATOR = 0xff, +}; + +enum { + VPD_AS_LONG_AS = -1, +}; + +enum { /* export_type */ + VPD_EXPORT_KEY_VALUE = 1, + VPD_EXPORT_VALUE, + VPD_EXPORT_AS_PARAMETER, +}; + +/* Callback for decodeVpdString to invoke. */ +typedef int VpdDecodeCallback(const uint8_t *key, int32_t key_len, + const uint8_t *value, int32_t value_len, + void *arg); + +/* Container data types */ +struct StringPair { + uint8_t *key; + uint8_t *value; + int pad_len; + int filter_out; /* TRUE means not exported. */ + struct StringPair *next; +}; + +struct PairContainer { + struct StringPair *first; +}; + + +/*********************************************************************** + * Encode and decode VPD entries + ***********************************************************************/ + +/* Encodes the len into multiple bytes with the following format. + * + * 7 6 ............ 0 + * +----+------------------+ + * |More| Length | ... + * +----+------------------+ + * + * The encode_buf points to the actual position we are going to store. + * encoded_len will return the exact bytes we encoded in this function. + * Returns fail if the buffer is not long enough. + */ +int encodeLen( + const int32_t len, + uint8_t *encode_buf, + const int32_t max_len, + int32_t *encoded_len); + +/* Given an encoded string, this functions decodes the length field which varies + * from 1 byte to many bytes. + * + * The in points the actual byte going to be decoded. The *length returns + * the decoded length field. The number of consumed bytes will be stroed in + * decoded_len. + * + * Returns VPD_FAIL if more bit is 1, but actually reaches the end of string. + */ +int decodeLen( + const int32_t max_len, + const uint8_t *in, + int32_t *length, + int32_t *decoded_len); + + +/* Encodes the terminator. + * When calling, the output_buf should point to the start of buffer while + * *generated_len should contain how many bytes exist in buffer now. + * After return, *generated_len would be plused the number of bytes generated + * in this function. + */ +int encodeVpdTerminator( + const int max_buffer_len, + uint8_t *output_buf, + int *generated_len); + +/* Encodes the given type/key/value pair into buffer. + * + * The pad_value_len is used to control the output value length. + * When pad_value_len > 0, the value is outputted into fixed length (pad \0 + * if the value is shorter). Truncated if too long. + * pad_value_len == VPD_NO_LIMIT, output the value as long as possible. + * This is useful when we want to fix the structure layout at beginning. + * + * The encoded string will be stored in output_buf. If it is longer than + * max_buffer_len, this function returns fail. If the buffer is long enough, + * the generated_len will be updated. + * + * When calling, the output_buf should point to the start of buffer while + * *generated_len should contain how many bytes exist in buffer now. + * After return, *generated_len would be plused the number of bytes generated + * in this function. + * + * The initial value of *generated_len can be non-zero, so that this value + * can be used between multiple calls to encodeVpd2Pair(). + */ +int encodeVpdString( + const uint8_t *key, + const uint8_t *value, + const int pad_value_len, + const int max_buffer_len, + uint8_t *output_buf, + int *generated_len); + + +/* Given the encoded string, this function invokes callback with extracted + * (key, value). The *consumed will be plused the number of bytes consumed in + * this function. + * + * The input_buf points to the first byte of the input buffer. + * + * The *consumed starts from 0, which is actually the next byte to be decoded. + * It can be non-zero to be used in multiple calls. + * + * If one entry is successfully decoded, sends it to callback and returns the + * result. + */ +int decodeVpdString( + const int32_t max_len, + const uint8_t *input_buf, + int32_t *consumed, + VpdDecodeCallback callback, + void *callback_arg); + +/*********************************************************************** + * Container helpers + ***********************************************************************/ +void initContainer(struct PairContainer *container); + +struct StringPair *findString(struct PairContainer *container, + const uint8_t *key, + struct StringPair ***prev_next); + +/* If key is already existed in container, its value will be replaced. + * If not existed, creates new entry in container. + */ +void setString(struct PairContainer *container, + const uint8_t *key, + const uint8_t *value, + const int pad_len); + +/* merge all entries in src into dst. If key is duplicate, overwrite it. + */ +void mergeContainer(struct PairContainer *dst, + const struct PairContainer *src); + +/* subtract src from dst. +*/ +int subtractContainer(struct PairContainer *dst, + const struct PairContainer *src); + +/* Given a container, encode its all entries into the buffer. + */ +int encodeContainer(const struct PairContainer *container, + const int max_buf_len, + uint8_t *buf, + int *generated); + +/* Given a VPD blob, decode its entries and push into container. + */ +int decodeToContainer(struct PairContainer *container, + const int32_t max_len, + const uint8_t *input_buf, + int32_t *consumed); + +/* Set filter for exporting functions. + * If filter is NULL, resets the filter so that everything can be exported. + */ +int setContainerFilter(struct PairContainer *container, + const uint8_t *filter); + +/* + * Remove a key. + * Returns VPD_OK if deleted successfully. Otherwise, VPD_FAIL. + */ +int deleteKey(struct PairContainer *container, + const uint8_t *key); + +/* + * Returns number of pairs in container. + */ +int lenOfContainer(const struct PairContainer *container); + +/* + * Export the container content with human-readable text. + * + * The buf points to the first byte of buffer and *generated contains the number + * of bytes already existed in buffer. + * + * Afterward, the *generated will be plused on exact bytes this function has + * generated. + */ +int exportContainer(const int export_type, + const struct PairContainer *container, + const int max_buf_len, + uint8_t *buf, + int *generated); + +void destroyContainer(struct PairContainer *container); + +#endif /* __LIB_VPD__ */ diff --git a/src/vendorcode/google/chromeos/vpd_decode.c b/src/vendorcode/google/chromeos/vpd_decode.c new file mode 100644 index 0000000..545fd81 --- /dev/null +++ b/src/vendorcode/google/chromeos/vpd_decode.c @@ -0,0 +1,89 @@ +/* + * Copyright (c) 2014 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + * + */ +#include <assert.h> +#include "lib_vpd.h" + +int decodeLen( + const int32_t max_len, + const uint8_t *in, + int32_t *length, + int32_t *decoded_len) { + uint8_t more; + int i = 0; + + assert(length); + assert(decoded_len); + + *length = 0; + do { + if (i >= max_len) return VPD_FAIL; + more = in[i] & 0x80; + *length <<= 7; + *length |= in[i] & 0x7f; + ++i; + } while (more); + + *decoded_len = i; + + return VPD_OK; +} + +/* Sequentially decodes type, key, and value. + */ +int decodeVpdString( + const int32_t max_len, + const uint8_t *input_buf, + int32_t *consumed, + VpdDecodeCallback callback, + void *callback_arg) { + int type; + int32_t key_len, value_len; + int32_t decoded_len; + const uint8_t *key, *value; + + /* type */ + if (*consumed >= max_len) + return VPD_FAIL; + + type = input_buf[*consumed]; + switch (type) { + case VPD_TYPE_INFO: + case VPD_TYPE_STRING: + (*consumed)++; + + /* key */ + if (VPD_OK != decodeLen(max_len - *consumed, &input_buf[*consumed], + &key_len, &decoded_len) || + *consumed + decoded_len >= max_len) { + return VPD_FAIL; + } + + *consumed += decoded_len; + key = &input_buf[*consumed]; + *consumed += key_len; + + /* value */ + if (VPD_OK != decodeLen(max_len - *consumed, &input_buf[*consumed], + &value_len, &decoded_len) || + *consumed + decoded_len > max_len) { + return VPD_FAIL; + } + *consumed += decoded_len; + value = &input_buf[*consumed]; + *consumed += value_len; + + if (type == VPD_TYPE_STRING) + return callback(key, key_len, value, value_len, callback_arg); + + return VPD_OK; + + default: + return VPD_FAIL; + break; + } + return VPD_OK; +} diff --git a/src/vendorcode/google/chromeos/vpd_tables.h b/src/vendorcode/google/chromeos/vpd_tables.h new file mode 100644 index 0000000..d58b5e8 --- /dev/null +++ b/src/vendorcode/google/chromeos/vpd_tables.h @@ -0,0 +1,114 @@ +/* + * Copyright (c) 2014 The Chromium OS Authors. All rights reserved. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + * + * Ported from mosys project (http://code.google.com/p/mosys/). + */ + +#ifndef __LIB_VPD_TABLES_H__ +#define __LIB_VPD_TABLES_H__ + +#include <inttypes.h> + +#define VPD_ENTRY_MAGIC "_SM_" +#define VPD_INFO_MAGIC \ + "\xfe" /* type: VPD header */ \ + "\x09" /* key length, 9 = 1 + 8 */ \ + "\x01" /* info version, 1 */ \ + "gVpdInfo" /* signature, 8 bytes */ \ + "\x04" /* value length */ + +/* Google specific VPD info */ +struct google_vpd_info { + union { + struct { + uint8_t type; + uint8_t key_len; + uint8_t info_ver; + uint8_t signature[8]; + uint8_t value_len; + } tlv; + uint8_t magic[12]; + } header; + uint32_t size; +} __attribute__((packed)); + +/* Entry */ +struct vpd_entry { + uint8_t anchor_string[4]; + uint8_t entry_cksum; + uint8_t entry_length; + uint8_t major_ver; + uint8_t minor_ver; + uint16_t max_size; + uint8_t entry_rev; + uint8_t format_area[5]; + uint8_t inter_anchor_string[5]; + uint8_t inter_anchor_cksum; + uint16_t table_length; + uint32_t table_address; + uint16_t table_entry_count; + uint8_t bcd_revision; +} __attribute__ ((packed)); + +/* Header */ +struct vpd_header { + uint8_t type; + uint8_t length; + uint16_t handle; +} __attribute__ ((packed)); + +/* Type 0 - firmware information */ +struct vpd_table_firmware { + uint8_t vendor; + uint8_t version; + uint16_t start_address; + uint8_t release_date; + uint8_t rom_size_64k_blocks; + uint32_t characteristics; + uint8_t extension[2]; /* v2.4+ */ + uint8_t major_ver; /* v2.4+ */ + uint8_t minor_ver; /* v2.4+ */ + uint8_t ec_major_ver; /* v2.4+ */ + uint8_t ec_minor_ver; /* v2.4+ */ +} __attribute__ ((packed)); + +/* Type 1 - system information */ +struct vpd_table_system { + uint8_t manufacturer; + uint8_t name; + uint8_t version; + uint8_t serial_number; + uint8_t uuid[16]; + uint8_t wakeup_type; + uint8_t sku_number; /* v2.4+ */ + uint8_t family; /* v2.4+ */ +} __attribute__ ((packed)); + +/* Type 127 - end of table */ +struct vpd_table_eot { + struct vpd_header header; +} __attribute__ ((packed)); + +/* Type 241 - binary blob pointer */ +struct vpd_table_binary_blob_pointer { + uint8_t struct_major_version; + uint8_t struct_minor_version; + uint8_t vendor; + uint8_t description; + uint8_t major_version; + uint8_t minor_version; + uint8_t variant; + uint8_t reserved[5]; + uint8_t uuid[16]; + uint32_t offset; + uint32_t size; +} __attribute__ ((packed)); + +/* The length and number of strings defined here is not a limitation of VPD. + * These numbers were deemed good enough during development. */ +#define VPD_MAX_STRINGS 10 +#define VPD_MAX_STRING_LENGTH 64 + +#endif /* __LIB_VPD_TABLES_H__ */

1 0

Patch set updated for coreboot: 9466f0f gen: Add "assert" in assert.h.
by Bruce Griffith 26 Sep '14

26 Sep '14

Bruce Griffith (Bruce.Griffith(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6961 -gerrit commit 9466f0f2114fbbe58e84b594c9c13bb1f682e4f4 Author: Hung-Te Lin <hungte(a)chromium.org> Date: Fri Feb 21 16:22:52 2014 +0800 gen: Add "assert" in assert.h. Typically assert.h should provide assert(). Change-Id: I465f4a616b212f7b00d445c575866b13eecfa6fb Signed-off-by: Hung-Te Lin <hungte(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/187410 Reviewed-by: Julius Werner <jwerner(a)chromium.org> (cherry picked from commit 3990584ac8e1ec9b3838bd9dfdf8a9cb2d20fbd0) Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com> Signed-off-by: Bruce Griffith <Bruce.Griffith(a)se-eng.com> --- src/include/assert.h | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/src/include/assert.h b/src/include/assert.h index 346e769..9f624a9 100644 --- a/src/include/assert.h +++ b/src/include/assert.h @@ -20,6 +20,8 @@ #ifndef __ASSERT_H__ #define __ASSERT_H__ +#include <console/console.h> + #if defined(__PRE_RAM__) && !CONFIG_CACHE_AS_RAM /* ROMCC versions */ @@ -59,6 +61,8 @@ /* die(""); */ \ } -#endif +#endif /* defined(__PRE_RAM__) && !CONFIG_CACHE_AS_RAM */ + +#define assert(statement) ASSERT(statement) #endif // __ASSERT_H__

1 0

Patch set updated for coreboot: e212a11 AGESA stub 00730F01: Add config.h and kconfig.h to Makefile.inc
by Bruce Griffith 26 Sep '14

26 Sep '14

Bruce Griffith (Bruce.Griffith(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6979 -gerrit commit e212a1145eb8625b4c193f6a1d3088b4873c7d1c Author: Bruce Griffith <Bruce.Griffith(a)se-eng.com> Date: Thu Sep 25 16:45:45 2014 -0600 AGESA stub 00730F01: Add config.h and kconfig.h to Makefile.inc The static library builder for the stub that interfaces to the AGESA binary does not include config.h and kconfig.h, so any header file changes that depend on Kconfig variables fail. Force these two system headers to be included in the build of any AGESA stub files. Signed-off-by: Bruce Griffith <Bruce.Griffith(a)se-eng.com> Change-Id: I2e8d38fa5aa21cc31b995ee3abe68ab3c3c55a68 --- src/vendorcode/amd/pi/00730F01/Makefile.inc | 41 ++++++++++++++++++----------- 1 file changed, 26 insertions(+), 15 deletions(-) diff --git a/src/vendorcode/amd/pi/00730F01/Makefile.inc b/src/vendorcode/amd/pi/00730F01/Makefile.inc index 2e24719..545d596 100644 --- a/src/vendorcode/amd/pi/00730F01/Makefile.inc +++ b/src/vendorcode/amd/pi/00730F01/Makefile.inc @@ -33,7 +33,7 @@ AGESA_ROOT = $(call strip_quotes,$(src)/../$(CONFIG_AGESA_BINARY_PI_PATH)) AGESA_INC = -I$(obj) -AGESA_INC += -Isrc/mainboard/$(MAINBOARDDIR) +AGESA_INC += -I$(src)/mainboard/$(MAINBOARDDIR) AGESA_INC += -I$(AGESA_ROOT)/binaryPI AGESA_INC += -I$(AGESA_ROOT) AGESA_INC += -I$(AGESA_ROOT)/Include @@ -49,29 +49,40 @@ AGESA_INC += -I$(AGESA_ROOT)/Proc/Fch/Common AGESA_INC += -I$(src)/southbridge/amd/agesa/hudson -AGESA_INC += -Isrc/arch/x86/include -AGESA_INC += -Isrc/include +AGESA_INC += -I$(src)/arch/x86/include +AGESA_INC += -I$(src)/include -CFLAGS_x86_32 += -march=amdfam10 -mno-3dnow -fno-zero-initialized-in-bss -fno-strict-aliasing +AGESA_CFLAGS += -march=amdfam10 -mno-3dnow -fno-zero-initialized-in-bss -fno-strict-aliasing +CFLAGS_x86_32 += $(AGESA_CFLAGS) export AGESA_ROOT := $(AGESA_ROOT) export AGESA_INC := $(AGESA_INC) export AGESA_CFLAGS := $(AGESA_CFLAGS) + CC_bootblock := $(CC_bootblock) $(AGESA_INC) $(AGESA_CFLAGS) CC_romstage := $(CC_romstage) $(AGESA_INC) $(AGESA_CFLAGS) CC_ramstage := $(CC_ramstage) $(AGESA_INC) $(AGESA_CFLAGS) CC_x86_32 := $(CC_x86_32) $(AGESA_INC) $(AGESA_CFLAGS) + ####################################################################### define create_agesa_cp_template # $1 AGESA source file # $2 AGESA copy-to location -$(agesa_obj_path)/$1: $2 - @printf " AGESA Copying $$(notdir $$(@F)) => $$(@D)\n" - cp -pf $$? $$(@D) - -libAgesa.$1: $(agesa_obj_path) $(agesa_obj_path)/$1 +$(agesa_src_copies_path)/$(notdir $2): $2 $(agesa_src_copies_path) + @printf " AGESA Copying $$(notdir $2) => $$(@D)\n" + if [ ! -r $(agesa_src_copies_path)/$(notdir $2) ]; then \ + cp -uf $2 $$(@D); \ + fi + +$(agesa_obj_path)/$1.libagesa.o: $(agesa_src_copies_path)/$(notdir $2) $(obj)/config.h $(agesa_obj_path) + @printf " CC $(subst $(agesa_obj_path)/,,$$(@))\n" + $(CC_libagesa) -c -MMD $(CFLAGS_libagesa) $(AGESA_CFLAGS) \ + $(AGESA_INC) \ + -include $(obj)/config.h -include $(src)/include/kconfig.h \ + -o $$@ \ + $(agesa_src_copies_path)/$(notdir $2) endef @@ -83,17 +94,17 @@ $(eval $(call create_class_compiler,libagesa,x86_32)) agesa_src_files := $(strip $(sort $(foreach file,$(strip $(agesa_raw_files)),$(call strip_quotes,$(file))))) agesa_obj_path := $(strip $(obj)/agesa) +agesa_src_copies_path := $(strip $(obj)/agesa) agesa_src_copies := $(strip $(foreach file,$(agesa_src_files),$(agesa_obj_path)/$(notdir $(file)))) agesa_obj_copies := $(strip $(agesa_src_copies:.c=.libagesa.o)) -$(agesa_obj_path): - mkdir $@ +$(agesa_src_path): + mkdir -p $@ -$(foreach file,$(strip $(agesa_src_files)),$(eval $(call create_agesa_cp_template,$(notdir $(file)),$(file)))) +$(agesa_obj_path): + mkdir -p $@ -$(agesa_obj_path)/%.libagesa.o: libAgesa.%.c - @printf " CC $(subst $(agesa_obj_path)/,,$(@))\n" - $(CC_libagesa) -MMD $(CFLAGS_libagesa) $(AGESA_INC) -c -o $@ $(agesa_obj_path)/$*.c +$(foreach file,$(strip $(agesa_src_files)),$(eval $(call create_agesa_cp_template,$(basename $(notdir $(file))),$(file)))) $(obj)/agesa/libagesa.00730F01.a: $(agesa_obj_copies) @printf " AGESA $(subst $(agesa_obj_path)/,,$(@))\n"

1 0

Patch set updated for coreboot: b3d234d i945 : Some fix for 945G/945GZ/945GC
by HAOUAS Elyes 26 Sep '14

26 Sep '14

HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6813 -gerrit commit b3d234d8d428ebd4277a851047dcc9c2030c3bff Author: Elyes <ehaouas(a)noos.fr> Date: Sun Aug 31 11:13:47 2014 +0200 i945 : Some fix for 945G/945GZ/945GC Change-Id: Icbf691f33222445e7fcd670e0c6e6c4a9dcaf0aa Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/northbridge/intel/i945/Kconfig | 3 ++- src/northbridge/intel/i945/acpi.c | 2 +- src/northbridge/intel/i945/early_init.c | 16 +++++++++--- src/northbridge/intel/i945/gma.c | 16 ++++++++++-- src/northbridge/intel/i945/northbridge.c | 8 +++++- src/northbridge/intel/i945/raminit.c | 42 +++++++++++++++++++------------- 6 files changed, 62 insertions(+), 25 deletions(-) diff --git a/src/northbridge/intel/i945/Kconfig b/src/northbridge/intel/i945/Kconfig index 360b2ab..99ea1fd 100644 --- a/src/northbridge/intel/i945/Kconfig +++ b/src/northbridge/intel/i945/Kconfig @@ -41,7 +41,8 @@ config BOOTBLOCK_NORTHBRIDGE_INIT config VGA_BIOS_ID string - default "8086,27a2" + default "8086,27a2" if NORTHBRIDGE_INTEL_SUBTYPE_I945GM + default "8086,2772" if NORTHBRIDGE_INTEL_SUBTYPE_I945GC config CHANNEL_XOR_RANDOMIZATION bool diff --git a/src/northbridge/intel/i945/acpi.c b/src/northbridge/intel/i945/acpi.c index e05bd58..46ca36a 100644 --- a/src/northbridge/intel/i945/acpi.c +++ b/src/northbridge/intel/i945/acpi.c @@ -36,7 +36,7 @@ unsigned long acpi_fill_mcfg(unsigned long current) u32 pciexbar_reg; int max_buses; - dev = dev_find_device(0x8086, 0x27a0, 0); + dev = dev_find_slot(0, PCI_DEVFN(0, 0)); if (!dev) return current; diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c index 08ce10b..f3f0f00 100644 --- a/src/northbridge/intel/i945/early_init.c +++ b/src/northbridge/intel/i945/early_init.c @@ -131,6 +131,9 @@ static void i945_detect_chipset(void) case 0: printk(BIOS_DEBUG, "up to DDR2-667"); break; + case 2: + printk(BIOS_DEBUG, "up to DDR2-667"); + break; case 3: printk(BIOS_DEBUG, "up to DDR2-533"); break; @@ -194,7 +197,7 @@ static void i945_setup_bars(void) /* Wait for MCH BAR to come up */ printk(BIOS_DEBUG, "Waiting for MCHBAR to come up..."); - if ((pci_read_config8(PCI_DEV(0, 0x0f, 0), 0xe6) & 0x2) == 0x00) { /* Bit 49 of CAPID0 */ + if ((pci_read_config8(PCI_DEV(0, 0x00, 0), 0xe6) & 0x2) == 0x00) { /* Bit 49 of CAPID0 */ do { reg8 = *(volatile u8 *)0xfed40000; } while (!(reg8 & 0x80)); @@ -226,6 +229,8 @@ static void i945_setup_egress_port(void) reg32 &= 0xffffff00; if ((MCHBAR32(CLKCFG) & 7) == 1) reg32 |= 0x0d; /* 533MHz */ + if ((MCHBAR32(CLKCFG) & 7) == 2) + reg32 |= 0x14; /* 800MHz */ if ((MCHBAR32(CLKCFG) & 7) == 3) reg32 |= 0x10; /* 667MHz */ EPBAR32(0x2c) = reg32; @@ -242,6 +247,11 @@ static void i945_setup_egress_port(void) EPBAR32(EPVC1IST + 4) = 0x009c009c; } + if ((MCHBAR32(CLKCFG) & 7) == 2) { /* 800MHz */ + EPBAR32(EPVC1IST + 0) = 0x00f000f0; + EPBAR32(EPVC1IST + 4) = 0x00f000f0; + } + if ((MCHBAR32(CLKCFG) & 7) == 3) { /* 667MHz */ EPBAR32(EPVC1IST + 0) = 0x00c000c0; EPBAR32(EPVC1IST + 4) = 0x00c000c0; @@ -425,9 +435,9 @@ static void i945_setup_dmi_rcrb(void) reg32 = DMIBAR32(0x204); reg32 &= ~0x3ff; #if 1 - reg32 |= 0x13f; /* for x4 DMI only */ + reg32 |= 0x13f; /* for x4 DMI only */ #else - reg32 |= 0x1e4; /* for x2 DMI only */ + reg32 |= 0x1e4; /* for x2 DMI only */ #endif DMIBAR32(0x204) = reg32; diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c index 9b0dbd2..b1c9a3b 100644 --- a/src/northbridge/intel/i945/gma.c +++ b/src/northbridge/intel/i945/gma.c @@ -499,6 +499,18 @@ static struct pci_operations gma_pci_ops = { .set_subsystem = gma_set_subsystem, }; +static const unsigned short i945_gma_func0_ids[] = { + 0x27a2, + 0x2772, + 0 +}; + +static const unsigned short i945_gma_func1_ids[] = { + 0x27a6, + 0x2776, + 0 +}; + static struct device_operations gma_func0_ops = { .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, @@ -524,11 +536,11 @@ static struct device_operations gma_func1_ops = { static const struct pci_driver i945_gma_func0_driver __pci_driver = { .ops = &gma_func0_ops, .vendor = PCI_VENDOR_ID_INTEL, - .device = 0x27a2, + .devices = i945_gma_func0_ids, }; static const struct pci_driver i945_gma_func1_driver __pci_driver = { .ops = &gma_func1_ops, .vendor = PCI_VENDOR_ID_INTEL, - .device = 0x27a6, + .devices = i945_gma_func1_ids, }; diff --git a/src/northbridge/intel/i945/northbridge.c b/src/northbridge/intel/i945/northbridge.c index 68d6d91..f666d49 100644 --- a/src/northbridge/intel/i945/northbridge.c +++ b/src/northbridge/intel/i945/northbridge.c @@ -267,10 +267,16 @@ static struct device_operations mc_ops = { .ops_pci = &intel_pci_ops, }; +static const unsigned short i945_pci_ids[] = { + 0x27a0, + 0x2770, + 0 +}; + static const struct pci_driver mc_driver __pci_driver = { .ops = &mc_ops, .vendor = PCI_VENDOR_ID_INTEL, - .device = 0x27a0, + .devices = i945_pci_ids, }; static void cpu_bus_init(device_t dev) diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c index e823bab..35ff7dc 100644 --- a/src/northbridge/intel/i945/raminit.c +++ b/src/northbridge/intel/i945/raminit.c @@ -121,29 +121,22 @@ static int memclk(void) return -1; } -#if CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GM static u16 fsbclk(void) { switch (MCHBAR32(CLKCFG) & 7) { - case 0: return 400; - case 1: return 533; - case 3: return 667; - default: printk(BIOS_DEBUG, "fsbclk: unknown register value %x\n", MCHBAR32(CLKCFG) & 7); - } - return 0xffff; -} -#elif CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GC -static u16 fsbclk(void) -{ - switch (MCHBAR32(CLKCFG) & 7) { - case 0: return 1066; + case 0: + #if CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GM + return 400; + #elif CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GC + return 1066; + #endif case 1: return 533; case 2: return 800; + case 3: return 667; default: printk(BIOS_DEBUG, "fsbclk: unknown register value %x\n", MCHBAR32(CLKCFG) & 7); } return 0xffff; } -#endif static int sdram_capabilities_max_supported_memory_frequency(void) { @@ -1965,6 +1958,7 @@ static void sdram_program_pll_settings(struct sys_info *sysinfo) case 400: MCHBAR8(CPCTL) = 0x90; break; /* FSB400 */ case 533: MCHBAR8(CPCTL) = 0x95; break; /* FSB533 */ case 667: MCHBAR8(CPCTL) = 0x8d; break; /* FSB667 */ + case 800: MCHBAR8(CPCTL) = 0x02; break; /* FSB800 */ } MCHBAR16(CPCTL) &= ~(1 << 11); @@ -2122,8 +2116,22 @@ static void sdram_program_memory_frequency(struct sys_info *sysinfo) switch (sysinfo->memory_frequency) { case 400: clkcfg |= (2 << 4); break; - case 533: clkcfg |= (3 << 4); break; - case 667: clkcfg |= (4 << 4); break; + case 533: + #if CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GM + clkcfg |= (3 << 4); + break; + #elif CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GC + clkcfg |= (2 << 4); + break; + #endif + case 667: + #if CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GM + clkcfg |= (4 << 4); + break; + #elif CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GC + clkcfg |= (3 << 4); + break; + #endif default: die("Target Memory Frequency Error"); } @@ -2264,7 +2272,7 @@ static void sdram_program_clock_crossing(void) 0x02010804, 0x00000000, /* DDR400 FSB800 */ 0x00010402, 0x00000000, /* DDR533 FSB800 */ - 0x04020180, 0x00000008, /* DDR667 FSB800 */ + 0x04020130, 0x00000008, /* DDR667 FSB800 */ 0x00020904, 0x00000000, /* DDR400 FSB1066 */ 0x02010804, 0x00000000, /* DDR533 FSB1066 */

1 0

New patch to review for coreboot: 2e868e6 AMD Trinity and Kabini: fix fan control
by WANG Siyuan 26 Sep '14

26 Sep '14

WANG Siyuan (wangsiyuanbuaa(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6981 -gerrit commit 2e868e6443d3a78ba5f5c06eb46111f22cc9e44a Author: WANG Siyuan <wangsiyuanbuaa(a)gmail.com> Date: Fri Sep 26 14:34:59 2014 +0800 AMD Trinity and Kabini: fix fan control enable_imc_thermal_zone doesn't work in agesawrapper_post_device. The fan can stop but can't run again. Move enable_imc_thermal_zone to write_acpi_tables can resolve this problem. Change-Id: I1b5bf3f6f7a66c60743f78918dc5442cdfc8b6e4 Signed-off-by: WANG Siyuan <SiYuan.Wang(a)amd.com> Signed-off-by: WANG Siyuan <wangsiyuanbuaa(a)gmail.com> --- src/cpu/amd/agesa/amd_late_init.c | 8 -------- src/mainboard/amd/olivehill/acpi_tables.c | 10 +++++++++- src/mainboard/amd/parmer/acpi_tables.c | 9 +++++++++ src/mainboard/amd/thatcher/acpi_tables.c | 9 +++++++++ 4 files changed, 27 insertions(+), 9 deletions(-) diff --git a/src/cpu/amd/agesa/amd_late_init.c b/src/cpu/amd/agesa/amd_late_init.c index c7927dc..cab03a3 100644 --- a/src/cpu/amd/agesa/amd_late_init.c +++ b/src/cpu/amd/agesa/amd_late_init.c @@ -27,9 +27,6 @@ #include <agesawrapper.h> #include <northbridge/amd/agesa/agesawrapper_call.h> -#if IS_ENABLED(CONFIG_HUDSON_IMC_FWM) -#include <southbridge/amd/agesa/hudson/imc.h> -#endif #if CONFIG_AMD_SB_CIMX #include <sb_cimx.h> #endif @@ -58,11 +55,6 @@ static void agesawrapper_post_device(void *unused) pci_write_config32(dev, 0x60, value); #endif -#if IS_ENABLED(CONFIG_HUDSON_IMC_FWM) - /* AMD AGESA does not enable thermal zone, so we enable it here. */ - enable_imc_thermal_zone(); -#endif - #if CONFIG_AMD_SB_CIMX sb_Late_Post(); #endif diff --git a/src/mainboard/amd/olivehill/acpi_tables.c b/src/mainboard/amd/olivehill/acpi_tables.c index a02b92c..b819970 100644 --- a/src/mainboard/amd/olivehill/acpi_tables.c +++ b/src/mainboard/amd/olivehill/acpi_tables.c @@ -27,8 +27,10 @@ #include <cpu/x86/msr.h> #include <cpu/amd/mtrr.h> #include <cpu/amd/amdfam16.h> - #include "agesawrapper.h" +#if IS_ENABLED(CONFIG_HUDSON_IMC_FWM) +#include <southbridge/amd/agesa/hudson/imc.h> +#endif extern const unsigned char AmlCode[]; @@ -282,5 +284,11 @@ unsigned long write_acpi_tables(unsigned long start) acpi_add_table(rsdp, ssdt); printk(BIOS_INFO, "ACPI: done.\n"); + +#if IS_ENABLED(CONFIG_HUDSON_IMC_FWM) + /* AMD AGESA does not enable thermal zone, so we enable it here. */ + enable_imc_thermal_zone(); +#endif + return current; } diff --git a/src/mainboard/amd/parmer/acpi_tables.c b/src/mainboard/amd/parmer/acpi_tables.c index e24ecc8..4f86205 100644 --- a/src/mainboard/amd/parmer/acpi_tables.c +++ b/src/mainboard/amd/parmer/acpi_tables.c @@ -29,6 +29,9 @@ #include <cpu/x86/msr.h> #include <cpu/amd/mtrr.h> #include <cpu/amd/amdfam15.h> +#if IS_ENABLED(CONFIG_HUDSON_IMC_FWM) +#include <southbridge/amd/agesa/hudson/imc.h> +#endif extern const unsigned char AmlCode[]; @@ -278,5 +281,11 @@ unsigned long write_acpi_tables(unsigned long start) acpi_add_table(rsdp, ssdt); printk(BIOS_INFO, "ACPI: done.\n"); + +#if IS_ENABLED(CONFIG_HUDSON_IMC_FWM) + /* AMD AGESA does not enable thermal zone, so we enable it here. */ + enable_imc_thermal_zone(); +#endif + return current; } diff --git a/src/mainboard/amd/thatcher/acpi_tables.c b/src/mainboard/amd/thatcher/acpi_tables.c index e24ecc8..4f86205 100644 --- a/src/mainboard/amd/thatcher/acpi_tables.c +++ b/src/mainboard/amd/thatcher/acpi_tables.c @@ -29,6 +29,9 @@ #include <cpu/x86/msr.h> #include <cpu/amd/mtrr.h> #include <cpu/amd/amdfam15.h> +#if IS_ENABLED(CONFIG_HUDSON_IMC_FWM) +#include <southbridge/amd/agesa/hudson/imc.h> +#endif extern const unsigned char AmlCode[]; @@ -278,5 +281,11 @@ unsigned long write_acpi_tables(unsigned long start) acpi_add_table(rsdp, ssdt); printk(BIOS_INFO, "ACPI: done.\n"); + +#if IS_ENABLED(CONFIG_HUDSON_IMC_FWM) + /* AMD AGESA does not enable thermal zone, so we enable it here. */ + enable_imc_thermal_zone(); +#endif + return current; }

1 0

Patch set updated for coreboot: 79c7ccc asrock/imb-a180/BiosCallOuts.c: Fix typo in temperatu*re* in comment
by Paul Menzel 26 Sep '14

26 Sep '14

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6684 -gerrit commit 79c7ccc8e003e988c88b1d137cad7afe62ef5e8d Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Sat Aug 16 07:31:19 2014 +0200 asrock/imb-a180/BiosCallOuts.c: Fix typo in temperatu*re* in comment Change-Id: If50685505143ccbd51098e92de72545c71b24892 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/mainboard/asrock/imb-a180/BiosCallOuts.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/asrock/imb-a180/BiosCallOuts.c b/src/mainboard/asrock/imb-a180/BiosCallOuts.c index a61c37f..70b3a70 100644 --- a/src/mainboard/asrock/imb-a180/BiosCallOuts.c +++ b/src/mainboard/asrock/imb-a180/BiosCallOuts.c @@ -160,7 +160,7 @@ static const CODEC_TBL_LIST CodecTableList[] = static void oem_fan_control(FCH_DATA_BLOCK *FchParams) { FCH_HWM_FAN_CTR oem_factl[5] = { - /*temperatuer input, fan mode, frequency, low_duty, med_duty, multiplier, lowtemp, medtemp, hightemp, LinearRange, LinearHoldCount */ + /* temperature input, fan mode, frequency, low_duty, med_duty, multiplier, lowtemp, medtemp, hightemp, LinearRange, LinearHoldCount */ /* imb_a180 FanOUT0 Fan header J32 */ {FAN_INPUT_INTERNAL_DIODE, (FAN_STEPMODE | FAN_POLARITY_HIGH), FREQ_100HZ, 40, 60, 0, 40, 65, 85, 0, 0}, /* imb_a180 FanOUT1 Fan header J31*/

1 0

New patch to review for coreboot: db4d998 libpayload: Build libpayload with debugging info turned up all the way.
by Isaac Christensen 26 Sep '14

26 Sep '14

Isaac Christensen (isaac.christensen(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6980 -gerrit commit db4d9984d529578686636b4552f3e1f515d5700a Author: Gabe Black <gabeblack(a)google.com> Date: Mon Dec 16 04:02:48 2013 -0800 libpayload: Build libpayload with debugging info turned up all the way. Pass -ggdb3 to the compiler when building libpayload, -ggdb so that it uses "the most expressive format available", and 3 so that the debugging level is set to 3, the highest value currently supported. The debugging information can be stripped by the payload consuming the library, and will definitely be stripped by cbfstool when installing that payload into an image. Change-Id: Ifd6c4a928fbb0b9fa9b3b2e0ea298abff31baf3b Signed-off-by: Gabe Black <gabeblack(a)google.com> Reviewed-on: https://chromium-review.googlesource.com/180252 Reviewed-by: Gabe Black <gabeblack(a)chromium.org> Tested-by: Gabe Black <gabeblack(a)chromium.org> Commit-Queue: Gabe Black <gabeblack(a)chromium.org> (cherry picked from commit dc04daaf099c53c57508b66e08f40945345a56ca) Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com> --- payloads/libpayload/Makefile.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/payloads/libpayload/Makefile.inc b/payloads/libpayload/Makefile.inc index d3b8787..ffe8371 100644 --- a/payloads/libpayload/Makefile.inc +++ b/payloads/libpayload/Makefile.inc @@ -53,7 +53,7 @@ subdirs-$(CONFIG_LP_CBFS) += libcbfs subdirs-$(CONFIG_LP_LZMA) += liblzma INCLUDES := -Iinclude -Iinclude/$(ARCHDIR-y) -I$(obj) -CFLAGS = $(EXTRA_CFLAGS) $(INCLUDES) -Os -pipe -nostdinc +CFLAGS = $(EXTRA_CFLAGS) $(INCLUDES) -Os -pipe -nostdinc -ggdb3 CFLAGS += -nostdlib -fno-builtin -ffreestanding -fomit-frame-pointer CFLAGS += -Wall -Wundef -Wstrict-prototypes -Wmissing-prototypes CFLAGS += -Wwrite-strings -Wredundant-decls -Wno-trigraphs

1 0

New patch to review for coreboot: 11c25dd AGESA stub 00730F01: Add config.h and kconfig.h to Makefile.inc
by Bruce Griffith 26 Sep '14

26 Sep '14

Bruce Griffith (Bruce.Griffith(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6979 -gerrit commit 11c25dd03a401f789aefcc0bc703715540b35843 Author: Bruce Griffith <Bruce.Griffith(a)se-eng.com> Date: Thu Sep 25 16:45:45 2014 -0600 AGESA stub 00730F01: Add config.h and kconfig.h to Makefile.inc The static library builder for the stub that interfaces to the AGESA binary does not include config.h and kconfig.h, so some header files changes that depend on Kconfig variables fail. Force these two system headers to be included in the build of any AGESA stub files. Signed-off-by: Bruce Griffith <Bruce.Griffith(a)se-eng.com> Change-Id: I2e8d38fa5aa21cc31b995ee3abe68ab3c3c55a68 --- src/vendorcode/amd/pi/00730F01/Makefile.inc | 41 ++++++++++++++++++----------- 1 file changed, 26 insertions(+), 15 deletions(-) diff --git a/src/vendorcode/amd/pi/00730F01/Makefile.inc b/src/vendorcode/amd/pi/00730F01/Makefile.inc index 2e24719..545d596 100644 --- a/src/vendorcode/amd/pi/00730F01/Makefile.inc +++ b/src/vendorcode/amd/pi/00730F01/Makefile.inc @@ -33,7 +33,7 @@ AGESA_ROOT = $(call strip_quotes,$(src)/../$(CONFIG_AGESA_BINARY_PI_PATH)) AGESA_INC = -I$(obj) -AGESA_INC += -Isrc/mainboard/$(MAINBOARDDIR) +AGESA_INC += -I$(src)/mainboard/$(MAINBOARDDIR) AGESA_INC += -I$(AGESA_ROOT)/binaryPI AGESA_INC += -I$(AGESA_ROOT) AGESA_INC += -I$(AGESA_ROOT)/Include @@ -49,29 +49,40 @@ AGESA_INC += -I$(AGESA_ROOT)/Proc/Fch/Common AGESA_INC += -I$(src)/southbridge/amd/agesa/hudson -AGESA_INC += -Isrc/arch/x86/include -AGESA_INC += -Isrc/include +AGESA_INC += -I$(src)/arch/x86/include +AGESA_INC += -I$(src)/include -CFLAGS_x86_32 += -march=amdfam10 -mno-3dnow -fno-zero-initialized-in-bss -fno-strict-aliasing +AGESA_CFLAGS += -march=amdfam10 -mno-3dnow -fno-zero-initialized-in-bss -fno-strict-aliasing +CFLAGS_x86_32 += $(AGESA_CFLAGS) export AGESA_ROOT := $(AGESA_ROOT) export AGESA_INC := $(AGESA_INC) export AGESA_CFLAGS := $(AGESA_CFLAGS) + CC_bootblock := $(CC_bootblock) $(AGESA_INC) $(AGESA_CFLAGS) CC_romstage := $(CC_romstage) $(AGESA_INC) $(AGESA_CFLAGS) CC_ramstage := $(CC_ramstage) $(AGESA_INC) $(AGESA_CFLAGS) CC_x86_32 := $(CC_x86_32) $(AGESA_INC) $(AGESA_CFLAGS) + ####################################################################### define create_agesa_cp_template # $1 AGESA source file # $2 AGESA copy-to location -$(agesa_obj_path)/$1: $2 - @printf " AGESA Copying $$(notdir $$(@F)) => $$(@D)\n" - cp -pf $$? $$(@D) - -libAgesa.$1: $(agesa_obj_path) $(agesa_obj_path)/$1 +$(agesa_src_copies_path)/$(notdir $2): $2 $(agesa_src_copies_path) + @printf " AGESA Copying $$(notdir $2) => $$(@D)\n" + if [ ! -r $(agesa_src_copies_path)/$(notdir $2) ]; then \ + cp -uf $2 $$(@D); \ + fi + +$(agesa_obj_path)/$1.libagesa.o: $(agesa_src_copies_path)/$(notdir $2) $(obj)/config.h $(agesa_obj_path) + @printf " CC $(subst $(agesa_obj_path)/,,$$(@))\n" + $(CC_libagesa) -c -MMD $(CFLAGS_libagesa) $(AGESA_CFLAGS) \ + $(AGESA_INC) \ + -include $(obj)/config.h -include $(src)/include/kconfig.h \ + -o $$@ \ + $(agesa_src_copies_path)/$(notdir $2) endef @@ -83,17 +94,17 @@ $(eval $(call create_class_compiler,libagesa,x86_32)) agesa_src_files := $(strip $(sort $(foreach file,$(strip $(agesa_raw_files)),$(call strip_quotes,$(file))))) agesa_obj_path := $(strip $(obj)/agesa) +agesa_src_copies_path := $(strip $(obj)/agesa) agesa_src_copies := $(strip $(foreach file,$(agesa_src_files),$(agesa_obj_path)/$(notdir $(file)))) agesa_obj_copies := $(strip $(agesa_src_copies:.c=.libagesa.o)) -$(agesa_obj_path): - mkdir $@ +$(agesa_src_path): + mkdir -p $@ -$(foreach file,$(strip $(agesa_src_files)),$(eval $(call create_agesa_cp_template,$(notdir $(file)),$(file)))) +$(agesa_obj_path): + mkdir -p $@ -$(agesa_obj_path)/%.libagesa.o: libAgesa.%.c - @printf " CC $(subst $(agesa_obj_path)/,,$(@))\n" - $(CC_libagesa) -MMD $(CFLAGS_libagesa) $(AGESA_INC) -c -o $@ $(agesa_obj_path)/$*.c +$(foreach file,$(strip $(agesa_src_files)),$(eval $(call create_agesa_cp_template,$(basename $(notdir $(file))),$(file)))) $(obj)/agesa/libagesa.00730F01.a: $(agesa_obj_copies) @printf " AGESA $(subst $(agesa_obj_path)/,,$(@))\n"

1 0

New patch to review for coreboot: 23c12ca AMD/Olive Hill Plus: Port IRQ routing to the mainboard
by Bruce Griffith 26 Sep '14

26 Sep '14

Bruce Griffith (Bruce.Griffith(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6978 -gerrit commit 23c12ca0a52036989ac667186933b820d6b8f425 Author: Bruce Griffith <Bruce.Griffith(a)se-eng.com> Date: Thu Sep 4 20:31:10 2014 -0600 AMD/Olive Hill Plus: Port IRQ routing to the mainboard Olive Hill needs the IRQ routing code ported to it. The file 00730F01/pci_devs.h was also missing a few devices so these were also added. The mptable.c file also needed to be updated to reflect the addition of the IRQ routing tables so that the MP Table can match the hardware IRQ routing. Change-Id: Id05157730af588665ee478fa567e5cc7ed1523e9 Signed-off-by: Bruce Griffith <Bruce.Griffith(a)se-eng.com> --- src/mainboard/amd/olivehillplus/agesawrapper.c | 15 +- src/mainboard/amd/olivehillplus/mainboard.c | 88 ++++++++++ src/mainboard/amd/olivehillplus/mptable.c | 231 +++++++++++-------------- src/northbridge/amd/agesa/00730F01/pci_devs.h | 50 ++++++ 4 files changed, 237 insertions(+), 147 deletions(-) diff --git a/src/mainboard/amd/olivehillplus/agesawrapper.c b/src/mainboard/amd/olivehillplus/agesawrapper.c index eecb45d..f88bfd5 100644 --- a/src/mainboard/amd/olivehillplus/agesawrapper.c +++ b/src/mainboard/amd/olivehillplus/agesawrapper.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2012 Advanced Micro Devices, Inc. + * 2014 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -524,15 +525,12 @@ AGESA_STATUS agesawrapper_amds3laterestore(void) #ifndef __PRE_RAM__ -extern UINT8 picr_data[0x54], intr_data[0x54]; - AGESA_STATUS agesawrapper_fchs3laterestore(void) { AGESA_STATUS status = AGESA_SUCCESS; FCH_DATA_BLOCK FchParams; AMD_CONFIG_PARAMS StdHeader; - UINT8 byte; StdHeader.HeapStatus = HEAP_SYSTEM_MEM; StdHeader.HeapBasePtr = GetHeapBase(&StdHeader) + 0x10; @@ -544,17 +542,6 @@ AGESA_STATUS agesawrapper_fchs3laterestore(void) FchParams.StdHeader = &StdHeader; s3_resume_init_data(&FchParams); FchInitS3LateRestore(&FchParams); - /* PIC IRQ routine */ - for (byte = 0x0; byte < sizeof(picr_data); byte ++) { - outb(byte, 0xC00); - outb(picr_data[byte], 0xC01); - } - - /* APIC IRQ routine */ - for (byte = 0x0; byte < sizeof(intr_data); byte ++) { - outb(byte | 0x80, 0xC00); - outb(intr_data[byte], 0xC01); - } return status; } diff --git a/src/mainboard/amd/olivehillplus/mainboard.c b/src/mainboard/amd/olivehillplus/mainboard.c index f7f4101..127666c 100644 --- a/src/mainboard/amd/olivehillplus/mainboard.c +++ b/src/mainboard/amd/olivehillplus/mainboard.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2012 Advanced Micro Devices, Inc. + * Copyright (C) 2014 Sage Electronic Engineering, LLC. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -22,12 +23,96 @@ #include <device/pci.h> #include <arch/io.h> #include <device/pci_def.h> +#include <southbridge/amd/amd_pci_util.h> #include <arch/acpi.h> #include "BiosCallOuts.h" #include <cpu/amd/agesa/s3_resume.h> #include "agesawrapper.h" #include <cpu/x86/msr.h> #include <cpu/amd/mtrr.h> +#include <southbridge/amd/agesa/hudson/hudson.h> +#include <southbridge/amd/agesa/hudson/pci_devs.h> +#include <northbridge/amd/agesa/00730F01/pci_devs.h> + +/*********************************************************** + * These arrays set up the FCH PCI_INTR registers 0xC00/0xC01. + * This table is responsible for physically routing the PIC and + * IOAPIC IRQs to the different PCI devices on the system. It + * is read and written via registers 0xC00/0xC01 as an + * Index/Data pair. These values are chipset and mainboard + * dependent and should be updated accordingly. + * + * These values are used by the PCI configuration space, + * MP Tables. TODO: Make ACPI use these values too. + */ +const u8 mainboard_picr_data[FCH_INT_TABLE_SIZE] = { + /* INTA# - INTH# */ + [0x00] = 0x03,0x04,0x05,0x07,0x0B,0x0A,0x0D,0x0C, + /* Misc-nil,0,1,2, INT from Serial irq */ + [0x08] = 0xFA,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F, + /* SCI, SMBUS0, ASF, HDA, FC, RSVD, PerMon, SD */ + [0x10] = 0x1F,0x1F,0x1F,0x03,0x1F,0x00,0x1F,0x1F, + /* IMC INT0 - 5 */ + [0x20] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F, + /* USB Devs 18/19/22 INTA-C */ + [0x30] = 0x05,0x04,0x05,0x04,0x04,0x05, + /* SATA */ + [0x41] = 0x04 +}; + +const u8 mainboard_intr_data[FCH_INT_TABLE_SIZE] = { + /* INTA# - INTH# */ + [0x00] = 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17, + /* Misc-nil,0,1,2, INT from Serial irq */ + [0x08] = 0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F, + /* SCI, SMBUS0, ASF, HDA, FC, GEC, PerMon, SD */ + [0x10] = 0x09,0x1F,0x1F,0x10,0x1F,0x10,0x1F,0x10,0x1F, + /* IMC INT0 - 5 */ + [0x20] = 0x05,0x1F,0x1F,0x1F,0x1F,0x1F, + /* USB Devs 18/19/20/22 INTA-C */ + [0x30] = 0x12,0x11,0x12,0x11,0x12,0x11,0x12, + /* SATA */ + [0x41] = 0x13 +}; + +/* + * This table defines the index into the picr/intr_data + * tables for each device. Any enabled device and slot + * that uses hardware interrupts should have an entry + * in this table to define its index into the FCH + * PCI_INTR register 0xC00/0xC01. This index will define + * the interrupt that it should use. Putting PIRQ_A into + * the PIN A index for a device will tell that device to + * use PIC IRQ 10 if it uses PIN A for its hardware INT. + */ +static const struct pirq_struct mainboard_pirq_data[] = { + /* {PCI_devfn, {PIN A, PIN B, PIN C, PIN D}}, */ + {GFX_DEVFN, {PIRQ_A, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* VGA: 01.0 */ + {ACTL_DEVFN,{PIRQ_NC, PIRQ_B, PIRQ_NC, PIRQ_NC}}, /* Audio: 01.1 */ + {NB_PCIE_PORT1_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D}}, /* x4 PCIe: 02.1 */ + {NB_PCIE_PORT2_DEVFN, {PIRQ_B, PIRQ_C, PIRQ_D, PIRQ_A}}, /* mPCIe: 02.2 */ + {NB_PCIE_PORT3_DEVFN, {PIRQ_C, PIRQ_D, PIRQ_A, PIRQ_B}}, /* NIC: 02.3 */ + {NB_PCIE_PORT4_DEVFN, {PIRQ_D, PIRQ_A, PIRQ_B, PIRQ_C}}, /* Edge: 02.4 */ + {NB_PCIE_PORT5_DEVFN, {PIRQ_E, PIRQ_F, PIRQ_G, PIRQ_H}}, /* Edge: 02.5 */ + {XHCI_DEVFN, {PIRQ_C, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* XHCI: 10.0 */ + {SATA_DEVFN, {PIRQ_SATA, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* SATA: 11.0 */ + {OHCI1_DEVFN, {PIRQ_OHCI1, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* OHCI1: 12.0 */ + {EHCI1_DEVFN, {PIRQ_NC, PIRQ_EHCI1, PIRQ_NC, PIRQ_NC}}, /* EHCI1: 12.2 */ + {OHCI2_DEVFN, {PIRQ_OHCI2, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* OHCI2: 13.0 */ + {EHCI2_DEVFN, {PIRQ_NC, PIRQ_EHCI2, PIRQ_NC, PIRQ_NC}}, /* EHCI2: 13.2 */ + {SMBUS_DEVFN, {PIRQ_SMBUS, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* SMBUS: 14.0 */ + {HDA_DEVFN, {PIRQ_HDA, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* HDA: 14.2 */ + {SD_DEVFN, {PIRQ_SD, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* SD: 14.7 */ +}; + +/* PIRQ Setup */ +static void pirq_setup(void) +{ + pirq_data_ptr = mainboard_pirq_data; + pirq_data_size = sizeof(mainboard_pirq_data) / sizeof(struct pirq_struct); + intr_data_ptr = mainboard_intr_data; + picr_data_ptr = mainboard_picr_data; +} /********************************************** * enable the dedicated function in mainboard. @@ -38,6 +123,9 @@ static void mainboard_enable(device_t dev) if (acpi_is_wakeup_s3()) agesawrapper_fchs3earlyrestore(); + + /* Initialize the PIRQ data structures for consumption */ + pirq_setup(); } struct chip_operations mainboard_ops = { diff --git a/src/mainboard/amd/olivehillplus/mptable.c b/src/mainboard/amd/olivehillplus/mptable.c index 73660e4..b6b3b7d 100644 --- a/src/mainboard/amd/olivehillplus/mptable.c +++ b/src/mainboard/amd/olivehillplus/mptable.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2012 Advanced Micro Devices, Inc. + * Copyright (C) 2014 Sage Electronic Engineering, LLC. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -27,159 +28,123 @@ #include <cpu/amd/amdfam15.h> #include <arch/cpu.h> #include <cpu/x86/lapic.h> -#include <southbridge/amd/agesa/hudson/hudson.h> /* pm_ioread() */ - -u8 picr_data[0x54] = { - 0x03,0x04,0x05,0x07,0x0B,0x0A,0x1F,0x1F,0xFA,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F, - 0x1F,0x1F,0x1F,0x03,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x05,0x04,0x05,0x04,0x04,0x05,0x04,0x05,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x04,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x03,0x04,0x05,0x07 -}; -u8 intr_data[0x54] = { - 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17,0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F, - 0x09,0x1F,0x1F,0x10,0x1F,0x10,0x1F,0x10,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x05,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x12,0x11,0x12,0x11,0x12,0x11,0x12,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x11,0x13,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x10,0x11,0x12,0x13 -}; - -static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned length) -{ - mc->mpc_length += length; - mc->mpc_entry_count++; -} - -static void my_smp_write_bus(struct mp_config_table *mc, - unsigned char id, const char *bustype) -{ - struct mpc_config_bus *mpc; - mpc = smp_next_mpc_entry(mc); - memset(mpc, '\0', sizeof(*mpc)); - mpc->mpc_type = MP_BUS; - mpc->mpc_busid = id; - memcpy(mpc->mpc_bustype, bustype, sizeof(mpc->mpc_bustype)); - smp_add_mpc_entry(mc, sizeof(*mpc)); -} +#include <southbridge/amd/amd_pci_util.h> +#include <drivers/generic/ioapic/chip.h> +#include <arch/ioapic.h> static void *smp_write_config_table(void *v) { struct mp_config_table *mc; int bus_isa; - u8 byte; - - /* - * By the time this function gets called, the IOAPIC registers - * have been written so they can be read to get the correct - * APIC ID and Version - */ - u8 ioapic_id = (io_apic_read(IO_APIC_ADDR, 0x00) >> 24); - u8 ioapic_ver = (io_apic_read(IO_APIC_ADDR, 0x01) & 0xFF); + /* Intialize the MP_Table */ mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); mptable_init(mc, LOCAL_APIC_ADDR); memcpy(mc->mpc_oem, "AMD ", 8); - smp_write_processors(mc); + /* + * Type 0: Processor Entries: + * LAPIC ID, LAPIC Version, CPU Flags:EN/BP, + * CPU Signature (Stepping, Model, Family), + * Feature Flags + */ + smp_write_processors(mc); - //mptable_write_buses(mc, NULL, &bus_isa); - my_smp_write_bus(mc, 0, "PCI "); - my_smp_write_bus(mc, 1, "PCI "); - bus_isa = 0x02; - my_smp_write_bus(mc, bus_isa, "ISA "); + /* Get bus Configuration */ + get_bus_conf(); + /* + * Type 1: bus Entries: + * bus ID, bus Type + */ + mptable_write_buses(mc, NULL, &bus_isa); + + /* + * Type 2: I/O APICs: + * APIC ID, Version, APIC Flags:EN, Address + */ + u8 ioapic_id = (io_apic_read(IO_APIC_ADDR, 0x00) >> 24); + u8 ioapic_ver = (io_apic_read(IO_APIC_ADDR, 0x01) & 0xFF); - /* I/O APICs: APIC ID Version State Address */ smp_write_ioapic(mc, ioapic_id, ioapic_ver, IO_APIC_ADDR); - smp_write_ioapic(mc, ioapic_id+1, 0x21, 0xFEC20000); - /* PIC IRQ routine */ - for (byte = 0x0; byte < sizeof(picr_data); byte ++) { - outb(byte, 0xC00); - outb(picr_data[byte], 0xC01); - } - - /* APIC IRQ routine */ - for (byte = 0x0; byte < sizeof(intr_data); byte ++) { - outb(byte | 0x80, 0xC00); - outb(intr_data[byte], 0xC01); - } - /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ -#define IO_LOCAL_INT(type, intr, apicid, pin) \ - smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); + /* + * Type 3: I/O Interrupt Table Entries: + * Int Type, Int Polarity, Int Level, Source bus ID, + * Source bus IRQ, Dest APIC ID, Dest PIN# + */ + mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0); /* PCI interrupts are level triggered, and are * associated with a specific bus/device/function tuple. */ -#define PCI_INT(bus, dev, int_sign, pin) \ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin)) - - /* Internal VGA */ - PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]); - PCI_INT(0x0, 0x01, 0x1, intr_data[0x03]); - - /* SMBUS */ - PCI_INT(0x0, 0x14, 0x0, 0x10); - - /* HD Audio */ - PCI_INT(0x0, 0x14, 0x0, intr_data[0x13]); - - /* USB */ - PCI_INT(0x0, 0x12, 0x0, intr_data[0x30]); - PCI_INT(0x0, 0x12, 0x1, intr_data[0x31]); - PCI_INT(0x0, 0x13, 0x0, intr_data[0x32]); - PCI_INT(0x0, 0x13, 0x1, intr_data[0x33]); - PCI_INT(0x0, 0x16, 0x0, intr_data[0x34]); - PCI_INT(0x0, 0x16, 0x1, intr_data[0x35]); - PCI_INT(0x0, 0x14, 0x2, intr_data[0x36]); - - /* sata */ - PCI_INT(0x0, 0x11, 0x0, intr_data[0x40]); - PCI_INT(0x0, 0x11, 0x0, intr_data[0x41]); - - /* on board NIC & Slot PCIE. */ - - /* PCI slots */ - device_t dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); - if (dev && dev->enabled) { - u8 bus_pci = dev->link_list->secondary; - /* PCI_SLOT 0. */ - PCI_INT(bus_pci, 0x5, 0x0, 0x14); - PCI_INT(bus_pci, 0x5, 0x1, 0x15); - PCI_INT(bus_pci, 0x5, 0x2, 0x16); - PCI_INT(bus_pci, 0x5, 0x3, 0x17); - - /* PCI_SLOT 1. */ - PCI_INT(bus_pci, 0x6, 0x0, 0x15); - PCI_INT(bus_pci, 0x6, 0x1, 0x16); - PCI_INT(bus_pci, 0x6, 0x2, 0x17); - PCI_INT(bus_pci, 0x6, 0x3, 0x14); - - /* PCI_SLOT 2. */ - PCI_INT(bus_pci, 0x7, 0x0, 0x16); - PCI_INT(bus_pci, 0x7, 0x1, 0x17); - PCI_INT(bus_pci, 0x7, 0x2, 0x14); - PCI_INT(bus_pci, 0x7, 0x3, 0x15); - } - - /* PCIe Lan*/ - PCI_INT(0x0, 0x06, 0x0, 0x13); - - /* FCH PCIe PortA */ - PCI_INT(0x0, 0x15, 0x0, 0x10); - /* FCH PCIe PortB */ - PCI_INT(0x0, 0x15, 0x1, 0x11); - /* FCH PCIe PortC */ - PCI_INT(0x0, 0x15, 0x2, 0x12); - /* FCH PCIe PortD */ - PCI_INT(0x0, 0x15, 0x3, 0x13); - - /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ - IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0); - IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1); +#define PCI_INT(bus, dev, fn, pin) \ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin)) + + /* APU Internal Graphic Device */ + PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[PIRQ_C]); + PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[PIRQ_D]); + + /* SMBUS / ACPI */ + PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[PIRQ_SMBUS]); + + /* Southbridge HD Audio */ + PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[PIRQ_HDA]); + + /* USB */ + PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[PIRQ_OHCI1]); + PCI_INT(0x0, 0x12, 0x1, intr_data_ptr[PIRQ_EHCI1]); + PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[PIRQ_OHCI2]); + PCI_INT(0x0, 0x13, 0x1, intr_data_ptr[PIRQ_EHCI2]); + PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[PIRQ_OHCI3]); + PCI_INT(0x0, 0x16, 0x1, intr_data_ptr[PIRQ_EHCI3]); + PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[PIRQ_OHCI4]); + + /* SATA */ + PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[PIRQ_SATA]); + + /* on board NIC & Slot PCIE */ + PCI_INT(0x1, 0x0, 0x0, intr_data_ptr[PIRQ_E]); + PCI_INT(0x2, 0x0, 0x0, intr_data_ptr[PIRQ_F]); + +// /* PCI slots */ +// device_t dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); +// if (dev && dev->enabled) { +// u8 bus_pci = dev->link_list->secondary; +// /* PCI_SLOT 0 */ +// PCI_INT(bus_pci, 0x5, 0x0, intr_data_ptr[PIRQ_E]); +// PCI_INT(bus_pci, 0x5, 0x1, intr_data_ptr[PIRQ_F]); +// PCI_INT(bus_pci, 0x5, 0x2, intr_data_ptr[PIRQ_G]); +// PCI_INT(bus_pci, 0x5, 0x3, intr_data_ptr[PIRQ_H]); +// +// /* PCI_SLOT 1 */ +// PCI_INT(bus_pci, 0x6, 0x0, intr_data_ptr[PIRQ_F]); +// PCI_INT(bus_pci, 0x6, 0x1, intr_data_ptr[PIRQ_G]); +// PCI_INT(bus_pci, 0x6, 0x2, intr_data_ptr[PIRQ_H]); +// PCI_INT(bus_pci, 0x6, 0x3, intr_data_ptr[PIRQ_E]); +// +// /* PCI_SLOT 2 */ +// PCI_INT(bus_pci, 0x7, 0x0, intr_data_ptr[PIRQ_G]); +// PCI_INT(bus_pci, 0x7, 0x1, intr_data_ptr[PIRQ_H]); +// PCI_INT(bus_pci, 0x7, 0x2, intr_data_ptr[PIRQ_E]); +// PCI_INT(bus_pci, 0x7, 0x3, intr_data_ptr[PIRQ_F]); +// +// PCI_INT(bus_pci, 0x0, 0x0, intr_data_ptr[PIRQ_C]); +// PCI_INT(bus_pci, 0x0, 0x1, intr_data_ptr[PIRQ_D]); +// PCI_INT(bus_pci, 0x0, 0x2, intr_data_ptr[PIRQ_E]); +// } +// +// /* PCIe Lan*/ +// PCI_INT(0x0, 0x06, 0x0, intr_data_ptr[PIRQ_D]); + + /*Local Ints: Type Polarity Trigger bus ID IRQ APIC ID PIN# */ +#define IO_LOCAL_INT(type, intr, apic, pin) \ + smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apic), (pin)); + + IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0); + IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1); + /* There is no extension information... */ /* Compute the checksums */ diff --git a/src/northbridge/amd/agesa/00730F01/pci_devs.h b/src/northbridge/amd/agesa/00730F01/pci_devs.h new file mode 100755 index 0000000..5bd5bb9 --- /dev/null +++ b/src/northbridge/amd/agesa/00730F01/pci_devs.h @@ -0,0 +1,50 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Sage Electronic Engineering, LLC. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _AMD_00730F01_PCI_DEVS_H_ +#define _AMD_00730F01_PCI_DEVS_H_ + +#define BUS0 0 + +/* Graphics and Display */ +#define GFX_DEV 0x1 +#define GFX_FUNC 0 +#define GFX_DEVFN PCI_DEVFN(GFX_DEV,GFX_FUNC) + +/* Internal Audio Controller */ +#define ACTL_FUNC 1 +#define ACTL_DEVFN PCI_DEVFN(GFX_DEV,ACTL_FUNC) + +/* PCIe Ports */ +#define NB_PCIE_PORT2_DEV 0x2 +#define NB_PCIE_FUNC0 0 +#define NB_PCIE_FUNC1 1 +#define NB_PCIE_FUNC2 2 +#define NB_PCIE_FUNC3 3 +#define NB_PCIE_FUNC4 4 +#define NB_PCIE_FUNC5 5 +#define NB_PCIE_PORT_DEVID 0x1439 +#define NB_PCIE_PORT0_DEVFN PCI_DEVFN(NB_PCIE_PORT2_DEV,NB_PCIE_FUNC0) +#define NB_PCIE_PORT1_DEVFN PCI_DEVFN(NB_PCIE_PORT2_DEV,NB_PCIE_FUNC1) +#define NB_PCIE_PORT2_DEVFN PCI_DEVFN(NB_PCIE_PORT2_DEV,NB_PCIE_FUNC2) +#define NB_PCIE_PORT3_DEVFN PCI_DEVFN(NB_PCIE_PORT2_DEV,NB_PCIE_FUNC3) +#define NB_PCIE_PORT4_DEVFN PCI_DEVFN(NB_PCIE_PORT2_DEV,NB_PCIE_FUNC4) +#define NB_PCIE_PORT5_DEVFN PCI_DEVFN(NB_PCIE_PORT2_DEV,NB_PCIE_FUNC5) + +#endif /* _AMD_00730F01_PCI_DEVS_H_ */

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coreboot-gerrit September 2014