coreboot-gerrit September 2014

coreboot-gerrit@coreboot.org

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580 discussions

New patch to review for coreboot: a31afc9 Remove stale char[] initialization causing unaligned memory access
by Isaac Christensen 25 Sep '14

25 Sep '14

Isaac Christensen (isaac.christensen(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6974 -gerrit commit a31afc9747186ebcd9e4b302f53e7516e3ea1c07 Author: Marcelo Povoa <marcelogp(a)chromium.org> Date: Fri Feb 14 15:42:49 2014 -0800 Remove stale char[] initialization causing unaligned memory access This throws an alignment fault when run in ARMv8 Foundation model and seems unnecessary, so remove it. Change-Id: I2e3aa54502c292958ba44ff4e2e71c27653f2e1a Signed-off-by: Marcelo Povoa <marcelogp(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/186744 Reviewed-by: David Hendricks <dhendrix(a)chromium.org> (cherry picked from commit 57510d553c56ca5dfb4765836ddb901744e29e20) Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com> --- src/device/device_util.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/device/device_util.c b/src/device/device_util.c index 4526c48..d5466cb 100644 --- a/src/device/device_util.c +++ b/src/device/device_util.c @@ -796,7 +796,7 @@ void print_resource_tree(struct device *root, int debug_level, const char *msg) void show_devs_tree(struct device *dev, int debug_level, int depth, int linknum) { - char depth_str[20] = ""; + char depth_str[20]; int i; struct device *sibling; struct bus *link;

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New patch to review for coreboot: 8790956 cbmem: Fix 64-bit pointer related casts in dynamic_cbmem.c
by Isaac Christensen 25 Sep '14

25 Sep '14

Isaac Christensen (isaac.christensen(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6973 -gerrit commit 8790956718b91446d0d9e69977d81d211821ccc7 Author: Marcelo Povoa <marcelogp(a)chromium.org> Date: Mon Feb 24 10:00:26 2014 -0800 cbmem: Fix 64-bit pointer related casts in dynamic_cbmem.c Change-Id: I7a382d42e1552d13b1feffc37848674f304adee2 Signed-off-by: Marcelo Povoa <marcelogp(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/187726 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-by: Stefan Reinauer <reinauer(a)chromium.org> Reviewed-by: David Hendricks <dhendrix(a)chromium.org> (cherry picked from commit 57bbca93f12e0ddbde3e673070483e13521dfbdd) Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com> --- src/lib/dynamic_cbmem.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/src/lib/dynamic_cbmem.c b/src/lib/dynamic_cbmem.c index 1382f1d..3a78316 100644 --- a/src/lib/dynamic_cbmem.c +++ b/src/lib/dynamic_cbmem.c @@ -107,7 +107,7 @@ static inline void *get_root(void) if (pointer->magic != CBMEM_POINTER_MAGIC) return NULL; - return (void *)pointer->root; + return (void *)(uintptr_t)pointer->root; } static inline void cbmem_entry_assign(struct cbmem_entry *entry, @@ -188,9 +188,9 @@ static inline int cbmem_fail_recovery(void) static int validate_entries(struct cbmem_root *root) { unsigned int i; - u32 current_end; + uintptr_t current_end; - current_end = (u32)get_top_aligned(); + current_end = (uintptr_t)get_top_aligned(); printk(BIOS_DEBUG, "CBMEM: recovering %d/%d entries from root @ %p\n", root->num_entries, root->max_entries, root); @@ -270,14 +270,14 @@ int cbmem_recovery(int is_wakeup) static void *cbmem_base(void) { struct cbmem_root *root; - u32 low_addr; + uintptr_t low_addr; root = get_root(); if (root == NULL) return NULL; - low_addr = (u32)root; + low_addr = (uintptr_t)root; /* Assume the lowest address is the last one added. */ if (root->num_entries > 0) { @@ -411,7 +411,7 @@ u64 cbmem_entry_size(const struct cbmem_entry *entry) void *cbmem_entry_start(const struct cbmem_entry *entry) { - return (void *)entry->start; + return (void *)(uintptr_t)entry->start; }

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Patch set updated for coreboot: 072cdd2 soc/qualcomm: Add generic support skeleton for ipq806x
by Isaac Christensen 25 Sep '14

25 Sep '14

Isaac Christensen (isaac.christensen(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6963 -gerrit commit 072cdd26a5f89cd9b9dd8b31f3dd725486c39214 Author: Furquan Shaikh <furquan(a)google.com> Date: Wed Mar 19 14:29:48 2014 -0700 soc/qualcomm: Add generic support skeleton for ipq806x Skeleton for soc ipq806x Old-Change-Id: I92a8d592d762f59665e15d1a7fc6cc73dc74c296 Signed-off-by: Furquan Shaikh <furquan(a)google.com> Reviewed-on: https://chromium-review.googlesource.com/190723 Reviewed-by: Vadim Bendebury <vbendeb(a)chromium.org> Commit-Queue: Furquan Shaikh <furquan(a)chromium.org> Tested-by: Furquan Shaikh <furquan(a)chromium.org> (cherry picked from commit e71d45733d86e77717fd2f592ef06113246db911) soc/ipq806x: Disable LPAE mode. LPAE (large physical address extension) is not available on this SOC core, do not enable it. Old-Change-Id: I9e9ad1aeaf613f04987c0c306a574085042d0e7b Signed-off-by: Deepa Dinamani <deepad(a)codeaurora.com> Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/198023 Reviewed-by: deepa dinamani <deepad(a)quicinc.com> (cherry picked from commit e6e12c39efd54e4fcbd444134bf30e211948a71b) Squashed 2 commits for the Qualcomm ipq806x SOC. Change-Id: I14521d3b2844ddd68112882de81453ce8d19fc16 Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com> --- src/soc/Kconfig | 3 ++- src/soc/Makefile.inc | 1 + src/soc/qualcomm/Kconfig | 1 + src/soc/qualcomm/Makefile.inc | 1 + src/soc/qualcomm/ipq806x/Kconfig | 22 ++++++++++++++++++++++ src/soc/qualcomm/ipq806x/Makefile.inc | 8 ++++++++ src/soc/qualcomm/ipq806x/cbfs.c | 26 ++++++++++++++++++++++++++ src/soc/qualcomm/ipq806x/timer.c | 28 ++++++++++++++++++++++++++++ 8 files changed, 89 insertions(+), 1 deletion(-) diff --git a/src/soc/Kconfig b/src/soc/Kconfig index 5903a57..53d7b90 100644 --- a/src/soc/Kconfig +++ b/src/soc/Kconfig @@ -1,3 +1,4 @@ source src/soc/intel/Kconfig source src/soc/nvidia/Kconfig -source src/soc/samsung/Kconfig \ No newline at end of file +source src/soc/qualcomm/Kconfig +source src/soc/samsung/Kconfig diff --git a/src/soc/Makefile.inc b/src/soc/Makefile.inc index b36d5be..6939346 100644 --- a/src/soc/Makefile.inc +++ b/src/soc/Makefile.inc @@ -3,4 +3,5 @@ ################################################################################ subdirs-y += intel subdirs-y += nvidia +subdirs-y += qualcomm subdirs-y += samsung diff --git a/src/soc/qualcomm/Kconfig b/src/soc/qualcomm/Kconfig new file mode 100644 index 0000000..b7a12d4 --- /dev/null +++ b/src/soc/qualcomm/Kconfig @@ -0,0 +1 @@ +source src/soc/qualcomm/ipq806x/Kconfig diff --git a/src/soc/qualcomm/Makefile.inc b/src/soc/qualcomm/Makefile.inc new file mode 100644 index 0000000..06b2f2f --- /dev/null +++ b/src/soc/qualcomm/Makefile.inc @@ -0,0 +1 @@ +subdirs-$(CONFIG_SOC_QC_IPQ806X) += ipq806x diff --git a/src/soc/qualcomm/ipq806x/Kconfig b/src/soc/qualcomm/ipq806x/Kconfig new file mode 100644 index 0000000..fcf8ccd --- /dev/null +++ b/src/soc/qualcomm/ipq806x/Kconfig @@ -0,0 +1,22 @@ +config SOC_QC_IPQ806X + select ARCH_BOOTBLOCK_ARMV4 + select ARCH_ROMSTAGE_ARMV7 + select ARCH_RAMSTAGE_ARMV7 + bool + default n + +if SOC_QC_IPQ806X + +config BOOTBLOCK_ROM_OFFSET + hex + default 0x0 + +config CBFS_HEADER_ROM_OFFSET + hex "offset of master CBFS header in ROM" + default 0x18000 + +config CBFS_ROM_OFFSET + hex "offset of CBFS data in ROM" + default 0x18080 + +endif diff --git a/src/soc/qualcomm/ipq806x/Makefile.inc b/src/soc/qualcomm/ipq806x/Makefile.inc new file mode 100644 index 0000000..be37581 --- /dev/null +++ b/src/soc/qualcomm/ipq806x/Makefile.inc @@ -0,0 +1,8 @@ +bootblock-y += cbfs.c +bootblock-y += timer.c + +romstage-y += cbfs.c +romstage-y += timer.c + +ramstage-y += cbfs.c +ramstage-y += timer.c diff --git a/src/soc/qualcomm/ipq806x/cbfs.c b/src/soc/qualcomm/ipq806x/cbfs.c new file mode 100644 index 0000000..97ae548 --- /dev/null +++ b/src/soc/qualcomm/ipq806x/cbfs.c @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + +#include <cbfs.h> /* This driver serves as a CBFS media source. */ + +int init_default_cbfs_media(struct cbfs_media *media) +{ + return 0; +} diff --git a/src/soc/qualcomm/ipq806x/timer.c b/src/soc/qualcomm/ipq806x/timer.c new file mode 100644 index 0000000..c4e250e --- /dev/null +++ b/src/soc/qualcomm/ipq806x/timer.c @@ -0,0 +1,28 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <timer.h> +#include <delay.h> +#include <thread.h> + +void init_timer(void) +{ +} +

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Patch set updated for coreboot: 912c99d Peppy/Falco: always use native graphics
by Isaac Christensen 25 Sep '14

25 Sep '14

Isaac Christensen (isaac.christensen(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6912 -gerrit commit 912c99dcfe22dc4b8a2cc23615b3cd92ab139116 Author: Ronald G. Minnich <rminnich(a)google.com> Date: Mon Dec 30 09:09:31 2013 -0800 Peppy/Falco: always use native graphics The products having shipped, and living in their own branch, we might as well enable native graphics since: 1. it works 2. it removes a blob and the only good blob is a dead blob 3. it's faster 4. when we have problems, we can diagnose them more easily 5. when we get to newer kernels the boot time will magically get faster as the driver realizes graphics is running. Where else do you get a 3-4 second speedup for free? Change-Id: Iad937320e7f46b1de7ab00dace04115a7f182ed1 Signed-off-by: Ronald G. Minnich <rminnich(a)google.com> Reviewed-on: https://chromium-review.googlesource.com/181225 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Commit-Queue: Ronald Minnich <rminnich(a)chromium.org> Tested-by: Ronald Minnich <rminnich(a)chromium.org> (cherry picked from commit 7b567d87a9fcf6736e90e730bd052e4465d57bdf) Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com> --- src/mainboard/google/falco/Kconfig | 1 + src/mainboard/google/peppy/Kconfig | 1 + 2 files changed, 2 insertions(+) diff --git a/src/mainboard/google/falco/Kconfig b/src/mainboard/google/falco/Kconfig index 3323fc2..ba39c7d 100644 --- a/src/mainboard/google/falco/Kconfig +++ b/src/mainboard/google/falco/Kconfig @@ -19,6 +19,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select EXTERNAL_MRC_BLOB select MONOTONIC_TIMER_MSR select MAINBOARD_HAS_NATIVE_VGA_INIT + select MAINBOARD_DO_NATIVE_VGA_INIT select INTEL_INT15 config VBOOT_RAMSTAGE_INDEX diff --git a/src/mainboard/google/peppy/Kconfig b/src/mainboard/google/peppy/Kconfig index 2343b8d..f991903 100644 --- a/src/mainboard/google/peppy/Kconfig +++ b/src/mainboard/google/peppy/Kconfig @@ -19,6 +19,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select EXTERNAL_MRC_BLOB select MONOTONIC_TIMER_MSR select MAINBOARD_HAS_NATIVE_VGA_INIT + select MAINBOARD_DO_NATIVE_VGA_INIT select INTEL_DP select INTEL_DDI select INTEL_INT15

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Patch merged into coreboot/master: 6481cfb peppy and falco: set panel power timings in northbridge, using devicetree, not mainboards
by gerrit＠coreboot.org 25 Sep '14

25 Sep '14

the following patch was just integrated into master: commit 6481cfb15d62784b87eabe972a742fa1e3da129d Author: Ronald G. Minnich <rminnich(a)google.com> Date: Tue Dec 17 15:21:54 2013 -0800 peppy and falco: set panel power timings in northbridge, using devicetree, not mainboards Historically we had set panel timing in the mainboard gma code. This goes back to the replay-attack video startup. We can let the haswell gma code set these values from the device tree settings. Change-Id: If32150d2857241ca2d2c88880086f49d25815d76 Signed-off-by: Ronald G. Minnich <rminnich(a)google.com> Reviewed-on: https://chromium-review.googlesource.com/180521 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Commit-Queue: Ronald Minnich <rminnich(a)chromium.org> Tested-by: Ronald Minnich <rminnich(a)chromium.org> (cherry picked from commit 406eab3ca6a9bc59382866817786bf96bbb19d56) Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com> Reviewed-on: http://review.coreboot.org/6911 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> See http://review.coreboot.org/6911 for details. -gerrit

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Patch merged into coreboot/master: e9e3189 libpayload: Add missing cache API stub to x86
by gerrit＠coreboot.org 25 Sep '14

25 Sep '14

the following patch was just integrated into master: commit e9e31892d20646be1bba0ee4175344f37e43469a Author: Julius Werner <jwerner(a)chromium.org> Date: Tue Jan 14 13:45:37 2014 -0800 libpayload: Add missing cache API stub to x86 This patch adds another cache invalidation stub to the x86 arch to make it usable in common code. This whole stuff should probably be redesigned anyway but I just want to get it working and unblock my CL for now... more cleanups coming later. Change-Id: I2e8bdd8aa0e6723209384c24042f053f2e993fe6 Signed-off-by: Julius Werner <jwerner(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/182534 Reviewed-by: Vincent Palatin <vpalatin(a)chromium.org> (cherry picked from commit cafce5182a7a2a9ce17ad40d9d893a40ebd5aafd) Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com> Reviewed-on: http://review.coreboot.org/6919 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> See http://review.coreboot.org/6919 for details. -gerrit

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Patch merged into coreboot/master: 04bfbf5 pit: Rename pit to peach_pit.
by gerrit＠coreboot.org 25 Sep '14

25 Sep '14

the following patch was just integrated into master: commit 04bfbf50950df6ef78aa354698b226928a4024bc Author: Gabe Black <gabeblack(a)google.com> Date: Wed Jan 22 20:50:27 2014 -0800 pit: Rename pit to peach_pit. The name pit goes by in many places in chromeos is peach_pit, where peach is the base name and pit is the name of this particular variant. To make it easier to work with within chromeos and to make the board names a little less ambiguous, this change renames the pit board to peach_pit, and from Pit to Peach Pit. Change-Id: I51c89ba3785cf4cb9769a989b1cac71bcd1b0a05 Signed-off-by: Gabe Black <gabeblack(a)google.com> Reviewed-on: https://chromium-review.googlesource.com/183552 Reviewed-by: David Hendricks <dhendrix(a)chromium.org> Commit-Queue: Gabe Black <gabeblack(a)chromium.org> Tested-by: Gabe Black <gabeblack(a)chromium.org> (cherry picked from commit cbbe1e9f04e34436a1bbae28628e0b5630d41054) Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com> Reviewed-on: http://review.coreboot.org/6928 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> See http://review.coreboot.org/6928 for details. -gerrit

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New patch to review for coreboot: 7914e70 intel/minnowmax: Enable S3 suspend/resume
by Mohan D'Costa 25 Sep '14

25 Sep '14

Mohan D'Costa (mohan(a)ndr.co.jp) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6972 -gerrit commit 7914e70ca7da0d2150efac0810e9c18d252b83f9 Author: Mohan D'Costa <mohan(a)ndr.co.jp> Date: Thu Sep 25 18:17:08 2014 +0900 intel/minnowmax: Enable S3 suspend/resume This enables S3 Suspend / Resume support for MinnowMax board using Intel's Bay Trail FSP Tested resume from Power Button and Magic Packet. Change-Id: I021122a68c05f2e725cabb8f3946249afe802bbe Signed-off-by: Mohan D'Costa <mohan(a)ndr.co.jp> --- src/mainboard/intel/minnowmax/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/src/mainboard/intel/minnowmax/Kconfig b/src/mainboard/intel/minnowmax/Kconfig index 0e83d5a..229172c 100644 --- a/src/mainboard/intel/minnowmax/Kconfig +++ b/src/mainboard/intel/minnowmax/Kconfig @@ -27,6 +27,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_OPTION_TABLE select OVERRIDE_MRC_CACHE_LOC select TSC_MONOTONIC_TIMER + select HAVE_ACPI_RESUME config MAINBOARD_DIR string

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Patch set updated for coreboot: 7ee3e9f intel/fsp_baytrail: Add S3 suspend/resume Support
by Mohan D'Costa 25 Sep '14

25 Sep '14

Mohan D'Costa (mohan(a)ndr.co.jp) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6937 -gerrit commit 7ee3e9f83cfd0a2e549b18e6c7c693387b4d356c Author: Mohan D'Costa <mohan(a)ndr.co.jp> Date: Thu Sep 18 15:57:06 2014 +0900 intel/fsp_baytrail: Add S3 suspend/resume Support This adds S3 Suspend / Resume support to Intel's Bay Trail FSP It is based on the "src/soc/intel/baytrail/romstage/romstage.c" implementation. Change-Id: If0011068eb7290d1b764c5c4b12c17375fb69008 Signed-off-by: Mohan D'Costa <mohan(a)ndr.co.jp> --- src/drivers/intel/fsp/Kconfig | 1 + src/soc/intel/fsp_baytrail/acpi/sleepstates.asl | 3 + src/soc/intel/fsp_baytrail/baytrail/romstage.h | 1 + src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c | 33 ++++++++++- src/soc/intel/fsp_baytrail/ramstage.c | 32 +++++++++++ src/soc/intel/fsp_baytrail/romstage/romstage.c | 68 ++++++++++++++++++++++- 6 files changed, 133 insertions(+), 5 deletions(-) diff --git a/src/drivers/intel/fsp/Kconfig b/src/drivers/intel/fsp/Kconfig index 5e44046..2d41365 100644 --- a/src/drivers/intel/fsp/Kconfig +++ b/src/drivers/intel/fsp/Kconfig @@ -63,6 +63,7 @@ config ENABLE_FSP_FAST_BOOT config ENABLE_MRC_CACHE bool + default y if HAVE_ACPI_RESUME default n help Enabling this feature will cause MRC data to be cached in NV storage. diff --git a/src/soc/intel/fsp_baytrail/acpi/sleepstates.asl b/src/soc/intel/fsp_baytrail/acpi/sleepstates.asl index 65339cc..12e359a 100644 --- a/src/soc/intel/fsp_baytrail/acpi/sleepstates.asl +++ b/src/soc/intel/fsp_baytrail/acpi/sleepstates.asl @@ -21,5 +21,8 @@ Name(\_S0, Package(){0x0,0x0,0x0,0x0}) // Name(\_S1, Package(){0x1,0x1,0x0,0x0}) +#if CONFIG_HAVE_ACPI_RESUME +Name(\_S3, Package(){0x5,0x5,0x0,0x0}) +#endif Name(\_S4, Package(){0x6,0x6,0x0,0x0}) Name(\_S5, Package(){0x7,0x7,0x0,0x0}) diff --git a/src/soc/intel/fsp_baytrail/baytrail/romstage.h b/src/soc/intel/fsp_baytrail/baytrail/romstage.h index 8feab8a..1ceb4cf 100644 --- a/src/soc/intel/fsp_baytrail/baytrail/romstage.h +++ b/src/soc/intel/fsp_baytrail/baytrail/romstage.h @@ -33,6 +33,7 @@ void report_platform_info(void); #include <fsptypes.h> void romstage_main_continue(EFI_STATUS status, void *hob_list_ptr); +uint32_t chipset_prev_sleep_state(uint32_t clear); #define NUM_ROMSTAGE_TS 4 diff --git a/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c b/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c index 60a1f7a..83a1100 100644 --- a/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c +++ b/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c @@ -28,7 +28,11 @@ #include <baytrail/pci_devs.h> #include <drivers/intel/fsp/fsp_util.h> #include "../chip.h" +#include <arch/io.h> #include <baytrail/reset.h> +#include <baytrail/pmc.h> +#include <baytrail/acpi.h> +#include <baytrail/iomap.h> #ifdef __PRE_RAM__ #include <baytrail/romstage.h> @@ -307,18 +311,43 @@ void chipset_fsp_early_init(FSP_INIT_PARAMS *pFspInitParams, FSP_INFO_HEADER *fsp_ptr) { FSP_INIT_RT_BUFFER *pFspRtBuffer = pFspInitParams->RtBufferPtr; + uint32_t prev_sleep_state; + + /* Get previous sleep state but don't clear */ + prev_sleep_state = chipset_prev_sleep_state(0); + printk(BIOS_INFO, "prev_sleep_state = S%d\n", prev_sleep_state); /* Initialize the UPD Data */ GetUpdDefaultFromFsp (fsp_ptr, pFspRtBuffer->Common.UpdDataRgnPtr); ConfigureDefaultUpdData(pFspRtBuffer->Common.UpdDataRgnPtr); pFspInitParams->NvsBufferPtr = NULL; - pFspRtBuffer->Common.BootMode = BOOT_WITH_FULL_CONFIGURATION; -#if IS_ENABLED(CONFIG_ENABLE_FSP_FAST_BOOT) +#if IS_ENABLED(CONFIG_ENABLE_MRC_CACHE) /* Find the fastboot cache that was saved in the ROM */ pFspInitParams->NvsBufferPtr = find_and_set_fastboot_cache(); #endif + if (prev_sleep_state == 3) { + /* S3 resume */ + if ( pFspInitParams->NvsBufferPtr == NULL) { + /* If waking from S3 and no cache then. */ + printk(BIOS_WARNING, "No MRC cache found in S3 resume path.\n"); + post_code(POST_RESUME_FAILURE); + /* Clear Sleep Type */ + outl(inl(ACPI_BASE_ADDRESS + PM1_CNT) & + ~(SLP_TYP), ACPI_BASE_ADDRESS + PM1_CNT); + /* Reboot */ + printk(BIOS_WARNING,"Rebooting..\n" ); + warm_reset(); + /* Should not reach here.. */ + die("Reboot System\n"); + } + pFspRtBuffer->Common.BootMode = BOOT_ON_S3_RESUME; + } else { + /* Not S3 resume */ + pFspRtBuffer->Common.BootMode = BOOT_WITH_FULL_CONFIGURATION; + } + return; } diff --git a/src/soc/intel/fsp_baytrail/ramstage.c b/src/soc/intel/fsp_baytrail/ramstage.c index e231701..814b16e 100644 --- a/src/soc/intel/fsp_baytrail/ramstage.c +++ b/src/soc/intel/fsp_baytrail/ramstage.c @@ -18,6 +18,7 @@ */ #include <arch/cpu.h> +#include <arch/acpi.h> #include <console/console.h> #include <cpu/intel/microcode.h> #include <cpu/x86/cr.h> @@ -25,10 +26,12 @@ #include <device/device.h> #include <device/pci_def.h> #include <device/pci_ops.h> +#include <romstage_handoff.h> #include <stdlib.h> #include <baytrail/gpio.h> #include <baytrail/lpc.h> +#include <baytrail/nvs.h> #include <baytrail/msr.h> #include <baytrail/pattrs.h> #include <baytrail/pci_devs.h> @@ -123,6 +126,32 @@ static void fill_in_pattrs(void) } +static inline void set_acpi_sleep_type(int val) +{ +#if CONFIG_HAVE_ACPI_RESUME + acpi_slp_type = val; +#endif +} + +static void s3_resume_prepare(void) +{ + global_nvs_t *gnvs; + struct romstage_handoff *romstage_handoff; + + gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(global_nvs_t)); + + romstage_handoff = cbmem_find(CBMEM_ID_ROMSTAGE_INFO); + if (romstage_handoff == NULL || romstage_handoff->s3_resume == 0) { + if (gnvs != NULL) { + memset(gnvs, 0, sizeof(global_nvs_t)); + } + set_acpi_sleep_type(0); + return; + } + + set_acpi_sleep_type(3); +} + void baytrail_init_pre_device(void) { struct soc_gpio_config *config; @@ -132,6 +161,9 @@ void baytrail_init_pre_device(void) /* Allow for SSE instructions to be executed. */ write_cr4(read_cr4() | CR4_OSFXSR | CR4_OSXMMEXCPT); + /* Indicate S3 resume to rest of ramstage. */ + s3_resume_prepare(); + /* Get GPIO initial states from mainboard */ config = mainboard_get_gpios(); setup_soc_gpios(config); diff --git a/src/soc/intel/fsp_baytrail/romstage/romstage.c b/src/soc/intel/fsp_baytrail/romstage/romstage.c index a63156f..0c72b98 100644 --- a/src/soc/intel/fsp_baytrail/romstage/romstage.c +++ b/src/soc/intel/fsp_baytrail/romstage/romstage.c @@ -24,6 +24,7 @@ #include <arch/io.h> #include <arch/cbfs.h> #include <arch/stages.h> +#include <arch/early_variables.h> #include <console/console.h> #include <cbmem.h> #include <cpu/x86/mtrr.h> @@ -44,6 +45,51 @@ #include <device/pci_def.h> #include <console/cbmem_console.h> +/* Return 0, 3, 4 or 5 to indicate the previous sleep state. */ +uint32_t chipset_prev_sleep_state(uint32_t clear) +{ + /* Default to S0. */ + uint32_t prev_sleep_state = 0; + uint32_t pm1_sts; + uint32_t pm1_cnt; + uint32_t gen_pmcon1; + + /* Read Power State */ + pm1_sts = inw(ACPI_BASE_ADDRESS + PM1_STS); + pm1_cnt = inl(ACPI_BASE_ADDRESS + PM1_CNT); + gen_pmcon1 = read32(PMC_BASE_ADDRESS + GEN_PMCON1); + + printk(BIOS_DEBUG, "PM1_STS = 0x%x PM1_CNT = 0x%x GEN_PMCON1 = 0x%x\n", + pm1_sts, pm1_cnt, gen_pmcon1); + + if (pm1_sts & WAK_STS) { + switch ((pm1_cnt & SLP_TYP) >> SLP_TYP_SHIFT) { + #if CONFIG_HAVE_ACPI_RESUME + case SLP_TYP_S3: + prev_sleep_state = 3; + break; + #endif + case SLP_TYP_S4: + prev_sleep_state = 4; + break; + + case SLP_TYP_S5: + prev_sleep_state = 5; + break; + } + /* If set Clear SLP_TYP. */ + if (clear == 1) { + outl(pm1_cnt & ~(SLP_TYP), ACPI_BASE_ADDRESS + PM1_CNT); + } + } + + if (gen_pmcon1 & (PWR_FLR | SUS_PWR_FLR)) { + prev_sleep_state = 5; + } + + return prev_sleep_state; +} + static void program_base_addresses(void) { uint32_t reg; @@ -174,6 +220,8 @@ void * asmlinkage main(FSP_INFO_HEADER *fsp_info_header) void romstage_main_continue(EFI_STATUS status, void *hob_list_ptr) { int cbmem_was_initted; void *cbmem_hob_ptr; + uint32_t prev_sleep_state; + struct romstage_handoff *handoff; #if IS_ENABLED(CONFIG_COLLECT_TIMESTAMPS) tsc_t after_initram_time = rdtsc(); @@ -193,6 +241,10 @@ void romstage_main_continue(EFI_STATUS status, void *hob_list_ptr) { printk(BIOS_DEBUG, "FSP Status: 0x%0x\n", (u32)status); + /* Get previous sleep state again and clear */ + prev_sleep_state = chipset_prev_sleep_state(1); + printk(BIOS_DEBUG, "%s: prev_sleep_state = S%d\n", __func__, prev_sleep_state); + report_platform_info(); #if IS_ENABLED(CONFIG_COLLECT_TIMESTAMPS) @@ -203,16 +255,26 @@ void romstage_main_continue(EFI_STATUS status, void *hob_list_ptr) { late_mainboard_romstage_entry(); post_code(0x4c); - quick_ram_check(); - post_code(0x4d); + /* if S3 resume skip ram check */ + if (prev_sleep_state != 3) { + quick_ram_check(); + post_code(0x4d); + } - cbmem_was_initted = !cbmem_recovery(0); + cbmem_was_initted = !cbmem_recovery(prev_sleep_state == 3); /* Save the HOB pointer in CBMEM to be used in ramstage*/ cbmem_hob_ptr = cbmem_add (CBMEM_ID_HOB_POINTER, sizeof(*hob_list_ptr)); *(u32*)cbmem_hob_ptr = (u32)hob_list_ptr; post_code(0x4e); + handoff = romstage_handoff_find_or_add(); + if (handoff != NULL) + handoff->s3_resume = (prev_sleep_state == 3); + else + printk(BIOS_DEBUG, "Romstage handoff structure not added!\n"); + + #if IS_ENABLED(CONFIG_COLLECT_TIMESTAMPS) timestamp_init(base_time); timestamp_reinit();

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Patch set updated for coreboot: ba9f2f8 minnowmax: Add S3 suspend/resume Support
by Mohan D'Costa 25 Sep '14

25 Sep '14

Mohan D'Costa (mohan(a)ndr.co.jp) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6937 -gerrit commit ba9f2f848e2a302a389c6ea0f62581fde67bcd50 Author: Mohan D'Costa <mohan(a)ndr.co.jp> Date: Thu Sep 18 15:57:06 2014 +0900 minnowmax: Add S3 suspend/resume Support This adds S3 Suspend / Resume support to MinnowMax board using Intel's Bay Trail FSP It is based on the "src/soc/intel/baytrail/romstage/romstage.c" implementation. Tested resume from Power Button and Magic Packet. Change-Id: If0011068eb7290d1b764c5c4b12c17375fb69008 Signed-off-by: Mohan D'Costa <mohan(a)ndr.co.jp> --- src/drivers/intel/fsp/Kconfig | 1 + src/mainboard/intel/minnowmax/Kconfig | 1 + src/soc/intel/fsp_baytrail/acpi/sleepstates.asl | 3 + src/soc/intel/fsp_baytrail/baytrail/romstage.h | 1 + src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c | 33 ++++++++++- src/soc/intel/fsp_baytrail/ramstage.c | 32 +++++++++++ src/soc/intel/fsp_baytrail/romstage/romstage.c | 68 ++++++++++++++++++++++- 7 files changed, 134 insertions(+), 5 deletions(-) diff --git a/src/drivers/intel/fsp/Kconfig b/src/drivers/intel/fsp/Kconfig index 5e44046..2d41365 100644 --- a/src/drivers/intel/fsp/Kconfig +++ b/src/drivers/intel/fsp/Kconfig @@ -63,6 +63,7 @@ config ENABLE_FSP_FAST_BOOT config ENABLE_MRC_CACHE bool + default y if HAVE_ACPI_RESUME default n help Enabling this feature will cause MRC data to be cached in NV storage. diff --git a/src/mainboard/intel/minnowmax/Kconfig b/src/mainboard/intel/minnowmax/Kconfig index 0e83d5a..229172c 100644 --- a/src/mainboard/intel/minnowmax/Kconfig +++ b/src/mainboard/intel/minnowmax/Kconfig @@ -27,6 +27,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_OPTION_TABLE select OVERRIDE_MRC_CACHE_LOC select TSC_MONOTONIC_TIMER + select HAVE_ACPI_RESUME config MAINBOARD_DIR string diff --git a/src/soc/intel/fsp_baytrail/acpi/sleepstates.asl b/src/soc/intel/fsp_baytrail/acpi/sleepstates.asl index 65339cc..12e359a 100644 --- a/src/soc/intel/fsp_baytrail/acpi/sleepstates.asl +++ b/src/soc/intel/fsp_baytrail/acpi/sleepstates.asl @@ -21,5 +21,8 @@ Name(\_S0, Package(){0x0,0x0,0x0,0x0}) // Name(\_S1, Package(){0x1,0x1,0x0,0x0}) +#if CONFIG_HAVE_ACPI_RESUME +Name(\_S3, Package(){0x5,0x5,0x0,0x0}) +#endif Name(\_S4, Package(){0x6,0x6,0x0,0x0}) Name(\_S5, Package(){0x7,0x7,0x0,0x0}) diff --git a/src/soc/intel/fsp_baytrail/baytrail/romstage.h b/src/soc/intel/fsp_baytrail/baytrail/romstage.h index 8feab8a..1ceb4cf 100644 --- a/src/soc/intel/fsp_baytrail/baytrail/romstage.h +++ b/src/soc/intel/fsp_baytrail/baytrail/romstage.h @@ -33,6 +33,7 @@ void report_platform_info(void); #include <fsptypes.h> void romstage_main_continue(EFI_STATUS status, void *hob_list_ptr); +uint32_t chipset_prev_sleep_state(uint32_t clear); #define NUM_ROMSTAGE_TS 4 diff --git a/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c b/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c index 60a1f7a..83a1100 100644 --- a/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c +++ b/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c @@ -28,7 +28,11 @@ #include <baytrail/pci_devs.h> #include <drivers/intel/fsp/fsp_util.h> #include "../chip.h" +#include <arch/io.h> #include <baytrail/reset.h> +#include <baytrail/pmc.h> +#include <baytrail/acpi.h> +#include <baytrail/iomap.h> #ifdef __PRE_RAM__ #include <baytrail/romstage.h> @@ -307,18 +311,43 @@ void chipset_fsp_early_init(FSP_INIT_PARAMS *pFspInitParams, FSP_INFO_HEADER *fsp_ptr) { FSP_INIT_RT_BUFFER *pFspRtBuffer = pFspInitParams->RtBufferPtr; + uint32_t prev_sleep_state; + + /* Get previous sleep state but don't clear */ + prev_sleep_state = chipset_prev_sleep_state(0); + printk(BIOS_INFO, "prev_sleep_state = S%d\n", prev_sleep_state); /* Initialize the UPD Data */ GetUpdDefaultFromFsp (fsp_ptr, pFspRtBuffer->Common.UpdDataRgnPtr); ConfigureDefaultUpdData(pFspRtBuffer->Common.UpdDataRgnPtr); pFspInitParams->NvsBufferPtr = NULL; - pFspRtBuffer->Common.BootMode = BOOT_WITH_FULL_CONFIGURATION; -#if IS_ENABLED(CONFIG_ENABLE_FSP_FAST_BOOT) +#if IS_ENABLED(CONFIG_ENABLE_MRC_CACHE) /* Find the fastboot cache that was saved in the ROM */ pFspInitParams->NvsBufferPtr = find_and_set_fastboot_cache(); #endif + if (prev_sleep_state == 3) { + /* S3 resume */ + if ( pFspInitParams->NvsBufferPtr == NULL) { + /* If waking from S3 and no cache then. */ + printk(BIOS_WARNING, "No MRC cache found in S3 resume path.\n"); + post_code(POST_RESUME_FAILURE); + /* Clear Sleep Type */ + outl(inl(ACPI_BASE_ADDRESS + PM1_CNT) & + ~(SLP_TYP), ACPI_BASE_ADDRESS + PM1_CNT); + /* Reboot */ + printk(BIOS_WARNING,"Rebooting..\n" ); + warm_reset(); + /* Should not reach here.. */ + die("Reboot System\n"); + } + pFspRtBuffer->Common.BootMode = BOOT_ON_S3_RESUME; + } else { + /* Not S3 resume */ + pFspRtBuffer->Common.BootMode = BOOT_WITH_FULL_CONFIGURATION; + } + return; } diff --git a/src/soc/intel/fsp_baytrail/ramstage.c b/src/soc/intel/fsp_baytrail/ramstage.c index e231701..814b16e 100644 --- a/src/soc/intel/fsp_baytrail/ramstage.c +++ b/src/soc/intel/fsp_baytrail/ramstage.c @@ -18,6 +18,7 @@ */ #include <arch/cpu.h> +#include <arch/acpi.h> #include <console/console.h> #include <cpu/intel/microcode.h> #include <cpu/x86/cr.h> @@ -25,10 +26,12 @@ #include <device/device.h> #include <device/pci_def.h> #include <device/pci_ops.h> +#include <romstage_handoff.h> #include <stdlib.h> #include <baytrail/gpio.h> #include <baytrail/lpc.h> +#include <baytrail/nvs.h> #include <baytrail/msr.h> #include <baytrail/pattrs.h> #include <baytrail/pci_devs.h> @@ -123,6 +126,32 @@ static void fill_in_pattrs(void) } +static inline void set_acpi_sleep_type(int val) +{ +#if CONFIG_HAVE_ACPI_RESUME + acpi_slp_type = val; +#endif +} + +static void s3_resume_prepare(void) +{ + global_nvs_t *gnvs; + struct romstage_handoff *romstage_handoff; + + gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(global_nvs_t)); + + romstage_handoff = cbmem_find(CBMEM_ID_ROMSTAGE_INFO); + if (romstage_handoff == NULL || romstage_handoff->s3_resume == 0) { + if (gnvs != NULL) { + memset(gnvs, 0, sizeof(global_nvs_t)); + } + set_acpi_sleep_type(0); + return; + } + + set_acpi_sleep_type(3); +} + void baytrail_init_pre_device(void) { struct soc_gpio_config *config; @@ -132,6 +161,9 @@ void baytrail_init_pre_device(void) /* Allow for SSE instructions to be executed. */ write_cr4(read_cr4() | CR4_OSFXSR | CR4_OSXMMEXCPT); + /* Indicate S3 resume to rest of ramstage. */ + s3_resume_prepare(); + /* Get GPIO initial states from mainboard */ config = mainboard_get_gpios(); setup_soc_gpios(config); diff --git a/src/soc/intel/fsp_baytrail/romstage/romstage.c b/src/soc/intel/fsp_baytrail/romstage/romstage.c index a63156f..0c72b98 100644 --- a/src/soc/intel/fsp_baytrail/romstage/romstage.c +++ b/src/soc/intel/fsp_baytrail/romstage/romstage.c @@ -24,6 +24,7 @@ #include <arch/io.h> #include <arch/cbfs.h> #include <arch/stages.h> +#include <arch/early_variables.h> #include <console/console.h> #include <cbmem.h> #include <cpu/x86/mtrr.h> @@ -44,6 +45,51 @@ #include <device/pci_def.h> #include <console/cbmem_console.h> +/* Return 0, 3, 4 or 5 to indicate the previous sleep state. */ +uint32_t chipset_prev_sleep_state(uint32_t clear) +{ + /* Default to S0. */ + uint32_t prev_sleep_state = 0; + uint32_t pm1_sts; + uint32_t pm1_cnt; + uint32_t gen_pmcon1; + + /* Read Power State */ + pm1_sts = inw(ACPI_BASE_ADDRESS + PM1_STS); + pm1_cnt = inl(ACPI_BASE_ADDRESS + PM1_CNT); + gen_pmcon1 = read32(PMC_BASE_ADDRESS + GEN_PMCON1); + + printk(BIOS_DEBUG, "PM1_STS = 0x%x PM1_CNT = 0x%x GEN_PMCON1 = 0x%x\n", + pm1_sts, pm1_cnt, gen_pmcon1); + + if (pm1_sts & WAK_STS) { + switch ((pm1_cnt & SLP_TYP) >> SLP_TYP_SHIFT) { + #if CONFIG_HAVE_ACPI_RESUME + case SLP_TYP_S3: + prev_sleep_state = 3; + break; + #endif + case SLP_TYP_S4: + prev_sleep_state = 4; + break; + + case SLP_TYP_S5: + prev_sleep_state = 5; + break; + } + /* If set Clear SLP_TYP. */ + if (clear == 1) { + outl(pm1_cnt & ~(SLP_TYP), ACPI_BASE_ADDRESS + PM1_CNT); + } + } + + if (gen_pmcon1 & (PWR_FLR | SUS_PWR_FLR)) { + prev_sleep_state = 5; + } + + return prev_sleep_state; +} + static void program_base_addresses(void) { uint32_t reg; @@ -174,6 +220,8 @@ void * asmlinkage main(FSP_INFO_HEADER *fsp_info_header) void romstage_main_continue(EFI_STATUS status, void *hob_list_ptr) { int cbmem_was_initted; void *cbmem_hob_ptr; + uint32_t prev_sleep_state; + struct romstage_handoff *handoff; #if IS_ENABLED(CONFIG_COLLECT_TIMESTAMPS) tsc_t after_initram_time = rdtsc(); @@ -193,6 +241,10 @@ void romstage_main_continue(EFI_STATUS status, void *hob_list_ptr) { printk(BIOS_DEBUG, "FSP Status: 0x%0x\n", (u32)status); + /* Get previous sleep state again and clear */ + prev_sleep_state = chipset_prev_sleep_state(1); + printk(BIOS_DEBUG, "%s: prev_sleep_state = S%d\n", __func__, prev_sleep_state); + report_platform_info(); #if IS_ENABLED(CONFIG_COLLECT_TIMESTAMPS) @@ -203,16 +255,26 @@ void romstage_main_continue(EFI_STATUS status, void *hob_list_ptr) { late_mainboard_romstage_entry(); post_code(0x4c); - quick_ram_check(); - post_code(0x4d); + /* if S3 resume skip ram check */ + if (prev_sleep_state != 3) { + quick_ram_check(); + post_code(0x4d); + } - cbmem_was_initted = !cbmem_recovery(0); + cbmem_was_initted = !cbmem_recovery(prev_sleep_state == 3); /* Save the HOB pointer in CBMEM to be used in ramstage*/ cbmem_hob_ptr = cbmem_add (CBMEM_ID_HOB_POINTER, sizeof(*hob_list_ptr)); *(u32*)cbmem_hob_ptr = (u32)hob_list_ptr; post_code(0x4e); + handoff = romstage_handoff_find_or_add(); + if (handoff != NULL) + handoff->s3_resume = (prev_sleep_state == 3); + else + printk(BIOS_DEBUG, "Romstage handoff structure not added!\n"); + + #if IS_ENABLED(CONFIG_COLLECT_TIMESTAMPS) timestamp_init(base_time); timestamp_reinit();

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coreboot-gerrit September 2014