coreboot-gerrit September 2014

coreboot-gerrit@coreboot.org

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Patch merged into coreboot/master: 61d07d6 libpayload: Build libpayload with debugging info turned up all the way.
by gerrit＠coreboot.org 29 Sep '14

29 Sep '14

the following patch was just integrated into master: commit 61d07d63ec5e1d6c4a8af2090ca6ee9be4448732 Author: Gabe Black <gabeblack(a)google.com> Date: Mon Dec 16 04:02:48 2013 -0800 libpayload: Build libpayload with debugging info turned up all the way. Pass -ggdb3 to the compiler when building libpayload, -ggdb so that it uses "the most expressive format available", and 3 so that the debugging level is set to 3, the highest value currently supported. The debugging information can be stripped by the payload consuming the library, and will definitely be stripped by cbfstool when installing that payload into an image. Change-Id: Ifd6c4a928fbb0b9fa9b3b2e0ea298abff31baf3b Signed-off-by: Gabe Black <gabeblack(a)google.com> Reviewed-on: https://chromium-review.googlesource.com/180252 Reviewed-by: Gabe Black <gabeblack(a)chromium.org> Tested-by: Gabe Black <gabeblack(a)chromium.org> Commit-Queue: Gabe Black <gabeblack(a)chromium.org> (cherry picked from commit dc04daaf099c53c57508b66e08f40945345a56ca) Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com> Reviewed-on: http://review.coreboot.org/6980 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Patrick Georgi <patrick(a)georgi-clan.de> See http://review.coreboot.org/6980 for details. -gerrit

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Patch merged into coreboot/master: 8404dca Remove stale char[] initialization causing unaligned memory access
by gerrit＠coreboot.org 29 Sep '14

29 Sep '14

the following patch was just integrated into master: commit 8404dca5a6c20f7b0e947011d9a185e6060ad157 Author: Marcelo Povoa <marcelogp(a)chromium.org> Date: Fri Feb 14 15:42:49 2014 -0800 Remove stale char[] initialization causing unaligned memory access This throws an alignment fault when run in ARMv8 Foundation model and seems unnecessary, so remove it. Change-Id: I2e3aa54502c292958ba44ff4e2e71c27653f2e1a Signed-off-by: Marcelo Povoa <marcelogp(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/186744 Reviewed-by: David Hendricks <dhendrix(a)chromium.org> (cherry picked from commit 57510d553c56ca5dfb4765836ddb901744e29e20) Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com> Reviewed-on: http://review.coreboot.org/6974 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick(a)georgi-clan.de> See http://review.coreboot.org/6974 for details. -gerrit

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Patch merged into coreboot/master: be1d1e7 google/panther: Be safe about invalid thermal readings
by gerrit＠coreboot.org 29 Sep '14

29 Sep '14

the following patch was just integrated into master: commit be1d1e7f838e09e67b8cc0e84cd842f4cf71f9ae Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Mon Mar 3 15:08:10 2014 -0800 google/panther: Be safe about invalid thermal readings In case we get an invalid thermal reading, let's run the fan at full speed rather than at low speed. This might impact the user experiance slightly in cases where the bad reading does not happen while the system is hot, but it will increase stability in the cases where the system is actually overheating. Also, set the critical temperature below tjmax, because otherwise thermal shutdown by the OS will never be triggered. Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Change-Id: Iab262f1f17a5dff875c596d9e8d50e4e50ee90f9 Reviewed-on: https://chromium-review.googlesource.com/188556 Reviewed-by: Shawn Nematbakhsh <shawnn(a)chromium.org> Commit-Queue: Stefan Reinauer <reinauer(a)chromium.org> Tested-by: Stefan Reinauer <reinauer(a)chromium.org> (cherry picked from commit 721fc2361ea9c6fea75409be57726294ce840f03) Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com> Reviewed-on: http://review.coreboot.org/6962 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick(a)georgi-clan.de> See http://review.coreboot.org/6962 for details. -gerrit

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Patch merged into coreboot/master: 3f1500f google/chromeec: Notify DPTF charger participant on AC state change
by gerrit＠coreboot.org 29 Sep '14

29 Sep '14

the following patch was just integrated into master: commit 3f1500f54f7d5d0bdc4b2f3a99cb7768d31066cc Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Thu Mar 6 08:37:49 2014 -0800 google/chromeec: Notify DPTF charger participant on AC state change The DPTF charger particpant device needs to be notified when the AC state changes so it can re-evaluate the PPCC object and apply the proper charge rate limit if necessary. Change-Id: I6723754e2fe12862f50709875140fcadcddb18eb Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/189029 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-by: Brad Geltz <brad.geltz(a)intel.com> (cherry picked from commit ed1ee577014421b021e8814edc91a1b696bf9eed) Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com> Reviewed-on: http://review.coreboot.org/6951 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Patrick Georgi <patrick(a)georgi-clan.de> See http://review.coreboot.org/6951 for details. -gerrit

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Patch merged into coreboot/master: 1f8d246 arm: Fix up new cache flush algorithm and replace dcache_*_all() with it
by gerrit＠coreboot.org 29 Sep '14

29 Sep '14

the following patch was just integrated into master: commit 1f8d246d2f69e9f130a736204faa77685a0cc937 Author: Julius Werner <jwerner(a)chromium.org> Date: Wed Jan 15 14:13:25 2014 -0800 arm: Fix up new cache flush algorithm and replace dcache_*_all() with it This patch fixes the remaining few bugs in our shiny new cache iteration by set/way/level algorithm to actually make it work: It makes it start from cache level 0 (previously it would always start at LoC and be "done" instantly), fixes up the two shifts that isolate the set bits at the end (which didn't seem to account for the fact that the first shift affects the second), and throws an S bit on that last shift so that it actually affects the conditionals after it. In addition, also moves the next_level block to the top so that we can share (and thus eliminate) some code at initialization, and turns the whole thing into a thrice-instantiated macro to create functions that fit our existing interface. Change-Id: I1338a589cbb37d74ea6e7a3d4f67ff827e24edbe Signed-off-by: Julius Werner <jwerner(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/183879 Reviewed-by: Stefan Reinauer <reinauer(a)google.com> Reviewed-by: David Hendricks <dhendrix(a)chromium.org> (cherry picked from commit 6d94f8330191c316fe093ddb5288329453da8a4b) Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com> Reviewed-on: http://review.coreboot.org/6932 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick(a)georgi-clan.de> See http://review.coreboot.org/6932 for details. -gerrit

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Patch merged into coreboot/master: 12de698 arm: Import armv7_dcache_wbinv_all function from NetBSD
by gerrit＠coreboot.org 29 Sep '14

29 Sep '14

the following patch was just integrated into master: commit 12de698c248e52a14cbb56f5fc3c4598115d72ef Author: Julius Werner <jwerner(a)chromium.org> Date: Mon Jan 13 11:13:23 2014 -0800 arm: Import armv7_dcache_wbinv_all function from NetBSD This patch pulls in NetBSD's full cache flushing algorithm for ARM, to replace our old, slow and slightly overzealous C-only implementation. It's a beautiful piece of code that manages to run on only caller-saved registers (meaning it doesn't need to write to memory) in a very tight loop, and it's BSD-licensed to boot (which we need for libpayload). Unfortunately it's also not quite correct, but I can fix that. Pulling the original in a separate commit to make it more obvious what changes are mine. Change-Id: I7a71c9e570866a6e25f756cb09ae2b6445048d83 Signed-off-by: Julius Werner <jwerner(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/183878 Reviewed-by: Stefan Reinauer <reinauer(a)google.com> Reviewed-by: Vincent Palatin <vpalatin(a)chromium.org> Reviewed-by: David Hendricks <dhendrix(a)chromium.org> (cherry picked from commit 4698467320613d7ddc39714f40aacbc990af9399) Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com> Reviewed-on: http://review.coreboot.org/6931 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick(a)georgi-clan.de> See http://review.coreboot.org/6931 for details. -gerrit

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New patch to review for coreboot: de590c4 util/fletcher: fix debug option parsing
by Patrick Georgi 29 Sep '14

29 Sep '14

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6988 -gerrit commit de590c42869e07911dc06a5e401c90273493df05 Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Mon Sep 29 10:12:29 2014 +0200 util/fletcher: fix debug option parsing sizeof(char[]-type+1) isn't very useful. Since one of the strings is constant, we also don't need to use strncmp that string's length. While at it, str*cmp don't return booleans, so check for value instead of faux bools. Change-Id: Iebb194a60eac454dafeade75f135df92068cf4ab Found-by: Coverity Scan Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> --- util/fletcher/fletcher.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/util/fletcher/fletcher.c b/util/fletcher/fletcher.c index 3147d50..a572494 100644 --- a/util/fletcher/fletcher.c +++ b/util/fletcher/fletcher.c @@ -111,7 +111,7 @@ int main(int argc, char **argv) checksum = fletcher32(&buffer[2], filesize/2 - 2); *((uint32_t *)& buffer[2]) = checksum; #ifndef DEBUG - if ((argc == 2) && !strncmp(argv[1], debugoption, sizeof(debugoption+1))) { + if ((argc == 2) && (strcmp(argv[1], debugoption) == 0)) { #endif fprintf(stderr, "Fletcher's Checksum: %x\n", checksum); #ifndef DEBUG

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New patch to review for coreboot: 33f240c cbfstool: free memory
by Patrick Georgi 29 Sep '14

29 Sep '14

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6987 -gerrit commit 33f240cd54eeb599a630ab2d913b2afdd1857960 Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Mon Sep 29 10:08:35 2014 +0200 cbfstool: free memory Change-Id: Ic53127a61154460fa3741a92a3b2de0eba446e9f Found-by: Coverity Scan Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> --- util/cbfstool/cbfs-mkpayload.c | 25 ++++++++++++++++++------- 1 file changed, 18 insertions(+), 7 deletions(-) diff --git a/util/cbfstool/cbfs-mkpayload.c b/util/cbfstool/cbfs-mkpayload.c index dabe322..38cc482 100644 --- a/util/cbfstool/cbfs-mkpayload.c +++ b/util/cbfstool/cbfs-mkpayload.c @@ -79,8 +79,9 @@ int parse_elf_to_payload(const struct buffer *input, int segments = 1; int isize = 0, osize = 0; int doffset = 0; - struct cbfs_payload_segment *segs; + struct cbfs_payload_segment *segs = NULL; int i; + int ret = 0; comp_func_ptr compress = compression_function(algo); if (!compress) @@ -133,12 +134,16 @@ int parse_elf_to_payload(const struct buffer *input, } /* allocate the segment header array */ segs = calloc(segments, sizeof(*segs)); - if (segs == NULL) - return -1; + if (segs == NULL) { + ret = -1; + goto out; + } /* Allocate a block of memory to store the data in */ if (buffer_create(output, (segments * sizeof(*segs)) + isize, - input->name) != 0) - return -1; + input->name) != 0) { + ret = -1; + goto out; + } memset(output->data, 0, output->size); doffset = (segments * sizeof(*segs)); @@ -208,7 +213,8 @@ int parse_elf_to_payload(const struct buffer *input, if (compress((char *)&header[phdr[i].p_offset], phdr[i].p_filesz, output->data + doffset, &len)) { buffer_delete(output); - return -1; + ret = -1; + goto out; } segs[segments].len = len; @@ -233,7 +239,12 @@ int parse_elf_to_payload(const struct buffer *input, output->size = (segments * sizeof(*segs)) + osize; xdr_segs(output, segs, segments); - return 0; + +out: + if (segs) free(segs); + if (shdr) free(shdr); + if (phdr) free(phdr); + return ret; } int parse_flat_binary_to_payload(const struct buffer *input,

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Patch set updated for coreboot: 851c693 intel/minnowmax: Enable S3 suspend/resume
by Mohan D'Costa 27 Sep '14

27 Sep '14

Mohan D'Costa (mohan(a)ndr.co.jp) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6972 -gerrit commit 851c6936af062badc746abb4cc7fe8468c9c5745 Author: Mohan D'Costa <mohan(a)ndr.co.jp> Date: Thu Sep 25 18:17:08 2014 +0900 intel/minnowmax: Enable S3 suspend/resume This enables S3 Suspend / Resume support for MinnowMax board using Intel's Bay Trail FSP Tested resume from Power Button and Magic Packet. Change-Id: I021122a68c05f2e725cabb8f3946249afe802bbe Signed-off-by: Mohan D'Costa <mohan(a)ndr.co.jp> --- src/mainboard/intel/minnowmax/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/src/mainboard/intel/minnowmax/Kconfig b/src/mainboard/intel/minnowmax/Kconfig index 0e83d5a..229172c 100644 --- a/src/mainboard/intel/minnowmax/Kconfig +++ b/src/mainboard/intel/minnowmax/Kconfig @@ -27,6 +27,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_OPTION_TABLE select OVERRIDE_MRC_CACHE_LOC select TSC_MONOTONIC_TIMER + select HAVE_ACPI_RESUME config MAINBOARD_DIR string

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Patch set updated for coreboot: b8fa8f9 intel/fsp_baytrail: Add S3 suspend/resume Support
by Mohan D'Costa 27 Sep '14

27 Sep '14

Mohan D'Costa (mohan(a)ndr.co.jp) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6937 -gerrit commit b8fa8f90f7083367ab4623e08aec5158f6ffe5c7 Author: Mohan D'Costa <mohan(a)ndr.co.jp> Date: Thu Sep 18 15:57:06 2014 +0900 intel/fsp_baytrail: Add S3 suspend/resume Support This adds S3 Suspend / Resume support to Intel's Bay Trail FSP It is based on the "src/soc/intel/baytrail/romstage/romstage.c" implementation. Change-Id: If0011068eb7290d1b764c5c4b12c17375fb69008 Signed-off-by: Mohan D'Costa <mohan(a)ndr.co.jp> --- src/drivers/intel/fsp/Kconfig | 1 + src/soc/intel/fsp_baytrail/acpi/sleepstates.asl | 3 + src/soc/intel/fsp_baytrail/baytrail/romstage.h | 1 + src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c | 33 ++++++++++- src/soc/intel/fsp_baytrail/ramstage.c | 32 +++++++++++ src/soc/intel/fsp_baytrail/romstage/romstage.c | 68 ++++++++++++++++++++++- 6 files changed, 133 insertions(+), 5 deletions(-) diff --git a/src/drivers/intel/fsp/Kconfig b/src/drivers/intel/fsp/Kconfig index 5e44046..2d41365 100644 --- a/src/drivers/intel/fsp/Kconfig +++ b/src/drivers/intel/fsp/Kconfig @@ -63,6 +63,7 @@ config ENABLE_FSP_FAST_BOOT config ENABLE_MRC_CACHE bool + default y if HAVE_ACPI_RESUME default n help Enabling this feature will cause MRC data to be cached in NV storage. diff --git a/src/soc/intel/fsp_baytrail/acpi/sleepstates.asl b/src/soc/intel/fsp_baytrail/acpi/sleepstates.asl index 65339cc..12e359a 100644 --- a/src/soc/intel/fsp_baytrail/acpi/sleepstates.asl +++ b/src/soc/intel/fsp_baytrail/acpi/sleepstates.asl @@ -21,5 +21,8 @@ Name(\_S0, Package(){0x0,0x0,0x0,0x0}) // Name(\_S1, Package(){0x1,0x1,0x0,0x0}) +#if CONFIG_HAVE_ACPI_RESUME +Name(\_S3, Package(){0x5,0x5,0x0,0x0}) +#endif Name(\_S4, Package(){0x6,0x6,0x0,0x0}) Name(\_S5, Package(){0x7,0x7,0x0,0x0}) diff --git a/src/soc/intel/fsp_baytrail/baytrail/romstage.h b/src/soc/intel/fsp_baytrail/baytrail/romstage.h index 8feab8a..1ceb4cf 100644 --- a/src/soc/intel/fsp_baytrail/baytrail/romstage.h +++ b/src/soc/intel/fsp_baytrail/baytrail/romstage.h @@ -33,6 +33,7 @@ void report_platform_info(void); #include <fsptypes.h> void romstage_main_continue(EFI_STATUS status, void *hob_list_ptr); +uint32_t chipset_prev_sleep_state(uint32_t clear); #define NUM_ROMSTAGE_TS 4 diff --git a/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c b/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c index 60a1f7a..83a1100 100644 --- a/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c +++ b/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c @@ -28,7 +28,11 @@ #include <baytrail/pci_devs.h> #include <drivers/intel/fsp/fsp_util.h> #include "../chip.h" +#include <arch/io.h> #include <baytrail/reset.h> +#include <baytrail/pmc.h> +#include <baytrail/acpi.h> +#include <baytrail/iomap.h> #ifdef __PRE_RAM__ #include <baytrail/romstage.h> @@ -307,18 +311,43 @@ void chipset_fsp_early_init(FSP_INIT_PARAMS *pFspInitParams, FSP_INFO_HEADER *fsp_ptr) { FSP_INIT_RT_BUFFER *pFspRtBuffer = pFspInitParams->RtBufferPtr; + uint32_t prev_sleep_state; + + /* Get previous sleep state but don't clear */ + prev_sleep_state = chipset_prev_sleep_state(0); + printk(BIOS_INFO, "prev_sleep_state = S%d\n", prev_sleep_state); /* Initialize the UPD Data */ GetUpdDefaultFromFsp (fsp_ptr, pFspRtBuffer->Common.UpdDataRgnPtr); ConfigureDefaultUpdData(pFspRtBuffer->Common.UpdDataRgnPtr); pFspInitParams->NvsBufferPtr = NULL; - pFspRtBuffer->Common.BootMode = BOOT_WITH_FULL_CONFIGURATION; -#if IS_ENABLED(CONFIG_ENABLE_FSP_FAST_BOOT) +#if IS_ENABLED(CONFIG_ENABLE_MRC_CACHE) /* Find the fastboot cache that was saved in the ROM */ pFspInitParams->NvsBufferPtr = find_and_set_fastboot_cache(); #endif + if (prev_sleep_state == 3) { + /* S3 resume */ + if ( pFspInitParams->NvsBufferPtr == NULL) { + /* If waking from S3 and no cache then. */ + printk(BIOS_WARNING, "No MRC cache found in S3 resume path.\n"); + post_code(POST_RESUME_FAILURE); + /* Clear Sleep Type */ + outl(inl(ACPI_BASE_ADDRESS + PM1_CNT) & + ~(SLP_TYP), ACPI_BASE_ADDRESS + PM1_CNT); + /* Reboot */ + printk(BIOS_WARNING,"Rebooting..\n" ); + warm_reset(); + /* Should not reach here.. */ + die("Reboot System\n"); + } + pFspRtBuffer->Common.BootMode = BOOT_ON_S3_RESUME; + } else { + /* Not S3 resume */ + pFspRtBuffer->Common.BootMode = BOOT_WITH_FULL_CONFIGURATION; + } + return; } diff --git a/src/soc/intel/fsp_baytrail/ramstage.c b/src/soc/intel/fsp_baytrail/ramstage.c index e231701..814b16e 100644 --- a/src/soc/intel/fsp_baytrail/ramstage.c +++ b/src/soc/intel/fsp_baytrail/ramstage.c @@ -18,6 +18,7 @@ */ #include <arch/cpu.h> +#include <arch/acpi.h> #include <console/console.h> #include <cpu/intel/microcode.h> #include <cpu/x86/cr.h> @@ -25,10 +26,12 @@ #include <device/device.h> #include <device/pci_def.h> #include <device/pci_ops.h> +#include <romstage_handoff.h> #include <stdlib.h> #include <baytrail/gpio.h> #include <baytrail/lpc.h> +#include <baytrail/nvs.h> #include <baytrail/msr.h> #include <baytrail/pattrs.h> #include <baytrail/pci_devs.h> @@ -123,6 +126,32 @@ static void fill_in_pattrs(void) } +static inline void set_acpi_sleep_type(int val) +{ +#if CONFIG_HAVE_ACPI_RESUME + acpi_slp_type = val; +#endif +} + +static void s3_resume_prepare(void) +{ + global_nvs_t *gnvs; + struct romstage_handoff *romstage_handoff; + + gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(global_nvs_t)); + + romstage_handoff = cbmem_find(CBMEM_ID_ROMSTAGE_INFO); + if (romstage_handoff == NULL || romstage_handoff->s3_resume == 0) { + if (gnvs != NULL) { + memset(gnvs, 0, sizeof(global_nvs_t)); + } + set_acpi_sleep_type(0); + return; + } + + set_acpi_sleep_type(3); +} + void baytrail_init_pre_device(void) { struct soc_gpio_config *config; @@ -132,6 +161,9 @@ void baytrail_init_pre_device(void) /* Allow for SSE instructions to be executed. */ write_cr4(read_cr4() | CR4_OSFXSR | CR4_OSXMMEXCPT); + /* Indicate S3 resume to rest of ramstage. */ + s3_resume_prepare(); + /* Get GPIO initial states from mainboard */ config = mainboard_get_gpios(); setup_soc_gpios(config); diff --git a/src/soc/intel/fsp_baytrail/romstage/romstage.c b/src/soc/intel/fsp_baytrail/romstage/romstage.c index a63156f..0c72b98 100644 --- a/src/soc/intel/fsp_baytrail/romstage/romstage.c +++ b/src/soc/intel/fsp_baytrail/romstage/romstage.c @@ -24,6 +24,7 @@ #include <arch/io.h> #include <arch/cbfs.h> #include <arch/stages.h> +#include <arch/early_variables.h> #include <console/console.h> #include <cbmem.h> #include <cpu/x86/mtrr.h> @@ -44,6 +45,51 @@ #include <device/pci_def.h> #include <console/cbmem_console.h> +/* Return 0, 3, 4 or 5 to indicate the previous sleep state. */ +uint32_t chipset_prev_sleep_state(uint32_t clear) +{ + /* Default to S0. */ + uint32_t prev_sleep_state = 0; + uint32_t pm1_sts; + uint32_t pm1_cnt; + uint32_t gen_pmcon1; + + /* Read Power State */ + pm1_sts = inw(ACPI_BASE_ADDRESS + PM1_STS); + pm1_cnt = inl(ACPI_BASE_ADDRESS + PM1_CNT); + gen_pmcon1 = read32(PMC_BASE_ADDRESS + GEN_PMCON1); + + printk(BIOS_DEBUG, "PM1_STS = 0x%x PM1_CNT = 0x%x GEN_PMCON1 = 0x%x\n", + pm1_sts, pm1_cnt, gen_pmcon1); + + if (pm1_sts & WAK_STS) { + switch ((pm1_cnt & SLP_TYP) >> SLP_TYP_SHIFT) { + #if CONFIG_HAVE_ACPI_RESUME + case SLP_TYP_S3: + prev_sleep_state = 3; + break; + #endif + case SLP_TYP_S4: + prev_sleep_state = 4; + break; + + case SLP_TYP_S5: + prev_sleep_state = 5; + break; + } + /* If set Clear SLP_TYP. */ + if (clear == 1) { + outl(pm1_cnt & ~(SLP_TYP), ACPI_BASE_ADDRESS + PM1_CNT); + } + } + + if (gen_pmcon1 & (PWR_FLR | SUS_PWR_FLR)) { + prev_sleep_state = 5; + } + + return prev_sleep_state; +} + static void program_base_addresses(void) { uint32_t reg; @@ -174,6 +220,8 @@ void * asmlinkage main(FSP_INFO_HEADER *fsp_info_header) void romstage_main_continue(EFI_STATUS status, void *hob_list_ptr) { int cbmem_was_initted; void *cbmem_hob_ptr; + uint32_t prev_sleep_state; + struct romstage_handoff *handoff; #if IS_ENABLED(CONFIG_COLLECT_TIMESTAMPS) tsc_t after_initram_time = rdtsc(); @@ -193,6 +241,10 @@ void romstage_main_continue(EFI_STATUS status, void *hob_list_ptr) { printk(BIOS_DEBUG, "FSP Status: 0x%0x\n", (u32)status); + /* Get previous sleep state again and clear */ + prev_sleep_state = chipset_prev_sleep_state(1); + printk(BIOS_DEBUG, "%s: prev_sleep_state = S%d\n", __func__, prev_sleep_state); + report_platform_info(); #if IS_ENABLED(CONFIG_COLLECT_TIMESTAMPS) @@ -203,16 +255,26 @@ void romstage_main_continue(EFI_STATUS status, void *hob_list_ptr) { late_mainboard_romstage_entry(); post_code(0x4c); - quick_ram_check(); - post_code(0x4d); + /* if S3 resume skip ram check */ + if (prev_sleep_state != 3) { + quick_ram_check(); + post_code(0x4d); + } - cbmem_was_initted = !cbmem_recovery(0); + cbmem_was_initted = !cbmem_recovery(prev_sleep_state == 3); /* Save the HOB pointer in CBMEM to be used in ramstage*/ cbmem_hob_ptr = cbmem_add (CBMEM_ID_HOB_POINTER, sizeof(*hob_list_ptr)); *(u32*)cbmem_hob_ptr = (u32)hob_list_ptr; post_code(0x4e); + handoff = romstage_handoff_find_or_add(); + if (handoff != NULL) + handoff->s3_resume = (prev_sleep_state == 3); + else + printk(BIOS_DEBUG, "Romstage handoff structure not added!\n"); + + #if IS_ENABLED(CONFIG_COLLECT_TIMESTAMPS) timestamp_init(base_time); timestamp_reinit();

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coreboot-gerrit September 2014