coreboot-gerrit September 2014

coreboot-gerrit@coreboot.org

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580 discussions

Patch merged into coreboot/master: a4a44a7 arm: Update a stale comment in bootblock .S files
by gerrit＠coreboot.org 09 Sep '14

09 Sep '14

the following patch was just integrated into master: commit a4a44a7b9a922da9bf3fbc692a05697715139814 Author: David Hendricks <dhendrix(a)chromium.org> Date: Thu Oct 3 14:02:45 2013 -0700 arm: Update a stale comment in bootblock .S files This just updates a comment which refers to "board_init_f". We use bootblock main() in coreboot. Change-Id: I4cb6b3c11f163b67fe48de495d13dce88710efc0 Reviewed-on: https://chromium-review.googlesource.com/172095 Reviewed-by: Gabe Black <gabeblack(a)chromium.org> Commit-Queue: David Hendricks <dhendrix(a)chromium.org> Tested-by: David Hendricks <dhendrix(a)chromium.org> (cherry picked from commit 65139f29682cedca8dfb58b3dfe67eab64299064) Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com> Reviewed-on: http://review.coreboot.org/6791 Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Tested-by: build bot (Jenkins) See http://review.coreboot.org/6791 for details. -gerrit

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Patch merged into coreboot/master: b6b1077 exynos: Install the BL1 and set the checksum in the Makefile.
by gerrit＠coreboot.org 09 Sep '14

09 Sep '14

the following patch was just integrated into master: commit b6b1077eec1a2afa84d0c8d469ad2e339cb775ef Author: Gabe Black <gabeblack(a)google.com> Date: Sun Dec 8 12:48:45 2013 -0800 exynos: Install the BL1 and set the checksum in the Makefile. Install the BL1 and set up the checksum in the Makefile instead of relying on post processing. Import the exynos checksum script, split it in two and simplify it significantly. Stop putting the CBFS header in the midst of the bootblock so that it can be checksummed before CBFS is put together. Stop saving space for it and leaving an anchor in the bootblock which nobody looks for. Change-Id: Icbb5a5914ece60b2827433b6dc29d80db996ea6c Signed-off-by: Gabe Black <gabeblack(a)google.com> Reviewed-on: https://chromium-review.googlesource.com/179229 Reviewed-by: Ronald Minnich <rminnich(a)chromium.org> Commit-Queue: Gabe Black <gabeblack(a)chromium.org> Tested-by: Gabe Black <gabeblack(a)chromium.org> (cherry picked from commit aa3a416705517c0a6ddfdeb19905ac8cafb33df1) Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com> Reviewed-on: http://review.coreboot.org/6834 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/6834 for details. -gerrit

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Patch merged into coreboot/master: 063c410 ARMv4: Add a minimal version of cpu.h.
by gerrit＠coreboot.org 09 Sep '14

09 Sep '14

the following patch was just integrated into master: commit 063c410a5429cabffbabb11388b76740bea0e6ab Author: Gabe Black <gabeblack(a)google.com> Date: Thu Oct 3 19:18:44 2013 -0700 ARMv4: Add a minimal version of cpu.h. All this version does is define asmlinkage to be nothing. It's required by the threading header file which is brought in by the timer implementation which I think is the hook for thread switching. Change-Id: Id57261d7c2c5ff8be00b0ad71bf7aaa9f3e24c1d Signed-off-by: Gabe Black <gabeblack(a)google.com> Reviewed-on: https://chromium-review.googlesource.com/171801 Reviewed-by: Ronald Minnich <rminnich(a)chromium.org> Tested-by: Gabe Black <gabeblack(a)chromium.org> Commit-Queue: Gabe Black <gabeblack(a)chromium.org> (cherry picked from commit e00379f54802066fd3e0685b291cdec289078055) Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com> Reviewed-on: http://review.coreboot.org/6831 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> See http://review.coreboot.org/6831 for details. -gerrit

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Patch set updated for coreboot: 2ab6a8b arm: Update a stale comment in bootblock .S files
by Isaac Christensen 09 Sep '14

09 Sep '14

Isaac Christensen (isaac.christensen(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6791 -gerrit commit 2ab6a8b5c7f9bb5a0afbe3674b5b9cf981da753c Author: David Hendricks <dhendrix(a)chromium.org> Date: Thu Oct 3 14:02:45 2013 -0700 arm: Update a stale comment in bootblock .S files This just updates a comment which refers to "board_init_f". We use bootblock main() in coreboot. Change-Id: I4cb6b3c11f163b67fe48de495d13dce88710efc0 Reviewed-on: https://chromium-review.googlesource.com/172095 Reviewed-by: Gabe Black <gabeblack(a)chromium.org> Commit-Queue: David Hendricks <dhendrix(a)chromium.org> Tested-by: David Hendricks <dhendrix(a)chromium.org> (cherry picked from commit 65139f29682cedca8dfb58b3dfe67eab64299064) Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com> --- src/arch/arm/armv4/bootblock.S | 2 +- src/arch/arm/armv7/bootblock.S | 2 +- src/soc/nvidia/tegra124/bootblock_asm.S | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/src/arch/arm/armv4/bootblock.S b/src/arch/arm/armv4/bootblock.S index 5f7de13..3ba2a88 100644 --- a/src/arch/arm/armv4/bootblock.S +++ b/src/arch/arm/armv4/bootblock.S @@ -65,7 +65,7 @@ init_stack_loop: cmp r0, r1 bne init_stack_loop -/* Set stackpointer in internal RAM to call board_init_f */ +/* Set stackpointer in internal RAM to call bootblock main() */ call_bootblock: ldr sp, .Stack /* Set up stack pointer */ ldr r0,=0x00000000 diff --git a/src/arch/arm/armv7/bootblock.S b/src/arch/arm/armv7/bootblock.S index b28a787..35882b0 100644 --- a/src/arch/arm/armv7/bootblock.S +++ b/src/arch/arm/armv7/bootblock.S @@ -76,7 +76,7 @@ init_stack_loop: cmp r0, r1 bne init_stack_loop -/* Set stackpointer in internal RAM to call board_init_f */ +/* Set stackpointer in internal RAM to call bootblock main() */ call_bootblock: ldr sp, .Stack /* Set up stack pointer */ ldr r0,=0x00000000 diff --git a/src/soc/nvidia/tegra124/bootblock_asm.S b/src/soc/nvidia/tegra124/bootblock_asm.S index 5f7de13..3ba2a88 100644 --- a/src/soc/nvidia/tegra124/bootblock_asm.S +++ b/src/soc/nvidia/tegra124/bootblock_asm.S @@ -65,7 +65,7 @@ init_stack_loop: cmp r0, r1 bne init_stack_loop -/* Set stackpointer in internal RAM to call board_init_f */ +/* Set stackpointer in internal RAM to call bootblock main() */ call_bootblock: ldr sp, .Stack /* Set up stack pointer */ ldr r0,=0x00000000

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Patch merged into coreboot/master: 2ceb1d8 tegra124: Switch the bootblock over the ARMv4 impelementation.
by gerrit＠coreboot.org 09 Sep '14

09 Sep '14

the following patch was just integrated into master: commit 2ceb1d8be6ef09efd66153a9ad6023843b514996 Author: Gabe Black <gabeblack(a)google.com> Date: Tue Oct 1 05:24:47 2013 -0700 tegra124: Switch the bootblock over the ARMv4 impelementation. The bootblock for the tegra124 runs on the AVP coprocessor which uses the ARMv4 architecture. Switch it over to that architecture. Change-Id: Ie527bbff938e6148c58727d448f9c2e6862da872 Signed-off-by: Gabe Black <gabeblack(a)google.com> Reviewed-on: https://chromium-review.googlesource.com/171402 Reviewed-by: Gabe Black <gabeblack(a)chromium.org> Tested-by: Gabe Black <gabeblack(a)chromium.org> Commit-Queue: Gabe Black <gabeblack(a)chromium.org> (cherry picked from commit c1aa76b7607ee40ff848628971a97eea5393aebe) Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com> Reviewed-on: http://review.coreboot.org/6784 Reviewed-by: Marc Jones <marc.jones(a)se-eng.com> Tested-by: build bot (Jenkins) See http://review.coreboot.org/6784 for details. -gerrit

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Patch merged into coreboot/master: f2f817e ARM: Add an ARMv4 architecture version.
by gerrit＠coreboot.org 09 Sep '14

09 Sep '14

the following patch was just integrated into master: commit f2f817ed1d5494b8ded166306564d16673fbf02c Author: Gabe Black <gabeblack(a)google.com> Date: Tue Oct 1 05:20:17 2013 -0700 ARM: Add an ARMv4 architecture version. This is needed for the tegra124's bootblock and includes enough implementation to support that use. No caching is supported, although there are function prototypes and stub implementations to satisfy includes and linking. Change-Id: Ib79dde8c30eda98b3e823cba2ff6115a610bb2e8 Signed-off-by: Gabe Black <gabeblack(a)google.com> Reviewed-on: https://chromium-review.googlesource.com/171401 Reviewed-by: Gabe Black <gabeblack(a)chromium.org> Tested-by: Gabe Black <gabeblack(a)chromium.org> Commit-Queue: Gabe Black <gabeblack(a)chromium.org> (cherry picked from commit 221dc76b3ce4c1d73851c432333e091e1c60f0cb) Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com> Reviewed-on: http://review.coreboot.org/6783 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> See http://review.coreboot.org/6783 for details. -gerrit

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New patch to review for coreboot: b4e2bc1 pnp: Allow setting of misc register 0xfa in device tree
by Isaac Christensen 09 Sep '14

09 Sep '14

Isaac Christensen (isaac.christensen(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6859 -gerrit commit b4e2bc1e07f83430f1e39565c4aec771fb589123 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Thu Oct 31 15:58:50 2013 -0700 pnp: Allow setting of misc register 0xfa in device tree Change-Id: I45885905f0adaa8f0ad9137d7034e6f7a0dc43de Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Reviewed-on: https://chromium-review.googlesource.com/175356 Reviewed-by: Stefan Reinauer <reinauer(a)chromium.org> Commit-Queue: Stefan Reinauer <reinauer(a)chromium.org> Tested-by: Stefan Reinauer <reinauer(a)chromium.org> (cherry picked from commit 7fe642543a8de249e13c3d63c3302a20910c247d) Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com> --- src/device/pnp_device.c | 5 +++++ src/include/device/pnp.h | 1 + src/include/device/pnp_def.h | 1 + src/superio/ite/it8772f/superio.c | 2 +- 4 files changed, 8 insertions(+), 1 deletion(-) diff --git a/src/device/pnp_device.c b/src/device/pnp_device.c index 987a253..0aaadaa 100644 --- a/src/device/pnp_device.c +++ b/src/device/pnp_device.c @@ -300,6 +300,11 @@ static void get_resources(device_t dev, struct pnp_info *info) resource->size = 1; resource->flags |= IORESOURCE_IRQ; } + if (info->flags & PNP_MSC10) { + resource = new_resource(dev, PNP_IDX_MSC10); + resource->size = 1; + resource->flags |= IORESOURCE_IRQ; + } } void pnp_enable_devices(device_t base_dev, struct device_operations *ops, diff --git a/src/include/device/pnp.h b/src/include/device/pnp.h index 43f457b..aed0439 100644 --- a/src/include/device/pnp.h +++ b/src/include/device/pnp.h @@ -48,6 +48,7 @@ struct pnp_info { #define PNP_EN 0x100 #define PNP_MSC0 0x200 #define PNP_MSC1 0x400 +#define PNP_MSC10 0x800 struct io_info io0, io1, io2, io3; }; struct resource *pnp_get_resource(device_t dev, unsigned index); diff --git a/src/include/device/pnp_def.h b/src/include/device/pnp_def.h index 91ec8f2..3258354 100644 --- a/src/include/device/pnp_def.h +++ b/src/include/device/pnp_def.h @@ -12,5 +12,6 @@ #define PNP_IDX_DRQ1 0x75 #define PNP_IDX_MSC0 0xf0 #define PNP_IDX_MSC1 0xf1 +#define PNP_IDX_MSC10 0xfa #endif /* DEVICE_PNP_DEF_H */ diff --git a/src/superio/ite/it8772f/superio.c b/src/superio/ite/it8772f/superio.c index 721e7f9..44bf33d 100644 --- a/src/superio/ite/it8772f/superio.c +++ b/src/superio/ite/it8772f/superio.c @@ -207,7 +207,7 @@ static struct pnp_info pnp_dev_info[] = { /* Serial Port 1 */ { &ops, IT8772F_SP1, PNP_IO0 | PNP_IRQ0, {0x0ff8, 0}, }, /* Environmental Controller */ - { &ops, IT8772F_EC, PNP_IO0 | PNP_IO1 | PNP_IRQ0, + { &ops, IT8772F_EC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_MSC10, {0x0ff8, 0}, {0x0ffc, 4}, }, /* KBC Keyboard */ { &ops, IT8772F_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0,

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New patch to review for coreboot: ce3771d mainboard/google/parrot: fix ACPI interrupt storm on lid switch change
by Andrew Litt 09 Sep '14

09 Sep '14

Andrew Litt (ajlitt(a)splunge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6858 -gerrit commit ce3771d5b30d286b82f0bacc63302f9c94a6740f Author: Andrew Litt <ajlitt(a)splunge.net> Date: Tue Sep 9 10:49:19 2014 -0500 mainboard/google/parrot: fix ACPI interrupt storm on lid switch change This fixes the ACPI interrupt storm on Parrot that happens when closing the lid or entering suspend by lid close (seen in /sys/firmware/acpi/interrupts/gpe1F). This patch inverts the interrupt trigger level every time the interrupt is received so that it doesn't fire until the next state change. Change-Id: I8b095914e9330c3217a4ceb058613fa952f4a234 Signed-off-by: Andrew Litt <ajlitt(a)splunge.net> --- src/mainboard/google/parrot/acpi/mainboard.asl | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/src/mainboard/google/parrot/acpi/mainboard.asl b/src/mainboard/google/parrot/acpi/mainboard.asl index 4ab9733..babb779 100644 --- a/src/mainboard/google/parrot/acpi/mainboard.asl +++ b/src/mainboard/google/parrot/acpi/mainboard.asl @@ -22,6 +22,11 @@ Scope (\_GPE) { Method(_L1F, 0x0, NotSerialized) { + /* Invert the interrupt level bit for the lid GPIO + so we don't get another _SB.LID0 until the state + changes again. GIV1 is the interrupt level control + register for GPIO bits 15:8 */ + Xor(GIV1, 0x80, GIV1) Notify(\_SB.LID0,0x80) } }

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Patch merged into coreboot/master: 70ad39e getac/p470: Add some more board info data
by gerrit＠coreboot.org 09 Sep '14

09 Sep '14

the following patch was just integrated into master: commit 70ad39e77524a45109830fdcba53143b0e0e2723 Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Sat Sep 6 16:06:57 2014 +0200 getac/p470: Add some more board info data Change-Id: I7cf47a16928436734df29af951f987db9cf9530d Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Reviewed-on: http://review.coreboot.org/6847 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> See http://review.coreboot.org/6847 for details. -gerrit

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New patch to review for coreboot: 6afbb60 Exynos5420: Fix up the i2c driver for use with the TPM driver
by Isaac Christensen 09 Sep '14

09 Sep '14

Isaac Christensen (isaac.christensen(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6857 -gerrit commit 6afbb600181131d341c3a0e86381ff369a5fff3d Author: Gabe Black <gabeblack(a)google.com> Date: Wed Nov 6 11:21:48 2013 -0800 Exynos5420: Fix up the i2c driver for use with the TPM driver The TPM driver expects to call i2c_read with zero address length. The i2c driver wasn't prepared to handle that particularly in the case of reads because it expected to send an address before switching over to read mode for the data. This change also fixes up the read and write calls to consistently be read32 and write32 instead of readl and writel. Change-Id: I33dee89b83d4cd9d3e1b90e84b40e761bb8d4de4 Signed-off-by: Gabe Black <gabeblack(a)google.com> Reviewed-on: https://chromium-review.googlesource.com/175966 Reviewed-by: Stefan Reinauer <reinauer(a)chromium.org> Tested-by: Stefan Reinauer <reinauer(a)chromium.org> Commit-Queue: Gabe Black <gabeblack(a)chromium.org> (cherry picked from commit cf686269424ea938d6f953d0f76103182eb71297) Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com> --- src/soc/samsung/exynos5420/i2c.c | 28 +++++++++++++++------------- 1 file changed, 15 insertions(+), 13 deletions(-) diff --git a/src/soc/samsung/exynos5420/i2c.c b/src/soc/samsung/exynos5420/i2c.c index 2268628..6ca0087 100644 --- a/src/soc/samsung/exynos5420/i2c.c +++ b/src/soc/samsung/exynos5420/i2c.c @@ -210,7 +210,7 @@ static int WaitForXfer(struct s3c24x0_i2c *i2c) static void ReadWriteByte(struct s3c24x0_i2c *i2c) { - writel(read32(&i2c->iiccon) & ~I2CCON_IRPND, &i2c->iiccon); + write32(read32(&i2c->iiccon) & ~I2CCON_IRPND, &i2c->iiccon); } static void i2c_ch_init(struct s3c24x0_i2c_bus *bus, int speed, int slaveadd) @@ -318,7 +318,7 @@ static void hsi2c_ch_init(struct s3c24x0_i2c_bus *i2c_bus, write32(HSI2C_RXFIFO_EN | HSI2C_TXFIFO_EN, &hsregs->usi_fifo_ctl); /* i2c_conf configure */ - write32(readl(&hsregs->usi_conf) | HSI2C_AUTO_MODE, &hsregs->usi_conf); + write32(read32(&hsregs->usi_conf) | HSI2C_AUTO_MODE, &hsregs->usi_conf); } /* SW reset for the high speed bus */ @@ -484,17 +484,19 @@ static int hsi2c_read(struct exynos5_hsi2c *i2c, /* chip address */ write32(HSI2C_SLV_ADDR_MAS(chip), &i2c->i2c_addr); - /* usi_ctl enable i2c func, master write configure */ - write32((HSI2C_TXCHON | HSI2C_FUNC_MODE_I2C | HSI2C_MASTER), - &i2c->usi_ctl); + if (alen) { + /* usi_ctl enable i2c func, master write configure */ + write32(HSI2C_TXCHON | HSI2C_FUNC_MODE_I2C | HSI2C_MASTER, + &i2c->usi_ctl); - /* auto_conf */ - write32(alen | HSI2C_MASTER_RUN | HSI2C_STOP_AFTER_TRANS, - &i2c->usi_auto_conf); + /* auto_conf */ + write32(alen | HSI2C_MASTER_RUN | HSI2C_STOP_AFTER_TRANS, + &i2c->usi_auto_conf); - if (hsi2c_senddata(i2c, addr, alen) || - hsi2c_wait_for_transfer(i2c) != 1) { - return -1; + if (hsi2c_senddata(i2c, addr, alen) || + hsi2c_wait_for_transfer(i2c) != 1) { + return -1; + } } /* usi_ctl enable i2c func, master WRITE configure */ @@ -542,7 +544,7 @@ static int i2c_transfer(struct s3c24x0_i2c *i2c, timer_monotonic_get(&current); end = current; mono_time_add_usecs(&end, I2C_TIMEOUT_MS * 1000); - while (readl(&i2c->iicstat) & I2CSTAT_BSY) { + while (read32(&i2c->iicstat) & I2CSTAT_BSY) { if (!mono_time_before(&current, &end)){ printk(BIOS_ERR, "%s timed out\n", __func__); return I2C_NOK_TOUT; @@ -607,7 +609,7 @@ static int i2c_transfer(struct s3c24x0_i2c *i2c, while ((i < data_len) && (result == I2C_OK)) { /* disable ACK for final READ */ if (i == data_len - 1) - write32(readl(&i2c->iiccon) + write32(read32(&i2c->iiccon) & ~I2CCON_ACKGEN, &i2c->iiccon); ReadWriteByte(i2c);

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coreboot-gerrit September 2014