coreboot-gerrit September 2014

coreboot-gerrit@coreboot.org

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580 discussions

Patch merged into coreboot/master: 802c910 Increase space for ACPI tables when using dynamic CBMEM
by gerrit＠coreboot.org 11 Sep '14

11 Sep '14

the following patch was just integrated into master: commit 802c910fa39d7245c96ad055988ccfc3a3ab26c1 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Thu Aug 28 23:03:15 2014 +0200 Increase space for ACPI tables when using dynamic CBMEM Unlike in old style CBMEM, dynamic CBMEM does not have a hand-calculated, hard-coded size, so allow up to 144K of space for ACPI tables. Change-Id: Id9dd7447c46d5fe7ed581be753d70e59add05320 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Reviewed-on: http://review.coreboot.org/6795 Tested-by: build bot (Jenkins) Reviewed-by: Gerd Hoffmann <kraxel(a)redhat.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> See http://review.coreboot.org/6795 for details. -gerrit

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Patch merged into coreboot/master: dac17a7 roda/rk886ex: Move dummy DCC ON# to finalize stage
by gerrit＠coreboot.org 11 Sep '14

11 Sep '14

the following patch was just integrated into master: commit dac17a74156a3eea2cc92c336b552165741119cb Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Fri Sep 5 23:53:39 2014 +0200 roda/rk886ex: Move dummy DCC ON# to finalize stage During Vladimir's ACPI cleanups, this was moved into the mainboard's enable stage, which will prevent the VGA option rom from executing correctly. Move it to the finalize stage to make sure it runs after all initialize functions have been called. Change-Id: I0fcca4d4a95f89382f377ce923f82ecb71467fd8 Signed-off-by: Stefan Reinauer <reinauer(a)google.com> Reviewed-on: http://review.coreboot.org/6845 Reviewed-by: Vladimir Serbinenko <phcoder(a)gmail.com> Tested-by: build bot (Jenkins) See http://review.coreboot.org/6845 for details. -gerrit

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New patch to review for coreboot: 94f6eee tegra124/nyan: various fixes and additions
by Isaac Christensen 10 Sep '14

10 Sep '14

Isaac Christensen (isaac.christensen(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6870 -gerrit commit 94f6eee46ae52a65165834c1ccbe7d8978389d3a Author: Hung-Te Lin <hungte(a)chromium.org> Date: Mon Oct 21 21:43:03 2013 +0800 tegra124/nyan: various fixes and additions Tegra124: SDMMC: Configure base clock frequency. Reviewed-on: https://chromium-review.googlesource.com/173841 (cherry picked from commit d3157e9a380cfb018cc69a1f23f277c3c5b680a6) Tegra124: SDMMC: Configure pinmux for MMC 3/4. Reviewed-on: https://chromium-review.googlesource.com/174011 (cherry picked from commit 55af9a86a56d6bc0ce9bcff4fd5226a60ae2033b) tegra124: Move DMA-related #defines and definitions to header Reviewed-on: https://chromium-review.googlesource.com/174444 (cherry picked from commit 9d917927a5b7151958289469b9049ac91efa41e3) tegra124: Assign console address for kernel. Reviewed-on: https://chromium-review.googlesource.com/174486 (cherry picked from commit 36e9370f30bd173879958d164156997841ec4e9c) nyan: Fix up the gpio indices in chromeos.c. Reviewed-on: https://chromium-review.googlesource.com/174418 (cherry picked from commit fba4ae1080c19f11abe1205b871ada14db996c61) Nyan: turn on the backlight. Reviewed-on: https://chromium-review.googlesource.com/174533 (cherry picked from commit 12649c9611981dd8d6567ba0238c8b8247c52215) tegra124: Fix the disp1 source field. Reviewed-on: https://chromium-review.googlesource.com/174701 (cherry picked from commit eed380e09075e1eef0bde7d1bb15c4343f30bfe0) nyan: set up the aux channel i2c interface Reviewed-on: https://chromium-review.googlesource.com/174620 (cherry picked from commit ea81cb44a1c11cd78643c69ac818304cd393749e) tegra124: fix typos in the clock code. Reviewed-on: https://chromium-review.googlesource.com/174684 (cherry picked from commit 72365c33693db4eb6e01032938221f592b7e5a02) tegra124: Revamp clock source/divisor configuration Reviewed-on: https://chromium-review.googlesource.com/174804 (cherry picked from commit 3f31a634f69595bcc6a473301d1492c97a767809) tegra: Add gpio_output_open_drain() function Reviewed-on: https://chromium-review.googlesource.com/174650 (cherry picked from commit bc1c28926810e722e9b82339ea0585d083e3fa8c) tegra124: add nvidia-generated files Reviewed-on: https://chromium-review.googlesource.com/174610 (cherry picked from commit 7706f3200f7fc11b7a443f336bff6a37afa94652) nyan: Ignore the dev mode GPIO. Reviewed-on: https://chromium-review.googlesource.com/174837 (cherry picked from commit 9513e608f3063fdb3e9d8bd04e6e5fe35a5bfcee) Tegra124: Add support for the ARM architectural timer. Reviewed-on: https://chromium-review.googlesource.com/174835 (cherry picked from commit 25a91fcf7e79cc450caa59bc6b65f954bb96ac6c) nyan: Initialize the ARM architectural timer in the RAM stage. Reviewed-on: https://chromium-review.googlesource.com/174836 (cherry picked from commit 581f592c12de91c0cf8279ede2850e38dd0cd2e8) tegra124: nyan: Move mainboard level clock stuff into the mainboard source. Reviewed-on: https://chromium-review.googlesource.com/174843 (cherry picked from commit 5ab100b0bad22814261f9b755b59394562c9145a) tegra124: add some explanatory text about U7.1 computations. Reviewed-on: https://chromium-review.googlesource.com/173910 (cherry picked from commit 822cad0ceeceeb5160c8216e05eec13fd04a6413) Set the EC SPI clock source to PLLP and divide down to around 5MHz Reviewed-on: https://chromium-review.googlesource.com/173954 (cherry picked from commit c0e22d76d3887ca1f727443a47db38dec12c0b74) nyan: Move non-essential configuration out of bootblock and into ram stage. Reviewed-on: https://chromium-review.googlesource.com/174844 (cherry picked from commit dad7f68c76f7b83edacd8b22c9dbd3f0ff027397) tegra124: clocks: Save some IOs in clock_enable_clear_reset. Reviewed-on: https://chromium-review.googlesource.com/174845 (cherry picked from commit 81b977a2758d42471667e2cbe31f160dfda5bca4) tegra124: re-write SPI driver w/ full duplex support Reviewed-on: https://chromium-review.googlesource.com/174446 (cherry picked from commit 51c9a34240d6a068780a7d1c27b032b56b2d3e54) tegra124: move SPI-related structures from .c to .h Reviewed-on: https://chromium-review.googlesource.com/174637 (cherry picked from commit 36760a4463c2c33f494ca7ea5a36810fa4502058) tegra124: add frame header info to SPI channel struct Reviewed-on: https://chromium-review.googlesource.com/174638 (cherry picked from commit e24773eb946e2c4cb5e828f055d45d92bd1a4f9f) tegra124: re-factor tegra_spi_init() Reviewed-on: https://chromium-review.googlesource.com/174639 (cherry picked from commit 88354b996459a702c36604f5f92c24e63df8de7e) nyan: Set CrOS EC frame header parameters for SPI Reviewed-on: https://chromium-review.googlesource.com/174710 (cherry picked from commit 29173ba5863eebb2864a8384435cde2f0d5ca233) tegra124: Add Rx frame header support to SPI code Reviewed-on: https://chromium-review.googlesource.com/174711 (cherry picked from commit 1d1630e770804649ef74d31db194d3bde9968832) tegra124: add support for the Serial Output Resource (sor) Reviewed-on: https://chromium-review.googlesource.com/174612 (cherry picked from commit 3eebd10afea4498380582e04560af89126911ed9) nyan: tegra124: Enable I, D and L2 caches in romstage. Reviewed-on: https://chromium-review.googlesource.com/173777 (cherry picked from commit 74512b7ecfbd50f01a25677307084699ee8c6007) tegra and tegra124: Bring up graphics Reviewed-on: https://chromium-review.googlesource.com/174613 (cherry picked from commit 7e944208a176cdac44a31e2a9961c8bd5dc4ece8) nyan: Move the DMA memory region. Reviewed-on: https://chromium-review.googlesource.com/174953 (cherry picked from commit c66e22859252eaebceb07a3118ac61f4cf6289eb) tegra124: Increase CBFS cache buffer size Reviewed-on: https://chromium-review.googlesource.com/174950 (cherry picked from commit 6dbb4e5f0d66c68df45ac73e3f223b856b715026) tegra124: Add USB PLL, PHY and EHCI setup code Reviewed-on: https://chromium-review.googlesource.com/174651 (cherry picked from commit ecd5c398ff6748a7d40089019471357b58d3a6ea) tegra124: add in some undocument clock source and PLL registers Reviewed-on: https://chromium-review.googlesource.com/174948 (cherry picked from commit 73fcc4981da6e4415b514eaafb42bc265ab0cd9a) tegra124: small cleanups of the code Reviewed-on: https://chromium-review.googlesource.com/174995 (cherry picked from commit 7256aba07e9567ef8d73f05e1f80c4d45fd57bda) Squashed 34 commits for tegra124 / nyan support. Change-Id: I050c7ad962e0d24550b0b33c9318e89c80d01f00 Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com> --- src/arch/arm/armv7/Makefile.inc | 3 + src/mainboard/google/nyan/Kconfig | 9 + src/mainboard/google/nyan/bootblock.c | 47 +- src/mainboard/google/nyan/chromeos.c | 12 +- src/mainboard/google/nyan/mainboard.c | 177 + src/mainboard/google/nyan/pmic.c | 7 +- src/mainboard/google/nyan/romstage.c | 86 +- src/soc/nvidia/tegra/dc.h | 1 + src/soc/nvidia/tegra/displayport.h | 316 + src/soc/nvidia/tegra/dp.c | 586 + src/soc/nvidia/tegra/gpio.c | 6 +- src/soc/nvidia/tegra/gpio.h | 14 +- src/soc/nvidia/tegra/usb.c | 120 + src/soc/nvidia/tegra/usb.h | 121 + src/soc/nvidia/tegra124/Kconfig | 13 + src/soc/nvidia/tegra124/Makefile.inc | 5 +- src/soc/nvidia/tegra124/clk_rst.h | 30 +- src/soc/nvidia/tegra124/clock.c | 131 +- src/soc/nvidia/tegra124/display.c | 178 +- src/soc/nvidia/tegra124/displayhack.c | 1333 + src/soc/nvidia/tegra124/dma.c | 87 - src/soc/nvidia/tegra124/dma.h | 132 + src/soc/nvidia/tegra124/include/soc/addressmap.h | 7 +- src/soc/nvidia/tegra124/include/soc/ardisplay.h | 42110 +++++++++++++++++++++ src/soc/nvidia/tegra124/include/soc/ardpaux.h | 1865 + src/soc/nvidia/tegra124/include/soc/arsor.h | 10227 +++++ src/soc/nvidia/tegra124/include/soc/clock.h | 64 +- src/soc/nvidia/tegra124/include/soc/display.h | 5 +- src/soc/nvidia/tegra124/pmc.h | 4 +- src/soc/nvidia/tegra124/sor.c | 169 + src/soc/nvidia/tegra124/sor.h | 908 + src/soc/nvidia/tegra124/spi.c | 714 +- src/soc/nvidia/tegra124/spi.h | 44 +- src/soc/nvidia/tegra124/sysctr.h | 54 + src/soc/nvidia/tegra124/usb.h | 50 + 35 files changed, 59040 insertions(+), 595 deletions(-) diff --git a/src/arch/arm/armv7/Makefile.inc b/src/arch/arm/armv7/Makefile.inc index bcd7d9e..2eb1af0 100644 --- a/src/arch/arm/armv7/Makefile.inc +++ b/src/arch/arm/armv7/Makefile.inc @@ -48,6 +48,9 @@ endif # CONFIG_ARCH_BOOTBLOCK_ARMV7 ifeq ($(CONFIG_ARCH_ROMSTAGE_ARMV7),y) romstage-y += cache.c +romstage-y += exception.c +romstage-y += exception_asm.S +romstage-y += mmu.c CFLAGS_romstage += $(armv7_flags) CPPFLAGS_romstage += $(armv7_flags) diff --git a/src/mainboard/google/nyan/Kconfig b/src/mainboard/google/nyan/Kconfig index 652cef1..4a14b15 100644 --- a/src/mainboard/google/nyan/Kconfig +++ b/src/mainboard/google/nyan/Kconfig @@ -26,6 +26,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select EC_GOOGLE_CHROMEEC select EC_GOOGLE_CHROMEEC_SPI select MAINBOARD_HAS_BOOTBLOCK_INIT + select MAINBOARD_DO_NATIVE_VGA_INIT select BOARD_ROMSIZE_KB_1024 config MAINBOARD_DIR @@ -40,6 +41,14 @@ config DRAM_SIZE_MB int default 2048 +config DRAM_DMA_START + hex + default 0x90000000 + +config DRAM_DMA_SIZE + hex + default 0x00100000 + choice prompt "BCT boot media" default BCT_CFG_SPI diff --git a/src/mainboard/google/nyan/bootblock.c b/src/mainboard/google/nyan/bootblock.c index 49133ca..ca8eca4 100644 --- a/src/mainboard/google/nyan/bootblock.c +++ b/src/mainboard/google/nyan/bootblock.c @@ -17,50 +17,47 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include <arch/io.h> #include <bootblock_common.h> #include <console/console.h> #include <device/i2c.h> +#include <soc/addressmap.h> #include <soc/clock.h> #include <soc/nvidia/tegra/i2c.h> +#include <soc/nvidia/tegra124/clk_rst.h> #include <soc/nvidia/tegra124/pinmux.h> #include <soc/nvidia/tegra124/spi.h> /* FIXME: move back to soc code? */ #include "pmic.h" +static struct clk_rst_ctlr *clk_rst = (void *)TEGRA_CLK_RST_BASE; + +static void set_clock_sources(void) +{ + /* UARTA gets PLLP, deactivate CLK_UART_DIV_OVERRIDE */ + writel(PLLP << CLK_SOURCE_SHIFT, &clk_rst->clk_src_uarta); + + clock_configure_source(mselect, PLLP, 102000); + + /* TODO: is the 1.333MHz correct? This may have always been bogus... */ + clock_configure_source(i2c5, CLK_M, 1333); +} + void bootblock_mainboard_init(void) { - clock_config(); + set_clock_sources(); + + clock_enable_clear_reset(CLK_L_CACHE2 | CLK_L_TMR, + CLK_H_I2C5 | CLK_H_APBDMA, + 0, CLK_V_MSELECT, 0); - // I2C1 clock. - pinmux_set_config(PINMUX_GEN1_I2C_SCL_INDEX, - PINMUX_GEN1_I2C_SCL_FUNC_I2C1 | PINMUX_INPUT_ENABLE); - // I2C1 data. - pinmux_set_config(PINMUX_GEN1_I2C_SDA_INDEX, - PINMUX_GEN1_I2C_SDA_FUNC_I2C1 | PINMUX_INPUT_ENABLE); - // I2C2 clock. - pinmux_set_config(PINMUX_GEN2_I2C_SCL_INDEX, - PINMUX_GEN2_I2C_SCL_FUNC_I2C2 | PINMUX_INPUT_ENABLE); - // I2C2 data. - pinmux_set_config(PINMUX_GEN2_I2C_SDA_INDEX, - PINMUX_GEN2_I2C_SDA_FUNC_I2C2 | PINMUX_INPUT_ENABLE); - // I2C3 (cam) clock. - pinmux_set_config(PINMUX_CAM_I2C_SCL_INDEX, - PINMUX_CAM_I2C_SCL_FUNC_I2C3 | PINMUX_INPUT_ENABLE); - // I2C3 (cam) data. - pinmux_set_config(PINMUX_CAM_I2C_SDA_INDEX, - PINMUX_CAM_I2C_SDA_FUNC_I2C3 | PINMUX_INPUT_ENABLE); // I2C5 (PMU) clock. pinmux_set_config(PINMUX_PWR_I2C_SCL_INDEX, PINMUX_PWR_I2C_SCL_FUNC_I2CPMU | PINMUX_INPUT_ENABLE); // I2C5 (PMU) data. pinmux_set_config(PINMUX_PWR_I2C_SDA_INDEX, PINMUX_PWR_I2C_SDA_FUNC_I2CPMU | PINMUX_INPUT_ENABLE); - - i2c_init(0); - i2c_init(1); - i2c_init(2); i2c_init(4); - pmic_init(4); /* SPI4 data out (MOSI) */ @@ -75,6 +72,6 @@ void bootblock_mainboard_init(void) /* SPI4 chip select 0 */ pinmux_set_config(PINMUX_SDMMC1_DAT3_INDEX, PINMUX_SDMMC1_DAT3_FUNC_SPI4 | PINMUX_INPUT_ENABLE); -// spi_init(); + tegra_spi_init(4); } diff --git a/src/mainboard/google/nyan/chromeos.c b/src/mainboard/google/nyan/chromeos.c index 5b8b9c0..6377fb2 100644 --- a/src/mainboard/google/nyan/chromeos.c +++ b/src/mainboard/google/nyan/chromeos.c @@ -33,7 +33,7 @@ void fill_lb_gpios(struct lb_gpios *gpios) /* Write Protect: active low */ gpios->gpios[count].port = GPIO_R1_INDEX; gpios->gpios[count].polarity = ACTIVE_LOW; - gpios->gpios[count].value = gpio_get_in_value(GPIO_R1_INDEX); + gpios->gpios[count].value = gpio_get_in_value(GPIO(R1)); strncpy((char *)gpios->gpios[count].name, "write protect", GPIO_MAX_NAME_LENGTH); count++; @@ -49,14 +49,14 @@ void fill_lb_gpios(struct lb_gpios *gpios) /* Lid: active high */ gpios->gpios[count].port = GPIO_R4_INDEX; gpios->gpios[count].polarity = ACTIVE_HIGH; - gpios->gpios[count].value = gpio_get_in_value(GPIO_R4_INDEX); + gpios->gpios[count].value = gpio_get_in_value(GPIO(R4)); strncpy((char *)gpios->gpios[count].name, "lid", GPIO_MAX_NAME_LENGTH); count++; /* Power: active low */ gpios->gpios[count].port = GPIO_Q0_INDEX; gpios->gpios[count].polarity = ACTIVE_LOW; - gpios->gpios[count].value = gpio_get_in_value(GPIO_Q0_INDEX); + gpios->gpios[count].value = gpio_get_in_value(GPIO(Q0)); strncpy((char *)gpios->gpios[count].name, "power", GPIO_MAX_NAME_LENGTH); count++; @@ -77,7 +77,7 @@ void fill_lb_gpios(struct lb_gpios *gpios) int get_developer_mode_switch(void) { - return gpio_get_in_value(GPIO_Q6_INDEX); + return 0; } int get_recovery_mode_switch(void) @@ -85,7 +85,7 @@ int get_recovery_mode_switch(void) uint32_t ec_events; /* The GPIO is active low. */ - if (!gpio_get_in_value(GPIO_Q7_INDEX)) // RECMODE_GPIO + if (!gpio_get_in_value(GPIO(Q7))) // RECMODE_GPIO return 1; ec_events = google_chromeec_get_events_b(); @@ -95,5 +95,5 @@ int get_recovery_mode_switch(void) int get_write_protect_state(void) { - return !gpio_get_in_value(GPIO_R1_INDEX); + return !gpio_get_in_value(GPIO(R1)); } diff --git a/src/mainboard/google/nyan/mainboard.c b/src/mainboard/google/nyan/mainboard.c index c7258ff..a25c91c 100644 --- a/src/mainboard/google/nyan/mainboard.c +++ b/src/mainboard/google/nyan/mainboard.c @@ -17,9 +17,47 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include <arch/io.h> #include <device/device.h> #include <boot/coreboot_tables.h> +#include <soc/addressmap.h> +#include <soc/clock.h> +#include <soc/nvidia/tegra/i2c.h> +#include <soc/nvidia/tegra124/clk_rst.h> #include <soc/nvidia/tegra124/gpio.h> +#include <soc/nvidia/tegra124/pmc.h> +#include <soc/nvidia/tegra124/spi.h> +#include <soc/nvidia/tegra124/usb.h> + +static struct clk_rst_ctlr *clk_rst = (void *)TEGRA_CLK_RST_BASE; + +static void set_clock_sources(void) +{ + clock_configure_source(i2c1, CLK_M, 1333); + clock_configure_source(i2c2, CLK_M, 1333); + clock_configure_source(i2c3, CLK_M, 1333); + clock_configure_source(i2c4, CLK_M, 1333); + + clock_configure_source(sbc1, PLLP, 5000); + + /* + * MMC3 and MMC4: Set base clock frequency for SD Clock to Tegra MMC's + * maximum speed (48MHz) so we can change SDCLK by second stage divisor + * in payloads, without touching base clock. + */ + clock_configure_source(sdmmc3, PLLP, 48000); + clock_configure_source(sdmmc4, PLLP, 48000); + + /* PLLP and PLLM are switched for HOST1x for no apparent reason. */ + write32(4 /* PLLP! */ << CLK_SOURCE_SHIFT | + /* TODO(rminnich): The divisor isn't accurate enough to get to + * 144MHz (it goes to 163 instead). What should we do here? */ + CLK_DIVIDER(TEGRA_PLLP_KHZ, 144000), + &clk_rst->clk_src_host1x); + + /* DISP1 doesn't support a divisor. Use PLLC which runs at 600MHz. */ + clock_configure_source(disp1, PLLC, 600000); +} static void setup_pinmux(void) { @@ -52,11 +90,139 @@ static void setup_pinmux(void) pinmux_set_config(PINMUX_ULPI_STP_INDEX, PINMUX_ULPI_STP_FUNC_SPI1 | PINMUX_PULL_NONE | PINMUX_INPUT_ENABLE); + + // I2C1 clock. + pinmux_set_config(PINMUX_GEN1_I2C_SCL_INDEX, + PINMUX_GEN1_I2C_SCL_FUNC_I2C1 | PINMUX_INPUT_ENABLE); + // I2C1 data. + pinmux_set_config(PINMUX_GEN1_I2C_SDA_INDEX, + PINMUX_GEN1_I2C_SDA_FUNC_I2C1 | PINMUX_INPUT_ENABLE); + // I2C2 clock. + pinmux_set_config(PINMUX_GEN2_I2C_SCL_INDEX, + PINMUX_GEN2_I2C_SCL_FUNC_I2C2 | PINMUX_INPUT_ENABLE); + // I2C2 data. + pinmux_set_config(PINMUX_GEN2_I2C_SDA_INDEX, + PINMUX_GEN2_I2C_SDA_FUNC_I2C2 | PINMUX_INPUT_ENABLE); + // I2C3 (cam) clock. + pinmux_set_config(PINMUX_CAM_I2C_SCL_INDEX, + PINMUX_CAM_I2C_SCL_FUNC_I2C3 | PINMUX_INPUT_ENABLE); + // I2C3 (cam) data. + pinmux_set_config(PINMUX_CAM_I2C_SDA_INDEX, + PINMUX_CAM_I2C_SDA_FUNC_I2C3 | PINMUX_INPUT_ENABLE); + // I2C4 (DDC) clock. + pinmux_set_config(PINMUX_DDC_SCL_INDEX, + PINMUX_DDC_SCL_FUNC_I2C4 | PINMUX_INPUT_ENABLE); + // I2C4 (DDC) data. + pinmux_set_config(PINMUX_DDC_SDA_INDEX, + PINMUX_DDC_SDA_FUNC_I2C4 | PINMUX_INPUT_ENABLE); + + // TODO(hungte) Revice pinmux setup, make nice little SoC functions for + // every single logical thing instead of dumping a wall of code below. + uint32_t pin_up = PINMUX_PULL_UP | PINMUX_INPUT_ENABLE, + pin_up3 = (PINMUX_PULL_UP | PINMUX_INPUT_ENABLE | + PINMUX_TRISTATE), + pin_down = PINMUX_PULL_DOWN | PINMUX_INPUT_ENABLE, + pin_none = PINMUX_PULL_NONE | PINMUX_INPUT_ENABLE; + + // MMC3 + pinmux_set_config(PINMUX_SDMMC3_CLK_INDEX, + PINMUX_SDMMC3_CLK_FUNC_SDMMC3 | pin_none); + pinmux_set_config(PINMUX_SDMMC3_CMD_INDEX, + PINMUX_SDMMC3_CMD_FUNC_SDMMC3 | pin_up); + pinmux_set_config(PINMUX_SDMMC3_DAT0_INDEX, + PINMUX_SDMMC3_DAT0_FUNC_SDMMC3 | pin_up); + pinmux_set_config(PINMUX_SDMMC3_DAT1_INDEX, + PINMUX_SDMMC3_DAT1_FUNC_SDMMC3 | pin_up); + pinmux_set_config(PINMUX_SDMMC3_DAT2_INDEX, + PINMUX_SDMMC3_DAT2_FUNC_SDMMC3 | pin_up); + pinmux_set_config(PINMUX_SDMMC3_DAT3_INDEX, + PINMUX_SDMMC3_DAT3_FUNC_SDMMC3 | pin_up); + pinmux_set_config(PINMUX_SDMMC3_CLK_LB_IN_INDEX, + PINMUX_SDMMC3_CLK_LB_IN_FUNC_SDMMC3 | pin_up3); + pinmux_set_config(PINMUX_SDMMC3_CLK_LB_OUT_INDEX, + PINMUX_SDMMC3_CLK_LB_OUT_FUNC_SDMMC3 | pin_down); + + // MMC3 Card Detect pin. + gpio_input_pullup(GPIO(V2)); + // Enable MMC power. + gpio_output(GPIO(R0), 1); + + // MMC4 + pinmux_set_config(PINMUX_SDMMC4_CLK_INDEX, + PINMUX_SDMMC4_CLK_FUNC_SDMMC4 | pin_none); + pinmux_set_config(PINMUX_SDMMC4_CMD_INDEX, + PINMUX_SDMMC4_CMD_FUNC_SDMMC4 | pin_up); + pinmux_set_config(PINMUX_SDMMC4_DAT0_INDEX, + PINMUX_SDMMC4_DAT0_FUNC_SDMMC4 | pin_up); + pinmux_set_config(PINMUX_SDMMC4_DAT1_INDEX, + PINMUX_SDMMC4_DAT1_FUNC_SDMMC4 | pin_up); + pinmux_set_config(PINMUX_SDMMC4_DAT2_INDEX, + PINMUX_SDMMC4_DAT2_FUNC_SDMMC4 | pin_up); + pinmux_set_config(PINMUX_SDMMC4_DAT3_INDEX, + PINMUX_SDMMC4_DAT3_FUNC_SDMMC4 | pin_up); + pinmux_set_config(PINMUX_SDMMC4_DAT4_INDEX, + PINMUX_SDMMC4_DAT4_FUNC_SDMMC4 | pin_up); + pinmux_set_config(PINMUX_SDMMC4_DAT5_INDEX, + PINMUX_SDMMC4_DAT5_FUNC_SDMMC4 | pin_up); + pinmux_set_config(PINMUX_SDMMC4_DAT6_INDEX, + PINMUX_SDMMC4_DAT6_FUNC_SDMMC4 | pin_up); + pinmux_set_config(PINMUX_SDMMC4_DAT7_INDEX, + PINMUX_SDMMC4_DAT7_FUNC_SDMMC4 | pin_up); + + /* TODO: This is supposed to work with the USB special function pinmux, + * but it doesn't. Go with GPIOs for now and solve the problem later. */ + gpio_output_open_drain(GPIO(N4), 1); /* USB VBUS EN0 */ + gpio_output_open_drain(GPIO(N5), 1); /* USB VBUS EN1 */ +} + +static void setup_kernel_info(void) +{ + // Setup required information for Linux kernel. + + // pmc.odmdata: [18:19]: console type, [15:17]: UART id. + // TODO(hungte) This should be done by filling BCT values, or derived + // from CONFIG_CONSOLE_SERIAL_UART[A-E]. Right now we simply copy the + // value defined in BCT. + struct tegra_pmc_regs *pmc = (void*)TEGRA_PMC_BASE; + writel(0x80080000, &pmc->odmdata); +} + +static void setup_ec_spi(void) +{ + struct tegra_spi_channel *spi; + + spi = tegra_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS); + + /* Set frame header for use by CrOS EC */ + spi->frame_header = 0xec; + spi->rx_frame_header_enable = 1; } static void mainboard_init(device_t dev) { + set_clock_sources(); + clock_enable_clear_reset(CLK_L_GPIO | CLK_L_I2C1 | + CLK_L_SDMMC4 | CLK_L_USBD, + CLK_H_EMC | CLK_H_I2C2 | CLK_H_SBC1 | + CLK_H_PMC | CLK_H_MEM | CLK_H_USB3, + CLK_U_I2C3 | CLK_U_CSITE | CLK_U_SDMMC3, + CLK_V_I2C4, + CLK_W_DVFS); + + usb_setup_utmip1(); + /* USB2 is the camera, we don't need it in firmware */ + usb_setup_utmip3(); + setup_pinmux(); + + i2c_init(0); + i2c_init(1); + i2c_init(2); + i2c_init(3); + + setup_kernel_info(); + clock_init_arm_generic_timer(); + setup_ec_spi(); } static void mainboard_enable(device_t dev) @@ -68,3 +234,14 @@ struct chip_operations mainboard_ops = { .name = "nyan", .enable_dev = mainboard_enable, }; + +void lb_board(struct lb_header *header) +{ + struct lb_range *dma; + + dma = (struct lb_range *)lb_new_record(header); + dma->tag = LB_TAB_DMA; + dma->size = sizeof(*dma); + dma->range_start = CONFIG_DRAM_DMA_START; + dma->range_size = CONFIG_DRAM_DMA_SIZE; +} diff --git a/src/mainboard/google/nyan/pmic.c b/src/mainboard/google/nyan/pmic.c index ab951ea..f52a48b 100644 --- a/src/mainboard/google/nyan/pmic.c +++ b/src/mainboard/google/nyan/pmic.c @@ -61,9 +61,14 @@ static struct pmic_write pmic_writes[] = * NOTE: We do this early because doing it later seems to hose the CPU * power rail/partition startup. Need to debug. */ - { 0x16, 0x3f } + { 0x16, 0x3f }, /* Don't write LDCONTROL - it's already 0xFF, i.e. all LDOs enabled. */ + /* panel power GPIO O4. Set mode for GPIO4 (0x0c to 7), then set + * the value (register 0x20 bit 4) + */ + { 0x0c, 0x07 }, + { 0x20, 0x10 }, }; void pmic_init(unsigned bus) diff --git a/src/mainboard/google/nyan/romstage.c b/src/mainboard/google/nyan/romstage.c index 5a66dde..a31f1f1 100644 --- a/src/mainboard/google/nyan/romstage.c +++ b/src/mainboard/google/nyan/romstage.c @@ -17,6 +17,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include <arch/cache.h> +#include <arch/cpu.h> +#include <arch/exception.h> #include <arch/stages.h> #include <device/device.h> #include <cbfs.h> @@ -25,11 +28,78 @@ #include "soc/nvidia/tegra124/chip.h" #include <soc/display.h> +// Convenient shorthand (in MB) +#define DRAM_START (CONFIG_SYS_SDRAM_BASE >> 20) +#define DRAM_SIZE CONFIG_DRAM_SIZE_MB +#define DRAM_END (DRAM_START + DRAM_SIZE) /* plus one... */ + +enum { + L2CTLR_ECC_PARITY = 0x1 << 21, + L2CTLR_TAG_RAM_LATENCY_MASK = 0x7 << 6, + L2CTLR_TAG_RAM_LATENCY_CYCLES_3 = 2 << 6, + L2CTLR_DATA_RAM_LATENCY_MASK = 0x7 << 0, + L2CTLR_DATA_RAM_LATENCY_CYCLES_3 = 2 << 0 +}; + +enum { + L2ACTLR_FORCE_L2_LOGIC_CLOCK_ENABLE_ACTIVE = 0x1 << 27, + L2ACTLR_ENABLE_HAZARD_DETECT_TIMEOUT = 0x1 << 7, + L2ACTLR_DISABLE_CLEAN_EVICT_PUSH_EXTERNAL = 0x1 << 3 +}; + +/* Configures L2 Control Register to use 3 cycles for DATA/TAG RAM latency. */ +static void configure_l2ctlr(void) +{ + uint32_t val; + + val = read_l2ctlr(); + val &= ~(L2CTLR_DATA_RAM_LATENCY_MASK | L2CTLR_TAG_RAM_LATENCY_MASK); + val |= (L2CTLR_DATA_RAM_LATENCY_CYCLES_3 | L2CTLR_TAG_RAM_LATENCY_CYCLES_3 | + L2CTLR_ECC_PARITY); + write_l2ctlr(val); +} + +/* Configures L2 Auxiliary Control Register for Cortex A15. */ +static void configure_l2actlr(void) +{ + uint32_t val; + + val = read_l2actlr(); + val |= (L2ACTLR_DISABLE_CLEAN_EVICT_PUSH_EXTERNAL | + L2ACTLR_ENABLE_HAZARD_DETECT_TIMEOUT | + L2ACTLR_FORCE_L2_LOGIC_CLOCK_ENABLE_ACTIVE); + write_l2actlr(val); +} + void main(void) { - void *entry; - const struct device *soc; - const struct soc_nvidia_tegra124_config *config; + // Globally disable MMU, caches and branch prediction (these should + // already be disabled by default on reset). + uint32_t sctlr = read_sctlr(); + sctlr &= ~(SCTLR_M | SCTLR_C | SCTLR_Z | SCTLR_I); + write_sctlr(sctlr); + + arm_invalidate_caches(); + + // Renable icache and branch prediction. + sctlr = read_sctlr(); + sctlr |= SCTLR_Z | SCTLR_I; + write_sctlr(sctlr); + + configure_l2ctlr(); + configure_l2actlr(); + + mmu_init(); + mmu_config_range(0, DRAM_START, DCACHE_OFF); + mmu_config_range(DRAM_START, DRAM_SIZE, DCACHE_WRITEBACK); + mmu_config_range(CONFIG_DRAM_DMA_START >> 20, + CONFIG_DRAM_DMA_SIZE >> 20, DCACHE_OFF); + mmu_config_range(DRAM_END, 4096 - DRAM_END, DCACHE_OFF); + mmu_disable_range(0, 1); + dcache_invalidate_all(); + dcache_mmu_enable(); + + exception_init(); /* for quality of the user interface, it's important to get * the video going ASAP. Because there are long delays in some @@ -39,15 +109,17 @@ void main(void) * early as we can in the RW stage, but never in the RO stage. */ - soc = dev_find_slot(DEVICE_PATH_CPU_CLUSTER, 0); + const struct device *soc = dev_find_slot(DEVICE_PATH_CPU_CLUSTER, 0); printk(BIOS_SPEW, "s%s: soc is %p\n", __func__, soc); - if (soc && soc->chip_info){ - config = soc->chip_info; + if (soc && soc->chip_info) { + const struct soc_nvidia_tegra124_config *config = + soc->chip_info; setup_display((struct soc_nvidia_tegra124_config *)config); } cbmem_initialize_empty(); - entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, "fallback/coreboot_ram"); + void *entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, + "fallback/coreboot_ram"); stage_exit(entry); } diff --git a/src/soc/nvidia/tegra/dc.h b/src/soc/nvidia/tegra/dc.h index 33dbe53..dac2065 100644 --- a/src/soc/nvidia/tegra/dc.h +++ b/src/soc/nvidia/tegra/dc.h @@ -561,4 +561,5 @@ struct disp_ctl_win { }; void display_startup(device_t dev); +void dp_bringup(u32 winb_addr); #endif /* __SOC_NVIDIA_TEGRA_DC_H */ diff --git a/src/soc/nvidia/tegra/displayport.h b/src/soc/nvidia/tegra/displayport.h new file mode 100644 index 0000000..8a57170 --- /dev/null +++ b/src/soc/nvidia/tegra/displayport.h @@ -0,0 +1,316 @@ +/* + * drivers/video/tegra/dc/dpaux_regs.h + * + * Copyright (c) 2011, NVIDIA Corporation. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef __SOC_NVIDIA_TEGRA_DISPLAYPORT_H__ +#define __SOC_NVIDIA_TEGRA_DISPLAYPORT_H__ + +/* things we can't get rid of just yet. */ +#define DPAUX_INTR_EN_AUX (0x1) +#define DPAUX_INTR_AUX (0x5) +#define DPAUX_DP_AUXDATA_WRITE_W(i) (0x9 + 4*(i)) +#define DPAUX_DP_AUXDATA_READ_W(i) (0x19 + 4*(i)) +#define DPAUX_DP_AUXADDR (0x29) +#define DPAUX_DP_AUXCTL (0x2d) +#define DPAUX_DP_AUXCTL_CMDLEN_SHIFT (0) +#define DPAUX_DP_AUXCTL_CMDLEN_FIELD (0xff) +#define DPAUX_DP_AUXCTL_CMD_SHIFT (12) +#define DPAUX_DP_AUXCTL_CMD_MASK (0xf << 12) +#define DPAUX_DP_AUXCTL_CMD_I2CWR (0 << 12) +#define DPAUX_DP_AUXCTL_CMD_I2CRD (1 << 12) +#define DPAUX_DP_AUXCTL_CMD_I2CREQWSTAT (2 << 12) +#define DPAUX_DP_AUXCTL_CMD_MOTWR (4 << 12) +#define DPAUX_DP_AUXCTL_CMD_MOTRD (5 << 12) +#define DPAUX_DP_AUXCTL_CMD_MOTREQWSTAT (6 << 12) +#define DPAUX_DP_AUXCTL_CMD_AUXWR (8 << 12) +#define DPAUX_DP_AUXCTL_CMD_AUXRD (9 << 12) +#define DPAUX_DP_AUXCTL_TRANSACTREQ_SHIFT (16) +#define DPAUX_DP_AUXCTL_TRANSACTREQ_MASK (0x1 << 16) +#define DPAUX_DP_AUXCTL_TRANSACTREQ_DONE (0 << 16) +#define DPAUX_DP_AUXCTL_TRANSACTREQ_PENDING (1 << 16) +#define DPAUX_DP_AUXCTL_RST_SHIFT (31) +#define DPAUX_DP_AUXCTL_RST_DEASSERT (0 << 31) +#define DPAUX_DP_AUXCTL_RST_ASSERT (1 << 31) +#define DPAUX_DP_AUXSTAT (0x31) +#define DPAUX_DP_AUXSTAT_HPD_STATUS_SHIFT (28) +#define DPAUX_DP_AUXSTAT_HPD_STATUS_UNPLUG (0 << 28) +#define DPAUX_DP_AUXSTAT_HPD_STATUS_PLUGGED (1 << 28) +#define DPAUX_DP_AUXSTAT_AUXCTL_STATE_SHIFT (20) +#define DPAUX_DP_AUXSTAT_AUXCTL_STATE_MASK (0xf << 20) +#define DPAUX_DP_AUXSTAT_AUXCTL_STATE_IDLE (0 << 20) +#define DPAUX_DP_AUXSTAT_AUXCTL_STATE_SYNC (1 << 20) +#define DPAUX_DP_AUXSTAT_AUXCTL_STATE_START1 (2 << 20) +#define DPAUX_DP_AUXSTAT_AUXCTL_STATE_COMMAND (3 << 20) +#define DPAUX_DP_AUXSTAT_AUXCTL_STATE_ADDRESS (4 << 20) +#define DPAUX_DP_AUXSTAT_AUXCTL_STATE_LENGTH (5 << 20) +#define DPAUX_DP_AUXSTAT_AUXCTL_STATE_WRITE1 (6 << 20) +#define DPAUX_DP_AUXSTAT_AUXCTL_STATE_READ1 (7 << 20) +#define DPAUX_DP_AUXSTAT_AUXCTL_STATE_GET_M (8 << 20) +#define DPAUX_DP_AUXSTAT_AUXCTL_STATE_STOP1 (9 << 20) +#define DPAUX_DP_AUXSTAT_AUXCTL_STATE_STOP2 (10 << 20) +#define DPAUX_DP_AUXSTAT_AUXCTL_STATE_REPLY (11 << 20) +#define DPAUX_DP_AUXSTAT_AUXCTL_STATE_CLEANUP (12 << 20) +#define DPAUX_DP_AUXSTAT_REPLYTYPE_SHIFT (16) +#define DPAUX_DP_AUXSTAT_REPLYTYPE_MASK (0xf << 16) +#define DPAUX_DP_AUXSTAT_REPLYTYPE_ACK (0 << 16) +#define DPAUX_DP_AUXSTAT_REPLYTYPE_NACK (1 << 16) +#define DPAUX_DP_AUXSTAT_REPLYTYPE_DEFER (2 << 16) +#define DPAUX_DP_AUXSTAT_REPLYTYPE_I2CNACK (4 << 16) +#define DPAUX_DP_AUXSTAT_REPLYTYPE_I2CDEFER (8 << 16) +#define DPAUX_DP_AUXSTAT_NO_STOP_ERROR_SHIFT (11) +#define DPAUX_DP_AUXSTAT_NO_STOP_ERROR_NOT_PENDING (0 << 11) +#define DPAUX_DP_AUXSTAT_NO_STOP_ERROR_PENDING (1 << 11) +#define DPAUX_DP_AUXSTAT_SINKSTAT_ERROR_SHIFT (10) +#define DPAUX_DP_AUXSTAT_SINKSTAT_ERROR_NOT_PENDING (0 << 10) +#define DPAUX_DP_AUXSTAT_SINKSTAT_ERROR_PENDING (1 << 10) +#define DPAUX_DP_AUXSTAT_RX_ERROR_SHIFT (9) +#define DPAUX_DP_AUXSTAT_RX_ERROR_NOT_PENDING (0 << 9) +#define DPAUX_DP_AUXSTAT_RX_ERROR_PENDING (1 << 9) +#define DPAUX_DP_AUXSTAT_TIMEOUT_ERROR_SHIFT (8) +#define DPAUX_DP_AUXSTAT_TIMEOUT_ERROR_NOT_PENDING (0 << 8) +#define DPAUX_DP_AUXSTAT_TIMEOUT_ERROR_PENDING (1 << 8) +#define DPAUX_DP_AUXSTAT_REPLY_M_SHIFT (0) +#define DPAUX_DP_AUXSTAT_REPLY_M_MASK (0xff << 0) +#define DPAUX_HPD_CONFIG (0x3d) +#define DPAUX_HPD_IRQ_CONFIG (0x41) +#define DPAUX_DP_AUX_CONFIG (0x45) +#define DPAUX_HYBRID_PADCTL (0x49) +#define DPAUX_HYBRID_PADCTL_I2C_SDA_INPUT_RCV_SHIFT (15) +#define DPAUX_HYBRID_PADCTL_I2C_SDA_INPUT_RCV_DISABLE (0 << 15) +#define DPAUX_HYBRID_PADCTL_I2C_SDA_INPUT_RCV_ENABLE (1 << 15) +#define DPAUX_HYBRID_PADCTL_I2C_SCL_INPUT_RCV_SHIFT (14) +#define DPAUX_HYBRID_PADCTL_I2C_SCL_INPUT_RCV_DISABLE (0 << 14) +#define DPAUX_HYBRID_PADCTL_I2C_SCL_INPUT_RCV_ENABLE (1 << 14) +#define DPAUX_HYBRID_PADCTL_AUX_CMH_SHIFT (12) +#define DPAUX_HYBRID_PADCTL_AUX_CMH_DEFAULT_MASK (0x3 << 12) +#define DPAUX_HYBRID_PADCTL_AUX_CMH_V0_60 (0 << 12) +#define DPAUX_HYBRID_PADCTL_AUX_CMH_V0_64 (1 << 12) +#define DPAUX_HYBRID_PADCTL_AUX_CMH_V0_70 (2 << 12) +#define DPAUX_HYBRID_PADCTL_AUX_CMH_V0_56 (3 << 12) +#define DPAUX_HYBRID_PADCTL_AUX_DRVZ_SHIFT (8) +#define DPAUX_HYBRID_PADCTL_AUX_DRVZ_DEFAULT_MASK (0x7 << 8) +#define DPAUX_HYBRID_PADCTL_AUX_DRVZ_OHM_78 (0 << 8) +#define DPAUX_HYBRID_PADCTL_AUX_DRVZ_OHM_60 (1 << 8) +#define DPAUX_HYBRID_PADCTL_AUX_DRVZ_OHM_54 (2 << 8) +#define DPAUX_HYBRID_PADCTL_AUX_DRVZ_OHM_45 (3 << 8) +#define DPAUX_HYBRID_PADCTL_AUX_DRVZ_OHM_50 (4 << 8) +#define DPAUX_HYBRID_PADCTL_AUX_DRVZ_OHM_42 (5 << 8) +#define DPAUX_HYBRID_PADCTL_AUX_DRVZ_OHM_39 (6 << 8) +#define DPAUX_HYBRID_PADCTL_AUX_DRVZ_OHM_34 (7 << 8) +#define DPAUX_HYBRID_PADCTL_AUX_DRVI_SHIFT (2) +#define DPAUX_HYBRID_PADCTL_AUX_DRVI_DEFAULT_MASK (0x3f << 2) +#define DPAUX_HYBRID_PADCTL_AUX_INPUT_RCV_SHIFT (1) +#define DPAUX_HYBRID_PADCTL_AUX_INPUT_RCV_DISABLE (0 << 1) +#define DPAUX_HYBRID_PADCTL_AUX_INPUT_RCV_ENABLE (1 << 1) +#define DPAUX_HYBRID_PADCTL_MODE_SHIFT (0) +#define DPAUX_HYBRID_PADCTL_MODE_AUX (0) +#define DPAUX_HYBRID_PADCTL_MODE_I2C (1) +#define DPAUX_HYBRID_SPARE (0x4d) +#define DPAUX_HYBRID_SPARE_PAD_PWR_POWERUP (0) +#define DPAUX_HYBRID_SPARE_PAD_PWR_POWERDOWN (1) + +/* TODO: figure out which of the NV_ constants are the same as all the other + * display port standard constants. + */ + +#define DP_AUX_DEFER_MAX_TRIES 7 +#define DP_AUX_TIMEOUT_MAX_TRIES 2 +#define DP_POWER_ON_MAX_TRIES 3 +#define DP_CLOCK_RECOVERY_MAX_TRIES 7 +#define DP_CLOCK_RECOVERY_TOT_TRIES 15 + +#define DP_AUX_MAX_BYTES 16 + +#define DP_LCDVCC_TO_HPD_DELAY_MS 200 +#define DP_AUX_TIMEOUT_MS 40 +#define DP_DPCP_RETRY_SLEEP_NS 400 + +enum { + driveCurrent_Level0 = 0, + driveCurrent_Level1 = 1, + driveCurrent_Level2 = 2, + driveCurrent_Level3 = 3, +}; + +enum { + preEmphasis_Disabled = 0, + preEmphasis_Level1 = 1, + preEmphasis_Level2 = 2, + preEmphasis_Level3 = 3, +}; + +enum { + postCursor2_Level0 = 0, + postCursor2_Level1 = 1, + postCursor2_Level2 = 2, + postCursor2_Level3 = 3, + postCursor2_Supported +}; + + +/* the +10ms is the time for power rail going up from 10-90% or + 90%-10% on powerdown */ +/* Time from power-rail is turned on and aux/12c-over-aux is available */ +#define EDP_PWR_ON_TO_AUX_TIME_MS (200+10) +/* Time from power-rail is turned on and MainLink is available for LT */ +#define EDP_PWR_ON_TO_ML_TIME_MS (200+10) +/* Time from turning off power to turn-it on again (does not include post + poweron time) */ +#define EDP_PWR_OFF_TO_ON_TIME_MS (500+10) + +struct tegra_dc_dp_data { + struct tegra_dc *dc; + struct tegra_dc_sor_data *sor; + void *aux_base; + struct tegra_dc_mode *mode; + struct tegra_dc_dp_link_config link_cfg; +}; + + +/* DPCD definitions */ +/* you know, all the vendors pick their own set of defines. + * All of them. + * FIXME so we can use the ones in include/device/drm_dp_helper.h + */ +#define NV_DPCD_REV (0x00000000) +#define NV_DPCD_REV_MAJOR_SHIFT (4) +#define NV_DPCD_REV_MAJOR_MASK (0xf << 4) +#define NV_DPCD_REV_MINOR_SHIFT (0) +#define NV_DPCD_REV_MINOR_MASK (0xf) +#define NV_DPCD_MAX_LINK_BANDWIDTH (0x00000001) +#define NV_DPCD_MAX_LINK_BANDWIDTH_VAL_1_62_GPBS (0x00000006) +#define NV_DPCD_MAX_LINK_BANDWIDTH_VAL_2_70_GPBS (0x0000000a) +#define NV_DPCD_MAX_LINK_BANDWIDTH_VAL_5_40_GPBS (0x00000014) +#define NV_DPCD_MAX_LANE_COUNT (0x00000002) +#define NV_DPCD_MAX_LANE_COUNT_MASK (0x1f) +#define NV_DPCD_MAX_LANE_COUNT_LANE_1 (0x00000001) +#define NV_DPCD_MAX_LANE_COUNT_LANE_2 (0x00000002) +#define NV_DPCD_MAX_LANE_COUNT_LANE_4 (0x00000004) +#define NV_DPCD_MAX_LANE_COUNT_ENHANCED_FRAMING_NO (0x00000000 << 7) +#define NV_DPCD_MAX_LANE_COUNT_ENHANCED_FRAMING_YES (0x00000001 << 7) +#define NV_DPCD_MAX_DOWNSPREAD (0x00000003) +#define NV_DPCD_MAX_DOWNSPREAD_VAL_NONE (0x00000000) +#define NV_DPCD_MAX_DOWNSPREAD_VAL_0_5_PCT (0x00000001) +#define NV_DPCD_MAX_DOWNSPREAD_NO_AUX_HANDSHAKE_LT_F (0x00000000 << 6) +#define NV_DPCD_MAX_DOWNSPREAD_NO_AUX_HANDSHAKE_LT_T (0x00000001 << 6) +#define NV_DPCD_EDP_CONFIG_CAP (0x0000000D) +#define NV_DPCD_EDP_CONFIG_CAP_ASC_RESET_NO (0x00000000) +#define NV_DPCD_EDP_CONFIG_CAP_ASC_RESET_YES (0x00000001) +#define NV_DPCD_EDP_CONFIG_CAP_FRAMING_CHANGE_NO (0x00000000 << 1) +#define NV_DPCD_EDP_CONFIG_CAP_FRAMING_CHANGE_YES (0x00000001 << 1) +#define NV_DPCD_LINK_BANDWIDTH_SET (0x00000100) +#define NV_DPCD_LANE_COUNT_SET (0x00000101) +#define NV_DPCD_LANE_COUNT_SET_ENHANCEDFRAMING_F (0x00000000 << 7) +#define NV_DPCD_LANE_COUNT_SET_ENHANCEDFRAMING_T (0x00000001 << 7) +#define NV_DPCD_TRAINING_PATTERN_SET (0x00000102) +#define NV_DPCD_TRAINING_PATTERN_SET_TPS_MASK 0x3 +#define NV_DPCD_TRAINING_PATTERN_SET_TPS_NONE (0x00000000) +#define NV_DPCD_TRAINING_PATTERN_SET_TPS_TP1 (0x00000001) +#define NV_DPCD_TRAINING_PATTERN_SET_TPS_TP2 (0x00000002) +#define NV_DPCD_TRAINING_PATTERN_SET_TPS_TP3 (0x00000003) +#define NV_DPCD_TRAINING_PATTERN_SET_SC_DISABLED_F (0x00000000 << 5) +#define NV_DPCD_TRAINING_PATTERN_SET_SC_DISABLED_T (0x00000001 << 5) +#define NV_DPCD_TRAINING_LANE0_SET (0x00000103) +#define NV_DPCD_TRAINING_LANE1_SET (0x00000104) +#define NV_DPCD_TRAINING_LANE2_SET (0x00000105) +#define NV_DPCD_TRAINING_LANE3_SET (0x00000106) +#define NV_DPCD_TRAINING_LANEX_SET_DC_SHIFT 0 +#define NV_DPCD_TRAINING_LANEX_SET_DC_MAX_REACHED_T (0x00000001 << 2) +#define NV_DPCD_TRAINING_LANEX_SET_PE_SHIFT 3 +#define NV_DPCD_TRAINING_LANEX_SET_PE_MAX_REACHED_T (0x00000001 << 5) +#define NV_DPCD_DOWNSPREAD_CTRL (0x00000107) +#define NV_DPCD_DOWNSPREAD_CTRL_SPREAD_AMP_NONE (0x00000000 << 4) +#define NV_DPCD_DOWNSPREAD_CTRL_SPREAD_AMP_LT_0_5 (0x00000001 << 4) +#define NV_DPCD_MAIN_LINK_CHANNEL_CODING_SET (0x00000108) +#define NV_DPCD_MAIN_LINK_CHANNEL_CODING_SET_ANSI_8B10B 1 +#define NV_DPCD_EDP_CONFIG_SET (0x0000010A) +#define NV_DPCD_EDP_CONFIG_SET_ASC_RESET_DISABLE (0x00000000) +#define NV_DPCD_EDP_CONFIG_SET_ASC_RESET_ENABLE (0x00000001) +#define NV_DPCD_EDP_CONFIG_SET_FRAMING_CHANGE_DISABLE (0x00000000 << 1) +#define NV_DPCD_EDP_CONFIG_SET_FRAMING_CHANGE_ENABLE (0x00000001 << 1) +#define NV_DPCD_TRAINING_LANE0_1_SET2 (0x0000010F) +#define NV_DPCD_TRAINING_LANE2_3_SET2 (0x00000110) +#define NV_DPCD_LANEX_SET2_PC2_SHIFT 0 +#define NV_DPCD_LANEX_SET2_PC2_MAX_REACHED_T (0x00000001 << 2) +#define NV_DPCD_LANEXPLUS1_SET2_PC2_SHIFT 4 +#define NV_DPCD_LANEXPLUS1_SET2_PC2_MAX_REACHED_T (0x00000001 << 6) +#define NV_DPCD_SINK_COUNT (0x00000200) +#define NV_DPCD_DEVICE_SERVICE_IRQ_VECTOR (0x00000201) +#define NV_DPCD_DEVICE_SERVICE_IRQ_VECTOR_AUTO_TEST_NO (0x00000000 << 1) +#define NV_DPCD_DEVICE_SERVICE_IRQ_VECTOR_AUTO_TEST_YES (0x00000001 << 1) +#define NV_DPCD_DEVICE_SERVICE_IRQ_VECTOR_CP_NO (0x00000000 << 2) +#define NV_DPCD_DEVICE_SERVICE_IRQ_VECTOR_CP_YES (0x00000001 << 2) +#define NV_DPCD_LANE0_1_STATUS (0x00000202) +#define NV_DPCD_LANE2_3_STATUS (0x00000203) +#define NV_DPCD_STATUS_LANEX_CR_DONE_SHIFT 0 +#define NV_DPCD_STATUS_LANEX_CR_DONE_NO (0x00000000) +#define NV_DPCD_STATUS_LANEX_CR_DONE_YES (0x00000001) +#define NV_DPCD_STATUS_LANEX_CHN_EQ_DONE_SHIFT 1 +#define NV_DPCD_STATUS_LANEX_CHN_EQ_DONE_NO (0x00000000 << 1) +#define NV_DPCD_STATUS_LANEX_CHN_EQ_DONE_YES (0x00000001 << 1) +#define NV_DPCD_STATUS_LANEX_SYMBOL_LOCKED_SHFIT 2 +#define NV_DPCD_STATUS_LANEX_SYMBOL_LOCKED_NO (0x00000000 << 2) +#define NV_DPCD_STATUS_LANEX_SYMBOL_LOCKED_YES (0x00000001 << 2) +#define NV_DPCD_STATUS_LANEXPLUS1_CR_DONE_SHIFT 4 +#define NV_DPCD_STATUS_LANEXPLUS1_CR_DONE_NO (0x00000000 << 4) +#define NV_DPCD_STATUS_LANEXPLUS1_CR_DONE_YES (0x00000001 << 4) +#define NV_DPCD_STATUS_LANEXPLUS1_CHN_EQ_DONE_SHIFT 5 +#define NV_DPCD_STATUS_LANEXPLUS1_CHN_EQ_DONE_NO (0x00000000 << 5) +#define NV_DPCD_STATUS_LANEXPLUS1_CHN_EQ_DONE_YES (0x00000001 << 5) +#define NV_DPCD_STATUS_LANEXPLUS1_SYMBOL_LOCKED_SHIFT 6 +#define NV_DPCD_STATUS_LANEXPLUS1_SYMBOL_LOCKED_NO (0x00000000 << 6) +#define NV_DPCD_STATUS_LANEXPLUS1_SYMBOL_LOCKED_YES (0x00000001 << 6) +#define NV_DPCD_LANE_ALIGN_STATUS_UPDATED (0x00000204) +#define NV_DPCD_LANE_ALIGN_STATUS_UPDATED_DONE_NO (0x00000000) +#define NV_DPCD_LANE_ALIGN_STATUS_UPDATED_DONE_YES (0x00000001) +#define NV_DPCD_LANE0_1_ADJUST_REQ (0x00000206) +#define NV_DPCD_LANE2_3_ADJUST_REQ (0x00000207) +#define NV_DPCD_ADJUST_REQ_LANEX_DC_SHIFT 0 +#define NV_DPCD_ADJUST_REQ_LANEX_DC_MASK 0x3 +#define NV_DPCD_ADJUST_REQ_LANEX_PE_SHIFT 2 +#define NV_DPCD_ADJUST_REQ_LANEX_PE_MASK (0x3 << 2) +#define NV_DPCD_ADJUST_REQ_LANEXPLUS1_DC_SHIFT 4 +#define NV_DPCD_ADJUST_REQ_LANEXPLUS1_DC_MASK (0x3 << 4) +#define NV_DPCD_ADJUST_REQ_LANEXPLUS1_PE_SHIFT 6 +#define NV_DPCD_ADJUST_REQ_LANEXPLUS1_PE_MASK (0x3 << 6) +#define NV_DPCD_ADJUST_REQ_POST_CURSOR2 (0x0000020C) +#define NV_DPCD_ADJUST_REQ_POST_CURSOR2_LANE_MASK 0x3 +#define NV_DPCD_ADJUST_REQ_POST_CURSOR2_LANE_SHIFT(i) (i*2) +#define NV_DPCD_TEST_REQUEST (0x00000218) +#define NV_DPCD_SOURCE_IEEE_OUI (0x00000300) +#define NV_DPCD_SINK_IEEE_OUI (0x00000400) +#define NV_DPCD_BRANCH_IEEE_OUI (0x00000500) +#define NV_DPCD_SET_POWER (0x00000600) +#define NV_DPCD_SET_POWER_VAL_RESERVED (0x00000000) +#define NV_DPCD_SET_POWER_VAL_D0_NORMAL (0x00000001) +#define NV_DPCD_SET_POWER_VAL_D3_PWRDWN (0x00000002) +#define NV_DPCD_HDCP_BKSV_OFFSET (0x00068000) +#define NV_DPCD_HDCP_RPRIME_OFFSET (0x00068005) +#define NV_DPCD_HDCP_AKSV_OFFSET (0x00068007) +#define NV_DPCD_HDCP_AN_OFFSET (0x0006800C) +#define NV_DPCD_HDCP_VPRIME_OFFSET (0x00068014) +#define NV_DPCD_HDCP_BCAPS_OFFSET (0x00068028) +#define NV_DPCD_HDCP_BSTATUS_OFFSET (0x00068029) +#define NV_DPCD_HDCP_BINFO_OFFSET (0x0006802A) +#define NV_DPCD_HDCP_KSV_FIFO_OFFSET (0x0006802C) +#define NV_DPCD_HDCP_AINFO_OFFSET (0x0006803B) + +int tegra_dc_dpaux_read(struct tegra_dc_dp_data *dp, u32 cmd, u32 addr, + u8 *data, u32 *size, u32 *aux_stat); +int dpaux_write(u32 addr, u32 size, u32 data); +int dpaux_read(u32 addr, u32 size, u8 *data); +void debug_dpaux_print(u32 addr, u32 size); +void dp_link_training(u32 lanes, u32 speed); +#endif /* __SOC_NVIDIA_TEGRA_DISPLAYPORT_H__ */ diff --git a/src/soc/nvidia/tegra/dp.c b/src/soc/nvidia/tegra/dp.c new file mode 100644 index 0000000..28e30c8 --- /dev/null +++ b/src/soc/nvidia/tegra/dp.c @@ -0,0 +1,586 @@ +/* + * drivers/video/tegra/dc/dp.c + * + * Copyright (c) 2011-2013, NVIDIA Corporation. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include <arch/io.h> +#include <console/console.h> +#include <device/device.h> +#include <device/i2c.h> +#include <stdlib.h> +#include <string.h> +#include <delay.h> +#include <soc/addressmap.h> +#include "i2c.h" +#include "dc.h" +/* shit. This is broken. */ +#include <soc/nvidia/tegra124/sor.h> +// this is really broken. #include <soc/ardpaux.h> +#include <soc/nvidia/tegra/displayport.h> + + +extern int dump; +unsigned long READL(void* p); +void WRITEL(unsigned long value, void* p); + +static inline u32 tegra_dpaux_readl(struct tegra_dc_dp_data *dp, u32 reg) +{ + void *addr = dp->aux_base + (u32)(reg <<2); + u32 reg_val = READL(addr); + return reg_val; +} + +static inline void tegra_dpaux_writel(struct tegra_dc_dp_data *dp, + u32 reg, u32 val) +{ + void *addr = dp->aux_base + (u32)(reg <<2); + WRITEL(val, addr); +} + + +static inline u32 tegra_dc_dpaux_poll_register(struct tegra_dc_dp_data *dp, + u32 reg, u32 mask, u32 exp_val, u32 poll_interval_us, u32 timeout_ms) +{ +// unsigned long timeout_jf = jiffies + msecs_to_jiffies(timeout_ms); + u32 reg_val = 0; + + printk(BIOS_SPEW, "JZ: %s: enter, poll_reg: %#x: timeout: 0x%x\n", + __func__, reg*4, timeout_ms); + do { +// udelay(poll_interval_us); + udelay(1); + reg_val = tegra_dpaux_readl(dp, reg); + } while (((reg_val & mask) != exp_val) && (--timeout_ms > 0)); + + if ((reg_val & mask) == exp_val) + return 0; /* success */ + printk(BIOS_SPEW,"dpaux_poll_register 0x%x: timeout: (reg_val)0x%08x & (mask)0x%08x != (exp_val)0x%08x\n", reg, reg_val, mask, exp_val); + return timeout_ms; +} + + +static inline int tegra_dpaux_wait_transaction(struct tegra_dc_dp_data *dp) +{ + /* According to DP spec, each aux transaction needs to finish + within 40ms. */ + if (tegra_dc_dpaux_poll_register(dp, DPAUX_DP_AUXCTL, + DPAUX_DP_AUXCTL_TRANSACTREQ_MASK, + DPAUX_DP_AUXCTL_TRANSACTREQ_DONE, + 100, DP_AUX_TIMEOUT_MS*1000) != 0) { + printk(BIOS_SPEW,"dp: DPAUX transaction timeout\n"); + return -1; + } + return 0; +} + +static int tegra_dc_dpaux_write_chunk(struct tegra_dc_dp_data *dp, u32 cmd, + u32 addr, u8 *data, u32 *size, u32 *aux_stat) +{ + int i; + u32 reg_val; + u32 timeout_retries = DP_AUX_TIMEOUT_MAX_TRIES; + u32 defer_retries = DP_AUX_DEFER_MAX_TRIES; + u32 temp_data; + + if (*size > DP_AUX_MAX_BYTES) + return -1; /* only write one chunk of data */ + + /* Make sure the command is write command */ + switch (cmd) { + case DPAUX_DP_AUXCTL_CMD_I2CWR: + case DPAUX_DP_AUXCTL_CMD_MOTWR: + case DPAUX_DP_AUXCTL_CMD_AUXWR: + break; + default: + printk(BIOS_SPEW,"dp: aux write cmd 0x%x is invalid\n", + cmd); + return -1; + } + +#if 0 +/* interesting. */ + if (tegra_platform_is_silicon()) { + *aux_stat = tegra_dpaux_readl(dp, DPAUX_DP_AUXSTAT); + if (!(*aux_stat & DPAUX_DP_AUXSTAT_HPD_STATUS_PLUGGED)) { + printk(BIOS_SPEW,"dp: HPD is not detected\n"); + return -EFAULT; + } + } +#endif + + tegra_dpaux_writel(dp, DPAUX_DP_AUXADDR, addr); + for (i = 0; i < DP_AUX_MAX_BYTES/4; ++i) { + memcpy(&temp_data, data, 4); + tegra_dpaux_writel(dp, DPAUX_DP_AUXDATA_WRITE_W(i), + temp_data); + data += 4; + } + + reg_val = tegra_dpaux_readl(dp, DPAUX_DP_AUXCTL); + reg_val &= ~DPAUX_DP_AUXCTL_CMD_MASK; + reg_val |= cmd; + reg_val &= ~DPAUX_DP_AUXCTL_CMDLEN_FIELD; + reg_val |= ((*size-1) << DPAUX_DP_AUXCTL_CMDLEN_SHIFT); + + while ((timeout_retries > 0) && (defer_retries > 0)) { + if ((timeout_retries != DP_AUX_TIMEOUT_MAX_TRIES) || + (defer_retries != DP_AUX_DEFER_MAX_TRIES)) + udelay(1); + + reg_val |= DPAUX_DP_AUXCTL_TRANSACTREQ_PENDING; + tegra_dpaux_writel(dp, DPAUX_DP_AUXCTL, reg_val); + + if (tegra_dpaux_wait_transaction(dp)) + printk(BIOS_SPEW,"dp: aux write transaction timeout\n"); + + *aux_stat = tegra_dpaux_readl(dp, DPAUX_DP_AUXSTAT); + + if ((*aux_stat & DPAUX_DP_AUXSTAT_TIMEOUT_ERROR_PENDING) || + (*aux_stat & DPAUX_DP_AUXSTAT_RX_ERROR_PENDING) || + (*aux_stat & DPAUX_DP_AUXSTAT_SINKSTAT_ERROR_PENDING) || + (*aux_stat & DPAUX_DP_AUXSTAT_NO_STOP_ERROR_PENDING)) { + if (timeout_retries-- > 0) { + printk(BIOS_SPEW,"dp: aux write retry (0x%x) -- %d\n", + *aux_stat, timeout_retries); + /* clear the error bits */ + tegra_dpaux_writel(dp, DPAUX_DP_AUXSTAT, + *aux_stat); + continue; + } else { + printk(BIOS_SPEW,"dp: aux write got error (0x%x)\n", + *aux_stat); + return -1; + } + } + + if ((*aux_stat & DPAUX_DP_AUXSTAT_REPLYTYPE_I2CDEFER) || + (*aux_stat & DPAUX_DP_AUXSTAT_REPLYTYPE_DEFER)) { + if (defer_retries-- > 0) { + printk(BIOS_SPEW, "dp: aux write defer (0x%x) -- %d\n", + *aux_stat, defer_retries); + /* clear the error bits */ + tegra_dpaux_writel(dp, DPAUX_DP_AUXSTAT, + *aux_stat); + continue; + } else { + printk(BIOS_SPEW, "dp: aux write defer exceeds max retries " + "(0x%x)\n", + *aux_stat); + return -1; + } + } + + if ((*aux_stat & DPAUX_DP_AUXSTAT_REPLYTYPE_MASK) == + DPAUX_DP_AUXSTAT_REPLYTYPE_ACK) { + *size = ((*aux_stat) & DPAUX_DP_AUXSTAT_REPLY_M_MASK); + return 0; + } else { + printk(BIOS_SPEW,"dp: aux write failed (0x%x)\n", *aux_stat); + return -1; + } + } + /* Should never come to here */ + return -1; +} + +static int tegra_dc_dpaux_write(struct tegra_dc_dp_data *dp, u32 cmd, u32 addr, + u8 *data, u32 *size, u32 *aux_stat) +{ + u32 cur_size = 0; + u32 finished = 0; + u32 cur_left; + int ret = 0; + + do { + cur_size = *size - finished; + if (cur_size > DP_AUX_MAX_BYTES) + cur_size = DP_AUX_MAX_BYTES; + cur_left = cur_size; + ret = tegra_dc_dpaux_write_chunk(dp, cmd, addr, + data, &cur_left, aux_stat); + + cur_size -= cur_left; + finished += cur_size; + addr += cur_size; + data += cur_size; + + if (ret) + break; + } while (*size > finished); + + *size = finished; + return ret; +} + +static int tegra_dc_dpaux_read_chunk(struct tegra_dc_dp_data *dp, u32 cmd, + u32 addr, u8 *data, u32 *size, u32 *aux_stat) +{ + u32 reg_val; + u32 timeout_retries = DP_AUX_TIMEOUT_MAX_TRIES; + u32 defer_retries = DP_AUX_DEFER_MAX_TRIES; + + if (*size > DP_AUX_MAX_BYTES) + return -1; /* only read one chunk */ + + /* Check to make sure the command is read command */ + switch (cmd) { + case DPAUX_DP_AUXCTL_CMD_I2CRD: + case DPAUX_DP_AUXCTL_CMD_I2CREQWSTAT: + case DPAUX_DP_AUXCTL_CMD_MOTRD: + case DPAUX_DP_AUXCTL_CMD_AUXRD: + break; + default: + printk(BIOS_SPEW,"dp: aux read cmd 0x%x is invalid\n", cmd); + return -1; + } + + if (0){ + *aux_stat = tegra_dpaux_readl(dp, DPAUX_DP_AUXSTAT); + if (!(*aux_stat & DPAUX_DP_AUXSTAT_HPD_STATUS_PLUGGED)) { + printk(BIOS_SPEW,"dp: HPD is not detected\n"); + //return EFAULT; + } + } + + tegra_dpaux_writel(dp, DPAUX_DP_AUXADDR, addr); + + reg_val = tegra_dpaux_readl(dp, DPAUX_DP_AUXCTL); + reg_val &= ~DPAUX_DP_AUXCTL_CMD_MASK; + reg_val |= cmd; + printk(BIOS_SPEW, "cmd = %08x\n", reg_val); + reg_val &= ~DPAUX_DP_AUXCTL_CMDLEN_FIELD; + reg_val |= ((*size-1) << DPAUX_DP_AUXCTL_CMDLEN_SHIFT); + printk(BIOS_SPEW, "cmd = %08x\n", reg_val); + while ((timeout_retries > 0) && (defer_retries > 0)) { + if ((timeout_retries != DP_AUX_TIMEOUT_MAX_TRIES) || + (defer_retries != DP_AUX_DEFER_MAX_TRIES)) + udelay(DP_DPCP_RETRY_SLEEP_NS * 2); + + reg_val |= DPAUX_DP_AUXCTL_TRANSACTREQ_PENDING; + printk(BIOS_SPEW, "cmd = %08x\n", reg_val); + tegra_dpaux_writel(dp, DPAUX_DP_AUXCTL, reg_val); + + if (tegra_dpaux_wait_transaction(dp)) + printk(BIOS_SPEW,"dp: aux read transaction timeout\n"); + + *aux_stat = tegra_dpaux_readl(dp, DPAUX_DP_AUXSTAT); + printk(BIOS_SPEW, "dp: %s: aux stat: 0x%08x\n", __func__, *aux_stat); + + if ((*aux_stat & DPAUX_DP_AUXSTAT_TIMEOUT_ERROR_PENDING) || + (*aux_stat & DPAUX_DP_AUXSTAT_RX_ERROR_PENDING) || + (*aux_stat & DPAUX_DP_AUXSTAT_SINKSTAT_ERROR_PENDING) || + (*aux_stat & DPAUX_DP_AUXSTAT_NO_STOP_ERROR_PENDING)) { + if (timeout_retries-- > 0) { + printk(BIOS_SPEW, "dp: aux read retry (0x%x) -- %d\n", + *aux_stat, timeout_retries); + /* clear the error bits */ + tegra_dpaux_writel(dp, DPAUX_DP_AUXSTAT, + *aux_stat); + continue; /* retry */ + } else { + printk(BIOS_SPEW,"dp: aux read got error (0x%x)\n", + *aux_stat); + return -1; + } + } + + if ((*aux_stat & DPAUX_DP_AUXSTAT_REPLYTYPE_I2CDEFER) || + (*aux_stat & DPAUX_DP_AUXSTAT_REPLYTYPE_DEFER)) { + if (defer_retries-- > 0) { + printk(BIOS_SPEW, "dp: aux read defer (0x%x) -- %d\n", + *aux_stat, defer_retries); + /* clear the error bits */ + tegra_dpaux_writel(dp, DPAUX_DP_AUXSTAT, + *aux_stat); + continue; + } else { + printk(BIOS_SPEW,"dp: aux read defer exceeds max retries " + "(0x%x)\n", *aux_stat); + return -1; + } + } + + if ((*aux_stat & DPAUX_DP_AUXSTAT_REPLYTYPE_MASK) == + DPAUX_DP_AUXSTAT_REPLYTYPE_ACK) { + int i; + u32 temp_data[4]; + + for (i = 0; i < DP_AUX_MAX_BYTES/4; ++i) + temp_data[i] = tegra_dpaux_readl(dp, + DPAUX_DP_AUXDATA_READ_W(i)); + + *size = ((*aux_stat) & DPAUX_DP_AUXSTAT_REPLY_M_MASK); + printk(BIOS_SPEW, "dp: aux read data %d bytes\n", *size); + memcpy(data, temp_data, *size); + + return 0; + } else { + printk(BIOS_SPEW,"dp: aux read failed (0x%x\n", *aux_stat); + return -1; + } + } + /* Should never come to here */ + printk(BIOS_SPEW, "%s: can't\n", __func__); + return -1; +} + +int tegra_dc_dpaux_read(struct tegra_dc_dp_data *dp, u32 cmd, u32 addr, + u8 *data, u32 *size, u32 *aux_stat) +{ + u32 finished = 0; + u32 cur_size; + int ret = 0; + + do { + cur_size = *size - finished; + if (cur_size > DP_AUX_MAX_BYTES) + cur_size = DP_AUX_MAX_BYTES; + + ret = tegra_dc_dpaux_read_chunk(dp, cmd, addr, + data, &cur_size, aux_stat); + + /* cur_size should be the real size returned */ + addr += cur_size; + data += cur_size; + finished += cur_size; + + if (ret) + break; + +#if 0 + if (cur_size == 0) { + printk(BIOS_SPEW,"JZ: no data found, ret\n"); + break; + } +#endif + } while (*size > finished); + + *size = finished; + return ret; +} + +static int tegra_dc_dp_dpcd_read(struct tegra_dc_dp_data *dp, u32 cmd, + u8 *data_ptr) +{ + u32 size = 1; + u32 status = 0; + int ret; + + ret = tegra_dc_dpaux_read_chunk(dp, DPAUX_DP_AUXCTL_CMD_AUXRD, + cmd, data_ptr, &size, &status); + if (ret) + printk(BIOS_SPEW,"dp: Failed to read DPCD data. CMD 0x%x, Status 0x%x\n", + cmd, status); + + return ret; +} + +static int tegra_dc_dp_init_max_link_cfg(struct tegra_dc_dp_data *dp, + struct tegra_dc_dp_link_config *cfg) +{ + u8 dpcd_data; + int ret; + + ret = tegra_dc_dp_dpcd_read(dp, NV_DPCD_MAX_LANE_COUNT, + &dpcd_data); + if (ret) + return ret; + + cfg->max_lane_count = dpcd_data & NV_DPCD_MAX_LANE_COUNT_MASK; + printk(BIOS_SPEW, "JZ: %s: max_lane_count: %d\n", __func__, cfg->max_lane_count); + + cfg->support_enhanced_framing = + (dpcd_data & NV_DPCD_MAX_LANE_COUNT_ENHANCED_FRAMING_YES) ? + 1 : 0; + printk(BIOS_SPEW, "JZ: %s: enh-framing: %d\n", __func__, cfg->support_enhanced_framing); + + ret = tegra_dc_dp_dpcd_read(dp, NV_DPCD_MAX_DOWNSPREAD, + &dpcd_data); + if (ret) + return ret; + cfg->downspread = (dpcd_data & NV_DPCD_MAX_DOWNSPREAD_VAL_0_5_PCT) ? + 1 : 0; + printk(BIOS_SPEW, "JZ: %s: downspread: %d\n", __func__, cfg->downspread); + + ret = tegra_dc_dp_dpcd_read(dp, NV_DPCD_MAX_LINK_BANDWIDTH, + &cfg->max_link_bw); + if (ret) + return ret; + printk(BIOS_SPEW, "JZ: %s: max_link_bw: %d\n", __func__, cfg->max_link_bw); + + // jz, changed + // cfg->bits_per_pixel = dp->dc->pdata->default_out->depth; + cfg->bits_per_pixel = 24; + + /* TODO: need to come from the board file */ + /* Venice2 settings */ + cfg->drive_current = 0x20202020; + cfg->preemphasis = 0; + cfg->postcursor = 0; + + ret = tegra_dc_dp_dpcd_read(dp, NV_DPCD_EDP_CONFIG_CAP, + &dpcd_data); + if (ret) + return ret; + cfg->alt_scramber_reset_cap = + (dpcd_data & NV_DPCD_EDP_CONFIG_CAP_ASC_RESET_YES) ? + 1 : 0; + cfg->only_enhanced_framing = + (dpcd_data & NV_DPCD_EDP_CONFIG_CAP_FRAMING_CHANGE_YES) ? + 1 : 0; + printk(BIOS_SPEW, "JZ: %s: alt_reset_cap: %d, only_enh_framing: %d\n", __func__, + cfg->alt_scramber_reset_cap, cfg->only_enhanced_framing); + + cfg->lane_count = cfg->max_lane_count; + cfg->link_bw = cfg->max_link_bw; + cfg->enhanced_framing = cfg->support_enhanced_framing; + return 0; +} + + +//struct tegra_dc dc_data = {0}; +struct tegra_dc_sor_data sor_data = {0}; +struct tegra_dc_dp_data dp_data = {0}; + +static int tegra_dc_dpcd_read_rev(struct tegra_dc_dp_data *dp, + u8 *rev) +{ + u32 size; + int ret; + u32 status = 0; + + size = 3; + ret = tegra_dc_dpaux_read(dp, DPAUX_DP_AUXCTL_CMD_AUXRD, + NV_DPCD_REV, rev, &size, &status); + if (ret) { + printk(BIOS_SPEW,"dp: Failed to read NV_DPCD_REV\n"); + return ret; + } + return 0; +} +u32 dp_setup_timing(u32 panel_id, u32 width, u32 height); +void dp_bringup(u32 winb_addr) +{ + struct tegra_dc_dp_data *dp = &dp_data; + + u32 dpcd_rev; + u32 pclk_freq; +// int ret; + + printk(BIOS_SPEW, "JZ: %s: entry\n",__func__); + + dp->sor = &sor_data; +// dp->sor->dc = dc; + dp->sor->base = (void *)TEGRA_ARM_SOR; +// dp->sor->base_res = base_res; +// dp->sor->sor_clk = clk; + dp->sor->link_cfg = &dp->link_cfg; + dp->sor->portnum = 0; + + dp->aux_base = (void *)TEGRA_ARM_DPAUX; +/* dp->mode = 0; */ /* ???? */ + + /* read panel info */ + if (!tegra_dc_dpcd_read_rev(dp, (u8 *)&dpcd_rev)) { + printk(BIOS_SPEW,"PANEL info: \n"); + printk(BIOS_SPEW,"--DPCP version(%#x): %d.%d\n", + dpcd_rev, (dpcd_rev >> 4)&0x0f, (dpcd_rev & 0x0f)); + } + + if (tegra_dc_dp_init_max_link_cfg(dp, &dp->link_cfg)) + printk(BIOS_SPEW,"dp: failed to init link configuration\n"); + + dp_link_training((u32)(dp->link_cfg.lane_count), + (u32)(dp->link_cfg.link_bw)); + + pclk_freq = dp_setup_timing(5, 2560, 1700); // W: 2560, H: 1700, use_plld2: 1 + printk(BIOS_SPEW, "JZ: %s: pclk_freq: %d\n",__func__, pclk_freq); + +// void dp_misc_setting(u32 panel_bpp, u32 width, u32 height, u32 winb_addr) +void dp_misc_setting(u32 panel_bpp, u32 width, u32 height, u32 winb_addr, + u32 lane_count, u32 enhanced_framing, u32 panel_edp, + u32 pclkfreq, u32 linkfreq); + + dp_misc_setting(dp->link_cfg.bits_per_pixel, + 2560, 1700, winb_addr, + (u32)dp->link_cfg.lane_count, + (u32)dp->link_cfg.enhanced_framing, + (u32)dp->link_cfg.alt_scramber_reset_cap, + pclk_freq, + dp->link_cfg.link_bw * 27); + + +} + +void debug_dpaux_print(u32 addr, u32 size) +{ + struct tegra_dc_dp_data *dp = &dp_data; + u32 status = 0; + u8 buf[16]; + int i; + + if ((size == 0) || (size > 16)) { + printk(BIOS_SPEW,"dp: %s: invalid size %d\n", __func__, size); + return; + } + + if (tegra_dc_dpaux_read(dp, DPAUX_DP_AUXCTL_CMD_AUXRD, + addr, buf, &size, &status)) { + printk(BIOS_SPEW,"******AuxRead Error: 0x%04x: status 0x%08x\n", addr, status); + return; + } + printk(BIOS_SPEW, "%s: addr: 0x%04x, size: %d\n", __func__, addr, size); + for (i=0; i < size; ++i) + printk(BIOS_SPEW," %02x", buf[i]); + + printk(BIOS_SPEW,"\n"); +} + +int dpaux_read(u32 addr, u32 size, u8 *data) +{ + + struct tegra_dc_dp_data *dp = &dp_data; + u32 status = 0; + + if ((size == 0) || (size > 16)) { + printk(BIOS_SPEW,"dp: %s: invalid size %d\n", __func__, size); + return -1; + } + + if (tegra_dc_dpaux_read(dp, DPAUX_DP_AUXCTL_CMD_AUXRD, + addr, data, &size, &status)) { + printk(BIOS_SPEW,"dp: Failed to read reg %#x, status: %#x\n", addr, status); + return -1; + } + + return 0; +} + +int dpaux_write(u32 addr, u32 size, u32 data) +{ + struct tegra_dc_dp_data *dp = &dp_data; + u32 status = 0; + int ret; + + printk(BIOS_SPEW, "JZ: %s: entry, addr: 0x%08x, size: 0x%08x, data: %#x\n", + __func__, addr, size, data); + + ret = tegra_dc_dpaux_write(dp, DPAUX_DP_AUXCTL_CMD_AUXWR, + addr, (u8 *)&data, &size, &status); + if (ret) + printk(BIOS_SPEW,"dp: Failed to write to reg %#x, status: 0x%x\n", + addr, status); + return ret; +} + diff --git a/src/soc/nvidia/tegra/gpio.c b/src/soc/nvidia/tegra/gpio.c index 0615320..4cf6d5f 100644 --- a/src/soc/nvidia/tegra/gpio.c +++ b/src/soc/nvidia/tegra/gpio.c @@ -36,15 +36,13 @@ void __gpio_input(gpio_t gpio, u32 pull) pinmux_set_config(gpio >> GPIO_PINMUX_SHIFT, pinmux_config); } -void gpio_output(gpio_t gpio, int value) +void __gpio_output(gpio_t gpio, int value, u32 od) { - /* TODO: Set OPEN_DRAIN based on what pin it is? */ - gpio_set_int_enable(gpio, 0); gpio_set_out_value(gpio, value); gpio_set_out_enable(gpio, 1); gpio_set_mode(gpio, GPIO_MODE_GPIO); - pinmux_set_config(gpio >> GPIO_PINMUX_SHIFT, PINMUX_PULL_NONE); + pinmux_set_config(gpio >> GPIO_PINMUX_SHIFT, PINMUX_PULL_NONE | od); } enum { diff --git a/src/soc/nvidia/tegra/gpio.h b/src/soc/nvidia/tegra/gpio.h index 546ea05..70c1026 100644 --- a/src/soc/nvidia/tegra/gpio.h +++ b/src/soc/nvidia/tegra/gpio.h @@ -31,10 +31,20 @@ typedef u32 gpio_t; #define GPIO(name) ((gpio_t)(GPIO_##name##_INDEX | \ (PINMUX_GPIO_##name << GPIO_PINMUX_SHIFT))) +void __gpio_output(gpio_t gpio, int value, u32 open_drain); +void __gpio_input(gpio_t gpio, u32 pull); + /* Higher level function wrappers for common GPIO configurations. */ -void gpio_output(gpio_t gpio, int value); -void __gpio_input(gpio_t gpio, u32 pull); +static inline void gpio_output(gpio_t gpio, int value) +{ + __gpio_output(gpio, value, 0); +} + +static inline void gpio_output_open_drain(gpio_t gpio, int value) +{ + __gpio_output(gpio, value, PINMUX_OPEN_DRAIN); +} static inline void gpio_input(gpio_t gpio) { diff --git a/src/soc/nvidia/tegra/usb.c b/src/soc/nvidia/tegra/usb.c new file mode 100644 index 0000000..0a3434f --- /dev/null +++ b/src/soc/nvidia/tegra/usb.c @@ -0,0 +1,120 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <delay.h> +#include <arch/io.h> +#include <console/console.h> +#include <soc/clock.h> + +#include "usb.h" + +/* Assume USBx clocked, out of reset, UTMI+ PLL set up, SAMP_x out of pwrdn */ +void usb_setup_utmip(struct usb_ctlr *usb) +{ + /* KHz formulas were guessed from U-Boot constants. Formats unclear. */ + int khz = clock_get_osc_khz(); + + /* Stop UTMI+ crystal clock while we mess with its settings */ + clrbits_le32(&usb->utmip.misc1, 1 << 30); /* PHY_XTAL_CLKEN */ + udelay(1); + + /* Take stuff out of pwrdn and add some magic numbers from U-Boot */ + write32(0x8 << 25 | /* HS slew rate [10:4] */ + 0x3 << 22 | /* HS driver output 'SETUP' [6:4] */ + 0 << 21 | /* LS bias selection */ + 0 << 18 | /* PDZI pwrdn */ + 0 << 16 | /* PD2 pwrdn */ + 0 << 14 | /* PD pwrdn */ + 1 << 13 | /* (rst) HS receiver terminations */ + 0x1 << 10 | /* (rst) LS falling slew rate */ + 0x1 << 8 | /* (rst) LS rising slew rate */ + 0x4 << 0 | /* HS driver output 'SETUP' [3:0] */ + 0, &usb->utmip.xcvr0); + write32(0x7 << 18 | /* Termination range adjustment */ + 0 << 4 | /* PDDR pwrdn */ + 0 << 2 | /* PDCHRP pwrdn */ + 0 << 0 | /* PDDISC pwrdn */ + 0, &usb->utmip.xcvr1); + write32(1 << 19 | /* FS send initial J before sync(?) */ + 1 << 16 | /* (rst) Allow stuff error on SoP */ + 1 << 9 | /* (rst) Check disc only on EoP */ + 0, &usb->utmip.tx); + write32(0x2 << 30 | /* (rst) Keep pattern on active */ + 1 << 28 | /* (rst) Realign inertia on pkt */ + 0x1 << 24 | /* (rst) edges-1 to move sampling */ + 0x3 << 21 | /* (rst) squelch delay on EoP */ + 0x11 << 15 | /* cycles until IDLE */ + 0x10 << 10 | /* elastic input depth */ + 0, &usb->utmip.hsrx0); + + /* U-Boot claims the USBD values for these are used across all UTMI+ + * PHYs. That sounds so horribly wrong that I'm not going to implement + * it, but keep it in mind if we're ever not using the USBD port. */ + write32(0x1 << 24 | /* HS disconnect detect level [2] */ + 1 << 23 | /* (rst) IDPD value */ + 1 << 22 | /* (rst) IDPD select */ + 1 << 11 | /* (rst) OTG pwrdn */ + 0 << 10 | /* bias pwrdn */ + 0x1 << 2 | /* HS disconnect detect level [1:0] */ + 0x2 << 0 | /* HS squelch detect level */ + 0, &usb->utmip.bias0); + + write32(khz / 2200 << 3 | /* bias pwrdn cycles (20us?) */ + 1 << 2 | /* (rst) VBUS wakeup pwrdn */ + 0 << 0 | /* PDTRK pwrdn */ + 0, &usb->utmip.bias1); + + write32(0xffff << 16 | /* (rst) */ + 25 * khz / 10 << 0 | /* TODO: what's this, really? */ + 0, &usb->utmip.debounce); + + udelay(1); + setbits_le32(&usb->utmip.misc1, 1 << 30); /* PHY_XTAL_CLKEN */ + + write32(1 << 12 | /* UTMI+ enable */ + 0 << 11 | /* UTMI+ reset */ + 0, &usb->suspend_ctrl); +} + +/* + * Tegra EHCI controllers need their usb_mode and lpm_ctrl registers initialized + * after every EHCI reset and before any other actions (such as Run/Stop bit) + * are taken. We reset the controller here, set those registers and rely on the + * fact that libpayload doesn't reset EHCI controllers on initialization for + * whatever weird reason. This is ugly, fragile, and I really don't like it, but + * making this work will require an ugly hack one way or another so we might as + * well take the path of least resistance for now. + */ +void usb_ehci_reset_and_prepare(struct usb_ctlr *usb, enum usb_phy_type type) +{ + int timeout = 1000; + + write32(1 << 1, &usb->ehci_usbcmd); /* Host Controller Reset */ + /* TODO: Resets are long, find way to parallelize... or just use XHCI */ + while (--timeout && (read32(&usb->ehci_usbcmd) & 1 << 1)) + /* wait for HC to reset */; + + if (!timeout) { + printk(BIOS_ERR, "ERROR: EHCI(%p) reset timeout", usb); + return; + } + + write32(3 << 0, &usb->usb_mode); /* Controller mode: HOST */ + write32(type << 29, &usb->lpm_ctrl); /* Parallel transceiver selct */ +} diff --git a/src/soc/nvidia/tegra/usb.h b/src/soc/nvidia/tegra/usb.h new file mode 100644 index 0000000..059a815 --- /dev/null +++ b/src/soc/nvidia/tegra/usb.h @@ -0,0 +1,121 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef __SOC_NVIDIA_TEGRA_USB_H__ +#define __SOC_NVIDIA_TEGRA_USB_H__ + +#include <stdint.h> + +struct utmip_ctlr { + u32 pll0; + u32 pll1; + u32 xcvr0; + u32 bias0; + u32 hsrx0; + u32 hsrx1; + u32 fslsrx0; + u32 fslsrx1; + u32 tx; + u32 misc0; + u32 misc1; + u32 debounce; + u32 batchrgr; + u32 spare; + u32 xcvr1; + u32 bias1; + u32 bias_sts; + u32 chrgr_debounce; + u32 misc_sts; + u32 pmc_wakeup; +}; + +struct usb_ctlr { + u32 id; + u32 _rsv0; + u32 host; + u32 device; + u32 txbuf; /* 0x010 */ + u32 rxbuf; + u32 _rsv1[58]; + u16 ehci_caplen; /* 0x100 */ + u16 ehci_version; + u32 ehci_hcsp; + u32 ehci_hccp; + u32 _rsv2[5]; + u32 dci_version; /* 0x120 */ + u32 dcc_params; + u32 extsts; + u32 extintr; + u32 ehci_usbcmd; /* 0x130 */ + u32 ehci_usbsts; + u32 ehci_usbintr; + u32 ehci_frindex; + u32 _rsv3; /* 0x140 */ + u32 ehci_periodic_base; + u32 ehci_async_base; + u32 async_ttsts; + u32 burst_size; /* 0x150 */ + u32 tx_fill_tuning; + u32 _rsv4; + u32 icusb_ctrl; + u32 ulpi_viewport; /* 0x160 */ + u32 _rsv5[4]; + u32 ehci_portsc; + u32 _rsv6[15]; + u32 lpm_ctrl; + u32 _rsv7[15]; + u32 otgsc; + u32 usb_mode; + u32 _rsv8; + u32 ep_nak; /* 0x200 */ + u32 ep_nak_enable; + u32 ep_setup; + u32 ep_init; + u32 ep_deinit; + u32 ep_sts; + u32 ep_complete; + u32 ep_ctrl[16]; + u32 _rsv9[105]; + u32 suspend_ctrl; /* 0x400 */ + u32 vbus_sensors; + u32 vbus_wakeup_id; + u32 alt_vbus_sts; + u32 legacy_ctrl; + u32 _rsv10[3]; + u32 interpacket_delay; + u32 _rsv11[27]; + u32 resume_delay; + u32 _rsv12; + u32 spare; + u32 _rsv13[9]; + u32 new_ctrl; + u32 _rsv14[207]; + struct utmip_ctlr utmip; /* 0x800 */ +}; + +enum usb_phy_type { /* For use in lpm_ctrl[31:29] */ + USB_PHY_UTMIP = 0, + USB_PHY_ULPI = 2, + USB_PHY_ICUSB_SER = 3, + USB_PHY_HSIC = 4, +}; + +void usb_setup_utmip(struct usb_ctlr *usb); +void usb_ehci_reset_and_prepare(struct usb_ctlr *usb, enum usb_phy_type type); +#endif diff --git a/src/soc/nvidia/tegra124/Kconfig b/src/soc/nvidia/tegra124/Kconfig index 30c9feb..38ecc0b 100644 --- a/src/soc/nvidia/tegra124/Kconfig +++ b/src/soc/nvidia/tegra124/Kconfig @@ -65,4 +65,17 @@ config STACK_SIZE hex default 0x800 +# TTB needs to be aligned to 16KB. Stick it in iRAM. +config TTB_BUFFER + hex "memory address of the TTB buffer" + default 0x40000000 + +config CBFS_CACHE_ADDRESS + hex "memory address to put CBFS cache data" + default 0x803c0000 + +config CBFS_CACHE_SIZE + hex "size of CBFS cache data" + default 0x00020000 + endif diff --git a/src/soc/nvidia/tegra124/Makefile.inc b/src/soc/nvidia/tegra124/Makefile.inc index d78553d..aa1ffcc 100644 --- a/src/soc/nvidia/tegra124/Makefile.inc +++ b/src/soc/nvidia/tegra124/Makefile.inc @@ -35,15 +35,18 @@ ramstage-y += cbfs.c ramstage-y += cbmem.c ramstage-y += cpug.S ramstage-y += clock.c -ramstage-y += display.c +ramstage-y += display.c displayhack.c ramstage-y += dma.c ramstage-y += i2c.c ramstage-y += monotonic_timer.c ramstage-y += soc.c +ramstage-y += sor.c ramstage-y += spi.c +ramstage-y += ../tegra/dp.c ramstage-y += ../tegra/gpio.c ramstage-y += ../tegra/i2c.c ramstage-y += ../tegra/pinmux.c +ramstage-y += ../tegra/usb.c ramstage-y += timer.c ramstage-$(CONFIG_CONSOLE_SERIAL) += uart.c diff --git a/src/soc/nvidia/tegra124/clk_rst.h b/src/soc/nvidia/tegra124/clk_rst.h index 4280f3c..56a3b33 100644 --- a/src/soc/nvidia/tegra124/clk_rst.h +++ b/src/soc/nvidia/tegra124/clk_rst.h @@ -192,7 +192,9 @@ struct __attribute__ ((__packed__)) clk_rst_ctlr { u32 clk_src_nand_speed; /* _CLK_SOURCE_NAND_SPEED, 0x3f8 */ u32 clk_src_i2c_slow; /* _CLK_SOURCE_I2C_SLOW, 0x3fc */ u32 clk_src_sys; /* _CLK_SOURCE_SYS, 0x400 */ - u32 _rsv26[7]; /* 0x404-41c */ + u32 _rsv26[4]; /* 0x404-410 */ + u32 clk_src_sor; /* _CLK_SOURCE_SOR_0, 0x414 */ + u32 _rsv261[2]; /* 0x404-410 */ u32 clk_src_sata_oob; /* _CLK_SOURCE_SATA_OOB, 0x420 */ u32 clk_src_sata; /* _CLK_SOURCE_SATA, 0x424 */ u32 clk_src_hda; /* _CLK_SOURCE_HDA, 0x428 */ @@ -267,7 +269,11 @@ struct __attribute__ ((__packed__)) clk_rst_ctlr { u32 _rsv31; /* 0x554 */ u32 super_gr3d_clk_div; /* _SUPER_GR3D_CLK_DIVIDER, 0x558 */ u32 spare_reg0; /* _SPARE_REG0, 0x55c */ - u32 _rsv32[40]; /* 0x560-5fc */ + u32 _rsv32[11]; /* 0x560-58c */ + u32 plldp_base; /* _PLLDP_BASE, 0x590 */ + u32 plldp_misc; /* _PLLDP_MISC, 0x594 */ + u32 plldp_ss_cfg; /* _PLLDP_SS_CFG, 0x598 */ + u32 _rsrv321[26]; u32 clk_src_xusb_core_host; /* _CLK_SOURCE_XUSB_CORE_HOST 0x600 */ u32 clk_src_xusb_falcon; /* _CLK_SOURCE_XUSB_FALCON 0x604 */ u32 clk_src_xusb_fs; /* _CLK_SOURCE_XUSB_FS 0x608 */ @@ -425,24 +431,10 @@ enum { #define OSC_XOFS_MASK (0x3F << OSC_XOFS_SHIFT) #define OSC_DRIVE_STRENGTH 7 -/* - * CLK_RST_CONTROLLER_CLK_SOURCE_x_OUT_0 - the mask here is normally 8 bits - * but can be 16. We could use knowledge we have to restrict the mask in - * the 8-bit cases (the divider_bits value returned by - * get_periph_clock_source()) but it does not seem worth it since the code - * already checks the ranges of values it is writing, in clk_get_divider(). - */ -#define CLK_DIVISOR_SHIFT 0 -#define CLK_DIVISOR_MASK (0xffff << CLK_DIVISOR_SHIFT) - -#define CLK_SOURCE_SHIFT 30 -#define CLK_SOURCE_MASK (3U << CLK_SOURCE_SHIFT) - -#define CLK_SOURCE3_SHIFT 29 -#define CLK_SOURCE3_MASK (7U << CLK_SOURCE3_SHIFT) +#define CLK_DIVISOR_MASK (0xffff) -#define CLK_SOURCE4_SHIFT 28 -#define CLK_SOURCE4_MASK (15U << CLK_SOURCE4_SHIFT) +#define CLK_SOURCE_SHIFT 29 +#define CLK_SOURCE_MASK (0x7 << CLK_SOURCE_SHIFT) #define CLK_UART_DIV_OVERRIDE (1 << 24) diff --git a/src/soc/nvidia/tegra124/clock.c b/src/soc/nvidia/tegra124/clock.c index 9dce867..5298ce8 100644 --- a/src/soc/nvidia/tegra124/clock.c +++ b/src/soc/nvidia/tegra124/clock.c @@ -18,14 +18,17 @@ #include <arch/io.h> #include <soc/addressmap.h> #include <soc/clock.h> +#include <stdlib.h> #include "clk_rst.h" #include "cpug.h" #include "flow.h" #include "pmc.h" +#include "sysctr.h" static struct clk_rst_ctlr *clk_rst = (void *)TEGRA_CLK_RST_BASE; static struct flow_ctlr *flow = (void *)TEGRA_FLOW_BASE; -static struct tegra_pmc_regs *pmc = (void*)TEGRA_PMC_BASE; +static struct tegra_pmc_regs *pmc = (void *)TEGRA_PMC_BASE; +static struct sysctr_regs *sysctr = (void *)TEGRA_SYSCTR0_BASE; struct pll_dividers { u32 n : 10; @@ -143,21 +146,6 @@ struct { }, }; -void clock_ll_set_source_divisor(u32 *reg, u32 source, u32 divisor) -{ - u32 value; - - value = readl(reg); - - value &= ~CLK_SOURCE_MASK; - value |= source << CLK_SOURCE_SHIFT; - - value &= ~CLK_DIVISOR_MASK; - value |= divisor << CLK_DIVISOR_SHIFT; - - writel(value, reg); -} - /* Get the oscillator frequency, from the corresponding hardware * configuration field. This is actually a per-soc thing. Avoid the * temptation to make it common. @@ -172,6 +160,20 @@ int clock_get_osc_khz(void) return osc_table[clock_get_osc_bits()].khz; } +void clock_init_arm_generic_timer(void) +{ + uint32_t freq = clock_get_osc_khz() * 1000; + // Set the cntfrq register. + __asm__ __volatile__("mcr p15, 0, %0, c14, c0, 0\n" :: "r"(freq)); + + // Record the system timer frequency. + write32(freq, &sysctr->cntfid0); + // Enable the system counter. + uint32_t cntcr = read32(&sysctr->cntcr); + cntcr |= SYSCTR_CNTCR_EN | SYSCTR_CNTCR_HDBG; + write32(cntcr, &sysctr->cntcr); +} + static void adjust_pllp_out_freqs(void) { u32 reg; @@ -204,6 +206,37 @@ static void init_pll(u32 *base, u32 *misc, const union pll_fields pll) writel(dividers | PLL_BASE_ENABLE, base); } +static void init_utmip_pll(void) +{ + int khz = clock_get_osc_khz(); + + /* Shut off PLL crystal clock while we mess with it */ + clrbits_le32(&clk_rst->utmip_pll_cfg2, 1 << 30); /* PHY_XTAL_CLKEN */ + udelay(1); + + write32(80 << 16 | /* (rst) phy_divn */ + 1 << 8 | /* (rst) phy_divm */ + 0, &clk_rst->utmip_pll_cfg0); /* 960MHz * 1 / 80 == 12 MHz */ + + write32(CEIL_DIV(khz, 8000) << 27 | /* pllu_enbl_cnt / 8 (1us) */ + 0 << 16 | /* PLLU pwrdn */ + 0 << 14 | /* pll_enable pwrdn */ + 0 << 12 | /* pll_active pwrdn */ + CEIL_DIV(khz, 102) << 0 | /* phy_stbl_cnt / 256 (2.5ms) */ + 0, &clk_rst->utmip_pll_cfg1); + + /* TODO: TRM can't decide if actv is 5us or 10us, keep an eye on it */ + write32(0 << 24 | /* SAMP_D/XDEV pwrdn */ + CEIL_DIV(khz, 3200) << 18 | /* phy_actv_cnt / 16 (5us) */ + CEIL_DIV(khz, 256) << 6 | /* pllu_stbl_cnt / 256 (1ms) */ + 0 << 4 | /* SAMP_C/USB3 pwrdn */ + 0 << 2 | /* SAMP_B/XHOST pwrdn */ + 0 << 0 | /* SAMP_A/USBD pwrdn */ + 0, &clk_rst->utmip_pll_cfg2); + + setbits_le32(&clk_rst->utmip_pll_cfg2, 1 << 30); /* PHY_XTAL_CLKEN */ +} + /* Initialize the UART and put it on CLK_M so we can use it during clock_init(). * Will later move it to PLLP in clock_config(). The divisor must be very small * to accomodate 12KHz OSCs, so we override the 16.0 UART divider with the 15.1 @@ -212,8 +245,8 @@ static void init_pll(u32 *base, u32 *misc, const union pll_fields pll) * been determined through trial and error (must lead to div 13 at 24MHz). */ void clock_early_uart(void) { - clock_ll_set_source_divisor(&clk_rst->clk_src_uarta, 3, - CLK_UART_DIV_OVERRIDE | CLK_DIVIDER(clock_get_osc_khz(), 1800)); + write32(CLK_M << CLK_SOURCE_SHIFT | CLK_UART_DIV_OVERRIDE | + CLK_DIVIDER(TEGRA_CLK_M_KHZ, 1800), &clk_rst->clk_src_uarta); setbits_le32(&clk_rst->clk_out_enb_l, CLK_L_UARTA); udelay(2); clrbits_le32(&clk_rst->rst_dev_l, CLK_L_UARTA); @@ -319,62 +352,26 @@ void clock_init(void) init_pll(&clk_rst->pllc_base, &clk_rst->pllc_misc, osc_table[osc].pllc); init_pll(&clk_rst->plld_base, &clk_rst->plld_misc, osc_table[osc].plld); init_pll(&clk_rst->pllu_base, &clk_rst->pllu_misc, osc_table[osc].pllu); + init_utmip_pll(); val = (1 << CLK_SYS_RATE_AHB_RATE_SHIFT); writel(val, &clk_rst->clk_sys_rate); } -void clock_config(void) +void clock_enable_clear_reset(u32 l, u32 h, u32 u, u32 v, u32 w) { - /* Enable clocks for the required peripherals. */ - /* TODO: can (should?) we use the _SET and _CLR registers here? */ - setbits_le32(&clk_rst->clk_out_enb_l, - CLK_L_CACHE2 | CLK_L_GPIO | CLK_L_TMR | CLK_L_I2C1 | - CLK_L_SDMMC4); - setbits_le32(&clk_rst->clk_out_enb_h, - CLK_H_EMC | CLK_H_I2C2 | CLK_H_I2C5 | CLK_H_SBC1 | - CLK_H_PMC | CLK_H_APBDMA | CLK_H_MEM); - setbits_le32(&clk_rst->clk_out_enb_u, - CLK_U_I2C3 | CLK_U_CSITE | CLK_U_SDMMC3); - setbits_le32(&clk_rst->clk_out_enb_v, CLK_V_MSELECT); - setbits_le32(&clk_rst->clk_out_enb_w, CLK_W_DVFS); - - /* - * Set MSELECT clock source as PLLP (00)_REG, and ask for a clock - * divider that would set the MSELECT clock at 102MHz for a - * PLLP base of 408MHz. - */ - clock_ll_set_source_divisor(&clk_rst->clk_src_mselect, 0, - CLK_DIVIDER(TEGRA_PLLP_KHZ, 102000)); - - /* Give clock time to stabilize */ - udelay(IO_STABILIZATION_DELAY); - - /* I2C1 gets CLK_M and a divisor of 17 */ - clock_ll_set_source_divisor(&clk_rst->clk_src_i2c1, 3, 16); - /* I2C2 gets CLK_M and a divisor of 17 */ - clock_ll_set_source_divisor(&clk_rst->clk_src_i2c2, 3, 16); - /* I2C3 (cam) gets CLK_M and a divisor of 17 */ - clock_ll_set_source_divisor(&clk_rst->clk_src_i2c3, 3, 16); - /* I2C5 (PMU) gets CLK_M and a divisor of 17 */ - clock_ll_set_source_divisor(&clk_rst->clk_src_i2c5, 3, 16); - - /* UARTA gets PLLP, deactivate CLK_UART_DIV_OVERRIDE */ - writel(0 << CLK_SOURCE_SHIFT, &clk_rst->clk_src_uarta); + if (l) writel(l, &clk_rst->clk_enb_l_set); + if (h) writel(h, &clk_rst->clk_enb_h_set); + if (u) writel(u, &clk_rst->clk_enb_u_set); + if (v) writel(v, &clk_rst->clk_enb_v_set); + if (w) writel(w, &clk_rst->clk_enb_w_set); - /* Give clock time to stabilize. */ + /* Give clocks time to stabilize. */ udelay(IO_STABILIZATION_DELAY); - /* Take required peripherals out of reset. */ - - clrbits_le32(&clk_rst->rst_dev_l, - CLK_L_CACHE2 | CLK_L_GPIO | CLK_L_TMR | CLK_L_I2C1 | - CLK_L_SDMMC4); - clrbits_le32(&clk_rst->rst_dev_h, - CLK_H_EMC | CLK_H_I2C2 | CLK_H_I2C5 | CLK_H_SBC1 | - CLK_H_PMC | CLK_H_APBDMA | CLK_H_MEM); - clrbits_le32(&clk_rst->rst_dev_u, - CLK_U_I2C3 | CLK_U_CSITE | CLK_U_SDMMC3); - clrbits_le32(&clk_rst->rst_dev_v, CLK_V_MSELECT); - clrbits_le32(&clk_rst->rst_dev_w, CLK_W_DVFS); + if (l) writel(l, &clk_rst->rst_dev_l_clr); + if (h) writel(h, &clk_rst->rst_dev_h_clr); + if (u) writel(u, &clk_rst->rst_dev_u_clr); + if (v) writel(v, &clk_rst->rst_dev_v_clr); + if (w) writel(w, &clk_rst->rst_dev_w_clr); } diff --git a/src/soc/nvidia/tegra124/display.c b/src/soc/nvidia/tegra124/display.c index b7d3d7f..f0203ad 100644 --- a/src/soc/nvidia/tegra124/display.c +++ b/src/soc/nvidia/tegra124/display.c @@ -30,13 +30,30 @@ #include <cpu/cpu.h> #include <boot/tables.h> #include <cbmem.h> +#include <edid.h> #include <soc/clock.h> #include <soc/nvidia/tegra/dc.h> -#include "clk_rst.h" #include "chip.h" #include <soc/display.h> -static struct clk_rst_ctlr *clk_rst = (void *)TEGRA_CLK_RST_BASE; +int dump = 0; +unsigned long READL(void * p); +void WRITEL(unsigned long value, void * p); +unsigned long READL(void * p) +{ + unsigned long value = readl(p); + if (dump) + printk(BIOS_SPEW, "readl %p %08lx\n", p, value); + return value; +} + + +void WRITEL(unsigned long value, void * p) +{ + if (dump) + printk(BIOS_SPEW, "writel %p %08lx\n", p, value); + writel(value, p); +} static const u32 rgb_enb_tab[PIN_REG_COUNT] = { 0x00000000, @@ -76,25 +93,25 @@ static int update_display_mode(struct dc_disp_reg *disp, u32 rate; u32 div; - writel(0x0, &disp->disp_timing_opt); + WRITEL(0x0, &disp->disp_timing_opt); - writel(config->vref_to_sync << 16 | config->href_to_sync, + WRITEL(config->vref_to_sync << 16 | config->href_to_sync, &disp->ref_to_sync); - writel(config->vsync_width << 16 | config->hsync_width, &disp->sync_width); - writel(config->vback_porch << 16 | config->hback_porch, &disp->back_porch); - writel(config->vfront_porch << 16 | config->hfront_porch, + WRITEL(config->vsync_width << 16 | config->hsync_width, &disp->sync_width); + WRITEL(config->vback_porch << 16 | config->hback_porch, &disp->back_porch); + WRITEL(config->vfront_porch << 16 | config->hfront_porch, &disp->front_porch); - writel(config->xres | (config->yres << 16), &disp->disp_active); + WRITEL(config->xres | (config->yres << 16), &disp->disp_active); val = DE_SELECT_ACTIVE << DE_SELECT_SHIFT; val |= DE_CONTROL_NORMAL << DE_CONTROL_SHIFT; - writel(val, &disp->data_enable_opt); + WRITEL(val, &disp->data_enable_opt); val = DATA_FORMAT_DF1P1C << DATA_FORMAT_SHIFT; val |= DATA_ALIGNMENT_MSB << DATA_ALIGNMENT_SHIFT; val |= DATA_ORDER_RED_BLUE << DATA_ORDER_SHIFT; - writel(val, &disp->disp_interface_ctrl); + WRITEL(val, &disp->disp_interface_ctrl); /* * The pixel clock divider is in 7.1 format (where the bottom bit @@ -107,11 +124,11 @@ static int update_display_mode(struct dc_disp_reg *disp, div = ((rate * 2 + config->pixel_clock / 2) / config->pixel_clock) - 2; printk(BIOS_SPEW, "Display clock %d, divider %d\n", rate, div); - writel(0x00010001, &disp->shift_clk_opt); + WRITEL(0x00010001, &disp->shift_clk_opt); val = PIXEL_CLK_DIVIDER_PCD1 << PIXEL_CLK_DIVIDER_SHIFT; val |= div << SHIFT_CLK_DIVIDER_SHIFT; - writel(val, &disp->disp_clk_ctrl); + WRITEL(val, &disp->disp_clk_ctrl); return 0; } @@ -157,55 +174,55 @@ static void update_window(struct display_controller *dc, u32 h_dda, v_dda; u32 val; - val = readl(&dc->cmd.disp_win_header); + val = READL(&dc->cmd.disp_win_header); val |= WINDOW_A_SELECT; - writel(val, &dc->cmd.disp_win_header); + WRITEL(val, &dc->cmd.disp_win_header); - writel(win->fmt, &dc->win.color_depth); + WRITEL(win->fmt, &dc->win.color_depth); clrsetbits_le32(&dc->win.byte_swap, BYTE_SWAP_MASK, BYTE_SWAP_NOSWAP << BYTE_SWAP_SHIFT); val = win->out_x << H_POSITION_SHIFT; val |= win->out_y << V_POSITION_SHIFT; - writel(val, &dc->win.pos); + WRITEL(val, &dc->win.pos); val = win->out_w << H_SIZE_SHIFT; val |= win->out_h << V_SIZE_SHIFT; - writel(val, &dc->win.size); + WRITEL(val, &dc->win.size); val = (win->w * win->bpp / 8) << H_PRESCALED_SIZE_SHIFT; val |= win->h << V_PRESCALED_SIZE_SHIFT; - writel(val, &dc->win.prescaled_size); + WRITEL(val, &dc->win.prescaled_size); - writel(0, &dc->win.h_initial_dda); - writel(0, &dc->win.v_initial_dda); + WRITEL(0, &dc->win.h_initial_dda); + WRITEL(0, &dc->win.v_initial_dda); h_dda = (win->w * 0x1000) / MAX(win->out_w - 1, 1); v_dda = (win->h * 0x1000) / MAX(win->out_h - 1, 1); val = h_dda << H_DDA_INC_SHIFT; val |= v_dda << V_DDA_INC_SHIFT; - writel(val, &dc->win.dda_increment); + WRITEL(val, &dc->win.dda_increment); - writel(win->stride, &dc->win.line_stride); - writel(0, &dc->win.buf_stride); + WRITEL(win->stride, &dc->win.line_stride); + WRITEL(0, &dc->win.buf_stride); val = WIN_ENABLE; if (win->bpp < 24) val |= COLOR_EXPAND; - writel(val, &dc->win.win_opt); + WRITEL(val, &dc->win.win_opt); - writel((u32) win->phys_addr, &dc->winbuf.start_addr); - writel(win->x, &dc->winbuf.addr_h_offset); - writel(win->y, &dc->winbuf.addr_v_offset); + WRITEL((u32) win->phys_addr, &dc->winbuf.start_addr); + WRITEL(win->x, &dc->winbuf.addr_h_offset); + WRITEL(win->y, &dc->winbuf.addr_v_offset); - writel(0xff00, &dc->win.blend_nokey); - writel(0xff00, &dc->win.blend_1win); + WRITEL(0xff00, &dc->win.blend_nokey); + WRITEL(0xff00, &dc->win.blend_1win); val = GENERAL_ACT_REQ | WIN_A_ACT_REQ; val |= GENERAL_UPDATE | WIN_A_UPDATE; - writel(val, &dc->cmd.state_ctrl); + WRITEL(val, &dc->cmd.state_ctrl); } /* this is really aimed at the lcd panel. That said, there are two display @@ -222,7 +239,36 @@ void display_startup(device_t dev) /* should probably just make it all MiB ... in future */ u32 framebuffer_size_mb = config->framebuffer_size / MiB; u32 framebuffer_base_mb= config->framebuffer_base / MiB; + /* light it all up */ + /* This one may have been done in romstage but that's ok for now. */ + if (config->panel_vdd_gpio){ + gpio_output(config->panel_vdd_gpio, 1); + printk(BIOS_SPEW,"%s: panel_vdd setting gpio %08x to %d\n", + __func__, config->panel_vdd_gpio, 1); + } + delay(1); + if (config->backlight_vdd_gpio){ + gpio_output(config->backlight_vdd_gpio, 1); + printk(BIOS_SPEW,"%s: backlight vdd setting gpio %08x to %d\n", + __func__, config->backlight_vdd_gpio, 1); + } + delay(1); + if (config->lvds_shutdown_gpio){ + gpio_output(config->lvds_shutdown_gpio, 0); + printk(BIOS_SPEW,"%s: lvds shutdown setting gpio %08x to %d\n", + __func__, config->lvds_shutdown_gpio, 0); + } + if (config->backlight_en_gpio){ + gpio_output(config->backlight_en_gpio, 1); + printk(BIOS_SPEW,"%s: backlight enable setting gpio %08x to %d\n", + __func__, config->backlight_en_gpio, 1); + } + if (config->pwm){ + gpio_output(config->pwm, 1); + printk(BIOS_SPEW,"%s: pwm setting gpio %08x to %d\n", + __func__, config->pwm, 1); + } printk(BIOS_SPEW, "%s: xres %d yres %d framebuffer_bits_per_pixel %d\n", __func__, @@ -252,53 +298,73 @@ void display_startup(device_t dev) * The panel_vdd is done in the romstage, so we need only * light things up here once we're sure it's all working. */ - setbits_le32(&clk_rst->rst_dev_l, CLK_L_DISP1 | CLK_L_HOST1X); - clock_ll_set_source_divisor(&clk_rst->clk_src_host1x, 4, - CLK_DIVIDER(TEGRA_PLLP_KHZ, 144000)); - /* u-boot uses PLLC for DISP1. - * But the u-boot code does not work and we don't set up PLLC anyway. - * PLLP seems quite good enough, so run with that for now. */ - clock_ll_set_source_divisor(&clk_rst->clk_src_disp1, 0 /* 4 */, - CLK_DIVIDER(TEGRA_PLLP_KHZ, 600000)); + /* init dc_a */ + init_dca_regs(); + /* init sor */ + init_sor_regs(); + + /* init dpaux */ + init_dpaux_regs(); + + /* power up perip */ + dp_io_powerup(); - udelay(2); + /* bringup dp */ + dp_bringup(framebuffer_base_mb*MiB); - clrbits_le32(&clk_rst->rst_dev_l, CLK_L_DISP1|CLK_L_HOST1X); + { u16 *cp = (void *)(framebuffer_base_mb*MiB); + for(i = 0; i < 1048576*8; i++) + if (i %(2560/2) < 1280/2) + cp[i] = 0x222; + else + cp[i] = 0x888; + } - writel(0x00000100, &dc->cmd.gen_incr_syncpt_ctrl); - writel(0x0000011a, &dc->cmd.cont_syncpt_vsync); - writel(0x00000000, &dc->cmd.int_type); - writel(0x00000000, &dc->cmd.int_polarity); - writel(0x00000000, &dc->cmd.int_mask); - writel(0x00000000, &dc->cmd.int_enb); + /* tell depthcharge ... + */ + struct edid edid; + edid.x_resolution = 2560; + edid.y_resolution = 1700; + edid.bytes_per_line = 2560 * 2; + edid.framebuffer_bits_per_pixel = 16; + set_vbe_mode_info_valid(&edid, (uintptr_t)(framebuffer_base_mb*MiB)); + + if (0){ +/* do we still need these? */ + WRITEL(0x00000100, &dc->cmd.gen_incr_syncpt_ctrl); + WRITEL(0x0000011a, &dc->cmd.cont_syncpt_vsync); + WRITEL(0x00000000, &dc->cmd.int_type); + WRITEL(0x00000000, &dc->cmd.int_polarity); + WRITEL(0x00000000, &dc->cmd.int_mask); + WRITEL(0x00000000, &dc->cmd.int_enb); val = PW0_ENABLE | PW1_ENABLE | PW2_ENABLE; val |= PW3_ENABLE | PW4_ENABLE | PM0_ENABLE; val |= PM1_ENABLE; - writel(val, &dc->cmd.disp_pow_ctrl); + WRITEL(val, &dc->cmd.disp_pow_ctrl); - val = readl(&dc->cmd.disp_cmd); + val = READL(&dc->cmd.disp_cmd); val |= CTRL_MODE_C_DISPLAY << CTRL_MODE_SHIFT; - writel(val, &dc->cmd.disp_cmd); + WRITEL(val, &dc->cmd.disp_cmd); - writel(0x00000020, &dc->disp.mem_high_pri); - writel(0x00000001, &dc->disp.mem_high_pri_timer); + WRITEL(0x00000020, &dc->disp.mem_high_pri); + WRITEL(0x00000001, &dc->disp.mem_high_pri_timer); for (i = 0; i < PIN_REG_COUNT; i++) { - writel(rgb_enb_tab[i], &dc->com.pin_output_enb[i]); - writel(rgb_polarity_tab[i], &dc->com.pin_output_polarity[i]); - writel(rgb_data_tab[i], &dc->com.pin_output_data[i]); + WRITEL(rgb_enb_tab[i], &dc->com.pin_output_enb[i]); + WRITEL(rgb_polarity_tab[i], &dc->com.pin_output_polarity[i]); + WRITEL(rgb_data_tab[i], &dc->com.pin_output_data[i]); } for (i = 0; i < PIN_OUTPUT_SEL_COUNT; i++) - writel(rgb_sel_tab[i], &dc->com.pin_output_sel[i]); + WRITEL(rgb_sel_tab[i], &dc->com.pin_output_sel[i]); if (config->pixel_clock) update_display_mode(&dc->disp, config); if (!setup_window(&window, config)) update_window(dc, &window, config); - + } } diff --git a/src/soc/nvidia/tegra124/displayhack.c b/src/soc/nvidia/tegra124/displayhack.c new file mode 100644 index 0000000..847d6f6 --- /dev/null +++ b/src/soc/nvidia/tegra124/displayhack.c @@ -0,0 +1,1333 @@ +/* this is too ugly to be allowed to live. But it's what works for now. */ +/* + * This file is part of the coreboot project. + * + * Copyright 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <arch/io.h> +#include <stdint.h> +#include <lib.h> +#include <stdlib.h> +#include <delay.h> +#include <soc/addressmap.h> +#include <device/device.h> +#include <stdlib.h> +#include <string.h> +#include <cpu/cpu.h> +#include <boot/tables.h> +#include <cbmem.h> +#include <soc/nvidia/tegra/dc.h> +#include "clk_rst.h" +#include <soc/clock.h> +#include "chip.h" +#include "sor.h" +#include <soc/display.h> +#include <soc/ardisplay.h> +#include <soc/arsor.h> +#include <soc/ardpaux.h> +//#include <soc/nvidia/tegra/displayport.h> +extern int dump; +unsigned long READL(void *p); +void WRITEL(unsigned long value, void *p); +void debug_dpaux_print(u32 addr, u32 size); +int dpaux_write(u32 addr, u32 size, u32 data); +int dpaux_read(u32 addr, u32 size, u8 * data); + +void init_dca_regs(void) +{ + struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)TEGRA_CLK_RST_BASE; +// u32 val; + + printk(BIOS_SPEW, "JZ: %s: entry\n", __func__); + +#define SWR_DISP1_RST (1 << 27) +#define SWR_HOST1X_RST (1 << 28) +#define CLK_ENB_DISP1 SWR_DISP1_RST +#define CLK_ENB_HOST1X SWR_HOST1X_RST +// REG(CLK_RST_CONTROLLER_RST_DEVICES_L_0, SWR_DISP1_RST, 1); +// REG(CLK_RST_CONTROLLER_RST_DEVICES_L_0, SWR_DISP1_RST, 0); +// REG(CLK_RST_CONTROLLER_CLK_OUT_ENB_L_0, CLK_ENB_DISP1, 1); + /* enable disp1 */ + setbits_le32(&clkrst->rst_dev_l, SWR_DISP1_RST); // Set Reset + clrbits_le32(&clkrst->rst_dev_l, SWR_DISP1_RST); // Clear Reset + setbits_le32(&clkrst->clk_out_enb_l, CLK_ENB_DISP1); // Set Enable + WRITEL(0x00000000, (void *)(0x60006000 + 0x138)); // CLK_SOURCE_DISP1 = PLLP +// WRITEL(0x40000000, (void *)(0x60006000 + 0x138)); // CLK_SOURCE_DISP1 = PLLD + /* enable host1x */ + clrbits_le32(&clkrst->rst_dev_l, SWR_HOST1X_RST); // Clear Reset + setbits_le32(&clkrst->clk_out_enb_l, CLK_ENB_HOST1X); // Set Enable + WRITEL(0x80000000, (void *)(0x60006000 + 0x180)); // CLK_SOURCE_HOST1X = PLLP +// WRITEL(0x40000000, (0x60006000 + 0x180)); // CLK_SOURCE_HOST1X = PLLC + +#if 1 +#define DCA_WRITE(reg, val) \ + { \ + WRITEL(val, (void *)(TEGRA_ARM_DISPLAYA + (reg<<2))); \ + } +#define DCA_READ_M_WRITE(reg, mask, val) \ + { \ + u32 _reg_val; \ + _reg_val = READL( (void *)(TEGRA_ARM_DISPLAYA + (reg<<2))); \ + _reg_val &= ~mask; \ + _reg_val |= val; \ + WRITEL(_reg_val, (void *)(TEGRA_ARM_DISPLAYA + (reg<<2))); \ + } +#else // read back +#define DCA_WRITE(reg, val) \ + { \ + printk(BIOS_SPEW,"DCA_WRITE: addr %#x = %#x\n", + (unsigned int) (TEGRA_ARM_DISPLAYA + (reg<<2)), val); \ + WRITEL(val, (void *)(TEGRA_ARM_DISPLAYA + (reg<<2))); \ + printk(BIOS_SPEW,"reads as %#x\n", \ + (unsigned int)READL( (void *)(TEGRA_ARM_DISPLAYA + (reg<<2)))); \ + } +#endif + + DCA_WRITE(DC_DISP_DISP_CLOCK_CONTROL_0, 0x00000006); //0x542410b8 + DCA_WRITE(DC_CMD_INT_STATUS_0, 0xffffffff); //0x542400dc + DCA_WRITE(DC_CMD_INT_MASK_0, 0x00000000); //0x542400e0 + DCA_WRITE(DC_CMD_INT_ENABLE_0, 0x00800701); //0x542400e4 + DCA_WRITE(DC_CMD_INT_POLARITY_0, 0x00c00706); //0x542400ec + DCA_WRITE(DC_DISP_DISP_SIGNAL_OPTIONS0_0, 0x00000000); //0x54241000 + DCA_WRITE(DC_DISP_DISP_SIGNAL_OPTIONS1_0, 0x00000000); //0x54241004 + DCA_WRITE(DC_DISP_DISP_WIN_OPTIONS_0, 0x00000000); //0x54241008 + DCA_WRITE(DC_DISP_MEM_HIGH_PRIORITY_0, 0x00000000); //0x5424100c + DCA_WRITE(DC_DISP_MEM_HIGH_PRIORITY_TIMER_0, 0x00000000); //0x54241010 + DCA_WRITE(DC_DISP_DISP_TIMING_OPTIONS_0, 0x00000000); //0x54241014 + DCA_WRITE(DC_DISP_REF_TO_SYNC_0, 0x00000000); //0x54241018 + DCA_WRITE(DC_DISP_SYNC_WIDTH_0, 0x00000000); //0x5424101c + DCA_WRITE(DC_DISP_BACK_PORCH_0, 0x00000000); //0x54241020 + DCA_WRITE(DC_DISP_DISP_ACTIVE_0, 0x00030003); //0x54241024 + DCA_WRITE(DC_DISP_FRONT_PORCH_0, 0x00000000); //0x54241028 + DCA_WRITE(DC_DISP_H_PULSE0_CONTROL_0, 0x00000000); //0x5424102c + DCA_WRITE(DC_DISP_H_PULSE0_POSITION_A_0, 0x00000000); //0x54241030 + DCA_WRITE(DC_DISP_H_PULSE0_POSITION_B_0, 0x00000000); //0x54241034 + DCA_WRITE(DC_DISP_H_PULSE0_POSITION_C_0, 0x00000000); //0x54241038 + DCA_WRITE(DC_DISP_H_PULSE0_POSITION_D_0, 0x00000000); //0x5424103c + DCA_WRITE(DC_DISP_H_PULSE1_CONTROL_0, 0x00000000); //0x54241040 + DCA_WRITE(DC_DISP_H_PULSE1_POSITION_A_0, 0x00000000); //0x54241044 + DCA_WRITE(DC_DISP_H_PULSE1_POSITION_B_0, 0x00000000); //0x54241048 + DCA_WRITE(DC_DISP_H_PULSE1_POSITION_C_0, 0x00000000); //0x5424104c + DCA_WRITE(DC_DISP_H_PULSE1_POSITION_D_0, 0x00000000); //0x54241050 + DCA_WRITE(DC_DISP_H_PULSE2_CONTROL_0, 0x00000000); //0x54241054 + DCA_WRITE(DC_DISP_H_PULSE2_POSITION_A_0, 0x00000000); //0x54241058 + DCA_WRITE(DC_DISP_H_PULSE2_POSITION_B_0, 0x00000000); //0x5424105c + DCA_WRITE(DC_DISP_H_PULSE2_POSITION_C_0, 0x00000000); //0x54241060 + DCA_WRITE(DC_DISP_H_PULSE2_POSITION_D_0, 0x00000000); //0x54241064 + DCA_WRITE(DC_DISP_V_PULSE0_CONTROL_0, 0x00000000); //0x54241068 + DCA_WRITE(DC_DISP_V_PULSE0_POSITION_A_0, 0x00000000); //0x5424106c + DCA_WRITE(DC_DISP_V_PULSE0_POSITION_B_0, 0x00000000); //0x54241070 + DCA_WRITE(DC_DISP_V_PULSE0_POSITION_C_0, 0x00000000); //0x54241074 + DCA_WRITE(DC_DISP_V_PULSE1_CONTROL_0, 0x00000000); //0x54241078 + DCA_WRITE(DC_DISP_V_PULSE1_POSITION_A_0, 0x00000000); //0x5424107c + DCA_WRITE(DC_DISP_V_PULSE1_POSITION_B_0, 0x00000000); //0x54241080 + DCA_WRITE(DC_DISP_V_PULSE1_POSITION_C_0, 0x00000000); //0x54241084 + DCA_WRITE(DC_DISP_V_PULSE2_CONTROL_0, 0x00000000); //0x54241088 + DCA_WRITE(DC_DISP_V_PULSE2_POSITION_A_0, 0x00000000); //0x5424108c + DCA_WRITE(DC_DISP_V_PULSE3_CONTROL_0, 0x00000000); //0x54241090 + DCA_WRITE(DC_DISP_V_PULSE3_POSITION_A_0, 0x00000000); //0x54241094 + DCA_WRITE(DC_DISP_M0_CONTROL_0, 0x00000000); //0x54241098 + DCA_WRITE(DC_DISP_M1_CONTROL_0, 0x00000000); //0x5424109c + DCA_WRITE(DC_DISP_DI_CONTROL_0, 0x00000000); //0x542410a0 + DCA_WRITE(DC_DISP_PP_CONTROL_0, 0x00000000); //0x542410a4 + DCA_WRITE(DC_DISP_PP_SELECT_A_0, 0x00000000); //0x542410a8 + DCA_WRITE(DC_DISP_PP_SELECT_B_0, 0x00000000); //0x542410ac + DCA_WRITE(DC_DISP_PP_SELECT_C_0, 0x00000000); //0x542410b0 + DCA_WRITE(DC_DISP_PP_SELECT_D_0, 0x00000000); //0x542410b4 + DCA_WRITE(DC_DISP_DISP_INTERFACE_CONTROL_0, 0x00000000); //0x542410bc + DCA_WRITE(DC_DISP_DISP_COLOR_CONTROL_0, 0x00000000); //0x542410c0 + DCA_WRITE(DC_DISP_SHIFT_CLOCK_OPTIONS_0, 0x00000000); //0x542410c4 + DCA_WRITE(DC_DISP_DATA_ENABLE_OPTIONS_0, 0x00000000); //0x542410c8 + DCA_WRITE(DC_DISP_SERIAL_INTERFACE_OPTIONS_0, 0x00000000); //0x542410cc + DCA_WRITE(DC_DISP_LCD_SPI_OPTIONS_0, 0x00000000); //0x542410d0 + DCA_WRITE(DC_DISP_COLOR_KEY0_LOWER_0, 0x00000000); //0x542410d8 + DCA_WRITE(DC_DISP_COLOR_KEY0_UPPER_0, 0x00000000); //0x542410dc + DCA_WRITE(DC_DISP_COLOR_KEY1_LOWER_0, 0x00000000); //0x542410e0 + DCA_WRITE(DC_DISP_COLOR_KEY1_UPPER_0, 0x00000000); //0x542410e4 + DCA_WRITE(DC_DISP_CURSOR_FOREGROUND_0, 0x00000000); //0x542410f0 + DCA_WRITE(DC_DISP_CURSOR_BACKGROUND_0, 0x00000000); //0x542410f4 + DCA_WRITE(DC_DISP_CURSOR_START_ADDR_0, 0x00200000); //0x542410f8 + DCA_WRITE(DC_DISP_CURSOR_START_ADDR_NS_0, 0x00000000); //0x542410fc + DCA_WRITE(DC_DISP_CURSOR_POSITION_0, 0x00000000); //0x54241100 + DCA_WRITE(DC_DISP_CURSOR_POSITION_NS_0, 0x00000000); //0x54241104 + DCA_WRITE(DC_DISP_INIT_SEQ_CONTROL_0, 0x00000000); //0x54241108 + DCA_WRITE(DC_DISP_SPI_INIT_SEQ_DATA_A_0, 0x00000000); //0x5424110c + DCA_WRITE(DC_DISP_SPI_INIT_SEQ_DATA_B_0, 0x00000000); //0x54241110 + DCA_WRITE(DC_DISP_SPI_INIT_SEQ_DATA_C_0, 0x00000000); //0x54241114 + DCA_WRITE(DC_DISP_SPI_INIT_SEQ_DATA_D_0, 0x00000000); //0x54241118 + DCA_WRITE(DC_DISP_DC_MCCIF_FIFOCTRL_0, 0x00000000); //0x54241200 + DCA_WRITE(DC_DISP_MCCIF_DISPLAY0A_HYST_0, 0xcf401f1f); //0x54241204 + DCA_WRITE(DC_DISP_MCCIF_DISPLAY0B_HYST_0, 0xcf401f1f); //0x54241208 + DCA_WRITE(DC_DISP_MCCIF_DISPLAY0C_HYST_0, 0xcf401f1f); //0x5424120c + DCA_WRITE(DC_DISP_DISP_MISC_CONTROL_0, 0x00000002); //0x54241304 + DCA_WRITE(DC_DISP_SD_CONTROL_0, 0x00004000); //0x54241308 + DCA_WRITE(DC_DISP_SD_CSC_COEFF_0, 0x00000000); //0x5424130c + + DCA_WRITE(DC_DISP_SD_LUT_0, 0x00000000); //0x54241310 +#define DC_DISP_SD_LUT_1_0 0x4c5 +#define DC_DISP_SD_LUT_2_0 0x4c6 +#define DC_DISP_SD_LUT_3_0 0x4c7 +#define DC_DISP_SD_LUT_4_0 0x4c8 +#define DC_DISP_SD_LUT_5_0 0x4c9 +#define DC_DISP_SD_LUT_6_0 0x4ca +#define DC_DISP_SD_LUT_7_0 0x4cb +#define DC_DISP_SD_LUT_8_0 0x4cc + DCA_WRITE(DC_DISP_SD_LUT_1_0, 0x00000000); //0x54241314 + DCA_WRITE(DC_DISP_SD_LUT_2_0, 0x00000000); //0x54241318 + DCA_WRITE(DC_DISP_SD_LUT_3_0, 0x00000000); //0x5424131c + DCA_WRITE(DC_DISP_SD_LUT_4_0, 0x00000000); //0x54241320 + DCA_WRITE(DC_DISP_SD_LUT_5_0, 0x00000000); //0x54241324 + DCA_WRITE(DC_DISP_SD_LUT_6_0, 0x00000000); //0x54241328 + DCA_WRITE(DC_DISP_SD_LUT_7_0, 0x00000000); //0x5424132c + DCA_WRITE(DC_DISP_SD_LUT_8_0, 0x00000000); //0x54241330 + DCA_WRITE(DC_DISP_SD_FLICKER_CONTROL_0, 0x00000000); //0x54241334 + DCA_WRITE(DC_DISP_SD_PIXEL_COUNT_0, 0x00000000); //0x54241338 + + DCA_WRITE(DC_DISP_SD_HISTOGRAM_0, 0x00000000); //0x5424133c +#define DC_DISP_SD_HISTOGRAM_1_0 0x4d0 +#define DC_DISP_SD_HISTOGRAM_2_0 0x4d1 +#define DC_DISP_SD_HISTOGRAM_3_0 0x4d2 +#define DC_DISP_SD_HISTOGRAM_4_0 0x4d3 +#define DC_DISP_SD_HISTOGRAM_5_0 0x4d4 +#define DC_DISP_SD_HISTOGRAM_6_0 0x4d5 +#define DC_DISP_SD_HISTOGRAM_7_0 0x4d6 + DCA_WRITE(DC_DISP_SD_HISTOGRAM_1_0, 0x00000000); //0x54241340 + DCA_WRITE(DC_DISP_SD_HISTOGRAM_2_0, 0x00000000); //0x54241344 + DCA_WRITE(DC_DISP_SD_HISTOGRAM_3_0, 0x00000000); //0x54241348 + DCA_WRITE(DC_DISP_SD_HISTOGRAM_4_0, 0x00000000); //0x5424134c + DCA_WRITE(DC_DISP_SD_HISTOGRAM_5_0, 0x00000000); //0x54241350 + DCA_WRITE(DC_DISP_SD_HISTOGRAM_6_0, 0x00000000); //0x54241354 + DCA_WRITE(DC_DISP_SD_HISTOGRAM_7_0, 0x00000000); //0x54241358 + DCA_WRITE(DC_DISP_SD_BL_PARAMETERS_0, 0x00000400); //0x5424135c + DCA_WRITE(DC_DISP_SD_BL_TF_0, 0x00000000); //0x54241360 +#define DC_DISP_SD_BL_TF_1_0 0x4d9 +#define DC_DISP_SD_BL_TF_2_0 0x4da +#define DC_DISP_SD_BL_TF_3_0 0x4db + DCA_WRITE(DC_DISP_SD_BL_TF_1_0, 0x00000000); //0x54241364 + DCA_WRITE(DC_DISP_SD_BL_TF_2_0, 0x00000000); //0x54241368 + DCA_WRITE(DC_DISP_SD_BL_TF_3_0, 0x00000000); //0x5424136c + DCA_WRITE(DC_DISP_SD_BL_CONTROL_0, 0x00000000); //0x54241370 + DCA_WRITE(DC_DISP_SD_HW_K_VALUES_0, 0x00000000); //0x54241374 + DCA_WRITE(DC_DISP_SD_MAN_K_VALUES_0, 0x00000000); //0x54241378 + DCA_WRITE(DC_DISP_SD_K_LIMIT_0, 0x00000000); //0x5424137c + DCA_WRITE(DC_DISP_SD_WINDOW_POSITION_0, 0x00000000); //0x54241380 + DCA_WRITE(DC_DISP_SD_WINDOW_SIZE_0, 0x00000000); //0x54241384 + DCA_WRITE(DC_DISP_SD_SOFT_CLIPPING_0, 0x02000080); //0x54241388 + DCA_WRITE(DC_DISP_SD_SMOOTH_K_0, 0x00000000); //0x5424138c + DCA_WRITE(DC_DISP_BLEND_BACKGROUND_COLOR_0, 0x00000000); //0x54241390 + DCA_WRITE(DC_DISP_INTERLACE_CONTROL_0, 0x00000000); //0x54241394 + DCA_WRITE(DC_DISP_INTERLACE_FIELD2_REF_TO_SYNC_0, 0x00000000); //0x54241398 + DCA_WRITE(DC_DISP_INTERLACE_FIELD2_SYNC_WIDTH_0, 0x00000000); //0x5424139c + DCA_WRITE(DC_DISP_INTERLACE_FIELD2_BACK_PORCH_0, 0x00000000); //0x542413a0 + DCA_WRITE(DC_DISP_INTERLACE_FIELD2_FRONT_PORCH_0, 0x00000000); //0x542413a4 + DCA_WRITE(DC_DISP_INTERLACE_FIELD2_DISP_ACTIVE_0, 0x00000000); //0x542413a8 + DCA_WRITE(DC_DISP_CURSOR_UNDERFLOW_CTRL_0, 0x00000000); //0x542413ac + DCA_WRITE(DC_DISP_CURSOR_START_ADDR_HI_0, 0x00000000); //0x542413b0 + DCA_WRITE(DC_DISP_CURSOR_START_ADDR_HI_NS_0, 0x00000000); //0x542413b4 + DCA_WRITE(DC_DISP_CURSOR_INTERLACE_CONTROL_0, 0x00000000); //0x542413b8 + DCA_WRITE(DC_DISP_CSC2_CONTROL_0, 0x00000000); //0x542413bc + DCA_WRITE(DC_DISP_BLEND_CURSOR_CONTROL_0, 0x00000000); //0x542413c4 + DCA_WRITE(DC_DISP_DVFS_CURSOR_CONTROL_0, 0x00000003); //0x542413c8 + DCA_WRITE(DC_DISP_CURSOR_UFLOW_DBG_PIXEL_0, 0x00000000); //0x542413cc + DCA_WRITE(DC_DISP_CURSOR_SPOOLUP_CONTROL_0, 0x00000001); //0x542413d0 + DCA_WRITE(DC_DISP_DISPLAY_CLK_GATE_OVERRIDE_0, 0x00000000); //0x542413d4 + DCA_WRITE(DC_DISP_DISPLAY_DBG_TIMING_0, 0x00000000); //0x542413d8 + DCA_WRITE(DC_DISP_DISPLAY_SPARE0_0, 0x00000000); //0x542413dc + DCA_WRITE(DC_DISP_DISPLAY_SPARE1_0, 0x00000000); //0x542413e0 + +#define wr32(reg, val) \ + WRITEL(val, (void *)reg) + + wr32((TEGRA_ARM_DISPLAYA + 0x0200), 0x00000000); + wr32((TEGRA_ARM_DISPLAYA + 0x0400), 0x00000000); + + DCA_WRITE(DC_CMD_DISPLAY_WINDOW_HEADER_0, 0x000000F0); + DCA_WRITE(DC_WIN_A_WIN_OPTIONS_0, 0x00000000); + DCA_WRITE(DC_WIN_A_BYTE_SWAP_0, 0x00000000); + DCA_WRITE(DC_WIN_A_BUFFER_CONTROL_0, 0x00000000); + DCA_WRITE(DC_WIN_A_COLOR_DEPTH_0, 0x0000000C); + DCA_WRITE(DC_WIN_A_POSITION_0, 0x00000000); + DCA_WRITE(DC_WIN_A_SIZE_0, 0x00000000); + DCA_WRITE(DC_WIN_A_PRESCALED_SIZE_0, 0x00000000); + DCA_WRITE(DC_WIN_A_H_INITIAL_DDA_0, 0x00000000); + DCA_WRITE(DC_WIN_A_V_INITIAL_DDA_0, 0x00000000); + DCA_WRITE(DC_WIN_A_DDA_INCREMENT_0, 0x00000000); + DCA_WRITE(DC_WIN_A_LINE_STRIDE_0, 0x00000000); + DCA_WRITE(DC_WIN_A_DV_CONTROL_0, 0x00000000); + + DCA_WRITE(DC_WIN_A_BLEND_LAYER_CONTROL_0, 0x01000000); + DCA_WRITE(DC_WIN_A_BLEND_MATCH_SELECT_0, 0x00000000); + DCA_WRITE(DC_WIN_A_BLEND_NOMATCH_SELECT_0, 0x00000000); + DCA_WRITE(DC_WIN_A_BLEND_ALPHA_1BIT_0, 0x00000000); + DCA_WRITE(DC_WINC_A_PALETTE_COLOR_EXT_0, 0x00000000); + DCA_WRITE(DC_WINC_A_CSC_YOF_0, 0x00000000); + DCA_WRITE(DC_WINC_A_CSC_KYRGB_0, 0x00000000); + DCA_WRITE(DC_WINC_A_CSC_KUR_0, 0x00000000); + DCA_WRITE(DC_WINC_A_CSC_KVR_0, 0x00000000); + DCA_WRITE(DC_WINC_A_CSC_KUG_0, 0x00000000); + DCA_WRITE(DC_WINC_A_CSC_KVG_0, 0x00000000); + DCA_WRITE(DC_WINC_A_CSC_KUB_0, 0x00000000); + DCA_WRITE(DC_WINC_A_CSC_KVB_0, 0x00000000); + DCA_WRITE(DC_WINBUF_A_START_ADDR_HI_0, 0x00000000); + DCA_WRITE(DC_WINBUF_A_ADDR_H_OFFSET_0, 0x00000000); + DCA_WRITE(DC_WINBUF_A_ADDR_V_OFFSET_0, 0x00000000); + DCA_WRITE(DC_CMD_DISPLAY_WINDOW_HEADER_0, 0x00000000); + + DCA_WRITE(DC_COM_CRC_CONTROL_0, 0x00000000); //0x54240c00 + DCA_WRITE(DC_COM_CRC_CHECKSUM_0, 0x00000000); //0x54240c04 + DCA_WRITE(DC_COM_PIN_OUTPUT_ENABLE0_0, 0x00000000); //0x54240c08 + DCA_WRITE(DC_COM_PIN_OUTPUT_ENABLE1_0, 0x00000000); //0x54240c0c + DCA_WRITE(DC_COM_PIN_OUTPUT_ENABLE2_0, 0x00510104); //0x54240c10 + DCA_WRITE(DC_COM_PIN_OUTPUT_ENABLE3_0, 0x00000555); //0x54240c14 + DCA_WRITE(DC_COM_PIN_OUTPUT_POLARITY0_0, 0x00000000); //0x54240c18 + DCA_WRITE(DC_COM_PIN_OUTPUT_POLARITY1_0, 0x00000000); //0x54240c1c + DCA_WRITE(DC_COM_PIN_OUTPUT_POLARITY2_0, 0x00000000); //0x54240c20 + DCA_WRITE(DC_COM_PIN_OUTPUT_POLARITY3_0, 0x00000000); //0x54240c24 + DCA_WRITE(DC_COM_PIN_OUTPUT_DATA0_0, 0x00000000); //0x54240c28 + DCA_WRITE(DC_COM_PIN_OUTPUT_DATA1_0, 0x00000000); //0x54240c2c + DCA_WRITE(DC_COM_PIN_OUTPUT_DATA2_0, 0x00000000); //0x54240c30 + DCA_WRITE(DC_COM_PIN_OUTPUT_DATA3_0, 0x00000000); //0x54240c34 + DCA_WRITE(DC_COM_PIN_INPUT_DATA0_0, 0x00000000); //0x54240c48 + DCA_WRITE(DC_COM_PIN_INPUT_DATA1_0, 0x00000000); //0x54240c4c + DCA_WRITE(DC_COM_PIN_OUTPUT_SELECT0_0, 0x00000000); //0x54240c50 + DCA_WRITE(DC_COM_PIN_OUTPUT_SELECT1_0, 0x00000000); //0x54240c54 + DCA_WRITE(DC_COM_PIN_OUTPUT_SELECT2_0, 0x00000000); //0x54240c58 + DCA_WRITE(DC_COM_PIN_OUTPUT_SELECT3_0, 0x00000000); //0x54240c5c + DCA_WRITE(DC_COM_PIN_OUTPUT_SELECT4_0, 0x00000000); //0x54240c60 + DCA_WRITE(DC_COM_PIN_OUTPUT_SELECT5_0, 0x00000000); //0x54240c64 + DCA_WRITE(DC_COM_PIN_OUTPUT_SELECT6_0, 0x00000000); //0x54240c68 + DCA_WRITE(DC_COM_PIN_MISC_CONTROL_0, 0x00000000); //0x54240c6c + DCA_WRITE(DC_COM_PM0_CONTROL_0, 0x00000000); //0x54240c70 + DCA_WRITE(DC_COM_PM0_DUTY_CYCLE_0, 0x00000000); //0x54240c74 + DCA_WRITE(DC_COM_PM1_CONTROL_0, 0x00000000); //0x54240c78 + DCA_WRITE(DC_COM_PM1_DUTY_CYCLE_0, 0x00000000); //0x54240c7c + DCA_WRITE(DC_COM_SPI_CONTROL_0, 0x00000000); //0x54240c80 + DCA_WRITE(DC_COM_SPI_START_BYTE_0, 0x00000000); //0x54240c84 + DCA_WRITE(DC_COM_HSPI_WRITE_DATA_AB_0, 0x00000000); //0x54240c88 + DCA_WRITE(DC_COM_HSPI_WRITE_DATA_CD_0, 0x00000000); //0x54240c8c + DCA_WRITE(DC_COM_HSPI_CS_DC_0, 0x00000000); //0x54240c90 + DCA_WRITE(DC_COM_SCRATCH_REGISTER_A_0, 0x00000000); //0x54240c94 + DCA_WRITE(DC_COM_SCRATCH_REGISTER_B_0, 0x00000000); //0x54240c98 + DCA_WRITE(DC_COM_CRC_CHECKSUM_LATCHED_0, 0x00000000); //0x54240ca4 + DCA_WRITE(DC_COM_CMU_CSC_KRR_0, 0x00000000); //0x54240ca8 + DCA_WRITE(DC_COM_CMU_CSC_KGR_0, 0x00000000); //0x54240cac + DCA_WRITE(DC_COM_CMU_CSC_KBR_0, 0x00000000); //0x54240cb0 + DCA_WRITE(DC_COM_CMU_CSC_KRG_0, 0x00000000); //0x54240cb4 + DCA_WRITE(DC_COM_CMU_CSC_KGG_0, 0x00000000); //0x54240cb8 + DCA_WRITE(DC_COM_CMU_CSC_KBG_0, 0x00000000); //0x54240cbc + DCA_WRITE(DC_COM_CMU_CSC_KRB_0, 0x00000000); //0x54240cc0 + DCA_WRITE(DC_COM_CMU_CSC_KGB_0, 0x00000000); //0x54240cc4 + DCA_WRITE(DC_COM_CMU_CSC_KBB_0, 0x00000000); //0x54240cc8 + DCA_WRITE(DC_COM_CMU_LUT_MASK_0, 0x00000000); //0x54240ccc + DCA_WRITE(DC_COM_CMU_LUT1_0, 0x00000000); //0x54240cd8 + DCA_WRITE(DC_COM_CMU_LUT2_0, 0x00000000); //0x54240cdc + DCA_WRITE(DC_COM_CMU_LUT1_READ_0, 0x00000000); //0x54240ce0 + DCA_WRITE(DC_COM_CMU_LUT2_READ_0, 0x00000000); //0x54240ce4 + DCA_WRITE(DC_CMD_GENERAL_INCR_SYNCPT_CNTRL_0, 0x00000000); //0x54240004 + DCA_WRITE(DC_CMD_GENERAL_INCR_SYNCPT_ERROR_0, 0x00000000); //0x54240008 + DCA_WRITE(DC_CMD_WIN_A_INCR_SYNCPT_CNTRL_0, 0x00000000); //0x54240024 + DCA_WRITE(DC_CMD_WIN_A_INCR_SYNCPT_ERROR_0, 0x00000000); //0x54240028 + DCA_WRITE(DC_CMD_WIN_B_INCR_SYNCPT_CNTRL_0, 0x00000000); //0x54240044 + DCA_WRITE(DC_CMD_WIN_B_INCR_SYNCPT_ERROR_0, 0x00000000); //0x54240048 + DCA_WRITE(DC_CMD_WIN_C_INCR_SYNCPT_CNTRL_0, 0x00000000); //0x54240064 + DCA_WRITE(DC_CMD_WIN_C_INCR_SYNCPT_ERROR_0, 0x00000000); //0x54240068 + DCA_WRITE(DC_CMD_CONT_SYNCPT_VSYNC_0, 0x00000000); //0x542400a0 + DCA_WRITE(DC_CMD_DISPLAY_COMMAND_OPTION0_0, 0x00000000); //0x542400c4 + DCA_WRITE(DC_CMD_DISPLAY_COMMAND_0, 0x00000000); //0x542400c8 + DCA_WRITE(DC_CMD_SIGNAL_RAISE_0, 0x00000000); //0x542400cc + DCA_WRITE(DC_CMD_DISPLAY_POWER_CONTROL_0, 0x00000000); //0x542400d8 + DCA_WRITE(DC_CMD_SIGNAL_RAISE1_0, 0x00000000); //0x542400f0 + DCA_WRITE(DC_CMD_SIGNAL_RAISE2_0, 0x00000000); //0x542400f4 + DCA_WRITE(DC_CMD_SIGNAL_RAISE3_0, 0x00000000); //0x542400f8 + DCA_WRITE(DC_CMD_STATE_CONTROL_0, 0x00000000); //0x54240104 + DCA_WRITE(DC_CMD_DISPLAY_WINDOW_HEADER_0, 0x00000000); //0x54240108 + DCA_WRITE(DC_CMD_REG_ACT_CONTROL_0, 0x00000000); //0x5424010c + DCA_WRITE(DC_CMD_WIN_T_STATE_CONTROL_0, 0x00000000); //0x54240110 + DCA_WRITE(DC_CMD_SECURE_CONTROL_0, 0x00000000); //0x54240114 + DCA_WRITE(DC_CMD_WIN_D_INCR_SYNCPT_CNTRL_0, 0x00000000); //0x54240134 + DCA_WRITE(DC_CMD_WIN_D_INCR_SYNCPT_ERROR_0, 0x00000000); //0x54240138 + printk(BIOS_SPEW, "initial DCA done\n"); +} + +void init_sor_regs(void) +{ + struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)TEGRA_CLK_RST_BASE; + + printk(BIOS_SPEW, "JZ: %s: entry\n", __func__); + +#define SWR_SOR0_RST (1 << 22) +#define CLK_ENB_SOR0 SWR_SOR0_RST +// REG(CLK_RST_CONTROLLER_RST_DEVICES_X_0, SWR_SOR0_RST, 1) +// REG(CLK_RST_CONTROLLER_RST_DEVICES_X_0, SWR_SOR0_RST, 0) +// REG(CLK_RST_CONTROLLER_CLK_OUT_ENB_X_0, CLK_ENB_SOR0, 1) +// REG(CLK_RST_CONTROLLER_CLK_SOURCE_SOR0_0, 0) //0x60006414 + setbits_le32(&clkrst->rst_devices_x, SWR_SOR0_RST); // Set Reset + clrbits_le32(&clkrst->rst_devices_x, SWR_SOR0_RST); // Clear Reset + setbits_le32(&clkrst->clk_out_enb_x, CLK_ENB_SOR0); // Set Enable + WRITEL(0x0, (void *)(0x60006000 + 0x414)); // CLK_SOURCE_SOR0 = PLLP + + //WRITEL(0xc000c000, (0x60006000 + 0x414)); // CLK_SOURCE_SOR0 = CLK_M + +#if 1 +#define SOR_WRITE(reg, val) \ + { \ + WRITEL(val, (void *)(TEGRA_ARM_SOR + (reg<<2))); \ + } + +#define SOR_READ(reg) READL( (void *)(TEGRA_ARM_SOR + (reg<<2))) + +#else // read back +#define SOR_WRITE(reg, val) \ + { \ + printk(BIOS_SPEW,"SOR_WRITE: addr %#x = %#x\n", + (unsigned int) (TEGRA_ARM_SOR + (reg<<2)), val); \ + WRITEL(val, (void *)(TEGRA_ARM_SOR + (reg<<2))); \ + printk(BIOS_SPEW,"= %#x\n", \ + (unsigned int)READL( (void *)(TEGRA_ARM_SOR + (reg<<2)))); \ + } +#endif +#define SOR_READ_M_WRITE(reg, mask, val) \ + { \ + u32 _reg_val; \ + _reg_val = READL( (void *)(TEGRA_ARM_SOR + (reg<<2))); \ + _reg_val &= ~mask; \ + _reg_val |= val; \ + WRITEL(_reg_val, (void *)(TEGRA_ARM_SOR + (reg<<2))); \ + } + + SOR_WRITE(SOR_NV_PDISP_SOR_SUPER_STATE0_0, 0x00000000); //0x54540004 + SOR_WRITE(SOR_NV_PDISP_SOR_SUPER_STATE1_0, 0x00000000); //0x54540008 + SOR_WRITE(SOR_NV_PDISP_SOR_STATE0_0, 0x00000000); //0x5454000c + SOR_WRITE(SOR_NV_PDISP_SOR_STATE1_0, 0x00000040); //0x54540010 + SOR_WRITE(SOR_NV_PDISP_HEAD_STATE0, 0x00000000); //0x54540014 + SOR_WRITE(SOR_NV_PDISP_HEAD_STATE0_1, 0x00000000); //0x54540018 + SOR_WRITE(SOR_NV_PDISP_HEAD_STATE1, 0x01011000); //0x5454001c + SOR_WRITE(SOR_NV_PDISP_HEAD_STATE1_1, 0x01011000); //0x54540020 + SOR_WRITE(SOR_NV_PDISP_HEAD_STATE2, 0x00000001); //0x54540024 + SOR_WRITE(SOR_NV_PDISP_HEAD_STATE2_1, 0x00000001); //0x54540028 + SOR_WRITE(SOR_NV_PDISP_HEAD_STATE3, 0x00010011); //0x5454002c + SOR_WRITE(SOR_NV_PDISP_HEAD_STATE3_1, 0x00010011); //0x54540030 + SOR_WRITE(SOR_NV_PDISP_HEAD_STATE4, 0x00110100); //0x54540034 + SOR_WRITE(SOR_NV_PDISP_HEAD_STATE4_1, 0x00110100); //0x54540038 + SOR_WRITE(SOR_NV_PDISP_HEAD_STATE5, 0x00000001); //0x5454003c + SOR_WRITE(SOR_NV_PDISP_HEAD_STATE5_1, 0x00000001); //0x54540040 + SOR_WRITE(SOR_NV_PDISP_SOR_CRC_CNTRL_0, 0x00000000); //0x54540044 + SOR_WRITE(SOR_NV_PDISP_SOR_DP_DEBUG_MVID_0, 0x00000000); //0x54540048 + SOR_WRITE(SOR_NV_PDISP_SOR_CLK_CNTRL_0, 0x00000018); //0x5454004c + SOR_WRITE(SOR_NV_PDISP_SOR_CAP_0, 0x00000000); //0x54540050 + SOR_WRITE(SOR_NV_PDISP_SOR_PWR_0, 0x00000000); //0x54540054 + SOR_WRITE(SOR_NV_PDISP_SOR_TEST_0, 0x00800000); //0x54540058 + SOR_WRITE(SOR_NV_PDISP_SOR_PLL0_0, 0x0f0003d5); //0x5454005c + SOR_WRITE(SOR_NV_PDISP_SOR_PLL1_0, 0x00001000); //0x54540060 + SOR_WRITE(SOR_NV_PDISP_SOR_PLL2_0, 0x01c00000); //0x54540064 + SOR_WRITE(SOR_NV_PDISP_SOR_PLL3_0, 0x38002220); //0x54540068 + SOR_WRITE(SOR_NV_PDISP_SOR_CSTM_0, 0x0001c800); //0x5454006c + SOR_WRITE(SOR_NV_PDISP_SOR_LVDS_0, 0x0001c800); //0x54540070 + SOR_WRITE(SOR_NV_PDISP_SOR_CRCA_0, 0x00000000); //0x54540074 + SOR_WRITE(SOR_NV_PDISP_SOR_CRCB_0, 0x00000000); //0x54540078 + SOR_WRITE(SOR_NV_PDISP_SOR_BLANK_0, 0x00000000); //0x5454007c + SOR_WRITE(SOR_NV_PDISP_SOR_SEQ_CTL_0, 0x00008800); //0x54540080 + SOR_WRITE(SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0, 0x00011000); //0x54540084 + SOR_WRITE(SOR_NV_PDISP_SOR_SEQ_INST0_0, 0x01008000); //0x54540088 + SOR_WRITE(SOR_NV_PDISP_SOR_SEQ_INST1_0, 0x01008000); //0x5454008c + SOR_WRITE(SOR_NV_PDISP_SOR_SEQ_INST2_0, 0x01008000); //0x54540090 + SOR_WRITE(SOR_NV_PDISP_SOR_SEQ_INST3_0, 0x01008000); //0x54540094 + SOR_WRITE(SOR_NV_PDISP_SOR_SEQ_INST4_0, 0x01008000); //0x54540098 + SOR_WRITE(SOR_NV_PDISP_SOR_SEQ_INST5_0, 0x01008000); //0x5454009c + SOR_WRITE(SOR_NV_PDISP_SOR_SEQ_INST6_0, 0x01008000); //0x545400a0 + SOR_WRITE(SOR_NV_PDISP_SOR_SEQ_INST7_0, 0x01008000); //0x545400a4 + SOR_WRITE(SOR_NV_PDISP_SOR_SEQ_INST8_0, 0x01008000); //0x545400a8 + SOR_WRITE(SOR_NV_PDISP_SOR_SEQ_INST9_0, 0x01008000); //0x545400ac + SOR_WRITE(SOR_NV_PDISP_SOR_SEQ_INSTA_0, 0x01008000); //0x545400b0 + SOR_WRITE(SOR_NV_PDISP_SOR_SEQ_INSTB_0, 0x01008000); //0x545400b4 + SOR_WRITE(SOR_NV_PDISP_SOR_SEQ_INSTC_0, 0x01008000); //0x545400b8 + SOR_WRITE(SOR_NV_PDISP_SOR_SEQ_INSTD_0, 0x01008000); //0x545400bc + SOR_WRITE(SOR_NV_PDISP_SOR_SEQ_INSTE_0, 0x01008000); //0x545400c0 + SOR_WRITE(SOR_NV_PDISP_SOR_SEQ_INSTF_0, 0x01008000); //0x545400c4 + SOR_WRITE(SOR_NV_PDISP_SOR_PWM_DIV_0, 0x00000000); //0x545400c8 + SOR_WRITE(SOR_NV_PDISP_SOR_PWM_CTL_0, 0x00000000); //0x545400cc + SOR_WRITE(SOR_NV_PDISP_SOR_VCRCA0_0, 0x00000000); //0x545400d0 + SOR_WRITE(SOR_NV_PDISP_SOR_VCRCA1_0, 0x00000000); //0x545400d4 + SOR_WRITE(SOR_NV_PDISP_SOR_VCRCB0_0, 0x00000000); //0x545400d8 + SOR_WRITE(SOR_NV_PDISP_SOR_VCRCB1_0, 0x00000000); //0x545400dc + SOR_WRITE(SOR_NV_PDISP_SOR_CCRCA0_0, 0x00000000); //0x545400e0 + SOR_WRITE(SOR_NV_PDISP_SOR_CCRCA1_0, 0x00000000); //0x545400e4 + SOR_WRITE(SOR_NV_PDISP_SOR_CCRCB0_0, 0x00000000); //0x545400e8 + SOR_WRITE(SOR_NV_PDISP_SOR_CCRCB1_0, 0x00000000); //0x545400ec + SOR_WRITE(SOR_NV_PDISP_SOR_EDATAA0_0, 0x00000000); //0x545400f0 + SOR_WRITE(SOR_NV_PDISP_SOR_EDATAA1_0, 0x00000000); //0x545400f4 + SOR_WRITE(SOR_NV_PDISP_SOR_EDATAB0_0, 0x00000000); //0x545400f8 + SOR_WRITE(SOR_NV_PDISP_SOR_EDATAB1_0, 0x00000000); //0x545400fc + SOR_WRITE(SOR_NV_PDISP_SOR_COUNTA0_0, 0x00000000); //0x54540100 + SOR_WRITE(SOR_NV_PDISP_SOR_COUNTA1_0, 0x00000000); //0x54540104 + SOR_WRITE(SOR_NV_PDISP_SOR_COUNTB0_0, 0x00000000); //0x54540108 + SOR_WRITE(SOR_NV_PDISP_SOR_COUNTB1_0, 0x00000000); //0x5454010c + SOR_WRITE(SOR_NV_PDISP_SOR_DEBUGA0_0, 0x00000000); //0x54540110 + SOR_WRITE(SOR_NV_PDISP_SOR_DEBUGA1_0, 0x00000000); //0x54540114 + SOR_WRITE(SOR_NV_PDISP_SOR_DEBUGB0_0, 0x00000000); //0x54540118 + SOR_WRITE(SOR_NV_PDISP_SOR_DEBUGB1_0, 0x00000000); //0x5454011c + SOR_WRITE(SOR_NV_PDISP_SOR_TRIG_0, 0x00000000); //0x54540120 + SOR_WRITE(SOR_NV_PDISP_SOR_MSCHECK_0, 0x80000000); //0x54540124 + SOR_WRITE(SOR_NV_PDISP_SOR_XBAR_CTRL_0, 0x8d111a23); //0x54540128 + SOR_WRITE(SOR_NV_PDISP_SOR_XBAR_POL_0, 0x00000000); //0x5454012c + SOR_WRITE(SOR_NV_PDISP_SOR_DP_LINKCTL0_0, 0x00000100); //0x54540130 + SOR_WRITE(SOR_NV_PDISP_SOR_DP_LINKCTL1_0, 0x00000100); //0x54540134 + SOR_WRITE(SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT0_0, 0x40404040); //0x54540138 + SOR_WRITE(SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT1_0, 0x80808080); //0x5454013c + SOR_WRITE(SOR_NV_PDISP_SOR_LANE4_DRIVE_CURRENT0_0, 0x00000040); //0x54540140 + SOR_WRITE(SOR_NV_PDISP_SOR_LANE4_DRIVE_CURRENT1_0, 0x00000080); //0x54540144 + SOR_WRITE(SOR_NV_PDISP_SOR_LANE_PREEMPHASIS0_0, 0x00000000); //0x54540148 + SOR_WRITE(SOR_NV_PDISP_SOR_LANE_PREEMPHASIS1_0, 0x00000000); //0x5454014c + SOR_WRITE(SOR_NV_PDISP_SOR_LANE4_PREEMPHASIS0_0, 0x00000000); //0x54540150 + SOR_WRITE(SOR_NV_PDISP_SOR_LANE4_PREEMPHASIS1_0, 0x00000000); //0x54540154 + SOR_WRITE(SOR_NV_PDISP_SOR_POSTCURSOR0_0, 0x00000000); //0x54540158 + SOR_WRITE(SOR_NV_PDISP_SOR_POSTCURSOR1_0, 0x00000000); //0x5454015c + SOR_WRITE(SOR_NV_PDISP_SOR_DP_CONFIG0_0, 0x94000000); //0x54540160 + SOR_WRITE(SOR_NV_PDISP_SOR_DP_CONFIG1_0, 0x94000000); //0x54540164 + SOR_WRITE(SOR_NV_PDISP_SOR_DP_MN0_0, 0x00008000); //0x54540168 + SOR_WRITE(SOR_NV_PDISP_SOR_DP_MN1_0, 0x00008000); //0x5454016c + SOR_WRITE(SOR_NV_PDISP_SOR_DP_PADCTL0_0, 0x00800000); //0x54540170 + SOR_WRITE(SOR_NV_PDISP_SOR_DP_PADCTL1_0, 0x00000000); //0x54540174 + SOR_WRITE(SOR_NV_PDISP_SOR_DP_DEBUG0_0, 0x00000000); //0x54540178 + SOR_WRITE(SOR_NV_PDISP_SOR_DP_DEBUG1_0, 0x00000000); //0x5454017c + SOR_WRITE(SOR_NV_PDISP_SOR_DP_SPARE0_0, 0x00000002); //0x54540180 + SOR_WRITE(SOR_NV_PDISP_SOR_DP_SPARE1_0, 0x00000000); //0x54540184 + SOR_WRITE(SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0, 0x001f0001); //0x54540188 + SOR_WRITE(SOR_NV_PDISP_SOR_DP_AUDIO_HBLANK_SYMBOLS_0, 0x00000000); //0x5454018c + SOR_WRITE(SOR_NV_PDISP_SOR_DP_AUDIO_VBLANK_SYMBOLS_0, 0x00000000); //0x54540190 + SOR_WRITE(SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_HEADER_0, 0x00000000); //0x54540194 + SOR_WRITE(SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK0_0,0x00000000); //0x54540198 + SOR_WRITE(SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK1_0,0x00000000); //0x5454019c + SOR_WRITE(SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK2_0,0x00000000); //0x545401a0 + SOR_WRITE(SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK3_0,0x00000000); //0x545401a4 + SOR_WRITE(SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK4_0,0x00000000); //0x545401a8 + SOR_WRITE(SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK5_0,0x00000000); //0x545401ac + SOR_WRITE(SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK6_0,0x00000000); //0x545401b0 + SOR_WRITE(SOR_NV_PDISP_SOR_DP_TPG_0, 0x50505050); //0x545401b4 + SOR_WRITE(SOR_NV_PDISP_SOR_DP_TPG_CONFIG_0, 0x00000000); //0x545401b8 + SOR_WRITE(SOR_NV_PDISP_SOR_DP_LQ_CSTM0_0, 0x00000000); //0x545401bc + SOR_WRITE(SOR_NV_PDISP_SOR_DP_LQ_CSTM1_0, 0x00000000); //0x545401c0 + SOR_WRITE(SOR_NV_PDISP_SOR_DP_LQ_CSTM2_0, 0x00000000); //0x545401c4 + printk(BIOS_SPEW, "initial SOR done\n"); +} + +void init_dpaux_regs(void) +{ + struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)TEGRA_CLK_RST_BASE; +// u32 val; + + printk(BIOS_SPEW, "JZ: %s: entry\n", __func__); + +#define SWR_DPAUX_RST (1 << 21) +#define CLK_ENB_DPAUX SWR_DPAUX_RST +// REG(CLK_RST_CONTROLLER_RST_DEVICES_X_0, SWR_DPAUX_RST, 1) +// REG(CLK_RST_CONTROLLER_RST_DEVICES_X_0, SWR_DPAUX_RST, 0) +// REG(CLK_RST_CONTROLLER_CLK_OUT_ENB_X_0, CLK_ENB_DPAUX, 1) + setbits_le32(&clkrst->rst_devices_x, SWR_DPAUX_RST); // Set Reset + clrbits_le32(&clkrst->rst_devices_x, SWR_DPAUX_RST); // Clear Reset + setbits_le32(&clkrst->clk_out_enb_x, CLK_ENB_DPAUX); // Set Enable + +#if 1 +#define DPAUX_WRITE(reg, val) \ + { \ + WRITEL(val, (void *)(TEGRA_ARM_DPAUX + (reg<<2))); \ + } +#define DPAUX_READ(reg) READL( (void *)(TEGRA_ARM_DPAUX + (reg<<2))) + +#else // read back +#define DPAUX_WRITE(reg, val) \ + { \ + printk(BIOS_SPEW,"DPAUX_WRITE: addr %#x = %#x\n", (unsigned int) + (TEGRA_ARM_DPAUX + (reg<<2)), val); \ + WRITEL(val, (void *)(TEGRA_ARM_DPAUX + (reg<<2))); \ + printk(BIOS_SPEW,"= %#x\n", \ + (unsigned int)READL( (void *)(TEGRA_ARM_DPAUX + (reg<<2)))); \ + } +#endif + + DPAUX_WRITE(DPAUX_INTR_EN_AUX, 0x00000000); //0x545c0004 + DPAUX_WRITE(DPAUX_INTR_AUX, 0x00000000); //0x545c0014 + DPAUX_WRITE(DPAUX_DP_AUXDATA_WRITE_W0, 0x00000000); //0x545c0024 + DPAUX_WRITE(DPAUX_DP_AUXDATA_WRITE_W1, 0x00000000); //0x545c0034 + DPAUX_WRITE(DPAUX_DP_AUXDATA_WRITE_W2, 0x00000000); //0x545c0044 + DPAUX_WRITE(DPAUX_DP_AUXDATA_WRITE_W3, 0x00000000); //0x545c0054 + DPAUX_WRITE(DPAUX_DP_AUXDATA_READ_W0, 0x00000000); //0x545c0064 + DPAUX_WRITE(DPAUX_DP_AUXDATA_READ_W1, 0x00000000); //0x545c0074 + DPAUX_WRITE(DPAUX_DP_AUXDATA_READ_W2, 0x00000000); //0x545c0084 + DPAUX_WRITE(DPAUX_DP_AUXDATA_READ_W3, 0x00000000); //0x545c0094 + DPAUX_WRITE(DPAUX_DP_AUXADDR, 0x00000000); //0x545c00a4 + DPAUX_WRITE(DPAUX_DP_AUXCTL, 0x00000000); //0x545c00b4 + DPAUX_WRITE(DPAUX_DP_AUXSTAT, 0x10000000); //0x545c00c4 + DPAUX_WRITE(DPAUX_DP_AUX_SINKSTATLO, 0x00000000); //0x545c00d4 + DPAUX_WRITE(DPAUX_DP_AUX_SINKSTATHI, 0x00000000); //0x545c00e4 + DPAUX_WRITE(DPAUX_HPD_CONFIG, 0x07d000fa); //0x545c00f4 + DPAUX_WRITE(DPAUX_HPD_IRQ_CONFIG, 0x000000fa); //0x545c0104 + DPAUX_WRITE(DPAUX_DP_AUX_CONFIG, 0x00000190); //0x545c0114 + DPAUX_WRITE(DPAUX_HYBRID_PADCTL, 0x00002462); //0x545c0124 + DPAUX_WRITE(DPAUX_HYBRID_SPARE, 0x00000000); //0x545c0134 + DPAUX_WRITE(DPAUX_SCRATCH_REG0_0, 0x00000000); //0x545c0144 + DPAUX_WRITE(DPAUX_SCRATCH_REG1_0, 0x00000000); //0x545c0154 + DPAUX_WRITE(DPAUX_SCRATCH_REG2_0, 0x00000000); //0x545c0164 + printk(BIOS_SPEW, "initial DPAUX done\n"); +} + +static int dp_poll_register(void *addr, u32 exp_val, u32 mask, u32 timeout_ms) +{ + + u32 reg_val = 0; + + printk(BIOS_SPEW, "JZ: %s: enter, addr %#x: exp_val: %#x, mask: %#x\n", + __func__, (unsigned int)addr, exp_val, mask); + do { + udelay(1); + reg_val = READL(addr); + } while (((reg_val & mask) != exp_val) && (--timeout_ms > 0)); + + if ((reg_val & mask) == exp_val) + return 0; /* success */ + printk(BIOS_SPEW, "poll_register %p: timeout\n", addr); + return timeout_ms; +} + +static void dp_io_set_dpd(u32 power_down) +{ + /* + * power_down: + * 0: out of Deep power down + * 1: into deep power down + */ + u32 val_reg; +#define DP_LVDS_SHIFT 25 +#define DP_LVDS (1 << DP_LVDS_SHIFT) + + val_reg = READL((void *)(0x7000e400 + 0x1c4)); /* APBDEV_PMC_IO_DPD2_STATUS_0 */ + printk(BIOS_SPEW, "JZ: %s: enter, into dpd %d, cur_status: %#x\n", + __func__, power_down, val_reg); + + if ((((val_reg & DP_LVDS) >> DP_LVDS_SHIFT) & 1) == power_down) { + printk(BIOS_SPEW, "PAD already POWER=%d\n", 1 - power_down); + return; + } + + /* APBDEV_PMC_IO_DPD2_REQ_0: E_DPD = power on */ + WRITEL((DP_LVDS | ((1 + power_down) << 30)), (void *)(0x7000e400 + 0x1c0)); + + dp_poll_register((void *)(0x7000e400 + 0x1C4), 0, DP_LVDS, 1000); + //APBDEV_PMC_IO_DPD2_STATUS_0 +} + +void dp_io_powerup(void) +{ + +//E_DPD = PMC.dpd2_status[25] +//PDBG = SOR_NV_PDISP_SOR_PLL2_0.AUX6(1) | SEQ.POWERDOWN_MACRO(1) & +//SOR_NV_PDISP_SOR_PLL2_0.AUX2(0) +//PDPLL = SOR_NV_PDISP_SOR_PLL0_0.PWR(1) | SEQ.PDPLL(0) & ~ SOR_NV_PDISP_SOR_PLL2_0.AUX1(0) +//VCOPD = SOR_NV_PDISP_SOR_PLL0_0.VCOPD(1) +//CAPPD = SOR_NV_PDISP_SOR_PLL2_0.AUX8(1) | SEQ.ASSERT_PLL_RESET(0) & +//~ SOR_NV_PDISP_SOR_PLL2_0.AUX1(0) +//PDPORT = SOR_NV_PDISP_SOR_PLL2_0.AUX7(1) | SEQ.PDPORT(1) & +//~ SOR_NV_PDISP_SOR_DP_LINKCTL0_0.ENABLE(0) +//PDCAL = SOR_NV_PDISP_SOR_DP_PADCTL0_0.PAD_CAL_PD(1) + +// struct clk_rst_ctlr *clkrst = +// (struct clk_rst_ctlr *)TEGRA_CLK_RST_BASE; + u32 reg_val; + + printk(BIOS_SPEW, "%s: entry\n", __func__); + +#if 0 + printk(BIOS_SPEW, "JZ: %s: %d: do nothing, ret\n", __func__, __LINE__); + return; +#endif + +#define SOR0_CLK_SEL0 (1 << 14) +#define SOR0_CLK_SEL1 (1 << 15) +// REG(CLK_RST_CONTROLLER_CLK_SOURCE_SOR0_0, SOR0_CLK_SEL1, 0); +// REG(CLK_RST_CONTROLLER_CLK_SOURCE_SOR0_0, SOR0_CLK_SEL0, 0);//sor safe clock + reg_val = READL((void *)(0x60006000 + 0x414)); + reg_val &= ~(SOR0_CLK_SEL0 | SOR0_CLK_SEL1); + WRITEL(reg_val, (void *)(0x60006000 + 0x414)); + +// clock(PLLDP, 270) + WRITEL(0, (void *)(0x60006000 + 0x594)); // plldp_misc + WRITEL(0x11400000, (void *)(0x60006000 + 0x598)); // plldp_ss_cfg + WRITEL(0x80305a01, (void *)(0x60006000 + 0x590));// plldp_base, 12 * 90 / 4 = 270 + WRITEL(0x11400000, (void *)(0x60006000 + 0x598)); // plldp_ss_cfg + WRITEL(0x40000000, (void *)(0x60006000 + 0x594)); // misc: enable lock + WRITEL(0xc0305a01, (void *)(0x60006000 + 0x590)); // base: enable + WRITEL(0xd8305a01, (void *)(0x60006000 + 0x590)); // base: check lock + WRITEL(0x58305a01, (void *)(0x60006000 + 0x590)); // base: disable bypass + WRITEL(0x11000000, (void *)(0x60006000 + 0x598)); // release clamp + udelay(10); // wait for plldp ready + + SOR_WRITE(SOR_NV_PDISP_SOR_CLK_CNTRL_0, (6 << 2) | 2);//select PLLDP, lowest speed(6x) + SOR_WRITE(SOR_NV_PDISP_SOR_DP_PADCTL0_0, 0x00800000); //set PDCAL + SOR_WRITE(SOR_NV_PDISP_SOR_PLL0_0, 0x050003D5); //set PWR,VCOPD + SOR_WRITE(SOR_NV_PDISP_SOR_PLL1_0, 0x00001100); //default + SOR_WRITE(SOR_NV_PDISP_SOR_PLL2_0, 0x01C20000); //set AUX1,6,7,8; clr AUX2 + SOR_WRITE(SOR_NV_PDISP_SOR_PLL3_0, 0x38002220); + + //REG(SOR_NV_PDISP_SOR_PLL3_0,PLLVDD_MODE, V1_8) + dp_io_set_dpd(0); + udelay(1); //Deassert E_DPD to enable core logic circuits, and wait for > 5us + + SOR_READ_M_WRITE(SOR_NV_PDISP_SOR_PLL2_0, + SOR_NV_PDISP_SOR_PLL2_0_AUX6_FIELD, + (0 << SOR_NV_PDISP_SOR_PLL2_0_AUX6_SHIFT)); + udelay(20); //Deassert PDBG to enable bandgap, and wait for > 20us. + + SOR_READ_M_WRITE(SOR_NV_PDISP_SOR_PLL0_0, + SOR_NV_PDISP_SOR_PLL0_0_PWR_FIELD, + (0 << SOR_NV_PDISP_SOR_PLL0_0_PWR_SHIFT)); + SOR_READ_M_WRITE(SOR_NV_PDISP_SOR_PLL0_0, + SOR_NV_PDISP_SOR_PLL0_0_VCOPD_FIELD, + (0 << SOR_NV_PDISP_SOR_PLL0_0_VCOPD_SHIFT)); + SOR_READ_M_WRITE(SOR_NV_PDISP_SOR_PLL2_0, + SOR_NV_PDISP_SOR_PLL2_0_AUX8_FIELD, + (0 << SOR_NV_PDISP_SOR_PLL2_0_AUX8_SHIFT)); + udelay(200); + //Enable the PLL/charge-pump/VCO, and wait for >200us for the PLL to + //lock. Input Clock must be running and stable before PDPLL + //de-assertion. + SOR_READ_M_WRITE(SOR_NV_PDISP_SOR_PLL2_0, + SOR_NV_PDISP_SOR_PLL2_0_AUX7_FIELD, + (0 << SOR_NV_PDISP_SOR_PLL2_0_AUX7_SHIFT)); + SOR_READ_M_WRITE(SOR_NV_PDISP_SOR_PLL2_0, + SOR_NV_PDISP_SOR_PLL2_0_AUX9_FIELD, + (1 << SOR_NV_PDISP_SOR_PLL2_0_AUX9_SHIFT)); + udelay(100); + + printk(BIOS_SPEW, "%s: exit\n", __func__); +} + +static int dpaux_check(u32 bytes, u32 data, u32 mask) +{ + u32 status = 0; + u8 buf[16]; + u32 temp; + + DPAUX_WRITE(DPAUX_DP_AUXDATA_READ_W0, 0); + status = dpaux_read(0x202, bytes, buf); + if (status != 0) + printk(BIOS_SPEW, "******AuxRead Error:%04x: status %08x\n", 0x202, + status); + else { + //temp = (buf[3] << 24) | (buf[2] << 16) | (buf[1] << 8) | buf[0] ; + //memcpy(&temp, buf, 4); + temp = DPAUX_READ(DPAUX_DP_AUXDATA_READ_W0); + if ((temp & mask) != (data & mask)) { + printk(BIOS_SPEW, "AuxCheck ERROR:(r_data) %08x & (mask) %08x != " + "(data) %08x & (mask) %08x\n", temp, mask, data, mask); + return -1; + } else { + printk(BIOS_SPEW, + "AuxCheck PASS:(bytes=%d,data=%08x,mask=%08x):0x%08x\n", + bytes, data, mask, temp); + return 0; + } + } + return -1; +} + +/* Modify the drive parameters for DP. There are up to four DP + * lanes. In principle, each lane can have different current, + * pre-emphasis, and postcur values. Nobody individualizes them; every + * single driver I've seen drives all the lanes to the same value + * (across x86 and ARM code). Actualy adjusting them individually and + * getting it all to work is probably a PhD thesis anyway. So, rather + * than the very complex code we see many places, the people who wrote + * this code realize: we can represent the 'volume' as a number in the + * range 0..3, with '0' as the base and '3' as being 'not to exceed'. + * + * So they abstract the values away, take care of the proper values, + * and set it all in one blow. Very nice. By far the easiest one of + * these functions we've seen. Sure, they could have constants, but + * nobody knows what PRE_EMPHASIS_3_5 and the other values actually + * *mean* anyway. Well, the hardware guys might. + */ +static void pattern_level(u32 current, u32 preemph, u32 postcur) +{ + printk(BIOS_SPEW, "set level:%d %d %d\n", current, preemph, postcur); + + //calibrating required + if (current == 0) + SOR_WRITE(SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT0_0, 0x20202020); + if (current == 1) + SOR_WRITE(SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT0_0, 0x24242424); + if (current == 2) + SOR_WRITE(SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT0_0, 0x30303030); + if (current == 3) + SOR_WRITE(SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT0_0, 0x40404040); + if (preemph == 0) + SOR_WRITE(SOR_NV_PDISP_SOR_LANE_PREEMPHASIS0_0, 0x00000000); + if (preemph == 1) + SOR_WRITE(SOR_NV_PDISP_SOR_LANE_PREEMPHASIS0_0, 0x08080808); + if (preemph == 2) + SOR_WRITE(SOR_NV_PDISP_SOR_LANE_PREEMPHASIS0_0, 0x10101010); + if (preemph == 3) + SOR_WRITE(SOR_NV_PDISP_SOR_LANE_PREEMPHASIS0_0, 0x18181818); + if (postcur == 0) + SOR_WRITE(SOR_NV_PDISP_SOR_POSTCURSOR0_0, 0x00000000); + if (postcur == 1) + SOR_WRITE(SOR_NV_PDISP_SOR_POSTCURSOR0_0, 0x04040404); + if (postcur == 2) + SOR_WRITE(SOR_NV_PDISP_SOR_POSTCURSOR0_0, 0x08080808); + if (postcur == 3) + SOR_WRITE(SOR_NV_PDISP_SOR_POSTCURSOR0_0, 0x10101010); +} + +static int dp_training(u32 level, u32 check, u32 speed) +{ + /* The levels are one of four choices. This code + * packs them into the three lowest nibl's. We may change this. + */ + u32 dc_lv = level & 0x0f; + u32 pe_lv = (level >> 4) & 0x0f; + u32 pc_lv = (level >> 8) & 0x0f; + u32 cnt = 0; + u32 cfg, cfg_d = 0; + u32 wcfg; +// u32 status = 0; + u8 buf[16]; + + while (cnt <= 5) { + pattern_level(dc_lv, pe_lv, pc_lv); + wcfg = (pe_lv << 3) | dc_lv; + if (dc_lv == 3) + wcfg = wcfg | 0x04; + if (pe_lv == 3) + wcfg = wcfg | 0x20; + wcfg = wcfg | (wcfg << 8) | (wcfg << 16) | (wcfg << 24); + dpaux_write(0x103, 4, wcfg); + udelay(50); //100us + DPAUX_WRITE(DPAUX_DP_AUXDATA_READ_W0, 0); + if (!dpaux_check(2, check, check)) + cnt = 100; + else { + dpaux_read(0x206, 1, buf); + cfg = DPAUX_READ(DPAUX_DP_AUXDATA_READ_W0); + cfg &= 0x00ff; + if (cfg == cfg_d) { + ++cnt; + if (cnt > 5) + printk(BIOS_SPEW, "link training FAILED\n"); + } else { + cnt = 0; + cfg_d = cfg; + dc_lv = cfg & 0x3; + pe_lv = (cfg >> 2) & 0x3; + if (speed == 20) { + dpaux_read(0x20C, 1, buf); + cfg = DPAUX_READ(DPAUX_DP_AUXDATA_READ_W0); + pc_lv = cfg & 0x3; + } else { + pc_lv = 0; + } + } + + } + debug_dpaux_print(0x200, 16); + } + + return ((pc_lv << 8) | (pe_lv << 4) | (dc_lv)); + +} + +void dp_link_training(u32 lanes, u32 speed); +void dp_link_training(u32 lanes, u32 speed) +{ + u32 lane_on; + u32 mask, level; + u32 reg_val; + + printk(BIOS_SPEW, "%s: entry, lanes: %d, speed: %d\n", __func__, lanes, + speed); + + printk(BIOS_SPEW, "\nLink training start\n"); + + switch (lanes) { + case 1: + lane_on = 0x04; + break; + case 2: + lane_on = 0x06; + break; + case 4: + lane_on = 0x0f; + break; + default: + printk(BIOS_SPEW, "dp: invalid lane count: %d\n", lanes); + return; + } + + SOR_WRITE(SOR_NV_PDISP_SOR_DP_PADCTL0_0, (0x008000000 | lane_on)); + SOR_READ_M_WRITE(SOR_NV_PDISP_SOR_DP_PADCTL0_0, + SOR_NV_PDISP_SOR_DP_PADCTL0_0_TX_PU_VALUE_FIELD, + (6 << SOR_NV_PDISP_SOR_DP_PADCTL0_0_TX_PU_VALUE_SHIFT)); + SOR_READ_M_WRITE(SOR_NV_PDISP_SOR_DP_PADCTL0_0, + SOR_NV_PDISP_SOR_DP_PADCTL0_0_TX_PU_FIELD, + (1 << SOR_NV_PDISP_SOR_DP_PADCTL0_0_TX_PU_SHIFT)); + SOR_WRITE(SOR_NV_PDISP_SOR_LVDS_0, 0); + + SOR_WRITE(SOR_NV_PDISP_SOR_CLK_CNTRL_0, ((speed << 2) | 2)); + udelay(100); + + //REG(CLK_RST_CONTROLLER_CLK_SOURCE_SOR0_0,SOR0_CLK_SEL0, 1) //sor clk=pad macro output + reg_val = readl((void *)(0x60006000 + 0x414)); + reg_val |= SOR0_CLK_SEL0; + + writel(reg_val, (void *)(0x60006000 + 0x414)); + + SOR_WRITE(SOR_NV_PDISP_SOR_DP_LINKCTL0_0, + (((0xF >> (4 - lanes)) << 16) | 1)); + + SOR_WRITE(SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0, 0x80100000); + printk(BIOS_SPEW, "Polling SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0.DONE\n"); + + dp_poll_register((void *)0x54540084, 0x00000000, 0x80000000, 1000); + + debug_dpaux_print(0x202, 4); + + printk(BIOS_SPEW, "set link rate and lane number: %dMHz, %d lanes\n", + (speed * 27), lanes); + +// printk(BIOS_SPEW,"JZ: dbg ret\n"); +// return; + +// %d = (%lanes<<8) | %speed + dpaux_write(0x100, 2, ((lanes << 8) | speed)); + printk(BIOS_SPEW, "precharge lane 10us\n"); + reg_val = SOR_READ(SOR_NV_PDISP_SOR_DP_PADCTL0_0); + SOR_WRITE(SOR_NV_PDISP_SOR_DP_PADCTL0_0, (0x000000f0 | reg_val)); + udelay(100); + SOR_WRITE(SOR_NV_PDISP_SOR_DP_PADCTL0_0, reg_val); + + printk(BIOS_SPEW, "link training cr start\n"); + SOR_WRITE(SOR_NV_PDISP_SOR_DP_TPG_0, 0x41414141); + dpaux_write(0x102, 1, 0x21); + + mask = 0x0000ffff >> ((4 - lanes) * 4); + level = 0; + level = dp_training(level, 0x1111 & mask, speed); + printk(BIOS_SPEW, "level:%x\n", level); + + debug_dpaux_print(0x210, 16); + + printk(BIOS_SPEW, "link training eq start\n"); + if (speed == 20) { + SOR_WRITE(SOR_NV_PDISP_SOR_DP_TPG_0, 0x43434343); + dpaux_write(0x102, 1, 0x23); + } else { + SOR_WRITE(SOR_NV_PDISP_SOR_DP_TPG_0, 0x42424242); + dpaux_write(0x102, 1, 0x22); + } + + level = dp_training(level, (0x7777 & mask) | 0x10000, speed); + printk(BIOS_SPEW, "level:%x\n", level); + + debug_dpaux_print(0x210, 16); + + SOR_WRITE(SOR_NV_PDISP_SOR_DP_TPG_0, 0x50505050); + dpaux_write(0x102, 1, 0); + dpaux_write(0x600, 1, 1); + + debug_dpaux_print(0x200, 16); + debug_dpaux_print(0x210, 16); + + printk(BIOS_SPEW, "Link training done\n\n"); + printk(BIOS_SPEW, "%s: exit\n", __func__); +} + +static u32 div_f(u32 a, u32 b, u32 one) +{ + u32 d = (((a - (a / b * b)) * one) + (b / 2)) / b; + return (d); +} + +u32 dp_setup_timing(u32 panel_id, u32 width, u32 height); +u32 dp_setup_timing(u32 panel_id, u32 width, u32 height) +{ + u32 reg_val; + u32 pclk_freq = 0; + + /////////////////////////////////////////// + // set up clocks, using PLLD2 + // format: pclk , PLL , panel + //2560x1440: 241.5 , 483/2, dp VESA.red. + //1920x1080: 148.5 , 594/4, dp CEA + //1600x1200: 161.0 , 483/3, dp VESA + //1280x 720: 74.25 , 594/8, dp CEA + // 1024x768: 63.5 , 508/8, dp VESA + // 800x600: 38.25 , 459/12, dp VESA + // 720x480: 27.00 , 594/22, dp CEA + // 640x480: 23.75 , 475/20, dp VESA + + u32 PLL_FREQ = 570; + u32 PLL_DIV = 2; + u32 SYNC_WIDTH = (10 << 16) | 32; + u32 BACK_PORCH = (36 << 16) | 80; + u32 FRONT_PORCH = (3 << 16) | 48; + u32 HSYNC_NEG = 1; + u32 VSYNC_NEG = 1; + + u32 SHIFT_CLK_DIVIDER = PLL_DIV * 2 - 2; + u32 DISP_ACTIVE = (height << 16) | width; + u32 DISP_TOTAL = DISP_ACTIVE + SYNC_WIDTH + BACK_PORCH + FRONT_PORCH; + u32 SYNC_END = SYNC_WIDTH - 0x10001; + u32 BLANK_END = SYNC_END + BACK_PORCH; + u32 BLANK_START = BLANK_END + DISP_ACTIVE; + u32 TOTAL_PIXELS = (DISP_TOTAL & 0xffff) * (DISP_TOTAL >> 16); + + u32 PLL_FREQ_I, PLL_FREQ_F; + u32 PCLK_FREQ_I, PCLK_FREQ_F; + u32 FRATE_I, FRATE_F; + + printk(BIOS_SPEW, "%s: entry\n", __func__); + + if (panel_id != 5) { + printk(BIOS_SPEW, "%s: Unsupported panel_id: %d, format=%dx%d\n", + __func__, panel_id, width, height); + return pclk_freq; + } + +// clock(plld2, %PLL_FREQ) // PLL_FREQ = 570 + writel(0, (void *)(0x60006000 + 0x4bc)); // plld2_misc + writel(0x13400000, (void *)(0x60006000 + 0x570)); // plld2_ss_cfg + writel(0x8008010c, (void *)(0x60006000 + 0x4b8)); // plld2_base + writel(0x80105F01, (void *)(0x60006000 + 0x4b8));// plld2_base: 12 * 95 / 2 = 570 + writel(0x40000000, (void *)(0x60006000 + 0x4bc)); // misc: enable lock + writel(0x80105f01, (void *)(0x60006000 + 0x4b8)); // base: enable + writel(0xc0105f01, (void *)(0x60006000 + 0x4b8)); // base: check lock + writel(0x58105f01, (void *)(0x60006000 + 0x4b8)); // base: disable bypass + writel(0x13800000, (void *)(0x60006000 + 0x570)); // plld2_ss_cfg + udelay(10); // wait for plld2 ready + +// REG(CLK_RST_CONTROLLER_CLK_SOURCE_DISP1_0, DISP1_CLK_SRC, PLLD2_OUT0) +#define DISP1_CLK_SRC (0x7 << 29) +#define PLLD2_OUT0 (0x5 << 29) + reg_val = readl((void *)(0x60006000 + 0x138)); + reg_val &= ~DISP1_CLK_SRC; + reg_val |= PLLD2_OUT0; + writel(reg_val, (void *)(0x60006000 + 0x138)); + udelay(10); + + PLL_FREQ = PLL_FREQ * 1000000; + pclk_freq = PLL_FREQ / PLL_DIV; + PLL_FREQ_I = PLL_FREQ / 1000000; + PLL_FREQ_F = div_f(PLL_FREQ, 1000000, 100); + PCLK_FREQ_I = PLL_FREQ / (PLL_DIV * 1000000); + PCLK_FREQ_F = div_f(PLL_FREQ, PLL_DIV * 1000000, 100); + FRATE_I = PLL_FREQ / (PLL_DIV * TOTAL_PIXELS); + FRATE_F = div_f(PLL_FREQ, (PLL_DIV * TOTAL_PIXELS), 100); + //bug 1021453 + BACK_PORCH = BACK_PORCH - 0x10000; + FRONT_PORCH = FRONT_PORCH + 0x10000; + + printk(BIOS_SPEW, "ACTIVE: %dx%d\n", (DISP_ACTIVE & 0xFFFF), + (DISP_ACTIVE >> 16)); + printk(BIOS_SPEW, "TOTAL: %dx%d\n", (DISP_TOTAL & 0xffff), + (DISP_TOTAL >> 16)); + printk(BIOS_SPEW, "PLL Freq: %d.%d MHz\n", PLL_FREQ_I, PLL_FREQ_F); + printk(BIOS_SPEW, "Pclk Freq: %d.%d MHz\n", PCLK_FREQ_I, + PCLK_FREQ_F); + printk(BIOS_SPEW, "Frame Rate: %d.%d Hz\n", FRATE_I, FRATE_F); + printk(BIOS_SPEW, "\n"); + + DCA_WRITE(DC_CMD_STATE_ACCESS_0, 0x00000004); + DCA_WRITE(DC_DISP_DISP_CLOCK_CONTROL_0, SHIFT_CLK_DIVIDER); + //Raster Timing + DCA_WRITE(DC_DISP_DISP_TIMING_OPTIONS_0, 0x00000001); + DCA_WRITE(DC_DISP_REF_TO_SYNC_0, 0x00010001); + DCA_WRITE(DC_DISP_SYNC_WIDTH_0, SYNC_WIDTH); + DCA_WRITE(DC_DISP_BACK_PORCH_0, BACK_PORCH); + DCA_WRITE(DC_DISP_DISP_ACTIVE_0, DISP_ACTIVE); + DCA_WRITE(DC_DISP_FRONT_PORCH_0, FRONT_PORCH); + + printk(BIOS_SPEW, + "JZ: sync_width: %d, back_porch: %d, disp_active: %d, front_porch: %d\n", + SYNC_WIDTH, BACK_PORCH, DISP_ACTIVE, FRONT_PORCH); + //REG(DC_DISP_DISP_WIN_OPTIONS_0, SOR_ENABLE , 1) + DCA_READ_M_WRITE(DC_DISP_DISP_WIN_OPTIONS_0, + DC_DISP_DISP_WIN_OPTIONS_0_SOR_ENABLE_FIELD, + (1 << DC_DISP_DISP_WIN_OPTIONS_0_SOR_ENABLE_SHIFT)); + + SOR_WRITE(SOR_NV_PDISP_HEAD_STATE1_0, DISP_TOTAL); + SOR_WRITE(SOR_NV_PDISP_HEAD_STATE2_0, SYNC_END); + SOR_WRITE(SOR_NV_PDISP_HEAD_STATE3_0, BLANK_END); + SOR_WRITE(SOR_NV_PDISP_HEAD_STATE4_0, BLANK_START); + + SOR_READ_M_WRITE(SOR_NV_PDISP_SOR_STATE1_0, + SOR_NV_PDISP_SOR_STATE1_0_ASY_HSYNCPOL_FIELD, + (HSYNC_NEG << + SOR_NV_PDISP_SOR_STATE1_0_ASY_HSYNCPOL_SHIFT)); + + SOR_READ_M_WRITE(SOR_NV_PDISP_SOR_STATE1_0, + SOR_NV_PDISP_SOR_STATE1_0_ASY_VSYNCPOL_FIELD, + (VSYNC_NEG << + SOR_NV_PDISP_SOR_STATE1_0_ASY_VSYNCPOL_SHIFT)); + + SOR_READ_M_WRITE(SOR_NV_PDISP_SOR_STATE1_0, + SOR_NV_PDISP_SOR_STATE1_0_ASY_PROTOCOL_FIELD, + (SOR_NV_PDISP_SOR_STATE1_0_ASY_PROTOCOL_DP_A << + SOR_NV_PDISP_SOR_STATE1_0_ASY_PROTOCOL_SHIFT)); + + SOR_READ_M_WRITE(SOR_NV_PDISP_SOR_STATE1_0, + SOR_NV_PDISP_SOR_STATE1_0_ASY_CRCMODE_FIELD, + (SOR_NV_PDISP_SOR_STATE1_0_ASY_CRCMODE_COMPLETE_RASTER << + SOR_NV_PDISP_SOR_STATE1_0_ASY_CRCMODE_SHIFT)); + + SOR_READ_M_WRITE(SOR_NV_PDISP_SOR_STATE1_0, + SOR_NV_PDISP_SOR_STATE1_0_ASY_SUBOWNER_FIELD, + (SOR_NV_PDISP_SOR_STATE1_0_ASY_SUBOWNER_NONE << + SOR_NV_PDISP_SOR_STATE1_0_ASY_SUBOWNER_SHIFT)); + + SOR_READ_M_WRITE(SOR_NV_PDISP_SOR_STATE1_0, + SOR_NV_PDISP_SOR_STATE1_0_ASY_OWNER_FIELD, + (SOR_NV_PDISP_SOR_STATE1_0_ASY_OWNER_HEAD0 << + SOR_NV_PDISP_SOR_STATE1_0_ASY_OWNER_SHIFT)); + printk(BIOS_SPEW, "%s: exit\n", __func__); + return pclk_freq; +} + +static u32 calc_config(u32 ts, u32 a, u32 b, u32 bpp) +{ + u32 act_cnt = (ts * a) / b; + u32 diff = (ts * a) - (act_cnt * b); + u32 act_pol; + u32 act_frac; + u32 err; + u32 water_mark; + printk(BIOS_SPEW, "calc_config ts %d a %d b %d bpp %d\n", ts, a, b, bpp); + if (diff != 0) { + if (diff > (b / 2)) { + diff = b - diff; + act_pol = 1; + act_frac = (b + diff - 1) / diff; + err = diff * act_frac - b; + } else { + act_pol = 0; + act_frac = b / diff; + err = b - (diff * act_frac); + } + if (act_frac > 15) { + act_pol = 1 - act_pol; + act_frac = 1; + err = diff; + } + } else { + act_pol = 1; + act_frac = 1; + err = 0; + } + + if (bpp) { + water_mark = (a * (b - a) * ts / (b * b)) + (2 * bpp / 8); + if (water_mark > 30) + water_mark = 30; + + SOR_WRITE(SOR_NV_PDISP_SOR_DP_CONFIG0_0, 0x84000000); + SOR_READ_M_WRITE(SOR_NV_PDISP_SOR_DP_CONFIG0_0, + SOR_NV_PDISP_SOR_DP_CONFIG0_0_ACTIVESYM_POLARITY_FIELD, + (act_pol << + SOR_NV_PDISP_SOR_DP_CONFIG0_0_ACTIVESYM_POLARITY_SHIFT)); + SOR_READ_M_WRITE(SOR_NV_PDISP_SOR_DP_CONFIG0_0, + SOR_NV_PDISP_SOR_DP_CONFIG0_0_ACTIVESYM_FRAC_FIELD, + (act_frac << + SOR_NV_PDISP_SOR_DP_CONFIG0_0_ACTIVESYM_FRAC_SHIFT)); + SOR_READ_M_WRITE(SOR_NV_PDISP_SOR_DP_CONFIG0_0, + SOR_NV_PDISP_SOR_DP_CONFIG0_0_ACTIVESYM_COUNT_FIELD, + (act_cnt << + SOR_NV_PDISP_SOR_DP_CONFIG0_0_ACTIVESYM_COUNT_SHIFT)); + SOR_READ_M_WRITE(SOR_NV_PDISP_SOR_DP_CONFIG0_0, + SOR_NV_PDISP_SOR_DP_CONFIG0_0_WATERMARK_FIELD, + (water_mark << + SOR_NV_PDISP_SOR_DP_CONFIG0_0_WATERMARK_SHIFT)); + + printk(BIOS_SPEW, + "SOR_DP_CONFIG0:TU,CNT,POL,FRAC,WMK,ERR=%d,%d,%d,%d,%d,%d/%d\n", + ts, act_cnt, act_pol, act_frac, water_mark, err, b); + } + return (err); +} + +static u32 dp_buf_config(u32 pclkfreq, u32 linkfreq, u32 lanes, u32 bpp) +{ + //to avoid 32bit overflow + u32 tusize = 0; + u32 pf = pclkfreq; + u32 lf = linkfreq; + u32 i; + u32 a, b; + u32 min_err = 1000000000; + u32 ts = 64; + u32 c_err; + printk(BIOS_SPEW, "dp buf config pclkfreq %d linkfreq %d lanes %d bpp %d\n", + pclkfreq, linkfreq, lanes, bpp); + for (i = 2; i <= 7; ++i) { + while (((pf / i * i) == pf) && ((lf / i * i) == lf)) { + pf = pf / i; + lf = lf / i; + } + } + + a = pf * bpp / 8; + b = lf * lanes; + printk(BIOS_SPEW, "ratio:%d/%d\n", a, b); + if (a > (b * 98 / 100)) + printk(BIOS_SPEW, "Error:link speed not enough\n"); + + //search best tusize + //min_err = 1000000000; + //ts = 64; + while (ts >= 32) { + c_err = calc_config(ts, a, b, 0); + if (c_err < min_err) { + if (c_err == 0) { + tusize = ts; + ts = 1; + } else { + min_err = c_err; + tusize = ts; + } + } + --ts; + } + + SOR_READ_M_WRITE(SOR_NV_PDISP_SOR_DP_LINKCTL0_0, + SOR_NV_PDISP_SOR_DP_LINKCTL0_0_TUSIZE_FIELD, + (tusize << SOR_NV_PDISP_SOR_DP_LINKCTL0_0_TUSIZE_SHIFT)); + calc_config(tusize, a, b, bpp); + + return (tusize); +} + +void dp_misc_setting(u32 panel_bpp, u32 width, u32 height, u32 winb_addr, + u32 lane_count, u32 enhanced_framing, u32 panel_edp, + u32 pclkfreq, u32 linkfreq); + +void dp_misc_setting(u32 panel_bpp, u32 width, u32 height, u32 winb_addr, + u32 lane_count, u32 enhanced_framing, u32 panel_edp, + u32 pclkfreq, u32 linkfreq) +{ + u32 tusize; + u32 linkctl; + + printk(BIOS_SPEW, "%s: entry, winb: 0x%08x ", __func__, winb_addr); + printk(BIOS_SPEW, " panel_bpp %d\n", panel_bpp); + + if (panel_bpp == 18) { + //0x54540010 + SOR_READ_M_WRITE(SOR_NV_PDISP_SOR_STATE1_0, + SOR_NV_PDISP_SOR_STATE1_0_ASY_PIXELDEPTH_FIELD, + (SOR_NV_PDISP_SOR_STATE1_0_ASY_PIXELDEPTH_BPP_18_444 << + SOR_NV_PDISP_SOR_STATE1_0_ASY_PIXELDEPTH_SHIFT)); + } + if (panel_bpp == 24) { + SOR_READ_M_WRITE(SOR_NV_PDISP_SOR_STATE1_0, + SOR_NV_PDISP_SOR_STATE1_0_ASY_PIXELDEPTH_FIELD, + (SOR_NV_PDISP_SOR_STATE1_0_ASY_PIXELDEPTH_BPP_24_444 << + SOR_NV_PDISP_SOR_STATE1_0_ASY_PIXELDEPTH_SHIFT)); + } + +#define SRC_BPP 16 +#define COLORDEPTH 0x6 + +#define BLUE 0xFF0000 +#define GREEN 0x00FF00 +#define RED 0x0000FF +#define YELLOW 0x00FFFF +#define BLACK 0x000000 +#define WHITE 0xFFFFFF +#define GREY 0x55aa00 + + DCA_WRITE(DC_B_WIN_BD_SIZE_0, ((height << 16) | width)); + DCA_WRITE(DC_B_WIN_BD_PRESCALED_SIZE_0, + ((height << 16) | (width * SRC_BPP / 8))); + DCA_WRITE(DC_B_WIN_BD_LINE_STRIDE_0, + ((width * SRC_BPP / 8 + 31) / 32 * 32)); + DCA_WRITE(DC_B_WIN_BD_COLOR_DEPTH_0, COLORDEPTH); + DCA_WRITE(DC_B_WINBUF_BD_START_ADDR_0, winb_addr); + DCA_WRITE(DC_B_WIN_BD_DDA_INCREMENT_0, 0x10001000); + + SOR_WRITE(SOR_NV_PDISP_SOR_CRC_CNTRL_0, 0x00000001); + DCA_WRITE(DC_COM_CRC_CONTROL_0, 0x00000009); //CRC_ALWAYS+CRC_ENABLE + DCA_WRITE(DC_COM_PIN_OUTPUT_ENABLE2_0, 0x00000000); + DCA_WRITE(DC_COM_PIN_OUTPUT_ENABLE3_0, 0x00000000); + DCA_WRITE(DC_DISP_DISP_SIGNAL_OPTIONS0_0, 0x00000000); + // DCA_WRITE (DC_DISP_BLEND_BACKGROUND_COLOR_0 ,WHITE ); + DCA_WRITE(DC_DISP_BLEND_BACKGROUND_COLOR_0, YELLOW); + DCA_WRITE(DC_CMD_DISPLAY_COMMAND_0, 0x00000020); + SOR_WRITE(SOR_NV_PDISP_SOR_DP_AUDIO_VBLANK_SYMBOLS_0, 0x00000e48); + + + dpaux_write(0x101, 1, (enhanced_framing << 7) | lane_count); + if (panel_edp) + dpaux_write(0x10A, 1, 1); + + tusize = + dp_buf_config(pclkfreq, (linkfreq * 1000000), lane_count, panel_bpp); + + printk(BIOS_SPEW, "JZ, after dp_buf_config, tusize: 0x%08x\n", tusize); + + linkctl = + ((0xF >> (4 - lane_count)) << 16) | (enhanced_framing << 14) | (tusize + << 2) | + 1; + + SOR_WRITE(SOR_NV_PDISP_SOR_DP_LINKCTL0_0, linkctl); + SOR_WRITE(SOR_NV_PDISP_SOR_DP_SPARE0_0, ((panel_edp << 1) | 0x05)); + + SOR_WRITE(SOR_NV_PDISP_SOR_PWR_0, 0x80000001); + printk(BIOS_SPEW, "Polling SOR_NV_PDISP_SOR_PWR_0.DONE\n"); + dp_poll_register((void *)0x54540054, 0x00000000, 0x80000000, 1000); + //SOR_NV_PDISP_SOR_PWR_0 + //sor_update + SOR_WRITE(SOR_NV_PDISP_SOR_STATE0_0, 0x00000000); + SOR_WRITE(SOR_NV_PDISP_SOR_SUPER_STATE1_0, 0x00000006); + //sor_super_update + SOR_WRITE(SOR_NV_PDISP_SOR_SUPER_STATE0_0, 0x00000000); + SOR_WRITE(SOR_NV_PDISP_SOR_SUPER_STATE1_0, 0x0000000e); + //sor_super_update + SOR_WRITE(SOR_NV_PDISP_SOR_SUPER_STATE0_0, 0x00000000); + printk(BIOS_SPEW, "Polling SOR_NV_PDISP_SOR_TEST_0.ATTACHED\n"); + dp_poll_register((void *)0x54540058, 0x00000400, 0x00000400, 1000); + //SOR_NV_PDISP_SOR_TEST_0 + + DCA_WRITE(DC_CMD_STATE_CONTROL_0, 0x00009f00); + DCA_WRITE(DC_CMD_STATE_CONTROL_0, 0x0000009f); + DCA_WRITE(DC_CMD_DISPLAY_POWER_CONTROL_0, 0x00050155); + + printk(BIOS_SPEW, "Polling SOR_NV_PDISP_SOR_TEST_0.AWAKE\n"); + dp_poll_register((void *)0x54540058, 0x00000200, 0x00000300, 1000); + //SOR_NV_PDISP_SOR_TEST_0 + + // DCA_WRITE (DC_CMD_STATE_ACCESS_0 ,0); + DCA_WRITE(DC_CMD_STATE_ACCESS_0, 4); + DCA_WRITE(DC_CMD_STATE_CONTROL_0, 0x0000ffff); + /* enable win_b */ + + DCA_READ_M_WRITE(DC_B_WIN_BD_WIN_OPTIONS_0, + DC_B_WIN_BD_WIN_OPTIONS_0_BD_WIN_ENABLE_FIELD, + (DC_B_WIN_BD_WIN_OPTIONS_0_BD_WIN_ENABLE_ENABLE << + DC_B_WIN_BD_WIN_OPTIONS_0_BD_WIN_ENABLE_SHIFT)); + + + printk(BIOS_SPEW, "JZ: %s: f_ret @ line %d\n", __func__, __LINE__); +} + diff --git a/src/soc/nvidia/tegra124/dma.c b/src/soc/nvidia/tegra124/dma.c index 964bb7b..0ab0ad0 100644 --- a/src/soc/nvidia/tegra124/dma.c +++ b/src/soc/nvidia/tegra124/dma.c @@ -26,95 +26,8 @@ #include "dma.h" -/* - * Note: Many APB DMA controller registers are laid out such that each - * bit controls or represents the status for the corresponding channel. - * So we will not bother to list each individual bit in this case. - */ -#define APBDMA_COMMAND_GEN (1 << 31) - -#define APBDMA_CNTRL_REG_COUNT_VALUE_MASK 0xffff -#define APBDMA_CNTRL_REG_COUNT_VALUE_SHIFT 0 - -struct apb_dma { - u32 command; /* 0x00 */ - u32 status; /* 0x04 */ - u32 rsvd1[2]; - u32 cntrl_reg; /* 0x10 */ - u32 irq_sta_cpu; /* 0x14 */ - u32 irq_sta_cop; /* 0x18 */ - u32 irq_mask; /* 0x1c */ - u32 irq_mask_set; /* 0x20 */ - u32 irq_mask_clr; /* 0x24 */ - u32 trig_reg; /* 0x28 */ - u32 channel_trig_reg; /* 0x2c */ - u32 dma_status; /* 0x30 */ - u32 channel_en_reg; /* 0x34 */ - u32 security_reg; /* 0x38 */ - u32 channel_swid; /* 0x3c */ - u32 rsvd[1]; - u32 chan_wt_reg0; /* 0x44 */ - u32 chan_wt_reg1; /* 0x48 */ - u32 chan_wt_reg2; /* 0x4c */ - u32 chan_wr_reg3; /* 0x50 */ - u32 channel_swid1; /* 0x54 */ -} __attribute__((packed)); struct apb_dma * const apb_dma = (struct apb_dma *)TEGRA_APB_DMA_BASE; -/* - * Naming in the doc included a superfluous _CHANNEL_n_ for - * each entry and was left out for the sake of conciseness. - */ -#define APBDMACHAN_CSR_ENB (1 << 31) -#define APBDMACHAN_CSR_IE_EOC (1 << 30) -#define APBDMACHAN_CSR_HOLD (1 << 29) -#define APBDMACHAN_CSR_DIR (1 << 28) -#define APBDMACHAN_CSR_ONCE (1 << 27) -#define APBDMACHAN_CSR_FLOW (1 << 21) -#define APBDMACHAN_CSR_REQ_SEL_MASK 0x1f -#define APBDMACHAN_CSR_REQ_SEL_SHIFT 16 - -#define APBDMACHAN_STA_BSY (1 << 31) -#define APBDMACHAN_STA_ISE_EOC (1 << 30) -#define APBDMACHAN_STA_HALT (1 << 29) -#define APBDMACHAN_STA_PING_PONG_STA (1 << 28) -#define APBDMACHAN_STA_DMA_ACTIVITY (1 << 27) -#define APBDMACHAN_STA_CHANNEL_PAUSE (1 << 26) - -#define APBDMACHAN_CSRE_CHANNEL_PAUSE (1 << 31) -#define APBDMACHAN_CSRE_TRIG_SEL_MASK 0x3f -#define APBDMACHAN_CSRE_TRIG_SEL_SHIFT 14 - -#define APBDMACHAN_AHB_PTR_MASK (0x3fffffff) -#define APBDMACHAN_AHB_PTR_SHIFT 2 - -#define APBDMACHAN_AHB_SEQ_INTR_ENB (1 << 31) -#define APBDMACHAN_AHB_SEQ_AHB_BUS_WIDTH_MASK 0x7 -#define APBDMACHAN_AHB_SEQ_AHB_BUS_WIDTH_SHIFT 28 -#define APBDMACHAN_AHB_SEQ_AHB_DATA_SWAP (1 << 27) -#define APBDMACHAN_AHB_SEQ_AHB_BURST_MASK 0x7 -#define APBDMACHAN_AHB_SEQ_AHB_BURST_SHIFT 24 -#define APBDMACHAN_AHB_SEQ_DBL_BUF (1 << 19) -#define APBDMACHAN_AHB_SEQ_WRAP_MASK 0x7 -#define APBDMACHAN_AHB_SEQ_WRAP_SHIFT 16 - -#define APBDMACHAN_AHB_SEQ_AHB_BUS_WIDTH_MASK 0x7 -#define APBDMACHAN_AHB_SEQ_AHB_BUS_WIDTH_SHIFT 28 - -#define APBDMACHAN_APB_PTR_MASK 0x3fffffff -#define APBDMACHAN_APB_PTR_SHIFT 2 - -#define APBDMACHAN_APB_SEQ_APB_BUS_WIDTH_MASK 0x7 -#define APBDMACHAN_APB_SEQ_APB_BUS_WIDTH_SHIFT 28 -#define APBDMACHAN_APB_SEQ_APB_DATA_SWAP (1 << 27) -#define APBDMACHAN_APB_SEQ_APB_ADDR_WRAP_MASK 0x7 -#define APBDMACHAN_APB_SEQ_APB_ADDR_WRAP_SHIFT 16 - -#define APBDMACHAN_WORD_TRANSFER_ - -#define APBDMACHAN_WORD_TRANSFER_MASK 0x0fffffff -#define APBDMACHAN_WORD_TRANSFER_SHIFT 2 - #define APB_DMA_OFFSET(n) \ (struct apb_dma_channel_regs *)(TEGRA_APB_DMA_BASE + n) struct apb_dma_channel apb_dma_channels[] = { diff --git a/src/soc/nvidia/tegra124/dma.h b/src/soc/nvidia/tegra124/dma.h index d7e9090..288f674 100644 --- a/src/soc/nvidia/tegra124/dma.h +++ b/src/soc/nvidia/tegra124/dma.h @@ -28,6 +28,138 @@ */ #define TEGRA_DMA_ALIGN_BYTES 4 +/* + * Note: Many APB DMA controller registers are laid out such that each + * bit controls or represents the status for the corresponding channel. + * So we will not bother to list each individual bit in this case. + */ +#define APBDMA_COMMAND_GEN (1 << 31) + +#define APBDMA_CNTRL_REG_COUNT_VALUE_MASK 0xffff +#define APBDMA_CNTRL_REG_COUNT_VALUE_SHIFT 0 + +/* + * Note: Many APB DMA controller registers are laid out such that each + * bit controls or represents the status for the corresponding channel. + * So we will not bother to list each individual bit in this case. + */ +#define APBDMA_COMMAND_GEN (1 << 31) + +#define APBDMA_CNTRL_REG_COUNT_VALUE_MASK 0xffff +#define APBDMA_CNTRL_REG_COUNT_VALUE_SHIFT 0 +struct apb_dma { + u32 command; /* 0x00 */ + u32 status; /* 0x04 */ + u32 rsvd1[2]; + u32 cntrl_reg; /* 0x10 */ + u32 irq_sta_cpu; /* 0x14 */ + u32 irq_sta_cop; /* 0x18 */ + u32 irq_mask; /* 0x1c */ + u32 irq_mask_set; /* 0x20 */ + u32 irq_mask_clr; /* 0x24 */ + u32 trig_reg; /* 0x28 */ + u32 channel_trig_reg; /* 0x2c */ + u32 dma_status; /* 0x30 */ + u32 channel_en_reg; /* 0x34 */ + u32 security_reg; /* 0x38 */ + u32 channel_swid; /* 0x3c */ + u32 rsvd[1]; + u32 chan_wt_reg0; /* 0x44 */ + u32 chan_wt_reg1; /* 0x48 */ + u32 chan_wt_reg2; /* 0x4c */ + u32 chan_wr_reg3; /* 0x50 */ + u32 channel_swid1; /* 0x54 */ +} __attribute__((packed)); + +/* + * Naming in the doc included a superfluous _CHANNEL_n_ for + * each entry and was left out for the sake of conciseness. + */ +#define APBDMACHAN_CSR_ENB (1 << 31) +#define APBDMACHAN_CSR_IE_EOC (1 << 30) +#define APBDMACHAN_CSR_HOLD (1 << 29) +#define APBDMACHAN_CSR_DIR (1 << 28) +#define APBDMACHAN_CSR_ONCE (1 << 27) +#define APBDMACHAN_CSR_FLOW (1 << 21) +#define APBDMACHAN_CSR_REQ_SEL_MASK 0x1f +#define APBDMACHAN_CSR_REQ_SEL_SHIFT 16 + +enum apbdmachan_req_sel { + APBDMA_SLAVE_CNTR_REQ = 0, + APBDMA_SLAVE_APBIF_CH0 = 1, + APBDMA_SLAVE_APBIF_CH1 = 2, + APBDMA_SLAVE_APBIF_CH2 = 3, + APBDMA_SLAVE_APBIF_CH3 = 4, + APBDMA_SLAVE_HSI = 5, + APBDMA_SLAVE_APBIF_CH4 = 6, + APBDMA_SLAVE_APBIF_CH5 = 7, + APBDMA_SLAVE_UART_A = 8, + APBDMA_SLAVE_UART_B = 9, + APBDMA_SLAVE_UART_C = 10, + APBDMA_SLAVE_DTV = 11, + APBDMA_SLAVE_APBIF_CH6 = 12, + APBDMA_SLAVE_APBIF_CH7 = 13, + APBDMA_SLAVE_APBIF_CH8 = 14, + APBDMA_SLAVE_SL2B1 = 15, + APBDMA_SLAVE_SL2B2 = 16, + APBDMA_SLAVE_SL2B3 = 17, + APBDMA_SLAVE_SL2B4 = 18, + APBDMA_SLAVE_UART_D = 19, + APBDMA_SLAVE_UART_E = 20, + APBDMA_SLAVE_I2C = 21, + APBDMA_SLAVE_I2C2 = 22, + APBDMA_SLAVE_I2C3 = 23, + APBDMA_SLAVE_DVC_I2C = 24, + APBDMA_SLAVE_OWR = 25, + APBDMA_SLAVE_I2C4 = 26, + APBDMA_SLAVE_SL2B5 = 27, + APBDMA_SLAVE_SL2B6 = 28, + APBDMA_SLAVE_APBIF_CH9 = 29, + APBDMA_SLAVE_I2C6 = 30, + APBDMA_SLAVE_NA31 = 31, +}; + +#define APBDMACHAN_STA_BSY (1 << 31) +#define APBDMACHAN_STA_ISE_EOC (1 << 30) +#define APBDMACHAN_STA_HALT (1 << 29) +#define APBDMACHAN_STA_PING_PONG_STA (1 << 28) +#define APBDMACHAN_STA_DMA_ACTIVITY (1 << 27) +#define APBDMACHAN_STA_CHANNEL_PAUSE (1 << 26) + +#define APBDMACHAN_CSRE_CHANNEL_PAUSE (1 << 31) +#define APBDMACHAN_CSRE_TRIG_SEL_MASK 0x3f +#define APBDMACHAN_CSRE_TRIG_SEL_SHIFT 14 + +#define APBDMACHAN_AHB_PTR_MASK (0x3fffffff) +#define APBDMACHAN_AHB_PTR_SHIFT 2 + +#define APBDMACHAN_AHB_SEQ_INTR_ENB (1 << 31) +#define APBDMACHAN_AHB_SEQ_AHB_BUS_WIDTH_MASK 0x7 +#define APBDMACHAN_AHB_SEQ_AHB_BUS_WIDTH_SHIFT 28 +#define APBDMACHAN_AHB_SEQ_AHB_DATA_SWAP (1 << 27) +#define APBDMACHAN_AHB_SEQ_AHB_BURST_MASK 0x7 +#define APBDMACHAN_AHB_SEQ_AHB_BURST_SHIFT 24 +#define APBDMACHAN_AHB_SEQ_DBL_BUF (1 << 19) +#define APBDMACHAN_AHB_SEQ_WRAP_MASK 0x7 +#define APBDMACHAN_AHB_SEQ_WRAP_SHIFT 16 + +#define APBDMACHAN_AHB_SEQ_AHB_BUS_WIDTH_MASK 0x7 +#define APBDMACHAN_AHB_SEQ_AHB_BUS_WIDTH_SHIFT 28 + +#define APBDMACHAN_APB_PTR_MASK 0x3fffffff +#define APBDMACHAN_APB_PTR_SHIFT 2 + +#define APBDMACHAN_APB_SEQ_APB_BUS_WIDTH_MASK 0x7 +#define APBDMACHAN_APB_SEQ_APB_BUS_WIDTH_SHIFT 28 +#define APBDMACHAN_APB_SEQ_APB_DATA_SWAP (1 << 27) +#define APBDMACHAN_APB_SEQ_APB_ADDR_WRAP_MASK 0x7 +#define APBDMACHAN_APB_SEQ_APB_ADDR_WRAP_SHIFT 16 + +#define APBDMACHAN_WORD_TRANSFER_ + +#define APBDMACHAN_WORD_TRANSFER_MASK 0x0fffffff +#define APBDMACHAN_WORD_TRANSFER_SHIFT 2 + struct apb_dma_channel_regs { u32 csr; /* 0x00 */ u32 sta; /* 0x04 */ diff --git a/src/soc/nvidia/tegra124/include/soc/addressmap.h b/src/soc/nvidia/tegra124/include/soc/addressmap.h index 9836215..29598a9 100644 --- a/src/soc/nvidia/tegra124/include/soc/addressmap.h +++ b/src/soc/nvidia/tegra124/include/soc/addressmap.h @@ -32,6 +32,8 @@ enum { TEGRA_ARM_PERIPHBASE = 0x50040000, TEGRA_ARM_DISPLAYA = 0x54200000, TEGRA_ARM_DISPLAYB = 0x54240000, + TEGRA_ARM_SOR = 0x54540000, + TEGRA_ARM_DPAUX = 0x545c0000, TEGRA_PG_UP_BASE = 0x60000000, TEGRA_TMRUS_BASE = 0x60005010, TEGRA_CLK_RST_BASE = 0x60006000, @@ -67,7 +69,10 @@ enum { TEGRA_EMC_BASE = TEGRA_APB_MISC_BASE + 0xF400, TEGRA_FUSE_BASE = TEGRA_APB_MISC_BASE + 0xF800, TEGRA_CSITE_BASE = 0x70040000, - TEGRA_USB_ADDR_MASK = 0xFFFFC000, + TEGRA_SYSCTR0_BASE = 0x700F0000, + TEGRA_USBD_BASE = 0x7D000000, + TEGRA_USB2_BASE = 0x7D004000, + TEGRA_USB3_BASE = 0x7D008000, }; enum { diff --git a/src/soc/nvidia/tegra124/include/soc/ardisplay.h b/src/soc/nvidia/tegra124/include/soc/ardisplay.h new file mode 100644 index 0000000..efc26a7 --- /dev/null +++ b/src/soc/nvidia/tegra124/include/soc/ardisplay.h @@ -0,0 +1,42110 @@ +// +// Copyright (c) 2013 NVIDIA Corporation. +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// +// Neither the name of the NVIDIA Corporation nor the names of its contributors +// may be used to endorse or promote products derived from this software +// without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// + +// +// DO NOT EDIT - generated by simspec! +// + +#ifndef ___ARDISPLAY_H_INC_ +#define ___ARDISPLAY_H_INC_ + +// Packet FAKE_DC_LPM +#define FAKE_DC_LPM_SIZE 21 + +#define FAKE_DC_LPM_CS_SHIFT _MK_SHIFT_CONST(0) +#define FAKE_DC_LPM_CS_FIELD _MK_FIELD_CONST(0x3, FAKE_DC_LPM_CS_SHIFT) +#define FAKE_DC_LPM_CS_RANGE _MK_SHIFT_CONST(1):_MK_SHIFT_CONST(0) +#define FAKE_DC_LPM_CS_ROW 0 + +#define FAKE_DC_LPM_CD_SHIFT _MK_SHIFT_CONST(2) +#define FAKE_DC_LPM_CD_FIELD _MK_FIELD_CONST(0x3f, FAKE_DC_LPM_CD_SHIFT) +#define FAKE_DC_LPM_CD_RANGE _MK_SHIFT_CONST(7):_MK_SHIFT_CONST(2) +#define FAKE_DC_LPM_CD_ROW 0 + +#define FAKE_DC_LPM_P_SHIFT _MK_SHIFT_CONST(8) +#define FAKE_DC_LPM_P_FIELD _MK_FIELD_CONST(0x3f, FAKE_DC_LPM_P_SHIFT) +#define FAKE_DC_LPM_P_RANGE _MK_SHIFT_CONST(13):_MK_SHIFT_CONST(8) +#define FAKE_DC_LPM_P_ROW 0 + +#define FAKE_DC_LPM_D_SHIFT _MK_SHIFT_CONST(14) +#define FAKE_DC_LPM_D_FIELD _MK_FIELD_CONST(0x7f, FAKE_DC_LPM_D_SHIFT) +#define FAKE_DC_LPM_D_RANGE _MK_SHIFT_CONST(20):_MK_SHIFT_CONST(14) +#define FAKE_DC_LPM_D_ROW 0 + + +// Packet FAKE_DC_HSPI +#define FAKE_DC_HSPI_SIZE 44 + +#define FAKE_DC_HSPI_DC_SHIFT _MK_SHIFT_CONST(0) +#define FAKE_DC_HSPI_DC_FIELD _MK_FIELD_CONST(0x1, FAKE_DC_HSPI_DC_SHIFT) +#define FAKE_DC_HSPI_DC_RANGE _MK_SHIFT_CONST(0):_MK_SHIFT_CONST(0) +#define FAKE_DC_HSPI_DC_ROW 0 + +#define FAKE_DC_HSPI_SCS_SHIFT _MK_SHIFT_CONST(1) +#define FAKE_DC_HSPI_SCS_FIELD _MK_FIELD_CONST(0x1, FAKE_DC_HSPI_SCS_SHIFT) +#define FAKE_DC_HSPI_SCS_RANGE _MK_SHIFT_CONST(1):_MK_SHIFT_CONST(1) +#define FAKE_DC_HSPI_SCS_ROW 0 + +#define FAKE_DC_HSPI_DATA_SHIFT _MK_SHIFT_CONST(12) +#define FAKE_DC_HSPI_DATA_FIELD _MK_FIELD_CONST(0xffffff, FAKE_DC_HSPI_DATA_SHIFT) +#define FAKE_DC_HSPI_DATA_RANGE _MK_SHIFT_CONST(35):_MK_SHIFT_CONST(12) +#define FAKE_DC_HSPI_DATA_ROW 0 + +#define FAKE_DC_HSPI_SB_SHIFT _MK_SHIFT_CONST(36) +#define FAKE_DC_HSPI_SB_FIELD _MK_FIELD_CONST(0xff, FAKE_DC_HSPI_SB_SHIFT) +#define FAKE_DC_HSPI_SB_RANGE _MK_SHIFT_CONST(43):_MK_SHIFT_CONST(36) +#define FAKE_DC_HSPI_SB_ROW 0 + + +// Packet DC_PIN_OUTPUT +#define DC_PIN_OUTPUT_SIZE 40 + +#define DC_PIN_OUTPUT_LD17_SHIFT _MK_SHIFT_CONST(0) +#define DC_PIN_OUTPUT_LD17_FIELD _MK_FIELD_CONST(0x1, DC_PIN_OUTPUT_LD17_SHIFT) +#define DC_PIN_OUTPUT_LD17_RANGE _MK_SHIFT_CONST(0):_MK_SHIFT_CONST(0) +#define DC_PIN_OUTPUT_LD17_ROW 0 + +#define DC_PIN_OUTPUT_LD16_SHIFT _MK_SHIFT_CONST(1) +#define DC_PIN_OUTPUT_LD16_FIELD _MK_FIELD_CONST(0x1, DC_PIN_OUTPUT_LD16_SHIFT) +#define DC_PIN_OUTPUT_LD16_RANGE _MK_SHIFT_CONST(1):_MK_SHIFT_CONST(1) +#define DC_PIN_OUTPUT_LD16_ROW 0 + +#define DC_PIN_OUTPUT_LD15_SHIFT _MK_SHIFT_CONST(2) +#define DC_PIN_OUTPUT_LD15_FIELD _MK_FIELD_CONST(0x1, DC_PIN_OUTPUT_LD15_SHIFT) +#define DC_PIN_OUTPUT_LD15_RANGE _MK_SHIFT_CONST(2):_MK_SHIFT_CONST(2) +#define DC_PIN_OUTPUT_LD15_ROW 0 + +#define DC_PIN_OUTPUT_LD14_SHIFT _MK_SHIFT_CONST(3) +#define DC_PIN_OUTPUT_LD14_FIELD _MK_FIELD_CONST(0x1, DC_PIN_OUTPUT_LD14_SHIFT) +#define DC_PIN_OUTPUT_LD14_RANGE _MK_SHIFT_CONST(3):_MK_SHIFT_CONST(3) +#define DC_PIN_OUTPUT_LD14_ROW 0 + +#define DC_PIN_OUTPUT_LD13_SHIFT _MK_SHIFT_CONST(4) +#define DC_PIN_OUTPUT_LD13_FIELD _MK_FIELD_CONST(0x1, DC_PIN_OUTPUT_LD13_SHIFT) +#define DC_PIN_OUTPUT_LD13_RANGE _MK_SHIFT_CONST(4):_MK_SHIFT_CONST(4) +#define DC_PIN_OUTPUT_LD13_ROW 0 + +#define DC_PIN_OUTPUT_LD12_SHIFT _MK_SHIFT_CONST(5) +#define DC_PIN_OUTPUT_LD12_FIELD _MK_FIELD_CONST(0x1, DC_PIN_OUTPUT_LD12_SHIFT) +#define DC_PIN_OUTPUT_LD12_RANGE _MK_SHIFT_CONST(5):_MK_SHIFT_CONST(5) +#define DC_PIN_OUTPUT_LD12_ROW 0 + +#define DC_PIN_OUTPUT_LD11_SHIFT _MK_SHIFT_CONST(6) +#define DC_PIN_OUTPUT_LD11_FIELD _MK_FIELD_CONST(0x1, DC_PIN_OUTPUT_LD11_SHIFT) +#define DC_PIN_OUTPUT_LD11_RANGE _MK_SHIFT_CONST(6):_MK_SHIFT_CONST(6) +#define DC_PIN_OUTPUT_LD11_ROW 0 + +#define DC_PIN_OUTPUT_LD10_SHIFT _MK_SHIFT_CONST(7) +#define DC_PIN_OUTPUT_LD10_FIELD _MK_FIELD_CONST(0x1, DC_PIN_OUTPUT_LD10_SHIFT) +#define DC_PIN_OUTPUT_LD10_RANGE _MK_SHIFT_CONST(7):_MK_SHIFT_CONST(7) +#define DC_PIN_OUTPUT_LD10_ROW 0 + +#define DC_PIN_OUTPUT_LD9_SHIFT _MK_SHIFT_CONST(8) +#define DC_PIN_OUTPUT_LD9_FIELD _MK_FIELD_CONST(0x1, DC_PIN_OUTPUT_LD9_SHIFT) +#define DC_PIN_OUTPUT_LD9_RANGE _MK_SHIFT_CONST(8):_MK_SHIFT_CONST(8) +#define DC_PIN_OUTPUT_LD9_ROW 0 + +#define DC_PIN_OUTPUT_LD8_SHIFT _MK_SHIFT_CONST(9) +#define DC_PIN_OUTPUT_LD8_FIELD _MK_FIELD_CONST(0x1, DC_PIN_OUTPUT_LD8_SHIFT) +#define DC_PIN_OUTPUT_LD8_RANGE _MK_SHIFT_CONST(9):_MK_SHIFT_CONST(9) +#define DC_PIN_OUTPUT_LD8_ROW 0 + +#define DC_PIN_OUTPUT_LD7_SHIFT _MK_SHIFT_CONST(10) +#define DC_PIN_OUTPUT_LD7_FIELD _MK_FIELD_CONST(0x1, DC_PIN_OUTPUT_LD7_SHIFT) +#define DC_PIN_OUTPUT_LD7_RANGE _MK_SHIFT_CONST(10):_MK_SHIFT_CONST(10) +#define DC_PIN_OUTPUT_LD7_ROW 0 + +#define DC_PIN_OUTPUT_LD6_SHIFT _MK_SHIFT_CONST(11) +#define DC_PIN_OUTPUT_LD6_FIELD _MK_FIELD_CONST(0x1, DC_PIN_OUTPUT_LD6_SHIFT) +#define DC_PIN_OUTPUT_LD6_RANGE _MK_SHIFT_CONST(11):_MK_SHIFT_CONST(11) +#define DC_PIN_OUTPUT_LD6_ROW 0 + +#define DC_PIN_OUTPUT_LD5_SHIFT _MK_SHIFT_CONST(12) +#define DC_PIN_OUTPUT_LD5_FIELD _MK_FIELD_CONST(0x1, DC_PIN_OUTPUT_LD5_SHIFT) +#define DC_PIN_OUTPUT_LD5_RANGE _MK_SHIFT_CONST(12):_MK_SHIFT_CONST(12) +#define DC_PIN_OUTPUT_LD5_ROW 0 + +#define DC_PIN_OUTPUT_LD4_SHIFT _MK_SHIFT_CONST(13) +#define DC_PIN_OUTPUT_LD4_FIELD _MK_FIELD_CONST(0x1, DC_PIN_OUTPUT_LD4_SHIFT) +#define DC_PIN_OUTPUT_LD4_RANGE _MK_SHIFT_CONST(13):_MK_SHIFT_CONST(13) +#define DC_PIN_OUTPUT_LD4_ROW 0 + +#define DC_PIN_OUTPUT_LD3_SHIFT _MK_SHIFT_CONST(14) +#define DC_PIN_OUTPUT_LD3_FIELD _MK_FIELD_CONST(0x1, DC_PIN_OUTPUT_LD3_SHIFT) +#define DC_PIN_OUTPUT_LD3_RANGE _MK_SHIFT_CONST(14):_MK_SHIFT_CONST(14) +#define DC_PIN_OUTPUT_LD3_ROW 0 + +#define DC_PIN_OUTPUT_LD2_SHIFT _MK_SHIFT_CONST(15) +#define DC_PIN_OUTPUT_LD2_FIELD _MK_FIELD_CONST(0x1, DC_PIN_OUTPUT_LD2_SHIFT) +#define DC_PIN_OUTPUT_LD2_RANGE _MK_SHIFT_CONST(15):_MK_SHIFT_CONST(15) +#define DC_PIN_OUTPUT_LD2_ROW 0 + +#define DC_PIN_OUTPUT_LD1_SHIFT _MK_SHIFT_CONST(16) +#define DC_PIN_OUTPUT_LD1_FIELD _MK_FIELD_CONST(0x1, DC_PIN_OUTPUT_LD1_SHIFT) +#define DC_PIN_OUTPUT_LD1_RANGE _MK_SHIFT_CONST(16):_MK_SHIFT_CONST(16) +#define DC_PIN_OUTPUT_LD1_ROW 0 + +#define DC_PIN_OUTPUT_LD0_SHIFT _MK_SHIFT_CONST(17) +#define DC_PIN_OUTPUT_LD0_FIELD _MK_FIELD_CONST(0x1, DC_PIN_OUTPUT_LD0_SHIFT) +#define DC_PIN_OUTPUT_LD0_RANGE _MK_SHIFT_CONST(17):_MK_SHIFT_CONST(17) +#define DC_PIN_OUTPUT_LD0_ROW 0 + +#define DC_PIN_OUTPUT_LPW0_SHIFT _MK_SHIFT_CONST(18) +#define DC_PIN_OUTPUT_LPW0_FIELD _MK_FIELD_CONST(0x1, DC_PIN_OUTPUT_LPW0_SHIFT) +#define DC_PIN_OUTPUT_LPW0_RANGE _MK_SHIFT_CONST(18):_MK_SHIFT_CONST(18) +#define DC_PIN_OUTPUT_LPW0_ROW 0 + +#define DC_PIN_OUTPUT_LPW1_SHIFT _MK_SHIFT_CONST(19) +#define DC_PIN_OUTPUT_LPW1_FIELD _MK_FIELD_CONST(0x1, DC_PIN_OUTPUT_LPW1_SHIFT) +#define DC_PIN_OUTPUT_LPW1_RANGE _MK_SHIFT_CONST(19):_MK_SHIFT_CONST(19) +#define DC_PIN_OUTPUT_LPW1_ROW 0 + +#define DC_PIN_OUTPUT_LPW2_SHIFT _MK_SHIFT_CONST(20) +#define DC_PIN_OUTPUT_LPW2_FIELD _MK_FIELD_CONST(0x1, DC_PIN_OUTPUT_LPW2_SHIFT) +#define DC_PIN_OUTPUT_LPW2_RANGE _MK_SHIFT_CONST(20):_MK_SHIFT_CONST(20) +#define DC_PIN_OUTPUT_LPW2_ROW 0 + +#define DC_PIN_OUTPUT_LSC0_SHIFT _MK_SHIFT_CONST(21) +#define DC_PIN_OUTPUT_LSC0_FIELD _MK_FIELD_CONST(0x1, DC_PIN_OUTPUT_LSC0_SHIFT) +#define DC_PIN_OUTPUT_LSC0_RANGE _MK_SHIFT_CONST(21):_MK_SHIFT_CONST(21) +#define DC_PIN_OUTPUT_LSC0_ROW 0 + +#define DC_PIN_OUTPUT_LSC1_SHIFT _MK_SHIFT_CONST(22) +#define DC_PIN_OUTPUT_LSC1_FIELD _MK_FIELD_CONST(0x1, DC_PIN_OUTPUT_LSC1_SHIFT) +#define DC_PIN_OUTPUT_LSC1_RANGE _MK_SHIFT_CONST(22):_MK_SHIFT_CONST(22) +#define DC_PIN_OUTPUT_LSC1_ROW 0 + +#define DC_PIN_OUTPUT_LVS_SHIFT _MK_SHIFT_CONST(23) +#define DC_PIN_OUTPUT_LVS_FIELD _MK_FIELD_CONST(0x1, DC_PIN_OUTPUT_LVS_SHIFT) +#define DC_PIN_OUTPUT_LVS_RANGE _MK_SHIFT_CONST(23):_MK_SHIFT_CONST(23) +#define DC_PIN_OUTPUT_LVS_ROW 0 + +#define DC_PIN_OUTPUT_LHS_SHIFT _MK_SHIFT_CONST(24) +#define DC_PIN_OUTPUT_LHS_FIELD _MK_FIELD_CONST(0x1, DC_PIN_OUTPUT_LHS_SHIFT) +#define DC_PIN_OUTPUT_LHS_RANGE _MK_SHIFT_CONST(24):_MK_SHIFT_CONST(24) +#define DC_PIN_OUTPUT_LHS_ROW 0 + +#define DC_PIN_OUTPUT_LHP0_SHIFT _MK_SHIFT_CONST(25) +#define DC_PIN_OUTPUT_LHP0_FIELD _MK_FIELD_CONST(0x1, DC_PIN_OUTPUT_LHP0_SHIFT) +#define DC_PIN_OUTPUT_LHP0_RANGE _MK_SHIFT_CONST(25):_MK_SHIFT_CONST(25) +#define DC_PIN_OUTPUT_LHP0_ROW 0 + +#define DC_PIN_OUTPUT_LHP1_SHIFT _MK_SHIFT_CONST(26) +#define DC_PIN_OUTPUT_LHP1_FIELD _MK_FIELD_CONST(0x1, DC_PIN_OUTPUT_LHP1_SHIFT) +#define DC_PIN_OUTPUT_LHP1_RANGE _MK_SHIFT_CONST(26):_MK_SHIFT_CONST(26) +#define DC_PIN_OUTPUT_LHP1_ROW 0 + +#define DC_PIN_OUTPUT_LHP2_SHIFT _MK_SHIFT_CONST(27) +#define DC_PIN_OUTPUT_LHP2_FIELD _MK_FIELD_CONST(0x1, DC_PIN_OUTPUT_LHP2_SHIFT) +#define DC_PIN_OUTPUT_LHP2_RANGE _MK_SHIFT_CONST(27):_MK_SHIFT_CONST(27) +#define DC_PIN_OUTPUT_LHP2_ROW 0 + +#define DC_PIN_OUTPUT_LVP0_SHIFT _MK_SHIFT_CONST(28) +#define DC_PIN_OUTPUT_LVP0_FIELD _MK_FIELD_CONST(0x1, DC_PIN_OUTPUT_LVP0_SHIFT) +#define DC_PIN_OUTPUT_LVP0_RANGE _MK_SHIFT_CONST(28):_MK_SHIFT_CONST(28) +#define DC_PIN_OUTPUT_LVP0_ROW 0 + +#define DC_PIN_OUTPUT_LVP1_SHIFT _MK_SHIFT_CONST(29) +#define DC_PIN_OUTPUT_LVP1_FIELD _MK_FIELD_CONST(0x1, DC_PIN_OUTPUT_LVP1_SHIFT) +#define DC_PIN_OUTPUT_LVP1_RANGE _MK_SHIFT_CONST(29):_MK_SHIFT_CONST(29) +#define DC_PIN_OUTPUT_LVP1_ROW 0 + +#define DC_PIN_OUTPUT_LM0_SHIFT _MK_SHIFT_CONST(30) +#define DC_PIN_OUTPUT_LM0_FIELD _MK_FIELD_CONST(0x1, DC_PIN_OUTPUT_LM0_SHIFT) +#define DC_PIN_OUTPUT_LM0_RANGE _MK_SHIFT_CONST(30):_MK_SHIFT_CONST(30) +#define DC_PIN_OUTPUT_LM0_ROW 0 + +#define DC_PIN_OUTPUT_LM1_SHIFT _MK_SHIFT_CONST(31) +#define DC_PIN_OUTPUT_LM1_FIELD _MK_FIELD_CONST(0x1, DC_PIN_OUTPUT_LM1_SHIFT) +#define DC_PIN_OUTPUT_LM1_RANGE _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(31) +#define DC_PIN_OUTPUT_LM1_ROW 0 + +#define DC_PIN_OUTPUT_LDI_SHIFT _MK_SHIFT_CONST(32) +#define DC_PIN_OUTPUT_LDI_FIELD _MK_FIELD_CONST(0x1, DC_PIN_OUTPUT_LDI_SHIFT) +#define DC_PIN_OUTPUT_LDI_RANGE _MK_SHIFT_CONST(32):_MK_SHIFT_CONST(32) +#define DC_PIN_OUTPUT_LDI_ROW 0 + +#define DC_PIN_OUTPUT_LPP_SHIFT _MK_SHIFT_CONST(33) +#define DC_PIN_OUTPUT_LPP_FIELD _MK_FIELD_CONST(0x1, DC_PIN_OUTPUT_LPP_SHIFT) +#define DC_PIN_OUTPUT_LPP_RANGE _MK_SHIFT_CONST(33):_MK_SHIFT_CONST(33) +#define DC_PIN_OUTPUT_LPP_ROW 0 + +#define DC_PIN_OUTPUT_LSCK_SHIFT _MK_SHIFT_CONST(34) +#define DC_PIN_OUTPUT_LSCK_FIELD _MK_FIELD_CONST(0x1, DC_PIN_OUTPUT_LSCK_SHIFT) +#define DC_PIN_OUTPUT_LSCK_RANGE _MK_SHIFT_CONST(34):_MK_SHIFT_CONST(34) +#define DC_PIN_OUTPUT_LSCK_ROW 0 + +#define DC_PIN_OUTPUT_LSDA_SHIFT _MK_SHIFT_CONST(35) +#define DC_PIN_OUTPUT_LSDA_FIELD _MK_FIELD_CONST(0x1, DC_PIN_OUTPUT_LSDA_SHIFT) +#define DC_PIN_OUTPUT_LSDA_RANGE _MK_SHIFT_CONST(35):_MK_SHIFT_CONST(35) +#define DC_PIN_OUTPUT_LSDA_ROW 0 + +#define DC_PIN_OUTPUT_LCSN_SHIFT _MK_SHIFT_CONST(36) +#define DC_PIN_OUTPUT_LCSN_FIELD _MK_FIELD_CONST(0x1, DC_PIN_OUTPUT_LCSN_SHIFT) +#define DC_PIN_OUTPUT_LCSN_RANGE _MK_SHIFT_CONST(36):_MK_SHIFT_CONST(36) +#define DC_PIN_OUTPUT_LCSN_ROW 0 + +#define DC_PIN_OUTPUT_LDC_SHIFT _MK_SHIFT_CONST(37) +#define DC_PIN_OUTPUT_LDC_FIELD _MK_FIELD_CONST(0x1, DC_PIN_OUTPUT_LDC_SHIFT) +#define DC_PIN_OUTPUT_LDC_RANGE _MK_SHIFT_CONST(37):_MK_SHIFT_CONST(37) +#define DC_PIN_OUTPUT_LDC_ROW 0 + +#define DC_PIN_OUTPUT_LSPI_SHIFT _MK_SHIFT_CONST(38) +#define DC_PIN_OUTPUT_LSPI_FIELD _MK_FIELD_CONST(0x1, DC_PIN_OUTPUT_LSPI_SHIFT) +#define DC_PIN_OUTPUT_LSPI_RANGE _MK_SHIFT_CONST(38):_MK_SHIFT_CONST(38) +#define DC_PIN_OUTPUT_LSPI_ROW 0 + +#define DC_PIN_OUTPUT_LSDI_SHIFT _MK_SHIFT_CONST(39) +#define DC_PIN_OUTPUT_LSDI_FIELD _MK_FIELD_CONST(0x1, DC_PIN_OUTPUT_LSDI_SHIFT) +#define DC_PIN_OUTPUT_LSDI_RANGE _MK_SHIFT_CONST(39):_MK_SHIFT_CONST(39) +#define DC_PIN_OUTPUT_LSDI_ROW 0 + + +// Packet RAISE +#define RAISE_SIZE 20 + +#define RAISE_RAISEVAL_SHIFT _MK_SHIFT_CONST(0) +#define RAISE_RAISEVAL_FIELD _MK_FIELD_CONST(0x1f, RAISE_RAISEVAL_SHIFT) +#define RAISE_RAISEVAL_RANGE _MK_SHIFT_CONST(4):_MK_SHIFT_CONST(0) +#define RAISE_RAISEVAL_ROW 0 + +#define RAISE_CHANNEL_SHIFT _MK_SHIFT_CONST(16) +#define RAISE_CHANNEL_FIELD _MK_FIELD_CONST(0xf, RAISE_CHANNEL_SHIFT) +#define RAISE_CHANNEL_RANGE _MK_SHIFT_CONST(19):_MK_SHIFT_CONST(16) +#define RAISE_CHANNEL_ROW 0 + +#define NV_DISPLAY_GENERAL_INCR_SYNCPT_NB_CONDS 8 + +// Register DC_CMD_GENERAL_INCR_SYNCPT_0 +#define DC_CMD_GENERAL_INCR_SYNCPT_0 _MK_ADDR_CONST(0x0) +#define DC_CMD_GENERAL_INCR_SYNCPT_0_SECURE 0x0 +#define DC_CMD_GENERAL_INCR_SYNCPT_0_WORD_COUNT 0x1 +#define DC_CMD_GENERAL_INCR_SYNCPT_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_CMD_GENERAL_INCR_SYNCPT_0_RESET_MASK _MK_MASK_CONST(0xffff) +#define DC_CMD_GENERAL_INCR_SYNCPT_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_CMD_GENERAL_INCR_SYNCPT_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_CMD_GENERAL_INCR_SYNCPT_0_READ_MASK _MK_MASK_CONST(0xffff) +#define DC_CMD_GENERAL_INCR_SYNCPT_0_WRITE_MASK _MK_MASK_CONST(0xffff) +#define DC_CMD_GENERAL_INCR_SYNCPT_0_GENERAL_COND_SHIFT _MK_SHIFT_CONST(8) +#define DC_CMD_GENERAL_INCR_SYNCPT_0_GENERAL_COND_FIELD _MK_FIELD_CONST(0xff, DC_CMD_GENERAL_INCR_SYNCPT_0_GENERAL_COND_SHIFT) +#define DC_CMD_GENERAL_INCR_SYNCPT_0_GENERAL_COND_RANGE 15:8 +#define DC_CMD_GENERAL_INCR_SYNCPT_0_GENERAL_COND_WOFFSET 0x0 +#define DC_CMD_GENERAL_INCR_SYNCPT_0_GENERAL_COND_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_GENERAL_INCR_SYNCPT_0_GENERAL_COND_DEFAULT_MASK _MK_MASK_CONST(0xff) +#define DC_CMD_GENERAL_INCR_SYNCPT_0_GENERAL_COND_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_GENERAL_INCR_SYNCPT_0_GENERAL_COND_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_CMD_GENERAL_INCR_SYNCPT_0_GENERAL_COND_IMMEDIATE _MK_ENUM_CONST(0) +#define DC_CMD_GENERAL_INCR_SYNCPT_0_GENERAL_COND_OP_DONE _MK_ENUM_CONST(1) +#define DC_CMD_GENERAL_INCR_SYNCPT_0_GENERAL_COND_RD_DONE _MK_ENUM_CONST(2) +#define DC_CMD_GENERAL_INCR_SYNCPT_0_GENERAL_COND_REG_WR_SAFE _MK_ENUM_CONST(3) +#define DC_CMD_GENERAL_INCR_SYNCPT_0_GENERAL_COND_HSPI _MK_ENUM_CONST(4) +#define DC_CMD_GENERAL_INCR_SYNCPT_0_GENERAL_COND_FRAME_DONE _MK_ENUM_CONST(5) +#define DC_CMD_GENERAL_INCR_SYNCPT_0_GENERAL_COND_VPULSE3 _MK_ENUM_CONST(6) +#define DC_CMD_GENERAL_INCR_SYNCPT_0_GENERAL_COND_FRAME_START _MK_ENUM_CONST(7) +#define DC_CMD_GENERAL_INCR_SYNCPT_0_GENERAL_COND_COND_8 _MK_ENUM_CONST(8) +#define DC_CMD_GENERAL_INCR_SYNCPT_0_GENERAL_COND_COND_9 _MK_ENUM_CONST(9) +#define DC_CMD_GENERAL_INCR_SYNCPT_0_GENERAL_COND_COND_10 _MK_ENUM_CONST(10) +#define DC_CMD_GENERAL_INCR_SYNCPT_0_GENERAL_COND_COND_11 _MK_ENUM_CONST(11) +#define DC_CMD_GENERAL_INCR_SYNCPT_0_GENERAL_COND_COND_12 _MK_ENUM_CONST(12) +#define DC_CMD_GENERAL_INCR_SYNCPT_0_GENERAL_COND_COND_13 _MK_ENUM_CONST(13) +#define DC_CMD_GENERAL_INCR_SYNCPT_0_GENERAL_COND_COND_14 _MK_ENUM_CONST(14) +#define DC_CMD_GENERAL_INCR_SYNCPT_0_GENERAL_COND_COND_15 _MK_ENUM_CONST(15) +#define DC_CMD_GENERAL_INCR_SYNCPT_0_GENERAL_COND_COND_16 _MK_ENUM_CONST(16) +#define DC_CMD_GENERAL_INCR_SYNCPT_0_GENERAL_COND_COND_17 _MK_ENUM_CONST(17) +#define DC_CMD_GENERAL_INCR_SYNCPT_0_GENERAL_COND_COND_18 _MK_ENUM_CONST(18) +#define DC_CMD_GENERAL_INCR_SYNCPT_0_GENERAL_COND_COND_19 _MK_ENUM_CONST(19) +#define DC_CMD_GENERAL_INCR_SYNCPT_0_GENERAL_COND_COND_20 _MK_ENUM_CONST(20) +#define DC_CMD_GENERAL_INCR_SYNCPT_0_GENERAL_COND_COND_21 _MK_ENUM_CONST(21) +#define DC_CMD_GENERAL_INCR_SYNCPT_0_GENERAL_COND_COND_22 _MK_ENUM_CONST(22) +#define DC_CMD_GENERAL_INCR_SYNCPT_0_GENERAL_COND_COND_23 _MK_ENUM_CONST(23) +#define DC_CMD_GENERAL_INCR_SYNCPT_0_GENERAL_COND_COND_24 _MK_ENUM_CONST(24) +#define DC_CMD_GENERAL_INCR_SYNCPT_0_GENERAL_COND_COND_25 _MK_ENUM_CONST(25) +#define DC_CMD_GENERAL_INCR_SYNCPT_0_GENERAL_COND_COND_26 _MK_ENUM_CONST(26) +#define DC_CMD_GENERAL_INCR_SYNCPT_0_GENERAL_COND_COND_27 _MK_ENUM_CONST(27) +#define DC_CMD_GENERAL_INCR_SYNCPT_0_GENERAL_COND_COND_28 _MK_ENUM_CONST(28) +#define DC_CMD_GENERAL_INCR_SYNCPT_0_GENERAL_COND_COND_29 _MK_ENUM_CONST(29) +#define DC_CMD_GENERAL_INCR_SYNCPT_0_GENERAL_COND_COND_30 _MK_ENUM_CONST(30) +#define DC_CMD_GENERAL_INCR_SYNCPT_0_GENERAL_COND_COND_31 _MK_ENUM_CONST(31) + +#define DC_CMD_GENERAL_INCR_SYNCPT_0_GENERAL_INDX_SHIFT _MK_SHIFT_CONST(0) +#define DC_CMD_GENERAL_INCR_SYNCPT_0_GENERAL_INDX_FIELD _MK_FIELD_CONST(0xff, DC_CMD_GENERAL_INCR_SYNCPT_0_GENERAL_INDX_SHIFT) +#define DC_CMD_GENERAL_INCR_SYNCPT_0_GENERAL_INDX_RANGE 7:0 +#define DC_CMD_GENERAL_INCR_SYNCPT_0_GENERAL_INDX_WOFFSET 0x0 +#define DC_CMD_GENERAL_INCR_SYNCPT_0_GENERAL_INDX_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_GENERAL_INCR_SYNCPT_0_GENERAL_INDX_DEFAULT_MASK _MK_MASK_CONST(0xff) +#define DC_CMD_GENERAL_INCR_SYNCPT_0_GENERAL_INDX_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_GENERAL_INCR_SYNCPT_0_GENERAL_INDX_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_CMD_GENERAL_INCR_SYNCPT_CNTRL_0 +#define DC_CMD_GENERAL_INCR_SYNCPT_CNTRL_0 _MK_ADDR_CONST(0x1) +#define DC_CMD_GENERAL_INCR_SYNCPT_CNTRL_0_SECURE 0x0 +#define DC_CMD_GENERAL_INCR_SYNCPT_CNTRL_0_WORD_COUNT 0x1 +#define DC_CMD_GENERAL_INCR_SYNCPT_CNTRL_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_CMD_GENERAL_INCR_SYNCPT_CNTRL_0_RESET_MASK _MK_MASK_CONST(0x101) +#define DC_CMD_GENERAL_INCR_SYNCPT_CNTRL_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_CMD_GENERAL_INCR_SYNCPT_CNTRL_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_CMD_GENERAL_INCR_SYNCPT_CNTRL_0_READ_MASK _MK_MASK_CONST(0x101) +#define DC_CMD_GENERAL_INCR_SYNCPT_CNTRL_0_WRITE_MASK _MK_MASK_CONST(0x101) +#define DC_CMD_GENERAL_INCR_SYNCPT_CNTRL_0_GENERAL_INCR_SYNCPT_NO_STALL_SHIFT _MK_SHIFT_CONST(8) +#define DC_CMD_GENERAL_INCR_SYNCPT_CNTRL_0_GENERAL_INCR_SYNCPT_NO_STALL_FIELD _MK_FIELD_CONST(0x1, DC_CMD_GENERAL_INCR_SYNCPT_CNTRL_0_GENERAL_INCR_SYNCPT_NO_STALL_SHIFT) +#define DC_CMD_GENERAL_INCR_SYNCPT_CNTRL_0_GENERAL_INCR_SYNCPT_NO_STALL_RANGE 8:8 +#define DC_CMD_GENERAL_INCR_SYNCPT_CNTRL_0_GENERAL_INCR_SYNCPT_NO_STALL_WOFFSET 0x0 +#define DC_CMD_GENERAL_INCR_SYNCPT_CNTRL_0_GENERAL_INCR_SYNCPT_NO_STALL_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_GENERAL_INCR_SYNCPT_CNTRL_0_GENERAL_INCR_SYNCPT_NO_STALL_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_CMD_GENERAL_INCR_SYNCPT_CNTRL_0_GENERAL_INCR_SYNCPT_NO_STALL_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_GENERAL_INCR_SYNCPT_CNTRL_0_GENERAL_INCR_SYNCPT_NO_STALL_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_CMD_GENERAL_INCR_SYNCPT_CNTRL_0_GENERAL_INCR_SYNCPT_SOFT_RESET_SHIFT _MK_SHIFT_CONST(0) +#define DC_CMD_GENERAL_INCR_SYNCPT_CNTRL_0_GENERAL_INCR_SYNCPT_SOFT_RESET_FIELD _MK_FIELD_CONST(0x1, DC_CMD_GENERAL_INCR_SYNCPT_CNTRL_0_GENERAL_INCR_SYNCPT_SOFT_RESET_SHIFT) +#define DC_CMD_GENERAL_INCR_SYNCPT_CNTRL_0_GENERAL_INCR_SYNCPT_SOFT_RESET_RANGE 0:0 +#define DC_CMD_GENERAL_INCR_SYNCPT_CNTRL_0_GENERAL_INCR_SYNCPT_SOFT_RESET_WOFFSET 0x0 +#define DC_CMD_GENERAL_INCR_SYNCPT_CNTRL_0_GENERAL_INCR_SYNCPT_SOFT_RESET_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_GENERAL_INCR_SYNCPT_CNTRL_0_GENERAL_INCR_SYNCPT_SOFT_RESET_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_CMD_GENERAL_INCR_SYNCPT_CNTRL_0_GENERAL_INCR_SYNCPT_SOFT_RESET_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_GENERAL_INCR_SYNCPT_CNTRL_0_GENERAL_INCR_SYNCPT_SOFT_RESET_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_CMD_GENERAL_INCR_SYNCPT_ERROR_0 +#define DC_CMD_GENERAL_INCR_SYNCPT_ERROR_0 _MK_ADDR_CONST(0x2) +#define DC_CMD_GENERAL_INCR_SYNCPT_ERROR_0_SECURE 0x0 +#define DC_CMD_GENERAL_INCR_SYNCPT_ERROR_0_WORD_COUNT 0x1 +#define DC_CMD_GENERAL_INCR_SYNCPT_ERROR_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_CMD_GENERAL_INCR_SYNCPT_ERROR_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_CMD_GENERAL_INCR_SYNCPT_ERROR_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_CMD_GENERAL_INCR_SYNCPT_ERROR_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_CMD_GENERAL_INCR_SYNCPT_ERROR_0_READ_MASK _MK_MASK_CONST(0xffffffff) +#define DC_CMD_GENERAL_INCR_SYNCPT_ERROR_0_WRITE_MASK _MK_MASK_CONST(0xffffffff) +#define DC_CMD_GENERAL_INCR_SYNCPT_ERROR_0_GENERAL_COND_STATUS_SHIFT _MK_SHIFT_CONST(0) +#define DC_CMD_GENERAL_INCR_SYNCPT_ERROR_0_GENERAL_COND_STATUS_FIELD _MK_FIELD_CONST(0xffffffff, DC_CMD_GENERAL_INCR_SYNCPT_ERROR_0_GENERAL_COND_STATUS_SHIFT) +#define DC_CMD_GENERAL_INCR_SYNCPT_ERROR_0_GENERAL_COND_STATUS_RANGE 31:0 +#define DC_CMD_GENERAL_INCR_SYNCPT_ERROR_0_GENERAL_COND_STATUS_WOFFSET 0x0 +#define DC_CMD_GENERAL_INCR_SYNCPT_ERROR_0_GENERAL_COND_STATUS_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_GENERAL_INCR_SYNCPT_ERROR_0_GENERAL_COND_STATUS_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_CMD_GENERAL_INCR_SYNCPT_ERROR_0_GENERAL_COND_STATUS_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_GENERAL_INCR_SYNCPT_ERROR_0_GENERAL_COND_STATUS_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Reserved address 3 [0x3] + +// Reserved address 4 [0x4] + +// Reserved address 5 [0x5] + +// Reserved address 6 [0x6] + +// Reserved address 7 [0x7] +#define NV_DISPLAY_WIN_A_INCR_SYNCPT_NB_CONDS 4 + +// Register DC_CMD_WIN_A_INCR_SYNCPT_0 +#define DC_CMD_WIN_A_INCR_SYNCPT_0 _MK_ADDR_CONST(0x8) +#define DC_CMD_WIN_A_INCR_SYNCPT_0_SECURE 0x0 +#define DC_CMD_WIN_A_INCR_SYNCPT_0_WORD_COUNT 0x1 +#define DC_CMD_WIN_A_INCR_SYNCPT_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_CMD_WIN_A_INCR_SYNCPT_0_RESET_MASK _MK_MASK_CONST(0xffff) +#define DC_CMD_WIN_A_INCR_SYNCPT_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_CMD_WIN_A_INCR_SYNCPT_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_CMD_WIN_A_INCR_SYNCPT_0_READ_MASK _MK_MASK_CONST(0xffff) +#define DC_CMD_WIN_A_INCR_SYNCPT_0_WRITE_MASK _MK_MASK_CONST(0xffff) +#define DC_CMD_WIN_A_INCR_SYNCPT_0_WIN_A_COND_SHIFT _MK_SHIFT_CONST(8) +#define DC_CMD_WIN_A_INCR_SYNCPT_0_WIN_A_COND_FIELD _MK_FIELD_CONST(0xff, DC_CMD_WIN_A_INCR_SYNCPT_0_WIN_A_COND_SHIFT) +#define DC_CMD_WIN_A_INCR_SYNCPT_0_WIN_A_COND_RANGE 15:8 +#define DC_CMD_WIN_A_INCR_SYNCPT_0_WIN_A_COND_WOFFSET 0x0 +#define DC_CMD_WIN_A_INCR_SYNCPT_0_WIN_A_COND_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_WIN_A_INCR_SYNCPT_0_WIN_A_COND_DEFAULT_MASK _MK_MASK_CONST(0xff) +#define DC_CMD_WIN_A_INCR_SYNCPT_0_WIN_A_COND_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_WIN_A_INCR_SYNCPT_0_WIN_A_COND_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_CMD_WIN_A_INCR_SYNCPT_0_WIN_A_COND_IMMEDIATE _MK_ENUM_CONST(0) +#define DC_CMD_WIN_A_INCR_SYNCPT_0_WIN_A_COND_OP_DONE _MK_ENUM_CONST(1) +#define DC_CMD_WIN_A_INCR_SYNCPT_0_WIN_A_COND_RD_DONE _MK_ENUM_CONST(2) +#define DC_CMD_WIN_A_INCR_SYNCPT_0_WIN_A_COND_REG_WR_SAFE _MK_ENUM_CONST(3) +#define DC_CMD_WIN_A_INCR_SYNCPT_0_WIN_A_COND_COND_4 _MK_ENUM_CONST(4) +#define DC_CMD_WIN_A_INCR_SYNCPT_0_WIN_A_COND_COND_5 _MK_ENUM_CONST(5) +#define DC_CMD_WIN_A_INCR_SYNCPT_0_WIN_A_COND_COND_6 _MK_ENUM_CONST(6) +#define DC_CMD_WIN_A_INCR_SYNCPT_0_WIN_A_COND_COND_7 _MK_ENUM_CONST(7) +#define DC_CMD_WIN_A_INCR_SYNCPT_0_WIN_A_COND_COND_8 _MK_ENUM_CONST(8) +#define DC_CMD_WIN_A_INCR_SYNCPT_0_WIN_A_COND_COND_9 _MK_ENUM_CONST(9) +#define DC_CMD_WIN_A_INCR_SYNCPT_0_WIN_A_COND_COND_10 _MK_ENUM_CONST(10) +#define DC_CMD_WIN_A_INCR_SYNCPT_0_WIN_A_COND_COND_11 _MK_ENUM_CONST(11) +#define DC_CMD_WIN_A_INCR_SYNCPT_0_WIN_A_COND_COND_12 _MK_ENUM_CONST(12) +#define DC_CMD_WIN_A_INCR_SYNCPT_0_WIN_A_COND_COND_13 _MK_ENUM_CONST(13) +#define DC_CMD_WIN_A_INCR_SYNCPT_0_WIN_A_COND_COND_14 _MK_ENUM_CONST(14) +#define DC_CMD_WIN_A_INCR_SYNCPT_0_WIN_A_COND_COND_15 _MK_ENUM_CONST(15) +#define DC_CMD_WIN_A_INCR_SYNCPT_0_WIN_A_COND_COND_16 _MK_ENUM_CONST(16) +#define DC_CMD_WIN_A_INCR_SYNCPT_0_WIN_A_COND_COND_17 _MK_ENUM_CONST(17) +#define DC_CMD_WIN_A_INCR_SYNCPT_0_WIN_A_COND_COND_18 _MK_ENUM_CONST(18) +#define DC_CMD_WIN_A_INCR_SYNCPT_0_WIN_A_COND_COND_19 _MK_ENUM_CONST(19) +#define DC_CMD_WIN_A_INCR_SYNCPT_0_WIN_A_COND_COND_20 _MK_ENUM_CONST(20) +#define DC_CMD_WIN_A_INCR_SYNCPT_0_WIN_A_COND_COND_21 _MK_ENUM_CONST(21) +#define DC_CMD_WIN_A_INCR_SYNCPT_0_WIN_A_COND_COND_22 _MK_ENUM_CONST(22) +#define DC_CMD_WIN_A_INCR_SYNCPT_0_WIN_A_COND_COND_23 _MK_ENUM_CONST(23) +#define DC_CMD_WIN_A_INCR_SYNCPT_0_WIN_A_COND_COND_24 _MK_ENUM_CONST(24) +#define DC_CMD_WIN_A_INCR_SYNCPT_0_WIN_A_COND_COND_25 _MK_ENUM_CONST(25) +#define DC_CMD_WIN_A_INCR_SYNCPT_0_WIN_A_COND_COND_26 _MK_ENUM_CONST(26) +#define DC_CMD_WIN_A_INCR_SYNCPT_0_WIN_A_COND_COND_27 _MK_ENUM_CONST(27) +#define DC_CMD_WIN_A_INCR_SYNCPT_0_WIN_A_COND_COND_28 _MK_ENUM_CONST(28) +#define DC_CMD_WIN_A_INCR_SYNCPT_0_WIN_A_COND_COND_29 _MK_ENUM_CONST(29) +#define DC_CMD_WIN_A_INCR_SYNCPT_0_WIN_A_COND_COND_30 _MK_ENUM_CONST(30) +#define DC_CMD_WIN_A_INCR_SYNCPT_0_WIN_A_COND_COND_31 _MK_ENUM_CONST(31) + +#define DC_CMD_WIN_A_INCR_SYNCPT_0_WIN_A_INDX_SHIFT _MK_SHIFT_CONST(0) +#define DC_CMD_WIN_A_INCR_SYNCPT_0_WIN_A_INDX_FIELD _MK_FIELD_CONST(0xff, DC_CMD_WIN_A_INCR_SYNCPT_0_WIN_A_INDX_SHIFT) +#define DC_CMD_WIN_A_INCR_SYNCPT_0_WIN_A_INDX_RANGE 7:0 +#define DC_CMD_WIN_A_INCR_SYNCPT_0_WIN_A_INDX_WOFFSET 0x0 +#define DC_CMD_WIN_A_INCR_SYNCPT_0_WIN_A_INDX_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_WIN_A_INCR_SYNCPT_0_WIN_A_INDX_DEFAULT_MASK _MK_MASK_CONST(0xff) +#define DC_CMD_WIN_A_INCR_SYNCPT_0_WIN_A_INDX_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_WIN_A_INCR_SYNCPT_0_WIN_A_INDX_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_CMD_WIN_A_INCR_SYNCPT_CNTRL_0 +#define DC_CMD_WIN_A_INCR_SYNCPT_CNTRL_0 _MK_ADDR_CONST(0x9) +#define DC_CMD_WIN_A_INCR_SYNCPT_CNTRL_0_SECURE 0x0 +#define DC_CMD_WIN_A_INCR_SYNCPT_CNTRL_0_WORD_COUNT 0x1 +#define DC_CMD_WIN_A_INCR_SYNCPT_CNTRL_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_CMD_WIN_A_INCR_SYNCPT_CNTRL_0_RESET_MASK _MK_MASK_CONST(0x101) +#define DC_CMD_WIN_A_INCR_SYNCPT_CNTRL_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_CMD_WIN_A_INCR_SYNCPT_CNTRL_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_CMD_WIN_A_INCR_SYNCPT_CNTRL_0_READ_MASK _MK_MASK_CONST(0x101) +#define DC_CMD_WIN_A_INCR_SYNCPT_CNTRL_0_WRITE_MASK _MK_MASK_CONST(0x101) +#define DC_CMD_WIN_A_INCR_SYNCPT_CNTRL_0_WIN_A_INCR_SYNCPT_NO_STALL_SHIFT _MK_SHIFT_CONST(8) +#define DC_CMD_WIN_A_INCR_SYNCPT_CNTRL_0_WIN_A_INCR_SYNCPT_NO_STALL_FIELD _MK_FIELD_CONST(0x1, DC_CMD_WIN_A_INCR_SYNCPT_CNTRL_0_WIN_A_INCR_SYNCPT_NO_STALL_SHIFT) +#define DC_CMD_WIN_A_INCR_SYNCPT_CNTRL_0_WIN_A_INCR_SYNCPT_NO_STALL_RANGE 8:8 +#define DC_CMD_WIN_A_INCR_SYNCPT_CNTRL_0_WIN_A_INCR_SYNCPT_NO_STALL_WOFFSET 0x0 +#define DC_CMD_WIN_A_INCR_SYNCPT_CNTRL_0_WIN_A_INCR_SYNCPT_NO_STALL_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_WIN_A_INCR_SYNCPT_CNTRL_0_WIN_A_INCR_SYNCPT_NO_STALL_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_CMD_WIN_A_INCR_SYNCPT_CNTRL_0_WIN_A_INCR_SYNCPT_NO_STALL_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_WIN_A_INCR_SYNCPT_CNTRL_0_WIN_A_INCR_SYNCPT_NO_STALL_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_CMD_WIN_A_INCR_SYNCPT_CNTRL_0_WIN_A_INCR_SYNCPT_SOFT_RESET_SHIFT _MK_SHIFT_CONST(0) +#define DC_CMD_WIN_A_INCR_SYNCPT_CNTRL_0_WIN_A_INCR_SYNCPT_SOFT_RESET_FIELD _MK_FIELD_CONST(0x1, DC_CMD_WIN_A_INCR_SYNCPT_CNTRL_0_WIN_A_INCR_SYNCPT_SOFT_RESET_SHIFT) +#define DC_CMD_WIN_A_INCR_SYNCPT_CNTRL_0_WIN_A_INCR_SYNCPT_SOFT_RESET_RANGE 0:0 +#define DC_CMD_WIN_A_INCR_SYNCPT_CNTRL_0_WIN_A_INCR_SYNCPT_SOFT_RESET_WOFFSET 0x0 +#define DC_CMD_WIN_A_INCR_SYNCPT_CNTRL_0_WIN_A_INCR_SYNCPT_SOFT_RESET_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_WIN_A_INCR_SYNCPT_CNTRL_0_WIN_A_INCR_SYNCPT_SOFT_RESET_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_CMD_WIN_A_INCR_SYNCPT_CNTRL_0_WIN_A_INCR_SYNCPT_SOFT_RESET_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_WIN_A_INCR_SYNCPT_CNTRL_0_WIN_A_INCR_SYNCPT_SOFT_RESET_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_CMD_WIN_A_INCR_SYNCPT_ERROR_0 +#define DC_CMD_WIN_A_INCR_SYNCPT_ERROR_0 _MK_ADDR_CONST(0xa) +#define DC_CMD_WIN_A_INCR_SYNCPT_ERROR_0_SECURE 0x0 +#define DC_CMD_WIN_A_INCR_SYNCPT_ERROR_0_WORD_COUNT 0x1 +#define DC_CMD_WIN_A_INCR_SYNCPT_ERROR_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_CMD_WIN_A_INCR_SYNCPT_ERROR_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_CMD_WIN_A_INCR_SYNCPT_ERROR_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_CMD_WIN_A_INCR_SYNCPT_ERROR_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_CMD_WIN_A_INCR_SYNCPT_ERROR_0_READ_MASK _MK_MASK_CONST(0xffffffff) +#define DC_CMD_WIN_A_INCR_SYNCPT_ERROR_0_WRITE_MASK _MK_MASK_CONST(0xffffffff) +#define DC_CMD_WIN_A_INCR_SYNCPT_ERROR_0_WIN_A_COND_STATUS_SHIFT _MK_SHIFT_CONST(0) +#define DC_CMD_WIN_A_INCR_SYNCPT_ERROR_0_WIN_A_COND_STATUS_FIELD _MK_FIELD_CONST(0xffffffff, DC_CMD_WIN_A_INCR_SYNCPT_ERROR_0_WIN_A_COND_STATUS_SHIFT) +#define DC_CMD_WIN_A_INCR_SYNCPT_ERROR_0_WIN_A_COND_STATUS_RANGE 31:0 +#define DC_CMD_WIN_A_INCR_SYNCPT_ERROR_0_WIN_A_COND_STATUS_WOFFSET 0x0 +#define DC_CMD_WIN_A_INCR_SYNCPT_ERROR_0_WIN_A_COND_STATUS_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_WIN_A_INCR_SYNCPT_ERROR_0_WIN_A_COND_STATUS_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_CMD_WIN_A_INCR_SYNCPT_ERROR_0_WIN_A_COND_STATUS_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_WIN_A_INCR_SYNCPT_ERROR_0_WIN_A_COND_STATUS_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Reserved address 11 [0xb] + +// Reserved address 12 [0xc] + +// Reserved address 13 [0xd] + +// Reserved address 14 [0xe] + +// Reserved address 15 [0xf] +#define NV_DISPLAY_WIN_B_INCR_SYNCPT_NB_CONDS 4 + +// Register DC_CMD_WIN_B_INCR_SYNCPT_0 +#define DC_CMD_WIN_B_INCR_SYNCPT_0 _MK_ADDR_CONST(0x10) +#define DC_CMD_WIN_B_INCR_SYNCPT_0_SECURE 0x0 +#define DC_CMD_WIN_B_INCR_SYNCPT_0_WORD_COUNT 0x1 +#define DC_CMD_WIN_B_INCR_SYNCPT_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_CMD_WIN_B_INCR_SYNCPT_0_RESET_MASK _MK_MASK_CONST(0xffff) +#define DC_CMD_WIN_B_INCR_SYNCPT_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_CMD_WIN_B_INCR_SYNCPT_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_CMD_WIN_B_INCR_SYNCPT_0_READ_MASK _MK_MASK_CONST(0xffff) +#define DC_CMD_WIN_B_INCR_SYNCPT_0_WRITE_MASK _MK_MASK_CONST(0xffff) +#define DC_CMD_WIN_B_INCR_SYNCPT_0_WIN_B_COND_SHIFT _MK_SHIFT_CONST(8) +#define DC_CMD_WIN_B_INCR_SYNCPT_0_WIN_B_COND_FIELD _MK_FIELD_CONST(0xff, DC_CMD_WIN_B_INCR_SYNCPT_0_WIN_B_COND_SHIFT) +#define DC_CMD_WIN_B_INCR_SYNCPT_0_WIN_B_COND_RANGE 15:8 +#define DC_CMD_WIN_B_INCR_SYNCPT_0_WIN_B_COND_WOFFSET 0x0 +#define DC_CMD_WIN_B_INCR_SYNCPT_0_WIN_B_COND_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_WIN_B_INCR_SYNCPT_0_WIN_B_COND_DEFAULT_MASK _MK_MASK_CONST(0xff) +#define DC_CMD_WIN_B_INCR_SYNCPT_0_WIN_B_COND_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_WIN_B_INCR_SYNCPT_0_WIN_B_COND_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_CMD_WIN_B_INCR_SYNCPT_0_WIN_B_COND_IMMEDIATE _MK_ENUM_CONST(0) +#define DC_CMD_WIN_B_INCR_SYNCPT_0_WIN_B_COND_OP_DONE _MK_ENUM_CONST(1) +#define DC_CMD_WIN_B_INCR_SYNCPT_0_WIN_B_COND_RD_DONE _MK_ENUM_CONST(2) +#define DC_CMD_WIN_B_INCR_SYNCPT_0_WIN_B_COND_REG_WR_SAFE _MK_ENUM_CONST(3) +#define DC_CMD_WIN_B_INCR_SYNCPT_0_WIN_B_COND_COND_4 _MK_ENUM_CONST(4) +#define DC_CMD_WIN_B_INCR_SYNCPT_0_WIN_B_COND_COND_5 _MK_ENUM_CONST(5) +#define DC_CMD_WIN_B_INCR_SYNCPT_0_WIN_B_COND_COND_6 _MK_ENUM_CONST(6) +#define DC_CMD_WIN_B_INCR_SYNCPT_0_WIN_B_COND_COND_7 _MK_ENUM_CONST(7) +#define DC_CMD_WIN_B_INCR_SYNCPT_0_WIN_B_COND_COND_8 _MK_ENUM_CONST(8) +#define DC_CMD_WIN_B_INCR_SYNCPT_0_WIN_B_COND_COND_9 _MK_ENUM_CONST(9) +#define DC_CMD_WIN_B_INCR_SYNCPT_0_WIN_B_COND_COND_10 _MK_ENUM_CONST(10) +#define DC_CMD_WIN_B_INCR_SYNCPT_0_WIN_B_COND_COND_11 _MK_ENUM_CONST(11) +#define DC_CMD_WIN_B_INCR_SYNCPT_0_WIN_B_COND_COND_12 _MK_ENUM_CONST(12) +#define DC_CMD_WIN_B_INCR_SYNCPT_0_WIN_B_COND_COND_13 _MK_ENUM_CONST(13) +#define DC_CMD_WIN_B_INCR_SYNCPT_0_WIN_B_COND_COND_14 _MK_ENUM_CONST(14) +#define DC_CMD_WIN_B_INCR_SYNCPT_0_WIN_B_COND_COND_15 _MK_ENUM_CONST(15) +#define DC_CMD_WIN_B_INCR_SYNCPT_0_WIN_B_COND_COND_16 _MK_ENUM_CONST(16) +#define DC_CMD_WIN_B_INCR_SYNCPT_0_WIN_B_COND_COND_17 _MK_ENUM_CONST(17) +#define DC_CMD_WIN_B_INCR_SYNCPT_0_WIN_B_COND_COND_18 _MK_ENUM_CONST(18) +#define DC_CMD_WIN_B_INCR_SYNCPT_0_WIN_B_COND_COND_19 _MK_ENUM_CONST(19) +#define DC_CMD_WIN_B_INCR_SYNCPT_0_WIN_B_COND_COND_20 _MK_ENUM_CONST(20) +#define DC_CMD_WIN_B_INCR_SYNCPT_0_WIN_B_COND_COND_21 _MK_ENUM_CONST(21) +#define DC_CMD_WIN_B_INCR_SYNCPT_0_WIN_B_COND_COND_22 _MK_ENUM_CONST(22) +#define DC_CMD_WIN_B_INCR_SYNCPT_0_WIN_B_COND_COND_23 _MK_ENUM_CONST(23) +#define DC_CMD_WIN_B_INCR_SYNCPT_0_WIN_B_COND_COND_24 _MK_ENUM_CONST(24) +#define DC_CMD_WIN_B_INCR_SYNCPT_0_WIN_B_COND_COND_25 _MK_ENUM_CONST(25) +#define DC_CMD_WIN_B_INCR_SYNCPT_0_WIN_B_COND_COND_26 _MK_ENUM_CONST(26) +#define DC_CMD_WIN_B_INCR_SYNCPT_0_WIN_B_COND_COND_27 _MK_ENUM_CONST(27) +#define DC_CMD_WIN_B_INCR_SYNCPT_0_WIN_B_COND_COND_28 _MK_ENUM_CONST(28) +#define DC_CMD_WIN_B_INCR_SYNCPT_0_WIN_B_COND_COND_29 _MK_ENUM_CONST(29) +#define DC_CMD_WIN_B_INCR_SYNCPT_0_WIN_B_COND_COND_30 _MK_ENUM_CONST(30) +#define DC_CMD_WIN_B_INCR_SYNCPT_0_WIN_B_COND_COND_31 _MK_ENUM_CONST(31) + +#define DC_CMD_WIN_B_INCR_SYNCPT_0_WIN_B_INDX_SHIFT _MK_SHIFT_CONST(0) +#define DC_CMD_WIN_B_INCR_SYNCPT_0_WIN_B_INDX_FIELD _MK_FIELD_CONST(0xff, DC_CMD_WIN_B_INCR_SYNCPT_0_WIN_B_INDX_SHIFT) +#define DC_CMD_WIN_B_INCR_SYNCPT_0_WIN_B_INDX_RANGE 7:0 +#define DC_CMD_WIN_B_INCR_SYNCPT_0_WIN_B_INDX_WOFFSET 0x0 +#define DC_CMD_WIN_B_INCR_SYNCPT_0_WIN_B_INDX_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_WIN_B_INCR_SYNCPT_0_WIN_B_INDX_DEFAULT_MASK _MK_MASK_CONST(0xff) +#define DC_CMD_WIN_B_INCR_SYNCPT_0_WIN_B_INDX_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_WIN_B_INCR_SYNCPT_0_WIN_B_INDX_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_CMD_WIN_B_INCR_SYNCPT_CNTRL_0 +#define DC_CMD_WIN_B_INCR_SYNCPT_CNTRL_0 _MK_ADDR_CONST(0x11) +#define DC_CMD_WIN_B_INCR_SYNCPT_CNTRL_0_SECURE 0x0 +#define DC_CMD_WIN_B_INCR_SYNCPT_CNTRL_0_WORD_COUNT 0x1 +#define DC_CMD_WIN_B_INCR_SYNCPT_CNTRL_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_CMD_WIN_B_INCR_SYNCPT_CNTRL_0_RESET_MASK _MK_MASK_CONST(0x101) +#define DC_CMD_WIN_B_INCR_SYNCPT_CNTRL_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_CMD_WIN_B_INCR_SYNCPT_CNTRL_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_CMD_WIN_B_INCR_SYNCPT_CNTRL_0_READ_MASK _MK_MASK_CONST(0x101) +#define DC_CMD_WIN_B_INCR_SYNCPT_CNTRL_0_WRITE_MASK _MK_MASK_CONST(0x101) +#define DC_CMD_WIN_B_INCR_SYNCPT_CNTRL_0_WIN_B_INCR_SYNCPT_NO_STALL_SHIFT _MK_SHIFT_CONST(8) +#define DC_CMD_WIN_B_INCR_SYNCPT_CNTRL_0_WIN_B_INCR_SYNCPT_NO_STALL_FIELD _MK_FIELD_CONST(0x1, DC_CMD_WIN_B_INCR_SYNCPT_CNTRL_0_WIN_B_INCR_SYNCPT_NO_STALL_SHIFT) +#define DC_CMD_WIN_B_INCR_SYNCPT_CNTRL_0_WIN_B_INCR_SYNCPT_NO_STALL_RANGE 8:8 +#define DC_CMD_WIN_B_INCR_SYNCPT_CNTRL_0_WIN_B_INCR_SYNCPT_NO_STALL_WOFFSET 0x0 +#define DC_CMD_WIN_B_INCR_SYNCPT_CNTRL_0_WIN_B_INCR_SYNCPT_NO_STALL_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_WIN_B_INCR_SYNCPT_CNTRL_0_WIN_B_INCR_SYNCPT_NO_STALL_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_CMD_WIN_B_INCR_SYNCPT_CNTRL_0_WIN_B_INCR_SYNCPT_NO_STALL_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_WIN_B_INCR_SYNCPT_CNTRL_0_WIN_B_INCR_SYNCPT_NO_STALL_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_CMD_WIN_B_INCR_SYNCPT_CNTRL_0_WIN_B_INCR_SYNCPT_SOFT_RESET_SHIFT _MK_SHIFT_CONST(0) +#define DC_CMD_WIN_B_INCR_SYNCPT_CNTRL_0_WIN_B_INCR_SYNCPT_SOFT_RESET_FIELD _MK_FIELD_CONST(0x1, DC_CMD_WIN_B_INCR_SYNCPT_CNTRL_0_WIN_B_INCR_SYNCPT_SOFT_RESET_SHIFT) +#define DC_CMD_WIN_B_INCR_SYNCPT_CNTRL_0_WIN_B_INCR_SYNCPT_SOFT_RESET_RANGE 0:0 +#define DC_CMD_WIN_B_INCR_SYNCPT_CNTRL_0_WIN_B_INCR_SYNCPT_SOFT_RESET_WOFFSET 0x0 +#define DC_CMD_WIN_B_INCR_SYNCPT_CNTRL_0_WIN_B_INCR_SYNCPT_SOFT_RESET_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_WIN_B_INCR_SYNCPT_CNTRL_0_WIN_B_INCR_SYNCPT_SOFT_RESET_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_CMD_WIN_B_INCR_SYNCPT_CNTRL_0_WIN_B_INCR_SYNCPT_SOFT_RESET_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_WIN_B_INCR_SYNCPT_CNTRL_0_WIN_B_INCR_SYNCPT_SOFT_RESET_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_CMD_WIN_B_INCR_SYNCPT_ERROR_0 +#define DC_CMD_WIN_B_INCR_SYNCPT_ERROR_0 _MK_ADDR_CONST(0x12) +#define DC_CMD_WIN_B_INCR_SYNCPT_ERROR_0_SECURE 0x0 +#define DC_CMD_WIN_B_INCR_SYNCPT_ERROR_0_WORD_COUNT 0x1 +#define DC_CMD_WIN_B_INCR_SYNCPT_ERROR_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_CMD_WIN_B_INCR_SYNCPT_ERROR_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_CMD_WIN_B_INCR_SYNCPT_ERROR_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_CMD_WIN_B_INCR_SYNCPT_ERROR_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_CMD_WIN_B_INCR_SYNCPT_ERROR_0_READ_MASK _MK_MASK_CONST(0xffffffff) +#define DC_CMD_WIN_B_INCR_SYNCPT_ERROR_0_WRITE_MASK _MK_MASK_CONST(0xffffffff) +#define DC_CMD_WIN_B_INCR_SYNCPT_ERROR_0_WIN_B_COND_STATUS_SHIFT _MK_SHIFT_CONST(0) +#define DC_CMD_WIN_B_INCR_SYNCPT_ERROR_0_WIN_B_COND_STATUS_FIELD _MK_FIELD_CONST(0xffffffff, DC_CMD_WIN_B_INCR_SYNCPT_ERROR_0_WIN_B_COND_STATUS_SHIFT) +#define DC_CMD_WIN_B_INCR_SYNCPT_ERROR_0_WIN_B_COND_STATUS_RANGE 31:0 +#define DC_CMD_WIN_B_INCR_SYNCPT_ERROR_0_WIN_B_COND_STATUS_WOFFSET 0x0 +#define DC_CMD_WIN_B_INCR_SYNCPT_ERROR_0_WIN_B_COND_STATUS_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_WIN_B_INCR_SYNCPT_ERROR_0_WIN_B_COND_STATUS_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_CMD_WIN_B_INCR_SYNCPT_ERROR_0_WIN_B_COND_STATUS_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_WIN_B_INCR_SYNCPT_ERROR_0_WIN_B_COND_STATUS_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Reserved address 19 [0x13] + +// Reserved address 20 [0x14] + +// Reserved address 21 [0x15] + +// Reserved address 22 [0x16] + +// Reserved address 23 [0x17] +#define NV_DISPLAY_WIN_C_INCR_SYNCPT_NB_CONDS 4 + +// Register DC_CMD_WIN_C_INCR_SYNCPT_0 +#define DC_CMD_WIN_C_INCR_SYNCPT_0 _MK_ADDR_CONST(0x18) +#define DC_CMD_WIN_C_INCR_SYNCPT_0_SECURE 0x0 +#define DC_CMD_WIN_C_INCR_SYNCPT_0_WORD_COUNT 0x1 +#define DC_CMD_WIN_C_INCR_SYNCPT_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_CMD_WIN_C_INCR_SYNCPT_0_RESET_MASK _MK_MASK_CONST(0xffff) +#define DC_CMD_WIN_C_INCR_SYNCPT_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_CMD_WIN_C_INCR_SYNCPT_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_CMD_WIN_C_INCR_SYNCPT_0_READ_MASK _MK_MASK_CONST(0xffff) +#define DC_CMD_WIN_C_INCR_SYNCPT_0_WRITE_MASK _MK_MASK_CONST(0xffff) +#define DC_CMD_WIN_C_INCR_SYNCPT_0_WIN_C_COND_SHIFT _MK_SHIFT_CONST(8) +#define DC_CMD_WIN_C_INCR_SYNCPT_0_WIN_C_COND_FIELD _MK_FIELD_CONST(0xff, DC_CMD_WIN_C_INCR_SYNCPT_0_WIN_C_COND_SHIFT) +#define DC_CMD_WIN_C_INCR_SYNCPT_0_WIN_C_COND_RANGE 15:8 +#define DC_CMD_WIN_C_INCR_SYNCPT_0_WIN_C_COND_WOFFSET 0x0 +#define DC_CMD_WIN_C_INCR_SYNCPT_0_WIN_C_COND_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_WIN_C_INCR_SYNCPT_0_WIN_C_COND_DEFAULT_MASK _MK_MASK_CONST(0xff) +#define DC_CMD_WIN_C_INCR_SYNCPT_0_WIN_C_COND_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_WIN_C_INCR_SYNCPT_0_WIN_C_COND_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_CMD_WIN_C_INCR_SYNCPT_0_WIN_C_COND_IMMEDIATE _MK_ENUM_CONST(0) +#define DC_CMD_WIN_C_INCR_SYNCPT_0_WIN_C_COND_OP_DONE _MK_ENUM_CONST(1) +#define DC_CMD_WIN_C_INCR_SYNCPT_0_WIN_C_COND_RD_DONE _MK_ENUM_CONST(2) +#define DC_CMD_WIN_C_INCR_SYNCPT_0_WIN_C_COND_REG_WR_SAFE _MK_ENUM_CONST(3) +#define DC_CMD_WIN_C_INCR_SYNCPT_0_WIN_C_COND_COND_4 _MK_ENUM_CONST(4) +#define DC_CMD_WIN_C_INCR_SYNCPT_0_WIN_C_COND_COND_5 _MK_ENUM_CONST(5) +#define DC_CMD_WIN_C_INCR_SYNCPT_0_WIN_C_COND_COND_6 _MK_ENUM_CONST(6) +#define DC_CMD_WIN_C_INCR_SYNCPT_0_WIN_C_COND_COND_7 _MK_ENUM_CONST(7) +#define DC_CMD_WIN_C_INCR_SYNCPT_0_WIN_C_COND_COND_8 _MK_ENUM_CONST(8) +#define DC_CMD_WIN_C_INCR_SYNCPT_0_WIN_C_COND_COND_9 _MK_ENUM_CONST(9) +#define DC_CMD_WIN_C_INCR_SYNCPT_0_WIN_C_COND_COND_10 _MK_ENUM_CONST(10) +#define DC_CMD_WIN_C_INCR_SYNCPT_0_WIN_C_COND_COND_11 _MK_ENUM_CONST(11) +#define DC_CMD_WIN_C_INCR_SYNCPT_0_WIN_C_COND_COND_12 _MK_ENUM_CONST(12) +#define DC_CMD_WIN_C_INCR_SYNCPT_0_WIN_C_COND_COND_13 _MK_ENUM_CONST(13) +#define DC_CMD_WIN_C_INCR_SYNCPT_0_WIN_C_COND_COND_14 _MK_ENUM_CONST(14) +#define DC_CMD_WIN_C_INCR_SYNCPT_0_WIN_C_COND_COND_15 _MK_ENUM_CONST(15) +#define DC_CMD_WIN_C_INCR_SYNCPT_0_WIN_C_COND_COND_16 _MK_ENUM_CONST(16) +#define DC_CMD_WIN_C_INCR_SYNCPT_0_WIN_C_COND_COND_17 _MK_ENUM_CONST(17) +#define DC_CMD_WIN_C_INCR_SYNCPT_0_WIN_C_COND_COND_18 _MK_ENUM_CONST(18) +#define DC_CMD_WIN_C_INCR_SYNCPT_0_WIN_C_COND_COND_19 _MK_ENUM_CONST(19) +#define DC_CMD_WIN_C_INCR_SYNCPT_0_WIN_C_COND_COND_20 _MK_ENUM_CONST(20) +#define DC_CMD_WIN_C_INCR_SYNCPT_0_WIN_C_COND_COND_21 _MK_ENUM_CONST(21) +#define DC_CMD_WIN_C_INCR_SYNCPT_0_WIN_C_COND_COND_22 _MK_ENUM_CONST(22) +#define DC_CMD_WIN_C_INCR_SYNCPT_0_WIN_C_COND_COND_23 _MK_ENUM_CONST(23) +#define DC_CMD_WIN_C_INCR_SYNCPT_0_WIN_C_COND_COND_24 _MK_ENUM_CONST(24) +#define DC_CMD_WIN_C_INCR_SYNCPT_0_WIN_C_COND_COND_25 _MK_ENUM_CONST(25) +#define DC_CMD_WIN_C_INCR_SYNCPT_0_WIN_C_COND_COND_26 _MK_ENUM_CONST(26) +#define DC_CMD_WIN_C_INCR_SYNCPT_0_WIN_C_COND_COND_27 _MK_ENUM_CONST(27) +#define DC_CMD_WIN_C_INCR_SYNCPT_0_WIN_C_COND_COND_28 _MK_ENUM_CONST(28) +#define DC_CMD_WIN_C_INCR_SYNCPT_0_WIN_C_COND_COND_29 _MK_ENUM_CONST(29) +#define DC_CMD_WIN_C_INCR_SYNCPT_0_WIN_C_COND_COND_30 _MK_ENUM_CONST(30) +#define DC_CMD_WIN_C_INCR_SYNCPT_0_WIN_C_COND_COND_31 _MK_ENUM_CONST(31) + +#define DC_CMD_WIN_C_INCR_SYNCPT_0_WIN_C_INDX_SHIFT _MK_SHIFT_CONST(0) +#define DC_CMD_WIN_C_INCR_SYNCPT_0_WIN_C_INDX_FIELD _MK_FIELD_CONST(0xff, DC_CMD_WIN_C_INCR_SYNCPT_0_WIN_C_INDX_SHIFT) +#define DC_CMD_WIN_C_INCR_SYNCPT_0_WIN_C_INDX_RANGE 7:0 +#define DC_CMD_WIN_C_INCR_SYNCPT_0_WIN_C_INDX_WOFFSET 0x0 +#define DC_CMD_WIN_C_INCR_SYNCPT_0_WIN_C_INDX_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_WIN_C_INCR_SYNCPT_0_WIN_C_INDX_DEFAULT_MASK _MK_MASK_CONST(0xff) +#define DC_CMD_WIN_C_INCR_SYNCPT_0_WIN_C_INDX_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_WIN_C_INCR_SYNCPT_0_WIN_C_INDX_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_CMD_WIN_C_INCR_SYNCPT_CNTRL_0 +#define DC_CMD_WIN_C_INCR_SYNCPT_CNTRL_0 _MK_ADDR_CONST(0x19) +#define DC_CMD_WIN_C_INCR_SYNCPT_CNTRL_0_SECURE 0x0 +#define DC_CMD_WIN_C_INCR_SYNCPT_CNTRL_0_WORD_COUNT 0x1 +#define DC_CMD_WIN_C_INCR_SYNCPT_CNTRL_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_CMD_WIN_C_INCR_SYNCPT_CNTRL_0_RESET_MASK _MK_MASK_CONST(0x101) +#define DC_CMD_WIN_C_INCR_SYNCPT_CNTRL_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_CMD_WIN_C_INCR_SYNCPT_CNTRL_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_CMD_WIN_C_INCR_SYNCPT_CNTRL_0_READ_MASK _MK_MASK_CONST(0x101) +#define DC_CMD_WIN_C_INCR_SYNCPT_CNTRL_0_WRITE_MASK _MK_MASK_CONST(0x101) +#define DC_CMD_WIN_C_INCR_SYNCPT_CNTRL_0_WIN_C_INCR_SYNCPT_NO_STALL_SHIFT _MK_SHIFT_CONST(8) +#define DC_CMD_WIN_C_INCR_SYNCPT_CNTRL_0_WIN_C_INCR_SYNCPT_NO_STALL_FIELD _MK_FIELD_CONST(0x1, DC_CMD_WIN_C_INCR_SYNCPT_CNTRL_0_WIN_C_INCR_SYNCPT_NO_STALL_SHIFT) +#define DC_CMD_WIN_C_INCR_SYNCPT_CNTRL_0_WIN_C_INCR_SYNCPT_NO_STALL_RANGE 8:8 +#define DC_CMD_WIN_C_INCR_SYNCPT_CNTRL_0_WIN_C_INCR_SYNCPT_NO_STALL_WOFFSET 0x0 +#define DC_CMD_WIN_C_INCR_SYNCPT_CNTRL_0_WIN_C_INCR_SYNCPT_NO_STALL_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_WIN_C_INCR_SYNCPT_CNTRL_0_WIN_C_INCR_SYNCPT_NO_STALL_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_CMD_WIN_C_INCR_SYNCPT_CNTRL_0_WIN_C_INCR_SYNCPT_NO_STALL_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_WIN_C_INCR_SYNCPT_CNTRL_0_WIN_C_INCR_SYNCPT_NO_STALL_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_CMD_WIN_C_INCR_SYNCPT_CNTRL_0_WIN_C_INCR_SYNCPT_SOFT_RESET_SHIFT _MK_SHIFT_CONST(0) +#define DC_CMD_WIN_C_INCR_SYNCPT_CNTRL_0_WIN_C_INCR_SYNCPT_SOFT_RESET_FIELD _MK_FIELD_CONST(0x1, DC_CMD_WIN_C_INCR_SYNCPT_CNTRL_0_WIN_C_INCR_SYNCPT_SOFT_RESET_SHIFT) +#define DC_CMD_WIN_C_INCR_SYNCPT_CNTRL_0_WIN_C_INCR_SYNCPT_SOFT_RESET_RANGE 0:0 +#define DC_CMD_WIN_C_INCR_SYNCPT_CNTRL_0_WIN_C_INCR_SYNCPT_SOFT_RESET_WOFFSET 0x0 +#define DC_CMD_WIN_C_INCR_SYNCPT_CNTRL_0_WIN_C_INCR_SYNCPT_SOFT_RESET_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_WIN_C_INCR_SYNCPT_CNTRL_0_WIN_C_INCR_SYNCPT_SOFT_RESET_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_CMD_WIN_C_INCR_SYNCPT_CNTRL_0_WIN_C_INCR_SYNCPT_SOFT_RESET_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_WIN_C_INCR_SYNCPT_CNTRL_0_WIN_C_INCR_SYNCPT_SOFT_RESET_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_CMD_WIN_C_INCR_SYNCPT_ERROR_0 +#define DC_CMD_WIN_C_INCR_SYNCPT_ERROR_0 _MK_ADDR_CONST(0x1a) +#define DC_CMD_WIN_C_INCR_SYNCPT_ERROR_0_SECURE 0x0 +#define DC_CMD_WIN_C_INCR_SYNCPT_ERROR_0_WORD_COUNT 0x1 +#define DC_CMD_WIN_C_INCR_SYNCPT_ERROR_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_CMD_WIN_C_INCR_SYNCPT_ERROR_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_CMD_WIN_C_INCR_SYNCPT_ERROR_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_CMD_WIN_C_INCR_SYNCPT_ERROR_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_CMD_WIN_C_INCR_SYNCPT_ERROR_0_READ_MASK _MK_MASK_CONST(0xffffffff) +#define DC_CMD_WIN_C_INCR_SYNCPT_ERROR_0_WRITE_MASK _MK_MASK_CONST(0xffffffff) +#define DC_CMD_WIN_C_INCR_SYNCPT_ERROR_0_WIN_C_COND_STATUS_SHIFT _MK_SHIFT_CONST(0) +#define DC_CMD_WIN_C_INCR_SYNCPT_ERROR_0_WIN_C_COND_STATUS_FIELD _MK_FIELD_CONST(0xffffffff, DC_CMD_WIN_C_INCR_SYNCPT_ERROR_0_WIN_C_COND_STATUS_SHIFT) +#define DC_CMD_WIN_C_INCR_SYNCPT_ERROR_0_WIN_C_COND_STATUS_RANGE 31:0 +#define DC_CMD_WIN_C_INCR_SYNCPT_ERROR_0_WIN_C_COND_STATUS_WOFFSET 0x0 +#define DC_CMD_WIN_C_INCR_SYNCPT_ERROR_0_WIN_C_COND_STATUS_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_WIN_C_INCR_SYNCPT_ERROR_0_WIN_C_COND_STATUS_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_CMD_WIN_C_INCR_SYNCPT_ERROR_0_WIN_C_COND_STATUS_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_WIN_C_INCR_SYNCPT_ERROR_0_WIN_C_COND_STATUS_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Reserved address 27 [0x1b] + +// Reserved address 28 [0x1c] + +// Reserved address 29 [0x1d] + +// Reserved address 30 [0x1e] + +// Reserved address 31 [0x1f] + +// Reserved address 32 [0x20] + +// Reserved address 33 [0x21] + +// Reserved address 34 [0x22] + +// Reserved address 35 [0x23] + +// Reserved address 36 [0x24] + +// Reserved address 37 [0x25] + +// Reserved address 38 [0x26] + +// Reserved address 39 [0x27] + +// Register DC_CMD_CONT_SYNCPT_VSYNC_0 +#define DC_CMD_CONT_SYNCPT_VSYNC_0 _MK_ADDR_CONST(0x28) +#define DC_CMD_CONT_SYNCPT_VSYNC_0_SECURE 0x0 +#define DC_CMD_CONT_SYNCPT_VSYNC_0_WORD_COUNT 0x1 +#define DC_CMD_CONT_SYNCPT_VSYNC_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_CMD_CONT_SYNCPT_VSYNC_0_RESET_MASK _MK_MASK_CONST(0x100) +#define DC_CMD_CONT_SYNCPT_VSYNC_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_CMD_CONT_SYNCPT_VSYNC_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_CMD_CONT_SYNCPT_VSYNC_0_READ_MASK _MK_MASK_CONST(0x1ff) +#define DC_CMD_CONT_SYNCPT_VSYNC_0_WRITE_MASK _MK_MASK_CONST(0x1ff) +#define DC_CMD_CONT_SYNCPT_VSYNC_0_VSYNC_INDX_SHIFT _MK_SHIFT_CONST(0) +#define DC_CMD_CONT_SYNCPT_VSYNC_0_VSYNC_INDX_FIELD _MK_FIELD_CONST(0xff, DC_CMD_CONT_SYNCPT_VSYNC_0_VSYNC_INDX_SHIFT) +#define DC_CMD_CONT_SYNCPT_VSYNC_0_VSYNC_INDX_RANGE 7:0 +#define DC_CMD_CONT_SYNCPT_VSYNC_0_VSYNC_INDX_WOFFSET 0x0 +#define DC_CMD_CONT_SYNCPT_VSYNC_0_VSYNC_INDX_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_CONT_SYNCPT_VSYNC_0_VSYNC_INDX_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_CMD_CONT_SYNCPT_VSYNC_0_VSYNC_INDX_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_CONT_SYNCPT_VSYNC_0_VSYNC_INDX_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_CMD_CONT_SYNCPT_VSYNC_0_VSYNC_EN_SHIFT _MK_SHIFT_CONST(8) +#define DC_CMD_CONT_SYNCPT_VSYNC_0_VSYNC_EN_FIELD _MK_FIELD_CONST(0x1, DC_CMD_CONT_SYNCPT_VSYNC_0_VSYNC_EN_SHIFT) +#define DC_CMD_CONT_SYNCPT_VSYNC_0_VSYNC_EN_RANGE 8:8 +#define DC_CMD_CONT_SYNCPT_VSYNC_0_VSYNC_EN_WOFFSET 0x0 +#define DC_CMD_CONT_SYNCPT_VSYNC_0_VSYNC_EN_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_CONT_SYNCPT_VSYNC_0_VSYNC_EN_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_CMD_CONT_SYNCPT_VSYNC_0_VSYNC_EN_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_CONT_SYNCPT_VSYNC_0_VSYNC_EN_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_CMD_CONT_SYNCPT_VSYNC_0_VSYNC_EN_DISABLE _MK_ENUM_CONST(0) +#define DC_CMD_CONT_SYNCPT_VSYNC_0_VSYNC_EN_ENABLE _MK_ENUM_CONST(1) + + +// Register DC_CMD_CTXSW_0 +#define DC_CMD_CTXSW_0 _MK_ADDR_CONST(0x30) +#define DC_CMD_CTXSW_0_SECURE 0x0 +#define DC_CMD_CTXSW_0_WORD_COUNT 0x1 +#define DC_CMD_CTXSW_0_RESET_VAL _MK_MASK_CONST(0xf000f800) +#define DC_CMD_CTXSW_0_RESET_MASK _MK_MASK_CONST(0xf3fffbff) +#define DC_CMD_CTXSW_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_CMD_CTXSW_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_CMD_CTXSW_0_READ_MASK _MK_MASK_CONST(0xf3fffbff) +#define DC_CMD_CTXSW_0_WRITE_MASK _MK_MASK_CONST(0xfbff) +#define DC_CMD_CTXSW_0_CURR_CLASS_SHIFT _MK_SHIFT_CONST(0) +#define DC_CMD_CTXSW_0_CURR_CLASS_FIELD _MK_FIELD_CONST(0x3ff, DC_CMD_CTXSW_0_CURR_CLASS_SHIFT) +#define DC_CMD_CTXSW_0_CURR_CLASS_RANGE 9:0 +#define DC_CMD_CTXSW_0_CURR_CLASS_WOFFSET 0x0 +#define DC_CMD_CTXSW_0_CURR_CLASS_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_CTXSW_0_CURR_CLASS_DEFAULT_MASK _MK_MASK_CONST(0x3ff) +#define DC_CMD_CTXSW_0_CURR_CLASS_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_CTXSW_0_CURR_CLASS_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_CMD_CTXSW_0_AUTO_ACK_SHIFT _MK_SHIFT_CONST(11) +#define DC_CMD_CTXSW_0_AUTO_ACK_FIELD _MK_FIELD_CONST(0x1, DC_CMD_CTXSW_0_AUTO_ACK_SHIFT) +#define DC_CMD_CTXSW_0_AUTO_ACK_RANGE 11:11 +#define DC_CMD_CTXSW_0_AUTO_ACK_WOFFSET 0x0 +#define DC_CMD_CTXSW_0_AUTO_ACK_DEFAULT _MK_MASK_CONST(0x1) +#define DC_CMD_CTXSW_0_AUTO_ACK_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_CMD_CTXSW_0_AUTO_ACK_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_CTXSW_0_AUTO_ACK_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_CMD_CTXSW_0_AUTO_ACK_MANUAL _MK_ENUM_CONST(0) +#define DC_CMD_CTXSW_0_AUTO_ACK_AUTOACK _MK_ENUM_CONST(1) + +#define DC_CMD_CTXSW_0_CURR_CHANNEL_SHIFT _MK_SHIFT_CONST(12) +#define DC_CMD_CTXSW_0_CURR_CHANNEL_FIELD _MK_FIELD_CONST(0xf, DC_CMD_CTXSW_0_CURR_CHANNEL_SHIFT) +#define DC_CMD_CTXSW_0_CURR_CHANNEL_RANGE 15:12 +#define DC_CMD_CTXSW_0_CURR_CHANNEL_WOFFSET 0x0 +#define DC_CMD_CTXSW_0_CURR_CHANNEL_DEFAULT _MK_MASK_CONST(0xf) +#define DC_CMD_CTXSW_0_CURR_CHANNEL_DEFAULT_MASK _MK_MASK_CONST(0xf) +#define DC_CMD_CTXSW_0_CURR_CHANNEL_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_CTXSW_0_CURR_CHANNEL_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_CMD_CTXSW_0_NEXT_CLASS_SHIFT _MK_SHIFT_CONST(16) +#define DC_CMD_CTXSW_0_NEXT_CLASS_FIELD _MK_FIELD_CONST(0x3ff, DC_CMD_CTXSW_0_NEXT_CLASS_SHIFT) +#define DC_CMD_CTXSW_0_NEXT_CLASS_RANGE 25:16 +#define DC_CMD_CTXSW_0_NEXT_CLASS_WOFFSET 0x0 +#define DC_CMD_CTXSW_0_NEXT_CLASS_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_CTXSW_0_NEXT_CLASS_DEFAULT_MASK _MK_MASK_CONST(0x3ff) +#define DC_CMD_CTXSW_0_NEXT_CLASS_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_CTXSW_0_NEXT_CLASS_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_CMD_CTXSW_0_NEXT_CHANNEL_SHIFT _MK_SHIFT_CONST(28) +#define DC_CMD_CTXSW_0_NEXT_CHANNEL_FIELD _MK_FIELD_CONST(0xf, DC_CMD_CTXSW_0_NEXT_CHANNEL_SHIFT) +#define DC_CMD_CTXSW_0_NEXT_CHANNEL_RANGE 31:28 +#define DC_CMD_CTXSW_0_NEXT_CHANNEL_WOFFSET 0x0 +#define DC_CMD_CTXSW_0_NEXT_CHANNEL_DEFAULT _MK_MASK_CONST(0xf) +#define DC_CMD_CTXSW_0_NEXT_CHANNEL_DEFAULT_MASK _MK_MASK_CONST(0xf) +#define DC_CMD_CTXSW_0_NEXT_CHANNEL_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_CTXSW_0_NEXT_CHANNEL_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_CMD_DISPLAY_COMMAND_OPTION0_0 +#define DC_CMD_DISPLAY_COMMAND_OPTION0_0 _MK_ADDR_CONST(0x31) +#define DC_CMD_DISPLAY_COMMAND_OPTION0_0_SECURE 0x0 +#define DC_CMD_DISPLAY_COMMAND_OPTION0_0_WORD_COUNT 0x1 +#define DC_CMD_DISPLAY_COMMAND_OPTION0_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_CMD_DISPLAY_COMMAND_OPTION0_0_RESET_MASK _MK_MASK_CONST(0x700ff) +#define DC_CMD_DISPLAY_COMMAND_OPTION0_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_CMD_DISPLAY_COMMAND_OPTION0_0_SW_DEFAULT_MASK _MK_MASK_CONST(0xc) +#define DC_CMD_DISPLAY_COMMAND_OPTION0_0_READ_MASK _MK_MASK_CONST(0x700ff) +#define DC_CMD_DISPLAY_COMMAND_OPTION0_0_WRITE_MASK _MK_MASK_CONST(0x700ff) +#define DC_CMD_DISPLAY_COMMAND_OPTION0_0_MSF_POLARITY_SHIFT _MK_SHIFT_CONST(0) +#define DC_CMD_DISPLAY_COMMAND_OPTION0_0_MSF_POLARITY_FIELD _MK_FIELD_CONST(0x1, DC_CMD_DISPLAY_COMMAND_OPTION0_0_MSF_POLARITY_SHIFT) +#define DC_CMD_DISPLAY_COMMAND_OPTION0_0_MSF_POLARITY_RANGE 0:0 +#define DC_CMD_DISPLAY_COMMAND_OPTION0_0_MSF_POLARITY_WOFFSET 0x0 +#define DC_CMD_DISPLAY_COMMAND_OPTION0_0_MSF_POLARITY_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_DISPLAY_COMMAND_OPTION0_0_MSF_POLARITY_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_CMD_DISPLAY_COMMAND_OPTION0_0_MSF_POLARITY_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_DISPLAY_COMMAND_OPTION0_0_MSF_POLARITY_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_CMD_DISPLAY_COMMAND_OPTION0_0_MSF_ENABLE_SHIFT _MK_SHIFT_CONST(1) +#define DC_CMD_DISPLAY_COMMAND_OPTION0_0_MSF_ENABLE_FIELD _MK_FIELD_CONST(0x1, DC_CMD_DISPLAY_COMMAND_OPTION0_0_MSF_ENABLE_SHIFT) +#define DC_CMD_DISPLAY_COMMAND_OPTION0_0_MSF_ENABLE_RANGE 1:1 +#define DC_CMD_DISPLAY_COMMAND_OPTION0_0_MSF_ENABLE_WOFFSET 0x0 +#define DC_CMD_DISPLAY_COMMAND_OPTION0_0_MSF_ENABLE_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_DISPLAY_COMMAND_OPTION0_0_MSF_ENABLE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_CMD_DISPLAY_COMMAND_OPTION0_0_MSF_ENABLE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_DISPLAY_COMMAND_OPTION0_0_MSF_ENABLE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_CMD_DISPLAY_COMMAND_OPTION0_0_MSF_ENABLE_DISABLE _MK_ENUM_CONST(0) +#define DC_CMD_DISPLAY_COMMAND_OPTION0_0_MSF_ENABLE_ENABLE _MK_ENUM_CONST(1) + +#define DC_CMD_DISPLAY_COMMAND_OPTION0_0_MSF_SOURCE_SHIFT _MK_SHIFT_CONST(2) +#define DC_CMD_DISPLAY_COMMAND_OPTION0_0_MSF_SOURCE_FIELD _MK_FIELD_CONST(0x3, DC_CMD_DISPLAY_COMMAND_OPTION0_0_MSF_SOURCE_SHIFT) +#define DC_CMD_DISPLAY_COMMAND_OPTION0_0_MSF_SOURCE_RANGE 3:2 +#define DC_CMD_DISPLAY_COMMAND_OPTION0_0_MSF_SOURCE_WOFFSET 0x0 +#define DC_CMD_DISPLAY_COMMAND_OPTION0_0_MSF_SOURCE_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_DISPLAY_COMMAND_OPTION0_0_MSF_SOURCE_DEFAULT_MASK _MK_MASK_CONST(0x3) +#define DC_CMD_DISPLAY_COMMAND_OPTION0_0_MSF_SOURCE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_DISPLAY_COMMAND_OPTION0_0_MSF_SOURCE_SW_DEFAULT_MASK _MK_MASK_CONST(0x3) +#define DC_CMD_DISPLAY_COMMAND_OPTION0_0_MSF_SOURCE_MSF_LSPI _MK_ENUM_CONST(0) +#define DC_CMD_DISPLAY_COMMAND_OPTION0_0_MSF_SOURCE_MSF_LDC _MK_ENUM_CONST(1) +#define DC_CMD_DISPLAY_COMMAND_OPTION0_0_MSF_SOURCE_MSF_LSDI _MK_ENUM_CONST(2) + +#define DC_CMD_DISPLAY_COMMAND_OPTION0_0_SSF_POLARITY_SHIFT _MK_SHIFT_CONST(4) +#define DC_CMD_DISPLAY_COMMAND_OPTION0_0_SSF_POLARITY_FIELD _MK_FIELD_CONST(0x1, DC_CMD_DISPLAY_COMMAND_OPTION0_0_SSF_POLARITY_SHIFT) +#define DC_CMD_DISPLAY_COMMAND_OPTION0_0_SSF_POLARITY_RANGE 4:4 +#define DC_CMD_DISPLAY_COMMAND_OPTION0_0_SSF_POLARITY_WOFFSET 0x0 +#define DC_CMD_DISPLAY_COMMAND_OPTION0_0_SSF_POLARITY_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_DISPLAY_COMMAND_OPTION0_0_SSF_POLARITY_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_CMD_DISPLAY_COMMAND_OPTION0_0_SSF_POLARITY_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_DISPLAY_COMMAND_OPTION0_0_SSF_POLARITY_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_CMD_DISPLAY_COMMAND_OPTION0_0_SSF_ENABLE_SHIFT _MK_SHIFT_CONST(5) +#define DC_CMD_DISPLAY_COMMAND_OPTION0_0_SSF_ENABLE_FIELD _MK_FIELD_CONST(0x1, DC_CMD_DISPLAY_COMMAND_OPTION0_0_SSF_ENABLE_SHIFT) +#define DC_CMD_DISPLAY_COMMAND_OPTION0_0_SSF_ENABLE_RANGE 5:5 +#define DC_CMD_DISPLAY_COMMAND_OPTION0_0_SSF_ENABLE_WOFFSET 0x0 +#define DC_CMD_DISPLAY_COMMAND_OPTION0_0_SSF_ENABLE_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_DISPLAY_COMMAND_OPTION0_0_SSF_ENABLE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_CMD_DISPLAY_COMMAND_OPTION0_0_SSF_ENABLE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_DISPLAY_COMMAND_OPTION0_0_SSF_ENABLE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_CMD_DISPLAY_COMMAND_OPTION0_0_SSF_ENABLE_DISABLE _MK_ENUM_CONST(0) +#define DC_CMD_DISPLAY_COMMAND_OPTION0_0_SSF_ENABLE_ENABLE _MK_ENUM_CONST(1) + +#define DC_CMD_DISPLAY_COMMAND_OPTION0_0_SSF_SOURCE_SHIFT _MK_SHIFT_CONST(6) +#define DC_CMD_DISPLAY_COMMAND_OPTION0_0_SSF_SOURCE_FIELD _MK_FIELD_CONST(0x3, DC_CMD_DISPLAY_COMMAND_OPTION0_0_SSF_SOURCE_SHIFT) +#define DC_CMD_DISPLAY_COMMAND_OPTION0_0_SSF_SOURCE_RANGE 7:6 +#define DC_CMD_DISPLAY_COMMAND_OPTION0_0_SSF_SOURCE_WOFFSET 0x0 +#define DC_CMD_DISPLAY_COMMAND_OPTION0_0_SSF_SOURCE_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_DISPLAY_COMMAND_OPTION0_0_SSF_SOURCE_DEFAULT_MASK _MK_MASK_CONST(0x3) +#define DC_CMD_DISPLAY_COMMAND_OPTION0_0_SSF_SOURCE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_DISPLAY_COMMAND_OPTION0_0_SSF_SOURCE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_CMD_DISPLAY_COMMAND_OPTION0_0_SSF_SOURCE_SSF_LDC _MK_ENUM_CONST(0) +#define DC_CMD_DISPLAY_COMMAND_OPTION0_0_SSF_SOURCE_SSF_LSPI _MK_ENUM_CONST(1) +#define DC_CMD_DISPLAY_COMMAND_OPTION0_0_SSF_SOURCE_SSF_LSDI _MK_ENUM_CONST(2) + +#define DC_CMD_DISPLAY_COMMAND_OPTION0_0_WINDOW_A_NC_DISPLAY_SHIFT _MK_SHIFT_CONST(16) +#define DC_CMD_DISPLAY_COMMAND_OPTION0_0_WINDOW_A_NC_DISPLAY_FIELD _MK_FIELD_CONST(0x1, DC_CMD_DISPLAY_COMMAND_OPTION0_0_WINDOW_A_NC_DISPLAY_SHIFT) +#define DC_CMD_DISPLAY_COMMAND_OPTION0_0_WINDOW_A_NC_DISPLAY_RANGE 16:16 +#define DC_CMD_DISPLAY_COMMAND_OPTION0_0_WINDOW_A_NC_DISPLAY_WOFFSET 0x0 +#define DC_CMD_DISPLAY_COMMAND_OPTION0_0_WINDOW_A_NC_DISPLAY_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_DISPLAY_COMMAND_OPTION0_0_WINDOW_A_NC_DISPLAY_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_CMD_DISPLAY_COMMAND_OPTION0_0_WINDOW_A_NC_DISPLAY_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_DISPLAY_COMMAND_OPTION0_0_WINDOW_A_NC_DISPLAY_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_CMD_DISPLAY_COMMAND_OPTION0_0_WINDOW_A_NC_DISPLAY_DISABLE _MK_ENUM_CONST(0) +#define DC_CMD_DISPLAY_COMMAND_OPTION0_0_WINDOW_A_NC_DISPLAY_ENABLE _MK_ENUM_CONST(1) + +#define DC_CMD_DISPLAY_COMMAND_OPTION0_0_WINDOW_B_NC_DISPLAY_SHIFT _MK_SHIFT_CONST(17) +#define DC_CMD_DISPLAY_COMMAND_OPTION0_0_WINDOW_B_NC_DISPLAY_FIELD _MK_FIELD_CONST(0x1, DC_CMD_DISPLAY_COMMAND_OPTION0_0_WINDOW_B_NC_DISPLAY_SHIFT) +#define DC_CMD_DISPLAY_COMMAND_OPTION0_0_WINDOW_B_NC_DISPLAY_RANGE 17:17 +#define DC_CMD_DISPLAY_COMMAND_OPTION0_0_WINDOW_B_NC_DISPLAY_WOFFSET 0x0 +#define DC_CMD_DISPLAY_COMMAND_OPTION0_0_WINDOW_B_NC_DISPLAY_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_DISPLAY_COMMAND_OPTION0_0_WINDOW_B_NC_DISPLAY_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_CMD_DISPLAY_COMMAND_OPTION0_0_WINDOW_B_NC_DISPLAY_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_DISPLAY_COMMAND_OPTION0_0_WINDOW_B_NC_DISPLAY_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_CMD_DISPLAY_COMMAND_OPTION0_0_WINDOW_B_NC_DISPLAY_DISABLE _MK_ENUM_CONST(0) +#define DC_CMD_DISPLAY_COMMAND_OPTION0_0_WINDOW_B_NC_DISPLAY_ENABLE _MK_ENUM_CONST(1) + +#define DC_CMD_DISPLAY_COMMAND_OPTION0_0_WINDOW_C_NC_DISPLAY_SHIFT _MK_SHIFT_CONST(18) +#define DC_CMD_DISPLAY_COMMAND_OPTION0_0_WINDOW_C_NC_DISPLAY_FIELD _MK_FIELD_CONST(0x1, DC_CMD_DISPLAY_COMMAND_OPTION0_0_WINDOW_C_NC_DISPLAY_SHIFT) +#define DC_CMD_DISPLAY_COMMAND_OPTION0_0_WINDOW_C_NC_DISPLAY_RANGE 18:18 +#define DC_CMD_DISPLAY_COMMAND_OPTION0_0_WINDOW_C_NC_DISPLAY_WOFFSET 0x0 +#define DC_CMD_DISPLAY_COMMAND_OPTION0_0_WINDOW_C_NC_DISPLAY_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_DISPLAY_COMMAND_OPTION0_0_WINDOW_C_NC_DISPLAY_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_CMD_DISPLAY_COMMAND_OPTION0_0_WINDOW_C_NC_DISPLAY_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_DISPLAY_COMMAND_OPTION0_0_WINDOW_C_NC_DISPLAY_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_CMD_DISPLAY_COMMAND_OPTION0_0_WINDOW_C_NC_DISPLAY_DISABLE _MK_ENUM_CONST(0) +#define DC_CMD_DISPLAY_COMMAND_OPTION0_0_WINDOW_C_NC_DISPLAY_ENABLE _MK_ENUM_CONST(1) + + +// Register DC_CMD_DISPLAY_COMMAND_0 +#define DC_CMD_DISPLAY_COMMAND_0 _MK_ADDR_CONST(0x32) +#define DC_CMD_DISPLAY_COMMAND_0_SECURE 0x0 +#define DC_CMD_DISPLAY_COMMAND_0_WORD_COUNT 0x1 +#define DC_CMD_DISPLAY_COMMAND_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_CMD_DISPLAY_COMMAND_0_RESET_MASK _MK_MASK_CONST(0x61) +#define DC_CMD_DISPLAY_COMMAND_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_CMD_DISPLAY_COMMAND_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_CMD_DISPLAY_COMMAND_0_READ_MASK _MK_MASK_CONST(0x7fc00061) +#define DC_CMD_DISPLAY_COMMAND_0_WRITE_MASK _MK_MASK_CONST(0x7fc00061) +#define DC_CMD_DISPLAY_COMMAND_0_DISP_COMMAND_RAISE_SHIFT _MK_SHIFT_CONST(0) +#define DC_CMD_DISPLAY_COMMAND_0_DISP_COMMAND_RAISE_FIELD _MK_FIELD_CONST(0x1, DC_CMD_DISPLAY_COMMAND_0_DISP_COMMAND_RAISE_SHIFT) +#define DC_CMD_DISPLAY_COMMAND_0_DISP_COMMAND_RAISE_RANGE 0:0 +#define DC_CMD_DISPLAY_COMMAND_0_DISP_COMMAND_RAISE_WOFFSET 0x0 +#define DC_CMD_DISPLAY_COMMAND_0_DISP_COMMAND_RAISE_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_DISPLAY_COMMAND_0_DISP_COMMAND_RAISE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_CMD_DISPLAY_COMMAND_0_DISP_COMMAND_RAISE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_DISPLAY_COMMAND_0_DISP_COMMAND_RAISE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_CMD_DISPLAY_COMMAND_0_DISP_COMMAND_RAISE_DISABLE _MK_ENUM_CONST(0) +#define DC_CMD_DISPLAY_COMMAND_0_DISP_COMMAND_RAISE_ENABLE _MK_ENUM_CONST(1) + +#define DC_CMD_DISPLAY_COMMAND_0_DISPLAY_CTRL_MODE_SHIFT _MK_SHIFT_CONST(5) +#define DC_CMD_DISPLAY_COMMAND_0_DISPLAY_CTRL_MODE_FIELD _MK_FIELD_CONST(0x3, DC_CMD_DISPLAY_COMMAND_0_DISPLAY_CTRL_MODE_SHIFT) +#define DC_CMD_DISPLAY_COMMAND_0_DISPLAY_CTRL_MODE_RANGE 6:5 +#define DC_CMD_DISPLAY_COMMAND_0_DISPLAY_CTRL_MODE_WOFFSET 0x0 +#define DC_CMD_DISPLAY_COMMAND_0_DISPLAY_CTRL_MODE_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_DISPLAY_COMMAND_0_DISPLAY_CTRL_MODE_DEFAULT_MASK _MK_MASK_CONST(0x3) +#define DC_CMD_DISPLAY_COMMAND_0_DISPLAY_CTRL_MODE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_DISPLAY_COMMAND_0_DISPLAY_CTRL_MODE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_CMD_DISPLAY_COMMAND_0_DISPLAY_CTRL_MODE_STOP _MK_ENUM_CONST(0) +#define DC_CMD_DISPLAY_COMMAND_0_DISPLAY_CTRL_MODE_C_DISPLAY _MK_ENUM_CONST(1) +#define DC_CMD_DISPLAY_COMMAND_0_DISPLAY_CTRL_MODE_NC_DISPLAY _MK_ENUM_CONST(2) + +#define DC_CMD_DISPLAY_COMMAND_0_DISP_COMMAND_RAISE_VECTOR_SHIFT _MK_SHIFT_CONST(22) +#define DC_CMD_DISPLAY_COMMAND_0_DISP_COMMAND_RAISE_VECTOR_FIELD _MK_FIELD_CONST(0x1f, DC_CMD_DISPLAY_COMMAND_0_DISP_COMMAND_RAISE_VECTOR_SHIFT) +#define DC_CMD_DISPLAY_COMMAND_0_DISP_COMMAND_RAISE_VECTOR_RANGE 26:22 +#define DC_CMD_DISPLAY_COMMAND_0_DISP_COMMAND_RAISE_VECTOR_WOFFSET 0x0 +#define DC_CMD_DISPLAY_COMMAND_0_DISP_COMMAND_RAISE_VECTOR_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_DISPLAY_COMMAND_0_DISP_COMMAND_RAISE_VECTOR_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_CMD_DISPLAY_COMMAND_0_DISP_COMMAND_RAISE_VECTOR_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_DISPLAY_COMMAND_0_DISP_COMMAND_RAISE_VECTOR_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_CMD_DISPLAY_COMMAND_0_DISP_COMMAND_RAISE_CHANNEL_ID_SHIFT _MK_SHIFT_CONST(27) +#define DC_CMD_DISPLAY_COMMAND_0_DISP_COMMAND_RAISE_CHANNEL_ID_FIELD _MK_FIELD_CONST(0xf, DC_CMD_DISPLAY_COMMAND_0_DISP_COMMAND_RAISE_CHANNEL_ID_SHIFT) +#define DC_CMD_DISPLAY_COMMAND_0_DISP_COMMAND_RAISE_CHANNEL_ID_RANGE 30:27 +#define DC_CMD_DISPLAY_COMMAND_0_DISP_COMMAND_RAISE_CHANNEL_ID_WOFFSET 0x0 +#define DC_CMD_DISPLAY_COMMAND_0_DISP_COMMAND_RAISE_CHANNEL_ID_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_DISPLAY_COMMAND_0_DISP_COMMAND_RAISE_CHANNEL_ID_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_CMD_DISPLAY_COMMAND_0_DISP_COMMAND_RAISE_CHANNEL_ID_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_DISPLAY_COMMAND_0_DISP_COMMAND_RAISE_CHANNEL_ID_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_CMD_SIGNAL_RAISE_0 +#define DC_CMD_SIGNAL_RAISE_0 _MK_ADDR_CONST(0x33) +#define DC_CMD_SIGNAL_RAISE_0_SECURE 0x0 +#define DC_CMD_SIGNAL_RAISE_0_WORD_COUNT 0x1 +#define DC_CMD_SIGNAL_RAISE_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_CMD_SIGNAL_RAISE_0_RESET_MASK _MK_MASK_CONST(0x1000) +#define DC_CMD_SIGNAL_RAISE_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_CMD_SIGNAL_RAISE_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_CMD_SIGNAL_RAISE_0_READ_MASK _MK_MASK_CONST(0xf171f) +#define DC_CMD_SIGNAL_RAISE_0_WRITE_MASK _MK_MASK_CONST(0xf171f) +#define DC_CMD_SIGNAL_RAISE_0_SIGNAL_RAISE_VECTOR_SHIFT _MK_SHIFT_CONST(0) +#define DC_CMD_SIGNAL_RAISE_0_SIGNAL_RAISE_VECTOR_FIELD _MK_FIELD_CONST(0x1f, DC_CMD_SIGNAL_RAISE_0_SIGNAL_RAISE_VECTOR_SHIFT) +#define DC_CMD_SIGNAL_RAISE_0_SIGNAL_RAISE_VECTOR_RANGE 4:0 +#define DC_CMD_SIGNAL_RAISE_0_SIGNAL_RAISE_VECTOR_WOFFSET 0x0 +#define DC_CMD_SIGNAL_RAISE_0_SIGNAL_RAISE_VECTOR_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_SIGNAL_RAISE_0_SIGNAL_RAISE_VECTOR_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_CMD_SIGNAL_RAISE_0_SIGNAL_RAISE_VECTOR_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_SIGNAL_RAISE_0_SIGNAL_RAISE_VECTOR_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_CMD_SIGNAL_RAISE_0_SIGNAL_RAISE_SELECT_SHIFT _MK_SHIFT_CONST(8) +#define DC_CMD_SIGNAL_RAISE_0_SIGNAL_RAISE_SELECT_FIELD _MK_FIELD_CONST(0x7, DC_CMD_SIGNAL_RAISE_0_SIGNAL_RAISE_SELECT_SHIFT) +#define DC_CMD_SIGNAL_RAISE_0_SIGNAL_RAISE_SELECT_RANGE 10:8 +#define DC_CMD_SIGNAL_RAISE_0_SIGNAL_RAISE_SELECT_WOFFSET 0x0 +#define DC_CMD_SIGNAL_RAISE_0_SIGNAL_RAISE_SELECT_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_SIGNAL_RAISE_0_SIGNAL_RAISE_SELECT_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_CMD_SIGNAL_RAISE_0_SIGNAL_RAISE_SELECT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_SIGNAL_RAISE_0_SIGNAL_RAISE_SELECT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_CMD_SIGNAL_RAISE_0_SIGNAL_RAISE_SELECT_NONE _MK_ENUM_CONST(0) +#define DC_CMD_SIGNAL_RAISE_0_SIGNAL_RAISE_SELECT_FRAME_END _MK_ENUM_CONST(1) +#define DC_CMD_SIGNAL_RAISE_0_SIGNAL_RAISE_SELECT_VBLANK _MK_ENUM_CONST(2) +#define DC_CMD_SIGNAL_RAISE_0_SIGNAL_RAISE_SELECT_VPULSE3 _MK_ENUM_CONST(3) +#define DC_CMD_SIGNAL_RAISE_0_SIGNAL_RAISE_SELECT_VBLANK_START _MK_ENUM_CONST(4) +#define DC_CMD_SIGNAL_RAISE_0_SIGNAL_RAISE_SELECT_VBLANK_END _MK_ENUM_CONST(5) +#define DC_CMD_SIGNAL_RAISE_0_SIGNAL_RAISE_SELECT_VPULSE3_START _MK_ENUM_CONST(6) +#define DC_CMD_SIGNAL_RAISE_0_SIGNAL_RAISE_SELECT_VPULSE3_END _MK_ENUM_CONST(7) + +#define DC_CMD_SIGNAL_RAISE_0_SIGNAL_RAISE_TYPE_SHIFT _MK_SHIFT_CONST(12) +#define DC_CMD_SIGNAL_RAISE_0_SIGNAL_RAISE_TYPE_FIELD _MK_FIELD_CONST(0x1, DC_CMD_SIGNAL_RAISE_0_SIGNAL_RAISE_TYPE_SHIFT) +#define DC_CMD_SIGNAL_RAISE_0_SIGNAL_RAISE_TYPE_RANGE 12:12 +#define DC_CMD_SIGNAL_RAISE_0_SIGNAL_RAISE_TYPE_WOFFSET 0x0 +#define DC_CMD_SIGNAL_RAISE_0_SIGNAL_RAISE_TYPE_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_SIGNAL_RAISE_0_SIGNAL_RAISE_TYPE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_CMD_SIGNAL_RAISE_0_SIGNAL_RAISE_TYPE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_SIGNAL_RAISE_0_SIGNAL_RAISE_TYPE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_CMD_SIGNAL_RAISE_0_SIGNAL_RAISE_TYPE_ONESHOT _MK_ENUM_CONST(0) +#define DC_CMD_SIGNAL_RAISE_0_SIGNAL_RAISE_TYPE_CONT _MK_ENUM_CONST(1) + +#define DC_CMD_SIGNAL_RAISE_0_SIGNAL_RAISE_CHANNEL_ID_SHIFT _MK_SHIFT_CONST(16) +#define DC_CMD_SIGNAL_RAISE_0_SIGNAL_RAISE_CHANNEL_ID_FIELD _MK_FIELD_CONST(0xf, DC_CMD_SIGNAL_RAISE_0_SIGNAL_RAISE_CHANNEL_ID_SHIFT) +#define DC_CMD_SIGNAL_RAISE_0_SIGNAL_RAISE_CHANNEL_ID_RANGE 19:16 +#define DC_CMD_SIGNAL_RAISE_0_SIGNAL_RAISE_CHANNEL_ID_WOFFSET 0x0 +#define DC_CMD_SIGNAL_RAISE_0_SIGNAL_RAISE_CHANNEL_ID_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_SIGNAL_RAISE_0_SIGNAL_RAISE_CHANNEL_ID_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_CMD_SIGNAL_RAISE_0_SIGNAL_RAISE_CHANNEL_ID_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_SIGNAL_RAISE_0_SIGNAL_RAISE_CHANNEL_ID_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Reserved address 52 [0x34] + +// Register DC_CMD_DISPLAY_POWER_CONTROL_0 +#define DC_CMD_DISPLAY_POWER_CONTROL_0 _MK_ADDR_CONST(0x36) +#define DC_CMD_DISPLAY_POWER_CONTROL_0_SECURE 0x0 +#define DC_CMD_DISPLAY_POWER_CONTROL_0_WORD_COUNT 0x1 +#define DC_CMD_DISPLAY_POWER_CONTROL_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_CMD_DISPLAY_POWER_CONTROL_0_RESET_MASK _MK_MASK_CONST(0x3050155) +#define DC_CMD_DISPLAY_POWER_CONTROL_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_CMD_DISPLAY_POWER_CONTROL_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_CMD_DISPLAY_POWER_CONTROL_0_READ_MASK _MK_MASK_CONST(0x3050155) +#define DC_CMD_DISPLAY_POWER_CONTROL_0_WRITE_MASK _MK_MASK_CONST(0x3050155) +#define DC_CMD_DISPLAY_POWER_CONTROL_0_PW0_ENABLE_SHIFT _MK_SHIFT_CONST(0) +#define DC_CMD_DISPLAY_POWER_CONTROL_0_PW0_ENABLE_FIELD _MK_FIELD_CONST(0x1, DC_CMD_DISPLAY_POWER_CONTROL_0_PW0_ENABLE_SHIFT) +#define DC_CMD_DISPLAY_POWER_CONTROL_0_PW0_ENABLE_RANGE 0:0 +#define DC_CMD_DISPLAY_POWER_CONTROL_0_PW0_ENABLE_WOFFSET 0x0 +#define DC_CMD_DISPLAY_POWER_CONTROL_0_PW0_ENABLE_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_DISPLAY_POWER_CONTROL_0_PW0_ENABLE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_CMD_DISPLAY_POWER_CONTROL_0_PW0_ENABLE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_DISPLAY_POWER_CONTROL_0_PW0_ENABLE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_CMD_DISPLAY_POWER_CONTROL_0_PW0_ENABLE_DISABLE _MK_ENUM_CONST(0) +#define DC_CMD_DISPLAY_POWER_CONTROL_0_PW0_ENABLE_ENABLE _MK_ENUM_CONST(1) + +#define DC_CMD_DISPLAY_POWER_CONTROL_0_PW1_ENABLE_SHIFT _MK_SHIFT_CONST(2) +#define DC_CMD_DISPLAY_POWER_CONTROL_0_PW1_ENABLE_FIELD _MK_FIELD_CONST(0x1, DC_CMD_DISPLAY_POWER_CONTROL_0_PW1_ENABLE_SHIFT) +#define DC_CMD_DISPLAY_POWER_CONTROL_0_PW1_ENABLE_RANGE 2:2 +#define DC_CMD_DISPLAY_POWER_CONTROL_0_PW1_ENABLE_WOFFSET 0x0 +#define DC_CMD_DISPLAY_POWER_CONTROL_0_PW1_ENABLE_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_DISPLAY_POWER_CONTROL_0_PW1_ENABLE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_CMD_DISPLAY_POWER_CONTROL_0_PW1_ENABLE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_DISPLAY_POWER_CONTROL_0_PW1_ENABLE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_CMD_DISPLAY_POWER_CONTROL_0_PW1_ENABLE_DISABLE _MK_ENUM_CONST(0) +#define DC_CMD_DISPLAY_POWER_CONTROL_0_PW1_ENABLE_ENABLE _MK_ENUM_CONST(1) + +#define DC_CMD_DISPLAY_POWER_CONTROL_0_PW2_ENABLE_SHIFT _MK_SHIFT_CONST(4) +#define DC_CMD_DISPLAY_POWER_CONTROL_0_PW2_ENABLE_FIELD _MK_FIELD_CONST(0x1, DC_CMD_DISPLAY_POWER_CONTROL_0_PW2_ENABLE_SHIFT) +#define DC_CMD_DISPLAY_POWER_CONTROL_0_PW2_ENABLE_RANGE 4:4 +#define DC_CMD_DISPLAY_POWER_CONTROL_0_PW2_ENABLE_WOFFSET 0x0 +#define DC_CMD_DISPLAY_POWER_CONTROL_0_PW2_ENABLE_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_DISPLAY_POWER_CONTROL_0_PW2_ENABLE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_CMD_DISPLAY_POWER_CONTROL_0_PW2_ENABLE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_DISPLAY_POWER_CONTROL_0_PW2_ENABLE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_CMD_DISPLAY_POWER_CONTROL_0_PW2_ENABLE_DISABLE _MK_ENUM_CONST(0) +#define DC_CMD_DISPLAY_POWER_CONTROL_0_PW2_ENABLE_ENABLE _MK_ENUM_CONST(1) + +#define DC_CMD_DISPLAY_POWER_CONTROL_0_PW3_ENABLE_SHIFT _MK_SHIFT_CONST(6) +#define DC_CMD_DISPLAY_POWER_CONTROL_0_PW3_ENABLE_FIELD _MK_FIELD_CONST(0x1, DC_CMD_DISPLAY_POWER_CONTROL_0_PW3_ENABLE_SHIFT) +#define DC_CMD_DISPLAY_POWER_CONTROL_0_PW3_ENABLE_RANGE 6:6 +#define DC_CMD_DISPLAY_POWER_CONTROL_0_PW3_ENABLE_WOFFSET 0x0 +#define DC_CMD_DISPLAY_POWER_CONTROL_0_PW3_ENABLE_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_DISPLAY_POWER_CONTROL_0_PW3_ENABLE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_CMD_DISPLAY_POWER_CONTROL_0_PW3_ENABLE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_DISPLAY_POWER_CONTROL_0_PW3_ENABLE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_CMD_DISPLAY_POWER_CONTROL_0_PW3_ENABLE_DISABLE _MK_ENUM_CONST(0) +#define DC_CMD_DISPLAY_POWER_CONTROL_0_PW3_ENABLE_ENABLE _MK_ENUM_CONST(1) + +#define DC_CMD_DISPLAY_POWER_CONTROL_0_PW4_ENABLE_SHIFT _MK_SHIFT_CONST(8) +#define DC_CMD_DISPLAY_POWER_CONTROL_0_PW4_ENABLE_FIELD _MK_FIELD_CONST(0x1, DC_CMD_DISPLAY_POWER_CONTROL_0_PW4_ENABLE_SHIFT) +#define DC_CMD_DISPLAY_POWER_CONTROL_0_PW4_ENABLE_RANGE 8:8 +#define DC_CMD_DISPLAY_POWER_CONTROL_0_PW4_ENABLE_WOFFSET 0x0 +#define DC_CMD_DISPLAY_POWER_CONTROL_0_PW4_ENABLE_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_DISPLAY_POWER_CONTROL_0_PW4_ENABLE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_CMD_DISPLAY_POWER_CONTROL_0_PW4_ENABLE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_DISPLAY_POWER_CONTROL_0_PW4_ENABLE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_CMD_DISPLAY_POWER_CONTROL_0_PW4_ENABLE_DISABLE _MK_ENUM_CONST(0) +#define DC_CMD_DISPLAY_POWER_CONTROL_0_PW4_ENABLE_ENABLE _MK_ENUM_CONST(1) + +#define DC_CMD_DISPLAY_POWER_CONTROL_0_PM0_ENABLE_SHIFT _MK_SHIFT_CONST(16) +#define DC_CMD_DISPLAY_POWER_CONTROL_0_PM0_ENABLE_FIELD _MK_FIELD_CONST(0x1, DC_CMD_DISPLAY_POWER_CONTROL_0_PM0_ENABLE_SHIFT) +#define DC_CMD_DISPLAY_POWER_CONTROL_0_PM0_ENABLE_RANGE 16:16 +#define DC_CMD_DISPLAY_POWER_CONTROL_0_PM0_ENABLE_WOFFSET 0x0 +#define DC_CMD_DISPLAY_POWER_CONTROL_0_PM0_ENABLE_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_DISPLAY_POWER_CONTROL_0_PM0_ENABLE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_CMD_DISPLAY_POWER_CONTROL_0_PM0_ENABLE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_DISPLAY_POWER_CONTROL_0_PM0_ENABLE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_CMD_DISPLAY_POWER_CONTROL_0_PM0_ENABLE_DISABLE _MK_ENUM_CONST(0) +#define DC_CMD_DISPLAY_POWER_CONTROL_0_PM0_ENABLE_ENABLE _MK_ENUM_CONST(1) + +#define DC_CMD_DISPLAY_POWER_CONTROL_0_PM1_ENABLE_SHIFT _MK_SHIFT_CONST(18) +#define DC_CMD_DISPLAY_POWER_CONTROL_0_PM1_ENABLE_FIELD _MK_FIELD_CONST(0x1, DC_CMD_DISPLAY_POWER_CONTROL_0_PM1_ENABLE_SHIFT) +#define DC_CMD_DISPLAY_POWER_CONTROL_0_PM1_ENABLE_RANGE 18:18 +#define DC_CMD_DISPLAY_POWER_CONTROL_0_PM1_ENABLE_WOFFSET 0x0 +#define DC_CMD_DISPLAY_POWER_CONTROL_0_PM1_ENABLE_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_DISPLAY_POWER_CONTROL_0_PM1_ENABLE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_CMD_DISPLAY_POWER_CONTROL_0_PM1_ENABLE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_DISPLAY_POWER_CONTROL_0_PM1_ENABLE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_CMD_DISPLAY_POWER_CONTROL_0_PM1_ENABLE_DISABLE _MK_ENUM_CONST(0) +#define DC_CMD_DISPLAY_POWER_CONTROL_0_PM1_ENABLE_ENABLE _MK_ENUM_CONST(1) + +#define DC_CMD_DISPLAY_POWER_CONTROL_0_SPI_ENABLE_SHIFT _MK_SHIFT_CONST(24) +#define DC_CMD_DISPLAY_POWER_CONTROL_0_SPI_ENABLE_FIELD _MK_FIELD_CONST(0x1, DC_CMD_DISPLAY_POWER_CONTROL_0_SPI_ENABLE_SHIFT) +#define DC_CMD_DISPLAY_POWER_CONTROL_0_SPI_ENABLE_RANGE 24:24 +#define DC_CMD_DISPLAY_POWER_CONTROL_0_SPI_ENABLE_WOFFSET 0x0 +#define DC_CMD_DISPLAY_POWER_CONTROL_0_SPI_ENABLE_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_DISPLAY_POWER_CONTROL_0_SPI_ENABLE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_CMD_DISPLAY_POWER_CONTROL_0_SPI_ENABLE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_DISPLAY_POWER_CONTROL_0_SPI_ENABLE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_CMD_DISPLAY_POWER_CONTROL_0_SPI_ENABLE_DISABLE _MK_ENUM_CONST(0) +#define DC_CMD_DISPLAY_POWER_CONTROL_0_SPI_ENABLE_ENABLE _MK_ENUM_CONST(1) + +#define DC_CMD_DISPLAY_POWER_CONTROL_0_HSPI_ENABLE_SHIFT _MK_SHIFT_CONST(25) +#define DC_CMD_DISPLAY_POWER_CONTROL_0_HSPI_ENABLE_FIELD _MK_FIELD_CONST(0x1, DC_CMD_DISPLAY_POWER_CONTROL_0_HSPI_ENABLE_SHIFT) +#define DC_CMD_DISPLAY_POWER_CONTROL_0_HSPI_ENABLE_RANGE 25:25 +#define DC_CMD_DISPLAY_POWER_CONTROL_0_HSPI_ENABLE_WOFFSET 0x0 +#define DC_CMD_DISPLAY_POWER_CONTROL_0_HSPI_ENABLE_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_DISPLAY_POWER_CONTROL_0_HSPI_ENABLE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_CMD_DISPLAY_POWER_CONTROL_0_HSPI_ENABLE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_DISPLAY_POWER_CONTROL_0_HSPI_ENABLE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_CMD_DISPLAY_POWER_CONTROL_0_HSPI_ENABLE_DISABLE _MK_ENUM_CONST(0) +#define DC_CMD_DISPLAY_POWER_CONTROL_0_HSPI_ENABLE_ENABLE _MK_ENUM_CONST(1) + + +// Register DC_CMD_INT_STATUS_0 +#define DC_CMD_INT_STATUS_0 _MK_ADDR_CONST(0x37) +#define DC_CMD_INT_STATUS_0_SECURE 0x0 +#define DC_CMD_INT_STATUS_0_WORD_COUNT 0x1 +#define DC_CMD_INT_STATUS_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_CMD_INT_STATUS_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_CMD_INT_STATUS_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_CMD_INT_STATUS_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_CMD_INT_STATUS_0_READ_MASK _MK_MASK_CONST(0x3c1f7bf) +#define DC_CMD_INT_STATUS_0_WRITE_MASK _MK_MASK_CONST(0x3c1f7bf) +#define DC_CMD_INT_STATUS_0_CTXSW_INT_SHIFT _MK_SHIFT_CONST(0) +#define DC_CMD_INT_STATUS_0_CTXSW_INT_FIELD _MK_FIELD_CONST(0x1, DC_CMD_INT_STATUS_0_CTXSW_INT_SHIFT) +#define DC_CMD_INT_STATUS_0_CTXSW_INT_RANGE 0:0 +#define DC_CMD_INT_STATUS_0_CTXSW_INT_WOFFSET 0x0 +#define DC_CMD_INT_STATUS_0_CTXSW_INT_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_INT_STATUS_0_CTXSW_INT_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_CMD_INT_STATUS_0_CTXSW_INT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_INT_STATUS_0_CTXSW_INT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_CMD_INT_STATUS_0_FRAME_END_INT_SHIFT _MK_SHIFT_CONST(1) +#define DC_CMD_INT_STATUS_0_FRAME_END_INT_FIELD _MK_FIELD_CONST(0x1, DC_CMD_INT_STATUS_0_FRAME_END_INT_SHIFT) +#define DC_CMD_INT_STATUS_0_FRAME_END_INT_RANGE 1:1 +#define DC_CMD_INT_STATUS_0_FRAME_END_INT_WOFFSET 0x0 +#define DC_CMD_INT_STATUS_0_FRAME_END_INT_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_INT_STATUS_0_FRAME_END_INT_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_CMD_INT_STATUS_0_FRAME_END_INT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_INT_STATUS_0_FRAME_END_INT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_CMD_INT_STATUS_0_V_BLANK_INT_SHIFT _MK_SHIFT_CONST(2) +#define DC_CMD_INT_STATUS_0_V_BLANK_INT_FIELD _MK_FIELD_CONST(0x1, DC_CMD_INT_STATUS_0_V_BLANK_INT_SHIFT) +#define DC_CMD_INT_STATUS_0_V_BLANK_INT_RANGE 2:2 +#define DC_CMD_INT_STATUS_0_V_BLANK_INT_WOFFSET 0x0 +#define DC_CMD_INT_STATUS_0_V_BLANK_INT_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_INT_STATUS_0_V_BLANK_INT_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_CMD_INT_STATUS_0_V_BLANK_INT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_INT_STATUS_0_V_BLANK_INT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_CMD_INT_STATUS_0_H_BLANK_INT_SHIFT _MK_SHIFT_CONST(3) +#define DC_CMD_INT_STATUS_0_H_BLANK_INT_FIELD _MK_FIELD_CONST(0x1, DC_CMD_INT_STATUS_0_H_BLANK_INT_SHIFT) +#define DC_CMD_INT_STATUS_0_H_BLANK_INT_RANGE 3:3 +#define DC_CMD_INT_STATUS_0_H_BLANK_INT_WOFFSET 0x0 +#define DC_CMD_INT_STATUS_0_H_BLANK_INT_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_INT_STATUS_0_H_BLANK_INT_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_CMD_INT_STATUS_0_H_BLANK_INT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_INT_STATUS_0_H_BLANK_INT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_CMD_INT_STATUS_0_V_PULSE3_INT_SHIFT _MK_SHIFT_CONST(4) +#define DC_CMD_INT_STATUS_0_V_PULSE3_INT_FIELD _MK_FIELD_CONST(0x1, DC_CMD_INT_STATUS_0_V_PULSE3_INT_SHIFT) +#define DC_CMD_INT_STATUS_0_V_PULSE3_INT_RANGE 4:4 +#define DC_CMD_INT_STATUS_0_V_PULSE3_INT_WOFFSET 0x0 +#define DC_CMD_INT_STATUS_0_V_PULSE3_INT_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_INT_STATUS_0_V_PULSE3_INT_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_CMD_INT_STATUS_0_V_PULSE3_INT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_INT_STATUS_0_V_PULSE3_INT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_CMD_INT_STATUS_0_V_PULSE2_INT_SHIFT _MK_SHIFT_CONST(5) +#define DC_CMD_INT_STATUS_0_V_PULSE2_INT_FIELD _MK_FIELD_CONST(0x1, DC_CMD_INT_STATUS_0_V_PULSE2_INT_SHIFT) +#define DC_CMD_INT_STATUS_0_V_PULSE2_INT_RANGE 5:5 +#define DC_CMD_INT_STATUS_0_V_PULSE2_INT_WOFFSET 0x0 +#define DC_CMD_INT_STATUS_0_V_PULSE2_INT_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_INT_STATUS_0_V_PULSE2_INT_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_CMD_INT_STATUS_0_V_PULSE2_INT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_INT_STATUS_0_V_PULSE2_INT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_CMD_INT_STATUS_0_SPI_BUSY_INT_SHIFT _MK_SHIFT_CONST(7) +#define DC_CMD_INT_STATUS_0_SPI_BUSY_INT_FIELD _MK_FIELD_CONST(0x1, DC_CMD_INT_STATUS_0_SPI_BUSY_INT_SHIFT) +#define DC_CMD_INT_STATUS_0_SPI_BUSY_INT_RANGE 7:7 +#define DC_CMD_INT_STATUS_0_SPI_BUSY_INT_WOFFSET 0x0 +#define DC_CMD_INT_STATUS_0_SPI_BUSY_INT_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_INT_STATUS_0_SPI_BUSY_INT_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_CMD_INT_STATUS_0_SPI_BUSY_INT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_INT_STATUS_0_SPI_BUSY_INT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_CMD_INT_STATUS_0_WIN_A_UF_INT_SHIFT _MK_SHIFT_CONST(8) +#define DC_CMD_INT_STATUS_0_WIN_A_UF_INT_FIELD _MK_FIELD_CONST(0x1, DC_CMD_INT_STATUS_0_WIN_A_UF_INT_SHIFT) +#define DC_CMD_INT_STATUS_0_WIN_A_UF_INT_RANGE 8:8 +#define DC_CMD_INT_STATUS_0_WIN_A_UF_INT_WOFFSET 0x0 +#define DC_CMD_INT_STATUS_0_WIN_A_UF_INT_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_INT_STATUS_0_WIN_A_UF_INT_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_CMD_INT_STATUS_0_WIN_A_UF_INT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_INT_STATUS_0_WIN_A_UF_INT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_CMD_INT_STATUS_0_WIN_B_UF_INT_SHIFT _MK_SHIFT_CONST(9) +#define DC_CMD_INT_STATUS_0_WIN_B_UF_INT_FIELD _MK_FIELD_CONST(0x1, DC_CMD_INT_STATUS_0_WIN_B_UF_INT_SHIFT) +#define DC_CMD_INT_STATUS_0_WIN_B_UF_INT_RANGE 9:9 +#define DC_CMD_INT_STATUS_0_WIN_B_UF_INT_WOFFSET 0x0 +#define DC_CMD_INT_STATUS_0_WIN_B_UF_INT_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_INT_STATUS_0_WIN_B_UF_INT_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_CMD_INT_STATUS_0_WIN_B_UF_INT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_INT_STATUS_0_WIN_B_UF_INT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_CMD_INT_STATUS_0_WIN_C_UF_INT_SHIFT _MK_SHIFT_CONST(10) +#define DC_CMD_INT_STATUS_0_WIN_C_UF_INT_FIELD _MK_FIELD_CONST(0x1, DC_CMD_INT_STATUS_0_WIN_C_UF_INT_SHIFT) +#define DC_CMD_INT_STATUS_0_WIN_C_UF_INT_RANGE 10:10 +#define DC_CMD_INT_STATUS_0_WIN_C_UF_INT_WOFFSET 0x0 +#define DC_CMD_INT_STATUS_0_WIN_C_UF_INT_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_INT_STATUS_0_WIN_C_UF_INT_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_CMD_INT_STATUS_0_WIN_C_UF_INT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_INT_STATUS_0_WIN_C_UF_INT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_CMD_INT_STATUS_0_MSF_INT_SHIFT _MK_SHIFT_CONST(12) +#define DC_CMD_INT_STATUS_0_MSF_INT_FIELD _MK_FIELD_CONST(0x1, DC_CMD_INT_STATUS_0_MSF_INT_SHIFT) +#define DC_CMD_INT_STATUS_0_MSF_INT_RANGE 12:12 +#define DC_CMD_INT_STATUS_0_MSF_INT_WOFFSET 0x0 +#define DC_CMD_INT_STATUS_0_MSF_INT_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_INT_STATUS_0_MSF_INT_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_CMD_INT_STATUS_0_MSF_INT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_INT_STATUS_0_MSF_INT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_CMD_INT_STATUS_0_SSF_INT_SHIFT _MK_SHIFT_CONST(13) +#define DC_CMD_INT_STATUS_0_SSF_INT_FIELD _MK_FIELD_CONST(0x1, DC_CMD_INT_STATUS_0_SSF_INT_SHIFT) +#define DC_CMD_INT_STATUS_0_SSF_INT_RANGE 13:13 +#define DC_CMD_INT_STATUS_0_SSF_INT_WOFFSET 0x0 +#define DC_CMD_INT_STATUS_0_SSF_INT_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_INT_STATUS_0_SSF_INT_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_CMD_INT_STATUS_0_SSF_INT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_INT_STATUS_0_SSF_INT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_CMD_INT_STATUS_0_WIN_A_OF_INT_SHIFT _MK_SHIFT_CONST(14) +#define DC_CMD_INT_STATUS_0_WIN_A_OF_INT_FIELD _MK_FIELD_CONST(0x1, DC_CMD_INT_STATUS_0_WIN_A_OF_INT_SHIFT) +#define DC_CMD_INT_STATUS_0_WIN_A_OF_INT_RANGE 14:14 +#define DC_CMD_INT_STATUS_0_WIN_A_OF_INT_WOFFSET 0x0 +#define DC_CMD_INT_STATUS_0_WIN_A_OF_INT_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_INT_STATUS_0_WIN_A_OF_INT_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_CMD_INT_STATUS_0_WIN_A_OF_INT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_INT_STATUS_0_WIN_A_OF_INT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_CMD_INT_STATUS_0_WIN_B_OF_INT_SHIFT _MK_SHIFT_CONST(15) +#define DC_CMD_INT_STATUS_0_WIN_B_OF_INT_FIELD _MK_FIELD_CONST(0x1, DC_CMD_INT_STATUS_0_WIN_B_OF_INT_SHIFT) +#define DC_CMD_INT_STATUS_0_WIN_B_OF_INT_RANGE 15:15 +#define DC_CMD_INT_STATUS_0_WIN_B_OF_INT_WOFFSET 0x0 +#define DC_CMD_INT_STATUS_0_WIN_B_OF_INT_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_INT_STATUS_0_WIN_B_OF_INT_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_CMD_INT_STATUS_0_WIN_B_OF_INT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_INT_STATUS_0_WIN_B_OF_INT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_CMD_INT_STATUS_0_WIN_C_OF_INT_SHIFT _MK_SHIFT_CONST(16) +#define DC_CMD_INT_STATUS_0_WIN_C_OF_INT_FIELD _MK_FIELD_CONST(0x1, DC_CMD_INT_STATUS_0_WIN_C_OF_INT_SHIFT) +#define DC_CMD_INT_STATUS_0_WIN_C_OF_INT_RANGE 16:16 +#define DC_CMD_INT_STATUS_0_WIN_C_OF_INT_WOFFSET 0x0 +#define DC_CMD_INT_STATUS_0_WIN_C_OF_INT_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_INT_STATUS_0_WIN_C_OF_INT_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_CMD_INT_STATUS_0_WIN_C_OF_INT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_INT_STATUS_0_WIN_C_OF_INT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_CMD_INT_STATUS_0_CMU_LUT_CONFLICT_INT_SHIFT _MK_SHIFT_CONST(22) +#define DC_CMD_INT_STATUS_0_CMU_LUT_CONFLICT_INT_FIELD _MK_FIELD_CONST(0x1, DC_CMD_INT_STATUS_0_CMU_LUT_CONFLICT_INT_SHIFT) +#define DC_CMD_INT_STATUS_0_CMU_LUT_CONFLICT_INT_RANGE 22:22 +#define DC_CMD_INT_STATUS_0_CMU_LUT_CONFLICT_INT_WOFFSET 0x0 +#define DC_CMD_INT_STATUS_0_CMU_LUT_CONFLICT_INT_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_INT_STATUS_0_CMU_LUT_CONFLICT_INT_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_CMD_INT_STATUS_0_CMU_LUT_CONFLICT_INT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_INT_STATUS_0_CMU_LUT_CONFLICT_INT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_CMD_INT_STATUS_0_HC_UF_INT_SHIFT _MK_SHIFT_CONST(23) +#define DC_CMD_INT_STATUS_0_HC_UF_INT_FIELD _MK_FIELD_CONST(0x1, DC_CMD_INT_STATUS_0_HC_UF_INT_SHIFT) +#define DC_CMD_INT_STATUS_0_HC_UF_INT_RANGE 23:23 +#define DC_CMD_INT_STATUS_0_HC_UF_INT_WOFFSET 0x0 +#define DC_CMD_INT_STATUS_0_HC_UF_INT_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_INT_STATUS_0_HC_UF_INT_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_CMD_INT_STATUS_0_HC_UF_INT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_INT_STATUS_0_HC_UF_INT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_CMD_INT_STATUS_0_WIN_D_UF_INT_SHIFT _MK_SHIFT_CONST(24) +#define DC_CMD_INT_STATUS_0_WIN_D_UF_INT_FIELD _MK_FIELD_CONST(0x1, DC_CMD_INT_STATUS_0_WIN_D_UF_INT_SHIFT) +#define DC_CMD_INT_STATUS_0_WIN_D_UF_INT_RANGE 24:24 +#define DC_CMD_INT_STATUS_0_WIN_D_UF_INT_WOFFSET 0x0 +#define DC_CMD_INT_STATUS_0_WIN_D_UF_INT_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_INT_STATUS_0_WIN_D_UF_INT_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_CMD_INT_STATUS_0_WIN_D_UF_INT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_INT_STATUS_0_WIN_D_UF_INT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_CMD_INT_STATUS_0_WIN_T_UF_INT_SHIFT _MK_SHIFT_CONST(25) +#define DC_CMD_INT_STATUS_0_WIN_T_UF_INT_FIELD _MK_FIELD_CONST(0x1, DC_CMD_INT_STATUS_0_WIN_T_UF_INT_SHIFT) +#define DC_CMD_INT_STATUS_0_WIN_T_UF_INT_RANGE 25:25 +#define DC_CMD_INT_STATUS_0_WIN_T_UF_INT_WOFFSET 0x0 +#define DC_CMD_INT_STATUS_0_WIN_T_UF_INT_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_INT_STATUS_0_WIN_T_UF_INT_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_CMD_INT_STATUS_0_WIN_T_UF_INT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_INT_STATUS_0_WIN_T_UF_INT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_CMD_INT_MASK_0 +#define DC_CMD_INT_MASK_0 _MK_ADDR_CONST(0x38) +#define DC_CMD_INT_MASK_0_SECURE 0x0 +#define DC_CMD_INT_MASK_0_WORD_COUNT 0x1 +#define DC_CMD_INT_MASK_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_CMD_INT_MASK_0_RESET_MASK _MK_MASK_CONST(0x3c1f7bf) +#define DC_CMD_INT_MASK_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_CMD_INT_MASK_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_CMD_INT_MASK_0_READ_MASK _MK_MASK_CONST(0x3c1f7bf) +#define DC_CMD_INT_MASK_0_WRITE_MASK _MK_MASK_CONST(0x3c1f7bf) +#define DC_CMD_INT_MASK_0_CTXSW_INT_MASK_SHIFT _MK_SHIFT_CONST(0) +#define DC_CMD_INT_MASK_0_CTXSW_INT_MASK_FIELD _MK_FIELD_CONST(0x1, DC_CMD_INT_MASK_0_CTXSW_INT_MASK_SHIFT) +#define DC_CMD_INT_MASK_0_CTXSW_INT_MASK_RANGE 0:0 +#define DC_CMD_INT_MASK_0_CTXSW_INT_MASK_WOFFSET 0x0 +#define DC_CMD_INT_MASK_0_CTXSW_INT_MASK_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_INT_MASK_0_CTXSW_INT_MASK_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_CMD_INT_MASK_0_CTXSW_INT_MASK_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_INT_MASK_0_CTXSW_INT_MASK_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_CMD_INT_MASK_0_CTXSW_INT_MASK_MASKED _MK_ENUM_CONST(0) +#define DC_CMD_INT_MASK_0_CTXSW_INT_MASK_NOTMASKED _MK_ENUM_CONST(1) + +#define DC_CMD_INT_MASK_0_FRAME_END_INT_MASK_SHIFT _MK_SHIFT_CONST(1) +#define DC_CMD_INT_MASK_0_FRAME_END_INT_MASK_FIELD _MK_FIELD_CONST(0x1, DC_CMD_INT_MASK_0_FRAME_END_INT_MASK_SHIFT) +#define DC_CMD_INT_MASK_0_FRAME_END_INT_MASK_RANGE 1:1 +#define DC_CMD_INT_MASK_0_FRAME_END_INT_MASK_WOFFSET 0x0 +#define DC_CMD_INT_MASK_0_FRAME_END_INT_MASK_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_INT_MASK_0_FRAME_END_INT_MASK_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_CMD_INT_MASK_0_FRAME_END_INT_MASK_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_INT_MASK_0_FRAME_END_INT_MASK_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_CMD_INT_MASK_0_FRAME_END_INT_MASK_MASKED _MK_ENUM_CONST(0) +#define DC_CMD_INT_MASK_0_FRAME_END_INT_MASK_NOTMASKED _MK_ENUM_CONST(1) + +#define DC_CMD_INT_MASK_0_V_BLANK_INT_MASK_SHIFT _MK_SHIFT_CONST(2) +#define DC_CMD_INT_MASK_0_V_BLANK_INT_MASK_FIELD _MK_FIELD_CONST(0x1, DC_CMD_INT_MASK_0_V_BLANK_INT_MASK_SHIFT) +#define DC_CMD_INT_MASK_0_V_BLANK_INT_MASK_RANGE 2:2 +#define DC_CMD_INT_MASK_0_V_BLANK_INT_MASK_WOFFSET 0x0 +#define DC_CMD_INT_MASK_0_V_BLANK_INT_MASK_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_INT_MASK_0_V_BLANK_INT_MASK_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_CMD_INT_MASK_0_V_BLANK_INT_MASK_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_INT_MASK_0_V_BLANK_INT_MASK_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_CMD_INT_MASK_0_V_BLANK_INT_MASK_MASKED _MK_ENUM_CONST(0) +#define DC_CMD_INT_MASK_0_V_BLANK_INT_MASK_NOTMASKED _MK_ENUM_CONST(1) + +#define DC_CMD_INT_MASK_0_H_BLANK_INT_MASK_SHIFT _MK_SHIFT_CONST(3) +#define DC_CMD_INT_MASK_0_H_BLANK_INT_MASK_FIELD _MK_FIELD_CONST(0x1, DC_CMD_INT_MASK_0_H_BLANK_INT_MASK_SHIFT) +#define DC_CMD_INT_MASK_0_H_BLANK_INT_MASK_RANGE 3:3 +#define DC_CMD_INT_MASK_0_H_BLANK_INT_MASK_WOFFSET 0x0 +#define DC_CMD_INT_MASK_0_H_BLANK_INT_MASK_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_INT_MASK_0_H_BLANK_INT_MASK_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_CMD_INT_MASK_0_H_BLANK_INT_MASK_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_INT_MASK_0_H_BLANK_INT_MASK_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_CMD_INT_MASK_0_H_BLANK_INT_MASK_MASKED _MK_ENUM_CONST(0) +#define DC_CMD_INT_MASK_0_H_BLANK_INT_MASK_NOTMASKED _MK_ENUM_CONST(1) + +#define DC_CMD_INT_MASK_0_V_PULSE3_INT_MASK_SHIFT _MK_SHIFT_CONST(4) +#define DC_CMD_INT_MASK_0_V_PULSE3_INT_MASK_FIELD _MK_FIELD_CONST(0x1, DC_CMD_INT_MASK_0_V_PULSE3_INT_MASK_SHIFT) +#define DC_CMD_INT_MASK_0_V_PULSE3_INT_MASK_RANGE 4:4 +#define DC_CMD_INT_MASK_0_V_PULSE3_INT_MASK_WOFFSET 0x0 +#define DC_CMD_INT_MASK_0_V_PULSE3_INT_MASK_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_INT_MASK_0_V_PULSE3_INT_MASK_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_CMD_INT_MASK_0_V_PULSE3_INT_MASK_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_INT_MASK_0_V_PULSE3_INT_MASK_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_CMD_INT_MASK_0_V_PULSE3_INT_MASK_MASKED _MK_ENUM_CONST(0) +#define DC_CMD_INT_MASK_0_V_PULSE3_INT_MASK_NOTMASKED _MK_ENUM_CONST(1) + +#define DC_CMD_INT_MASK_0_V_PULSE2_INT_MASK_SHIFT _MK_SHIFT_CONST(5) +#define DC_CMD_INT_MASK_0_V_PULSE2_INT_MASK_FIELD _MK_FIELD_CONST(0x1, DC_CMD_INT_MASK_0_V_PULSE2_INT_MASK_SHIFT) +#define DC_CMD_INT_MASK_0_V_PULSE2_INT_MASK_RANGE 5:5 +#define DC_CMD_INT_MASK_0_V_PULSE2_INT_MASK_WOFFSET 0x0 +#define DC_CMD_INT_MASK_0_V_PULSE2_INT_MASK_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_INT_MASK_0_V_PULSE2_INT_MASK_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_CMD_INT_MASK_0_V_PULSE2_INT_MASK_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_INT_MASK_0_V_PULSE2_INT_MASK_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_CMD_INT_MASK_0_V_PULSE2_INT_MASK_MASKED _MK_ENUM_CONST(0) +#define DC_CMD_INT_MASK_0_V_PULSE2_INT_MASK_NOTMASKED _MK_ENUM_CONST(1) + +#define DC_CMD_INT_MASK_0_SPI_BUSY_INT_MASK_SHIFT _MK_SHIFT_CONST(7) +#define DC_CMD_INT_MASK_0_SPI_BUSY_INT_MASK_FIELD _MK_FIELD_CONST(0x1, DC_CMD_INT_MASK_0_SPI_BUSY_INT_MASK_SHIFT) +#define DC_CMD_INT_MASK_0_SPI_BUSY_INT_MASK_RANGE 7:7 +#define DC_CMD_INT_MASK_0_SPI_BUSY_INT_MASK_WOFFSET 0x0 +#define DC_CMD_INT_MASK_0_SPI_BUSY_INT_MASK_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_INT_MASK_0_SPI_BUSY_INT_MASK_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_CMD_INT_MASK_0_SPI_BUSY_INT_MASK_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_INT_MASK_0_SPI_BUSY_INT_MASK_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_CMD_INT_MASK_0_SPI_BUSY_INT_MASK_MASKED _MK_ENUM_CONST(0) +#define DC_CMD_INT_MASK_0_SPI_BUSY_INT_MASK_NOTMASKED _MK_ENUM_CONST(1) + +#define DC_CMD_INT_MASK_0_WIN_A_UF_INT_MASK_SHIFT _MK_SHIFT_CONST(8) +#define DC_CMD_INT_MASK_0_WIN_A_UF_INT_MASK_FIELD _MK_FIELD_CONST(0x1, DC_CMD_INT_MASK_0_WIN_A_UF_INT_MASK_SHIFT) +#define DC_CMD_INT_MASK_0_WIN_A_UF_INT_MASK_RANGE 8:8 +#define DC_CMD_INT_MASK_0_WIN_A_UF_INT_MASK_WOFFSET 0x0 +#define DC_CMD_INT_MASK_0_WIN_A_UF_INT_MASK_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_INT_MASK_0_WIN_A_UF_INT_MASK_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_CMD_INT_MASK_0_WIN_A_UF_INT_MASK_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_INT_MASK_0_WIN_A_UF_INT_MASK_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_CMD_INT_MASK_0_WIN_A_UF_INT_MASK_MASKED _MK_ENUM_CONST(0) +#define DC_CMD_INT_MASK_0_WIN_A_UF_INT_MASK_NOTMASKED _MK_ENUM_CONST(1) + +#define DC_CMD_INT_MASK_0_WIN_B_UF_INT_MASK_SHIFT _MK_SHIFT_CONST(9) +#define DC_CMD_INT_MASK_0_WIN_B_UF_INT_MASK_FIELD _MK_FIELD_CONST(0x1, DC_CMD_INT_MASK_0_WIN_B_UF_INT_MASK_SHIFT) +#define DC_CMD_INT_MASK_0_WIN_B_UF_INT_MASK_RANGE 9:9 +#define DC_CMD_INT_MASK_0_WIN_B_UF_INT_MASK_WOFFSET 0x0 +#define DC_CMD_INT_MASK_0_WIN_B_UF_INT_MASK_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_INT_MASK_0_WIN_B_UF_INT_MASK_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_CMD_INT_MASK_0_WIN_B_UF_INT_MASK_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_INT_MASK_0_WIN_B_UF_INT_MASK_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_CMD_INT_MASK_0_WIN_B_UF_INT_MASK_MASKED _MK_ENUM_CONST(0) +#define DC_CMD_INT_MASK_0_WIN_B_UF_INT_MASK_NOTMASKED _MK_ENUM_CONST(1) + +#define DC_CMD_INT_MASK_0_WIN_C_UF_INT_MASK_SHIFT _MK_SHIFT_CONST(10) +#define DC_CMD_INT_MASK_0_WIN_C_UF_INT_MASK_FIELD _MK_FIELD_CONST(0x1, DC_CMD_INT_MASK_0_WIN_C_UF_INT_MASK_SHIFT) +#define DC_CMD_INT_MASK_0_WIN_C_UF_INT_MASK_RANGE 10:10 +#define DC_CMD_INT_MASK_0_WIN_C_UF_INT_MASK_WOFFSET 0x0 +#define DC_CMD_INT_MASK_0_WIN_C_UF_INT_MASK_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_INT_MASK_0_WIN_C_UF_INT_MASK_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_CMD_INT_MASK_0_WIN_C_UF_INT_MASK_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_INT_MASK_0_WIN_C_UF_INT_MASK_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_CMD_INT_MASK_0_WIN_C_UF_INT_MASK_MASKED _MK_ENUM_CONST(0) +#define DC_CMD_INT_MASK_0_WIN_C_UF_INT_MASK_NOTMASKED _MK_ENUM_CONST(1) + +#define DC_CMD_INT_MASK_0_MSF_INT_MASK_SHIFT _MK_SHIFT_CONST(12) +#define DC_CMD_INT_MASK_0_MSF_INT_MASK_FIELD _MK_FIELD_CONST(0x1, DC_CMD_INT_MASK_0_MSF_INT_MASK_SHIFT) +#define DC_CMD_INT_MASK_0_MSF_INT_MASK_RANGE 12:12 +#define DC_CMD_INT_MASK_0_MSF_INT_MASK_WOFFSET 0x0 +#define DC_CMD_INT_MASK_0_MSF_INT_MASK_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_INT_MASK_0_MSF_INT_MASK_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_CMD_INT_MASK_0_MSF_INT_MASK_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_INT_MASK_0_MSF_INT_MASK_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_CMD_INT_MASK_0_MSF_INT_MASK_MASKED _MK_ENUM_CONST(0) +#define DC_CMD_INT_MASK_0_MSF_INT_MASK_NOTMASKED _MK_ENUM_CONST(1) + +#define DC_CMD_INT_MASK_0_SSF_INT_MASK_SHIFT _MK_SHIFT_CONST(13) +#define DC_CMD_INT_MASK_0_SSF_INT_MASK_FIELD _MK_FIELD_CONST(0x1, DC_CMD_INT_MASK_0_SSF_INT_MASK_SHIFT) +#define DC_CMD_INT_MASK_0_SSF_INT_MASK_RANGE 13:13 +#define DC_CMD_INT_MASK_0_SSF_INT_MASK_WOFFSET 0x0 +#define DC_CMD_INT_MASK_0_SSF_INT_MASK_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_INT_MASK_0_SSF_INT_MASK_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_CMD_INT_MASK_0_SSF_INT_MASK_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_INT_MASK_0_SSF_INT_MASK_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_CMD_INT_MASK_0_SSF_INT_MASK_MASKED _MK_ENUM_CONST(0) +#define DC_CMD_INT_MASK_0_SSF_INT_MASK_NOTMASKED _MK_ENUM_CONST(1) + +#define DC_CMD_INT_MASK_0_WIN_A_OF_INT_MASK_SHIFT _MK_SHIFT_CONST(14) +#define DC_CMD_INT_MASK_0_WIN_A_OF_INT_MASK_FIELD _MK_FIELD_CONST(0x1, DC_CMD_INT_MASK_0_WIN_A_OF_INT_MASK_SHIFT) +#define DC_CMD_INT_MASK_0_WIN_A_OF_INT_MASK_RANGE 14:14 +#define DC_CMD_INT_MASK_0_WIN_A_OF_INT_MASK_WOFFSET 0x0 +#define DC_CMD_INT_MASK_0_WIN_A_OF_INT_MASK_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_INT_MASK_0_WIN_A_OF_INT_MASK_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_CMD_INT_MASK_0_WIN_A_OF_INT_MASK_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_INT_MASK_0_WIN_A_OF_INT_MASK_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_CMD_INT_MASK_0_WIN_A_OF_INT_MASK_MASKED _MK_ENUM_CONST(0) +#define DC_CMD_INT_MASK_0_WIN_A_OF_INT_MASK_NOTMASKED _MK_ENUM_CONST(1) + +#define DC_CMD_INT_MASK_0_WIN_B_OF_INT_MASK_SHIFT _MK_SHIFT_CONST(15) +#define DC_CMD_INT_MASK_0_WIN_B_OF_INT_MASK_FIELD _MK_FIELD_CONST(0x1, DC_CMD_INT_MASK_0_WIN_B_OF_INT_MASK_SHIFT) +#define DC_CMD_INT_MASK_0_WIN_B_OF_INT_MASK_RANGE 15:15 +#define DC_CMD_INT_MASK_0_WIN_B_OF_INT_MASK_WOFFSET 0x0 +#define DC_CMD_INT_MASK_0_WIN_B_OF_INT_MASK_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_INT_MASK_0_WIN_B_OF_INT_MASK_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_CMD_INT_MASK_0_WIN_B_OF_INT_MASK_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_INT_MASK_0_WIN_B_OF_INT_MASK_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_CMD_INT_MASK_0_WIN_B_OF_INT_MASK_MASKED _MK_ENUM_CONST(0) +#define DC_CMD_INT_MASK_0_WIN_B_OF_INT_MASK_NOTMASKED _MK_ENUM_CONST(1) + +#define DC_CMD_INT_MASK_0_WIN_C_OF_INT_MASK_SHIFT _MK_SHIFT_CONST(16) +#define DC_CMD_INT_MASK_0_WIN_C_OF_INT_MASK_FIELD _MK_FIELD_CONST(0x1, DC_CMD_INT_MASK_0_WIN_C_OF_INT_MASK_SHIFT) +#define DC_CMD_INT_MASK_0_WIN_C_OF_INT_MASK_RANGE 16:16 +#define DC_CMD_INT_MASK_0_WIN_C_OF_INT_MASK_WOFFSET 0x0 +#define DC_CMD_INT_MASK_0_WIN_C_OF_INT_MASK_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_INT_MASK_0_WIN_C_OF_INT_MASK_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_CMD_INT_MASK_0_WIN_C_OF_INT_MASK_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_INT_MASK_0_WIN_C_OF_INT_MASK_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_CMD_INT_MASK_0_WIN_C_OF_INT_MASK_MASKED _MK_ENUM_CONST(0) +#define DC_CMD_INT_MASK_0_WIN_C_OF_INT_MASK_NOTMASKED _MK_ENUM_CONST(1) + +#define DC_CMD_INT_MASK_0_CMU_LUT_CONFLICT_INT_MASK_SHIFT _MK_SHIFT_CONST(22) +#define DC_CMD_INT_MASK_0_CMU_LUT_CONFLICT_INT_MASK_FIELD _MK_FIELD_CONST(0x1, DC_CMD_INT_MASK_0_CMU_LUT_CONFLICT_INT_MASK_SHIFT) +#define DC_CMD_INT_MASK_0_CMU_LUT_CONFLICT_INT_MASK_RANGE 22:22 +#define DC_CMD_INT_MASK_0_CMU_LUT_CONFLICT_INT_MASK_WOFFSET 0x0 +#define DC_CMD_INT_MASK_0_CMU_LUT_CONFLICT_INT_MASK_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_INT_MASK_0_CMU_LUT_CONFLICT_INT_MASK_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_CMD_INT_MASK_0_CMU_LUT_CONFLICT_INT_MASK_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_INT_MASK_0_CMU_LUT_CONFLICT_INT_MASK_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_CMD_INT_MASK_0_CMU_LUT_CONFLICT_INT_MASK_MASKED _MK_ENUM_CONST(0) +#define DC_CMD_INT_MASK_0_CMU_LUT_CONFLICT_INT_MASK_NOTMASKED _MK_ENUM_CONST(1) + +#define DC_CMD_INT_MASK_0_HC_UF_INT_MASK_SHIFT _MK_SHIFT_CONST(23) +#define DC_CMD_INT_MASK_0_HC_UF_INT_MASK_FIELD _MK_FIELD_CONST(0x1, DC_CMD_INT_MASK_0_HC_UF_INT_MASK_SHIFT) +#define DC_CMD_INT_MASK_0_HC_UF_INT_MASK_RANGE 23:23 +#define DC_CMD_INT_MASK_0_HC_UF_INT_MASK_WOFFSET 0x0 +#define DC_CMD_INT_MASK_0_HC_UF_INT_MASK_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_INT_MASK_0_HC_UF_INT_MASK_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_CMD_INT_MASK_0_HC_UF_INT_MASK_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_INT_MASK_0_HC_UF_INT_MASK_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_CMD_INT_MASK_0_HC_UF_INT_MASK_MASKED _MK_ENUM_CONST(0) +#define DC_CMD_INT_MASK_0_HC_UF_INT_MASK_NOTMASKED _MK_ENUM_CONST(1) + +#define DC_CMD_INT_MASK_0_WIN_D_UF_INT_MASK_SHIFT _MK_SHIFT_CONST(24) +#define DC_CMD_INT_MASK_0_WIN_D_UF_INT_MASK_FIELD _MK_FIELD_CONST(0x1, DC_CMD_INT_MASK_0_WIN_D_UF_INT_MASK_SHIFT) +#define DC_CMD_INT_MASK_0_WIN_D_UF_INT_MASK_RANGE 24:24 +#define DC_CMD_INT_MASK_0_WIN_D_UF_INT_MASK_WOFFSET 0x0 +#define DC_CMD_INT_MASK_0_WIN_D_UF_INT_MASK_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_INT_MASK_0_WIN_D_UF_INT_MASK_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_CMD_INT_MASK_0_WIN_D_UF_INT_MASK_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_INT_MASK_0_WIN_D_UF_INT_MASK_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_CMD_INT_MASK_0_WIN_D_UF_INT_MASK_MASKED _MK_ENUM_CONST(0) +#define DC_CMD_INT_MASK_0_WIN_D_UF_INT_MASK_NOTMASKED _MK_ENUM_CONST(1) + +#define DC_CMD_INT_MASK_0_WIN_T_UF_INT_MASK_SHIFT _MK_SHIFT_CONST(25) +#define DC_CMD_INT_MASK_0_WIN_T_UF_INT_MASK_FIELD _MK_FIELD_CONST(0x1, DC_CMD_INT_MASK_0_WIN_T_UF_INT_MASK_SHIFT) +#define DC_CMD_INT_MASK_0_WIN_T_UF_INT_MASK_RANGE 25:25 +#define DC_CMD_INT_MASK_0_WIN_T_UF_INT_MASK_WOFFSET 0x0 +#define DC_CMD_INT_MASK_0_WIN_T_UF_INT_MASK_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_INT_MASK_0_WIN_T_UF_INT_MASK_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_CMD_INT_MASK_0_WIN_T_UF_INT_MASK_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_INT_MASK_0_WIN_T_UF_INT_MASK_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_CMD_INT_MASK_0_WIN_T_UF_INT_MASK_MASKED _MK_ENUM_CONST(0) +#define DC_CMD_INT_MASK_0_WIN_T_UF_INT_MASK_NOTMASKED _MK_ENUM_CONST(1) + + +// Register DC_CMD_INT_ENABLE_0 +#define DC_CMD_INT_ENABLE_0 _MK_ADDR_CONST(0x39) +#define DC_CMD_INT_ENABLE_0_SECURE 0x0 +#define DC_CMD_INT_ENABLE_0_WORD_COUNT 0x1 +#define DC_CMD_INT_ENABLE_0_RESET_VAL _MK_MASK_CONST(0x1) +#define DC_CMD_INT_ENABLE_0_RESET_MASK _MK_MASK_CONST(0x3c1f7bf) +#define DC_CMD_INT_ENABLE_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_CMD_INT_ENABLE_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_CMD_INT_ENABLE_0_READ_MASK _MK_MASK_CONST(0x3c1f7bf) +#define DC_CMD_INT_ENABLE_0_WRITE_MASK _MK_MASK_CONST(0x3c1f7bf) +#define DC_CMD_INT_ENABLE_0_CTXSW_INT_ENABLE_SHIFT _MK_SHIFT_CONST(0) +#define DC_CMD_INT_ENABLE_0_CTXSW_INT_ENABLE_FIELD _MK_FIELD_CONST(0x1, DC_CMD_INT_ENABLE_0_CTXSW_INT_ENABLE_SHIFT) +#define DC_CMD_INT_ENABLE_0_CTXSW_INT_ENABLE_RANGE 0:0 +#define DC_CMD_INT_ENABLE_0_CTXSW_INT_ENABLE_WOFFSET 0x0 +#define DC_CMD_INT_ENABLE_0_CTXSW_INT_ENABLE_DEFAULT _MK_MASK_CONST(0x1) +#define DC_CMD_INT_ENABLE_0_CTXSW_INT_ENABLE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_CMD_INT_ENABLE_0_CTXSW_INT_ENABLE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_INT_ENABLE_0_CTXSW_INT_ENABLE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_CMD_INT_ENABLE_0_CTXSW_INT_ENABLE_DISABLE _MK_ENUM_CONST(0) +#define DC_CMD_INT_ENABLE_0_CTXSW_INT_ENABLE_ENABLE _MK_ENUM_CONST(1) + +#define DC_CMD_INT_ENABLE_0_FRAME_END_INT_ENABLE_SHIFT _MK_SHIFT_CONST(1) +#define DC_CMD_INT_ENABLE_0_FRAME_END_INT_ENABLE_FIELD _MK_FIELD_CONST(0x1, DC_CMD_INT_ENABLE_0_FRAME_END_INT_ENABLE_SHIFT) +#define DC_CMD_INT_ENABLE_0_FRAME_END_INT_ENABLE_RANGE 1:1 +#define DC_CMD_INT_ENABLE_0_FRAME_END_INT_ENABLE_WOFFSET 0x0 +#define DC_CMD_INT_ENABLE_0_FRAME_END_INT_ENABLE_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_INT_ENABLE_0_FRAME_END_INT_ENABLE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_CMD_INT_ENABLE_0_FRAME_END_INT_ENABLE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_INT_ENABLE_0_FRAME_END_INT_ENABLE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_CMD_INT_ENABLE_0_FRAME_END_INT_ENABLE_DISABLE _MK_ENUM_CONST(0) +#define DC_CMD_INT_ENABLE_0_FRAME_END_INT_ENABLE_ENABLE _MK_ENUM_CONST(1) + +#define DC_CMD_INT_ENABLE_0_V_BLANK_INT_ENABLE_SHIFT _MK_SHIFT_CONST(2) +#define DC_CMD_INT_ENABLE_0_V_BLANK_INT_ENABLE_FIELD _MK_FIELD_CONST(0x1, DC_CMD_INT_ENABLE_0_V_BLANK_INT_ENABLE_SHIFT) +#define DC_CMD_INT_ENABLE_0_V_BLANK_INT_ENABLE_RANGE 2:2 +#define DC_CMD_INT_ENABLE_0_V_BLANK_INT_ENABLE_WOFFSET 0x0 +#define DC_CMD_INT_ENABLE_0_V_BLANK_INT_ENABLE_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_INT_ENABLE_0_V_BLANK_INT_ENABLE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_CMD_INT_ENABLE_0_V_BLANK_INT_ENABLE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_INT_ENABLE_0_V_BLANK_INT_ENABLE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_CMD_INT_ENABLE_0_V_BLANK_INT_ENABLE_DISABLE _MK_ENUM_CONST(0) +#define DC_CMD_INT_ENABLE_0_V_BLANK_INT_ENABLE_ENABLE _MK_ENUM_CONST(1) + +#define DC_CMD_INT_ENABLE_0_H_BLANK_INT_ENABLE_SHIFT _MK_SHIFT_CONST(3) +#define DC_CMD_INT_ENABLE_0_H_BLANK_INT_ENABLE_FIELD _MK_FIELD_CONST(0x1, DC_CMD_INT_ENABLE_0_H_BLANK_INT_ENABLE_SHIFT) +#define DC_CMD_INT_ENABLE_0_H_BLANK_INT_ENABLE_RANGE 3:3 +#define DC_CMD_INT_ENABLE_0_H_BLANK_INT_ENABLE_WOFFSET 0x0 +#define DC_CMD_INT_ENABLE_0_H_BLANK_INT_ENABLE_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_INT_ENABLE_0_H_BLANK_INT_ENABLE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_CMD_INT_ENABLE_0_H_BLANK_INT_ENABLE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_INT_ENABLE_0_H_BLANK_INT_ENABLE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_CMD_INT_ENABLE_0_H_BLANK_INT_ENABLE_DISABLE _MK_ENUM_CONST(0) +#define DC_CMD_INT_ENABLE_0_H_BLANK_INT_ENABLE_ENABLE _MK_ENUM_CONST(1) + +#define DC_CMD_INT_ENABLE_0_V_PULSE3_INT_ENABLE_SHIFT _MK_SHIFT_CONST(4) +#define DC_CMD_INT_ENABLE_0_V_PULSE3_INT_ENABLE_FIELD _MK_FIELD_CONST(0x1, DC_CMD_INT_ENABLE_0_V_PULSE3_INT_ENABLE_SHIFT) +#define DC_CMD_INT_ENABLE_0_V_PULSE3_INT_ENABLE_RANGE 4:4 +#define DC_CMD_INT_ENABLE_0_V_PULSE3_INT_ENABLE_WOFFSET 0x0 +#define DC_CMD_INT_ENABLE_0_V_PULSE3_INT_ENABLE_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_INT_ENABLE_0_V_PULSE3_INT_ENABLE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_CMD_INT_ENABLE_0_V_PULSE3_INT_ENABLE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_INT_ENABLE_0_V_PULSE3_INT_ENABLE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_CMD_INT_ENABLE_0_V_PULSE3_INT_ENABLE_DISABLE _MK_ENUM_CONST(0) +#define DC_CMD_INT_ENABLE_0_V_PULSE3_INT_ENABLE_ENABLE _MK_ENUM_CONST(1) + +#define DC_CMD_INT_ENABLE_0_V_PULSE2_INT_ENABLE_SHIFT _MK_SHIFT_CONST(5) +#define DC_CMD_INT_ENABLE_0_V_PULSE2_INT_ENABLE_FIELD _MK_FIELD_CONST(0x1, DC_CMD_INT_ENABLE_0_V_PULSE2_INT_ENABLE_SHIFT) +#define DC_CMD_INT_ENABLE_0_V_PULSE2_INT_ENABLE_RANGE 5:5 +#define DC_CMD_INT_ENABLE_0_V_PULSE2_INT_ENABLE_WOFFSET 0x0 +#define DC_CMD_INT_ENABLE_0_V_PULSE2_INT_ENABLE_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_INT_ENABLE_0_V_PULSE2_INT_ENABLE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_CMD_INT_ENABLE_0_V_PULSE2_INT_ENABLE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_INT_ENABLE_0_V_PULSE2_INT_ENABLE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_CMD_INT_ENABLE_0_V_PULSE2_INT_ENABLE_DISABLE _MK_ENUM_CONST(0) +#define DC_CMD_INT_ENABLE_0_V_PULSE2_INT_ENABLE_ENABLE _MK_ENUM_CONST(1) + +#define DC_CMD_INT_ENABLE_0_SPI_BUSY_INT_ENABLE_SHIFT _MK_SHIFT_CONST(7) +#define DC_CMD_INT_ENABLE_0_SPI_BUSY_INT_ENABLE_FIELD _MK_FIELD_CONST(0x1, DC_CMD_INT_ENABLE_0_SPI_BUSY_INT_ENABLE_SHIFT) +#define DC_CMD_INT_ENABLE_0_SPI_BUSY_INT_ENABLE_RANGE 7:7 +#define DC_CMD_INT_ENABLE_0_SPI_BUSY_INT_ENABLE_WOFFSET 0x0 +#define DC_CMD_INT_ENABLE_0_SPI_BUSY_INT_ENABLE_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_INT_ENABLE_0_SPI_BUSY_INT_ENABLE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_CMD_INT_ENABLE_0_SPI_BUSY_INT_ENABLE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_INT_ENABLE_0_SPI_BUSY_INT_ENABLE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_CMD_INT_ENABLE_0_SPI_BUSY_INT_ENABLE_DISABLE _MK_ENUM_CONST(0) +#define DC_CMD_INT_ENABLE_0_SPI_BUSY_INT_ENABLE_ENABLE _MK_ENUM_CONST(1) + +#define DC_CMD_INT_ENABLE_0_WIN_A_UF_INT_ENABLE_SHIFT _MK_SHIFT_CONST(8) +#define DC_CMD_INT_ENABLE_0_WIN_A_UF_INT_ENABLE_FIELD _MK_FIELD_CONST(0x1, DC_CMD_INT_ENABLE_0_WIN_A_UF_INT_ENABLE_SHIFT) +#define DC_CMD_INT_ENABLE_0_WIN_A_UF_INT_ENABLE_RANGE 8:8 +#define DC_CMD_INT_ENABLE_0_WIN_A_UF_INT_ENABLE_WOFFSET 0x0 +#define DC_CMD_INT_ENABLE_0_WIN_A_UF_INT_ENABLE_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_INT_ENABLE_0_WIN_A_UF_INT_ENABLE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_CMD_INT_ENABLE_0_WIN_A_UF_INT_ENABLE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_INT_ENABLE_0_WIN_A_UF_INT_ENABLE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_CMD_INT_ENABLE_0_WIN_A_UF_INT_ENABLE_DISABLE _MK_ENUM_CONST(0) +#define DC_CMD_INT_ENABLE_0_WIN_A_UF_INT_ENABLE_ENABLE _MK_ENUM_CONST(1) + +#define DC_CMD_INT_ENABLE_0_WIN_B_UF_INT_ENABLE_SHIFT _MK_SHIFT_CONST(9) +#define DC_CMD_INT_ENABLE_0_WIN_B_UF_INT_ENABLE_FIELD _MK_FIELD_CONST(0x1, DC_CMD_INT_ENABLE_0_WIN_B_UF_INT_ENABLE_SHIFT) +#define DC_CMD_INT_ENABLE_0_WIN_B_UF_INT_ENABLE_RANGE 9:9 +#define DC_CMD_INT_ENABLE_0_WIN_B_UF_INT_ENABLE_WOFFSET 0x0 +#define DC_CMD_INT_ENABLE_0_WIN_B_UF_INT_ENABLE_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_INT_ENABLE_0_WIN_B_UF_INT_ENABLE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_CMD_INT_ENABLE_0_WIN_B_UF_INT_ENABLE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_INT_ENABLE_0_WIN_B_UF_INT_ENABLE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_CMD_INT_ENABLE_0_WIN_B_UF_INT_ENABLE_DISABLE _MK_ENUM_CONST(0) +#define DC_CMD_INT_ENABLE_0_WIN_B_UF_INT_ENABLE_ENABLE _MK_ENUM_CONST(1) + +#define DC_CMD_INT_ENABLE_0_WIN_C_UF_INT_ENABLE_SHIFT _MK_SHIFT_CONST(10) +#define DC_CMD_INT_ENABLE_0_WIN_C_UF_INT_ENABLE_FIELD _MK_FIELD_CONST(0x1, DC_CMD_INT_ENABLE_0_WIN_C_UF_INT_ENABLE_SHIFT) +#define DC_CMD_INT_ENABLE_0_WIN_C_UF_INT_ENABLE_RANGE 10:10 +#define DC_CMD_INT_ENABLE_0_WIN_C_UF_INT_ENABLE_WOFFSET 0x0 +#define DC_CMD_INT_ENABLE_0_WIN_C_UF_INT_ENABLE_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_INT_ENABLE_0_WIN_C_UF_INT_ENABLE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_CMD_INT_ENABLE_0_WIN_C_UF_INT_ENABLE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_INT_ENABLE_0_WIN_C_UF_INT_ENABLE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_CMD_INT_ENABLE_0_WIN_C_UF_INT_ENABLE_DISABLE _MK_ENUM_CONST(0) +#define DC_CMD_INT_ENABLE_0_WIN_C_UF_INT_ENABLE_ENABLE _MK_ENUM_CONST(1) + +#define DC_CMD_INT_ENABLE_0_MSF_INT_ENABLE_SHIFT _MK_SHIFT_CONST(12) +#define DC_CMD_INT_ENABLE_0_MSF_INT_ENABLE_FIELD _MK_FIELD_CONST(0x1, DC_CMD_INT_ENABLE_0_MSF_INT_ENABLE_SHIFT) +#define DC_CMD_INT_ENABLE_0_MSF_INT_ENABLE_RANGE 12:12 +#define DC_CMD_INT_ENABLE_0_MSF_INT_ENABLE_WOFFSET 0x0 +#define DC_CMD_INT_ENABLE_0_MSF_INT_ENABLE_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_INT_ENABLE_0_MSF_INT_ENABLE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_CMD_INT_ENABLE_0_MSF_INT_ENABLE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_INT_ENABLE_0_MSF_INT_ENABLE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_CMD_INT_ENABLE_0_MSF_INT_ENABLE_DISABLE _MK_ENUM_CONST(0) +#define DC_CMD_INT_ENABLE_0_MSF_INT_ENABLE_ENABLE _MK_ENUM_CONST(1) + +#define DC_CMD_INT_ENABLE_0_SSF_INT_ENABLE_SHIFT _MK_SHIFT_CONST(13) +#define DC_CMD_INT_ENABLE_0_SSF_INT_ENABLE_FIELD _MK_FIELD_CONST(0x1, DC_CMD_INT_ENABLE_0_SSF_INT_ENABLE_SHIFT) +#define DC_CMD_INT_ENABLE_0_SSF_INT_ENABLE_RANGE 13:13 +#define DC_CMD_INT_ENABLE_0_SSF_INT_ENABLE_WOFFSET 0x0 +#define DC_CMD_INT_ENABLE_0_SSF_INT_ENABLE_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_INT_ENABLE_0_SSF_INT_ENABLE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_CMD_INT_ENABLE_0_SSF_INT_ENABLE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_INT_ENABLE_0_SSF_INT_ENABLE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_CMD_INT_ENABLE_0_SSF_INT_ENABLE_DISABLE _MK_ENUM_CONST(0) +#define DC_CMD_INT_ENABLE_0_SSF_INT_ENABLE_ENABLE _MK_ENUM_CONST(1) + +#define DC_CMD_INT_ENABLE_0_WIN_A_OF_INT_ENABLE_SHIFT _MK_SHIFT_CONST(14) +#define DC_CMD_INT_ENABLE_0_WIN_A_OF_INT_ENABLE_FIELD _MK_FIELD_CONST(0x1, DC_CMD_INT_ENABLE_0_WIN_A_OF_INT_ENABLE_SHIFT) +#define DC_CMD_INT_ENABLE_0_WIN_A_OF_INT_ENABLE_RANGE 14:14 +#define DC_CMD_INT_ENABLE_0_WIN_A_OF_INT_ENABLE_WOFFSET 0x0 +#define DC_CMD_INT_ENABLE_0_WIN_A_OF_INT_ENABLE_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_INT_ENABLE_0_WIN_A_OF_INT_ENABLE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_CMD_INT_ENABLE_0_WIN_A_OF_INT_ENABLE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_INT_ENABLE_0_WIN_A_OF_INT_ENABLE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_CMD_INT_ENABLE_0_WIN_A_OF_INT_ENABLE_DISABLE _MK_ENUM_CONST(0) +#define DC_CMD_INT_ENABLE_0_WIN_A_OF_INT_ENABLE_ENABLE _MK_ENUM_CONST(1) + +#define DC_CMD_INT_ENABLE_0_WIN_B_OF_INT_ENABLE_SHIFT _MK_SHIFT_CONST(15) +#define DC_CMD_INT_ENABLE_0_WIN_B_OF_INT_ENABLE_FIELD _MK_FIELD_CONST(0x1, DC_CMD_INT_ENABLE_0_WIN_B_OF_INT_ENABLE_SHIFT) +#define DC_CMD_INT_ENABLE_0_WIN_B_OF_INT_ENABLE_RANGE 15:15 +#define DC_CMD_INT_ENABLE_0_WIN_B_OF_INT_ENABLE_WOFFSET 0x0 +#define DC_CMD_INT_ENABLE_0_WIN_B_OF_INT_ENABLE_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_INT_ENABLE_0_WIN_B_OF_INT_ENABLE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_CMD_INT_ENABLE_0_WIN_B_OF_INT_ENABLE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_INT_ENABLE_0_WIN_B_OF_INT_ENABLE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_CMD_INT_ENABLE_0_WIN_B_OF_INT_ENABLE_DISABLE _MK_ENUM_CONST(0) +#define DC_CMD_INT_ENABLE_0_WIN_B_OF_INT_ENABLE_ENABLE _MK_ENUM_CONST(1) + +#define DC_CMD_INT_ENABLE_0_WIN_C_OF_INT_ENABLE_SHIFT _MK_SHIFT_CONST(16) +#define DC_CMD_INT_ENABLE_0_WIN_C_OF_INT_ENABLE_FIELD _MK_FIELD_CONST(0x1, DC_CMD_INT_ENABLE_0_WIN_C_OF_INT_ENABLE_SHIFT) +#define DC_CMD_INT_ENABLE_0_WIN_C_OF_INT_ENABLE_RANGE 16:16 +#define DC_CMD_INT_ENABLE_0_WIN_C_OF_INT_ENABLE_WOFFSET 0x0 +#define DC_CMD_INT_ENABLE_0_WIN_C_OF_INT_ENABLE_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_INT_ENABLE_0_WIN_C_OF_INT_ENABLE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_CMD_INT_ENABLE_0_WIN_C_OF_INT_ENABLE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_INT_ENABLE_0_WIN_C_OF_INT_ENABLE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_CMD_INT_ENABLE_0_WIN_C_OF_INT_ENABLE_DISABLE _MK_ENUM_CONST(0) +#define DC_CMD_INT_ENABLE_0_WIN_C_OF_INT_ENABLE_ENABLE _MK_ENUM_CONST(1) + +#define DC_CMD_INT_ENABLE_0_CMU_LUT_CONFLICT_INT_ENABLE_SHIFT _MK_SHIFT_CONST(22) +#define DC_CMD_INT_ENABLE_0_CMU_LUT_CONFLICT_INT_ENABLE_FIELD _MK_FIELD_CONST(0x1, DC_CMD_INT_ENABLE_0_CMU_LUT_CONFLICT_INT_ENABLE_SHIFT) +#define DC_CMD_INT_ENABLE_0_CMU_LUT_CONFLICT_INT_ENABLE_RANGE 22:22 +#define DC_CMD_INT_ENABLE_0_CMU_LUT_CONFLICT_INT_ENABLE_WOFFSET 0x0 +#define DC_CMD_INT_ENABLE_0_CMU_LUT_CONFLICT_INT_ENABLE_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_INT_ENABLE_0_CMU_LUT_CONFLICT_INT_ENABLE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_CMD_INT_ENABLE_0_CMU_LUT_CONFLICT_INT_ENABLE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_INT_ENABLE_0_CMU_LUT_CONFLICT_INT_ENABLE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_CMD_INT_ENABLE_0_CMU_LUT_CONFLICT_INT_ENABLE_DISABLE _MK_ENUM_CONST(0) +#define DC_CMD_INT_ENABLE_0_CMU_LUT_CONFLICT_INT_ENABLE_ENABLE _MK_ENUM_CONST(1) + +#define DC_CMD_INT_ENABLE_0_HC_UF_INT_ENABLE_SHIFT _MK_SHIFT_CONST(23) +#define DC_CMD_INT_ENABLE_0_HC_UF_INT_ENABLE_FIELD _MK_FIELD_CONST(0x1, DC_CMD_INT_ENABLE_0_HC_UF_INT_ENABLE_SHIFT) +#define DC_CMD_INT_ENABLE_0_HC_UF_INT_ENABLE_RANGE 23:23 +#define DC_CMD_INT_ENABLE_0_HC_UF_INT_ENABLE_WOFFSET 0x0 +#define DC_CMD_INT_ENABLE_0_HC_UF_INT_ENABLE_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_INT_ENABLE_0_HC_UF_INT_ENABLE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_CMD_INT_ENABLE_0_HC_UF_INT_ENABLE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_INT_ENABLE_0_HC_UF_INT_ENABLE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_CMD_INT_ENABLE_0_HC_UF_INT_ENABLE_DISABLE _MK_ENUM_CONST(0) +#define DC_CMD_INT_ENABLE_0_HC_UF_INT_ENABLE_ENABLE _MK_ENUM_CONST(1) + +#define DC_CMD_INT_ENABLE_0_WIN_D_UF_INT_ENABLE_SHIFT _MK_SHIFT_CONST(24) +#define DC_CMD_INT_ENABLE_0_WIN_D_UF_INT_ENABLE_FIELD _MK_FIELD_CONST(0x1, DC_CMD_INT_ENABLE_0_WIN_D_UF_INT_ENABLE_SHIFT) +#define DC_CMD_INT_ENABLE_0_WIN_D_UF_INT_ENABLE_RANGE 24:24 +#define DC_CMD_INT_ENABLE_0_WIN_D_UF_INT_ENABLE_WOFFSET 0x0 +#define DC_CMD_INT_ENABLE_0_WIN_D_UF_INT_ENABLE_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_INT_ENABLE_0_WIN_D_UF_INT_ENABLE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_CMD_INT_ENABLE_0_WIN_D_UF_INT_ENABLE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_INT_ENABLE_0_WIN_D_UF_INT_ENABLE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_CMD_INT_ENABLE_0_WIN_D_UF_INT_ENABLE_DISABLE _MK_ENUM_CONST(0) +#define DC_CMD_INT_ENABLE_0_WIN_D_UF_INT_ENABLE_ENABLE _MK_ENUM_CONST(1) + +#define DC_CMD_INT_ENABLE_0_WIN_T_UF_INT_ENABLE_SHIFT _MK_SHIFT_CONST(25) +#define DC_CMD_INT_ENABLE_0_WIN_T_UF_INT_ENABLE_FIELD _MK_FIELD_CONST(0x1, DC_CMD_INT_ENABLE_0_WIN_T_UF_INT_ENABLE_SHIFT) +#define DC_CMD_INT_ENABLE_0_WIN_T_UF_INT_ENABLE_RANGE 25:25 +#define DC_CMD_INT_ENABLE_0_WIN_T_UF_INT_ENABLE_WOFFSET 0x0 +#define DC_CMD_INT_ENABLE_0_WIN_T_UF_INT_ENABLE_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_INT_ENABLE_0_WIN_T_UF_INT_ENABLE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_CMD_INT_ENABLE_0_WIN_T_UF_INT_ENABLE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_INT_ENABLE_0_WIN_T_UF_INT_ENABLE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_CMD_INT_ENABLE_0_WIN_T_UF_INT_ENABLE_DISABLE _MK_ENUM_CONST(0) +#define DC_CMD_INT_ENABLE_0_WIN_T_UF_INT_ENABLE_ENABLE _MK_ENUM_CONST(1) + + +// Register DC_CMD_INT_TYPE_0 +#define DC_CMD_INT_TYPE_0 _MK_ADDR_CONST(0x3a) +#define DC_CMD_INT_TYPE_0_SECURE 0x0 +#define DC_CMD_INT_TYPE_0_WORD_COUNT 0x1 +#define DC_CMD_INT_TYPE_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_CMD_INT_TYPE_0_RESET_MASK _MK_MASK_CONST(0x3c1f7be) +#define DC_CMD_INT_TYPE_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_CMD_INT_TYPE_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_CMD_INT_TYPE_0_READ_MASK _MK_MASK_CONST(0x3c1f7be) +#define DC_CMD_INT_TYPE_0_WRITE_MASK _MK_MASK_CONST(0x3c1f7be) +#define DC_CMD_INT_TYPE_0_FRAME_END_INT_TYPE_SHIFT _MK_SHIFT_CONST(1) +#define DC_CMD_INT_TYPE_0_FRAME_END_INT_TYPE_FIELD _MK_FIELD_CONST(0x1, DC_CMD_INT_TYPE_0_FRAME_END_INT_TYPE_SHIFT) +#define DC_CMD_INT_TYPE_0_FRAME_END_INT_TYPE_RANGE 1:1 +#define DC_CMD_INT_TYPE_0_FRAME_END_INT_TYPE_WOFFSET 0x0 +#define DC_CMD_INT_TYPE_0_FRAME_END_INT_TYPE_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_INT_TYPE_0_FRAME_END_INT_TYPE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_CMD_INT_TYPE_0_FRAME_END_INT_TYPE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_INT_TYPE_0_FRAME_END_INT_TYPE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_CMD_INT_TYPE_0_FRAME_END_INT_TYPE_EDGE _MK_ENUM_CONST(0) +#define DC_CMD_INT_TYPE_0_FRAME_END_INT_TYPE_LEVEL _MK_ENUM_CONST(1) + +#define DC_CMD_INT_TYPE_0_V_BLANK_INT_TYPE_SHIFT _MK_SHIFT_CONST(2) +#define DC_CMD_INT_TYPE_0_V_BLANK_INT_TYPE_FIELD _MK_FIELD_CONST(0x1, DC_CMD_INT_TYPE_0_V_BLANK_INT_TYPE_SHIFT) +#define DC_CMD_INT_TYPE_0_V_BLANK_INT_TYPE_RANGE 2:2 +#define DC_CMD_INT_TYPE_0_V_BLANK_INT_TYPE_WOFFSET 0x0 +#define DC_CMD_INT_TYPE_0_V_BLANK_INT_TYPE_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_INT_TYPE_0_V_BLANK_INT_TYPE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_CMD_INT_TYPE_0_V_BLANK_INT_TYPE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_INT_TYPE_0_V_BLANK_INT_TYPE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_CMD_INT_TYPE_0_V_BLANK_INT_TYPE_EDGE _MK_ENUM_CONST(0) +#define DC_CMD_INT_TYPE_0_V_BLANK_INT_TYPE_LEVEL _MK_ENUM_CONST(1) + +#define DC_CMD_INT_TYPE_0_H_BLANK_INT_TYPE_SHIFT _MK_SHIFT_CONST(3) +#define DC_CMD_INT_TYPE_0_H_BLANK_INT_TYPE_FIELD _MK_FIELD_CONST(0x1, DC_CMD_INT_TYPE_0_H_BLANK_INT_TYPE_SHIFT) +#define DC_CMD_INT_TYPE_0_H_BLANK_INT_TYPE_RANGE 3:3 +#define DC_CMD_INT_TYPE_0_H_BLANK_INT_TYPE_WOFFSET 0x0 +#define DC_CMD_INT_TYPE_0_H_BLANK_INT_TYPE_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_INT_TYPE_0_H_BLANK_INT_TYPE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_CMD_INT_TYPE_0_H_BLANK_INT_TYPE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_INT_TYPE_0_H_BLANK_INT_TYPE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_CMD_INT_TYPE_0_H_BLANK_INT_TYPE_EDGE _MK_ENUM_CONST(0) +#define DC_CMD_INT_TYPE_0_H_BLANK_INT_TYPE_LEVEL _MK_ENUM_CONST(1) + +#define DC_CMD_INT_TYPE_0_V_PULSE3_INT_TYPE_SHIFT _MK_SHIFT_CONST(4) +#define DC_CMD_INT_TYPE_0_V_PULSE3_INT_TYPE_FIELD _MK_FIELD_CONST(0x1, DC_CMD_INT_TYPE_0_V_PULSE3_INT_TYPE_SHIFT) +#define DC_CMD_INT_TYPE_0_V_PULSE3_INT_TYPE_RANGE 4:4 +#define DC_CMD_INT_TYPE_0_V_PULSE3_INT_TYPE_WOFFSET 0x0 +#define DC_CMD_INT_TYPE_0_V_PULSE3_INT_TYPE_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_INT_TYPE_0_V_PULSE3_INT_TYPE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_CMD_INT_TYPE_0_V_PULSE3_INT_TYPE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_INT_TYPE_0_V_PULSE3_INT_TYPE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_CMD_INT_TYPE_0_V_PULSE3_INT_TYPE_EDGE _MK_ENUM_CONST(0) +#define DC_CMD_INT_TYPE_0_V_PULSE3_INT_TYPE_LEVEL _MK_ENUM_CONST(1) + +#define DC_CMD_INT_TYPE_0_V_PULSE2_INT_TYPE_SHIFT _MK_SHIFT_CONST(5) +#define DC_CMD_INT_TYPE_0_V_PULSE2_INT_TYPE_FIELD _MK_FIELD_CONST(0x1, DC_CMD_INT_TYPE_0_V_PULSE2_INT_TYPE_SHIFT) +#define DC_CMD_INT_TYPE_0_V_PULSE2_INT_TYPE_RANGE 5:5 +#define DC_CMD_INT_TYPE_0_V_PULSE2_INT_TYPE_WOFFSET 0x0 +#define DC_CMD_INT_TYPE_0_V_PULSE2_INT_TYPE_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_INT_TYPE_0_V_PULSE2_INT_TYPE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_CMD_INT_TYPE_0_V_PULSE2_INT_TYPE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_INT_TYPE_0_V_PULSE2_INT_TYPE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_CMD_INT_TYPE_0_V_PULSE2_INT_TYPE_EDGE _MK_ENUM_CONST(0) +#define DC_CMD_INT_TYPE_0_V_PULSE2_INT_TYPE_LEVEL _MK_ENUM_CONST(1) + +#define DC_CMD_INT_TYPE_0_SPI_BUSY_INT_TYPE_SHIFT _MK_SHIFT_CONST(7) +#define DC_CMD_INT_TYPE_0_SPI_BUSY_INT_TYPE_FIELD _MK_FIELD_CONST(0x1, DC_CMD_INT_TYPE_0_SPI_BUSY_INT_TYPE_SHIFT) +#define DC_CMD_INT_TYPE_0_SPI_BUSY_INT_TYPE_RANGE 7:7 +#define DC_CMD_INT_TYPE_0_SPI_BUSY_INT_TYPE_WOFFSET 0x0 +#define DC_CMD_INT_TYPE_0_SPI_BUSY_INT_TYPE_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_INT_TYPE_0_SPI_BUSY_INT_TYPE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_CMD_INT_TYPE_0_SPI_BUSY_INT_TYPE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_INT_TYPE_0_SPI_BUSY_INT_TYPE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_CMD_INT_TYPE_0_SPI_BUSY_INT_TYPE_EDGE _MK_ENUM_CONST(0) +#define DC_CMD_INT_TYPE_0_SPI_BUSY_INT_TYPE_LEVEL _MK_ENUM_CONST(1) + +#define DC_CMD_INT_TYPE_0_WIN_A_UF_INT_TYPE_SHIFT _MK_SHIFT_CONST(8) +#define DC_CMD_INT_TYPE_0_WIN_A_UF_INT_TYPE_FIELD _MK_FIELD_CONST(0x1, DC_CMD_INT_TYPE_0_WIN_A_UF_INT_TYPE_SHIFT) +#define DC_CMD_INT_TYPE_0_WIN_A_UF_INT_TYPE_RANGE 8:8 +#define DC_CMD_INT_TYPE_0_WIN_A_UF_INT_TYPE_WOFFSET 0x0 +#define DC_CMD_INT_TYPE_0_WIN_A_UF_INT_TYPE_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_INT_TYPE_0_WIN_A_UF_INT_TYPE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_CMD_INT_TYPE_0_WIN_A_UF_INT_TYPE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_INT_TYPE_0_WIN_A_UF_INT_TYPE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_CMD_INT_TYPE_0_WIN_A_UF_INT_TYPE_EDGE _MK_ENUM_CONST(0) +#define DC_CMD_INT_TYPE_0_WIN_A_UF_INT_TYPE_LEVEL _MK_ENUM_CONST(1) + +#define DC_CMD_INT_TYPE_0_WIN_B_UF_INT_TYPE_SHIFT _MK_SHIFT_CONST(9) +#define DC_CMD_INT_TYPE_0_WIN_B_UF_INT_TYPE_FIELD _MK_FIELD_CONST(0x1, DC_CMD_INT_TYPE_0_WIN_B_UF_INT_TYPE_SHIFT) +#define DC_CMD_INT_TYPE_0_WIN_B_UF_INT_TYPE_RANGE 9:9 +#define DC_CMD_INT_TYPE_0_WIN_B_UF_INT_TYPE_WOFFSET 0x0 +#define DC_CMD_INT_TYPE_0_WIN_B_UF_INT_TYPE_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_INT_TYPE_0_WIN_B_UF_INT_TYPE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_CMD_INT_TYPE_0_WIN_B_UF_INT_TYPE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_INT_TYPE_0_WIN_B_UF_INT_TYPE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_CMD_INT_TYPE_0_WIN_B_UF_INT_TYPE_EDGE _MK_ENUM_CONST(0) +#define DC_CMD_INT_TYPE_0_WIN_B_UF_INT_TYPE_LEVEL _MK_ENUM_CONST(1) + +#define DC_CMD_INT_TYPE_0_WIN_C_UF_INT_TYPE_SHIFT _MK_SHIFT_CONST(10) +#define DC_CMD_INT_TYPE_0_WIN_C_UF_INT_TYPE_FIELD _MK_FIELD_CONST(0x1, DC_CMD_INT_TYPE_0_WIN_C_UF_INT_TYPE_SHIFT) +#define DC_CMD_INT_TYPE_0_WIN_C_UF_INT_TYPE_RANGE 10:10 +#define DC_CMD_INT_TYPE_0_WIN_C_UF_INT_TYPE_WOFFSET 0x0 +#define DC_CMD_INT_TYPE_0_WIN_C_UF_INT_TYPE_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_INT_TYPE_0_WIN_C_UF_INT_TYPE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_CMD_INT_TYPE_0_WIN_C_UF_INT_TYPE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_INT_TYPE_0_WIN_C_UF_INT_TYPE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_CMD_INT_TYPE_0_WIN_C_UF_INT_TYPE_EDGE _MK_ENUM_CONST(0) +#define DC_CMD_INT_TYPE_0_WIN_C_UF_INT_TYPE_LEVEL _MK_ENUM_CONST(1) + +#define DC_CMD_INT_TYPE_0_MSF_INT_TYPE_SHIFT _MK_SHIFT_CONST(12) +#define DC_CMD_INT_TYPE_0_MSF_INT_TYPE_FIELD _MK_FIELD_CONST(0x1, DC_CMD_INT_TYPE_0_MSF_INT_TYPE_SHIFT) +#define DC_CMD_INT_TYPE_0_MSF_INT_TYPE_RANGE 12:12 +#define DC_CMD_INT_TYPE_0_MSF_INT_TYPE_WOFFSET 0x0 +#define DC_CMD_INT_TYPE_0_MSF_INT_TYPE_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_INT_TYPE_0_MSF_INT_TYPE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_CMD_INT_TYPE_0_MSF_INT_TYPE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_INT_TYPE_0_MSF_INT_TYPE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_CMD_INT_TYPE_0_MSF_INT_TYPE_EDGE _MK_ENUM_CONST(0) +#define DC_CMD_INT_TYPE_0_MSF_INT_TYPE_LEVEL _MK_ENUM_CONST(1) + +#define DC_CMD_INT_TYPE_0_SSF_INT_TYPE_SHIFT _MK_SHIFT_CONST(13) +#define DC_CMD_INT_TYPE_0_SSF_INT_TYPE_FIELD _MK_FIELD_CONST(0x1, DC_CMD_INT_TYPE_0_SSF_INT_TYPE_SHIFT) +#define DC_CMD_INT_TYPE_0_SSF_INT_TYPE_RANGE 13:13 +#define DC_CMD_INT_TYPE_0_SSF_INT_TYPE_WOFFSET 0x0 +#define DC_CMD_INT_TYPE_0_SSF_INT_TYPE_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_INT_TYPE_0_SSF_INT_TYPE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_CMD_INT_TYPE_0_SSF_INT_TYPE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_INT_TYPE_0_SSF_INT_TYPE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_CMD_INT_TYPE_0_SSF_INT_TYPE_EDGE _MK_ENUM_CONST(0) +#define DC_CMD_INT_TYPE_0_SSF_INT_TYPE_LEVEL _MK_ENUM_CONST(1) + +#define DC_CMD_INT_TYPE_0_WIN_A_OF_INT_TYPE_SHIFT _MK_SHIFT_CONST(14) +#define DC_CMD_INT_TYPE_0_WIN_A_OF_INT_TYPE_FIELD _MK_FIELD_CONST(0x1, DC_CMD_INT_TYPE_0_WIN_A_OF_INT_TYPE_SHIFT) +#define DC_CMD_INT_TYPE_0_WIN_A_OF_INT_TYPE_RANGE 14:14 +#define DC_CMD_INT_TYPE_0_WIN_A_OF_INT_TYPE_WOFFSET 0x0 +#define DC_CMD_INT_TYPE_0_WIN_A_OF_INT_TYPE_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_INT_TYPE_0_WIN_A_OF_INT_TYPE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_CMD_INT_TYPE_0_WIN_A_OF_INT_TYPE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_INT_TYPE_0_WIN_A_OF_INT_TYPE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_CMD_INT_TYPE_0_WIN_A_OF_INT_TYPE_EDGE _MK_ENUM_CONST(0) +#define DC_CMD_INT_TYPE_0_WIN_A_OF_INT_TYPE_LEVEL _MK_ENUM_CONST(1) + +#define DC_CMD_INT_TYPE_0_WIN_B_OF_INT_TYPE_SHIFT _MK_SHIFT_CONST(15) +#define DC_CMD_INT_TYPE_0_WIN_B_OF_INT_TYPE_FIELD _MK_FIELD_CONST(0x1, DC_CMD_INT_TYPE_0_WIN_B_OF_INT_TYPE_SHIFT) +#define DC_CMD_INT_TYPE_0_WIN_B_OF_INT_TYPE_RANGE 15:15 +#define DC_CMD_INT_TYPE_0_WIN_B_OF_INT_TYPE_WOFFSET 0x0 +#define DC_CMD_INT_TYPE_0_WIN_B_OF_INT_TYPE_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_INT_TYPE_0_WIN_B_OF_INT_TYPE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_CMD_INT_TYPE_0_WIN_B_OF_INT_TYPE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_INT_TYPE_0_WIN_B_OF_INT_TYPE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_CMD_INT_TYPE_0_WIN_B_OF_INT_TYPE_EDGE _MK_ENUM_CONST(0) +#define DC_CMD_INT_TYPE_0_WIN_B_OF_INT_TYPE_LEVEL _MK_ENUM_CONST(1) + +#define DC_CMD_INT_TYPE_0_WIN_C_OF_INT_TYPE_SHIFT _MK_SHIFT_CONST(16) +#define DC_CMD_INT_TYPE_0_WIN_C_OF_INT_TYPE_FIELD _MK_FIELD_CONST(0x1, DC_CMD_INT_TYPE_0_WIN_C_OF_INT_TYPE_SHIFT) +#define DC_CMD_INT_TYPE_0_WIN_C_OF_INT_TYPE_RANGE 16:16 +#define DC_CMD_INT_TYPE_0_WIN_C_OF_INT_TYPE_WOFFSET 0x0 +#define DC_CMD_INT_TYPE_0_WIN_C_OF_INT_TYPE_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_INT_TYPE_0_WIN_C_OF_INT_TYPE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_CMD_INT_TYPE_0_WIN_C_OF_INT_TYPE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_INT_TYPE_0_WIN_C_OF_INT_TYPE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_CMD_INT_TYPE_0_WIN_C_OF_INT_TYPE_EDGE _MK_ENUM_CONST(0) +#define DC_CMD_INT_TYPE_0_WIN_C_OF_INT_TYPE_LEVEL _MK_ENUM_CONST(1) + +#define DC_CMD_INT_TYPE_0_CMU_LUT_CONFLICT_INT_TYPE_SHIFT _MK_SHIFT_CONST(22) +#define DC_CMD_INT_TYPE_0_CMU_LUT_CONFLICT_INT_TYPE_FIELD _MK_FIELD_CONST(0x1, DC_CMD_INT_TYPE_0_CMU_LUT_CONFLICT_INT_TYPE_SHIFT) +#define DC_CMD_INT_TYPE_0_CMU_LUT_CONFLICT_INT_TYPE_RANGE 22:22 +#define DC_CMD_INT_TYPE_0_CMU_LUT_CONFLICT_INT_TYPE_WOFFSET 0x0 +#define DC_CMD_INT_TYPE_0_CMU_LUT_CONFLICT_INT_TYPE_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_INT_TYPE_0_CMU_LUT_CONFLICT_INT_TYPE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_CMD_INT_TYPE_0_CMU_LUT_CONFLICT_INT_TYPE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_INT_TYPE_0_CMU_LUT_CONFLICT_INT_TYPE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_CMD_INT_TYPE_0_CMU_LUT_CONFLICT_INT_TYPE_INIT_ENUM EDGE +#define DC_CMD_INT_TYPE_0_CMU_LUT_CONFLICT_INT_TYPE_EDGE _MK_ENUM_CONST(0) +#define DC_CMD_INT_TYPE_0_CMU_LUT_CONFLICT_INT_TYPE_LEVEL _MK_ENUM_CONST(1) + +#define DC_CMD_INT_TYPE_0_HC_UF_INT_TYPE_SHIFT _MK_SHIFT_CONST(23) +#define DC_CMD_INT_TYPE_0_HC_UF_INT_TYPE_FIELD _MK_FIELD_CONST(0x1, DC_CMD_INT_TYPE_0_HC_UF_INT_TYPE_SHIFT) +#define DC_CMD_INT_TYPE_0_HC_UF_INT_TYPE_RANGE 23:23 +#define DC_CMD_INT_TYPE_0_HC_UF_INT_TYPE_WOFFSET 0x0 +#define DC_CMD_INT_TYPE_0_HC_UF_INT_TYPE_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_INT_TYPE_0_HC_UF_INT_TYPE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_CMD_INT_TYPE_0_HC_UF_INT_TYPE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_INT_TYPE_0_HC_UF_INT_TYPE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_CMD_INT_TYPE_0_HC_UF_INT_TYPE_EDGE _MK_ENUM_CONST(0) +#define DC_CMD_INT_TYPE_0_HC_UF_INT_TYPE_LEVEL _MK_ENUM_CONST(1) + +#define DC_CMD_INT_TYPE_0_WIN_D_UF_INT_TYPE_SHIFT _MK_SHIFT_CONST(24) +#define DC_CMD_INT_TYPE_0_WIN_D_UF_INT_TYPE_FIELD _MK_FIELD_CONST(0x1, DC_CMD_INT_TYPE_0_WIN_D_UF_INT_TYPE_SHIFT) +#define DC_CMD_INT_TYPE_0_WIN_D_UF_INT_TYPE_RANGE 24:24 +#define DC_CMD_INT_TYPE_0_WIN_D_UF_INT_TYPE_WOFFSET 0x0 +#define DC_CMD_INT_TYPE_0_WIN_D_UF_INT_TYPE_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_INT_TYPE_0_WIN_D_UF_INT_TYPE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_CMD_INT_TYPE_0_WIN_D_UF_INT_TYPE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_INT_TYPE_0_WIN_D_UF_INT_TYPE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_CMD_INT_TYPE_0_WIN_D_UF_INT_TYPE_EDGE _MK_ENUM_CONST(0) +#define DC_CMD_INT_TYPE_0_WIN_D_UF_INT_TYPE_LEVEL _MK_ENUM_CONST(1) + +#define DC_CMD_INT_TYPE_0_WIN_T_UF_INT_TYPE_SHIFT _MK_SHIFT_CONST(25) +#define DC_CMD_INT_TYPE_0_WIN_T_UF_INT_TYPE_FIELD _MK_FIELD_CONST(0x1, DC_CMD_INT_TYPE_0_WIN_T_UF_INT_TYPE_SHIFT) +#define DC_CMD_INT_TYPE_0_WIN_T_UF_INT_TYPE_RANGE 25:25 +#define DC_CMD_INT_TYPE_0_WIN_T_UF_INT_TYPE_WOFFSET 0x0 +#define DC_CMD_INT_TYPE_0_WIN_T_UF_INT_TYPE_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_INT_TYPE_0_WIN_T_UF_INT_TYPE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_CMD_INT_TYPE_0_WIN_T_UF_INT_TYPE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_INT_TYPE_0_WIN_T_UF_INT_TYPE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_CMD_INT_TYPE_0_WIN_T_UF_INT_TYPE_EDGE _MK_ENUM_CONST(0) +#define DC_CMD_INT_TYPE_0_WIN_T_UF_INT_TYPE_LEVEL _MK_ENUM_CONST(1) + + +// Register DC_CMD_INT_POLARITY_0 +#define DC_CMD_INT_POLARITY_0 _MK_ADDR_CONST(0x3b) +#define DC_CMD_INT_POLARITY_0_SECURE 0x0 +#define DC_CMD_INT_POLARITY_0_WORD_COUNT 0x1 +#define DC_CMD_INT_POLARITY_0_RESET_VAL _MK_MASK_CONST(0x400000) +#define DC_CMD_INT_POLARITY_0_RESET_MASK _MK_MASK_CONST(0x3c1f7be) +#define DC_CMD_INT_POLARITY_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_CMD_INT_POLARITY_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_CMD_INT_POLARITY_0_READ_MASK _MK_MASK_CONST(0x3c1f7be) +#define DC_CMD_INT_POLARITY_0_WRITE_MASK _MK_MASK_CONST(0x3c1f7be) +#define DC_CMD_INT_POLARITY_0_FRAME_END_INT_POLARITY_SHIFT _MK_SHIFT_CONST(1) +#define DC_CMD_INT_POLARITY_0_FRAME_END_INT_POLARITY_FIELD _MK_FIELD_CONST(0x1, DC_CMD_INT_POLARITY_0_FRAME_END_INT_POLARITY_SHIFT) +#define DC_CMD_INT_POLARITY_0_FRAME_END_INT_POLARITY_RANGE 1:1 +#define DC_CMD_INT_POLARITY_0_FRAME_END_INT_POLARITY_WOFFSET 0x0 +#define DC_CMD_INT_POLARITY_0_FRAME_END_INT_POLARITY_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_INT_POLARITY_0_FRAME_END_INT_POLARITY_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_CMD_INT_POLARITY_0_FRAME_END_INT_POLARITY_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_INT_POLARITY_0_FRAME_END_INT_POLARITY_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_CMD_INT_POLARITY_0_FRAME_END_INT_POLARITY_LOW _MK_ENUM_CONST(0) +#define DC_CMD_INT_POLARITY_0_FRAME_END_INT_POLARITY_HIGH _MK_ENUM_CONST(1) + +#define DC_CMD_INT_POLARITY_0_V_BLANK_INT_POLARITY_SHIFT _MK_SHIFT_CONST(2) +#define DC_CMD_INT_POLARITY_0_V_BLANK_INT_POLARITY_FIELD _MK_FIELD_CONST(0x1, DC_CMD_INT_POLARITY_0_V_BLANK_INT_POLARITY_SHIFT) +#define DC_CMD_INT_POLARITY_0_V_BLANK_INT_POLARITY_RANGE 2:2 +#define DC_CMD_INT_POLARITY_0_V_BLANK_INT_POLARITY_WOFFSET 0x0 +#define DC_CMD_INT_POLARITY_0_V_BLANK_INT_POLARITY_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_INT_POLARITY_0_V_BLANK_INT_POLARITY_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_CMD_INT_POLARITY_0_V_BLANK_INT_POLARITY_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_INT_POLARITY_0_V_BLANK_INT_POLARITY_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_CMD_INT_POLARITY_0_V_BLANK_INT_POLARITY_LOW _MK_ENUM_CONST(0) +#define DC_CMD_INT_POLARITY_0_V_BLANK_INT_POLARITY_HIGH _MK_ENUM_CONST(1) + +#define DC_CMD_INT_POLARITY_0_H_BLANK_INT_POLARITY_SHIFT _MK_SHIFT_CONST(3) +#define DC_CMD_INT_POLARITY_0_H_BLANK_INT_POLARITY_FIELD _MK_FIELD_CONST(0x1, DC_CMD_INT_POLARITY_0_H_BLANK_INT_POLARITY_SHIFT) +#define DC_CMD_INT_POLARITY_0_H_BLANK_INT_POLARITY_RANGE 3:3 +#define DC_CMD_INT_POLARITY_0_H_BLANK_INT_POLARITY_WOFFSET 0x0 +#define DC_CMD_INT_POLARITY_0_H_BLANK_INT_POLARITY_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_INT_POLARITY_0_H_BLANK_INT_POLARITY_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_CMD_INT_POLARITY_0_H_BLANK_INT_POLARITY_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_INT_POLARITY_0_H_BLANK_INT_POLARITY_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_CMD_INT_POLARITY_0_H_BLANK_INT_POLARITY_LOW _MK_ENUM_CONST(0) +#define DC_CMD_INT_POLARITY_0_H_BLANK_INT_POLARITY_HIGH _MK_ENUM_CONST(1) + +#define DC_CMD_INT_POLARITY_0_V_PULSE3_INT_POLARITY_SHIFT _MK_SHIFT_CONST(4) +#define DC_CMD_INT_POLARITY_0_V_PULSE3_INT_POLARITY_FIELD _MK_FIELD_CONST(0x1, DC_CMD_INT_POLARITY_0_V_PULSE3_INT_POLARITY_SHIFT) +#define DC_CMD_INT_POLARITY_0_V_PULSE3_INT_POLARITY_RANGE 4:4 +#define DC_CMD_INT_POLARITY_0_V_PULSE3_INT_POLARITY_WOFFSET 0x0 +#define DC_CMD_INT_POLARITY_0_V_PULSE3_INT_POLARITY_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_INT_POLARITY_0_V_PULSE3_INT_POLARITY_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_CMD_INT_POLARITY_0_V_PULSE3_INT_POLARITY_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_INT_POLARITY_0_V_PULSE3_INT_POLARITY_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_CMD_INT_POLARITY_0_V_PULSE3_INT_POLARITY_LOW _MK_ENUM_CONST(0) +#define DC_CMD_INT_POLARITY_0_V_PULSE3_INT_POLARITY_HIGH _MK_ENUM_CONST(1) + +#define DC_CMD_INT_POLARITY_0_V_PULSE2_INT_POLARITY_SHIFT _MK_SHIFT_CONST(5) +#define DC_CMD_INT_POLARITY_0_V_PULSE2_INT_POLARITY_FIELD _MK_FIELD_CONST(0x1, DC_CMD_INT_POLARITY_0_V_PULSE2_INT_POLARITY_SHIFT) +#define DC_CMD_INT_POLARITY_0_V_PULSE2_INT_POLARITY_RANGE 5:5 +#define DC_CMD_INT_POLARITY_0_V_PULSE2_INT_POLARITY_WOFFSET 0x0 +#define DC_CMD_INT_POLARITY_0_V_PULSE2_INT_POLARITY_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_INT_POLARITY_0_V_PULSE2_INT_POLARITY_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_CMD_INT_POLARITY_0_V_PULSE2_INT_POLARITY_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_INT_POLARITY_0_V_PULSE2_INT_POLARITY_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_CMD_INT_POLARITY_0_V_PULSE2_INT_POLARITY_LOW _MK_ENUM_CONST(0) +#define DC_CMD_INT_POLARITY_0_V_PULSE2_INT_POLARITY_HIGH _MK_ENUM_CONST(1) + +#define DC_CMD_INT_POLARITY_0_SPI_BUSY_INT_POLARITY_SHIFT _MK_SHIFT_CONST(7) +#define DC_CMD_INT_POLARITY_0_SPI_BUSY_INT_POLARITY_FIELD _MK_FIELD_CONST(0x1, DC_CMD_INT_POLARITY_0_SPI_BUSY_INT_POLARITY_SHIFT) +#define DC_CMD_INT_POLARITY_0_SPI_BUSY_INT_POLARITY_RANGE 7:7 +#define DC_CMD_INT_POLARITY_0_SPI_BUSY_INT_POLARITY_WOFFSET 0x0 +#define DC_CMD_INT_POLARITY_0_SPI_BUSY_INT_POLARITY_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_INT_POLARITY_0_SPI_BUSY_INT_POLARITY_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_CMD_INT_POLARITY_0_SPI_BUSY_INT_POLARITY_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_INT_POLARITY_0_SPI_BUSY_INT_POLARITY_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_CMD_INT_POLARITY_0_SPI_BUSY_INT_POLARITY_LOW _MK_ENUM_CONST(0) +#define DC_CMD_INT_POLARITY_0_SPI_BUSY_INT_POLARITY_HIGH _MK_ENUM_CONST(1) + +#define DC_CMD_INT_POLARITY_0_WIN_A_UF_INT_POLARITY_SHIFT _MK_SHIFT_CONST(8) +#define DC_CMD_INT_POLARITY_0_WIN_A_UF_INT_POLARITY_FIELD _MK_FIELD_CONST(0x1, DC_CMD_INT_POLARITY_0_WIN_A_UF_INT_POLARITY_SHIFT) +#define DC_CMD_INT_POLARITY_0_WIN_A_UF_INT_POLARITY_RANGE 8:8 +#define DC_CMD_INT_POLARITY_0_WIN_A_UF_INT_POLARITY_WOFFSET 0x0 +#define DC_CMD_INT_POLARITY_0_WIN_A_UF_INT_POLARITY_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_INT_POLARITY_0_WIN_A_UF_INT_POLARITY_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_CMD_INT_POLARITY_0_WIN_A_UF_INT_POLARITY_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_INT_POLARITY_0_WIN_A_UF_INT_POLARITY_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_CMD_INT_POLARITY_0_WIN_A_UF_INT_POLARITY_LOW _MK_ENUM_CONST(0) +#define DC_CMD_INT_POLARITY_0_WIN_A_UF_INT_POLARITY_HIGH _MK_ENUM_CONST(1) + +#define DC_CMD_INT_POLARITY_0_WIN_B_UF_INT_POLARITY_SHIFT _MK_SHIFT_CONST(9) +#define DC_CMD_INT_POLARITY_0_WIN_B_UF_INT_POLARITY_FIELD _MK_FIELD_CONST(0x1, DC_CMD_INT_POLARITY_0_WIN_B_UF_INT_POLARITY_SHIFT) +#define DC_CMD_INT_POLARITY_0_WIN_B_UF_INT_POLARITY_RANGE 9:9 +#define DC_CMD_INT_POLARITY_0_WIN_B_UF_INT_POLARITY_WOFFSET 0x0 +#define DC_CMD_INT_POLARITY_0_WIN_B_UF_INT_POLARITY_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_INT_POLARITY_0_WIN_B_UF_INT_POLARITY_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_CMD_INT_POLARITY_0_WIN_B_UF_INT_POLARITY_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_INT_POLARITY_0_WIN_B_UF_INT_POLARITY_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_CMD_INT_POLARITY_0_WIN_B_UF_INT_POLARITY_LOW _MK_ENUM_CONST(0) +#define DC_CMD_INT_POLARITY_0_WIN_B_UF_INT_POLARITY_HIGH _MK_ENUM_CONST(1) + +#define DC_CMD_INT_POLARITY_0_WIN_C_UF_INT_POLARITY_SHIFT _MK_SHIFT_CONST(10) +#define DC_CMD_INT_POLARITY_0_WIN_C_UF_INT_POLARITY_FIELD _MK_FIELD_CONST(0x1, DC_CMD_INT_POLARITY_0_WIN_C_UF_INT_POLARITY_SHIFT) +#define DC_CMD_INT_POLARITY_0_WIN_C_UF_INT_POLARITY_RANGE 10:10 +#define DC_CMD_INT_POLARITY_0_WIN_C_UF_INT_POLARITY_WOFFSET 0x0 +#define DC_CMD_INT_POLARITY_0_WIN_C_UF_INT_POLARITY_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_INT_POLARITY_0_WIN_C_UF_INT_POLARITY_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_CMD_INT_POLARITY_0_WIN_C_UF_INT_POLARITY_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_INT_POLARITY_0_WIN_C_UF_INT_POLARITY_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_CMD_INT_POLARITY_0_WIN_C_UF_INT_POLARITY_LOW _MK_ENUM_CONST(0) +#define DC_CMD_INT_POLARITY_0_WIN_C_UF_INT_POLARITY_HIGH _MK_ENUM_CONST(1) + +#define DC_CMD_INT_POLARITY_0_MSF_INT_POLARITY_SHIFT _MK_SHIFT_CONST(12) +#define DC_CMD_INT_POLARITY_0_MSF_INT_POLARITY_FIELD _MK_FIELD_CONST(0x1, DC_CMD_INT_POLARITY_0_MSF_INT_POLARITY_SHIFT) +#define DC_CMD_INT_POLARITY_0_MSF_INT_POLARITY_RANGE 12:12 +#define DC_CMD_INT_POLARITY_0_MSF_INT_POLARITY_WOFFSET 0x0 +#define DC_CMD_INT_POLARITY_0_MSF_INT_POLARITY_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_INT_POLARITY_0_MSF_INT_POLARITY_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_CMD_INT_POLARITY_0_MSF_INT_POLARITY_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_INT_POLARITY_0_MSF_INT_POLARITY_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_CMD_INT_POLARITY_0_MSF_INT_POLARITY_LOW _MK_ENUM_CONST(0) +#define DC_CMD_INT_POLARITY_0_MSF_INT_POLARITY_HIGH _MK_ENUM_CONST(1) + +#define DC_CMD_INT_POLARITY_0_SSF_INT_POLARITY_SHIFT _MK_SHIFT_CONST(13) +#define DC_CMD_INT_POLARITY_0_SSF_INT_POLARITY_FIELD _MK_FIELD_CONST(0x1, DC_CMD_INT_POLARITY_0_SSF_INT_POLARITY_SHIFT) +#define DC_CMD_INT_POLARITY_0_SSF_INT_POLARITY_RANGE 13:13 +#define DC_CMD_INT_POLARITY_0_SSF_INT_POLARITY_WOFFSET 0x0 +#define DC_CMD_INT_POLARITY_0_SSF_INT_POLARITY_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_INT_POLARITY_0_SSF_INT_POLARITY_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_CMD_INT_POLARITY_0_SSF_INT_POLARITY_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_INT_POLARITY_0_SSF_INT_POLARITY_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_CMD_INT_POLARITY_0_SSF_INT_POLARITY_LOW _MK_ENUM_CONST(0) +#define DC_CMD_INT_POLARITY_0_SSF_INT_POLARITY_HIGH _MK_ENUM_CONST(1) + +#define DC_CMD_INT_POLARITY_0_WIN_A_OF_INT_POLARITY_SHIFT _MK_SHIFT_CONST(14) +#define DC_CMD_INT_POLARITY_0_WIN_A_OF_INT_POLARITY_FIELD _MK_FIELD_CONST(0x1, DC_CMD_INT_POLARITY_0_WIN_A_OF_INT_POLARITY_SHIFT) +#define DC_CMD_INT_POLARITY_0_WIN_A_OF_INT_POLARITY_RANGE 14:14 +#define DC_CMD_INT_POLARITY_0_WIN_A_OF_INT_POLARITY_WOFFSET 0x0 +#define DC_CMD_INT_POLARITY_0_WIN_A_OF_INT_POLARITY_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_INT_POLARITY_0_WIN_A_OF_INT_POLARITY_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_CMD_INT_POLARITY_0_WIN_A_OF_INT_POLARITY_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_INT_POLARITY_0_WIN_A_OF_INT_POLARITY_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_CMD_INT_POLARITY_0_WIN_A_OF_INT_POLARITY_LOW _MK_ENUM_CONST(0) +#define DC_CMD_INT_POLARITY_0_WIN_A_OF_INT_POLARITY_HIGH _MK_ENUM_CONST(1) + +#define DC_CMD_INT_POLARITY_0_WIN_B_OF_INT_POLARITY_SHIFT _MK_SHIFT_CONST(15) +#define DC_CMD_INT_POLARITY_0_WIN_B_OF_INT_POLARITY_FIELD _MK_FIELD_CONST(0x1, DC_CMD_INT_POLARITY_0_WIN_B_OF_INT_POLARITY_SHIFT) +#define DC_CMD_INT_POLARITY_0_WIN_B_OF_INT_POLARITY_RANGE 15:15 +#define DC_CMD_INT_POLARITY_0_WIN_B_OF_INT_POLARITY_WOFFSET 0x0 +#define DC_CMD_INT_POLARITY_0_WIN_B_OF_INT_POLARITY_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_INT_POLARITY_0_WIN_B_OF_INT_POLARITY_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_CMD_INT_POLARITY_0_WIN_B_OF_INT_POLARITY_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_INT_POLARITY_0_WIN_B_OF_INT_POLARITY_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_CMD_INT_POLARITY_0_WIN_B_OF_INT_POLARITY_LOW _MK_ENUM_CONST(0) +#define DC_CMD_INT_POLARITY_0_WIN_B_OF_INT_POLARITY_HIGH _MK_ENUM_CONST(1) + +#define DC_CMD_INT_POLARITY_0_WIN_C_OF_INT_POLARITY_SHIFT _MK_SHIFT_CONST(16) +#define DC_CMD_INT_POLARITY_0_WIN_C_OF_INT_POLARITY_FIELD _MK_FIELD_CONST(0x1, DC_CMD_INT_POLARITY_0_WIN_C_OF_INT_POLARITY_SHIFT) +#define DC_CMD_INT_POLARITY_0_WIN_C_OF_INT_POLARITY_RANGE 16:16 +#define DC_CMD_INT_POLARITY_0_WIN_C_OF_INT_POLARITY_WOFFSET 0x0 +#define DC_CMD_INT_POLARITY_0_WIN_C_OF_INT_POLARITY_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_INT_POLARITY_0_WIN_C_OF_INT_POLARITY_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_CMD_INT_POLARITY_0_WIN_C_OF_INT_POLARITY_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_INT_POLARITY_0_WIN_C_OF_INT_POLARITY_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_CMD_INT_POLARITY_0_WIN_C_OF_INT_POLARITY_LOW _MK_ENUM_CONST(0) +#define DC_CMD_INT_POLARITY_0_WIN_C_OF_INT_POLARITY_HIGH _MK_ENUM_CONST(1) + +#define DC_CMD_INT_POLARITY_0_CMU_LUT_CONFLICT_INT_POLARITY_SHIFT _MK_SHIFT_CONST(22) +#define DC_CMD_INT_POLARITY_0_CMU_LUT_CONFLICT_INT_POLARITY_FIELD _MK_FIELD_CONST(0x1, DC_CMD_INT_POLARITY_0_CMU_LUT_CONFLICT_INT_POLARITY_SHIFT) +#define DC_CMD_INT_POLARITY_0_CMU_LUT_CONFLICT_INT_POLARITY_RANGE 22:22 +#define DC_CMD_INT_POLARITY_0_CMU_LUT_CONFLICT_INT_POLARITY_WOFFSET 0x0 +#define DC_CMD_INT_POLARITY_0_CMU_LUT_CONFLICT_INT_POLARITY_DEFAULT _MK_MASK_CONST(0x1) +#define DC_CMD_INT_POLARITY_0_CMU_LUT_CONFLICT_INT_POLARITY_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_CMD_INT_POLARITY_0_CMU_LUT_CONFLICT_INT_POLARITY_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_INT_POLARITY_0_CMU_LUT_CONFLICT_INT_POLARITY_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_CMD_INT_POLARITY_0_CMU_LUT_CONFLICT_INT_POLARITY_INIT_ENUM HIGH +#define DC_CMD_INT_POLARITY_0_CMU_LUT_CONFLICT_INT_POLARITY_LOW _MK_ENUM_CONST(0) +#define DC_CMD_INT_POLARITY_0_CMU_LUT_CONFLICT_INT_POLARITY_HIGH _MK_ENUM_CONST(1) + +#define DC_CMD_INT_POLARITY_0_HC_UF_INT_POLARITY_SHIFT _MK_SHIFT_CONST(23) +#define DC_CMD_INT_POLARITY_0_HC_UF_INT_POLARITY_FIELD _MK_FIELD_CONST(0x1, DC_CMD_INT_POLARITY_0_HC_UF_INT_POLARITY_SHIFT) +#define DC_CMD_INT_POLARITY_0_HC_UF_INT_POLARITY_RANGE 23:23 +#define DC_CMD_INT_POLARITY_0_HC_UF_INT_POLARITY_WOFFSET 0x0 +#define DC_CMD_INT_POLARITY_0_HC_UF_INT_POLARITY_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_INT_POLARITY_0_HC_UF_INT_POLARITY_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_CMD_INT_POLARITY_0_HC_UF_INT_POLARITY_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_INT_POLARITY_0_HC_UF_INT_POLARITY_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_CMD_INT_POLARITY_0_HC_UF_INT_POLARITY_LOW _MK_ENUM_CONST(0) +#define DC_CMD_INT_POLARITY_0_HC_UF_INT_POLARITY_HIGH _MK_ENUM_CONST(1) + +#define DC_CMD_INT_POLARITY_0_WIN_D_UF_INT_POLARITY_SHIFT _MK_SHIFT_CONST(24) +#define DC_CMD_INT_POLARITY_0_WIN_D_UF_INT_POLARITY_FIELD _MK_FIELD_CONST(0x1, DC_CMD_INT_POLARITY_0_WIN_D_UF_INT_POLARITY_SHIFT) +#define DC_CMD_INT_POLARITY_0_WIN_D_UF_INT_POLARITY_RANGE 24:24 +#define DC_CMD_INT_POLARITY_0_WIN_D_UF_INT_POLARITY_WOFFSET 0x0 +#define DC_CMD_INT_POLARITY_0_WIN_D_UF_INT_POLARITY_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_INT_POLARITY_0_WIN_D_UF_INT_POLARITY_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_CMD_INT_POLARITY_0_WIN_D_UF_INT_POLARITY_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_INT_POLARITY_0_WIN_D_UF_INT_POLARITY_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_CMD_INT_POLARITY_0_WIN_D_UF_INT_POLARITY_LOW _MK_ENUM_CONST(0) +#define DC_CMD_INT_POLARITY_0_WIN_D_UF_INT_POLARITY_HIGH _MK_ENUM_CONST(1) + +#define DC_CMD_INT_POLARITY_0_WIN_T_UF_INT_POLARITY_SHIFT _MK_SHIFT_CONST(25) +#define DC_CMD_INT_POLARITY_0_WIN_T_UF_INT_POLARITY_FIELD _MK_FIELD_CONST(0x1, DC_CMD_INT_POLARITY_0_WIN_T_UF_INT_POLARITY_SHIFT) +#define DC_CMD_INT_POLARITY_0_WIN_T_UF_INT_POLARITY_RANGE 25:25 +#define DC_CMD_INT_POLARITY_0_WIN_T_UF_INT_POLARITY_WOFFSET 0x0 +#define DC_CMD_INT_POLARITY_0_WIN_T_UF_INT_POLARITY_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_INT_POLARITY_0_WIN_T_UF_INT_POLARITY_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_CMD_INT_POLARITY_0_WIN_T_UF_INT_POLARITY_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_INT_POLARITY_0_WIN_T_UF_INT_POLARITY_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_CMD_INT_POLARITY_0_WIN_T_UF_INT_POLARITY_LOW _MK_ENUM_CONST(0) +#define DC_CMD_INT_POLARITY_0_WIN_T_UF_INT_POLARITY_HIGH _MK_ENUM_CONST(1) + + +// Register DC_CMD_SIGNAL_RAISE1_0 +#define DC_CMD_SIGNAL_RAISE1_0 _MK_ADDR_CONST(0x3c) +#define DC_CMD_SIGNAL_RAISE1_0_SECURE 0x0 +#define DC_CMD_SIGNAL_RAISE1_0_WORD_COUNT 0x1 +#define DC_CMD_SIGNAL_RAISE1_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_CMD_SIGNAL_RAISE1_0_RESET_MASK _MK_MASK_CONST(0x1000) +#define DC_CMD_SIGNAL_RAISE1_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_CMD_SIGNAL_RAISE1_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_CMD_SIGNAL_RAISE1_0_READ_MASK _MK_MASK_CONST(0xf171f) +#define DC_CMD_SIGNAL_RAISE1_0_WRITE_MASK _MK_MASK_CONST(0xf171f) +#define DC_CMD_SIGNAL_RAISE1_0_SIGNAL_RAISE1_VECTOR_SHIFT _MK_SHIFT_CONST(0) +#define DC_CMD_SIGNAL_RAISE1_0_SIGNAL_RAISE1_VECTOR_FIELD _MK_FIELD_CONST(0x1f, DC_CMD_SIGNAL_RAISE1_0_SIGNAL_RAISE1_VECTOR_SHIFT) +#define DC_CMD_SIGNAL_RAISE1_0_SIGNAL_RAISE1_VECTOR_RANGE 4:0 +#define DC_CMD_SIGNAL_RAISE1_0_SIGNAL_RAISE1_VECTOR_WOFFSET 0x0 +#define DC_CMD_SIGNAL_RAISE1_0_SIGNAL_RAISE1_VECTOR_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_SIGNAL_RAISE1_0_SIGNAL_RAISE1_VECTOR_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_CMD_SIGNAL_RAISE1_0_SIGNAL_RAISE1_VECTOR_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_SIGNAL_RAISE1_0_SIGNAL_RAISE1_VECTOR_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_CMD_SIGNAL_RAISE1_0_SIGNAL_RAISE1_SELECT_SHIFT _MK_SHIFT_CONST(8) +#define DC_CMD_SIGNAL_RAISE1_0_SIGNAL_RAISE1_SELECT_FIELD _MK_FIELD_CONST(0x7, DC_CMD_SIGNAL_RAISE1_0_SIGNAL_RAISE1_SELECT_SHIFT) +#define DC_CMD_SIGNAL_RAISE1_0_SIGNAL_RAISE1_SELECT_RANGE 10:8 +#define DC_CMD_SIGNAL_RAISE1_0_SIGNAL_RAISE1_SELECT_WOFFSET 0x0 +#define DC_CMD_SIGNAL_RAISE1_0_SIGNAL_RAISE1_SELECT_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_SIGNAL_RAISE1_0_SIGNAL_RAISE1_SELECT_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_CMD_SIGNAL_RAISE1_0_SIGNAL_RAISE1_SELECT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_SIGNAL_RAISE1_0_SIGNAL_RAISE1_SELECT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_CMD_SIGNAL_RAISE1_0_SIGNAL_RAISE1_SELECT_NONE _MK_ENUM_CONST(0) +#define DC_CMD_SIGNAL_RAISE1_0_SIGNAL_RAISE1_SELECT_FRAME_END _MK_ENUM_CONST(1) +#define DC_CMD_SIGNAL_RAISE1_0_SIGNAL_RAISE1_SELECT_VBLANK _MK_ENUM_CONST(2) +#define DC_CMD_SIGNAL_RAISE1_0_SIGNAL_RAISE1_SELECT_VPULSE3 _MK_ENUM_CONST(3) +#define DC_CMD_SIGNAL_RAISE1_0_SIGNAL_RAISE1_SELECT_VBLANK_START _MK_ENUM_CONST(4) +#define DC_CMD_SIGNAL_RAISE1_0_SIGNAL_RAISE1_SELECT_VBLANK_END _MK_ENUM_CONST(5) +#define DC_CMD_SIGNAL_RAISE1_0_SIGNAL_RAISE1_SELECT_VPULSE3_START _MK_ENUM_CONST(6) +#define DC_CMD_SIGNAL_RAISE1_0_SIGNAL_RAISE1_SELECT_VPULSE3_END _MK_ENUM_CONST(7) + +#define DC_CMD_SIGNAL_RAISE1_0_SIGNAL_RAISE1_TYPE_SHIFT _MK_SHIFT_CONST(12) +#define DC_CMD_SIGNAL_RAISE1_0_SIGNAL_RAISE1_TYPE_FIELD _MK_FIELD_CONST(0x1, DC_CMD_SIGNAL_RAISE1_0_SIGNAL_RAISE1_TYPE_SHIFT) +#define DC_CMD_SIGNAL_RAISE1_0_SIGNAL_RAISE1_TYPE_RANGE 12:12 +#define DC_CMD_SIGNAL_RAISE1_0_SIGNAL_RAISE1_TYPE_WOFFSET 0x0 +#define DC_CMD_SIGNAL_RAISE1_0_SIGNAL_RAISE1_TYPE_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_SIGNAL_RAISE1_0_SIGNAL_RAISE1_TYPE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_CMD_SIGNAL_RAISE1_0_SIGNAL_RAISE1_TYPE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_SIGNAL_RAISE1_0_SIGNAL_RAISE1_TYPE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_CMD_SIGNAL_RAISE1_0_SIGNAL_RAISE1_TYPE_ONESHOT _MK_ENUM_CONST(0) +#define DC_CMD_SIGNAL_RAISE1_0_SIGNAL_RAISE1_TYPE_CONT _MK_ENUM_CONST(1) + +#define DC_CMD_SIGNAL_RAISE1_0_SIGNAL_RAISE1_CHANNEL_ID_SHIFT _MK_SHIFT_CONST(16) +#define DC_CMD_SIGNAL_RAISE1_0_SIGNAL_RAISE1_CHANNEL_ID_FIELD _MK_FIELD_CONST(0xf, DC_CMD_SIGNAL_RAISE1_0_SIGNAL_RAISE1_CHANNEL_ID_SHIFT) +#define DC_CMD_SIGNAL_RAISE1_0_SIGNAL_RAISE1_CHANNEL_ID_RANGE 19:16 +#define DC_CMD_SIGNAL_RAISE1_0_SIGNAL_RAISE1_CHANNEL_ID_WOFFSET 0x0 +#define DC_CMD_SIGNAL_RAISE1_0_SIGNAL_RAISE1_CHANNEL_ID_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_SIGNAL_RAISE1_0_SIGNAL_RAISE1_CHANNEL_ID_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_CMD_SIGNAL_RAISE1_0_SIGNAL_RAISE1_CHANNEL_ID_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_SIGNAL_RAISE1_0_SIGNAL_RAISE1_CHANNEL_ID_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_CMD_SIGNAL_RAISE2_0 +#define DC_CMD_SIGNAL_RAISE2_0 _MK_ADDR_CONST(0x3d) +#define DC_CMD_SIGNAL_RAISE2_0_SECURE 0x0 +#define DC_CMD_SIGNAL_RAISE2_0_WORD_COUNT 0x1 +#define DC_CMD_SIGNAL_RAISE2_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_CMD_SIGNAL_RAISE2_0_RESET_MASK _MK_MASK_CONST(0x1000) +#define DC_CMD_SIGNAL_RAISE2_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_CMD_SIGNAL_RAISE2_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_CMD_SIGNAL_RAISE2_0_READ_MASK _MK_MASK_CONST(0xf171f) +#define DC_CMD_SIGNAL_RAISE2_0_WRITE_MASK _MK_MASK_CONST(0xf171f) +#define DC_CMD_SIGNAL_RAISE2_0_SIGNAL_RAISE2_VECTOR_SHIFT _MK_SHIFT_CONST(0) +#define DC_CMD_SIGNAL_RAISE2_0_SIGNAL_RAISE2_VECTOR_FIELD _MK_FIELD_CONST(0x1f, DC_CMD_SIGNAL_RAISE2_0_SIGNAL_RAISE2_VECTOR_SHIFT) +#define DC_CMD_SIGNAL_RAISE2_0_SIGNAL_RAISE2_VECTOR_RANGE 4:0 +#define DC_CMD_SIGNAL_RAISE2_0_SIGNAL_RAISE2_VECTOR_WOFFSET 0x0 +#define DC_CMD_SIGNAL_RAISE2_0_SIGNAL_RAISE2_VECTOR_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_SIGNAL_RAISE2_0_SIGNAL_RAISE2_VECTOR_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_CMD_SIGNAL_RAISE2_0_SIGNAL_RAISE2_VECTOR_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_SIGNAL_RAISE2_0_SIGNAL_RAISE2_VECTOR_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_CMD_SIGNAL_RAISE2_0_SIGNAL_RAISE2_SELECT_SHIFT _MK_SHIFT_CONST(8) +#define DC_CMD_SIGNAL_RAISE2_0_SIGNAL_RAISE2_SELECT_FIELD _MK_FIELD_CONST(0x7, DC_CMD_SIGNAL_RAISE2_0_SIGNAL_RAISE2_SELECT_SHIFT) +#define DC_CMD_SIGNAL_RAISE2_0_SIGNAL_RAISE2_SELECT_RANGE 10:8 +#define DC_CMD_SIGNAL_RAISE2_0_SIGNAL_RAISE2_SELECT_WOFFSET 0x0 +#define DC_CMD_SIGNAL_RAISE2_0_SIGNAL_RAISE2_SELECT_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_SIGNAL_RAISE2_0_SIGNAL_RAISE2_SELECT_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_CMD_SIGNAL_RAISE2_0_SIGNAL_RAISE2_SELECT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_SIGNAL_RAISE2_0_SIGNAL_RAISE2_SELECT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_CMD_SIGNAL_RAISE2_0_SIGNAL_RAISE2_SELECT_NONE _MK_ENUM_CONST(0) +#define DC_CMD_SIGNAL_RAISE2_0_SIGNAL_RAISE2_SELECT_FRAME_END _MK_ENUM_CONST(1) +#define DC_CMD_SIGNAL_RAISE2_0_SIGNAL_RAISE2_SELECT_VBLANK _MK_ENUM_CONST(2) +#define DC_CMD_SIGNAL_RAISE2_0_SIGNAL_RAISE2_SELECT_VPULSE3 _MK_ENUM_CONST(3) +#define DC_CMD_SIGNAL_RAISE2_0_SIGNAL_RAISE2_SELECT_VBLANK_START _MK_ENUM_CONST(4) +#define DC_CMD_SIGNAL_RAISE2_0_SIGNAL_RAISE2_SELECT_VBLANK_END _MK_ENUM_CONST(5) +#define DC_CMD_SIGNAL_RAISE2_0_SIGNAL_RAISE2_SELECT_VPULSE3_START _MK_ENUM_CONST(6) +#define DC_CMD_SIGNAL_RAISE2_0_SIGNAL_RAISE2_SELECT_VPULSE3_END _MK_ENUM_CONST(7) + +#define DC_CMD_SIGNAL_RAISE2_0_SIGNAL_RAISE2_TYPE_SHIFT _MK_SHIFT_CONST(12) +#define DC_CMD_SIGNAL_RAISE2_0_SIGNAL_RAISE2_TYPE_FIELD _MK_FIELD_CONST(0x1, DC_CMD_SIGNAL_RAISE2_0_SIGNAL_RAISE2_TYPE_SHIFT) +#define DC_CMD_SIGNAL_RAISE2_0_SIGNAL_RAISE2_TYPE_RANGE 12:12 +#define DC_CMD_SIGNAL_RAISE2_0_SIGNAL_RAISE2_TYPE_WOFFSET 0x0 +#define DC_CMD_SIGNAL_RAISE2_0_SIGNAL_RAISE2_TYPE_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_SIGNAL_RAISE2_0_SIGNAL_RAISE2_TYPE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_CMD_SIGNAL_RAISE2_0_SIGNAL_RAISE2_TYPE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_SIGNAL_RAISE2_0_SIGNAL_RAISE2_TYPE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_CMD_SIGNAL_RAISE2_0_SIGNAL_RAISE2_TYPE_ONESHOT _MK_ENUM_CONST(0) +#define DC_CMD_SIGNAL_RAISE2_0_SIGNAL_RAISE2_TYPE_CONT _MK_ENUM_CONST(1) + +#define DC_CMD_SIGNAL_RAISE2_0_SIGNAL_RAISE2_CHANNEL_ID_SHIFT _MK_SHIFT_CONST(16) +#define DC_CMD_SIGNAL_RAISE2_0_SIGNAL_RAISE2_CHANNEL_ID_FIELD _MK_FIELD_CONST(0xf, DC_CMD_SIGNAL_RAISE2_0_SIGNAL_RAISE2_CHANNEL_ID_SHIFT) +#define DC_CMD_SIGNAL_RAISE2_0_SIGNAL_RAISE2_CHANNEL_ID_RANGE 19:16 +#define DC_CMD_SIGNAL_RAISE2_0_SIGNAL_RAISE2_CHANNEL_ID_WOFFSET 0x0 +#define DC_CMD_SIGNAL_RAISE2_0_SIGNAL_RAISE2_CHANNEL_ID_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_SIGNAL_RAISE2_0_SIGNAL_RAISE2_CHANNEL_ID_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_CMD_SIGNAL_RAISE2_0_SIGNAL_RAISE2_CHANNEL_ID_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_SIGNAL_RAISE2_0_SIGNAL_RAISE2_CHANNEL_ID_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_CMD_SIGNAL_RAISE3_0 +#define DC_CMD_SIGNAL_RAISE3_0 _MK_ADDR_CONST(0x3e) +#define DC_CMD_SIGNAL_RAISE3_0_SECURE 0x0 +#define DC_CMD_SIGNAL_RAISE3_0_WORD_COUNT 0x1 +#define DC_CMD_SIGNAL_RAISE3_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_CMD_SIGNAL_RAISE3_0_RESET_MASK _MK_MASK_CONST(0x1000) +#define DC_CMD_SIGNAL_RAISE3_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_CMD_SIGNAL_RAISE3_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_CMD_SIGNAL_RAISE3_0_READ_MASK _MK_MASK_CONST(0xf171f) +#define DC_CMD_SIGNAL_RAISE3_0_WRITE_MASK _MK_MASK_CONST(0xf171f) +#define DC_CMD_SIGNAL_RAISE3_0_SIGNAL_RAISE3_VECTOR_SHIFT _MK_SHIFT_CONST(0) +#define DC_CMD_SIGNAL_RAISE3_0_SIGNAL_RAISE3_VECTOR_FIELD _MK_FIELD_CONST(0x1f, DC_CMD_SIGNAL_RAISE3_0_SIGNAL_RAISE3_VECTOR_SHIFT) +#define DC_CMD_SIGNAL_RAISE3_0_SIGNAL_RAISE3_VECTOR_RANGE 4:0 +#define DC_CMD_SIGNAL_RAISE3_0_SIGNAL_RAISE3_VECTOR_WOFFSET 0x0 +#define DC_CMD_SIGNAL_RAISE3_0_SIGNAL_RAISE3_VECTOR_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_SIGNAL_RAISE3_0_SIGNAL_RAISE3_VECTOR_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_CMD_SIGNAL_RAISE3_0_SIGNAL_RAISE3_VECTOR_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_SIGNAL_RAISE3_0_SIGNAL_RAISE3_VECTOR_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_CMD_SIGNAL_RAISE3_0_SIGNAL_RAISE3_SELECT_SHIFT _MK_SHIFT_CONST(8) +#define DC_CMD_SIGNAL_RAISE3_0_SIGNAL_RAISE3_SELECT_FIELD _MK_FIELD_CONST(0x7, DC_CMD_SIGNAL_RAISE3_0_SIGNAL_RAISE3_SELECT_SHIFT) +#define DC_CMD_SIGNAL_RAISE3_0_SIGNAL_RAISE3_SELECT_RANGE 10:8 +#define DC_CMD_SIGNAL_RAISE3_0_SIGNAL_RAISE3_SELECT_WOFFSET 0x0 +#define DC_CMD_SIGNAL_RAISE3_0_SIGNAL_RAISE3_SELECT_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_SIGNAL_RAISE3_0_SIGNAL_RAISE3_SELECT_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_CMD_SIGNAL_RAISE3_0_SIGNAL_RAISE3_SELECT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_SIGNAL_RAISE3_0_SIGNAL_RAISE3_SELECT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_CMD_SIGNAL_RAISE3_0_SIGNAL_RAISE3_SELECT_NONE _MK_ENUM_CONST(0) +#define DC_CMD_SIGNAL_RAISE3_0_SIGNAL_RAISE3_SELECT_FRAME_END _MK_ENUM_CONST(1) +#define DC_CMD_SIGNAL_RAISE3_0_SIGNAL_RAISE3_SELECT_VBLANK _MK_ENUM_CONST(2) +#define DC_CMD_SIGNAL_RAISE3_0_SIGNAL_RAISE3_SELECT_VPULSE3 _MK_ENUM_CONST(3) +#define DC_CMD_SIGNAL_RAISE3_0_SIGNAL_RAISE3_SELECT_VBLANK_START _MK_ENUM_CONST(4) +#define DC_CMD_SIGNAL_RAISE3_0_SIGNAL_RAISE3_SELECT_VBLANK_END _MK_ENUM_CONST(5) +#define DC_CMD_SIGNAL_RAISE3_0_SIGNAL_RAISE3_SELECT_VPULSE3_START _MK_ENUM_CONST(6) +#define DC_CMD_SIGNAL_RAISE3_0_SIGNAL_RAISE3_SELECT_VPULSE3_END _MK_ENUM_CONST(7) + +#define DC_CMD_SIGNAL_RAISE3_0_SIGNAL_RAISE3_TYPE_SHIFT _MK_SHIFT_CONST(12) +#define DC_CMD_SIGNAL_RAISE3_0_SIGNAL_RAISE3_TYPE_FIELD _MK_FIELD_CONST(0x1, DC_CMD_SIGNAL_RAISE3_0_SIGNAL_RAISE3_TYPE_SHIFT) +#define DC_CMD_SIGNAL_RAISE3_0_SIGNAL_RAISE3_TYPE_RANGE 12:12 +#define DC_CMD_SIGNAL_RAISE3_0_SIGNAL_RAISE3_TYPE_WOFFSET 0x0 +#define DC_CMD_SIGNAL_RAISE3_0_SIGNAL_RAISE3_TYPE_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_SIGNAL_RAISE3_0_SIGNAL_RAISE3_TYPE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_CMD_SIGNAL_RAISE3_0_SIGNAL_RAISE3_TYPE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_SIGNAL_RAISE3_0_SIGNAL_RAISE3_TYPE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_CMD_SIGNAL_RAISE3_0_SIGNAL_RAISE3_TYPE_ONESHOT _MK_ENUM_CONST(0) +#define DC_CMD_SIGNAL_RAISE3_0_SIGNAL_RAISE3_TYPE_CONT _MK_ENUM_CONST(1) + +#define DC_CMD_SIGNAL_RAISE3_0_SIGNAL_RAISE3_CHANNEL_ID_SHIFT _MK_SHIFT_CONST(16) +#define DC_CMD_SIGNAL_RAISE3_0_SIGNAL_RAISE3_CHANNEL_ID_FIELD _MK_FIELD_CONST(0xf, DC_CMD_SIGNAL_RAISE3_0_SIGNAL_RAISE3_CHANNEL_ID_SHIFT) +#define DC_CMD_SIGNAL_RAISE3_0_SIGNAL_RAISE3_CHANNEL_ID_RANGE 19:16 +#define DC_CMD_SIGNAL_RAISE3_0_SIGNAL_RAISE3_CHANNEL_ID_WOFFSET 0x0 +#define DC_CMD_SIGNAL_RAISE3_0_SIGNAL_RAISE3_CHANNEL_ID_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_SIGNAL_RAISE3_0_SIGNAL_RAISE3_CHANNEL_ID_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_CMD_SIGNAL_RAISE3_0_SIGNAL_RAISE3_CHANNEL_ID_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_SIGNAL_RAISE3_0_SIGNAL_RAISE3_CHANNEL_ID_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Reserved address 63 [0x3f] + +// Register DC_CMD_STATE_ACCESS_0 +#define DC_CMD_STATE_ACCESS_0 _MK_ADDR_CONST(0x40) +#define DC_CMD_STATE_ACCESS_0_SECURE 0x0 +#define DC_CMD_STATE_ACCESS_0_WORD_COUNT 0x1 +#define DC_CMD_STATE_ACCESS_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_CMD_STATE_ACCESS_0_RESET_MASK _MK_MASK_CONST(0x5) +#define DC_CMD_STATE_ACCESS_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_CMD_STATE_ACCESS_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_CMD_STATE_ACCESS_0_READ_MASK _MK_MASK_CONST(0x5) +#define DC_CMD_STATE_ACCESS_0_WRITE_MASK _MK_MASK_CONST(0x5) +#define DC_CMD_STATE_ACCESS_0_READ_MUX_SHIFT _MK_SHIFT_CONST(0) +#define DC_CMD_STATE_ACCESS_0_READ_MUX_FIELD _MK_FIELD_CONST(0x1, DC_CMD_STATE_ACCESS_0_READ_MUX_SHIFT) +#define DC_CMD_STATE_ACCESS_0_READ_MUX_RANGE 0:0 +#define DC_CMD_STATE_ACCESS_0_READ_MUX_WOFFSET 0x0 +#define DC_CMD_STATE_ACCESS_0_READ_MUX_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_STATE_ACCESS_0_READ_MUX_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_CMD_STATE_ACCESS_0_READ_MUX_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_STATE_ACCESS_0_READ_MUX_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_CMD_STATE_ACCESS_0_READ_MUX_ASSEMBLY _MK_ENUM_CONST(0) +#define DC_CMD_STATE_ACCESS_0_READ_MUX_ACTIVE _MK_ENUM_CONST(1) + +#define DC_CMD_STATE_ACCESS_0_WRITE_MUX_SHIFT _MK_SHIFT_CONST(2) +#define DC_CMD_STATE_ACCESS_0_WRITE_MUX_FIELD _MK_FIELD_CONST(0x1, DC_CMD_STATE_ACCESS_0_WRITE_MUX_SHIFT) +#define DC_CMD_STATE_ACCESS_0_WRITE_MUX_RANGE 2:2 +#define DC_CMD_STATE_ACCESS_0_WRITE_MUX_WOFFSET 0x0 +#define DC_CMD_STATE_ACCESS_0_WRITE_MUX_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_STATE_ACCESS_0_WRITE_MUX_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_CMD_STATE_ACCESS_0_WRITE_MUX_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_STATE_ACCESS_0_WRITE_MUX_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_CMD_STATE_ACCESS_0_WRITE_MUX_ASSEMBLY _MK_ENUM_CONST(0) +#define DC_CMD_STATE_ACCESS_0_WRITE_MUX_ACTIVE _MK_ENUM_CONST(1) + + +// Register DC_CMD_STATE_CONTROL_0 +#define DC_CMD_STATE_CONTROL_0 _MK_ADDR_CONST(0x41) +#define DC_CMD_STATE_CONTROL_0_SECURE 0x0 +#define DC_CMD_STATE_CONTROL_0_WORD_COUNT 0x1 +#define DC_CMD_STATE_CONTROL_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_CMD_STATE_CONTROL_0_RESET_MASK _MK_MASK_CONST(0x1009f9f) +#define DC_CMD_STATE_CONTROL_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_CMD_STATE_CONTROL_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_CMD_STATE_CONTROL_0_READ_MASK _MK_MASK_CONST(0x1009f9f) +#define DC_CMD_STATE_CONTROL_0_WRITE_MASK _MK_MASK_CONST(0x1009f9f) +#define DC_CMD_STATE_CONTROL_0_GENERAL_ACT_REQ_SHIFT _MK_SHIFT_CONST(0) +#define DC_CMD_STATE_CONTROL_0_GENERAL_ACT_REQ_FIELD _MK_FIELD_CONST(0x1, DC_CMD_STATE_CONTROL_0_GENERAL_ACT_REQ_SHIFT) +#define DC_CMD_STATE_CONTROL_0_GENERAL_ACT_REQ_RANGE 0:0 +#define DC_CMD_STATE_CONTROL_0_GENERAL_ACT_REQ_WOFFSET 0x0 +#define DC_CMD_STATE_CONTROL_0_GENERAL_ACT_REQ_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_STATE_CONTROL_0_GENERAL_ACT_REQ_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_CMD_STATE_CONTROL_0_GENERAL_ACT_REQ_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_STATE_CONTROL_0_GENERAL_ACT_REQ_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_CMD_STATE_CONTROL_0_GENERAL_ACT_REQ_DISABLE _MK_ENUM_CONST(0) +#define DC_CMD_STATE_CONTROL_0_GENERAL_ACT_REQ_ENABLE _MK_ENUM_CONST(1) + +#define DC_CMD_STATE_CONTROL_0_WIN_A_ACT_REQ_SHIFT _MK_SHIFT_CONST(1) +#define DC_CMD_STATE_CONTROL_0_WIN_A_ACT_REQ_FIELD _MK_FIELD_CONST(0x1, DC_CMD_STATE_CONTROL_0_WIN_A_ACT_REQ_SHIFT) +#define DC_CMD_STATE_CONTROL_0_WIN_A_ACT_REQ_RANGE 1:1 +#define DC_CMD_STATE_CONTROL_0_WIN_A_ACT_REQ_WOFFSET 0x0 +#define DC_CMD_STATE_CONTROL_0_WIN_A_ACT_REQ_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_STATE_CONTROL_0_WIN_A_ACT_REQ_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_CMD_STATE_CONTROL_0_WIN_A_ACT_REQ_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_STATE_CONTROL_0_WIN_A_ACT_REQ_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_CMD_STATE_CONTROL_0_WIN_A_ACT_REQ_DISABLE _MK_ENUM_CONST(0) +#define DC_CMD_STATE_CONTROL_0_WIN_A_ACT_REQ_ENABLE _MK_ENUM_CONST(1) + +#define DC_CMD_STATE_CONTROL_0_WIN_B_ACT_REQ_SHIFT _MK_SHIFT_CONST(2) +#define DC_CMD_STATE_CONTROL_0_WIN_B_ACT_REQ_FIELD _MK_FIELD_CONST(0x1, DC_CMD_STATE_CONTROL_0_WIN_B_ACT_REQ_SHIFT) +#define DC_CMD_STATE_CONTROL_0_WIN_B_ACT_REQ_RANGE 2:2 +#define DC_CMD_STATE_CONTROL_0_WIN_B_ACT_REQ_WOFFSET 0x0 +#define DC_CMD_STATE_CONTROL_0_WIN_B_ACT_REQ_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_STATE_CONTROL_0_WIN_B_ACT_REQ_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_CMD_STATE_CONTROL_0_WIN_B_ACT_REQ_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_STATE_CONTROL_0_WIN_B_ACT_REQ_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_CMD_STATE_CONTROL_0_WIN_B_ACT_REQ_DISABLE _MK_ENUM_CONST(0) +#define DC_CMD_STATE_CONTROL_0_WIN_B_ACT_REQ_ENABLE _MK_ENUM_CONST(1) + +#define DC_CMD_STATE_CONTROL_0_WIN_C_ACT_REQ_SHIFT _MK_SHIFT_CONST(3) +#define DC_CMD_STATE_CONTROL_0_WIN_C_ACT_REQ_FIELD _MK_FIELD_CONST(0x1, DC_CMD_STATE_CONTROL_0_WIN_C_ACT_REQ_SHIFT) +#define DC_CMD_STATE_CONTROL_0_WIN_C_ACT_REQ_RANGE 3:3 +#define DC_CMD_STATE_CONTROL_0_WIN_C_ACT_REQ_WOFFSET 0x0 +#define DC_CMD_STATE_CONTROL_0_WIN_C_ACT_REQ_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_STATE_CONTROL_0_WIN_C_ACT_REQ_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_CMD_STATE_CONTROL_0_WIN_C_ACT_REQ_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_STATE_CONTROL_0_WIN_C_ACT_REQ_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_CMD_STATE_CONTROL_0_WIN_C_ACT_REQ_DISABLE _MK_ENUM_CONST(0) +#define DC_CMD_STATE_CONTROL_0_WIN_C_ACT_REQ_ENABLE _MK_ENUM_CONST(1) + +#define DC_CMD_STATE_CONTROL_0_WIN_D_ACT_REQ_SHIFT _MK_SHIFT_CONST(4) +#define DC_CMD_STATE_CONTROL_0_WIN_D_ACT_REQ_FIELD _MK_FIELD_CONST(0x1, DC_CMD_STATE_CONTROL_0_WIN_D_ACT_REQ_SHIFT) +#define DC_CMD_STATE_CONTROL_0_WIN_D_ACT_REQ_RANGE 4:4 +#define DC_CMD_STATE_CONTROL_0_WIN_D_ACT_REQ_WOFFSET 0x0 +#define DC_CMD_STATE_CONTROL_0_WIN_D_ACT_REQ_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_STATE_CONTROL_0_WIN_D_ACT_REQ_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_CMD_STATE_CONTROL_0_WIN_D_ACT_REQ_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_STATE_CONTROL_0_WIN_D_ACT_REQ_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_CMD_STATE_CONTROL_0_WIN_D_ACT_REQ_DISABLE _MK_ENUM_CONST(0) +#define DC_CMD_STATE_CONTROL_0_WIN_D_ACT_REQ_ENABLE _MK_ENUM_CONST(1) + +#define DC_CMD_STATE_CONTROL_0_CURSOR_ACT_REQ_SHIFT _MK_SHIFT_CONST(7) +#define DC_CMD_STATE_CONTROL_0_CURSOR_ACT_REQ_FIELD _MK_FIELD_CONST(0x1, DC_CMD_STATE_CONTROL_0_CURSOR_ACT_REQ_SHIFT) +#define DC_CMD_STATE_CONTROL_0_CURSOR_ACT_REQ_RANGE 7:7 +#define DC_CMD_STATE_CONTROL_0_CURSOR_ACT_REQ_WOFFSET 0x0 +#define DC_CMD_STATE_CONTROL_0_CURSOR_ACT_REQ_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_STATE_CONTROL_0_CURSOR_ACT_REQ_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_CMD_STATE_CONTROL_0_CURSOR_ACT_REQ_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_STATE_CONTROL_0_CURSOR_ACT_REQ_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_CMD_STATE_CONTROL_0_CURSOR_ACT_REQ_DISABLE _MK_ENUM_CONST(0) +#define DC_CMD_STATE_CONTROL_0_CURSOR_ACT_REQ_ENABLE _MK_ENUM_CONST(1) + +#define DC_CMD_STATE_CONTROL_0_GENERAL_UPDATE_SHIFT _MK_SHIFT_CONST(8) +#define DC_CMD_STATE_CONTROL_0_GENERAL_UPDATE_FIELD _MK_FIELD_CONST(0x1, DC_CMD_STATE_CONTROL_0_GENERAL_UPDATE_SHIFT) +#define DC_CMD_STATE_CONTROL_0_GENERAL_UPDATE_RANGE 8:8 +#define DC_CMD_STATE_CONTROL_0_GENERAL_UPDATE_WOFFSET 0x0 +#define DC_CMD_STATE_CONTROL_0_GENERAL_UPDATE_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_STATE_CONTROL_0_GENERAL_UPDATE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_CMD_STATE_CONTROL_0_GENERAL_UPDATE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_STATE_CONTROL_0_GENERAL_UPDATE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_CMD_STATE_CONTROL_0_GENERAL_UPDATE_DISABLE _MK_ENUM_CONST(0) +#define DC_CMD_STATE_CONTROL_0_GENERAL_UPDATE_ENABLE _MK_ENUM_CONST(1) + +#define DC_CMD_STATE_CONTROL_0_WIN_A_UPDATE_SHIFT _MK_SHIFT_CONST(9) +#define DC_CMD_STATE_CONTROL_0_WIN_A_UPDATE_FIELD _MK_FIELD_CONST(0x1, DC_CMD_STATE_CONTROL_0_WIN_A_UPDATE_SHIFT) +#define DC_CMD_STATE_CONTROL_0_WIN_A_UPDATE_RANGE 9:9 +#define DC_CMD_STATE_CONTROL_0_WIN_A_UPDATE_WOFFSET 0x0 +#define DC_CMD_STATE_CONTROL_0_WIN_A_UPDATE_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_STATE_CONTROL_0_WIN_A_UPDATE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_CMD_STATE_CONTROL_0_WIN_A_UPDATE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_STATE_CONTROL_0_WIN_A_UPDATE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_CMD_STATE_CONTROL_0_WIN_A_UPDATE_DISABLE _MK_ENUM_CONST(0) +#define DC_CMD_STATE_CONTROL_0_WIN_A_UPDATE_ENABLE _MK_ENUM_CONST(1) + +#define DC_CMD_STATE_CONTROL_0_WIN_B_UPDATE_SHIFT _MK_SHIFT_CONST(10) +#define DC_CMD_STATE_CONTROL_0_WIN_B_UPDATE_FIELD _MK_FIELD_CONST(0x1, DC_CMD_STATE_CONTROL_0_WIN_B_UPDATE_SHIFT) +#define DC_CMD_STATE_CONTROL_0_WIN_B_UPDATE_RANGE 10:10 +#define DC_CMD_STATE_CONTROL_0_WIN_B_UPDATE_WOFFSET 0x0 +#define DC_CMD_STATE_CONTROL_0_WIN_B_UPDATE_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_STATE_CONTROL_0_WIN_B_UPDATE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_CMD_STATE_CONTROL_0_WIN_B_UPDATE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_STATE_CONTROL_0_WIN_B_UPDATE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_CMD_STATE_CONTROL_0_WIN_B_UPDATE_DISABLE _MK_ENUM_CONST(0) +#define DC_CMD_STATE_CONTROL_0_WIN_B_UPDATE_ENABLE _MK_ENUM_CONST(1) + +#define DC_CMD_STATE_CONTROL_0_WIN_C_UPDATE_SHIFT _MK_SHIFT_CONST(11) +#define DC_CMD_STATE_CONTROL_0_WIN_C_UPDATE_FIELD _MK_FIELD_CONST(0x1, DC_CMD_STATE_CONTROL_0_WIN_C_UPDATE_SHIFT) +#define DC_CMD_STATE_CONTROL_0_WIN_C_UPDATE_RANGE 11:11 +#define DC_CMD_STATE_CONTROL_0_WIN_C_UPDATE_WOFFSET 0x0 +#define DC_CMD_STATE_CONTROL_0_WIN_C_UPDATE_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_STATE_CONTROL_0_WIN_C_UPDATE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_CMD_STATE_CONTROL_0_WIN_C_UPDATE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_STATE_CONTROL_0_WIN_C_UPDATE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_CMD_STATE_CONTROL_0_WIN_C_UPDATE_DISABLE _MK_ENUM_CONST(0) +#define DC_CMD_STATE_CONTROL_0_WIN_C_UPDATE_ENABLE _MK_ENUM_CONST(1) + +#define DC_CMD_STATE_CONTROL_0_WIN_D_UPDATE_SHIFT _MK_SHIFT_CONST(12) +#define DC_CMD_STATE_CONTROL_0_WIN_D_UPDATE_FIELD _MK_FIELD_CONST(0x1, DC_CMD_STATE_CONTROL_0_WIN_D_UPDATE_SHIFT) +#define DC_CMD_STATE_CONTROL_0_WIN_D_UPDATE_RANGE 12:12 +#define DC_CMD_STATE_CONTROL_0_WIN_D_UPDATE_WOFFSET 0x0 +#define DC_CMD_STATE_CONTROL_0_WIN_D_UPDATE_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_STATE_CONTROL_0_WIN_D_UPDATE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_CMD_STATE_CONTROL_0_WIN_D_UPDATE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_STATE_CONTROL_0_WIN_D_UPDATE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_CMD_STATE_CONTROL_0_WIN_D_UPDATE_DISABLE _MK_ENUM_CONST(0) +#define DC_CMD_STATE_CONTROL_0_WIN_D_UPDATE_ENABLE _MK_ENUM_CONST(1) + +#define DC_CMD_STATE_CONTROL_0_CURSOR_UPDATE_SHIFT _MK_SHIFT_CONST(15) +#define DC_CMD_STATE_CONTROL_0_CURSOR_UPDATE_FIELD _MK_FIELD_CONST(0x1, DC_CMD_STATE_CONTROL_0_CURSOR_UPDATE_SHIFT) +#define DC_CMD_STATE_CONTROL_0_CURSOR_UPDATE_RANGE 15:15 +#define DC_CMD_STATE_CONTROL_0_CURSOR_UPDATE_WOFFSET 0x0 +#define DC_CMD_STATE_CONTROL_0_CURSOR_UPDATE_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_STATE_CONTROL_0_CURSOR_UPDATE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_CMD_STATE_CONTROL_0_CURSOR_UPDATE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_STATE_CONTROL_0_CURSOR_UPDATE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_CMD_STATE_CONTROL_0_CURSOR_UPDATE_DISABLE _MK_ENUM_CONST(0) +#define DC_CMD_STATE_CONTROL_0_CURSOR_UPDATE_ENABLE _MK_ENUM_CONST(1) + +#define DC_CMD_STATE_CONTROL_0_NC_HOST_TRIG_ENABLE_SHIFT _MK_SHIFT_CONST(24) +#define DC_CMD_STATE_CONTROL_0_NC_HOST_TRIG_ENABLE_FIELD _MK_FIELD_CONST(0x1, DC_CMD_STATE_CONTROL_0_NC_HOST_TRIG_ENABLE_SHIFT) +#define DC_CMD_STATE_CONTROL_0_NC_HOST_TRIG_ENABLE_RANGE 24:24 +#define DC_CMD_STATE_CONTROL_0_NC_HOST_TRIG_ENABLE_WOFFSET 0x0 +#define DC_CMD_STATE_CONTROL_0_NC_HOST_TRIG_ENABLE_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_STATE_CONTROL_0_NC_HOST_TRIG_ENABLE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_CMD_STATE_CONTROL_0_NC_HOST_TRIG_ENABLE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_STATE_CONTROL_0_NC_HOST_TRIG_ENABLE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_CMD_STATE_CONTROL_0_NC_HOST_TRIG_ENABLE_DISABLE _MK_ENUM_CONST(0) +#define DC_CMD_STATE_CONTROL_0_NC_HOST_TRIG_ENABLE_ENABLE _MK_ENUM_CONST(1) + + +// Register DC_CMD_DISPLAY_WINDOW_HEADER_0 +#define DC_CMD_DISPLAY_WINDOW_HEADER_0 _MK_ADDR_CONST(0x42) +#define DC_CMD_DISPLAY_WINDOW_HEADER_0_SECURE 0x0 +#define DC_CMD_DISPLAY_WINDOW_HEADER_0_WORD_COUNT 0x1 +#define DC_CMD_DISPLAY_WINDOW_HEADER_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_CMD_DISPLAY_WINDOW_HEADER_0_RESET_MASK _MK_MASK_CONST(0xf0) +#define DC_CMD_DISPLAY_WINDOW_HEADER_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_CMD_DISPLAY_WINDOW_HEADER_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_CMD_DISPLAY_WINDOW_HEADER_0_READ_MASK _MK_MASK_CONST(0xf0) +#define DC_CMD_DISPLAY_WINDOW_HEADER_0_WRITE_MASK _MK_MASK_CONST(0xf0) +#define DC_CMD_DISPLAY_WINDOW_HEADER_0_WINDOW_A_SELECT_SHIFT _MK_SHIFT_CONST(4) +#define DC_CMD_DISPLAY_WINDOW_HEADER_0_WINDOW_A_SELECT_FIELD _MK_FIELD_CONST(0x1, DC_CMD_DISPLAY_WINDOW_HEADER_0_WINDOW_A_SELECT_SHIFT) +#define DC_CMD_DISPLAY_WINDOW_HEADER_0_WINDOW_A_SELECT_RANGE 4:4 +#define DC_CMD_DISPLAY_WINDOW_HEADER_0_WINDOW_A_SELECT_WOFFSET 0x0 +#define DC_CMD_DISPLAY_WINDOW_HEADER_0_WINDOW_A_SELECT_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_DISPLAY_WINDOW_HEADER_0_WINDOW_A_SELECT_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_CMD_DISPLAY_WINDOW_HEADER_0_WINDOW_A_SELECT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_DISPLAY_WINDOW_HEADER_0_WINDOW_A_SELECT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_CMD_DISPLAY_WINDOW_HEADER_0_WINDOW_A_SELECT_DISABLE _MK_ENUM_CONST(0) +#define DC_CMD_DISPLAY_WINDOW_HEADER_0_WINDOW_A_SELECT_ENABLE _MK_ENUM_CONST(1) + +#define DC_CMD_DISPLAY_WINDOW_HEADER_0_WINDOW_B_SELECT_SHIFT _MK_SHIFT_CONST(5) +#define DC_CMD_DISPLAY_WINDOW_HEADER_0_WINDOW_B_SELECT_FIELD _MK_FIELD_CONST(0x1, DC_CMD_DISPLAY_WINDOW_HEADER_0_WINDOW_B_SELECT_SHIFT) +#define DC_CMD_DISPLAY_WINDOW_HEADER_0_WINDOW_B_SELECT_RANGE 5:5 +#define DC_CMD_DISPLAY_WINDOW_HEADER_0_WINDOW_B_SELECT_WOFFSET 0x0 +#define DC_CMD_DISPLAY_WINDOW_HEADER_0_WINDOW_B_SELECT_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_DISPLAY_WINDOW_HEADER_0_WINDOW_B_SELECT_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_CMD_DISPLAY_WINDOW_HEADER_0_WINDOW_B_SELECT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_DISPLAY_WINDOW_HEADER_0_WINDOW_B_SELECT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_CMD_DISPLAY_WINDOW_HEADER_0_WINDOW_B_SELECT_DISABLE _MK_ENUM_CONST(0) +#define DC_CMD_DISPLAY_WINDOW_HEADER_0_WINDOW_B_SELECT_ENABLE _MK_ENUM_CONST(1) + +#define DC_CMD_DISPLAY_WINDOW_HEADER_0_WINDOW_C_SELECT_SHIFT _MK_SHIFT_CONST(6) +#define DC_CMD_DISPLAY_WINDOW_HEADER_0_WINDOW_C_SELECT_FIELD _MK_FIELD_CONST(0x1, DC_CMD_DISPLAY_WINDOW_HEADER_0_WINDOW_C_SELECT_SHIFT) +#define DC_CMD_DISPLAY_WINDOW_HEADER_0_WINDOW_C_SELECT_RANGE 6:6 +#define DC_CMD_DISPLAY_WINDOW_HEADER_0_WINDOW_C_SELECT_WOFFSET 0x0 +#define DC_CMD_DISPLAY_WINDOW_HEADER_0_WINDOW_C_SELECT_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_DISPLAY_WINDOW_HEADER_0_WINDOW_C_SELECT_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_CMD_DISPLAY_WINDOW_HEADER_0_WINDOW_C_SELECT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_DISPLAY_WINDOW_HEADER_0_WINDOW_C_SELECT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_CMD_DISPLAY_WINDOW_HEADER_0_WINDOW_C_SELECT_DISABLE _MK_ENUM_CONST(0) +#define DC_CMD_DISPLAY_WINDOW_HEADER_0_WINDOW_C_SELECT_ENABLE _MK_ENUM_CONST(1) + +#define DC_CMD_DISPLAY_WINDOW_HEADER_0_WINDOW_D_SELECT_SHIFT _MK_SHIFT_CONST(7) +#define DC_CMD_DISPLAY_WINDOW_HEADER_0_WINDOW_D_SELECT_FIELD _MK_FIELD_CONST(0x1, DC_CMD_DISPLAY_WINDOW_HEADER_0_WINDOW_D_SELECT_SHIFT) +#define DC_CMD_DISPLAY_WINDOW_HEADER_0_WINDOW_D_SELECT_RANGE 7:7 +#define DC_CMD_DISPLAY_WINDOW_HEADER_0_WINDOW_D_SELECT_WOFFSET 0x0 +#define DC_CMD_DISPLAY_WINDOW_HEADER_0_WINDOW_D_SELECT_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_DISPLAY_WINDOW_HEADER_0_WINDOW_D_SELECT_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_CMD_DISPLAY_WINDOW_HEADER_0_WINDOW_D_SELECT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_DISPLAY_WINDOW_HEADER_0_WINDOW_D_SELECT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_CMD_DISPLAY_WINDOW_HEADER_0_WINDOW_D_SELECT_DISABLE _MK_ENUM_CONST(0) +#define DC_CMD_DISPLAY_WINDOW_HEADER_0_WINDOW_D_SELECT_ENABLE _MK_ENUM_CONST(1) + + +// Register DC_CMD_REG_ACT_CONTROL_0 +#define DC_CMD_REG_ACT_CONTROL_0 _MK_ADDR_CONST(0x43) +#define DC_CMD_REG_ACT_CONTROL_0_SECURE 0x0 +#define DC_CMD_REG_ACT_CONTROL_0_WORD_COUNT 0x1 +#define DC_CMD_REG_ACT_CONTROL_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_CMD_REG_ACT_CONTROL_0_RESET_MASK _MK_MASK_CONST(0x4d5) +#define DC_CMD_REG_ACT_CONTROL_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_CMD_REG_ACT_CONTROL_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_CMD_REG_ACT_CONTROL_0_READ_MASK _MK_MASK_CONST(0x4d5) +#define DC_CMD_REG_ACT_CONTROL_0_WRITE_MASK _MK_MASK_CONST(0x4d5) +#define DC_CMD_REG_ACT_CONTROL_0_GENERAL_ACT_CNTR_SEL_SHIFT _MK_SHIFT_CONST(0) +#define DC_CMD_REG_ACT_CONTROL_0_GENERAL_ACT_CNTR_SEL_FIELD _MK_FIELD_CONST(0x1, DC_CMD_REG_ACT_CONTROL_0_GENERAL_ACT_CNTR_SEL_SHIFT) +#define DC_CMD_REG_ACT_CONTROL_0_GENERAL_ACT_CNTR_SEL_RANGE 0:0 +#define DC_CMD_REG_ACT_CONTROL_0_GENERAL_ACT_CNTR_SEL_WOFFSET 0x0 +#define DC_CMD_REG_ACT_CONTROL_0_GENERAL_ACT_CNTR_SEL_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_REG_ACT_CONTROL_0_GENERAL_ACT_CNTR_SEL_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_CMD_REG_ACT_CONTROL_0_GENERAL_ACT_CNTR_SEL_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_REG_ACT_CONTROL_0_GENERAL_ACT_CNTR_SEL_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_CMD_REG_ACT_CONTROL_0_GENERAL_ACT_CNTR_SEL_VCOUNTER _MK_ENUM_CONST(0) +#define DC_CMD_REG_ACT_CONTROL_0_GENERAL_ACT_CNTR_SEL_HCOUNTER _MK_ENUM_CONST(1) + +#define DC_CMD_REG_ACT_CONTROL_0_WIN_A_ACT_CNTR_SEL_SHIFT _MK_SHIFT_CONST(2) +#define DC_CMD_REG_ACT_CONTROL_0_WIN_A_ACT_CNTR_SEL_FIELD _MK_FIELD_CONST(0x1, DC_CMD_REG_ACT_CONTROL_0_WIN_A_ACT_CNTR_SEL_SHIFT) +#define DC_CMD_REG_ACT_CONTROL_0_WIN_A_ACT_CNTR_SEL_RANGE 2:2 +#define DC_CMD_REG_ACT_CONTROL_0_WIN_A_ACT_CNTR_SEL_WOFFSET 0x0 +#define DC_CMD_REG_ACT_CONTROL_0_WIN_A_ACT_CNTR_SEL_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_REG_ACT_CONTROL_0_WIN_A_ACT_CNTR_SEL_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_CMD_REG_ACT_CONTROL_0_WIN_A_ACT_CNTR_SEL_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_REG_ACT_CONTROL_0_WIN_A_ACT_CNTR_SEL_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_CMD_REG_ACT_CONTROL_0_WIN_A_ACT_CNTR_SEL_VCOUNTER _MK_ENUM_CONST(0) +#define DC_CMD_REG_ACT_CONTROL_0_WIN_A_ACT_CNTR_SEL_HCOUNTER _MK_ENUM_CONST(1) + +#define DC_CMD_REG_ACT_CONTROL_0_WIN_B_ACT_CNTR_SEL_SHIFT _MK_SHIFT_CONST(4) +#define DC_CMD_REG_ACT_CONTROL_0_WIN_B_ACT_CNTR_SEL_FIELD _MK_FIELD_CONST(0x1, DC_CMD_REG_ACT_CONTROL_0_WIN_B_ACT_CNTR_SEL_SHIFT) +#define DC_CMD_REG_ACT_CONTROL_0_WIN_B_ACT_CNTR_SEL_RANGE 4:4 +#define DC_CMD_REG_ACT_CONTROL_0_WIN_B_ACT_CNTR_SEL_WOFFSET 0x0 +#define DC_CMD_REG_ACT_CONTROL_0_WIN_B_ACT_CNTR_SEL_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_REG_ACT_CONTROL_0_WIN_B_ACT_CNTR_SEL_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_CMD_REG_ACT_CONTROL_0_WIN_B_ACT_CNTR_SEL_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_REG_ACT_CONTROL_0_WIN_B_ACT_CNTR_SEL_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_CMD_REG_ACT_CONTROL_0_WIN_B_ACT_CNTR_SEL_VCOUNTER _MK_ENUM_CONST(0) +#define DC_CMD_REG_ACT_CONTROL_0_WIN_B_ACT_CNTR_SEL_HCOUNTER _MK_ENUM_CONST(1) + +#define DC_CMD_REG_ACT_CONTROL_0_WIN_C_ACT_CNTR_SEL_SHIFT _MK_SHIFT_CONST(6) +#define DC_CMD_REG_ACT_CONTROL_0_WIN_C_ACT_CNTR_SEL_FIELD _MK_FIELD_CONST(0x1, DC_CMD_REG_ACT_CONTROL_0_WIN_C_ACT_CNTR_SEL_SHIFT) +#define DC_CMD_REG_ACT_CONTROL_0_WIN_C_ACT_CNTR_SEL_RANGE 6:6 +#define DC_CMD_REG_ACT_CONTROL_0_WIN_C_ACT_CNTR_SEL_WOFFSET 0x0 +#define DC_CMD_REG_ACT_CONTROL_0_WIN_C_ACT_CNTR_SEL_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_REG_ACT_CONTROL_0_WIN_C_ACT_CNTR_SEL_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_CMD_REG_ACT_CONTROL_0_WIN_C_ACT_CNTR_SEL_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_REG_ACT_CONTROL_0_WIN_C_ACT_CNTR_SEL_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_CMD_REG_ACT_CONTROL_0_WIN_C_ACT_CNTR_SEL_VCOUNTER _MK_ENUM_CONST(0) +#define DC_CMD_REG_ACT_CONTROL_0_WIN_C_ACT_CNTR_SEL_HCOUNTER _MK_ENUM_CONST(1) + +#define DC_CMD_REG_ACT_CONTROL_0_CURSOR_ACT_CNTR_SEL_SHIFT _MK_SHIFT_CONST(7) +#define DC_CMD_REG_ACT_CONTROL_0_CURSOR_ACT_CNTR_SEL_FIELD _MK_FIELD_CONST(0x1, DC_CMD_REG_ACT_CONTROL_0_CURSOR_ACT_CNTR_SEL_SHIFT) +#define DC_CMD_REG_ACT_CONTROL_0_CURSOR_ACT_CNTR_SEL_RANGE 7:7 +#define DC_CMD_REG_ACT_CONTROL_0_CURSOR_ACT_CNTR_SEL_WOFFSET 0x0 +#define DC_CMD_REG_ACT_CONTROL_0_CURSOR_ACT_CNTR_SEL_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_REG_ACT_CONTROL_0_CURSOR_ACT_CNTR_SEL_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_CMD_REG_ACT_CONTROL_0_CURSOR_ACT_CNTR_SEL_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_REG_ACT_CONTROL_0_CURSOR_ACT_CNTR_SEL_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_CMD_REG_ACT_CONTROL_0_CURSOR_ACT_CNTR_SEL_VCOUNTER _MK_ENUM_CONST(0) +#define DC_CMD_REG_ACT_CONTROL_0_CURSOR_ACT_CNTR_SEL_HCOUNTER _MK_ENUM_CONST(1) + +#define DC_CMD_REG_ACT_CONTROL_0_WIN_D_ACT_CNTR_SEL_SHIFT _MK_SHIFT_CONST(10) +#define DC_CMD_REG_ACT_CONTROL_0_WIN_D_ACT_CNTR_SEL_FIELD _MK_FIELD_CONST(0x1, DC_CMD_REG_ACT_CONTROL_0_WIN_D_ACT_CNTR_SEL_SHIFT) +#define DC_CMD_REG_ACT_CONTROL_0_WIN_D_ACT_CNTR_SEL_RANGE 10:10 +#define DC_CMD_REG_ACT_CONTROL_0_WIN_D_ACT_CNTR_SEL_WOFFSET 0x0 +#define DC_CMD_REG_ACT_CONTROL_0_WIN_D_ACT_CNTR_SEL_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_REG_ACT_CONTROL_0_WIN_D_ACT_CNTR_SEL_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_CMD_REG_ACT_CONTROL_0_WIN_D_ACT_CNTR_SEL_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_REG_ACT_CONTROL_0_WIN_D_ACT_CNTR_SEL_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_CMD_REG_ACT_CONTROL_0_WIN_D_ACT_CNTR_SEL_VCOUNTER _MK_ENUM_CONST(0) +#define DC_CMD_REG_ACT_CONTROL_0_WIN_D_ACT_CNTR_SEL_HCOUNTER _MK_ENUM_CONST(1) + + +// Register DC_CMD_WIN_T_STATE_CONTROL_0 +#define DC_CMD_WIN_T_STATE_CONTROL_0 _MK_ADDR_CONST(0x44) +#define DC_CMD_WIN_T_STATE_CONTROL_0_SECURE 0x0 +#define DC_CMD_WIN_T_STATE_CONTROL_0_WORD_COUNT 0x1 +#define DC_CMD_WIN_T_STATE_CONTROL_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_CMD_WIN_T_STATE_CONTROL_0_RESET_MASK _MK_MASK_CONST(0x101) +#define DC_CMD_WIN_T_STATE_CONTROL_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_CMD_WIN_T_STATE_CONTROL_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_CMD_WIN_T_STATE_CONTROL_0_READ_MASK _MK_MASK_CONST(0x101) +#define DC_CMD_WIN_T_STATE_CONTROL_0_WRITE_MASK _MK_MASK_CONST(0x101) +#define DC_CMD_WIN_T_STATE_CONTROL_0_WIN_T_ACT_REQ_SHIFT _MK_SHIFT_CONST(0) +#define DC_CMD_WIN_T_STATE_CONTROL_0_WIN_T_ACT_REQ_FIELD _MK_FIELD_CONST(0x1, DC_CMD_WIN_T_STATE_CONTROL_0_WIN_T_ACT_REQ_SHIFT) +#define DC_CMD_WIN_T_STATE_CONTROL_0_WIN_T_ACT_REQ_RANGE 0:0 +#define DC_CMD_WIN_T_STATE_CONTROL_0_WIN_T_ACT_REQ_WOFFSET 0x0 +#define DC_CMD_WIN_T_STATE_CONTROL_0_WIN_T_ACT_REQ_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_WIN_T_STATE_CONTROL_0_WIN_T_ACT_REQ_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_CMD_WIN_T_STATE_CONTROL_0_WIN_T_ACT_REQ_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_WIN_T_STATE_CONTROL_0_WIN_T_ACT_REQ_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_CMD_WIN_T_STATE_CONTROL_0_WIN_T_ACT_REQ_DISABLE _MK_ENUM_CONST(0) +#define DC_CMD_WIN_T_STATE_CONTROL_0_WIN_T_ACT_REQ_ENABLE _MK_ENUM_CONST(1) + +#define DC_CMD_WIN_T_STATE_CONTROL_0_WIN_T_UPDATE_SHIFT _MK_SHIFT_CONST(8) +#define DC_CMD_WIN_T_STATE_CONTROL_0_WIN_T_UPDATE_FIELD _MK_FIELD_CONST(0x1, DC_CMD_WIN_T_STATE_CONTROL_0_WIN_T_UPDATE_SHIFT) +#define DC_CMD_WIN_T_STATE_CONTROL_0_WIN_T_UPDATE_RANGE 8:8 +#define DC_CMD_WIN_T_STATE_CONTROL_0_WIN_T_UPDATE_WOFFSET 0x0 +#define DC_CMD_WIN_T_STATE_CONTROL_0_WIN_T_UPDATE_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_WIN_T_STATE_CONTROL_0_WIN_T_UPDATE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_CMD_WIN_T_STATE_CONTROL_0_WIN_T_UPDATE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_WIN_T_STATE_CONTROL_0_WIN_T_UPDATE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_CMD_WIN_T_STATE_CONTROL_0_WIN_T_UPDATE_DISABLE _MK_ENUM_CONST(0) +#define DC_CMD_WIN_T_STATE_CONTROL_0_WIN_T_UPDATE_ENABLE _MK_ENUM_CONST(1) + + +// Register DC_CMD_SECURE_CONTROL_0 +#define DC_CMD_SECURE_CONTROL_0 _MK_ADDR_CONST(0x45) +#define DC_CMD_SECURE_CONTROL_0_SECURE 0x0 +#define DC_CMD_SECURE_CONTROL_0_WORD_COUNT 0x1 +#define DC_CMD_SECURE_CONTROL_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_CMD_SECURE_CONTROL_0_RESET_MASK _MK_MASK_CONST(0x3f07) +#define DC_CMD_SECURE_CONTROL_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_CMD_SECURE_CONTROL_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_CMD_SECURE_CONTROL_0_READ_MASK _MK_MASK_CONST(0x3f07) +#define DC_CMD_SECURE_CONTROL_0_WRITE_MASK _MK_MASK_CONST(0x3f07) +#define DC_CMD_SECURE_CONTROL_0_SECURE_ENABLE_SHIFT _MK_SHIFT_CONST(0) +#define DC_CMD_SECURE_CONTROL_0_SECURE_ENABLE_FIELD _MK_FIELD_CONST(0x1, DC_CMD_SECURE_CONTROL_0_SECURE_ENABLE_SHIFT) +#define DC_CMD_SECURE_CONTROL_0_SECURE_ENABLE_RANGE 0:0 +#define DC_CMD_SECURE_CONTROL_0_SECURE_ENABLE_WOFFSET 0x0 +#define DC_CMD_SECURE_CONTROL_0_SECURE_ENABLE_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_SECURE_CONTROL_0_SECURE_ENABLE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_CMD_SECURE_CONTROL_0_SECURE_ENABLE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_SECURE_CONTROL_0_SECURE_ENABLE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_CMD_SECURE_CONTROL_0_SECURE_ENABLE_INIT_ENUM DISABLE +#define DC_CMD_SECURE_CONTROL_0_SECURE_ENABLE_DISABLE _MK_ENUM_CONST(0) +#define DC_CMD_SECURE_CONTROL_0_SECURE_ENABLE_ENABLE _MK_ENUM_CONST(1) + +#define DC_CMD_SECURE_CONTROL_0_SECURE_CMU_PROTECT_SHIFT _MK_SHIFT_CONST(1) +#define DC_CMD_SECURE_CONTROL_0_SECURE_CMU_PROTECT_FIELD _MK_FIELD_CONST(0x1, DC_CMD_SECURE_CONTROL_0_SECURE_CMU_PROTECT_SHIFT) +#define DC_CMD_SECURE_CONTROL_0_SECURE_CMU_PROTECT_RANGE 1:1 +#define DC_CMD_SECURE_CONTROL_0_SECURE_CMU_PROTECT_WOFFSET 0x0 +#define DC_CMD_SECURE_CONTROL_0_SECURE_CMU_PROTECT_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_SECURE_CONTROL_0_SECURE_CMU_PROTECT_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_CMD_SECURE_CONTROL_0_SECURE_CMU_PROTECT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_SECURE_CONTROL_0_SECURE_CMU_PROTECT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_CMD_SECURE_CONTROL_0_SECURE_CMU_PROTECT_INIT_ENUM DISABLE +#define DC_CMD_SECURE_CONTROL_0_SECURE_CMU_PROTECT_DISABLE _MK_ENUM_CONST(0) +#define DC_CMD_SECURE_CONTROL_0_SECURE_CMU_PROTECT_ENABLE _MK_ENUM_CONST(1) + +#define DC_CMD_SECURE_CONTROL_0_SECURE_CRC_PROTECT_SHIFT _MK_SHIFT_CONST(2) +#define DC_CMD_SECURE_CONTROL_0_SECURE_CRC_PROTECT_FIELD _MK_FIELD_CONST(0x1, DC_CMD_SECURE_CONTROL_0_SECURE_CRC_PROTECT_SHIFT) +#define DC_CMD_SECURE_CONTROL_0_SECURE_CRC_PROTECT_RANGE 2:2 +#define DC_CMD_SECURE_CONTROL_0_SECURE_CRC_PROTECT_WOFFSET 0x0 +#define DC_CMD_SECURE_CONTROL_0_SECURE_CRC_PROTECT_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_SECURE_CONTROL_0_SECURE_CRC_PROTECT_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_CMD_SECURE_CONTROL_0_SECURE_CRC_PROTECT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_SECURE_CONTROL_0_SECURE_CRC_PROTECT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_CMD_SECURE_CONTROL_0_SECURE_CRC_PROTECT_INIT_ENUM DISABLE +#define DC_CMD_SECURE_CONTROL_0_SECURE_CRC_PROTECT_DISABLE _MK_ENUM_CONST(0) +#define DC_CMD_SECURE_CONTROL_0_SECURE_CRC_PROTECT_ENABLE _MK_ENUM_CONST(1) + +#define DC_CMD_SECURE_CONTROL_0_SECURE_WRITE_MUX_SHIFT _MK_SHIFT_CONST(8) +#define DC_CMD_SECURE_CONTROL_0_SECURE_WRITE_MUX_FIELD _MK_FIELD_CONST(0x1, DC_CMD_SECURE_CONTROL_0_SECURE_WRITE_MUX_SHIFT) +#define DC_CMD_SECURE_CONTROL_0_SECURE_WRITE_MUX_RANGE 8:8 +#define DC_CMD_SECURE_CONTROL_0_SECURE_WRITE_MUX_WOFFSET 0x0 +#define DC_CMD_SECURE_CONTROL_0_SECURE_WRITE_MUX_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_SECURE_CONTROL_0_SECURE_WRITE_MUX_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_CMD_SECURE_CONTROL_0_SECURE_WRITE_MUX_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_SECURE_CONTROL_0_SECURE_WRITE_MUX_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_CMD_SECURE_CONTROL_0_SECURE_WRITE_MUX_INIT_ENUM ASSEMBLY +#define DC_CMD_SECURE_CONTROL_0_SECURE_WRITE_MUX_ASSEMBLY _MK_ENUM_CONST(0) +#define DC_CMD_SECURE_CONTROL_0_SECURE_WRITE_MUX_ACTIVE _MK_ENUM_CONST(1) + +#define DC_CMD_SECURE_CONTROL_0_SECURE_READ_MUX_SHIFT _MK_SHIFT_CONST(9) +#define DC_CMD_SECURE_CONTROL_0_SECURE_READ_MUX_FIELD _MK_FIELD_CONST(0x1, DC_CMD_SECURE_CONTROL_0_SECURE_READ_MUX_SHIFT) +#define DC_CMD_SECURE_CONTROL_0_SECURE_READ_MUX_RANGE 9:9 +#define DC_CMD_SECURE_CONTROL_0_SECURE_READ_MUX_WOFFSET 0x0 +#define DC_CMD_SECURE_CONTROL_0_SECURE_READ_MUX_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_SECURE_CONTROL_0_SECURE_READ_MUX_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_CMD_SECURE_CONTROL_0_SECURE_READ_MUX_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_SECURE_CONTROL_0_SECURE_READ_MUX_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_CMD_SECURE_CONTROL_0_SECURE_READ_MUX_INIT_ENUM ASSEMBLY +#define DC_CMD_SECURE_CONTROL_0_SECURE_READ_MUX_ASSEMBLY _MK_ENUM_CONST(0) +#define DC_CMD_SECURE_CONTROL_0_SECURE_READ_MUX_ACTIVE _MK_ENUM_CONST(1) + +#define DC_CMD_SECURE_CONTROL_0_SECURE_HDMI_PROTECT_SHIFT _MK_SHIFT_CONST(10) +#define DC_CMD_SECURE_CONTROL_0_SECURE_HDMI_PROTECT_FIELD _MK_FIELD_CONST(0x1, DC_CMD_SECURE_CONTROL_0_SECURE_HDMI_PROTECT_SHIFT) +#define DC_CMD_SECURE_CONTROL_0_SECURE_HDMI_PROTECT_RANGE 10:10 +#define DC_CMD_SECURE_CONTROL_0_SECURE_HDMI_PROTECT_WOFFSET 0x0 +#define DC_CMD_SECURE_CONTROL_0_SECURE_HDMI_PROTECT_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_SECURE_CONTROL_0_SECURE_HDMI_PROTECT_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_CMD_SECURE_CONTROL_0_SECURE_HDMI_PROTECT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_SECURE_CONTROL_0_SECURE_HDMI_PROTECT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_CMD_SECURE_CONTROL_0_SECURE_HDMI_PROTECT_INIT_ENUM DISABLE +#define DC_CMD_SECURE_CONTROL_0_SECURE_HDMI_PROTECT_DISABLE _MK_ENUM_CONST(0) +#define DC_CMD_SECURE_CONTROL_0_SECURE_HDMI_PROTECT_ENABLE _MK_ENUM_CONST(1) + +#define DC_CMD_SECURE_CONTROL_0_SECURE_DSIA_PROTECT_SHIFT _MK_SHIFT_CONST(11) +#define DC_CMD_SECURE_CONTROL_0_SECURE_DSIA_PROTECT_FIELD _MK_FIELD_CONST(0x1, DC_CMD_SECURE_CONTROL_0_SECURE_DSIA_PROTECT_SHIFT) +#define DC_CMD_SECURE_CONTROL_0_SECURE_DSIA_PROTECT_RANGE 11:11 +#define DC_CMD_SECURE_CONTROL_0_SECURE_DSIA_PROTECT_WOFFSET 0x0 +#define DC_CMD_SECURE_CONTROL_0_SECURE_DSIA_PROTECT_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_SECURE_CONTROL_0_SECURE_DSIA_PROTECT_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_CMD_SECURE_CONTROL_0_SECURE_DSIA_PROTECT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_SECURE_CONTROL_0_SECURE_DSIA_PROTECT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_CMD_SECURE_CONTROL_0_SECURE_DSIA_PROTECT_INIT_ENUM DISABLE +#define DC_CMD_SECURE_CONTROL_0_SECURE_DSIA_PROTECT_DISABLE _MK_ENUM_CONST(0) +#define DC_CMD_SECURE_CONTROL_0_SECURE_DSIA_PROTECT_ENABLE _MK_ENUM_CONST(1) + +#define DC_CMD_SECURE_CONTROL_0_SECURE_DSIB_PROTECT_SHIFT _MK_SHIFT_CONST(12) +#define DC_CMD_SECURE_CONTROL_0_SECURE_DSIB_PROTECT_FIELD _MK_FIELD_CONST(0x1, DC_CMD_SECURE_CONTROL_0_SECURE_DSIB_PROTECT_SHIFT) +#define DC_CMD_SECURE_CONTROL_0_SECURE_DSIB_PROTECT_RANGE 12:12 +#define DC_CMD_SECURE_CONTROL_0_SECURE_DSIB_PROTECT_WOFFSET 0x0 +#define DC_CMD_SECURE_CONTROL_0_SECURE_DSIB_PROTECT_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_SECURE_CONTROL_0_SECURE_DSIB_PROTECT_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_CMD_SECURE_CONTROL_0_SECURE_DSIB_PROTECT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_SECURE_CONTROL_0_SECURE_DSIB_PROTECT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_CMD_SECURE_CONTROL_0_SECURE_DSIB_PROTECT_INIT_ENUM DISABLE +#define DC_CMD_SECURE_CONTROL_0_SECURE_DSIB_PROTECT_DISABLE _MK_ENUM_CONST(0) +#define DC_CMD_SECURE_CONTROL_0_SECURE_DSIB_PROTECT_ENABLE _MK_ENUM_CONST(1) + +#define DC_CMD_SECURE_CONTROL_0_SECURE_SOR_PROTECT_SHIFT _MK_SHIFT_CONST(13) +#define DC_CMD_SECURE_CONTROL_0_SECURE_SOR_PROTECT_FIELD _MK_FIELD_CONST(0x1, DC_CMD_SECURE_CONTROL_0_SECURE_SOR_PROTECT_SHIFT) +#define DC_CMD_SECURE_CONTROL_0_SECURE_SOR_PROTECT_RANGE 13:13 +#define DC_CMD_SECURE_CONTROL_0_SECURE_SOR_PROTECT_WOFFSET 0x0 +#define DC_CMD_SECURE_CONTROL_0_SECURE_SOR_PROTECT_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_SECURE_CONTROL_0_SECURE_SOR_PROTECT_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_CMD_SECURE_CONTROL_0_SECURE_SOR_PROTECT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_SECURE_CONTROL_0_SECURE_SOR_PROTECT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_CMD_SECURE_CONTROL_0_SECURE_SOR_PROTECT_INIT_ENUM DISABLE +#define DC_CMD_SECURE_CONTROL_0_SECURE_SOR_PROTECT_DISABLE _MK_ENUM_CONST(0) +#define DC_CMD_SECURE_CONTROL_0_SECURE_SOR_PROTECT_ENABLE _MK_ENUM_CONST(1) + + +// Reserved address 70 [0x46] + +// Reserved address 71 [0x47] + +// Reserved address 72 [0x48] + +// Reserved address 73 [0x49] + +// Reserved address 74 [0x4a] + +// Reserved address 75 [0x4b] +#define NV_DISPLAY_WIN_D_INCR_SYNCPT_NB_CONDS 4 + +// Register DC_CMD_WIN_D_INCR_SYNCPT_0 +#define DC_CMD_WIN_D_INCR_SYNCPT_0 _MK_ADDR_CONST(0x4c) +#define DC_CMD_WIN_D_INCR_SYNCPT_0_SECURE 0x0 +#define DC_CMD_WIN_D_INCR_SYNCPT_0_WORD_COUNT 0x1 +#define DC_CMD_WIN_D_INCR_SYNCPT_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_CMD_WIN_D_INCR_SYNCPT_0_RESET_MASK _MK_MASK_CONST(0xffff) +#define DC_CMD_WIN_D_INCR_SYNCPT_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_CMD_WIN_D_INCR_SYNCPT_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_CMD_WIN_D_INCR_SYNCPT_0_READ_MASK _MK_MASK_CONST(0xffff) +#define DC_CMD_WIN_D_INCR_SYNCPT_0_WRITE_MASK _MK_MASK_CONST(0xffff) +#define DC_CMD_WIN_D_INCR_SYNCPT_0_WIN_D_COND_SHIFT _MK_SHIFT_CONST(8) +#define DC_CMD_WIN_D_INCR_SYNCPT_0_WIN_D_COND_FIELD _MK_FIELD_CONST(0xff, DC_CMD_WIN_D_INCR_SYNCPT_0_WIN_D_COND_SHIFT) +#define DC_CMD_WIN_D_INCR_SYNCPT_0_WIN_D_COND_RANGE 15:8 +#define DC_CMD_WIN_D_INCR_SYNCPT_0_WIN_D_COND_WOFFSET 0x0 +#define DC_CMD_WIN_D_INCR_SYNCPT_0_WIN_D_COND_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_WIN_D_INCR_SYNCPT_0_WIN_D_COND_DEFAULT_MASK _MK_MASK_CONST(0xff) +#define DC_CMD_WIN_D_INCR_SYNCPT_0_WIN_D_COND_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_WIN_D_INCR_SYNCPT_0_WIN_D_COND_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_CMD_WIN_D_INCR_SYNCPT_0_WIN_D_COND_IMMEDIATE _MK_ENUM_CONST(0) +#define DC_CMD_WIN_D_INCR_SYNCPT_0_WIN_D_COND_OP_DONE _MK_ENUM_CONST(1) +#define DC_CMD_WIN_D_INCR_SYNCPT_0_WIN_D_COND_RD_DONE _MK_ENUM_CONST(2) +#define DC_CMD_WIN_D_INCR_SYNCPT_0_WIN_D_COND_REG_WR_SAFE _MK_ENUM_CONST(3) +#define DC_CMD_WIN_D_INCR_SYNCPT_0_WIN_D_COND_COND_4 _MK_ENUM_CONST(4) +#define DC_CMD_WIN_D_INCR_SYNCPT_0_WIN_D_COND_COND_5 _MK_ENUM_CONST(5) +#define DC_CMD_WIN_D_INCR_SYNCPT_0_WIN_D_COND_COND_6 _MK_ENUM_CONST(6) +#define DC_CMD_WIN_D_INCR_SYNCPT_0_WIN_D_COND_COND_7 _MK_ENUM_CONST(7) +#define DC_CMD_WIN_D_INCR_SYNCPT_0_WIN_D_COND_COND_8 _MK_ENUM_CONST(8) +#define DC_CMD_WIN_D_INCR_SYNCPT_0_WIN_D_COND_COND_9 _MK_ENUM_CONST(9) +#define DC_CMD_WIN_D_INCR_SYNCPT_0_WIN_D_COND_COND_10 _MK_ENUM_CONST(10) +#define DC_CMD_WIN_D_INCR_SYNCPT_0_WIN_D_COND_COND_11 _MK_ENUM_CONST(11) +#define DC_CMD_WIN_D_INCR_SYNCPT_0_WIN_D_COND_COND_12 _MK_ENUM_CONST(12) +#define DC_CMD_WIN_D_INCR_SYNCPT_0_WIN_D_COND_COND_13 _MK_ENUM_CONST(13) +#define DC_CMD_WIN_D_INCR_SYNCPT_0_WIN_D_COND_COND_14 _MK_ENUM_CONST(14) +#define DC_CMD_WIN_D_INCR_SYNCPT_0_WIN_D_COND_COND_15 _MK_ENUM_CONST(15) +#define DC_CMD_WIN_D_INCR_SYNCPT_0_WIN_D_COND_COND_16 _MK_ENUM_CONST(16) +#define DC_CMD_WIN_D_INCR_SYNCPT_0_WIN_D_COND_COND_17 _MK_ENUM_CONST(17) +#define DC_CMD_WIN_D_INCR_SYNCPT_0_WIN_D_COND_COND_18 _MK_ENUM_CONST(18) +#define DC_CMD_WIN_D_INCR_SYNCPT_0_WIN_D_COND_COND_19 _MK_ENUM_CONST(19) +#define DC_CMD_WIN_D_INCR_SYNCPT_0_WIN_D_COND_COND_20 _MK_ENUM_CONST(20) +#define DC_CMD_WIN_D_INCR_SYNCPT_0_WIN_D_COND_COND_21 _MK_ENUM_CONST(21) +#define DC_CMD_WIN_D_INCR_SYNCPT_0_WIN_D_COND_COND_22 _MK_ENUM_CONST(22) +#define DC_CMD_WIN_D_INCR_SYNCPT_0_WIN_D_COND_COND_23 _MK_ENUM_CONST(23) +#define DC_CMD_WIN_D_INCR_SYNCPT_0_WIN_D_COND_COND_24 _MK_ENUM_CONST(24) +#define DC_CMD_WIN_D_INCR_SYNCPT_0_WIN_D_COND_COND_25 _MK_ENUM_CONST(25) +#define DC_CMD_WIN_D_INCR_SYNCPT_0_WIN_D_COND_COND_26 _MK_ENUM_CONST(26) +#define DC_CMD_WIN_D_INCR_SYNCPT_0_WIN_D_COND_COND_27 _MK_ENUM_CONST(27) +#define DC_CMD_WIN_D_INCR_SYNCPT_0_WIN_D_COND_COND_28 _MK_ENUM_CONST(28) +#define DC_CMD_WIN_D_INCR_SYNCPT_0_WIN_D_COND_COND_29 _MK_ENUM_CONST(29) +#define DC_CMD_WIN_D_INCR_SYNCPT_0_WIN_D_COND_COND_30 _MK_ENUM_CONST(30) +#define DC_CMD_WIN_D_INCR_SYNCPT_0_WIN_D_COND_COND_31 _MK_ENUM_CONST(31) + +#define DC_CMD_WIN_D_INCR_SYNCPT_0_WIN_D_INDX_SHIFT _MK_SHIFT_CONST(0) +#define DC_CMD_WIN_D_INCR_SYNCPT_0_WIN_D_INDX_FIELD _MK_FIELD_CONST(0xff, DC_CMD_WIN_D_INCR_SYNCPT_0_WIN_D_INDX_SHIFT) +#define DC_CMD_WIN_D_INCR_SYNCPT_0_WIN_D_INDX_RANGE 7:0 +#define DC_CMD_WIN_D_INCR_SYNCPT_0_WIN_D_INDX_WOFFSET 0x0 +#define DC_CMD_WIN_D_INCR_SYNCPT_0_WIN_D_INDX_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_WIN_D_INCR_SYNCPT_0_WIN_D_INDX_DEFAULT_MASK _MK_MASK_CONST(0xff) +#define DC_CMD_WIN_D_INCR_SYNCPT_0_WIN_D_INDX_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_WIN_D_INCR_SYNCPT_0_WIN_D_INDX_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_CMD_WIN_D_INCR_SYNCPT_CNTRL_0 +#define DC_CMD_WIN_D_INCR_SYNCPT_CNTRL_0 _MK_ADDR_CONST(0x4d) +#define DC_CMD_WIN_D_INCR_SYNCPT_CNTRL_0_SECURE 0x0 +#define DC_CMD_WIN_D_INCR_SYNCPT_CNTRL_0_WORD_COUNT 0x1 +#define DC_CMD_WIN_D_INCR_SYNCPT_CNTRL_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_CMD_WIN_D_INCR_SYNCPT_CNTRL_0_RESET_MASK _MK_MASK_CONST(0x101) +#define DC_CMD_WIN_D_INCR_SYNCPT_CNTRL_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_CMD_WIN_D_INCR_SYNCPT_CNTRL_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_CMD_WIN_D_INCR_SYNCPT_CNTRL_0_READ_MASK _MK_MASK_CONST(0x101) +#define DC_CMD_WIN_D_INCR_SYNCPT_CNTRL_0_WRITE_MASK _MK_MASK_CONST(0x101) +#define DC_CMD_WIN_D_INCR_SYNCPT_CNTRL_0_WIN_D_INCR_SYNCPT_NO_STALL_SHIFT _MK_SHIFT_CONST(8) +#define DC_CMD_WIN_D_INCR_SYNCPT_CNTRL_0_WIN_D_INCR_SYNCPT_NO_STALL_FIELD _MK_FIELD_CONST(0x1, DC_CMD_WIN_D_INCR_SYNCPT_CNTRL_0_WIN_D_INCR_SYNCPT_NO_STALL_SHIFT) +#define DC_CMD_WIN_D_INCR_SYNCPT_CNTRL_0_WIN_D_INCR_SYNCPT_NO_STALL_RANGE 8:8 +#define DC_CMD_WIN_D_INCR_SYNCPT_CNTRL_0_WIN_D_INCR_SYNCPT_NO_STALL_WOFFSET 0x0 +#define DC_CMD_WIN_D_INCR_SYNCPT_CNTRL_0_WIN_D_INCR_SYNCPT_NO_STALL_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_WIN_D_INCR_SYNCPT_CNTRL_0_WIN_D_INCR_SYNCPT_NO_STALL_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_CMD_WIN_D_INCR_SYNCPT_CNTRL_0_WIN_D_INCR_SYNCPT_NO_STALL_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_WIN_D_INCR_SYNCPT_CNTRL_0_WIN_D_INCR_SYNCPT_NO_STALL_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_CMD_WIN_D_INCR_SYNCPT_CNTRL_0_WIN_D_INCR_SYNCPT_SOFT_RESET_SHIFT _MK_SHIFT_CONST(0) +#define DC_CMD_WIN_D_INCR_SYNCPT_CNTRL_0_WIN_D_INCR_SYNCPT_SOFT_RESET_FIELD _MK_FIELD_CONST(0x1, DC_CMD_WIN_D_INCR_SYNCPT_CNTRL_0_WIN_D_INCR_SYNCPT_SOFT_RESET_SHIFT) +#define DC_CMD_WIN_D_INCR_SYNCPT_CNTRL_0_WIN_D_INCR_SYNCPT_SOFT_RESET_RANGE 0:0 +#define DC_CMD_WIN_D_INCR_SYNCPT_CNTRL_0_WIN_D_INCR_SYNCPT_SOFT_RESET_WOFFSET 0x0 +#define DC_CMD_WIN_D_INCR_SYNCPT_CNTRL_0_WIN_D_INCR_SYNCPT_SOFT_RESET_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_WIN_D_INCR_SYNCPT_CNTRL_0_WIN_D_INCR_SYNCPT_SOFT_RESET_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_CMD_WIN_D_INCR_SYNCPT_CNTRL_0_WIN_D_INCR_SYNCPT_SOFT_RESET_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_WIN_D_INCR_SYNCPT_CNTRL_0_WIN_D_INCR_SYNCPT_SOFT_RESET_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_CMD_WIN_D_INCR_SYNCPT_ERROR_0 +#define DC_CMD_WIN_D_INCR_SYNCPT_ERROR_0 _MK_ADDR_CONST(0x4e) +#define DC_CMD_WIN_D_INCR_SYNCPT_ERROR_0_SECURE 0x0 +#define DC_CMD_WIN_D_INCR_SYNCPT_ERROR_0_WORD_COUNT 0x1 +#define DC_CMD_WIN_D_INCR_SYNCPT_ERROR_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_CMD_WIN_D_INCR_SYNCPT_ERROR_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_CMD_WIN_D_INCR_SYNCPT_ERROR_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_CMD_WIN_D_INCR_SYNCPT_ERROR_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_CMD_WIN_D_INCR_SYNCPT_ERROR_0_READ_MASK _MK_MASK_CONST(0xffffffff) +#define DC_CMD_WIN_D_INCR_SYNCPT_ERROR_0_WRITE_MASK _MK_MASK_CONST(0xffffffff) +#define DC_CMD_WIN_D_INCR_SYNCPT_ERROR_0_WIN_D_COND_STATUS_SHIFT _MK_SHIFT_CONST(0) +#define DC_CMD_WIN_D_INCR_SYNCPT_ERROR_0_WIN_D_COND_STATUS_FIELD _MK_FIELD_CONST(0xffffffff, DC_CMD_WIN_D_INCR_SYNCPT_ERROR_0_WIN_D_COND_STATUS_SHIFT) +#define DC_CMD_WIN_D_INCR_SYNCPT_ERROR_0_WIN_D_COND_STATUS_RANGE 31:0 +#define DC_CMD_WIN_D_INCR_SYNCPT_ERROR_0_WIN_D_COND_STATUS_WOFFSET 0x0 +#define DC_CMD_WIN_D_INCR_SYNCPT_ERROR_0_WIN_D_COND_STATUS_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_WIN_D_INCR_SYNCPT_ERROR_0_WIN_D_COND_STATUS_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_CMD_WIN_D_INCR_SYNCPT_ERROR_0_WIN_D_COND_STATUS_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_CMD_WIN_D_INCR_SYNCPT_ERROR_0_WIN_D_COND_STATUS_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Reserved address 79 [0x4f] + +// Reserved address 80 [0x50] + +// Reserved address 81 [0x51] + +// Reserved address 82 [0x52] + +// Reserved address 83 [0x53] + +// Reserved address 84 [0x54] + +// Reserved address 85 [0x55] + +// Reserved address 86 [0x56] + +// Reserved address 87 [0x57] + +// Reserved address 88 [0x58] + +// Reserved address 89 [0x59] + +// Reserved address 90 [0x5a] + +// Reserved address 91 [0x5b] + +// Register DC_COM_CRC_CONTROL_0 +#define DC_COM_CRC_CONTROL_0 _MK_ADDR_CONST(0x300) +#define DC_COM_CRC_CONTROL_0_SECURE 0x0 +#define DC_COM_CRC_CONTROL_0_WORD_COUNT 0x1 +#define DC_COM_CRC_CONTROL_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_COM_CRC_CONTROL_0_RESET_MASK _MK_MASK_CONST(0xf) +#define DC_COM_CRC_CONTROL_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_COM_CRC_CONTROL_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_CRC_CONTROL_0_READ_MASK _MK_MASK_CONST(0xf) +#define DC_COM_CRC_CONTROL_0_WRITE_MASK _MK_MASK_CONST(0xf) +#define DC_COM_CRC_CONTROL_0_CRC_ENABLE_SHIFT _MK_SHIFT_CONST(0) +#define DC_COM_CRC_CONTROL_0_CRC_ENABLE_FIELD _MK_FIELD_CONST(0x1, DC_COM_CRC_CONTROL_0_CRC_ENABLE_SHIFT) +#define DC_COM_CRC_CONTROL_0_CRC_ENABLE_RANGE 0:0 +#define DC_COM_CRC_CONTROL_0_CRC_ENABLE_WOFFSET 0x0 +#define DC_COM_CRC_CONTROL_0_CRC_ENABLE_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_CRC_CONTROL_0_CRC_ENABLE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_COM_CRC_CONTROL_0_CRC_ENABLE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_CRC_CONTROL_0_CRC_ENABLE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_CRC_CONTROL_0_CRC_ENABLE_DISABLE _MK_ENUM_CONST(0) +#define DC_COM_CRC_CONTROL_0_CRC_ENABLE_ENABLE _MK_ENUM_CONST(1) + +#define DC_COM_CRC_CONTROL_0_CRC_WAIT_SHIFT _MK_SHIFT_CONST(1) +#define DC_COM_CRC_CONTROL_0_CRC_WAIT_FIELD _MK_FIELD_CONST(0x1, DC_COM_CRC_CONTROL_0_CRC_WAIT_SHIFT) +#define DC_COM_CRC_CONTROL_0_CRC_WAIT_RANGE 1:1 +#define DC_COM_CRC_CONTROL_0_CRC_WAIT_WOFFSET 0x0 +#define DC_COM_CRC_CONTROL_0_CRC_WAIT_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_CRC_CONTROL_0_CRC_WAIT_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_COM_CRC_CONTROL_0_CRC_WAIT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_CRC_CONTROL_0_CRC_WAIT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_COM_CRC_CONTROL_0_CRC_INPUT_DATA_SHIFT _MK_SHIFT_CONST(2) +#define DC_COM_CRC_CONTROL_0_CRC_INPUT_DATA_FIELD _MK_FIELD_CONST(0x1, DC_COM_CRC_CONTROL_0_CRC_INPUT_DATA_SHIFT) +#define DC_COM_CRC_CONTROL_0_CRC_INPUT_DATA_RANGE 2:2 +#define DC_COM_CRC_CONTROL_0_CRC_INPUT_DATA_WOFFSET 0x0 +#define DC_COM_CRC_CONTROL_0_CRC_INPUT_DATA_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_CRC_CONTROL_0_CRC_INPUT_DATA_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_COM_CRC_CONTROL_0_CRC_INPUT_DATA_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_CRC_CONTROL_0_CRC_INPUT_DATA_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_CRC_CONTROL_0_CRC_INPUT_DATA_FULL_FRAME _MK_ENUM_CONST(0) +#define DC_COM_CRC_CONTROL_0_CRC_INPUT_DATA_ACTIVE_DATA _MK_ENUM_CONST(1) + +#define DC_COM_CRC_CONTROL_0_CRC_ALWAYS_SHIFT _MK_SHIFT_CONST(3) +#define DC_COM_CRC_CONTROL_0_CRC_ALWAYS_FIELD _MK_FIELD_CONST(0x1, DC_COM_CRC_CONTROL_0_CRC_ALWAYS_SHIFT) +#define DC_COM_CRC_CONTROL_0_CRC_ALWAYS_RANGE 3:3 +#define DC_COM_CRC_CONTROL_0_CRC_ALWAYS_WOFFSET 0x0 +#define DC_COM_CRC_CONTROL_0_CRC_ALWAYS_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_CRC_CONTROL_0_CRC_ALWAYS_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_COM_CRC_CONTROL_0_CRC_ALWAYS_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_CRC_CONTROL_0_CRC_ALWAYS_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_CRC_CONTROL_0_CRC_ALWAYS_DISABLE _MK_ENUM_CONST(0) +#define DC_COM_CRC_CONTROL_0_CRC_ALWAYS_ENABLE _MK_ENUM_CONST(1) + + +// Register DC_COM_CRC_CHECKSUM_0 +#define DC_COM_CRC_CHECKSUM_0 _MK_ADDR_CONST(0x301) +#define DC_COM_CRC_CHECKSUM_0_SECURE 0x0 +#define DC_COM_CRC_CHECKSUM_0_WORD_COUNT 0x1 +#define DC_COM_CRC_CHECKSUM_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_COM_CRC_CHECKSUM_0_RESET_MASK _MK_MASK_CONST(0xffffffff) +#define DC_COM_CRC_CHECKSUM_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_COM_CRC_CHECKSUM_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_CRC_CHECKSUM_0_READ_MASK _MK_MASK_CONST(0xffffffff) +#define DC_COM_CRC_CHECKSUM_0_WRITE_MASK _MK_MASK_CONST(0x0) +#define DC_COM_CRC_CHECKSUM_0_CRC_CHECKSUM_SHIFT _MK_SHIFT_CONST(0) +#define DC_COM_CRC_CHECKSUM_0_CRC_CHECKSUM_FIELD _MK_FIELD_CONST(0xffffffff, DC_COM_CRC_CHECKSUM_0_CRC_CHECKSUM_SHIFT) +#define DC_COM_CRC_CHECKSUM_0_CRC_CHECKSUM_RANGE 31:0 +#define DC_COM_CRC_CHECKSUM_0_CRC_CHECKSUM_WOFFSET 0x0 +#define DC_COM_CRC_CHECKSUM_0_CRC_CHECKSUM_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_CRC_CHECKSUM_0_CRC_CHECKSUM_DEFAULT_MASK _MK_MASK_CONST(0xffffffff) +#define DC_COM_CRC_CHECKSUM_0_CRC_CHECKSUM_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_CRC_CHECKSUM_0_CRC_CHECKSUM_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_COM_PIN_OUTPUT_ENABLE0_0 +#define DC_COM_PIN_OUTPUT_ENABLE0_0 _MK_ADDR_CONST(0x302) +#define DC_COM_PIN_OUTPUT_ENABLE0_0_SECURE 0x0 +#define DC_COM_PIN_OUTPUT_ENABLE0_0_WORD_COUNT 0x1 +#define DC_COM_PIN_OUTPUT_ENABLE0_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_ENABLE0_0_RESET_MASK _MK_MASK_CONST(0x55555555) +#define DC_COM_PIN_OUTPUT_ENABLE0_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_ENABLE0_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_ENABLE0_0_READ_MASK _MK_MASK_CONST(0x55555555) +#define DC_COM_PIN_OUTPUT_ENABLE0_0_WRITE_MASK _MK_MASK_CONST(0x55555555) +#define DC_COM_PIN_OUTPUT_ENABLE0_0_LD0_OUTPUT_ENABLE_SHIFT _MK_SHIFT_CONST(0) +#define DC_COM_PIN_OUTPUT_ENABLE0_0_LD0_OUTPUT_ENABLE_FIELD _MK_FIELD_CONST(0x1, DC_COM_PIN_OUTPUT_ENABLE0_0_LD0_OUTPUT_ENABLE_SHIFT) +#define DC_COM_PIN_OUTPUT_ENABLE0_0_LD0_OUTPUT_ENABLE_RANGE 0:0 +#define DC_COM_PIN_OUTPUT_ENABLE0_0_LD0_OUTPUT_ENABLE_WOFFSET 0x0 +#define DC_COM_PIN_OUTPUT_ENABLE0_0_LD0_OUTPUT_ENABLE_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_ENABLE0_0_LD0_OUTPUT_ENABLE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_COM_PIN_OUTPUT_ENABLE0_0_LD0_OUTPUT_ENABLE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_ENABLE0_0_LD0_OUTPUT_ENABLE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_ENABLE0_0_LD0_OUTPUT_ENABLE_ENABLE _MK_ENUM_CONST(0) +#define DC_COM_PIN_OUTPUT_ENABLE0_0_LD0_OUTPUT_ENABLE_DISABLE _MK_ENUM_CONST(1) + +#define DC_COM_PIN_OUTPUT_ENABLE0_0_LD1_OUTPUT_ENABLE_SHIFT _MK_SHIFT_CONST(2) +#define DC_COM_PIN_OUTPUT_ENABLE0_0_LD1_OUTPUT_ENABLE_FIELD _MK_FIELD_CONST(0x1, DC_COM_PIN_OUTPUT_ENABLE0_0_LD1_OUTPUT_ENABLE_SHIFT) +#define DC_COM_PIN_OUTPUT_ENABLE0_0_LD1_OUTPUT_ENABLE_RANGE 2:2 +#define DC_COM_PIN_OUTPUT_ENABLE0_0_LD1_OUTPUT_ENABLE_WOFFSET 0x0 +#define DC_COM_PIN_OUTPUT_ENABLE0_0_LD1_OUTPUT_ENABLE_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_ENABLE0_0_LD1_OUTPUT_ENABLE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_COM_PIN_OUTPUT_ENABLE0_0_LD1_OUTPUT_ENABLE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_ENABLE0_0_LD1_OUTPUT_ENABLE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_ENABLE0_0_LD1_OUTPUT_ENABLE_ENABLE _MK_ENUM_CONST(0) +#define DC_COM_PIN_OUTPUT_ENABLE0_0_LD1_OUTPUT_ENABLE_DISABLE _MK_ENUM_CONST(1) + +#define DC_COM_PIN_OUTPUT_ENABLE0_0_LD2_OUTPUT_ENABLE_SHIFT _MK_SHIFT_CONST(4) +#define DC_COM_PIN_OUTPUT_ENABLE0_0_LD2_OUTPUT_ENABLE_FIELD _MK_FIELD_CONST(0x1, DC_COM_PIN_OUTPUT_ENABLE0_0_LD2_OUTPUT_ENABLE_SHIFT) +#define DC_COM_PIN_OUTPUT_ENABLE0_0_LD2_OUTPUT_ENABLE_RANGE 4:4 +#define DC_COM_PIN_OUTPUT_ENABLE0_0_LD2_OUTPUT_ENABLE_WOFFSET 0x0 +#define DC_COM_PIN_OUTPUT_ENABLE0_0_LD2_OUTPUT_ENABLE_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_ENABLE0_0_LD2_OUTPUT_ENABLE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_COM_PIN_OUTPUT_ENABLE0_0_LD2_OUTPUT_ENABLE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_ENABLE0_0_LD2_OUTPUT_ENABLE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_ENABLE0_0_LD2_OUTPUT_ENABLE_ENABLE _MK_ENUM_CONST(0) +#define DC_COM_PIN_OUTPUT_ENABLE0_0_LD2_OUTPUT_ENABLE_DISABLE _MK_ENUM_CONST(1) + +#define DC_COM_PIN_OUTPUT_ENABLE0_0_LD3_OUTPUT_ENABLE_SHIFT _MK_SHIFT_CONST(6) +#define DC_COM_PIN_OUTPUT_ENABLE0_0_LD3_OUTPUT_ENABLE_FIELD _MK_FIELD_CONST(0x1, DC_COM_PIN_OUTPUT_ENABLE0_0_LD3_OUTPUT_ENABLE_SHIFT) +#define DC_COM_PIN_OUTPUT_ENABLE0_0_LD3_OUTPUT_ENABLE_RANGE 6:6 +#define DC_COM_PIN_OUTPUT_ENABLE0_0_LD3_OUTPUT_ENABLE_WOFFSET 0x0 +#define DC_COM_PIN_OUTPUT_ENABLE0_0_LD3_OUTPUT_ENABLE_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_ENABLE0_0_LD3_OUTPUT_ENABLE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_COM_PIN_OUTPUT_ENABLE0_0_LD3_OUTPUT_ENABLE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_ENABLE0_0_LD3_OUTPUT_ENABLE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_ENABLE0_0_LD3_OUTPUT_ENABLE_ENABLE _MK_ENUM_CONST(0) +#define DC_COM_PIN_OUTPUT_ENABLE0_0_LD3_OUTPUT_ENABLE_DISABLE _MK_ENUM_CONST(1) + +#define DC_COM_PIN_OUTPUT_ENABLE0_0_LD4_OUTPUT_ENABLE_SHIFT _MK_SHIFT_CONST(8) +#define DC_COM_PIN_OUTPUT_ENABLE0_0_LD4_OUTPUT_ENABLE_FIELD _MK_FIELD_CONST(0x1, DC_COM_PIN_OUTPUT_ENABLE0_0_LD4_OUTPUT_ENABLE_SHIFT) +#define DC_COM_PIN_OUTPUT_ENABLE0_0_LD4_OUTPUT_ENABLE_RANGE 8:8 +#define DC_COM_PIN_OUTPUT_ENABLE0_0_LD4_OUTPUT_ENABLE_WOFFSET 0x0 +#define DC_COM_PIN_OUTPUT_ENABLE0_0_LD4_OUTPUT_ENABLE_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_ENABLE0_0_LD4_OUTPUT_ENABLE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_COM_PIN_OUTPUT_ENABLE0_0_LD4_OUTPUT_ENABLE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_ENABLE0_0_LD4_OUTPUT_ENABLE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_ENABLE0_0_LD4_OUTPUT_ENABLE_ENABLE _MK_ENUM_CONST(0) +#define DC_COM_PIN_OUTPUT_ENABLE0_0_LD4_OUTPUT_ENABLE_DISABLE _MK_ENUM_CONST(1) + +#define DC_COM_PIN_OUTPUT_ENABLE0_0_LD5_OUTPUT_ENABLE_SHIFT _MK_SHIFT_CONST(10) +#define DC_COM_PIN_OUTPUT_ENABLE0_0_LD5_OUTPUT_ENABLE_FIELD _MK_FIELD_CONST(0x1, DC_COM_PIN_OUTPUT_ENABLE0_0_LD5_OUTPUT_ENABLE_SHIFT) +#define DC_COM_PIN_OUTPUT_ENABLE0_0_LD5_OUTPUT_ENABLE_RANGE 10:10 +#define DC_COM_PIN_OUTPUT_ENABLE0_0_LD5_OUTPUT_ENABLE_WOFFSET 0x0 +#define DC_COM_PIN_OUTPUT_ENABLE0_0_LD5_OUTPUT_ENABLE_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_ENABLE0_0_LD5_OUTPUT_ENABLE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_COM_PIN_OUTPUT_ENABLE0_0_LD5_OUTPUT_ENABLE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_ENABLE0_0_LD5_OUTPUT_ENABLE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_ENABLE0_0_LD5_OUTPUT_ENABLE_ENABLE _MK_ENUM_CONST(0) +#define DC_COM_PIN_OUTPUT_ENABLE0_0_LD5_OUTPUT_ENABLE_DISABLE _MK_ENUM_CONST(1) + +#define DC_COM_PIN_OUTPUT_ENABLE0_0_LD6_OUTPUT_ENABLE_SHIFT _MK_SHIFT_CONST(12) +#define DC_COM_PIN_OUTPUT_ENABLE0_0_LD6_OUTPUT_ENABLE_FIELD _MK_FIELD_CONST(0x1, DC_COM_PIN_OUTPUT_ENABLE0_0_LD6_OUTPUT_ENABLE_SHIFT) +#define DC_COM_PIN_OUTPUT_ENABLE0_0_LD6_OUTPUT_ENABLE_RANGE 12:12 +#define DC_COM_PIN_OUTPUT_ENABLE0_0_LD6_OUTPUT_ENABLE_WOFFSET 0x0 +#define DC_COM_PIN_OUTPUT_ENABLE0_0_LD6_OUTPUT_ENABLE_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_ENABLE0_0_LD6_OUTPUT_ENABLE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_COM_PIN_OUTPUT_ENABLE0_0_LD6_OUTPUT_ENABLE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_ENABLE0_0_LD6_OUTPUT_ENABLE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_ENABLE0_0_LD6_OUTPUT_ENABLE_ENABLE _MK_ENUM_CONST(0) +#define DC_COM_PIN_OUTPUT_ENABLE0_0_LD6_OUTPUT_ENABLE_DISABLE _MK_ENUM_CONST(1) + +#define DC_COM_PIN_OUTPUT_ENABLE0_0_LD7_OUTPUT_ENABLE_SHIFT _MK_SHIFT_CONST(14) +#define DC_COM_PIN_OUTPUT_ENABLE0_0_LD7_OUTPUT_ENABLE_FIELD _MK_FIELD_CONST(0x1, DC_COM_PIN_OUTPUT_ENABLE0_0_LD7_OUTPUT_ENABLE_SHIFT) +#define DC_COM_PIN_OUTPUT_ENABLE0_0_LD7_OUTPUT_ENABLE_RANGE 14:14 +#define DC_COM_PIN_OUTPUT_ENABLE0_0_LD7_OUTPUT_ENABLE_WOFFSET 0x0 +#define DC_COM_PIN_OUTPUT_ENABLE0_0_LD7_OUTPUT_ENABLE_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_ENABLE0_0_LD7_OUTPUT_ENABLE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_COM_PIN_OUTPUT_ENABLE0_0_LD7_OUTPUT_ENABLE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_ENABLE0_0_LD7_OUTPUT_ENABLE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_ENABLE0_0_LD7_OUTPUT_ENABLE_ENABLE _MK_ENUM_CONST(0) +#define DC_COM_PIN_OUTPUT_ENABLE0_0_LD7_OUTPUT_ENABLE_DISABLE _MK_ENUM_CONST(1) + +#define DC_COM_PIN_OUTPUT_ENABLE0_0_LD8_OUTPUT_ENABLE_SHIFT _MK_SHIFT_CONST(16) +#define DC_COM_PIN_OUTPUT_ENABLE0_0_LD8_OUTPUT_ENABLE_FIELD _MK_FIELD_CONST(0x1, DC_COM_PIN_OUTPUT_ENABLE0_0_LD8_OUTPUT_ENABLE_SHIFT) +#define DC_COM_PIN_OUTPUT_ENABLE0_0_LD8_OUTPUT_ENABLE_RANGE 16:16 +#define DC_COM_PIN_OUTPUT_ENABLE0_0_LD8_OUTPUT_ENABLE_WOFFSET 0x0 +#define DC_COM_PIN_OUTPUT_ENABLE0_0_LD8_OUTPUT_ENABLE_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_ENABLE0_0_LD8_OUTPUT_ENABLE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_COM_PIN_OUTPUT_ENABLE0_0_LD8_OUTPUT_ENABLE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_ENABLE0_0_LD8_OUTPUT_ENABLE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_ENABLE0_0_LD8_OUTPUT_ENABLE_ENABLE _MK_ENUM_CONST(0) +#define DC_COM_PIN_OUTPUT_ENABLE0_0_LD8_OUTPUT_ENABLE_DISABLE _MK_ENUM_CONST(1) + +#define DC_COM_PIN_OUTPUT_ENABLE0_0_LD9_OUTPUT_ENABLE_SHIFT _MK_SHIFT_CONST(18) +#define DC_COM_PIN_OUTPUT_ENABLE0_0_LD9_OUTPUT_ENABLE_FIELD _MK_FIELD_CONST(0x1, DC_COM_PIN_OUTPUT_ENABLE0_0_LD9_OUTPUT_ENABLE_SHIFT) +#define DC_COM_PIN_OUTPUT_ENABLE0_0_LD9_OUTPUT_ENABLE_RANGE 18:18 +#define DC_COM_PIN_OUTPUT_ENABLE0_0_LD9_OUTPUT_ENABLE_WOFFSET 0x0 +#define DC_COM_PIN_OUTPUT_ENABLE0_0_LD9_OUTPUT_ENABLE_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_ENABLE0_0_LD9_OUTPUT_ENABLE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_COM_PIN_OUTPUT_ENABLE0_0_LD9_OUTPUT_ENABLE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_ENABLE0_0_LD9_OUTPUT_ENABLE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_ENABLE0_0_LD9_OUTPUT_ENABLE_ENABLE _MK_ENUM_CONST(0) +#define DC_COM_PIN_OUTPUT_ENABLE0_0_LD9_OUTPUT_ENABLE_DISABLE _MK_ENUM_CONST(1) + +#define DC_COM_PIN_OUTPUT_ENABLE0_0_LD10_OUTPUT_ENABLE_SHIFT _MK_SHIFT_CONST(20) +#define DC_COM_PIN_OUTPUT_ENABLE0_0_LD10_OUTPUT_ENABLE_FIELD _MK_FIELD_CONST(0x1, DC_COM_PIN_OUTPUT_ENABLE0_0_LD10_OUTPUT_ENABLE_SHIFT) +#define DC_COM_PIN_OUTPUT_ENABLE0_0_LD10_OUTPUT_ENABLE_RANGE 20:20 +#define DC_COM_PIN_OUTPUT_ENABLE0_0_LD10_OUTPUT_ENABLE_WOFFSET 0x0 +#define DC_COM_PIN_OUTPUT_ENABLE0_0_LD10_OUTPUT_ENABLE_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_ENABLE0_0_LD10_OUTPUT_ENABLE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_COM_PIN_OUTPUT_ENABLE0_0_LD10_OUTPUT_ENABLE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_ENABLE0_0_LD10_OUTPUT_ENABLE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_ENABLE0_0_LD10_OUTPUT_ENABLE_ENABLE _MK_ENUM_CONST(0) +#define DC_COM_PIN_OUTPUT_ENABLE0_0_LD10_OUTPUT_ENABLE_DISABLE _MK_ENUM_CONST(1) + +#define DC_COM_PIN_OUTPUT_ENABLE0_0_LD11_OUTPUT_ENABLE_SHIFT _MK_SHIFT_CONST(22) +#define DC_COM_PIN_OUTPUT_ENABLE0_0_LD11_OUTPUT_ENABLE_FIELD _MK_FIELD_CONST(0x1, DC_COM_PIN_OUTPUT_ENABLE0_0_LD11_OUTPUT_ENABLE_SHIFT) +#define DC_COM_PIN_OUTPUT_ENABLE0_0_LD11_OUTPUT_ENABLE_RANGE 22:22 +#define DC_COM_PIN_OUTPUT_ENABLE0_0_LD11_OUTPUT_ENABLE_WOFFSET 0x0 +#define DC_COM_PIN_OUTPUT_ENABLE0_0_LD11_OUTPUT_ENABLE_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_ENABLE0_0_LD11_OUTPUT_ENABLE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_COM_PIN_OUTPUT_ENABLE0_0_LD11_OUTPUT_ENABLE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_ENABLE0_0_LD11_OUTPUT_ENABLE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_ENABLE0_0_LD11_OUTPUT_ENABLE_ENABLE _MK_ENUM_CONST(0) +#define DC_COM_PIN_OUTPUT_ENABLE0_0_LD11_OUTPUT_ENABLE_DISABLE _MK_ENUM_CONST(1) + +#define DC_COM_PIN_OUTPUT_ENABLE0_0_LD12_OUTPUT_ENABLE_SHIFT _MK_SHIFT_CONST(24) +#define DC_COM_PIN_OUTPUT_ENABLE0_0_LD12_OUTPUT_ENABLE_FIELD _MK_FIELD_CONST(0x1, DC_COM_PIN_OUTPUT_ENABLE0_0_LD12_OUTPUT_ENABLE_SHIFT) +#define DC_COM_PIN_OUTPUT_ENABLE0_0_LD12_OUTPUT_ENABLE_RANGE 24:24 +#define DC_COM_PIN_OUTPUT_ENABLE0_0_LD12_OUTPUT_ENABLE_WOFFSET 0x0 +#define DC_COM_PIN_OUTPUT_ENABLE0_0_LD12_OUTPUT_ENABLE_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_ENABLE0_0_LD12_OUTPUT_ENABLE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_COM_PIN_OUTPUT_ENABLE0_0_LD12_OUTPUT_ENABLE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_ENABLE0_0_LD12_OUTPUT_ENABLE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_ENABLE0_0_LD12_OUTPUT_ENABLE_ENABLE _MK_ENUM_CONST(0) +#define DC_COM_PIN_OUTPUT_ENABLE0_0_LD12_OUTPUT_ENABLE_DISABLE _MK_ENUM_CONST(1) + +#define DC_COM_PIN_OUTPUT_ENABLE0_0_LD13_OUTPUT_ENABLE_SHIFT _MK_SHIFT_CONST(26) +#define DC_COM_PIN_OUTPUT_ENABLE0_0_LD13_OUTPUT_ENABLE_FIELD _MK_FIELD_CONST(0x1, DC_COM_PIN_OUTPUT_ENABLE0_0_LD13_OUTPUT_ENABLE_SHIFT) +#define DC_COM_PIN_OUTPUT_ENABLE0_0_LD13_OUTPUT_ENABLE_RANGE 26:26 +#define DC_COM_PIN_OUTPUT_ENABLE0_0_LD13_OUTPUT_ENABLE_WOFFSET 0x0 +#define DC_COM_PIN_OUTPUT_ENABLE0_0_LD13_OUTPUT_ENABLE_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_ENABLE0_0_LD13_OUTPUT_ENABLE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_COM_PIN_OUTPUT_ENABLE0_0_LD13_OUTPUT_ENABLE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_ENABLE0_0_LD13_OUTPUT_ENABLE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_ENABLE0_0_LD13_OUTPUT_ENABLE_ENABLE _MK_ENUM_CONST(0) +#define DC_COM_PIN_OUTPUT_ENABLE0_0_LD13_OUTPUT_ENABLE_DISABLE _MK_ENUM_CONST(1) + +#define DC_COM_PIN_OUTPUT_ENABLE0_0_LD14_OUTPUT_ENABLE_SHIFT _MK_SHIFT_CONST(28) +#define DC_COM_PIN_OUTPUT_ENABLE0_0_LD14_OUTPUT_ENABLE_FIELD _MK_FIELD_CONST(0x1, DC_COM_PIN_OUTPUT_ENABLE0_0_LD14_OUTPUT_ENABLE_SHIFT) +#define DC_COM_PIN_OUTPUT_ENABLE0_0_LD14_OUTPUT_ENABLE_RANGE 28:28 +#define DC_COM_PIN_OUTPUT_ENABLE0_0_LD14_OUTPUT_ENABLE_WOFFSET 0x0 +#define DC_COM_PIN_OUTPUT_ENABLE0_0_LD14_OUTPUT_ENABLE_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_ENABLE0_0_LD14_OUTPUT_ENABLE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_COM_PIN_OUTPUT_ENABLE0_0_LD14_OUTPUT_ENABLE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_ENABLE0_0_LD14_OUTPUT_ENABLE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_ENABLE0_0_LD14_OUTPUT_ENABLE_ENABLE _MK_ENUM_CONST(0) +#define DC_COM_PIN_OUTPUT_ENABLE0_0_LD14_OUTPUT_ENABLE_DISABLE _MK_ENUM_CONST(1) + +#define DC_COM_PIN_OUTPUT_ENABLE0_0_LD15_OUTPUT_ENABLE_SHIFT _MK_SHIFT_CONST(30) +#define DC_COM_PIN_OUTPUT_ENABLE0_0_LD15_OUTPUT_ENABLE_FIELD _MK_FIELD_CONST(0x1, DC_COM_PIN_OUTPUT_ENABLE0_0_LD15_OUTPUT_ENABLE_SHIFT) +#define DC_COM_PIN_OUTPUT_ENABLE0_0_LD15_OUTPUT_ENABLE_RANGE 30:30 +#define DC_COM_PIN_OUTPUT_ENABLE0_0_LD15_OUTPUT_ENABLE_WOFFSET 0x0 +#define DC_COM_PIN_OUTPUT_ENABLE0_0_LD15_OUTPUT_ENABLE_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_ENABLE0_0_LD15_OUTPUT_ENABLE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_COM_PIN_OUTPUT_ENABLE0_0_LD15_OUTPUT_ENABLE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_ENABLE0_0_LD15_OUTPUT_ENABLE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_ENABLE0_0_LD15_OUTPUT_ENABLE_ENABLE _MK_ENUM_CONST(0) +#define DC_COM_PIN_OUTPUT_ENABLE0_0_LD15_OUTPUT_ENABLE_DISABLE _MK_ENUM_CONST(1) + + +// Register DC_COM_PIN_OUTPUT_ENABLE1_0 +#define DC_COM_PIN_OUTPUT_ENABLE1_0 _MK_ADDR_CONST(0x303) +#define DC_COM_PIN_OUTPUT_ENABLE1_0_SECURE 0x0 +#define DC_COM_PIN_OUTPUT_ENABLE1_0_WORD_COUNT 0x1 +#define DC_COM_PIN_OUTPUT_ENABLE1_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_ENABLE1_0_RESET_MASK _MK_MASK_CONST(0x55150005) +#define DC_COM_PIN_OUTPUT_ENABLE1_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_ENABLE1_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_ENABLE1_0_READ_MASK _MK_MASK_CONST(0x55150005) +#define DC_COM_PIN_OUTPUT_ENABLE1_0_WRITE_MASK _MK_MASK_CONST(0x55150005) +#define DC_COM_PIN_OUTPUT_ENABLE1_0_LD16_OUTPUT_ENABLE_SHIFT _MK_SHIFT_CONST(0) +#define DC_COM_PIN_OUTPUT_ENABLE1_0_LD16_OUTPUT_ENABLE_FIELD _MK_FIELD_CONST(0x1, DC_COM_PIN_OUTPUT_ENABLE1_0_LD16_OUTPUT_ENABLE_SHIFT) +#define DC_COM_PIN_OUTPUT_ENABLE1_0_LD16_OUTPUT_ENABLE_RANGE 0:0 +#define DC_COM_PIN_OUTPUT_ENABLE1_0_LD16_OUTPUT_ENABLE_WOFFSET 0x0 +#define DC_COM_PIN_OUTPUT_ENABLE1_0_LD16_OUTPUT_ENABLE_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_ENABLE1_0_LD16_OUTPUT_ENABLE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_COM_PIN_OUTPUT_ENABLE1_0_LD16_OUTPUT_ENABLE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_ENABLE1_0_LD16_OUTPUT_ENABLE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_ENABLE1_0_LD16_OUTPUT_ENABLE_ENABLE _MK_ENUM_CONST(0) +#define DC_COM_PIN_OUTPUT_ENABLE1_0_LD16_OUTPUT_ENABLE_DISABLE _MK_ENUM_CONST(1) + +#define DC_COM_PIN_OUTPUT_ENABLE1_0_LD17_OUTPUT_ENABLE_SHIFT _MK_SHIFT_CONST(2) +#define DC_COM_PIN_OUTPUT_ENABLE1_0_LD17_OUTPUT_ENABLE_FIELD _MK_FIELD_CONST(0x1, DC_COM_PIN_OUTPUT_ENABLE1_0_LD17_OUTPUT_ENABLE_SHIFT) +#define DC_COM_PIN_OUTPUT_ENABLE1_0_LD17_OUTPUT_ENABLE_RANGE 2:2 +#define DC_COM_PIN_OUTPUT_ENABLE1_0_LD17_OUTPUT_ENABLE_WOFFSET 0x0 +#define DC_COM_PIN_OUTPUT_ENABLE1_0_LD17_OUTPUT_ENABLE_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_ENABLE1_0_LD17_OUTPUT_ENABLE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_COM_PIN_OUTPUT_ENABLE1_0_LD17_OUTPUT_ENABLE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_ENABLE1_0_LD17_OUTPUT_ENABLE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_ENABLE1_0_LD17_OUTPUT_ENABLE_ENABLE _MK_ENUM_CONST(0) +#define DC_COM_PIN_OUTPUT_ENABLE1_0_LD17_OUTPUT_ENABLE_DISABLE _MK_ENUM_CONST(1) + +#define DC_COM_PIN_OUTPUT_ENABLE1_0_LPW0_OUTPUT_ENABLE_SHIFT _MK_SHIFT_CONST(16) +#define DC_COM_PIN_OUTPUT_ENABLE1_0_LPW0_OUTPUT_ENABLE_FIELD _MK_FIELD_CONST(0x1, DC_COM_PIN_OUTPUT_ENABLE1_0_LPW0_OUTPUT_ENABLE_SHIFT) +#define DC_COM_PIN_OUTPUT_ENABLE1_0_LPW0_OUTPUT_ENABLE_RANGE 16:16 +#define DC_COM_PIN_OUTPUT_ENABLE1_0_LPW0_OUTPUT_ENABLE_WOFFSET 0x0 +#define DC_COM_PIN_OUTPUT_ENABLE1_0_LPW0_OUTPUT_ENABLE_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_ENABLE1_0_LPW0_OUTPUT_ENABLE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_COM_PIN_OUTPUT_ENABLE1_0_LPW0_OUTPUT_ENABLE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_ENABLE1_0_LPW0_OUTPUT_ENABLE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_ENABLE1_0_LPW0_OUTPUT_ENABLE_ENABLE _MK_ENUM_CONST(0) +#define DC_COM_PIN_OUTPUT_ENABLE1_0_LPW0_OUTPUT_ENABLE_DISABLE _MK_ENUM_CONST(1) + +#define DC_COM_PIN_OUTPUT_ENABLE1_0_LPW1_OUTPUT_ENABLE_SHIFT _MK_SHIFT_CONST(18) +#define DC_COM_PIN_OUTPUT_ENABLE1_0_LPW1_OUTPUT_ENABLE_FIELD _MK_FIELD_CONST(0x1, DC_COM_PIN_OUTPUT_ENABLE1_0_LPW1_OUTPUT_ENABLE_SHIFT) +#define DC_COM_PIN_OUTPUT_ENABLE1_0_LPW1_OUTPUT_ENABLE_RANGE 18:18 +#define DC_COM_PIN_OUTPUT_ENABLE1_0_LPW1_OUTPUT_ENABLE_WOFFSET 0x0 +#define DC_COM_PIN_OUTPUT_ENABLE1_0_LPW1_OUTPUT_ENABLE_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_ENABLE1_0_LPW1_OUTPUT_ENABLE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_COM_PIN_OUTPUT_ENABLE1_0_LPW1_OUTPUT_ENABLE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_ENABLE1_0_LPW1_OUTPUT_ENABLE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_ENABLE1_0_LPW1_OUTPUT_ENABLE_ENABLE _MK_ENUM_CONST(0) +#define DC_COM_PIN_OUTPUT_ENABLE1_0_LPW1_OUTPUT_ENABLE_DISABLE _MK_ENUM_CONST(1) + +#define DC_COM_PIN_OUTPUT_ENABLE1_0_LPW2_OUTPUT_ENABLE_SHIFT _MK_SHIFT_CONST(20) +#define DC_COM_PIN_OUTPUT_ENABLE1_0_LPW2_OUTPUT_ENABLE_FIELD _MK_FIELD_CONST(0x1, DC_COM_PIN_OUTPUT_ENABLE1_0_LPW2_OUTPUT_ENABLE_SHIFT) +#define DC_COM_PIN_OUTPUT_ENABLE1_0_LPW2_OUTPUT_ENABLE_RANGE 20:20 +#define DC_COM_PIN_OUTPUT_ENABLE1_0_LPW2_OUTPUT_ENABLE_WOFFSET 0x0 +#define DC_COM_PIN_OUTPUT_ENABLE1_0_LPW2_OUTPUT_ENABLE_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_ENABLE1_0_LPW2_OUTPUT_ENABLE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_COM_PIN_OUTPUT_ENABLE1_0_LPW2_OUTPUT_ENABLE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_ENABLE1_0_LPW2_OUTPUT_ENABLE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_ENABLE1_0_LPW2_OUTPUT_ENABLE_ENABLE _MK_ENUM_CONST(0) +#define DC_COM_PIN_OUTPUT_ENABLE1_0_LPW2_OUTPUT_ENABLE_DISABLE _MK_ENUM_CONST(1) + +#define DC_COM_PIN_OUTPUT_ENABLE1_0_LSC0_OUTPUT_ENABLE_SHIFT _MK_SHIFT_CONST(24) +#define DC_COM_PIN_OUTPUT_ENABLE1_0_LSC0_OUTPUT_ENABLE_FIELD _MK_FIELD_CONST(0x1, DC_COM_PIN_OUTPUT_ENABLE1_0_LSC0_OUTPUT_ENABLE_SHIFT) +#define DC_COM_PIN_OUTPUT_ENABLE1_0_LSC0_OUTPUT_ENABLE_RANGE 24:24 +#define DC_COM_PIN_OUTPUT_ENABLE1_0_LSC0_OUTPUT_ENABLE_WOFFSET 0x0 +#define DC_COM_PIN_OUTPUT_ENABLE1_0_LSC0_OUTPUT_ENABLE_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_ENABLE1_0_LSC0_OUTPUT_ENABLE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_COM_PIN_OUTPUT_ENABLE1_0_LSC0_OUTPUT_ENABLE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_ENABLE1_0_LSC0_OUTPUT_ENABLE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_ENABLE1_0_LSC0_OUTPUT_ENABLE_ENABLE _MK_ENUM_CONST(0) +#define DC_COM_PIN_OUTPUT_ENABLE1_0_LSC0_OUTPUT_ENABLE_DISABLE _MK_ENUM_CONST(1) + +#define DC_COM_PIN_OUTPUT_ENABLE1_0_LSC1_OUTPUT_ENABLE_SHIFT _MK_SHIFT_CONST(26) +#define DC_COM_PIN_OUTPUT_ENABLE1_0_LSC1_OUTPUT_ENABLE_FIELD _MK_FIELD_CONST(0x1, DC_COM_PIN_OUTPUT_ENABLE1_0_LSC1_OUTPUT_ENABLE_SHIFT) +#define DC_COM_PIN_OUTPUT_ENABLE1_0_LSC1_OUTPUT_ENABLE_RANGE 26:26 +#define DC_COM_PIN_OUTPUT_ENABLE1_0_LSC1_OUTPUT_ENABLE_WOFFSET 0x0 +#define DC_COM_PIN_OUTPUT_ENABLE1_0_LSC1_OUTPUT_ENABLE_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_ENABLE1_0_LSC1_OUTPUT_ENABLE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_COM_PIN_OUTPUT_ENABLE1_0_LSC1_OUTPUT_ENABLE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_ENABLE1_0_LSC1_OUTPUT_ENABLE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_ENABLE1_0_LSC1_OUTPUT_ENABLE_ENABLE _MK_ENUM_CONST(0) +#define DC_COM_PIN_OUTPUT_ENABLE1_0_LSC1_OUTPUT_ENABLE_DISABLE _MK_ENUM_CONST(1) + +#define DC_COM_PIN_OUTPUT_ENABLE1_0_LVS_OUTPUT_ENABLE_SHIFT _MK_SHIFT_CONST(28) +#define DC_COM_PIN_OUTPUT_ENABLE1_0_LVS_OUTPUT_ENABLE_FIELD _MK_FIELD_CONST(0x1, DC_COM_PIN_OUTPUT_ENABLE1_0_LVS_OUTPUT_ENABLE_SHIFT) +#define DC_COM_PIN_OUTPUT_ENABLE1_0_LVS_OUTPUT_ENABLE_RANGE 28:28 +#define DC_COM_PIN_OUTPUT_ENABLE1_0_LVS_OUTPUT_ENABLE_WOFFSET 0x0 +#define DC_COM_PIN_OUTPUT_ENABLE1_0_LVS_OUTPUT_ENABLE_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_ENABLE1_0_LVS_OUTPUT_ENABLE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_COM_PIN_OUTPUT_ENABLE1_0_LVS_OUTPUT_ENABLE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_ENABLE1_0_LVS_OUTPUT_ENABLE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_ENABLE1_0_LVS_OUTPUT_ENABLE_ENABLE _MK_ENUM_CONST(0) +#define DC_COM_PIN_OUTPUT_ENABLE1_0_LVS_OUTPUT_ENABLE_DISABLE _MK_ENUM_CONST(1) + +#define DC_COM_PIN_OUTPUT_ENABLE1_0_LHS_OUTPUT_ENABLE_SHIFT _MK_SHIFT_CONST(30) +#define DC_COM_PIN_OUTPUT_ENABLE1_0_LHS_OUTPUT_ENABLE_FIELD _MK_FIELD_CONST(0x1, DC_COM_PIN_OUTPUT_ENABLE1_0_LHS_OUTPUT_ENABLE_SHIFT) +#define DC_COM_PIN_OUTPUT_ENABLE1_0_LHS_OUTPUT_ENABLE_RANGE 30:30 +#define DC_COM_PIN_OUTPUT_ENABLE1_0_LHS_OUTPUT_ENABLE_WOFFSET 0x0 +#define DC_COM_PIN_OUTPUT_ENABLE1_0_LHS_OUTPUT_ENABLE_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_ENABLE1_0_LHS_OUTPUT_ENABLE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_COM_PIN_OUTPUT_ENABLE1_0_LHS_OUTPUT_ENABLE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_ENABLE1_0_LHS_OUTPUT_ENABLE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_ENABLE1_0_LHS_OUTPUT_ENABLE_ENABLE _MK_ENUM_CONST(0) +#define DC_COM_PIN_OUTPUT_ENABLE1_0_LHS_OUTPUT_ENABLE_DISABLE _MK_ENUM_CONST(1) + + +// Register DC_COM_PIN_OUTPUT_ENABLE2_0 +#define DC_COM_PIN_OUTPUT_ENABLE2_0 _MK_ADDR_CONST(0x304) +#define DC_COM_PIN_OUTPUT_ENABLE2_0_SECURE 0x0 +#define DC_COM_PIN_OUTPUT_ENABLE2_0_WORD_COUNT 0x1 +#define DC_COM_PIN_OUTPUT_ENABLE2_0_RESET_VAL _MK_MASK_CONST(0x510104) +#define DC_COM_PIN_OUTPUT_ENABLE2_0_RESET_MASK _MK_MASK_CONST(0x550515) +#define DC_COM_PIN_OUTPUT_ENABLE2_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x510104) +#define DC_COM_PIN_OUTPUT_ENABLE2_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x510104) +#define DC_COM_PIN_OUTPUT_ENABLE2_0_READ_MASK _MK_MASK_CONST(0x550515) +#define DC_COM_PIN_OUTPUT_ENABLE2_0_WRITE_MASK _MK_MASK_CONST(0x550515) +#define DC_COM_PIN_OUTPUT_ENABLE2_0_LHP0_OUTPUT_ENABLE_SHIFT _MK_SHIFT_CONST(0) +#define DC_COM_PIN_OUTPUT_ENABLE2_0_LHP0_OUTPUT_ENABLE_FIELD _MK_FIELD_CONST(0x1, DC_COM_PIN_OUTPUT_ENABLE2_0_LHP0_OUTPUT_ENABLE_SHIFT) +#define DC_COM_PIN_OUTPUT_ENABLE2_0_LHP0_OUTPUT_ENABLE_RANGE 0:0 +#define DC_COM_PIN_OUTPUT_ENABLE2_0_LHP0_OUTPUT_ENABLE_WOFFSET 0x0 +#define DC_COM_PIN_OUTPUT_ENABLE2_0_LHP0_OUTPUT_ENABLE_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_ENABLE2_0_LHP0_OUTPUT_ENABLE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_COM_PIN_OUTPUT_ENABLE2_0_LHP0_OUTPUT_ENABLE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_ENABLE2_0_LHP0_OUTPUT_ENABLE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_ENABLE2_0_LHP0_OUTPUT_ENABLE_ENABLE _MK_ENUM_CONST(0) +#define DC_COM_PIN_OUTPUT_ENABLE2_0_LHP0_OUTPUT_ENABLE_DISABLE _MK_ENUM_CONST(1) + +#define DC_COM_PIN_OUTPUT_ENABLE2_0_LHP1_OUTPUT_ENABLE_SHIFT _MK_SHIFT_CONST(2) +#define DC_COM_PIN_OUTPUT_ENABLE2_0_LHP1_OUTPUT_ENABLE_FIELD _MK_FIELD_CONST(0x1, DC_COM_PIN_OUTPUT_ENABLE2_0_LHP1_OUTPUT_ENABLE_SHIFT) +#define DC_COM_PIN_OUTPUT_ENABLE2_0_LHP1_OUTPUT_ENABLE_RANGE 2:2 +#define DC_COM_PIN_OUTPUT_ENABLE2_0_LHP1_OUTPUT_ENABLE_WOFFSET 0x0 +#define DC_COM_PIN_OUTPUT_ENABLE2_0_LHP1_OUTPUT_ENABLE_DEFAULT _MK_MASK_CONST(0x1) +#define DC_COM_PIN_OUTPUT_ENABLE2_0_LHP1_OUTPUT_ENABLE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_COM_PIN_OUTPUT_ENABLE2_0_LHP1_OUTPUT_ENABLE_SW_DEFAULT _MK_MASK_CONST(0x1) +#define DC_COM_PIN_OUTPUT_ENABLE2_0_LHP1_OUTPUT_ENABLE_SW_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_COM_PIN_OUTPUT_ENABLE2_0_LHP1_OUTPUT_ENABLE_ENABLE _MK_ENUM_CONST(0) +#define DC_COM_PIN_OUTPUT_ENABLE2_0_LHP1_OUTPUT_ENABLE_DISABLE _MK_ENUM_CONST(1) + +#define DC_COM_PIN_OUTPUT_ENABLE2_0_LHP2_OUTPUT_ENABLE_SHIFT _MK_SHIFT_CONST(4) +#define DC_COM_PIN_OUTPUT_ENABLE2_0_LHP2_OUTPUT_ENABLE_FIELD _MK_FIELD_CONST(0x1, DC_COM_PIN_OUTPUT_ENABLE2_0_LHP2_OUTPUT_ENABLE_SHIFT) +#define DC_COM_PIN_OUTPUT_ENABLE2_0_LHP2_OUTPUT_ENABLE_RANGE 4:4 +#define DC_COM_PIN_OUTPUT_ENABLE2_0_LHP2_OUTPUT_ENABLE_WOFFSET 0x0 +#define DC_COM_PIN_OUTPUT_ENABLE2_0_LHP2_OUTPUT_ENABLE_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_ENABLE2_0_LHP2_OUTPUT_ENABLE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_COM_PIN_OUTPUT_ENABLE2_0_LHP2_OUTPUT_ENABLE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_ENABLE2_0_LHP2_OUTPUT_ENABLE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_ENABLE2_0_LHP2_OUTPUT_ENABLE_ENABLE _MK_ENUM_CONST(0) +#define DC_COM_PIN_OUTPUT_ENABLE2_0_LHP2_OUTPUT_ENABLE_DISABLE _MK_ENUM_CONST(1) + +#define DC_COM_PIN_OUTPUT_ENABLE2_0_LVP0_OUTPUT_ENABLE_SHIFT _MK_SHIFT_CONST(8) +#define DC_COM_PIN_OUTPUT_ENABLE2_0_LVP0_OUTPUT_ENABLE_FIELD _MK_FIELD_CONST(0x1, DC_COM_PIN_OUTPUT_ENABLE2_0_LVP0_OUTPUT_ENABLE_SHIFT) +#define DC_COM_PIN_OUTPUT_ENABLE2_0_LVP0_OUTPUT_ENABLE_RANGE 8:8 +#define DC_COM_PIN_OUTPUT_ENABLE2_0_LVP0_OUTPUT_ENABLE_WOFFSET 0x0 +#define DC_COM_PIN_OUTPUT_ENABLE2_0_LVP0_OUTPUT_ENABLE_DEFAULT _MK_MASK_CONST(0x1) +#define DC_COM_PIN_OUTPUT_ENABLE2_0_LVP0_OUTPUT_ENABLE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_COM_PIN_OUTPUT_ENABLE2_0_LVP0_OUTPUT_ENABLE_SW_DEFAULT _MK_MASK_CONST(0x1) +#define DC_COM_PIN_OUTPUT_ENABLE2_0_LVP0_OUTPUT_ENABLE_SW_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_COM_PIN_OUTPUT_ENABLE2_0_LVP0_OUTPUT_ENABLE_ENABLE _MK_ENUM_CONST(0) +#define DC_COM_PIN_OUTPUT_ENABLE2_0_LVP0_OUTPUT_ENABLE_DISABLE _MK_ENUM_CONST(1) + +#define DC_COM_PIN_OUTPUT_ENABLE2_0_LVP1_OUTPUT_ENABLE_SHIFT _MK_SHIFT_CONST(10) +#define DC_COM_PIN_OUTPUT_ENABLE2_0_LVP1_OUTPUT_ENABLE_FIELD _MK_FIELD_CONST(0x1, DC_COM_PIN_OUTPUT_ENABLE2_0_LVP1_OUTPUT_ENABLE_SHIFT) +#define DC_COM_PIN_OUTPUT_ENABLE2_0_LVP1_OUTPUT_ENABLE_RANGE 10:10 +#define DC_COM_PIN_OUTPUT_ENABLE2_0_LVP1_OUTPUT_ENABLE_WOFFSET 0x0 +#define DC_COM_PIN_OUTPUT_ENABLE2_0_LVP1_OUTPUT_ENABLE_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_ENABLE2_0_LVP1_OUTPUT_ENABLE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_COM_PIN_OUTPUT_ENABLE2_0_LVP1_OUTPUT_ENABLE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_ENABLE2_0_LVP1_OUTPUT_ENABLE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_ENABLE2_0_LVP1_OUTPUT_ENABLE_ENABLE _MK_ENUM_CONST(0) +#define DC_COM_PIN_OUTPUT_ENABLE2_0_LVP1_OUTPUT_ENABLE_DISABLE _MK_ENUM_CONST(1) + +#define DC_COM_PIN_OUTPUT_ENABLE2_0_LM0_OUTPUT_ENABLE_SHIFT _MK_SHIFT_CONST(16) +#define DC_COM_PIN_OUTPUT_ENABLE2_0_LM0_OUTPUT_ENABLE_FIELD _MK_FIELD_CONST(0x1, DC_COM_PIN_OUTPUT_ENABLE2_0_LM0_OUTPUT_ENABLE_SHIFT) +#define DC_COM_PIN_OUTPUT_ENABLE2_0_LM0_OUTPUT_ENABLE_RANGE 16:16 +#define DC_COM_PIN_OUTPUT_ENABLE2_0_LM0_OUTPUT_ENABLE_WOFFSET 0x0 +#define DC_COM_PIN_OUTPUT_ENABLE2_0_LM0_OUTPUT_ENABLE_DEFAULT _MK_MASK_CONST(0x1) +#define DC_COM_PIN_OUTPUT_ENABLE2_0_LM0_OUTPUT_ENABLE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_COM_PIN_OUTPUT_ENABLE2_0_LM0_OUTPUT_ENABLE_SW_DEFAULT _MK_MASK_CONST(0x1) +#define DC_COM_PIN_OUTPUT_ENABLE2_0_LM0_OUTPUT_ENABLE_SW_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_COM_PIN_OUTPUT_ENABLE2_0_LM0_OUTPUT_ENABLE_ENABLE _MK_ENUM_CONST(0) +#define DC_COM_PIN_OUTPUT_ENABLE2_0_LM0_OUTPUT_ENABLE_DISABLE _MK_ENUM_CONST(1) + +#define DC_COM_PIN_OUTPUT_ENABLE2_0_LM1_OUTPUT_ENABLE_SHIFT _MK_SHIFT_CONST(18) +#define DC_COM_PIN_OUTPUT_ENABLE2_0_LM1_OUTPUT_ENABLE_FIELD _MK_FIELD_CONST(0x1, DC_COM_PIN_OUTPUT_ENABLE2_0_LM1_OUTPUT_ENABLE_SHIFT) +#define DC_COM_PIN_OUTPUT_ENABLE2_0_LM1_OUTPUT_ENABLE_RANGE 18:18 +#define DC_COM_PIN_OUTPUT_ENABLE2_0_LM1_OUTPUT_ENABLE_WOFFSET 0x0 +#define DC_COM_PIN_OUTPUT_ENABLE2_0_LM1_OUTPUT_ENABLE_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_ENABLE2_0_LM1_OUTPUT_ENABLE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_COM_PIN_OUTPUT_ENABLE2_0_LM1_OUTPUT_ENABLE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_ENABLE2_0_LM1_OUTPUT_ENABLE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_ENABLE2_0_LM1_OUTPUT_ENABLE_ENABLE _MK_ENUM_CONST(0) +#define DC_COM_PIN_OUTPUT_ENABLE2_0_LM1_OUTPUT_ENABLE_DISABLE _MK_ENUM_CONST(1) + +#define DC_COM_PIN_OUTPUT_ENABLE2_0_LDI_OUTPUT_ENABLE_SHIFT _MK_SHIFT_CONST(20) +#define DC_COM_PIN_OUTPUT_ENABLE2_0_LDI_OUTPUT_ENABLE_FIELD _MK_FIELD_CONST(0x1, DC_COM_PIN_OUTPUT_ENABLE2_0_LDI_OUTPUT_ENABLE_SHIFT) +#define DC_COM_PIN_OUTPUT_ENABLE2_0_LDI_OUTPUT_ENABLE_RANGE 20:20 +#define DC_COM_PIN_OUTPUT_ENABLE2_0_LDI_OUTPUT_ENABLE_WOFFSET 0x0 +#define DC_COM_PIN_OUTPUT_ENABLE2_0_LDI_OUTPUT_ENABLE_DEFAULT _MK_MASK_CONST(0x1) +#define DC_COM_PIN_OUTPUT_ENABLE2_0_LDI_OUTPUT_ENABLE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_COM_PIN_OUTPUT_ENABLE2_0_LDI_OUTPUT_ENABLE_SW_DEFAULT _MK_MASK_CONST(0x1) +#define DC_COM_PIN_OUTPUT_ENABLE2_0_LDI_OUTPUT_ENABLE_SW_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_COM_PIN_OUTPUT_ENABLE2_0_LDI_OUTPUT_ENABLE_ENABLE _MK_ENUM_CONST(0) +#define DC_COM_PIN_OUTPUT_ENABLE2_0_LDI_OUTPUT_ENABLE_DISABLE _MK_ENUM_CONST(1) + +#define DC_COM_PIN_OUTPUT_ENABLE2_0_LPP_OUTPUT_ENABLE_SHIFT _MK_SHIFT_CONST(22) +#define DC_COM_PIN_OUTPUT_ENABLE2_0_LPP_OUTPUT_ENABLE_FIELD _MK_FIELD_CONST(0x1, DC_COM_PIN_OUTPUT_ENABLE2_0_LPP_OUTPUT_ENABLE_SHIFT) +#define DC_COM_PIN_OUTPUT_ENABLE2_0_LPP_OUTPUT_ENABLE_RANGE 22:22 +#define DC_COM_PIN_OUTPUT_ENABLE2_0_LPP_OUTPUT_ENABLE_WOFFSET 0x0 +#define DC_COM_PIN_OUTPUT_ENABLE2_0_LPP_OUTPUT_ENABLE_DEFAULT _MK_MASK_CONST(0x1) +#define DC_COM_PIN_OUTPUT_ENABLE2_0_LPP_OUTPUT_ENABLE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_COM_PIN_OUTPUT_ENABLE2_0_LPP_OUTPUT_ENABLE_SW_DEFAULT _MK_MASK_CONST(0x1) +#define DC_COM_PIN_OUTPUT_ENABLE2_0_LPP_OUTPUT_ENABLE_SW_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_COM_PIN_OUTPUT_ENABLE2_0_LPP_OUTPUT_ENABLE_ENABLE _MK_ENUM_CONST(0) +#define DC_COM_PIN_OUTPUT_ENABLE2_0_LPP_OUTPUT_ENABLE_DISABLE _MK_ENUM_CONST(1) + + +// Register DC_COM_PIN_OUTPUT_ENABLE3_0 +#define DC_COM_PIN_OUTPUT_ENABLE3_0 _MK_ADDR_CONST(0x305) +#define DC_COM_PIN_OUTPUT_ENABLE3_0_SECURE 0x0 +#define DC_COM_PIN_OUTPUT_ENABLE3_0_WORD_COUNT 0x1 +#define DC_COM_PIN_OUTPUT_ENABLE3_0_RESET_VAL _MK_MASK_CONST(0x555) +#define DC_COM_PIN_OUTPUT_ENABLE3_0_RESET_MASK _MK_MASK_CONST(0x555) +#define DC_COM_PIN_OUTPUT_ENABLE3_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x555) +#define DC_COM_PIN_OUTPUT_ENABLE3_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x555) +#define DC_COM_PIN_OUTPUT_ENABLE3_0_READ_MASK _MK_MASK_CONST(0x555) +#define DC_COM_PIN_OUTPUT_ENABLE3_0_WRITE_MASK _MK_MASK_CONST(0x555) +#define DC_COM_PIN_OUTPUT_ENABLE3_0_LSCK_OUTPUT_ENABLE_SHIFT _MK_SHIFT_CONST(0) +#define DC_COM_PIN_OUTPUT_ENABLE3_0_LSCK_OUTPUT_ENABLE_FIELD _MK_FIELD_CONST(0x1, DC_COM_PIN_OUTPUT_ENABLE3_0_LSCK_OUTPUT_ENABLE_SHIFT) +#define DC_COM_PIN_OUTPUT_ENABLE3_0_LSCK_OUTPUT_ENABLE_RANGE 0:0 +#define DC_COM_PIN_OUTPUT_ENABLE3_0_LSCK_OUTPUT_ENABLE_WOFFSET 0x0 +#define DC_COM_PIN_OUTPUT_ENABLE3_0_LSCK_OUTPUT_ENABLE_DEFAULT _MK_MASK_CONST(0x1) +#define DC_COM_PIN_OUTPUT_ENABLE3_0_LSCK_OUTPUT_ENABLE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_COM_PIN_OUTPUT_ENABLE3_0_LSCK_OUTPUT_ENABLE_SW_DEFAULT _MK_MASK_CONST(0x1) +#define DC_COM_PIN_OUTPUT_ENABLE3_0_LSCK_OUTPUT_ENABLE_SW_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_COM_PIN_OUTPUT_ENABLE3_0_LSCK_OUTPUT_ENABLE_ENABLE _MK_ENUM_CONST(0) +#define DC_COM_PIN_OUTPUT_ENABLE3_0_LSCK_OUTPUT_ENABLE_DISABLE _MK_ENUM_CONST(1) + +#define DC_COM_PIN_OUTPUT_ENABLE3_0_LSDA_OUTPUT_ENABLE_SHIFT _MK_SHIFT_CONST(2) +#define DC_COM_PIN_OUTPUT_ENABLE3_0_LSDA_OUTPUT_ENABLE_FIELD _MK_FIELD_CONST(0x1, DC_COM_PIN_OUTPUT_ENABLE3_0_LSDA_OUTPUT_ENABLE_SHIFT) +#define DC_COM_PIN_OUTPUT_ENABLE3_0_LSDA_OUTPUT_ENABLE_RANGE 2:2 +#define DC_COM_PIN_OUTPUT_ENABLE3_0_LSDA_OUTPUT_ENABLE_WOFFSET 0x0 +#define DC_COM_PIN_OUTPUT_ENABLE3_0_LSDA_OUTPUT_ENABLE_DEFAULT _MK_MASK_CONST(0x1) +#define DC_COM_PIN_OUTPUT_ENABLE3_0_LSDA_OUTPUT_ENABLE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_COM_PIN_OUTPUT_ENABLE3_0_LSDA_OUTPUT_ENABLE_SW_DEFAULT _MK_MASK_CONST(0x1) +#define DC_COM_PIN_OUTPUT_ENABLE3_0_LSDA_OUTPUT_ENABLE_SW_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_COM_PIN_OUTPUT_ENABLE3_0_LSDA_OUTPUT_ENABLE_ENABLE _MK_ENUM_CONST(0) +#define DC_COM_PIN_OUTPUT_ENABLE3_0_LSDA_OUTPUT_ENABLE_DISABLE _MK_ENUM_CONST(1) + +#define DC_COM_PIN_OUTPUT_ENABLE3_0_LCSN_OUTPUT_ENABLE_SHIFT _MK_SHIFT_CONST(4) +#define DC_COM_PIN_OUTPUT_ENABLE3_0_LCSN_OUTPUT_ENABLE_FIELD _MK_FIELD_CONST(0x1, DC_COM_PIN_OUTPUT_ENABLE3_0_LCSN_OUTPUT_ENABLE_SHIFT) +#define DC_COM_PIN_OUTPUT_ENABLE3_0_LCSN_OUTPUT_ENABLE_RANGE 4:4 +#define DC_COM_PIN_OUTPUT_ENABLE3_0_LCSN_OUTPUT_ENABLE_WOFFSET 0x0 +#define DC_COM_PIN_OUTPUT_ENABLE3_0_LCSN_OUTPUT_ENABLE_DEFAULT _MK_MASK_CONST(0x1) +#define DC_COM_PIN_OUTPUT_ENABLE3_0_LCSN_OUTPUT_ENABLE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_COM_PIN_OUTPUT_ENABLE3_0_LCSN_OUTPUT_ENABLE_SW_DEFAULT _MK_MASK_CONST(0x1) +#define DC_COM_PIN_OUTPUT_ENABLE3_0_LCSN_OUTPUT_ENABLE_SW_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_COM_PIN_OUTPUT_ENABLE3_0_LCSN_OUTPUT_ENABLE_ENABLE _MK_ENUM_CONST(0) +#define DC_COM_PIN_OUTPUT_ENABLE3_0_LCSN_OUTPUT_ENABLE_DISABLE _MK_ENUM_CONST(1) + +#define DC_COM_PIN_OUTPUT_ENABLE3_0_LDC_OUTPUT_ENABLE_SHIFT _MK_SHIFT_CONST(6) +#define DC_COM_PIN_OUTPUT_ENABLE3_0_LDC_OUTPUT_ENABLE_FIELD _MK_FIELD_CONST(0x1, DC_COM_PIN_OUTPUT_ENABLE3_0_LDC_OUTPUT_ENABLE_SHIFT) +#define DC_COM_PIN_OUTPUT_ENABLE3_0_LDC_OUTPUT_ENABLE_RANGE 6:6 +#define DC_COM_PIN_OUTPUT_ENABLE3_0_LDC_OUTPUT_ENABLE_WOFFSET 0x0 +#define DC_COM_PIN_OUTPUT_ENABLE3_0_LDC_OUTPUT_ENABLE_DEFAULT _MK_MASK_CONST(0x1) +#define DC_COM_PIN_OUTPUT_ENABLE3_0_LDC_OUTPUT_ENABLE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_COM_PIN_OUTPUT_ENABLE3_0_LDC_OUTPUT_ENABLE_SW_DEFAULT _MK_MASK_CONST(0x1) +#define DC_COM_PIN_OUTPUT_ENABLE3_0_LDC_OUTPUT_ENABLE_SW_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_COM_PIN_OUTPUT_ENABLE3_0_LDC_OUTPUT_ENABLE_ENABLE _MK_ENUM_CONST(0) +#define DC_COM_PIN_OUTPUT_ENABLE3_0_LDC_OUTPUT_ENABLE_DISABLE _MK_ENUM_CONST(1) + +#define DC_COM_PIN_OUTPUT_ENABLE3_0_LSPI_OUTPUT_ENABLE_SHIFT _MK_SHIFT_CONST(8) +#define DC_COM_PIN_OUTPUT_ENABLE3_0_LSPI_OUTPUT_ENABLE_FIELD _MK_FIELD_CONST(0x1, DC_COM_PIN_OUTPUT_ENABLE3_0_LSPI_OUTPUT_ENABLE_SHIFT) +#define DC_COM_PIN_OUTPUT_ENABLE3_0_LSPI_OUTPUT_ENABLE_RANGE 8:8 +#define DC_COM_PIN_OUTPUT_ENABLE3_0_LSPI_OUTPUT_ENABLE_WOFFSET 0x0 +#define DC_COM_PIN_OUTPUT_ENABLE3_0_LSPI_OUTPUT_ENABLE_DEFAULT _MK_MASK_CONST(0x1) +#define DC_COM_PIN_OUTPUT_ENABLE3_0_LSPI_OUTPUT_ENABLE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_COM_PIN_OUTPUT_ENABLE3_0_LSPI_OUTPUT_ENABLE_SW_DEFAULT _MK_MASK_CONST(0x1) +#define DC_COM_PIN_OUTPUT_ENABLE3_0_LSPI_OUTPUT_ENABLE_SW_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_COM_PIN_OUTPUT_ENABLE3_0_LSPI_OUTPUT_ENABLE_ENABLE _MK_ENUM_CONST(0) +#define DC_COM_PIN_OUTPUT_ENABLE3_0_LSPI_OUTPUT_ENABLE_DISABLE _MK_ENUM_CONST(1) + +#define DC_COM_PIN_OUTPUT_ENABLE3_0_LSDI_OUTPUT_ENABLE_SHIFT _MK_SHIFT_CONST(10) +#define DC_COM_PIN_OUTPUT_ENABLE3_0_LSDI_OUTPUT_ENABLE_FIELD _MK_FIELD_CONST(0x1, DC_COM_PIN_OUTPUT_ENABLE3_0_LSDI_OUTPUT_ENABLE_SHIFT) +#define DC_COM_PIN_OUTPUT_ENABLE3_0_LSDI_OUTPUT_ENABLE_RANGE 10:10 +#define DC_COM_PIN_OUTPUT_ENABLE3_0_LSDI_OUTPUT_ENABLE_WOFFSET 0x0 +#define DC_COM_PIN_OUTPUT_ENABLE3_0_LSDI_OUTPUT_ENABLE_DEFAULT _MK_MASK_CONST(0x1) +#define DC_COM_PIN_OUTPUT_ENABLE3_0_LSDI_OUTPUT_ENABLE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_COM_PIN_OUTPUT_ENABLE3_0_LSDI_OUTPUT_ENABLE_SW_DEFAULT _MK_MASK_CONST(0x1) +#define DC_COM_PIN_OUTPUT_ENABLE3_0_LSDI_OUTPUT_ENABLE_SW_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_COM_PIN_OUTPUT_ENABLE3_0_LSDI_OUTPUT_ENABLE_ENABLE _MK_ENUM_CONST(0) +#define DC_COM_PIN_OUTPUT_ENABLE3_0_LSDI_OUTPUT_ENABLE_DISABLE _MK_ENUM_CONST(1) + + +// Register DC_COM_PIN_OUTPUT_POLARITY0_0 +#define DC_COM_PIN_OUTPUT_POLARITY0_0 _MK_ADDR_CONST(0x306) +#define DC_COM_PIN_OUTPUT_POLARITY0_0_SECURE 0x0 +#define DC_COM_PIN_OUTPUT_POLARITY0_0_WORD_COUNT 0x1 +#define DC_COM_PIN_OUTPUT_POLARITY0_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_POLARITY0_0_RESET_MASK _MK_MASK_CONST(0x55555555) +#define DC_COM_PIN_OUTPUT_POLARITY0_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_POLARITY0_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_POLARITY0_0_READ_MASK _MK_MASK_CONST(0x55555555) +#define DC_COM_PIN_OUTPUT_POLARITY0_0_WRITE_MASK _MK_MASK_CONST(0x55555555) +#define DC_COM_PIN_OUTPUT_POLARITY0_0_LD0_OUTPUT_POLARITY_SHIFT _MK_SHIFT_CONST(0) +#define DC_COM_PIN_OUTPUT_POLARITY0_0_LD0_OUTPUT_POLARITY_FIELD _MK_FIELD_CONST(0x1, DC_COM_PIN_OUTPUT_POLARITY0_0_LD0_OUTPUT_POLARITY_SHIFT) +#define DC_COM_PIN_OUTPUT_POLARITY0_0_LD0_OUTPUT_POLARITY_RANGE 0:0 +#define DC_COM_PIN_OUTPUT_POLARITY0_0_LD0_OUTPUT_POLARITY_WOFFSET 0x0 +#define DC_COM_PIN_OUTPUT_POLARITY0_0_LD0_OUTPUT_POLARITY_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_POLARITY0_0_LD0_OUTPUT_POLARITY_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_COM_PIN_OUTPUT_POLARITY0_0_LD0_OUTPUT_POLARITY_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_POLARITY0_0_LD0_OUTPUT_POLARITY_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_POLARITY0_0_LD0_OUTPUT_POLARITY_HIGH _MK_ENUM_CONST(0) +#define DC_COM_PIN_OUTPUT_POLARITY0_0_LD0_OUTPUT_POLARITY_LOW _MK_ENUM_CONST(1) + +#define DC_COM_PIN_OUTPUT_POLARITY0_0_LD1_OUTPUT_POLARITY_SHIFT _MK_SHIFT_CONST(2) +#define DC_COM_PIN_OUTPUT_POLARITY0_0_LD1_OUTPUT_POLARITY_FIELD _MK_FIELD_CONST(0x1, DC_COM_PIN_OUTPUT_POLARITY0_0_LD1_OUTPUT_POLARITY_SHIFT) +#define DC_COM_PIN_OUTPUT_POLARITY0_0_LD1_OUTPUT_POLARITY_RANGE 2:2 +#define DC_COM_PIN_OUTPUT_POLARITY0_0_LD1_OUTPUT_POLARITY_WOFFSET 0x0 +#define DC_COM_PIN_OUTPUT_POLARITY0_0_LD1_OUTPUT_POLARITY_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_POLARITY0_0_LD1_OUTPUT_POLARITY_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_COM_PIN_OUTPUT_POLARITY0_0_LD1_OUTPUT_POLARITY_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_POLARITY0_0_LD1_OUTPUT_POLARITY_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_POLARITY0_0_LD1_OUTPUT_POLARITY_HIGH _MK_ENUM_CONST(0) +#define DC_COM_PIN_OUTPUT_POLARITY0_0_LD1_OUTPUT_POLARITY_LOW _MK_ENUM_CONST(1) + +#define DC_COM_PIN_OUTPUT_POLARITY0_0_LD2_OUTPUT_POLARITY_SHIFT _MK_SHIFT_CONST(4) +#define DC_COM_PIN_OUTPUT_POLARITY0_0_LD2_OUTPUT_POLARITY_FIELD _MK_FIELD_CONST(0x1, DC_COM_PIN_OUTPUT_POLARITY0_0_LD2_OUTPUT_POLARITY_SHIFT) +#define DC_COM_PIN_OUTPUT_POLARITY0_0_LD2_OUTPUT_POLARITY_RANGE 4:4 +#define DC_COM_PIN_OUTPUT_POLARITY0_0_LD2_OUTPUT_POLARITY_WOFFSET 0x0 +#define DC_COM_PIN_OUTPUT_POLARITY0_0_LD2_OUTPUT_POLARITY_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_POLARITY0_0_LD2_OUTPUT_POLARITY_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_COM_PIN_OUTPUT_POLARITY0_0_LD2_OUTPUT_POLARITY_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_POLARITY0_0_LD2_OUTPUT_POLARITY_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_POLARITY0_0_LD2_OUTPUT_POLARITY_HIGH _MK_ENUM_CONST(0) +#define DC_COM_PIN_OUTPUT_POLARITY0_0_LD2_OUTPUT_POLARITY_LOW _MK_ENUM_CONST(1) + +#define DC_COM_PIN_OUTPUT_POLARITY0_0_LD3_OUTPUT_POLARITY_SHIFT _MK_SHIFT_CONST(6) +#define DC_COM_PIN_OUTPUT_POLARITY0_0_LD3_OUTPUT_POLARITY_FIELD _MK_FIELD_CONST(0x1, DC_COM_PIN_OUTPUT_POLARITY0_0_LD3_OUTPUT_POLARITY_SHIFT) +#define DC_COM_PIN_OUTPUT_POLARITY0_0_LD3_OUTPUT_POLARITY_RANGE 6:6 +#define DC_COM_PIN_OUTPUT_POLARITY0_0_LD3_OUTPUT_POLARITY_WOFFSET 0x0 +#define DC_COM_PIN_OUTPUT_POLARITY0_0_LD3_OUTPUT_POLARITY_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_POLARITY0_0_LD3_OUTPUT_POLARITY_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_COM_PIN_OUTPUT_POLARITY0_0_LD3_OUTPUT_POLARITY_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_POLARITY0_0_LD3_OUTPUT_POLARITY_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_POLARITY0_0_LD3_OUTPUT_POLARITY_HIGH _MK_ENUM_CONST(0) +#define DC_COM_PIN_OUTPUT_POLARITY0_0_LD3_OUTPUT_POLARITY_LOW _MK_ENUM_CONST(1) + +#define DC_COM_PIN_OUTPUT_POLARITY0_0_LD4_OUTPUT_POLARITY_SHIFT _MK_SHIFT_CONST(8) +#define DC_COM_PIN_OUTPUT_POLARITY0_0_LD4_OUTPUT_POLARITY_FIELD _MK_FIELD_CONST(0x1, DC_COM_PIN_OUTPUT_POLARITY0_0_LD4_OUTPUT_POLARITY_SHIFT) +#define DC_COM_PIN_OUTPUT_POLARITY0_0_LD4_OUTPUT_POLARITY_RANGE 8:8 +#define DC_COM_PIN_OUTPUT_POLARITY0_0_LD4_OUTPUT_POLARITY_WOFFSET 0x0 +#define DC_COM_PIN_OUTPUT_POLARITY0_0_LD4_OUTPUT_POLARITY_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_POLARITY0_0_LD4_OUTPUT_POLARITY_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_COM_PIN_OUTPUT_POLARITY0_0_LD4_OUTPUT_POLARITY_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_POLARITY0_0_LD4_OUTPUT_POLARITY_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_POLARITY0_0_LD4_OUTPUT_POLARITY_HIGH _MK_ENUM_CONST(0) +#define DC_COM_PIN_OUTPUT_POLARITY0_0_LD4_OUTPUT_POLARITY_LOW _MK_ENUM_CONST(1) + +#define DC_COM_PIN_OUTPUT_POLARITY0_0_LD5_OUTPUT_POLARITY_SHIFT _MK_SHIFT_CONST(10) +#define DC_COM_PIN_OUTPUT_POLARITY0_0_LD5_OUTPUT_POLARITY_FIELD _MK_FIELD_CONST(0x1, DC_COM_PIN_OUTPUT_POLARITY0_0_LD5_OUTPUT_POLARITY_SHIFT) +#define DC_COM_PIN_OUTPUT_POLARITY0_0_LD5_OUTPUT_POLARITY_RANGE 10:10 +#define DC_COM_PIN_OUTPUT_POLARITY0_0_LD5_OUTPUT_POLARITY_WOFFSET 0x0 +#define DC_COM_PIN_OUTPUT_POLARITY0_0_LD5_OUTPUT_POLARITY_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_POLARITY0_0_LD5_OUTPUT_POLARITY_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_COM_PIN_OUTPUT_POLARITY0_0_LD5_OUTPUT_POLARITY_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_POLARITY0_0_LD5_OUTPUT_POLARITY_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_POLARITY0_0_LD5_OUTPUT_POLARITY_HIGH _MK_ENUM_CONST(0) +#define DC_COM_PIN_OUTPUT_POLARITY0_0_LD5_OUTPUT_POLARITY_LOW _MK_ENUM_CONST(1) + +#define DC_COM_PIN_OUTPUT_POLARITY0_0_LD6_OUTPUT_POLARITY_SHIFT _MK_SHIFT_CONST(12) +#define DC_COM_PIN_OUTPUT_POLARITY0_0_LD6_OUTPUT_POLARITY_FIELD _MK_FIELD_CONST(0x1, DC_COM_PIN_OUTPUT_POLARITY0_0_LD6_OUTPUT_POLARITY_SHIFT) +#define DC_COM_PIN_OUTPUT_POLARITY0_0_LD6_OUTPUT_POLARITY_RANGE 12:12 +#define DC_COM_PIN_OUTPUT_POLARITY0_0_LD6_OUTPUT_POLARITY_WOFFSET 0x0 +#define DC_COM_PIN_OUTPUT_POLARITY0_0_LD6_OUTPUT_POLARITY_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_POLARITY0_0_LD6_OUTPUT_POLARITY_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_COM_PIN_OUTPUT_POLARITY0_0_LD6_OUTPUT_POLARITY_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_POLARITY0_0_LD6_OUTPUT_POLARITY_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_POLARITY0_0_LD6_OUTPUT_POLARITY_HIGH _MK_ENUM_CONST(0) +#define DC_COM_PIN_OUTPUT_POLARITY0_0_LD6_OUTPUT_POLARITY_LOW _MK_ENUM_CONST(1) + +#define DC_COM_PIN_OUTPUT_POLARITY0_0_LD7_OUTPUT_POLARITY_SHIFT _MK_SHIFT_CONST(14) +#define DC_COM_PIN_OUTPUT_POLARITY0_0_LD7_OUTPUT_POLARITY_FIELD _MK_FIELD_CONST(0x1, DC_COM_PIN_OUTPUT_POLARITY0_0_LD7_OUTPUT_POLARITY_SHIFT) +#define DC_COM_PIN_OUTPUT_POLARITY0_0_LD7_OUTPUT_POLARITY_RANGE 14:14 +#define DC_COM_PIN_OUTPUT_POLARITY0_0_LD7_OUTPUT_POLARITY_WOFFSET 0x0 +#define DC_COM_PIN_OUTPUT_POLARITY0_0_LD7_OUTPUT_POLARITY_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_POLARITY0_0_LD7_OUTPUT_POLARITY_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_COM_PIN_OUTPUT_POLARITY0_0_LD7_OUTPUT_POLARITY_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_POLARITY0_0_LD7_OUTPUT_POLARITY_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_POLARITY0_0_LD7_OUTPUT_POLARITY_HIGH _MK_ENUM_CONST(0) +#define DC_COM_PIN_OUTPUT_POLARITY0_0_LD7_OUTPUT_POLARITY_LOW _MK_ENUM_CONST(1) + +#define DC_COM_PIN_OUTPUT_POLARITY0_0_LD8_OUTPUT_POLARITY_SHIFT _MK_SHIFT_CONST(16) +#define DC_COM_PIN_OUTPUT_POLARITY0_0_LD8_OUTPUT_POLARITY_FIELD _MK_FIELD_CONST(0x1, DC_COM_PIN_OUTPUT_POLARITY0_0_LD8_OUTPUT_POLARITY_SHIFT) +#define DC_COM_PIN_OUTPUT_POLARITY0_0_LD8_OUTPUT_POLARITY_RANGE 16:16 +#define DC_COM_PIN_OUTPUT_POLARITY0_0_LD8_OUTPUT_POLARITY_WOFFSET 0x0 +#define DC_COM_PIN_OUTPUT_POLARITY0_0_LD8_OUTPUT_POLARITY_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_POLARITY0_0_LD8_OUTPUT_POLARITY_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_COM_PIN_OUTPUT_POLARITY0_0_LD8_OUTPUT_POLARITY_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_POLARITY0_0_LD8_OUTPUT_POLARITY_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_POLARITY0_0_LD8_OUTPUT_POLARITY_HIGH _MK_ENUM_CONST(0) +#define DC_COM_PIN_OUTPUT_POLARITY0_0_LD8_OUTPUT_POLARITY_LOW _MK_ENUM_CONST(1) + +#define DC_COM_PIN_OUTPUT_POLARITY0_0_LD9_OUTPUT_POLARITY_SHIFT _MK_SHIFT_CONST(18) +#define DC_COM_PIN_OUTPUT_POLARITY0_0_LD9_OUTPUT_POLARITY_FIELD _MK_FIELD_CONST(0x1, DC_COM_PIN_OUTPUT_POLARITY0_0_LD9_OUTPUT_POLARITY_SHIFT) +#define DC_COM_PIN_OUTPUT_POLARITY0_0_LD9_OUTPUT_POLARITY_RANGE 18:18 +#define DC_COM_PIN_OUTPUT_POLARITY0_0_LD9_OUTPUT_POLARITY_WOFFSET 0x0 +#define DC_COM_PIN_OUTPUT_POLARITY0_0_LD9_OUTPUT_POLARITY_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_POLARITY0_0_LD9_OUTPUT_POLARITY_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_COM_PIN_OUTPUT_POLARITY0_0_LD9_OUTPUT_POLARITY_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_POLARITY0_0_LD9_OUTPUT_POLARITY_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_POLARITY0_0_LD9_OUTPUT_POLARITY_HIGH _MK_ENUM_CONST(0) +#define DC_COM_PIN_OUTPUT_POLARITY0_0_LD9_OUTPUT_POLARITY_LOW _MK_ENUM_CONST(1) + +#define DC_COM_PIN_OUTPUT_POLARITY0_0_LD10_OUTPUT_POLARITY_SHIFT _MK_SHIFT_CONST(20) +#define DC_COM_PIN_OUTPUT_POLARITY0_0_LD10_OUTPUT_POLARITY_FIELD _MK_FIELD_CONST(0x1, DC_COM_PIN_OUTPUT_POLARITY0_0_LD10_OUTPUT_POLARITY_SHIFT) +#define DC_COM_PIN_OUTPUT_POLARITY0_0_LD10_OUTPUT_POLARITY_RANGE 20:20 +#define DC_COM_PIN_OUTPUT_POLARITY0_0_LD10_OUTPUT_POLARITY_WOFFSET 0x0 +#define DC_COM_PIN_OUTPUT_POLARITY0_0_LD10_OUTPUT_POLARITY_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_POLARITY0_0_LD10_OUTPUT_POLARITY_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_COM_PIN_OUTPUT_POLARITY0_0_LD10_OUTPUT_POLARITY_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_POLARITY0_0_LD10_OUTPUT_POLARITY_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_POLARITY0_0_LD10_OUTPUT_POLARITY_HIGH _MK_ENUM_CONST(0) +#define DC_COM_PIN_OUTPUT_POLARITY0_0_LD10_OUTPUT_POLARITY_LOW _MK_ENUM_CONST(1) + +#define DC_COM_PIN_OUTPUT_POLARITY0_0_LD11_OUTPUT_POLARITY_SHIFT _MK_SHIFT_CONST(22) +#define DC_COM_PIN_OUTPUT_POLARITY0_0_LD11_OUTPUT_POLARITY_FIELD _MK_FIELD_CONST(0x1, DC_COM_PIN_OUTPUT_POLARITY0_0_LD11_OUTPUT_POLARITY_SHIFT) +#define DC_COM_PIN_OUTPUT_POLARITY0_0_LD11_OUTPUT_POLARITY_RANGE 22:22 +#define DC_COM_PIN_OUTPUT_POLARITY0_0_LD11_OUTPUT_POLARITY_WOFFSET 0x0 +#define DC_COM_PIN_OUTPUT_POLARITY0_0_LD11_OUTPUT_POLARITY_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_POLARITY0_0_LD11_OUTPUT_POLARITY_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_COM_PIN_OUTPUT_POLARITY0_0_LD11_OUTPUT_POLARITY_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_POLARITY0_0_LD11_OUTPUT_POLARITY_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_POLARITY0_0_LD11_OUTPUT_POLARITY_HIGH _MK_ENUM_CONST(0) +#define DC_COM_PIN_OUTPUT_POLARITY0_0_LD11_OUTPUT_POLARITY_LOW _MK_ENUM_CONST(1) + +#define DC_COM_PIN_OUTPUT_POLARITY0_0_LD12_OUTPUT_POLARITY_SHIFT _MK_SHIFT_CONST(24) +#define DC_COM_PIN_OUTPUT_POLARITY0_0_LD12_OUTPUT_POLARITY_FIELD _MK_FIELD_CONST(0x1, DC_COM_PIN_OUTPUT_POLARITY0_0_LD12_OUTPUT_POLARITY_SHIFT) +#define DC_COM_PIN_OUTPUT_POLARITY0_0_LD12_OUTPUT_POLARITY_RANGE 24:24 +#define DC_COM_PIN_OUTPUT_POLARITY0_0_LD12_OUTPUT_POLARITY_WOFFSET 0x0 +#define DC_COM_PIN_OUTPUT_POLARITY0_0_LD12_OUTPUT_POLARITY_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_POLARITY0_0_LD12_OUTPUT_POLARITY_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_COM_PIN_OUTPUT_POLARITY0_0_LD12_OUTPUT_POLARITY_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_POLARITY0_0_LD12_OUTPUT_POLARITY_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_POLARITY0_0_LD12_OUTPUT_POLARITY_HIGH _MK_ENUM_CONST(0) +#define DC_COM_PIN_OUTPUT_POLARITY0_0_LD12_OUTPUT_POLARITY_LOW _MK_ENUM_CONST(1) + +#define DC_COM_PIN_OUTPUT_POLARITY0_0_LD13_OUTPUT_POLARITY_SHIFT _MK_SHIFT_CONST(26) +#define DC_COM_PIN_OUTPUT_POLARITY0_0_LD13_OUTPUT_POLARITY_FIELD _MK_FIELD_CONST(0x1, DC_COM_PIN_OUTPUT_POLARITY0_0_LD13_OUTPUT_POLARITY_SHIFT) +#define DC_COM_PIN_OUTPUT_POLARITY0_0_LD13_OUTPUT_POLARITY_RANGE 26:26 +#define DC_COM_PIN_OUTPUT_POLARITY0_0_LD13_OUTPUT_POLARITY_WOFFSET 0x0 +#define DC_COM_PIN_OUTPUT_POLARITY0_0_LD13_OUTPUT_POLARITY_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_POLARITY0_0_LD13_OUTPUT_POLARITY_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_COM_PIN_OUTPUT_POLARITY0_0_LD13_OUTPUT_POLARITY_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_POLARITY0_0_LD13_OUTPUT_POLARITY_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_POLARITY0_0_LD13_OUTPUT_POLARITY_HIGH _MK_ENUM_CONST(0) +#define DC_COM_PIN_OUTPUT_POLARITY0_0_LD13_OUTPUT_POLARITY_LOW _MK_ENUM_CONST(1) + +#define DC_COM_PIN_OUTPUT_POLARITY0_0_LD14_OUTPUT_POLARITY_SHIFT _MK_SHIFT_CONST(28) +#define DC_COM_PIN_OUTPUT_POLARITY0_0_LD14_OUTPUT_POLARITY_FIELD _MK_FIELD_CONST(0x1, DC_COM_PIN_OUTPUT_POLARITY0_0_LD14_OUTPUT_POLARITY_SHIFT) +#define DC_COM_PIN_OUTPUT_POLARITY0_0_LD14_OUTPUT_POLARITY_RANGE 28:28 +#define DC_COM_PIN_OUTPUT_POLARITY0_0_LD14_OUTPUT_POLARITY_WOFFSET 0x0 +#define DC_COM_PIN_OUTPUT_POLARITY0_0_LD14_OUTPUT_POLARITY_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_POLARITY0_0_LD14_OUTPUT_POLARITY_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_COM_PIN_OUTPUT_POLARITY0_0_LD14_OUTPUT_POLARITY_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_POLARITY0_0_LD14_OUTPUT_POLARITY_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_POLARITY0_0_LD14_OUTPUT_POLARITY_HIGH _MK_ENUM_CONST(0) +#define DC_COM_PIN_OUTPUT_POLARITY0_0_LD14_OUTPUT_POLARITY_LOW _MK_ENUM_CONST(1) + +#define DC_COM_PIN_OUTPUT_POLARITY0_0_LD15_OUTPUT_POLARITY_SHIFT _MK_SHIFT_CONST(30) +#define DC_COM_PIN_OUTPUT_POLARITY0_0_LD15_OUTPUT_POLARITY_FIELD _MK_FIELD_CONST(0x1, DC_COM_PIN_OUTPUT_POLARITY0_0_LD15_OUTPUT_POLARITY_SHIFT) +#define DC_COM_PIN_OUTPUT_POLARITY0_0_LD15_OUTPUT_POLARITY_RANGE 30:30 +#define DC_COM_PIN_OUTPUT_POLARITY0_0_LD15_OUTPUT_POLARITY_WOFFSET 0x0 +#define DC_COM_PIN_OUTPUT_POLARITY0_0_LD15_OUTPUT_POLARITY_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_POLARITY0_0_LD15_OUTPUT_POLARITY_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_COM_PIN_OUTPUT_POLARITY0_0_LD15_OUTPUT_POLARITY_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_POLARITY0_0_LD15_OUTPUT_POLARITY_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_POLARITY0_0_LD15_OUTPUT_POLARITY_HIGH _MK_ENUM_CONST(0) +#define DC_COM_PIN_OUTPUT_POLARITY0_0_LD15_OUTPUT_POLARITY_LOW _MK_ENUM_CONST(1) + + +// Register DC_COM_PIN_OUTPUT_POLARITY1_0 +#define DC_COM_PIN_OUTPUT_POLARITY1_0 _MK_ADDR_CONST(0x307) +#define DC_COM_PIN_OUTPUT_POLARITY1_0_SECURE 0x0 +#define DC_COM_PIN_OUTPUT_POLARITY1_0_WORD_COUNT 0x1 +#define DC_COM_PIN_OUTPUT_POLARITY1_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_POLARITY1_0_RESET_MASK _MK_MASK_CONST(0x55150005) +#define DC_COM_PIN_OUTPUT_POLARITY1_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_POLARITY1_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_POLARITY1_0_READ_MASK _MK_MASK_CONST(0x55150005) +#define DC_COM_PIN_OUTPUT_POLARITY1_0_WRITE_MASK _MK_MASK_CONST(0x55150005) +#define DC_COM_PIN_OUTPUT_POLARITY1_0_LD16_OUTPUT_POLARITY_SHIFT _MK_SHIFT_CONST(0) +#define DC_COM_PIN_OUTPUT_POLARITY1_0_LD16_OUTPUT_POLARITY_FIELD _MK_FIELD_CONST(0x1, DC_COM_PIN_OUTPUT_POLARITY1_0_LD16_OUTPUT_POLARITY_SHIFT) +#define DC_COM_PIN_OUTPUT_POLARITY1_0_LD16_OUTPUT_POLARITY_RANGE 0:0 +#define DC_COM_PIN_OUTPUT_POLARITY1_0_LD16_OUTPUT_POLARITY_WOFFSET 0x0 +#define DC_COM_PIN_OUTPUT_POLARITY1_0_LD16_OUTPUT_POLARITY_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_POLARITY1_0_LD16_OUTPUT_POLARITY_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_COM_PIN_OUTPUT_POLARITY1_0_LD16_OUTPUT_POLARITY_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_POLARITY1_0_LD16_OUTPUT_POLARITY_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_POLARITY1_0_LD16_OUTPUT_POLARITY_HIGH _MK_ENUM_CONST(0) +#define DC_COM_PIN_OUTPUT_POLARITY1_0_LD16_OUTPUT_POLARITY_LOW _MK_ENUM_CONST(1) + +#define DC_COM_PIN_OUTPUT_POLARITY1_0_LD17_OUTPUT_POLARITY_SHIFT _MK_SHIFT_CONST(2) +#define DC_COM_PIN_OUTPUT_POLARITY1_0_LD17_OUTPUT_POLARITY_FIELD _MK_FIELD_CONST(0x1, DC_COM_PIN_OUTPUT_POLARITY1_0_LD17_OUTPUT_POLARITY_SHIFT) +#define DC_COM_PIN_OUTPUT_POLARITY1_0_LD17_OUTPUT_POLARITY_RANGE 2:2 +#define DC_COM_PIN_OUTPUT_POLARITY1_0_LD17_OUTPUT_POLARITY_WOFFSET 0x0 +#define DC_COM_PIN_OUTPUT_POLARITY1_0_LD17_OUTPUT_POLARITY_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_POLARITY1_0_LD17_OUTPUT_POLARITY_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_COM_PIN_OUTPUT_POLARITY1_0_LD17_OUTPUT_POLARITY_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_POLARITY1_0_LD17_OUTPUT_POLARITY_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_POLARITY1_0_LD17_OUTPUT_POLARITY_HIGH _MK_ENUM_CONST(0) +#define DC_COM_PIN_OUTPUT_POLARITY1_0_LD17_OUTPUT_POLARITY_LOW _MK_ENUM_CONST(1) + +#define DC_COM_PIN_OUTPUT_POLARITY1_0_LPW0_OUTPUT_POLARITY_SHIFT _MK_SHIFT_CONST(16) +#define DC_COM_PIN_OUTPUT_POLARITY1_0_LPW0_OUTPUT_POLARITY_FIELD _MK_FIELD_CONST(0x1, DC_COM_PIN_OUTPUT_POLARITY1_0_LPW0_OUTPUT_POLARITY_SHIFT) +#define DC_COM_PIN_OUTPUT_POLARITY1_0_LPW0_OUTPUT_POLARITY_RANGE 16:16 +#define DC_COM_PIN_OUTPUT_POLARITY1_0_LPW0_OUTPUT_POLARITY_WOFFSET 0x0 +#define DC_COM_PIN_OUTPUT_POLARITY1_0_LPW0_OUTPUT_POLARITY_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_POLARITY1_0_LPW0_OUTPUT_POLARITY_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_COM_PIN_OUTPUT_POLARITY1_0_LPW0_OUTPUT_POLARITY_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_POLARITY1_0_LPW0_OUTPUT_POLARITY_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_POLARITY1_0_LPW0_OUTPUT_POLARITY_HIGH _MK_ENUM_CONST(0) +#define DC_COM_PIN_OUTPUT_POLARITY1_0_LPW0_OUTPUT_POLARITY_LOW _MK_ENUM_CONST(1) + +#define DC_COM_PIN_OUTPUT_POLARITY1_0_LPW1_OUTPUT_POLARITY_SHIFT _MK_SHIFT_CONST(18) +#define DC_COM_PIN_OUTPUT_POLARITY1_0_LPW1_OUTPUT_POLARITY_FIELD _MK_FIELD_CONST(0x1, DC_COM_PIN_OUTPUT_POLARITY1_0_LPW1_OUTPUT_POLARITY_SHIFT) +#define DC_COM_PIN_OUTPUT_POLARITY1_0_LPW1_OUTPUT_POLARITY_RANGE 18:18 +#define DC_COM_PIN_OUTPUT_POLARITY1_0_LPW1_OUTPUT_POLARITY_WOFFSET 0x0 +#define DC_COM_PIN_OUTPUT_POLARITY1_0_LPW1_OUTPUT_POLARITY_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_POLARITY1_0_LPW1_OUTPUT_POLARITY_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_COM_PIN_OUTPUT_POLARITY1_0_LPW1_OUTPUT_POLARITY_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_POLARITY1_0_LPW1_OUTPUT_POLARITY_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_POLARITY1_0_LPW1_OUTPUT_POLARITY_HIGH _MK_ENUM_CONST(0) +#define DC_COM_PIN_OUTPUT_POLARITY1_0_LPW1_OUTPUT_POLARITY_LOW _MK_ENUM_CONST(1) + +#define DC_COM_PIN_OUTPUT_POLARITY1_0_LPW2_OUTPUT_POLARITY_SHIFT _MK_SHIFT_CONST(20) +#define DC_COM_PIN_OUTPUT_POLARITY1_0_LPW2_OUTPUT_POLARITY_FIELD _MK_FIELD_CONST(0x1, DC_COM_PIN_OUTPUT_POLARITY1_0_LPW2_OUTPUT_POLARITY_SHIFT) +#define DC_COM_PIN_OUTPUT_POLARITY1_0_LPW2_OUTPUT_POLARITY_RANGE 20:20 +#define DC_COM_PIN_OUTPUT_POLARITY1_0_LPW2_OUTPUT_POLARITY_WOFFSET 0x0 +#define DC_COM_PIN_OUTPUT_POLARITY1_0_LPW2_OUTPUT_POLARITY_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_POLARITY1_0_LPW2_OUTPUT_POLARITY_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_COM_PIN_OUTPUT_POLARITY1_0_LPW2_OUTPUT_POLARITY_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_POLARITY1_0_LPW2_OUTPUT_POLARITY_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_POLARITY1_0_LPW2_OUTPUT_POLARITY_HIGH _MK_ENUM_CONST(0) +#define DC_COM_PIN_OUTPUT_POLARITY1_0_LPW2_OUTPUT_POLARITY_LOW _MK_ENUM_CONST(1) + +#define DC_COM_PIN_OUTPUT_POLARITY1_0_LSC0_OUTPUT_POLARITY_SHIFT _MK_SHIFT_CONST(24) +#define DC_COM_PIN_OUTPUT_POLARITY1_0_LSC0_OUTPUT_POLARITY_FIELD _MK_FIELD_CONST(0x1, DC_COM_PIN_OUTPUT_POLARITY1_0_LSC0_OUTPUT_POLARITY_SHIFT) +#define DC_COM_PIN_OUTPUT_POLARITY1_0_LSC0_OUTPUT_POLARITY_RANGE 24:24 +#define DC_COM_PIN_OUTPUT_POLARITY1_0_LSC0_OUTPUT_POLARITY_WOFFSET 0x0 +#define DC_COM_PIN_OUTPUT_POLARITY1_0_LSC0_OUTPUT_POLARITY_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_POLARITY1_0_LSC0_OUTPUT_POLARITY_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_COM_PIN_OUTPUT_POLARITY1_0_LSC0_OUTPUT_POLARITY_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_POLARITY1_0_LSC0_OUTPUT_POLARITY_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_POLARITY1_0_LSC0_OUTPUT_POLARITY_HIGH _MK_ENUM_CONST(0) +#define DC_COM_PIN_OUTPUT_POLARITY1_0_LSC0_OUTPUT_POLARITY_LOW _MK_ENUM_CONST(1) + +#define DC_COM_PIN_OUTPUT_POLARITY1_0_LSC1_OUTPUT_POLARITY_SHIFT _MK_SHIFT_CONST(26) +#define DC_COM_PIN_OUTPUT_POLARITY1_0_LSC1_OUTPUT_POLARITY_FIELD _MK_FIELD_CONST(0x1, DC_COM_PIN_OUTPUT_POLARITY1_0_LSC1_OUTPUT_POLARITY_SHIFT) +#define DC_COM_PIN_OUTPUT_POLARITY1_0_LSC1_OUTPUT_POLARITY_RANGE 26:26 +#define DC_COM_PIN_OUTPUT_POLARITY1_0_LSC1_OUTPUT_POLARITY_WOFFSET 0x0 +#define DC_COM_PIN_OUTPUT_POLARITY1_0_LSC1_OUTPUT_POLARITY_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_POLARITY1_0_LSC1_OUTPUT_POLARITY_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_COM_PIN_OUTPUT_POLARITY1_0_LSC1_OUTPUT_POLARITY_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_POLARITY1_0_LSC1_OUTPUT_POLARITY_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_POLARITY1_0_LSC1_OUTPUT_POLARITY_HIGH _MK_ENUM_CONST(0) +#define DC_COM_PIN_OUTPUT_POLARITY1_0_LSC1_OUTPUT_POLARITY_LOW _MK_ENUM_CONST(1) + +#define DC_COM_PIN_OUTPUT_POLARITY1_0_LVS_OUTPUT_POLARITY_SHIFT _MK_SHIFT_CONST(28) +#define DC_COM_PIN_OUTPUT_POLARITY1_0_LVS_OUTPUT_POLARITY_FIELD _MK_FIELD_CONST(0x1, DC_COM_PIN_OUTPUT_POLARITY1_0_LVS_OUTPUT_POLARITY_SHIFT) +#define DC_COM_PIN_OUTPUT_POLARITY1_0_LVS_OUTPUT_POLARITY_RANGE 28:28 +#define DC_COM_PIN_OUTPUT_POLARITY1_0_LVS_OUTPUT_POLARITY_WOFFSET 0x0 +#define DC_COM_PIN_OUTPUT_POLARITY1_0_LVS_OUTPUT_POLARITY_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_POLARITY1_0_LVS_OUTPUT_POLARITY_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_COM_PIN_OUTPUT_POLARITY1_0_LVS_OUTPUT_POLARITY_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_POLARITY1_0_LVS_OUTPUT_POLARITY_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_POLARITY1_0_LVS_OUTPUT_POLARITY_HIGH _MK_ENUM_CONST(0) +#define DC_COM_PIN_OUTPUT_POLARITY1_0_LVS_OUTPUT_POLARITY_LOW _MK_ENUM_CONST(1) + +#define DC_COM_PIN_OUTPUT_POLARITY1_0_LHS_OUTPUT_POLARITY_SHIFT _MK_SHIFT_CONST(30) +#define DC_COM_PIN_OUTPUT_POLARITY1_0_LHS_OUTPUT_POLARITY_FIELD _MK_FIELD_CONST(0x1, DC_COM_PIN_OUTPUT_POLARITY1_0_LHS_OUTPUT_POLARITY_SHIFT) +#define DC_COM_PIN_OUTPUT_POLARITY1_0_LHS_OUTPUT_POLARITY_RANGE 30:30 +#define DC_COM_PIN_OUTPUT_POLARITY1_0_LHS_OUTPUT_POLARITY_WOFFSET 0x0 +#define DC_COM_PIN_OUTPUT_POLARITY1_0_LHS_OUTPUT_POLARITY_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_POLARITY1_0_LHS_OUTPUT_POLARITY_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_COM_PIN_OUTPUT_POLARITY1_0_LHS_OUTPUT_POLARITY_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_POLARITY1_0_LHS_OUTPUT_POLARITY_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_POLARITY1_0_LHS_OUTPUT_POLARITY_HIGH _MK_ENUM_CONST(0) +#define DC_COM_PIN_OUTPUT_POLARITY1_0_LHS_OUTPUT_POLARITY_LOW _MK_ENUM_CONST(1) + + +// Register DC_COM_PIN_OUTPUT_POLARITY2_0 +#define DC_COM_PIN_OUTPUT_POLARITY2_0 _MK_ADDR_CONST(0x308) +#define DC_COM_PIN_OUTPUT_POLARITY2_0_SECURE 0x0 +#define DC_COM_PIN_OUTPUT_POLARITY2_0_WORD_COUNT 0x1 +#define DC_COM_PIN_OUTPUT_POLARITY2_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_POLARITY2_0_RESET_MASK _MK_MASK_CONST(0x550515) +#define DC_COM_PIN_OUTPUT_POLARITY2_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_POLARITY2_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_POLARITY2_0_READ_MASK _MK_MASK_CONST(0x550515) +#define DC_COM_PIN_OUTPUT_POLARITY2_0_WRITE_MASK _MK_MASK_CONST(0x550515) +#define DC_COM_PIN_OUTPUT_POLARITY2_0_LHP0_OUTPUT_POLARITY_SHIFT _MK_SHIFT_CONST(0) +#define DC_COM_PIN_OUTPUT_POLARITY2_0_LHP0_OUTPUT_POLARITY_FIELD _MK_FIELD_CONST(0x1, DC_COM_PIN_OUTPUT_POLARITY2_0_LHP0_OUTPUT_POLARITY_SHIFT) +#define DC_COM_PIN_OUTPUT_POLARITY2_0_LHP0_OUTPUT_POLARITY_RANGE 0:0 +#define DC_COM_PIN_OUTPUT_POLARITY2_0_LHP0_OUTPUT_POLARITY_WOFFSET 0x0 +#define DC_COM_PIN_OUTPUT_POLARITY2_0_LHP0_OUTPUT_POLARITY_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_POLARITY2_0_LHP0_OUTPUT_POLARITY_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_COM_PIN_OUTPUT_POLARITY2_0_LHP0_OUTPUT_POLARITY_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_POLARITY2_0_LHP0_OUTPUT_POLARITY_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_POLARITY2_0_LHP0_OUTPUT_POLARITY_HIGH _MK_ENUM_CONST(0) +#define DC_COM_PIN_OUTPUT_POLARITY2_0_LHP0_OUTPUT_POLARITY_LOW _MK_ENUM_CONST(1) + +#define DC_COM_PIN_OUTPUT_POLARITY2_0_LHP1_OUTPUT_POLARITY_SHIFT _MK_SHIFT_CONST(2) +#define DC_COM_PIN_OUTPUT_POLARITY2_0_LHP1_OUTPUT_POLARITY_FIELD _MK_FIELD_CONST(0x1, DC_COM_PIN_OUTPUT_POLARITY2_0_LHP1_OUTPUT_POLARITY_SHIFT) +#define DC_COM_PIN_OUTPUT_POLARITY2_0_LHP1_OUTPUT_POLARITY_RANGE 2:2 +#define DC_COM_PIN_OUTPUT_POLARITY2_0_LHP1_OUTPUT_POLARITY_WOFFSET 0x0 +#define DC_COM_PIN_OUTPUT_POLARITY2_0_LHP1_OUTPUT_POLARITY_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_POLARITY2_0_LHP1_OUTPUT_POLARITY_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_COM_PIN_OUTPUT_POLARITY2_0_LHP1_OUTPUT_POLARITY_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_POLARITY2_0_LHP1_OUTPUT_POLARITY_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_POLARITY2_0_LHP1_OUTPUT_POLARITY_HIGH _MK_ENUM_CONST(0) +#define DC_COM_PIN_OUTPUT_POLARITY2_0_LHP1_OUTPUT_POLARITY_LOW _MK_ENUM_CONST(1) + +#define DC_COM_PIN_OUTPUT_POLARITY2_0_LHP2_OUTPUT_POLARITY_SHIFT _MK_SHIFT_CONST(4) +#define DC_COM_PIN_OUTPUT_POLARITY2_0_LHP2_OUTPUT_POLARITY_FIELD _MK_FIELD_CONST(0x1, DC_COM_PIN_OUTPUT_POLARITY2_0_LHP2_OUTPUT_POLARITY_SHIFT) +#define DC_COM_PIN_OUTPUT_POLARITY2_0_LHP2_OUTPUT_POLARITY_RANGE 4:4 +#define DC_COM_PIN_OUTPUT_POLARITY2_0_LHP2_OUTPUT_POLARITY_WOFFSET 0x0 +#define DC_COM_PIN_OUTPUT_POLARITY2_0_LHP2_OUTPUT_POLARITY_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_POLARITY2_0_LHP2_OUTPUT_POLARITY_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_COM_PIN_OUTPUT_POLARITY2_0_LHP2_OUTPUT_POLARITY_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_POLARITY2_0_LHP2_OUTPUT_POLARITY_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_POLARITY2_0_LHP2_OUTPUT_POLARITY_HIGH _MK_ENUM_CONST(0) +#define DC_COM_PIN_OUTPUT_POLARITY2_0_LHP2_OUTPUT_POLARITY_LOW _MK_ENUM_CONST(1) + +#define DC_COM_PIN_OUTPUT_POLARITY2_0_LVP0_OUTPUT_POLARITY_SHIFT _MK_SHIFT_CONST(8) +#define DC_COM_PIN_OUTPUT_POLARITY2_0_LVP0_OUTPUT_POLARITY_FIELD _MK_FIELD_CONST(0x1, DC_COM_PIN_OUTPUT_POLARITY2_0_LVP0_OUTPUT_POLARITY_SHIFT) +#define DC_COM_PIN_OUTPUT_POLARITY2_0_LVP0_OUTPUT_POLARITY_RANGE 8:8 +#define DC_COM_PIN_OUTPUT_POLARITY2_0_LVP0_OUTPUT_POLARITY_WOFFSET 0x0 +#define DC_COM_PIN_OUTPUT_POLARITY2_0_LVP0_OUTPUT_POLARITY_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_POLARITY2_0_LVP0_OUTPUT_POLARITY_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_COM_PIN_OUTPUT_POLARITY2_0_LVP0_OUTPUT_POLARITY_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_POLARITY2_0_LVP0_OUTPUT_POLARITY_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_POLARITY2_0_LVP0_OUTPUT_POLARITY_HIGH _MK_ENUM_CONST(0) +#define DC_COM_PIN_OUTPUT_POLARITY2_0_LVP0_OUTPUT_POLARITY_LOW _MK_ENUM_CONST(1) + +#define DC_COM_PIN_OUTPUT_POLARITY2_0_LVP1_OUTPUT_POLARITY_SHIFT _MK_SHIFT_CONST(10) +#define DC_COM_PIN_OUTPUT_POLARITY2_0_LVP1_OUTPUT_POLARITY_FIELD _MK_FIELD_CONST(0x1, DC_COM_PIN_OUTPUT_POLARITY2_0_LVP1_OUTPUT_POLARITY_SHIFT) +#define DC_COM_PIN_OUTPUT_POLARITY2_0_LVP1_OUTPUT_POLARITY_RANGE 10:10 +#define DC_COM_PIN_OUTPUT_POLARITY2_0_LVP1_OUTPUT_POLARITY_WOFFSET 0x0 +#define DC_COM_PIN_OUTPUT_POLARITY2_0_LVP1_OUTPUT_POLARITY_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_POLARITY2_0_LVP1_OUTPUT_POLARITY_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_COM_PIN_OUTPUT_POLARITY2_0_LVP1_OUTPUT_POLARITY_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_POLARITY2_0_LVP1_OUTPUT_POLARITY_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_POLARITY2_0_LVP1_OUTPUT_POLARITY_HIGH _MK_ENUM_CONST(0) +#define DC_COM_PIN_OUTPUT_POLARITY2_0_LVP1_OUTPUT_POLARITY_LOW _MK_ENUM_CONST(1) + +#define DC_COM_PIN_OUTPUT_POLARITY2_0_LM0_OUTPUT_POLARITY_SHIFT _MK_SHIFT_CONST(16) +#define DC_COM_PIN_OUTPUT_POLARITY2_0_LM0_OUTPUT_POLARITY_FIELD _MK_FIELD_CONST(0x1, DC_COM_PIN_OUTPUT_POLARITY2_0_LM0_OUTPUT_POLARITY_SHIFT) +#define DC_COM_PIN_OUTPUT_POLARITY2_0_LM0_OUTPUT_POLARITY_RANGE 16:16 +#define DC_COM_PIN_OUTPUT_POLARITY2_0_LM0_OUTPUT_POLARITY_WOFFSET 0x0 +#define DC_COM_PIN_OUTPUT_POLARITY2_0_LM0_OUTPUT_POLARITY_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_POLARITY2_0_LM0_OUTPUT_POLARITY_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_COM_PIN_OUTPUT_POLARITY2_0_LM0_OUTPUT_POLARITY_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_POLARITY2_0_LM0_OUTPUT_POLARITY_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_POLARITY2_0_LM0_OUTPUT_POLARITY_HIGH _MK_ENUM_CONST(0) +#define DC_COM_PIN_OUTPUT_POLARITY2_0_LM0_OUTPUT_POLARITY_LOW _MK_ENUM_CONST(1) + +#define DC_COM_PIN_OUTPUT_POLARITY2_0_LM1_OUTPUT_POLARITY_SHIFT _MK_SHIFT_CONST(18) +#define DC_COM_PIN_OUTPUT_POLARITY2_0_LM1_OUTPUT_POLARITY_FIELD _MK_FIELD_CONST(0x1, DC_COM_PIN_OUTPUT_POLARITY2_0_LM1_OUTPUT_POLARITY_SHIFT) +#define DC_COM_PIN_OUTPUT_POLARITY2_0_LM1_OUTPUT_POLARITY_RANGE 18:18 +#define DC_COM_PIN_OUTPUT_POLARITY2_0_LM1_OUTPUT_POLARITY_WOFFSET 0x0 +#define DC_COM_PIN_OUTPUT_POLARITY2_0_LM1_OUTPUT_POLARITY_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_POLARITY2_0_LM1_OUTPUT_POLARITY_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_COM_PIN_OUTPUT_POLARITY2_0_LM1_OUTPUT_POLARITY_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_POLARITY2_0_LM1_OUTPUT_POLARITY_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_POLARITY2_0_LM1_OUTPUT_POLARITY_HIGH _MK_ENUM_CONST(0) +#define DC_COM_PIN_OUTPUT_POLARITY2_0_LM1_OUTPUT_POLARITY_LOW _MK_ENUM_CONST(1) + +#define DC_COM_PIN_OUTPUT_POLARITY2_0_LDI_OUTPUT_POLARITY_SHIFT _MK_SHIFT_CONST(20) +#define DC_COM_PIN_OUTPUT_POLARITY2_0_LDI_OUTPUT_POLARITY_FIELD _MK_FIELD_CONST(0x1, DC_COM_PIN_OUTPUT_POLARITY2_0_LDI_OUTPUT_POLARITY_SHIFT) +#define DC_COM_PIN_OUTPUT_POLARITY2_0_LDI_OUTPUT_POLARITY_RANGE 20:20 +#define DC_COM_PIN_OUTPUT_POLARITY2_0_LDI_OUTPUT_POLARITY_WOFFSET 0x0 +#define DC_COM_PIN_OUTPUT_POLARITY2_0_LDI_OUTPUT_POLARITY_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_POLARITY2_0_LDI_OUTPUT_POLARITY_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_COM_PIN_OUTPUT_POLARITY2_0_LDI_OUTPUT_POLARITY_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_POLARITY2_0_LDI_OUTPUT_POLARITY_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_POLARITY2_0_LDI_OUTPUT_POLARITY_HIGH _MK_ENUM_CONST(0) +#define DC_COM_PIN_OUTPUT_POLARITY2_0_LDI_OUTPUT_POLARITY_LOW _MK_ENUM_CONST(1) + +#define DC_COM_PIN_OUTPUT_POLARITY2_0_LPP_OUTPUT_POLARITY_SHIFT _MK_SHIFT_CONST(22) +#define DC_COM_PIN_OUTPUT_POLARITY2_0_LPP_OUTPUT_POLARITY_FIELD _MK_FIELD_CONST(0x1, DC_COM_PIN_OUTPUT_POLARITY2_0_LPP_OUTPUT_POLARITY_SHIFT) +#define DC_COM_PIN_OUTPUT_POLARITY2_0_LPP_OUTPUT_POLARITY_RANGE 22:22 +#define DC_COM_PIN_OUTPUT_POLARITY2_0_LPP_OUTPUT_POLARITY_WOFFSET 0x0 +#define DC_COM_PIN_OUTPUT_POLARITY2_0_LPP_OUTPUT_POLARITY_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_POLARITY2_0_LPP_OUTPUT_POLARITY_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_COM_PIN_OUTPUT_POLARITY2_0_LPP_OUTPUT_POLARITY_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_POLARITY2_0_LPP_OUTPUT_POLARITY_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_POLARITY2_0_LPP_OUTPUT_POLARITY_HIGH _MK_ENUM_CONST(0) +#define DC_COM_PIN_OUTPUT_POLARITY2_0_LPP_OUTPUT_POLARITY_LOW _MK_ENUM_CONST(1) + + +// Register DC_COM_PIN_OUTPUT_POLARITY3_0 +#define DC_COM_PIN_OUTPUT_POLARITY3_0 _MK_ADDR_CONST(0x309) +#define DC_COM_PIN_OUTPUT_POLARITY3_0_SECURE 0x0 +#define DC_COM_PIN_OUTPUT_POLARITY3_0_WORD_COUNT 0x1 +#define DC_COM_PIN_OUTPUT_POLARITY3_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_POLARITY3_0_RESET_MASK _MK_MASK_CONST(0x555) +#define DC_COM_PIN_OUTPUT_POLARITY3_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_POLARITY3_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_POLARITY3_0_READ_MASK _MK_MASK_CONST(0x555) +#define DC_COM_PIN_OUTPUT_POLARITY3_0_WRITE_MASK _MK_MASK_CONST(0x555) +#define DC_COM_PIN_OUTPUT_POLARITY3_0_LSCK_OUTPUT_POLARITY_SHIFT _MK_SHIFT_CONST(0) +#define DC_COM_PIN_OUTPUT_POLARITY3_0_LSCK_OUTPUT_POLARITY_FIELD _MK_FIELD_CONST(0x1, DC_COM_PIN_OUTPUT_POLARITY3_0_LSCK_OUTPUT_POLARITY_SHIFT) +#define DC_COM_PIN_OUTPUT_POLARITY3_0_LSCK_OUTPUT_POLARITY_RANGE 0:0 +#define DC_COM_PIN_OUTPUT_POLARITY3_0_LSCK_OUTPUT_POLARITY_WOFFSET 0x0 +#define DC_COM_PIN_OUTPUT_POLARITY3_0_LSCK_OUTPUT_POLARITY_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_POLARITY3_0_LSCK_OUTPUT_POLARITY_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_COM_PIN_OUTPUT_POLARITY3_0_LSCK_OUTPUT_POLARITY_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_POLARITY3_0_LSCK_OUTPUT_POLARITY_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_POLARITY3_0_LSCK_OUTPUT_POLARITY_HIGH _MK_ENUM_CONST(0) +#define DC_COM_PIN_OUTPUT_POLARITY3_0_LSCK_OUTPUT_POLARITY_LOW _MK_ENUM_CONST(1) + +#define DC_COM_PIN_OUTPUT_POLARITY3_0_LSDA_OUTPUT_POLARITY_SHIFT _MK_SHIFT_CONST(2) +#define DC_COM_PIN_OUTPUT_POLARITY3_0_LSDA_OUTPUT_POLARITY_FIELD _MK_FIELD_CONST(0x1, DC_COM_PIN_OUTPUT_POLARITY3_0_LSDA_OUTPUT_POLARITY_SHIFT) +#define DC_COM_PIN_OUTPUT_POLARITY3_0_LSDA_OUTPUT_POLARITY_RANGE 2:2 +#define DC_COM_PIN_OUTPUT_POLARITY3_0_LSDA_OUTPUT_POLARITY_WOFFSET 0x0 +#define DC_COM_PIN_OUTPUT_POLARITY3_0_LSDA_OUTPUT_POLARITY_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_POLARITY3_0_LSDA_OUTPUT_POLARITY_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_COM_PIN_OUTPUT_POLARITY3_0_LSDA_OUTPUT_POLARITY_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_POLARITY3_0_LSDA_OUTPUT_POLARITY_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_POLARITY3_0_LSDA_OUTPUT_POLARITY_HIGH _MK_ENUM_CONST(0) +#define DC_COM_PIN_OUTPUT_POLARITY3_0_LSDA_OUTPUT_POLARITY_LOW _MK_ENUM_CONST(1) + +#define DC_COM_PIN_OUTPUT_POLARITY3_0_LCSN_OUTPUT_POLARITY_SHIFT _MK_SHIFT_CONST(4) +#define DC_COM_PIN_OUTPUT_POLARITY3_0_LCSN_OUTPUT_POLARITY_FIELD _MK_FIELD_CONST(0x1, DC_COM_PIN_OUTPUT_POLARITY3_0_LCSN_OUTPUT_POLARITY_SHIFT) +#define DC_COM_PIN_OUTPUT_POLARITY3_0_LCSN_OUTPUT_POLARITY_RANGE 4:4 +#define DC_COM_PIN_OUTPUT_POLARITY3_0_LCSN_OUTPUT_POLARITY_WOFFSET 0x0 +#define DC_COM_PIN_OUTPUT_POLARITY3_0_LCSN_OUTPUT_POLARITY_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_POLARITY3_0_LCSN_OUTPUT_POLARITY_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_COM_PIN_OUTPUT_POLARITY3_0_LCSN_OUTPUT_POLARITY_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_POLARITY3_0_LCSN_OUTPUT_POLARITY_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_POLARITY3_0_LCSN_OUTPUT_POLARITY_HIGH _MK_ENUM_CONST(0) +#define DC_COM_PIN_OUTPUT_POLARITY3_0_LCSN_OUTPUT_POLARITY_LOW _MK_ENUM_CONST(1) + +#define DC_COM_PIN_OUTPUT_POLARITY3_0_LDC_OUTPUT_POLARITY_SHIFT _MK_SHIFT_CONST(6) +#define DC_COM_PIN_OUTPUT_POLARITY3_0_LDC_OUTPUT_POLARITY_FIELD _MK_FIELD_CONST(0x1, DC_COM_PIN_OUTPUT_POLARITY3_0_LDC_OUTPUT_POLARITY_SHIFT) +#define DC_COM_PIN_OUTPUT_POLARITY3_0_LDC_OUTPUT_POLARITY_RANGE 6:6 +#define DC_COM_PIN_OUTPUT_POLARITY3_0_LDC_OUTPUT_POLARITY_WOFFSET 0x0 +#define DC_COM_PIN_OUTPUT_POLARITY3_0_LDC_OUTPUT_POLARITY_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_POLARITY3_0_LDC_OUTPUT_POLARITY_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_COM_PIN_OUTPUT_POLARITY3_0_LDC_OUTPUT_POLARITY_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_POLARITY3_0_LDC_OUTPUT_POLARITY_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_POLARITY3_0_LDC_OUTPUT_POLARITY_HIGH _MK_ENUM_CONST(0) +#define DC_COM_PIN_OUTPUT_POLARITY3_0_LDC_OUTPUT_POLARITY_LOW _MK_ENUM_CONST(1) + +#define DC_COM_PIN_OUTPUT_POLARITY3_0_LSPI_OUTPUT_POLARITY_SHIFT _MK_SHIFT_CONST(8) +#define DC_COM_PIN_OUTPUT_POLARITY3_0_LSPI_OUTPUT_POLARITY_FIELD _MK_FIELD_CONST(0x1, DC_COM_PIN_OUTPUT_POLARITY3_0_LSPI_OUTPUT_POLARITY_SHIFT) +#define DC_COM_PIN_OUTPUT_POLARITY3_0_LSPI_OUTPUT_POLARITY_RANGE 8:8 +#define DC_COM_PIN_OUTPUT_POLARITY3_0_LSPI_OUTPUT_POLARITY_WOFFSET 0x0 +#define DC_COM_PIN_OUTPUT_POLARITY3_0_LSPI_OUTPUT_POLARITY_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_POLARITY3_0_LSPI_OUTPUT_POLARITY_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_COM_PIN_OUTPUT_POLARITY3_0_LSPI_OUTPUT_POLARITY_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_POLARITY3_0_LSPI_OUTPUT_POLARITY_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_POLARITY3_0_LSPI_OUTPUT_POLARITY_HIGH _MK_ENUM_CONST(0) +#define DC_COM_PIN_OUTPUT_POLARITY3_0_LSPI_OUTPUT_POLARITY_LOW _MK_ENUM_CONST(1) + +#define DC_COM_PIN_OUTPUT_POLARITY3_0_LSDI_OUTPUT_POLARITY_SHIFT _MK_SHIFT_CONST(10) +#define DC_COM_PIN_OUTPUT_POLARITY3_0_LSDI_OUTPUT_POLARITY_FIELD _MK_FIELD_CONST(0x1, DC_COM_PIN_OUTPUT_POLARITY3_0_LSDI_OUTPUT_POLARITY_SHIFT) +#define DC_COM_PIN_OUTPUT_POLARITY3_0_LSDI_OUTPUT_POLARITY_RANGE 10:10 +#define DC_COM_PIN_OUTPUT_POLARITY3_0_LSDI_OUTPUT_POLARITY_WOFFSET 0x0 +#define DC_COM_PIN_OUTPUT_POLARITY3_0_LSDI_OUTPUT_POLARITY_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_POLARITY3_0_LSDI_OUTPUT_POLARITY_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_COM_PIN_OUTPUT_POLARITY3_0_LSDI_OUTPUT_POLARITY_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_POLARITY3_0_LSDI_OUTPUT_POLARITY_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_POLARITY3_0_LSDI_OUTPUT_POLARITY_HIGH _MK_ENUM_CONST(0) +#define DC_COM_PIN_OUTPUT_POLARITY3_0_LSDI_OUTPUT_POLARITY_LOW _MK_ENUM_CONST(1) + + +// Register DC_COM_PIN_OUTPUT_DATA0_0 +#define DC_COM_PIN_OUTPUT_DATA0_0 _MK_ADDR_CONST(0x30a) +#define DC_COM_PIN_OUTPUT_DATA0_0_SECURE 0x0 +#define DC_COM_PIN_OUTPUT_DATA0_0_WORD_COUNT 0x1 +#define DC_COM_PIN_OUTPUT_DATA0_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA0_0_RESET_MASK _MK_MASK_CONST(0xffffffff) +#define DC_COM_PIN_OUTPUT_DATA0_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA0_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA0_0_READ_MASK _MK_MASK_CONST(0x55555555) +#define DC_COM_PIN_OUTPUT_DATA0_0_WRITE_MASK _MK_MASK_CONST(0xffffffff) +#define DC_COM_PIN_OUTPUT_DATA0_0_LD0_OUTPUT_DATA_SHIFT _MK_SHIFT_CONST(0) +#define DC_COM_PIN_OUTPUT_DATA0_0_LD0_OUTPUT_DATA_FIELD _MK_FIELD_CONST(0x1, DC_COM_PIN_OUTPUT_DATA0_0_LD0_OUTPUT_DATA_SHIFT) +#define DC_COM_PIN_OUTPUT_DATA0_0_LD0_OUTPUT_DATA_RANGE 0:0 +#define DC_COM_PIN_OUTPUT_DATA0_0_LD0_OUTPUT_DATA_WOFFSET 0x0 +#define DC_COM_PIN_OUTPUT_DATA0_0_LD0_OUTPUT_DATA_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA0_0_LD0_OUTPUT_DATA_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_COM_PIN_OUTPUT_DATA0_0_LD0_OUTPUT_DATA_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA0_0_LD0_OUTPUT_DATA_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA0_0_LD0_OUTPUT_DATA_LOW _MK_ENUM_CONST(0) +#define DC_COM_PIN_OUTPUT_DATA0_0_LD0_OUTPUT_DATA_HIGH _MK_ENUM_CONST(1) + +#define DC_COM_PIN_OUTPUT_DATA0_0_LD0_OUTPUT_DATA_MASK_SHIFT _MK_SHIFT_CONST(1) +#define DC_COM_PIN_OUTPUT_DATA0_0_LD0_OUTPUT_DATA_MASK_FIELD _MK_FIELD_CONST(0x1, DC_COM_PIN_OUTPUT_DATA0_0_LD0_OUTPUT_DATA_MASK_SHIFT) +#define DC_COM_PIN_OUTPUT_DATA0_0_LD0_OUTPUT_DATA_MASK_RANGE 1:1 +#define DC_COM_PIN_OUTPUT_DATA0_0_LD0_OUTPUT_DATA_MASK_WOFFSET 0x0 +#define DC_COM_PIN_OUTPUT_DATA0_0_LD0_OUTPUT_DATA_MASK_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA0_0_LD0_OUTPUT_DATA_MASK_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_COM_PIN_OUTPUT_DATA0_0_LD0_OUTPUT_DATA_MASK_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA0_0_LD0_OUTPUT_DATA_MASK_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA0_0_LD0_OUTPUT_DATA_MASK_MASKED _MK_ENUM_CONST(0) +#define DC_COM_PIN_OUTPUT_DATA0_0_LD0_OUTPUT_DATA_MASK_NOTMASKED _MK_ENUM_CONST(1) + +#define DC_COM_PIN_OUTPUT_DATA0_0_LD1_OUTPUT_DATA_SHIFT _MK_SHIFT_CONST(2) +#define DC_COM_PIN_OUTPUT_DATA0_0_LD1_OUTPUT_DATA_FIELD _MK_FIELD_CONST(0x1, DC_COM_PIN_OUTPUT_DATA0_0_LD1_OUTPUT_DATA_SHIFT) +#define DC_COM_PIN_OUTPUT_DATA0_0_LD1_OUTPUT_DATA_RANGE 2:2 +#define DC_COM_PIN_OUTPUT_DATA0_0_LD1_OUTPUT_DATA_WOFFSET 0x0 +#define DC_COM_PIN_OUTPUT_DATA0_0_LD1_OUTPUT_DATA_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA0_0_LD1_OUTPUT_DATA_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_COM_PIN_OUTPUT_DATA0_0_LD1_OUTPUT_DATA_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA0_0_LD1_OUTPUT_DATA_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA0_0_LD1_OUTPUT_DATA_LOW _MK_ENUM_CONST(0) +#define DC_COM_PIN_OUTPUT_DATA0_0_LD1_OUTPUT_DATA_HIGH _MK_ENUM_CONST(1) + +#define DC_COM_PIN_OUTPUT_DATA0_0_LD1_OUTPUT_DATA_MASK_SHIFT _MK_SHIFT_CONST(3) +#define DC_COM_PIN_OUTPUT_DATA0_0_LD1_OUTPUT_DATA_MASK_FIELD _MK_FIELD_CONST(0x1, DC_COM_PIN_OUTPUT_DATA0_0_LD1_OUTPUT_DATA_MASK_SHIFT) +#define DC_COM_PIN_OUTPUT_DATA0_0_LD1_OUTPUT_DATA_MASK_RANGE 3:3 +#define DC_COM_PIN_OUTPUT_DATA0_0_LD1_OUTPUT_DATA_MASK_WOFFSET 0x0 +#define DC_COM_PIN_OUTPUT_DATA0_0_LD1_OUTPUT_DATA_MASK_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA0_0_LD1_OUTPUT_DATA_MASK_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_COM_PIN_OUTPUT_DATA0_0_LD1_OUTPUT_DATA_MASK_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA0_0_LD1_OUTPUT_DATA_MASK_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA0_0_LD1_OUTPUT_DATA_MASK_MASKED _MK_ENUM_CONST(0) +#define DC_COM_PIN_OUTPUT_DATA0_0_LD1_OUTPUT_DATA_MASK_NOTMASKED _MK_ENUM_CONST(1) + +#define DC_COM_PIN_OUTPUT_DATA0_0_LD2_OUTPUT_DATA_SHIFT _MK_SHIFT_CONST(4) +#define DC_COM_PIN_OUTPUT_DATA0_0_LD2_OUTPUT_DATA_FIELD _MK_FIELD_CONST(0x1, DC_COM_PIN_OUTPUT_DATA0_0_LD2_OUTPUT_DATA_SHIFT) +#define DC_COM_PIN_OUTPUT_DATA0_0_LD2_OUTPUT_DATA_RANGE 4:4 +#define DC_COM_PIN_OUTPUT_DATA0_0_LD2_OUTPUT_DATA_WOFFSET 0x0 +#define DC_COM_PIN_OUTPUT_DATA0_0_LD2_OUTPUT_DATA_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA0_0_LD2_OUTPUT_DATA_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_COM_PIN_OUTPUT_DATA0_0_LD2_OUTPUT_DATA_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA0_0_LD2_OUTPUT_DATA_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA0_0_LD2_OUTPUT_DATA_LOW _MK_ENUM_CONST(0) +#define DC_COM_PIN_OUTPUT_DATA0_0_LD2_OUTPUT_DATA_HIGH _MK_ENUM_CONST(1) + +#define DC_COM_PIN_OUTPUT_DATA0_0_LD2_OUTPUT_DATA_MASK_SHIFT _MK_SHIFT_CONST(5) +#define DC_COM_PIN_OUTPUT_DATA0_0_LD2_OUTPUT_DATA_MASK_FIELD _MK_FIELD_CONST(0x1, DC_COM_PIN_OUTPUT_DATA0_0_LD2_OUTPUT_DATA_MASK_SHIFT) +#define DC_COM_PIN_OUTPUT_DATA0_0_LD2_OUTPUT_DATA_MASK_RANGE 5:5 +#define DC_COM_PIN_OUTPUT_DATA0_0_LD2_OUTPUT_DATA_MASK_WOFFSET 0x0 +#define DC_COM_PIN_OUTPUT_DATA0_0_LD2_OUTPUT_DATA_MASK_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA0_0_LD2_OUTPUT_DATA_MASK_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_COM_PIN_OUTPUT_DATA0_0_LD2_OUTPUT_DATA_MASK_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA0_0_LD2_OUTPUT_DATA_MASK_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA0_0_LD2_OUTPUT_DATA_MASK_MASKED _MK_ENUM_CONST(0) +#define DC_COM_PIN_OUTPUT_DATA0_0_LD2_OUTPUT_DATA_MASK_NOTMASKED _MK_ENUM_CONST(1) + +#define DC_COM_PIN_OUTPUT_DATA0_0_LD3_OUTPUT_DATA_SHIFT _MK_SHIFT_CONST(6) +#define DC_COM_PIN_OUTPUT_DATA0_0_LD3_OUTPUT_DATA_FIELD _MK_FIELD_CONST(0x1, DC_COM_PIN_OUTPUT_DATA0_0_LD3_OUTPUT_DATA_SHIFT) +#define DC_COM_PIN_OUTPUT_DATA0_0_LD3_OUTPUT_DATA_RANGE 6:6 +#define DC_COM_PIN_OUTPUT_DATA0_0_LD3_OUTPUT_DATA_WOFFSET 0x0 +#define DC_COM_PIN_OUTPUT_DATA0_0_LD3_OUTPUT_DATA_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA0_0_LD3_OUTPUT_DATA_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_COM_PIN_OUTPUT_DATA0_0_LD3_OUTPUT_DATA_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA0_0_LD3_OUTPUT_DATA_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA0_0_LD3_OUTPUT_DATA_LOW _MK_ENUM_CONST(0) +#define DC_COM_PIN_OUTPUT_DATA0_0_LD3_OUTPUT_DATA_HIGH _MK_ENUM_CONST(1) + +#define DC_COM_PIN_OUTPUT_DATA0_0_LD3_OUTPUT_DATA_MASK_SHIFT _MK_SHIFT_CONST(7) +#define DC_COM_PIN_OUTPUT_DATA0_0_LD3_OUTPUT_DATA_MASK_FIELD _MK_FIELD_CONST(0x1, DC_COM_PIN_OUTPUT_DATA0_0_LD3_OUTPUT_DATA_MASK_SHIFT) +#define DC_COM_PIN_OUTPUT_DATA0_0_LD3_OUTPUT_DATA_MASK_RANGE 7:7 +#define DC_COM_PIN_OUTPUT_DATA0_0_LD3_OUTPUT_DATA_MASK_WOFFSET 0x0 +#define DC_COM_PIN_OUTPUT_DATA0_0_LD3_OUTPUT_DATA_MASK_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA0_0_LD3_OUTPUT_DATA_MASK_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_COM_PIN_OUTPUT_DATA0_0_LD3_OUTPUT_DATA_MASK_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA0_0_LD3_OUTPUT_DATA_MASK_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA0_0_LD3_OUTPUT_DATA_MASK_MASKED _MK_ENUM_CONST(0) +#define DC_COM_PIN_OUTPUT_DATA0_0_LD3_OUTPUT_DATA_MASK_NOTMASKED _MK_ENUM_CONST(1) + +#define DC_COM_PIN_OUTPUT_DATA0_0_LD4_OUTPUT_DATA_SHIFT _MK_SHIFT_CONST(8) +#define DC_COM_PIN_OUTPUT_DATA0_0_LD4_OUTPUT_DATA_FIELD _MK_FIELD_CONST(0x1, DC_COM_PIN_OUTPUT_DATA0_0_LD4_OUTPUT_DATA_SHIFT) +#define DC_COM_PIN_OUTPUT_DATA0_0_LD4_OUTPUT_DATA_RANGE 8:8 +#define DC_COM_PIN_OUTPUT_DATA0_0_LD4_OUTPUT_DATA_WOFFSET 0x0 +#define DC_COM_PIN_OUTPUT_DATA0_0_LD4_OUTPUT_DATA_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA0_0_LD4_OUTPUT_DATA_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_COM_PIN_OUTPUT_DATA0_0_LD4_OUTPUT_DATA_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA0_0_LD4_OUTPUT_DATA_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA0_0_LD4_OUTPUT_DATA_LOW _MK_ENUM_CONST(0) +#define DC_COM_PIN_OUTPUT_DATA0_0_LD4_OUTPUT_DATA_HIGH _MK_ENUM_CONST(1) + +#define DC_COM_PIN_OUTPUT_DATA0_0_LD4_OUTPUT_DATA_MASK_SHIFT _MK_SHIFT_CONST(9) +#define DC_COM_PIN_OUTPUT_DATA0_0_LD4_OUTPUT_DATA_MASK_FIELD _MK_FIELD_CONST(0x1, DC_COM_PIN_OUTPUT_DATA0_0_LD4_OUTPUT_DATA_MASK_SHIFT) +#define DC_COM_PIN_OUTPUT_DATA0_0_LD4_OUTPUT_DATA_MASK_RANGE 9:9 +#define DC_COM_PIN_OUTPUT_DATA0_0_LD4_OUTPUT_DATA_MASK_WOFFSET 0x0 +#define DC_COM_PIN_OUTPUT_DATA0_0_LD4_OUTPUT_DATA_MASK_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA0_0_LD4_OUTPUT_DATA_MASK_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_COM_PIN_OUTPUT_DATA0_0_LD4_OUTPUT_DATA_MASK_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA0_0_LD4_OUTPUT_DATA_MASK_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA0_0_LD4_OUTPUT_DATA_MASK_MASKED _MK_ENUM_CONST(0) +#define DC_COM_PIN_OUTPUT_DATA0_0_LD4_OUTPUT_DATA_MASK_NOTMASKED _MK_ENUM_CONST(1) + +#define DC_COM_PIN_OUTPUT_DATA0_0_LD5_OUTPUT_DATA_SHIFT _MK_SHIFT_CONST(10) +#define DC_COM_PIN_OUTPUT_DATA0_0_LD5_OUTPUT_DATA_FIELD _MK_FIELD_CONST(0x1, DC_COM_PIN_OUTPUT_DATA0_0_LD5_OUTPUT_DATA_SHIFT) +#define DC_COM_PIN_OUTPUT_DATA0_0_LD5_OUTPUT_DATA_RANGE 10:10 +#define DC_COM_PIN_OUTPUT_DATA0_0_LD5_OUTPUT_DATA_WOFFSET 0x0 +#define DC_COM_PIN_OUTPUT_DATA0_0_LD5_OUTPUT_DATA_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA0_0_LD5_OUTPUT_DATA_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_COM_PIN_OUTPUT_DATA0_0_LD5_OUTPUT_DATA_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA0_0_LD5_OUTPUT_DATA_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA0_0_LD5_OUTPUT_DATA_LOW _MK_ENUM_CONST(0) +#define DC_COM_PIN_OUTPUT_DATA0_0_LD5_OUTPUT_DATA_HIGH _MK_ENUM_CONST(1) + +#define DC_COM_PIN_OUTPUT_DATA0_0_LD5_OUTPUT_DATA_MASK_SHIFT _MK_SHIFT_CONST(11) +#define DC_COM_PIN_OUTPUT_DATA0_0_LD5_OUTPUT_DATA_MASK_FIELD _MK_FIELD_CONST(0x1, DC_COM_PIN_OUTPUT_DATA0_0_LD5_OUTPUT_DATA_MASK_SHIFT) +#define DC_COM_PIN_OUTPUT_DATA0_0_LD5_OUTPUT_DATA_MASK_RANGE 11:11 +#define DC_COM_PIN_OUTPUT_DATA0_0_LD5_OUTPUT_DATA_MASK_WOFFSET 0x0 +#define DC_COM_PIN_OUTPUT_DATA0_0_LD5_OUTPUT_DATA_MASK_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA0_0_LD5_OUTPUT_DATA_MASK_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_COM_PIN_OUTPUT_DATA0_0_LD5_OUTPUT_DATA_MASK_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA0_0_LD5_OUTPUT_DATA_MASK_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA0_0_LD5_OUTPUT_DATA_MASK_MASKED _MK_ENUM_CONST(0) +#define DC_COM_PIN_OUTPUT_DATA0_0_LD5_OUTPUT_DATA_MASK_NOTMASKED _MK_ENUM_CONST(1) + +#define DC_COM_PIN_OUTPUT_DATA0_0_LD6_OUTPUT_DATA_SHIFT _MK_SHIFT_CONST(12) +#define DC_COM_PIN_OUTPUT_DATA0_0_LD6_OUTPUT_DATA_FIELD _MK_FIELD_CONST(0x1, DC_COM_PIN_OUTPUT_DATA0_0_LD6_OUTPUT_DATA_SHIFT) +#define DC_COM_PIN_OUTPUT_DATA0_0_LD6_OUTPUT_DATA_RANGE 12:12 +#define DC_COM_PIN_OUTPUT_DATA0_0_LD6_OUTPUT_DATA_WOFFSET 0x0 +#define DC_COM_PIN_OUTPUT_DATA0_0_LD6_OUTPUT_DATA_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA0_0_LD6_OUTPUT_DATA_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_COM_PIN_OUTPUT_DATA0_0_LD6_OUTPUT_DATA_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA0_0_LD6_OUTPUT_DATA_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA0_0_LD6_OUTPUT_DATA_LOW _MK_ENUM_CONST(0) +#define DC_COM_PIN_OUTPUT_DATA0_0_LD6_OUTPUT_DATA_HIGH _MK_ENUM_CONST(1) + +#define DC_COM_PIN_OUTPUT_DATA0_0_LD6_OUTPUT_DATA_MASK_SHIFT _MK_SHIFT_CONST(13) +#define DC_COM_PIN_OUTPUT_DATA0_0_LD6_OUTPUT_DATA_MASK_FIELD _MK_FIELD_CONST(0x1, DC_COM_PIN_OUTPUT_DATA0_0_LD6_OUTPUT_DATA_MASK_SHIFT) +#define DC_COM_PIN_OUTPUT_DATA0_0_LD6_OUTPUT_DATA_MASK_RANGE 13:13 +#define DC_COM_PIN_OUTPUT_DATA0_0_LD6_OUTPUT_DATA_MASK_WOFFSET 0x0 +#define DC_COM_PIN_OUTPUT_DATA0_0_LD6_OUTPUT_DATA_MASK_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA0_0_LD6_OUTPUT_DATA_MASK_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_COM_PIN_OUTPUT_DATA0_0_LD6_OUTPUT_DATA_MASK_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA0_0_LD6_OUTPUT_DATA_MASK_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA0_0_LD6_OUTPUT_DATA_MASK_MASKED _MK_ENUM_CONST(0) +#define DC_COM_PIN_OUTPUT_DATA0_0_LD6_OUTPUT_DATA_MASK_NOTMASKED _MK_ENUM_CONST(1) + +#define DC_COM_PIN_OUTPUT_DATA0_0_LD7_OUTPUT_DATA_SHIFT _MK_SHIFT_CONST(14) +#define DC_COM_PIN_OUTPUT_DATA0_0_LD7_OUTPUT_DATA_FIELD _MK_FIELD_CONST(0x1, DC_COM_PIN_OUTPUT_DATA0_0_LD7_OUTPUT_DATA_SHIFT) +#define DC_COM_PIN_OUTPUT_DATA0_0_LD7_OUTPUT_DATA_RANGE 14:14 +#define DC_COM_PIN_OUTPUT_DATA0_0_LD7_OUTPUT_DATA_WOFFSET 0x0 +#define DC_COM_PIN_OUTPUT_DATA0_0_LD7_OUTPUT_DATA_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA0_0_LD7_OUTPUT_DATA_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_COM_PIN_OUTPUT_DATA0_0_LD7_OUTPUT_DATA_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA0_0_LD7_OUTPUT_DATA_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA0_0_LD7_OUTPUT_DATA_LOW _MK_ENUM_CONST(0) +#define DC_COM_PIN_OUTPUT_DATA0_0_LD7_OUTPUT_DATA_HIGH _MK_ENUM_CONST(1) + +#define DC_COM_PIN_OUTPUT_DATA0_0_LD7_OUTPUT_DATA_MASK_SHIFT _MK_SHIFT_CONST(15) +#define DC_COM_PIN_OUTPUT_DATA0_0_LD7_OUTPUT_DATA_MASK_FIELD _MK_FIELD_CONST(0x1, DC_COM_PIN_OUTPUT_DATA0_0_LD7_OUTPUT_DATA_MASK_SHIFT) +#define DC_COM_PIN_OUTPUT_DATA0_0_LD7_OUTPUT_DATA_MASK_RANGE 15:15 +#define DC_COM_PIN_OUTPUT_DATA0_0_LD7_OUTPUT_DATA_MASK_WOFFSET 0x0 +#define DC_COM_PIN_OUTPUT_DATA0_0_LD7_OUTPUT_DATA_MASK_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA0_0_LD7_OUTPUT_DATA_MASK_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_COM_PIN_OUTPUT_DATA0_0_LD7_OUTPUT_DATA_MASK_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA0_0_LD7_OUTPUT_DATA_MASK_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA0_0_LD7_OUTPUT_DATA_MASK_MASKED _MK_ENUM_CONST(0) +#define DC_COM_PIN_OUTPUT_DATA0_0_LD7_OUTPUT_DATA_MASK_NOTMASKED _MK_ENUM_CONST(1) + +#define DC_COM_PIN_OUTPUT_DATA0_0_LD8_OUTPUT_DATA_SHIFT _MK_SHIFT_CONST(16) +#define DC_COM_PIN_OUTPUT_DATA0_0_LD8_OUTPUT_DATA_FIELD _MK_FIELD_CONST(0x1, DC_COM_PIN_OUTPUT_DATA0_0_LD8_OUTPUT_DATA_SHIFT) +#define DC_COM_PIN_OUTPUT_DATA0_0_LD8_OUTPUT_DATA_RANGE 16:16 +#define DC_COM_PIN_OUTPUT_DATA0_0_LD8_OUTPUT_DATA_WOFFSET 0x0 +#define DC_COM_PIN_OUTPUT_DATA0_0_LD8_OUTPUT_DATA_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA0_0_LD8_OUTPUT_DATA_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_COM_PIN_OUTPUT_DATA0_0_LD8_OUTPUT_DATA_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA0_0_LD8_OUTPUT_DATA_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA0_0_LD8_OUTPUT_DATA_LOW _MK_ENUM_CONST(0) +#define DC_COM_PIN_OUTPUT_DATA0_0_LD8_OUTPUT_DATA_HIGH _MK_ENUM_CONST(1) + +#define DC_COM_PIN_OUTPUT_DATA0_0_LD8_OUTPUT_DATA_MASK_SHIFT _MK_SHIFT_CONST(17) +#define DC_COM_PIN_OUTPUT_DATA0_0_LD8_OUTPUT_DATA_MASK_FIELD _MK_FIELD_CONST(0x1, DC_COM_PIN_OUTPUT_DATA0_0_LD8_OUTPUT_DATA_MASK_SHIFT) +#define DC_COM_PIN_OUTPUT_DATA0_0_LD8_OUTPUT_DATA_MASK_RANGE 17:17 +#define DC_COM_PIN_OUTPUT_DATA0_0_LD8_OUTPUT_DATA_MASK_WOFFSET 0x0 +#define DC_COM_PIN_OUTPUT_DATA0_0_LD8_OUTPUT_DATA_MASK_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA0_0_LD8_OUTPUT_DATA_MASK_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_COM_PIN_OUTPUT_DATA0_0_LD8_OUTPUT_DATA_MASK_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA0_0_LD8_OUTPUT_DATA_MASK_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA0_0_LD8_OUTPUT_DATA_MASK_MASKED _MK_ENUM_CONST(0) +#define DC_COM_PIN_OUTPUT_DATA0_0_LD8_OUTPUT_DATA_MASK_NOTMASKED _MK_ENUM_CONST(1) + +#define DC_COM_PIN_OUTPUT_DATA0_0_LD9_OUTPUT_DATA_SHIFT _MK_SHIFT_CONST(18) +#define DC_COM_PIN_OUTPUT_DATA0_0_LD9_OUTPUT_DATA_FIELD _MK_FIELD_CONST(0x1, DC_COM_PIN_OUTPUT_DATA0_0_LD9_OUTPUT_DATA_SHIFT) +#define DC_COM_PIN_OUTPUT_DATA0_0_LD9_OUTPUT_DATA_RANGE 18:18 +#define DC_COM_PIN_OUTPUT_DATA0_0_LD9_OUTPUT_DATA_WOFFSET 0x0 +#define DC_COM_PIN_OUTPUT_DATA0_0_LD9_OUTPUT_DATA_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA0_0_LD9_OUTPUT_DATA_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_COM_PIN_OUTPUT_DATA0_0_LD9_OUTPUT_DATA_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA0_0_LD9_OUTPUT_DATA_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA0_0_LD9_OUTPUT_DATA_LOW _MK_ENUM_CONST(0) +#define DC_COM_PIN_OUTPUT_DATA0_0_LD9_OUTPUT_DATA_HIGH _MK_ENUM_CONST(1) + +#define DC_COM_PIN_OUTPUT_DATA0_0_LD9_OUTPUT_DATA_MASK_SHIFT _MK_SHIFT_CONST(19) +#define DC_COM_PIN_OUTPUT_DATA0_0_LD9_OUTPUT_DATA_MASK_FIELD _MK_FIELD_CONST(0x1, DC_COM_PIN_OUTPUT_DATA0_0_LD9_OUTPUT_DATA_MASK_SHIFT) +#define DC_COM_PIN_OUTPUT_DATA0_0_LD9_OUTPUT_DATA_MASK_RANGE 19:19 +#define DC_COM_PIN_OUTPUT_DATA0_0_LD9_OUTPUT_DATA_MASK_WOFFSET 0x0 +#define DC_COM_PIN_OUTPUT_DATA0_0_LD9_OUTPUT_DATA_MASK_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA0_0_LD9_OUTPUT_DATA_MASK_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_COM_PIN_OUTPUT_DATA0_0_LD9_OUTPUT_DATA_MASK_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA0_0_LD9_OUTPUT_DATA_MASK_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA0_0_LD9_OUTPUT_DATA_MASK_MASKED _MK_ENUM_CONST(0) +#define DC_COM_PIN_OUTPUT_DATA0_0_LD9_OUTPUT_DATA_MASK_NOTMASKED _MK_ENUM_CONST(1) + +#define DC_COM_PIN_OUTPUT_DATA0_0_LD10_OUTPUT_DATA_SHIFT _MK_SHIFT_CONST(20) +#define DC_COM_PIN_OUTPUT_DATA0_0_LD10_OUTPUT_DATA_FIELD _MK_FIELD_CONST(0x1, DC_COM_PIN_OUTPUT_DATA0_0_LD10_OUTPUT_DATA_SHIFT) +#define DC_COM_PIN_OUTPUT_DATA0_0_LD10_OUTPUT_DATA_RANGE 20:20 +#define DC_COM_PIN_OUTPUT_DATA0_0_LD10_OUTPUT_DATA_WOFFSET 0x0 +#define DC_COM_PIN_OUTPUT_DATA0_0_LD10_OUTPUT_DATA_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA0_0_LD10_OUTPUT_DATA_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_COM_PIN_OUTPUT_DATA0_0_LD10_OUTPUT_DATA_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA0_0_LD10_OUTPUT_DATA_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA0_0_LD10_OUTPUT_DATA_LOW _MK_ENUM_CONST(0) +#define DC_COM_PIN_OUTPUT_DATA0_0_LD10_OUTPUT_DATA_HIGH _MK_ENUM_CONST(1) + +#define DC_COM_PIN_OUTPUT_DATA0_0_LD10_OUTPUT_DATA_MASK_SHIFT _MK_SHIFT_CONST(21) +#define DC_COM_PIN_OUTPUT_DATA0_0_LD10_OUTPUT_DATA_MASK_FIELD _MK_FIELD_CONST(0x1, DC_COM_PIN_OUTPUT_DATA0_0_LD10_OUTPUT_DATA_MASK_SHIFT) +#define DC_COM_PIN_OUTPUT_DATA0_0_LD10_OUTPUT_DATA_MASK_RANGE 21:21 +#define DC_COM_PIN_OUTPUT_DATA0_0_LD10_OUTPUT_DATA_MASK_WOFFSET 0x0 +#define DC_COM_PIN_OUTPUT_DATA0_0_LD10_OUTPUT_DATA_MASK_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA0_0_LD10_OUTPUT_DATA_MASK_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_COM_PIN_OUTPUT_DATA0_0_LD10_OUTPUT_DATA_MASK_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA0_0_LD10_OUTPUT_DATA_MASK_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA0_0_LD10_OUTPUT_DATA_MASK_MASKED _MK_ENUM_CONST(0) +#define DC_COM_PIN_OUTPUT_DATA0_0_LD10_OUTPUT_DATA_MASK_NOTMASKED _MK_ENUM_CONST(1) + +#define DC_COM_PIN_OUTPUT_DATA0_0_LD11_OUTPUT_DATA_SHIFT _MK_SHIFT_CONST(22) +#define DC_COM_PIN_OUTPUT_DATA0_0_LD11_OUTPUT_DATA_FIELD _MK_FIELD_CONST(0x1, DC_COM_PIN_OUTPUT_DATA0_0_LD11_OUTPUT_DATA_SHIFT) +#define DC_COM_PIN_OUTPUT_DATA0_0_LD11_OUTPUT_DATA_RANGE 22:22 +#define DC_COM_PIN_OUTPUT_DATA0_0_LD11_OUTPUT_DATA_WOFFSET 0x0 +#define DC_COM_PIN_OUTPUT_DATA0_0_LD11_OUTPUT_DATA_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA0_0_LD11_OUTPUT_DATA_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_COM_PIN_OUTPUT_DATA0_0_LD11_OUTPUT_DATA_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA0_0_LD11_OUTPUT_DATA_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA0_0_LD11_OUTPUT_DATA_LOW _MK_ENUM_CONST(0) +#define DC_COM_PIN_OUTPUT_DATA0_0_LD11_OUTPUT_DATA_HIGH _MK_ENUM_CONST(1) + +#define DC_COM_PIN_OUTPUT_DATA0_0_LD11_OUTPUT_DATA_MASK_SHIFT _MK_SHIFT_CONST(23) +#define DC_COM_PIN_OUTPUT_DATA0_0_LD11_OUTPUT_DATA_MASK_FIELD _MK_FIELD_CONST(0x1, DC_COM_PIN_OUTPUT_DATA0_0_LD11_OUTPUT_DATA_MASK_SHIFT) +#define DC_COM_PIN_OUTPUT_DATA0_0_LD11_OUTPUT_DATA_MASK_RANGE 23:23 +#define DC_COM_PIN_OUTPUT_DATA0_0_LD11_OUTPUT_DATA_MASK_WOFFSET 0x0 +#define DC_COM_PIN_OUTPUT_DATA0_0_LD11_OUTPUT_DATA_MASK_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA0_0_LD11_OUTPUT_DATA_MASK_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_COM_PIN_OUTPUT_DATA0_0_LD11_OUTPUT_DATA_MASK_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA0_0_LD11_OUTPUT_DATA_MASK_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA0_0_LD11_OUTPUT_DATA_MASK_MASKED _MK_ENUM_CONST(0) +#define DC_COM_PIN_OUTPUT_DATA0_0_LD11_OUTPUT_DATA_MASK_NOTMASKED _MK_ENUM_CONST(1) + +#define DC_COM_PIN_OUTPUT_DATA0_0_LD12_OUTPUT_DATA_SHIFT _MK_SHIFT_CONST(24) +#define DC_COM_PIN_OUTPUT_DATA0_0_LD12_OUTPUT_DATA_FIELD _MK_FIELD_CONST(0x1, DC_COM_PIN_OUTPUT_DATA0_0_LD12_OUTPUT_DATA_SHIFT) +#define DC_COM_PIN_OUTPUT_DATA0_0_LD12_OUTPUT_DATA_RANGE 24:24 +#define DC_COM_PIN_OUTPUT_DATA0_0_LD12_OUTPUT_DATA_WOFFSET 0x0 +#define DC_COM_PIN_OUTPUT_DATA0_0_LD12_OUTPUT_DATA_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA0_0_LD12_OUTPUT_DATA_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_COM_PIN_OUTPUT_DATA0_0_LD12_OUTPUT_DATA_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA0_0_LD12_OUTPUT_DATA_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA0_0_LD12_OUTPUT_DATA_LOW _MK_ENUM_CONST(0) +#define DC_COM_PIN_OUTPUT_DATA0_0_LD12_OUTPUT_DATA_HIGH _MK_ENUM_CONST(1) + +#define DC_COM_PIN_OUTPUT_DATA0_0_LD12_OUTPUT_DATA_MASK_SHIFT _MK_SHIFT_CONST(25) +#define DC_COM_PIN_OUTPUT_DATA0_0_LD12_OUTPUT_DATA_MASK_FIELD _MK_FIELD_CONST(0x1, DC_COM_PIN_OUTPUT_DATA0_0_LD12_OUTPUT_DATA_MASK_SHIFT) +#define DC_COM_PIN_OUTPUT_DATA0_0_LD12_OUTPUT_DATA_MASK_RANGE 25:25 +#define DC_COM_PIN_OUTPUT_DATA0_0_LD12_OUTPUT_DATA_MASK_WOFFSET 0x0 +#define DC_COM_PIN_OUTPUT_DATA0_0_LD12_OUTPUT_DATA_MASK_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA0_0_LD12_OUTPUT_DATA_MASK_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_COM_PIN_OUTPUT_DATA0_0_LD12_OUTPUT_DATA_MASK_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA0_0_LD12_OUTPUT_DATA_MASK_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA0_0_LD12_OUTPUT_DATA_MASK_MASKED _MK_ENUM_CONST(0) +#define DC_COM_PIN_OUTPUT_DATA0_0_LD12_OUTPUT_DATA_MASK_NOTMASKED _MK_ENUM_CONST(1) + +#define DC_COM_PIN_OUTPUT_DATA0_0_LD13_OUTPUT_DATA_SHIFT _MK_SHIFT_CONST(26) +#define DC_COM_PIN_OUTPUT_DATA0_0_LD13_OUTPUT_DATA_FIELD _MK_FIELD_CONST(0x1, DC_COM_PIN_OUTPUT_DATA0_0_LD13_OUTPUT_DATA_SHIFT) +#define DC_COM_PIN_OUTPUT_DATA0_0_LD13_OUTPUT_DATA_RANGE 26:26 +#define DC_COM_PIN_OUTPUT_DATA0_0_LD13_OUTPUT_DATA_WOFFSET 0x0 +#define DC_COM_PIN_OUTPUT_DATA0_0_LD13_OUTPUT_DATA_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA0_0_LD13_OUTPUT_DATA_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_COM_PIN_OUTPUT_DATA0_0_LD13_OUTPUT_DATA_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA0_0_LD13_OUTPUT_DATA_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA0_0_LD13_OUTPUT_DATA_LOW _MK_ENUM_CONST(0) +#define DC_COM_PIN_OUTPUT_DATA0_0_LD13_OUTPUT_DATA_HIGH _MK_ENUM_CONST(1) + +#define DC_COM_PIN_OUTPUT_DATA0_0_LD13_OUTPUT_DATA_MASK_SHIFT _MK_SHIFT_CONST(27) +#define DC_COM_PIN_OUTPUT_DATA0_0_LD13_OUTPUT_DATA_MASK_FIELD _MK_FIELD_CONST(0x1, DC_COM_PIN_OUTPUT_DATA0_0_LD13_OUTPUT_DATA_MASK_SHIFT) +#define DC_COM_PIN_OUTPUT_DATA0_0_LD13_OUTPUT_DATA_MASK_RANGE 27:27 +#define DC_COM_PIN_OUTPUT_DATA0_0_LD13_OUTPUT_DATA_MASK_WOFFSET 0x0 +#define DC_COM_PIN_OUTPUT_DATA0_0_LD13_OUTPUT_DATA_MASK_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA0_0_LD13_OUTPUT_DATA_MASK_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_COM_PIN_OUTPUT_DATA0_0_LD13_OUTPUT_DATA_MASK_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA0_0_LD13_OUTPUT_DATA_MASK_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA0_0_LD13_OUTPUT_DATA_MASK_MASKED _MK_ENUM_CONST(0) +#define DC_COM_PIN_OUTPUT_DATA0_0_LD13_OUTPUT_DATA_MASK_NOTMASKED _MK_ENUM_CONST(1) + +#define DC_COM_PIN_OUTPUT_DATA0_0_LD14_OUTPUT_DATA_SHIFT _MK_SHIFT_CONST(28) +#define DC_COM_PIN_OUTPUT_DATA0_0_LD14_OUTPUT_DATA_FIELD _MK_FIELD_CONST(0x1, DC_COM_PIN_OUTPUT_DATA0_0_LD14_OUTPUT_DATA_SHIFT) +#define DC_COM_PIN_OUTPUT_DATA0_0_LD14_OUTPUT_DATA_RANGE 28:28 +#define DC_COM_PIN_OUTPUT_DATA0_0_LD14_OUTPUT_DATA_WOFFSET 0x0 +#define DC_COM_PIN_OUTPUT_DATA0_0_LD14_OUTPUT_DATA_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA0_0_LD14_OUTPUT_DATA_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_COM_PIN_OUTPUT_DATA0_0_LD14_OUTPUT_DATA_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA0_0_LD14_OUTPUT_DATA_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA0_0_LD14_OUTPUT_DATA_LOW _MK_ENUM_CONST(0) +#define DC_COM_PIN_OUTPUT_DATA0_0_LD14_OUTPUT_DATA_HIGH _MK_ENUM_CONST(1) + +#define DC_COM_PIN_OUTPUT_DATA0_0_LD14_OUTPUT_DATA_MASK_SHIFT _MK_SHIFT_CONST(29) +#define DC_COM_PIN_OUTPUT_DATA0_0_LD14_OUTPUT_DATA_MASK_FIELD _MK_FIELD_CONST(0x1, DC_COM_PIN_OUTPUT_DATA0_0_LD14_OUTPUT_DATA_MASK_SHIFT) +#define DC_COM_PIN_OUTPUT_DATA0_0_LD14_OUTPUT_DATA_MASK_RANGE 29:29 +#define DC_COM_PIN_OUTPUT_DATA0_0_LD14_OUTPUT_DATA_MASK_WOFFSET 0x0 +#define DC_COM_PIN_OUTPUT_DATA0_0_LD14_OUTPUT_DATA_MASK_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA0_0_LD14_OUTPUT_DATA_MASK_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_COM_PIN_OUTPUT_DATA0_0_LD14_OUTPUT_DATA_MASK_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA0_0_LD14_OUTPUT_DATA_MASK_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA0_0_LD14_OUTPUT_DATA_MASK_MASKED _MK_ENUM_CONST(0) +#define DC_COM_PIN_OUTPUT_DATA0_0_LD14_OUTPUT_DATA_MASK_NOTMASKED _MK_ENUM_CONST(1) + +#define DC_COM_PIN_OUTPUT_DATA0_0_LD15_OUTPUT_DATA_SHIFT _MK_SHIFT_CONST(30) +#define DC_COM_PIN_OUTPUT_DATA0_0_LD15_OUTPUT_DATA_FIELD _MK_FIELD_CONST(0x1, DC_COM_PIN_OUTPUT_DATA0_0_LD15_OUTPUT_DATA_SHIFT) +#define DC_COM_PIN_OUTPUT_DATA0_0_LD15_OUTPUT_DATA_RANGE 30:30 +#define DC_COM_PIN_OUTPUT_DATA0_0_LD15_OUTPUT_DATA_WOFFSET 0x0 +#define DC_COM_PIN_OUTPUT_DATA0_0_LD15_OUTPUT_DATA_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA0_0_LD15_OUTPUT_DATA_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_COM_PIN_OUTPUT_DATA0_0_LD15_OUTPUT_DATA_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA0_0_LD15_OUTPUT_DATA_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA0_0_LD15_OUTPUT_DATA_LOW _MK_ENUM_CONST(0) +#define DC_COM_PIN_OUTPUT_DATA0_0_LD15_OUTPUT_DATA_HIGH _MK_ENUM_CONST(1) + +#define DC_COM_PIN_OUTPUT_DATA0_0_LD15_OUTPUT_DATA_MASK_SHIFT _MK_SHIFT_CONST(31) +#define DC_COM_PIN_OUTPUT_DATA0_0_LD15_OUTPUT_DATA_MASK_FIELD _MK_FIELD_CONST(0x1, DC_COM_PIN_OUTPUT_DATA0_0_LD15_OUTPUT_DATA_MASK_SHIFT) +#define DC_COM_PIN_OUTPUT_DATA0_0_LD15_OUTPUT_DATA_MASK_RANGE 31:31 +#define DC_COM_PIN_OUTPUT_DATA0_0_LD15_OUTPUT_DATA_MASK_WOFFSET 0x0 +#define DC_COM_PIN_OUTPUT_DATA0_0_LD15_OUTPUT_DATA_MASK_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA0_0_LD15_OUTPUT_DATA_MASK_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_COM_PIN_OUTPUT_DATA0_0_LD15_OUTPUT_DATA_MASK_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA0_0_LD15_OUTPUT_DATA_MASK_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA0_0_LD15_OUTPUT_DATA_MASK_MASKED _MK_ENUM_CONST(0) +#define DC_COM_PIN_OUTPUT_DATA0_0_LD15_OUTPUT_DATA_MASK_NOTMASKED _MK_ENUM_CONST(1) + + +// Register DC_COM_PIN_OUTPUT_DATA1_0 +#define DC_COM_PIN_OUTPUT_DATA1_0 _MK_ADDR_CONST(0x30b) +#define DC_COM_PIN_OUTPUT_DATA1_0_SECURE 0x0 +#define DC_COM_PIN_OUTPUT_DATA1_0_WORD_COUNT 0x1 +#define DC_COM_PIN_OUTPUT_DATA1_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA1_0_RESET_MASK _MK_MASK_CONST(0xff3f000f) +#define DC_COM_PIN_OUTPUT_DATA1_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA1_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA1_0_READ_MASK _MK_MASK_CONST(0x55150005) +#define DC_COM_PIN_OUTPUT_DATA1_0_WRITE_MASK _MK_MASK_CONST(0xff3f000f) +#define DC_COM_PIN_OUTPUT_DATA1_0_LD16_OUTPUT_DATA_SHIFT _MK_SHIFT_CONST(0) +#define DC_COM_PIN_OUTPUT_DATA1_0_LD16_OUTPUT_DATA_FIELD _MK_FIELD_CONST(0x1, DC_COM_PIN_OUTPUT_DATA1_0_LD16_OUTPUT_DATA_SHIFT) +#define DC_COM_PIN_OUTPUT_DATA1_0_LD16_OUTPUT_DATA_RANGE 0:0 +#define DC_COM_PIN_OUTPUT_DATA1_0_LD16_OUTPUT_DATA_WOFFSET 0x0 +#define DC_COM_PIN_OUTPUT_DATA1_0_LD16_OUTPUT_DATA_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA1_0_LD16_OUTPUT_DATA_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_COM_PIN_OUTPUT_DATA1_0_LD16_OUTPUT_DATA_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA1_0_LD16_OUTPUT_DATA_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA1_0_LD16_OUTPUT_DATA_LOW _MK_ENUM_CONST(0) +#define DC_COM_PIN_OUTPUT_DATA1_0_LD16_OUTPUT_DATA_HIGH _MK_ENUM_CONST(1) + +#define DC_COM_PIN_OUTPUT_DATA1_0_LD16_OUTPUT_DATA_MASK_SHIFT _MK_SHIFT_CONST(1) +#define DC_COM_PIN_OUTPUT_DATA1_0_LD16_OUTPUT_DATA_MASK_FIELD _MK_FIELD_CONST(0x1, DC_COM_PIN_OUTPUT_DATA1_0_LD16_OUTPUT_DATA_MASK_SHIFT) +#define DC_COM_PIN_OUTPUT_DATA1_0_LD16_OUTPUT_DATA_MASK_RANGE 1:1 +#define DC_COM_PIN_OUTPUT_DATA1_0_LD16_OUTPUT_DATA_MASK_WOFFSET 0x0 +#define DC_COM_PIN_OUTPUT_DATA1_0_LD16_OUTPUT_DATA_MASK_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA1_0_LD16_OUTPUT_DATA_MASK_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_COM_PIN_OUTPUT_DATA1_0_LD16_OUTPUT_DATA_MASK_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA1_0_LD16_OUTPUT_DATA_MASK_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA1_0_LD16_OUTPUT_DATA_MASK_MASKED _MK_ENUM_CONST(0) +#define DC_COM_PIN_OUTPUT_DATA1_0_LD16_OUTPUT_DATA_MASK_NOTMASKED _MK_ENUM_CONST(1) + +#define DC_COM_PIN_OUTPUT_DATA1_0_LD17_OUTPUT_DATA_SHIFT _MK_SHIFT_CONST(2) +#define DC_COM_PIN_OUTPUT_DATA1_0_LD17_OUTPUT_DATA_FIELD _MK_FIELD_CONST(0x1, DC_COM_PIN_OUTPUT_DATA1_0_LD17_OUTPUT_DATA_SHIFT) +#define DC_COM_PIN_OUTPUT_DATA1_0_LD17_OUTPUT_DATA_RANGE 2:2 +#define DC_COM_PIN_OUTPUT_DATA1_0_LD17_OUTPUT_DATA_WOFFSET 0x0 +#define DC_COM_PIN_OUTPUT_DATA1_0_LD17_OUTPUT_DATA_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA1_0_LD17_OUTPUT_DATA_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_COM_PIN_OUTPUT_DATA1_0_LD17_OUTPUT_DATA_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA1_0_LD17_OUTPUT_DATA_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA1_0_LD17_OUTPUT_DATA_LOW _MK_ENUM_CONST(0) +#define DC_COM_PIN_OUTPUT_DATA1_0_LD17_OUTPUT_DATA_HIGH _MK_ENUM_CONST(1) + +#define DC_COM_PIN_OUTPUT_DATA1_0_LD17_OUTPUT_DATA_MASK_SHIFT _MK_SHIFT_CONST(3) +#define DC_COM_PIN_OUTPUT_DATA1_0_LD17_OUTPUT_DATA_MASK_FIELD _MK_FIELD_CONST(0x1, DC_COM_PIN_OUTPUT_DATA1_0_LD17_OUTPUT_DATA_MASK_SHIFT) +#define DC_COM_PIN_OUTPUT_DATA1_0_LD17_OUTPUT_DATA_MASK_RANGE 3:3 +#define DC_COM_PIN_OUTPUT_DATA1_0_LD17_OUTPUT_DATA_MASK_WOFFSET 0x0 +#define DC_COM_PIN_OUTPUT_DATA1_0_LD17_OUTPUT_DATA_MASK_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA1_0_LD17_OUTPUT_DATA_MASK_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_COM_PIN_OUTPUT_DATA1_0_LD17_OUTPUT_DATA_MASK_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA1_0_LD17_OUTPUT_DATA_MASK_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA1_0_LD17_OUTPUT_DATA_MASK_MASKED _MK_ENUM_CONST(0) +#define DC_COM_PIN_OUTPUT_DATA1_0_LD17_OUTPUT_DATA_MASK_NOTMASKED _MK_ENUM_CONST(1) + +#define DC_COM_PIN_OUTPUT_DATA1_0_LPW0_OUTPUT_DATA_SHIFT _MK_SHIFT_CONST(16) +#define DC_COM_PIN_OUTPUT_DATA1_0_LPW0_OUTPUT_DATA_FIELD _MK_FIELD_CONST(0x1, DC_COM_PIN_OUTPUT_DATA1_0_LPW0_OUTPUT_DATA_SHIFT) +#define DC_COM_PIN_OUTPUT_DATA1_0_LPW0_OUTPUT_DATA_RANGE 16:16 +#define DC_COM_PIN_OUTPUT_DATA1_0_LPW0_OUTPUT_DATA_WOFFSET 0x0 +#define DC_COM_PIN_OUTPUT_DATA1_0_LPW0_OUTPUT_DATA_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA1_0_LPW0_OUTPUT_DATA_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_COM_PIN_OUTPUT_DATA1_0_LPW0_OUTPUT_DATA_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA1_0_LPW0_OUTPUT_DATA_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA1_0_LPW0_OUTPUT_DATA_LOW _MK_ENUM_CONST(0) +#define DC_COM_PIN_OUTPUT_DATA1_0_LPW0_OUTPUT_DATA_HIGH _MK_ENUM_CONST(1) + +#define DC_COM_PIN_OUTPUT_DATA1_0_LPW0_OUTPUT_DATA_MASK_SHIFT _MK_SHIFT_CONST(17) +#define DC_COM_PIN_OUTPUT_DATA1_0_LPW0_OUTPUT_DATA_MASK_FIELD _MK_FIELD_CONST(0x1, DC_COM_PIN_OUTPUT_DATA1_0_LPW0_OUTPUT_DATA_MASK_SHIFT) +#define DC_COM_PIN_OUTPUT_DATA1_0_LPW0_OUTPUT_DATA_MASK_RANGE 17:17 +#define DC_COM_PIN_OUTPUT_DATA1_0_LPW0_OUTPUT_DATA_MASK_WOFFSET 0x0 +#define DC_COM_PIN_OUTPUT_DATA1_0_LPW0_OUTPUT_DATA_MASK_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA1_0_LPW0_OUTPUT_DATA_MASK_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_COM_PIN_OUTPUT_DATA1_0_LPW0_OUTPUT_DATA_MASK_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA1_0_LPW0_OUTPUT_DATA_MASK_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA1_0_LPW0_OUTPUT_DATA_MASK_MASKED _MK_ENUM_CONST(0) +#define DC_COM_PIN_OUTPUT_DATA1_0_LPW0_OUTPUT_DATA_MASK_NOTMASKED _MK_ENUM_CONST(1) + +#define DC_COM_PIN_OUTPUT_DATA1_0_LPW1_OUTPUT_DATA_SHIFT _MK_SHIFT_CONST(18) +#define DC_COM_PIN_OUTPUT_DATA1_0_LPW1_OUTPUT_DATA_FIELD _MK_FIELD_CONST(0x1, DC_COM_PIN_OUTPUT_DATA1_0_LPW1_OUTPUT_DATA_SHIFT) +#define DC_COM_PIN_OUTPUT_DATA1_0_LPW1_OUTPUT_DATA_RANGE 18:18 +#define DC_COM_PIN_OUTPUT_DATA1_0_LPW1_OUTPUT_DATA_WOFFSET 0x0 +#define DC_COM_PIN_OUTPUT_DATA1_0_LPW1_OUTPUT_DATA_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA1_0_LPW1_OUTPUT_DATA_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_COM_PIN_OUTPUT_DATA1_0_LPW1_OUTPUT_DATA_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA1_0_LPW1_OUTPUT_DATA_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA1_0_LPW1_OUTPUT_DATA_LOW _MK_ENUM_CONST(0) +#define DC_COM_PIN_OUTPUT_DATA1_0_LPW1_OUTPUT_DATA_HIGH _MK_ENUM_CONST(1) + +#define DC_COM_PIN_OUTPUT_DATA1_0_LPW1_OUTPUT_DATA_MASK_SHIFT _MK_SHIFT_CONST(19) +#define DC_COM_PIN_OUTPUT_DATA1_0_LPW1_OUTPUT_DATA_MASK_FIELD _MK_FIELD_CONST(0x1, DC_COM_PIN_OUTPUT_DATA1_0_LPW1_OUTPUT_DATA_MASK_SHIFT) +#define DC_COM_PIN_OUTPUT_DATA1_0_LPW1_OUTPUT_DATA_MASK_RANGE 19:19 +#define DC_COM_PIN_OUTPUT_DATA1_0_LPW1_OUTPUT_DATA_MASK_WOFFSET 0x0 +#define DC_COM_PIN_OUTPUT_DATA1_0_LPW1_OUTPUT_DATA_MASK_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA1_0_LPW1_OUTPUT_DATA_MASK_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_COM_PIN_OUTPUT_DATA1_0_LPW1_OUTPUT_DATA_MASK_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA1_0_LPW1_OUTPUT_DATA_MASK_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA1_0_LPW1_OUTPUT_DATA_MASK_MASKED _MK_ENUM_CONST(0) +#define DC_COM_PIN_OUTPUT_DATA1_0_LPW1_OUTPUT_DATA_MASK_NOTMASKED _MK_ENUM_CONST(1) + +#define DC_COM_PIN_OUTPUT_DATA1_0_LPW2_OUTPUT_DATA_SHIFT _MK_SHIFT_CONST(20) +#define DC_COM_PIN_OUTPUT_DATA1_0_LPW2_OUTPUT_DATA_FIELD _MK_FIELD_CONST(0x1, DC_COM_PIN_OUTPUT_DATA1_0_LPW2_OUTPUT_DATA_SHIFT) +#define DC_COM_PIN_OUTPUT_DATA1_0_LPW2_OUTPUT_DATA_RANGE 20:20 +#define DC_COM_PIN_OUTPUT_DATA1_0_LPW2_OUTPUT_DATA_WOFFSET 0x0 +#define DC_COM_PIN_OUTPUT_DATA1_0_LPW2_OUTPUT_DATA_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA1_0_LPW2_OUTPUT_DATA_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_COM_PIN_OUTPUT_DATA1_0_LPW2_OUTPUT_DATA_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA1_0_LPW2_OUTPUT_DATA_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA1_0_LPW2_OUTPUT_DATA_LOW _MK_ENUM_CONST(0) +#define DC_COM_PIN_OUTPUT_DATA1_0_LPW2_OUTPUT_DATA_HIGH _MK_ENUM_CONST(1) + +#define DC_COM_PIN_OUTPUT_DATA1_0_LPW2_OUTPUT_DATA_MASK_SHIFT _MK_SHIFT_CONST(21) +#define DC_COM_PIN_OUTPUT_DATA1_0_LPW2_OUTPUT_DATA_MASK_FIELD _MK_FIELD_CONST(0x1, DC_COM_PIN_OUTPUT_DATA1_0_LPW2_OUTPUT_DATA_MASK_SHIFT) +#define DC_COM_PIN_OUTPUT_DATA1_0_LPW2_OUTPUT_DATA_MASK_RANGE 21:21 +#define DC_COM_PIN_OUTPUT_DATA1_0_LPW2_OUTPUT_DATA_MASK_WOFFSET 0x0 +#define DC_COM_PIN_OUTPUT_DATA1_0_LPW2_OUTPUT_DATA_MASK_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA1_0_LPW2_OUTPUT_DATA_MASK_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_COM_PIN_OUTPUT_DATA1_0_LPW2_OUTPUT_DATA_MASK_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA1_0_LPW2_OUTPUT_DATA_MASK_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA1_0_LPW2_OUTPUT_DATA_MASK_MASKED _MK_ENUM_CONST(0) +#define DC_COM_PIN_OUTPUT_DATA1_0_LPW2_OUTPUT_DATA_MASK_NOTMASKED _MK_ENUM_CONST(1) + +#define DC_COM_PIN_OUTPUT_DATA1_0_LSC0_OUTPUT_DATA_SHIFT _MK_SHIFT_CONST(24) +#define DC_COM_PIN_OUTPUT_DATA1_0_LSC0_OUTPUT_DATA_FIELD _MK_FIELD_CONST(0x1, DC_COM_PIN_OUTPUT_DATA1_0_LSC0_OUTPUT_DATA_SHIFT) +#define DC_COM_PIN_OUTPUT_DATA1_0_LSC0_OUTPUT_DATA_RANGE 24:24 +#define DC_COM_PIN_OUTPUT_DATA1_0_LSC0_OUTPUT_DATA_WOFFSET 0x0 +#define DC_COM_PIN_OUTPUT_DATA1_0_LSC0_OUTPUT_DATA_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA1_0_LSC0_OUTPUT_DATA_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_COM_PIN_OUTPUT_DATA1_0_LSC0_OUTPUT_DATA_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA1_0_LSC0_OUTPUT_DATA_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA1_0_LSC0_OUTPUT_DATA_LOW _MK_ENUM_CONST(0) +#define DC_COM_PIN_OUTPUT_DATA1_0_LSC0_OUTPUT_DATA_HIGH _MK_ENUM_CONST(1) + +#define DC_COM_PIN_OUTPUT_DATA1_0_LSC0_OUTPUT_DATA_MASK_SHIFT _MK_SHIFT_CONST(25) +#define DC_COM_PIN_OUTPUT_DATA1_0_LSC0_OUTPUT_DATA_MASK_FIELD _MK_FIELD_CONST(0x1, DC_COM_PIN_OUTPUT_DATA1_0_LSC0_OUTPUT_DATA_MASK_SHIFT) +#define DC_COM_PIN_OUTPUT_DATA1_0_LSC0_OUTPUT_DATA_MASK_RANGE 25:25 +#define DC_COM_PIN_OUTPUT_DATA1_0_LSC0_OUTPUT_DATA_MASK_WOFFSET 0x0 +#define DC_COM_PIN_OUTPUT_DATA1_0_LSC0_OUTPUT_DATA_MASK_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA1_0_LSC0_OUTPUT_DATA_MASK_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_COM_PIN_OUTPUT_DATA1_0_LSC0_OUTPUT_DATA_MASK_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA1_0_LSC0_OUTPUT_DATA_MASK_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA1_0_LSC0_OUTPUT_DATA_MASK_MASKED _MK_ENUM_CONST(0) +#define DC_COM_PIN_OUTPUT_DATA1_0_LSC0_OUTPUT_DATA_MASK_NOTMASKED _MK_ENUM_CONST(1) + +#define DC_COM_PIN_OUTPUT_DATA1_0_LSC1_OUTPUT_DATA_SHIFT _MK_SHIFT_CONST(26) +#define DC_COM_PIN_OUTPUT_DATA1_0_LSC1_OUTPUT_DATA_FIELD _MK_FIELD_CONST(0x1, DC_COM_PIN_OUTPUT_DATA1_0_LSC1_OUTPUT_DATA_SHIFT) +#define DC_COM_PIN_OUTPUT_DATA1_0_LSC1_OUTPUT_DATA_RANGE 26:26 +#define DC_COM_PIN_OUTPUT_DATA1_0_LSC1_OUTPUT_DATA_WOFFSET 0x0 +#define DC_COM_PIN_OUTPUT_DATA1_0_LSC1_OUTPUT_DATA_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA1_0_LSC1_OUTPUT_DATA_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_COM_PIN_OUTPUT_DATA1_0_LSC1_OUTPUT_DATA_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA1_0_LSC1_OUTPUT_DATA_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA1_0_LSC1_OUTPUT_DATA_LOW _MK_ENUM_CONST(0) +#define DC_COM_PIN_OUTPUT_DATA1_0_LSC1_OUTPUT_DATA_HIGH _MK_ENUM_CONST(1) + +#define DC_COM_PIN_OUTPUT_DATA1_0_LSC1_OUTPUT_DATA_MASK_SHIFT _MK_SHIFT_CONST(27) +#define DC_COM_PIN_OUTPUT_DATA1_0_LSC1_OUTPUT_DATA_MASK_FIELD _MK_FIELD_CONST(0x1, DC_COM_PIN_OUTPUT_DATA1_0_LSC1_OUTPUT_DATA_MASK_SHIFT) +#define DC_COM_PIN_OUTPUT_DATA1_0_LSC1_OUTPUT_DATA_MASK_RANGE 27:27 +#define DC_COM_PIN_OUTPUT_DATA1_0_LSC1_OUTPUT_DATA_MASK_WOFFSET 0x0 +#define DC_COM_PIN_OUTPUT_DATA1_0_LSC1_OUTPUT_DATA_MASK_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA1_0_LSC1_OUTPUT_DATA_MASK_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_COM_PIN_OUTPUT_DATA1_0_LSC1_OUTPUT_DATA_MASK_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA1_0_LSC1_OUTPUT_DATA_MASK_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA1_0_LSC1_OUTPUT_DATA_MASK_MASKED _MK_ENUM_CONST(0) +#define DC_COM_PIN_OUTPUT_DATA1_0_LSC1_OUTPUT_DATA_MASK_NOTMASKED _MK_ENUM_CONST(1) + +#define DC_COM_PIN_OUTPUT_DATA1_0_LVS_OUTPUT_DATA_SHIFT _MK_SHIFT_CONST(28) +#define DC_COM_PIN_OUTPUT_DATA1_0_LVS_OUTPUT_DATA_FIELD _MK_FIELD_CONST(0x1, DC_COM_PIN_OUTPUT_DATA1_0_LVS_OUTPUT_DATA_SHIFT) +#define DC_COM_PIN_OUTPUT_DATA1_0_LVS_OUTPUT_DATA_RANGE 28:28 +#define DC_COM_PIN_OUTPUT_DATA1_0_LVS_OUTPUT_DATA_WOFFSET 0x0 +#define DC_COM_PIN_OUTPUT_DATA1_0_LVS_OUTPUT_DATA_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA1_0_LVS_OUTPUT_DATA_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_COM_PIN_OUTPUT_DATA1_0_LVS_OUTPUT_DATA_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA1_0_LVS_OUTPUT_DATA_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA1_0_LVS_OUTPUT_DATA_LOW _MK_ENUM_CONST(0) +#define DC_COM_PIN_OUTPUT_DATA1_0_LVS_OUTPUT_DATA_HIGH _MK_ENUM_CONST(1) + +#define DC_COM_PIN_OUTPUT_DATA1_0_LVS_OUTPUT_DATA_MASK_SHIFT _MK_SHIFT_CONST(29) +#define DC_COM_PIN_OUTPUT_DATA1_0_LVS_OUTPUT_DATA_MASK_FIELD _MK_FIELD_CONST(0x1, DC_COM_PIN_OUTPUT_DATA1_0_LVS_OUTPUT_DATA_MASK_SHIFT) +#define DC_COM_PIN_OUTPUT_DATA1_0_LVS_OUTPUT_DATA_MASK_RANGE 29:29 +#define DC_COM_PIN_OUTPUT_DATA1_0_LVS_OUTPUT_DATA_MASK_WOFFSET 0x0 +#define DC_COM_PIN_OUTPUT_DATA1_0_LVS_OUTPUT_DATA_MASK_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA1_0_LVS_OUTPUT_DATA_MASK_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_COM_PIN_OUTPUT_DATA1_0_LVS_OUTPUT_DATA_MASK_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA1_0_LVS_OUTPUT_DATA_MASK_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA1_0_LVS_OUTPUT_DATA_MASK_MASKED _MK_ENUM_CONST(0) +#define DC_COM_PIN_OUTPUT_DATA1_0_LVS_OUTPUT_DATA_MASK_NOTMASKED _MK_ENUM_CONST(1) + +#define DC_COM_PIN_OUTPUT_DATA1_0_LHS_OUTPUT_DATA_SHIFT _MK_SHIFT_CONST(30) +#define DC_COM_PIN_OUTPUT_DATA1_0_LHS_OUTPUT_DATA_FIELD _MK_FIELD_CONST(0x1, DC_COM_PIN_OUTPUT_DATA1_0_LHS_OUTPUT_DATA_SHIFT) +#define DC_COM_PIN_OUTPUT_DATA1_0_LHS_OUTPUT_DATA_RANGE 30:30 +#define DC_COM_PIN_OUTPUT_DATA1_0_LHS_OUTPUT_DATA_WOFFSET 0x0 +#define DC_COM_PIN_OUTPUT_DATA1_0_LHS_OUTPUT_DATA_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA1_0_LHS_OUTPUT_DATA_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_COM_PIN_OUTPUT_DATA1_0_LHS_OUTPUT_DATA_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA1_0_LHS_OUTPUT_DATA_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA1_0_LHS_OUTPUT_DATA_LOW _MK_ENUM_CONST(0) +#define DC_COM_PIN_OUTPUT_DATA1_0_LHS_OUTPUT_DATA_HIGH _MK_ENUM_CONST(1) + +#define DC_COM_PIN_OUTPUT_DATA1_0_LHS_OUTPUT_DATA_MASK_SHIFT _MK_SHIFT_CONST(31) +#define DC_COM_PIN_OUTPUT_DATA1_0_LHS_OUTPUT_DATA_MASK_FIELD _MK_FIELD_CONST(0x1, DC_COM_PIN_OUTPUT_DATA1_0_LHS_OUTPUT_DATA_MASK_SHIFT) +#define DC_COM_PIN_OUTPUT_DATA1_0_LHS_OUTPUT_DATA_MASK_RANGE 31:31 +#define DC_COM_PIN_OUTPUT_DATA1_0_LHS_OUTPUT_DATA_MASK_WOFFSET 0x0 +#define DC_COM_PIN_OUTPUT_DATA1_0_LHS_OUTPUT_DATA_MASK_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA1_0_LHS_OUTPUT_DATA_MASK_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_COM_PIN_OUTPUT_DATA1_0_LHS_OUTPUT_DATA_MASK_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA1_0_LHS_OUTPUT_DATA_MASK_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA1_0_LHS_OUTPUT_DATA_MASK_MASKED _MK_ENUM_CONST(0) +#define DC_COM_PIN_OUTPUT_DATA1_0_LHS_OUTPUT_DATA_MASK_NOTMASKED _MK_ENUM_CONST(1) + + +// Register DC_COM_PIN_OUTPUT_DATA2_0 +#define DC_COM_PIN_OUTPUT_DATA2_0 _MK_ADDR_CONST(0x30c) +#define DC_COM_PIN_OUTPUT_DATA2_0_SECURE 0x0 +#define DC_COM_PIN_OUTPUT_DATA2_0_WORD_COUNT 0x1 +#define DC_COM_PIN_OUTPUT_DATA2_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA2_0_RESET_MASK _MK_MASK_CONST(0xff0f3f) +#define DC_COM_PIN_OUTPUT_DATA2_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA2_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA2_0_READ_MASK _MK_MASK_CONST(0x550515) +#define DC_COM_PIN_OUTPUT_DATA2_0_WRITE_MASK _MK_MASK_CONST(0xff0f3f) +#define DC_COM_PIN_OUTPUT_DATA2_0_LHP0_OUTPUT_DATA_SHIFT _MK_SHIFT_CONST(0) +#define DC_COM_PIN_OUTPUT_DATA2_0_LHP0_OUTPUT_DATA_FIELD _MK_FIELD_CONST(0x1, DC_COM_PIN_OUTPUT_DATA2_0_LHP0_OUTPUT_DATA_SHIFT) +#define DC_COM_PIN_OUTPUT_DATA2_0_LHP0_OUTPUT_DATA_RANGE 0:0 +#define DC_COM_PIN_OUTPUT_DATA2_0_LHP0_OUTPUT_DATA_WOFFSET 0x0 +#define DC_COM_PIN_OUTPUT_DATA2_0_LHP0_OUTPUT_DATA_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA2_0_LHP0_OUTPUT_DATA_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_COM_PIN_OUTPUT_DATA2_0_LHP0_OUTPUT_DATA_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA2_0_LHP0_OUTPUT_DATA_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA2_0_LHP0_OUTPUT_DATA_LOW _MK_ENUM_CONST(0) +#define DC_COM_PIN_OUTPUT_DATA2_0_LHP0_OUTPUT_DATA_HIGH _MK_ENUM_CONST(1) + +#define DC_COM_PIN_OUTPUT_DATA2_0_LHP0_OUTPUT_DATA_MASK_SHIFT _MK_SHIFT_CONST(1) +#define DC_COM_PIN_OUTPUT_DATA2_0_LHP0_OUTPUT_DATA_MASK_FIELD _MK_FIELD_CONST(0x1, DC_COM_PIN_OUTPUT_DATA2_0_LHP0_OUTPUT_DATA_MASK_SHIFT) +#define DC_COM_PIN_OUTPUT_DATA2_0_LHP0_OUTPUT_DATA_MASK_RANGE 1:1 +#define DC_COM_PIN_OUTPUT_DATA2_0_LHP0_OUTPUT_DATA_MASK_WOFFSET 0x0 +#define DC_COM_PIN_OUTPUT_DATA2_0_LHP0_OUTPUT_DATA_MASK_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA2_0_LHP0_OUTPUT_DATA_MASK_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_COM_PIN_OUTPUT_DATA2_0_LHP0_OUTPUT_DATA_MASK_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA2_0_LHP0_OUTPUT_DATA_MASK_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA2_0_LHP0_OUTPUT_DATA_MASK_MASKED _MK_ENUM_CONST(0) +#define DC_COM_PIN_OUTPUT_DATA2_0_LHP0_OUTPUT_DATA_MASK_NOTMASKED _MK_ENUM_CONST(1) + +#define DC_COM_PIN_OUTPUT_DATA2_0_LHP1_OUTPUT_DATA_SHIFT _MK_SHIFT_CONST(2) +#define DC_COM_PIN_OUTPUT_DATA2_0_LHP1_OUTPUT_DATA_FIELD _MK_FIELD_CONST(0x1, DC_COM_PIN_OUTPUT_DATA2_0_LHP1_OUTPUT_DATA_SHIFT) +#define DC_COM_PIN_OUTPUT_DATA2_0_LHP1_OUTPUT_DATA_RANGE 2:2 +#define DC_COM_PIN_OUTPUT_DATA2_0_LHP1_OUTPUT_DATA_WOFFSET 0x0 +#define DC_COM_PIN_OUTPUT_DATA2_0_LHP1_OUTPUT_DATA_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA2_0_LHP1_OUTPUT_DATA_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_COM_PIN_OUTPUT_DATA2_0_LHP1_OUTPUT_DATA_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA2_0_LHP1_OUTPUT_DATA_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA2_0_LHP1_OUTPUT_DATA_LOW _MK_ENUM_CONST(0) +#define DC_COM_PIN_OUTPUT_DATA2_0_LHP1_OUTPUT_DATA_HIGH _MK_ENUM_CONST(1) + +#define DC_COM_PIN_OUTPUT_DATA2_0_LHP1_OUTPUT_DATA_MASK_SHIFT _MK_SHIFT_CONST(3) +#define DC_COM_PIN_OUTPUT_DATA2_0_LHP1_OUTPUT_DATA_MASK_FIELD _MK_FIELD_CONST(0x1, DC_COM_PIN_OUTPUT_DATA2_0_LHP1_OUTPUT_DATA_MASK_SHIFT) +#define DC_COM_PIN_OUTPUT_DATA2_0_LHP1_OUTPUT_DATA_MASK_RANGE 3:3 +#define DC_COM_PIN_OUTPUT_DATA2_0_LHP1_OUTPUT_DATA_MASK_WOFFSET 0x0 +#define DC_COM_PIN_OUTPUT_DATA2_0_LHP1_OUTPUT_DATA_MASK_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA2_0_LHP1_OUTPUT_DATA_MASK_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_COM_PIN_OUTPUT_DATA2_0_LHP1_OUTPUT_DATA_MASK_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA2_0_LHP1_OUTPUT_DATA_MASK_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA2_0_LHP1_OUTPUT_DATA_MASK_MASKED _MK_ENUM_CONST(0) +#define DC_COM_PIN_OUTPUT_DATA2_0_LHP1_OUTPUT_DATA_MASK_NOTMASKED _MK_ENUM_CONST(1) + +#define DC_COM_PIN_OUTPUT_DATA2_0_LHP2_OUTPUT_DATA_SHIFT _MK_SHIFT_CONST(4) +#define DC_COM_PIN_OUTPUT_DATA2_0_LHP2_OUTPUT_DATA_FIELD _MK_FIELD_CONST(0x1, DC_COM_PIN_OUTPUT_DATA2_0_LHP2_OUTPUT_DATA_SHIFT) +#define DC_COM_PIN_OUTPUT_DATA2_0_LHP2_OUTPUT_DATA_RANGE 4:4 +#define DC_COM_PIN_OUTPUT_DATA2_0_LHP2_OUTPUT_DATA_WOFFSET 0x0 +#define DC_COM_PIN_OUTPUT_DATA2_0_LHP2_OUTPUT_DATA_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA2_0_LHP2_OUTPUT_DATA_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_COM_PIN_OUTPUT_DATA2_0_LHP2_OUTPUT_DATA_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA2_0_LHP2_OUTPUT_DATA_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA2_0_LHP2_OUTPUT_DATA_LOW _MK_ENUM_CONST(0) +#define DC_COM_PIN_OUTPUT_DATA2_0_LHP2_OUTPUT_DATA_HIGH _MK_ENUM_CONST(1) + +#define DC_COM_PIN_OUTPUT_DATA2_0_LHP2_OUTPUT_DATA_MASK_SHIFT _MK_SHIFT_CONST(5) +#define DC_COM_PIN_OUTPUT_DATA2_0_LHP2_OUTPUT_DATA_MASK_FIELD _MK_FIELD_CONST(0x1, DC_COM_PIN_OUTPUT_DATA2_0_LHP2_OUTPUT_DATA_MASK_SHIFT) +#define DC_COM_PIN_OUTPUT_DATA2_0_LHP2_OUTPUT_DATA_MASK_RANGE 5:5 +#define DC_COM_PIN_OUTPUT_DATA2_0_LHP2_OUTPUT_DATA_MASK_WOFFSET 0x0 +#define DC_COM_PIN_OUTPUT_DATA2_0_LHP2_OUTPUT_DATA_MASK_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA2_0_LHP2_OUTPUT_DATA_MASK_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_COM_PIN_OUTPUT_DATA2_0_LHP2_OUTPUT_DATA_MASK_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA2_0_LHP2_OUTPUT_DATA_MASK_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA2_0_LHP2_OUTPUT_DATA_MASK_MASKED _MK_ENUM_CONST(0) +#define DC_COM_PIN_OUTPUT_DATA2_0_LHP2_OUTPUT_DATA_MASK_NOTMASKED _MK_ENUM_CONST(1) + +#define DC_COM_PIN_OUTPUT_DATA2_0_LVP0_OUTPUT_DATA_SHIFT _MK_SHIFT_CONST(8) +#define DC_COM_PIN_OUTPUT_DATA2_0_LVP0_OUTPUT_DATA_FIELD _MK_FIELD_CONST(0x1, DC_COM_PIN_OUTPUT_DATA2_0_LVP0_OUTPUT_DATA_SHIFT) +#define DC_COM_PIN_OUTPUT_DATA2_0_LVP0_OUTPUT_DATA_RANGE 8:8 +#define DC_COM_PIN_OUTPUT_DATA2_0_LVP0_OUTPUT_DATA_WOFFSET 0x0 +#define DC_COM_PIN_OUTPUT_DATA2_0_LVP0_OUTPUT_DATA_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA2_0_LVP0_OUTPUT_DATA_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_COM_PIN_OUTPUT_DATA2_0_LVP0_OUTPUT_DATA_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA2_0_LVP0_OUTPUT_DATA_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA2_0_LVP0_OUTPUT_DATA_LOW _MK_ENUM_CONST(0) +#define DC_COM_PIN_OUTPUT_DATA2_0_LVP0_OUTPUT_DATA_HIGH _MK_ENUM_CONST(1) + +#define DC_COM_PIN_OUTPUT_DATA2_0_LVP0_OUTPUT_DATA_MASK_SHIFT _MK_SHIFT_CONST(9) +#define DC_COM_PIN_OUTPUT_DATA2_0_LVP0_OUTPUT_DATA_MASK_FIELD _MK_FIELD_CONST(0x1, DC_COM_PIN_OUTPUT_DATA2_0_LVP0_OUTPUT_DATA_MASK_SHIFT) +#define DC_COM_PIN_OUTPUT_DATA2_0_LVP0_OUTPUT_DATA_MASK_RANGE 9:9 +#define DC_COM_PIN_OUTPUT_DATA2_0_LVP0_OUTPUT_DATA_MASK_WOFFSET 0x0 +#define DC_COM_PIN_OUTPUT_DATA2_0_LVP0_OUTPUT_DATA_MASK_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA2_0_LVP0_OUTPUT_DATA_MASK_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_COM_PIN_OUTPUT_DATA2_0_LVP0_OUTPUT_DATA_MASK_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA2_0_LVP0_OUTPUT_DATA_MASK_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA2_0_LVP0_OUTPUT_DATA_MASK_MASKED _MK_ENUM_CONST(0) +#define DC_COM_PIN_OUTPUT_DATA2_0_LVP0_OUTPUT_DATA_MASK_NOTMASKED _MK_ENUM_CONST(1) + +#define DC_COM_PIN_OUTPUT_DATA2_0_LVP1_OUTPUT_DATA_SHIFT _MK_SHIFT_CONST(10) +#define DC_COM_PIN_OUTPUT_DATA2_0_LVP1_OUTPUT_DATA_FIELD _MK_FIELD_CONST(0x1, DC_COM_PIN_OUTPUT_DATA2_0_LVP1_OUTPUT_DATA_SHIFT) +#define DC_COM_PIN_OUTPUT_DATA2_0_LVP1_OUTPUT_DATA_RANGE 10:10 +#define DC_COM_PIN_OUTPUT_DATA2_0_LVP1_OUTPUT_DATA_WOFFSET 0x0 +#define DC_COM_PIN_OUTPUT_DATA2_0_LVP1_OUTPUT_DATA_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA2_0_LVP1_OUTPUT_DATA_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_COM_PIN_OUTPUT_DATA2_0_LVP1_OUTPUT_DATA_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA2_0_LVP1_OUTPUT_DATA_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA2_0_LVP1_OUTPUT_DATA_LOW _MK_ENUM_CONST(0) +#define DC_COM_PIN_OUTPUT_DATA2_0_LVP1_OUTPUT_DATA_HIGH _MK_ENUM_CONST(1) + +#define DC_COM_PIN_OUTPUT_DATA2_0_LVP1_OUTPUT_DATA_MASK_SHIFT _MK_SHIFT_CONST(11) +#define DC_COM_PIN_OUTPUT_DATA2_0_LVP1_OUTPUT_DATA_MASK_FIELD _MK_FIELD_CONST(0x1, DC_COM_PIN_OUTPUT_DATA2_0_LVP1_OUTPUT_DATA_MASK_SHIFT) +#define DC_COM_PIN_OUTPUT_DATA2_0_LVP1_OUTPUT_DATA_MASK_RANGE 11:11 +#define DC_COM_PIN_OUTPUT_DATA2_0_LVP1_OUTPUT_DATA_MASK_WOFFSET 0x0 +#define DC_COM_PIN_OUTPUT_DATA2_0_LVP1_OUTPUT_DATA_MASK_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA2_0_LVP1_OUTPUT_DATA_MASK_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_COM_PIN_OUTPUT_DATA2_0_LVP1_OUTPUT_DATA_MASK_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA2_0_LVP1_OUTPUT_DATA_MASK_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA2_0_LVP1_OUTPUT_DATA_MASK_MASKED _MK_ENUM_CONST(0) +#define DC_COM_PIN_OUTPUT_DATA2_0_LVP1_OUTPUT_DATA_MASK_NOTMASKED _MK_ENUM_CONST(1) + +#define DC_COM_PIN_OUTPUT_DATA2_0_LM0_OUTPUT_DATA_SHIFT _MK_SHIFT_CONST(16) +#define DC_COM_PIN_OUTPUT_DATA2_0_LM0_OUTPUT_DATA_FIELD _MK_FIELD_CONST(0x1, DC_COM_PIN_OUTPUT_DATA2_0_LM0_OUTPUT_DATA_SHIFT) +#define DC_COM_PIN_OUTPUT_DATA2_0_LM0_OUTPUT_DATA_RANGE 16:16 +#define DC_COM_PIN_OUTPUT_DATA2_0_LM0_OUTPUT_DATA_WOFFSET 0x0 +#define DC_COM_PIN_OUTPUT_DATA2_0_LM0_OUTPUT_DATA_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA2_0_LM0_OUTPUT_DATA_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_COM_PIN_OUTPUT_DATA2_0_LM0_OUTPUT_DATA_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA2_0_LM0_OUTPUT_DATA_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA2_0_LM0_OUTPUT_DATA_LOW _MK_ENUM_CONST(0) +#define DC_COM_PIN_OUTPUT_DATA2_0_LM0_OUTPUT_DATA_HIGH _MK_ENUM_CONST(1) + +#define DC_COM_PIN_OUTPUT_DATA2_0_LM0_OUTPUT_DATA_MASK_SHIFT _MK_SHIFT_CONST(17) +#define DC_COM_PIN_OUTPUT_DATA2_0_LM0_OUTPUT_DATA_MASK_FIELD _MK_FIELD_CONST(0x1, DC_COM_PIN_OUTPUT_DATA2_0_LM0_OUTPUT_DATA_MASK_SHIFT) +#define DC_COM_PIN_OUTPUT_DATA2_0_LM0_OUTPUT_DATA_MASK_RANGE 17:17 +#define DC_COM_PIN_OUTPUT_DATA2_0_LM0_OUTPUT_DATA_MASK_WOFFSET 0x0 +#define DC_COM_PIN_OUTPUT_DATA2_0_LM0_OUTPUT_DATA_MASK_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA2_0_LM0_OUTPUT_DATA_MASK_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_COM_PIN_OUTPUT_DATA2_0_LM0_OUTPUT_DATA_MASK_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA2_0_LM0_OUTPUT_DATA_MASK_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA2_0_LM0_OUTPUT_DATA_MASK_MASKED _MK_ENUM_CONST(0) +#define DC_COM_PIN_OUTPUT_DATA2_0_LM0_OUTPUT_DATA_MASK_NOTMASKED _MK_ENUM_CONST(1) + +#define DC_COM_PIN_OUTPUT_DATA2_0_LM1_OUTPUT_DATA_SHIFT _MK_SHIFT_CONST(18) +#define DC_COM_PIN_OUTPUT_DATA2_0_LM1_OUTPUT_DATA_FIELD _MK_FIELD_CONST(0x1, DC_COM_PIN_OUTPUT_DATA2_0_LM1_OUTPUT_DATA_SHIFT) +#define DC_COM_PIN_OUTPUT_DATA2_0_LM1_OUTPUT_DATA_RANGE 18:18 +#define DC_COM_PIN_OUTPUT_DATA2_0_LM1_OUTPUT_DATA_WOFFSET 0x0 +#define DC_COM_PIN_OUTPUT_DATA2_0_LM1_OUTPUT_DATA_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA2_0_LM1_OUTPUT_DATA_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_COM_PIN_OUTPUT_DATA2_0_LM1_OUTPUT_DATA_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA2_0_LM1_OUTPUT_DATA_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA2_0_LM1_OUTPUT_DATA_LOW _MK_ENUM_CONST(0) +#define DC_COM_PIN_OUTPUT_DATA2_0_LM1_OUTPUT_DATA_HIGH _MK_ENUM_CONST(1) + +#define DC_COM_PIN_OUTPUT_DATA2_0_LM1_OUTPUT_DATA_MASK_SHIFT _MK_SHIFT_CONST(19) +#define DC_COM_PIN_OUTPUT_DATA2_0_LM1_OUTPUT_DATA_MASK_FIELD _MK_FIELD_CONST(0x1, DC_COM_PIN_OUTPUT_DATA2_0_LM1_OUTPUT_DATA_MASK_SHIFT) +#define DC_COM_PIN_OUTPUT_DATA2_0_LM1_OUTPUT_DATA_MASK_RANGE 19:19 +#define DC_COM_PIN_OUTPUT_DATA2_0_LM1_OUTPUT_DATA_MASK_WOFFSET 0x0 +#define DC_COM_PIN_OUTPUT_DATA2_0_LM1_OUTPUT_DATA_MASK_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA2_0_LM1_OUTPUT_DATA_MASK_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_COM_PIN_OUTPUT_DATA2_0_LM1_OUTPUT_DATA_MASK_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA2_0_LM1_OUTPUT_DATA_MASK_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA2_0_LM1_OUTPUT_DATA_MASK_MASKED _MK_ENUM_CONST(0) +#define DC_COM_PIN_OUTPUT_DATA2_0_LM1_OUTPUT_DATA_MASK_NOTMASKED _MK_ENUM_CONST(1) + +#define DC_COM_PIN_OUTPUT_DATA2_0_LDI_OUTPUT_DATA_SHIFT _MK_SHIFT_CONST(20) +#define DC_COM_PIN_OUTPUT_DATA2_0_LDI_OUTPUT_DATA_FIELD _MK_FIELD_CONST(0x1, DC_COM_PIN_OUTPUT_DATA2_0_LDI_OUTPUT_DATA_SHIFT) +#define DC_COM_PIN_OUTPUT_DATA2_0_LDI_OUTPUT_DATA_RANGE 20:20 +#define DC_COM_PIN_OUTPUT_DATA2_0_LDI_OUTPUT_DATA_WOFFSET 0x0 +#define DC_COM_PIN_OUTPUT_DATA2_0_LDI_OUTPUT_DATA_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA2_0_LDI_OUTPUT_DATA_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_COM_PIN_OUTPUT_DATA2_0_LDI_OUTPUT_DATA_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA2_0_LDI_OUTPUT_DATA_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA2_0_LDI_OUTPUT_DATA_LOW _MK_ENUM_CONST(0) +#define DC_COM_PIN_OUTPUT_DATA2_0_LDI_OUTPUT_DATA_HIGH _MK_ENUM_CONST(1) + +#define DC_COM_PIN_OUTPUT_DATA2_0_LDI_OUTPUT_DATA_MASK_SHIFT _MK_SHIFT_CONST(21) +#define DC_COM_PIN_OUTPUT_DATA2_0_LDI_OUTPUT_DATA_MASK_FIELD _MK_FIELD_CONST(0x1, DC_COM_PIN_OUTPUT_DATA2_0_LDI_OUTPUT_DATA_MASK_SHIFT) +#define DC_COM_PIN_OUTPUT_DATA2_0_LDI_OUTPUT_DATA_MASK_RANGE 21:21 +#define DC_COM_PIN_OUTPUT_DATA2_0_LDI_OUTPUT_DATA_MASK_WOFFSET 0x0 +#define DC_COM_PIN_OUTPUT_DATA2_0_LDI_OUTPUT_DATA_MASK_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA2_0_LDI_OUTPUT_DATA_MASK_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_COM_PIN_OUTPUT_DATA2_0_LDI_OUTPUT_DATA_MASK_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA2_0_LDI_OUTPUT_DATA_MASK_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA2_0_LDI_OUTPUT_DATA_MASK_MASKED _MK_ENUM_CONST(0) +#define DC_COM_PIN_OUTPUT_DATA2_0_LDI_OUTPUT_DATA_MASK_NOTMASKED _MK_ENUM_CONST(1) + +#define DC_COM_PIN_OUTPUT_DATA2_0_LPP_OUTPUT_DATA_SHIFT _MK_SHIFT_CONST(22) +#define DC_COM_PIN_OUTPUT_DATA2_0_LPP_OUTPUT_DATA_FIELD _MK_FIELD_CONST(0x1, DC_COM_PIN_OUTPUT_DATA2_0_LPP_OUTPUT_DATA_SHIFT) +#define DC_COM_PIN_OUTPUT_DATA2_0_LPP_OUTPUT_DATA_RANGE 22:22 +#define DC_COM_PIN_OUTPUT_DATA2_0_LPP_OUTPUT_DATA_WOFFSET 0x0 +#define DC_COM_PIN_OUTPUT_DATA2_0_LPP_OUTPUT_DATA_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA2_0_LPP_OUTPUT_DATA_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_COM_PIN_OUTPUT_DATA2_0_LPP_OUTPUT_DATA_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA2_0_LPP_OUTPUT_DATA_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA2_0_LPP_OUTPUT_DATA_LOW _MK_ENUM_CONST(0) +#define DC_COM_PIN_OUTPUT_DATA2_0_LPP_OUTPUT_DATA_HIGH _MK_ENUM_CONST(1) + +#define DC_COM_PIN_OUTPUT_DATA2_0_LPP_OUTPUT_DATA_MASK_SHIFT _MK_SHIFT_CONST(23) +#define DC_COM_PIN_OUTPUT_DATA2_0_LPP_OUTPUT_DATA_MASK_FIELD _MK_FIELD_CONST(0x1, DC_COM_PIN_OUTPUT_DATA2_0_LPP_OUTPUT_DATA_MASK_SHIFT) +#define DC_COM_PIN_OUTPUT_DATA2_0_LPP_OUTPUT_DATA_MASK_RANGE 23:23 +#define DC_COM_PIN_OUTPUT_DATA2_0_LPP_OUTPUT_DATA_MASK_WOFFSET 0x0 +#define DC_COM_PIN_OUTPUT_DATA2_0_LPP_OUTPUT_DATA_MASK_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA2_0_LPP_OUTPUT_DATA_MASK_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_COM_PIN_OUTPUT_DATA2_0_LPP_OUTPUT_DATA_MASK_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA2_0_LPP_OUTPUT_DATA_MASK_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA2_0_LPP_OUTPUT_DATA_MASK_MASKED _MK_ENUM_CONST(0) +#define DC_COM_PIN_OUTPUT_DATA2_0_LPP_OUTPUT_DATA_MASK_NOTMASKED _MK_ENUM_CONST(1) + + +// Register DC_COM_PIN_OUTPUT_DATA3_0 +#define DC_COM_PIN_OUTPUT_DATA3_0 _MK_ADDR_CONST(0x30d) +#define DC_COM_PIN_OUTPUT_DATA3_0_SECURE 0x0 +#define DC_COM_PIN_OUTPUT_DATA3_0_WORD_COUNT 0x1 +#define DC_COM_PIN_OUTPUT_DATA3_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA3_0_RESET_MASK _MK_MASK_CONST(0xfff) +#define DC_COM_PIN_OUTPUT_DATA3_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA3_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA3_0_READ_MASK _MK_MASK_CONST(0x555) +#define DC_COM_PIN_OUTPUT_DATA3_0_WRITE_MASK _MK_MASK_CONST(0xfff) +#define DC_COM_PIN_OUTPUT_DATA3_0_LSCK_OUTPUT_DATA_SHIFT _MK_SHIFT_CONST(0) +#define DC_COM_PIN_OUTPUT_DATA3_0_LSCK_OUTPUT_DATA_FIELD _MK_FIELD_CONST(0x1, DC_COM_PIN_OUTPUT_DATA3_0_LSCK_OUTPUT_DATA_SHIFT) +#define DC_COM_PIN_OUTPUT_DATA3_0_LSCK_OUTPUT_DATA_RANGE 0:0 +#define DC_COM_PIN_OUTPUT_DATA3_0_LSCK_OUTPUT_DATA_WOFFSET 0x0 +#define DC_COM_PIN_OUTPUT_DATA3_0_LSCK_OUTPUT_DATA_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA3_0_LSCK_OUTPUT_DATA_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_COM_PIN_OUTPUT_DATA3_0_LSCK_OUTPUT_DATA_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA3_0_LSCK_OUTPUT_DATA_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA3_0_LSCK_OUTPUT_DATA_LOW _MK_ENUM_CONST(0) +#define DC_COM_PIN_OUTPUT_DATA3_0_LSCK_OUTPUT_DATA_HIGH _MK_ENUM_CONST(1) + +#define DC_COM_PIN_OUTPUT_DATA3_0_LSCK_OUTPUT_DATA_MASK_SHIFT _MK_SHIFT_CONST(1) +#define DC_COM_PIN_OUTPUT_DATA3_0_LSCK_OUTPUT_DATA_MASK_FIELD _MK_FIELD_CONST(0x1, DC_COM_PIN_OUTPUT_DATA3_0_LSCK_OUTPUT_DATA_MASK_SHIFT) +#define DC_COM_PIN_OUTPUT_DATA3_0_LSCK_OUTPUT_DATA_MASK_RANGE 1:1 +#define DC_COM_PIN_OUTPUT_DATA3_0_LSCK_OUTPUT_DATA_MASK_WOFFSET 0x0 +#define DC_COM_PIN_OUTPUT_DATA3_0_LSCK_OUTPUT_DATA_MASK_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA3_0_LSCK_OUTPUT_DATA_MASK_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_COM_PIN_OUTPUT_DATA3_0_LSCK_OUTPUT_DATA_MASK_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA3_0_LSCK_OUTPUT_DATA_MASK_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA3_0_LSCK_OUTPUT_DATA_MASK_MASKED _MK_ENUM_CONST(0) +#define DC_COM_PIN_OUTPUT_DATA3_0_LSCK_OUTPUT_DATA_MASK_NOTMASKED _MK_ENUM_CONST(1) + +#define DC_COM_PIN_OUTPUT_DATA3_0_LSDA_OUTPUT_DATA_SHIFT _MK_SHIFT_CONST(2) +#define DC_COM_PIN_OUTPUT_DATA3_0_LSDA_OUTPUT_DATA_FIELD _MK_FIELD_CONST(0x1, DC_COM_PIN_OUTPUT_DATA3_0_LSDA_OUTPUT_DATA_SHIFT) +#define DC_COM_PIN_OUTPUT_DATA3_0_LSDA_OUTPUT_DATA_RANGE 2:2 +#define DC_COM_PIN_OUTPUT_DATA3_0_LSDA_OUTPUT_DATA_WOFFSET 0x0 +#define DC_COM_PIN_OUTPUT_DATA3_0_LSDA_OUTPUT_DATA_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA3_0_LSDA_OUTPUT_DATA_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_COM_PIN_OUTPUT_DATA3_0_LSDA_OUTPUT_DATA_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA3_0_LSDA_OUTPUT_DATA_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA3_0_LSDA_OUTPUT_DATA_LOW _MK_ENUM_CONST(0) +#define DC_COM_PIN_OUTPUT_DATA3_0_LSDA_OUTPUT_DATA_HIGH _MK_ENUM_CONST(1) + +#define DC_COM_PIN_OUTPUT_DATA3_0_LSDA_OUTPUT_DATA_MASK_SHIFT _MK_SHIFT_CONST(3) +#define DC_COM_PIN_OUTPUT_DATA3_0_LSDA_OUTPUT_DATA_MASK_FIELD _MK_FIELD_CONST(0x1, DC_COM_PIN_OUTPUT_DATA3_0_LSDA_OUTPUT_DATA_MASK_SHIFT) +#define DC_COM_PIN_OUTPUT_DATA3_0_LSDA_OUTPUT_DATA_MASK_RANGE 3:3 +#define DC_COM_PIN_OUTPUT_DATA3_0_LSDA_OUTPUT_DATA_MASK_WOFFSET 0x0 +#define DC_COM_PIN_OUTPUT_DATA3_0_LSDA_OUTPUT_DATA_MASK_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA3_0_LSDA_OUTPUT_DATA_MASK_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_COM_PIN_OUTPUT_DATA3_0_LSDA_OUTPUT_DATA_MASK_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA3_0_LSDA_OUTPUT_DATA_MASK_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA3_0_LSDA_OUTPUT_DATA_MASK_MASKED _MK_ENUM_CONST(0) +#define DC_COM_PIN_OUTPUT_DATA3_0_LSDA_OUTPUT_DATA_MASK_NOTMASKED _MK_ENUM_CONST(1) + +#define DC_COM_PIN_OUTPUT_DATA3_0_LCSN_OUTPUT_DATA_SHIFT _MK_SHIFT_CONST(4) +#define DC_COM_PIN_OUTPUT_DATA3_0_LCSN_OUTPUT_DATA_FIELD _MK_FIELD_CONST(0x1, DC_COM_PIN_OUTPUT_DATA3_0_LCSN_OUTPUT_DATA_SHIFT) +#define DC_COM_PIN_OUTPUT_DATA3_0_LCSN_OUTPUT_DATA_RANGE 4:4 +#define DC_COM_PIN_OUTPUT_DATA3_0_LCSN_OUTPUT_DATA_WOFFSET 0x0 +#define DC_COM_PIN_OUTPUT_DATA3_0_LCSN_OUTPUT_DATA_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA3_0_LCSN_OUTPUT_DATA_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_COM_PIN_OUTPUT_DATA3_0_LCSN_OUTPUT_DATA_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA3_0_LCSN_OUTPUT_DATA_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA3_0_LCSN_OUTPUT_DATA_LOW _MK_ENUM_CONST(0) +#define DC_COM_PIN_OUTPUT_DATA3_0_LCSN_OUTPUT_DATA_HIGH _MK_ENUM_CONST(1) + +#define DC_COM_PIN_OUTPUT_DATA3_0_LCSN_OUTPUT_DATA_MASK_SHIFT _MK_SHIFT_CONST(5) +#define DC_COM_PIN_OUTPUT_DATA3_0_LCSN_OUTPUT_DATA_MASK_FIELD _MK_FIELD_CONST(0x1, DC_COM_PIN_OUTPUT_DATA3_0_LCSN_OUTPUT_DATA_MASK_SHIFT) +#define DC_COM_PIN_OUTPUT_DATA3_0_LCSN_OUTPUT_DATA_MASK_RANGE 5:5 +#define DC_COM_PIN_OUTPUT_DATA3_0_LCSN_OUTPUT_DATA_MASK_WOFFSET 0x0 +#define DC_COM_PIN_OUTPUT_DATA3_0_LCSN_OUTPUT_DATA_MASK_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA3_0_LCSN_OUTPUT_DATA_MASK_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_COM_PIN_OUTPUT_DATA3_0_LCSN_OUTPUT_DATA_MASK_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA3_0_LCSN_OUTPUT_DATA_MASK_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA3_0_LCSN_OUTPUT_DATA_MASK_MASKED _MK_ENUM_CONST(0) +#define DC_COM_PIN_OUTPUT_DATA3_0_LCSN_OUTPUT_DATA_MASK_NOTMASKED _MK_ENUM_CONST(1) + +#define DC_COM_PIN_OUTPUT_DATA3_0_LDC_OUTPUT_DATA_SHIFT _MK_SHIFT_CONST(6) +#define DC_COM_PIN_OUTPUT_DATA3_0_LDC_OUTPUT_DATA_FIELD _MK_FIELD_CONST(0x1, DC_COM_PIN_OUTPUT_DATA3_0_LDC_OUTPUT_DATA_SHIFT) +#define DC_COM_PIN_OUTPUT_DATA3_0_LDC_OUTPUT_DATA_RANGE 6:6 +#define DC_COM_PIN_OUTPUT_DATA3_0_LDC_OUTPUT_DATA_WOFFSET 0x0 +#define DC_COM_PIN_OUTPUT_DATA3_0_LDC_OUTPUT_DATA_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA3_0_LDC_OUTPUT_DATA_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_COM_PIN_OUTPUT_DATA3_0_LDC_OUTPUT_DATA_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA3_0_LDC_OUTPUT_DATA_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA3_0_LDC_OUTPUT_DATA_LOW _MK_ENUM_CONST(0) +#define DC_COM_PIN_OUTPUT_DATA3_0_LDC_OUTPUT_DATA_HIGH _MK_ENUM_CONST(1) + +#define DC_COM_PIN_OUTPUT_DATA3_0_LDC_OUTPUT_DATA_MASK_SHIFT _MK_SHIFT_CONST(7) +#define DC_COM_PIN_OUTPUT_DATA3_0_LDC_OUTPUT_DATA_MASK_FIELD _MK_FIELD_CONST(0x1, DC_COM_PIN_OUTPUT_DATA3_0_LDC_OUTPUT_DATA_MASK_SHIFT) +#define DC_COM_PIN_OUTPUT_DATA3_0_LDC_OUTPUT_DATA_MASK_RANGE 7:7 +#define DC_COM_PIN_OUTPUT_DATA3_0_LDC_OUTPUT_DATA_MASK_WOFFSET 0x0 +#define DC_COM_PIN_OUTPUT_DATA3_0_LDC_OUTPUT_DATA_MASK_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA3_0_LDC_OUTPUT_DATA_MASK_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_COM_PIN_OUTPUT_DATA3_0_LDC_OUTPUT_DATA_MASK_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA3_0_LDC_OUTPUT_DATA_MASK_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA3_0_LDC_OUTPUT_DATA_MASK_MASKED _MK_ENUM_CONST(0) +#define DC_COM_PIN_OUTPUT_DATA3_0_LDC_OUTPUT_DATA_MASK_NOTMASKED _MK_ENUM_CONST(1) + +#define DC_COM_PIN_OUTPUT_DATA3_0_LSPI_OUTPUT_DATA_SHIFT _MK_SHIFT_CONST(8) +#define DC_COM_PIN_OUTPUT_DATA3_0_LSPI_OUTPUT_DATA_FIELD _MK_FIELD_CONST(0x1, DC_COM_PIN_OUTPUT_DATA3_0_LSPI_OUTPUT_DATA_SHIFT) +#define DC_COM_PIN_OUTPUT_DATA3_0_LSPI_OUTPUT_DATA_RANGE 8:8 +#define DC_COM_PIN_OUTPUT_DATA3_0_LSPI_OUTPUT_DATA_WOFFSET 0x0 +#define DC_COM_PIN_OUTPUT_DATA3_0_LSPI_OUTPUT_DATA_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA3_0_LSPI_OUTPUT_DATA_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_COM_PIN_OUTPUT_DATA3_0_LSPI_OUTPUT_DATA_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA3_0_LSPI_OUTPUT_DATA_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA3_0_LSPI_OUTPUT_DATA_LOW _MK_ENUM_CONST(0) +#define DC_COM_PIN_OUTPUT_DATA3_0_LSPI_OUTPUT_DATA_HIGH _MK_ENUM_CONST(1) + +#define DC_COM_PIN_OUTPUT_DATA3_0_LSPI_OUTPUT_DATA_MASK_SHIFT _MK_SHIFT_CONST(9) +#define DC_COM_PIN_OUTPUT_DATA3_0_LSPI_OUTPUT_DATA_MASK_FIELD _MK_FIELD_CONST(0x1, DC_COM_PIN_OUTPUT_DATA3_0_LSPI_OUTPUT_DATA_MASK_SHIFT) +#define DC_COM_PIN_OUTPUT_DATA3_0_LSPI_OUTPUT_DATA_MASK_RANGE 9:9 +#define DC_COM_PIN_OUTPUT_DATA3_0_LSPI_OUTPUT_DATA_MASK_WOFFSET 0x0 +#define DC_COM_PIN_OUTPUT_DATA3_0_LSPI_OUTPUT_DATA_MASK_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA3_0_LSPI_OUTPUT_DATA_MASK_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_COM_PIN_OUTPUT_DATA3_0_LSPI_OUTPUT_DATA_MASK_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA3_0_LSPI_OUTPUT_DATA_MASK_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA3_0_LSPI_OUTPUT_DATA_MASK_MASKED _MK_ENUM_CONST(0) +#define DC_COM_PIN_OUTPUT_DATA3_0_LSPI_OUTPUT_DATA_MASK_NOTMASKED _MK_ENUM_CONST(1) + +#define DC_COM_PIN_OUTPUT_DATA3_0_LSDI_OUTPUT_DATA_SHIFT _MK_SHIFT_CONST(10) +#define DC_COM_PIN_OUTPUT_DATA3_0_LSDI_OUTPUT_DATA_FIELD _MK_FIELD_CONST(0x1, DC_COM_PIN_OUTPUT_DATA3_0_LSDI_OUTPUT_DATA_SHIFT) +#define DC_COM_PIN_OUTPUT_DATA3_0_LSDI_OUTPUT_DATA_RANGE 10:10 +#define DC_COM_PIN_OUTPUT_DATA3_0_LSDI_OUTPUT_DATA_WOFFSET 0x0 +#define DC_COM_PIN_OUTPUT_DATA3_0_LSDI_OUTPUT_DATA_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA3_0_LSDI_OUTPUT_DATA_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_COM_PIN_OUTPUT_DATA3_0_LSDI_OUTPUT_DATA_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA3_0_LSDI_OUTPUT_DATA_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA3_0_LSDI_OUTPUT_DATA_LOW _MK_ENUM_CONST(0) +#define DC_COM_PIN_OUTPUT_DATA3_0_LSDI_OUTPUT_DATA_HIGH _MK_ENUM_CONST(1) + +#define DC_COM_PIN_OUTPUT_DATA3_0_LSDI_OUTPUT_DATA_MASK_SHIFT _MK_SHIFT_CONST(11) +#define DC_COM_PIN_OUTPUT_DATA3_0_LSDI_OUTPUT_DATA_MASK_FIELD _MK_FIELD_CONST(0x1, DC_COM_PIN_OUTPUT_DATA3_0_LSDI_OUTPUT_DATA_MASK_SHIFT) +#define DC_COM_PIN_OUTPUT_DATA3_0_LSDI_OUTPUT_DATA_MASK_RANGE 11:11 +#define DC_COM_PIN_OUTPUT_DATA3_0_LSDI_OUTPUT_DATA_MASK_WOFFSET 0x0 +#define DC_COM_PIN_OUTPUT_DATA3_0_LSDI_OUTPUT_DATA_MASK_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA3_0_LSDI_OUTPUT_DATA_MASK_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_COM_PIN_OUTPUT_DATA3_0_LSDI_OUTPUT_DATA_MASK_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA3_0_LSDI_OUTPUT_DATA_MASK_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_DATA3_0_LSDI_OUTPUT_DATA_MASK_MASKED _MK_ENUM_CONST(0) +#define DC_COM_PIN_OUTPUT_DATA3_0_LSDI_OUTPUT_DATA_MASK_NOTMASKED _MK_ENUM_CONST(1) + + +// Reserved address 782 [0x30e] + +// Reserved address 783 [0x30f] + +// Reserved address 784 [0x310] + +// Reserved address 785 [0x311] + +// Register DC_COM_PIN_INPUT_DATA0_0 +#define DC_COM_PIN_INPUT_DATA0_0 _MK_ADDR_CONST(0x312) +#define DC_COM_PIN_INPUT_DATA0_0_SECURE 0x0 +#define DC_COM_PIN_INPUT_DATA0_0_WORD_COUNT 0x1 +#define DC_COM_PIN_INPUT_DATA0_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_COM_PIN_INPUT_DATA0_0_RESET_MASK _MK_MASK_CONST(0x3ffff) +#define DC_COM_PIN_INPUT_DATA0_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_COM_PIN_INPUT_DATA0_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_PIN_INPUT_DATA0_0_READ_MASK _MK_MASK_CONST(0x3ffff) +#define DC_COM_PIN_INPUT_DATA0_0_WRITE_MASK _MK_MASK_CONST(0x0) +#define DC_COM_PIN_INPUT_DATA0_0_LD0_INPUT_DATA_SHIFT _MK_SHIFT_CONST(0) +#define DC_COM_PIN_INPUT_DATA0_0_LD0_INPUT_DATA_FIELD _MK_FIELD_CONST(0x1, DC_COM_PIN_INPUT_DATA0_0_LD0_INPUT_DATA_SHIFT) +#define DC_COM_PIN_INPUT_DATA0_0_LD0_INPUT_DATA_RANGE 0:0 +#define DC_COM_PIN_INPUT_DATA0_0_LD0_INPUT_DATA_WOFFSET 0x0 +#define DC_COM_PIN_INPUT_DATA0_0_LD0_INPUT_DATA_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_INPUT_DATA0_0_LD0_INPUT_DATA_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_COM_PIN_INPUT_DATA0_0_LD0_INPUT_DATA_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_INPUT_DATA0_0_LD0_INPUT_DATA_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_COM_PIN_INPUT_DATA0_0_LD1_INPUT_DATA_SHIFT _MK_SHIFT_CONST(1) +#define DC_COM_PIN_INPUT_DATA0_0_LD1_INPUT_DATA_FIELD _MK_FIELD_CONST(0x1, DC_COM_PIN_INPUT_DATA0_0_LD1_INPUT_DATA_SHIFT) +#define DC_COM_PIN_INPUT_DATA0_0_LD1_INPUT_DATA_RANGE 1:1 +#define DC_COM_PIN_INPUT_DATA0_0_LD1_INPUT_DATA_WOFFSET 0x0 +#define DC_COM_PIN_INPUT_DATA0_0_LD1_INPUT_DATA_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_INPUT_DATA0_0_LD1_INPUT_DATA_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_COM_PIN_INPUT_DATA0_0_LD1_INPUT_DATA_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_INPUT_DATA0_0_LD1_INPUT_DATA_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_COM_PIN_INPUT_DATA0_0_LD2_INPUT_DATA_SHIFT _MK_SHIFT_CONST(2) +#define DC_COM_PIN_INPUT_DATA0_0_LD2_INPUT_DATA_FIELD _MK_FIELD_CONST(0x1, DC_COM_PIN_INPUT_DATA0_0_LD2_INPUT_DATA_SHIFT) +#define DC_COM_PIN_INPUT_DATA0_0_LD2_INPUT_DATA_RANGE 2:2 +#define DC_COM_PIN_INPUT_DATA0_0_LD2_INPUT_DATA_WOFFSET 0x0 +#define DC_COM_PIN_INPUT_DATA0_0_LD2_INPUT_DATA_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_INPUT_DATA0_0_LD2_INPUT_DATA_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_COM_PIN_INPUT_DATA0_0_LD2_INPUT_DATA_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_INPUT_DATA0_0_LD2_INPUT_DATA_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_COM_PIN_INPUT_DATA0_0_LD3_INPUT_DATA_SHIFT _MK_SHIFT_CONST(3) +#define DC_COM_PIN_INPUT_DATA0_0_LD3_INPUT_DATA_FIELD _MK_FIELD_CONST(0x1, DC_COM_PIN_INPUT_DATA0_0_LD3_INPUT_DATA_SHIFT) +#define DC_COM_PIN_INPUT_DATA0_0_LD3_INPUT_DATA_RANGE 3:3 +#define DC_COM_PIN_INPUT_DATA0_0_LD3_INPUT_DATA_WOFFSET 0x0 +#define DC_COM_PIN_INPUT_DATA0_0_LD3_INPUT_DATA_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_INPUT_DATA0_0_LD3_INPUT_DATA_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_COM_PIN_INPUT_DATA0_0_LD3_INPUT_DATA_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_INPUT_DATA0_0_LD3_INPUT_DATA_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_COM_PIN_INPUT_DATA0_0_LD4_INPUT_DATA_SHIFT _MK_SHIFT_CONST(4) +#define DC_COM_PIN_INPUT_DATA0_0_LD4_INPUT_DATA_FIELD _MK_FIELD_CONST(0x1, DC_COM_PIN_INPUT_DATA0_0_LD4_INPUT_DATA_SHIFT) +#define DC_COM_PIN_INPUT_DATA0_0_LD4_INPUT_DATA_RANGE 4:4 +#define DC_COM_PIN_INPUT_DATA0_0_LD4_INPUT_DATA_WOFFSET 0x0 +#define DC_COM_PIN_INPUT_DATA0_0_LD4_INPUT_DATA_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_INPUT_DATA0_0_LD4_INPUT_DATA_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_COM_PIN_INPUT_DATA0_0_LD4_INPUT_DATA_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_INPUT_DATA0_0_LD4_INPUT_DATA_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_COM_PIN_INPUT_DATA0_0_LD5_INPUT_DATA_SHIFT _MK_SHIFT_CONST(5) +#define DC_COM_PIN_INPUT_DATA0_0_LD5_INPUT_DATA_FIELD _MK_FIELD_CONST(0x1, DC_COM_PIN_INPUT_DATA0_0_LD5_INPUT_DATA_SHIFT) +#define DC_COM_PIN_INPUT_DATA0_0_LD5_INPUT_DATA_RANGE 5:5 +#define DC_COM_PIN_INPUT_DATA0_0_LD5_INPUT_DATA_WOFFSET 0x0 +#define DC_COM_PIN_INPUT_DATA0_0_LD5_INPUT_DATA_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_INPUT_DATA0_0_LD5_INPUT_DATA_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_COM_PIN_INPUT_DATA0_0_LD5_INPUT_DATA_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_INPUT_DATA0_0_LD5_INPUT_DATA_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_COM_PIN_INPUT_DATA0_0_LD6_INPUT_DATA_SHIFT _MK_SHIFT_CONST(6) +#define DC_COM_PIN_INPUT_DATA0_0_LD6_INPUT_DATA_FIELD _MK_FIELD_CONST(0x1, DC_COM_PIN_INPUT_DATA0_0_LD6_INPUT_DATA_SHIFT) +#define DC_COM_PIN_INPUT_DATA0_0_LD6_INPUT_DATA_RANGE 6:6 +#define DC_COM_PIN_INPUT_DATA0_0_LD6_INPUT_DATA_WOFFSET 0x0 +#define DC_COM_PIN_INPUT_DATA0_0_LD6_INPUT_DATA_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_INPUT_DATA0_0_LD6_INPUT_DATA_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_COM_PIN_INPUT_DATA0_0_LD6_INPUT_DATA_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_INPUT_DATA0_0_LD6_INPUT_DATA_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_COM_PIN_INPUT_DATA0_0_LD7_INPUT_DATA_SHIFT _MK_SHIFT_CONST(7) +#define DC_COM_PIN_INPUT_DATA0_0_LD7_INPUT_DATA_FIELD _MK_FIELD_CONST(0x1, DC_COM_PIN_INPUT_DATA0_0_LD7_INPUT_DATA_SHIFT) +#define DC_COM_PIN_INPUT_DATA0_0_LD7_INPUT_DATA_RANGE 7:7 +#define DC_COM_PIN_INPUT_DATA0_0_LD7_INPUT_DATA_WOFFSET 0x0 +#define DC_COM_PIN_INPUT_DATA0_0_LD7_INPUT_DATA_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_INPUT_DATA0_0_LD7_INPUT_DATA_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_COM_PIN_INPUT_DATA0_0_LD7_INPUT_DATA_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_INPUT_DATA0_0_LD7_INPUT_DATA_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_COM_PIN_INPUT_DATA0_0_LD8_INPUT_DATA_SHIFT _MK_SHIFT_CONST(8) +#define DC_COM_PIN_INPUT_DATA0_0_LD8_INPUT_DATA_FIELD _MK_FIELD_CONST(0x1, DC_COM_PIN_INPUT_DATA0_0_LD8_INPUT_DATA_SHIFT) +#define DC_COM_PIN_INPUT_DATA0_0_LD8_INPUT_DATA_RANGE 8:8 +#define DC_COM_PIN_INPUT_DATA0_0_LD8_INPUT_DATA_WOFFSET 0x0 +#define DC_COM_PIN_INPUT_DATA0_0_LD8_INPUT_DATA_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_INPUT_DATA0_0_LD8_INPUT_DATA_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_COM_PIN_INPUT_DATA0_0_LD8_INPUT_DATA_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_INPUT_DATA0_0_LD8_INPUT_DATA_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_COM_PIN_INPUT_DATA0_0_LD9_INPUT_DATA_SHIFT _MK_SHIFT_CONST(9) +#define DC_COM_PIN_INPUT_DATA0_0_LD9_INPUT_DATA_FIELD _MK_FIELD_CONST(0x1, DC_COM_PIN_INPUT_DATA0_0_LD9_INPUT_DATA_SHIFT) +#define DC_COM_PIN_INPUT_DATA0_0_LD9_INPUT_DATA_RANGE 9:9 +#define DC_COM_PIN_INPUT_DATA0_0_LD9_INPUT_DATA_WOFFSET 0x0 +#define DC_COM_PIN_INPUT_DATA0_0_LD9_INPUT_DATA_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_INPUT_DATA0_0_LD9_INPUT_DATA_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_COM_PIN_INPUT_DATA0_0_LD9_INPUT_DATA_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_INPUT_DATA0_0_LD9_INPUT_DATA_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_COM_PIN_INPUT_DATA0_0_LD10_INPUT_DATA_SHIFT _MK_SHIFT_CONST(10) +#define DC_COM_PIN_INPUT_DATA0_0_LD10_INPUT_DATA_FIELD _MK_FIELD_CONST(0x1, DC_COM_PIN_INPUT_DATA0_0_LD10_INPUT_DATA_SHIFT) +#define DC_COM_PIN_INPUT_DATA0_0_LD10_INPUT_DATA_RANGE 10:10 +#define DC_COM_PIN_INPUT_DATA0_0_LD10_INPUT_DATA_WOFFSET 0x0 +#define DC_COM_PIN_INPUT_DATA0_0_LD10_INPUT_DATA_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_INPUT_DATA0_0_LD10_INPUT_DATA_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_COM_PIN_INPUT_DATA0_0_LD10_INPUT_DATA_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_INPUT_DATA0_0_LD10_INPUT_DATA_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_COM_PIN_INPUT_DATA0_0_LD11_INPUT_DATA_SHIFT _MK_SHIFT_CONST(11) +#define DC_COM_PIN_INPUT_DATA0_0_LD11_INPUT_DATA_FIELD _MK_FIELD_CONST(0x1, DC_COM_PIN_INPUT_DATA0_0_LD11_INPUT_DATA_SHIFT) +#define DC_COM_PIN_INPUT_DATA0_0_LD11_INPUT_DATA_RANGE 11:11 +#define DC_COM_PIN_INPUT_DATA0_0_LD11_INPUT_DATA_WOFFSET 0x0 +#define DC_COM_PIN_INPUT_DATA0_0_LD11_INPUT_DATA_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_INPUT_DATA0_0_LD11_INPUT_DATA_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_COM_PIN_INPUT_DATA0_0_LD11_INPUT_DATA_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_INPUT_DATA0_0_LD11_INPUT_DATA_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_COM_PIN_INPUT_DATA0_0_LD12_INPUT_DATA_SHIFT _MK_SHIFT_CONST(12) +#define DC_COM_PIN_INPUT_DATA0_0_LD12_INPUT_DATA_FIELD _MK_FIELD_CONST(0x1, DC_COM_PIN_INPUT_DATA0_0_LD12_INPUT_DATA_SHIFT) +#define DC_COM_PIN_INPUT_DATA0_0_LD12_INPUT_DATA_RANGE 12:12 +#define DC_COM_PIN_INPUT_DATA0_0_LD12_INPUT_DATA_WOFFSET 0x0 +#define DC_COM_PIN_INPUT_DATA0_0_LD12_INPUT_DATA_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_INPUT_DATA0_0_LD12_INPUT_DATA_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_COM_PIN_INPUT_DATA0_0_LD12_INPUT_DATA_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_INPUT_DATA0_0_LD12_INPUT_DATA_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_COM_PIN_INPUT_DATA0_0_LD13_INPUT_DATA_SHIFT _MK_SHIFT_CONST(13) +#define DC_COM_PIN_INPUT_DATA0_0_LD13_INPUT_DATA_FIELD _MK_FIELD_CONST(0x1, DC_COM_PIN_INPUT_DATA0_0_LD13_INPUT_DATA_SHIFT) +#define DC_COM_PIN_INPUT_DATA0_0_LD13_INPUT_DATA_RANGE 13:13 +#define DC_COM_PIN_INPUT_DATA0_0_LD13_INPUT_DATA_WOFFSET 0x0 +#define DC_COM_PIN_INPUT_DATA0_0_LD13_INPUT_DATA_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_INPUT_DATA0_0_LD13_INPUT_DATA_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_COM_PIN_INPUT_DATA0_0_LD13_INPUT_DATA_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_INPUT_DATA0_0_LD13_INPUT_DATA_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_COM_PIN_INPUT_DATA0_0_LD14_INPUT_DATA_SHIFT _MK_SHIFT_CONST(14) +#define DC_COM_PIN_INPUT_DATA0_0_LD14_INPUT_DATA_FIELD _MK_FIELD_CONST(0x1, DC_COM_PIN_INPUT_DATA0_0_LD14_INPUT_DATA_SHIFT) +#define DC_COM_PIN_INPUT_DATA0_0_LD14_INPUT_DATA_RANGE 14:14 +#define DC_COM_PIN_INPUT_DATA0_0_LD14_INPUT_DATA_WOFFSET 0x0 +#define DC_COM_PIN_INPUT_DATA0_0_LD14_INPUT_DATA_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_INPUT_DATA0_0_LD14_INPUT_DATA_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_COM_PIN_INPUT_DATA0_0_LD14_INPUT_DATA_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_INPUT_DATA0_0_LD14_INPUT_DATA_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_COM_PIN_INPUT_DATA0_0_LD15_INPUT_DATA_SHIFT _MK_SHIFT_CONST(15) +#define DC_COM_PIN_INPUT_DATA0_0_LD15_INPUT_DATA_FIELD _MK_FIELD_CONST(0x1, DC_COM_PIN_INPUT_DATA0_0_LD15_INPUT_DATA_SHIFT) +#define DC_COM_PIN_INPUT_DATA0_0_LD15_INPUT_DATA_RANGE 15:15 +#define DC_COM_PIN_INPUT_DATA0_0_LD15_INPUT_DATA_WOFFSET 0x0 +#define DC_COM_PIN_INPUT_DATA0_0_LD15_INPUT_DATA_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_INPUT_DATA0_0_LD15_INPUT_DATA_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_COM_PIN_INPUT_DATA0_0_LD15_INPUT_DATA_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_INPUT_DATA0_0_LD15_INPUT_DATA_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_COM_PIN_INPUT_DATA0_0_LD16_INPUT_DATA_SHIFT _MK_SHIFT_CONST(16) +#define DC_COM_PIN_INPUT_DATA0_0_LD16_INPUT_DATA_FIELD _MK_FIELD_CONST(0x1, DC_COM_PIN_INPUT_DATA0_0_LD16_INPUT_DATA_SHIFT) +#define DC_COM_PIN_INPUT_DATA0_0_LD16_INPUT_DATA_RANGE 16:16 +#define DC_COM_PIN_INPUT_DATA0_0_LD16_INPUT_DATA_WOFFSET 0x0 +#define DC_COM_PIN_INPUT_DATA0_0_LD16_INPUT_DATA_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_INPUT_DATA0_0_LD16_INPUT_DATA_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_COM_PIN_INPUT_DATA0_0_LD16_INPUT_DATA_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_INPUT_DATA0_0_LD16_INPUT_DATA_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_COM_PIN_INPUT_DATA0_0_LD17_INPUT_DATA_SHIFT _MK_SHIFT_CONST(17) +#define DC_COM_PIN_INPUT_DATA0_0_LD17_INPUT_DATA_FIELD _MK_FIELD_CONST(0x1, DC_COM_PIN_INPUT_DATA0_0_LD17_INPUT_DATA_SHIFT) +#define DC_COM_PIN_INPUT_DATA0_0_LD17_INPUT_DATA_RANGE 17:17 +#define DC_COM_PIN_INPUT_DATA0_0_LD17_INPUT_DATA_WOFFSET 0x0 +#define DC_COM_PIN_INPUT_DATA0_0_LD17_INPUT_DATA_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_INPUT_DATA0_0_LD17_INPUT_DATA_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_COM_PIN_INPUT_DATA0_0_LD17_INPUT_DATA_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_INPUT_DATA0_0_LD17_INPUT_DATA_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_COM_PIN_INPUT_DATA1_0 +#define DC_COM_PIN_INPUT_DATA1_0 _MK_ADDR_CONST(0x313) +#define DC_COM_PIN_INPUT_DATA1_0_SECURE 0x0 +#define DC_COM_PIN_INPUT_DATA1_0_WORD_COUNT 0x1 +#define DC_COM_PIN_INPUT_DATA1_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_COM_PIN_INPUT_DATA1_0_RESET_MASK _MK_MASK_CONST(0x3ff37f7) +#define DC_COM_PIN_INPUT_DATA1_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_COM_PIN_INPUT_DATA1_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_PIN_INPUT_DATA1_0_READ_MASK _MK_MASK_CONST(0x3ff37f7) +#define DC_COM_PIN_INPUT_DATA1_0_WRITE_MASK _MK_MASK_CONST(0x0) +#define DC_COM_PIN_INPUT_DATA1_0_LPW0_INPUT_DATA_SHIFT _MK_SHIFT_CONST(0) +#define DC_COM_PIN_INPUT_DATA1_0_LPW0_INPUT_DATA_FIELD _MK_FIELD_CONST(0x1, DC_COM_PIN_INPUT_DATA1_0_LPW0_INPUT_DATA_SHIFT) +#define DC_COM_PIN_INPUT_DATA1_0_LPW0_INPUT_DATA_RANGE 0:0 +#define DC_COM_PIN_INPUT_DATA1_0_LPW0_INPUT_DATA_WOFFSET 0x0 +#define DC_COM_PIN_INPUT_DATA1_0_LPW0_INPUT_DATA_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_INPUT_DATA1_0_LPW0_INPUT_DATA_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_COM_PIN_INPUT_DATA1_0_LPW0_INPUT_DATA_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_INPUT_DATA1_0_LPW0_INPUT_DATA_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_COM_PIN_INPUT_DATA1_0_LPW1_INPUT_DATA_SHIFT _MK_SHIFT_CONST(1) +#define DC_COM_PIN_INPUT_DATA1_0_LPW1_INPUT_DATA_FIELD _MK_FIELD_CONST(0x1, DC_COM_PIN_INPUT_DATA1_0_LPW1_INPUT_DATA_SHIFT) +#define DC_COM_PIN_INPUT_DATA1_0_LPW1_INPUT_DATA_RANGE 1:1 +#define DC_COM_PIN_INPUT_DATA1_0_LPW1_INPUT_DATA_WOFFSET 0x0 +#define DC_COM_PIN_INPUT_DATA1_0_LPW1_INPUT_DATA_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_INPUT_DATA1_0_LPW1_INPUT_DATA_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_COM_PIN_INPUT_DATA1_0_LPW1_INPUT_DATA_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_INPUT_DATA1_0_LPW1_INPUT_DATA_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_COM_PIN_INPUT_DATA1_0_LPW2_INPUT_DATA_SHIFT _MK_SHIFT_CONST(2) +#define DC_COM_PIN_INPUT_DATA1_0_LPW2_INPUT_DATA_FIELD _MK_FIELD_CONST(0x1, DC_COM_PIN_INPUT_DATA1_0_LPW2_INPUT_DATA_SHIFT) +#define DC_COM_PIN_INPUT_DATA1_0_LPW2_INPUT_DATA_RANGE 2:2 +#define DC_COM_PIN_INPUT_DATA1_0_LPW2_INPUT_DATA_WOFFSET 0x0 +#define DC_COM_PIN_INPUT_DATA1_0_LPW2_INPUT_DATA_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_INPUT_DATA1_0_LPW2_INPUT_DATA_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_COM_PIN_INPUT_DATA1_0_LPW2_INPUT_DATA_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_INPUT_DATA1_0_LPW2_INPUT_DATA_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_COM_PIN_INPUT_DATA1_0_LSC0_INPUT_DATA_SHIFT _MK_SHIFT_CONST(4) +#define DC_COM_PIN_INPUT_DATA1_0_LSC0_INPUT_DATA_FIELD _MK_FIELD_CONST(0x1, DC_COM_PIN_INPUT_DATA1_0_LSC0_INPUT_DATA_SHIFT) +#define DC_COM_PIN_INPUT_DATA1_0_LSC0_INPUT_DATA_RANGE 4:4 +#define DC_COM_PIN_INPUT_DATA1_0_LSC0_INPUT_DATA_WOFFSET 0x0 +#define DC_COM_PIN_INPUT_DATA1_0_LSC0_INPUT_DATA_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_INPUT_DATA1_0_LSC0_INPUT_DATA_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_COM_PIN_INPUT_DATA1_0_LSC0_INPUT_DATA_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_INPUT_DATA1_0_LSC0_INPUT_DATA_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_COM_PIN_INPUT_DATA1_0_LSC1_INPUT_DATA_SHIFT _MK_SHIFT_CONST(5) +#define DC_COM_PIN_INPUT_DATA1_0_LSC1_INPUT_DATA_FIELD _MK_FIELD_CONST(0x1, DC_COM_PIN_INPUT_DATA1_0_LSC1_INPUT_DATA_SHIFT) +#define DC_COM_PIN_INPUT_DATA1_0_LSC1_INPUT_DATA_RANGE 5:5 +#define DC_COM_PIN_INPUT_DATA1_0_LSC1_INPUT_DATA_WOFFSET 0x0 +#define DC_COM_PIN_INPUT_DATA1_0_LSC1_INPUT_DATA_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_INPUT_DATA1_0_LSC1_INPUT_DATA_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_COM_PIN_INPUT_DATA1_0_LSC1_INPUT_DATA_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_INPUT_DATA1_0_LSC1_INPUT_DATA_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_COM_PIN_INPUT_DATA1_0_LVS_INPUT_DATA_SHIFT _MK_SHIFT_CONST(6) +#define DC_COM_PIN_INPUT_DATA1_0_LVS_INPUT_DATA_FIELD _MK_FIELD_CONST(0x1, DC_COM_PIN_INPUT_DATA1_0_LVS_INPUT_DATA_SHIFT) +#define DC_COM_PIN_INPUT_DATA1_0_LVS_INPUT_DATA_RANGE 6:6 +#define DC_COM_PIN_INPUT_DATA1_0_LVS_INPUT_DATA_WOFFSET 0x0 +#define DC_COM_PIN_INPUT_DATA1_0_LVS_INPUT_DATA_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_INPUT_DATA1_0_LVS_INPUT_DATA_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_COM_PIN_INPUT_DATA1_0_LVS_INPUT_DATA_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_INPUT_DATA1_0_LVS_INPUT_DATA_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_COM_PIN_INPUT_DATA1_0_LHS_INPUT_DATA_SHIFT _MK_SHIFT_CONST(7) +#define DC_COM_PIN_INPUT_DATA1_0_LHS_INPUT_DATA_FIELD _MK_FIELD_CONST(0x1, DC_COM_PIN_INPUT_DATA1_0_LHS_INPUT_DATA_SHIFT) +#define DC_COM_PIN_INPUT_DATA1_0_LHS_INPUT_DATA_RANGE 7:7 +#define DC_COM_PIN_INPUT_DATA1_0_LHS_INPUT_DATA_WOFFSET 0x0 +#define DC_COM_PIN_INPUT_DATA1_0_LHS_INPUT_DATA_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_INPUT_DATA1_0_LHS_INPUT_DATA_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_COM_PIN_INPUT_DATA1_0_LHS_INPUT_DATA_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_INPUT_DATA1_0_LHS_INPUT_DATA_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_COM_PIN_INPUT_DATA1_0_LHP0_INPUT_DATA_SHIFT _MK_SHIFT_CONST(8) +#define DC_COM_PIN_INPUT_DATA1_0_LHP0_INPUT_DATA_FIELD _MK_FIELD_CONST(0x1, DC_COM_PIN_INPUT_DATA1_0_LHP0_INPUT_DATA_SHIFT) +#define DC_COM_PIN_INPUT_DATA1_0_LHP0_INPUT_DATA_RANGE 8:8 +#define DC_COM_PIN_INPUT_DATA1_0_LHP0_INPUT_DATA_WOFFSET 0x0 +#define DC_COM_PIN_INPUT_DATA1_0_LHP0_INPUT_DATA_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_INPUT_DATA1_0_LHP0_INPUT_DATA_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_COM_PIN_INPUT_DATA1_0_LHP0_INPUT_DATA_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_INPUT_DATA1_0_LHP0_INPUT_DATA_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_COM_PIN_INPUT_DATA1_0_LHP1_INPUT_DATA_SHIFT _MK_SHIFT_CONST(9) +#define DC_COM_PIN_INPUT_DATA1_0_LHP1_INPUT_DATA_FIELD _MK_FIELD_CONST(0x1, DC_COM_PIN_INPUT_DATA1_0_LHP1_INPUT_DATA_SHIFT) +#define DC_COM_PIN_INPUT_DATA1_0_LHP1_INPUT_DATA_RANGE 9:9 +#define DC_COM_PIN_INPUT_DATA1_0_LHP1_INPUT_DATA_WOFFSET 0x0 +#define DC_COM_PIN_INPUT_DATA1_0_LHP1_INPUT_DATA_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_INPUT_DATA1_0_LHP1_INPUT_DATA_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_COM_PIN_INPUT_DATA1_0_LHP1_INPUT_DATA_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_INPUT_DATA1_0_LHP1_INPUT_DATA_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_COM_PIN_INPUT_DATA1_0_LHP2_INPUT_DATA_SHIFT _MK_SHIFT_CONST(10) +#define DC_COM_PIN_INPUT_DATA1_0_LHP2_INPUT_DATA_FIELD _MK_FIELD_CONST(0x1, DC_COM_PIN_INPUT_DATA1_0_LHP2_INPUT_DATA_SHIFT) +#define DC_COM_PIN_INPUT_DATA1_0_LHP2_INPUT_DATA_RANGE 10:10 +#define DC_COM_PIN_INPUT_DATA1_0_LHP2_INPUT_DATA_WOFFSET 0x0 +#define DC_COM_PIN_INPUT_DATA1_0_LHP2_INPUT_DATA_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_INPUT_DATA1_0_LHP2_INPUT_DATA_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_COM_PIN_INPUT_DATA1_0_LHP2_INPUT_DATA_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_INPUT_DATA1_0_LHP2_INPUT_DATA_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_COM_PIN_INPUT_DATA1_0_LVP0_INPUT_DATA_SHIFT _MK_SHIFT_CONST(12) +#define DC_COM_PIN_INPUT_DATA1_0_LVP0_INPUT_DATA_FIELD _MK_FIELD_CONST(0x1, DC_COM_PIN_INPUT_DATA1_0_LVP0_INPUT_DATA_SHIFT) +#define DC_COM_PIN_INPUT_DATA1_0_LVP0_INPUT_DATA_RANGE 12:12 +#define DC_COM_PIN_INPUT_DATA1_0_LVP0_INPUT_DATA_WOFFSET 0x0 +#define DC_COM_PIN_INPUT_DATA1_0_LVP0_INPUT_DATA_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_INPUT_DATA1_0_LVP0_INPUT_DATA_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_COM_PIN_INPUT_DATA1_0_LVP0_INPUT_DATA_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_INPUT_DATA1_0_LVP0_INPUT_DATA_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_COM_PIN_INPUT_DATA1_0_LVP1_INPUT_DATA_SHIFT _MK_SHIFT_CONST(13) +#define DC_COM_PIN_INPUT_DATA1_0_LVP1_INPUT_DATA_FIELD _MK_FIELD_CONST(0x1, DC_COM_PIN_INPUT_DATA1_0_LVP1_INPUT_DATA_SHIFT) +#define DC_COM_PIN_INPUT_DATA1_0_LVP1_INPUT_DATA_RANGE 13:13 +#define DC_COM_PIN_INPUT_DATA1_0_LVP1_INPUT_DATA_WOFFSET 0x0 +#define DC_COM_PIN_INPUT_DATA1_0_LVP1_INPUT_DATA_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_INPUT_DATA1_0_LVP1_INPUT_DATA_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_COM_PIN_INPUT_DATA1_0_LVP1_INPUT_DATA_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_INPUT_DATA1_0_LVP1_INPUT_DATA_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_COM_PIN_INPUT_DATA1_0_LM0_INPUT_DATA_SHIFT _MK_SHIFT_CONST(16) +#define DC_COM_PIN_INPUT_DATA1_0_LM0_INPUT_DATA_FIELD _MK_FIELD_CONST(0x1, DC_COM_PIN_INPUT_DATA1_0_LM0_INPUT_DATA_SHIFT) +#define DC_COM_PIN_INPUT_DATA1_0_LM0_INPUT_DATA_RANGE 16:16 +#define DC_COM_PIN_INPUT_DATA1_0_LM0_INPUT_DATA_WOFFSET 0x0 +#define DC_COM_PIN_INPUT_DATA1_0_LM0_INPUT_DATA_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_INPUT_DATA1_0_LM0_INPUT_DATA_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_COM_PIN_INPUT_DATA1_0_LM0_INPUT_DATA_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_INPUT_DATA1_0_LM0_INPUT_DATA_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_COM_PIN_INPUT_DATA1_0_LM1_INPUT_DATA_SHIFT _MK_SHIFT_CONST(17) +#define DC_COM_PIN_INPUT_DATA1_0_LM1_INPUT_DATA_FIELD _MK_FIELD_CONST(0x1, DC_COM_PIN_INPUT_DATA1_0_LM1_INPUT_DATA_SHIFT) +#define DC_COM_PIN_INPUT_DATA1_0_LM1_INPUT_DATA_RANGE 17:17 +#define DC_COM_PIN_INPUT_DATA1_0_LM1_INPUT_DATA_WOFFSET 0x0 +#define DC_COM_PIN_INPUT_DATA1_0_LM1_INPUT_DATA_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_INPUT_DATA1_0_LM1_INPUT_DATA_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_COM_PIN_INPUT_DATA1_0_LM1_INPUT_DATA_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_INPUT_DATA1_0_LM1_INPUT_DATA_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_COM_PIN_INPUT_DATA1_0_LDI_INPUT_DATA_SHIFT _MK_SHIFT_CONST(18) +#define DC_COM_PIN_INPUT_DATA1_0_LDI_INPUT_DATA_FIELD _MK_FIELD_CONST(0x1, DC_COM_PIN_INPUT_DATA1_0_LDI_INPUT_DATA_SHIFT) +#define DC_COM_PIN_INPUT_DATA1_0_LDI_INPUT_DATA_RANGE 18:18 +#define DC_COM_PIN_INPUT_DATA1_0_LDI_INPUT_DATA_WOFFSET 0x0 +#define DC_COM_PIN_INPUT_DATA1_0_LDI_INPUT_DATA_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_INPUT_DATA1_0_LDI_INPUT_DATA_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_COM_PIN_INPUT_DATA1_0_LDI_INPUT_DATA_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_INPUT_DATA1_0_LDI_INPUT_DATA_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_COM_PIN_INPUT_DATA1_0_LPP_INPUT_DATA_SHIFT _MK_SHIFT_CONST(19) +#define DC_COM_PIN_INPUT_DATA1_0_LPP_INPUT_DATA_FIELD _MK_FIELD_CONST(0x1, DC_COM_PIN_INPUT_DATA1_0_LPP_INPUT_DATA_SHIFT) +#define DC_COM_PIN_INPUT_DATA1_0_LPP_INPUT_DATA_RANGE 19:19 +#define DC_COM_PIN_INPUT_DATA1_0_LPP_INPUT_DATA_WOFFSET 0x0 +#define DC_COM_PIN_INPUT_DATA1_0_LPP_INPUT_DATA_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_INPUT_DATA1_0_LPP_INPUT_DATA_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_COM_PIN_INPUT_DATA1_0_LPP_INPUT_DATA_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_INPUT_DATA1_0_LPP_INPUT_DATA_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_COM_PIN_INPUT_DATA1_0_LSCK_INPUT_DATA_SHIFT _MK_SHIFT_CONST(20) +#define DC_COM_PIN_INPUT_DATA1_0_LSCK_INPUT_DATA_FIELD _MK_FIELD_CONST(0x1, DC_COM_PIN_INPUT_DATA1_0_LSCK_INPUT_DATA_SHIFT) +#define DC_COM_PIN_INPUT_DATA1_0_LSCK_INPUT_DATA_RANGE 20:20 +#define DC_COM_PIN_INPUT_DATA1_0_LSCK_INPUT_DATA_WOFFSET 0x0 +#define DC_COM_PIN_INPUT_DATA1_0_LSCK_INPUT_DATA_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_INPUT_DATA1_0_LSCK_INPUT_DATA_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_COM_PIN_INPUT_DATA1_0_LSCK_INPUT_DATA_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_INPUT_DATA1_0_LSCK_INPUT_DATA_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_COM_PIN_INPUT_DATA1_0_LSDA_INPUT_DATA_SHIFT _MK_SHIFT_CONST(21) +#define DC_COM_PIN_INPUT_DATA1_0_LSDA_INPUT_DATA_FIELD _MK_FIELD_CONST(0x1, DC_COM_PIN_INPUT_DATA1_0_LSDA_INPUT_DATA_SHIFT) +#define DC_COM_PIN_INPUT_DATA1_0_LSDA_INPUT_DATA_RANGE 21:21 +#define DC_COM_PIN_INPUT_DATA1_0_LSDA_INPUT_DATA_WOFFSET 0x0 +#define DC_COM_PIN_INPUT_DATA1_0_LSDA_INPUT_DATA_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_INPUT_DATA1_0_LSDA_INPUT_DATA_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_COM_PIN_INPUT_DATA1_0_LSDA_INPUT_DATA_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_INPUT_DATA1_0_LSDA_INPUT_DATA_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_COM_PIN_INPUT_DATA1_0_LCSN_INPUT_DATA_SHIFT _MK_SHIFT_CONST(22) +#define DC_COM_PIN_INPUT_DATA1_0_LCSN_INPUT_DATA_FIELD _MK_FIELD_CONST(0x1, DC_COM_PIN_INPUT_DATA1_0_LCSN_INPUT_DATA_SHIFT) +#define DC_COM_PIN_INPUT_DATA1_0_LCSN_INPUT_DATA_RANGE 22:22 +#define DC_COM_PIN_INPUT_DATA1_0_LCSN_INPUT_DATA_WOFFSET 0x0 +#define DC_COM_PIN_INPUT_DATA1_0_LCSN_INPUT_DATA_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_INPUT_DATA1_0_LCSN_INPUT_DATA_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_COM_PIN_INPUT_DATA1_0_LCSN_INPUT_DATA_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_INPUT_DATA1_0_LCSN_INPUT_DATA_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_COM_PIN_INPUT_DATA1_0_LDC_INPUT_DATA_SHIFT _MK_SHIFT_CONST(23) +#define DC_COM_PIN_INPUT_DATA1_0_LDC_INPUT_DATA_FIELD _MK_FIELD_CONST(0x1, DC_COM_PIN_INPUT_DATA1_0_LDC_INPUT_DATA_SHIFT) +#define DC_COM_PIN_INPUT_DATA1_0_LDC_INPUT_DATA_RANGE 23:23 +#define DC_COM_PIN_INPUT_DATA1_0_LDC_INPUT_DATA_WOFFSET 0x0 +#define DC_COM_PIN_INPUT_DATA1_0_LDC_INPUT_DATA_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_INPUT_DATA1_0_LDC_INPUT_DATA_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_COM_PIN_INPUT_DATA1_0_LDC_INPUT_DATA_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_INPUT_DATA1_0_LDC_INPUT_DATA_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_COM_PIN_INPUT_DATA1_0_LSPI_INPUT_DATA_SHIFT _MK_SHIFT_CONST(24) +#define DC_COM_PIN_INPUT_DATA1_0_LSPI_INPUT_DATA_FIELD _MK_FIELD_CONST(0x1, DC_COM_PIN_INPUT_DATA1_0_LSPI_INPUT_DATA_SHIFT) +#define DC_COM_PIN_INPUT_DATA1_0_LSPI_INPUT_DATA_RANGE 24:24 +#define DC_COM_PIN_INPUT_DATA1_0_LSPI_INPUT_DATA_WOFFSET 0x0 +#define DC_COM_PIN_INPUT_DATA1_0_LSPI_INPUT_DATA_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_INPUT_DATA1_0_LSPI_INPUT_DATA_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_COM_PIN_INPUT_DATA1_0_LSPI_INPUT_DATA_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_INPUT_DATA1_0_LSPI_INPUT_DATA_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_COM_PIN_INPUT_DATA1_0_LSDI_INPUT_DATA_SHIFT _MK_SHIFT_CONST(25) +#define DC_COM_PIN_INPUT_DATA1_0_LSDI_INPUT_DATA_FIELD _MK_FIELD_CONST(0x1, DC_COM_PIN_INPUT_DATA1_0_LSDI_INPUT_DATA_SHIFT) +#define DC_COM_PIN_INPUT_DATA1_0_LSDI_INPUT_DATA_RANGE 25:25 +#define DC_COM_PIN_INPUT_DATA1_0_LSDI_INPUT_DATA_WOFFSET 0x0 +#define DC_COM_PIN_INPUT_DATA1_0_LSDI_INPUT_DATA_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_INPUT_DATA1_0_LSDI_INPUT_DATA_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_COM_PIN_INPUT_DATA1_0_LSDI_INPUT_DATA_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_INPUT_DATA1_0_LSDI_INPUT_DATA_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_COM_PIN_OUTPUT_SELECT0_0 +#define DC_COM_PIN_OUTPUT_SELECT0_0 _MK_ADDR_CONST(0x314) +#define DC_COM_PIN_OUTPUT_SELECT0_0_SECURE 0x0 +#define DC_COM_PIN_OUTPUT_SELECT0_0_WORD_COUNT 0x1 +#define DC_COM_PIN_OUTPUT_SELECT0_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_SELECT0_0_RESET_MASK _MK_MASK_CONST(0x77777777) +#define DC_COM_PIN_OUTPUT_SELECT0_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_SELECT0_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_SELECT0_0_READ_MASK _MK_MASK_CONST(0x77777777) +#define DC_COM_PIN_OUTPUT_SELECT0_0_WRITE_MASK _MK_MASK_CONST(0x77777777) +#define DC_COM_PIN_OUTPUT_SELECT0_0_LD0_OUTPUT_SELECT_SHIFT _MK_SHIFT_CONST(0) +#define DC_COM_PIN_OUTPUT_SELECT0_0_LD0_OUTPUT_SELECT_FIELD _MK_FIELD_CONST(0x7, DC_COM_PIN_OUTPUT_SELECT0_0_LD0_OUTPUT_SELECT_SHIFT) +#define DC_COM_PIN_OUTPUT_SELECT0_0_LD0_OUTPUT_SELECT_RANGE 2:0 +#define DC_COM_PIN_OUTPUT_SELECT0_0_LD0_OUTPUT_SELECT_WOFFSET 0x0 +#define DC_COM_PIN_OUTPUT_SELECT0_0_LD0_OUTPUT_SELECT_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_SELECT0_0_LD0_OUTPUT_SELECT_DEFAULT_MASK _MK_MASK_CONST(0x7) +#define DC_COM_PIN_OUTPUT_SELECT0_0_LD0_OUTPUT_SELECT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_SELECT0_0_LD0_OUTPUT_SELECT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_COM_PIN_OUTPUT_SELECT0_0_LD1_OUTPUT_SELECT_SHIFT _MK_SHIFT_CONST(4) +#define DC_COM_PIN_OUTPUT_SELECT0_0_LD1_OUTPUT_SELECT_FIELD _MK_FIELD_CONST(0x7, DC_COM_PIN_OUTPUT_SELECT0_0_LD1_OUTPUT_SELECT_SHIFT) +#define DC_COM_PIN_OUTPUT_SELECT0_0_LD1_OUTPUT_SELECT_RANGE 6:4 +#define DC_COM_PIN_OUTPUT_SELECT0_0_LD1_OUTPUT_SELECT_WOFFSET 0x0 +#define DC_COM_PIN_OUTPUT_SELECT0_0_LD1_OUTPUT_SELECT_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_SELECT0_0_LD1_OUTPUT_SELECT_DEFAULT_MASK _MK_MASK_CONST(0x7) +#define DC_COM_PIN_OUTPUT_SELECT0_0_LD1_OUTPUT_SELECT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_SELECT0_0_LD1_OUTPUT_SELECT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_COM_PIN_OUTPUT_SELECT0_0_LD2_OUTPUT_SELECT_SHIFT _MK_SHIFT_CONST(8) +#define DC_COM_PIN_OUTPUT_SELECT0_0_LD2_OUTPUT_SELECT_FIELD _MK_FIELD_CONST(0x7, DC_COM_PIN_OUTPUT_SELECT0_0_LD2_OUTPUT_SELECT_SHIFT) +#define DC_COM_PIN_OUTPUT_SELECT0_0_LD2_OUTPUT_SELECT_RANGE 10:8 +#define DC_COM_PIN_OUTPUT_SELECT0_0_LD2_OUTPUT_SELECT_WOFFSET 0x0 +#define DC_COM_PIN_OUTPUT_SELECT0_0_LD2_OUTPUT_SELECT_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_SELECT0_0_LD2_OUTPUT_SELECT_DEFAULT_MASK _MK_MASK_CONST(0x7) +#define DC_COM_PIN_OUTPUT_SELECT0_0_LD2_OUTPUT_SELECT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_SELECT0_0_LD2_OUTPUT_SELECT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_COM_PIN_OUTPUT_SELECT0_0_LD3_OUTPUT_SELECT_SHIFT _MK_SHIFT_CONST(12) +#define DC_COM_PIN_OUTPUT_SELECT0_0_LD3_OUTPUT_SELECT_FIELD _MK_FIELD_CONST(0x7, DC_COM_PIN_OUTPUT_SELECT0_0_LD3_OUTPUT_SELECT_SHIFT) +#define DC_COM_PIN_OUTPUT_SELECT0_0_LD3_OUTPUT_SELECT_RANGE 14:12 +#define DC_COM_PIN_OUTPUT_SELECT0_0_LD3_OUTPUT_SELECT_WOFFSET 0x0 +#define DC_COM_PIN_OUTPUT_SELECT0_0_LD3_OUTPUT_SELECT_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_SELECT0_0_LD3_OUTPUT_SELECT_DEFAULT_MASK _MK_MASK_CONST(0x7) +#define DC_COM_PIN_OUTPUT_SELECT0_0_LD3_OUTPUT_SELECT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_SELECT0_0_LD3_OUTPUT_SELECT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_COM_PIN_OUTPUT_SELECT0_0_LD4_OUTPUT_SELECT_SHIFT _MK_SHIFT_CONST(16) +#define DC_COM_PIN_OUTPUT_SELECT0_0_LD4_OUTPUT_SELECT_FIELD _MK_FIELD_CONST(0x7, DC_COM_PIN_OUTPUT_SELECT0_0_LD4_OUTPUT_SELECT_SHIFT) +#define DC_COM_PIN_OUTPUT_SELECT0_0_LD4_OUTPUT_SELECT_RANGE 18:16 +#define DC_COM_PIN_OUTPUT_SELECT0_0_LD4_OUTPUT_SELECT_WOFFSET 0x0 +#define DC_COM_PIN_OUTPUT_SELECT0_0_LD4_OUTPUT_SELECT_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_SELECT0_0_LD4_OUTPUT_SELECT_DEFAULT_MASK _MK_MASK_CONST(0x7) +#define DC_COM_PIN_OUTPUT_SELECT0_0_LD4_OUTPUT_SELECT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_SELECT0_0_LD4_OUTPUT_SELECT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_COM_PIN_OUTPUT_SELECT0_0_LD5_OUTPUT_SELECT_SHIFT _MK_SHIFT_CONST(20) +#define DC_COM_PIN_OUTPUT_SELECT0_0_LD5_OUTPUT_SELECT_FIELD _MK_FIELD_CONST(0x7, DC_COM_PIN_OUTPUT_SELECT0_0_LD5_OUTPUT_SELECT_SHIFT) +#define DC_COM_PIN_OUTPUT_SELECT0_0_LD5_OUTPUT_SELECT_RANGE 22:20 +#define DC_COM_PIN_OUTPUT_SELECT0_0_LD5_OUTPUT_SELECT_WOFFSET 0x0 +#define DC_COM_PIN_OUTPUT_SELECT0_0_LD5_OUTPUT_SELECT_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_SELECT0_0_LD5_OUTPUT_SELECT_DEFAULT_MASK _MK_MASK_CONST(0x7) +#define DC_COM_PIN_OUTPUT_SELECT0_0_LD5_OUTPUT_SELECT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_SELECT0_0_LD5_OUTPUT_SELECT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_COM_PIN_OUTPUT_SELECT0_0_LD6_OUTPUT_SELECT_SHIFT _MK_SHIFT_CONST(24) +#define DC_COM_PIN_OUTPUT_SELECT0_0_LD6_OUTPUT_SELECT_FIELD _MK_FIELD_CONST(0x7, DC_COM_PIN_OUTPUT_SELECT0_0_LD6_OUTPUT_SELECT_SHIFT) +#define DC_COM_PIN_OUTPUT_SELECT0_0_LD6_OUTPUT_SELECT_RANGE 26:24 +#define DC_COM_PIN_OUTPUT_SELECT0_0_LD6_OUTPUT_SELECT_WOFFSET 0x0 +#define DC_COM_PIN_OUTPUT_SELECT0_0_LD6_OUTPUT_SELECT_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_SELECT0_0_LD6_OUTPUT_SELECT_DEFAULT_MASK _MK_MASK_CONST(0x7) +#define DC_COM_PIN_OUTPUT_SELECT0_0_LD6_OUTPUT_SELECT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_SELECT0_0_LD6_OUTPUT_SELECT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_COM_PIN_OUTPUT_SELECT0_0_LD7_OUTPUT_SELECT_SHIFT _MK_SHIFT_CONST(28) +#define DC_COM_PIN_OUTPUT_SELECT0_0_LD7_OUTPUT_SELECT_FIELD _MK_FIELD_CONST(0x7, DC_COM_PIN_OUTPUT_SELECT0_0_LD7_OUTPUT_SELECT_SHIFT) +#define DC_COM_PIN_OUTPUT_SELECT0_0_LD7_OUTPUT_SELECT_RANGE 30:28 +#define DC_COM_PIN_OUTPUT_SELECT0_0_LD7_OUTPUT_SELECT_WOFFSET 0x0 +#define DC_COM_PIN_OUTPUT_SELECT0_0_LD7_OUTPUT_SELECT_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_SELECT0_0_LD7_OUTPUT_SELECT_DEFAULT_MASK _MK_MASK_CONST(0x7) +#define DC_COM_PIN_OUTPUT_SELECT0_0_LD7_OUTPUT_SELECT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_SELECT0_0_LD7_OUTPUT_SELECT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_COM_PIN_OUTPUT_SELECT1_0 +#define DC_COM_PIN_OUTPUT_SELECT1_0 _MK_ADDR_CONST(0x315) +#define DC_COM_PIN_OUTPUT_SELECT1_0_SECURE 0x0 +#define DC_COM_PIN_OUTPUT_SELECT1_0_WORD_COUNT 0x1 +#define DC_COM_PIN_OUTPUT_SELECT1_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_SELECT1_0_RESET_MASK _MK_MASK_CONST(0x77777777) +#define DC_COM_PIN_OUTPUT_SELECT1_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_SELECT1_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_SELECT1_0_READ_MASK _MK_MASK_CONST(0x77777777) +#define DC_COM_PIN_OUTPUT_SELECT1_0_WRITE_MASK _MK_MASK_CONST(0x77777777) +#define DC_COM_PIN_OUTPUT_SELECT1_0_LD8_OUTPUT_SELECT_SHIFT _MK_SHIFT_CONST(0) +#define DC_COM_PIN_OUTPUT_SELECT1_0_LD8_OUTPUT_SELECT_FIELD _MK_FIELD_CONST(0x7, DC_COM_PIN_OUTPUT_SELECT1_0_LD8_OUTPUT_SELECT_SHIFT) +#define DC_COM_PIN_OUTPUT_SELECT1_0_LD8_OUTPUT_SELECT_RANGE 2:0 +#define DC_COM_PIN_OUTPUT_SELECT1_0_LD8_OUTPUT_SELECT_WOFFSET 0x0 +#define DC_COM_PIN_OUTPUT_SELECT1_0_LD8_OUTPUT_SELECT_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_SELECT1_0_LD8_OUTPUT_SELECT_DEFAULT_MASK _MK_MASK_CONST(0x7) +#define DC_COM_PIN_OUTPUT_SELECT1_0_LD8_OUTPUT_SELECT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_SELECT1_0_LD8_OUTPUT_SELECT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_COM_PIN_OUTPUT_SELECT1_0_LD9_OUTPUT_SELECT_SHIFT _MK_SHIFT_CONST(4) +#define DC_COM_PIN_OUTPUT_SELECT1_0_LD9_OUTPUT_SELECT_FIELD _MK_FIELD_CONST(0x7, DC_COM_PIN_OUTPUT_SELECT1_0_LD9_OUTPUT_SELECT_SHIFT) +#define DC_COM_PIN_OUTPUT_SELECT1_0_LD9_OUTPUT_SELECT_RANGE 6:4 +#define DC_COM_PIN_OUTPUT_SELECT1_0_LD9_OUTPUT_SELECT_WOFFSET 0x0 +#define DC_COM_PIN_OUTPUT_SELECT1_0_LD9_OUTPUT_SELECT_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_SELECT1_0_LD9_OUTPUT_SELECT_DEFAULT_MASK _MK_MASK_CONST(0x7) +#define DC_COM_PIN_OUTPUT_SELECT1_0_LD9_OUTPUT_SELECT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_SELECT1_0_LD9_OUTPUT_SELECT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_COM_PIN_OUTPUT_SELECT1_0_LD10_OUTPUT_SELECT_SHIFT _MK_SHIFT_CONST(8) +#define DC_COM_PIN_OUTPUT_SELECT1_0_LD10_OUTPUT_SELECT_FIELD _MK_FIELD_CONST(0x7, DC_COM_PIN_OUTPUT_SELECT1_0_LD10_OUTPUT_SELECT_SHIFT) +#define DC_COM_PIN_OUTPUT_SELECT1_0_LD10_OUTPUT_SELECT_RANGE 10:8 +#define DC_COM_PIN_OUTPUT_SELECT1_0_LD10_OUTPUT_SELECT_WOFFSET 0x0 +#define DC_COM_PIN_OUTPUT_SELECT1_0_LD10_OUTPUT_SELECT_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_SELECT1_0_LD10_OUTPUT_SELECT_DEFAULT_MASK _MK_MASK_CONST(0x7) +#define DC_COM_PIN_OUTPUT_SELECT1_0_LD10_OUTPUT_SELECT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_SELECT1_0_LD10_OUTPUT_SELECT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_COM_PIN_OUTPUT_SELECT1_0_LD11_OUTPUT_SELECT_SHIFT _MK_SHIFT_CONST(12) +#define DC_COM_PIN_OUTPUT_SELECT1_0_LD11_OUTPUT_SELECT_FIELD _MK_FIELD_CONST(0x7, DC_COM_PIN_OUTPUT_SELECT1_0_LD11_OUTPUT_SELECT_SHIFT) +#define DC_COM_PIN_OUTPUT_SELECT1_0_LD11_OUTPUT_SELECT_RANGE 14:12 +#define DC_COM_PIN_OUTPUT_SELECT1_0_LD11_OUTPUT_SELECT_WOFFSET 0x0 +#define DC_COM_PIN_OUTPUT_SELECT1_0_LD11_OUTPUT_SELECT_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_SELECT1_0_LD11_OUTPUT_SELECT_DEFAULT_MASK _MK_MASK_CONST(0x7) +#define DC_COM_PIN_OUTPUT_SELECT1_0_LD11_OUTPUT_SELECT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_SELECT1_0_LD11_OUTPUT_SELECT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_COM_PIN_OUTPUT_SELECT1_0_LD12_OUTPUT_SELECT_SHIFT _MK_SHIFT_CONST(16) +#define DC_COM_PIN_OUTPUT_SELECT1_0_LD12_OUTPUT_SELECT_FIELD _MK_FIELD_CONST(0x7, DC_COM_PIN_OUTPUT_SELECT1_0_LD12_OUTPUT_SELECT_SHIFT) +#define DC_COM_PIN_OUTPUT_SELECT1_0_LD12_OUTPUT_SELECT_RANGE 18:16 +#define DC_COM_PIN_OUTPUT_SELECT1_0_LD12_OUTPUT_SELECT_WOFFSET 0x0 +#define DC_COM_PIN_OUTPUT_SELECT1_0_LD12_OUTPUT_SELECT_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_SELECT1_0_LD12_OUTPUT_SELECT_DEFAULT_MASK _MK_MASK_CONST(0x7) +#define DC_COM_PIN_OUTPUT_SELECT1_0_LD12_OUTPUT_SELECT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_SELECT1_0_LD12_OUTPUT_SELECT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_COM_PIN_OUTPUT_SELECT1_0_LD13_OUTPUT_SELECT_SHIFT _MK_SHIFT_CONST(20) +#define DC_COM_PIN_OUTPUT_SELECT1_0_LD13_OUTPUT_SELECT_FIELD _MK_FIELD_CONST(0x7, DC_COM_PIN_OUTPUT_SELECT1_0_LD13_OUTPUT_SELECT_SHIFT) +#define DC_COM_PIN_OUTPUT_SELECT1_0_LD13_OUTPUT_SELECT_RANGE 22:20 +#define DC_COM_PIN_OUTPUT_SELECT1_0_LD13_OUTPUT_SELECT_WOFFSET 0x0 +#define DC_COM_PIN_OUTPUT_SELECT1_0_LD13_OUTPUT_SELECT_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_SELECT1_0_LD13_OUTPUT_SELECT_DEFAULT_MASK _MK_MASK_CONST(0x7) +#define DC_COM_PIN_OUTPUT_SELECT1_0_LD13_OUTPUT_SELECT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_SELECT1_0_LD13_OUTPUT_SELECT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_COM_PIN_OUTPUT_SELECT1_0_LD14_OUTPUT_SELECT_SHIFT _MK_SHIFT_CONST(24) +#define DC_COM_PIN_OUTPUT_SELECT1_0_LD14_OUTPUT_SELECT_FIELD _MK_FIELD_CONST(0x7, DC_COM_PIN_OUTPUT_SELECT1_0_LD14_OUTPUT_SELECT_SHIFT) +#define DC_COM_PIN_OUTPUT_SELECT1_0_LD14_OUTPUT_SELECT_RANGE 26:24 +#define DC_COM_PIN_OUTPUT_SELECT1_0_LD14_OUTPUT_SELECT_WOFFSET 0x0 +#define DC_COM_PIN_OUTPUT_SELECT1_0_LD14_OUTPUT_SELECT_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_SELECT1_0_LD14_OUTPUT_SELECT_DEFAULT_MASK _MK_MASK_CONST(0x7) +#define DC_COM_PIN_OUTPUT_SELECT1_0_LD14_OUTPUT_SELECT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_SELECT1_0_LD14_OUTPUT_SELECT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_COM_PIN_OUTPUT_SELECT1_0_LD15_OUTPUT_SELECT_SHIFT _MK_SHIFT_CONST(28) +#define DC_COM_PIN_OUTPUT_SELECT1_0_LD15_OUTPUT_SELECT_FIELD _MK_FIELD_CONST(0x7, DC_COM_PIN_OUTPUT_SELECT1_0_LD15_OUTPUT_SELECT_SHIFT) +#define DC_COM_PIN_OUTPUT_SELECT1_0_LD15_OUTPUT_SELECT_RANGE 30:28 +#define DC_COM_PIN_OUTPUT_SELECT1_0_LD15_OUTPUT_SELECT_WOFFSET 0x0 +#define DC_COM_PIN_OUTPUT_SELECT1_0_LD15_OUTPUT_SELECT_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_SELECT1_0_LD15_OUTPUT_SELECT_DEFAULT_MASK _MK_MASK_CONST(0x7) +#define DC_COM_PIN_OUTPUT_SELECT1_0_LD15_OUTPUT_SELECT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_SELECT1_0_LD15_OUTPUT_SELECT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_COM_PIN_OUTPUT_SELECT2_0 +#define DC_COM_PIN_OUTPUT_SELECT2_0 _MK_ADDR_CONST(0x316) +#define DC_COM_PIN_OUTPUT_SELECT2_0_SECURE 0x0 +#define DC_COM_PIN_OUTPUT_SELECT2_0_WORD_COUNT 0x1 +#define DC_COM_PIN_OUTPUT_SELECT2_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_SELECT2_0_RESET_MASK _MK_MASK_CONST(0x77) +#define DC_COM_PIN_OUTPUT_SELECT2_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_SELECT2_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_SELECT2_0_READ_MASK _MK_MASK_CONST(0x77) +#define DC_COM_PIN_OUTPUT_SELECT2_0_WRITE_MASK _MK_MASK_CONST(0x77) +#define DC_COM_PIN_OUTPUT_SELECT2_0_LD16_OUTPUT_SELECT_SHIFT _MK_SHIFT_CONST(0) +#define DC_COM_PIN_OUTPUT_SELECT2_0_LD16_OUTPUT_SELECT_FIELD _MK_FIELD_CONST(0x7, DC_COM_PIN_OUTPUT_SELECT2_0_LD16_OUTPUT_SELECT_SHIFT) +#define DC_COM_PIN_OUTPUT_SELECT2_0_LD16_OUTPUT_SELECT_RANGE 2:0 +#define DC_COM_PIN_OUTPUT_SELECT2_0_LD16_OUTPUT_SELECT_WOFFSET 0x0 +#define DC_COM_PIN_OUTPUT_SELECT2_0_LD16_OUTPUT_SELECT_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_SELECT2_0_LD16_OUTPUT_SELECT_DEFAULT_MASK _MK_MASK_CONST(0x7) +#define DC_COM_PIN_OUTPUT_SELECT2_0_LD16_OUTPUT_SELECT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_SELECT2_0_LD16_OUTPUT_SELECT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_COM_PIN_OUTPUT_SELECT2_0_LD17_OUTPUT_SELECT_SHIFT _MK_SHIFT_CONST(4) +#define DC_COM_PIN_OUTPUT_SELECT2_0_LD17_OUTPUT_SELECT_FIELD _MK_FIELD_CONST(0x7, DC_COM_PIN_OUTPUT_SELECT2_0_LD17_OUTPUT_SELECT_SHIFT) +#define DC_COM_PIN_OUTPUT_SELECT2_0_LD17_OUTPUT_SELECT_RANGE 6:4 +#define DC_COM_PIN_OUTPUT_SELECT2_0_LD17_OUTPUT_SELECT_WOFFSET 0x0 +#define DC_COM_PIN_OUTPUT_SELECT2_0_LD17_OUTPUT_SELECT_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_SELECT2_0_LD17_OUTPUT_SELECT_DEFAULT_MASK _MK_MASK_CONST(0x7) +#define DC_COM_PIN_OUTPUT_SELECT2_0_LD17_OUTPUT_SELECT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_SELECT2_0_LD17_OUTPUT_SELECT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_COM_PIN_OUTPUT_SELECT3_0 +#define DC_COM_PIN_OUTPUT_SELECT3_0 _MK_ADDR_CONST(0x317) +#define DC_COM_PIN_OUTPUT_SELECT3_0_SECURE 0x0 +#define DC_COM_PIN_OUTPUT_SELECT3_0_WORD_COUNT 0x1 +#define DC_COM_PIN_OUTPUT_SELECT3_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_SELECT3_0_RESET_MASK _MK_MASK_CONST(0x77770777) +#define DC_COM_PIN_OUTPUT_SELECT3_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_SELECT3_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_SELECT3_0_READ_MASK _MK_MASK_CONST(0x77770777) +#define DC_COM_PIN_OUTPUT_SELECT3_0_WRITE_MASK _MK_MASK_CONST(0x77770777) +#define DC_COM_PIN_OUTPUT_SELECT3_0_LPW0_OUTPUT_SELECT_SHIFT _MK_SHIFT_CONST(0) +#define DC_COM_PIN_OUTPUT_SELECT3_0_LPW0_OUTPUT_SELECT_FIELD _MK_FIELD_CONST(0x7, DC_COM_PIN_OUTPUT_SELECT3_0_LPW0_OUTPUT_SELECT_SHIFT) +#define DC_COM_PIN_OUTPUT_SELECT3_0_LPW0_OUTPUT_SELECT_RANGE 2:0 +#define DC_COM_PIN_OUTPUT_SELECT3_0_LPW0_OUTPUT_SELECT_WOFFSET 0x0 +#define DC_COM_PIN_OUTPUT_SELECT3_0_LPW0_OUTPUT_SELECT_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_SELECT3_0_LPW0_OUTPUT_SELECT_DEFAULT_MASK _MK_MASK_CONST(0x7) +#define DC_COM_PIN_OUTPUT_SELECT3_0_LPW0_OUTPUT_SELECT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_SELECT3_0_LPW0_OUTPUT_SELECT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_COM_PIN_OUTPUT_SELECT3_0_LPW1_OUTPUT_SELECT_SHIFT _MK_SHIFT_CONST(4) +#define DC_COM_PIN_OUTPUT_SELECT3_0_LPW1_OUTPUT_SELECT_FIELD _MK_FIELD_CONST(0x7, DC_COM_PIN_OUTPUT_SELECT3_0_LPW1_OUTPUT_SELECT_SHIFT) +#define DC_COM_PIN_OUTPUT_SELECT3_0_LPW1_OUTPUT_SELECT_RANGE 6:4 +#define DC_COM_PIN_OUTPUT_SELECT3_0_LPW1_OUTPUT_SELECT_WOFFSET 0x0 +#define DC_COM_PIN_OUTPUT_SELECT3_0_LPW1_OUTPUT_SELECT_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_SELECT3_0_LPW1_OUTPUT_SELECT_DEFAULT_MASK _MK_MASK_CONST(0x7) +#define DC_COM_PIN_OUTPUT_SELECT3_0_LPW1_OUTPUT_SELECT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_SELECT3_0_LPW1_OUTPUT_SELECT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_COM_PIN_OUTPUT_SELECT3_0_LPW2_OUTPUT_SELECT_SHIFT _MK_SHIFT_CONST(8) +#define DC_COM_PIN_OUTPUT_SELECT3_0_LPW2_OUTPUT_SELECT_FIELD _MK_FIELD_CONST(0x7, DC_COM_PIN_OUTPUT_SELECT3_0_LPW2_OUTPUT_SELECT_SHIFT) +#define DC_COM_PIN_OUTPUT_SELECT3_0_LPW2_OUTPUT_SELECT_RANGE 10:8 +#define DC_COM_PIN_OUTPUT_SELECT3_0_LPW2_OUTPUT_SELECT_WOFFSET 0x0 +#define DC_COM_PIN_OUTPUT_SELECT3_0_LPW2_OUTPUT_SELECT_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_SELECT3_0_LPW2_OUTPUT_SELECT_DEFAULT_MASK _MK_MASK_CONST(0x7) +#define DC_COM_PIN_OUTPUT_SELECT3_0_LPW2_OUTPUT_SELECT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_SELECT3_0_LPW2_OUTPUT_SELECT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_COM_PIN_OUTPUT_SELECT3_0_LSC0_OUTPUT_SELECT_SHIFT _MK_SHIFT_CONST(16) +#define DC_COM_PIN_OUTPUT_SELECT3_0_LSC0_OUTPUT_SELECT_FIELD _MK_FIELD_CONST(0x7, DC_COM_PIN_OUTPUT_SELECT3_0_LSC0_OUTPUT_SELECT_SHIFT) +#define DC_COM_PIN_OUTPUT_SELECT3_0_LSC0_OUTPUT_SELECT_RANGE 18:16 +#define DC_COM_PIN_OUTPUT_SELECT3_0_LSC0_OUTPUT_SELECT_WOFFSET 0x0 +#define DC_COM_PIN_OUTPUT_SELECT3_0_LSC0_OUTPUT_SELECT_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_SELECT3_0_LSC0_OUTPUT_SELECT_DEFAULT_MASK _MK_MASK_CONST(0x7) +#define DC_COM_PIN_OUTPUT_SELECT3_0_LSC0_OUTPUT_SELECT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_SELECT3_0_LSC0_OUTPUT_SELECT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_COM_PIN_OUTPUT_SELECT3_0_LSC1_OUTPUT_SELECT_SHIFT _MK_SHIFT_CONST(20) +#define DC_COM_PIN_OUTPUT_SELECT3_0_LSC1_OUTPUT_SELECT_FIELD _MK_FIELD_CONST(0x7, DC_COM_PIN_OUTPUT_SELECT3_0_LSC1_OUTPUT_SELECT_SHIFT) +#define DC_COM_PIN_OUTPUT_SELECT3_0_LSC1_OUTPUT_SELECT_RANGE 22:20 +#define DC_COM_PIN_OUTPUT_SELECT3_0_LSC1_OUTPUT_SELECT_WOFFSET 0x0 +#define DC_COM_PIN_OUTPUT_SELECT3_0_LSC1_OUTPUT_SELECT_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_SELECT3_0_LSC1_OUTPUT_SELECT_DEFAULT_MASK _MK_MASK_CONST(0x7) +#define DC_COM_PIN_OUTPUT_SELECT3_0_LSC1_OUTPUT_SELECT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_SELECT3_0_LSC1_OUTPUT_SELECT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_COM_PIN_OUTPUT_SELECT3_0_LVS_OUTPUT_SELECT_SHIFT _MK_SHIFT_CONST(24) +#define DC_COM_PIN_OUTPUT_SELECT3_0_LVS_OUTPUT_SELECT_FIELD _MK_FIELD_CONST(0x7, DC_COM_PIN_OUTPUT_SELECT3_0_LVS_OUTPUT_SELECT_SHIFT) +#define DC_COM_PIN_OUTPUT_SELECT3_0_LVS_OUTPUT_SELECT_RANGE 26:24 +#define DC_COM_PIN_OUTPUT_SELECT3_0_LVS_OUTPUT_SELECT_WOFFSET 0x0 +#define DC_COM_PIN_OUTPUT_SELECT3_0_LVS_OUTPUT_SELECT_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_SELECT3_0_LVS_OUTPUT_SELECT_DEFAULT_MASK _MK_MASK_CONST(0x7) +#define DC_COM_PIN_OUTPUT_SELECT3_0_LVS_OUTPUT_SELECT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_SELECT3_0_LVS_OUTPUT_SELECT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_COM_PIN_OUTPUT_SELECT3_0_LHS_OUTPUT_SELECT_SHIFT _MK_SHIFT_CONST(28) +#define DC_COM_PIN_OUTPUT_SELECT3_0_LHS_OUTPUT_SELECT_FIELD _MK_FIELD_CONST(0x7, DC_COM_PIN_OUTPUT_SELECT3_0_LHS_OUTPUT_SELECT_SHIFT) +#define DC_COM_PIN_OUTPUT_SELECT3_0_LHS_OUTPUT_SELECT_RANGE 30:28 +#define DC_COM_PIN_OUTPUT_SELECT3_0_LHS_OUTPUT_SELECT_WOFFSET 0x0 +#define DC_COM_PIN_OUTPUT_SELECT3_0_LHS_OUTPUT_SELECT_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_SELECT3_0_LHS_OUTPUT_SELECT_DEFAULT_MASK _MK_MASK_CONST(0x7) +#define DC_COM_PIN_OUTPUT_SELECT3_0_LHS_OUTPUT_SELECT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_SELECT3_0_LHS_OUTPUT_SELECT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_COM_PIN_OUTPUT_SELECT4_0 +#define DC_COM_PIN_OUTPUT_SELECT4_0 _MK_ADDR_CONST(0x318) +#define DC_COM_PIN_OUTPUT_SELECT4_0_SECURE 0x0 +#define DC_COM_PIN_OUTPUT_SELECT4_0_WORD_COUNT 0x1 +#define DC_COM_PIN_OUTPUT_SELECT4_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_SELECT4_0_RESET_MASK _MK_MASK_CONST(0x770777) +#define DC_COM_PIN_OUTPUT_SELECT4_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_SELECT4_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_SELECT4_0_READ_MASK _MK_MASK_CONST(0x770777) +#define DC_COM_PIN_OUTPUT_SELECT4_0_WRITE_MASK _MK_MASK_CONST(0x770777) +#define DC_COM_PIN_OUTPUT_SELECT4_0_LHP0_OUTPUT_SELECT_SHIFT _MK_SHIFT_CONST(0) +#define DC_COM_PIN_OUTPUT_SELECT4_0_LHP0_OUTPUT_SELECT_FIELD _MK_FIELD_CONST(0x7, DC_COM_PIN_OUTPUT_SELECT4_0_LHP0_OUTPUT_SELECT_SHIFT) +#define DC_COM_PIN_OUTPUT_SELECT4_0_LHP0_OUTPUT_SELECT_RANGE 2:0 +#define DC_COM_PIN_OUTPUT_SELECT4_0_LHP0_OUTPUT_SELECT_WOFFSET 0x0 +#define DC_COM_PIN_OUTPUT_SELECT4_0_LHP0_OUTPUT_SELECT_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_SELECT4_0_LHP0_OUTPUT_SELECT_DEFAULT_MASK _MK_MASK_CONST(0x7) +#define DC_COM_PIN_OUTPUT_SELECT4_0_LHP0_OUTPUT_SELECT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_SELECT4_0_LHP0_OUTPUT_SELECT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_COM_PIN_OUTPUT_SELECT4_0_LHP1_OUTPUT_SELECT_SHIFT _MK_SHIFT_CONST(4) +#define DC_COM_PIN_OUTPUT_SELECT4_0_LHP1_OUTPUT_SELECT_FIELD _MK_FIELD_CONST(0x7, DC_COM_PIN_OUTPUT_SELECT4_0_LHP1_OUTPUT_SELECT_SHIFT) +#define DC_COM_PIN_OUTPUT_SELECT4_0_LHP1_OUTPUT_SELECT_RANGE 6:4 +#define DC_COM_PIN_OUTPUT_SELECT4_0_LHP1_OUTPUT_SELECT_WOFFSET 0x0 +#define DC_COM_PIN_OUTPUT_SELECT4_0_LHP1_OUTPUT_SELECT_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_SELECT4_0_LHP1_OUTPUT_SELECT_DEFAULT_MASK _MK_MASK_CONST(0x7) +#define DC_COM_PIN_OUTPUT_SELECT4_0_LHP1_OUTPUT_SELECT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_SELECT4_0_LHP1_OUTPUT_SELECT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_COM_PIN_OUTPUT_SELECT4_0_LHP2_OUTPUT_SELECT_SHIFT _MK_SHIFT_CONST(8) +#define DC_COM_PIN_OUTPUT_SELECT4_0_LHP2_OUTPUT_SELECT_FIELD _MK_FIELD_CONST(0x7, DC_COM_PIN_OUTPUT_SELECT4_0_LHP2_OUTPUT_SELECT_SHIFT) +#define DC_COM_PIN_OUTPUT_SELECT4_0_LHP2_OUTPUT_SELECT_RANGE 10:8 +#define DC_COM_PIN_OUTPUT_SELECT4_0_LHP2_OUTPUT_SELECT_WOFFSET 0x0 +#define DC_COM_PIN_OUTPUT_SELECT4_0_LHP2_OUTPUT_SELECT_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_SELECT4_0_LHP2_OUTPUT_SELECT_DEFAULT_MASK _MK_MASK_CONST(0x7) +#define DC_COM_PIN_OUTPUT_SELECT4_0_LHP2_OUTPUT_SELECT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_SELECT4_0_LHP2_OUTPUT_SELECT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_COM_PIN_OUTPUT_SELECT4_0_LVP0_OUTPUT_SELECT_SHIFT _MK_SHIFT_CONST(16) +#define DC_COM_PIN_OUTPUT_SELECT4_0_LVP0_OUTPUT_SELECT_FIELD _MK_FIELD_CONST(0x7, DC_COM_PIN_OUTPUT_SELECT4_0_LVP0_OUTPUT_SELECT_SHIFT) +#define DC_COM_PIN_OUTPUT_SELECT4_0_LVP0_OUTPUT_SELECT_RANGE 18:16 +#define DC_COM_PIN_OUTPUT_SELECT4_0_LVP0_OUTPUT_SELECT_WOFFSET 0x0 +#define DC_COM_PIN_OUTPUT_SELECT4_0_LVP0_OUTPUT_SELECT_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_SELECT4_0_LVP0_OUTPUT_SELECT_DEFAULT_MASK _MK_MASK_CONST(0x7) +#define DC_COM_PIN_OUTPUT_SELECT4_0_LVP0_OUTPUT_SELECT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_SELECT4_0_LVP0_OUTPUT_SELECT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_COM_PIN_OUTPUT_SELECT4_0_LVP1_OUTPUT_SELECT_SHIFT _MK_SHIFT_CONST(20) +#define DC_COM_PIN_OUTPUT_SELECT4_0_LVP1_OUTPUT_SELECT_FIELD _MK_FIELD_CONST(0x7, DC_COM_PIN_OUTPUT_SELECT4_0_LVP1_OUTPUT_SELECT_SHIFT) +#define DC_COM_PIN_OUTPUT_SELECT4_0_LVP1_OUTPUT_SELECT_RANGE 22:20 +#define DC_COM_PIN_OUTPUT_SELECT4_0_LVP1_OUTPUT_SELECT_WOFFSET 0x0 +#define DC_COM_PIN_OUTPUT_SELECT4_0_LVP1_OUTPUT_SELECT_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_SELECT4_0_LVP1_OUTPUT_SELECT_DEFAULT_MASK _MK_MASK_CONST(0x7) +#define DC_COM_PIN_OUTPUT_SELECT4_0_LVP1_OUTPUT_SELECT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_SELECT4_0_LVP1_OUTPUT_SELECT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_COM_PIN_OUTPUT_SELECT5_0 +#define DC_COM_PIN_OUTPUT_SELECT5_0 _MK_ADDR_CONST(0x319) +#define DC_COM_PIN_OUTPUT_SELECT5_0_SECURE 0x0 +#define DC_COM_PIN_OUTPUT_SELECT5_0_WORD_COUNT 0x1 +#define DC_COM_PIN_OUTPUT_SELECT5_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_SELECT5_0_RESET_MASK _MK_MASK_CONST(0x7777) +#define DC_COM_PIN_OUTPUT_SELECT5_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_SELECT5_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_SELECT5_0_READ_MASK _MK_MASK_CONST(0x7777) +#define DC_COM_PIN_OUTPUT_SELECT5_0_WRITE_MASK _MK_MASK_CONST(0x7777) +#define DC_COM_PIN_OUTPUT_SELECT5_0_LM0_OUTPUT_SELECT_SHIFT _MK_SHIFT_CONST(0) +#define DC_COM_PIN_OUTPUT_SELECT5_0_LM0_OUTPUT_SELECT_FIELD _MK_FIELD_CONST(0x7, DC_COM_PIN_OUTPUT_SELECT5_0_LM0_OUTPUT_SELECT_SHIFT) +#define DC_COM_PIN_OUTPUT_SELECT5_0_LM0_OUTPUT_SELECT_RANGE 2:0 +#define DC_COM_PIN_OUTPUT_SELECT5_0_LM0_OUTPUT_SELECT_WOFFSET 0x0 +#define DC_COM_PIN_OUTPUT_SELECT5_0_LM0_OUTPUT_SELECT_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_SELECT5_0_LM0_OUTPUT_SELECT_DEFAULT_MASK _MK_MASK_CONST(0x7) +#define DC_COM_PIN_OUTPUT_SELECT5_0_LM0_OUTPUT_SELECT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_SELECT5_0_LM0_OUTPUT_SELECT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_COM_PIN_OUTPUT_SELECT5_0_LM1_OUTPUT_SELECT_SHIFT _MK_SHIFT_CONST(4) +#define DC_COM_PIN_OUTPUT_SELECT5_0_LM1_OUTPUT_SELECT_FIELD _MK_FIELD_CONST(0x7, DC_COM_PIN_OUTPUT_SELECT5_0_LM1_OUTPUT_SELECT_SHIFT) +#define DC_COM_PIN_OUTPUT_SELECT5_0_LM1_OUTPUT_SELECT_RANGE 6:4 +#define DC_COM_PIN_OUTPUT_SELECT5_0_LM1_OUTPUT_SELECT_WOFFSET 0x0 +#define DC_COM_PIN_OUTPUT_SELECT5_0_LM1_OUTPUT_SELECT_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_SELECT5_0_LM1_OUTPUT_SELECT_DEFAULT_MASK _MK_MASK_CONST(0x7) +#define DC_COM_PIN_OUTPUT_SELECT5_0_LM1_OUTPUT_SELECT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_SELECT5_0_LM1_OUTPUT_SELECT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_COM_PIN_OUTPUT_SELECT5_0_LDI_OUTPUT_SELECT_SHIFT _MK_SHIFT_CONST(8) +#define DC_COM_PIN_OUTPUT_SELECT5_0_LDI_OUTPUT_SELECT_FIELD _MK_FIELD_CONST(0x7, DC_COM_PIN_OUTPUT_SELECT5_0_LDI_OUTPUT_SELECT_SHIFT) +#define DC_COM_PIN_OUTPUT_SELECT5_0_LDI_OUTPUT_SELECT_RANGE 10:8 +#define DC_COM_PIN_OUTPUT_SELECT5_0_LDI_OUTPUT_SELECT_WOFFSET 0x0 +#define DC_COM_PIN_OUTPUT_SELECT5_0_LDI_OUTPUT_SELECT_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_SELECT5_0_LDI_OUTPUT_SELECT_DEFAULT_MASK _MK_MASK_CONST(0x7) +#define DC_COM_PIN_OUTPUT_SELECT5_0_LDI_OUTPUT_SELECT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_SELECT5_0_LDI_OUTPUT_SELECT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_COM_PIN_OUTPUT_SELECT5_0_LPP_OUTPUT_SELECT_SHIFT _MK_SHIFT_CONST(12) +#define DC_COM_PIN_OUTPUT_SELECT5_0_LPP_OUTPUT_SELECT_FIELD _MK_FIELD_CONST(0x7, DC_COM_PIN_OUTPUT_SELECT5_0_LPP_OUTPUT_SELECT_SHIFT) +#define DC_COM_PIN_OUTPUT_SELECT5_0_LPP_OUTPUT_SELECT_RANGE 14:12 +#define DC_COM_PIN_OUTPUT_SELECT5_0_LPP_OUTPUT_SELECT_WOFFSET 0x0 +#define DC_COM_PIN_OUTPUT_SELECT5_0_LPP_OUTPUT_SELECT_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_SELECT5_0_LPP_OUTPUT_SELECT_DEFAULT_MASK _MK_MASK_CONST(0x7) +#define DC_COM_PIN_OUTPUT_SELECT5_0_LPP_OUTPUT_SELECT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_SELECT5_0_LPP_OUTPUT_SELECT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_COM_PIN_OUTPUT_SELECT6_0 +#define DC_COM_PIN_OUTPUT_SELECT6_0 _MK_ADDR_CONST(0x31a) +#define DC_COM_PIN_OUTPUT_SELECT6_0_SECURE 0x0 +#define DC_COM_PIN_OUTPUT_SELECT6_0_WORD_COUNT 0x1 +#define DC_COM_PIN_OUTPUT_SELECT6_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_SELECT6_0_RESET_MASK _MK_MASK_CONST(0x777777) +#define DC_COM_PIN_OUTPUT_SELECT6_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_SELECT6_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_SELECT6_0_READ_MASK _MK_MASK_CONST(0x777777) +#define DC_COM_PIN_OUTPUT_SELECT6_0_WRITE_MASK _MK_MASK_CONST(0x777777) +#define DC_COM_PIN_OUTPUT_SELECT6_0_LSCK_OUTPUT_SELECT_SHIFT _MK_SHIFT_CONST(0) +#define DC_COM_PIN_OUTPUT_SELECT6_0_LSCK_OUTPUT_SELECT_FIELD _MK_FIELD_CONST(0x7, DC_COM_PIN_OUTPUT_SELECT6_0_LSCK_OUTPUT_SELECT_SHIFT) +#define DC_COM_PIN_OUTPUT_SELECT6_0_LSCK_OUTPUT_SELECT_RANGE 2:0 +#define DC_COM_PIN_OUTPUT_SELECT6_0_LSCK_OUTPUT_SELECT_WOFFSET 0x0 +#define DC_COM_PIN_OUTPUT_SELECT6_0_LSCK_OUTPUT_SELECT_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_SELECT6_0_LSCK_OUTPUT_SELECT_DEFAULT_MASK _MK_MASK_CONST(0x7) +#define DC_COM_PIN_OUTPUT_SELECT6_0_LSCK_OUTPUT_SELECT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_SELECT6_0_LSCK_OUTPUT_SELECT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_COM_PIN_OUTPUT_SELECT6_0_LSDA_OUTPUT_SELECT_SHIFT _MK_SHIFT_CONST(4) +#define DC_COM_PIN_OUTPUT_SELECT6_0_LSDA_OUTPUT_SELECT_FIELD _MK_FIELD_CONST(0x7, DC_COM_PIN_OUTPUT_SELECT6_0_LSDA_OUTPUT_SELECT_SHIFT) +#define DC_COM_PIN_OUTPUT_SELECT6_0_LSDA_OUTPUT_SELECT_RANGE 6:4 +#define DC_COM_PIN_OUTPUT_SELECT6_0_LSDA_OUTPUT_SELECT_WOFFSET 0x0 +#define DC_COM_PIN_OUTPUT_SELECT6_0_LSDA_OUTPUT_SELECT_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_SELECT6_0_LSDA_OUTPUT_SELECT_DEFAULT_MASK _MK_MASK_CONST(0x7) +#define DC_COM_PIN_OUTPUT_SELECT6_0_LSDA_OUTPUT_SELECT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_SELECT6_0_LSDA_OUTPUT_SELECT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_COM_PIN_OUTPUT_SELECT6_0_LCSN_OUTPUT_SELECT_SHIFT _MK_SHIFT_CONST(8) +#define DC_COM_PIN_OUTPUT_SELECT6_0_LCSN_OUTPUT_SELECT_FIELD _MK_FIELD_CONST(0x7, DC_COM_PIN_OUTPUT_SELECT6_0_LCSN_OUTPUT_SELECT_SHIFT) +#define DC_COM_PIN_OUTPUT_SELECT6_0_LCSN_OUTPUT_SELECT_RANGE 10:8 +#define DC_COM_PIN_OUTPUT_SELECT6_0_LCSN_OUTPUT_SELECT_WOFFSET 0x0 +#define DC_COM_PIN_OUTPUT_SELECT6_0_LCSN_OUTPUT_SELECT_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_SELECT6_0_LCSN_OUTPUT_SELECT_DEFAULT_MASK _MK_MASK_CONST(0x7) +#define DC_COM_PIN_OUTPUT_SELECT6_0_LCSN_OUTPUT_SELECT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_SELECT6_0_LCSN_OUTPUT_SELECT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_COM_PIN_OUTPUT_SELECT6_0_LDC_OUTPUT_SELECT_SHIFT _MK_SHIFT_CONST(12) +#define DC_COM_PIN_OUTPUT_SELECT6_0_LDC_OUTPUT_SELECT_FIELD _MK_FIELD_CONST(0x7, DC_COM_PIN_OUTPUT_SELECT6_0_LDC_OUTPUT_SELECT_SHIFT) +#define DC_COM_PIN_OUTPUT_SELECT6_0_LDC_OUTPUT_SELECT_RANGE 14:12 +#define DC_COM_PIN_OUTPUT_SELECT6_0_LDC_OUTPUT_SELECT_WOFFSET 0x0 +#define DC_COM_PIN_OUTPUT_SELECT6_0_LDC_OUTPUT_SELECT_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_SELECT6_0_LDC_OUTPUT_SELECT_DEFAULT_MASK _MK_MASK_CONST(0x7) +#define DC_COM_PIN_OUTPUT_SELECT6_0_LDC_OUTPUT_SELECT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_SELECT6_0_LDC_OUTPUT_SELECT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_COM_PIN_OUTPUT_SELECT6_0_LSPI_OUTPUT_SELECT_SHIFT _MK_SHIFT_CONST(16) +#define DC_COM_PIN_OUTPUT_SELECT6_0_LSPI_OUTPUT_SELECT_FIELD _MK_FIELD_CONST(0x7, DC_COM_PIN_OUTPUT_SELECT6_0_LSPI_OUTPUT_SELECT_SHIFT) +#define DC_COM_PIN_OUTPUT_SELECT6_0_LSPI_OUTPUT_SELECT_RANGE 18:16 +#define DC_COM_PIN_OUTPUT_SELECT6_0_LSPI_OUTPUT_SELECT_WOFFSET 0x0 +#define DC_COM_PIN_OUTPUT_SELECT6_0_LSPI_OUTPUT_SELECT_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_SELECT6_0_LSPI_OUTPUT_SELECT_DEFAULT_MASK _MK_MASK_CONST(0x7) +#define DC_COM_PIN_OUTPUT_SELECT6_0_LSPI_OUTPUT_SELECT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_SELECT6_0_LSPI_OUTPUT_SELECT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_COM_PIN_OUTPUT_SELECT6_0_LSDI_OUTPUT_SELECT_SHIFT _MK_SHIFT_CONST(20) +#define DC_COM_PIN_OUTPUT_SELECT6_0_LSDI_OUTPUT_SELECT_FIELD _MK_FIELD_CONST(0x7, DC_COM_PIN_OUTPUT_SELECT6_0_LSDI_OUTPUT_SELECT_SHIFT) +#define DC_COM_PIN_OUTPUT_SELECT6_0_LSDI_OUTPUT_SELECT_RANGE 22:20 +#define DC_COM_PIN_OUTPUT_SELECT6_0_LSDI_OUTPUT_SELECT_WOFFSET 0x0 +#define DC_COM_PIN_OUTPUT_SELECT6_0_LSDI_OUTPUT_SELECT_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_SELECT6_0_LSDI_OUTPUT_SELECT_DEFAULT_MASK _MK_MASK_CONST(0x7) +#define DC_COM_PIN_OUTPUT_SELECT6_0_LSDI_OUTPUT_SELECT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_OUTPUT_SELECT6_0_LSDI_OUTPUT_SELECT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_COM_PIN_MISC_CONTROL_0 +#define DC_COM_PIN_MISC_CONTROL_0 _MK_ADDR_CONST(0x31b) +#define DC_COM_PIN_MISC_CONTROL_0_SECURE 0x0 +#define DC_COM_PIN_MISC_CONTROL_0_WORD_COUNT 0x1 +#define DC_COM_PIN_MISC_CONTROL_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_COM_PIN_MISC_CONTROL_0_RESET_MASK _MK_MASK_CONST(0x4) +#define DC_COM_PIN_MISC_CONTROL_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_COM_PIN_MISC_CONTROL_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_PIN_MISC_CONTROL_0_READ_MASK _MK_MASK_CONST(0x4) +#define DC_COM_PIN_MISC_CONTROL_0_WRITE_MASK _MK_MASK_CONST(0x4) +#define DC_COM_PIN_MISC_CONTROL_0_DISP_CLOCK_OUTPUT_SHIFT _MK_SHIFT_CONST(2) +#define DC_COM_PIN_MISC_CONTROL_0_DISP_CLOCK_OUTPUT_FIELD _MK_FIELD_CONST(0x1, DC_COM_PIN_MISC_CONTROL_0_DISP_CLOCK_OUTPUT_SHIFT) +#define DC_COM_PIN_MISC_CONTROL_0_DISP_CLOCK_OUTPUT_RANGE 2:2 +#define DC_COM_PIN_MISC_CONTROL_0_DISP_CLOCK_OUTPUT_WOFFSET 0x0 +#define DC_COM_PIN_MISC_CONTROL_0_DISP_CLOCK_OUTPUT_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_MISC_CONTROL_0_DISP_CLOCK_OUTPUT_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_COM_PIN_MISC_CONTROL_0_DISP_CLOCK_OUTPUT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PIN_MISC_CONTROL_0_DISP_CLOCK_OUTPUT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_PIN_MISC_CONTROL_0_DISP_CLOCK_OUTPUT_DISABLE _MK_ENUM_CONST(0) +#define DC_COM_PIN_MISC_CONTROL_0_DISP_CLOCK_OUTPUT_ENABLE _MK_ENUM_CONST(1) + + +// Register DC_COM_PM0_CONTROL_0 +#define DC_COM_PM0_CONTROL_0 _MK_ADDR_CONST(0x31c) +#define DC_COM_PM0_CONTROL_0_SECURE 0x0 +#define DC_COM_PM0_CONTROL_0_WORD_COUNT 0x1 +#define DC_COM_PM0_CONTROL_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_COM_PM0_CONTROL_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_COM_PM0_CONTROL_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_COM_PM0_CONTROL_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_PM0_CONTROL_0_READ_MASK _MK_MASK_CONST(0xfffff3) +#define DC_COM_PM0_CONTROL_0_WRITE_MASK _MK_MASK_CONST(0xfffff3) +#define DC_COM_PM0_CONTROL_0_PM0_CLOCK_SELECT_SHIFT _MK_SHIFT_CONST(0) +#define DC_COM_PM0_CONTROL_0_PM0_CLOCK_SELECT_FIELD _MK_FIELD_CONST(0x3, DC_COM_PM0_CONTROL_0_PM0_CLOCK_SELECT_SHIFT) +#define DC_COM_PM0_CONTROL_0_PM0_CLOCK_SELECT_RANGE 1:0 +#define DC_COM_PM0_CONTROL_0_PM0_CLOCK_SELECT_WOFFSET 0x0 +#define DC_COM_PM0_CONTROL_0_PM0_CLOCK_SELECT_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PM0_CONTROL_0_PM0_CLOCK_SELECT_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_PM0_CONTROL_0_PM0_CLOCK_SELECT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PM0_CONTROL_0_PM0_CLOCK_SELECT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_COM_PM0_CONTROL_0_PM0_CLOCK_DIVIDER_SHIFT _MK_SHIFT_CONST(4) +#define DC_COM_PM0_CONTROL_0_PM0_CLOCK_DIVIDER_FIELD _MK_FIELD_CONST(0x3fff, DC_COM_PM0_CONTROL_0_PM0_CLOCK_DIVIDER_SHIFT) +#define DC_COM_PM0_CONTROL_0_PM0_CLOCK_DIVIDER_RANGE 17:4 +#define DC_COM_PM0_CONTROL_0_PM0_CLOCK_DIVIDER_WOFFSET 0x0 +#define DC_COM_PM0_CONTROL_0_PM0_CLOCK_DIVIDER_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PM0_CONTROL_0_PM0_CLOCK_DIVIDER_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_PM0_CONTROL_0_PM0_CLOCK_DIVIDER_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PM0_CONTROL_0_PM0_CLOCK_DIVIDER_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_COM_PM0_CONTROL_0_PM0_PERIOD_SHIFT _MK_SHIFT_CONST(18) +#define DC_COM_PM0_CONTROL_0_PM0_PERIOD_FIELD _MK_FIELD_CONST(0x3f, DC_COM_PM0_CONTROL_0_PM0_PERIOD_SHIFT) +#define DC_COM_PM0_CONTROL_0_PM0_PERIOD_RANGE 23:18 +#define DC_COM_PM0_CONTROL_0_PM0_PERIOD_WOFFSET 0x0 +#define DC_COM_PM0_CONTROL_0_PM0_PERIOD_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PM0_CONTROL_0_PM0_PERIOD_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_PM0_CONTROL_0_PM0_PERIOD_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PM0_CONTROL_0_PM0_PERIOD_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_COM_PM0_DUTY_CYCLE_0 +#define DC_COM_PM0_DUTY_CYCLE_0 _MK_ADDR_CONST(0x31d) +#define DC_COM_PM0_DUTY_CYCLE_0_SECURE 0x0 +#define DC_COM_PM0_DUTY_CYCLE_0_WORD_COUNT 0x1 +#define DC_COM_PM0_DUTY_CYCLE_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_COM_PM0_DUTY_CYCLE_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_COM_PM0_DUTY_CYCLE_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_COM_PM0_DUTY_CYCLE_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_PM0_DUTY_CYCLE_0_READ_MASK _MK_MASK_CONST(0x1ff) +#define DC_COM_PM0_DUTY_CYCLE_0_WRITE_MASK _MK_MASK_CONST(0x1ff) +#define DC_COM_PM0_DUTY_CYCLE_0_PM0_DUTY_CYCLE_SHIFT _MK_SHIFT_CONST(0) +#define DC_COM_PM0_DUTY_CYCLE_0_PM0_DUTY_CYCLE_FIELD _MK_FIELD_CONST(0x1ff, DC_COM_PM0_DUTY_CYCLE_0_PM0_DUTY_CYCLE_SHIFT) +#define DC_COM_PM0_DUTY_CYCLE_0_PM0_DUTY_CYCLE_RANGE 8:0 +#define DC_COM_PM0_DUTY_CYCLE_0_PM0_DUTY_CYCLE_WOFFSET 0x0 +#define DC_COM_PM0_DUTY_CYCLE_0_PM0_DUTY_CYCLE_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PM0_DUTY_CYCLE_0_PM0_DUTY_CYCLE_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_PM0_DUTY_CYCLE_0_PM0_DUTY_CYCLE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PM0_DUTY_CYCLE_0_PM0_DUTY_CYCLE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_COM_PM1_CONTROL_0 +#define DC_COM_PM1_CONTROL_0 _MK_ADDR_CONST(0x31e) +#define DC_COM_PM1_CONTROL_0_SECURE 0x0 +#define DC_COM_PM1_CONTROL_0_WORD_COUNT 0x1 +#define DC_COM_PM1_CONTROL_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_COM_PM1_CONTROL_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_COM_PM1_CONTROL_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_COM_PM1_CONTROL_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_PM1_CONTROL_0_READ_MASK _MK_MASK_CONST(0xfffff3) +#define DC_COM_PM1_CONTROL_0_WRITE_MASK _MK_MASK_CONST(0xfffff3) +#define DC_COM_PM1_CONTROL_0_PM1_CLOCK_SELECT_SHIFT _MK_SHIFT_CONST(0) +#define DC_COM_PM1_CONTROL_0_PM1_CLOCK_SELECT_FIELD _MK_FIELD_CONST(0x3, DC_COM_PM1_CONTROL_0_PM1_CLOCK_SELECT_SHIFT) +#define DC_COM_PM1_CONTROL_0_PM1_CLOCK_SELECT_RANGE 1:0 +#define DC_COM_PM1_CONTROL_0_PM1_CLOCK_SELECT_WOFFSET 0x0 +#define DC_COM_PM1_CONTROL_0_PM1_CLOCK_SELECT_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PM1_CONTROL_0_PM1_CLOCK_SELECT_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_PM1_CONTROL_0_PM1_CLOCK_SELECT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PM1_CONTROL_0_PM1_CLOCK_SELECT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_COM_PM1_CONTROL_0_PM1_CLOCK_DIVIDER_SHIFT _MK_SHIFT_CONST(4) +#define DC_COM_PM1_CONTROL_0_PM1_CLOCK_DIVIDER_FIELD _MK_FIELD_CONST(0x3fff, DC_COM_PM1_CONTROL_0_PM1_CLOCK_DIVIDER_SHIFT) +#define DC_COM_PM1_CONTROL_0_PM1_CLOCK_DIVIDER_RANGE 17:4 +#define DC_COM_PM1_CONTROL_0_PM1_CLOCK_DIVIDER_WOFFSET 0x0 +#define DC_COM_PM1_CONTROL_0_PM1_CLOCK_DIVIDER_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PM1_CONTROL_0_PM1_CLOCK_DIVIDER_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_PM1_CONTROL_0_PM1_CLOCK_DIVIDER_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PM1_CONTROL_0_PM1_CLOCK_DIVIDER_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_COM_PM1_CONTROL_0_PM1_PERIOD_SHIFT _MK_SHIFT_CONST(18) +#define DC_COM_PM1_CONTROL_0_PM1_PERIOD_FIELD _MK_FIELD_CONST(0x3f, DC_COM_PM1_CONTROL_0_PM1_PERIOD_SHIFT) +#define DC_COM_PM1_CONTROL_0_PM1_PERIOD_RANGE 23:18 +#define DC_COM_PM1_CONTROL_0_PM1_PERIOD_WOFFSET 0x0 +#define DC_COM_PM1_CONTROL_0_PM1_PERIOD_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PM1_CONTROL_0_PM1_PERIOD_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_PM1_CONTROL_0_PM1_PERIOD_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PM1_CONTROL_0_PM1_PERIOD_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_COM_PM1_DUTY_CYCLE_0 +#define DC_COM_PM1_DUTY_CYCLE_0 _MK_ADDR_CONST(0x31f) +#define DC_COM_PM1_DUTY_CYCLE_0_SECURE 0x0 +#define DC_COM_PM1_DUTY_CYCLE_0_WORD_COUNT 0x1 +#define DC_COM_PM1_DUTY_CYCLE_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_COM_PM1_DUTY_CYCLE_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_COM_PM1_DUTY_CYCLE_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_COM_PM1_DUTY_CYCLE_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_PM1_DUTY_CYCLE_0_READ_MASK _MK_MASK_CONST(0x1ff) +#define DC_COM_PM1_DUTY_CYCLE_0_WRITE_MASK _MK_MASK_CONST(0x1ff) +#define DC_COM_PM1_DUTY_CYCLE_0_PM1_DUTY_CYCLE_SHIFT _MK_SHIFT_CONST(0) +#define DC_COM_PM1_DUTY_CYCLE_0_PM1_DUTY_CYCLE_FIELD _MK_FIELD_CONST(0x1ff, DC_COM_PM1_DUTY_CYCLE_0_PM1_DUTY_CYCLE_SHIFT) +#define DC_COM_PM1_DUTY_CYCLE_0_PM1_DUTY_CYCLE_RANGE 8:0 +#define DC_COM_PM1_DUTY_CYCLE_0_PM1_DUTY_CYCLE_WOFFSET 0x0 +#define DC_COM_PM1_DUTY_CYCLE_0_PM1_DUTY_CYCLE_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PM1_DUTY_CYCLE_0_PM1_DUTY_CYCLE_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_PM1_DUTY_CYCLE_0_PM1_DUTY_CYCLE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_PM1_DUTY_CYCLE_0_PM1_DUTY_CYCLE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_COM_SPI_CONTROL_0 +#define DC_COM_SPI_CONTROL_0 _MK_ADDR_CONST(0x320) +#define DC_COM_SPI_CONTROL_0_SECURE 0x0 +#define DC_COM_SPI_CONTROL_0_WORD_COUNT 0x1 +#define DC_COM_SPI_CONTROL_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_COM_SPI_CONTROL_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_COM_SPI_CONTROL_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_COM_SPI_CONTROL_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_SPI_CONTROL_0_READ_MASK _MK_MASK_CONST(0x31f00fb) +#define DC_COM_SPI_CONTROL_0_WRITE_MASK _MK_MASK_CONST(0x31f00fb) +#define DC_COM_SPI_CONTROL_0_SPI_SERIAL_CLK_CONTROL_SHIFT _MK_SHIFT_CONST(0) +#define DC_COM_SPI_CONTROL_0_SPI_SERIAL_CLK_CONTROL_FIELD _MK_FIELD_CONST(0x3, DC_COM_SPI_CONTROL_0_SPI_SERIAL_CLK_CONTROL_SHIFT) +#define DC_COM_SPI_CONTROL_0_SPI_SERIAL_CLK_CONTROL_RANGE 1:0 +#define DC_COM_SPI_CONTROL_0_SPI_SERIAL_CLK_CONTROL_WOFFSET 0x0 +#define DC_COM_SPI_CONTROL_0_SPI_SERIAL_CLK_CONTROL_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_SPI_CONTROL_0_SPI_SERIAL_CLK_CONTROL_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_SPI_CONTROL_0_SPI_SERIAL_CLK_CONTROL_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_SPI_CONTROL_0_SPI_SERIAL_CLK_CONTROL_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_COM_SPI_CONTROL_0_SPI_DATA_DIRECTION_SHIFT _MK_SHIFT_CONST(3) +#define DC_COM_SPI_CONTROL_0_SPI_DATA_DIRECTION_FIELD _MK_FIELD_CONST(0x1, DC_COM_SPI_CONTROL_0_SPI_DATA_DIRECTION_SHIFT) +#define DC_COM_SPI_CONTROL_0_SPI_DATA_DIRECTION_RANGE 3:3 +#define DC_COM_SPI_CONTROL_0_SPI_DATA_DIRECTION_WOFFSET 0x0 +#define DC_COM_SPI_CONTROL_0_SPI_DATA_DIRECTION_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_SPI_CONTROL_0_SPI_DATA_DIRECTION_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_SPI_CONTROL_0_SPI_DATA_DIRECTION_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_SPI_CONTROL_0_SPI_DATA_DIRECTION_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_SPI_CONTROL_0_SPI_DATA_DIRECTION_MSB2LSB _MK_ENUM_CONST(0) +#define DC_COM_SPI_CONTROL_0_SPI_DATA_DIRECTION_LSB2MSB _MK_ENUM_CONST(1) + +#define DC_COM_SPI_CONTROL_0_SPI_BITS_PER_CYCLE_SHIFT _MK_SHIFT_CONST(4) +#define DC_COM_SPI_CONTROL_0_SPI_BITS_PER_CYCLE_FIELD _MK_FIELD_CONST(0xf, DC_COM_SPI_CONTROL_0_SPI_BITS_PER_CYCLE_SHIFT) +#define DC_COM_SPI_CONTROL_0_SPI_BITS_PER_CYCLE_RANGE 7:4 +#define DC_COM_SPI_CONTROL_0_SPI_BITS_PER_CYCLE_WOFFSET 0x0 +#define DC_COM_SPI_CONTROL_0_SPI_BITS_PER_CYCLE_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_SPI_CONTROL_0_SPI_BITS_PER_CYCLE_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_SPI_CONTROL_0_SPI_BITS_PER_CYCLE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_SPI_CONTROL_0_SPI_BITS_PER_CYCLE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_SPI_CONTROL_0_SPI_BITS_PER_CYCLE_SPI8 _MK_ENUM_CONST(0) +#define DC_COM_SPI_CONTROL_0_SPI_BITS_PER_CYCLE_SPI8DC _MK_ENUM_CONST(1) +#define DC_COM_SPI_CONTROL_0_SPI_BITS_PER_CYCLE_SPI12 _MK_ENUM_CONST(2) +#define DC_COM_SPI_CONTROL_0_SPI_BITS_PER_CYCLE_SPI16 _MK_ENUM_CONST(3) +#define DC_COM_SPI_CONTROL_0_SPI_BITS_PER_CYCLE_SPI16DC _MK_ENUM_CONST(4) +#define DC_COM_SPI_CONTROL_0_SPI_BITS_PER_CYCLE_SPI16SB _MK_ENUM_CONST(5) +#define DC_COM_SPI_CONTROL_0_SPI_BITS_PER_CYCLE_SPI18 _MK_ENUM_CONST(6) +#define DC_COM_SPI_CONTROL_0_SPI_BITS_PER_CYCLE_SPI24 _MK_ENUM_CONST(7) + +#define DC_COM_SPI_CONTROL_0_SPI_CLK_DIVIDER_SHIFT _MK_SHIFT_CONST(16) +#define DC_COM_SPI_CONTROL_0_SPI_CLK_DIVIDER_FIELD _MK_FIELD_CONST(0x1f, DC_COM_SPI_CONTROL_0_SPI_CLK_DIVIDER_SHIFT) +#define DC_COM_SPI_CONTROL_0_SPI_CLK_DIVIDER_RANGE 20:16 +#define DC_COM_SPI_CONTROL_0_SPI_CLK_DIVIDER_WOFFSET 0x0 +#define DC_COM_SPI_CONTROL_0_SPI_CLK_DIVIDER_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_SPI_CONTROL_0_SPI_CLK_DIVIDER_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_SPI_CONTROL_0_SPI_CLK_DIVIDER_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_SPI_CONTROL_0_SPI_CLK_DIVIDER_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_COM_SPI_CONTROL_0_SPI_STATUS_ENABLE_SHIFT _MK_SHIFT_CONST(24) +#define DC_COM_SPI_CONTROL_0_SPI_STATUS_ENABLE_FIELD _MK_FIELD_CONST(0x3, DC_COM_SPI_CONTROL_0_SPI_STATUS_ENABLE_SHIFT) +#define DC_COM_SPI_CONTROL_0_SPI_STATUS_ENABLE_RANGE 25:24 +#define DC_COM_SPI_CONTROL_0_SPI_STATUS_ENABLE_WOFFSET 0x0 +#define DC_COM_SPI_CONTROL_0_SPI_STATUS_ENABLE_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_SPI_CONTROL_0_SPI_STATUS_ENABLE_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_SPI_CONTROL_0_SPI_STATUS_ENABLE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_SPI_CONTROL_0_SPI_STATUS_ENABLE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_COM_SPI_START_BYTE_0 +#define DC_COM_SPI_START_BYTE_0 _MK_ADDR_CONST(0x321) +#define DC_COM_SPI_START_BYTE_0_SECURE 0x0 +#define DC_COM_SPI_START_BYTE_0_WORD_COUNT 0x1 +#define DC_COM_SPI_START_BYTE_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_COM_SPI_START_BYTE_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_COM_SPI_START_BYTE_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_COM_SPI_START_BYTE_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_SPI_START_BYTE_0_READ_MASK _MK_MASK_CONST(0xffff) +#define DC_COM_SPI_START_BYTE_0_WRITE_MASK _MK_MASK_CONST(0xffff) +#define DC_COM_SPI_START_BYTE_0_SPI_DATA_START_BYTE_SHIFT _MK_SHIFT_CONST(0) +#define DC_COM_SPI_START_BYTE_0_SPI_DATA_START_BYTE_FIELD _MK_FIELD_CONST(0xff, DC_COM_SPI_START_BYTE_0_SPI_DATA_START_BYTE_SHIFT) +#define DC_COM_SPI_START_BYTE_0_SPI_DATA_START_BYTE_RANGE 7:0 +#define DC_COM_SPI_START_BYTE_0_SPI_DATA_START_BYTE_WOFFSET 0x0 +#define DC_COM_SPI_START_BYTE_0_SPI_DATA_START_BYTE_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_SPI_START_BYTE_0_SPI_DATA_START_BYTE_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_SPI_START_BYTE_0_SPI_DATA_START_BYTE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_SPI_START_BYTE_0_SPI_DATA_START_BYTE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_COM_SPI_START_BYTE_0_SPI_COMMAND_START_BYTE_SHIFT _MK_SHIFT_CONST(8) +#define DC_COM_SPI_START_BYTE_0_SPI_COMMAND_START_BYTE_FIELD _MK_FIELD_CONST(0xff, DC_COM_SPI_START_BYTE_0_SPI_COMMAND_START_BYTE_SHIFT) +#define DC_COM_SPI_START_BYTE_0_SPI_COMMAND_START_BYTE_RANGE 15:8 +#define DC_COM_SPI_START_BYTE_0_SPI_COMMAND_START_BYTE_WOFFSET 0x0 +#define DC_COM_SPI_START_BYTE_0_SPI_COMMAND_START_BYTE_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_SPI_START_BYTE_0_SPI_COMMAND_START_BYTE_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_SPI_START_BYTE_0_SPI_COMMAND_START_BYTE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_SPI_START_BYTE_0_SPI_COMMAND_START_BYTE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_COM_HSPI_WRITE_DATA_AB_0 +#define DC_COM_HSPI_WRITE_DATA_AB_0 _MK_ADDR_CONST(0x322) +#define DC_COM_HSPI_WRITE_DATA_AB_0_SECURE 0x0 +#define DC_COM_HSPI_WRITE_DATA_AB_0_WORD_COUNT 0x1 +#define DC_COM_HSPI_WRITE_DATA_AB_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_COM_HSPI_WRITE_DATA_AB_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_COM_HSPI_WRITE_DATA_AB_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_COM_HSPI_WRITE_DATA_AB_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_HSPI_WRITE_DATA_AB_0_READ_MASK _MK_MASK_CONST(0xffffffff) +#define DC_COM_HSPI_WRITE_DATA_AB_0_WRITE_MASK _MK_MASK_CONST(0xffffffff) +#define DC_COM_HSPI_WRITE_DATA_AB_0_HSPI_WRITE_DATA_A_SHIFT _MK_SHIFT_CONST(0) +#define DC_COM_HSPI_WRITE_DATA_AB_0_HSPI_WRITE_DATA_A_FIELD _MK_FIELD_CONST(0xffff, DC_COM_HSPI_WRITE_DATA_AB_0_HSPI_WRITE_DATA_A_SHIFT) +#define DC_COM_HSPI_WRITE_DATA_AB_0_HSPI_WRITE_DATA_A_RANGE 15:0 +#define DC_COM_HSPI_WRITE_DATA_AB_0_HSPI_WRITE_DATA_A_WOFFSET 0x0 +#define DC_COM_HSPI_WRITE_DATA_AB_0_HSPI_WRITE_DATA_A_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_HSPI_WRITE_DATA_AB_0_HSPI_WRITE_DATA_A_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_HSPI_WRITE_DATA_AB_0_HSPI_WRITE_DATA_A_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_HSPI_WRITE_DATA_AB_0_HSPI_WRITE_DATA_A_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_COM_HSPI_WRITE_DATA_AB_0_HSPI_WRITE_DATA_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_COM_HSPI_WRITE_DATA_AB_0_HSPI_WRITE_DATA_B_FIELD _MK_FIELD_CONST(0xffff, DC_COM_HSPI_WRITE_DATA_AB_0_HSPI_WRITE_DATA_B_SHIFT) +#define DC_COM_HSPI_WRITE_DATA_AB_0_HSPI_WRITE_DATA_B_RANGE 31:16 +#define DC_COM_HSPI_WRITE_DATA_AB_0_HSPI_WRITE_DATA_B_WOFFSET 0x0 +#define DC_COM_HSPI_WRITE_DATA_AB_0_HSPI_WRITE_DATA_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_HSPI_WRITE_DATA_AB_0_HSPI_WRITE_DATA_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_HSPI_WRITE_DATA_AB_0_HSPI_WRITE_DATA_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_HSPI_WRITE_DATA_AB_0_HSPI_WRITE_DATA_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_COM_HSPI_WRITE_DATA_CD_0 +#define DC_COM_HSPI_WRITE_DATA_CD_0 _MK_ADDR_CONST(0x323) +#define DC_COM_HSPI_WRITE_DATA_CD_0_SECURE 0x0 +#define DC_COM_HSPI_WRITE_DATA_CD_0_WORD_COUNT 0x1 +#define DC_COM_HSPI_WRITE_DATA_CD_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_COM_HSPI_WRITE_DATA_CD_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_COM_HSPI_WRITE_DATA_CD_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_COM_HSPI_WRITE_DATA_CD_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_HSPI_WRITE_DATA_CD_0_READ_MASK _MK_MASK_CONST(0xffffffff) +#define DC_COM_HSPI_WRITE_DATA_CD_0_WRITE_MASK _MK_MASK_CONST(0xffffffff) +#define DC_COM_HSPI_WRITE_DATA_CD_0_HSPI_WRITE_DATA_C_SHIFT _MK_SHIFT_CONST(0) +#define DC_COM_HSPI_WRITE_DATA_CD_0_HSPI_WRITE_DATA_C_FIELD _MK_FIELD_CONST(0xffff, DC_COM_HSPI_WRITE_DATA_CD_0_HSPI_WRITE_DATA_C_SHIFT) +#define DC_COM_HSPI_WRITE_DATA_CD_0_HSPI_WRITE_DATA_C_RANGE 15:0 +#define DC_COM_HSPI_WRITE_DATA_CD_0_HSPI_WRITE_DATA_C_WOFFSET 0x0 +#define DC_COM_HSPI_WRITE_DATA_CD_0_HSPI_WRITE_DATA_C_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_HSPI_WRITE_DATA_CD_0_HSPI_WRITE_DATA_C_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_HSPI_WRITE_DATA_CD_0_HSPI_WRITE_DATA_C_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_HSPI_WRITE_DATA_CD_0_HSPI_WRITE_DATA_C_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_COM_HSPI_WRITE_DATA_CD_0_HSPI_WRITE_DATA_D_SHIFT _MK_SHIFT_CONST(16) +#define DC_COM_HSPI_WRITE_DATA_CD_0_HSPI_WRITE_DATA_D_FIELD _MK_FIELD_CONST(0xffff, DC_COM_HSPI_WRITE_DATA_CD_0_HSPI_WRITE_DATA_D_SHIFT) +#define DC_COM_HSPI_WRITE_DATA_CD_0_HSPI_WRITE_DATA_D_RANGE 31:16 +#define DC_COM_HSPI_WRITE_DATA_CD_0_HSPI_WRITE_DATA_D_WOFFSET 0x0 +#define DC_COM_HSPI_WRITE_DATA_CD_0_HSPI_WRITE_DATA_D_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_HSPI_WRITE_DATA_CD_0_HSPI_WRITE_DATA_D_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_HSPI_WRITE_DATA_CD_0_HSPI_WRITE_DATA_D_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_HSPI_WRITE_DATA_CD_0_HSPI_WRITE_DATA_D_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_COM_HSPI_CS_DC_0 +#define DC_COM_HSPI_CS_DC_0 _MK_ADDR_CONST(0x324) +#define DC_COM_HSPI_CS_DC_0_SECURE 0x0 +#define DC_COM_HSPI_CS_DC_0_WORD_COUNT 0x1 +#define DC_COM_HSPI_CS_DC_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_COM_HSPI_CS_DC_0_RESET_MASK _MK_MASK_CONST(0x1) +#define DC_COM_HSPI_CS_DC_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_COM_HSPI_CS_DC_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_HSPI_CS_DC_0_READ_MASK _MK_MASK_CONST(0x1f0ffff1) +#define DC_COM_HSPI_CS_DC_0_WRITE_MASK _MK_MASK_CONST(0x1f0ffff1) +#define DC_COM_HSPI_CS_DC_0_HSPI_RAISE_SHIFT _MK_SHIFT_CONST(0) +#define DC_COM_HSPI_CS_DC_0_HSPI_RAISE_FIELD _MK_FIELD_CONST(0x1, DC_COM_HSPI_CS_DC_0_HSPI_RAISE_SHIFT) +#define DC_COM_HSPI_CS_DC_0_HSPI_RAISE_RANGE 0:0 +#define DC_COM_HSPI_CS_DC_0_HSPI_RAISE_WOFFSET 0x0 +#define DC_COM_HSPI_CS_DC_0_HSPI_RAISE_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_HSPI_CS_DC_0_HSPI_RAISE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_COM_HSPI_CS_DC_0_HSPI_RAISE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_HSPI_CS_DC_0_HSPI_RAISE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_HSPI_CS_DC_0_HSPI_RAISE_DISABLE _MK_ENUM_CONST(0) +#define DC_COM_HSPI_CS_DC_0_HSPI_RAISE_ENABLE _MK_ENUM_CONST(1) + +#define DC_COM_HSPI_CS_DC_0_HSPI_DC_SHIFT _MK_SHIFT_CONST(4) +#define DC_COM_HSPI_CS_DC_0_HSPI_DC_FIELD _MK_FIELD_CONST(0xf, DC_COM_HSPI_CS_DC_0_HSPI_DC_SHIFT) +#define DC_COM_HSPI_CS_DC_0_HSPI_DC_RANGE 7:4 +#define DC_COM_HSPI_CS_DC_0_HSPI_DC_WOFFSET 0x0 +#define DC_COM_HSPI_CS_DC_0_HSPI_DC_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_HSPI_CS_DC_0_HSPI_DC_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_HSPI_CS_DC_0_HSPI_DC_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_HSPI_CS_DC_0_HSPI_DC_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_COM_HSPI_CS_DC_0_HSPI_MAIN_CS_SHIFT _MK_SHIFT_CONST(8) +#define DC_COM_HSPI_CS_DC_0_HSPI_MAIN_CS_FIELD _MK_FIELD_CONST(0xf, DC_COM_HSPI_CS_DC_0_HSPI_MAIN_CS_SHIFT) +#define DC_COM_HSPI_CS_DC_0_HSPI_MAIN_CS_RANGE 11:8 +#define DC_COM_HSPI_CS_DC_0_HSPI_MAIN_CS_WOFFSET 0x0 +#define DC_COM_HSPI_CS_DC_0_HSPI_MAIN_CS_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_HSPI_CS_DC_0_HSPI_MAIN_CS_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_HSPI_CS_DC_0_HSPI_MAIN_CS_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_HSPI_CS_DC_0_HSPI_MAIN_CS_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_COM_HSPI_CS_DC_0_HSPI_SUB_CS_SHIFT _MK_SHIFT_CONST(12) +#define DC_COM_HSPI_CS_DC_0_HSPI_SUB_CS_FIELD _MK_FIELD_CONST(0xf, DC_COM_HSPI_CS_DC_0_HSPI_SUB_CS_SHIFT) +#define DC_COM_HSPI_CS_DC_0_HSPI_SUB_CS_RANGE 15:12 +#define DC_COM_HSPI_CS_DC_0_HSPI_SUB_CS_WOFFSET 0x0 +#define DC_COM_HSPI_CS_DC_0_HSPI_SUB_CS_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_HSPI_CS_DC_0_HSPI_SUB_CS_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_HSPI_CS_DC_0_HSPI_SUB_CS_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_HSPI_CS_DC_0_HSPI_SUB_CS_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_COM_HSPI_CS_DC_0_HSPI_RAISE_CHANNEL_ID_SHIFT _MK_SHIFT_CONST(16) +#define DC_COM_HSPI_CS_DC_0_HSPI_RAISE_CHANNEL_ID_FIELD _MK_FIELD_CONST(0xf, DC_COM_HSPI_CS_DC_0_HSPI_RAISE_CHANNEL_ID_SHIFT) +#define DC_COM_HSPI_CS_DC_0_HSPI_RAISE_CHANNEL_ID_RANGE 19:16 +#define DC_COM_HSPI_CS_DC_0_HSPI_RAISE_CHANNEL_ID_WOFFSET 0x0 +#define DC_COM_HSPI_CS_DC_0_HSPI_RAISE_CHANNEL_ID_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_HSPI_CS_DC_0_HSPI_RAISE_CHANNEL_ID_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_HSPI_CS_DC_0_HSPI_RAISE_CHANNEL_ID_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_HSPI_CS_DC_0_HSPI_RAISE_CHANNEL_ID_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_COM_HSPI_CS_DC_0_HSPI_RAISE_VECTOR_SHIFT _MK_SHIFT_CONST(24) +#define DC_COM_HSPI_CS_DC_0_HSPI_RAISE_VECTOR_FIELD _MK_FIELD_CONST(0x1f, DC_COM_HSPI_CS_DC_0_HSPI_RAISE_VECTOR_SHIFT) +#define DC_COM_HSPI_CS_DC_0_HSPI_RAISE_VECTOR_RANGE 28:24 +#define DC_COM_HSPI_CS_DC_0_HSPI_RAISE_VECTOR_WOFFSET 0x0 +#define DC_COM_HSPI_CS_DC_0_HSPI_RAISE_VECTOR_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_HSPI_CS_DC_0_HSPI_RAISE_VECTOR_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_HSPI_CS_DC_0_HSPI_RAISE_VECTOR_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_HSPI_CS_DC_0_HSPI_RAISE_VECTOR_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_COM_SCRATCH_REGISTER_A_0 +#define DC_COM_SCRATCH_REGISTER_A_0 _MK_ADDR_CONST(0x325) +#define DC_COM_SCRATCH_REGISTER_A_0_SECURE 0x0 +#define DC_COM_SCRATCH_REGISTER_A_0_WORD_COUNT 0x1 +#define DC_COM_SCRATCH_REGISTER_A_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_COM_SCRATCH_REGISTER_A_0_RESET_MASK _MK_MASK_CONST(0xffffffff) +#define DC_COM_SCRATCH_REGISTER_A_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_COM_SCRATCH_REGISTER_A_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_SCRATCH_REGISTER_A_0_READ_MASK _MK_MASK_CONST(0xffffffff) +#define DC_COM_SCRATCH_REGISTER_A_0_WRITE_MASK _MK_MASK_CONST(0xffffffff) +#define DC_COM_SCRATCH_REGISTER_A_0_SCRATCH_REGISTER_A_SHIFT _MK_SHIFT_CONST(0) +#define DC_COM_SCRATCH_REGISTER_A_0_SCRATCH_REGISTER_A_FIELD _MK_FIELD_CONST(0xffffffff, DC_COM_SCRATCH_REGISTER_A_0_SCRATCH_REGISTER_A_SHIFT) +#define DC_COM_SCRATCH_REGISTER_A_0_SCRATCH_REGISTER_A_RANGE 31:0 +#define DC_COM_SCRATCH_REGISTER_A_0_SCRATCH_REGISTER_A_WOFFSET 0x0 +#define DC_COM_SCRATCH_REGISTER_A_0_SCRATCH_REGISTER_A_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_SCRATCH_REGISTER_A_0_SCRATCH_REGISTER_A_DEFAULT_MASK _MK_MASK_CONST(0xffffffff) +#define DC_COM_SCRATCH_REGISTER_A_0_SCRATCH_REGISTER_A_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_SCRATCH_REGISTER_A_0_SCRATCH_REGISTER_A_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_COM_SCRATCH_REGISTER_B_0 +#define DC_COM_SCRATCH_REGISTER_B_0 _MK_ADDR_CONST(0x326) +#define DC_COM_SCRATCH_REGISTER_B_0_SECURE 0x0 +#define DC_COM_SCRATCH_REGISTER_B_0_WORD_COUNT 0x1 +#define DC_COM_SCRATCH_REGISTER_B_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_COM_SCRATCH_REGISTER_B_0_RESET_MASK _MK_MASK_CONST(0xffffffff) +#define DC_COM_SCRATCH_REGISTER_B_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_COM_SCRATCH_REGISTER_B_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_SCRATCH_REGISTER_B_0_READ_MASK _MK_MASK_CONST(0xffffffff) +#define DC_COM_SCRATCH_REGISTER_B_0_WRITE_MASK _MK_MASK_CONST(0xffffffff) +#define DC_COM_SCRATCH_REGISTER_B_0_SCRATCH_REGISTER_B_SHIFT _MK_SHIFT_CONST(0) +#define DC_COM_SCRATCH_REGISTER_B_0_SCRATCH_REGISTER_B_FIELD _MK_FIELD_CONST(0xffffffff, DC_COM_SCRATCH_REGISTER_B_0_SCRATCH_REGISTER_B_SHIFT) +#define DC_COM_SCRATCH_REGISTER_B_0_SCRATCH_REGISTER_B_RANGE 31:0 +#define DC_COM_SCRATCH_REGISTER_B_0_SCRATCH_REGISTER_B_WOFFSET 0x0 +#define DC_COM_SCRATCH_REGISTER_B_0_SCRATCH_REGISTER_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_SCRATCH_REGISTER_B_0_SCRATCH_REGISTER_B_DEFAULT_MASK _MK_MASK_CONST(0xffffffff) +#define DC_COM_SCRATCH_REGISTER_B_0_SCRATCH_REGISTER_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_SCRATCH_REGISTER_B_0_SCRATCH_REGISTER_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Reserved address 807 [0x327] + +// Reserved address 808 [0x328] + +// Register DC_COM_CRC_CHECKSUM_LATCHED_0 +#define DC_COM_CRC_CHECKSUM_LATCHED_0 _MK_ADDR_CONST(0x329) +#define DC_COM_CRC_CHECKSUM_LATCHED_0_SECURE 0x0 +#define DC_COM_CRC_CHECKSUM_LATCHED_0_WORD_COUNT 0x1 +#define DC_COM_CRC_CHECKSUM_LATCHED_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_COM_CRC_CHECKSUM_LATCHED_0_RESET_MASK _MK_MASK_CONST(0xffffffff) +#define DC_COM_CRC_CHECKSUM_LATCHED_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_COM_CRC_CHECKSUM_LATCHED_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_CRC_CHECKSUM_LATCHED_0_READ_MASK _MK_MASK_CONST(0xffffffff) +#define DC_COM_CRC_CHECKSUM_LATCHED_0_WRITE_MASK _MK_MASK_CONST(0x0) +#define DC_COM_CRC_CHECKSUM_LATCHED_0_CRC_CHECKSUM_LATCHED_SHIFT _MK_SHIFT_CONST(0) +#define DC_COM_CRC_CHECKSUM_LATCHED_0_CRC_CHECKSUM_LATCHED_FIELD _MK_FIELD_CONST(0xffffffff, DC_COM_CRC_CHECKSUM_LATCHED_0_CRC_CHECKSUM_LATCHED_SHIFT) +#define DC_COM_CRC_CHECKSUM_LATCHED_0_CRC_CHECKSUM_LATCHED_RANGE 31:0 +#define DC_COM_CRC_CHECKSUM_LATCHED_0_CRC_CHECKSUM_LATCHED_WOFFSET 0x0 +#define DC_COM_CRC_CHECKSUM_LATCHED_0_CRC_CHECKSUM_LATCHED_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_CRC_CHECKSUM_LATCHED_0_CRC_CHECKSUM_LATCHED_DEFAULT_MASK _MK_MASK_CONST(0xffffffff) +#define DC_COM_CRC_CHECKSUM_LATCHED_0_CRC_CHECKSUM_LATCHED_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_CRC_CHECKSUM_LATCHED_0_CRC_CHECKSUM_LATCHED_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Packet CMU_PIXEL_IN +#define CMU_PIXEL_IN_SIZE 24 + +#define CMU_PIXEL_IN_RED_SHIFT _MK_SHIFT_CONST(0) +#define CMU_PIXEL_IN_RED_FIELD _MK_FIELD_CONST(0xff, CMU_PIXEL_IN_RED_SHIFT) +#define CMU_PIXEL_IN_RED_RANGE _MK_SHIFT_CONST(7):_MK_SHIFT_CONST(0) +#define CMU_PIXEL_IN_RED_ROW 0 + +#define CMU_PIXEL_IN_GRN_SHIFT _MK_SHIFT_CONST(8) +#define CMU_PIXEL_IN_GRN_FIELD _MK_FIELD_CONST(0xff, CMU_PIXEL_IN_GRN_SHIFT) +#define CMU_PIXEL_IN_GRN_RANGE _MK_SHIFT_CONST(15):_MK_SHIFT_CONST(8) +#define CMU_PIXEL_IN_GRN_ROW 0 + +#define CMU_PIXEL_IN_BLU_SHIFT _MK_SHIFT_CONST(16) +#define CMU_PIXEL_IN_BLU_FIELD _MK_FIELD_CONST(0xff, CMU_PIXEL_IN_BLU_SHIFT) +#define CMU_PIXEL_IN_BLU_RANGE _MK_SHIFT_CONST(23):_MK_SHIFT_CONST(16) +#define CMU_PIXEL_IN_BLU_ROW 0 + + +// Packet CMU_LUT1_PIXEL_OUT +#define CMU_LUT1_PIXEL_OUT_SIZE 36 + +#define CMU_LUT1_PIXEL_OUT_RED_SHIFT _MK_SHIFT_CONST(0) +#define CMU_LUT1_PIXEL_OUT_RED_FIELD _MK_FIELD_CONST(0xfff, CMU_LUT1_PIXEL_OUT_RED_SHIFT) +#define CMU_LUT1_PIXEL_OUT_RED_RANGE _MK_SHIFT_CONST(11):_MK_SHIFT_CONST(0) +#define CMU_LUT1_PIXEL_OUT_RED_ROW 0 + +#define CMU_LUT1_PIXEL_OUT_GRN_SHIFT _MK_SHIFT_CONST(12) +#define CMU_LUT1_PIXEL_OUT_GRN_FIELD _MK_FIELD_CONST(0xfff, CMU_LUT1_PIXEL_OUT_GRN_SHIFT) +#define CMU_LUT1_PIXEL_OUT_GRN_RANGE _MK_SHIFT_CONST(23):_MK_SHIFT_CONST(12) +#define CMU_LUT1_PIXEL_OUT_GRN_ROW 0 + +#define CMU_LUT1_PIXEL_OUT_BLU_SHIFT _MK_SHIFT_CONST(24) +#define CMU_LUT1_PIXEL_OUT_BLU_FIELD _MK_FIELD_CONST(0xfff, CMU_LUT1_PIXEL_OUT_BLU_SHIFT) +#define CMU_LUT1_PIXEL_OUT_BLU_RANGE _MK_SHIFT_CONST(35):_MK_SHIFT_CONST(24) +#define CMU_LUT1_PIXEL_OUT_BLU_ROW 0 + + +// Register DC_COM_CMU_CSC_KRR_0 +#define DC_COM_CMU_CSC_KRR_0 _MK_ADDR_CONST(0x32a) +#define DC_COM_CMU_CSC_KRR_0_SECURE 0x0 +#define DC_COM_CMU_CSC_KRR_0_WORD_COUNT 0x1 +#define DC_COM_CMU_CSC_KRR_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_COM_CMU_CSC_KRR_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_COM_CMU_CSC_KRR_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_COM_CMU_CSC_KRR_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_CMU_CSC_KRR_0_READ_MASK _MK_MASK_CONST(0x3ff) +#define DC_COM_CMU_CSC_KRR_0_WRITE_MASK _MK_MASK_CONST(0x3ff) +#define DC_COM_CMU_CSC_KRR_0_KRR_SHIFT _MK_SHIFT_CONST(0) +#define DC_COM_CMU_CSC_KRR_0_KRR_FIELD _MK_FIELD_CONST(0x3ff, DC_COM_CMU_CSC_KRR_0_KRR_SHIFT) +#define DC_COM_CMU_CSC_KRR_0_KRR_RANGE 9:0 +#define DC_COM_CMU_CSC_KRR_0_KRR_WOFFSET 0x0 +#define DC_COM_CMU_CSC_KRR_0_KRR_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_CMU_CSC_KRR_0_KRR_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_CMU_CSC_KRR_0_KRR_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_CMU_CSC_KRR_0_KRR_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_COM_CMU_CSC_KGR_0 +#define DC_COM_CMU_CSC_KGR_0 _MK_ADDR_CONST(0x32b) +#define DC_COM_CMU_CSC_KGR_0_SECURE 0x0 +#define DC_COM_CMU_CSC_KGR_0_WORD_COUNT 0x1 +#define DC_COM_CMU_CSC_KGR_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_COM_CMU_CSC_KGR_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_COM_CMU_CSC_KGR_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_COM_CMU_CSC_KGR_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_CMU_CSC_KGR_0_READ_MASK _MK_MASK_CONST(0x3ff) +#define DC_COM_CMU_CSC_KGR_0_WRITE_MASK _MK_MASK_CONST(0x3ff) +#define DC_COM_CMU_CSC_KGR_0_KGR_SHIFT _MK_SHIFT_CONST(0) +#define DC_COM_CMU_CSC_KGR_0_KGR_FIELD _MK_FIELD_CONST(0x3ff, DC_COM_CMU_CSC_KGR_0_KGR_SHIFT) +#define DC_COM_CMU_CSC_KGR_0_KGR_RANGE 9:0 +#define DC_COM_CMU_CSC_KGR_0_KGR_WOFFSET 0x0 +#define DC_COM_CMU_CSC_KGR_0_KGR_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_CMU_CSC_KGR_0_KGR_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_CMU_CSC_KGR_0_KGR_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_CMU_CSC_KGR_0_KGR_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_COM_CMU_CSC_KBR_0 +#define DC_COM_CMU_CSC_KBR_0 _MK_ADDR_CONST(0x32c) +#define DC_COM_CMU_CSC_KBR_0_SECURE 0x0 +#define DC_COM_CMU_CSC_KBR_0_WORD_COUNT 0x1 +#define DC_COM_CMU_CSC_KBR_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_COM_CMU_CSC_KBR_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_COM_CMU_CSC_KBR_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_COM_CMU_CSC_KBR_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_CMU_CSC_KBR_0_READ_MASK _MK_MASK_CONST(0x3ff) +#define DC_COM_CMU_CSC_KBR_0_WRITE_MASK _MK_MASK_CONST(0x3ff) +#define DC_COM_CMU_CSC_KBR_0_KBR_SHIFT _MK_SHIFT_CONST(0) +#define DC_COM_CMU_CSC_KBR_0_KBR_FIELD _MK_FIELD_CONST(0x3ff, DC_COM_CMU_CSC_KBR_0_KBR_SHIFT) +#define DC_COM_CMU_CSC_KBR_0_KBR_RANGE 9:0 +#define DC_COM_CMU_CSC_KBR_0_KBR_WOFFSET 0x0 +#define DC_COM_CMU_CSC_KBR_0_KBR_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_CMU_CSC_KBR_0_KBR_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_CMU_CSC_KBR_0_KBR_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_CMU_CSC_KBR_0_KBR_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_COM_CMU_CSC_KRG_0 +#define DC_COM_CMU_CSC_KRG_0 _MK_ADDR_CONST(0x32d) +#define DC_COM_CMU_CSC_KRG_0_SECURE 0x0 +#define DC_COM_CMU_CSC_KRG_0_WORD_COUNT 0x1 +#define DC_COM_CMU_CSC_KRG_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_COM_CMU_CSC_KRG_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_COM_CMU_CSC_KRG_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_COM_CMU_CSC_KRG_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_CMU_CSC_KRG_0_READ_MASK _MK_MASK_CONST(0x3ff) +#define DC_COM_CMU_CSC_KRG_0_WRITE_MASK _MK_MASK_CONST(0x3ff) +#define DC_COM_CMU_CSC_KRG_0_KRG_SHIFT _MK_SHIFT_CONST(0) +#define DC_COM_CMU_CSC_KRG_0_KRG_FIELD _MK_FIELD_CONST(0x3ff, DC_COM_CMU_CSC_KRG_0_KRG_SHIFT) +#define DC_COM_CMU_CSC_KRG_0_KRG_RANGE 9:0 +#define DC_COM_CMU_CSC_KRG_0_KRG_WOFFSET 0x0 +#define DC_COM_CMU_CSC_KRG_0_KRG_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_CMU_CSC_KRG_0_KRG_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_CMU_CSC_KRG_0_KRG_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_CMU_CSC_KRG_0_KRG_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_COM_CMU_CSC_KGG_0 +#define DC_COM_CMU_CSC_KGG_0 _MK_ADDR_CONST(0x32e) +#define DC_COM_CMU_CSC_KGG_0_SECURE 0x0 +#define DC_COM_CMU_CSC_KGG_0_WORD_COUNT 0x1 +#define DC_COM_CMU_CSC_KGG_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_COM_CMU_CSC_KGG_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_COM_CMU_CSC_KGG_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_COM_CMU_CSC_KGG_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_CMU_CSC_KGG_0_READ_MASK _MK_MASK_CONST(0x3ff) +#define DC_COM_CMU_CSC_KGG_0_WRITE_MASK _MK_MASK_CONST(0x3ff) +#define DC_COM_CMU_CSC_KGG_0_KGG_SHIFT _MK_SHIFT_CONST(0) +#define DC_COM_CMU_CSC_KGG_0_KGG_FIELD _MK_FIELD_CONST(0x3ff, DC_COM_CMU_CSC_KGG_0_KGG_SHIFT) +#define DC_COM_CMU_CSC_KGG_0_KGG_RANGE 9:0 +#define DC_COM_CMU_CSC_KGG_0_KGG_WOFFSET 0x0 +#define DC_COM_CMU_CSC_KGG_0_KGG_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_CMU_CSC_KGG_0_KGG_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_CMU_CSC_KGG_0_KGG_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_CMU_CSC_KGG_0_KGG_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_COM_CMU_CSC_KBG_0 +#define DC_COM_CMU_CSC_KBG_0 _MK_ADDR_CONST(0x32f) +#define DC_COM_CMU_CSC_KBG_0_SECURE 0x0 +#define DC_COM_CMU_CSC_KBG_0_WORD_COUNT 0x1 +#define DC_COM_CMU_CSC_KBG_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_COM_CMU_CSC_KBG_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_COM_CMU_CSC_KBG_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_COM_CMU_CSC_KBG_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_CMU_CSC_KBG_0_READ_MASK _MK_MASK_CONST(0x3ff) +#define DC_COM_CMU_CSC_KBG_0_WRITE_MASK _MK_MASK_CONST(0x3ff) +#define DC_COM_CMU_CSC_KBG_0_KBG_SHIFT _MK_SHIFT_CONST(0) +#define DC_COM_CMU_CSC_KBG_0_KBG_FIELD _MK_FIELD_CONST(0x3ff, DC_COM_CMU_CSC_KBG_0_KBG_SHIFT) +#define DC_COM_CMU_CSC_KBG_0_KBG_RANGE 9:0 +#define DC_COM_CMU_CSC_KBG_0_KBG_WOFFSET 0x0 +#define DC_COM_CMU_CSC_KBG_0_KBG_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_CMU_CSC_KBG_0_KBG_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_CMU_CSC_KBG_0_KBG_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_CMU_CSC_KBG_0_KBG_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_COM_CMU_CSC_KRB_0 +#define DC_COM_CMU_CSC_KRB_0 _MK_ADDR_CONST(0x330) +#define DC_COM_CMU_CSC_KRB_0_SECURE 0x0 +#define DC_COM_CMU_CSC_KRB_0_WORD_COUNT 0x1 +#define DC_COM_CMU_CSC_KRB_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_COM_CMU_CSC_KRB_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_COM_CMU_CSC_KRB_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_COM_CMU_CSC_KRB_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_CMU_CSC_KRB_0_READ_MASK _MK_MASK_CONST(0x3ff) +#define DC_COM_CMU_CSC_KRB_0_WRITE_MASK _MK_MASK_CONST(0x3ff) +#define DC_COM_CMU_CSC_KRB_0_KRB_SHIFT _MK_SHIFT_CONST(0) +#define DC_COM_CMU_CSC_KRB_0_KRB_FIELD _MK_FIELD_CONST(0x3ff, DC_COM_CMU_CSC_KRB_0_KRB_SHIFT) +#define DC_COM_CMU_CSC_KRB_0_KRB_RANGE 9:0 +#define DC_COM_CMU_CSC_KRB_0_KRB_WOFFSET 0x0 +#define DC_COM_CMU_CSC_KRB_0_KRB_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_CMU_CSC_KRB_0_KRB_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_CMU_CSC_KRB_0_KRB_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_CMU_CSC_KRB_0_KRB_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_COM_CMU_CSC_KGB_0 +#define DC_COM_CMU_CSC_KGB_0 _MK_ADDR_CONST(0x331) +#define DC_COM_CMU_CSC_KGB_0_SECURE 0x0 +#define DC_COM_CMU_CSC_KGB_0_WORD_COUNT 0x1 +#define DC_COM_CMU_CSC_KGB_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_COM_CMU_CSC_KGB_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_COM_CMU_CSC_KGB_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_COM_CMU_CSC_KGB_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_CMU_CSC_KGB_0_READ_MASK _MK_MASK_CONST(0x3ff) +#define DC_COM_CMU_CSC_KGB_0_WRITE_MASK _MK_MASK_CONST(0x3ff) +#define DC_COM_CMU_CSC_KGB_0_KGB_SHIFT _MK_SHIFT_CONST(0) +#define DC_COM_CMU_CSC_KGB_0_KGB_FIELD _MK_FIELD_CONST(0x3ff, DC_COM_CMU_CSC_KGB_0_KGB_SHIFT) +#define DC_COM_CMU_CSC_KGB_0_KGB_RANGE 9:0 +#define DC_COM_CMU_CSC_KGB_0_KGB_WOFFSET 0x0 +#define DC_COM_CMU_CSC_KGB_0_KGB_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_CMU_CSC_KGB_0_KGB_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_CMU_CSC_KGB_0_KGB_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_CMU_CSC_KGB_0_KGB_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_COM_CMU_CSC_KBB_0 +#define DC_COM_CMU_CSC_KBB_0 _MK_ADDR_CONST(0x332) +#define DC_COM_CMU_CSC_KBB_0_SECURE 0x0 +#define DC_COM_CMU_CSC_KBB_0_WORD_COUNT 0x1 +#define DC_COM_CMU_CSC_KBB_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_COM_CMU_CSC_KBB_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_COM_CMU_CSC_KBB_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_COM_CMU_CSC_KBB_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_CMU_CSC_KBB_0_READ_MASK _MK_MASK_CONST(0x3ff) +#define DC_COM_CMU_CSC_KBB_0_WRITE_MASK _MK_MASK_CONST(0x3ff) +#define DC_COM_CMU_CSC_KBB_0_KBB_SHIFT _MK_SHIFT_CONST(0) +#define DC_COM_CMU_CSC_KBB_0_KBB_FIELD _MK_FIELD_CONST(0x3ff, DC_COM_CMU_CSC_KBB_0_KBB_SHIFT) +#define DC_COM_CMU_CSC_KBB_0_KBB_RANGE 9:0 +#define DC_COM_CMU_CSC_KBB_0_KBB_WOFFSET 0x0 +#define DC_COM_CMU_CSC_KBB_0_KBB_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_CMU_CSC_KBB_0_KBB_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_CMU_CSC_KBB_0_KBB_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_CMU_CSC_KBB_0_KBB_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_COM_CMU_LUT_MASK_0 +#define DC_COM_CMU_LUT_MASK_0 _MK_ADDR_CONST(0x333) +#define DC_COM_CMU_LUT_MASK_0_SECURE 0x0 +#define DC_COM_CMU_LUT_MASK_0_WORD_COUNT 0x1 +#define DC_COM_CMU_LUT_MASK_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_COM_CMU_LUT_MASK_0_RESET_MASK _MK_MASK_CONST(0x303) +#define DC_COM_CMU_LUT_MASK_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_COM_CMU_LUT_MASK_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_CMU_LUT_MASK_0_READ_MASK _MK_MASK_CONST(0x303) +#define DC_COM_CMU_LUT_MASK_0_WRITE_MASK _MK_MASK_CONST(0x303) +#define DC_COM_CMU_LUT_MASK_0_LUT1_WR_MASK_SHIFT _MK_SHIFT_CONST(0) +#define DC_COM_CMU_LUT_MASK_0_LUT1_WR_MASK_FIELD _MK_FIELD_CONST(0x3, DC_COM_CMU_LUT_MASK_0_LUT1_WR_MASK_SHIFT) +#define DC_COM_CMU_LUT_MASK_0_LUT1_WR_MASK_RANGE 1:0 +#define DC_COM_CMU_LUT_MASK_0_LUT1_WR_MASK_WOFFSET 0x0 +#define DC_COM_CMU_LUT_MASK_0_LUT1_WR_MASK_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_CMU_LUT_MASK_0_LUT1_WR_MASK_DEFAULT_MASK _MK_MASK_CONST(0x3) +#define DC_COM_CMU_LUT_MASK_0_LUT1_WR_MASK_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_CMU_LUT_MASK_0_LUT1_WR_MASK_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_CMU_LUT_MASK_0_LUT1_WR_MASK_ALL _MK_ENUM_CONST(0) +#define DC_COM_CMU_LUT_MASK_0_LUT1_WR_MASK_RED _MK_ENUM_CONST(1) +#define DC_COM_CMU_LUT_MASK_0_LUT1_WR_MASK_GREEN _MK_ENUM_CONST(2) +#define DC_COM_CMU_LUT_MASK_0_LUT1_WR_MASK_BLUE _MK_ENUM_CONST(3) + +#define DC_COM_CMU_LUT_MASK_0_LUT2_WR_MASK_SHIFT _MK_SHIFT_CONST(8) +#define DC_COM_CMU_LUT_MASK_0_LUT2_WR_MASK_FIELD _MK_FIELD_CONST(0x3, DC_COM_CMU_LUT_MASK_0_LUT2_WR_MASK_SHIFT) +#define DC_COM_CMU_LUT_MASK_0_LUT2_WR_MASK_RANGE 9:8 +#define DC_COM_CMU_LUT_MASK_0_LUT2_WR_MASK_WOFFSET 0x0 +#define DC_COM_CMU_LUT_MASK_0_LUT2_WR_MASK_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_CMU_LUT_MASK_0_LUT2_WR_MASK_DEFAULT_MASK _MK_MASK_CONST(0x3) +#define DC_COM_CMU_LUT_MASK_0_LUT2_WR_MASK_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_CMU_LUT_MASK_0_LUT2_WR_MASK_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_CMU_LUT_MASK_0_LUT2_WR_MASK_ALL _MK_ENUM_CONST(0) +#define DC_COM_CMU_LUT_MASK_0_LUT2_WR_MASK_RED _MK_ENUM_CONST(1) +#define DC_COM_CMU_LUT_MASK_0_LUT2_WR_MASK_GREEN _MK_ENUM_CONST(2) +#define DC_COM_CMU_LUT_MASK_0_LUT2_WR_MASK_BLUE _MK_ENUM_CONST(3) + + +// Reserved address 820 [0x334] + +// Reserved address 821 [0x335] + +// Register DC_COM_CMU_LUT1_0 +#define DC_COM_CMU_LUT1_0 _MK_ADDR_CONST(0x336) +#define DC_COM_CMU_LUT1_0_SECURE 0x0 +#define DC_COM_CMU_LUT1_0_WORD_COUNT 0x1 +#define DC_COM_CMU_LUT1_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_COM_CMU_LUT1_0_RESET_MASK _MK_MASK_CONST(0xff) +#define DC_COM_CMU_LUT1_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_COM_CMU_LUT1_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_CMU_LUT1_0_READ_MASK _MK_MASK_CONST(0xfff00ff) +#define DC_COM_CMU_LUT1_0_WRITE_MASK _MK_MASK_CONST(0xfff00ff) +#define DC_COM_CMU_LUT1_0_LUT1_ADDR_SHIFT _MK_SHIFT_CONST(0) +#define DC_COM_CMU_LUT1_0_LUT1_ADDR_FIELD _MK_FIELD_CONST(0xff, DC_COM_CMU_LUT1_0_LUT1_ADDR_SHIFT) +#define DC_COM_CMU_LUT1_0_LUT1_ADDR_RANGE 7:0 +#define DC_COM_CMU_LUT1_0_LUT1_ADDR_WOFFSET 0x0 +#define DC_COM_CMU_LUT1_0_LUT1_ADDR_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_CMU_LUT1_0_LUT1_ADDR_DEFAULT_MASK _MK_MASK_CONST(0xff) +#define DC_COM_CMU_LUT1_0_LUT1_ADDR_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_CMU_LUT1_0_LUT1_ADDR_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_COM_CMU_LUT1_0_LUT1_DATA_SHIFT _MK_SHIFT_CONST(16) +#define DC_COM_CMU_LUT1_0_LUT1_DATA_FIELD _MK_FIELD_CONST(0xfff, DC_COM_CMU_LUT1_0_LUT1_DATA_SHIFT) +#define DC_COM_CMU_LUT1_0_LUT1_DATA_RANGE 27:16 +#define DC_COM_CMU_LUT1_0_LUT1_DATA_WOFFSET 0x0 +#define DC_COM_CMU_LUT1_0_LUT1_DATA_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_CMU_LUT1_0_LUT1_DATA_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_CMU_LUT1_0_LUT1_DATA_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_CMU_LUT1_0_LUT1_DATA_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_COM_CMU_LUT2_0 +#define DC_COM_CMU_LUT2_0 _MK_ADDR_CONST(0x337) +#define DC_COM_CMU_LUT2_0_SECURE 0x0 +#define DC_COM_CMU_LUT2_0_WORD_COUNT 0x1 +#define DC_COM_CMU_LUT2_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_COM_CMU_LUT2_0_RESET_MASK _MK_MASK_CONST(0x3ff) +#define DC_COM_CMU_LUT2_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_COM_CMU_LUT2_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_CMU_LUT2_0_READ_MASK _MK_MASK_CONST(0xff03ff) +#define DC_COM_CMU_LUT2_0_WRITE_MASK _MK_MASK_CONST(0xff03ff) +#define DC_COM_CMU_LUT2_0_LUT2_ADDR_SHIFT _MK_SHIFT_CONST(0) +#define DC_COM_CMU_LUT2_0_LUT2_ADDR_FIELD _MK_FIELD_CONST(0x3ff, DC_COM_CMU_LUT2_0_LUT2_ADDR_SHIFT) +#define DC_COM_CMU_LUT2_0_LUT2_ADDR_RANGE 9:0 +#define DC_COM_CMU_LUT2_0_LUT2_ADDR_WOFFSET 0x0 +#define DC_COM_CMU_LUT2_0_LUT2_ADDR_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_CMU_LUT2_0_LUT2_ADDR_DEFAULT_MASK _MK_MASK_CONST(0x3ff) +#define DC_COM_CMU_LUT2_0_LUT2_ADDR_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_CMU_LUT2_0_LUT2_ADDR_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_COM_CMU_LUT2_0_LUT2_DATA_SHIFT _MK_SHIFT_CONST(16) +#define DC_COM_CMU_LUT2_0_LUT2_DATA_FIELD _MK_FIELD_CONST(0xff, DC_COM_CMU_LUT2_0_LUT2_DATA_SHIFT) +#define DC_COM_CMU_LUT2_0_LUT2_DATA_RANGE 23:16 +#define DC_COM_CMU_LUT2_0_LUT2_DATA_WOFFSET 0x0 +#define DC_COM_CMU_LUT2_0_LUT2_DATA_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_CMU_LUT2_0_LUT2_DATA_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_CMU_LUT2_0_LUT2_DATA_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_CMU_LUT2_0_LUT2_DATA_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_COM_CMU_LUT1_READ_0 +#define DC_COM_CMU_LUT1_READ_0 _MK_ADDR_CONST(0x338) +#define DC_COM_CMU_LUT1_READ_0_SECURE 0x0 +#define DC_COM_CMU_LUT1_READ_0_WORD_COUNT 0x1 +#define DC_COM_CMU_LUT1_READ_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_COM_CMU_LUT1_READ_0_RESET_MASK _MK_MASK_CONST(0x31) +#define DC_COM_CMU_LUT1_READ_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_COM_CMU_LUT1_READ_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_CMU_LUT1_READ_0_READ_MASK _MK_MASK_CONST(0xff31) +#define DC_COM_CMU_LUT1_READ_0_WRITE_MASK _MK_MASK_CONST(0xff31) +#define DC_COM_CMU_LUT1_READ_0_LUT1_READ_EN_SHIFT _MK_SHIFT_CONST(0) +#define DC_COM_CMU_LUT1_READ_0_LUT1_READ_EN_FIELD _MK_FIELD_CONST(0x1, DC_COM_CMU_LUT1_READ_0_LUT1_READ_EN_SHIFT) +#define DC_COM_CMU_LUT1_READ_0_LUT1_READ_EN_RANGE 0:0 +#define DC_COM_CMU_LUT1_READ_0_LUT1_READ_EN_WOFFSET 0x0 +#define DC_COM_CMU_LUT1_READ_0_LUT1_READ_EN_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_CMU_LUT1_READ_0_LUT1_READ_EN_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_COM_CMU_LUT1_READ_0_LUT1_READ_EN_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_CMU_LUT1_READ_0_LUT1_READ_EN_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_COM_CMU_LUT1_READ_0_LUT1_READ_MASK_SHIFT _MK_SHIFT_CONST(4) +#define DC_COM_CMU_LUT1_READ_0_LUT1_READ_MASK_FIELD _MK_FIELD_CONST(0x3, DC_COM_CMU_LUT1_READ_0_LUT1_READ_MASK_SHIFT) +#define DC_COM_CMU_LUT1_READ_0_LUT1_READ_MASK_RANGE 5:4 +#define DC_COM_CMU_LUT1_READ_0_LUT1_READ_MASK_WOFFSET 0x0 +#define DC_COM_CMU_LUT1_READ_0_LUT1_READ_MASK_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_CMU_LUT1_READ_0_LUT1_READ_MASK_DEFAULT_MASK _MK_MASK_CONST(0x3) +#define DC_COM_CMU_LUT1_READ_0_LUT1_READ_MASK_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_CMU_LUT1_READ_0_LUT1_READ_MASK_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_CMU_LUT1_READ_0_LUT1_READ_MASK_ALL _MK_ENUM_CONST(0) +#define DC_COM_CMU_LUT1_READ_0_LUT1_READ_MASK_RED _MK_ENUM_CONST(1) +#define DC_COM_CMU_LUT1_READ_0_LUT1_READ_MASK_GREEN _MK_ENUM_CONST(2) +#define DC_COM_CMU_LUT1_READ_0_LUT1_READ_MASK_BLUE _MK_ENUM_CONST(3) + +#define DC_COM_CMU_LUT1_READ_0_LUT1_READ_ADDR_SHIFT _MK_SHIFT_CONST(8) +#define DC_COM_CMU_LUT1_READ_0_LUT1_READ_ADDR_FIELD _MK_FIELD_CONST(0xff, DC_COM_CMU_LUT1_READ_0_LUT1_READ_ADDR_SHIFT) +#define DC_COM_CMU_LUT1_READ_0_LUT1_READ_ADDR_RANGE 15:8 +#define DC_COM_CMU_LUT1_READ_0_LUT1_READ_ADDR_WOFFSET 0x0 +#define DC_COM_CMU_LUT1_READ_0_LUT1_READ_ADDR_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_CMU_LUT1_READ_0_LUT1_READ_ADDR_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_CMU_LUT1_READ_0_LUT1_READ_ADDR_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_CMU_LUT1_READ_0_LUT1_READ_ADDR_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_COM_CMU_LUT2_READ_0 +#define DC_COM_CMU_LUT2_READ_0 _MK_ADDR_CONST(0x339) +#define DC_COM_CMU_LUT2_READ_0_SECURE 0x0 +#define DC_COM_CMU_LUT2_READ_0_WORD_COUNT 0x1 +#define DC_COM_CMU_LUT2_READ_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_COM_CMU_LUT2_READ_0_RESET_MASK _MK_MASK_CONST(0x31) +#define DC_COM_CMU_LUT2_READ_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_COM_CMU_LUT2_READ_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_CMU_LUT2_READ_0_READ_MASK _MK_MASK_CONST(0x3ff31) +#define DC_COM_CMU_LUT2_READ_0_WRITE_MASK _MK_MASK_CONST(0x3ff31) +#define DC_COM_CMU_LUT2_READ_0_LUT2_READ_EN_SHIFT _MK_SHIFT_CONST(0) +#define DC_COM_CMU_LUT2_READ_0_LUT2_READ_EN_FIELD _MK_FIELD_CONST(0x1, DC_COM_CMU_LUT2_READ_0_LUT2_READ_EN_SHIFT) +#define DC_COM_CMU_LUT2_READ_0_LUT2_READ_EN_RANGE 0:0 +#define DC_COM_CMU_LUT2_READ_0_LUT2_READ_EN_WOFFSET 0x0 +#define DC_COM_CMU_LUT2_READ_0_LUT2_READ_EN_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_CMU_LUT2_READ_0_LUT2_READ_EN_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_COM_CMU_LUT2_READ_0_LUT2_READ_EN_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_CMU_LUT2_READ_0_LUT2_READ_EN_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_COM_CMU_LUT2_READ_0_LUT2_READ_MASK_SHIFT _MK_SHIFT_CONST(4) +#define DC_COM_CMU_LUT2_READ_0_LUT2_READ_MASK_FIELD _MK_FIELD_CONST(0x3, DC_COM_CMU_LUT2_READ_0_LUT2_READ_MASK_SHIFT) +#define DC_COM_CMU_LUT2_READ_0_LUT2_READ_MASK_RANGE 5:4 +#define DC_COM_CMU_LUT2_READ_0_LUT2_READ_MASK_WOFFSET 0x0 +#define DC_COM_CMU_LUT2_READ_0_LUT2_READ_MASK_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_CMU_LUT2_READ_0_LUT2_READ_MASK_DEFAULT_MASK _MK_MASK_CONST(0x3) +#define DC_COM_CMU_LUT2_READ_0_LUT2_READ_MASK_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_CMU_LUT2_READ_0_LUT2_READ_MASK_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_CMU_LUT2_READ_0_LUT2_READ_MASK_ALL _MK_ENUM_CONST(0) +#define DC_COM_CMU_LUT2_READ_0_LUT2_READ_MASK_RED _MK_ENUM_CONST(1) +#define DC_COM_CMU_LUT2_READ_0_LUT2_READ_MASK_GREEN _MK_ENUM_CONST(2) +#define DC_COM_CMU_LUT2_READ_0_LUT2_READ_MASK_BLUE _MK_ENUM_CONST(3) + +#define DC_COM_CMU_LUT2_READ_0_LUT2_READ_ADDR_SHIFT _MK_SHIFT_CONST(8) +#define DC_COM_CMU_LUT2_READ_0_LUT2_READ_ADDR_FIELD _MK_FIELD_CONST(0x3ff, DC_COM_CMU_LUT2_READ_0_LUT2_READ_ADDR_SHIFT) +#define DC_COM_CMU_LUT2_READ_0_LUT2_READ_ADDR_RANGE 17:8 +#define DC_COM_CMU_LUT2_READ_0_LUT2_READ_ADDR_WOFFSET 0x0 +#define DC_COM_CMU_LUT2_READ_0_LUT2_READ_ADDR_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_CMU_LUT2_READ_0_LUT2_READ_ADDR_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_COM_CMU_LUT2_READ_0_LUT2_READ_ADDR_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_COM_CMU_LUT2_READ_0_LUT2_READ_ADDR_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Reserved address 826 [0x33a] + +// Reserved address 827 [0x33b] + +// Reserved address 828 [0x33c] + +// Reserved address 829 [0x33d] + +// Register DC_DISP_DISP_SIGNAL_OPTIONS0_0 +#define DC_DISP_DISP_SIGNAL_OPTIONS0_0 _MK_ADDR_CONST(0x400) +#define DC_DISP_DISP_SIGNAL_OPTIONS0_0_SECURE 0x0 +#define DC_DISP_DISP_SIGNAL_OPTIONS0_0_WORD_COUNT 0x1 +#define DC_DISP_DISP_SIGNAL_OPTIONS0_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_DISP_SIGNAL_OPTIONS0_0_RESET_MASK _MK_MASK_CONST(0x51d1500) +#define DC_DISP_DISP_SIGNAL_OPTIONS0_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_DISP_SIGNAL_OPTIONS0_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_DISP_SIGNAL_OPTIONS0_0_READ_MASK _MK_MASK_CONST(0x51d1500) +#define DC_DISP_DISP_SIGNAL_OPTIONS0_0_WRITE_MASK _MK_MASK_CONST(0x51d1500) +#define DC_DISP_DISP_SIGNAL_OPTIONS0_0_H_PULSE0_ENABLE_SHIFT _MK_SHIFT_CONST(8) +#define DC_DISP_DISP_SIGNAL_OPTIONS0_0_H_PULSE0_ENABLE_FIELD _MK_FIELD_CONST(0x1, DC_DISP_DISP_SIGNAL_OPTIONS0_0_H_PULSE0_ENABLE_SHIFT) +#define DC_DISP_DISP_SIGNAL_OPTIONS0_0_H_PULSE0_ENABLE_RANGE 8:8 +#define DC_DISP_DISP_SIGNAL_OPTIONS0_0_H_PULSE0_ENABLE_WOFFSET 0x0 +#define DC_DISP_DISP_SIGNAL_OPTIONS0_0_H_PULSE0_ENABLE_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_DISP_SIGNAL_OPTIONS0_0_H_PULSE0_ENABLE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_DISP_DISP_SIGNAL_OPTIONS0_0_H_PULSE0_ENABLE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_DISP_SIGNAL_OPTIONS0_0_H_PULSE0_ENABLE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_DISP_SIGNAL_OPTIONS0_0_H_PULSE0_ENABLE_DISABLE _MK_ENUM_CONST(0) +#define DC_DISP_DISP_SIGNAL_OPTIONS0_0_H_PULSE0_ENABLE_ENABLE _MK_ENUM_CONST(1) + +#define DC_DISP_DISP_SIGNAL_OPTIONS0_0_H_PULSE1_ENABLE_SHIFT _MK_SHIFT_CONST(10) +#define DC_DISP_DISP_SIGNAL_OPTIONS0_0_H_PULSE1_ENABLE_FIELD _MK_FIELD_CONST(0x1, DC_DISP_DISP_SIGNAL_OPTIONS0_0_H_PULSE1_ENABLE_SHIFT) +#define DC_DISP_DISP_SIGNAL_OPTIONS0_0_H_PULSE1_ENABLE_RANGE 10:10 +#define DC_DISP_DISP_SIGNAL_OPTIONS0_0_H_PULSE1_ENABLE_WOFFSET 0x0 +#define DC_DISP_DISP_SIGNAL_OPTIONS0_0_H_PULSE1_ENABLE_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_DISP_SIGNAL_OPTIONS0_0_H_PULSE1_ENABLE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_DISP_DISP_SIGNAL_OPTIONS0_0_H_PULSE1_ENABLE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_DISP_SIGNAL_OPTIONS0_0_H_PULSE1_ENABLE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_DISP_SIGNAL_OPTIONS0_0_H_PULSE1_ENABLE_DISABLE _MK_ENUM_CONST(0) +#define DC_DISP_DISP_SIGNAL_OPTIONS0_0_H_PULSE1_ENABLE_ENABLE _MK_ENUM_CONST(1) + +#define DC_DISP_DISP_SIGNAL_OPTIONS0_0_H_PULSE2_ENABLE_SHIFT _MK_SHIFT_CONST(12) +#define DC_DISP_DISP_SIGNAL_OPTIONS0_0_H_PULSE2_ENABLE_FIELD _MK_FIELD_CONST(0x1, DC_DISP_DISP_SIGNAL_OPTIONS0_0_H_PULSE2_ENABLE_SHIFT) +#define DC_DISP_DISP_SIGNAL_OPTIONS0_0_H_PULSE2_ENABLE_RANGE 12:12 +#define DC_DISP_DISP_SIGNAL_OPTIONS0_0_H_PULSE2_ENABLE_WOFFSET 0x0 +#define DC_DISP_DISP_SIGNAL_OPTIONS0_0_H_PULSE2_ENABLE_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_DISP_SIGNAL_OPTIONS0_0_H_PULSE2_ENABLE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_DISP_DISP_SIGNAL_OPTIONS0_0_H_PULSE2_ENABLE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_DISP_SIGNAL_OPTIONS0_0_H_PULSE2_ENABLE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_DISP_SIGNAL_OPTIONS0_0_H_PULSE2_ENABLE_DISABLE _MK_ENUM_CONST(0) +#define DC_DISP_DISP_SIGNAL_OPTIONS0_0_H_PULSE2_ENABLE_ENABLE _MK_ENUM_CONST(1) + +#define DC_DISP_DISP_SIGNAL_OPTIONS0_0_V_PULSE0_ENABLE_SHIFT _MK_SHIFT_CONST(16) +#define DC_DISP_DISP_SIGNAL_OPTIONS0_0_V_PULSE0_ENABLE_FIELD _MK_FIELD_CONST(0x1, DC_DISP_DISP_SIGNAL_OPTIONS0_0_V_PULSE0_ENABLE_SHIFT) +#define DC_DISP_DISP_SIGNAL_OPTIONS0_0_V_PULSE0_ENABLE_RANGE 16:16 +#define DC_DISP_DISP_SIGNAL_OPTIONS0_0_V_PULSE0_ENABLE_WOFFSET 0x0 +#define DC_DISP_DISP_SIGNAL_OPTIONS0_0_V_PULSE0_ENABLE_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_DISP_SIGNAL_OPTIONS0_0_V_PULSE0_ENABLE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_DISP_DISP_SIGNAL_OPTIONS0_0_V_PULSE0_ENABLE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_DISP_SIGNAL_OPTIONS0_0_V_PULSE0_ENABLE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_DISP_SIGNAL_OPTIONS0_0_V_PULSE0_ENABLE_DISABLE _MK_ENUM_CONST(0) +#define DC_DISP_DISP_SIGNAL_OPTIONS0_0_V_PULSE0_ENABLE_ENABLE _MK_ENUM_CONST(1) + +#define DC_DISP_DISP_SIGNAL_OPTIONS0_0_V_PULSE1_ENABLE_SHIFT _MK_SHIFT_CONST(18) +#define DC_DISP_DISP_SIGNAL_OPTIONS0_0_V_PULSE1_ENABLE_FIELD _MK_FIELD_CONST(0x1, DC_DISP_DISP_SIGNAL_OPTIONS0_0_V_PULSE1_ENABLE_SHIFT) +#define DC_DISP_DISP_SIGNAL_OPTIONS0_0_V_PULSE1_ENABLE_RANGE 18:18 +#define DC_DISP_DISP_SIGNAL_OPTIONS0_0_V_PULSE1_ENABLE_WOFFSET 0x0 +#define DC_DISP_DISP_SIGNAL_OPTIONS0_0_V_PULSE1_ENABLE_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_DISP_SIGNAL_OPTIONS0_0_V_PULSE1_ENABLE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_DISP_DISP_SIGNAL_OPTIONS0_0_V_PULSE1_ENABLE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_DISP_SIGNAL_OPTIONS0_0_V_PULSE1_ENABLE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_DISP_SIGNAL_OPTIONS0_0_V_PULSE1_ENABLE_DISABLE _MK_ENUM_CONST(0) +#define DC_DISP_DISP_SIGNAL_OPTIONS0_0_V_PULSE1_ENABLE_ENABLE _MK_ENUM_CONST(1) + +#define DC_DISP_DISP_SIGNAL_OPTIONS0_0_V_PULSE2_ENABLE_SHIFT _MK_SHIFT_CONST(19) +#define DC_DISP_DISP_SIGNAL_OPTIONS0_0_V_PULSE2_ENABLE_FIELD _MK_FIELD_CONST(0x1, DC_DISP_DISP_SIGNAL_OPTIONS0_0_V_PULSE2_ENABLE_SHIFT) +#define DC_DISP_DISP_SIGNAL_OPTIONS0_0_V_PULSE2_ENABLE_RANGE 19:19 +#define DC_DISP_DISP_SIGNAL_OPTIONS0_0_V_PULSE2_ENABLE_WOFFSET 0x0 +#define DC_DISP_DISP_SIGNAL_OPTIONS0_0_V_PULSE2_ENABLE_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_DISP_SIGNAL_OPTIONS0_0_V_PULSE2_ENABLE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_DISP_DISP_SIGNAL_OPTIONS0_0_V_PULSE2_ENABLE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_DISP_SIGNAL_OPTIONS0_0_V_PULSE2_ENABLE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_DISP_SIGNAL_OPTIONS0_0_V_PULSE2_ENABLE_DISABLE _MK_ENUM_CONST(0) +#define DC_DISP_DISP_SIGNAL_OPTIONS0_0_V_PULSE2_ENABLE_ENABLE _MK_ENUM_CONST(1) + +#define DC_DISP_DISP_SIGNAL_OPTIONS0_0_V_PULSE3_ENABLE_SHIFT _MK_SHIFT_CONST(20) +#define DC_DISP_DISP_SIGNAL_OPTIONS0_0_V_PULSE3_ENABLE_FIELD _MK_FIELD_CONST(0x1, DC_DISP_DISP_SIGNAL_OPTIONS0_0_V_PULSE3_ENABLE_SHIFT) +#define DC_DISP_DISP_SIGNAL_OPTIONS0_0_V_PULSE3_ENABLE_RANGE 20:20 +#define DC_DISP_DISP_SIGNAL_OPTIONS0_0_V_PULSE3_ENABLE_WOFFSET 0x0 +#define DC_DISP_DISP_SIGNAL_OPTIONS0_0_V_PULSE3_ENABLE_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_DISP_SIGNAL_OPTIONS0_0_V_PULSE3_ENABLE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_DISP_DISP_SIGNAL_OPTIONS0_0_V_PULSE3_ENABLE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_DISP_SIGNAL_OPTIONS0_0_V_PULSE3_ENABLE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_DISP_SIGNAL_OPTIONS0_0_V_PULSE3_ENABLE_DISABLE _MK_ENUM_CONST(0) +#define DC_DISP_DISP_SIGNAL_OPTIONS0_0_V_PULSE3_ENABLE_ENABLE _MK_ENUM_CONST(1) + +#define DC_DISP_DISP_SIGNAL_OPTIONS0_0_M0_ENABLE_SHIFT _MK_SHIFT_CONST(24) +#define DC_DISP_DISP_SIGNAL_OPTIONS0_0_M0_ENABLE_FIELD _MK_FIELD_CONST(0x1, DC_DISP_DISP_SIGNAL_OPTIONS0_0_M0_ENABLE_SHIFT) +#define DC_DISP_DISP_SIGNAL_OPTIONS0_0_M0_ENABLE_RANGE 24:24 +#define DC_DISP_DISP_SIGNAL_OPTIONS0_0_M0_ENABLE_WOFFSET 0x0 +#define DC_DISP_DISP_SIGNAL_OPTIONS0_0_M0_ENABLE_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_DISP_SIGNAL_OPTIONS0_0_M0_ENABLE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_DISP_DISP_SIGNAL_OPTIONS0_0_M0_ENABLE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_DISP_SIGNAL_OPTIONS0_0_M0_ENABLE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_DISP_SIGNAL_OPTIONS0_0_M0_ENABLE_DISABLE _MK_ENUM_CONST(0) +#define DC_DISP_DISP_SIGNAL_OPTIONS0_0_M0_ENABLE_ENABLE _MK_ENUM_CONST(1) + +#define DC_DISP_DISP_SIGNAL_OPTIONS0_0_M1_ENABLE_SHIFT _MK_SHIFT_CONST(26) +#define DC_DISP_DISP_SIGNAL_OPTIONS0_0_M1_ENABLE_FIELD _MK_FIELD_CONST(0x1, DC_DISP_DISP_SIGNAL_OPTIONS0_0_M1_ENABLE_SHIFT) +#define DC_DISP_DISP_SIGNAL_OPTIONS0_0_M1_ENABLE_RANGE 26:26 +#define DC_DISP_DISP_SIGNAL_OPTIONS0_0_M1_ENABLE_WOFFSET 0x0 +#define DC_DISP_DISP_SIGNAL_OPTIONS0_0_M1_ENABLE_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_DISP_SIGNAL_OPTIONS0_0_M1_ENABLE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_DISP_DISP_SIGNAL_OPTIONS0_0_M1_ENABLE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_DISP_SIGNAL_OPTIONS0_0_M1_ENABLE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_DISP_SIGNAL_OPTIONS0_0_M1_ENABLE_DISABLE _MK_ENUM_CONST(0) +#define DC_DISP_DISP_SIGNAL_OPTIONS0_0_M1_ENABLE_ENABLE _MK_ENUM_CONST(1) + + +// Register DC_DISP_DISP_SIGNAL_OPTIONS1_0 +#define DC_DISP_DISP_SIGNAL_OPTIONS1_0 _MK_ADDR_CONST(0x401) +#define DC_DISP_DISP_SIGNAL_OPTIONS1_0_SECURE 0x0 +#define DC_DISP_DISP_SIGNAL_OPTIONS1_0_WORD_COUNT 0x1 +#define DC_DISP_DISP_SIGNAL_OPTIONS1_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_DISP_SIGNAL_OPTIONS1_0_RESET_MASK _MK_MASK_CONST(0x50000) +#define DC_DISP_DISP_SIGNAL_OPTIONS1_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_DISP_SIGNAL_OPTIONS1_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_DISP_SIGNAL_OPTIONS1_0_READ_MASK _MK_MASK_CONST(0x50000) +#define DC_DISP_DISP_SIGNAL_OPTIONS1_0_WRITE_MASK _MK_MASK_CONST(0x50000) +#define DC_DISP_DISP_SIGNAL_OPTIONS1_0_DI_ENABLE_SHIFT _MK_SHIFT_CONST(16) +#define DC_DISP_DISP_SIGNAL_OPTIONS1_0_DI_ENABLE_FIELD _MK_FIELD_CONST(0x1, DC_DISP_DISP_SIGNAL_OPTIONS1_0_DI_ENABLE_SHIFT) +#define DC_DISP_DISP_SIGNAL_OPTIONS1_0_DI_ENABLE_RANGE 16:16 +#define DC_DISP_DISP_SIGNAL_OPTIONS1_0_DI_ENABLE_WOFFSET 0x0 +#define DC_DISP_DISP_SIGNAL_OPTIONS1_0_DI_ENABLE_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_DISP_SIGNAL_OPTIONS1_0_DI_ENABLE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_DISP_DISP_SIGNAL_OPTIONS1_0_DI_ENABLE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_DISP_SIGNAL_OPTIONS1_0_DI_ENABLE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_DISP_SIGNAL_OPTIONS1_0_DI_ENABLE_DISABLE _MK_ENUM_CONST(0) +#define DC_DISP_DISP_SIGNAL_OPTIONS1_0_DI_ENABLE_ENABLE _MK_ENUM_CONST(1) + +#define DC_DISP_DISP_SIGNAL_OPTIONS1_0_PP_ENABLE_SHIFT _MK_SHIFT_CONST(18) +#define DC_DISP_DISP_SIGNAL_OPTIONS1_0_PP_ENABLE_FIELD _MK_FIELD_CONST(0x1, DC_DISP_DISP_SIGNAL_OPTIONS1_0_PP_ENABLE_SHIFT) +#define DC_DISP_DISP_SIGNAL_OPTIONS1_0_PP_ENABLE_RANGE 18:18 +#define DC_DISP_DISP_SIGNAL_OPTIONS1_0_PP_ENABLE_WOFFSET 0x0 +#define DC_DISP_DISP_SIGNAL_OPTIONS1_0_PP_ENABLE_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_DISP_SIGNAL_OPTIONS1_0_PP_ENABLE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_DISP_DISP_SIGNAL_OPTIONS1_0_PP_ENABLE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_DISP_SIGNAL_OPTIONS1_0_PP_ENABLE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_DISP_SIGNAL_OPTIONS1_0_PP_ENABLE_DISABLE _MK_ENUM_CONST(0) +#define DC_DISP_DISP_SIGNAL_OPTIONS1_0_PP_ENABLE_ENABLE _MK_ENUM_CONST(1) + + +// Register DC_DISP_DISP_WIN_OPTIONS_0 +#define DC_DISP_DISP_WIN_OPTIONS_0 _MK_ADDR_CONST(0x402) +#define DC_DISP_DISP_WIN_OPTIONS_0_SECURE 0x0 +#define DC_DISP_DISP_WIN_OPTIONS_0_WORD_COUNT 0x1 +#define DC_DISP_DISP_WIN_OPTIONS_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_DISP_WIN_OPTIONS_0_RESET_MASK _MK_MASK_CONST(0x62010000) +#define DC_DISP_DISP_WIN_OPTIONS_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_DISP_WIN_OPTIONS_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_DISP_WIN_OPTIONS_0_READ_MASK _MK_MASK_CONST(0x62010000) +#define DC_DISP_DISP_WIN_OPTIONS_0_WRITE_MASK _MK_MASK_CONST(0x62010000) +#define DC_DISP_DISP_WIN_OPTIONS_0_CURSOR_ENABLE_SHIFT _MK_SHIFT_CONST(16) +#define DC_DISP_DISP_WIN_OPTIONS_0_CURSOR_ENABLE_FIELD _MK_FIELD_CONST(0x1, DC_DISP_DISP_WIN_OPTIONS_0_CURSOR_ENABLE_SHIFT) +#define DC_DISP_DISP_WIN_OPTIONS_0_CURSOR_ENABLE_RANGE 16:16 +#define DC_DISP_DISP_WIN_OPTIONS_0_CURSOR_ENABLE_WOFFSET 0x0 +#define DC_DISP_DISP_WIN_OPTIONS_0_CURSOR_ENABLE_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_DISP_WIN_OPTIONS_0_CURSOR_ENABLE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_DISP_DISP_WIN_OPTIONS_0_CURSOR_ENABLE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_DISP_WIN_OPTIONS_0_CURSOR_ENABLE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_DISP_WIN_OPTIONS_0_CURSOR_ENABLE_DISABLE _MK_ENUM_CONST(0) +#define DC_DISP_DISP_WIN_OPTIONS_0_CURSOR_ENABLE_ENABLE _MK_ENUM_CONST(1) + +#define DC_DISP_DISP_WIN_OPTIONS_0_SOR_ENABLE_SHIFT _MK_SHIFT_CONST(25) +#define DC_DISP_DISP_WIN_OPTIONS_0_SOR_ENABLE_FIELD _MK_FIELD_CONST(0x1, DC_DISP_DISP_WIN_OPTIONS_0_SOR_ENABLE_SHIFT) +#define DC_DISP_DISP_WIN_OPTIONS_0_SOR_ENABLE_RANGE 25:25 +#define DC_DISP_DISP_WIN_OPTIONS_0_SOR_ENABLE_WOFFSET 0x0 +#define DC_DISP_DISP_WIN_OPTIONS_0_SOR_ENABLE_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_DISP_WIN_OPTIONS_0_SOR_ENABLE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_DISP_DISP_WIN_OPTIONS_0_SOR_ENABLE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_DISP_WIN_OPTIONS_0_SOR_ENABLE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_DISP_WIN_OPTIONS_0_SOR_ENABLE_DISABLE _MK_ENUM_CONST(0) +#define DC_DISP_DISP_WIN_OPTIONS_0_SOR_ENABLE_ENABLE _MK_ENUM_CONST(1) + +#define DC_DISP_DISP_WIN_OPTIONS_0_DSI_ENABLE_SHIFT _MK_SHIFT_CONST(29) +#define DC_DISP_DISP_WIN_OPTIONS_0_DSI_ENABLE_FIELD _MK_FIELD_CONST(0x1, DC_DISP_DISP_WIN_OPTIONS_0_DSI_ENABLE_SHIFT) +#define DC_DISP_DISP_WIN_OPTIONS_0_DSI_ENABLE_RANGE 29:29 +#define DC_DISP_DISP_WIN_OPTIONS_0_DSI_ENABLE_WOFFSET 0x0 +#define DC_DISP_DISP_WIN_OPTIONS_0_DSI_ENABLE_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_DISP_WIN_OPTIONS_0_DSI_ENABLE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_DISP_DISP_WIN_OPTIONS_0_DSI_ENABLE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_DISP_WIN_OPTIONS_0_DSI_ENABLE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_DISP_WIN_OPTIONS_0_DSI_ENABLE_DISABLE _MK_ENUM_CONST(0) +#define DC_DISP_DISP_WIN_OPTIONS_0_DSI_ENABLE_ENABLE _MK_ENUM_CONST(1) + +#define DC_DISP_DISP_WIN_OPTIONS_0_HDMI_ENABLE_SHIFT _MK_SHIFT_CONST(30) +#define DC_DISP_DISP_WIN_OPTIONS_0_HDMI_ENABLE_FIELD _MK_FIELD_CONST(0x1, DC_DISP_DISP_WIN_OPTIONS_0_HDMI_ENABLE_SHIFT) +#define DC_DISP_DISP_WIN_OPTIONS_0_HDMI_ENABLE_RANGE 30:30 +#define DC_DISP_DISP_WIN_OPTIONS_0_HDMI_ENABLE_WOFFSET 0x0 +#define DC_DISP_DISP_WIN_OPTIONS_0_HDMI_ENABLE_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_DISP_WIN_OPTIONS_0_HDMI_ENABLE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_DISP_DISP_WIN_OPTIONS_0_HDMI_ENABLE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_DISP_WIN_OPTIONS_0_HDMI_ENABLE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_DISP_WIN_OPTIONS_0_HDMI_ENABLE_DISABLE _MK_ENUM_CONST(0) +#define DC_DISP_DISP_WIN_OPTIONS_0_HDMI_ENABLE_ENABLE _MK_ENUM_CONST(1) + + +// Register DC_DISP_MEM_HIGH_PRIORITY_0 +#define DC_DISP_MEM_HIGH_PRIORITY_0 _MK_ADDR_CONST(0x403) +#define DC_DISP_MEM_HIGH_PRIORITY_0_SECURE 0x0 +#define DC_DISP_MEM_HIGH_PRIORITY_0_WORD_COUNT 0x1 +#define DC_DISP_MEM_HIGH_PRIORITY_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_MEM_HIGH_PRIORITY_0_RESET_MASK _MK_MASK_CONST(0x3f7f7f7f) +#define DC_DISP_MEM_HIGH_PRIORITY_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_MEM_HIGH_PRIORITY_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_MEM_HIGH_PRIORITY_0_READ_MASK _MK_MASK_CONST(0x3f7f7f7f) +#define DC_DISP_MEM_HIGH_PRIORITY_0_WRITE_MASK _MK_MASK_CONST(0x3f7f7f7f) +#define DC_DISP_MEM_HIGH_PRIORITY_0_CBR_DISPLAY0A2MC_HPTH_SHIFT _MK_SHIFT_CONST(0) +#define DC_DISP_MEM_HIGH_PRIORITY_0_CBR_DISPLAY0A2MC_HPTH_FIELD _MK_FIELD_CONST(0x7f, DC_DISP_MEM_HIGH_PRIORITY_0_CBR_DISPLAY0A2MC_HPTH_SHIFT) +#define DC_DISP_MEM_HIGH_PRIORITY_0_CBR_DISPLAY0A2MC_HPTH_RANGE 6:0 +#define DC_DISP_MEM_HIGH_PRIORITY_0_CBR_DISPLAY0A2MC_HPTH_WOFFSET 0x0 +#define DC_DISP_MEM_HIGH_PRIORITY_0_CBR_DISPLAY0A2MC_HPTH_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_MEM_HIGH_PRIORITY_0_CBR_DISPLAY0A2MC_HPTH_DEFAULT_MASK _MK_MASK_CONST(0x7f) +#define DC_DISP_MEM_HIGH_PRIORITY_0_CBR_DISPLAY0A2MC_HPTH_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_MEM_HIGH_PRIORITY_0_CBR_DISPLAY0A2MC_HPTH_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_DISP_MEM_HIGH_PRIORITY_0_CBR_DISPLAYB2MC_HPTH_SHIFT _MK_SHIFT_CONST(8) +#define DC_DISP_MEM_HIGH_PRIORITY_0_CBR_DISPLAYB2MC_HPTH_FIELD _MK_FIELD_CONST(0x7f, DC_DISP_MEM_HIGH_PRIORITY_0_CBR_DISPLAYB2MC_HPTH_SHIFT) +#define DC_DISP_MEM_HIGH_PRIORITY_0_CBR_DISPLAYB2MC_HPTH_RANGE 14:8 +#define DC_DISP_MEM_HIGH_PRIORITY_0_CBR_DISPLAYB2MC_HPTH_WOFFSET 0x0 +#define DC_DISP_MEM_HIGH_PRIORITY_0_CBR_DISPLAYB2MC_HPTH_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_MEM_HIGH_PRIORITY_0_CBR_DISPLAYB2MC_HPTH_DEFAULT_MASK _MK_MASK_CONST(0x7f) +#define DC_DISP_MEM_HIGH_PRIORITY_0_CBR_DISPLAYB2MC_HPTH_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_MEM_HIGH_PRIORITY_0_CBR_DISPLAYB2MC_HPTH_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_DISP_MEM_HIGH_PRIORITY_0_CBR_DISPLAY0C2MC_HPTH_SHIFT _MK_SHIFT_CONST(16) +#define DC_DISP_MEM_HIGH_PRIORITY_0_CBR_DISPLAY0C2MC_HPTH_FIELD _MK_FIELD_CONST(0x7f, DC_DISP_MEM_HIGH_PRIORITY_0_CBR_DISPLAY0C2MC_HPTH_SHIFT) +#define DC_DISP_MEM_HIGH_PRIORITY_0_CBR_DISPLAY0C2MC_HPTH_RANGE 22:16 +#define DC_DISP_MEM_HIGH_PRIORITY_0_CBR_DISPLAY0C2MC_HPTH_WOFFSET 0x0 +#define DC_DISP_MEM_HIGH_PRIORITY_0_CBR_DISPLAY0C2MC_HPTH_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_MEM_HIGH_PRIORITY_0_CBR_DISPLAY0C2MC_HPTH_DEFAULT_MASK _MK_MASK_CONST(0x7f) +#define DC_DISP_MEM_HIGH_PRIORITY_0_CBR_DISPLAY0C2MC_HPTH_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_MEM_HIGH_PRIORITY_0_CBR_DISPLAY0C2MC_HPTH_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_DISP_MEM_HIGH_PRIORITY_0_CSR_DISPLAYHC2MC_HPTH_SHIFT _MK_SHIFT_CONST(24) +#define DC_DISP_MEM_HIGH_PRIORITY_0_CSR_DISPLAYHC2MC_HPTH_FIELD _MK_FIELD_CONST(0x3f, DC_DISP_MEM_HIGH_PRIORITY_0_CSR_DISPLAYHC2MC_HPTH_SHIFT) +#define DC_DISP_MEM_HIGH_PRIORITY_0_CSR_DISPLAYHC2MC_HPTH_RANGE 29:24 +#define DC_DISP_MEM_HIGH_PRIORITY_0_CSR_DISPLAYHC2MC_HPTH_WOFFSET 0x0 +#define DC_DISP_MEM_HIGH_PRIORITY_0_CSR_DISPLAYHC2MC_HPTH_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_MEM_HIGH_PRIORITY_0_CSR_DISPLAYHC2MC_HPTH_DEFAULT_MASK _MK_MASK_CONST(0x3f) +#define DC_DISP_MEM_HIGH_PRIORITY_0_CSR_DISPLAYHC2MC_HPTH_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_MEM_HIGH_PRIORITY_0_CSR_DISPLAYHC2MC_HPTH_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_DISP_MEM_HIGH_PRIORITY_TIMER_0 +#define DC_DISP_MEM_HIGH_PRIORITY_TIMER_0 _MK_ADDR_CONST(0x404) +#define DC_DISP_MEM_HIGH_PRIORITY_TIMER_0_SECURE 0x0 +#define DC_DISP_MEM_HIGH_PRIORITY_TIMER_0_WORD_COUNT 0x1 +#define DC_DISP_MEM_HIGH_PRIORITY_TIMER_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_MEM_HIGH_PRIORITY_TIMER_0_RESET_MASK _MK_MASK_CONST(0x3f3f3f3f) +#define DC_DISP_MEM_HIGH_PRIORITY_TIMER_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_MEM_HIGH_PRIORITY_TIMER_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_MEM_HIGH_PRIORITY_TIMER_0_READ_MASK _MK_MASK_CONST(0x3f3f3f3f) +#define DC_DISP_MEM_HIGH_PRIORITY_TIMER_0_WRITE_MASK _MK_MASK_CONST(0x3f3f3f3f) +#define DC_DISP_MEM_HIGH_PRIORITY_TIMER_0_CBR_DISPLAY0A2MC_HPTM_SHIFT _MK_SHIFT_CONST(0) +#define DC_DISP_MEM_HIGH_PRIORITY_TIMER_0_CBR_DISPLAY0A2MC_HPTM_FIELD _MK_FIELD_CONST(0x3f, DC_DISP_MEM_HIGH_PRIORITY_TIMER_0_CBR_DISPLAY0A2MC_HPTM_SHIFT) +#define DC_DISP_MEM_HIGH_PRIORITY_TIMER_0_CBR_DISPLAY0A2MC_HPTM_RANGE 5:0 +#define DC_DISP_MEM_HIGH_PRIORITY_TIMER_0_CBR_DISPLAY0A2MC_HPTM_WOFFSET 0x0 +#define DC_DISP_MEM_HIGH_PRIORITY_TIMER_0_CBR_DISPLAY0A2MC_HPTM_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_MEM_HIGH_PRIORITY_TIMER_0_CBR_DISPLAY0A2MC_HPTM_DEFAULT_MASK _MK_MASK_CONST(0x3f) +#define DC_DISP_MEM_HIGH_PRIORITY_TIMER_0_CBR_DISPLAY0A2MC_HPTM_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_MEM_HIGH_PRIORITY_TIMER_0_CBR_DISPLAY0A2MC_HPTM_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_DISP_MEM_HIGH_PRIORITY_TIMER_0_CBR_DISPLAYB2MC_HPTM_SHIFT _MK_SHIFT_CONST(8) +#define DC_DISP_MEM_HIGH_PRIORITY_TIMER_0_CBR_DISPLAYB2MC_HPTM_FIELD _MK_FIELD_CONST(0x3f, DC_DISP_MEM_HIGH_PRIORITY_TIMER_0_CBR_DISPLAYB2MC_HPTM_SHIFT) +#define DC_DISP_MEM_HIGH_PRIORITY_TIMER_0_CBR_DISPLAYB2MC_HPTM_RANGE 13:8 +#define DC_DISP_MEM_HIGH_PRIORITY_TIMER_0_CBR_DISPLAYB2MC_HPTM_WOFFSET 0x0 +#define DC_DISP_MEM_HIGH_PRIORITY_TIMER_0_CBR_DISPLAYB2MC_HPTM_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_MEM_HIGH_PRIORITY_TIMER_0_CBR_DISPLAYB2MC_HPTM_DEFAULT_MASK _MK_MASK_CONST(0x3f) +#define DC_DISP_MEM_HIGH_PRIORITY_TIMER_0_CBR_DISPLAYB2MC_HPTM_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_MEM_HIGH_PRIORITY_TIMER_0_CBR_DISPLAYB2MC_HPTM_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_DISP_MEM_HIGH_PRIORITY_TIMER_0_CBR_DISPLAY0C2MC_HPTM_SHIFT _MK_SHIFT_CONST(16) +#define DC_DISP_MEM_HIGH_PRIORITY_TIMER_0_CBR_DISPLAY0C2MC_HPTM_FIELD _MK_FIELD_CONST(0x3f, DC_DISP_MEM_HIGH_PRIORITY_TIMER_0_CBR_DISPLAY0C2MC_HPTM_SHIFT) +#define DC_DISP_MEM_HIGH_PRIORITY_TIMER_0_CBR_DISPLAY0C2MC_HPTM_RANGE 21:16 +#define DC_DISP_MEM_HIGH_PRIORITY_TIMER_0_CBR_DISPLAY0C2MC_HPTM_WOFFSET 0x0 +#define DC_DISP_MEM_HIGH_PRIORITY_TIMER_0_CBR_DISPLAY0C2MC_HPTM_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_MEM_HIGH_PRIORITY_TIMER_0_CBR_DISPLAY0C2MC_HPTM_DEFAULT_MASK _MK_MASK_CONST(0x3f) +#define DC_DISP_MEM_HIGH_PRIORITY_TIMER_0_CBR_DISPLAY0C2MC_HPTM_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_MEM_HIGH_PRIORITY_TIMER_0_CBR_DISPLAY0C2MC_HPTM_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_DISP_MEM_HIGH_PRIORITY_TIMER_0_CSR_DISPLAYHC2MC_HPTM_SHIFT _MK_SHIFT_CONST(24) +#define DC_DISP_MEM_HIGH_PRIORITY_TIMER_0_CSR_DISPLAYHC2MC_HPTM_FIELD _MK_FIELD_CONST(0x3f, DC_DISP_MEM_HIGH_PRIORITY_TIMER_0_CSR_DISPLAYHC2MC_HPTM_SHIFT) +#define DC_DISP_MEM_HIGH_PRIORITY_TIMER_0_CSR_DISPLAYHC2MC_HPTM_RANGE 29:24 +#define DC_DISP_MEM_HIGH_PRIORITY_TIMER_0_CSR_DISPLAYHC2MC_HPTM_WOFFSET 0x0 +#define DC_DISP_MEM_HIGH_PRIORITY_TIMER_0_CSR_DISPLAYHC2MC_HPTM_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_MEM_HIGH_PRIORITY_TIMER_0_CSR_DISPLAYHC2MC_HPTM_DEFAULT_MASK _MK_MASK_CONST(0x3f) +#define DC_DISP_MEM_HIGH_PRIORITY_TIMER_0_CSR_DISPLAYHC2MC_HPTM_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_MEM_HIGH_PRIORITY_TIMER_0_CSR_DISPLAYHC2MC_HPTM_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_DISP_DISP_TIMING_OPTIONS_0 +#define DC_DISP_DISP_TIMING_OPTIONS_0 _MK_ADDR_CONST(0x405) +#define DC_DISP_DISP_TIMING_OPTIONS_0_SECURE 0x0 +#define DC_DISP_DISP_TIMING_OPTIONS_0_WORD_COUNT 0x1 +#define DC_DISP_DISP_TIMING_OPTIONS_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_DISP_TIMING_OPTIONS_0_RESET_MASK _MK_MASK_CONST(0x1fff) +#define DC_DISP_DISP_TIMING_OPTIONS_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_DISP_TIMING_OPTIONS_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_DISP_TIMING_OPTIONS_0_READ_MASK _MK_MASK_CONST(0x1fff) +#define DC_DISP_DISP_TIMING_OPTIONS_0_WRITE_MASK _MK_MASK_CONST(0x1fff) +#define DC_DISP_DISP_TIMING_OPTIONS_0_VSYNC_H_POSITION_SHIFT _MK_SHIFT_CONST(0) +#define DC_DISP_DISP_TIMING_OPTIONS_0_VSYNC_H_POSITION_FIELD _MK_FIELD_CONST(0x1fff, DC_DISP_DISP_TIMING_OPTIONS_0_VSYNC_H_POSITION_SHIFT) +#define DC_DISP_DISP_TIMING_OPTIONS_0_VSYNC_H_POSITION_RANGE 12:0 +#define DC_DISP_DISP_TIMING_OPTIONS_0_VSYNC_H_POSITION_WOFFSET 0x0 +#define DC_DISP_DISP_TIMING_OPTIONS_0_VSYNC_H_POSITION_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_DISP_TIMING_OPTIONS_0_VSYNC_H_POSITION_DEFAULT_MASK _MK_MASK_CONST(0x1fff) +#define DC_DISP_DISP_TIMING_OPTIONS_0_VSYNC_H_POSITION_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_DISP_TIMING_OPTIONS_0_VSYNC_H_POSITION_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_DISP_REF_TO_SYNC_0 +#define DC_DISP_REF_TO_SYNC_0 _MK_ADDR_CONST(0x406) +#define DC_DISP_REF_TO_SYNC_0_SECURE 0x0 +#define DC_DISP_REF_TO_SYNC_0_WORD_COUNT 0x1 +#define DC_DISP_REF_TO_SYNC_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_REF_TO_SYNC_0_RESET_MASK _MK_MASK_CONST(0x1fff1fff) +#define DC_DISP_REF_TO_SYNC_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_REF_TO_SYNC_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_REF_TO_SYNC_0_READ_MASK _MK_MASK_CONST(0x1fff1fff) +#define DC_DISP_REF_TO_SYNC_0_WRITE_MASK _MK_MASK_CONST(0x1fff1fff) +#define DC_DISP_REF_TO_SYNC_0_H_REF_TO_SYNC_SHIFT _MK_SHIFT_CONST(0) +#define DC_DISP_REF_TO_SYNC_0_H_REF_TO_SYNC_FIELD _MK_FIELD_CONST(0x1fff, DC_DISP_REF_TO_SYNC_0_H_REF_TO_SYNC_SHIFT) +#define DC_DISP_REF_TO_SYNC_0_H_REF_TO_SYNC_RANGE 12:0 +#define DC_DISP_REF_TO_SYNC_0_H_REF_TO_SYNC_WOFFSET 0x0 +#define DC_DISP_REF_TO_SYNC_0_H_REF_TO_SYNC_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_REF_TO_SYNC_0_H_REF_TO_SYNC_DEFAULT_MASK _MK_MASK_CONST(0x1fff) +#define DC_DISP_REF_TO_SYNC_0_H_REF_TO_SYNC_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_REF_TO_SYNC_0_H_REF_TO_SYNC_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_DISP_REF_TO_SYNC_0_V_REF_TO_SYNC_SHIFT _MK_SHIFT_CONST(16) +#define DC_DISP_REF_TO_SYNC_0_V_REF_TO_SYNC_FIELD _MK_FIELD_CONST(0x1fff, DC_DISP_REF_TO_SYNC_0_V_REF_TO_SYNC_SHIFT) +#define DC_DISP_REF_TO_SYNC_0_V_REF_TO_SYNC_RANGE 28:16 +#define DC_DISP_REF_TO_SYNC_0_V_REF_TO_SYNC_WOFFSET 0x0 +#define DC_DISP_REF_TO_SYNC_0_V_REF_TO_SYNC_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_REF_TO_SYNC_0_V_REF_TO_SYNC_DEFAULT_MASK _MK_MASK_CONST(0x1fff) +#define DC_DISP_REF_TO_SYNC_0_V_REF_TO_SYNC_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_REF_TO_SYNC_0_V_REF_TO_SYNC_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_DISP_SYNC_WIDTH_0 +#define DC_DISP_SYNC_WIDTH_0 _MK_ADDR_CONST(0x407) +#define DC_DISP_SYNC_WIDTH_0_SECURE 0x0 +#define DC_DISP_SYNC_WIDTH_0_WORD_COUNT 0x1 +#define DC_DISP_SYNC_WIDTH_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_SYNC_WIDTH_0_RESET_MASK _MK_MASK_CONST(0x1fff1fff) +#define DC_DISP_SYNC_WIDTH_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_SYNC_WIDTH_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_SYNC_WIDTH_0_READ_MASK _MK_MASK_CONST(0x1fff1fff) +#define DC_DISP_SYNC_WIDTH_0_WRITE_MASK _MK_MASK_CONST(0x1fff1fff) +#define DC_DISP_SYNC_WIDTH_0_H_SYNC_WIDTH_SHIFT _MK_SHIFT_CONST(0) +#define DC_DISP_SYNC_WIDTH_0_H_SYNC_WIDTH_FIELD _MK_FIELD_CONST(0x1fff, DC_DISP_SYNC_WIDTH_0_H_SYNC_WIDTH_SHIFT) +#define DC_DISP_SYNC_WIDTH_0_H_SYNC_WIDTH_RANGE 12:0 +#define DC_DISP_SYNC_WIDTH_0_H_SYNC_WIDTH_WOFFSET 0x0 +#define DC_DISP_SYNC_WIDTH_0_H_SYNC_WIDTH_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SYNC_WIDTH_0_H_SYNC_WIDTH_DEFAULT_MASK _MK_MASK_CONST(0x1fff) +#define DC_DISP_SYNC_WIDTH_0_H_SYNC_WIDTH_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SYNC_WIDTH_0_H_SYNC_WIDTH_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_DISP_SYNC_WIDTH_0_V_SYNC_WIDTH_SHIFT _MK_SHIFT_CONST(16) +#define DC_DISP_SYNC_WIDTH_0_V_SYNC_WIDTH_FIELD _MK_FIELD_CONST(0x1fff, DC_DISP_SYNC_WIDTH_0_V_SYNC_WIDTH_SHIFT) +#define DC_DISP_SYNC_WIDTH_0_V_SYNC_WIDTH_RANGE 28:16 +#define DC_DISP_SYNC_WIDTH_0_V_SYNC_WIDTH_WOFFSET 0x0 +#define DC_DISP_SYNC_WIDTH_0_V_SYNC_WIDTH_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SYNC_WIDTH_0_V_SYNC_WIDTH_DEFAULT_MASK _MK_MASK_CONST(0x1fff) +#define DC_DISP_SYNC_WIDTH_0_V_SYNC_WIDTH_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SYNC_WIDTH_0_V_SYNC_WIDTH_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_DISP_BACK_PORCH_0 +#define DC_DISP_BACK_PORCH_0 _MK_ADDR_CONST(0x408) +#define DC_DISP_BACK_PORCH_0_SECURE 0x0 +#define DC_DISP_BACK_PORCH_0_WORD_COUNT 0x1 +#define DC_DISP_BACK_PORCH_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_BACK_PORCH_0_RESET_MASK _MK_MASK_CONST(0x1fff1fff) +#define DC_DISP_BACK_PORCH_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_BACK_PORCH_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_BACK_PORCH_0_READ_MASK _MK_MASK_CONST(0x1fff1fff) +#define DC_DISP_BACK_PORCH_0_WRITE_MASK _MK_MASK_CONST(0x1fff1fff) +#define DC_DISP_BACK_PORCH_0_H_BACK_PORCH_SHIFT _MK_SHIFT_CONST(0) +#define DC_DISP_BACK_PORCH_0_H_BACK_PORCH_FIELD _MK_FIELD_CONST(0x1fff, DC_DISP_BACK_PORCH_0_H_BACK_PORCH_SHIFT) +#define DC_DISP_BACK_PORCH_0_H_BACK_PORCH_RANGE 12:0 +#define DC_DISP_BACK_PORCH_0_H_BACK_PORCH_WOFFSET 0x0 +#define DC_DISP_BACK_PORCH_0_H_BACK_PORCH_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_BACK_PORCH_0_H_BACK_PORCH_DEFAULT_MASK _MK_MASK_CONST(0x1fff) +#define DC_DISP_BACK_PORCH_0_H_BACK_PORCH_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_BACK_PORCH_0_H_BACK_PORCH_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_DISP_BACK_PORCH_0_V_BACK_PORCH_SHIFT _MK_SHIFT_CONST(16) +#define DC_DISP_BACK_PORCH_0_V_BACK_PORCH_FIELD _MK_FIELD_CONST(0x1fff, DC_DISP_BACK_PORCH_0_V_BACK_PORCH_SHIFT) +#define DC_DISP_BACK_PORCH_0_V_BACK_PORCH_RANGE 28:16 +#define DC_DISP_BACK_PORCH_0_V_BACK_PORCH_WOFFSET 0x0 +#define DC_DISP_BACK_PORCH_0_V_BACK_PORCH_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_BACK_PORCH_0_V_BACK_PORCH_DEFAULT_MASK _MK_MASK_CONST(0x1fff) +#define DC_DISP_BACK_PORCH_0_V_BACK_PORCH_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_BACK_PORCH_0_V_BACK_PORCH_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_DISP_DISP_ACTIVE_0 +#define DC_DISP_DISP_ACTIVE_0 _MK_ADDR_CONST(0x409) +#define DC_DISP_DISP_ACTIVE_0_SECURE 0x0 +#define DC_DISP_DISP_ACTIVE_0_WORD_COUNT 0x1 +#define DC_DISP_DISP_ACTIVE_0_RESET_VAL _MK_MASK_CONST(0x30003) +#define DC_DISP_DISP_ACTIVE_0_RESET_MASK _MK_MASK_CONST(0x1fff1fff) +#define DC_DISP_DISP_ACTIVE_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_DISP_ACTIVE_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_DISP_ACTIVE_0_READ_MASK _MK_MASK_CONST(0x1fff1fff) +#define DC_DISP_DISP_ACTIVE_0_WRITE_MASK _MK_MASK_CONST(0x1fff1fff) +#define DC_DISP_DISP_ACTIVE_0_H_DISP_ACTIVE_SHIFT _MK_SHIFT_CONST(0) +#define DC_DISP_DISP_ACTIVE_0_H_DISP_ACTIVE_FIELD _MK_FIELD_CONST(0x1fff, DC_DISP_DISP_ACTIVE_0_H_DISP_ACTIVE_SHIFT) +#define DC_DISP_DISP_ACTIVE_0_H_DISP_ACTIVE_RANGE 12:0 +#define DC_DISP_DISP_ACTIVE_0_H_DISP_ACTIVE_WOFFSET 0x0 +#define DC_DISP_DISP_ACTIVE_0_H_DISP_ACTIVE_DEFAULT _MK_MASK_CONST(0x3) +#define DC_DISP_DISP_ACTIVE_0_H_DISP_ACTIVE_DEFAULT_MASK _MK_MASK_CONST(0x1fff) +#define DC_DISP_DISP_ACTIVE_0_H_DISP_ACTIVE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_DISP_ACTIVE_0_H_DISP_ACTIVE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_DISP_DISP_ACTIVE_0_V_DISP_ACTIVE_SHIFT _MK_SHIFT_CONST(16) +#define DC_DISP_DISP_ACTIVE_0_V_DISP_ACTIVE_FIELD _MK_FIELD_CONST(0x1fff, DC_DISP_DISP_ACTIVE_0_V_DISP_ACTIVE_SHIFT) +#define DC_DISP_DISP_ACTIVE_0_V_DISP_ACTIVE_RANGE 28:16 +#define DC_DISP_DISP_ACTIVE_0_V_DISP_ACTIVE_WOFFSET 0x0 +#define DC_DISP_DISP_ACTIVE_0_V_DISP_ACTIVE_DEFAULT _MK_MASK_CONST(0x3) +#define DC_DISP_DISP_ACTIVE_0_V_DISP_ACTIVE_DEFAULT_MASK _MK_MASK_CONST(0x1fff) +#define DC_DISP_DISP_ACTIVE_0_V_DISP_ACTIVE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_DISP_ACTIVE_0_V_DISP_ACTIVE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_DISP_FRONT_PORCH_0 +#define DC_DISP_FRONT_PORCH_0 _MK_ADDR_CONST(0x40a) +#define DC_DISP_FRONT_PORCH_0_SECURE 0x0 +#define DC_DISP_FRONT_PORCH_0_WORD_COUNT 0x1 +#define DC_DISP_FRONT_PORCH_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_FRONT_PORCH_0_RESET_MASK _MK_MASK_CONST(0x1fff1fff) +#define DC_DISP_FRONT_PORCH_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_FRONT_PORCH_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_FRONT_PORCH_0_READ_MASK _MK_MASK_CONST(0x1fff1fff) +#define DC_DISP_FRONT_PORCH_0_WRITE_MASK _MK_MASK_CONST(0x1fff1fff) +#define DC_DISP_FRONT_PORCH_0_H_FRONT_PORCH_SHIFT _MK_SHIFT_CONST(0) +#define DC_DISP_FRONT_PORCH_0_H_FRONT_PORCH_FIELD _MK_FIELD_CONST(0x1fff, DC_DISP_FRONT_PORCH_0_H_FRONT_PORCH_SHIFT) +#define DC_DISP_FRONT_PORCH_0_H_FRONT_PORCH_RANGE 12:0 +#define DC_DISP_FRONT_PORCH_0_H_FRONT_PORCH_WOFFSET 0x0 +#define DC_DISP_FRONT_PORCH_0_H_FRONT_PORCH_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_FRONT_PORCH_0_H_FRONT_PORCH_DEFAULT_MASK _MK_MASK_CONST(0x1fff) +#define DC_DISP_FRONT_PORCH_0_H_FRONT_PORCH_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_FRONT_PORCH_0_H_FRONT_PORCH_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_DISP_FRONT_PORCH_0_V_FRONT_PORCH_SHIFT _MK_SHIFT_CONST(16) +#define DC_DISP_FRONT_PORCH_0_V_FRONT_PORCH_FIELD _MK_FIELD_CONST(0x1fff, DC_DISP_FRONT_PORCH_0_V_FRONT_PORCH_SHIFT) +#define DC_DISP_FRONT_PORCH_0_V_FRONT_PORCH_RANGE 28:16 +#define DC_DISP_FRONT_PORCH_0_V_FRONT_PORCH_WOFFSET 0x0 +#define DC_DISP_FRONT_PORCH_0_V_FRONT_PORCH_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_FRONT_PORCH_0_V_FRONT_PORCH_DEFAULT_MASK _MK_MASK_CONST(0x1fff) +#define DC_DISP_FRONT_PORCH_0_V_FRONT_PORCH_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_FRONT_PORCH_0_V_FRONT_PORCH_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_DISP_H_PULSE0_CONTROL_0 +#define DC_DISP_H_PULSE0_CONTROL_0 _MK_ADDR_CONST(0x40b) +#define DC_DISP_H_PULSE0_CONTROL_0_SECURE 0x0 +#define DC_DISP_H_PULSE0_CONTROL_0_WORD_COUNT 0x1 +#define DC_DISP_H_PULSE0_CONTROL_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_H_PULSE0_CONTROL_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_H_PULSE0_CONTROL_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_H_PULSE0_CONTROL_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_H_PULSE0_CONTROL_0_READ_MASK _MK_MASK_CONST(0xfd8) +#define DC_DISP_H_PULSE0_CONTROL_0_WRITE_MASK _MK_MASK_CONST(0xfd8) +#define DC_DISP_H_PULSE0_CONTROL_0_H_PULSE0_MODE_SHIFT _MK_SHIFT_CONST(3) +#define DC_DISP_H_PULSE0_CONTROL_0_H_PULSE0_MODE_FIELD _MK_FIELD_CONST(0x1, DC_DISP_H_PULSE0_CONTROL_0_H_PULSE0_MODE_SHIFT) +#define DC_DISP_H_PULSE0_CONTROL_0_H_PULSE0_MODE_RANGE 3:3 +#define DC_DISP_H_PULSE0_CONTROL_0_H_PULSE0_MODE_WOFFSET 0x0 +#define DC_DISP_H_PULSE0_CONTROL_0_H_PULSE0_MODE_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_H_PULSE0_CONTROL_0_H_PULSE0_MODE_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_H_PULSE0_CONTROL_0_H_PULSE0_MODE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_H_PULSE0_CONTROL_0_H_PULSE0_MODE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_H_PULSE0_CONTROL_0_H_PULSE0_MODE_NORMAL _MK_ENUM_CONST(0) +#define DC_DISP_H_PULSE0_CONTROL_0_H_PULSE0_MODE_ONE_CLOCK _MK_ENUM_CONST(1) + +#define DC_DISP_H_PULSE0_CONTROL_0_H_PULSE0_POLARITY_SHIFT _MK_SHIFT_CONST(4) +#define DC_DISP_H_PULSE0_CONTROL_0_H_PULSE0_POLARITY_FIELD _MK_FIELD_CONST(0x1, DC_DISP_H_PULSE0_CONTROL_0_H_PULSE0_POLARITY_SHIFT) +#define DC_DISP_H_PULSE0_CONTROL_0_H_PULSE0_POLARITY_RANGE 4:4 +#define DC_DISP_H_PULSE0_CONTROL_0_H_PULSE0_POLARITY_WOFFSET 0x0 +#define DC_DISP_H_PULSE0_CONTROL_0_H_PULSE0_POLARITY_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_H_PULSE0_CONTROL_0_H_PULSE0_POLARITY_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_H_PULSE0_CONTROL_0_H_PULSE0_POLARITY_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_H_PULSE0_CONTROL_0_H_PULSE0_POLARITY_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_H_PULSE0_CONTROL_0_H_PULSE0_POLARITY_HIGH _MK_ENUM_CONST(0) +#define DC_DISP_H_PULSE0_CONTROL_0_H_PULSE0_POLARITY_LOW _MK_ENUM_CONST(1) + +#define DC_DISP_H_PULSE0_CONTROL_0_H_PULSE0_V_QUAL_SHIFT _MK_SHIFT_CONST(6) +#define DC_DISP_H_PULSE0_CONTROL_0_H_PULSE0_V_QUAL_FIELD _MK_FIELD_CONST(0x3, DC_DISP_H_PULSE0_CONTROL_0_H_PULSE0_V_QUAL_SHIFT) +#define DC_DISP_H_PULSE0_CONTROL_0_H_PULSE0_V_QUAL_RANGE 7:6 +#define DC_DISP_H_PULSE0_CONTROL_0_H_PULSE0_V_QUAL_WOFFSET 0x0 +#define DC_DISP_H_PULSE0_CONTROL_0_H_PULSE0_V_QUAL_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_H_PULSE0_CONTROL_0_H_PULSE0_V_QUAL_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_H_PULSE0_CONTROL_0_H_PULSE0_V_QUAL_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_H_PULSE0_CONTROL_0_H_PULSE0_V_QUAL_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_H_PULSE0_CONTROL_0_H_PULSE0_V_QUAL_ALWAYS _MK_ENUM_CONST(0) +#define DC_DISP_H_PULSE0_CONTROL_0_H_PULSE0_V_QUAL_VACTIVE _MK_ENUM_CONST(2) +#define DC_DISP_H_PULSE0_CONTROL_0_H_PULSE0_V_QUAL_VACTIVE1 _MK_ENUM_CONST(3) + +#define DC_DISP_H_PULSE0_CONTROL_0_H_PULSE0_LAST_SHIFT _MK_SHIFT_CONST(8) +#define DC_DISP_H_PULSE0_CONTROL_0_H_PULSE0_LAST_FIELD _MK_FIELD_CONST(0xf, DC_DISP_H_PULSE0_CONTROL_0_H_PULSE0_LAST_SHIFT) +#define DC_DISP_H_PULSE0_CONTROL_0_H_PULSE0_LAST_RANGE 11:8 +#define DC_DISP_H_PULSE0_CONTROL_0_H_PULSE0_LAST_WOFFSET 0x0 +#define DC_DISP_H_PULSE0_CONTROL_0_H_PULSE0_LAST_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_H_PULSE0_CONTROL_0_H_PULSE0_LAST_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_H_PULSE0_CONTROL_0_H_PULSE0_LAST_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_H_PULSE0_CONTROL_0_H_PULSE0_LAST_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_H_PULSE0_CONTROL_0_H_PULSE0_LAST_START_A _MK_ENUM_CONST(0) +#define DC_DISP_H_PULSE0_CONTROL_0_H_PULSE0_LAST_END_A _MK_ENUM_CONST(1) +#define DC_DISP_H_PULSE0_CONTROL_0_H_PULSE0_LAST_START_B _MK_ENUM_CONST(2) +#define DC_DISP_H_PULSE0_CONTROL_0_H_PULSE0_LAST_END_B _MK_ENUM_CONST(3) +#define DC_DISP_H_PULSE0_CONTROL_0_H_PULSE0_LAST_START_C _MK_ENUM_CONST(4) +#define DC_DISP_H_PULSE0_CONTROL_0_H_PULSE0_LAST_END_C _MK_ENUM_CONST(5) +#define DC_DISP_H_PULSE0_CONTROL_0_H_PULSE0_LAST_START_D _MK_ENUM_CONST(6) +#define DC_DISP_H_PULSE0_CONTROL_0_H_PULSE0_LAST_END_D _MK_ENUM_CONST(7) + + +// Register DC_DISP_H_PULSE0_POSITION_A_0 +#define DC_DISP_H_PULSE0_POSITION_A_0 _MK_ADDR_CONST(0x40c) +#define DC_DISP_H_PULSE0_POSITION_A_0_SECURE 0x0 +#define DC_DISP_H_PULSE0_POSITION_A_0_WORD_COUNT 0x1 +#define DC_DISP_H_PULSE0_POSITION_A_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_H_PULSE0_POSITION_A_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_H_PULSE0_POSITION_A_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_H_PULSE0_POSITION_A_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_H_PULSE0_POSITION_A_0_READ_MASK _MK_MASK_CONST(0x1fff1fff) +#define DC_DISP_H_PULSE0_POSITION_A_0_WRITE_MASK _MK_MASK_CONST(0x1fff1fff) +#define DC_DISP_H_PULSE0_POSITION_A_0_H_PULSE0_START_A_SHIFT _MK_SHIFT_CONST(0) +#define DC_DISP_H_PULSE0_POSITION_A_0_H_PULSE0_START_A_FIELD _MK_FIELD_CONST(0x1fff, DC_DISP_H_PULSE0_POSITION_A_0_H_PULSE0_START_A_SHIFT) +#define DC_DISP_H_PULSE0_POSITION_A_0_H_PULSE0_START_A_RANGE 12:0 +#define DC_DISP_H_PULSE0_POSITION_A_0_H_PULSE0_START_A_WOFFSET 0x0 +#define DC_DISP_H_PULSE0_POSITION_A_0_H_PULSE0_START_A_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_H_PULSE0_POSITION_A_0_H_PULSE0_START_A_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_H_PULSE0_POSITION_A_0_H_PULSE0_START_A_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_H_PULSE0_POSITION_A_0_H_PULSE0_START_A_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_DISP_H_PULSE0_POSITION_A_0_H_PULSE0_END_A_SHIFT _MK_SHIFT_CONST(16) +#define DC_DISP_H_PULSE0_POSITION_A_0_H_PULSE0_END_A_FIELD _MK_FIELD_CONST(0x1fff, DC_DISP_H_PULSE0_POSITION_A_0_H_PULSE0_END_A_SHIFT) +#define DC_DISP_H_PULSE0_POSITION_A_0_H_PULSE0_END_A_RANGE 28:16 +#define DC_DISP_H_PULSE0_POSITION_A_0_H_PULSE0_END_A_WOFFSET 0x0 +#define DC_DISP_H_PULSE0_POSITION_A_0_H_PULSE0_END_A_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_H_PULSE0_POSITION_A_0_H_PULSE0_END_A_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_H_PULSE0_POSITION_A_0_H_PULSE0_END_A_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_H_PULSE0_POSITION_A_0_H_PULSE0_END_A_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_DISP_H_PULSE0_POSITION_B_0 +#define DC_DISP_H_PULSE0_POSITION_B_0 _MK_ADDR_CONST(0x40d) +#define DC_DISP_H_PULSE0_POSITION_B_0_SECURE 0x0 +#define DC_DISP_H_PULSE0_POSITION_B_0_WORD_COUNT 0x1 +#define DC_DISP_H_PULSE0_POSITION_B_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_H_PULSE0_POSITION_B_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_H_PULSE0_POSITION_B_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_H_PULSE0_POSITION_B_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_H_PULSE0_POSITION_B_0_READ_MASK _MK_MASK_CONST(0x1fff1fff) +#define DC_DISP_H_PULSE0_POSITION_B_0_WRITE_MASK _MK_MASK_CONST(0x1fff1fff) +#define DC_DISP_H_PULSE0_POSITION_B_0_H_PULSE0_START_B_SHIFT _MK_SHIFT_CONST(0) +#define DC_DISP_H_PULSE0_POSITION_B_0_H_PULSE0_START_B_FIELD _MK_FIELD_CONST(0x1fff, DC_DISP_H_PULSE0_POSITION_B_0_H_PULSE0_START_B_SHIFT) +#define DC_DISP_H_PULSE0_POSITION_B_0_H_PULSE0_START_B_RANGE 12:0 +#define DC_DISP_H_PULSE0_POSITION_B_0_H_PULSE0_START_B_WOFFSET 0x0 +#define DC_DISP_H_PULSE0_POSITION_B_0_H_PULSE0_START_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_H_PULSE0_POSITION_B_0_H_PULSE0_START_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_H_PULSE0_POSITION_B_0_H_PULSE0_START_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_H_PULSE0_POSITION_B_0_H_PULSE0_START_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_DISP_H_PULSE0_POSITION_B_0_H_PULSE0_END_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_DISP_H_PULSE0_POSITION_B_0_H_PULSE0_END_B_FIELD _MK_FIELD_CONST(0x1fff, DC_DISP_H_PULSE0_POSITION_B_0_H_PULSE0_END_B_SHIFT) +#define DC_DISP_H_PULSE0_POSITION_B_0_H_PULSE0_END_B_RANGE 28:16 +#define DC_DISP_H_PULSE0_POSITION_B_0_H_PULSE0_END_B_WOFFSET 0x0 +#define DC_DISP_H_PULSE0_POSITION_B_0_H_PULSE0_END_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_H_PULSE0_POSITION_B_0_H_PULSE0_END_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_H_PULSE0_POSITION_B_0_H_PULSE0_END_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_H_PULSE0_POSITION_B_0_H_PULSE0_END_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_DISP_H_PULSE0_POSITION_C_0 +#define DC_DISP_H_PULSE0_POSITION_C_0 _MK_ADDR_CONST(0x40e) +#define DC_DISP_H_PULSE0_POSITION_C_0_SECURE 0x0 +#define DC_DISP_H_PULSE0_POSITION_C_0_WORD_COUNT 0x1 +#define DC_DISP_H_PULSE0_POSITION_C_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_H_PULSE0_POSITION_C_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_H_PULSE0_POSITION_C_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_H_PULSE0_POSITION_C_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_H_PULSE0_POSITION_C_0_READ_MASK _MK_MASK_CONST(0x1fff1fff) +#define DC_DISP_H_PULSE0_POSITION_C_0_WRITE_MASK _MK_MASK_CONST(0x1fff1fff) +#define DC_DISP_H_PULSE0_POSITION_C_0_H_PULSE0_START_C_SHIFT _MK_SHIFT_CONST(0) +#define DC_DISP_H_PULSE0_POSITION_C_0_H_PULSE0_START_C_FIELD _MK_FIELD_CONST(0x1fff, DC_DISP_H_PULSE0_POSITION_C_0_H_PULSE0_START_C_SHIFT) +#define DC_DISP_H_PULSE0_POSITION_C_0_H_PULSE0_START_C_RANGE 12:0 +#define DC_DISP_H_PULSE0_POSITION_C_0_H_PULSE0_START_C_WOFFSET 0x0 +#define DC_DISP_H_PULSE0_POSITION_C_0_H_PULSE0_START_C_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_H_PULSE0_POSITION_C_0_H_PULSE0_START_C_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_H_PULSE0_POSITION_C_0_H_PULSE0_START_C_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_H_PULSE0_POSITION_C_0_H_PULSE0_START_C_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_DISP_H_PULSE0_POSITION_C_0_H_PULSE0_END_C_SHIFT _MK_SHIFT_CONST(16) +#define DC_DISP_H_PULSE0_POSITION_C_0_H_PULSE0_END_C_FIELD _MK_FIELD_CONST(0x1fff, DC_DISP_H_PULSE0_POSITION_C_0_H_PULSE0_END_C_SHIFT) +#define DC_DISP_H_PULSE0_POSITION_C_0_H_PULSE0_END_C_RANGE 28:16 +#define DC_DISP_H_PULSE0_POSITION_C_0_H_PULSE0_END_C_WOFFSET 0x0 +#define DC_DISP_H_PULSE0_POSITION_C_0_H_PULSE0_END_C_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_H_PULSE0_POSITION_C_0_H_PULSE0_END_C_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_H_PULSE0_POSITION_C_0_H_PULSE0_END_C_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_H_PULSE0_POSITION_C_0_H_PULSE0_END_C_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_DISP_H_PULSE0_POSITION_D_0 +#define DC_DISP_H_PULSE0_POSITION_D_0 _MK_ADDR_CONST(0x40f) +#define DC_DISP_H_PULSE0_POSITION_D_0_SECURE 0x0 +#define DC_DISP_H_PULSE0_POSITION_D_0_WORD_COUNT 0x1 +#define DC_DISP_H_PULSE0_POSITION_D_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_H_PULSE0_POSITION_D_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_H_PULSE0_POSITION_D_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_H_PULSE0_POSITION_D_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_H_PULSE0_POSITION_D_0_READ_MASK _MK_MASK_CONST(0x1fff1fff) +#define DC_DISP_H_PULSE0_POSITION_D_0_WRITE_MASK _MK_MASK_CONST(0x1fff1fff) +#define DC_DISP_H_PULSE0_POSITION_D_0_H_PULSE0_START_D_SHIFT _MK_SHIFT_CONST(0) +#define DC_DISP_H_PULSE0_POSITION_D_0_H_PULSE0_START_D_FIELD _MK_FIELD_CONST(0x1fff, DC_DISP_H_PULSE0_POSITION_D_0_H_PULSE0_START_D_SHIFT) +#define DC_DISP_H_PULSE0_POSITION_D_0_H_PULSE0_START_D_RANGE 12:0 +#define DC_DISP_H_PULSE0_POSITION_D_0_H_PULSE0_START_D_WOFFSET 0x0 +#define DC_DISP_H_PULSE0_POSITION_D_0_H_PULSE0_START_D_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_H_PULSE0_POSITION_D_0_H_PULSE0_START_D_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_H_PULSE0_POSITION_D_0_H_PULSE0_START_D_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_H_PULSE0_POSITION_D_0_H_PULSE0_START_D_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_DISP_H_PULSE0_POSITION_D_0_H_PULSE0_END_D_SHIFT _MK_SHIFT_CONST(16) +#define DC_DISP_H_PULSE0_POSITION_D_0_H_PULSE0_END_D_FIELD _MK_FIELD_CONST(0x1fff, DC_DISP_H_PULSE0_POSITION_D_0_H_PULSE0_END_D_SHIFT) +#define DC_DISP_H_PULSE0_POSITION_D_0_H_PULSE0_END_D_RANGE 28:16 +#define DC_DISP_H_PULSE0_POSITION_D_0_H_PULSE0_END_D_WOFFSET 0x0 +#define DC_DISP_H_PULSE0_POSITION_D_0_H_PULSE0_END_D_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_H_PULSE0_POSITION_D_0_H_PULSE0_END_D_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_H_PULSE0_POSITION_D_0_H_PULSE0_END_D_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_H_PULSE0_POSITION_D_0_H_PULSE0_END_D_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_DISP_H_PULSE1_CONTROL_0 +#define DC_DISP_H_PULSE1_CONTROL_0 _MK_ADDR_CONST(0x410) +#define DC_DISP_H_PULSE1_CONTROL_0_SECURE 0x0 +#define DC_DISP_H_PULSE1_CONTROL_0_WORD_COUNT 0x1 +#define DC_DISP_H_PULSE1_CONTROL_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_H_PULSE1_CONTROL_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_H_PULSE1_CONTROL_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_H_PULSE1_CONTROL_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_H_PULSE1_CONTROL_0_READ_MASK _MK_MASK_CONST(0xfd8) +#define DC_DISP_H_PULSE1_CONTROL_0_WRITE_MASK _MK_MASK_CONST(0xfd8) +#define DC_DISP_H_PULSE1_CONTROL_0_H_PULSE1_MODE_SHIFT _MK_SHIFT_CONST(3) +#define DC_DISP_H_PULSE1_CONTROL_0_H_PULSE1_MODE_FIELD _MK_FIELD_CONST(0x1, DC_DISP_H_PULSE1_CONTROL_0_H_PULSE1_MODE_SHIFT) +#define DC_DISP_H_PULSE1_CONTROL_0_H_PULSE1_MODE_RANGE 3:3 +#define DC_DISP_H_PULSE1_CONTROL_0_H_PULSE1_MODE_WOFFSET 0x0 +#define DC_DISP_H_PULSE1_CONTROL_0_H_PULSE1_MODE_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_H_PULSE1_CONTROL_0_H_PULSE1_MODE_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_H_PULSE1_CONTROL_0_H_PULSE1_MODE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_H_PULSE1_CONTROL_0_H_PULSE1_MODE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_H_PULSE1_CONTROL_0_H_PULSE1_MODE_NORMAL _MK_ENUM_CONST(0) +#define DC_DISP_H_PULSE1_CONTROL_0_H_PULSE1_MODE_ONE_CLOCK _MK_ENUM_CONST(1) + +#define DC_DISP_H_PULSE1_CONTROL_0_H_PULSE1_POLARITY_SHIFT _MK_SHIFT_CONST(4) +#define DC_DISP_H_PULSE1_CONTROL_0_H_PULSE1_POLARITY_FIELD _MK_FIELD_CONST(0x1, DC_DISP_H_PULSE1_CONTROL_0_H_PULSE1_POLARITY_SHIFT) +#define DC_DISP_H_PULSE1_CONTROL_0_H_PULSE1_POLARITY_RANGE 4:4 +#define DC_DISP_H_PULSE1_CONTROL_0_H_PULSE1_POLARITY_WOFFSET 0x0 +#define DC_DISP_H_PULSE1_CONTROL_0_H_PULSE1_POLARITY_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_H_PULSE1_CONTROL_0_H_PULSE1_POLARITY_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_H_PULSE1_CONTROL_0_H_PULSE1_POLARITY_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_H_PULSE1_CONTROL_0_H_PULSE1_POLARITY_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_H_PULSE1_CONTROL_0_H_PULSE1_POLARITY_HIGH _MK_ENUM_CONST(0) +#define DC_DISP_H_PULSE1_CONTROL_0_H_PULSE1_POLARITY_LOW _MK_ENUM_CONST(1) + +#define DC_DISP_H_PULSE1_CONTROL_0_H_PULSE1_V_QUAL_SHIFT _MK_SHIFT_CONST(6) +#define DC_DISP_H_PULSE1_CONTROL_0_H_PULSE1_V_QUAL_FIELD _MK_FIELD_CONST(0x3, DC_DISP_H_PULSE1_CONTROL_0_H_PULSE1_V_QUAL_SHIFT) +#define DC_DISP_H_PULSE1_CONTROL_0_H_PULSE1_V_QUAL_RANGE 7:6 +#define DC_DISP_H_PULSE1_CONTROL_0_H_PULSE1_V_QUAL_WOFFSET 0x0 +#define DC_DISP_H_PULSE1_CONTROL_0_H_PULSE1_V_QUAL_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_H_PULSE1_CONTROL_0_H_PULSE1_V_QUAL_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_H_PULSE1_CONTROL_0_H_PULSE1_V_QUAL_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_H_PULSE1_CONTROL_0_H_PULSE1_V_QUAL_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_H_PULSE1_CONTROL_0_H_PULSE1_V_QUAL_ALWAYS _MK_ENUM_CONST(0) +#define DC_DISP_H_PULSE1_CONTROL_0_H_PULSE1_V_QUAL_VACTIVE _MK_ENUM_CONST(2) +#define DC_DISP_H_PULSE1_CONTROL_0_H_PULSE1_V_QUAL_VACTIVE1 _MK_ENUM_CONST(3) + +#define DC_DISP_H_PULSE1_CONTROL_0_H_PULSE1_LAST_SHIFT _MK_SHIFT_CONST(8) +#define DC_DISP_H_PULSE1_CONTROL_0_H_PULSE1_LAST_FIELD _MK_FIELD_CONST(0xf, DC_DISP_H_PULSE1_CONTROL_0_H_PULSE1_LAST_SHIFT) +#define DC_DISP_H_PULSE1_CONTROL_0_H_PULSE1_LAST_RANGE 11:8 +#define DC_DISP_H_PULSE1_CONTROL_0_H_PULSE1_LAST_WOFFSET 0x0 +#define DC_DISP_H_PULSE1_CONTROL_0_H_PULSE1_LAST_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_H_PULSE1_CONTROL_0_H_PULSE1_LAST_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_H_PULSE1_CONTROL_0_H_PULSE1_LAST_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_H_PULSE1_CONTROL_0_H_PULSE1_LAST_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_H_PULSE1_CONTROL_0_H_PULSE1_LAST_START_A _MK_ENUM_CONST(0) +#define DC_DISP_H_PULSE1_CONTROL_0_H_PULSE1_LAST_END_A _MK_ENUM_CONST(1) +#define DC_DISP_H_PULSE1_CONTROL_0_H_PULSE1_LAST_START_B _MK_ENUM_CONST(2) +#define DC_DISP_H_PULSE1_CONTROL_0_H_PULSE1_LAST_END_B _MK_ENUM_CONST(3) +#define DC_DISP_H_PULSE1_CONTROL_0_H_PULSE1_LAST_START_C _MK_ENUM_CONST(4) +#define DC_DISP_H_PULSE1_CONTROL_0_H_PULSE1_LAST_END_C _MK_ENUM_CONST(5) +#define DC_DISP_H_PULSE1_CONTROL_0_H_PULSE1_LAST_START_D _MK_ENUM_CONST(6) +#define DC_DISP_H_PULSE1_CONTROL_0_H_PULSE1_LAST_END_D _MK_ENUM_CONST(7) + + +// Register DC_DISP_H_PULSE1_POSITION_A_0 +#define DC_DISP_H_PULSE1_POSITION_A_0 _MK_ADDR_CONST(0x411) +#define DC_DISP_H_PULSE1_POSITION_A_0_SECURE 0x0 +#define DC_DISP_H_PULSE1_POSITION_A_0_WORD_COUNT 0x1 +#define DC_DISP_H_PULSE1_POSITION_A_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_H_PULSE1_POSITION_A_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_H_PULSE1_POSITION_A_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_H_PULSE1_POSITION_A_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_H_PULSE1_POSITION_A_0_READ_MASK _MK_MASK_CONST(0x1fff1fff) +#define DC_DISP_H_PULSE1_POSITION_A_0_WRITE_MASK _MK_MASK_CONST(0x1fff1fff) +#define DC_DISP_H_PULSE1_POSITION_A_0_H_PULSE1_START_A_SHIFT _MK_SHIFT_CONST(0) +#define DC_DISP_H_PULSE1_POSITION_A_0_H_PULSE1_START_A_FIELD _MK_FIELD_CONST(0x1fff, DC_DISP_H_PULSE1_POSITION_A_0_H_PULSE1_START_A_SHIFT) +#define DC_DISP_H_PULSE1_POSITION_A_0_H_PULSE1_START_A_RANGE 12:0 +#define DC_DISP_H_PULSE1_POSITION_A_0_H_PULSE1_START_A_WOFFSET 0x0 +#define DC_DISP_H_PULSE1_POSITION_A_0_H_PULSE1_START_A_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_H_PULSE1_POSITION_A_0_H_PULSE1_START_A_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_H_PULSE1_POSITION_A_0_H_PULSE1_START_A_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_H_PULSE1_POSITION_A_0_H_PULSE1_START_A_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_DISP_H_PULSE1_POSITION_A_0_H_PULSE1_END_A_SHIFT _MK_SHIFT_CONST(16) +#define DC_DISP_H_PULSE1_POSITION_A_0_H_PULSE1_END_A_FIELD _MK_FIELD_CONST(0x1fff, DC_DISP_H_PULSE1_POSITION_A_0_H_PULSE1_END_A_SHIFT) +#define DC_DISP_H_PULSE1_POSITION_A_0_H_PULSE1_END_A_RANGE 28:16 +#define DC_DISP_H_PULSE1_POSITION_A_0_H_PULSE1_END_A_WOFFSET 0x0 +#define DC_DISP_H_PULSE1_POSITION_A_0_H_PULSE1_END_A_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_H_PULSE1_POSITION_A_0_H_PULSE1_END_A_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_H_PULSE1_POSITION_A_0_H_PULSE1_END_A_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_H_PULSE1_POSITION_A_0_H_PULSE1_END_A_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_DISP_H_PULSE1_POSITION_B_0 +#define DC_DISP_H_PULSE1_POSITION_B_0 _MK_ADDR_CONST(0x412) +#define DC_DISP_H_PULSE1_POSITION_B_0_SECURE 0x0 +#define DC_DISP_H_PULSE1_POSITION_B_0_WORD_COUNT 0x1 +#define DC_DISP_H_PULSE1_POSITION_B_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_H_PULSE1_POSITION_B_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_H_PULSE1_POSITION_B_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_H_PULSE1_POSITION_B_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_H_PULSE1_POSITION_B_0_READ_MASK _MK_MASK_CONST(0x1fff1fff) +#define DC_DISP_H_PULSE1_POSITION_B_0_WRITE_MASK _MK_MASK_CONST(0x1fff1fff) +#define DC_DISP_H_PULSE1_POSITION_B_0_H_PULSE1_START_B_SHIFT _MK_SHIFT_CONST(0) +#define DC_DISP_H_PULSE1_POSITION_B_0_H_PULSE1_START_B_FIELD _MK_FIELD_CONST(0x1fff, DC_DISP_H_PULSE1_POSITION_B_0_H_PULSE1_START_B_SHIFT) +#define DC_DISP_H_PULSE1_POSITION_B_0_H_PULSE1_START_B_RANGE 12:0 +#define DC_DISP_H_PULSE1_POSITION_B_0_H_PULSE1_START_B_WOFFSET 0x0 +#define DC_DISP_H_PULSE1_POSITION_B_0_H_PULSE1_START_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_H_PULSE1_POSITION_B_0_H_PULSE1_START_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_H_PULSE1_POSITION_B_0_H_PULSE1_START_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_H_PULSE1_POSITION_B_0_H_PULSE1_START_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_DISP_H_PULSE1_POSITION_B_0_H_PULSE1_END_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_DISP_H_PULSE1_POSITION_B_0_H_PULSE1_END_B_FIELD _MK_FIELD_CONST(0x1fff, DC_DISP_H_PULSE1_POSITION_B_0_H_PULSE1_END_B_SHIFT) +#define DC_DISP_H_PULSE1_POSITION_B_0_H_PULSE1_END_B_RANGE 28:16 +#define DC_DISP_H_PULSE1_POSITION_B_0_H_PULSE1_END_B_WOFFSET 0x0 +#define DC_DISP_H_PULSE1_POSITION_B_0_H_PULSE1_END_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_H_PULSE1_POSITION_B_0_H_PULSE1_END_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_H_PULSE1_POSITION_B_0_H_PULSE1_END_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_H_PULSE1_POSITION_B_0_H_PULSE1_END_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_DISP_H_PULSE1_POSITION_C_0 +#define DC_DISP_H_PULSE1_POSITION_C_0 _MK_ADDR_CONST(0x413) +#define DC_DISP_H_PULSE1_POSITION_C_0_SECURE 0x0 +#define DC_DISP_H_PULSE1_POSITION_C_0_WORD_COUNT 0x1 +#define DC_DISP_H_PULSE1_POSITION_C_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_H_PULSE1_POSITION_C_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_H_PULSE1_POSITION_C_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_H_PULSE1_POSITION_C_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_H_PULSE1_POSITION_C_0_READ_MASK _MK_MASK_CONST(0x1fff1fff) +#define DC_DISP_H_PULSE1_POSITION_C_0_WRITE_MASK _MK_MASK_CONST(0x1fff1fff) +#define DC_DISP_H_PULSE1_POSITION_C_0_H_PULSE1_START_C_SHIFT _MK_SHIFT_CONST(0) +#define DC_DISP_H_PULSE1_POSITION_C_0_H_PULSE1_START_C_FIELD _MK_FIELD_CONST(0x1fff, DC_DISP_H_PULSE1_POSITION_C_0_H_PULSE1_START_C_SHIFT) +#define DC_DISP_H_PULSE1_POSITION_C_0_H_PULSE1_START_C_RANGE 12:0 +#define DC_DISP_H_PULSE1_POSITION_C_0_H_PULSE1_START_C_WOFFSET 0x0 +#define DC_DISP_H_PULSE1_POSITION_C_0_H_PULSE1_START_C_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_H_PULSE1_POSITION_C_0_H_PULSE1_START_C_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_H_PULSE1_POSITION_C_0_H_PULSE1_START_C_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_H_PULSE1_POSITION_C_0_H_PULSE1_START_C_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_DISP_H_PULSE1_POSITION_C_0_H_PULSE1_END_C_SHIFT _MK_SHIFT_CONST(16) +#define DC_DISP_H_PULSE1_POSITION_C_0_H_PULSE1_END_C_FIELD _MK_FIELD_CONST(0x1fff, DC_DISP_H_PULSE1_POSITION_C_0_H_PULSE1_END_C_SHIFT) +#define DC_DISP_H_PULSE1_POSITION_C_0_H_PULSE1_END_C_RANGE 28:16 +#define DC_DISP_H_PULSE1_POSITION_C_0_H_PULSE1_END_C_WOFFSET 0x0 +#define DC_DISP_H_PULSE1_POSITION_C_0_H_PULSE1_END_C_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_H_PULSE1_POSITION_C_0_H_PULSE1_END_C_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_H_PULSE1_POSITION_C_0_H_PULSE1_END_C_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_H_PULSE1_POSITION_C_0_H_PULSE1_END_C_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_DISP_H_PULSE1_POSITION_D_0 +#define DC_DISP_H_PULSE1_POSITION_D_0 _MK_ADDR_CONST(0x414) +#define DC_DISP_H_PULSE1_POSITION_D_0_SECURE 0x0 +#define DC_DISP_H_PULSE1_POSITION_D_0_WORD_COUNT 0x1 +#define DC_DISP_H_PULSE1_POSITION_D_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_H_PULSE1_POSITION_D_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_H_PULSE1_POSITION_D_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_H_PULSE1_POSITION_D_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_H_PULSE1_POSITION_D_0_READ_MASK _MK_MASK_CONST(0x1fff1fff) +#define DC_DISP_H_PULSE1_POSITION_D_0_WRITE_MASK _MK_MASK_CONST(0x1fff1fff) +#define DC_DISP_H_PULSE1_POSITION_D_0_H_PULSE1_START_D_SHIFT _MK_SHIFT_CONST(0) +#define DC_DISP_H_PULSE1_POSITION_D_0_H_PULSE1_START_D_FIELD _MK_FIELD_CONST(0x1fff, DC_DISP_H_PULSE1_POSITION_D_0_H_PULSE1_START_D_SHIFT) +#define DC_DISP_H_PULSE1_POSITION_D_0_H_PULSE1_START_D_RANGE 12:0 +#define DC_DISP_H_PULSE1_POSITION_D_0_H_PULSE1_START_D_WOFFSET 0x0 +#define DC_DISP_H_PULSE1_POSITION_D_0_H_PULSE1_START_D_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_H_PULSE1_POSITION_D_0_H_PULSE1_START_D_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_H_PULSE1_POSITION_D_0_H_PULSE1_START_D_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_H_PULSE1_POSITION_D_0_H_PULSE1_START_D_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_DISP_H_PULSE1_POSITION_D_0_H_PULSE1_END_D_SHIFT _MK_SHIFT_CONST(16) +#define DC_DISP_H_PULSE1_POSITION_D_0_H_PULSE1_END_D_FIELD _MK_FIELD_CONST(0x1fff, DC_DISP_H_PULSE1_POSITION_D_0_H_PULSE1_END_D_SHIFT) +#define DC_DISP_H_PULSE1_POSITION_D_0_H_PULSE1_END_D_RANGE 28:16 +#define DC_DISP_H_PULSE1_POSITION_D_0_H_PULSE1_END_D_WOFFSET 0x0 +#define DC_DISP_H_PULSE1_POSITION_D_0_H_PULSE1_END_D_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_H_PULSE1_POSITION_D_0_H_PULSE1_END_D_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_H_PULSE1_POSITION_D_0_H_PULSE1_END_D_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_H_PULSE1_POSITION_D_0_H_PULSE1_END_D_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_DISP_H_PULSE2_CONTROL_0 +#define DC_DISP_H_PULSE2_CONTROL_0 _MK_ADDR_CONST(0x415) +#define DC_DISP_H_PULSE2_CONTROL_0_SECURE 0x0 +#define DC_DISP_H_PULSE2_CONTROL_0_WORD_COUNT 0x1 +#define DC_DISP_H_PULSE2_CONTROL_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_H_PULSE2_CONTROL_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_H_PULSE2_CONTROL_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_H_PULSE2_CONTROL_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_H_PULSE2_CONTROL_0_READ_MASK _MK_MASK_CONST(0xfd8) +#define DC_DISP_H_PULSE2_CONTROL_0_WRITE_MASK _MK_MASK_CONST(0xfd8) +#define DC_DISP_H_PULSE2_CONTROL_0_H_PULSE2_MODE_SHIFT _MK_SHIFT_CONST(3) +#define DC_DISP_H_PULSE2_CONTROL_0_H_PULSE2_MODE_FIELD _MK_FIELD_CONST(0x1, DC_DISP_H_PULSE2_CONTROL_0_H_PULSE2_MODE_SHIFT) +#define DC_DISP_H_PULSE2_CONTROL_0_H_PULSE2_MODE_RANGE 3:3 +#define DC_DISP_H_PULSE2_CONTROL_0_H_PULSE2_MODE_WOFFSET 0x0 +#define DC_DISP_H_PULSE2_CONTROL_0_H_PULSE2_MODE_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_H_PULSE2_CONTROL_0_H_PULSE2_MODE_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_H_PULSE2_CONTROL_0_H_PULSE2_MODE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_H_PULSE2_CONTROL_0_H_PULSE2_MODE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_H_PULSE2_CONTROL_0_H_PULSE2_MODE_NORMAL _MK_ENUM_CONST(0) +#define DC_DISP_H_PULSE2_CONTROL_0_H_PULSE2_MODE_ONE_CLOCK _MK_ENUM_CONST(1) + +#define DC_DISP_H_PULSE2_CONTROL_0_H_PULSE2_POLARITY_SHIFT _MK_SHIFT_CONST(4) +#define DC_DISP_H_PULSE2_CONTROL_0_H_PULSE2_POLARITY_FIELD _MK_FIELD_CONST(0x1, DC_DISP_H_PULSE2_CONTROL_0_H_PULSE2_POLARITY_SHIFT) +#define DC_DISP_H_PULSE2_CONTROL_0_H_PULSE2_POLARITY_RANGE 4:4 +#define DC_DISP_H_PULSE2_CONTROL_0_H_PULSE2_POLARITY_WOFFSET 0x0 +#define DC_DISP_H_PULSE2_CONTROL_0_H_PULSE2_POLARITY_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_H_PULSE2_CONTROL_0_H_PULSE2_POLARITY_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_H_PULSE2_CONTROL_0_H_PULSE2_POLARITY_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_H_PULSE2_CONTROL_0_H_PULSE2_POLARITY_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_H_PULSE2_CONTROL_0_H_PULSE2_POLARITY_HIGH _MK_ENUM_CONST(0) +#define DC_DISP_H_PULSE2_CONTROL_0_H_PULSE2_POLARITY_LOW _MK_ENUM_CONST(1) + +#define DC_DISP_H_PULSE2_CONTROL_0_H_PULSE2_V_QUAL_SHIFT _MK_SHIFT_CONST(6) +#define DC_DISP_H_PULSE2_CONTROL_0_H_PULSE2_V_QUAL_FIELD _MK_FIELD_CONST(0x3, DC_DISP_H_PULSE2_CONTROL_0_H_PULSE2_V_QUAL_SHIFT) +#define DC_DISP_H_PULSE2_CONTROL_0_H_PULSE2_V_QUAL_RANGE 7:6 +#define DC_DISP_H_PULSE2_CONTROL_0_H_PULSE2_V_QUAL_WOFFSET 0x0 +#define DC_DISP_H_PULSE2_CONTROL_0_H_PULSE2_V_QUAL_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_H_PULSE2_CONTROL_0_H_PULSE2_V_QUAL_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_H_PULSE2_CONTROL_0_H_PULSE2_V_QUAL_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_H_PULSE2_CONTROL_0_H_PULSE2_V_QUAL_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_H_PULSE2_CONTROL_0_H_PULSE2_V_QUAL_ALWAYS _MK_ENUM_CONST(0) +#define DC_DISP_H_PULSE2_CONTROL_0_H_PULSE2_V_QUAL_VACTIVE _MK_ENUM_CONST(2) +#define DC_DISP_H_PULSE2_CONTROL_0_H_PULSE2_V_QUAL_VACTIVE1 _MK_ENUM_CONST(3) + +#define DC_DISP_H_PULSE2_CONTROL_0_H_PULSE2_LAST_SHIFT _MK_SHIFT_CONST(8) +#define DC_DISP_H_PULSE2_CONTROL_0_H_PULSE2_LAST_FIELD _MK_FIELD_CONST(0xf, DC_DISP_H_PULSE2_CONTROL_0_H_PULSE2_LAST_SHIFT) +#define DC_DISP_H_PULSE2_CONTROL_0_H_PULSE2_LAST_RANGE 11:8 +#define DC_DISP_H_PULSE2_CONTROL_0_H_PULSE2_LAST_WOFFSET 0x0 +#define DC_DISP_H_PULSE2_CONTROL_0_H_PULSE2_LAST_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_H_PULSE2_CONTROL_0_H_PULSE2_LAST_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_H_PULSE2_CONTROL_0_H_PULSE2_LAST_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_H_PULSE2_CONTROL_0_H_PULSE2_LAST_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_H_PULSE2_CONTROL_0_H_PULSE2_LAST_START_A _MK_ENUM_CONST(0) +#define DC_DISP_H_PULSE2_CONTROL_0_H_PULSE2_LAST_END_A _MK_ENUM_CONST(1) +#define DC_DISP_H_PULSE2_CONTROL_0_H_PULSE2_LAST_START_B _MK_ENUM_CONST(2) +#define DC_DISP_H_PULSE2_CONTROL_0_H_PULSE2_LAST_END_B _MK_ENUM_CONST(3) +#define DC_DISP_H_PULSE2_CONTROL_0_H_PULSE2_LAST_START_C _MK_ENUM_CONST(4) +#define DC_DISP_H_PULSE2_CONTROL_0_H_PULSE2_LAST_END_C _MK_ENUM_CONST(5) +#define DC_DISP_H_PULSE2_CONTROL_0_H_PULSE2_LAST_START_D _MK_ENUM_CONST(6) +#define DC_DISP_H_PULSE2_CONTROL_0_H_PULSE2_LAST_END_D _MK_ENUM_CONST(7) + + +// Register DC_DISP_H_PULSE2_POSITION_A_0 +#define DC_DISP_H_PULSE2_POSITION_A_0 _MK_ADDR_CONST(0x416) +#define DC_DISP_H_PULSE2_POSITION_A_0_SECURE 0x0 +#define DC_DISP_H_PULSE2_POSITION_A_0_WORD_COUNT 0x1 +#define DC_DISP_H_PULSE2_POSITION_A_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_H_PULSE2_POSITION_A_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_H_PULSE2_POSITION_A_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_H_PULSE2_POSITION_A_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_H_PULSE2_POSITION_A_0_READ_MASK _MK_MASK_CONST(0x1fff1fff) +#define DC_DISP_H_PULSE2_POSITION_A_0_WRITE_MASK _MK_MASK_CONST(0x1fff1fff) +#define DC_DISP_H_PULSE2_POSITION_A_0_H_PULSE2_START_A_SHIFT _MK_SHIFT_CONST(0) +#define DC_DISP_H_PULSE2_POSITION_A_0_H_PULSE2_START_A_FIELD _MK_FIELD_CONST(0x1fff, DC_DISP_H_PULSE2_POSITION_A_0_H_PULSE2_START_A_SHIFT) +#define DC_DISP_H_PULSE2_POSITION_A_0_H_PULSE2_START_A_RANGE 12:0 +#define DC_DISP_H_PULSE2_POSITION_A_0_H_PULSE2_START_A_WOFFSET 0x0 +#define DC_DISP_H_PULSE2_POSITION_A_0_H_PULSE2_START_A_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_H_PULSE2_POSITION_A_0_H_PULSE2_START_A_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_H_PULSE2_POSITION_A_0_H_PULSE2_START_A_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_H_PULSE2_POSITION_A_0_H_PULSE2_START_A_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_DISP_H_PULSE2_POSITION_A_0_H_PULSE2_END_A_SHIFT _MK_SHIFT_CONST(16) +#define DC_DISP_H_PULSE2_POSITION_A_0_H_PULSE2_END_A_FIELD _MK_FIELD_CONST(0x1fff, DC_DISP_H_PULSE2_POSITION_A_0_H_PULSE2_END_A_SHIFT) +#define DC_DISP_H_PULSE2_POSITION_A_0_H_PULSE2_END_A_RANGE 28:16 +#define DC_DISP_H_PULSE2_POSITION_A_0_H_PULSE2_END_A_WOFFSET 0x0 +#define DC_DISP_H_PULSE2_POSITION_A_0_H_PULSE2_END_A_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_H_PULSE2_POSITION_A_0_H_PULSE2_END_A_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_H_PULSE2_POSITION_A_0_H_PULSE2_END_A_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_H_PULSE2_POSITION_A_0_H_PULSE2_END_A_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_DISP_H_PULSE2_POSITION_B_0 +#define DC_DISP_H_PULSE2_POSITION_B_0 _MK_ADDR_CONST(0x417) +#define DC_DISP_H_PULSE2_POSITION_B_0_SECURE 0x0 +#define DC_DISP_H_PULSE2_POSITION_B_0_WORD_COUNT 0x1 +#define DC_DISP_H_PULSE2_POSITION_B_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_H_PULSE2_POSITION_B_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_H_PULSE2_POSITION_B_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_H_PULSE2_POSITION_B_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_H_PULSE2_POSITION_B_0_READ_MASK _MK_MASK_CONST(0x1fff1fff) +#define DC_DISP_H_PULSE2_POSITION_B_0_WRITE_MASK _MK_MASK_CONST(0x1fff1fff) +#define DC_DISP_H_PULSE2_POSITION_B_0_H_PULSE2_START_B_SHIFT _MK_SHIFT_CONST(0) +#define DC_DISP_H_PULSE2_POSITION_B_0_H_PULSE2_START_B_FIELD _MK_FIELD_CONST(0x1fff, DC_DISP_H_PULSE2_POSITION_B_0_H_PULSE2_START_B_SHIFT) +#define DC_DISP_H_PULSE2_POSITION_B_0_H_PULSE2_START_B_RANGE 12:0 +#define DC_DISP_H_PULSE2_POSITION_B_0_H_PULSE2_START_B_WOFFSET 0x0 +#define DC_DISP_H_PULSE2_POSITION_B_0_H_PULSE2_START_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_H_PULSE2_POSITION_B_0_H_PULSE2_START_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_H_PULSE2_POSITION_B_0_H_PULSE2_START_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_H_PULSE2_POSITION_B_0_H_PULSE2_START_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_DISP_H_PULSE2_POSITION_B_0_H_PULSE2_END_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_DISP_H_PULSE2_POSITION_B_0_H_PULSE2_END_B_FIELD _MK_FIELD_CONST(0x1fff, DC_DISP_H_PULSE2_POSITION_B_0_H_PULSE2_END_B_SHIFT) +#define DC_DISP_H_PULSE2_POSITION_B_0_H_PULSE2_END_B_RANGE 28:16 +#define DC_DISP_H_PULSE2_POSITION_B_0_H_PULSE2_END_B_WOFFSET 0x0 +#define DC_DISP_H_PULSE2_POSITION_B_0_H_PULSE2_END_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_H_PULSE2_POSITION_B_0_H_PULSE2_END_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_H_PULSE2_POSITION_B_0_H_PULSE2_END_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_H_PULSE2_POSITION_B_0_H_PULSE2_END_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_DISP_H_PULSE2_POSITION_C_0 +#define DC_DISP_H_PULSE2_POSITION_C_0 _MK_ADDR_CONST(0x418) +#define DC_DISP_H_PULSE2_POSITION_C_0_SECURE 0x0 +#define DC_DISP_H_PULSE2_POSITION_C_0_WORD_COUNT 0x1 +#define DC_DISP_H_PULSE2_POSITION_C_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_H_PULSE2_POSITION_C_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_H_PULSE2_POSITION_C_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_H_PULSE2_POSITION_C_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_H_PULSE2_POSITION_C_0_READ_MASK _MK_MASK_CONST(0x1fff1fff) +#define DC_DISP_H_PULSE2_POSITION_C_0_WRITE_MASK _MK_MASK_CONST(0x1fff1fff) +#define DC_DISP_H_PULSE2_POSITION_C_0_H_PULSE2_START_C_SHIFT _MK_SHIFT_CONST(0) +#define DC_DISP_H_PULSE2_POSITION_C_0_H_PULSE2_START_C_FIELD _MK_FIELD_CONST(0x1fff, DC_DISP_H_PULSE2_POSITION_C_0_H_PULSE2_START_C_SHIFT) +#define DC_DISP_H_PULSE2_POSITION_C_0_H_PULSE2_START_C_RANGE 12:0 +#define DC_DISP_H_PULSE2_POSITION_C_0_H_PULSE2_START_C_WOFFSET 0x0 +#define DC_DISP_H_PULSE2_POSITION_C_0_H_PULSE2_START_C_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_H_PULSE2_POSITION_C_0_H_PULSE2_START_C_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_H_PULSE2_POSITION_C_0_H_PULSE2_START_C_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_H_PULSE2_POSITION_C_0_H_PULSE2_START_C_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_DISP_H_PULSE2_POSITION_C_0_H_PULSE2_END_C_SHIFT _MK_SHIFT_CONST(16) +#define DC_DISP_H_PULSE2_POSITION_C_0_H_PULSE2_END_C_FIELD _MK_FIELD_CONST(0x1fff, DC_DISP_H_PULSE2_POSITION_C_0_H_PULSE2_END_C_SHIFT) +#define DC_DISP_H_PULSE2_POSITION_C_0_H_PULSE2_END_C_RANGE 28:16 +#define DC_DISP_H_PULSE2_POSITION_C_0_H_PULSE2_END_C_WOFFSET 0x0 +#define DC_DISP_H_PULSE2_POSITION_C_0_H_PULSE2_END_C_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_H_PULSE2_POSITION_C_0_H_PULSE2_END_C_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_H_PULSE2_POSITION_C_0_H_PULSE2_END_C_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_H_PULSE2_POSITION_C_0_H_PULSE2_END_C_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_DISP_H_PULSE2_POSITION_D_0 +#define DC_DISP_H_PULSE2_POSITION_D_0 _MK_ADDR_CONST(0x419) +#define DC_DISP_H_PULSE2_POSITION_D_0_SECURE 0x0 +#define DC_DISP_H_PULSE2_POSITION_D_0_WORD_COUNT 0x1 +#define DC_DISP_H_PULSE2_POSITION_D_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_H_PULSE2_POSITION_D_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_H_PULSE2_POSITION_D_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_H_PULSE2_POSITION_D_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_H_PULSE2_POSITION_D_0_READ_MASK _MK_MASK_CONST(0x1fff1fff) +#define DC_DISP_H_PULSE2_POSITION_D_0_WRITE_MASK _MK_MASK_CONST(0x1fff1fff) +#define DC_DISP_H_PULSE2_POSITION_D_0_H_PULSE2_START_D_SHIFT _MK_SHIFT_CONST(0) +#define DC_DISP_H_PULSE2_POSITION_D_0_H_PULSE2_START_D_FIELD _MK_FIELD_CONST(0x1fff, DC_DISP_H_PULSE2_POSITION_D_0_H_PULSE2_START_D_SHIFT) +#define DC_DISP_H_PULSE2_POSITION_D_0_H_PULSE2_START_D_RANGE 12:0 +#define DC_DISP_H_PULSE2_POSITION_D_0_H_PULSE2_START_D_WOFFSET 0x0 +#define DC_DISP_H_PULSE2_POSITION_D_0_H_PULSE2_START_D_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_H_PULSE2_POSITION_D_0_H_PULSE2_START_D_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_H_PULSE2_POSITION_D_0_H_PULSE2_START_D_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_H_PULSE2_POSITION_D_0_H_PULSE2_START_D_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_DISP_H_PULSE2_POSITION_D_0_H_PULSE2_END_D_SHIFT _MK_SHIFT_CONST(16) +#define DC_DISP_H_PULSE2_POSITION_D_0_H_PULSE2_END_D_FIELD _MK_FIELD_CONST(0x1fff, DC_DISP_H_PULSE2_POSITION_D_0_H_PULSE2_END_D_SHIFT) +#define DC_DISP_H_PULSE2_POSITION_D_0_H_PULSE2_END_D_RANGE 28:16 +#define DC_DISP_H_PULSE2_POSITION_D_0_H_PULSE2_END_D_WOFFSET 0x0 +#define DC_DISP_H_PULSE2_POSITION_D_0_H_PULSE2_END_D_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_H_PULSE2_POSITION_D_0_H_PULSE2_END_D_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_H_PULSE2_POSITION_D_0_H_PULSE2_END_D_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_H_PULSE2_POSITION_D_0_H_PULSE2_END_D_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_DISP_V_PULSE0_CONTROL_0 +#define DC_DISP_V_PULSE0_CONTROL_0 _MK_ADDR_CONST(0x41a) +#define DC_DISP_V_PULSE0_CONTROL_0_SECURE 0x0 +#define DC_DISP_V_PULSE0_CONTROL_0_WORD_COUNT 0x1 +#define DC_DISP_V_PULSE0_CONTROL_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_V_PULSE0_CONTROL_0_RESET_MASK _MK_MASK_CONST(0x1fff0000) +#define DC_DISP_V_PULSE0_CONTROL_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_V_PULSE0_CONTROL_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_V_PULSE0_CONTROL_0_READ_MASK _MK_MASK_CONST(0x1fff0fd0) +#define DC_DISP_V_PULSE0_CONTROL_0_WRITE_MASK _MK_MASK_CONST(0x1fff0fd0) +#define DC_DISP_V_PULSE0_CONTROL_0_V_PULSE0_POLARITY_SHIFT _MK_SHIFT_CONST(4) +#define DC_DISP_V_PULSE0_CONTROL_0_V_PULSE0_POLARITY_FIELD _MK_FIELD_CONST(0x1, DC_DISP_V_PULSE0_CONTROL_0_V_PULSE0_POLARITY_SHIFT) +#define DC_DISP_V_PULSE0_CONTROL_0_V_PULSE0_POLARITY_RANGE 4:4 +#define DC_DISP_V_PULSE0_CONTROL_0_V_PULSE0_POLARITY_WOFFSET 0x0 +#define DC_DISP_V_PULSE0_CONTROL_0_V_PULSE0_POLARITY_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_V_PULSE0_CONTROL_0_V_PULSE0_POLARITY_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_V_PULSE0_CONTROL_0_V_PULSE0_POLARITY_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_V_PULSE0_CONTROL_0_V_PULSE0_POLARITY_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_V_PULSE0_CONTROL_0_V_PULSE0_POLARITY_HIGH _MK_ENUM_CONST(0) +#define DC_DISP_V_PULSE0_CONTROL_0_V_PULSE0_POLARITY_LOW _MK_ENUM_CONST(1) + +#define DC_DISP_V_PULSE0_CONTROL_0_V_PULSE0_DELAY_SHIFT _MK_SHIFT_CONST(6) +#define DC_DISP_V_PULSE0_CONTROL_0_V_PULSE0_DELAY_FIELD _MK_FIELD_CONST(0x3, DC_DISP_V_PULSE0_CONTROL_0_V_PULSE0_DELAY_SHIFT) +#define DC_DISP_V_PULSE0_CONTROL_0_V_PULSE0_DELAY_RANGE 7:6 +#define DC_DISP_V_PULSE0_CONTROL_0_V_PULSE0_DELAY_WOFFSET 0x0 +#define DC_DISP_V_PULSE0_CONTROL_0_V_PULSE0_DELAY_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_V_PULSE0_CONTROL_0_V_PULSE0_DELAY_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_V_PULSE0_CONTROL_0_V_PULSE0_DELAY_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_V_PULSE0_CONTROL_0_V_PULSE0_DELAY_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_V_PULSE0_CONTROL_0_V_PULSE0_DELAY_NODELAY _MK_ENUM_CONST(0) +#define DC_DISP_V_PULSE0_CONTROL_0_V_PULSE0_DELAY_DELAY1 _MK_ENUM_CONST(1) +#define DC_DISP_V_PULSE0_CONTROL_0_V_PULSE0_DELAY_DELAY2 _MK_ENUM_CONST(2) + +#define DC_DISP_V_PULSE0_CONTROL_0_V_PULSE0_LAST_SHIFT _MK_SHIFT_CONST(8) +#define DC_DISP_V_PULSE0_CONTROL_0_V_PULSE0_LAST_FIELD _MK_FIELD_CONST(0xf, DC_DISP_V_PULSE0_CONTROL_0_V_PULSE0_LAST_SHIFT) +#define DC_DISP_V_PULSE0_CONTROL_0_V_PULSE0_LAST_RANGE 11:8 +#define DC_DISP_V_PULSE0_CONTROL_0_V_PULSE0_LAST_WOFFSET 0x0 +#define DC_DISP_V_PULSE0_CONTROL_0_V_PULSE0_LAST_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_V_PULSE0_CONTROL_0_V_PULSE0_LAST_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_V_PULSE0_CONTROL_0_V_PULSE0_LAST_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_V_PULSE0_CONTROL_0_V_PULSE0_LAST_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_V_PULSE0_CONTROL_0_V_PULSE0_LAST_START_A _MK_ENUM_CONST(0) +#define DC_DISP_V_PULSE0_CONTROL_0_V_PULSE0_LAST_END_A _MK_ENUM_CONST(1) +#define DC_DISP_V_PULSE0_CONTROL_0_V_PULSE0_LAST_START_B _MK_ENUM_CONST(2) +#define DC_DISP_V_PULSE0_CONTROL_0_V_PULSE0_LAST_END_B _MK_ENUM_CONST(3) +#define DC_DISP_V_PULSE0_CONTROL_0_V_PULSE0_LAST_START_C _MK_ENUM_CONST(4) +#define DC_DISP_V_PULSE0_CONTROL_0_V_PULSE0_LAST_END_C _MK_ENUM_CONST(5) + +#define DC_DISP_V_PULSE0_CONTROL_0_V_PULSE0_H_POSITION_SHIFT _MK_SHIFT_CONST(16) +#define DC_DISP_V_PULSE0_CONTROL_0_V_PULSE0_H_POSITION_FIELD _MK_FIELD_CONST(0x1fff, DC_DISP_V_PULSE0_CONTROL_0_V_PULSE0_H_POSITION_SHIFT) +#define DC_DISP_V_PULSE0_CONTROL_0_V_PULSE0_H_POSITION_RANGE 28:16 +#define DC_DISP_V_PULSE0_CONTROL_0_V_PULSE0_H_POSITION_WOFFSET 0x0 +#define DC_DISP_V_PULSE0_CONTROL_0_V_PULSE0_H_POSITION_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_V_PULSE0_CONTROL_0_V_PULSE0_H_POSITION_DEFAULT_MASK _MK_MASK_CONST(0x1fff) +#define DC_DISP_V_PULSE0_CONTROL_0_V_PULSE0_H_POSITION_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_V_PULSE0_CONTROL_0_V_PULSE0_H_POSITION_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_DISP_V_PULSE0_POSITION_A_0 +#define DC_DISP_V_PULSE0_POSITION_A_0 _MK_ADDR_CONST(0x41b) +#define DC_DISP_V_PULSE0_POSITION_A_0_SECURE 0x0 +#define DC_DISP_V_PULSE0_POSITION_A_0_WORD_COUNT 0x1 +#define DC_DISP_V_PULSE0_POSITION_A_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_V_PULSE0_POSITION_A_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_V_PULSE0_POSITION_A_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_V_PULSE0_POSITION_A_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_V_PULSE0_POSITION_A_0_READ_MASK _MK_MASK_CONST(0x1fff1fff) +#define DC_DISP_V_PULSE0_POSITION_A_0_WRITE_MASK _MK_MASK_CONST(0x1fff1fff) +#define DC_DISP_V_PULSE0_POSITION_A_0_V_PULSE0_START_A_SHIFT _MK_SHIFT_CONST(0) +#define DC_DISP_V_PULSE0_POSITION_A_0_V_PULSE0_START_A_FIELD _MK_FIELD_CONST(0x1fff, DC_DISP_V_PULSE0_POSITION_A_0_V_PULSE0_START_A_SHIFT) +#define DC_DISP_V_PULSE0_POSITION_A_0_V_PULSE0_START_A_RANGE 12:0 +#define DC_DISP_V_PULSE0_POSITION_A_0_V_PULSE0_START_A_WOFFSET 0x0 +#define DC_DISP_V_PULSE0_POSITION_A_0_V_PULSE0_START_A_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_V_PULSE0_POSITION_A_0_V_PULSE0_START_A_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_V_PULSE0_POSITION_A_0_V_PULSE0_START_A_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_V_PULSE0_POSITION_A_0_V_PULSE0_START_A_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_DISP_V_PULSE0_POSITION_A_0_V_PULSE0_END_A_SHIFT _MK_SHIFT_CONST(16) +#define DC_DISP_V_PULSE0_POSITION_A_0_V_PULSE0_END_A_FIELD _MK_FIELD_CONST(0x1fff, DC_DISP_V_PULSE0_POSITION_A_0_V_PULSE0_END_A_SHIFT) +#define DC_DISP_V_PULSE0_POSITION_A_0_V_PULSE0_END_A_RANGE 28:16 +#define DC_DISP_V_PULSE0_POSITION_A_0_V_PULSE0_END_A_WOFFSET 0x0 +#define DC_DISP_V_PULSE0_POSITION_A_0_V_PULSE0_END_A_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_V_PULSE0_POSITION_A_0_V_PULSE0_END_A_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_V_PULSE0_POSITION_A_0_V_PULSE0_END_A_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_V_PULSE0_POSITION_A_0_V_PULSE0_END_A_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_DISP_V_PULSE0_POSITION_B_0 +#define DC_DISP_V_PULSE0_POSITION_B_0 _MK_ADDR_CONST(0x41c) +#define DC_DISP_V_PULSE0_POSITION_B_0_SECURE 0x0 +#define DC_DISP_V_PULSE0_POSITION_B_0_WORD_COUNT 0x1 +#define DC_DISP_V_PULSE0_POSITION_B_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_V_PULSE0_POSITION_B_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_V_PULSE0_POSITION_B_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_V_PULSE0_POSITION_B_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_V_PULSE0_POSITION_B_0_READ_MASK _MK_MASK_CONST(0x1fff1fff) +#define DC_DISP_V_PULSE0_POSITION_B_0_WRITE_MASK _MK_MASK_CONST(0x1fff1fff) +#define DC_DISP_V_PULSE0_POSITION_B_0_V_PULSE0_START_B_SHIFT _MK_SHIFT_CONST(0) +#define DC_DISP_V_PULSE0_POSITION_B_0_V_PULSE0_START_B_FIELD _MK_FIELD_CONST(0x1fff, DC_DISP_V_PULSE0_POSITION_B_0_V_PULSE0_START_B_SHIFT) +#define DC_DISP_V_PULSE0_POSITION_B_0_V_PULSE0_START_B_RANGE 12:0 +#define DC_DISP_V_PULSE0_POSITION_B_0_V_PULSE0_START_B_WOFFSET 0x0 +#define DC_DISP_V_PULSE0_POSITION_B_0_V_PULSE0_START_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_V_PULSE0_POSITION_B_0_V_PULSE0_START_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_V_PULSE0_POSITION_B_0_V_PULSE0_START_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_V_PULSE0_POSITION_B_0_V_PULSE0_START_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_DISP_V_PULSE0_POSITION_B_0_V_PULSE0_END_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_DISP_V_PULSE0_POSITION_B_0_V_PULSE0_END_B_FIELD _MK_FIELD_CONST(0x1fff, DC_DISP_V_PULSE0_POSITION_B_0_V_PULSE0_END_B_SHIFT) +#define DC_DISP_V_PULSE0_POSITION_B_0_V_PULSE0_END_B_RANGE 28:16 +#define DC_DISP_V_PULSE0_POSITION_B_0_V_PULSE0_END_B_WOFFSET 0x0 +#define DC_DISP_V_PULSE0_POSITION_B_0_V_PULSE0_END_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_V_PULSE0_POSITION_B_0_V_PULSE0_END_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_V_PULSE0_POSITION_B_0_V_PULSE0_END_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_V_PULSE0_POSITION_B_0_V_PULSE0_END_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_DISP_V_PULSE0_POSITION_C_0 +#define DC_DISP_V_PULSE0_POSITION_C_0 _MK_ADDR_CONST(0x41d) +#define DC_DISP_V_PULSE0_POSITION_C_0_SECURE 0x0 +#define DC_DISP_V_PULSE0_POSITION_C_0_WORD_COUNT 0x1 +#define DC_DISP_V_PULSE0_POSITION_C_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_V_PULSE0_POSITION_C_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_V_PULSE0_POSITION_C_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_V_PULSE0_POSITION_C_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_V_PULSE0_POSITION_C_0_READ_MASK _MK_MASK_CONST(0x1fff1fff) +#define DC_DISP_V_PULSE0_POSITION_C_0_WRITE_MASK _MK_MASK_CONST(0x1fff1fff) +#define DC_DISP_V_PULSE0_POSITION_C_0_V_PULSE0_START_C_SHIFT _MK_SHIFT_CONST(0) +#define DC_DISP_V_PULSE0_POSITION_C_0_V_PULSE0_START_C_FIELD _MK_FIELD_CONST(0x1fff, DC_DISP_V_PULSE0_POSITION_C_0_V_PULSE0_START_C_SHIFT) +#define DC_DISP_V_PULSE0_POSITION_C_0_V_PULSE0_START_C_RANGE 12:0 +#define DC_DISP_V_PULSE0_POSITION_C_0_V_PULSE0_START_C_WOFFSET 0x0 +#define DC_DISP_V_PULSE0_POSITION_C_0_V_PULSE0_START_C_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_V_PULSE0_POSITION_C_0_V_PULSE0_START_C_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_V_PULSE0_POSITION_C_0_V_PULSE0_START_C_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_V_PULSE0_POSITION_C_0_V_PULSE0_START_C_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_DISP_V_PULSE0_POSITION_C_0_V_PULSE0_END_C_SHIFT _MK_SHIFT_CONST(16) +#define DC_DISP_V_PULSE0_POSITION_C_0_V_PULSE0_END_C_FIELD _MK_FIELD_CONST(0x1fff, DC_DISP_V_PULSE0_POSITION_C_0_V_PULSE0_END_C_SHIFT) +#define DC_DISP_V_PULSE0_POSITION_C_0_V_PULSE0_END_C_RANGE 28:16 +#define DC_DISP_V_PULSE0_POSITION_C_0_V_PULSE0_END_C_WOFFSET 0x0 +#define DC_DISP_V_PULSE0_POSITION_C_0_V_PULSE0_END_C_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_V_PULSE0_POSITION_C_0_V_PULSE0_END_C_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_V_PULSE0_POSITION_C_0_V_PULSE0_END_C_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_V_PULSE0_POSITION_C_0_V_PULSE0_END_C_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_DISP_V_PULSE1_CONTROL_0 +#define DC_DISP_V_PULSE1_CONTROL_0 _MK_ADDR_CONST(0x41e) +#define DC_DISP_V_PULSE1_CONTROL_0_SECURE 0x0 +#define DC_DISP_V_PULSE1_CONTROL_0_WORD_COUNT 0x1 +#define DC_DISP_V_PULSE1_CONTROL_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_V_PULSE1_CONTROL_0_RESET_MASK _MK_MASK_CONST(0x1fff0010) +#define DC_DISP_V_PULSE1_CONTROL_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_V_PULSE1_CONTROL_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_V_PULSE1_CONTROL_0_READ_MASK _MK_MASK_CONST(0x1fff0fd0) +#define DC_DISP_V_PULSE1_CONTROL_0_WRITE_MASK _MK_MASK_CONST(0x1fff0fd0) +#define DC_DISP_V_PULSE1_CONTROL_0_V_PULSE1_POLARITY_SHIFT _MK_SHIFT_CONST(4) +#define DC_DISP_V_PULSE1_CONTROL_0_V_PULSE1_POLARITY_FIELD _MK_FIELD_CONST(0x1, DC_DISP_V_PULSE1_CONTROL_0_V_PULSE1_POLARITY_SHIFT) +#define DC_DISP_V_PULSE1_CONTROL_0_V_PULSE1_POLARITY_RANGE 4:4 +#define DC_DISP_V_PULSE1_CONTROL_0_V_PULSE1_POLARITY_WOFFSET 0x0 +#define DC_DISP_V_PULSE1_CONTROL_0_V_PULSE1_POLARITY_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_V_PULSE1_CONTROL_0_V_PULSE1_POLARITY_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_DISP_V_PULSE1_CONTROL_0_V_PULSE1_POLARITY_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_V_PULSE1_CONTROL_0_V_PULSE1_POLARITY_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_V_PULSE1_CONTROL_0_V_PULSE1_POLARITY_HIGH _MK_ENUM_CONST(0) +#define DC_DISP_V_PULSE1_CONTROL_0_V_PULSE1_POLARITY_LOW _MK_ENUM_CONST(1) + +#define DC_DISP_V_PULSE1_CONTROL_0_V_PULSE1_DELAY_SHIFT _MK_SHIFT_CONST(6) +#define DC_DISP_V_PULSE1_CONTROL_0_V_PULSE1_DELAY_FIELD _MK_FIELD_CONST(0x3, DC_DISP_V_PULSE1_CONTROL_0_V_PULSE1_DELAY_SHIFT) +#define DC_DISP_V_PULSE1_CONTROL_0_V_PULSE1_DELAY_RANGE 7:6 +#define DC_DISP_V_PULSE1_CONTROL_0_V_PULSE1_DELAY_WOFFSET 0x0 +#define DC_DISP_V_PULSE1_CONTROL_0_V_PULSE1_DELAY_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_V_PULSE1_CONTROL_0_V_PULSE1_DELAY_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_V_PULSE1_CONTROL_0_V_PULSE1_DELAY_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_V_PULSE1_CONTROL_0_V_PULSE1_DELAY_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_V_PULSE1_CONTROL_0_V_PULSE1_DELAY_NODELAY _MK_ENUM_CONST(0) +#define DC_DISP_V_PULSE1_CONTROL_0_V_PULSE1_DELAY_DELAY1 _MK_ENUM_CONST(1) +#define DC_DISP_V_PULSE1_CONTROL_0_V_PULSE1_DELAY_DELAY2 _MK_ENUM_CONST(2) + +#define DC_DISP_V_PULSE1_CONTROL_0_V_PULSE1_LAST_SHIFT _MK_SHIFT_CONST(8) +#define DC_DISP_V_PULSE1_CONTROL_0_V_PULSE1_LAST_FIELD _MK_FIELD_CONST(0xf, DC_DISP_V_PULSE1_CONTROL_0_V_PULSE1_LAST_SHIFT) +#define DC_DISP_V_PULSE1_CONTROL_0_V_PULSE1_LAST_RANGE 11:8 +#define DC_DISP_V_PULSE1_CONTROL_0_V_PULSE1_LAST_WOFFSET 0x0 +#define DC_DISP_V_PULSE1_CONTROL_0_V_PULSE1_LAST_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_V_PULSE1_CONTROL_0_V_PULSE1_LAST_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_V_PULSE1_CONTROL_0_V_PULSE1_LAST_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_V_PULSE1_CONTROL_0_V_PULSE1_LAST_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_V_PULSE1_CONTROL_0_V_PULSE1_LAST_START_A _MK_ENUM_CONST(0) +#define DC_DISP_V_PULSE1_CONTROL_0_V_PULSE1_LAST_END_A _MK_ENUM_CONST(1) +#define DC_DISP_V_PULSE1_CONTROL_0_V_PULSE1_LAST_START_B _MK_ENUM_CONST(2) +#define DC_DISP_V_PULSE1_CONTROL_0_V_PULSE1_LAST_END_B _MK_ENUM_CONST(3) +#define DC_DISP_V_PULSE1_CONTROL_0_V_PULSE1_LAST_START_C _MK_ENUM_CONST(4) +#define DC_DISP_V_PULSE1_CONTROL_0_V_PULSE1_LAST_END_C _MK_ENUM_CONST(5) + +#define DC_DISP_V_PULSE1_CONTROL_0_V_PULSE1_H_POSITION_SHIFT _MK_SHIFT_CONST(16) +#define DC_DISP_V_PULSE1_CONTROL_0_V_PULSE1_H_POSITION_FIELD _MK_FIELD_CONST(0x1fff, DC_DISP_V_PULSE1_CONTROL_0_V_PULSE1_H_POSITION_SHIFT) +#define DC_DISP_V_PULSE1_CONTROL_0_V_PULSE1_H_POSITION_RANGE 28:16 +#define DC_DISP_V_PULSE1_CONTROL_0_V_PULSE1_H_POSITION_WOFFSET 0x0 +#define DC_DISP_V_PULSE1_CONTROL_0_V_PULSE1_H_POSITION_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_V_PULSE1_CONTROL_0_V_PULSE1_H_POSITION_DEFAULT_MASK _MK_MASK_CONST(0x1fff) +#define DC_DISP_V_PULSE1_CONTROL_0_V_PULSE1_H_POSITION_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_V_PULSE1_CONTROL_0_V_PULSE1_H_POSITION_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_DISP_V_PULSE1_POSITION_A_0 +#define DC_DISP_V_PULSE1_POSITION_A_0 _MK_ADDR_CONST(0x41f) +#define DC_DISP_V_PULSE1_POSITION_A_0_SECURE 0x0 +#define DC_DISP_V_PULSE1_POSITION_A_0_WORD_COUNT 0x1 +#define DC_DISP_V_PULSE1_POSITION_A_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_V_PULSE1_POSITION_A_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_V_PULSE1_POSITION_A_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_V_PULSE1_POSITION_A_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_V_PULSE1_POSITION_A_0_READ_MASK _MK_MASK_CONST(0x1fff1fff) +#define DC_DISP_V_PULSE1_POSITION_A_0_WRITE_MASK _MK_MASK_CONST(0x1fff1fff) +#define DC_DISP_V_PULSE1_POSITION_A_0_V_PULSE1_START_A_SHIFT _MK_SHIFT_CONST(0) +#define DC_DISP_V_PULSE1_POSITION_A_0_V_PULSE1_START_A_FIELD _MK_FIELD_CONST(0x1fff, DC_DISP_V_PULSE1_POSITION_A_0_V_PULSE1_START_A_SHIFT) +#define DC_DISP_V_PULSE1_POSITION_A_0_V_PULSE1_START_A_RANGE 12:0 +#define DC_DISP_V_PULSE1_POSITION_A_0_V_PULSE1_START_A_WOFFSET 0x0 +#define DC_DISP_V_PULSE1_POSITION_A_0_V_PULSE1_START_A_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_V_PULSE1_POSITION_A_0_V_PULSE1_START_A_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_V_PULSE1_POSITION_A_0_V_PULSE1_START_A_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_V_PULSE1_POSITION_A_0_V_PULSE1_START_A_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_DISP_V_PULSE1_POSITION_A_0_V_PULSE1_END_A_SHIFT _MK_SHIFT_CONST(16) +#define DC_DISP_V_PULSE1_POSITION_A_0_V_PULSE1_END_A_FIELD _MK_FIELD_CONST(0x1fff, DC_DISP_V_PULSE1_POSITION_A_0_V_PULSE1_END_A_SHIFT) +#define DC_DISP_V_PULSE1_POSITION_A_0_V_PULSE1_END_A_RANGE 28:16 +#define DC_DISP_V_PULSE1_POSITION_A_0_V_PULSE1_END_A_WOFFSET 0x0 +#define DC_DISP_V_PULSE1_POSITION_A_0_V_PULSE1_END_A_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_V_PULSE1_POSITION_A_0_V_PULSE1_END_A_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_V_PULSE1_POSITION_A_0_V_PULSE1_END_A_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_V_PULSE1_POSITION_A_0_V_PULSE1_END_A_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_DISP_V_PULSE1_POSITION_B_0 +#define DC_DISP_V_PULSE1_POSITION_B_0 _MK_ADDR_CONST(0x420) +#define DC_DISP_V_PULSE1_POSITION_B_0_SECURE 0x0 +#define DC_DISP_V_PULSE1_POSITION_B_0_WORD_COUNT 0x1 +#define DC_DISP_V_PULSE1_POSITION_B_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_V_PULSE1_POSITION_B_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_V_PULSE1_POSITION_B_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_V_PULSE1_POSITION_B_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_V_PULSE1_POSITION_B_0_READ_MASK _MK_MASK_CONST(0x1fff1fff) +#define DC_DISP_V_PULSE1_POSITION_B_0_WRITE_MASK _MK_MASK_CONST(0x1fff1fff) +#define DC_DISP_V_PULSE1_POSITION_B_0_V_PULSE1_START_B_SHIFT _MK_SHIFT_CONST(0) +#define DC_DISP_V_PULSE1_POSITION_B_0_V_PULSE1_START_B_FIELD _MK_FIELD_CONST(0x1fff, DC_DISP_V_PULSE1_POSITION_B_0_V_PULSE1_START_B_SHIFT) +#define DC_DISP_V_PULSE1_POSITION_B_0_V_PULSE1_START_B_RANGE 12:0 +#define DC_DISP_V_PULSE1_POSITION_B_0_V_PULSE1_START_B_WOFFSET 0x0 +#define DC_DISP_V_PULSE1_POSITION_B_0_V_PULSE1_START_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_V_PULSE1_POSITION_B_0_V_PULSE1_START_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_V_PULSE1_POSITION_B_0_V_PULSE1_START_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_V_PULSE1_POSITION_B_0_V_PULSE1_START_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_DISP_V_PULSE1_POSITION_B_0_V_PULSE1_END_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_DISP_V_PULSE1_POSITION_B_0_V_PULSE1_END_B_FIELD _MK_FIELD_CONST(0x1fff, DC_DISP_V_PULSE1_POSITION_B_0_V_PULSE1_END_B_SHIFT) +#define DC_DISP_V_PULSE1_POSITION_B_0_V_PULSE1_END_B_RANGE 28:16 +#define DC_DISP_V_PULSE1_POSITION_B_0_V_PULSE1_END_B_WOFFSET 0x0 +#define DC_DISP_V_PULSE1_POSITION_B_0_V_PULSE1_END_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_V_PULSE1_POSITION_B_0_V_PULSE1_END_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_V_PULSE1_POSITION_B_0_V_PULSE1_END_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_V_PULSE1_POSITION_B_0_V_PULSE1_END_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_DISP_V_PULSE1_POSITION_C_0 +#define DC_DISP_V_PULSE1_POSITION_C_0 _MK_ADDR_CONST(0x421) +#define DC_DISP_V_PULSE1_POSITION_C_0_SECURE 0x0 +#define DC_DISP_V_PULSE1_POSITION_C_0_WORD_COUNT 0x1 +#define DC_DISP_V_PULSE1_POSITION_C_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_V_PULSE1_POSITION_C_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_V_PULSE1_POSITION_C_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_V_PULSE1_POSITION_C_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_V_PULSE1_POSITION_C_0_READ_MASK _MK_MASK_CONST(0x1fff1fff) +#define DC_DISP_V_PULSE1_POSITION_C_0_WRITE_MASK _MK_MASK_CONST(0x1fff1fff) +#define DC_DISP_V_PULSE1_POSITION_C_0_V_PULSE1_START_C_SHIFT _MK_SHIFT_CONST(0) +#define DC_DISP_V_PULSE1_POSITION_C_0_V_PULSE1_START_C_FIELD _MK_FIELD_CONST(0x1fff, DC_DISP_V_PULSE1_POSITION_C_0_V_PULSE1_START_C_SHIFT) +#define DC_DISP_V_PULSE1_POSITION_C_0_V_PULSE1_START_C_RANGE 12:0 +#define DC_DISP_V_PULSE1_POSITION_C_0_V_PULSE1_START_C_WOFFSET 0x0 +#define DC_DISP_V_PULSE1_POSITION_C_0_V_PULSE1_START_C_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_V_PULSE1_POSITION_C_0_V_PULSE1_START_C_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_V_PULSE1_POSITION_C_0_V_PULSE1_START_C_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_V_PULSE1_POSITION_C_0_V_PULSE1_START_C_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_DISP_V_PULSE1_POSITION_C_0_V_PULSE1_END_C_SHIFT _MK_SHIFT_CONST(16) +#define DC_DISP_V_PULSE1_POSITION_C_0_V_PULSE1_END_C_FIELD _MK_FIELD_CONST(0x1fff, DC_DISP_V_PULSE1_POSITION_C_0_V_PULSE1_END_C_SHIFT) +#define DC_DISP_V_PULSE1_POSITION_C_0_V_PULSE1_END_C_RANGE 28:16 +#define DC_DISP_V_PULSE1_POSITION_C_0_V_PULSE1_END_C_WOFFSET 0x0 +#define DC_DISP_V_PULSE1_POSITION_C_0_V_PULSE1_END_C_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_V_PULSE1_POSITION_C_0_V_PULSE1_END_C_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_V_PULSE1_POSITION_C_0_V_PULSE1_END_C_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_V_PULSE1_POSITION_C_0_V_PULSE1_END_C_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_DISP_V_PULSE2_CONTROL_0 +#define DC_DISP_V_PULSE2_CONTROL_0 _MK_ADDR_CONST(0x422) +#define DC_DISP_V_PULSE2_CONTROL_0_SECURE 0x0 +#define DC_DISP_V_PULSE2_CONTROL_0_WORD_COUNT 0x1 +#define DC_DISP_V_PULSE2_CONTROL_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_V_PULSE2_CONTROL_0_RESET_MASK _MK_MASK_CONST(0x1fff0010) +#define DC_DISP_V_PULSE2_CONTROL_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_V_PULSE2_CONTROL_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_V_PULSE2_CONTROL_0_READ_MASK _MK_MASK_CONST(0x1fff0110) +#define DC_DISP_V_PULSE2_CONTROL_0_WRITE_MASK _MK_MASK_CONST(0x1fff0110) +#define DC_DISP_V_PULSE2_CONTROL_0_V_PULSE2_POLARITY_SHIFT _MK_SHIFT_CONST(4) +#define DC_DISP_V_PULSE2_CONTROL_0_V_PULSE2_POLARITY_FIELD _MK_FIELD_CONST(0x1, DC_DISP_V_PULSE2_CONTROL_0_V_PULSE2_POLARITY_SHIFT) +#define DC_DISP_V_PULSE2_CONTROL_0_V_PULSE2_POLARITY_RANGE 4:4 +#define DC_DISP_V_PULSE2_CONTROL_0_V_PULSE2_POLARITY_WOFFSET 0x0 +#define DC_DISP_V_PULSE2_CONTROL_0_V_PULSE2_POLARITY_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_V_PULSE2_CONTROL_0_V_PULSE2_POLARITY_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_DISP_V_PULSE2_CONTROL_0_V_PULSE2_POLARITY_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_V_PULSE2_CONTROL_0_V_PULSE2_POLARITY_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_V_PULSE2_CONTROL_0_V_PULSE2_POLARITY_HIGH _MK_ENUM_CONST(0) +#define DC_DISP_V_PULSE2_CONTROL_0_V_PULSE2_POLARITY_LOW _MK_ENUM_CONST(1) + +#define DC_DISP_V_PULSE2_CONTROL_0_V_PULSE2_LAST_SHIFT _MK_SHIFT_CONST(8) +#define DC_DISP_V_PULSE2_CONTROL_0_V_PULSE2_LAST_FIELD _MK_FIELD_CONST(0x1, DC_DISP_V_PULSE2_CONTROL_0_V_PULSE2_LAST_SHIFT) +#define DC_DISP_V_PULSE2_CONTROL_0_V_PULSE2_LAST_RANGE 8:8 +#define DC_DISP_V_PULSE2_CONTROL_0_V_PULSE2_LAST_WOFFSET 0x0 +#define DC_DISP_V_PULSE2_CONTROL_0_V_PULSE2_LAST_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_V_PULSE2_CONTROL_0_V_PULSE2_LAST_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_V_PULSE2_CONTROL_0_V_PULSE2_LAST_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_V_PULSE2_CONTROL_0_V_PULSE2_LAST_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_V_PULSE2_CONTROL_0_V_PULSE2_LAST_START_A _MK_ENUM_CONST(0) +#define DC_DISP_V_PULSE2_CONTROL_0_V_PULSE2_LAST_END_A _MK_ENUM_CONST(1) + +#define DC_DISP_V_PULSE2_CONTROL_0_V_PULSE2_H_POSITION_SHIFT _MK_SHIFT_CONST(16) +#define DC_DISP_V_PULSE2_CONTROL_0_V_PULSE2_H_POSITION_FIELD _MK_FIELD_CONST(0x1fff, DC_DISP_V_PULSE2_CONTROL_0_V_PULSE2_H_POSITION_SHIFT) +#define DC_DISP_V_PULSE2_CONTROL_0_V_PULSE2_H_POSITION_RANGE 28:16 +#define DC_DISP_V_PULSE2_CONTROL_0_V_PULSE2_H_POSITION_WOFFSET 0x0 +#define DC_DISP_V_PULSE2_CONTROL_0_V_PULSE2_H_POSITION_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_V_PULSE2_CONTROL_0_V_PULSE2_H_POSITION_DEFAULT_MASK _MK_MASK_CONST(0x1fff) +#define DC_DISP_V_PULSE2_CONTROL_0_V_PULSE2_H_POSITION_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_V_PULSE2_CONTROL_0_V_PULSE2_H_POSITION_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_DISP_V_PULSE2_POSITION_A_0 +#define DC_DISP_V_PULSE2_POSITION_A_0 _MK_ADDR_CONST(0x423) +#define DC_DISP_V_PULSE2_POSITION_A_0_SECURE 0x0 +#define DC_DISP_V_PULSE2_POSITION_A_0_WORD_COUNT 0x1 +#define DC_DISP_V_PULSE2_POSITION_A_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_V_PULSE2_POSITION_A_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_V_PULSE2_POSITION_A_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_V_PULSE2_POSITION_A_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_V_PULSE2_POSITION_A_0_READ_MASK _MK_MASK_CONST(0x1fff1fff) +#define DC_DISP_V_PULSE2_POSITION_A_0_WRITE_MASK _MK_MASK_CONST(0x1fff1fff) +#define DC_DISP_V_PULSE2_POSITION_A_0_V_PULSE2_START_A_SHIFT _MK_SHIFT_CONST(0) +#define DC_DISP_V_PULSE2_POSITION_A_0_V_PULSE2_START_A_FIELD _MK_FIELD_CONST(0x1fff, DC_DISP_V_PULSE2_POSITION_A_0_V_PULSE2_START_A_SHIFT) +#define DC_DISP_V_PULSE2_POSITION_A_0_V_PULSE2_START_A_RANGE 12:0 +#define DC_DISP_V_PULSE2_POSITION_A_0_V_PULSE2_START_A_WOFFSET 0x0 +#define DC_DISP_V_PULSE2_POSITION_A_0_V_PULSE2_START_A_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_V_PULSE2_POSITION_A_0_V_PULSE2_START_A_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_V_PULSE2_POSITION_A_0_V_PULSE2_START_A_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_V_PULSE2_POSITION_A_0_V_PULSE2_START_A_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_DISP_V_PULSE2_POSITION_A_0_V_PULSE2_END_A_SHIFT _MK_SHIFT_CONST(16) +#define DC_DISP_V_PULSE2_POSITION_A_0_V_PULSE2_END_A_FIELD _MK_FIELD_CONST(0x1fff, DC_DISP_V_PULSE2_POSITION_A_0_V_PULSE2_END_A_SHIFT) +#define DC_DISP_V_PULSE2_POSITION_A_0_V_PULSE2_END_A_RANGE 28:16 +#define DC_DISP_V_PULSE2_POSITION_A_0_V_PULSE2_END_A_WOFFSET 0x0 +#define DC_DISP_V_PULSE2_POSITION_A_0_V_PULSE2_END_A_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_V_PULSE2_POSITION_A_0_V_PULSE2_END_A_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_V_PULSE2_POSITION_A_0_V_PULSE2_END_A_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_V_PULSE2_POSITION_A_0_V_PULSE2_END_A_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_DISP_V_PULSE3_CONTROL_0 +#define DC_DISP_V_PULSE3_CONTROL_0 _MK_ADDR_CONST(0x424) +#define DC_DISP_V_PULSE3_CONTROL_0_SECURE 0x0 +#define DC_DISP_V_PULSE3_CONTROL_0_WORD_COUNT 0x1 +#define DC_DISP_V_PULSE3_CONTROL_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_V_PULSE3_CONTROL_0_RESET_MASK _MK_MASK_CONST(0x1fff0010) +#define DC_DISP_V_PULSE3_CONTROL_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_V_PULSE3_CONTROL_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_V_PULSE3_CONTROL_0_READ_MASK _MK_MASK_CONST(0x1fff0110) +#define DC_DISP_V_PULSE3_CONTROL_0_WRITE_MASK _MK_MASK_CONST(0x1fff0110) +#define DC_DISP_V_PULSE3_CONTROL_0_V_PULSE3_POLARITY_SHIFT _MK_SHIFT_CONST(4) +#define DC_DISP_V_PULSE3_CONTROL_0_V_PULSE3_POLARITY_FIELD _MK_FIELD_CONST(0x1, DC_DISP_V_PULSE3_CONTROL_0_V_PULSE3_POLARITY_SHIFT) +#define DC_DISP_V_PULSE3_CONTROL_0_V_PULSE3_POLARITY_RANGE 4:4 +#define DC_DISP_V_PULSE3_CONTROL_0_V_PULSE3_POLARITY_WOFFSET 0x0 +#define DC_DISP_V_PULSE3_CONTROL_0_V_PULSE3_POLARITY_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_V_PULSE3_CONTROL_0_V_PULSE3_POLARITY_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_DISP_V_PULSE3_CONTROL_0_V_PULSE3_POLARITY_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_V_PULSE3_CONTROL_0_V_PULSE3_POLARITY_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_V_PULSE3_CONTROL_0_V_PULSE3_POLARITY_HIGH _MK_ENUM_CONST(0) +#define DC_DISP_V_PULSE3_CONTROL_0_V_PULSE3_POLARITY_LOW _MK_ENUM_CONST(1) + +#define DC_DISP_V_PULSE3_CONTROL_0_V_PULSE3_LAST_SHIFT _MK_SHIFT_CONST(8) +#define DC_DISP_V_PULSE3_CONTROL_0_V_PULSE3_LAST_FIELD _MK_FIELD_CONST(0x1, DC_DISP_V_PULSE3_CONTROL_0_V_PULSE3_LAST_SHIFT) +#define DC_DISP_V_PULSE3_CONTROL_0_V_PULSE3_LAST_RANGE 8:8 +#define DC_DISP_V_PULSE3_CONTROL_0_V_PULSE3_LAST_WOFFSET 0x0 +#define DC_DISP_V_PULSE3_CONTROL_0_V_PULSE3_LAST_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_V_PULSE3_CONTROL_0_V_PULSE3_LAST_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_V_PULSE3_CONTROL_0_V_PULSE3_LAST_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_V_PULSE3_CONTROL_0_V_PULSE3_LAST_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_V_PULSE3_CONTROL_0_V_PULSE3_LAST_START_A _MK_ENUM_CONST(0) +#define DC_DISP_V_PULSE3_CONTROL_0_V_PULSE3_LAST_END_A _MK_ENUM_CONST(1) + +#define DC_DISP_V_PULSE3_CONTROL_0_V_PULSE3_H_POSITION_SHIFT _MK_SHIFT_CONST(16) +#define DC_DISP_V_PULSE3_CONTROL_0_V_PULSE3_H_POSITION_FIELD _MK_FIELD_CONST(0x1fff, DC_DISP_V_PULSE3_CONTROL_0_V_PULSE3_H_POSITION_SHIFT) +#define DC_DISP_V_PULSE3_CONTROL_0_V_PULSE3_H_POSITION_RANGE 28:16 +#define DC_DISP_V_PULSE3_CONTROL_0_V_PULSE3_H_POSITION_WOFFSET 0x0 +#define DC_DISP_V_PULSE3_CONTROL_0_V_PULSE3_H_POSITION_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_V_PULSE3_CONTROL_0_V_PULSE3_H_POSITION_DEFAULT_MASK _MK_MASK_CONST(0x1fff) +#define DC_DISP_V_PULSE3_CONTROL_0_V_PULSE3_H_POSITION_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_V_PULSE3_CONTROL_0_V_PULSE3_H_POSITION_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_DISP_V_PULSE3_POSITION_A_0 +#define DC_DISP_V_PULSE3_POSITION_A_0 _MK_ADDR_CONST(0x425) +#define DC_DISP_V_PULSE3_POSITION_A_0_SECURE 0x0 +#define DC_DISP_V_PULSE3_POSITION_A_0_WORD_COUNT 0x1 +#define DC_DISP_V_PULSE3_POSITION_A_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_V_PULSE3_POSITION_A_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_V_PULSE3_POSITION_A_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_V_PULSE3_POSITION_A_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_V_PULSE3_POSITION_A_0_READ_MASK _MK_MASK_CONST(0x1fff1fff) +#define DC_DISP_V_PULSE3_POSITION_A_0_WRITE_MASK _MK_MASK_CONST(0x1fff1fff) +#define DC_DISP_V_PULSE3_POSITION_A_0_V_PULSE3_START_A_SHIFT _MK_SHIFT_CONST(0) +#define DC_DISP_V_PULSE3_POSITION_A_0_V_PULSE3_START_A_FIELD _MK_FIELD_CONST(0x1fff, DC_DISP_V_PULSE3_POSITION_A_0_V_PULSE3_START_A_SHIFT) +#define DC_DISP_V_PULSE3_POSITION_A_0_V_PULSE3_START_A_RANGE 12:0 +#define DC_DISP_V_PULSE3_POSITION_A_0_V_PULSE3_START_A_WOFFSET 0x0 +#define DC_DISP_V_PULSE3_POSITION_A_0_V_PULSE3_START_A_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_V_PULSE3_POSITION_A_0_V_PULSE3_START_A_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_V_PULSE3_POSITION_A_0_V_PULSE3_START_A_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_V_PULSE3_POSITION_A_0_V_PULSE3_START_A_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_DISP_V_PULSE3_POSITION_A_0_V_PULSE3_END_A_SHIFT _MK_SHIFT_CONST(16) +#define DC_DISP_V_PULSE3_POSITION_A_0_V_PULSE3_END_A_FIELD _MK_FIELD_CONST(0x1fff, DC_DISP_V_PULSE3_POSITION_A_0_V_PULSE3_END_A_SHIFT) +#define DC_DISP_V_PULSE3_POSITION_A_0_V_PULSE3_END_A_RANGE 28:16 +#define DC_DISP_V_PULSE3_POSITION_A_0_V_PULSE3_END_A_WOFFSET 0x0 +#define DC_DISP_V_PULSE3_POSITION_A_0_V_PULSE3_END_A_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_V_PULSE3_POSITION_A_0_V_PULSE3_END_A_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_V_PULSE3_POSITION_A_0_V_PULSE3_END_A_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_V_PULSE3_POSITION_A_0_V_PULSE3_END_A_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_DISP_M0_CONTROL_0 +#define DC_DISP_M0_CONTROL_0 _MK_ADDR_CONST(0x426) +#define DC_DISP_M0_CONTROL_0_SECURE 0x0 +#define DC_DISP_M0_CONTROL_0_WORD_COUNT 0x1 +#define DC_DISP_M0_CONTROL_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_M0_CONTROL_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_M0_CONTROL_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_M0_CONTROL_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_M0_CONTROL_0_READ_MASK _MK_MASK_CONST(0x1fff1ff3) +#define DC_DISP_M0_CONTROL_0_WRITE_MASK _MK_MASK_CONST(0x1fff1ff3) +#define DC_DISP_M0_CONTROL_0_M0_CLOCK_SELECT_SHIFT _MK_SHIFT_CONST(0) +#define DC_DISP_M0_CONTROL_0_M0_CLOCK_SELECT_FIELD _MK_FIELD_CONST(0x3, DC_DISP_M0_CONTROL_0_M0_CLOCK_SELECT_SHIFT) +#define DC_DISP_M0_CONTROL_0_M0_CLOCK_SELECT_RANGE 1:0 +#define DC_DISP_M0_CONTROL_0_M0_CLOCK_SELECT_WOFFSET 0x0 +#define DC_DISP_M0_CONTROL_0_M0_CLOCK_SELECT_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_M0_CONTROL_0_M0_CLOCK_SELECT_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_M0_CONTROL_0_M0_CLOCK_SELECT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_M0_CONTROL_0_M0_CLOCK_SELECT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_M0_CONTROL_0_M0_CLOCK_SELECT_PCLK _MK_ENUM_CONST(0) +#define DC_DISP_M0_CONTROL_0_M0_CLOCK_SELECT_LCLK _MK_ENUM_CONST(2) +#define DC_DISP_M0_CONTROL_0_M0_CLOCK_SELECT_FCLK _MK_ENUM_CONST(3) + +#define DC_DISP_M0_CONTROL_0_M0_PHASE_CONTROL_SHIFT _MK_SHIFT_CONST(4) +#define DC_DISP_M0_CONTROL_0_M0_PHASE_CONTROL_FIELD _MK_FIELD_CONST(0x3, DC_DISP_M0_CONTROL_0_M0_PHASE_CONTROL_SHIFT) +#define DC_DISP_M0_CONTROL_0_M0_PHASE_CONTROL_RANGE 5:4 +#define DC_DISP_M0_CONTROL_0_M0_PHASE_CONTROL_WOFFSET 0x0 +#define DC_DISP_M0_CONTROL_0_M0_PHASE_CONTROL_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_M0_CONTROL_0_M0_PHASE_CONTROL_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_M0_CONTROL_0_M0_PHASE_CONTROL_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_M0_CONTROL_0_M0_PHASE_CONTROL_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_M0_CONTROL_0_M0_PHASE_CONTROL_FREE_RUN _MK_ENUM_CONST(0) +#define DC_DISP_M0_CONTROL_0_M0_PHASE_CONTROL_VACTIVE_RESTART _MK_ENUM_CONST(2) +#define DC_DISP_M0_CONTROL_0_M0_PHASE_CONTROL_FRAME_INVERT _MK_ENUM_CONST(3) + +#define DC_DISP_M0_CONTROL_0_M0_PHASE_RESET_SHIFT _MK_SHIFT_CONST(6) +#define DC_DISP_M0_CONTROL_0_M0_PHASE_RESET_FIELD _MK_FIELD_CONST(0x1, DC_DISP_M0_CONTROL_0_M0_PHASE_RESET_SHIFT) +#define DC_DISP_M0_CONTROL_0_M0_PHASE_RESET_RANGE 6:6 +#define DC_DISP_M0_CONTROL_0_M0_PHASE_RESET_WOFFSET 0x0 +#define DC_DISP_M0_CONTROL_0_M0_PHASE_RESET_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_M0_CONTROL_0_M0_PHASE_RESET_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_M0_CONTROL_0_M0_PHASE_RESET_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_M0_CONTROL_0_M0_PHASE_RESET_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_M0_CONTROL_0_M0_PHASE_RESET_DISABLE _MK_ENUM_CONST(0) +#define DC_DISP_M0_CONTROL_0_M0_PHASE_RESET_ENABLE _MK_ENUM_CONST(1) + +#define DC_DISP_M0_CONTROL_0_M0_POLARITY_SHIFT _MK_SHIFT_CONST(7) +#define DC_DISP_M0_CONTROL_0_M0_POLARITY_FIELD _MK_FIELD_CONST(0x1, DC_DISP_M0_CONTROL_0_M0_POLARITY_SHIFT) +#define DC_DISP_M0_CONTROL_0_M0_POLARITY_RANGE 7:7 +#define DC_DISP_M0_CONTROL_0_M0_POLARITY_WOFFSET 0x0 +#define DC_DISP_M0_CONTROL_0_M0_POLARITY_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_M0_CONTROL_0_M0_POLARITY_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_M0_CONTROL_0_M0_POLARITY_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_M0_CONTROL_0_M0_POLARITY_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_M0_CONTROL_0_M0_POLARITY_HIGH _MK_ENUM_CONST(0) +#define DC_DISP_M0_CONTROL_0_M0_POLARITY_LOW _MK_ENUM_CONST(1) + +#define DC_DISP_M0_CONTROL_0_M0_PERIOD_SHIFT _MK_SHIFT_CONST(8) +#define DC_DISP_M0_CONTROL_0_M0_PERIOD_FIELD _MK_FIELD_CONST(0x1f, DC_DISP_M0_CONTROL_0_M0_PERIOD_SHIFT) +#define DC_DISP_M0_CONTROL_0_M0_PERIOD_RANGE 12:8 +#define DC_DISP_M0_CONTROL_0_M0_PERIOD_WOFFSET 0x0 +#define DC_DISP_M0_CONTROL_0_M0_PERIOD_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_M0_CONTROL_0_M0_PERIOD_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_M0_CONTROL_0_M0_PERIOD_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_M0_CONTROL_0_M0_PERIOD_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_DISP_M0_CONTROL_0_M0_H_POSITION_SHIFT _MK_SHIFT_CONST(16) +#define DC_DISP_M0_CONTROL_0_M0_H_POSITION_FIELD _MK_FIELD_CONST(0x1fff, DC_DISP_M0_CONTROL_0_M0_H_POSITION_SHIFT) +#define DC_DISP_M0_CONTROL_0_M0_H_POSITION_RANGE 28:16 +#define DC_DISP_M0_CONTROL_0_M0_H_POSITION_WOFFSET 0x0 +#define DC_DISP_M0_CONTROL_0_M0_H_POSITION_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_M0_CONTROL_0_M0_H_POSITION_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_M0_CONTROL_0_M0_H_POSITION_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_M0_CONTROL_0_M0_H_POSITION_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_DISP_M1_CONTROL_0 +#define DC_DISP_M1_CONTROL_0 _MK_ADDR_CONST(0x427) +#define DC_DISP_M1_CONTROL_0_SECURE 0x0 +#define DC_DISP_M1_CONTROL_0_WORD_COUNT 0x1 +#define DC_DISP_M1_CONTROL_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_M1_CONTROL_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_M1_CONTROL_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_M1_CONTROL_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_M1_CONTROL_0_READ_MASK _MK_MASK_CONST(0x1fff1ff3) +#define DC_DISP_M1_CONTROL_0_WRITE_MASK _MK_MASK_CONST(0x1fff1ff3) +#define DC_DISP_M1_CONTROL_0_M1_CLOCK_SELECT_SHIFT _MK_SHIFT_CONST(0) +#define DC_DISP_M1_CONTROL_0_M1_CLOCK_SELECT_FIELD _MK_FIELD_CONST(0x3, DC_DISP_M1_CONTROL_0_M1_CLOCK_SELECT_SHIFT) +#define DC_DISP_M1_CONTROL_0_M1_CLOCK_SELECT_RANGE 1:0 +#define DC_DISP_M1_CONTROL_0_M1_CLOCK_SELECT_WOFFSET 0x0 +#define DC_DISP_M1_CONTROL_0_M1_CLOCK_SELECT_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_M1_CONTROL_0_M1_CLOCK_SELECT_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_M1_CONTROL_0_M1_CLOCK_SELECT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_M1_CONTROL_0_M1_CLOCK_SELECT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_M1_CONTROL_0_M1_CLOCK_SELECT_PCLK _MK_ENUM_CONST(0) +#define DC_DISP_M1_CONTROL_0_M1_CLOCK_SELECT_M0SYNC _MK_ENUM_CONST(1) +#define DC_DISP_M1_CONTROL_0_M1_CLOCK_SELECT_LCLK _MK_ENUM_CONST(2) +#define DC_DISP_M1_CONTROL_0_M1_CLOCK_SELECT_FCLK _MK_ENUM_CONST(3) + +#define DC_DISP_M1_CONTROL_0_M1_PHASE_CONTROL_SHIFT _MK_SHIFT_CONST(4) +#define DC_DISP_M1_CONTROL_0_M1_PHASE_CONTROL_FIELD _MK_FIELD_CONST(0x3, DC_DISP_M1_CONTROL_0_M1_PHASE_CONTROL_SHIFT) +#define DC_DISP_M1_CONTROL_0_M1_PHASE_CONTROL_RANGE 5:4 +#define DC_DISP_M1_CONTROL_0_M1_PHASE_CONTROL_WOFFSET 0x0 +#define DC_DISP_M1_CONTROL_0_M1_PHASE_CONTROL_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_M1_CONTROL_0_M1_PHASE_CONTROL_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_M1_CONTROL_0_M1_PHASE_CONTROL_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_M1_CONTROL_0_M1_PHASE_CONTROL_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_M1_CONTROL_0_M1_PHASE_CONTROL_FREE_RUN _MK_ENUM_CONST(0) +#define DC_DISP_M1_CONTROL_0_M1_PHASE_CONTROL_VACTIVE_RESTART _MK_ENUM_CONST(2) +#define DC_DISP_M1_CONTROL_0_M1_PHASE_CONTROL_FRAME_INVERT _MK_ENUM_CONST(3) + +#define DC_DISP_M1_CONTROL_0_M1_PHASE_RESET_SHIFT _MK_SHIFT_CONST(6) +#define DC_DISP_M1_CONTROL_0_M1_PHASE_RESET_FIELD _MK_FIELD_CONST(0x1, DC_DISP_M1_CONTROL_0_M1_PHASE_RESET_SHIFT) +#define DC_DISP_M1_CONTROL_0_M1_PHASE_RESET_RANGE 6:6 +#define DC_DISP_M1_CONTROL_0_M1_PHASE_RESET_WOFFSET 0x0 +#define DC_DISP_M1_CONTROL_0_M1_PHASE_RESET_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_M1_CONTROL_0_M1_PHASE_RESET_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_M1_CONTROL_0_M1_PHASE_RESET_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_M1_CONTROL_0_M1_PHASE_RESET_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_M1_CONTROL_0_M1_PHASE_RESET_DISABLE _MK_ENUM_CONST(0) +#define DC_DISP_M1_CONTROL_0_M1_PHASE_RESET_ENABLE _MK_ENUM_CONST(1) + +#define DC_DISP_M1_CONTROL_0_M1_POLARITY_SHIFT _MK_SHIFT_CONST(7) +#define DC_DISP_M1_CONTROL_0_M1_POLARITY_FIELD _MK_FIELD_CONST(0x1, DC_DISP_M1_CONTROL_0_M1_POLARITY_SHIFT) +#define DC_DISP_M1_CONTROL_0_M1_POLARITY_RANGE 7:7 +#define DC_DISP_M1_CONTROL_0_M1_POLARITY_WOFFSET 0x0 +#define DC_DISP_M1_CONTROL_0_M1_POLARITY_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_M1_CONTROL_0_M1_POLARITY_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_M1_CONTROL_0_M1_POLARITY_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_M1_CONTROL_0_M1_POLARITY_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_M1_CONTROL_0_M1_POLARITY_HIGH _MK_ENUM_CONST(0) +#define DC_DISP_M1_CONTROL_0_M1_POLARITY_LOW _MK_ENUM_CONST(1) + +#define DC_DISP_M1_CONTROL_0_M1_PERIOD_SHIFT _MK_SHIFT_CONST(8) +#define DC_DISP_M1_CONTROL_0_M1_PERIOD_FIELD _MK_FIELD_CONST(0x1f, DC_DISP_M1_CONTROL_0_M1_PERIOD_SHIFT) +#define DC_DISP_M1_CONTROL_0_M1_PERIOD_RANGE 12:8 +#define DC_DISP_M1_CONTROL_0_M1_PERIOD_WOFFSET 0x0 +#define DC_DISP_M1_CONTROL_0_M1_PERIOD_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_M1_CONTROL_0_M1_PERIOD_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_M1_CONTROL_0_M1_PERIOD_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_M1_CONTROL_0_M1_PERIOD_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_DISP_M1_CONTROL_0_M1_H_POSITION_SHIFT _MK_SHIFT_CONST(16) +#define DC_DISP_M1_CONTROL_0_M1_H_POSITION_FIELD _MK_FIELD_CONST(0x1fff, DC_DISP_M1_CONTROL_0_M1_H_POSITION_SHIFT) +#define DC_DISP_M1_CONTROL_0_M1_H_POSITION_RANGE 28:16 +#define DC_DISP_M1_CONTROL_0_M1_H_POSITION_WOFFSET 0x0 +#define DC_DISP_M1_CONTROL_0_M1_H_POSITION_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_M1_CONTROL_0_M1_H_POSITION_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_M1_CONTROL_0_M1_H_POSITION_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_M1_CONTROL_0_M1_H_POSITION_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_DISP_DI_CONTROL_0 +#define DC_DISP_DI_CONTROL_0 _MK_ADDR_CONST(0x428) +#define DC_DISP_DI_CONTROL_0_SECURE 0x0 +#define DC_DISP_DI_CONTROL_0_WORD_COUNT 0x1 +#define DC_DISP_DI_CONTROL_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_DI_CONTROL_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_DI_CONTROL_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_DI_CONTROL_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_DI_CONTROL_0_READ_MASK _MK_MASK_CONST(0x1fff00d3) +#define DC_DISP_DI_CONTROL_0_WRITE_MASK _MK_MASK_CONST(0x1fff00d3) +#define DC_DISP_DI_CONTROL_0_DI_MODE_SHIFT _MK_SHIFT_CONST(0) +#define DC_DISP_DI_CONTROL_0_DI_MODE_FIELD _MK_FIELD_CONST(0x3, DC_DISP_DI_CONTROL_0_DI_MODE_SHIFT) +#define DC_DISP_DI_CONTROL_0_DI_MODE_RANGE 1:0 +#define DC_DISP_DI_CONTROL_0_DI_MODE_WOFFSET 0x0 +#define DC_DISP_DI_CONTROL_0_DI_MODE_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_DI_CONTROL_0_DI_MODE_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_DI_CONTROL_0_DI_MODE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_DI_CONTROL_0_DI_MODE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_DISP_DI_CONTROL_0_PIXDATA_INV_SELECT_SHIFT _MK_SHIFT_CONST(4) +#define DC_DISP_DI_CONTROL_0_PIXDATA_INV_SELECT_FIELD _MK_FIELD_CONST(0x1, DC_DISP_DI_CONTROL_0_PIXDATA_INV_SELECT_SHIFT) +#define DC_DISP_DI_CONTROL_0_PIXDATA_INV_SELECT_RANGE 4:4 +#define DC_DISP_DI_CONTROL_0_PIXDATA_INV_SELECT_WOFFSET 0x0 +#define DC_DISP_DI_CONTROL_0_PIXDATA_INV_SELECT_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_DI_CONTROL_0_PIXDATA_INV_SELECT_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_DI_CONTROL_0_PIXDATA_INV_SELECT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_DI_CONTROL_0_PIXDATA_INV_SELECT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_DI_CONTROL_0_PIXDATA_INV_SELECT_DI _MK_ENUM_CONST(0) +#define DC_DISP_DI_CONTROL_0_PIXDATA_INV_SELECT_DIXORM0 _MK_ENUM_CONST(1) + +#define DC_DISP_DI_CONTROL_0_PIXDATA_INV_CONTROL_SHIFT _MK_SHIFT_CONST(6) +#define DC_DISP_DI_CONTROL_0_PIXDATA_INV_CONTROL_FIELD _MK_FIELD_CONST(0x3, DC_DISP_DI_CONTROL_0_PIXDATA_INV_CONTROL_SHIFT) +#define DC_DISP_DI_CONTROL_0_PIXDATA_INV_CONTROL_RANGE 7:6 +#define DC_DISP_DI_CONTROL_0_PIXDATA_INV_CONTROL_WOFFSET 0x0 +#define DC_DISP_DI_CONTROL_0_PIXDATA_INV_CONTROL_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_DI_CONTROL_0_PIXDATA_INV_CONTROL_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_DI_CONTROL_0_PIXDATA_INV_CONTROL_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_DI_CONTROL_0_PIXDATA_INV_CONTROL_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_DI_CONTROL_0_PIXDATA_INV_CONTROL_NOINV _MK_ENUM_CONST(0) +#define DC_DISP_DI_CONTROL_0_PIXDATA_INV_CONTROL_EVENINV _MK_ENUM_CONST(1) +#define DC_DISP_DI_CONTROL_0_PIXDATA_INV_CONTROL_ODDINV _MK_ENUM_CONST(2) +#define DC_DISP_DI_CONTROL_0_PIXDATA_INV_CONTROL_ALLINV _MK_ENUM_CONST(3) + +#define DC_DISP_DI_CONTROL_0_DI_H_POSITION_SHIFT _MK_SHIFT_CONST(16) +#define DC_DISP_DI_CONTROL_0_DI_H_POSITION_FIELD _MK_FIELD_CONST(0x1fff, DC_DISP_DI_CONTROL_0_DI_H_POSITION_SHIFT) +#define DC_DISP_DI_CONTROL_0_DI_H_POSITION_RANGE 28:16 +#define DC_DISP_DI_CONTROL_0_DI_H_POSITION_WOFFSET 0x0 +#define DC_DISP_DI_CONTROL_0_DI_H_POSITION_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_DI_CONTROL_0_DI_H_POSITION_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_DI_CONTROL_0_DI_H_POSITION_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_DI_CONTROL_0_DI_H_POSITION_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_DISP_PP_CONTROL_0 +#define DC_DISP_PP_CONTROL_0 _MK_ADDR_CONST(0x429) +#define DC_DISP_PP_CONTROL_0_SECURE 0x0 +#define DC_DISP_PP_CONTROL_0_WORD_COUNT 0x1 +#define DC_DISP_PP_CONTROL_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_PP_CONTROL_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_PP_CONTROL_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_PP_CONTROL_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_PP_CONTROL_0_READ_MASK _MK_MASK_CONST(0xffff) +#define DC_DISP_PP_CONTROL_0_WRITE_MASK _MK_MASK_CONST(0xffff) +#define DC_DISP_PP_CONTROL_0_PP_DIRECTION_SHIFT _MK_SHIFT_CONST(0) +#define DC_DISP_PP_CONTROL_0_PP_DIRECTION_FIELD _MK_FIELD_CONST(0x3, DC_DISP_PP_CONTROL_0_PP_DIRECTION_SHIFT) +#define DC_DISP_PP_CONTROL_0_PP_DIRECTION_RANGE 1:0 +#define DC_DISP_PP_CONTROL_0_PP_DIRECTION_WOFFSET 0x0 +#define DC_DISP_PP_CONTROL_0_PP_DIRECTION_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_PP_CONTROL_0_PP_DIRECTION_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_PP_CONTROL_0_PP_DIRECTION_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_PP_CONTROL_0_PP_DIRECTION_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_PP_CONTROL_0_PP_DIRECTION_ALWAYS_INC _MK_ENUM_CONST(0) +#define DC_DISP_PP_CONTROL_0_PP_DIRECTION_INC_IF_DI0 _MK_ENUM_CONST(1) +#define DC_DISP_PP_CONTROL_0_PP_DIRECTION_DEC_IF_DI0 _MK_ENUM_CONST(2) +#define DC_DISP_PP_CONTROL_0_PP_DIRECTION_ALWAYS_DEC _MK_ENUM_CONST(3) + +#define DC_DISP_PP_CONTROL_0_PP_V_QUALIFIER_SHIFT _MK_SHIFT_CONST(2) +#define DC_DISP_PP_CONTROL_0_PP_V_QUALIFIER_FIELD _MK_FIELD_CONST(0x3, DC_DISP_PP_CONTROL_0_PP_V_QUALIFIER_SHIFT) +#define DC_DISP_PP_CONTROL_0_PP_V_QUALIFIER_RANGE 3:2 +#define DC_DISP_PP_CONTROL_0_PP_V_QUALIFIER_WOFFSET 0x0 +#define DC_DISP_PP_CONTROL_0_PP_V_QUALIFIER_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_PP_CONTROL_0_PP_V_QUALIFIER_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_PP_CONTROL_0_PP_V_QUALIFIER_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_PP_CONTROL_0_PP_V_QUALIFIER_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_PP_CONTROL_0_PP_V_QUALIFIER_FREE_RUN _MK_ENUM_CONST(0) +#define DC_DISP_PP_CONTROL_0_PP_V_QUALIFIER_VPULSE1 _MK_ENUM_CONST(1) +#define DC_DISP_PP_CONTROL_0_PP_V_QUALIFIER_VPULSE2 _MK_ENUM_CONST(2) +#define DC_DISP_PP_CONTROL_0_PP_V_QUALIFIER_VPULSE3 _MK_ENUM_CONST(3) + +#define DC_DISP_PP_CONTROL_0_PP_H_DELAY_SHIFT _MK_SHIFT_CONST(4) +#define DC_DISP_PP_CONTROL_0_PP_H_DELAY_FIELD _MK_FIELD_CONST(0xf, DC_DISP_PP_CONTROL_0_PP_H_DELAY_SHIFT) +#define DC_DISP_PP_CONTROL_0_PP_H_DELAY_RANGE 7:4 +#define DC_DISP_PP_CONTROL_0_PP_H_DELAY_WOFFSET 0x0 +#define DC_DISP_PP_CONTROL_0_PP_H_DELAY_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_PP_CONTROL_0_PP_H_DELAY_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_PP_CONTROL_0_PP_H_DELAY_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_PP_CONTROL_0_PP_H_DELAY_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_DISP_PP_CONTROL_0_PP_HIGH_PULSE_SHIFT _MK_SHIFT_CONST(8) +#define DC_DISP_PP_CONTROL_0_PP_HIGH_PULSE_FIELD _MK_FIELD_CONST(0xf, DC_DISP_PP_CONTROL_0_PP_HIGH_PULSE_SHIFT) +#define DC_DISP_PP_CONTROL_0_PP_HIGH_PULSE_RANGE 11:8 +#define DC_DISP_PP_CONTROL_0_PP_HIGH_PULSE_WOFFSET 0x0 +#define DC_DISP_PP_CONTROL_0_PP_HIGH_PULSE_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_PP_CONTROL_0_PP_HIGH_PULSE_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_PP_CONTROL_0_PP_HIGH_PULSE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_PP_CONTROL_0_PP_HIGH_PULSE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_DISP_PP_CONTROL_0_PP_LOW_PULSE_SHIFT _MK_SHIFT_CONST(12) +#define DC_DISP_PP_CONTROL_0_PP_LOW_PULSE_FIELD _MK_FIELD_CONST(0xf, DC_DISP_PP_CONTROL_0_PP_LOW_PULSE_SHIFT) +#define DC_DISP_PP_CONTROL_0_PP_LOW_PULSE_RANGE 15:12 +#define DC_DISP_PP_CONTROL_0_PP_LOW_PULSE_WOFFSET 0x0 +#define DC_DISP_PP_CONTROL_0_PP_LOW_PULSE_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_PP_CONTROL_0_PP_LOW_PULSE_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_PP_CONTROL_0_PP_LOW_PULSE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_PP_CONTROL_0_PP_LOW_PULSE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_DISP_PP_SELECT_A_0 +#define DC_DISP_PP_SELECT_A_0 _MK_ADDR_CONST(0x42a) +#define DC_DISP_PP_SELECT_A_0_SECURE 0x0 +#define DC_DISP_PP_SELECT_A_0_WORD_COUNT 0x1 +#define DC_DISP_PP_SELECT_A_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_PP_SELECT_A_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_PP_SELECT_A_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_PP_SELECT_A_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_PP_SELECT_A_0_READ_MASK _MK_MASK_CONST(0xffffffff) +#define DC_DISP_PP_SELECT_A_0_WRITE_MASK _MK_MASK_CONST(0xffffffff) +#define DC_DISP_PP_SELECT_A_0_PP_SELECT_A_SHIFT _MK_SHIFT_CONST(0) +#define DC_DISP_PP_SELECT_A_0_PP_SELECT_A_FIELD _MK_FIELD_CONST(0xffffffff, DC_DISP_PP_SELECT_A_0_PP_SELECT_A_SHIFT) +#define DC_DISP_PP_SELECT_A_0_PP_SELECT_A_RANGE 31:0 +#define DC_DISP_PP_SELECT_A_0_PP_SELECT_A_WOFFSET 0x0 +#define DC_DISP_PP_SELECT_A_0_PP_SELECT_A_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_PP_SELECT_A_0_PP_SELECT_A_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_PP_SELECT_A_0_PP_SELECT_A_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_PP_SELECT_A_0_PP_SELECT_A_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_DISP_PP_SELECT_B_0 +#define DC_DISP_PP_SELECT_B_0 _MK_ADDR_CONST(0x42b) +#define DC_DISP_PP_SELECT_B_0_SECURE 0x0 +#define DC_DISP_PP_SELECT_B_0_WORD_COUNT 0x1 +#define DC_DISP_PP_SELECT_B_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_PP_SELECT_B_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_PP_SELECT_B_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_PP_SELECT_B_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_PP_SELECT_B_0_READ_MASK _MK_MASK_CONST(0xffffffff) +#define DC_DISP_PP_SELECT_B_0_WRITE_MASK _MK_MASK_CONST(0xffffffff) +#define DC_DISP_PP_SELECT_B_0_PP_SELECT_B_SHIFT _MK_SHIFT_CONST(0) +#define DC_DISP_PP_SELECT_B_0_PP_SELECT_B_FIELD _MK_FIELD_CONST(0xffffffff, DC_DISP_PP_SELECT_B_0_PP_SELECT_B_SHIFT) +#define DC_DISP_PP_SELECT_B_0_PP_SELECT_B_RANGE 31:0 +#define DC_DISP_PP_SELECT_B_0_PP_SELECT_B_WOFFSET 0x0 +#define DC_DISP_PP_SELECT_B_0_PP_SELECT_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_PP_SELECT_B_0_PP_SELECT_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_PP_SELECT_B_0_PP_SELECT_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_PP_SELECT_B_0_PP_SELECT_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_DISP_PP_SELECT_C_0 +#define DC_DISP_PP_SELECT_C_0 _MK_ADDR_CONST(0x42c) +#define DC_DISP_PP_SELECT_C_0_SECURE 0x0 +#define DC_DISP_PP_SELECT_C_0_WORD_COUNT 0x1 +#define DC_DISP_PP_SELECT_C_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_PP_SELECT_C_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_PP_SELECT_C_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_PP_SELECT_C_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_PP_SELECT_C_0_READ_MASK _MK_MASK_CONST(0xffffffff) +#define DC_DISP_PP_SELECT_C_0_WRITE_MASK _MK_MASK_CONST(0xffffffff) +#define DC_DISP_PP_SELECT_C_0_PP_SELECT_C_SHIFT _MK_SHIFT_CONST(0) +#define DC_DISP_PP_SELECT_C_0_PP_SELECT_C_FIELD _MK_FIELD_CONST(0xffffffff, DC_DISP_PP_SELECT_C_0_PP_SELECT_C_SHIFT) +#define DC_DISP_PP_SELECT_C_0_PP_SELECT_C_RANGE 31:0 +#define DC_DISP_PP_SELECT_C_0_PP_SELECT_C_WOFFSET 0x0 +#define DC_DISP_PP_SELECT_C_0_PP_SELECT_C_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_PP_SELECT_C_0_PP_SELECT_C_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_PP_SELECT_C_0_PP_SELECT_C_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_PP_SELECT_C_0_PP_SELECT_C_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_DISP_PP_SELECT_D_0 +#define DC_DISP_PP_SELECT_D_0 _MK_ADDR_CONST(0x42d) +#define DC_DISP_PP_SELECT_D_0_SECURE 0x0 +#define DC_DISP_PP_SELECT_D_0_WORD_COUNT 0x1 +#define DC_DISP_PP_SELECT_D_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_PP_SELECT_D_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_PP_SELECT_D_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_PP_SELECT_D_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_PP_SELECT_D_0_READ_MASK _MK_MASK_CONST(0xffffffff) +#define DC_DISP_PP_SELECT_D_0_WRITE_MASK _MK_MASK_CONST(0xffffffff) +#define DC_DISP_PP_SELECT_D_0_PP_SELECT_D_SHIFT _MK_SHIFT_CONST(0) +#define DC_DISP_PP_SELECT_D_0_PP_SELECT_D_FIELD _MK_FIELD_CONST(0xffffffff, DC_DISP_PP_SELECT_D_0_PP_SELECT_D_SHIFT) +#define DC_DISP_PP_SELECT_D_0_PP_SELECT_D_RANGE 31:0 +#define DC_DISP_PP_SELECT_D_0_PP_SELECT_D_WOFFSET 0x0 +#define DC_DISP_PP_SELECT_D_0_PP_SELECT_D_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_PP_SELECT_D_0_PP_SELECT_D_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_PP_SELECT_D_0_PP_SELECT_D_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_PP_SELECT_D_0_PP_SELECT_D_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_DISP_DISP_CLOCK_CONTROL_0 +#define DC_DISP_DISP_CLOCK_CONTROL_0 _MK_ADDR_CONST(0x42e) +#define DC_DISP_DISP_CLOCK_CONTROL_0_SECURE 0x0 +#define DC_DISP_DISP_CLOCK_CONTROL_0_WORD_COUNT 0x1 +#define DC_DISP_DISP_CLOCK_CONTROL_0_RESET_VAL _MK_MASK_CONST(0x6) +#define DC_DISP_DISP_CLOCK_CONTROL_0_RESET_MASK _MK_MASK_CONST(0xfff) +#define DC_DISP_DISP_CLOCK_CONTROL_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_DISP_CLOCK_CONTROL_0_SW_DEFAULT_MASK _MK_MASK_CONST(0xf00) +#define DC_DISP_DISP_CLOCK_CONTROL_0_READ_MASK _MK_MASK_CONST(0xfff) +#define DC_DISP_DISP_CLOCK_CONTROL_0_WRITE_MASK _MK_MASK_CONST(0xfff) +#define DC_DISP_DISP_CLOCK_CONTROL_0_SHIFT_CLK_DIVIDER_SHIFT _MK_SHIFT_CONST(0) +#define DC_DISP_DISP_CLOCK_CONTROL_0_SHIFT_CLK_DIVIDER_FIELD _MK_FIELD_CONST(0xff, DC_DISP_DISP_CLOCK_CONTROL_0_SHIFT_CLK_DIVIDER_SHIFT) +#define DC_DISP_DISP_CLOCK_CONTROL_0_SHIFT_CLK_DIVIDER_RANGE 7:0 +#define DC_DISP_DISP_CLOCK_CONTROL_0_SHIFT_CLK_DIVIDER_WOFFSET 0x0 +#define DC_DISP_DISP_CLOCK_CONTROL_0_SHIFT_CLK_DIVIDER_DEFAULT _MK_MASK_CONST(0x6) +#define DC_DISP_DISP_CLOCK_CONTROL_0_SHIFT_CLK_DIVIDER_DEFAULT_MASK _MK_MASK_CONST(0xff) +#define DC_DISP_DISP_CLOCK_CONTROL_0_SHIFT_CLK_DIVIDER_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_DISP_CLOCK_CONTROL_0_SHIFT_CLK_DIVIDER_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_DISP_DISP_CLOCK_CONTROL_0_PIXEL_CLK_DIVIDER_SHIFT _MK_SHIFT_CONST(8) +#define DC_DISP_DISP_CLOCK_CONTROL_0_PIXEL_CLK_DIVIDER_FIELD _MK_FIELD_CONST(0xf, DC_DISP_DISP_CLOCK_CONTROL_0_PIXEL_CLK_DIVIDER_SHIFT) +#define DC_DISP_DISP_CLOCK_CONTROL_0_PIXEL_CLK_DIVIDER_RANGE 11:8 +#define DC_DISP_DISP_CLOCK_CONTROL_0_PIXEL_CLK_DIVIDER_WOFFSET 0x0 +#define DC_DISP_DISP_CLOCK_CONTROL_0_PIXEL_CLK_DIVIDER_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_DISP_CLOCK_CONTROL_0_PIXEL_CLK_DIVIDER_DEFAULT_MASK _MK_MASK_CONST(0xf) +#define DC_DISP_DISP_CLOCK_CONTROL_0_PIXEL_CLK_DIVIDER_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_DISP_CLOCK_CONTROL_0_PIXEL_CLK_DIVIDER_SW_DEFAULT_MASK _MK_MASK_CONST(0xf) +#define DC_DISP_DISP_CLOCK_CONTROL_0_PIXEL_CLK_DIVIDER_PCD1 _MK_ENUM_CONST(0) +#define DC_DISP_DISP_CLOCK_CONTROL_0_PIXEL_CLK_DIVIDER_PCD1H _MK_ENUM_CONST(1) +#define DC_DISP_DISP_CLOCK_CONTROL_0_PIXEL_CLK_DIVIDER_PCD2 _MK_ENUM_CONST(2) +#define DC_DISP_DISP_CLOCK_CONTROL_0_PIXEL_CLK_DIVIDER_PCD3 _MK_ENUM_CONST(3) +#define DC_DISP_DISP_CLOCK_CONTROL_0_PIXEL_CLK_DIVIDER_PCD4 _MK_ENUM_CONST(4) +#define DC_DISP_DISP_CLOCK_CONTROL_0_PIXEL_CLK_DIVIDER_PCD6 _MK_ENUM_CONST(5) +#define DC_DISP_DISP_CLOCK_CONTROL_0_PIXEL_CLK_DIVIDER_PCD8 _MK_ENUM_CONST(6) +#define DC_DISP_DISP_CLOCK_CONTROL_0_PIXEL_CLK_DIVIDER_PCD9 _MK_ENUM_CONST(7) +#define DC_DISP_DISP_CLOCK_CONTROL_0_PIXEL_CLK_DIVIDER_PCD12 _MK_ENUM_CONST(8) +#define DC_DISP_DISP_CLOCK_CONTROL_0_PIXEL_CLK_DIVIDER_PCD16 _MK_ENUM_CONST(9) +#define DC_DISP_DISP_CLOCK_CONTROL_0_PIXEL_CLK_DIVIDER_PCD18 _MK_ENUM_CONST(10) +#define DC_DISP_DISP_CLOCK_CONTROL_0_PIXEL_CLK_DIVIDER_PCD24 _MK_ENUM_CONST(11) +#define DC_DISP_DISP_CLOCK_CONTROL_0_PIXEL_CLK_DIVIDER_PCD13 _MK_ENUM_CONST(12) + + +// Register DC_DISP_DISP_INTERFACE_CONTROL_0 +#define DC_DISP_DISP_INTERFACE_CONTROL_0 _MK_ADDR_CONST(0x42f) +#define DC_DISP_DISP_INTERFACE_CONTROL_0_SECURE 0x0 +#define DC_DISP_DISP_INTERFACE_CONTROL_0_WORD_COUNT 0x1 +#define DC_DISP_DISP_INTERFACE_CONTROL_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_DISP_INTERFACE_CONTROL_0_RESET_MASK _MK_MASK_CONST(0x30f) +#define DC_DISP_DISP_INTERFACE_CONTROL_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_DISP_INTERFACE_CONTROL_0_SW_DEFAULT_MASK _MK_MASK_CONST(0xf) +#define DC_DISP_DISP_INTERFACE_CONTROL_0_READ_MASK _MK_MASK_CONST(0x30f) +#define DC_DISP_DISP_INTERFACE_CONTROL_0_WRITE_MASK _MK_MASK_CONST(0x30f) +#define DC_DISP_DISP_INTERFACE_CONTROL_0_DISP_DATA_FORMAT_SHIFT _MK_SHIFT_CONST(0) +#define DC_DISP_DISP_INTERFACE_CONTROL_0_DISP_DATA_FORMAT_FIELD _MK_FIELD_CONST(0xf, DC_DISP_DISP_INTERFACE_CONTROL_0_DISP_DATA_FORMAT_SHIFT) +#define DC_DISP_DISP_INTERFACE_CONTROL_0_DISP_DATA_FORMAT_RANGE 3:0 +#define DC_DISP_DISP_INTERFACE_CONTROL_0_DISP_DATA_FORMAT_WOFFSET 0x0 +#define DC_DISP_DISP_INTERFACE_CONTROL_0_DISP_DATA_FORMAT_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_DISP_INTERFACE_CONTROL_0_DISP_DATA_FORMAT_DEFAULT_MASK _MK_MASK_CONST(0xf) +#define DC_DISP_DISP_INTERFACE_CONTROL_0_DISP_DATA_FORMAT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_DISP_INTERFACE_CONTROL_0_DISP_DATA_FORMAT_SW_DEFAULT_MASK _MK_MASK_CONST(0xf) +#define DC_DISP_DISP_INTERFACE_CONTROL_0_DISP_DATA_FORMAT_DF1P1C _MK_ENUM_CONST(0) +#define DC_DISP_DISP_INTERFACE_CONTROL_0_DISP_DATA_FORMAT_DF1P2C24B _MK_ENUM_CONST(1) +#define DC_DISP_DISP_INTERFACE_CONTROL_0_DISP_DATA_FORMAT_DF1P2C18B _MK_ENUM_CONST(2) +#define DC_DISP_DISP_INTERFACE_CONTROL_0_DISP_DATA_FORMAT_DF1P2C16B _MK_ENUM_CONST(3) +#define DC_DISP_DISP_INTERFACE_CONTROL_0_DISP_DATA_FORMAT_DF1S _MK_ENUM_CONST(4) +#define DC_DISP_DISP_INTERFACE_CONTROL_0_DISP_DATA_FORMAT_DF2S _MK_ENUM_CONST(5) +#define DC_DISP_DISP_INTERFACE_CONTROL_0_DISP_DATA_FORMAT_DF3S _MK_ENUM_CONST(6) +#define DC_DISP_DISP_INTERFACE_CONTROL_0_DISP_DATA_FORMAT_DFSPI _MK_ENUM_CONST(7) +#define DC_DISP_DISP_INTERFACE_CONTROL_0_DISP_DATA_FORMAT_DF1P3C24B _MK_ENUM_CONST(8) +#define DC_DISP_DISP_INTERFACE_CONTROL_0_DISP_DATA_FORMAT_DF2P1C18B _MK_ENUM_CONST(9) +#define DC_DISP_DISP_INTERFACE_CONTROL_0_DISP_DATA_FORMAT_DFDUAL1P1C18B _MK_ENUM_CONST(10) + +#define DC_DISP_DISP_INTERFACE_CONTROL_0_DISP_DATA_ALIGNMENT_SHIFT _MK_SHIFT_CONST(8) +#define DC_DISP_DISP_INTERFACE_CONTROL_0_DISP_DATA_ALIGNMENT_FIELD _MK_FIELD_CONST(0x1, DC_DISP_DISP_INTERFACE_CONTROL_0_DISP_DATA_ALIGNMENT_SHIFT) +#define DC_DISP_DISP_INTERFACE_CONTROL_0_DISP_DATA_ALIGNMENT_RANGE 8:8 +#define DC_DISP_DISP_INTERFACE_CONTROL_0_DISP_DATA_ALIGNMENT_WOFFSET 0x0 +#define DC_DISP_DISP_INTERFACE_CONTROL_0_DISP_DATA_ALIGNMENT_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_DISP_INTERFACE_CONTROL_0_DISP_DATA_ALIGNMENT_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_DISP_DISP_INTERFACE_CONTROL_0_DISP_DATA_ALIGNMENT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_DISP_INTERFACE_CONTROL_0_DISP_DATA_ALIGNMENT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_DISP_INTERFACE_CONTROL_0_DISP_DATA_ALIGNMENT_MSB _MK_ENUM_CONST(0) +#define DC_DISP_DISP_INTERFACE_CONTROL_0_DISP_DATA_ALIGNMENT_LSB _MK_ENUM_CONST(1) + +#define DC_DISP_DISP_INTERFACE_CONTROL_0_DISP_DATA_ORDER_SHIFT _MK_SHIFT_CONST(9) +#define DC_DISP_DISP_INTERFACE_CONTROL_0_DISP_DATA_ORDER_FIELD _MK_FIELD_CONST(0x1, DC_DISP_DISP_INTERFACE_CONTROL_0_DISP_DATA_ORDER_SHIFT) +#define DC_DISP_DISP_INTERFACE_CONTROL_0_DISP_DATA_ORDER_RANGE 9:9 +#define DC_DISP_DISP_INTERFACE_CONTROL_0_DISP_DATA_ORDER_WOFFSET 0x0 +#define DC_DISP_DISP_INTERFACE_CONTROL_0_DISP_DATA_ORDER_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_DISP_INTERFACE_CONTROL_0_DISP_DATA_ORDER_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_DISP_DISP_INTERFACE_CONTROL_0_DISP_DATA_ORDER_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_DISP_INTERFACE_CONTROL_0_DISP_DATA_ORDER_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_DISP_INTERFACE_CONTROL_0_DISP_DATA_ORDER_RED_BLUE _MK_ENUM_CONST(0) +#define DC_DISP_DISP_INTERFACE_CONTROL_0_DISP_DATA_ORDER_BLUE_RED _MK_ENUM_CONST(1) + + +// Register DC_DISP_DISP_COLOR_CONTROL_0 +#define DC_DISP_DISP_COLOR_CONTROL_0 _MK_ADDR_CONST(0x430) +#define DC_DISP_DISP_COLOR_CONTROL_0_SECURE 0x0 +#define DC_DISP_DISP_COLOR_CONTROL_0_WORD_COUNT 0x1 +#define DC_DISP_DISP_COLOR_CONTROL_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_DISP_COLOR_CONTROL_0_RESET_MASK _MK_MASK_CONST(0xf1530cf) +#define DC_DISP_DISP_COLOR_CONTROL_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_DISP_COLOR_CONTROL_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_DISP_COLOR_CONTROL_0_READ_MASK _MK_MASK_CONST(0xf1733cf) +#define DC_DISP_DISP_COLOR_CONTROL_0_WRITE_MASK _MK_MASK_CONST(0xf1733cf) +#define DC_DISP_DISP_COLOR_CONTROL_0_BASE_COLOR_SIZE_SHIFT _MK_SHIFT_CONST(0) +#define DC_DISP_DISP_COLOR_CONTROL_0_BASE_COLOR_SIZE_FIELD _MK_FIELD_CONST(0xf, DC_DISP_DISP_COLOR_CONTROL_0_BASE_COLOR_SIZE_SHIFT) +#define DC_DISP_DISP_COLOR_CONTROL_0_BASE_COLOR_SIZE_RANGE 3:0 +#define DC_DISP_DISP_COLOR_CONTROL_0_BASE_COLOR_SIZE_WOFFSET 0x0 +#define DC_DISP_DISP_COLOR_CONTROL_0_BASE_COLOR_SIZE_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_DISP_COLOR_CONTROL_0_BASE_COLOR_SIZE_DEFAULT_MASK _MK_MASK_CONST(0xf) +#define DC_DISP_DISP_COLOR_CONTROL_0_BASE_COLOR_SIZE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_DISP_COLOR_CONTROL_0_BASE_COLOR_SIZE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_DISP_COLOR_CONTROL_0_BASE_COLOR_SIZE_BASE666 _MK_ENUM_CONST(0) +#define DC_DISP_DISP_COLOR_CONTROL_0_BASE_COLOR_SIZE_BASE111 _MK_ENUM_CONST(1) +#define DC_DISP_DISP_COLOR_CONTROL_0_BASE_COLOR_SIZE_BASE222 _MK_ENUM_CONST(2) +#define DC_DISP_DISP_COLOR_CONTROL_0_BASE_COLOR_SIZE_BASE333 _MK_ENUM_CONST(3) +#define DC_DISP_DISP_COLOR_CONTROL_0_BASE_COLOR_SIZE_BASE444 _MK_ENUM_CONST(4) +#define DC_DISP_DISP_COLOR_CONTROL_0_BASE_COLOR_SIZE_BASE555 _MK_ENUM_CONST(5) +#define DC_DISP_DISP_COLOR_CONTROL_0_BASE_COLOR_SIZE_BASE565 _MK_ENUM_CONST(6) +#define DC_DISP_DISP_COLOR_CONTROL_0_BASE_COLOR_SIZE_BASE332 _MK_ENUM_CONST(7) +#define DC_DISP_DISP_COLOR_CONTROL_0_BASE_COLOR_SIZE_BASE888 _MK_ENUM_CONST(8) + +#define DC_DISP_DISP_COLOR_CONTROL_0_TEMPORAL_DITHER_PHASE_SHIFT _MK_SHIFT_CONST(6) +#define DC_DISP_DISP_COLOR_CONTROL_0_TEMPORAL_DITHER_PHASE_FIELD _MK_FIELD_CONST(0x3, DC_DISP_DISP_COLOR_CONTROL_0_TEMPORAL_DITHER_PHASE_SHIFT) +#define DC_DISP_DISP_COLOR_CONTROL_0_TEMPORAL_DITHER_PHASE_RANGE 7:6 +#define DC_DISP_DISP_COLOR_CONTROL_0_TEMPORAL_DITHER_PHASE_WOFFSET 0x0 +#define DC_DISP_DISP_COLOR_CONTROL_0_TEMPORAL_DITHER_PHASE_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_DISP_COLOR_CONTROL_0_TEMPORAL_DITHER_PHASE_DEFAULT_MASK _MK_MASK_CONST(0x3) +#define DC_DISP_DISP_COLOR_CONTROL_0_TEMPORAL_DITHER_PHASE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_DISP_COLOR_CONTROL_0_TEMPORAL_DITHER_PHASE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_DISP_DISP_COLOR_CONTROL_0_DITHER_CONTROL_SHIFT _MK_SHIFT_CONST(8) +#define DC_DISP_DISP_COLOR_CONTROL_0_DITHER_CONTROL_FIELD _MK_FIELD_CONST(0x3, DC_DISP_DISP_COLOR_CONTROL_0_DITHER_CONTROL_SHIFT) +#define DC_DISP_DISP_COLOR_CONTROL_0_DITHER_CONTROL_RANGE 9:8 +#define DC_DISP_DISP_COLOR_CONTROL_0_DITHER_CONTROL_WOFFSET 0x0 +#define DC_DISP_DISP_COLOR_CONTROL_0_DITHER_CONTROL_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_DISP_COLOR_CONTROL_0_DITHER_CONTROL_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_DISP_COLOR_CONTROL_0_DITHER_CONTROL_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_DISP_COLOR_CONTROL_0_DITHER_CONTROL_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_DISP_COLOR_CONTROL_0_DITHER_CONTROL_DISABLE _MK_ENUM_CONST(0) +#define DC_DISP_DISP_COLOR_CONTROL_0_DITHER_CONTROL_ORDERED _MK_ENUM_CONST(2) +#define DC_DISP_DISP_COLOR_CONTROL_0_DITHER_CONTROL_TEMPORAL _MK_ENUM_CONST(3) + +#define DC_DISP_DISP_COLOR_CONTROL_0_ORD_DITHER_ROTATION_SHIFT _MK_SHIFT_CONST(12) +#define DC_DISP_DISP_COLOR_CONTROL_0_ORD_DITHER_ROTATION_FIELD _MK_FIELD_CONST(0x3, DC_DISP_DISP_COLOR_CONTROL_0_ORD_DITHER_ROTATION_SHIFT) +#define DC_DISP_DISP_COLOR_CONTROL_0_ORD_DITHER_ROTATION_RANGE 13:12 +#define DC_DISP_DISP_COLOR_CONTROL_0_ORD_DITHER_ROTATION_WOFFSET 0x0 +#define DC_DISP_DISP_COLOR_CONTROL_0_ORD_DITHER_ROTATION_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_DISP_COLOR_CONTROL_0_ORD_DITHER_ROTATION_DEFAULT_MASK _MK_MASK_CONST(0x3) +#define DC_DISP_DISP_COLOR_CONTROL_0_ORD_DITHER_ROTATION_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_DISP_COLOR_CONTROL_0_ORD_DITHER_ROTATION_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_DISP_DISP_COLOR_CONTROL_0_DISP_COLOR_SWAP_SHIFT _MK_SHIFT_CONST(16) +#define DC_DISP_DISP_COLOR_CONTROL_0_DISP_COLOR_SWAP_FIELD _MK_FIELD_CONST(0x1, DC_DISP_DISP_COLOR_CONTROL_0_DISP_COLOR_SWAP_SHIFT) +#define DC_DISP_DISP_COLOR_CONTROL_0_DISP_COLOR_SWAP_RANGE 16:16 +#define DC_DISP_DISP_COLOR_CONTROL_0_DISP_COLOR_SWAP_WOFFSET 0x0 +#define DC_DISP_DISP_COLOR_CONTROL_0_DISP_COLOR_SWAP_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_DISP_COLOR_CONTROL_0_DISP_COLOR_SWAP_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_DISP_DISP_COLOR_CONTROL_0_DISP_COLOR_SWAP_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_DISP_COLOR_CONTROL_0_DISP_COLOR_SWAP_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_DISP_COLOR_CONTROL_0_DISP_COLOR_SWAP_RGB _MK_ENUM_CONST(0) +#define DC_DISP_DISP_COLOR_CONTROL_0_DISP_COLOR_SWAP_BGR _MK_ENUM_CONST(1) + +#define DC_DISP_DISP_COLOR_CONTROL_0_BLANK_COLOR_SHIFT _MK_SHIFT_CONST(17) +#define DC_DISP_DISP_COLOR_CONTROL_0_BLANK_COLOR_FIELD _MK_FIELD_CONST(0x1, DC_DISP_DISP_COLOR_CONTROL_0_BLANK_COLOR_SHIFT) +#define DC_DISP_DISP_COLOR_CONTROL_0_BLANK_COLOR_RANGE 17:17 +#define DC_DISP_DISP_COLOR_CONTROL_0_BLANK_COLOR_WOFFSET 0x0 +#define DC_DISP_DISP_COLOR_CONTROL_0_BLANK_COLOR_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_DISP_COLOR_CONTROL_0_BLANK_COLOR_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_DISP_COLOR_CONTROL_0_BLANK_COLOR_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_DISP_COLOR_CONTROL_0_BLANK_COLOR_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_DISP_DISP_COLOR_CONTROL_0_NON_BASE_COLOR_SHIFT _MK_SHIFT_CONST(18) +#define DC_DISP_DISP_COLOR_CONTROL_0_NON_BASE_COLOR_FIELD _MK_FIELD_CONST(0x1, DC_DISP_DISP_COLOR_CONTROL_0_NON_BASE_COLOR_SHIFT) +#define DC_DISP_DISP_COLOR_CONTROL_0_NON_BASE_COLOR_RANGE 18:18 +#define DC_DISP_DISP_COLOR_CONTROL_0_NON_BASE_COLOR_WOFFSET 0x0 +#define DC_DISP_DISP_COLOR_CONTROL_0_NON_BASE_COLOR_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_DISP_COLOR_CONTROL_0_NON_BASE_COLOR_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_DISP_DISP_COLOR_CONTROL_0_NON_BASE_COLOR_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_DISP_COLOR_CONTROL_0_NON_BASE_COLOR_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_DISP_DISP_COLOR_CONTROL_0_CMU_ENABLE_SHIFT _MK_SHIFT_CONST(20) +#define DC_DISP_DISP_COLOR_CONTROL_0_CMU_ENABLE_FIELD _MK_FIELD_CONST(0x1, DC_DISP_DISP_COLOR_CONTROL_0_CMU_ENABLE_SHIFT) +#define DC_DISP_DISP_COLOR_CONTROL_0_CMU_ENABLE_RANGE 20:20 +#define DC_DISP_DISP_COLOR_CONTROL_0_CMU_ENABLE_WOFFSET 0x0 +#define DC_DISP_DISP_COLOR_CONTROL_0_CMU_ENABLE_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_DISP_COLOR_CONTROL_0_CMU_ENABLE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_DISP_DISP_COLOR_CONTROL_0_CMU_ENABLE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_DISP_COLOR_CONTROL_0_CMU_ENABLE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_DISP_COLOR_CONTROL_0_CMU_ENABLE_INIT_ENUM DISABLE +#define DC_DISP_DISP_COLOR_CONTROL_0_CMU_ENABLE_DISABLE _MK_ENUM_CONST(0) +#define DC_DISP_DISP_COLOR_CONTROL_0_CMU_ENABLE_ENABLE _MK_ENUM_CONST(1) + +#define DC_DISP_DISP_COLOR_CONTROL_0_LCD_MD0_SHIFT _MK_SHIFT_CONST(24) +#define DC_DISP_DISP_COLOR_CONTROL_0_LCD_MD0_FIELD _MK_FIELD_CONST(0x1, DC_DISP_DISP_COLOR_CONTROL_0_LCD_MD0_SHIFT) +#define DC_DISP_DISP_COLOR_CONTROL_0_LCD_MD0_RANGE 24:24 +#define DC_DISP_DISP_COLOR_CONTROL_0_LCD_MD0_WOFFSET 0x0 +#define DC_DISP_DISP_COLOR_CONTROL_0_LCD_MD0_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_DISP_COLOR_CONTROL_0_LCD_MD0_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_DISP_DISP_COLOR_CONTROL_0_LCD_MD0_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_DISP_COLOR_CONTROL_0_LCD_MD0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_DISP_COLOR_CONTROL_0_LCD_MD0_LOW _MK_ENUM_CONST(0) +#define DC_DISP_DISP_COLOR_CONTROL_0_LCD_MD0_HIGH _MK_ENUM_CONST(1) + +#define DC_DISP_DISP_COLOR_CONTROL_0_LCD_MD1_SHIFT _MK_SHIFT_CONST(25) +#define DC_DISP_DISP_COLOR_CONTROL_0_LCD_MD1_FIELD _MK_FIELD_CONST(0x1, DC_DISP_DISP_COLOR_CONTROL_0_LCD_MD1_SHIFT) +#define DC_DISP_DISP_COLOR_CONTROL_0_LCD_MD1_RANGE 25:25 +#define DC_DISP_DISP_COLOR_CONTROL_0_LCD_MD1_WOFFSET 0x0 +#define DC_DISP_DISP_COLOR_CONTROL_0_LCD_MD1_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_DISP_COLOR_CONTROL_0_LCD_MD1_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_DISP_DISP_COLOR_CONTROL_0_LCD_MD1_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_DISP_COLOR_CONTROL_0_LCD_MD1_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_DISP_COLOR_CONTROL_0_LCD_MD1_LOW _MK_ENUM_CONST(0) +#define DC_DISP_DISP_COLOR_CONTROL_0_LCD_MD1_HIGH _MK_ENUM_CONST(1) + +#define DC_DISP_DISP_COLOR_CONTROL_0_LCD_MD2_SHIFT _MK_SHIFT_CONST(26) +#define DC_DISP_DISP_COLOR_CONTROL_0_LCD_MD2_FIELD _MK_FIELD_CONST(0x1, DC_DISP_DISP_COLOR_CONTROL_0_LCD_MD2_SHIFT) +#define DC_DISP_DISP_COLOR_CONTROL_0_LCD_MD2_RANGE 26:26 +#define DC_DISP_DISP_COLOR_CONTROL_0_LCD_MD2_WOFFSET 0x0 +#define DC_DISP_DISP_COLOR_CONTROL_0_LCD_MD2_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_DISP_COLOR_CONTROL_0_LCD_MD2_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_DISP_DISP_COLOR_CONTROL_0_LCD_MD2_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_DISP_COLOR_CONTROL_0_LCD_MD2_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_DISP_COLOR_CONTROL_0_LCD_MD2_LOW _MK_ENUM_CONST(0) +#define DC_DISP_DISP_COLOR_CONTROL_0_LCD_MD2_HIGH _MK_ENUM_CONST(1) + +#define DC_DISP_DISP_COLOR_CONTROL_0_LCD_MD3_SHIFT _MK_SHIFT_CONST(27) +#define DC_DISP_DISP_COLOR_CONTROL_0_LCD_MD3_FIELD _MK_FIELD_CONST(0x1, DC_DISP_DISP_COLOR_CONTROL_0_LCD_MD3_SHIFT) +#define DC_DISP_DISP_COLOR_CONTROL_0_LCD_MD3_RANGE 27:27 +#define DC_DISP_DISP_COLOR_CONTROL_0_LCD_MD3_WOFFSET 0x0 +#define DC_DISP_DISP_COLOR_CONTROL_0_LCD_MD3_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_DISP_COLOR_CONTROL_0_LCD_MD3_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_DISP_DISP_COLOR_CONTROL_0_LCD_MD3_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_DISP_COLOR_CONTROL_0_LCD_MD3_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_DISP_COLOR_CONTROL_0_LCD_MD3_LOW _MK_ENUM_CONST(0) +#define DC_DISP_DISP_COLOR_CONTROL_0_LCD_MD3_HIGH _MK_ENUM_CONST(1) + + +// Register DC_DISP_SHIFT_CLOCK_OPTIONS_0 +#define DC_DISP_SHIFT_CLOCK_OPTIONS_0 _MK_ADDR_CONST(0x431) +#define DC_DISP_SHIFT_CLOCK_OPTIONS_0_SECURE 0x0 +#define DC_DISP_SHIFT_CLOCK_OPTIONS_0_WORD_COUNT 0x1 +#define DC_DISP_SHIFT_CLOCK_OPTIONS_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_SHIFT_CLOCK_OPTIONS_0_RESET_MASK _MK_MASK_CONST(0xff00ff) +#define DC_DISP_SHIFT_CLOCK_OPTIONS_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_SHIFT_CLOCK_OPTIONS_0_SW_DEFAULT_MASK _MK_MASK_CONST(0xc0) +#define DC_DISP_SHIFT_CLOCK_OPTIONS_0_READ_MASK _MK_MASK_CONST(0xff00ff) +#define DC_DISP_SHIFT_CLOCK_OPTIONS_0_WRITE_MASK _MK_MASK_CONST(0xff00ff) +#define DC_DISP_SHIFT_CLOCK_OPTIONS_0_SC0_H_QUALIFIER_SHIFT _MK_SHIFT_CONST(0) +#define DC_DISP_SHIFT_CLOCK_OPTIONS_0_SC0_H_QUALIFIER_FIELD _MK_FIELD_CONST(0x7, DC_DISP_SHIFT_CLOCK_OPTIONS_0_SC0_H_QUALIFIER_SHIFT) +#define DC_DISP_SHIFT_CLOCK_OPTIONS_0_SC0_H_QUALIFIER_RANGE 2:0 +#define DC_DISP_SHIFT_CLOCK_OPTIONS_0_SC0_H_QUALIFIER_WOFFSET 0x0 +#define DC_DISP_SHIFT_CLOCK_OPTIONS_0_SC0_H_QUALIFIER_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SHIFT_CLOCK_OPTIONS_0_SC0_H_QUALIFIER_DEFAULT_MASK _MK_MASK_CONST(0x7) +#define DC_DISP_SHIFT_CLOCK_OPTIONS_0_SC0_H_QUALIFIER_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SHIFT_CLOCK_OPTIONS_0_SC0_H_QUALIFIER_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_SHIFT_CLOCK_OPTIONS_0_SC0_H_QUALIFIER_DISABLE _MK_ENUM_CONST(0) +#define DC_DISP_SHIFT_CLOCK_OPTIONS_0_SC0_H_QUALIFIER_NO_HQUAL _MK_ENUM_CONST(1) +#define DC_DISP_SHIFT_CLOCK_OPTIONS_0_SC0_H_QUALIFIER_HACTIVE _MK_ENUM_CONST(2) +#define DC_DISP_SHIFT_CLOCK_OPTIONS_0_SC0_H_QUALIFIER_EXT_HACTIVE _MK_ENUM_CONST(3) +#define DC_DISP_SHIFT_CLOCK_OPTIONS_0_SC0_H_QUALIFIER_HPULSE0 _MK_ENUM_CONST(4) +#define DC_DISP_SHIFT_CLOCK_OPTIONS_0_SC0_H_QUALIFIER_EXT_HPULSE0 _MK_ENUM_CONST(5) + +#define DC_DISP_SHIFT_CLOCK_OPTIONS_0_SC0_V_QUALIFIER_SHIFT _MK_SHIFT_CONST(3) +#define DC_DISP_SHIFT_CLOCK_OPTIONS_0_SC0_V_QUALIFIER_FIELD _MK_FIELD_CONST(0x7, DC_DISP_SHIFT_CLOCK_OPTIONS_0_SC0_V_QUALIFIER_SHIFT) +#define DC_DISP_SHIFT_CLOCK_OPTIONS_0_SC0_V_QUALIFIER_RANGE 5:3 +#define DC_DISP_SHIFT_CLOCK_OPTIONS_0_SC0_V_QUALIFIER_WOFFSET 0x0 +#define DC_DISP_SHIFT_CLOCK_OPTIONS_0_SC0_V_QUALIFIER_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SHIFT_CLOCK_OPTIONS_0_SC0_V_QUALIFIER_DEFAULT_MASK _MK_MASK_CONST(0x7) +#define DC_DISP_SHIFT_CLOCK_OPTIONS_0_SC0_V_QUALIFIER_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SHIFT_CLOCK_OPTIONS_0_SC0_V_QUALIFIER_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_SHIFT_CLOCK_OPTIONS_0_SC0_V_QUALIFIER_NO_VQUAL _MK_ENUM_CONST(0) +#define DC_DISP_SHIFT_CLOCK_OPTIONS_0_SC0_V_QUALIFIER_RESERVED _MK_ENUM_CONST(1) +#define DC_DISP_SHIFT_CLOCK_OPTIONS_0_SC0_V_QUALIFIER_VACTIVE _MK_ENUM_CONST(2) +#define DC_DISP_SHIFT_CLOCK_OPTIONS_0_SC0_V_QUALIFIER_EXT_VACTIVE _MK_ENUM_CONST(3) +#define DC_DISP_SHIFT_CLOCK_OPTIONS_0_SC0_V_QUALIFIER_VPULSE0 _MK_ENUM_CONST(4) +#define DC_DISP_SHIFT_CLOCK_OPTIONS_0_SC0_V_QUALIFIER_EXT_VPULSE0 _MK_ENUM_CONST(5) + +#define DC_DISP_SHIFT_CLOCK_OPTIONS_0_SC0_CLK_DIVIDER_SHIFT _MK_SHIFT_CONST(6) +#define DC_DISP_SHIFT_CLOCK_OPTIONS_0_SC0_CLK_DIVIDER_FIELD _MK_FIELD_CONST(0x3, DC_DISP_SHIFT_CLOCK_OPTIONS_0_SC0_CLK_DIVIDER_SHIFT) +#define DC_DISP_SHIFT_CLOCK_OPTIONS_0_SC0_CLK_DIVIDER_RANGE 7:6 +#define DC_DISP_SHIFT_CLOCK_OPTIONS_0_SC0_CLK_DIVIDER_WOFFSET 0x0 +#define DC_DISP_SHIFT_CLOCK_OPTIONS_0_SC0_CLK_DIVIDER_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SHIFT_CLOCK_OPTIONS_0_SC0_CLK_DIVIDER_DEFAULT_MASK _MK_MASK_CONST(0x3) +#define DC_DISP_SHIFT_CLOCK_OPTIONS_0_SC0_CLK_DIVIDER_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SHIFT_CLOCK_OPTIONS_0_SC0_CLK_DIVIDER_SW_DEFAULT_MASK _MK_MASK_CONST(0x3) +#define DC_DISP_SHIFT_CLOCK_OPTIONS_0_SC0_CLK_DIVIDER_DIV1 _MK_ENUM_CONST(0) +#define DC_DISP_SHIFT_CLOCK_OPTIONS_0_SC0_CLK_DIVIDER_DIV2 _MK_ENUM_CONST(1) +#define DC_DISP_SHIFT_CLOCK_OPTIONS_0_SC0_CLK_DIVIDER_DIV4 _MK_ENUM_CONST(2) +#define DC_DISP_SHIFT_CLOCK_OPTIONS_0_SC0_CLK_DIVIDER_DIV2_ALIGNED _MK_ENUM_CONST(3) + +#define DC_DISP_SHIFT_CLOCK_OPTIONS_0_SC1_H_QUALIFIER_SHIFT _MK_SHIFT_CONST(16) +#define DC_DISP_SHIFT_CLOCK_OPTIONS_0_SC1_H_QUALIFIER_FIELD _MK_FIELD_CONST(0x7, DC_DISP_SHIFT_CLOCK_OPTIONS_0_SC1_H_QUALIFIER_SHIFT) +#define DC_DISP_SHIFT_CLOCK_OPTIONS_0_SC1_H_QUALIFIER_RANGE 18:16 +#define DC_DISP_SHIFT_CLOCK_OPTIONS_0_SC1_H_QUALIFIER_WOFFSET 0x0 +#define DC_DISP_SHIFT_CLOCK_OPTIONS_0_SC1_H_QUALIFIER_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SHIFT_CLOCK_OPTIONS_0_SC1_H_QUALIFIER_DEFAULT_MASK _MK_MASK_CONST(0x7) +#define DC_DISP_SHIFT_CLOCK_OPTIONS_0_SC1_H_QUALIFIER_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SHIFT_CLOCK_OPTIONS_0_SC1_H_QUALIFIER_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_SHIFT_CLOCK_OPTIONS_0_SC1_H_QUALIFIER_DISABLE _MK_ENUM_CONST(0) +#define DC_DISP_SHIFT_CLOCK_OPTIONS_0_SC1_H_QUALIFIER_NO_HQUAL _MK_ENUM_CONST(1) +#define DC_DISP_SHIFT_CLOCK_OPTIONS_0_SC1_H_QUALIFIER_HACTIVE _MK_ENUM_CONST(2) +#define DC_DISP_SHIFT_CLOCK_OPTIONS_0_SC1_H_QUALIFIER_EXT_HACTIVE _MK_ENUM_CONST(3) +#define DC_DISP_SHIFT_CLOCK_OPTIONS_0_SC1_H_QUALIFIER_HPULSE1 _MK_ENUM_CONST(4) +#define DC_DISP_SHIFT_CLOCK_OPTIONS_0_SC1_H_QUALIFIER_EXT_HPULSE1 _MK_ENUM_CONST(5) + +#define DC_DISP_SHIFT_CLOCK_OPTIONS_0_SC1_V_QUALIFIER_SHIFT _MK_SHIFT_CONST(19) +#define DC_DISP_SHIFT_CLOCK_OPTIONS_0_SC1_V_QUALIFIER_FIELD _MK_FIELD_CONST(0x7, DC_DISP_SHIFT_CLOCK_OPTIONS_0_SC1_V_QUALIFIER_SHIFT) +#define DC_DISP_SHIFT_CLOCK_OPTIONS_0_SC1_V_QUALIFIER_RANGE 21:19 +#define DC_DISP_SHIFT_CLOCK_OPTIONS_0_SC1_V_QUALIFIER_WOFFSET 0x0 +#define DC_DISP_SHIFT_CLOCK_OPTIONS_0_SC1_V_QUALIFIER_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SHIFT_CLOCK_OPTIONS_0_SC1_V_QUALIFIER_DEFAULT_MASK _MK_MASK_CONST(0x7) +#define DC_DISP_SHIFT_CLOCK_OPTIONS_0_SC1_V_QUALIFIER_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SHIFT_CLOCK_OPTIONS_0_SC1_V_QUALIFIER_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_SHIFT_CLOCK_OPTIONS_0_SC1_V_QUALIFIER_NO_VQUAL _MK_ENUM_CONST(0) +#define DC_DISP_SHIFT_CLOCK_OPTIONS_0_SC1_V_QUALIFIER_RESERVED _MK_ENUM_CONST(1) +#define DC_DISP_SHIFT_CLOCK_OPTIONS_0_SC1_V_QUALIFIER_VACTIVE _MK_ENUM_CONST(2) +#define DC_DISP_SHIFT_CLOCK_OPTIONS_0_SC1_V_QUALIFIER_EXT_VACTIVE _MK_ENUM_CONST(3) +#define DC_DISP_SHIFT_CLOCK_OPTIONS_0_SC1_V_QUALIFIER_VPULSE1 _MK_ENUM_CONST(4) +#define DC_DISP_SHIFT_CLOCK_OPTIONS_0_SC1_V_QUALIFIER_EXT_VPULSE1 _MK_ENUM_CONST(5) + +#define DC_DISP_SHIFT_CLOCK_OPTIONS_0_SC1_CLK_DIVIDER_SHIFT _MK_SHIFT_CONST(22) +#define DC_DISP_SHIFT_CLOCK_OPTIONS_0_SC1_CLK_DIVIDER_FIELD _MK_FIELD_CONST(0x3, DC_DISP_SHIFT_CLOCK_OPTIONS_0_SC1_CLK_DIVIDER_SHIFT) +#define DC_DISP_SHIFT_CLOCK_OPTIONS_0_SC1_CLK_DIVIDER_RANGE 23:22 +#define DC_DISP_SHIFT_CLOCK_OPTIONS_0_SC1_CLK_DIVIDER_WOFFSET 0x0 +#define DC_DISP_SHIFT_CLOCK_OPTIONS_0_SC1_CLK_DIVIDER_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SHIFT_CLOCK_OPTIONS_0_SC1_CLK_DIVIDER_DEFAULT_MASK _MK_MASK_CONST(0x3) +#define DC_DISP_SHIFT_CLOCK_OPTIONS_0_SC1_CLK_DIVIDER_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SHIFT_CLOCK_OPTIONS_0_SC1_CLK_DIVIDER_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_SHIFT_CLOCK_OPTIONS_0_SC1_CLK_DIVIDER_DIV1 _MK_ENUM_CONST(0) +#define DC_DISP_SHIFT_CLOCK_OPTIONS_0_SC1_CLK_DIVIDER_DIV2 _MK_ENUM_CONST(1) +#define DC_DISP_SHIFT_CLOCK_OPTIONS_0_SC1_CLK_DIVIDER_DIV4 _MK_ENUM_CONST(2) +#define DC_DISP_SHIFT_CLOCK_OPTIONS_0_SC1_CLK_DIVIDER_DIV2_ALIGNED _MK_ENUM_CONST(3) + + +// Register DC_DISP_DATA_ENABLE_OPTIONS_0 +#define DC_DISP_DATA_ENABLE_OPTIONS_0 _MK_ADDR_CONST(0x432) +#define DC_DISP_DATA_ENABLE_OPTIONS_0_SECURE 0x0 +#define DC_DISP_DATA_ENABLE_OPTIONS_0_WORD_COUNT 0x1 +#define DC_DISP_DATA_ENABLE_OPTIONS_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_DATA_ENABLE_OPTIONS_0_RESET_MASK _MK_MASK_CONST(0x1f) +#define DC_DISP_DATA_ENABLE_OPTIONS_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_DATA_ENABLE_OPTIONS_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_DATA_ENABLE_OPTIONS_0_READ_MASK _MK_MASK_CONST(0x1f) +#define DC_DISP_DATA_ENABLE_OPTIONS_0_WRITE_MASK _MK_MASK_CONST(0x1f) +#define DC_DISP_DATA_ENABLE_OPTIONS_0_DE_SELECT_SHIFT _MK_SHIFT_CONST(0) +#define DC_DISP_DATA_ENABLE_OPTIONS_0_DE_SELECT_FIELD _MK_FIELD_CONST(0x3, DC_DISP_DATA_ENABLE_OPTIONS_0_DE_SELECT_SHIFT) +#define DC_DISP_DATA_ENABLE_OPTIONS_0_DE_SELECT_RANGE 1:0 +#define DC_DISP_DATA_ENABLE_OPTIONS_0_DE_SELECT_WOFFSET 0x0 +#define DC_DISP_DATA_ENABLE_OPTIONS_0_DE_SELECT_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_DATA_ENABLE_OPTIONS_0_DE_SELECT_DEFAULT_MASK _MK_MASK_CONST(0x3) +#define DC_DISP_DATA_ENABLE_OPTIONS_0_DE_SELECT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_DATA_ENABLE_OPTIONS_0_DE_SELECT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_DATA_ENABLE_OPTIONS_0_DE_SELECT_ACTIVE_BLANK _MK_ENUM_CONST(0) +#define DC_DISP_DATA_ENABLE_OPTIONS_0_DE_SELECT_ACTIVE _MK_ENUM_CONST(1) +#define DC_DISP_DATA_ENABLE_OPTIONS_0_DE_SELECT_ACTIVE_IS _MK_ENUM_CONST(2) + +#define DC_DISP_DATA_ENABLE_OPTIONS_0_DE_CONTROL_SHIFT _MK_SHIFT_CONST(2) +#define DC_DISP_DATA_ENABLE_OPTIONS_0_DE_CONTROL_FIELD _MK_FIELD_CONST(0x7, DC_DISP_DATA_ENABLE_OPTIONS_0_DE_CONTROL_SHIFT) +#define DC_DISP_DATA_ENABLE_OPTIONS_0_DE_CONTROL_RANGE 4:2 +#define DC_DISP_DATA_ENABLE_OPTIONS_0_DE_CONTROL_WOFFSET 0x0 +#define DC_DISP_DATA_ENABLE_OPTIONS_0_DE_CONTROL_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_DATA_ENABLE_OPTIONS_0_DE_CONTROL_DEFAULT_MASK _MK_MASK_CONST(0x7) +#define DC_DISP_DATA_ENABLE_OPTIONS_0_DE_CONTROL_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_DATA_ENABLE_OPTIONS_0_DE_CONTROL_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_DATA_ENABLE_OPTIONS_0_DE_CONTROL_ONECLK _MK_ENUM_CONST(0) +#define DC_DISP_DATA_ENABLE_OPTIONS_0_DE_CONTROL_NORMAL _MK_ENUM_CONST(1) +#define DC_DISP_DATA_ENABLE_OPTIONS_0_DE_CONTROL_EARLY_EXT _MK_ENUM_CONST(2) +#define DC_DISP_DATA_ENABLE_OPTIONS_0_DE_CONTROL_EARLY _MK_ENUM_CONST(3) +#define DC_DISP_DATA_ENABLE_OPTIONS_0_DE_CONTROL_ACTIVE_BLANK _MK_ENUM_CONST(4) + + +// Register DC_DISP_SERIAL_INTERFACE_OPTIONS_0 +#define DC_DISP_SERIAL_INTERFACE_OPTIONS_0 _MK_ADDR_CONST(0x433) +#define DC_DISP_SERIAL_INTERFACE_OPTIONS_0_SECURE 0x0 +#define DC_DISP_SERIAL_INTERFACE_OPTIONS_0_WORD_COUNT 0x1 +#define DC_DISP_SERIAL_INTERFACE_OPTIONS_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_SERIAL_INTERFACE_OPTIONS_0_RESET_MASK _MK_MASK_CONST(0xff) +#define DC_DISP_SERIAL_INTERFACE_OPTIONS_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_SERIAL_INTERFACE_OPTIONS_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_SERIAL_INTERFACE_OPTIONS_0_READ_MASK _MK_MASK_CONST(0xff) +#define DC_DISP_SERIAL_INTERFACE_OPTIONS_0_WRITE_MASK _MK_MASK_CONST(0xff) +#define DC_DISP_SERIAL_INTERFACE_OPTIONS_0_SDT_STP_MODE_SHIFT _MK_SHIFT_CONST(0) +#define DC_DISP_SERIAL_INTERFACE_OPTIONS_0_SDT_STP_MODE_FIELD _MK_FIELD_CONST(0x3, DC_DISP_SERIAL_INTERFACE_OPTIONS_0_SDT_STP_MODE_SHIFT) +#define DC_DISP_SERIAL_INTERFACE_OPTIONS_0_SDT_STP_MODE_RANGE 1:0 +#define DC_DISP_SERIAL_INTERFACE_OPTIONS_0_SDT_STP_MODE_WOFFSET 0x0 +#define DC_DISP_SERIAL_INTERFACE_OPTIONS_0_SDT_STP_MODE_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SERIAL_INTERFACE_OPTIONS_0_SDT_STP_MODE_DEFAULT_MASK _MK_MASK_CONST(0x3) +#define DC_DISP_SERIAL_INTERFACE_OPTIONS_0_SDT_STP_MODE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SERIAL_INTERFACE_OPTIONS_0_SDT_STP_MODE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_SERIAL_INTERFACE_OPTIONS_0_SDT_STP_MODE_DISABLE _MK_ENUM_CONST(0) +#define DC_DISP_SERIAL_INTERFACE_OPTIONS_0_SDT_STP_MODE_RESERVED _MK_ENUM_CONST(1) +#define DC_DISP_SERIAL_INTERFACE_OPTIONS_0_SDT_STP_MODE_ENABLE_DUP _MK_ENUM_CONST(2) +#define DC_DISP_SERIAL_INTERFACE_OPTIONS_0_SDT_STP_MODE_ENABLE _MK_ENUM_CONST(3) + +#define DC_DISP_SERIAL_INTERFACE_OPTIONS_0_SDT_STP_DURATION_SHIFT _MK_SHIFT_CONST(2) +#define DC_DISP_SERIAL_INTERFACE_OPTIONS_0_SDT_STP_DURATION_FIELD _MK_FIELD_CONST(0xf, DC_DISP_SERIAL_INTERFACE_OPTIONS_0_SDT_STP_DURATION_SHIFT) +#define DC_DISP_SERIAL_INTERFACE_OPTIONS_0_SDT_STP_DURATION_RANGE 5:2 +#define DC_DISP_SERIAL_INTERFACE_OPTIONS_0_SDT_STP_DURATION_WOFFSET 0x0 +#define DC_DISP_SERIAL_INTERFACE_OPTIONS_0_SDT_STP_DURATION_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SERIAL_INTERFACE_OPTIONS_0_SDT_STP_DURATION_DEFAULT_MASK _MK_MASK_CONST(0xf) +#define DC_DISP_SERIAL_INTERFACE_OPTIONS_0_SDT_STP_DURATION_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SERIAL_INTERFACE_OPTIONS_0_SDT_STP_DURATION_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_DISP_SERIAL_INTERFACE_OPTIONS_0_STH_DURATION_SHIFT _MK_SHIFT_CONST(6) +#define DC_DISP_SERIAL_INTERFACE_OPTIONS_0_STH_DURATION_FIELD _MK_FIELD_CONST(0x1, DC_DISP_SERIAL_INTERFACE_OPTIONS_0_STH_DURATION_SHIFT) +#define DC_DISP_SERIAL_INTERFACE_OPTIONS_0_STH_DURATION_RANGE 6:6 +#define DC_DISP_SERIAL_INTERFACE_OPTIONS_0_STH_DURATION_WOFFSET 0x0 +#define DC_DISP_SERIAL_INTERFACE_OPTIONS_0_STH_DURATION_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SERIAL_INTERFACE_OPTIONS_0_STH_DURATION_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_DISP_SERIAL_INTERFACE_OPTIONS_0_STH_DURATION_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SERIAL_INTERFACE_OPTIONS_0_STH_DURATION_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_SERIAL_INTERFACE_OPTIONS_0_STH_DURATION_ONE_CLOCK _MK_ENUM_CONST(0) +#define DC_DISP_SERIAL_INTERFACE_OPTIONS_0_STH_DURATION_TWO_CLOCK _MK_ENUM_CONST(1) + +#define DC_DISP_SERIAL_INTERFACE_OPTIONS_0_STP_CONTROL_SHIFT _MK_SHIFT_CONST(7) +#define DC_DISP_SERIAL_INTERFACE_OPTIONS_0_STP_CONTROL_FIELD _MK_FIELD_CONST(0x1, DC_DISP_SERIAL_INTERFACE_OPTIONS_0_STP_CONTROL_SHIFT) +#define DC_DISP_SERIAL_INTERFACE_OPTIONS_0_STP_CONTROL_RANGE 7:7 +#define DC_DISP_SERIAL_INTERFACE_OPTIONS_0_STP_CONTROL_WOFFSET 0x0 +#define DC_DISP_SERIAL_INTERFACE_OPTIONS_0_STP_CONTROL_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SERIAL_INTERFACE_OPTIONS_0_STP_CONTROL_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_DISP_SERIAL_INTERFACE_OPTIONS_0_STP_CONTROL_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SERIAL_INTERFACE_OPTIONS_0_STP_CONTROL_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_SERIAL_INTERFACE_OPTIONS_0_STP_CONTROL_NORMAL _MK_ENUM_CONST(0) +#define DC_DISP_SERIAL_INTERFACE_OPTIONS_0_STP_CONTROL_EXTENDED _MK_ENUM_CONST(1) + + +// Register DC_DISP_LCD_SPI_OPTIONS_0 +#define DC_DISP_LCD_SPI_OPTIONS_0 _MK_ADDR_CONST(0x434) +#define DC_DISP_LCD_SPI_OPTIONS_0_SECURE 0x0 +#define DC_DISP_LCD_SPI_OPTIONS_0_WORD_COUNT 0x1 +#define DC_DISP_LCD_SPI_OPTIONS_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_LCD_SPI_OPTIONS_0_RESET_MASK _MK_MASK_CONST(0x1f) +#define DC_DISP_LCD_SPI_OPTIONS_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_LCD_SPI_OPTIONS_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_LCD_SPI_OPTIONS_0_READ_MASK _MK_MASK_CONST(0x1f) +#define DC_DISP_LCD_SPI_OPTIONS_0_WRITE_MASK _MK_MASK_CONST(0x1f) +#define DC_DISP_LCD_SPI_OPTIONS_0_LCD_SPI_CS_SHIFT _MK_SHIFT_CONST(0) +#define DC_DISP_LCD_SPI_OPTIONS_0_LCD_SPI_CS_FIELD _MK_FIELD_CONST(0x1, DC_DISP_LCD_SPI_OPTIONS_0_LCD_SPI_CS_SHIFT) +#define DC_DISP_LCD_SPI_OPTIONS_0_LCD_SPI_CS_RANGE 0:0 +#define DC_DISP_LCD_SPI_OPTIONS_0_LCD_SPI_CS_WOFFSET 0x0 +#define DC_DISP_LCD_SPI_OPTIONS_0_LCD_SPI_CS_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_LCD_SPI_OPTIONS_0_LCD_SPI_CS_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_DISP_LCD_SPI_OPTIONS_0_LCD_SPI_CS_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_LCD_SPI_OPTIONS_0_LCD_SPI_CS_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_LCD_SPI_OPTIONS_0_LCD_SPI_CS_MAIN _MK_ENUM_CONST(0) +#define DC_DISP_LCD_SPI_OPTIONS_0_LCD_SPI_CS_SUB _MK_ENUM_CONST(1) + +#define DC_DISP_LCD_SPI_OPTIONS_0_LCD_SPI_DC_SHIFT _MK_SHIFT_CONST(1) +#define DC_DISP_LCD_SPI_OPTIONS_0_LCD_SPI_DC_FIELD _MK_FIELD_CONST(0x1, DC_DISP_LCD_SPI_OPTIONS_0_LCD_SPI_DC_SHIFT) +#define DC_DISP_LCD_SPI_OPTIONS_0_LCD_SPI_DC_RANGE 1:1 +#define DC_DISP_LCD_SPI_OPTIONS_0_LCD_SPI_DC_WOFFSET 0x0 +#define DC_DISP_LCD_SPI_OPTIONS_0_LCD_SPI_DC_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_LCD_SPI_OPTIONS_0_LCD_SPI_DC_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_DISP_LCD_SPI_OPTIONS_0_LCD_SPI_DC_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_LCD_SPI_OPTIONS_0_LCD_SPI_DC_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_LCD_SPI_OPTIONS_0_LCD_SPI_DC_LOW _MK_ENUM_CONST(0) +#define DC_DISP_LCD_SPI_OPTIONS_0_LCD_SPI_DC_HIGH _MK_ENUM_CONST(1) + +#define DC_DISP_LCD_SPI_OPTIONS_0_SPI_CS_CONTROL_SHIFT _MK_SHIFT_CONST(2) +#define DC_DISP_LCD_SPI_OPTIONS_0_SPI_CS_CONTROL_FIELD _MK_FIELD_CONST(0x3, DC_DISP_LCD_SPI_OPTIONS_0_SPI_CS_CONTROL_SHIFT) +#define DC_DISP_LCD_SPI_OPTIONS_0_SPI_CS_CONTROL_RANGE 3:2 +#define DC_DISP_LCD_SPI_OPTIONS_0_SPI_CS_CONTROL_WOFFSET 0x0 +#define DC_DISP_LCD_SPI_OPTIONS_0_SPI_CS_CONTROL_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_LCD_SPI_OPTIONS_0_SPI_CS_CONTROL_DEFAULT_MASK _MK_MASK_CONST(0x3) +#define DC_DISP_LCD_SPI_OPTIONS_0_SPI_CS_CONTROL_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_LCD_SPI_OPTIONS_0_SPI_CS_CONTROL_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_LCD_SPI_OPTIONS_0_SPI_CS_CONTROL_LCD_IS_SPI _MK_ENUM_CONST(0) +#define DC_DISP_LCD_SPI_OPTIONS_0_SPI_CS_CONTROL_LCD_SPI _MK_ENUM_CONST(1) +#define DC_DISP_LCD_SPI_OPTIONS_0_SPI_CS_CONTROL_IS_SPI _MK_ENUM_CONST(2) +#define DC_DISP_LCD_SPI_OPTIONS_0_SPI_CS_CONTROL_FORCED _MK_ENUM_CONST(3) + +#define DC_DISP_LCD_SPI_OPTIONS_0_LCD_SPI_DIRECTION_SHIFT _MK_SHIFT_CONST(4) +#define DC_DISP_LCD_SPI_OPTIONS_0_LCD_SPI_DIRECTION_FIELD _MK_FIELD_CONST(0x1, DC_DISP_LCD_SPI_OPTIONS_0_LCD_SPI_DIRECTION_SHIFT) +#define DC_DISP_LCD_SPI_OPTIONS_0_LCD_SPI_DIRECTION_RANGE 4:4 +#define DC_DISP_LCD_SPI_OPTIONS_0_LCD_SPI_DIRECTION_WOFFSET 0x0 +#define DC_DISP_LCD_SPI_OPTIONS_0_LCD_SPI_DIRECTION_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_LCD_SPI_OPTIONS_0_LCD_SPI_DIRECTION_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_DISP_LCD_SPI_OPTIONS_0_LCD_SPI_DIRECTION_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_LCD_SPI_OPTIONS_0_LCD_SPI_DIRECTION_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_LCD_SPI_OPTIONS_0_LCD_SPI_DIRECTION_MSB2LSB _MK_ENUM_CONST(0) +#define DC_DISP_LCD_SPI_OPTIONS_0_LCD_SPI_DIRECTION_LSB2MSB _MK_ENUM_CONST(1) + + +// Reserved address 1077 [0x435] + +// Register DC_DISP_COLOR_KEY0_LOWER_0 +#define DC_DISP_COLOR_KEY0_LOWER_0 _MK_ADDR_CONST(0x436) +#define DC_DISP_COLOR_KEY0_LOWER_0_SECURE 0x0 +#define DC_DISP_COLOR_KEY0_LOWER_0_WORD_COUNT 0x1 +#define DC_DISP_COLOR_KEY0_LOWER_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_COLOR_KEY0_LOWER_0_RESET_MASK _MK_MASK_CONST(0xffffffff) +#define DC_DISP_COLOR_KEY0_LOWER_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_COLOR_KEY0_LOWER_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_COLOR_KEY0_LOWER_0_READ_MASK _MK_MASK_CONST(0xffffffff) +#define DC_DISP_COLOR_KEY0_LOWER_0_WRITE_MASK _MK_MASK_CONST(0xffffffff) +#define DC_DISP_COLOR_KEY0_LOWER_0_COLOR_KEY0_L_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_DISP_COLOR_KEY0_LOWER_0_COLOR_KEY0_L_R_FIELD _MK_FIELD_CONST(0xff, DC_DISP_COLOR_KEY0_LOWER_0_COLOR_KEY0_L_R_SHIFT) +#define DC_DISP_COLOR_KEY0_LOWER_0_COLOR_KEY0_L_R_RANGE 7:0 +#define DC_DISP_COLOR_KEY0_LOWER_0_COLOR_KEY0_L_R_WOFFSET 0x0 +#define DC_DISP_COLOR_KEY0_LOWER_0_COLOR_KEY0_L_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_COLOR_KEY0_LOWER_0_COLOR_KEY0_L_R_DEFAULT_MASK _MK_MASK_CONST(0xff) +#define DC_DISP_COLOR_KEY0_LOWER_0_COLOR_KEY0_L_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_COLOR_KEY0_LOWER_0_COLOR_KEY0_L_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_DISP_COLOR_KEY0_LOWER_0_COLOR_KEY0_L_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_DISP_COLOR_KEY0_LOWER_0_COLOR_KEY0_L_G_FIELD _MK_FIELD_CONST(0xff, DC_DISP_COLOR_KEY0_LOWER_0_COLOR_KEY0_L_G_SHIFT) +#define DC_DISP_COLOR_KEY0_LOWER_0_COLOR_KEY0_L_G_RANGE 15:8 +#define DC_DISP_COLOR_KEY0_LOWER_0_COLOR_KEY0_L_G_WOFFSET 0x0 +#define DC_DISP_COLOR_KEY0_LOWER_0_COLOR_KEY0_L_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_COLOR_KEY0_LOWER_0_COLOR_KEY0_L_G_DEFAULT_MASK _MK_MASK_CONST(0xff) +#define DC_DISP_COLOR_KEY0_LOWER_0_COLOR_KEY0_L_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_COLOR_KEY0_LOWER_0_COLOR_KEY0_L_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_DISP_COLOR_KEY0_LOWER_0_COLOR_KEY0_L_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_DISP_COLOR_KEY0_LOWER_0_COLOR_KEY0_L_B_FIELD _MK_FIELD_CONST(0xff, DC_DISP_COLOR_KEY0_LOWER_0_COLOR_KEY0_L_B_SHIFT) +#define DC_DISP_COLOR_KEY0_LOWER_0_COLOR_KEY0_L_B_RANGE 23:16 +#define DC_DISP_COLOR_KEY0_LOWER_0_COLOR_KEY0_L_B_WOFFSET 0x0 +#define DC_DISP_COLOR_KEY0_LOWER_0_COLOR_KEY0_L_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_COLOR_KEY0_LOWER_0_COLOR_KEY0_L_B_DEFAULT_MASK _MK_MASK_CONST(0xff) +#define DC_DISP_COLOR_KEY0_LOWER_0_COLOR_KEY0_L_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_COLOR_KEY0_LOWER_0_COLOR_KEY0_L_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_DISP_COLOR_KEY0_LOWER_0_COLOR_KEY0_L_A_SHIFT _MK_SHIFT_CONST(24) +#define DC_DISP_COLOR_KEY0_LOWER_0_COLOR_KEY0_L_A_FIELD _MK_FIELD_CONST(0xff, DC_DISP_COLOR_KEY0_LOWER_0_COLOR_KEY0_L_A_SHIFT) +#define DC_DISP_COLOR_KEY0_LOWER_0_COLOR_KEY0_L_A_RANGE 31:24 +#define DC_DISP_COLOR_KEY0_LOWER_0_COLOR_KEY0_L_A_WOFFSET 0x0 +#define DC_DISP_COLOR_KEY0_LOWER_0_COLOR_KEY0_L_A_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_COLOR_KEY0_LOWER_0_COLOR_KEY0_L_A_DEFAULT_MASK _MK_MASK_CONST(0xff) +#define DC_DISP_COLOR_KEY0_LOWER_0_COLOR_KEY0_L_A_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_COLOR_KEY0_LOWER_0_COLOR_KEY0_L_A_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_DISP_COLOR_KEY0_UPPER_0 +#define DC_DISP_COLOR_KEY0_UPPER_0 _MK_ADDR_CONST(0x437) +#define DC_DISP_COLOR_KEY0_UPPER_0_SECURE 0x0 +#define DC_DISP_COLOR_KEY0_UPPER_0_WORD_COUNT 0x1 +#define DC_DISP_COLOR_KEY0_UPPER_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_COLOR_KEY0_UPPER_0_RESET_MASK _MK_MASK_CONST(0xffffffff) +#define DC_DISP_COLOR_KEY0_UPPER_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_COLOR_KEY0_UPPER_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_COLOR_KEY0_UPPER_0_READ_MASK _MK_MASK_CONST(0xffffffff) +#define DC_DISP_COLOR_KEY0_UPPER_0_WRITE_MASK _MK_MASK_CONST(0xffffffff) +#define DC_DISP_COLOR_KEY0_UPPER_0_COLOR_KEY0_U_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_DISP_COLOR_KEY0_UPPER_0_COLOR_KEY0_U_R_FIELD _MK_FIELD_CONST(0xff, DC_DISP_COLOR_KEY0_UPPER_0_COLOR_KEY0_U_R_SHIFT) +#define DC_DISP_COLOR_KEY0_UPPER_0_COLOR_KEY0_U_R_RANGE 7:0 +#define DC_DISP_COLOR_KEY0_UPPER_0_COLOR_KEY0_U_R_WOFFSET 0x0 +#define DC_DISP_COLOR_KEY0_UPPER_0_COLOR_KEY0_U_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_COLOR_KEY0_UPPER_0_COLOR_KEY0_U_R_DEFAULT_MASK _MK_MASK_CONST(0xff) +#define DC_DISP_COLOR_KEY0_UPPER_0_COLOR_KEY0_U_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_COLOR_KEY0_UPPER_0_COLOR_KEY0_U_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_DISP_COLOR_KEY0_UPPER_0_COLOR_KEY0_U_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_DISP_COLOR_KEY0_UPPER_0_COLOR_KEY0_U_G_FIELD _MK_FIELD_CONST(0xff, DC_DISP_COLOR_KEY0_UPPER_0_COLOR_KEY0_U_G_SHIFT) +#define DC_DISP_COLOR_KEY0_UPPER_0_COLOR_KEY0_U_G_RANGE 15:8 +#define DC_DISP_COLOR_KEY0_UPPER_0_COLOR_KEY0_U_G_WOFFSET 0x0 +#define DC_DISP_COLOR_KEY0_UPPER_0_COLOR_KEY0_U_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_COLOR_KEY0_UPPER_0_COLOR_KEY0_U_G_DEFAULT_MASK _MK_MASK_CONST(0xff) +#define DC_DISP_COLOR_KEY0_UPPER_0_COLOR_KEY0_U_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_COLOR_KEY0_UPPER_0_COLOR_KEY0_U_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_DISP_COLOR_KEY0_UPPER_0_COLOR_KEY0_U_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_DISP_COLOR_KEY0_UPPER_0_COLOR_KEY0_U_B_FIELD _MK_FIELD_CONST(0xff, DC_DISP_COLOR_KEY0_UPPER_0_COLOR_KEY0_U_B_SHIFT) +#define DC_DISP_COLOR_KEY0_UPPER_0_COLOR_KEY0_U_B_RANGE 23:16 +#define DC_DISP_COLOR_KEY0_UPPER_0_COLOR_KEY0_U_B_WOFFSET 0x0 +#define DC_DISP_COLOR_KEY0_UPPER_0_COLOR_KEY0_U_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_COLOR_KEY0_UPPER_0_COLOR_KEY0_U_B_DEFAULT_MASK _MK_MASK_CONST(0xff) +#define DC_DISP_COLOR_KEY0_UPPER_0_COLOR_KEY0_U_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_COLOR_KEY0_UPPER_0_COLOR_KEY0_U_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_DISP_COLOR_KEY0_UPPER_0_COLOR_KEY0_U_A_SHIFT _MK_SHIFT_CONST(24) +#define DC_DISP_COLOR_KEY0_UPPER_0_COLOR_KEY0_U_A_FIELD _MK_FIELD_CONST(0xff, DC_DISP_COLOR_KEY0_UPPER_0_COLOR_KEY0_U_A_SHIFT) +#define DC_DISP_COLOR_KEY0_UPPER_0_COLOR_KEY0_U_A_RANGE 31:24 +#define DC_DISP_COLOR_KEY0_UPPER_0_COLOR_KEY0_U_A_WOFFSET 0x0 +#define DC_DISP_COLOR_KEY0_UPPER_0_COLOR_KEY0_U_A_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_COLOR_KEY0_UPPER_0_COLOR_KEY0_U_A_DEFAULT_MASK _MK_MASK_CONST(0xff) +#define DC_DISP_COLOR_KEY0_UPPER_0_COLOR_KEY0_U_A_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_COLOR_KEY0_UPPER_0_COLOR_KEY0_U_A_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_DISP_COLOR_KEY1_LOWER_0 +#define DC_DISP_COLOR_KEY1_LOWER_0 _MK_ADDR_CONST(0x438) +#define DC_DISP_COLOR_KEY1_LOWER_0_SECURE 0x0 +#define DC_DISP_COLOR_KEY1_LOWER_0_WORD_COUNT 0x1 +#define DC_DISP_COLOR_KEY1_LOWER_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_COLOR_KEY1_LOWER_0_RESET_MASK _MK_MASK_CONST(0xffffffff) +#define DC_DISP_COLOR_KEY1_LOWER_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_COLOR_KEY1_LOWER_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_COLOR_KEY1_LOWER_0_READ_MASK _MK_MASK_CONST(0xffffffff) +#define DC_DISP_COLOR_KEY1_LOWER_0_WRITE_MASK _MK_MASK_CONST(0xffffffff) +#define DC_DISP_COLOR_KEY1_LOWER_0_COLOR_KEY1_L_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_DISP_COLOR_KEY1_LOWER_0_COLOR_KEY1_L_R_FIELD _MK_FIELD_CONST(0xff, DC_DISP_COLOR_KEY1_LOWER_0_COLOR_KEY1_L_R_SHIFT) +#define DC_DISP_COLOR_KEY1_LOWER_0_COLOR_KEY1_L_R_RANGE 7:0 +#define DC_DISP_COLOR_KEY1_LOWER_0_COLOR_KEY1_L_R_WOFFSET 0x0 +#define DC_DISP_COLOR_KEY1_LOWER_0_COLOR_KEY1_L_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_COLOR_KEY1_LOWER_0_COLOR_KEY1_L_R_DEFAULT_MASK _MK_MASK_CONST(0xff) +#define DC_DISP_COLOR_KEY1_LOWER_0_COLOR_KEY1_L_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_COLOR_KEY1_LOWER_0_COLOR_KEY1_L_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_DISP_COLOR_KEY1_LOWER_0_COLOR_KEY1_L_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_DISP_COLOR_KEY1_LOWER_0_COLOR_KEY1_L_G_FIELD _MK_FIELD_CONST(0xff, DC_DISP_COLOR_KEY1_LOWER_0_COLOR_KEY1_L_G_SHIFT) +#define DC_DISP_COLOR_KEY1_LOWER_0_COLOR_KEY1_L_G_RANGE 15:8 +#define DC_DISP_COLOR_KEY1_LOWER_0_COLOR_KEY1_L_G_WOFFSET 0x0 +#define DC_DISP_COLOR_KEY1_LOWER_0_COLOR_KEY1_L_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_COLOR_KEY1_LOWER_0_COLOR_KEY1_L_G_DEFAULT_MASK _MK_MASK_CONST(0xff) +#define DC_DISP_COLOR_KEY1_LOWER_0_COLOR_KEY1_L_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_COLOR_KEY1_LOWER_0_COLOR_KEY1_L_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_DISP_COLOR_KEY1_LOWER_0_COLOR_KEY1_L_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_DISP_COLOR_KEY1_LOWER_0_COLOR_KEY1_L_B_FIELD _MK_FIELD_CONST(0xff, DC_DISP_COLOR_KEY1_LOWER_0_COLOR_KEY1_L_B_SHIFT) +#define DC_DISP_COLOR_KEY1_LOWER_0_COLOR_KEY1_L_B_RANGE 23:16 +#define DC_DISP_COLOR_KEY1_LOWER_0_COLOR_KEY1_L_B_WOFFSET 0x0 +#define DC_DISP_COLOR_KEY1_LOWER_0_COLOR_KEY1_L_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_COLOR_KEY1_LOWER_0_COLOR_KEY1_L_B_DEFAULT_MASK _MK_MASK_CONST(0xff) +#define DC_DISP_COLOR_KEY1_LOWER_0_COLOR_KEY1_L_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_COLOR_KEY1_LOWER_0_COLOR_KEY1_L_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_DISP_COLOR_KEY1_LOWER_0_COLOR_KEY1_L_A_SHIFT _MK_SHIFT_CONST(24) +#define DC_DISP_COLOR_KEY1_LOWER_0_COLOR_KEY1_L_A_FIELD _MK_FIELD_CONST(0xff, DC_DISP_COLOR_KEY1_LOWER_0_COLOR_KEY1_L_A_SHIFT) +#define DC_DISP_COLOR_KEY1_LOWER_0_COLOR_KEY1_L_A_RANGE 31:24 +#define DC_DISP_COLOR_KEY1_LOWER_0_COLOR_KEY1_L_A_WOFFSET 0x0 +#define DC_DISP_COLOR_KEY1_LOWER_0_COLOR_KEY1_L_A_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_COLOR_KEY1_LOWER_0_COLOR_KEY1_L_A_DEFAULT_MASK _MK_MASK_CONST(0xff) +#define DC_DISP_COLOR_KEY1_LOWER_0_COLOR_KEY1_L_A_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_COLOR_KEY1_LOWER_0_COLOR_KEY1_L_A_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_DISP_COLOR_KEY1_UPPER_0 +#define DC_DISP_COLOR_KEY1_UPPER_0 _MK_ADDR_CONST(0x439) +#define DC_DISP_COLOR_KEY1_UPPER_0_SECURE 0x0 +#define DC_DISP_COLOR_KEY1_UPPER_0_WORD_COUNT 0x1 +#define DC_DISP_COLOR_KEY1_UPPER_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_COLOR_KEY1_UPPER_0_RESET_MASK _MK_MASK_CONST(0xffffffff) +#define DC_DISP_COLOR_KEY1_UPPER_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_COLOR_KEY1_UPPER_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_COLOR_KEY1_UPPER_0_READ_MASK _MK_MASK_CONST(0xffffffff) +#define DC_DISP_COLOR_KEY1_UPPER_0_WRITE_MASK _MK_MASK_CONST(0xffffffff) +#define DC_DISP_COLOR_KEY1_UPPER_0_COLOR_KEY1_U_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_DISP_COLOR_KEY1_UPPER_0_COLOR_KEY1_U_R_FIELD _MK_FIELD_CONST(0xff, DC_DISP_COLOR_KEY1_UPPER_0_COLOR_KEY1_U_R_SHIFT) +#define DC_DISP_COLOR_KEY1_UPPER_0_COLOR_KEY1_U_R_RANGE 7:0 +#define DC_DISP_COLOR_KEY1_UPPER_0_COLOR_KEY1_U_R_WOFFSET 0x0 +#define DC_DISP_COLOR_KEY1_UPPER_0_COLOR_KEY1_U_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_COLOR_KEY1_UPPER_0_COLOR_KEY1_U_R_DEFAULT_MASK _MK_MASK_CONST(0xff) +#define DC_DISP_COLOR_KEY1_UPPER_0_COLOR_KEY1_U_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_COLOR_KEY1_UPPER_0_COLOR_KEY1_U_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_DISP_COLOR_KEY1_UPPER_0_COLOR_KEY1_U_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_DISP_COLOR_KEY1_UPPER_0_COLOR_KEY1_U_G_FIELD _MK_FIELD_CONST(0xff, DC_DISP_COLOR_KEY1_UPPER_0_COLOR_KEY1_U_G_SHIFT) +#define DC_DISP_COLOR_KEY1_UPPER_0_COLOR_KEY1_U_G_RANGE 15:8 +#define DC_DISP_COLOR_KEY1_UPPER_0_COLOR_KEY1_U_G_WOFFSET 0x0 +#define DC_DISP_COLOR_KEY1_UPPER_0_COLOR_KEY1_U_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_COLOR_KEY1_UPPER_0_COLOR_KEY1_U_G_DEFAULT_MASK _MK_MASK_CONST(0xff) +#define DC_DISP_COLOR_KEY1_UPPER_0_COLOR_KEY1_U_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_COLOR_KEY1_UPPER_0_COLOR_KEY1_U_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_DISP_COLOR_KEY1_UPPER_0_COLOR_KEY1_U_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_DISP_COLOR_KEY1_UPPER_0_COLOR_KEY1_U_B_FIELD _MK_FIELD_CONST(0xff, DC_DISP_COLOR_KEY1_UPPER_0_COLOR_KEY1_U_B_SHIFT) +#define DC_DISP_COLOR_KEY1_UPPER_0_COLOR_KEY1_U_B_RANGE 23:16 +#define DC_DISP_COLOR_KEY1_UPPER_0_COLOR_KEY1_U_B_WOFFSET 0x0 +#define DC_DISP_COLOR_KEY1_UPPER_0_COLOR_KEY1_U_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_COLOR_KEY1_UPPER_0_COLOR_KEY1_U_B_DEFAULT_MASK _MK_MASK_CONST(0xff) +#define DC_DISP_COLOR_KEY1_UPPER_0_COLOR_KEY1_U_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_COLOR_KEY1_UPPER_0_COLOR_KEY1_U_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_DISP_COLOR_KEY1_UPPER_0_COLOR_KEY1_U_A_SHIFT _MK_SHIFT_CONST(24) +#define DC_DISP_COLOR_KEY1_UPPER_0_COLOR_KEY1_U_A_FIELD _MK_FIELD_CONST(0xff, DC_DISP_COLOR_KEY1_UPPER_0_COLOR_KEY1_U_A_SHIFT) +#define DC_DISP_COLOR_KEY1_UPPER_0_COLOR_KEY1_U_A_RANGE 31:24 +#define DC_DISP_COLOR_KEY1_UPPER_0_COLOR_KEY1_U_A_WOFFSET 0x0 +#define DC_DISP_COLOR_KEY1_UPPER_0_COLOR_KEY1_U_A_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_COLOR_KEY1_UPPER_0_COLOR_KEY1_U_A_DEFAULT_MASK _MK_MASK_CONST(0xff) +#define DC_DISP_COLOR_KEY1_UPPER_0_COLOR_KEY1_U_A_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_COLOR_KEY1_UPPER_0_COLOR_KEY1_U_A_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Reserved address 1082 [0x43a] + +// Register DC_DISP_CURSOR_FOREGROUND_0 +#define DC_DISP_CURSOR_FOREGROUND_0 _MK_ADDR_CONST(0x43c) +#define DC_DISP_CURSOR_FOREGROUND_0_SECURE 0x0 +#define DC_DISP_CURSOR_FOREGROUND_0_WORD_COUNT 0x1 +#define DC_DISP_CURSOR_FOREGROUND_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_CURSOR_FOREGROUND_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_CURSOR_FOREGROUND_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_CURSOR_FOREGROUND_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_CURSOR_FOREGROUND_0_READ_MASK _MK_MASK_CONST(0xffffff) +#define DC_DISP_CURSOR_FOREGROUND_0_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_DISP_CURSOR_FOREGROUND_0_CURSOR_FOREGROUND_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_DISP_CURSOR_FOREGROUND_0_CURSOR_FOREGROUND_R_FIELD _MK_FIELD_CONST(0xff, DC_DISP_CURSOR_FOREGROUND_0_CURSOR_FOREGROUND_R_SHIFT) +#define DC_DISP_CURSOR_FOREGROUND_0_CURSOR_FOREGROUND_R_RANGE 7:0 +#define DC_DISP_CURSOR_FOREGROUND_0_CURSOR_FOREGROUND_R_WOFFSET 0x0 +#define DC_DISP_CURSOR_FOREGROUND_0_CURSOR_FOREGROUND_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_CURSOR_FOREGROUND_0_CURSOR_FOREGROUND_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_CURSOR_FOREGROUND_0_CURSOR_FOREGROUND_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_CURSOR_FOREGROUND_0_CURSOR_FOREGROUND_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_DISP_CURSOR_FOREGROUND_0_CURSOR_FOREGROUND_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_DISP_CURSOR_FOREGROUND_0_CURSOR_FOREGROUND_G_FIELD _MK_FIELD_CONST(0xff, DC_DISP_CURSOR_FOREGROUND_0_CURSOR_FOREGROUND_G_SHIFT) +#define DC_DISP_CURSOR_FOREGROUND_0_CURSOR_FOREGROUND_G_RANGE 15:8 +#define DC_DISP_CURSOR_FOREGROUND_0_CURSOR_FOREGROUND_G_WOFFSET 0x0 +#define DC_DISP_CURSOR_FOREGROUND_0_CURSOR_FOREGROUND_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_CURSOR_FOREGROUND_0_CURSOR_FOREGROUND_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_CURSOR_FOREGROUND_0_CURSOR_FOREGROUND_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_CURSOR_FOREGROUND_0_CURSOR_FOREGROUND_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_DISP_CURSOR_FOREGROUND_0_CURSOR_FOREGROUND_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_DISP_CURSOR_FOREGROUND_0_CURSOR_FOREGROUND_B_FIELD _MK_FIELD_CONST(0xff, DC_DISP_CURSOR_FOREGROUND_0_CURSOR_FOREGROUND_B_SHIFT) +#define DC_DISP_CURSOR_FOREGROUND_0_CURSOR_FOREGROUND_B_RANGE 23:16 +#define DC_DISP_CURSOR_FOREGROUND_0_CURSOR_FOREGROUND_B_WOFFSET 0x0 +#define DC_DISP_CURSOR_FOREGROUND_0_CURSOR_FOREGROUND_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_CURSOR_FOREGROUND_0_CURSOR_FOREGROUND_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_CURSOR_FOREGROUND_0_CURSOR_FOREGROUND_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_CURSOR_FOREGROUND_0_CURSOR_FOREGROUND_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_DISP_CURSOR_BACKGROUND_0 +#define DC_DISP_CURSOR_BACKGROUND_0 _MK_ADDR_CONST(0x43d) +#define DC_DISP_CURSOR_BACKGROUND_0_SECURE 0x0 +#define DC_DISP_CURSOR_BACKGROUND_0_WORD_COUNT 0x1 +#define DC_DISP_CURSOR_BACKGROUND_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_CURSOR_BACKGROUND_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_CURSOR_BACKGROUND_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_CURSOR_BACKGROUND_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_CURSOR_BACKGROUND_0_READ_MASK _MK_MASK_CONST(0xffffff) +#define DC_DISP_CURSOR_BACKGROUND_0_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_DISP_CURSOR_BACKGROUND_0_CURSOR_BACKGROUND_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_DISP_CURSOR_BACKGROUND_0_CURSOR_BACKGROUND_R_FIELD _MK_FIELD_CONST(0xff, DC_DISP_CURSOR_BACKGROUND_0_CURSOR_BACKGROUND_R_SHIFT) +#define DC_DISP_CURSOR_BACKGROUND_0_CURSOR_BACKGROUND_R_RANGE 7:0 +#define DC_DISP_CURSOR_BACKGROUND_0_CURSOR_BACKGROUND_R_WOFFSET 0x0 +#define DC_DISP_CURSOR_BACKGROUND_0_CURSOR_BACKGROUND_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_CURSOR_BACKGROUND_0_CURSOR_BACKGROUND_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_CURSOR_BACKGROUND_0_CURSOR_BACKGROUND_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_CURSOR_BACKGROUND_0_CURSOR_BACKGROUND_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_DISP_CURSOR_BACKGROUND_0_CURSOR_BACKGROUND_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_DISP_CURSOR_BACKGROUND_0_CURSOR_BACKGROUND_G_FIELD _MK_FIELD_CONST(0xff, DC_DISP_CURSOR_BACKGROUND_0_CURSOR_BACKGROUND_G_SHIFT) +#define DC_DISP_CURSOR_BACKGROUND_0_CURSOR_BACKGROUND_G_RANGE 15:8 +#define DC_DISP_CURSOR_BACKGROUND_0_CURSOR_BACKGROUND_G_WOFFSET 0x0 +#define DC_DISP_CURSOR_BACKGROUND_0_CURSOR_BACKGROUND_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_CURSOR_BACKGROUND_0_CURSOR_BACKGROUND_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_CURSOR_BACKGROUND_0_CURSOR_BACKGROUND_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_CURSOR_BACKGROUND_0_CURSOR_BACKGROUND_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_DISP_CURSOR_BACKGROUND_0_CURSOR_BACKGROUND_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_DISP_CURSOR_BACKGROUND_0_CURSOR_BACKGROUND_B_FIELD _MK_FIELD_CONST(0xff, DC_DISP_CURSOR_BACKGROUND_0_CURSOR_BACKGROUND_B_SHIFT) +#define DC_DISP_CURSOR_BACKGROUND_0_CURSOR_BACKGROUND_B_RANGE 23:16 +#define DC_DISP_CURSOR_BACKGROUND_0_CURSOR_BACKGROUND_B_WOFFSET 0x0 +#define DC_DISP_CURSOR_BACKGROUND_0_CURSOR_BACKGROUND_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_CURSOR_BACKGROUND_0_CURSOR_BACKGROUND_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_CURSOR_BACKGROUND_0_CURSOR_BACKGROUND_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_CURSOR_BACKGROUND_0_CURSOR_BACKGROUND_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_DISP_CURSOR_START_ADDR_0 +#define DC_DISP_CURSOR_START_ADDR_0 _MK_ADDR_CONST(0x43e) +#define DC_DISP_CURSOR_START_ADDR_0_SECURE 0x0 +#define DC_DISP_CURSOR_START_ADDR_0_WORD_COUNT 0x1 +#define DC_DISP_CURSOR_START_ADDR_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_CURSOR_START_ADDR_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_CURSOR_START_ADDR_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_CURSOR_START_ADDR_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_CURSOR_START_ADDR_0_READ_MASK _MK_MASK_CONST(0x333fffff) +#define DC_DISP_CURSOR_START_ADDR_0_WRITE_MASK _MK_MASK_CONST(0x333fffff) +#define DC_DISP_CURSOR_START_ADDR_0_CURSOR_START_ADDR_SHIFT _MK_SHIFT_CONST(0) +#define DC_DISP_CURSOR_START_ADDR_0_CURSOR_START_ADDR_FIELD _MK_FIELD_CONST(0x3fffff, DC_DISP_CURSOR_START_ADDR_0_CURSOR_START_ADDR_SHIFT) +#define DC_DISP_CURSOR_START_ADDR_0_CURSOR_START_ADDR_RANGE 21:0 +#define DC_DISP_CURSOR_START_ADDR_0_CURSOR_START_ADDR_WOFFSET 0x0 +#define DC_DISP_CURSOR_START_ADDR_0_CURSOR_START_ADDR_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_CURSOR_START_ADDR_0_CURSOR_START_ADDR_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_CURSOR_START_ADDR_0_CURSOR_START_ADDR_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_CURSOR_START_ADDR_0_CURSOR_START_ADDR_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_DISP_CURSOR_START_ADDR_0_CURSOR_SIZE_SHIFT _MK_SHIFT_CONST(24) +#define DC_DISP_CURSOR_START_ADDR_0_CURSOR_SIZE_FIELD _MK_FIELD_CONST(0x3, DC_DISP_CURSOR_START_ADDR_0_CURSOR_SIZE_SHIFT) +#define DC_DISP_CURSOR_START_ADDR_0_CURSOR_SIZE_RANGE 25:24 +#define DC_DISP_CURSOR_START_ADDR_0_CURSOR_SIZE_WOFFSET 0x0 +#define DC_DISP_CURSOR_START_ADDR_0_CURSOR_SIZE_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_CURSOR_START_ADDR_0_CURSOR_SIZE_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_CURSOR_START_ADDR_0_CURSOR_SIZE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_CURSOR_START_ADDR_0_CURSOR_SIZE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_CURSOR_START_ADDR_0_CURSOR_SIZE_C32X32 _MK_ENUM_CONST(0) +#define DC_DISP_CURSOR_START_ADDR_0_CURSOR_SIZE_C64X64 _MK_ENUM_CONST(1) +#define DC_DISP_CURSOR_START_ADDR_0_CURSOR_SIZE_C128X128 _MK_ENUM_CONST(2) +#define DC_DISP_CURSOR_START_ADDR_0_CURSOR_SIZE_C256X256 _MK_ENUM_CONST(3) + +#define DC_DISP_CURSOR_START_ADDR_0_CURSOR_CLIPPING_SHIFT _MK_SHIFT_CONST(28) +#define DC_DISP_CURSOR_START_ADDR_0_CURSOR_CLIPPING_FIELD _MK_FIELD_CONST(0x3, DC_DISP_CURSOR_START_ADDR_0_CURSOR_CLIPPING_SHIFT) +#define DC_DISP_CURSOR_START_ADDR_0_CURSOR_CLIPPING_RANGE 29:28 +#define DC_DISP_CURSOR_START_ADDR_0_CURSOR_CLIPPING_WOFFSET 0x0 +#define DC_DISP_CURSOR_START_ADDR_0_CURSOR_CLIPPING_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_CURSOR_START_ADDR_0_CURSOR_CLIPPING_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_CURSOR_START_ADDR_0_CURSOR_CLIPPING_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_CURSOR_START_ADDR_0_CURSOR_CLIPPING_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_CURSOR_START_ADDR_0_CURSOR_CLIPPING_DISPLAY _MK_ENUM_CONST(0) +#define DC_DISP_CURSOR_START_ADDR_0_CURSOR_CLIPPING_WA _MK_ENUM_CONST(1) +#define DC_DISP_CURSOR_START_ADDR_0_CURSOR_CLIPPING_WB _MK_ENUM_CONST(2) +#define DC_DISP_CURSOR_START_ADDR_0_CURSOR_CLIPPING_WC _MK_ENUM_CONST(3) + + +// Register DC_DISP_CURSOR_START_ADDR_NS_0 +#define DC_DISP_CURSOR_START_ADDR_NS_0 _MK_ADDR_CONST(0x43f) +#define DC_DISP_CURSOR_START_ADDR_NS_0_SECURE 0x0 +#define DC_DISP_CURSOR_START_ADDR_NS_0_WORD_COUNT 0x1 +#define DC_DISP_CURSOR_START_ADDR_NS_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_CURSOR_START_ADDR_NS_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_CURSOR_START_ADDR_NS_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_CURSOR_START_ADDR_NS_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_CURSOR_START_ADDR_NS_0_READ_MASK _MK_MASK_CONST(0x333fffff) +#define DC_DISP_CURSOR_START_ADDR_NS_0_WRITE_MASK _MK_MASK_CONST(0x333fffff) +#define DC_DISP_CURSOR_START_ADDR_NS_0_CURSOR_START_ADDR_NS_SHIFT _MK_SHIFT_CONST(0) +#define DC_DISP_CURSOR_START_ADDR_NS_0_CURSOR_START_ADDR_NS_FIELD _MK_FIELD_CONST(0x3fffff, DC_DISP_CURSOR_START_ADDR_NS_0_CURSOR_START_ADDR_NS_SHIFT) +#define DC_DISP_CURSOR_START_ADDR_NS_0_CURSOR_START_ADDR_NS_RANGE 21:0 +#define DC_DISP_CURSOR_START_ADDR_NS_0_CURSOR_START_ADDR_NS_WOFFSET 0x0 +#define DC_DISP_CURSOR_START_ADDR_NS_0_CURSOR_START_ADDR_NS_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_CURSOR_START_ADDR_NS_0_CURSOR_START_ADDR_NS_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_CURSOR_START_ADDR_NS_0_CURSOR_START_ADDR_NS_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_CURSOR_START_ADDR_NS_0_CURSOR_START_ADDR_NS_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_DISP_CURSOR_START_ADDR_NS_0_CURSOR_SIZE_NS_SHIFT _MK_SHIFT_CONST(24) +#define DC_DISP_CURSOR_START_ADDR_NS_0_CURSOR_SIZE_NS_FIELD _MK_FIELD_CONST(0x3, DC_DISP_CURSOR_START_ADDR_NS_0_CURSOR_SIZE_NS_SHIFT) +#define DC_DISP_CURSOR_START_ADDR_NS_0_CURSOR_SIZE_NS_RANGE 25:24 +#define DC_DISP_CURSOR_START_ADDR_NS_0_CURSOR_SIZE_NS_WOFFSET 0x0 +#define DC_DISP_CURSOR_START_ADDR_NS_0_CURSOR_SIZE_NS_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_CURSOR_START_ADDR_NS_0_CURSOR_SIZE_NS_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_CURSOR_START_ADDR_NS_0_CURSOR_SIZE_NS_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_CURSOR_START_ADDR_NS_0_CURSOR_SIZE_NS_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_CURSOR_START_ADDR_NS_0_CURSOR_SIZE_NS_C32X32 _MK_ENUM_CONST(0) +#define DC_DISP_CURSOR_START_ADDR_NS_0_CURSOR_SIZE_NS_C64X64 _MK_ENUM_CONST(1) +#define DC_DISP_CURSOR_START_ADDR_NS_0_CURSOR_SIZE_NS_C128X128 _MK_ENUM_CONST(2) +#define DC_DISP_CURSOR_START_ADDR_NS_0_CURSOR_SIZE_NS_C256X256 _MK_ENUM_CONST(3) + +#define DC_DISP_CURSOR_START_ADDR_NS_0_CURSOR_CLIPPING_NS_SHIFT _MK_SHIFT_CONST(28) +#define DC_DISP_CURSOR_START_ADDR_NS_0_CURSOR_CLIPPING_NS_FIELD _MK_FIELD_CONST(0x3, DC_DISP_CURSOR_START_ADDR_NS_0_CURSOR_CLIPPING_NS_SHIFT) +#define DC_DISP_CURSOR_START_ADDR_NS_0_CURSOR_CLIPPING_NS_RANGE 29:28 +#define DC_DISP_CURSOR_START_ADDR_NS_0_CURSOR_CLIPPING_NS_WOFFSET 0x0 +#define DC_DISP_CURSOR_START_ADDR_NS_0_CURSOR_CLIPPING_NS_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_CURSOR_START_ADDR_NS_0_CURSOR_CLIPPING_NS_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_CURSOR_START_ADDR_NS_0_CURSOR_CLIPPING_NS_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_CURSOR_START_ADDR_NS_0_CURSOR_CLIPPING_NS_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_CURSOR_START_ADDR_NS_0_CURSOR_CLIPPING_NS_DISPLAY _MK_ENUM_CONST(0) +#define DC_DISP_CURSOR_START_ADDR_NS_0_CURSOR_CLIPPING_NS_WA _MK_ENUM_CONST(1) +#define DC_DISP_CURSOR_START_ADDR_NS_0_CURSOR_CLIPPING_NS_WB _MK_ENUM_CONST(2) +#define DC_DISP_CURSOR_START_ADDR_NS_0_CURSOR_CLIPPING_NS_WC _MK_ENUM_CONST(3) + + +// Register DC_DISP_CURSOR_POSITION_0 +#define DC_DISP_CURSOR_POSITION_0 _MK_ADDR_CONST(0x440) +#define DC_DISP_CURSOR_POSITION_0_SECURE 0x0 +#define DC_DISP_CURSOR_POSITION_0_WORD_COUNT 0x1 +#define DC_DISP_CURSOR_POSITION_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_CURSOR_POSITION_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_CURSOR_POSITION_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_CURSOR_POSITION_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_CURSOR_POSITION_0_READ_MASK _MK_MASK_CONST(0x3fff3fff) +#define DC_DISP_CURSOR_POSITION_0_WRITE_MASK _MK_MASK_CONST(0x3fff3fff) +#define DC_DISP_CURSOR_POSITION_0_H_CURSOR_POSITION_SHIFT _MK_SHIFT_CONST(0) +#define DC_DISP_CURSOR_POSITION_0_H_CURSOR_POSITION_FIELD _MK_FIELD_CONST(0x3fff, DC_DISP_CURSOR_POSITION_0_H_CURSOR_POSITION_SHIFT) +#define DC_DISP_CURSOR_POSITION_0_H_CURSOR_POSITION_RANGE 13:0 +#define DC_DISP_CURSOR_POSITION_0_H_CURSOR_POSITION_WOFFSET 0x0 +#define DC_DISP_CURSOR_POSITION_0_H_CURSOR_POSITION_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_CURSOR_POSITION_0_H_CURSOR_POSITION_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_CURSOR_POSITION_0_H_CURSOR_POSITION_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_CURSOR_POSITION_0_H_CURSOR_POSITION_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_DISP_CURSOR_POSITION_0_V_CURSOR_POSITION_SHIFT _MK_SHIFT_CONST(16) +#define DC_DISP_CURSOR_POSITION_0_V_CURSOR_POSITION_FIELD _MK_FIELD_CONST(0x3fff, DC_DISP_CURSOR_POSITION_0_V_CURSOR_POSITION_SHIFT) +#define DC_DISP_CURSOR_POSITION_0_V_CURSOR_POSITION_RANGE 29:16 +#define DC_DISP_CURSOR_POSITION_0_V_CURSOR_POSITION_WOFFSET 0x0 +#define DC_DISP_CURSOR_POSITION_0_V_CURSOR_POSITION_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_CURSOR_POSITION_0_V_CURSOR_POSITION_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_CURSOR_POSITION_0_V_CURSOR_POSITION_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_CURSOR_POSITION_0_V_CURSOR_POSITION_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_DISP_CURSOR_POSITION_NS_0 +#define DC_DISP_CURSOR_POSITION_NS_0 _MK_ADDR_CONST(0x441) +#define DC_DISP_CURSOR_POSITION_NS_0_SECURE 0x0 +#define DC_DISP_CURSOR_POSITION_NS_0_WORD_COUNT 0x1 +#define DC_DISP_CURSOR_POSITION_NS_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_CURSOR_POSITION_NS_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_CURSOR_POSITION_NS_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_CURSOR_POSITION_NS_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_CURSOR_POSITION_NS_0_READ_MASK _MK_MASK_CONST(0x3fff3fff) +#define DC_DISP_CURSOR_POSITION_NS_0_WRITE_MASK _MK_MASK_CONST(0x3fff3fff) +#define DC_DISP_CURSOR_POSITION_NS_0_H_CURSOR_POSITION_NS_SHIFT _MK_SHIFT_CONST(0) +#define DC_DISP_CURSOR_POSITION_NS_0_H_CURSOR_POSITION_NS_FIELD _MK_FIELD_CONST(0x3fff, DC_DISP_CURSOR_POSITION_NS_0_H_CURSOR_POSITION_NS_SHIFT) +#define DC_DISP_CURSOR_POSITION_NS_0_H_CURSOR_POSITION_NS_RANGE 13:0 +#define DC_DISP_CURSOR_POSITION_NS_0_H_CURSOR_POSITION_NS_WOFFSET 0x0 +#define DC_DISP_CURSOR_POSITION_NS_0_H_CURSOR_POSITION_NS_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_CURSOR_POSITION_NS_0_H_CURSOR_POSITION_NS_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_CURSOR_POSITION_NS_0_H_CURSOR_POSITION_NS_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_CURSOR_POSITION_NS_0_H_CURSOR_POSITION_NS_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_DISP_CURSOR_POSITION_NS_0_V_CURSOR_POSITION_NS_SHIFT _MK_SHIFT_CONST(16) +#define DC_DISP_CURSOR_POSITION_NS_0_V_CURSOR_POSITION_NS_FIELD _MK_FIELD_CONST(0x3fff, DC_DISP_CURSOR_POSITION_NS_0_V_CURSOR_POSITION_NS_SHIFT) +#define DC_DISP_CURSOR_POSITION_NS_0_V_CURSOR_POSITION_NS_RANGE 29:16 +#define DC_DISP_CURSOR_POSITION_NS_0_V_CURSOR_POSITION_NS_WOFFSET 0x0 +#define DC_DISP_CURSOR_POSITION_NS_0_V_CURSOR_POSITION_NS_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_CURSOR_POSITION_NS_0_V_CURSOR_POSITION_NS_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_CURSOR_POSITION_NS_0_V_CURSOR_POSITION_NS_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_CURSOR_POSITION_NS_0_V_CURSOR_POSITION_NS_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_DISP_INIT_SEQ_CONTROL_0 +#define DC_DISP_INIT_SEQ_CONTROL_0 _MK_ADDR_CONST(0x442) +#define DC_DISP_INIT_SEQ_CONTROL_0_SECURE 0x0 +#define DC_DISP_INIT_SEQ_CONTROL_0_WORD_COUNT 0x1 +#define DC_DISP_INIT_SEQ_CONTROL_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_INIT_SEQ_CONTROL_0_RESET_MASK _MK_MASK_CONST(0x3) +#define DC_DISP_INIT_SEQ_CONTROL_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_INIT_SEQ_CONTROL_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_INIT_SEQ_CONTROL_0_READ_MASK _MK_MASK_CONST(0xff3) +#define DC_DISP_INIT_SEQ_CONTROL_0_WRITE_MASK _MK_MASK_CONST(0xff3) +#define DC_DISP_INIT_SEQ_CONTROL_0_SEND_INIT_SEQUENCE_SHIFT _MK_SHIFT_CONST(0) +#define DC_DISP_INIT_SEQ_CONTROL_0_SEND_INIT_SEQUENCE_FIELD _MK_FIELD_CONST(0x1, DC_DISP_INIT_SEQ_CONTROL_0_SEND_INIT_SEQUENCE_SHIFT) +#define DC_DISP_INIT_SEQ_CONTROL_0_SEND_INIT_SEQUENCE_RANGE 0:0 +#define DC_DISP_INIT_SEQ_CONTROL_0_SEND_INIT_SEQUENCE_WOFFSET 0x0 +#define DC_DISP_INIT_SEQ_CONTROL_0_SEND_INIT_SEQUENCE_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_INIT_SEQ_CONTROL_0_SEND_INIT_SEQUENCE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_DISP_INIT_SEQ_CONTROL_0_SEND_INIT_SEQUENCE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_INIT_SEQ_CONTROL_0_SEND_INIT_SEQUENCE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_INIT_SEQ_CONTROL_0_SEND_INIT_SEQUENCE_DISABLE _MK_ENUM_CONST(0) +#define DC_DISP_INIT_SEQ_CONTROL_0_SEND_INIT_SEQUENCE_ENABLE _MK_ENUM_CONST(1) + +#define DC_DISP_INIT_SEQ_CONTROL_0_INIT_SEQUENCE_MODE_SHIFT _MK_SHIFT_CONST(1) +#define DC_DISP_INIT_SEQ_CONTROL_0_INIT_SEQUENCE_MODE_FIELD _MK_FIELD_CONST(0x1, DC_DISP_INIT_SEQ_CONTROL_0_INIT_SEQUENCE_MODE_SHIFT) +#define DC_DISP_INIT_SEQ_CONTROL_0_INIT_SEQUENCE_MODE_RANGE 1:1 +#define DC_DISP_INIT_SEQ_CONTROL_0_INIT_SEQUENCE_MODE_WOFFSET 0x0 +#define DC_DISP_INIT_SEQ_CONTROL_0_INIT_SEQUENCE_MODE_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_INIT_SEQ_CONTROL_0_INIT_SEQUENCE_MODE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_DISP_INIT_SEQ_CONTROL_0_INIT_SEQUENCE_MODE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_INIT_SEQ_CONTROL_0_INIT_SEQUENCE_MODE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_INIT_SEQ_CONTROL_0_INIT_SEQUENCE_MODE_PLCD_INIT _MK_ENUM_CONST(0) +#define DC_DISP_INIT_SEQ_CONTROL_0_INIT_SEQUENCE_MODE_SPI_INIT _MK_ENUM_CONST(1) + +#define DC_DISP_INIT_SEQ_CONTROL_0_INIT_SEQ_DC_SIGNAL_SHIFT _MK_SHIFT_CONST(4) +#define DC_DISP_INIT_SEQ_CONTROL_0_INIT_SEQ_DC_SIGNAL_FIELD _MK_FIELD_CONST(0x7, DC_DISP_INIT_SEQ_CONTROL_0_INIT_SEQ_DC_SIGNAL_SHIFT) +#define DC_DISP_INIT_SEQ_CONTROL_0_INIT_SEQ_DC_SIGNAL_RANGE 6:4 +#define DC_DISP_INIT_SEQ_CONTROL_0_INIT_SEQ_DC_SIGNAL_WOFFSET 0x0 +#define DC_DISP_INIT_SEQ_CONTROL_0_INIT_SEQ_DC_SIGNAL_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_INIT_SEQ_CONTROL_0_INIT_SEQ_DC_SIGNAL_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_INIT_SEQ_CONTROL_0_INIT_SEQ_DC_SIGNAL_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_INIT_SEQ_CONTROL_0_INIT_SEQ_DC_SIGNAL_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_INIT_SEQ_CONTROL_0_INIT_SEQ_DC_SIGNAL_NODC _MK_ENUM_CONST(0) +#define DC_DISP_INIT_SEQ_CONTROL_0_INIT_SEQ_DC_SIGNAL_VSYNC _MK_ENUM_CONST(1) +#define DC_DISP_INIT_SEQ_CONTROL_0_INIT_SEQ_DC_SIGNAL_VPULSE0 _MK_ENUM_CONST(2) +#define DC_DISP_INIT_SEQ_CONTROL_0_INIT_SEQ_DC_SIGNAL_VPULSE1 _MK_ENUM_CONST(3) +#define DC_DISP_INIT_SEQ_CONTROL_0_INIT_SEQ_DC_SIGNAL_VPULSE2 _MK_ENUM_CONST(4) +#define DC_DISP_INIT_SEQ_CONTROL_0_INIT_SEQ_DC_SIGNAL_VPULSE3 _MK_ENUM_CONST(5) + +#define DC_DISP_INIT_SEQ_CONTROL_0_INIT_SEQ_DC_CONTROL_SHIFT _MK_SHIFT_CONST(7) +#define DC_DISP_INIT_SEQ_CONTROL_0_INIT_SEQ_DC_CONTROL_FIELD _MK_FIELD_CONST(0x1, DC_DISP_INIT_SEQ_CONTROL_0_INIT_SEQ_DC_CONTROL_SHIFT) +#define DC_DISP_INIT_SEQ_CONTROL_0_INIT_SEQ_DC_CONTROL_RANGE 7:7 +#define DC_DISP_INIT_SEQ_CONTROL_0_INIT_SEQ_DC_CONTROL_WOFFSET 0x0 +#define DC_DISP_INIT_SEQ_CONTROL_0_INIT_SEQ_DC_CONTROL_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_INIT_SEQ_CONTROL_0_INIT_SEQ_DC_CONTROL_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_INIT_SEQ_CONTROL_0_INIT_SEQ_DC_CONTROL_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_INIT_SEQ_CONTROL_0_INIT_SEQ_DC_CONTROL_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_DISP_INIT_SEQ_CONTROL_0_FRAME_INIT_SEQ_CYCLES_SHIFT _MK_SHIFT_CONST(8) +#define DC_DISP_INIT_SEQ_CONTROL_0_FRAME_INIT_SEQ_CYCLES_FIELD _MK_FIELD_CONST(0xf, DC_DISP_INIT_SEQ_CONTROL_0_FRAME_INIT_SEQ_CYCLES_SHIFT) +#define DC_DISP_INIT_SEQ_CONTROL_0_FRAME_INIT_SEQ_CYCLES_RANGE 11:8 +#define DC_DISP_INIT_SEQ_CONTROL_0_FRAME_INIT_SEQ_CYCLES_WOFFSET 0x0 +#define DC_DISP_INIT_SEQ_CONTROL_0_FRAME_INIT_SEQ_CYCLES_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_INIT_SEQ_CONTROL_0_FRAME_INIT_SEQ_CYCLES_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_INIT_SEQ_CONTROL_0_FRAME_INIT_SEQ_CYCLES_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_INIT_SEQ_CONTROL_0_FRAME_INIT_SEQ_CYCLES_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_DISP_SPI_INIT_SEQ_DATA_A_0 +#define DC_DISP_SPI_INIT_SEQ_DATA_A_0 _MK_ADDR_CONST(0x443) +#define DC_DISP_SPI_INIT_SEQ_DATA_A_0_SECURE 0x0 +#define DC_DISP_SPI_INIT_SEQ_DATA_A_0_WORD_COUNT 0x1 +#define DC_DISP_SPI_INIT_SEQ_DATA_A_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_SPI_INIT_SEQ_DATA_A_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_SPI_INIT_SEQ_DATA_A_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_SPI_INIT_SEQ_DATA_A_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_SPI_INIT_SEQ_DATA_A_0_READ_MASK _MK_MASK_CONST(0xffffffff) +#define DC_DISP_SPI_INIT_SEQ_DATA_A_0_WRITE_MASK _MK_MASK_CONST(0xffffffff) +#define DC_DISP_SPI_INIT_SEQ_DATA_A_0_SPI_INIT_SEQ_DATA_A_SHIFT _MK_SHIFT_CONST(0) +#define DC_DISP_SPI_INIT_SEQ_DATA_A_0_SPI_INIT_SEQ_DATA_A_FIELD _MK_FIELD_CONST(0xffffffff, DC_DISP_SPI_INIT_SEQ_DATA_A_0_SPI_INIT_SEQ_DATA_A_SHIFT) +#define DC_DISP_SPI_INIT_SEQ_DATA_A_0_SPI_INIT_SEQ_DATA_A_RANGE 31:0 +#define DC_DISP_SPI_INIT_SEQ_DATA_A_0_SPI_INIT_SEQ_DATA_A_WOFFSET 0x0 +#define DC_DISP_SPI_INIT_SEQ_DATA_A_0_SPI_INIT_SEQ_DATA_A_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SPI_INIT_SEQ_DATA_A_0_SPI_INIT_SEQ_DATA_A_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_SPI_INIT_SEQ_DATA_A_0_SPI_INIT_SEQ_DATA_A_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SPI_INIT_SEQ_DATA_A_0_SPI_INIT_SEQ_DATA_A_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_DISP_SPI_INIT_SEQ_DATA_B_0 +#define DC_DISP_SPI_INIT_SEQ_DATA_B_0 _MK_ADDR_CONST(0x444) +#define DC_DISP_SPI_INIT_SEQ_DATA_B_0_SECURE 0x0 +#define DC_DISP_SPI_INIT_SEQ_DATA_B_0_WORD_COUNT 0x1 +#define DC_DISP_SPI_INIT_SEQ_DATA_B_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_SPI_INIT_SEQ_DATA_B_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_SPI_INIT_SEQ_DATA_B_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_SPI_INIT_SEQ_DATA_B_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_SPI_INIT_SEQ_DATA_B_0_READ_MASK _MK_MASK_CONST(0xffffffff) +#define DC_DISP_SPI_INIT_SEQ_DATA_B_0_WRITE_MASK _MK_MASK_CONST(0xffffffff) +#define DC_DISP_SPI_INIT_SEQ_DATA_B_0_SPI_INIT_SEQ_DATA_B_SHIFT _MK_SHIFT_CONST(0) +#define DC_DISP_SPI_INIT_SEQ_DATA_B_0_SPI_INIT_SEQ_DATA_B_FIELD _MK_FIELD_CONST(0xffffffff, DC_DISP_SPI_INIT_SEQ_DATA_B_0_SPI_INIT_SEQ_DATA_B_SHIFT) +#define DC_DISP_SPI_INIT_SEQ_DATA_B_0_SPI_INIT_SEQ_DATA_B_RANGE 31:0 +#define DC_DISP_SPI_INIT_SEQ_DATA_B_0_SPI_INIT_SEQ_DATA_B_WOFFSET 0x0 +#define DC_DISP_SPI_INIT_SEQ_DATA_B_0_SPI_INIT_SEQ_DATA_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SPI_INIT_SEQ_DATA_B_0_SPI_INIT_SEQ_DATA_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_SPI_INIT_SEQ_DATA_B_0_SPI_INIT_SEQ_DATA_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SPI_INIT_SEQ_DATA_B_0_SPI_INIT_SEQ_DATA_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_DISP_SPI_INIT_SEQ_DATA_C_0 +#define DC_DISP_SPI_INIT_SEQ_DATA_C_0 _MK_ADDR_CONST(0x445) +#define DC_DISP_SPI_INIT_SEQ_DATA_C_0_SECURE 0x0 +#define DC_DISP_SPI_INIT_SEQ_DATA_C_0_WORD_COUNT 0x1 +#define DC_DISP_SPI_INIT_SEQ_DATA_C_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_SPI_INIT_SEQ_DATA_C_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_SPI_INIT_SEQ_DATA_C_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_SPI_INIT_SEQ_DATA_C_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_SPI_INIT_SEQ_DATA_C_0_READ_MASK _MK_MASK_CONST(0xffffffff) +#define DC_DISP_SPI_INIT_SEQ_DATA_C_0_WRITE_MASK _MK_MASK_CONST(0xffffffff) +#define DC_DISP_SPI_INIT_SEQ_DATA_C_0_SPI_INIT_SEQ_DATA_C_SHIFT _MK_SHIFT_CONST(0) +#define DC_DISP_SPI_INIT_SEQ_DATA_C_0_SPI_INIT_SEQ_DATA_C_FIELD _MK_FIELD_CONST(0xffffffff, DC_DISP_SPI_INIT_SEQ_DATA_C_0_SPI_INIT_SEQ_DATA_C_SHIFT) +#define DC_DISP_SPI_INIT_SEQ_DATA_C_0_SPI_INIT_SEQ_DATA_C_RANGE 31:0 +#define DC_DISP_SPI_INIT_SEQ_DATA_C_0_SPI_INIT_SEQ_DATA_C_WOFFSET 0x0 +#define DC_DISP_SPI_INIT_SEQ_DATA_C_0_SPI_INIT_SEQ_DATA_C_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SPI_INIT_SEQ_DATA_C_0_SPI_INIT_SEQ_DATA_C_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_SPI_INIT_SEQ_DATA_C_0_SPI_INIT_SEQ_DATA_C_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SPI_INIT_SEQ_DATA_C_0_SPI_INIT_SEQ_DATA_C_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_DISP_SPI_INIT_SEQ_DATA_D_0 +#define DC_DISP_SPI_INIT_SEQ_DATA_D_0 _MK_ADDR_CONST(0x446) +#define DC_DISP_SPI_INIT_SEQ_DATA_D_0_SECURE 0x0 +#define DC_DISP_SPI_INIT_SEQ_DATA_D_0_WORD_COUNT 0x1 +#define DC_DISP_SPI_INIT_SEQ_DATA_D_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_SPI_INIT_SEQ_DATA_D_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_SPI_INIT_SEQ_DATA_D_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_SPI_INIT_SEQ_DATA_D_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_SPI_INIT_SEQ_DATA_D_0_READ_MASK _MK_MASK_CONST(0xffffffff) +#define DC_DISP_SPI_INIT_SEQ_DATA_D_0_WRITE_MASK _MK_MASK_CONST(0xffffffff) +#define DC_DISP_SPI_INIT_SEQ_DATA_D_0_SPI_INIT_SEQ_DATA_D_SHIFT _MK_SHIFT_CONST(0) +#define DC_DISP_SPI_INIT_SEQ_DATA_D_0_SPI_INIT_SEQ_DATA_D_FIELD _MK_FIELD_CONST(0xffffffff, DC_DISP_SPI_INIT_SEQ_DATA_D_0_SPI_INIT_SEQ_DATA_D_SHIFT) +#define DC_DISP_SPI_INIT_SEQ_DATA_D_0_SPI_INIT_SEQ_DATA_D_RANGE 31:0 +#define DC_DISP_SPI_INIT_SEQ_DATA_D_0_SPI_INIT_SEQ_DATA_D_WOFFSET 0x0 +#define DC_DISP_SPI_INIT_SEQ_DATA_D_0_SPI_INIT_SEQ_DATA_D_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SPI_INIT_SEQ_DATA_D_0_SPI_INIT_SEQ_DATA_D_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_SPI_INIT_SEQ_DATA_D_0_SPI_INIT_SEQ_DATA_D_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SPI_INIT_SEQ_DATA_D_0_SPI_INIT_SEQ_DATA_D_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_DISP_DC_MCCIF_FIFOCTRL_0 +#define DC_DISP_DC_MCCIF_FIFOCTRL_0 _MK_ADDR_CONST(0x480) +#define DC_DISP_DC_MCCIF_FIFOCTRL_0_SECURE 0x0 +#define DC_DISP_DC_MCCIF_FIFOCTRL_0_WORD_COUNT 0x1 +#define DC_DISP_DC_MCCIF_FIFOCTRL_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_DC_MCCIF_FIFOCTRL_0_RESET_MASK _MK_MASK_CONST(0x1f000f) +#define DC_DISP_DC_MCCIF_FIFOCTRL_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_DC_MCCIF_FIFOCTRL_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_DC_MCCIF_FIFOCTRL_0_READ_MASK _MK_MASK_CONST(0x1f000f) +#define DC_DISP_DC_MCCIF_FIFOCTRL_0_WRITE_MASK _MK_MASK_CONST(0x1f000f) +#define DC_DISP_DC_MCCIF_FIFOCTRL_0_DC_MCCIF_WRCL_MCLE2X_SHIFT _MK_SHIFT_CONST(0) +#define DC_DISP_DC_MCCIF_FIFOCTRL_0_DC_MCCIF_WRCL_MCLE2X_FIELD _MK_FIELD_CONST(0x1, DC_DISP_DC_MCCIF_FIFOCTRL_0_DC_MCCIF_WRCL_MCLE2X_SHIFT) +#define DC_DISP_DC_MCCIF_FIFOCTRL_0_DC_MCCIF_WRCL_MCLE2X_RANGE 0:0 +#define DC_DISP_DC_MCCIF_FIFOCTRL_0_DC_MCCIF_WRCL_MCLE2X_WOFFSET 0x0 +#define DC_DISP_DC_MCCIF_FIFOCTRL_0_DC_MCCIF_WRCL_MCLE2X_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_DC_MCCIF_FIFOCTRL_0_DC_MCCIF_WRCL_MCLE2X_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_DISP_DC_MCCIF_FIFOCTRL_0_DC_MCCIF_WRCL_MCLE2X_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_DC_MCCIF_FIFOCTRL_0_DC_MCCIF_WRCL_MCLE2X_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_DC_MCCIF_FIFOCTRL_0_DC_MCCIF_WRCL_MCLE2X_INIT_ENUM DISABLE +#define DC_DISP_DC_MCCIF_FIFOCTRL_0_DC_MCCIF_WRCL_MCLE2X_DISABLE _MK_ENUM_CONST(0) +#define DC_DISP_DC_MCCIF_FIFOCTRL_0_DC_MCCIF_WRCL_MCLE2X_ENABLE _MK_ENUM_CONST(1) + +#define DC_DISP_DC_MCCIF_FIFOCTRL_0_DC_MCCIF_RDMC_RDFAST_SHIFT _MK_SHIFT_CONST(1) +#define DC_DISP_DC_MCCIF_FIFOCTRL_0_DC_MCCIF_RDMC_RDFAST_FIELD _MK_FIELD_CONST(0x1, DC_DISP_DC_MCCIF_FIFOCTRL_0_DC_MCCIF_RDMC_RDFAST_SHIFT) +#define DC_DISP_DC_MCCIF_FIFOCTRL_0_DC_MCCIF_RDMC_RDFAST_RANGE 1:1 +#define DC_DISP_DC_MCCIF_FIFOCTRL_0_DC_MCCIF_RDMC_RDFAST_WOFFSET 0x0 +#define DC_DISP_DC_MCCIF_FIFOCTRL_0_DC_MCCIF_RDMC_RDFAST_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_DC_MCCIF_FIFOCTRL_0_DC_MCCIF_RDMC_RDFAST_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_DISP_DC_MCCIF_FIFOCTRL_0_DC_MCCIF_RDMC_RDFAST_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_DC_MCCIF_FIFOCTRL_0_DC_MCCIF_RDMC_RDFAST_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_DC_MCCIF_FIFOCTRL_0_DC_MCCIF_RDMC_RDFAST_INIT_ENUM DISABLE +#define DC_DISP_DC_MCCIF_FIFOCTRL_0_DC_MCCIF_RDMC_RDFAST_DISABLE _MK_ENUM_CONST(0) +#define DC_DISP_DC_MCCIF_FIFOCTRL_0_DC_MCCIF_RDMC_RDFAST_ENABLE _MK_ENUM_CONST(1) + +#define DC_DISP_DC_MCCIF_FIFOCTRL_0_DC_MCCIF_WRMC_CLLE2X_SHIFT _MK_SHIFT_CONST(2) +#define DC_DISP_DC_MCCIF_FIFOCTRL_0_DC_MCCIF_WRMC_CLLE2X_FIELD _MK_FIELD_CONST(0x1, DC_DISP_DC_MCCIF_FIFOCTRL_0_DC_MCCIF_WRMC_CLLE2X_SHIFT) +#define DC_DISP_DC_MCCIF_FIFOCTRL_0_DC_MCCIF_WRMC_CLLE2X_RANGE 2:2 +#define DC_DISP_DC_MCCIF_FIFOCTRL_0_DC_MCCIF_WRMC_CLLE2X_WOFFSET 0x0 +#define DC_DISP_DC_MCCIF_FIFOCTRL_0_DC_MCCIF_WRMC_CLLE2X_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_DC_MCCIF_FIFOCTRL_0_DC_MCCIF_WRMC_CLLE2X_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_DISP_DC_MCCIF_FIFOCTRL_0_DC_MCCIF_WRMC_CLLE2X_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_DC_MCCIF_FIFOCTRL_0_DC_MCCIF_WRMC_CLLE2X_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_DC_MCCIF_FIFOCTRL_0_DC_MCCIF_WRMC_CLLE2X_INIT_ENUM DISABLE +#define DC_DISP_DC_MCCIF_FIFOCTRL_0_DC_MCCIF_WRMC_CLLE2X_DISABLE _MK_ENUM_CONST(0) +#define DC_DISP_DC_MCCIF_FIFOCTRL_0_DC_MCCIF_WRMC_CLLE2X_ENABLE _MK_ENUM_CONST(1) + +#define DC_DISP_DC_MCCIF_FIFOCTRL_0_DC_MCCIF_RDCL_RDFAST_SHIFT _MK_SHIFT_CONST(3) +#define DC_DISP_DC_MCCIF_FIFOCTRL_0_DC_MCCIF_RDCL_RDFAST_FIELD _MK_FIELD_CONST(0x1, DC_DISP_DC_MCCIF_FIFOCTRL_0_DC_MCCIF_RDCL_RDFAST_SHIFT) +#define DC_DISP_DC_MCCIF_FIFOCTRL_0_DC_MCCIF_RDCL_RDFAST_RANGE 3:3 +#define DC_DISP_DC_MCCIF_FIFOCTRL_0_DC_MCCIF_RDCL_RDFAST_WOFFSET 0x0 +#define DC_DISP_DC_MCCIF_FIFOCTRL_0_DC_MCCIF_RDCL_RDFAST_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_DC_MCCIF_FIFOCTRL_0_DC_MCCIF_RDCL_RDFAST_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_DISP_DC_MCCIF_FIFOCTRL_0_DC_MCCIF_RDCL_RDFAST_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_DC_MCCIF_FIFOCTRL_0_DC_MCCIF_RDCL_RDFAST_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_DC_MCCIF_FIFOCTRL_0_DC_MCCIF_RDCL_RDFAST_INIT_ENUM DISABLE +#define DC_DISP_DC_MCCIF_FIFOCTRL_0_DC_MCCIF_RDCL_RDFAST_DISABLE _MK_ENUM_CONST(0) +#define DC_DISP_DC_MCCIF_FIFOCTRL_0_DC_MCCIF_RDCL_RDFAST_ENABLE _MK_ENUM_CONST(1) + +#define DC_DISP_DC_MCCIF_FIFOCTRL_0_DC_WCLK_OVERRIDE_SHIFT _MK_SHIFT_CONST(16) +#define DC_DISP_DC_MCCIF_FIFOCTRL_0_DC_WCLK_OVERRIDE_FIELD _MK_FIELD_CONST(0x1, DC_DISP_DC_MCCIF_FIFOCTRL_0_DC_WCLK_OVERRIDE_SHIFT) +#define DC_DISP_DC_MCCIF_FIFOCTRL_0_DC_WCLK_OVERRIDE_RANGE 16:16 +#define DC_DISP_DC_MCCIF_FIFOCTRL_0_DC_WCLK_OVERRIDE_WOFFSET 0x0 +#define DC_DISP_DC_MCCIF_FIFOCTRL_0_DC_WCLK_OVERRIDE_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_DC_MCCIF_FIFOCTRL_0_DC_WCLK_OVERRIDE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_DISP_DC_MCCIF_FIFOCTRL_0_DC_WCLK_OVERRIDE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_DC_MCCIF_FIFOCTRL_0_DC_WCLK_OVERRIDE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_DISP_DC_MCCIF_FIFOCTRL_0_DC_RCLK_OVERRIDE_SHIFT _MK_SHIFT_CONST(17) +#define DC_DISP_DC_MCCIF_FIFOCTRL_0_DC_RCLK_OVERRIDE_FIELD _MK_FIELD_CONST(0x1, DC_DISP_DC_MCCIF_FIFOCTRL_0_DC_RCLK_OVERRIDE_SHIFT) +#define DC_DISP_DC_MCCIF_FIFOCTRL_0_DC_RCLK_OVERRIDE_RANGE 17:17 +#define DC_DISP_DC_MCCIF_FIFOCTRL_0_DC_RCLK_OVERRIDE_WOFFSET 0x0 +#define DC_DISP_DC_MCCIF_FIFOCTRL_0_DC_RCLK_OVERRIDE_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_DC_MCCIF_FIFOCTRL_0_DC_RCLK_OVERRIDE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_DISP_DC_MCCIF_FIFOCTRL_0_DC_RCLK_OVERRIDE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_DC_MCCIF_FIFOCTRL_0_DC_RCLK_OVERRIDE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_DISP_DC_MCCIF_FIFOCTRL_0_DC_CCLK_OVERRIDE_SHIFT _MK_SHIFT_CONST(18) +#define DC_DISP_DC_MCCIF_FIFOCTRL_0_DC_CCLK_OVERRIDE_FIELD _MK_FIELD_CONST(0x1, DC_DISP_DC_MCCIF_FIFOCTRL_0_DC_CCLK_OVERRIDE_SHIFT) +#define DC_DISP_DC_MCCIF_FIFOCTRL_0_DC_CCLK_OVERRIDE_RANGE 18:18 +#define DC_DISP_DC_MCCIF_FIFOCTRL_0_DC_CCLK_OVERRIDE_WOFFSET 0x0 +#define DC_DISP_DC_MCCIF_FIFOCTRL_0_DC_CCLK_OVERRIDE_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_DC_MCCIF_FIFOCTRL_0_DC_CCLK_OVERRIDE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_DISP_DC_MCCIF_FIFOCTRL_0_DC_CCLK_OVERRIDE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_DC_MCCIF_FIFOCTRL_0_DC_CCLK_OVERRIDE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_DISP_DC_MCCIF_FIFOCTRL_0_DC_WCLK_OVR_MODE_SHIFT _MK_SHIFT_CONST(19) +#define DC_DISP_DC_MCCIF_FIFOCTRL_0_DC_WCLK_OVR_MODE_FIELD _MK_FIELD_CONST(0x1, DC_DISP_DC_MCCIF_FIFOCTRL_0_DC_WCLK_OVR_MODE_SHIFT) +#define DC_DISP_DC_MCCIF_FIFOCTRL_0_DC_WCLK_OVR_MODE_RANGE 19:19 +#define DC_DISP_DC_MCCIF_FIFOCTRL_0_DC_WCLK_OVR_MODE_WOFFSET 0x0 +#define DC_DISP_DC_MCCIF_FIFOCTRL_0_DC_WCLK_OVR_MODE_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_DC_MCCIF_FIFOCTRL_0_DC_WCLK_OVR_MODE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_DISP_DC_MCCIF_FIFOCTRL_0_DC_WCLK_OVR_MODE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_DC_MCCIF_FIFOCTRL_0_DC_WCLK_OVR_MODE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_DC_MCCIF_FIFOCTRL_0_DC_WCLK_OVR_MODE_INIT_ENUM LEGACY +#define DC_DISP_DC_MCCIF_FIFOCTRL_0_DC_WCLK_OVR_MODE_LEGACY _MK_ENUM_CONST(0) +#define DC_DISP_DC_MCCIF_FIFOCTRL_0_DC_WCLK_OVR_MODE_ON _MK_ENUM_CONST(1) + +#define DC_DISP_DC_MCCIF_FIFOCTRL_0_DC_RCLK_OVR_MODE_SHIFT _MK_SHIFT_CONST(20) +#define DC_DISP_DC_MCCIF_FIFOCTRL_0_DC_RCLK_OVR_MODE_FIELD _MK_FIELD_CONST(0x1, DC_DISP_DC_MCCIF_FIFOCTRL_0_DC_RCLK_OVR_MODE_SHIFT) +#define DC_DISP_DC_MCCIF_FIFOCTRL_0_DC_RCLK_OVR_MODE_RANGE 20:20 +#define DC_DISP_DC_MCCIF_FIFOCTRL_0_DC_RCLK_OVR_MODE_WOFFSET 0x0 +#define DC_DISP_DC_MCCIF_FIFOCTRL_0_DC_RCLK_OVR_MODE_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_DC_MCCIF_FIFOCTRL_0_DC_RCLK_OVR_MODE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_DISP_DC_MCCIF_FIFOCTRL_0_DC_RCLK_OVR_MODE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_DC_MCCIF_FIFOCTRL_0_DC_RCLK_OVR_MODE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_DC_MCCIF_FIFOCTRL_0_DC_RCLK_OVR_MODE_INIT_ENUM LEGACY +#define DC_DISP_DC_MCCIF_FIFOCTRL_0_DC_RCLK_OVR_MODE_LEGACY _MK_ENUM_CONST(0) +#define DC_DISP_DC_MCCIF_FIFOCTRL_0_DC_RCLK_OVR_MODE_ON _MK_ENUM_CONST(1) + + +// Register DC_DISP_MCCIF_DISPLAY0A_HYST_0 +#define DC_DISP_MCCIF_DISPLAY0A_HYST_0 _MK_ADDR_CONST(0x481) +#define DC_DISP_MCCIF_DISPLAY0A_HYST_0_SECURE 0x0 +#define DC_DISP_MCCIF_DISPLAY0A_HYST_0_WORD_COUNT 0x1 +#define DC_DISP_MCCIF_DISPLAY0A_HYST_0_RESET_VAL _MK_MASK_CONST(0xcf401f1f) +#define DC_DISP_MCCIF_DISPLAY0A_HYST_0_RESET_MASK _MK_MASK_CONST(0xffffffff) +#define DC_DISP_MCCIF_DISPLAY0A_HYST_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_MCCIF_DISPLAY0A_HYST_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_MCCIF_DISPLAY0A_HYST_0_READ_MASK _MK_MASK_CONST(0xffffffff) +#define DC_DISP_MCCIF_DISPLAY0A_HYST_0_WRITE_MASK _MK_MASK_CONST(0xffffffff) +#define DC_DISP_MCCIF_DISPLAY0A_HYST_0_CSR_DISPLAY0A2MC_HYST_REQ_TM_SHIFT _MK_SHIFT_CONST(0) +#define DC_DISP_MCCIF_DISPLAY0A_HYST_0_CSR_DISPLAY0A2MC_HYST_REQ_TM_FIELD _MK_FIELD_CONST(0xff, DC_DISP_MCCIF_DISPLAY0A_HYST_0_CSR_DISPLAY0A2MC_HYST_REQ_TM_SHIFT) +#define DC_DISP_MCCIF_DISPLAY0A_HYST_0_CSR_DISPLAY0A2MC_HYST_REQ_TM_RANGE 7:0 +#define DC_DISP_MCCIF_DISPLAY0A_HYST_0_CSR_DISPLAY0A2MC_HYST_REQ_TM_WOFFSET 0x0 +#define DC_DISP_MCCIF_DISPLAY0A_HYST_0_CSR_DISPLAY0A2MC_HYST_REQ_TM_DEFAULT _MK_MASK_CONST(0x1f) +#define DC_DISP_MCCIF_DISPLAY0A_HYST_0_CSR_DISPLAY0A2MC_HYST_REQ_TM_DEFAULT_MASK _MK_MASK_CONST(0xff) +#define DC_DISP_MCCIF_DISPLAY0A_HYST_0_CSR_DISPLAY0A2MC_HYST_REQ_TM_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_MCCIF_DISPLAY0A_HYST_0_CSR_DISPLAY0A2MC_HYST_REQ_TM_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_DISP_MCCIF_DISPLAY0A_HYST_0_CSR_DISPLAY0A2MC_DHYST_TM_SHIFT _MK_SHIFT_CONST(8) +#define DC_DISP_MCCIF_DISPLAY0A_HYST_0_CSR_DISPLAY0A2MC_DHYST_TM_FIELD _MK_FIELD_CONST(0xff, DC_DISP_MCCIF_DISPLAY0A_HYST_0_CSR_DISPLAY0A2MC_DHYST_TM_SHIFT) +#define DC_DISP_MCCIF_DISPLAY0A_HYST_0_CSR_DISPLAY0A2MC_DHYST_TM_RANGE 15:8 +#define DC_DISP_MCCIF_DISPLAY0A_HYST_0_CSR_DISPLAY0A2MC_DHYST_TM_WOFFSET 0x0 +#define DC_DISP_MCCIF_DISPLAY0A_HYST_0_CSR_DISPLAY0A2MC_DHYST_TM_DEFAULT _MK_MASK_CONST(0x1f) +#define DC_DISP_MCCIF_DISPLAY0A_HYST_0_CSR_DISPLAY0A2MC_DHYST_TM_DEFAULT_MASK _MK_MASK_CONST(0xff) +#define DC_DISP_MCCIF_DISPLAY0A_HYST_0_CSR_DISPLAY0A2MC_DHYST_TM_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_MCCIF_DISPLAY0A_HYST_0_CSR_DISPLAY0A2MC_DHYST_TM_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_DISP_MCCIF_DISPLAY0A_HYST_0_CSR_DISPLAY0A2MC_DHYST_TH_SHIFT _MK_SHIFT_CONST(16) +#define DC_DISP_MCCIF_DISPLAY0A_HYST_0_CSR_DISPLAY0A2MC_DHYST_TH_FIELD _MK_FIELD_CONST(0xff, DC_DISP_MCCIF_DISPLAY0A_HYST_0_CSR_DISPLAY0A2MC_DHYST_TH_SHIFT) +#define DC_DISP_MCCIF_DISPLAY0A_HYST_0_CSR_DISPLAY0A2MC_DHYST_TH_RANGE 23:16 +#define DC_DISP_MCCIF_DISPLAY0A_HYST_0_CSR_DISPLAY0A2MC_DHYST_TH_WOFFSET 0x0 +#define DC_DISP_MCCIF_DISPLAY0A_HYST_0_CSR_DISPLAY0A2MC_DHYST_TH_DEFAULT _MK_MASK_CONST(0x40) +#define DC_DISP_MCCIF_DISPLAY0A_HYST_0_CSR_DISPLAY0A2MC_DHYST_TH_DEFAULT_MASK _MK_MASK_CONST(0xff) +#define DC_DISP_MCCIF_DISPLAY0A_HYST_0_CSR_DISPLAY0A2MC_DHYST_TH_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_MCCIF_DISPLAY0A_HYST_0_CSR_DISPLAY0A2MC_DHYST_TH_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_DISP_MCCIF_DISPLAY0A_HYST_0_CSR_DISPLAY0A2MC_HYST_TM_SHIFT _MK_SHIFT_CONST(24) +#define DC_DISP_MCCIF_DISPLAY0A_HYST_0_CSR_DISPLAY0A2MC_HYST_TM_FIELD _MK_FIELD_CONST(0xf, DC_DISP_MCCIF_DISPLAY0A_HYST_0_CSR_DISPLAY0A2MC_HYST_TM_SHIFT) +#define DC_DISP_MCCIF_DISPLAY0A_HYST_0_CSR_DISPLAY0A2MC_HYST_TM_RANGE 27:24 +#define DC_DISP_MCCIF_DISPLAY0A_HYST_0_CSR_DISPLAY0A2MC_HYST_TM_WOFFSET 0x0 +#define DC_DISP_MCCIF_DISPLAY0A_HYST_0_CSR_DISPLAY0A2MC_HYST_TM_DEFAULT _MK_MASK_CONST(0xf) +#define DC_DISP_MCCIF_DISPLAY0A_HYST_0_CSR_DISPLAY0A2MC_HYST_TM_DEFAULT_MASK _MK_MASK_CONST(0xf) +#define DC_DISP_MCCIF_DISPLAY0A_HYST_0_CSR_DISPLAY0A2MC_HYST_TM_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_MCCIF_DISPLAY0A_HYST_0_CSR_DISPLAY0A2MC_HYST_TM_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_DISP_MCCIF_DISPLAY0A_HYST_0_CSR_DISPLAY0A2MC_HYST_REQ_TH_SHIFT _MK_SHIFT_CONST(28) +#define DC_DISP_MCCIF_DISPLAY0A_HYST_0_CSR_DISPLAY0A2MC_HYST_REQ_TH_FIELD _MK_FIELD_CONST(0x7, DC_DISP_MCCIF_DISPLAY0A_HYST_0_CSR_DISPLAY0A2MC_HYST_REQ_TH_SHIFT) +#define DC_DISP_MCCIF_DISPLAY0A_HYST_0_CSR_DISPLAY0A2MC_HYST_REQ_TH_RANGE 30:28 +#define DC_DISP_MCCIF_DISPLAY0A_HYST_0_CSR_DISPLAY0A2MC_HYST_REQ_TH_WOFFSET 0x0 +#define DC_DISP_MCCIF_DISPLAY0A_HYST_0_CSR_DISPLAY0A2MC_HYST_REQ_TH_DEFAULT _MK_MASK_CONST(0x4) +#define DC_DISP_MCCIF_DISPLAY0A_HYST_0_CSR_DISPLAY0A2MC_HYST_REQ_TH_DEFAULT_MASK _MK_MASK_CONST(0x7) +#define DC_DISP_MCCIF_DISPLAY0A_HYST_0_CSR_DISPLAY0A2MC_HYST_REQ_TH_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_MCCIF_DISPLAY0A_HYST_0_CSR_DISPLAY0A2MC_HYST_REQ_TH_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_DISP_MCCIF_DISPLAY0A_HYST_0_CSR_DISPLAY0A2MC_HYST_EN_SHIFT _MK_SHIFT_CONST(31) +#define DC_DISP_MCCIF_DISPLAY0A_HYST_0_CSR_DISPLAY0A2MC_HYST_EN_FIELD _MK_FIELD_CONST(0x1, DC_DISP_MCCIF_DISPLAY0A_HYST_0_CSR_DISPLAY0A2MC_HYST_EN_SHIFT) +#define DC_DISP_MCCIF_DISPLAY0A_HYST_0_CSR_DISPLAY0A2MC_HYST_EN_RANGE 31:31 +#define DC_DISP_MCCIF_DISPLAY0A_HYST_0_CSR_DISPLAY0A2MC_HYST_EN_WOFFSET 0x0 +#define DC_DISP_MCCIF_DISPLAY0A_HYST_0_CSR_DISPLAY0A2MC_HYST_EN_DEFAULT _MK_MASK_CONST(0x1) +#define DC_DISP_MCCIF_DISPLAY0A_HYST_0_CSR_DISPLAY0A2MC_HYST_EN_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_DISP_MCCIF_DISPLAY0A_HYST_0_CSR_DISPLAY0A2MC_HYST_EN_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_MCCIF_DISPLAY0A_HYST_0_CSR_DISPLAY0A2MC_HYST_EN_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_MCCIF_DISPLAY0A_HYST_0_CSR_DISPLAY0A2MC_HYST_EN_INIT_ENUM ENABLE +#define DC_DISP_MCCIF_DISPLAY0A_HYST_0_CSR_DISPLAY0A2MC_HYST_EN_ENABLE _MK_ENUM_CONST(1) +#define DC_DISP_MCCIF_DISPLAY0A_HYST_0_CSR_DISPLAY0A2MC_HYST_EN_DISABLE _MK_ENUM_CONST(0) + + +// Register DC_DISP_MCCIF_DISPLAY0B_HYST_0 +#define DC_DISP_MCCIF_DISPLAY0B_HYST_0 _MK_ADDR_CONST(0x482) +#define DC_DISP_MCCIF_DISPLAY0B_HYST_0_SECURE 0x0 +#define DC_DISP_MCCIF_DISPLAY0B_HYST_0_WORD_COUNT 0x1 +#define DC_DISP_MCCIF_DISPLAY0B_HYST_0_RESET_VAL _MK_MASK_CONST(0xcf401f1f) +#define DC_DISP_MCCIF_DISPLAY0B_HYST_0_RESET_MASK _MK_MASK_CONST(0xffffffff) +#define DC_DISP_MCCIF_DISPLAY0B_HYST_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_MCCIF_DISPLAY0B_HYST_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_MCCIF_DISPLAY0B_HYST_0_READ_MASK _MK_MASK_CONST(0xffffffff) +#define DC_DISP_MCCIF_DISPLAY0B_HYST_0_WRITE_MASK _MK_MASK_CONST(0xffffffff) +#define DC_DISP_MCCIF_DISPLAY0B_HYST_0_CSR_DISPLAY0B2MC_HYST_REQ_TM_SHIFT _MK_SHIFT_CONST(0) +#define DC_DISP_MCCIF_DISPLAY0B_HYST_0_CSR_DISPLAY0B2MC_HYST_REQ_TM_FIELD _MK_FIELD_CONST(0xff, DC_DISP_MCCIF_DISPLAY0B_HYST_0_CSR_DISPLAY0B2MC_HYST_REQ_TM_SHIFT) +#define DC_DISP_MCCIF_DISPLAY0B_HYST_0_CSR_DISPLAY0B2MC_HYST_REQ_TM_RANGE 7:0 +#define DC_DISP_MCCIF_DISPLAY0B_HYST_0_CSR_DISPLAY0B2MC_HYST_REQ_TM_WOFFSET 0x0 +#define DC_DISP_MCCIF_DISPLAY0B_HYST_0_CSR_DISPLAY0B2MC_HYST_REQ_TM_DEFAULT _MK_MASK_CONST(0x1f) +#define DC_DISP_MCCIF_DISPLAY0B_HYST_0_CSR_DISPLAY0B2MC_HYST_REQ_TM_DEFAULT_MASK _MK_MASK_CONST(0xff) +#define DC_DISP_MCCIF_DISPLAY0B_HYST_0_CSR_DISPLAY0B2MC_HYST_REQ_TM_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_MCCIF_DISPLAY0B_HYST_0_CSR_DISPLAY0B2MC_HYST_REQ_TM_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_DISP_MCCIF_DISPLAY0B_HYST_0_CSR_DISPLAY0B2MC_DHYST_TM_SHIFT _MK_SHIFT_CONST(8) +#define DC_DISP_MCCIF_DISPLAY0B_HYST_0_CSR_DISPLAY0B2MC_DHYST_TM_FIELD _MK_FIELD_CONST(0xff, DC_DISP_MCCIF_DISPLAY0B_HYST_0_CSR_DISPLAY0B2MC_DHYST_TM_SHIFT) +#define DC_DISP_MCCIF_DISPLAY0B_HYST_0_CSR_DISPLAY0B2MC_DHYST_TM_RANGE 15:8 +#define DC_DISP_MCCIF_DISPLAY0B_HYST_0_CSR_DISPLAY0B2MC_DHYST_TM_WOFFSET 0x0 +#define DC_DISP_MCCIF_DISPLAY0B_HYST_0_CSR_DISPLAY0B2MC_DHYST_TM_DEFAULT _MK_MASK_CONST(0x1f) +#define DC_DISP_MCCIF_DISPLAY0B_HYST_0_CSR_DISPLAY0B2MC_DHYST_TM_DEFAULT_MASK _MK_MASK_CONST(0xff) +#define DC_DISP_MCCIF_DISPLAY0B_HYST_0_CSR_DISPLAY0B2MC_DHYST_TM_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_MCCIF_DISPLAY0B_HYST_0_CSR_DISPLAY0B2MC_DHYST_TM_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_DISP_MCCIF_DISPLAY0B_HYST_0_CSR_DISPLAY0B2MC_DHYST_TH_SHIFT _MK_SHIFT_CONST(16) +#define DC_DISP_MCCIF_DISPLAY0B_HYST_0_CSR_DISPLAY0B2MC_DHYST_TH_FIELD _MK_FIELD_CONST(0xff, DC_DISP_MCCIF_DISPLAY0B_HYST_0_CSR_DISPLAY0B2MC_DHYST_TH_SHIFT) +#define DC_DISP_MCCIF_DISPLAY0B_HYST_0_CSR_DISPLAY0B2MC_DHYST_TH_RANGE 23:16 +#define DC_DISP_MCCIF_DISPLAY0B_HYST_0_CSR_DISPLAY0B2MC_DHYST_TH_WOFFSET 0x0 +#define DC_DISP_MCCIF_DISPLAY0B_HYST_0_CSR_DISPLAY0B2MC_DHYST_TH_DEFAULT _MK_MASK_CONST(0x40) +#define DC_DISP_MCCIF_DISPLAY0B_HYST_0_CSR_DISPLAY0B2MC_DHYST_TH_DEFAULT_MASK _MK_MASK_CONST(0xff) +#define DC_DISP_MCCIF_DISPLAY0B_HYST_0_CSR_DISPLAY0B2MC_DHYST_TH_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_MCCIF_DISPLAY0B_HYST_0_CSR_DISPLAY0B2MC_DHYST_TH_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_DISP_MCCIF_DISPLAY0B_HYST_0_CSR_DISPLAY0B2MC_HYST_TM_SHIFT _MK_SHIFT_CONST(24) +#define DC_DISP_MCCIF_DISPLAY0B_HYST_0_CSR_DISPLAY0B2MC_HYST_TM_FIELD _MK_FIELD_CONST(0xf, DC_DISP_MCCIF_DISPLAY0B_HYST_0_CSR_DISPLAY0B2MC_HYST_TM_SHIFT) +#define DC_DISP_MCCIF_DISPLAY0B_HYST_0_CSR_DISPLAY0B2MC_HYST_TM_RANGE 27:24 +#define DC_DISP_MCCIF_DISPLAY0B_HYST_0_CSR_DISPLAY0B2MC_HYST_TM_WOFFSET 0x0 +#define DC_DISP_MCCIF_DISPLAY0B_HYST_0_CSR_DISPLAY0B2MC_HYST_TM_DEFAULT _MK_MASK_CONST(0xf) +#define DC_DISP_MCCIF_DISPLAY0B_HYST_0_CSR_DISPLAY0B2MC_HYST_TM_DEFAULT_MASK _MK_MASK_CONST(0xf) +#define DC_DISP_MCCIF_DISPLAY0B_HYST_0_CSR_DISPLAY0B2MC_HYST_TM_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_MCCIF_DISPLAY0B_HYST_0_CSR_DISPLAY0B2MC_HYST_TM_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_DISP_MCCIF_DISPLAY0B_HYST_0_CSR_DISPLAY0B2MC_HYST_REQ_TH_SHIFT _MK_SHIFT_CONST(28) +#define DC_DISP_MCCIF_DISPLAY0B_HYST_0_CSR_DISPLAY0B2MC_HYST_REQ_TH_FIELD _MK_FIELD_CONST(0x7, DC_DISP_MCCIF_DISPLAY0B_HYST_0_CSR_DISPLAY0B2MC_HYST_REQ_TH_SHIFT) +#define DC_DISP_MCCIF_DISPLAY0B_HYST_0_CSR_DISPLAY0B2MC_HYST_REQ_TH_RANGE 30:28 +#define DC_DISP_MCCIF_DISPLAY0B_HYST_0_CSR_DISPLAY0B2MC_HYST_REQ_TH_WOFFSET 0x0 +#define DC_DISP_MCCIF_DISPLAY0B_HYST_0_CSR_DISPLAY0B2MC_HYST_REQ_TH_DEFAULT _MK_MASK_CONST(0x4) +#define DC_DISP_MCCIF_DISPLAY0B_HYST_0_CSR_DISPLAY0B2MC_HYST_REQ_TH_DEFAULT_MASK _MK_MASK_CONST(0x7) +#define DC_DISP_MCCIF_DISPLAY0B_HYST_0_CSR_DISPLAY0B2MC_HYST_REQ_TH_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_MCCIF_DISPLAY0B_HYST_0_CSR_DISPLAY0B2MC_HYST_REQ_TH_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_DISP_MCCIF_DISPLAY0B_HYST_0_CSR_DISPLAY0B2MC_HYST_EN_SHIFT _MK_SHIFT_CONST(31) +#define DC_DISP_MCCIF_DISPLAY0B_HYST_0_CSR_DISPLAY0B2MC_HYST_EN_FIELD _MK_FIELD_CONST(0x1, DC_DISP_MCCIF_DISPLAY0B_HYST_0_CSR_DISPLAY0B2MC_HYST_EN_SHIFT) +#define DC_DISP_MCCIF_DISPLAY0B_HYST_0_CSR_DISPLAY0B2MC_HYST_EN_RANGE 31:31 +#define DC_DISP_MCCIF_DISPLAY0B_HYST_0_CSR_DISPLAY0B2MC_HYST_EN_WOFFSET 0x0 +#define DC_DISP_MCCIF_DISPLAY0B_HYST_0_CSR_DISPLAY0B2MC_HYST_EN_DEFAULT _MK_MASK_CONST(0x1) +#define DC_DISP_MCCIF_DISPLAY0B_HYST_0_CSR_DISPLAY0B2MC_HYST_EN_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_DISP_MCCIF_DISPLAY0B_HYST_0_CSR_DISPLAY0B2MC_HYST_EN_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_MCCIF_DISPLAY0B_HYST_0_CSR_DISPLAY0B2MC_HYST_EN_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_MCCIF_DISPLAY0B_HYST_0_CSR_DISPLAY0B2MC_HYST_EN_INIT_ENUM ENABLE +#define DC_DISP_MCCIF_DISPLAY0B_HYST_0_CSR_DISPLAY0B2MC_HYST_EN_ENABLE _MK_ENUM_CONST(1) +#define DC_DISP_MCCIF_DISPLAY0B_HYST_0_CSR_DISPLAY0B2MC_HYST_EN_DISABLE _MK_ENUM_CONST(0) + + +// Register DC_DISP_MCCIF_DISPLAY0C_HYST_0 +#define DC_DISP_MCCIF_DISPLAY0C_HYST_0 _MK_ADDR_CONST(0x483) +#define DC_DISP_MCCIF_DISPLAY0C_HYST_0_SECURE 0x0 +#define DC_DISP_MCCIF_DISPLAY0C_HYST_0_WORD_COUNT 0x1 +#define DC_DISP_MCCIF_DISPLAY0C_HYST_0_RESET_VAL _MK_MASK_CONST(0xcf401f1f) +#define DC_DISP_MCCIF_DISPLAY0C_HYST_0_RESET_MASK _MK_MASK_CONST(0xffffffff) +#define DC_DISP_MCCIF_DISPLAY0C_HYST_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_MCCIF_DISPLAY0C_HYST_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_MCCIF_DISPLAY0C_HYST_0_READ_MASK _MK_MASK_CONST(0xffffffff) +#define DC_DISP_MCCIF_DISPLAY0C_HYST_0_WRITE_MASK _MK_MASK_CONST(0xffffffff) +#define DC_DISP_MCCIF_DISPLAY0C_HYST_0_CSR_DISPLAY0C2MC_HYST_REQ_TM_SHIFT _MK_SHIFT_CONST(0) +#define DC_DISP_MCCIF_DISPLAY0C_HYST_0_CSR_DISPLAY0C2MC_HYST_REQ_TM_FIELD _MK_FIELD_CONST(0xff, DC_DISP_MCCIF_DISPLAY0C_HYST_0_CSR_DISPLAY0C2MC_HYST_REQ_TM_SHIFT) +#define DC_DISP_MCCIF_DISPLAY0C_HYST_0_CSR_DISPLAY0C2MC_HYST_REQ_TM_RANGE 7:0 +#define DC_DISP_MCCIF_DISPLAY0C_HYST_0_CSR_DISPLAY0C2MC_HYST_REQ_TM_WOFFSET 0x0 +#define DC_DISP_MCCIF_DISPLAY0C_HYST_0_CSR_DISPLAY0C2MC_HYST_REQ_TM_DEFAULT _MK_MASK_CONST(0x1f) +#define DC_DISP_MCCIF_DISPLAY0C_HYST_0_CSR_DISPLAY0C2MC_HYST_REQ_TM_DEFAULT_MASK _MK_MASK_CONST(0xff) +#define DC_DISP_MCCIF_DISPLAY0C_HYST_0_CSR_DISPLAY0C2MC_HYST_REQ_TM_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_MCCIF_DISPLAY0C_HYST_0_CSR_DISPLAY0C2MC_HYST_REQ_TM_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_DISP_MCCIF_DISPLAY0C_HYST_0_CSR_DISPLAY0C2MC_DHYST_TM_SHIFT _MK_SHIFT_CONST(8) +#define DC_DISP_MCCIF_DISPLAY0C_HYST_0_CSR_DISPLAY0C2MC_DHYST_TM_FIELD _MK_FIELD_CONST(0xff, DC_DISP_MCCIF_DISPLAY0C_HYST_0_CSR_DISPLAY0C2MC_DHYST_TM_SHIFT) +#define DC_DISP_MCCIF_DISPLAY0C_HYST_0_CSR_DISPLAY0C2MC_DHYST_TM_RANGE 15:8 +#define DC_DISP_MCCIF_DISPLAY0C_HYST_0_CSR_DISPLAY0C2MC_DHYST_TM_WOFFSET 0x0 +#define DC_DISP_MCCIF_DISPLAY0C_HYST_0_CSR_DISPLAY0C2MC_DHYST_TM_DEFAULT _MK_MASK_CONST(0x1f) +#define DC_DISP_MCCIF_DISPLAY0C_HYST_0_CSR_DISPLAY0C2MC_DHYST_TM_DEFAULT_MASK _MK_MASK_CONST(0xff) +#define DC_DISP_MCCIF_DISPLAY0C_HYST_0_CSR_DISPLAY0C2MC_DHYST_TM_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_MCCIF_DISPLAY0C_HYST_0_CSR_DISPLAY0C2MC_DHYST_TM_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_DISP_MCCIF_DISPLAY0C_HYST_0_CSR_DISPLAY0C2MC_DHYST_TH_SHIFT _MK_SHIFT_CONST(16) +#define DC_DISP_MCCIF_DISPLAY0C_HYST_0_CSR_DISPLAY0C2MC_DHYST_TH_FIELD _MK_FIELD_CONST(0xff, DC_DISP_MCCIF_DISPLAY0C_HYST_0_CSR_DISPLAY0C2MC_DHYST_TH_SHIFT) +#define DC_DISP_MCCIF_DISPLAY0C_HYST_0_CSR_DISPLAY0C2MC_DHYST_TH_RANGE 23:16 +#define DC_DISP_MCCIF_DISPLAY0C_HYST_0_CSR_DISPLAY0C2MC_DHYST_TH_WOFFSET 0x0 +#define DC_DISP_MCCIF_DISPLAY0C_HYST_0_CSR_DISPLAY0C2MC_DHYST_TH_DEFAULT _MK_MASK_CONST(0x40) +#define DC_DISP_MCCIF_DISPLAY0C_HYST_0_CSR_DISPLAY0C2MC_DHYST_TH_DEFAULT_MASK _MK_MASK_CONST(0xff) +#define DC_DISP_MCCIF_DISPLAY0C_HYST_0_CSR_DISPLAY0C2MC_DHYST_TH_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_MCCIF_DISPLAY0C_HYST_0_CSR_DISPLAY0C2MC_DHYST_TH_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_DISP_MCCIF_DISPLAY0C_HYST_0_CSR_DISPLAY0C2MC_HYST_TM_SHIFT _MK_SHIFT_CONST(24) +#define DC_DISP_MCCIF_DISPLAY0C_HYST_0_CSR_DISPLAY0C2MC_HYST_TM_FIELD _MK_FIELD_CONST(0xf, DC_DISP_MCCIF_DISPLAY0C_HYST_0_CSR_DISPLAY0C2MC_HYST_TM_SHIFT) +#define DC_DISP_MCCIF_DISPLAY0C_HYST_0_CSR_DISPLAY0C2MC_HYST_TM_RANGE 27:24 +#define DC_DISP_MCCIF_DISPLAY0C_HYST_0_CSR_DISPLAY0C2MC_HYST_TM_WOFFSET 0x0 +#define DC_DISP_MCCIF_DISPLAY0C_HYST_0_CSR_DISPLAY0C2MC_HYST_TM_DEFAULT _MK_MASK_CONST(0xf) +#define DC_DISP_MCCIF_DISPLAY0C_HYST_0_CSR_DISPLAY0C2MC_HYST_TM_DEFAULT_MASK _MK_MASK_CONST(0xf) +#define DC_DISP_MCCIF_DISPLAY0C_HYST_0_CSR_DISPLAY0C2MC_HYST_TM_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_MCCIF_DISPLAY0C_HYST_0_CSR_DISPLAY0C2MC_HYST_TM_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_DISP_MCCIF_DISPLAY0C_HYST_0_CSR_DISPLAY0C2MC_HYST_REQ_TH_SHIFT _MK_SHIFT_CONST(28) +#define DC_DISP_MCCIF_DISPLAY0C_HYST_0_CSR_DISPLAY0C2MC_HYST_REQ_TH_FIELD _MK_FIELD_CONST(0x7, DC_DISP_MCCIF_DISPLAY0C_HYST_0_CSR_DISPLAY0C2MC_HYST_REQ_TH_SHIFT) +#define DC_DISP_MCCIF_DISPLAY0C_HYST_0_CSR_DISPLAY0C2MC_HYST_REQ_TH_RANGE 30:28 +#define DC_DISP_MCCIF_DISPLAY0C_HYST_0_CSR_DISPLAY0C2MC_HYST_REQ_TH_WOFFSET 0x0 +#define DC_DISP_MCCIF_DISPLAY0C_HYST_0_CSR_DISPLAY0C2MC_HYST_REQ_TH_DEFAULT _MK_MASK_CONST(0x4) +#define DC_DISP_MCCIF_DISPLAY0C_HYST_0_CSR_DISPLAY0C2MC_HYST_REQ_TH_DEFAULT_MASK _MK_MASK_CONST(0x7) +#define DC_DISP_MCCIF_DISPLAY0C_HYST_0_CSR_DISPLAY0C2MC_HYST_REQ_TH_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_MCCIF_DISPLAY0C_HYST_0_CSR_DISPLAY0C2MC_HYST_REQ_TH_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_DISP_MCCIF_DISPLAY0C_HYST_0_CSR_DISPLAY0C2MC_HYST_EN_SHIFT _MK_SHIFT_CONST(31) +#define DC_DISP_MCCIF_DISPLAY0C_HYST_0_CSR_DISPLAY0C2MC_HYST_EN_FIELD _MK_FIELD_CONST(0x1, DC_DISP_MCCIF_DISPLAY0C_HYST_0_CSR_DISPLAY0C2MC_HYST_EN_SHIFT) +#define DC_DISP_MCCIF_DISPLAY0C_HYST_0_CSR_DISPLAY0C2MC_HYST_EN_RANGE 31:31 +#define DC_DISP_MCCIF_DISPLAY0C_HYST_0_CSR_DISPLAY0C2MC_HYST_EN_WOFFSET 0x0 +#define DC_DISP_MCCIF_DISPLAY0C_HYST_0_CSR_DISPLAY0C2MC_HYST_EN_DEFAULT _MK_MASK_CONST(0x1) +#define DC_DISP_MCCIF_DISPLAY0C_HYST_0_CSR_DISPLAY0C2MC_HYST_EN_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_DISP_MCCIF_DISPLAY0C_HYST_0_CSR_DISPLAY0C2MC_HYST_EN_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_MCCIF_DISPLAY0C_HYST_0_CSR_DISPLAY0C2MC_HYST_EN_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_MCCIF_DISPLAY0C_HYST_0_CSR_DISPLAY0C2MC_HYST_EN_INIT_ENUM ENABLE +#define DC_DISP_MCCIF_DISPLAY0C_HYST_0_CSR_DISPLAY0C2MC_HYST_EN_ENABLE _MK_ENUM_CONST(1) +#define DC_DISP_MCCIF_DISPLAY0C_HYST_0_CSR_DISPLAY0C2MC_HYST_EN_DISABLE _MK_ENUM_CONST(0) + + +// Reserved address 1216 [0x4c0] + +// Register DC_DISP_DISP_MISC_CONTROL_0 +#define DC_DISP_DISP_MISC_CONTROL_0 _MK_ADDR_CONST(0x4c1) +#define DC_DISP_DISP_MISC_CONTROL_0_SECURE 0x0 +#define DC_DISP_DISP_MISC_CONTROL_0_WORD_COUNT 0x1 +#define DC_DISP_DISP_MISC_CONTROL_0_RESET_VAL _MK_MASK_CONST(0x2) +#define DC_DISP_DISP_MISC_CONTROL_0_RESET_MASK _MK_MASK_CONST(0x3) +#define DC_DISP_DISP_MISC_CONTROL_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_DISP_MISC_CONTROL_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_DISP_MISC_CONTROL_0_READ_MASK _MK_MASK_CONST(0x3) +#define DC_DISP_DISP_MISC_CONTROL_0_WRITE_MASK _MK_MASK_CONST(0x3) +#define DC_DISP_DISP_MISC_CONTROL_0_PHASE_SHIFT_2P1C18B_SHIFT _MK_SHIFT_CONST(0) +#define DC_DISP_DISP_MISC_CONTROL_0_PHASE_SHIFT_2P1C18B_FIELD _MK_FIELD_CONST(0x1, DC_DISP_DISP_MISC_CONTROL_0_PHASE_SHIFT_2P1C18B_SHIFT) +#define DC_DISP_DISP_MISC_CONTROL_0_PHASE_SHIFT_2P1C18B_RANGE 0:0 +#define DC_DISP_DISP_MISC_CONTROL_0_PHASE_SHIFT_2P1C18B_WOFFSET 0x0 +#define DC_DISP_DISP_MISC_CONTROL_0_PHASE_SHIFT_2P1C18B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_DISP_MISC_CONTROL_0_PHASE_SHIFT_2P1C18B_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_DISP_DISP_MISC_CONTROL_0_PHASE_SHIFT_2P1C18B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_DISP_MISC_CONTROL_0_PHASE_SHIFT_2P1C18B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_DISP_MISC_CONTROL_0_PHASE_SHIFT_2P1C18B_DISABLE _MK_ENUM_CONST(0) +#define DC_DISP_DISP_MISC_CONTROL_0_PHASE_SHIFT_2P1C18B_ENABLE _MK_ENUM_CONST(1) + +#define DC_DISP_DISP_MISC_CONTROL_0_UF_LINE_FLUSH_SHIFT _MK_SHIFT_CONST(1) +#define DC_DISP_DISP_MISC_CONTROL_0_UF_LINE_FLUSH_FIELD _MK_FIELD_CONST(0x1, DC_DISP_DISP_MISC_CONTROL_0_UF_LINE_FLUSH_SHIFT) +#define DC_DISP_DISP_MISC_CONTROL_0_UF_LINE_FLUSH_RANGE 1:1 +#define DC_DISP_DISP_MISC_CONTROL_0_UF_LINE_FLUSH_WOFFSET 0x0 +#define DC_DISP_DISP_MISC_CONTROL_0_UF_LINE_FLUSH_DEFAULT _MK_MASK_CONST(0x1) +#define DC_DISP_DISP_MISC_CONTROL_0_UF_LINE_FLUSH_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_DISP_DISP_MISC_CONTROL_0_UF_LINE_FLUSH_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_DISP_MISC_CONTROL_0_UF_LINE_FLUSH_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_DISP_MISC_CONTROL_0_UF_LINE_FLUSH_DISABLE _MK_ENUM_CONST(0) +#define DC_DISP_DISP_MISC_CONTROL_0_UF_LINE_FLUSH_ENABLE _MK_ENUM_CONST(1) + + +// Packet SD_PIXEL +#define SD_PIXEL_SIZE 24 + +#define SD_PIXEL_RED_SHIFT _MK_SHIFT_CONST(0) +#define SD_PIXEL_RED_FIELD _MK_FIELD_CONST(0xff, SD_PIXEL_RED_SHIFT) +#define SD_PIXEL_RED_RANGE _MK_SHIFT_CONST(7):_MK_SHIFT_CONST(0) +#define SD_PIXEL_RED_ROW 0 + +#define SD_PIXEL_GRN_SHIFT _MK_SHIFT_CONST(8) +#define SD_PIXEL_GRN_FIELD _MK_FIELD_CONST(0xff, SD_PIXEL_GRN_SHIFT) +#define SD_PIXEL_GRN_RANGE _MK_SHIFT_CONST(15):_MK_SHIFT_CONST(8) +#define SD_PIXEL_GRN_ROW 0 + +#define SD_PIXEL_BLU_SHIFT _MK_SHIFT_CONST(16) +#define SD_PIXEL_BLU_FIELD _MK_FIELD_CONST(0xff, SD_PIXEL_BLU_SHIFT) +#define SD_PIXEL_BLU_RANGE _MK_SHIFT_CONST(23):_MK_SHIFT_CONST(16) +#define SD_PIXEL_BLU_ROW 0 + + +// Register DC_DISP_SD_CONTROL_0 +#define DC_DISP_SD_CONTROL_0 _MK_ADDR_CONST(0x4c2) +#define DC_DISP_SD_CONTROL_0_SECURE 0x0 +#define DC_DISP_SD_CONTROL_0_WORD_COUNT 0x1 +#define DC_DISP_SD_CONTROL_0_RESET_VAL _MK_MASK_CONST(0x4000) +#define DC_DISP_SD_CONTROL_0_RESET_MASK _MK_MASK_CONST(0x7000ffff) +#define DC_DISP_SD_CONTROL_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_SD_CONTROL_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_SD_CONTROL_0_READ_MASK _MK_MASK_CONST(0x7000ffff) +#define DC_DISP_SD_CONTROL_0_WRITE_MASK _MK_MASK_CONST(0x7000ffff) +#define DC_DISP_SD_CONTROL_0_SD_ENABLE_SHIFT _MK_SHIFT_CONST(0) +#define DC_DISP_SD_CONTROL_0_SD_ENABLE_FIELD _MK_FIELD_CONST(0x3, DC_DISP_SD_CONTROL_0_SD_ENABLE_SHIFT) +#define DC_DISP_SD_CONTROL_0_SD_ENABLE_RANGE 1:0 +#define DC_DISP_SD_CONTROL_0_SD_ENABLE_WOFFSET 0x0 +#define DC_DISP_SD_CONTROL_0_SD_ENABLE_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_CONTROL_0_SD_ENABLE_DEFAULT_MASK _MK_MASK_CONST(0x3) +#define DC_DISP_SD_CONTROL_0_SD_ENABLE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_CONTROL_0_SD_ENABLE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_SD_CONTROL_0_SD_ENABLE_DISABLE _MK_ENUM_CONST(0) +#define DC_DISP_SD_CONTROL_0_SD_ENABLE_ENABLE _MK_ENUM_CONST(1) +#define DC_DISP_SD_CONTROL_0_SD_ENABLE_ONE_SHOT _MK_ENUM_CONST(2) + +#define DC_DISP_SD_CONTROL_0_USE_VID_LUMA_SHIFT _MK_SHIFT_CONST(2) +#define DC_DISP_SD_CONTROL_0_USE_VID_LUMA_FIELD _MK_FIELD_CONST(0x1, DC_DISP_SD_CONTROL_0_USE_VID_LUMA_SHIFT) +#define DC_DISP_SD_CONTROL_0_USE_VID_LUMA_RANGE 2:2 +#define DC_DISP_SD_CONTROL_0_USE_VID_LUMA_WOFFSET 0x0 +#define DC_DISP_SD_CONTROL_0_USE_VID_LUMA_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_CONTROL_0_USE_VID_LUMA_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_DISP_SD_CONTROL_0_USE_VID_LUMA_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_CONTROL_0_USE_VID_LUMA_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_SD_CONTROL_0_USE_VID_LUMA_DISABLE _MK_ENUM_CONST(0) +#define DC_DISP_SD_CONTROL_0_USE_VID_LUMA_ENABLE _MK_ENUM_CONST(1) + +#define DC_DISP_SD_CONTROL_0_BIN_WIDTH_SHIFT _MK_SHIFT_CONST(3) +#define DC_DISP_SD_CONTROL_0_BIN_WIDTH_FIELD _MK_FIELD_CONST(0x3, DC_DISP_SD_CONTROL_0_BIN_WIDTH_SHIFT) +#define DC_DISP_SD_CONTROL_0_BIN_WIDTH_RANGE 4:3 +#define DC_DISP_SD_CONTROL_0_BIN_WIDTH_WOFFSET 0x0 +#define DC_DISP_SD_CONTROL_0_BIN_WIDTH_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_CONTROL_0_BIN_WIDTH_DEFAULT_MASK _MK_MASK_CONST(0x3) +#define DC_DISP_SD_CONTROL_0_BIN_WIDTH_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_CONTROL_0_BIN_WIDTH_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_SD_CONTROL_0_BIN_WIDTH_ONE _MK_ENUM_CONST(0) +#define DC_DISP_SD_CONTROL_0_BIN_WIDTH_TWO _MK_ENUM_CONST(1) +#define DC_DISP_SD_CONTROL_0_BIN_WIDTH_FOUR _MK_ENUM_CONST(2) +#define DC_DISP_SD_CONTROL_0_BIN_WIDTH_EIGHT _MK_ENUM_CONST(3) + +#define DC_DISP_SD_CONTROL_0_AGGRESSIVENESS_SHIFT _MK_SHIFT_CONST(5) +#define DC_DISP_SD_CONTROL_0_AGGRESSIVENESS_FIELD _MK_FIELD_CONST(0x7, DC_DISP_SD_CONTROL_0_AGGRESSIVENESS_SHIFT) +#define DC_DISP_SD_CONTROL_0_AGGRESSIVENESS_RANGE 7:5 +#define DC_DISP_SD_CONTROL_0_AGGRESSIVENESS_WOFFSET 0x0 +#define DC_DISP_SD_CONTROL_0_AGGRESSIVENESS_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_CONTROL_0_AGGRESSIVENESS_DEFAULT_MASK _MK_MASK_CONST(0x7) +#define DC_DISP_SD_CONTROL_0_AGGRESSIVENESS_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_CONTROL_0_AGGRESSIVENESS_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_DISP_SD_CONTROL_0_HW_UPDATE_DLY_SHIFT _MK_SHIFT_CONST(8) +#define DC_DISP_SD_CONTROL_0_HW_UPDATE_DLY_FIELD _MK_FIELD_CONST(0x3, DC_DISP_SD_CONTROL_0_HW_UPDATE_DLY_SHIFT) +#define DC_DISP_SD_CONTROL_0_HW_UPDATE_DLY_RANGE 9:8 +#define DC_DISP_SD_CONTROL_0_HW_UPDATE_DLY_WOFFSET 0x0 +#define DC_DISP_SD_CONTROL_0_HW_UPDATE_DLY_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_CONTROL_0_HW_UPDATE_DLY_DEFAULT_MASK _MK_MASK_CONST(0x3) +#define DC_DISP_SD_CONTROL_0_HW_UPDATE_DLY_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_CONTROL_0_HW_UPDATE_DLY_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_DISP_SD_CONTROL_0_SD_ONE_SHOT_SHIFT _MK_SHIFT_CONST(10) +#define DC_DISP_SD_CONTROL_0_SD_ONE_SHOT_FIELD _MK_FIELD_CONST(0x1, DC_DISP_SD_CONTROL_0_SD_ONE_SHOT_SHIFT) +#define DC_DISP_SD_CONTROL_0_SD_ONE_SHOT_RANGE 10:10 +#define DC_DISP_SD_CONTROL_0_SD_ONE_SHOT_WOFFSET 0x0 +#define DC_DISP_SD_CONTROL_0_SD_ONE_SHOT_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_CONTROL_0_SD_ONE_SHOT_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_DISP_SD_CONTROL_0_SD_ONE_SHOT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_CONTROL_0_SD_ONE_SHOT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_SD_CONTROL_0_SD_ONE_SHOT_DISABLE _MK_ENUM_CONST(0) +#define DC_DISP_SD_CONTROL_0_SD_ONE_SHOT_ENABLE _MK_ENUM_CONST(1) + +#define DC_DISP_SD_CONTROL_0_SD_CORRECTION_MODE_SHIFT _MK_SHIFT_CONST(11) +#define DC_DISP_SD_CONTROL_0_SD_CORRECTION_MODE_FIELD _MK_FIELD_CONST(0x1, DC_DISP_SD_CONTROL_0_SD_CORRECTION_MODE_SHIFT) +#define DC_DISP_SD_CONTROL_0_SD_CORRECTION_MODE_RANGE 11:11 +#define DC_DISP_SD_CONTROL_0_SD_CORRECTION_MODE_WOFFSET 0x0 +#define DC_DISP_SD_CONTROL_0_SD_CORRECTION_MODE_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_CONTROL_0_SD_CORRECTION_MODE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_DISP_SD_CONTROL_0_SD_CORRECTION_MODE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_CONTROL_0_SD_CORRECTION_MODE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_SD_CONTROL_0_SD_CORRECTION_MODE_AUTO_CORRECT _MK_ENUM_CONST(0) +#define DC_DISP_SD_CONTROL_0_SD_CORRECTION_MODE_MANUAL _MK_ENUM_CONST(1) + +#define DC_DISP_SD_CONTROL_0_K_LIMIT_ENABLE_SHIFT _MK_SHIFT_CONST(12) +#define DC_DISP_SD_CONTROL_0_K_LIMIT_ENABLE_FIELD _MK_FIELD_CONST(0x1, DC_DISP_SD_CONTROL_0_K_LIMIT_ENABLE_SHIFT) +#define DC_DISP_SD_CONTROL_0_K_LIMIT_ENABLE_RANGE 12:12 +#define DC_DISP_SD_CONTROL_0_K_LIMIT_ENABLE_WOFFSET 0x0 +#define DC_DISP_SD_CONTROL_0_K_LIMIT_ENABLE_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_CONTROL_0_K_LIMIT_ENABLE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_DISP_SD_CONTROL_0_K_LIMIT_ENABLE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_CONTROL_0_K_LIMIT_ENABLE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_SD_CONTROL_0_K_LIMIT_ENABLE_INIT_ENUM DISABLE +#define DC_DISP_SD_CONTROL_0_K_LIMIT_ENABLE_DISABLE _MK_ENUM_CONST(0) +#define DC_DISP_SD_CONTROL_0_K_LIMIT_ENABLE_ENABLE _MK_ENUM_CONST(1) + +#define DC_DISP_SD_CONTROL_0_SD_WINDOW_ENABLE_SHIFT _MK_SHIFT_CONST(13) +#define DC_DISP_SD_CONTROL_0_SD_WINDOW_ENABLE_FIELD _MK_FIELD_CONST(0x1, DC_DISP_SD_CONTROL_0_SD_WINDOW_ENABLE_SHIFT) +#define DC_DISP_SD_CONTROL_0_SD_WINDOW_ENABLE_RANGE 13:13 +#define DC_DISP_SD_CONTROL_0_SD_WINDOW_ENABLE_WOFFSET 0x0 +#define DC_DISP_SD_CONTROL_0_SD_WINDOW_ENABLE_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_CONTROL_0_SD_WINDOW_ENABLE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_DISP_SD_CONTROL_0_SD_WINDOW_ENABLE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_CONTROL_0_SD_WINDOW_ENABLE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_SD_CONTROL_0_SD_WINDOW_ENABLE_INIT_ENUM DISABLE +#define DC_DISP_SD_CONTROL_0_SD_WINDOW_ENABLE_DISABLE _MK_ENUM_CONST(0) +#define DC_DISP_SD_CONTROL_0_SD_WINDOW_ENABLE_ENABLE _MK_ENUM_CONST(1) + +#define DC_DISP_SD_CONTROL_0_SOFT_CLIPPING_ENABLE_SHIFT _MK_SHIFT_CONST(14) +#define DC_DISP_SD_CONTROL_0_SOFT_CLIPPING_ENABLE_FIELD _MK_FIELD_CONST(0x1, DC_DISP_SD_CONTROL_0_SOFT_CLIPPING_ENABLE_SHIFT) +#define DC_DISP_SD_CONTROL_0_SOFT_CLIPPING_ENABLE_RANGE 14:14 +#define DC_DISP_SD_CONTROL_0_SOFT_CLIPPING_ENABLE_WOFFSET 0x0 +#define DC_DISP_SD_CONTROL_0_SOFT_CLIPPING_ENABLE_DEFAULT _MK_MASK_CONST(0x1) +#define DC_DISP_SD_CONTROL_0_SOFT_CLIPPING_ENABLE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_DISP_SD_CONTROL_0_SOFT_CLIPPING_ENABLE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_CONTROL_0_SOFT_CLIPPING_ENABLE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_SD_CONTROL_0_SOFT_CLIPPING_ENABLE_INIT_ENUM ENABLE +#define DC_DISP_SD_CONTROL_0_SOFT_CLIPPING_ENABLE_DISABLE _MK_ENUM_CONST(0) +#define DC_DISP_SD_CONTROL_0_SOFT_CLIPPING_ENABLE_ENABLE _MK_ENUM_CONST(1) + +#define DC_DISP_SD_CONTROL_0_SMOOTH_K_ENABLE_SHIFT _MK_SHIFT_CONST(15) +#define DC_DISP_SD_CONTROL_0_SMOOTH_K_ENABLE_FIELD _MK_FIELD_CONST(0x1, DC_DISP_SD_CONTROL_0_SMOOTH_K_ENABLE_SHIFT) +#define DC_DISP_SD_CONTROL_0_SMOOTH_K_ENABLE_RANGE 15:15 +#define DC_DISP_SD_CONTROL_0_SMOOTH_K_ENABLE_WOFFSET 0x0 +#define DC_DISP_SD_CONTROL_0_SMOOTH_K_ENABLE_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_CONTROL_0_SMOOTH_K_ENABLE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_DISP_SD_CONTROL_0_SMOOTH_K_ENABLE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_CONTROL_0_SMOOTH_K_ENABLE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_SD_CONTROL_0_SMOOTH_K_ENABLE_INIT_ENUM DISABLE +#define DC_DISP_SD_CONTROL_0_SMOOTH_K_ENABLE_DISABLE _MK_ENUM_CONST(0) +#define DC_DISP_SD_CONTROL_0_SMOOTH_K_ENABLE_ENABLE _MK_ENUM_CONST(1) + +#define DC_DISP_SD_CONTROL_0_SD_FRAME_PROC_CONTROL_SHIFT _MK_SHIFT_CONST(28) +#define DC_DISP_SD_CONTROL_0_SD_FRAME_PROC_CONTROL_FIELD _MK_FIELD_CONST(0x1, DC_DISP_SD_CONTROL_0_SD_FRAME_PROC_CONTROL_SHIFT) +#define DC_DISP_SD_CONTROL_0_SD_FRAME_PROC_CONTROL_RANGE 28:28 +#define DC_DISP_SD_CONTROL_0_SD_FRAME_PROC_CONTROL_WOFFSET 0x0 +#define DC_DISP_SD_CONTROL_0_SD_FRAME_PROC_CONTROL_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_CONTROL_0_SD_FRAME_PROC_CONTROL_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_DISP_SD_CONTROL_0_SD_FRAME_PROC_CONTROL_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_CONTROL_0_SD_FRAME_PROC_CONTROL_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_SD_CONTROL_0_SD_FRAME_PROC_CONTROL_INIT_ENUM VSYNC +#define DC_DISP_SD_CONTROL_0_SD_FRAME_PROC_CONTROL_VSYNC _MK_ENUM_CONST(0) +#define DC_DISP_SD_CONTROL_0_SD_FRAME_PROC_CONTROL_VPULSE2 _MK_ENUM_CONST(1) + +#define DC_DISP_SD_CONTROL_0_K_INIT_BIAS_SHIFT _MK_SHIFT_CONST(29) +#define DC_DISP_SD_CONTROL_0_K_INIT_BIAS_FIELD _MK_FIELD_CONST(0x3, DC_DISP_SD_CONTROL_0_K_INIT_BIAS_SHIFT) +#define DC_DISP_SD_CONTROL_0_K_INIT_BIAS_RANGE 30:29 +#define DC_DISP_SD_CONTROL_0_K_INIT_BIAS_WOFFSET 0x0 +#define DC_DISP_SD_CONTROL_0_K_INIT_BIAS_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_CONTROL_0_K_INIT_BIAS_DEFAULT_MASK _MK_MASK_CONST(0x3) +#define DC_DISP_SD_CONTROL_0_K_INIT_BIAS_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_CONTROL_0_K_INIT_BIAS_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_SD_CONTROL_0_K_INIT_BIAS_INIT_ENUM BIAS0 +#define DC_DISP_SD_CONTROL_0_K_INIT_BIAS_BIAS0 _MK_ENUM_CONST(0) +#define DC_DISP_SD_CONTROL_0_K_INIT_BIAS_BIAS1 _MK_ENUM_CONST(1) +#define DC_DISP_SD_CONTROL_0_K_INIT_BIAS_BIAS_HALF _MK_ENUM_CONST(2) +#define DC_DISP_SD_CONTROL_0_K_INIT_BIAS_BIAS_MSB _MK_ENUM_CONST(3) + + +// Register DC_DISP_SD_CSC_COEFF_0 +#define DC_DISP_SD_CSC_COEFF_0 _MK_ADDR_CONST(0x4c3) +#define DC_DISP_SD_CSC_COEFF_0_SECURE 0x0 +#define DC_DISP_SD_CSC_COEFF_0_WORD_COUNT 0x1 +#define DC_DISP_SD_CSC_COEFF_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_SD_CSC_COEFF_0_RESET_MASK _MK_MASK_CONST(0xf0f0f0) +#define DC_DISP_SD_CSC_COEFF_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_SD_CSC_COEFF_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_SD_CSC_COEFF_0_READ_MASK _MK_MASK_CONST(0xf0f0f0) +#define DC_DISP_SD_CSC_COEFF_0_WRITE_MASK _MK_MASK_CONST(0xf0f0f0) +#define DC_DISP_SD_CSC_COEFF_0_R_COEFF_SHIFT _MK_SHIFT_CONST(4) +#define DC_DISP_SD_CSC_COEFF_0_R_COEFF_FIELD _MK_FIELD_CONST(0xf, DC_DISP_SD_CSC_COEFF_0_R_COEFF_SHIFT) +#define DC_DISP_SD_CSC_COEFF_0_R_COEFF_RANGE 7:4 +#define DC_DISP_SD_CSC_COEFF_0_R_COEFF_WOFFSET 0x0 +#define DC_DISP_SD_CSC_COEFF_0_R_COEFF_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_CSC_COEFF_0_R_COEFF_DEFAULT_MASK _MK_MASK_CONST(0xf) +#define DC_DISP_SD_CSC_COEFF_0_R_COEFF_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_CSC_COEFF_0_R_COEFF_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_DISP_SD_CSC_COEFF_0_G_COEFF_SHIFT _MK_SHIFT_CONST(12) +#define DC_DISP_SD_CSC_COEFF_0_G_COEFF_FIELD _MK_FIELD_CONST(0xf, DC_DISP_SD_CSC_COEFF_0_G_COEFF_SHIFT) +#define DC_DISP_SD_CSC_COEFF_0_G_COEFF_RANGE 15:12 +#define DC_DISP_SD_CSC_COEFF_0_G_COEFF_WOFFSET 0x0 +#define DC_DISP_SD_CSC_COEFF_0_G_COEFF_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_CSC_COEFF_0_G_COEFF_DEFAULT_MASK _MK_MASK_CONST(0xf) +#define DC_DISP_SD_CSC_COEFF_0_G_COEFF_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_CSC_COEFF_0_G_COEFF_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_DISP_SD_CSC_COEFF_0_B_COEFF_SHIFT _MK_SHIFT_CONST(20) +#define DC_DISP_SD_CSC_COEFF_0_B_COEFF_FIELD _MK_FIELD_CONST(0xf, DC_DISP_SD_CSC_COEFF_0_B_COEFF_SHIFT) +#define DC_DISP_SD_CSC_COEFF_0_B_COEFF_RANGE 23:20 +#define DC_DISP_SD_CSC_COEFF_0_B_COEFF_WOFFSET 0x0 +#define DC_DISP_SD_CSC_COEFF_0_B_COEFF_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_CSC_COEFF_0_B_COEFF_DEFAULT_MASK _MK_MASK_CONST(0xf) +#define DC_DISP_SD_CSC_COEFF_0_B_COEFF_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_CSC_COEFF_0_B_COEFF_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_DISP_SD_LUT_0 +#define DC_DISP_SD_LUT_0 _MK_ADDR_CONST(0x4c4) +#define DC_DISP_SD_LUT_0_SECURE 0x0 +#define DC_DISP_SD_LUT_0_WORD_COUNT 0x1 +#define DC_DISP_SD_LUT_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_SD_LUT_0_RESET_MASK _MK_MASK_CONST(0xffffff) +#define DC_DISP_SD_LUT_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_SD_LUT_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_SD_LUT_0_READ_MASK _MK_MASK_CONST(0xffffff) +#define DC_DISP_SD_LUT_0_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_DISP_SD_LUT_0_R_LUT_SHIFT _MK_SHIFT_CONST(0) +#define DC_DISP_SD_LUT_0_R_LUT_FIELD _MK_FIELD_CONST(0xff, DC_DISP_SD_LUT_0_R_LUT_SHIFT) +#define DC_DISP_SD_LUT_0_R_LUT_RANGE 7:0 +#define DC_DISP_SD_LUT_0_R_LUT_WOFFSET 0x0 +#define DC_DISP_SD_LUT_0_R_LUT_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_LUT_0_R_LUT_DEFAULT_MASK _MK_MASK_CONST(0xff) +#define DC_DISP_SD_LUT_0_R_LUT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_LUT_0_R_LUT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_DISP_SD_LUT_0_G_LUT_SHIFT _MK_SHIFT_CONST(8) +#define DC_DISP_SD_LUT_0_G_LUT_FIELD _MK_FIELD_CONST(0xff, DC_DISP_SD_LUT_0_G_LUT_SHIFT) +#define DC_DISP_SD_LUT_0_G_LUT_RANGE 15:8 +#define DC_DISP_SD_LUT_0_G_LUT_WOFFSET 0x0 +#define DC_DISP_SD_LUT_0_G_LUT_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_LUT_0_G_LUT_DEFAULT_MASK _MK_MASK_CONST(0xff) +#define DC_DISP_SD_LUT_0_G_LUT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_LUT_0_G_LUT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_DISP_SD_LUT_0_B_LUT_SHIFT _MK_SHIFT_CONST(16) +#define DC_DISP_SD_LUT_0_B_LUT_FIELD _MK_FIELD_CONST(0xff, DC_DISP_SD_LUT_0_B_LUT_SHIFT) +#define DC_DISP_SD_LUT_0_B_LUT_RANGE 23:16 +#define DC_DISP_SD_LUT_0_B_LUT_WOFFSET 0x0 +#define DC_DISP_SD_LUT_0_B_LUT_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_LUT_0_B_LUT_DEFAULT_MASK _MK_MASK_CONST(0xff) +#define DC_DISP_SD_LUT_0_B_LUT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_LUT_0_B_LUT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_DISP_SD_LUT +#define DC_DISP_SD_LUT _MK_ADDR_CONST(0x4c4) +#define DC_DISP_SD_LUT_SECURE 0x0 +#define DC_DISP_SD_LUT_WORD_COUNT 0x1 +#define DC_DISP_SD_LUT_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_SD_LUT_RESET_MASK _MK_MASK_CONST(0xffffff) +#define DC_DISP_SD_LUT_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_SD_LUT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_SD_LUT_READ_MASK _MK_MASK_CONST(0xffffff) +#define DC_DISP_SD_LUT_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_DISP_SD_LUT_R_LUT_SHIFT _MK_SHIFT_CONST(0) +#define DC_DISP_SD_LUT_R_LUT_FIELD _MK_FIELD_CONST(0xff, DC_DISP_SD_LUT_R_LUT_SHIFT) +#define DC_DISP_SD_LUT_R_LUT_RANGE 7:0 +#define DC_DISP_SD_LUT_R_LUT_WOFFSET 0x0 +#define DC_DISP_SD_LUT_R_LUT_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_LUT_R_LUT_DEFAULT_MASK _MK_MASK_CONST(0xff) +#define DC_DISP_SD_LUT_R_LUT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_LUT_R_LUT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_DISP_SD_LUT_G_LUT_SHIFT _MK_SHIFT_CONST(8) +#define DC_DISP_SD_LUT_G_LUT_FIELD _MK_FIELD_CONST(0xff, DC_DISP_SD_LUT_G_LUT_SHIFT) +#define DC_DISP_SD_LUT_G_LUT_RANGE 15:8 +#define DC_DISP_SD_LUT_G_LUT_WOFFSET 0x0 +#define DC_DISP_SD_LUT_G_LUT_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_LUT_G_LUT_DEFAULT_MASK _MK_MASK_CONST(0xff) +#define DC_DISP_SD_LUT_G_LUT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_LUT_G_LUT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_DISP_SD_LUT_B_LUT_SHIFT _MK_SHIFT_CONST(16) +#define DC_DISP_SD_LUT_B_LUT_FIELD _MK_FIELD_CONST(0xff, DC_DISP_SD_LUT_B_LUT_SHIFT) +#define DC_DISP_SD_LUT_B_LUT_RANGE 23:16 +#define DC_DISP_SD_LUT_B_LUT_WOFFSET 0x0 +#define DC_DISP_SD_LUT_B_LUT_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_LUT_B_LUT_DEFAULT_MASK _MK_MASK_CONST(0xff) +#define DC_DISP_SD_LUT_B_LUT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_LUT_B_LUT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_DISP_SD_LUT_1 +#define DC_DISP_SD_LUT_1 _MK_ADDR_CONST(0x4c5) +#define DC_DISP_SD_LUT_1_SECURE 0x0 +#define DC_DISP_SD_LUT_1_WORD_COUNT 0x1 +#define DC_DISP_SD_LUT_1_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_SD_LUT_1_RESET_MASK _MK_MASK_CONST(0xffffff) +#define DC_DISP_SD_LUT_1_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_SD_LUT_1_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_SD_LUT_1_READ_MASK _MK_MASK_CONST(0xffffff) +#define DC_DISP_SD_LUT_1_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_DISP_SD_LUT_1_R_LUT_SHIFT _MK_SHIFT_CONST(0) +#define DC_DISP_SD_LUT_1_R_LUT_FIELD _MK_FIELD_CONST(0xff, DC_DISP_SD_LUT_1_R_LUT_SHIFT) +#define DC_DISP_SD_LUT_1_R_LUT_RANGE 7:0 +#define DC_DISP_SD_LUT_1_R_LUT_WOFFSET 0x0 +#define DC_DISP_SD_LUT_1_R_LUT_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_LUT_1_R_LUT_DEFAULT_MASK _MK_MASK_CONST(0xff) +#define DC_DISP_SD_LUT_1_R_LUT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_LUT_1_R_LUT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_DISP_SD_LUT_1_G_LUT_SHIFT _MK_SHIFT_CONST(8) +#define DC_DISP_SD_LUT_1_G_LUT_FIELD _MK_FIELD_CONST(0xff, DC_DISP_SD_LUT_1_G_LUT_SHIFT) +#define DC_DISP_SD_LUT_1_G_LUT_RANGE 15:8 +#define DC_DISP_SD_LUT_1_G_LUT_WOFFSET 0x0 +#define DC_DISP_SD_LUT_1_G_LUT_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_LUT_1_G_LUT_DEFAULT_MASK _MK_MASK_CONST(0xff) +#define DC_DISP_SD_LUT_1_G_LUT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_LUT_1_G_LUT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_DISP_SD_LUT_1_B_LUT_SHIFT _MK_SHIFT_CONST(16) +#define DC_DISP_SD_LUT_1_B_LUT_FIELD _MK_FIELD_CONST(0xff, DC_DISP_SD_LUT_1_B_LUT_SHIFT) +#define DC_DISP_SD_LUT_1_B_LUT_RANGE 23:16 +#define DC_DISP_SD_LUT_1_B_LUT_WOFFSET 0x0 +#define DC_DISP_SD_LUT_1_B_LUT_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_LUT_1_B_LUT_DEFAULT_MASK _MK_MASK_CONST(0xff) +#define DC_DISP_SD_LUT_1_B_LUT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_LUT_1_B_LUT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_DISP_SD_LUT_2 +#define DC_DISP_SD_LUT_2 _MK_ADDR_CONST(0x4c6) +#define DC_DISP_SD_LUT_2_SECURE 0x0 +#define DC_DISP_SD_LUT_2_WORD_COUNT 0x1 +#define DC_DISP_SD_LUT_2_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_SD_LUT_2_RESET_MASK _MK_MASK_CONST(0xffffff) +#define DC_DISP_SD_LUT_2_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_SD_LUT_2_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_SD_LUT_2_READ_MASK _MK_MASK_CONST(0xffffff) +#define DC_DISP_SD_LUT_2_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_DISP_SD_LUT_2_R_LUT_SHIFT _MK_SHIFT_CONST(0) +#define DC_DISP_SD_LUT_2_R_LUT_FIELD _MK_FIELD_CONST(0xff, DC_DISP_SD_LUT_2_R_LUT_SHIFT) +#define DC_DISP_SD_LUT_2_R_LUT_RANGE 7:0 +#define DC_DISP_SD_LUT_2_R_LUT_WOFFSET 0x0 +#define DC_DISP_SD_LUT_2_R_LUT_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_LUT_2_R_LUT_DEFAULT_MASK _MK_MASK_CONST(0xff) +#define DC_DISP_SD_LUT_2_R_LUT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_LUT_2_R_LUT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_DISP_SD_LUT_2_G_LUT_SHIFT _MK_SHIFT_CONST(8) +#define DC_DISP_SD_LUT_2_G_LUT_FIELD _MK_FIELD_CONST(0xff, DC_DISP_SD_LUT_2_G_LUT_SHIFT) +#define DC_DISP_SD_LUT_2_G_LUT_RANGE 15:8 +#define DC_DISP_SD_LUT_2_G_LUT_WOFFSET 0x0 +#define DC_DISP_SD_LUT_2_G_LUT_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_LUT_2_G_LUT_DEFAULT_MASK _MK_MASK_CONST(0xff) +#define DC_DISP_SD_LUT_2_G_LUT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_LUT_2_G_LUT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_DISP_SD_LUT_2_B_LUT_SHIFT _MK_SHIFT_CONST(16) +#define DC_DISP_SD_LUT_2_B_LUT_FIELD _MK_FIELD_CONST(0xff, DC_DISP_SD_LUT_2_B_LUT_SHIFT) +#define DC_DISP_SD_LUT_2_B_LUT_RANGE 23:16 +#define DC_DISP_SD_LUT_2_B_LUT_WOFFSET 0x0 +#define DC_DISP_SD_LUT_2_B_LUT_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_LUT_2_B_LUT_DEFAULT_MASK _MK_MASK_CONST(0xff) +#define DC_DISP_SD_LUT_2_B_LUT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_LUT_2_B_LUT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_DISP_SD_LUT_3 +#define DC_DISP_SD_LUT_3 _MK_ADDR_CONST(0x4c7) +#define DC_DISP_SD_LUT_3_SECURE 0x0 +#define DC_DISP_SD_LUT_3_WORD_COUNT 0x1 +#define DC_DISP_SD_LUT_3_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_SD_LUT_3_RESET_MASK _MK_MASK_CONST(0xffffff) +#define DC_DISP_SD_LUT_3_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_SD_LUT_3_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_SD_LUT_3_READ_MASK _MK_MASK_CONST(0xffffff) +#define DC_DISP_SD_LUT_3_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_DISP_SD_LUT_3_R_LUT_SHIFT _MK_SHIFT_CONST(0) +#define DC_DISP_SD_LUT_3_R_LUT_FIELD _MK_FIELD_CONST(0xff, DC_DISP_SD_LUT_3_R_LUT_SHIFT) +#define DC_DISP_SD_LUT_3_R_LUT_RANGE 7:0 +#define DC_DISP_SD_LUT_3_R_LUT_WOFFSET 0x0 +#define DC_DISP_SD_LUT_3_R_LUT_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_LUT_3_R_LUT_DEFAULT_MASK _MK_MASK_CONST(0xff) +#define DC_DISP_SD_LUT_3_R_LUT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_LUT_3_R_LUT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_DISP_SD_LUT_3_G_LUT_SHIFT _MK_SHIFT_CONST(8) +#define DC_DISP_SD_LUT_3_G_LUT_FIELD _MK_FIELD_CONST(0xff, DC_DISP_SD_LUT_3_G_LUT_SHIFT) +#define DC_DISP_SD_LUT_3_G_LUT_RANGE 15:8 +#define DC_DISP_SD_LUT_3_G_LUT_WOFFSET 0x0 +#define DC_DISP_SD_LUT_3_G_LUT_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_LUT_3_G_LUT_DEFAULT_MASK _MK_MASK_CONST(0xff) +#define DC_DISP_SD_LUT_3_G_LUT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_LUT_3_G_LUT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_DISP_SD_LUT_3_B_LUT_SHIFT _MK_SHIFT_CONST(16) +#define DC_DISP_SD_LUT_3_B_LUT_FIELD _MK_FIELD_CONST(0xff, DC_DISP_SD_LUT_3_B_LUT_SHIFT) +#define DC_DISP_SD_LUT_3_B_LUT_RANGE 23:16 +#define DC_DISP_SD_LUT_3_B_LUT_WOFFSET 0x0 +#define DC_DISP_SD_LUT_3_B_LUT_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_LUT_3_B_LUT_DEFAULT_MASK _MK_MASK_CONST(0xff) +#define DC_DISP_SD_LUT_3_B_LUT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_LUT_3_B_LUT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_DISP_SD_LUT_4 +#define DC_DISP_SD_LUT_4 _MK_ADDR_CONST(0x4c8) +#define DC_DISP_SD_LUT_4_SECURE 0x0 +#define DC_DISP_SD_LUT_4_WORD_COUNT 0x1 +#define DC_DISP_SD_LUT_4_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_SD_LUT_4_RESET_MASK _MK_MASK_CONST(0xffffff) +#define DC_DISP_SD_LUT_4_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_SD_LUT_4_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_SD_LUT_4_READ_MASK _MK_MASK_CONST(0xffffff) +#define DC_DISP_SD_LUT_4_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_DISP_SD_LUT_4_R_LUT_SHIFT _MK_SHIFT_CONST(0) +#define DC_DISP_SD_LUT_4_R_LUT_FIELD _MK_FIELD_CONST(0xff, DC_DISP_SD_LUT_4_R_LUT_SHIFT) +#define DC_DISP_SD_LUT_4_R_LUT_RANGE 7:0 +#define DC_DISP_SD_LUT_4_R_LUT_WOFFSET 0x0 +#define DC_DISP_SD_LUT_4_R_LUT_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_LUT_4_R_LUT_DEFAULT_MASK _MK_MASK_CONST(0xff) +#define DC_DISP_SD_LUT_4_R_LUT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_LUT_4_R_LUT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_DISP_SD_LUT_4_G_LUT_SHIFT _MK_SHIFT_CONST(8) +#define DC_DISP_SD_LUT_4_G_LUT_FIELD _MK_FIELD_CONST(0xff, DC_DISP_SD_LUT_4_G_LUT_SHIFT) +#define DC_DISP_SD_LUT_4_G_LUT_RANGE 15:8 +#define DC_DISP_SD_LUT_4_G_LUT_WOFFSET 0x0 +#define DC_DISP_SD_LUT_4_G_LUT_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_LUT_4_G_LUT_DEFAULT_MASK _MK_MASK_CONST(0xff) +#define DC_DISP_SD_LUT_4_G_LUT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_LUT_4_G_LUT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_DISP_SD_LUT_4_B_LUT_SHIFT _MK_SHIFT_CONST(16) +#define DC_DISP_SD_LUT_4_B_LUT_FIELD _MK_FIELD_CONST(0xff, DC_DISP_SD_LUT_4_B_LUT_SHIFT) +#define DC_DISP_SD_LUT_4_B_LUT_RANGE 23:16 +#define DC_DISP_SD_LUT_4_B_LUT_WOFFSET 0x0 +#define DC_DISP_SD_LUT_4_B_LUT_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_LUT_4_B_LUT_DEFAULT_MASK _MK_MASK_CONST(0xff) +#define DC_DISP_SD_LUT_4_B_LUT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_LUT_4_B_LUT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_DISP_SD_LUT_5 +#define DC_DISP_SD_LUT_5 _MK_ADDR_CONST(0x4c9) +#define DC_DISP_SD_LUT_5_SECURE 0x0 +#define DC_DISP_SD_LUT_5_WORD_COUNT 0x1 +#define DC_DISP_SD_LUT_5_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_SD_LUT_5_RESET_MASK _MK_MASK_CONST(0xffffff) +#define DC_DISP_SD_LUT_5_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_SD_LUT_5_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_SD_LUT_5_READ_MASK _MK_MASK_CONST(0xffffff) +#define DC_DISP_SD_LUT_5_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_DISP_SD_LUT_5_R_LUT_SHIFT _MK_SHIFT_CONST(0) +#define DC_DISP_SD_LUT_5_R_LUT_FIELD _MK_FIELD_CONST(0xff, DC_DISP_SD_LUT_5_R_LUT_SHIFT) +#define DC_DISP_SD_LUT_5_R_LUT_RANGE 7:0 +#define DC_DISP_SD_LUT_5_R_LUT_WOFFSET 0x0 +#define DC_DISP_SD_LUT_5_R_LUT_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_LUT_5_R_LUT_DEFAULT_MASK _MK_MASK_CONST(0xff) +#define DC_DISP_SD_LUT_5_R_LUT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_LUT_5_R_LUT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_DISP_SD_LUT_5_G_LUT_SHIFT _MK_SHIFT_CONST(8) +#define DC_DISP_SD_LUT_5_G_LUT_FIELD _MK_FIELD_CONST(0xff, DC_DISP_SD_LUT_5_G_LUT_SHIFT) +#define DC_DISP_SD_LUT_5_G_LUT_RANGE 15:8 +#define DC_DISP_SD_LUT_5_G_LUT_WOFFSET 0x0 +#define DC_DISP_SD_LUT_5_G_LUT_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_LUT_5_G_LUT_DEFAULT_MASK _MK_MASK_CONST(0xff) +#define DC_DISP_SD_LUT_5_G_LUT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_LUT_5_G_LUT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_DISP_SD_LUT_5_B_LUT_SHIFT _MK_SHIFT_CONST(16) +#define DC_DISP_SD_LUT_5_B_LUT_FIELD _MK_FIELD_CONST(0xff, DC_DISP_SD_LUT_5_B_LUT_SHIFT) +#define DC_DISP_SD_LUT_5_B_LUT_RANGE 23:16 +#define DC_DISP_SD_LUT_5_B_LUT_WOFFSET 0x0 +#define DC_DISP_SD_LUT_5_B_LUT_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_LUT_5_B_LUT_DEFAULT_MASK _MK_MASK_CONST(0xff) +#define DC_DISP_SD_LUT_5_B_LUT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_LUT_5_B_LUT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_DISP_SD_LUT_6 +#define DC_DISP_SD_LUT_6 _MK_ADDR_CONST(0x4ca) +#define DC_DISP_SD_LUT_6_SECURE 0x0 +#define DC_DISP_SD_LUT_6_WORD_COUNT 0x1 +#define DC_DISP_SD_LUT_6_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_SD_LUT_6_RESET_MASK _MK_MASK_CONST(0xffffff) +#define DC_DISP_SD_LUT_6_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_SD_LUT_6_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_SD_LUT_6_READ_MASK _MK_MASK_CONST(0xffffff) +#define DC_DISP_SD_LUT_6_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_DISP_SD_LUT_6_R_LUT_SHIFT _MK_SHIFT_CONST(0) +#define DC_DISP_SD_LUT_6_R_LUT_FIELD _MK_FIELD_CONST(0xff, DC_DISP_SD_LUT_6_R_LUT_SHIFT) +#define DC_DISP_SD_LUT_6_R_LUT_RANGE 7:0 +#define DC_DISP_SD_LUT_6_R_LUT_WOFFSET 0x0 +#define DC_DISP_SD_LUT_6_R_LUT_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_LUT_6_R_LUT_DEFAULT_MASK _MK_MASK_CONST(0xff) +#define DC_DISP_SD_LUT_6_R_LUT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_LUT_6_R_LUT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_DISP_SD_LUT_6_G_LUT_SHIFT _MK_SHIFT_CONST(8) +#define DC_DISP_SD_LUT_6_G_LUT_FIELD _MK_FIELD_CONST(0xff, DC_DISP_SD_LUT_6_G_LUT_SHIFT) +#define DC_DISP_SD_LUT_6_G_LUT_RANGE 15:8 +#define DC_DISP_SD_LUT_6_G_LUT_WOFFSET 0x0 +#define DC_DISP_SD_LUT_6_G_LUT_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_LUT_6_G_LUT_DEFAULT_MASK _MK_MASK_CONST(0xff) +#define DC_DISP_SD_LUT_6_G_LUT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_LUT_6_G_LUT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_DISP_SD_LUT_6_B_LUT_SHIFT _MK_SHIFT_CONST(16) +#define DC_DISP_SD_LUT_6_B_LUT_FIELD _MK_FIELD_CONST(0xff, DC_DISP_SD_LUT_6_B_LUT_SHIFT) +#define DC_DISP_SD_LUT_6_B_LUT_RANGE 23:16 +#define DC_DISP_SD_LUT_6_B_LUT_WOFFSET 0x0 +#define DC_DISP_SD_LUT_6_B_LUT_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_LUT_6_B_LUT_DEFAULT_MASK _MK_MASK_CONST(0xff) +#define DC_DISP_SD_LUT_6_B_LUT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_LUT_6_B_LUT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_DISP_SD_LUT_7 +#define DC_DISP_SD_LUT_7 _MK_ADDR_CONST(0x4cb) +#define DC_DISP_SD_LUT_7_SECURE 0x0 +#define DC_DISP_SD_LUT_7_WORD_COUNT 0x1 +#define DC_DISP_SD_LUT_7_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_SD_LUT_7_RESET_MASK _MK_MASK_CONST(0xffffff) +#define DC_DISP_SD_LUT_7_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_SD_LUT_7_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_SD_LUT_7_READ_MASK _MK_MASK_CONST(0xffffff) +#define DC_DISP_SD_LUT_7_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_DISP_SD_LUT_7_R_LUT_SHIFT _MK_SHIFT_CONST(0) +#define DC_DISP_SD_LUT_7_R_LUT_FIELD _MK_FIELD_CONST(0xff, DC_DISP_SD_LUT_7_R_LUT_SHIFT) +#define DC_DISP_SD_LUT_7_R_LUT_RANGE 7:0 +#define DC_DISP_SD_LUT_7_R_LUT_WOFFSET 0x0 +#define DC_DISP_SD_LUT_7_R_LUT_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_LUT_7_R_LUT_DEFAULT_MASK _MK_MASK_CONST(0xff) +#define DC_DISP_SD_LUT_7_R_LUT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_LUT_7_R_LUT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_DISP_SD_LUT_7_G_LUT_SHIFT _MK_SHIFT_CONST(8) +#define DC_DISP_SD_LUT_7_G_LUT_FIELD _MK_FIELD_CONST(0xff, DC_DISP_SD_LUT_7_G_LUT_SHIFT) +#define DC_DISP_SD_LUT_7_G_LUT_RANGE 15:8 +#define DC_DISP_SD_LUT_7_G_LUT_WOFFSET 0x0 +#define DC_DISP_SD_LUT_7_G_LUT_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_LUT_7_G_LUT_DEFAULT_MASK _MK_MASK_CONST(0xff) +#define DC_DISP_SD_LUT_7_G_LUT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_LUT_7_G_LUT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_DISP_SD_LUT_7_B_LUT_SHIFT _MK_SHIFT_CONST(16) +#define DC_DISP_SD_LUT_7_B_LUT_FIELD _MK_FIELD_CONST(0xff, DC_DISP_SD_LUT_7_B_LUT_SHIFT) +#define DC_DISP_SD_LUT_7_B_LUT_RANGE 23:16 +#define DC_DISP_SD_LUT_7_B_LUT_WOFFSET 0x0 +#define DC_DISP_SD_LUT_7_B_LUT_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_LUT_7_B_LUT_DEFAULT_MASK _MK_MASK_CONST(0xff) +#define DC_DISP_SD_LUT_7_B_LUT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_LUT_7_B_LUT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_DISP_SD_LUT_8 +#define DC_DISP_SD_LUT_8 _MK_ADDR_CONST(0x4cc) +#define DC_DISP_SD_LUT_8_SECURE 0x0 +#define DC_DISP_SD_LUT_8_WORD_COUNT 0x1 +#define DC_DISP_SD_LUT_8_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_SD_LUT_8_RESET_MASK _MK_MASK_CONST(0xffffff) +#define DC_DISP_SD_LUT_8_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_SD_LUT_8_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_SD_LUT_8_READ_MASK _MK_MASK_CONST(0xffffff) +#define DC_DISP_SD_LUT_8_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_DISP_SD_LUT_8_R_LUT_SHIFT _MK_SHIFT_CONST(0) +#define DC_DISP_SD_LUT_8_R_LUT_FIELD _MK_FIELD_CONST(0xff, DC_DISP_SD_LUT_8_R_LUT_SHIFT) +#define DC_DISP_SD_LUT_8_R_LUT_RANGE 7:0 +#define DC_DISP_SD_LUT_8_R_LUT_WOFFSET 0x0 +#define DC_DISP_SD_LUT_8_R_LUT_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_LUT_8_R_LUT_DEFAULT_MASK _MK_MASK_CONST(0xff) +#define DC_DISP_SD_LUT_8_R_LUT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_LUT_8_R_LUT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_DISP_SD_LUT_8_G_LUT_SHIFT _MK_SHIFT_CONST(8) +#define DC_DISP_SD_LUT_8_G_LUT_FIELD _MK_FIELD_CONST(0xff, DC_DISP_SD_LUT_8_G_LUT_SHIFT) +#define DC_DISP_SD_LUT_8_G_LUT_RANGE 15:8 +#define DC_DISP_SD_LUT_8_G_LUT_WOFFSET 0x0 +#define DC_DISP_SD_LUT_8_G_LUT_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_LUT_8_G_LUT_DEFAULT_MASK _MK_MASK_CONST(0xff) +#define DC_DISP_SD_LUT_8_G_LUT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_LUT_8_G_LUT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_DISP_SD_LUT_8_B_LUT_SHIFT _MK_SHIFT_CONST(16) +#define DC_DISP_SD_LUT_8_B_LUT_FIELD _MK_FIELD_CONST(0xff, DC_DISP_SD_LUT_8_B_LUT_SHIFT) +#define DC_DISP_SD_LUT_8_B_LUT_RANGE 23:16 +#define DC_DISP_SD_LUT_8_B_LUT_WOFFSET 0x0 +#define DC_DISP_SD_LUT_8_B_LUT_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_LUT_8_B_LUT_DEFAULT_MASK _MK_MASK_CONST(0xff) +#define DC_DISP_SD_LUT_8_B_LUT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_LUT_8_B_LUT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_DISP_SD_FLICKER_CONTROL_0 +#define DC_DISP_SD_FLICKER_CONTROL_0 _MK_ADDR_CONST(0x4cd) +#define DC_DISP_SD_FLICKER_CONTROL_0_SECURE 0x0 +#define DC_DISP_SD_FLICKER_CONTROL_0_WORD_COUNT 0x1 +#define DC_DISP_SD_FLICKER_CONTROL_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_SD_FLICKER_CONTROL_0_RESET_MASK _MK_MASK_CONST(0xffff) +#define DC_DISP_SD_FLICKER_CONTROL_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_SD_FLICKER_CONTROL_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_SD_FLICKER_CONTROL_0_READ_MASK _MK_MASK_CONST(0xffff) +#define DC_DISP_SD_FLICKER_CONTROL_0_WRITE_MASK _MK_MASK_CONST(0xffff) +#define DC_DISP_SD_FLICKER_CONTROL_0_TIME_LIMIT_SHIFT _MK_SHIFT_CONST(0) +#define DC_DISP_SD_FLICKER_CONTROL_0_TIME_LIMIT_FIELD _MK_FIELD_CONST(0xff, DC_DISP_SD_FLICKER_CONTROL_0_TIME_LIMIT_SHIFT) +#define DC_DISP_SD_FLICKER_CONTROL_0_TIME_LIMIT_RANGE 7:0 +#define DC_DISP_SD_FLICKER_CONTROL_0_TIME_LIMIT_WOFFSET 0x0 +#define DC_DISP_SD_FLICKER_CONTROL_0_TIME_LIMIT_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_FLICKER_CONTROL_0_TIME_LIMIT_DEFAULT_MASK _MK_MASK_CONST(0xff) +#define DC_DISP_SD_FLICKER_CONTROL_0_TIME_LIMIT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_FLICKER_CONTROL_0_TIME_LIMIT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_DISP_SD_FLICKER_CONTROL_0_THRESHOLD_SHIFT _MK_SHIFT_CONST(8) +#define DC_DISP_SD_FLICKER_CONTROL_0_THRESHOLD_FIELD _MK_FIELD_CONST(0xff, DC_DISP_SD_FLICKER_CONTROL_0_THRESHOLD_SHIFT) +#define DC_DISP_SD_FLICKER_CONTROL_0_THRESHOLD_RANGE 15:8 +#define DC_DISP_SD_FLICKER_CONTROL_0_THRESHOLD_WOFFSET 0x0 +#define DC_DISP_SD_FLICKER_CONTROL_0_THRESHOLD_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_FLICKER_CONTROL_0_THRESHOLD_DEFAULT_MASK _MK_MASK_CONST(0xff) +#define DC_DISP_SD_FLICKER_CONTROL_0_THRESHOLD_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_FLICKER_CONTROL_0_THRESHOLD_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_DISP_SD_PIXEL_COUNT_0 +#define DC_DISP_SD_PIXEL_COUNT_0 _MK_ADDR_CONST(0x4ce) +#define DC_DISP_SD_PIXEL_COUNT_0_SECURE 0x0 +#define DC_DISP_SD_PIXEL_COUNT_0_WORD_COUNT 0x1 +#define DC_DISP_SD_PIXEL_COUNT_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_SD_PIXEL_COUNT_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_SD_PIXEL_COUNT_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_SD_PIXEL_COUNT_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_SD_PIXEL_COUNT_0_READ_MASK _MK_MASK_CONST(0xffff) +#define DC_DISP_SD_PIXEL_COUNT_0_WRITE_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_SD_PIXEL_COUNT_0_NUM_PIXELS_SHIFT _MK_SHIFT_CONST(0) +#define DC_DISP_SD_PIXEL_COUNT_0_NUM_PIXELS_FIELD _MK_FIELD_CONST(0xffff, DC_DISP_SD_PIXEL_COUNT_0_NUM_PIXELS_SHIFT) +#define DC_DISP_SD_PIXEL_COUNT_0_NUM_PIXELS_RANGE 15:0 +#define DC_DISP_SD_PIXEL_COUNT_0_NUM_PIXELS_WOFFSET 0x0 +#define DC_DISP_SD_PIXEL_COUNT_0_NUM_PIXELS_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_PIXEL_COUNT_0_NUM_PIXELS_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_SD_PIXEL_COUNT_0_NUM_PIXELS_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_PIXEL_COUNT_0_NUM_PIXELS_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_DISP_SD_HISTOGRAM_0 +#define DC_DISP_SD_HISTOGRAM_0 _MK_ADDR_CONST(0x4cf) +#define DC_DISP_SD_HISTOGRAM_0_SECURE 0x0 +#define DC_DISP_SD_HISTOGRAM_0_WORD_COUNT 0x1 +#define DC_DISP_SD_HISTOGRAM_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_SD_HISTOGRAM_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_SD_HISTOGRAM_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_SD_HISTOGRAM_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_SD_HISTOGRAM_0_READ_MASK _MK_MASK_CONST(0xffffffff) +#define DC_DISP_SD_HISTOGRAM_0_WRITE_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_SD_HISTOGRAM_0_BIN_0_SHIFT _MK_SHIFT_CONST(0) +#define DC_DISP_SD_HISTOGRAM_0_BIN_0_FIELD _MK_FIELD_CONST(0xff, DC_DISP_SD_HISTOGRAM_0_BIN_0_SHIFT) +#define DC_DISP_SD_HISTOGRAM_0_BIN_0_RANGE 7:0 +#define DC_DISP_SD_HISTOGRAM_0_BIN_0_WOFFSET 0x0 +#define DC_DISP_SD_HISTOGRAM_0_BIN_0_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_HISTOGRAM_0_BIN_0_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_SD_HISTOGRAM_0_BIN_0_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_HISTOGRAM_0_BIN_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_DISP_SD_HISTOGRAM_0_BIN_1_SHIFT _MK_SHIFT_CONST(8) +#define DC_DISP_SD_HISTOGRAM_0_BIN_1_FIELD _MK_FIELD_CONST(0xff, DC_DISP_SD_HISTOGRAM_0_BIN_1_SHIFT) +#define DC_DISP_SD_HISTOGRAM_0_BIN_1_RANGE 15:8 +#define DC_DISP_SD_HISTOGRAM_0_BIN_1_WOFFSET 0x0 +#define DC_DISP_SD_HISTOGRAM_0_BIN_1_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_HISTOGRAM_0_BIN_1_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_SD_HISTOGRAM_0_BIN_1_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_HISTOGRAM_0_BIN_1_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_DISP_SD_HISTOGRAM_0_BIN_2_SHIFT _MK_SHIFT_CONST(16) +#define DC_DISP_SD_HISTOGRAM_0_BIN_2_FIELD _MK_FIELD_CONST(0xff, DC_DISP_SD_HISTOGRAM_0_BIN_2_SHIFT) +#define DC_DISP_SD_HISTOGRAM_0_BIN_2_RANGE 23:16 +#define DC_DISP_SD_HISTOGRAM_0_BIN_2_WOFFSET 0x0 +#define DC_DISP_SD_HISTOGRAM_0_BIN_2_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_HISTOGRAM_0_BIN_2_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_SD_HISTOGRAM_0_BIN_2_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_HISTOGRAM_0_BIN_2_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_DISP_SD_HISTOGRAM_0_BIN_3_SHIFT _MK_SHIFT_CONST(24) +#define DC_DISP_SD_HISTOGRAM_0_BIN_3_FIELD _MK_FIELD_CONST(0xff, DC_DISP_SD_HISTOGRAM_0_BIN_3_SHIFT) +#define DC_DISP_SD_HISTOGRAM_0_BIN_3_RANGE 31:24 +#define DC_DISP_SD_HISTOGRAM_0_BIN_3_WOFFSET 0x0 +#define DC_DISP_SD_HISTOGRAM_0_BIN_3_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_HISTOGRAM_0_BIN_3_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_SD_HISTOGRAM_0_BIN_3_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_HISTOGRAM_0_BIN_3_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_DISP_SD_HISTOGRAM +#define DC_DISP_SD_HISTOGRAM _MK_ADDR_CONST(0x4cf) +#define DC_DISP_SD_HISTOGRAM_SECURE 0x0 +#define DC_DISP_SD_HISTOGRAM_WORD_COUNT 0x1 +#define DC_DISP_SD_HISTOGRAM_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_SD_HISTOGRAM_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_SD_HISTOGRAM_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_SD_HISTOGRAM_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_SD_HISTOGRAM_READ_MASK _MK_MASK_CONST(0xffffffff) +#define DC_DISP_SD_HISTOGRAM_WRITE_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_SD_HISTOGRAM_BIN_0_SHIFT _MK_SHIFT_CONST(0) +#define DC_DISP_SD_HISTOGRAM_BIN_0_FIELD _MK_FIELD_CONST(0xff, DC_DISP_SD_HISTOGRAM_BIN_0_SHIFT) +#define DC_DISP_SD_HISTOGRAM_BIN_0_RANGE 7:0 +#define DC_DISP_SD_HISTOGRAM_BIN_0_WOFFSET 0x0 +#define DC_DISP_SD_HISTOGRAM_BIN_0_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_HISTOGRAM_BIN_0_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_SD_HISTOGRAM_BIN_0_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_HISTOGRAM_BIN_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_DISP_SD_HISTOGRAM_BIN_1_SHIFT _MK_SHIFT_CONST(8) +#define DC_DISP_SD_HISTOGRAM_BIN_1_FIELD _MK_FIELD_CONST(0xff, DC_DISP_SD_HISTOGRAM_BIN_1_SHIFT) +#define DC_DISP_SD_HISTOGRAM_BIN_1_RANGE 15:8 +#define DC_DISP_SD_HISTOGRAM_BIN_1_WOFFSET 0x0 +#define DC_DISP_SD_HISTOGRAM_BIN_1_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_HISTOGRAM_BIN_1_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_SD_HISTOGRAM_BIN_1_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_HISTOGRAM_BIN_1_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_DISP_SD_HISTOGRAM_BIN_2_SHIFT _MK_SHIFT_CONST(16) +#define DC_DISP_SD_HISTOGRAM_BIN_2_FIELD _MK_FIELD_CONST(0xff, DC_DISP_SD_HISTOGRAM_BIN_2_SHIFT) +#define DC_DISP_SD_HISTOGRAM_BIN_2_RANGE 23:16 +#define DC_DISP_SD_HISTOGRAM_BIN_2_WOFFSET 0x0 +#define DC_DISP_SD_HISTOGRAM_BIN_2_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_HISTOGRAM_BIN_2_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_SD_HISTOGRAM_BIN_2_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_HISTOGRAM_BIN_2_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_DISP_SD_HISTOGRAM_BIN_3_SHIFT _MK_SHIFT_CONST(24) +#define DC_DISP_SD_HISTOGRAM_BIN_3_FIELD _MK_FIELD_CONST(0xff, DC_DISP_SD_HISTOGRAM_BIN_3_SHIFT) +#define DC_DISP_SD_HISTOGRAM_BIN_3_RANGE 31:24 +#define DC_DISP_SD_HISTOGRAM_BIN_3_WOFFSET 0x0 +#define DC_DISP_SD_HISTOGRAM_BIN_3_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_HISTOGRAM_BIN_3_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_SD_HISTOGRAM_BIN_3_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_HISTOGRAM_BIN_3_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_DISP_SD_HISTOGRAM_1 +#define DC_DISP_SD_HISTOGRAM_1 _MK_ADDR_CONST(0x4d0) +#define DC_DISP_SD_HISTOGRAM_1_SECURE 0x0 +#define DC_DISP_SD_HISTOGRAM_1_WORD_COUNT 0x1 +#define DC_DISP_SD_HISTOGRAM_1_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_SD_HISTOGRAM_1_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_SD_HISTOGRAM_1_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_SD_HISTOGRAM_1_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_SD_HISTOGRAM_1_READ_MASK _MK_MASK_CONST(0xffffffff) +#define DC_DISP_SD_HISTOGRAM_1_WRITE_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_SD_HISTOGRAM_1_BIN_0_SHIFT _MK_SHIFT_CONST(0) +#define DC_DISP_SD_HISTOGRAM_1_BIN_0_FIELD _MK_FIELD_CONST(0xff, DC_DISP_SD_HISTOGRAM_1_BIN_0_SHIFT) +#define DC_DISP_SD_HISTOGRAM_1_BIN_0_RANGE 7:0 +#define DC_DISP_SD_HISTOGRAM_1_BIN_0_WOFFSET 0x0 +#define DC_DISP_SD_HISTOGRAM_1_BIN_0_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_HISTOGRAM_1_BIN_0_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_SD_HISTOGRAM_1_BIN_0_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_HISTOGRAM_1_BIN_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_DISP_SD_HISTOGRAM_1_BIN_1_SHIFT _MK_SHIFT_CONST(8) +#define DC_DISP_SD_HISTOGRAM_1_BIN_1_FIELD _MK_FIELD_CONST(0xff, DC_DISP_SD_HISTOGRAM_1_BIN_1_SHIFT) +#define DC_DISP_SD_HISTOGRAM_1_BIN_1_RANGE 15:8 +#define DC_DISP_SD_HISTOGRAM_1_BIN_1_WOFFSET 0x0 +#define DC_DISP_SD_HISTOGRAM_1_BIN_1_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_HISTOGRAM_1_BIN_1_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_SD_HISTOGRAM_1_BIN_1_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_HISTOGRAM_1_BIN_1_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_DISP_SD_HISTOGRAM_1_BIN_2_SHIFT _MK_SHIFT_CONST(16) +#define DC_DISP_SD_HISTOGRAM_1_BIN_2_FIELD _MK_FIELD_CONST(0xff, DC_DISP_SD_HISTOGRAM_1_BIN_2_SHIFT) +#define DC_DISP_SD_HISTOGRAM_1_BIN_2_RANGE 23:16 +#define DC_DISP_SD_HISTOGRAM_1_BIN_2_WOFFSET 0x0 +#define DC_DISP_SD_HISTOGRAM_1_BIN_2_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_HISTOGRAM_1_BIN_2_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_SD_HISTOGRAM_1_BIN_2_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_HISTOGRAM_1_BIN_2_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_DISP_SD_HISTOGRAM_1_BIN_3_SHIFT _MK_SHIFT_CONST(24) +#define DC_DISP_SD_HISTOGRAM_1_BIN_3_FIELD _MK_FIELD_CONST(0xff, DC_DISP_SD_HISTOGRAM_1_BIN_3_SHIFT) +#define DC_DISP_SD_HISTOGRAM_1_BIN_3_RANGE 31:24 +#define DC_DISP_SD_HISTOGRAM_1_BIN_3_WOFFSET 0x0 +#define DC_DISP_SD_HISTOGRAM_1_BIN_3_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_HISTOGRAM_1_BIN_3_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_SD_HISTOGRAM_1_BIN_3_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_HISTOGRAM_1_BIN_3_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_DISP_SD_HISTOGRAM_2 +#define DC_DISP_SD_HISTOGRAM_2 _MK_ADDR_CONST(0x4d1) +#define DC_DISP_SD_HISTOGRAM_2_SECURE 0x0 +#define DC_DISP_SD_HISTOGRAM_2_WORD_COUNT 0x1 +#define DC_DISP_SD_HISTOGRAM_2_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_SD_HISTOGRAM_2_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_SD_HISTOGRAM_2_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_SD_HISTOGRAM_2_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_SD_HISTOGRAM_2_READ_MASK _MK_MASK_CONST(0xffffffff) +#define DC_DISP_SD_HISTOGRAM_2_WRITE_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_SD_HISTOGRAM_2_BIN_0_SHIFT _MK_SHIFT_CONST(0) +#define DC_DISP_SD_HISTOGRAM_2_BIN_0_FIELD _MK_FIELD_CONST(0xff, DC_DISP_SD_HISTOGRAM_2_BIN_0_SHIFT) +#define DC_DISP_SD_HISTOGRAM_2_BIN_0_RANGE 7:0 +#define DC_DISP_SD_HISTOGRAM_2_BIN_0_WOFFSET 0x0 +#define DC_DISP_SD_HISTOGRAM_2_BIN_0_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_HISTOGRAM_2_BIN_0_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_SD_HISTOGRAM_2_BIN_0_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_HISTOGRAM_2_BIN_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_DISP_SD_HISTOGRAM_2_BIN_1_SHIFT _MK_SHIFT_CONST(8) +#define DC_DISP_SD_HISTOGRAM_2_BIN_1_FIELD _MK_FIELD_CONST(0xff, DC_DISP_SD_HISTOGRAM_2_BIN_1_SHIFT) +#define DC_DISP_SD_HISTOGRAM_2_BIN_1_RANGE 15:8 +#define DC_DISP_SD_HISTOGRAM_2_BIN_1_WOFFSET 0x0 +#define DC_DISP_SD_HISTOGRAM_2_BIN_1_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_HISTOGRAM_2_BIN_1_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_SD_HISTOGRAM_2_BIN_1_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_HISTOGRAM_2_BIN_1_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_DISP_SD_HISTOGRAM_2_BIN_2_SHIFT _MK_SHIFT_CONST(16) +#define DC_DISP_SD_HISTOGRAM_2_BIN_2_FIELD _MK_FIELD_CONST(0xff, DC_DISP_SD_HISTOGRAM_2_BIN_2_SHIFT) +#define DC_DISP_SD_HISTOGRAM_2_BIN_2_RANGE 23:16 +#define DC_DISP_SD_HISTOGRAM_2_BIN_2_WOFFSET 0x0 +#define DC_DISP_SD_HISTOGRAM_2_BIN_2_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_HISTOGRAM_2_BIN_2_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_SD_HISTOGRAM_2_BIN_2_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_HISTOGRAM_2_BIN_2_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_DISP_SD_HISTOGRAM_2_BIN_3_SHIFT _MK_SHIFT_CONST(24) +#define DC_DISP_SD_HISTOGRAM_2_BIN_3_FIELD _MK_FIELD_CONST(0xff, DC_DISP_SD_HISTOGRAM_2_BIN_3_SHIFT) +#define DC_DISP_SD_HISTOGRAM_2_BIN_3_RANGE 31:24 +#define DC_DISP_SD_HISTOGRAM_2_BIN_3_WOFFSET 0x0 +#define DC_DISP_SD_HISTOGRAM_2_BIN_3_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_HISTOGRAM_2_BIN_3_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_SD_HISTOGRAM_2_BIN_3_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_HISTOGRAM_2_BIN_3_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_DISP_SD_HISTOGRAM_3 +#define DC_DISP_SD_HISTOGRAM_3 _MK_ADDR_CONST(0x4d2) +#define DC_DISP_SD_HISTOGRAM_3_SECURE 0x0 +#define DC_DISP_SD_HISTOGRAM_3_WORD_COUNT 0x1 +#define DC_DISP_SD_HISTOGRAM_3_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_SD_HISTOGRAM_3_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_SD_HISTOGRAM_3_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_SD_HISTOGRAM_3_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_SD_HISTOGRAM_3_READ_MASK _MK_MASK_CONST(0xffffffff) +#define DC_DISP_SD_HISTOGRAM_3_WRITE_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_SD_HISTOGRAM_3_BIN_0_SHIFT _MK_SHIFT_CONST(0) +#define DC_DISP_SD_HISTOGRAM_3_BIN_0_FIELD _MK_FIELD_CONST(0xff, DC_DISP_SD_HISTOGRAM_3_BIN_0_SHIFT) +#define DC_DISP_SD_HISTOGRAM_3_BIN_0_RANGE 7:0 +#define DC_DISP_SD_HISTOGRAM_3_BIN_0_WOFFSET 0x0 +#define DC_DISP_SD_HISTOGRAM_3_BIN_0_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_HISTOGRAM_3_BIN_0_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_SD_HISTOGRAM_3_BIN_0_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_HISTOGRAM_3_BIN_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_DISP_SD_HISTOGRAM_3_BIN_1_SHIFT _MK_SHIFT_CONST(8) +#define DC_DISP_SD_HISTOGRAM_3_BIN_1_FIELD _MK_FIELD_CONST(0xff, DC_DISP_SD_HISTOGRAM_3_BIN_1_SHIFT) +#define DC_DISP_SD_HISTOGRAM_3_BIN_1_RANGE 15:8 +#define DC_DISP_SD_HISTOGRAM_3_BIN_1_WOFFSET 0x0 +#define DC_DISP_SD_HISTOGRAM_3_BIN_1_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_HISTOGRAM_3_BIN_1_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_SD_HISTOGRAM_3_BIN_1_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_HISTOGRAM_3_BIN_1_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_DISP_SD_HISTOGRAM_3_BIN_2_SHIFT _MK_SHIFT_CONST(16) +#define DC_DISP_SD_HISTOGRAM_3_BIN_2_FIELD _MK_FIELD_CONST(0xff, DC_DISP_SD_HISTOGRAM_3_BIN_2_SHIFT) +#define DC_DISP_SD_HISTOGRAM_3_BIN_2_RANGE 23:16 +#define DC_DISP_SD_HISTOGRAM_3_BIN_2_WOFFSET 0x0 +#define DC_DISP_SD_HISTOGRAM_3_BIN_2_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_HISTOGRAM_3_BIN_2_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_SD_HISTOGRAM_3_BIN_2_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_HISTOGRAM_3_BIN_2_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_DISP_SD_HISTOGRAM_3_BIN_3_SHIFT _MK_SHIFT_CONST(24) +#define DC_DISP_SD_HISTOGRAM_3_BIN_3_FIELD _MK_FIELD_CONST(0xff, DC_DISP_SD_HISTOGRAM_3_BIN_3_SHIFT) +#define DC_DISP_SD_HISTOGRAM_3_BIN_3_RANGE 31:24 +#define DC_DISP_SD_HISTOGRAM_3_BIN_3_WOFFSET 0x0 +#define DC_DISP_SD_HISTOGRAM_3_BIN_3_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_HISTOGRAM_3_BIN_3_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_SD_HISTOGRAM_3_BIN_3_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_HISTOGRAM_3_BIN_3_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_DISP_SD_HISTOGRAM_4 +#define DC_DISP_SD_HISTOGRAM_4 _MK_ADDR_CONST(0x4d3) +#define DC_DISP_SD_HISTOGRAM_4_SECURE 0x0 +#define DC_DISP_SD_HISTOGRAM_4_WORD_COUNT 0x1 +#define DC_DISP_SD_HISTOGRAM_4_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_SD_HISTOGRAM_4_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_SD_HISTOGRAM_4_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_SD_HISTOGRAM_4_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_SD_HISTOGRAM_4_READ_MASK _MK_MASK_CONST(0xffffffff) +#define DC_DISP_SD_HISTOGRAM_4_WRITE_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_SD_HISTOGRAM_4_BIN_0_SHIFT _MK_SHIFT_CONST(0) +#define DC_DISP_SD_HISTOGRAM_4_BIN_0_FIELD _MK_FIELD_CONST(0xff, DC_DISP_SD_HISTOGRAM_4_BIN_0_SHIFT) +#define DC_DISP_SD_HISTOGRAM_4_BIN_0_RANGE 7:0 +#define DC_DISP_SD_HISTOGRAM_4_BIN_0_WOFFSET 0x0 +#define DC_DISP_SD_HISTOGRAM_4_BIN_0_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_HISTOGRAM_4_BIN_0_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_SD_HISTOGRAM_4_BIN_0_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_HISTOGRAM_4_BIN_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_DISP_SD_HISTOGRAM_4_BIN_1_SHIFT _MK_SHIFT_CONST(8) +#define DC_DISP_SD_HISTOGRAM_4_BIN_1_FIELD _MK_FIELD_CONST(0xff, DC_DISP_SD_HISTOGRAM_4_BIN_1_SHIFT) +#define DC_DISP_SD_HISTOGRAM_4_BIN_1_RANGE 15:8 +#define DC_DISP_SD_HISTOGRAM_4_BIN_1_WOFFSET 0x0 +#define DC_DISP_SD_HISTOGRAM_4_BIN_1_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_HISTOGRAM_4_BIN_1_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_SD_HISTOGRAM_4_BIN_1_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_HISTOGRAM_4_BIN_1_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_DISP_SD_HISTOGRAM_4_BIN_2_SHIFT _MK_SHIFT_CONST(16) +#define DC_DISP_SD_HISTOGRAM_4_BIN_2_FIELD _MK_FIELD_CONST(0xff, DC_DISP_SD_HISTOGRAM_4_BIN_2_SHIFT) +#define DC_DISP_SD_HISTOGRAM_4_BIN_2_RANGE 23:16 +#define DC_DISP_SD_HISTOGRAM_4_BIN_2_WOFFSET 0x0 +#define DC_DISP_SD_HISTOGRAM_4_BIN_2_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_HISTOGRAM_4_BIN_2_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_SD_HISTOGRAM_4_BIN_2_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_HISTOGRAM_4_BIN_2_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_DISP_SD_HISTOGRAM_4_BIN_3_SHIFT _MK_SHIFT_CONST(24) +#define DC_DISP_SD_HISTOGRAM_4_BIN_3_FIELD _MK_FIELD_CONST(0xff, DC_DISP_SD_HISTOGRAM_4_BIN_3_SHIFT) +#define DC_DISP_SD_HISTOGRAM_4_BIN_3_RANGE 31:24 +#define DC_DISP_SD_HISTOGRAM_4_BIN_3_WOFFSET 0x0 +#define DC_DISP_SD_HISTOGRAM_4_BIN_3_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_HISTOGRAM_4_BIN_3_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_SD_HISTOGRAM_4_BIN_3_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_HISTOGRAM_4_BIN_3_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_DISP_SD_HISTOGRAM_5 +#define DC_DISP_SD_HISTOGRAM_5 _MK_ADDR_CONST(0x4d4) +#define DC_DISP_SD_HISTOGRAM_5_SECURE 0x0 +#define DC_DISP_SD_HISTOGRAM_5_WORD_COUNT 0x1 +#define DC_DISP_SD_HISTOGRAM_5_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_SD_HISTOGRAM_5_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_SD_HISTOGRAM_5_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_SD_HISTOGRAM_5_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_SD_HISTOGRAM_5_READ_MASK _MK_MASK_CONST(0xffffffff) +#define DC_DISP_SD_HISTOGRAM_5_WRITE_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_SD_HISTOGRAM_5_BIN_0_SHIFT _MK_SHIFT_CONST(0) +#define DC_DISP_SD_HISTOGRAM_5_BIN_0_FIELD _MK_FIELD_CONST(0xff, DC_DISP_SD_HISTOGRAM_5_BIN_0_SHIFT) +#define DC_DISP_SD_HISTOGRAM_5_BIN_0_RANGE 7:0 +#define DC_DISP_SD_HISTOGRAM_5_BIN_0_WOFFSET 0x0 +#define DC_DISP_SD_HISTOGRAM_5_BIN_0_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_HISTOGRAM_5_BIN_0_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_SD_HISTOGRAM_5_BIN_0_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_HISTOGRAM_5_BIN_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_DISP_SD_HISTOGRAM_5_BIN_1_SHIFT _MK_SHIFT_CONST(8) +#define DC_DISP_SD_HISTOGRAM_5_BIN_1_FIELD _MK_FIELD_CONST(0xff, DC_DISP_SD_HISTOGRAM_5_BIN_1_SHIFT) +#define DC_DISP_SD_HISTOGRAM_5_BIN_1_RANGE 15:8 +#define DC_DISP_SD_HISTOGRAM_5_BIN_1_WOFFSET 0x0 +#define DC_DISP_SD_HISTOGRAM_5_BIN_1_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_HISTOGRAM_5_BIN_1_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_SD_HISTOGRAM_5_BIN_1_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_HISTOGRAM_5_BIN_1_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_DISP_SD_HISTOGRAM_5_BIN_2_SHIFT _MK_SHIFT_CONST(16) +#define DC_DISP_SD_HISTOGRAM_5_BIN_2_FIELD _MK_FIELD_CONST(0xff, DC_DISP_SD_HISTOGRAM_5_BIN_2_SHIFT) +#define DC_DISP_SD_HISTOGRAM_5_BIN_2_RANGE 23:16 +#define DC_DISP_SD_HISTOGRAM_5_BIN_2_WOFFSET 0x0 +#define DC_DISP_SD_HISTOGRAM_5_BIN_2_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_HISTOGRAM_5_BIN_2_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_SD_HISTOGRAM_5_BIN_2_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_HISTOGRAM_5_BIN_2_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_DISP_SD_HISTOGRAM_5_BIN_3_SHIFT _MK_SHIFT_CONST(24) +#define DC_DISP_SD_HISTOGRAM_5_BIN_3_FIELD _MK_FIELD_CONST(0xff, DC_DISP_SD_HISTOGRAM_5_BIN_3_SHIFT) +#define DC_DISP_SD_HISTOGRAM_5_BIN_3_RANGE 31:24 +#define DC_DISP_SD_HISTOGRAM_5_BIN_3_WOFFSET 0x0 +#define DC_DISP_SD_HISTOGRAM_5_BIN_3_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_HISTOGRAM_5_BIN_3_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_SD_HISTOGRAM_5_BIN_3_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_HISTOGRAM_5_BIN_3_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_DISP_SD_HISTOGRAM_6 +#define DC_DISP_SD_HISTOGRAM_6 _MK_ADDR_CONST(0x4d5) +#define DC_DISP_SD_HISTOGRAM_6_SECURE 0x0 +#define DC_DISP_SD_HISTOGRAM_6_WORD_COUNT 0x1 +#define DC_DISP_SD_HISTOGRAM_6_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_SD_HISTOGRAM_6_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_SD_HISTOGRAM_6_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_SD_HISTOGRAM_6_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_SD_HISTOGRAM_6_READ_MASK _MK_MASK_CONST(0xffffffff) +#define DC_DISP_SD_HISTOGRAM_6_WRITE_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_SD_HISTOGRAM_6_BIN_0_SHIFT _MK_SHIFT_CONST(0) +#define DC_DISP_SD_HISTOGRAM_6_BIN_0_FIELD _MK_FIELD_CONST(0xff, DC_DISP_SD_HISTOGRAM_6_BIN_0_SHIFT) +#define DC_DISP_SD_HISTOGRAM_6_BIN_0_RANGE 7:0 +#define DC_DISP_SD_HISTOGRAM_6_BIN_0_WOFFSET 0x0 +#define DC_DISP_SD_HISTOGRAM_6_BIN_0_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_HISTOGRAM_6_BIN_0_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_SD_HISTOGRAM_6_BIN_0_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_HISTOGRAM_6_BIN_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_DISP_SD_HISTOGRAM_6_BIN_1_SHIFT _MK_SHIFT_CONST(8) +#define DC_DISP_SD_HISTOGRAM_6_BIN_1_FIELD _MK_FIELD_CONST(0xff, DC_DISP_SD_HISTOGRAM_6_BIN_1_SHIFT) +#define DC_DISP_SD_HISTOGRAM_6_BIN_1_RANGE 15:8 +#define DC_DISP_SD_HISTOGRAM_6_BIN_1_WOFFSET 0x0 +#define DC_DISP_SD_HISTOGRAM_6_BIN_1_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_HISTOGRAM_6_BIN_1_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_SD_HISTOGRAM_6_BIN_1_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_HISTOGRAM_6_BIN_1_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_DISP_SD_HISTOGRAM_6_BIN_2_SHIFT _MK_SHIFT_CONST(16) +#define DC_DISP_SD_HISTOGRAM_6_BIN_2_FIELD _MK_FIELD_CONST(0xff, DC_DISP_SD_HISTOGRAM_6_BIN_2_SHIFT) +#define DC_DISP_SD_HISTOGRAM_6_BIN_2_RANGE 23:16 +#define DC_DISP_SD_HISTOGRAM_6_BIN_2_WOFFSET 0x0 +#define DC_DISP_SD_HISTOGRAM_6_BIN_2_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_HISTOGRAM_6_BIN_2_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_SD_HISTOGRAM_6_BIN_2_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_HISTOGRAM_6_BIN_2_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_DISP_SD_HISTOGRAM_6_BIN_3_SHIFT _MK_SHIFT_CONST(24) +#define DC_DISP_SD_HISTOGRAM_6_BIN_3_FIELD _MK_FIELD_CONST(0xff, DC_DISP_SD_HISTOGRAM_6_BIN_3_SHIFT) +#define DC_DISP_SD_HISTOGRAM_6_BIN_3_RANGE 31:24 +#define DC_DISP_SD_HISTOGRAM_6_BIN_3_WOFFSET 0x0 +#define DC_DISP_SD_HISTOGRAM_6_BIN_3_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_HISTOGRAM_6_BIN_3_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_SD_HISTOGRAM_6_BIN_3_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_HISTOGRAM_6_BIN_3_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_DISP_SD_HISTOGRAM_7 +#define DC_DISP_SD_HISTOGRAM_7 _MK_ADDR_CONST(0x4d6) +#define DC_DISP_SD_HISTOGRAM_7_SECURE 0x0 +#define DC_DISP_SD_HISTOGRAM_7_WORD_COUNT 0x1 +#define DC_DISP_SD_HISTOGRAM_7_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_SD_HISTOGRAM_7_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_SD_HISTOGRAM_7_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_SD_HISTOGRAM_7_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_SD_HISTOGRAM_7_READ_MASK _MK_MASK_CONST(0xffffffff) +#define DC_DISP_SD_HISTOGRAM_7_WRITE_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_SD_HISTOGRAM_7_BIN_0_SHIFT _MK_SHIFT_CONST(0) +#define DC_DISP_SD_HISTOGRAM_7_BIN_0_FIELD _MK_FIELD_CONST(0xff, DC_DISP_SD_HISTOGRAM_7_BIN_0_SHIFT) +#define DC_DISP_SD_HISTOGRAM_7_BIN_0_RANGE 7:0 +#define DC_DISP_SD_HISTOGRAM_7_BIN_0_WOFFSET 0x0 +#define DC_DISP_SD_HISTOGRAM_7_BIN_0_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_HISTOGRAM_7_BIN_0_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_SD_HISTOGRAM_7_BIN_0_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_HISTOGRAM_7_BIN_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_DISP_SD_HISTOGRAM_7_BIN_1_SHIFT _MK_SHIFT_CONST(8) +#define DC_DISP_SD_HISTOGRAM_7_BIN_1_FIELD _MK_FIELD_CONST(0xff, DC_DISP_SD_HISTOGRAM_7_BIN_1_SHIFT) +#define DC_DISP_SD_HISTOGRAM_7_BIN_1_RANGE 15:8 +#define DC_DISP_SD_HISTOGRAM_7_BIN_1_WOFFSET 0x0 +#define DC_DISP_SD_HISTOGRAM_7_BIN_1_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_HISTOGRAM_7_BIN_1_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_SD_HISTOGRAM_7_BIN_1_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_HISTOGRAM_7_BIN_1_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_DISP_SD_HISTOGRAM_7_BIN_2_SHIFT _MK_SHIFT_CONST(16) +#define DC_DISP_SD_HISTOGRAM_7_BIN_2_FIELD _MK_FIELD_CONST(0xff, DC_DISP_SD_HISTOGRAM_7_BIN_2_SHIFT) +#define DC_DISP_SD_HISTOGRAM_7_BIN_2_RANGE 23:16 +#define DC_DISP_SD_HISTOGRAM_7_BIN_2_WOFFSET 0x0 +#define DC_DISP_SD_HISTOGRAM_7_BIN_2_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_HISTOGRAM_7_BIN_2_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_SD_HISTOGRAM_7_BIN_2_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_HISTOGRAM_7_BIN_2_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_DISP_SD_HISTOGRAM_7_BIN_3_SHIFT _MK_SHIFT_CONST(24) +#define DC_DISP_SD_HISTOGRAM_7_BIN_3_FIELD _MK_FIELD_CONST(0xff, DC_DISP_SD_HISTOGRAM_7_BIN_3_SHIFT) +#define DC_DISP_SD_HISTOGRAM_7_BIN_3_RANGE 31:24 +#define DC_DISP_SD_HISTOGRAM_7_BIN_3_WOFFSET 0x0 +#define DC_DISP_SD_HISTOGRAM_7_BIN_3_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_HISTOGRAM_7_BIN_3_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_SD_HISTOGRAM_7_BIN_3_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_HISTOGRAM_7_BIN_3_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_DISP_SD_BL_PARAMETERS_0 +#define DC_DISP_SD_BL_PARAMETERS_0 _MK_ADDR_CONST(0x4d7) +#define DC_DISP_SD_BL_PARAMETERS_0_SECURE 0x0 +#define DC_DISP_SD_BL_PARAMETERS_0_WORD_COUNT 0x1 +#define DC_DISP_SD_BL_PARAMETERS_0_RESET_VAL _MK_MASK_CONST(0x400) +#define DC_DISP_SD_BL_PARAMETERS_0_RESET_MASK _MK_MASK_CONST(0xff07ff) +#define DC_DISP_SD_BL_PARAMETERS_0_SW_DEFAULT_VAL _MK_MASK_CONST(0xff0000) +#define DC_DISP_SD_BL_PARAMETERS_0_SW_DEFAULT_MASK _MK_MASK_CONST(0xff0000) +#define DC_DISP_SD_BL_PARAMETERS_0_READ_MASK _MK_MASK_CONST(0xff07ff) +#define DC_DISP_SD_BL_PARAMETERS_0_WRITE_MASK _MK_MASK_CONST(0xff07ff) +#define DC_DISP_SD_BL_PARAMETERS_0_TIME_CONSTANT_SHIFT _MK_SHIFT_CONST(0) +#define DC_DISP_SD_BL_PARAMETERS_0_TIME_CONSTANT_FIELD _MK_FIELD_CONST(0x7ff, DC_DISP_SD_BL_PARAMETERS_0_TIME_CONSTANT_SHIFT) +#define DC_DISP_SD_BL_PARAMETERS_0_TIME_CONSTANT_RANGE 10:0 +#define DC_DISP_SD_BL_PARAMETERS_0_TIME_CONSTANT_WOFFSET 0x0 +#define DC_DISP_SD_BL_PARAMETERS_0_TIME_CONSTANT_DEFAULT _MK_MASK_CONST(0x400) +#define DC_DISP_SD_BL_PARAMETERS_0_TIME_CONSTANT_DEFAULT_MASK _MK_MASK_CONST(0x7ff) +#define DC_DISP_SD_BL_PARAMETERS_0_TIME_CONSTANT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_BL_PARAMETERS_0_TIME_CONSTANT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_DISP_SD_BL_PARAMETERS_0_STEP_SHIFT _MK_SHIFT_CONST(16) +#define DC_DISP_SD_BL_PARAMETERS_0_STEP_FIELD _MK_FIELD_CONST(0xff, DC_DISP_SD_BL_PARAMETERS_0_STEP_SHIFT) +#define DC_DISP_SD_BL_PARAMETERS_0_STEP_RANGE 23:16 +#define DC_DISP_SD_BL_PARAMETERS_0_STEP_WOFFSET 0x0 +#define DC_DISP_SD_BL_PARAMETERS_0_STEP_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_BL_PARAMETERS_0_STEP_DEFAULT_MASK _MK_MASK_CONST(0xff) +#define DC_DISP_SD_BL_PARAMETERS_0_STEP_SW_DEFAULT _MK_MASK_CONST(0xff) +#define DC_DISP_SD_BL_PARAMETERS_0_STEP_SW_DEFAULT_MASK _MK_MASK_CONST(0xff) + + +// Register DC_DISP_SD_BL_TF_0 +#define DC_DISP_SD_BL_TF_0 _MK_ADDR_CONST(0x4d8) +#define DC_DISP_SD_BL_TF_0_SECURE 0x0 +#define DC_DISP_SD_BL_TF_0_WORD_COUNT 0x1 +#define DC_DISP_SD_BL_TF_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_SD_BL_TF_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_SD_BL_TF_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_SD_BL_TF_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_SD_BL_TF_0_READ_MASK _MK_MASK_CONST(0xffffffff) +#define DC_DISP_SD_BL_TF_0_WRITE_MASK _MK_MASK_CONST(0xffffffff) +#define DC_DISP_SD_BL_TF_0_POINT_0_SHIFT _MK_SHIFT_CONST(0) +#define DC_DISP_SD_BL_TF_0_POINT_0_FIELD _MK_FIELD_CONST(0xff, DC_DISP_SD_BL_TF_0_POINT_0_SHIFT) +#define DC_DISP_SD_BL_TF_0_POINT_0_RANGE 7:0 +#define DC_DISP_SD_BL_TF_0_POINT_0_WOFFSET 0x0 +#define DC_DISP_SD_BL_TF_0_POINT_0_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_BL_TF_0_POINT_0_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_SD_BL_TF_0_POINT_0_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_BL_TF_0_POINT_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_DISP_SD_BL_TF_0_POINT_1_SHIFT _MK_SHIFT_CONST(8) +#define DC_DISP_SD_BL_TF_0_POINT_1_FIELD _MK_FIELD_CONST(0xff, DC_DISP_SD_BL_TF_0_POINT_1_SHIFT) +#define DC_DISP_SD_BL_TF_0_POINT_1_RANGE 15:8 +#define DC_DISP_SD_BL_TF_0_POINT_1_WOFFSET 0x0 +#define DC_DISP_SD_BL_TF_0_POINT_1_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_BL_TF_0_POINT_1_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_SD_BL_TF_0_POINT_1_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_BL_TF_0_POINT_1_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_DISP_SD_BL_TF_0_POINT_2_SHIFT _MK_SHIFT_CONST(16) +#define DC_DISP_SD_BL_TF_0_POINT_2_FIELD _MK_FIELD_CONST(0xff, DC_DISP_SD_BL_TF_0_POINT_2_SHIFT) +#define DC_DISP_SD_BL_TF_0_POINT_2_RANGE 23:16 +#define DC_DISP_SD_BL_TF_0_POINT_2_WOFFSET 0x0 +#define DC_DISP_SD_BL_TF_0_POINT_2_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_BL_TF_0_POINT_2_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_SD_BL_TF_0_POINT_2_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_BL_TF_0_POINT_2_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_DISP_SD_BL_TF_0_POINT_3_SHIFT _MK_SHIFT_CONST(24) +#define DC_DISP_SD_BL_TF_0_POINT_3_FIELD _MK_FIELD_CONST(0xff, DC_DISP_SD_BL_TF_0_POINT_3_SHIFT) +#define DC_DISP_SD_BL_TF_0_POINT_3_RANGE 31:24 +#define DC_DISP_SD_BL_TF_0_POINT_3_WOFFSET 0x0 +#define DC_DISP_SD_BL_TF_0_POINT_3_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_BL_TF_0_POINT_3_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_SD_BL_TF_0_POINT_3_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_BL_TF_0_POINT_3_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_DISP_SD_BL_TF +#define DC_DISP_SD_BL_TF _MK_ADDR_CONST(0x4d8) +#define DC_DISP_SD_BL_TF_SECURE 0x0 +#define DC_DISP_SD_BL_TF_WORD_COUNT 0x1 +#define DC_DISP_SD_BL_TF_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_SD_BL_TF_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_SD_BL_TF_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_SD_BL_TF_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_SD_BL_TF_READ_MASK _MK_MASK_CONST(0xffffffff) +#define DC_DISP_SD_BL_TF_WRITE_MASK _MK_MASK_CONST(0xffffffff) +#define DC_DISP_SD_BL_TF_POINT_0_SHIFT _MK_SHIFT_CONST(0) +#define DC_DISP_SD_BL_TF_POINT_0_FIELD _MK_FIELD_CONST(0xff, DC_DISP_SD_BL_TF_POINT_0_SHIFT) +#define DC_DISP_SD_BL_TF_POINT_0_RANGE 7:0 +#define DC_DISP_SD_BL_TF_POINT_0_WOFFSET 0x0 +#define DC_DISP_SD_BL_TF_POINT_0_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_BL_TF_POINT_0_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_SD_BL_TF_POINT_0_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_BL_TF_POINT_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_DISP_SD_BL_TF_POINT_1_SHIFT _MK_SHIFT_CONST(8) +#define DC_DISP_SD_BL_TF_POINT_1_FIELD _MK_FIELD_CONST(0xff, DC_DISP_SD_BL_TF_POINT_1_SHIFT) +#define DC_DISP_SD_BL_TF_POINT_1_RANGE 15:8 +#define DC_DISP_SD_BL_TF_POINT_1_WOFFSET 0x0 +#define DC_DISP_SD_BL_TF_POINT_1_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_BL_TF_POINT_1_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_SD_BL_TF_POINT_1_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_BL_TF_POINT_1_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_DISP_SD_BL_TF_POINT_2_SHIFT _MK_SHIFT_CONST(16) +#define DC_DISP_SD_BL_TF_POINT_2_FIELD _MK_FIELD_CONST(0xff, DC_DISP_SD_BL_TF_POINT_2_SHIFT) +#define DC_DISP_SD_BL_TF_POINT_2_RANGE 23:16 +#define DC_DISP_SD_BL_TF_POINT_2_WOFFSET 0x0 +#define DC_DISP_SD_BL_TF_POINT_2_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_BL_TF_POINT_2_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_SD_BL_TF_POINT_2_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_BL_TF_POINT_2_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_DISP_SD_BL_TF_POINT_3_SHIFT _MK_SHIFT_CONST(24) +#define DC_DISP_SD_BL_TF_POINT_3_FIELD _MK_FIELD_CONST(0xff, DC_DISP_SD_BL_TF_POINT_3_SHIFT) +#define DC_DISP_SD_BL_TF_POINT_3_RANGE 31:24 +#define DC_DISP_SD_BL_TF_POINT_3_WOFFSET 0x0 +#define DC_DISP_SD_BL_TF_POINT_3_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_BL_TF_POINT_3_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_SD_BL_TF_POINT_3_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_BL_TF_POINT_3_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_DISP_SD_BL_TF_1 +#define DC_DISP_SD_BL_TF_1 _MK_ADDR_CONST(0x4d9) +#define DC_DISP_SD_BL_TF_1_SECURE 0x0 +#define DC_DISP_SD_BL_TF_1_WORD_COUNT 0x1 +#define DC_DISP_SD_BL_TF_1_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_SD_BL_TF_1_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_SD_BL_TF_1_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_SD_BL_TF_1_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_SD_BL_TF_1_READ_MASK _MK_MASK_CONST(0xffffffff) +#define DC_DISP_SD_BL_TF_1_WRITE_MASK _MK_MASK_CONST(0xffffffff) +#define DC_DISP_SD_BL_TF_1_POINT_0_SHIFT _MK_SHIFT_CONST(0) +#define DC_DISP_SD_BL_TF_1_POINT_0_FIELD _MK_FIELD_CONST(0xff, DC_DISP_SD_BL_TF_1_POINT_0_SHIFT) +#define DC_DISP_SD_BL_TF_1_POINT_0_RANGE 7:0 +#define DC_DISP_SD_BL_TF_1_POINT_0_WOFFSET 0x0 +#define DC_DISP_SD_BL_TF_1_POINT_0_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_BL_TF_1_POINT_0_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_SD_BL_TF_1_POINT_0_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_BL_TF_1_POINT_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_DISP_SD_BL_TF_1_POINT_1_SHIFT _MK_SHIFT_CONST(8) +#define DC_DISP_SD_BL_TF_1_POINT_1_FIELD _MK_FIELD_CONST(0xff, DC_DISP_SD_BL_TF_1_POINT_1_SHIFT) +#define DC_DISP_SD_BL_TF_1_POINT_1_RANGE 15:8 +#define DC_DISP_SD_BL_TF_1_POINT_1_WOFFSET 0x0 +#define DC_DISP_SD_BL_TF_1_POINT_1_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_BL_TF_1_POINT_1_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_SD_BL_TF_1_POINT_1_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_BL_TF_1_POINT_1_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_DISP_SD_BL_TF_1_POINT_2_SHIFT _MK_SHIFT_CONST(16) +#define DC_DISP_SD_BL_TF_1_POINT_2_FIELD _MK_FIELD_CONST(0xff, DC_DISP_SD_BL_TF_1_POINT_2_SHIFT) +#define DC_DISP_SD_BL_TF_1_POINT_2_RANGE 23:16 +#define DC_DISP_SD_BL_TF_1_POINT_2_WOFFSET 0x0 +#define DC_DISP_SD_BL_TF_1_POINT_2_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_BL_TF_1_POINT_2_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_SD_BL_TF_1_POINT_2_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_BL_TF_1_POINT_2_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_DISP_SD_BL_TF_1_POINT_3_SHIFT _MK_SHIFT_CONST(24) +#define DC_DISP_SD_BL_TF_1_POINT_3_FIELD _MK_FIELD_CONST(0xff, DC_DISP_SD_BL_TF_1_POINT_3_SHIFT) +#define DC_DISP_SD_BL_TF_1_POINT_3_RANGE 31:24 +#define DC_DISP_SD_BL_TF_1_POINT_3_WOFFSET 0x0 +#define DC_DISP_SD_BL_TF_1_POINT_3_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_BL_TF_1_POINT_3_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_SD_BL_TF_1_POINT_3_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_BL_TF_1_POINT_3_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_DISP_SD_BL_TF_2 +#define DC_DISP_SD_BL_TF_2 _MK_ADDR_CONST(0x4da) +#define DC_DISP_SD_BL_TF_2_SECURE 0x0 +#define DC_DISP_SD_BL_TF_2_WORD_COUNT 0x1 +#define DC_DISP_SD_BL_TF_2_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_SD_BL_TF_2_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_SD_BL_TF_2_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_SD_BL_TF_2_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_SD_BL_TF_2_READ_MASK _MK_MASK_CONST(0xffffffff) +#define DC_DISP_SD_BL_TF_2_WRITE_MASK _MK_MASK_CONST(0xffffffff) +#define DC_DISP_SD_BL_TF_2_POINT_0_SHIFT _MK_SHIFT_CONST(0) +#define DC_DISP_SD_BL_TF_2_POINT_0_FIELD _MK_FIELD_CONST(0xff, DC_DISP_SD_BL_TF_2_POINT_0_SHIFT) +#define DC_DISP_SD_BL_TF_2_POINT_0_RANGE 7:0 +#define DC_DISP_SD_BL_TF_2_POINT_0_WOFFSET 0x0 +#define DC_DISP_SD_BL_TF_2_POINT_0_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_BL_TF_2_POINT_0_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_SD_BL_TF_2_POINT_0_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_BL_TF_2_POINT_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_DISP_SD_BL_TF_2_POINT_1_SHIFT _MK_SHIFT_CONST(8) +#define DC_DISP_SD_BL_TF_2_POINT_1_FIELD _MK_FIELD_CONST(0xff, DC_DISP_SD_BL_TF_2_POINT_1_SHIFT) +#define DC_DISP_SD_BL_TF_2_POINT_1_RANGE 15:8 +#define DC_DISP_SD_BL_TF_2_POINT_1_WOFFSET 0x0 +#define DC_DISP_SD_BL_TF_2_POINT_1_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_BL_TF_2_POINT_1_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_SD_BL_TF_2_POINT_1_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_BL_TF_2_POINT_1_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_DISP_SD_BL_TF_2_POINT_2_SHIFT _MK_SHIFT_CONST(16) +#define DC_DISP_SD_BL_TF_2_POINT_2_FIELD _MK_FIELD_CONST(0xff, DC_DISP_SD_BL_TF_2_POINT_2_SHIFT) +#define DC_DISP_SD_BL_TF_2_POINT_2_RANGE 23:16 +#define DC_DISP_SD_BL_TF_2_POINT_2_WOFFSET 0x0 +#define DC_DISP_SD_BL_TF_2_POINT_2_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_BL_TF_2_POINT_2_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_SD_BL_TF_2_POINT_2_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_BL_TF_2_POINT_2_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_DISP_SD_BL_TF_2_POINT_3_SHIFT _MK_SHIFT_CONST(24) +#define DC_DISP_SD_BL_TF_2_POINT_3_FIELD _MK_FIELD_CONST(0xff, DC_DISP_SD_BL_TF_2_POINT_3_SHIFT) +#define DC_DISP_SD_BL_TF_2_POINT_3_RANGE 31:24 +#define DC_DISP_SD_BL_TF_2_POINT_3_WOFFSET 0x0 +#define DC_DISP_SD_BL_TF_2_POINT_3_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_BL_TF_2_POINT_3_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_SD_BL_TF_2_POINT_3_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_BL_TF_2_POINT_3_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_DISP_SD_BL_TF_3 +#define DC_DISP_SD_BL_TF_3 _MK_ADDR_CONST(0x4db) +#define DC_DISP_SD_BL_TF_3_SECURE 0x0 +#define DC_DISP_SD_BL_TF_3_WORD_COUNT 0x1 +#define DC_DISP_SD_BL_TF_3_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_SD_BL_TF_3_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_SD_BL_TF_3_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_SD_BL_TF_3_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_SD_BL_TF_3_READ_MASK _MK_MASK_CONST(0xffffffff) +#define DC_DISP_SD_BL_TF_3_WRITE_MASK _MK_MASK_CONST(0xffffffff) +#define DC_DISP_SD_BL_TF_3_POINT_0_SHIFT _MK_SHIFT_CONST(0) +#define DC_DISP_SD_BL_TF_3_POINT_0_FIELD _MK_FIELD_CONST(0xff, DC_DISP_SD_BL_TF_3_POINT_0_SHIFT) +#define DC_DISP_SD_BL_TF_3_POINT_0_RANGE 7:0 +#define DC_DISP_SD_BL_TF_3_POINT_0_WOFFSET 0x0 +#define DC_DISP_SD_BL_TF_3_POINT_0_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_BL_TF_3_POINT_0_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_SD_BL_TF_3_POINT_0_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_BL_TF_3_POINT_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_DISP_SD_BL_TF_3_POINT_1_SHIFT _MK_SHIFT_CONST(8) +#define DC_DISP_SD_BL_TF_3_POINT_1_FIELD _MK_FIELD_CONST(0xff, DC_DISP_SD_BL_TF_3_POINT_1_SHIFT) +#define DC_DISP_SD_BL_TF_3_POINT_1_RANGE 15:8 +#define DC_DISP_SD_BL_TF_3_POINT_1_WOFFSET 0x0 +#define DC_DISP_SD_BL_TF_3_POINT_1_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_BL_TF_3_POINT_1_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_SD_BL_TF_3_POINT_1_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_BL_TF_3_POINT_1_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_DISP_SD_BL_TF_3_POINT_2_SHIFT _MK_SHIFT_CONST(16) +#define DC_DISP_SD_BL_TF_3_POINT_2_FIELD _MK_FIELD_CONST(0xff, DC_DISP_SD_BL_TF_3_POINT_2_SHIFT) +#define DC_DISP_SD_BL_TF_3_POINT_2_RANGE 23:16 +#define DC_DISP_SD_BL_TF_3_POINT_2_WOFFSET 0x0 +#define DC_DISP_SD_BL_TF_3_POINT_2_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_BL_TF_3_POINT_2_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_SD_BL_TF_3_POINT_2_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_BL_TF_3_POINT_2_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_DISP_SD_BL_TF_3_POINT_3_SHIFT _MK_SHIFT_CONST(24) +#define DC_DISP_SD_BL_TF_3_POINT_3_FIELD _MK_FIELD_CONST(0xff, DC_DISP_SD_BL_TF_3_POINT_3_SHIFT) +#define DC_DISP_SD_BL_TF_3_POINT_3_RANGE 31:24 +#define DC_DISP_SD_BL_TF_3_POINT_3_WOFFSET 0x0 +#define DC_DISP_SD_BL_TF_3_POINT_3_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_BL_TF_3_POINT_3_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_SD_BL_TF_3_POINT_3_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_BL_TF_3_POINT_3_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_DISP_SD_BL_CONTROL_0 +#define DC_DISP_SD_BL_CONTROL_0 _MK_ADDR_CONST(0x4dc) +#define DC_DISP_SD_BL_CONTROL_0_SECURE 0x0 +#define DC_DISP_SD_BL_CONTROL_0_WORD_COUNT 0x1 +#define DC_DISP_SD_BL_CONTROL_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_SD_BL_CONTROL_0_RESET_MASK _MK_MASK_CONST(0x3) +#define DC_DISP_SD_BL_CONTROL_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_SD_BL_CONTROL_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_SD_BL_CONTROL_0_READ_MASK _MK_MASK_CONST(0xff03) +#define DC_DISP_SD_BL_CONTROL_0_WRITE_MASK _MK_MASK_CONST(0x3) +#define DC_DISP_SD_BL_CONTROL_0_BL_MODE_SHIFT _MK_SHIFT_CONST(0) +#define DC_DISP_SD_BL_CONTROL_0_BL_MODE_FIELD _MK_FIELD_CONST(0x3, DC_DISP_SD_BL_CONTROL_0_BL_MODE_SHIFT) +#define DC_DISP_SD_BL_CONTROL_0_BL_MODE_RANGE 1:0 +#define DC_DISP_SD_BL_CONTROL_0_BL_MODE_WOFFSET 0x0 +#define DC_DISP_SD_BL_CONTROL_0_BL_MODE_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_BL_CONTROL_0_BL_MODE_DEFAULT_MASK _MK_MASK_CONST(0x3) +#define DC_DISP_SD_BL_CONTROL_0_BL_MODE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_BL_CONTROL_0_BL_MODE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_SD_BL_CONTROL_0_BL_MODE_MANUAL _MK_ENUM_CONST(0) +#define DC_DISP_SD_BL_CONTROL_0_BL_MODE_PWM_AUTO _MK_ENUM_CONST(1) + +#define DC_DISP_SD_BL_CONTROL_0_BRIGHTNESS_SHIFT _MK_SHIFT_CONST(8) +#define DC_DISP_SD_BL_CONTROL_0_BRIGHTNESS_FIELD _MK_FIELD_CONST(0xff, DC_DISP_SD_BL_CONTROL_0_BRIGHTNESS_SHIFT) +#define DC_DISP_SD_BL_CONTROL_0_BRIGHTNESS_RANGE 15:8 +#define DC_DISP_SD_BL_CONTROL_0_BRIGHTNESS_WOFFSET 0x0 +#define DC_DISP_SD_BL_CONTROL_0_BRIGHTNESS_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_BL_CONTROL_0_BRIGHTNESS_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_SD_BL_CONTROL_0_BRIGHTNESS_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_BL_CONTROL_0_BRIGHTNESS_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define NV_DISPLAY_MAN_K_SIZE 10 + +// Register DC_DISP_SD_HW_K_VALUES_0 +#define DC_DISP_SD_HW_K_VALUES_0 _MK_ADDR_CONST(0x4dd) +#define DC_DISP_SD_HW_K_VALUES_0_SECURE 0x0 +#define DC_DISP_SD_HW_K_VALUES_0_WORD_COUNT 0x1 +#define DC_DISP_SD_HW_K_VALUES_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_SD_HW_K_VALUES_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_SD_HW_K_VALUES_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_SD_HW_K_VALUES_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_SD_HW_K_VALUES_0_READ_MASK _MK_MASK_CONST(0x3fffffff) +#define DC_DISP_SD_HW_K_VALUES_0_WRITE_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_SD_HW_K_VALUES_0_HW_K_RED_SHIFT _MK_SHIFT_CONST(0) +#define DC_DISP_SD_HW_K_VALUES_0_HW_K_RED_FIELD _MK_FIELD_CONST(0x3ff, DC_DISP_SD_HW_K_VALUES_0_HW_K_RED_SHIFT) +#define DC_DISP_SD_HW_K_VALUES_0_HW_K_RED_RANGE 9:0 +#define DC_DISP_SD_HW_K_VALUES_0_HW_K_RED_WOFFSET 0x0 +#define DC_DISP_SD_HW_K_VALUES_0_HW_K_RED_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_HW_K_VALUES_0_HW_K_RED_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_SD_HW_K_VALUES_0_HW_K_RED_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_HW_K_VALUES_0_HW_K_RED_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_DISP_SD_HW_K_VALUES_0_HW_K_GREEN_SHIFT _MK_SHIFT_CONST(10) +#define DC_DISP_SD_HW_K_VALUES_0_HW_K_GREEN_FIELD _MK_FIELD_CONST(0x3ff, DC_DISP_SD_HW_K_VALUES_0_HW_K_GREEN_SHIFT) +#define DC_DISP_SD_HW_K_VALUES_0_HW_K_GREEN_RANGE 19:10 +#define DC_DISP_SD_HW_K_VALUES_0_HW_K_GREEN_WOFFSET 0x0 +#define DC_DISP_SD_HW_K_VALUES_0_HW_K_GREEN_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_HW_K_VALUES_0_HW_K_GREEN_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_SD_HW_K_VALUES_0_HW_K_GREEN_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_HW_K_VALUES_0_HW_K_GREEN_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_DISP_SD_HW_K_VALUES_0_HW_K_BLUE_SHIFT _MK_SHIFT_CONST(20) +#define DC_DISP_SD_HW_K_VALUES_0_HW_K_BLUE_FIELD _MK_FIELD_CONST(0x3ff, DC_DISP_SD_HW_K_VALUES_0_HW_K_BLUE_SHIFT) +#define DC_DISP_SD_HW_K_VALUES_0_HW_K_BLUE_RANGE 29:20 +#define DC_DISP_SD_HW_K_VALUES_0_HW_K_BLUE_WOFFSET 0x0 +#define DC_DISP_SD_HW_K_VALUES_0_HW_K_BLUE_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_HW_K_VALUES_0_HW_K_BLUE_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_SD_HW_K_VALUES_0_HW_K_BLUE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_HW_K_VALUES_0_HW_K_BLUE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_DISP_SD_MAN_K_VALUES_0 +#define DC_DISP_SD_MAN_K_VALUES_0 _MK_ADDR_CONST(0x4de) +#define DC_DISP_SD_MAN_K_VALUES_0_SECURE 0x0 +#define DC_DISP_SD_MAN_K_VALUES_0_WORD_COUNT 0x1 +#define DC_DISP_SD_MAN_K_VALUES_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_SD_MAN_K_VALUES_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_SD_MAN_K_VALUES_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_SD_MAN_K_VALUES_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_SD_MAN_K_VALUES_0_READ_MASK _MK_MASK_CONST(0x3fffffff) +#define DC_DISP_SD_MAN_K_VALUES_0_WRITE_MASK _MK_MASK_CONST(0x3fffffff) +#define DC_DISP_SD_MAN_K_VALUES_0_MAN_K_RED_SHIFT _MK_SHIFT_CONST(0) +#define DC_DISP_SD_MAN_K_VALUES_0_MAN_K_RED_FIELD _MK_FIELD_CONST(0x3ff, DC_DISP_SD_MAN_K_VALUES_0_MAN_K_RED_SHIFT) +#define DC_DISP_SD_MAN_K_VALUES_0_MAN_K_RED_RANGE 9:0 +#define DC_DISP_SD_MAN_K_VALUES_0_MAN_K_RED_WOFFSET 0x0 +#define DC_DISP_SD_MAN_K_VALUES_0_MAN_K_RED_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_MAN_K_VALUES_0_MAN_K_RED_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_SD_MAN_K_VALUES_0_MAN_K_RED_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_MAN_K_VALUES_0_MAN_K_RED_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_DISP_SD_MAN_K_VALUES_0_MAN_K_GREEN_SHIFT _MK_SHIFT_CONST(10) +#define DC_DISP_SD_MAN_K_VALUES_0_MAN_K_GREEN_FIELD _MK_FIELD_CONST(0x3ff, DC_DISP_SD_MAN_K_VALUES_0_MAN_K_GREEN_SHIFT) +#define DC_DISP_SD_MAN_K_VALUES_0_MAN_K_GREEN_RANGE 19:10 +#define DC_DISP_SD_MAN_K_VALUES_0_MAN_K_GREEN_WOFFSET 0x0 +#define DC_DISP_SD_MAN_K_VALUES_0_MAN_K_GREEN_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_MAN_K_VALUES_0_MAN_K_GREEN_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_SD_MAN_K_VALUES_0_MAN_K_GREEN_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_MAN_K_VALUES_0_MAN_K_GREEN_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_DISP_SD_MAN_K_VALUES_0_MAN_K_BLUE_SHIFT _MK_SHIFT_CONST(20) +#define DC_DISP_SD_MAN_K_VALUES_0_MAN_K_BLUE_FIELD _MK_FIELD_CONST(0x3ff, DC_DISP_SD_MAN_K_VALUES_0_MAN_K_BLUE_SHIFT) +#define DC_DISP_SD_MAN_K_VALUES_0_MAN_K_BLUE_RANGE 29:20 +#define DC_DISP_SD_MAN_K_VALUES_0_MAN_K_BLUE_WOFFSET 0x0 +#define DC_DISP_SD_MAN_K_VALUES_0_MAN_K_BLUE_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_MAN_K_VALUES_0_MAN_K_BLUE_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_SD_MAN_K_VALUES_0_MAN_K_BLUE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_MAN_K_VALUES_0_MAN_K_BLUE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_DISP_SD_K_LIMIT_0 +#define DC_DISP_SD_K_LIMIT_0 _MK_ADDR_CONST(0x4df) +#define DC_DISP_SD_K_LIMIT_0_SECURE 0x0 +#define DC_DISP_SD_K_LIMIT_0_WORD_COUNT 0x1 +#define DC_DISP_SD_K_LIMIT_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_SD_K_LIMIT_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_SD_K_LIMIT_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_SD_K_LIMIT_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_SD_K_LIMIT_0_READ_MASK _MK_MASK_CONST(0x3ff) +#define DC_DISP_SD_K_LIMIT_0_WRITE_MASK _MK_MASK_CONST(0x3ff) +#define DC_DISP_SD_K_LIMIT_0_K_LIMIT_SHIFT _MK_SHIFT_CONST(0) +#define DC_DISP_SD_K_LIMIT_0_K_LIMIT_FIELD _MK_FIELD_CONST(0x3ff, DC_DISP_SD_K_LIMIT_0_K_LIMIT_SHIFT) +#define DC_DISP_SD_K_LIMIT_0_K_LIMIT_RANGE 9:0 +#define DC_DISP_SD_K_LIMIT_0_K_LIMIT_WOFFSET 0x0 +#define DC_DISP_SD_K_LIMIT_0_K_LIMIT_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_K_LIMIT_0_K_LIMIT_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_SD_K_LIMIT_0_K_LIMIT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_K_LIMIT_0_K_LIMIT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_DISP_SD_WINDOW_POSITION_0 +#define DC_DISP_SD_WINDOW_POSITION_0 _MK_ADDR_CONST(0x4e0) +#define DC_DISP_SD_WINDOW_POSITION_0_SECURE 0x0 +#define DC_DISP_SD_WINDOW_POSITION_0_WORD_COUNT 0x1 +#define DC_DISP_SD_WINDOW_POSITION_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_SD_WINDOW_POSITION_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_SD_WINDOW_POSITION_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_SD_WINDOW_POSITION_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_SD_WINDOW_POSITION_0_READ_MASK _MK_MASK_CONST(0x1fff1fff) +#define DC_DISP_SD_WINDOW_POSITION_0_WRITE_MASK _MK_MASK_CONST(0x1fff1fff) +#define DC_DISP_SD_WINDOW_POSITION_0_SD_WIN_H_POSITION_SHIFT _MK_SHIFT_CONST(0) +#define DC_DISP_SD_WINDOW_POSITION_0_SD_WIN_H_POSITION_FIELD _MK_FIELD_CONST(0x1fff, DC_DISP_SD_WINDOW_POSITION_0_SD_WIN_H_POSITION_SHIFT) +#define DC_DISP_SD_WINDOW_POSITION_0_SD_WIN_H_POSITION_RANGE 12:0 +#define DC_DISP_SD_WINDOW_POSITION_0_SD_WIN_H_POSITION_WOFFSET 0x0 +#define DC_DISP_SD_WINDOW_POSITION_0_SD_WIN_H_POSITION_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_WINDOW_POSITION_0_SD_WIN_H_POSITION_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_SD_WINDOW_POSITION_0_SD_WIN_H_POSITION_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_WINDOW_POSITION_0_SD_WIN_H_POSITION_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_DISP_SD_WINDOW_POSITION_0_SD_WIN_V_POSITION_SHIFT _MK_SHIFT_CONST(16) +#define DC_DISP_SD_WINDOW_POSITION_0_SD_WIN_V_POSITION_FIELD _MK_FIELD_CONST(0x1fff, DC_DISP_SD_WINDOW_POSITION_0_SD_WIN_V_POSITION_SHIFT) +#define DC_DISP_SD_WINDOW_POSITION_0_SD_WIN_V_POSITION_RANGE 28:16 +#define DC_DISP_SD_WINDOW_POSITION_0_SD_WIN_V_POSITION_WOFFSET 0x0 +#define DC_DISP_SD_WINDOW_POSITION_0_SD_WIN_V_POSITION_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_WINDOW_POSITION_0_SD_WIN_V_POSITION_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_SD_WINDOW_POSITION_0_SD_WIN_V_POSITION_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_WINDOW_POSITION_0_SD_WIN_V_POSITION_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_DISP_SD_WINDOW_SIZE_0 +#define DC_DISP_SD_WINDOW_SIZE_0 _MK_ADDR_CONST(0x4e1) +#define DC_DISP_SD_WINDOW_SIZE_0_SECURE 0x0 +#define DC_DISP_SD_WINDOW_SIZE_0_WORD_COUNT 0x1 +#define DC_DISP_SD_WINDOW_SIZE_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_SD_WINDOW_SIZE_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_SD_WINDOW_SIZE_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_SD_WINDOW_SIZE_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_SD_WINDOW_SIZE_0_READ_MASK _MK_MASK_CONST(0x1fff1fff) +#define DC_DISP_SD_WINDOW_SIZE_0_WRITE_MASK _MK_MASK_CONST(0x1fff1fff) +#define DC_DISP_SD_WINDOW_SIZE_0_SD_WIN_H_SIZE_SHIFT _MK_SHIFT_CONST(0) +#define DC_DISP_SD_WINDOW_SIZE_0_SD_WIN_H_SIZE_FIELD _MK_FIELD_CONST(0x1fff, DC_DISP_SD_WINDOW_SIZE_0_SD_WIN_H_SIZE_SHIFT) +#define DC_DISP_SD_WINDOW_SIZE_0_SD_WIN_H_SIZE_RANGE 12:0 +#define DC_DISP_SD_WINDOW_SIZE_0_SD_WIN_H_SIZE_WOFFSET 0x0 +#define DC_DISP_SD_WINDOW_SIZE_0_SD_WIN_H_SIZE_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_WINDOW_SIZE_0_SD_WIN_H_SIZE_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_SD_WINDOW_SIZE_0_SD_WIN_H_SIZE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_WINDOW_SIZE_0_SD_WIN_H_SIZE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_DISP_SD_WINDOW_SIZE_0_SD_WIN_V_SIZE_SHIFT _MK_SHIFT_CONST(16) +#define DC_DISP_SD_WINDOW_SIZE_0_SD_WIN_V_SIZE_FIELD _MK_FIELD_CONST(0x1fff, DC_DISP_SD_WINDOW_SIZE_0_SD_WIN_V_SIZE_SHIFT) +#define DC_DISP_SD_WINDOW_SIZE_0_SD_WIN_V_SIZE_RANGE 28:16 +#define DC_DISP_SD_WINDOW_SIZE_0_SD_WIN_V_SIZE_WOFFSET 0x0 +#define DC_DISP_SD_WINDOW_SIZE_0_SD_WIN_V_SIZE_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_WINDOW_SIZE_0_SD_WIN_V_SIZE_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_SD_WINDOW_SIZE_0_SD_WIN_V_SIZE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_WINDOW_SIZE_0_SD_WIN_V_SIZE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_DISP_SD_SOFT_CLIPPING_0 +#define DC_DISP_SD_SOFT_CLIPPING_0 _MK_ADDR_CONST(0x4e2) +#define DC_DISP_SD_SOFT_CLIPPING_0_SECURE 0x0 +#define DC_DISP_SD_SOFT_CLIPPING_0_WORD_COUNT 0x1 +#define DC_DISP_SD_SOFT_CLIPPING_0_RESET_VAL _MK_MASK_CONST(0x2000080) +#define DC_DISP_SD_SOFT_CLIPPING_0_RESET_MASK _MK_MASK_CONST(0xffff00ff) +#define DC_DISP_SD_SOFT_CLIPPING_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_SD_SOFT_CLIPPING_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_SD_SOFT_CLIPPING_0_READ_MASK _MK_MASK_CONST(0xffff00ff) +#define DC_DISP_SD_SOFT_CLIPPING_0_WRITE_MASK _MK_MASK_CONST(0xffff00ff) +#define DC_DISP_SD_SOFT_CLIPPING_0_SOFT_CLIPPING_THRESHOLD_SHIFT _MK_SHIFT_CONST(0) +#define DC_DISP_SD_SOFT_CLIPPING_0_SOFT_CLIPPING_THRESHOLD_FIELD _MK_FIELD_CONST(0xff, DC_DISP_SD_SOFT_CLIPPING_0_SOFT_CLIPPING_THRESHOLD_SHIFT) +#define DC_DISP_SD_SOFT_CLIPPING_0_SOFT_CLIPPING_THRESHOLD_RANGE 7:0 +#define DC_DISP_SD_SOFT_CLIPPING_0_SOFT_CLIPPING_THRESHOLD_WOFFSET 0x0 +#define DC_DISP_SD_SOFT_CLIPPING_0_SOFT_CLIPPING_THRESHOLD_DEFAULT _MK_MASK_CONST(0x80) +#define DC_DISP_SD_SOFT_CLIPPING_0_SOFT_CLIPPING_THRESHOLD_DEFAULT_MASK _MK_MASK_CONST(0xff) +#define DC_DISP_SD_SOFT_CLIPPING_0_SOFT_CLIPPING_THRESHOLD_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_SOFT_CLIPPING_0_SOFT_CLIPPING_THRESHOLD_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_DISP_SD_SOFT_CLIPPING_0_SOFT_CLIPPING_RECIP_SHIFT _MK_SHIFT_CONST(16) +#define DC_DISP_SD_SOFT_CLIPPING_0_SOFT_CLIPPING_RECIP_FIELD _MK_FIELD_CONST(0xffff, DC_DISP_SD_SOFT_CLIPPING_0_SOFT_CLIPPING_RECIP_SHIFT) +#define DC_DISP_SD_SOFT_CLIPPING_0_SOFT_CLIPPING_RECIP_RANGE 31:16 +#define DC_DISP_SD_SOFT_CLIPPING_0_SOFT_CLIPPING_RECIP_WOFFSET 0x0 +#define DC_DISP_SD_SOFT_CLIPPING_0_SOFT_CLIPPING_RECIP_DEFAULT _MK_MASK_CONST(0x200) +#define DC_DISP_SD_SOFT_CLIPPING_0_SOFT_CLIPPING_RECIP_DEFAULT_MASK _MK_MASK_CONST(0xffff) +#define DC_DISP_SD_SOFT_CLIPPING_0_SOFT_CLIPPING_RECIP_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_SOFT_CLIPPING_0_SOFT_CLIPPING_RECIP_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_DISP_SD_SMOOTH_K_0 +#define DC_DISP_SD_SMOOTH_K_0 _MK_ADDR_CONST(0x4e3) +#define DC_DISP_SD_SMOOTH_K_0_SECURE 0x0 +#define DC_DISP_SD_SMOOTH_K_0_WORD_COUNT 0x1 +#define DC_DISP_SD_SMOOTH_K_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_SD_SMOOTH_K_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_SD_SMOOTH_K_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_SD_SMOOTH_K_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_SD_SMOOTH_K_0_READ_MASK _MK_MASK_CONST(0x3fff) +#define DC_DISP_SD_SMOOTH_K_0_WRITE_MASK _MK_MASK_CONST(0x3fff) +#define DC_DISP_SD_SMOOTH_K_0_SMOOTH_K_INCR_SHIFT _MK_SHIFT_CONST(0) +#define DC_DISP_SD_SMOOTH_K_0_SMOOTH_K_INCR_FIELD _MK_FIELD_CONST(0x3fff, DC_DISP_SD_SMOOTH_K_0_SMOOTH_K_INCR_SHIFT) +#define DC_DISP_SD_SMOOTH_K_0_SMOOTH_K_INCR_RANGE 13:0 +#define DC_DISP_SD_SMOOTH_K_0_SMOOTH_K_INCR_WOFFSET 0x0 +#define DC_DISP_SD_SMOOTH_K_0_SMOOTH_K_INCR_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_SMOOTH_K_0_SMOOTH_K_INCR_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_SD_SMOOTH_K_0_SMOOTH_K_INCR_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_SD_SMOOTH_K_0_SMOOTH_K_INCR_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_DISP_BLEND_BACKGROUND_COLOR_0 +#define DC_DISP_BLEND_BACKGROUND_COLOR_0 _MK_ADDR_CONST(0x4e4) +#define DC_DISP_BLEND_BACKGROUND_COLOR_0_SECURE 0x0 +#define DC_DISP_BLEND_BACKGROUND_COLOR_0_WORD_COUNT 0x1 +#define DC_DISP_BLEND_BACKGROUND_COLOR_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_BLEND_BACKGROUND_COLOR_0_RESET_MASK _MK_MASK_CONST(0xffffffff) +#define DC_DISP_BLEND_BACKGROUND_COLOR_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_BLEND_BACKGROUND_COLOR_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_BLEND_BACKGROUND_COLOR_0_READ_MASK _MK_MASK_CONST(0xffffffff) +#define DC_DISP_BLEND_BACKGROUND_COLOR_0_WRITE_MASK _MK_MASK_CONST(0xffffffff) +#define DC_DISP_BLEND_BACKGROUND_COLOR_0_BKGND_RED_SHIFT _MK_SHIFT_CONST(0) +#define DC_DISP_BLEND_BACKGROUND_COLOR_0_BKGND_RED_FIELD _MK_FIELD_CONST(0xff, DC_DISP_BLEND_BACKGROUND_COLOR_0_BKGND_RED_SHIFT) +#define DC_DISP_BLEND_BACKGROUND_COLOR_0_BKGND_RED_RANGE 7:0 +#define DC_DISP_BLEND_BACKGROUND_COLOR_0_BKGND_RED_WOFFSET 0x0 +#define DC_DISP_BLEND_BACKGROUND_COLOR_0_BKGND_RED_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_BLEND_BACKGROUND_COLOR_0_BKGND_RED_DEFAULT_MASK _MK_MASK_CONST(0xff) +#define DC_DISP_BLEND_BACKGROUND_COLOR_0_BKGND_RED_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_BLEND_BACKGROUND_COLOR_0_BKGND_RED_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_DISP_BLEND_BACKGROUND_COLOR_0_BKGND_GREEN_SHIFT _MK_SHIFT_CONST(8) +#define DC_DISP_BLEND_BACKGROUND_COLOR_0_BKGND_GREEN_FIELD _MK_FIELD_CONST(0xff, DC_DISP_BLEND_BACKGROUND_COLOR_0_BKGND_GREEN_SHIFT) +#define DC_DISP_BLEND_BACKGROUND_COLOR_0_BKGND_GREEN_RANGE 15:8 +#define DC_DISP_BLEND_BACKGROUND_COLOR_0_BKGND_GREEN_WOFFSET 0x0 +#define DC_DISP_BLEND_BACKGROUND_COLOR_0_BKGND_GREEN_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_BLEND_BACKGROUND_COLOR_0_BKGND_GREEN_DEFAULT_MASK _MK_MASK_CONST(0xff) +#define DC_DISP_BLEND_BACKGROUND_COLOR_0_BKGND_GREEN_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_BLEND_BACKGROUND_COLOR_0_BKGND_GREEN_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_DISP_BLEND_BACKGROUND_COLOR_0_BKGND_BLUE_SHIFT _MK_SHIFT_CONST(16) +#define DC_DISP_BLEND_BACKGROUND_COLOR_0_BKGND_BLUE_FIELD _MK_FIELD_CONST(0xff, DC_DISP_BLEND_BACKGROUND_COLOR_0_BKGND_BLUE_SHIFT) +#define DC_DISP_BLEND_BACKGROUND_COLOR_0_BKGND_BLUE_RANGE 23:16 +#define DC_DISP_BLEND_BACKGROUND_COLOR_0_BKGND_BLUE_WOFFSET 0x0 +#define DC_DISP_BLEND_BACKGROUND_COLOR_0_BKGND_BLUE_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_BLEND_BACKGROUND_COLOR_0_BKGND_BLUE_DEFAULT_MASK _MK_MASK_CONST(0xff) +#define DC_DISP_BLEND_BACKGROUND_COLOR_0_BKGND_BLUE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_BLEND_BACKGROUND_COLOR_0_BKGND_BLUE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_DISP_BLEND_BACKGROUND_COLOR_0_BKGND_ALPHA_SHIFT _MK_SHIFT_CONST(24) +#define DC_DISP_BLEND_BACKGROUND_COLOR_0_BKGND_ALPHA_FIELD _MK_FIELD_CONST(0xff, DC_DISP_BLEND_BACKGROUND_COLOR_0_BKGND_ALPHA_SHIFT) +#define DC_DISP_BLEND_BACKGROUND_COLOR_0_BKGND_ALPHA_RANGE 31:24 +#define DC_DISP_BLEND_BACKGROUND_COLOR_0_BKGND_ALPHA_WOFFSET 0x0 +#define DC_DISP_BLEND_BACKGROUND_COLOR_0_BKGND_ALPHA_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_BLEND_BACKGROUND_COLOR_0_BKGND_ALPHA_DEFAULT_MASK _MK_MASK_CONST(0xff) +#define DC_DISP_BLEND_BACKGROUND_COLOR_0_BKGND_ALPHA_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_BLEND_BACKGROUND_COLOR_0_BKGND_ALPHA_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_DISP_INTERLACE_CONTROL_0 +#define DC_DISP_INTERLACE_CONTROL_0 _MK_ADDR_CONST(0x4e5) +#define DC_DISP_INTERLACE_CONTROL_0_SECURE 0x0 +#define DC_DISP_INTERLACE_CONTROL_0_WORD_COUNT 0x1 +#define DC_DISP_INTERLACE_CONTROL_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_INTERLACE_CONTROL_0_RESET_MASK _MK_MASK_CONST(0x7) +#define DC_DISP_INTERLACE_CONTROL_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_INTERLACE_CONTROL_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_INTERLACE_CONTROL_0_READ_MASK _MK_MASK_CONST(0x7) +#define DC_DISP_INTERLACE_CONTROL_0_WRITE_MASK _MK_MASK_CONST(0x3) +#define DC_DISP_INTERLACE_CONTROL_0_INTERLACE_ENABLE_SHIFT _MK_SHIFT_CONST(0) +#define DC_DISP_INTERLACE_CONTROL_0_INTERLACE_ENABLE_FIELD _MK_FIELD_CONST(0x1, DC_DISP_INTERLACE_CONTROL_0_INTERLACE_ENABLE_SHIFT) +#define DC_DISP_INTERLACE_CONTROL_0_INTERLACE_ENABLE_RANGE 0:0 +#define DC_DISP_INTERLACE_CONTROL_0_INTERLACE_ENABLE_WOFFSET 0x0 +#define DC_DISP_INTERLACE_CONTROL_0_INTERLACE_ENABLE_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_INTERLACE_CONTROL_0_INTERLACE_ENABLE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_DISP_INTERLACE_CONTROL_0_INTERLACE_ENABLE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_INTERLACE_CONTROL_0_INTERLACE_ENABLE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_INTERLACE_CONTROL_0_INTERLACE_ENABLE_DISABLE _MK_ENUM_CONST(0) +#define DC_DISP_INTERLACE_CONTROL_0_INTERLACE_ENABLE_ENABLE _MK_ENUM_CONST(1) + +#define DC_DISP_INTERLACE_CONTROL_0_INTERLACE_START_SHIFT _MK_SHIFT_CONST(1) +#define DC_DISP_INTERLACE_CONTROL_0_INTERLACE_START_FIELD _MK_FIELD_CONST(0x1, DC_DISP_INTERLACE_CONTROL_0_INTERLACE_START_SHIFT) +#define DC_DISP_INTERLACE_CONTROL_0_INTERLACE_START_RANGE 1:1 +#define DC_DISP_INTERLACE_CONTROL_0_INTERLACE_START_WOFFSET 0x0 +#define DC_DISP_INTERLACE_CONTROL_0_INTERLACE_START_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_INTERLACE_CONTROL_0_INTERLACE_START_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_DISP_INTERLACE_CONTROL_0_INTERLACE_START_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_INTERLACE_CONTROL_0_INTERLACE_START_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_INTERLACE_CONTROL_0_INTERLACE_START_FIELD1 _MK_ENUM_CONST(0) +#define DC_DISP_INTERLACE_CONTROL_0_INTERLACE_START_FIELD2 _MK_ENUM_CONST(1) + +#define DC_DISP_INTERLACE_CONTROL_0_INTERLACE_STATUS_SHIFT _MK_SHIFT_CONST(2) +#define DC_DISP_INTERLACE_CONTROL_0_INTERLACE_STATUS_FIELD _MK_FIELD_CONST(0x1, DC_DISP_INTERLACE_CONTROL_0_INTERLACE_STATUS_SHIFT) +#define DC_DISP_INTERLACE_CONTROL_0_INTERLACE_STATUS_RANGE 2:2 +#define DC_DISP_INTERLACE_CONTROL_0_INTERLACE_STATUS_WOFFSET 0x0 +#define DC_DISP_INTERLACE_CONTROL_0_INTERLACE_STATUS_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_INTERLACE_CONTROL_0_INTERLACE_STATUS_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_DISP_INTERLACE_CONTROL_0_INTERLACE_STATUS_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_INTERLACE_CONTROL_0_INTERLACE_STATUS_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_INTERLACE_CONTROL_0_INTERLACE_STATUS_FIELD1 _MK_ENUM_CONST(0) +#define DC_DISP_INTERLACE_CONTROL_0_INTERLACE_STATUS_FIELD2 _MK_ENUM_CONST(1) + + +// Register DC_DISP_INTERLACE_FIELD2_REF_TO_SYNC_0 +#define DC_DISP_INTERLACE_FIELD2_REF_TO_SYNC_0 _MK_ADDR_CONST(0x4e6) +#define DC_DISP_INTERLACE_FIELD2_REF_TO_SYNC_0_SECURE 0x0 +#define DC_DISP_INTERLACE_FIELD2_REF_TO_SYNC_0_WORD_COUNT 0x1 +#define DC_DISP_INTERLACE_FIELD2_REF_TO_SYNC_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_INTERLACE_FIELD2_REF_TO_SYNC_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_INTERLACE_FIELD2_REF_TO_SYNC_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_INTERLACE_FIELD2_REF_TO_SYNC_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_INTERLACE_FIELD2_REF_TO_SYNC_0_READ_MASK _MK_MASK_CONST(0x1fff1fff) +#define DC_DISP_INTERLACE_FIELD2_REF_TO_SYNC_0_WRITE_MASK _MK_MASK_CONST(0x1fff1fff) +#define DC_DISP_INTERLACE_FIELD2_REF_TO_SYNC_0_FIELD2_H_REF_TO_SYNC_SHIFT _MK_SHIFT_CONST(0) +#define DC_DISP_INTERLACE_FIELD2_REF_TO_SYNC_0_FIELD2_H_REF_TO_SYNC_FIELD _MK_FIELD_CONST(0x1fff, DC_DISP_INTERLACE_FIELD2_REF_TO_SYNC_0_FIELD2_H_REF_TO_SYNC_SHIFT) +#define DC_DISP_INTERLACE_FIELD2_REF_TO_SYNC_0_FIELD2_H_REF_TO_SYNC_RANGE 12:0 +#define DC_DISP_INTERLACE_FIELD2_REF_TO_SYNC_0_FIELD2_H_REF_TO_SYNC_WOFFSET 0x0 +#define DC_DISP_INTERLACE_FIELD2_REF_TO_SYNC_0_FIELD2_H_REF_TO_SYNC_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_INTERLACE_FIELD2_REF_TO_SYNC_0_FIELD2_H_REF_TO_SYNC_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_INTERLACE_FIELD2_REF_TO_SYNC_0_FIELD2_H_REF_TO_SYNC_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_INTERLACE_FIELD2_REF_TO_SYNC_0_FIELD2_H_REF_TO_SYNC_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_DISP_INTERLACE_FIELD2_REF_TO_SYNC_0_FIELD2_V_REF_TO_SYNC_SHIFT _MK_SHIFT_CONST(16) +#define DC_DISP_INTERLACE_FIELD2_REF_TO_SYNC_0_FIELD2_V_REF_TO_SYNC_FIELD _MK_FIELD_CONST(0x1fff, DC_DISP_INTERLACE_FIELD2_REF_TO_SYNC_0_FIELD2_V_REF_TO_SYNC_SHIFT) +#define DC_DISP_INTERLACE_FIELD2_REF_TO_SYNC_0_FIELD2_V_REF_TO_SYNC_RANGE 28:16 +#define DC_DISP_INTERLACE_FIELD2_REF_TO_SYNC_0_FIELD2_V_REF_TO_SYNC_WOFFSET 0x0 +#define DC_DISP_INTERLACE_FIELD2_REF_TO_SYNC_0_FIELD2_V_REF_TO_SYNC_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_INTERLACE_FIELD2_REF_TO_SYNC_0_FIELD2_V_REF_TO_SYNC_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_INTERLACE_FIELD2_REF_TO_SYNC_0_FIELD2_V_REF_TO_SYNC_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_INTERLACE_FIELD2_REF_TO_SYNC_0_FIELD2_V_REF_TO_SYNC_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_DISP_INTERLACE_FIELD2_SYNC_WIDTH_0 +#define DC_DISP_INTERLACE_FIELD2_SYNC_WIDTH_0 _MK_ADDR_CONST(0x4e7) +#define DC_DISP_INTERLACE_FIELD2_SYNC_WIDTH_0_SECURE 0x0 +#define DC_DISP_INTERLACE_FIELD2_SYNC_WIDTH_0_WORD_COUNT 0x1 +#define DC_DISP_INTERLACE_FIELD2_SYNC_WIDTH_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_INTERLACE_FIELD2_SYNC_WIDTH_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_INTERLACE_FIELD2_SYNC_WIDTH_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_INTERLACE_FIELD2_SYNC_WIDTH_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_INTERLACE_FIELD2_SYNC_WIDTH_0_READ_MASK _MK_MASK_CONST(0x1fff1fff) +#define DC_DISP_INTERLACE_FIELD2_SYNC_WIDTH_0_WRITE_MASK _MK_MASK_CONST(0x1fff1fff) +#define DC_DISP_INTERLACE_FIELD2_SYNC_WIDTH_0_FIELD2_H_SYNC_WIDTH_SHIFT _MK_SHIFT_CONST(0) +#define DC_DISP_INTERLACE_FIELD2_SYNC_WIDTH_0_FIELD2_H_SYNC_WIDTH_FIELD _MK_FIELD_CONST(0x1fff, DC_DISP_INTERLACE_FIELD2_SYNC_WIDTH_0_FIELD2_H_SYNC_WIDTH_SHIFT) +#define DC_DISP_INTERLACE_FIELD2_SYNC_WIDTH_0_FIELD2_H_SYNC_WIDTH_RANGE 12:0 +#define DC_DISP_INTERLACE_FIELD2_SYNC_WIDTH_0_FIELD2_H_SYNC_WIDTH_WOFFSET 0x0 +#define DC_DISP_INTERLACE_FIELD2_SYNC_WIDTH_0_FIELD2_H_SYNC_WIDTH_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_INTERLACE_FIELD2_SYNC_WIDTH_0_FIELD2_H_SYNC_WIDTH_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_INTERLACE_FIELD2_SYNC_WIDTH_0_FIELD2_H_SYNC_WIDTH_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_INTERLACE_FIELD2_SYNC_WIDTH_0_FIELD2_H_SYNC_WIDTH_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_DISP_INTERLACE_FIELD2_SYNC_WIDTH_0_FIELD2_V_SYNC_WIDTH_SHIFT _MK_SHIFT_CONST(16) +#define DC_DISP_INTERLACE_FIELD2_SYNC_WIDTH_0_FIELD2_V_SYNC_WIDTH_FIELD _MK_FIELD_CONST(0x1fff, DC_DISP_INTERLACE_FIELD2_SYNC_WIDTH_0_FIELD2_V_SYNC_WIDTH_SHIFT) +#define DC_DISP_INTERLACE_FIELD2_SYNC_WIDTH_0_FIELD2_V_SYNC_WIDTH_RANGE 28:16 +#define DC_DISP_INTERLACE_FIELD2_SYNC_WIDTH_0_FIELD2_V_SYNC_WIDTH_WOFFSET 0x0 +#define DC_DISP_INTERLACE_FIELD2_SYNC_WIDTH_0_FIELD2_V_SYNC_WIDTH_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_INTERLACE_FIELD2_SYNC_WIDTH_0_FIELD2_V_SYNC_WIDTH_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_INTERLACE_FIELD2_SYNC_WIDTH_0_FIELD2_V_SYNC_WIDTH_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_INTERLACE_FIELD2_SYNC_WIDTH_0_FIELD2_V_SYNC_WIDTH_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_DISP_INTERLACE_FIELD2_BACK_PORCH_0 +#define DC_DISP_INTERLACE_FIELD2_BACK_PORCH_0 _MK_ADDR_CONST(0x4e8) +#define DC_DISP_INTERLACE_FIELD2_BACK_PORCH_0_SECURE 0x0 +#define DC_DISP_INTERLACE_FIELD2_BACK_PORCH_0_WORD_COUNT 0x1 +#define DC_DISP_INTERLACE_FIELD2_BACK_PORCH_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_INTERLACE_FIELD2_BACK_PORCH_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_INTERLACE_FIELD2_BACK_PORCH_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_INTERLACE_FIELD2_BACK_PORCH_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_INTERLACE_FIELD2_BACK_PORCH_0_READ_MASK _MK_MASK_CONST(0x1fff1fff) +#define DC_DISP_INTERLACE_FIELD2_BACK_PORCH_0_WRITE_MASK _MK_MASK_CONST(0x1fff1fff) +#define DC_DISP_INTERLACE_FIELD2_BACK_PORCH_0_FIELD2_H_BACK_PORCH_SHIFT _MK_SHIFT_CONST(0) +#define DC_DISP_INTERLACE_FIELD2_BACK_PORCH_0_FIELD2_H_BACK_PORCH_FIELD _MK_FIELD_CONST(0x1fff, DC_DISP_INTERLACE_FIELD2_BACK_PORCH_0_FIELD2_H_BACK_PORCH_SHIFT) +#define DC_DISP_INTERLACE_FIELD2_BACK_PORCH_0_FIELD2_H_BACK_PORCH_RANGE 12:0 +#define DC_DISP_INTERLACE_FIELD2_BACK_PORCH_0_FIELD2_H_BACK_PORCH_WOFFSET 0x0 +#define DC_DISP_INTERLACE_FIELD2_BACK_PORCH_0_FIELD2_H_BACK_PORCH_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_INTERLACE_FIELD2_BACK_PORCH_0_FIELD2_H_BACK_PORCH_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_INTERLACE_FIELD2_BACK_PORCH_0_FIELD2_H_BACK_PORCH_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_INTERLACE_FIELD2_BACK_PORCH_0_FIELD2_H_BACK_PORCH_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_DISP_INTERLACE_FIELD2_BACK_PORCH_0_FIELD2_V_BACK_PORCH_SHIFT _MK_SHIFT_CONST(16) +#define DC_DISP_INTERLACE_FIELD2_BACK_PORCH_0_FIELD2_V_BACK_PORCH_FIELD _MK_FIELD_CONST(0x1fff, DC_DISP_INTERLACE_FIELD2_BACK_PORCH_0_FIELD2_V_BACK_PORCH_SHIFT) +#define DC_DISP_INTERLACE_FIELD2_BACK_PORCH_0_FIELD2_V_BACK_PORCH_RANGE 28:16 +#define DC_DISP_INTERLACE_FIELD2_BACK_PORCH_0_FIELD2_V_BACK_PORCH_WOFFSET 0x0 +#define DC_DISP_INTERLACE_FIELD2_BACK_PORCH_0_FIELD2_V_BACK_PORCH_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_INTERLACE_FIELD2_BACK_PORCH_0_FIELD2_V_BACK_PORCH_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_INTERLACE_FIELD2_BACK_PORCH_0_FIELD2_V_BACK_PORCH_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_INTERLACE_FIELD2_BACK_PORCH_0_FIELD2_V_BACK_PORCH_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_DISP_INTERLACE_FIELD2_FRONT_PORCH_0 +#define DC_DISP_INTERLACE_FIELD2_FRONT_PORCH_0 _MK_ADDR_CONST(0x4e9) +#define DC_DISP_INTERLACE_FIELD2_FRONT_PORCH_0_SECURE 0x0 +#define DC_DISP_INTERLACE_FIELD2_FRONT_PORCH_0_WORD_COUNT 0x1 +#define DC_DISP_INTERLACE_FIELD2_FRONT_PORCH_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_INTERLACE_FIELD2_FRONT_PORCH_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_INTERLACE_FIELD2_FRONT_PORCH_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_INTERLACE_FIELD2_FRONT_PORCH_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_INTERLACE_FIELD2_FRONT_PORCH_0_READ_MASK _MK_MASK_CONST(0x1fff1fff) +#define DC_DISP_INTERLACE_FIELD2_FRONT_PORCH_0_WRITE_MASK _MK_MASK_CONST(0x1fff1fff) +#define DC_DISP_INTERLACE_FIELD2_FRONT_PORCH_0_FIELD2_H_FRONT_PORCH_SHIFT _MK_SHIFT_CONST(0) +#define DC_DISP_INTERLACE_FIELD2_FRONT_PORCH_0_FIELD2_H_FRONT_PORCH_FIELD _MK_FIELD_CONST(0x1fff, DC_DISP_INTERLACE_FIELD2_FRONT_PORCH_0_FIELD2_H_FRONT_PORCH_SHIFT) +#define DC_DISP_INTERLACE_FIELD2_FRONT_PORCH_0_FIELD2_H_FRONT_PORCH_RANGE 12:0 +#define DC_DISP_INTERLACE_FIELD2_FRONT_PORCH_0_FIELD2_H_FRONT_PORCH_WOFFSET 0x0 +#define DC_DISP_INTERLACE_FIELD2_FRONT_PORCH_0_FIELD2_H_FRONT_PORCH_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_INTERLACE_FIELD2_FRONT_PORCH_0_FIELD2_H_FRONT_PORCH_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_INTERLACE_FIELD2_FRONT_PORCH_0_FIELD2_H_FRONT_PORCH_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_INTERLACE_FIELD2_FRONT_PORCH_0_FIELD2_H_FRONT_PORCH_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_DISP_INTERLACE_FIELD2_FRONT_PORCH_0_FIELD2_V_FRONT_PORCH_SHIFT _MK_SHIFT_CONST(16) +#define DC_DISP_INTERLACE_FIELD2_FRONT_PORCH_0_FIELD2_V_FRONT_PORCH_FIELD _MK_FIELD_CONST(0x1fff, DC_DISP_INTERLACE_FIELD2_FRONT_PORCH_0_FIELD2_V_FRONT_PORCH_SHIFT) +#define DC_DISP_INTERLACE_FIELD2_FRONT_PORCH_0_FIELD2_V_FRONT_PORCH_RANGE 28:16 +#define DC_DISP_INTERLACE_FIELD2_FRONT_PORCH_0_FIELD2_V_FRONT_PORCH_WOFFSET 0x0 +#define DC_DISP_INTERLACE_FIELD2_FRONT_PORCH_0_FIELD2_V_FRONT_PORCH_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_INTERLACE_FIELD2_FRONT_PORCH_0_FIELD2_V_FRONT_PORCH_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_INTERLACE_FIELD2_FRONT_PORCH_0_FIELD2_V_FRONT_PORCH_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_INTERLACE_FIELD2_FRONT_PORCH_0_FIELD2_V_FRONT_PORCH_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_DISP_INTERLACE_FIELD2_DISP_ACTIVE_0 +#define DC_DISP_INTERLACE_FIELD2_DISP_ACTIVE_0 _MK_ADDR_CONST(0x4ea) +#define DC_DISP_INTERLACE_FIELD2_DISP_ACTIVE_0_SECURE 0x0 +#define DC_DISP_INTERLACE_FIELD2_DISP_ACTIVE_0_WORD_COUNT 0x1 +#define DC_DISP_INTERLACE_FIELD2_DISP_ACTIVE_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_INTERLACE_FIELD2_DISP_ACTIVE_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_INTERLACE_FIELD2_DISP_ACTIVE_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_INTERLACE_FIELD2_DISP_ACTIVE_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_INTERLACE_FIELD2_DISP_ACTIVE_0_READ_MASK _MK_MASK_CONST(0x1fff1fff) +#define DC_DISP_INTERLACE_FIELD2_DISP_ACTIVE_0_WRITE_MASK _MK_MASK_CONST(0x1fff1fff) +#define DC_DISP_INTERLACE_FIELD2_DISP_ACTIVE_0_FIELD2_H_DISP_ACTIVE_SHIFT _MK_SHIFT_CONST(0) +#define DC_DISP_INTERLACE_FIELD2_DISP_ACTIVE_0_FIELD2_H_DISP_ACTIVE_FIELD _MK_FIELD_CONST(0x1fff, DC_DISP_INTERLACE_FIELD2_DISP_ACTIVE_0_FIELD2_H_DISP_ACTIVE_SHIFT) +#define DC_DISP_INTERLACE_FIELD2_DISP_ACTIVE_0_FIELD2_H_DISP_ACTIVE_RANGE 12:0 +#define DC_DISP_INTERLACE_FIELD2_DISP_ACTIVE_0_FIELD2_H_DISP_ACTIVE_WOFFSET 0x0 +#define DC_DISP_INTERLACE_FIELD2_DISP_ACTIVE_0_FIELD2_H_DISP_ACTIVE_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_INTERLACE_FIELD2_DISP_ACTIVE_0_FIELD2_H_DISP_ACTIVE_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_INTERLACE_FIELD2_DISP_ACTIVE_0_FIELD2_H_DISP_ACTIVE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_INTERLACE_FIELD2_DISP_ACTIVE_0_FIELD2_H_DISP_ACTIVE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_DISP_INTERLACE_FIELD2_DISP_ACTIVE_0_FIELD2_V_DISP_ACTIVE_SHIFT _MK_SHIFT_CONST(16) +#define DC_DISP_INTERLACE_FIELD2_DISP_ACTIVE_0_FIELD2_V_DISP_ACTIVE_FIELD _MK_FIELD_CONST(0x1fff, DC_DISP_INTERLACE_FIELD2_DISP_ACTIVE_0_FIELD2_V_DISP_ACTIVE_SHIFT) +#define DC_DISP_INTERLACE_FIELD2_DISP_ACTIVE_0_FIELD2_V_DISP_ACTIVE_RANGE 28:16 +#define DC_DISP_INTERLACE_FIELD2_DISP_ACTIVE_0_FIELD2_V_DISP_ACTIVE_WOFFSET 0x0 +#define DC_DISP_INTERLACE_FIELD2_DISP_ACTIVE_0_FIELD2_V_DISP_ACTIVE_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_INTERLACE_FIELD2_DISP_ACTIVE_0_FIELD2_V_DISP_ACTIVE_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_INTERLACE_FIELD2_DISP_ACTIVE_0_FIELD2_V_DISP_ACTIVE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_INTERLACE_FIELD2_DISP_ACTIVE_0_FIELD2_V_DISP_ACTIVE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_DISP_CURSOR_UNDERFLOW_CTRL_0 +#define DC_DISP_CURSOR_UNDERFLOW_CTRL_0 _MK_ADDR_CONST(0x4eb) +#define DC_DISP_CURSOR_UNDERFLOW_CTRL_0_SECURE 0x0 +#define DC_DISP_CURSOR_UNDERFLOW_CTRL_0_WORD_COUNT 0x1 +#define DC_DISP_CURSOR_UNDERFLOW_CTRL_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_CURSOR_UNDERFLOW_CTRL_0_RESET_MASK _MK_MASK_CONST(0x81) +#define DC_DISP_CURSOR_UNDERFLOW_CTRL_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_CURSOR_UNDERFLOW_CTRL_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_CURSOR_UNDERFLOW_CTRL_0_READ_MASK _MK_MASK_CONST(0x81) +#define DC_DISP_CURSOR_UNDERFLOW_CTRL_0_WRITE_MASK _MK_MASK_CONST(0x81) +#define DC_DISP_CURSOR_UNDERFLOW_CTRL_0_CURSOR_UFLOW_CTRL_DBG_MODE_SHIFT _MK_SHIFT_CONST(0) +#define DC_DISP_CURSOR_UNDERFLOW_CTRL_0_CURSOR_UFLOW_CTRL_DBG_MODE_FIELD _MK_FIELD_CONST(0x1, DC_DISP_CURSOR_UNDERFLOW_CTRL_0_CURSOR_UFLOW_CTRL_DBG_MODE_SHIFT) +#define DC_DISP_CURSOR_UNDERFLOW_CTRL_0_CURSOR_UFLOW_CTRL_DBG_MODE_RANGE 0:0 +#define DC_DISP_CURSOR_UNDERFLOW_CTRL_0_CURSOR_UFLOW_CTRL_DBG_MODE_WOFFSET 0x0 +#define DC_DISP_CURSOR_UNDERFLOW_CTRL_0_CURSOR_UFLOW_CTRL_DBG_MODE_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_CURSOR_UNDERFLOW_CTRL_0_CURSOR_UFLOW_CTRL_DBG_MODE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_DISP_CURSOR_UNDERFLOW_CTRL_0_CURSOR_UFLOW_CTRL_DBG_MODE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_CURSOR_UNDERFLOW_CTRL_0_CURSOR_UFLOW_CTRL_DBG_MODE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_CURSOR_UNDERFLOW_CTRL_0_CURSOR_UFLOW_CTRL_DBG_MODE_DISABLE _MK_ENUM_CONST(0) +#define DC_DISP_CURSOR_UNDERFLOW_CTRL_0_CURSOR_UFLOW_CTRL_DBG_MODE_ENABLE _MK_ENUM_CONST(1) + +#define DC_DISP_CURSOR_UNDERFLOW_CTRL_0_CURSOR_UFLOW_CYA_SHIFT _MK_SHIFT_CONST(7) +#define DC_DISP_CURSOR_UNDERFLOW_CTRL_0_CURSOR_UFLOW_CYA_FIELD _MK_FIELD_CONST(0x1, DC_DISP_CURSOR_UNDERFLOW_CTRL_0_CURSOR_UFLOW_CYA_SHIFT) +#define DC_DISP_CURSOR_UNDERFLOW_CTRL_0_CURSOR_UFLOW_CYA_RANGE 7:7 +#define DC_DISP_CURSOR_UNDERFLOW_CTRL_0_CURSOR_UFLOW_CYA_WOFFSET 0x0 +#define DC_DISP_CURSOR_UNDERFLOW_CTRL_0_CURSOR_UFLOW_CYA_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_CURSOR_UNDERFLOW_CTRL_0_CURSOR_UFLOW_CYA_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_DISP_CURSOR_UNDERFLOW_CTRL_0_CURSOR_UFLOW_CYA_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_CURSOR_UNDERFLOW_CTRL_0_CURSOR_UFLOW_CYA_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_CURSOR_UNDERFLOW_CTRL_0_CURSOR_UFLOW_CYA_DISABLE _MK_ENUM_CONST(0) +#define DC_DISP_CURSOR_UNDERFLOW_CTRL_0_CURSOR_UFLOW_CYA_ENABLE _MK_ENUM_CONST(1) + + +// Register DC_DISP_CURSOR_START_ADDR_HI_0 +#define DC_DISP_CURSOR_START_ADDR_HI_0 _MK_ADDR_CONST(0x4ec) +#define DC_DISP_CURSOR_START_ADDR_HI_0_SECURE 0x0 +#define DC_DISP_CURSOR_START_ADDR_HI_0_WORD_COUNT 0x1 +#define DC_DISP_CURSOR_START_ADDR_HI_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_CURSOR_START_ADDR_HI_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_CURSOR_START_ADDR_HI_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_CURSOR_START_ADDR_HI_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_CURSOR_START_ADDR_HI_0_READ_MASK _MK_MASK_CONST(0x3) +#define DC_DISP_CURSOR_START_ADDR_HI_0_WRITE_MASK _MK_MASK_CONST(0x3) +#define DC_DISP_CURSOR_START_ADDR_HI_0_CURSOR_START_ADDR_HI_SHIFT _MK_SHIFT_CONST(0) +#define DC_DISP_CURSOR_START_ADDR_HI_0_CURSOR_START_ADDR_HI_FIELD _MK_FIELD_CONST(0x3, DC_DISP_CURSOR_START_ADDR_HI_0_CURSOR_START_ADDR_HI_SHIFT) +#define DC_DISP_CURSOR_START_ADDR_HI_0_CURSOR_START_ADDR_HI_RANGE 1:0 +#define DC_DISP_CURSOR_START_ADDR_HI_0_CURSOR_START_ADDR_HI_WOFFSET 0x0 +#define DC_DISP_CURSOR_START_ADDR_HI_0_CURSOR_START_ADDR_HI_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_CURSOR_START_ADDR_HI_0_CURSOR_START_ADDR_HI_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_CURSOR_START_ADDR_HI_0_CURSOR_START_ADDR_HI_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_CURSOR_START_ADDR_HI_0_CURSOR_START_ADDR_HI_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_DISP_CURSOR_START_ADDR_HI_NS_0 +#define DC_DISP_CURSOR_START_ADDR_HI_NS_0 _MK_ADDR_CONST(0x4ed) +#define DC_DISP_CURSOR_START_ADDR_HI_NS_0_SECURE 0x0 +#define DC_DISP_CURSOR_START_ADDR_HI_NS_0_WORD_COUNT 0x1 +#define DC_DISP_CURSOR_START_ADDR_HI_NS_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_CURSOR_START_ADDR_HI_NS_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_CURSOR_START_ADDR_HI_NS_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_CURSOR_START_ADDR_HI_NS_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_CURSOR_START_ADDR_HI_NS_0_READ_MASK _MK_MASK_CONST(0x3) +#define DC_DISP_CURSOR_START_ADDR_HI_NS_0_WRITE_MASK _MK_MASK_CONST(0x3) +#define DC_DISP_CURSOR_START_ADDR_HI_NS_0_CURSOR_START_ADDR_HI_NS_SHIFT _MK_SHIFT_CONST(0) +#define DC_DISP_CURSOR_START_ADDR_HI_NS_0_CURSOR_START_ADDR_HI_NS_FIELD _MK_FIELD_CONST(0x3, DC_DISP_CURSOR_START_ADDR_HI_NS_0_CURSOR_START_ADDR_HI_NS_SHIFT) +#define DC_DISP_CURSOR_START_ADDR_HI_NS_0_CURSOR_START_ADDR_HI_NS_RANGE 1:0 +#define DC_DISP_CURSOR_START_ADDR_HI_NS_0_CURSOR_START_ADDR_HI_NS_WOFFSET 0x0 +#define DC_DISP_CURSOR_START_ADDR_HI_NS_0_CURSOR_START_ADDR_HI_NS_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_CURSOR_START_ADDR_HI_NS_0_CURSOR_START_ADDR_HI_NS_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_CURSOR_START_ADDR_HI_NS_0_CURSOR_START_ADDR_HI_NS_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_CURSOR_START_ADDR_HI_NS_0_CURSOR_START_ADDR_HI_NS_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_DISP_CURSOR_INTERLACE_CONTROL_0 +#define DC_DISP_CURSOR_INTERLACE_CONTROL_0 _MK_ADDR_CONST(0x4ee) +#define DC_DISP_CURSOR_INTERLACE_CONTROL_0_SECURE 0x0 +#define DC_DISP_CURSOR_INTERLACE_CONTROL_0_WORD_COUNT 0x1 +#define DC_DISP_CURSOR_INTERLACE_CONTROL_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_CURSOR_INTERLACE_CONTROL_0_RESET_MASK _MK_MASK_CONST(0x1f) +#define DC_DISP_CURSOR_INTERLACE_CONTROL_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_CURSOR_INTERLACE_CONTROL_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_CURSOR_INTERLACE_CONTROL_0_READ_MASK _MK_MASK_CONST(0x1f) +#define DC_DISP_CURSOR_INTERLACE_CONTROL_0_WRITE_MASK _MK_MASK_CONST(0x1b) +#define DC_DISP_CURSOR_INTERLACE_CONTROL_0_CURSOR_INTERLACE_ENABLE_SHIFT _MK_SHIFT_CONST(0) +#define DC_DISP_CURSOR_INTERLACE_CONTROL_0_CURSOR_INTERLACE_ENABLE_FIELD _MK_FIELD_CONST(0x1, DC_DISP_CURSOR_INTERLACE_CONTROL_0_CURSOR_INTERLACE_ENABLE_SHIFT) +#define DC_DISP_CURSOR_INTERLACE_CONTROL_0_CURSOR_INTERLACE_ENABLE_RANGE 0:0 +#define DC_DISP_CURSOR_INTERLACE_CONTROL_0_CURSOR_INTERLACE_ENABLE_WOFFSET 0x0 +#define DC_DISP_CURSOR_INTERLACE_CONTROL_0_CURSOR_INTERLACE_ENABLE_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_CURSOR_INTERLACE_CONTROL_0_CURSOR_INTERLACE_ENABLE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_DISP_CURSOR_INTERLACE_CONTROL_0_CURSOR_INTERLACE_ENABLE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_CURSOR_INTERLACE_CONTROL_0_CURSOR_INTERLACE_ENABLE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_CURSOR_INTERLACE_CONTROL_0_CURSOR_INTERLACE_ENABLE_DISABLE _MK_ENUM_CONST(0) +#define DC_DISP_CURSOR_INTERLACE_CONTROL_0_CURSOR_INTERLACE_ENABLE_ENABLE _MK_ENUM_CONST(1) + +#define DC_DISP_CURSOR_INTERLACE_CONTROL_0_CURSOR_INTERLACE_START_SHIFT _MK_SHIFT_CONST(1) +#define DC_DISP_CURSOR_INTERLACE_CONTROL_0_CURSOR_INTERLACE_START_FIELD _MK_FIELD_CONST(0x1, DC_DISP_CURSOR_INTERLACE_CONTROL_0_CURSOR_INTERLACE_START_SHIFT) +#define DC_DISP_CURSOR_INTERLACE_CONTROL_0_CURSOR_INTERLACE_START_RANGE 1:1 +#define DC_DISP_CURSOR_INTERLACE_CONTROL_0_CURSOR_INTERLACE_START_WOFFSET 0x0 +#define DC_DISP_CURSOR_INTERLACE_CONTROL_0_CURSOR_INTERLACE_START_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_CURSOR_INTERLACE_CONTROL_0_CURSOR_INTERLACE_START_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_DISP_CURSOR_INTERLACE_CONTROL_0_CURSOR_INTERLACE_START_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_CURSOR_INTERLACE_CONTROL_0_CURSOR_INTERLACE_START_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_CURSOR_INTERLACE_CONTROL_0_CURSOR_INTERLACE_START_LINE0 _MK_ENUM_CONST(0) +#define DC_DISP_CURSOR_INTERLACE_CONTROL_0_CURSOR_INTERLACE_START_LINE1 _MK_ENUM_CONST(1) + +#define DC_DISP_CURSOR_INTERLACE_CONTROL_0_CURSOR_INTERLACE_STATUS_SHIFT _MK_SHIFT_CONST(2) +#define DC_DISP_CURSOR_INTERLACE_CONTROL_0_CURSOR_INTERLACE_STATUS_FIELD _MK_FIELD_CONST(0x1, DC_DISP_CURSOR_INTERLACE_CONTROL_0_CURSOR_INTERLACE_STATUS_SHIFT) +#define DC_DISP_CURSOR_INTERLACE_CONTROL_0_CURSOR_INTERLACE_STATUS_RANGE 2:2 +#define DC_DISP_CURSOR_INTERLACE_CONTROL_0_CURSOR_INTERLACE_STATUS_WOFFSET 0x0 +#define DC_DISP_CURSOR_INTERLACE_CONTROL_0_CURSOR_INTERLACE_STATUS_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_CURSOR_INTERLACE_CONTROL_0_CURSOR_INTERLACE_STATUS_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_DISP_CURSOR_INTERLACE_CONTROL_0_CURSOR_INTERLACE_STATUS_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_CURSOR_INTERLACE_CONTROL_0_CURSOR_INTERLACE_STATUS_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_CURSOR_INTERLACE_CONTROL_0_CURSOR_INTERLACE_STATUS_LINE0 _MK_ENUM_CONST(0) +#define DC_DISP_CURSOR_INTERLACE_CONTROL_0_CURSOR_INTERLACE_STATUS_LINE1 _MK_ENUM_CONST(1) + +#define DC_DISP_CURSOR_INTERLACE_CONTROL_0_CURSOR_INTERLACE_FIELD1_VOFF_INCR_SHIFT _MK_SHIFT_CONST(3) +#define DC_DISP_CURSOR_INTERLACE_CONTROL_0_CURSOR_INTERLACE_FIELD1_VOFF_INCR_FIELD _MK_FIELD_CONST(0x1, DC_DISP_CURSOR_INTERLACE_CONTROL_0_CURSOR_INTERLACE_FIELD1_VOFF_INCR_SHIFT) +#define DC_DISP_CURSOR_INTERLACE_CONTROL_0_CURSOR_INTERLACE_FIELD1_VOFF_INCR_RANGE 3:3 +#define DC_DISP_CURSOR_INTERLACE_CONTROL_0_CURSOR_INTERLACE_FIELD1_VOFF_INCR_WOFFSET 0x0 +#define DC_DISP_CURSOR_INTERLACE_CONTROL_0_CURSOR_INTERLACE_FIELD1_VOFF_INCR_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_CURSOR_INTERLACE_CONTROL_0_CURSOR_INTERLACE_FIELD1_VOFF_INCR_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_DISP_CURSOR_INTERLACE_CONTROL_0_CURSOR_INTERLACE_FIELD1_VOFF_INCR_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_CURSOR_INTERLACE_CONTROL_0_CURSOR_INTERLACE_FIELD1_VOFF_INCR_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_CURSOR_INTERLACE_CONTROL_0_CURSOR_INTERLACE_FIELD1_VOFF_INCR_DISABLE _MK_ENUM_CONST(0) +#define DC_DISP_CURSOR_INTERLACE_CONTROL_0_CURSOR_INTERLACE_FIELD1_VOFF_INCR_ENABLE _MK_ENUM_CONST(1) + +#define DC_DISP_CURSOR_INTERLACE_CONTROL_0_CURSOR_INTERLACE_FIELD2_VOFF_INCR_SHIFT _MK_SHIFT_CONST(4) +#define DC_DISP_CURSOR_INTERLACE_CONTROL_0_CURSOR_INTERLACE_FIELD2_VOFF_INCR_FIELD _MK_FIELD_CONST(0x1, DC_DISP_CURSOR_INTERLACE_CONTROL_0_CURSOR_INTERLACE_FIELD2_VOFF_INCR_SHIFT) +#define DC_DISP_CURSOR_INTERLACE_CONTROL_0_CURSOR_INTERLACE_FIELD2_VOFF_INCR_RANGE 4:4 +#define DC_DISP_CURSOR_INTERLACE_CONTROL_0_CURSOR_INTERLACE_FIELD2_VOFF_INCR_WOFFSET 0x0 +#define DC_DISP_CURSOR_INTERLACE_CONTROL_0_CURSOR_INTERLACE_FIELD2_VOFF_INCR_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_CURSOR_INTERLACE_CONTROL_0_CURSOR_INTERLACE_FIELD2_VOFF_INCR_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_DISP_CURSOR_INTERLACE_CONTROL_0_CURSOR_INTERLACE_FIELD2_VOFF_INCR_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_CURSOR_INTERLACE_CONTROL_0_CURSOR_INTERLACE_FIELD2_VOFF_INCR_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_CURSOR_INTERLACE_CONTROL_0_CURSOR_INTERLACE_FIELD2_VOFF_INCR_DISABLE _MK_ENUM_CONST(0) +#define DC_DISP_CURSOR_INTERLACE_CONTROL_0_CURSOR_INTERLACE_FIELD2_VOFF_INCR_ENABLE _MK_ENUM_CONST(1) + + +// Register DC_DISP_CSC2_CONTROL_0 +#define DC_DISP_CSC2_CONTROL_0 _MK_ADDR_CONST(0x4ef) +#define DC_DISP_CSC2_CONTROL_0_SECURE 0x0 +#define DC_DISP_CSC2_CONTROL_0_WORD_COUNT 0x1 +#define DC_DISP_CSC2_CONTROL_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_CSC2_CONTROL_0_RESET_MASK _MK_MASK_CONST(0x7) +#define DC_DISP_CSC2_CONTROL_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_CSC2_CONTROL_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_CSC2_CONTROL_0_READ_MASK _MK_MASK_CONST(0x7) +#define DC_DISP_CSC2_CONTROL_0_WRITE_MASK _MK_MASK_CONST(0x7) +#define DC_DISP_CSC2_CONTROL_0_OUTPUT_COLOR_SELECT_SHIFT _MK_SHIFT_CONST(0) +#define DC_DISP_CSC2_CONTROL_0_OUTPUT_COLOR_SELECT_FIELD _MK_FIELD_CONST(0x3, DC_DISP_CSC2_CONTROL_0_OUTPUT_COLOR_SELECT_SHIFT) +#define DC_DISP_CSC2_CONTROL_0_OUTPUT_COLOR_SELECT_RANGE 1:0 +#define DC_DISP_CSC2_CONTROL_0_OUTPUT_COLOR_SELECT_WOFFSET 0x0 +#define DC_DISP_CSC2_CONTROL_0_OUTPUT_COLOR_SELECT_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_CSC2_CONTROL_0_OUTPUT_COLOR_SELECT_DEFAULT_MASK _MK_MASK_CONST(0x3) +#define DC_DISP_CSC2_CONTROL_0_OUTPUT_COLOR_SELECT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_CSC2_CONTROL_0_OUTPUT_COLOR_SELECT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_CSC2_CONTROL_0_OUTPUT_COLOR_SELECT_INIT_ENUM RGB +#define DC_DISP_CSC2_CONTROL_0_OUTPUT_COLOR_SELECT_RGB _MK_ENUM_CONST(0) +#define DC_DISP_CSC2_CONTROL_0_OUTPUT_COLOR_SELECT_YCBCR709 _MK_ENUM_CONST(1) +#define DC_DISP_CSC2_CONTROL_0_OUTPUT_COLOR_SELECT_YCBCR601 _MK_ENUM_CONST(2) + +#define DC_DISP_CSC2_CONTROL_0_LIMIT_RGB_COLOR_SHIFT _MK_SHIFT_CONST(2) +#define DC_DISP_CSC2_CONTROL_0_LIMIT_RGB_COLOR_FIELD _MK_FIELD_CONST(0x1, DC_DISP_CSC2_CONTROL_0_LIMIT_RGB_COLOR_SHIFT) +#define DC_DISP_CSC2_CONTROL_0_LIMIT_RGB_COLOR_RANGE 2:2 +#define DC_DISP_CSC2_CONTROL_0_LIMIT_RGB_COLOR_WOFFSET 0x0 +#define DC_DISP_CSC2_CONTROL_0_LIMIT_RGB_COLOR_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_CSC2_CONTROL_0_LIMIT_RGB_COLOR_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_DISP_CSC2_CONTROL_0_LIMIT_RGB_COLOR_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_CSC2_CONTROL_0_LIMIT_RGB_COLOR_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_CSC2_CONTROL_0_LIMIT_RGB_COLOR_DISABLE _MK_ENUM_CONST(0) +#define DC_DISP_CSC2_CONTROL_0_LIMIT_RGB_COLOR_ENABLE _MK_ENUM_CONST(1) + + +// Reserved address 1264 [0x4f0] + +// Register DC_DISP_BLEND_CURSOR_CONTROL_0 +#define DC_DISP_BLEND_CURSOR_CONTROL_0 _MK_ADDR_CONST(0x4f1) +#define DC_DISP_BLEND_CURSOR_CONTROL_0_SECURE 0x0 +#define DC_DISP_BLEND_CURSOR_CONTROL_0_WORD_COUNT 0x1 +#define DC_DISP_BLEND_CURSOR_CONTROL_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_BLEND_CURSOR_CONTROL_0_RESET_MASK _MK_MASK_CONST(0x10303ff) +#define DC_DISP_BLEND_CURSOR_CONTROL_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_BLEND_CURSOR_CONTROL_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_BLEND_CURSOR_CONTROL_0_READ_MASK _MK_MASK_CONST(0x10303ff) +#define DC_DISP_BLEND_CURSOR_CONTROL_0_WRITE_MASK _MK_MASK_CONST(0x10303ff) +#define DC_DISP_BLEND_CURSOR_CONTROL_0_CURSOR_ALPHA_SHIFT _MK_SHIFT_CONST(0) +#define DC_DISP_BLEND_CURSOR_CONTROL_0_CURSOR_ALPHA_FIELD _MK_FIELD_CONST(0xff, DC_DISP_BLEND_CURSOR_CONTROL_0_CURSOR_ALPHA_SHIFT) +#define DC_DISP_BLEND_CURSOR_CONTROL_0_CURSOR_ALPHA_RANGE 7:0 +#define DC_DISP_BLEND_CURSOR_CONTROL_0_CURSOR_ALPHA_WOFFSET 0x0 +#define DC_DISP_BLEND_CURSOR_CONTROL_0_CURSOR_ALPHA_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_BLEND_CURSOR_CONTROL_0_CURSOR_ALPHA_DEFAULT_MASK _MK_MASK_CONST(0xff) +#define DC_DISP_BLEND_CURSOR_CONTROL_0_CURSOR_ALPHA_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_BLEND_CURSOR_CONTROL_0_CURSOR_ALPHA_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_DISP_BLEND_CURSOR_CONTROL_0_CURSOR_SRC_BLEND_FACTOR_SELECT_SHIFT _MK_SHIFT_CONST(8) +#define DC_DISP_BLEND_CURSOR_CONTROL_0_CURSOR_SRC_BLEND_FACTOR_SELECT_FIELD _MK_FIELD_CONST(0x3, DC_DISP_BLEND_CURSOR_CONTROL_0_CURSOR_SRC_BLEND_FACTOR_SELECT_SHIFT) +#define DC_DISP_BLEND_CURSOR_CONTROL_0_CURSOR_SRC_BLEND_FACTOR_SELECT_RANGE 9:8 +#define DC_DISP_BLEND_CURSOR_CONTROL_0_CURSOR_SRC_BLEND_FACTOR_SELECT_WOFFSET 0x0 +#define DC_DISP_BLEND_CURSOR_CONTROL_0_CURSOR_SRC_BLEND_FACTOR_SELECT_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_BLEND_CURSOR_CONTROL_0_CURSOR_SRC_BLEND_FACTOR_SELECT_DEFAULT_MASK _MK_MASK_CONST(0x3) +#define DC_DISP_BLEND_CURSOR_CONTROL_0_CURSOR_SRC_BLEND_FACTOR_SELECT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_BLEND_CURSOR_CONTROL_0_CURSOR_SRC_BLEND_FACTOR_SELECT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_BLEND_CURSOR_CONTROL_0_CURSOR_SRC_BLEND_FACTOR_SELECT_K1 _MK_ENUM_CONST(0) +#define DC_DISP_BLEND_CURSOR_CONTROL_0_CURSOR_SRC_BLEND_FACTOR_SELECT_K1_TIMES_SRC _MK_ENUM_CONST(1) + +#define DC_DISP_BLEND_CURSOR_CONTROL_0_CURSOR_DST_BLEND_FACTOR_SELECT_SHIFT _MK_SHIFT_CONST(16) +#define DC_DISP_BLEND_CURSOR_CONTROL_0_CURSOR_DST_BLEND_FACTOR_SELECT_FIELD _MK_FIELD_CONST(0x3, DC_DISP_BLEND_CURSOR_CONTROL_0_CURSOR_DST_BLEND_FACTOR_SELECT_SHIFT) +#define DC_DISP_BLEND_CURSOR_CONTROL_0_CURSOR_DST_BLEND_FACTOR_SELECT_RANGE 17:16 +#define DC_DISP_BLEND_CURSOR_CONTROL_0_CURSOR_DST_BLEND_FACTOR_SELECT_WOFFSET 0x0 +#define DC_DISP_BLEND_CURSOR_CONTROL_0_CURSOR_DST_BLEND_FACTOR_SELECT_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_BLEND_CURSOR_CONTROL_0_CURSOR_DST_BLEND_FACTOR_SELECT_DEFAULT_MASK _MK_MASK_CONST(0x3) +#define DC_DISP_BLEND_CURSOR_CONTROL_0_CURSOR_DST_BLEND_FACTOR_SELECT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_BLEND_CURSOR_CONTROL_0_CURSOR_DST_BLEND_FACTOR_SELECT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_BLEND_CURSOR_CONTROL_0_CURSOR_DST_BLEND_FACTOR_SELECT_ZERO _MK_ENUM_CONST(0) +#define DC_DISP_BLEND_CURSOR_CONTROL_0_CURSOR_DST_BLEND_FACTOR_SELECT_K1 _MK_ENUM_CONST(1) +#define DC_DISP_BLEND_CURSOR_CONTROL_0_CURSOR_DST_BLEND_FACTOR_SELECT_NEG_K1_TIMES_SRC _MK_ENUM_CONST(2) + +#define DC_DISP_BLEND_CURSOR_CONTROL_0_CURSOR_MODE_SELECT_SHIFT _MK_SHIFT_CONST(24) +#define DC_DISP_BLEND_CURSOR_CONTROL_0_CURSOR_MODE_SELECT_FIELD _MK_FIELD_CONST(0x1, DC_DISP_BLEND_CURSOR_CONTROL_0_CURSOR_MODE_SELECT_SHIFT) +#define DC_DISP_BLEND_CURSOR_CONTROL_0_CURSOR_MODE_SELECT_RANGE 24:24 +#define DC_DISP_BLEND_CURSOR_CONTROL_0_CURSOR_MODE_SELECT_WOFFSET 0x0 +#define DC_DISP_BLEND_CURSOR_CONTROL_0_CURSOR_MODE_SELECT_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_BLEND_CURSOR_CONTROL_0_CURSOR_MODE_SELECT_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_DISP_BLEND_CURSOR_CONTROL_0_CURSOR_MODE_SELECT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_BLEND_CURSOR_CONTROL_0_CURSOR_MODE_SELECT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_BLEND_CURSOR_CONTROL_0_CURSOR_MODE_SELECT_LEGACY _MK_ENUM_CONST(0) +#define DC_DISP_BLEND_CURSOR_CONTROL_0_CURSOR_MODE_SELECT_NORMAL _MK_ENUM_CONST(1) + + +// Register DC_DISP_DVFS_CURSOR_CONTROL_0 +#define DC_DISP_DVFS_CURSOR_CONTROL_0 _MK_ADDR_CONST(0x4f2) +#define DC_DISP_DVFS_CURSOR_CONTROL_0_SECURE 0x0 +#define DC_DISP_DVFS_CURSOR_CONTROL_0_WORD_COUNT 0x1 +#define DC_DISP_DVFS_CURSOR_CONTROL_0_RESET_VAL _MK_MASK_CONST(0x3) +#define DC_DISP_DVFS_CURSOR_CONTROL_0_RESET_MASK _MK_MASK_CONST(0x1ff) +#define DC_DISP_DVFS_CURSOR_CONTROL_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_DVFS_CURSOR_CONTROL_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_DVFS_CURSOR_CONTROL_0_READ_MASK _MK_MASK_CONST(0x1ff) +#define DC_DISP_DVFS_CURSOR_CONTROL_0_WRITE_MASK _MK_MASK_CONST(0x1ff) +#define DC_DISP_DVFS_CURSOR_CONTROL_0_CURSOR_DVFS_THRESHOLD_SHIFT _MK_SHIFT_CONST(0) +#define DC_DISP_DVFS_CURSOR_CONTROL_0_CURSOR_DVFS_THRESHOLD_FIELD _MK_FIELD_CONST(0xff, DC_DISP_DVFS_CURSOR_CONTROL_0_CURSOR_DVFS_THRESHOLD_SHIFT) +#define DC_DISP_DVFS_CURSOR_CONTROL_0_CURSOR_DVFS_THRESHOLD_RANGE 7:0 +#define DC_DISP_DVFS_CURSOR_CONTROL_0_CURSOR_DVFS_THRESHOLD_WOFFSET 0x0 +#define DC_DISP_DVFS_CURSOR_CONTROL_0_CURSOR_DVFS_THRESHOLD_DEFAULT _MK_MASK_CONST(0x3) +#define DC_DISP_DVFS_CURSOR_CONTROL_0_CURSOR_DVFS_THRESHOLD_DEFAULT_MASK _MK_MASK_CONST(0xff) +#define DC_DISP_DVFS_CURSOR_CONTROL_0_CURSOR_DVFS_THRESHOLD_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_DVFS_CURSOR_CONTROL_0_CURSOR_DVFS_THRESHOLD_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_DISP_DVFS_CURSOR_CONTROL_0_CURSOR_DVFS_ENABLE_SHIFT _MK_SHIFT_CONST(8) +#define DC_DISP_DVFS_CURSOR_CONTROL_0_CURSOR_DVFS_ENABLE_FIELD _MK_FIELD_CONST(0x1, DC_DISP_DVFS_CURSOR_CONTROL_0_CURSOR_DVFS_ENABLE_SHIFT) +#define DC_DISP_DVFS_CURSOR_CONTROL_0_CURSOR_DVFS_ENABLE_RANGE 8:8 +#define DC_DISP_DVFS_CURSOR_CONTROL_0_CURSOR_DVFS_ENABLE_WOFFSET 0x0 +#define DC_DISP_DVFS_CURSOR_CONTROL_0_CURSOR_DVFS_ENABLE_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_DVFS_CURSOR_CONTROL_0_CURSOR_DVFS_ENABLE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_DISP_DVFS_CURSOR_CONTROL_0_CURSOR_DVFS_ENABLE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_DVFS_CURSOR_CONTROL_0_CURSOR_DVFS_ENABLE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_DVFS_CURSOR_CONTROL_0_CURSOR_DVFS_ENABLE_INIT_ENUM DISABLE +#define DC_DISP_DVFS_CURSOR_CONTROL_0_CURSOR_DVFS_ENABLE_DISABLE _MK_ENUM_CONST(0) +#define DC_DISP_DVFS_CURSOR_CONTROL_0_CURSOR_DVFS_ENABLE_ENABLE _MK_ENUM_CONST(1) + + +// Register DC_DISP_CURSOR_UFLOW_DBG_PIXEL_0 +#define DC_DISP_CURSOR_UFLOW_DBG_PIXEL_0 _MK_ADDR_CONST(0x4f3) +#define DC_DISP_CURSOR_UFLOW_DBG_PIXEL_0_SECURE 0x0 +#define DC_DISP_CURSOR_UFLOW_DBG_PIXEL_0_WORD_COUNT 0x1 +#define DC_DISP_CURSOR_UFLOW_DBG_PIXEL_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_CURSOR_UFLOW_DBG_PIXEL_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_CURSOR_UFLOW_DBG_PIXEL_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_CURSOR_UFLOW_DBG_PIXEL_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_CURSOR_UFLOW_DBG_PIXEL_0_READ_MASK _MK_MASK_CONST(0xffffffff) +#define DC_DISP_CURSOR_UFLOW_DBG_PIXEL_0_WRITE_MASK _MK_MASK_CONST(0xffffffff) +#define DC_DISP_CURSOR_UFLOW_DBG_PIXEL_0_CURSOR_UFLOW_DBG_PIXEL_SHIFT _MK_SHIFT_CONST(0) +#define DC_DISP_CURSOR_UFLOW_DBG_PIXEL_0_CURSOR_UFLOW_DBG_PIXEL_FIELD _MK_FIELD_CONST(0xffffffff, DC_DISP_CURSOR_UFLOW_DBG_PIXEL_0_CURSOR_UFLOW_DBG_PIXEL_SHIFT) +#define DC_DISP_CURSOR_UFLOW_DBG_PIXEL_0_CURSOR_UFLOW_DBG_PIXEL_RANGE 31:0 +#define DC_DISP_CURSOR_UFLOW_DBG_PIXEL_0_CURSOR_UFLOW_DBG_PIXEL_WOFFSET 0x0 +#define DC_DISP_CURSOR_UFLOW_DBG_PIXEL_0_CURSOR_UFLOW_DBG_PIXEL_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_CURSOR_UFLOW_DBG_PIXEL_0_CURSOR_UFLOW_DBG_PIXEL_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_CURSOR_UFLOW_DBG_PIXEL_0_CURSOR_UFLOW_DBG_PIXEL_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_CURSOR_UFLOW_DBG_PIXEL_0_CURSOR_UFLOW_DBG_PIXEL_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_DISP_CURSOR_SPOOLUP_CONTROL_0 +#define DC_DISP_CURSOR_SPOOLUP_CONTROL_0 _MK_ADDR_CONST(0x4f4) +#define DC_DISP_CURSOR_SPOOLUP_CONTROL_0_SECURE 0x0 +#define DC_DISP_CURSOR_SPOOLUP_CONTROL_0_WORD_COUNT 0x1 +#define DC_DISP_CURSOR_SPOOLUP_CONTROL_0_RESET_VAL _MK_MASK_CONST(0x1) +#define DC_DISP_CURSOR_SPOOLUP_CONTROL_0_RESET_MASK _MK_MASK_CONST(0xff) +#define DC_DISP_CURSOR_SPOOLUP_CONTROL_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_CURSOR_SPOOLUP_CONTROL_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_CURSOR_SPOOLUP_CONTROL_0_READ_MASK _MK_MASK_CONST(0xff) +#define DC_DISP_CURSOR_SPOOLUP_CONTROL_0_WRITE_MASK _MK_MASK_CONST(0xff) +#define DC_DISP_CURSOR_SPOOLUP_CONTROL_0_CURSOR_SPOOLUP_START_SHIFT _MK_SHIFT_CONST(0) +#define DC_DISP_CURSOR_SPOOLUP_CONTROL_0_CURSOR_SPOOLUP_START_FIELD _MK_FIELD_CONST(0xff, DC_DISP_CURSOR_SPOOLUP_CONTROL_0_CURSOR_SPOOLUP_START_SHIFT) +#define DC_DISP_CURSOR_SPOOLUP_CONTROL_0_CURSOR_SPOOLUP_START_RANGE 7:0 +#define DC_DISP_CURSOR_SPOOLUP_CONTROL_0_CURSOR_SPOOLUP_START_WOFFSET 0x0 +#define DC_DISP_CURSOR_SPOOLUP_CONTROL_0_CURSOR_SPOOLUP_START_DEFAULT _MK_MASK_CONST(0x1) +#define DC_DISP_CURSOR_SPOOLUP_CONTROL_0_CURSOR_SPOOLUP_START_DEFAULT_MASK _MK_MASK_CONST(0xff) +#define DC_DISP_CURSOR_SPOOLUP_CONTROL_0_CURSOR_SPOOLUP_START_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_CURSOR_SPOOLUP_CONTROL_0_CURSOR_SPOOLUP_START_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_DISP_DISPLAY_CLK_GATE_OVERRIDE_0 +#define DC_DISP_DISPLAY_CLK_GATE_OVERRIDE_0 _MK_ADDR_CONST(0x4f5) +#define DC_DISP_DISPLAY_CLK_GATE_OVERRIDE_0_SECURE 0x0 +#define DC_DISP_DISPLAY_CLK_GATE_OVERRIDE_0_WORD_COUNT 0x1 +#define DC_DISP_DISPLAY_CLK_GATE_OVERRIDE_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_DISPLAY_CLK_GATE_OVERRIDE_0_RESET_MASK _MK_MASK_CONST(0x3) +#define DC_DISP_DISPLAY_CLK_GATE_OVERRIDE_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_DISPLAY_CLK_GATE_OVERRIDE_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_DISPLAY_CLK_GATE_OVERRIDE_0_READ_MASK _MK_MASK_CONST(0x3) +#define DC_DISP_DISPLAY_CLK_GATE_OVERRIDE_0_WRITE_MASK _MK_MASK_CONST(0x3) +#define DC_DISP_DISPLAY_CLK_GATE_OVERRIDE_0_CURSOR_CLK_GATE_OVERRIDE_SHIFT _MK_SHIFT_CONST(0) +#define DC_DISP_DISPLAY_CLK_GATE_OVERRIDE_0_CURSOR_CLK_GATE_OVERRIDE_FIELD _MK_FIELD_CONST(0x1, DC_DISP_DISPLAY_CLK_GATE_OVERRIDE_0_CURSOR_CLK_GATE_OVERRIDE_SHIFT) +#define DC_DISP_DISPLAY_CLK_GATE_OVERRIDE_0_CURSOR_CLK_GATE_OVERRIDE_RANGE 0:0 +#define DC_DISP_DISPLAY_CLK_GATE_OVERRIDE_0_CURSOR_CLK_GATE_OVERRIDE_WOFFSET 0x0 +#define DC_DISP_DISPLAY_CLK_GATE_OVERRIDE_0_CURSOR_CLK_GATE_OVERRIDE_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_DISPLAY_CLK_GATE_OVERRIDE_0_CURSOR_CLK_GATE_OVERRIDE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_DISP_DISPLAY_CLK_GATE_OVERRIDE_0_CURSOR_CLK_GATE_OVERRIDE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_DISPLAY_CLK_GATE_OVERRIDE_0_CURSOR_CLK_GATE_OVERRIDE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_DISPLAY_CLK_GATE_OVERRIDE_0_CURSOR_CLK_GATE_OVERRIDE_DISABLE _MK_ENUM_CONST(0) +#define DC_DISP_DISPLAY_CLK_GATE_OVERRIDE_0_CURSOR_CLK_GATE_OVERRIDE_ENABLE _MK_ENUM_CONST(1) + +#define DC_DISP_DISPLAY_CLK_GATE_OVERRIDE_0_CMU_CLK_GATE_OVERRIDE_SHIFT _MK_SHIFT_CONST(1) +#define DC_DISP_DISPLAY_CLK_GATE_OVERRIDE_0_CMU_CLK_GATE_OVERRIDE_FIELD _MK_FIELD_CONST(0x1, DC_DISP_DISPLAY_CLK_GATE_OVERRIDE_0_CMU_CLK_GATE_OVERRIDE_SHIFT) +#define DC_DISP_DISPLAY_CLK_GATE_OVERRIDE_0_CMU_CLK_GATE_OVERRIDE_RANGE 1:1 +#define DC_DISP_DISPLAY_CLK_GATE_OVERRIDE_0_CMU_CLK_GATE_OVERRIDE_WOFFSET 0x0 +#define DC_DISP_DISPLAY_CLK_GATE_OVERRIDE_0_CMU_CLK_GATE_OVERRIDE_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_DISPLAY_CLK_GATE_OVERRIDE_0_CMU_CLK_GATE_OVERRIDE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_DISP_DISPLAY_CLK_GATE_OVERRIDE_0_CMU_CLK_GATE_OVERRIDE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_DISPLAY_CLK_GATE_OVERRIDE_0_CMU_CLK_GATE_OVERRIDE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_DISPLAY_CLK_GATE_OVERRIDE_0_CMU_CLK_GATE_OVERRIDE_DISABLE _MK_ENUM_CONST(0) +#define DC_DISP_DISPLAY_CLK_GATE_OVERRIDE_0_CMU_CLK_GATE_OVERRIDE_ENABLE _MK_ENUM_CONST(1) + + +// Register DC_DISP_DISPLAY_DBG_TIMING_0 +#define DC_DISP_DISPLAY_DBG_TIMING_0 _MK_ADDR_CONST(0x4f6) +#define DC_DISP_DISPLAY_DBG_TIMING_0_SECURE 0x0 +#define DC_DISP_DISPLAY_DBG_TIMING_0_WORD_COUNT 0x1 +#define DC_DISP_DISPLAY_DBG_TIMING_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_DISPLAY_DBG_TIMING_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_DISPLAY_DBG_TIMING_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_DISPLAY_DBG_TIMING_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_DISPLAY_DBG_TIMING_0_READ_MASK _MK_MASK_CONST(0x9fff9fff) +#define DC_DISP_DISPLAY_DBG_TIMING_0_WRITE_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_DISPLAY_DBG_TIMING_0_V_COUNT_SHIFT _MK_SHIFT_CONST(0) +#define DC_DISP_DISPLAY_DBG_TIMING_0_V_COUNT_FIELD _MK_FIELD_CONST(0x1fff, DC_DISP_DISPLAY_DBG_TIMING_0_V_COUNT_SHIFT) +#define DC_DISP_DISPLAY_DBG_TIMING_0_V_COUNT_RANGE 12:0 +#define DC_DISP_DISPLAY_DBG_TIMING_0_V_COUNT_WOFFSET 0x0 +#define DC_DISP_DISPLAY_DBG_TIMING_0_V_COUNT_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_DISPLAY_DBG_TIMING_0_V_COUNT_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_DISPLAY_DBG_TIMING_0_V_COUNT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_DISPLAY_DBG_TIMING_0_V_COUNT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_DISP_DISPLAY_DBG_TIMING_0_V_BLANK_SHIFT _MK_SHIFT_CONST(15) +#define DC_DISP_DISPLAY_DBG_TIMING_0_V_BLANK_FIELD _MK_FIELD_CONST(0x1, DC_DISP_DISPLAY_DBG_TIMING_0_V_BLANK_SHIFT) +#define DC_DISP_DISPLAY_DBG_TIMING_0_V_BLANK_RANGE 15:15 +#define DC_DISP_DISPLAY_DBG_TIMING_0_V_BLANK_WOFFSET 0x0 +#define DC_DISP_DISPLAY_DBG_TIMING_0_V_BLANK_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_DISPLAY_DBG_TIMING_0_V_BLANK_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_DISPLAY_DBG_TIMING_0_V_BLANK_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_DISPLAY_DBG_TIMING_0_V_BLANK_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_DISP_DISPLAY_DBG_TIMING_0_H_COUNT_SHIFT _MK_SHIFT_CONST(16) +#define DC_DISP_DISPLAY_DBG_TIMING_0_H_COUNT_FIELD _MK_FIELD_CONST(0x1fff, DC_DISP_DISPLAY_DBG_TIMING_0_H_COUNT_SHIFT) +#define DC_DISP_DISPLAY_DBG_TIMING_0_H_COUNT_RANGE 28:16 +#define DC_DISP_DISPLAY_DBG_TIMING_0_H_COUNT_WOFFSET 0x0 +#define DC_DISP_DISPLAY_DBG_TIMING_0_H_COUNT_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_DISPLAY_DBG_TIMING_0_H_COUNT_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_DISPLAY_DBG_TIMING_0_H_COUNT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_DISPLAY_DBG_TIMING_0_H_COUNT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_DISP_DISPLAY_DBG_TIMING_0_H_BLANK_SHIFT _MK_SHIFT_CONST(31) +#define DC_DISP_DISPLAY_DBG_TIMING_0_H_BLANK_FIELD _MK_FIELD_CONST(0x1, DC_DISP_DISPLAY_DBG_TIMING_0_H_BLANK_SHIFT) +#define DC_DISP_DISPLAY_DBG_TIMING_0_H_BLANK_RANGE 31:31 +#define DC_DISP_DISPLAY_DBG_TIMING_0_H_BLANK_WOFFSET 0x0 +#define DC_DISP_DISPLAY_DBG_TIMING_0_H_BLANK_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_DISPLAY_DBG_TIMING_0_H_BLANK_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_DISPLAY_DBG_TIMING_0_H_BLANK_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_DISPLAY_DBG_TIMING_0_H_BLANK_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_DISP_DISPLAY_SPARE0_0 +#define DC_DISP_DISPLAY_SPARE0_0 _MK_ADDR_CONST(0x4f7) +#define DC_DISP_DISPLAY_SPARE0_0_SECURE 0x0 +#define DC_DISP_DISPLAY_SPARE0_0_WORD_COUNT 0x1 +#define DC_DISP_DISPLAY_SPARE0_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_DISPLAY_SPARE0_0_RESET_MASK _MK_MASK_CONST(0xffffffff) +#define DC_DISP_DISPLAY_SPARE0_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_DISPLAY_SPARE0_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_DISPLAY_SPARE0_0_READ_MASK _MK_MASK_CONST(0xffffffff) +#define DC_DISP_DISPLAY_SPARE0_0_WRITE_MASK _MK_MASK_CONST(0xffffffff) +#define DC_DISP_DISPLAY_SPARE0_0_SCRATCH_0_SHIFT _MK_SHIFT_CONST(0) +#define DC_DISP_DISPLAY_SPARE0_0_SCRATCH_0_FIELD _MK_FIELD_CONST(0xffffffff, DC_DISP_DISPLAY_SPARE0_0_SCRATCH_0_SHIFT) +#define DC_DISP_DISPLAY_SPARE0_0_SCRATCH_0_RANGE 31:0 +#define DC_DISP_DISPLAY_SPARE0_0_SCRATCH_0_WOFFSET 0x0 +#define DC_DISP_DISPLAY_SPARE0_0_SCRATCH_0_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_DISPLAY_SPARE0_0_SCRATCH_0_DEFAULT_MASK _MK_MASK_CONST(0xffffffff) +#define DC_DISP_DISPLAY_SPARE0_0_SCRATCH_0_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_DISPLAY_SPARE0_0_SCRATCH_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_DISP_DISPLAY_SPARE1_0 +#define DC_DISP_DISPLAY_SPARE1_0 _MK_ADDR_CONST(0x4f8) +#define DC_DISP_DISPLAY_SPARE1_0_SECURE 0x0 +#define DC_DISP_DISPLAY_SPARE1_0_WORD_COUNT 0x1 +#define DC_DISP_DISPLAY_SPARE1_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_DISPLAY_SPARE1_0_RESET_MASK _MK_MASK_CONST(0xffffffff) +#define DC_DISP_DISPLAY_SPARE1_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_DISP_DISPLAY_SPARE1_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_DISP_DISPLAY_SPARE1_0_READ_MASK _MK_MASK_CONST(0xffffffff) +#define DC_DISP_DISPLAY_SPARE1_0_WRITE_MASK _MK_MASK_CONST(0xffffffff) +#define DC_DISP_DISPLAY_SPARE1_0_SCRATCH_1_SHIFT _MK_SHIFT_CONST(0) +#define DC_DISP_DISPLAY_SPARE1_0_SCRATCH_1_FIELD _MK_FIELD_CONST(0xffffffff, DC_DISP_DISPLAY_SPARE1_0_SCRATCH_1_SHIFT) +#define DC_DISP_DISPLAY_SPARE1_0_SCRATCH_1_RANGE 31:0 +#define DC_DISP_DISPLAY_SPARE1_0_SCRATCH_1_WOFFSET 0x0 +#define DC_DISP_DISPLAY_SPARE1_0_SCRATCH_1_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_DISPLAY_SPARE1_0_SCRATCH_1_DEFAULT_MASK _MK_MASK_CONST(0xffffffff) +#define DC_DISP_DISPLAY_SPARE1_0_SCRATCH_1_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_DISP_DISPLAY_SPARE1_0_SCRATCH_1_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Reserved address 1273 [0x4f9] + +// Reserved address 1274 [0x4fa] + +// Reserved address 1275 [0x4fb] + +// Reserved address 1276 [0x4fc] + +// Reserved address 1277 [0x4fd] + +// +// REGISTER LIST +// +#define LIST_ARDISPLAY_REGS(_op_) \ +_op_(DC_CMD_GENERAL_INCR_SYNCPT_0) \ +_op_(DC_CMD_GENERAL_INCR_SYNCPT_CNTRL_0) \ +_op_(DC_CMD_GENERAL_INCR_SYNCPT_ERROR_0) \ +_op_(DC_CMD_WIN_A_INCR_SYNCPT_0) \ +_op_(DC_CMD_WIN_A_INCR_SYNCPT_CNTRL_0) \ +_op_(DC_CMD_WIN_A_INCR_SYNCPT_ERROR_0) \ +_op_(DC_CMD_WIN_B_INCR_SYNCPT_0) \ +_op_(DC_CMD_WIN_B_INCR_SYNCPT_CNTRL_0) \ +_op_(DC_CMD_WIN_B_INCR_SYNCPT_ERROR_0) \ +_op_(DC_CMD_WIN_C_INCR_SYNCPT_0) \ +_op_(DC_CMD_WIN_C_INCR_SYNCPT_CNTRL_0) \ +_op_(DC_CMD_WIN_C_INCR_SYNCPT_ERROR_0) \ +_op_(DC_CMD_CONT_SYNCPT_VSYNC_0) \ +_op_(DC_CMD_CTXSW_0) \ +_op_(DC_CMD_DISPLAY_COMMAND_OPTION0_0) \ +_op_(DC_CMD_DISPLAY_COMMAND_0) \ +_op_(DC_CMD_SIGNAL_RAISE_0) \ +_op_(DC_CMD_DISPLAY_POWER_CONTROL_0) \ +_op_(DC_CMD_INT_STATUS_0) \ +_op_(DC_CMD_INT_MASK_0) \ +_op_(DC_CMD_INT_ENABLE_0) \ +_op_(DC_CMD_INT_TYPE_0) \ +_op_(DC_CMD_INT_POLARITY_0) \ +_op_(DC_CMD_SIGNAL_RAISE1_0) \ +_op_(DC_CMD_SIGNAL_RAISE2_0) \ +_op_(DC_CMD_SIGNAL_RAISE3_0) \ +_op_(DC_CMD_STATE_ACCESS_0) \ +_op_(DC_CMD_STATE_CONTROL_0) \ +_op_(DC_CMD_DISPLAY_WINDOW_HEADER_0) \ +_op_(DC_CMD_REG_ACT_CONTROL_0) \ +_op_(DC_CMD_WIN_T_STATE_CONTROL_0) \ +_op_(DC_CMD_SECURE_CONTROL_0) \ +_op_(DC_CMD_WIN_D_INCR_SYNCPT_0) \ +_op_(DC_CMD_WIN_D_INCR_SYNCPT_CNTRL_0) \ +_op_(DC_CMD_WIN_D_INCR_SYNCPT_ERROR_0) \ +_op_(DC_COM_CRC_CONTROL_0) \ +_op_(DC_COM_CRC_CHECKSUM_0) \ +_op_(DC_COM_PIN_OUTPUT_ENABLE0_0) \ +_op_(DC_COM_PIN_OUTPUT_ENABLE1_0) \ +_op_(DC_COM_PIN_OUTPUT_ENABLE2_0) \ +_op_(DC_COM_PIN_OUTPUT_ENABLE3_0) \ +_op_(DC_COM_PIN_OUTPUT_POLARITY0_0) \ +_op_(DC_COM_PIN_OUTPUT_POLARITY1_0) \ +_op_(DC_COM_PIN_OUTPUT_POLARITY2_0) \ +_op_(DC_COM_PIN_OUTPUT_POLARITY3_0) \ +_op_(DC_COM_PIN_OUTPUT_DATA0_0) \ +_op_(DC_COM_PIN_OUTPUT_DATA1_0) \ +_op_(DC_COM_PIN_OUTPUT_DATA2_0) \ +_op_(DC_COM_PIN_OUTPUT_DATA3_0) \ +_op_(DC_COM_PIN_INPUT_DATA0_0) \ +_op_(DC_COM_PIN_INPUT_DATA1_0) \ +_op_(DC_COM_PIN_OUTPUT_SELECT0_0) \ +_op_(DC_COM_PIN_OUTPUT_SELECT1_0) \ +_op_(DC_COM_PIN_OUTPUT_SELECT2_0) \ +_op_(DC_COM_PIN_OUTPUT_SELECT3_0) \ +_op_(DC_COM_PIN_OUTPUT_SELECT4_0) \ +_op_(DC_COM_PIN_OUTPUT_SELECT5_0) \ +_op_(DC_COM_PIN_OUTPUT_SELECT6_0) \ +_op_(DC_COM_PIN_MISC_CONTROL_0) \ +_op_(DC_COM_PM0_CONTROL_0) \ +_op_(DC_COM_PM0_DUTY_CYCLE_0) \ +_op_(DC_COM_PM1_CONTROL_0) \ +_op_(DC_COM_PM1_DUTY_CYCLE_0) \ +_op_(DC_COM_SPI_CONTROL_0) \ +_op_(DC_COM_SPI_START_BYTE_0) \ +_op_(DC_COM_HSPI_WRITE_DATA_AB_0) \ +_op_(DC_COM_HSPI_WRITE_DATA_CD_0) \ +_op_(DC_COM_HSPI_CS_DC_0) \ +_op_(DC_COM_SCRATCH_REGISTER_A_0) \ +_op_(DC_COM_SCRATCH_REGISTER_B_0) \ +_op_(DC_COM_CRC_CHECKSUM_LATCHED_0) \ +_op_(DC_COM_CMU_CSC_KRR_0) \ +_op_(DC_COM_CMU_CSC_KGR_0) \ +_op_(DC_COM_CMU_CSC_KBR_0) \ +_op_(DC_COM_CMU_CSC_KRG_0) \ +_op_(DC_COM_CMU_CSC_KGG_0) \ +_op_(DC_COM_CMU_CSC_KBG_0) \ +_op_(DC_COM_CMU_CSC_KRB_0) \ +_op_(DC_COM_CMU_CSC_KGB_0) \ +_op_(DC_COM_CMU_CSC_KBB_0) \ +_op_(DC_COM_CMU_LUT_MASK_0) \ +_op_(DC_COM_CMU_LUT1_0) \ +_op_(DC_COM_CMU_LUT2_0) \ +_op_(DC_COM_CMU_LUT1_READ_0) \ +_op_(DC_COM_CMU_LUT2_READ_0) \ +_op_(DC_DISP_DISP_SIGNAL_OPTIONS0_0) \ +_op_(DC_DISP_DISP_SIGNAL_OPTIONS1_0) \ +_op_(DC_DISP_DISP_WIN_OPTIONS_0) \ +_op_(DC_DISP_MEM_HIGH_PRIORITY_0) \ +_op_(DC_DISP_MEM_HIGH_PRIORITY_TIMER_0) \ +_op_(DC_DISP_DISP_TIMING_OPTIONS_0) \ +_op_(DC_DISP_REF_TO_SYNC_0) \ +_op_(DC_DISP_SYNC_WIDTH_0) \ +_op_(DC_DISP_BACK_PORCH_0) \ +_op_(DC_DISP_DISP_ACTIVE_0) \ +_op_(DC_DISP_FRONT_PORCH_0) \ +_op_(DC_DISP_H_PULSE0_CONTROL_0) \ +_op_(DC_DISP_H_PULSE0_POSITION_A_0) \ +_op_(DC_DISP_H_PULSE0_POSITION_B_0) \ +_op_(DC_DISP_H_PULSE0_POSITION_C_0) \ +_op_(DC_DISP_H_PULSE0_POSITION_D_0) \ +_op_(DC_DISP_H_PULSE1_CONTROL_0) \ +_op_(DC_DISP_H_PULSE1_POSITION_A_0) \ +_op_(DC_DISP_H_PULSE1_POSITION_B_0) \ +_op_(DC_DISP_H_PULSE1_POSITION_C_0) \ +_op_(DC_DISP_H_PULSE1_POSITION_D_0) \ +_op_(DC_DISP_H_PULSE2_CONTROL_0) \ +_op_(DC_DISP_H_PULSE2_POSITION_A_0) \ +_op_(DC_DISP_H_PULSE2_POSITION_B_0) \ +_op_(DC_DISP_H_PULSE2_POSITION_C_0) \ +_op_(DC_DISP_H_PULSE2_POSITION_D_0) \ +_op_(DC_DISP_V_PULSE0_CONTROL_0) \ +_op_(DC_DISP_V_PULSE0_POSITION_A_0) \ +_op_(DC_DISP_V_PULSE0_POSITION_B_0) \ +_op_(DC_DISP_V_PULSE0_POSITION_C_0) \ +_op_(DC_DISP_V_PULSE1_CONTROL_0) \ +_op_(DC_DISP_V_PULSE1_POSITION_A_0) \ +_op_(DC_DISP_V_PULSE1_POSITION_B_0) \ +_op_(DC_DISP_V_PULSE1_POSITION_C_0) \ +_op_(DC_DISP_V_PULSE2_CONTROL_0) \ +_op_(DC_DISP_V_PULSE2_POSITION_A_0) \ +_op_(DC_DISP_V_PULSE3_CONTROL_0) \ +_op_(DC_DISP_V_PULSE3_POSITION_A_0) \ +_op_(DC_DISP_M0_CONTROL_0) \ +_op_(DC_DISP_M1_CONTROL_0) \ +_op_(DC_DISP_DI_CONTROL_0) \ +_op_(DC_DISP_PP_CONTROL_0) \ +_op_(DC_DISP_PP_SELECT_A_0) \ +_op_(DC_DISP_PP_SELECT_B_0) \ +_op_(DC_DISP_PP_SELECT_C_0) \ +_op_(DC_DISP_PP_SELECT_D_0) \ +_op_(DC_DISP_DISP_CLOCK_CONTROL_0) \ +_op_(DC_DISP_DISP_INTERFACE_CONTROL_0) \ +_op_(DC_DISP_DISP_COLOR_CONTROL_0) \ +_op_(DC_DISP_SHIFT_CLOCK_OPTIONS_0) \ +_op_(DC_DISP_DATA_ENABLE_OPTIONS_0) \ +_op_(DC_DISP_SERIAL_INTERFACE_OPTIONS_0) \ +_op_(DC_DISP_LCD_SPI_OPTIONS_0) \ +_op_(DC_DISP_COLOR_KEY0_LOWER_0) \ +_op_(DC_DISP_COLOR_KEY0_UPPER_0) \ +_op_(DC_DISP_COLOR_KEY1_LOWER_0) \ +_op_(DC_DISP_COLOR_KEY1_UPPER_0) \ +_op_(DC_DISP_CURSOR_FOREGROUND_0) \ +_op_(DC_DISP_CURSOR_BACKGROUND_0) \ +_op_(DC_DISP_CURSOR_START_ADDR_0) \ +_op_(DC_DISP_CURSOR_START_ADDR_NS_0) \ +_op_(DC_DISP_CURSOR_POSITION_0) \ +_op_(DC_DISP_CURSOR_POSITION_NS_0) \ +_op_(DC_DISP_INIT_SEQ_CONTROL_0) \ +_op_(DC_DISP_SPI_INIT_SEQ_DATA_A_0) \ +_op_(DC_DISP_SPI_INIT_SEQ_DATA_B_0) \ +_op_(DC_DISP_SPI_INIT_SEQ_DATA_C_0) \ +_op_(DC_DISP_SPI_INIT_SEQ_DATA_D_0) \ +_op_(DC_DISP_DC_MCCIF_FIFOCTRL_0) \ +_op_(DC_DISP_MCCIF_DISPLAY0A_HYST_0) \ +_op_(DC_DISP_MCCIF_DISPLAY0B_HYST_0) \ +_op_(DC_DISP_MCCIF_DISPLAY0C_HYST_0) \ +_op_(DC_DISP_DISP_MISC_CONTROL_0) \ +_op_(DC_DISP_SD_CONTROL_0) \ +_op_(DC_DISP_SD_CSC_COEFF_0) \ +_op_(DC_DISP_SD_LUT_0) \ +_op_(DC_DISP_SD_LUT) \ +_op_(DC_DISP_SD_LUT_1) \ +_op_(DC_DISP_SD_LUT_2) \ +_op_(DC_DISP_SD_LUT_3) \ +_op_(DC_DISP_SD_LUT_4) \ +_op_(DC_DISP_SD_LUT_5) \ +_op_(DC_DISP_SD_LUT_6) \ +_op_(DC_DISP_SD_LUT_7) \ +_op_(DC_DISP_SD_LUT_8) \ +_op_(DC_DISP_SD_FLICKER_CONTROL_0) \ +_op_(DC_DISP_SD_PIXEL_COUNT_0) \ +_op_(DC_DISP_SD_HISTOGRAM_0) \ +_op_(DC_DISP_SD_HISTOGRAM) \ +_op_(DC_DISP_SD_HISTOGRAM_1) \ +_op_(DC_DISP_SD_HISTOGRAM_2) \ +_op_(DC_DISP_SD_HISTOGRAM_3) \ +_op_(DC_DISP_SD_HISTOGRAM_4) \ +_op_(DC_DISP_SD_HISTOGRAM_5) \ +_op_(DC_DISP_SD_HISTOGRAM_6) \ +_op_(DC_DISP_SD_HISTOGRAM_7) \ +_op_(DC_DISP_SD_BL_PARAMETERS_0) \ +_op_(DC_DISP_SD_BL_TF_0) \ +_op_(DC_DISP_SD_BL_TF) \ +_op_(DC_DISP_SD_BL_TF_1) \ +_op_(DC_DISP_SD_BL_TF_2) \ +_op_(DC_DISP_SD_BL_TF_3) \ +_op_(DC_DISP_SD_BL_CONTROL_0) \ +_op_(DC_DISP_SD_HW_K_VALUES_0) \ +_op_(DC_DISP_SD_MAN_K_VALUES_0) \ +_op_(DC_DISP_SD_K_LIMIT_0) \ +_op_(DC_DISP_SD_WINDOW_POSITION_0) \ +_op_(DC_DISP_SD_WINDOW_SIZE_0) \ +_op_(DC_DISP_SD_SOFT_CLIPPING_0) \ +_op_(DC_DISP_SD_SMOOTH_K_0) \ +_op_(DC_DISP_BLEND_BACKGROUND_COLOR_0) \ +_op_(DC_DISP_INTERLACE_CONTROL_0) \ +_op_(DC_DISP_INTERLACE_FIELD2_REF_TO_SYNC_0) \ +_op_(DC_DISP_INTERLACE_FIELD2_SYNC_WIDTH_0) \ +_op_(DC_DISP_INTERLACE_FIELD2_BACK_PORCH_0) \ +_op_(DC_DISP_INTERLACE_FIELD2_FRONT_PORCH_0) \ +_op_(DC_DISP_INTERLACE_FIELD2_DISP_ACTIVE_0) \ +_op_(DC_DISP_CURSOR_UNDERFLOW_CTRL_0) \ +_op_(DC_DISP_CURSOR_START_ADDR_HI_0) \ +_op_(DC_DISP_CURSOR_START_ADDR_HI_NS_0) \ +_op_(DC_DISP_CURSOR_INTERLACE_CONTROL_0) \ +_op_(DC_DISP_CSC2_CONTROL_0) \ +_op_(DC_DISP_BLEND_CURSOR_CONTROL_0) \ +_op_(DC_DISP_DVFS_CURSOR_CONTROL_0) \ +_op_(DC_DISP_CURSOR_UFLOW_DBG_PIXEL_0) \ +_op_(DC_DISP_CURSOR_SPOOLUP_CONTROL_0) \ +_op_(DC_DISP_DISPLAY_CLK_GATE_OVERRIDE_0) \ +_op_(DC_DISP_DISPLAY_DBG_TIMING_0) \ +_op_(DC_DISP_DISPLAY_SPARE0_0) \ +_op_(DC_DISP_DISPLAY_SPARE1_0) + + +// +// ADDRESS SPACES +// + +#define BASE_ADDRESS_DC_CMD 0x00000000 +#define BASE_ADDRESS_DC_COM 0x00000300 +#define BASE_ADDRESS_DC_DISP 0x00000400 + +// +// ARDISPLAY REGISTER BANKS +// + +#define DC_CMD0_FIRST_REG 0x0000 // DC_CMD_GENERAL_INCR_SYNCPT_0 +#define DC_CMD0_LAST_REG 0x0002 // DC_CMD_GENERAL_INCR_SYNCPT_ERROR_0 +#define DC_CMD1_FIRST_REG 0x0008 // DC_CMD_WIN_A_INCR_SYNCPT_0 +#define DC_CMD1_LAST_REG 0x000a // DC_CMD_WIN_A_INCR_SYNCPT_ERROR_0 +#define DC_CMD2_FIRST_REG 0x0010 // DC_CMD_WIN_B_INCR_SYNCPT_0 +#define DC_CMD2_LAST_REG 0x0012 // DC_CMD_WIN_B_INCR_SYNCPT_ERROR_0 +#define DC_CMD3_FIRST_REG 0x0018 // DC_CMD_WIN_C_INCR_SYNCPT_0 +#define DC_CMD3_LAST_REG 0x001a // DC_CMD_WIN_C_INCR_SYNCPT_ERROR_0 +#define DC_CMD4_FIRST_REG 0x0028 // DC_CMD_CONT_SYNCPT_VSYNC_0 +#define DC_CMD4_LAST_REG 0x0028 // DC_CMD_CONT_SYNCPT_VSYNC_0 +#define DC_CMD5_FIRST_REG 0x0030 // DC_CMD_CTXSW_0 +#define DC_CMD5_LAST_REG 0x0033 // DC_CMD_SIGNAL_RAISE_0 +#define DC_CMD6_FIRST_REG 0x0036 // DC_CMD_DISPLAY_POWER_CONTROL_0 +#define DC_CMD6_LAST_REG 0x003e // DC_CMD_SIGNAL_RAISE3_0 +#define DC_CMD7_FIRST_REG 0x0040 // DC_CMD_STATE_ACCESS_0 +#define DC_CMD7_LAST_REG 0x0045 // DC_CMD_SECURE_CONTROL_0 +#define DC_CMD8_FIRST_REG 0x004c // DC_CMD_WIN_D_INCR_SYNCPT_0 +#define DC_CMD8_LAST_REG 0x004e // DC_CMD_WIN_D_INCR_SYNCPT_ERROR_0 +#define DC_COM0_FIRST_REG 0x0300 // DC_COM_CRC_CONTROL_0 +#define DC_COM0_LAST_REG 0x030d // DC_COM_PIN_OUTPUT_DATA3_0 +#define DC_COM1_FIRST_REG 0x0312 // DC_COM_PIN_INPUT_DATA0_0 +#define DC_COM1_LAST_REG 0x0326 // DC_COM_SCRATCH_REGISTER_B_0 +#define DC_COM2_FIRST_REG 0x0329 // DC_COM_CRC_CHECKSUM_LATCHED_0 +#define DC_COM2_LAST_REG 0x0333 // DC_COM_CMU_LUT_MASK_0 +#define DC_COM3_FIRST_REG 0x0336 // DC_COM_CMU_LUT1_0 +#define DC_COM3_LAST_REG 0x0339 // DC_COM_CMU_LUT2_READ_0 +#define DC_DISP0_FIRST_REG 0x0400 // DC_DISP_DISP_SIGNAL_OPTIONS0_0 +#define DC_DISP0_LAST_REG 0x0434 // DC_DISP_LCD_SPI_OPTIONS_0 +#define DC_DISP1_FIRST_REG 0x0436 // DC_DISP_COLOR_KEY0_LOWER_0 +#define DC_DISP1_LAST_REG 0x0439 // DC_DISP_COLOR_KEY1_UPPER_0 +#define DC_DISP2_FIRST_REG 0x043c // DC_DISP_CURSOR_FOREGROUND_0 +#define DC_DISP2_LAST_REG 0x0446 // DC_DISP_SPI_INIT_SEQ_DATA_D_0 +#define DC_DISP3_FIRST_REG 0x0480 // DC_DISP_DC_MCCIF_FIFOCTRL_0 +#define DC_DISP3_LAST_REG 0x0483 // DC_DISP_MCCIF_DISPLAY0C_HYST_0 +#define DC_DISP4_FIRST_REG 0x04c1 // DC_DISP_DISP_MISC_CONTROL_0 +#define DC_DISP4_LAST_REG 0x04ef // DC_DISP_CSC2_CONTROL_0 +#define DC_DISP5_FIRST_REG 0x04f1 // DC_DISP_BLEND_CURSOR_CONTROL_0 +#define DC_DISP5_LAST_REG 0x04f8 // DC_DISP_DISPLAY_SPARE1_0 + +// To satisfy various compilers and platforms, +// we let users control the types and syntax of certain constants, using macros. +#ifndef _MK_SHIFT_CONST + #define _MK_SHIFT_CONST(_constant_) _constant_ +#endif +#ifndef _MK_MASK_CONST + #define _MK_MASK_CONST(_constant_) _constant_ +#endif +#ifndef _MK_ENUM_CONST + #define _MK_ENUM_CONST(_constant_) (_constant_ ## UL) +#endif +#ifndef _MK_ADDR_CONST + #define _MK_ADDR_CONST(_constant_) _constant_ +#endif +#ifndef _MK_FIELD_CONST + #define _MK_FIELD_CONST(_mask_, _shift_) (_MK_MASK_CONST(_mask_) << _MK_SHIFT_CONST(_shift_)) +#endif + +#endif + // ifndef ___ARDISPLAY_H_INC_ +// +// Copyright (c) 2013 NVIDIA Corporation. +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// +// Neither the name of the NVIDIA Corporation nor the names of its contributors +// may be used to endorse or promote products derived from this software +// without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// + +// +// DO NOT EDIT - generated by simspec! +// + +#ifndef ___ARDISPLAY_A_H_INC_ +#define ___ARDISPLAY_A_H_INC_ + +// Ram DC_WINC_A_COLOR_PALETTE_0 +#define DC_WINC_A_COLOR_PALETTE_0 _MK_ADDR_CONST(0x500) +#define DC_WINC_A_COLOR_PALETTE_0_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_0_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_0_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_0_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_0_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_0_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_0_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_0_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_0_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_0_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_0_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_0_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_0_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_0_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_0_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_0_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_0_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_0_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_0_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_0_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_0_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_0_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_0_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_0_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_0_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_0_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_0_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_0_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_0_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_0_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_0_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE +#define DC_WINC_A_COLOR_PALETTE _MK_ADDR_CONST(0x500) +#define DC_WINC_A_COLOR_PALETTE_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_1 +#define DC_WINC_A_COLOR_PALETTE_1 _MK_ADDR_CONST(0x501) +#define DC_WINC_A_COLOR_PALETTE_1_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_1_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_1_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_1_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_1_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_1_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_1_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_1_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_1_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_1_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_1_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_1_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_1_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_1_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_1_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_1_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_1_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_1_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_1_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_1_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_1_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_1_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_1_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_1_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_1_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_1_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_1_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_1_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_1_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_1_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_1_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_1_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_1_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_1_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_1_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_2 +#define DC_WINC_A_COLOR_PALETTE_2 _MK_ADDR_CONST(0x502) +#define DC_WINC_A_COLOR_PALETTE_2_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_2_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_2_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_2_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_2_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_2_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_2_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_2_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_2_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_2_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_2_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_2_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_2_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_2_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_2_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_2_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_2_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_2_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_2_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_2_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_2_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_2_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_2_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_2_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_2_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_2_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_2_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_2_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_2_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_2_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_2_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_2_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_2_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_2_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_2_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_3 +#define DC_WINC_A_COLOR_PALETTE_3 _MK_ADDR_CONST(0x503) +#define DC_WINC_A_COLOR_PALETTE_3_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_3_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_3_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_3_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_3_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_3_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_3_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_3_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_3_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_3_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_3_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_3_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_3_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_3_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_3_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_3_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_3_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_3_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_3_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_3_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_3_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_3_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_3_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_3_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_3_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_3_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_3_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_3_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_3_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_3_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_3_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_3_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_3_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_3_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_3_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_4 +#define DC_WINC_A_COLOR_PALETTE_4 _MK_ADDR_CONST(0x504) +#define DC_WINC_A_COLOR_PALETTE_4_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_4_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_4_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_4_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_4_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_4_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_4_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_4_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_4_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_4_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_4_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_4_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_4_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_4_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_4_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_4_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_4_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_4_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_4_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_4_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_4_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_4_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_4_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_4_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_4_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_4_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_4_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_4_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_4_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_4_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_4_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_4_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_4_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_4_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_4_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_5 +#define DC_WINC_A_COLOR_PALETTE_5 _MK_ADDR_CONST(0x505) +#define DC_WINC_A_COLOR_PALETTE_5_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_5_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_5_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_5_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_5_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_5_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_5_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_5_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_5_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_5_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_5_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_5_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_5_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_5_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_5_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_5_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_5_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_5_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_5_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_5_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_5_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_5_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_5_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_5_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_5_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_5_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_5_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_5_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_5_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_5_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_5_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_5_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_5_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_5_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_5_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_6 +#define DC_WINC_A_COLOR_PALETTE_6 _MK_ADDR_CONST(0x506) +#define DC_WINC_A_COLOR_PALETTE_6_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_6_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_6_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_6_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_6_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_6_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_6_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_6_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_6_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_6_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_6_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_6_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_6_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_6_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_6_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_6_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_6_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_6_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_6_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_6_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_6_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_6_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_6_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_6_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_6_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_6_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_6_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_6_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_6_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_6_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_6_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_6_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_6_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_6_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_6_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_7 +#define DC_WINC_A_COLOR_PALETTE_7 _MK_ADDR_CONST(0x507) +#define DC_WINC_A_COLOR_PALETTE_7_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_7_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_7_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_7_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_7_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_7_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_7_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_7_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_7_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_7_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_7_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_7_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_7_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_7_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_7_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_7_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_7_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_7_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_7_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_7_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_7_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_7_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_7_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_7_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_7_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_7_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_7_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_7_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_7_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_7_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_7_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_7_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_7_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_7_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_7_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_8 +#define DC_WINC_A_COLOR_PALETTE_8 _MK_ADDR_CONST(0x508) +#define DC_WINC_A_COLOR_PALETTE_8_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_8_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_8_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_8_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_8_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_8_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_8_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_8_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_8_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_8_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_8_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_8_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_8_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_8_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_8_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_8_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_8_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_8_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_8_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_8_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_8_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_8_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_8_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_8_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_8_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_8_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_8_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_8_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_8_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_8_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_8_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_8_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_8_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_8_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_8_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_9 +#define DC_WINC_A_COLOR_PALETTE_9 _MK_ADDR_CONST(0x509) +#define DC_WINC_A_COLOR_PALETTE_9_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_9_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_9_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_9_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_9_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_9_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_9_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_9_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_9_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_9_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_9_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_9_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_9_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_9_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_9_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_9_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_9_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_9_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_9_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_9_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_9_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_9_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_9_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_9_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_9_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_9_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_9_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_9_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_9_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_9_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_9_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_9_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_9_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_9_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_9_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_10 +#define DC_WINC_A_COLOR_PALETTE_10 _MK_ADDR_CONST(0x50a) +#define DC_WINC_A_COLOR_PALETTE_10_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_10_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_10_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_10_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_10_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_10_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_10_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_10_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_10_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_10_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_10_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_10_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_10_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_10_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_10_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_10_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_10_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_10_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_10_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_10_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_10_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_10_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_10_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_10_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_10_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_10_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_10_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_10_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_10_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_10_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_10_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_10_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_10_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_10_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_10_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_11 +#define DC_WINC_A_COLOR_PALETTE_11 _MK_ADDR_CONST(0x50b) +#define DC_WINC_A_COLOR_PALETTE_11_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_11_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_11_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_11_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_11_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_11_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_11_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_11_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_11_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_11_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_11_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_11_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_11_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_11_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_11_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_11_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_11_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_11_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_11_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_11_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_11_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_11_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_11_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_11_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_11_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_11_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_11_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_11_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_11_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_11_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_11_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_11_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_11_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_11_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_11_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_12 +#define DC_WINC_A_COLOR_PALETTE_12 _MK_ADDR_CONST(0x50c) +#define DC_WINC_A_COLOR_PALETTE_12_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_12_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_12_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_12_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_12_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_12_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_12_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_12_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_12_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_12_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_12_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_12_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_12_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_12_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_12_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_12_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_12_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_12_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_12_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_12_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_12_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_12_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_12_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_12_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_12_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_12_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_12_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_12_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_12_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_12_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_12_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_12_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_12_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_12_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_12_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_13 +#define DC_WINC_A_COLOR_PALETTE_13 _MK_ADDR_CONST(0x50d) +#define DC_WINC_A_COLOR_PALETTE_13_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_13_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_13_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_13_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_13_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_13_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_13_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_13_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_13_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_13_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_13_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_13_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_13_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_13_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_13_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_13_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_13_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_13_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_13_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_13_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_13_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_13_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_13_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_13_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_13_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_13_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_13_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_13_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_13_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_13_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_13_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_13_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_13_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_13_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_13_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_14 +#define DC_WINC_A_COLOR_PALETTE_14 _MK_ADDR_CONST(0x50e) +#define DC_WINC_A_COLOR_PALETTE_14_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_14_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_14_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_14_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_14_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_14_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_14_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_14_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_14_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_14_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_14_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_14_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_14_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_14_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_14_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_14_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_14_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_14_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_14_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_14_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_14_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_14_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_14_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_14_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_14_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_14_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_14_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_14_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_14_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_14_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_14_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_14_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_14_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_14_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_14_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_15 +#define DC_WINC_A_COLOR_PALETTE_15 _MK_ADDR_CONST(0x50f) +#define DC_WINC_A_COLOR_PALETTE_15_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_15_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_15_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_15_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_15_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_15_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_15_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_15_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_15_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_15_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_15_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_15_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_15_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_15_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_15_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_15_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_15_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_15_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_15_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_15_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_15_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_15_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_15_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_15_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_15_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_15_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_15_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_15_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_15_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_15_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_15_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_15_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_15_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_15_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_15_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_16 +#define DC_WINC_A_COLOR_PALETTE_16 _MK_ADDR_CONST(0x510) +#define DC_WINC_A_COLOR_PALETTE_16_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_16_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_16_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_16_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_16_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_16_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_16_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_16_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_16_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_16_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_16_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_16_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_16_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_16_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_16_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_16_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_16_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_16_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_16_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_16_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_16_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_16_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_16_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_16_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_16_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_16_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_16_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_16_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_16_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_16_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_16_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_16_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_16_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_16_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_16_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_17 +#define DC_WINC_A_COLOR_PALETTE_17 _MK_ADDR_CONST(0x511) +#define DC_WINC_A_COLOR_PALETTE_17_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_17_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_17_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_17_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_17_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_17_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_17_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_17_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_17_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_17_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_17_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_17_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_17_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_17_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_17_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_17_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_17_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_17_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_17_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_17_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_17_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_17_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_17_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_17_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_17_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_17_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_17_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_17_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_17_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_17_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_17_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_17_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_17_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_17_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_17_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_18 +#define DC_WINC_A_COLOR_PALETTE_18 _MK_ADDR_CONST(0x512) +#define DC_WINC_A_COLOR_PALETTE_18_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_18_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_18_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_18_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_18_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_18_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_18_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_18_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_18_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_18_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_18_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_18_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_18_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_18_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_18_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_18_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_18_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_18_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_18_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_18_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_18_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_18_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_18_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_18_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_18_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_18_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_18_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_18_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_18_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_18_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_18_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_18_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_18_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_18_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_18_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_19 +#define DC_WINC_A_COLOR_PALETTE_19 _MK_ADDR_CONST(0x513) +#define DC_WINC_A_COLOR_PALETTE_19_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_19_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_19_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_19_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_19_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_19_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_19_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_19_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_19_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_19_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_19_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_19_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_19_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_19_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_19_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_19_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_19_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_19_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_19_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_19_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_19_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_19_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_19_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_19_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_19_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_19_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_19_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_19_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_19_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_19_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_19_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_19_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_19_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_19_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_19_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_20 +#define DC_WINC_A_COLOR_PALETTE_20 _MK_ADDR_CONST(0x514) +#define DC_WINC_A_COLOR_PALETTE_20_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_20_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_20_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_20_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_20_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_20_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_20_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_20_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_20_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_20_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_20_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_20_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_20_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_20_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_20_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_20_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_20_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_20_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_20_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_20_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_20_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_20_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_20_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_20_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_20_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_20_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_20_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_20_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_20_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_20_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_20_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_20_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_20_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_20_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_20_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_21 +#define DC_WINC_A_COLOR_PALETTE_21 _MK_ADDR_CONST(0x515) +#define DC_WINC_A_COLOR_PALETTE_21_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_21_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_21_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_21_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_21_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_21_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_21_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_21_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_21_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_21_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_21_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_21_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_21_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_21_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_21_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_21_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_21_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_21_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_21_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_21_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_21_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_21_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_21_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_21_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_21_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_21_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_21_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_21_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_21_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_21_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_21_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_21_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_21_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_21_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_21_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_22 +#define DC_WINC_A_COLOR_PALETTE_22 _MK_ADDR_CONST(0x516) +#define DC_WINC_A_COLOR_PALETTE_22_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_22_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_22_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_22_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_22_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_22_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_22_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_22_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_22_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_22_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_22_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_22_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_22_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_22_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_22_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_22_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_22_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_22_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_22_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_22_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_22_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_22_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_22_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_22_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_22_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_22_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_22_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_22_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_22_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_22_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_22_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_22_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_22_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_22_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_22_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_23 +#define DC_WINC_A_COLOR_PALETTE_23 _MK_ADDR_CONST(0x517) +#define DC_WINC_A_COLOR_PALETTE_23_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_23_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_23_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_23_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_23_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_23_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_23_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_23_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_23_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_23_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_23_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_23_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_23_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_23_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_23_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_23_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_23_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_23_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_23_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_23_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_23_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_23_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_23_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_23_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_23_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_23_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_23_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_23_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_23_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_23_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_23_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_23_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_23_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_23_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_23_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_24 +#define DC_WINC_A_COLOR_PALETTE_24 _MK_ADDR_CONST(0x518) +#define DC_WINC_A_COLOR_PALETTE_24_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_24_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_24_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_24_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_24_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_24_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_24_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_24_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_24_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_24_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_24_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_24_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_24_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_24_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_24_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_24_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_24_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_24_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_24_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_24_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_24_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_24_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_24_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_24_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_24_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_24_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_24_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_24_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_24_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_24_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_24_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_24_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_24_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_24_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_24_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_25 +#define DC_WINC_A_COLOR_PALETTE_25 _MK_ADDR_CONST(0x519) +#define DC_WINC_A_COLOR_PALETTE_25_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_25_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_25_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_25_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_25_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_25_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_25_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_25_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_25_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_25_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_25_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_25_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_25_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_25_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_25_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_25_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_25_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_25_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_25_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_25_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_25_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_25_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_25_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_25_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_25_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_25_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_25_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_25_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_25_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_25_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_25_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_25_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_25_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_25_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_25_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_26 +#define DC_WINC_A_COLOR_PALETTE_26 _MK_ADDR_CONST(0x51a) +#define DC_WINC_A_COLOR_PALETTE_26_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_26_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_26_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_26_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_26_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_26_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_26_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_26_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_26_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_26_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_26_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_26_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_26_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_26_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_26_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_26_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_26_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_26_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_26_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_26_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_26_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_26_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_26_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_26_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_26_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_26_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_26_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_26_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_26_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_26_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_26_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_26_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_26_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_26_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_26_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_27 +#define DC_WINC_A_COLOR_PALETTE_27 _MK_ADDR_CONST(0x51b) +#define DC_WINC_A_COLOR_PALETTE_27_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_27_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_27_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_27_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_27_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_27_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_27_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_27_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_27_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_27_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_27_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_27_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_27_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_27_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_27_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_27_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_27_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_27_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_27_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_27_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_27_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_27_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_27_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_27_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_27_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_27_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_27_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_27_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_27_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_27_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_27_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_27_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_27_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_27_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_27_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_28 +#define DC_WINC_A_COLOR_PALETTE_28 _MK_ADDR_CONST(0x51c) +#define DC_WINC_A_COLOR_PALETTE_28_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_28_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_28_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_28_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_28_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_28_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_28_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_28_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_28_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_28_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_28_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_28_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_28_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_28_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_28_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_28_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_28_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_28_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_28_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_28_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_28_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_28_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_28_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_28_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_28_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_28_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_28_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_28_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_28_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_28_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_28_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_28_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_28_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_28_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_28_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_29 +#define DC_WINC_A_COLOR_PALETTE_29 _MK_ADDR_CONST(0x51d) +#define DC_WINC_A_COLOR_PALETTE_29_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_29_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_29_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_29_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_29_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_29_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_29_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_29_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_29_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_29_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_29_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_29_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_29_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_29_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_29_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_29_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_29_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_29_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_29_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_29_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_29_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_29_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_29_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_29_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_29_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_29_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_29_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_29_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_29_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_29_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_29_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_29_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_29_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_29_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_29_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_30 +#define DC_WINC_A_COLOR_PALETTE_30 _MK_ADDR_CONST(0x51e) +#define DC_WINC_A_COLOR_PALETTE_30_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_30_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_30_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_30_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_30_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_30_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_30_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_30_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_30_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_30_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_30_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_30_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_30_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_30_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_30_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_30_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_30_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_30_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_30_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_30_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_30_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_30_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_30_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_30_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_30_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_30_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_30_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_30_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_30_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_30_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_30_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_30_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_30_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_30_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_30_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_31 +#define DC_WINC_A_COLOR_PALETTE_31 _MK_ADDR_CONST(0x51f) +#define DC_WINC_A_COLOR_PALETTE_31_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_31_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_31_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_31_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_31_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_31_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_31_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_31_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_31_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_31_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_31_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_31_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_31_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_31_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_31_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_31_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_31_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_31_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_31_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_31_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_31_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_31_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_31_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_31_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_31_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_31_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_31_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_31_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_31_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_31_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_31_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_31_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_31_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_31_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_31_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_32 +#define DC_WINC_A_COLOR_PALETTE_32 _MK_ADDR_CONST(0x520) +#define DC_WINC_A_COLOR_PALETTE_32_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_32_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_32_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_32_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_32_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_32_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_32_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_32_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_32_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_32_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_32_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_32_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_32_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_32_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_32_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_32_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_32_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_32_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_32_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_32_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_32_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_32_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_32_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_32_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_32_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_32_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_32_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_32_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_32_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_32_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_32_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_32_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_32_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_32_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_32_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_33 +#define DC_WINC_A_COLOR_PALETTE_33 _MK_ADDR_CONST(0x521) +#define DC_WINC_A_COLOR_PALETTE_33_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_33_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_33_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_33_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_33_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_33_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_33_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_33_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_33_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_33_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_33_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_33_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_33_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_33_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_33_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_33_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_33_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_33_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_33_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_33_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_33_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_33_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_33_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_33_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_33_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_33_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_33_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_33_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_33_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_33_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_33_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_33_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_33_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_33_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_33_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_34 +#define DC_WINC_A_COLOR_PALETTE_34 _MK_ADDR_CONST(0x522) +#define DC_WINC_A_COLOR_PALETTE_34_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_34_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_34_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_34_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_34_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_34_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_34_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_34_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_34_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_34_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_34_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_34_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_34_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_34_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_34_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_34_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_34_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_34_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_34_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_34_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_34_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_34_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_34_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_34_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_34_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_34_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_34_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_34_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_34_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_34_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_34_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_34_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_34_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_34_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_34_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_35 +#define DC_WINC_A_COLOR_PALETTE_35 _MK_ADDR_CONST(0x523) +#define DC_WINC_A_COLOR_PALETTE_35_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_35_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_35_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_35_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_35_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_35_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_35_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_35_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_35_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_35_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_35_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_35_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_35_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_35_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_35_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_35_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_35_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_35_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_35_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_35_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_35_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_35_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_35_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_35_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_35_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_35_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_35_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_35_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_35_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_35_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_35_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_35_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_35_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_35_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_35_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_36 +#define DC_WINC_A_COLOR_PALETTE_36 _MK_ADDR_CONST(0x524) +#define DC_WINC_A_COLOR_PALETTE_36_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_36_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_36_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_36_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_36_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_36_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_36_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_36_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_36_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_36_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_36_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_36_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_36_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_36_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_36_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_36_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_36_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_36_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_36_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_36_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_36_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_36_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_36_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_36_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_36_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_36_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_36_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_36_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_36_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_36_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_36_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_36_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_36_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_36_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_36_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_37 +#define DC_WINC_A_COLOR_PALETTE_37 _MK_ADDR_CONST(0x525) +#define DC_WINC_A_COLOR_PALETTE_37_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_37_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_37_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_37_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_37_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_37_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_37_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_37_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_37_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_37_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_37_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_37_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_37_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_37_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_37_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_37_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_37_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_37_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_37_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_37_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_37_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_37_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_37_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_37_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_37_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_37_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_37_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_37_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_37_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_37_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_37_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_37_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_37_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_37_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_37_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_38 +#define DC_WINC_A_COLOR_PALETTE_38 _MK_ADDR_CONST(0x526) +#define DC_WINC_A_COLOR_PALETTE_38_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_38_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_38_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_38_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_38_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_38_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_38_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_38_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_38_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_38_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_38_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_38_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_38_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_38_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_38_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_38_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_38_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_38_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_38_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_38_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_38_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_38_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_38_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_38_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_38_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_38_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_38_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_38_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_38_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_38_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_38_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_38_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_38_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_38_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_38_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_39 +#define DC_WINC_A_COLOR_PALETTE_39 _MK_ADDR_CONST(0x527) +#define DC_WINC_A_COLOR_PALETTE_39_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_39_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_39_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_39_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_39_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_39_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_39_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_39_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_39_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_39_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_39_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_39_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_39_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_39_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_39_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_39_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_39_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_39_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_39_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_39_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_39_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_39_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_39_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_39_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_39_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_39_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_39_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_39_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_39_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_39_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_39_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_39_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_39_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_39_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_39_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_40 +#define DC_WINC_A_COLOR_PALETTE_40 _MK_ADDR_CONST(0x528) +#define DC_WINC_A_COLOR_PALETTE_40_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_40_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_40_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_40_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_40_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_40_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_40_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_40_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_40_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_40_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_40_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_40_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_40_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_40_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_40_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_40_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_40_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_40_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_40_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_40_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_40_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_40_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_40_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_40_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_40_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_40_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_40_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_40_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_40_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_40_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_40_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_40_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_40_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_40_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_40_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_41 +#define DC_WINC_A_COLOR_PALETTE_41 _MK_ADDR_CONST(0x529) +#define DC_WINC_A_COLOR_PALETTE_41_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_41_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_41_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_41_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_41_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_41_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_41_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_41_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_41_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_41_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_41_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_41_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_41_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_41_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_41_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_41_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_41_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_41_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_41_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_41_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_41_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_41_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_41_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_41_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_41_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_41_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_41_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_41_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_41_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_41_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_41_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_41_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_41_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_41_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_41_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_42 +#define DC_WINC_A_COLOR_PALETTE_42 _MK_ADDR_CONST(0x52a) +#define DC_WINC_A_COLOR_PALETTE_42_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_42_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_42_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_42_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_42_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_42_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_42_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_42_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_42_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_42_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_42_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_42_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_42_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_42_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_42_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_42_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_42_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_42_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_42_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_42_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_42_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_42_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_42_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_42_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_42_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_42_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_42_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_42_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_42_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_42_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_42_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_42_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_42_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_42_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_42_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_43 +#define DC_WINC_A_COLOR_PALETTE_43 _MK_ADDR_CONST(0x52b) +#define DC_WINC_A_COLOR_PALETTE_43_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_43_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_43_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_43_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_43_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_43_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_43_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_43_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_43_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_43_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_43_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_43_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_43_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_43_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_43_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_43_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_43_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_43_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_43_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_43_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_43_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_43_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_43_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_43_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_43_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_43_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_43_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_43_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_43_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_43_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_43_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_43_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_43_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_43_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_43_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_44 +#define DC_WINC_A_COLOR_PALETTE_44 _MK_ADDR_CONST(0x52c) +#define DC_WINC_A_COLOR_PALETTE_44_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_44_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_44_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_44_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_44_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_44_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_44_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_44_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_44_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_44_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_44_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_44_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_44_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_44_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_44_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_44_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_44_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_44_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_44_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_44_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_44_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_44_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_44_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_44_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_44_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_44_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_44_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_44_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_44_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_44_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_44_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_44_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_44_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_44_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_44_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_45 +#define DC_WINC_A_COLOR_PALETTE_45 _MK_ADDR_CONST(0x52d) +#define DC_WINC_A_COLOR_PALETTE_45_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_45_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_45_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_45_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_45_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_45_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_45_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_45_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_45_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_45_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_45_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_45_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_45_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_45_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_45_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_45_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_45_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_45_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_45_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_45_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_45_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_45_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_45_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_45_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_45_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_45_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_45_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_45_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_45_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_45_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_45_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_45_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_45_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_45_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_45_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_46 +#define DC_WINC_A_COLOR_PALETTE_46 _MK_ADDR_CONST(0x52e) +#define DC_WINC_A_COLOR_PALETTE_46_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_46_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_46_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_46_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_46_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_46_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_46_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_46_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_46_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_46_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_46_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_46_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_46_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_46_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_46_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_46_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_46_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_46_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_46_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_46_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_46_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_46_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_46_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_46_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_46_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_46_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_46_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_46_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_46_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_46_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_46_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_46_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_46_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_46_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_46_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_47 +#define DC_WINC_A_COLOR_PALETTE_47 _MK_ADDR_CONST(0x52f) +#define DC_WINC_A_COLOR_PALETTE_47_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_47_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_47_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_47_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_47_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_47_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_47_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_47_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_47_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_47_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_47_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_47_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_47_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_47_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_47_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_47_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_47_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_47_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_47_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_47_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_47_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_47_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_47_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_47_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_47_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_47_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_47_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_47_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_47_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_47_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_47_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_47_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_47_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_47_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_47_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_48 +#define DC_WINC_A_COLOR_PALETTE_48 _MK_ADDR_CONST(0x530) +#define DC_WINC_A_COLOR_PALETTE_48_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_48_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_48_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_48_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_48_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_48_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_48_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_48_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_48_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_48_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_48_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_48_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_48_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_48_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_48_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_48_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_48_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_48_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_48_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_48_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_48_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_48_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_48_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_48_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_48_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_48_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_48_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_48_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_48_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_48_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_48_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_48_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_48_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_48_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_48_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_49 +#define DC_WINC_A_COLOR_PALETTE_49 _MK_ADDR_CONST(0x531) +#define DC_WINC_A_COLOR_PALETTE_49_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_49_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_49_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_49_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_49_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_49_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_49_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_49_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_49_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_49_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_49_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_49_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_49_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_49_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_49_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_49_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_49_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_49_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_49_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_49_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_49_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_49_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_49_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_49_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_49_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_49_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_49_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_49_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_49_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_49_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_49_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_49_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_49_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_49_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_49_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_50 +#define DC_WINC_A_COLOR_PALETTE_50 _MK_ADDR_CONST(0x532) +#define DC_WINC_A_COLOR_PALETTE_50_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_50_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_50_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_50_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_50_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_50_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_50_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_50_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_50_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_50_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_50_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_50_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_50_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_50_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_50_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_50_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_50_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_50_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_50_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_50_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_50_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_50_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_50_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_50_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_50_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_50_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_50_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_50_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_50_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_50_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_50_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_50_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_50_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_50_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_50_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_51 +#define DC_WINC_A_COLOR_PALETTE_51 _MK_ADDR_CONST(0x533) +#define DC_WINC_A_COLOR_PALETTE_51_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_51_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_51_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_51_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_51_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_51_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_51_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_51_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_51_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_51_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_51_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_51_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_51_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_51_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_51_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_51_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_51_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_51_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_51_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_51_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_51_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_51_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_51_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_51_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_51_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_51_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_51_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_51_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_51_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_51_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_51_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_51_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_51_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_51_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_51_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_52 +#define DC_WINC_A_COLOR_PALETTE_52 _MK_ADDR_CONST(0x534) +#define DC_WINC_A_COLOR_PALETTE_52_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_52_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_52_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_52_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_52_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_52_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_52_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_52_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_52_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_52_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_52_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_52_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_52_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_52_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_52_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_52_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_52_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_52_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_52_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_52_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_52_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_52_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_52_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_52_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_52_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_52_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_52_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_52_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_52_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_52_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_52_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_52_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_52_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_52_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_52_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_53 +#define DC_WINC_A_COLOR_PALETTE_53 _MK_ADDR_CONST(0x535) +#define DC_WINC_A_COLOR_PALETTE_53_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_53_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_53_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_53_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_53_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_53_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_53_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_53_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_53_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_53_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_53_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_53_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_53_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_53_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_53_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_53_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_53_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_53_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_53_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_53_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_53_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_53_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_53_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_53_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_53_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_53_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_53_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_53_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_53_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_53_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_53_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_53_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_53_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_53_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_53_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_54 +#define DC_WINC_A_COLOR_PALETTE_54 _MK_ADDR_CONST(0x536) +#define DC_WINC_A_COLOR_PALETTE_54_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_54_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_54_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_54_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_54_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_54_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_54_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_54_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_54_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_54_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_54_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_54_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_54_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_54_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_54_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_54_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_54_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_54_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_54_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_54_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_54_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_54_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_54_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_54_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_54_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_54_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_54_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_54_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_54_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_54_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_54_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_54_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_54_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_54_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_54_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_55 +#define DC_WINC_A_COLOR_PALETTE_55 _MK_ADDR_CONST(0x537) +#define DC_WINC_A_COLOR_PALETTE_55_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_55_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_55_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_55_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_55_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_55_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_55_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_55_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_55_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_55_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_55_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_55_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_55_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_55_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_55_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_55_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_55_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_55_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_55_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_55_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_55_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_55_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_55_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_55_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_55_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_55_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_55_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_55_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_55_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_55_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_55_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_55_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_55_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_55_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_55_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_56 +#define DC_WINC_A_COLOR_PALETTE_56 _MK_ADDR_CONST(0x538) +#define DC_WINC_A_COLOR_PALETTE_56_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_56_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_56_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_56_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_56_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_56_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_56_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_56_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_56_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_56_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_56_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_56_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_56_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_56_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_56_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_56_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_56_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_56_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_56_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_56_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_56_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_56_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_56_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_56_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_56_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_56_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_56_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_56_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_56_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_56_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_56_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_56_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_56_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_56_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_56_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_57 +#define DC_WINC_A_COLOR_PALETTE_57 _MK_ADDR_CONST(0x539) +#define DC_WINC_A_COLOR_PALETTE_57_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_57_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_57_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_57_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_57_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_57_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_57_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_57_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_57_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_57_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_57_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_57_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_57_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_57_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_57_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_57_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_57_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_57_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_57_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_57_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_57_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_57_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_57_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_57_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_57_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_57_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_57_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_57_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_57_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_57_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_57_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_57_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_57_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_57_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_57_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_58 +#define DC_WINC_A_COLOR_PALETTE_58 _MK_ADDR_CONST(0x53a) +#define DC_WINC_A_COLOR_PALETTE_58_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_58_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_58_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_58_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_58_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_58_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_58_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_58_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_58_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_58_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_58_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_58_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_58_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_58_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_58_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_58_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_58_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_58_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_58_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_58_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_58_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_58_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_58_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_58_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_58_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_58_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_58_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_58_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_58_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_58_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_58_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_58_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_58_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_58_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_58_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_59 +#define DC_WINC_A_COLOR_PALETTE_59 _MK_ADDR_CONST(0x53b) +#define DC_WINC_A_COLOR_PALETTE_59_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_59_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_59_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_59_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_59_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_59_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_59_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_59_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_59_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_59_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_59_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_59_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_59_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_59_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_59_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_59_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_59_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_59_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_59_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_59_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_59_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_59_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_59_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_59_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_59_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_59_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_59_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_59_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_59_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_59_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_59_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_59_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_59_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_59_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_59_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_60 +#define DC_WINC_A_COLOR_PALETTE_60 _MK_ADDR_CONST(0x53c) +#define DC_WINC_A_COLOR_PALETTE_60_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_60_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_60_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_60_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_60_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_60_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_60_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_60_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_60_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_60_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_60_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_60_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_60_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_60_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_60_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_60_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_60_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_60_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_60_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_60_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_60_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_60_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_60_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_60_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_60_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_60_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_60_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_60_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_60_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_60_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_60_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_60_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_60_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_60_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_60_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_61 +#define DC_WINC_A_COLOR_PALETTE_61 _MK_ADDR_CONST(0x53d) +#define DC_WINC_A_COLOR_PALETTE_61_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_61_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_61_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_61_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_61_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_61_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_61_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_61_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_61_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_61_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_61_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_61_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_61_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_61_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_61_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_61_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_61_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_61_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_61_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_61_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_61_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_61_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_61_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_61_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_61_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_61_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_61_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_61_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_61_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_61_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_61_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_61_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_61_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_61_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_61_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_62 +#define DC_WINC_A_COLOR_PALETTE_62 _MK_ADDR_CONST(0x53e) +#define DC_WINC_A_COLOR_PALETTE_62_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_62_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_62_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_62_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_62_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_62_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_62_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_62_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_62_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_62_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_62_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_62_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_62_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_62_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_62_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_62_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_62_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_62_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_62_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_62_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_62_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_62_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_62_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_62_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_62_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_62_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_62_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_62_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_62_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_62_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_62_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_62_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_62_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_62_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_62_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_63 +#define DC_WINC_A_COLOR_PALETTE_63 _MK_ADDR_CONST(0x53f) +#define DC_WINC_A_COLOR_PALETTE_63_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_63_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_63_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_63_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_63_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_63_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_63_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_63_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_63_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_63_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_63_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_63_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_63_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_63_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_63_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_63_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_63_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_63_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_63_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_63_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_63_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_63_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_63_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_63_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_63_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_63_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_63_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_63_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_63_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_63_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_63_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_63_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_63_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_63_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_63_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_64 +#define DC_WINC_A_COLOR_PALETTE_64 _MK_ADDR_CONST(0x540) +#define DC_WINC_A_COLOR_PALETTE_64_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_64_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_64_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_64_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_64_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_64_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_64_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_64_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_64_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_64_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_64_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_64_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_64_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_64_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_64_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_64_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_64_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_64_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_64_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_64_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_64_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_64_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_64_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_64_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_64_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_64_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_64_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_64_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_64_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_64_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_64_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_64_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_64_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_64_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_64_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_65 +#define DC_WINC_A_COLOR_PALETTE_65 _MK_ADDR_CONST(0x541) +#define DC_WINC_A_COLOR_PALETTE_65_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_65_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_65_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_65_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_65_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_65_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_65_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_65_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_65_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_65_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_65_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_65_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_65_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_65_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_65_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_65_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_65_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_65_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_65_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_65_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_65_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_65_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_65_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_65_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_65_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_65_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_65_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_65_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_65_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_65_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_65_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_65_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_65_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_65_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_65_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_66 +#define DC_WINC_A_COLOR_PALETTE_66 _MK_ADDR_CONST(0x542) +#define DC_WINC_A_COLOR_PALETTE_66_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_66_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_66_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_66_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_66_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_66_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_66_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_66_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_66_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_66_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_66_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_66_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_66_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_66_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_66_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_66_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_66_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_66_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_66_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_66_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_66_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_66_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_66_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_66_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_66_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_66_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_66_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_66_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_66_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_66_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_66_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_66_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_66_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_66_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_66_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_67 +#define DC_WINC_A_COLOR_PALETTE_67 _MK_ADDR_CONST(0x543) +#define DC_WINC_A_COLOR_PALETTE_67_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_67_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_67_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_67_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_67_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_67_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_67_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_67_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_67_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_67_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_67_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_67_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_67_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_67_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_67_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_67_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_67_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_67_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_67_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_67_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_67_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_67_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_67_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_67_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_67_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_67_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_67_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_67_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_67_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_67_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_67_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_67_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_67_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_67_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_67_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_68 +#define DC_WINC_A_COLOR_PALETTE_68 _MK_ADDR_CONST(0x544) +#define DC_WINC_A_COLOR_PALETTE_68_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_68_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_68_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_68_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_68_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_68_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_68_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_68_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_68_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_68_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_68_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_68_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_68_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_68_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_68_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_68_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_68_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_68_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_68_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_68_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_68_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_68_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_68_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_68_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_68_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_68_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_68_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_68_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_68_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_68_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_68_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_68_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_68_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_68_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_68_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_69 +#define DC_WINC_A_COLOR_PALETTE_69 _MK_ADDR_CONST(0x545) +#define DC_WINC_A_COLOR_PALETTE_69_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_69_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_69_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_69_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_69_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_69_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_69_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_69_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_69_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_69_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_69_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_69_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_69_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_69_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_69_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_69_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_69_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_69_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_69_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_69_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_69_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_69_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_69_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_69_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_69_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_69_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_69_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_69_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_69_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_69_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_69_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_69_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_69_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_69_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_69_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_70 +#define DC_WINC_A_COLOR_PALETTE_70 _MK_ADDR_CONST(0x546) +#define DC_WINC_A_COLOR_PALETTE_70_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_70_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_70_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_70_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_70_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_70_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_70_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_70_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_70_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_70_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_70_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_70_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_70_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_70_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_70_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_70_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_70_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_70_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_70_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_70_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_70_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_70_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_70_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_70_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_70_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_70_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_70_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_70_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_70_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_70_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_70_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_70_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_70_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_70_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_70_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_71 +#define DC_WINC_A_COLOR_PALETTE_71 _MK_ADDR_CONST(0x547) +#define DC_WINC_A_COLOR_PALETTE_71_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_71_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_71_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_71_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_71_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_71_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_71_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_71_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_71_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_71_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_71_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_71_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_71_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_71_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_71_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_71_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_71_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_71_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_71_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_71_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_71_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_71_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_71_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_71_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_71_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_71_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_71_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_71_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_71_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_71_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_71_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_71_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_71_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_71_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_71_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_72 +#define DC_WINC_A_COLOR_PALETTE_72 _MK_ADDR_CONST(0x548) +#define DC_WINC_A_COLOR_PALETTE_72_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_72_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_72_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_72_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_72_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_72_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_72_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_72_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_72_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_72_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_72_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_72_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_72_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_72_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_72_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_72_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_72_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_72_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_72_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_72_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_72_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_72_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_72_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_72_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_72_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_72_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_72_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_72_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_72_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_72_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_72_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_72_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_72_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_72_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_72_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_73 +#define DC_WINC_A_COLOR_PALETTE_73 _MK_ADDR_CONST(0x549) +#define DC_WINC_A_COLOR_PALETTE_73_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_73_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_73_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_73_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_73_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_73_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_73_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_73_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_73_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_73_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_73_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_73_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_73_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_73_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_73_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_73_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_73_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_73_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_73_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_73_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_73_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_73_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_73_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_73_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_73_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_73_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_73_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_73_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_73_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_73_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_73_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_73_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_73_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_73_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_73_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_74 +#define DC_WINC_A_COLOR_PALETTE_74 _MK_ADDR_CONST(0x54a) +#define DC_WINC_A_COLOR_PALETTE_74_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_74_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_74_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_74_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_74_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_74_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_74_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_74_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_74_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_74_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_74_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_74_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_74_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_74_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_74_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_74_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_74_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_74_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_74_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_74_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_74_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_74_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_74_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_74_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_74_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_74_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_74_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_74_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_74_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_74_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_74_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_74_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_74_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_74_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_74_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_75 +#define DC_WINC_A_COLOR_PALETTE_75 _MK_ADDR_CONST(0x54b) +#define DC_WINC_A_COLOR_PALETTE_75_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_75_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_75_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_75_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_75_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_75_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_75_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_75_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_75_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_75_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_75_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_75_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_75_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_75_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_75_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_75_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_75_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_75_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_75_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_75_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_75_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_75_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_75_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_75_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_75_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_75_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_75_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_75_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_75_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_75_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_75_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_75_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_75_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_75_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_75_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_76 +#define DC_WINC_A_COLOR_PALETTE_76 _MK_ADDR_CONST(0x54c) +#define DC_WINC_A_COLOR_PALETTE_76_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_76_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_76_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_76_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_76_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_76_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_76_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_76_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_76_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_76_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_76_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_76_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_76_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_76_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_76_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_76_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_76_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_76_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_76_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_76_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_76_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_76_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_76_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_76_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_76_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_76_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_76_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_76_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_76_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_76_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_76_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_76_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_76_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_76_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_76_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_77 +#define DC_WINC_A_COLOR_PALETTE_77 _MK_ADDR_CONST(0x54d) +#define DC_WINC_A_COLOR_PALETTE_77_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_77_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_77_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_77_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_77_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_77_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_77_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_77_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_77_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_77_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_77_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_77_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_77_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_77_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_77_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_77_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_77_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_77_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_77_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_77_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_77_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_77_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_77_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_77_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_77_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_77_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_77_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_77_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_77_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_77_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_77_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_77_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_77_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_77_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_77_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_78 +#define DC_WINC_A_COLOR_PALETTE_78 _MK_ADDR_CONST(0x54e) +#define DC_WINC_A_COLOR_PALETTE_78_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_78_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_78_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_78_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_78_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_78_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_78_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_78_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_78_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_78_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_78_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_78_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_78_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_78_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_78_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_78_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_78_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_78_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_78_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_78_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_78_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_78_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_78_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_78_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_78_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_78_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_78_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_78_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_78_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_78_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_78_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_78_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_78_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_78_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_78_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_79 +#define DC_WINC_A_COLOR_PALETTE_79 _MK_ADDR_CONST(0x54f) +#define DC_WINC_A_COLOR_PALETTE_79_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_79_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_79_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_79_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_79_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_79_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_79_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_79_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_79_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_79_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_79_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_79_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_79_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_79_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_79_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_79_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_79_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_79_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_79_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_79_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_79_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_79_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_79_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_79_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_79_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_79_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_79_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_79_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_79_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_79_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_79_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_79_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_79_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_79_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_79_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_80 +#define DC_WINC_A_COLOR_PALETTE_80 _MK_ADDR_CONST(0x550) +#define DC_WINC_A_COLOR_PALETTE_80_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_80_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_80_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_80_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_80_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_80_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_80_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_80_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_80_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_80_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_80_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_80_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_80_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_80_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_80_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_80_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_80_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_80_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_80_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_80_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_80_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_80_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_80_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_80_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_80_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_80_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_80_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_80_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_80_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_80_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_80_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_80_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_80_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_80_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_80_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_81 +#define DC_WINC_A_COLOR_PALETTE_81 _MK_ADDR_CONST(0x551) +#define DC_WINC_A_COLOR_PALETTE_81_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_81_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_81_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_81_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_81_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_81_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_81_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_81_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_81_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_81_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_81_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_81_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_81_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_81_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_81_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_81_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_81_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_81_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_81_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_81_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_81_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_81_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_81_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_81_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_81_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_81_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_81_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_81_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_81_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_81_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_81_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_81_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_81_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_81_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_81_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_82 +#define DC_WINC_A_COLOR_PALETTE_82 _MK_ADDR_CONST(0x552) +#define DC_WINC_A_COLOR_PALETTE_82_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_82_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_82_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_82_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_82_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_82_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_82_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_82_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_82_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_82_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_82_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_82_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_82_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_82_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_82_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_82_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_82_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_82_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_82_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_82_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_82_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_82_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_82_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_82_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_82_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_82_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_82_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_82_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_82_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_82_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_82_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_82_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_82_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_82_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_82_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_83 +#define DC_WINC_A_COLOR_PALETTE_83 _MK_ADDR_CONST(0x553) +#define DC_WINC_A_COLOR_PALETTE_83_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_83_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_83_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_83_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_83_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_83_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_83_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_83_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_83_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_83_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_83_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_83_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_83_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_83_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_83_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_83_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_83_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_83_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_83_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_83_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_83_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_83_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_83_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_83_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_83_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_83_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_83_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_83_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_83_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_83_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_83_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_83_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_83_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_83_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_83_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_84 +#define DC_WINC_A_COLOR_PALETTE_84 _MK_ADDR_CONST(0x554) +#define DC_WINC_A_COLOR_PALETTE_84_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_84_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_84_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_84_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_84_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_84_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_84_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_84_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_84_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_84_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_84_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_84_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_84_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_84_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_84_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_84_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_84_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_84_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_84_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_84_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_84_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_84_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_84_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_84_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_84_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_84_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_84_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_84_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_84_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_84_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_84_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_84_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_84_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_84_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_84_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_85 +#define DC_WINC_A_COLOR_PALETTE_85 _MK_ADDR_CONST(0x555) +#define DC_WINC_A_COLOR_PALETTE_85_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_85_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_85_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_85_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_85_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_85_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_85_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_85_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_85_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_85_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_85_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_85_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_85_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_85_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_85_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_85_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_85_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_85_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_85_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_85_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_85_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_85_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_85_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_85_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_85_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_85_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_85_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_85_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_85_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_85_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_85_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_85_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_85_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_85_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_85_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_86 +#define DC_WINC_A_COLOR_PALETTE_86 _MK_ADDR_CONST(0x556) +#define DC_WINC_A_COLOR_PALETTE_86_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_86_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_86_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_86_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_86_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_86_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_86_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_86_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_86_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_86_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_86_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_86_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_86_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_86_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_86_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_86_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_86_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_86_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_86_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_86_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_86_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_86_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_86_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_86_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_86_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_86_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_86_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_86_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_86_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_86_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_86_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_86_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_86_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_86_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_86_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_87 +#define DC_WINC_A_COLOR_PALETTE_87 _MK_ADDR_CONST(0x557) +#define DC_WINC_A_COLOR_PALETTE_87_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_87_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_87_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_87_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_87_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_87_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_87_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_87_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_87_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_87_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_87_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_87_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_87_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_87_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_87_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_87_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_87_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_87_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_87_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_87_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_87_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_87_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_87_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_87_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_87_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_87_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_87_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_87_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_87_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_87_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_87_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_87_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_87_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_87_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_87_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_88 +#define DC_WINC_A_COLOR_PALETTE_88 _MK_ADDR_CONST(0x558) +#define DC_WINC_A_COLOR_PALETTE_88_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_88_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_88_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_88_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_88_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_88_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_88_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_88_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_88_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_88_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_88_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_88_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_88_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_88_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_88_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_88_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_88_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_88_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_88_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_88_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_88_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_88_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_88_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_88_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_88_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_88_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_88_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_88_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_88_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_88_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_88_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_88_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_88_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_88_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_88_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_89 +#define DC_WINC_A_COLOR_PALETTE_89 _MK_ADDR_CONST(0x559) +#define DC_WINC_A_COLOR_PALETTE_89_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_89_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_89_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_89_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_89_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_89_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_89_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_89_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_89_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_89_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_89_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_89_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_89_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_89_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_89_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_89_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_89_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_89_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_89_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_89_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_89_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_89_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_89_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_89_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_89_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_89_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_89_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_89_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_89_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_89_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_89_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_89_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_89_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_89_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_89_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_90 +#define DC_WINC_A_COLOR_PALETTE_90 _MK_ADDR_CONST(0x55a) +#define DC_WINC_A_COLOR_PALETTE_90_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_90_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_90_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_90_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_90_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_90_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_90_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_90_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_90_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_90_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_90_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_90_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_90_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_90_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_90_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_90_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_90_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_90_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_90_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_90_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_90_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_90_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_90_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_90_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_90_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_90_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_90_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_90_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_90_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_90_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_90_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_90_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_90_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_90_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_90_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_91 +#define DC_WINC_A_COLOR_PALETTE_91 _MK_ADDR_CONST(0x55b) +#define DC_WINC_A_COLOR_PALETTE_91_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_91_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_91_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_91_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_91_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_91_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_91_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_91_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_91_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_91_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_91_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_91_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_91_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_91_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_91_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_91_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_91_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_91_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_91_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_91_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_91_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_91_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_91_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_91_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_91_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_91_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_91_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_91_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_91_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_91_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_91_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_91_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_91_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_91_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_91_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_92 +#define DC_WINC_A_COLOR_PALETTE_92 _MK_ADDR_CONST(0x55c) +#define DC_WINC_A_COLOR_PALETTE_92_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_92_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_92_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_92_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_92_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_92_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_92_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_92_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_92_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_92_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_92_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_92_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_92_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_92_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_92_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_92_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_92_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_92_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_92_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_92_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_92_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_92_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_92_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_92_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_92_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_92_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_92_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_92_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_92_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_92_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_92_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_92_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_92_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_92_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_92_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_93 +#define DC_WINC_A_COLOR_PALETTE_93 _MK_ADDR_CONST(0x55d) +#define DC_WINC_A_COLOR_PALETTE_93_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_93_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_93_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_93_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_93_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_93_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_93_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_93_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_93_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_93_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_93_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_93_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_93_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_93_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_93_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_93_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_93_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_93_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_93_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_93_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_93_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_93_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_93_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_93_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_93_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_93_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_93_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_93_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_93_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_93_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_93_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_93_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_93_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_93_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_93_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_94 +#define DC_WINC_A_COLOR_PALETTE_94 _MK_ADDR_CONST(0x55e) +#define DC_WINC_A_COLOR_PALETTE_94_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_94_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_94_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_94_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_94_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_94_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_94_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_94_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_94_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_94_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_94_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_94_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_94_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_94_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_94_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_94_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_94_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_94_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_94_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_94_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_94_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_94_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_94_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_94_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_94_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_94_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_94_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_94_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_94_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_94_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_94_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_94_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_94_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_94_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_94_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_95 +#define DC_WINC_A_COLOR_PALETTE_95 _MK_ADDR_CONST(0x55f) +#define DC_WINC_A_COLOR_PALETTE_95_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_95_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_95_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_95_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_95_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_95_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_95_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_95_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_95_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_95_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_95_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_95_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_95_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_95_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_95_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_95_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_95_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_95_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_95_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_95_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_95_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_95_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_95_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_95_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_95_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_95_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_95_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_95_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_95_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_95_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_95_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_95_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_95_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_95_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_95_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_96 +#define DC_WINC_A_COLOR_PALETTE_96 _MK_ADDR_CONST(0x560) +#define DC_WINC_A_COLOR_PALETTE_96_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_96_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_96_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_96_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_96_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_96_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_96_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_96_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_96_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_96_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_96_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_96_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_96_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_96_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_96_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_96_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_96_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_96_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_96_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_96_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_96_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_96_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_96_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_96_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_96_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_96_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_96_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_96_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_96_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_96_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_96_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_96_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_96_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_96_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_96_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_97 +#define DC_WINC_A_COLOR_PALETTE_97 _MK_ADDR_CONST(0x561) +#define DC_WINC_A_COLOR_PALETTE_97_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_97_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_97_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_97_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_97_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_97_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_97_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_97_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_97_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_97_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_97_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_97_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_97_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_97_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_97_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_97_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_97_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_97_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_97_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_97_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_97_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_97_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_97_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_97_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_97_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_97_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_97_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_97_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_97_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_97_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_97_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_97_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_97_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_97_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_97_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_98 +#define DC_WINC_A_COLOR_PALETTE_98 _MK_ADDR_CONST(0x562) +#define DC_WINC_A_COLOR_PALETTE_98_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_98_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_98_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_98_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_98_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_98_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_98_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_98_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_98_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_98_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_98_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_98_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_98_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_98_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_98_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_98_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_98_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_98_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_98_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_98_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_98_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_98_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_98_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_98_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_98_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_98_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_98_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_98_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_98_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_98_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_98_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_98_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_98_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_98_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_98_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_99 +#define DC_WINC_A_COLOR_PALETTE_99 _MK_ADDR_CONST(0x563) +#define DC_WINC_A_COLOR_PALETTE_99_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_99_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_99_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_99_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_99_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_99_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_99_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_99_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_99_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_99_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_99_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_99_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_99_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_99_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_99_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_99_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_99_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_99_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_99_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_99_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_99_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_99_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_99_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_99_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_99_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_99_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_99_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_99_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_99_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_99_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_99_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_99_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_99_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_99_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_99_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_100 +#define DC_WINC_A_COLOR_PALETTE_100 _MK_ADDR_CONST(0x564) +#define DC_WINC_A_COLOR_PALETTE_100_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_100_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_100_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_100_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_100_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_100_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_100_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_100_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_100_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_100_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_100_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_100_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_100_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_100_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_100_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_100_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_100_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_100_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_100_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_100_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_100_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_100_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_100_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_100_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_100_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_100_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_100_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_100_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_100_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_100_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_100_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_100_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_100_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_100_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_100_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_101 +#define DC_WINC_A_COLOR_PALETTE_101 _MK_ADDR_CONST(0x565) +#define DC_WINC_A_COLOR_PALETTE_101_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_101_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_101_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_101_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_101_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_101_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_101_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_101_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_101_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_101_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_101_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_101_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_101_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_101_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_101_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_101_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_101_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_101_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_101_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_101_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_101_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_101_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_101_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_101_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_101_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_101_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_101_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_101_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_101_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_101_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_101_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_101_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_101_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_101_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_101_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_102 +#define DC_WINC_A_COLOR_PALETTE_102 _MK_ADDR_CONST(0x566) +#define DC_WINC_A_COLOR_PALETTE_102_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_102_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_102_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_102_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_102_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_102_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_102_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_102_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_102_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_102_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_102_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_102_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_102_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_102_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_102_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_102_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_102_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_102_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_102_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_102_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_102_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_102_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_102_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_102_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_102_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_102_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_102_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_102_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_102_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_102_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_102_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_102_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_102_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_102_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_102_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_103 +#define DC_WINC_A_COLOR_PALETTE_103 _MK_ADDR_CONST(0x567) +#define DC_WINC_A_COLOR_PALETTE_103_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_103_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_103_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_103_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_103_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_103_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_103_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_103_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_103_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_103_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_103_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_103_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_103_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_103_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_103_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_103_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_103_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_103_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_103_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_103_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_103_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_103_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_103_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_103_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_103_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_103_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_103_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_103_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_103_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_103_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_103_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_103_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_103_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_103_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_103_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_104 +#define DC_WINC_A_COLOR_PALETTE_104 _MK_ADDR_CONST(0x568) +#define DC_WINC_A_COLOR_PALETTE_104_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_104_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_104_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_104_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_104_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_104_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_104_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_104_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_104_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_104_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_104_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_104_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_104_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_104_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_104_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_104_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_104_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_104_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_104_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_104_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_104_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_104_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_104_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_104_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_104_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_104_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_104_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_104_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_104_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_104_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_104_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_104_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_104_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_104_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_104_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_105 +#define DC_WINC_A_COLOR_PALETTE_105 _MK_ADDR_CONST(0x569) +#define DC_WINC_A_COLOR_PALETTE_105_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_105_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_105_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_105_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_105_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_105_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_105_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_105_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_105_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_105_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_105_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_105_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_105_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_105_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_105_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_105_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_105_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_105_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_105_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_105_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_105_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_105_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_105_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_105_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_105_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_105_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_105_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_105_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_105_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_105_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_105_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_105_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_105_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_105_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_105_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_106 +#define DC_WINC_A_COLOR_PALETTE_106 _MK_ADDR_CONST(0x56a) +#define DC_WINC_A_COLOR_PALETTE_106_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_106_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_106_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_106_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_106_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_106_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_106_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_106_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_106_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_106_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_106_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_106_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_106_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_106_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_106_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_106_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_106_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_106_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_106_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_106_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_106_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_106_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_106_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_106_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_106_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_106_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_106_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_106_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_106_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_106_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_106_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_106_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_106_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_106_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_106_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_107 +#define DC_WINC_A_COLOR_PALETTE_107 _MK_ADDR_CONST(0x56b) +#define DC_WINC_A_COLOR_PALETTE_107_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_107_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_107_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_107_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_107_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_107_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_107_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_107_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_107_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_107_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_107_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_107_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_107_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_107_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_107_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_107_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_107_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_107_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_107_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_107_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_107_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_107_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_107_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_107_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_107_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_107_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_107_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_107_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_107_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_107_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_107_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_107_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_107_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_107_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_107_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_108 +#define DC_WINC_A_COLOR_PALETTE_108 _MK_ADDR_CONST(0x56c) +#define DC_WINC_A_COLOR_PALETTE_108_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_108_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_108_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_108_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_108_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_108_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_108_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_108_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_108_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_108_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_108_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_108_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_108_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_108_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_108_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_108_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_108_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_108_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_108_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_108_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_108_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_108_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_108_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_108_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_108_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_108_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_108_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_108_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_108_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_108_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_108_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_108_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_108_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_108_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_108_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_109 +#define DC_WINC_A_COLOR_PALETTE_109 _MK_ADDR_CONST(0x56d) +#define DC_WINC_A_COLOR_PALETTE_109_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_109_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_109_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_109_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_109_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_109_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_109_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_109_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_109_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_109_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_109_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_109_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_109_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_109_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_109_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_109_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_109_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_109_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_109_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_109_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_109_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_109_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_109_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_109_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_109_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_109_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_109_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_109_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_109_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_109_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_109_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_109_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_109_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_109_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_109_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_110 +#define DC_WINC_A_COLOR_PALETTE_110 _MK_ADDR_CONST(0x56e) +#define DC_WINC_A_COLOR_PALETTE_110_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_110_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_110_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_110_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_110_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_110_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_110_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_110_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_110_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_110_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_110_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_110_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_110_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_110_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_110_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_110_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_110_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_110_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_110_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_110_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_110_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_110_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_110_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_110_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_110_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_110_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_110_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_110_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_110_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_110_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_110_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_110_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_110_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_110_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_110_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_111 +#define DC_WINC_A_COLOR_PALETTE_111 _MK_ADDR_CONST(0x56f) +#define DC_WINC_A_COLOR_PALETTE_111_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_111_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_111_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_111_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_111_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_111_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_111_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_111_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_111_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_111_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_111_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_111_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_111_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_111_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_111_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_111_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_111_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_111_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_111_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_111_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_111_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_111_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_111_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_111_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_111_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_111_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_111_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_111_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_111_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_111_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_111_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_111_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_111_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_111_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_111_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_112 +#define DC_WINC_A_COLOR_PALETTE_112 _MK_ADDR_CONST(0x570) +#define DC_WINC_A_COLOR_PALETTE_112_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_112_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_112_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_112_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_112_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_112_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_112_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_112_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_112_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_112_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_112_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_112_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_112_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_112_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_112_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_112_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_112_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_112_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_112_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_112_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_112_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_112_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_112_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_112_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_112_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_112_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_112_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_112_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_112_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_112_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_112_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_112_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_112_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_112_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_112_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_113 +#define DC_WINC_A_COLOR_PALETTE_113 _MK_ADDR_CONST(0x571) +#define DC_WINC_A_COLOR_PALETTE_113_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_113_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_113_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_113_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_113_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_113_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_113_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_113_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_113_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_113_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_113_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_113_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_113_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_113_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_113_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_113_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_113_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_113_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_113_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_113_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_113_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_113_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_113_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_113_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_113_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_113_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_113_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_113_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_113_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_113_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_113_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_113_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_113_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_113_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_113_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_114 +#define DC_WINC_A_COLOR_PALETTE_114 _MK_ADDR_CONST(0x572) +#define DC_WINC_A_COLOR_PALETTE_114_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_114_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_114_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_114_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_114_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_114_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_114_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_114_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_114_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_114_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_114_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_114_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_114_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_114_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_114_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_114_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_114_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_114_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_114_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_114_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_114_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_114_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_114_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_114_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_114_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_114_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_114_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_114_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_114_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_114_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_114_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_114_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_114_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_114_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_114_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_115 +#define DC_WINC_A_COLOR_PALETTE_115 _MK_ADDR_CONST(0x573) +#define DC_WINC_A_COLOR_PALETTE_115_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_115_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_115_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_115_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_115_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_115_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_115_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_115_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_115_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_115_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_115_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_115_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_115_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_115_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_115_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_115_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_115_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_115_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_115_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_115_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_115_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_115_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_115_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_115_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_115_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_115_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_115_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_115_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_115_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_115_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_115_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_115_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_115_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_115_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_115_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_116 +#define DC_WINC_A_COLOR_PALETTE_116 _MK_ADDR_CONST(0x574) +#define DC_WINC_A_COLOR_PALETTE_116_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_116_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_116_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_116_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_116_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_116_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_116_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_116_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_116_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_116_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_116_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_116_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_116_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_116_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_116_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_116_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_116_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_116_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_116_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_116_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_116_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_116_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_116_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_116_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_116_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_116_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_116_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_116_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_116_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_116_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_116_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_116_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_116_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_116_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_116_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_117 +#define DC_WINC_A_COLOR_PALETTE_117 _MK_ADDR_CONST(0x575) +#define DC_WINC_A_COLOR_PALETTE_117_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_117_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_117_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_117_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_117_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_117_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_117_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_117_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_117_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_117_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_117_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_117_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_117_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_117_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_117_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_117_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_117_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_117_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_117_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_117_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_117_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_117_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_117_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_117_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_117_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_117_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_117_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_117_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_117_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_117_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_117_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_117_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_117_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_117_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_117_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_118 +#define DC_WINC_A_COLOR_PALETTE_118 _MK_ADDR_CONST(0x576) +#define DC_WINC_A_COLOR_PALETTE_118_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_118_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_118_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_118_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_118_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_118_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_118_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_118_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_118_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_118_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_118_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_118_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_118_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_118_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_118_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_118_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_118_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_118_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_118_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_118_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_118_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_118_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_118_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_118_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_118_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_118_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_118_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_118_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_118_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_118_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_118_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_118_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_118_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_118_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_118_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_119 +#define DC_WINC_A_COLOR_PALETTE_119 _MK_ADDR_CONST(0x577) +#define DC_WINC_A_COLOR_PALETTE_119_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_119_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_119_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_119_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_119_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_119_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_119_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_119_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_119_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_119_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_119_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_119_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_119_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_119_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_119_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_119_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_119_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_119_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_119_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_119_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_119_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_119_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_119_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_119_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_119_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_119_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_119_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_119_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_119_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_119_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_119_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_119_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_119_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_119_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_119_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_120 +#define DC_WINC_A_COLOR_PALETTE_120 _MK_ADDR_CONST(0x578) +#define DC_WINC_A_COLOR_PALETTE_120_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_120_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_120_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_120_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_120_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_120_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_120_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_120_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_120_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_120_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_120_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_120_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_120_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_120_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_120_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_120_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_120_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_120_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_120_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_120_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_120_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_120_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_120_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_120_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_120_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_120_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_120_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_120_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_120_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_120_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_120_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_120_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_120_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_120_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_120_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_121 +#define DC_WINC_A_COLOR_PALETTE_121 _MK_ADDR_CONST(0x579) +#define DC_WINC_A_COLOR_PALETTE_121_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_121_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_121_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_121_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_121_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_121_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_121_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_121_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_121_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_121_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_121_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_121_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_121_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_121_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_121_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_121_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_121_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_121_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_121_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_121_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_121_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_121_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_121_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_121_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_121_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_121_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_121_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_121_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_121_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_121_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_121_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_121_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_121_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_121_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_121_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_122 +#define DC_WINC_A_COLOR_PALETTE_122 _MK_ADDR_CONST(0x57a) +#define DC_WINC_A_COLOR_PALETTE_122_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_122_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_122_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_122_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_122_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_122_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_122_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_122_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_122_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_122_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_122_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_122_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_122_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_122_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_122_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_122_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_122_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_122_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_122_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_122_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_122_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_122_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_122_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_122_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_122_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_122_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_122_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_122_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_122_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_122_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_122_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_122_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_122_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_122_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_122_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_123 +#define DC_WINC_A_COLOR_PALETTE_123 _MK_ADDR_CONST(0x57b) +#define DC_WINC_A_COLOR_PALETTE_123_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_123_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_123_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_123_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_123_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_123_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_123_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_123_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_123_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_123_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_123_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_123_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_123_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_123_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_123_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_123_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_123_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_123_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_123_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_123_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_123_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_123_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_123_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_123_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_123_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_123_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_123_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_123_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_123_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_123_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_123_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_123_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_123_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_123_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_123_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_124 +#define DC_WINC_A_COLOR_PALETTE_124 _MK_ADDR_CONST(0x57c) +#define DC_WINC_A_COLOR_PALETTE_124_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_124_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_124_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_124_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_124_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_124_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_124_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_124_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_124_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_124_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_124_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_124_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_124_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_124_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_124_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_124_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_124_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_124_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_124_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_124_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_124_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_124_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_124_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_124_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_124_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_124_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_124_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_124_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_124_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_124_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_124_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_124_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_124_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_124_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_124_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_125 +#define DC_WINC_A_COLOR_PALETTE_125 _MK_ADDR_CONST(0x57d) +#define DC_WINC_A_COLOR_PALETTE_125_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_125_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_125_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_125_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_125_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_125_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_125_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_125_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_125_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_125_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_125_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_125_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_125_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_125_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_125_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_125_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_125_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_125_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_125_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_125_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_125_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_125_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_125_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_125_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_125_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_125_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_125_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_125_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_125_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_125_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_125_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_125_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_125_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_125_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_125_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_126 +#define DC_WINC_A_COLOR_PALETTE_126 _MK_ADDR_CONST(0x57e) +#define DC_WINC_A_COLOR_PALETTE_126_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_126_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_126_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_126_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_126_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_126_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_126_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_126_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_126_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_126_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_126_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_126_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_126_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_126_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_126_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_126_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_126_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_126_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_126_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_126_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_126_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_126_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_126_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_126_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_126_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_126_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_126_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_126_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_126_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_126_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_126_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_126_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_126_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_126_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_126_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_127 +#define DC_WINC_A_COLOR_PALETTE_127 _MK_ADDR_CONST(0x57f) +#define DC_WINC_A_COLOR_PALETTE_127_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_127_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_127_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_127_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_127_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_127_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_127_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_127_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_127_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_127_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_127_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_127_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_127_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_127_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_127_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_127_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_127_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_127_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_127_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_127_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_127_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_127_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_127_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_127_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_127_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_127_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_127_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_127_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_127_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_127_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_127_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_127_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_127_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_127_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_127_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_128 +#define DC_WINC_A_COLOR_PALETTE_128 _MK_ADDR_CONST(0x580) +#define DC_WINC_A_COLOR_PALETTE_128_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_128_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_128_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_128_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_128_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_128_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_128_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_128_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_128_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_128_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_128_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_128_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_128_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_128_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_128_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_128_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_128_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_128_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_128_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_128_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_128_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_128_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_128_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_128_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_128_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_128_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_128_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_128_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_128_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_128_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_128_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_128_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_128_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_128_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_128_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_129 +#define DC_WINC_A_COLOR_PALETTE_129 _MK_ADDR_CONST(0x581) +#define DC_WINC_A_COLOR_PALETTE_129_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_129_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_129_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_129_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_129_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_129_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_129_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_129_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_129_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_129_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_129_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_129_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_129_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_129_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_129_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_129_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_129_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_129_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_129_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_129_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_129_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_129_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_129_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_129_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_129_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_129_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_129_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_129_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_129_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_129_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_129_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_129_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_129_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_129_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_129_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_130 +#define DC_WINC_A_COLOR_PALETTE_130 _MK_ADDR_CONST(0x582) +#define DC_WINC_A_COLOR_PALETTE_130_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_130_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_130_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_130_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_130_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_130_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_130_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_130_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_130_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_130_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_130_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_130_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_130_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_130_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_130_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_130_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_130_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_130_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_130_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_130_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_130_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_130_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_130_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_130_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_130_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_130_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_130_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_130_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_130_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_130_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_130_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_130_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_130_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_130_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_130_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_131 +#define DC_WINC_A_COLOR_PALETTE_131 _MK_ADDR_CONST(0x583) +#define DC_WINC_A_COLOR_PALETTE_131_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_131_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_131_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_131_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_131_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_131_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_131_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_131_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_131_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_131_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_131_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_131_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_131_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_131_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_131_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_131_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_131_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_131_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_131_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_131_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_131_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_131_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_131_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_131_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_131_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_131_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_131_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_131_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_131_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_131_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_131_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_131_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_131_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_131_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_131_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_132 +#define DC_WINC_A_COLOR_PALETTE_132 _MK_ADDR_CONST(0x584) +#define DC_WINC_A_COLOR_PALETTE_132_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_132_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_132_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_132_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_132_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_132_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_132_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_132_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_132_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_132_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_132_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_132_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_132_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_132_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_132_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_132_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_132_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_132_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_132_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_132_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_132_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_132_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_132_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_132_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_132_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_132_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_132_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_132_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_132_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_132_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_132_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_132_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_132_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_132_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_132_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_133 +#define DC_WINC_A_COLOR_PALETTE_133 _MK_ADDR_CONST(0x585) +#define DC_WINC_A_COLOR_PALETTE_133_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_133_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_133_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_133_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_133_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_133_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_133_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_133_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_133_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_133_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_133_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_133_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_133_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_133_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_133_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_133_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_133_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_133_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_133_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_133_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_133_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_133_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_133_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_133_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_133_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_133_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_133_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_133_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_133_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_133_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_133_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_133_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_133_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_133_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_133_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_134 +#define DC_WINC_A_COLOR_PALETTE_134 _MK_ADDR_CONST(0x586) +#define DC_WINC_A_COLOR_PALETTE_134_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_134_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_134_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_134_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_134_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_134_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_134_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_134_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_134_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_134_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_134_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_134_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_134_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_134_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_134_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_134_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_134_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_134_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_134_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_134_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_134_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_134_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_134_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_134_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_134_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_134_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_134_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_134_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_134_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_134_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_134_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_134_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_134_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_134_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_134_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_135 +#define DC_WINC_A_COLOR_PALETTE_135 _MK_ADDR_CONST(0x587) +#define DC_WINC_A_COLOR_PALETTE_135_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_135_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_135_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_135_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_135_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_135_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_135_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_135_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_135_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_135_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_135_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_135_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_135_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_135_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_135_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_135_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_135_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_135_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_135_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_135_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_135_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_135_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_135_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_135_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_135_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_135_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_135_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_135_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_135_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_135_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_135_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_135_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_135_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_135_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_135_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_136 +#define DC_WINC_A_COLOR_PALETTE_136 _MK_ADDR_CONST(0x588) +#define DC_WINC_A_COLOR_PALETTE_136_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_136_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_136_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_136_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_136_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_136_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_136_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_136_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_136_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_136_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_136_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_136_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_136_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_136_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_136_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_136_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_136_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_136_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_136_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_136_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_136_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_136_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_136_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_136_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_136_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_136_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_136_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_136_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_136_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_136_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_136_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_136_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_136_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_136_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_136_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_137 +#define DC_WINC_A_COLOR_PALETTE_137 _MK_ADDR_CONST(0x589) +#define DC_WINC_A_COLOR_PALETTE_137_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_137_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_137_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_137_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_137_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_137_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_137_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_137_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_137_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_137_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_137_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_137_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_137_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_137_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_137_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_137_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_137_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_137_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_137_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_137_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_137_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_137_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_137_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_137_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_137_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_137_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_137_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_137_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_137_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_137_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_137_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_137_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_137_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_137_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_137_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_138 +#define DC_WINC_A_COLOR_PALETTE_138 _MK_ADDR_CONST(0x58a) +#define DC_WINC_A_COLOR_PALETTE_138_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_138_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_138_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_138_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_138_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_138_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_138_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_138_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_138_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_138_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_138_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_138_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_138_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_138_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_138_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_138_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_138_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_138_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_138_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_138_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_138_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_138_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_138_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_138_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_138_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_138_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_138_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_138_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_138_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_138_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_138_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_138_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_138_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_138_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_138_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_139 +#define DC_WINC_A_COLOR_PALETTE_139 _MK_ADDR_CONST(0x58b) +#define DC_WINC_A_COLOR_PALETTE_139_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_139_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_139_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_139_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_139_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_139_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_139_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_139_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_139_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_139_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_139_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_139_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_139_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_139_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_139_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_139_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_139_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_139_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_139_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_139_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_139_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_139_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_139_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_139_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_139_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_139_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_139_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_139_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_139_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_139_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_139_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_139_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_139_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_139_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_139_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_140 +#define DC_WINC_A_COLOR_PALETTE_140 _MK_ADDR_CONST(0x58c) +#define DC_WINC_A_COLOR_PALETTE_140_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_140_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_140_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_140_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_140_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_140_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_140_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_140_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_140_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_140_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_140_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_140_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_140_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_140_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_140_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_140_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_140_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_140_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_140_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_140_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_140_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_140_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_140_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_140_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_140_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_140_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_140_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_140_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_140_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_140_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_140_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_140_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_140_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_140_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_140_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_141 +#define DC_WINC_A_COLOR_PALETTE_141 _MK_ADDR_CONST(0x58d) +#define DC_WINC_A_COLOR_PALETTE_141_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_141_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_141_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_141_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_141_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_141_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_141_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_141_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_141_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_141_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_141_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_141_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_141_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_141_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_141_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_141_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_141_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_141_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_141_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_141_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_141_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_141_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_141_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_141_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_141_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_141_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_141_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_141_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_141_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_141_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_141_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_141_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_141_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_141_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_141_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_142 +#define DC_WINC_A_COLOR_PALETTE_142 _MK_ADDR_CONST(0x58e) +#define DC_WINC_A_COLOR_PALETTE_142_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_142_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_142_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_142_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_142_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_142_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_142_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_142_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_142_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_142_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_142_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_142_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_142_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_142_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_142_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_142_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_142_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_142_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_142_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_142_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_142_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_142_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_142_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_142_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_142_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_142_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_142_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_142_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_142_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_142_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_142_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_142_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_142_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_142_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_142_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_143 +#define DC_WINC_A_COLOR_PALETTE_143 _MK_ADDR_CONST(0x58f) +#define DC_WINC_A_COLOR_PALETTE_143_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_143_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_143_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_143_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_143_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_143_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_143_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_143_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_143_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_143_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_143_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_143_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_143_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_143_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_143_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_143_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_143_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_143_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_143_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_143_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_143_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_143_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_143_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_143_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_143_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_143_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_143_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_143_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_143_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_143_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_143_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_143_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_143_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_143_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_143_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_144 +#define DC_WINC_A_COLOR_PALETTE_144 _MK_ADDR_CONST(0x590) +#define DC_WINC_A_COLOR_PALETTE_144_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_144_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_144_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_144_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_144_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_144_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_144_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_144_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_144_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_144_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_144_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_144_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_144_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_144_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_144_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_144_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_144_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_144_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_144_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_144_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_144_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_144_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_144_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_144_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_144_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_144_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_144_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_144_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_144_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_144_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_144_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_144_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_144_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_144_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_144_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_145 +#define DC_WINC_A_COLOR_PALETTE_145 _MK_ADDR_CONST(0x591) +#define DC_WINC_A_COLOR_PALETTE_145_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_145_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_145_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_145_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_145_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_145_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_145_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_145_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_145_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_145_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_145_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_145_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_145_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_145_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_145_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_145_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_145_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_145_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_145_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_145_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_145_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_145_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_145_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_145_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_145_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_145_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_145_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_145_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_145_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_145_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_145_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_145_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_145_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_145_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_145_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_146 +#define DC_WINC_A_COLOR_PALETTE_146 _MK_ADDR_CONST(0x592) +#define DC_WINC_A_COLOR_PALETTE_146_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_146_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_146_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_146_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_146_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_146_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_146_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_146_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_146_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_146_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_146_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_146_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_146_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_146_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_146_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_146_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_146_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_146_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_146_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_146_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_146_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_146_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_146_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_146_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_146_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_146_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_146_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_146_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_146_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_146_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_146_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_146_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_146_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_146_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_146_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_147 +#define DC_WINC_A_COLOR_PALETTE_147 _MK_ADDR_CONST(0x593) +#define DC_WINC_A_COLOR_PALETTE_147_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_147_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_147_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_147_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_147_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_147_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_147_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_147_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_147_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_147_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_147_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_147_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_147_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_147_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_147_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_147_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_147_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_147_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_147_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_147_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_147_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_147_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_147_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_147_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_147_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_147_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_147_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_147_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_147_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_147_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_147_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_147_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_147_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_147_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_147_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_148 +#define DC_WINC_A_COLOR_PALETTE_148 _MK_ADDR_CONST(0x594) +#define DC_WINC_A_COLOR_PALETTE_148_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_148_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_148_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_148_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_148_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_148_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_148_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_148_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_148_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_148_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_148_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_148_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_148_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_148_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_148_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_148_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_148_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_148_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_148_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_148_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_148_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_148_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_148_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_148_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_148_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_148_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_148_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_148_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_148_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_148_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_148_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_148_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_148_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_148_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_148_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_149 +#define DC_WINC_A_COLOR_PALETTE_149 _MK_ADDR_CONST(0x595) +#define DC_WINC_A_COLOR_PALETTE_149_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_149_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_149_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_149_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_149_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_149_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_149_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_149_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_149_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_149_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_149_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_149_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_149_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_149_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_149_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_149_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_149_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_149_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_149_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_149_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_149_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_149_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_149_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_149_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_149_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_149_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_149_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_149_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_149_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_149_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_149_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_149_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_149_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_149_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_149_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_150 +#define DC_WINC_A_COLOR_PALETTE_150 _MK_ADDR_CONST(0x596) +#define DC_WINC_A_COLOR_PALETTE_150_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_150_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_150_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_150_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_150_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_150_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_150_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_150_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_150_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_150_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_150_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_150_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_150_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_150_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_150_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_150_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_150_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_150_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_150_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_150_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_150_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_150_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_150_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_150_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_150_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_150_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_150_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_150_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_150_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_150_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_150_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_150_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_150_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_150_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_150_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_151 +#define DC_WINC_A_COLOR_PALETTE_151 _MK_ADDR_CONST(0x597) +#define DC_WINC_A_COLOR_PALETTE_151_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_151_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_151_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_151_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_151_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_151_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_151_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_151_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_151_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_151_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_151_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_151_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_151_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_151_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_151_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_151_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_151_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_151_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_151_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_151_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_151_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_151_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_151_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_151_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_151_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_151_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_151_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_151_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_151_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_151_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_151_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_151_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_151_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_151_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_151_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_152 +#define DC_WINC_A_COLOR_PALETTE_152 _MK_ADDR_CONST(0x598) +#define DC_WINC_A_COLOR_PALETTE_152_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_152_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_152_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_152_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_152_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_152_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_152_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_152_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_152_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_152_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_152_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_152_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_152_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_152_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_152_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_152_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_152_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_152_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_152_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_152_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_152_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_152_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_152_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_152_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_152_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_152_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_152_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_152_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_152_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_152_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_152_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_152_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_152_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_152_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_152_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_153 +#define DC_WINC_A_COLOR_PALETTE_153 _MK_ADDR_CONST(0x599) +#define DC_WINC_A_COLOR_PALETTE_153_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_153_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_153_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_153_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_153_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_153_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_153_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_153_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_153_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_153_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_153_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_153_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_153_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_153_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_153_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_153_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_153_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_153_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_153_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_153_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_153_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_153_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_153_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_153_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_153_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_153_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_153_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_153_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_153_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_153_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_153_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_153_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_153_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_153_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_153_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_154 +#define DC_WINC_A_COLOR_PALETTE_154 _MK_ADDR_CONST(0x59a) +#define DC_WINC_A_COLOR_PALETTE_154_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_154_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_154_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_154_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_154_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_154_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_154_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_154_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_154_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_154_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_154_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_154_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_154_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_154_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_154_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_154_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_154_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_154_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_154_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_154_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_154_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_154_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_154_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_154_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_154_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_154_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_154_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_154_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_154_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_154_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_154_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_154_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_154_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_154_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_154_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_155 +#define DC_WINC_A_COLOR_PALETTE_155 _MK_ADDR_CONST(0x59b) +#define DC_WINC_A_COLOR_PALETTE_155_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_155_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_155_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_155_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_155_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_155_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_155_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_155_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_155_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_155_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_155_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_155_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_155_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_155_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_155_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_155_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_155_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_155_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_155_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_155_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_155_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_155_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_155_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_155_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_155_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_155_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_155_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_155_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_155_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_155_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_155_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_155_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_155_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_155_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_155_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_156 +#define DC_WINC_A_COLOR_PALETTE_156 _MK_ADDR_CONST(0x59c) +#define DC_WINC_A_COLOR_PALETTE_156_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_156_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_156_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_156_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_156_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_156_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_156_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_156_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_156_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_156_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_156_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_156_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_156_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_156_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_156_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_156_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_156_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_156_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_156_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_156_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_156_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_156_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_156_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_156_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_156_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_156_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_156_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_156_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_156_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_156_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_156_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_156_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_156_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_156_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_156_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_157 +#define DC_WINC_A_COLOR_PALETTE_157 _MK_ADDR_CONST(0x59d) +#define DC_WINC_A_COLOR_PALETTE_157_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_157_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_157_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_157_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_157_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_157_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_157_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_157_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_157_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_157_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_157_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_157_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_157_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_157_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_157_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_157_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_157_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_157_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_157_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_157_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_157_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_157_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_157_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_157_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_157_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_157_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_157_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_157_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_157_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_157_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_157_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_157_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_157_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_157_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_157_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_158 +#define DC_WINC_A_COLOR_PALETTE_158 _MK_ADDR_CONST(0x59e) +#define DC_WINC_A_COLOR_PALETTE_158_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_158_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_158_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_158_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_158_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_158_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_158_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_158_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_158_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_158_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_158_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_158_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_158_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_158_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_158_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_158_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_158_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_158_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_158_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_158_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_158_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_158_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_158_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_158_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_158_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_158_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_158_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_158_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_158_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_158_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_158_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_158_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_158_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_158_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_158_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_159 +#define DC_WINC_A_COLOR_PALETTE_159 _MK_ADDR_CONST(0x59f) +#define DC_WINC_A_COLOR_PALETTE_159_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_159_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_159_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_159_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_159_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_159_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_159_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_159_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_159_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_159_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_159_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_159_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_159_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_159_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_159_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_159_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_159_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_159_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_159_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_159_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_159_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_159_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_159_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_159_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_159_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_159_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_159_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_159_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_159_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_159_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_159_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_159_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_159_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_159_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_159_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_160 +#define DC_WINC_A_COLOR_PALETTE_160 _MK_ADDR_CONST(0x5a0) +#define DC_WINC_A_COLOR_PALETTE_160_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_160_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_160_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_160_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_160_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_160_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_160_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_160_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_160_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_160_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_160_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_160_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_160_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_160_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_160_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_160_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_160_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_160_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_160_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_160_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_160_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_160_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_160_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_160_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_160_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_160_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_160_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_160_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_160_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_160_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_160_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_160_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_160_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_160_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_160_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_161 +#define DC_WINC_A_COLOR_PALETTE_161 _MK_ADDR_CONST(0x5a1) +#define DC_WINC_A_COLOR_PALETTE_161_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_161_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_161_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_161_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_161_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_161_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_161_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_161_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_161_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_161_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_161_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_161_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_161_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_161_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_161_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_161_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_161_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_161_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_161_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_161_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_161_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_161_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_161_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_161_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_161_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_161_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_161_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_161_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_161_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_161_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_161_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_161_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_161_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_161_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_161_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_162 +#define DC_WINC_A_COLOR_PALETTE_162 _MK_ADDR_CONST(0x5a2) +#define DC_WINC_A_COLOR_PALETTE_162_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_162_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_162_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_162_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_162_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_162_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_162_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_162_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_162_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_162_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_162_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_162_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_162_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_162_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_162_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_162_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_162_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_162_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_162_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_162_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_162_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_162_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_162_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_162_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_162_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_162_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_162_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_162_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_162_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_162_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_162_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_162_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_162_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_162_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_162_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_163 +#define DC_WINC_A_COLOR_PALETTE_163 _MK_ADDR_CONST(0x5a3) +#define DC_WINC_A_COLOR_PALETTE_163_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_163_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_163_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_163_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_163_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_163_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_163_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_163_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_163_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_163_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_163_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_163_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_163_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_163_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_163_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_163_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_163_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_163_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_163_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_163_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_163_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_163_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_163_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_163_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_163_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_163_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_163_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_163_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_163_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_163_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_163_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_163_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_163_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_163_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_163_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_164 +#define DC_WINC_A_COLOR_PALETTE_164 _MK_ADDR_CONST(0x5a4) +#define DC_WINC_A_COLOR_PALETTE_164_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_164_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_164_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_164_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_164_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_164_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_164_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_164_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_164_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_164_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_164_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_164_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_164_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_164_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_164_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_164_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_164_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_164_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_164_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_164_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_164_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_164_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_164_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_164_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_164_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_164_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_164_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_164_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_164_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_164_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_164_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_164_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_164_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_164_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_164_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_165 +#define DC_WINC_A_COLOR_PALETTE_165 _MK_ADDR_CONST(0x5a5) +#define DC_WINC_A_COLOR_PALETTE_165_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_165_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_165_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_165_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_165_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_165_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_165_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_165_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_165_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_165_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_165_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_165_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_165_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_165_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_165_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_165_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_165_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_165_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_165_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_165_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_165_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_165_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_165_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_165_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_165_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_165_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_165_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_165_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_165_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_165_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_165_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_165_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_165_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_165_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_165_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_166 +#define DC_WINC_A_COLOR_PALETTE_166 _MK_ADDR_CONST(0x5a6) +#define DC_WINC_A_COLOR_PALETTE_166_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_166_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_166_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_166_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_166_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_166_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_166_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_166_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_166_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_166_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_166_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_166_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_166_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_166_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_166_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_166_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_166_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_166_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_166_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_166_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_166_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_166_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_166_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_166_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_166_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_166_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_166_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_166_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_166_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_166_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_166_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_166_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_166_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_166_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_166_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_167 +#define DC_WINC_A_COLOR_PALETTE_167 _MK_ADDR_CONST(0x5a7) +#define DC_WINC_A_COLOR_PALETTE_167_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_167_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_167_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_167_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_167_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_167_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_167_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_167_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_167_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_167_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_167_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_167_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_167_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_167_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_167_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_167_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_167_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_167_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_167_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_167_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_167_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_167_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_167_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_167_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_167_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_167_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_167_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_167_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_167_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_167_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_167_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_167_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_167_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_167_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_167_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_168 +#define DC_WINC_A_COLOR_PALETTE_168 _MK_ADDR_CONST(0x5a8) +#define DC_WINC_A_COLOR_PALETTE_168_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_168_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_168_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_168_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_168_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_168_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_168_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_168_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_168_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_168_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_168_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_168_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_168_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_168_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_168_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_168_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_168_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_168_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_168_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_168_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_168_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_168_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_168_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_168_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_168_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_168_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_168_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_168_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_168_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_168_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_168_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_168_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_168_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_168_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_168_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_169 +#define DC_WINC_A_COLOR_PALETTE_169 _MK_ADDR_CONST(0x5a9) +#define DC_WINC_A_COLOR_PALETTE_169_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_169_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_169_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_169_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_169_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_169_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_169_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_169_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_169_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_169_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_169_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_169_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_169_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_169_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_169_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_169_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_169_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_169_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_169_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_169_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_169_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_169_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_169_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_169_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_169_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_169_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_169_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_169_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_169_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_169_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_169_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_169_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_169_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_169_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_169_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_170 +#define DC_WINC_A_COLOR_PALETTE_170 _MK_ADDR_CONST(0x5aa) +#define DC_WINC_A_COLOR_PALETTE_170_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_170_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_170_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_170_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_170_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_170_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_170_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_170_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_170_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_170_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_170_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_170_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_170_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_170_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_170_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_170_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_170_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_170_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_170_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_170_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_170_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_170_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_170_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_170_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_170_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_170_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_170_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_170_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_170_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_170_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_170_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_170_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_170_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_170_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_170_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_171 +#define DC_WINC_A_COLOR_PALETTE_171 _MK_ADDR_CONST(0x5ab) +#define DC_WINC_A_COLOR_PALETTE_171_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_171_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_171_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_171_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_171_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_171_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_171_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_171_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_171_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_171_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_171_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_171_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_171_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_171_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_171_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_171_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_171_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_171_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_171_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_171_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_171_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_171_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_171_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_171_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_171_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_171_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_171_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_171_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_171_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_171_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_171_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_171_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_171_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_171_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_171_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_172 +#define DC_WINC_A_COLOR_PALETTE_172 _MK_ADDR_CONST(0x5ac) +#define DC_WINC_A_COLOR_PALETTE_172_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_172_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_172_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_172_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_172_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_172_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_172_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_172_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_172_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_172_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_172_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_172_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_172_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_172_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_172_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_172_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_172_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_172_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_172_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_172_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_172_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_172_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_172_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_172_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_172_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_172_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_172_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_172_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_172_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_172_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_172_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_172_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_172_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_172_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_172_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_173 +#define DC_WINC_A_COLOR_PALETTE_173 _MK_ADDR_CONST(0x5ad) +#define DC_WINC_A_COLOR_PALETTE_173_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_173_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_173_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_173_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_173_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_173_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_173_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_173_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_173_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_173_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_173_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_173_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_173_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_173_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_173_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_173_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_173_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_173_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_173_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_173_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_173_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_173_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_173_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_173_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_173_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_173_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_173_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_173_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_173_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_173_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_173_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_173_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_173_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_173_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_173_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_174 +#define DC_WINC_A_COLOR_PALETTE_174 _MK_ADDR_CONST(0x5ae) +#define DC_WINC_A_COLOR_PALETTE_174_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_174_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_174_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_174_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_174_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_174_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_174_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_174_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_174_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_174_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_174_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_174_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_174_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_174_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_174_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_174_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_174_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_174_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_174_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_174_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_174_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_174_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_174_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_174_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_174_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_174_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_174_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_174_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_174_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_174_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_174_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_174_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_174_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_174_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_174_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_175 +#define DC_WINC_A_COLOR_PALETTE_175 _MK_ADDR_CONST(0x5af) +#define DC_WINC_A_COLOR_PALETTE_175_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_175_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_175_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_175_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_175_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_175_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_175_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_175_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_175_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_175_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_175_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_175_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_175_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_175_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_175_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_175_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_175_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_175_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_175_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_175_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_175_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_175_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_175_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_175_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_175_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_175_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_175_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_175_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_175_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_175_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_175_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_175_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_175_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_175_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_175_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_176 +#define DC_WINC_A_COLOR_PALETTE_176 _MK_ADDR_CONST(0x5b0) +#define DC_WINC_A_COLOR_PALETTE_176_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_176_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_176_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_176_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_176_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_176_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_176_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_176_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_176_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_176_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_176_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_176_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_176_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_176_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_176_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_176_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_176_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_176_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_176_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_176_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_176_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_176_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_176_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_176_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_176_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_176_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_176_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_176_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_176_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_176_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_176_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_176_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_176_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_176_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_176_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_177 +#define DC_WINC_A_COLOR_PALETTE_177 _MK_ADDR_CONST(0x5b1) +#define DC_WINC_A_COLOR_PALETTE_177_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_177_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_177_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_177_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_177_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_177_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_177_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_177_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_177_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_177_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_177_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_177_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_177_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_177_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_177_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_177_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_177_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_177_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_177_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_177_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_177_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_177_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_177_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_177_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_177_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_177_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_177_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_177_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_177_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_177_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_177_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_177_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_177_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_177_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_177_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_178 +#define DC_WINC_A_COLOR_PALETTE_178 _MK_ADDR_CONST(0x5b2) +#define DC_WINC_A_COLOR_PALETTE_178_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_178_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_178_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_178_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_178_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_178_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_178_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_178_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_178_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_178_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_178_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_178_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_178_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_178_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_178_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_178_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_178_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_178_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_178_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_178_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_178_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_178_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_178_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_178_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_178_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_178_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_178_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_178_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_178_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_178_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_178_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_178_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_178_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_178_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_178_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_179 +#define DC_WINC_A_COLOR_PALETTE_179 _MK_ADDR_CONST(0x5b3) +#define DC_WINC_A_COLOR_PALETTE_179_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_179_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_179_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_179_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_179_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_179_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_179_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_179_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_179_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_179_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_179_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_179_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_179_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_179_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_179_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_179_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_179_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_179_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_179_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_179_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_179_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_179_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_179_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_179_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_179_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_179_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_179_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_179_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_179_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_179_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_179_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_179_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_179_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_179_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_179_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_180 +#define DC_WINC_A_COLOR_PALETTE_180 _MK_ADDR_CONST(0x5b4) +#define DC_WINC_A_COLOR_PALETTE_180_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_180_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_180_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_180_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_180_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_180_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_180_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_180_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_180_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_180_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_180_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_180_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_180_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_180_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_180_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_180_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_180_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_180_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_180_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_180_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_180_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_180_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_180_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_180_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_180_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_180_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_180_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_180_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_180_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_180_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_180_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_180_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_180_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_180_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_180_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_181 +#define DC_WINC_A_COLOR_PALETTE_181 _MK_ADDR_CONST(0x5b5) +#define DC_WINC_A_COLOR_PALETTE_181_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_181_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_181_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_181_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_181_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_181_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_181_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_181_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_181_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_181_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_181_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_181_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_181_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_181_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_181_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_181_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_181_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_181_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_181_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_181_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_181_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_181_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_181_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_181_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_181_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_181_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_181_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_181_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_181_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_181_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_181_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_181_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_181_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_181_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_181_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_182 +#define DC_WINC_A_COLOR_PALETTE_182 _MK_ADDR_CONST(0x5b6) +#define DC_WINC_A_COLOR_PALETTE_182_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_182_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_182_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_182_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_182_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_182_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_182_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_182_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_182_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_182_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_182_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_182_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_182_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_182_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_182_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_182_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_182_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_182_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_182_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_182_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_182_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_182_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_182_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_182_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_182_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_182_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_182_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_182_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_182_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_182_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_182_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_182_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_182_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_182_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_182_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_183 +#define DC_WINC_A_COLOR_PALETTE_183 _MK_ADDR_CONST(0x5b7) +#define DC_WINC_A_COLOR_PALETTE_183_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_183_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_183_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_183_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_183_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_183_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_183_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_183_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_183_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_183_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_183_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_183_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_183_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_183_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_183_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_183_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_183_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_183_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_183_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_183_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_183_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_183_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_183_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_183_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_183_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_183_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_183_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_183_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_183_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_183_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_183_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_183_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_183_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_183_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_183_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_184 +#define DC_WINC_A_COLOR_PALETTE_184 _MK_ADDR_CONST(0x5b8) +#define DC_WINC_A_COLOR_PALETTE_184_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_184_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_184_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_184_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_184_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_184_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_184_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_184_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_184_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_184_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_184_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_184_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_184_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_184_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_184_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_184_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_184_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_184_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_184_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_184_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_184_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_184_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_184_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_184_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_184_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_184_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_184_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_184_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_184_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_184_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_184_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_184_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_184_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_184_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_184_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_185 +#define DC_WINC_A_COLOR_PALETTE_185 _MK_ADDR_CONST(0x5b9) +#define DC_WINC_A_COLOR_PALETTE_185_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_185_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_185_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_185_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_185_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_185_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_185_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_185_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_185_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_185_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_185_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_185_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_185_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_185_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_185_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_185_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_185_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_185_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_185_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_185_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_185_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_185_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_185_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_185_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_185_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_185_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_185_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_185_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_185_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_185_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_185_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_185_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_185_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_185_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_185_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_186 +#define DC_WINC_A_COLOR_PALETTE_186 _MK_ADDR_CONST(0x5ba) +#define DC_WINC_A_COLOR_PALETTE_186_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_186_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_186_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_186_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_186_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_186_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_186_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_186_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_186_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_186_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_186_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_186_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_186_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_186_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_186_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_186_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_186_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_186_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_186_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_186_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_186_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_186_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_186_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_186_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_186_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_186_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_186_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_186_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_186_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_186_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_186_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_186_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_186_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_186_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_186_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_187 +#define DC_WINC_A_COLOR_PALETTE_187 _MK_ADDR_CONST(0x5bb) +#define DC_WINC_A_COLOR_PALETTE_187_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_187_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_187_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_187_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_187_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_187_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_187_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_187_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_187_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_187_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_187_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_187_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_187_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_187_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_187_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_187_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_187_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_187_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_187_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_187_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_187_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_187_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_187_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_187_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_187_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_187_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_187_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_187_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_187_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_187_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_187_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_187_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_187_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_187_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_187_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_188 +#define DC_WINC_A_COLOR_PALETTE_188 _MK_ADDR_CONST(0x5bc) +#define DC_WINC_A_COLOR_PALETTE_188_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_188_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_188_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_188_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_188_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_188_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_188_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_188_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_188_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_188_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_188_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_188_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_188_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_188_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_188_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_188_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_188_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_188_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_188_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_188_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_188_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_188_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_188_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_188_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_188_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_188_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_188_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_188_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_188_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_188_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_188_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_188_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_188_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_188_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_188_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_189 +#define DC_WINC_A_COLOR_PALETTE_189 _MK_ADDR_CONST(0x5bd) +#define DC_WINC_A_COLOR_PALETTE_189_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_189_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_189_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_189_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_189_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_189_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_189_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_189_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_189_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_189_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_189_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_189_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_189_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_189_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_189_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_189_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_189_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_189_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_189_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_189_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_189_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_189_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_189_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_189_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_189_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_189_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_189_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_189_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_189_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_189_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_189_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_189_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_189_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_189_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_189_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_190 +#define DC_WINC_A_COLOR_PALETTE_190 _MK_ADDR_CONST(0x5be) +#define DC_WINC_A_COLOR_PALETTE_190_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_190_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_190_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_190_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_190_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_190_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_190_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_190_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_190_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_190_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_190_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_190_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_190_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_190_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_190_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_190_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_190_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_190_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_190_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_190_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_190_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_190_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_190_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_190_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_190_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_190_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_190_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_190_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_190_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_190_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_190_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_190_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_190_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_190_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_190_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_191 +#define DC_WINC_A_COLOR_PALETTE_191 _MK_ADDR_CONST(0x5bf) +#define DC_WINC_A_COLOR_PALETTE_191_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_191_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_191_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_191_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_191_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_191_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_191_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_191_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_191_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_191_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_191_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_191_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_191_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_191_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_191_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_191_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_191_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_191_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_191_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_191_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_191_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_191_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_191_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_191_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_191_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_191_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_191_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_191_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_191_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_191_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_191_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_191_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_191_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_191_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_191_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_192 +#define DC_WINC_A_COLOR_PALETTE_192 _MK_ADDR_CONST(0x5c0) +#define DC_WINC_A_COLOR_PALETTE_192_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_192_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_192_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_192_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_192_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_192_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_192_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_192_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_192_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_192_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_192_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_192_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_192_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_192_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_192_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_192_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_192_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_192_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_192_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_192_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_192_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_192_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_192_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_192_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_192_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_192_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_192_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_192_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_192_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_192_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_192_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_192_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_192_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_192_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_192_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_193 +#define DC_WINC_A_COLOR_PALETTE_193 _MK_ADDR_CONST(0x5c1) +#define DC_WINC_A_COLOR_PALETTE_193_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_193_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_193_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_193_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_193_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_193_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_193_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_193_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_193_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_193_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_193_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_193_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_193_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_193_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_193_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_193_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_193_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_193_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_193_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_193_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_193_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_193_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_193_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_193_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_193_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_193_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_193_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_193_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_193_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_193_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_193_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_193_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_193_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_193_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_193_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_194 +#define DC_WINC_A_COLOR_PALETTE_194 _MK_ADDR_CONST(0x5c2) +#define DC_WINC_A_COLOR_PALETTE_194_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_194_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_194_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_194_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_194_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_194_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_194_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_194_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_194_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_194_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_194_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_194_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_194_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_194_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_194_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_194_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_194_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_194_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_194_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_194_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_194_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_194_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_194_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_194_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_194_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_194_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_194_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_194_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_194_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_194_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_194_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_194_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_194_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_194_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_194_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_195 +#define DC_WINC_A_COLOR_PALETTE_195 _MK_ADDR_CONST(0x5c3) +#define DC_WINC_A_COLOR_PALETTE_195_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_195_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_195_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_195_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_195_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_195_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_195_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_195_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_195_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_195_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_195_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_195_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_195_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_195_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_195_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_195_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_195_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_195_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_195_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_195_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_195_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_195_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_195_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_195_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_195_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_195_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_195_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_195_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_195_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_195_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_195_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_195_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_195_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_195_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_195_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_196 +#define DC_WINC_A_COLOR_PALETTE_196 _MK_ADDR_CONST(0x5c4) +#define DC_WINC_A_COLOR_PALETTE_196_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_196_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_196_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_196_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_196_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_196_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_196_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_196_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_196_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_196_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_196_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_196_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_196_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_196_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_196_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_196_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_196_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_196_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_196_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_196_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_196_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_196_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_196_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_196_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_196_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_196_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_196_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_196_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_196_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_196_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_196_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_196_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_196_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_196_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_196_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_197 +#define DC_WINC_A_COLOR_PALETTE_197 _MK_ADDR_CONST(0x5c5) +#define DC_WINC_A_COLOR_PALETTE_197_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_197_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_197_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_197_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_197_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_197_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_197_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_197_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_197_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_197_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_197_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_197_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_197_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_197_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_197_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_197_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_197_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_197_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_197_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_197_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_197_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_197_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_197_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_197_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_197_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_197_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_197_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_197_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_197_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_197_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_197_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_197_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_197_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_197_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_197_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_198 +#define DC_WINC_A_COLOR_PALETTE_198 _MK_ADDR_CONST(0x5c6) +#define DC_WINC_A_COLOR_PALETTE_198_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_198_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_198_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_198_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_198_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_198_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_198_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_198_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_198_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_198_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_198_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_198_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_198_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_198_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_198_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_198_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_198_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_198_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_198_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_198_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_198_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_198_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_198_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_198_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_198_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_198_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_198_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_198_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_198_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_198_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_198_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_198_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_198_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_198_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_198_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_199 +#define DC_WINC_A_COLOR_PALETTE_199 _MK_ADDR_CONST(0x5c7) +#define DC_WINC_A_COLOR_PALETTE_199_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_199_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_199_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_199_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_199_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_199_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_199_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_199_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_199_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_199_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_199_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_199_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_199_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_199_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_199_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_199_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_199_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_199_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_199_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_199_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_199_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_199_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_199_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_199_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_199_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_199_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_199_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_199_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_199_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_199_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_199_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_199_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_199_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_199_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_199_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_200 +#define DC_WINC_A_COLOR_PALETTE_200 _MK_ADDR_CONST(0x5c8) +#define DC_WINC_A_COLOR_PALETTE_200_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_200_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_200_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_200_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_200_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_200_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_200_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_200_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_200_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_200_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_200_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_200_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_200_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_200_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_200_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_200_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_200_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_200_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_200_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_200_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_200_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_200_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_200_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_200_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_200_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_200_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_200_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_200_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_200_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_200_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_200_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_200_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_200_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_200_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_200_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_201 +#define DC_WINC_A_COLOR_PALETTE_201 _MK_ADDR_CONST(0x5c9) +#define DC_WINC_A_COLOR_PALETTE_201_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_201_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_201_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_201_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_201_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_201_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_201_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_201_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_201_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_201_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_201_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_201_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_201_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_201_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_201_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_201_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_201_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_201_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_201_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_201_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_201_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_201_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_201_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_201_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_201_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_201_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_201_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_201_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_201_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_201_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_201_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_201_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_201_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_201_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_201_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_202 +#define DC_WINC_A_COLOR_PALETTE_202 _MK_ADDR_CONST(0x5ca) +#define DC_WINC_A_COLOR_PALETTE_202_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_202_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_202_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_202_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_202_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_202_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_202_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_202_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_202_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_202_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_202_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_202_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_202_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_202_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_202_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_202_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_202_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_202_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_202_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_202_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_202_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_202_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_202_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_202_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_202_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_202_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_202_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_202_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_202_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_202_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_202_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_202_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_202_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_202_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_202_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_203 +#define DC_WINC_A_COLOR_PALETTE_203 _MK_ADDR_CONST(0x5cb) +#define DC_WINC_A_COLOR_PALETTE_203_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_203_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_203_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_203_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_203_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_203_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_203_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_203_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_203_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_203_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_203_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_203_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_203_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_203_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_203_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_203_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_203_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_203_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_203_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_203_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_203_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_203_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_203_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_203_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_203_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_203_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_203_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_203_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_203_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_203_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_203_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_203_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_203_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_203_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_203_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_204 +#define DC_WINC_A_COLOR_PALETTE_204 _MK_ADDR_CONST(0x5cc) +#define DC_WINC_A_COLOR_PALETTE_204_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_204_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_204_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_204_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_204_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_204_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_204_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_204_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_204_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_204_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_204_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_204_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_204_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_204_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_204_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_204_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_204_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_204_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_204_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_204_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_204_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_204_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_204_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_204_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_204_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_204_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_204_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_204_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_204_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_204_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_204_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_204_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_204_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_204_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_204_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_205 +#define DC_WINC_A_COLOR_PALETTE_205 _MK_ADDR_CONST(0x5cd) +#define DC_WINC_A_COLOR_PALETTE_205_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_205_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_205_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_205_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_205_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_205_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_205_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_205_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_205_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_205_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_205_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_205_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_205_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_205_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_205_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_205_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_205_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_205_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_205_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_205_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_205_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_205_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_205_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_205_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_205_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_205_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_205_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_205_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_205_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_205_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_205_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_205_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_205_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_205_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_205_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_206 +#define DC_WINC_A_COLOR_PALETTE_206 _MK_ADDR_CONST(0x5ce) +#define DC_WINC_A_COLOR_PALETTE_206_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_206_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_206_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_206_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_206_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_206_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_206_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_206_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_206_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_206_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_206_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_206_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_206_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_206_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_206_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_206_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_206_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_206_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_206_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_206_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_206_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_206_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_206_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_206_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_206_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_206_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_206_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_206_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_206_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_206_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_206_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_206_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_206_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_206_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_206_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_207 +#define DC_WINC_A_COLOR_PALETTE_207 _MK_ADDR_CONST(0x5cf) +#define DC_WINC_A_COLOR_PALETTE_207_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_207_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_207_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_207_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_207_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_207_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_207_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_207_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_207_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_207_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_207_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_207_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_207_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_207_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_207_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_207_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_207_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_207_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_207_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_207_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_207_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_207_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_207_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_207_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_207_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_207_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_207_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_207_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_207_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_207_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_207_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_207_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_207_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_207_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_207_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_208 +#define DC_WINC_A_COLOR_PALETTE_208 _MK_ADDR_CONST(0x5d0) +#define DC_WINC_A_COLOR_PALETTE_208_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_208_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_208_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_208_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_208_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_208_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_208_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_208_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_208_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_208_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_208_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_208_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_208_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_208_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_208_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_208_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_208_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_208_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_208_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_208_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_208_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_208_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_208_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_208_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_208_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_208_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_208_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_208_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_208_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_208_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_208_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_208_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_208_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_208_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_208_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_209 +#define DC_WINC_A_COLOR_PALETTE_209 _MK_ADDR_CONST(0x5d1) +#define DC_WINC_A_COLOR_PALETTE_209_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_209_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_209_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_209_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_209_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_209_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_209_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_209_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_209_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_209_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_209_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_209_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_209_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_209_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_209_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_209_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_209_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_209_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_209_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_209_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_209_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_209_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_209_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_209_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_209_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_209_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_209_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_209_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_209_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_209_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_209_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_209_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_209_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_209_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_209_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_210 +#define DC_WINC_A_COLOR_PALETTE_210 _MK_ADDR_CONST(0x5d2) +#define DC_WINC_A_COLOR_PALETTE_210_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_210_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_210_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_210_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_210_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_210_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_210_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_210_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_210_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_210_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_210_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_210_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_210_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_210_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_210_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_210_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_210_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_210_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_210_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_210_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_210_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_210_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_210_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_210_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_210_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_210_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_210_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_210_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_210_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_210_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_210_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_210_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_210_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_210_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_210_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_211 +#define DC_WINC_A_COLOR_PALETTE_211 _MK_ADDR_CONST(0x5d3) +#define DC_WINC_A_COLOR_PALETTE_211_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_211_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_211_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_211_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_211_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_211_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_211_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_211_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_211_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_211_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_211_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_211_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_211_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_211_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_211_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_211_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_211_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_211_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_211_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_211_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_211_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_211_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_211_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_211_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_211_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_211_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_211_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_211_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_211_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_211_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_211_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_211_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_211_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_211_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_211_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_212 +#define DC_WINC_A_COLOR_PALETTE_212 _MK_ADDR_CONST(0x5d4) +#define DC_WINC_A_COLOR_PALETTE_212_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_212_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_212_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_212_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_212_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_212_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_212_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_212_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_212_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_212_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_212_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_212_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_212_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_212_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_212_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_212_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_212_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_212_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_212_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_212_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_212_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_212_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_212_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_212_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_212_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_212_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_212_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_212_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_212_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_212_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_212_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_212_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_212_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_212_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_212_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_213 +#define DC_WINC_A_COLOR_PALETTE_213 _MK_ADDR_CONST(0x5d5) +#define DC_WINC_A_COLOR_PALETTE_213_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_213_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_213_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_213_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_213_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_213_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_213_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_213_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_213_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_213_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_213_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_213_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_213_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_213_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_213_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_213_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_213_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_213_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_213_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_213_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_213_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_213_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_213_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_213_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_213_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_213_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_213_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_213_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_213_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_213_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_213_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_213_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_213_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_213_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_213_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_214 +#define DC_WINC_A_COLOR_PALETTE_214 _MK_ADDR_CONST(0x5d6) +#define DC_WINC_A_COLOR_PALETTE_214_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_214_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_214_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_214_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_214_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_214_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_214_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_214_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_214_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_214_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_214_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_214_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_214_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_214_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_214_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_214_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_214_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_214_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_214_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_214_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_214_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_214_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_214_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_214_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_214_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_214_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_214_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_214_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_214_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_214_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_214_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_214_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_214_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_214_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_214_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_215 +#define DC_WINC_A_COLOR_PALETTE_215 _MK_ADDR_CONST(0x5d7) +#define DC_WINC_A_COLOR_PALETTE_215_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_215_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_215_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_215_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_215_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_215_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_215_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_215_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_215_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_215_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_215_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_215_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_215_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_215_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_215_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_215_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_215_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_215_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_215_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_215_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_215_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_215_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_215_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_215_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_215_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_215_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_215_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_215_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_215_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_215_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_215_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_215_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_215_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_215_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_215_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_216 +#define DC_WINC_A_COLOR_PALETTE_216 _MK_ADDR_CONST(0x5d8) +#define DC_WINC_A_COLOR_PALETTE_216_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_216_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_216_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_216_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_216_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_216_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_216_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_216_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_216_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_216_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_216_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_216_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_216_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_216_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_216_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_216_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_216_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_216_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_216_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_216_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_216_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_216_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_216_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_216_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_216_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_216_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_216_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_216_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_216_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_216_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_216_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_216_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_216_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_216_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_216_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_217 +#define DC_WINC_A_COLOR_PALETTE_217 _MK_ADDR_CONST(0x5d9) +#define DC_WINC_A_COLOR_PALETTE_217_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_217_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_217_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_217_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_217_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_217_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_217_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_217_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_217_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_217_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_217_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_217_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_217_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_217_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_217_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_217_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_217_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_217_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_217_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_217_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_217_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_217_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_217_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_217_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_217_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_217_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_217_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_217_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_217_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_217_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_217_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_217_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_217_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_217_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_217_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_218 +#define DC_WINC_A_COLOR_PALETTE_218 _MK_ADDR_CONST(0x5da) +#define DC_WINC_A_COLOR_PALETTE_218_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_218_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_218_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_218_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_218_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_218_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_218_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_218_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_218_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_218_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_218_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_218_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_218_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_218_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_218_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_218_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_218_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_218_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_218_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_218_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_218_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_218_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_218_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_218_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_218_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_218_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_218_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_218_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_218_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_218_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_218_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_218_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_218_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_218_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_218_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_219 +#define DC_WINC_A_COLOR_PALETTE_219 _MK_ADDR_CONST(0x5db) +#define DC_WINC_A_COLOR_PALETTE_219_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_219_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_219_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_219_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_219_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_219_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_219_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_219_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_219_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_219_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_219_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_219_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_219_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_219_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_219_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_219_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_219_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_219_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_219_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_219_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_219_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_219_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_219_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_219_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_219_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_219_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_219_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_219_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_219_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_219_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_219_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_219_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_219_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_219_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_219_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_220 +#define DC_WINC_A_COLOR_PALETTE_220 _MK_ADDR_CONST(0x5dc) +#define DC_WINC_A_COLOR_PALETTE_220_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_220_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_220_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_220_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_220_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_220_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_220_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_220_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_220_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_220_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_220_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_220_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_220_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_220_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_220_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_220_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_220_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_220_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_220_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_220_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_220_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_220_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_220_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_220_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_220_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_220_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_220_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_220_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_220_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_220_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_220_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_220_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_220_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_220_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_220_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_221 +#define DC_WINC_A_COLOR_PALETTE_221 _MK_ADDR_CONST(0x5dd) +#define DC_WINC_A_COLOR_PALETTE_221_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_221_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_221_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_221_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_221_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_221_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_221_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_221_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_221_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_221_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_221_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_221_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_221_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_221_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_221_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_221_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_221_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_221_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_221_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_221_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_221_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_221_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_221_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_221_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_221_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_221_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_221_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_221_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_221_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_221_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_221_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_221_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_221_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_221_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_221_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_222 +#define DC_WINC_A_COLOR_PALETTE_222 _MK_ADDR_CONST(0x5de) +#define DC_WINC_A_COLOR_PALETTE_222_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_222_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_222_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_222_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_222_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_222_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_222_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_222_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_222_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_222_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_222_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_222_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_222_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_222_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_222_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_222_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_222_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_222_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_222_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_222_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_222_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_222_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_222_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_222_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_222_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_222_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_222_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_222_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_222_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_222_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_222_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_222_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_222_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_222_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_222_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_223 +#define DC_WINC_A_COLOR_PALETTE_223 _MK_ADDR_CONST(0x5df) +#define DC_WINC_A_COLOR_PALETTE_223_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_223_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_223_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_223_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_223_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_223_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_223_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_223_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_223_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_223_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_223_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_223_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_223_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_223_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_223_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_223_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_223_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_223_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_223_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_223_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_223_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_223_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_223_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_223_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_223_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_223_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_223_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_223_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_223_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_223_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_223_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_223_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_223_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_223_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_223_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_224 +#define DC_WINC_A_COLOR_PALETTE_224 _MK_ADDR_CONST(0x5e0) +#define DC_WINC_A_COLOR_PALETTE_224_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_224_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_224_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_224_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_224_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_224_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_224_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_224_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_224_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_224_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_224_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_224_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_224_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_224_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_224_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_224_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_224_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_224_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_224_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_224_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_224_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_224_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_224_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_224_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_224_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_224_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_224_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_224_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_224_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_224_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_224_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_224_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_224_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_224_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_224_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_225 +#define DC_WINC_A_COLOR_PALETTE_225 _MK_ADDR_CONST(0x5e1) +#define DC_WINC_A_COLOR_PALETTE_225_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_225_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_225_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_225_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_225_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_225_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_225_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_225_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_225_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_225_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_225_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_225_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_225_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_225_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_225_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_225_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_225_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_225_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_225_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_225_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_225_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_225_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_225_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_225_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_225_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_225_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_225_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_225_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_225_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_225_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_225_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_225_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_225_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_225_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_225_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_226 +#define DC_WINC_A_COLOR_PALETTE_226 _MK_ADDR_CONST(0x5e2) +#define DC_WINC_A_COLOR_PALETTE_226_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_226_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_226_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_226_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_226_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_226_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_226_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_226_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_226_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_226_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_226_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_226_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_226_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_226_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_226_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_226_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_226_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_226_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_226_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_226_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_226_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_226_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_226_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_226_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_226_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_226_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_226_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_226_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_226_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_226_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_226_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_226_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_226_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_226_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_226_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_227 +#define DC_WINC_A_COLOR_PALETTE_227 _MK_ADDR_CONST(0x5e3) +#define DC_WINC_A_COLOR_PALETTE_227_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_227_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_227_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_227_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_227_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_227_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_227_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_227_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_227_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_227_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_227_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_227_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_227_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_227_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_227_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_227_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_227_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_227_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_227_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_227_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_227_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_227_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_227_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_227_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_227_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_227_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_227_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_227_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_227_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_227_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_227_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_227_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_227_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_227_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_227_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_228 +#define DC_WINC_A_COLOR_PALETTE_228 _MK_ADDR_CONST(0x5e4) +#define DC_WINC_A_COLOR_PALETTE_228_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_228_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_228_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_228_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_228_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_228_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_228_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_228_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_228_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_228_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_228_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_228_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_228_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_228_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_228_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_228_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_228_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_228_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_228_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_228_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_228_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_228_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_228_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_228_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_228_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_228_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_228_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_228_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_228_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_228_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_228_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_228_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_228_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_228_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_228_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_229 +#define DC_WINC_A_COLOR_PALETTE_229 _MK_ADDR_CONST(0x5e5) +#define DC_WINC_A_COLOR_PALETTE_229_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_229_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_229_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_229_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_229_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_229_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_229_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_229_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_229_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_229_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_229_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_229_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_229_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_229_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_229_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_229_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_229_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_229_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_229_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_229_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_229_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_229_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_229_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_229_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_229_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_229_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_229_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_229_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_229_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_229_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_229_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_229_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_229_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_229_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_229_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_230 +#define DC_WINC_A_COLOR_PALETTE_230 _MK_ADDR_CONST(0x5e6) +#define DC_WINC_A_COLOR_PALETTE_230_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_230_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_230_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_230_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_230_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_230_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_230_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_230_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_230_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_230_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_230_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_230_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_230_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_230_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_230_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_230_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_230_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_230_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_230_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_230_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_230_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_230_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_230_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_230_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_230_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_230_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_230_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_230_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_230_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_230_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_230_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_230_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_230_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_230_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_230_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_231 +#define DC_WINC_A_COLOR_PALETTE_231 _MK_ADDR_CONST(0x5e7) +#define DC_WINC_A_COLOR_PALETTE_231_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_231_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_231_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_231_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_231_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_231_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_231_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_231_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_231_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_231_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_231_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_231_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_231_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_231_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_231_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_231_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_231_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_231_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_231_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_231_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_231_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_231_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_231_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_231_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_231_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_231_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_231_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_231_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_231_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_231_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_231_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_231_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_231_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_231_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_231_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_232 +#define DC_WINC_A_COLOR_PALETTE_232 _MK_ADDR_CONST(0x5e8) +#define DC_WINC_A_COLOR_PALETTE_232_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_232_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_232_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_232_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_232_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_232_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_232_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_232_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_232_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_232_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_232_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_232_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_232_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_232_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_232_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_232_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_232_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_232_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_232_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_232_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_232_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_232_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_232_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_232_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_232_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_232_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_232_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_232_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_232_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_232_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_232_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_232_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_232_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_232_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_232_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_233 +#define DC_WINC_A_COLOR_PALETTE_233 _MK_ADDR_CONST(0x5e9) +#define DC_WINC_A_COLOR_PALETTE_233_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_233_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_233_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_233_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_233_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_233_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_233_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_233_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_233_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_233_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_233_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_233_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_233_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_233_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_233_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_233_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_233_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_233_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_233_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_233_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_233_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_233_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_233_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_233_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_233_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_233_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_233_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_233_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_233_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_233_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_233_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_233_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_233_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_233_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_233_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_234 +#define DC_WINC_A_COLOR_PALETTE_234 _MK_ADDR_CONST(0x5ea) +#define DC_WINC_A_COLOR_PALETTE_234_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_234_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_234_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_234_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_234_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_234_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_234_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_234_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_234_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_234_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_234_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_234_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_234_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_234_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_234_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_234_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_234_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_234_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_234_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_234_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_234_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_234_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_234_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_234_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_234_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_234_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_234_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_234_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_234_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_234_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_234_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_234_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_234_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_234_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_234_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_235 +#define DC_WINC_A_COLOR_PALETTE_235 _MK_ADDR_CONST(0x5eb) +#define DC_WINC_A_COLOR_PALETTE_235_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_235_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_235_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_235_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_235_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_235_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_235_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_235_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_235_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_235_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_235_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_235_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_235_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_235_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_235_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_235_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_235_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_235_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_235_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_235_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_235_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_235_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_235_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_235_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_235_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_235_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_235_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_235_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_235_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_235_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_235_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_235_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_235_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_235_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_235_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_236 +#define DC_WINC_A_COLOR_PALETTE_236 _MK_ADDR_CONST(0x5ec) +#define DC_WINC_A_COLOR_PALETTE_236_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_236_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_236_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_236_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_236_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_236_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_236_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_236_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_236_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_236_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_236_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_236_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_236_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_236_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_236_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_236_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_236_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_236_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_236_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_236_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_236_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_236_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_236_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_236_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_236_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_236_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_236_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_236_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_236_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_236_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_236_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_236_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_236_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_236_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_236_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_237 +#define DC_WINC_A_COLOR_PALETTE_237 _MK_ADDR_CONST(0x5ed) +#define DC_WINC_A_COLOR_PALETTE_237_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_237_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_237_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_237_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_237_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_237_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_237_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_237_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_237_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_237_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_237_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_237_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_237_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_237_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_237_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_237_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_237_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_237_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_237_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_237_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_237_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_237_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_237_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_237_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_237_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_237_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_237_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_237_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_237_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_237_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_237_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_237_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_237_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_237_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_237_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_238 +#define DC_WINC_A_COLOR_PALETTE_238 _MK_ADDR_CONST(0x5ee) +#define DC_WINC_A_COLOR_PALETTE_238_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_238_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_238_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_238_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_238_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_238_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_238_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_238_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_238_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_238_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_238_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_238_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_238_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_238_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_238_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_238_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_238_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_238_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_238_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_238_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_238_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_238_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_238_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_238_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_238_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_238_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_238_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_238_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_238_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_238_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_238_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_238_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_238_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_238_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_238_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_239 +#define DC_WINC_A_COLOR_PALETTE_239 _MK_ADDR_CONST(0x5ef) +#define DC_WINC_A_COLOR_PALETTE_239_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_239_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_239_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_239_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_239_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_239_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_239_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_239_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_239_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_239_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_239_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_239_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_239_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_239_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_239_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_239_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_239_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_239_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_239_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_239_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_239_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_239_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_239_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_239_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_239_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_239_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_239_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_239_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_239_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_239_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_239_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_239_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_239_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_239_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_239_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_240 +#define DC_WINC_A_COLOR_PALETTE_240 _MK_ADDR_CONST(0x5f0) +#define DC_WINC_A_COLOR_PALETTE_240_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_240_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_240_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_240_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_240_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_240_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_240_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_240_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_240_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_240_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_240_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_240_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_240_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_240_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_240_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_240_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_240_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_240_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_240_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_240_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_240_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_240_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_240_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_240_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_240_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_240_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_240_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_240_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_240_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_240_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_240_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_240_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_240_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_240_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_240_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_241 +#define DC_WINC_A_COLOR_PALETTE_241 _MK_ADDR_CONST(0x5f1) +#define DC_WINC_A_COLOR_PALETTE_241_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_241_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_241_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_241_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_241_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_241_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_241_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_241_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_241_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_241_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_241_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_241_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_241_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_241_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_241_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_241_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_241_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_241_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_241_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_241_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_241_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_241_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_241_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_241_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_241_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_241_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_241_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_241_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_241_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_241_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_241_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_241_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_241_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_241_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_241_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_242 +#define DC_WINC_A_COLOR_PALETTE_242 _MK_ADDR_CONST(0x5f2) +#define DC_WINC_A_COLOR_PALETTE_242_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_242_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_242_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_242_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_242_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_242_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_242_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_242_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_242_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_242_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_242_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_242_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_242_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_242_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_242_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_242_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_242_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_242_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_242_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_242_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_242_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_242_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_242_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_242_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_242_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_242_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_242_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_242_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_242_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_242_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_242_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_242_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_242_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_242_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_242_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_243 +#define DC_WINC_A_COLOR_PALETTE_243 _MK_ADDR_CONST(0x5f3) +#define DC_WINC_A_COLOR_PALETTE_243_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_243_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_243_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_243_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_243_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_243_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_243_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_243_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_243_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_243_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_243_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_243_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_243_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_243_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_243_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_243_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_243_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_243_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_243_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_243_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_243_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_243_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_243_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_243_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_243_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_243_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_243_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_243_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_243_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_243_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_243_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_243_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_243_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_243_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_243_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_244 +#define DC_WINC_A_COLOR_PALETTE_244 _MK_ADDR_CONST(0x5f4) +#define DC_WINC_A_COLOR_PALETTE_244_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_244_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_244_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_244_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_244_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_244_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_244_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_244_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_244_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_244_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_244_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_244_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_244_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_244_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_244_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_244_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_244_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_244_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_244_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_244_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_244_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_244_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_244_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_244_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_244_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_244_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_244_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_244_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_244_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_244_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_244_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_244_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_244_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_244_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_244_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_245 +#define DC_WINC_A_COLOR_PALETTE_245 _MK_ADDR_CONST(0x5f5) +#define DC_WINC_A_COLOR_PALETTE_245_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_245_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_245_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_245_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_245_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_245_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_245_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_245_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_245_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_245_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_245_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_245_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_245_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_245_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_245_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_245_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_245_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_245_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_245_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_245_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_245_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_245_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_245_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_245_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_245_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_245_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_245_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_245_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_245_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_245_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_245_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_245_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_245_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_245_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_245_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_246 +#define DC_WINC_A_COLOR_PALETTE_246 _MK_ADDR_CONST(0x5f6) +#define DC_WINC_A_COLOR_PALETTE_246_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_246_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_246_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_246_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_246_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_246_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_246_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_246_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_246_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_246_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_246_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_246_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_246_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_246_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_246_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_246_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_246_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_246_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_246_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_246_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_246_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_246_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_246_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_246_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_246_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_246_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_246_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_246_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_246_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_246_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_246_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_246_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_246_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_246_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_246_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_247 +#define DC_WINC_A_COLOR_PALETTE_247 _MK_ADDR_CONST(0x5f7) +#define DC_WINC_A_COLOR_PALETTE_247_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_247_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_247_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_247_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_247_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_247_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_247_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_247_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_247_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_247_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_247_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_247_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_247_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_247_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_247_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_247_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_247_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_247_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_247_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_247_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_247_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_247_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_247_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_247_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_247_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_247_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_247_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_247_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_247_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_247_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_247_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_247_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_247_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_247_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_247_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_248 +#define DC_WINC_A_COLOR_PALETTE_248 _MK_ADDR_CONST(0x5f8) +#define DC_WINC_A_COLOR_PALETTE_248_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_248_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_248_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_248_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_248_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_248_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_248_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_248_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_248_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_248_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_248_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_248_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_248_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_248_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_248_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_248_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_248_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_248_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_248_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_248_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_248_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_248_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_248_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_248_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_248_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_248_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_248_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_248_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_248_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_248_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_248_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_248_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_248_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_248_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_248_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_249 +#define DC_WINC_A_COLOR_PALETTE_249 _MK_ADDR_CONST(0x5f9) +#define DC_WINC_A_COLOR_PALETTE_249_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_249_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_249_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_249_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_249_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_249_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_249_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_249_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_249_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_249_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_249_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_249_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_249_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_249_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_249_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_249_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_249_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_249_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_249_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_249_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_249_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_249_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_249_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_249_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_249_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_249_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_249_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_249_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_249_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_249_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_249_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_249_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_249_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_249_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_249_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_250 +#define DC_WINC_A_COLOR_PALETTE_250 _MK_ADDR_CONST(0x5fa) +#define DC_WINC_A_COLOR_PALETTE_250_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_250_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_250_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_250_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_250_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_250_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_250_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_250_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_250_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_250_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_250_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_250_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_250_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_250_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_250_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_250_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_250_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_250_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_250_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_250_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_250_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_250_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_250_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_250_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_250_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_250_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_250_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_250_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_250_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_250_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_250_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_250_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_250_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_250_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_250_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_251 +#define DC_WINC_A_COLOR_PALETTE_251 _MK_ADDR_CONST(0x5fb) +#define DC_WINC_A_COLOR_PALETTE_251_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_251_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_251_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_251_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_251_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_251_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_251_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_251_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_251_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_251_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_251_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_251_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_251_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_251_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_251_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_251_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_251_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_251_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_251_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_251_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_251_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_251_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_251_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_251_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_251_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_251_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_251_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_251_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_251_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_251_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_251_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_251_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_251_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_251_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_251_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_252 +#define DC_WINC_A_COLOR_PALETTE_252 _MK_ADDR_CONST(0x5fc) +#define DC_WINC_A_COLOR_PALETTE_252_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_252_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_252_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_252_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_252_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_252_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_252_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_252_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_252_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_252_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_252_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_252_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_252_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_252_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_252_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_252_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_252_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_252_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_252_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_252_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_252_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_252_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_252_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_252_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_252_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_252_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_252_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_252_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_252_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_252_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_252_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_252_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_252_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_252_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_252_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_253 +#define DC_WINC_A_COLOR_PALETTE_253 _MK_ADDR_CONST(0x5fd) +#define DC_WINC_A_COLOR_PALETTE_253_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_253_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_253_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_253_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_253_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_253_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_253_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_253_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_253_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_253_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_253_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_253_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_253_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_253_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_253_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_253_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_253_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_253_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_253_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_253_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_253_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_253_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_253_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_253_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_253_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_253_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_253_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_253_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_253_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_253_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_253_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_253_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_253_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_253_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_253_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_254 +#define DC_WINC_A_COLOR_PALETTE_254 _MK_ADDR_CONST(0x5fe) +#define DC_WINC_A_COLOR_PALETTE_254_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_254_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_254_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_254_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_254_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_254_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_254_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_254_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_254_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_254_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_254_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_254_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_254_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_254_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_254_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_254_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_254_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_254_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_254_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_254_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_254_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_254_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_254_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_254_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_254_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_254_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_254_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_254_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_254_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_254_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_254_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_254_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_254_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_254_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_254_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_WINC_A_COLOR_PALETTE_255 +#define DC_WINC_A_COLOR_PALETTE_255 _MK_ADDR_CONST(0x5ff) +#define DC_WINC_A_COLOR_PALETTE_255_SECURE 0x0 +#define DC_WINC_A_COLOR_PALETTE_255_WORD_COUNT 0x1 +#define DC_WINC_A_COLOR_PALETTE_255_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_255_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_255_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_255_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_255_READ_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_255_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_WINC_A_COLOR_PALETTE_255_A_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_COLOR_PALETTE_255_A_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_255_A_COLOR_PALETTE_R_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_255_A_COLOR_PALETTE_R_RANGE 7:0 +#define DC_WINC_A_COLOR_PALETTE_255_A_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_255_A_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_255_A_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_255_A_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_255_A_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_255_A_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_COLOR_PALETTE_255_A_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_255_A_COLOR_PALETTE_G_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_255_A_COLOR_PALETTE_G_RANGE 15:8 +#define DC_WINC_A_COLOR_PALETTE_255_A_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_255_A_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_255_A_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_255_A_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_255_A_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_COLOR_PALETTE_255_A_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_COLOR_PALETTE_255_A_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_COLOR_PALETTE_255_A_COLOR_PALETTE_B_SHIFT) +#define DC_WINC_A_COLOR_PALETTE_255_A_COLOR_PALETTE_B_RANGE 23:16 +#define DC_WINC_A_COLOR_PALETTE_255_A_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_WINC_A_COLOR_PALETTE_255_A_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_255_A_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_255_A_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_COLOR_PALETTE_255_A_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_WINC_A_PALETTE_COLOR_EXT_0 +#define DC_WINC_A_PALETTE_COLOR_EXT_0 _MK_ADDR_CONST(0x600) +#define DC_WINC_A_PALETTE_COLOR_EXT_0_SECURE 0x0 +#define DC_WINC_A_PALETTE_COLOR_EXT_0_WORD_COUNT 0x1 +#define DC_WINC_A_PALETTE_COLOR_EXT_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_PALETTE_COLOR_EXT_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_PALETTE_COLOR_EXT_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_PALETTE_COLOR_EXT_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_PALETTE_COLOR_EXT_0_READ_MASK _MK_MASK_CONST(0xfe) +#define DC_WINC_A_PALETTE_COLOR_EXT_0_WRITE_MASK _MK_MASK_CONST(0xfe) +#define DC_WINC_A_PALETTE_COLOR_EXT_0_A_PALETTE_COLOR_EXT_SHIFT _MK_SHIFT_CONST(1) +#define DC_WINC_A_PALETTE_COLOR_EXT_0_A_PALETTE_COLOR_EXT_FIELD _MK_FIELD_CONST(0x7f, DC_WINC_A_PALETTE_COLOR_EXT_0_A_PALETTE_COLOR_EXT_SHIFT) +#define DC_WINC_A_PALETTE_COLOR_EXT_0_A_PALETTE_COLOR_EXT_RANGE 7:1 +#define DC_WINC_A_PALETTE_COLOR_EXT_0_A_PALETTE_COLOR_EXT_WOFFSET 0x0 +#define DC_WINC_A_PALETTE_COLOR_EXT_0_A_PALETTE_COLOR_EXT_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_PALETTE_COLOR_EXT_0_A_PALETTE_COLOR_EXT_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_PALETTE_COLOR_EXT_0_A_PALETTE_COLOR_EXT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_PALETTE_COLOR_EXT_0_A_PALETTE_COLOR_EXT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_WINC_A_H_FILTER_P00_0 +#define DC_WINC_A_H_FILTER_P00_0 _MK_ADDR_CONST(0x601) +#define DC_WINC_A_H_FILTER_P00_0_SECURE 0x0 +#define DC_WINC_A_H_FILTER_P00_0_WORD_COUNT 0x1 +#define DC_WINC_A_H_FILTER_P00_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P00_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P00_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P00_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P00_0_READ_MASK _MK_MASK_CONST(0xffffffff) +#define DC_WINC_A_H_FILTER_P00_0_WRITE_MASK _MK_MASK_CONST(0xffffffff) +#define DC_WINC_A_H_FILTER_P00_0_A_H_FILTER_P00C0_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_H_FILTER_P00_0_A_H_FILTER_P00C0_FIELD _MK_FIELD_CONST(0x7, DC_WINC_A_H_FILTER_P00_0_A_H_FILTER_P00C0_SHIFT) +#define DC_WINC_A_H_FILTER_P00_0_A_H_FILTER_P00C0_RANGE 2:0 +#define DC_WINC_A_H_FILTER_P00_0_A_H_FILTER_P00C0_WOFFSET 0x0 +#define DC_WINC_A_H_FILTER_P00_0_A_H_FILTER_P00C0_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P00_0_A_H_FILTER_P00C0_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P00_0_A_H_FILTER_P00C0_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P00_0_A_H_FILTER_P00C0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_H_FILTER_P00_0_A_H_FILTER_P00C1_SHIFT _MK_SHIFT_CONST(3) +#define DC_WINC_A_H_FILTER_P00_0_A_H_FILTER_P00C1_FIELD _MK_FIELD_CONST(0x1f, DC_WINC_A_H_FILTER_P00_0_A_H_FILTER_P00C1_SHIFT) +#define DC_WINC_A_H_FILTER_P00_0_A_H_FILTER_P00C1_RANGE 7:3 +#define DC_WINC_A_H_FILTER_P00_0_A_H_FILTER_P00C1_WOFFSET 0x0 +#define DC_WINC_A_H_FILTER_P00_0_A_H_FILTER_P00C1_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P00_0_A_H_FILTER_P00C1_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P00_0_A_H_FILTER_P00C1_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P00_0_A_H_FILTER_P00C1_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_H_FILTER_P00_0_A_H_FILTER_P00C2_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_H_FILTER_P00_0_A_H_FILTER_P00C2_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_H_FILTER_P00_0_A_H_FILTER_P00C2_SHIFT) +#define DC_WINC_A_H_FILTER_P00_0_A_H_FILTER_P00C2_RANGE 15:8 +#define DC_WINC_A_H_FILTER_P00_0_A_H_FILTER_P00C2_WOFFSET 0x0 +#define DC_WINC_A_H_FILTER_P00_0_A_H_FILTER_P00C2_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P00_0_A_H_FILTER_P00C2_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P00_0_A_H_FILTER_P00C2_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P00_0_A_H_FILTER_P00C2_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_H_FILTER_P00_0_A_H_FILTER_P00C3_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_H_FILTER_P00_0_A_H_FILTER_P00C3_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_H_FILTER_P00_0_A_H_FILTER_P00C3_SHIFT) +#define DC_WINC_A_H_FILTER_P00_0_A_H_FILTER_P00C3_RANGE 23:16 +#define DC_WINC_A_H_FILTER_P00_0_A_H_FILTER_P00C3_WOFFSET 0x0 +#define DC_WINC_A_H_FILTER_P00_0_A_H_FILTER_P00C3_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P00_0_A_H_FILTER_P00C3_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P00_0_A_H_FILTER_P00C3_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P00_0_A_H_FILTER_P00C3_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_H_FILTER_P00_0_A_H_FILTER_P00C4_SHIFT _MK_SHIFT_CONST(24) +#define DC_WINC_A_H_FILTER_P00_0_A_H_FILTER_P00C4_FIELD _MK_FIELD_CONST(0x1f, DC_WINC_A_H_FILTER_P00_0_A_H_FILTER_P00C4_SHIFT) +#define DC_WINC_A_H_FILTER_P00_0_A_H_FILTER_P00C4_RANGE 28:24 +#define DC_WINC_A_H_FILTER_P00_0_A_H_FILTER_P00C4_WOFFSET 0x0 +#define DC_WINC_A_H_FILTER_P00_0_A_H_FILTER_P00C4_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P00_0_A_H_FILTER_P00C4_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P00_0_A_H_FILTER_P00C4_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P00_0_A_H_FILTER_P00C4_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_H_FILTER_P00_0_A_H_FILTER_P00C5_SHIFT _MK_SHIFT_CONST(29) +#define DC_WINC_A_H_FILTER_P00_0_A_H_FILTER_P00C5_FIELD _MK_FIELD_CONST(0x7, DC_WINC_A_H_FILTER_P00_0_A_H_FILTER_P00C5_SHIFT) +#define DC_WINC_A_H_FILTER_P00_0_A_H_FILTER_P00C5_RANGE 31:29 +#define DC_WINC_A_H_FILTER_P00_0_A_H_FILTER_P00C5_WOFFSET 0x0 +#define DC_WINC_A_H_FILTER_P00_0_A_H_FILTER_P00C5_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P00_0_A_H_FILTER_P00C5_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P00_0_A_H_FILTER_P00C5_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P00_0_A_H_FILTER_P00C5_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_WINC_A_H_FILTER_P01_0 +#define DC_WINC_A_H_FILTER_P01_0 _MK_ADDR_CONST(0x602) +#define DC_WINC_A_H_FILTER_P01_0_SECURE 0x0 +#define DC_WINC_A_H_FILTER_P01_0_WORD_COUNT 0x1 +#define DC_WINC_A_H_FILTER_P01_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P01_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P01_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P01_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P01_0_READ_MASK _MK_MASK_CONST(0xffffffff) +#define DC_WINC_A_H_FILTER_P01_0_WRITE_MASK _MK_MASK_CONST(0xffffffff) +#define DC_WINC_A_H_FILTER_P01_0_A_H_FILTER_P01C0_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_H_FILTER_P01_0_A_H_FILTER_P01C0_FIELD _MK_FIELD_CONST(0x7, DC_WINC_A_H_FILTER_P01_0_A_H_FILTER_P01C0_SHIFT) +#define DC_WINC_A_H_FILTER_P01_0_A_H_FILTER_P01C0_RANGE 2:0 +#define DC_WINC_A_H_FILTER_P01_0_A_H_FILTER_P01C0_WOFFSET 0x0 +#define DC_WINC_A_H_FILTER_P01_0_A_H_FILTER_P01C0_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P01_0_A_H_FILTER_P01C0_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P01_0_A_H_FILTER_P01C0_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P01_0_A_H_FILTER_P01C0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_H_FILTER_P01_0_A_H_FILTER_P01C1_SHIFT _MK_SHIFT_CONST(3) +#define DC_WINC_A_H_FILTER_P01_0_A_H_FILTER_P01C1_FIELD _MK_FIELD_CONST(0x1f, DC_WINC_A_H_FILTER_P01_0_A_H_FILTER_P01C1_SHIFT) +#define DC_WINC_A_H_FILTER_P01_0_A_H_FILTER_P01C1_RANGE 7:3 +#define DC_WINC_A_H_FILTER_P01_0_A_H_FILTER_P01C1_WOFFSET 0x0 +#define DC_WINC_A_H_FILTER_P01_0_A_H_FILTER_P01C1_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P01_0_A_H_FILTER_P01C1_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P01_0_A_H_FILTER_P01C1_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P01_0_A_H_FILTER_P01C1_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_H_FILTER_P01_0_A_H_FILTER_P01C2_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_H_FILTER_P01_0_A_H_FILTER_P01C2_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_H_FILTER_P01_0_A_H_FILTER_P01C2_SHIFT) +#define DC_WINC_A_H_FILTER_P01_0_A_H_FILTER_P01C2_RANGE 15:8 +#define DC_WINC_A_H_FILTER_P01_0_A_H_FILTER_P01C2_WOFFSET 0x0 +#define DC_WINC_A_H_FILTER_P01_0_A_H_FILTER_P01C2_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P01_0_A_H_FILTER_P01C2_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P01_0_A_H_FILTER_P01C2_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P01_0_A_H_FILTER_P01C2_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_H_FILTER_P01_0_A_H_FILTER_P01C3_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_H_FILTER_P01_0_A_H_FILTER_P01C3_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_H_FILTER_P01_0_A_H_FILTER_P01C3_SHIFT) +#define DC_WINC_A_H_FILTER_P01_0_A_H_FILTER_P01C3_RANGE 23:16 +#define DC_WINC_A_H_FILTER_P01_0_A_H_FILTER_P01C3_WOFFSET 0x0 +#define DC_WINC_A_H_FILTER_P01_0_A_H_FILTER_P01C3_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P01_0_A_H_FILTER_P01C3_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P01_0_A_H_FILTER_P01C3_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P01_0_A_H_FILTER_P01C3_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_H_FILTER_P01_0_A_H_FILTER_P01C4_SHIFT _MK_SHIFT_CONST(24) +#define DC_WINC_A_H_FILTER_P01_0_A_H_FILTER_P01C4_FIELD _MK_FIELD_CONST(0x1f, DC_WINC_A_H_FILTER_P01_0_A_H_FILTER_P01C4_SHIFT) +#define DC_WINC_A_H_FILTER_P01_0_A_H_FILTER_P01C4_RANGE 28:24 +#define DC_WINC_A_H_FILTER_P01_0_A_H_FILTER_P01C4_WOFFSET 0x0 +#define DC_WINC_A_H_FILTER_P01_0_A_H_FILTER_P01C4_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P01_0_A_H_FILTER_P01C4_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P01_0_A_H_FILTER_P01C4_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P01_0_A_H_FILTER_P01C4_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_H_FILTER_P01_0_A_H_FILTER_P01C5_SHIFT _MK_SHIFT_CONST(29) +#define DC_WINC_A_H_FILTER_P01_0_A_H_FILTER_P01C5_FIELD _MK_FIELD_CONST(0x7, DC_WINC_A_H_FILTER_P01_0_A_H_FILTER_P01C5_SHIFT) +#define DC_WINC_A_H_FILTER_P01_0_A_H_FILTER_P01C5_RANGE 31:29 +#define DC_WINC_A_H_FILTER_P01_0_A_H_FILTER_P01C5_WOFFSET 0x0 +#define DC_WINC_A_H_FILTER_P01_0_A_H_FILTER_P01C5_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P01_0_A_H_FILTER_P01C5_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P01_0_A_H_FILTER_P01C5_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P01_0_A_H_FILTER_P01C5_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_WINC_A_H_FILTER_P02_0 +#define DC_WINC_A_H_FILTER_P02_0 _MK_ADDR_CONST(0x603) +#define DC_WINC_A_H_FILTER_P02_0_SECURE 0x0 +#define DC_WINC_A_H_FILTER_P02_0_WORD_COUNT 0x1 +#define DC_WINC_A_H_FILTER_P02_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P02_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P02_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P02_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P02_0_READ_MASK _MK_MASK_CONST(0xffffffff) +#define DC_WINC_A_H_FILTER_P02_0_WRITE_MASK _MK_MASK_CONST(0xffffffff) +#define DC_WINC_A_H_FILTER_P02_0_A_H_FILTER_P02C0_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_H_FILTER_P02_0_A_H_FILTER_P02C0_FIELD _MK_FIELD_CONST(0x7, DC_WINC_A_H_FILTER_P02_0_A_H_FILTER_P02C0_SHIFT) +#define DC_WINC_A_H_FILTER_P02_0_A_H_FILTER_P02C0_RANGE 2:0 +#define DC_WINC_A_H_FILTER_P02_0_A_H_FILTER_P02C0_WOFFSET 0x0 +#define DC_WINC_A_H_FILTER_P02_0_A_H_FILTER_P02C0_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P02_0_A_H_FILTER_P02C0_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P02_0_A_H_FILTER_P02C0_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P02_0_A_H_FILTER_P02C0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_H_FILTER_P02_0_A_H_FILTER_P02C1_SHIFT _MK_SHIFT_CONST(3) +#define DC_WINC_A_H_FILTER_P02_0_A_H_FILTER_P02C1_FIELD _MK_FIELD_CONST(0x1f, DC_WINC_A_H_FILTER_P02_0_A_H_FILTER_P02C1_SHIFT) +#define DC_WINC_A_H_FILTER_P02_0_A_H_FILTER_P02C1_RANGE 7:3 +#define DC_WINC_A_H_FILTER_P02_0_A_H_FILTER_P02C1_WOFFSET 0x0 +#define DC_WINC_A_H_FILTER_P02_0_A_H_FILTER_P02C1_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P02_0_A_H_FILTER_P02C1_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P02_0_A_H_FILTER_P02C1_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P02_0_A_H_FILTER_P02C1_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_H_FILTER_P02_0_A_H_FILTER_P02C2_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_H_FILTER_P02_0_A_H_FILTER_P02C2_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_H_FILTER_P02_0_A_H_FILTER_P02C2_SHIFT) +#define DC_WINC_A_H_FILTER_P02_0_A_H_FILTER_P02C2_RANGE 15:8 +#define DC_WINC_A_H_FILTER_P02_0_A_H_FILTER_P02C2_WOFFSET 0x0 +#define DC_WINC_A_H_FILTER_P02_0_A_H_FILTER_P02C2_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P02_0_A_H_FILTER_P02C2_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P02_0_A_H_FILTER_P02C2_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P02_0_A_H_FILTER_P02C2_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_H_FILTER_P02_0_A_H_FILTER_P02C3_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_H_FILTER_P02_0_A_H_FILTER_P02C3_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_H_FILTER_P02_0_A_H_FILTER_P02C3_SHIFT) +#define DC_WINC_A_H_FILTER_P02_0_A_H_FILTER_P02C3_RANGE 23:16 +#define DC_WINC_A_H_FILTER_P02_0_A_H_FILTER_P02C3_WOFFSET 0x0 +#define DC_WINC_A_H_FILTER_P02_0_A_H_FILTER_P02C3_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P02_0_A_H_FILTER_P02C3_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P02_0_A_H_FILTER_P02C3_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P02_0_A_H_FILTER_P02C3_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_H_FILTER_P02_0_A_H_FILTER_P02C4_SHIFT _MK_SHIFT_CONST(24) +#define DC_WINC_A_H_FILTER_P02_0_A_H_FILTER_P02C4_FIELD _MK_FIELD_CONST(0x1f, DC_WINC_A_H_FILTER_P02_0_A_H_FILTER_P02C4_SHIFT) +#define DC_WINC_A_H_FILTER_P02_0_A_H_FILTER_P02C4_RANGE 28:24 +#define DC_WINC_A_H_FILTER_P02_0_A_H_FILTER_P02C4_WOFFSET 0x0 +#define DC_WINC_A_H_FILTER_P02_0_A_H_FILTER_P02C4_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P02_0_A_H_FILTER_P02C4_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P02_0_A_H_FILTER_P02C4_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P02_0_A_H_FILTER_P02C4_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_H_FILTER_P02_0_A_H_FILTER_P02C5_SHIFT _MK_SHIFT_CONST(29) +#define DC_WINC_A_H_FILTER_P02_0_A_H_FILTER_P02C5_FIELD _MK_FIELD_CONST(0x7, DC_WINC_A_H_FILTER_P02_0_A_H_FILTER_P02C5_SHIFT) +#define DC_WINC_A_H_FILTER_P02_0_A_H_FILTER_P02C5_RANGE 31:29 +#define DC_WINC_A_H_FILTER_P02_0_A_H_FILTER_P02C5_WOFFSET 0x0 +#define DC_WINC_A_H_FILTER_P02_0_A_H_FILTER_P02C5_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P02_0_A_H_FILTER_P02C5_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P02_0_A_H_FILTER_P02C5_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P02_0_A_H_FILTER_P02C5_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_WINC_A_H_FILTER_P03_0 +#define DC_WINC_A_H_FILTER_P03_0 _MK_ADDR_CONST(0x604) +#define DC_WINC_A_H_FILTER_P03_0_SECURE 0x0 +#define DC_WINC_A_H_FILTER_P03_0_WORD_COUNT 0x1 +#define DC_WINC_A_H_FILTER_P03_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P03_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P03_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P03_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P03_0_READ_MASK _MK_MASK_CONST(0xffffffff) +#define DC_WINC_A_H_FILTER_P03_0_WRITE_MASK _MK_MASK_CONST(0xffffffff) +#define DC_WINC_A_H_FILTER_P03_0_A_H_FILTER_P03C0_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_H_FILTER_P03_0_A_H_FILTER_P03C0_FIELD _MK_FIELD_CONST(0x7, DC_WINC_A_H_FILTER_P03_0_A_H_FILTER_P03C0_SHIFT) +#define DC_WINC_A_H_FILTER_P03_0_A_H_FILTER_P03C0_RANGE 2:0 +#define DC_WINC_A_H_FILTER_P03_0_A_H_FILTER_P03C0_WOFFSET 0x0 +#define DC_WINC_A_H_FILTER_P03_0_A_H_FILTER_P03C0_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P03_0_A_H_FILTER_P03C0_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P03_0_A_H_FILTER_P03C0_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P03_0_A_H_FILTER_P03C0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_H_FILTER_P03_0_A_H_FILTER_P03C1_SHIFT _MK_SHIFT_CONST(3) +#define DC_WINC_A_H_FILTER_P03_0_A_H_FILTER_P03C1_FIELD _MK_FIELD_CONST(0x1f, DC_WINC_A_H_FILTER_P03_0_A_H_FILTER_P03C1_SHIFT) +#define DC_WINC_A_H_FILTER_P03_0_A_H_FILTER_P03C1_RANGE 7:3 +#define DC_WINC_A_H_FILTER_P03_0_A_H_FILTER_P03C1_WOFFSET 0x0 +#define DC_WINC_A_H_FILTER_P03_0_A_H_FILTER_P03C1_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P03_0_A_H_FILTER_P03C1_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P03_0_A_H_FILTER_P03C1_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P03_0_A_H_FILTER_P03C1_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_H_FILTER_P03_0_A_H_FILTER_P03C2_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_H_FILTER_P03_0_A_H_FILTER_P03C2_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_H_FILTER_P03_0_A_H_FILTER_P03C2_SHIFT) +#define DC_WINC_A_H_FILTER_P03_0_A_H_FILTER_P03C2_RANGE 15:8 +#define DC_WINC_A_H_FILTER_P03_0_A_H_FILTER_P03C2_WOFFSET 0x0 +#define DC_WINC_A_H_FILTER_P03_0_A_H_FILTER_P03C2_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P03_0_A_H_FILTER_P03C2_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P03_0_A_H_FILTER_P03C2_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P03_0_A_H_FILTER_P03C2_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_H_FILTER_P03_0_A_H_FILTER_P03C3_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_H_FILTER_P03_0_A_H_FILTER_P03C3_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_H_FILTER_P03_0_A_H_FILTER_P03C3_SHIFT) +#define DC_WINC_A_H_FILTER_P03_0_A_H_FILTER_P03C3_RANGE 23:16 +#define DC_WINC_A_H_FILTER_P03_0_A_H_FILTER_P03C3_WOFFSET 0x0 +#define DC_WINC_A_H_FILTER_P03_0_A_H_FILTER_P03C3_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P03_0_A_H_FILTER_P03C3_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P03_0_A_H_FILTER_P03C3_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P03_0_A_H_FILTER_P03C3_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_H_FILTER_P03_0_A_H_FILTER_P03C4_SHIFT _MK_SHIFT_CONST(24) +#define DC_WINC_A_H_FILTER_P03_0_A_H_FILTER_P03C4_FIELD _MK_FIELD_CONST(0x1f, DC_WINC_A_H_FILTER_P03_0_A_H_FILTER_P03C4_SHIFT) +#define DC_WINC_A_H_FILTER_P03_0_A_H_FILTER_P03C4_RANGE 28:24 +#define DC_WINC_A_H_FILTER_P03_0_A_H_FILTER_P03C4_WOFFSET 0x0 +#define DC_WINC_A_H_FILTER_P03_0_A_H_FILTER_P03C4_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P03_0_A_H_FILTER_P03C4_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P03_0_A_H_FILTER_P03C4_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P03_0_A_H_FILTER_P03C4_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_H_FILTER_P03_0_A_H_FILTER_P03C5_SHIFT _MK_SHIFT_CONST(29) +#define DC_WINC_A_H_FILTER_P03_0_A_H_FILTER_P03C5_FIELD _MK_FIELD_CONST(0x7, DC_WINC_A_H_FILTER_P03_0_A_H_FILTER_P03C5_SHIFT) +#define DC_WINC_A_H_FILTER_P03_0_A_H_FILTER_P03C5_RANGE 31:29 +#define DC_WINC_A_H_FILTER_P03_0_A_H_FILTER_P03C5_WOFFSET 0x0 +#define DC_WINC_A_H_FILTER_P03_0_A_H_FILTER_P03C5_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P03_0_A_H_FILTER_P03C5_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P03_0_A_H_FILTER_P03C5_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P03_0_A_H_FILTER_P03C5_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_WINC_A_H_FILTER_P04_0 +#define DC_WINC_A_H_FILTER_P04_0 _MK_ADDR_CONST(0x605) +#define DC_WINC_A_H_FILTER_P04_0_SECURE 0x0 +#define DC_WINC_A_H_FILTER_P04_0_WORD_COUNT 0x1 +#define DC_WINC_A_H_FILTER_P04_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P04_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P04_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P04_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P04_0_READ_MASK _MK_MASK_CONST(0xffffffff) +#define DC_WINC_A_H_FILTER_P04_0_WRITE_MASK _MK_MASK_CONST(0xffffffff) +#define DC_WINC_A_H_FILTER_P04_0_A_H_FILTER_P04C0_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_H_FILTER_P04_0_A_H_FILTER_P04C0_FIELD _MK_FIELD_CONST(0x7, DC_WINC_A_H_FILTER_P04_0_A_H_FILTER_P04C0_SHIFT) +#define DC_WINC_A_H_FILTER_P04_0_A_H_FILTER_P04C0_RANGE 2:0 +#define DC_WINC_A_H_FILTER_P04_0_A_H_FILTER_P04C0_WOFFSET 0x0 +#define DC_WINC_A_H_FILTER_P04_0_A_H_FILTER_P04C0_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P04_0_A_H_FILTER_P04C0_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P04_0_A_H_FILTER_P04C0_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P04_0_A_H_FILTER_P04C0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_H_FILTER_P04_0_A_H_FILTER_P04C1_SHIFT _MK_SHIFT_CONST(3) +#define DC_WINC_A_H_FILTER_P04_0_A_H_FILTER_P04C1_FIELD _MK_FIELD_CONST(0x1f, DC_WINC_A_H_FILTER_P04_0_A_H_FILTER_P04C1_SHIFT) +#define DC_WINC_A_H_FILTER_P04_0_A_H_FILTER_P04C1_RANGE 7:3 +#define DC_WINC_A_H_FILTER_P04_0_A_H_FILTER_P04C1_WOFFSET 0x0 +#define DC_WINC_A_H_FILTER_P04_0_A_H_FILTER_P04C1_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P04_0_A_H_FILTER_P04C1_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P04_0_A_H_FILTER_P04C1_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P04_0_A_H_FILTER_P04C1_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_H_FILTER_P04_0_A_H_FILTER_P04C2_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_H_FILTER_P04_0_A_H_FILTER_P04C2_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_H_FILTER_P04_0_A_H_FILTER_P04C2_SHIFT) +#define DC_WINC_A_H_FILTER_P04_0_A_H_FILTER_P04C2_RANGE 15:8 +#define DC_WINC_A_H_FILTER_P04_0_A_H_FILTER_P04C2_WOFFSET 0x0 +#define DC_WINC_A_H_FILTER_P04_0_A_H_FILTER_P04C2_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P04_0_A_H_FILTER_P04C2_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P04_0_A_H_FILTER_P04C2_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P04_0_A_H_FILTER_P04C2_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_H_FILTER_P04_0_A_H_FILTER_P04C3_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_H_FILTER_P04_0_A_H_FILTER_P04C3_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_H_FILTER_P04_0_A_H_FILTER_P04C3_SHIFT) +#define DC_WINC_A_H_FILTER_P04_0_A_H_FILTER_P04C3_RANGE 23:16 +#define DC_WINC_A_H_FILTER_P04_0_A_H_FILTER_P04C3_WOFFSET 0x0 +#define DC_WINC_A_H_FILTER_P04_0_A_H_FILTER_P04C3_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P04_0_A_H_FILTER_P04C3_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P04_0_A_H_FILTER_P04C3_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P04_0_A_H_FILTER_P04C3_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_H_FILTER_P04_0_A_H_FILTER_P04C4_SHIFT _MK_SHIFT_CONST(24) +#define DC_WINC_A_H_FILTER_P04_0_A_H_FILTER_P04C4_FIELD _MK_FIELD_CONST(0x1f, DC_WINC_A_H_FILTER_P04_0_A_H_FILTER_P04C4_SHIFT) +#define DC_WINC_A_H_FILTER_P04_0_A_H_FILTER_P04C4_RANGE 28:24 +#define DC_WINC_A_H_FILTER_P04_0_A_H_FILTER_P04C4_WOFFSET 0x0 +#define DC_WINC_A_H_FILTER_P04_0_A_H_FILTER_P04C4_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P04_0_A_H_FILTER_P04C4_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P04_0_A_H_FILTER_P04C4_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P04_0_A_H_FILTER_P04C4_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_H_FILTER_P04_0_A_H_FILTER_P04C5_SHIFT _MK_SHIFT_CONST(29) +#define DC_WINC_A_H_FILTER_P04_0_A_H_FILTER_P04C5_FIELD _MK_FIELD_CONST(0x7, DC_WINC_A_H_FILTER_P04_0_A_H_FILTER_P04C5_SHIFT) +#define DC_WINC_A_H_FILTER_P04_0_A_H_FILTER_P04C5_RANGE 31:29 +#define DC_WINC_A_H_FILTER_P04_0_A_H_FILTER_P04C5_WOFFSET 0x0 +#define DC_WINC_A_H_FILTER_P04_0_A_H_FILTER_P04C5_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P04_0_A_H_FILTER_P04C5_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P04_0_A_H_FILTER_P04C5_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P04_0_A_H_FILTER_P04C5_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_WINC_A_H_FILTER_P05_0 +#define DC_WINC_A_H_FILTER_P05_0 _MK_ADDR_CONST(0x606) +#define DC_WINC_A_H_FILTER_P05_0_SECURE 0x0 +#define DC_WINC_A_H_FILTER_P05_0_WORD_COUNT 0x1 +#define DC_WINC_A_H_FILTER_P05_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P05_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P05_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P05_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P05_0_READ_MASK _MK_MASK_CONST(0xffffffff) +#define DC_WINC_A_H_FILTER_P05_0_WRITE_MASK _MK_MASK_CONST(0xffffffff) +#define DC_WINC_A_H_FILTER_P05_0_A_H_FILTER_P05C0_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_H_FILTER_P05_0_A_H_FILTER_P05C0_FIELD _MK_FIELD_CONST(0x7, DC_WINC_A_H_FILTER_P05_0_A_H_FILTER_P05C0_SHIFT) +#define DC_WINC_A_H_FILTER_P05_0_A_H_FILTER_P05C0_RANGE 2:0 +#define DC_WINC_A_H_FILTER_P05_0_A_H_FILTER_P05C0_WOFFSET 0x0 +#define DC_WINC_A_H_FILTER_P05_0_A_H_FILTER_P05C0_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P05_0_A_H_FILTER_P05C0_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P05_0_A_H_FILTER_P05C0_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P05_0_A_H_FILTER_P05C0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_H_FILTER_P05_0_A_H_FILTER_P05C1_SHIFT _MK_SHIFT_CONST(3) +#define DC_WINC_A_H_FILTER_P05_0_A_H_FILTER_P05C1_FIELD _MK_FIELD_CONST(0x1f, DC_WINC_A_H_FILTER_P05_0_A_H_FILTER_P05C1_SHIFT) +#define DC_WINC_A_H_FILTER_P05_0_A_H_FILTER_P05C1_RANGE 7:3 +#define DC_WINC_A_H_FILTER_P05_0_A_H_FILTER_P05C1_WOFFSET 0x0 +#define DC_WINC_A_H_FILTER_P05_0_A_H_FILTER_P05C1_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P05_0_A_H_FILTER_P05C1_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P05_0_A_H_FILTER_P05C1_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P05_0_A_H_FILTER_P05C1_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_H_FILTER_P05_0_A_H_FILTER_P05C2_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_H_FILTER_P05_0_A_H_FILTER_P05C2_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_H_FILTER_P05_0_A_H_FILTER_P05C2_SHIFT) +#define DC_WINC_A_H_FILTER_P05_0_A_H_FILTER_P05C2_RANGE 15:8 +#define DC_WINC_A_H_FILTER_P05_0_A_H_FILTER_P05C2_WOFFSET 0x0 +#define DC_WINC_A_H_FILTER_P05_0_A_H_FILTER_P05C2_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P05_0_A_H_FILTER_P05C2_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P05_0_A_H_FILTER_P05C2_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P05_0_A_H_FILTER_P05C2_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_H_FILTER_P05_0_A_H_FILTER_P05C3_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_H_FILTER_P05_0_A_H_FILTER_P05C3_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_H_FILTER_P05_0_A_H_FILTER_P05C3_SHIFT) +#define DC_WINC_A_H_FILTER_P05_0_A_H_FILTER_P05C3_RANGE 23:16 +#define DC_WINC_A_H_FILTER_P05_0_A_H_FILTER_P05C3_WOFFSET 0x0 +#define DC_WINC_A_H_FILTER_P05_0_A_H_FILTER_P05C3_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P05_0_A_H_FILTER_P05C3_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P05_0_A_H_FILTER_P05C3_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P05_0_A_H_FILTER_P05C3_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_H_FILTER_P05_0_A_H_FILTER_P05C4_SHIFT _MK_SHIFT_CONST(24) +#define DC_WINC_A_H_FILTER_P05_0_A_H_FILTER_P05C4_FIELD _MK_FIELD_CONST(0x1f, DC_WINC_A_H_FILTER_P05_0_A_H_FILTER_P05C4_SHIFT) +#define DC_WINC_A_H_FILTER_P05_0_A_H_FILTER_P05C4_RANGE 28:24 +#define DC_WINC_A_H_FILTER_P05_0_A_H_FILTER_P05C4_WOFFSET 0x0 +#define DC_WINC_A_H_FILTER_P05_0_A_H_FILTER_P05C4_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P05_0_A_H_FILTER_P05C4_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P05_0_A_H_FILTER_P05C4_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P05_0_A_H_FILTER_P05C4_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_H_FILTER_P05_0_A_H_FILTER_P05C5_SHIFT _MK_SHIFT_CONST(29) +#define DC_WINC_A_H_FILTER_P05_0_A_H_FILTER_P05C5_FIELD _MK_FIELD_CONST(0x7, DC_WINC_A_H_FILTER_P05_0_A_H_FILTER_P05C5_SHIFT) +#define DC_WINC_A_H_FILTER_P05_0_A_H_FILTER_P05C5_RANGE 31:29 +#define DC_WINC_A_H_FILTER_P05_0_A_H_FILTER_P05C5_WOFFSET 0x0 +#define DC_WINC_A_H_FILTER_P05_0_A_H_FILTER_P05C5_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P05_0_A_H_FILTER_P05C5_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P05_0_A_H_FILTER_P05C5_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P05_0_A_H_FILTER_P05C5_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_WINC_A_H_FILTER_P06_0 +#define DC_WINC_A_H_FILTER_P06_0 _MK_ADDR_CONST(0x607) +#define DC_WINC_A_H_FILTER_P06_0_SECURE 0x0 +#define DC_WINC_A_H_FILTER_P06_0_WORD_COUNT 0x1 +#define DC_WINC_A_H_FILTER_P06_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P06_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P06_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P06_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P06_0_READ_MASK _MK_MASK_CONST(0xffffffff) +#define DC_WINC_A_H_FILTER_P06_0_WRITE_MASK _MK_MASK_CONST(0xffffffff) +#define DC_WINC_A_H_FILTER_P06_0_A_H_FILTER_P06C0_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_H_FILTER_P06_0_A_H_FILTER_P06C0_FIELD _MK_FIELD_CONST(0x7, DC_WINC_A_H_FILTER_P06_0_A_H_FILTER_P06C0_SHIFT) +#define DC_WINC_A_H_FILTER_P06_0_A_H_FILTER_P06C0_RANGE 2:0 +#define DC_WINC_A_H_FILTER_P06_0_A_H_FILTER_P06C0_WOFFSET 0x0 +#define DC_WINC_A_H_FILTER_P06_0_A_H_FILTER_P06C0_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P06_0_A_H_FILTER_P06C0_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P06_0_A_H_FILTER_P06C0_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P06_0_A_H_FILTER_P06C0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_H_FILTER_P06_0_A_H_FILTER_P06C1_SHIFT _MK_SHIFT_CONST(3) +#define DC_WINC_A_H_FILTER_P06_0_A_H_FILTER_P06C1_FIELD _MK_FIELD_CONST(0x1f, DC_WINC_A_H_FILTER_P06_0_A_H_FILTER_P06C1_SHIFT) +#define DC_WINC_A_H_FILTER_P06_0_A_H_FILTER_P06C1_RANGE 7:3 +#define DC_WINC_A_H_FILTER_P06_0_A_H_FILTER_P06C1_WOFFSET 0x0 +#define DC_WINC_A_H_FILTER_P06_0_A_H_FILTER_P06C1_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P06_0_A_H_FILTER_P06C1_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P06_0_A_H_FILTER_P06C1_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P06_0_A_H_FILTER_P06C1_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_H_FILTER_P06_0_A_H_FILTER_P06C2_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_H_FILTER_P06_0_A_H_FILTER_P06C2_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_H_FILTER_P06_0_A_H_FILTER_P06C2_SHIFT) +#define DC_WINC_A_H_FILTER_P06_0_A_H_FILTER_P06C2_RANGE 15:8 +#define DC_WINC_A_H_FILTER_P06_0_A_H_FILTER_P06C2_WOFFSET 0x0 +#define DC_WINC_A_H_FILTER_P06_0_A_H_FILTER_P06C2_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P06_0_A_H_FILTER_P06C2_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P06_0_A_H_FILTER_P06C2_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P06_0_A_H_FILTER_P06C2_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_H_FILTER_P06_0_A_H_FILTER_P06C3_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_H_FILTER_P06_0_A_H_FILTER_P06C3_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_H_FILTER_P06_0_A_H_FILTER_P06C3_SHIFT) +#define DC_WINC_A_H_FILTER_P06_0_A_H_FILTER_P06C3_RANGE 23:16 +#define DC_WINC_A_H_FILTER_P06_0_A_H_FILTER_P06C3_WOFFSET 0x0 +#define DC_WINC_A_H_FILTER_P06_0_A_H_FILTER_P06C3_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P06_0_A_H_FILTER_P06C3_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P06_0_A_H_FILTER_P06C3_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P06_0_A_H_FILTER_P06C3_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_H_FILTER_P06_0_A_H_FILTER_P06C4_SHIFT _MK_SHIFT_CONST(24) +#define DC_WINC_A_H_FILTER_P06_0_A_H_FILTER_P06C4_FIELD _MK_FIELD_CONST(0x1f, DC_WINC_A_H_FILTER_P06_0_A_H_FILTER_P06C4_SHIFT) +#define DC_WINC_A_H_FILTER_P06_0_A_H_FILTER_P06C4_RANGE 28:24 +#define DC_WINC_A_H_FILTER_P06_0_A_H_FILTER_P06C4_WOFFSET 0x0 +#define DC_WINC_A_H_FILTER_P06_0_A_H_FILTER_P06C4_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P06_0_A_H_FILTER_P06C4_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P06_0_A_H_FILTER_P06C4_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P06_0_A_H_FILTER_P06C4_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_H_FILTER_P06_0_A_H_FILTER_P06C5_SHIFT _MK_SHIFT_CONST(29) +#define DC_WINC_A_H_FILTER_P06_0_A_H_FILTER_P06C5_FIELD _MK_FIELD_CONST(0x7, DC_WINC_A_H_FILTER_P06_0_A_H_FILTER_P06C5_SHIFT) +#define DC_WINC_A_H_FILTER_P06_0_A_H_FILTER_P06C5_RANGE 31:29 +#define DC_WINC_A_H_FILTER_P06_0_A_H_FILTER_P06C5_WOFFSET 0x0 +#define DC_WINC_A_H_FILTER_P06_0_A_H_FILTER_P06C5_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P06_0_A_H_FILTER_P06C5_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P06_0_A_H_FILTER_P06C5_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P06_0_A_H_FILTER_P06C5_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_WINC_A_H_FILTER_P07_0 +#define DC_WINC_A_H_FILTER_P07_0 _MK_ADDR_CONST(0x608) +#define DC_WINC_A_H_FILTER_P07_0_SECURE 0x0 +#define DC_WINC_A_H_FILTER_P07_0_WORD_COUNT 0x1 +#define DC_WINC_A_H_FILTER_P07_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P07_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P07_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P07_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P07_0_READ_MASK _MK_MASK_CONST(0xffffffff) +#define DC_WINC_A_H_FILTER_P07_0_WRITE_MASK _MK_MASK_CONST(0xffffffff) +#define DC_WINC_A_H_FILTER_P07_0_A_H_FILTER_P07C0_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_H_FILTER_P07_0_A_H_FILTER_P07C0_FIELD _MK_FIELD_CONST(0x7, DC_WINC_A_H_FILTER_P07_0_A_H_FILTER_P07C0_SHIFT) +#define DC_WINC_A_H_FILTER_P07_0_A_H_FILTER_P07C0_RANGE 2:0 +#define DC_WINC_A_H_FILTER_P07_0_A_H_FILTER_P07C0_WOFFSET 0x0 +#define DC_WINC_A_H_FILTER_P07_0_A_H_FILTER_P07C0_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P07_0_A_H_FILTER_P07C0_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P07_0_A_H_FILTER_P07C0_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P07_0_A_H_FILTER_P07C0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_H_FILTER_P07_0_A_H_FILTER_P07C1_SHIFT _MK_SHIFT_CONST(3) +#define DC_WINC_A_H_FILTER_P07_0_A_H_FILTER_P07C1_FIELD _MK_FIELD_CONST(0x1f, DC_WINC_A_H_FILTER_P07_0_A_H_FILTER_P07C1_SHIFT) +#define DC_WINC_A_H_FILTER_P07_0_A_H_FILTER_P07C1_RANGE 7:3 +#define DC_WINC_A_H_FILTER_P07_0_A_H_FILTER_P07C1_WOFFSET 0x0 +#define DC_WINC_A_H_FILTER_P07_0_A_H_FILTER_P07C1_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P07_0_A_H_FILTER_P07C1_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P07_0_A_H_FILTER_P07C1_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P07_0_A_H_FILTER_P07C1_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_H_FILTER_P07_0_A_H_FILTER_P07C2_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_H_FILTER_P07_0_A_H_FILTER_P07C2_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_H_FILTER_P07_0_A_H_FILTER_P07C2_SHIFT) +#define DC_WINC_A_H_FILTER_P07_0_A_H_FILTER_P07C2_RANGE 15:8 +#define DC_WINC_A_H_FILTER_P07_0_A_H_FILTER_P07C2_WOFFSET 0x0 +#define DC_WINC_A_H_FILTER_P07_0_A_H_FILTER_P07C2_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P07_0_A_H_FILTER_P07C2_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P07_0_A_H_FILTER_P07C2_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P07_0_A_H_FILTER_P07C2_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_H_FILTER_P07_0_A_H_FILTER_P07C3_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_H_FILTER_P07_0_A_H_FILTER_P07C3_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_H_FILTER_P07_0_A_H_FILTER_P07C3_SHIFT) +#define DC_WINC_A_H_FILTER_P07_0_A_H_FILTER_P07C3_RANGE 23:16 +#define DC_WINC_A_H_FILTER_P07_0_A_H_FILTER_P07C3_WOFFSET 0x0 +#define DC_WINC_A_H_FILTER_P07_0_A_H_FILTER_P07C3_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P07_0_A_H_FILTER_P07C3_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P07_0_A_H_FILTER_P07C3_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P07_0_A_H_FILTER_P07C3_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_H_FILTER_P07_0_A_H_FILTER_P07C4_SHIFT _MK_SHIFT_CONST(24) +#define DC_WINC_A_H_FILTER_P07_0_A_H_FILTER_P07C4_FIELD _MK_FIELD_CONST(0x1f, DC_WINC_A_H_FILTER_P07_0_A_H_FILTER_P07C4_SHIFT) +#define DC_WINC_A_H_FILTER_P07_0_A_H_FILTER_P07C4_RANGE 28:24 +#define DC_WINC_A_H_FILTER_P07_0_A_H_FILTER_P07C4_WOFFSET 0x0 +#define DC_WINC_A_H_FILTER_P07_0_A_H_FILTER_P07C4_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P07_0_A_H_FILTER_P07C4_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P07_0_A_H_FILTER_P07C4_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P07_0_A_H_FILTER_P07C4_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_H_FILTER_P07_0_A_H_FILTER_P07C5_SHIFT _MK_SHIFT_CONST(29) +#define DC_WINC_A_H_FILTER_P07_0_A_H_FILTER_P07C5_FIELD _MK_FIELD_CONST(0x7, DC_WINC_A_H_FILTER_P07_0_A_H_FILTER_P07C5_SHIFT) +#define DC_WINC_A_H_FILTER_P07_0_A_H_FILTER_P07C5_RANGE 31:29 +#define DC_WINC_A_H_FILTER_P07_0_A_H_FILTER_P07C5_WOFFSET 0x0 +#define DC_WINC_A_H_FILTER_P07_0_A_H_FILTER_P07C5_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P07_0_A_H_FILTER_P07C5_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P07_0_A_H_FILTER_P07C5_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P07_0_A_H_FILTER_P07C5_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_WINC_A_H_FILTER_P08_0 +#define DC_WINC_A_H_FILTER_P08_0 _MK_ADDR_CONST(0x609) +#define DC_WINC_A_H_FILTER_P08_0_SECURE 0x0 +#define DC_WINC_A_H_FILTER_P08_0_WORD_COUNT 0x1 +#define DC_WINC_A_H_FILTER_P08_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P08_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P08_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P08_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P08_0_READ_MASK _MK_MASK_CONST(0xffffffff) +#define DC_WINC_A_H_FILTER_P08_0_WRITE_MASK _MK_MASK_CONST(0xffffffff) +#define DC_WINC_A_H_FILTER_P08_0_A_H_FILTER_P08C0_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_H_FILTER_P08_0_A_H_FILTER_P08C0_FIELD _MK_FIELD_CONST(0x7, DC_WINC_A_H_FILTER_P08_0_A_H_FILTER_P08C0_SHIFT) +#define DC_WINC_A_H_FILTER_P08_0_A_H_FILTER_P08C0_RANGE 2:0 +#define DC_WINC_A_H_FILTER_P08_0_A_H_FILTER_P08C0_WOFFSET 0x0 +#define DC_WINC_A_H_FILTER_P08_0_A_H_FILTER_P08C0_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P08_0_A_H_FILTER_P08C0_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P08_0_A_H_FILTER_P08C0_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P08_0_A_H_FILTER_P08C0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_H_FILTER_P08_0_A_H_FILTER_P08C1_SHIFT _MK_SHIFT_CONST(3) +#define DC_WINC_A_H_FILTER_P08_0_A_H_FILTER_P08C1_FIELD _MK_FIELD_CONST(0x1f, DC_WINC_A_H_FILTER_P08_0_A_H_FILTER_P08C1_SHIFT) +#define DC_WINC_A_H_FILTER_P08_0_A_H_FILTER_P08C1_RANGE 7:3 +#define DC_WINC_A_H_FILTER_P08_0_A_H_FILTER_P08C1_WOFFSET 0x0 +#define DC_WINC_A_H_FILTER_P08_0_A_H_FILTER_P08C1_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P08_0_A_H_FILTER_P08C1_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P08_0_A_H_FILTER_P08C1_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P08_0_A_H_FILTER_P08C1_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_H_FILTER_P08_0_A_H_FILTER_P08C2_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_H_FILTER_P08_0_A_H_FILTER_P08C2_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_H_FILTER_P08_0_A_H_FILTER_P08C2_SHIFT) +#define DC_WINC_A_H_FILTER_P08_0_A_H_FILTER_P08C2_RANGE 15:8 +#define DC_WINC_A_H_FILTER_P08_0_A_H_FILTER_P08C2_WOFFSET 0x0 +#define DC_WINC_A_H_FILTER_P08_0_A_H_FILTER_P08C2_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P08_0_A_H_FILTER_P08C2_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P08_0_A_H_FILTER_P08C2_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P08_0_A_H_FILTER_P08C2_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_H_FILTER_P08_0_A_H_FILTER_P08C3_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_H_FILTER_P08_0_A_H_FILTER_P08C3_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_H_FILTER_P08_0_A_H_FILTER_P08C3_SHIFT) +#define DC_WINC_A_H_FILTER_P08_0_A_H_FILTER_P08C3_RANGE 23:16 +#define DC_WINC_A_H_FILTER_P08_0_A_H_FILTER_P08C3_WOFFSET 0x0 +#define DC_WINC_A_H_FILTER_P08_0_A_H_FILTER_P08C3_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P08_0_A_H_FILTER_P08C3_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P08_0_A_H_FILTER_P08C3_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P08_0_A_H_FILTER_P08C3_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_H_FILTER_P08_0_A_H_FILTER_P08C4_SHIFT _MK_SHIFT_CONST(24) +#define DC_WINC_A_H_FILTER_P08_0_A_H_FILTER_P08C4_FIELD _MK_FIELD_CONST(0x1f, DC_WINC_A_H_FILTER_P08_0_A_H_FILTER_P08C4_SHIFT) +#define DC_WINC_A_H_FILTER_P08_0_A_H_FILTER_P08C4_RANGE 28:24 +#define DC_WINC_A_H_FILTER_P08_0_A_H_FILTER_P08C4_WOFFSET 0x0 +#define DC_WINC_A_H_FILTER_P08_0_A_H_FILTER_P08C4_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P08_0_A_H_FILTER_P08C4_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P08_0_A_H_FILTER_P08C4_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P08_0_A_H_FILTER_P08C4_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_H_FILTER_P08_0_A_H_FILTER_P08C5_SHIFT _MK_SHIFT_CONST(29) +#define DC_WINC_A_H_FILTER_P08_0_A_H_FILTER_P08C5_FIELD _MK_FIELD_CONST(0x7, DC_WINC_A_H_FILTER_P08_0_A_H_FILTER_P08C5_SHIFT) +#define DC_WINC_A_H_FILTER_P08_0_A_H_FILTER_P08C5_RANGE 31:29 +#define DC_WINC_A_H_FILTER_P08_0_A_H_FILTER_P08C5_WOFFSET 0x0 +#define DC_WINC_A_H_FILTER_P08_0_A_H_FILTER_P08C5_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P08_0_A_H_FILTER_P08C5_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P08_0_A_H_FILTER_P08C5_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P08_0_A_H_FILTER_P08C5_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_WINC_A_H_FILTER_P09_0 +#define DC_WINC_A_H_FILTER_P09_0 _MK_ADDR_CONST(0x60a) +#define DC_WINC_A_H_FILTER_P09_0_SECURE 0x0 +#define DC_WINC_A_H_FILTER_P09_0_WORD_COUNT 0x1 +#define DC_WINC_A_H_FILTER_P09_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P09_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P09_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P09_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P09_0_READ_MASK _MK_MASK_CONST(0xffffffff) +#define DC_WINC_A_H_FILTER_P09_0_WRITE_MASK _MK_MASK_CONST(0xffffffff) +#define DC_WINC_A_H_FILTER_P09_0_A_H_FILTER_P09C0_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_H_FILTER_P09_0_A_H_FILTER_P09C0_FIELD _MK_FIELD_CONST(0x7, DC_WINC_A_H_FILTER_P09_0_A_H_FILTER_P09C0_SHIFT) +#define DC_WINC_A_H_FILTER_P09_0_A_H_FILTER_P09C0_RANGE 2:0 +#define DC_WINC_A_H_FILTER_P09_0_A_H_FILTER_P09C0_WOFFSET 0x0 +#define DC_WINC_A_H_FILTER_P09_0_A_H_FILTER_P09C0_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P09_0_A_H_FILTER_P09C0_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P09_0_A_H_FILTER_P09C0_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P09_0_A_H_FILTER_P09C0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_H_FILTER_P09_0_A_H_FILTER_P09C1_SHIFT _MK_SHIFT_CONST(3) +#define DC_WINC_A_H_FILTER_P09_0_A_H_FILTER_P09C1_FIELD _MK_FIELD_CONST(0x1f, DC_WINC_A_H_FILTER_P09_0_A_H_FILTER_P09C1_SHIFT) +#define DC_WINC_A_H_FILTER_P09_0_A_H_FILTER_P09C1_RANGE 7:3 +#define DC_WINC_A_H_FILTER_P09_0_A_H_FILTER_P09C1_WOFFSET 0x0 +#define DC_WINC_A_H_FILTER_P09_0_A_H_FILTER_P09C1_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P09_0_A_H_FILTER_P09C1_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P09_0_A_H_FILTER_P09C1_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P09_0_A_H_FILTER_P09C1_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_H_FILTER_P09_0_A_H_FILTER_P09C2_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_H_FILTER_P09_0_A_H_FILTER_P09C2_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_H_FILTER_P09_0_A_H_FILTER_P09C2_SHIFT) +#define DC_WINC_A_H_FILTER_P09_0_A_H_FILTER_P09C2_RANGE 15:8 +#define DC_WINC_A_H_FILTER_P09_0_A_H_FILTER_P09C2_WOFFSET 0x0 +#define DC_WINC_A_H_FILTER_P09_0_A_H_FILTER_P09C2_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P09_0_A_H_FILTER_P09C2_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P09_0_A_H_FILTER_P09C2_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P09_0_A_H_FILTER_P09C2_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_H_FILTER_P09_0_A_H_FILTER_P09C3_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_H_FILTER_P09_0_A_H_FILTER_P09C3_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_H_FILTER_P09_0_A_H_FILTER_P09C3_SHIFT) +#define DC_WINC_A_H_FILTER_P09_0_A_H_FILTER_P09C3_RANGE 23:16 +#define DC_WINC_A_H_FILTER_P09_0_A_H_FILTER_P09C3_WOFFSET 0x0 +#define DC_WINC_A_H_FILTER_P09_0_A_H_FILTER_P09C3_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P09_0_A_H_FILTER_P09C3_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P09_0_A_H_FILTER_P09C3_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P09_0_A_H_FILTER_P09C3_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_H_FILTER_P09_0_A_H_FILTER_P09C4_SHIFT _MK_SHIFT_CONST(24) +#define DC_WINC_A_H_FILTER_P09_0_A_H_FILTER_P09C4_FIELD _MK_FIELD_CONST(0x1f, DC_WINC_A_H_FILTER_P09_0_A_H_FILTER_P09C4_SHIFT) +#define DC_WINC_A_H_FILTER_P09_0_A_H_FILTER_P09C4_RANGE 28:24 +#define DC_WINC_A_H_FILTER_P09_0_A_H_FILTER_P09C4_WOFFSET 0x0 +#define DC_WINC_A_H_FILTER_P09_0_A_H_FILTER_P09C4_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P09_0_A_H_FILTER_P09C4_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P09_0_A_H_FILTER_P09C4_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P09_0_A_H_FILTER_P09C4_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_H_FILTER_P09_0_A_H_FILTER_P09C5_SHIFT _MK_SHIFT_CONST(29) +#define DC_WINC_A_H_FILTER_P09_0_A_H_FILTER_P09C5_FIELD _MK_FIELD_CONST(0x7, DC_WINC_A_H_FILTER_P09_0_A_H_FILTER_P09C5_SHIFT) +#define DC_WINC_A_H_FILTER_P09_0_A_H_FILTER_P09C5_RANGE 31:29 +#define DC_WINC_A_H_FILTER_P09_0_A_H_FILTER_P09C5_WOFFSET 0x0 +#define DC_WINC_A_H_FILTER_P09_0_A_H_FILTER_P09C5_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P09_0_A_H_FILTER_P09C5_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P09_0_A_H_FILTER_P09C5_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P09_0_A_H_FILTER_P09C5_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_WINC_A_H_FILTER_P0A_0 +#define DC_WINC_A_H_FILTER_P0A_0 _MK_ADDR_CONST(0x60b) +#define DC_WINC_A_H_FILTER_P0A_0_SECURE 0x0 +#define DC_WINC_A_H_FILTER_P0A_0_WORD_COUNT 0x1 +#define DC_WINC_A_H_FILTER_P0A_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P0A_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P0A_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P0A_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P0A_0_READ_MASK _MK_MASK_CONST(0xffffffff) +#define DC_WINC_A_H_FILTER_P0A_0_WRITE_MASK _MK_MASK_CONST(0xffffffff) +#define DC_WINC_A_H_FILTER_P0A_0_A_H_FILTER_P0AC0_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_H_FILTER_P0A_0_A_H_FILTER_P0AC0_FIELD _MK_FIELD_CONST(0x7, DC_WINC_A_H_FILTER_P0A_0_A_H_FILTER_P0AC0_SHIFT) +#define DC_WINC_A_H_FILTER_P0A_0_A_H_FILTER_P0AC0_RANGE 2:0 +#define DC_WINC_A_H_FILTER_P0A_0_A_H_FILTER_P0AC0_WOFFSET 0x0 +#define DC_WINC_A_H_FILTER_P0A_0_A_H_FILTER_P0AC0_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P0A_0_A_H_FILTER_P0AC0_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P0A_0_A_H_FILTER_P0AC0_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P0A_0_A_H_FILTER_P0AC0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_H_FILTER_P0A_0_A_H_FILTER_P0AC1_SHIFT _MK_SHIFT_CONST(3) +#define DC_WINC_A_H_FILTER_P0A_0_A_H_FILTER_P0AC1_FIELD _MK_FIELD_CONST(0x1f, DC_WINC_A_H_FILTER_P0A_0_A_H_FILTER_P0AC1_SHIFT) +#define DC_WINC_A_H_FILTER_P0A_0_A_H_FILTER_P0AC1_RANGE 7:3 +#define DC_WINC_A_H_FILTER_P0A_0_A_H_FILTER_P0AC1_WOFFSET 0x0 +#define DC_WINC_A_H_FILTER_P0A_0_A_H_FILTER_P0AC1_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P0A_0_A_H_FILTER_P0AC1_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P0A_0_A_H_FILTER_P0AC1_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P0A_0_A_H_FILTER_P0AC1_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_H_FILTER_P0A_0_A_H_FILTER_P0AC2_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_H_FILTER_P0A_0_A_H_FILTER_P0AC2_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_H_FILTER_P0A_0_A_H_FILTER_P0AC2_SHIFT) +#define DC_WINC_A_H_FILTER_P0A_0_A_H_FILTER_P0AC2_RANGE 15:8 +#define DC_WINC_A_H_FILTER_P0A_0_A_H_FILTER_P0AC2_WOFFSET 0x0 +#define DC_WINC_A_H_FILTER_P0A_0_A_H_FILTER_P0AC2_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P0A_0_A_H_FILTER_P0AC2_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P0A_0_A_H_FILTER_P0AC2_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P0A_0_A_H_FILTER_P0AC2_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_H_FILTER_P0A_0_A_H_FILTER_P0AC3_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_H_FILTER_P0A_0_A_H_FILTER_P0AC3_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_H_FILTER_P0A_0_A_H_FILTER_P0AC3_SHIFT) +#define DC_WINC_A_H_FILTER_P0A_0_A_H_FILTER_P0AC3_RANGE 23:16 +#define DC_WINC_A_H_FILTER_P0A_0_A_H_FILTER_P0AC3_WOFFSET 0x0 +#define DC_WINC_A_H_FILTER_P0A_0_A_H_FILTER_P0AC3_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P0A_0_A_H_FILTER_P0AC3_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P0A_0_A_H_FILTER_P0AC3_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P0A_0_A_H_FILTER_P0AC3_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_H_FILTER_P0A_0_A_H_FILTER_P0AC4_SHIFT _MK_SHIFT_CONST(24) +#define DC_WINC_A_H_FILTER_P0A_0_A_H_FILTER_P0AC4_FIELD _MK_FIELD_CONST(0x1f, DC_WINC_A_H_FILTER_P0A_0_A_H_FILTER_P0AC4_SHIFT) +#define DC_WINC_A_H_FILTER_P0A_0_A_H_FILTER_P0AC4_RANGE 28:24 +#define DC_WINC_A_H_FILTER_P0A_0_A_H_FILTER_P0AC4_WOFFSET 0x0 +#define DC_WINC_A_H_FILTER_P0A_0_A_H_FILTER_P0AC4_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P0A_0_A_H_FILTER_P0AC4_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P0A_0_A_H_FILTER_P0AC4_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P0A_0_A_H_FILTER_P0AC4_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_H_FILTER_P0A_0_A_H_FILTER_P0AC5_SHIFT _MK_SHIFT_CONST(29) +#define DC_WINC_A_H_FILTER_P0A_0_A_H_FILTER_P0AC5_FIELD _MK_FIELD_CONST(0x7, DC_WINC_A_H_FILTER_P0A_0_A_H_FILTER_P0AC5_SHIFT) +#define DC_WINC_A_H_FILTER_P0A_0_A_H_FILTER_P0AC5_RANGE 31:29 +#define DC_WINC_A_H_FILTER_P0A_0_A_H_FILTER_P0AC5_WOFFSET 0x0 +#define DC_WINC_A_H_FILTER_P0A_0_A_H_FILTER_P0AC5_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P0A_0_A_H_FILTER_P0AC5_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P0A_0_A_H_FILTER_P0AC5_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P0A_0_A_H_FILTER_P0AC5_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_WINC_A_H_FILTER_P0B_0 +#define DC_WINC_A_H_FILTER_P0B_0 _MK_ADDR_CONST(0x60c) +#define DC_WINC_A_H_FILTER_P0B_0_SECURE 0x0 +#define DC_WINC_A_H_FILTER_P0B_0_WORD_COUNT 0x1 +#define DC_WINC_A_H_FILTER_P0B_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P0B_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P0B_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P0B_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P0B_0_READ_MASK _MK_MASK_CONST(0xffffffff) +#define DC_WINC_A_H_FILTER_P0B_0_WRITE_MASK _MK_MASK_CONST(0xffffffff) +#define DC_WINC_A_H_FILTER_P0B_0_A_H_FILTER_P0BC0_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_H_FILTER_P0B_0_A_H_FILTER_P0BC0_FIELD _MK_FIELD_CONST(0x7, DC_WINC_A_H_FILTER_P0B_0_A_H_FILTER_P0BC0_SHIFT) +#define DC_WINC_A_H_FILTER_P0B_0_A_H_FILTER_P0BC0_RANGE 2:0 +#define DC_WINC_A_H_FILTER_P0B_0_A_H_FILTER_P0BC0_WOFFSET 0x0 +#define DC_WINC_A_H_FILTER_P0B_0_A_H_FILTER_P0BC0_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P0B_0_A_H_FILTER_P0BC0_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P0B_0_A_H_FILTER_P0BC0_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P0B_0_A_H_FILTER_P0BC0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_H_FILTER_P0B_0_A_H_FILTER_P0BC1_SHIFT _MK_SHIFT_CONST(3) +#define DC_WINC_A_H_FILTER_P0B_0_A_H_FILTER_P0BC1_FIELD _MK_FIELD_CONST(0x1f, DC_WINC_A_H_FILTER_P0B_0_A_H_FILTER_P0BC1_SHIFT) +#define DC_WINC_A_H_FILTER_P0B_0_A_H_FILTER_P0BC1_RANGE 7:3 +#define DC_WINC_A_H_FILTER_P0B_0_A_H_FILTER_P0BC1_WOFFSET 0x0 +#define DC_WINC_A_H_FILTER_P0B_0_A_H_FILTER_P0BC1_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P0B_0_A_H_FILTER_P0BC1_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P0B_0_A_H_FILTER_P0BC1_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P0B_0_A_H_FILTER_P0BC1_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_H_FILTER_P0B_0_A_H_FILTER_P0BC2_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_H_FILTER_P0B_0_A_H_FILTER_P0BC2_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_H_FILTER_P0B_0_A_H_FILTER_P0BC2_SHIFT) +#define DC_WINC_A_H_FILTER_P0B_0_A_H_FILTER_P0BC2_RANGE 15:8 +#define DC_WINC_A_H_FILTER_P0B_0_A_H_FILTER_P0BC2_WOFFSET 0x0 +#define DC_WINC_A_H_FILTER_P0B_0_A_H_FILTER_P0BC2_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P0B_0_A_H_FILTER_P0BC2_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P0B_0_A_H_FILTER_P0BC2_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P0B_0_A_H_FILTER_P0BC2_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_H_FILTER_P0B_0_A_H_FILTER_P0BC3_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_H_FILTER_P0B_0_A_H_FILTER_P0BC3_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_H_FILTER_P0B_0_A_H_FILTER_P0BC3_SHIFT) +#define DC_WINC_A_H_FILTER_P0B_0_A_H_FILTER_P0BC3_RANGE 23:16 +#define DC_WINC_A_H_FILTER_P0B_0_A_H_FILTER_P0BC3_WOFFSET 0x0 +#define DC_WINC_A_H_FILTER_P0B_0_A_H_FILTER_P0BC3_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P0B_0_A_H_FILTER_P0BC3_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P0B_0_A_H_FILTER_P0BC3_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P0B_0_A_H_FILTER_P0BC3_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_H_FILTER_P0B_0_A_H_FILTER_P0BC4_SHIFT _MK_SHIFT_CONST(24) +#define DC_WINC_A_H_FILTER_P0B_0_A_H_FILTER_P0BC4_FIELD _MK_FIELD_CONST(0x1f, DC_WINC_A_H_FILTER_P0B_0_A_H_FILTER_P0BC4_SHIFT) +#define DC_WINC_A_H_FILTER_P0B_0_A_H_FILTER_P0BC4_RANGE 28:24 +#define DC_WINC_A_H_FILTER_P0B_0_A_H_FILTER_P0BC4_WOFFSET 0x0 +#define DC_WINC_A_H_FILTER_P0B_0_A_H_FILTER_P0BC4_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P0B_0_A_H_FILTER_P0BC4_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P0B_0_A_H_FILTER_P0BC4_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P0B_0_A_H_FILTER_P0BC4_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_H_FILTER_P0B_0_A_H_FILTER_P0BC5_SHIFT _MK_SHIFT_CONST(29) +#define DC_WINC_A_H_FILTER_P0B_0_A_H_FILTER_P0BC5_FIELD _MK_FIELD_CONST(0x7, DC_WINC_A_H_FILTER_P0B_0_A_H_FILTER_P0BC5_SHIFT) +#define DC_WINC_A_H_FILTER_P0B_0_A_H_FILTER_P0BC5_RANGE 31:29 +#define DC_WINC_A_H_FILTER_P0B_0_A_H_FILTER_P0BC5_WOFFSET 0x0 +#define DC_WINC_A_H_FILTER_P0B_0_A_H_FILTER_P0BC5_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P0B_0_A_H_FILTER_P0BC5_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P0B_0_A_H_FILTER_P0BC5_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P0B_0_A_H_FILTER_P0BC5_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_WINC_A_H_FILTER_P0C_0 +#define DC_WINC_A_H_FILTER_P0C_0 _MK_ADDR_CONST(0x60d) +#define DC_WINC_A_H_FILTER_P0C_0_SECURE 0x0 +#define DC_WINC_A_H_FILTER_P0C_0_WORD_COUNT 0x1 +#define DC_WINC_A_H_FILTER_P0C_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P0C_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P0C_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P0C_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P0C_0_READ_MASK _MK_MASK_CONST(0xffffffff) +#define DC_WINC_A_H_FILTER_P0C_0_WRITE_MASK _MK_MASK_CONST(0xffffffff) +#define DC_WINC_A_H_FILTER_P0C_0_A_H_FILTER_P0CC0_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_H_FILTER_P0C_0_A_H_FILTER_P0CC0_FIELD _MK_FIELD_CONST(0x7, DC_WINC_A_H_FILTER_P0C_0_A_H_FILTER_P0CC0_SHIFT) +#define DC_WINC_A_H_FILTER_P0C_0_A_H_FILTER_P0CC0_RANGE 2:0 +#define DC_WINC_A_H_FILTER_P0C_0_A_H_FILTER_P0CC0_WOFFSET 0x0 +#define DC_WINC_A_H_FILTER_P0C_0_A_H_FILTER_P0CC0_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P0C_0_A_H_FILTER_P0CC0_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P0C_0_A_H_FILTER_P0CC0_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P0C_0_A_H_FILTER_P0CC0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_H_FILTER_P0C_0_A_H_FILTER_P0CC1_SHIFT _MK_SHIFT_CONST(3) +#define DC_WINC_A_H_FILTER_P0C_0_A_H_FILTER_P0CC1_FIELD _MK_FIELD_CONST(0x1f, DC_WINC_A_H_FILTER_P0C_0_A_H_FILTER_P0CC1_SHIFT) +#define DC_WINC_A_H_FILTER_P0C_0_A_H_FILTER_P0CC1_RANGE 7:3 +#define DC_WINC_A_H_FILTER_P0C_0_A_H_FILTER_P0CC1_WOFFSET 0x0 +#define DC_WINC_A_H_FILTER_P0C_0_A_H_FILTER_P0CC1_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P0C_0_A_H_FILTER_P0CC1_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P0C_0_A_H_FILTER_P0CC1_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P0C_0_A_H_FILTER_P0CC1_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_H_FILTER_P0C_0_A_H_FILTER_P0CC2_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_H_FILTER_P0C_0_A_H_FILTER_P0CC2_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_H_FILTER_P0C_0_A_H_FILTER_P0CC2_SHIFT) +#define DC_WINC_A_H_FILTER_P0C_0_A_H_FILTER_P0CC2_RANGE 15:8 +#define DC_WINC_A_H_FILTER_P0C_0_A_H_FILTER_P0CC2_WOFFSET 0x0 +#define DC_WINC_A_H_FILTER_P0C_0_A_H_FILTER_P0CC2_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P0C_0_A_H_FILTER_P0CC2_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P0C_0_A_H_FILTER_P0CC2_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P0C_0_A_H_FILTER_P0CC2_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_H_FILTER_P0C_0_A_H_FILTER_P0CC3_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_H_FILTER_P0C_0_A_H_FILTER_P0CC3_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_H_FILTER_P0C_0_A_H_FILTER_P0CC3_SHIFT) +#define DC_WINC_A_H_FILTER_P0C_0_A_H_FILTER_P0CC3_RANGE 23:16 +#define DC_WINC_A_H_FILTER_P0C_0_A_H_FILTER_P0CC3_WOFFSET 0x0 +#define DC_WINC_A_H_FILTER_P0C_0_A_H_FILTER_P0CC3_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P0C_0_A_H_FILTER_P0CC3_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P0C_0_A_H_FILTER_P0CC3_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P0C_0_A_H_FILTER_P0CC3_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_H_FILTER_P0C_0_A_H_FILTER_P0CC4_SHIFT _MK_SHIFT_CONST(24) +#define DC_WINC_A_H_FILTER_P0C_0_A_H_FILTER_P0CC4_FIELD _MK_FIELD_CONST(0x1f, DC_WINC_A_H_FILTER_P0C_0_A_H_FILTER_P0CC4_SHIFT) +#define DC_WINC_A_H_FILTER_P0C_0_A_H_FILTER_P0CC4_RANGE 28:24 +#define DC_WINC_A_H_FILTER_P0C_0_A_H_FILTER_P0CC4_WOFFSET 0x0 +#define DC_WINC_A_H_FILTER_P0C_0_A_H_FILTER_P0CC4_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P0C_0_A_H_FILTER_P0CC4_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P0C_0_A_H_FILTER_P0CC4_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P0C_0_A_H_FILTER_P0CC4_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_H_FILTER_P0C_0_A_H_FILTER_P0CC5_SHIFT _MK_SHIFT_CONST(29) +#define DC_WINC_A_H_FILTER_P0C_0_A_H_FILTER_P0CC5_FIELD _MK_FIELD_CONST(0x7, DC_WINC_A_H_FILTER_P0C_0_A_H_FILTER_P0CC5_SHIFT) +#define DC_WINC_A_H_FILTER_P0C_0_A_H_FILTER_P0CC5_RANGE 31:29 +#define DC_WINC_A_H_FILTER_P0C_0_A_H_FILTER_P0CC5_WOFFSET 0x0 +#define DC_WINC_A_H_FILTER_P0C_0_A_H_FILTER_P0CC5_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P0C_0_A_H_FILTER_P0CC5_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P0C_0_A_H_FILTER_P0CC5_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P0C_0_A_H_FILTER_P0CC5_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_WINC_A_H_FILTER_P0D_0 +#define DC_WINC_A_H_FILTER_P0D_0 _MK_ADDR_CONST(0x60e) +#define DC_WINC_A_H_FILTER_P0D_0_SECURE 0x0 +#define DC_WINC_A_H_FILTER_P0D_0_WORD_COUNT 0x1 +#define DC_WINC_A_H_FILTER_P0D_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P0D_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P0D_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P0D_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P0D_0_READ_MASK _MK_MASK_CONST(0xffffffff) +#define DC_WINC_A_H_FILTER_P0D_0_WRITE_MASK _MK_MASK_CONST(0xffffffff) +#define DC_WINC_A_H_FILTER_P0D_0_A_H_FILTER_P0DC0_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_H_FILTER_P0D_0_A_H_FILTER_P0DC0_FIELD _MK_FIELD_CONST(0x7, DC_WINC_A_H_FILTER_P0D_0_A_H_FILTER_P0DC0_SHIFT) +#define DC_WINC_A_H_FILTER_P0D_0_A_H_FILTER_P0DC0_RANGE 2:0 +#define DC_WINC_A_H_FILTER_P0D_0_A_H_FILTER_P0DC0_WOFFSET 0x0 +#define DC_WINC_A_H_FILTER_P0D_0_A_H_FILTER_P0DC0_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P0D_0_A_H_FILTER_P0DC0_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P0D_0_A_H_FILTER_P0DC0_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P0D_0_A_H_FILTER_P0DC0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_H_FILTER_P0D_0_A_H_FILTER_P0DC1_SHIFT _MK_SHIFT_CONST(3) +#define DC_WINC_A_H_FILTER_P0D_0_A_H_FILTER_P0DC1_FIELD _MK_FIELD_CONST(0x1f, DC_WINC_A_H_FILTER_P0D_0_A_H_FILTER_P0DC1_SHIFT) +#define DC_WINC_A_H_FILTER_P0D_0_A_H_FILTER_P0DC1_RANGE 7:3 +#define DC_WINC_A_H_FILTER_P0D_0_A_H_FILTER_P0DC1_WOFFSET 0x0 +#define DC_WINC_A_H_FILTER_P0D_0_A_H_FILTER_P0DC1_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P0D_0_A_H_FILTER_P0DC1_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P0D_0_A_H_FILTER_P0DC1_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P0D_0_A_H_FILTER_P0DC1_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_H_FILTER_P0D_0_A_H_FILTER_P0DC2_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_H_FILTER_P0D_0_A_H_FILTER_P0DC2_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_H_FILTER_P0D_0_A_H_FILTER_P0DC2_SHIFT) +#define DC_WINC_A_H_FILTER_P0D_0_A_H_FILTER_P0DC2_RANGE 15:8 +#define DC_WINC_A_H_FILTER_P0D_0_A_H_FILTER_P0DC2_WOFFSET 0x0 +#define DC_WINC_A_H_FILTER_P0D_0_A_H_FILTER_P0DC2_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P0D_0_A_H_FILTER_P0DC2_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P0D_0_A_H_FILTER_P0DC2_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P0D_0_A_H_FILTER_P0DC2_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_H_FILTER_P0D_0_A_H_FILTER_P0DC3_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_H_FILTER_P0D_0_A_H_FILTER_P0DC3_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_H_FILTER_P0D_0_A_H_FILTER_P0DC3_SHIFT) +#define DC_WINC_A_H_FILTER_P0D_0_A_H_FILTER_P0DC3_RANGE 23:16 +#define DC_WINC_A_H_FILTER_P0D_0_A_H_FILTER_P0DC3_WOFFSET 0x0 +#define DC_WINC_A_H_FILTER_P0D_0_A_H_FILTER_P0DC3_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P0D_0_A_H_FILTER_P0DC3_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P0D_0_A_H_FILTER_P0DC3_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P0D_0_A_H_FILTER_P0DC3_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_H_FILTER_P0D_0_A_H_FILTER_P0DC4_SHIFT _MK_SHIFT_CONST(24) +#define DC_WINC_A_H_FILTER_P0D_0_A_H_FILTER_P0DC4_FIELD _MK_FIELD_CONST(0x1f, DC_WINC_A_H_FILTER_P0D_0_A_H_FILTER_P0DC4_SHIFT) +#define DC_WINC_A_H_FILTER_P0D_0_A_H_FILTER_P0DC4_RANGE 28:24 +#define DC_WINC_A_H_FILTER_P0D_0_A_H_FILTER_P0DC4_WOFFSET 0x0 +#define DC_WINC_A_H_FILTER_P0D_0_A_H_FILTER_P0DC4_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P0D_0_A_H_FILTER_P0DC4_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P0D_0_A_H_FILTER_P0DC4_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P0D_0_A_H_FILTER_P0DC4_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_H_FILTER_P0D_0_A_H_FILTER_P0DC5_SHIFT _MK_SHIFT_CONST(29) +#define DC_WINC_A_H_FILTER_P0D_0_A_H_FILTER_P0DC5_FIELD _MK_FIELD_CONST(0x7, DC_WINC_A_H_FILTER_P0D_0_A_H_FILTER_P0DC5_SHIFT) +#define DC_WINC_A_H_FILTER_P0D_0_A_H_FILTER_P0DC5_RANGE 31:29 +#define DC_WINC_A_H_FILTER_P0D_0_A_H_FILTER_P0DC5_WOFFSET 0x0 +#define DC_WINC_A_H_FILTER_P0D_0_A_H_FILTER_P0DC5_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P0D_0_A_H_FILTER_P0DC5_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P0D_0_A_H_FILTER_P0DC5_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P0D_0_A_H_FILTER_P0DC5_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_WINC_A_H_FILTER_P0E_0 +#define DC_WINC_A_H_FILTER_P0E_0 _MK_ADDR_CONST(0x60f) +#define DC_WINC_A_H_FILTER_P0E_0_SECURE 0x0 +#define DC_WINC_A_H_FILTER_P0E_0_WORD_COUNT 0x1 +#define DC_WINC_A_H_FILTER_P0E_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P0E_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P0E_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P0E_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P0E_0_READ_MASK _MK_MASK_CONST(0xffffffff) +#define DC_WINC_A_H_FILTER_P0E_0_WRITE_MASK _MK_MASK_CONST(0xffffffff) +#define DC_WINC_A_H_FILTER_P0E_0_A_H_FILTER_P0EC0_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_H_FILTER_P0E_0_A_H_FILTER_P0EC0_FIELD _MK_FIELD_CONST(0x7, DC_WINC_A_H_FILTER_P0E_0_A_H_FILTER_P0EC0_SHIFT) +#define DC_WINC_A_H_FILTER_P0E_0_A_H_FILTER_P0EC0_RANGE 2:0 +#define DC_WINC_A_H_FILTER_P0E_0_A_H_FILTER_P0EC0_WOFFSET 0x0 +#define DC_WINC_A_H_FILTER_P0E_0_A_H_FILTER_P0EC0_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P0E_0_A_H_FILTER_P0EC0_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P0E_0_A_H_FILTER_P0EC0_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P0E_0_A_H_FILTER_P0EC0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_H_FILTER_P0E_0_A_H_FILTER_P0EC1_SHIFT _MK_SHIFT_CONST(3) +#define DC_WINC_A_H_FILTER_P0E_0_A_H_FILTER_P0EC1_FIELD _MK_FIELD_CONST(0x1f, DC_WINC_A_H_FILTER_P0E_0_A_H_FILTER_P0EC1_SHIFT) +#define DC_WINC_A_H_FILTER_P0E_0_A_H_FILTER_P0EC1_RANGE 7:3 +#define DC_WINC_A_H_FILTER_P0E_0_A_H_FILTER_P0EC1_WOFFSET 0x0 +#define DC_WINC_A_H_FILTER_P0E_0_A_H_FILTER_P0EC1_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P0E_0_A_H_FILTER_P0EC1_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P0E_0_A_H_FILTER_P0EC1_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P0E_0_A_H_FILTER_P0EC1_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_H_FILTER_P0E_0_A_H_FILTER_P0EC2_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_H_FILTER_P0E_0_A_H_FILTER_P0EC2_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_H_FILTER_P0E_0_A_H_FILTER_P0EC2_SHIFT) +#define DC_WINC_A_H_FILTER_P0E_0_A_H_FILTER_P0EC2_RANGE 15:8 +#define DC_WINC_A_H_FILTER_P0E_0_A_H_FILTER_P0EC2_WOFFSET 0x0 +#define DC_WINC_A_H_FILTER_P0E_0_A_H_FILTER_P0EC2_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P0E_0_A_H_FILTER_P0EC2_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P0E_0_A_H_FILTER_P0EC2_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P0E_0_A_H_FILTER_P0EC2_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_H_FILTER_P0E_0_A_H_FILTER_P0EC3_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_H_FILTER_P0E_0_A_H_FILTER_P0EC3_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_H_FILTER_P0E_0_A_H_FILTER_P0EC3_SHIFT) +#define DC_WINC_A_H_FILTER_P0E_0_A_H_FILTER_P0EC3_RANGE 23:16 +#define DC_WINC_A_H_FILTER_P0E_0_A_H_FILTER_P0EC3_WOFFSET 0x0 +#define DC_WINC_A_H_FILTER_P0E_0_A_H_FILTER_P0EC3_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P0E_0_A_H_FILTER_P0EC3_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P0E_0_A_H_FILTER_P0EC3_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P0E_0_A_H_FILTER_P0EC3_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_H_FILTER_P0E_0_A_H_FILTER_P0EC4_SHIFT _MK_SHIFT_CONST(24) +#define DC_WINC_A_H_FILTER_P0E_0_A_H_FILTER_P0EC4_FIELD _MK_FIELD_CONST(0x1f, DC_WINC_A_H_FILTER_P0E_0_A_H_FILTER_P0EC4_SHIFT) +#define DC_WINC_A_H_FILTER_P0E_0_A_H_FILTER_P0EC4_RANGE 28:24 +#define DC_WINC_A_H_FILTER_P0E_0_A_H_FILTER_P0EC4_WOFFSET 0x0 +#define DC_WINC_A_H_FILTER_P0E_0_A_H_FILTER_P0EC4_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P0E_0_A_H_FILTER_P0EC4_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P0E_0_A_H_FILTER_P0EC4_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P0E_0_A_H_FILTER_P0EC4_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_H_FILTER_P0E_0_A_H_FILTER_P0EC5_SHIFT _MK_SHIFT_CONST(29) +#define DC_WINC_A_H_FILTER_P0E_0_A_H_FILTER_P0EC5_FIELD _MK_FIELD_CONST(0x7, DC_WINC_A_H_FILTER_P0E_0_A_H_FILTER_P0EC5_SHIFT) +#define DC_WINC_A_H_FILTER_P0E_0_A_H_FILTER_P0EC5_RANGE 31:29 +#define DC_WINC_A_H_FILTER_P0E_0_A_H_FILTER_P0EC5_WOFFSET 0x0 +#define DC_WINC_A_H_FILTER_P0E_0_A_H_FILTER_P0EC5_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P0E_0_A_H_FILTER_P0EC5_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P0E_0_A_H_FILTER_P0EC5_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P0E_0_A_H_FILTER_P0EC5_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_WINC_A_H_FILTER_P0F_0 +#define DC_WINC_A_H_FILTER_P0F_0 _MK_ADDR_CONST(0x610) +#define DC_WINC_A_H_FILTER_P0F_0_SECURE 0x0 +#define DC_WINC_A_H_FILTER_P0F_0_WORD_COUNT 0x1 +#define DC_WINC_A_H_FILTER_P0F_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P0F_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P0F_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P0F_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P0F_0_READ_MASK _MK_MASK_CONST(0xffffffff) +#define DC_WINC_A_H_FILTER_P0F_0_WRITE_MASK _MK_MASK_CONST(0xffffffff) +#define DC_WINC_A_H_FILTER_P0F_0_A_H_FILTER_P0FC0_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_H_FILTER_P0F_0_A_H_FILTER_P0FC0_FIELD _MK_FIELD_CONST(0x7, DC_WINC_A_H_FILTER_P0F_0_A_H_FILTER_P0FC0_SHIFT) +#define DC_WINC_A_H_FILTER_P0F_0_A_H_FILTER_P0FC0_RANGE 2:0 +#define DC_WINC_A_H_FILTER_P0F_0_A_H_FILTER_P0FC0_WOFFSET 0x0 +#define DC_WINC_A_H_FILTER_P0F_0_A_H_FILTER_P0FC0_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P0F_0_A_H_FILTER_P0FC0_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P0F_0_A_H_FILTER_P0FC0_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P0F_0_A_H_FILTER_P0FC0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_H_FILTER_P0F_0_A_H_FILTER_P0FC1_SHIFT _MK_SHIFT_CONST(3) +#define DC_WINC_A_H_FILTER_P0F_0_A_H_FILTER_P0FC1_FIELD _MK_FIELD_CONST(0x1f, DC_WINC_A_H_FILTER_P0F_0_A_H_FILTER_P0FC1_SHIFT) +#define DC_WINC_A_H_FILTER_P0F_0_A_H_FILTER_P0FC1_RANGE 7:3 +#define DC_WINC_A_H_FILTER_P0F_0_A_H_FILTER_P0FC1_WOFFSET 0x0 +#define DC_WINC_A_H_FILTER_P0F_0_A_H_FILTER_P0FC1_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P0F_0_A_H_FILTER_P0FC1_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P0F_0_A_H_FILTER_P0FC1_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P0F_0_A_H_FILTER_P0FC1_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_H_FILTER_P0F_0_A_H_FILTER_P0FC2_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_H_FILTER_P0F_0_A_H_FILTER_P0FC2_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_H_FILTER_P0F_0_A_H_FILTER_P0FC2_SHIFT) +#define DC_WINC_A_H_FILTER_P0F_0_A_H_FILTER_P0FC2_RANGE 15:8 +#define DC_WINC_A_H_FILTER_P0F_0_A_H_FILTER_P0FC2_WOFFSET 0x0 +#define DC_WINC_A_H_FILTER_P0F_0_A_H_FILTER_P0FC2_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P0F_0_A_H_FILTER_P0FC2_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P0F_0_A_H_FILTER_P0FC2_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P0F_0_A_H_FILTER_P0FC2_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_H_FILTER_P0F_0_A_H_FILTER_P0FC3_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINC_A_H_FILTER_P0F_0_A_H_FILTER_P0FC3_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_H_FILTER_P0F_0_A_H_FILTER_P0FC3_SHIFT) +#define DC_WINC_A_H_FILTER_P0F_0_A_H_FILTER_P0FC3_RANGE 23:16 +#define DC_WINC_A_H_FILTER_P0F_0_A_H_FILTER_P0FC3_WOFFSET 0x0 +#define DC_WINC_A_H_FILTER_P0F_0_A_H_FILTER_P0FC3_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P0F_0_A_H_FILTER_P0FC3_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P0F_0_A_H_FILTER_P0FC3_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P0F_0_A_H_FILTER_P0FC3_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_H_FILTER_P0F_0_A_H_FILTER_P0FC4_SHIFT _MK_SHIFT_CONST(24) +#define DC_WINC_A_H_FILTER_P0F_0_A_H_FILTER_P0FC4_FIELD _MK_FIELD_CONST(0x1f, DC_WINC_A_H_FILTER_P0F_0_A_H_FILTER_P0FC4_SHIFT) +#define DC_WINC_A_H_FILTER_P0F_0_A_H_FILTER_P0FC4_RANGE 28:24 +#define DC_WINC_A_H_FILTER_P0F_0_A_H_FILTER_P0FC4_WOFFSET 0x0 +#define DC_WINC_A_H_FILTER_P0F_0_A_H_FILTER_P0FC4_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P0F_0_A_H_FILTER_P0FC4_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P0F_0_A_H_FILTER_P0FC4_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P0F_0_A_H_FILTER_P0FC4_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_H_FILTER_P0F_0_A_H_FILTER_P0FC5_SHIFT _MK_SHIFT_CONST(29) +#define DC_WINC_A_H_FILTER_P0F_0_A_H_FILTER_P0FC5_FIELD _MK_FIELD_CONST(0x7, DC_WINC_A_H_FILTER_P0F_0_A_H_FILTER_P0FC5_SHIFT) +#define DC_WINC_A_H_FILTER_P0F_0_A_H_FILTER_P0FC5_RANGE 31:29 +#define DC_WINC_A_H_FILTER_P0F_0_A_H_FILTER_P0FC5_WOFFSET 0x0 +#define DC_WINC_A_H_FILTER_P0F_0_A_H_FILTER_P0FC5_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P0F_0_A_H_FILTER_P0FC5_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P0F_0_A_H_FILTER_P0FC5_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_P0F_0_A_H_FILTER_P0FC5_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_WINC_A_CSC_YOF_0 +#define DC_WINC_A_CSC_YOF_0 _MK_ADDR_CONST(0x611) +#define DC_WINC_A_CSC_YOF_0_SECURE 0x0 +#define DC_WINC_A_CSC_YOF_0_WORD_COUNT 0x1 +#define DC_WINC_A_CSC_YOF_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_CSC_YOF_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_CSC_YOF_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_CSC_YOF_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_CSC_YOF_0_READ_MASK _MK_MASK_CONST(0xff) +#define DC_WINC_A_CSC_YOF_0_WRITE_MASK _MK_MASK_CONST(0xff) +#define DC_WINC_A_CSC_YOF_0_A_CSC_YOF_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_CSC_YOF_0_A_CSC_YOF_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_CSC_YOF_0_A_CSC_YOF_SHIFT) +#define DC_WINC_A_CSC_YOF_0_A_CSC_YOF_RANGE 7:0 +#define DC_WINC_A_CSC_YOF_0_A_CSC_YOF_WOFFSET 0x0 +#define DC_WINC_A_CSC_YOF_0_A_CSC_YOF_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_CSC_YOF_0_A_CSC_YOF_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_CSC_YOF_0_A_CSC_YOF_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_CSC_YOF_0_A_CSC_YOF_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_WINC_A_CSC_KYRGB_0 +#define DC_WINC_A_CSC_KYRGB_0 _MK_ADDR_CONST(0x612) +#define DC_WINC_A_CSC_KYRGB_0_SECURE 0x0 +#define DC_WINC_A_CSC_KYRGB_0_WORD_COUNT 0x1 +#define DC_WINC_A_CSC_KYRGB_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_CSC_KYRGB_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_CSC_KYRGB_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_CSC_KYRGB_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_CSC_KYRGB_0_READ_MASK _MK_MASK_CONST(0x3ff) +#define DC_WINC_A_CSC_KYRGB_0_WRITE_MASK _MK_MASK_CONST(0x3ff) +#define DC_WINC_A_CSC_KYRGB_0_A_CSC_KYRGB_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_CSC_KYRGB_0_A_CSC_KYRGB_FIELD _MK_FIELD_CONST(0x3ff, DC_WINC_A_CSC_KYRGB_0_A_CSC_KYRGB_SHIFT) +#define DC_WINC_A_CSC_KYRGB_0_A_CSC_KYRGB_RANGE 9:0 +#define DC_WINC_A_CSC_KYRGB_0_A_CSC_KYRGB_WOFFSET 0x0 +#define DC_WINC_A_CSC_KYRGB_0_A_CSC_KYRGB_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_CSC_KYRGB_0_A_CSC_KYRGB_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_CSC_KYRGB_0_A_CSC_KYRGB_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_CSC_KYRGB_0_A_CSC_KYRGB_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_WINC_A_CSC_KUR_0 +#define DC_WINC_A_CSC_KUR_0 _MK_ADDR_CONST(0x613) +#define DC_WINC_A_CSC_KUR_0_SECURE 0x0 +#define DC_WINC_A_CSC_KUR_0_WORD_COUNT 0x1 +#define DC_WINC_A_CSC_KUR_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_CSC_KUR_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_CSC_KUR_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_CSC_KUR_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_CSC_KUR_0_READ_MASK _MK_MASK_CONST(0x7ff) +#define DC_WINC_A_CSC_KUR_0_WRITE_MASK _MK_MASK_CONST(0x7ff) +#define DC_WINC_A_CSC_KUR_0_A_CSC_KUR_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_CSC_KUR_0_A_CSC_KUR_FIELD _MK_FIELD_CONST(0x7ff, DC_WINC_A_CSC_KUR_0_A_CSC_KUR_SHIFT) +#define DC_WINC_A_CSC_KUR_0_A_CSC_KUR_RANGE 10:0 +#define DC_WINC_A_CSC_KUR_0_A_CSC_KUR_WOFFSET 0x0 +#define DC_WINC_A_CSC_KUR_0_A_CSC_KUR_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_CSC_KUR_0_A_CSC_KUR_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_CSC_KUR_0_A_CSC_KUR_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_CSC_KUR_0_A_CSC_KUR_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_WINC_A_CSC_KVR_0 +#define DC_WINC_A_CSC_KVR_0 _MK_ADDR_CONST(0x614) +#define DC_WINC_A_CSC_KVR_0_SECURE 0x0 +#define DC_WINC_A_CSC_KVR_0_WORD_COUNT 0x1 +#define DC_WINC_A_CSC_KVR_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_CSC_KVR_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_CSC_KVR_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_CSC_KVR_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_CSC_KVR_0_READ_MASK _MK_MASK_CONST(0x7ff) +#define DC_WINC_A_CSC_KVR_0_WRITE_MASK _MK_MASK_CONST(0x7ff) +#define DC_WINC_A_CSC_KVR_0_A_CSC_KVR_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_CSC_KVR_0_A_CSC_KVR_FIELD _MK_FIELD_CONST(0x7ff, DC_WINC_A_CSC_KVR_0_A_CSC_KVR_SHIFT) +#define DC_WINC_A_CSC_KVR_0_A_CSC_KVR_RANGE 10:0 +#define DC_WINC_A_CSC_KVR_0_A_CSC_KVR_WOFFSET 0x0 +#define DC_WINC_A_CSC_KVR_0_A_CSC_KVR_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_CSC_KVR_0_A_CSC_KVR_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_CSC_KVR_0_A_CSC_KVR_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_CSC_KVR_0_A_CSC_KVR_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_WINC_A_CSC_KUG_0 +#define DC_WINC_A_CSC_KUG_0 _MK_ADDR_CONST(0x615) +#define DC_WINC_A_CSC_KUG_0_SECURE 0x0 +#define DC_WINC_A_CSC_KUG_0_WORD_COUNT 0x1 +#define DC_WINC_A_CSC_KUG_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_CSC_KUG_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_CSC_KUG_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_CSC_KUG_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_CSC_KUG_0_READ_MASK _MK_MASK_CONST(0x3ff) +#define DC_WINC_A_CSC_KUG_0_WRITE_MASK _MK_MASK_CONST(0x3ff) +#define DC_WINC_A_CSC_KUG_0_A_CSC_KUG_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_CSC_KUG_0_A_CSC_KUG_FIELD _MK_FIELD_CONST(0x3ff, DC_WINC_A_CSC_KUG_0_A_CSC_KUG_SHIFT) +#define DC_WINC_A_CSC_KUG_0_A_CSC_KUG_RANGE 9:0 +#define DC_WINC_A_CSC_KUG_0_A_CSC_KUG_WOFFSET 0x0 +#define DC_WINC_A_CSC_KUG_0_A_CSC_KUG_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_CSC_KUG_0_A_CSC_KUG_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_CSC_KUG_0_A_CSC_KUG_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_CSC_KUG_0_A_CSC_KUG_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_WINC_A_CSC_KVG_0 +#define DC_WINC_A_CSC_KVG_0 _MK_ADDR_CONST(0x616) +#define DC_WINC_A_CSC_KVG_0_SECURE 0x0 +#define DC_WINC_A_CSC_KVG_0_WORD_COUNT 0x1 +#define DC_WINC_A_CSC_KVG_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_CSC_KVG_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_CSC_KVG_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_CSC_KVG_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_CSC_KVG_0_READ_MASK _MK_MASK_CONST(0x3ff) +#define DC_WINC_A_CSC_KVG_0_WRITE_MASK _MK_MASK_CONST(0x3ff) +#define DC_WINC_A_CSC_KVG_0_A_CSC_KVG_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_CSC_KVG_0_A_CSC_KVG_FIELD _MK_FIELD_CONST(0x3ff, DC_WINC_A_CSC_KVG_0_A_CSC_KVG_SHIFT) +#define DC_WINC_A_CSC_KVG_0_A_CSC_KVG_RANGE 9:0 +#define DC_WINC_A_CSC_KVG_0_A_CSC_KVG_WOFFSET 0x0 +#define DC_WINC_A_CSC_KVG_0_A_CSC_KVG_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_CSC_KVG_0_A_CSC_KVG_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_CSC_KVG_0_A_CSC_KVG_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_CSC_KVG_0_A_CSC_KVG_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_WINC_A_CSC_KUB_0 +#define DC_WINC_A_CSC_KUB_0 _MK_ADDR_CONST(0x617) +#define DC_WINC_A_CSC_KUB_0_SECURE 0x0 +#define DC_WINC_A_CSC_KUB_0_WORD_COUNT 0x1 +#define DC_WINC_A_CSC_KUB_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_CSC_KUB_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_CSC_KUB_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_CSC_KUB_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_CSC_KUB_0_READ_MASK _MK_MASK_CONST(0x7ff) +#define DC_WINC_A_CSC_KUB_0_WRITE_MASK _MK_MASK_CONST(0x7ff) +#define DC_WINC_A_CSC_KUB_0_A_CSC_KUB_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_CSC_KUB_0_A_CSC_KUB_FIELD _MK_FIELD_CONST(0x7ff, DC_WINC_A_CSC_KUB_0_A_CSC_KUB_SHIFT) +#define DC_WINC_A_CSC_KUB_0_A_CSC_KUB_RANGE 10:0 +#define DC_WINC_A_CSC_KUB_0_A_CSC_KUB_WOFFSET 0x0 +#define DC_WINC_A_CSC_KUB_0_A_CSC_KUB_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_CSC_KUB_0_A_CSC_KUB_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_CSC_KUB_0_A_CSC_KUB_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_CSC_KUB_0_A_CSC_KUB_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_WINC_A_CSC_KVB_0 +#define DC_WINC_A_CSC_KVB_0 _MK_ADDR_CONST(0x618) +#define DC_WINC_A_CSC_KVB_0_SECURE 0x0 +#define DC_WINC_A_CSC_KVB_0_WORD_COUNT 0x1 +#define DC_WINC_A_CSC_KVB_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_CSC_KVB_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_CSC_KVB_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_CSC_KVB_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_CSC_KVB_0_READ_MASK _MK_MASK_CONST(0x7ff) +#define DC_WINC_A_CSC_KVB_0_WRITE_MASK _MK_MASK_CONST(0x7ff) +#define DC_WINC_A_CSC_KVB_0_A_CSC_KVB_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_CSC_KVB_0_A_CSC_KVB_FIELD _MK_FIELD_CONST(0x7ff, DC_WINC_A_CSC_KVB_0_A_CSC_KVB_SHIFT) +#define DC_WINC_A_CSC_KVB_0_A_CSC_KVB_RANGE 10:0 +#define DC_WINC_A_CSC_KVB_0_A_CSC_KVB_WOFFSET 0x0 +#define DC_WINC_A_CSC_KVB_0_A_CSC_KVB_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_CSC_KVB_0_A_CSC_KVB_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_CSC_KVB_0_A_CSC_KVB_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_CSC_KVB_0_A_CSC_KVB_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_WINC_A_V_FILTER_P00_0 +#define DC_WINC_A_V_FILTER_P00_0 _MK_ADDR_CONST(0x619) +#define DC_WINC_A_V_FILTER_P00_0_SECURE 0x0 +#define DC_WINC_A_V_FILTER_P00_0_WORD_COUNT 0x1 +#define DC_WINC_A_V_FILTER_P00_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_V_FILTER_P00_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_V_FILTER_P00_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_V_FILTER_P00_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_V_FILTER_P00_0_READ_MASK _MK_MASK_CONST(0xff) +#define DC_WINC_A_V_FILTER_P00_0_WRITE_MASK _MK_MASK_CONST(0xff) +#define DC_WINC_A_V_FILTER_P00_0_A_V_FILTER_P00C0_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_V_FILTER_P00_0_A_V_FILTER_P00C0_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_V_FILTER_P00_0_A_V_FILTER_P00C0_SHIFT) +#define DC_WINC_A_V_FILTER_P00_0_A_V_FILTER_P00C0_RANGE 7:0 +#define DC_WINC_A_V_FILTER_P00_0_A_V_FILTER_P00C0_WOFFSET 0x0 +#define DC_WINC_A_V_FILTER_P00_0_A_V_FILTER_P00C0_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_V_FILTER_P00_0_A_V_FILTER_P00C0_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_V_FILTER_P00_0_A_V_FILTER_P00C0_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_V_FILTER_P00_0_A_V_FILTER_P00C0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_WINC_A_V_FILTER_P01_0 +#define DC_WINC_A_V_FILTER_P01_0 _MK_ADDR_CONST(0x61a) +#define DC_WINC_A_V_FILTER_P01_0_SECURE 0x0 +#define DC_WINC_A_V_FILTER_P01_0_WORD_COUNT 0x1 +#define DC_WINC_A_V_FILTER_P01_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_V_FILTER_P01_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_V_FILTER_P01_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_V_FILTER_P01_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_V_FILTER_P01_0_READ_MASK _MK_MASK_CONST(0xff) +#define DC_WINC_A_V_FILTER_P01_0_WRITE_MASK _MK_MASK_CONST(0xff) +#define DC_WINC_A_V_FILTER_P01_0_A_V_FILTER_P01C0_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_V_FILTER_P01_0_A_V_FILTER_P01C0_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_V_FILTER_P01_0_A_V_FILTER_P01C0_SHIFT) +#define DC_WINC_A_V_FILTER_P01_0_A_V_FILTER_P01C0_RANGE 7:0 +#define DC_WINC_A_V_FILTER_P01_0_A_V_FILTER_P01C0_WOFFSET 0x0 +#define DC_WINC_A_V_FILTER_P01_0_A_V_FILTER_P01C0_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_V_FILTER_P01_0_A_V_FILTER_P01C0_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_V_FILTER_P01_0_A_V_FILTER_P01C0_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_V_FILTER_P01_0_A_V_FILTER_P01C0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_WINC_A_V_FILTER_P02_0 +#define DC_WINC_A_V_FILTER_P02_0 _MK_ADDR_CONST(0x61b) +#define DC_WINC_A_V_FILTER_P02_0_SECURE 0x0 +#define DC_WINC_A_V_FILTER_P02_0_WORD_COUNT 0x1 +#define DC_WINC_A_V_FILTER_P02_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_V_FILTER_P02_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_V_FILTER_P02_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_V_FILTER_P02_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_V_FILTER_P02_0_READ_MASK _MK_MASK_CONST(0xff) +#define DC_WINC_A_V_FILTER_P02_0_WRITE_MASK _MK_MASK_CONST(0xff) +#define DC_WINC_A_V_FILTER_P02_0_A_V_FILTER_P02C0_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_V_FILTER_P02_0_A_V_FILTER_P02C0_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_V_FILTER_P02_0_A_V_FILTER_P02C0_SHIFT) +#define DC_WINC_A_V_FILTER_P02_0_A_V_FILTER_P02C0_RANGE 7:0 +#define DC_WINC_A_V_FILTER_P02_0_A_V_FILTER_P02C0_WOFFSET 0x0 +#define DC_WINC_A_V_FILTER_P02_0_A_V_FILTER_P02C0_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_V_FILTER_P02_0_A_V_FILTER_P02C0_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_V_FILTER_P02_0_A_V_FILTER_P02C0_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_V_FILTER_P02_0_A_V_FILTER_P02C0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_WINC_A_V_FILTER_P03_0 +#define DC_WINC_A_V_FILTER_P03_0 _MK_ADDR_CONST(0x61c) +#define DC_WINC_A_V_FILTER_P03_0_SECURE 0x0 +#define DC_WINC_A_V_FILTER_P03_0_WORD_COUNT 0x1 +#define DC_WINC_A_V_FILTER_P03_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_V_FILTER_P03_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_V_FILTER_P03_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_V_FILTER_P03_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_V_FILTER_P03_0_READ_MASK _MK_MASK_CONST(0xff) +#define DC_WINC_A_V_FILTER_P03_0_WRITE_MASK _MK_MASK_CONST(0xff) +#define DC_WINC_A_V_FILTER_P03_0_A_V_FILTER_P03C0_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_V_FILTER_P03_0_A_V_FILTER_P03C0_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_V_FILTER_P03_0_A_V_FILTER_P03C0_SHIFT) +#define DC_WINC_A_V_FILTER_P03_0_A_V_FILTER_P03C0_RANGE 7:0 +#define DC_WINC_A_V_FILTER_P03_0_A_V_FILTER_P03C0_WOFFSET 0x0 +#define DC_WINC_A_V_FILTER_P03_0_A_V_FILTER_P03C0_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_V_FILTER_P03_0_A_V_FILTER_P03C0_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_V_FILTER_P03_0_A_V_FILTER_P03C0_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_V_FILTER_P03_0_A_V_FILTER_P03C0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_WINC_A_V_FILTER_P04_0 +#define DC_WINC_A_V_FILTER_P04_0 _MK_ADDR_CONST(0x61d) +#define DC_WINC_A_V_FILTER_P04_0_SECURE 0x0 +#define DC_WINC_A_V_FILTER_P04_0_WORD_COUNT 0x1 +#define DC_WINC_A_V_FILTER_P04_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_V_FILTER_P04_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_V_FILTER_P04_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_V_FILTER_P04_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_V_FILTER_P04_0_READ_MASK _MK_MASK_CONST(0xff) +#define DC_WINC_A_V_FILTER_P04_0_WRITE_MASK _MK_MASK_CONST(0xff) +#define DC_WINC_A_V_FILTER_P04_0_A_V_FILTER_P04C0_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_V_FILTER_P04_0_A_V_FILTER_P04C0_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_V_FILTER_P04_0_A_V_FILTER_P04C0_SHIFT) +#define DC_WINC_A_V_FILTER_P04_0_A_V_FILTER_P04C0_RANGE 7:0 +#define DC_WINC_A_V_FILTER_P04_0_A_V_FILTER_P04C0_WOFFSET 0x0 +#define DC_WINC_A_V_FILTER_P04_0_A_V_FILTER_P04C0_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_V_FILTER_P04_0_A_V_FILTER_P04C0_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_V_FILTER_P04_0_A_V_FILTER_P04C0_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_V_FILTER_P04_0_A_V_FILTER_P04C0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_WINC_A_V_FILTER_P05_0 +#define DC_WINC_A_V_FILTER_P05_0 _MK_ADDR_CONST(0x61e) +#define DC_WINC_A_V_FILTER_P05_0_SECURE 0x0 +#define DC_WINC_A_V_FILTER_P05_0_WORD_COUNT 0x1 +#define DC_WINC_A_V_FILTER_P05_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_V_FILTER_P05_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_V_FILTER_P05_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_V_FILTER_P05_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_V_FILTER_P05_0_READ_MASK _MK_MASK_CONST(0xff) +#define DC_WINC_A_V_FILTER_P05_0_WRITE_MASK _MK_MASK_CONST(0xff) +#define DC_WINC_A_V_FILTER_P05_0_A_V_FILTER_P05C0_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_V_FILTER_P05_0_A_V_FILTER_P05C0_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_V_FILTER_P05_0_A_V_FILTER_P05C0_SHIFT) +#define DC_WINC_A_V_FILTER_P05_0_A_V_FILTER_P05C0_RANGE 7:0 +#define DC_WINC_A_V_FILTER_P05_0_A_V_FILTER_P05C0_WOFFSET 0x0 +#define DC_WINC_A_V_FILTER_P05_0_A_V_FILTER_P05C0_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_V_FILTER_P05_0_A_V_FILTER_P05C0_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_V_FILTER_P05_0_A_V_FILTER_P05C0_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_V_FILTER_P05_0_A_V_FILTER_P05C0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_WINC_A_V_FILTER_P06_0 +#define DC_WINC_A_V_FILTER_P06_0 _MK_ADDR_CONST(0x61f) +#define DC_WINC_A_V_FILTER_P06_0_SECURE 0x0 +#define DC_WINC_A_V_FILTER_P06_0_WORD_COUNT 0x1 +#define DC_WINC_A_V_FILTER_P06_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_V_FILTER_P06_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_V_FILTER_P06_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_V_FILTER_P06_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_V_FILTER_P06_0_READ_MASK _MK_MASK_CONST(0xff) +#define DC_WINC_A_V_FILTER_P06_0_WRITE_MASK _MK_MASK_CONST(0xff) +#define DC_WINC_A_V_FILTER_P06_0_A_V_FILTER_P06C0_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_V_FILTER_P06_0_A_V_FILTER_P06C0_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_V_FILTER_P06_0_A_V_FILTER_P06C0_SHIFT) +#define DC_WINC_A_V_FILTER_P06_0_A_V_FILTER_P06C0_RANGE 7:0 +#define DC_WINC_A_V_FILTER_P06_0_A_V_FILTER_P06C0_WOFFSET 0x0 +#define DC_WINC_A_V_FILTER_P06_0_A_V_FILTER_P06C0_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_V_FILTER_P06_0_A_V_FILTER_P06C0_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_V_FILTER_P06_0_A_V_FILTER_P06C0_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_V_FILTER_P06_0_A_V_FILTER_P06C0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_WINC_A_V_FILTER_P07_0 +#define DC_WINC_A_V_FILTER_P07_0 _MK_ADDR_CONST(0x620) +#define DC_WINC_A_V_FILTER_P07_0_SECURE 0x0 +#define DC_WINC_A_V_FILTER_P07_0_WORD_COUNT 0x1 +#define DC_WINC_A_V_FILTER_P07_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_V_FILTER_P07_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_V_FILTER_P07_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_V_FILTER_P07_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_V_FILTER_P07_0_READ_MASK _MK_MASK_CONST(0xff) +#define DC_WINC_A_V_FILTER_P07_0_WRITE_MASK _MK_MASK_CONST(0xff) +#define DC_WINC_A_V_FILTER_P07_0_A_V_FILTER_P07C0_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_V_FILTER_P07_0_A_V_FILTER_P07C0_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_V_FILTER_P07_0_A_V_FILTER_P07C0_SHIFT) +#define DC_WINC_A_V_FILTER_P07_0_A_V_FILTER_P07C0_RANGE 7:0 +#define DC_WINC_A_V_FILTER_P07_0_A_V_FILTER_P07C0_WOFFSET 0x0 +#define DC_WINC_A_V_FILTER_P07_0_A_V_FILTER_P07C0_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_V_FILTER_P07_0_A_V_FILTER_P07C0_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_V_FILTER_P07_0_A_V_FILTER_P07C0_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_V_FILTER_P07_0_A_V_FILTER_P07C0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_WINC_A_V_FILTER_P08_0 +#define DC_WINC_A_V_FILTER_P08_0 _MK_ADDR_CONST(0x621) +#define DC_WINC_A_V_FILTER_P08_0_SECURE 0x0 +#define DC_WINC_A_V_FILTER_P08_0_WORD_COUNT 0x1 +#define DC_WINC_A_V_FILTER_P08_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_V_FILTER_P08_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_V_FILTER_P08_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_V_FILTER_P08_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_V_FILTER_P08_0_READ_MASK _MK_MASK_CONST(0xff) +#define DC_WINC_A_V_FILTER_P08_0_WRITE_MASK _MK_MASK_CONST(0xff) +#define DC_WINC_A_V_FILTER_P08_0_A_V_FILTER_P08C0_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_V_FILTER_P08_0_A_V_FILTER_P08C0_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_V_FILTER_P08_0_A_V_FILTER_P08C0_SHIFT) +#define DC_WINC_A_V_FILTER_P08_0_A_V_FILTER_P08C0_RANGE 7:0 +#define DC_WINC_A_V_FILTER_P08_0_A_V_FILTER_P08C0_WOFFSET 0x0 +#define DC_WINC_A_V_FILTER_P08_0_A_V_FILTER_P08C0_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_V_FILTER_P08_0_A_V_FILTER_P08C0_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_V_FILTER_P08_0_A_V_FILTER_P08C0_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_V_FILTER_P08_0_A_V_FILTER_P08C0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_WINC_A_V_FILTER_P09_0 +#define DC_WINC_A_V_FILTER_P09_0 _MK_ADDR_CONST(0x622) +#define DC_WINC_A_V_FILTER_P09_0_SECURE 0x0 +#define DC_WINC_A_V_FILTER_P09_0_WORD_COUNT 0x1 +#define DC_WINC_A_V_FILTER_P09_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_V_FILTER_P09_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_V_FILTER_P09_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_V_FILTER_P09_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_V_FILTER_P09_0_READ_MASK _MK_MASK_CONST(0xff) +#define DC_WINC_A_V_FILTER_P09_0_WRITE_MASK _MK_MASK_CONST(0xff) +#define DC_WINC_A_V_FILTER_P09_0_A_V_FILTER_P09C0_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_V_FILTER_P09_0_A_V_FILTER_P09C0_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_V_FILTER_P09_0_A_V_FILTER_P09C0_SHIFT) +#define DC_WINC_A_V_FILTER_P09_0_A_V_FILTER_P09C0_RANGE 7:0 +#define DC_WINC_A_V_FILTER_P09_0_A_V_FILTER_P09C0_WOFFSET 0x0 +#define DC_WINC_A_V_FILTER_P09_0_A_V_FILTER_P09C0_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_V_FILTER_P09_0_A_V_FILTER_P09C0_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_V_FILTER_P09_0_A_V_FILTER_P09C0_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_V_FILTER_P09_0_A_V_FILTER_P09C0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_WINC_A_V_FILTER_P0A_0 +#define DC_WINC_A_V_FILTER_P0A_0 _MK_ADDR_CONST(0x623) +#define DC_WINC_A_V_FILTER_P0A_0_SECURE 0x0 +#define DC_WINC_A_V_FILTER_P0A_0_WORD_COUNT 0x1 +#define DC_WINC_A_V_FILTER_P0A_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_V_FILTER_P0A_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_V_FILTER_P0A_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_V_FILTER_P0A_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_V_FILTER_P0A_0_READ_MASK _MK_MASK_CONST(0xff) +#define DC_WINC_A_V_FILTER_P0A_0_WRITE_MASK _MK_MASK_CONST(0xff) +#define DC_WINC_A_V_FILTER_P0A_0_A_V_FILTER_P0AC0_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_V_FILTER_P0A_0_A_V_FILTER_P0AC0_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_V_FILTER_P0A_0_A_V_FILTER_P0AC0_SHIFT) +#define DC_WINC_A_V_FILTER_P0A_0_A_V_FILTER_P0AC0_RANGE 7:0 +#define DC_WINC_A_V_FILTER_P0A_0_A_V_FILTER_P0AC0_WOFFSET 0x0 +#define DC_WINC_A_V_FILTER_P0A_0_A_V_FILTER_P0AC0_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_V_FILTER_P0A_0_A_V_FILTER_P0AC0_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_V_FILTER_P0A_0_A_V_FILTER_P0AC0_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_V_FILTER_P0A_0_A_V_FILTER_P0AC0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_WINC_A_V_FILTER_P0B_0 +#define DC_WINC_A_V_FILTER_P0B_0 _MK_ADDR_CONST(0x624) +#define DC_WINC_A_V_FILTER_P0B_0_SECURE 0x0 +#define DC_WINC_A_V_FILTER_P0B_0_WORD_COUNT 0x1 +#define DC_WINC_A_V_FILTER_P0B_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_V_FILTER_P0B_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_V_FILTER_P0B_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_V_FILTER_P0B_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_V_FILTER_P0B_0_READ_MASK _MK_MASK_CONST(0xff) +#define DC_WINC_A_V_FILTER_P0B_0_WRITE_MASK _MK_MASK_CONST(0xff) +#define DC_WINC_A_V_FILTER_P0B_0_A_V_FILTER_P0BC0_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_V_FILTER_P0B_0_A_V_FILTER_P0BC0_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_V_FILTER_P0B_0_A_V_FILTER_P0BC0_SHIFT) +#define DC_WINC_A_V_FILTER_P0B_0_A_V_FILTER_P0BC0_RANGE 7:0 +#define DC_WINC_A_V_FILTER_P0B_0_A_V_FILTER_P0BC0_WOFFSET 0x0 +#define DC_WINC_A_V_FILTER_P0B_0_A_V_FILTER_P0BC0_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_V_FILTER_P0B_0_A_V_FILTER_P0BC0_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_V_FILTER_P0B_0_A_V_FILTER_P0BC0_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_V_FILTER_P0B_0_A_V_FILTER_P0BC0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_WINC_A_V_FILTER_P0C_0 +#define DC_WINC_A_V_FILTER_P0C_0 _MK_ADDR_CONST(0x625) +#define DC_WINC_A_V_FILTER_P0C_0_SECURE 0x0 +#define DC_WINC_A_V_FILTER_P0C_0_WORD_COUNT 0x1 +#define DC_WINC_A_V_FILTER_P0C_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_V_FILTER_P0C_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_V_FILTER_P0C_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_V_FILTER_P0C_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_V_FILTER_P0C_0_READ_MASK _MK_MASK_CONST(0xff) +#define DC_WINC_A_V_FILTER_P0C_0_WRITE_MASK _MK_MASK_CONST(0xff) +#define DC_WINC_A_V_FILTER_P0C_0_A_V_FILTER_P0CC0_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_V_FILTER_P0C_0_A_V_FILTER_P0CC0_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_V_FILTER_P0C_0_A_V_FILTER_P0CC0_SHIFT) +#define DC_WINC_A_V_FILTER_P0C_0_A_V_FILTER_P0CC0_RANGE 7:0 +#define DC_WINC_A_V_FILTER_P0C_0_A_V_FILTER_P0CC0_WOFFSET 0x0 +#define DC_WINC_A_V_FILTER_P0C_0_A_V_FILTER_P0CC0_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_V_FILTER_P0C_0_A_V_FILTER_P0CC0_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_V_FILTER_P0C_0_A_V_FILTER_P0CC0_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_V_FILTER_P0C_0_A_V_FILTER_P0CC0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_WINC_A_V_FILTER_P0D_0 +#define DC_WINC_A_V_FILTER_P0D_0 _MK_ADDR_CONST(0x626) +#define DC_WINC_A_V_FILTER_P0D_0_SECURE 0x0 +#define DC_WINC_A_V_FILTER_P0D_0_WORD_COUNT 0x1 +#define DC_WINC_A_V_FILTER_P0D_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_V_FILTER_P0D_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_V_FILTER_P0D_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_V_FILTER_P0D_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_V_FILTER_P0D_0_READ_MASK _MK_MASK_CONST(0xff) +#define DC_WINC_A_V_FILTER_P0D_0_WRITE_MASK _MK_MASK_CONST(0xff) +#define DC_WINC_A_V_FILTER_P0D_0_A_V_FILTER_P0DC0_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_V_FILTER_P0D_0_A_V_FILTER_P0DC0_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_V_FILTER_P0D_0_A_V_FILTER_P0DC0_SHIFT) +#define DC_WINC_A_V_FILTER_P0D_0_A_V_FILTER_P0DC0_RANGE 7:0 +#define DC_WINC_A_V_FILTER_P0D_0_A_V_FILTER_P0DC0_WOFFSET 0x0 +#define DC_WINC_A_V_FILTER_P0D_0_A_V_FILTER_P0DC0_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_V_FILTER_P0D_0_A_V_FILTER_P0DC0_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_V_FILTER_P0D_0_A_V_FILTER_P0DC0_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_V_FILTER_P0D_0_A_V_FILTER_P0DC0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_WINC_A_V_FILTER_P0E_0 +#define DC_WINC_A_V_FILTER_P0E_0 _MK_ADDR_CONST(0x627) +#define DC_WINC_A_V_FILTER_P0E_0_SECURE 0x0 +#define DC_WINC_A_V_FILTER_P0E_0_WORD_COUNT 0x1 +#define DC_WINC_A_V_FILTER_P0E_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_V_FILTER_P0E_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_V_FILTER_P0E_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_V_FILTER_P0E_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_V_FILTER_P0E_0_READ_MASK _MK_MASK_CONST(0xff) +#define DC_WINC_A_V_FILTER_P0E_0_WRITE_MASK _MK_MASK_CONST(0xff) +#define DC_WINC_A_V_FILTER_P0E_0_A_V_FILTER_P0EC0_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_V_FILTER_P0E_0_A_V_FILTER_P0EC0_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_V_FILTER_P0E_0_A_V_FILTER_P0EC0_SHIFT) +#define DC_WINC_A_V_FILTER_P0E_0_A_V_FILTER_P0EC0_RANGE 7:0 +#define DC_WINC_A_V_FILTER_P0E_0_A_V_FILTER_P0EC0_WOFFSET 0x0 +#define DC_WINC_A_V_FILTER_P0E_0_A_V_FILTER_P0EC0_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_V_FILTER_P0E_0_A_V_FILTER_P0EC0_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_V_FILTER_P0E_0_A_V_FILTER_P0EC0_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_V_FILTER_P0E_0_A_V_FILTER_P0EC0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_WINC_A_V_FILTER_P0F_0 +#define DC_WINC_A_V_FILTER_P0F_0 _MK_ADDR_CONST(0x628) +#define DC_WINC_A_V_FILTER_P0F_0_SECURE 0x0 +#define DC_WINC_A_V_FILTER_P0F_0_WORD_COUNT 0x1 +#define DC_WINC_A_V_FILTER_P0F_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_V_FILTER_P0F_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_V_FILTER_P0F_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_V_FILTER_P0F_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_V_FILTER_P0F_0_READ_MASK _MK_MASK_CONST(0xff) +#define DC_WINC_A_V_FILTER_P0F_0_WRITE_MASK _MK_MASK_CONST(0xff) +#define DC_WINC_A_V_FILTER_P0F_0_A_V_FILTER_P0FC0_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_V_FILTER_P0F_0_A_V_FILTER_P0FC0_FIELD _MK_FIELD_CONST(0xff, DC_WINC_A_V_FILTER_P0F_0_A_V_FILTER_P0FC0_SHIFT) +#define DC_WINC_A_V_FILTER_P0F_0_A_V_FILTER_P0FC0_RANGE 7:0 +#define DC_WINC_A_V_FILTER_P0F_0_A_V_FILTER_P0FC0_WOFFSET 0x0 +#define DC_WINC_A_V_FILTER_P0F_0_A_V_FILTER_P0FC0_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_V_FILTER_P0F_0_A_V_FILTER_P0FC0_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_V_FILTER_P0F_0_A_V_FILTER_P0FC0_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_V_FILTER_P0F_0_A_V_FILTER_P0FC0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_WINC_A_H_FILTER_HI_P00_0 +#define DC_WINC_A_H_FILTER_HI_P00_0 _MK_ADDR_CONST(0x629) +#define DC_WINC_A_H_FILTER_HI_P00_0_SECURE 0x0 +#define DC_WINC_A_H_FILTER_HI_P00_0_WORD_COUNT 0x1 +#define DC_WINC_A_H_FILTER_HI_P00_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P00_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P00_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P00_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P00_0_READ_MASK _MK_MASK_CONST(0x3ff) +#define DC_WINC_A_H_FILTER_HI_P00_0_WRITE_MASK _MK_MASK_CONST(0x3ff) +#define DC_WINC_A_H_FILTER_HI_P00_0_A_H_FILTER_HI_P00C0_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_H_FILTER_HI_P00_0_A_H_FILTER_HI_P00C0_FIELD _MK_FIELD_CONST(0x3, DC_WINC_A_H_FILTER_HI_P00_0_A_H_FILTER_HI_P00C0_SHIFT) +#define DC_WINC_A_H_FILTER_HI_P00_0_A_H_FILTER_HI_P00C0_RANGE 1:0 +#define DC_WINC_A_H_FILTER_HI_P00_0_A_H_FILTER_HI_P00C0_WOFFSET 0x0 +#define DC_WINC_A_H_FILTER_HI_P00_0_A_H_FILTER_HI_P00C0_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P00_0_A_H_FILTER_HI_P00C0_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P00_0_A_H_FILTER_HI_P00C0_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P00_0_A_H_FILTER_HI_P00C0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_H_FILTER_HI_P00_0_A_H_FILTER_HI_P00C1_SHIFT _MK_SHIFT_CONST(2) +#define DC_WINC_A_H_FILTER_HI_P00_0_A_H_FILTER_HI_P00C1_FIELD _MK_FIELD_CONST(0x3, DC_WINC_A_H_FILTER_HI_P00_0_A_H_FILTER_HI_P00C1_SHIFT) +#define DC_WINC_A_H_FILTER_HI_P00_0_A_H_FILTER_HI_P00C1_RANGE 3:2 +#define DC_WINC_A_H_FILTER_HI_P00_0_A_H_FILTER_HI_P00C1_WOFFSET 0x0 +#define DC_WINC_A_H_FILTER_HI_P00_0_A_H_FILTER_HI_P00C1_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P00_0_A_H_FILTER_HI_P00C1_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P00_0_A_H_FILTER_HI_P00C1_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P00_0_A_H_FILTER_HI_P00C1_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_H_FILTER_HI_P00_0_A_H_FILTER_HI_P00C2_SHIFT _MK_SHIFT_CONST(4) +#define DC_WINC_A_H_FILTER_HI_P00_0_A_H_FILTER_HI_P00C2_FIELD _MK_FIELD_CONST(0x1, DC_WINC_A_H_FILTER_HI_P00_0_A_H_FILTER_HI_P00C2_SHIFT) +#define DC_WINC_A_H_FILTER_HI_P00_0_A_H_FILTER_HI_P00C2_RANGE 4:4 +#define DC_WINC_A_H_FILTER_HI_P00_0_A_H_FILTER_HI_P00C2_WOFFSET 0x0 +#define DC_WINC_A_H_FILTER_HI_P00_0_A_H_FILTER_HI_P00C2_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P00_0_A_H_FILTER_HI_P00C2_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P00_0_A_H_FILTER_HI_P00C2_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P00_0_A_H_FILTER_HI_P00C2_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_H_FILTER_HI_P00_0_A_H_FILTER_HI_P00C3_SHIFT _MK_SHIFT_CONST(5) +#define DC_WINC_A_H_FILTER_HI_P00_0_A_H_FILTER_HI_P00C3_FIELD _MK_FIELD_CONST(0x1, DC_WINC_A_H_FILTER_HI_P00_0_A_H_FILTER_HI_P00C3_SHIFT) +#define DC_WINC_A_H_FILTER_HI_P00_0_A_H_FILTER_HI_P00C3_RANGE 5:5 +#define DC_WINC_A_H_FILTER_HI_P00_0_A_H_FILTER_HI_P00C3_WOFFSET 0x0 +#define DC_WINC_A_H_FILTER_HI_P00_0_A_H_FILTER_HI_P00C3_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P00_0_A_H_FILTER_HI_P00C3_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P00_0_A_H_FILTER_HI_P00C3_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P00_0_A_H_FILTER_HI_P00C3_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_H_FILTER_HI_P00_0_A_H_FILTER_HI_P00C4_SHIFT _MK_SHIFT_CONST(6) +#define DC_WINC_A_H_FILTER_HI_P00_0_A_H_FILTER_HI_P00C4_FIELD _MK_FIELD_CONST(0x3, DC_WINC_A_H_FILTER_HI_P00_0_A_H_FILTER_HI_P00C4_SHIFT) +#define DC_WINC_A_H_FILTER_HI_P00_0_A_H_FILTER_HI_P00C4_RANGE 7:6 +#define DC_WINC_A_H_FILTER_HI_P00_0_A_H_FILTER_HI_P00C4_WOFFSET 0x0 +#define DC_WINC_A_H_FILTER_HI_P00_0_A_H_FILTER_HI_P00C4_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P00_0_A_H_FILTER_HI_P00C4_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P00_0_A_H_FILTER_HI_P00C4_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P00_0_A_H_FILTER_HI_P00C4_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_H_FILTER_HI_P00_0_A_H_FILTER_HI_P00C5_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_H_FILTER_HI_P00_0_A_H_FILTER_HI_P00C5_FIELD _MK_FIELD_CONST(0x3, DC_WINC_A_H_FILTER_HI_P00_0_A_H_FILTER_HI_P00C5_SHIFT) +#define DC_WINC_A_H_FILTER_HI_P00_0_A_H_FILTER_HI_P00C5_RANGE 9:8 +#define DC_WINC_A_H_FILTER_HI_P00_0_A_H_FILTER_HI_P00C5_WOFFSET 0x0 +#define DC_WINC_A_H_FILTER_HI_P00_0_A_H_FILTER_HI_P00C5_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P00_0_A_H_FILTER_HI_P00C5_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P00_0_A_H_FILTER_HI_P00C5_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P00_0_A_H_FILTER_HI_P00C5_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_WINC_A_H_FILTER_HI_P01_0 +#define DC_WINC_A_H_FILTER_HI_P01_0 _MK_ADDR_CONST(0x62a) +#define DC_WINC_A_H_FILTER_HI_P01_0_SECURE 0x0 +#define DC_WINC_A_H_FILTER_HI_P01_0_WORD_COUNT 0x1 +#define DC_WINC_A_H_FILTER_HI_P01_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P01_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P01_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P01_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P01_0_READ_MASK _MK_MASK_CONST(0x3ff) +#define DC_WINC_A_H_FILTER_HI_P01_0_WRITE_MASK _MK_MASK_CONST(0x3ff) +#define DC_WINC_A_H_FILTER_HI_P01_0_A_H_FILTER_HI_P01C0_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_H_FILTER_HI_P01_0_A_H_FILTER_HI_P01C0_FIELD _MK_FIELD_CONST(0x3, DC_WINC_A_H_FILTER_HI_P01_0_A_H_FILTER_HI_P01C0_SHIFT) +#define DC_WINC_A_H_FILTER_HI_P01_0_A_H_FILTER_HI_P01C0_RANGE 1:0 +#define DC_WINC_A_H_FILTER_HI_P01_0_A_H_FILTER_HI_P01C0_WOFFSET 0x0 +#define DC_WINC_A_H_FILTER_HI_P01_0_A_H_FILTER_HI_P01C0_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P01_0_A_H_FILTER_HI_P01C0_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P01_0_A_H_FILTER_HI_P01C0_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P01_0_A_H_FILTER_HI_P01C0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_H_FILTER_HI_P01_0_A_H_FILTER_HI_P01C1_SHIFT _MK_SHIFT_CONST(2) +#define DC_WINC_A_H_FILTER_HI_P01_0_A_H_FILTER_HI_P01C1_FIELD _MK_FIELD_CONST(0x3, DC_WINC_A_H_FILTER_HI_P01_0_A_H_FILTER_HI_P01C1_SHIFT) +#define DC_WINC_A_H_FILTER_HI_P01_0_A_H_FILTER_HI_P01C1_RANGE 3:2 +#define DC_WINC_A_H_FILTER_HI_P01_0_A_H_FILTER_HI_P01C1_WOFFSET 0x0 +#define DC_WINC_A_H_FILTER_HI_P01_0_A_H_FILTER_HI_P01C1_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P01_0_A_H_FILTER_HI_P01C1_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P01_0_A_H_FILTER_HI_P01C1_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P01_0_A_H_FILTER_HI_P01C1_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_H_FILTER_HI_P01_0_A_H_FILTER_HI_P01C2_SHIFT _MK_SHIFT_CONST(4) +#define DC_WINC_A_H_FILTER_HI_P01_0_A_H_FILTER_HI_P01C2_FIELD _MK_FIELD_CONST(0x1, DC_WINC_A_H_FILTER_HI_P01_0_A_H_FILTER_HI_P01C2_SHIFT) +#define DC_WINC_A_H_FILTER_HI_P01_0_A_H_FILTER_HI_P01C2_RANGE 4:4 +#define DC_WINC_A_H_FILTER_HI_P01_0_A_H_FILTER_HI_P01C2_WOFFSET 0x0 +#define DC_WINC_A_H_FILTER_HI_P01_0_A_H_FILTER_HI_P01C2_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P01_0_A_H_FILTER_HI_P01C2_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P01_0_A_H_FILTER_HI_P01C2_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P01_0_A_H_FILTER_HI_P01C2_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_H_FILTER_HI_P01_0_A_H_FILTER_HI_P01C3_SHIFT _MK_SHIFT_CONST(5) +#define DC_WINC_A_H_FILTER_HI_P01_0_A_H_FILTER_HI_P01C3_FIELD _MK_FIELD_CONST(0x1, DC_WINC_A_H_FILTER_HI_P01_0_A_H_FILTER_HI_P01C3_SHIFT) +#define DC_WINC_A_H_FILTER_HI_P01_0_A_H_FILTER_HI_P01C3_RANGE 5:5 +#define DC_WINC_A_H_FILTER_HI_P01_0_A_H_FILTER_HI_P01C3_WOFFSET 0x0 +#define DC_WINC_A_H_FILTER_HI_P01_0_A_H_FILTER_HI_P01C3_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P01_0_A_H_FILTER_HI_P01C3_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P01_0_A_H_FILTER_HI_P01C3_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P01_0_A_H_FILTER_HI_P01C3_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_H_FILTER_HI_P01_0_A_H_FILTER_HI_P01C4_SHIFT _MK_SHIFT_CONST(6) +#define DC_WINC_A_H_FILTER_HI_P01_0_A_H_FILTER_HI_P01C4_FIELD _MK_FIELD_CONST(0x3, DC_WINC_A_H_FILTER_HI_P01_0_A_H_FILTER_HI_P01C4_SHIFT) +#define DC_WINC_A_H_FILTER_HI_P01_0_A_H_FILTER_HI_P01C4_RANGE 7:6 +#define DC_WINC_A_H_FILTER_HI_P01_0_A_H_FILTER_HI_P01C4_WOFFSET 0x0 +#define DC_WINC_A_H_FILTER_HI_P01_0_A_H_FILTER_HI_P01C4_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P01_0_A_H_FILTER_HI_P01C4_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P01_0_A_H_FILTER_HI_P01C4_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P01_0_A_H_FILTER_HI_P01C4_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_H_FILTER_HI_P01_0_A_H_FILTER_HI_P01C5_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_H_FILTER_HI_P01_0_A_H_FILTER_HI_P01C5_FIELD _MK_FIELD_CONST(0x3, DC_WINC_A_H_FILTER_HI_P01_0_A_H_FILTER_HI_P01C5_SHIFT) +#define DC_WINC_A_H_FILTER_HI_P01_0_A_H_FILTER_HI_P01C5_RANGE 9:8 +#define DC_WINC_A_H_FILTER_HI_P01_0_A_H_FILTER_HI_P01C5_WOFFSET 0x0 +#define DC_WINC_A_H_FILTER_HI_P01_0_A_H_FILTER_HI_P01C5_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P01_0_A_H_FILTER_HI_P01C5_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P01_0_A_H_FILTER_HI_P01C5_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P01_0_A_H_FILTER_HI_P01C5_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_WINC_A_H_FILTER_HI_P02_0 +#define DC_WINC_A_H_FILTER_HI_P02_0 _MK_ADDR_CONST(0x62b) +#define DC_WINC_A_H_FILTER_HI_P02_0_SECURE 0x0 +#define DC_WINC_A_H_FILTER_HI_P02_0_WORD_COUNT 0x1 +#define DC_WINC_A_H_FILTER_HI_P02_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P02_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P02_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P02_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P02_0_READ_MASK _MK_MASK_CONST(0x3ff) +#define DC_WINC_A_H_FILTER_HI_P02_0_WRITE_MASK _MK_MASK_CONST(0x3ff) +#define DC_WINC_A_H_FILTER_HI_P02_0_A_H_FILTER_HI_P02C0_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_H_FILTER_HI_P02_0_A_H_FILTER_HI_P02C0_FIELD _MK_FIELD_CONST(0x3, DC_WINC_A_H_FILTER_HI_P02_0_A_H_FILTER_HI_P02C0_SHIFT) +#define DC_WINC_A_H_FILTER_HI_P02_0_A_H_FILTER_HI_P02C0_RANGE 1:0 +#define DC_WINC_A_H_FILTER_HI_P02_0_A_H_FILTER_HI_P02C0_WOFFSET 0x0 +#define DC_WINC_A_H_FILTER_HI_P02_0_A_H_FILTER_HI_P02C0_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P02_0_A_H_FILTER_HI_P02C0_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P02_0_A_H_FILTER_HI_P02C0_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P02_0_A_H_FILTER_HI_P02C0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_H_FILTER_HI_P02_0_A_H_FILTER_HI_P02C1_SHIFT _MK_SHIFT_CONST(2) +#define DC_WINC_A_H_FILTER_HI_P02_0_A_H_FILTER_HI_P02C1_FIELD _MK_FIELD_CONST(0x3, DC_WINC_A_H_FILTER_HI_P02_0_A_H_FILTER_HI_P02C1_SHIFT) +#define DC_WINC_A_H_FILTER_HI_P02_0_A_H_FILTER_HI_P02C1_RANGE 3:2 +#define DC_WINC_A_H_FILTER_HI_P02_0_A_H_FILTER_HI_P02C1_WOFFSET 0x0 +#define DC_WINC_A_H_FILTER_HI_P02_0_A_H_FILTER_HI_P02C1_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P02_0_A_H_FILTER_HI_P02C1_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P02_0_A_H_FILTER_HI_P02C1_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P02_0_A_H_FILTER_HI_P02C1_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_H_FILTER_HI_P02_0_A_H_FILTER_HI_P02C2_SHIFT _MK_SHIFT_CONST(4) +#define DC_WINC_A_H_FILTER_HI_P02_0_A_H_FILTER_HI_P02C2_FIELD _MK_FIELD_CONST(0x1, DC_WINC_A_H_FILTER_HI_P02_0_A_H_FILTER_HI_P02C2_SHIFT) +#define DC_WINC_A_H_FILTER_HI_P02_0_A_H_FILTER_HI_P02C2_RANGE 4:4 +#define DC_WINC_A_H_FILTER_HI_P02_0_A_H_FILTER_HI_P02C2_WOFFSET 0x0 +#define DC_WINC_A_H_FILTER_HI_P02_0_A_H_FILTER_HI_P02C2_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P02_0_A_H_FILTER_HI_P02C2_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P02_0_A_H_FILTER_HI_P02C2_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P02_0_A_H_FILTER_HI_P02C2_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_H_FILTER_HI_P02_0_A_H_FILTER_HI_P02C3_SHIFT _MK_SHIFT_CONST(5) +#define DC_WINC_A_H_FILTER_HI_P02_0_A_H_FILTER_HI_P02C3_FIELD _MK_FIELD_CONST(0x1, DC_WINC_A_H_FILTER_HI_P02_0_A_H_FILTER_HI_P02C3_SHIFT) +#define DC_WINC_A_H_FILTER_HI_P02_0_A_H_FILTER_HI_P02C3_RANGE 5:5 +#define DC_WINC_A_H_FILTER_HI_P02_0_A_H_FILTER_HI_P02C3_WOFFSET 0x0 +#define DC_WINC_A_H_FILTER_HI_P02_0_A_H_FILTER_HI_P02C3_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P02_0_A_H_FILTER_HI_P02C3_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P02_0_A_H_FILTER_HI_P02C3_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P02_0_A_H_FILTER_HI_P02C3_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_H_FILTER_HI_P02_0_A_H_FILTER_HI_P02C4_SHIFT _MK_SHIFT_CONST(6) +#define DC_WINC_A_H_FILTER_HI_P02_0_A_H_FILTER_HI_P02C4_FIELD _MK_FIELD_CONST(0x3, DC_WINC_A_H_FILTER_HI_P02_0_A_H_FILTER_HI_P02C4_SHIFT) +#define DC_WINC_A_H_FILTER_HI_P02_0_A_H_FILTER_HI_P02C4_RANGE 7:6 +#define DC_WINC_A_H_FILTER_HI_P02_0_A_H_FILTER_HI_P02C4_WOFFSET 0x0 +#define DC_WINC_A_H_FILTER_HI_P02_0_A_H_FILTER_HI_P02C4_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P02_0_A_H_FILTER_HI_P02C4_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P02_0_A_H_FILTER_HI_P02C4_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P02_0_A_H_FILTER_HI_P02C4_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_H_FILTER_HI_P02_0_A_H_FILTER_HI_P02C5_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_H_FILTER_HI_P02_0_A_H_FILTER_HI_P02C5_FIELD _MK_FIELD_CONST(0x3, DC_WINC_A_H_FILTER_HI_P02_0_A_H_FILTER_HI_P02C5_SHIFT) +#define DC_WINC_A_H_FILTER_HI_P02_0_A_H_FILTER_HI_P02C5_RANGE 9:8 +#define DC_WINC_A_H_FILTER_HI_P02_0_A_H_FILTER_HI_P02C5_WOFFSET 0x0 +#define DC_WINC_A_H_FILTER_HI_P02_0_A_H_FILTER_HI_P02C5_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P02_0_A_H_FILTER_HI_P02C5_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P02_0_A_H_FILTER_HI_P02C5_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P02_0_A_H_FILTER_HI_P02C5_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_WINC_A_H_FILTER_HI_P03_0 +#define DC_WINC_A_H_FILTER_HI_P03_0 _MK_ADDR_CONST(0x62c) +#define DC_WINC_A_H_FILTER_HI_P03_0_SECURE 0x0 +#define DC_WINC_A_H_FILTER_HI_P03_0_WORD_COUNT 0x1 +#define DC_WINC_A_H_FILTER_HI_P03_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P03_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P03_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P03_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P03_0_READ_MASK _MK_MASK_CONST(0x3ff) +#define DC_WINC_A_H_FILTER_HI_P03_0_WRITE_MASK _MK_MASK_CONST(0x3ff) +#define DC_WINC_A_H_FILTER_HI_P03_0_A_H_FILTER_HI_P03C0_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_H_FILTER_HI_P03_0_A_H_FILTER_HI_P03C0_FIELD _MK_FIELD_CONST(0x3, DC_WINC_A_H_FILTER_HI_P03_0_A_H_FILTER_HI_P03C0_SHIFT) +#define DC_WINC_A_H_FILTER_HI_P03_0_A_H_FILTER_HI_P03C0_RANGE 1:0 +#define DC_WINC_A_H_FILTER_HI_P03_0_A_H_FILTER_HI_P03C0_WOFFSET 0x0 +#define DC_WINC_A_H_FILTER_HI_P03_0_A_H_FILTER_HI_P03C0_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P03_0_A_H_FILTER_HI_P03C0_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P03_0_A_H_FILTER_HI_P03C0_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P03_0_A_H_FILTER_HI_P03C0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_H_FILTER_HI_P03_0_A_H_FILTER_HI_P03C1_SHIFT _MK_SHIFT_CONST(2) +#define DC_WINC_A_H_FILTER_HI_P03_0_A_H_FILTER_HI_P03C1_FIELD _MK_FIELD_CONST(0x3, DC_WINC_A_H_FILTER_HI_P03_0_A_H_FILTER_HI_P03C1_SHIFT) +#define DC_WINC_A_H_FILTER_HI_P03_0_A_H_FILTER_HI_P03C1_RANGE 3:2 +#define DC_WINC_A_H_FILTER_HI_P03_0_A_H_FILTER_HI_P03C1_WOFFSET 0x0 +#define DC_WINC_A_H_FILTER_HI_P03_0_A_H_FILTER_HI_P03C1_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P03_0_A_H_FILTER_HI_P03C1_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P03_0_A_H_FILTER_HI_P03C1_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P03_0_A_H_FILTER_HI_P03C1_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_H_FILTER_HI_P03_0_A_H_FILTER_HI_P03C2_SHIFT _MK_SHIFT_CONST(4) +#define DC_WINC_A_H_FILTER_HI_P03_0_A_H_FILTER_HI_P03C2_FIELD _MK_FIELD_CONST(0x1, DC_WINC_A_H_FILTER_HI_P03_0_A_H_FILTER_HI_P03C2_SHIFT) +#define DC_WINC_A_H_FILTER_HI_P03_0_A_H_FILTER_HI_P03C2_RANGE 4:4 +#define DC_WINC_A_H_FILTER_HI_P03_0_A_H_FILTER_HI_P03C2_WOFFSET 0x0 +#define DC_WINC_A_H_FILTER_HI_P03_0_A_H_FILTER_HI_P03C2_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P03_0_A_H_FILTER_HI_P03C2_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P03_0_A_H_FILTER_HI_P03C2_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P03_0_A_H_FILTER_HI_P03C2_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_H_FILTER_HI_P03_0_A_H_FILTER_HI_P03C3_SHIFT _MK_SHIFT_CONST(5) +#define DC_WINC_A_H_FILTER_HI_P03_0_A_H_FILTER_HI_P03C3_FIELD _MK_FIELD_CONST(0x1, DC_WINC_A_H_FILTER_HI_P03_0_A_H_FILTER_HI_P03C3_SHIFT) +#define DC_WINC_A_H_FILTER_HI_P03_0_A_H_FILTER_HI_P03C3_RANGE 5:5 +#define DC_WINC_A_H_FILTER_HI_P03_0_A_H_FILTER_HI_P03C3_WOFFSET 0x0 +#define DC_WINC_A_H_FILTER_HI_P03_0_A_H_FILTER_HI_P03C3_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P03_0_A_H_FILTER_HI_P03C3_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P03_0_A_H_FILTER_HI_P03C3_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P03_0_A_H_FILTER_HI_P03C3_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_H_FILTER_HI_P03_0_A_H_FILTER_HI_P03C4_SHIFT _MK_SHIFT_CONST(6) +#define DC_WINC_A_H_FILTER_HI_P03_0_A_H_FILTER_HI_P03C4_FIELD _MK_FIELD_CONST(0x3, DC_WINC_A_H_FILTER_HI_P03_0_A_H_FILTER_HI_P03C4_SHIFT) +#define DC_WINC_A_H_FILTER_HI_P03_0_A_H_FILTER_HI_P03C4_RANGE 7:6 +#define DC_WINC_A_H_FILTER_HI_P03_0_A_H_FILTER_HI_P03C4_WOFFSET 0x0 +#define DC_WINC_A_H_FILTER_HI_P03_0_A_H_FILTER_HI_P03C4_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P03_0_A_H_FILTER_HI_P03C4_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P03_0_A_H_FILTER_HI_P03C4_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P03_0_A_H_FILTER_HI_P03C4_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_H_FILTER_HI_P03_0_A_H_FILTER_HI_P03C5_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_H_FILTER_HI_P03_0_A_H_FILTER_HI_P03C5_FIELD _MK_FIELD_CONST(0x3, DC_WINC_A_H_FILTER_HI_P03_0_A_H_FILTER_HI_P03C5_SHIFT) +#define DC_WINC_A_H_FILTER_HI_P03_0_A_H_FILTER_HI_P03C5_RANGE 9:8 +#define DC_WINC_A_H_FILTER_HI_P03_0_A_H_FILTER_HI_P03C5_WOFFSET 0x0 +#define DC_WINC_A_H_FILTER_HI_P03_0_A_H_FILTER_HI_P03C5_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P03_0_A_H_FILTER_HI_P03C5_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P03_0_A_H_FILTER_HI_P03C5_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P03_0_A_H_FILTER_HI_P03C5_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_WINC_A_H_FILTER_HI_P04_0 +#define DC_WINC_A_H_FILTER_HI_P04_0 _MK_ADDR_CONST(0x62d) +#define DC_WINC_A_H_FILTER_HI_P04_0_SECURE 0x0 +#define DC_WINC_A_H_FILTER_HI_P04_0_WORD_COUNT 0x1 +#define DC_WINC_A_H_FILTER_HI_P04_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P04_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P04_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P04_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P04_0_READ_MASK _MK_MASK_CONST(0x3ff) +#define DC_WINC_A_H_FILTER_HI_P04_0_WRITE_MASK _MK_MASK_CONST(0x3ff) +#define DC_WINC_A_H_FILTER_HI_P04_0_A_H_FILTER_HI_P04C0_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_H_FILTER_HI_P04_0_A_H_FILTER_HI_P04C0_FIELD _MK_FIELD_CONST(0x3, DC_WINC_A_H_FILTER_HI_P04_0_A_H_FILTER_HI_P04C0_SHIFT) +#define DC_WINC_A_H_FILTER_HI_P04_0_A_H_FILTER_HI_P04C0_RANGE 1:0 +#define DC_WINC_A_H_FILTER_HI_P04_0_A_H_FILTER_HI_P04C0_WOFFSET 0x0 +#define DC_WINC_A_H_FILTER_HI_P04_0_A_H_FILTER_HI_P04C0_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P04_0_A_H_FILTER_HI_P04C0_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P04_0_A_H_FILTER_HI_P04C0_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P04_0_A_H_FILTER_HI_P04C0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_H_FILTER_HI_P04_0_A_H_FILTER_HI_P04C1_SHIFT _MK_SHIFT_CONST(2) +#define DC_WINC_A_H_FILTER_HI_P04_0_A_H_FILTER_HI_P04C1_FIELD _MK_FIELD_CONST(0x3, DC_WINC_A_H_FILTER_HI_P04_0_A_H_FILTER_HI_P04C1_SHIFT) +#define DC_WINC_A_H_FILTER_HI_P04_0_A_H_FILTER_HI_P04C1_RANGE 3:2 +#define DC_WINC_A_H_FILTER_HI_P04_0_A_H_FILTER_HI_P04C1_WOFFSET 0x0 +#define DC_WINC_A_H_FILTER_HI_P04_0_A_H_FILTER_HI_P04C1_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P04_0_A_H_FILTER_HI_P04C1_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P04_0_A_H_FILTER_HI_P04C1_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P04_0_A_H_FILTER_HI_P04C1_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_H_FILTER_HI_P04_0_A_H_FILTER_HI_P04C2_SHIFT _MK_SHIFT_CONST(4) +#define DC_WINC_A_H_FILTER_HI_P04_0_A_H_FILTER_HI_P04C2_FIELD _MK_FIELD_CONST(0x1, DC_WINC_A_H_FILTER_HI_P04_0_A_H_FILTER_HI_P04C2_SHIFT) +#define DC_WINC_A_H_FILTER_HI_P04_0_A_H_FILTER_HI_P04C2_RANGE 4:4 +#define DC_WINC_A_H_FILTER_HI_P04_0_A_H_FILTER_HI_P04C2_WOFFSET 0x0 +#define DC_WINC_A_H_FILTER_HI_P04_0_A_H_FILTER_HI_P04C2_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P04_0_A_H_FILTER_HI_P04C2_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P04_0_A_H_FILTER_HI_P04C2_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P04_0_A_H_FILTER_HI_P04C2_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_H_FILTER_HI_P04_0_A_H_FILTER_HI_P04C3_SHIFT _MK_SHIFT_CONST(5) +#define DC_WINC_A_H_FILTER_HI_P04_0_A_H_FILTER_HI_P04C3_FIELD _MK_FIELD_CONST(0x1, DC_WINC_A_H_FILTER_HI_P04_0_A_H_FILTER_HI_P04C3_SHIFT) +#define DC_WINC_A_H_FILTER_HI_P04_0_A_H_FILTER_HI_P04C3_RANGE 5:5 +#define DC_WINC_A_H_FILTER_HI_P04_0_A_H_FILTER_HI_P04C3_WOFFSET 0x0 +#define DC_WINC_A_H_FILTER_HI_P04_0_A_H_FILTER_HI_P04C3_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P04_0_A_H_FILTER_HI_P04C3_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P04_0_A_H_FILTER_HI_P04C3_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P04_0_A_H_FILTER_HI_P04C3_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_H_FILTER_HI_P04_0_A_H_FILTER_HI_P04C4_SHIFT _MK_SHIFT_CONST(6) +#define DC_WINC_A_H_FILTER_HI_P04_0_A_H_FILTER_HI_P04C4_FIELD _MK_FIELD_CONST(0x3, DC_WINC_A_H_FILTER_HI_P04_0_A_H_FILTER_HI_P04C4_SHIFT) +#define DC_WINC_A_H_FILTER_HI_P04_0_A_H_FILTER_HI_P04C4_RANGE 7:6 +#define DC_WINC_A_H_FILTER_HI_P04_0_A_H_FILTER_HI_P04C4_WOFFSET 0x0 +#define DC_WINC_A_H_FILTER_HI_P04_0_A_H_FILTER_HI_P04C4_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P04_0_A_H_FILTER_HI_P04C4_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P04_0_A_H_FILTER_HI_P04C4_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P04_0_A_H_FILTER_HI_P04C4_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_H_FILTER_HI_P04_0_A_H_FILTER_HI_P04C5_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_H_FILTER_HI_P04_0_A_H_FILTER_HI_P04C5_FIELD _MK_FIELD_CONST(0x3, DC_WINC_A_H_FILTER_HI_P04_0_A_H_FILTER_HI_P04C5_SHIFT) +#define DC_WINC_A_H_FILTER_HI_P04_0_A_H_FILTER_HI_P04C5_RANGE 9:8 +#define DC_WINC_A_H_FILTER_HI_P04_0_A_H_FILTER_HI_P04C5_WOFFSET 0x0 +#define DC_WINC_A_H_FILTER_HI_P04_0_A_H_FILTER_HI_P04C5_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P04_0_A_H_FILTER_HI_P04C5_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P04_0_A_H_FILTER_HI_P04C5_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P04_0_A_H_FILTER_HI_P04C5_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_WINC_A_H_FILTER_HI_P05_0 +#define DC_WINC_A_H_FILTER_HI_P05_0 _MK_ADDR_CONST(0x62e) +#define DC_WINC_A_H_FILTER_HI_P05_0_SECURE 0x0 +#define DC_WINC_A_H_FILTER_HI_P05_0_WORD_COUNT 0x1 +#define DC_WINC_A_H_FILTER_HI_P05_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P05_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P05_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P05_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P05_0_READ_MASK _MK_MASK_CONST(0x3ff) +#define DC_WINC_A_H_FILTER_HI_P05_0_WRITE_MASK _MK_MASK_CONST(0x3ff) +#define DC_WINC_A_H_FILTER_HI_P05_0_A_H_FILTER_HI_P05C0_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_H_FILTER_HI_P05_0_A_H_FILTER_HI_P05C0_FIELD _MK_FIELD_CONST(0x3, DC_WINC_A_H_FILTER_HI_P05_0_A_H_FILTER_HI_P05C0_SHIFT) +#define DC_WINC_A_H_FILTER_HI_P05_0_A_H_FILTER_HI_P05C0_RANGE 1:0 +#define DC_WINC_A_H_FILTER_HI_P05_0_A_H_FILTER_HI_P05C0_WOFFSET 0x0 +#define DC_WINC_A_H_FILTER_HI_P05_0_A_H_FILTER_HI_P05C0_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P05_0_A_H_FILTER_HI_P05C0_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P05_0_A_H_FILTER_HI_P05C0_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P05_0_A_H_FILTER_HI_P05C0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_H_FILTER_HI_P05_0_A_H_FILTER_HI_P05C1_SHIFT _MK_SHIFT_CONST(2) +#define DC_WINC_A_H_FILTER_HI_P05_0_A_H_FILTER_HI_P05C1_FIELD _MK_FIELD_CONST(0x3, DC_WINC_A_H_FILTER_HI_P05_0_A_H_FILTER_HI_P05C1_SHIFT) +#define DC_WINC_A_H_FILTER_HI_P05_0_A_H_FILTER_HI_P05C1_RANGE 3:2 +#define DC_WINC_A_H_FILTER_HI_P05_0_A_H_FILTER_HI_P05C1_WOFFSET 0x0 +#define DC_WINC_A_H_FILTER_HI_P05_0_A_H_FILTER_HI_P05C1_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P05_0_A_H_FILTER_HI_P05C1_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P05_0_A_H_FILTER_HI_P05C1_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P05_0_A_H_FILTER_HI_P05C1_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_H_FILTER_HI_P05_0_A_H_FILTER_HI_P05C2_SHIFT _MK_SHIFT_CONST(4) +#define DC_WINC_A_H_FILTER_HI_P05_0_A_H_FILTER_HI_P05C2_FIELD _MK_FIELD_CONST(0x1, DC_WINC_A_H_FILTER_HI_P05_0_A_H_FILTER_HI_P05C2_SHIFT) +#define DC_WINC_A_H_FILTER_HI_P05_0_A_H_FILTER_HI_P05C2_RANGE 4:4 +#define DC_WINC_A_H_FILTER_HI_P05_0_A_H_FILTER_HI_P05C2_WOFFSET 0x0 +#define DC_WINC_A_H_FILTER_HI_P05_0_A_H_FILTER_HI_P05C2_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P05_0_A_H_FILTER_HI_P05C2_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P05_0_A_H_FILTER_HI_P05C2_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P05_0_A_H_FILTER_HI_P05C2_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_H_FILTER_HI_P05_0_A_H_FILTER_HI_P05C3_SHIFT _MK_SHIFT_CONST(5) +#define DC_WINC_A_H_FILTER_HI_P05_0_A_H_FILTER_HI_P05C3_FIELD _MK_FIELD_CONST(0x1, DC_WINC_A_H_FILTER_HI_P05_0_A_H_FILTER_HI_P05C3_SHIFT) +#define DC_WINC_A_H_FILTER_HI_P05_0_A_H_FILTER_HI_P05C3_RANGE 5:5 +#define DC_WINC_A_H_FILTER_HI_P05_0_A_H_FILTER_HI_P05C3_WOFFSET 0x0 +#define DC_WINC_A_H_FILTER_HI_P05_0_A_H_FILTER_HI_P05C3_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P05_0_A_H_FILTER_HI_P05C3_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P05_0_A_H_FILTER_HI_P05C3_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P05_0_A_H_FILTER_HI_P05C3_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_H_FILTER_HI_P05_0_A_H_FILTER_HI_P05C4_SHIFT _MK_SHIFT_CONST(6) +#define DC_WINC_A_H_FILTER_HI_P05_0_A_H_FILTER_HI_P05C4_FIELD _MK_FIELD_CONST(0x3, DC_WINC_A_H_FILTER_HI_P05_0_A_H_FILTER_HI_P05C4_SHIFT) +#define DC_WINC_A_H_FILTER_HI_P05_0_A_H_FILTER_HI_P05C4_RANGE 7:6 +#define DC_WINC_A_H_FILTER_HI_P05_0_A_H_FILTER_HI_P05C4_WOFFSET 0x0 +#define DC_WINC_A_H_FILTER_HI_P05_0_A_H_FILTER_HI_P05C4_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P05_0_A_H_FILTER_HI_P05C4_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P05_0_A_H_FILTER_HI_P05C4_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P05_0_A_H_FILTER_HI_P05C4_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_H_FILTER_HI_P05_0_A_H_FILTER_HI_P05C5_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_H_FILTER_HI_P05_0_A_H_FILTER_HI_P05C5_FIELD _MK_FIELD_CONST(0x3, DC_WINC_A_H_FILTER_HI_P05_0_A_H_FILTER_HI_P05C5_SHIFT) +#define DC_WINC_A_H_FILTER_HI_P05_0_A_H_FILTER_HI_P05C5_RANGE 9:8 +#define DC_WINC_A_H_FILTER_HI_P05_0_A_H_FILTER_HI_P05C5_WOFFSET 0x0 +#define DC_WINC_A_H_FILTER_HI_P05_0_A_H_FILTER_HI_P05C5_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P05_0_A_H_FILTER_HI_P05C5_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P05_0_A_H_FILTER_HI_P05C5_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P05_0_A_H_FILTER_HI_P05C5_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_WINC_A_H_FILTER_HI_P06_0 +#define DC_WINC_A_H_FILTER_HI_P06_0 _MK_ADDR_CONST(0x62f) +#define DC_WINC_A_H_FILTER_HI_P06_0_SECURE 0x0 +#define DC_WINC_A_H_FILTER_HI_P06_0_WORD_COUNT 0x1 +#define DC_WINC_A_H_FILTER_HI_P06_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P06_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P06_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P06_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P06_0_READ_MASK _MK_MASK_CONST(0x3ff) +#define DC_WINC_A_H_FILTER_HI_P06_0_WRITE_MASK _MK_MASK_CONST(0x3ff) +#define DC_WINC_A_H_FILTER_HI_P06_0_A_H_FILTER_HI_P06C0_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_H_FILTER_HI_P06_0_A_H_FILTER_HI_P06C0_FIELD _MK_FIELD_CONST(0x3, DC_WINC_A_H_FILTER_HI_P06_0_A_H_FILTER_HI_P06C0_SHIFT) +#define DC_WINC_A_H_FILTER_HI_P06_0_A_H_FILTER_HI_P06C0_RANGE 1:0 +#define DC_WINC_A_H_FILTER_HI_P06_0_A_H_FILTER_HI_P06C0_WOFFSET 0x0 +#define DC_WINC_A_H_FILTER_HI_P06_0_A_H_FILTER_HI_P06C0_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P06_0_A_H_FILTER_HI_P06C0_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P06_0_A_H_FILTER_HI_P06C0_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P06_0_A_H_FILTER_HI_P06C0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_H_FILTER_HI_P06_0_A_H_FILTER_HI_P06C1_SHIFT _MK_SHIFT_CONST(2) +#define DC_WINC_A_H_FILTER_HI_P06_0_A_H_FILTER_HI_P06C1_FIELD _MK_FIELD_CONST(0x3, DC_WINC_A_H_FILTER_HI_P06_0_A_H_FILTER_HI_P06C1_SHIFT) +#define DC_WINC_A_H_FILTER_HI_P06_0_A_H_FILTER_HI_P06C1_RANGE 3:2 +#define DC_WINC_A_H_FILTER_HI_P06_0_A_H_FILTER_HI_P06C1_WOFFSET 0x0 +#define DC_WINC_A_H_FILTER_HI_P06_0_A_H_FILTER_HI_P06C1_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P06_0_A_H_FILTER_HI_P06C1_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P06_0_A_H_FILTER_HI_P06C1_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P06_0_A_H_FILTER_HI_P06C1_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_H_FILTER_HI_P06_0_A_H_FILTER_HI_P06C2_SHIFT _MK_SHIFT_CONST(4) +#define DC_WINC_A_H_FILTER_HI_P06_0_A_H_FILTER_HI_P06C2_FIELD _MK_FIELD_CONST(0x1, DC_WINC_A_H_FILTER_HI_P06_0_A_H_FILTER_HI_P06C2_SHIFT) +#define DC_WINC_A_H_FILTER_HI_P06_0_A_H_FILTER_HI_P06C2_RANGE 4:4 +#define DC_WINC_A_H_FILTER_HI_P06_0_A_H_FILTER_HI_P06C2_WOFFSET 0x0 +#define DC_WINC_A_H_FILTER_HI_P06_0_A_H_FILTER_HI_P06C2_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P06_0_A_H_FILTER_HI_P06C2_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P06_0_A_H_FILTER_HI_P06C2_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P06_0_A_H_FILTER_HI_P06C2_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_H_FILTER_HI_P06_0_A_H_FILTER_HI_P06C3_SHIFT _MK_SHIFT_CONST(5) +#define DC_WINC_A_H_FILTER_HI_P06_0_A_H_FILTER_HI_P06C3_FIELD _MK_FIELD_CONST(0x1, DC_WINC_A_H_FILTER_HI_P06_0_A_H_FILTER_HI_P06C3_SHIFT) +#define DC_WINC_A_H_FILTER_HI_P06_0_A_H_FILTER_HI_P06C3_RANGE 5:5 +#define DC_WINC_A_H_FILTER_HI_P06_0_A_H_FILTER_HI_P06C3_WOFFSET 0x0 +#define DC_WINC_A_H_FILTER_HI_P06_0_A_H_FILTER_HI_P06C3_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P06_0_A_H_FILTER_HI_P06C3_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P06_0_A_H_FILTER_HI_P06C3_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P06_0_A_H_FILTER_HI_P06C3_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_H_FILTER_HI_P06_0_A_H_FILTER_HI_P06C4_SHIFT _MK_SHIFT_CONST(6) +#define DC_WINC_A_H_FILTER_HI_P06_0_A_H_FILTER_HI_P06C4_FIELD _MK_FIELD_CONST(0x3, DC_WINC_A_H_FILTER_HI_P06_0_A_H_FILTER_HI_P06C4_SHIFT) +#define DC_WINC_A_H_FILTER_HI_P06_0_A_H_FILTER_HI_P06C4_RANGE 7:6 +#define DC_WINC_A_H_FILTER_HI_P06_0_A_H_FILTER_HI_P06C4_WOFFSET 0x0 +#define DC_WINC_A_H_FILTER_HI_P06_0_A_H_FILTER_HI_P06C4_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P06_0_A_H_FILTER_HI_P06C4_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P06_0_A_H_FILTER_HI_P06C4_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P06_0_A_H_FILTER_HI_P06C4_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_H_FILTER_HI_P06_0_A_H_FILTER_HI_P06C5_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_H_FILTER_HI_P06_0_A_H_FILTER_HI_P06C5_FIELD _MK_FIELD_CONST(0x3, DC_WINC_A_H_FILTER_HI_P06_0_A_H_FILTER_HI_P06C5_SHIFT) +#define DC_WINC_A_H_FILTER_HI_P06_0_A_H_FILTER_HI_P06C5_RANGE 9:8 +#define DC_WINC_A_H_FILTER_HI_P06_0_A_H_FILTER_HI_P06C5_WOFFSET 0x0 +#define DC_WINC_A_H_FILTER_HI_P06_0_A_H_FILTER_HI_P06C5_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P06_0_A_H_FILTER_HI_P06C5_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P06_0_A_H_FILTER_HI_P06C5_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P06_0_A_H_FILTER_HI_P06C5_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_WINC_A_H_FILTER_HI_P07_0 +#define DC_WINC_A_H_FILTER_HI_P07_0 _MK_ADDR_CONST(0x630) +#define DC_WINC_A_H_FILTER_HI_P07_0_SECURE 0x0 +#define DC_WINC_A_H_FILTER_HI_P07_0_WORD_COUNT 0x1 +#define DC_WINC_A_H_FILTER_HI_P07_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P07_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P07_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P07_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P07_0_READ_MASK _MK_MASK_CONST(0x3ff) +#define DC_WINC_A_H_FILTER_HI_P07_0_WRITE_MASK _MK_MASK_CONST(0x3ff) +#define DC_WINC_A_H_FILTER_HI_P07_0_A_H_FILTER_HI_P07C0_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_H_FILTER_HI_P07_0_A_H_FILTER_HI_P07C0_FIELD _MK_FIELD_CONST(0x3, DC_WINC_A_H_FILTER_HI_P07_0_A_H_FILTER_HI_P07C0_SHIFT) +#define DC_WINC_A_H_FILTER_HI_P07_0_A_H_FILTER_HI_P07C0_RANGE 1:0 +#define DC_WINC_A_H_FILTER_HI_P07_0_A_H_FILTER_HI_P07C0_WOFFSET 0x0 +#define DC_WINC_A_H_FILTER_HI_P07_0_A_H_FILTER_HI_P07C0_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P07_0_A_H_FILTER_HI_P07C0_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P07_0_A_H_FILTER_HI_P07C0_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P07_0_A_H_FILTER_HI_P07C0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_H_FILTER_HI_P07_0_A_H_FILTER_HI_P07C1_SHIFT _MK_SHIFT_CONST(2) +#define DC_WINC_A_H_FILTER_HI_P07_0_A_H_FILTER_HI_P07C1_FIELD _MK_FIELD_CONST(0x3, DC_WINC_A_H_FILTER_HI_P07_0_A_H_FILTER_HI_P07C1_SHIFT) +#define DC_WINC_A_H_FILTER_HI_P07_0_A_H_FILTER_HI_P07C1_RANGE 3:2 +#define DC_WINC_A_H_FILTER_HI_P07_0_A_H_FILTER_HI_P07C1_WOFFSET 0x0 +#define DC_WINC_A_H_FILTER_HI_P07_0_A_H_FILTER_HI_P07C1_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P07_0_A_H_FILTER_HI_P07C1_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P07_0_A_H_FILTER_HI_P07C1_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P07_0_A_H_FILTER_HI_P07C1_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_H_FILTER_HI_P07_0_A_H_FILTER_HI_P07C2_SHIFT _MK_SHIFT_CONST(4) +#define DC_WINC_A_H_FILTER_HI_P07_0_A_H_FILTER_HI_P07C2_FIELD _MK_FIELD_CONST(0x1, DC_WINC_A_H_FILTER_HI_P07_0_A_H_FILTER_HI_P07C2_SHIFT) +#define DC_WINC_A_H_FILTER_HI_P07_0_A_H_FILTER_HI_P07C2_RANGE 4:4 +#define DC_WINC_A_H_FILTER_HI_P07_0_A_H_FILTER_HI_P07C2_WOFFSET 0x0 +#define DC_WINC_A_H_FILTER_HI_P07_0_A_H_FILTER_HI_P07C2_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P07_0_A_H_FILTER_HI_P07C2_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P07_0_A_H_FILTER_HI_P07C2_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P07_0_A_H_FILTER_HI_P07C2_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_H_FILTER_HI_P07_0_A_H_FILTER_HI_P07C3_SHIFT _MK_SHIFT_CONST(5) +#define DC_WINC_A_H_FILTER_HI_P07_0_A_H_FILTER_HI_P07C3_FIELD _MK_FIELD_CONST(0x1, DC_WINC_A_H_FILTER_HI_P07_0_A_H_FILTER_HI_P07C3_SHIFT) +#define DC_WINC_A_H_FILTER_HI_P07_0_A_H_FILTER_HI_P07C3_RANGE 5:5 +#define DC_WINC_A_H_FILTER_HI_P07_0_A_H_FILTER_HI_P07C3_WOFFSET 0x0 +#define DC_WINC_A_H_FILTER_HI_P07_0_A_H_FILTER_HI_P07C3_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P07_0_A_H_FILTER_HI_P07C3_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P07_0_A_H_FILTER_HI_P07C3_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P07_0_A_H_FILTER_HI_P07C3_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_H_FILTER_HI_P07_0_A_H_FILTER_HI_P07C4_SHIFT _MK_SHIFT_CONST(6) +#define DC_WINC_A_H_FILTER_HI_P07_0_A_H_FILTER_HI_P07C4_FIELD _MK_FIELD_CONST(0x3, DC_WINC_A_H_FILTER_HI_P07_0_A_H_FILTER_HI_P07C4_SHIFT) +#define DC_WINC_A_H_FILTER_HI_P07_0_A_H_FILTER_HI_P07C4_RANGE 7:6 +#define DC_WINC_A_H_FILTER_HI_P07_0_A_H_FILTER_HI_P07C4_WOFFSET 0x0 +#define DC_WINC_A_H_FILTER_HI_P07_0_A_H_FILTER_HI_P07C4_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P07_0_A_H_FILTER_HI_P07C4_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P07_0_A_H_FILTER_HI_P07C4_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P07_0_A_H_FILTER_HI_P07C4_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_H_FILTER_HI_P07_0_A_H_FILTER_HI_P07C5_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_H_FILTER_HI_P07_0_A_H_FILTER_HI_P07C5_FIELD _MK_FIELD_CONST(0x3, DC_WINC_A_H_FILTER_HI_P07_0_A_H_FILTER_HI_P07C5_SHIFT) +#define DC_WINC_A_H_FILTER_HI_P07_0_A_H_FILTER_HI_P07C5_RANGE 9:8 +#define DC_WINC_A_H_FILTER_HI_P07_0_A_H_FILTER_HI_P07C5_WOFFSET 0x0 +#define DC_WINC_A_H_FILTER_HI_P07_0_A_H_FILTER_HI_P07C5_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P07_0_A_H_FILTER_HI_P07C5_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P07_0_A_H_FILTER_HI_P07C5_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P07_0_A_H_FILTER_HI_P07C5_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_WINC_A_H_FILTER_HI_P08_0 +#define DC_WINC_A_H_FILTER_HI_P08_0 _MK_ADDR_CONST(0x631) +#define DC_WINC_A_H_FILTER_HI_P08_0_SECURE 0x0 +#define DC_WINC_A_H_FILTER_HI_P08_0_WORD_COUNT 0x1 +#define DC_WINC_A_H_FILTER_HI_P08_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P08_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P08_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P08_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P08_0_READ_MASK _MK_MASK_CONST(0x3ff) +#define DC_WINC_A_H_FILTER_HI_P08_0_WRITE_MASK _MK_MASK_CONST(0x3ff) +#define DC_WINC_A_H_FILTER_HI_P08_0_A_H_FILTER_HI_P08C0_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_H_FILTER_HI_P08_0_A_H_FILTER_HI_P08C0_FIELD _MK_FIELD_CONST(0x3, DC_WINC_A_H_FILTER_HI_P08_0_A_H_FILTER_HI_P08C0_SHIFT) +#define DC_WINC_A_H_FILTER_HI_P08_0_A_H_FILTER_HI_P08C0_RANGE 1:0 +#define DC_WINC_A_H_FILTER_HI_P08_0_A_H_FILTER_HI_P08C0_WOFFSET 0x0 +#define DC_WINC_A_H_FILTER_HI_P08_0_A_H_FILTER_HI_P08C0_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P08_0_A_H_FILTER_HI_P08C0_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P08_0_A_H_FILTER_HI_P08C0_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P08_0_A_H_FILTER_HI_P08C0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_H_FILTER_HI_P08_0_A_H_FILTER_HI_P08C1_SHIFT _MK_SHIFT_CONST(2) +#define DC_WINC_A_H_FILTER_HI_P08_0_A_H_FILTER_HI_P08C1_FIELD _MK_FIELD_CONST(0x3, DC_WINC_A_H_FILTER_HI_P08_0_A_H_FILTER_HI_P08C1_SHIFT) +#define DC_WINC_A_H_FILTER_HI_P08_0_A_H_FILTER_HI_P08C1_RANGE 3:2 +#define DC_WINC_A_H_FILTER_HI_P08_0_A_H_FILTER_HI_P08C1_WOFFSET 0x0 +#define DC_WINC_A_H_FILTER_HI_P08_0_A_H_FILTER_HI_P08C1_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P08_0_A_H_FILTER_HI_P08C1_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P08_0_A_H_FILTER_HI_P08C1_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P08_0_A_H_FILTER_HI_P08C1_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_H_FILTER_HI_P08_0_A_H_FILTER_HI_P08C2_SHIFT _MK_SHIFT_CONST(4) +#define DC_WINC_A_H_FILTER_HI_P08_0_A_H_FILTER_HI_P08C2_FIELD _MK_FIELD_CONST(0x1, DC_WINC_A_H_FILTER_HI_P08_0_A_H_FILTER_HI_P08C2_SHIFT) +#define DC_WINC_A_H_FILTER_HI_P08_0_A_H_FILTER_HI_P08C2_RANGE 4:4 +#define DC_WINC_A_H_FILTER_HI_P08_0_A_H_FILTER_HI_P08C2_WOFFSET 0x0 +#define DC_WINC_A_H_FILTER_HI_P08_0_A_H_FILTER_HI_P08C2_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P08_0_A_H_FILTER_HI_P08C2_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P08_0_A_H_FILTER_HI_P08C2_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P08_0_A_H_FILTER_HI_P08C2_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_H_FILTER_HI_P08_0_A_H_FILTER_HI_P08C3_SHIFT _MK_SHIFT_CONST(5) +#define DC_WINC_A_H_FILTER_HI_P08_0_A_H_FILTER_HI_P08C3_FIELD _MK_FIELD_CONST(0x1, DC_WINC_A_H_FILTER_HI_P08_0_A_H_FILTER_HI_P08C3_SHIFT) +#define DC_WINC_A_H_FILTER_HI_P08_0_A_H_FILTER_HI_P08C3_RANGE 5:5 +#define DC_WINC_A_H_FILTER_HI_P08_0_A_H_FILTER_HI_P08C3_WOFFSET 0x0 +#define DC_WINC_A_H_FILTER_HI_P08_0_A_H_FILTER_HI_P08C3_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P08_0_A_H_FILTER_HI_P08C3_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P08_0_A_H_FILTER_HI_P08C3_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P08_0_A_H_FILTER_HI_P08C3_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_H_FILTER_HI_P08_0_A_H_FILTER_HI_P08C4_SHIFT _MK_SHIFT_CONST(6) +#define DC_WINC_A_H_FILTER_HI_P08_0_A_H_FILTER_HI_P08C4_FIELD _MK_FIELD_CONST(0x3, DC_WINC_A_H_FILTER_HI_P08_0_A_H_FILTER_HI_P08C4_SHIFT) +#define DC_WINC_A_H_FILTER_HI_P08_0_A_H_FILTER_HI_P08C4_RANGE 7:6 +#define DC_WINC_A_H_FILTER_HI_P08_0_A_H_FILTER_HI_P08C4_WOFFSET 0x0 +#define DC_WINC_A_H_FILTER_HI_P08_0_A_H_FILTER_HI_P08C4_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P08_0_A_H_FILTER_HI_P08C4_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P08_0_A_H_FILTER_HI_P08C4_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P08_0_A_H_FILTER_HI_P08C4_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_H_FILTER_HI_P08_0_A_H_FILTER_HI_P08C5_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_H_FILTER_HI_P08_0_A_H_FILTER_HI_P08C5_FIELD _MK_FIELD_CONST(0x3, DC_WINC_A_H_FILTER_HI_P08_0_A_H_FILTER_HI_P08C5_SHIFT) +#define DC_WINC_A_H_FILTER_HI_P08_0_A_H_FILTER_HI_P08C5_RANGE 9:8 +#define DC_WINC_A_H_FILTER_HI_P08_0_A_H_FILTER_HI_P08C5_WOFFSET 0x0 +#define DC_WINC_A_H_FILTER_HI_P08_0_A_H_FILTER_HI_P08C5_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P08_0_A_H_FILTER_HI_P08C5_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P08_0_A_H_FILTER_HI_P08C5_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P08_0_A_H_FILTER_HI_P08C5_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_WINC_A_H_FILTER_HI_P09_0 +#define DC_WINC_A_H_FILTER_HI_P09_0 _MK_ADDR_CONST(0x632) +#define DC_WINC_A_H_FILTER_HI_P09_0_SECURE 0x0 +#define DC_WINC_A_H_FILTER_HI_P09_0_WORD_COUNT 0x1 +#define DC_WINC_A_H_FILTER_HI_P09_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P09_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P09_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P09_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P09_0_READ_MASK _MK_MASK_CONST(0x3ff) +#define DC_WINC_A_H_FILTER_HI_P09_0_WRITE_MASK _MK_MASK_CONST(0x3ff) +#define DC_WINC_A_H_FILTER_HI_P09_0_A_H_FILTER_HI_P09C0_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_H_FILTER_HI_P09_0_A_H_FILTER_HI_P09C0_FIELD _MK_FIELD_CONST(0x3, DC_WINC_A_H_FILTER_HI_P09_0_A_H_FILTER_HI_P09C0_SHIFT) +#define DC_WINC_A_H_FILTER_HI_P09_0_A_H_FILTER_HI_P09C0_RANGE 1:0 +#define DC_WINC_A_H_FILTER_HI_P09_0_A_H_FILTER_HI_P09C0_WOFFSET 0x0 +#define DC_WINC_A_H_FILTER_HI_P09_0_A_H_FILTER_HI_P09C0_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P09_0_A_H_FILTER_HI_P09C0_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P09_0_A_H_FILTER_HI_P09C0_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P09_0_A_H_FILTER_HI_P09C0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_H_FILTER_HI_P09_0_A_H_FILTER_HI_P09C1_SHIFT _MK_SHIFT_CONST(2) +#define DC_WINC_A_H_FILTER_HI_P09_0_A_H_FILTER_HI_P09C1_FIELD _MK_FIELD_CONST(0x3, DC_WINC_A_H_FILTER_HI_P09_0_A_H_FILTER_HI_P09C1_SHIFT) +#define DC_WINC_A_H_FILTER_HI_P09_0_A_H_FILTER_HI_P09C1_RANGE 3:2 +#define DC_WINC_A_H_FILTER_HI_P09_0_A_H_FILTER_HI_P09C1_WOFFSET 0x0 +#define DC_WINC_A_H_FILTER_HI_P09_0_A_H_FILTER_HI_P09C1_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P09_0_A_H_FILTER_HI_P09C1_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P09_0_A_H_FILTER_HI_P09C1_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P09_0_A_H_FILTER_HI_P09C1_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_H_FILTER_HI_P09_0_A_H_FILTER_HI_P09C2_SHIFT _MK_SHIFT_CONST(4) +#define DC_WINC_A_H_FILTER_HI_P09_0_A_H_FILTER_HI_P09C2_FIELD _MK_FIELD_CONST(0x1, DC_WINC_A_H_FILTER_HI_P09_0_A_H_FILTER_HI_P09C2_SHIFT) +#define DC_WINC_A_H_FILTER_HI_P09_0_A_H_FILTER_HI_P09C2_RANGE 4:4 +#define DC_WINC_A_H_FILTER_HI_P09_0_A_H_FILTER_HI_P09C2_WOFFSET 0x0 +#define DC_WINC_A_H_FILTER_HI_P09_0_A_H_FILTER_HI_P09C2_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P09_0_A_H_FILTER_HI_P09C2_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P09_0_A_H_FILTER_HI_P09C2_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P09_0_A_H_FILTER_HI_P09C2_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_H_FILTER_HI_P09_0_A_H_FILTER_HI_P09C3_SHIFT _MK_SHIFT_CONST(5) +#define DC_WINC_A_H_FILTER_HI_P09_0_A_H_FILTER_HI_P09C3_FIELD _MK_FIELD_CONST(0x1, DC_WINC_A_H_FILTER_HI_P09_0_A_H_FILTER_HI_P09C3_SHIFT) +#define DC_WINC_A_H_FILTER_HI_P09_0_A_H_FILTER_HI_P09C3_RANGE 5:5 +#define DC_WINC_A_H_FILTER_HI_P09_0_A_H_FILTER_HI_P09C3_WOFFSET 0x0 +#define DC_WINC_A_H_FILTER_HI_P09_0_A_H_FILTER_HI_P09C3_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P09_0_A_H_FILTER_HI_P09C3_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P09_0_A_H_FILTER_HI_P09C3_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P09_0_A_H_FILTER_HI_P09C3_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_H_FILTER_HI_P09_0_A_H_FILTER_HI_P09C4_SHIFT _MK_SHIFT_CONST(6) +#define DC_WINC_A_H_FILTER_HI_P09_0_A_H_FILTER_HI_P09C4_FIELD _MK_FIELD_CONST(0x3, DC_WINC_A_H_FILTER_HI_P09_0_A_H_FILTER_HI_P09C4_SHIFT) +#define DC_WINC_A_H_FILTER_HI_P09_0_A_H_FILTER_HI_P09C4_RANGE 7:6 +#define DC_WINC_A_H_FILTER_HI_P09_0_A_H_FILTER_HI_P09C4_WOFFSET 0x0 +#define DC_WINC_A_H_FILTER_HI_P09_0_A_H_FILTER_HI_P09C4_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P09_0_A_H_FILTER_HI_P09C4_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P09_0_A_H_FILTER_HI_P09C4_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P09_0_A_H_FILTER_HI_P09C4_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_H_FILTER_HI_P09_0_A_H_FILTER_HI_P09C5_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_H_FILTER_HI_P09_0_A_H_FILTER_HI_P09C5_FIELD _MK_FIELD_CONST(0x3, DC_WINC_A_H_FILTER_HI_P09_0_A_H_FILTER_HI_P09C5_SHIFT) +#define DC_WINC_A_H_FILTER_HI_P09_0_A_H_FILTER_HI_P09C5_RANGE 9:8 +#define DC_WINC_A_H_FILTER_HI_P09_0_A_H_FILTER_HI_P09C5_WOFFSET 0x0 +#define DC_WINC_A_H_FILTER_HI_P09_0_A_H_FILTER_HI_P09C5_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P09_0_A_H_FILTER_HI_P09C5_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P09_0_A_H_FILTER_HI_P09C5_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P09_0_A_H_FILTER_HI_P09C5_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_WINC_A_H_FILTER_HI_P0A_0 +#define DC_WINC_A_H_FILTER_HI_P0A_0 _MK_ADDR_CONST(0x633) +#define DC_WINC_A_H_FILTER_HI_P0A_0_SECURE 0x0 +#define DC_WINC_A_H_FILTER_HI_P0A_0_WORD_COUNT 0x1 +#define DC_WINC_A_H_FILTER_HI_P0A_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P0A_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P0A_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P0A_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P0A_0_READ_MASK _MK_MASK_CONST(0x3ff) +#define DC_WINC_A_H_FILTER_HI_P0A_0_WRITE_MASK _MK_MASK_CONST(0x3ff) +#define DC_WINC_A_H_FILTER_HI_P0A_0_A_H_FILTER_HI_P0AC0_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_H_FILTER_HI_P0A_0_A_H_FILTER_HI_P0AC0_FIELD _MK_FIELD_CONST(0x3, DC_WINC_A_H_FILTER_HI_P0A_0_A_H_FILTER_HI_P0AC0_SHIFT) +#define DC_WINC_A_H_FILTER_HI_P0A_0_A_H_FILTER_HI_P0AC0_RANGE 1:0 +#define DC_WINC_A_H_FILTER_HI_P0A_0_A_H_FILTER_HI_P0AC0_WOFFSET 0x0 +#define DC_WINC_A_H_FILTER_HI_P0A_0_A_H_FILTER_HI_P0AC0_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P0A_0_A_H_FILTER_HI_P0AC0_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P0A_0_A_H_FILTER_HI_P0AC0_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P0A_0_A_H_FILTER_HI_P0AC0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_H_FILTER_HI_P0A_0_A_H_FILTER_HI_P0AC1_SHIFT _MK_SHIFT_CONST(2) +#define DC_WINC_A_H_FILTER_HI_P0A_0_A_H_FILTER_HI_P0AC1_FIELD _MK_FIELD_CONST(0x3, DC_WINC_A_H_FILTER_HI_P0A_0_A_H_FILTER_HI_P0AC1_SHIFT) +#define DC_WINC_A_H_FILTER_HI_P0A_0_A_H_FILTER_HI_P0AC1_RANGE 3:2 +#define DC_WINC_A_H_FILTER_HI_P0A_0_A_H_FILTER_HI_P0AC1_WOFFSET 0x0 +#define DC_WINC_A_H_FILTER_HI_P0A_0_A_H_FILTER_HI_P0AC1_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P0A_0_A_H_FILTER_HI_P0AC1_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P0A_0_A_H_FILTER_HI_P0AC1_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P0A_0_A_H_FILTER_HI_P0AC1_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_H_FILTER_HI_P0A_0_A_H_FILTER_HI_P0AC2_SHIFT _MK_SHIFT_CONST(4) +#define DC_WINC_A_H_FILTER_HI_P0A_0_A_H_FILTER_HI_P0AC2_FIELD _MK_FIELD_CONST(0x1, DC_WINC_A_H_FILTER_HI_P0A_0_A_H_FILTER_HI_P0AC2_SHIFT) +#define DC_WINC_A_H_FILTER_HI_P0A_0_A_H_FILTER_HI_P0AC2_RANGE 4:4 +#define DC_WINC_A_H_FILTER_HI_P0A_0_A_H_FILTER_HI_P0AC2_WOFFSET 0x0 +#define DC_WINC_A_H_FILTER_HI_P0A_0_A_H_FILTER_HI_P0AC2_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P0A_0_A_H_FILTER_HI_P0AC2_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P0A_0_A_H_FILTER_HI_P0AC2_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P0A_0_A_H_FILTER_HI_P0AC2_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_H_FILTER_HI_P0A_0_A_H_FILTER_HI_P0AC3_SHIFT _MK_SHIFT_CONST(5) +#define DC_WINC_A_H_FILTER_HI_P0A_0_A_H_FILTER_HI_P0AC3_FIELD _MK_FIELD_CONST(0x1, DC_WINC_A_H_FILTER_HI_P0A_0_A_H_FILTER_HI_P0AC3_SHIFT) +#define DC_WINC_A_H_FILTER_HI_P0A_0_A_H_FILTER_HI_P0AC3_RANGE 5:5 +#define DC_WINC_A_H_FILTER_HI_P0A_0_A_H_FILTER_HI_P0AC3_WOFFSET 0x0 +#define DC_WINC_A_H_FILTER_HI_P0A_0_A_H_FILTER_HI_P0AC3_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P0A_0_A_H_FILTER_HI_P0AC3_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P0A_0_A_H_FILTER_HI_P0AC3_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P0A_0_A_H_FILTER_HI_P0AC3_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_H_FILTER_HI_P0A_0_A_H_FILTER_HI_P0AC4_SHIFT _MK_SHIFT_CONST(6) +#define DC_WINC_A_H_FILTER_HI_P0A_0_A_H_FILTER_HI_P0AC4_FIELD _MK_FIELD_CONST(0x3, DC_WINC_A_H_FILTER_HI_P0A_0_A_H_FILTER_HI_P0AC4_SHIFT) +#define DC_WINC_A_H_FILTER_HI_P0A_0_A_H_FILTER_HI_P0AC4_RANGE 7:6 +#define DC_WINC_A_H_FILTER_HI_P0A_0_A_H_FILTER_HI_P0AC4_WOFFSET 0x0 +#define DC_WINC_A_H_FILTER_HI_P0A_0_A_H_FILTER_HI_P0AC4_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P0A_0_A_H_FILTER_HI_P0AC4_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P0A_0_A_H_FILTER_HI_P0AC4_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P0A_0_A_H_FILTER_HI_P0AC4_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_H_FILTER_HI_P0A_0_A_H_FILTER_HI_P0AC5_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_H_FILTER_HI_P0A_0_A_H_FILTER_HI_P0AC5_FIELD _MK_FIELD_CONST(0x3, DC_WINC_A_H_FILTER_HI_P0A_0_A_H_FILTER_HI_P0AC5_SHIFT) +#define DC_WINC_A_H_FILTER_HI_P0A_0_A_H_FILTER_HI_P0AC5_RANGE 9:8 +#define DC_WINC_A_H_FILTER_HI_P0A_0_A_H_FILTER_HI_P0AC5_WOFFSET 0x0 +#define DC_WINC_A_H_FILTER_HI_P0A_0_A_H_FILTER_HI_P0AC5_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P0A_0_A_H_FILTER_HI_P0AC5_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P0A_0_A_H_FILTER_HI_P0AC5_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P0A_0_A_H_FILTER_HI_P0AC5_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_WINC_A_H_FILTER_HI_P0B_0 +#define DC_WINC_A_H_FILTER_HI_P0B_0 _MK_ADDR_CONST(0x634) +#define DC_WINC_A_H_FILTER_HI_P0B_0_SECURE 0x0 +#define DC_WINC_A_H_FILTER_HI_P0B_0_WORD_COUNT 0x1 +#define DC_WINC_A_H_FILTER_HI_P0B_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P0B_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P0B_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P0B_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P0B_0_READ_MASK _MK_MASK_CONST(0x3ff) +#define DC_WINC_A_H_FILTER_HI_P0B_0_WRITE_MASK _MK_MASK_CONST(0x3ff) +#define DC_WINC_A_H_FILTER_HI_P0B_0_A_H_FILTER_HI_P0BC0_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_H_FILTER_HI_P0B_0_A_H_FILTER_HI_P0BC0_FIELD _MK_FIELD_CONST(0x3, DC_WINC_A_H_FILTER_HI_P0B_0_A_H_FILTER_HI_P0BC0_SHIFT) +#define DC_WINC_A_H_FILTER_HI_P0B_0_A_H_FILTER_HI_P0BC0_RANGE 1:0 +#define DC_WINC_A_H_FILTER_HI_P0B_0_A_H_FILTER_HI_P0BC0_WOFFSET 0x0 +#define DC_WINC_A_H_FILTER_HI_P0B_0_A_H_FILTER_HI_P0BC0_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P0B_0_A_H_FILTER_HI_P0BC0_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P0B_0_A_H_FILTER_HI_P0BC0_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P0B_0_A_H_FILTER_HI_P0BC0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_H_FILTER_HI_P0B_0_A_H_FILTER_HI_P0BC1_SHIFT _MK_SHIFT_CONST(2) +#define DC_WINC_A_H_FILTER_HI_P0B_0_A_H_FILTER_HI_P0BC1_FIELD _MK_FIELD_CONST(0x3, DC_WINC_A_H_FILTER_HI_P0B_0_A_H_FILTER_HI_P0BC1_SHIFT) +#define DC_WINC_A_H_FILTER_HI_P0B_0_A_H_FILTER_HI_P0BC1_RANGE 3:2 +#define DC_WINC_A_H_FILTER_HI_P0B_0_A_H_FILTER_HI_P0BC1_WOFFSET 0x0 +#define DC_WINC_A_H_FILTER_HI_P0B_0_A_H_FILTER_HI_P0BC1_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P0B_0_A_H_FILTER_HI_P0BC1_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P0B_0_A_H_FILTER_HI_P0BC1_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P0B_0_A_H_FILTER_HI_P0BC1_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_H_FILTER_HI_P0B_0_A_H_FILTER_HI_P0BC2_SHIFT _MK_SHIFT_CONST(4) +#define DC_WINC_A_H_FILTER_HI_P0B_0_A_H_FILTER_HI_P0BC2_FIELD _MK_FIELD_CONST(0x1, DC_WINC_A_H_FILTER_HI_P0B_0_A_H_FILTER_HI_P0BC2_SHIFT) +#define DC_WINC_A_H_FILTER_HI_P0B_0_A_H_FILTER_HI_P0BC2_RANGE 4:4 +#define DC_WINC_A_H_FILTER_HI_P0B_0_A_H_FILTER_HI_P0BC2_WOFFSET 0x0 +#define DC_WINC_A_H_FILTER_HI_P0B_0_A_H_FILTER_HI_P0BC2_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P0B_0_A_H_FILTER_HI_P0BC2_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P0B_0_A_H_FILTER_HI_P0BC2_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P0B_0_A_H_FILTER_HI_P0BC2_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_H_FILTER_HI_P0B_0_A_H_FILTER_HI_P0BC3_SHIFT _MK_SHIFT_CONST(5) +#define DC_WINC_A_H_FILTER_HI_P0B_0_A_H_FILTER_HI_P0BC3_FIELD _MK_FIELD_CONST(0x1, DC_WINC_A_H_FILTER_HI_P0B_0_A_H_FILTER_HI_P0BC3_SHIFT) +#define DC_WINC_A_H_FILTER_HI_P0B_0_A_H_FILTER_HI_P0BC3_RANGE 5:5 +#define DC_WINC_A_H_FILTER_HI_P0B_0_A_H_FILTER_HI_P0BC3_WOFFSET 0x0 +#define DC_WINC_A_H_FILTER_HI_P0B_0_A_H_FILTER_HI_P0BC3_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P0B_0_A_H_FILTER_HI_P0BC3_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P0B_0_A_H_FILTER_HI_P0BC3_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P0B_0_A_H_FILTER_HI_P0BC3_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_H_FILTER_HI_P0B_0_A_H_FILTER_HI_P0BC4_SHIFT _MK_SHIFT_CONST(6) +#define DC_WINC_A_H_FILTER_HI_P0B_0_A_H_FILTER_HI_P0BC4_FIELD _MK_FIELD_CONST(0x3, DC_WINC_A_H_FILTER_HI_P0B_0_A_H_FILTER_HI_P0BC4_SHIFT) +#define DC_WINC_A_H_FILTER_HI_P0B_0_A_H_FILTER_HI_P0BC4_RANGE 7:6 +#define DC_WINC_A_H_FILTER_HI_P0B_0_A_H_FILTER_HI_P0BC4_WOFFSET 0x0 +#define DC_WINC_A_H_FILTER_HI_P0B_0_A_H_FILTER_HI_P0BC4_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P0B_0_A_H_FILTER_HI_P0BC4_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P0B_0_A_H_FILTER_HI_P0BC4_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P0B_0_A_H_FILTER_HI_P0BC4_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_H_FILTER_HI_P0B_0_A_H_FILTER_HI_P0BC5_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_H_FILTER_HI_P0B_0_A_H_FILTER_HI_P0BC5_FIELD _MK_FIELD_CONST(0x3, DC_WINC_A_H_FILTER_HI_P0B_0_A_H_FILTER_HI_P0BC5_SHIFT) +#define DC_WINC_A_H_FILTER_HI_P0B_0_A_H_FILTER_HI_P0BC5_RANGE 9:8 +#define DC_WINC_A_H_FILTER_HI_P0B_0_A_H_FILTER_HI_P0BC5_WOFFSET 0x0 +#define DC_WINC_A_H_FILTER_HI_P0B_0_A_H_FILTER_HI_P0BC5_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P0B_0_A_H_FILTER_HI_P0BC5_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P0B_0_A_H_FILTER_HI_P0BC5_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P0B_0_A_H_FILTER_HI_P0BC5_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_WINC_A_H_FILTER_HI_P0C_0 +#define DC_WINC_A_H_FILTER_HI_P0C_0 _MK_ADDR_CONST(0x635) +#define DC_WINC_A_H_FILTER_HI_P0C_0_SECURE 0x0 +#define DC_WINC_A_H_FILTER_HI_P0C_0_WORD_COUNT 0x1 +#define DC_WINC_A_H_FILTER_HI_P0C_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P0C_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P0C_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P0C_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P0C_0_READ_MASK _MK_MASK_CONST(0x3ff) +#define DC_WINC_A_H_FILTER_HI_P0C_0_WRITE_MASK _MK_MASK_CONST(0x3ff) +#define DC_WINC_A_H_FILTER_HI_P0C_0_A_H_FILTER_HI_P0CC0_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_H_FILTER_HI_P0C_0_A_H_FILTER_HI_P0CC0_FIELD _MK_FIELD_CONST(0x3, DC_WINC_A_H_FILTER_HI_P0C_0_A_H_FILTER_HI_P0CC0_SHIFT) +#define DC_WINC_A_H_FILTER_HI_P0C_0_A_H_FILTER_HI_P0CC0_RANGE 1:0 +#define DC_WINC_A_H_FILTER_HI_P0C_0_A_H_FILTER_HI_P0CC0_WOFFSET 0x0 +#define DC_WINC_A_H_FILTER_HI_P0C_0_A_H_FILTER_HI_P0CC0_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P0C_0_A_H_FILTER_HI_P0CC0_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P0C_0_A_H_FILTER_HI_P0CC0_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P0C_0_A_H_FILTER_HI_P0CC0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_H_FILTER_HI_P0C_0_A_H_FILTER_HI_P0CC1_SHIFT _MK_SHIFT_CONST(2) +#define DC_WINC_A_H_FILTER_HI_P0C_0_A_H_FILTER_HI_P0CC1_FIELD _MK_FIELD_CONST(0x3, DC_WINC_A_H_FILTER_HI_P0C_0_A_H_FILTER_HI_P0CC1_SHIFT) +#define DC_WINC_A_H_FILTER_HI_P0C_0_A_H_FILTER_HI_P0CC1_RANGE 3:2 +#define DC_WINC_A_H_FILTER_HI_P0C_0_A_H_FILTER_HI_P0CC1_WOFFSET 0x0 +#define DC_WINC_A_H_FILTER_HI_P0C_0_A_H_FILTER_HI_P0CC1_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P0C_0_A_H_FILTER_HI_P0CC1_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P0C_0_A_H_FILTER_HI_P0CC1_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P0C_0_A_H_FILTER_HI_P0CC1_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_H_FILTER_HI_P0C_0_A_H_FILTER_HI_P0CC2_SHIFT _MK_SHIFT_CONST(4) +#define DC_WINC_A_H_FILTER_HI_P0C_0_A_H_FILTER_HI_P0CC2_FIELD _MK_FIELD_CONST(0x1, DC_WINC_A_H_FILTER_HI_P0C_0_A_H_FILTER_HI_P0CC2_SHIFT) +#define DC_WINC_A_H_FILTER_HI_P0C_0_A_H_FILTER_HI_P0CC2_RANGE 4:4 +#define DC_WINC_A_H_FILTER_HI_P0C_0_A_H_FILTER_HI_P0CC2_WOFFSET 0x0 +#define DC_WINC_A_H_FILTER_HI_P0C_0_A_H_FILTER_HI_P0CC2_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P0C_0_A_H_FILTER_HI_P0CC2_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P0C_0_A_H_FILTER_HI_P0CC2_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P0C_0_A_H_FILTER_HI_P0CC2_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_H_FILTER_HI_P0C_0_A_H_FILTER_HI_P0CC3_SHIFT _MK_SHIFT_CONST(5) +#define DC_WINC_A_H_FILTER_HI_P0C_0_A_H_FILTER_HI_P0CC3_FIELD _MK_FIELD_CONST(0x1, DC_WINC_A_H_FILTER_HI_P0C_0_A_H_FILTER_HI_P0CC3_SHIFT) +#define DC_WINC_A_H_FILTER_HI_P0C_0_A_H_FILTER_HI_P0CC3_RANGE 5:5 +#define DC_WINC_A_H_FILTER_HI_P0C_0_A_H_FILTER_HI_P0CC3_WOFFSET 0x0 +#define DC_WINC_A_H_FILTER_HI_P0C_0_A_H_FILTER_HI_P0CC3_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P0C_0_A_H_FILTER_HI_P0CC3_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P0C_0_A_H_FILTER_HI_P0CC3_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P0C_0_A_H_FILTER_HI_P0CC3_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_H_FILTER_HI_P0C_0_A_H_FILTER_HI_P0CC4_SHIFT _MK_SHIFT_CONST(6) +#define DC_WINC_A_H_FILTER_HI_P0C_0_A_H_FILTER_HI_P0CC4_FIELD _MK_FIELD_CONST(0x3, DC_WINC_A_H_FILTER_HI_P0C_0_A_H_FILTER_HI_P0CC4_SHIFT) +#define DC_WINC_A_H_FILTER_HI_P0C_0_A_H_FILTER_HI_P0CC4_RANGE 7:6 +#define DC_WINC_A_H_FILTER_HI_P0C_0_A_H_FILTER_HI_P0CC4_WOFFSET 0x0 +#define DC_WINC_A_H_FILTER_HI_P0C_0_A_H_FILTER_HI_P0CC4_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P0C_0_A_H_FILTER_HI_P0CC4_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P0C_0_A_H_FILTER_HI_P0CC4_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P0C_0_A_H_FILTER_HI_P0CC4_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_H_FILTER_HI_P0C_0_A_H_FILTER_HI_P0CC5_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_H_FILTER_HI_P0C_0_A_H_FILTER_HI_P0CC5_FIELD _MK_FIELD_CONST(0x3, DC_WINC_A_H_FILTER_HI_P0C_0_A_H_FILTER_HI_P0CC5_SHIFT) +#define DC_WINC_A_H_FILTER_HI_P0C_0_A_H_FILTER_HI_P0CC5_RANGE 9:8 +#define DC_WINC_A_H_FILTER_HI_P0C_0_A_H_FILTER_HI_P0CC5_WOFFSET 0x0 +#define DC_WINC_A_H_FILTER_HI_P0C_0_A_H_FILTER_HI_P0CC5_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P0C_0_A_H_FILTER_HI_P0CC5_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P0C_0_A_H_FILTER_HI_P0CC5_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P0C_0_A_H_FILTER_HI_P0CC5_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_WINC_A_H_FILTER_HI_P0D_0 +#define DC_WINC_A_H_FILTER_HI_P0D_0 _MK_ADDR_CONST(0x636) +#define DC_WINC_A_H_FILTER_HI_P0D_0_SECURE 0x0 +#define DC_WINC_A_H_FILTER_HI_P0D_0_WORD_COUNT 0x1 +#define DC_WINC_A_H_FILTER_HI_P0D_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P0D_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P0D_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P0D_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P0D_0_READ_MASK _MK_MASK_CONST(0x3ff) +#define DC_WINC_A_H_FILTER_HI_P0D_0_WRITE_MASK _MK_MASK_CONST(0x3ff) +#define DC_WINC_A_H_FILTER_HI_P0D_0_A_H_FILTER_HI_P0DC0_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_H_FILTER_HI_P0D_0_A_H_FILTER_HI_P0DC0_FIELD _MK_FIELD_CONST(0x3, DC_WINC_A_H_FILTER_HI_P0D_0_A_H_FILTER_HI_P0DC0_SHIFT) +#define DC_WINC_A_H_FILTER_HI_P0D_0_A_H_FILTER_HI_P0DC0_RANGE 1:0 +#define DC_WINC_A_H_FILTER_HI_P0D_0_A_H_FILTER_HI_P0DC0_WOFFSET 0x0 +#define DC_WINC_A_H_FILTER_HI_P0D_0_A_H_FILTER_HI_P0DC0_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P0D_0_A_H_FILTER_HI_P0DC0_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P0D_0_A_H_FILTER_HI_P0DC0_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P0D_0_A_H_FILTER_HI_P0DC0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_H_FILTER_HI_P0D_0_A_H_FILTER_HI_P0DC1_SHIFT _MK_SHIFT_CONST(2) +#define DC_WINC_A_H_FILTER_HI_P0D_0_A_H_FILTER_HI_P0DC1_FIELD _MK_FIELD_CONST(0x3, DC_WINC_A_H_FILTER_HI_P0D_0_A_H_FILTER_HI_P0DC1_SHIFT) +#define DC_WINC_A_H_FILTER_HI_P0D_0_A_H_FILTER_HI_P0DC1_RANGE 3:2 +#define DC_WINC_A_H_FILTER_HI_P0D_0_A_H_FILTER_HI_P0DC1_WOFFSET 0x0 +#define DC_WINC_A_H_FILTER_HI_P0D_0_A_H_FILTER_HI_P0DC1_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P0D_0_A_H_FILTER_HI_P0DC1_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P0D_0_A_H_FILTER_HI_P0DC1_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P0D_0_A_H_FILTER_HI_P0DC1_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_H_FILTER_HI_P0D_0_A_H_FILTER_HI_P0DC2_SHIFT _MK_SHIFT_CONST(4) +#define DC_WINC_A_H_FILTER_HI_P0D_0_A_H_FILTER_HI_P0DC2_FIELD _MK_FIELD_CONST(0x1, DC_WINC_A_H_FILTER_HI_P0D_0_A_H_FILTER_HI_P0DC2_SHIFT) +#define DC_WINC_A_H_FILTER_HI_P0D_0_A_H_FILTER_HI_P0DC2_RANGE 4:4 +#define DC_WINC_A_H_FILTER_HI_P0D_0_A_H_FILTER_HI_P0DC2_WOFFSET 0x0 +#define DC_WINC_A_H_FILTER_HI_P0D_0_A_H_FILTER_HI_P0DC2_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P0D_0_A_H_FILTER_HI_P0DC2_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P0D_0_A_H_FILTER_HI_P0DC2_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P0D_0_A_H_FILTER_HI_P0DC2_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_H_FILTER_HI_P0D_0_A_H_FILTER_HI_P0DC3_SHIFT _MK_SHIFT_CONST(5) +#define DC_WINC_A_H_FILTER_HI_P0D_0_A_H_FILTER_HI_P0DC3_FIELD _MK_FIELD_CONST(0x1, DC_WINC_A_H_FILTER_HI_P0D_0_A_H_FILTER_HI_P0DC3_SHIFT) +#define DC_WINC_A_H_FILTER_HI_P0D_0_A_H_FILTER_HI_P0DC3_RANGE 5:5 +#define DC_WINC_A_H_FILTER_HI_P0D_0_A_H_FILTER_HI_P0DC3_WOFFSET 0x0 +#define DC_WINC_A_H_FILTER_HI_P0D_0_A_H_FILTER_HI_P0DC3_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P0D_0_A_H_FILTER_HI_P0DC3_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P0D_0_A_H_FILTER_HI_P0DC3_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P0D_0_A_H_FILTER_HI_P0DC3_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_H_FILTER_HI_P0D_0_A_H_FILTER_HI_P0DC4_SHIFT _MK_SHIFT_CONST(6) +#define DC_WINC_A_H_FILTER_HI_P0D_0_A_H_FILTER_HI_P0DC4_FIELD _MK_FIELD_CONST(0x3, DC_WINC_A_H_FILTER_HI_P0D_0_A_H_FILTER_HI_P0DC4_SHIFT) +#define DC_WINC_A_H_FILTER_HI_P0D_0_A_H_FILTER_HI_P0DC4_RANGE 7:6 +#define DC_WINC_A_H_FILTER_HI_P0D_0_A_H_FILTER_HI_P0DC4_WOFFSET 0x0 +#define DC_WINC_A_H_FILTER_HI_P0D_0_A_H_FILTER_HI_P0DC4_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P0D_0_A_H_FILTER_HI_P0DC4_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P0D_0_A_H_FILTER_HI_P0DC4_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P0D_0_A_H_FILTER_HI_P0DC4_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_H_FILTER_HI_P0D_0_A_H_FILTER_HI_P0DC5_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_H_FILTER_HI_P0D_0_A_H_FILTER_HI_P0DC5_FIELD _MK_FIELD_CONST(0x3, DC_WINC_A_H_FILTER_HI_P0D_0_A_H_FILTER_HI_P0DC5_SHIFT) +#define DC_WINC_A_H_FILTER_HI_P0D_0_A_H_FILTER_HI_P0DC5_RANGE 9:8 +#define DC_WINC_A_H_FILTER_HI_P0D_0_A_H_FILTER_HI_P0DC5_WOFFSET 0x0 +#define DC_WINC_A_H_FILTER_HI_P0D_0_A_H_FILTER_HI_P0DC5_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P0D_0_A_H_FILTER_HI_P0DC5_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P0D_0_A_H_FILTER_HI_P0DC5_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P0D_0_A_H_FILTER_HI_P0DC5_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_WINC_A_H_FILTER_HI_P0E_0 +#define DC_WINC_A_H_FILTER_HI_P0E_0 _MK_ADDR_CONST(0x637) +#define DC_WINC_A_H_FILTER_HI_P0E_0_SECURE 0x0 +#define DC_WINC_A_H_FILTER_HI_P0E_0_WORD_COUNT 0x1 +#define DC_WINC_A_H_FILTER_HI_P0E_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P0E_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P0E_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P0E_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P0E_0_READ_MASK _MK_MASK_CONST(0x3ff) +#define DC_WINC_A_H_FILTER_HI_P0E_0_WRITE_MASK _MK_MASK_CONST(0x3ff) +#define DC_WINC_A_H_FILTER_HI_P0E_0_A_H_FILTER_HI_P0EC0_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_H_FILTER_HI_P0E_0_A_H_FILTER_HI_P0EC0_FIELD _MK_FIELD_CONST(0x3, DC_WINC_A_H_FILTER_HI_P0E_0_A_H_FILTER_HI_P0EC0_SHIFT) +#define DC_WINC_A_H_FILTER_HI_P0E_0_A_H_FILTER_HI_P0EC0_RANGE 1:0 +#define DC_WINC_A_H_FILTER_HI_P0E_0_A_H_FILTER_HI_P0EC0_WOFFSET 0x0 +#define DC_WINC_A_H_FILTER_HI_P0E_0_A_H_FILTER_HI_P0EC0_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P0E_0_A_H_FILTER_HI_P0EC0_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P0E_0_A_H_FILTER_HI_P0EC0_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P0E_0_A_H_FILTER_HI_P0EC0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_H_FILTER_HI_P0E_0_A_H_FILTER_HI_P0EC1_SHIFT _MK_SHIFT_CONST(2) +#define DC_WINC_A_H_FILTER_HI_P0E_0_A_H_FILTER_HI_P0EC1_FIELD _MK_FIELD_CONST(0x3, DC_WINC_A_H_FILTER_HI_P0E_0_A_H_FILTER_HI_P0EC1_SHIFT) +#define DC_WINC_A_H_FILTER_HI_P0E_0_A_H_FILTER_HI_P0EC1_RANGE 3:2 +#define DC_WINC_A_H_FILTER_HI_P0E_0_A_H_FILTER_HI_P0EC1_WOFFSET 0x0 +#define DC_WINC_A_H_FILTER_HI_P0E_0_A_H_FILTER_HI_P0EC1_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P0E_0_A_H_FILTER_HI_P0EC1_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P0E_0_A_H_FILTER_HI_P0EC1_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P0E_0_A_H_FILTER_HI_P0EC1_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_H_FILTER_HI_P0E_0_A_H_FILTER_HI_P0EC2_SHIFT _MK_SHIFT_CONST(4) +#define DC_WINC_A_H_FILTER_HI_P0E_0_A_H_FILTER_HI_P0EC2_FIELD _MK_FIELD_CONST(0x1, DC_WINC_A_H_FILTER_HI_P0E_0_A_H_FILTER_HI_P0EC2_SHIFT) +#define DC_WINC_A_H_FILTER_HI_P0E_0_A_H_FILTER_HI_P0EC2_RANGE 4:4 +#define DC_WINC_A_H_FILTER_HI_P0E_0_A_H_FILTER_HI_P0EC2_WOFFSET 0x0 +#define DC_WINC_A_H_FILTER_HI_P0E_0_A_H_FILTER_HI_P0EC2_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P0E_0_A_H_FILTER_HI_P0EC2_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P0E_0_A_H_FILTER_HI_P0EC2_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P0E_0_A_H_FILTER_HI_P0EC2_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_H_FILTER_HI_P0E_0_A_H_FILTER_HI_P0EC3_SHIFT _MK_SHIFT_CONST(5) +#define DC_WINC_A_H_FILTER_HI_P0E_0_A_H_FILTER_HI_P0EC3_FIELD _MK_FIELD_CONST(0x1, DC_WINC_A_H_FILTER_HI_P0E_0_A_H_FILTER_HI_P0EC3_SHIFT) +#define DC_WINC_A_H_FILTER_HI_P0E_0_A_H_FILTER_HI_P0EC3_RANGE 5:5 +#define DC_WINC_A_H_FILTER_HI_P0E_0_A_H_FILTER_HI_P0EC3_WOFFSET 0x0 +#define DC_WINC_A_H_FILTER_HI_P0E_0_A_H_FILTER_HI_P0EC3_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P0E_0_A_H_FILTER_HI_P0EC3_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P0E_0_A_H_FILTER_HI_P0EC3_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P0E_0_A_H_FILTER_HI_P0EC3_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_H_FILTER_HI_P0E_0_A_H_FILTER_HI_P0EC4_SHIFT _MK_SHIFT_CONST(6) +#define DC_WINC_A_H_FILTER_HI_P0E_0_A_H_FILTER_HI_P0EC4_FIELD _MK_FIELD_CONST(0x3, DC_WINC_A_H_FILTER_HI_P0E_0_A_H_FILTER_HI_P0EC4_SHIFT) +#define DC_WINC_A_H_FILTER_HI_P0E_0_A_H_FILTER_HI_P0EC4_RANGE 7:6 +#define DC_WINC_A_H_FILTER_HI_P0E_0_A_H_FILTER_HI_P0EC4_WOFFSET 0x0 +#define DC_WINC_A_H_FILTER_HI_P0E_0_A_H_FILTER_HI_P0EC4_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P0E_0_A_H_FILTER_HI_P0EC4_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P0E_0_A_H_FILTER_HI_P0EC4_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P0E_0_A_H_FILTER_HI_P0EC4_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_H_FILTER_HI_P0E_0_A_H_FILTER_HI_P0EC5_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_H_FILTER_HI_P0E_0_A_H_FILTER_HI_P0EC5_FIELD _MK_FIELD_CONST(0x3, DC_WINC_A_H_FILTER_HI_P0E_0_A_H_FILTER_HI_P0EC5_SHIFT) +#define DC_WINC_A_H_FILTER_HI_P0E_0_A_H_FILTER_HI_P0EC5_RANGE 9:8 +#define DC_WINC_A_H_FILTER_HI_P0E_0_A_H_FILTER_HI_P0EC5_WOFFSET 0x0 +#define DC_WINC_A_H_FILTER_HI_P0E_0_A_H_FILTER_HI_P0EC5_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P0E_0_A_H_FILTER_HI_P0EC5_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P0E_0_A_H_FILTER_HI_P0EC5_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P0E_0_A_H_FILTER_HI_P0EC5_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_WINC_A_H_FILTER_HI_P0F_0 +#define DC_WINC_A_H_FILTER_HI_P0F_0 _MK_ADDR_CONST(0x638) +#define DC_WINC_A_H_FILTER_HI_P0F_0_SECURE 0x0 +#define DC_WINC_A_H_FILTER_HI_P0F_0_WORD_COUNT 0x1 +#define DC_WINC_A_H_FILTER_HI_P0F_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P0F_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P0F_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P0F_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P0F_0_READ_MASK _MK_MASK_CONST(0x3ff) +#define DC_WINC_A_H_FILTER_HI_P0F_0_WRITE_MASK _MK_MASK_CONST(0x3ff) +#define DC_WINC_A_H_FILTER_HI_P0F_0_A_H_FILTER_HI_P0FC0_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINC_A_H_FILTER_HI_P0F_0_A_H_FILTER_HI_P0FC0_FIELD _MK_FIELD_CONST(0x3, DC_WINC_A_H_FILTER_HI_P0F_0_A_H_FILTER_HI_P0FC0_SHIFT) +#define DC_WINC_A_H_FILTER_HI_P0F_0_A_H_FILTER_HI_P0FC0_RANGE 1:0 +#define DC_WINC_A_H_FILTER_HI_P0F_0_A_H_FILTER_HI_P0FC0_WOFFSET 0x0 +#define DC_WINC_A_H_FILTER_HI_P0F_0_A_H_FILTER_HI_P0FC0_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P0F_0_A_H_FILTER_HI_P0FC0_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P0F_0_A_H_FILTER_HI_P0FC0_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P0F_0_A_H_FILTER_HI_P0FC0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_H_FILTER_HI_P0F_0_A_H_FILTER_HI_P0FC1_SHIFT _MK_SHIFT_CONST(2) +#define DC_WINC_A_H_FILTER_HI_P0F_0_A_H_FILTER_HI_P0FC1_FIELD _MK_FIELD_CONST(0x3, DC_WINC_A_H_FILTER_HI_P0F_0_A_H_FILTER_HI_P0FC1_SHIFT) +#define DC_WINC_A_H_FILTER_HI_P0F_0_A_H_FILTER_HI_P0FC1_RANGE 3:2 +#define DC_WINC_A_H_FILTER_HI_P0F_0_A_H_FILTER_HI_P0FC1_WOFFSET 0x0 +#define DC_WINC_A_H_FILTER_HI_P0F_0_A_H_FILTER_HI_P0FC1_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P0F_0_A_H_FILTER_HI_P0FC1_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P0F_0_A_H_FILTER_HI_P0FC1_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P0F_0_A_H_FILTER_HI_P0FC1_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_H_FILTER_HI_P0F_0_A_H_FILTER_HI_P0FC2_SHIFT _MK_SHIFT_CONST(4) +#define DC_WINC_A_H_FILTER_HI_P0F_0_A_H_FILTER_HI_P0FC2_FIELD _MK_FIELD_CONST(0x1, DC_WINC_A_H_FILTER_HI_P0F_0_A_H_FILTER_HI_P0FC2_SHIFT) +#define DC_WINC_A_H_FILTER_HI_P0F_0_A_H_FILTER_HI_P0FC2_RANGE 4:4 +#define DC_WINC_A_H_FILTER_HI_P0F_0_A_H_FILTER_HI_P0FC2_WOFFSET 0x0 +#define DC_WINC_A_H_FILTER_HI_P0F_0_A_H_FILTER_HI_P0FC2_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P0F_0_A_H_FILTER_HI_P0FC2_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P0F_0_A_H_FILTER_HI_P0FC2_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P0F_0_A_H_FILTER_HI_P0FC2_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_H_FILTER_HI_P0F_0_A_H_FILTER_HI_P0FC3_SHIFT _MK_SHIFT_CONST(5) +#define DC_WINC_A_H_FILTER_HI_P0F_0_A_H_FILTER_HI_P0FC3_FIELD _MK_FIELD_CONST(0x1, DC_WINC_A_H_FILTER_HI_P0F_0_A_H_FILTER_HI_P0FC3_SHIFT) +#define DC_WINC_A_H_FILTER_HI_P0F_0_A_H_FILTER_HI_P0FC3_RANGE 5:5 +#define DC_WINC_A_H_FILTER_HI_P0F_0_A_H_FILTER_HI_P0FC3_WOFFSET 0x0 +#define DC_WINC_A_H_FILTER_HI_P0F_0_A_H_FILTER_HI_P0FC3_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P0F_0_A_H_FILTER_HI_P0FC3_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P0F_0_A_H_FILTER_HI_P0FC3_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P0F_0_A_H_FILTER_HI_P0FC3_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_H_FILTER_HI_P0F_0_A_H_FILTER_HI_P0FC4_SHIFT _MK_SHIFT_CONST(6) +#define DC_WINC_A_H_FILTER_HI_P0F_0_A_H_FILTER_HI_P0FC4_FIELD _MK_FIELD_CONST(0x3, DC_WINC_A_H_FILTER_HI_P0F_0_A_H_FILTER_HI_P0FC4_SHIFT) +#define DC_WINC_A_H_FILTER_HI_P0F_0_A_H_FILTER_HI_P0FC4_RANGE 7:6 +#define DC_WINC_A_H_FILTER_HI_P0F_0_A_H_FILTER_HI_P0FC4_WOFFSET 0x0 +#define DC_WINC_A_H_FILTER_HI_P0F_0_A_H_FILTER_HI_P0FC4_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P0F_0_A_H_FILTER_HI_P0FC4_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P0F_0_A_H_FILTER_HI_P0FC4_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P0F_0_A_H_FILTER_HI_P0FC4_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINC_A_H_FILTER_HI_P0F_0_A_H_FILTER_HI_P0FC5_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINC_A_H_FILTER_HI_P0F_0_A_H_FILTER_HI_P0FC5_FIELD _MK_FIELD_CONST(0x3, DC_WINC_A_H_FILTER_HI_P0F_0_A_H_FILTER_HI_P0FC5_SHIFT) +#define DC_WINC_A_H_FILTER_HI_P0F_0_A_H_FILTER_HI_P0FC5_RANGE 9:8 +#define DC_WINC_A_H_FILTER_HI_P0F_0_A_H_FILTER_HI_P0FC5_WOFFSET 0x0 +#define DC_WINC_A_H_FILTER_HI_P0F_0_A_H_FILTER_HI_P0FC5_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P0F_0_A_H_FILTER_HI_P0FC5_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P0F_0_A_H_FILTER_HI_P0FC5_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINC_A_H_FILTER_HI_P0F_0_A_H_FILTER_HI_P0FC5_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_WIN_A_WIN_OPTIONS_0 +#define DC_WIN_A_WIN_OPTIONS_0 _MK_ADDR_CONST(0x700) +#define DC_WIN_A_WIN_OPTIONS_0_SECURE 0x0 +#define DC_WIN_A_WIN_OPTIONS_0_WORD_COUNT 0x1 +#define DC_WIN_A_WIN_OPTIONS_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WIN_A_WIN_OPTIONS_0_RESET_MASK _MK_MASK_CONST(0xc0814010) +#define DC_WIN_A_WIN_OPTIONS_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WIN_A_WIN_OPTIONS_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WIN_A_WIN_OPTIONS_0_READ_MASK _MK_MASK_CONST(0xc0d55555) +#define DC_WIN_A_WIN_OPTIONS_0_WRITE_MASK _MK_MASK_CONST(0xc0d55555) +#define DC_WIN_A_WIN_OPTIONS_0_A_H_DIRECTION_SHIFT _MK_SHIFT_CONST(0) +#define DC_WIN_A_WIN_OPTIONS_0_A_H_DIRECTION_FIELD _MK_FIELD_CONST(0x1, DC_WIN_A_WIN_OPTIONS_0_A_H_DIRECTION_SHIFT) +#define DC_WIN_A_WIN_OPTIONS_0_A_H_DIRECTION_RANGE 0:0 +#define DC_WIN_A_WIN_OPTIONS_0_A_H_DIRECTION_WOFFSET 0x0 +#define DC_WIN_A_WIN_OPTIONS_0_A_H_DIRECTION_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WIN_A_WIN_OPTIONS_0_A_H_DIRECTION_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WIN_A_WIN_OPTIONS_0_A_H_DIRECTION_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WIN_A_WIN_OPTIONS_0_A_H_DIRECTION_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WIN_A_WIN_OPTIONS_0_A_H_DIRECTION_INCREMENT _MK_ENUM_CONST(0) +#define DC_WIN_A_WIN_OPTIONS_0_A_H_DIRECTION_DECREMENT _MK_ENUM_CONST(1) + +#define DC_WIN_A_WIN_OPTIONS_0_A_V_DIRECTION_SHIFT _MK_SHIFT_CONST(2) +#define DC_WIN_A_WIN_OPTIONS_0_A_V_DIRECTION_FIELD _MK_FIELD_CONST(0x1, DC_WIN_A_WIN_OPTIONS_0_A_V_DIRECTION_SHIFT) +#define DC_WIN_A_WIN_OPTIONS_0_A_V_DIRECTION_RANGE 2:2 +#define DC_WIN_A_WIN_OPTIONS_0_A_V_DIRECTION_WOFFSET 0x0 +#define DC_WIN_A_WIN_OPTIONS_0_A_V_DIRECTION_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WIN_A_WIN_OPTIONS_0_A_V_DIRECTION_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WIN_A_WIN_OPTIONS_0_A_V_DIRECTION_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WIN_A_WIN_OPTIONS_0_A_V_DIRECTION_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WIN_A_WIN_OPTIONS_0_A_V_DIRECTION_INCREMENT _MK_ENUM_CONST(0) +#define DC_WIN_A_WIN_OPTIONS_0_A_V_DIRECTION_DECREMENT _MK_ENUM_CONST(1) + +#define DC_WIN_A_WIN_OPTIONS_0_A_SCAN_COLUMN_SHIFT _MK_SHIFT_CONST(4) +#define DC_WIN_A_WIN_OPTIONS_0_A_SCAN_COLUMN_FIELD _MK_FIELD_CONST(0x1, DC_WIN_A_WIN_OPTIONS_0_A_SCAN_COLUMN_SHIFT) +#define DC_WIN_A_WIN_OPTIONS_0_A_SCAN_COLUMN_RANGE 4:4 +#define DC_WIN_A_WIN_OPTIONS_0_A_SCAN_COLUMN_WOFFSET 0x0 +#define DC_WIN_A_WIN_OPTIONS_0_A_SCAN_COLUMN_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WIN_A_WIN_OPTIONS_0_A_SCAN_COLUMN_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_WIN_A_WIN_OPTIONS_0_A_SCAN_COLUMN_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WIN_A_WIN_OPTIONS_0_A_SCAN_COLUMN_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WIN_A_WIN_OPTIONS_0_A_SCAN_COLUMN_DISABLE _MK_ENUM_CONST(0) +#define DC_WIN_A_WIN_OPTIONS_0_A_SCAN_COLUMN_ENABLE _MK_ENUM_CONST(1) + +#define DC_WIN_A_WIN_OPTIONS_0_A_COLOR_EXPAND_SHIFT _MK_SHIFT_CONST(6) +#define DC_WIN_A_WIN_OPTIONS_0_A_COLOR_EXPAND_FIELD _MK_FIELD_CONST(0x1, DC_WIN_A_WIN_OPTIONS_0_A_COLOR_EXPAND_SHIFT) +#define DC_WIN_A_WIN_OPTIONS_0_A_COLOR_EXPAND_RANGE 6:6 +#define DC_WIN_A_WIN_OPTIONS_0_A_COLOR_EXPAND_WOFFSET 0x0 +#define DC_WIN_A_WIN_OPTIONS_0_A_COLOR_EXPAND_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WIN_A_WIN_OPTIONS_0_A_COLOR_EXPAND_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WIN_A_WIN_OPTIONS_0_A_COLOR_EXPAND_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WIN_A_WIN_OPTIONS_0_A_COLOR_EXPAND_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WIN_A_WIN_OPTIONS_0_A_COLOR_EXPAND_DISABLE _MK_ENUM_CONST(0) +#define DC_WIN_A_WIN_OPTIONS_0_A_COLOR_EXPAND_ENABLE _MK_ENUM_CONST(1) + +#define DC_WIN_A_WIN_OPTIONS_0_A_H_FILTER_ENABLE_SHIFT _MK_SHIFT_CONST(8) +#define DC_WIN_A_WIN_OPTIONS_0_A_H_FILTER_ENABLE_FIELD _MK_FIELD_CONST(0x1, DC_WIN_A_WIN_OPTIONS_0_A_H_FILTER_ENABLE_SHIFT) +#define DC_WIN_A_WIN_OPTIONS_0_A_H_FILTER_ENABLE_RANGE 8:8 +#define DC_WIN_A_WIN_OPTIONS_0_A_H_FILTER_ENABLE_WOFFSET 0x0 +#define DC_WIN_A_WIN_OPTIONS_0_A_H_FILTER_ENABLE_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WIN_A_WIN_OPTIONS_0_A_H_FILTER_ENABLE_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WIN_A_WIN_OPTIONS_0_A_H_FILTER_ENABLE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WIN_A_WIN_OPTIONS_0_A_H_FILTER_ENABLE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WIN_A_WIN_OPTIONS_0_A_H_FILTER_ENABLE_DISABLE _MK_ENUM_CONST(0) +#define DC_WIN_A_WIN_OPTIONS_0_A_H_FILTER_ENABLE_ENABLE _MK_ENUM_CONST(1) + +#define DC_WIN_A_WIN_OPTIONS_0_A_V_FILTER_ENABLE_SHIFT _MK_SHIFT_CONST(10) +#define DC_WIN_A_WIN_OPTIONS_0_A_V_FILTER_ENABLE_FIELD _MK_FIELD_CONST(0x1, DC_WIN_A_WIN_OPTIONS_0_A_V_FILTER_ENABLE_SHIFT) +#define DC_WIN_A_WIN_OPTIONS_0_A_V_FILTER_ENABLE_RANGE 10:10 +#define DC_WIN_A_WIN_OPTIONS_0_A_V_FILTER_ENABLE_WOFFSET 0x0 +#define DC_WIN_A_WIN_OPTIONS_0_A_V_FILTER_ENABLE_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WIN_A_WIN_OPTIONS_0_A_V_FILTER_ENABLE_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WIN_A_WIN_OPTIONS_0_A_V_FILTER_ENABLE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WIN_A_WIN_OPTIONS_0_A_V_FILTER_ENABLE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WIN_A_WIN_OPTIONS_0_A_V_FILTER_ENABLE_DISABLE _MK_ENUM_CONST(0) +#define DC_WIN_A_WIN_OPTIONS_0_A_V_FILTER_ENABLE_ENABLE _MK_ENUM_CONST(1) + +#define DC_WIN_A_WIN_OPTIONS_0_A_V_FILTER_OPTIMIZE_SHIFT _MK_SHIFT_CONST(12) +#define DC_WIN_A_WIN_OPTIONS_0_A_V_FILTER_OPTIMIZE_FIELD _MK_FIELD_CONST(0x1, DC_WIN_A_WIN_OPTIONS_0_A_V_FILTER_OPTIMIZE_SHIFT) +#define DC_WIN_A_WIN_OPTIONS_0_A_V_FILTER_OPTIMIZE_RANGE 12:12 +#define DC_WIN_A_WIN_OPTIONS_0_A_V_FILTER_OPTIMIZE_WOFFSET 0x0 +#define DC_WIN_A_WIN_OPTIONS_0_A_V_FILTER_OPTIMIZE_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WIN_A_WIN_OPTIONS_0_A_V_FILTER_OPTIMIZE_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WIN_A_WIN_OPTIONS_0_A_V_FILTER_OPTIMIZE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WIN_A_WIN_OPTIONS_0_A_V_FILTER_OPTIMIZE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WIN_A_WIN_OPTIONS_0_A_V_FILTER_OPTIMIZE_DISABLE _MK_ENUM_CONST(0) +#define DC_WIN_A_WIN_OPTIONS_0_A_V_FILTER_OPTIMIZE_ENABLE _MK_ENUM_CONST(1) + +#define DC_WIN_A_WIN_OPTIONS_0_A_V_FILTER_UV_ALIGN_SHIFT _MK_SHIFT_CONST(14) +#define DC_WIN_A_WIN_OPTIONS_0_A_V_FILTER_UV_ALIGN_FIELD _MK_FIELD_CONST(0x1, DC_WIN_A_WIN_OPTIONS_0_A_V_FILTER_UV_ALIGN_SHIFT) +#define DC_WIN_A_WIN_OPTIONS_0_A_V_FILTER_UV_ALIGN_RANGE 14:14 +#define DC_WIN_A_WIN_OPTIONS_0_A_V_FILTER_UV_ALIGN_WOFFSET 0x0 +#define DC_WIN_A_WIN_OPTIONS_0_A_V_FILTER_UV_ALIGN_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WIN_A_WIN_OPTIONS_0_A_V_FILTER_UV_ALIGN_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_WIN_A_WIN_OPTIONS_0_A_V_FILTER_UV_ALIGN_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WIN_A_WIN_OPTIONS_0_A_V_FILTER_UV_ALIGN_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WIN_A_WIN_OPTIONS_0_A_V_FILTER_UV_ALIGN_DISABLE _MK_ENUM_CONST(0) +#define DC_WIN_A_WIN_OPTIONS_0_A_V_FILTER_UV_ALIGN_ENABLE _MK_ENUM_CONST(1) + +#define DC_WIN_A_WIN_OPTIONS_0_A_CP_ENABLE_SHIFT _MK_SHIFT_CONST(16) +#define DC_WIN_A_WIN_OPTIONS_0_A_CP_ENABLE_FIELD _MK_FIELD_CONST(0x1, DC_WIN_A_WIN_OPTIONS_0_A_CP_ENABLE_SHIFT) +#define DC_WIN_A_WIN_OPTIONS_0_A_CP_ENABLE_RANGE 16:16 +#define DC_WIN_A_WIN_OPTIONS_0_A_CP_ENABLE_WOFFSET 0x0 +#define DC_WIN_A_WIN_OPTIONS_0_A_CP_ENABLE_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WIN_A_WIN_OPTIONS_0_A_CP_ENABLE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_WIN_A_WIN_OPTIONS_0_A_CP_ENABLE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WIN_A_WIN_OPTIONS_0_A_CP_ENABLE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WIN_A_WIN_OPTIONS_0_A_CP_ENABLE_DISABLE _MK_ENUM_CONST(0) +#define DC_WIN_A_WIN_OPTIONS_0_A_CP_ENABLE_ENABLE _MK_ENUM_CONST(1) + +#define DC_WIN_A_WIN_OPTIONS_0_A_CSC_ENABLE_SHIFT _MK_SHIFT_CONST(18) +#define DC_WIN_A_WIN_OPTIONS_0_A_CSC_ENABLE_FIELD _MK_FIELD_CONST(0x1, DC_WIN_A_WIN_OPTIONS_0_A_CSC_ENABLE_SHIFT) +#define DC_WIN_A_WIN_OPTIONS_0_A_CSC_ENABLE_RANGE 18:18 +#define DC_WIN_A_WIN_OPTIONS_0_A_CSC_ENABLE_WOFFSET 0x0 +#define DC_WIN_A_WIN_OPTIONS_0_A_CSC_ENABLE_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WIN_A_WIN_OPTIONS_0_A_CSC_ENABLE_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WIN_A_WIN_OPTIONS_0_A_CSC_ENABLE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WIN_A_WIN_OPTIONS_0_A_CSC_ENABLE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WIN_A_WIN_OPTIONS_0_A_CSC_ENABLE_DISABLE _MK_ENUM_CONST(0) +#define DC_WIN_A_WIN_OPTIONS_0_A_CSC_ENABLE_ENABLE _MK_ENUM_CONST(1) + +#define DC_WIN_A_WIN_OPTIONS_0_A_DV_ENABLE_SHIFT _MK_SHIFT_CONST(20) +#define DC_WIN_A_WIN_OPTIONS_0_A_DV_ENABLE_FIELD _MK_FIELD_CONST(0x1, DC_WIN_A_WIN_OPTIONS_0_A_DV_ENABLE_SHIFT) +#define DC_WIN_A_WIN_OPTIONS_0_A_DV_ENABLE_RANGE 20:20 +#define DC_WIN_A_WIN_OPTIONS_0_A_DV_ENABLE_WOFFSET 0x0 +#define DC_WIN_A_WIN_OPTIONS_0_A_DV_ENABLE_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WIN_A_WIN_OPTIONS_0_A_DV_ENABLE_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WIN_A_WIN_OPTIONS_0_A_DV_ENABLE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WIN_A_WIN_OPTIONS_0_A_DV_ENABLE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WIN_A_WIN_OPTIONS_0_A_DV_ENABLE_DISABLE _MK_ENUM_CONST(0) +#define DC_WIN_A_WIN_OPTIONS_0_A_DV_ENABLE_ENABLE _MK_ENUM_CONST(1) + +#define DC_WIN_A_WIN_OPTIONS_0_A_YUV_RANGE_EXPAND_SHIFT _MK_SHIFT_CONST(22) +#define DC_WIN_A_WIN_OPTIONS_0_A_YUV_RANGE_EXPAND_FIELD _MK_FIELD_CONST(0x1, DC_WIN_A_WIN_OPTIONS_0_A_YUV_RANGE_EXPAND_SHIFT) +#define DC_WIN_A_WIN_OPTIONS_0_A_YUV_RANGE_EXPAND_RANGE 22:22 +#define DC_WIN_A_WIN_OPTIONS_0_A_YUV_RANGE_EXPAND_WOFFSET 0x0 +#define DC_WIN_A_WIN_OPTIONS_0_A_YUV_RANGE_EXPAND_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WIN_A_WIN_OPTIONS_0_A_YUV_RANGE_EXPAND_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WIN_A_WIN_OPTIONS_0_A_YUV_RANGE_EXPAND_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WIN_A_WIN_OPTIONS_0_A_YUV_RANGE_EXPAND_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WIN_A_WIN_OPTIONS_0_A_YUV_RANGE_EXPAND_DISABLE _MK_ENUM_CONST(0) +#define DC_WIN_A_WIN_OPTIONS_0_A_YUV_RANGE_EXPAND_ENABLE _MK_ENUM_CONST(1) + +#define DC_WIN_A_WIN_OPTIONS_0_A_INTERLACE_ENABLE_SHIFT _MK_SHIFT_CONST(23) +#define DC_WIN_A_WIN_OPTIONS_0_A_INTERLACE_ENABLE_FIELD _MK_FIELD_CONST(0x1, DC_WIN_A_WIN_OPTIONS_0_A_INTERLACE_ENABLE_SHIFT) +#define DC_WIN_A_WIN_OPTIONS_0_A_INTERLACE_ENABLE_RANGE 23:23 +#define DC_WIN_A_WIN_OPTIONS_0_A_INTERLACE_ENABLE_WOFFSET 0x0 +#define DC_WIN_A_WIN_OPTIONS_0_A_INTERLACE_ENABLE_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WIN_A_WIN_OPTIONS_0_A_INTERLACE_ENABLE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_WIN_A_WIN_OPTIONS_0_A_INTERLACE_ENABLE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WIN_A_WIN_OPTIONS_0_A_INTERLACE_ENABLE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WIN_A_WIN_OPTIONS_0_A_INTERLACE_ENABLE_DISABLE _MK_ENUM_CONST(0) +#define DC_WIN_A_WIN_OPTIONS_0_A_INTERLACE_ENABLE_ENABLE _MK_ENUM_CONST(1) + +#define DC_WIN_A_WIN_OPTIONS_0_A_WIN_ENABLE_SHIFT _MK_SHIFT_CONST(30) +#define DC_WIN_A_WIN_OPTIONS_0_A_WIN_ENABLE_FIELD _MK_FIELD_CONST(0x1, DC_WIN_A_WIN_OPTIONS_0_A_WIN_ENABLE_SHIFT) +#define DC_WIN_A_WIN_OPTIONS_0_A_WIN_ENABLE_RANGE 30:30 +#define DC_WIN_A_WIN_OPTIONS_0_A_WIN_ENABLE_WOFFSET 0x0 +#define DC_WIN_A_WIN_OPTIONS_0_A_WIN_ENABLE_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WIN_A_WIN_OPTIONS_0_A_WIN_ENABLE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_WIN_A_WIN_OPTIONS_0_A_WIN_ENABLE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WIN_A_WIN_OPTIONS_0_A_WIN_ENABLE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WIN_A_WIN_OPTIONS_0_A_WIN_ENABLE_DISABLE _MK_ENUM_CONST(0) +#define DC_WIN_A_WIN_OPTIONS_0_A_WIN_ENABLE_ENABLE _MK_ENUM_CONST(1) + +#define DC_WIN_A_WIN_OPTIONS_0_A_H_FILTER_MODE_SHIFT _MK_SHIFT_CONST(31) +#define DC_WIN_A_WIN_OPTIONS_0_A_H_FILTER_MODE_FIELD _MK_FIELD_CONST(0x1, DC_WIN_A_WIN_OPTIONS_0_A_H_FILTER_MODE_SHIFT) +#define DC_WIN_A_WIN_OPTIONS_0_A_H_FILTER_MODE_RANGE 31:31 +#define DC_WIN_A_WIN_OPTIONS_0_A_H_FILTER_MODE_WOFFSET 0x0 +#define DC_WIN_A_WIN_OPTIONS_0_A_H_FILTER_MODE_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WIN_A_WIN_OPTIONS_0_A_H_FILTER_MODE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_WIN_A_WIN_OPTIONS_0_A_H_FILTER_MODE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WIN_A_WIN_OPTIONS_0_A_H_FILTER_MODE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WIN_A_WIN_OPTIONS_0_A_H_FILTER_MODE_OLD _MK_ENUM_CONST(0) +#define DC_WIN_A_WIN_OPTIONS_0_A_H_FILTER_MODE_NEW _MK_ENUM_CONST(1) + + +// Register DC_WIN_A_BYTE_SWAP_0 +#define DC_WIN_A_BYTE_SWAP_0 _MK_ADDR_CONST(0x701) +#define DC_WIN_A_BYTE_SWAP_0_SECURE 0x0 +#define DC_WIN_A_BYTE_SWAP_0_WORD_COUNT 0x1 +#define DC_WIN_A_BYTE_SWAP_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WIN_A_BYTE_SWAP_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WIN_A_BYTE_SWAP_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WIN_A_BYTE_SWAP_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WIN_A_BYTE_SWAP_0_READ_MASK _MK_MASK_CONST(0x7) +#define DC_WIN_A_BYTE_SWAP_0_WRITE_MASK _MK_MASK_CONST(0x7) +#define DC_WIN_A_BYTE_SWAP_0_A_BYTE_SWAP_SHIFT _MK_SHIFT_CONST(0) +#define DC_WIN_A_BYTE_SWAP_0_A_BYTE_SWAP_FIELD _MK_FIELD_CONST(0x7, DC_WIN_A_BYTE_SWAP_0_A_BYTE_SWAP_SHIFT) +#define DC_WIN_A_BYTE_SWAP_0_A_BYTE_SWAP_RANGE 2:0 +#define DC_WIN_A_BYTE_SWAP_0_A_BYTE_SWAP_WOFFSET 0x0 +#define DC_WIN_A_BYTE_SWAP_0_A_BYTE_SWAP_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WIN_A_BYTE_SWAP_0_A_BYTE_SWAP_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WIN_A_BYTE_SWAP_0_A_BYTE_SWAP_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WIN_A_BYTE_SWAP_0_A_BYTE_SWAP_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WIN_A_BYTE_SWAP_0_A_BYTE_SWAP_NOSWAP _MK_ENUM_CONST(0) +#define DC_WIN_A_BYTE_SWAP_0_A_BYTE_SWAP_SWAP2 _MK_ENUM_CONST(1) +#define DC_WIN_A_BYTE_SWAP_0_A_BYTE_SWAP_SWAP4 _MK_ENUM_CONST(2) +#define DC_WIN_A_BYTE_SWAP_0_A_BYTE_SWAP_SWAP4HW _MK_ENUM_CONST(3) +#define DC_WIN_A_BYTE_SWAP_0_A_BYTE_SWAP_SWAP02 _MK_ENUM_CONST(4) +#define DC_WIN_A_BYTE_SWAP_0_A_BYTE_SWAP_SWAPLEFT _MK_ENUM_CONST(5) + + +// Register DC_WIN_A_BUFFER_CONTROL_0 +#define DC_WIN_A_BUFFER_CONTROL_0 _MK_ADDR_CONST(0x702) +#define DC_WIN_A_BUFFER_CONTROL_0_SECURE 0x0 +#define DC_WIN_A_BUFFER_CONTROL_0_WORD_COUNT 0x1 +#define DC_WIN_A_BUFFER_CONTROL_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WIN_A_BUFFER_CONTROL_0_RESET_MASK _MK_MASK_CONST(0x7) +#define DC_WIN_A_BUFFER_CONTROL_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WIN_A_BUFFER_CONTROL_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WIN_A_BUFFER_CONTROL_0_READ_MASK _MK_MASK_CONST(0x7) +#define DC_WIN_A_BUFFER_CONTROL_0_WRITE_MASK _MK_MASK_CONST(0x7) +#define DC_WIN_A_BUFFER_CONTROL_0_A_BUFFER_CONTROL_SHIFT _MK_SHIFT_CONST(0) +#define DC_WIN_A_BUFFER_CONTROL_0_A_BUFFER_CONTROL_FIELD _MK_FIELD_CONST(0x7, DC_WIN_A_BUFFER_CONTROL_0_A_BUFFER_CONTROL_SHIFT) +#define DC_WIN_A_BUFFER_CONTROL_0_A_BUFFER_CONTROL_RANGE 2:0 +#define DC_WIN_A_BUFFER_CONTROL_0_A_BUFFER_CONTROL_WOFFSET 0x0 +#define DC_WIN_A_BUFFER_CONTROL_0_A_BUFFER_CONTROL_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WIN_A_BUFFER_CONTROL_0_A_BUFFER_CONTROL_DEFAULT_MASK _MK_MASK_CONST(0x7) +#define DC_WIN_A_BUFFER_CONTROL_0_A_BUFFER_CONTROL_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WIN_A_BUFFER_CONTROL_0_A_BUFFER_CONTROL_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WIN_A_BUFFER_CONTROL_0_A_BUFFER_CONTROL_HOST _MK_ENUM_CONST(0) +#define DC_WIN_A_BUFFER_CONTROL_0_A_BUFFER_CONTROL_VI _MK_ENUM_CONST(1) +#define DC_WIN_A_BUFFER_CONTROL_0_A_BUFFER_CONTROL_SB2D _MK_ENUM_CONST(4) + + +// Register DC_WIN_A_COLOR_DEPTH_0 +#define DC_WIN_A_COLOR_DEPTH_0 _MK_ADDR_CONST(0x703) +#define DC_WIN_A_COLOR_DEPTH_0_SECURE 0x0 +#define DC_WIN_A_COLOR_DEPTH_0_WORD_COUNT 0x1 +#define DC_WIN_A_COLOR_DEPTH_0_RESET_VAL _MK_MASK_CONST(0xc) +#define DC_WIN_A_COLOR_DEPTH_0_RESET_MASK _MK_MASK_CONST(0x7f) +#define DC_WIN_A_COLOR_DEPTH_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WIN_A_COLOR_DEPTH_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WIN_A_COLOR_DEPTH_0_READ_MASK _MK_MASK_CONST(0x7f) +#define DC_WIN_A_COLOR_DEPTH_0_WRITE_MASK _MK_MASK_CONST(0x7f) +#define DC_WIN_A_COLOR_DEPTH_0_A_COLOR_DEPTH_SHIFT _MK_SHIFT_CONST(0) +#define DC_WIN_A_COLOR_DEPTH_0_A_COLOR_DEPTH_FIELD _MK_FIELD_CONST(0x7f, DC_WIN_A_COLOR_DEPTH_0_A_COLOR_DEPTH_SHIFT) +#define DC_WIN_A_COLOR_DEPTH_0_A_COLOR_DEPTH_RANGE 6:0 +#define DC_WIN_A_COLOR_DEPTH_0_A_COLOR_DEPTH_WOFFSET 0x0 +#define DC_WIN_A_COLOR_DEPTH_0_A_COLOR_DEPTH_DEFAULT _MK_MASK_CONST(0xc) +#define DC_WIN_A_COLOR_DEPTH_0_A_COLOR_DEPTH_DEFAULT_MASK _MK_MASK_CONST(0x7f) +#define DC_WIN_A_COLOR_DEPTH_0_A_COLOR_DEPTH_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WIN_A_COLOR_DEPTH_0_A_COLOR_DEPTH_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WIN_A_COLOR_DEPTH_0_A_COLOR_DEPTH_INIT_ENUM B8G8R8A8 +#define DC_WIN_A_COLOR_DEPTH_0_A_COLOR_DEPTH_T_P8 _MK_ENUM_CONST(3) +#define DC_WIN_A_COLOR_DEPTH_0_A_COLOR_DEPTH_P8 _MK_ENUM_CONST(3) +#define DC_WIN_A_COLOR_DEPTH_0_A_COLOR_DEPTH_T_A4R4G4B4 _MK_ENUM_CONST(4) +#define DC_WIN_A_COLOR_DEPTH_0_A_COLOR_DEPTH_B4G4R4A4 _MK_ENUM_CONST(4) +#define DC_WIN_A_COLOR_DEPTH_0_A_COLOR_DEPTH_T_A1R5G5B5 _MK_ENUM_CONST(5) +#define DC_WIN_A_COLOR_DEPTH_0_A_COLOR_DEPTH_B5G5R5A _MK_ENUM_CONST(5) +#define DC_WIN_A_COLOR_DEPTH_0_A_COLOR_DEPTH_T_R5G6B5 _MK_ENUM_CONST(6) +#define DC_WIN_A_COLOR_DEPTH_0_A_COLOR_DEPTH_B5G6R5 _MK_ENUM_CONST(6) +#define DC_WIN_A_COLOR_DEPTH_0_A_COLOR_DEPTH_T_R5G5B5A1 _MK_ENUM_CONST(7) +#define DC_WIN_A_COLOR_DEPTH_0_A_COLOR_DEPTH_AB5G5R5 _MK_ENUM_CONST(7) +#define DC_WIN_A_COLOR_DEPTH_0_A_COLOR_DEPTH_T_A8R8G8B8 _MK_ENUM_CONST(12) +#define DC_WIN_A_COLOR_DEPTH_0_A_COLOR_DEPTH_B8G8R8A8 _MK_ENUM_CONST(12) +#define DC_WIN_A_COLOR_DEPTH_0_A_COLOR_DEPTH_T_A8B8G8R8 _MK_ENUM_CONST(13) +#define DC_WIN_A_COLOR_DEPTH_0_A_COLOR_DEPTH_R8G8B8A8 _MK_ENUM_CONST(13) +#define DC_WIN_A_COLOR_DEPTH_0_A_COLOR_DEPTH_T_U8_Y8__V8_Y8 _MK_ENUM_CONST(16) +#define DC_WIN_A_COLOR_DEPTH_0_A_COLOR_DEPTH_CbYCrY422 _MK_ENUM_CONST(16) +#define DC_WIN_A_COLOR_DEPTH_0_A_COLOR_DEPTH_YCbCr422 _MK_ENUM_CONST(16) +#define DC_WIN_A_COLOR_DEPTH_0_A_COLOR_DEPTH_T_U8_Y8__V8_Y8_TRUE _MK_ENUM_CONST(17) +#define DC_WIN_A_COLOR_DEPTH_0_A_COLOR_DEPTH_UYVY422 _MK_ENUM_CONST(17) +#define DC_WIN_A_COLOR_DEPTH_0_A_COLOR_DEPTH_YUV422 _MK_ENUM_CONST(17) +#define DC_WIN_A_COLOR_DEPTH_0_A_COLOR_DEPTH_T_Y8___U8___V8_N420 _MK_ENUM_CONST(18) +#define DC_WIN_A_COLOR_DEPTH_0_A_COLOR_DEPTH_YCbCr420P _MK_ENUM_CONST(18) +#define DC_WIN_A_COLOR_DEPTH_0_A_COLOR_DEPTH_T_Y8___U8___V8_N420_TRUE _MK_ENUM_CONST(19) +#define DC_WIN_A_COLOR_DEPTH_0_A_COLOR_DEPTH_YUV420P _MK_ENUM_CONST(19) +#define DC_WIN_A_COLOR_DEPTH_0_A_COLOR_DEPTH_T_Y8___U8___V8_N422 _MK_ENUM_CONST(20) +#define DC_WIN_A_COLOR_DEPTH_0_A_COLOR_DEPTH_YCbCr422P _MK_ENUM_CONST(20) +#define DC_WIN_A_COLOR_DEPTH_0_A_COLOR_DEPTH_T_Y8___U8___V8_N422_TRUE _MK_ENUM_CONST(21) +#define DC_WIN_A_COLOR_DEPTH_0_A_COLOR_DEPTH_YUV422P _MK_ENUM_CONST(21) +#define DC_WIN_A_COLOR_DEPTH_0_A_COLOR_DEPTH_T_Y8___U8___V8_N422R _MK_ENUM_CONST(22) +#define DC_WIN_A_COLOR_DEPTH_0_A_COLOR_DEPTH_YCbCr422RP _MK_ENUM_CONST(22) +#define DC_WIN_A_COLOR_DEPTH_0_A_COLOR_DEPTH_YCbCr422R _MK_ENUM_CONST(22) +#define DC_WIN_A_COLOR_DEPTH_0_A_COLOR_DEPTH_T_Y8___U8___V8_N422R_TRUE _MK_ENUM_CONST(23) +#define DC_WIN_A_COLOR_DEPTH_0_A_COLOR_DEPTH_YUV422RP _MK_ENUM_CONST(23) +#define DC_WIN_A_COLOR_DEPTH_0_A_COLOR_DEPTH_YUV422R _MK_ENUM_CONST(23) +#define DC_WIN_A_COLOR_DEPTH_0_A_COLOR_DEPTH_T_V8_Y8__U8_Y8 _MK_ENUM_CONST(24) +#define DC_WIN_A_COLOR_DEPTH_0_A_COLOR_DEPTH_CrYCbY422 _MK_ENUM_CONST(24) +#define DC_WIN_A_COLOR_DEPTH_0_A_COLOR_DEPTH_T_V8_Y8__U8_Y8_TRUE _MK_ENUM_CONST(25) +#define DC_WIN_A_COLOR_DEPTH_0_A_COLOR_DEPTH_VYUY422 _MK_ENUM_CONST(25) +#define DC_WIN_A_COLOR_DEPTH_0_A_COLOR_DEPTH_T_Y8_U8__Y8_V8 _MK_ENUM_CONST(61) +#define DC_WIN_A_COLOR_DEPTH_0_A_COLOR_DEPTH_YCbYCr422 _MK_ENUM_CONST(61) +#define DC_WIN_A_COLOR_DEPTH_0_A_COLOR_DEPTH_T_Y8_U8__Y8_V8_TRUE _MK_ENUM_CONST(62) +#define DC_WIN_A_COLOR_DEPTH_0_A_COLOR_DEPTH_YUYV422 _MK_ENUM_CONST(62) +#define DC_WIN_A_COLOR_DEPTH_0_A_COLOR_DEPTH_T_Y8_V8__Y8_U8 _MK_ENUM_CONST(63) +#define DC_WIN_A_COLOR_DEPTH_0_A_COLOR_DEPTH_YCrYCb422 _MK_ENUM_CONST(63) +#define DC_WIN_A_COLOR_DEPTH_0_A_COLOR_DEPTH_T_Y8_V8__Y8_U8_TRUE _MK_ENUM_CONST(64) +#define DC_WIN_A_COLOR_DEPTH_0_A_COLOR_DEPTH_YVYU422 _MK_ENUM_CONST(64) +#define DC_WIN_A_COLOR_DEPTH_0_A_COLOR_DEPTH_T_R8G8B8X8 _MK_ENUM_CONST(65) +#define DC_WIN_A_COLOR_DEPTH_0_A_COLOR_DEPTH_T_B8G8R8X8 _MK_ENUM_CONST(66) +#define DC_WIN_A_COLOR_DEPTH_0_A_COLOR_DEPTH_T_Y8 _MK_ENUM_CONST(26) +#define DC_WIN_A_COLOR_DEPTH_0_A_COLOR_DEPTH_Y8 _MK_ENUM_CONST(26) +#define DC_WIN_A_COLOR_DEPTH_0_A_COLOR_DEPTH_T_A4B4G4R4 _MK_ENUM_CONST(27) +#define DC_WIN_A_COLOR_DEPTH_0_A_COLOR_DEPTH_R4G4B4A4 _MK_ENUM_CONST(27) +#define DC_WIN_A_COLOR_DEPTH_0_A_COLOR_DEPTH_T_A1B5G5R5 _MK_ENUM_CONST(28) +#define DC_WIN_A_COLOR_DEPTH_0_A_COLOR_DEPTH_R5G5B5A _MK_ENUM_CONST(28) +#define DC_WIN_A_COLOR_DEPTH_0_A_COLOR_DEPTH_T_B5G5R5A1 _MK_ENUM_CONST(29) +#define DC_WIN_A_COLOR_DEPTH_0_A_COLOR_DEPTH_AR5G5B5 _MK_ENUM_CONST(29) +#define DC_WIN_A_COLOR_DEPTH_0_A_COLOR_DEPTH_T_X1R5G5B5 _MK_ENUM_CONST(30) +#define DC_WIN_A_COLOR_DEPTH_0_A_COLOR_DEPTH_B5G5R5X1 _MK_ENUM_CONST(30) +#define DC_WIN_A_COLOR_DEPTH_0_A_COLOR_DEPTH_T_R5G5B5X1 _MK_ENUM_CONST(31) +#define DC_WIN_A_COLOR_DEPTH_0_A_COLOR_DEPTH_X1B5G5R5 _MK_ENUM_CONST(31) +#define DC_WIN_A_COLOR_DEPTH_0_A_COLOR_DEPTH_T_X1B5G5R5 _MK_ENUM_CONST(32) +#define DC_WIN_A_COLOR_DEPTH_0_A_COLOR_DEPTH_R5G5B5X1 _MK_ENUM_CONST(32) +#define DC_WIN_A_COLOR_DEPTH_0_A_COLOR_DEPTH_T_B5G5R5X1 _MK_ENUM_CONST(33) +#define DC_WIN_A_COLOR_DEPTH_0_A_COLOR_DEPTH_X1R5G5B5 _MK_ENUM_CONST(33) +#define DC_WIN_A_COLOR_DEPTH_0_A_COLOR_DEPTH_T_B5G6R5 _MK_ENUM_CONST(34) +#define DC_WIN_A_COLOR_DEPTH_0_A_COLOR_DEPTH_R5G6B5 _MK_ENUM_CONST(34) +#define DC_WIN_A_COLOR_DEPTH_0_A_COLOR_DEPTH_T_B8G8R8A8 _MK_ENUM_CONST(35) +#define DC_WIN_A_COLOR_DEPTH_0_A_COLOR_DEPTH_T_R8G8B8A8 _MK_ENUM_CONST(36) +#define DC_WIN_A_COLOR_DEPTH_0_A_COLOR_DEPTH_T_X8R8G8B8 _MK_ENUM_CONST(37) +#define DC_WIN_A_COLOR_DEPTH_0_A_COLOR_DEPTH_B8G8R8X8 _MK_ENUM_CONST(37) +#define DC_WIN_A_COLOR_DEPTH_0_A_COLOR_DEPTH_T_X8B8G8R8 _MK_ENUM_CONST(38) +#define DC_WIN_A_COLOR_DEPTH_0_A_COLOR_DEPTH_R8G8B8X8 _MK_ENUM_CONST(38) +#define DC_WIN_A_COLOR_DEPTH_0_A_COLOR_DEPTH_T_A8Y8U8V8 _MK_ENUM_CONST(39) +#define DC_WIN_A_COLOR_DEPTH_0_A_COLOR_DEPTH_T_V8U8Y8A8 _MK_ENUM_CONST(40) +#define DC_WIN_A_COLOR_DEPTH_0_A_COLOR_DEPTH_T_Y8___U8___V8_N444 _MK_ENUM_CONST(41) +#define DC_WIN_A_COLOR_DEPTH_0_A_COLOR_DEPTH_YCbCr444P _MK_ENUM_CONST(41) +#define DC_WIN_A_COLOR_DEPTH_0_A_COLOR_DEPTH_T_Y8___U8V8_N420 _MK_ENUM_CONST(42) +#define DC_WIN_A_COLOR_DEPTH_0_A_COLOR_DEPTH_YCrCb420SP _MK_ENUM_CONST(42) +#define DC_WIN_A_COLOR_DEPTH_0_A_COLOR_DEPTH_T_Y8___V8U8_N420 _MK_ENUM_CONST(43) +#define DC_WIN_A_COLOR_DEPTH_0_A_COLOR_DEPTH_YCbCr420SP _MK_ENUM_CONST(43) +#define DC_WIN_A_COLOR_DEPTH_0_A_COLOR_DEPTH_T_Y8___U8V8_N422 _MK_ENUM_CONST(44) +#define DC_WIN_A_COLOR_DEPTH_0_A_COLOR_DEPTH_YCrCb422SP _MK_ENUM_CONST(44) +#define DC_WIN_A_COLOR_DEPTH_0_A_COLOR_DEPTH_T_Y8___V8U8_N422 _MK_ENUM_CONST(45) +#define DC_WIN_A_COLOR_DEPTH_0_A_COLOR_DEPTH_YCbCr422SP _MK_ENUM_CONST(45) +#define DC_WIN_A_COLOR_DEPTH_0_A_COLOR_DEPTH_T_Y8___U8V8_N422R _MK_ENUM_CONST(46) +#define DC_WIN_A_COLOR_DEPTH_0_A_COLOR_DEPTH_YCrCb422RSP _MK_ENUM_CONST(46) +#define DC_WIN_A_COLOR_DEPTH_0_A_COLOR_DEPTH_T_Y8___V8U8_N422R _MK_ENUM_CONST(47) +#define DC_WIN_A_COLOR_DEPTH_0_A_COLOR_DEPTH_YCbCr422RSP _MK_ENUM_CONST(47) +#define DC_WIN_A_COLOR_DEPTH_0_A_COLOR_DEPTH_T_Y8___U8V8_N444 _MK_ENUM_CONST(48) +#define DC_WIN_A_COLOR_DEPTH_0_A_COLOR_DEPTH_YCrCb444SP _MK_ENUM_CONST(48) +#define DC_WIN_A_COLOR_DEPTH_0_A_COLOR_DEPTH_T_Y8___V8U8_N444 _MK_ENUM_CONST(49) +#define DC_WIN_A_COLOR_DEPTH_0_A_COLOR_DEPTH_YCbCr444SP _MK_ENUM_CONST(49) +#define DC_WIN_A_COLOR_DEPTH_0_A_COLOR_DEPTH_T_A8Y8U8V8_TRUE _MK_ENUM_CONST(50) +#define DC_WIN_A_COLOR_DEPTH_0_A_COLOR_DEPTH_T_V8U8Y8A8_TRUE _MK_ENUM_CONST(51) +#define DC_WIN_A_COLOR_DEPTH_0_A_COLOR_DEPTH_T_Y8___U8___V8_N444_TRUE _MK_ENUM_CONST(52) +#define DC_WIN_A_COLOR_DEPTH_0_A_COLOR_DEPTH_YUV444P _MK_ENUM_CONST(52) +#define DC_WIN_A_COLOR_DEPTH_0_A_COLOR_DEPTH_T_Y8___U8V8_N420_TRUE _MK_ENUM_CONST(53) +#define DC_WIN_A_COLOR_DEPTH_0_A_COLOR_DEPTH_YVU420SP _MK_ENUM_CONST(53) +#define DC_WIN_A_COLOR_DEPTH_0_A_COLOR_DEPTH_T_Y8___V8U8_N420_TRUE _MK_ENUM_CONST(54) +#define DC_WIN_A_COLOR_DEPTH_0_A_COLOR_DEPTH_YUV420SP _MK_ENUM_CONST(54) +#define DC_WIN_A_COLOR_DEPTH_0_A_COLOR_DEPTH_T_Y8___U8V8_N422_TRUE _MK_ENUM_CONST(55) +#define DC_WIN_A_COLOR_DEPTH_0_A_COLOR_DEPTH_YVU422SP _MK_ENUM_CONST(55) +#define DC_WIN_A_COLOR_DEPTH_0_A_COLOR_DEPTH_T_Y8___V8U8_N422_TRUE _MK_ENUM_CONST(56) +#define DC_WIN_A_COLOR_DEPTH_0_A_COLOR_DEPTH_YUV422SP _MK_ENUM_CONST(56) +#define DC_WIN_A_COLOR_DEPTH_0_A_COLOR_DEPTH_T_Y8___U8V8_N422R_TRUE _MK_ENUM_CONST(57) +#define DC_WIN_A_COLOR_DEPTH_0_A_COLOR_DEPTH_YVU422RSP _MK_ENUM_CONST(57) +#define DC_WIN_A_COLOR_DEPTH_0_A_COLOR_DEPTH_T_Y8___V8U8_N422R_TRUE _MK_ENUM_CONST(58) +#define DC_WIN_A_COLOR_DEPTH_0_A_COLOR_DEPTH_YUV422RSP _MK_ENUM_CONST(58) +#define DC_WIN_A_COLOR_DEPTH_0_A_COLOR_DEPTH_T_Y8___U8V8_N444_TRUE _MK_ENUM_CONST(59) +#define DC_WIN_A_COLOR_DEPTH_0_A_COLOR_DEPTH_YVU444SP _MK_ENUM_CONST(59) +#define DC_WIN_A_COLOR_DEPTH_0_A_COLOR_DEPTH_T_Y8___V8U8_N444_TRUE _MK_ENUM_CONST(60) +#define DC_WIN_A_COLOR_DEPTH_0_A_COLOR_DEPTH_YUV444SP _MK_ENUM_CONST(60) + + +// Register DC_WIN_A_POSITION_0 +#define DC_WIN_A_POSITION_0 _MK_ADDR_CONST(0x704) +#define DC_WIN_A_POSITION_0_SECURE 0x0 +#define DC_WIN_A_POSITION_0_WORD_COUNT 0x1 +#define DC_WIN_A_POSITION_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WIN_A_POSITION_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WIN_A_POSITION_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WIN_A_POSITION_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WIN_A_POSITION_0_READ_MASK _MK_MASK_CONST(0x1fff1fff) +#define DC_WIN_A_POSITION_0_WRITE_MASK _MK_MASK_CONST(0x1fff1fff) +#define DC_WIN_A_POSITION_0_A_H_POSITION_SHIFT _MK_SHIFT_CONST(0) +#define DC_WIN_A_POSITION_0_A_H_POSITION_FIELD _MK_FIELD_CONST(0x1fff, DC_WIN_A_POSITION_0_A_H_POSITION_SHIFT) +#define DC_WIN_A_POSITION_0_A_H_POSITION_RANGE 12:0 +#define DC_WIN_A_POSITION_0_A_H_POSITION_WOFFSET 0x0 +#define DC_WIN_A_POSITION_0_A_H_POSITION_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WIN_A_POSITION_0_A_H_POSITION_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WIN_A_POSITION_0_A_H_POSITION_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WIN_A_POSITION_0_A_H_POSITION_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WIN_A_POSITION_0_A_V_POSITION_SHIFT _MK_SHIFT_CONST(16) +#define DC_WIN_A_POSITION_0_A_V_POSITION_FIELD _MK_FIELD_CONST(0x1fff, DC_WIN_A_POSITION_0_A_V_POSITION_SHIFT) +#define DC_WIN_A_POSITION_0_A_V_POSITION_RANGE 28:16 +#define DC_WIN_A_POSITION_0_A_V_POSITION_WOFFSET 0x0 +#define DC_WIN_A_POSITION_0_A_V_POSITION_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WIN_A_POSITION_0_A_V_POSITION_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WIN_A_POSITION_0_A_V_POSITION_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WIN_A_POSITION_0_A_V_POSITION_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_WIN_A_SIZE_0 +#define DC_WIN_A_SIZE_0 _MK_ADDR_CONST(0x705) +#define DC_WIN_A_SIZE_0_SECURE 0x0 +#define DC_WIN_A_SIZE_0_WORD_COUNT 0x1 +#define DC_WIN_A_SIZE_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WIN_A_SIZE_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WIN_A_SIZE_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WIN_A_SIZE_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WIN_A_SIZE_0_READ_MASK _MK_MASK_CONST(0x1fff1fff) +#define DC_WIN_A_SIZE_0_WRITE_MASK _MK_MASK_CONST(0x1fff1fff) +#define DC_WIN_A_SIZE_0_A_H_SIZE_SHIFT _MK_SHIFT_CONST(0) +#define DC_WIN_A_SIZE_0_A_H_SIZE_FIELD _MK_FIELD_CONST(0x1fff, DC_WIN_A_SIZE_0_A_H_SIZE_SHIFT) +#define DC_WIN_A_SIZE_0_A_H_SIZE_RANGE 12:0 +#define DC_WIN_A_SIZE_0_A_H_SIZE_WOFFSET 0x0 +#define DC_WIN_A_SIZE_0_A_H_SIZE_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WIN_A_SIZE_0_A_H_SIZE_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WIN_A_SIZE_0_A_H_SIZE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WIN_A_SIZE_0_A_H_SIZE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WIN_A_SIZE_0_A_V_SIZE_SHIFT _MK_SHIFT_CONST(16) +#define DC_WIN_A_SIZE_0_A_V_SIZE_FIELD _MK_FIELD_CONST(0x1fff, DC_WIN_A_SIZE_0_A_V_SIZE_SHIFT) +#define DC_WIN_A_SIZE_0_A_V_SIZE_RANGE 28:16 +#define DC_WIN_A_SIZE_0_A_V_SIZE_WOFFSET 0x0 +#define DC_WIN_A_SIZE_0_A_V_SIZE_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WIN_A_SIZE_0_A_V_SIZE_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WIN_A_SIZE_0_A_V_SIZE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WIN_A_SIZE_0_A_V_SIZE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_WIN_A_PRESCALED_SIZE_0 +#define DC_WIN_A_PRESCALED_SIZE_0 _MK_ADDR_CONST(0x706) +#define DC_WIN_A_PRESCALED_SIZE_0_SECURE 0x0 +#define DC_WIN_A_PRESCALED_SIZE_0_WORD_COUNT 0x1 +#define DC_WIN_A_PRESCALED_SIZE_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WIN_A_PRESCALED_SIZE_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WIN_A_PRESCALED_SIZE_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WIN_A_PRESCALED_SIZE_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WIN_A_PRESCALED_SIZE_0_READ_MASK _MK_MASK_CONST(0x1fff7fff) +#define DC_WIN_A_PRESCALED_SIZE_0_WRITE_MASK _MK_MASK_CONST(0x1fff7fff) +#define DC_WIN_A_PRESCALED_SIZE_0_A_H_PRESCALED_SIZE_SHIFT _MK_SHIFT_CONST(0) +#define DC_WIN_A_PRESCALED_SIZE_0_A_H_PRESCALED_SIZE_FIELD _MK_FIELD_CONST(0x7fff, DC_WIN_A_PRESCALED_SIZE_0_A_H_PRESCALED_SIZE_SHIFT) +#define DC_WIN_A_PRESCALED_SIZE_0_A_H_PRESCALED_SIZE_RANGE 14:0 +#define DC_WIN_A_PRESCALED_SIZE_0_A_H_PRESCALED_SIZE_WOFFSET 0x0 +#define DC_WIN_A_PRESCALED_SIZE_0_A_H_PRESCALED_SIZE_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WIN_A_PRESCALED_SIZE_0_A_H_PRESCALED_SIZE_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WIN_A_PRESCALED_SIZE_0_A_H_PRESCALED_SIZE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WIN_A_PRESCALED_SIZE_0_A_H_PRESCALED_SIZE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WIN_A_PRESCALED_SIZE_0_A_V_PRESCALED_SIZE_SHIFT _MK_SHIFT_CONST(16) +#define DC_WIN_A_PRESCALED_SIZE_0_A_V_PRESCALED_SIZE_FIELD _MK_FIELD_CONST(0x1fff, DC_WIN_A_PRESCALED_SIZE_0_A_V_PRESCALED_SIZE_SHIFT) +#define DC_WIN_A_PRESCALED_SIZE_0_A_V_PRESCALED_SIZE_RANGE 28:16 +#define DC_WIN_A_PRESCALED_SIZE_0_A_V_PRESCALED_SIZE_WOFFSET 0x0 +#define DC_WIN_A_PRESCALED_SIZE_0_A_V_PRESCALED_SIZE_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WIN_A_PRESCALED_SIZE_0_A_V_PRESCALED_SIZE_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WIN_A_PRESCALED_SIZE_0_A_V_PRESCALED_SIZE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WIN_A_PRESCALED_SIZE_0_A_V_PRESCALED_SIZE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_WIN_A_H_INITIAL_DDA_0 +#define DC_WIN_A_H_INITIAL_DDA_0 _MK_ADDR_CONST(0x707) +#define DC_WIN_A_H_INITIAL_DDA_0_SECURE 0x0 +#define DC_WIN_A_H_INITIAL_DDA_0_WORD_COUNT 0x1 +#define DC_WIN_A_H_INITIAL_DDA_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WIN_A_H_INITIAL_DDA_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WIN_A_H_INITIAL_DDA_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WIN_A_H_INITIAL_DDA_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WIN_A_H_INITIAL_DDA_0_READ_MASK _MK_MASK_CONST(0xffff) +#define DC_WIN_A_H_INITIAL_DDA_0_WRITE_MASK _MK_MASK_CONST(0xffff) +#define DC_WIN_A_H_INITIAL_DDA_0_A_H_INITIAL_DDA_SHIFT _MK_SHIFT_CONST(0) +#define DC_WIN_A_H_INITIAL_DDA_0_A_H_INITIAL_DDA_FIELD _MK_FIELD_CONST(0xffff, DC_WIN_A_H_INITIAL_DDA_0_A_H_INITIAL_DDA_SHIFT) +#define DC_WIN_A_H_INITIAL_DDA_0_A_H_INITIAL_DDA_RANGE 15:0 +#define DC_WIN_A_H_INITIAL_DDA_0_A_H_INITIAL_DDA_WOFFSET 0x0 +#define DC_WIN_A_H_INITIAL_DDA_0_A_H_INITIAL_DDA_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WIN_A_H_INITIAL_DDA_0_A_H_INITIAL_DDA_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WIN_A_H_INITIAL_DDA_0_A_H_INITIAL_DDA_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WIN_A_H_INITIAL_DDA_0_A_H_INITIAL_DDA_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_WIN_A_V_INITIAL_DDA_0 +#define DC_WIN_A_V_INITIAL_DDA_0 _MK_ADDR_CONST(0x708) +#define DC_WIN_A_V_INITIAL_DDA_0_SECURE 0x0 +#define DC_WIN_A_V_INITIAL_DDA_0_WORD_COUNT 0x1 +#define DC_WIN_A_V_INITIAL_DDA_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WIN_A_V_INITIAL_DDA_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WIN_A_V_INITIAL_DDA_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WIN_A_V_INITIAL_DDA_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WIN_A_V_INITIAL_DDA_0_READ_MASK _MK_MASK_CONST(0xffff) +#define DC_WIN_A_V_INITIAL_DDA_0_WRITE_MASK _MK_MASK_CONST(0xffff) +#define DC_WIN_A_V_INITIAL_DDA_0_A_V_INITIAL_DDA_SHIFT _MK_SHIFT_CONST(0) +#define DC_WIN_A_V_INITIAL_DDA_0_A_V_INITIAL_DDA_FIELD _MK_FIELD_CONST(0xffff, DC_WIN_A_V_INITIAL_DDA_0_A_V_INITIAL_DDA_SHIFT) +#define DC_WIN_A_V_INITIAL_DDA_0_A_V_INITIAL_DDA_RANGE 15:0 +#define DC_WIN_A_V_INITIAL_DDA_0_A_V_INITIAL_DDA_WOFFSET 0x0 +#define DC_WIN_A_V_INITIAL_DDA_0_A_V_INITIAL_DDA_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WIN_A_V_INITIAL_DDA_0_A_V_INITIAL_DDA_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WIN_A_V_INITIAL_DDA_0_A_V_INITIAL_DDA_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WIN_A_V_INITIAL_DDA_0_A_V_INITIAL_DDA_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_WIN_A_DDA_INCREMENT_0 +#define DC_WIN_A_DDA_INCREMENT_0 _MK_ADDR_CONST(0x709) +#define DC_WIN_A_DDA_INCREMENT_0_SECURE 0x0 +#define DC_WIN_A_DDA_INCREMENT_0_WORD_COUNT 0x1 +#define DC_WIN_A_DDA_INCREMENT_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WIN_A_DDA_INCREMENT_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WIN_A_DDA_INCREMENT_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WIN_A_DDA_INCREMENT_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WIN_A_DDA_INCREMENT_0_READ_MASK _MK_MASK_CONST(0xffffffff) +#define DC_WIN_A_DDA_INCREMENT_0_WRITE_MASK _MK_MASK_CONST(0xffffffff) +#define DC_WIN_A_DDA_INCREMENT_0_A_H_DDA_INCREMENT_SHIFT _MK_SHIFT_CONST(0) +#define DC_WIN_A_DDA_INCREMENT_0_A_H_DDA_INCREMENT_FIELD _MK_FIELD_CONST(0xffff, DC_WIN_A_DDA_INCREMENT_0_A_H_DDA_INCREMENT_SHIFT) +#define DC_WIN_A_DDA_INCREMENT_0_A_H_DDA_INCREMENT_RANGE 15:0 +#define DC_WIN_A_DDA_INCREMENT_0_A_H_DDA_INCREMENT_WOFFSET 0x0 +#define DC_WIN_A_DDA_INCREMENT_0_A_H_DDA_INCREMENT_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WIN_A_DDA_INCREMENT_0_A_H_DDA_INCREMENT_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WIN_A_DDA_INCREMENT_0_A_H_DDA_INCREMENT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WIN_A_DDA_INCREMENT_0_A_H_DDA_INCREMENT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WIN_A_DDA_INCREMENT_0_A_V_DDA_INCREMENT_SHIFT _MK_SHIFT_CONST(16) +#define DC_WIN_A_DDA_INCREMENT_0_A_V_DDA_INCREMENT_FIELD _MK_FIELD_CONST(0xffff, DC_WIN_A_DDA_INCREMENT_0_A_V_DDA_INCREMENT_SHIFT) +#define DC_WIN_A_DDA_INCREMENT_0_A_V_DDA_INCREMENT_RANGE 31:16 +#define DC_WIN_A_DDA_INCREMENT_0_A_V_DDA_INCREMENT_WOFFSET 0x0 +#define DC_WIN_A_DDA_INCREMENT_0_A_V_DDA_INCREMENT_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WIN_A_DDA_INCREMENT_0_A_V_DDA_INCREMENT_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WIN_A_DDA_INCREMENT_0_A_V_DDA_INCREMENT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WIN_A_DDA_INCREMENT_0_A_V_DDA_INCREMENT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_WIN_A_LINE_STRIDE_0 +#define DC_WIN_A_LINE_STRIDE_0 _MK_ADDR_CONST(0x70a) +#define DC_WIN_A_LINE_STRIDE_0_SECURE 0x0 +#define DC_WIN_A_LINE_STRIDE_0_WORD_COUNT 0x1 +#define DC_WIN_A_LINE_STRIDE_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WIN_A_LINE_STRIDE_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WIN_A_LINE_STRIDE_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WIN_A_LINE_STRIDE_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WIN_A_LINE_STRIDE_0_READ_MASK _MK_MASK_CONST(0xffffffff) +#define DC_WIN_A_LINE_STRIDE_0_WRITE_MASK _MK_MASK_CONST(0xffffffff) +#define DC_WIN_A_LINE_STRIDE_0_A_LINE_STRIDE_SHIFT _MK_SHIFT_CONST(0) +#define DC_WIN_A_LINE_STRIDE_0_A_LINE_STRIDE_FIELD _MK_FIELD_CONST(0xffff, DC_WIN_A_LINE_STRIDE_0_A_LINE_STRIDE_SHIFT) +#define DC_WIN_A_LINE_STRIDE_0_A_LINE_STRIDE_RANGE 15:0 +#define DC_WIN_A_LINE_STRIDE_0_A_LINE_STRIDE_WOFFSET 0x0 +#define DC_WIN_A_LINE_STRIDE_0_A_LINE_STRIDE_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WIN_A_LINE_STRIDE_0_A_LINE_STRIDE_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WIN_A_LINE_STRIDE_0_A_LINE_STRIDE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WIN_A_LINE_STRIDE_0_A_LINE_STRIDE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WIN_A_LINE_STRIDE_0_A_UV_LINE_STRIDE_SHIFT _MK_SHIFT_CONST(16) +#define DC_WIN_A_LINE_STRIDE_0_A_UV_LINE_STRIDE_FIELD _MK_FIELD_CONST(0xffff, DC_WIN_A_LINE_STRIDE_0_A_UV_LINE_STRIDE_SHIFT) +#define DC_WIN_A_LINE_STRIDE_0_A_UV_LINE_STRIDE_RANGE 31:16 +#define DC_WIN_A_LINE_STRIDE_0_A_UV_LINE_STRIDE_WOFFSET 0x0 +#define DC_WIN_A_LINE_STRIDE_0_A_UV_LINE_STRIDE_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WIN_A_LINE_STRIDE_0_A_UV_LINE_STRIDE_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WIN_A_LINE_STRIDE_0_A_UV_LINE_STRIDE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WIN_A_LINE_STRIDE_0_A_UV_LINE_STRIDE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Reserved address 1803 [0x70b] + +// Reserved address 1804 [0x70c] + +// Reserved address 1805 [0x70d] + +// Register DC_WIN_A_DV_CONTROL_0 +#define DC_WIN_A_DV_CONTROL_0 _MK_ADDR_CONST(0x70e) +#define DC_WIN_A_DV_CONTROL_0_SECURE 0x0 +#define DC_WIN_A_DV_CONTROL_0_WORD_COUNT 0x1 +#define DC_WIN_A_DV_CONTROL_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WIN_A_DV_CONTROL_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WIN_A_DV_CONTROL_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WIN_A_DV_CONTROL_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WIN_A_DV_CONTROL_0_READ_MASK _MK_MASK_CONST(0x70707) +#define DC_WIN_A_DV_CONTROL_0_WRITE_MASK _MK_MASK_CONST(0x70707) +#define DC_WIN_A_DV_CONTROL_0_A_DV_CONTROL_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_WIN_A_DV_CONTROL_0_A_DV_CONTROL_R_FIELD _MK_FIELD_CONST(0x7, DC_WIN_A_DV_CONTROL_0_A_DV_CONTROL_R_SHIFT) +#define DC_WIN_A_DV_CONTROL_0_A_DV_CONTROL_R_RANGE 2:0 +#define DC_WIN_A_DV_CONTROL_0_A_DV_CONTROL_R_WOFFSET 0x0 +#define DC_WIN_A_DV_CONTROL_0_A_DV_CONTROL_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WIN_A_DV_CONTROL_0_A_DV_CONTROL_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WIN_A_DV_CONTROL_0_A_DV_CONTROL_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WIN_A_DV_CONTROL_0_A_DV_CONTROL_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WIN_A_DV_CONTROL_0_A_DV_CONTROL_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_WIN_A_DV_CONTROL_0_A_DV_CONTROL_G_FIELD _MK_FIELD_CONST(0x7, DC_WIN_A_DV_CONTROL_0_A_DV_CONTROL_G_SHIFT) +#define DC_WIN_A_DV_CONTROL_0_A_DV_CONTROL_G_RANGE 10:8 +#define DC_WIN_A_DV_CONTROL_0_A_DV_CONTROL_G_WOFFSET 0x0 +#define DC_WIN_A_DV_CONTROL_0_A_DV_CONTROL_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WIN_A_DV_CONTROL_0_A_DV_CONTROL_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WIN_A_DV_CONTROL_0_A_DV_CONTROL_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WIN_A_DV_CONTROL_0_A_DV_CONTROL_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WIN_A_DV_CONTROL_0_A_DV_CONTROL_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_WIN_A_DV_CONTROL_0_A_DV_CONTROL_B_FIELD _MK_FIELD_CONST(0x7, DC_WIN_A_DV_CONTROL_0_A_DV_CONTROL_B_SHIFT) +#define DC_WIN_A_DV_CONTROL_0_A_DV_CONTROL_B_RANGE 18:16 +#define DC_WIN_A_DV_CONTROL_0_A_DV_CONTROL_B_WOFFSET 0x0 +#define DC_WIN_A_DV_CONTROL_0_A_DV_CONTROL_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WIN_A_DV_CONTROL_0_A_DV_CONTROL_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WIN_A_DV_CONTROL_0_A_DV_CONTROL_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WIN_A_DV_CONTROL_0_A_DV_CONTROL_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Reserved address 1807 [0x70f] + +// Reserved address 1808 [0x710] + +// Reserved address 1809 [0x711] + +// Reserved address 1810 [0x712] + +// Reserved address 1811 [0x713] + +// Reserved address 1812 [0x714] + +// Reserved address 1813 [0x715] + +// Register DC_WIN_A_BLEND_LAYER_CONTROL_0 +#define DC_WIN_A_BLEND_LAYER_CONTROL_0 _MK_ADDR_CONST(0x716) +#define DC_WIN_A_BLEND_LAYER_CONTROL_0_SECURE 0x0 +#define DC_WIN_A_BLEND_LAYER_CONTROL_0_WORD_COUNT 0x1 +#define DC_WIN_A_BLEND_LAYER_CONTROL_0_RESET_VAL _MK_MASK_CONST(0x1000000) +#define DC_WIN_A_BLEND_LAYER_CONTROL_0_RESET_MASK _MK_MASK_CONST(0xfffffff) +#define DC_WIN_A_BLEND_LAYER_CONTROL_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WIN_A_BLEND_LAYER_CONTROL_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WIN_A_BLEND_LAYER_CONTROL_0_READ_MASK _MK_MASK_CONST(0xfffffff) +#define DC_WIN_A_BLEND_LAYER_CONTROL_0_WRITE_MASK _MK_MASK_CONST(0xfffffff) +#define DC_WIN_A_BLEND_LAYER_CONTROL_0_A_WINDOW_LAYER_DEPTH_SHIFT _MK_SHIFT_CONST(0) +#define DC_WIN_A_BLEND_LAYER_CONTROL_0_A_WINDOW_LAYER_DEPTH_FIELD _MK_FIELD_CONST(0xff, DC_WIN_A_BLEND_LAYER_CONTROL_0_A_WINDOW_LAYER_DEPTH_SHIFT) +#define DC_WIN_A_BLEND_LAYER_CONTROL_0_A_WINDOW_LAYER_DEPTH_RANGE 7:0 +#define DC_WIN_A_BLEND_LAYER_CONTROL_0_A_WINDOW_LAYER_DEPTH_WOFFSET 0x0 +#define DC_WIN_A_BLEND_LAYER_CONTROL_0_A_WINDOW_LAYER_DEPTH_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WIN_A_BLEND_LAYER_CONTROL_0_A_WINDOW_LAYER_DEPTH_DEFAULT_MASK _MK_MASK_CONST(0xff) +#define DC_WIN_A_BLEND_LAYER_CONTROL_0_A_WINDOW_LAYER_DEPTH_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WIN_A_BLEND_LAYER_CONTROL_0_A_WINDOW_LAYER_DEPTH_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WIN_A_BLEND_LAYER_CONTROL_0_A_K1_SHIFT _MK_SHIFT_CONST(8) +#define DC_WIN_A_BLEND_LAYER_CONTROL_0_A_K1_FIELD _MK_FIELD_CONST(0xff, DC_WIN_A_BLEND_LAYER_CONTROL_0_A_K1_SHIFT) +#define DC_WIN_A_BLEND_LAYER_CONTROL_0_A_K1_RANGE 15:8 +#define DC_WIN_A_BLEND_LAYER_CONTROL_0_A_K1_WOFFSET 0x0 +#define DC_WIN_A_BLEND_LAYER_CONTROL_0_A_K1_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WIN_A_BLEND_LAYER_CONTROL_0_A_K1_DEFAULT_MASK _MK_MASK_CONST(0xff) +#define DC_WIN_A_BLEND_LAYER_CONTROL_0_A_K1_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WIN_A_BLEND_LAYER_CONTROL_0_A_K1_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WIN_A_BLEND_LAYER_CONTROL_0_A_K2_SHIFT _MK_SHIFT_CONST(16) +#define DC_WIN_A_BLEND_LAYER_CONTROL_0_A_K2_FIELD _MK_FIELD_CONST(0xff, DC_WIN_A_BLEND_LAYER_CONTROL_0_A_K2_SHIFT) +#define DC_WIN_A_BLEND_LAYER_CONTROL_0_A_K2_RANGE 23:16 +#define DC_WIN_A_BLEND_LAYER_CONTROL_0_A_K2_WOFFSET 0x0 +#define DC_WIN_A_BLEND_LAYER_CONTROL_0_A_K2_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WIN_A_BLEND_LAYER_CONTROL_0_A_K2_DEFAULT_MASK _MK_MASK_CONST(0xff) +#define DC_WIN_A_BLEND_LAYER_CONTROL_0_A_K2_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WIN_A_BLEND_LAYER_CONTROL_0_A_K2_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WIN_A_BLEND_LAYER_CONTROL_0_A_BLEND_BYPASS_SHIFT _MK_SHIFT_CONST(24) +#define DC_WIN_A_BLEND_LAYER_CONTROL_0_A_BLEND_BYPASS_FIELD _MK_FIELD_CONST(0x1, DC_WIN_A_BLEND_LAYER_CONTROL_0_A_BLEND_BYPASS_SHIFT) +#define DC_WIN_A_BLEND_LAYER_CONTROL_0_A_BLEND_BYPASS_RANGE 24:24 +#define DC_WIN_A_BLEND_LAYER_CONTROL_0_A_BLEND_BYPASS_WOFFSET 0x0 +#define DC_WIN_A_BLEND_LAYER_CONTROL_0_A_BLEND_BYPASS_DEFAULT _MK_MASK_CONST(0x1) +#define DC_WIN_A_BLEND_LAYER_CONTROL_0_A_BLEND_BYPASS_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_WIN_A_BLEND_LAYER_CONTROL_0_A_BLEND_BYPASS_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WIN_A_BLEND_LAYER_CONTROL_0_A_BLEND_BYPASS_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WIN_A_BLEND_LAYER_CONTROL_0_A_BLEND_BYPASS_INIT_ENUM BLEND_BYPASS +#define DC_WIN_A_BLEND_LAYER_CONTROL_0_A_BLEND_BYPASS_BLEND_ENABLE _MK_ENUM_CONST(0) +#define DC_WIN_A_BLEND_LAYER_CONTROL_0_A_BLEND_BYPASS_BLEND_BYPASS _MK_ENUM_CONST(1) + +#define DC_WIN_A_BLEND_LAYER_CONTROL_0_A_COLOR_KEY_SELECT_SHIFT _MK_SHIFT_CONST(25) +#define DC_WIN_A_BLEND_LAYER_CONTROL_0_A_COLOR_KEY_SELECT_FIELD _MK_FIELD_CONST(0x7, DC_WIN_A_BLEND_LAYER_CONTROL_0_A_COLOR_KEY_SELECT_SHIFT) +#define DC_WIN_A_BLEND_LAYER_CONTROL_0_A_COLOR_KEY_SELECT_RANGE 27:25 +#define DC_WIN_A_BLEND_LAYER_CONTROL_0_A_COLOR_KEY_SELECT_WOFFSET 0x0 +#define DC_WIN_A_BLEND_LAYER_CONTROL_0_A_COLOR_KEY_SELECT_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WIN_A_BLEND_LAYER_CONTROL_0_A_COLOR_KEY_SELECT_DEFAULT_MASK _MK_MASK_CONST(0x7) +#define DC_WIN_A_BLEND_LAYER_CONTROL_0_A_COLOR_KEY_SELECT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WIN_A_BLEND_LAYER_CONTROL_0_A_COLOR_KEY_SELECT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WIN_A_BLEND_LAYER_CONTROL_0_A_COLOR_KEY_SELECT_NONE _MK_ENUM_CONST(0) +#define DC_WIN_A_BLEND_LAYER_CONTROL_0_A_COLOR_KEY_SELECT_WINDOWA_KEY0 _MK_ENUM_CONST(1) +#define DC_WIN_A_BLEND_LAYER_CONTROL_0_A_COLOR_KEY_SELECT_WINDOWA_KEY1 _MK_ENUM_CONST(2) +#define DC_WIN_A_BLEND_LAYER_CONTROL_0_A_COLOR_KEY_SELECT_WINDOWB_KEY0 _MK_ENUM_CONST(3) +#define DC_WIN_A_BLEND_LAYER_CONTROL_0_A_COLOR_KEY_SELECT_WINDOWB_KEY1 _MK_ENUM_CONST(4) +#define DC_WIN_A_BLEND_LAYER_CONTROL_0_A_COLOR_KEY_SELECT_WINDOWC_KEY0 _MK_ENUM_CONST(5) +#define DC_WIN_A_BLEND_LAYER_CONTROL_0_A_COLOR_KEY_SELECT_WINDOWC_KEY1 _MK_ENUM_CONST(6) + + +// Register DC_WIN_A_BLEND_MATCH_SELECT_0 +#define DC_WIN_A_BLEND_MATCH_SELECT_0 _MK_ADDR_CONST(0x717) +#define DC_WIN_A_BLEND_MATCH_SELECT_0_SECURE 0x0 +#define DC_WIN_A_BLEND_MATCH_SELECT_0_WORD_COUNT 0x1 +#define DC_WIN_A_BLEND_MATCH_SELECT_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WIN_A_BLEND_MATCH_SELECT_0_RESET_MASK _MK_MASK_CONST(0x3377) +#define DC_WIN_A_BLEND_MATCH_SELECT_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WIN_A_BLEND_MATCH_SELECT_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WIN_A_BLEND_MATCH_SELECT_0_READ_MASK _MK_MASK_CONST(0x3377) +#define DC_WIN_A_BLEND_MATCH_SELECT_0_WRITE_MASK _MK_MASK_CONST(0x3377) +#define DC_WIN_A_BLEND_MATCH_SELECT_0_A_BLEND_FACTOR_SRC_COLOR_MATCH_SELECT_SHIFT _MK_SHIFT_CONST(0) +#define DC_WIN_A_BLEND_MATCH_SELECT_0_A_BLEND_FACTOR_SRC_COLOR_MATCH_SELECT_FIELD _MK_FIELD_CONST(0x7, DC_WIN_A_BLEND_MATCH_SELECT_0_A_BLEND_FACTOR_SRC_COLOR_MATCH_SELECT_SHIFT) +#define DC_WIN_A_BLEND_MATCH_SELECT_0_A_BLEND_FACTOR_SRC_COLOR_MATCH_SELECT_RANGE 2:0 +#define DC_WIN_A_BLEND_MATCH_SELECT_0_A_BLEND_FACTOR_SRC_COLOR_MATCH_SELECT_WOFFSET 0x0 +#define DC_WIN_A_BLEND_MATCH_SELECT_0_A_BLEND_FACTOR_SRC_COLOR_MATCH_SELECT_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WIN_A_BLEND_MATCH_SELECT_0_A_BLEND_FACTOR_SRC_COLOR_MATCH_SELECT_DEFAULT_MASK _MK_MASK_CONST(0x7) +#define DC_WIN_A_BLEND_MATCH_SELECT_0_A_BLEND_FACTOR_SRC_COLOR_MATCH_SELECT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WIN_A_BLEND_MATCH_SELECT_0_A_BLEND_FACTOR_SRC_COLOR_MATCH_SELECT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WIN_A_BLEND_MATCH_SELECT_0_A_BLEND_FACTOR_SRC_COLOR_MATCH_SELECT_ZERO _MK_ENUM_CONST(0) +#define DC_WIN_A_BLEND_MATCH_SELECT_0_A_BLEND_FACTOR_SRC_COLOR_MATCH_SELECT_ONE _MK_ENUM_CONST(1) +#define DC_WIN_A_BLEND_MATCH_SELECT_0_A_BLEND_FACTOR_SRC_COLOR_MATCH_SELECT_K1 _MK_ENUM_CONST(2) +#define DC_WIN_A_BLEND_MATCH_SELECT_0_A_BLEND_FACTOR_SRC_COLOR_MATCH_SELECT_K1_TIMES_DST _MK_ENUM_CONST(3) +#define DC_WIN_A_BLEND_MATCH_SELECT_0_A_BLEND_FACTOR_SRC_COLOR_MATCH_SELECT_NEG_K1_TIMES_DST _MK_ENUM_CONST(4) +#define DC_WIN_A_BLEND_MATCH_SELECT_0_A_BLEND_FACTOR_SRC_COLOR_MATCH_SELECT_K1_TIMES_SRC _MK_ENUM_CONST(5) + +#define DC_WIN_A_BLEND_MATCH_SELECT_0_A_BLEND_FACTOR_DST_COLOR_MATCH_SELECT_SHIFT _MK_SHIFT_CONST(4) +#define DC_WIN_A_BLEND_MATCH_SELECT_0_A_BLEND_FACTOR_DST_COLOR_MATCH_SELECT_FIELD _MK_FIELD_CONST(0x7, DC_WIN_A_BLEND_MATCH_SELECT_0_A_BLEND_FACTOR_DST_COLOR_MATCH_SELECT_SHIFT) +#define DC_WIN_A_BLEND_MATCH_SELECT_0_A_BLEND_FACTOR_DST_COLOR_MATCH_SELECT_RANGE 6:4 +#define DC_WIN_A_BLEND_MATCH_SELECT_0_A_BLEND_FACTOR_DST_COLOR_MATCH_SELECT_WOFFSET 0x0 +#define DC_WIN_A_BLEND_MATCH_SELECT_0_A_BLEND_FACTOR_DST_COLOR_MATCH_SELECT_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WIN_A_BLEND_MATCH_SELECT_0_A_BLEND_FACTOR_DST_COLOR_MATCH_SELECT_DEFAULT_MASK _MK_MASK_CONST(0x7) +#define DC_WIN_A_BLEND_MATCH_SELECT_0_A_BLEND_FACTOR_DST_COLOR_MATCH_SELECT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WIN_A_BLEND_MATCH_SELECT_0_A_BLEND_FACTOR_DST_COLOR_MATCH_SELECT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WIN_A_BLEND_MATCH_SELECT_0_A_BLEND_FACTOR_DST_COLOR_MATCH_SELECT_ZERO _MK_ENUM_CONST(0) +#define DC_WIN_A_BLEND_MATCH_SELECT_0_A_BLEND_FACTOR_DST_COLOR_MATCH_SELECT_ONE _MK_ENUM_CONST(1) +#define DC_WIN_A_BLEND_MATCH_SELECT_0_A_BLEND_FACTOR_DST_COLOR_MATCH_SELECT_K1 _MK_ENUM_CONST(2) +#define DC_WIN_A_BLEND_MATCH_SELECT_0_A_BLEND_FACTOR_DST_COLOR_MATCH_SELECT_K2 _MK_ENUM_CONST(3) +#define DC_WIN_A_BLEND_MATCH_SELECT_0_A_BLEND_FACTOR_DST_COLOR_MATCH_SELECT_K1_TIMES_DST _MK_ENUM_CONST(4) +#define DC_WIN_A_BLEND_MATCH_SELECT_0_A_BLEND_FACTOR_DST_COLOR_MATCH_SELECT_NEG_K1_TIMES_DST _MK_ENUM_CONST(5) +#define DC_WIN_A_BLEND_MATCH_SELECT_0_A_BLEND_FACTOR_DST_COLOR_MATCH_SELECT_NEG_K1_TIMES_SRC _MK_ENUM_CONST(6) +#define DC_WIN_A_BLEND_MATCH_SELECT_0_A_BLEND_FACTOR_DST_COLOR_MATCH_SELECT_NEG_K1 _MK_ENUM_CONST(7) + +#define DC_WIN_A_BLEND_MATCH_SELECT_0_A_BLEND_FACTOR_SRC_ALPHA_MATCH_SELECT_SHIFT _MK_SHIFT_CONST(8) +#define DC_WIN_A_BLEND_MATCH_SELECT_0_A_BLEND_FACTOR_SRC_ALPHA_MATCH_SELECT_FIELD _MK_FIELD_CONST(0x3, DC_WIN_A_BLEND_MATCH_SELECT_0_A_BLEND_FACTOR_SRC_ALPHA_MATCH_SELECT_SHIFT) +#define DC_WIN_A_BLEND_MATCH_SELECT_0_A_BLEND_FACTOR_SRC_ALPHA_MATCH_SELECT_RANGE 9:8 +#define DC_WIN_A_BLEND_MATCH_SELECT_0_A_BLEND_FACTOR_SRC_ALPHA_MATCH_SELECT_WOFFSET 0x0 +#define DC_WIN_A_BLEND_MATCH_SELECT_0_A_BLEND_FACTOR_SRC_ALPHA_MATCH_SELECT_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WIN_A_BLEND_MATCH_SELECT_0_A_BLEND_FACTOR_SRC_ALPHA_MATCH_SELECT_DEFAULT_MASK _MK_MASK_CONST(0x3) +#define DC_WIN_A_BLEND_MATCH_SELECT_0_A_BLEND_FACTOR_SRC_ALPHA_MATCH_SELECT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WIN_A_BLEND_MATCH_SELECT_0_A_BLEND_FACTOR_SRC_ALPHA_MATCH_SELECT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WIN_A_BLEND_MATCH_SELECT_0_A_BLEND_FACTOR_SRC_ALPHA_MATCH_SELECT_ZERO _MK_ENUM_CONST(0) +#define DC_WIN_A_BLEND_MATCH_SELECT_0_A_BLEND_FACTOR_SRC_ALPHA_MATCH_SELECT_K1 _MK_ENUM_CONST(1) +#define DC_WIN_A_BLEND_MATCH_SELECT_0_A_BLEND_FACTOR_SRC_ALPHA_MATCH_SELECT_K2 _MK_ENUM_CONST(2) + +#define DC_WIN_A_BLEND_MATCH_SELECT_0_A_BLEND_FACTOR_DST_ALPHA_MATCH_SELECT_SHIFT _MK_SHIFT_CONST(12) +#define DC_WIN_A_BLEND_MATCH_SELECT_0_A_BLEND_FACTOR_DST_ALPHA_MATCH_SELECT_FIELD _MK_FIELD_CONST(0x3, DC_WIN_A_BLEND_MATCH_SELECT_0_A_BLEND_FACTOR_DST_ALPHA_MATCH_SELECT_SHIFT) +#define DC_WIN_A_BLEND_MATCH_SELECT_0_A_BLEND_FACTOR_DST_ALPHA_MATCH_SELECT_RANGE 13:12 +#define DC_WIN_A_BLEND_MATCH_SELECT_0_A_BLEND_FACTOR_DST_ALPHA_MATCH_SELECT_WOFFSET 0x0 +#define DC_WIN_A_BLEND_MATCH_SELECT_0_A_BLEND_FACTOR_DST_ALPHA_MATCH_SELECT_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WIN_A_BLEND_MATCH_SELECT_0_A_BLEND_FACTOR_DST_ALPHA_MATCH_SELECT_DEFAULT_MASK _MK_MASK_CONST(0x3) +#define DC_WIN_A_BLEND_MATCH_SELECT_0_A_BLEND_FACTOR_DST_ALPHA_MATCH_SELECT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WIN_A_BLEND_MATCH_SELECT_0_A_BLEND_FACTOR_DST_ALPHA_MATCH_SELECT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WIN_A_BLEND_MATCH_SELECT_0_A_BLEND_FACTOR_DST_ALPHA_MATCH_SELECT_ZERO _MK_ENUM_CONST(0) +#define DC_WIN_A_BLEND_MATCH_SELECT_0_A_BLEND_FACTOR_DST_ALPHA_MATCH_SELECT_ONE _MK_ENUM_CONST(1) +#define DC_WIN_A_BLEND_MATCH_SELECT_0_A_BLEND_FACTOR_DST_ALPHA_MATCH_SELECT_NEG_K1_TIMES_SRC _MK_ENUM_CONST(2) +#define DC_WIN_A_BLEND_MATCH_SELECT_0_A_BLEND_FACTOR_DST_ALPHA_MATCH_SELECT_K2 _MK_ENUM_CONST(3) + + +// Register DC_WIN_A_BLEND_NOMATCH_SELECT_0 +#define DC_WIN_A_BLEND_NOMATCH_SELECT_0 _MK_ADDR_CONST(0x718) +#define DC_WIN_A_BLEND_NOMATCH_SELECT_0_SECURE 0x0 +#define DC_WIN_A_BLEND_NOMATCH_SELECT_0_WORD_COUNT 0x1 +#define DC_WIN_A_BLEND_NOMATCH_SELECT_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WIN_A_BLEND_NOMATCH_SELECT_0_RESET_MASK _MK_MASK_CONST(0x3377) +#define DC_WIN_A_BLEND_NOMATCH_SELECT_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WIN_A_BLEND_NOMATCH_SELECT_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WIN_A_BLEND_NOMATCH_SELECT_0_READ_MASK _MK_MASK_CONST(0x3377) +#define DC_WIN_A_BLEND_NOMATCH_SELECT_0_WRITE_MASK _MK_MASK_CONST(0x3377) +#define DC_WIN_A_BLEND_NOMATCH_SELECT_0_A_BLEND_FACTOR_SRC_COLOR_NOMATCH_SELECT_SHIFT _MK_SHIFT_CONST(0) +#define DC_WIN_A_BLEND_NOMATCH_SELECT_0_A_BLEND_FACTOR_SRC_COLOR_NOMATCH_SELECT_FIELD _MK_FIELD_CONST(0x7, DC_WIN_A_BLEND_NOMATCH_SELECT_0_A_BLEND_FACTOR_SRC_COLOR_NOMATCH_SELECT_SHIFT) +#define DC_WIN_A_BLEND_NOMATCH_SELECT_0_A_BLEND_FACTOR_SRC_COLOR_NOMATCH_SELECT_RANGE 2:0 +#define DC_WIN_A_BLEND_NOMATCH_SELECT_0_A_BLEND_FACTOR_SRC_COLOR_NOMATCH_SELECT_WOFFSET 0x0 +#define DC_WIN_A_BLEND_NOMATCH_SELECT_0_A_BLEND_FACTOR_SRC_COLOR_NOMATCH_SELECT_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WIN_A_BLEND_NOMATCH_SELECT_0_A_BLEND_FACTOR_SRC_COLOR_NOMATCH_SELECT_DEFAULT_MASK _MK_MASK_CONST(0x7) +#define DC_WIN_A_BLEND_NOMATCH_SELECT_0_A_BLEND_FACTOR_SRC_COLOR_NOMATCH_SELECT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WIN_A_BLEND_NOMATCH_SELECT_0_A_BLEND_FACTOR_SRC_COLOR_NOMATCH_SELECT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WIN_A_BLEND_NOMATCH_SELECT_0_A_BLEND_FACTOR_SRC_COLOR_NOMATCH_SELECT_ZERO _MK_ENUM_CONST(0) +#define DC_WIN_A_BLEND_NOMATCH_SELECT_0_A_BLEND_FACTOR_SRC_COLOR_NOMATCH_SELECT_ONE _MK_ENUM_CONST(1) +#define DC_WIN_A_BLEND_NOMATCH_SELECT_0_A_BLEND_FACTOR_SRC_COLOR_NOMATCH_SELECT_K1 _MK_ENUM_CONST(2) +#define DC_WIN_A_BLEND_NOMATCH_SELECT_0_A_BLEND_FACTOR_SRC_COLOR_NOMATCH_SELECT_K1_TIMES_DST _MK_ENUM_CONST(3) +#define DC_WIN_A_BLEND_NOMATCH_SELECT_0_A_BLEND_FACTOR_SRC_COLOR_NOMATCH_SELECT_NEG_K1_TIMES_DST _MK_ENUM_CONST(4) +#define DC_WIN_A_BLEND_NOMATCH_SELECT_0_A_BLEND_FACTOR_SRC_COLOR_NOMATCH_SELECT_K1_TIMES_SRC _MK_ENUM_CONST(5) + +#define DC_WIN_A_BLEND_NOMATCH_SELECT_0_A_BLEND_FACTOR_DST_COLOR_NOMATCH_SELECT_SHIFT _MK_SHIFT_CONST(4) +#define DC_WIN_A_BLEND_NOMATCH_SELECT_0_A_BLEND_FACTOR_DST_COLOR_NOMATCH_SELECT_FIELD _MK_FIELD_CONST(0x7, DC_WIN_A_BLEND_NOMATCH_SELECT_0_A_BLEND_FACTOR_DST_COLOR_NOMATCH_SELECT_SHIFT) +#define DC_WIN_A_BLEND_NOMATCH_SELECT_0_A_BLEND_FACTOR_DST_COLOR_NOMATCH_SELECT_RANGE 6:4 +#define DC_WIN_A_BLEND_NOMATCH_SELECT_0_A_BLEND_FACTOR_DST_COLOR_NOMATCH_SELECT_WOFFSET 0x0 +#define DC_WIN_A_BLEND_NOMATCH_SELECT_0_A_BLEND_FACTOR_DST_COLOR_NOMATCH_SELECT_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WIN_A_BLEND_NOMATCH_SELECT_0_A_BLEND_FACTOR_DST_COLOR_NOMATCH_SELECT_DEFAULT_MASK _MK_MASK_CONST(0x7) +#define DC_WIN_A_BLEND_NOMATCH_SELECT_0_A_BLEND_FACTOR_DST_COLOR_NOMATCH_SELECT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WIN_A_BLEND_NOMATCH_SELECT_0_A_BLEND_FACTOR_DST_COLOR_NOMATCH_SELECT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WIN_A_BLEND_NOMATCH_SELECT_0_A_BLEND_FACTOR_DST_COLOR_NOMATCH_SELECT_ZERO _MK_ENUM_CONST(0) +#define DC_WIN_A_BLEND_NOMATCH_SELECT_0_A_BLEND_FACTOR_DST_COLOR_NOMATCH_SELECT_ONE _MK_ENUM_CONST(1) +#define DC_WIN_A_BLEND_NOMATCH_SELECT_0_A_BLEND_FACTOR_DST_COLOR_NOMATCH_SELECT_K1 _MK_ENUM_CONST(2) +#define DC_WIN_A_BLEND_NOMATCH_SELECT_0_A_BLEND_FACTOR_DST_COLOR_NOMATCH_SELECT_K2 _MK_ENUM_CONST(3) +#define DC_WIN_A_BLEND_NOMATCH_SELECT_0_A_BLEND_FACTOR_DST_COLOR_NOMATCH_SELECT_K1_TIMES_DST _MK_ENUM_CONST(4) +#define DC_WIN_A_BLEND_NOMATCH_SELECT_0_A_BLEND_FACTOR_DST_COLOR_NOMATCH_SELECT_NEG_K1_TIMES_DST _MK_ENUM_CONST(5) +#define DC_WIN_A_BLEND_NOMATCH_SELECT_0_A_BLEND_FACTOR_DST_COLOR_NOMATCH_SELECT_NEG_K1_TIMES_SRC _MK_ENUM_CONST(6) +#define DC_WIN_A_BLEND_NOMATCH_SELECT_0_A_BLEND_FACTOR_DST_COLOR_NOMATCH_SELECT_NEG_K1 _MK_ENUM_CONST(7) + +#define DC_WIN_A_BLEND_NOMATCH_SELECT_0_A_BLEND_FACTOR_SRC_ALPHA_NOMATCH_SELECT_SHIFT _MK_SHIFT_CONST(8) +#define DC_WIN_A_BLEND_NOMATCH_SELECT_0_A_BLEND_FACTOR_SRC_ALPHA_NOMATCH_SELECT_FIELD _MK_FIELD_CONST(0x3, DC_WIN_A_BLEND_NOMATCH_SELECT_0_A_BLEND_FACTOR_SRC_ALPHA_NOMATCH_SELECT_SHIFT) +#define DC_WIN_A_BLEND_NOMATCH_SELECT_0_A_BLEND_FACTOR_SRC_ALPHA_NOMATCH_SELECT_RANGE 9:8 +#define DC_WIN_A_BLEND_NOMATCH_SELECT_0_A_BLEND_FACTOR_SRC_ALPHA_NOMATCH_SELECT_WOFFSET 0x0 +#define DC_WIN_A_BLEND_NOMATCH_SELECT_0_A_BLEND_FACTOR_SRC_ALPHA_NOMATCH_SELECT_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WIN_A_BLEND_NOMATCH_SELECT_0_A_BLEND_FACTOR_SRC_ALPHA_NOMATCH_SELECT_DEFAULT_MASK _MK_MASK_CONST(0x3) +#define DC_WIN_A_BLEND_NOMATCH_SELECT_0_A_BLEND_FACTOR_SRC_ALPHA_NOMATCH_SELECT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WIN_A_BLEND_NOMATCH_SELECT_0_A_BLEND_FACTOR_SRC_ALPHA_NOMATCH_SELECT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WIN_A_BLEND_NOMATCH_SELECT_0_A_BLEND_FACTOR_SRC_ALPHA_NOMATCH_SELECT_ZERO _MK_ENUM_CONST(0) +#define DC_WIN_A_BLEND_NOMATCH_SELECT_0_A_BLEND_FACTOR_SRC_ALPHA_NOMATCH_SELECT_K1 _MK_ENUM_CONST(1) +#define DC_WIN_A_BLEND_NOMATCH_SELECT_0_A_BLEND_FACTOR_SRC_ALPHA_NOMATCH_SELECT_K2 _MK_ENUM_CONST(2) + +#define DC_WIN_A_BLEND_NOMATCH_SELECT_0_A_BLEND_FACTOR_DST_ALPHA_NOMATCH_SELECT_SHIFT _MK_SHIFT_CONST(12) +#define DC_WIN_A_BLEND_NOMATCH_SELECT_0_A_BLEND_FACTOR_DST_ALPHA_NOMATCH_SELECT_FIELD _MK_FIELD_CONST(0x3, DC_WIN_A_BLEND_NOMATCH_SELECT_0_A_BLEND_FACTOR_DST_ALPHA_NOMATCH_SELECT_SHIFT) +#define DC_WIN_A_BLEND_NOMATCH_SELECT_0_A_BLEND_FACTOR_DST_ALPHA_NOMATCH_SELECT_RANGE 13:12 +#define DC_WIN_A_BLEND_NOMATCH_SELECT_0_A_BLEND_FACTOR_DST_ALPHA_NOMATCH_SELECT_WOFFSET 0x0 +#define DC_WIN_A_BLEND_NOMATCH_SELECT_0_A_BLEND_FACTOR_DST_ALPHA_NOMATCH_SELECT_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WIN_A_BLEND_NOMATCH_SELECT_0_A_BLEND_FACTOR_DST_ALPHA_NOMATCH_SELECT_DEFAULT_MASK _MK_MASK_CONST(0x3) +#define DC_WIN_A_BLEND_NOMATCH_SELECT_0_A_BLEND_FACTOR_DST_ALPHA_NOMATCH_SELECT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WIN_A_BLEND_NOMATCH_SELECT_0_A_BLEND_FACTOR_DST_ALPHA_NOMATCH_SELECT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WIN_A_BLEND_NOMATCH_SELECT_0_A_BLEND_FACTOR_DST_ALPHA_NOMATCH_SELECT_ZERO _MK_ENUM_CONST(0) +#define DC_WIN_A_BLEND_NOMATCH_SELECT_0_A_BLEND_FACTOR_DST_ALPHA_NOMATCH_SELECT_ONE _MK_ENUM_CONST(1) +#define DC_WIN_A_BLEND_NOMATCH_SELECT_0_A_BLEND_FACTOR_DST_ALPHA_NOMATCH_SELECT_NEG_K1_TIMES_SRC _MK_ENUM_CONST(2) +#define DC_WIN_A_BLEND_NOMATCH_SELECT_0_A_BLEND_FACTOR_DST_ALPHA_NOMATCH_SELECT_K2 _MK_ENUM_CONST(3) + + +// Register DC_WIN_A_BLEND_ALPHA_1BIT_0 +#define DC_WIN_A_BLEND_ALPHA_1BIT_0 _MK_ADDR_CONST(0x719) +#define DC_WIN_A_BLEND_ALPHA_1BIT_0_SECURE 0x0 +#define DC_WIN_A_BLEND_ALPHA_1BIT_0_WORD_COUNT 0x1 +#define DC_WIN_A_BLEND_ALPHA_1BIT_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WIN_A_BLEND_ALPHA_1BIT_0_RESET_MASK _MK_MASK_CONST(0xffff) +#define DC_WIN_A_BLEND_ALPHA_1BIT_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WIN_A_BLEND_ALPHA_1BIT_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WIN_A_BLEND_ALPHA_1BIT_0_READ_MASK _MK_MASK_CONST(0xffff) +#define DC_WIN_A_BLEND_ALPHA_1BIT_0_WRITE_MASK _MK_MASK_CONST(0xffff) +#define DC_WIN_A_BLEND_ALPHA_1BIT_0_A_BLEND_WEIGHT0_SHIFT _MK_SHIFT_CONST(0) +#define DC_WIN_A_BLEND_ALPHA_1BIT_0_A_BLEND_WEIGHT0_FIELD _MK_FIELD_CONST(0xff, DC_WIN_A_BLEND_ALPHA_1BIT_0_A_BLEND_WEIGHT0_SHIFT) +#define DC_WIN_A_BLEND_ALPHA_1BIT_0_A_BLEND_WEIGHT0_RANGE 7:0 +#define DC_WIN_A_BLEND_ALPHA_1BIT_0_A_BLEND_WEIGHT0_WOFFSET 0x0 +#define DC_WIN_A_BLEND_ALPHA_1BIT_0_A_BLEND_WEIGHT0_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WIN_A_BLEND_ALPHA_1BIT_0_A_BLEND_WEIGHT0_DEFAULT_MASK _MK_MASK_CONST(0xff) +#define DC_WIN_A_BLEND_ALPHA_1BIT_0_A_BLEND_WEIGHT0_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WIN_A_BLEND_ALPHA_1BIT_0_A_BLEND_WEIGHT0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WIN_A_BLEND_ALPHA_1BIT_0_A_BLEND_WEIGHT1_SHIFT _MK_SHIFT_CONST(8) +#define DC_WIN_A_BLEND_ALPHA_1BIT_0_A_BLEND_WEIGHT1_FIELD _MK_FIELD_CONST(0xff, DC_WIN_A_BLEND_ALPHA_1BIT_0_A_BLEND_WEIGHT1_SHIFT) +#define DC_WIN_A_BLEND_ALPHA_1BIT_0_A_BLEND_WEIGHT1_RANGE 15:8 +#define DC_WIN_A_BLEND_ALPHA_1BIT_0_A_BLEND_WEIGHT1_WOFFSET 0x0 +#define DC_WIN_A_BLEND_ALPHA_1BIT_0_A_BLEND_WEIGHT1_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WIN_A_BLEND_ALPHA_1BIT_0_A_BLEND_WEIGHT1_DEFAULT_MASK _MK_MASK_CONST(0xff) +#define DC_WIN_A_BLEND_ALPHA_1BIT_0_A_BLEND_WEIGHT1_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WIN_A_BLEND_ALPHA_1BIT_0_A_BLEND_WEIGHT1_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_WINBUF_A_START_ADDR_0 +#define DC_WINBUF_A_START_ADDR_0 _MK_ADDR_CONST(0x800) +#define DC_WINBUF_A_START_ADDR_0_SECURE 0x0 +#define DC_WINBUF_A_START_ADDR_0_WORD_COUNT 0x1 +#define DC_WINBUF_A_START_ADDR_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_START_ADDR_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_START_ADDR_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_START_ADDR_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_START_ADDR_0_READ_MASK _MK_MASK_CONST(0xffffffff) +#define DC_WINBUF_A_START_ADDR_0_WRITE_MASK _MK_MASK_CONST(0xffffffff) +#define DC_WINBUF_A_START_ADDR_0_A_START_ADDR_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINBUF_A_START_ADDR_0_A_START_ADDR_FIELD _MK_FIELD_CONST(0xffffffff, DC_WINBUF_A_START_ADDR_0_A_START_ADDR_SHIFT) +#define DC_WINBUF_A_START_ADDR_0_A_START_ADDR_RANGE 31:0 +#define DC_WINBUF_A_START_ADDR_0_A_START_ADDR_WOFFSET 0x0 +#define DC_WINBUF_A_START_ADDR_0_A_START_ADDR_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_START_ADDR_0_A_START_ADDR_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_START_ADDR_0_A_START_ADDR_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_START_ADDR_0_A_START_ADDR_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_WINBUF_A_START_ADDR_NS_0 +#define DC_WINBUF_A_START_ADDR_NS_0 _MK_ADDR_CONST(0x801) +#define DC_WINBUF_A_START_ADDR_NS_0_SECURE 0x0 +#define DC_WINBUF_A_START_ADDR_NS_0_WORD_COUNT 0x1 +#define DC_WINBUF_A_START_ADDR_NS_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_START_ADDR_NS_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_START_ADDR_NS_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_START_ADDR_NS_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_START_ADDR_NS_0_READ_MASK _MK_MASK_CONST(0xffffffff) +#define DC_WINBUF_A_START_ADDR_NS_0_WRITE_MASK _MK_MASK_CONST(0xffffffff) +#define DC_WINBUF_A_START_ADDR_NS_0_A_START_ADDR_NS_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINBUF_A_START_ADDR_NS_0_A_START_ADDR_NS_FIELD _MK_FIELD_CONST(0xffffffff, DC_WINBUF_A_START_ADDR_NS_0_A_START_ADDR_NS_SHIFT) +#define DC_WINBUF_A_START_ADDR_NS_0_A_START_ADDR_NS_RANGE 31:0 +#define DC_WINBUF_A_START_ADDR_NS_0_A_START_ADDR_NS_WOFFSET 0x0 +#define DC_WINBUF_A_START_ADDR_NS_0_A_START_ADDR_NS_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_START_ADDR_NS_0_A_START_ADDR_NS_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_START_ADDR_NS_0_A_START_ADDR_NS_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_START_ADDR_NS_0_A_START_ADDR_NS_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_WINBUF_A_START_ADDR_U_0 +#define DC_WINBUF_A_START_ADDR_U_0 _MK_ADDR_CONST(0x802) +#define DC_WINBUF_A_START_ADDR_U_0_SECURE 0x0 +#define DC_WINBUF_A_START_ADDR_U_0_WORD_COUNT 0x1 +#define DC_WINBUF_A_START_ADDR_U_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_START_ADDR_U_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_START_ADDR_U_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_START_ADDR_U_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_START_ADDR_U_0_READ_MASK _MK_MASK_CONST(0xffffffff) +#define DC_WINBUF_A_START_ADDR_U_0_WRITE_MASK _MK_MASK_CONST(0xffffffff) +#define DC_WINBUF_A_START_ADDR_U_0_A_START_ADDR_U_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINBUF_A_START_ADDR_U_0_A_START_ADDR_U_FIELD _MK_FIELD_CONST(0xffffffff, DC_WINBUF_A_START_ADDR_U_0_A_START_ADDR_U_SHIFT) +#define DC_WINBUF_A_START_ADDR_U_0_A_START_ADDR_U_RANGE 31:0 +#define DC_WINBUF_A_START_ADDR_U_0_A_START_ADDR_U_WOFFSET 0x0 +#define DC_WINBUF_A_START_ADDR_U_0_A_START_ADDR_U_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_START_ADDR_U_0_A_START_ADDR_U_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_START_ADDR_U_0_A_START_ADDR_U_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_START_ADDR_U_0_A_START_ADDR_U_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_WINBUF_A_START_ADDR_U_NS_0 +#define DC_WINBUF_A_START_ADDR_U_NS_0 _MK_ADDR_CONST(0x803) +#define DC_WINBUF_A_START_ADDR_U_NS_0_SECURE 0x0 +#define DC_WINBUF_A_START_ADDR_U_NS_0_WORD_COUNT 0x1 +#define DC_WINBUF_A_START_ADDR_U_NS_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_START_ADDR_U_NS_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_START_ADDR_U_NS_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_START_ADDR_U_NS_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_START_ADDR_U_NS_0_READ_MASK _MK_MASK_CONST(0xffffffff) +#define DC_WINBUF_A_START_ADDR_U_NS_0_WRITE_MASK _MK_MASK_CONST(0xffffffff) +#define DC_WINBUF_A_START_ADDR_U_NS_0_A_START_ADDR_U_NS_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINBUF_A_START_ADDR_U_NS_0_A_START_ADDR_U_NS_FIELD _MK_FIELD_CONST(0xffffffff, DC_WINBUF_A_START_ADDR_U_NS_0_A_START_ADDR_U_NS_SHIFT) +#define DC_WINBUF_A_START_ADDR_U_NS_0_A_START_ADDR_U_NS_RANGE 31:0 +#define DC_WINBUF_A_START_ADDR_U_NS_0_A_START_ADDR_U_NS_WOFFSET 0x0 +#define DC_WINBUF_A_START_ADDR_U_NS_0_A_START_ADDR_U_NS_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_START_ADDR_U_NS_0_A_START_ADDR_U_NS_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_START_ADDR_U_NS_0_A_START_ADDR_U_NS_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_START_ADDR_U_NS_0_A_START_ADDR_U_NS_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_WINBUF_A_START_ADDR_V_0 +#define DC_WINBUF_A_START_ADDR_V_0 _MK_ADDR_CONST(0x804) +#define DC_WINBUF_A_START_ADDR_V_0_SECURE 0x0 +#define DC_WINBUF_A_START_ADDR_V_0_WORD_COUNT 0x1 +#define DC_WINBUF_A_START_ADDR_V_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_START_ADDR_V_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_START_ADDR_V_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_START_ADDR_V_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_START_ADDR_V_0_READ_MASK _MK_MASK_CONST(0xffffffff) +#define DC_WINBUF_A_START_ADDR_V_0_WRITE_MASK _MK_MASK_CONST(0xffffffff) +#define DC_WINBUF_A_START_ADDR_V_0_A_START_ADDR_V_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINBUF_A_START_ADDR_V_0_A_START_ADDR_V_FIELD _MK_FIELD_CONST(0xffffffff, DC_WINBUF_A_START_ADDR_V_0_A_START_ADDR_V_SHIFT) +#define DC_WINBUF_A_START_ADDR_V_0_A_START_ADDR_V_RANGE 31:0 +#define DC_WINBUF_A_START_ADDR_V_0_A_START_ADDR_V_WOFFSET 0x0 +#define DC_WINBUF_A_START_ADDR_V_0_A_START_ADDR_V_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_START_ADDR_V_0_A_START_ADDR_V_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_START_ADDR_V_0_A_START_ADDR_V_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_START_ADDR_V_0_A_START_ADDR_V_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_WINBUF_A_START_ADDR_V_NS_0 +#define DC_WINBUF_A_START_ADDR_V_NS_0 _MK_ADDR_CONST(0x805) +#define DC_WINBUF_A_START_ADDR_V_NS_0_SECURE 0x0 +#define DC_WINBUF_A_START_ADDR_V_NS_0_WORD_COUNT 0x1 +#define DC_WINBUF_A_START_ADDR_V_NS_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_START_ADDR_V_NS_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_START_ADDR_V_NS_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_START_ADDR_V_NS_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_START_ADDR_V_NS_0_READ_MASK _MK_MASK_CONST(0xffffffff) +#define DC_WINBUF_A_START_ADDR_V_NS_0_WRITE_MASK _MK_MASK_CONST(0xffffffff) +#define DC_WINBUF_A_START_ADDR_V_NS_0_A_START_ADDR_V_NS_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINBUF_A_START_ADDR_V_NS_0_A_START_ADDR_V_NS_FIELD _MK_FIELD_CONST(0xffffffff, DC_WINBUF_A_START_ADDR_V_NS_0_A_START_ADDR_V_NS_SHIFT) +#define DC_WINBUF_A_START_ADDR_V_NS_0_A_START_ADDR_V_NS_RANGE 31:0 +#define DC_WINBUF_A_START_ADDR_V_NS_0_A_START_ADDR_V_NS_WOFFSET 0x0 +#define DC_WINBUF_A_START_ADDR_V_NS_0_A_START_ADDR_V_NS_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_START_ADDR_V_NS_0_A_START_ADDR_V_NS_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_START_ADDR_V_NS_0_A_START_ADDR_V_NS_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_START_ADDR_V_NS_0_A_START_ADDR_V_NS_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_WINBUF_A_ADDR_H_OFFSET_0 +#define DC_WINBUF_A_ADDR_H_OFFSET_0 _MK_ADDR_CONST(0x806) +#define DC_WINBUF_A_ADDR_H_OFFSET_0_SECURE 0x0 +#define DC_WINBUF_A_ADDR_H_OFFSET_0_WORD_COUNT 0x1 +#define DC_WINBUF_A_ADDR_H_OFFSET_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_ADDR_H_OFFSET_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_ADDR_H_OFFSET_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_ADDR_H_OFFSET_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_ADDR_H_OFFSET_0_READ_MASK _MK_MASK_CONST(0xffffffff) +#define DC_WINBUF_A_ADDR_H_OFFSET_0_WRITE_MASK _MK_MASK_CONST(0xffffffff) +#define DC_WINBUF_A_ADDR_H_OFFSET_0_A_ADDR_H_OFFSET_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINBUF_A_ADDR_H_OFFSET_0_A_ADDR_H_OFFSET_FIELD _MK_FIELD_CONST(0xffffffff, DC_WINBUF_A_ADDR_H_OFFSET_0_A_ADDR_H_OFFSET_SHIFT) +#define DC_WINBUF_A_ADDR_H_OFFSET_0_A_ADDR_H_OFFSET_RANGE 31:0 +#define DC_WINBUF_A_ADDR_H_OFFSET_0_A_ADDR_H_OFFSET_WOFFSET 0x0 +#define DC_WINBUF_A_ADDR_H_OFFSET_0_A_ADDR_H_OFFSET_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_ADDR_H_OFFSET_0_A_ADDR_H_OFFSET_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_ADDR_H_OFFSET_0_A_ADDR_H_OFFSET_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_ADDR_H_OFFSET_0_A_ADDR_H_OFFSET_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_WINBUF_A_ADDR_H_OFFSET_NS_0 +#define DC_WINBUF_A_ADDR_H_OFFSET_NS_0 _MK_ADDR_CONST(0x807) +#define DC_WINBUF_A_ADDR_H_OFFSET_NS_0_SECURE 0x0 +#define DC_WINBUF_A_ADDR_H_OFFSET_NS_0_WORD_COUNT 0x1 +#define DC_WINBUF_A_ADDR_H_OFFSET_NS_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_ADDR_H_OFFSET_NS_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_ADDR_H_OFFSET_NS_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_ADDR_H_OFFSET_NS_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_ADDR_H_OFFSET_NS_0_READ_MASK _MK_MASK_CONST(0xffffffff) +#define DC_WINBUF_A_ADDR_H_OFFSET_NS_0_WRITE_MASK _MK_MASK_CONST(0xffffffff) +#define DC_WINBUF_A_ADDR_H_OFFSET_NS_0_A_ADDR_H_OFFSET_NS_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINBUF_A_ADDR_H_OFFSET_NS_0_A_ADDR_H_OFFSET_NS_FIELD _MK_FIELD_CONST(0xffffffff, DC_WINBUF_A_ADDR_H_OFFSET_NS_0_A_ADDR_H_OFFSET_NS_SHIFT) +#define DC_WINBUF_A_ADDR_H_OFFSET_NS_0_A_ADDR_H_OFFSET_NS_RANGE 31:0 +#define DC_WINBUF_A_ADDR_H_OFFSET_NS_0_A_ADDR_H_OFFSET_NS_WOFFSET 0x0 +#define DC_WINBUF_A_ADDR_H_OFFSET_NS_0_A_ADDR_H_OFFSET_NS_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_ADDR_H_OFFSET_NS_0_A_ADDR_H_OFFSET_NS_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_ADDR_H_OFFSET_NS_0_A_ADDR_H_OFFSET_NS_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_ADDR_H_OFFSET_NS_0_A_ADDR_H_OFFSET_NS_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_WINBUF_A_ADDR_V_OFFSET_0 +#define DC_WINBUF_A_ADDR_V_OFFSET_0 _MK_ADDR_CONST(0x808) +#define DC_WINBUF_A_ADDR_V_OFFSET_0_SECURE 0x0 +#define DC_WINBUF_A_ADDR_V_OFFSET_0_WORD_COUNT 0x1 +#define DC_WINBUF_A_ADDR_V_OFFSET_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_ADDR_V_OFFSET_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_ADDR_V_OFFSET_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_ADDR_V_OFFSET_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_ADDR_V_OFFSET_0_READ_MASK _MK_MASK_CONST(0xffffffff) +#define DC_WINBUF_A_ADDR_V_OFFSET_0_WRITE_MASK _MK_MASK_CONST(0xffffffff) +#define DC_WINBUF_A_ADDR_V_OFFSET_0_A_ADDR_V_OFFSET_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINBUF_A_ADDR_V_OFFSET_0_A_ADDR_V_OFFSET_FIELD _MK_FIELD_CONST(0xffffffff, DC_WINBUF_A_ADDR_V_OFFSET_0_A_ADDR_V_OFFSET_SHIFT) +#define DC_WINBUF_A_ADDR_V_OFFSET_0_A_ADDR_V_OFFSET_RANGE 31:0 +#define DC_WINBUF_A_ADDR_V_OFFSET_0_A_ADDR_V_OFFSET_WOFFSET 0x0 +#define DC_WINBUF_A_ADDR_V_OFFSET_0_A_ADDR_V_OFFSET_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_ADDR_V_OFFSET_0_A_ADDR_V_OFFSET_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_ADDR_V_OFFSET_0_A_ADDR_V_OFFSET_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_ADDR_V_OFFSET_0_A_ADDR_V_OFFSET_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_WINBUF_A_ADDR_V_OFFSET_NS_0 +#define DC_WINBUF_A_ADDR_V_OFFSET_NS_0 _MK_ADDR_CONST(0x809) +#define DC_WINBUF_A_ADDR_V_OFFSET_NS_0_SECURE 0x0 +#define DC_WINBUF_A_ADDR_V_OFFSET_NS_0_WORD_COUNT 0x1 +#define DC_WINBUF_A_ADDR_V_OFFSET_NS_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_ADDR_V_OFFSET_NS_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_ADDR_V_OFFSET_NS_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_ADDR_V_OFFSET_NS_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_ADDR_V_OFFSET_NS_0_READ_MASK _MK_MASK_CONST(0xffffffff) +#define DC_WINBUF_A_ADDR_V_OFFSET_NS_0_WRITE_MASK _MK_MASK_CONST(0xffffffff) +#define DC_WINBUF_A_ADDR_V_OFFSET_NS_0_A_ADDR_V_OFFSET_NS_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINBUF_A_ADDR_V_OFFSET_NS_0_A_ADDR_V_OFFSET_NS_FIELD _MK_FIELD_CONST(0xffffffff, DC_WINBUF_A_ADDR_V_OFFSET_NS_0_A_ADDR_V_OFFSET_NS_SHIFT) +#define DC_WINBUF_A_ADDR_V_OFFSET_NS_0_A_ADDR_V_OFFSET_NS_RANGE 31:0 +#define DC_WINBUF_A_ADDR_V_OFFSET_NS_0_A_ADDR_V_OFFSET_NS_WOFFSET 0x0 +#define DC_WINBUF_A_ADDR_V_OFFSET_NS_0_A_ADDR_V_OFFSET_NS_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_ADDR_V_OFFSET_NS_0_A_ADDR_V_OFFSET_NS_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_ADDR_V_OFFSET_NS_0_A_ADDR_V_OFFSET_NS_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_ADDR_V_OFFSET_NS_0_A_ADDR_V_OFFSET_NS_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_WINBUF_A_UFLOW_STATUS_0 +#define DC_WINBUF_A_UFLOW_STATUS_0 _MK_ADDR_CONST(0x80a) +#define DC_WINBUF_A_UFLOW_STATUS_0_SECURE 0x0 +#define DC_WINBUF_A_UFLOW_STATUS_0_WORD_COUNT 0x1 +#define DC_WINBUF_A_UFLOW_STATUS_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_UFLOW_STATUS_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_UFLOW_STATUS_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_UFLOW_STATUS_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_UFLOW_STATUS_0_READ_MASK _MK_MASK_CONST(0x40ffffff) +#define DC_WINBUF_A_UFLOW_STATUS_0_WRITE_MASK _MK_MASK_CONST(0x40ffffff) +#define DC_WINBUF_A_UFLOW_STATUS_0_UFLOW_COUNT_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINBUF_A_UFLOW_STATUS_0_UFLOW_COUNT_FIELD _MK_FIELD_CONST(0xffffff, DC_WINBUF_A_UFLOW_STATUS_0_UFLOW_COUNT_SHIFT) +#define DC_WINBUF_A_UFLOW_STATUS_0_UFLOW_COUNT_RANGE 23:0 +#define DC_WINBUF_A_UFLOW_STATUS_0_UFLOW_COUNT_WOFFSET 0x0 +#define DC_WINBUF_A_UFLOW_STATUS_0_UFLOW_COUNT_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_UFLOW_STATUS_0_UFLOW_COUNT_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_UFLOW_STATUS_0_UFLOW_COUNT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_UFLOW_STATUS_0_UFLOW_COUNT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINBUF_A_UFLOW_STATUS_0_COUNT_OFLOW_SHIFT _MK_SHIFT_CONST(30) +#define DC_WINBUF_A_UFLOW_STATUS_0_COUNT_OFLOW_FIELD _MK_FIELD_CONST(0x1, DC_WINBUF_A_UFLOW_STATUS_0_COUNT_OFLOW_SHIFT) +#define DC_WINBUF_A_UFLOW_STATUS_0_COUNT_OFLOW_RANGE 30:30 +#define DC_WINBUF_A_UFLOW_STATUS_0_COUNT_OFLOW_WOFFSET 0x0 +#define DC_WINBUF_A_UFLOW_STATUS_0_COUNT_OFLOW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_UFLOW_STATUS_0_COUNT_OFLOW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_UFLOW_STATUS_0_COUNT_OFLOW_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_UFLOW_STATUS_0_COUNT_OFLOW_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_WINBUF_A_SURFACE_KIND_0 +#define DC_WINBUF_A_SURFACE_KIND_0 _MK_ADDR_CONST(0x80b) +#define DC_WINBUF_A_SURFACE_KIND_0_SECURE 0x0 +#define DC_WINBUF_A_SURFACE_KIND_0_WORD_COUNT 0x1 +#define DC_WINBUF_A_SURFACE_KIND_0_RESET_VAL _MK_MASK_CONST(0x10) +#define DC_WINBUF_A_SURFACE_KIND_0_RESET_MASK _MK_MASK_CONST(0x73) +#define DC_WINBUF_A_SURFACE_KIND_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_SURFACE_KIND_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_SURFACE_KIND_0_READ_MASK _MK_MASK_CONST(0x73) +#define DC_WINBUF_A_SURFACE_KIND_0_WRITE_MASK _MK_MASK_CONST(0x73) +#define DC_WINBUF_A_SURFACE_KIND_0_A_SURFACE_KIND_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINBUF_A_SURFACE_KIND_0_A_SURFACE_KIND_FIELD _MK_FIELD_CONST(0x3, DC_WINBUF_A_SURFACE_KIND_0_A_SURFACE_KIND_SHIFT) +#define DC_WINBUF_A_SURFACE_KIND_0_A_SURFACE_KIND_RANGE 1:0 +#define DC_WINBUF_A_SURFACE_KIND_0_A_SURFACE_KIND_WOFFSET 0x0 +#define DC_WINBUF_A_SURFACE_KIND_0_A_SURFACE_KIND_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_SURFACE_KIND_0_A_SURFACE_KIND_DEFAULT_MASK _MK_MASK_CONST(0x3) +#define DC_WINBUF_A_SURFACE_KIND_0_A_SURFACE_KIND_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_SURFACE_KIND_0_A_SURFACE_KIND_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_SURFACE_KIND_0_A_SURFACE_KIND_PITCH _MK_ENUM_CONST(0) +#define DC_WINBUF_A_SURFACE_KIND_0_A_SURFACE_KIND_TILED _MK_ENUM_CONST(1) +#define DC_WINBUF_A_SURFACE_KIND_0_A_SURFACE_KIND_BL_16B2 _MK_ENUM_CONST(2) + +#define DC_WINBUF_A_SURFACE_KIND_0_A_BLOCK_HEIGHT_SHIFT _MK_SHIFT_CONST(4) +#define DC_WINBUF_A_SURFACE_KIND_0_A_BLOCK_HEIGHT_FIELD _MK_FIELD_CONST(0x7, DC_WINBUF_A_SURFACE_KIND_0_A_BLOCK_HEIGHT_SHIFT) +#define DC_WINBUF_A_SURFACE_KIND_0_A_BLOCK_HEIGHT_RANGE 6:4 +#define DC_WINBUF_A_SURFACE_KIND_0_A_BLOCK_HEIGHT_WOFFSET 0x0 +#define DC_WINBUF_A_SURFACE_KIND_0_A_BLOCK_HEIGHT_DEFAULT _MK_MASK_CONST(0x1) +#define DC_WINBUF_A_SURFACE_KIND_0_A_BLOCK_HEIGHT_DEFAULT_MASK _MK_MASK_CONST(0x7) +#define DC_WINBUF_A_SURFACE_KIND_0_A_BLOCK_HEIGHT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_SURFACE_KIND_0_A_BLOCK_HEIGHT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_SURFACE_KIND_0_A_BLOCK_HEIGHT_HEIGHT_1 _MK_ENUM_CONST(0) +#define DC_WINBUF_A_SURFACE_KIND_0_A_BLOCK_HEIGHT_HEIGHT_2 _MK_ENUM_CONST(1) +#define DC_WINBUF_A_SURFACE_KIND_0_A_BLOCK_HEIGHT_HEIGHT_4 _MK_ENUM_CONST(2) +#define DC_WINBUF_A_SURFACE_KIND_0_A_BLOCK_HEIGHT_HEIGHT_8 _MK_ENUM_CONST(3) +#define DC_WINBUF_A_SURFACE_KIND_0_A_BLOCK_HEIGHT_HEIGHT_16 _MK_ENUM_CONST(4) +#define DC_WINBUF_A_SURFACE_KIND_0_A_BLOCK_HEIGHT_HEIGHT_32 _MK_ENUM_CONST(5) + + +// Register DC_WINBUF_A_SURFACE_WEIGHT_0 +#define DC_WINBUF_A_SURFACE_WEIGHT_0 _MK_ADDR_CONST(0x80c) +#define DC_WINBUF_A_SURFACE_WEIGHT_0_SECURE 0x0 +#define DC_WINBUF_A_SURFACE_WEIGHT_0_WORD_COUNT 0x1 +#define DC_WINBUF_A_SURFACE_WEIGHT_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_SURFACE_WEIGHT_0_RESET_MASK _MK_MASK_CONST(0x1) +#define DC_WINBUF_A_SURFACE_WEIGHT_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_SURFACE_WEIGHT_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_SURFACE_WEIGHT_0_READ_MASK _MK_MASK_CONST(0x7f) +#define DC_WINBUF_A_SURFACE_WEIGHT_0_WRITE_MASK _MK_MASK_CONST(0x7f) +#define DC_WINBUF_A_SURFACE_WEIGHT_0_A_SURFACE_WEIGHT_OVERRIDE_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINBUF_A_SURFACE_WEIGHT_0_A_SURFACE_WEIGHT_OVERRIDE_FIELD _MK_FIELD_CONST(0x1, DC_WINBUF_A_SURFACE_WEIGHT_0_A_SURFACE_WEIGHT_OVERRIDE_SHIFT) +#define DC_WINBUF_A_SURFACE_WEIGHT_0_A_SURFACE_WEIGHT_OVERRIDE_RANGE 0:0 +#define DC_WINBUF_A_SURFACE_WEIGHT_0_A_SURFACE_WEIGHT_OVERRIDE_WOFFSET 0x0 +#define DC_WINBUF_A_SURFACE_WEIGHT_0_A_SURFACE_WEIGHT_OVERRIDE_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_SURFACE_WEIGHT_0_A_SURFACE_WEIGHT_OVERRIDE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_WINBUF_A_SURFACE_WEIGHT_0_A_SURFACE_WEIGHT_OVERRIDE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_SURFACE_WEIGHT_0_A_SURFACE_WEIGHT_OVERRIDE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_SURFACE_WEIGHT_0_A_SURFACE_WEIGHT_OVERRIDE_DISABLE _MK_ENUM_CONST(0) +#define DC_WINBUF_A_SURFACE_WEIGHT_0_A_SURFACE_WEIGHT_OVERRIDE_ENABLE _MK_ENUM_CONST(1) + +#define DC_WINBUF_A_SURFACE_WEIGHT_0_A_SURFACE_WEIGHT_Y_SHIFT _MK_SHIFT_CONST(1) +#define DC_WINBUF_A_SURFACE_WEIGHT_0_A_SURFACE_WEIGHT_Y_FIELD _MK_FIELD_CONST(0x3, DC_WINBUF_A_SURFACE_WEIGHT_0_A_SURFACE_WEIGHT_Y_SHIFT) +#define DC_WINBUF_A_SURFACE_WEIGHT_0_A_SURFACE_WEIGHT_Y_RANGE 2:1 +#define DC_WINBUF_A_SURFACE_WEIGHT_0_A_SURFACE_WEIGHT_Y_WOFFSET 0x0 +#define DC_WINBUF_A_SURFACE_WEIGHT_0_A_SURFACE_WEIGHT_Y_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_SURFACE_WEIGHT_0_A_SURFACE_WEIGHT_Y_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_SURFACE_WEIGHT_0_A_SURFACE_WEIGHT_Y_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_SURFACE_WEIGHT_0_A_SURFACE_WEIGHT_Y_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_SURFACE_WEIGHT_0_A_SURFACE_WEIGHT_Y_WEIGHT_2 _MK_ENUM_CONST(0) +#define DC_WINBUF_A_SURFACE_WEIGHT_0_A_SURFACE_WEIGHT_Y_WEIGHT_4 _MK_ENUM_CONST(1) +#define DC_WINBUF_A_SURFACE_WEIGHT_0_A_SURFACE_WEIGHT_Y_WEIGHT_8 _MK_ENUM_CONST(2) +#define DC_WINBUF_A_SURFACE_WEIGHT_0_A_SURFACE_WEIGHT_Y_WEIGHT_16 _MK_ENUM_CONST(3) + +#define DC_WINBUF_A_SURFACE_WEIGHT_0_A_SURFACE_WEIGHT_U_SHIFT _MK_SHIFT_CONST(3) +#define DC_WINBUF_A_SURFACE_WEIGHT_0_A_SURFACE_WEIGHT_U_FIELD _MK_FIELD_CONST(0x3, DC_WINBUF_A_SURFACE_WEIGHT_0_A_SURFACE_WEIGHT_U_SHIFT) +#define DC_WINBUF_A_SURFACE_WEIGHT_0_A_SURFACE_WEIGHT_U_RANGE 4:3 +#define DC_WINBUF_A_SURFACE_WEIGHT_0_A_SURFACE_WEIGHT_U_WOFFSET 0x0 +#define DC_WINBUF_A_SURFACE_WEIGHT_0_A_SURFACE_WEIGHT_U_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_SURFACE_WEIGHT_0_A_SURFACE_WEIGHT_U_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_SURFACE_WEIGHT_0_A_SURFACE_WEIGHT_U_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_SURFACE_WEIGHT_0_A_SURFACE_WEIGHT_U_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_SURFACE_WEIGHT_0_A_SURFACE_WEIGHT_U_WEIGHT_2 _MK_ENUM_CONST(0) +#define DC_WINBUF_A_SURFACE_WEIGHT_0_A_SURFACE_WEIGHT_U_WEIGHT_4 _MK_ENUM_CONST(1) +#define DC_WINBUF_A_SURFACE_WEIGHT_0_A_SURFACE_WEIGHT_U_WEIGHT_8 _MK_ENUM_CONST(2) +#define DC_WINBUF_A_SURFACE_WEIGHT_0_A_SURFACE_WEIGHT_U_WEIGHT_16 _MK_ENUM_CONST(3) + +#define DC_WINBUF_A_SURFACE_WEIGHT_0_A_SURFACE_WEIGHT_V_SHIFT _MK_SHIFT_CONST(5) +#define DC_WINBUF_A_SURFACE_WEIGHT_0_A_SURFACE_WEIGHT_V_FIELD _MK_FIELD_CONST(0x3, DC_WINBUF_A_SURFACE_WEIGHT_0_A_SURFACE_WEIGHT_V_SHIFT) +#define DC_WINBUF_A_SURFACE_WEIGHT_0_A_SURFACE_WEIGHT_V_RANGE 6:5 +#define DC_WINBUF_A_SURFACE_WEIGHT_0_A_SURFACE_WEIGHT_V_WOFFSET 0x0 +#define DC_WINBUF_A_SURFACE_WEIGHT_0_A_SURFACE_WEIGHT_V_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_SURFACE_WEIGHT_0_A_SURFACE_WEIGHT_V_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_SURFACE_WEIGHT_0_A_SURFACE_WEIGHT_V_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_SURFACE_WEIGHT_0_A_SURFACE_WEIGHT_V_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_SURFACE_WEIGHT_0_A_SURFACE_WEIGHT_V_WEIGHT_2 _MK_ENUM_CONST(0) +#define DC_WINBUF_A_SURFACE_WEIGHT_0_A_SURFACE_WEIGHT_V_WEIGHT_4 _MK_ENUM_CONST(1) +#define DC_WINBUF_A_SURFACE_WEIGHT_0_A_SURFACE_WEIGHT_V_WEIGHT_8 _MK_ENUM_CONST(2) +#define DC_WINBUF_A_SURFACE_WEIGHT_0_A_SURFACE_WEIGHT_V_WEIGHT_16 _MK_ENUM_CONST(3) + + +// Register DC_WINBUF_A_START_ADDR_HI_0 +#define DC_WINBUF_A_START_ADDR_HI_0 _MK_ADDR_CONST(0x80d) +#define DC_WINBUF_A_START_ADDR_HI_0_SECURE 0x0 +#define DC_WINBUF_A_START_ADDR_HI_0_WORD_COUNT 0x1 +#define DC_WINBUF_A_START_ADDR_HI_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_START_ADDR_HI_0_RESET_MASK _MK_MASK_CONST(0x3) +#define DC_WINBUF_A_START_ADDR_HI_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_START_ADDR_HI_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_START_ADDR_HI_0_READ_MASK _MK_MASK_CONST(0x3) +#define DC_WINBUF_A_START_ADDR_HI_0_WRITE_MASK _MK_MASK_CONST(0x3) +#define DC_WINBUF_A_START_ADDR_HI_0_A_START_ADDR_HI_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINBUF_A_START_ADDR_HI_0_A_START_ADDR_HI_FIELD _MK_FIELD_CONST(0x3, DC_WINBUF_A_START_ADDR_HI_0_A_START_ADDR_HI_SHIFT) +#define DC_WINBUF_A_START_ADDR_HI_0_A_START_ADDR_HI_RANGE 1:0 +#define DC_WINBUF_A_START_ADDR_HI_0_A_START_ADDR_HI_WOFFSET 0x0 +#define DC_WINBUF_A_START_ADDR_HI_0_A_START_ADDR_HI_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_START_ADDR_HI_0_A_START_ADDR_HI_DEFAULT_MASK _MK_MASK_CONST(0x3) +#define DC_WINBUF_A_START_ADDR_HI_0_A_START_ADDR_HI_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_START_ADDR_HI_0_A_START_ADDR_HI_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_WINBUF_A_START_ADDR_HI_NS_0 +#define DC_WINBUF_A_START_ADDR_HI_NS_0 _MK_ADDR_CONST(0x80e) +#define DC_WINBUF_A_START_ADDR_HI_NS_0_SECURE 0x0 +#define DC_WINBUF_A_START_ADDR_HI_NS_0_WORD_COUNT 0x1 +#define DC_WINBUF_A_START_ADDR_HI_NS_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_START_ADDR_HI_NS_0_RESET_MASK _MK_MASK_CONST(0x3) +#define DC_WINBUF_A_START_ADDR_HI_NS_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_START_ADDR_HI_NS_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_START_ADDR_HI_NS_0_READ_MASK _MK_MASK_CONST(0x3) +#define DC_WINBUF_A_START_ADDR_HI_NS_0_WRITE_MASK _MK_MASK_CONST(0x3) +#define DC_WINBUF_A_START_ADDR_HI_NS_0_A_START_ADDR_HI_NS_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINBUF_A_START_ADDR_HI_NS_0_A_START_ADDR_HI_NS_FIELD _MK_FIELD_CONST(0x3, DC_WINBUF_A_START_ADDR_HI_NS_0_A_START_ADDR_HI_NS_SHIFT) +#define DC_WINBUF_A_START_ADDR_HI_NS_0_A_START_ADDR_HI_NS_RANGE 1:0 +#define DC_WINBUF_A_START_ADDR_HI_NS_0_A_START_ADDR_HI_NS_WOFFSET 0x0 +#define DC_WINBUF_A_START_ADDR_HI_NS_0_A_START_ADDR_HI_NS_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_START_ADDR_HI_NS_0_A_START_ADDR_HI_NS_DEFAULT_MASK _MK_MASK_CONST(0x3) +#define DC_WINBUF_A_START_ADDR_HI_NS_0_A_START_ADDR_HI_NS_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_START_ADDR_HI_NS_0_A_START_ADDR_HI_NS_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_WINBUF_A_START_ADDR_HI_U_0 +#define DC_WINBUF_A_START_ADDR_HI_U_0 _MK_ADDR_CONST(0x80f) +#define DC_WINBUF_A_START_ADDR_HI_U_0_SECURE 0x0 +#define DC_WINBUF_A_START_ADDR_HI_U_0_WORD_COUNT 0x1 +#define DC_WINBUF_A_START_ADDR_HI_U_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_START_ADDR_HI_U_0_RESET_MASK _MK_MASK_CONST(0x3) +#define DC_WINBUF_A_START_ADDR_HI_U_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_START_ADDR_HI_U_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_START_ADDR_HI_U_0_READ_MASK _MK_MASK_CONST(0x3) +#define DC_WINBUF_A_START_ADDR_HI_U_0_WRITE_MASK _MK_MASK_CONST(0x3) +#define DC_WINBUF_A_START_ADDR_HI_U_0_A_START_ADDR_HI_U_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINBUF_A_START_ADDR_HI_U_0_A_START_ADDR_HI_U_FIELD _MK_FIELD_CONST(0x3, DC_WINBUF_A_START_ADDR_HI_U_0_A_START_ADDR_HI_U_SHIFT) +#define DC_WINBUF_A_START_ADDR_HI_U_0_A_START_ADDR_HI_U_RANGE 1:0 +#define DC_WINBUF_A_START_ADDR_HI_U_0_A_START_ADDR_HI_U_WOFFSET 0x0 +#define DC_WINBUF_A_START_ADDR_HI_U_0_A_START_ADDR_HI_U_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_START_ADDR_HI_U_0_A_START_ADDR_HI_U_DEFAULT_MASK _MK_MASK_CONST(0x3) +#define DC_WINBUF_A_START_ADDR_HI_U_0_A_START_ADDR_HI_U_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_START_ADDR_HI_U_0_A_START_ADDR_HI_U_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_WINBUF_A_START_ADDR_HI_U_NS_0 +#define DC_WINBUF_A_START_ADDR_HI_U_NS_0 _MK_ADDR_CONST(0x810) +#define DC_WINBUF_A_START_ADDR_HI_U_NS_0_SECURE 0x0 +#define DC_WINBUF_A_START_ADDR_HI_U_NS_0_WORD_COUNT 0x1 +#define DC_WINBUF_A_START_ADDR_HI_U_NS_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_START_ADDR_HI_U_NS_0_RESET_MASK _MK_MASK_CONST(0x3) +#define DC_WINBUF_A_START_ADDR_HI_U_NS_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_START_ADDR_HI_U_NS_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_START_ADDR_HI_U_NS_0_READ_MASK _MK_MASK_CONST(0x3) +#define DC_WINBUF_A_START_ADDR_HI_U_NS_0_WRITE_MASK _MK_MASK_CONST(0x3) +#define DC_WINBUF_A_START_ADDR_HI_U_NS_0_A_START_ADDR_HI_U_NS_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINBUF_A_START_ADDR_HI_U_NS_0_A_START_ADDR_HI_U_NS_FIELD _MK_FIELD_CONST(0x3, DC_WINBUF_A_START_ADDR_HI_U_NS_0_A_START_ADDR_HI_U_NS_SHIFT) +#define DC_WINBUF_A_START_ADDR_HI_U_NS_0_A_START_ADDR_HI_U_NS_RANGE 1:0 +#define DC_WINBUF_A_START_ADDR_HI_U_NS_0_A_START_ADDR_HI_U_NS_WOFFSET 0x0 +#define DC_WINBUF_A_START_ADDR_HI_U_NS_0_A_START_ADDR_HI_U_NS_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_START_ADDR_HI_U_NS_0_A_START_ADDR_HI_U_NS_DEFAULT_MASK _MK_MASK_CONST(0x3) +#define DC_WINBUF_A_START_ADDR_HI_U_NS_0_A_START_ADDR_HI_U_NS_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_START_ADDR_HI_U_NS_0_A_START_ADDR_HI_U_NS_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_WINBUF_A_START_ADDR_HI_V_0 +#define DC_WINBUF_A_START_ADDR_HI_V_0 _MK_ADDR_CONST(0x811) +#define DC_WINBUF_A_START_ADDR_HI_V_0_SECURE 0x0 +#define DC_WINBUF_A_START_ADDR_HI_V_0_WORD_COUNT 0x1 +#define DC_WINBUF_A_START_ADDR_HI_V_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_START_ADDR_HI_V_0_RESET_MASK _MK_MASK_CONST(0x3) +#define DC_WINBUF_A_START_ADDR_HI_V_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_START_ADDR_HI_V_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_START_ADDR_HI_V_0_READ_MASK _MK_MASK_CONST(0x3) +#define DC_WINBUF_A_START_ADDR_HI_V_0_WRITE_MASK _MK_MASK_CONST(0x3) +#define DC_WINBUF_A_START_ADDR_HI_V_0_A_START_ADDR_HI_V_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINBUF_A_START_ADDR_HI_V_0_A_START_ADDR_HI_V_FIELD _MK_FIELD_CONST(0x3, DC_WINBUF_A_START_ADDR_HI_V_0_A_START_ADDR_HI_V_SHIFT) +#define DC_WINBUF_A_START_ADDR_HI_V_0_A_START_ADDR_HI_V_RANGE 1:0 +#define DC_WINBUF_A_START_ADDR_HI_V_0_A_START_ADDR_HI_V_WOFFSET 0x0 +#define DC_WINBUF_A_START_ADDR_HI_V_0_A_START_ADDR_HI_V_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_START_ADDR_HI_V_0_A_START_ADDR_HI_V_DEFAULT_MASK _MK_MASK_CONST(0x3) +#define DC_WINBUF_A_START_ADDR_HI_V_0_A_START_ADDR_HI_V_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_START_ADDR_HI_V_0_A_START_ADDR_HI_V_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_WINBUF_A_START_ADDR_HI_V_NS_0 +#define DC_WINBUF_A_START_ADDR_HI_V_NS_0 _MK_ADDR_CONST(0x812) +#define DC_WINBUF_A_START_ADDR_HI_V_NS_0_SECURE 0x0 +#define DC_WINBUF_A_START_ADDR_HI_V_NS_0_WORD_COUNT 0x1 +#define DC_WINBUF_A_START_ADDR_HI_V_NS_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_START_ADDR_HI_V_NS_0_RESET_MASK _MK_MASK_CONST(0x3) +#define DC_WINBUF_A_START_ADDR_HI_V_NS_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_START_ADDR_HI_V_NS_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_START_ADDR_HI_V_NS_0_READ_MASK _MK_MASK_CONST(0x3) +#define DC_WINBUF_A_START_ADDR_HI_V_NS_0_WRITE_MASK _MK_MASK_CONST(0x3) +#define DC_WINBUF_A_START_ADDR_HI_V_NS_0_A_START_ADDR_HI_V_NS_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINBUF_A_START_ADDR_HI_V_NS_0_A_START_ADDR_HI_V_NS_FIELD _MK_FIELD_CONST(0x3, DC_WINBUF_A_START_ADDR_HI_V_NS_0_A_START_ADDR_HI_V_NS_SHIFT) +#define DC_WINBUF_A_START_ADDR_HI_V_NS_0_A_START_ADDR_HI_V_NS_RANGE 1:0 +#define DC_WINBUF_A_START_ADDR_HI_V_NS_0_A_START_ADDR_HI_V_NS_WOFFSET 0x0 +#define DC_WINBUF_A_START_ADDR_HI_V_NS_0_A_START_ADDR_HI_V_NS_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_START_ADDR_HI_V_NS_0_A_START_ADDR_HI_V_NS_DEFAULT_MASK _MK_MASK_CONST(0x3) +#define DC_WINBUF_A_START_ADDR_HI_V_NS_0_A_START_ADDR_HI_V_NS_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_START_ADDR_HI_V_NS_0_A_START_ADDR_HI_V_NS_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_WINBUF_A_START_ADDR_FIELD2_0 +#define DC_WINBUF_A_START_ADDR_FIELD2_0 _MK_ADDR_CONST(0x813) +#define DC_WINBUF_A_START_ADDR_FIELD2_0_SECURE 0x0 +#define DC_WINBUF_A_START_ADDR_FIELD2_0_WORD_COUNT 0x1 +#define DC_WINBUF_A_START_ADDR_FIELD2_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_START_ADDR_FIELD2_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_START_ADDR_FIELD2_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_START_ADDR_FIELD2_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_START_ADDR_FIELD2_0_READ_MASK _MK_MASK_CONST(0xffffffff) +#define DC_WINBUF_A_START_ADDR_FIELD2_0_WRITE_MASK _MK_MASK_CONST(0xffffffff) +#define DC_WINBUF_A_START_ADDR_FIELD2_0_A_START_ADDR_FIELD2_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINBUF_A_START_ADDR_FIELD2_0_A_START_ADDR_FIELD2_FIELD _MK_FIELD_CONST(0xffffffff, DC_WINBUF_A_START_ADDR_FIELD2_0_A_START_ADDR_FIELD2_SHIFT) +#define DC_WINBUF_A_START_ADDR_FIELD2_0_A_START_ADDR_FIELD2_RANGE 31:0 +#define DC_WINBUF_A_START_ADDR_FIELD2_0_A_START_ADDR_FIELD2_WOFFSET 0x0 +#define DC_WINBUF_A_START_ADDR_FIELD2_0_A_START_ADDR_FIELD2_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_START_ADDR_FIELD2_0_A_START_ADDR_FIELD2_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_START_ADDR_FIELD2_0_A_START_ADDR_FIELD2_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_START_ADDR_FIELD2_0_A_START_ADDR_FIELD2_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_WINBUF_A_START_ADDR_FIELD2_NS_0 +#define DC_WINBUF_A_START_ADDR_FIELD2_NS_0 _MK_ADDR_CONST(0x814) +#define DC_WINBUF_A_START_ADDR_FIELD2_NS_0_SECURE 0x0 +#define DC_WINBUF_A_START_ADDR_FIELD2_NS_0_WORD_COUNT 0x1 +#define DC_WINBUF_A_START_ADDR_FIELD2_NS_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_START_ADDR_FIELD2_NS_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_START_ADDR_FIELD2_NS_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_START_ADDR_FIELD2_NS_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_START_ADDR_FIELD2_NS_0_READ_MASK _MK_MASK_CONST(0xffffffff) +#define DC_WINBUF_A_START_ADDR_FIELD2_NS_0_WRITE_MASK _MK_MASK_CONST(0xffffffff) +#define DC_WINBUF_A_START_ADDR_FIELD2_NS_0_A_START_ADDR_FIELD2_NS_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINBUF_A_START_ADDR_FIELD2_NS_0_A_START_ADDR_FIELD2_NS_FIELD _MK_FIELD_CONST(0xffffffff, DC_WINBUF_A_START_ADDR_FIELD2_NS_0_A_START_ADDR_FIELD2_NS_SHIFT) +#define DC_WINBUF_A_START_ADDR_FIELD2_NS_0_A_START_ADDR_FIELD2_NS_RANGE 31:0 +#define DC_WINBUF_A_START_ADDR_FIELD2_NS_0_A_START_ADDR_FIELD2_NS_WOFFSET 0x0 +#define DC_WINBUF_A_START_ADDR_FIELD2_NS_0_A_START_ADDR_FIELD2_NS_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_START_ADDR_FIELD2_NS_0_A_START_ADDR_FIELD2_NS_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_START_ADDR_FIELD2_NS_0_A_START_ADDR_FIELD2_NS_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_START_ADDR_FIELD2_NS_0_A_START_ADDR_FIELD2_NS_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_WINBUF_A_START_ADDR_FIELD2_U_0 +#define DC_WINBUF_A_START_ADDR_FIELD2_U_0 _MK_ADDR_CONST(0x815) +#define DC_WINBUF_A_START_ADDR_FIELD2_U_0_SECURE 0x0 +#define DC_WINBUF_A_START_ADDR_FIELD2_U_0_WORD_COUNT 0x1 +#define DC_WINBUF_A_START_ADDR_FIELD2_U_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_START_ADDR_FIELD2_U_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_START_ADDR_FIELD2_U_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_START_ADDR_FIELD2_U_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_START_ADDR_FIELD2_U_0_READ_MASK _MK_MASK_CONST(0xffffffff) +#define DC_WINBUF_A_START_ADDR_FIELD2_U_0_WRITE_MASK _MK_MASK_CONST(0xffffffff) +#define DC_WINBUF_A_START_ADDR_FIELD2_U_0_A_START_ADDR_FIELD2_U_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINBUF_A_START_ADDR_FIELD2_U_0_A_START_ADDR_FIELD2_U_FIELD _MK_FIELD_CONST(0xffffffff, DC_WINBUF_A_START_ADDR_FIELD2_U_0_A_START_ADDR_FIELD2_U_SHIFT) +#define DC_WINBUF_A_START_ADDR_FIELD2_U_0_A_START_ADDR_FIELD2_U_RANGE 31:0 +#define DC_WINBUF_A_START_ADDR_FIELD2_U_0_A_START_ADDR_FIELD2_U_WOFFSET 0x0 +#define DC_WINBUF_A_START_ADDR_FIELD2_U_0_A_START_ADDR_FIELD2_U_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_START_ADDR_FIELD2_U_0_A_START_ADDR_FIELD2_U_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_START_ADDR_FIELD2_U_0_A_START_ADDR_FIELD2_U_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_START_ADDR_FIELD2_U_0_A_START_ADDR_FIELD2_U_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_WINBUF_A_START_ADDR_FIELD2_U_NS_0 +#define DC_WINBUF_A_START_ADDR_FIELD2_U_NS_0 _MK_ADDR_CONST(0x816) +#define DC_WINBUF_A_START_ADDR_FIELD2_U_NS_0_SECURE 0x0 +#define DC_WINBUF_A_START_ADDR_FIELD2_U_NS_0_WORD_COUNT 0x1 +#define DC_WINBUF_A_START_ADDR_FIELD2_U_NS_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_START_ADDR_FIELD2_U_NS_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_START_ADDR_FIELD2_U_NS_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_START_ADDR_FIELD2_U_NS_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_START_ADDR_FIELD2_U_NS_0_READ_MASK _MK_MASK_CONST(0xffffffff) +#define DC_WINBUF_A_START_ADDR_FIELD2_U_NS_0_WRITE_MASK _MK_MASK_CONST(0xffffffff) +#define DC_WINBUF_A_START_ADDR_FIELD2_U_NS_0_A_START_ADDR_FIELD2_U_NS_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINBUF_A_START_ADDR_FIELD2_U_NS_0_A_START_ADDR_FIELD2_U_NS_FIELD _MK_FIELD_CONST(0xffffffff, DC_WINBUF_A_START_ADDR_FIELD2_U_NS_0_A_START_ADDR_FIELD2_U_NS_SHIFT) +#define DC_WINBUF_A_START_ADDR_FIELD2_U_NS_0_A_START_ADDR_FIELD2_U_NS_RANGE 31:0 +#define DC_WINBUF_A_START_ADDR_FIELD2_U_NS_0_A_START_ADDR_FIELD2_U_NS_WOFFSET 0x0 +#define DC_WINBUF_A_START_ADDR_FIELD2_U_NS_0_A_START_ADDR_FIELD2_U_NS_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_START_ADDR_FIELD2_U_NS_0_A_START_ADDR_FIELD2_U_NS_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_START_ADDR_FIELD2_U_NS_0_A_START_ADDR_FIELD2_U_NS_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_START_ADDR_FIELD2_U_NS_0_A_START_ADDR_FIELD2_U_NS_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_WINBUF_A_START_ADDR_FIELD2_V_0 +#define DC_WINBUF_A_START_ADDR_FIELD2_V_0 _MK_ADDR_CONST(0x817) +#define DC_WINBUF_A_START_ADDR_FIELD2_V_0_SECURE 0x0 +#define DC_WINBUF_A_START_ADDR_FIELD2_V_0_WORD_COUNT 0x1 +#define DC_WINBUF_A_START_ADDR_FIELD2_V_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_START_ADDR_FIELD2_V_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_START_ADDR_FIELD2_V_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_START_ADDR_FIELD2_V_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_START_ADDR_FIELD2_V_0_READ_MASK _MK_MASK_CONST(0xffffffff) +#define DC_WINBUF_A_START_ADDR_FIELD2_V_0_WRITE_MASK _MK_MASK_CONST(0xffffffff) +#define DC_WINBUF_A_START_ADDR_FIELD2_V_0_A_START_ADDR_FIELD2_V_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINBUF_A_START_ADDR_FIELD2_V_0_A_START_ADDR_FIELD2_V_FIELD _MK_FIELD_CONST(0xffffffff, DC_WINBUF_A_START_ADDR_FIELD2_V_0_A_START_ADDR_FIELD2_V_SHIFT) +#define DC_WINBUF_A_START_ADDR_FIELD2_V_0_A_START_ADDR_FIELD2_V_RANGE 31:0 +#define DC_WINBUF_A_START_ADDR_FIELD2_V_0_A_START_ADDR_FIELD2_V_WOFFSET 0x0 +#define DC_WINBUF_A_START_ADDR_FIELD2_V_0_A_START_ADDR_FIELD2_V_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_START_ADDR_FIELD2_V_0_A_START_ADDR_FIELD2_V_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_START_ADDR_FIELD2_V_0_A_START_ADDR_FIELD2_V_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_START_ADDR_FIELD2_V_0_A_START_ADDR_FIELD2_V_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_WINBUF_A_START_ADDR_FIELD2_V_NS_0 +#define DC_WINBUF_A_START_ADDR_FIELD2_V_NS_0 _MK_ADDR_CONST(0x818) +#define DC_WINBUF_A_START_ADDR_FIELD2_V_NS_0_SECURE 0x0 +#define DC_WINBUF_A_START_ADDR_FIELD2_V_NS_0_WORD_COUNT 0x1 +#define DC_WINBUF_A_START_ADDR_FIELD2_V_NS_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_START_ADDR_FIELD2_V_NS_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_START_ADDR_FIELD2_V_NS_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_START_ADDR_FIELD2_V_NS_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_START_ADDR_FIELD2_V_NS_0_READ_MASK _MK_MASK_CONST(0xffffffff) +#define DC_WINBUF_A_START_ADDR_FIELD2_V_NS_0_WRITE_MASK _MK_MASK_CONST(0xffffffff) +#define DC_WINBUF_A_START_ADDR_FIELD2_V_NS_0_A_START_ADDR_FIELD2_V_NS_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINBUF_A_START_ADDR_FIELD2_V_NS_0_A_START_ADDR_FIELD2_V_NS_FIELD _MK_FIELD_CONST(0xffffffff, DC_WINBUF_A_START_ADDR_FIELD2_V_NS_0_A_START_ADDR_FIELD2_V_NS_SHIFT) +#define DC_WINBUF_A_START_ADDR_FIELD2_V_NS_0_A_START_ADDR_FIELD2_V_NS_RANGE 31:0 +#define DC_WINBUF_A_START_ADDR_FIELD2_V_NS_0_A_START_ADDR_FIELD2_V_NS_WOFFSET 0x0 +#define DC_WINBUF_A_START_ADDR_FIELD2_V_NS_0_A_START_ADDR_FIELD2_V_NS_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_START_ADDR_FIELD2_V_NS_0_A_START_ADDR_FIELD2_V_NS_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_START_ADDR_FIELD2_V_NS_0_A_START_ADDR_FIELD2_V_NS_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_START_ADDR_FIELD2_V_NS_0_A_START_ADDR_FIELD2_V_NS_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_WINBUF_A_START_ADDR_FIELD2_HI_0 +#define DC_WINBUF_A_START_ADDR_FIELD2_HI_0 _MK_ADDR_CONST(0x819) +#define DC_WINBUF_A_START_ADDR_FIELD2_HI_0_SECURE 0x0 +#define DC_WINBUF_A_START_ADDR_FIELD2_HI_0_WORD_COUNT 0x1 +#define DC_WINBUF_A_START_ADDR_FIELD2_HI_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_START_ADDR_FIELD2_HI_0_RESET_MASK _MK_MASK_CONST(0x3) +#define DC_WINBUF_A_START_ADDR_FIELD2_HI_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_START_ADDR_FIELD2_HI_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_START_ADDR_FIELD2_HI_0_READ_MASK _MK_MASK_CONST(0x3) +#define DC_WINBUF_A_START_ADDR_FIELD2_HI_0_WRITE_MASK _MK_MASK_CONST(0x3) +#define DC_WINBUF_A_START_ADDR_FIELD2_HI_0_A_START_ADDR_FIELD2_HI_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINBUF_A_START_ADDR_FIELD2_HI_0_A_START_ADDR_FIELD2_HI_FIELD _MK_FIELD_CONST(0x3, DC_WINBUF_A_START_ADDR_FIELD2_HI_0_A_START_ADDR_FIELD2_HI_SHIFT) +#define DC_WINBUF_A_START_ADDR_FIELD2_HI_0_A_START_ADDR_FIELD2_HI_RANGE 1:0 +#define DC_WINBUF_A_START_ADDR_FIELD2_HI_0_A_START_ADDR_FIELD2_HI_WOFFSET 0x0 +#define DC_WINBUF_A_START_ADDR_FIELD2_HI_0_A_START_ADDR_FIELD2_HI_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_START_ADDR_FIELD2_HI_0_A_START_ADDR_FIELD2_HI_DEFAULT_MASK _MK_MASK_CONST(0x3) +#define DC_WINBUF_A_START_ADDR_FIELD2_HI_0_A_START_ADDR_FIELD2_HI_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_START_ADDR_FIELD2_HI_0_A_START_ADDR_FIELD2_HI_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_WINBUF_A_START_ADDR_FIELD2_HI_NS_0 +#define DC_WINBUF_A_START_ADDR_FIELD2_HI_NS_0 _MK_ADDR_CONST(0x81a) +#define DC_WINBUF_A_START_ADDR_FIELD2_HI_NS_0_SECURE 0x0 +#define DC_WINBUF_A_START_ADDR_FIELD2_HI_NS_0_WORD_COUNT 0x1 +#define DC_WINBUF_A_START_ADDR_FIELD2_HI_NS_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_START_ADDR_FIELD2_HI_NS_0_RESET_MASK _MK_MASK_CONST(0x3) +#define DC_WINBUF_A_START_ADDR_FIELD2_HI_NS_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_START_ADDR_FIELD2_HI_NS_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_START_ADDR_FIELD2_HI_NS_0_READ_MASK _MK_MASK_CONST(0x3) +#define DC_WINBUF_A_START_ADDR_FIELD2_HI_NS_0_WRITE_MASK _MK_MASK_CONST(0x3) +#define DC_WINBUF_A_START_ADDR_FIELD2_HI_NS_0_A_START_ADDR_FIELD2_HI_NS_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINBUF_A_START_ADDR_FIELD2_HI_NS_0_A_START_ADDR_FIELD2_HI_NS_FIELD _MK_FIELD_CONST(0x3, DC_WINBUF_A_START_ADDR_FIELD2_HI_NS_0_A_START_ADDR_FIELD2_HI_NS_SHIFT) +#define DC_WINBUF_A_START_ADDR_FIELD2_HI_NS_0_A_START_ADDR_FIELD2_HI_NS_RANGE 1:0 +#define DC_WINBUF_A_START_ADDR_FIELD2_HI_NS_0_A_START_ADDR_FIELD2_HI_NS_WOFFSET 0x0 +#define DC_WINBUF_A_START_ADDR_FIELD2_HI_NS_0_A_START_ADDR_FIELD2_HI_NS_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_START_ADDR_FIELD2_HI_NS_0_A_START_ADDR_FIELD2_HI_NS_DEFAULT_MASK _MK_MASK_CONST(0x3) +#define DC_WINBUF_A_START_ADDR_FIELD2_HI_NS_0_A_START_ADDR_FIELD2_HI_NS_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_START_ADDR_FIELD2_HI_NS_0_A_START_ADDR_FIELD2_HI_NS_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_WINBUF_A_START_ADDR_FIELD2_HI_U_0 +#define DC_WINBUF_A_START_ADDR_FIELD2_HI_U_0 _MK_ADDR_CONST(0x81b) +#define DC_WINBUF_A_START_ADDR_FIELD2_HI_U_0_SECURE 0x0 +#define DC_WINBUF_A_START_ADDR_FIELD2_HI_U_0_WORD_COUNT 0x1 +#define DC_WINBUF_A_START_ADDR_FIELD2_HI_U_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_START_ADDR_FIELD2_HI_U_0_RESET_MASK _MK_MASK_CONST(0x3) +#define DC_WINBUF_A_START_ADDR_FIELD2_HI_U_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_START_ADDR_FIELD2_HI_U_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_START_ADDR_FIELD2_HI_U_0_READ_MASK _MK_MASK_CONST(0x3) +#define DC_WINBUF_A_START_ADDR_FIELD2_HI_U_0_WRITE_MASK _MK_MASK_CONST(0x3) +#define DC_WINBUF_A_START_ADDR_FIELD2_HI_U_0_A_START_ADDR_FIELD2_HI_U_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINBUF_A_START_ADDR_FIELD2_HI_U_0_A_START_ADDR_FIELD2_HI_U_FIELD _MK_FIELD_CONST(0x3, DC_WINBUF_A_START_ADDR_FIELD2_HI_U_0_A_START_ADDR_FIELD2_HI_U_SHIFT) +#define DC_WINBUF_A_START_ADDR_FIELD2_HI_U_0_A_START_ADDR_FIELD2_HI_U_RANGE 1:0 +#define DC_WINBUF_A_START_ADDR_FIELD2_HI_U_0_A_START_ADDR_FIELD2_HI_U_WOFFSET 0x0 +#define DC_WINBUF_A_START_ADDR_FIELD2_HI_U_0_A_START_ADDR_FIELD2_HI_U_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_START_ADDR_FIELD2_HI_U_0_A_START_ADDR_FIELD2_HI_U_DEFAULT_MASK _MK_MASK_CONST(0x3) +#define DC_WINBUF_A_START_ADDR_FIELD2_HI_U_0_A_START_ADDR_FIELD2_HI_U_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_START_ADDR_FIELD2_HI_U_0_A_START_ADDR_FIELD2_HI_U_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_WINBUF_A_START_ADDR_FIELD2_HI_U_NS_0 +#define DC_WINBUF_A_START_ADDR_FIELD2_HI_U_NS_0 _MK_ADDR_CONST(0x81c) +#define DC_WINBUF_A_START_ADDR_FIELD2_HI_U_NS_0_SECURE 0x0 +#define DC_WINBUF_A_START_ADDR_FIELD2_HI_U_NS_0_WORD_COUNT 0x1 +#define DC_WINBUF_A_START_ADDR_FIELD2_HI_U_NS_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_START_ADDR_FIELD2_HI_U_NS_0_RESET_MASK _MK_MASK_CONST(0x3) +#define DC_WINBUF_A_START_ADDR_FIELD2_HI_U_NS_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_START_ADDR_FIELD2_HI_U_NS_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_START_ADDR_FIELD2_HI_U_NS_0_READ_MASK _MK_MASK_CONST(0x3) +#define DC_WINBUF_A_START_ADDR_FIELD2_HI_U_NS_0_WRITE_MASK _MK_MASK_CONST(0x3) +#define DC_WINBUF_A_START_ADDR_FIELD2_HI_U_NS_0_A_START_ADDR_FIELD2_HI_U_NS_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINBUF_A_START_ADDR_FIELD2_HI_U_NS_0_A_START_ADDR_FIELD2_HI_U_NS_FIELD _MK_FIELD_CONST(0x3, DC_WINBUF_A_START_ADDR_FIELD2_HI_U_NS_0_A_START_ADDR_FIELD2_HI_U_NS_SHIFT) +#define DC_WINBUF_A_START_ADDR_FIELD2_HI_U_NS_0_A_START_ADDR_FIELD2_HI_U_NS_RANGE 1:0 +#define DC_WINBUF_A_START_ADDR_FIELD2_HI_U_NS_0_A_START_ADDR_FIELD2_HI_U_NS_WOFFSET 0x0 +#define DC_WINBUF_A_START_ADDR_FIELD2_HI_U_NS_0_A_START_ADDR_FIELD2_HI_U_NS_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_START_ADDR_FIELD2_HI_U_NS_0_A_START_ADDR_FIELD2_HI_U_NS_DEFAULT_MASK _MK_MASK_CONST(0x3) +#define DC_WINBUF_A_START_ADDR_FIELD2_HI_U_NS_0_A_START_ADDR_FIELD2_HI_U_NS_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_START_ADDR_FIELD2_HI_U_NS_0_A_START_ADDR_FIELD2_HI_U_NS_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_WINBUF_A_START_ADDR_FIELD2_HI_V_0 +#define DC_WINBUF_A_START_ADDR_FIELD2_HI_V_0 _MK_ADDR_CONST(0x81d) +#define DC_WINBUF_A_START_ADDR_FIELD2_HI_V_0_SECURE 0x0 +#define DC_WINBUF_A_START_ADDR_FIELD2_HI_V_0_WORD_COUNT 0x1 +#define DC_WINBUF_A_START_ADDR_FIELD2_HI_V_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_START_ADDR_FIELD2_HI_V_0_RESET_MASK _MK_MASK_CONST(0x3) +#define DC_WINBUF_A_START_ADDR_FIELD2_HI_V_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_START_ADDR_FIELD2_HI_V_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_START_ADDR_FIELD2_HI_V_0_READ_MASK _MK_MASK_CONST(0x3) +#define DC_WINBUF_A_START_ADDR_FIELD2_HI_V_0_WRITE_MASK _MK_MASK_CONST(0x3) +#define DC_WINBUF_A_START_ADDR_FIELD2_HI_V_0_A_START_ADDR_FIELD2_HI_V_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINBUF_A_START_ADDR_FIELD2_HI_V_0_A_START_ADDR_FIELD2_HI_V_FIELD _MK_FIELD_CONST(0x3, DC_WINBUF_A_START_ADDR_FIELD2_HI_V_0_A_START_ADDR_FIELD2_HI_V_SHIFT) +#define DC_WINBUF_A_START_ADDR_FIELD2_HI_V_0_A_START_ADDR_FIELD2_HI_V_RANGE 1:0 +#define DC_WINBUF_A_START_ADDR_FIELD2_HI_V_0_A_START_ADDR_FIELD2_HI_V_WOFFSET 0x0 +#define DC_WINBUF_A_START_ADDR_FIELD2_HI_V_0_A_START_ADDR_FIELD2_HI_V_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_START_ADDR_FIELD2_HI_V_0_A_START_ADDR_FIELD2_HI_V_DEFAULT_MASK _MK_MASK_CONST(0x3) +#define DC_WINBUF_A_START_ADDR_FIELD2_HI_V_0_A_START_ADDR_FIELD2_HI_V_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_START_ADDR_FIELD2_HI_V_0_A_START_ADDR_FIELD2_HI_V_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_WINBUF_A_START_ADDR_FIELD2_HI_V_NS_0 +#define DC_WINBUF_A_START_ADDR_FIELD2_HI_V_NS_0 _MK_ADDR_CONST(0x81e) +#define DC_WINBUF_A_START_ADDR_FIELD2_HI_V_NS_0_SECURE 0x0 +#define DC_WINBUF_A_START_ADDR_FIELD2_HI_V_NS_0_WORD_COUNT 0x1 +#define DC_WINBUF_A_START_ADDR_FIELD2_HI_V_NS_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_START_ADDR_FIELD2_HI_V_NS_0_RESET_MASK _MK_MASK_CONST(0x3) +#define DC_WINBUF_A_START_ADDR_FIELD2_HI_V_NS_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_START_ADDR_FIELD2_HI_V_NS_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_START_ADDR_FIELD2_HI_V_NS_0_READ_MASK _MK_MASK_CONST(0x3) +#define DC_WINBUF_A_START_ADDR_FIELD2_HI_V_NS_0_WRITE_MASK _MK_MASK_CONST(0x3) +#define DC_WINBUF_A_START_ADDR_FIELD2_HI_V_NS_0_A_START_ADDR_FIELD2_HI_V_NS_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINBUF_A_START_ADDR_FIELD2_HI_V_NS_0_A_START_ADDR_FIELD2_HI_V_NS_FIELD _MK_FIELD_CONST(0x3, DC_WINBUF_A_START_ADDR_FIELD2_HI_V_NS_0_A_START_ADDR_FIELD2_HI_V_NS_SHIFT) +#define DC_WINBUF_A_START_ADDR_FIELD2_HI_V_NS_0_A_START_ADDR_FIELD2_HI_V_NS_RANGE 1:0 +#define DC_WINBUF_A_START_ADDR_FIELD2_HI_V_NS_0_A_START_ADDR_FIELD2_HI_V_NS_WOFFSET 0x0 +#define DC_WINBUF_A_START_ADDR_FIELD2_HI_V_NS_0_A_START_ADDR_FIELD2_HI_V_NS_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_START_ADDR_FIELD2_HI_V_NS_0_A_START_ADDR_FIELD2_HI_V_NS_DEFAULT_MASK _MK_MASK_CONST(0x3) +#define DC_WINBUF_A_START_ADDR_FIELD2_HI_V_NS_0_A_START_ADDR_FIELD2_HI_V_NS_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_START_ADDR_FIELD2_HI_V_NS_0_A_START_ADDR_FIELD2_HI_V_NS_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_WINBUF_A_ADDR_H_OFFSET_FIELD2_0 +#define DC_WINBUF_A_ADDR_H_OFFSET_FIELD2_0 _MK_ADDR_CONST(0x81f) +#define DC_WINBUF_A_ADDR_H_OFFSET_FIELD2_0_SECURE 0x0 +#define DC_WINBUF_A_ADDR_H_OFFSET_FIELD2_0_WORD_COUNT 0x1 +#define DC_WINBUF_A_ADDR_H_OFFSET_FIELD2_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_ADDR_H_OFFSET_FIELD2_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_ADDR_H_OFFSET_FIELD2_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_ADDR_H_OFFSET_FIELD2_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_ADDR_H_OFFSET_FIELD2_0_READ_MASK _MK_MASK_CONST(0xffffffff) +#define DC_WINBUF_A_ADDR_H_OFFSET_FIELD2_0_WRITE_MASK _MK_MASK_CONST(0xffffffff) +#define DC_WINBUF_A_ADDR_H_OFFSET_FIELD2_0_A_ADDR_H_OFFSET_FIELD2_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINBUF_A_ADDR_H_OFFSET_FIELD2_0_A_ADDR_H_OFFSET_FIELD2_FIELD _MK_FIELD_CONST(0xffffffff, DC_WINBUF_A_ADDR_H_OFFSET_FIELD2_0_A_ADDR_H_OFFSET_FIELD2_SHIFT) +#define DC_WINBUF_A_ADDR_H_OFFSET_FIELD2_0_A_ADDR_H_OFFSET_FIELD2_RANGE 31:0 +#define DC_WINBUF_A_ADDR_H_OFFSET_FIELD2_0_A_ADDR_H_OFFSET_FIELD2_WOFFSET 0x0 +#define DC_WINBUF_A_ADDR_H_OFFSET_FIELD2_0_A_ADDR_H_OFFSET_FIELD2_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_ADDR_H_OFFSET_FIELD2_0_A_ADDR_H_OFFSET_FIELD2_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_ADDR_H_OFFSET_FIELD2_0_A_ADDR_H_OFFSET_FIELD2_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_ADDR_H_OFFSET_FIELD2_0_A_ADDR_H_OFFSET_FIELD2_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_WINBUF_A_ADDR_H_OFFSET_FIELD2_NS_0 +#define DC_WINBUF_A_ADDR_H_OFFSET_FIELD2_NS_0 _MK_ADDR_CONST(0x820) +#define DC_WINBUF_A_ADDR_H_OFFSET_FIELD2_NS_0_SECURE 0x0 +#define DC_WINBUF_A_ADDR_H_OFFSET_FIELD2_NS_0_WORD_COUNT 0x1 +#define DC_WINBUF_A_ADDR_H_OFFSET_FIELD2_NS_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_ADDR_H_OFFSET_FIELD2_NS_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_ADDR_H_OFFSET_FIELD2_NS_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_ADDR_H_OFFSET_FIELD2_NS_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_ADDR_H_OFFSET_FIELD2_NS_0_READ_MASK _MK_MASK_CONST(0xffffffff) +#define DC_WINBUF_A_ADDR_H_OFFSET_FIELD2_NS_0_WRITE_MASK _MK_MASK_CONST(0xffffffff) +#define DC_WINBUF_A_ADDR_H_OFFSET_FIELD2_NS_0_A_ADDR_H_OFFSET_FIELD2_NS_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINBUF_A_ADDR_H_OFFSET_FIELD2_NS_0_A_ADDR_H_OFFSET_FIELD2_NS_FIELD _MK_FIELD_CONST(0xffffffff, DC_WINBUF_A_ADDR_H_OFFSET_FIELD2_NS_0_A_ADDR_H_OFFSET_FIELD2_NS_SHIFT) +#define DC_WINBUF_A_ADDR_H_OFFSET_FIELD2_NS_0_A_ADDR_H_OFFSET_FIELD2_NS_RANGE 31:0 +#define DC_WINBUF_A_ADDR_H_OFFSET_FIELD2_NS_0_A_ADDR_H_OFFSET_FIELD2_NS_WOFFSET 0x0 +#define DC_WINBUF_A_ADDR_H_OFFSET_FIELD2_NS_0_A_ADDR_H_OFFSET_FIELD2_NS_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_ADDR_H_OFFSET_FIELD2_NS_0_A_ADDR_H_OFFSET_FIELD2_NS_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_ADDR_H_OFFSET_FIELD2_NS_0_A_ADDR_H_OFFSET_FIELD2_NS_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_ADDR_H_OFFSET_FIELD2_NS_0_A_ADDR_H_OFFSET_FIELD2_NS_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_WINBUF_A_ADDR_V_OFFSET_FIELD2_0 +#define DC_WINBUF_A_ADDR_V_OFFSET_FIELD2_0 _MK_ADDR_CONST(0x821) +#define DC_WINBUF_A_ADDR_V_OFFSET_FIELD2_0_SECURE 0x0 +#define DC_WINBUF_A_ADDR_V_OFFSET_FIELD2_0_WORD_COUNT 0x1 +#define DC_WINBUF_A_ADDR_V_OFFSET_FIELD2_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_ADDR_V_OFFSET_FIELD2_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_ADDR_V_OFFSET_FIELD2_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_ADDR_V_OFFSET_FIELD2_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_ADDR_V_OFFSET_FIELD2_0_READ_MASK _MK_MASK_CONST(0xffffffff) +#define DC_WINBUF_A_ADDR_V_OFFSET_FIELD2_0_WRITE_MASK _MK_MASK_CONST(0xffffffff) +#define DC_WINBUF_A_ADDR_V_OFFSET_FIELD2_0_A_ADDR_V_OFFSET_FIELD2_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINBUF_A_ADDR_V_OFFSET_FIELD2_0_A_ADDR_V_OFFSET_FIELD2_FIELD _MK_FIELD_CONST(0xffffffff, DC_WINBUF_A_ADDR_V_OFFSET_FIELD2_0_A_ADDR_V_OFFSET_FIELD2_SHIFT) +#define DC_WINBUF_A_ADDR_V_OFFSET_FIELD2_0_A_ADDR_V_OFFSET_FIELD2_RANGE 31:0 +#define DC_WINBUF_A_ADDR_V_OFFSET_FIELD2_0_A_ADDR_V_OFFSET_FIELD2_WOFFSET 0x0 +#define DC_WINBUF_A_ADDR_V_OFFSET_FIELD2_0_A_ADDR_V_OFFSET_FIELD2_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_ADDR_V_OFFSET_FIELD2_0_A_ADDR_V_OFFSET_FIELD2_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_ADDR_V_OFFSET_FIELD2_0_A_ADDR_V_OFFSET_FIELD2_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_ADDR_V_OFFSET_FIELD2_0_A_ADDR_V_OFFSET_FIELD2_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_WINBUF_A_ADDR_V_OFFSET_FIELD2_NS_0 +#define DC_WINBUF_A_ADDR_V_OFFSET_FIELD2_NS_0 _MK_ADDR_CONST(0x822) +#define DC_WINBUF_A_ADDR_V_OFFSET_FIELD2_NS_0_SECURE 0x0 +#define DC_WINBUF_A_ADDR_V_OFFSET_FIELD2_NS_0_WORD_COUNT 0x1 +#define DC_WINBUF_A_ADDR_V_OFFSET_FIELD2_NS_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_ADDR_V_OFFSET_FIELD2_NS_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_ADDR_V_OFFSET_FIELD2_NS_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_ADDR_V_OFFSET_FIELD2_NS_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_ADDR_V_OFFSET_FIELD2_NS_0_READ_MASK _MK_MASK_CONST(0xffffffff) +#define DC_WINBUF_A_ADDR_V_OFFSET_FIELD2_NS_0_WRITE_MASK _MK_MASK_CONST(0xffffffff) +#define DC_WINBUF_A_ADDR_V_OFFSET_FIELD2_NS_0_A_ADDR_V_OFFSET_FIELD2_NS_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINBUF_A_ADDR_V_OFFSET_FIELD2_NS_0_A_ADDR_V_OFFSET_FIELD2_NS_FIELD _MK_FIELD_CONST(0xffffffff, DC_WINBUF_A_ADDR_V_OFFSET_FIELD2_NS_0_A_ADDR_V_OFFSET_FIELD2_NS_SHIFT) +#define DC_WINBUF_A_ADDR_V_OFFSET_FIELD2_NS_0_A_ADDR_V_OFFSET_FIELD2_NS_RANGE 31:0 +#define DC_WINBUF_A_ADDR_V_OFFSET_FIELD2_NS_0_A_ADDR_V_OFFSET_FIELD2_NS_WOFFSET 0x0 +#define DC_WINBUF_A_ADDR_V_OFFSET_FIELD2_NS_0_A_ADDR_V_OFFSET_FIELD2_NS_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_ADDR_V_OFFSET_FIELD2_NS_0_A_ADDR_V_OFFSET_FIELD2_NS_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_ADDR_V_OFFSET_FIELD2_NS_0_A_ADDR_V_OFFSET_FIELD2_NS_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_ADDR_V_OFFSET_FIELD2_NS_0_A_ADDR_V_OFFSET_FIELD2_NS_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Reserved address 2083 [0x823] + +// Register DC_WINBUF_A_UFLOW_CTRL_0 +#define DC_WINBUF_A_UFLOW_CTRL_0 _MK_ADDR_CONST(0x824) +#define DC_WINBUF_A_UFLOW_CTRL_0_SECURE 0x0 +#define DC_WINBUF_A_UFLOW_CTRL_0_WORD_COUNT 0x1 +#define DC_WINBUF_A_UFLOW_CTRL_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_UFLOW_CTRL_0_RESET_MASK _MK_MASK_CONST(0x1) +#define DC_WINBUF_A_UFLOW_CTRL_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_UFLOW_CTRL_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_UFLOW_CTRL_0_READ_MASK _MK_MASK_CONST(0x1) +#define DC_WINBUF_A_UFLOW_CTRL_0_WRITE_MASK _MK_MASK_CONST(0x1) +#define DC_WINBUF_A_UFLOW_CTRL_0_A_UFLOW_CTRL_DBG_MODE_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINBUF_A_UFLOW_CTRL_0_A_UFLOW_CTRL_DBG_MODE_FIELD _MK_FIELD_CONST(0x1, DC_WINBUF_A_UFLOW_CTRL_0_A_UFLOW_CTRL_DBG_MODE_SHIFT) +#define DC_WINBUF_A_UFLOW_CTRL_0_A_UFLOW_CTRL_DBG_MODE_RANGE 0:0 +#define DC_WINBUF_A_UFLOW_CTRL_0_A_UFLOW_CTRL_DBG_MODE_WOFFSET 0x0 +#define DC_WINBUF_A_UFLOW_CTRL_0_A_UFLOW_CTRL_DBG_MODE_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_UFLOW_CTRL_0_A_UFLOW_CTRL_DBG_MODE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_WINBUF_A_UFLOW_CTRL_0_A_UFLOW_CTRL_DBG_MODE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_UFLOW_CTRL_0_A_UFLOW_CTRL_DBG_MODE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_UFLOW_CTRL_0_A_UFLOW_CTRL_DBG_MODE_DISABLE _MK_ENUM_CONST(0) +#define DC_WINBUF_A_UFLOW_CTRL_0_A_UFLOW_CTRL_DBG_MODE_ENABLE _MK_ENUM_CONST(1) + + +// Register DC_WINBUF_A_UFLOW_DBG_PIXEL_0 +#define DC_WINBUF_A_UFLOW_DBG_PIXEL_0 _MK_ADDR_CONST(0x825) +#define DC_WINBUF_A_UFLOW_DBG_PIXEL_0_SECURE 0x0 +#define DC_WINBUF_A_UFLOW_DBG_PIXEL_0_WORD_COUNT 0x1 +#define DC_WINBUF_A_UFLOW_DBG_PIXEL_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_UFLOW_DBG_PIXEL_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_UFLOW_DBG_PIXEL_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_UFLOW_DBG_PIXEL_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_UFLOW_DBG_PIXEL_0_READ_MASK _MK_MASK_CONST(0xffffffff) +#define DC_WINBUF_A_UFLOW_DBG_PIXEL_0_WRITE_MASK _MK_MASK_CONST(0xffffffff) +#define DC_WINBUF_A_UFLOW_DBG_PIXEL_0_A_UFLOW_DBG_PIXEL_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINBUF_A_UFLOW_DBG_PIXEL_0_A_UFLOW_DBG_PIXEL_FIELD _MK_FIELD_CONST(0xffffffff, DC_WINBUF_A_UFLOW_DBG_PIXEL_0_A_UFLOW_DBG_PIXEL_SHIFT) +#define DC_WINBUF_A_UFLOW_DBG_PIXEL_0_A_UFLOW_DBG_PIXEL_RANGE 31:0 +#define DC_WINBUF_A_UFLOW_DBG_PIXEL_0_A_UFLOW_DBG_PIXEL_WOFFSET 0x0 +#define DC_WINBUF_A_UFLOW_DBG_PIXEL_0_A_UFLOW_DBG_PIXEL_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_UFLOW_DBG_PIXEL_0_A_UFLOW_DBG_PIXEL_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_UFLOW_DBG_PIXEL_0_A_UFLOW_DBG_PIXEL_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_UFLOW_DBG_PIXEL_0_A_UFLOW_DBG_PIXEL_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_WINBUF_A_UFLOW_THRESHOLD_0 +#define DC_WINBUF_A_UFLOW_THRESHOLD_0 _MK_ADDR_CONST(0x826) +#define DC_WINBUF_A_UFLOW_THRESHOLD_0_SECURE 0x0 +#define DC_WINBUF_A_UFLOW_THRESHOLD_0_WORD_COUNT 0x1 +#define DC_WINBUF_A_UFLOW_THRESHOLD_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_UFLOW_THRESHOLD_0_RESET_MASK _MK_MASK_CONST(0x1fff) +#define DC_WINBUF_A_UFLOW_THRESHOLD_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_UFLOW_THRESHOLD_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_UFLOW_THRESHOLD_0_READ_MASK _MK_MASK_CONST(0x1fff) +#define DC_WINBUF_A_UFLOW_THRESHOLD_0_WRITE_MASK _MK_MASK_CONST(0x1fff) +#define DC_WINBUF_A_UFLOW_THRESHOLD_0_A_UFLOW_THRESHOLD_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINBUF_A_UFLOW_THRESHOLD_0_A_UFLOW_THRESHOLD_FIELD _MK_FIELD_CONST(0x1fff, DC_WINBUF_A_UFLOW_THRESHOLD_0_A_UFLOW_THRESHOLD_SHIFT) +#define DC_WINBUF_A_UFLOW_THRESHOLD_0_A_UFLOW_THRESHOLD_RANGE 12:0 +#define DC_WINBUF_A_UFLOW_THRESHOLD_0_A_UFLOW_THRESHOLD_WOFFSET 0x0 +#define DC_WINBUF_A_UFLOW_THRESHOLD_0_A_UFLOW_THRESHOLD_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_UFLOW_THRESHOLD_0_A_UFLOW_THRESHOLD_DEFAULT_MASK _MK_MASK_CONST(0x1fff) +#define DC_WINBUF_A_UFLOW_THRESHOLD_0_A_UFLOW_THRESHOLD_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_UFLOW_THRESHOLD_0_A_UFLOW_THRESHOLD_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_WINBUF_A_SPOOL_UP_0 +#define DC_WINBUF_A_SPOOL_UP_0 _MK_ADDR_CONST(0x827) +#define DC_WINBUF_A_SPOOL_UP_0_SECURE 0x0 +#define DC_WINBUF_A_SPOOL_UP_0_WORD_COUNT 0x1 +#define DC_WINBUF_A_SPOOL_UP_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_SPOOL_UP_0_RESET_MASK _MK_MASK_CONST(0x3) +#define DC_WINBUF_A_SPOOL_UP_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_SPOOL_UP_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_SPOOL_UP_0_READ_MASK _MK_MASK_CONST(0x1fff0003) +#define DC_WINBUF_A_SPOOL_UP_0_WRITE_MASK _MK_MASK_CONST(0x1fff0003) +#define DC_WINBUF_A_SPOOL_UP_0_A_SPOOL_UP_CTRL_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINBUF_A_SPOOL_UP_0_A_SPOOL_UP_CTRL_FIELD _MK_FIELD_CONST(0x1, DC_WINBUF_A_SPOOL_UP_0_A_SPOOL_UP_CTRL_SHIFT) +#define DC_WINBUF_A_SPOOL_UP_0_A_SPOOL_UP_CTRL_RANGE 0:0 +#define DC_WINBUF_A_SPOOL_UP_0_A_SPOOL_UP_CTRL_WOFFSET 0x0 +#define DC_WINBUF_A_SPOOL_UP_0_A_SPOOL_UP_CTRL_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_SPOOL_UP_0_A_SPOOL_UP_CTRL_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_WINBUF_A_SPOOL_UP_0_A_SPOOL_UP_CTRL_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_SPOOL_UP_0_A_SPOOL_UP_CTRL_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_SPOOL_UP_0_A_SPOOL_UP_CTRL_MAX _MK_ENUM_CONST(0) +#define DC_WINBUF_A_SPOOL_UP_0_A_SPOOL_UP_CTRL_PROGRAMMABLE _MK_ENUM_CONST(1) + +#define DC_WINBUF_A_SPOOL_UP_0_A_SPOOL_UP_EDGE_SHIFT _MK_SHIFT_CONST(1) +#define DC_WINBUF_A_SPOOL_UP_0_A_SPOOL_UP_EDGE_FIELD _MK_FIELD_CONST(0x1, DC_WINBUF_A_SPOOL_UP_0_A_SPOOL_UP_EDGE_SHIFT) +#define DC_WINBUF_A_SPOOL_UP_0_A_SPOOL_UP_EDGE_RANGE 1:1 +#define DC_WINBUF_A_SPOOL_UP_0_A_SPOOL_UP_EDGE_WOFFSET 0x0 +#define DC_WINBUF_A_SPOOL_UP_0_A_SPOOL_UP_EDGE_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_SPOOL_UP_0_A_SPOOL_UP_EDGE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_WINBUF_A_SPOOL_UP_0_A_SPOOL_UP_EDGE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_SPOOL_UP_0_A_SPOOL_UP_EDGE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_SPOOL_UP_0_A_SPOOL_UP_EDGE_NEGEDGE _MK_ENUM_CONST(0) +#define DC_WINBUF_A_SPOOL_UP_0_A_SPOOL_UP_EDGE_POSEDGE _MK_ENUM_CONST(1) + +#define DC_WINBUF_A_SPOOL_UP_0_A_SPOOL_UP_DURATION_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINBUF_A_SPOOL_UP_0_A_SPOOL_UP_DURATION_FIELD _MK_FIELD_CONST(0x1fff, DC_WINBUF_A_SPOOL_UP_0_A_SPOOL_UP_DURATION_SHIFT) +#define DC_WINBUF_A_SPOOL_UP_0_A_SPOOL_UP_DURATION_RANGE 28:16 +#define DC_WINBUF_A_SPOOL_UP_0_A_SPOOL_UP_DURATION_WOFFSET 0x0 +#define DC_WINBUF_A_SPOOL_UP_0_A_SPOOL_UP_DURATION_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_SPOOL_UP_0_A_SPOOL_UP_DURATION_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_SPOOL_UP_0_A_SPOOL_UP_DURATION_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_SPOOL_UP_0_A_SPOOL_UP_DURATION_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_WINBUF_A_SCALEFACTOR_THRESHOLD_0 +#define DC_WINBUF_A_SCALEFACTOR_THRESHOLD_0 _MK_ADDR_CONST(0x828) +#define DC_WINBUF_A_SCALEFACTOR_THRESHOLD_0_SECURE 0x0 +#define DC_WINBUF_A_SCALEFACTOR_THRESHOLD_0_WORD_COUNT 0x1 +#define DC_WINBUF_A_SCALEFACTOR_THRESHOLD_0_RESET_VAL _MK_MASK_CONST(0xffffffff) +#define DC_WINBUF_A_SCALEFACTOR_THRESHOLD_0_RESET_MASK _MK_MASK_CONST(0xffffffff) +#define DC_WINBUF_A_SCALEFACTOR_THRESHOLD_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_SCALEFACTOR_THRESHOLD_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_SCALEFACTOR_THRESHOLD_0_READ_MASK _MK_MASK_CONST(0xffffffff) +#define DC_WINBUF_A_SCALEFACTOR_THRESHOLD_0_WRITE_MASK _MK_MASK_CONST(0xffffffff) +#define DC_WINBUF_A_SCALEFACTOR_THRESHOLD_0_A_SF_HWM_THRESHOLD_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINBUF_A_SCALEFACTOR_THRESHOLD_0_A_SF_HWM_THRESHOLD_FIELD _MK_FIELD_CONST(0xffff, DC_WINBUF_A_SCALEFACTOR_THRESHOLD_0_A_SF_HWM_THRESHOLD_SHIFT) +#define DC_WINBUF_A_SCALEFACTOR_THRESHOLD_0_A_SF_HWM_THRESHOLD_RANGE 15:0 +#define DC_WINBUF_A_SCALEFACTOR_THRESHOLD_0_A_SF_HWM_THRESHOLD_WOFFSET 0x0 +#define DC_WINBUF_A_SCALEFACTOR_THRESHOLD_0_A_SF_HWM_THRESHOLD_DEFAULT _MK_MASK_CONST(0xffff) +#define DC_WINBUF_A_SCALEFACTOR_THRESHOLD_0_A_SF_HWM_THRESHOLD_DEFAULT_MASK _MK_MASK_CONST(0xffff) +#define DC_WINBUF_A_SCALEFACTOR_THRESHOLD_0_A_SF_HWM_THRESHOLD_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_SCALEFACTOR_THRESHOLD_0_A_SF_HWM_THRESHOLD_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINBUF_A_SCALEFACTOR_THRESHOLD_0_A_SF_LWM_THRESHOLD_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINBUF_A_SCALEFACTOR_THRESHOLD_0_A_SF_LWM_THRESHOLD_FIELD _MK_FIELD_CONST(0xffff, DC_WINBUF_A_SCALEFACTOR_THRESHOLD_0_A_SF_LWM_THRESHOLD_SHIFT) +#define DC_WINBUF_A_SCALEFACTOR_THRESHOLD_0_A_SF_LWM_THRESHOLD_RANGE 31:16 +#define DC_WINBUF_A_SCALEFACTOR_THRESHOLD_0_A_SF_LWM_THRESHOLD_WOFFSET 0x0 +#define DC_WINBUF_A_SCALEFACTOR_THRESHOLD_0_A_SF_LWM_THRESHOLD_DEFAULT _MK_MASK_CONST(0xffff) +#define DC_WINBUF_A_SCALEFACTOR_THRESHOLD_0_A_SF_LWM_THRESHOLD_DEFAULT_MASK _MK_MASK_CONST(0xffff) +#define DC_WINBUF_A_SCALEFACTOR_THRESHOLD_0_A_SF_LWM_THRESHOLD_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_SCALEFACTOR_THRESHOLD_0_A_SF_LWM_THRESHOLD_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_WINBUF_A_LATENCY_THRESHOLD_0 +#define DC_WINBUF_A_LATENCY_THRESHOLD_0 _MK_ADDR_CONST(0x829) +#define DC_WINBUF_A_LATENCY_THRESHOLD_0_SECURE 0x0 +#define DC_WINBUF_A_LATENCY_THRESHOLD_0_WORD_COUNT 0x1 +#define DC_WINBUF_A_LATENCY_THRESHOLD_0_RESET_VAL _MK_MASK_CONST(0xffff) +#define DC_WINBUF_A_LATENCY_THRESHOLD_0_RESET_MASK _MK_MASK_CONST(0xdfffffff) +#define DC_WINBUF_A_LATENCY_THRESHOLD_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_LATENCY_THRESHOLD_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_LATENCY_THRESHOLD_0_READ_MASK _MK_MASK_CONST(0xdfffffff) +#define DC_WINBUF_A_LATENCY_THRESHOLD_0_WRITE_MASK _MK_MASK_CONST(0xdfffffff) +#define DC_WINBUF_A_LATENCY_THRESHOLD_0_A_RDY4LATENCY_THRESHOLD_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINBUF_A_LATENCY_THRESHOLD_0_A_RDY4LATENCY_THRESHOLD_FIELD _MK_FIELD_CONST(0xffff, DC_WINBUF_A_LATENCY_THRESHOLD_0_A_RDY4LATENCY_THRESHOLD_SHIFT) +#define DC_WINBUF_A_LATENCY_THRESHOLD_0_A_RDY4LATENCY_THRESHOLD_RANGE 15:0 +#define DC_WINBUF_A_LATENCY_THRESHOLD_0_A_RDY4LATENCY_THRESHOLD_WOFFSET 0x0 +#define DC_WINBUF_A_LATENCY_THRESHOLD_0_A_RDY4LATENCY_THRESHOLD_DEFAULT _MK_MASK_CONST(0xffff) +#define DC_WINBUF_A_LATENCY_THRESHOLD_0_A_RDY4LATENCY_THRESHOLD_DEFAULT_MASK _MK_MASK_CONST(0xffff) +#define DC_WINBUF_A_LATENCY_THRESHOLD_0_A_RDY4LATENCY_THRESHOLD_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_LATENCY_THRESHOLD_0_A_RDY4LATENCY_THRESHOLD_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINBUF_A_LATENCY_THRESHOLD_0_A_RDY4LATENCY_SPOOLUP_DURATION_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINBUF_A_LATENCY_THRESHOLD_0_A_RDY4LATENCY_SPOOLUP_DURATION_FIELD _MK_FIELD_CONST(0x1fff, DC_WINBUF_A_LATENCY_THRESHOLD_0_A_RDY4LATENCY_SPOOLUP_DURATION_SHIFT) +#define DC_WINBUF_A_LATENCY_THRESHOLD_0_A_RDY4LATENCY_SPOOLUP_DURATION_RANGE 28:16 +#define DC_WINBUF_A_LATENCY_THRESHOLD_0_A_RDY4LATENCY_SPOOLUP_DURATION_WOFFSET 0x0 +#define DC_WINBUF_A_LATENCY_THRESHOLD_0_A_RDY4LATENCY_SPOOLUP_DURATION_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_LATENCY_THRESHOLD_0_A_RDY4LATENCY_SPOOLUP_DURATION_DEFAULT_MASK _MK_MASK_CONST(0x1fff) +#define DC_WINBUF_A_LATENCY_THRESHOLD_0_A_RDY4LATENCY_SPOOLUP_DURATION_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_LATENCY_THRESHOLD_0_A_RDY4LATENCY_SPOOLUP_DURATION_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINBUF_A_LATENCY_THRESHOLD_0_A_RDY4LATENCY_SPOOLUP_CTRL_SHIFT _MK_SHIFT_CONST(30) +#define DC_WINBUF_A_LATENCY_THRESHOLD_0_A_RDY4LATENCY_SPOOLUP_CTRL_FIELD _MK_FIELD_CONST(0x1, DC_WINBUF_A_LATENCY_THRESHOLD_0_A_RDY4LATENCY_SPOOLUP_CTRL_SHIFT) +#define DC_WINBUF_A_LATENCY_THRESHOLD_0_A_RDY4LATENCY_SPOOLUP_CTRL_RANGE 30:30 +#define DC_WINBUF_A_LATENCY_THRESHOLD_0_A_RDY4LATENCY_SPOOLUP_CTRL_WOFFSET 0x0 +#define DC_WINBUF_A_LATENCY_THRESHOLD_0_A_RDY4LATENCY_SPOOLUP_CTRL_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_LATENCY_THRESHOLD_0_A_RDY4LATENCY_SPOOLUP_CTRL_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_WINBUF_A_LATENCY_THRESHOLD_0_A_RDY4LATENCY_SPOOLUP_CTRL_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_LATENCY_THRESHOLD_0_A_RDY4LATENCY_SPOOLUP_CTRL_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_LATENCY_THRESHOLD_0_A_RDY4LATENCY_SPOOLUP_CTRL_INIT_ENUM DISALLOW +#define DC_WINBUF_A_LATENCY_THRESHOLD_0_A_RDY4LATENCY_SPOOLUP_CTRL_DISALLOW _MK_ENUM_CONST(0) +#define DC_WINBUF_A_LATENCY_THRESHOLD_0_A_RDY4LATENCY_SPOOLUP_CTRL_ALLOW _MK_ENUM_CONST(1) + +#define DC_WINBUF_A_LATENCY_THRESHOLD_0_A_RDY4LATENCY_THRESHOLD_ENABLE_SHIFT _MK_SHIFT_CONST(31) +#define DC_WINBUF_A_LATENCY_THRESHOLD_0_A_RDY4LATENCY_THRESHOLD_ENABLE_FIELD _MK_FIELD_CONST(0x1, DC_WINBUF_A_LATENCY_THRESHOLD_0_A_RDY4LATENCY_THRESHOLD_ENABLE_SHIFT) +#define DC_WINBUF_A_LATENCY_THRESHOLD_0_A_RDY4LATENCY_THRESHOLD_ENABLE_RANGE 31:31 +#define DC_WINBUF_A_LATENCY_THRESHOLD_0_A_RDY4LATENCY_THRESHOLD_ENABLE_WOFFSET 0x0 +#define DC_WINBUF_A_LATENCY_THRESHOLD_0_A_RDY4LATENCY_THRESHOLD_ENABLE_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_LATENCY_THRESHOLD_0_A_RDY4LATENCY_THRESHOLD_ENABLE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_WINBUF_A_LATENCY_THRESHOLD_0_A_RDY4LATENCY_THRESHOLD_ENABLE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_LATENCY_THRESHOLD_0_A_RDY4LATENCY_THRESHOLD_ENABLE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_LATENCY_THRESHOLD_0_A_RDY4LATENCY_THRESHOLD_ENABLE_INIT_ENUM DISABLE +#define DC_WINBUF_A_LATENCY_THRESHOLD_0_A_RDY4LATENCY_THRESHOLD_ENABLE_DISABLE _MK_ENUM_CONST(0) +#define DC_WINBUF_A_LATENCY_THRESHOLD_0_A_RDY4LATENCY_THRESHOLD_ENABLE_ENABLE _MK_ENUM_CONST(1) + + +// Register DC_WINBUF_A_MEMFETCH_DEBUG_STATUS_0 +#define DC_WINBUF_A_MEMFETCH_DEBUG_STATUS_0 _MK_ADDR_CONST(0x82a) +#define DC_WINBUF_A_MEMFETCH_DEBUG_STATUS_0_SECURE 0x0 +#define DC_WINBUF_A_MEMFETCH_DEBUG_STATUS_0_WORD_COUNT 0x1 +#define DC_WINBUF_A_MEMFETCH_DEBUG_STATUS_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_MEMFETCH_DEBUG_STATUS_0_RESET_MASK _MK_MASK_CONST(0x1ffff) +#define DC_WINBUF_A_MEMFETCH_DEBUG_STATUS_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_MEMFETCH_DEBUG_STATUS_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_MEMFETCH_DEBUG_STATUS_0_READ_MASK _MK_MASK_CONST(0x1ffff) +#define DC_WINBUF_A_MEMFETCH_DEBUG_STATUS_0_WRITE_MASK _MK_MASK_CONST(0x1ffff) +#define DC_WINBUF_A_MEMFETCH_DEBUG_STATUS_0_B_UNDERFLOW_LINE0_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINBUF_A_MEMFETCH_DEBUG_STATUS_0_B_UNDERFLOW_LINE0_FIELD _MK_FIELD_CONST(0x1, DC_WINBUF_A_MEMFETCH_DEBUG_STATUS_0_B_UNDERFLOW_LINE0_SHIFT) +#define DC_WINBUF_A_MEMFETCH_DEBUG_STATUS_0_B_UNDERFLOW_LINE0_RANGE 0:0 +#define DC_WINBUF_A_MEMFETCH_DEBUG_STATUS_0_B_UNDERFLOW_LINE0_WOFFSET 0x0 +#define DC_WINBUF_A_MEMFETCH_DEBUG_STATUS_0_B_UNDERFLOW_LINE0_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_MEMFETCH_DEBUG_STATUS_0_B_UNDERFLOW_LINE0_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_WINBUF_A_MEMFETCH_DEBUG_STATUS_0_B_UNDERFLOW_LINE0_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_MEMFETCH_DEBUG_STATUS_0_B_UNDERFLOW_LINE0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINBUF_A_MEMFETCH_DEBUG_STATUS_0_B_UNDERFLOW_LINE1_SHIFT _MK_SHIFT_CONST(1) +#define DC_WINBUF_A_MEMFETCH_DEBUG_STATUS_0_B_UNDERFLOW_LINE1_FIELD _MK_FIELD_CONST(0x1, DC_WINBUF_A_MEMFETCH_DEBUG_STATUS_0_B_UNDERFLOW_LINE1_SHIFT) +#define DC_WINBUF_A_MEMFETCH_DEBUG_STATUS_0_B_UNDERFLOW_LINE1_RANGE 1:1 +#define DC_WINBUF_A_MEMFETCH_DEBUG_STATUS_0_B_UNDERFLOW_LINE1_WOFFSET 0x0 +#define DC_WINBUF_A_MEMFETCH_DEBUG_STATUS_0_B_UNDERFLOW_LINE1_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_MEMFETCH_DEBUG_STATUS_0_B_UNDERFLOW_LINE1_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_WINBUF_A_MEMFETCH_DEBUG_STATUS_0_B_UNDERFLOW_LINE1_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_MEMFETCH_DEBUG_STATUS_0_B_UNDERFLOW_LINE1_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINBUF_A_MEMFETCH_DEBUG_STATUS_0_B_POOL_NOT_EMPTY_SHIFT _MK_SHIFT_CONST(2) +#define DC_WINBUF_A_MEMFETCH_DEBUG_STATUS_0_B_POOL_NOT_EMPTY_FIELD _MK_FIELD_CONST(0x1, DC_WINBUF_A_MEMFETCH_DEBUG_STATUS_0_B_POOL_NOT_EMPTY_SHIFT) +#define DC_WINBUF_A_MEMFETCH_DEBUG_STATUS_0_B_POOL_NOT_EMPTY_RANGE 2:2 +#define DC_WINBUF_A_MEMFETCH_DEBUG_STATUS_0_B_POOL_NOT_EMPTY_WOFFSET 0x0 +#define DC_WINBUF_A_MEMFETCH_DEBUG_STATUS_0_B_POOL_NOT_EMPTY_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_MEMFETCH_DEBUG_STATUS_0_B_POOL_NOT_EMPTY_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_WINBUF_A_MEMFETCH_DEBUG_STATUS_0_B_POOL_NOT_EMPTY_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_MEMFETCH_DEBUG_STATUS_0_B_POOL_NOT_EMPTY_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINBUF_A_MEMFETCH_DEBUG_STATUS_0_B_DP_POOL_AVAIL_SHIFT _MK_SHIFT_CONST(3) +#define DC_WINBUF_A_MEMFETCH_DEBUG_STATUS_0_B_DP_POOL_AVAIL_FIELD _MK_FIELD_CONST(0x1, DC_WINBUF_A_MEMFETCH_DEBUG_STATUS_0_B_DP_POOL_AVAIL_SHIFT) +#define DC_WINBUF_A_MEMFETCH_DEBUG_STATUS_0_B_DP_POOL_AVAIL_RANGE 3:3 +#define DC_WINBUF_A_MEMFETCH_DEBUG_STATUS_0_B_DP_POOL_AVAIL_WOFFSET 0x0 +#define DC_WINBUF_A_MEMFETCH_DEBUG_STATUS_0_B_DP_POOL_AVAIL_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_MEMFETCH_DEBUG_STATUS_0_B_DP_POOL_AVAIL_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_WINBUF_A_MEMFETCH_DEBUG_STATUS_0_B_DP_POOL_AVAIL_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_MEMFETCH_DEBUG_STATUS_0_B_DP_POOL_AVAIL_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINBUF_A_MEMFETCH_DEBUG_STATUS_0_B_Y_SSM_NON_IDLE_SHIFT _MK_SHIFT_CONST(4) +#define DC_WINBUF_A_MEMFETCH_DEBUG_STATUS_0_B_Y_SSM_NON_IDLE_FIELD _MK_FIELD_CONST(0x1, DC_WINBUF_A_MEMFETCH_DEBUG_STATUS_0_B_Y_SSM_NON_IDLE_SHIFT) +#define DC_WINBUF_A_MEMFETCH_DEBUG_STATUS_0_B_Y_SSM_NON_IDLE_RANGE 4:4 +#define DC_WINBUF_A_MEMFETCH_DEBUG_STATUS_0_B_Y_SSM_NON_IDLE_WOFFSET 0x0 +#define DC_WINBUF_A_MEMFETCH_DEBUG_STATUS_0_B_Y_SSM_NON_IDLE_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_MEMFETCH_DEBUG_STATUS_0_B_Y_SSM_NON_IDLE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_WINBUF_A_MEMFETCH_DEBUG_STATUS_0_B_Y_SSM_NON_IDLE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_MEMFETCH_DEBUG_STATUS_0_B_Y_SSM_NON_IDLE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINBUF_A_MEMFETCH_DEBUG_STATUS_0_B_U_SSM_NON_IDLE_SHIFT _MK_SHIFT_CONST(5) +#define DC_WINBUF_A_MEMFETCH_DEBUG_STATUS_0_B_U_SSM_NON_IDLE_FIELD _MK_FIELD_CONST(0x1, DC_WINBUF_A_MEMFETCH_DEBUG_STATUS_0_B_U_SSM_NON_IDLE_SHIFT) +#define DC_WINBUF_A_MEMFETCH_DEBUG_STATUS_0_B_U_SSM_NON_IDLE_RANGE 5:5 +#define DC_WINBUF_A_MEMFETCH_DEBUG_STATUS_0_B_U_SSM_NON_IDLE_WOFFSET 0x0 +#define DC_WINBUF_A_MEMFETCH_DEBUG_STATUS_0_B_U_SSM_NON_IDLE_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_MEMFETCH_DEBUG_STATUS_0_B_U_SSM_NON_IDLE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_WINBUF_A_MEMFETCH_DEBUG_STATUS_0_B_U_SSM_NON_IDLE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_MEMFETCH_DEBUG_STATUS_0_B_U_SSM_NON_IDLE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINBUF_A_MEMFETCH_DEBUG_STATUS_0_B_V_SSM_NON_IDLE_SHIFT _MK_SHIFT_CONST(6) +#define DC_WINBUF_A_MEMFETCH_DEBUG_STATUS_0_B_V_SSM_NON_IDLE_FIELD _MK_FIELD_CONST(0x1, DC_WINBUF_A_MEMFETCH_DEBUG_STATUS_0_B_V_SSM_NON_IDLE_SHIFT) +#define DC_WINBUF_A_MEMFETCH_DEBUG_STATUS_0_B_V_SSM_NON_IDLE_RANGE 6:6 +#define DC_WINBUF_A_MEMFETCH_DEBUG_STATUS_0_B_V_SSM_NON_IDLE_WOFFSET 0x0 +#define DC_WINBUF_A_MEMFETCH_DEBUG_STATUS_0_B_V_SSM_NON_IDLE_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_MEMFETCH_DEBUG_STATUS_0_B_V_SSM_NON_IDLE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_WINBUF_A_MEMFETCH_DEBUG_STATUS_0_B_V_SSM_NON_IDLE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_MEMFETCH_DEBUG_STATUS_0_B_V_SSM_NON_IDLE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINBUF_A_MEMFETCH_DEBUG_STATUS_0_B_DP_VALID_NON_IDLE_SHIFT _MK_SHIFT_CONST(7) +#define DC_WINBUF_A_MEMFETCH_DEBUG_STATUS_0_B_DP_VALID_NON_IDLE_FIELD _MK_FIELD_CONST(0x1, DC_WINBUF_A_MEMFETCH_DEBUG_STATUS_0_B_DP_VALID_NON_IDLE_SHIFT) +#define DC_WINBUF_A_MEMFETCH_DEBUG_STATUS_0_B_DP_VALID_NON_IDLE_RANGE 7:7 +#define DC_WINBUF_A_MEMFETCH_DEBUG_STATUS_0_B_DP_VALID_NON_IDLE_WOFFSET 0x0 +#define DC_WINBUF_A_MEMFETCH_DEBUG_STATUS_0_B_DP_VALID_NON_IDLE_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_MEMFETCH_DEBUG_STATUS_0_B_DP_VALID_NON_IDLE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_WINBUF_A_MEMFETCH_DEBUG_STATUS_0_B_DP_VALID_NON_IDLE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_MEMFETCH_DEBUG_STATUS_0_B_DP_VALID_NON_IDLE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINBUF_A_MEMFETCH_DEBUG_STATUS_0_B_REQ_FIFO_NON_IDLE_SHIFT _MK_SHIFT_CONST(8) +#define DC_WINBUF_A_MEMFETCH_DEBUG_STATUS_0_B_REQ_FIFO_NON_IDLE_FIELD _MK_FIELD_CONST(0x1, DC_WINBUF_A_MEMFETCH_DEBUG_STATUS_0_B_REQ_FIFO_NON_IDLE_SHIFT) +#define DC_WINBUF_A_MEMFETCH_DEBUG_STATUS_0_B_REQ_FIFO_NON_IDLE_RANGE 8:8 +#define DC_WINBUF_A_MEMFETCH_DEBUG_STATUS_0_B_REQ_FIFO_NON_IDLE_WOFFSET 0x0 +#define DC_WINBUF_A_MEMFETCH_DEBUG_STATUS_0_B_REQ_FIFO_NON_IDLE_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_MEMFETCH_DEBUG_STATUS_0_B_REQ_FIFO_NON_IDLE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_WINBUF_A_MEMFETCH_DEBUG_STATUS_0_B_REQ_FIFO_NON_IDLE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_MEMFETCH_DEBUG_STATUS_0_B_REQ_FIFO_NON_IDLE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINBUF_A_MEMFETCH_DEBUG_STATUS_0_B_RSP_FIFO_NON_IDLE_SHIFT _MK_SHIFT_CONST(9) +#define DC_WINBUF_A_MEMFETCH_DEBUG_STATUS_0_B_RSP_FIFO_NON_IDLE_FIELD _MK_FIELD_CONST(0x1, DC_WINBUF_A_MEMFETCH_DEBUG_STATUS_0_B_RSP_FIFO_NON_IDLE_SHIFT) +#define DC_WINBUF_A_MEMFETCH_DEBUG_STATUS_0_B_RSP_FIFO_NON_IDLE_RANGE 9:9 +#define DC_WINBUF_A_MEMFETCH_DEBUG_STATUS_0_B_RSP_FIFO_NON_IDLE_WOFFSET 0x0 +#define DC_WINBUF_A_MEMFETCH_DEBUG_STATUS_0_B_RSP_FIFO_NON_IDLE_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_MEMFETCH_DEBUG_STATUS_0_B_RSP_FIFO_NON_IDLE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_WINBUF_A_MEMFETCH_DEBUG_STATUS_0_B_RSP_FIFO_NON_IDLE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_MEMFETCH_DEBUG_STATUS_0_B_RSP_FIFO_NON_IDLE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINBUF_A_MEMFETCH_DEBUG_STATUS_0_B_TAG_FIFO_NON_IDLE_SHIFT _MK_SHIFT_CONST(10) +#define DC_WINBUF_A_MEMFETCH_DEBUG_STATUS_0_B_TAG_FIFO_NON_IDLE_FIELD _MK_FIELD_CONST(0x1, DC_WINBUF_A_MEMFETCH_DEBUG_STATUS_0_B_TAG_FIFO_NON_IDLE_SHIFT) +#define DC_WINBUF_A_MEMFETCH_DEBUG_STATUS_0_B_TAG_FIFO_NON_IDLE_RANGE 10:10 +#define DC_WINBUF_A_MEMFETCH_DEBUG_STATUS_0_B_TAG_FIFO_NON_IDLE_WOFFSET 0x0 +#define DC_WINBUF_A_MEMFETCH_DEBUG_STATUS_0_B_TAG_FIFO_NON_IDLE_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_MEMFETCH_DEBUG_STATUS_0_B_TAG_FIFO_NON_IDLE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_WINBUF_A_MEMFETCH_DEBUG_STATUS_0_B_TAG_FIFO_NON_IDLE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_MEMFETCH_DEBUG_STATUS_0_B_TAG_FIFO_NON_IDLE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINBUF_A_MEMFETCH_DEBUG_STATUS_0_B_SURFACE_FIFO_NON_IDLE_SHIFT _MK_SHIFT_CONST(11) +#define DC_WINBUF_A_MEMFETCH_DEBUG_STATUS_0_B_SURFACE_FIFO_NON_IDLE_FIELD _MK_FIELD_CONST(0x1, DC_WINBUF_A_MEMFETCH_DEBUG_STATUS_0_B_SURFACE_FIFO_NON_IDLE_SHIFT) +#define DC_WINBUF_A_MEMFETCH_DEBUG_STATUS_0_B_SURFACE_FIFO_NON_IDLE_RANGE 11:11 +#define DC_WINBUF_A_MEMFETCH_DEBUG_STATUS_0_B_SURFACE_FIFO_NON_IDLE_WOFFSET 0x0 +#define DC_WINBUF_A_MEMFETCH_DEBUG_STATUS_0_B_SURFACE_FIFO_NON_IDLE_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_MEMFETCH_DEBUG_STATUS_0_B_SURFACE_FIFO_NON_IDLE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_WINBUF_A_MEMFETCH_DEBUG_STATUS_0_B_SURFACE_FIFO_NON_IDLE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_MEMFETCH_DEBUG_STATUS_0_B_SURFACE_FIFO_NON_IDLE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINBUF_A_MEMFETCH_DEBUG_STATUS_0_B_FRAME_FIFO_NON_IDLE_SHIFT _MK_SHIFT_CONST(12) +#define DC_WINBUF_A_MEMFETCH_DEBUG_STATUS_0_B_FRAME_FIFO_NON_IDLE_FIELD _MK_FIELD_CONST(0x1, DC_WINBUF_A_MEMFETCH_DEBUG_STATUS_0_B_FRAME_FIFO_NON_IDLE_SHIFT) +#define DC_WINBUF_A_MEMFETCH_DEBUG_STATUS_0_B_FRAME_FIFO_NON_IDLE_RANGE 12:12 +#define DC_WINBUF_A_MEMFETCH_DEBUG_STATUS_0_B_FRAME_FIFO_NON_IDLE_WOFFSET 0x0 +#define DC_WINBUF_A_MEMFETCH_DEBUG_STATUS_0_B_FRAME_FIFO_NON_IDLE_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_MEMFETCH_DEBUG_STATUS_0_B_FRAME_FIFO_NON_IDLE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_WINBUF_A_MEMFETCH_DEBUG_STATUS_0_B_FRAME_FIFO_NON_IDLE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_MEMFETCH_DEBUG_STATUS_0_B_FRAME_FIFO_NON_IDLE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINBUF_A_MEMFETCH_DEBUG_STATUS_0_B_PIPE0_FIFO_NON_IDLE_SHIFT _MK_SHIFT_CONST(13) +#define DC_WINBUF_A_MEMFETCH_DEBUG_STATUS_0_B_PIPE0_FIFO_NON_IDLE_FIELD _MK_FIELD_CONST(0x1, DC_WINBUF_A_MEMFETCH_DEBUG_STATUS_0_B_PIPE0_FIFO_NON_IDLE_SHIFT) +#define DC_WINBUF_A_MEMFETCH_DEBUG_STATUS_0_B_PIPE0_FIFO_NON_IDLE_RANGE 13:13 +#define DC_WINBUF_A_MEMFETCH_DEBUG_STATUS_0_B_PIPE0_FIFO_NON_IDLE_WOFFSET 0x0 +#define DC_WINBUF_A_MEMFETCH_DEBUG_STATUS_0_B_PIPE0_FIFO_NON_IDLE_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_MEMFETCH_DEBUG_STATUS_0_B_PIPE0_FIFO_NON_IDLE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_WINBUF_A_MEMFETCH_DEBUG_STATUS_0_B_PIPE0_FIFO_NON_IDLE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_MEMFETCH_DEBUG_STATUS_0_B_PIPE0_FIFO_NON_IDLE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINBUF_A_MEMFETCH_DEBUG_STATUS_0_B_PIPE1_FIFO_NON_IDLE_SHIFT _MK_SHIFT_CONST(14) +#define DC_WINBUF_A_MEMFETCH_DEBUG_STATUS_0_B_PIPE1_FIFO_NON_IDLE_FIELD _MK_FIELD_CONST(0x1, DC_WINBUF_A_MEMFETCH_DEBUG_STATUS_0_B_PIPE1_FIFO_NON_IDLE_SHIFT) +#define DC_WINBUF_A_MEMFETCH_DEBUG_STATUS_0_B_PIPE1_FIFO_NON_IDLE_RANGE 14:14 +#define DC_WINBUF_A_MEMFETCH_DEBUG_STATUS_0_B_PIPE1_FIFO_NON_IDLE_WOFFSET 0x0 +#define DC_WINBUF_A_MEMFETCH_DEBUG_STATUS_0_B_PIPE1_FIFO_NON_IDLE_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_MEMFETCH_DEBUG_STATUS_0_B_PIPE1_FIFO_NON_IDLE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_WINBUF_A_MEMFETCH_DEBUG_STATUS_0_B_PIPE1_FIFO_NON_IDLE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_MEMFETCH_DEBUG_STATUS_0_B_PIPE1_FIFO_NON_IDLE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINBUF_A_MEMFETCH_DEBUG_STATUS_0_B_ALIGN_FIFO_NON_IDLE_SHIFT _MK_SHIFT_CONST(15) +#define DC_WINBUF_A_MEMFETCH_DEBUG_STATUS_0_B_ALIGN_FIFO_NON_IDLE_FIELD _MK_FIELD_CONST(0x1, DC_WINBUF_A_MEMFETCH_DEBUG_STATUS_0_B_ALIGN_FIFO_NON_IDLE_SHIFT) +#define DC_WINBUF_A_MEMFETCH_DEBUG_STATUS_0_B_ALIGN_FIFO_NON_IDLE_RANGE 15:15 +#define DC_WINBUF_A_MEMFETCH_DEBUG_STATUS_0_B_ALIGN_FIFO_NON_IDLE_WOFFSET 0x0 +#define DC_WINBUF_A_MEMFETCH_DEBUG_STATUS_0_B_ALIGN_FIFO_NON_IDLE_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_MEMFETCH_DEBUG_STATUS_0_B_ALIGN_FIFO_NON_IDLE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_WINBUF_A_MEMFETCH_DEBUG_STATUS_0_B_ALIGN_FIFO_NON_IDLE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_MEMFETCH_DEBUG_STATUS_0_B_ALIGN_FIFO_NON_IDLE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_WINBUF_A_MEMFETCH_DEBUG_STATUS_0_A_DEBUG_ENABLE_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINBUF_A_MEMFETCH_DEBUG_STATUS_0_A_DEBUG_ENABLE_FIELD _MK_FIELD_CONST(0x1, DC_WINBUF_A_MEMFETCH_DEBUG_STATUS_0_A_DEBUG_ENABLE_SHIFT) +#define DC_WINBUF_A_MEMFETCH_DEBUG_STATUS_0_A_DEBUG_ENABLE_RANGE 16:16 +#define DC_WINBUF_A_MEMFETCH_DEBUG_STATUS_0_A_DEBUG_ENABLE_WOFFSET 0x0 +#define DC_WINBUF_A_MEMFETCH_DEBUG_STATUS_0_A_DEBUG_ENABLE_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_MEMFETCH_DEBUG_STATUS_0_A_DEBUG_ENABLE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_WINBUF_A_MEMFETCH_DEBUG_STATUS_0_A_DEBUG_ENABLE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_MEMFETCH_DEBUG_STATUS_0_A_DEBUG_ENABLE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_WINBUF_A_MEMFETCH_CONTROL_0 +#define DC_WINBUF_A_MEMFETCH_CONTROL_0 _MK_ADDR_CONST(0x82b) +#define DC_WINBUF_A_MEMFETCH_CONTROL_0_SECURE 0x0 +#define DC_WINBUF_A_MEMFETCH_CONTROL_0_WORD_COUNT 0x1 +#define DC_WINBUF_A_MEMFETCH_CONTROL_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_MEMFETCH_CONTROL_0_RESET_MASK _MK_MASK_CONST(0x3) +#define DC_WINBUF_A_MEMFETCH_CONTROL_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x1) +#define DC_WINBUF_A_MEMFETCH_CONTROL_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_WINBUF_A_MEMFETCH_CONTROL_0_READ_MASK _MK_MASK_CONST(0x3) +#define DC_WINBUF_A_MEMFETCH_CONTROL_0_WRITE_MASK _MK_MASK_CONST(0x3) +#define DC_WINBUF_A_MEMFETCH_CONTROL_0_A_MEMFETCH_RESET_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINBUF_A_MEMFETCH_CONTROL_0_A_MEMFETCH_RESET_FIELD _MK_FIELD_CONST(0x1, DC_WINBUF_A_MEMFETCH_CONTROL_0_A_MEMFETCH_RESET_SHIFT) +#define DC_WINBUF_A_MEMFETCH_CONTROL_0_A_MEMFETCH_RESET_RANGE 0:0 +#define DC_WINBUF_A_MEMFETCH_CONTROL_0_A_MEMFETCH_RESET_WOFFSET 0x0 +#define DC_WINBUF_A_MEMFETCH_CONTROL_0_A_MEMFETCH_RESET_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_MEMFETCH_CONTROL_0_A_MEMFETCH_RESET_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_WINBUF_A_MEMFETCH_CONTROL_0_A_MEMFETCH_RESET_SW_DEFAULT _MK_MASK_CONST(0x1) +#define DC_WINBUF_A_MEMFETCH_CONTROL_0_A_MEMFETCH_RESET_SW_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_WINBUF_A_MEMFETCH_CONTROL_0_A_MEMFETCH_RESET_DISABLE _MK_ENUM_CONST(0) +#define DC_WINBUF_A_MEMFETCH_CONTROL_0_A_MEMFETCH_RESET_ENABLE _MK_ENUM_CONST(1) + +#define DC_WINBUF_A_MEMFETCH_CONTROL_0_A_MEMFETCH_CLK_GATE_OVERRIDE_SHIFT _MK_SHIFT_CONST(1) +#define DC_WINBUF_A_MEMFETCH_CONTROL_0_A_MEMFETCH_CLK_GATE_OVERRIDE_FIELD _MK_FIELD_CONST(0x1, DC_WINBUF_A_MEMFETCH_CONTROL_0_A_MEMFETCH_CLK_GATE_OVERRIDE_SHIFT) +#define DC_WINBUF_A_MEMFETCH_CONTROL_0_A_MEMFETCH_CLK_GATE_OVERRIDE_RANGE 1:1 +#define DC_WINBUF_A_MEMFETCH_CONTROL_0_A_MEMFETCH_CLK_GATE_OVERRIDE_WOFFSET 0x0 +#define DC_WINBUF_A_MEMFETCH_CONTROL_0_A_MEMFETCH_CLK_GATE_OVERRIDE_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_MEMFETCH_CONTROL_0_A_MEMFETCH_CLK_GATE_OVERRIDE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_WINBUF_A_MEMFETCH_CONTROL_0_A_MEMFETCH_CLK_GATE_OVERRIDE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_MEMFETCH_CONTROL_0_A_MEMFETCH_CLK_GATE_OVERRIDE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_MEMFETCH_CONTROL_0_A_MEMFETCH_CLK_GATE_OVERRIDE_DISABLE _MK_ENUM_CONST(0) +#define DC_WINBUF_A_MEMFETCH_CONTROL_0_A_MEMFETCH_CLK_GATE_OVERRIDE_ENABLE _MK_ENUM_CONST(1) + + +// Register DC_WINBUF_A_OCCUPANCY_THROTTLE_0 +#define DC_WINBUF_A_OCCUPANCY_THROTTLE_0 _MK_ADDR_CONST(0x82c) +#define DC_WINBUF_A_OCCUPANCY_THROTTLE_0_SECURE 0x0 +#define DC_WINBUF_A_OCCUPANCY_THROTTLE_0_WORD_COUNT 0x1 +#define DC_WINBUF_A_OCCUPANCY_THROTTLE_0_RESET_VAL _MK_MASK_CONST(0xffff0000) +#define DC_WINBUF_A_OCCUPANCY_THROTTLE_0_RESET_MASK _MK_MASK_CONST(0xffff0001) +#define DC_WINBUF_A_OCCUPANCY_THROTTLE_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_OCCUPANCY_THROTTLE_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_OCCUPANCY_THROTTLE_0_READ_MASK _MK_MASK_CONST(0xffff0001) +#define DC_WINBUF_A_OCCUPANCY_THROTTLE_0_WRITE_MASK _MK_MASK_CONST(0xffff0001) +#define DC_WINBUF_A_OCCUPANCY_THROTTLE_0_A_OCCUPANCY_THROTTLE_MODE_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINBUF_A_OCCUPANCY_THROTTLE_0_A_OCCUPANCY_THROTTLE_MODE_FIELD _MK_FIELD_CONST(0x1, DC_WINBUF_A_OCCUPANCY_THROTTLE_0_A_OCCUPANCY_THROTTLE_MODE_SHIFT) +#define DC_WINBUF_A_OCCUPANCY_THROTTLE_0_A_OCCUPANCY_THROTTLE_MODE_RANGE 0:0 +#define DC_WINBUF_A_OCCUPANCY_THROTTLE_0_A_OCCUPANCY_THROTTLE_MODE_WOFFSET 0x0 +#define DC_WINBUF_A_OCCUPANCY_THROTTLE_0_A_OCCUPANCY_THROTTLE_MODE_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_OCCUPANCY_THROTTLE_0_A_OCCUPANCY_THROTTLE_MODE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_WINBUF_A_OCCUPANCY_THROTTLE_0_A_OCCUPANCY_THROTTLE_MODE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_OCCUPANCY_THROTTLE_0_A_OCCUPANCY_THROTTLE_MODE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_OCCUPANCY_THROTTLE_0_A_OCCUPANCY_THROTTLE_MODE_DISABLE _MK_ENUM_CONST(0) +#define DC_WINBUF_A_OCCUPANCY_THROTTLE_0_A_OCCUPANCY_THROTTLE_MODE_ENABLE _MK_ENUM_CONST(1) + +#define DC_WINBUF_A_OCCUPANCY_THROTTLE_0_A_OCCUPANCY_MAX_THRESHOLD_SHIFT _MK_SHIFT_CONST(16) +#define DC_WINBUF_A_OCCUPANCY_THROTTLE_0_A_OCCUPANCY_MAX_THRESHOLD_FIELD _MK_FIELD_CONST(0xffff, DC_WINBUF_A_OCCUPANCY_THROTTLE_0_A_OCCUPANCY_MAX_THRESHOLD_SHIFT) +#define DC_WINBUF_A_OCCUPANCY_THROTTLE_0_A_OCCUPANCY_MAX_THRESHOLD_RANGE 31:16 +#define DC_WINBUF_A_OCCUPANCY_THROTTLE_0_A_OCCUPANCY_MAX_THRESHOLD_WOFFSET 0x0 +#define DC_WINBUF_A_OCCUPANCY_THROTTLE_0_A_OCCUPANCY_MAX_THRESHOLD_DEFAULT _MK_MASK_CONST(0xffff) +#define DC_WINBUF_A_OCCUPANCY_THROTTLE_0_A_OCCUPANCY_MAX_THRESHOLD_DEFAULT_MASK _MK_MASK_CONST(0xffff) +#define DC_WINBUF_A_OCCUPANCY_THROTTLE_0_A_OCCUPANCY_MAX_THRESHOLD_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_OCCUPANCY_THROTTLE_0_A_OCCUPANCY_MAX_THRESHOLD_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_WINBUF_A_SCRATCH_REGISTER_0_0 +#define DC_WINBUF_A_SCRATCH_REGISTER_0_0 _MK_ADDR_CONST(0x82d) +#define DC_WINBUF_A_SCRATCH_REGISTER_0_0_SECURE 0x0 +#define DC_WINBUF_A_SCRATCH_REGISTER_0_0_WORD_COUNT 0x1 +#define DC_WINBUF_A_SCRATCH_REGISTER_0_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_SCRATCH_REGISTER_0_0_RESET_MASK _MK_MASK_CONST(0xffffffff) +#define DC_WINBUF_A_SCRATCH_REGISTER_0_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_SCRATCH_REGISTER_0_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_SCRATCH_REGISTER_0_0_READ_MASK _MK_MASK_CONST(0xffffffff) +#define DC_WINBUF_A_SCRATCH_REGISTER_0_0_WRITE_MASK _MK_MASK_CONST(0xffffffff) +#define DC_WINBUF_A_SCRATCH_REGISTER_0_0_A_SCRATCH_REGISTER_0_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINBUF_A_SCRATCH_REGISTER_0_0_A_SCRATCH_REGISTER_0_FIELD _MK_FIELD_CONST(0xffffffff, DC_WINBUF_A_SCRATCH_REGISTER_0_0_A_SCRATCH_REGISTER_0_SHIFT) +#define DC_WINBUF_A_SCRATCH_REGISTER_0_0_A_SCRATCH_REGISTER_0_RANGE 31:0 +#define DC_WINBUF_A_SCRATCH_REGISTER_0_0_A_SCRATCH_REGISTER_0_WOFFSET 0x0 +#define DC_WINBUF_A_SCRATCH_REGISTER_0_0_A_SCRATCH_REGISTER_0_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_SCRATCH_REGISTER_0_0_A_SCRATCH_REGISTER_0_DEFAULT_MASK _MK_MASK_CONST(0xffffffff) +#define DC_WINBUF_A_SCRATCH_REGISTER_0_0_A_SCRATCH_REGISTER_0_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_SCRATCH_REGISTER_0_0_A_SCRATCH_REGISTER_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_WINBUF_A_SCRATCH_REGISTER_1_0 +#define DC_WINBUF_A_SCRATCH_REGISTER_1_0 _MK_ADDR_CONST(0x82e) +#define DC_WINBUF_A_SCRATCH_REGISTER_1_0_SECURE 0x0 +#define DC_WINBUF_A_SCRATCH_REGISTER_1_0_WORD_COUNT 0x1 +#define DC_WINBUF_A_SCRATCH_REGISTER_1_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_SCRATCH_REGISTER_1_0_RESET_MASK _MK_MASK_CONST(0xffffffff) +#define DC_WINBUF_A_SCRATCH_REGISTER_1_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_SCRATCH_REGISTER_1_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_SCRATCH_REGISTER_1_0_READ_MASK _MK_MASK_CONST(0xffffffff) +#define DC_WINBUF_A_SCRATCH_REGISTER_1_0_WRITE_MASK _MK_MASK_CONST(0xffffffff) +#define DC_WINBUF_A_SCRATCH_REGISTER_1_0_A_SCRATCH_REGISTER_1_SHIFT _MK_SHIFT_CONST(0) +#define DC_WINBUF_A_SCRATCH_REGISTER_1_0_A_SCRATCH_REGISTER_1_FIELD _MK_FIELD_CONST(0xffffffff, DC_WINBUF_A_SCRATCH_REGISTER_1_0_A_SCRATCH_REGISTER_1_SHIFT) +#define DC_WINBUF_A_SCRATCH_REGISTER_1_0_A_SCRATCH_REGISTER_1_RANGE 31:0 +#define DC_WINBUF_A_SCRATCH_REGISTER_1_0_A_SCRATCH_REGISTER_1_WOFFSET 0x0 +#define DC_WINBUF_A_SCRATCH_REGISTER_1_0_A_SCRATCH_REGISTER_1_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_SCRATCH_REGISTER_1_0_A_SCRATCH_REGISTER_1_DEFAULT_MASK _MK_MASK_CONST(0xffffffff) +#define DC_WINBUF_A_SCRATCH_REGISTER_1_0_A_SCRATCH_REGISTER_1_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_WINBUF_A_SCRATCH_REGISTER_1_0_A_SCRATCH_REGISTER_1_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// +// REGISTER LIST +// +#define LIST_ARDISPLAY_A_REGS(_op_) \ +_op_(DC_WINC_A_COLOR_PALETTE_0) \ +_op_(DC_WINC_A_COLOR_PALETTE) \ +_op_(DC_WINC_A_COLOR_PALETTE_1) \ +_op_(DC_WINC_A_COLOR_PALETTE_2) \ +_op_(DC_WINC_A_COLOR_PALETTE_3) \ +_op_(DC_WINC_A_COLOR_PALETTE_4) \ +_op_(DC_WINC_A_COLOR_PALETTE_5) \ +_op_(DC_WINC_A_COLOR_PALETTE_6) \ +_op_(DC_WINC_A_COLOR_PALETTE_7) \ +_op_(DC_WINC_A_COLOR_PALETTE_8) \ +_op_(DC_WINC_A_COLOR_PALETTE_9) \ +_op_(DC_WINC_A_COLOR_PALETTE_10) \ +_op_(DC_WINC_A_COLOR_PALETTE_11) \ +_op_(DC_WINC_A_COLOR_PALETTE_12) \ +_op_(DC_WINC_A_COLOR_PALETTE_13) \ +_op_(DC_WINC_A_COLOR_PALETTE_14) \ +_op_(DC_WINC_A_COLOR_PALETTE_15) \ +_op_(DC_WINC_A_COLOR_PALETTE_16) \ +_op_(DC_WINC_A_COLOR_PALETTE_17) \ +_op_(DC_WINC_A_COLOR_PALETTE_18) \ +_op_(DC_WINC_A_COLOR_PALETTE_19) \ +_op_(DC_WINC_A_COLOR_PALETTE_20) \ +_op_(DC_WINC_A_COLOR_PALETTE_21) \ +_op_(DC_WINC_A_COLOR_PALETTE_22) \ +_op_(DC_WINC_A_COLOR_PALETTE_23) \ +_op_(DC_WINC_A_COLOR_PALETTE_24) \ +_op_(DC_WINC_A_COLOR_PALETTE_25) \ +_op_(DC_WINC_A_COLOR_PALETTE_26) \ +_op_(DC_WINC_A_COLOR_PALETTE_27) \ +_op_(DC_WINC_A_COLOR_PALETTE_28) \ +_op_(DC_WINC_A_COLOR_PALETTE_29) \ +_op_(DC_WINC_A_COLOR_PALETTE_30) \ +_op_(DC_WINC_A_COLOR_PALETTE_31) \ +_op_(DC_WINC_A_COLOR_PALETTE_32) \ +_op_(DC_WINC_A_COLOR_PALETTE_33) \ +_op_(DC_WINC_A_COLOR_PALETTE_34) \ +_op_(DC_WINC_A_COLOR_PALETTE_35) \ +_op_(DC_WINC_A_COLOR_PALETTE_36) \ +_op_(DC_WINC_A_COLOR_PALETTE_37) \ +_op_(DC_WINC_A_COLOR_PALETTE_38) \ +_op_(DC_WINC_A_COLOR_PALETTE_39) \ +_op_(DC_WINC_A_COLOR_PALETTE_40) \ +_op_(DC_WINC_A_COLOR_PALETTE_41) \ +_op_(DC_WINC_A_COLOR_PALETTE_42) \ +_op_(DC_WINC_A_COLOR_PALETTE_43) \ +_op_(DC_WINC_A_COLOR_PALETTE_44) \ +_op_(DC_WINC_A_COLOR_PALETTE_45) \ +_op_(DC_WINC_A_COLOR_PALETTE_46) \ +_op_(DC_WINC_A_COLOR_PALETTE_47) \ +_op_(DC_WINC_A_COLOR_PALETTE_48) \ +_op_(DC_WINC_A_COLOR_PALETTE_49) \ +_op_(DC_WINC_A_COLOR_PALETTE_50) \ +_op_(DC_WINC_A_COLOR_PALETTE_51) \ +_op_(DC_WINC_A_COLOR_PALETTE_52) \ +_op_(DC_WINC_A_COLOR_PALETTE_53) \ +_op_(DC_WINC_A_COLOR_PALETTE_54) \ +_op_(DC_WINC_A_COLOR_PALETTE_55) \ +_op_(DC_WINC_A_COLOR_PALETTE_56) \ +_op_(DC_WINC_A_COLOR_PALETTE_57) \ +_op_(DC_WINC_A_COLOR_PALETTE_58) \ +_op_(DC_WINC_A_COLOR_PALETTE_59) \ +_op_(DC_WINC_A_COLOR_PALETTE_60) \ +_op_(DC_WINC_A_COLOR_PALETTE_61) \ +_op_(DC_WINC_A_COLOR_PALETTE_62) \ +_op_(DC_WINC_A_COLOR_PALETTE_63) \ +_op_(DC_WINC_A_COLOR_PALETTE_64) \ +_op_(DC_WINC_A_COLOR_PALETTE_65) \ +_op_(DC_WINC_A_COLOR_PALETTE_66) \ +_op_(DC_WINC_A_COLOR_PALETTE_67) \ +_op_(DC_WINC_A_COLOR_PALETTE_68) \ +_op_(DC_WINC_A_COLOR_PALETTE_69) \ +_op_(DC_WINC_A_COLOR_PALETTE_70) \ +_op_(DC_WINC_A_COLOR_PALETTE_71) \ +_op_(DC_WINC_A_COLOR_PALETTE_72) \ +_op_(DC_WINC_A_COLOR_PALETTE_73) \ +_op_(DC_WINC_A_COLOR_PALETTE_74) \ +_op_(DC_WINC_A_COLOR_PALETTE_75) \ +_op_(DC_WINC_A_COLOR_PALETTE_76) \ +_op_(DC_WINC_A_COLOR_PALETTE_77) \ +_op_(DC_WINC_A_COLOR_PALETTE_78) \ +_op_(DC_WINC_A_COLOR_PALETTE_79) \ +_op_(DC_WINC_A_COLOR_PALETTE_80) \ +_op_(DC_WINC_A_COLOR_PALETTE_81) \ +_op_(DC_WINC_A_COLOR_PALETTE_82) \ +_op_(DC_WINC_A_COLOR_PALETTE_83) \ +_op_(DC_WINC_A_COLOR_PALETTE_84) \ +_op_(DC_WINC_A_COLOR_PALETTE_85) \ +_op_(DC_WINC_A_COLOR_PALETTE_86) \ +_op_(DC_WINC_A_COLOR_PALETTE_87) \ +_op_(DC_WINC_A_COLOR_PALETTE_88) \ +_op_(DC_WINC_A_COLOR_PALETTE_89) \ +_op_(DC_WINC_A_COLOR_PALETTE_90) \ +_op_(DC_WINC_A_COLOR_PALETTE_91) \ +_op_(DC_WINC_A_COLOR_PALETTE_92) \ +_op_(DC_WINC_A_COLOR_PALETTE_93) \ +_op_(DC_WINC_A_COLOR_PALETTE_94) \ +_op_(DC_WINC_A_COLOR_PALETTE_95) \ +_op_(DC_WINC_A_COLOR_PALETTE_96) \ +_op_(DC_WINC_A_COLOR_PALETTE_97) \ +_op_(DC_WINC_A_COLOR_PALETTE_98) \ +_op_(DC_WINC_A_COLOR_PALETTE_99) \ +_op_(DC_WINC_A_COLOR_PALETTE_100) \ +_op_(DC_WINC_A_COLOR_PALETTE_101) \ +_op_(DC_WINC_A_COLOR_PALETTE_102) \ +_op_(DC_WINC_A_COLOR_PALETTE_103) \ +_op_(DC_WINC_A_COLOR_PALETTE_104) \ +_op_(DC_WINC_A_COLOR_PALETTE_105) \ +_op_(DC_WINC_A_COLOR_PALETTE_106) \ +_op_(DC_WINC_A_COLOR_PALETTE_107) \ +_op_(DC_WINC_A_COLOR_PALETTE_108) \ +_op_(DC_WINC_A_COLOR_PALETTE_109) \ +_op_(DC_WINC_A_COLOR_PALETTE_110) \ +_op_(DC_WINC_A_COLOR_PALETTE_111) \ +_op_(DC_WINC_A_COLOR_PALETTE_112) \ +_op_(DC_WINC_A_COLOR_PALETTE_113) \ +_op_(DC_WINC_A_COLOR_PALETTE_114) \ +_op_(DC_WINC_A_COLOR_PALETTE_115) \ +_op_(DC_WINC_A_COLOR_PALETTE_116) \ +_op_(DC_WINC_A_COLOR_PALETTE_117) \ +_op_(DC_WINC_A_COLOR_PALETTE_118) \ +_op_(DC_WINC_A_COLOR_PALETTE_119) \ +_op_(DC_WINC_A_COLOR_PALETTE_120) \ +_op_(DC_WINC_A_COLOR_PALETTE_121) \ +_op_(DC_WINC_A_COLOR_PALETTE_122) \ +_op_(DC_WINC_A_COLOR_PALETTE_123) \ +_op_(DC_WINC_A_COLOR_PALETTE_124) \ +_op_(DC_WINC_A_COLOR_PALETTE_125) \ +_op_(DC_WINC_A_COLOR_PALETTE_126) \ +_op_(DC_WINC_A_COLOR_PALETTE_127) \ +_op_(DC_WINC_A_COLOR_PALETTE_128) \ +_op_(DC_WINC_A_COLOR_PALETTE_129) \ +_op_(DC_WINC_A_COLOR_PALETTE_130) \ +_op_(DC_WINC_A_COLOR_PALETTE_131) \ +_op_(DC_WINC_A_COLOR_PALETTE_132) \ +_op_(DC_WINC_A_COLOR_PALETTE_133) \ +_op_(DC_WINC_A_COLOR_PALETTE_134) \ +_op_(DC_WINC_A_COLOR_PALETTE_135) \ +_op_(DC_WINC_A_COLOR_PALETTE_136) \ +_op_(DC_WINC_A_COLOR_PALETTE_137) \ +_op_(DC_WINC_A_COLOR_PALETTE_138) \ +_op_(DC_WINC_A_COLOR_PALETTE_139) \ +_op_(DC_WINC_A_COLOR_PALETTE_140) \ +_op_(DC_WINC_A_COLOR_PALETTE_141) \ +_op_(DC_WINC_A_COLOR_PALETTE_142) \ +_op_(DC_WINC_A_COLOR_PALETTE_143) \ +_op_(DC_WINC_A_COLOR_PALETTE_144) \ +_op_(DC_WINC_A_COLOR_PALETTE_145) \ +_op_(DC_WINC_A_COLOR_PALETTE_146) \ +_op_(DC_WINC_A_COLOR_PALETTE_147) \ +_op_(DC_WINC_A_COLOR_PALETTE_148) \ +_op_(DC_WINC_A_COLOR_PALETTE_149) \ +_op_(DC_WINC_A_COLOR_PALETTE_150) \ +_op_(DC_WINC_A_COLOR_PALETTE_151) \ +_op_(DC_WINC_A_COLOR_PALETTE_152) \ +_op_(DC_WINC_A_COLOR_PALETTE_153) \ +_op_(DC_WINC_A_COLOR_PALETTE_154) \ +_op_(DC_WINC_A_COLOR_PALETTE_155) \ +_op_(DC_WINC_A_COLOR_PALETTE_156) \ +_op_(DC_WINC_A_COLOR_PALETTE_157) \ +_op_(DC_WINC_A_COLOR_PALETTE_158) \ +_op_(DC_WINC_A_COLOR_PALETTE_159) \ +_op_(DC_WINC_A_COLOR_PALETTE_160) \ +_op_(DC_WINC_A_COLOR_PALETTE_161) \ +_op_(DC_WINC_A_COLOR_PALETTE_162) \ +_op_(DC_WINC_A_COLOR_PALETTE_163) \ +_op_(DC_WINC_A_COLOR_PALETTE_164) \ +_op_(DC_WINC_A_COLOR_PALETTE_165) \ +_op_(DC_WINC_A_COLOR_PALETTE_166) \ +_op_(DC_WINC_A_COLOR_PALETTE_167) \ +_op_(DC_WINC_A_COLOR_PALETTE_168) \ +_op_(DC_WINC_A_COLOR_PALETTE_169) \ +_op_(DC_WINC_A_COLOR_PALETTE_170) \ +_op_(DC_WINC_A_COLOR_PALETTE_171) \ +_op_(DC_WINC_A_COLOR_PALETTE_172) \ +_op_(DC_WINC_A_COLOR_PALETTE_173) \ +_op_(DC_WINC_A_COLOR_PALETTE_174) \ +_op_(DC_WINC_A_COLOR_PALETTE_175) \ +_op_(DC_WINC_A_COLOR_PALETTE_176) \ +_op_(DC_WINC_A_COLOR_PALETTE_177) \ +_op_(DC_WINC_A_COLOR_PALETTE_178) \ +_op_(DC_WINC_A_COLOR_PALETTE_179) \ +_op_(DC_WINC_A_COLOR_PALETTE_180) \ +_op_(DC_WINC_A_COLOR_PALETTE_181) \ +_op_(DC_WINC_A_COLOR_PALETTE_182) \ +_op_(DC_WINC_A_COLOR_PALETTE_183) \ +_op_(DC_WINC_A_COLOR_PALETTE_184) \ +_op_(DC_WINC_A_COLOR_PALETTE_185) \ +_op_(DC_WINC_A_COLOR_PALETTE_186) \ +_op_(DC_WINC_A_COLOR_PALETTE_187) \ +_op_(DC_WINC_A_COLOR_PALETTE_188) \ +_op_(DC_WINC_A_COLOR_PALETTE_189) \ +_op_(DC_WINC_A_COLOR_PALETTE_190) \ +_op_(DC_WINC_A_COLOR_PALETTE_191) \ +_op_(DC_WINC_A_COLOR_PALETTE_192) \ +_op_(DC_WINC_A_COLOR_PALETTE_193) \ +_op_(DC_WINC_A_COLOR_PALETTE_194) \ +_op_(DC_WINC_A_COLOR_PALETTE_195) \ +_op_(DC_WINC_A_COLOR_PALETTE_196) \ +_op_(DC_WINC_A_COLOR_PALETTE_197) \ +_op_(DC_WINC_A_COLOR_PALETTE_198) \ +_op_(DC_WINC_A_COLOR_PALETTE_199) \ +_op_(DC_WINC_A_COLOR_PALETTE_200) \ +_op_(DC_WINC_A_COLOR_PALETTE_201) \ +_op_(DC_WINC_A_COLOR_PALETTE_202) \ +_op_(DC_WINC_A_COLOR_PALETTE_203) \ +_op_(DC_WINC_A_COLOR_PALETTE_204) \ +_op_(DC_WINC_A_COLOR_PALETTE_205) \ +_op_(DC_WINC_A_COLOR_PALETTE_206) \ +_op_(DC_WINC_A_COLOR_PALETTE_207) \ +_op_(DC_WINC_A_COLOR_PALETTE_208) \ +_op_(DC_WINC_A_COLOR_PALETTE_209) \ +_op_(DC_WINC_A_COLOR_PALETTE_210) \ +_op_(DC_WINC_A_COLOR_PALETTE_211) \ +_op_(DC_WINC_A_COLOR_PALETTE_212) \ +_op_(DC_WINC_A_COLOR_PALETTE_213) \ +_op_(DC_WINC_A_COLOR_PALETTE_214) \ +_op_(DC_WINC_A_COLOR_PALETTE_215) \ +_op_(DC_WINC_A_COLOR_PALETTE_216) \ +_op_(DC_WINC_A_COLOR_PALETTE_217) \ +_op_(DC_WINC_A_COLOR_PALETTE_218) \ +_op_(DC_WINC_A_COLOR_PALETTE_219) \ +_op_(DC_WINC_A_COLOR_PALETTE_220) \ +_op_(DC_WINC_A_COLOR_PALETTE_221) \ +_op_(DC_WINC_A_COLOR_PALETTE_222) \ +_op_(DC_WINC_A_COLOR_PALETTE_223) \ +_op_(DC_WINC_A_COLOR_PALETTE_224) \ +_op_(DC_WINC_A_COLOR_PALETTE_225) \ +_op_(DC_WINC_A_COLOR_PALETTE_226) \ +_op_(DC_WINC_A_COLOR_PALETTE_227) \ +_op_(DC_WINC_A_COLOR_PALETTE_228) \ +_op_(DC_WINC_A_COLOR_PALETTE_229) \ +_op_(DC_WINC_A_COLOR_PALETTE_230) \ +_op_(DC_WINC_A_COLOR_PALETTE_231) \ +_op_(DC_WINC_A_COLOR_PALETTE_232) \ +_op_(DC_WINC_A_COLOR_PALETTE_233) \ +_op_(DC_WINC_A_COLOR_PALETTE_234) \ +_op_(DC_WINC_A_COLOR_PALETTE_235) \ +_op_(DC_WINC_A_COLOR_PALETTE_236) \ +_op_(DC_WINC_A_COLOR_PALETTE_237) \ +_op_(DC_WINC_A_COLOR_PALETTE_238) \ +_op_(DC_WINC_A_COLOR_PALETTE_239) \ +_op_(DC_WINC_A_COLOR_PALETTE_240) \ +_op_(DC_WINC_A_COLOR_PALETTE_241) \ +_op_(DC_WINC_A_COLOR_PALETTE_242) \ +_op_(DC_WINC_A_COLOR_PALETTE_243) \ +_op_(DC_WINC_A_COLOR_PALETTE_244) \ +_op_(DC_WINC_A_COLOR_PALETTE_245) \ +_op_(DC_WINC_A_COLOR_PALETTE_246) \ +_op_(DC_WINC_A_COLOR_PALETTE_247) \ +_op_(DC_WINC_A_COLOR_PALETTE_248) \ +_op_(DC_WINC_A_COLOR_PALETTE_249) \ +_op_(DC_WINC_A_COLOR_PALETTE_250) \ +_op_(DC_WINC_A_COLOR_PALETTE_251) \ +_op_(DC_WINC_A_COLOR_PALETTE_252) \ +_op_(DC_WINC_A_COLOR_PALETTE_253) \ +_op_(DC_WINC_A_COLOR_PALETTE_254) \ +_op_(DC_WINC_A_COLOR_PALETTE_255) \ +_op_(DC_WINC_A_PALETTE_COLOR_EXT_0) \ +_op_(DC_WINC_A_H_FILTER_P00_0) \ +_op_(DC_WINC_A_H_FILTER_P01_0) \ +_op_(DC_WINC_A_H_FILTER_P02_0) \ +_op_(DC_WINC_A_H_FILTER_P03_0) \ +_op_(DC_WINC_A_H_FILTER_P04_0) \ +_op_(DC_WINC_A_H_FILTER_P05_0) \ +_op_(DC_WINC_A_H_FILTER_P06_0) \ +_op_(DC_WINC_A_H_FILTER_P07_0) \ +_op_(DC_WINC_A_H_FILTER_P08_0) \ +_op_(DC_WINC_A_H_FILTER_P09_0) \ +_op_(DC_WINC_A_H_FILTER_P0A_0) \ +_op_(DC_WINC_A_H_FILTER_P0B_0) \ +_op_(DC_WINC_A_H_FILTER_P0C_0) \ +_op_(DC_WINC_A_H_FILTER_P0D_0) \ +_op_(DC_WINC_A_H_FILTER_P0E_0) \ +_op_(DC_WINC_A_H_FILTER_P0F_0) \ +_op_(DC_WINC_A_CSC_YOF_0) \ +_op_(DC_WINC_A_CSC_KYRGB_0) \ +_op_(DC_WINC_A_CSC_KUR_0) \ +_op_(DC_WINC_A_CSC_KVR_0) \ +_op_(DC_WINC_A_CSC_KUG_0) \ +_op_(DC_WINC_A_CSC_KVG_0) \ +_op_(DC_WINC_A_CSC_KUB_0) \ +_op_(DC_WINC_A_CSC_KVB_0) \ +_op_(DC_WINC_A_V_FILTER_P00_0) \ +_op_(DC_WINC_A_V_FILTER_P01_0) \ +_op_(DC_WINC_A_V_FILTER_P02_0) \ +_op_(DC_WINC_A_V_FILTER_P03_0) \ +_op_(DC_WINC_A_V_FILTER_P04_0) \ +_op_(DC_WINC_A_V_FILTER_P05_0) \ +_op_(DC_WINC_A_V_FILTER_P06_0) \ +_op_(DC_WINC_A_V_FILTER_P07_0) \ +_op_(DC_WINC_A_V_FILTER_P08_0) \ +_op_(DC_WINC_A_V_FILTER_P09_0) \ +_op_(DC_WINC_A_V_FILTER_P0A_0) \ +_op_(DC_WINC_A_V_FILTER_P0B_0) \ +_op_(DC_WINC_A_V_FILTER_P0C_0) \ +_op_(DC_WINC_A_V_FILTER_P0D_0) \ +_op_(DC_WINC_A_V_FILTER_P0E_0) \ +_op_(DC_WINC_A_V_FILTER_P0F_0) \ +_op_(DC_WINC_A_H_FILTER_HI_P00_0) \ +_op_(DC_WINC_A_H_FILTER_HI_P01_0) \ +_op_(DC_WINC_A_H_FILTER_HI_P02_0) \ +_op_(DC_WINC_A_H_FILTER_HI_P03_0) \ +_op_(DC_WINC_A_H_FILTER_HI_P04_0) \ +_op_(DC_WINC_A_H_FILTER_HI_P05_0) \ +_op_(DC_WINC_A_H_FILTER_HI_P06_0) \ +_op_(DC_WINC_A_H_FILTER_HI_P07_0) \ +_op_(DC_WINC_A_H_FILTER_HI_P08_0) \ +_op_(DC_WINC_A_H_FILTER_HI_P09_0) \ +_op_(DC_WINC_A_H_FILTER_HI_P0A_0) \ +_op_(DC_WINC_A_H_FILTER_HI_P0B_0) \ +_op_(DC_WINC_A_H_FILTER_HI_P0C_0) \ +_op_(DC_WINC_A_H_FILTER_HI_P0D_0) \ +_op_(DC_WINC_A_H_FILTER_HI_P0E_0) \ +_op_(DC_WINC_A_H_FILTER_HI_P0F_0) \ +_op_(DC_WIN_A_WIN_OPTIONS_0) \ +_op_(DC_WIN_A_BYTE_SWAP_0) \ +_op_(DC_WIN_A_BUFFER_CONTROL_0) \ +_op_(DC_WIN_A_COLOR_DEPTH_0) \ +_op_(DC_WIN_A_POSITION_0) \ +_op_(DC_WIN_A_SIZE_0) \ +_op_(DC_WIN_A_PRESCALED_SIZE_0) \ +_op_(DC_WIN_A_H_INITIAL_DDA_0) \ +_op_(DC_WIN_A_V_INITIAL_DDA_0) \ +_op_(DC_WIN_A_DDA_INCREMENT_0) \ +_op_(DC_WIN_A_LINE_STRIDE_0) \ +_op_(DC_WIN_A_DV_CONTROL_0) \ +_op_(DC_WIN_A_BLEND_LAYER_CONTROL_0) \ +_op_(DC_WIN_A_BLEND_MATCH_SELECT_0) \ +_op_(DC_WIN_A_BLEND_NOMATCH_SELECT_0) \ +_op_(DC_WIN_A_BLEND_ALPHA_1BIT_0) \ +_op_(DC_WINBUF_A_START_ADDR_0) \ +_op_(DC_WINBUF_A_START_ADDR_NS_0) \ +_op_(DC_WINBUF_A_START_ADDR_U_0) \ +_op_(DC_WINBUF_A_START_ADDR_U_NS_0) \ +_op_(DC_WINBUF_A_START_ADDR_V_0) \ +_op_(DC_WINBUF_A_START_ADDR_V_NS_0) \ +_op_(DC_WINBUF_A_ADDR_H_OFFSET_0) \ +_op_(DC_WINBUF_A_ADDR_H_OFFSET_NS_0) \ +_op_(DC_WINBUF_A_ADDR_V_OFFSET_0) \ +_op_(DC_WINBUF_A_ADDR_V_OFFSET_NS_0) \ +_op_(DC_WINBUF_A_UFLOW_STATUS_0) \ +_op_(DC_WINBUF_A_SURFACE_KIND_0) \ +_op_(DC_WINBUF_A_SURFACE_WEIGHT_0) \ +_op_(DC_WINBUF_A_START_ADDR_HI_0) \ +_op_(DC_WINBUF_A_START_ADDR_HI_NS_0) \ +_op_(DC_WINBUF_A_START_ADDR_HI_U_0) \ +_op_(DC_WINBUF_A_START_ADDR_HI_U_NS_0) \ +_op_(DC_WINBUF_A_START_ADDR_HI_V_0) \ +_op_(DC_WINBUF_A_START_ADDR_HI_V_NS_0) \ +_op_(DC_WINBUF_A_START_ADDR_FIELD2_0) \ +_op_(DC_WINBUF_A_START_ADDR_FIELD2_NS_0) \ +_op_(DC_WINBUF_A_START_ADDR_FIELD2_U_0) \ +_op_(DC_WINBUF_A_START_ADDR_FIELD2_U_NS_0) \ +_op_(DC_WINBUF_A_START_ADDR_FIELD2_V_0) \ +_op_(DC_WINBUF_A_START_ADDR_FIELD2_V_NS_0) \ +_op_(DC_WINBUF_A_START_ADDR_FIELD2_HI_0) \ +_op_(DC_WINBUF_A_START_ADDR_FIELD2_HI_NS_0) \ +_op_(DC_WINBUF_A_START_ADDR_FIELD2_HI_U_0) \ +_op_(DC_WINBUF_A_START_ADDR_FIELD2_HI_U_NS_0) \ +_op_(DC_WINBUF_A_START_ADDR_FIELD2_HI_V_0) \ +_op_(DC_WINBUF_A_START_ADDR_FIELD2_HI_V_NS_0) \ +_op_(DC_WINBUF_A_ADDR_H_OFFSET_FIELD2_0) \ +_op_(DC_WINBUF_A_ADDR_H_OFFSET_FIELD2_NS_0) \ +_op_(DC_WINBUF_A_ADDR_V_OFFSET_FIELD2_0) \ +_op_(DC_WINBUF_A_ADDR_V_OFFSET_FIELD2_NS_0) \ +_op_(DC_WINBUF_A_UFLOW_CTRL_0) \ +_op_(DC_WINBUF_A_UFLOW_DBG_PIXEL_0) \ +_op_(DC_WINBUF_A_UFLOW_THRESHOLD_0) \ +_op_(DC_WINBUF_A_SPOOL_UP_0) \ +_op_(DC_WINBUF_A_SCALEFACTOR_THRESHOLD_0) \ +_op_(DC_WINBUF_A_LATENCY_THRESHOLD_0) \ +_op_(DC_WINBUF_A_MEMFETCH_DEBUG_STATUS_0) \ +_op_(DC_WINBUF_A_MEMFETCH_CONTROL_0) \ +_op_(DC_WINBUF_A_OCCUPANCY_THROTTLE_0) \ +_op_(DC_WINBUF_A_SCRATCH_REGISTER_0_0) \ +_op_(DC_WINBUF_A_SCRATCH_REGISTER_1_0) + + +// +// ADDRESS SPACES +// + +#define BASE_ADDRESS_DC_WINC 0x00000500 +#define BASE_ADDRESS_DC_WIN 0x00000700 +#define BASE_ADDRESS_DC_WINBUF 0x00000800 + +// +// ARDISPLAY_A REGISTER BANKS +// + +#define DC_WINC0_FIRST_REG 0x0500 // DC_WINC_A_COLOR_PALETTE_0 +#define DC_WINC0_LAST_REG 0x0638 // DC_WINC_A_H_FILTER_HI_P0F_0 +#define DC_WIN0_FIRST_REG 0x0700 // DC_WIN_A_WIN_OPTIONS_0 +#define DC_WIN0_LAST_REG 0x070a // DC_WIN_A_LINE_STRIDE_0 +#define DC_WIN1_FIRST_REG 0x070e // DC_WIN_A_DV_CONTROL_0 +#define DC_WIN1_LAST_REG 0x070e // DC_WIN_A_DV_CONTROL_0 +#define DC_WIN2_FIRST_REG 0x0716 // DC_WIN_A_BLEND_LAYER_CONTROL_0 +#define DC_WIN2_LAST_REG 0x0719 // DC_WIN_A_BLEND_ALPHA_1BIT_0 +#define DC_WINBUF0_FIRST_REG 0x0800 // DC_WINBUF_A_START_ADDR_0 +#define DC_WINBUF0_LAST_REG 0x0822 // DC_WINBUF_A_ADDR_V_OFFSET_FIELD2_NS_0 +#define DC_WINBUF1_FIRST_REG 0x0824 // DC_WINBUF_A_UFLOW_CTRL_0 +#define DC_WINBUF1_LAST_REG 0x082e // DC_WINBUF_A_SCRATCH_REGISTER_1_0 + +// To satisfy various compilers and platforms, +// we let users control the types and syntax of certain constants, using macros. +#ifndef _MK_SHIFT_CONST + #define _MK_SHIFT_CONST(_constant_) _constant_ +#endif +#ifndef _MK_MASK_CONST + #define _MK_MASK_CONST(_constant_) _constant_ +#endif +#ifndef _MK_ENUM_CONST + #define _MK_ENUM_CONST(_constant_) (_constant_ ## UL) +#endif +#ifndef _MK_ADDR_CONST + #define _MK_ADDR_CONST(_constant_) _constant_ +#endif +#ifndef _MK_FIELD_CONST + #define _MK_FIELD_CONST(_mask_, _shift_) (_MK_MASK_CONST(_mask_) << _MK_SHIFT_CONST(_shift_)) +#endif + +#endif // ifndef ___ARDISPLAY_A_H_INC_ +// +// Copyright (c) 2013 NVIDIA Corporation. +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// +// Neither the name of the NVIDIA Corporation nor the names of its contributors +// may be used to endorse or promote products derived from this software +// without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// + +// +// DO NOT EDIT - generated by simspec! +// + +#ifndef ___ARDISPLAY_BD_H_INC_ +#define ___ARDISPLAY_BD_H_INC_ + +// Ram DC_B_WINC_BD_COLOR_PALETTE_0 +#define DC_B_WINC_BD_COLOR_PALETTE_0 _MK_ADDR_CONST(0xc00) +#define DC_B_WINC_BD_COLOR_PALETTE_0_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_0_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_0_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_0_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_0_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_0_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_0_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_0_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_0_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_0_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_0_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_0_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_0_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_0_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_0_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_0_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_0_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_0_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_0_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_0_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_0_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_0_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_0_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_0_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_0_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_0_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_0_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_0_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_0_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_0_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_0_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE +#define DC_B_WINC_BD_COLOR_PALETTE _MK_ADDR_CONST(0xc00) +#define DC_B_WINC_BD_COLOR_PALETTE_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_1 +#define DC_B_WINC_BD_COLOR_PALETTE_1 _MK_ADDR_CONST(0xc01) +#define DC_B_WINC_BD_COLOR_PALETTE_1_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_1_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_1_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_1_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_1_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_1_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_1_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_1_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_1_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_1_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_1_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_1_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_1_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_1_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_1_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_1_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_1_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_1_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_1_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_1_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_1_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_1_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_1_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_1_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_1_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_1_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_1_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_1_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_1_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_1_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_1_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_1_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_1_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_1_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_1_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_2 +#define DC_B_WINC_BD_COLOR_PALETTE_2 _MK_ADDR_CONST(0xc02) +#define DC_B_WINC_BD_COLOR_PALETTE_2_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_2_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_2_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_2_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_2_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_2_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_2_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_2_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_2_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_2_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_2_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_2_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_2_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_2_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_2_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_2_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_2_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_2_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_2_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_2_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_2_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_2_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_2_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_2_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_2_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_2_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_2_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_2_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_2_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_2_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_2_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_2_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_2_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_2_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_2_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_3 +#define DC_B_WINC_BD_COLOR_PALETTE_3 _MK_ADDR_CONST(0xc03) +#define DC_B_WINC_BD_COLOR_PALETTE_3_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_3_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_3_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_3_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_3_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_3_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_3_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_3_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_3_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_3_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_3_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_3_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_3_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_3_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_3_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_3_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_3_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_3_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_3_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_3_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_3_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_3_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_3_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_3_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_3_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_3_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_3_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_3_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_3_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_3_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_3_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_3_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_3_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_3_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_3_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_4 +#define DC_B_WINC_BD_COLOR_PALETTE_4 _MK_ADDR_CONST(0xc04) +#define DC_B_WINC_BD_COLOR_PALETTE_4_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_4_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_4_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_4_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_4_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_4_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_4_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_4_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_4_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_4_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_4_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_4_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_4_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_4_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_4_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_4_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_4_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_4_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_4_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_4_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_4_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_4_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_4_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_4_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_4_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_4_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_4_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_4_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_4_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_4_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_4_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_4_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_4_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_4_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_4_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_5 +#define DC_B_WINC_BD_COLOR_PALETTE_5 _MK_ADDR_CONST(0xc05) +#define DC_B_WINC_BD_COLOR_PALETTE_5_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_5_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_5_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_5_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_5_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_5_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_5_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_5_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_5_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_5_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_5_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_5_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_5_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_5_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_5_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_5_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_5_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_5_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_5_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_5_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_5_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_5_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_5_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_5_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_5_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_5_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_5_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_5_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_5_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_5_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_5_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_5_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_5_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_5_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_5_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_6 +#define DC_B_WINC_BD_COLOR_PALETTE_6 _MK_ADDR_CONST(0xc06) +#define DC_B_WINC_BD_COLOR_PALETTE_6_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_6_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_6_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_6_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_6_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_6_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_6_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_6_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_6_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_6_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_6_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_6_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_6_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_6_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_6_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_6_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_6_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_6_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_6_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_6_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_6_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_6_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_6_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_6_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_6_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_6_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_6_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_6_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_6_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_6_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_6_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_6_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_6_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_6_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_6_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_7 +#define DC_B_WINC_BD_COLOR_PALETTE_7 _MK_ADDR_CONST(0xc07) +#define DC_B_WINC_BD_COLOR_PALETTE_7_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_7_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_7_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_7_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_7_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_7_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_7_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_7_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_7_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_7_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_7_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_7_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_7_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_7_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_7_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_7_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_7_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_7_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_7_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_7_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_7_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_7_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_7_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_7_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_7_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_7_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_7_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_7_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_7_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_7_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_7_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_7_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_7_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_7_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_7_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_8 +#define DC_B_WINC_BD_COLOR_PALETTE_8 _MK_ADDR_CONST(0xc08) +#define DC_B_WINC_BD_COLOR_PALETTE_8_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_8_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_8_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_8_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_8_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_8_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_8_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_8_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_8_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_8_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_8_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_8_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_8_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_8_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_8_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_8_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_8_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_8_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_8_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_8_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_8_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_8_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_8_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_8_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_8_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_8_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_8_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_8_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_8_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_8_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_8_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_8_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_8_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_8_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_8_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_9 +#define DC_B_WINC_BD_COLOR_PALETTE_9 _MK_ADDR_CONST(0xc09) +#define DC_B_WINC_BD_COLOR_PALETTE_9_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_9_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_9_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_9_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_9_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_9_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_9_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_9_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_9_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_9_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_9_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_9_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_9_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_9_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_9_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_9_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_9_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_9_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_9_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_9_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_9_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_9_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_9_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_9_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_9_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_9_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_9_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_9_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_9_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_9_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_9_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_9_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_9_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_9_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_9_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_10 +#define DC_B_WINC_BD_COLOR_PALETTE_10 _MK_ADDR_CONST(0xc0a) +#define DC_B_WINC_BD_COLOR_PALETTE_10_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_10_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_10_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_10_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_10_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_10_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_10_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_10_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_10_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_10_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_10_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_10_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_10_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_10_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_10_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_10_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_10_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_10_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_10_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_10_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_10_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_10_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_10_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_10_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_10_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_10_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_10_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_10_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_10_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_10_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_10_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_10_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_10_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_10_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_10_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_11 +#define DC_B_WINC_BD_COLOR_PALETTE_11 _MK_ADDR_CONST(0xc0b) +#define DC_B_WINC_BD_COLOR_PALETTE_11_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_11_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_11_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_11_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_11_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_11_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_11_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_11_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_11_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_11_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_11_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_11_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_11_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_11_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_11_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_11_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_11_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_11_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_11_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_11_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_11_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_11_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_11_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_11_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_11_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_11_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_11_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_11_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_11_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_11_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_11_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_11_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_11_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_11_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_11_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_12 +#define DC_B_WINC_BD_COLOR_PALETTE_12 _MK_ADDR_CONST(0xc0c) +#define DC_B_WINC_BD_COLOR_PALETTE_12_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_12_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_12_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_12_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_12_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_12_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_12_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_12_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_12_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_12_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_12_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_12_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_12_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_12_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_12_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_12_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_12_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_12_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_12_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_12_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_12_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_12_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_12_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_12_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_12_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_12_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_12_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_12_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_12_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_12_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_12_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_12_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_12_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_12_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_12_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_13 +#define DC_B_WINC_BD_COLOR_PALETTE_13 _MK_ADDR_CONST(0xc0d) +#define DC_B_WINC_BD_COLOR_PALETTE_13_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_13_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_13_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_13_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_13_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_13_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_13_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_13_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_13_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_13_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_13_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_13_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_13_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_13_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_13_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_13_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_13_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_13_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_13_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_13_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_13_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_13_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_13_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_13_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_13_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_13_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_13_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_13_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_13_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_13_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_13_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_13_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_13_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_13_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_13_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_14 +#define DC_B_WINC_BD_COLOR_PALETTE_14 _MK_ADDR_CONST(0xc0e) +#define DC_B_WINC_BD_COLOR_PALETTE_14_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_14_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_14_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_14_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_14_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_14_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_14_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_14_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_14_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_14_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_14_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_14_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_14_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_14_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_14_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_14_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_14_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_14_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_14_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_14_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_14_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_14_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_14_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_14_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_14_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_14_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_14_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_14_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_14_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_14_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_14_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_14_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_14_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_14_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_14_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_15 +#define DC_B_WINC_BD_COLOR_PALETTE_15 _MK_ADDR_CONST(0xc0f) +#define DC_B_WINC_BD_COLOR_PALETTE_15_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_15_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_15_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_15_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_15_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_15_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_15_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_15_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_15_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_15_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_15_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_15_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_15_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_15_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_15_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_15_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_15_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_15_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_15_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_15_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_15_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_15_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_15_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_15_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_15_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_15_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_15_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_15_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_15_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_15_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_15_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_15_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_15_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_15_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_15_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_16 +#define DC_B_WINC_BD_COLOR_PALETTE_16 _MK_ADDR_CONST(0xc10) +#define DC_B_WINC_BD_COLOR_PALETTE_16_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_16_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_16_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_16_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_16_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_16_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_16_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_16_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_16_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_16_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_16_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_16_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_16_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_16_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_16_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_16_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_16_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_16_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_16_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_16_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_16_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_16_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_16_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_16_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_16_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_16_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_16_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_16_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_16_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_16_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_16_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_16_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_16_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_16_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_16_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_17 +#define DC_B_WINC_BD_COLOR_PALETTE_17 _MK_ADDR_CONST(0xc11) +#define DC_B_WINC_BD_COLOR_PALETTE_17_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_17_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_17_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_17_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_17_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_17_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_17_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_17_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_17_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_17_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_17_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_17_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_17_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_17_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_17_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_17_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_17_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_17_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_17_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_17_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_17_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_17_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_17_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_17_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_17_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_17_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_17_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_17_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_17_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_17_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_17_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_17_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_17_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_17_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_17_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_18 +#define DC_B_WINC_BD_COLOR_PALETTE_18 _MK_ADDR_CONST(0xc12) +#define DC_B_WINC_BD_COLOR_PALETTE_18_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_18_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_18_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_18_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_18_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_18_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_18_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_18_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_18_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_18_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_18_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_18_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_18_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_18_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_18_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_18_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_18_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_18_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_18_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_18_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_18_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_18_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_18_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_18_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_18_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_18_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_18_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_18_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_18_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_18_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_18_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_18_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_18_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_18_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_18_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_19 +#define DC_B_WINC_BD_COLOR_PALETTE_19 _MK_ADDR_CONST(0xc13) +#define DC_B_WINC_BD_COLOR_PALETTE_19_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_19_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_19_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_19_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_19_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_19_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_19_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_19_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_19_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_19_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_19_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_19_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_19_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_19_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_19_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_19_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_19_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_19_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_19_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_19_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_19_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_19_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_19_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_19_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_19_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_19_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_19_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_19_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_19_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_19_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_19_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_19_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_19_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_19_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_19_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_20 +#define DC_B_WINC_BD_COLOR_PALETTE_20 _MK_ADDR_CONST(0xc14) +#define DC_B_WINC_BD_COLOR_PALETTE_20_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_20_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_20_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_20_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_20_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_20_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_20_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_20_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_20_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_20_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_20_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_20_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_20_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_20_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_20_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_20_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_20_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_20_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_20_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_20_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_20_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_20_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_20_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_20_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_20_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_20_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_20_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_20_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_20_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_20_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_20_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_20_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_20_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_20_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_20_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_21 +#define DC_B_WINC_BD_COLOR_PALETTE_21 _MK_ADDR_CONST(0xc15) +#define DC_B_WINC_BD_COLOR_PALETTE_21_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_21_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_21_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_21_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_21_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_21_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_21_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_21_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_21_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_21_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_21_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_21_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_21_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_21_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_21_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_21_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_21_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_21_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_21_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_21_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_21_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_21_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_21_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_21_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_21_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_21_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_21_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_21_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_21_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_21_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_21_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_21_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_21_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_21_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_21_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_22 +#define DC_B_WINC_BD_COLOR_PALETTE_22 _MK_ADDR_CONST(0xc16) +#define DC_B_WINC_BD_COLOR_PALETTE_22_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_22_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_22_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_22_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_22_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_22_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_22_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_22_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_22_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_22_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_22_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_22_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_22_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_22_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_22_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_22_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_22_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_22_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_22_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_22_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_22_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_22_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_22_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_22_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_22_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_22_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_22_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_22_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_22_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_22_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_22_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_22_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_22_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_22_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_22_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_23 +#define DC_B_WINC_BD_COLOR_PALETTE_23 _MK_ADDR_CONST(0xc17) +#define DC_B_WINC_BD_COLOR_PALETTE_23_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_23_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_23_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_23_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_23_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_23_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_23_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_23_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_23_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_23_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_23_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_23_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_23_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_23_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_23_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_23_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_23_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_23_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_23_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_23_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_23_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_23_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_23_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_23_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_23_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_23_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_23_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_23_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_23_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_23_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_23_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_23_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_23_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_23_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_23_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_24 +#define DC_B_WINC_BD_COLOR_PALETTE_24 _MK_ADDR_CONST(0xc18) +#define DC_B_WINC_BD_COLOR_PALETTE_24_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_24_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_24_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_24_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_24_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_24_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_24_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_24_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_24_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_24_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_24_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_24_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_24_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_24_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_24_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_24_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_24_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_24_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_24_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_24_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_24_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_24_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_24_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_24_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_24_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_24_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_24_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_24_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_24_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_24_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_24_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_24_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_24_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_24_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_24_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_25 +#define DC_B_WINC_BD_COLOR_PALETTE_25 _MK_ADDR_CONST(0xc19) +#define DC_B_WINC_BD_COLOR_PALETTE_25_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_25_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_25_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_25_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_25_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_25_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_25_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_25_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_25_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_25_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_25_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_25_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_25_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_25_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_25_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_25_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_25_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_25_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_25_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_25_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_25_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_25_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_25_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_25_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_25_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_25_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_25_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_25_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_25_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_25_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_25_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_25_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_25_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_25_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_25_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_26 +#define DC_B_WINC_BD_COLOR_PALETTE_26 _MK_ADDR_CONST(0xc1a) +#define DC_B_WINC_BD_COLOR_PALETTE_26_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_26_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_26_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_26_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_26_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_26_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_26_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_26_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_26_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_26_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_26_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_26_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_26_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_26_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_26_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_26_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_26_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_26_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_26_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_26_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_26_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_26_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_26_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_26_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_26_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_26_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_26_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_26_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_26_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_26_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_26_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_26_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_26_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_26_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_26_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_27 +#define DC_B_WINC_BD_COLOR_PALETTE_27 _MK_ADDR_CONST(0xc1b) +#define DC_B_WINC_BD_COLOR_PALETTE_27_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_27_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_27_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_27_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_27_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_27_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_27_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_27_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_27_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_27_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_27_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_27_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_27_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_27_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_27_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_27_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_27_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_27_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_27_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_27_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_27_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_27_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_27_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_27_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_27_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_27_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_27_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_27_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_27_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_27_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_27_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_27_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_27_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_27_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_27_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_28 +#define DC_B_WINC_BD_COLOR_PALETTE_28 _MK_ADDR_CONST(0xc1c) +#define DC_B_WINC_BD_COLOR_PALETTE_28_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_28_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_28_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_28_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_28_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_28_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_28_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_28_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_28_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_28_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_28_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_28_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_28_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_28_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_28_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_28_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_28_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_28_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_28_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_28_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_28_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_28_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_28_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_28_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_28_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_28_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_28_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_28_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_28_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_28_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_28_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_28_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_28_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_28_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_28_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_29 +#define DC_B_WINC_BD_COLOR_PALETTE_29 _MK_ADDR_CONST(0xc1d) +#define DC_B_WINC_BD_COLOR_PALETTE_29_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_29_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_29_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_29_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_29_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_29_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_29_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_29_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_29_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_29_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_29_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_29_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_29_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_29_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_29_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_29_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_29_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_29_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_29_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_29_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_29_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_29_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_29_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_29_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_29_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_29_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_29_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_29_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_29_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_29_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_29_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_29_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_29_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_29_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_29_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_30 +#define DC_B_WINC_BD_COLOR_PALETTE_30 _MK_ADDR_CONST(0xc1e) +#define DC_B_WINC_BD_COLOR_PALETTE_30_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_30_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_30_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_30_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_30_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_30_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_30_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_30_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_30_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_30_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_30_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_30_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_30_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_30_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_30_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_30_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_30_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_30_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_30_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_30_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_30_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_30_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_30_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_30_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_30_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_30_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_30_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_30_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_30_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_30_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_30_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_30_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_30_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_30_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_30_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_31 +#define DC_B_WINC_BD_COLOR_PALETTE_31 _MK_ADDR_CONST(0xc1f) +#define DC_B_WINC_BD_COLOR_PALETTE_31_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_31_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_31_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_31_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_31_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_31_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_31_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_31_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_31_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_31_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_31_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_31_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_31_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_31_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_31_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_31_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_31_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_31_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_31_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_31_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_31_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_31_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_31_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_31_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_31_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_31_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_31_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_31_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_31_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_31_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_31_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_31_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_31_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_31_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_31_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_32 +#define DC_B_WINC_BD_COLOR_PALETTE_32 _MK_ADDR_CONST(0xc20) +#define DC_B_WINC_BD_COLOR_PALETTE_32_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_32_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_32_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_32_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_32_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_32_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_32_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_32_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_32_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_32_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_32_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_32_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_32_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_32_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_32_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_32_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_32_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_32_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_32_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_32_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_32_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_32_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_32_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_32_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_32_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_32_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_32_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_32_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_32_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_32_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_32_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_32_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_32_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_32_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_32_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_33 +#define DC_B_WINC_BD_COLOR_PALETTE_33 _MK_ADDR_CONST(0xc21) +#define DC_B_WINC_BD_COLOR_PALETTE_33_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_33_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_33_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_33_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_33_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_33_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_33_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_33_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_33_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_33_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_33_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_33_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_33_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_33_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_33_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_33_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_33_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_33_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_33_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_33_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_33_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_33_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_33_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_33_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_33_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_33_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_33_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_33_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_33_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_33_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_33_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_33_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_33_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_33_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_33_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_34 +#define DC_B_WINC_BD_COLOR_PALETTE_34 _MK_ADDR_CONST(0xc22) +#define DC_B_WINC_BD_COLOR_PALETTE_34_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_34_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_34_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_34_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_34_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_34_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_34_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_34_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_34_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_34_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_34_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_34_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_34_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_34_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_34_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_34_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_34_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_34_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_34_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_34_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_34_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_34_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_34_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_34_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_34_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_34_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_34_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_34_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_34_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_34_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_34_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_34_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_34_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_34_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_34_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_35 +#define DC_B_WINC_BD_COLOR_PALETTE_35 _MK_ADDR_CONST(0xc23) +#define DC_B_WINC_BD_COLOR_PALETTE_35_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_35_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_35_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_35_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_35_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_35_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_35_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_35_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_35_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_35_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_35_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_35_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_35_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_35_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_35_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_35_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_35_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_35_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_35_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_35_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_35_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_35_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_35_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_35_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_35_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_35_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_35_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_35_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_35_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_35_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_35_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_35_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_35_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_35_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_35_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_36 +#define DC_B_WINC_BD_COLOR_PALETTE_36 _MK_ADDR_CONST(0xc24) +#define DC_B_WINC_BD_COLOR_PALETTE_36_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_36_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_36_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_36_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_36_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_36_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_36_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_36_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_36_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_36_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_36_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_36_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_36_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_36_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_36_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_36_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_36_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_36_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_36_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_36_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_36_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_36_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_36_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_36_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_36_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_36_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_36_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_36_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_36_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_36_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_36_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_36_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_36_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_36_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_36_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_37 +#define DC_B_WINC_BD_COLOR_PALETTE_37 _MK_ADDR_CONST(0xc25) +#define DC_B_WINC_BD_COLOR_PALETTE_37_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_37_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_37_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_37_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_37_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_37_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_37_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_37_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_37_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_37_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_37_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_37_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_37_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_37_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_37_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_37_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_37_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_37_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_37_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_37_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_37_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_37_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_37_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_37_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_37_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_37_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_37_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_37_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_37_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_37_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_37_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_37_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_37_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_37_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_37_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_38 +#define DC_B_WINC_BD_COLOR_PALETTE_38 _MK_ADDR_CONST(0xc26) +#define DC_B_WINC_BD_COLOR_PALETTE_38_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_38_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_38_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_38_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_38_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_38_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_38_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_38_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_38_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_38_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_38_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_38_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_38_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_38_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_38_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_38_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_38_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_38_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_38_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_38_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_38_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_38_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_38_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_38_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_38_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_38_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_38_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_38_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_38_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_38_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_38_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_38_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_38_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_38_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_38_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_39 +#define DC_B_WINC_BD_COLOR_PALETTE_39 _MK_ADDR_CONST(0xc27) +#define DC_B_WINC_BD_COLOR_PALETTE_39_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_39_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_39_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_39_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_39_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_39_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_39_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_39_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_39_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_39_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_39_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_39_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_39_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_39_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_39_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_39_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_39_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_39_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_39_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_39_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_39_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_39_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_39_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_39_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_39_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_39_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_39_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_39_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_39_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_39_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_39_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_39_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_39_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_39_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_39_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_40 +#define DC_B_WINC_BD_COLOR_PALETTE_40 _MK_ADDR_CONST(0xc28) +#define DC_B_WINC_BD_COLOR_PALETTE_40_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_40_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_40_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_40_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_40_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_40_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_40_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_40_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_40_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_40_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_40_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_40_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_40_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_40_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_40_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_40_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_40_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_40_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_40_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_40_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_40_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_40_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_40_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_40_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_40_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_40_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_40_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_40_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_40_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_40_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_40_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_40_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_40_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_40_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_40_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_41 +#define DC_B_WINC_BD_COLOR_PALETTE_41 _MK_ADDR_CONST(0xc29) +#define DC_B_WINC_BD_COLOR_PALETTE_41_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_41_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_41_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_41_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_41_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_41_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_41_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_41_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_41_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_41_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_41_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_41_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_41_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_41_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_41_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_41_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_41_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_41_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_41_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_41_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_41_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_41_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_41_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_41_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_41_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_41_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_41_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_41_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_41_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_41_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_41_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_41_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_41_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_41_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_41_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_42 +#define DC_B_WINC_BD_COLOR_PALETTE_42 _MK_ADDR_CONST(0xc2a) +#define DC_B_WINC_BD_COLOR_PALETTE_42_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_42_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_42_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_42_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_42_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_42_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_42_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_42_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_42_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_42_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_42_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_42_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_42_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_42_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_42_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_42_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_42_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_42_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_42_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_42_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_42_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_42_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_42_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_42_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_42_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_42_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_42_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_42_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_42_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_42_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_42_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_42_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_42_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_42_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_42_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_43 +#define DC_B_WINC_BD_COLOR_PALETTE_43 _MK_ADDR_CONST(0xc2b) +#define DC_B_WINC_BD_COLOR_PALETTE_43_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_43_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_43_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_43_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_43_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_43_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_43_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_43_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_43_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_43_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_43_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_43_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_43_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_43_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_43_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_43_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_43_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_43_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_43_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_43_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_43_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_43_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_43_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_43_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_43_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_43_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_43_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_43_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_43_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_43_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_43_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_43_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_43_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_43_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_43_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_44 +#define DC_B_WINC_BD_COLOR_PALETTE_44 _MK_ADDR_CONST(0xc2c) +#define DC_B_WINC_BD_COLOR_PALETTE_44_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_44_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_44_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_44_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_44_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_44_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_44_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_44_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_44_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_44_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_44_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_44_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_44_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_44_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_44_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_44_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_44_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_44_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_44_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_44_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_44_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_44_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_44_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_44_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_44_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_44_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_44_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_44_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_44_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_44_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_44_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_44_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_44_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_44_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_44_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_45 +#define DC_B_WINC_BD_COLOR_PALETTE_45 _MK_ADDR_CONST(0xc2d) +#define DC_B_WINC_BD_COLOR_PALETTE_45_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_45_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_45_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_45_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_45_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_45_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_45_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_45_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_45_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_45_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_45_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_45_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_45_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_45_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_45_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_45_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_45_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_45_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_45_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_45_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_45_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_45_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_45_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_45_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_45_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_45_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_45_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_45_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_45_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_45_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_45_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_45_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_45_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_45_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_45_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_46 +#define DC_B_WINC_BD_COLOR_PALETTE_46 _MK_ADDR_CONST(0xc2e) +#define DC_B_WINC_BD_COLOR_PALETTE_46_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_46_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_46_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_46_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_46_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_46_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_46_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_46_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_46_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_46_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_46_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_46_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_46_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_46_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_46_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_46_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_46_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_46_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_46_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_46_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_46_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_46_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_46_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_46_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_46_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_46_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_46_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_46_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_46_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_46_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_46_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_46_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_46_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_46_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_46_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_47 +#define DC_B_WINC_BD_COLOR_PALETTE_47 _MK_ADDR_CONST(0xc2f) +#define DC_B_WINC_BD_COLOR_PALETTE_47_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_47_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_47_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_47_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_47_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_47_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_47_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_47_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_47_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_47_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_47_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_47_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_47_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_47_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_47_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_47_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_47_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_47_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_47_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_47_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_47_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_47_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_47_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_47_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_47_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_47_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_47_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_47_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_47_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_47_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_47_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_47_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_47_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_47_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_47_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_48 +#define DC_B_WINC_BD_COLOR_PALETTE_48 _MK_ADDR_CONST(0xc30) +#define DC_B_WINC_BD_COLOR_PALETTE_48_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_48_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_48_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_48_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_48_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_48_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_48_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_48_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_48_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_48_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_48_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_48_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_48_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_48_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_48_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_48_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_48_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_48_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_48_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_48_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_48_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_48_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_48_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_48_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_48_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_48_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_48_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_48_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_48_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_48_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_48_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_48_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_48_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_48_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_48_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_49 +#define DC_B_WINC_BD_COLOR_PALETTE_49 _MK_ADDR_CONST(0xc31) +#define DC_B_WINC_BD_COLOR_PALETTE_49_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_49_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_49_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_49_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_49_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_49_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_49_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_49_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_49_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_49_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_49_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_49_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_49_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_49_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_49_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_49_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_49_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_49_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_49_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_49_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_49_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_49_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_49_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_49_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_49_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_49_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_49_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_49_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_49_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_49_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_49_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_49_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_49_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_49_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_49_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_50 +#define DC_B_WINC_BD_COLOR_PALETTE_50 _MK_ADDR_CONST(0xc32) +#define DC_B_WINC_BD_COLOR_PALETTE_50_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_50_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_50_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_50_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_50_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_50_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_50_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_50_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_50_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_50_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_50_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_50_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_50_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_50_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_50_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_50_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_50_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_50_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_50_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_50_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_50_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_50_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_50_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_50_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_50_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_50_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_50_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_50_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_50_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_50_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_50_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_50_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_50_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_50_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_50_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_51 +#define DC_B_WINC_BD_COLOR_PALETTE_51 _MK_ADDR_CONST(0xc33) +#define DC_B_WINC_BD_COLOR_PALETTE_51_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_51_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_51_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_51_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_51_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_51_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_51_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_51_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_51_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_51_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_51_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_51_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_51_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_51_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_51_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_51_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_51_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_51_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_51_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_51_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_51_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_51_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_51_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_51_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_51_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_51_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_51_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_51_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_51_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_51_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_51_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_51_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_51_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_51_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_51_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_52 +#define DC_B_WINC_BD_COLOR_PALETTE_52 _MK_ADDR_CONST(0xc34) +#define DC_B_WINC_BD_COLOR_PALETTE_52_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_52_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_52_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_52_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_52_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_52_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_52_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_52_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_52_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_52_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_52_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_52_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_52_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_52_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_52_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_52_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_52_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_52_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_52_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_52_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_52_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_52_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_52_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_52_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_52_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_52_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_52_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_52_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_52_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_52_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_52_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_52_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_52_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_52_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_52_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_53 +#define DC_B_WINC_BD_COLOR_PALETTE_53 _MK_ADDR_CONST(0xc35) +#define DC_B_WINC_BD_COLOR_PALETTE_53_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_53_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_53_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_53_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_53_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_53_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_53_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_53_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_53_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_53_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_53_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_53_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_53_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_53_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_53_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_53_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_53_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_53_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_53_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_53_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_53_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_53_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_53_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_53_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_53_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_53_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_53_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_53_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_53_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_53_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_53_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_53_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_53_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_53_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_53_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_54 +#define DC_B_WINC_BD_COLOR_PALETTE_54 _MK_ADDR_CONST(0xc36) +#define DC_B_WINC_BD_COLOR_PALETTE_54_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_54_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_54_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_54_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_54_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_54_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_54_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_54_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_54_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_54_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_54_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_54_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_54_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_54_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_54_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_54_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_54_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_54_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_54_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_54_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_54_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_54_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_54_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_54_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_54_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_54_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_54_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_54_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_54_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_54_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_54_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_54_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_54_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_54_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_54_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_55 +#define DC_B_WINC_BD_COLOR_PALETTE_55 _MK_ADDR_CONST(0xc37) +#define DC_B_WINC_BD_COLOR_PALETTE_55_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_55_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_55_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_55_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_55_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_55_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_55_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_55_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_55_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_55_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_55_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_55_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_55_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_55_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_55_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_55_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_55_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_55_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_55_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_55_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_55_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_55_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_55_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_55_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_55_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_55_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_55_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_55_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_55_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_55_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_55_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_55_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_55_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_55_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_55_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_56 +#define DC_B_WINC_BD_COLOR_PALETTE_56 _MK_ADDR_CONST(0xc38) +#define DC_B_WINC_BD_COLOR_PALETTE_56_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_56_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_56_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_56_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_56_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_56_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_56_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_56_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_56_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_56_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_56_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_56_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_56_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_56_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_56_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_56_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_56_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_56_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_56_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_56_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_56_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_56_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_56_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_56_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_56_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_56_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_56_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_56_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_56_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_56_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_56_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_56_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_56_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_56_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_56_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_57 +#define DC_B_WINC_BD_COLOR_PALETTE_57 _MK_ADDR_CONST(0xc39) +#define DC_B_WINC_BD_COLOR_PALETTE_57_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_57_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_57_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_57_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_57_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_57_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_57_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_57_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_57_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_57_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_57_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_57_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_57_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_57_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_57_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_57_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_57_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_57_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_57_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_57_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_57_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_57_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_57_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_57_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_57_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_57_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_57_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_57_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_57_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_57_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_57_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_57_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_57_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_57_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_57_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_58 +#define DC_B_WINC_BD_COLOR_PALETTE_58 _MK_ADDR_CONST(0xc3a) +#define DC_B_WINC_BD_COLOR_PALETTE_58_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_58_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_58_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_58_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_58_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_58_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_58_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_58_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_58_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_58_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_58_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_58_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_58_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_58_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_58_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_58_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_58_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_58_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_58_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_58_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_58_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_58_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_58_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_58_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_58_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_58_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_58_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_58_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_58_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_58_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_58_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_58_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_58_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_58_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_58_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_59 +#define DC_B_WINC_BD_COLOR_PALETTE_59 _MK_ADDR_CONST(0xc3b) +#define DC_B_WINC_BD_COLOR_PALETTE_59_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_59_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_59_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_59_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_59_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_59_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_59_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_59_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_59_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_59_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_59_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_59_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_59_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_59_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_59_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_59_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_59_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_59_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_59_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_59_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_59_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_59_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_59_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_59_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_59_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_59_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_59_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_59_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_59_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_59_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_59_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_59_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_59_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_59_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_59_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_60 +#define DC_B_WINC_BD_COLOR_PALETTE_60 _MK_ADDR_CONST(0xc3c) +#define DC_B_WINC_BD_COLOR_PALETTE_60_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_60_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_60_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_60_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_60_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_60_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_60_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_60_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_60_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_60_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_60_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_60_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_60_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_60_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_60_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_60_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_60_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_60_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_60_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_60_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_60_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_60_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_60_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_60_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_60_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_60_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_60_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_60_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_60_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_60_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_60_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_60_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_60_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_60_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_60_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_61 +#define DC_B_WINC_BD_COLOR_PALETTE_61 _MK_ADDR_CONST(0xc3d) +#define DC_B_WINC_BD_COLOR_PALETTE_61_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_61_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_61_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_61_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_61_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_61_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_61_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_61_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_61_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_61_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_61_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_61_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_61_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_61_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_61_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_61_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_61_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_61_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_61_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_61_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_61_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_61_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_61_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_61_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_61_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_61_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_61_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_61_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_61_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_61_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_61_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_61_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_61_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_61_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_61_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_62 +#define DC_B_WINC_BD_COLOR_PALETTE_62 _MK_ADDR_CONST(0xc3e) +#define DC_B_WINC_BD_COLOR_PALETTE_62_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_62_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_62_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_62_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_62_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_62_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_62_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_62_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_62_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_62_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_62_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_62_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_62_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_62_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_62_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_62_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_62_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_62_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_62_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_62_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_62_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_62_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_62_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_62_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_62_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_62_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_62_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_62_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_62_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_62_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_62_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_62_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_62_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_62_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_62_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_63 +#define DC_B_WINC_BD_COLOR_PALETTE_63 _MK_ADDR_CONST(0xc3f) +#define DC_B_WINC_BD_COLOR_PALETTE_63_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_63_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_63_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_63_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_63_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_63_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_63_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_63_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_63_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_63_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_63_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_63_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_63_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_63_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_63_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_63_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_63_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_63_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_63_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_63_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_63_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_63_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_63_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_63_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_63_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_63_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_63_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_63_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_63_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_63_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_63_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_63_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_63_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_63_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_63_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_64 +#define DC_B_WINC_BD_COLOR_PALETTE_64 _MK_ADDR_CONST(0xc40) +#define DC_B_WINC_BD_COLOR_PALETTE_64_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_64_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_64_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_64_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_64_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_64_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_64_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_64_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_64_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_64_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_64_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_64_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_64_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_64_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_64_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_64_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_64_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_64_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_64_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_64_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_64_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_64_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_64_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_64_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_64_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_64_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_64_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_64_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_64_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_64_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_64_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_64_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_64_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_64_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_64_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_65 +#define DC_B_WINC_BD_COLOR_PALETTE_65 _MK_ADDR_CONST(0xc41) +#define DC_B_WINC_BD_COLOR_PALETTE_65_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_65_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_65_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_65_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_65_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_65_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_65_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_65_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_65_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_65_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_65_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_65_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_65_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_65_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_65_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_65_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_65_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_65_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_65_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_65_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_65_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_65_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_65_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_65_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_65_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_65_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_65_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_65_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_65_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_65_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_65_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_65_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_65_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_65_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_65_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_66 +#define DC_B_WINC_BD_COLOR_PALETTE_66 _MK_ADDR_CONST(0xc42) +#define DC_B_WINC_BD_COLOR_PALETTE_66_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_66_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_66_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_66_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_66_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_66_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_66_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_66_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_66_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_66_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_66_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_66_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_66_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_66_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_66_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_66_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_66_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_66_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_66_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_66_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_66_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_66_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_66_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_66_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_66_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_66_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_66_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_66_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_66_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_66_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_66_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_66_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_66_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_66_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_66_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_67 +#define DC_B_WINC_BD_COLOR_PALETTE_67 _MK_ADDR_CONST(0xc43) +#define DC_B_WINC_BD_COLOR_PALETTE_67_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_67_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_67_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_67_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_67_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_67_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_67_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_67_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_67_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_67_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_67_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_67_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_67_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_67_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_67_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_67_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_67_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_67_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_67_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_67_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_67_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_67_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_67_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_67_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_67_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_67_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_67_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_67_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_67_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_67_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_67_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_67_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_67_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_67_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_67_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_68 +#define DC_B_WINC_BD_COLOR_PALETTE_68 _MK_ADDR_CONST(0xc44) +#define DC_B_WINC_BD_COLOR_PALETTE_68_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_68_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_68_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_68_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_68_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_68_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_68_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_68_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_68_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_68_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_68_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_68_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_68_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_68_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_68_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_68_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_68_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_68_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_68_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_68_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_68_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_68_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_68_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_68_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_68_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_68_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_68_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_68_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_68_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_68_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_68_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_68_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_68_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_68_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_68_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_69 +#define DC_B_WINC_BD_COLOR_PALETTE_69 _MK_ADDR_CONST(0xc45) +#define DC_B_WINC_BD_COLOR_PALETTE_69_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_69_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_69_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_69_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_69_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_69_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_69_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_69_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_69_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_69_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_69_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_69_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_69_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_69_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_69_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_69_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_69_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_69_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_69_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_69_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_69_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_69_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_69_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_69_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_69_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_69_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_69_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_69_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_69_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_69_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_69_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_69_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_69_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_69_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_69_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_70 +#define DC_B_WINC_BD_COLOR_PALETTE_70 _MK_ADDR_CONST(0xc46) +#define DC_B_WINC_BD_COLOR_PALETTE_70_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_70_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_70_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_70_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_70_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_70_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_70_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_70_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_70_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_70_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_70_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_70_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_70_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_70_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_70_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_70_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_70_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_70_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_70_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_70_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_70_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_70_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_70_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_70_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_70_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_70_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_70_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_70_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_70_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_70_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_70_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_70_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_70_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_70_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_70_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_71 +#define DC_B_WINC_BD_COLOR_PALETTE_71 _MK_ADDR_CONST(0xc47) +#define DC_B_WINC_BD_COLOR_PALETTE_71_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_71_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_71_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_71_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_71_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_71_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_71_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_71_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_71_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_71_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_71_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_71_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_71_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_71_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_71_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_71_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_71_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_71_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_71_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_71_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_71_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_71_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_71_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_71_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_71_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_71_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_71_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_71_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_71_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_71_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_71_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_71_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_71_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_71_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_71_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_72 +#define DC_B_WINC_BD_COLOR_PALETTE_72 _MK_ADDR_CONST(0xc48) +#define DC_B_WINC_BD_COLOR_PALETTE_72_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_72_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_72_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_72_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_72_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_72_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_72_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_72_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_72_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_72_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_72_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_72_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_72_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_72_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_72_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_72_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_72_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_72_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_72_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_72_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_72_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_72_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_72_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_72_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_72_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_72_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_72_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_72_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_72_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_72_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_72_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_72_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_72_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_72_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_72_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_73 +#define DC_B_WINC_BD_COLOR_PALETTE_73 _MK_ADDR_CONST(0xc49) +#define DC_B_WINC_BD_COLOR_PALETTE_73_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_73_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_73_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_73_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_73_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_73_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_73_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_73_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_73_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_73_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_73_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_73_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_73_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_73_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_73_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_73_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_73_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_73_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_73_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_73_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_73_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_73_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_73_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_73_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_73_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_73_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_73_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_73_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_73_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_73_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_73_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_73_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_73_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_73_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_73_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_74 +#define DC_B_WINC_BD_COLOR_PALETTE_74 _MK_ADDR_CONST(0xc4a) +#define DC_B_WINC_BD_COLOR_PALETTE_74_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_74_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_74_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_74_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_74_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_74_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_74_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_74_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_74_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_74_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_74_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_74_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_74_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_74_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_74_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_74_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_74_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_74_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_74_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_74_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_74_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_74_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_74_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_74_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_74_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_74_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_74_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_74_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_74_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_74_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_74_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_74_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_74_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_74_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_74_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_75 +#define DC_B_WINC_BD_COLOR_PALETTE_75 _MK_ADDR_CONST(0xc4b) +#define DC_B_WINC_BD_COLOR_PALETTE_75_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_75_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_75_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_75_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_75_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_75_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_75_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_75_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_75_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_75_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_75_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_75_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_75_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_75_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_75_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_75_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_75_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_75_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_75_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_75_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_75_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_75_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_75_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_75_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_75_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_75_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_75_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_75_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_75_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_75_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_75_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_75_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_75_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_75_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_75_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_76 +#define DC_B_WINC_BD_COLOR_PALETTE_76 _MK_ADDR_CONST(0xc4c) +#define DC_B_WINC_BD_COLOR_PALETTE_76_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_76_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_76_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_76_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_76_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_76_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_76_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_76_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_76_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_76_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_76_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_76_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_76_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_76_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_76_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_76_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_76_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_76_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_76_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_76_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_76_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_76_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_76_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_76_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_76_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_76_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_76_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_76_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_76_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_76_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_76_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_76_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_76_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_76_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_76_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_77 +#define DC_B_WINC_BD_COLOR_PALETTE_77 _MK_ADDR_CONST(0xc4d) +#define DC_B_WINC_BD_COLOR_PALETTE_77_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_77_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_77_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_77_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_77_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_77_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_77_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_77_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_77_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_77_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_77_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_77_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_77_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_77_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_77_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_77_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_77_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_77_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_77_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_77_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_77_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_77_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_77_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_77_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_77_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_77_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_77_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_77_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_77_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_77_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_77_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_77_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_77_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_77_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_77_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_78 +#define DC_B_WINC_BD_COLOR_PALETTE_78 _MK_ADDR_CONST(0xc4e) +#define DC_B_WINC_BD_COLOR_PALETTE_78_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_78_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_78_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_78_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_78_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_78_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_78_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_78_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_78_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_78_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_78_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_78_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_78_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_78_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_78_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_78_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_78_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_78_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_78_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_78_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_78_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_78_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_78_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_78_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_78_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_78_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_78_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_78_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_78_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_78_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_78_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_78_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_78_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_78_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_78_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_79 +#define DC_B_WINC_BD_COLOR_PALETTE_79 _MK_ADDR_CONST(0xc4f) +#define DC_B_WINC_BD_COLOR_PALETTE_79_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_79_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_79_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_79_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_79_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_79_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_79_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_79_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_79_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_79_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_79_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_79_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_79_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_79_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_79_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_79_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_79_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_79_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_79_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_79_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_79_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_79_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_79_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_79_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_79_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_79_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_79_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_79_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_79_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_79_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_79_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_79_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_79_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_79_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_79_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_80 +#define DC_B_WINC_BD_COLOR_PALETTE_80 _MK_ADDR_CONST(0xc50) +#define DC_B_WINC_BD_COLOR_PALETTE_80_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_80_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_80_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_80_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_80_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_80_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_80_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_80_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_80_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_80_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_80_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_80_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_80_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_80_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_80_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_80_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_80_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_80_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_80_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_80_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_80_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_80_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_80_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_80_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_80_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_80_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_80_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_80_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_80_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_80_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_80_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_80_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_80_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_80_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_80_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_81 +#define DC_B_WINC_BD_COLOR_PALETTE_81 _MK_ADDR_CONST(0xc51) +#define DC_B_WINC_BD_COLOR_PALETTE_81_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_81_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_81_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_81_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_81_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_81_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_81_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_81_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_81_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_81_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_81_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_81_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_81_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_81_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_81_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_81_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_81_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_81_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_81_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_81_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_81_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_81_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_81_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_81_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_81_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_81_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_81_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_81_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_81_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_81_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_81_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_81_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_81_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_81_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_81_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_82 +#define DC_B_WINC_BD_COLOR_PALETTE_82 _MK_ADDR_CONST(0xc52) +#define DC_B_WINC_BD_COLOR_PALETTE_82_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_82_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_82_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_82_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_82_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_82_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_82_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_82_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_82_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_82_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_82_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_82_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_82_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_82_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_82_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_82_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_82_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_82_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_82_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_82_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_82_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_82_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_82_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_82_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_82_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_82_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_82_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_82_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_82_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_82_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_82_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_82_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_82_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_82_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_82_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_83 +#define DC_B_WINC_BD_COLOR_PALETTE_83 _MK_ADDR_CONST(0xc53) +#define DC_B_WINC_BD_COLOR_PALETTE_83_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_83_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_83_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_83_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_83_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_83_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_83_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_83_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_83_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_83_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_83_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_83_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_83_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_83_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_83_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_83_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_83_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_83_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_83_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_83_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_83_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_83_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_83_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_83_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_83_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_83_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_83_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_83_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_83_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_83_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_83_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_83_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_83_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_83_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_83_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_84 +#define DC_B_WINC_BD_COLOR_PALETTE_84 _MK_ADDR_CONST(0xc54) +#define DC_B_WINC_BD_COLOR_PALETTE_84_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_84_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_84_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_84_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_84_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_84_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_84_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_84_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_84_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_84_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_84_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_84_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_84_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_84_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_84_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_84_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_84_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_84_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_84_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_84_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_84_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_84_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_84_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_84_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_84_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_84_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_84_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_84_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_84_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_84_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_84_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_84_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_84_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_84_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_84_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_85 +#define DC_B_WINC_BD_COLOR_PALETTE_85 _MK_ADDR_CONST(0xc55) +#define DC_B_WINC_BD_COLOR_PALETTE_85_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_85_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_85_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_85_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_85_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_85_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_85_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_85_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_85_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_85_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_85_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_85_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_85_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_85_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_85_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_85_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_85_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_85_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_85_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_85_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_85_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_85_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_85_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_85_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_85_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_85_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_85_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_85_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_85_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_85_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_85_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_85_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_85_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_85_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_85_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_86 +#define DC_B_WINC_BD_COLOR_PALETTE_86 _MK_ADDR_CONST(0xc56) +#define DC_B_WINC_BD_COLOR_PALETTE_86_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_86_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_86_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_86_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_86_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_86_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_86_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_86_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_86_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_86_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_86_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_86_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_86_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_86_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_86_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_86_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_86_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_86_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_86_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_86_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_86_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_86_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_86_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_86_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_86_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_86_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_86_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_86_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_86_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_86_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_86_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_86_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_86_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_86_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_86_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_87 +#define DC_B_WINC_BD_COLOR_PALETTE_87 _MK_ADDR_CONST(0xc57) +#define DC_B_WINC_BD_COLOR_PALETTE_87_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_87_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_87_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_87_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_87_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_87_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_87_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_87_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_87_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_87_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_87_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_87_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_87_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_87_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_87_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_87_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_87_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_87_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_87_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_87_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_87_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_87_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_87_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_87_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_87_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_87_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_87_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_87_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_87_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_87_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_87_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_87_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_87_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_87_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_87_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_88 +#define DC_B_WINC_BD_COLOR_PALETTE_88 _MK_ADDR_CONST(0xc58) +#define DC_B_WINC_BD_COLOR_PALETTE_88_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_88_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_88_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_88_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_88_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_88_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_88_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_88_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_88_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_88_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_88_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_88_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_88_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_88_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_88_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_88_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_88_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_88_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_88_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_88_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_88_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_88_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_88_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_88_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_88_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_88_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_88_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_88_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_88_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_88_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_88_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_88_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_88_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_88_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_88_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_89 +#define DC_B_WINC_BD_COLOR_PALETTE_89 _MK_ADDR_CONST(0xc59) +#define DC_B_WINC_BD_COLOR_PALETTE_89_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_89_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_89_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_89_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_89_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_89_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_89_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_89_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_89_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_89_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_89_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_89_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_89_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_89_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_89_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_89_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_89_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_89_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_89_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_89_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_89_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_89_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_89_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_89_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_89_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_89_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_89_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_89_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_89_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_89_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_89_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_89_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_89_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_89_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_89_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_90 +#define DC_B_WINC_BD_COLOR_PALETTE_90 _MK_ADDR_CONST(0xc5a) +#define DC_B_WINC_BD_COLOR_PALETTE_90_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_90_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_90_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_90_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_90_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_90_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_90_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_90_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_90_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_90_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_90_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_90_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_90_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_90_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_90_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_90_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_90_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_90_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_90_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_90_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_90_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_90_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_90_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_90_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_90_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_90_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_90_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_90_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_90_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_90_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_90_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_90_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_90_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_90_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_90_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_91 +#define DC_B_WINC_BD_COLOR_PALETTE_91 _MK_ADDR_CONST(0xc5b) +#define DC_B_WINC_BD_COLOR_PALETTE_91_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_91_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_91_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_91_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_91_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_91_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_91_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_91_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_91_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_91_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_91_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_91_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_91_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_91_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_91_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_91_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_91_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_91_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_91_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_91_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_91_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_91_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_91_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_91_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_91_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_91_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_91_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_91_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_91_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_91_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_91_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_91_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_91_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_91_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_91_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_92 +#define DC_B_WINC_BD_COLOR_PALETTE_92 _MK_ADDR_CONST(0xc5c) +#define DC_B_WINC_BD_COLOR_PALETTE_92_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_92_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_92_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_92_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_92_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_92_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_92_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_92_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_92_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_92_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_92_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_92_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_92_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_92_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_92_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_92_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_92_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_92_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_92_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_92_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_92_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_92_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_92_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_92_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_92_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_92_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_92_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_92_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_92_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_92_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_92_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_92_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_92_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_92_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_92_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_93 +#define DC_B_WINC_BD_COLOR_PALETTE_93 _MK_ADDR_CONST(0xc5d) +#define DC_B_WINC_BD_COLOR_PALETTE_93_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_93_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_93_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_93_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_93_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_93_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_93_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_93_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_93_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_93_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_93_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_93_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_93_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_93_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_93_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_93_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_93_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_93_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_93_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_93_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_93_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_93_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_93_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_93_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_93_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_93_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_93_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_93_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_93_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_93_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_93_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_93_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_93_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_93_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_93_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_94 +#define DC_B_WINC_BD_COLOR_PALETTE_94 _MK_ADDR_CONST(0xc5e) +#define DC_B_WINC_BD_COLOR_PALETTE_94_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_94_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_94_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_94_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_94_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_94_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_94_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_94_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_94_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_94_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_94_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_94_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_94_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_94_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_94_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_94_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_94_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_94_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_94_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_94_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_94_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_94_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_94_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_94_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_94_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_94_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_94_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_94_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_94_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_94_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_94_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_94_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_94_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_94_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_94_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_95 +#define DC_B_WINC_BD_COLOR_PALETTE_95 _MK_ADDR_CONST(0xc5f) +#define DC_B_WINC_BD_COLOR_PALETTE_95_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_95_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_95_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_95_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_95_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_95_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_95_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_95_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_95_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_95_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_95_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_95_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_95_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_95_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_95_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_95_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_95_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_95_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_95_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_95_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_95_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_95_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_95_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_95_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_95_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_95_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_95_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_95_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_95_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_95_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_95_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_95_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_95_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_95_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_95_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_96 +#define DC_B_WINC_BD_COLOR_PALETTE_96 _MK_ADDR_CONST(0xc60) +#define DC_B_WINC_BD_COLOR_PALETTE_96_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_96_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_96_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_96_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_96_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_96_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_96_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_96_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_96_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_96_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_96_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_96_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_96_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_96_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_96_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_96_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_96_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_96_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_96_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_96_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_96_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_96_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_96_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_96_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_96_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_96_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_96_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_96_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_96_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_96_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_96_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_96_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_96_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_96_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_96_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_97 +#define DC_B_WINC_BD_COLOR_PALETTE_97 _MK_ADDR_CONST(0xc61) +#define DC_B_WINC_BD_COLOR_PALETTE_97_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_97_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_97_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_97_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_97_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_97_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_97_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_97_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_97_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_97_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_97_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_97_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_97_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_97_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_97_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_97_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_97_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_97_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_97_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_97_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_97_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_97_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_97_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_97_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_97_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_97_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_97_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_97_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_97_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_97_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_97_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_97_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_97_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_97_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_97_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_98 +#define DC_B_WINC_BD_COLOR_PALETTE_98 _MK_ADDR_CONST(0xc62) +#define DC_B_WINC_BD_COLOR_PALETTE_98_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_98_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_98_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_98_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_98_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_98_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_98_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_98_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_98_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_98_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_98_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_98_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_98_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_98_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_98_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_98_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_98_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_98_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_98_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_98_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_98_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_98_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_98_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_98_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_98_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_98_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_98_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_98_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_98_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_98_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_98_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_98_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_98_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_98_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_98_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_99 +#define DC_B_WINC_BD_COLOR_PALETTE_99 _MK_ADDR_CONST(0xc63) +#define DC_B_WINC_BD_COLOR_PALETTE_99_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_99_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_99_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_99_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_99_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_99_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_99_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_99_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_99_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_99_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_99_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_99_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_99_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_99_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_99_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_99_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_99_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_99_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_99_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_99_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_99_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_99_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_99_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_99_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_99_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_99_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_99_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_99_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_99_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_99_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_99_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_99_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_99_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_99_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_99_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_100 +#define DC_B_WINC_BD_COLOR_PALETTE_100 _MK_ADDR_CONST(0xc64) +#define DC_B_WINC_BD_COLOR_PALETTE_100_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_100_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_100_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_100_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_100_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_100_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_100_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_100_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_100_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_100_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_100_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_100_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_100_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_100_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_100_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_100_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_100_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_100_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_100_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_100_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_100_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_100_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_100_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_100_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_100_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_100_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_100_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_100_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_100_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_100_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_100_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_100_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_100_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_100_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_100_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_101 +#define DC_B_WINC_BD_COLOR_PALETTE_101 _MK_ADDR_CONST(0xc65) +#define DC_B_WINC_BD_COLOR_PALETTE_101_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_101_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_101_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_101_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_101_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_101_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_101_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_101_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_101_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_101_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_101_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_101_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_101_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_101_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_101_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_101_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_101_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_101_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_101_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_101_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_101_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_101_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_101_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_101_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_101_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_101_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_101_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_101_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_101_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_101_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_101_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_101_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_101_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_101_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_101_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_102 +#define DC_B_WINC_BD_COLOR_PALETTE_102 _MK_ADDR_CONST(0xc66) +#define DC_B_WINC_BD_COLOR_PALETTE_102_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_102_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_102_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_102_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_102_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_102_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_102_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_102_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_102_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_102_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_102_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_102_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_102_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_102_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_102_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_102_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_102_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_102_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_102_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_102_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_102_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_102_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_102_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_102_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_102_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_102_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_102_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_102_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_102_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_102_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_102_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_102_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_102_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_102_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_102_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_103 +#define DC_B_WINC_BD_COLOR_PALETTE_103 _MK_ADDR_CONST(0xc67) +#define DC_B_WINC_BD_COLOR_PALETTE_103_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_103_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_103_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_103_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_103_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_103_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_103_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_103_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_103_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_103_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_103_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_103_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_103_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_103_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_103_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_103_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_103_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_103_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_103_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_103_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_103_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_103_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_103_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_103_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_103_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_103_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_103_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_103_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_103_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_103_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_103_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_103_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_103_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_103_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_103_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_104 +#define DC_B_WINC_BD_COLOR_PALETTE_104 _MK_ADDR_CONST(0xc68) +#define DC_B_WINC_BD_COLOR_PALETTE_104_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_104_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_104_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_104_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_104_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_104_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_104_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_104_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_104_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_104_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_104_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_104_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_104_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_104_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_104_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_104_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_104_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_104_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_104_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_104_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_104_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_104_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_104_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_104_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_104_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_104_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_104_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_104_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_104_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_104_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_104_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_104_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_104_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_104_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_104_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_105 +#define DC_B_WINC_BD_COLOR_PALETTE_105 _MK_ADDR_CONST(0xc69) +#define DC_B_WINC_BD_COLOR_PALETTE_105_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_105_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_105_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_105_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_105_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_105_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_105_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_105_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_105_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_105_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_105_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_105_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_105_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_105_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_105_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_105_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_105_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_105_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_105_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_105_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_105_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_105_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_105_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_105_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_105_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_105_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_105_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_105_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_105_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_105_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_105_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_105_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_105_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_105_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_105_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_106 +#define DC_B_WINC_BD_COLOR_PALETTE_106 _MK_ADDR_CONST(0xc6a) +#define DC_B_WINC_BD_COLOR_PALETTE_106_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_106_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_106_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_106_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_106_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_106_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_106_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_106_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_106_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_106_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_106_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_106_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_106_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_106_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_106_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_106_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_106_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_106_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_106_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_106_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_106_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_106_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_106_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_106_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_106_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_106_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_106_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_106_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_106_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_106_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_106_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_106_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_106_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_106_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_106_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_107 +#define DC_B_WINC_BD_COLOR_PALETTE_107 _MK_ADDR_CONST(0xc6b) +#define DC_B_WINC_BD_COLOR_PALETTE_107_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_107_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_107_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_107_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_107_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_107_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_107_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_107_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_107_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_107_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_107_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_107_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_107_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_107_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_107_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_107_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_107_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_107_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_107_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_107_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_107_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_107_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_107_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_107_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_107_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_107_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_107_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_107_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_107_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_107_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_107_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_107_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_107_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_107_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_107_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_108 +#define DC_B_WINC_BD_COLOR_PALETTE_108 _MK_ADDR_CONST(0xc6c) +#define DC_B_WINC_BD_COLOR_PALETTE_108_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_108_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_108_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_108_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_108_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_108_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_108_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_108_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_108_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_108_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_108_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_108_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_108_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_108_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_108_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_108_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_108_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_108_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_108_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_108_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_108_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_108_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_108_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_108_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_108_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_108_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_108_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_108_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_108_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_108_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_108_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_108_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_108_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_108_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_108_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_109 +#define DC_B_WINC_BD_COLOR_PALETTE_109 _MK_ADDR_CONST(0xc6d) +#define DC_B_WINC_BD_COLOR_PALETTE_109_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_109_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_109_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_109_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_109_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_109_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_109_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_109_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_109_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_109_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_109_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_109_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_109_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_109_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_109_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_109_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_109_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_109_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_109_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_109_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_109_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_109_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_109_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_109_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_109_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_109_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_109_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_109_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_109_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_109_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_109_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_109_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_109_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_109_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_109_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_110 +#define DC_B_WINC_BD_COLOR_PALETTE_110 _MK_ADDR_CONST(0xc6e) +#define DC_B_WINC_BD_COLOR_PALETTE_110_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_110_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_110_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_110_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_110_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_110_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_110_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_110_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_110_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_110_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_110_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_110_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_110_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_110_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_110_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_110_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_110_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_110_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_110_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_110_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_110_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_110_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_110_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_110_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_110_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_110_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_110_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_110_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_110_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_110_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_110_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_110_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_110_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_110_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_110_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_111 +#define DC_B_WINC_BD_COLOR_PALETTE_111 _MK_ADDR_CONST(0xc6f) +#define DC_B_WINC_BD_COLOR_PALETTE_111_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_111_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_111_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_111_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_111_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_111_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_111_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_111_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_111_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_111_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_111_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_111_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_111_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_111_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_111_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_111_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_111_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_111_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_111_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_111_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_111_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_111_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_111_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_111_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_111_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_111_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_111_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_111_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_111_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_111_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_111_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_111_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_111_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_111_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_111_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_112 +#define DC_B_WINC_BD_COLOR_PALETTE_112 _MK_ADDR_CONST(0xc70) +#define DC_B_WINC_BD_COLOR_PALETTE_112_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_112_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_112_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_112_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_112_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_112_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_112_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_112_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_112_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_112_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_112_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_112_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_112_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_112_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_112_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_112_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_112_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_112_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_112_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_112_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_112_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_112_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_112_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_112_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_112_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_112_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_112_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_112_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_112_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_112_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_112_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_112_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_112_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_112_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_112_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_113 +#define DC_B_WINC_BD_COLOR_PALETTE_113 _MK_ADDR_CONST(0xc71) +#define DC_B_WINC_BD_COLOR_PALETTE_113_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_113_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_113_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_113_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_113_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_113_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_113_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_113_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_113_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_113_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_113_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_113_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_113_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_113_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_113_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_113_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_113_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_113_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_113_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_113_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_113_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_113_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_113_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_113_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_113_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_113_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_113_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_113_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_113_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_113_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_113_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_113_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_113_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_113_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_113_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_114 +#define DC_B_WINC_BD_COLOR_PALETTE_114 _MK_ADDR_CONST(0xc72) +#define DC_B_WINC_BD_COLOR_PALETTE_114_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_114_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_114_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_114_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_114_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_114_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_114_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_114_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_114_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_114_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_114_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_114_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_114_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_114_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_114_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_114_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_114_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_114_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_114_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_114_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_114_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_114_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_114_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_114_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_114_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_114_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_114_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_114_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_114_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_114_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_114_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_114_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_114_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_114_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_114_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_115 +#define DC_B_WINC_BD_COLOR_PALETTE_115 _MK_ADDR_CONST(0xc73) +#define DC_B_WINC_BD_COLOR_PALETTE_115_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_115_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_115_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_115_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_115_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_115_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_115_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_115_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_115_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_115_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_115_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_115_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_115_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_115_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_115_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_115_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_115_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_115_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_115_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_115_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_115_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_115_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_115_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_115_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_115_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_115_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_115_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_115_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_115_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_115_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_115_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_115_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_115_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_115_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_115_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_116 +#define DC_B_WINC_BD_COLOR_PALETTE_116 _MK_ADDR_CONST(0xc74) +#define DC_B_WINC_BD_COLOR_PALETTE_116_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_116_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_116_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_116_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_116_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_116_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_116_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_116_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_116_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_116_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_116_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_116_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_116_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_116_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_116_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_116_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_116_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_116_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_116_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_116_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_116_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_116_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_116_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_116_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_116_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_116_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_116_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_116_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_116_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_116_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_116_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_116_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_116_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_116_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_116_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_117 +#define DC_B_WINC_BD_COLOR_PALETTE_117 _MK_ADDR_CONST(0xc75) +#define DC_B_WINC_BD_COLOR_PALETTE_117_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_117_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_117_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_117_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_117_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_117_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_117_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_117_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_117_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_117_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_117_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_117_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_117_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_117_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_117_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_117_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_117_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_117_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_117_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_117_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_117_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_117_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_117_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_117_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_117_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_117_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_117_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_117_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_117_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_117_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_117_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_117_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_117_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_117_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_117_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_118 +#define DC_B_WINC_BD_COLOR_PALETTE_118 _MK_ADDR_CONST(0xc76) +#define DC_B_WINC_BD_COLOR_PALETTE_118_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_118_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_118_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_118_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_118_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_118_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_118_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_118_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_118_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_118_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_118_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_118_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_118_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_118_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_118_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_118_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_118_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_118_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_118_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_118_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_118_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_118_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_118_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_118_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_118_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_118_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_118_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_118_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_118_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_118_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_118_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_118_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_118_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_118_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_118_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_119 +#define DC_B_WINC_BD_COLOR_PALETTE_119 _MK_ADDR_CONST(0xc77) +#define DC_B_WINC_BD_COLOR_PALETTE_119_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_119_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_119_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_119_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_119_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_119_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_119_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_119_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_119_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_119_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_119_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_119_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_119_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_119_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_119_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_119_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_119_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_119_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_119_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_119_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_119_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_119_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_119_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_119_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_119_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_119_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_119_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_119_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_119_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_119_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_119_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_119_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_119_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_119_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_119_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_120 +#define DC_B_WINC_BD_COLOR_PALETTE_120 _MK_ADDR_CONST(0xc78) +#define DC_B_WINC_BD_COLOR_PALETTE_120_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_120_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_120_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_120_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_120_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_120_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_120_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_120_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_120_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_120_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_120_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_120_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_120_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_120_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_120_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_120_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_120_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_120_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_120_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_120_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_120_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_120_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_120_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_120_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_120_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_120_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_120_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_120_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_120_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_120_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_120_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_120_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_120_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_120_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_120_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_121 +#define DC_B_WINC_BD_COLOR_PALETTE_121 _MK_ADDR_CONST(0xc79) +#define DC_B_WINC_BD_COLOR_PALETTE_121_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_121_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_121_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_121_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_121_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_121_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_121_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_121_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_121_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_121_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_121_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_121_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_121_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_121_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_121_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_121_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_121_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_121_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_121_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_121_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_121_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_121_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_121_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_121_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_121_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_121_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_121_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_121_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_121_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_121_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_121_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_121_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_121_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_121_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_121_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_122 +#define DC_B_WINC_BD_COLOR_PALETTE_122 _MK_ADDR_CONST(0xc7a) +#define DC_B_WINC_BD_COLOR_PALETTE_122_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_122_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_122_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_122_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_122_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_122_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_122_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_122_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_122_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_122_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_122_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_122_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_122_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_122_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_122_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_122_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_122_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_122_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_122_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_122_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_122_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_122_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_122_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_122_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_122_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_122_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_122_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_122_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_122_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_122_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_122_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_122_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_122_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_122_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_122_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_123 +#define DC_B_WINC_BD_COLOR_PALETTE_123 _MK_ADDR_CONST(0xc7b) +#define DC_B_WINC_BD_COLOR_PALETTE_123_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_123_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_123_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_123_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_123_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_123_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_123_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_123_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_123_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_123_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_123_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_123_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_123_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_123_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_123_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_123_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_123_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_123_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_123_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_123_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_123_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_123_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_123_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_123_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_123_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_123_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_123_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_123_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_123_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_123_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_123_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_123_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_123_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_123_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_123_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_124 +#define DC_B_WINC_BD_COLOR_PALETTE_124 _MK_ADDR_CONST(0xc7c) +#define DC_B_WINC_BD_COLOR_PALETTE_124_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_124_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_124_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_124_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_124_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_124_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_124_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_124_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_124_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_124_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_124_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_124_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_124_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_124_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_124_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_124_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_124_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_124_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_124_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_124_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_124_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_124_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_124_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_124_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_124_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_124_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_124_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_124_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_124_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_124_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_124_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_124_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_124_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_124_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_124_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_125 +#define DC_B_WINC_BD_COLOR_PALETTE_125 _MK_ADDR_CONST(0xc7d) +#define DC_B_WINC_BD_COLOR_PALETTE_125_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_125_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_125_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_125_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_125_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_125_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_125_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_125_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_125_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_125_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_125_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_125_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_125_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_125_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_125_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_125_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_125_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_125_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_125_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_125_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_125_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_125_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_125_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_125_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_125_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_125_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_125_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_125_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_125_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_125_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_125_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_125_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_125_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_125_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_125_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_126 +#define DC_B_WINC_BD_COLOR_PALETTE_126 _MK_ADDR_CONST(0xc7e) +#define DC_B_WINC_BD_COLOR_PALETTE_126_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_126_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_126_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_126_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_126_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_126_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_126_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_126_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_126_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_126_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_126_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_126_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_126_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_126_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_126_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_126_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_126_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_126_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_126_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_126_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_126_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_126_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_126_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_126_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_126_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_126_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_126_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_126_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_126_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_126_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_126_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_126_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_126_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_126_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_126_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_127 +#define DC_B_WINC_BD_COLOR_PALETTE_127 _MK_ADDR_CONST(0xc7f) +#define DC_B_WINC_BD_COLOR_PALETTE_127_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_127_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_127_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_127_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_127_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_127_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_127_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_127_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_127_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_127_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_127_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_127_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_127_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_127_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_127_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_127_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_127_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_127_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_127_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_127_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_127_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_127_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_127_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_127_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_127_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_127_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_127_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_127_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_127_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_127_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_127_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_127_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_127_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_127_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_127_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_128 +#define DC_B_WINC_BD_COLOR_PALETTE_128 _MK_ADDR_CONST(0xc80) +#define DC_B_WINC_BD_COLOR_PALETTE_128_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_128_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_128_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_128_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_128_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_128_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_128_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_128_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_128_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_128_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_128_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_128_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_128_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_128_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_128_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_128_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_128_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_128_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_128_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_128_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_128_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_128_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_128_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_128_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_128_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_128_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_128_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_128_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_128_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_128_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_128_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_128_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_128_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_128_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_128_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_129 +#define DC_B_WINC_BD_COLOR_PALETTE_129 _MK_ADDR_CONST(0xc81) +#define DC_B_WINC_BD_COLOR_PALETTE_129_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_129_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_129_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_129_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_129_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_129_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_129_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_129_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_129_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_129_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_129_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_129_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_129_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_129_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_129_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_129_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_129_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_129_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_129_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_129_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_129_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_129_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_129_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_129_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_129_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_129_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_129_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_129_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_129_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_129_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_129_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_129_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_129_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_129_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_129_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_130 +#define DC_B_WINC_BD_COLOR_PALETTE_130 _MK_ADDR_CONST(0xc82) +#define DC_B_WINC_BD_COLOR_PALETTE_130_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_130_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_130_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_130_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_130_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_130_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_130_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_130_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_130_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_130_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_130_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_130_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_130_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_130_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_130_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_130_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_130_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_130_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_130_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_130_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_130_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_130_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_130_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_130_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_130_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_130_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_130_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_130_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_130_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_130_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_130_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_130_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_130_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_130_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_130_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_131 +#define DC_B_WINC_BD_COLOR_PALETTE_131 _MK_ADDR_CONST(0xc83) +#define DC_B_WINC_BD_COLOR_PALETTE_131_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_131_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_131_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_131_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_131_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_131_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_131_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_131_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_131_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_131_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_131_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_131_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_131_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_131_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_131_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_131_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_131_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_131_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_131_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_131_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_131_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_131_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_131_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_131_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_131_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_131_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_131_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_131_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_131_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_131_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_131_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_131_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_131_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_131_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_131_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_132 +#define DC_B_WINC_BD_COLOR_PALETTE_132 _MK_ADDR_CONST(0xc84) +#define DC_B_WINC_BD_COLOR_PALETTE_132_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_132_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_132_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_132_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_132_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_132_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_132_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_132_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_132_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_132_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_132_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_132_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_132_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_132_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_132_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_132_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_132_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_132_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_132_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_132_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_132_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_132_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_132_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_132_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_132_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_132_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_132_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_132_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_132_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_132_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_132_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_132_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_132_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_132_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_132_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_133 +#define DC_B_WINC_BD_COLOR_PALETTE_133 _MK_ADDR_CONST(0xc85) +#define DC_B_WINC_BD_COLOR_PALETTE_133_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_133_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_133_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_133_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_133_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_133_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_133_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_133_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_133_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_133_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_133_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_133_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_133_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_133_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_133_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_133_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_133_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_133_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_133_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_133_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_133_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_133_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_133_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_133_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_133_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_133_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_133_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_133_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_133_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_133_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_133_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_133_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_133_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_133_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_133_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_134 +#define DC_B_WINC_BD_COLOR_PALETTE_134 _MK_ADDR_CONST(0xc86) +#define DC_B_WINC_BD_COLOR_PALETTE_134_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_134_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_134_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_134_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_134_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_134_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_134_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_134_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_134_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_134_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_134_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_134_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_134_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_134_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_134_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_134_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_134_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_134_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_134_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_134_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_134_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_134_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_134_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_134_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_134_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_134_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_134_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_134_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_134_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_134_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_134_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_134_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_134_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_134_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_134_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_135 +#define DC_B_WINC_BD_COLOR_PALETTE_135 _MK_ADDR_CONST(0xc87) +#define DC_B_WINC_BD_COLOR_PALETTE_135_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_135_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_135_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_135_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_135_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_135_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_135_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_135_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_135_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_135_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_135_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_135_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_135_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_135_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_135_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_135_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_135_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_135_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_135_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_135_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_135_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_135_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_135_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_135_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_135_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_135_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_135_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_135_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_135_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_135_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_135_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_135_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_135_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_135_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_135_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_136 +#define DC_B_WINC_BD_COLOR_PALETTE_136 _MK_ADDR_CONST(0xc88) +#define DC_B_WINC_BD_COLOR_PALETTE_136_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_136_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_136_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_136_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_136_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_136_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_136_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_136_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_136_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_136_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_136_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_136_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_136_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_136_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_136_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_136_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_136_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_136_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_136_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_136_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_136_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_136_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_136_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_136_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_136_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_136_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_136_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_136_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_136_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_136_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_136_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_136_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_136_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_136_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_136_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_137 +#define DC_B_WINC_BD_COLOR_PALETTE_137 _MK_ADDR_CONST(0xc89) +#define DC_B_WINC_BD_COLOR_PALETTE_137_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_137_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_137_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_137_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_137_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_137_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_137_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_137_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_137_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_137_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_137_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_137_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_137_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_137_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_137_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_137_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_137_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_137_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_137_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_137_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_137_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_137_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_137_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_137_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_137_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_137_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_137_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_137_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_137_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_137_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_137_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_137_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_137_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_137_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_137_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_138 +#define DC_B_WINC_BD_COLOR_PALETTE_138 _MK_ADDR_CONST(0xc8a) +#define DC_B_WINC_BD_COLOR_PALETTE_138_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_138_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_138_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_138_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_138_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_138_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_138_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_138_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_138_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_138_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_138_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_138_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_138_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_138_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_138_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_138_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_138_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_138_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_138_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_138_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_138_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_138_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_138_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_138_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_138_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_138_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_138_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_138_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_138_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_138_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_138_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_138_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_138_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_138_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_138_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_139 +#define DC_B_WINC_BD_COLOR_PALETTE_139 _MK_ADDR_CONST(0xc8b) +#define DC_B_WINC_BD_COLOR_PALETTE_139_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_139_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_139_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_139_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_139_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_139_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_139_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_139_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_139_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_139_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_139_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_139_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_139_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_139_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_139_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_139_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_139_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_139_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_139_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_139_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_139_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_139_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_139_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_139_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_139_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_139_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_139_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_139_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_139_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_139_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_139_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_139_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_139_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_139_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_139_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_140 +#define DC_B_WINC_BD_COLOR_PALETTE_140 _MK_ADDR_CONST(0xc8c) +#define DC_B_WINC_BD_COLOR_PALETTE_140_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_140_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_140_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_140_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_140_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_140_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_140_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_140_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_140_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_140_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_140_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_140_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_140_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_140_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_140_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_140_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_140_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_140_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_140_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_140_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_140_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_140_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_140_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_140_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_140_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_140_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_140_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_140_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_140_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_140_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_140_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_140_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_140_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_140_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_140_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_141 +#define DC_B_WINC_BD_COLOR_PALETTE_141 _MK_ADDR_CONST(0xc8d) +#define DC_B_WINC_BD_COLOR_PALETTE_141_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_141_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_141_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_141_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_141_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_141_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_141_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_141_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_141_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_141_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_141_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_141_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_141_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_141_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_141_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_141_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_141_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_141_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_141_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_141_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_141_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_141_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_141_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_141_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_141_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_141_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_141_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_141_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_141_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_141_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_141_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_141_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_141_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_141_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_141_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_142 +#define DC_B_WINC_BD_COLOR_PALETTE_142 _MK_ADDR_CONST(0xc8e) +#define DC_B_WINC_BD_COLOR_PALETTE_142_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_142_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_142_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_142_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_142_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_142_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_142_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_142_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_142_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_142_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_142_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_142_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_142_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_142_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_142_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_142_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_142_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_142_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_142_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_142_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_142_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_142_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_142_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_142_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_142_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_142_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_142_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_142_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_142_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_142_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_142_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_142_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_142_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_142_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_142_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_143 +#define DC_B_WINC_BD_COLOR_PALETTE_143 _MK_ADDR_CONST(0xc8f) +#define DC_B_WINC_BD_COLOR_PALETTE_143_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_143_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_143_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_143_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_143_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_143_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_143_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_143_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_143_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_143_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_143_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_143_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_143_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_143_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_143_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_143_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_143_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_143_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_143_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_143_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_143_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_143_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_143_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_143_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_143_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_143_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_143_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_143_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_143_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_143_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_143_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_143_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_143_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_143_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_143_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_144 +#define DC_B_WINC_BD_COLOR_PALETTE_144 _MK_ADDR_CONST(0xc90) +#define DC_B_WINC_BD_COLOR_PALETTE_144_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_144_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_144_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_144_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_144_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_144_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_144_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_144_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_144_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_144_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_144_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_144_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_144_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_144_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_144_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_144_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_144_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_144_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_144_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_144_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_144_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_144_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_144_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_144_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_144_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_144_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_144_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_144_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_144_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_144_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_144_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_144_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_144_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_144_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_144_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_145 +#define DC_B_WINC_BD_COLOR_PALETTE_145 _MK_ADDR_CONST(0xc91) +#define DC_B_WINC_BD_COLOR_PALETTE_145_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_145_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_145_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_145_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_145_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_145_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_145_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_145_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_145_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_145_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_145_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_145_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_145_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_145_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_145_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_145_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_145_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_145_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_145_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_145_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_145_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_145_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_145_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_145_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_145_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_145_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_145_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_145_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_145_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_145_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_145_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_145_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_145_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_145_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_145_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_146 +#define DC_B_WINC_BD_COLOR_PALETTE_146 _MK_ADDR_CONST(0xc92) +#define DC_B_WINC_BD_COLOR_PALETTE_146_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_146_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_146_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_146_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_146_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_146_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_146_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_146_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_146_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_146_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_146_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_146_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_146_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_146_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_146_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_146_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_146_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_146_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_146_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_146_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_146_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_146_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_146_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_146_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_146_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_146_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_146_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_146_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_146_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_146_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_146_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_146_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_146_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_146_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_146_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_147 +#define DC_B_WINC_BD_COLOR_PALETTE_147 _MK_ADDR_CONST(0xc93) +#define DC_B_WINC_BD_COLOR_PALETTE_147_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_147_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_147_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_147_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_147_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_147_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_147_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_147_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_147_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_147_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_147_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_147_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_147_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_147_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_147_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_147_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_147_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_147_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_147_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_147_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_147_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_147_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_147_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_147_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_147_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_147_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_147_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_147_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_147_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_147_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_147_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_147_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_147_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_147_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_147_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_148 +#define DC_B_WINC_BD_COLOR_PALETTE_148 _MK_ADDR_CONST(0xc94) +#define DC_B_WINC_BD_COLOR_PALETTE_148_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_148_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_148_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_148_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_148_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_148_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_148_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_148_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_148_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_148_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_148_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_148_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_148_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_148_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_148_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_148_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_148_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_148_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_148_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_148_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_148_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_148_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_148_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_148_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_148_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_148_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_148_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_148_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_148_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_148_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_148_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_148_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_148_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_148_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_148_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_149 +#define DC_B_WINC_BD_COLOR_PALETTE_149 _MK_ADDR_CONST(0xc95) +#define DC_B_WINC_BD_COLOR_PALETTE_149_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_149_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_149_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_149_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_149_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_149_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_149_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_149_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_149_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_149_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_149_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_149_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_149_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_149_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_149_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_149_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_149_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_149_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_149_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_149_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_149_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_149_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_149_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_149_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_149_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_149_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_149_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_149_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_149_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_149_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_149_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_149_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_149_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_149_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_149_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_150 +#define DC_B_WINC_BD_COLOR_PALETTE_150 _MK_ADDR_CONST(0xc96) +#define DC_B_WINC_BD_COLOR_PALETTE_150_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_150_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_150_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_150_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_150_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_150_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_150_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_150_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_150_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_150_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_150_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_150_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_150_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_150_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_150_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_150_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_150_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_150_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_150_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_150_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_150_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_150_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_150_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_150_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_150_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_150_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_150_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_150_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_150_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_150_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_150_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_150_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_150_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_150_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_150_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_151 +#define DC_B_WINC_BD_COLOR_PALETTE_151 _MK_ADDR_CONST(0xc97) +#define DC_B_WINC_BD_COLOR_PALETTE_151_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_151_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_151_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_151_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_151_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_151_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_151_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_151_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_151_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_151_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_151_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_151_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_151_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_151_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_151_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_151_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_151_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_151_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_151_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_151_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_151_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_151_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_151_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_151_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_151_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_151_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_151_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_151_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_151_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_151_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_151_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_151_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_151_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_151_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_151_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_152 +#define DC_B_WINC_BD_COLOR_PALETTE_152 _MK_ADDR_CONST(0xc98) +#define DC_B_WINC_BD_COLOR_PALETTE_152_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_152_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_152_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_152_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_152_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_152_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_152_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_152_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_152_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_152_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_152_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_152_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_152_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_152_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_152_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_152_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_152_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_152_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_152_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_152_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_152_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_152_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_152_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_152_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_152_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_152_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_152_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_152_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_152_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_152_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_152_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_152_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_152_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_152_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_152_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_153 +#define DC_B_WINC_BD_COLOR_PALETTE_153 _MK_ADDR_CONST(0xc99) +#define DC_B_WINC_BD_COLOR_PALETTE_153_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_153_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_153_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_153_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_153_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_153_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_153_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_153_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_153_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_153_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_153_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_153_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_153_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_153_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_153_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_153_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_153_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_153_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_153_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_153_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_153_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_153_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_153_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_153_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_153_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_153_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_153_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_153_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_153_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_153_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_153_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_153_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_153_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_153_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_153_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_154 +#define DC_B_WINC_BD_COLOR_PALETTE_154 _MK_ADDR_CONST(0xc9a) +#define DC_B_WINC_BD_COLOR_PALETTE_154_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_154_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_154_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_154_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_154_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_154_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_154_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_154_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_154_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_154_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_154_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_154_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_154_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_154_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_154_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_154_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_154_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_154_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_154_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_154_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_154_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_154_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_154_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_154_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_154_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_154_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_154_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_154_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_154_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_154_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_154_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_154_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_154_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_154_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_154_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_155 +#define DC_B_WINC_BD_COLOR_PALETTE_155 _MK_ADDR_CONST(0xc9b) +#define DC_B_WINC_BD_COLOR_PALETTE_155_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_155_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_155_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_155_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_155_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_155_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_155_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_155_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_155_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_155_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_155_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_155_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_155_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_155_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_155_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_155_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_155_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_155_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_155_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_155_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_155_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_155_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_155_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_155_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_155_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_155_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_155_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_155_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_155_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_155_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_155_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_155_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_155_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_155_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_155_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_156 +#define DC_B_WINC_BD_COLOR_PALETTE_156 _MK_ADDR_CONST(0xc9c) +#define DC_B_WINC_BD_COLOR_PALETTE_156_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_156_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_156_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_156_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_156_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_156_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_156_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_156_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_156_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_156_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_156_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_156_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_156_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_156_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_156_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_156_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_156_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_156_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_156_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_156_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_156_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_156_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_156_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_156_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_156_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_156_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_156_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_156_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_156_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_156_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_156_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_156_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_156_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_156_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_156_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_157 +#define DC_B_WINC_BD_COLOR_PALETTE_157 _MK_ADDR_CONST(0xc9d) +#define DC_B_WINC_BD_COLOR_PALETTE_157_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_157_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_157_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_157_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_157_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_157_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_157_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_157_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_157_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_157_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_157_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_157_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_157_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_157_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_157_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_157_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_157_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_157_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_157_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_157_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_157_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_157_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_157_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_157_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_157_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_157_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_157_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_157_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_157_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_157_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_157_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_157_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_157_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_157_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_157_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_158 +#define DC_B_WINC_BD_COLOR_PALETTE_158 _MK_ADDR_CONST(0xc9e) +#define DC_B_WINC_BD_COLOR_PALETTE_158_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_158_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_158_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_158_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_158_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_158_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_158_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_158_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_158_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_158_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_158_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_158_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_158_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_158_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_158_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_158_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_158_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_158_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_158_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_158_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_158_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_158_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_158_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_158_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_158_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_158_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_158_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_158_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_158_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_158_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_158_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_158_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_158_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_158_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_158_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_159 +#define DC_B_WINC_BD_COLOR_PALETTE_159 _MK_ADDR_CONST(0xc9f) +#define DC_B_WINC_BD_COLOR_PALETTE_159_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_159_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_159_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_159_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_159_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_159_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_159_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_159_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_159_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_159_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_159_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_159_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_159_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_159_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_159_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_159_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_159_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_159_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_159_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_159_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_159_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_159_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_159_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_159_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_159_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_159_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_159_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_159_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_159_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_159_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_159_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_159_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_159_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_159_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_159_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_160 +#define DC_B_WINC_BD_COLOR_PALETTE_160 _MK_ADDR_CONST(0xca0) +#define DC_B_WINC_BD_COLOR_PALETTE_160_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_160_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_160_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_160_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_160_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_160_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_160_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_160_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_160_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_160_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_160_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_160_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_160_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_160_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_160_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_160_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_160_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_160_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_160_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_160_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_160_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_160_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_160_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_160_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_160_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_160_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_160_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_160_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_160_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_160_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_160_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_160_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_160_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_160_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_160_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_161 +#define DC_B_WINC_BD_COLOR_PALETTE_161 _MK_ADDR_CONST(0xca1) +#define DC_B_WINC_BD_COLOR_PALETTE_161_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_161_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_161_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_161_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_161_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_161_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_161_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_161_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_161_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_161_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_161_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_161_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_161_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_161_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_161_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_161_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_161_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_161_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_161_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_161_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_161_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_161_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_161_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_161_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_161_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_161_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_161_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_161_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_161_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_161_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_161_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_161_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_161_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_161_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_161_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_162 +#define DC_B_WINC_BD_COLOR_PALETTE_162 _MK_ADDR_CONST(0xca2) +#define DC_B_WINC_BD_COLOR_PALETTE_162_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_162_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_162_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_162_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_162_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_162_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_162_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_162_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_162_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_162_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_162_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_162_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_162_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_162_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_162_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_162_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_162_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_162_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_162_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_162_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_162_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_162_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_162_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_162_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_162_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_162_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_162_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_162_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_162_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_162_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_162_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_162_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_162_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_162_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_162_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_163 +#define DC_B_WINC_BD_COLOR_PALETTE_163 _MK_ADDR_CONST(0xca3) +#define DC_B_WINC_BD_COLOR_PALETTE_163_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_163_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_163_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_163_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_163_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_163_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_163_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_163_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_163_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_163_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_163_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_163_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_163_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_163_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_163_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_163_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_163_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_163_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_163_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_163_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_163_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_163_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_163_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_163_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_163_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_163_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_163_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_163_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_163_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_163_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_163_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_163_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_163_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_163_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_163_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_164 +#define DC_B_WINC_BD_COLOR_PALETTE_164 _MK_ADDR_CONST(0xca4) +#define DC_B_WINC_BD_COLOR_PALETTE_164_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_164_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_164_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_164_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_164_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_164_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_164_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_164_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_164_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_164_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_164_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_164_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_164_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_164_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_164_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_164_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_164_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_164_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_164_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_164_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_164_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_164_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_164_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_164_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_164_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_164_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_164_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_164_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_164_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_164_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_164_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_164_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_164_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_164_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_164_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_165 +#define DC_B_WINC_BD_COLOR_PALETTE_165 _MK_ADDR_CONST(0xca5) +#define DC_B_WINC_BD_COLOR_PALETTE_165_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_165_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_165_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_165_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_165_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_165_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_165_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_165_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_165_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_165_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_165_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_165_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_165_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_165_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_165_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_165_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_165_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_165_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_165_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_165_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_165_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_165_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_165_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_165_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_165_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_165_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_165_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_165_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_165_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_165_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_165_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_165_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_165_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_165_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_165_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_166 +#define DC_B_WINC_BD_COLOR_PALETTE_166 _MK_ADDR_CONST(0xca6) +#define DC_B_WINC_BD_COLOR_PALETTE_166_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_166_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_166_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_166_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_166_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_166_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_166_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_166_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_166_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_166_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_166_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_166_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_166_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_166_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_166_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_166_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_166_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_166_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_166_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_166_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_166_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_166_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_166_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_166_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_166_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_166_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_166_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_166_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_166_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_166_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_166_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_166_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_166_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_166_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_166_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_167 +#define DC_B_WINC_BD_COLOR_PALETTE_167 _MK_ADDR_CONST(0xca7) +#define DC_B_WINC_BD_COLOR_PALETTE_167_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_167_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_167_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_167_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_167_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_167_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_167_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_167_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_167_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_167_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_167_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_167_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_167_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_167_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_167_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_167_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_167_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_167_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_167_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_167_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_167_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_167_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_167_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_167_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_167_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_167_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_167_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_167_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_167_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_167_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_167_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_167_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_167_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_167_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_167_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_168 +#define DC_B_WINC_BD_COLOR_PALETTE_168 _MK_ADDR_CONST(0xca8) +#define DC_B_WINC_BD_COLOR_PALETTE_168_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_168_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_168_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_168_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_168_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_168_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_168_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_168_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_168_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_168_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_168_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_168_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_168_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_168_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_168_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_168_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_168_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_168_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_168_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_168_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_168_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_168_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_168_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_168_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_168_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_168_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_168_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_168_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_168_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_168_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_168_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_168_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_168_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_168_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_168_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_169 +#define DC_B_WINC_BD_COLOR_PALETTE_169 _MK_ADDR_CONST(0xca9) +#define DC_B_WINC_BD_COLOR_PALETTE_169_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_169_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_169_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_169_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_169_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_169_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_169_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_169_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_169_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_169_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_169_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_169_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_169_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_169_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_169_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_169_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_169_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_169_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_169_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_169_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_169_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_169_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_169_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_169_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_169_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_169_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_169_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_169_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_169_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_169_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_169_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_169_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_169_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_169_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_169_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_170 +#define DC_B_WINC_BD_COLOR_PALETTE_170 _MK_ADDR_CONST(0xcaa) +#define DC_B_WINC_BD_COLOR_PALETTE_170_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_170_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_170_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_170_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_170_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_170_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_170_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_170_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_170_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_170_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_170_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_170_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_170_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_170_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_170_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_170_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_170_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_170_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_170_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_170_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_170_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_170_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_170_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_170_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_170_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_170_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_170_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_170_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_170_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_170_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_170_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_170_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_170_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_170_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_170_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_171 +#define DC_B_WINC_BD_COLOR_PALETTE_171 _MK_ADDR_CONST(0xcab) +#define DC_B_WINC_BD_COLOR_PALETTE_171_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_171_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_171_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_171_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_171_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_171_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_171_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_171_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_171_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_171_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_171_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_171_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_171_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_171_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_171_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_171_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_171_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_171_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_171_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_171_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_171_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_171_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_171_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_171_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_171_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_171_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_171_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_171_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_171_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_171_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_171_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_171_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_171_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_171_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_171_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_172 +#define DC_B_WINC_BD_COLOR_PALETTE_172 _MK_ADDR_CONST(0xcac) +#define DC_B_WINC_BD_COLOR_PALETTE_172_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_172_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_172_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_172_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_172_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_172_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_172_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_172_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_172_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_172_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_172_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_172_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_172_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_172_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_172_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_172_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_172_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_172_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_172_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_172_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_172_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_172_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_172_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_172_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_172_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_172_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_172_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_172_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_172_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_172_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_172_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_172_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_172_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_172_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_172_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_173 +#define DC_B_WINC_BD_COLOR_PALETTE_173 _MK_ADDR_CONST(0xcad) +#define DC_B_WINC_BD_COLOR_PALETTE_173_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_173_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_173_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_173_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_173_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_173_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_173_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_173_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_173_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_173_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_173_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_173_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_173_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_173_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_173_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_173_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_173_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_173_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_173_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_173_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_173_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_173_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_173_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_173_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_173_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_173_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_173_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_173_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_173_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_173_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_173_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_173_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_173_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_173_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_173_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_174 +#define DC_B_WINC_BD_COLOR_PALETTE_174 _MK_ADDR_CONST(0xcae) +#define DC_B_WINC_BD_COLOR_PALETTE_174_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_174_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_174_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_174_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_174_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_174_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_174_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_174_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_174_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_174_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_174_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_174_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_174_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_174_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_174_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_174_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_174_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_174_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_174_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_174_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_174_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_174_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_174_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_174_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_174_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_174_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_174_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_174_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_174_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_174_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_174_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_174_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_174_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_174_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_174_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_175 +#define DC_B_WINC_BD_COLOR_PALETTE_175 _MK_ADDR_CONST(0xcaf) +#define DC_B_WINC_BD_COLOR_PALETTE_175_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_175_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_175_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_175_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_175_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_175_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_175_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_175_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_175_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_175_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_175_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_175_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_175_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_175_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_175_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_175_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_175_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_175_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_175_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_175_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_175_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_175_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_175_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_175_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_175_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_175_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_175_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_175_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_175_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_175_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_175_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_175_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_175_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_175_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_175_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_176 +#define DC_B_WINC_BD_COLOR_PALETTE_176 _MK_ADDR_CONST(0xcb0) +#define DC_B_WINC_BD_COLOR_PALETTE_176_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_176_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_176_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_176_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_176_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_176_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_176_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_176_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_176_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_176_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_176_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_176_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_176_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_176_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_176_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_176_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_176_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_176_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_176_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_176_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_176_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_176_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_176_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_176_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_176_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_176_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_176_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_176_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_176_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_176_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_176_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_176_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_176_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_176_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_176_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_177 +#define DC_B_WINC_BD_COLOR_PALETTE_177 _MK_ADDR_CONST(0xcb1) +#define DC_B_WINC_BD_COLOR_PALETTE_177_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_177_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_177_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_177_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_177_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_177_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_177_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_177_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_177_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_177_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_177_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_177_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_177_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_177_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_177_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_177_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_177_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_177_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_177_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_177_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_177_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_177_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_177_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_177_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_177_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_177_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_177_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_177_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_177_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_177_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_177_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_177_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_177_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_177_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_177_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_178 +#define DC_B_WINC_BD_COLOR_PALETTE_178 _MK_ADDR_CONST(0xcb2) +#define DC_B_WINC_BD_COLOR_PALETTE_178_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_178_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_178_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_178_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_178_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_178_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_178_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_178_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_178_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_178_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_178_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_178_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_178_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_178_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_178_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_178_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_178_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_178_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_178_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_178_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_178_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_178_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_178_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_178_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_178_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_178_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_178_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_178_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_178_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_178_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_178_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_178_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_178_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_178_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_178_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_179 +#define DC_B_WINC_BD_COLOR_PALETTE_179 _MK_ADDR_CONST(0xcb3) +#define DC_B_WINC_BD_COLOR_PALETTE_179_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_179_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_179_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_179_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_179_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_179_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_179_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_179_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_179_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_179_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_179_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_179_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_179_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_179_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_179_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_179_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_179_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_179_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_179_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_179_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_179_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_179_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_179_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_179_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_179_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_179_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_179_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_179_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_179_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_179_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_179_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_179_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_179_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_179_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_179_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_180 +#define DC_B_WINC_BD_COLOR_PALETTE_180 _MK_ADDR_CONST(0xcb4) +#define DC_B_WINC_BD_COLOR_PALETTE_180_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_180_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_180_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_180_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_180_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_180_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_180_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_180_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_180_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_180_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_180_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_180_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_180_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_180_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_180_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_180_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_180_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_180_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_180_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_180_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_180_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_180_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_180_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_180_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_180_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_180_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_180_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_180_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_180_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_180_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_180_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_180_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_180_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_180_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_180_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_181 +#define DC_B_WINC_BD_COLOR_PALETTE_181 _MK_ADDR_CONST(0xcb5) +#define DC_B_WINC_BD_COLOR_PALETTE_181_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_181_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_181_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_181_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_181_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_181_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_181_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_181_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_181_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_181_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_181_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_181_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_181_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_181_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_181_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_181_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_181_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_181_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_181_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_181_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_181_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_181_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_181_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_181_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_181_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_181_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_181_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_181_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_181_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_181_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_181_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_181_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_181_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_181_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_181_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_182 +#define DC_B_WINC_BD_COLOR_PALETTE_182 _MK_ADDR_CONST(0xcb6) +#define DC_B_WINC_BD_COLOR_PALETTE_182_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_182_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_182_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_182_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_182_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_182_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_182_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_182_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_182_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_182_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_182_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_182_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_182_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_182_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_182_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_182_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_182_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_182_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_182_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_182_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_182_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_182_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_182_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_182_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_182_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_182_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_182_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_182_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_182_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_182_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_182_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_182_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_182_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_182_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_182_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_183 +#define DC_B_WINC_BD_COLOR_PALETTE_183 _MK_ADDR_CONST(0xcb7) +#define DC_B_WINC_BD_COLOR_PALETTE_183_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_183_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_183_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_183_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_183_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_183_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_183_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_183_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_183_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_183_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_183_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_183_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_183_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_183_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_183_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_183_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_183_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_183_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_183_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_183_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_183_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_183_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_183_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_183_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_183_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_183_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_183_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_183_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_183_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_183_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_183_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_183_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_183_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_183_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_183_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_184 +#define DC_B_WINC_BD_COLOR_PALETTE_184 _MK_ADDR_CONST(0xcb8) +#define DC_B_WINC_BD_COLOR_PALETTE_184_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_184_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_184_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_184_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_184_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_184_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_184_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_184_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_184_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_184_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_184_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_184_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_184_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_184_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_184_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_184_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_184_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_184_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_184_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_184_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_184_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_184_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_184_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_184_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_184_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_184_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_184_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_184_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_184_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_184_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_184_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_184_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_184_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_184_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_184_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_185 +#define DC_B_WINC_BD_COLOR_PALETTE_185 _MK_ADDR_CONST(0xcb9) +#define DC_B_WINC_BD_COLOR_PALETTE_185_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_185_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_185_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_185_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_185_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_185_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_185_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_185_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_185_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_185_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_185_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_185_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_185_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_185_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_185_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_185_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_185_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_185_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_185_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_185_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_185_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_185_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_185_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_185_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_185_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_185_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_185_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_185_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_185_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_185_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_185_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_185_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_185_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_185_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_185_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_186 +#define DC_B_WINC_BD_COLOR_PALETTE_186 _MK_ADDR_CONST(0xcba) +#define DC_B_WINC_BD_COLOR_PALETTE_186_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_186_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_186_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_186_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_186_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_186_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_186_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_186_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_186_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_186_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_186_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_186_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_186_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_186_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_186_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_186_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_186_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_186_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_186_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_186_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_186_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_186_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_186_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_186_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_186_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_186_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_186_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_186_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_186_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_186_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_186_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_186_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_186_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_186_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_186_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_187 +#define DC_B_WINC_BD_COLOR_PALETTE_187 _MK_ADDR_CONST(0xcbb) +#define DC_B_WINC_BD_COLOR_PALETTE_187_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_187_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_187_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_187_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_187_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_187_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_187_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_187_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_187_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_187_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_187_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_187_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_187_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_187_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_187_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_187_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_187_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_187_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_187_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_187_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_187_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_187_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_187_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_187_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_187_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_187_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_187_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_187_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_187_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_187_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_187_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_187_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_187_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_187_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_187_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_188 +#define DC_B_WINC_BD_COLOR_PALETTE_188 _MK_ADDR_CONST(0xcbc) +#define DC_B_WINC_BD_COLOR_PALETTE_188_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_188_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_188_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_188_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_188_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_188_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_188_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_188_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_188_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_188_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_188_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_188_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_188_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_188_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_188_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_188_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_188_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_188_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_188_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_188_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_188_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_188_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_188_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_188_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_188_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_188_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_188_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_188_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_188_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_188_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_188_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_188_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_188_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_188_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_188_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_189 +#define DC_B_WINC_BD_COLOR_PALETTE_189 _MK_ADDR_CONST(0xcbd) +#define DC_B_WINC_BD_COLOR_PALETTE_189_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_189_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_189_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_189_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_189_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_189_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_189_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_189_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_189_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_189_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_189_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_189_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_189_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_189_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_189_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_189_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_189_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_189_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_189_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_189_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_189_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_189_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_189_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_189_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_189_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_189_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_189_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_189_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_189_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_189_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_189_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_189_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_189_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_189_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_189_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_190 +#define DC_B_WINC_BD_COLOR_PALETTE_190 _MK_ADDR_CONST(0xcbe) +#define DC_B_WINC_BD_COLOR_PALETTE_190_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_190_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_190_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_190_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_190_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_190_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_190_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_190_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_190_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_190_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_190_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_190_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_190_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_190_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_190_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_190_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_190_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_190_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_190_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_190_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_190_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_190_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_190_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_190_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_190_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_190_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_190_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_190_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_190_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_190_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_190_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_190_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_190_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_190_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_190_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_191 +#define DC_B_WINC_BD_COLOR_PALETTE_191 _MK_ADDR_CONST(0xcbf) +#define DC_B_WINC_BD_COLOR_PALETTE_191_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_191_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_191_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_191_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_191_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_191_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_191_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_191_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_191_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_191_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_191_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_191_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_191_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_191_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_191_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_191_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_191_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_191_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_191_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_191_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_191_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_191_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_191_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_191_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_191_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_191_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_191_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_191_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_191_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_191_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_191_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_191_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_191_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_191_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_191_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_192 +#define DC_B_WINC_BD_COLOR_PALETTE_192 _MK_ADDR_CONST(0xcc0) +#define DC_B_WINC_BD_COLOR_PALETTE_192_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_192_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_192_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_192_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_192_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_192_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_192_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_192_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_192_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_192_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_192_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_192_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_192_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_192_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_192_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_192_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_192_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_192_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_192_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_192_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_192_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_192_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_192_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_192_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_192_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_192_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_192_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_192_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_192_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_192_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_192_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_192_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_192_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_192_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_192_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_193 +#define DC_B_WINC_BD_COLOR_PALETTE_193 _MK_ADDR_CONST(0xcc1) +#define DC_B_WINC_BD_COLOR_PALETTE_193_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_193_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_193_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_193_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_193_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_193_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_193_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_193_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_193_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_193_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_193_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_193_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_193_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_193_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_193_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_193_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_193_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_193_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_193_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_193_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_193_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_193_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_193_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_193_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_193_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_193_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_193_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_193_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_193_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_193_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_193_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_193_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_193_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_193_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_193_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_194 +#define DC_B_WINC_BD_COLOR_PALETTE_194 _MK_ADDR_CONST(0xcc2) +#define DC_B_WINC_BD_COLOR_PALETTE_194_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_194_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_194_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_194_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_194_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_194_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_194_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_194_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_194_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_194_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_194_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_194_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_194_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_194_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_194_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_194_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_194_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_194_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_194_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_194_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_194_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_194_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_194_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_194_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_194_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_194_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_194_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_194_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_194_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_194_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_194_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_194_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_194_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_194_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_194_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_195 +#define DC_B_WINC_BD_COLOR_PALETTE_195 _MK_ADDR_CONST(0xcc3) +#define DC_B_WINC_BD_COLOR_PALETTE_195_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_195_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_195_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_195_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_195_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_195_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_195_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_195_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_195_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_195_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_195_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_195_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_195_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_195_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_195_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_195_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_195_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_195_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_195_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_195_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_195_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_195_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_195_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_195_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_195_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_195_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_195_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_195_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_195_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_195_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_195_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_195_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_195_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_195_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_195_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_196 +#define DC_B_WINC_BD_COLOR_PALETTE_196 _MK_ADDR_CONST(0xcc4) +#define DC_B_WINC_BD_COLOR_PALETTE_196_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_196_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_196_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_196_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_196_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_196_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_196_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_196_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_196_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_196_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_196_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_196_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_196_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_196_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_196_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_196_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_196_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_196_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_196_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_196_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_196_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_196_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_196_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_196_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_196_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_196_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_196_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_196_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_196_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_196_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_196_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_196_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_196_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_196_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_196_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_197 +#define DC_B_WINC_BD_COLOR_PALETTE_197 _MK_ADDR_CONST(0xcc5) +#define DC_B_WINC_BD_COLOR_PALETTE_197_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_197_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_197_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_197_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_197_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_197_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_197_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_197_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_197_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_197_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_197_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_197_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_197_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_197_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_197_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_197_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_197_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_197_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_197_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_197_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_197_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_197_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_197_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_197_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_197_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_197_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_197_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_197_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_197_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_197_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_197_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_197_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_197_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_197_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_197_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_198 +#define DC_B_WINC_BD_COLOR_PALETTE_198 _MK_ADDR_CONST(0xcc6) +#define DC_B_WINC_BD_COLOR_PALETTE_198_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_198_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_198_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_198_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_198_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_198_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_198_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_198_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_198_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_198_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_198_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_198_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_198_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_198_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_198_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_198_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_198_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_198_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_198_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_198_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_198_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_198_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_198_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_198_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_198_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_198_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_198_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_198_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_198_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_198_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_198_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_198_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_198_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_198_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_198_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_199 +#define DC_B_WINC_BD_COLOR_PALETTE_199 _MK_ADDR_CONST(0xcc7) +#define DC_B_WINC_BD_COLOR_PALETTE_199_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_199_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_199_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_199_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_199_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_199_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_199_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_199_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_199_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_199_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_199_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_199_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_199_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_199_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_199_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_199_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_199_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_199_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_199_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_199_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_199_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_199_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_199_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_199_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_199_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_199_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_199_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_199_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_199_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_199_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_199_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_199_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_199_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_199_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_199_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_200 +#define DC_B_WINC_BD_COLOR_PALETTE_200 _MK_ADDR_CONST(0xcc8) +#define DC_B_WINC_BD_COLOR_PALETTE_200_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_200_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_200_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_200_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_200_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_200_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_200_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_200_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_200_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_200_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_200_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_200_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_200_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_200_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_200_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_200_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_200_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_200_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_200_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_200_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_200_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_200_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_200_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_200_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_200_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_200_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_200_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_200_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_200_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_200_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_200_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_200_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_200_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_200_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_200_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_201 +#define DC_B_WINC_BD_COLOR_PALETTE_201 _MK_ADDR_CONST(0xcc9) +#define DC_B_WINC_BD_COLOR_PALETTE_201_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_201_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_201_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_201_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_201_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_201_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_201_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_201_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_201_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_201_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_201_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_201_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_201_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_201_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_201_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_201_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_201_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_201_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_201_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_201_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_201_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_201_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_201_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_201_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_201_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_201_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_201_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_201_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_201_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_201_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_201_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_201_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_201_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_201_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_201_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_202 +#define DC_B_WINC_BD_COLOR_PALETTE_202 _MK_ADDR_CONST(0xcca) +#define DC_B_WINC_BD_COLOR_PALETTE_202_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_202_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_202_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_202_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_202_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_202_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_202_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_202_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_202_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_202_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_202_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_202_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_202_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_202_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_202_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_202_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_202_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_202_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_202_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_202_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_202_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_202_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_202_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_202_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_202_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_202_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_202_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_202_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_202_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_202_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_202_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_202_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_202_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_202_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_202_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_203 +#define DC_B_WINC_BD_COLOR_PALETTE_203 _MK_ADDR_CONST(0xccb) +#define DC_B_WINC_BD_COLOR_PALETTE_203_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_203_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_203_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_203_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_203_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_203_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_203_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_203_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_203_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_203_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_203_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_203_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_203_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_203_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_203_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_203_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_203_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_203_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_203_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_203_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_203_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_203_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_203_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_203_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_203_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_203_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_203_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_203_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_203_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_203_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_203_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_203_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_203_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_203_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_203_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_204 +#define DC_B_WINC_BD_COLOR_PALETTE_204 _MK_ADDR_CONST(0xccc) +#define DC_B_WINC_BD_COLOR_PALETTE_204_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_204_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_204_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_204_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_204_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_204_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_204_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_204_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_204_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_204_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_204_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_204_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_204_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_204_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_204_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_204_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_204_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_204_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_204_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_204_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_204_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_204_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_204_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_204_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_204_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_204_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_204_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_204_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_204_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_204_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_204_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_204_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_204_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_204_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_204_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_205 +#define DC_B_WINC_BD_COLOR_PALETTE_205 _MK_ADDR_CONST(0xccd) +#define DC_B_WINC_BD_COLOR_PALETTE_205_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_205_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_205_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_205_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_205_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_205_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_205_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_205_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_205_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_205_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_205_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_205_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_205_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_205_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_205_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_205_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_205_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_205_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_205_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_205_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_205_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_205_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_205_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_205_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_205_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_205_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_205_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_205_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_205_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_205_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_205_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_205_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_205_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_205_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_205_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_206 +#define DC_B_WINC_BD_COLOR_PALETTE_206 _MK_ADDR_CONST(0xcce) +#define DC_B_WINC_BD_COLOR_PALETTE_206_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_206_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_206_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_206_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_206_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_206_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_206_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_206_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_206_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_206_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_206_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_206_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_206_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_206_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_206_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_206_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_206_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_206_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_206_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_206_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_206_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_206_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_206_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_206_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_206_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_206_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_206_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_206_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_206_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_206_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_206_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_206_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_206_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_206_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_206_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_207 +#define DC_B_WINC_BD_COLOR_PALETTE_207 _MK_ADDR_CONST(0xccf) +#define DC_B_WINC_BD_COLOR_PALETTE_207_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_207_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_207_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_207_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_207_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_207_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_207_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_207_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_207_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_207_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_207_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_207_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_207_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_207_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_207_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_207_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_207_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_207_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_207_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_207_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_207_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_207_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_207_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_207_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_207_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_207_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_207_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_207_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_207_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_207_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_207_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_207_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_207_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_207_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_207_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_208 +#define DC_B_WINC_BD_COLOR_PALETTE_208 _MK_ADDR_CONST(0xcd0) +#define DC_B_WINC_BD_COLOR_PALETTE_208_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_208_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_208_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_208_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_208_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_208_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_208_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_208_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_208_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_208_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_208_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_208_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_208_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_208_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_208_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_208_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_208_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_208_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_208_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_208_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_208_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_208_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_208_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_208_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_208_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_208_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_208_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_208_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_208_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_208_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_208_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_208_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_208_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_208_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_208_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_209 +#define DC_B_WINC_BD_COLOR_PALETTE_209 _MK_ADDR_CONST(0xcd1) +#define DC_B_WINC_BD_COLOR_PALETTE_209_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_209_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_209_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_209_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_209_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_209_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_209_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_209_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_209_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_209_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_209_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_209_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_209_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_209_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_209_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_209_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_209_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_209_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_209_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_209_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_209_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_209_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_209_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_209_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_209_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_209_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_209_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_209_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_209_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_209_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_209_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_209_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_209_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_209_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_209_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_210 +#define DC_B_WINC_BD_COLOR_PALETTE_210 _MK_ADDR_CONST(0xcd2) +#define DC_B_WINC_BD_COLOR_PALETTE_210_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_210_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_210_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_210_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_210_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_210_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_210_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_210_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_210_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_210_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_210_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_210_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_210_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_210_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_210_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_210_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_210_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_210_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_210_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_210_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_210_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_210_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_210_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_210_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_210_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_210_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_210_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_210_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_210_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_210_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_210_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_210_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_210_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_210_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_210_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_211 +#define DC_B_WINC_BD_COLOR_PALETTE_211 _MK_ADDR_CONST(0xcd3) +#define DC_B_WINC_BD_COLOR_PALETTE_211_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_211_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_211_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_211_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_211_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_211_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_211_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_211_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_211_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_211_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_211_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_211_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_211_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_211_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_211_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_211_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_211_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_211_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_211_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_211_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_211_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_211_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_211_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_211_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_211_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_211_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_211_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_211_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_211_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_211_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_211_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_211_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_211_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_211_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_211_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_212 +#define DC_B_WINC_BD_COLOR_PALETTE_212 _MK_ADDR_CONST(0xcd4) +#define DC_B_WINC_BD_COLOR_PALETTE_212_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_212_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_212_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_212_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_212_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_212_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_212_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_212_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_212_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_212_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_212_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_212_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_212_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_212_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_212_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_212_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_212_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_212_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_212_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_212_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_212_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_212_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_212_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_212_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_212_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_212_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_212_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_212_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_212_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_212_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_212_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_212_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_212_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_212_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_212_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_213 +#define DC_B_WINC_BD_COLOR_PALETTE_213 _MK_ADDR_CONST(0xcd5) +#define DC_B_WINC_BD_COLOR_PALETTE_213_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_213_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_213_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_213_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_213_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_213_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_213_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_213_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_213_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_213_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_213_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_213_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_213_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_213_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_213_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_213_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_213_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_213_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_213_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_213_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_213_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_213_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_213_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_213_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_213_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_213_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_213_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_213_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_213_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_213_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_213_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_213_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_213_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_213_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_213_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_214 +#define DC_B_WINC_BD_COLOR_PALETTE_214 _MK_ADDR_CONST(0xcd6) +#define DC_B_WINC_BD_COLOR_PALETTE_214_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_214_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_214_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_214_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_214_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_214_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_214_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_214_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_214_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_214_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_214_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_214_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_214_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_214_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_214_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_214_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_214_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_214_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_214_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_214_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_214_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_214_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_214_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_214_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_214_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_214_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_214_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_214_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_214_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_214_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_214_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_214_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_214_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_214_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_214_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_215 +#define DC_B_WINC_BD_COLOR_PALETTE_215 _MK_ADDR_CONST(0xcd7) +#define DC_B_WINC_BD_COLOR_PALETTE_215_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_215_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_215_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_215_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_215_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_215_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_215_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_215_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_215_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_215_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_215_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_215_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_215_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_215_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_215_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_215_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_215_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_215_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_215_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_215_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_215_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_215_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_215_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_215_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_215_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_215_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_215_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_215_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_215_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_215_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_215_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_215_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_215_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_215_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_215_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_216 +#define DC_B_WINC_BD_COLOR_PALETTE_216 _MK_ADDR_CONST(0xcd8) +#define DC_B_WINC_BD_COLOR_PALETTE_216_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_216_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_216_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_216_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_216_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_216_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_216_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_216_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_216_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_216_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_216_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_216_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_216_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_216_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_216_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_216_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_216_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_216_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_216_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_216_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_216_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_216_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_216_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_216_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_216_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_216_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_216_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_216_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_216_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_216_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_216_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_216_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_216_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_216_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_216_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_217 +#define DC_B_WINC_BD_COLOR_PALETTE_217 _MK_ADDR_CONST(0xcd9) +#define DC_B_WINC_BD_COLOR_PALETTE_217_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_217_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_217_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_217_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_217_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_217_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_217_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_217_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_217_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_217_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_217_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_217_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_217_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_217_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_217_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_217_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_217_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_217_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_217_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_217_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_217_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_217_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_217_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_217_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_217_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_217_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_217_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_217_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_217_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_217_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_217_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_217_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_217_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_217_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_217_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_218 +#define DC_B_WINC_BD_COLOR_PALETTE_218 _MK_ADDR_CONST(0xcda) +#define DC_B_WINC_BD_COLOR_PALETTE_218_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_218_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_218_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_218_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_218_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_218_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_218_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_218_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_218_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_218_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_218_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_218_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_218_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_218_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_218_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_218_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_218_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_218_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_218_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_218_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_218_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_218_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_218_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_218_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_218_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_218_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_218_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_218_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_218_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_218_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_218_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_218_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_218_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_218_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_218_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_219 +#define DC_B_WINC_BD_COLOR_PALETTE_219 _MK_ADDR_CONST(0xcdb) +#define DC_B_WINC_BD_COLOR_PALETTE_219_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_219_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_219_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_219_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_219_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_219_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_219_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_219_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_219_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_219_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_219_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_219_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_219_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_219_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_219_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_219_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_219_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_219_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_219_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_219_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_219_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_219_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_219_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_219_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_219_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_219_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_219_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_219_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_219_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_219_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_219_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_219_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_219_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_219_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_219_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_220 +#define DC_B_WINC_BD_COLOR_PALETTE_220 _MK_ADDR_CONST(0xcdc) +#define DC_B_WINC_BD_COLOR_PALETTE_220_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_220_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_220_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_220_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_220_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_220_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_220_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_220_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_220_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_220_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_220_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_220_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_220_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_220_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_220_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_220_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_220_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_220_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_220_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_220_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_220_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_220_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_220_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_220_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_220_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_220_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_220_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_220_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_220_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_220_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_220_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_220_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_220_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_220_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_220_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_221 +#define DC_B_WINC_BD_COLOR_PALETTE_221 _MK_ADDR_CONST(0xcdd) +#define DC_B_WINC_BD_COLOR_PALETTE_221_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_221_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_221_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_221_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_221_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_221_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_221_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_221_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_221_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_221_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_221_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_221_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_221_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_221_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_221_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_221_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_221_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_221_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_221_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_221_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_221_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_221_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_221_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_221_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_221_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_221_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_221_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_221_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_221_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_221_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_221_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_221_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_221_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_221_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_221_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_222 +#define DC_B_WINC_BD_COLOR_PALETTE_222 _MK_ADDR_CONST(0xcde) +#define DC_B_WINC_BD_COLOR_PALETTE_222_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_222_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_222_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_222_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_222_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_222_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_222_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_222_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_222_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_222_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_222_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_222_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_222_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_222_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_222_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_222_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_222_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_222_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_222_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_222_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_222_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_222_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_222_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_222_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_222_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_222_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_222_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_222_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_222_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_222_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_222_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_222_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_222_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_222_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_222_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_223 +#define DC_B_WINC_BD_COLOR_PALETTE_223 _MK_ADDR_CONST(0xcdf) +#define DC_B_WINC_BD_COLOR_PALETTE_223_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_223_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_223_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_223_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_223_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_223_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_223_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_223_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_223_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_223_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_223_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_223_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_223_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_223_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_223_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_223_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_223_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_223_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_223_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_223_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_223_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_223_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_223_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_223_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_223_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_223_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_223_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_223_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_223_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_223_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_223_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_223_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_223_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_223_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_223_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_224 +#define DC_B_WINC_BD_COLOR_PALETTE_224 _MK_ADDR_CONST(0xce0) +#define DC_B_WINC_BD_COLOR_PALETTE_224_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_224_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_224_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_224_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_224_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_224_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_224_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_224_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_224_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_224_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_224_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_224_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_224_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_224_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_224_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_224_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_224_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_224_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_224_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_224_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_224_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_224_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_224_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_224_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_224_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_224_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_224_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_224_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_224_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_224_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_224_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_224_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_224_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_224_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_224_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_225 +#define DC_B_WINC_BD_COLOR_PALETTE_225 _MK_ADDR_CONST(0xce1) +#define DC_B_WINC_BD_COLOR_PALETTE_225_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_225_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_225_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_225_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_225_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_225_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_225_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_225_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_225_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_225_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_225_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_225_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_225_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_225_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_225_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_225_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_225_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_225_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_225_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_225_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_225_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_225_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_225_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_225_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_225_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_225_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_225_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_225_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_225_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_225_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_225_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_225_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_225_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_225_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_225_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_226 +#define DC_B_WINC_BD_COLOR_PALETTE_226 _MK_ADDR_CONST(0xce2) +#define DC_B_WINC_BD_COLOR_PALETTE_226_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_226_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_226_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_226_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_226_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_226_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_226_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_226_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_226_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_226_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_226_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_226_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_226_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_226_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_226_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_226_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_226_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_226_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_226_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_226_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_226_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_226_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_226_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_226_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_226_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_226_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_226_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_226_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_226_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_226_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_226_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_226_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_226_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_226_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_226_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_227 +#define DC_B_WINC_BD_COLOR_PALETTE_227 _MK_ADDR_CONST(0xce3) +#define DC_B_WINC_BD_COLOR_PALETTE_227_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_227_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_227_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_227_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_227_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_227_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_227_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_227_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_227_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_227_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_227_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_227_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_227_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_227_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_227_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_227_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_227_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_227_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_227_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_227_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_227_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_227_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_227_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_227_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_227_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_227_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_227_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_227_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_227_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_227_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_227_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_227_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_227_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_227_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_227_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_228 +#define DC_B_WINC_BD_COLOR_PALETTE_228 _MK_ADDR_CONST(0xce4) +#define DC_B_WINC_BD_COLOR_PALETTE_228_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_228_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_228_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_228_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_228_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_228_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_228_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_228_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_228_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_228_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_228_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_228_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_228_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_228_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_228_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_228_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_228_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_228_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_228_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_228_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_228_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_228_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_228_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_228_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_228_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_228_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_228_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_228_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_228_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_228_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_228_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_228_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_228_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_228_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_228_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_229 +#define DC_B_WINC_BD_COLOR_PALETTE_229 _MK_ADDR_CONST(0xce5) +#define DC_B_WINC_BD_COLOR_PALETTE_229_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_229_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_229_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_229_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_229_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_229_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_229_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_229_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_229_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_229_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_229_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_229_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_229_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_229_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_229_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_229_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_229_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_229_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_229_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_229_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_229_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_229_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_229_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_229_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_229_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_229_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_229_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_229_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_229_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_229_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_229_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_229_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_229_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_229_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_229_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_230 +#define DC_B_WINC_BD_COLOR_PALETTE_230 _MK_ADDR_CONST(0xce6) +#define DC_B_WINC_BD_COLOR_PALETTE_230_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_230_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_230_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_230_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_230_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_230_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_230_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_230_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_230_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_230_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_230_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_230_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_230_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_230_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_230_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_230_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_230_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_230_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_230_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_230_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_230_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_230_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_230_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_230_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_230_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_230_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_230_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_230_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_230_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_230_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_230_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_230_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_230_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_230_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_230_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_231 +#define DC_B_WINC_BD_COLOR_PALETTE_231 _MK_ADDR_CONST(0xce7) +#define DC_B_WINC_BD_COLOR_PALETTE_231_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_231_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_231_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_231_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_231_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_231_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_231_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_231_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_231_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_231_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_231_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_231_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_231_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_231_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_231_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_231_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_231_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_231_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_231_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_231_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_231_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_231_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_231_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_231_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_231_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_231_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_231_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_231_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_231_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_231_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_231_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_231_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_231_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_231_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_231_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_232 +#define DC_B_WINC_BD_COLOR_PALETTE_232 _MK_ADDR_CONST(0xce8) +#define DC_B_WINC_BD_COLOR_PALETTE_232_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_232_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_232_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_232_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_232_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_232_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_232_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_232_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_232_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_232_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_232_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_232_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_232_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_232_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_232_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_232_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_232_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_232_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_232_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_232_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_232_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_232_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_232_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_232_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_232_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_232_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_232_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_232_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_232_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_232_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_232_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_232_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_232_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_232_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_232_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_233 +#define DC_B_WINC_BD_COLOR_PALETTE_233 _MK_ADDR_CONST(0xce9) +#define DC_B_WINC_BD_COLOR_PALETTE_233_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_233_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_233_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_233_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_233_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_233_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_233_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_233_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_233_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_233_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_233_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_233_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_233_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_233_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_233_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_233_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_233_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_233_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_233_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_233_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_233_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_233_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_233_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_233_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_233_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_233_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_233_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_233_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_233_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_233_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_233_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_233_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_233_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_233_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_233_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_234 +#define DC_B_WINC_BD_COLOR_PALETTE_234 _MK_ADDR_CONST(0xcea) +#define DC_B_WINC_BD_COLOR_PALETTE_234_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_234_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_234_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_234_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_234_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_234_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_234_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_234_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_234_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_234_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_234_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_234_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_234_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_234_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_234_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_234_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_234_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_234_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_234_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_234_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_234_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_234_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_234_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_234_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_234_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_234_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_234_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_234_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_234_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_234_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_234_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_234_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_234_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_234_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_234_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_235 +#define DC_B_WINC_BD_COLOR_PALETTE_235 _MK_ADDR_CONST(0xceb) +#define DC_B_WINC_BD_COLOR_PALETTE_235_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_235_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_235_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_235_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_235_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_235_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_235_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_235_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_235_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_235_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_235_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_235_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_235_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_235_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_235_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_235_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_235_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_235_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_235_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_235_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_235_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_235_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_235_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_235_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_235_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_235_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_235_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_235_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_235_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_235_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_235_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_235_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_235_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_235_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_235_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_236 +#define DC_B_WINC_BD_COLOR_PALETTE_236 _MK_ADDR_CONST(0xcec) +#define DC_B_WINC_BD_COLOR_PALETTE_236_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_236_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_236_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_236_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_236_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_236_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_236_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_236_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_236_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_236_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_236_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_236_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_236_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_236_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_236_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_236_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_236_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_236_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_236_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_236_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_236_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_236_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_236_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_236_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_236_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_236_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_236_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_236_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_236_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_236_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_236_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_236_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_236_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_236_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_236_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_237 +#define DC_B_WINC_BD_COLOR_PALETTE_237 _MK_ADDR_CONST(0xced) +#define DC_B_WINC_BD_COLOR_PALETTE_237_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_237_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_237_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_237_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_237_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_237_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_237_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_237_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_237_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_237_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_237_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_237_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_237_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_237_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_237_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_237_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_237_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_237_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_237_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_237_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_237_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_237_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_237_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_237_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_237_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_237_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_237_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_237_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_237_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_237_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_237_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_237_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_237_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_237_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_237_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_238 +#define DC_B_WINC_BD_COLOR_PALETTE_238 _MK_ADDR_CONST(0xcee) +#define DC_B_WINC_BD_COLOR_PALETTE_238_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_238_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_238_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_238_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_238_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_238_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_238_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_238_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_238_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_238_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_238_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_238_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_238_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_238_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_238_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_238_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_238_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_238_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_238_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_238_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_238_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_238_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_238_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_238_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_238_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_238_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_238_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_238_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_238_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_238_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_238_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_238_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_238_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_238_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_238_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_239 +#define DC_B_WINC_BD_COLOR_PALETTE_239 _MK_ADDR_CONST(0xcef) +#define DC_B_WINC_BD_COLOR_PALETTE_239_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_239_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_239_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_239_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_239_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_239_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_239_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_239_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_239_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_239_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_239_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_239_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_239_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_239_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_239_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_239_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_239_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_239_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_239_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_239_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_239_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_239_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_239_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_239_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_239_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_239_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_239_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_239_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_239_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_239_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_239_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_239_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_239_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_239_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_239_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_240 +#define DC_B_WINC_BD_COLOR_PALETTE_240 _MK_ADDR_CONST(0xcf0) +#define DC_B_WINC_BD_COLOR_PALETTE_240_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_240_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_240_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_240_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_240_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_240_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_240_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_240_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_240_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_240_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_240_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_240_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_240_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_240_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_240_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_240_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_240_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_240_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_240_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_240_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_240_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_240_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_240_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_240_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_240_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_240_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_240_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_240_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_240_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_240_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_240_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_240_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_240_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_240_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_240_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_241 +#define DC_B_WINC_BD_COLOR_PALETTE_241 _MK_ADDR_CONST(0xcf1) +#define DC_B_WINC_BD_COLOR_PALETTE_241_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_241_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_241_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_241_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_241_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_241_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_241_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_241_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_241_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_241_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_241_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_241_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_241_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_241_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_241_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_241_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_241_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_241_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_241_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_241_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_241_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_241_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_241_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_241_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_241_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_241_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_241_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_241_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_241_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_241_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_241_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_241_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_241_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_241_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_241_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_242 +#define DC_B_WINC_BD_COLOR_PALETTE_242 _MK_ADDR_CONST(0xcf2) +#define DC_B_WINC_BD_COLOR_PALETTE_242_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_242_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_242_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_242_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_242_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_242_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_242_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_242_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_242_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_242_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_242_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_242_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_242_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_242_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_242_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_242_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_242_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_242_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_242_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_242_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_242_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_242_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_242_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_242_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_242_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_242_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_242_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_242_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_242_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_242_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_242_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_242_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_242_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_242_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_242_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_243 +#define DC_B_WINC_BD_COLOR_PALETTE_243 _MK_ADDR_CONST(0xcf3) +#define DC_B_WINC_BD_COLOR_PALETTE_243_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_243_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_243_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_243_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_243_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_243_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_243_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_243_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_243_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_243_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_243_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_243_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_243_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_243_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_243_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_243_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_243_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_243_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_243_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_243_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_243_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_243_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_243_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_243_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_243_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_243_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_243_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_243_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_243_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_243_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_243_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_243_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_243_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_243_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_243_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_244 +#define DC_B_WINC_BD_COLOR_PALETTE_244 _MK_ADDR_CONST(0xcf4) +#define DC_B_WINC_BD_COLOR_PALETTE_244_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_244_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_244_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_244_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_244_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_244_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_244_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_244_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_244_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_244_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_244_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_244_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_244_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_244_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_244_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_244_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_244_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_244_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_244_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_244_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_244_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_244_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_244_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_244_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_244_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_244_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_244_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_244_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_244_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_244_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_244_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_244_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_244_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_244_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_244_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_245 +#define DC_B_WINC_BD_COLOR_PALETTE_245 _MK_ADDR_CONST(0xcf5) +#define DC_B_WINC_BD_COLOR_PALETTE_245_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_245_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_245_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_245_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_245_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_245_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_245_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_245_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_245_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_245_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_245_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_245_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_245_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_245_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_245_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_245_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_245_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_245_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_245_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_245_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_245_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_245_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_245_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_245_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_245_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_245_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_245_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_245_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_245_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_245_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_245_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_245_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_245_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_245_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_245_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_246 +#define DC_B_WINC_BD_COLOR_PALETTE_246 _MK_ADDR_CONST(0xcf6) +#define DC_B_WINC_BD_COLOR_PALETTE_246_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_246_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_246_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_246_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_246_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_246_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_246_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_246_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_246_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_246_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_246_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_246_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_246_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_246_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_246_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_246_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_246_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_246_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_246_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_246_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_246_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_246_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_246_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_246_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_246_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_246_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_246_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_246_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_246_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_246_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_246_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_246_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_246_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_246_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_246_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_247 +#define DC_B_WINC_BD_COLOR_PALETTE_247 _MK_ADDR_CONST(0xcf7) +#define DC_B_WINC_BD_COLOR_PALETTE_247_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_247_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_247_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_247_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_247_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_247_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_247_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_247_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_247_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_247_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_247_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_247_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_247_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_247_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_247_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_247_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_247_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_247_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_247_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_247_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_247_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_247_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_247_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_247_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_247_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_247_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_247_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_247_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_247_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_247_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_247_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_247_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_247_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_247_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_247_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_248 +#define DC_B_WINC_BD_COLOR_PALETTE_248 _MK_ADDR_CONST(0xcf8) +#define DC_B_WINC_BD_COLOR_PALETTE_248_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_248_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_248_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_248_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_248_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_248_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_248_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_248_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_248_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_248_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_248_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_248_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_248_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_248_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_248_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_248_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_248_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_248_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_248_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_248_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_248_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_248_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_248_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_248_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_248_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_248_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_248_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_248_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_248_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_248_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_248_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_248_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_248_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_248_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_248_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_249 +#define DC_B_WINC_BD_COLOR_PALETTE_249 _MK_ADDR_CONST(0xcf9) +#define DC_B_WINC_BD_COLOR_PALETTE_249_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_249_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_249_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_249_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_249_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_249_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_249_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_249_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_249_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_249_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_249_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_249_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_249_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_249_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_249_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_249_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_249_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_249_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_249_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_249_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_249_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_249_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_249_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_249_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_249_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_249_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_249_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_249_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_249_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_249_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_249_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_249_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_249_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_249_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_249_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_250 +#define DC_B_WINC_BD_COLOR_PALETTE_250 _MK_ADDR_CONST(0xcfa) +#define DC_B_WINC_BD_COLOR_PALETTE_250_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_250_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_250_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_250_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_250_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_250_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_250_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_250_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_250_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_250_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_250_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_250_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_250_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_250_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_250_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_250_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_250_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_250_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_250_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_250_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_250_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_250_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_250_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_250_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_250_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_250_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_250_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_250_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_250_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_250_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_250_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_250_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_250_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_250_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_250_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_251 +#define DC_B_WINC_BD_COLOR_PALETTE_251 _MK_ADDR_CONST(0xcfb) +#define DC_B_WINC_BD_COLOR_PALETTE_251_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_251_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_251_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_251_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_251_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_251_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_251_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_251_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_251_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_251_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_251_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_251_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_251_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_251_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_251_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_251_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_251_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_251_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_251_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_251_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_251_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_251_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_251_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_251_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_251_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_251_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_251_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_251_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_251_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_251_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_251_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_251_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_251_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_251_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_251_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_252 +#define DC_B_WINC_BD_COLOR_PALETTE_252 _MK_ADDR_CONST(0xcfc) +#define DC_B_WINC_BD_COLOR_PALETTE_252_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_252_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_252_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_252_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_252_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_252_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_252_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_252_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_252_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_252_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_252_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_252_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_252_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_252_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_252_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_252_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_252_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_252_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_252_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_252_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_252_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_252_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_252_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_252_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_252_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_252_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_252_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_252_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_252_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_252_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_252_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_252_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_252_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_252_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_252_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_253 +#define DC_B_WINC_BD_COLOR_PALETTE_253 _MK_ADDR_CONST(0xcfd) +#define DC_B_WINC_BD_COLOR_PALETTE_253_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_253_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_253_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_253_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_253_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_253_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_253_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_253_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_253_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_253_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_253_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_253_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_253_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_253_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_253_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_253_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_253_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_253_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_253_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_253_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_253_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_253_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_253_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_253_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_253_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_253_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_253_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_253_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_253_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_253_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_253_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_253_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_253_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_253_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_253_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_254 +#define DC_B_WINC_BD_COLOR_PALETTE_254 _MK_ADDR_CONST(0xcfe) +#define DC_B_WINC_BD_COLOR_PALETTE_254_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_254_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_254_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_254_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_254_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_254_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_254_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_254_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_254_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_254_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_254_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_254_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_254_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_254_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_254_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_254_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_254_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_254_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_254_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_254_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_254_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_254_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_254_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_254_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_254_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_254_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_254_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_254_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_254_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_254_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_254_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_254_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_254_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_254_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_254_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Ram DC_B_WINC_BD_COLOR_PALETTE_255 +#define DC_B_WINC_BD_COLOR_PALETTE_255 _MK_ADDR_CONST(0xcff) +#define DC_B_WINC_BD_COLOR_PALETTE_255_SECURE 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_255_WORD_COUNT 0x1 +#define DC_B_WINC_BD_COLOR_PALETTE_255_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_255_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_255_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_255_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_255_READ_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_255_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define DC_B_WINC_BD_COLOR_PALETTE_255_BD_COLOR_PALETTE_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_COLOR_PALETTE_255_BD_COLOR_PALETTE_R_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_255_BD_COLOR_PALETTE_R_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_255_BD_COLOR_PALETTE_R_RANGE 7:0 +#define DC_B_WINC_BD_COLOR_PALETTE_255_BD_COLOR_PALETTE_R_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_255_BD_COLOR_PALETTE_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_255_BD_COLOR_PALETTE_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_255_BD_COLOR_PALETTE_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_255_BD_COLOR_PALETTE_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_255_BD_COLOR_PALETTE_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_COLOR_PALETTE_255_BD_COLOR_PALETTE_G_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_255_BD_COLOR_PALETTE_G_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_255_BD_COLOR_PALETTE_G_RANGE 15:8 +#define DC_B_WINC_BD_COLOR_PALETTE_255_BD_COLOR_PALETTE_G_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_255_BD_COLOR_PALETTE_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_255_BD_COLOR_PALETTE_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_255_BD_COLOR_PALETTE_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_255_BD_COLOR_PALETTE_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_COLOR_PALETTE_255_BD_COLOR_PALETTE_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_COLOR_PALETTE_255_BD_COLOR_PALETTE_B_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_COLOR_PALETTE_255_BD_COLOR_PALETTE_B_SHIFT) +#define DC_B_WINC_BD_COLOR_PALETTE_255_BD_COLOR_PALETTE_B_RANGE 23:16 +#define DC_B_WINC_BD_COLOR_PALETTE_255_BD_COLOR_PALETTE_B_WOFFSET 0x0 +#define DC_B_WINC_BD_COLOR_PALETTE_255_BD_COLOR_PALETTE_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_255_BD_COLOR_PALETTE_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_255_BD_COLOR_PALETTE_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_COLOR_PALETTE_255_BD_COLOR_PALETTE_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_B_WINC_BD_PALETTE_COLOR_EXT_0 +#define DC_B_WINC_BD_PALETTE_COLOR_EXT_0 _MK_ADDR_CONST(0xd00) +#define DC_B_WINC_BD_PALETTE_COLOR_EXT_0_SECURE 0x0 +#define DC_B_WINC_BD_PALETTE_COLOR_EXT_0_WORD_COUNT 0x1 +#define DC_B_WINC_BD_PALETTE_COLOR_EXT_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_PALETTE_COLOR_EXT_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_PALETTE_COLOR_EXT_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_PALETTE_COLOR_EXT_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_PALETTE_COLOR_EXT_0_READ_MASK _MK_MASK_CONST(0xfe) +#define DC_B_WINC_BD_PALETTE_COLOR_EXT_0_WRITE_MASK _MK_MASK_CONST(0xfe) +#define DC_B_WINC_BD_PALETTE_COLOR_EXT_0_BD_PALETTE_COLOR_EXT_SHIFT _MK_SHIFT_CONST(1) +#define DC_B_WINC_BD_PALETTE_COLOR_EXT_0_BD_PALETTE_COLOR_EXT_FIELD _MK_FIELD_CONST(0x7f, DC_B_WINC_BD_PALETTE_COLOR_EXT_0_BD_PALETTE_COLOR_EXT_SHIFT) +#define DC_B_WINC_BD_PALETTE_COLOR_EXT_0_BD_PALETTE_COLOR_EXT_RANGE 7:1 +#define DC_B_WINC_BD_PALETTE_COLOR_EXT_0_BD_PALETTE_COLOR_EXT_WOFFSET 0x0 +#define DC_B_WINC_BD_PALETTE_COLOR_EXT_0_BD_PALETTE_COLOR_EXT_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_PALETTE_COLOR_EXT_0_BD_PALETTE_COLOR_EXT_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_PALETTE_COLOR_EXT_0_BD_PALETTE_COLOR_EXT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_PALETTE_COLOR_EXT_0_BD_PALETTE_COLOR_EXT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_B_WINC_BD_H_FILTER_P00_0 +#define DC_B_WINC_BD_H_FILTER_P00_0 _MK_ADDR_CONST(0xd01) +#define DC_B_WINC_BD_H_FILTER_P00_0_SECURE 0x0 +#define DC_B_WINC_BD_H_FILTER_P00_0_WORD_COUNT 0x1 +#define DC_B_WINC_BD_H_FILTER_P00_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P00_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P00_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P00_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P00_0_READ_MASK _MK_MASK_CONST(0xffffffff) +#define DC_B_WINC_BD_H_FILTER_P00_0_WRITE_MASK _MK_MASK_CONST(0xffffffff) +#define DC_B_WINC_BD_H_FILTER_P00_0_BD_H_FILTER_P00C0_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_H_FILTER_P00_0_BD_H_FILTER_P00C0_FIELD _MK_FIELD_CONST(0x7, DC_B_WINC_BD_H_FILTER_P00_0_BD_H_FILTER_P00C0_SHIFT) +#define DC_B_WINC_BD_H_FILTER_P00_0_BD_H_FILTER_P00C0_RANGE 2:0 +#define DC_B_WINC_BD_H_FILTER_P00_0_BD_H_FILTER_P00C0_WOFFSET 0x0 +#define DC_B_WINC_BD_H_FILTER_P00_0_BD_H_FILTER_P00C0_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P00_0_BD_H_FILTER_P00C0_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P00_0_BD_H_FILTER_P00C0_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P00_0_BD_H_FILTER_P00C0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_H_FILTER_P00_0_BD_H_FILTER_P00C1_SHIFT _MK_SHIFT_CONST(3) +#define DC_B_WINC_BD_H_FILTER_P00_0_BD_H_FILTER_P00C1_FIELD _MK_FIELD_CONST(0x1f, DC_B_WINC_BD_H_FILTER_P00_0_BD_H_FILTER_P00C1_SHIFT) +#define DC_B_WINC_BD_H_FILTER_P00_0_BD_H_FILTER_P00C1_RANGE 7:3 +#define DC_B_WINC_BD_H_FILTER_P00_0_BD_H_FILTER_P00C1_WOFFSET 0x0 +#define DC_B_WINC_BD_H_FILTER_P00_0_BD_H_FILTER_P00C1_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P00_0_BD_H_FILTER_P00C1_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P00_0_BD_H_FILTER_P00C1_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P00_0_BD_H_FILTER_P00C1_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_H_FILTER_P00_0_BD_H_FILTER_P00C2_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_H_FILTER_P00_0_BD_H_FILTER_P00C2_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_H_FILTER_P00_0_BD_H_FILTER_P00C2_SHIFT) +#define DC_B_WINC_BD_H_FILTER_P00_0_BD_H_FILTER_P00C2_RANGE 15:8 +#define DC_B_WINC_BD_H_FILTER_P00_0_BD_H_FILTER_P00C2_WOFFSET 0x0 +#define DC_B_WINC_BD_H_FILTER_P00_0_BD_H_FILTER_P00C2_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P00_0_BD_H_FILTER_P00C2_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P00_0_BD_H_FILTER_P00C2_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P00_0_BD_H_FILTER_P00C2_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_H_FILTER_P00_0_BD_H_FILTER_P00C3_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_H_FILTER_P00_0_BD_H_FILTER_P00C3_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_H_FILTER_P00_0_BD_H_FILTER_P00C3_SHIFT) +#define DC_B_WINC_BD_H_FILTER_P00_0_BD_H_FILTER_P00C3_RANGE 23:16 +#define DC_B_WINC_BD_H_FILTER_P00_0_BD_H_FILTER_P00C3_WOFFSET 0x0 +#define DC_B_WINC_BD_H_FILTER_P00_0_BD_H_FILTER_P00C3_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P00_0_BD_H_FILTER_P00C3_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P00_0_BD_H_FILTER_P00C3_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P00_0_BD_H_FILTER_P00C3_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_H_FILTER_P00_0_BD_H_FILTER_P00C4_SHIFT _MK_SHIFT_CONST(24) +#define DC_B_WINC_BD_H_FILTER_P00_0_BD_H_FILTER_P00C4_FIELD _MK_FIELD_CONST(0x1f, DC_B_WINC_BD_H_FILTER_P00_0_BD_H_FILTER_P00C4_SHIFT) +#define DC_B_WINC_BD_H_FILTER_P00_0_BD_H_FILTER_P00C4_RANGE 28:24 +#define DC_B_WINC_BD_H_FILTER_P00_0_BD_H_FILTER_P00C4_WOFFSET 0x0 +#define DC_B_WINC_BD_H_FILTER_P00_0_BD_H_FILTER_P00C4_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P00_0_BD_H_FILTER_P00C4_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P00_0_BD_H_FILTER_P00C4_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P00_0_BD_H_FILTER_P00C4_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_H_FILTER_P00_0_BD_H_FILTER_P00C5_SHIFT _MK_SHIFT_CONST(29) +#define DC_B_WINC_BD_H_FILTER_P00_0_BD_H_FILTER_P00C5_FIELD _MK_FIELD_CONST(0x7, DC_B_WINC_BD_H_FILTER_P00_0_BD_H_FILTER_P00C5_SHIFT) +#define DC_B_WINC_BD_H_FILTER_P00_0_BD_H_FILTER_P00C5_RANGE 31:29 +#define DC_B_WINC_BD_H_FILTER_P00_0_BD_H_FILTER_P00C5_WOFFSET 0x0 +#define DC_B_WINC_BD_H_FILTER_P00_0_BD_H_FILTER_P00C5_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P00_0_BD_H_FILTER_P00C5_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P00_0_BD_H_FILTER_P00C5_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P00_0_BD_H_FILTER_P00C5_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_B_WINC_BD_H_FILTER_P01_0 +#define DC_B_WINC_BD_H_FILTER_P01_0 _MK_ADDR_CONST(0xd02) +#define DC_B_WINC_BD_H_FILTER_P01_0_SECURE 0x0 +#define DC_B_WINC_BD_H_FILTER_P01_0_WORD_COUNT 0x1 +#define DC_B_WINC_BD_H_FILTER_P01_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P01_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P01_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P01_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P01_0_READ_MASK _MK_MASK_CONST(0xffffffff) +#define DC_B_WINC_BD_H_FILTER_P01_0_WRITE_MASK _MK_MASK_CONST(0xffffffff) +#define DC_B_WINC_BD_H_FILTER_P01_0_BD_H_FILTER_P01C0_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_H_FILTER_P01_0_BD_H_FILTER_P01C0_FIELD _MK_FIELD_CONST(0x7, DC_B_WINC_BD_H_FILTER_P01_0_BD_H_FILTER_P01C0_SHIFT) +#define DC_B_WINC_BD_H_FILTER_P01_0_BD_H_FILTER_P01C0_RANGE 2:0 +#define DC_B_WINC_BD_H_FILTER_P01_0_BD_H_FILTER_P01C0_WOFFSET 0x0 +#define DC_B_WINC_BD_H_FILTER_P01_0_BD_H_FILTER_P01C0_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P01_0_BD_H_FILTER_P01C0_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P01_0_BD_H_FILTER_P01C0_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P01_0_BD_H_FILTER_P01C0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_H_FILTER_P01_0_BD_H_FILTER_P01C1_SHIFT _MK_SHIFT_CONST(3) +#define DC_B_WINC_BD_H_FILTER_P01_0_BD_H_FILTER_P01C1_FIELD _MK_FIELD_CONST(0x1f, DC_B_WINC_BD_H_FILTER_P01_0_BD_H_FILTER_P01C1_SHIFT) +#define DC_B_WINC_BD_H_FILTER_P01_0_BD_H_FILTER_P01C1_RANGE 7:3 +#define DC_B_WINC_BD_H_FILTER_P01_0_BD_H_FILTER_P01C1_WOFFSET 0x0 +#define DC_B_WINC_BD_H_FILTER_P01_0_BD_H_FILTER_P01C1_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P01_0_BD_H_FILTER_P01C1_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P01_0_BD_H_FILTER_P01C1_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P01_0_BD_H_FILTER_P01C1_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_H_FILTER_P01_0_BD_H_FILTER_P01C2_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_H_FILTER_P01_0_BD_H_FILTER_P01C2_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_H_FILTER_P01_0_BD_H_FILTER_P01C2_SHIFT) +#define DC_B_WINC_BD_H_FILTER_P01_0_BD_H_FILTER_P01C2_RANGE 15:8 +#define DC_B_WINC_BD_H_FILTER_P01_0_BD_H_FILTER_P01C2_WOFFSET 0x0 +#define DC_B_WINC_BD_H_FILTER_P01_0_BD_H_FILTER_P01C2_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P01_0_BD_H_FILTER_P01C2_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P01_0_BD_H_FILTER_P01C2_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P01_0_BD_H_FILTER_P01C2_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_H_FILTER_P01_0_BD_H_FILTER_P01C3_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_H_FILTER_P01_0_BD_H_FILTER_P01C3_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_H_FILTER_P01_0_BD_H_FILTER_P01C3_SHIFT) +#define DC_B_WINC_BD_H_FILTER_P01_0_BD_H_FILTER_P01C3_RANGE 23:16 +#define DC_B_WINC_BD_H_FILTER_P01_0_BD_H_FILTER_P01C3_WOFFSET 0x0 +#define DC_B_WINC_BD_H_FILTER_P01_0_BD_H_FILTER_P01C3_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P01_0_BD_H_FILTER_P01C3_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P01_0_BD_H_FILTER_P01C3_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P01_0_BD_H_FILTER_P01C3_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_H_FILTER_P01_0_BD_H_FILTER_P01C4_SHIFT _MK_SHIFT_CONST(24) +#define DC_B_WINC_BD_H_FILTER_P01_0_BD_H_FILTER_P01C4_FIELD _MK_FIELD_CONST(0x1f, DC_B_WINC_BD_H_FILTER_P01_0_BD_H_FILTER_P01C4_SHIFT) +#define DC_B_WINC_BD_H_FILTER_P01_0_BD_H_FILTER_P01C4_RANGE 28:24 +#define DC_B_WINC_BD_H_FILTER_P01_0_BD_H_FILTER_P01C4_WOFFSET 0x0 +#define DC_B_WINC_BD_H_FILTER_P01_0_BD_H_FILTER_P01C4_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P01_0_BD_H_FILTER_P01C4_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P01_0_BD_H_FILTER_P01C4_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P01_0_BD_H_FILTER_P01C4_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_H_FILTER_P01_0_BD_H_FILTER_P01C5_SHIFT _MK_SHIFT_CONST(29) +#define DC_B_WINC_BD_H_FILTER_P01_0_BD_H_FILTER_P01C5_FIELD _MK_FIELD_CONST(0x7, DC_B_WINC_BD_H_FILTER_P01_0_BD_H_FILTER_P01C5_SHIFT) +#define DC_B_WINC_BD_H_FILTER_P01_0_BD_H_FILTER_P01C5_RANGE 31:29 +#define DC_B_WINC_BD_H_FILTER_P01_0_BD_H_FILTER_P01C5_WOFFSET 0x0 +#define DC_B_WINC_BD_H_FILTER_P01_0_BD_H_FILTER_P01C5_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P01_0_BD_H_FILTER_P01C5_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P01_0_BD_H_FILTER_P01C5_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P01_0_BD_H_FILTER_P01C5_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_B_WINC_BD_H_FILTER_P02_0 +#define DC_B_WINC_BD_H_FILTER_P02_0 _MK_ADDR_CONST(0xd03) +#define DC_B_WINC_BD_H_FILTER_P02_0_SECURE 0x0 +#define DC_B_WINC_BD_H_FILTER_P02_0_WORD_COUNT 0x1 +#define DC_B_WINC_BD_H_FILTER_P02_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P02_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P02_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P02_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P02_0_READ_MASK _MK_MASK_CONST(0xffffffff) +#define DC_B_WINC_BD_H_FILTER_P02_0_WRITE_MASK _MK_MASK_CONST(0xffffffff) +#define DC_B_WINC_BD_H_FILTER_P02_0_BD_H_FILTER_P02C0_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_H_FILTER_P02_0_BD_H_FILTER_P02C0_FIELD _MK_FIELD_CONST(0x7, DC_B_WINC_BD_H_FILTER_P02_0_BD_H_FILTER_P02C0_SHIFT) +#define DC_B_WINC_BD_H_FILTER_P02_0_BD_H_FILTER_P02C0_RANGE 2:0 +#define DC_B_WINC_BD_H_FILTER_P02_0_BD_H_FILTER_P02C0_WOFFSET 0x0 +#define DC_B_WINC_BD_H_FILTER_P02_0_BD_H_FILTER_P02C0_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P02_0_BD_H_FILTER_P02C0_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P02_0_BD_H_FILTER_P02C0_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P02_0_BD_H_FILTER_P02C0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_H_FILTER_P02_0_BD_H_FILTER_P02C1_SHIFT _MK_SHIFT_CONST(3) +#define DC_B_WINC_BD_H_FILTER_P02_0_BD_H_FILTER_P02C1_FIELD _MK_FIELD_CONST(0x1f, DC_B_WINC_BD_H_FILTER_P02_0_BD_H_FILTER_P02C1_SHIFT) +#define DC_B_WINC_BD_H_FILTER_P02_0_BD_H_FILTER_P02C1_RANGE 7:3 +#define DC_B_WINC_BD_H_FILTER_P02_0_BD_H_FILTER_P02C1_WOFFSET 0x0 +#define DC_B_WINC_BD_H_FILTER_P02_0_BD_H_FILTER_P02C1_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P02_0_BD_H_FILTER_P02C1_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P02_0_BD_H_FILTER_P02C1_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P02_0_BD_H_FILTER_P02C1_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_H_FILTER_P02_0_BD_H_FILTER_P02C2_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_H_FILTER_P02_0_BD_H_FILTER_P02C2_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_H_FILTER_P02_0_BD_H_FILTER_P02C2_SHIFT) +#define DC_B_WINC_BD_H_FILTER_P02_0_BD_H_FILTER_P02C2_RANGE 15:8 +#define DC_B_WINC_BD_H_FILTER_P02_0_BD_H_FILTER_P02C2_WOFFSET 0x0 +#define DC_B_WINC_BD_H_FILTER_P02_0_BD_H_FILTER_P02C2_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P02_0_BD_H_FILTER_P02C2_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P02_0_BD_H_FILTER_P02C2_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P02_0_BD_H_FILTER_P02C2_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_H_FILTER_P02_0_BD_H_FILTER_P02C3_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_H_FILTER_P02_0_BD_H_FILTER_P02C3_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_H_FILTER_P02_0_BD_H_FILTER_P02C3_SHIFT) +#define DC_B_WINC_BD_H_FILTER_P02_0_BD_H_FILTER_P02C3_RANGE 23:16 +#define DC_B_WINC_BD_H_FILTER_P02_0_BD_H_FILTER_P02C3_WOFFSET 0x0 +#define DC_B_WINC_BD_H_FILTER_P02_0_BD_H_FILTER_P02C3_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P02_0_BD_H_FILTER_P02C3_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P02_0_BD_H_FILTER_P02C3_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P02_0_BD_H_FILTER_P02C3_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_H_FILTER_P02_0_BD_H_FILTER_P02C4_SHIFT _MK_SHIFT_CONST(24) +#define DC_B_WINC_BD_H_FILTER_P02_0_BD_H_FILTER_P02C4_FIELD _MK_FIELD_CONST(0x1f, DC_B_WINC_BD_H_FILTER_P02_0_BD_H_FILTER_P02C4_SHIFT) +#define DC_B_WINC_BD_H_FILTER_P02_0_BD_H_FILTER_P02C4_RANGE 28:24 +#define DC_B_WINC_BD_H_FILTER_P02_0_BD_H_FILTER_P02C4_WOFFSET 0x0 +#define DC_B_WINC_BD_H_FILTER_P02_0_BD_H_FILTER_P02C4_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P02_0_BD_H_FILTER_P02C4_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P02_0_BD_H_FILTER_P02C4_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P02_0_BD_H_FILTER_P02C4_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_H_FILTER_P02_0_BD_H_FILTER_P02C5_SHIFT _MK_SHIFT_CONST(29) +#define DC_B_WINC_BD_H_FILTER_P02_0_BD_H_FILTER_P02C5_FIELD _MK_FIELD_CONST(0x7, DC_B_WINC_BD_H_FILTER_P02_0_BD_H_FILTER_P02C5_SHIFT) +#define DC_B_WINC_BD_H_FILTER_P02_0_BD_H_FILTER_P02C5_RANGE 31:29 +#define DC_B_WINC_BD_H_FILTER_P02_0_BD_H_FILTER_P02C5_WOFFSET 0x0 +#define DC_B_WINC_BD_H_FILTER_P02_0_BD_H_FILTER_P02C5_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P02_0_BD_H_FILTER_P02C5_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P02_0_BD_H_FILTER_P02C5_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P02_0_BD_H_FILTER_P02C5_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_B_WINC_BD_H_FILTER_P03_0 +#define DC_B_WINC_BD_H_FILTER_P03_0 _MK_ADDR_CONST(0xd04) +#define DC_B_WINC_BD_H_FILTER_P03_0_SECURE 0x0 +#define DC_B_WINC_BD_H_FILTER_P03_0_WORD_COUNT 0x1 +#define DC_B_WINC_BD_H_FILTER_P03_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P03_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P03_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P03_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P03_0_READ_MASK _MK_MASK_CONST(0xffffffff) +#define DC_B_WINC_BD_H_FILTER_P03_0_WRITE_MASK _MK_MASK_CONST(0xffffffff) +#define DC_B_WINC_BD_H_FILTER_P03_0_BD_H_FILTER_P03C0_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_H_FILTER_P03_0_BD_H_FILTER_P03C0_FIELD _MK_FIELD_CONST(0x7, DC_B_WINC_BD_H_FILTER_P03_0_BD_H_FILTER_P03C0_SHIFT) +#define DC_B_WINC_BD_H_FILTER_P03_0_BD_H_FILTER_P03C0_RANGE 2:0 +#define DC_B_WINC_BD_H_FILTER_P03_0_BD_H_FILTER_P03C0_WOFFSET 0x0 +#define DC_B_WINC_BD_H_FILTER_P03_0_BD_H_FILTER_P03C0_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P03_0_BD_H_FILTER_P03C0_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P03_0_BD_H_FILTER_P03C0_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P03_0_BD_H_FILTER_P03C0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_H_FILTER_P03_0_BD_H_FILTER_P03C1_SHIFT _MK_SHIFT_CONST(3) +#define DC_B_WINC_BD_H_FILTER_P03_0_BD_H_FILTER_P03C1_FIELD _MK_FIELD_CONST(0x1f, DC_B_WINC_BD_H_FILTER_P03_0_BD_H_FILTER_P03C1_SHIFT) +#define DC_B_WINC_BD_H_FILTER_P03_0_BD_H_FILTER_P03C1_RANGE 7:3 +#define DC_B_WINC_BD_H_FILTER_P03_0_BD_H_FILTER_P03C1_WOFFSET 0x0 +#define DC_B_WINC_BD_H_FILTER_P03_0_BD_H_FILTER_P03C1_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P03_0_BD_H_FILTER_P03C1_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P03_0_BD_H_FILTER_P03C1_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P03_0_BD_H_FILTER_P03C1_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_H_FILTER_P03_0_BD_H_FILTER_P03C2_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_H_FILTER_P03_0_BD_H_FILTER_P03C2_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_H_FILTER_P03_0_BD_H_FILTER_P03C2_SHIFT) +#define DC_B_WINC_BD_H_FILTER_P03_0_BD_H_FILTER_P03C2_RANGE 15:8 +#define DC_B_WINC_BD_H_FILTER_P03_0_BD_H_FILTER_P03C2_WOFFSET 0x0 +#define DC_B_WINC_BD_H_FILTER_P03_0_BD_H_FILTER_P03C2_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P03_0_BD_H_FILTER_P03C2_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P03_0_BD_H_FILTER_P03C2_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P03_0_BD_H_FILTER_P03C2_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_H_FILTER_P03_0_BD_H_FILTER_P03C3_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_H_FILTER_P03_0_BD_H_FILTER_P03C3_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_H_FILTER_P03_0_BD_H_FILTER_P03C3_SHIFT) +#define DC_B_WINC_BD_H_FILTER_P03_0_BD_H_FILTER_P03C3_RANGE 23:16 +#define DC_B_WINC_BD_H_FILTER_P03_0_BD_H_FILTER_P03C3_WOFFSET 0x0 +#define DC_B_WINC_BD_H_FILTER_P03_0_BD_H_FILTER_P03C3_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P03_0_BD_H_FILTER_P03C3_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P03_0_BD_H_FILTER_P03C3_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P03_0_BD_H_FILTER_P03C3_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_H_FILTER_P03_0_BD_H_FILTER_P03C4_SHIFT _MK_SHIFT_CONST(24) +#define DC_B_WINC_BD_H_FILTER_P03_0_BD_H_FILTER_P03C4_FIELD _MK_FIELD_CONST(0x1f, DC_B_WINC_BD_H_FILTER_P03_0_BD_H_FILTER_P03C4_SHIFT) +#define DC_B_WINC_BD_H_FILTER_P03_0_BD_H_FILTER_P03C4_RANGE 28:24 +#define DC_B_WINC_BD_H_FILTER_P03_0_BD_H_FILTER_P03C4_WOFFSET 0x0 +#define DC_B_WINC_BD_H_FILTER_P03_0_BD_H_FILTER_P03C4_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P03_0_BD_H_FILTER_P03C4_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P03_0_BD_H_FILTER_P03C4_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P03_0_BD_H_FILTER_P03C4_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_H_FILTER_P03_0_BD_H_FILTER_P03C5_SHIFT _MK_SHIFT_CONST(29) +#define DC_B_WINC_BD_H_FILTER_P03_0_BD_H_FILTER_P03C5_FIELD _MK_FIELD_CONST(0x7, DC_B_WINC_BD_H_FILTER_P03_0_BD_H_FILTER_P03C5_SHIFT) +#define DC_B_WINC_BD_H_FILTER_P03_0_BD_H_FILTER_P03C5_RANGE 31:29 +#define DC_B_WINC_BD_H_FILTER_P03_0_BD_H_FILTER_P03C5_WOFFSET 0x0 +#define DC_B_WINC_BD_H_FILTER_P03_0_BD_H_FILTER_P03C5_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P03_0_BD_H_FILTER_P03C5_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P03_0_BD_H_FILTER_P03C5_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P03_0_BD_H_FILTER_P03C5_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_B_WINC_BD_H_FILTER_P04_0 +#define DC_B_WINC_BD_H_FILTER_P04_0 _MK_ADDR_CONST(0xd05) +#define DC_B_WINC_BD_H_FILTER_P04_0_SECURE 0x0 +#define DC_B_WINC_BD_H_FILTER_P04_0_WORD_COUNT 0x1 +#define DC_B_WINC_BD_H_FILTER_P04_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P04_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P04_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P04_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P04_0_READ_MASK _MK_MASK_CONST(0xffffffff) +#define DC_B_WINC_BD_H_FILTER_P04_0_WRITE_MASK _MK_MASK_CONST(0xffffffff) +#define DC_B_WINC_BD_H_FILTER_P04_0_BD_H_FILTER_P04C0_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_H_FILTER_P04_0_BD_H_FILTER_P04C0_FIELD _MK_FIELD_CONST(0x7, DC_B_WINC_BD_H_FILTER_P04_0_BD_H_FILTER_P04C0_SHIFT) +#define DC_B_WINC_BD_H_FILTER_P04_0_BD_H_FILTER_P04C0_RANGE 2:0 +#define DC_B_WINC_BD_H_FILTER_P04_0_BD_H_FILTER_P04C0_WOFFSET 0x0 +#define DC_B_WINC_BD_H_FILTER_P04_0_BD_H_FILTER_P04C0_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P04_0_BD_H_FILTER_P04C0_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P04_0_BD_H_FILTER_P04C0_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P04_0_BD_H_FILTER_P04C0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_H_FILTER_P04_0_BD_H_FILTER_P04C1_SHIFT _MK_SHIFT_CONST(3) +#define DC_B_WINC_BD_H_FILTER_P04_0_BD_H_FILTER_P04C1_FIELD _MK_FIELD_CONST(0x1f, DC_B_WINC_BD_H_FILTER_P04_0_BD_H_FILTER_P04C1_SHIFT) +#define DC_B_WINC_BD_H_FILTER_P04_0_BD_H_FILTER_P04C1_RANGE 7:3 +#define DC_B_WINC_BD_H_FILTER_P04_0_BD_H_FILTER_P04C1_WOFFSET 0x0 +#define DC_B_WINC_BD_H_FILTER_P04_0_BD_H_FILTER_P04C1_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P04_0_BD_H_FILTER_P04C1_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P04_0_BD_H_FILTER_P04C1_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P04_0_BD_H_FILTER_P04C1_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_H_FILTER_P04_0_BD_H_FILTER_P04C2_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_H_FILTER_P04_0_BD_H_FILTER_P04C2_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_H_FILTER_P04_0_BD_H_FILTER_P04C2_SHIFT) +#define DC_B_WINC_BD_H_FILTER_P04_0_BD_H_FILTER_P04C2_RANGE 15:8 +#define DC_B_WINC_BD_H_FILTER_P04_0_BD_H_FILTER_P04C2_WOFFSET 0x0 +#define DC_B_WINC_BD_H_FILTER_P04_0_BD_H_FILTER_P04C2_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P04_0_BD_H_FILTER_P04C2_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P04_0_BD_H_FILTER_P04C2_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P04_0_BD_H_FILTER_P04C2_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_H_FILTER_P04_0_BD_H_FILTER_P04C3_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_H_FILTER_P04_0_BD_H_FILTER_P04C3_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_H_FILTER_P04_0_BD_H_FILTER_P04C3_SHIFT) +#define DC_B_WINC_BD_H_FILTER_P04_0_BD_H_FILTER_P04C3_RANGE 23:16 +#define DC_B_WINC_BD_H_FILTER_P04_0_BD_H_FILTER_P04C3_WOFFSET 0x0 +#define DC_B_WINC_BD_H_FILTER_P04_0_BD_H_FILTER_P04C3_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P04_0_BD_H_FILTER_P04C3_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P04_0_BD_H_FILTER_P04C3_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P04_0_BD_H_FILTER_P04C3_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_H_FILTER_P04_0_BD_H_FILTER_P04C4_SHIFT _MK_SHIFT_CONST(24) +#define DC_B_WINC_BD_H_FILTER_P04_0_BD_H_FILTER_P04C4_FIELD _MK_FIELD_CONST(0x1f, DC_B_WINC_BD_H_FILTER_P04_0_BD_H_FILTER_P04C4_SHIFT) +#define DC_B_WINC_BD_H_FILTER_P04_0_BD_H_FILTER_P04C4_RANGE 28:24 +#define DC_B_WINC_BD_H_FILTER_P04_0_BD_H_FILTER_P04C4_WOFFSET 0x0 +#define DC_B_WINC_BD_H_FILTER_P04_0_BD_H_FILTER_P04C4_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P04_0_BD_H_FILTER_P04C4_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P04_0_BD_H_FILTER_P04C4_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P04_0_BD_H_FILTER_P04C4_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_H_FILTER_P04_0_BD_H_FILTER_P04C5_SHIFT _MK_SHIFT_CONST(29) +#define DC_B_WINC_BD_H_FILTER_P04_0_BD_H_FILTER_P04C5_FIELD _MK_FIELD_CONST(0x7, DC_B_WINC_BD_H_FILTER_P04_0_BD_H_FILTER_P04C5_SHIFT) +#define DC_B_WINC_BD_H_FILTER_P04_0_BD_H_FILTER_P04C5_RANGE 31:29 +#define DC_B_WINC_BD_H_FILTER_P04_0_BD_H_FILTER_P04C5_WOFFSET 0x0 +#define DC_B_WINC_BD_H_FILTER_P04_0_BD_H_FILTER_P04C5_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P04_0_BD_H_FILTER_P04C5_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P04_0_BD_H_FILTER_P04C5_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P04_0_BD_H_FILTER_P04C5_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_B_WINC_BD_H_FILTER_P05_0 +#define DC_B_WINC_BD_H_FILTER_P05_0 _MK_ADDR_CONST(0xd06) +#define DC_B_WINC_BD_H_FILTER_P05_0_SECURE 0x0 +#define DC_B_WINC_BD_H_FILTER_P05_0_WORD_COUNT 0x1 +#define DC_B_WINC_BD_H_FILTER_P05_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P05_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P05_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P05_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P05_0_READ_MASK _MK_MASK_CONST(0xffffffff) +#define DC_B_WINC_BD_H_FILTER_P05_0_WRITE_MASK _MK_MASK_CONST(0xffffffff) +#define DC_B_WINC_BD_H_FILTER_P05_0_BD_H_FILTER_P05C0_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_H_FILTER_P05_0_BD_H_FILTER_P05C0_FIELD _MK_FIELD_CONST(0x7, DC_B_WINC_BD_H_FILTER_P05_0_BD_H_FILTER_P05C0_SHIFT) +#define DC_B_WINC_BD_H_FILTER_P05_0_BD_H_FILTER_P05C0_RANGE 2:0 +#define DC_B_WINC_BD_H_FILTER_P05_0_BD_H_FILTER_P05C0_WOFFSET 0x0 +#define DC_B_WINC_BD_H_FILTER_P05_0_BD_H_FILTER_P05C0_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P05_0_BD_H_FILTER_P05C0_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P05_0_BD_H_FILTER_P05C0_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P05_0_BD_H_FILTER_P05C0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_H_FILTER_P05_0_BD_H_FILTER_P05C1_SHIFT _MK_SHIFT_CONST(3) +#define DC_B_WINC_BD_H_FILTER_P05_0_BD_H_FILTER_P05C1_FIELD _MK_FIELD_CONST(0x1f, DC_B_WINC_BD_H_FILTER_P05_0_BD_H_FILTER_P05C1_SHIFT) +#define DC_B_WINC_BD_H_FILTER_P05_0_BD_H_FILTER_P05C1_RANGE 7:3 +#define DC_B_WINC_BD_H_FILTER_P05_0_BD_H_FILTER_P05C1_WOFFSET 0x0 +#define DC_B_WINC_BD_H_FILTER_P05_0_BD_H_FILTER_P05C1_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P05_0_BD_H_FILTER_P05C1_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P05_0_BD_H_FILTER_P05C1_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P05_0_BD_H_FILTER_P05C1_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_H_FILTER_P05_0_BD_H_FILTER_P05C2_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_H_FILTER_P05_0_BD_H_FILTER_P05C2_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_H_FILTER_P05_0_BD_H_FILTER_P05C2_SHIFT) +#define DC_B_WINC_BD_H_FILTER_P05_0_BD_H_FILTER_P05C2_RANGE 15:8 +#define DC_B_WINC_BD_H_FILTER_P05_0_BD_H_FILTER_P05C2_WOFFSET 0x0 +#define DC_B_WINC_BD_H_FILTER_P05_0_BD_H_FILTER_P05C2_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P05_0_BD_H_FILTER_P05C2_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P05_0_BD_H_FILTER_P05C2_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P05_0_BD_H_FILTER_P05C2_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_H_FILTER_P05_0_BD_H_FILTER_P05C3_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_H_FILTER_P05_0_BD_H_FILTER_P05C3_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_H_FILTER_P05_0_BD_H_FILTER_P05C3_SHIFT) +#define DC_B_WINC_BD_H_FILTER_P05_0_BD_H_FILTER_P05C3_RANGE 23:16 +#define DC_B_WINC_BD_H_FILTER_P05_0_BD_H_FILTER_P05C3_WOFFSET 0x0 +#define DC_B_WINC_BD_H_FILTER_P05_0_BD_H_FILTER_P05C3_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P05_0_BD_H_FILTER_P05C3_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P05_0_BD_H_FILTER_P05C3_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P05_0_BD_H_FILTER_P05C3_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_H_FILTER_P05_0_BD_H_FILTER_P05C4_SHIFT _MK_SHIFT_CONST(24) +#define DC_B_WINC_BD_H_FILTER_P05_0_BD_H_FILTER_P05C4_FIELD _MK_FIELD_CONST(0x1f, DC_B_WINC_BD_H_FILTER_P05_0_BD_H_FILTER_P05C4_SHIFT) +#define DC_B_WINC_BD_H_FILTER_P05_0_BD_H_FILTER_P05C4_RANGE 28:24 +#define DC_B_WINC_BD_H_FILTER_P05_0_BD_H_FILTER_P05C4_WOFFSET 0x0 +#define DC_B_WINC_BD_H_FILTER_P05_0_BD_H_FILTER_P05C4_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P05_0_BD_H_FILTER_P05C4_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P05_0_BD_H_FILTER_P05C4_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P05_0_BD_H_FILTER_P05C4_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_H_FILTER_P05_0_BD_H_FILTER_P05C5_SHIFT _MK_SHIFT_CONST(29) +#define DC_B_WINC_BD_H_FILTER_P05_0_BD_H_FILTER_P05C5_FIELD _MK_FIELD_CONST(0x7, DC_B_WINC_BD_H_FILTER_P05_0_BD_H_FILTER_P05C5_SHIFT) +#define DC_B_WINC_BD_H_FILTER_P05_0_BD_H_FILTER_P05C5_RANGE 31:29 +#define DC_B_WINC_BD_H_FILTER_P05_0_BD_H_FILTER_P05C5_WOFFSET 0x0 +#define DC_B_WINC_BD_H_FILTER_P05_0_BD_H_FILTER_P05C5_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P05_0_BD_H_FILTER_P05C5_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P05_0_BD_H_FILTER_P05C5_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P05_0_BD_H_FILTER_P05C5_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_B_WINC_BD_H_FILTER_P06_0 +#define DC_B_WINC_BD_H_FILTER_P06_0 _MK_ADDR_CONST(0xd07) +#define DC_B_WINC_BD_H_FILTER_P06_0_SECURE 0x0 +#define DC_B_WINC_BD_H_FILTER_P06_0_WORD_COUNT 0x1 +#define DC_B_WINC_BD_H_FILTER_P06_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P06_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P06_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P06_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P06_0_READ_MASK _MK_MASK_CONST(0xffffffff) +#define DC_B_WINC_BD_H_FILTER_P06_0_WRITE_MASK _MK_MASK_CONST(0xffffffff) +#define DC_B_WINC_BD_H_FILTER_P06_0_BD_H_FILTER_P06C0_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_H_FILTER_P06_0_BD_H_FILTER_P06C0_FIELD _MK_FIELD_CONST(0x7, DC_B_WINC_BD_H_FILTER_P06_0_BD_H_FILTER_P06C0_SHIFT) +#define DC_B_WINC_BD_H_FILTER_P06_0_BD_H_FILTER_P06C0_RANGE 2:0 +#define DC_B_WINC_BD_H_FILTER_P06_0_BD_H_FILTER_P06C0_WOFFSET 0x0 +#define DC_B_WINC_BD_H_FILTER_P06_0_BD_H_FILTER_P06C0_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P06_0_BD_H_FILTER_P06C0_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P06_0_BD_H_FILTER_P06C0_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P06_0_BD_H_FILTER_P06C0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_H_FILTER_P06_0_BD_H_FILTER_P06C1_SHIFT _MK_SHIFT_CONST(3) +#define DC_B_WINC_BD_H_FILTER_P06_0_BD_H_FILTER_P06C1_FIELD _MK_FIELD_CONST(0x1f, DC_B_WINC_BD_H_FILTER_P06_0_BD_H_FILTER_P06C1_SHIFT) +#define DC_B_WINC_BD_H_FILTER_P06_0_BD_H_FILTER_P06C1_RANGE 7:3 +#define DC_B_WINC_BD_H_FILTER_P06_0_BD_H_FILTER_P06C1_WOFFSET 0x0 +#define DC_B_WINC_BD_H_FILTER_P06_0_BD_H_FILTER_P06C1_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P06_0_BD_H_FILTER_P06C1_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P06_0_BD_H_FILTER_P06C1_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P06_0_BD_H_FILTER_P06C1_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_H_FILTER_P06_0_BD_H_FILTER_P06C2_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_H_FILTER_P06_0_BD_H_FILTER_P06C2_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_H_FILTER_P06_0_BD_H_FILTER_P06C2_SHIFT) +#define DC_B_WINC_BD_H_FILTER_P06_0_BD_H_FILTER_P06C2_RANGE 15:8 +#define DC_B_WINC_BD_H_FILTER_P06_0_BD_H_FILTER_P06C2_WOFFSET 0x0 +#define DC_B_WINC_BD_H_FILTER_P06_0_BD_H_FILTER_P06C2_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P06_0_BD_H_FILTER_P06C2_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P06_0_BD_H_FILTER_P06C2_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P06_0_BD_H_FILTER_P06C2_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_H_FILTER_P06_0_BD_H_FILTER_P06C3_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_H_FILTER_P06_0_BD_H_FILTER_P06C3_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_H_FILTER_P06_0_BD_H_FILTER_P06C3_SHIFT) +#define DC_B_WINC_BD_H_FILTER_P06_0_BD_H_FILTER_P06C3_RANGE 23:16 +#define DC_B_WINC_BD_H_FILTER_P06_0_BD_H_FILTER_P06C3_WOFFSET 0x0 +#define DC_B_WINC_BD_H_FILTER_P06_0_BD_H_FILTER_P06C3_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P06_0_BD_H_FILTER_P06C3_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P06_0_BD_H_FILTER_P06C3_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P06_0_BD_H_FILTER_P06C3_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_H_FILTER_P06_0_BD_H_FILTER_P06C4_SHIFT _MK_SHIFT_CONST(24) +#define DC_B_WINC_BD_H_FILTER_P06_0_BD_H_FILTER_P06C4_FIELD _MK_FIELD_CONST(0x1f, DC_B_WINC_BD_H_FILTER_P06_0_BD_H_FILTER_P06C4_SHIFT) +#define DC_B_WINC_BD_H_FILTER_P06_0_BD_H_FILTER_P06C4_RANGE 28:24 +#define DC_B_WINC_BD_H_FILTER_P06_0_BD_H_FILTER_P06C4_WOFFSET 0x0 +#define DC_B_WINC_BD_H_FILTER_P06_0_BD_H_FILTER_P06C4_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P06_0_BD_H_FILTER_P06C4_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P06_0_BD_H_FILTER_P06C4_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P06_0_BD_H_FILTER_P06C4_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_H_FILTER_P06_0_BD_H_FILTER_P06C5_SHIFT _MK_SHIFT_CONST(29) +#define DC_B_WINC_BD_H_FILTER_P06_0_BD_H_FILTER_P06C5_FIELD _MK_FIELD_CONST(0x7, DC_B_WINC_BD_H_FILTER_P06_0_BD_H_FILTER_P06C5_SHIFT) +#define DC_B_WINC_BD_H_FILTER_P06_0_BD_H_FILTER_P06C5_RANGE 31:29 +#define DC_B_WINC_BD_H_FILTER_P06_0_BD_H_FILTER_P06C5_WOFFSET 0x0 +#define DC_B_WINC_BD_H_FILTER_P06_0_BD_H_FILTER_P06C5_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P06_0_BD_H_FILTER_P06C5_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P06_0_BD_H_FILTER_P06C5_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P06_0_BD_H_FILTER_P06C5_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_B_WINC_BD_H_FILTER_P07_0 +#define DC_B_WINC_BD_H_FILTER_P07_0 _MK_ADDR_CONST(0xd08) +#define DC_B_WINC_BD_H_FILTER_P07_0_SECURE 0x0 +#define DC_B_WINC_BD_H_FILTER_P07_0_WORD_COUNT 0x1 +#define DC_B_WINC_BD_H_FILTER_P07_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P07_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P07_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P07_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P07_0_READ_MASK _MK_MASK_CONST(0xffffffff) +#define DC_B_WINC_BD_H_FILTER_P07_0_WRITE_MASK _MK_MASK_CONST(0xffffffff) +#define DC_B_WINC_BD_H_FILTER_P07_0_BD_H_FILTER_P07C0_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_H_FILTER_P07_0_BD_H_FILTER_P07C0_FIELD _MK_FIELD_CONST(0x7, DC_B_WINC_BD_H_FILTER_P07_0_BD_H_FILTER_P07C0_SHIFT) +#define DC_B_WINC_BD_H_FILTER_P07_0_BD_H_FILTER_P07C0_RANGE 2:0 +#define DC_B_WINC_BD_H_FILTER_P07_0_BD_H_FILTER_P07C0_WOFFSET 0x0 +#define DC_B_WINC_BD_H_FILTER_P07_0_BD_H_FILTER_P07C0_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P07_0_BD_H_FILTER_P07C0_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P07_0_BD_H_FILTER_P07C0_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P07_0_BD_H_FILTER_P07C0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_H_FILTER_P07_0_BD_H_FILTER_P07C1_SHIFT _MK_SHIFT_CONST(3) +#define DC_B_WINC_BD_H_FILTER_P07_0_BD_H_FILTER_P07C1_FIELD _MK_FIELD_CONST(0x1f, DC_B_WINC_BD_H_FILTER_P07_0_BD_H_FILTER_P07C1_SHIFT) +#define DC_B_WINC_BD_H_FILTER_P07_0_BD_H_FILTER_P07C1_RANGE 7:3 +#define DC_B_WINC_BD_H_FILTER_P07_0_BD_H_FILTER_P07C1_WOFFSET 0x0 +#define DC_B_WINC_BD_H_FILTER_P07_0_BD_H_FILTER_P07C1_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P07_0_BD_H_FILTER_P07C1_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P07_0_BD_H_FILTER_P07C1_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P07_0_BD_H_FILTER_P07C1_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_H_FILTER_P07_0_BD_H_FILTER_P07C2_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_H_FILTER_P07_0_BD_H_FILTER_P07C2_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_H_FILTER_P07_0_BD_H_FILTER_P07C2_SHIFT) +#define DC_B_WINC_BD_H_FILTER_P07_0_BD_H_FILTER_P07C2_RANGE 15:8 +#define DC_B_WINC_BD_H_FILTER_P07_0_BD_H_FILTER_P07C2_WOFFSET 0x0 +#define DC_B_WINC_BD_H_FILTER_P07_0_BD_H_FILTER_P07C2_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P07_0_BD_H_FILTER_P07C2_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P07_0_BD_H_FILTER_P07C2_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P07_0_BD_H_FILTER_P07C2_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_H_FILTER_P07_0_BD_H_FILTER_P07C3_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_H_FILTER_P07_0_BD_H_FILTER_P07C3_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_H_FILTER_P07_0_BD_H_FILTER_P07C3_SHIFT) +#define DC_B_WINC_BD_H_FILTER_P07_0_BD_H_FILTER_P07C3_RANGE 23:16 +#define DC_B_WINC_BD_H_FILTER_P07_0_BD_H_FILTER_P07C3_WOFFSET 0x0 +#define DC_B_WINC_BD_H_FILTER_P07_0_BD_H_FILTER_P07C3_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P07_0_BD_H_FILTER_P07C3_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P07_0_BD_H_FILTER_P07C3_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P07_0_BD_H_FILTER_P07C3_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_H_FILTER_P07_0_BD_H_FILTER_P07C4_SHIFT _MK_SHIFT_CONST(24) +#define DC_B_WINC_BD_H_FILTER_P07_0_BD_H_FILTER_P07C4_FIELD _MK_FIELD_CONST(0x1f, DC_B_WINC_BD_H_FILTER_P07_0_BD_H_FILTER_P07C4_SHIFT) +#define DC_B_WINC_BD_H_FILTER_P07_0_BD_H_FILTER_P07C4_RANGE 28:24 +#define DC_B_WINC_BD_H_FILTER_P07_0_BD_H_FILTER_P07C4_WOFFSET 0x0 +#define DC_B_WINC_BD_H_FILTER_P07_0_BD_H_FILTER_P07C4_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P07_0_BD_H_FILTER_P07C4_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P07_0_BD_H_FILTER_P07C4_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P07_0_BD_H_FILTER_P07C4_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_H_FILTER_P07_0_BD_H_FILTER_P07C5_SHIFT _MK_SHIFT_CONST(29) +#define DC_B_WINC_BD_H_FILTER_P07_0_BD_H_FILTER_P07C5_FIELD _MK_FIELD_CONST(0x7, DC_B_WINC_BD_H_FILTER_P07_0_BD_H_FILTER_P07C5_SHIFT) +#define DC_B_WINC_BD_H_FILTER_P07_0_BD_H_FILTER_P07C5_RANGE 31:29 +#define DC_B_WINC_BD_H_FILTER_P07_0_BD_H_FILTER_P07C5_WOFFSET 0x0 +#define DC_B_WINC_BD_H_FILTER_P07_0_BD_H_FILTER_P07C5_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P07_0_BD_H_FILTER_P07C5_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P07_0_BD_H_FILTER_P07C5_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P07_0_BD_H_FILTER_P07C5_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_B_WINC_BD_H_FILTER_P08_0 +#define DC_B_WINC_BD_H_FILTER_P08_0 _MK_ADDR_CONST(0xd09) +#define DC_B_WINC_BD_H_FILTER_P08_0_SECURE 0x0 +#define DC_B_WINC_BD_H_FILTER_P08_0_WORD_COUNT 0x1 +#define DC_B_WINC_BD_H_FILTER_P08_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P08_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P08_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P08_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P08_0_READ_MASK _MK_MASK_CONST(0xffffffff) +#define DC_B_WINC_BD_H_FILTER_P08_0_WRITE_MASK _MK_MASK_CONST(0xffffffff) +#define DC_B_WINC_BD_H_FILTER_P08_0_BD_H_FILTER_P08C0_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_H_FILTER_P08_0_BD_H_FILTER_P08C0_FIELD _MK_FIELD_CONST(0x7, DC_B_WINC_BD_H_FILTER_P08_0_BD_H_FILTER_P08C0_SHIFT) +#define DC_B_WINC_BD_H_FILTER_P08_0_BD_H_FILTER_P08C0_RANGE 2:0 +#define DC_B_WINC_BD_H_FILTER_P08_0_BD_H_FILTER_P08C0_WOFFSET 0x0 +#define DC_B_WINC_BD_H_FILTER_P08_0_BD_H_FILTER_P08C0_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P08_0_BD_H_FILTER_P08C0_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P08_0_BD_H_FILTER_P08C0_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P08_0_BD_H_FILTER_P08C0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_H_FILTER_P08_0_BD_H_FILTER_P08C1_SHIFT _MK_SHIFT_CONST(3) +#define DC_B_WINC_BD_H_FILTER_P08_0_BD_H_FILTER_P08C1_FIELD _MK_FIELD_CONST(0x1f, DC_B_WINC_BD_H_FILTER_P08_0_BD_H_FILTER_P08C1_SHIFT) +#define DC_B_WINC_BD_H_FILTER_P08_0_BD_H_FILTER_P08C1_RANGE 7:3 +#define DC_B_WINC_BD_H_FILTER_P08_0_BD_H_FILTER_P08C1_WOFFSET 0x0 +#define DC_B_WINC_BD_H_FILTER_P08_0_BD_H_FILTER_P08C1_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P08_0_BD_H_FILTER_P08C1_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P08_0_BD_H_FILTER_P08C1_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P08_0_BD_H_FILTER_P08C1_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_H_FILTER_P08_0_BD_H_FILTER_P08C2_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_H_FILTER_P08_0_BD_H_FILTER_P08C2_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_H_FILTER_P08_0_BD_H_FILTER_P08C2_SHIFT) +#define DC_B_WINC_BD_H_FILTER_P08_0_BD_H_FILTER_P08C2_RANGE 15:8 +#define DC_B_WINC_BD_H_FILTER_P08_0_BD_H_FILTER_P08C2_WOFFSET 0x0 +#define DC_B_WINC_BD_H_FILTER_P08_0_BD_H_FILTER_P08C2_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P08_0_BD_H_FILTER_P08C2_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P08_0_BD_H_FILTER_P08C2_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P08_0_BD_H_FILTER_P08C2_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_H_FILTER_P08_0_BD_H_FILTER_P08C3_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_H_FILTER_P08_0_BD_H_FILTER_P08C3_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_H_FILTER_P08_0_BD_H_FILTER_P08C3_SHIFT) +#define DC_B_WINC_BD_H_FILTER_P08_0_BD_H_FILTER_P08C3_RANGE 23:16 +#define DC_B_WINC_BD_H_FILTER_P08_0_BD_H_FILTER_P08C3_WOFFSET 0x0 +#define DC_B_WINC_BD_H_FILTER_P08_0_BD_H_FILTER_P08C3_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P08_0_BD_H_FILTER_P08C3_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P08_0_BD_H_FILTER_P08C3_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P08_0_BD_H_FILTER_P08C3_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_H_FILTER_P08_0_BD_H_FILTER_P08C4_SHIFT _MK_SHIFT_CONST(24) +#define DC_B_WINC_BD_H_FILTER_P08_0_BD_H_FILTER_P08C4_FIELD _MK_FIELD_CONST(0x1f, DC_B_WINC_BD_H_FILTER_P08_0_BD_H_FILTER_P08C4_SHIFT) +#define DC_B_WINC_BD_H_FILTER_P08_0_BD_H_FILTER_P08C4_RANGE 28:24 +#define DC_B_WINC_BD_H_FILTER_P08_0_BD_H_FILTER_P08C4_WOFFSET 0x0 +#define DC_B_WINC_BD_H_FILTER_P08_0_BD_H_FILTER_P08C4_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P08_0_BD_H_FILTER_P08C4_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P08_0_BD_H_FILTER_P08C4_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P08_0_BD_H_FILTER_P08C4_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_H_FILTER_P08_0_BD_H_FILTER_P08C5_SHIFT _MK_SHIFT_CONST(29) +#define DC_B_WINC_BD_H_FILTER_P08_0_BD_H_FILTER_P08C5_FIELD _MK_FIELD_CONST(0x7, DC_B_WINC_BD_H_FILTER_P08_0_BD_H_FILTER_P08C5_SHIFT) +#define DC_B_WINC_BD_H_FILTER_P08_0_BD_H_FILTER_P08C5_RANGE 31:29 +#define DC_B_WINC_BD_H_FILTER_P08_0_BD_H_FILTER_P08C5_WOFFSET 0x0 +#define DC_B_WINC_BD_H_FILTER_P08_0_BD_H_FILTER_P08C5_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P08_0_BD_H_FILTER_P08C5_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P08_0_BD_H_FILTER_P08C5_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P08_0_BD_H_FILTER_P08C5_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_B_WINC_BD_H_FILTER_P09_0 +#define DC_B_WINC_BD_H_FILTER_P09_0 _MK_ADDR_CONST(0xd0a) +#define DC_B_WINC_BD_H_FILTER_P09_0_SECURE 0x0 +#define DC_B_WINC_BD_H_FILTER_P09_0_WORD_COUNT 0x1 +#define DC_B_WINC_BD_H_FILTER_P09_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P09_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P09_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P09_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P09_0_READ_MASK _MK_MASK_CONST(0xffffffff) +#define DC_B_WINC_BD_H_FILTER_P09_0_WRITE_MASK _MK_MASK_CONST(0xffffffff) +#define DC_B_WINC_BD_H_FILTER_P09_0_BD_H_FILTER_P09C0_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_H_FILTER_P09_0_BD_H_FILTER_P09C0_FIELD _MK_FIELD_CONST(0x7, DC_B_WINC_BD_H_FILTER_P09_0_BD_H_FILTER_P09C0_SHIFT) +#define DC_B_WINC_BD_H_FILTER_P09_0_BD_H_FILTER_P09C0_RANGE 2:0 +#define DC_B_WINC_BD_H_FILTER_P09_0_BD_H_FILTER_P09C0_WOFFSET 0x0 +#define DC_B_WINC_BD_H_FILTER_P09_0_BD_H_FILTER_P09C0_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P09_0_BD_H_FILTER_P09C0_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P09_0_BD_H_FILTER_P09C0_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P09_0_BD_H_FILTER_P09C0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_H_FILTER_P09_0_BD_H_FILTER_P09C1_SHIFT _MK_SHIFT_CONST(3) +#define DC_B_WINC_BD_H_FILTER_P09_0_BD_H_FILTER_P09C1_FIELD _MK_FIELD_CONST(0x1f, DC_B_WINC_BD_H_FILTER_P09_0_BD_H_FILTER_P09C1_SHIFT) +#define DC_B_WINC_BD_H_FILTER_P09_0_BD_H_FILTER_P09C1_RANGE 7:3 +#define DC_B_WINC_BD_H_FILTER_P09_0_BD_H_FILTER_P09C1_WOFFSET 0x0 +#define DC_B_WINC_BD_H_FILTER_P09_0_BD_H_FILTER_P09C1_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P09_0_BD_H_FILTER_P09C1_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P09_0_BD_H_FILTER_P09C1_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P09_0_BD_H_FILTER_P09C1_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_H_FILTER_P09_0_BD_H_FILTER_P09C2_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_H_FILTER_P09_0_BD_H_FILTER_P09C2_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_H_FILTER_P09_0_BD_H_FILTER_P09C2_SHIFT) +#define DC_B_WINC_BD_H_FILTER_P09_0_BD_H_FILTER_P09C2_RANGE 15:8 +#define DC_B_WINC_BD_H_FILTER_P09_0_BD_H_FILTER_P09C2_WOFFSET 0x0 +#define DC_B_WINC_BD_H_FILTER_P09_0_BD_H_FILTER_P09C2_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P09_0_BD_H_FILTER_P09C2_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P09_0_BD_H_FILTER_P09C2_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P09_0_BD_H_FILTER_P09C2_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_H_FILTER_P09_0_BD_H_FILTER_P09C3_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_H_FILTER_P09_0_BD_H_FILTER_P09C3_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_H_FILTER_P09_0_BD_H_FILTER_P09C3_SHIFT) +#define DC_B_WINC_BD_H_FILTER_P09_0_BD_H_FILTER_P09C3_RANGE 23:16 +#define DC_B_WINC_BD_H_FILTER_P09_0_BD_H_FILTER_P09C3_WOFFSET 0x0 +#define DC_B_WINC_BD_H_FILTER_P09_0_BD_H_FILTER_P09C3_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P09_0_BD_H_FILTER_P09C3_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P09_0_BD_H_FILTER_P09C3_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P09_0_BD_H_FILTER_P09C3_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_H_FILTER_P09_0_BD_H_FILTER_P09C4_SHIFT _MK_SHIFT_CONST(24) +#define DC_B_WINC_BD_H_FILTER_P09_0_BD_H_FILTER_P09C4_FIELD _MK_FIELD_CONST(0x1f, DC_B_WINC_BD_H_FILTER_P09_0_BD_H_FILTER_P09C4_SHIFT) +#define DC_B_WINC_BD_H_FILTER_P09_0_BD_H_FILTER_P09C4_RANGE 28:24 +#define DC_B_WINC_BD_H_FILTER_P09_0_BD_H_FILTER_P09C4_WOFFSET 0x0 +#define DC_B_WINC_BD_H_FILTER_P09_0_BD_H_FILTER_P09C4_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P09_0_BD_H_FILTER_P09C4_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P09_0_BD_H_FILTER_P09C4_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P09_0_BD_H_FILTER_P09C4_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_H_FILTER_P09_0_BD_H_FILTER_P09C5_SHIFT _MK_SHIFT_CONST(29) +#define DC_B_WINC_BD_H_FILTER_P09_0_BD_H_FILTER_P09C5_FIELD _MK_FIELD_CONST(0x7, DC_B_WINC_BD_H_FILTER_P09_0_BD_H_FILTER_P09C5_SHIFT) +#define DC_B_WINC_BD_H_FILTER_P09_0_BD_H_FILTER_P09C5_RANGE 31:29 +#define DC_B_WINC_BD_H_FILTER_P09_0_BD_H_FILTER_P09C5_WOFFSET 0x0 +#define DC_B_WINC_BD_H_FILTER_P09_0_BD_H_FILTER_P09C5_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P09_0_BD_H_FILTER_P09C5_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P09_0_BD_H_FILTER_P09C5_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P09_0_BD_H_FILTER_P09C5_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_B_WINC_BD_H_FILTER_P0A_0 +#define DC_B_WINC_BD_H_FILTER_P0A_0 _MK_ADDR_CONST(0xd0b) +#define DC_B_WINC_BD_H_FILTER_P0A_0_SECURE 0x0 +#define DC_B_WINC_BD_H_FILTER_P0A_0_WORD_COUNT 0x1 +#define DC_B_WINC_BD_H_FILTER_P0A_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P0A_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P0A_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P0A_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P0A_0_READ_MASK _MK_MASK_CONST(0xffffffff) +#define DC_B_WINC_BD_H_FILTER_P0A_0_WRITE_MASK _MK_MASK_CONST(0xffffffff) +#define DC_B_WINC_BD_H_FILTER_P0A_0_BD_H_FILTER_P0AC0_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_H_FILTER_P0A_0_BD_H_FILTER_P0AC0_FIELD _MK_FIELD_CONST(0x7, DC_B_WINC_BD_H_FILTER_P0A_0_BD_H_FILTER_P0AC0_SHIFT) +#define DC_B_WINC_BD_H_FILTER_P0A_0_BD_H_FILTER_P0AC0_RANGE 2:0 +#define DC_B_WINC_BD_H_FILTER_P0A_0_BD_H_FILTER_P0AC0_WOFFSET 0x0 +#define DC_B_WINC_BD_H_FILTER_P0A_0_BD_H_FILTER_P0AC0_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P0A_0_BD_H_FILTER_P0AC0_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P0A_0_BD_H_FILTER_P0AC0_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P0A_0_BD_H_FILTER_P0AC0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_H_FILTER_P0A_0_BD_H_FILTER_P0AC1_SHIFT _MK_SHIFT_CONST(3) +#define DC_B_WINC_BD_H_FILTER_P0A_0_BD_H_FILTER_P0AC1_FIELD _MK_FIELD_CONST(0x1f, DC_B_WINC_BD_H_FILTER_P0A_0_BD_H_FILTER_P0AC1_SHIFT) +#define DC_B_WINC_BD_H_FILTER_P0A_0_BD_H_FILTER_P0AC1_RANGE 7:3 +#define DC_B_WINC_BD_H_FILTER_P0A_0_BD_H_FILTER_P0AC1_WOFFSET 0x0 +#define DC_B_WINC_BD_H_FILTER_P0A_0_BD_H_FILTER_P0AC1_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P0A_0_BD_H_FILTER_P0AC1_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P0A_0_BD_H_FILTER_P0AC1_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P0A_0_BD_H_FILTER_P0AC1_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_H_FILTER_P0A_0_BD_H_FILTER_P0AC2_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_H_FILTER_P0A_0_BD_H_FILTER_P0AC2_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_H_FILTER_P0A_0_BD_H_FILTER_P0AC2_SHIFT) +#define DC_B_WINC_BD_H_FILTER_P0A_0_BD_H_FILTER_P0AC2_RANGE 15:8 +#define DC_B_WINC_BD_H_FILTER_P0A_0_BD_H_FILTER_P0AC2_WOFFSET 0x0 +#define DC_B_WINC_BD_H_FILTER_P0A_0_BD_H_FILTER_P0AC2_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P0A_0_BD_H_FILTER_P0AC2_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P0A_0_BD_H_FILTER_P0AC2_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P0A_0_BD_H_FILTER_P0AC2_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_H_FILTER_P0A_0_BD_H_FILTER_P0AC3_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_H_FILTER_P0A_0_BD_H_FILTER_P0AC3_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_H_FILTER_P0A_0_BD_H_FILTER_P0AC3_SHIFT) +#define DC_B_WINC_BD_H_FILTER_P0A_0_BD_H_FILTER_P0AC3_RANGE 23:16 +#define DC_B_WINC_BD_H_FILTER_P0A_0_BD_H_FILTER_P0AC3_WOFFSET 0x0 +#define DC_B_WINC_BD_H_FILTER_P0A_0_BD_H_FILTER_P0AC3_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P0A_0_BD_H_FILTER_P0AC3_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P0A_0_BD_H_FILTER_P0AC3_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P0A_0_BD_H_FILTER_P0AC3_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_H_FILTER_P0A_0_BD_H_FILTER_P0AC4_SHIFT _MK_SHIFT_CONST(24) +#define DC_B_WINC_BD_H_FILTER_P0A_0_BD_H_FILTER_P0AC4_FIELD _MK_FIELD_CONST(0x1f, DC_B_WINC_BD_H_FILTER_P0A_0_BD_H_FILTER_P0AC4_SHIFT) +#define DC_B_WINC_BD_H_FILTER_P0A_0_BD_H_FILTER_P0AC4_RANGE 28:24 +#define DC_B_WINC_BD_H_FILTER_P0A_0_BD_H_FILTER_P0AC4_WOFFSET 0x0 +#define DC_B_WINC_BD_H_FILTER_P0A_0_BD_H_FILTER_P0AC4_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P0A_0_BD_H_FILTER_P0AC4_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P0A_0_BD_H_FILTER_P0AC4_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P0A_0_BD_H_FILTER_P0AC4_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_H_FILTER_P0A_0_BD_H_FILTER_P0AC5_SHIFT _MK_SHIFT_CONST(29) +#define DC_B_WINC_BD_H_FILTER_P0A_0_BD_H_FILTER_P0AC5_FIELD _MK_FIELD_CONST(0x7, DC_B_WINC_BD_H_FILTER_P0A_0_BD_H_FILTER_P0AC5_SHIFT) +#define DC_B_WINC_BD_H_FILTER_P0A_0_BD_H_FILTER_P0AC5_RANGE 31:29 +#define DC_B_WINC_BD_H_FILTER_P0A_0_BD_H_FILTER_P0AC5_WOFFSET 0x0 +#define DC_B_WINC_BD_H_FILTER_P0A_0_BD_H_FILTER_P0AC5_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P0A_0_BD_H_FILTER_P0AC5_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P0A_0_BD_H_FILTER_P0AC5_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P0A_0_BD_H_FILTER_P0AC5_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_B_WINC_BD_H_FILTER_P0B_0 +#define DC_B_WINC_BD_H_FILTER_P0B_0 _MK_ADDR_CONST(0xd0c) +#define DC_B_WINC_BD_H_FILTER_P0B_0_SECURE 0x0 +#define DC_B_WINC_BD_H_FILTER_P0B_0_WORD_COUNT 0x1 +#define DC_B_WINC_BD_H_FILTER_P0B_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P0B_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P0B_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P0B_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P0B_0_READ_MASK _MK_MASK_CONST(0xffffffff) +#define DC_B_WINC_BD_H_FILTER_P0B_0_WRITE_MASK _MK_MASK_CONST(0xffffffff) +#define DC_B_WINC_BD_H_FILTER_P0B_0_BD_H_FILTER_P0BC0_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_H_FILTER_P0B_0_BD_H_FILTER_P0BC0_FIELD _MK_FIELD_CONST(0x7, DC_B_WINC_BD_H_FILTER_P0B_0_BD_H_FILTER_P0BC0_SHIFT) +#define DC_B_WINC_BD_H_FILTER_P0B_0_BD_H_FILTER_P0BC0_RANGE 2:0 +#define DC_B_WINC_BD_H_FILTER_P0B_0_BD_H_FILTER_P0BC0_WOFFSET 0x0 +#define DC_B_WINC_BD_H_FILTER_P0B_0_BD_H_FILTER_P0BC0_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P0B_0_BD_H_FILTER_P0BC0_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P0B_0_BD_H_FILTER_P0BC0_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P0B_0_BD_H_FILTER_P0BC0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_H_FILTER_P0B_0_BD_H_FILTER_P0BC1_SHIFT _MK_SHIFT_CONST(3) +#define DC_B_WINC_BD_H_FILTER_P0B_0_BD_H_FILTER_P0BC1_FIELD _MK_FIELD_CONST(0x1f, DC_B_WINC_BD_H_FILTER_P0B_0_BD_H_FILTER_P0BC1_SHIFT) +#define DC_B_WINC_BD_H_FILTER_P0B_0_BD_H_FILTER_P0BC1_RANGE 7:3 +#define DC_B_WINC_BD_H_FILTER_P0B_0_BD_H_FILTER_P0BC1_WOFFSET 0x0 +#define DC_B_WINC_BD_H_FILTER_P0B_0_BD_H_FILTER_P0BC1_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P0B_0_BD_H_FILTER_P0BC1_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P0B_0_BD_H_FILTER_P0BC1_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P0B_0_BD_H_FILTER_P0BC1_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_H_FILTER_P0B_0_BD_H_FILTER_P0BC2_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_H_FILTER_P0B_0_BD_H_FILTER_P0BC2_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_H_FILTER_P0B_0_BD_H_FILTER_P0BC2_SHIFT) +#define DC_B_WINC_BD_H_FILTER_P0B_0_BD_H_FILTER_P0BC2_RANGE 15:8 +#define DC_B_WINC_BD_H_FILTER_P0B_0_BD_H_FILTER_P0BC2_WOFFSET 0x0 +#define DC_B_WINC_BD_H_FILTER_P0B_0_BD_H_FILTER_P0BC2_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P0B_0_BD_H_FILTER_P0BC2_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P0B_0_BD_H_FILTER_P0BC2_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P0B_0_BD_H_FILTER_P0BC2_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_H_FILTER_P0B_0_BD_H_FILTER_P0BC3_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_H_FILTER_P0B_0_BD_H_FILTER_P0BC3_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_H_FILTER_P0B_0_BD_H_FILTER_P0BC3_SHIFT) +#define DC_B_WINC_BD_H_FILTER_P0B_0_BD_H_FILTER_P0BC3_RANGE 23:16 +#define DC_B_WINC_BD_H_FILTER_P0B_0_BD_H_FILTER_P0BC3_WOFFSET 0x0 +#define DC_B_WINC_BD_H_FILTER_P0B_0_BD_H_FILTER_P0BC3_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P0B_0_BD_H_FILTER_P0BC3_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P0B_0_BD_H_FILTER_P0BC3_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P0B_0_BD_H_FILTER_P0BC3_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_H_FILTER_P0B_0_BD_H_FILTER_P0BC4_SHIFT _MK_SHIFT_CONST(24) +#define DC_B_WINC_BD_H_FILTER_P0B_0_BD_H_FILTER_P0BC4_FIELD _MK_FIELD_CONST(0x1f, DC_B_WINC_BD_H_FILTER_P0B_0_BD_H_FILTER_P0BC4_SHIFT) +#define DC_B_WINC_BD_H_FILTER_P0B_0_BD_H_FILTER_P0BC4_RANGE 28:24 +#define DC_B_WINC_BD_H_FILTER_P0B_0_BD_H_FILTER_P0BC4_WOFFSET 0x0 +#define DC_B_WINC_BD_H_FILTER_P0B_0_BD_H_FILTER_P0BC4_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P0B_0_BD_H_FILTER_P0BC4_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P0B_0_BD_H_FILTER_P0BC4_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P0B_0_BD_H_FILTER_P0BC4_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_H_FILTER_P0B_0_BD_H_FILTER_P0BC5_SHIFT _MK_SHIFT_CONST(29) +#define DC_B_WINC_BD_H_FILTER_P0B_0_BD_H_FILTER_P0BC5_FIELD _MK_FIELD_CONST(0x7, DC_B_WINC_BD_H_FILTER_P0B_0_BD_H_FILTER_P0BC5_SHIFT) +#define DC_B_WINC_BD_H_FILTER_P0B_0_BD_H_FILTER_P0BC5_RANGE 31:29 +#define DC_B_WINC_BD_H_FILTER_P0B_0_BD_H_FILTER_P0BC5_WOFFSET 0x0 +#define DC_B_WINC_BD_H_FILTER_P0B_0_BD_H_FILTER_P0BC5_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P0B_0_BD_H_FILTER_P0BC5_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P0B_0_BD_H_FILTER_P0BC5_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P0B_0_BD_H_FILTER_P0BC5_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_B_WINC_BD_H_FILTER_P0C_0 +#define DC_B_WINC_BD_H_FILTER_P0C_0 _MK_ADDR_CONST(0xd0d) +#define DC_B_WINC_BD_H_FILTER_P0C_0_SECURE 0x0 +#define DC_B_WINC_BD_H_FILTER_P0C_0_WORD_COUNT 0x1 +#define DC_B_WINC_BD_H_FILTER_P0C_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P0C_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P0C_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P0C_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P0C_0_READ_MASK _MK_MASK_CONST(0xffffffff) +#define DC_B_WINC_BD_H_FILTER_P0C_0_WRITE_MASK _MK_MASK_CONST(0xffffffff) +#define DC_B_WINC_BD_H_FILTER_P0C_0_BD_H_FILTER_P0CC0_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_H_FILTER_P0C_0_BD_H_FILTER_P0CC0_FIELD _MK_FIELD_CONST(0x7, DC_B_WINC_BD_H_FILTER_P0C_0_BD_H_FILTER_P0CC0_SHIFT) +#define DC_B_WINC_BD_H_FILTER_P0C_0_BD_H_FILTER_P0CC0_RANGE 2:0 +#define DC_B_WINC_BD_H_FILTER_P0C_0_BD_H_FILTER_P0CC0_WOFFSET 0x0 +#define DC_B_WINC_BD_H_FILTER_P0C_0_BD_H_FILTER_P0CC0_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P0C_0_BD_H_FILTER_P0CC0_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P0C_0_BD_H_FILTER_P0CC0_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P0C_0_BD_H_FILTER_P0CC0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_H_FILTER_P0C_0_BD_H_FILTER_P0CC1_SHIFT _MK_SHIFT_CONST(3) +#define DC_B_WINC_BD_H_FILTER_P0C_0_BD_H_FILTER_P0CC1_FIELD _MK_FIELD_CONST(0x1f, DC_B_WINC_BD_H_FILTER_P0C_0_BD_H_FILTER_P0CC1_SHIFT) +#define DC_B_WINC_BD_H_FILTER_P0C_0_BD_H_FILTER_P0CC1_RANGE 7:3 +#define DC_B_WINC_BD_H_FILTER_P0C_0_BD_H_FILTER_P0CC1_WOFFSET 0x0 +#define DC_B_WINC_BD_H_FILTER_P0C_0_BD_H_FILTER_P0CC1_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P0C_0_BD_H_FILTER_P0CC1_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P0C_0_BD_H_FILTER_P0CC1_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P0C_0_BD_H_FILTER_P0CC1_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_H_FILTER_P0C_0_BD_H_FILTER_P0CC2_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_H_FILTER_P0C_0_BD_H_FILTER_P0CC2_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_H_FILTER_P0C_0_BD_H_FILTER_P0CC2_SHIFT) +#define DC_B_WINC_BD_H_FILTER_P0C_0_BD_H_FILTER_P0CC2_RANGE 15:8 +#define DC_B_WINC_BD_H_FILTER_P0C_0_BD_H_FILTER_P0CC2_WOFFSET 0x0 +#define DC_B_WINC_BD_H_FILTER_P0C_0_BD_H_FILTER_P0CC2_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P0C_0_BD_H_FILTER_P0CC2_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P0C_0_BD_H_FILTER_P0CC2_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P0C_0_BD_H_FILTER_P0CC2_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_H_FILTER_P0C_0_BD_H_FILTER_P0CC3_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_H_FILTER_P0C_0_BD_H_FILTER_P0CC3_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_H_FILTER_P0C_0_BD_H_FILTER_P0CC3_SHIFT) +#define DC_B_WINC_BD_H_FILTER_P0C_0_BD_H_FILTER_P0CC3_RANGE 23:16 +#define DC_B_WINC_BD_H_FILTER_P0C_0_BD_H_FILTER_P0CC3_WOFFSET 0x0 +#define DC_B_WINC_BD_H_FILTER_P0C_0_BD_H_FILTER_P0CC3_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P0C_0_BD_H_FILTER_P0CC3_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P0C_0_BD_H_FILTER_P0CC3_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P0C_0_BD_H_FILTER_P0CC3_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_H_FILTER_P0C_0_BD_H_FILTER_P0CC4_SHIFT _MK_SHIFT_CONST(24) +#define DC_B_WINC_BD_H_FILTER_P0C_0_BD_H_FILTER_P0CC4_FIELD _MK_FIELD_CONST(0x1f, DC_B_WINC_BD_H_FILTER_P0C_0_BD_H_FILTER_P0CC4_SHIFT) +#define DC_B_WINC_BD_H_FILTER_P0C_0_BD_H_FILTER_P0CC4_RANGE 28:24 +#define DC_B_WINC_BD_H_FILTER_P0C_0_BD_H_FILTER_P0CC4_WOFFSET 0x0 +#define DC_B_WINC_BD_H_FILTER_P0C_0_BD_H_FILTER_P0CC4_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P0C_0_BD_H_FILTER_P0CC4_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P0C_0_BD_H_FILTER_P0CC4_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P0C_0_BD_H_FILTER_P0CC4_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_H_FILTER_P0C_0_BD_H_FILTER_P0CC5_SHIFT _MK_SHIFT_CONST(29) +#define DC_B_WINC_BD_H_FILTER_P0C_0_BD_H_FILTER_P0CC5_FIELD _MK_FIELD_CONST(0x7, DC_B_WINC_BD_H_FILTER_P0C_0_BD_H_FILTER_P0CC5_SHIFT) +#define DC_B_WINC_BD_H_FILTER_P0C_0_BD_H_FILTER_P0CC5_RANGE 31:29 +#define DC_B_WINC_BD_H_FILTER_P0C_0_BD_H_FILTER_P0CC5_WOFFSET 0x0 +#define DC_B_WINC_BD_H_FILTER_P0C_0_BD_H_FILTER_P0CC5_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P0C_0_BD_H_FILTER_P0CC5_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P0C_0_BD_H_FILTER_P0CC5_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P0C_0_BD_H_FILTER_P0CC5_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_B_WINC_BD_H_FILTER_P0D_0 +#define DC_B_WINC_BD_H_FILTER_P0D_0 _MK_ADDR_CONST(0xd0e) +#define DC_B_WINC_BD_H_FILTER_P0D_0_SECURE 0x0 +#define DC_B_WINC_BD_H_FILTER_P0D_0_WORD_COUNT 0x1 +#define DC_B_WINC_BD_H_FILTER_P0D_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P0D_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P0D_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P0D_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P0D_0_READ_MASK _MK_MASK_CONST(0xffffffff) +#define DC_B_WINC_BD_H_FILTER_P0D_0_WRITE_MASK _MK_MASK_CONST(0xffffffff) +#define DC_B_WINC_BD_H_FILTER_P0D_0_BD_H_FILTER_P0DC0_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_H_FILTER_P0D_0_BD_H_FILTER_P0DC0_FIELD _MK_FIELD_CONST(0x7, DC_B_WINC_BD_H_FILTER_P0D_0_BD_H_FILTER_P0DC0_SHIFT) +#define DC_B_WINC_BD_H_FILTER_P0D_0_BD_H_FILTER_P0DC0_RANGE 2:0 +#define DC_B_WINC_BD_H_FILTER_P0D_0_BD_H_FILTER_P0DC0_WOFFSET 0x0 +#define DC_B_WINC_BD_H_FILTER_P0D_0_BD_H_FILTER_P0DC0_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P0D_0_BD_H_FILTER_P0DC0_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P0D_0_BD_H_FILTER_P0DC0_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P0D_0_BD_H_FILTER_P0DC0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_H_FILTER_P0D_0_BD_H_FILTER_P0DC1_SHIFT _MK_SHIFT_CONST(3) +#define DC_B_WINC_BD_H_FILTER_P0D_0_BD_H_FILTER_P0DC1_FIELD _MK_FIELD_CONST(0x1f, DC_B_WINC_BD_H_FILTER_P0D_0_BD_H_FILTER_P0DC1_SHIFT) +#define DC_B_WINC_BD_H_FILTER_P0D_0_BD_H_FILTER_P0DC1_RANGE 7:3 +#define DC_B_WINC_BD_H_FILTER_P0D_0_BD_H_FILTER_P0DC1_WOFFSET 0x0 +#define DC_B_WINC_BD_H_FILTER_P0D_0_BD_H_FILTER_P0DC1_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P0D_0_BD_H_FILTER_P0DC1_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P0D_0_BD_H_FILTER_P0DC1_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P0D_0_BD_H_FILTER_P0DC1_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_H_FILTER_P0D_0_BD_H_FILTER_P0DC2_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_H_FILTER_P0D_0_BD_H_FILTER_P0DC2_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_H_FILTER_P0D_0_BD_H_FILTER_P0DC2_SHIFT) +#define DC_B_WINC_BD_H_FILTER_P0D_0_BD_H_FILTER_P0DC2_RANGE 15:8 +#define DC_B_WINC_BD_H_FILTER_P0D_0_BD_H_FILTER_P0DC2_WOFFSET 0x0 +#define DC_B_WINC_BD_H_FILTER_P0D_0_BD_H_FILTER_P0DC2_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P0D_0_BD_H_FILTER_P0DC2_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P0D_0_BD_H_FILTER_P0DC2_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P0D_0_BD_H_FILTER_P0DC2_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_H_FILTER_P0D_0_BD_H_FILTER_P0DC3_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_H_FILTER_P0D_0_BD_H_FILTER_P0DC3_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_H_FILTER_P0D_0_BD_H_FILTER_P0DC3_SHIFT) +#define DC_B_WINC_BD_H_FILTER_P0D_0_BD_H_FILTER_P0DC3_RANGE 23:16 +#define DC_B_WINC_BD_H_FILTER_P0D_0_BD_H_FILTER_P0DC3_WOFFSET 0x0 +#define DC_B_WINC_BD_H_FILTER_P0D_0_BD_H_FILTER_P0DC3_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P0D_0_BD_H_FILTER_P0DC3_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P0D_0_BD_H_FILTER_P0DC3_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P0D_0_BD_H_FILTER_P0DC3_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_H_FILTER_P0D_0_BD_H_FILTER_P0DC4_SHIFT _MK_SHIFT_CONST(24) +#define DC_B_WINC_BD_H_FILTER_P0D_0_BD_H_FILTER_P0DC4_FIELD _MK_FIELD_CONST(0x1f, DC_B_WINC_BD_H_FILTER_P0D_0_BD_H_FILTER_P0DC4_SHIFT) +#define DC_B_WINC_BD_H_FILTER_P0D_0_BD_H_FILTER_P0DC4_RANGE 28:24 +#define DC_B_WINC_BD_H_FILTER_P0D_0_BD_H_FILTER_P0DC4_WOFFSET 0x0 +#define DC_B_WINC_BD_H_FILTER_P0D_0_BD_H_FILTER_P0DC4_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P0D_0_BD_H_FILTER_P0DC4_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P0D_0_BD_H_FILTER_P0DC4_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P0D_0_BD_H_FILTER_P0DC4_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_H_FILTER_P0D_0_BD_H_FILTER_P0DC5_SHIFT _MK_SHIFT_CONST(29) +#define DC_B_WINC_BD_H_FILTER_P0D_0_BD_H_FILTER_P0DC5_FIELD _MK_FIELD_CONST(0x7, DC_B_WINC_BD_H_FILTER_P0D_0_BD_H_FILTER_P0DC5_SHIFT) +#define DC_B_WINC_BD_H_FILTER_P0D_0_BD_H_FILTER_P0DC5_RANGE 31:29 +#define DC_B_WINC_BD_H_FILTER_P0D_0_BD_H_FILTER_P0DC5_WOFFSET 0x0 +#define DC_B_WINC_BD_H_FILTER_P0D_0_BD_H_FILTER_P0DC5_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P0D_0_BD_H_FILTER_P0DC5_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P0D_0_BD_H_FILTER_P0DC5_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P0D_0_BD_H_FILTER_P0DC5_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_B_WINC_BD_H_FILTER_P0E_0 +#define DC_B_WINC_BD_H_FILTER_P0E_0 _MK_ADDR_CONST(0xd0f) +#define DC_B_WINC_BD_H_FILTER_P0E_0_SECURE 0x0 +#define DC_B_WINC_BD_H_FILTER_P0E_0_WORD_COUNT 0x1 +#define DC_B_WINC_BD_H_FILTER_P0E_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P0E_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P0E_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P0E_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P0E_0_READ_MASK _MK_MASK_CONST(0xffffffff) +#define DC_B_WINC_BD_H_FILTER_P0E_0_WRITE_MASK _MK_MASK_CONST(0xffffffff) +#define DC_B_WINC_BD_H_FILTER_P0E_0_BD_H_FILTER_P0EC0_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_H_FILTER_P0E_0_BD_H_FILTER_P0EC0_FIELD _MK_FIELD_CONST(0x7, DC_B_WINC_BD_H_FILTER_P0E_0_BD_H_FILTER_P0EC0_SHIFT) +#define DC_B_WINC_BD_H_FILTER_P0E_0_BD_H_FILTER_P0EC0_RANGE 2:0 +#define DC_B_WINC_BD_H_FILTER_P0E_0_BD_H_FILTER_P0EC0_WOFFSET 0x0 +#define DC_B_WINC_BD_H_FILTER_P0E_0_BD_H_FILTER_P0EC0_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P0E_0_BD_H_FILTER_P0EC0_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P0E_0_BD_H_FILTER_P0EC0_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P0E_0_BD_H_FILTER_P0EC0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_H_FILTER_P0E_0_BD_H_FILTER_P0EC1_SHIFT _MK_SHIFT_CONST(3) +#define DC_B_WINC_BD_H_FILTER_P0E_0_BD_H_FILTER_P0EC1_FIELD _MK_FIELD_CONST(0x1f, DC_B_WINC_BD_H_FILTER_P0E_0_BD_H_FILTER_P0EC1_SHIFT) +#define DC_B_WINC_BD_H_FILTER_P0E_0_BD_H_FILTER_P0EC1_RANGE 7:3 +#define DC_B_WINC_BD_H_FILTER_P0E_0_BD_H_FILTER_P0EC1_WOFFSET 0x0 +#define DC_B_WINC_BD_H_FILTER_P0E_0_BD_H_FILTER_P0EC1_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P0E_0_BD_H_FILTER_P0EC1_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P0E_0_BD_H_FILTER_P0EC1_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P0E_0_BD_H_FILTER_P0EC1_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_H_FILTER_P0E_0_BD_H_FILTER_P0EC2_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_H_FILTER_P0E_0_BD_H_FILTER_P0EC2_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_H_FILTER_P0E_0_BD_H_FILTER_P0EC2_SHIFT) +#define DC_B_WINC_BD_H_FILTER_P0E_0_BD_H_FILTER_P0EC2_RANGE 15:8 +#define DC_B_WINC_BD_H_FILTER_P0E_0_BD_H_FILTER_P0EC2_WOFFSET 0x0 +#define DC_B_WINC_BD_H_FILTER_P0E_0_BD_H_FILTER_P0EC2_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P0E_0_BD_H_FILTER_P0EC2_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P0E_0_BD_H_FILTER_P0EC2_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P0E_0_BD_H_FILTER_P0EC2_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_H_FILTER_P0E_0_BD_H_FILTER_P0EC3_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_H_FILTER_P0E_0_BD_H_FILTER_P0EC3_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_H_FILTER_P0E_0_BD_H_FILTER_P0EC3_SHIFT) +#define DC_B_WINC_BD_H_FILTER_P0E_0_BD_H_FILTER_P0EC3_RANGE 23:16 +#define DC_B_WINC_BD_H_FILTER_P0E_0_BD_H_FILTER_P0EC3_WOFFSET 0x0 +#define DC_B_WINC_BD_H_FILTER_P0E_0_BD_H_FILTER_P0EC3_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P0E_0_BD_H_FILTER_P0EC3_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P0E_0_BD_H_FILTER_P0EC3_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P0E_0_BD_H_FILTER_P0EC3_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_H_FILTER_P0E_0_BD_H_FILTER_P0EC4_SHIFT _MK_SHIFT_CONST(24) +#define DC_B_WINC_BD_H_FILTER_P0E_0_BD_H_FILTER_P0EC4_FIELD _MK_FIELD_CONST(0x1f, DC_B_WINC_BD_H_FILTER_P0E_0_BD_H_FILTER_P0EC4_SHIFT) +#define DC_B_WINC_BD_H_FILTER_P0E_0_BD_H_FILTER_P0EC4_RANGE 28:24 +#define DC_B_WINC_BD_H_FILTER_P0E_0_BD_H_FILTER_P0EC4_WOFFSET 0x0 +#define DC_B_WINC_BD_H_FILTER_P0E_0_BD_H_FILTER_P0EC4_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P0E_0_BD_H_FILTER_P0EC4_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P0E_0_BD_H_FILTER_P0EC4_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P0E_0_BD_H_FILTER_P0EC4_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_H_FILTER_P0E_0_BD_H_FILTER_P0EC5_SHIFT _MK_SHIFT_CONST(29) +#define DC_B_WINC_BD_H_FILTER_P0E_0_BD_H_FILTER_P0EC5_FIELD _MK_FIELD_CONST(0x7, DC_B_WINC_BD_H_FILTER_P0E_0_BD_H_FILTER_P0EC5_SHIFT) +#define DC_B_WINC_BD_H_FILTER_P0E_0_BD_H_FILTER_P0EC5_RANGE 31:29 +#define DC_B_WINC_BD_H_FILTER_P0E_0_BD_H_FILTER_P0EC5_WOFFSET 0x0 +#define DC_B_WINC_BD_H_FILTER_P0E_0_BD_H_FILTER_P0EC5_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P0E_0_BD_H_FILTER_P0EC5_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P0E_0_BD_H_FILTER_P0EC5_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P0E_0_BD_H_FILTER_P0EC5_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_B_WINC_BD_H_FILTER_P0F_0 +#define DC_B_WINC_BD_H_FILTER_P0F_0 _MK_ADDR_CONST(0xd10) +#define DC_B_WINC_BD_H_FILTER_P0F_0_SECURE 0x0 +#define DC_B_WINC_BD_H_FILTER_P0F_0_WORD_COUNT 0x1 +#define DC_B_WINC_BD_H_FILTER_P0F_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P0F_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P0F_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P0F_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P0F_0_READ_MASK _MK_MASK_CONST(0xffffffff) +#define DC_B_WINC_BD_H_FILTER_P0F_0_WRITE_MASK _MK_MASK_CONST(0xffffffff) +#define DC_B_WINC_BD_H_FILTER_P0F_0_BD_H_FILTER_P0FC0_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_H_FILTER_P0F_0_BD_H_FILTER_P0FC0_FIELD _MK_FIELD_CONST(0x7, DC_B_WINC_BD_H_FILTER_P0F_0_BD_H_FILTER_P0FC0_SHIFT) +#define DC_B_WINC_BD_H_FILTER_P0F_0_BD_H_FILTER_P0FC0_RANGE 2:0 +#define DC_B_WINC_BD_H_FILTER_P0F_0_BD_H_FILTER_P0FC0_WOFFSET 0x0 +#define DC_B_WINC_BD_H_FILTER_P0F_0_BD_H_FILTER_P0FC0_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P0F_0_BD_H_FILTER_P0FC0_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P0F_0_BD_H_FILTER_P0FC0_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P0F_0_BD_H_FILTER_P0FC0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_H_FILTER_P0F_0_BD_H_FILTER_P0FC1_SHIFT _MK_SHIFT_CONST(3) +#define DC_B_WINC_BD_H_FILTER_P0F_0_BD_H_FILTER_P0FC1_FIELD _MK_FIELD_CONST(0x1f, DC_B_WINC_BD_H_FILTER_P0F_0_BD_H_FILTER_P0FC1_SHIFT) +#define DC_B_WINC_BD_H_FILTER_P0F_0_BD_H_FILTER_P0FC1_RANGE 7:3 +#define DC_B_WINC_BD_H_FILTER_P0F_0_BD_H_FILTER_P0FC1_WOFFSET 0x0 +#define DC_B_WINC_BD_H_FILTER_P0F_0_BD_H_FILTER_P0FC1_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P0F_0_BD_H_FILTER_P0FC1_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P0F_0_BD_H_FILTER_P0FC1_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P0F_0_BD_H_FILTER_P0FC1_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_H_FILTER_P0F_0_BD_H_FILTER_P0FC2_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_H_FILTER_P0F_0_BD_H_FILTER_P0FC2_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_H_FILTER_P0F_0_BD_H_FILTER_P0FC2_SHIFT) +#define DC_B_WINC_BD_H_FILTER_P0F_0_BD_H_FILTER_P0FC2_RANGE 15:8 +#define DC_B_WINC_BD_H_FILTER_P0F_0_BD_H_FILTER_P0FC2_WOFFSET 0x0 +#define DC_B_WINC_BD_H_FILTER_P0F_0_BD_H_FILTER_P0FC2_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P0F_0_BD_H_FILTER_P0FC2_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P0F_0_BD_H_FILTER_P0FC2_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P0F_0_BD_H_FILTER_P0FC2_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_H_FILTER_P0F_0_BD_H_FILTER_P0FC3_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINC_BD_H_FILTER_P0F_0_BD_H_FILTER_P0FC3_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_H_FILTER_P0F_0_BD_H_FILTER_P0FC3_SHIFT) +#define DC_B_WINC_BD_H_FILTER_P0F_0_BD_H_FILTER_P0FC3_RANGE 23:16 +#define DC_B_WINC_BD_H_FILTER_P0F_0_BD_H_FILTER_P0FC3_WOFFSET 0x0 +#define DC_B_WINC_BD_H_FILTER_P0F_0_BD_H_FILTER_P0FC3_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P0F_0_BD_H_FILTER_P0FC3_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P0F_0_BD_H_FILTER_P0FC3_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P0F_0_BD_H_FILTER_P0FC3_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_H_FILTER_P0F_0_BD_H_FILTER_P0FC4_SHIFT _MK_SHIFT_CONST(24) +#define DC_B_WINC_BD_H_FILTER_P0F_0_BD_H_FILTER_P0FC4_FIELD _MK_FIELD_CONST(0x1f, DC_B_WINC_BD_H_FILTER_P0F_0_BD_H_FILTER_P0FC4_SHIFT) +#define DC_B_WINC_BD_H_FILTER_P0F_0_BD_H_FILTER_P0FC4_RANGE 28:24 +#define DC_B_WINC_BD_H_FILTER_P0F_0_BD_H_FILTER_P0FC4_WOFFSET 0x0 +#define DC_B_WINC_BD_H_FILTER_P0F_0_BD_H_FILTER_P0FC4_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P0F_0_BD_H_FILTER_P0FC4_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P0F_0_BD_H_FILTER_P0FC4_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P0F_0_BD_H_FILTER_P0FC4_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_H_FILTER_P0F_0_BD_H_FILTER_P0FC5_SHIFT _MK_SHIFT_CONST(29) +#define DC_B_WINC_BD_H_FILTER_P0F_0_BD_H_FILTER_P0FC5_FIELD _MK_FIELD_CONST(0x7, DC_B_WINC_BD_H_FILTER_P0F_0_BD_H_FILTER_P0FC5_SHIFT) +#define DC_B_WINC_BD_H_FILTER_P0F_0_BD_H_FILTER_P0FC5_RANGE 31:29 +#define DC_B_WINC_BD_H_FILTER_P0F_0_BD_H_FILTER_P0FC5_WOFFSET 0x0 +#define DC_B_WINC_BD_H_FILTER_P0F_0_BD_H_FILTER_P0FC5_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P0F_0_BD_H_FILTER_P0FC5_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P0F_0_BD_H_FILTER_P0FC5_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_P0F_0_BD_H_FILTER_P0FC5_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_B_WINC_BD_CSC_YOF_0 +#define DC_B_WINC_BD_CSC_YOF_0 _MK_ADDR_CONST(0xd11) +#define DC_B_WINC_BD_CSC_YOF_0_SECURE 0x0 +#define DC_B_WINC_BD_CSC_YOF_0_WORD_COUNT 0x1 +#define DC_B_WINC_BD_CSC_YOF_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_CSC_YOF_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_CSC_YOF_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_CSC_YOF_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_CSC_YOF_0_READ_MASK _MK_MASK_CONST(0xff) +#define DC_B_WINC_BD_CSC_YOF_0_WRITE_MASK _MK_MASK_CONST(0xff) +#define DC_B_WINC_BD_CSC_YOF_0_BD_CSC_YOF_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_CSC_YOF_0_BD_CSC_YOF_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_CSC_YOF_0_BD_CSC_YOF_SHIFT) +#define DC_B_WINC_BD_CSC_YOF_0_BD_CSC_YOF_RANGE 7:0 +#define DC_B_WINC_BD_CSC_YOF_0_BD_CSC_YOF_WOFFSET 0x0 +#define DC_B_WINC_BD_CSC_YOF_0_BD_CSC_YOF_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_CSC_YOF_0_BD_CSC_YOF_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_CSC_YOF_0_BD_CSC_YOF_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_CSC_YOF_0_BD_CSC_YOF_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_B_WINC_BD_CSC_KYRGB_0 +#define DC_B_WINC_BD_CSC_KYRGB_0 _MK_ADDR_CONST(0xd12) +#define DC_B_WINC_BD_CSC_KYRGB_0_SECURE 0x0 +#define DC_B_WINC_BD_CSC_KYRGB_0_WORD_COUNT 0x1 +#define DC_B_WINC_BD_CSC_KYRGB_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_CSC_KYRGB_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_CSC_KYRGB_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_CSC_KYRGB_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_CSC_KYRGB_0_READ_MASK _MK_MASK_CONST(0x3ff) +#define DC_B_WINC_BD_CSC_KYRGB_0_WRITE_MASK _MK_MASK_CONST(0x3ff) +#define DC_B_WINC_BD_CSC_KYRGB_0_BD_CSC_KYRGB_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_CSC_KYRGB_0_BD_CSC_KYRGB_FIELD _MK_FIELD_CONST(0x3ff, DC_B_WINC_BD_CSC_KYRGB_0_BD_CSC_KYRGB_SHIFT) +#define DC_B_WINC_BD_CSC_KYRGB_0_BD_CSC_KYRGB_RANGE 9:0 +#define DC_B_WINC_BD_CSC_KYRGB_0_BD_CSC_KYRGB_WOFFSET 0x0 +#define DC_B_WINC_BD_CSC_KYRGB_0_BD_CSC_KYRGB_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_CSC_KYRGB_0_BD_CSC_KYRGB_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_CSC_KYRGB_0_BD_CSC_KYRGB_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_CSC_KYRGB_0_BD_CSC_KYRGB_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_B_WINC_BD_CSC_KUR_0 +#define DC_B_WINC_BD_CSC_KUR_0 _MK_ADDR_CONST(0xd13) +#define DC_B_WINC_BD_CSC_KUR_0_SECURE 0x0 +#define DC_B_WINC_BD_CSC_KUR_0_WORD_COUNT 0x1 +#define DC_B_WINC_BD_CSC_KUR_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_CSC_KUR_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_CSC_KUR_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_CSC_KUR_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_CSC_KUR_0_READ_MASK _MK_MASK_CONST(0x7ff) +#define DC_B_WINC_BD_CSC_KUR_0_WRITE_MASK _MK_MASK_CONST(0x7ff) +#define DC_B_WINC_BD_CSC_KUR_0_BD_CSC_KUR_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_CSC_KUR_0_BD_CSC_KUR_FIELD _MK_FIELD_CONST(0x7ff, DC_B_WINC_BD_CSC_KUR_0_BD_CSC_KUR_SHIFT) +#define DC_B_WINC_BD_CSC_KUR_0_BD_CSC_KUR_RANGE 10:0 +#define DC_B_WINC_BD_CSC_KUR_0_BD_CSC_KUR_WOFFSET 0x0 +#define DC_B_WINC_BD_CSC_KUR_0_BD_CSC_KUR_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_CSC_KUR_0_BD_CSC_KUR_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_CSC_KUR_0_BD_CSC_KUR_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_CSC_KUR_0_BD_CSC_KUR_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_B_WINC_BD_CSC_KVR_0 +#define DC_B_WINC_BD_CSC_KVR_0 _MK_ADDR_CONST(0xd14) +#define DC_B_WINC_BD_CSC_KVR_0_SECURE 0x0 +#define DC_B_WINC_BD_CSC_KVR_0_WORD_COUNT 0x1 +#define DC_B_WINC_BD_CSC_KVR_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_CSC_KVR_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_CSC_KVR_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_CSC_KVR_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_CSC_KVR_0_READ_MASK _MK_MASK_CONST(0x7ff) +#define DC_B_WINC_BD_CSC_KVR_0_WRITE_MASK _MK_MASK_CONST(0x7ff) +#define DC_B_WINC_BD_CSC_KVR_0_BD_CSC_KVR_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_CSC_KVR_0_BD_CSC_KVR_FIELD _MK_FIELD_CONST(0x7ff, DC_B_WINC_BD_CSC_KVR_0_BD_CSC_KVR_SHIFT) +#define DC_B_WINC_BD_CSC_KVR_0_BD_CSC_KVR_RANGE 10:0 +#define DC_B_WINC_BD_CSC_KVR_0_BD_CSC_KVR_WOFFSET 0x0 +#define DC_B_WINC_BD_CSC_KVR_0_BD_CSC_KVR_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_CSC_KVR_0_BD_CSC_KVR_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_CSC_KVR_0_BD_CSC_KVR_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_CSC_KVR_0_BD_CSC_KVR_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_B_WINC_BD_CSC_KUG_0 +#define DC_B_WINC_BD_CSC_KUG_0 _MK_ADDR_CONST(0xd15) +#define DC_B_WINC_BD_CSC_KUG_0_SECURE 0x0 +#define DC_B_WINC_BD_CSC_KUG_0_WORD_COUNT 0x1 +#define DC_B_WINC_BD_CSC_KUG_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_CSC_KUG_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_CSC_KUG_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_CSC_KUG_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_CSC_KUG_0_READ_MASK _MK_MASK_CONST(0x3ff) +#define DC_B_WINC_BD_CSC_KUG_0_WRITE_MASK _MK_MASK_CONST(0x3ff) +#define DC_B_WINC_BD_CSC_KUG_0_BD_CSC_KUG_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_CSC_KUG_0_BD_CSC_KUG_FIELD _MK_FIELD_CONST(0x3ff, DC_B_WINC_BD_CSC_KUG_0_BD_CSC_KUG_SHIFT) +#define DC_B_WINC_BD_CSC_KUG_0_BD_CSC_KUG_RANGE 9:0 +#define DC_B_WINC_BD_CSC_KUG_0_BD_CSC_KUG_WOFFSET 0x0 +#define DC_B_WINC_BD_CSC_KUG_0_BD_CSC_KUG_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_CSC_KUG_0_BD_CSC_KUG_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_CSC_KUG_0_BD_CSC_KUG_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_CSC_KUG_0_BD_CSC_KUG_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_B_WINC_BD_CSC_KVG_0 +#define DC_B_WINC_BD_CSC_KVG_0 _MK_ADDR_CONST(0xd16) +#define DC_B_WINC_BD_CSC_KVG_0_SECURE 0x0 +#define DC_B_WINC_BD_CSC_KVG_0_WORD_COUNT 0x1 +#define DC_B_WINC_BD_CSC_KVG_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_CSC_KVG_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_CSC_KVG_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_CSC_KVG_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_CSC_KVG_0_READ_MASK _MK_MASK_CONST(0x3ff) +#define DC_B_WINC_BD_CSC_KVG_0_WRITE_MASK _MK_MASK_CONST(0x3ff) +#define DC_B_WINC_BD_CSC_KVG_0_BD_CSC_KVG_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_CSC_KVG_0_BD_CSC_KVG_FIELD _MK_FIELD_CONST(0x3ff, DC_B_WINC_BD_CSC_KVG_0_BD_CSC_KVG_SHIFT) +#define DC_B_WINC_BD_CSC_KVG_0_BD_CSC_KVG_RANGE 9:0 +#define DC_B_WINC_BD_CSC_KVG_0_BD_CSC_KVG_WOFFSET 0x0 +#define DC_B_WINC_BD_CSC_KVG_0_BD_CSC_KVG_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_CSC_KVG_0_BD_CSC_KVG_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_CSC_KVG_0_BD_CSC_KVG_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_CSC_KVG_0_BD_CSC_KVG_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_B_WINC_BD_CSC_KUB_0 +#define DC_B_WINC_BD_CSC_KUB_0 _MK_ADDR_CONST(0xd17) +#define DC_B_WINC_BD_CSC_KUB_0_SECURE 0x0 +#define DC_B_WINC_BD_CSC_KUB_0_WORD_COUNT 0x1 +#define DC_B_WINC_BD_CSC_KUB_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_CSC_KUB_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_CSC_KUB_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_CSC_KUB_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_CSC_KUB_0_READ_MASK _MK_MASK_CONST(0x7ff) +#define DC_B_WINC_BD_CSC_KUB_0_WRITE_MASK _MK_MASK_CONST(0x7ff) +#define DC_B_WINC_BD_CSC_KUB_0_BD_CSC_KUB_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_CSC_KUB_0_BD_CSC_KUB_FIELD _MK_FIELD_CONST(0x7ff, DC_B_WINC_BD_CSC_KUB_0_BD_CSC_KUB_SHIFT) +#define DC_B_WINC_BD_CSC_KUB_0_BD_CSC_KUB_RANGE 10:0 +#define DC_B_WINC_BD_CSC_KUB_0_BD_CSC_KUB_WOFFSET 0x0 +#define DC_B_WINC_BD_CSC_KUB_0_BD_CSC_KUB_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_CSC_KUB_0_BD_CSC_KUB_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_CSC_KUB_0_BD_CSC_KUB_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_CSC_KUB_0_BD_CSC_KUB_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_B_WINC_BD_CSC_KVB_0 +#define DC_B_WINC_BD_CSC_KVB_0 _MK_ADDR_CONST(0xd18) +#define DC_B_WINC_BD_CSC_KVB_0_SECURE 0x0 +#define DC_B_WINC_BD_CSC_KVB_0_WORD_COUNT 0x1 +#define DC_B_WINC_BD_CSC_KVB_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_CSC_KVB_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_CSC_KVB_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_CSC_KVB_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_CSC_KVB_0_READ_MASK _MK_MASK_CONST(0x7ff) +#define DC_B_WINC_BD_CSC_KVB_0_WRITE_MASK _MK_MASK_CONST(0x7ff) +#define DC_B_WINC_BD_CSC_KVB_0_BD_CSC_KVB_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_CSC_KVB_0_BD_CSC_KVB_FIELD _MK_FIELD_CONST(0x7ff, DC_B_WINC_BD_CSC_KVB_0_BD_CSC_KVB_SHIFT) +#define DC_B_WINC_BD_CSC_KVB_0_BD_CSC_KVB_RANGE 10:0 +#define DC_B_WINC_BD_CSC_KVB_0_BD_CSC_KVB_WOFFSET 0x0 +#define DC_B_WINC_BD_CSC_KVB_0_BD_CSC_KVB_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_CSC_KVB_0_BD_CSC_KVB_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_CSC_KVB_0_BD_CSC_KVB_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_CSC_KVB_0_BD_CSC_KVB_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_B_WINC_BD_V_FILTER_P00_0 +#define DC_B_WINC_BD_V_FILTER_P00_0 _MK_ADDR_CONST(0xd19) +#define DC_B_WINC_BD_V_FILTER_P00_0_SECURE 0x0 +#define DC_B_WINC_BD_V_FILTER_P00_0_WORD_COUNT 0x1 +#define DC_B_WINC_BD_V_FILTER_P00_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_V_FILTER_P00_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_V_FILTER_P00_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_V_FILTER_P00_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_V_FILTER_P00_0_READ_MASK _MK_MASK_CONST(0xff) +#define DC_B_WINC_BD_V_FILTER_P00_0_WRITE_MASK _MK_MASK_CONST(0xff) +#define DC_B_WINC_BD_V_FILTER_P00_0_BD_V_FILTER_P00C0_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_V_FILTER_P00_0_BD_V_FILTER_P00C0_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_V_FILTER_P00_0_BD_V_FILTER_P00C0_SHIFT) +#define DC_B_WINC_BD_V_FILTER_P00_0_BD_V_FILTER_P00C0_RANGE 7:0 +#define DC_B_WINC_BD_V_FILTER_P00_0_BD_V_FILTER_P00C0_WOFFSET 0x0 +#define DC_B_WINC_BD_V_FILTER_P00_0_BD_V_FILTER_P00C0_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_V_FILTER_P00_0_BD_V_FILTER_P00C0_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_V_FILTER_P00_0_BD_V_FILTER_P00C0_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_V_FILTER_P00_0_BD_V_FILTER_P00C0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_B_WINC_BD_V_FILTER_P01_0 +#define DC_B_WINC_BD_V_FILTER_P01_0 _MK_ADDR_CONST(0xd1a) +#define DC_B_WINC_BD_V_FILTER_P01_0_SECURE 0x0 +#define DC_B_WINC_BD_V_FILTER_P01_0_WORD_COUNT 0x1 +#define DC_B_WINC_BD_V_FILTER_P01_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_V_FILTER_P01_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_V_FILTER_P01_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_V_FILTER_P01_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_V_FILTER_P01_0_READ_MASK _MK_MASK_CONST(0xff) +#define DC_B_WINC_BD_V_FILTER_P01_0_WRITE_MASK _MK_MASK_CONST(0xff) +#define DC_B_WINC_BD_V_FILTER_P01_0_BD_V_FILTER_P01C0_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_V_FILTER_P01_0_BD_V_FILTER_P01C0_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_V_FILTER_P01_0_BD_V_FILTER_P01C0_SHIFT) +#define DC_B_WINC_BD_V_FILTER_P01_0_BD_V_FILTER_P01C0_RANGE 7:0 +#define DC_B_WINC_BD_V_FILTER_P01_0_BD_V_FILTER_P01C0_WOFFSET 0x0 +#define DC_B_WINC_BD_V_FILTER_P01_0_BD_V_FILTER_P01C0_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_V_FILTER_P01_0_BD_V_FILTER_P01C0_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_V_FILTER_P01_0_BD_V_FILTER_P01C0_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_V_FILTER_P01_0_BD_V_FILTER_P01C0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_B_WINC_BD_V_FILTER_P02_0 +#define DC_B_WINC_BD_V_FILTER_P02_0 _MK_ADDR_CONST(0xd1b) +#define DC_B_WINC_BD_V_FILTER_P02_0_SECURE 0x0 +#define DC_B_WINC_BD_V_FILTER_P02_0_WORD_COUNT 0x1 +#define DC_B_WINC_BD_V_FILTER_P02_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_V_FILTER_P02_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_V_FILTER_P02_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_V_FILTER_P02_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_V_FILTER_P02_0_READ_MASK _MK_MASK_CONST(0xff) +#define DC_B_WINC_BD_V_FILTER_P02_0_WRITE_MASK _MK_MASK_CONST(0xff) +#define DC_B_WINC_BD_V_FILTER_P02_0_BD_V_FILTER_P02C0_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_V_FILTER_P02_0_BD_V_FILTER_P02C0_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_V_FILTER_P02_0_BD_V_FILTER_P02C0_SHIFT) +#define DC_B_WINC_BD_V_FILTER_P02_0_BD_V_FILTER_P02C0_RANGE 7:0 +#define DC_B_WINC_BD_V_FILTER_P02_0_BD_V_FILTER_P02C0_WOFFSET 0x0 +#define DC_B_WINC_BD_V_FILTER_P02_0_BD_V_FILTER_P02C0_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_V_FILTER_P02_0_BD_V_FILTER_P02C0_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_V_FILTER_P02_0_BD_V_FILTER_P02C0_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_V_FILTER_P02_0_BD_V_FILTER_P02C0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_B_WINC_BD_V_FILTER_P03_0 +#define DC_B_WINC_BD_V_FILTER_P03_0 _MK_ADDR_CONST(0xd1c) +#define DC_B_WINC_BD_V_FILTER_P03_0_SECURE 0x0 +#define DC_B_WINC_BD_V_FILTER_P03_0_WORD_COUNT 0x1 +#define DC_B_WINC_BD_V_FILTER_P03_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_V_FILTER_P03_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_V_FILTER_P03_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_V_FILTER_P03_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_V_FILTER_P03_0_READ_MASK _MK_MASK_CONST(0xff) +#define DC_B_WINC_BD_V_FILTER_P03_0_WRITE_MASK _MK_MASK_CONST(0xff) +#define DC_B_WINC_BD_V_FILTER_P03_0_BD_V_FILTER_P03C0_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_V_FILTER_P03_0_BD_V_FILTER_P03C0_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_V_FILTER_P03_0_BD_V_FILTER_P03C0_SHIFT) +#define DC_B_WINC_BD_V_FILTER_P03_0_BD_V_FILTER_P03C0_RANGE 7:0 +#define DC_B_WINC_BD_V_FILTER_P03_0_BD_V_FILTER_P03C0_WOFFSET 0x0 +#define DC_B_WINC_BD_V_FILTER_P03_0_BD_V_FILTER_P03C0_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_V_FILTER_P03_0_BD_V_FILTER_P03C0_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_V_FILTER_P03_0_BD_V_FILTER_P03C0_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_V_FILTER_P03_0_BD_V_FILTER_P03C0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_B_WINC_BD_V_FILTER_P04_0 +#define DC_B_WINC_BD_V_FILTER_P04_0 _MK_ADDR_CONST(0xd1d) +#define DC_B_WINC_BD_V_FILTER_P04_0_SECURE 0x0 +#define DC_B_WINC_BD_V_FILTER_P04_0_WORD_COUNT 0x1 +#define DC_B_WINC_BD_V_FILTER_P04_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_V_FILTER_P04_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_V_FILTER_P04_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_V_FILTER_P04_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_V_FILTER_P04_0_READ_MASK _MK_MASK_CONST(0xff) +#define DC_B_WINC_BD_V_FILTER_P04_0_WRITE_MASK _MK_MASK_CONST(0xff) +#define DC_B_WINC_BD_V_FILTER_P04_0_BD_V_FILTER_P04C0_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_V_FILTER_P04_0_BD_V_FILTER_P04C0_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_V_FILTER_P04_0_BD_V_FILTER_P04C0_SHIFT) +#define DC_B_WINC_BD_V_FILTER_P04_0_BD_V_FILTER_P04C0_RANGE 7:0 +#define DC_B_WINC_BD_V_FILTER_P04_0_BD_V_FILTER_P04C0_WOFFSET 0x0 +#define DC_B_WINC_BD_V_FILTER_P04_0_BD_V_FILTER_P04C0_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_V_FILTER_P04_0_BD_V_FILTER_P04C0_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_V_FILTER_P04_0_BD_V_FILTER_P04C0_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_V_FILTER_P04_0_BD_V_FILTER_P04C0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_B_WINC_BD_V_FILTER_P05_0 +#define DC_B_WINC_BD_V_FILTER_P05_0 _MK_ADDR_CONST(0xd1e) +#define DC_B_WINC_BD_V_FILTER_P05_0_SECURE 0x0 +#define DC_B_WINC_BD_V_FILTER_P05_0_WORD_COUNT 0x1 +#define DC_B_WINC_BD_V_FILTER_P05_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_V_FILTER_P05_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_V_FILTER_P05_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_V_FILTER_P05_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_V_FILTER_P05_0_READ_MASK _MK_MASK_CONST(0xff) +#define DC_B_WINC_BD_V_FILTER_P05_0_WRITE_MASK _MK_MASK_CONST(0xff) +#define DC_B_WINC_BD_V_FILTER_P05_0_BD_V_FILTER_P05C0_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_V_FILTER_P05_0_BD_V_FILTER_P05C0_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_V_FILTER_P05_0_BD_V_FILTER_P05C0_SHIFT) +#define DC_B_WINC_BD_V_FILTER_P05_0_BD_V_FILTER_P05C0_RANGE 7:0 +#define DC_B_WINC_BD_V_FILTER_P05_0_BD_V_FILTER_P05C0_WOFFSET 0x0 +#define DC_B_WINC_BD_V_FILTER_P05_0_BD_V_FILTER_P05C0_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_V_FILTER_P05_0_BD_V_FILTER_P05C0_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_V_FILTER_P05_0_BD_V_FILTER_P05C0_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_V_FILTER_P05_0_BD_V_FILTER_P05C0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_B_WINC_BD_V_FILTER_P06_0 +#define DC_B_WINC_BD_V_FILTER_P06_0 _MK_ADDR_CONST(0xd1f) +#define DC_B_WINC_BD_V_FILTER_P06_0_SECURE 0x0 +#define DC_B_WINC_BD_V_FILTER_P06_0_WORD_COUNT 0x1 +#define DC_B_WINC_BD_V_FILTER_P06_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_V_FILTER_P06_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_V_FILTER_P06_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_V_FILTER_P06_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_V_FILTER_P06_0_READ_MASK _MK_MASK_CONST(0xff) +#define DC_B_WINC_BD_V_FILTER_P06_0_WRITE_MASK _MK_MASK_CONST(0xff) +#define DC_B_WINC_BD_V_FILTER_P06_0_BD_V_FILTER_P06C0_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_V_FILTER_P06_0_BD_V_FILTER_P06C0_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_V_FILTER_P06_0_BD_V_FILTER_P06C0_SHIFT) +#define DC_B_WINC_BD_V_FILTER_P06_0_BD_V_FILTER_P06C0_RANGE 7:0 +#define DC_B_WINC_BD_V_FILTER_P06_0_BD_V_FILTER_P06C0_WOFFSET 0x0 +#define DC_B_WINC_BD_V_FILTER_P06_0_BD_V_FILTER_P06C0_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_V_FILTER_P06_0_BD_V_FILTER_P06C0_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_V_FILTER_P06_0_BD_V_FILTER_P06C0_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_V_FILTER_P06_0_BD_V_FILTER_P06C0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_B_WINC_BD_V_FILTER_P07_0 +#define DC_B_WINC_BD_V_FILTER_P07_0 _MK_ADDR_CONST(0xd20) +#define DC_B_WINC_BD_V_FILTER_P07_0_SECURE 0x0 +#define DC_B_WINC_BD_V_FILTER_P07_0_WORD_COUNT 0x1 +#define DC_B_WINC_BD_V_FILTER_P07_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_V_FILTER_P07_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_V_FILTER_P07_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_V_FILTER_P07_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_V_FILTER_P07_0_READ_MASK _MK_MASK_CONST(0xff) +#define DC_B_WINC_BD_V_FILTER_P07_0_WRITE_MASK _MK_MASK_CONST(0xff) +#define DC_B_WINC_BD_V_FILTER_P07_0_BD_V_FILTER_P07C0_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_V_FILTER_P07_0_BD_V_FILTER_P07C0_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_V_FILTER_P07_0_BD_V_FILTER_P07C0_SHIFT) +#define DC_B_WINC_BD_V_FILTER_P07_0_BD_V_FILTER_P07C0_RANGE 7:0 +#define DC_B_WINC_BD_V_FILTER_P07_0_BD_V_FILTER_P07C0_WOFFSET 0x0 +#define DC_B_WINC_BD_V_FILTER_P07_0_BD_V_FILTER_P07C0_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_V_FILTER_P07_0_BD_V_FILTER_P07C0_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_V_FILTER_P07_0_BD_V_FILTER_P07C0_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_V_FILTER_P07_0_BD_V_FILTER_P07C0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_B_WINC_BD_V_FILTER_P08_0 +#define DC_B_WINC_BD_V_FILTER_P08_0 _MK_ADDR_CONST(0xd21) +#define DC_B_WINC_BD_V_FILTER_P08_0_SECURE 0x0 +#define DC_B_WINC_BD_V_FILTER_P08_0_WORD_COUNT 0x1 +#define DC_B_WINC_BD_V_FILTER_P08_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_V_FILTER_P08_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_V_FILTER_P08_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_V_FILTER_P08_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_V_FILTER_P08_0_READ_MASK _MK_MASK_CONST(0xff) +#define DC_B_WINC_BD_V_FILTER_P08_0_WRITE_MASK _MK_MASK_CONST(0xff) +#define DC_B_WINC_BD_V_FILTER_P08_0_BD_V_FILTER_P08C0_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_V_FILTER_P08_0_BD_V_FILTER_P08C0_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_V_FILTER_P08_0_BD_V_FILTER_P08C0_SHIFT) +#define DC_B_WINC_BD_V_FILTER_P08_0_BD_V_FILTER_P08C0_RANGE 7:0 +#define DC_B_WINC_BD_V_FILTER_P08_0_BD_V_FILTER_P08C0_WOFFSET 0x0 +#define DC_B_WINC_BD_V_FILTER_P08_0_BD_V_FILTER_P08C0_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_V_FILTER_P08_0_BD_V_FILTER_P08C0_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_V_FILTER_P08_0_BD_V_FILTER_P08C0_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_V_FILTER_P08_0_BD_V_FILTER_P08C0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_B_WINC_BD_V_FILTER_P09_0 +#define DC_B_WINC_BD_V_FILTER_P09_0 _MK_ADDR_CONST(0xd22) +#define DC_B_WINC_BD_V_FILTER_P09_0_SECURE 0x0 +#define DC_B_WINC_BD_V_FILTER_P09_0_WORD_COUNT 0x1 +#define DC_B_WINC_BD_V_FILTER_P09_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_V_FILTER_P09_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_V_FILTER_P09_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_V_FILTER_P09_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_V_FILTER_P09_0_READ_MASK _MK_MASK_CONST(0xff) +#define DC_B_WINC_BD_V_FILTER_P09_0_WRITE_MASK _MK_MASK_CONST(0xff) +#define DC_B_WINC_BD_V_FILTER_P09_0_BD_V_FILTER_P09C0_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_V_FILTER_P09_0_BD_V_FILTER_P09C0_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_V_FILTER_P09_0_BD_V_FILTER_P09C0_SHIFT) +#define DC_B_WINC_BD_V_FILTER_P09_0_BD_V_FILTER_P09C0_RANGE 7:0 +#define DC_B_WINC_BD_V_FILTER_P09_0_BD_V_FILTER_P09C0_WOFFSET 0x0 +#define DC_B_WINC_BD_V_FILTER_P09_0_BD_V_FILTER_P09C0_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_V_FILTER_P09_0_BD_V_FILTER_P09C0_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_V_FILTER_P09_0_BD_V_FILTER_P09C0_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_V_FILTER_P09_0_BD_V_FILTER_P09C0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_B_WINC_BD_V_FILTER_P0A_0 +#define DC_B_WINC_BD_V_FILTER_P0A_0 _MK_ADDR_CONST(0xd23) +#define DC_B_WINC_BD_V_FILTER_P0A_0_SECURE 0x0 +#define DC_B_WINC_BD_V_FILTER_P0A_0_WORD_COUNT 0x1 +#define DC_B_WINC_BD_V_FILTER_P0A_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_V_FILTER_P0A_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_V_FILTER_P0A_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_V_FILTER_P0A_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_V_FILTER_P0A_0_READ_MASK _MK_MASK_CONST(0xff) +#define DC_B_WINC_BD_V_FILTER_P0A_0_WRITE_MASK _MK_MASK_CONST(0xff) +#define DC_B_WINC_BD_V_FILTER_P0A_0_BD_V_FILTER_P0AC0_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_V_FILTER_P0A_0_BD_V_FILTER_P0AC0_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_V_FILTER_P0A_0_BD_V_FILTER_P0AC0_SHIFT) +#define DC_B_WINC_BD_V_FILTER_P0A_0_BD_V_FILTER_P0AC0_RANGE 7:0 +#define DC_B_WINC_BD_V_FILTER_P0A_0_BD_V_FILTER_P0AC0_WOFFSET 0x0 +#define DC_B_WINC_BD_V_FILTER_P0A_0_BD_V_FILTER_P0AC0_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_V_FILTER_P0A_0_BD_V_FILTER_P0AC0_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_V_FILTER_P0A_0_BD_V_FILTER_P0AC0_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_V_FILTER_P0A_0_BD_V_FILTER_P0AC0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_B_WINC_BD_V_FILTER_P0B_0 +#define DC_B_WINC_BD_V_FILTER_P0B_0 _MK_ADDR_CONST(0xd24) +#define DC_B_WINC_BD_V_FILTER_P0B_0_SECURE 0x0 +#define DC_B_WINC_BD_V_FILTER_P0B_0_WORD_COUNT 0x1 +#define DC_B_WINC_BD_V_FILTER_P0B_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_V_FILTER_P0B_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_V_FILTER_P0B_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_V_FILTER_P0B_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_V_FILTER_P0B_0_READ_MASK _MK_MASK_CONST(0xff) +#define DC_B_WINC_BD_V_FILTER_P0B_0_WRITE_MASK _MK_MASK_CONST(0xff) +#define DC_B_WINC_BD_V_FILTER_P0B_0_BD_V_FILTER_P0BC0_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_V_FILTER_P0B_0_BD_V_FILTER_P0BC0_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_V_FILTER_P0B_0_BD_V_FILTER_P0BC0_SHIFT) +#define DC_B_WINC_BD_V_FILTER_P0B_0_BD_V_FILTER_P0BC0_RANGE 7:0 +#define DC_B_WINC_BD_V_FILTER_P0B_0_BD_V_FILTER_P0BC0_WOFFSET 0x0 +#define DC_B_WINC_BD_V_FILTER_P0B_0_BD_V_FILTER_P0BC0_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_V_FILTER_P0B_0_BD_V_FILTER_P0BC0_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_V_FILTER_P0B_0_BD_V_FILTER_P0BC0_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_V_FILTER_P0B_0_BD_V_FILTER_P0BC0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_B_WINC_BD_V_FILTER_P0C_0 +#define DC_B_WINC_BD_V_FILTER_P0C_0 _MK_ADDR_CONST(0xd25) +#define DC_B_WINC_BD_V_FILTER_P0C_0_SECURE 0x0 +#define DC_B_WINC_BD_V_FILTER_P0C_0_WORD_COUNT 0x1 +#define DC_B_WINC_BD_V_FILTER_P0C_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_V_FILTER_P0C_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_V_FILTER_P0C_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_V_FILTER_P0C_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_V_FILTER_P0C_0_READ_MASK _MK_MASK_CONST(0xff) +#define DC_B_WINC_BD_V_FILTER_P0C_0_WRITE_MASK _MK_MASK_CONST(0xff) +#define DC_B_WINC_BD_V_FILTER_P0C_0_BD_V_FILTER_P0CC0_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_V_FILTER_P0C_0_BD_V_FILTER_P0CC0_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_V_FILTER_P0C_0_BD_V_FILTER_P0CC0_SHIFT) +#define DC_B_WINC_BD_V_FILTER_P0C_0_BD_V_FILTER_P0CC0_RANGE 7:0 +#define DC_B_WINC_BD_V_FILTER_P0C_0_BD_V_FILTER_P0CC0_WOFFSET 0x0 +#define DC_B_WINC_BD_V_FILTER_P0C_0_BD_V_FILTER_P0CC0_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_V_FILTER_P0C_0_BD_V_FILTER_P0CC0_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_V_FILTER_P0C_0_BD_V_FILTER_P0CC0_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_V_FILTER_P0C_0_BD_V_FILTER_P0CC0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_B_WINC_BD_V_FILTER_P0D_0 +#define DC_B_WINC_BD_V_FILTER_P0D_0 _MK_ADDR_CONST(0xd26) +#define DC_B_WINC_BD_V_FILTER_P0D_0_SECURE 0x0 +#define DC_B_WINC_BD_V_FILTER_P0D_0_WORD_COUNT 0x1 +#define DC_B_WINC_BD_V_FILTER_P0D_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_V_FILTER_P0D_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_V_FILTER_P0D_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_V_FILTER_P0D_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_V_FILTER_P0D_0_READ_MASK _MK_MASK_CONST(0xff) +#define DC_B_WINC_BD_V_FILTER_P0D_0_WRITE_MASK _MK_MASK_CONST(0xff) +#define DC_B_WINC_BD_V_FILTER_P0D_0_BD_V_FILTER_P0DC0_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_V_FILTER_P0D_0_BD_V_FILTER_P0DC0_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_V_FILTER_P0D_0_BD_V_FILTER_P0DC0_SHIFT) +#define DC_B_WINC_BD_V_FILTER_P0D_0_BD_V_FILTER_P0DC0_RANGE 7:0 +#define DC_B_WINC_BD_V_FILTER_P0D_0_BD_V_FILTER_P0DC0_WOFFSET 0x0 +#define DC_B_WINC_BD_V_FILTER_P0D_0_BD_V_FILTER_P0DC0_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_V_FILTER_P0D_0_BD_V_FILTER_P0DC0_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_V_FILTER_P0D_0_BD_V_FILTER_P0DC0_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_V_FILTER_P0D_0_BD_V_FILTER_P0DC0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_B_WINC_BD_V_FILTER_P0E_0 +#define DC_B_WINC_BD_V_FILTER_P0E_0 _MK_ADDR_CONST(0xd27) +#define DC_B_WINC_BD_V_FILTER_P0E_0_SECURE 0x0 +#define DC_B_WINC_BD_V_FILTER_P0E_0_WORD_COUNT 0x1 +#define DC_B_WINC_BD_V_FILTER_P0E_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_V_FILTER_P0E_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_V_FILTER_P0E_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_V_FILTER_P0E_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_V_FILTER_P0E_0_READ_MASK _MK_MASK_CONST(0xff) +#define DC_B_WINC_BD_V_FILTER_P0E_0_WRITE_MASK _MK_MASK_CONST(0xff) +#define DC_B_WINC_BD_V_FILTER_P0E_0_BD_V_FILTER_P0EC0_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_V_FILTER_P0E_0_BD_V_FILTER_P0EC0_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_V_FILTER_P0E_0_BD_V_FILTER_P0EC0_SHIFT) +#define DC_B_WINC_BD_V_FILTER_P0E_0_BD_V_FILTER_P0EC0_RANGE 7:0 +#define DC_B_WINC_BD_V_FILTER_P0E_0_BD_V_FILTER_P0EC0_WOFFSET 0x0 +#define DC_B_WINC_BD_V_FILTER_P0E_0_BD_V_FILTER_P0EC0_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_V_FILTER_P0E_0_BD_V_FILTER_P0EC0_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_V_FILTER_P0E_0_BD_V_FILTER_P0EC0_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_V_FILTER_P0E_0_BD_V_FILTER_P0EC0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_B_WINC_BD_V_FILTER_P0F_0 +#define DC_B_WINC_BD_V_FILTER_P0F_0 _MK_ADDR_CONST(0xd28) +#define DC_B_WINC_BD_V_FILTER_P0F_0_SECURE 0x0 +#define DC_B_WINC_BD_V_FILTER_P0F_0_WORD_COUNT 0x1 +#define DC_B_WINC_BD_V_FILTER_P0F_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_V_FILTER_P0F_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_V_FILTER_P0F_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_V_FILTER_P0F_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_V_FILTER_P0F_0_READ_MASK _MK_MASK_CONST(0xff) +#define DC_B_WINC_BD_V_FILTER_P0F_0_WRITE_MASK _MK_MASK_CONST(0xff) +#define DC_B_WINC_BD_V_FILTER_P0F_0_BD_V_FILTER_P0FC0_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_V_FILTER_P0F_0_BD_V_FILTER_P0FC0_FIELD _MK_FIELD_CONST(0xff, DC_B_WINC_BD_V_FILTER_P0F_0_BD_V_FILTER_P0FC0_SHIFT) +#define DC_B_WINC_BD_V_FILTER_P0F_0_BD_V_FILTER_P0FC0_RANGE 7:0 +#define DC_B_WINC_BD_V_FILTER_P0F_0_BD_V_FILTER_P0FC0_WOFFSET 0x0 +#define DC_B_WINC_BD_V_FILTER_P0F_0_BD_V_FILTER_P0FC0_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_V_FILTER_P0F_0_BD_V_FILTER_P0FC0_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_V_FILTER_P0F_0_BD_V_FILTER_P0FC0_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_V_FILTER_P0F_0_BD_V_FILTER_P0FC0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_B_WINC_BD_H_FILTER_HI_P00_0 +#define DC_B_WINC_BD_H_FILTER_HI_P00_0 _MK_ADDR_CONST(0xd29) +#define DC_B_WINC_BD_H_FILTER_HI_P00_0_SECURE 0x0 +#define DC_B_WINC_BD_H_FILTER_HI_P00_0_WORD_COUNT 0x1 +#define DC_B_WINC_BD_H_FILTER_HI_P00_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P00_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P00_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P00_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P00_0_READ_MASK _MK_MASK_CONST(0x3ff) +#define DC_B_WINC_BD_H_FILTER_HI_P00_0_WRITE_MASK _MK_MASK_CONST(0x3ff) +#define DC_B_WINC_BD_H_FILTER_HI_P00_0_BD_H_FILTER_HI_P00C0_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_H_FILTER_HI_P00_0_BD_H_FILTER_HI_P00C0_FIELD _MK_FIELD_CONST(0x3, DC_B_WINC_BD_H_FILTER_HI_P00_0_BD_H_FILTER_HI_P00C0_SHIFT) +#define DC_B_WINC_BD_H_FILTER_HI_P00_0_BD_H_FILTER_HI_P00C0_RANGE 1:0 +#define DC_B_WINC_BD_H_FILTER_HI_P00_0_BD_H_FILTER_HI_P00C0_WOFFSET 0x0 +#define DC_B_WINC_BD_H_FILTER_HI_P00_0_BD_H_FILTER_HI_P00C0_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P00_0_BD_H_FILTER_HI_P00C0_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P00_0_BD_H_FILTER_HI_P00C0_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P00_0_BD_H_FILTER_HI_P00C0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_H_FILTER_HI_P00_0_BD_H_FILTER_HI_P00C1_SHIFT _MK_SHIFT_CONST(2) +#define DC_B_WINC_BD_H_FILTER_HI_P00_0_BD_H_FILTER_HI_P00C1_FIELD _MK_FIELD_CONST(0x3, DC_B_WINC_BD_H_FILTER_HI_P00_0_BD_H_FILTER_HI_P00C1_SHIFT) +#define DC_B_WINC_BD_H_FILTER_HI_P00_0_BD_H_FILTER_HI_P00C1_RANGE 3:2 +#define DC_B_WINC_BD_H_FILTER_HI_P00_0_BD_H_FILTER_HI_P00C1_WOFFSET 0x0 +#define DC_B_WINC_BD_H_FILTER_HI_P00_0_BD_H_FILTER_HI_P00C1_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P00_0_BD_H_FILTER_HI_P00C1_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P00_0_BD_H_FILTER_HI_P00C1_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P00_0_BD_H_FILTER_HI_P00C1_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_H_FILTER_HI_P00_0_BD_H_FILTER_HI_P00C2_SHIFT _MK_SHIFT_CONST(4) +#define DC_B_WINC_BD_H_FILTER_HI_P00_0_BD_H_FILTER_HI_P00C2_FIELD _MK_FIELD_CONST(0x1, DC_B_WINC_BD_H_FILTER_HI_P00_0_BD_H_FILTER_HI_P00C2_SHIFT) +#define DC_B_WINC_BD_H_FILTER_HI_P00_0_BD_H_FILTER_HI_P00C2_RANGE 4:4 +#define DC_B_WINC_BD_H_FILTER_HI_P00_0_BD_H_FILTER_HI_P00C2_WOFFSET 0x0 +#define DC_B_WINC_BD_H_FILTER_HI_P00_0_BD_H_FILTER_HI_P00C2_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P00_0_BD_H_FILTER_HI_P00C2_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P00_0_BD_H_FILTER_HI_P00C2_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P00_0_BD_H_FILTER_HI_P00C2_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_H_FILTER_HI_P00_0_BD_H_FILTER_HI_P00C3_SHIFT _MK_SHIFT_CONST(5) +#define DC_B_WINC_BD_H_FILTER_HI_P00_0_BD_H_FILTER_HI_P00C3_FIELD _MK_FIELD_CONST(0x1, DC_B_WINC_BD_H_FILTER_HI_P00_0_BD_H_FILTER_HI_P00C3_SHIFT) +#define DC_B_WINC_BD_H_FILTER_HI_P00_0_BD_H_FILTER_HI_P00C3_RANGE 5:5 +#define DC_B_WINC_BD_H_FILTER_HI_P00_0_BD_H_FILTER_HI_P00C3_WOFFSET 0x0 +#define DC_B_WINC_BD_H_FILTER_HI_P00_0_BD_H_FILTER_HI_P00C3_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P00_0_BD_H_FILTER_HI_P00C3_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P00_0_BD_H_FILTER_HI_P00C3_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P00_0_BD_H_FILTER_HI_P00C3_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_H_FILTER_HI_P00_0_BD_H_FILTER_HI_P00C4_SHIFT _MK_SHIFT_CONST(6) +#define DC_B_WINC_BD_H_FILTER_HI_P00_0_BD_H_FILTER_HI_P00C4_FIELD _MK_FIELD_CONST(0x3, DC_B_WINC_BD_H_FILTER_HI_P00_0_BD_H_FILTER_HI_P00C4_SHIFT) +#define DC_B_WINC_BD_H_FILTER_HI_P00_0_BD_H_FILTER_HI_P00C4_RANGE 7:6 +#define DC_B_WINC_BD_H_FILTER_HI_P00_0_BD_H_FILTER_HI_P00C4_WOFFSET 0x0 +#define DC_B_WINC_BD_H_FILTER_HI_P00_0_BD_H_FILTER_HI_P00C4_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P00_0_BD_H_FILTER_HI_P00C4_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P00_0_BD_H_FILTER_HI_P00C4_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P00_0_BD_H_FILTER_HI_P00C4_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_H_FILTER_HI_P00_0_BD_H_FILTER_HI_P00C5_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_H_FILTER_HI_P00_0_BD_H_FILTER_HI_P00C5_FIELD _MK_FIELD_CONST(0x3, DC_B_WINC_BD_H_FILTER_HI_P00_0_BD_H_FILTER_HI_P00C5_SHIFT) +#define DC_B_WINC_BD_H_FILTER_HI_P00_0_BD_H_FILTER_HI_P00C5_RANGE 9:8 +#define DC_B_WINC_BD_H_FILTER_HI_P00_0_BD_H_FILTER_HI_P00C5_WOFFSET 0x0 +#define DC_B_WINC_BD_H_FILTER_HI_P00_0_BD_H_FILTER_HI_P00C5_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P00_0_BD_H_FILTER_HI_P00C5_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P00_0_BD_H_FILTER_HI_P00C5_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P00_0_BD_H_FILTER_HI_P00C5_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_B_WINC_BD_H_FILTER_HI_P01_0 +#define DC_B_WINC_BD_H_FILTER_HI_P01_0 _MK_ADDR_CONST(0xd2a) +#define DC_B_WINC_BD_H_FILTER_HI_P01_0_SECURE 0x0 +#define DC_B_WINC_BD_H_FILTER_HI_P01_0_WORD_COUNT 0x1 +#define DC_B_WINC_BD_H_FILTER_HI_P01_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P01_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P01_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P01_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P01_0_READ_MASK _MK_MASK_CONST(0x3ff) +#define DC_B_WINC_BD_H_FILTER_HI_P01_0_WRITE_MASK _MK_MASK_CONST(0x3ff) +#define DC_B_WINC_BD_H_FILTER_HI_P01_0_BD_H_FILTER_HI_P01C0_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_H_FILTER_HI_P01_0_BD_H_FILTER_HI_P01C0_FIELD _MK_FIELD_CONST(0x3, DC_B_WINC_BD_H_FILTER_HI_P01_0_BD_H_FILTER_HI_P01C0_SHIFT) +#define DC_B_WINC_BD_H_FILTER_HI_P01_0_BD_H_FILTER_HI_P01C0_RANGE 1:0 +#define DC_B_WINC_BD_H_FILTER_HI_P01_0_BD_H_FILTER_HI_P01C0_WOFFSET 0x0 +#define DC_B_WINC_BD_H_FILTER_HI_P01_0_BD_H_FILTER_HI_P01C0_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P01_0_BD_H_FILTER_HI_P01C0_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P01_0_BD_H_FILTER_HI_P01C0_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P01_0_BD_H_FILTER_HI_P01C0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_H_FILTER_HI_P01_0_BD_H_FILTER_HI_P01C1_SHIFT _MK_SHIFT_CONST(2) +#define DC_B_WINC_BD_H_FILTER_HI_P01_0_BD_H_FILTER_HI_P01C1_FIELD _MK_FIELD_CONST(0x3, DC_B_WINC_BD_H_FILTER_HI_P01_0_BD_H_FILTER_HI_P01C1_SHIFT) +#define DC_B_WINC_BD_H_FILTER_HI_P01_0_BD_H_FILTER_HI_P01C1_RANGE 3:2 +#define DC_B_WINC_BD_H_FILTER_HI_P01_0_BD_H_FILTER_HI_P01C1_WOFFSET 0x0 +#define DC_B_WINC_BD_H_FILTER_HI_P01_0_BD_H_FILTER_HI_P01C1_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P01_0_BD_H_FILTER_HI_P01C1_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P01_0_BD_H_FILTER_HI_P01C1_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P01_0_BD_H_FILTER_HI_P01C1_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_H_FILTER_HI_P01_0_BD_H_FILTER_HI_P01C2_SHIFT _MK_SHIFT_CONST(4) +#define DC_B_WINC_BD_H_FILTER_HI_P01_0_BD_H_FILTER_HI_P01C2_FIELD _MK_FIELD_CONST(0x1, DC_B_WINC_BD_H_FILTER_HI_P01_0_BD_H_FILTER_HI_P01C2_SHIFT) +#define DC_B_WINC_BD_H_FILTER_HI_P01_0_BD_H_FILTER_HI_P01C2_RANGE 4:4 +#define DC_B_WINC_BD_H_FILTER_HI_P01_0_BD_H_FILTER_HI_P01C2_WOFFSET 0x0 +#define DC_B_WINC_BD_H_FILTER_HI_P01_0_BD_H_FILTER_HI_P01C2_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P01_0_BD_H_FILTER_HI_P01C2_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P01_0_BD_H_FILTER_HI_P01C2_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P01_0_BD_H_FILTER_HI_P01C2_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_H_FILTER_HI_P01_0_BD_H_FILTER_HI_P01C3_SHIFT _MK_SHIFT_CONST(5) +#define DC_B_WINC_BD_H_FILTER_HI_P01_0_BD_H_FILTER_HI_P01C3_FIELD _MK_FIELD_CONST(0x1, DC_B_WINC_BD_H_FILTER_HI_P01_0_BD_H_FILTER_HI_P01C3_SHIFT) +#define DC_B_WINC_BD_H_FILTER_HI_P01_0_BD_H_FILTER_HI_P01C3_RANGE 5:5 +#define DC_B_WINC_BD_H_FILTER_HI_P01_0_BD_H_FILTER_HI_P01C3_WOFFSET 0x0 +#define DC_B_WINC_BD_H_FILTER_HI_P01_0_BD_H_FILTER_HI_P01C3_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P01_0_BD_H_FILTER_HI_P01C3_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P01_0_BD_H_FILTER_HI_P01C3_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P01_0_BD_H_FILTER_HI_P01C3_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_H_FILTER_HI_P01_0_BD_H_FILTER_HI_P01C4_SHIFT _MK_SHIFT_CONST(6) +#define DC_B_WINC_BD_H_FILTER_HI_P01_0_BD_H_FILTER_HI_P01C4_FIELD _MK_FIELD_CONST(0x3, DC_B_WINC_BD_H_FILTER_HI_P01_0_BD_H_FILTER_HI_P01C4_SHIFT) +#define DC_B_WINC_BD_H_FILTER_HI_P01_0_BD_H_FILTER_HI_P01C4_RANGE 7:6 +#define DC_B_WINC_BD_H_FILTER_HI_P01_0_BD_H_FILTER_HI_P01C4_WOFFSET 0x0 +#define DC_B_WINC_BD_H_FILTER_HI_P01_0_BD_H_FILTER_HI_P01C4_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P01_0_BD_H_FILTER_HI_P01C4_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P01_0_BD_H_FILTER_HI_P01C4_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P01_0_BD_H_FILTER_HI_P01C4_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_H_FILTER_HI_P01_0_BD_H_FILTER_HI_P01C5_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_H_FILTER_HI_P01_0_BD_H_FILTER_HI_P01C5_FIELD _MK_FIELD_CONST(0x3, DC_B_WINC_BD_H_FILTER_HI_P01_0_BD_H_FILTER_HI_P01C5_SHIFT) +#define DC_B_WINC_BD_H_FILTER_HI_P01_0_BD_H_FILTER_HI_P01C5_RANGE 9:8 +#define DC_B_WINC_BD_H_FILTER_HI_P01_0_BD_H_FILTER_HI_P01C5_WOFFSET 0x0 +#define DC_B_WINC_BD_H_FILTER_HI_P01_0_BD_H_FILTER_HI_P01C5_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P01_0_BD_H_FILTER_HI_P01C5_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P01_0_BD_H_FILTER_HI_P01C5_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P01_0_BD_H_FILTER_HI_P01C5_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_B_WINC_BD_H_FILTER_HI_P02_0 +#define DC_B_WINC_BD_H_FILTER_HI_P02_0 _MK_ADDR_CONST(0xd2b) +#define DC_B_WINC_BD_H_FILTER_HI_P02_0_SECURE 0x0 +#define DC_B_WINC_BD_H_FILTER_HI_P02_0_WORD_COUNT 0x1 +#define DC_B_WINC_BD_H_FILTER_HI_P02_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P02_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P02_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P02_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P02_0_READ_MASK _MK_MASK_CONST(0x3ff) +#define DC_B_WINC_BD_H_FILTER_HI_P02_0_WRITE_MASK _MK_MASK_CONST(0x3ff) +#define DC_B_WINC_BD_H_FILTER_HI_P02_0_BD_H_FILTER_HI_P02C0_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_H_FILTER_HI_P02_0_BD_H_FILTER_HI_P02C0_FIELD _MK_FIELD_CONST(0x3, DC_B_WINC_BD_H_FILTER_HI_P02_0_BD_H_FILTER_HI_P02C0_SHIFT) +#define DC_B_WINC_BD_H_FILTER_HI_P02_0_BD_H_FILTER_HI_P02C0_RANGE 1:0 +#define DC_B_WINC_BD_H_FILTER_HI_P02_0_BD_H_FILTER_HI_P02C0_WOFFSET 0x0 +#define DC_B_WINC_BD_H_FILTER_HI_P02_0_BD_H_FILTER_HI_P02C0_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P02_0_BD_H_FILTER_HI_P02C0_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P02_0_BD_H_FILTER_HI_P02C0_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P02_0_BD_H_FILTER_HI_P02C0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_H_FILTER_HI_P02_0_BD_H_FILTER_HI_P02C1_SHIFT _MK_SHIFT_CONST(2) +#define DC_B_WINC_BD_H_FILTER_HI_P02_0_BD_H_FILTER_HI_P02C1_FIELD _MK_FIELD_CONST(0x3, DC_B_WINC_BD_H_FILTER_HI_P02_0_BD_H_FILTER_HI_P02C1_SHIFT) +#define DC_B_WINC_BD_H_FILTER_HI_P02_0_BD_H_FILTER_HI_P02C1_RANGE 3:2 +#define DC_B_WINC_BD_H_FILTER_HI_P02_0_BD_H_FILTER_HI_P02C1_WOFFSET 0x0 +#define DC_B_WINC_BD_H_FILTER_HI_P02_0_BD_H_FILTER_HI_P02C1_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P02_0_BD_H_FILTER_HI_P02C1_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P02_0_BD_H_FILTER_HI_P02C1_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P02_0_BD_H_FILTER_HI_P02C1_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_H_FILTER_HI_P02_0_BD_H_FILTER_HI_P02C2_SHIFT _MK_SHIFT_CONST(4) +#define DC_B_WINC_BD_H_FILTER_HI_P02_0_BD_H_FILTER_HI_P02C2_FIELD _MK_FIELD_CONST(0x1, DC_B_WINC_BD_H_FILTER_HI_P02_0_BD_H_FILTER_HI_P02C2_SHIFT) +#define DC_B_WINC_BD_H_FILTER_HI_P02_0_BD_H_FILTER_HI_P02C2_RANGE 4:4 +#define DC_B_WINC_BD_H_FILTER_HI_P02_0_BD_H_FILTER_HI_P02C2_WOFFSET 0x0 +#define DC_B_WINC_BD_H_FILTER_HI_P02_0_BD_H_FILTER_HI_P02C2_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P02_0_BD_H_FILTER_HI_P02C2_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P02_0_BD_H_FILTER_HI_P02C2_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P02_0_BD_H_FILTER_HI_P02C2_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_H_FILTER_HI_P02_0_BD_H_FILTER_HI_P02C3_SHIFT _MK_SHIFT_CONST(5) +#define DC_B_WINC_BD_H_FILTER_HI_P02_0_BD_H_FILTER_HI_P02C3_FIELD _MK_FIELD_CONST(0x1, DC_B_WINC_BD_H_FILTER_HI_P02_0_BD_H_FILTER_HI_P02C3_SHIFT) +#define DC_B_WINC_BD_H_FILTER_HI_P02_0_BD_H_FILTER_HI_P02C3_RANGE 5:5 +#define DC_B_WINC_BD_H_FILTER_HI_P02_0_BD_H_FILTER_HI_P02C3_WOFFSET 0x0 +#define DC_B_WINC_BD_H_FILTER_HI_P02_0_BD_H_FILTER_HI_P02C3_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P02_0_BD_H_FILTER_HI_P02C3_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P02_0_BD_H_FILTER_HI_P02C3_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P02_0_BD_H_FILTER_HI_P02C3_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_H_FILTER_HI_P02_0_BD_H_FILTER_HI_P02C4_SHIFT _MK_SHIFT_CONST(6) +#define DC_B_WINC_BD_H_FILTER_HI_P02_0_BD_H_FILTER_HI_P02C4_FIELD _MK_FIELD_CONST(0x3, DC_B_WINC_BD_H_FILTER_HI_P02_0_BD_H_FILTER_HI_P02C4_SHIFT) +#define DC_B_WINC_BD_H_FILTER_HI_P02_0_BD_H_FILTER_HI_P02C4_RANGE 7:6 +#define DC_B_WINC_BD_H_FILTER_HI_P02_0_BD_H_FILTER_HI_P02C4_WOFFSET 0x0 +#define DC_B_WINC_BD_H_FILTER_HI_P02_0_BD_H_FILTER_HI_P02C4_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P02_0_BD_H_FILTER_HI_P02C4_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P02_0_BD_H_FILTER_HI_P02C4_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P02_0_BD_H_FILTER_HI_P02C4_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_H_FILTER_HI_P02_0_BD_H_FILTER_HI_P02C5_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_H_FILTER_HI_P02_0_BD_H_FILTER_HI_P02C5_FIELD _MK_FIELD_CONST(0x3, DC_B_WINC_BD_H_FILTER_HI_P02_0_BD_H_FILTER_HI_P02C5_SHIFT) +#define DC_B_WINC_BD_H_FILTER_HI_P02_0_BD_H_FILTER_HI_P02C5_RANGE 9:8 +#define DC_B_WINC_BD_H_FILTER_HI_P02_0_BD_H_FILTER_HI_P02C5_WOFFSET 0x0 +#define DC_B_WINC_BD_H_FILTER_HI_P02_0_BD_H_FILTER_HI_P02C5_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P02_0_BD_H_FILTER_HI_P02C5_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P02_0_BD_H_FILTER_HI_P02C5_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P02_0_BD_H_FILTER_HI_P02C5_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_B_WINC_BD_H_FILTER_HI_P03_0 +#define DC_B_WINC_BD_H_FILTER_HI_P03_0 _MK_ADDR_CONST(0xd2c) +#define DC_B_WINC_BD_H_FILTER_HI_P03_0_SECURE 0x0 +#define DC_B_WINC_BD_H_FILTER_HI_P03_0_WORD_COUNT 0x1 +#define DC_B_WINC_BD_H_FILTER_HI_P03_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P03_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P03_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P03_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P03_0_READ_MASK _MK_MASK_CONST(0x3ff) +#define DC_B_WINC_BD_H_FILTER_HI_P03_0_WRITE_MASK _MK_MASK_CONST(0x3ff) +#define DC_B_WINC_BD_H_FILTER_HI_P03_0_BD_H_FILTER_HI_P03C0_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_H_FILTER_HI_P03_0_BD_H_FILTER_HI_P03C0_FIELD _MK_FIELD_CONST(0x3, DC_B_WINC_BD_H_FILTER_HI_P03_0_BD_H_FILTER_HI_P03C0_SHIFT) +#define DC_B_WINC_BD_H_FILTER_HI_P03_0_BD_H_FILTER_HI_P03C0_RANGE 1:0 +#define DC_B_WINC_BD_H_FILTER_HI_P03_0_BD_H_FILTER_HI_P03C0_WOFFSET 0x0 +#define DC_B_WINC_BD_H_FILTER_HI_P03_0_BD_H_FILTER_HI_P03C0_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P03_0_BD_H_FILTER_HI_P03C0_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P03_0_BD_H_FILTER_HI_P03C0_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P03_0_BD_H_FILTER_HI_P03C0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_H_FILTER_HI_P03_0_BD_H_FILTER_HI_P03C1_SHIFT _MK_SHIFT_CONST(2) +#define DC_B_WINC_BD_H_FILTER_HI_P03_0_BD_H_FILTER_HI_P03C1_FIELD _MK_FIELD_CONST(0x3, DC_B_WINC_BD_H_FILTER_HI_P03_0_BD_H_FILTER_HI_P03C1_SHIFT) +#define DC_B_WINC_BD_H_FILTER_HI_P03_0_BD_H_FILTER_HI_P03C1_RANGE 3:2 +#define DC_B_WINC_BD_H_FILTER_HI_P03_0_BD_H_FILTER_HI_P03C1_WOFFSET 0x0 +#define DC_B_WINC_BD_H_FILTER_HI_P03_0_BD_H_FILTER_HI_P03C1_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P03_0_BD_H_FILTER_HI_P03C1_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P03_0_BD_H_FILTER_HI_P03C1_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P03_0_BD_H_FILTER_HI_P03C1_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_H_FILTER_HI_P03_0_BD_H_FILTER_HI_P03C2_SHIFT _MK_SHIFT_CONST(4) +#define DC_B_WINC_BD_H_FILTER_HI_P03_0_BD_H_FILTER_HI_P03C2_FIELD _MK_FIELD_CONST(0x1, DC_B_WINC_BD_H_FILTER_HI_P03_0_BD_H_FILTER_HI_P03C2_SHIFT) +#define DC_B_WINC_BD_H_FILTER_HI_P03_0_BD_H_FILTER_HI_P03C2_RANGE 4:4 +#define DC_B_WINC_BD_H_FILTER_HI_P03_0_BD_H_FILTER_HI_P03C2_WOFFSET 0x0 +#define DC_B_WINC_BD_H_FILTER_HI_P03_0_BD_H_FILTER_HI_P03C2_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P03_0_BD_H_FILTER_HI_P03C2_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P03_0_BD_H_FILTER_HI_P03C2_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P03_0_BD_H_FILTER_HI_P03C2_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_H_FILTER_HI_P03_0_BD_H_FILTER_HI_P03C3_SHIFT _MK_SHIFT_CONST(5) +#define DC_B_WINC_BD_H_FILTER_HI_P03_0_BD_H_FILTER_HI_P03C3_FIELD _MK_FIELD_CONST(0x1, DC_B_WINC_BD_H_FILTER_HI_P03_0_BD_H_FILTER_HI_P03C3_SHIFT) +#define DC_B_WINC_BD_H_FILTER_HI_P03_0_BD_H_FILTER_HI_P03C3_RANGE 5:5 +#define DC_B_WINC_BD_H_FILTER_HI_P03_0_BD_H_FILTER_HI_P03C3_WOFFSET 0x0 +#define DC_B_WINC_BD_H_FILTER_HI_P03_0_BD_H_FILTER_HI_P03C3_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P03_0_BD_H_FILTER_HI_P03C3_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P03_0_BD_H_FILTER_HI_P03C3_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P03_0_BD_H_FILTER_HI_P03C3_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_H_FILTER_HI_P03_0_BD_H_FILTER_HI_P03C4_SHIFT _MK_SHIFT_CONST(6) +#define DC_B_WINC_BD_H_FILTER_HI_P03_0_BD_H_FILTER_HI_P03C4_FIELD _MK_FIELD_CONST(0x3, DC_B_WINC_BD_H_FILTER_HI_P03_0_BD_H_FILTER_HI_P03C4_SHIFT) +#define DC_B_WINC_BD_H_FILTER_HI_P03_0_BD_H_FILTER_HI_P03C4_RANGE 7:6 +#define DC_B_WINC_BD_H_FILTER_HI_P03_0_BD_H_FILTER_HI_P03C4_WOFFSET 0x0 +#define DC_B_WINC_BD_H_FILTER_HI_P03_0_BD_H_FILTER_HI_P03C4_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P03_0_BD_H_FILTER_HI_P03C4_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P03_0_BD_H_FILTER_HI_P03C4_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P03_0_BD_H_FILTER_HI_P03C4_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_H_FILTER_HI_P03_0_BD_H_FILTER_HI_P03C5_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_H_FILTER_HI_P03_0_BD_H_FILTER_HI_P03C5_FIELD _MK_FIELD_CONST(0x3, DC_B_WINC_BD_H_FILTER_HI_P03_0_BD_H_FILTER_HI_P03C5_SHIFT) +#define DC_B_WINC_BD_H_FILTER_HI_P03_0_BD_H_FILTER_HI_P03C5_RANGE 9:8 +#define DC_B_WINC_BD_H_FILTER_HI_P03_0_BD_H_FILTER_HI_P03C5_WOFFSET 0x0 +#define DC_B_WINC_BD_H_FILTER_HI_P03_0_BD_H_FILTER_HI_P03C5_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P03_0_BD_H_FILTER_HI_P03C5_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P03_0_BD_H_FILTER_HI_P03C5_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P03_0_BD_H_FILTER_HI_P03C5_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_B_WINC_BD_H_FILTER_HI_P04_0 +#define DC_B_WINC_BD_H_FILTER_HI_P04_0 _MK_ADDR_CONST(0xd2d) +#define DC_B_WINC_BD_H_FILTER_HI_P04_0_SECURE 0x0 +#define DC_B_WINC_BD_H_FILTER_HI_P04_0_WORD_COUNT 0x1 +#define DC_B_WINC_BD_H_FILTER_HI_P04_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P04_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P04_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P04_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P04_0_READ_MASK _MK_MASK_CONST(0x3ff) +#define DC_B_WINC_BD_H_FILTER_HI_P04_0_WRITE_MASK _MK_MASK_CONST(0x3ff) +#define DC_B_WINC_BD_H_FILTER_HI_P04_0_BD_H_FILTER_HI_P04C0_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_H_FILTER_HI_P04_0_BD_H_FILTER_HI_P04C0_FIELD _MK_FIELD_CONST(0x3, DC_B_WINC_BD_H_FILTER_HI_P04_0_BD_H_FILTER_HI_P04C0_SHIFT) +#define DC_B_WINC_BD_H_FILTER_HI_P04_0_BD_H_FILTER_HI_P04C0_RANGE 1:0 +#define DC_B_WINC_BD_H_FILTER_HI_P04_0_BD_H_FILTER_HI_P04C0_WOFFSET 0x0 +#define DC_B_WINC_BD_H_FILTER_HI_P04_0_BD_H_FILTER_HI_P04C0_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P04_0_BD_H_FILTER_HI_P04C0_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P04_0_BD_H_FILTER_HI_P04C0_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P04_0_BD_H_FILTER_HI_P04C0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_H_FILTER_HI_P04_0_BD_H_FILTER_HI_P04C1_SHIFT _MK_SHIFT_CONST(2) +#define DC_B_WINC_BD_H_FILTER_HI_P04_0_BD_H_FILTER_HI_P04C1_FIELD _MK_FIELD_CONST(0x3, DC_B_WINC_BD_H_FILTER_HI_P04_0_BD_H_FILTER_HI_P04C1_SHIFT) +#define DC_B_WINC_BD_H_FILTER_HI_P04_0_BD_H_FILTER_HI_P04C1_RANGE 3:2 +#define DC_B_WINC_BD_H_FILTER_HI_P04_0_BD_H_FILTER_HI_P04C1_WOFFSET 0x0 +#define DC_B_WINC_BD_H_FILTER_HI_P04_0_BD_H_FILTER_HI_P04C1_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P04_0_BD_H_FILTER_HI_P04C1_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P04_0_BD_H_FILTER_HI_P04C1_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P04_0_BD_H_FILTER_HI_P04C1_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_H_FILTER_HI_P04_0_BD_H_FILTER_HI_P04C2_SHIFT _MK_SHIFT_CONST(4) +#define DC_B_WINC_BD_H_FILTER_HI_P04_0_BD_H_FILTER_HI_P04C2_FIELD _MK_FIELD_CONST(0x1, DC_B_WINC_BD_H_FILTER_HI_P04_0_BD_H_FILTER_HI_P04C2_SHIFT) +#define DC_B_WINC_BD_H_FILTER_HI_P04_0_BD_H_FILTER_HI_P04C2_RANGE 4:4 +#define DC_B_WINC_BD_H_FILTER_HI_P04_0_BD_H_FILTER_HI_P04C2_WOFFSET 0x0 +#define DC_B_WINC_BD_H_FILTER_HI_P04_0_BD_H_FILTER_HI_P04C2_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P04_0_BD_H_FILTER_HI_P04C2_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P04_0_BD_H_FILTER_HI_P04C2_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P04_0_BD_H_FILTER_HI_P04C2_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_H_FILTER_HI_P04_0_BD_H_FILTER_HI_P04C3_SHIFT _MK_SHIFT_CONST(5) +#define DC_B_WINC_BD_H_FILTER_HI_P04_0_BD_H_FILTER_HI_P04C3_FIELD _MK_FIELD_CONST(0x1, DC_B_WINC_BD_H_FILTER_HI_P04_0_BD_H_FILTER_HI_P04C3_SHIFT) +#define DC_B_WINC_BD_H_FILTER_HI_P04_0_BD_H_FILTER_HI_P04C3_RANGE 5:5 +#define DC_B_WINC_BD_H_FILTER_HI_P04_0_BD_H_FILTER_HI_P04C3_WOFFSET 0x0 +#define DC_B_WINC_BD_H_FILTER_HI_P04_0_BD_H_FILTER_HI_P04C3_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P04_0_BD_H_FILTER_HI_P04C3_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P04_0_BD_H_FILTER_HI_P04C3_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P04_0_BD_H_FILTER_HI_P04C3_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_H_FILTER_HI_P04_0_BD_H_FILTER_HI_P04C4_SHIFT _MK_SHIFT_CONST(6) +#define DC_B_WINC_BD_H_FILTER_HI_P04_0_BD_H_FILTER_HI_P04C4_FIELD _MK_FIELD_CONST(0x3, DC_B_WINC_BD_H_FILTER_HI_P04_0_BD_H_FILTER_HI_P04C4_SHIFT) +#define DC_B_WINC_BD_H_FILTER_HI_P04_0_BD_H_FILTER_HI_P04C4_RANGE 7:6 +#define DC_B_WINC_BD_H_FILTER_HI_P04_0_BD_H_FILTER_HI_P04C4_WOFFSET 0x0 +#define DC_B_WINC_BD_H_FILTER_HI_P04_0_BD_H_FILTER_HI_P04C4_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P04_0_BD_H_FILTER_HI_P04C4_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P04_0_BD_H_FILTER_HI_P04C4_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P04_0_BD_H_FILTER_HI_P04C4_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_H_FILTER_HI_P04_0_BD_H_FILTER_HI_P04C5_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_H_FILTER_HI_P04_0_BD_H_FILTER_HI_P04C5_FIELD _MK_FIELD_CONST(0x3, DC_B_WINC_BD_H_FILTER_HI_P04_0_BD_H_FILTER_HI_P04C5_SHIFT) +#define DC_B_WINC_BD_H_FILTER_HI_P04_0_BD_H_FILTER_HI_P04C5_RANGE 9:8 +#define DC_B_WINC_BD_H_FILTER_HI_P04_0_BD_H_FILTER_HI_P04C5_WOFFSET 0x0 +#define DC_B_WINC_BD_H_FILTER_HI_P04_0_BD_H_FILTER_HI_P04C5_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P04_0_BD_H_FILTER_HI_P04C5_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P04_0_BD_H_FILTER_HI_P04C5_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P04_0_BD_H_FILTER_HI_P04C5_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_B_WINC_BD_H_FILTER_HI_P05_0 +#define DC_B_WINC_BD_H_FILTER_HI_P05_0 _MK_ADDR_CONST(0xd2e) +#define DC_B_WINC_BD_H_FILTER_HI_P05_0_SECURE 0x0 +#define DC_B_WINC_BD_H_FILTER_HI_P05_0_WORD_COUNT 0x1 +#define DC_B_WINC_BD_H_FILTER_HI_P05_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P05_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P05_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P05_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P05_0_READ_MASK _MK_MASK_CONST(0x3ff) +#define DC_B_WINC_BD_H_FILTER_HI_P05_0_WRITE_MASK _MK_MASK_CONST(0x3ff) +#define DC_B_WINC_BD_H_FILTER_HI_P05_0_BD_H_FILTER_HI_P05C0_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_H_FILTER_HI_P05_0_BD_H_FILTER_HI_P05C0_FIELD _MK_FIELD_CONST(0x3, DC_B_WINC_BD_H_FILTER_HI_P05_0_BD_H_FILTER_HI_P05C0_SHIFT) +#define DC_B_WINC_BD_H_FILTER_HI_P05_0_BD_H_FILTER_HI_P05C0_RANGE 1:0 +#define DC_B_WINC_BD_H_FILTER_HI_P05_0_BD_H_FILTER_HI_P05C0_WOFFSET 0x0 +#define DC_B_WINC_BD_H_FILTER_HI_P05_0_BD_H_FILTER_HI_P05C0_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P05_0_BD_H_FILTER_HI_P05C0_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P05_0_BD_H_FILTER_HI_P05C0_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P05_0_BD_H_FILTER_HI_P05C0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_H_FILTER_HI_P05_0_BD_H_FILTER_HI_P05C1_SHIFT _MK_SHIFT_CONST(2) +#define DC_B_WINC_BD_H_FILTER_HI_P05_0_BD_H_FILTER_HI_P05C1_FIELD _MK_FIELD_CONST(0x3, DC_B_WINC_BD_H_FILTER_HI_P05_0_BD_H_FILTER_HI_P05C1_SHIFT) +#define DC_B_WINC_BD_H_FILTER_HI_P05_0_BD_H_FILTER_HI_P05C1_RANGE 3:2 +#define DC_B_WINC_BD_H_FILTER_HI_P05_0_BD_H_FILTER_HI_P05C1_WOFFSET 0x0 +#define DC_B_WINC_BD_H_FILTER_HI_P05_0_BD_H_FILTER_HI_P05C1_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P05_0_BD_H_FILTER_HI_P05C1_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P05_0_BD_H_FILTER_HI_P05C1_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P05_0_BD_H_FILTER_HI_P05C1_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_H_FILTER_HI_P05_0_BD_H_FILTER_HI_P05C2_SHIFT _MK_SHIFT_CONST(4) +#define DC_B_WINC_BD_H_FILTER_HI_P05_0_BD_H_FILTER_HI_P05C2_FIELD _MK_FIELD_CONST(0x1, DC_B_WINC_BD_H_FILTER_HI_P05_0_BD_H_FILTER_HI_P05C2_SHIFT) +#define DC_B_WINC_BD_H_FILTER_HI_P05_0_BD_H_FILTER_HI_P05C2_RANGE 4:4 +#define DC_B_WINC_BD_H_FILTER_HI_P05_0_BD_H_FILTER_HI_P05C2_WOFFSET 0x0 +#define DC_B_WINC_BD_H_FILTER_HI_P05_0_BD_H_FILTER_HI_P05C2_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P05_0_BD_H_FILTER_HI_P05C2_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P05_0_BD_H_FILTER_HI_P05C2_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P05_0_BD_H_FILTER_HI_P05C2_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_H_FILTER_HI_P05_0_BD_H_FILTER_HI_P05C3_SHIFT _MK_SHIFT_CONST(5) +#define DC_B_WINC_BD_H_FILTER_HI_P05_0_BD_H_FILTER_HI_P05C3_FIELD _MK_FIELD_CONST(0x1, DC_B_WINC_BD_H_FILTER_HI_P05_0_BD_H_FILTER_HI_P05C3_SHIFT) +#define DC_B_WINC_BD_H_FILTER_HI_P05_0_BD_H_FILTER_HI_P05C3_RANGE 5:5 +#define DC_B_WINC_BD_H_FILTER_HI_P05_0_BD_H_FILTER_HI_P05C3_WOFFSET 0x0 +#define DC_B_WINC_BD_H_FILTER_HI_P05_0_BD_H_FILTER_HI_P05C3_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P05_0_BD_H_FILTER_HI_P05C3_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P05_0_BD_H_FILTER_HI_P05C3_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P05_0_BD_H_FILTER_HI_P05C3_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_H_FILTER_HI_P05_0_BD_H_FILTER_HI_P05C4_SHIFT _MK_SHIFT_CONST(6) +#define DC_B_WINC_BD_H_FILTER_HI_P05_0_BD_H_FILTER_HI_P05C4_FIELD _MK_FIELD_CONST(0x3, DC_B_WINC_BD_H_FILTER_HI_P05_0_BD_H_FILTER_HI_P05C4_SHIFT) +#define DC_B_WINC_BD_H_FILTER_HI_P05_0_BD_H_FILTER_HI_P05C4_RANGE 7:6 +#define DC_B_WINC_BD_H_FILTER_HI_P05_0_BD_H_FILTER_HI_P05C4_WOFFSET 0x0 +#define DC_B_WINC_BD_H_FILTER_HI_P05_0_BD_H_FILTER_HI_P05C4_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P05_0_BD_H_FILTER_HI_P05C4_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P05_0_BD_H_FILTER_HI_P05C4_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P05_0_BD_H_FILTER_HI_P05C4_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_H_FILTER_HI_P05_0_BD_H_FILTER_HI_P05C5_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_H_FILTER_HI_P05_0_BD_H_FILTER_HI_P05C5_FIELD _MK_FIELD_CONST(0x3, DC_B_WINC_BD_H_FILTER_HI_P05_0_BD_H_FILTER_HI_P05C5_SHIFT) +#define DC_B_WINC_BD_H_FILTER_HI_P05_0_BD_H_FILTER_HI_P05C5_RANGE 9:8 +#define DC_B_WINC_BD_H_FILTER_HI_P05_0_BD_H_FILTER_HI_P05C5_WOFFSET 0x0 +#define DC_B_WINC_BD_H_FILTER_HI_P05_0_BD_H_FILTER_HI_P05C5_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P05_0_BD_H_FILTER_HI_P05C5_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P05_0_BD_H_FILTER_HI_P05C5_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P05_0_BD_H_FILTER_HI_P05C5_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_B_WINC_BD_H_FILTER_HI_P06_0 +#define DC_B_WINC_BD_H_FILTER_HI_P06_0 _MK_ADDR_CONST(0xd2f) +#define DC_B_WINC_BD_H_FILTER_HI_P06_0_SECURE 0x0 +#define DC_B_WINC_BD_H_FILTER_HI_P06_0_WORD_COUNT 0x1 +#define DC_B_WINC_BD_H_FILTER_HI_P06_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P06_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P06_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P06_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P06_0_READ_MASK _MK_MASK_CONST(0x3ff) +#define DC_B_WINC_BD_H_FILTER_HI_P06_0_WRITE_MASK _MK_MASK_CONST(0x3ff) +#define DC_B_WINC_BD_H_FILTER_HI_P06_0_BD_H_FILTER_HI_P06C0_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_H_FILTER_HI_P06_0_BD_H_FILTER_HI_P06C0_FIELD _MK_FIELD_CONST(0x3, DC_B_WINC_BD_H_FILTER_HI_P06_0_BD_H_FILTER_HI_P06C0_SHIFT) +#define DC_B_WINC_BD_H_FILTER_HI_P06_0_BD_H_FILTER_HI_P06C0_RANGE 1:0 +#define DC_B_WINC_BD_H_FILTER_HI_P06_0_BD_H_FILTER_HI_P06C0_WOFFSET 0x0 +#define DC_B_WINC_BD_H_FILTER_HI_P06_0_BD_H_FILTER_HI_P06C0_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P06_0_BD_H_FILTER_HI_P06C0_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P06_0_BD_H_FILTER_HI_P06C0_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P06_0_BD_H_FILTER_HI_P06C0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_H_FILTER_HI_P06_0_BD_H_FILTER_HI_P06C1_SHIFT _MK_SHIFT_CONST(2) +#define DC_B_WINC_BD_H_FILTER_HI_P06_0_BD_H_FILTER_HI_P06C1_FIELD _MK_FIELD_CONST(0x3, DC_B_WINC_BD_H_FILTER_HI_P06_0_BD_H_FILTER_HI_P06C1_SHIFT) +#define DC_B_WINC_BD_H_FILTER_HI_P06_0_BD_H_FILTER_HI_P06C1_RANGE 3:2 +#define DC_B_WINC_BD_H_FILTER_HI_P06_0_BD_H_FILTER_HI_P06C1_WOFFSET 0x0 +#define DC_B_WINC_BD_H_FILTER_HI_P06_0_BD_H_FILTER_HI_P06C1_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P06_0_BD_H_FILTER_HI_P06C1_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P06_0_BD_H_FILTER_HI_P06C1_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P06_0_BD_H_FILTER_HI_P06C1_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_H_FILTER_HI_P06_0_BD_H_FILTER_HI_P06C2_SHIFT _MK_SHIFT_CONST(4) +#define DC_B_WINC_BD_H_FILTER_HI_P06_0_BD_H_FILTER_HI_P06C2_FIELD _MK_FIELD_CONST(0x1, DC_B_WINC_BD_H_FILTER_HI_P06_0_BD_H_FILTER_HI_P06C2_SHIFT) +#define DC_B_WINC_BD_H_FILTER_HI_P06_0_BD_H_FILTER_HI_P06C2_RANGE 4:4 +#define DC_B_WINC_BD_H_FILTER_HI_P06_0_BD_H_FILTER_HI_P06C2_WOFFSET 0x0 +#define DC_B_WINC_BD_H_FILTER_HI_P06_0_BD_H_FILTER_HI_P06C2_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P06_0_BD_H_FILTER_HI_P06C2_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P06_0_BD_H_FILTER_HI_P06C2_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P06_0_BD_H_FILTER_HI_P06C2_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_H_FILTER_HI_P06_0_BD_H_FILTER_HI_P06C3_SHIFT _MK_SHIFT_CONST(5) +#define DC_B_WINC_BD_H_FILTER_HI_P06_0_BD_H_FILTER_HI_P06C3_FIELD _MK_FIELD_CONST(0x1, DC_B_WINC_BD_H_FILTER_HI_P06_0_BD_H_FILTER_HI_P06C3_SHIFT) +#define DC_B_WINC_BD_H_FILTER_HI_P06_0_BD_H_FILTER_HI_P06C3_RANGE 5:5 +#define DC_B_WINC_BD_H_FILTER_HI_P06_0_BD_H_FILTER_HI_P06C3_WOFFSET 0x0 +#define DC_B_WINC_BD_H_FILTER_HI_P06_0_BD_H_FILTER_HI_P06C3_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P06_0_BD_H_FILTER_HI_P06C3_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P06_0_BD_H_FILTER_HI_P06C3_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P06_0_BD_H_FILTER_HI_P06C3_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_H_FILTER_HI_P06_0_BD_H_FILTER_HI_P06C4_SHIFT _MK_SHIFT_CONST(6) +#define DC_B_WINC_BD_H_FILTER_HI_P06_0_BD_H_FILTER_HI_P06C4_FIELD _MK_FIELD_CONST(0x3, DC_B_WINC_BD_H_FILTER_HI_P06_0_BD_H_FILTER_HI_P06C4_SHIFT) +#define DC_B_WINC_BD_H_FILTER_HI_P06_0_BD_H_FILTER_HI_P06C4_RANGE 7:6 +#define DC_B_WINC_BD_H_FILTER_HI_P06_0_BD_H_FILTER_HI_P06C4_WOFFSET 0x0 +#define DC_B_WINC_BD_H_FILTER_HI_P06_0_BD_H_FILTER_HI_P06C4_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P06_0_BD_H_FILTER_HI_P06C4_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P06_0_BD_H_FILTER_HI_P06C4_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P06_0_BD_H_FILTER_HI_P06C4_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_H_FILTER_HI_P06_0_BD_H_FILTER_HI_P06C5_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_H_FILTER_HI_P06_0_BD_H_FILTER_HI_P06C5_FIELD _MK_FIELD_CONST(0x3, DC_B_WINC_BD_H_FILTER_HI_P06_0_BD_H_FILTER_HI_P06C5_SHIFT) +#define DC_B_WINC_BD_H_FILTER_HI_P06_0_BD_H_FILTER_HI_P06C5_RANGE 9:8 +#define DC_B_WINC_BD_H_FILTER_HI_P06_0_BD_H_FILTER_HI_P06C5_WOFFSET 0x0 +#define DC_B_WINC_BD_H_FILTER_HI_P06_0_BD_H_FILTER_HI_P06C5_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P06_0_BD_H_FILTER_HI_P06C5_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P06_0_BD_H_FILTER_HI_P06C5_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P06_0_BD_H_FILTER_HI_P06C5_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_B_WINC_BD_H_FILTER_HI_P07_0 +#define DC_B_WINC_BD_H_FILTER_HI_P07_0 _MK_ADDR_CONST(0xd30) +#define DC_B_WINC_BD_H_FILTER_HI_P07_0_SECURE 0x0 +#define DC_B_WINC_BD_H_FILTER_HI_P07_0_WORD_COUNT 0x1 +#define DC_B_WINC_BD_H_FILTER_HI_P07_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P07_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P07_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P07_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P07_0_READ_MASK _MK_MASK_CONST(0x3ff) +#define DC_B_WINC_BD_H_FILTER_HI_P07_0_WRITE_MASK _MK_MASK_CONST(0x3ff) +#define DC_B_WINC_BD_H_FILTER_HI_P07_0_BD_H_FILTER_HI_P07C0_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_H_FILTER_HI_P07_0_BD_H_FILTER_HI_P07C0_FIELD _MK_FIELD_CONST(0x3, DC_B_WINC_BD_H_FILTER_HI_P07_0_BD_H_FILTER_HI_P07C0_SHIFT) +#define DC_B_WINC_BD_H_FILTER_HI_P07_0_BD_H_FILTER_HI_P07C0_RANGE 1:0 +#define DC_B_WINC_BD_H_FILTER_HI_P07_0_BD_H_FILTER_HI_P07C0_WOFFSET 0x0 +#define DC_B_WINC_BD_H_FILTER_HI_P07_0_BD_H_FILTER_HI_P07C0_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P07_0_BD_H_FILTER_HI_P07C0_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P07_0_BD_H_FILTER_HI_P07C0_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P07_0_BD_H_FILTER_HI_P07C0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_H_FILTER_HI_P07_0_BD_H_FILTER_HI_P07C1_SHIFT _MK_SHIFT_CONST(2) +#define DC_B_WINC_BD_H_FILTER_HI_P07_0_BD_H_FILTER_HI_P07C1_FIELD _MK_FIELD_CONST(0x3, DC_B_WINC_BD_H_FILTER_HI_P07_0_BD_H_FILTER_HI_P07C1_SHIFT) +#define DC_B_WINC_BD_H_FILTER_HI_P07_0_BD_H_FILTER_HI_P07C1_RANGE 3:2 +#define DC_B_WINC_BD_H_FILTER_HI_P07_0_BD_H_FILTER_HI_P07C1_WOFFSET 0x0 +#define DC_B_WINC_BD_H_FILTER_HI_P07_0_BD_H_FILTER_HI_P07C1_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P07_0_BD_H_FILTER_HI_P07C1_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P07_0_BD_H_FILTER_HI_P07C1_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P07_0_BD_H_FILTER_HI_P07C1_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_H_FILTER_HI_P07_0_BD_H_FILTER_HI_P07C2_SHIFT _MK_SHIFT_CONST(4) +#define DC_B_WINC_BD_H_FILTER_HI_P07_0_BD_H_FILTER_HI_P07C2_FIELD _MK_FIELD_CONST(0x1, DC_B_WINC_BD_H_FILTER_HI_P07_0_BD_H_FILTER_HI_P07C2_SHIFT) +#define DC_B_WINC_BD_H_FILTER_HI_P07_0_BD_H_FILTER_HI_P07C2_RANGE 4:4 +#define DC_B_WINC_BD_H_FILTER_HI_P07_0_BD_H_FILTER_HI_P07C2_WOFFSET 0x0 +#define DC_B_WINC_BD_H_FILTER_HI_P07_0_BD_H_FILTER_HI_P07C2_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P07_0_BD_H_FILTER_HI_P07C2_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P07_0_BD_H_FILTER_HI_P07C2_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P07_0_BD_H_FILTER_HI_P07C2_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_H_FILTER_HI_P07_0_BD_H_FILTER_HI_P07C3_SHIFT _MK_SHIFT_CONST(5) +#define DC_B_WINC_BD_H_FILTER_HI_P07_0_BD_H_FILTER_HI_P07C3_FIELD _MK_FIELD_CONST(0x1, DC_B_WINC_BD_H_FILTER_HI_P07_0_BD_H_FILTER_HI_P07C3_SHIFT) +#define DC_B_WINC_BD_H_FILTER_HI_P07_0_BD_H_FILTER_HI_P07C3_RANGE 5:5 +#define DC_B_WINC_BD_H_FILTER_HI_P07_0_BD_H_FILTER_HI_P07C3_WOFFSET 0x0 +#define DC_B_WINC_BD_H_FILTER_HI_P07_0_BD_H_FILTER_HI_P07C3_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P07_0_BD_H_FILTER_HI_P07C3_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P07_0_BD_H_FILTER_HI_P07C3_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P07_0_BD_H_FILTER_HI_P07C3_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_H_FILTER_HI_P07_0_BD_H_FILTER_HI_P07C4_SHIFT _MK_SHIFT_CONST(6) +#define DC_B_WINC_BD_H_FILTER_HI_P07_0_BD_H_FILTER_HI_P07C4_FIELD _MK_FIELD_CONST(0x3, DC_B_WINC_BD_H_FILTER_HI_P07_0_BD_H_FILTER_HI_P07C4_SHIFT) +#define DC_B_WINC_BD_H_FILTER_HI_P07_0_BD_H_FILTER_HI_P07C4_RANGE 7:6 +#define DC_B_WINC_BD_H_FILTER_HI_P07_0_BD_H_FILTER_HI_P07C4_WOFFSET 0x0 +#define DC_B_WINC_BD_H_FILTER_HI_P07_0_BD_H_FILTER_HI_P07C4_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P07_0_BD_H_FILTER_HI_P07C4_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P07_0_BD_H_FILTER_HI_P07C4_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P07_0_BD_H_FILTER_HI_P07C4_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_H_FILTER_HI_P07_0_BD_H_FILTER_HI_P07C5_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_H_FILTER_HI_P07_0_BD_H_FILTER_HI_P07C5_FIELD _MK_FIELD_CONST(0x3, DC_B_WINC_BD_H_FILTER_HI_P07_0_BD_H_FILTER_HI_P07C5_SHIFT) +#define DC_B_WINC_BD_H_FILTER_HI_P07_0_BD_H_FILTER_HI_P07C5_RANGE 9:8 +#define DC_B_WINC_BD_H_FILTER_HI_P07_0_BD_H_FILTER_HI_P07C5_WOFFSET 0x0 +#define DC_B_WINC_BD_H_FILTER_HI_P07_0_BD_H_FILTER_HI_P07C5_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P07_0_BD_H_FILTER_HI_P07C5_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P07_0_BD_H_FILTER_HI_P07C5_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P07_0_BD_H_FILTER_HI_P07C5_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_B_WINC_BD_H_FILTER_HI_P08_0 +#define DC_B_WINC_BD_H_FILTER_HI_P08_0 _MK_ADDR_CONST(0xd31) +#define DC_B_WINC_BD_H_FILTER_HI_P08_0_SECURE 0x0 +#define DC_B_WINC_BD_H_FILTER_HI_P08_0_WORD_COUNT 0x1 +#define DC_B_WINC_BD_H_FILTER_HI_P08_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P08_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P08_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P08_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P08_0_READ_MASK _MK_MASK_CONST(0x3ff) +#define DC_B_WINC_BD_H_FILTER_HI_P08_0_WRITE_MASK _MK_MASK_CONST(0x3ff) +#define DC_B_WINC_BD_H_FILTER_HI_P08_0_BD_H_FILTER_HI_P08C0_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_H_FILTER_HI_P08_0_BD_H_FILTER_HI_P08C0_FIELD _MK_FIELD_CONST(0x3, DC_B_WINC_BD_H_FILTER_HI_P08_0_BD_H_FILTER_HI_P08C0_SHIFT) +#define DC_B_WINC_BD_H_FILTER_HI_P08_0_BD_H_FILTER_HI_P08C0_RANGE 1:0 +#define DC_B_WINC_BD_H_FILTER_HI_P08_0_BD_H_FILTER_HI_P08C0_WOFFSET 0x0 +#define DC_B_WINC_BD_H_FILTER_HI_P08_0_BD_H_FILTER_HI_P08C0_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P08_0_BD_H_FILTER_HI_P08C0_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P08_0_BD_H_FILTER_HI_P08C0_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P08_0_BD_H_FILTER_HI_P08C0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_H_FILTER_HI_P08_0_BD_H_FILTER_HI_P08C1_SHIFT _MK_SHIFT_CONST(2) +#define DC_B_WINC_BD_H_FILTER_HI_P08_0_BD_H_FILTER_HI_P08C1_FIELD _MK_FIELD_CONST(0x3, DC_B_WINC_BD_H_FILTER_HI_P08_0_BD_H_FILTER_HI_P08C1_SHIFT) +#define DC_B_WINC_BD_H_FILTER_HI_P08_0_BD_H_FILTER_HI_P08C1_RANGE 3:2 +#define DC_B_WINC_BD_H_FILTER_HI_P08_0_BD_H_FILTER_HI_P08C1_WOFFSET 0x0 +#define DC_B_WINC_BD_H_FILTER_HI_P08_0_BD_H_FILTER_HI_P08C1_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P08_0_BD_H_FILTER_HI_P08C1_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P08_0_BD_H_FILTER_HI_P08C1_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P08_0_BD_H_FILTER_HI_P08C1_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_H_FILTER_HI_P08_0_BD_H_FILTER_HI_P08C2_SHIFT _MK_SHIFT_CONST(4) +#define DC_B_WINC_BD_H_FILTER_HI_P08_0_BD_H_FILTER_HI_P08C2_FIELD _MK_FIELD_CONST(0x1, DC_B_WINC_BD_H_FILTER_HI_P08_0_BD_H_FILTER_HI_P08C2_SHIFT) +#define DC_B_WINC_BD_H_FILTER_HI_P08_0_BD_H_FILTER_HI_P08C2_RANGE 4:4 +#define DC_B_WINC_BD_H_FILTER_HI_P08_0_BD_H_FILTER_HI_P08C2_WOFFSET 0x0 +#define DC_B_WINC_BD_H_FILTER_HI_P08_0_BD_H_FILTER_HI_P08C2_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P08_0_BD_H_FILTER_HI_P08C2_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P08_0_BD_H_FILTER_HI_P08C2_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P08_0_BD_H_FILTER_HI_P08C2_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_H_FILTER_HI_P08_0_BD_H_FILTER_HI_P08C3_SHIFT _MK_SHIFT_CONST(5) +#define DC_B_WINC_BD_H_FILTER_HI_P08_0_BD_H_FILTER_HI_P08C3_FIELD _MK_FIELD_CONST(0x1, DC_B_WINC_BD_H_FILTER_HI_P08_0_BD_H_FILTER_HI_P08C3_SHIFT) +#define DC_B_WINC_BD_H_FILTER_HI_P08_0_BD_H_FILTER_HI_P08C3_RANGE 5:5 +#define DC_B_WINC_BD_H_FILTER_HI_P08_0_BD_H_FILTER_HI_P08C3_WOFFSET 0x0 +#define DC_B_WINC_BD_H_FILTER_HI_P08_0_BD_H_FILTER_HI_P08C3_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P08_0_BD_H_FILTER_HI_P08C3_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P08_0_BD_H_FILTER_HI_P08C3_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P08_0_BD_H_FILTER_HI_P08C3_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_H_FILTER_HI_P08_0_BD_H_FILTER_HI_P08C4_SHIFT _MK_SHIFT_CONST(6) +#define DC_B_WINC_BD_H_FILTER_HI_P08_0_BD_H_FILTER_HI_P08C4_FIELD _MK_FIELD_CONST(0x3, DC_B_WINC_BD_H_FILTER_HI_P08_0_BD_H_FILTER_HI_P08C4_SHIFT) +#define DC_B_WINC_BD_H_FILTER_HI_P08_0_BD_H_FILTER_HI_P08C4_RANGE 7:6 +#define DC_B_WINC_BD_H_FILTER_HI_P08_0_BD_H_FILTER_HI_P08C4_WOFFSET 0x0 +#define DC_B_WINC_BD_H_FILTER_HI_P08_0_BD_H_FILTER_HI_P08C4_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P08_0_BD_H_FILTER_HI_P08C4_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P08_0_BD_H_FILTER_HI_P08C4_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P08_0_BD_H_FILTER_HI_P08C4_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_H_FILTER_HI_P08_0_BD_H_FILTER_HI_P08C5_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_H_FILTER_HI_P08_0_BD_H_FILTER_HI_P08C5_FIELD _MK_FIELD_CONST(0x3, DC_B_WINC_BD_H_FILTER_HI_P08_0_BD_H_FILTER_HI_P08C5_SHIFT) +#define DC_B_WINC_BD_H_FILTER_HI_P08_0_BD_H_FILTER_HI_P08C5_RANGE 9:8 +#define DC_B_WINC_BD_H_FILTER_HI_P08_0_BD_H_FILTER_HI_P08C5_WOFFSET 0x0 +#define DC_B_WINC_BD_H_FILTER_HI_P08_0_BD_H_FILTER_HI_P08C5_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P08_0_BD_H_FILTER_HI_P08C5_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P08_0_BD_H_FILTER_HI_P08C5_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P08_0_BD_H_FILTER_HI_P08C5_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_B_WINC_BD_H_FILTER_HI_P09_0 +#define DC_B_WINC_BD_H_FILTER_HI_P09_0 _MK_ADDR_CONST(0xd32) +#define DC_B_WINC_BD_H_FILTER_HI_P09_0_SECURE 0x0 +#define DC_B_WINC_BD_H_FILTER_HI_P09_0_WORD_COUNT 0x1 +#define DC_B_WINC_BD_H_FILTER_HI_P09_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P09_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P09_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P09_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P09_0_READ_MASK _MK_MASK_CONST(0x3ff) +#define DC_B_WINC_BD_H_FILTER_HI_P09_0_WRITE_MASK _MK_MASK_CONST(0x3ff) +#define DC_B_WINC_BD_H_FILTER_HI_P09_0_BD_H_FILTER_HI_P09C0_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_H_FILTER_HI_P09_0_BD_H_FILTER_HI_P09C0_FIELD _MK_FIELD_CONST(0x3, DC_B_WINC_BD_H_FILTER_HI_P09_0_BD_H_FILTER_HI_P09C0_SHIFT) +#define DC_B_WINC_BD_H_FILTER_HI_P09_0_BD_H_FILTER_HI_P09C0_RANGE 1:0 +#define DC_B_WINC_BD_H_FILTER_HI_P09_0_BD_H_FILTER_HI_P09C0_WOFFSET 0x0 +#define DC_B_WINC_BD_H_FILTER_HI_P09_0_BD_H_FILTER_HI_P09C0_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P09_0_BD_H_FILTER_HI_P09C0_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P09_0_BD_H_FILTER_HI_P09C0_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P09_0_BD_H_FILTER_HI_P09C0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_H_FILTER_HI_P09_0_BD_H_FILTER_HI_P09C1_SHIFT _MK_SHIFT_CONST(2) +#define DC_B_WINC_BD_H_FILTER_HI_P09_0_BD_H_FILTER_HI_P09C1_FIELD _MK_FIELD_CONST(0x3, DC_B_WINC_BD_H_FILTER_HI_P09_0_BD_H_FILTER_HI_P09C1_SHIFT) +#define DC_B_WINC_BD_H_FILTER_HI_P09_0_BD_H_FILTER_HI_P09C1_RANGE 3:2 +#define DC_B_WINC_BD_H_FILTER_HI_P09_0_BD_H_FILTER_HI_P09C1_WOFFSET 0x0 +#define DC_B_WINC_BD_H_FILTER_HI_P09_0_BD_H_FILTER_HI_P09C1_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P09_0_BD_H_FILTER_HI_P09C1_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P09_0_BD_H_FILTER_HI_P09C1_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P09_0_BD_H_FILTER_HI_P09C1_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_H_FILTER_HI_P09_0_BD_H_FILTER_HI_P09C2_SHIFT _MK_SHIFT_CONST(4) +#define DC_B_WINC_BD_H_FILTER_HI_P09_0_BD_H_FILTER_HI_P09C2_FIELD _MK_FIELD_CONST(0x1, DC_B_WINC_BD_H_FILTER_HI_P09_0_BD_H_FILTER_HI_P09C2_SHIFT) +#define DC_B_WINC_BD_H_FILTER_HI_P09_0_BD_H_FILTER_HI_P09C2_RANGE 4:4 +#define DC_B_WINC_BD_H_FILTER_HI_P09_0_BD_H_FILTER_HI_P09C2_WOFFSET 0x0 +#define DC_B_WINC_BD_H_FILTER_HI_P09_0_BD_H_FILTER_HI_P09C2_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P09_0_BD_H_FILTER_HI_P09C2_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P09_0_BD_H_FILTER_HI_P09C2_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P09_0_BD_H_FILTER_HI_P09C2_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_H_FILTER_HI_P09_0_BD_H_FILTER_HI_P09C3_SHIFT _MK_SHIFT_CONST(5) +#define DC_B_WINC_BD_H_FILTER_HI_P09_0_BD_H_FILTER_HI_P09C3_FIELD _MK_FIELD_CONST(0x1, DC_B_WINC_BD_H_FILTER_HI_P09_0_BD_H_FILTER_HI_P09C3_SHIFT) +#define DC_B_WINC_BD_H_FILTER_HI_P09_0_BD_H_FILTER_HI_P09C3_RANGE 5:5 +#define DC_B_WINC_BD_H_FILTER_HI_P09_0_BD_H_FILTER_HI_P09C3_WOFFSET 0x0 +#define DC_B_WINC_BD_H_FILTER_HI_P09_0_BD_H_FILTER_HI_P09C3_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P09_0_BD_H_FILTER_HI_P09C3_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P09_0_BD_H_FILTER_HI_P09C3_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P09_0_BD_H_FILTER_HI_P09C3_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_H_FILTER_HI_P09_0_BD_H_FILTER_HI_P09C4_SHIFT _MK_SHIFT_CONST(6) +#define DC_B_WINC_BD_H_FILTER_HI_P09_0_BD_H_FILTER_HI_P09C4_FIELD _MK_FIELD_CONST(0x3, DC_B_WINC_BD_H_FILTER_HI_P09_0_BD_H_FILTER_HI_P09C4_SHIFT) +#define DC_B_WINC_BD_H_FILTER_HI_P09_0_BD_H_FILTER_HI_P09C4_RANGE 7:6 +#define DC_B_WINC_BD_H_FILTER_HI_P09_0_BD_H_FILTER_HI_P09C4_WOFFSET 0x0 +#define DC_B_WINC_BD_H_FILTER_HI_P09_0_BD_H_FILTER_HI_P09C4_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P09_0_BD_H_FILTER_HI_P09C4_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P09_0_BD_H_FILTER_HI_P09C4_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P09_0_BD_H_FILTER_HI_P09C4_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_H_FILTER_HI_P09_0_BD_H_FILTER_HI_P09C5_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_H_FILTER_HI_P09_0_BD_H_FILTER_HI_P09C5_FIELD _MK_FIELD_CONST(0x3, DC_B_WINC_BD_H_FILTER_HI_P09_0_BD_H_FILTER_HI_P09C5_SHIFT) +#define DC_B_WINC_BD_H_FILTER_HI_P09_0_BD_H_FILTER_HI_P09C5_RANGE 9:8 +#define DC_B_WINC_BD_H_FILTER_HI_P09_0_BD_H_FILTER_HI_P09C5_WOFFSET 0x0 +#define DC_B_WINC_BD_H_FILTER_HI_P09_0_BD_H_FILTER_HI_P09C5_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P09_0_BD_H_FILTER_HI_P09C5_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P09_0_BD_H_FILTER_HI_P09C5_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P09_0_BD_H_FILTER_HI_P09C5_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_B_WINC_BD_H_FILTER_HI_P0A_0 +#define DC_B_WINC_BD_H_FILTER_HI_P0A_0 _MK_ADDR_CONST(0xd33) +#define DC_B_WINC_BD_H_FILTER_HI_P0A_0_SECURE 0x0 +#define DC_B_WINC_BD_H_FILTER_HI_P0A_0_WORD_COUNT 0x1 +#define DC_B_WINC_BD_H_FILTER_HI_P0A_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P0A_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P0A_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P0A_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P0A_0_READ_MASK _MK_MASK_CONST(0x3ff) +#define DC_B_WINC_BD_H_FILTER_HI_P0A_0_WRITE_MASK _MK_MASK_CONST(0x3ff) +#define DC_B_WINC_BD_H_FILTER_HI_P0A_0_BD_H_FILTER_HI_P0AC0_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_H_FILTER_HI_P0A_0_BD_H_FILTER_HI_P0AC0_FIELD _MK_FIELD_CONST(0x3, DC_B_WINC_BD_H_FILTER_HI_P0A_0_BD_H_FILTER_HI_P0AC0_SHIFT) +#define DC_B_WINC_BD_H_FILTER_HI_P0A_0_BD_H_FILTER_HI_P0AC0_RANGE 1:0 +#define DC_B_WINC_BD_H_FILTER_HI_P0A_0_BD_H_FILTER_HI_P0AC0_WOFFSET 0x0 +#define DC_B_WINC_BD_H_FILTER_HI_P0A_0_BD_H_FILTER_HI_P0AC0_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P0A_0_BD_H_FILTER_HI_P0AC0_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P0A_0_BD_H_FILTER_HI_P0AC0_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P0A_0_BD_H_FILTER_HI_P0AC0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_H_FILTER_HI_P0A_0_BD_H_FILTER_HI_P0AC1_SHIFT _MK_SHIFT_CONST(2) +#define DC_B_WINC_BD_H_FILTER_HI_P0A_0_BD_H_FILTER_HI_P0AC1_FIELD _MK_FIELD_CONST(0x3, DC_B_WINC_BD_H_FILTER_HI_P0A_0_BD_H_FILTER_HI_P0AC1_SHIFT) +#define DC_B_WINC_BD_H_FILTER_HI_P0A_0_BD_H_FILTER_HI_P0AC1_RANGE 3:2 +#define DC_B_WINC_BD_H_FILTER_HI_P0A_0_BD_H_FILTER_HI_P0AC1_WOFFSET 0x0 +#define DC_B_WINC_BD_H_FILTER_HI_P0A_0_BD_H_FILTER_HI_P0AC1_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P0A_0_BD_H_FILTER_HI_P0AC1_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P0A_0_BD_H_FILTER_HI_P0AC1_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P0A_0_BD_H_FILTER_HI_P0AC1_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_H_FILTER_HI_P0A_0_BD_H_FILTER_HI_P0AC2_SHIFT _MK_SHIFT_CONST(4) +#define DC_B_WINC_BD_H_FILTER_HI_P0A_0_BD_H_FILTER_HI_P0AC2_FIELD _MK_FIELD_CONST(0x1, DC_B_WINC_BD_H_FILTER_HI_P0A_0_BD_H_FILTER_HI_P0AC2_SHIFT) +#define DC_B_WINC_BD_H_FILTER_HI_P0A_0_BD_H_FILTER_HI_P0AC2_RANGE 4:4 +#define DC_B_WINC_BD_H_FILTER_HI_P0A_0_BD_H_FILTER_HI_P0AC2_WOFFSET 0x0 +#define DC_B_WINC_BD_H_FILTER_HI_P0A_0_BD_H_FILTER_HI_P0AC2_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P0A_0_BD_H_FILTER_HI_P0AC2_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P0A_0_BD_H_FILTER_HI_P0AC2_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P0A_0_BD_H_FILTER_HI_P0AC2_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_H_FILTER_HI_P0A_0_BD_H_FILTER_HI_P0AC3_SHIFT _MK_SHIFT_CONST(5) +#define DC_B_WINC_BD_H_FILTER_HI_P0A_0_BD_H_FILTER_HI_P0AC3_FIELD _MK_FIELD_CONST(0x1, DC_B_WINC_BD_H_FILTER_HI_P0A_0_BD_H_FILTER_HI_P0AC3_SHIFT) +#define DC_B_WINC_BD_H_FILTER_HI_P0A_0_BD_H_FILTER_HI_P0AC3_RANGE 5:5 +#define DC_B_WINC_BD_H_FILTER_HI_P0A_0_BD_H_FILTER_HI_P0AC3_WOFFSET 0x0 +#define DC_B_WINC_BD_H_FILTER_HI_P0A_0_BD_H_FILTER_HI_P0AC3_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P0A_0_BD_H_FILTER_HI_P0AC3_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P0A_0_BD_H_FILTER_HI_P0AC3_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P0A_0_BD_H_FILTER_HI_P0AC3_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_H_FILTER_HI_P0A_0_BD_H_FILTER_HI_P0AC4_SHIFT _MK_SHIFT_CONST(6) +#define DC_B_WINC_BD_H_FILTER_HI_P0A_0_BD_H_FILTER_HI_P0AC4_FIELD _MK_FIELD_CONST(0x3, DC_B_WINC_BD_H_FILTER_HI_P0A_0_BD_H_FILTER_HI_P0AC4_SHIFT) +#define DC_B_WINC_BD_H_FILTER_HI_P0A_0_BD_H_FILTER_HI_P0AC4_RANGE 7:6 +#define DC_B_WINC_BD_H_FILTER_HI_P0A_0_BD_H_FILTER_HI_P0AC4_WOFFSET 0x0 +#define DC_B_WINC_BD_H_FILTER_HI_P0A_0_BD_H_FILTER_HI_P0AC4_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P0A_0_BD_H_FILTER_HI_P0AC4_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P0A_0_BD_H_FILTER_HI_P0AC4_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P0A_0_BD_H_FILTER_HI_P0AC4_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_H_FILTER_HI_P0A_0_BD_H_FILTER_HI_P0AC5_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_H_FILTER_HI_P0A_0_BD_H_FILTER_HI_P0AC5_FIELD _MK_FIELD_CONST(0x3, DC_B_WINC_BD_H_FILTER_HI_P0A_0_BD_H_FILTER_HI_P0AC5_SHIFT) +#define DC_B_WINC_BD_H_FILTER_HI_P0A_0_BD_H_FILTER_HI_P0AC5_RANGE 9:8 +#define DC_B_WINC_BD_H_FILTER_HI_P0A_0_BD_H_FILTER_HI_P0AC5_WOFFSET 0x0 +#define DC_B_WINC_BD_H_FILTER_HI_P0A_0_BD_H_FILTER_HI_P0AC5_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P0A_0_BD_H_FILTER_HI_P0AC5_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P0A_0_BD_H_FILTER_HI_P0AC5_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P0A_0_BD_H_FILTER_HI_P0AC5_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_B_WINC_BD_H_FILTER_HI_P0B_0 +#define DC_B_WINC_BD_H_FILTER_HI_P0B_0 _MK_ADDR_CONST(0xd34) +#define DC_B_WINC_BD_H_FILTER_HI_P0B_0_SECURE 0x0 +#define DC_B_WINC_BD_H_FILTER_HI_P0B_0_WORD_COUNT 0x1 +#define DC_B_WINC_BD_H_FILTER_HI_P0B_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P0B_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P0B_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P0B_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P0B_0_READ_MASK _MK_MASK_CONST(0x3ff) +#define DC_B_WINC_BD_H_FILTER_HI_P0B_0_WRITE_MASK _MK_MASK_CONST(0x3ff) +#define DC_B_WINC_BD_H_FILTER_HI_P0B_0_BD_H_FILTER_HI_P0BC0_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_H_FILTER_HI_P0B_0_BD_H_FILTER_HI_P0BC0_FIELD _MK_FIELD_CONST(0x3, DC_B_WINC_BD_H_FILTER_HI_P0B_0_BD_H_FILTER_HI_P0BC0_SHIFT) +#define DC_B_WINC_BD_H_FILTER_HI_P0B_0_BD_H_FILTER_HI_P0BC0_RANGE 1:0 +#define DC_B_WINC_BD_H_FILTER_HI_P0B_0_BD_H_FILTER_HI_P0BC0_WOFFSET 0x0 +#define DC_B_WINC_BD_H_FILTER_HI_P0B_0_BD_H_FILTER_HI_P0BC0_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P0B_0_BD_H_FILTER_HI_P0BC0_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P0B_0_BD_H_FILTER_HI_P0BC0_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P0B_0_BD_H_FILTER_HI_P0BC0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_H_FILTER_HI_P0B_0_BD_H_FILTER_HI_P0BC1_SHIFT _MK_SHIFT_CONST(2) +#define DC_B_WINC_BD_H_FILTER_HI_P0B_0_BD_H_FILTER_HI_P0BC1_FIELD _MK_FIELD_CONST(0x3, DC_B_WINC_BD_H_FILTER_HI_P0B_0_BD_H_FILTER_HI_P0BC1_SHIFT) +#define DC_B_WINC_BD_H_FILTER_HI_P0B_0_BD_H_FILTER_HI_P0BC1_RANGE 3:2 +#define DC_B_WINC_BD_H_FILTER_HI_P0B_0_BD_H_FILTER_HI_P0BC1_WOFFSET 0x0 +#define DC_B_WINC_BD_H_FILTER_HI_P0B_0_BD_H_FILTER_HI_P0BC1_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P0B_0_BD_H_FILTER_HI_P0BC1_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P0B_0_BD_H_FILTER_HI_P0BC1_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P0B_0_BD_H_FILTER_HI_P0BC1_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_H_FILTER_HI_P0B_0_BD_H_FILTER_HI_P0BC2_SHIFT _MK_SHIFT_CONST(4) +#define DC_B_WINC_BD_H_FILTER_HI_P0B_0_BD_H_FILTER_HI_P0BC2_FIELD _MK_FIELD_CONST(0x1, DC_B_WINC_BD_H_FILTER_HI_P0B_0_BD_H_FILTER_HI_P0BC2_SHIFT) +#define DC_B_WINC_BD_H_FILTER_HI_P0B_0_BD_H_FILTER_HI_P0BC2_RANGE 4:4 +#define DC_B_WINC_BD_H_FILTER_HI_P0B_0_BD_H_FILTER_HI_P0BC2_WOFFSET 0x0 +#define DC_B_WINC_BD_H_FILTER_HI_P0B_0_BD_H_FILTER_HI_P0BC2_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P0B_0_BD_H_FILTER_HI_P0BC2_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P0B_0_BD_H_FILTER_HI_P0BC2_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P0B_0_BD_H_FILTER_HI_P0BC2_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_H_FILTER_HI_P0B_0_BD_H_FILTER_HI_P0BC3_SHIFT _MK_SHIFT_CONST(5) +#define DC_B_WINC_BD_H_FILTER_HI_P0B_0_BD_H_FILTER_HI_P0BC3_FIELD _MK_FIELD_CONST(0x1, DC_B_WINC_BD_H_FILTER_HI_P0B_0_BD_H_FILTER_HI_P0BC3_SHIFT) +#define DC_B_WINC_BD_H_FILTER_HI_P0B_0_BD_H_FILTER_HI_P0BC3_RANGE 5:5 +#define DC_B_WINC_BD_H_FILTER_HI_P0B_0_BD_H_FILTER_HI_P0BC3_WOFFSET 0x0 +#define DC_B_WINC_BD_H_FILTER_HI_P0B_0_BD_H_FILTER_HI_P0BC3_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P0B_0_BD_H_FILTER_HI_P0BC3_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P0B_0_BD_H_FILTER_HI_P0BC3_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P0B_0_BD_H_FILTER_HI_P0BC3_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_H_FILTER_HI_P0B_0_BD_H_FILTER_HI_P0BC4_SHIFT _MK_SHIFT_CONST(6) +#define DC_B_WINC_BD_H_FILTER_HI_P0B_0_BD_H_FILTER_HI_P0BC4_FIELD _MK_FIELD_CONST(0x3, DC_B_WINC_BD_H_FILTER_HI_P0B_0_BD_H_FILTER_HI_P0BC4_SHIFT) +#define DC_B_WINC_BD_H_FILTER_HI_P0B_0_BD_H_FILTER_HI_P0BC4_RANGE 7:6 +#define DC_B_WINC_BD_H_FILTER_HI_P0B_0_BD_H_FILTER_HI_P0BC4_WOFFSET 0x0 +#define DC_B_WINC_BD_H_FILTER_HI_P0B_0_BD_H_FILTER_HI_P0BC4_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P0B_0_BD_H_FILTER_HI_P0BC4_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P0B_0_BD_H_FILTER_HI_P0BC4_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P0B_0_BD_H_FILTER_HI_P0BC4_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_H_FILTER_HI_P0B_0_BD_H_FILTER_HI_P0BC5_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_H_FILTER_HI_P0B_0_BD_H_FILTER_HI_P0BC5_FIELD _MK_FIELD_CONST(0x3, DC_B_WINC_BD_H_FILTER_HI_P0B_0_BD_H_FILTER_HI_P0BC5_SHIFT) +#define DC_B_WINC_BD_H_FILTER_HI_P0B_0_BD_H_FILTER_HI_P0BC5_RANGE 9:8 +#define DC_B_WINC_BD_H_FILTER_HI_P0B_0_BD_H_FILTER_HI_P0BC5_WOFFSET 0x0 +#define DC_B_WINC_BD_H_FILTER_HI_P0B_0_BD_H_FILTER_HI_P0BC5_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P0B_0_BD_H_FILTER_HI_P0BC5_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P0B_0_BD_H_FILTER_HI_P0BC5_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P0B_0_BD_H_FILTER_HI_P0BC5_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_B_WINC_BD_H_FILTER_HI_P0C_0 +#define DC_B_WINC_BD_H_FILTER_HI_P0C_0 _MK_ADDR_CONST(0xd35) +#define DC_B_WINC_BD_H_FILTER_HI_P0C_0_SECURE 0x0 +#define DC_B_WINC_BD_H_FILTER_HI_P0C_0_WORD_COUNT 0x1 +#define DC_B_WINC_BD_H_FILTER_HI_P0C_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P0C_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P0C_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P0C_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P0C_0_READ_MASK _MK_MASK_CONST(0x3ff) +#define DC_B_WINC_BD_H_FILTER_HI_P0C_0_WRITE_MASK _MK_MASK_CONST(0x3ff) +#define DC_B_WINC_BD_H_FILTER_HI_P0C_0_BD_H_FILTER_HI_P0CC0_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_H_FILTER_HI_P0C_0_BD_H_FILTER_HI_P0CC0_FIELD _MK_FIELD_CONST(0x3, DC_B_WINC_BD_H_FILTER_HI_P0C_0_BD_H_FILTER_HI_P0CC0_SHIFT) +#define DC_B_WINC_BD_H_FILTER_HI_P0C_0_BD_H_FILTER_HI_P0CC0_RANGE 1:0 +#define DC_B_WINC_BD_H_FILTER_HI_P0C_0_BD_H_FILTER_HI_P0CC0_WOFFSET 0x0 +#define DC_B_WINC_BD_H_FILTER_HI_P0C_0_BD_H_FILTER_HI_P0CC0_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P0C_0_BD_H_FILTER_HI_P0CC0_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P0C_0_BD_H_FILTER_HI_P0CC0_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P0C_0_BD_H_FILTER_HI_P0CC0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_H_FILTER_HI_P0C_0_BD_H_FILTER_HI_P0CC1_SHIFT _MK_SHIFT_CONST(2) +#define DC_B_WINC_BD_H_FILTER_HI_P0C_0_BD_H_FILTER_HI_P0CC1_FIELD _MK_FIELD_CONST(0x3, DC_B_WINC_BD_H_FILTER_HI_P0C_0_BD_H_FILTER_HI_P0CC1_SHIFT) +#define DC_B_WINC_BD_H_FILTER_HI_P0C_0_BD_H_FILTER_HI_P0CC1_RANGE 3:2 +#define DC_B_WINC_BD_H_FILTER_HI_P0C_0_BD_H_FILTER_HI_P0CC1_WOFFSET 0x0 +#define DC_B_WINC_BD_H_FILTER_HI_P0C_0_BD_H_FILTER_HI_P0CC1_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P0C_0_BD_H_FILTER_HI_P0CC1_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P0C_0_BD_H_FILTER_HI_P0CC1_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P0C_0_BD_H_FILTER_HI_P0CC1_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_H_FILTER_HI_P0C_0_BD_H_FILTER_HI_P0CC2_SHIFT _MK_SHIFT_CONST(4) +#define DC_B_WINC_BD_H_FILTER_HI_P0C_0_BD_H_FILTER_HI_P0CC2_FIELD _MK_FIELD_CONST(0x1, DC_B_WINC_BD_H_FILTER_HI_P0C_0_BD_H_FILTER_HI_P0CC2_SHIFT) +#define DC_B_WINC_BD_H_FILTER_HI_P0C_0_BD_H_FILTER_HI_P0CC2_RANGE 4:4 +#define DC_B_WINC_BD_H_FILTER_HI_P0C_0_BD_H_FILTER_HI_P0CC2_WOFFSET 0x0 +#define DC_B_WINC_BD_H_FILTER_HI_P0C_0_BD_H_FILTER_HI_P0CC2_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P0C_0_BD_H_FILTER_HI_P0CC2_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P0C_0_BD_H_FILTER_HI_P0CC2_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P0C_0_BD_H_FILTER_HI_P0CC2_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_H_FILTER_HI_P0C_0_BD_H_FILTER_HI_P0CC3_SHIFT _MK_SHIFT_CONST(5) +#define DC_B_WINC_BD_H_FILTER_HI_P0C_0_BD_H_FILTER_HI_P0CC3_FIELD _MK_FIELD_CONST(0x1, DC_B_WINC_BD_H_FILTER_HI_P0C_0_BD_H_FILTER_HI_P0CC3_SHIFT) +#define DC_B_WINC_BD_H_FILTER_HI_P0C_0_BD_H_FILTER_HI_P0CC3_RANGE 5:5 +#define DC_B_WINC_BD_H_FILTER_HI_P0C_0_BD_H_FILTER_HI_P0CC3_WOFFSET 0x0 +#define DC_B_WINC_BD_H_FILTER_HI_P0C_0_BD_H_FILTER_HI_P0CC3_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P0C_0_BD_H_FILTER_HI_P0CC3_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P0C_0_BD_H_FILTER_HI_P0CC3_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P0C_0_BD_H_FILTER_HI_P0CC3_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_H_FILTER_HI_P0C_0_BD_H_FILTER_HI_P0CC4_SHIFT _MK_SHIFT_CONST(6) +#define DC_B_WINC_BD_H_FILTER_HI_P0C_0_BD_H_FILTER_HI_P0CC4_FIELD _MK_FIELD_CONST(0x3, DC_B_WINC_BD_H_FILTER_HI_P0C_0_BD_H_FILTER_HI_P0CC4_SHIFT) +#define DC_B_WINC_BD_H_FILTER_HI_P0C_0_BD_H_FILTER_HI_P0CC4_RANGE 7:6 +#define DC_B_WINC_BD_H_FILTER_HI_P0C_0_BD_H_FILTER_HI_P0CC4_WOFFSET 0x0 +#define DC_B_WINC_BD_H_FILTER_HI_P0C_0_BD_H_FILTER_HI_P0CC4_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P0C_0_BD_H_FILTER_HI_P0CC4_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P0C_0_BD_H_FILTER_HI_P0CC4_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P0C_0_BD_H_FILTER_HI_P0CC4_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_H_FILTER_HI_P0C_0_BD_H_FILTER_HI_P0CC5_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_H_FILTER_HI_P0C_0_BD_H_FILTER_HI_P0CC5_FIELD _MK_FIELD_CONST(0x3, DC_B_WINC_BD_H_FILTER_HI_P0C_0_BD_H_FILTER_HI_P0CC5_SHIFT) +#define DC_B_WINC_BD_H_FILTER_HI_P0C_0_BD_H_FILTER_HI_P0CC5_RANGE 9:8 +#define DC_B_WINC_BD_H_FILTER_HI_P0C_0_BD_H_FILTER_HI_P0CC5_WOFFSET 0x0 +#define DC_B_WINC_BD_H_FILTER_HI_P0C_0_BD_H_FILTER_HI_P0CC5_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P0C_0_BD_H_FILTER_HI_P0CC5_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P0C_0_BD_H_FILTER_HI_P0CC5_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P0C_0_BD_H_FILTER_HI_P0CC5_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_B_WINC_BD_H_FILTER_HI_P0D_0 +#define DC_B_WINC_BD_H_FILTER_HI_P0D_0 _MK_ADDR_CONST(0xd36) +#define DC_B_WINC_BD_H_FILTER_HI_P0D_0_SECURE 0x0 +#define DC_B_WINC_BD_H_FILTER_HI_P0D_0_WORD_COUNT 0x1 +#define DC_B_WINC_BD_H_FILTER_HI_P0D_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P0D_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P0D_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P0D_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P0D_0_READ_MASK _MK_MASK_CONST(0x3ff) +#define DC_B_WINC_BD_H_FILTER_HI_P0D_0_WRITE_MASK _MK_MASK_CONST(0x3ff) +#define DC_B_WINC_BD_H_FILTER_HI_P0D_0_BD_H_FILTER_HI_P0DC0_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_H_FILTER_HI_P0D_0_BD_H_FILTER_HI_P0DC0_FIELD _MK_FIELD_CONST(0x3, DC_B_WINC_BD_H_FILTER_HI_P0D_0_BD_H_FILTER_HI_P0DC0_SHIFT) +#define DC_B_WINC_BD_H_FILTER_HI_P0D_0_BD_H_FILTER_HI_P0DC0_RANGE 1:0 +#define DC_B_WINC_BD_H_FILTER_HI_P0D_0_BD_H_FILTER_HI_P0DC0_WOFFSET 0x0 +#define DC_B_WINC_BD_H_FILTER_HI_P0D_0_BD_H_FILTER_HI_P0DC0_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P0D_0_BD_H_FILTER_HI_P0DC0_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P0D_0_BD_H_FILTER_HI_P0DC0_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P0D_0_BD_H_FILTER_HI_P0DC0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_H_FILTER_HI_P0D_0_BD_H_FILTER_HI_P0DC1_SHIFT _MK_SHIFT_CONST(2) +#define DC_B_WINC_BD_H_FILTER_HI_P0D_0_BD_H_FILTER_HI_P0DC1_FIELD _MK_FIELD_CONST(0x3, DC_B_WINC_BD_H_FILTER_HI_P0D_0_BD_H_FILTER_HI_P0DC1_SHIFT) +#define DC_B_WINC_BD_H_FILTER_HI_P0D_0_BD_H_FILTER_HI_P0DC1_RANGE 3:2 +#define DC_B_WINC_BD_H_FILTER_HI_P0D_0_BD_H_FILTER_HI_P0DC1_WOFFSET 0x0 +#define DC_B_WINC_BD_H_FILTER_HI_P0D_0_BD_H_FILTER_HI_P0DC1_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P0D_0_BD_H_FILTER_HI_P0DC1_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P0D_0_BD_H_FILTER_HI_P0DC1_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P0D_0_BD_H_FILTER_HI_P0DC1_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_H_FILTER_HI_P0D_0_BD_H_FILTER_HI_P0DC2_SHIFT _MK_SHIFT_CONST(4) +#define DC_B_WINC_BD_H_FILTER_HI_P0D_0_BD_H_FILTER_HI_P0DC2_FIELD _MK_FIELD_CONST(0x1, DC_B_WINC_BD_H_FILTER_HI_P0D_0_BD_H_FILTER_HI_P0DC2_SHIFT) +#define DC_B_WINC_BD_H_FILTER_HI_P0D_0_BD_H_FILTER_HI_P0DC2_RANGE 4:4 +#define DC_B_WINC_BD_H_FILTER_HI_P0D_0_BD_H_FILTER_HI_P0DC2_WOFFSET 0x0 +#define DC_B_WINC_BD_H_FILTER_HI_P0D_0_BD_H_FILTER_HI_P0DC2_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P0D_0_BD_H_FILTER_HI_P0DC2_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P0D_0_BD_H_FILTER_HI_P0DC2_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P0D_0_BD_H_FILTER_HI_P0DC2_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_H_FILTER_HI_P0D_0_BD_H_FILTER_HI_P0DC3_SHIFT _MK_SHIFT_CONST(5) +#define DC_B_WINC_BD_H_FILTER_HI_P0D_0_BD_H_FILTER_HI_P0DC3_FIELD _MK_FIELD_CONST(0x1, DC_B_WINC_BD_H_FILTER_HI_P0D_0_BD_H_FILTER_HI_P0DC3_SHIFT) +#define DC_B_WINC_BD_H_FILTER_HI_P0D_0_BD_H_FILTER_HI_P0DC3_RANGE 5:5 +#define DC_B_WINC_BD_H_FILTER_HI_P0D_0_BD_H_FILTER_HI_P0DC3_WOFFSET 0x0 +#define DC_B_WINC_BD_H_FILTER_HI_P0D_0_BD_H_FILTER_HI_P0DC3_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P0D_0_BD_H_FILTER_HI_P0DC3_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P0D_0_BD_H_FILTER_HI_P0DC3_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P0D_0_BD_H_FILTER_HI_P0DC3_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_H_FILTER_HI_P0D_0_BD_H_FILTER_HI_P0DC4_SHIFT _MK_SHIFT_CONST(6) +#define DC_B_WINC_BD_H_FILTER_HI_P0D_0_BD_H_FILTER_HI_P0DC4_FIELD _MK_FIELD_CONST(0x3, DC_B_WINC_BD_H_FILTER_HI_P0D_0_BD_H_FILTER_HI_P0DC4_SHIFT) +#define DC_B_WINC_BD_H_FILTER_HI_P0D_0_BD_H_FILTER_HI_P0DC4_RANGE 7:6 +#define DC_B_WINC_BD_H_FILTER_HI_P0D_0_BD_H_FILTER_HI_P0DC4_WOFFSET 0x0 +#define DC_B_WINC_BD_H_FILTER_HI_P0D_0_BD_H_FILTER_HI_P0DC4_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P0D_0_BD_H_FILTER_HI_P0DC4_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P0D_0_BD_H_FILTER_HI_P0DC4_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P0D_0_BD_H_FILTER_HI_P0DC4_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_H_FILTER_HI_P0D_0_BD_H_FILTER_HI_P0DC5_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_H_FILTER_HI_P0D_0_BD_H_FILTER_HI_P0DC5_FIELD _MK_FIELD_CONST(0x3, DC_B_WINC_BD_H_FILTER_HI_P0D_0_BD_H_FILTER_HI_P0DC5_SHIFT) +#define DC_B_WINC_BD_H_FILTER_HI_P0D_0_BD_H_FILTER_HI_P0DC5_RANGE 9:8 +#define DC_B_WINC_BD_H_FILTER_HI_P0D_0_BD_H_FILTER_HI_P0DC5_WOFFSET 0x0 +#define DC_B_WINC_BD_H_FILTER_HI_P0D_0_BD_H_FILTER_HI_P0DC5_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P0D_0_BD_H_FILTER_HI_P0DC5_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P0D_0_BD_H_FILTER_HI_P0DC5_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P0D_0_BD_H_FILTER_HI_P0DC5_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_B_WINC_BD_H_FILTER_HI_P0E_0 +#define DC_B_WINC_BD_H_FILTER_HI_P0E_0 _MK_ADDR_CONST(0xd37) +#define DC_B_WINC_BD_H_FILTER_HI_P0E_0_SECURE 0x0 +#define DC_B_WINC_BD_H_FILTER_HI_P0E_0_WORD_COUNT 0x1 +#define DC_B_WINC_BD_H_FILTER_HI_P0E_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P0E_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P0E_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P0E_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P0E_0_READ_MASK _MK_MASK_CONST(0x3ff) +#define DC_B_WINC_BD_H_FILTER_HI_P0E_0_WRITE_MASK _MK_MASK_CONST(0x3ff) +#define DC_B_WINC_BD_H_FILTER_HI_P0E_0_BD_H_FILTER_HI_P0EC0_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_H_FILTER_HI_P0E_0_BD_H_FILTER_HI_P0EC0_FIELD _MK_FIELD_CONST(0x3, DC_B_WINC_BD_H_FILTER_HI_P0E_0_BD_H_FILTER_HI_P0EC0_SHIFT) +#define DC_B_WINC_BD_H_FILTER_HI_P0E_0_BD_H_FILTER_HI_P0EC0_RANGE 1:0 +#define DC_B_WINC_BD_H_FILTER_HI_P0E_0_BD_H_FILTER_HI_P0EC0_WOFFSET 0x0 +#define DC_B_WINC_BD_H_FILTER_HI_P0E_0_BD_H_FILTER_HI_P0EC0_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P0E_0_BD_H_FILTER_HI_P0EC0_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P0E_0_BD_H_FILTER_HI_P0EC0_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P0E_0_BD_H_FILTER_HI_P0EC0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_H_FILTER_HI_P0E_0_BD_H_FILTER_HI_P0EC1_SHIFT _MK_SHIFT_CONST(2) +#define DC_B_WINC_BD_H_FILTER_HI_P0E_0_BD_H_FILTER_HI_P0EC1_FIELD _MK_FIELD_CONST(0x3, DC_B_WINC_BD_H_FILTER_HI_P0E_0_BD_H_FILTER_HI_P0EC1_SHIFT) +#define DC_B_WINC_BD_H_FILTER_HI_P0E_0_BD_H_FILTER_HI_P0EC1_RANGE 3:2 +#define DC_B_WINC_BD_H_FILTER_HI_P0E_0_BD_H_FILTER_HI_P0EC1_WOFFSET 0x0 +#define DC_B_WINC_BD_H_FILTER_HI_P0E_0_BD_H_FILTER_HI_P0EC1_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P0E_0_BD_H_FILTER_HI_P0EC1_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P0E_0_BD_H_FILTER_HI_P0EC1_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P0E_0_BD_H_FILTER_HI_P0EC1_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_H_FILTER_HI_P0E_0_BD_H_FILTER_HI_P0EC2_SHIFT _MK_SHIFT_CONST(4) +#define DC_B_WINC_BD_H_FILTER_HI_P0E_0_BD_H_FILTER_HI_P0EC2_FIELD _MK_FIELD_CONST(0x1, DC_B_WINC_BD_H_FILTER_HI_P0E_0_BD_H_FILTER_HI_P0EC2_SHIFT) +#define DC_B_WINC_BD_H_FILTER_HI_P0E_0_BD_H_FILTER_HI_P0EC2_RANGE 4:4 +#define DC_B_WINC_BD_H_FILTER_HI_P0E_0_BD_H_FILTER_HI_P0EC2_WOFFSET 0x0 +#define DC_B_WINC_BD_H_FILTER_HI_P0E_0_BD_H_FILTER_HI_P0EC2_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P0E_0_BD_H_FILTER_HI_P0EC2_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P0E_0_BD_H_FILTER_HI_P0EC2_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P0E_0_BD_H_FILTER_HI_P0EC2_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_H_FILTER_HI_P0E_0_BD_H_FILTER_HI_P0EC3_SHIFT _MK_SHIFT_CONST(5) +#define DC_B_WINC_BD_H_FILTER_HI_P0E_0_BD_H_FILTER_HI_P0EC3_FIELD _MK_FIELD_CONST(0x1, DC_B_WINC_BD_H_FILTER_HI_P0E_0_BD_H_FILTER_HI_P0EC3_SHIFT) +#define DC_B_WINC_BD_H_FILTER_HI_P0E_0_BD_H_FILTER_HI_P0EC3_RANGE 5:5 +#define DC_B_WINC_BD_H_FILTER_HI_P0E_0_BD_H_FILTER_HI_P0EC3_WOFFSET 0x0 +#define DC_B_WINC_BD_H_FILTER_HI_P0E_0_BD_H_FILTER_HI_P0EC3_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P0E_0_BD_H_FILTER_HI_P0EC3_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P0E_0_BD_H_FILTER_HI_P0EC3_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P0E_0_BD_H_FILTER_HI_P0EC3_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_H_FILTER_HI_P0E_0_BD_H_FILTER_HI_P0EC4_SHIFT _MK_SHIFT_CONST(6) +#define DC_B_WINC_BD_H_FILTER_HI_P0E_0_BD_H_FILTER_HI_P0EC4_FIELD _MK_FIELD_CONST(0x3, DC_B_WINC_BD_H_FILTER_HI_P0E_0_BD_H_FILTER_HI_P0EC4_SHIFT) +#define DC_B_WINC_BD_H_FILTER_HI_P0E_0_BD_H_FILTER_HI_P0EC4_RANGE 7:6 +#define DC_B_WINC_BD_H_FILTER_HI_P0E_0_BD_H_FILTER_HI_P0EC4_WOFFSET 0x0 +#define DC_B_WINC_BD_H_FILTER_HI_P0E_0_BD_H_FILTER_HI_P0EC4_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P0E_0_BD_H_FILTER_HI_P0EC4_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P0E_0_BD_H_FILTER_HI_P0EC4_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P0E_0_BD_H_FILTER_HI_P0EC4_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_H_FILTER_HI_P0E_0_BD_H_FILTER_HI_P0EC5_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_H_FILTER_HI_P0E_0_BD_H_FILTER_HI_P0EC5_FIELD _MK_FIELD_CONST(0x3, DC_B_WINC_BD_H_FILTER_HI_P0E_0_BD_H_FILTER_HI_P0EC5_SHIFT) +#define DC_B_WINC_BD_H_FILTER_HI_P0E_0_BD_H_FILTER_HI_P0EC5_RANGE 9:8 +#define DC_B_WINC_BD_H_FILTER_HI_P0E_0_BD_H_FILTER_HI_P0EC5_WOFFSET 0x0 +#define DC_B_WINC_BD_H_FILTER_HI_P0E_0_BD_H_FILTER_HI_P0EC5_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P0E_0_BD_H_FILTER_HI_P0EC5_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P0E_0_BD_H_FILTER_HI_P0EC5_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P0E_0_BD_H_FILTER_HI_P0EC5_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_B_WINC_BD_H_FILTER_HI_P0F_0 +#define DC_B_WINC_BD_H_FILTER_HI_P0F_0 _MK_ADDR_CONST(0xd38) +#define DC_B_WINC_BD_H_FILTER_HI_P0F_0_SECURE 0x0 +#define DC_B_WINC_BD_H_FILTER_HI_P0F_0_WORD_COUNT 0x1 +#define DC_B_WINC_BD_H_FILTER_HI_P0F_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P0F_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P0F_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P0F_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P0F_0_READ_MASK _MK_MASK_CONST(0x3ff) +#define DC_B_WINC_BD_H_FILTER_HI_P0F_0_WRITE_MASK _MK_MASK_CONST(0x3ff) +#define DC_B_WINC_BD_H_FILTER_HI_P0F_0_BD_H_FILTER_HI_P0FC0_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINC_BD_H_FILTER_HI_P0F_0_BD_H_FILTER_HI_P0FC0_FIELD _MK_FIELD_CONST(0x3, DC_B_WINC_BD_H_FILTER_HI_P0F_0_BD_H_FILTER_HI_P0FC0_SHIFT) +#define DC_B_WINC_BD_H_FILTER_HI_P0F_0_BD_H_FILTER_HI_P0FC0_RANGE 1:0 +#define DC_B_WINC_BD_H_FILTER_HI_P0F_0_BD_H_FILTER_HI_P0FC0_WOFFSET 0x0 +#define DC_B_WINC_BD_H_FILTER_HI_P0F_0_BD_H_FILTER_HI_P0FC0_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P0F_0_BD_H_FILTER_HI_P0FC0_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P0F_0_BD_H_FILTER_HI_P0FC0_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P0F_0_BD_H_FILTER_HI_P0FC0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_H_FILTER_HI_P0F_0_BD_H_FILTER_HI_P0FC1_SHIFT _MK_SHIFT_CONST(2) +#define DC_B_WINC_BD_H_FILTER_HI_P0F_0_BD_H_FILTER_HI_P0FC1_FIELD _MK_FIELD_CONST(0x3, DC_B_WINC_BD_H_FILTER_HI_P0F_0_BD_H_FILTER_HI_P0FC1_SHIFT) +#define DC_B_WINC_BD_H_FILTER_HI_P0F_0_BD_H_FILTER_HI_P0FC1_RANGE 3:2 +#define DC_B_WINC_BD_H_FILTER_HI_P0F_0_BD_H_FILTER_HI_P0FC1_WOFFSET 0x0 +#define DC_B_WINC_BD_H_FILTER_HI_P0F_0_BD_H_FILTER_HI_P0FC1_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P0F_0_BD_H_FILTER_HI_P0FC1_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P0F_0_BD_H_FILTER_HI_P0FC1_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P0F_0_BD_H_FILTER_HI_P0FC1_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_H_FILTER_HI_P0F_0_BD_H_FILTER_HI_P0FC2_SHIFT _MK_SHIFT_CONST(4) +#define DC_B_WINC_BD_H_FILTER_HI_P0F_0_BD_H_FILTER_HI_P0FC2_FIELD _MK_FIELD_CONST(0x1, DC_B_WINC_BD_H_FILTER_HI_P0F_0_BD_H_FILTER_HI_P0FC2_SHIFT) +#define DC_B_WINC_BD_H_FILTER_HI_P0F_0_BD_H_FILTER_HI_P0FC2_RANGE 4:4 +#define DC_B_WINC_BD_H_FILTER_HI_P0F_0_BD_H_FILTER_HI_P0FC2_WOFFSET 0x0 +#define DC_B_WINC_BD_H_FILTER_HI_P0F_0_BD_H_FILTER_HI_P0FC2_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P0F_0_BD_H_FILTER_HI_P0FC2_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P0F_0_BD_H_FILTER_HI_P0FC2_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P0F_0_BD_H_FILTER_HI_P0FC2_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_H_FILTER_HI_P0F_0_BD_H_FILTER_HI_P0FC3_SHIFT _MK_SHIFT_CONST(5) +#define DC_B_WINC_BD_H_FILTER_HI_P0F_0_BD_H_FILTER_HI_P0FC3_FIELD _MK_FIELD_CONST(0x1, DC_B_WINC_BD_H_FILTER_HI_P0F_0_BD_H_FILTER_HI_P0FC3_SHIFT) +#define DC_B_WINC_BD_H_FILTER_HI_P0F_0_BD_H_FILTER_HI_P0FC3_RANGE 5:5 +#define DC_B_WINC_BD_H_FILTER_HI_P0F_0_BD_H_FILTER_HI_P0FC3_WOFFSET 0x0 +#define DC_B_WINC_BD_H_FILTER_HI_P0F_0_BD_H_FILTER_HI_P0FC3_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P0F_0_BD_H_FILTER_HI_P0FC3_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P0F_0_BD_H_FILTER_HI_P0FC3_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P0F_0_BD_H_FILTER_HI_P0FC3_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_H_FILTER_HI_P0F_0_BD_H_FILTER_HI_P0FC4_SHIFT _MK_SHIFT_CONST(6) +#define DC_B_WINC_BD_H_FILTER_HI_P0F_0_BD_H_FILTER_HI_P0FC4_FIELD _MK_FIELD_CONST(0x3, DC_B_WINC_BD_H_FILTER_HI_P0F_0_BD_H_FILTER_HI_P0FC4_SHIFT) +#define DC_B_WINC_BD_H_FILTER_HI_P0F_0_BD_H_FILTER_HI_P0FC4_RANGE 7:6 +#define DC_B_WINC_BD_H_FILTER_HI_P0F_0_BD_H_FILTER_HI_P0FC4_WOFFSET 0x0 +#define DC_B_WINC_BD_H_FILTER_HI_P0F_0_BD_H_FILTER_HI_P0FC4_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P0F_0_BD_H_FILTER_HI_P0FC4_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P0F_0_BD_H_FILTER_HI_P0FC4_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P0F_0_BD_H_FILTER_HI_P0FC4_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINC_BD_H_FILTER_HI_P0F_0_BD_H_FILTER_HI_P0FC5_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINC_BD_H_FILTER_HI_P0F_0_BD_H_FILTER_HI_P0FC5_FIELD _MK_FIELD_CONST(0x3, DC_B_WINC_BD_H_FILTER_HI_P0F_0_BD_H_FILTER_HI_P0FC5_SHIFT) +#define DC_B_WINC_BD_H_FILTER_HI_P0F_0_BD_H_FILTER_HI_P0FC5_RANGE 9:8 +#define DC_B_WINC_BD_H_FILTER_HI_P0F_0_BD_H_FILTER_HI_P0FC5_WOFFSET 0x0 +#define DC_B_WINC_BD_H_FILTER_HI_P0F_0_BD_H_FILTER_HI_P0FC5_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P0F_0_BD_H_FILTER_HI_P0FC5_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P0F_0_BD_H_FILTER_HI_P0FC5_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINC_BD_H_FILTER_HI_P0F_0_BD_H_FILTER_HI_P0FC5_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_B_WIN_BD_WIN_OPTIONS_0 +#define DC_B_WIN_BD_WIN_OPTIONS_0 _MK_ADDR_CONST(0xd80) +#define DC_B_WIN_BD_WIN_OPTIONS_0_SECURE 0x0 +#define DC_B_WIN_BD_WIN_OPTIONS_0_WORD_COUNT 0x1 +#define DC_B_WIN_BD_WIN_OPTIONS_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WIN_BD_WIN_OPTIONS_0_RESET_MASK _MK_MASK_CONST(0xc0814010) +#define DC_B_WIN_BD_WIN_OPTIONS_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WIN_BD_WIN_OPTIONS_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WIN_BD_WIN_OPTIONS_0_READ_MASK _MK_MASK_CONST(0xc0d55555) +#define DC_B_WIN_BD_WIN_OPTIONS_0_WRITE_MASK _MK_MASK_CONST(0xc0d55555) +#define DC_B_WIN_BD_WIN_OPTIONS_0_BD_H_DIRECTION_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WIN_BD_WIN_OPTIONS_0_BD_H_DIRECTION_FIELD _MK_FIELD_CONST(0x1, DC_B_WIN_BD_WIN_OPTIONS_0_BD_H_DIRECTION_SHIFT) +#define DC_B_WIN_BD_WIN_OPTIONS_0_BD_H_DIRECTION_RANGE 0:0 +#define DC_B_WIN_BD_WIN_OPTIONS_0_BD_H_DIRECTION_WOFFSET 0x0 +#define DC_B_WIN_BD_WIN_OPTIONS_0_BD_H_DIRECTION_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WIN_BD_WIN_OPTIONS_0_BD_H_DIRECTION_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WIN_BD_WIN_OPTIONS_0_BD_H_DIRECTION_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WIN_BD_WIN_OPTIONS_0_BD_H_DIRECTION_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WIN_BD_WIN_OPTIONS_0_BD_H_DIRECTION_INCREMENT _MK_ENUM_CONST(0) +#define DC_B_WIN_BD_WIN_OPTIONS_0_BD_H_DIRECTION_DECREMENT _MK_ENUM_CONST(1) + +#define DC_B_WIN_BD_WIN_OPTIONS_0_BD_V_DIRECTION_SHIFT _MK_SHIFT_CONST(2) +#define DC_B_WIN_BD_WIN_OPTIONS_0_BD_V_DIRECTION_FIELD _MK_FIELD_CONST(0x1, DC_B_WIN_BD_WIN_OPTIONS_0_BD_V_DIRECTION_SHIFT) +#define DC_B_WIN_BD_WIN_OPTIONS_0_BD_V_DIRECTION_RANGE 2:2 +#define DC_B_WIN_BD_WIN_OPTIONS_0_BD_V_DIRECTION_WOFFSET 0x0 +#define DC_B_WIN_BD_WIN_OPTIONS_0_BD_V_DIRECTION_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WIN_BD_WIN_OPTIONS_0_BD_V_DIRECTION_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WIN_BD_WIN_OPTIONS_0_BD_V_DIRECTION_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WIN_BD_WIN_OPTIONS_0_BD_V_DIRECTION_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WIN_BD_WIN_OPTIONS_0_BD_V_DIRECTION_INCREMENT _MK_ENUM_CONST(0) +#define DC_B_WIN_BD_WIN_OPTIONS_0_BD_V_DIRECTION_DECREMENT _MK_ENUM_CONST(1) + +#define DC_B_WIN_BD_WIN_OPTIONS_0_BD_SCAN_COLUMN_SHIFT _MK_SHIFT_CONST(4) +#define DC_B_WIN_BD_WIN_OPTIONS_0_BD_SCAN_COLUMN_FIELD _MK_FIELD_CONST(0x1, DC_B_WIN_BD_WIN_OPTIONS_0_BD_SCAN_COLUMN_SHIFT) +#define DC_B_WIN_BD_WIN_OPTIONS_0_BD_SCAN_COLUMN_RANGE 4:4 +#define DC_B_WIN_BD_WIN_OPTIONS_0_BD_SCAN_COLUMN_WOFFSET 0x0 +#define DC_B_WIN_BD_WIN_OPTIONS_0_BD_SCAN_COLUMN_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WIN_BD_WIN_OPTIONS_0_BD_SCAN_COLUMN_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_B_WIN_BD_WIN_OPTIONS_0_BD_SCAN_COLUMN_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WIN_BD_WIN_OPTIONS_0_BD_SCAN_COLUMN_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WIN_BD_WIN_OPTIONS_0_BD_SCAN_COLUMN_DISABLE _MK_ENUM_CONST(0) +#define DC_B_WIN_BD_WIN_OPTIONS_0_BD_SCAN_COLUMN_ENABLE _MK_ENUM_CONST(1) + +#define DC_B_WIN_BD_WIN_OPTIONS_0_BD_COLOR_EXPAND_SHIFT _MK_SHIFT_CONST(6) +#define DC_B_WIN_BD_WIN_OPTIONS_0_BD_COLOR_EXPAND_FIELD _MK_FIELD_CONST(0x1, DC_B_WIN_BD_WIN_OPTIONS_0_BD_COLOR_EXPAND_SHIFT) +#define DC_B_WIN_BD_WIN_OPTIONS_0_BD_COLOR_EXPAND_RANGE 6:6 +#define DC_B_WIN_BD_WIN_OPTIONS_0_BD_COLOR_EXPAND_WOFFSET 0x0 +#define DC_B_WIN_BD_WIN_OPTIONS_0_BD_COLOR_EXPAND_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WIN_BD_WIN_OPTIONS_0_BD_COLOR_EXPAND_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WIN_BD_WIN_OPTIONS_0_BD_COLOR_EXPAND_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WIN_BD_WIN_OPTIONS_0_BD_COLOR_EXPAND_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WIN_BD_WIN_OPTIONS_0_BD_COLOR_EXPAND_DISABLE _MK_ENUM_CONST(0) +#define DC_B_WIN_BD_WIN_OPTIONS_0_BD_COLOR_EXPAND_ENABLE _MK_ENUM_CONST(1) + +#define DC_B_WIN_BD_WIN_OPTIONS_0_BD_H_FILTER_ENABLE_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WIN_BD_WIN_OPTIONS_0_BD_H_FILTER_ENABLE_FIELD _MK_FIELD_CONST(0x1, DC_B_WIN_BD_WIN_OPTIONS_0_BD_H_FILTER_ENABLE_SHIFT) +#define DC_B_WIN_BD_WIN_OPTIONS_0_BD_H_FILTER_ENABLE_RANGE 8:8 +#define DC_B_WIN_BD_WIN_OPTIONS_0_BD_H_FILTER_ENABLE_WOFFSET 0x0 +#define DC_B_WIN_BD_WIN_OPTIONS_0_BD_H_FILTER_ENABLE_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WIN_BD_WIN_OPTIONS_0_BD_H_FILTER_ENABLE_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WIN_BD_WIN_OPTIONS_0_BD_H_FILTER_ENABLE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WIN_BD_WIN_OPTIONS_0_BD_H_FILTER_ENABLE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WIN_BD_WIN_OPTIONS_0_BD_H_FILTER_ENABLE_DISABLE _MK_ENUM_CONST(0) +#define DC_B_WIN_BD_WIN_OPTIONS_0_BD_H_FILTER_ENABLE_ENABLE _MK_ENUM_CONST(1) + +#define DC_B_WIN_BD_WIN_OPTIONS_0_BD_V_FILTER_ENABLE_SHIFT _MK_SHIFT_CONST(10) +#define DC_B_WIN_BD_WIN_OPTIONS_0_BD_V_FILTER_ENABLE_FIELD _MK_FIELD_CONST(0x1, DC_B_WIN_BD_WIN_OPTIONS_0_BD_V_FILTER_ENABLE_SHIFT) +#define DC_B_WIN_BD_WIN_OPTIONS_0_BD_V_FILTER_ENABLE_RANGE 10:10 +#define DC_B_WIN_BD_WIN_OPTIONS_0_BD_V_FILTER_ENABLE_WOFFSET 0x0 +#define DC_B_WIN_BD_WIN_OPTIONS_0_BD_V_FILTER_ENABLE_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WIN_BD_WIN_OPTIONS_0_BD_V_FILTER_ENABLE_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WIN_BD_WIN_OPTIONS_0_BD_V_FILTER_ENABLE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WIN_BD_WIN_OPTIONS_0_BD_V_FILTER_ENABLE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WIN_BD_WIN_OPTIONS_0_BD_V_FILTER_ENABLE_DISABLE _MK_ENUM_CONST(0) +#define DC_B_WIN_BD_WIN_OPTIONS_0_BD_V_FILTER_ENABLE_ENABLE _MK_ENUM_CONST(1) + +#define DC_B_WIN_BD_WIN_OPTIONS_0_BD_V_FILTER_OPTIMIZE_SHIFT _MK_SHIFT_CONST(12) +#define DC_B_WIN_BD_WIN_OPTIONS_0_BD_V_FILTER_OPTIMIZE_FIELD _MK_FIELD_CONST(0x1, DC_B_WIN_BD_WIN_OPTIONS_0_BD_V_FILTER_OPTIMIZE_SHIFT) +#define DC_B_WIN_BD_WIN_OPTIONS_0_BD_V_FILTER_OPTIMIZE_RANGE 12:12 +#define DC_B_WIN_BD_WIN_OPTIONS_0_BD_V_FILTER_OPTIMIZE_WOFFSET 0x0 +#define DC_B_WIN_BD_WIN_OPTIONS_0_BD_V_FILTER_OPTIMIZE_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WIN_BD_WIN_OPTIONS_0_BD_V_FILTER_OPTIMIZE_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WIN_BD_WIN_OPTIONS_0_BD_V_FILTER_OPTIMIZE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WIN_BD_WIN_OPTIONS_0_BD_V_FILTER_OPTIMIZE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WIN_BD_WIN_OPTIONS_0_BD_V_FILTER_OPTIMIZE_DISABLE _MK_ENUM_CONST(0) +#define DC_B_WIN_BD_WIN_OPTIONS_0_BD_V_FILTER_OPTIMIZE_ENABLE _MK_ENUM_CONST(1) + +#define DC_B_WIN_BD_WIN_OPTIONS_0_BD_V_FILTER_UV_ALIGN_SHIFT _MK_SHIFT_CONST(14) +#define DC_B_WIN_BD_WIN_OPTIONS_0_BD_V_FILTER_UV_ALIGN_FIELD _MK_FIELD_CONST(0x1, DC_B_WIN_BD_WIN_OPTIONS_0_BD_V_FILTER_UV_ALIGN_SHIFT) +#define DC_B_WIN_BD_WIN_OPTIONS_0_BD_V_FILTER_UV_ALIGN_RANGE 14:14 +#define DC_B_WIN_BD_WIN_OPTIONS_0_BD_V_FILTER_UV_ALIGN_WOFFSET 0x0 +#define DC_B_WIN_BD_WIN_OPTIONS_0_BD_V_FILTER_UV_ALIGN_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WIN_BD_WIN_OPTIONS_0_BD_V_FILTER_UV_ALIGN_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_B_WIN_BD_WIN_OPTIONS_0_BD_V_FILTER_UV_ALIGN_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WIN_BD_WIN_OPTIONS_0_BD_V_FILTER_UV_ALIGN_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WIN_BD_WIN_OPTIONS_0_BD_V_FILTER_UV_ALIGN_DISABLE _MK_ENUM_CONST(0) +#define DC_B_WIN_BD_WIN_OPTIONS_0_BD_V_FILTER_UV_ALIGN_ENABLE _MK_ENUM_CONST(1) + +#define DC_B_WIN_BD_WIN_OPTIONS_0_BD_CP_ENABLE_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WIN_BD_WIN_OPTIONS_0_BD_CP_ENABLE_FIELD _MK_FIELD_CONST(0x1, DC_B_WIN_BD_WIN_OPTIONS_0_BD_CP_ENABLE_SHIFT) +#define DC_B_WIN_BD_WIN_OPTIONS_0_BD_CP_ENABLE_RANGE 16:16 +#define DC_B_WIN_BD_WIN_OPTIONS_0_BD_CP_ENABLE_WOFFSET 0x0 +#define DC_B_WIN_BD_WIN_OPTIONS_0_BD_CP_ENABLE_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WIN_BD_WIN_OPTIONS_0_BD_CP_ENABLE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_B_WIN_BD_WIN_OPTIONS_0_BD_CP_ENABLE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WIN_BD_WIN_OPTIONS_0_BD_CP_ENABLE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WIN_BD_WIN_OPTIONS_0_BD_CP_ENABLE_DISABLE _MK_ENUM_CONST(0) +#define DC_B_WIN_BD_WIN_OPTIONS_0_BD_CP_ENABLE_ENABLE _MK_ENUM_CONST(1) + +#define DC_B_WIN_BD_WIN_OPTIONS_0_BD_CSC_ENABLE_SHIFT _MK_SHIFT_CONST(18) +#define DC_B_WIN_BD_WIN_OPTIONS_0_BD_CSC_ENABLE_FIELD _MK_FIELD_CONST(0x1, DC_B_WIN_BD_WIN_OPTIONS_0_BD_CSC_ENABLE_SHIFT) +#define DC_B_WIN_BD_WIN_OPTIONS_0_BD_CSC_ENABLE_RANGE 18:18 +#define DC_B_WIN_BD_WIN_OPTIONS_0_BD_CSC_ENABLE_WOFFSET 0x0 +#define DC_B_WIN_BD_WIN_OPTIONS_0_BD_CSC_ENABLE_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WIN_BD_WIN_OPTIONS_0_BD_CSC_ENABLE_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WIN_BD_WIN_OPTIONS_0_BD_CSC_ENABLE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WIN_BD_WIN_OPTIONS_0_BD_CSC_ENABLE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WIN_BD_WIN_OPTIONS_0_BD_CSC_ENABLE_DISABLE _MK_ENUM_CONST(0) +#define DC_B_WIN_BD_WIN_OPTIONS_0_BD_CSC_ENABLE_ENABLE _MK_ENUM_CONST(1) + +#define DC_B_WIN_BD_WIN_OPTIONS_0_BD_DV_ENABLE_SHIFT _MK_SHIFT_CONST(20) +#define DC_B_WIN_BD_WIN_OPTIONS_0_BD_DV_ENABLE_FIELD _MK_FIELD_CONST(0x1, DC_B_WIN_BD_WIN_OPTIONS_0_BD_DV_ENABLE_SHIFT) +#define DC_B_WIN_BD_WIN_OPTIONS_0_BD_DV_ENABLE_RANGE 20:20 +#define DC_B_WIN_BD_WIN_OPTIONS_0_BD_DV_ENABLE_WOFFSET 0x0 +#define DC_B_WIN_BD_WIN_OPTIONS_0_BD_DV_ENABLE_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WIN_BD_WIN_OPTIONS_0_BD_DV_ENABLE_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WIN_BD_WIN_OPTIONS_0_BD_DV_ENABLE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WIN_BD_WIN_OPTIONS_0_BD_DV_ENABLE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WIN_BD_WIN_OPTIONS_0_BD_DV_ENABLE_DISABLE _MK_ENUM_CONST(0) +#define DC_B_WIN_BD_WIN_OPTIONS_0_BD_DV_ENABLE_ENABLE _MK_ENUM_CONST(1) + +#define DC_B_WIN_BD_WIN_OPTIONS_0_BD_YUV_RANGE_EXPAND_SHIFT _MK_SHIFT_CONST(22) +#define DC_B_WIN_BD_WIN_OPTIONS_0_BD_YUV_RANGE_EXPAND_FIELD _MK_FIELD_CONST(0x1, DC_B_WIN_BD_WIN_OPTIONS_0_BD_YUV_RANGE_EXPAND_SHIFT) +#define DC_B_WIN_BD_WIN_OPTIONS_0_BD_YUV_RANGE_EXPAND_RANGE 22:22 +#define DC_B_WIN_BD_WIN_OPTIONS_0_BD_YUV_RANGE_EXPAND_WOFFSET 0x0 +#define DC_B_WIN_BD_WIN_OPTIONS_0_BD_YUV_RANGE_EXPAND_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WIN_BD_WIN_OPTIONS_0_BD_YUV_RANGE_EXPAND_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WIN_BD_WIN_OPTIONS_0_BD_YUV_RANGE_EXPAND_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WIN_BD_WIN_OPTIONS_0_BD_YUV_RANGE_EXPAND_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WIN_BD_WIN_OPTIONS_0_BD_YUV_RANGE_EXPAND_DISABLE _MK_ENUM_CONST(0) +#define DC_B_WIN_BD_WIN_OPTIONS_0_BD_YUV_RANGE_EXPAND_ENABLE _MK_ENUM_CONST(1) + +#define DC_B_WIN_BD_WIN_OPTIONS_0_BD_INTERLACE_ENABLE_SHIFT _MK_SHIFT_CONST(23) +#define DC_B_WIN_BD_WIN_OPTIONS_0_BD_INTERLACE_ENABLE_FIELD _MK_FIELD_CONST(0x1, DC_B_WIN_BD_WIN_OPTIONS_0_BD_INTERLACE_ENABLE_SHIFT) +#define DC_B_WIN_BD_WIN_OPTIONS_0_BD_INTERLACE_ENABLE_RANGE 23:23 +#define DC_B_WIN_BD_WIN_OPTIONS_0_BD_INTERLACE_ENABLE_WOFFSET 0x0 +#define DC_B_WIN_BD_WIN_OPTIONS_0_BD_INTERLACE_ENABLE_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WIN_BD_WIN_OPTIONS_0_BD_INTERLACE_ENABLE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_B_WIN_BD_WIN_OPTIONS_0_BD_INTERLACE_ENABLE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WIN_BD_WIN_OPTIONS_0_BD_INTERLACE_ENABLE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WIN_BD_WIN_OPTIONS_0_BD_INTERLACE_ENABLE_DISABLE _MK_ENUM_CONST(0) +#define DC_B_WIN_BD_WIN_OPTIONS_0_BD_INTERLACE_ENABLE_ENABLE _MK_ENUM_CONST(1) + +#define DC_B_WIN_BD_WIN_OPTIONS_0_BD_WIN_ENABLE_SHIFT _MK_SHIFT_CONST(30) +#define DC_B_WIN_BD_WIN_OPTIONS_0_BD_WIN_ENABLE_FIELD _MK_FIELD_CONST(0x1, DC_B_WIN_BD_WIN_OPTIONS_0_BD_WIN_ENABLE_SHIFT) +#define DC_B_WIN_BD_WIN_OPTIONS_0_BD_WIN_ENABLE_RANGE 30:30 +#define DC_B_WIN_BD_WIN_OPTIONS_0_BD_WIN_ENABLE_WOFFSET 0x0 +#define DC_B_WIN_BD_WIN_OPTIONS_0_BD_WIN_ENABLE_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WIN_BD_WIN_OPTIONS_0_BD_WIN_ENABLE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_B_WIN_BD_WIN_OPTIONS_0_BD_WIN_ENABLE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WIN_BD_WIN_OPTIONS_0_BD_WIN_ENABLE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WIN_BD_WIN_OPTIONS_0_BD_WIN_ENABLE_DISABLE _MK_ENUM_CONST(0) +#define DC_B_WIN_BD_WIN_OPTIONS_0_BD_WIN_ENABLE_ENABLE _MK_ENUM_CONST(1) + +#define DC_B_WIN_BD_WIN_OPTIONS_0_BD_H_FILTER_MODE_SHIFT _MK_SHIFT_CONST(31) +#define DC_B_WIN_BD_WIN_OPTIONS_0_BD_H_FILTER_MODE_FIELD _MK_FIELD_CONST(0x1, DC_B_WIN_BD_WIN_OPTIONS_0_BD_H_FILTER_MODE_SHIFT) +#define DC_B_WIN_BD_WIN_OPTIONS_0_BD_H_FILTER_MODE_RANGE 31:31 +#define DC_B_WIN_BD_WIN_OPTIONS_0_BD_H_FILTER_MODE_WOFFSET 0x0 +#define DC_B_WIN_BD_WIN_OPTIONS_0_BD_H_FILTER_MODE_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WIN_BD_WIN_OPTIONS_0_BD_H_FILTER_MODE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_B_WIN_BD_WIN_OPTIONS_0_BD_H_FILTER_MODE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WIN_BD_WIN_OPTIONS_0_BD_H_FILTER_MODE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WIN_BD_WIN_OPTIONS_0_BD_H_FILTER_MODE_OLD _MK_ENUM_CONST(0) +#define DC_B_WIN_BD_WIN_OPTIONS_0_BD_H_FILTER_MODE_NEW _MK_ENUM_CONST(1) + + +// Register DC_B_WIN_BD_BYTE_SWAP_0 +#define DC_B_WIN_BD_BYTE_SWAP_0 _MK_ADDR_CONST(0xd81) +#define DC_B_WIN_BD_BYTE_SWAP_0_SECURE 0x0 +#define DC_B_WIN_BD_BYTE_SWAP_0_WORD_COUNT 0x1 +#define DC_B_WIN_BD_BYTE_SWAP_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WIN_BD_BYTE_SWAP_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WIN_BD_BYTE_SWAP_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WIN_BD_BYTE_SWAP_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WIN_BD_BYTE_SWAP_0_READ_MASK _MK_MASK_CONST(0x7) +#define DC_B_WIN_BD_BYTE_SWAP_0_WRITE_MASK _MK_MASK_CONST(0x7) +#define DC_B_WIN_BD_BYTE_SWAP_0_BD_BYTE_SWAP_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WIN_BD_BYTE_SWAP_0_BD_BYTE_SWAP_FIELD _MK_FIELD_CONST(0x7, DC_B_WIN_BD_BYTE_SWAP_0_BD_BYTE_SWAP_SHIFT) +#define DC_B_WIN_BD_BYTE_SWAP_0_BD_BYTE_SWAP_RANGE 2:0 +#define DC_B_WIN_BD_BYTE_SWAP_0_BD_BYTE_SWAP_WOFFSET 0x0 +#define DC_B_WIN_BD_BYTE_SWAP_0_BD_BYTE_SWAP_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WIN_BD_BYTE_SWAP_0_BD_BYTE_SWAP_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WIN_BD_BYTE_SWAP_0_BD_BYTE_SWAP_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WIN_BD_BYTE_SWAP_0_BD_BYTE_SWAP_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WIN_BD_BYTE_SWAP_0_BD_BYTE_SWAP_NOSWAP _MK_ENUM_CONST(0) +#define DC_B_WIN_BD_BYTE_SWAP_0_BD_BYTE_SWAP_SWAP2 _MK_ENUM_CONST(1) +#define DC_B_WIN_BD_BYTE_SWAP_0_BD_BYTE_SWAP_SWAP4 _MK_ENUM_CONST(2) +#define DC_B_WIN_BD_BYTE_SWAP_0_BD_BYTE_SWAP_SWAP4HW _MK_ENUM_CONST(3) +#define DC_B_WIN_BD_BYTE_SWAP_0_BD_BYTE_SWAP_SWAP02 _MK_ENUM_CONST(4) +#define DC_B_WIN_BD_BYTE_SWAP_0_BD_BYTE_SWAP_SWAPLEFT _MK_ENUM_CONST(5) + + +// Register DC_B_WIN_BD_BUFFER_CONTROL_0 +#define DC_B_WIN_BD_BUFFER_CONTROL_0 _MK_ADDR_CONST(0xd82) +#define DC_B_WIN_BD_BUFFER_CONTROL_0_SECURE 0x0 +#define DC_B_WIN_BD_BUFFER_CONTROL_0_WORD_COUNT 0x1 +#define DC_B_WIN_BD_BUFFER_CONTROL_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WIN_BD_BUFFER_CONTROL_0_RESET_MASK _MK_MASK_CONST(0x7) +#define DC_B_WIN_BD_BUFFER_CONTROL_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WIN_BD_BUFFER_CONTROL_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WIN_BD_BUFFER_CONTROL_0_READ_MASK _MK_MASK_CONST(0x7) +#define DC_B_WIN_BD_BUFFER_CONTROL_0_WRITE_MASK _MK_MASK_CONST(0x7) +#define DC_B_WIN_BD_BUFFER_CONTROL_0_BD_BUFFER_CONTROL_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WIN_BD_BUFFER_CONTROL_0_BD_BUFFER_CONTROL_FIELD _MK_FIELD_CONST(0x7, DC_B_WIN_BD_BUFFER_CONTROL_0_BD_BUFFER_CONTROL_SHIFT) +#define DC_B_WIN_BD_BUFFER_CONTROL_0_BD_BUFFER_CONTROL_RANGE 2:0 +#define DC_B_WIN_BD_BUFFER_CONTROL_0_BD_BUFFER_CONTROL_WOFFSET 0x0 +#define DC_B_WIN_BD_BUFFER_CONTROL_0_BD_BUFFER_CONTROL_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WIN_BD_BUFFER_CONTROL_0_BD_BUFFER_CONTROL_DEFAULT_MASK _MK_MASK_CONST(0x7) +#define DC_B_WIN_BD_BUFFER_CONTROL_0_BD_BUFFER_CONTROL_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WIN_BD_BUFFER_CONTROL_0_BD_BUFFER_CONTROL_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WIN_BD_BUFFER_CONTROL_0_BD_BUFFER_CONTROL_HOST _MK_ENUM_CONST(0) +#define DC_B_WIN_BD_BUFFER_CONTROL_0_BD_BUFFER_CONTROL_VI _MK_ENUM_CONST(1) +#define DC_B_WIN_BD_BUFFER_CONTROL_0_BD_BUFFER_CONTROL_SB2D _MK_ENUM_CONST(4) + + +// Register DC_B_WIN_BD_COLOR_DEPTH_0 +#define DC_B_WIN_BD_COLOR_DEPTH_0 _MK_ADDR_CONST(0xd83) +#define DC_B_WIN_BD_COLOR_DEPTH_0_SECURE 0x0 +#define DC_B_WIN_BD_COLOR_DEPTH_0_WORD_COUNT 0x1 +#define DC_B_WIN_BD_COLOR_DEPTH_0_RESET_VAL _MK_MASK_CONST(0xc) +#define DC_B_WIN_BD_COLOR_DEPTH_0_RESET_MASK _MK_MASK_CONST(0x7f) +#define DC_B_WIN_BD_COLOR_DEPTH_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WIN_BD_COLOR_DEPTH_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WIN_BD_COLOR_DEPTH_0_READ_MASK _MK_MASK_CONST(0x7f) +#define DC_B_WIN_BD_COLOR_DEPTH_0_WRITE_MASK _MK_MASK_CONST(0x7f) +#define DC_B_WIN_BD_COLOR_DEPTH_0_BD_COLOR_DEPTH_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WIN_BD_COLOR_DEPTH_0_BD_COLOR_DEPTH_FIELD _MK_FIELD_CONST(0x7f, DC_B_WIN_BD_COLOR_DEPTH_0_BD_COLOR_DEPTH_SHIFT) +#define DC_B_WIN_BD_COLOR_DEPTH_0_BD_COLOR_DEPTH_RANGE 6:0 +#define DC_B_WIN_BD_COLOR_DEPTH_0_BD_COLOR_DEPTH_WOFFSET 0x0 +#define DC_B_WIN_BD_COLOR_DEPTH_0_BD_COLOR_DEPTH_DEFAULT _MK_MASK_CONST(0xc) +#define DC_B_WIN_BD_COLOR_DEPTH_0_BD_COLOR_DEPTH_DEFAULT_MASK _MK_MASK_CONST(0x7f) +#define DC_B_WIN_BD_COLOR_DEPTH_0_BD_COLOR_DEPTH_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WIN_BD_COLOR_DEPTH_0_BD_COLOR_DEPTH_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WIN_BD_COLOR_DEPTH_0_BD_COLOR_DEPTH_INIT_ENUM B8G8R8A8 +#define DC_B_WIN_BD_COLOR_DEPTH_0_BD_COLOR_DEPTH_T_P8 _MK_ENUM_CONST(3) +#define DC_B_WIN_BD_COLOR_DEPTH_0_BD_COLOR_DEPTH_P8 _MK_ENUM_CONST(3) +#define DC_B_WIN_BD_COLOR_DEPTH_0_BD_COLOR_DEPTH_T_A4R4G4B4 _MK_ENUM_CONST(4) +#define DC_B_WIN_BD_COLOR_DEPTH_0_BD_COLOR_DEPTH_B4G4R4A4 _MK_ENUM_CONST(4) +#define DC_B_WIN_BD_COLOR_DEPTH_0_BD_COLOR_DEPTH_T_A1R5G5B5 _MK_ENUM_CONST(5) +#define DC_B_WIN_BD_COLOR_DEPTH_0_BD_COLOR_DEPTH_B5G5R5A _MK_ENUM_CONST(5) +#define DC_B_WIN_BD_COLOR_DEPTH_0_BD_COLOR_DEPTH_T_R5G6B5 _MK_ENUM_CONST(6) +#define DC_B_WIN_BD_COLOR_DEPTH_0_BD_COLOR_DEPTH_B5G6R5 _MK_ENUM_CONST(6) +#define DC_B_WIN_BD_COLOR_DEPTH_0_BD_COLOR_DEPTH_T_R5G5B5A1 _MK_ENUM_CONST(7) +#define DC_B_WIN_BD_COLOR_DEPTH_0_BD_COLOR_DEPTH_AB5G5R5 _MK_ENUM_CONST(7) +#define DC_B_WIN_BD_COLOR_DEPTH_0_BD_COLOR_DEPTH_T_A8R8G8B8 _MK_ENUM_CONST(12) +#define DC_B_WIN_BD_COLOR_DEPTH_0_BD_COLOR_DEPTH_B8G8R8A8 _MK_ENUM_CONST(12) +#define DC_B_WIN_BD_COLOR_DEPTH_0_BD_COLOR_DEPTH_T_A8B8G8R8 _MK_ENUM_CONST(13) +#define DC_B_WIN_BD_COLOR_DEPTH_0_BD_COLOR_DEPTH_R8G8B8A8 _MK_ENUM_CONST(13) +#define DC_B_WIN_BD_COLOR_DEPTH_0_BD_COLOR_DEPTH_T_U8_Y8__V8_Y8 _MK_ENUM_CONST(16) +#define DC_B_WIN_BD_COLOR_DEPTH_0_BD_COLOR_DEPTH_CbYCrY422 _MK_ENUM_CONST(16) +#define DC_B_WIN_BD_COLOR_DEPTH_0_BD_COLOR_DEPTH_YCbCr422 _MK_ENUM_CONST(16) +#define DC_B_WIN_BD_COLOR_DEPTH_0_BD_COLOR_DEPTH_T_U8_Y8__V8_Y8_TRUE _MK_ENUM_CONST(17) +#define DC_B_WIN_BD_COLOR_DEPTH_0_BD_COLOR_DEPTH_UYVY422 _MK_ENUM_CONST(17) +#define DC_B_WIN_BD_COLOR_DEPTH_0_BD_COLOR_DEPTH_YUV422 _MK_ENUM_CONST(17) +#define DC_B_WIN_BD_COLOR_DEPTH_0_BD_COLOR_DEPTH_T_Y8___U8___V8_N420 _MK_ENUM_CONST(18) +#define DC_B_WIN_BD_COLOR_DEPTH_0_BD_COLOR_DEPTH_YCbCr420P _MK_ENUM_CONST(18) +#define DC_B_WIN_BD_COLOR_DEPTH_0_BD_COLOR_DEPTH_T_Y8___U8___V8_N420_TRUE _MK_ENUM_CONST(19) +#define DC_B_WIN_BD_COLOR_DEPTH_0_BD_COLOR_DEPTH_YUV420P _MK_ENUM_CONST(19) +#define DC_B_WIN_BD_COLOR_DEPTH_0_BD_COLOR_DEPTH_T_Y8___U8___V8_N422 _MK_ENUM_CONST(20) +#define DC_B_WIN_BD_COLOR_DEPTH_0_BD_COLOR_DEPTH_YCbCr422P _MK_ENUM_CONST(20) +#define DC_B_WIN_BD_COLOR_DEPTH_0_BD_COLOR_DEPTH_T_Y8___U8___V8_N422_TRUE _MK_ENUM_CONST(21) +#define DC_B_WIN_BD_COLOR_DEPTH_0_BD_COLOR_DEPTH_YUV422P _MK_ENUM_CONST(21) +#define DC_B_WIN_BD_COLOR_DEPTH_0_BD_COLOR_DEPTH_T_Y8___U8___V8_N422R _MK_ENUM_CONST(22) +#define DC_B_WIN_BD_COLOR_DEPTH_0_BD_COLOR_DEPTH_YCbCr422RP _MK_ENUM_CONST(22) +#define DC_B_WIN_BD_COLOR_DEPTH_0_BD_COLOR_DEPTH_YCbCr422R _MK_ENUM_CONST(22) +#define DC_B_WIN_BD_COLOR_DEPTH_0_BD_COLOR_DEPTH_T_Y8___U8___V8_N422R_TRUE _MK_ENUM_CONST(23) +#define DC_B_WIN_BD_COLOR_DEPTH_0_BD_COLOR_DEPTH_YUV422RP _MK_ENUM_CONST(23) +#define DC_B_WIN_BD_COLOR_DEPTH_0_BD_COLOR_DEPTH_YUV422R _MK_ENUM_CONST(23) +#define DC_B_WIN_BD_COLOR_DEPTH_0_BD_COLOR_DEPTH_T_V8_Y8__U8_Y8 _MK_ENUM_CONST(24) +#define DC_B_WIN_BD_COLOR_DEPTH_0_BD_COLOR_DEPTH_CrYCbY422 _MK_ENUM_CONST(24) +#define DC_B_WIN_BD_COLOR_DEPTH_0_BD_COLOR_DEPTH_T_V8_Y8__U8_Y8_TRUE _MK_ENUM_CONST(25) +#define DC_B_WIN_BD_COLOR_DEPTH_0_BD_COLOR_DEPTH_VYUY422 _MK_ENUM_CONST(25) +#define DC_B_WIN_BD_COLOR_DEPTH_0_BD_COLOR_DEPTH_T_Y8_U8__Y8_V8 _MK_ENUM_CONST(61) +#define DC_B_WIN_BD_COLOR_DEPTH_0_BD_COLOR_DEPTH_YCbYCr422 _MK_ENUM_CONST(61) +#define DC_B_WIN_BD_COLOR_DEPTH_0_BD_COLOR_DEPTH_T_Y8_U8__Y8_V8_TRUE _MK_ENUM_CONST(62) +#define DC_B_WIN_BD_COLOR_DEPTH_0_BD_COLOR_DEPTH_YUYV422 _MK_ENUM_CONST(62) +#define DC_B_WIN_BD_COLOR_DEPTH_0_BD_COLOR_DEPTH_T_Y8_V8__Y8_U8 _MK_ENUM_CONST(63) +#define DC_B_WIN_BD_COLOR_DEPTH_0_BD_COLOR_DEPTH_YCrYCb422 _MK_ENUM_CONST(63) +#define DC_B_WIN_BD_COLOR_DEPTH_0_BD_COLOR_DEPTH_T_Y8_V8__Y8_U8_TRUE _MK_ENUM_CONST(64) +#define DC_B_WIN_BD_COLOR_DEPTH_0_BD_COLOR_DEPTH_YVYU422 _MK_ENUM_CONST(64) +#define DC_B_WIN_BD_COLOR_DEPTH_0_BD_COLOR_DEPTH_T_R8G8B8X8 _MK_ENUM_CONST(65) +#define DC_B_WIN_BD_COLOR_DEPTH_0_BD_COLOR_DEPTH_T_B8G8R8X8 _MK_ENUM_CONST(66) +#define DC_B_WIN_BD_COLOR_DEPTH_0_BD_COLOR_DEPTH_T_Y8 _MK_ENUM_CONST(26) +#define DC_B_WIN_BD_COLOR_DEPTH_0_BD_COLOR_DEPTH_Y8 _MK_ENUM_CONST(26) +#define DC_B_WIN_BD_COLOR_DEPTH_0_BD_COLOR_DEPTH_T_A4B4G4R4 _MK_ENUM_CONST(27) +#define DC_B_WIN_BD_COLOR_DEPTH_0_BD_COLOR_DEPTH_R4G4B4A4 _MK_ENUM_CONST(27) +#define DC_B_WIN_BD_COLOR_DEPTH_0_BD_COLOR_DEPTH_T_A1B5G5R5 _MK_ENUM_CONST(28) +#define DC_B_WIN_BD_COLOR_DEPTH_0_BD_COLOR_DEPTH_R5G5B5A _MK_ENUM_CONST(28) +#define DC_B_WIN_BD_COLOR_DEPTH_0_BD_COLOR_DEPTH_T_B5G5R5A1 _MK_ENUM_CONST(29) +#define DC_B_WIN_BD_COLOR_DEPTH_0_BD_COLOR_DEPTH_AR5G5B5 _MK_ENUM_CONST(29) +#define DC_B_WIN_BD_COLOR_DEPTH_0_BD_COLOR_DEPTH_T_X1R5G5B5 _MK_ENUM_CONST(30) +#define DC_B_WIN_BD_COLOR_DEPTH_0_BD_COLOR_DEPTH_B5G5R5X1 _MK_ENUM_CONST(30) +#define DC_B_WIN_BD_COLOR_DEPTH_0_BD_COLOR_DEPTH_T_R5G5B5X1 _MK_ENUM_CONST(31) +#define DC_B_WIN_BD_COLOR_DEPTH_0_BD_COLOR_DEPTH_X1B5G5R5 _MK_ENUM_CONST(31) +#define DC_B_WIN_BD_COLOR_DEPTH_0_BD_COLOR_DEPTH_T_X1B5G5R5 _MK_ENUM_CONST(32) +#define DC_B_WIN_BD_COLOR_DEPTH_0_BD_COLOR_DEPTH_R5G5B5X1 _MK_ENUM_CONST(32) +#define DC_B_WIN_BD_COLOR_DEPTH_0_BD_COLOR_DEPTH_T_B5G5R5X1 _MK_ENUM_CONST(33) +#define DC_B_WIN_BD_COLOR_DEPTH_0_BD_COLOR_DEPTH_X1R5G5B5 _MK_ENUM_CONST(33) +#define DC_B_WIN_BD_COLOR_DEPTH_0_BD_COLOR_DEPTH_T_B5G6R5 _MK_ENUM_CONST(34) +#define DC_B_WIN_BD_COLOR_DEPTH_0_BD_COLOR_DEPTH_R5G6B5 _MK_ENUM_CONST(34) +#define DC_B_WIN_BD_COLOR_DEPTH_0_BD_COLOR_DEPTH_T_B8G8R8A8 _MK_ENUM_CONST(35) +#define DC_B_WIN_BD_COLOR_DEPTH_0_BD_COLOR_DEPTH_T_R8G8B8A8 _MK_ENUM_CONST(36) +#define DC_B_WIN_BD_COLOR_DEPTH_0_BD_COLOR_DEPTH_T_X8R8G8B8 _MK_ENUM_CONST(37) +#define DC_B_WIN_BD_COLOR_DEPTH_0_BD_COLOR_DEPTH_B8G8R8X8 _MK_ENUM_CONST(37) +#define DC_B_WIN_BD_COLOR_DEPTH_0_BD_COLOR_DEPTH_T_X8B8G8R8 _MK_ENUM_CONST(38) +#define DC_B_WIN_BD_COLOR_DEPTH_0_BD_COLOR_DEPTH_R8G8B8X8 _MK_ENUM_CONST(38) +#define DC_B_WIN_BD_COLOR_DEPTH_0_BD_COLOR_DEPTH_T_A8Y8U8V8 _MK_ENUM_CONST(39) +#define DC_B_WIN_BD_COLOR_DEPTH_0_BD_COLOR_DEPTH_T_V8U8Y8A8 _MK_ENUM_CONST(40) +#define DC_B_WIN_BD_COLOR_DEPTH_0_BD_COLOR_DEPTH_T_Y8___U8___V8_N444 _MK_ENUM_CONST(41) +#define DC_B_WIN_BD_COLOR_DEPTH_0_BD_COLOR_DEPTH_YCbCr444P _MK_ENUM_CONST(41) +#define DC_B_WIN_BD_COLOR_DEPTH_0_BD_COLOR_DEPTH_T_Y8___U8V8_N420 _MK_ENUM_CONST(42) +#define DC_B_WIN_BD_COLOR_DEPTH_0_BD_COLOR_DEPTH_YCrCb420SP _MK_ENUM_CONST(42) +#define DC_B_WIN_BD_COLOR_DEPTH_0_BD_COLOR_DEPTH_T_Y8___V8U8_N420 _MK_ENUM_CONST(43) +#define DC_B_WIN_BD_COLOR_DEPTH_0_BD_COLOR_DEPTH_YCbCr420SP _MK_ENUM_CONST(43) +#define DC_B_WIN_BD_COLOR_DEPTH_0_BD_COLOR_DEPTH_T_Y8___U8V8_N422 _MK_ENUM_CONST(44) +#define DC_B_WIN_BD_COLOR_DEPTH_0_BD_COLOR_DEPTH_YCrCb422SP _MK_ENUM_CONST(44) +#define DC_B_WIN_BD_COLOR_DEPTH_0_BD_COLOR_DEPTH_T_Y8___V8U8_N422 _MK_ENUM_CONST(45) +#define DC_B_WIN_BD_COLOR_DEPTH_0_BD_COLOR_DEPTH_YCbCr422SP _MK_ENUM_CONST(45) +#define DC_B_WIN_BD_COLOR_DEPTH_0_BD_COLOR_DEPTH_T_Y8___U8V8_N422R _MK_ENUM_CONST(46) +#define DC_B_WIN_BD_COLOR_DEPTH_0_BD_COLOR_DEPTH_YCrCb422RSP _MK_ENUM_CONST(46) +#define DC_B_WIN_BD_COLOR_DEPTH_0_BD_COLOR_DEPTH_T_Y8___V8U8_N422R _MK_ENUM_CONST(47) +#define DC_B_WIN_BD_COLOR_DEPTH_0_BD_COLOR_DEPTH_YCbCr422RSP _MK_ENUM_CONST(47) +#define DC_B_WIN_BD_COLOR_DEPTH_0_BD_COLOR_DEPTH_T_Y8___U8V8_N444 _MK_ENUM_CONST(48) +#define DC_B_WIN_BD_COLOR_DEPTH_0_BD_COLOR_DEPTH_YCrCb444SP _MK_ENUM_CONST(48) +#define DC_B_WIN_BD_COLOR_DEPTH_0_BD_COLOR_DEPTH_T_Y8___V8U8_N444 _MK_ENUM_CONST(49) +#define DC_B_WIN_BD_COLOR_DEPTH_0_BD_COLOR_DEPTH_YCbCr444SP _MK_ENUM_CONST(49) +#define DC_B_WIN_BD_COLOR_DEPTH_0_BD_COLOR_DEPTH_T_A8Y8U8V8_TRUE _MK_ENUM_CONST(50) +#define DC_B_WIN_BD_COLOR_DEPTH_0_BD_COLOR_DEPTH_T_V8U8Y8A8_TRUE _MK_ENUM_CONST(51) +#define DC_B_WIN_BD_COLOR_DEPTH_0_BD_COLOR_DEPTH_T_Y8___U8___V8_N444_TRUE _MK_ENUM_CONST(52) +#define DC_B_WIN_BD_COLOR_DEPTH_0_BD_COLOR_DEPTH_YUV444P _MK_ENUM_CONST(52) +#define DC_B_WIN_BD_COLOR_DEPTH_0_BD_COLOR_DEPTH_T_Y8___U8V8_N420_TRUE _MK_ENUM_CONST(53) +#define DC_B_WIN_BD_COLOR_DEPTH_0_BD_COLOR_DEPTH_YVU420SP _MK_ENUM_CONST(53) +#define DC_B_WIN_BD_COLOR_DEPTH_0_BD_COLOR_DEPTH_T_Y8___V8U8_N420_TRUE _MK_ENUM_CONST(54) +#define DC_B_WIN_BD_COLOR_DEPTH_0_BD_COLOR_DEPTH_YUV420SP _MK_ENUM_CONST(54) +#define DC_B_WIN_BD_COLOR_DEPTH_0_BD_COLOR_DEPTH_T_Y8___U8V8_N422_TRUE _MK_ENUM_CONST(55) +#define DC_B_WIN_BD_COLOR_DEPTH_0_BD_COLOR_DEPTH_YVU422SP _MK_ENUM_CONST(55) +#define DC_B_WIN_BD_COLOR_DEPTH_0_BD_COLOR_DEPTH_T_Y8___V8U8_N422_TRUE _MK_ENUM_CONST(56) +#define DC_B_WIN_BD_COLOR_DEPTH_0_BD_COLOR_DEPTH_YUV422SP _MK_ENUM_CONST(56) +#define DC_B_WIN_BD_COLOR_DEPTH_0_BD_COLOR_DEPTH_T_Y8___U8V8_N422R_TRUE _MK_ENUM_CONST(57) +#define DC_B_WIN_BD_COLOR_DEPTH_0_BD_COLOR_DEPTH_YVU422RSP _MK_ENUM_CONST(57) +#define DC_B_WIN_BD_COLOR_DEPTH_0_BD_COLOR_DEPTH_T_Y8___V8U8_N422R_TRUE _MK_ENUM_CONST(58) +#define DC_B_WIN_BD_COLOR_DEPTH_0_BD_COLOR_DEPTH_YUV422RSP _MK_ENUM_CONST(58) +#define DC_B_WIN_BD_COLOR_DEPTH_0_BD_COLOR_DEPTH_T_Y8___U8V8_N444_TRUE _MK_ENUM_CONST(59) +#define DC_B_WIN_BD_COLOR_DEPTH_0_BD_COLOR_DEPTH_YVU444SP _MK_ENUM_CONST(59) +#define DC_B_WIN_BD_COLOR_DEPTH_0_BD_COLOR_DEPTH_T_Y8___V8U8_N444_TRUE _MK_ENUM_CONST(60) +#define DC_B_WIN_BD_COLOR_DEPTH_0_BD_COLOR_DEPTH_YUV444SP _MK_ENUM_CONST(60) + + +// Register DC_B_WIN_BD_POSITION_0 +#define DC_B_WIN_BD_POSITION_0 _MK_ADDR_CONST(0xd84) +#define DC_B_WIN_BD_POSITION_0_SECURE 0x0 +#define DC_B_WIN_BD_POSITION_0_WORD_COUNT 0x1 +#define DC_B_WIN_BD_POSITION_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WIN_BD_POSITION_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WIN_BD_POSITION_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WIN_BD_POSITION_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WIN_BD_POSITION_0_READ_MASK _MK_MASK_CONST(0x1fff1fff) +#define DC_B_WIN_BD_POSITION_0_WRITE_MASK _MK_MASK_CONST(0x1fff1fff) +#define DC_B_WIN_BD_POSITION_0_BD_H_POSITION_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WIN_BD_POSITION_0_BD_H_POSITION_FIELD _MK_FIELD_CONST(0x1fff, DC_B_WIN_BD_POSITION_0_BD_H_POSITION_SHIFT) +#define DC_B_WIN_BD_POSITION_0_BD_H_POSITION_RANGE 12:0 +#define DC_B_WIN_BD_POSITION_0_BD_H_POSITION_WOFFSET 0x0 +#define DC_B_WIN_BD_POSITION_0_BD_H_POSITION_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WIN_BD_POSITION_0_BD_H_POSITION_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WIN_BD_POSITION_0_BD_H_POSITION_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WIN_BD_POSITION_0_BD_H_POSITION_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WIN_BD_POSITION_0_BD_V_POSITION_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WIN_BD_POSITION_0_BD_V_POSITION_FIELD _MK_FIELD_CONST(0x1fff, DC_B_WIN_BD_POSITION_0_BD_V_POSITION_SHIFT) +#define DC_B_WIN_BD_POSITION_0_BD_V_POSITION_RANGE 28:16 +#define DC_B_WIN_BD_POSITION_0_BD_V_POSITION_WOFFSET 0x0 +#define DC_B_WIN_BD_POSITION_0_BD_V_POSITION_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WIN_BD_POSITION_0_BD_V_POSITION_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WIN_BD_POSITION_0_BD_V_POSITION_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WIN_BD_POSITION_0_BD_V_POSITION_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_B_WIN_BD_SIZE_0 +#define DC_B_WIN_BD_SIZE_0 _MK_ADDR_CONST(0xd85) +#define DC_B_WIN_BD_SIZE_0_SECURE 0x0 +#define DC_B_WIN_BD_SIZE_0_WORD_COUNT 0x1 +#define DC_B_WIN_BD_SIZE_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WIN_BD_SIZE_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WIN_BD_SIZE_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WIN_BD_SIZE_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WIN_BD_SIZE_0_READ_MASK _MK_MASK_CONST(0x1fff1fff) +#define DC_B_WIN_BD_SIZE_0_WRITE_MASK _MK_MASK_CONST(0x1fff1fff) +#define DC_B_WIN_BD_SIZE_0_BD_H_SIZE_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WIN_BD_SIZE_0_BD_H_SIZE_FIELD _MK_FIELD_CONST(0x1fff, DC_B_WIN_BD_SIZE_0_BD_H_SIZE_SHIFT) +#define DC_B_WIN_BD_SIZE_0_BD_H_SIZE_RANGE 12:0 +#define DC_B_WIN_BD_SIZE_0_BD_H_SIZE_WOFFSET 0x0 +#define DC_B_WIN_BD_SIZE_0_BD_H_SIZE_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WIN_BD_SIZE_0_BD_H_SIZE_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WIN_BD_SIZE_0_BD_H_SIZE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WIN_BD_SIZE_0_BD_H_SIZE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WIN_BD_SIZE_0_BD_V_SIZE_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WIN_BD_SIZE_0_BD_V_SIZE_FIELD _MK_FIELD_CONST(0x1fff, DC_B_WIN_BD_SIZE_0_BD_V_SIZE_SHIFT) +#define DC_B_WIN_BD_SIZE_0_BD_V_SIZE_RANGE 28:16 +#define DC_B_WIN_BD_SIZE_0_BD_V_SIZE_WOFFSET 0x0 +#define DC_B_WIN_BD_SIZE_0_BD_V_SIZE_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WIN_BD_SIZE_0_BD_V_SIZE_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WIN_BD_SIZE_0_BD_V_SIZE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WIN_BD_SIZE_0_BD_V_SIZE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_B_WIN_BD_PRESCALED_SIZE_0 +#define DC_B_WIN_BD_PRESCALED_SIZE_0 _MK_ADDR_CONST(0xd86) +#define DC_B_WIN_BD_PRESCALED_SIZE_0_SECURE 0x0 +#define DC_B_WIN_BD_PRESCALED_SIZE_0_WORD_COUNT 0x1 +#define DC_B_WIN_BD_PRESCALED_SIZE_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WIN_BD_PRESCALED_SIZE_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WIN_BD_PRESCALED_SIZE_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WIN_BD_PRESCALED_SIZE_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WIN_BD_PRESCALED_SIZE_0_READ_MASK _MK_MASK_CONST(0x1fff7fff) +#define DC_B_WIN_BD_PRESCALED_SIZE_0_WRITE_MASK _MK_MASK_CONST(0x1fff7fff) +#define DC_B_WIN_BD_PRESCALED_SIZE_0_BD_H_PRESCALED_SIZE_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WIN_BD_PRESCALED_SIZE_0_BD_H_PRESCALED_SIZE_FIELD _MK_FIELD_CONST(0x7fff, DC_B_WIN_BD_PRESCALED_SIZE_0_BD_H_PRESCALED_SIZE_SHIFT) +#define DC_B_WIN_BD_PRESCALED_SIZE_0_BD_H_PRESCALED_SIZE_RANGE 14:0 +#define DC_B_WIN_BD_PRESCALED_SIZE_0_BD_H_PRESCALED_SIZE_WOFFSET 0x0 +#define DC_B_WIN_BD_PRESCALED_SIZE_0_BD_H_PRESCALED_SIZE_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WIN_BD_PRESCALED_SIZE_0_BD_H_PRESCALED_SIZE_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WIN_BD_PRESCALED_SIZE_0_BD_H_PRESCALED_SIZE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WIN_BD_PRESCALED_SIZE_0_BD_H_PRESCALED_SIZE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WIN_BD_PRESCALED_SIZE_0_BD_V_PRESCALED_SIZE_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WIN_BD_PRESCALED_SIZE_0_BD_V_PRESCALED_SIZE_FIELD _MK_FIELD_CONST(0x1fff, DC_B_WIN_BD_PRESCALED_SIZE_0_BD_V_PRESCALED_SIZE_SHIFT) +#define DC_B_WIN_BD_PRESCALED_SIZE_0_BD_V_PRESCALED_SIZE_RANGE 28:16 +#define DC_B_WIN_BD_PRESCALED_SIZE_0_BD_V_PRESCALED_SIZE_WOFFSET 0x0 +#define DC_B_WIN_BD_PRESCALED_SIZE_0_BD_V_PRESCALED_SIZE_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WIN_BD_PRESCALED_SIZE_0_BD_V_PRESCALED_SIZE_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WIN_BD_PRESCALED_SIZE_0_BD_V_PRESCALED_SIZE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WIN_BD_PRESCALED_SIZE_0_BD_V_PRESCALED_SIZE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_B_WIN_BD_H_INITIAL_DDA_0 +#define DC_B_WIN_BD_H_INITIAL_DDA_0 _MK_ADDR_CONST(0xd87) +#define DC_B_WIN_BD_H_INITIAL_DDA_0_SECURE 0x0 +#define DC_B_WIN_BD_H_INITIAL_DDA_0_WORD_COUNT 0x1 +#define DC_B_WIN_BD_H_INITIAL_DDA_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WIN_BD_H_INITIAL_DDA_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WIN_BD_H_INITIAL_DDA_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WIN_BD_H_INITIAL_DDA_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WIN_BD_H_INITIAL_DDA_0_READ_MASK _MK_MASK_CONST(0xffff) +#define DC_B_WIN_BD_H_INITIAL_DDA_0_WRITE_MASK _MK_MASK_CONST(0xffff) +#define DC_B_WIN_BD_H_INITIAL_DDA_0_BD_H_INITIAL_DDA_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WIN_BD_H_INITIAL_DDA_0_BD_H_INITIAL_DDA_FIELD _MK_FIELD_CONST(0xffff, DC_B_WIN_BD_H_INITIAL_DDA_0_BD_H_INITIAL_DDA_SHIFT) +#define DC_B_WIN_BD_H_INITIAL_DDA_0_BD_H_INITIAL_DDA_RANGE 15:0 +#define DC_B_WIN_BD_H_INITIAL_DDA_0_BD_H_INITIAL_DDA_WOFFSET 0x0 +#define DC_B_WIN_BD_H_INITIAL_DDA_0_BD_H_INITIAL_DDA_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WIN_BD_H_INITIAL_DDA_0_BD_H_INITIAL_DDA_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WIN_BD_H_INITIAL_DDA_0_BD_H_INITIAL_DDA_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WIN_BD_H_INITIAL_DDA_0_BD_H_INITIAL_DDA_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_B_WIN_BD_V_INITIAL_DDA_0 +#define DC_B_WIN_BD_V_INITIAL_DDA_0 _MK_ADDR_CONST(0xd88) +#define DC_B_WIN_BD_V_INITIAL_DDA_0_SECURE 0x0 +#define DC_B_WIN_BD_V_INITIAL_DDA_0_WORD_COUNT 0x1 +#define DC_B_WIN_BD_V_INITIAL_DDA_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WIN_BD_V_INITIAL_DDA_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WIN_BD_V_INITIAL_DDA_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WIN_BD_V_INITIAL_DDA_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WIN_BD_V_INITIAL_DDA_0_READ_MASK _MK_MASK_CONST(0xffff) +#define DC_B_WIN_BD_V_INITIAL_DDA_0_WRITE_MASK _MK_MASK_CONST(0xffff) +#define DC_B_WIN_BD_V_INITIAL_DDA_0_BD_V_INITIAL_DDA_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WIN_BD_V_INITIAL_DDA_0_BD_V_INITIAL_DDA_FIELD _MK_FIELD_CONST(0xffff, DC_B_WIN_BD_V_INITIAL_DDA_0_BD_V_INITIAL_DDA_SHIFT) +#define DC_B_WIN_BD_V_INITIAL_DDA_0_BD_V_INITIAL_DDA_RANGE 15:0 +#define DC_B_WIN_BD_V_INITIAL_DDA_0_BD_V_INITIAL_DDA_WOFFSET 0x0 +#define DC_B_WIN_BD_V_INITIAL_DDA_0_BD_V_INITIAL_DDA_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WIN_BD_V_INITIAL_DDA_0_BD_V_INITIAL_DDA_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WIN_BD_V_INITIAL_DDA_0_BD_V_INITIAL_DDA_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WIN_BD_V_INITIAL_DDA_0_BD_V_INITIAL_DDA_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_B_WIN_BD_DDA_INCREMENT_0 +#define DC_B_WIN_BD_DDA_INCREMENT_0 _MK_ADDR_CONST(0xd89) +#define DC_B_WIN_BD_DDA_INCREMENT_0_SECURE 0x0 +#define DC_B_WIN_BD_DDA_INCREMENT_0_WORD_COUNT 0x1 +#define DC_B_WIN_BD_DDA_INCREMENT_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WIN_BD_DDA_INCREMENT_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WIN_BD_DDA_INCREMENT_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WIN_BD_DDA_INCREMENT_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WIN_BD_DDA_INCREMENT_0_READ_MASK _MK_MASK_CONST(0xffffffff) +#define DC_B_WIN_BD_DDA_INCREMENT_0_WRITE_MASK _MK_MASK_CONST(0xffffffff) +#define DC_B_WIN_BD_DDA_INCREMENT_0_BD_H_DDA_INCREMENT_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WIN_BD_DDA_INCREMENT_0_BD_H_DDA_INCREMENT_FIELD _MK_FIELD_CONST(0xffff, DC_B_WIN_BD_DDA_INCREMENT_0_BD_H_DDA_INCREMENT_SHIFT) +#define DC_B_WIN_BD_DDA_INCREMENT_0_BD_H_DDA_INCREMENT_RANGE 15:0 +#define DC_B_WIN_BD_DDA_INCREMENT_0_BD_H_DDA_INCREMENT_WOFFSET 0x0 +#define DC_B_WIN_BD_DDA_INCREMENT_0_BD_H_DDA_INCREMENT_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WIN_BD_DDA_INCREMENT_0_BD_H_DDA_INCREMENT_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WIN_BD_DDA_INCREMENT_0_BD_H_DDA_INCREMENT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WIN_BD_DDA_INCREMENT_0_BD_H_DDA_INCREMENT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WIN_BD_DDA_INCREMENT_0_BD_V_DDA_INCREMENT_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WIN_BD_DDA_INCREMENT_0_BD_V_DDA_INCREMENT_FIELD _MK_FIELD_CONST(0xffff, DC_B_WIN_BD_DDA_INCREMENT_0_BD_V_DDA_INCREMENT_SHIFT) +#define DC_B_WIN_BD_DDA_INCREMENT_0_BD_V_DDA_INCREMENT_RANGE 31:16 +#define DC_B_WIN_BD_DDA_INCREMENT_0_BD_V_DDA_INCREMENT_WOFFSET 0x0 +#define DC_B_WIN_BD_DDA_INCREMENT_0_BD_V_DDA_INCREMENT_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WIN_BD_DDA_INCREMENT_0_BD_V_DDA_INCREMENT_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WIN_BD_DDA_INCREMENT_0_BD_V_DDA_INCREMENT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WIN_BD_DDA_INCREMENT_0_BD_V_DDA_INCREMENT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_B_WIN_BD_LINE_STRIDE_0 +#define DC_B_WIN_BD_LINE_STRIDE_0 _MK_ADDR_CONST(0xd8a) +#define DC_B_WIN_BD_LINE_STRIDE_0_SECURE 0x0 +#define DC_B_WIN_BD_LINE_STRIDE_0_WORD_COUNT 0x1 +#define DC_B_WIN_BD_LINE_STRIDE_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WIN_BD_LINE_STRIDE_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WIN_BD_LINE_STRIDE_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WIN_BD_LINE_STRIDE_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WIN_BD_LINE_STRIDE_0_READ_MASK _MK_MASK_CONST(0xffffffff) +#define DC_B_WIN_BD_LINE_STRIDE_0_WRITE_MASK _MK_MASK_CONST(0xffffffff) +#define DC_B_WIN_BD_LINE_STRIDE_0_BD_LINE_STRIDE_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WIN_BD_LINE_STRIDE_0_BD_LINE_STRIDE_FIELD _MK_FIELD_CONST(0xffff, DC_B_WIN_BD_LINE_STRIDE_0_BD_LINE_STRIDE_SHIFT) +#define DC_B_WIN_BD_LINE_STRIDE_0_BD_LINE_STRIDE_RANGE 15:0 +#define DC_B_WIN_BD_LINE_STRIDE_0_BD_LINE_STRIDE_WOFFSET 0x0 +#define DC_B_WIN_BD_LINE_STRIDE_0_BD_LINE_STRIDE_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WIN_BD_LINE_STRIDE_0_BD_LINE_STRIDE_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WIN_BD_LINE_STRIDE_0_BD_LINE_STRIDE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WIN_BD_LINE_STRIDE_0_BD_LINE_STRIDE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WIN_BD_LINE_STRIDE_0_BD_UV_LINE_STRIDE_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WIN_BD_LINE_STRIDE_0_BD_UV_LINE_STRIDE_FIELD _MK_FIELD_CONST(0xffff, DC_B_WIN_BD_LINE_STRIDE_0_BD_UV_LINE_STRIDE_SHIFT) +#define DC_B_WIN_BD_LINE_STRIDE_0_BD_UV_LINE_STRIDE_RANGE 31:16 +#define DC_B_WIN_BD_LINE_STRIDE_0_BD_UV_LINE_STRIDE_WOFFSET 0x0 +#define DC_B_WIN_BD_LINE_STRIDE_0_BD_UV_LINE_STRIDE_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WIN_BD_LINE_STRIDE_0_BD_UV_LINE_STRIDE_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WIN_BD_LINE_STRIDE_0_BD_UV_LINE_STRIDE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WIN_BD_LINE_STRIDE_0_BD_UV_LINE_STRIDE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Reserved address 3467 [0xd8b] + +// Reserved address 3468 [0xd8c] + +// Reserved address 3469 [0xd8d] + +// Register DC_B_WIN_BD_DV_CONTROL_0 +#define DC_B_WIN_BD_DV_CONTROL_0 _MK_ADDR_CONST(0xd8e) +#define DC_B_WIN_BD_DV_CONTROL_0_SECURE 0x0 +#define DC_B_WIN_BD_DV_CONTROL_0_WORD_COUNT 0x1 +#define DC_B_WIN_BD_DV_CONTROL_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WIN_BD_DV_CONTROL_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WIN_BD_DV_CONTROL_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WIN_BD_DV_CONTROL_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WIN_BD_DV_CONTROL_0_READ_MASK _MK_MASK_CONST(0x70707) +#define DC_B_WIN_BD_DV_CONTROL_0_WRITE_MASK _MK_MASK_CONST(0x70707) +#define DC_B_WIN_BD_DV_CONTROL_0_BD_DV_CONTROL_R_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WIN_BD_DV_CONTROL_0_BD_DV_CONTROL_R_FIELD _MK_FIELD_CONST(0x7, DC_B_WIN_BD_DV_CONTROL_0_BD_DV_CONTROL_R_SHIFT) +#define DC_B_WIN_BD_DV_CONTROL_0_BD_DV_CONTROL_R_RANGE 2:0 +#define DC_B_WIN_BD_DV_CONTROL_0_BD_DV_CONTROL_R_WOFFSET 0x0 +#define DC_B_WIN_BD_DV_CONTROL_0_BD_DV_CONTROL_R_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WIN_BD_DV_CONTROL_0_BD_DV_CONTROL_R_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WIN_BD_DV_CONTROL_0_BD_DV_CONTROL_R_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WIN_BD_DV_CONTROL_0_BD_DV_CONTROL_R_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WIN_BD_DV_CONTROL_0_BD_DV_CONTROL_G_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WIN_BD_DV_CONTROL_0_BD_DV_CONTROL_G_FIELD _MK_FIELD_CONST(0x7, DC_B_WIN_BD_DV_CONTROL_0_BD_DV_CONTROL_G_SHIFT) +#define DC_B_WIN_BD_DV_CONTROL_0_BD_DV_CONTROL_G_RANGE 10:8 +#define DC_B_WIN_BD_DV_CONTROL_0_BD_DV_CONTROL_G_WOFFSET 0x0 +#define DC_B_WIN_BD_DV_CONTROL_0_BD_DV_CONTROL_G_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WIN_BD_DV_CONTROL_0_BD_DV_CONTROL_G_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WIN_BD_DV_CONTROL_0_BD_DV_CONTROL_G_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WIN_BD_DV_CONTROL_0_BD_DV_CONTROL_G_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WIN_BD_DV_CONTROL_0_BD_DV_CONTROL_B_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WIN_BD_DV_CONTROL_0_BD_DV_CONTROL_B_FIELD _MK_FIELD_CONST(0x7, DC_B_WIN_BD_DV_CONTROL_0_BD_DV_CONTROL_B_SHIFT) +#define DC_B_WIN_BD_DV_CONTROL_0_BD_DV_CONTROL_B_RANGE 18:16 +#define DC_B_WIN_BD_DV_CONTROL_0_BD_DV_CONTROL_B_WOFFSET 0x0 +#define DC_B_WIN_BD_DV_CONTROL_0_BD_DV_CONTROL_B_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WIN_BD_DV_CONTROL_0_BD_DV_CONTROL_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WIN_BD_DV_CONTROL_0_BD_DV_CONTROL_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WIN_BD_DV_CONTROL_0_BD_DV_CONTROL_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Reserved address 3471 [0xd8f] + +// Reserved address 3472 [0xd90] + +// Reserved address 3473 [0xd91] + +// Reserved address 3474 [0xd92] + +// Reserved address 3475 [0xd93] + +// Reserved address 3476 [0xd94] + +// Reserved address 3477 [0xd95] + +// Register DC_B_WIN_BD_BLEND_LAYER_CONTROL_0 +#define DC_B_WIN_BD_BLEND_LAYER_CONTROL_0 _MK_ADDR_CONST(0xd96) +#define DC_B_WIN_BD_BLEND_LAYER_CONTROL_0_SECURE 0x0 +#define DC_B_WIN_BD_BLEND_LAYER_CONTROL_0_WORD_COUNT 0x1 +#define DC_B_WIN_BD_BLEND_LAYER_CONTROL_0_RESET_VAL _MK_MASK_CONST(0x1000000) +#define DC_B_WIN_BD_BLEND_LAYER_CONTROL_0_RESET_MASK _MK_MASK_CONST(0xfffffff) +#define DC_B_WIN_BD_BLEND_LAYER_CONTROL_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WIN_BD_BLEND_LAYER_CONTROL_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WIN_BD_BLEND_LAYER_CONTROL_0_READ_MASK _MK_MASK_CONST(0xfffffff) +#define DC_B_WIN_BD_BLEND_LAYER_CONTROL_0_WRITE_MASK _MK_MASK_CONST(0xfffffff) +#define DC_B_WIN_BD_BLEND_LAYER_CONTROL_0_BD_WINDOW_LAYER_DEPTH_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WIN_BD_BLEND_LAYER_CONTROL_0_BD_WINDOW_LAYER_DEPTH_FIELD _MK_FIELD_CONST(0xff, DC_B_WIN_BD_BLEND_LAYER_CONTROL_0_BD_WINDOW_LAYER_DEPTH_SHIFT) +#define DC_B_WIN_BD_BLEND_LAYER_CONTROL_0_BD_WINDOW_LAYER_DEPTH_RANGE 7:0 +#define DC_B_WIN_BD_BLEND_LAYER_CONTROL_0_BD_WINDOW_LAYER_DEPTH_WOFFSET 0x0 +#define DC_B_WIN_BD_BLEND_LAYER_CONTROL_0_BD_WINDOW_LAYER_DEPTH_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WIN_BD_BLEND_LAYER_CONTROL_0_BD_WINDOW_LAYER_DEPTH_DEFAULT_MASK _MK_MASK_CONST(0xff) +#define DC_B_WIN_BD_BLEND_LAYER_CONTROL_0_BD_WINDOW_LAYER_DEPTH_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WIN_BD_BLEND_LAYER_CONTROL_0_BD_WINDOW_LAYER_DEPTH_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WIN_BD_BLEND_LAYER_CONTROL_0_BD_K1_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WIN_BD_BLEND_LAYER_CONTROL_0_BD_K1_FIELD _MK_FIELD_CONST(0xff, DC_B_WIN_BD_BLEND_LAYER_CONTROL_0_BD_K1_SHIFT) +#define DC_B_WIN_BD_BLEND_LAYER_CONTROL_0_BD_K1_RANGE 15:8 +#define DC_B_WIN_BD_BLEND_LAYER_CONTROL_0_BD_K1_WOFFSET 0x0 +#define DC_B_WIN_BD_BLEND_LAYER_CONTROL_0_BD_K1_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WIN_BD_BLEND_LAYER_CONTROL_0_BD_K1_DEFAULT_MASK _MK_MASK_CONST(0xff) +#define DC_B_WIN_BD_BLEND_LAYER_CONTROL_0_BD_K1_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WIN_BD_BLEND_LAYER_CONTROL_0_BD_K1_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WIN_BD_BLEND_LAYER_CONTROL_0_BD_K2_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WIN_BD_BLEND_LAYER_CONTROL_0_BD_K2_FIELD _MK_FIELD_CONST(0xff, DC_B_WIN_BD_BLEND_LAYER_CONTROL_0_BD_K2_SHIFT) +#define DC_B_WIN_BD_BLEND_LAYER_CONTROL_0_BD_K2_RANGE 23:16 +#define DC_B_WIN_BD_BLEND_LAYER_CONTROL_0_BD_K2_WOFFSET 0x0 +#define DC_B_WIN_BD_BLEND_LAYER_CONTROL_0_BD_K2_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WIN_BD_BLEND_LAYER_CONTROL_0_BD_K2_DEFAULT_MASK _MK_MASK_CONST(0xff) +#define DC_B_WIN_BD_BLEND_LAYER_CONTROL_0_BD_K2_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WIN_BD_BLEND_LAYER_CONTROL_0_BD_K2_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WIN_BD_BLEND_LAYER_CONTROL_0_BD_BLEND_BYPASS_SHIFT _MK_SHIFT_CONST(24) +#define DC_B_WIN_BD_BLEND_LAYER_CONTROL_0_BD_BLEND_BYPASS_FIELD _MK_FIELD_CONST(0x1, DC_B_WIN_BD_BLEND_LAYER_CONTROL_0_BD_BLEND_BYPASS_SHIFT) +#define DC_B_WIN_BD_BLEND_LAYER_CONTROL_0_BD_BLEND_BYPASS_RANGE 24:24 +#define DC_B_WIN_BD_BLEND_LAYER_CONTROL_0_BD_BLEND_BYPASS_WOFFSET 0x0 +#define DC_B_WIN_BD_BLEND_LAYER_CONTROL_0_BD_BLEND_BYPASS_DEFAULT _MK_MASK_CONST(0x1) +#define DC_B_WIN_BD_BLEND_LAYER_CONTROL_0_BD_BLEND_BYPASS_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_B_WIN_BD_BLEND_LAYER_CONTROL_0_BD_BLEND_BYPASS_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WIN_BD_BLEND_LAYER_CONTROL_0_BD_BLEND_BYPASS_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WIN_BD_BLEND_LAYER_CONTROL_0_BD_BLEND_BYPASS_INIT_ENUM BLEND_BYPASS +#define DC_B_WIN_BD_BLEND_LAYER_CONTROL_0_BD_BLEND_BYPASS_BLEND_ENABLE _MK_ENUM_CONST(0) +#define DC_B_WIN_BD_BLEND_LAYER_CONTROL_0_BD_BLEND_BYPASS_BLEND_BYPASS _MK_ENUM_CONST(1) + +#define DC_B_WIN_BD_BLEND_LAYER_CONTROL_0_BD_COLOR_KEY_SELECT_SHIFT _MK_SHIFT_CONST(25) +#define DC_B_WIN_BD_BLEND_LAYER_CONTROL_0_BD_COLOR_KEY_SELECT_FIELD _MK_FIELD_CONST(0x7, DC_B_WIN_BD_BLEND_LAYER_CONTROL_0_BD_COLOR_KEY_SELECT_SHIFT) +#define DC_B_WIN_BD_BLEND_LAYER_CONTROL_0_BD_COLOR_KEY_SELECT_RANGE 27:25 +#define DC_B_WIN_BD_BLEND_LAYER_CONTROL_0_BD_COLOR_KEY_SELECT_WOFFSET 0x0 +#define DC_B_WIN_BD_BLEND_LAYER_CONTROL_0_BD_COLOR_KEY_SELECT_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WIN_BD_BLEND_LAYER_CONTROL_0_BD_COLOR_KEY_SELECT_DEFAULT_MASK _MK_MASK_CONST(0x7) +#define DC_B_WIN_BD_BLEND_LAYER_CONTROL_0_BD_COLOR_KEY_SELECT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WIN_BD_BLEND_LAYER_CONTROL_0_BD_COLOR_KEY_SELECT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WIN_BD_BLEND_LAYER_CONTROL_0_BD_COLOR_KEY_SELECT_NONE _MK_ENUM_CONST(0) +#define DC_B_WIN_BD_BLEND_LAYER_CONTROL_0_BD_COLOR_KEY_SELECT_WINDOWA_KEY0 _MK_ENUM_CONST(1) +#define DC_B_WIN_BD_BLEND_LAYER_CONTROL_0_BD_COLOR_KEY_SELECT_WINDOWA_KEY1 _MK_ENUM_CONST(2) +#define DC_B_WIN_BD_BLEND_LAYER_CONTROL_0_BD_COLOR_KEY_SELECT_WINDOWB_KEY0 _MK_ENUM_CONST(3) +#define DC_B_WIN_BD_BLEND_LAYER_CONTROL_0_BD_COLOR_KEY_SELECT_WINDOWB_KEY1 _MK_ENUM_CONST(4) +#define DC_B_WIN_BD_BLEND_LAYER_CONTROL_0_BD_COLOR_KEY_SELECT_WINDOWC_KEY0 _MK_ENUM_CONST(5) +#define DC_B_WIN_BD_BLEND_LAYER_CONTROL_0_BD_COLOR_KEY_SELECT_WINDOWC_KEY1 _MK_ENUM_CONST(6) + + +// Register DC_B_WIN_BD_BLEND_MATCH_SELECT_0 +#define DC_B_WIN_BD_BLEND_MATCH_SELECT_0 _MK_ADDR_CONST(0xd97) +#define DC_B_WIN_BD_BLEND_MATCH_SELECT_0_SECURE 0x0 +#define DC_B_WIN_BD_BLEND_MATCH_SELECT_0_WORD_COUNT 0x1 +#define DC_B_WIN_BD_BLEND_MATCH_SELECT_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WIN_BD_BLEND_MATCH_SELECT_0_RESET_MASK _MK_MASK_CONST(0x3377) +#define DC_B_WIN_BD_BLEND_MATCH_SELECT_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WIN_BD_BLEND_MATCH_SELECT_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WIN_BD_BLEND_MATCH_SELECT_0_READ_MASK _MK_MASK_CONST(0x3377) +#define DC_B_WIN_BD_BLEND_MATCH_SELECT_0_WRITE_MASK _MK_MASK_CONST(0x3377) +#define DC_B_WIN_BD_BLEND_MATCH_SELECT_0_BD_BLEND_FACTOR_SRC_COLOR_MATCH_SELECT_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WIN_BD_BLEND_MATCH_SELECT_0_BD_BLEND_FACTOR_SRC_COLOR_MATCH_SELECT_FIELD _MK_FIELD_CONST(0x7, DC_B_WIN_BD_BLEND_MATCH_SELECT_0_BD_BLEND_FACTOR_SRC_COLOR_MATCH_SELECT_SHIFT) +#define DC_B_WIN_BD_BLEND_MATCH_SELECT_0_BD_BLEND_FACTOR_SRC_COLOR_MATCH_SELECT_RANGE 2:0 +#define DC_B_WIN_BD_BLEND_MATCH_SELECT_0_BD_BLEND_FACTOR_SRC_COLOR_MATCH_SELECT_WOFFSET 0x0 +#define DC_B_WIN_BD_BLEND_MATCH_SELECT_0_BD_BLEND_FACTOR_SRC_COLOR_MATCH_SELECT_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WIN_BD_BLEND_MATCH_SELECT_0_BD_BLEND_FACTOR_SRC_COLOR_MATCH_SELECT_DEFAULT_MASK _MK_MASK_CONST(0x7) +#define DC_B_WIN_BD_BLEND_MATCH_SELECT_0_BD_BLEND_FACTOR_SRC_COLOR_MATCH_SELECT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WIN_BD_BLEND_MATCH_SELECT_0_BD_BLEND_FACTOR_SRC_COLOR_MATCH_SELECT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WIN_BD_BLEND_MATCH_SELECT_0_BD_BLEND_FACTOR_SRC_COLOR_MATCH_SELECT_ZERO _MK_ENUM_CONST(0) +#define DC_B_WIN_BD_BLEND_MATCH_SELECT_0_BD_BLEND_FACTOR_SRC_COLOR_MATCH_SELECT_ONE _MK_ENUM_CONST(1) +#define DC_B_WIN_BD_BLEND_MATCH_SELECT_0_BD_BLEND_FACTOR_SRC_COLOR_MATCH_SELECT_K1 _MK_ENUM_CONST(2) +#define DC_B_WIN_BD_BLEND_MATCH_SELECT_0_BD_BLEND_FACTOR_SRC_COLOR_MATCH_SELECT_K1_TIMES_DST _MK_ENUM_CONST(3) +#define DC_B_WIN_BD_BLEND_MATCH_SELECT_0_BD_BLEND_FACTOR_SRC_COLOR_MATCH_SELECT_NEG_K1_TIMES_DST _MK_ENUM_CONST(4) +#define DC_B_WIN_BD_BLEND_MATCH_SELECT_0_BD_BLEND_FACTOR_SRC_COLOR_MATCH_SELECT_K1_TIMES_SRC _MK_ENUM_CONST(5) + +#define DC_B_WIN_BD_BLEND_MATCH_SELECT_0_BD_BLEND_FACTOR_DST_COLOR_MATCH_SELECT_SHIFT _MK_SHIFT_CONST(4) +#define DC_B_WIN_BD_BLEND_MATCH_SELECT_0_BD_BLEND_FACTOR_DST_COLOR_MATCH_SELECT_FIELD _MK_FIELD_CONST(0x7, DC_B_WIN_BD_BLEND_MATCH_SELECT_0_BD_BLEND_FACTOR_DST_COLOR_MATCH_SELECT_SHIFT) +#define DC_B_WIN_BD_BLEND_MATCH_SELECT_0_BD_BLEND_FACTOR_DST_COLOR_MATCH_SELECT_RANGE 6:4 +#define DC_B_WIN_BD_BLEND_MATCH_SELECT_0_BD_BLEND_FACTOR_DST_COLOR_MATCH_SELECT_WOFFSET 0x0 +#define DC_B_WIN_BD_BLEND_MATCH_SELECT_0_BD_BLEND_FACTOR_DST_COLOR_MATCH_SELECT_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WIN_BD_BLEND_MATCH_SELECT_0_BD_BLEND_FACTOR_DST_COLOR_MATCH_SELECT_DEFAULT_MASK _MK_MASK_CONST(0x7) +#define DC_B_WIN_BD_BLEND_MATCH_SELECT_0_BD_BLEND_FACTOR_DST_COLOR_MATCH_SELECT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WIN_BD_BLEND_MATCH_SELECT_0_BD_BLEND_FACTOR_DST_COLOR_MATCH_SELECT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WIN_BD_BLEND_MATCH_SELECT_0_BD_BLEND_FACTOR_DST_COLOR_MATCH_SELECT_ZERO _MK_ENUM_CONST(0) +#define DC_B_WIN_BD_BLEND_MATCH_SELECT_0_BD_BLEND_FACTOR_DST_COLOR_MATCH_SELECT_ONE _MK_ENUM_CONST(1) +#define DC_B_WIN_BD_BLEND_MATCH_SELECT_0_BD_BLEND_FACTOR_DST_COLOR_MATCH_SELECT_K1 _MK_ENUM_CONST(2) +#define DC_B_WIN_BD_BLEND_MATCH_SELECT_0_BD_BLEND_FACTOR_DST_COLOR_MATCH_SELECT_K2 _MK_ENUM_CONST(3) +#define DC_B_WIN_BD_BLEND_MATCH_SELECT_0_BD_BLEND_FACTOR_DST_COLOR_MATCH_SELECT_K1_TIMES_DST _MK_ENUM_CONST(4) +#define DC_B_WIN_BD_BLEND_MATCH_SELECT_0_BD_BLEND_FACTOR_DST_COLOR_MATCH_SELECT_NEG_K1_TIMES_DST _MK_ENUM_CONST(5) +#define DC_B_WIN_BD_BLEND_MATCH_SELECT_0_BD_BLEND_FACTOR_DST_COLOR_MATCH_SELECT_NEG_K1_TIMES_SRC _MK_ENUM_CONST(6) +#define DC_B_WIN_BD_BLEND_MATCH_SELECT_0_BD_BLEND_FACTOR_DST_COLOR_MATCH_SELECT_NEG_K1 _MK_ENUM_CONST(7) + +#define DC_B_WIN_BD_BLEND_MATCH_SELECT_0_BD_BLEND_FACTOR_SRC_ALPHA_MATCH_SELECT_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WIN_BD_BLEND_MATCH_SELECT_0_BD_BLEND_FACTOR_SRC_ALPHA_MATCH_SELECT_FIELD _MK_FIELD_CONST(0x3, DC_B_WIN_BD_BLEND_MATCH_SELECT_0_BD_BLEND_FACTOR_SRC_ALPHA_MATCH_SELECT_SHIFT) +#define DC_B_WIN_BD_BLEND_MATCH_SELECT_0_BD_BLEND_FACTOR_SRC_ALPHA_MATCH_SELECT_RANGE 9:8 +#define DC_B_WIN_BD_BLEND_MATCH_SELECT_0_BD_BLEND_FACTOR_SRC_ALPHA_MATCH_SELECT_WOFFSET 0x0 +#define DC_B_WIN_BD_BLEND_MATCH_SELECT_0_BD_BLEND_FACTOR_SRC_ALPHA_MATCH_SELECT_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WIN_BD_BLEND_MATCH_SELECT_0_BD_BLEND_FACTOR_SRC_ALPHA_MATCH_SELECT_DEFAULT_MASK _MK_MASK_CONST(0x3) +#define DC_B_WIN_BD_BLEND_MATCH_SELECT_0_BD_BLEND_FACTOR_SRC_ALPHA_MATCH_SELECT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WIN_BD_BLEND_MATCH_SELECT_0_BD_BLEND_FACTOR_SRC_ALPHA_MATCH_SELECT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WIN_BD_BLEND_MATCH_SELECT_0_BD_BLEND_FACTOR_SRC_ALPHA_MATCH_SELECT_ZERO _MK_ENUM_CONST(0) +#define DC_B_WIN_BD_BLEND_MATCH_SELECT_0_BD_BLEND_FACTOR_SRC_ALPHA_MATCH_SELECT_K1 _MK_ENUM_CONST(1) +#define DC_B_WIN_BD_BLEND_MATCH_SELECT_0_BD_BLEND_FACTOR_SRC_ALPHA_MATCH_SELECT_K2 _MK_ENUM_CONST(2) + +#define DC_B_WIN_BD_BLEND_MATCH_SELECT_0_BD_BLEND_FACTOR_DST_ALPHA_MATCH_SELECT_SHIFT _MK_SHIFT_CONST(12) +#define DC_B_WIN_BD_BLEND_MATCH_SELECT_0_BD_BLEND_FACTOR_DST_ALPHA_MATCH_SELECT_FIELD _MK_FIELD_CONST(0x3, DC_B_WIN_BD_BLEND_MATCH_SELECT_0_BD_BLEND_FACTOR_DST_ALPHA_MATCH_SELECT_SHIFT) +#define DC_B_WIN_BD_BLEND_MATCH_SELECT_0_BD_BLEND_FACTOR_DST_ALPHA_MATCH_SELECT_RANGE 13:12 +#define DC_B_WIN_BD_BLEND_MATCH_SELECT_0_BD_BLEND_FACTOR_DST_ALPHA_MATCH_SELECT_WOFFSET 0x0 +#define DC_B_WIN_BD_BLEND_MATCH_SELECT_0_BD_BLEND_FACTOR_DST_ALPHA_MATCH_SELECT_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WIN_BD_BLEND_MATCH_SELECT_0_BD_BLEND_FACTOR_DST_ALPHA_MATCH_SELECT_DEFAULT_MASK _MK_MASK_CONST(0x3) +#define DC_B_WIN_BD_BLEND_MATCH_SELECT_0_BD_BLEND_FACTOR_DST_ALPHA_MATCH_SELECT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WIN_BD_BLEND_MATCH_SELECT_0_BD_BLEND_FACTOR_DST_ALPHA_MATCH_SELECT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WIN_BD_BLEND_MATCH_SELECT_0_BD_BLEND_FACTOR_DST_ALPHA_MATCH_SELECT_ZERO _MK_ENUM_CONST(0) +#define DC_B_WIN_BD_BLEND_MATCH_SELECT_0_BD_BLEND_FACTOR_DST_ALPHA_MATCH_SELECT_ONE _MK_ENUM_CONST(1) +#define DC_B_WIN_BD_BLEND_MATCH_SELECT_0_BD_BLEND_FACTOR_DST_ALPHA_MATCH_SELECT_NEG_K1_TIMES_SRC _MK_ENUM_CONST(2) +#define DC_B_WIN_BD_BLEND_MATCH_SELECT_0_BD_BLEND_FACTOR_DST_ALPHA_MATCH_SELECT_K2 _MK_ENUM_CONST(3) + + +// Register DC_B_WIN_BD_BLEND_NOMATCH_SELECT_0 +#define DC_B_WIN_BD_BLEND_NOMATCH_SELECT_0 _MK_ADDR_CONST(0xd98) +#define DC_B_WIN_BD_BLEND_NOMATCH_SELECT_0_SECURE 0x0 +#define DC_B_WIN_BD_BLEND_NOMATCH_SELECT_0_WORD_COUNT 0x1 +#define DC_B_WIN_BD_BLEND_NOMATCH_SELECT_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WIN_BD_BLEND_NOMATCH_SELECT_0_RESET_MASK _MK_MASK_CONST(0x3377) +#define DC_B_WIN_BD_BLEND_NOMATCH_SELECT_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WIN_BD_BLEND_NOMATCH_SELECT_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WIN_BD_BLEND_NOMATCH_SELECT_0_READ_MASK _MK_MASK_CONST(0x3377) +#define DC_B_WIN_BD_BLEND_NOMATCH_SELECT_0_WRITE_MASK _MK_MASK_CONST(0x3377) +#define DC_B_WIN_BD_BLEND_NOMATCH_SELECT_0_BD_BLEND_FACTOR_SRC_COLOR_NOMATCH_SELECT_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WIN_BD_BLEND_NOMATCH_SELECT_0_BD_BLEND_FACTOR_SRC_COLOR_NOMATCH_SELECT_FIELD _MK_FIELD_CONST(0x7, DC_B_WIN_BD_BLEND_NOMATCH_SELECT_0_BD_BLEND_FACTOR_SRC_COLOR_NOMATCH_SELECT_SHIFT) +#define DC_B_WIN_BD_BLEND_NOMATCH_SELECT_0_BD_BLEND_FACTOR_SRC_COLOR_NOMATCH_SELECT_RANGE 2:0 +#define DC_B_WIN_BD_BLEND_NOMATCH_SELECT_0_BD_BLEND_FACTOR_SRC_COLOR_NOMATCH_SELECT_WOFFSET 0x0 +#define DC_B_WIN_BD_BLEND_NOMATCH_SELECT_0_BD_BLEND_FACTOR_SRC_COLOR_NOMATCH_SELECT_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WIN_BD_BLEND_NOMATCH_SELECT_0_BD_BLEND_FACTOR_SRC_COLOR_NOMATCH_SELECT_DEFAULT_MASK _MK_MASK_CONST(0x7) +#define DC_B_WIN_BD_BLEND_NOMATCH_SELECT_0_BD_BLEND_FACTOR_SRC_COLOR_NOMATCH_SELECT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WIN_BD_BLEND_NOMATCH_SELECT_0_BD_BLEND_FACTOR_SRC_COLOR_NOMATCH_SELECT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WIN_BD_BLEND_NOMATCH_SELECT_0_BD_BLEND_FACTOR_SRC_COLOR_NOMATCH_SELECT_ZERO _MK_ENUM_CONST(0) +#define DC_B_WIN_BD_BLEND_NOMATCH_SELECT_0_BD_BLEND_FACTOR_SRC_COLOR_NOMATCH_SELECT_ONE _MK_ENUM_CONST(1) +#define DC_B_WIN_BD_BLEND_NOMATCH_SELECT_0_BD_BLEND_FACTOR_SRC_COLOR_NOMATCH_SELECT_K1 _MK_ENUM_CONST(2) +#define DC_B_WIN_BD_BLEND_NOMATCH_SELECT_0_BD_BLEND_FACTOR_SRC_COLOR_NOMATCH_SELECT_K1_TIMES_DST _MK_ENUM_CONST(3) +#define DC_B_WIN_BD_BLEND_NOMATCH_SELECT_0_BD_BLEND_FACTOR_SRC_COLOR_NOMATCH_SELECT_NEG_K1_TIMES_DST _MK_ENUM_CONST(4) +#define DC_B_WIN_BD_BLEND_NOMATCH_SELECT_0_BD_BLEND_FACTOR_SRC_COLOR_NOMATCH_SELECT_K1_TIMES_SRC _MK_ENUM_CONST(5) + +#define DC_B_WIN_BD_BLEND_NOMATCH_SELECT_0_BD_BLEND_FACTOR_DST_COLOR_NOMATCH_SELECT_SHIFT _MK_SHIFT_CONST(4) +#define DC_B_WIN_BD_BLEND_NOMATCH_SELECT_0_BD_BLEND_FACTOR_DST_COLOR_NOMATCH_SELECT_FIELD _MK_FIELD_CONST(0x7, DC_B_WIN_BD_BLEND_NOMATCH_SELECT_0_BD_BLEND_FACTOR_DST_COLOR_NOMATCH_SELECT_SHIFT) +#define DC_B_WIN_BD_BLEND_NOMATCH_SELECT_0_BD_BLEND_FACTOR_DST_COLOR_NOMATCH_SELECT_RANGE 6:4 +#define DC_B_WIN_BD_BLEND_NOMATCH_SELECT_0_BD_BLEND_FACTOR_DST_COLOR_NOMATCH_SELECT_WOFFSET 0x0 +#define DC_B_WIN_BD_BLEND_NOMATCH_SELECT_0_BD_BLEND_FACTOR_DST_COLOR_NOMATCH_SELECT_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WIN_BD_BLEND_NOMATCH_SELECT_0_BD_BLEND_FACTOR_DST_COLOR_NOMATCH_SELECT_DEFAULT_MASK _MK_MASK_CONST(0x7) +#define DC_B_WIN_BD_BLEND_NOMATCH_SELECT_0_BD_BLEND_FACTOR_DST_COLOR_NOMATCH_SELECT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WIN_BD_BLEND_NOMATCH_SELECT_0_BD_BLEND_FACTOR_DST_COLOR_NOMATCH_SELECT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WIN_BD_BLEND_NOMATCH_SELECT_0_BD_BLEND_FACTOR_DST_COLOR_NOMATCH_SELECT_ZERO _MK_ENUM_CONST(0) +#define DC_B_WIN_BD_BLEND_NOMATCH_SELECT_0_BD_BLEND_FACTOR_DST_COLOR_NOMATCH_SELECT_ONE _MK_ENUM_CONST(1) +#define DC_B_WIN_BD_BLEND_NOMATCH_SELECT_0_BD_BLEND_FACTOR_DST_COLOR_NOMATCH_SELECT_K1 _MK_ENUM_CONST(2) +#define DC_B_WIN_BD_BLEND_NOMATCH_SELECT_0_BD_BLEND_FACTOR_DST_COLOR_NOMATCH_SELECT_K2 _MK_ENUM_CONST(3) +#define DC_B_WIN_BD_BLEND_NOMATCH_SELECT_0_BD_BLEND_FACTOR_DST_COLOR_NOMATCH_SELECT_K1_TIMES_DST _MK_ENUM_CONST(4) +#define DC_B_WIN_BD_BLEND_NOMATCH_SELECT_0_BD_BLEND_FACTOR_DST_COLOR_NOMATCH_SELECT_NEG_K1_TIMES_DST _MK_ENUM_CONST(5) +#define DC_B_WIN_BD_BLEND_NOMATCH_SELECT_0_BD_BLEND_FACTOR_DST_COLOR_NOMATCH_SELECT_NEG_K1_TIMES_SRC _MK_ENUM_CONST(6) +#define DC_B_WIN_BD_BLEND_NOMATCH_SELECT_0_BD_BLEND_FACTOR_DST_COLOR_NOMATCH_SELECT_NEG_K1 _MK_ENUM_CONST(7) + +#define DC_B_WIN_BD_BLEND_NOMATCH_SELECT_0_BD_BLEND_FACTOR_SRC_ALPHA_NOMATCH_SELECT_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WIN_BD_BLEND_NOMATCH_SELECT_0_BD_BLEND_FACTOR_SRC_ALPHA_NOMATCH_SELECT_FIELD _MK_FIELD_CONST(0x3, DC_B_WIN_BD_BLEND_NOMATCH_SELECT_0_BD_BLEND_FACTOR_SRC_ALPHA_NOMATCH_SELECT_SHIFT) +#define DC_B_WIN_BD_BLEND_NOMATCH_SELECT_0_BD_BLEND_FACTOR_SRC_ALPHA_NOMATCH_SELECT_RANGE 9:8 +#define DC_B_WIN_BD_BLEND_NOMATCH_SELECT_0_BD_BLEND_FACTOR_SRC_ALPHA_NOMATCH_SELECT_WOFFSET 0x0 +#define DC_B_WIN_BD_BLEND_NOMATCH_SELECT_0_BD_BLEND_FACTOR_SRC_ALPHA_NOMATCH_SELECT_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WIN_BD_BLEND_NOMATCH_SELECT_0_BD_BLEND_FACTOR_SRC_ALPHA_NOMATCH_SELECT_DEFAULT_MASK _MK_MASK_CONST(0x3) +#define DC_B_WIN_BD_BLEND_NOMATCH_SELECT_0_BD_BLEND_FACTOR_SRC_ALPHA_NOMATCH_SELECT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WIN_BD_BLEND_NOMATCH_SELECT_0_BD_BLEND_FACTOR_SRC_ALPHA_NOMATCH_SELECT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WIN_BD_BLEND_NOMATCH_SELECT_0_BD_BLEND_FACTOR_SRC_ALPHA_NOMATCH_SELECT_ZERO _MK_ENUM_CONST(0) +#define DC_B_WIN_BD_BLEND_NOMATCH_SELECT_0_BD_BLEND_FACTOR_SRC_ALPHA_NOMATCH_SELECT_K1 _MK_ENUM_CONST(1) +#define DC_B_WIN_BD_BLEND_NOMATCH_SELECT_0_BD_BLEND_FACTOR_SRC_ALPHA_NOMATCH_SELECT_K2 _MK_ENUM_CONST(2) + +#define DC_B_WIN_BD_BLEND_NOMATCH_SELECT_0_BD_BLEND_FACTOR_DST_ALPHA_NOMATCH_SELECT_SHIFT _MK_SHIFT_CONST(12) +#define DC_B_WIN_BD_BLEND_NOMATCH_SELECT_0_BD_BLEND_FACTOR_DST_ALPHA_NOMATCH_SELECT_FIELD _MK_FIELD_CONST(0x3, DC_B_WIN_BD_BLEND_NOMATCH_SELECT_0_BD_BLEND_FACTOR_DST_ALPHA_NOMATCH_SELECT_SHIFT) +#define DC_B_WIN_BD_BLEND_NOMATCH_SELECT_0_BD_BLEND_FACTOR_DST_ALPHA_NOMATCH_SELECT_RANGE 13:12 +#define DC_B_WIN_BD_BLEND_NOMATCH_SELECT_0_BD_BLEND_FACTOR_DST_ALPHA_NOMATCH_SELECT_WOFFSET 0x0 +#define DC_B_WIN_BD_BLEND_NOMATCH_SELECT_0_BD_BLEND_FACTOR_DST_ALPHA_NOMATCH_SELECT_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WIN_BD_BLEND_NOMATCH_SELECT_0_BD_BLEND_FACTOR_DST_ALPHA_NOMATCH_SELECT_DEFAULT_MASK _MK_MASK_CONST(0x3) +#define DC_B_WIN_BD_BLEND_NOMATCH_SELECT_0_BD_BLEND_FACTOR_DST_ALPHA_NOMATCH_SELECT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WIN_BD_BLEND_NOMATCH_SELECT_0_BD_BLEND_FACTOR_DST_ALPHA_NOMATCH_SELECT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WIN_BD_BLEND_NOMATCH_SELECT_0_BD_BLEND_FACTOR_DST_ALPHA_NOMATCH_SELECT_ZERO _MK_ENUM_CONST(0) +#define DC_B_WIN_BD_BLEND_NOMATCH_SELECT_0_BD_BLEND_FACTOR_DST_ALPHA_NOMATCH_SELECT_ONE _MK_ENUM_CONST(1) +#define DC_B_WIN_BD_BLEND_NOMATCH_SELECT_0_BD_BLEND_FACTOR_DST_ALPHA_NOMATCH_SELECT_NEG_K1_TIMES_SRC _MK_ENUM_CONST(2) +#define DC_B_WIN_BD_BLEND_NOMATCH_SELECT_0_BD_BLEND_FACTOR_DST_ALPHA_NOMATCH_SELECT_K2 _MK_ENUM_CONST(3) + + +// Register DC_B_WIN_BD_BLEND_ALPHA_1BIT_0 +#define DC_B_WIN_BD_BLEND_ALPHA_1BIT_0 _MK_ADDR_CONST(0xd99) +#define DC_B_WIN_BD_BLEND_ALPHA_1BIT_0_SECURE 0x0 +#define DC_B_WIN_BD_BLEND_ALPHA_1BIT_0_WORD_COUNT 0x1 +#define DC_B_WIN_BD_BLEND_ALPHA_1BIT_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WIN_BD_BLEND_ALPHA_1BIT_0_RESET_MASK _MK_MASK_CONST(0xffff) +#define DC_B_WIN_BD_BLEND_ALPHA_1BIT_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WIN_BD_BLEND_ALPHA_1BIT_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WIN_BD_BLEND_ALPHA_1BIT_0_READ_MASK _MK_MASK_CONST(0xffff) +#define DC_B_WIN_BD_BLEND_ALPHA_1BIT_0_WRITE_MASK _MK_MASK_CONST(0xffff) +#define DC_B_WIN_BD_BLEND_ALPHA_1BIT_0_BD_BLEND_WEIGHT0_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WIN_BD_BLEND_ALPHA_1BIT_0_BD_BLEND_WEIGHT0_FIELD _MK_FIELD_CONST(0xff, DC_B_WIN_BD_BLEND_ALPHA_1BIT_0_BD_BLEND_WEIGHT0_SHIFT) +#define DC_B_WIN_BD_BLEND_ALPHA_1BIT_0_BD_BLEND_WEIGHT0_RANGE 7:0 +#define DC_B_WIN_BD_BLEND_ALPHA_1BIT_0_BD_BLEND_WEIGHT0_WOFFSET 0x0 +#define DC_B_WIN_BD_BLEND_ALPHA_1BIT_0_BD_BLEND_WEIGHT0_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WIN_BD_BLEND_ALPHA_1BIT_0_BD_BLEND_WEIGHT0_DEFAULT_MASK _MK_MASK_CONST(0xff) +#define DC_B_WIN_BD_BLEND_ALPHA_1BIT_0_BD_BLEND_WEIGHT0_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WIN_BD_BLEND_ALPHA_1BIT_0_BD_BLEND_WEIGHT0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WIN_BD_BLEND_ALPHA_1BIT_0_BD_BLEND_WEIGHT1_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WIN_BD_BLEND_ALPHA_1BIT_0_BD_BLEND_WEIGHT1_FIELD _MK_FIELD_CONST(0xff, DC_B_WIN_BD_BLEND_ALPHA_1BIT_0_BD_BLEND_WEIGHT1_SHIFT) +#define DC_B_WIN_BD_BLEND_ALPHA_1BIT_0_BD_BLEND_WEIGHT1_RANGE 15:8 +#define DC_B_WIN_BD_BLEND_ALPHA_1BIT_0_BD_BLEND_WEIGHT1_WOFFSET 0x0 +#define DC_B_WIN_BD_BLEND_ALPHA_1BIT_0_BD_BLEND_WEIGHT1_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WIN_BD_BLEND_ALPHA_1BIT_0_BD_BLEND_WEIGHT1_DEFAULT_MASK _MK_MASK_CONST(0xff) +#define DC_B_WIN_BD_BLEND_ALPHA_1BIT_0_BD_BLEND_WEIGHT1_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WIN_BD_BLEND_ALPHA_1BIT_0_BD_BLEND_WEIGHT1_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_B_WINBUF_BD_START_ADDR_0 +#define DC_B_WINBUF_BD_START_ADDR_0 _MK_ADDR_CONST(0xdc0) +#define DC_B_WINBUF_BD_START_ADDR_0_SECURE 0x0 +#define DC_B_WINBUF_BD_START_ADDR_0_WORD_COUNT 0x1 +#define DC_B_WINBUF_BD_START_ADDR_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_START_ADDR_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_START_ADDR_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_START_ADDR_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_START_ADDR_0_READ_MASK _MK_MASK_CONST(0xffffffff) +#define DC_B_WINBUF_BD_START_ADDR_0_WRITE_MASK _MK_MASK_CONST(0xffffffff) +#define DC_B_WINBUF_BD_START_ADDR_0_BD_START_ADDR_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINBUF_BD_START_ADDR_0_BD_START_ADDR_FIELD _MK_FIELD_CONST(0xffffffff, DC_B_WINBUF_BD_START_ADDR_0_BD_START_ADDR_SHIFT) +#define DC_B_WINBUF_BD_START_ADDR_0_BD_START_ADDR_RANGE 31:0 +#define DC_B_WINBUF_BD_START_ADDR_0_BD_START_ADDR_WOFFSET 0x0 +#define DC_B_WINBUF_BD_START_ADDR_0_BD_START_ADDR_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_START_ADDR_0_BD_START_ADDR_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_START_ADDR_0_BD_START_ADDR_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_START_ADDR_0_BD_START_ADDR_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_B_WINBUF_BD_START_ADDR_NS_0 +#define DC_B_WINBUF_BD_START_ADDR_NS_0 _MK_ADDR_CONST(0xdc1) +#define DC_B_WINBUF_BD_START_ADDR_NS_0_SECURE 0x0 +#define DC_B_WINBUF_BD_START_ADDR_NS_0_WORD_COUNT 0x1 +#define DC_B_WINBUF_BD_START_ADDR_NS_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_START_ADDR_NS_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_START_ADDR_NS_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_START_ADDR_NS_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_START_ADDR_NS_0_READ_MASK _MK_MASK_CONST(0xffffffff) +#define DC_B_WINBUF_BD_START_ADDR_NS_0_WRITE_MASK _MK_MASK_CONST(0xffffffff) +#define DC_B_WINBUF_BD_START_ADDR_NS_0_BD_START_ADDR_NS_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINBUF_BD_START_ADDR_NS_0_BD_START_ADDR_NS_FIELD _MK_FIELD_CONST(0xffffffff, DC_B_WINBUF_BD_START_ADDR_NS_0_BD_START_ADDR_NS_SHIFT) +#define DC_B_WINBUF_BD_START_ADDR_NS_0_BD_START_ADDR_NS_RANGE 31:0 +#define DC_B_WINBUF_BD_START_ADDR_NS_0_BD_START_ADDR_NS_WOFFSET 0x0 +#define DC_B_WINBUF_BD_START_ADDR_NS_0_BD_START_ADDR_NS_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_START_ADDR_NS_0_BD_START_ADDR_NS_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_START_ADDR_NS_0_BD_START_ADDR_NS_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_START_ADDR_NS_0_BD_START_ADDR_NS_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_B_WINBUF_BD_START_ADDR_U_0 +#define DC_B_WINBUF_BD_START_ADDR_U_0 _MK_ADDR_CONST(0xdc2) +#define DC_B_WINBUF_BD_START_ADDR_U_0_SECURE 0x0 +#define DC_B_WINBUF_BD_START_ADDR_U_0_WORD_COUNT 0x1 +#define DC_B_WINBUF_BD_START_ADDR_U_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_START_ADDR_U_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_START_ADDR_U_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_START_ADDR_U_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_START_ADDR_U_0_READ_MASK _MK_MASK_CONST(0xffffffff) +#define DC_B_WINBUF_BD_START_ADDR_U_0_WRITE_MASK _MK_MASK_CONST(0xffffffff) +#define DC_B_WINBUF_BD_START_ADDR_U_0_BD_START_ADDR_U_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINBUF_BD_START_ADDR_U_0_BD_START_ADDR_U_FIELD _MK_FIELD_CONST(0xffffffff, DC_B_WINBUF_BD_START_ADDR_U_0_BD_START_ADDR_U_SHIFT) +#define DC_B_WINBUF_BD_START_ADDR_U_0_BD_START_ADDR_U_RANGE 31:0 +#define DC_B_WINBUF_BD_START_ADDR_U_0_BD_START_ADDR_U_WOFFSET 0x0 +#define DC_B_WINBUF_BD_START_ADDR_U_0_BD_START_ADDR_U_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_START_ADDR_U_0_BD_START_ADDR_U_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_START_ADDR_U_0_BD_START_ADDR_U_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_START_ADDR_U_0_BD_START_ADDR_U_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_B_WINBUF_BD_START_ADDR_U_NS_0 +#define DC_B_WINBUF_BD_START_ADDR_U_NS_0 _MK_ADDR_CONST(0xdc3) +#define DC_B_WINBUF_BD_START_ADDR_U_NS_0_SECURE 0x0 +#define DC_B_WINBUF_BD_START_ADDR_U_NS_0_WORD_COUNT 0x1 +#define DC_B_WINBUF_BD_START_ADDR_U_NS_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_START_ADDR_U_NS_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_START_ADDR_U_NS_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_START_ADDR_U_NS_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_START_ADDR_U_NS_0_READ_MASK _MK_MASK_CONST(0xffffffff) +#define DC_B_WINBUF_BD_START_ADDR_U_NS_0_WRITE_MASK _MK_MASK_CONST(0xffffffff) +#define DC_B_WINBUF_BD_START_ADDR_U_NS_0_BD_START_ADDR_U_NS_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINBUF_BD_START_ADDR_U_NS_0_BD_START_ADDR_U_NS_FIELD _MK_FIELD_CONST(0xffffffff, DC_B_WINBUF_BD_START_ADDR_U_NS_0_BD_START_ADDR_U_NS_SHIFT) +#define DC_B_WINBUF_BD_START_ADDR_U_NS_0_BD_START_ADDR_U_NS_RANGE 31:0 +#define DC_B_WINBUF_BD_START_ADDR_U_NS_0_BD_START_ADDR_U_NS_WOFFSET 0x0 +#define DC_B_WINBUF_BD_START_ADDR_U_NS_0_BD_START_ADDR_U_NS_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_START_ADDR_U_NS_0_BD_START_ADDR_U_NS_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_START_ADDR_U_NS_0_BD_START_ADDR_U_NS_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_START_ADDR_U_NS_0_BD_START_ADDR_U_NS_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_B_WINBUF_BD_START_ADDR_V_0 +#define DC_B_WINBUF_BD_START_ADDR_V_0 _MK_ADDR_CONST(0xdc4) +#define DC_B_WINBUF_BD_START_ADDR_V_0_SECURE 0x0 +#define DC_B_WINBUF_BD_START_ADDR_V_0_WORD_COUNT 0x1 +#define DC_B_WINBUF_BD_START_ADDR_V_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_START_ADDR_V_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_START_ADDR_V_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_START_ADDR_V_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_START_ADDR_V_0_READ_MASK _MK_MASK_CONST(0xffffffff) +#define DC_B_WINBUF_BD_START_ADDR_V_0_WRITE_MASK _MK_MASK_CONST(0xffffffff) +#define DC_B_WINBUF_BD_START_ADDR_V_0_BD_START_ADDR_V_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINBUF_BD_START_ADDR_V_0_BD_START_ADDR_V_FIELD _MK_FIELD_CONST(0xffffffff, DC_B_WINBUF_BD_START_ADDR_V_0_BD_START_ADDR_V_SHIFT) +#define DC_B_WINBUF_BD_START_ADDR_V_0_BD_START_ADDR_V_RANGE 31:0 +#define DC_B_WINBUF_BD_START_ADDR_V_0_BD_START_ADDR_V_WOFFSET 0x0 +#define DC_B_WINBUF_BD_START_ADDR_V_0_BD_START_ADDR_V_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_START_ADDR_V_0_BD_START_ADDR_V_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_START_ADDR_V_0_BD_START_ADDR_V_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_START_ADDR_V_0_BD_START_ADDR_V_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_B_WINBUF_BD_START_ADDR_V_NS_0 +#define DC_B_WINBUF_BD_START_ADDR_V_NS_0 _MK_ADDR_CONST(0xdc5) +#define DC_B_WINBUF_BD_START_ADDR_V_NS_0_SECURE 0x0 +#define DC_B_WINBUF_BD_START_ADDR_V_NS_0_WORD_COUNT 0x1 +#define DC_B_WINBUF_BD_START_ADDR_V_NS_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_START_ADDR_V_NS_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_START_ADDR_V_NS_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_START_ADDR_V_NS_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_START_ADDR_V_NS_0_READ_MASK _MK_MASK_CONST(0xffffffff) +#define DC_B_WINBUF_BD_START_ADDR_V_NS_0_WRITE_MASK _MK_MASK_CONST(0xffffffff) +#define DC_B_WINBUF_BD_START_ADDR_V_NS_0_BD_START_ADDR_V_NS_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINBUF_BD_START_ADDR_V_NS_0_BD_START_ADDR_V_NS_FIELD _MK_FIELD_CONST(0xffffffff, DC_B_WINBUF_BD_START_ADDR_V_NS_0_BD_START_ADDR_V_NS_SHIFT) +#define DC_B_WINBUF_BD_START_ADDR_V_NS_0_BD_START_ADDR_V_NS_RANGE 31:0 +#define DC_B_WINBUF_BD_START_ADDR_V_NS_0_BD_START_ADDR_V_NS_WOFFSET 0x0 +#define DC_B_WINBUF_BD_START_ADDR_V_NS_0_BD_START_ADDR_V_NS_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_START_ADDR_V_NS_0_BD_START_ADDR_V_NS_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_START_ADDR_V_NS_0_BD_START_ADDR_V_NS_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_START_ADDR_V_NS_0_BD_START_ADDR_V_NS_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_B_WINBUF_BD_ADDR_H_OFFSET_0 +#define DC_B_WINBUF_BD_ADDR_H_OFFSET_0 _MK_ADDR_CONST(0xdc6) +#define DC_B_WINBUF_BD_ADDR_H_OFFSET_0_SECURE 0x0 +#define DC_B_WINBUF_BD_ADDR_H_OFFSET_0_WORD_COUNT 0x1 +#define DC_B_WINBUF_BD_ADDR_H_OFFSET_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_ADDR_H_OFFSET_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_ADDR_H_OFFSET_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_ADDR_H_OFFSET_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_ADDR_H_OFFSET_0_READ_MASK _MK_MASK_CONST(0xffffffff) +#define DC_B_WINBUF_BD_ADDR_H_OFFSET_0_WRITE_MASK _MK_MASK_CONST(0xffffffff) +#define DC_B_WINBUF_BD_ADDR_H_OFFSET_0_BD_ADDR_H_OFFSET_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINBUF_BD_ADDR_H_OFFSET_0_BD_ADDR_H_OFFSET_FIELD _MK_FIELD_CONST(0xffffffff, DC_B_WINBUF_BD_ADDR_H_OFFSET_0_BD_ADDR_H_OFFSET_SHIFT) +#define DC_B_WINBUF_BD_ADDR_H_OFFSET_0_BD_ADDR_H_OFFSET_RANGE 31:0 +#define DC_B_WINBUF_BD_ADDR_H_OFFSET_0_BD_ADDR_H_OFFSET_WOFFSET 0x0 +#define DC_B_WINBUF_BD_ADDR_H_OFFSET_0_BD_ADDR_H_OFFSET_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_ADDR_H_OFFSET_0_BD_ADDR_H_OFFSET_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_ADDR_H_OFFSET_0_BD_ADDR_H_OFFSET_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_ADDR_H_OFFSET_0_BD_ADDR_H_OFFSET_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_B_WINBUF_BD_ADDR_H_OFFSET_NS_0 +#define DC_B_WINBUF_BD_ADDR_H_OFFSET_NS_0 _MK_ADDR_CONST(0xdc7) +#define DC_B_WINBUF_BD_ADDR_H_OFFSET_NS_0_SECURE 0x0 +#define DC_B_WINBUF_BD_ADDR_H_OFFSET_NS_0_WORD_COUNT 0x1 +#define DC_B_WINBUF_BD_ADDR_H_OFFSET_NS_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_ADDR_H_OFFSET_NS_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_ADDR_H_OFFSET_NS_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_ADDR_H_OFFSET_NS_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_ADDR_H_OFFSET_NS_0_READ_MASK _MK_MASK_CONST(0xffffffff) +#define DC_B_WINBUF_BD_ADDR_H_OFFSET_NS_0_WRITE_MASK _MK_MASK_CONST(0xffffffff) +#define DC_B_WINBUF_BD_ADDR_H_OFFSET_NS_0_BD_ADDR_H_OFFSET_NS_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINBUF_BD_ADDR_H_OFFSET_NS_0_BD_ADDR_H_OFFSET_NS_FIELD _MK_FIELD_CONST(0xffffffff, DC_B_WINBUF_BD_ADDR_H_OFFSET_NS_0_BD_ADDR_H_OFFSET_NS_SHIFT) +#define DC_B_WINBUF_BD_ADDR_H_OFFSET_NS_0_BD_ADDR_H_OFFSET_NS_RANGE 31:0 +#define DC_B_WINBUF_BD_ADDR_H_OFFSET_NS_0_BD_ADDR_H_OFFSET_NS_WOFFSET 0x0 +#define DC_B_WINBUF_BD_ADDR_H_OFFSET_NS_0_BD_ADDR_H_OFFSET_NS_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_ADDR_H_OFFSET_NS_0_BD_ADDR_H_OFFSET_NS_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_ADDR_H_OFFSET_NS_0_BD_ADDR_H_OFFSET_NS_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_ADDR_H_OFFSET_NS_0_BD_ADDR_H_OFFSET_NS_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_B_WINBUF_BD_ADDR_V_OFFSET_0 +#define DC_B_WINBUF_BD_ADDR_V_OFFSET_0 _MK_ADDR_CONST(0xdc8) +#define DC_B_WINBUF_BD_ADDR_V_OFFSET_0_SECURE 0x0 +#define DC_B_WINBUF_BD_ADDR_V_OFFSET_0_WORD_COUNT 0x1 +#define DC_B_WINBUF_BD_ADDR_V_OFFSET_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_ADDR_V_OFFSET_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_ADDR_V_OFFSET_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_ADDR_V_OFFSET_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_ADDR_V_OFFSET_0_READ_MASK _MK_MASK_CONST(0xffffffff) +#define DC_B_WINBUF_BD_ADDR_V_OFFSET_0_WRITE_MASK _MK_MASK_CONST(0xffffffff) +#define DC_B_WINBUF_BD_ADDR_V_OFFSET_0_BD_ADDR_V_OFFSET_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINBUF_BD_ADDR_V_OFFSET_0_BD_ADDR_V_OFFSET_FIELD _MK_FIELD_CONST(0xffffffff, DC_B_WINBUF_BD_ADDR_V_OFFSET_0_BD_ADDR_V_OFFSET_SHIFT) +#define DC_B_WINBUF_BD_ADDR_V_OFFSET_0_BD_ADDR_V_OFFSET_RANGE 31:0 +#define DC_B_WINBUF_BD_ADDR_V_OFFSET_0_BD_ADDR_V_OFFSET_WOFFSET 0x0 +#define DC_B_WINBUF_BD_ADDR_V_OFFSET_0_BD_ADDR_V_OFFSET_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_ADDR_V_OFFSET_0_BD_ADDR_V_OFFSET_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_ADDR_V_OFFSET_0_BD_ADDR_V_OFFSET_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_ADDR_V_OFFSET_0_BD_ADDR_V_OFFSET_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_B_WINBUF_BD_ADDR_V_OFFSET_NS_0 +#define DC_B_WINBUF_BD_ADDR_V_OFFSET_NS_0 _MK_ADDR_CONST(0xdc9) +#define DC_B_WINBUF_BD_ADDR_V_OFFSET_NS_0_SECURE 0x0 +#define DC_B_WINBUF_BD_ADDR_V_OFFSET_NS_0_WORD_COUNT 0x1 +#define DC_B_WINBUF_BD_ADDR_V_OFFSET_NS_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_ADDR_V_OFFSET_NS_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_ADDR_V_OFFSET_NS_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_ADDR_V_OFFSET_NS_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_ADDR_V_OFFSET_NS_0_READ_MASK _MK_MASK_CONST(0xffffffff) +#define DC_B_WINBUF_BD_ADDR_V_OFFSET_NS_0_WRITE_MASK _MK_MASK_CONST(0xffffffff) +#define DC_B_WINBUF_BD_ADDR_V_OFFSET_NS_0_BD_ADDR_V_OFFSET_NS_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINBUF_BD_ADDR_V_OFFSET_NS_0_BD_ADDR_V_OFFSET_NS_FIELD _MK_FIELD_CONST(0xffffffff, DC_B_WINBUF_BD_ADDR_V_OFFSET_NS_0_BD_ADDR_V_OFFSET_NS_SHIFT) +#define DC_B_WINBUF_BD_ADDR_V_OFFSET_NS_0_BD_ADDR_V_OFFSET_NS_RANGE 31:0 +#define DC_B_WINBUF_BD_ADDR_V_OFFSET_NS_0_BD_ADDR_V_OFFSET_NS_WOFFSET 0x0 +#define DC_B_WINBUF_BD_ADDR_V_OFFSET_NS_0_BD_ADDR_V_OFFSET_NS_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_ADDR_V_OFFSET_NS_0_BD_ADDR_V_OFFSET_NS_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_ADDR_V_OFFSET_NS_0_BD_ADDR_V_OFFSET_NS_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_ADDR_V_OFFSET_NS_0_BD_ADDR_V_OFFSET_NS_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_B_WINBUF_BD_UFLOW_STATUS_0 +#define DC_B_WINBUF_BD_UFLOW_STATUS_0 _MK_ADDR_CONST(0xdca) +#define DC_B_WINBUF_BD_UFLOW_STATUS_0_SECURE 0x0 +#define DC_B_WINBUF_BD_UFLOW_STATUS_0_WORD_COUNT 0x1 +#define DC_B_WINBUF_BD_UFLOW_STATUS_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_UFLOW_STATUS_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_UFLOW_STATUS_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_UFLOW_STATUS_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_UFLOW_STATUS_0_READ_MASK _MK_MASK_CONST(0x40ffffff) +#define DC_B_WINBUF_BD_UFLOW_STATUS_0_WRITE_MASK _MK_MASK_CONST(0x40ffffff) +#define DC_B_WINBUF_BD_UFLOW_STATUS_0_UFLOW_COUNT_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINBUF_BD_UFLOW_STATUS_0_UFLOW_COUNT_FIELD _MK_FIELD_CONST(0xffffff, DC_B_WINBUF_BD_UFLOW_STATUS_0_UFLOW_COUNT_SHIFT) +#define DC_B_WINBUF_BD_UFLOW_STATUS_0_UFLOW_COUNT_RANGE 23:0 +#define DC_B_WINBUF_BD_UFLOW_STATUS_0_UFLOW_COUNT_WOFFSET 0x0 +#define DC_B_WINBUF_BD_UFLOW_STATUS_0_UFLOW_COUNT_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_UFLOW_STATUS_0_UFLOW_COUNT_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_UFLOW_STATUS_0_UFLOW_COUNT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_UFLOW_STATUS_0_UFLOW_COUNT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINBUF_BD_UFLOW_STATUS_0_COUNT_OFLOW_SHIFT _MK_SHIFT_CONST(30) +#define DC_B_WINBUF_BD_UFLOW_STATUS_0_COUNT_OFLOW_FIELD _MK_FIELD_CONST(0x1, DC_B_WINBUF_BD_UFLOW_STATUS_0_COUNT_OFLOW_SHIFT) +#define DC_B_WINBUF_BD_UFLOW_STATUS_0_COUNT_OFLOW_RANGE 30:30 +#define DC_B_WINBUF_BD_UFLOW_STATUS_0_COUNT_OFLOW_WOFFSET 0x0 +#define DC_B_WINBUF_BD_UFLOW_STATUS_0_COUNT_OFLOW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_UFLOW_STATUS_0_COUNT_OFLOW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_UFLOW_STATUS_0_COUNT_OFLOW_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_UFLOW_STATUS_0_COUNT_OFLOW_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_B_WINBUF_BD_SURFACE_KIND_0 +#define DC_B_WINBUF_BD_SURFACE_KIND_0 _MK_ADDR_CONST(0xdcb) +#define DC_B_WINBUF_BD_SURFACE_KIND_0_SECURE 0x0 +#define DC_B_WINBUF_BD_SURFACE_KIND_0_WORD_COUNT 0x1 +#define DC_B_WINBUF_BD_SURFACE_KIND_0_RESET_VAL _MK_MASK_CONST(0x10) +#define DC_B_WINBUF_BD_SURFACE_KIND_0_RESET_MASK _MK_MASK_CONST(0x73) +#define DC_B_WINBUF_BD_SURFACE_KIND_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_SURFACE_KIND_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_SURFACE_KIND_0_READ_MASK _MK_MASK_CONST(0x73) +#define DC_B_WINBUF_BD_SURFACE_KIND_0_WRITE_MASK _MK_MASK_CONST(0x73) +#define DC_B_WINBUF_BD_SURFACE_KIND_0_BD_SURFACE_KIND_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINBUF_BD_SURFACE_KIND_0_BD_SURFACE_KIND_FIELD _MK_FIELD_CONST(0x3, DC_B_WINBUF_BD_SURFACE_KIND_0_BD_SURFACE_KIND_SHIFT) +#define DC_B_WINBUF_BD_SURFACE_KIND_0_BD_SURFACE_KIND_RANGE 1:0 +#define DC_B_WINBUF_BD_SURFACE_KIND_0_BD_SURFACE_KIND_WOFFSET 0x0 +#define DC_B_WINBUF_BD_SURFACE_KIND_0_BD_SURFACE_KIND_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_SURFACE_KIND_0_BD_SURFACE_KIND_DEFAULT_MASK _MK_MASK_CONST(0x3) +#define DC_B_WINBUF_BD_SURFACE_KIND_0_BD_SURFACE_KIND_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_SURFACE_KIND_0_BD_SURFACE_KIND_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_SURFACE_KIND_0_BD_SURFACE_KIND_PITCH _MK_ENUM_CONST(0) +#define DC_B_WINBUF_BD_SURFACE_KIND_0_BD_SURFACE_KIND_TILED _MK_ENUM_CONST(1) +#define DC_B_WINBUF_BD_SURFACE_KIND_0_BD_SURFACE_KIND_BL_16B2 _MK_ENUM_CONST(2) + +#define DC_B_WINBUF_BD_SURFACE_KIND_0_BD_BLOCK_HEIGHT_SHIFT _MK_SHIFT_CONST(4) +#define DC_B_WINBUF_BD_SURFACE_KIND_0_BD_BLOCK_HEIGHT_FIELD _MK_FIELD_CONST(0x7, DC_B_WINBUF_BD_SURFACE_KIND_0_BD_BLOCK_HEIGHT_SHIFT) +#define DC_B_WINBUF_BD_SURFACE_KIND_0_BD_BLOCK_HEIGHT_RANGE 6:4 +#define DC_B_WINBUF_BD_SURFACE_KIND_0_BD_BLOCK_HEIGHT_WOFFSET 0x0 +#define DC_B_WINBUF_BD_SURFACE_KIND_0_BD_BLOCK_HEIGHT_DEFAULT _MK_MASK_CONST(0x1) +#define DC_B_WINBUF_BD_SURFACE_KIND_0_BD_BLOCK_HEIGHT_DEFAULT_MASK _MK_MASK_CONST(0x7) +#define DC_B_WINBUF_BD_SURFACE_KIND_0_BD_BLOCK_HEIGHT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_SURFACE_KIND_0_BD_BLOCK_HEIGHT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_SURFACE_KIND_0_BD_BLOCK_HEIGHT_HEIGHT_1 _MK_ENUM_CONST(0) +#define DC_B_WINBUF_BD_SURFACE_KIND_0_BD_BLOCK_HEIGHT_HEIGHT_2 _MK_ENUM_CONST(1) +#define DC_B_WINBUF_BD_SURFACE_KIND_0_BD_BLOCK_HEIGHT_HEIGHT_4 _MK_ENUM_CONST(2) +#define DC_B_WINBUF_BD_SURFACE_KIND_0_BD_BLOCK_HEIGHT_HEIGHT_8 _MK_ENUM_CONST(3) +#define DC_B_WINBUF_BD_SURFACE_KIND_0_BD_BLOCK_HEIGHT_HEIGHT_16 _MK_ENUM_CONST(4) +#define DC_B_WINBUF_BD_SURFACE_KIND_0_BD_BLOCK_HEIGHT_HEIGHT_32 _MK_ENUM_CONST(5) + + +// Register DC_B_WINBUF_BD_SURFACE_WEIGHT_0 +#define DC_B_WINBUF_BD_SURFACE_WEIGHT_0 _MK_ADDR_CONST(0xdcc) +#define DC_B_WINBUF_BD_SURFACE_WEIGHT_0_SECURE 0x0 +#define DC_B_WINBUF_BD_SURFACE_WEIGHT_0_WORD_COUNT 0x1 +#define DC_B_WINBUF_BD_SURFACE_WEIGHT_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_SURFACE_WEIGHT_0_RESET_MASK _MK_MASK_CONST(0x1) +#define DC_B_WINBUF_BD_SURFACE_WEIGHT_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_SURFACE_WEIGHT_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_SURFACE_WEIGHT_0_READ_MASK _MK_MASK_CONST(0x7f) +#define DC_B_WINBUF_BD_SURFACE_WEIGHT_0_WRITE_MASK _MK_MASK_CONST(0x7f) +#define DC_B_WINBUF_BD_SURFACE_WEIGHT_0_BD_SURFACE_WEIGHT_OVERRIDE_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINBUF_BD_SURFACE_WEIGHT_0_BD_SURFACE_WEIGHT_OVERRIDE_FIELD _MK_FIELD_CONST(0x1, DC_B_WINBUF_BD_SURFACE_WEIGHT_0_BD_SURFACE_WEIGHT_OVERRIDE_SHIFT) +#define DC_B_WINBUF_BD_SURFACE_WEIGHT_0_BD_SURFACE_WEIGHT_OVERRIDE_RANGE 0:0 +#define DC_B_WINBUF_BD_SURFACE_WEIGHT_0_BD_SURFACE_WEIGHT_OVERRIDE_WOFFSET 0x0 +#define DC_B_WINBUF_BD_SURFACE_WEIGHT_0_BD_SURFACE_WEIGHT_OVERRIDE_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_SURFACE_WEIGHT_0_BD_SURFACE_WEIGHT_OVERRIDE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_B_WINBUF_BD_SURFACE_WEIGHT_0_BD_SURFACE_WEIGHT_OVERRIDE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_SURFACE_WEIGHT_0_BD_SURFACE_WEIGHT_OVERRIDE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_SURFACE_WEIGHT_0_BD_SURFACE_WEIGHT_OVERRIDE_DISABLE _MK_ENUM_CONST(0) +#define DC_B_WINBUF_BD_SURFACE_WEIGHT_0_BD_SURFACE_WEIGHT_OVERRIDE_ENABLE _MK_ENUM_CONST(1) + +#define DC_B_WINBUF_BD_SURFACE_WEIGHT_0_BD_SURFACE_WEIGHT_Y_SHIFT _MK_SHIFT_CONST(1) +#define DC_B_WINBUF_BD_SURFACE_WEIGHT_0_BD_SURFACE_WEIGHT_Y_FIELD _MK_FIELD_CONST(0x3, DC_B_WINBUF_BD_SURFACE_WEIGHT_0_BD_SURFACE_WEIGHT_Y_SHIFT) +#define DC_B_WINBUF_BD_SURFACE_WEIGHT_0_BD_SURFACE_WEIGHT_Y_RANGE 2:1 +#define DC_B_WINBUF_BD_SURFACE_WEIGHT_0_BD_SURFACE_WEIGHT_Y_WOFFSET 0x0 +#define DC_B_WINBUF_BD_SURFACE_WEIGHT_0_BD_SURFACE_WEIGHT_Y_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_SURFACE_WEIGHT_0_BD_SURFACE_WEIGHT_Y_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_SURFACE_WEIGHT_0_BD_SURFACE_WEIGHT_Y_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_SURFACE_WEIGHT_0_BD_SURFACE_WEIGHT_Y_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_SURFACE_WEIGHT_0_BD_SURFACE_WEIGHT_Y_WEIGHT_2 _MK_ENUM_CONST(0) +#define DC_B_WINBUF_BD_SURFACE_WEIGHT_0_BD_SURFACE_WEIGHT_Y_WEIGHT_4 _MK_ENUM_CONST(1) +#define DC_B_WINBUF_BD_SURFACE_WEIGHT_0_BD_SURFACE_WEIGHT_Y_WEIGHT_8 _MK_ENUM_CONST(2) +#define DC_B_WINBUF_BD_SURFACE_WEIGHT_0_BD_SURFACE_WEIGHT_Y_WEIGHT_16 _MK_ENUM_CONST(3) + +#define DC_B_WINBUF_BD_SURFACE_WEIGHT_0_BD_SURFACE_WEIGHT_U_SHIFT _MK_SHIFT_CONST(3) +#define DC_B_WINBUF_BD_SURFACE_WEIGHT_0_BD_SURFACE_WEIGHT_U_FIELD _MK_FIELD_CONST(0x3, DC_B_WINBUF_BD_SURFACE_WEIGHT_0_BD_SURFACE_WEIGHT_U_SHIFT) +#define DC_B_WINBUF_BD_SURFACE_WEIGHT_0_BD_SURFACE_WEIGHT_U_RANGE 4:3 +#define DC_B_WINBUF_BD_SURFACE_WEIGHT_0_BD_SURFACE_WEIGHT_U_WOFFSET 0x0 +#define DC_B_WINBUF_BD_SURFACE_WEIGHT_0_BD_SURFACE_WEIGHT_U_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_SURFACE_WEIGHT_0_BD_SURFACE_WEIGHT_U_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_SURFACE_WEIGHT_0_BD_SURFACE_WEIGHT_U_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_SURFACE_WEIGHT_0_BD_SURFACE_WEIGHT_U_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_SURFACE_WEIGHT_0_BD_SURFACE_WEIGHT_U_WEIGHT_2 _MK_ENUM_CONST(0) +#define DC_B_WINBUF_BD_SURFACE_WEIGHT_0_BD_SURFACE_WEIGHT_U_WEIGHT_4 _MK_ENUM_CONST(1) +#define DC_B_WINBUF_BD_SURFACE_WEIGHT_0_BD_SURFACE_WEIGHT_U_WEIGHT_8 _MK_ENUM_CONST(2) +#define DC_B_WINBUF_BD_SURFACE_WEIGHT_0_BD_SURFACE_WEIGHT_U_WEIGHT_16 _MK_ENUM_CONST(3) + +#define DC_B_WINBUF_BD_SURFACE_WEIGHT_0_BD_SURFACE_WEIGHT_V_SHIFT _MK_SHIFT_CONST(5) +#define DC_B_WINBUF_BD_SURFACE_WEIGHT_0_BD_SURFACE_WEIGHT_V_FIELD _MK_FIELD_CONST(0x3, DC_B_WINBUF_BD_SURFACE_WEIGHT_0_BD_SURFACE_WEIGHT_V_SHIFT) +#define DC_B_WINBUF_BD_SURFACE_WEIGHT_0_BD_SURFACE_WEIGHT_V_RANGE 6:5 +#define DC_B_WINBUF_BD_SURFACE_WEIGHT_0_BD_SURFACE_WEIGHT_V_WOFFSET 0x0 +#define DC_B_WINBUF_BD_SURFACE_WEIGHT_0_BD_SURFACE_WEIGHT_V_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_SURFACE_WEIGHT_0_BD_SURFACE_WEIGHT_V_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_SURFACE_WEIGHT_0_BD_SURFACE_WEIGHT_V_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_SURFACE_WEIGHT_0_BD_SURFACE_WEIGHT_V_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_SURFACE_WEIGHT_0_BD_SURFACE_WEIGHT_V_WEIGHT_2 _MK_ENUM_CONST(0) +#define DC_B_WINBUF_BD_SURFACE_WEIGHT_0_BD_SURFACE_WEIGHT_V_WEIGHT_4 _MK_ENUM_CONST(1) +#define DC_B_WINBUF_BD_SURFACE_WEIGHT_0_BD_SURFACE_WEIGHT_V_WEIGHT_8 _MK_ENUM_CONST(2) +#define DC_B_WINBUF_BD_SURFACE_WEIGHT_0_BD_SURFACE_WEIGHT_V_WEIGHT_16 _MK_ENUM_CONST(3) + + +// Register DC_B_WINBUF_BD_START_ADDR_HI_0 +#define DC_B_WINBUF_BD_START_ADDR_HI_0 _MK_ADDR_CONST(0xdcd) +#define DC_B_WINBUF_BD_START_ADDR_HI_0_SECURE 0x0 +#define DC_B_WINBUF_BD_START_ADDR_HI_0_WORD_COUNT 0x1 +#define DC_B_WINBUF_BD_START_ADDR_HI_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_START_ADDR_HI_0_RESET_MASK _MK_MASK_CONST(0x3) +#define DC_B_WINBUF_BD_START_ADDR_HI_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_START_ADDR_HI_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_START_ADDR_HI_0_READ_MASK _MK_MASK_CONST(0x3) +#define DC_B_WINBUF_BD_START_ADDR_HI_0_WRITE_MASK _MK_MASK_CONST(0x3) +#define DC_B_WINBUF_BD_START_ADDR_HI_0_BD_START_ADDR_HI_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINBUF_BD_START_ADDR_HI_0_BD_START_ADDR_HI_FIELD _MK_FIELD_CONST(0x3, DC_B_WINBUF_BD_START_ADDR_HI_0_BD_START_ADDR_HI_SHIFT) +#define DC_B_WINBUF_BD_START_ADDR_HI_0_BD_START_ADDR_HI_RANGE 1:0 +#define DC_B_WINBUF_BD_START_ADDR_HI_0_BD_START_ADDR_HI_WOFFSET 0x0 +#define DC_B_WINBUF_BD_START_ADDR_HI_0_BD_START_ADDR_HI_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_START_ADDR_HI_0_BD_START_ADDR_HI_DEFAULT_MASK _MK_MASK_CONST(0x3) +#define DC_B_WINBUF_BD_START_ADDR_HI_0_BD_START_ADDR_HI_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_START_ADDR_HI_0_BD_START_ADDR_HI_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_B_WINBUF_BD_START_ADDR_HI_NS_0 +#define DC_B_WINBUF_BD_START_ADDR_HI_NS_0 _MK_ADDR_CONST(0xdce) +#define DC_B_WINBUF_BD_START_ADDR_HI_NS_0_SECURE 0x0 +#define DC_B_WINBUF_BD_START_ADDR_HI_NS_0_WORD_COUNT 0x1 +#define DC_B_WINBUF_BD_START_ADDR_HI_NS_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_START_ADDR_HI_NS_0_RESET_MASK _MK_MASK_CONST(0x3) +#define DC_B_WINBUF_BD_START_ADDR_HI_NS_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_START_ADDR_HI_NS_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_START_ADDR_HI_NS_0_READ_MASK _MK_MASK_CONST(0x3) +#define DC_B_WINBUF_BD_START_ADDR_HI_NS_0_WRITE_MASK _MK_MASK_CONST(0x3) +#define DC_B_WINBUF_BD_START_ADDR_HI_NS_0_BD_START_ADDR_HI_NS_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINBUF_BD_START_ADDR_HI_NS_0_BD_START_ADDR_HI_NS_FIELD _MK_FIELD_CONST(0x3, DC_B_WINBUF_BD_START_ADDR_HI_NS_0_BD_START_ADDR_HI_NS_SHIFT) +#define DC_B_WINBUF_BD_START_ADDR_HI_NS_0_BD_START_ADDR_HI_NS_RANGE 1:0 +#define DC_B_WINBUF_BD_START_ADDR_HI_NS_0_BD_START_ADDR_HI_NS_WOFFSET 0x0 +#define DC_B_WINBUF_BD_START_ADDR_HI_NS_0_BD_START_ADDR_HI_NS_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_START_ADDR_HI_NS_0_BD_START_ADDR_HI_NS_DEFAULT_MASK _MK_MASK_CONST(0x3) +#define DC_B_WINBUF_BD_START_ADDR_HI_NS_0_BD_START_ADDR_HI_NS_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_START_ADDR_HI_NS_0_BD_START_ADDR_HI_NS_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_B_WINBUF_BD_START_ADDR_HI_U_0 +#define DC_B_WINBUF_BD_START_ADDR_HI_U_0 _MK_ADDR_CONST(0xdcf) +#define DC_B_WINBUF_BD_START_ADDR_HI_U_0_SECURE 0x0 +#define DC_B_WINBUF_BD_START_ADDR_HI_U_0_WORD_COUNT 0x1 +#define DC_B_WINBUF_BD_START_ADDR_HI_U_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_START_ADDR_HI_U_0_RESET_MASK _MK_MASK_CONST(0x3) +#define DC_B_WINBUF_BD_START_ADDR_HI_U_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_START_ADDR_HI_U_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_START_ADDR_HI_U_0_READ_MASK _MK_MASK_CONST(0x3) +#define DC_B_WINBUF_BD_START_ADDR_HI_U_0_WRITE_MASK _MK_MASK_CONST(0x3) +#define DC_B_WINBUF_BD_START_ADDR_HI_U_0_BD_START_ADDR_HI_U_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINBUF_BD_START_ADDR_HI_U_0_BD_START_ADDR_HI_U_FIELD _MK_FIELD_CONST(0x3, DC_B_WINBUF_BD_START_ADDR_HI_U_0_BD_START_ADDR_HI_U_SHIFT) +#define DC_B_WINBUF_BD_START_ADDR_HI_U_0_BD_START_ADDR_HI_U_RANGE 1:0 +#define DC_B_WINBUF_BD_START_ADDR_HI_U_0_BD_START_ADDR_HI_U_WOFFSET 0x0 +#define DC_B_WINBUF_BD_START_ADDR_HI_U_0_BD_START_ADDR_HI_U_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_START_ADDR_HI_U_0_BD_START_ADDR_HI_U_DEFAULT_MASK _MK_MASK_CONST(0x3) +#define DC_B_WINBUF_BD_START_ADDR_HI_U_0_BD_START_ADDR_HI_U_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_START_ADDR_HI_U_0_BD_START_ADDR_HI_U_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_B_WINBUF_BD_START_ADDR_HI_U_NS_0 +#define DC_B_WINBUF_BD_START_ADDR_HI_U_NS_0 _MK_ADDR_CONST(0xdd0) +#define DC_B_WINBUF_BD_START_ADDR_HI_U_NS_0_SECURE 0x0 +#define DC_B_WINBUF_BD_START_ADDR_HI_U_NS_0_WORD_COUNT 0x1 +#define DC_B_WINBUF_BD_START_ADDR_HI_U_NS_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_START_ADDR_HI_U_NS_0_RESET_MASK _MK_MASK_CONST(0x3) +#define DC_B_WINBUF_BD_START_ADDR_HI_U_NS_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_START_ADDR_HI_U_NS_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_START_ADDR_HI_U_NS_0_READ_MASK _MK_MASK_CONST(0x3) +#define DC_B_WINBUF_BD_START_ADDR_HI_U_NS_0_WRITE_MASK _MK_MASK_CONST(0x3) +#define DC_B_WINBUF_BD_START_ADDR_HI_U_NS_0_BD_START_ADDR_HI_U_NS_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINBUF_BD_START_ADDR_HI_U_NS_0_BD_START_ADDR_HI_U_NS_FIELD _MK_FIELD_CONST(0x3, DC_B_WINBUF_BD_START_ADDR_HI_U_NS_0_BD_START_ADDR_HI_U_NS_SHIFT) +#define DC_B_WINBUF_BD_START_ADDR_HI_U_NS_0_BD_START_ADDR_HI_U_NS_RANGE 1:0 +#define DC_B_WINBUF_BD_START_ADDR_HI_U_NS_0_BD_START_ADDR_HI_U_NS_WOFFSET 0x0 +#define DC_B_WINBUF_BD_START_ADDR_HI_U_NS_0_BD_START_ADDR_HI_U_NS_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_START_ADDR_HI_U_NS_0_BD_START_ADDR_HI_U_NS_DEFAULT_MASK _MK_MASK_CONST(0x3) +#define DC_B_WINBUF_BD_START_ADDR_HI_U_NS_0_BD_START_ADDR_HI_U_NS_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_START_ADDR_HI_U_NS_0_BD_START_ADDR_HI_U_NS_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_B_WINBUF_BD_START_ADDR_HI_V_0 +#define DC_B_WINBUF_BD_START_ADDR_HI_V_0 _MK_ADDR_CONST(0xdd1) +#define DC_B_WINBUF_BD_START_ADDR_HI_V_0_SECURE 0x0 +#define DC_B_WINBUF_BD_START_ADDR_HI_V_0_WORD_COUNT 0x1 +#define DC_B_WINBUF_BD_START_ADDR_HI_V_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_START_ADDR_HI_V_0_RESET_MASK _MK_MASK_CONST(0x3) +#define DC_B_WINBUF_BD_START_ADDR_HI_V_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_START_ADDR_HI_V_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_START_ADDR_HI_V_0_READ_MASK _MK_MASK_CONST(0x3) +#define DC_B_WINBUF_BD_START_ADDR_HI_V_0_WRITE_MASK _MK_MASK_CONST(0x3) +#define DC_B_WINBUF_BD_START_ADDR_HI_V_0_BD_START_ADDR_HI_V_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINBUF_BD_START_ADDR_HI_V_0_BD_START_ADDR_HI_V_FIELD _MK_FIELD_CONST(0x3, DC_B_WINBUF_BD_START_ADDR_HI_V_0_BD_START_ADDR_HI_V_SHIFT) +#define DC_B_WINBUF_BD_START_ADDR_HI_V_0_BD_START_ADDR_HI_V_RANGE 1:0 +#define DC_B_WINBUF_BD_START_ADDR_HI_V_0_BD_START_ADDR_HI_V_WOFFSET 0x0 +#define DC_B_WINBUF_BD_START_ADDR_HI_V_0_BD_START_ADDR_HI_V_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_START_ADDR_HI_V_0_BD_START_ADDR_HI_V_DEFAULT_MASK _MK_MASK_CONST(0x3) +#define DC_B_WINBUF_BD_START_ADDR_HI_V_0_BD_START_ADDR_HI_V_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_START_ADDR_HI_V_0_BD_START_ADDR_HI_V_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_B_WINBUF_BD_START_ADDR_HI_V_NS_0 +#define DC_B_WINBUF_BD_START_ADDR_HI_V_NS_0 _MK_ADDR_CONST(0xdd2) +#define DC_B_WINBUF_BD_START_ADDR_HI_V_NS_0_SECURE 0x0 +#define DC_B_WINBUF_BD_START_ADDR_HI_V_NS_0_WORD_COUNT 0x1 +#define DC_B_WINBUF_BD_START_ADDR_HI_V_NS_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_START_ADDR_HI_V_NS_0_RESET_MASK _MK_MASK_CONST(0x3) +#define DC_B_WINBUF_BD_START_ADDR_HI_V_NS_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_START_ADDR_HI_V_NS_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_START_ADDR_HI_V_NS_0_READ_MASK _MK_MASK_CONST(0x3) +#define DC_B_WINBUF_BD_START_ADDR_HI_V_NS_0_WRITE_MASK _MK_MASK_CONST(0x3) +#define DC_B_WINBUF_BD_START_ADDR_HI_V_NS_0_BD_START_ADDR_HI_V_NS_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINBUF_BD_START_ADDR_HI_V_NS_0_BD_START_ADDR_HI_V_NS_FIELD _MK_FIELD_CONST(0x3, DC_B_WINBUF_BD_START_ADDR_HI_V_NS_0_BD_START_ADDR_HI_V_NS_SHIFT) +#define DC_B_WINBUF_BD_START_ADDR_HI_V_NS_0_BD_START_ADDR_HI_V_NS_RANGE 1:0 +#define DC_B_WINBUF_BD_START_ADDR_HI_V_NS_0_BD_START_ADDR_HI_V_NS_WOFFSET 0x0 +#define DC_B_WINBUF_BD_START_ADDR_HI_V_NS_0_BD_START_ADDR_HI_V_NS_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_START_ADDR_HI_V_NS_0_BD_START_ADDR_HI_V_NS_DEFAULT_MASK _MK_MASK_CONST(0x3) +#define DC_B_WINBUF_BD_START_ADDR_HI_V_NS_0_BD_START_ADDR_HI_V_NS_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_START_ADDR_HI_V_NS_0_BD_START_ADDR_HI_V_NS_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_B_WINBUF_BD_START_ADDR_FIELD2_0 +#define DC_B_WINBUF_BD_START_ADDR_FIELD2_0 _MK_ADDR_CONST(0xdd3) +#define DC_B_WINBUF_BD_START_ADDR_FIELD2_0_SECURE 0x0 +#define DC_B_WINBUF_BD_START_ADDR_FIELD2_0_WORD_COUNT 0x1 +#define DC_B_WINBUF_BD_START_ADDR_FIELD2_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_START_ADDR_FIELD2_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_START_ADDR_FIELD2_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_START_ADDR_FIELD2_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_START_ADDR_FIELD2_0_READ_MASK _MK_MASK_CONST(0xffffffff) +#define DC_B_WINBUF_BD_START_ADDR_FIELD2_0_WRITE_MASK _MK_MASK_CONST(0xffffffff) +#define DC_B_WINBUF_BD_START_ADDR_FIELD2_0_BD_START_ADDR_FIELD2_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINBUF_BD_START_ADDR_FIELD2_0_BD_START_ADDR_FIELD2_FIELD _MK_FIELD_CONST(0xffffffff, DC_B_WINBUF_BD_START_ADDR_FIELD2_0_BD_START_ADDR_FIELD2_SHIFT) +#define DC_B_WINBUF_BD_START_ADDR_FIELD2_0_BD_START_ADDR_FIELD2_RANGE 31:0 +#define DC_B_WINBUF_BD_START_ADDR_FIELD2_0_BD_START_ADDR_FIELD2_WOFFSET 0x0 +#define DC_B_WINBUF_BD_START_ADDR_FIELD2_0_BD_START_ADDR_FIELD2_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_START_ADDR_FIELD2_0_BD_START_ADDR_FIELD2_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_START_ADDR_FIELD2_0_BD_START_ADDR_FIELD2_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_START_ADDR_FIELD2_0_BD_START_ADDR_FIELD2_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_B_WINBUF_BD_START_ADDR_FIELD2_NS_0 +#define DC_B_WINBUF_BD_START_ADDR_FIELD2_NS_0 _MK_ADDR_CONST(0xdd4) +#define DC_B_WINBUF_BD_START_ADDR_FIELD2_NS_0_SECURE 0x0 +#define DC_B_WINBUF_BD_START_ADDR_FIELD2_NS_0_WORD_COUNT 0x1 +#define DC_B_WINBUF_BD_START_ADDR_FIELD2_NS_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_START_ADDR_FIELD2_NS_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_START_ADDR_FIELD2_NS_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_START_ADDR_FIELD2_NS_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_START_ADDR_FIELD2_NS_0_READ_MASK _MK_MASK_CONST(0xffffffff) +#define DC_B_WINBUF_BD_START_ADDR_FIELD2_NS_0_WRITE_MASK _MK_MASK_CONST(0xffffffff) +#define DC_B_WINBUF_BD_START_ADDR_FIELD2_NS_0_BD_START_ADDR_FIELD2_NS_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINBUF_BD_START_ADDR_FIELD2_NS_0_BD_START_ADDR_FIELD2_NS_FIELD _MK_FIELD_CONST(0xffffffff, DC_B_WINBUF_BD_START_ADDR_FIELD2_NS_0_BD_START_ADDR_FIELD2_NS_SHIFT) +#define DC_B_WINBUF_BD_START_ADDR_FIELD2_NS_0_BD_START_ADDR_FIELD2_NS_RANGE 31:0 +#define DC_B_WINBUF_BD_START_ADDR_FIELD2_NS_0_BD_START_ADDR_FIELD2_NS_WOFFSET 0x0 +#define DC_B_WINBUF_BD_START_ADDR_FIELD2_NS_0_BD_START_ADDR_FIELD2_NS_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_START_ADDR_FIELD2_NS_0_BD_START_ADDR_FIELD2_NS_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_START_ADDR_FIELD2_NS_0_BD_START_ADDR_FIELD2_NS_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_START_ADDR_FIELD2_NS_0_BD_START_ADDR_FIELD2_NS_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_B_WINBUF_BD_START_ADDR_FIELD2_U_0 +#define DC_B_WINBUF_BD_START_ADDR_FIELD2_U_0 _MK_ADDR_CONST(0xdd5) +#define DC_B_WINBUF_BD_START_ADDR_FIELD2_U_0_SECURE 0x0 +#define DC_B_WINBUF_BD_START_ADDR_FIELD2_U_0_WORD_COUNT 0x1 +#define DC_B_WINBUF_BD_START_ADDR_FIELD2_U_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_START_ADDR_FIELD2_U_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_START_ADDR_FIELD2_U_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_START_ADDR_FIELD2_U_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_START_ADDR_FIELD2_U_0_READ_MASK _MK_MASK_CONST(0xffffffff) +#define DC_B_WINBUF_BD_START_ADDR_FIELD2_U_0_WRITE_MASK _MK_MASK_CONST(0xffffffff) +#define DC_B_WINBUF_BD_START_ADDR_FIELD2_U_0_BD_START_ADDR_FIELD2_U_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINBUF_BD_START_ADDR_FIELD2_U_0_BD_START_ADDR_FIELD2_U_FIELD _MK_FIELD_CONST(0xffffffff, DC_B_WINBUF_BD_START_ADDR_FIELD2_U_0_BD_START_ADDR_FIELD2_U_SHIFT) +#define DC_B_WINBUF_BD_START_ADDR_FIELD2_U_0_BD_START_ADDR_FIELD2_U_RANGE 31:0 +#define DC_B_WINBUF_BD_START_ADDR_FIELD2_U_0_BD_START_ADDR_FIELD2_U_WOFFSET 0x0 +#define DC_B_WINBUF_BD_START_ADDR_FIELD2_U_0_BD_START_ADDR_FIELD2_U_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_START_ADDR_FIELD2_U_0_BD_START_ADDR_FIELD2_U_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_START_ADDR_FIELD2_U_0_BD_START_ADDR_FIELD2_U_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_START_ADDR_FIELD2_U_0_BD_START_ADDR_FIELD2_U_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_B_WINBUF_BD_START_ADDR_FIELD2_U_NS_0 +#define DC_B_WINBUF_BD_START_ADDR_FIELD2_U_NS_0 _MK_ADDR_CONST(0xdd6) +#define DC_B_WINBUF_BD_START_ADDR_FIELD2_U_NS_0_SECURE 0x0 +#define DC_B_WINBUF_BD_START_ADDR_FIELD2_U_NS_0_WORD_COUNT 0x1 +#define DC_B_WINBUF_BD_START_ADDR_FIELD2_U_NS_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_START_ADDR_FIELD2_U_NS_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_START_ADDR_FIELD2_U_NS_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_START_ADDR_FIELD2_U_NS_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_START_ADDR_FIELD2_U_NS_0_READ_MASK _MK_MASK_CONST(0xffffffff) +#define DC_B_WINBUF_BD_START_ADDR_FIELD2_U_NS_0_WRITE_MASK _MK_MASK_CONST(0xffffffff) +#define DC_B_WINBUF_BD_START_ADDR_FIELD2_U_NS_0_BD_START_ADDR_FIELD2_U_NS_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINBUF_BD_START_ADDR_FIELD2_U_NS_0_BD_START_ADDR_FIELD2_U_NS_FIELD _MK_FIELD_CONST(0xffffffff, DC_B_WINBUF_BD_START_ADDR_FIELD2_U_NS_0_BD_START_ADDR_FIELD2_U_NS_SHIFT) +#define DC_B_WINBUF_BD_START_ADDR_FIELD2_U_NS_0_BD_START_ADDR_FIELD2_U_NS_RANGE 31:0 +#define DC_B_WINBUF_BD_START_ADDR_FIELD2_U_NS_0_BD_START_ADDR_FIELD2_U_NS_WOFFSET 0x0 +#define DC_B_WINBUF_BD_START_ADDR_FIELD2_U_NS_0_BD_START_ADDR_FIELD2_U_NS_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_START_ADDR_FIELD2_U_NS_0_BD_START_ADDR_FIELD2_U_NS_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_START_ADDR_FIELD2_U_NS_0_BD_START_ADDR_FIELD2_U_NS_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_START_ADDR_FIELD2_U_NS_0_BD_START_ADDR_FIELD2_U_NS_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_B_WINBUF_BD_START_ADDR_FIELD2_V_0 +#define DC_B_WINBUF_BD_START_ADDR_FIELD2_V_0 _MK_ADDR_CONST(0xdd7) +#define DC_B_WINBUF_BD_START_ADDR_FIELD2_V_0_SECURE 0x0 +#define DC_B_WINBUF_BD_START_ADDR_FIELD2_V_0_WORD_COUNT 0x1 +#define DC_B_WINBUF_BD_START_ADDR_FIELD2_V_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_START_ADDR_FIELD2_V_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_START_ADDR_FIELD2_V_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_START_ADDR_FIELD2_V_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_START_ADDR_FIELD2_V_0_READ_MASK _MK_MASK_CONST(0xffffffff) +#define DC_B_WINBUF_BD_START_ADDR_FIELD2_V_0_WRITE_MASK _MK_MASK_CONST(0xffffffff) +#define DC_B_WINBUF_BD_START_ADDR_FIELD2_V_0_BD_START_ADDR_FIELD2_V_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINBUF_BD_START_ADDR_FIELD2_V_0_BD_START_ADDR_FIELD2_V_FIELD _MK_FIELD_CONST(0xffffffff, DC_B_WINBUF_BD_START_ADDR_FIELD2_V_0_BD_START_ADDR_FIELD2_V_SHIFT) +#define DC_B_WINBUF_BD_START_ADDR_FIELD2_V_0_BD_START_ADDR_FIELD2_V_RANGE 31:0 +#define DC_B_WINBUF_BD_START_ADDR_FIELD2_V_0_BD_START_ADDR_FIELD2_V_WOFFSET 0x0 +#define DC_B_WINBUF_BD_START_ADDR_FIELD2_V_0_BD_START_ADDR_FIELD2_V_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_START_ADDR_FIELD2_V_0_BD_START_ADDR_FIELD2_V_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_START_ADDR_FIELD2_V_0_BD_START_ADDR_FIELD2_V_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_START_ADDR_FIELD2_V_0_BD_START_ADDR_FIELD2_V_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_B_WINBUF_BD_START_ADDR_FIELD2_V_NS_0 +#define DC_B_WINBUF_BD_START_ADDR_FIELD2_V_NS_0 _MK_ADDR_CONST(0xdd8) +#define DC_B_WINBUF_BD_START_ADDR_FIELD2_V_NS_0_SECURE 0x0 +#define DC_B_WINBUF_BD_START_ADDR_FIELD2_V_NS_0_WORD_COUNT 0x1 +#define DC_B_WINBUF_BD_START_ADDR_FIELD2_V_NS_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_START_ADDR_FIELD2_V_NS_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_START_ADDR_FIELD2_V_NS_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_START_ADDR_FIELD2_V_NS_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_START_ADDR_FIELD2_V_NS_0_READ_MASK _MK_MASK_CONST(0xffffffff) +#define DC_B_WINBUF_BD_START_ADDR_FIELD2_V_NS_0_WRITE_MASK _MK_MASK_CONST(0xffffffff) +#define DC_B_WINBUF_BD_START_ADDR_FIELD2_V_NS_0_BD_START_ADDR_FIELD2_V_NS_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINBUF_BD_START_ADDR_FIELD2_V_NS_0_BD_START_ADDR_FIELD2_V_NS_FIELD _MK_FIELD_CONST(0xffffffff, DC_B_WINBUF_BD_START_ADDR_FIELD2_V_NS_0_BD_START_ADDR_FIELD2_V_NS_SHIFT) +#define DC_B_WINBUF_BD_START_ADDR_FIELD2_V_NS_0_BD_START_ADDR_FIELD2_V_NS_RANGE 31:0 +#define DC_B_WINBUF_BD_START_ADDR_FIELD2_V_NS_0_BD_START_ADDR_FIELD2_V_NS_WOFFSET 0x0 +#define DC_B_WINBUF_BD_START_ADDR_FIELD2_V_NS_0_BD_START_ADDR_FIELD2_V_NS_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_START_ADDR_FIELD2_V_NS_0_BD_START_ADDR_FIELD2_V_NS_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_START_ADDR_FIELD2_V_NS_0_BD_START_ADDR_FIELD2_V_NS_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_START_ADDR_FIELD2_V_NS_0_BD_START_ADDR_FIELD2_V_NS_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_B_WINBUF_BD_START_ADDR_FIELD2_HI_0 +#define DC_B_WINBUF_BD_START_ADDR_FIELD2_HI_0 _MK_ADDR_CONST(0xdd9) +#define DC_B_WINBUF_BD_START_ADDR_FIELD2_HI_0_SECURE 0x0 +#define DC_B_WINBUF_BD_START_ADDR_FIELD2_HI_0_WORD_COUNT 0x1 +#define DC_B_WINBUF_BD_START_ADDR_FIELD2_HI_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_START_ADDR_FIELD2_HI_0_RESET_MASK _MK_MASK_CONST(0x3) +#define DC_B_WINBUF_BD_START_ADDR_FIELD2_HI_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_START_ADDR_FIELD2_HI_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_START_ADDR_FIELD2_HI_0_READ_MASK _MK_MASK_CONST(0x3) +#define DC_B_WINBUF_BD_START_ADDR_FIELD2_HI_0_WRITE_MASK _MK_MASK_CONST(0x3) +#define DC_B_WINBUF_BD_START_ADDR_FIELD2_HI_0_BD_START_ADDR_FIELD2_HI_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINBUF_BD_START_ADDR_FIELD2_HI_0_BD_START_ADDR_FIELD2_HI_FIELD _MK_FIELD_CONST(0x3, DC_B_WINBUF_BD_START_ADDR_FIELD2_HI_0_BD_START_ADDR_FIELD2_HI_SHIFT) +#define DC_B_WINBUF_BD_START_ADDR_FIELD2_HI_0_BD_START_ADDR_FIELD2_HI_RANGE 1:0 +#define DC_B_WINBUF_BD_START_ADDR_FIELD2_HI_0_BD_START_ADDR_FIELD2_HI_WOFFSET 0x0 +#define DC_B_WINBUF_BD_START_ADDR_FIELD2_HI_0_BD_START_ADDR_FIELD2_HI_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_START_ADDR_FIELD2_HI_0_BD_START_ADDR_FIELD2_HI_DEFAULT_MASK _MK_MASK_CONST(0x3) +#define DC_B_WINBUF_BD_START_ADDR_FIELD2_HI_0_BD_START_ADDR_FIELD2_HI_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_START_ADDR_FIELD2_HI_0_BD_START_ADDR_FIELD2_HI_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_B_WINBUF_BD_START_ADDR_FIELD2_HI_NS_0 +#define DC_B_WINBUF_BD_START_ADDR_FIELD2_HI_NS_0 _MK_ADDR_CONST(0xdda) +#define DC_B_WINBUF_BD_START_ADDR_FIELD2_HI_NS_0_SECURE 0x0 +#define DC_B_WINBUF_BD_START_ADDR_FIELD2_HI_NS_0_WORD_COUNT 0x1 +#define DC_B_WINBUF_BD_START_ADDR_FIELD2_HI_NS_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_START_ADDR_FIELD2_HI_NS_0_RESET_MASK _MK_MASK_CONST(0x3) +#define DC_B_WINBUF_BD_START_ADDR_FIELD2_HI_NS_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_START_ADDR_FIELD2_HI_NS_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_START_ADDR_FIELD2_HI_NS_0_READ_MASK _MK_MASK_CONST(0x3) +#define DC_B_WINBUF_BD_START_ADDR_FIELD2_HI_NS_0_WRITE_MASK _MK_MASK_CONST(0x3) +#define DC_B_WINBUF_BD_START_ADDR_FIELD2_HI_NS_0_BD_START_ADDR_FIELD2_HI_NS_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINBUF_BD_START_ADDR_FIELD2_HI_NS_0_BD_START_ADDR_FIELD2_HI_NS_FIELD _MK_FIELD_CONST(0x3, DC_B_WINBUF_BD_START_ADDR_FIELD2_HI_NS_0_BD_START_ADDR_FIELD2_HI_NS_SHIFT) +#define DC_B_WINBUF_BD_START_ADDR_FIELD2_HI_NS_0_BD_START_ADDR_FIELD2_HI_NS_RANGE 1:0 +#define DC_B_WINBUF_BD_START_ADDR_FIELD2_HI_NS_0_BD_START_ADDR_FIELD2_HI_NS_WOFFSET 0x0 +#define DC_B_WINBUF_BD_START_ADDR_FIELD2_HI_NS_0_BD_START_ADDR_FIELD2_HI_NS_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_START_ADDR_FIELD2_HI_NS_0_BD_START_ADDR_FIELD2_HI_NS_DEFAULT_MASK _MK_MASK_CONST(0x3) +#define DC_B_WINBUF_BD_START_ADDR_FIELD2_HI_NS_0_BD_START_ADDR_FIELD2_HI_NS_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_START_ADDR_FIELD2_HI_NS_0_BD_START_ADDR_FIELD2_HI_NS_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_B_WINBUF_BD_START_ADDR_FIELD2_HI_U_0 +#define DC_B_WINBUF_BD_START_ADDR_FIELD2_HI_U_0 _MK_ADDR_CONST(0xddb) +#define DC_B_WINBUF_BD_START_ADDR_FIELD2_HI_U_0_SECURE 0x0 +#define DC_B_WINBUF_BD_START_ADDR_FIELD2_HI_U_0_WORD_COUNT 0x1 +#define DC_B_WINBUF_BD_START_ADDR_FIELD2_HI_U_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_START_ADDR_FIELD2_HI_U_0_RESET_MASK _MK_MASK_CONST(0x3) +#define DC_B_WINBUF_BD_START_ADDR_FIELD2_HI_U_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_START_ADDR_FIELD2_HI_U_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_START_ADDR_FIELD2_HI_U_0_READ_MASK _MK_MASK_CONST(0x3) +#define DC_B_WINBUF_BD_START_ADDR_FIELD2_HI_U_0_WRITE_MASK _MK_MASK_CONST(0x3) +#define DC_B_WINBUF_BD_START_ADDR_FIELD2_HI_U_0_BD_START_ADDR_FIELD2_HI_U_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINBUF_BD_START_ADDR_FIELD2_HI_U_0_BD_START_ADDR_FIELD2_HI_U_FIELD _MK_FIELD_CONST(0x3, DC_B_WINBUF_BD_START_ADDR_FIELD2_HI_U_0_BD_START_ADDR_FIELD2_HI_U_SHIFT) +#define DC_B_WINBUF_BD_START_ADDR_FIELD2_HI_U_0_BD_START_ADDR_FIELD2_HI_U_RANGE 1:0 +#define DC_B_WINBUF_BD_START_ADDR_FIELD2_HI_U_0_BD_START_ADDR_FIELD2_HI_U_WOFFSET 0x0 +#define DC_B_WINBUF_BD_START_ADDR_FIELD2_HI_U_0_BD_START_ADDR_FIELD2_HI_U_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_START_ADDR_FIELD2_HI_U_0_BD_START_ADDR_FIELD2_HI_U_DEFAULT_MASK _MK_MASK_CONST(0x3) +#define DC_B_WINBUF_BD_START_ADDR_FIELD2_HI_U_0_BD_START_ADDR_FIELD2_HI_U_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_START_ADDR_FIELD2_HI_U_0_BD_START_ADDR_FIELD2_HI_U_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_B_WINBUF_BD_START_ADDR_FIELD2_HI_U_NS_0 +#define DC_B_WINBUF_BD_START_ADDR_FIELD2_HI_U_NS_0 _MK_ADDR_CONST(0xddc) +#define DC_B_WINBUF_BD_START_ADDR_FIELD2_HI_U_NS_0_SECURE 0x0 +#define DC_B_WINBUF_BD_START_ADDR_FIELD2_HI_U_NS_0_WORD_COUNT 0x1 +#define DC_B_WINBUF_BD_START_ADDR_FIELD2_HI_U_NS_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_START_ADDR_FIELD2_HI_U_NS_0_RESET_MASK _MK_MASK_CONST(0x3) +#define DC_B_WINBUF_BD_START_ADDR_FIELD2_HI_U_NS_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_START_ADDR_FIELD2_HI_U_NS_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_START_ADDR_FIELD2_HI_U_NS_0_READ_MASK _MK_MASK_CONST(0x3) +#define DC_B_WINBUF_BD_START_ADDR_FIELD2_HI_U_NS_0_WRITE_MASK _MK_MASK_CONST(0x3) +#define DC_B_WINBUF_BD_START_ADDR_FIELD2_HI_U_NS_0_BD_START_ADDR_FIELD2_HI_U_NS_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINBUF_BD_START_ADDR_FIELD2_HI_U_NS_0_BD_START_ADDR_FIELD2_HI_U_NS_FIELD _MK_FIELD_CONST(0x3, DC_B_WINBUF_BD_START_ADDR_FIELD2_HI_U_NS_0_BD_START_ADDR_FIELD2_HI_U_NS_SHIFT) +#define DC_B_WINBUF_BD_START_ADDR_FIELD2_HI_U_NS_0_BD_START_ADDR_FIELD2_HI_U_NS_RANGE 1:0 +#define DC_B_WINBUF_BD_START_ADDR_FIELD2_HI_U_NS_0_BD_START_ADDR_FIELD2_HI_U_NS_WOFFSET 0x0 +#define DC_B_WINBUF_BD_START_ADDR_FIELD2_HI_U_NS_0_BD_START_ADDR_FIELD2_HI_U_NS_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_START_ADDR_FIELD2_HI_U_NS_0_BD_START_ADDR_FIELD2_HI_U_NS_DEFAULT_MASK _MK_MASK_CONST(0x3) +#define DC_B_WINBUF_BD_START_ADDR_FIELD2_HI_U_NS_0_BD_START_ADDR_FIELD2_HI_U_NS_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_START_ADDR_FIELD2_HI_U_NS_0_BD_START_ADDR_FIELD2_HI_U_NS_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_B_WINBUF_BD_START_ADDR_FIELD2_HI_V_0 +#define DC_B_WINBUF_BD_START_ADDR_FIELD2_HI_V_0 _MK_ADDR_CONST(0xddd) +#define DC_B_WINBUF_BD_START_ADDR_FIELD2_HI_V_0_SECURE 0x0 +#define DC_B_WINBUF_BD_START_ADDR_FIELD2_HI_V_0_WORD_COUNT 0x1 +#define DC_B_WINBUF_BD_START_ADDR_FIELD2_HI_V_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_START_ADDR_FIELD2_HI_V_0_RESET_MASK _MK_MASK_CONST(0x3) +#define DC_B_WINBUF_BD_START_ADDR_FIELD2_HI_V_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_START_ADDR_FIELD2_HI_V_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_START_ADDR_FIELD2_HI_V_0_READ_MASK _MK_MASK_CONST(0x3) +#define DC_B_WINBUF_BD_START_ADDR_FIELD2_HI_V_0_WRITE_MASK _MK_MASK_CONST(0x3) +#define DC_B_WINBUF_BD_START_ADDR_FIELD2_HI_V_0_BD_START_ADDR_FIELD2_HI_V_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINBUF_BD_START_ADDR_FIELD2_HI_V_0_BD_START_ADDR_FIELD2_HI_V_FIELD _MK_FIELD_CONST(0x3, DC_B_WINBUF_BD_START_ADDR_FIELD2_HI_V_0_BD_START_ADDR_FIELD2_HI_V_SHIFT) +#define DC_B_WINBUF_BD_START_ADDR_FIELD2_HI_V_0_BD_START_ADDR_FIELD2_HI_V_RANGE 1:0 +#define DC_B_WINBUF_BD_START_ADDR_FIELD2_HI_V_0_BD_START_ADDR_FIELD2_HI_V_WOFFSET 0x0 +#define DC_B_WINBUF_BD_START_ADDR_FIELD2_HI_V_0_BD_START_ADDR_FIELD2_HI_V_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_START_ADDR_FIELD2_HI_V_0_BD_START_ADDR_FIELD2_HI_V_DEFAULT_MASK _MK_MASK_CONST(0x3) +#define DC_B_WINBUF_BD_START_ADDR_FIELD2_HI_V_0_BD_START_ADDR_FIELD2_HI_V_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_START_ADDR_FIELD2_HI_V_0_BD_START_ADDR_FIELD2_HI_V_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_B_WINBUF_BD_START_ADDR_FIELD2_HI_V_NS_0 +#define DC_B_WINBUF_BD_START_ADDR_FIELD2_HI_V_NS_0 _MK_ADDR_CONST(0xdde) +#define DC_B_WINBUF_BD_START_ADDR_FIELD2_HI_V_NS_0_SECURE 0x0 +#define DC_B_WINBUF_BD_START_ADDR_FIELD2_HI_V_NS_0_WORD_COUNT 0x1 +#define DC_B_WINBUF_BD_START_ADDR_FIELD2_HI_V_NS_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_START_ADDR_FIELD2_HI_V_NS_0_RESET_MASK _MK_MASK_CONST(0x3) +#define DC_B_WINBUF_BD_START_ADDR_FIELD2_HI_V_NS_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_START_ADDR_FIELD2_HI_V_NS_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_START_ADDR_FIELD2_HI_V_NS_0_READ_MASK _MK_MASK_CONST(0x3) +#define DC_B_WINBUF_BD_START_ADDR_FIELD2_HI_V_NS_0_WRITE_MASK _MK_MASK_CONST(0x3) +#define DC_B_WINBUF_BD_START_ADDR_FIELD2_HI_V_NS_0_BD_START_ADDR_FIELD2_HI_V_NS_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINBUF_BD_START_ADDR_FIELD2_HI_V_NS_0_BD_START_ADDR_FIELD2_HI_V_NS_FIELD _MK_FIELD_CONST(0x3, DC_B_WINBUF_BD_START_ADDR_FIELD2_HI_V_NS_0_BD_START_ADDR_FIELD2_HI_V_NS_SHIFT) +#define DC_B_WINBUF_BD_START_ADDR_FIELD2_HI_V_NS_0_BD_START_ADDR_FIELD2_HI_V_NS_RANGE 1:0 +#define DC_B_WINBUF_BD_START_ADDR_FIELD2_HI_V_NS_0_BD_START_ADDR_FIELD2_HI_V_NS_WOFFSET 0x0 +#define DC_B_WINBUF_BD_START_ADDR_FIELD2_HI_V_NS_0_BD_START_ADDR_FIELD2_HI_V_NS_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_START_ADDR_FIELD2_HI_V_NS_0_BD_START_ADDR_FIELD2_HI_V_NS_DEFAULT_MASK _MK_MASK_CONST(0x3) +#define DC_B_WINBUF_BD_START_ADDR_FIELD2_HI_V_NS_0_BD_START_ADDR_FIELD2_HI_V_NS_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_START_ADDR_FIELD2_HI_V_NS_0_BD_START_ADDR_FIELD2_HI_V_NS_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_B_WINBUF_BD_ADDR_H_OFFSET_FIELD2_0 +#define DC_B_WINBUF_BD_ADDR_H_OFFSET_FIELD2_0 _MK_ADDR_CONST(0xddf) +#define DC_B_WINBUF_BD_ADDR_H_OFFSET_FIELD2_0_SECURE 0x0 +#define DC_B_WINBUF_BD_ADDR_H_OFFSET_FIELD2_0_WORD_COUNT 0x1 +#define DC_B_WINBUF_BD_ADDR_H_OFFSET_FIELD2_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_ADDR_H_OFFSET_FIELD2_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_ADDR_H_OFFSET_FIELD2_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_ADDR_H_OFFSET_FIELD2_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_ADDR_H_OFFSET_FIELD2_0_READ_MASK _MK_MASK_CONST(0xffffffff) +#define DC_B_WINBUF_BD_ADDR_H_OFFSET_FIELD2_0_WRITE_MASK _MK_MASK_CONST(0xffffffff) +#define DC_B_WINBUF_BD_ADDR_H_OFFSET_FIELD2_0_BD_ADDR_H_OFFSET_FIELD2_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINBUF_BD_ADDR_H_OFFSET_FIELD2_0_BD_ADDR_H_OFFSET_FIELD2_FIELD _MK_FIELD_CONST(0xffffffff, DC_B_WINBUF_BD_ADDR_H_OFFSET_FIELD2_0_BD_ADDR_H_OFFSET_FIELD2_SHIFT) +#define DC_B_WINBUF_BD_ADDR_H_OFFSET_FIELD2_0_BD_ADDR_H_OFFSET_FIELD2_RANGE 31:0 +#define DC_B_WINBUF_BD_ADDR_H_OFFSET_FIELD2_0_BD_ADDR_H_OFFSET_FIELD2_WOFFSET 0x0 +#define DC_B_WINBUF_BD_ADDR_H_OFFSET_FIELD2_0_BD_ADDR_H_OFFSET_FIELD2_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_ADDR_H_OFFSET_FIELD2_0_BD_ADDR_H_OFFSET_FIELD2_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_ADDR_H_OFFSET_FIELD2_0_BD_ADDR_H_OFFSET_FIELD2_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_ADDR_H_OFFSET_FIELD2_0_BD_ADDR_H_OFFSET_FIELD2_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_B_WINBUF_BD_ADDR_H_OFFSET_FIELD2_NS_0 +#define DC_B_WINBUF_BD_ADDR_H_OFFSET_FIELD2_NS_0 _MK_ADDR_CONST(0xde0) +#define DC_B_WINBUF_BD_ADDR_H_OFFSET_FIELD2_NS_0_SECURE 0x0 +#define DC_B_WINBUF_BD_ADDR_H_OFFSET_FIELD2_NS_0_WORD_COUNT 0x1 +#define DC_B_WINBUF_BD_ADDR_H_OFFSET_FIELD2_NS_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_ADDR_H_OFFSET_FIELD2_NS_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_ADDR_H_OFFSET_FIELD2_NS_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_ADDR_H_OFFSET_FIELD2_NS_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_ADDR_H_OFFSET_FIELD2_NS_0_READ_MASK _MK_MASK_CONST(0xffffffff) +#define DC_B_WINBUF_BD_ADDR_H_OFFSET_FIELD2_NS_0_WRITE_MASK _MK_MASK_CONST(0xffffffff) +#define DC_B_WINBUF_BD_ADDR_H_OFFSET_FIELD2_NS_0_BD_ADDR_H_OFFSET_FIELD2_NS_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINBUF_BD_ADDR_H_OFFSET_FIELD2_NS_0_BD_ADDR_H_OFFSET_FIELD2_NS_FIELD _MK_FIELD_CONST(0xffffffff, DC_B_WINBUF_BD_ADDR_H_OFFSET_FIELD2_NS_0_BD_ADDR_H_OFFSET_FIELD2_NS_SHIFT) +#define DC_B_WINBUF_BD_ADDR_H_OFFSET_FIELD2_NS_0_BD_ADDR_H_OFFSET_FIELD2_NS_RANGE 31:0 +#define DC_B_WINBUF_BD_ADDR_H_OFFSET_FIELD2_NS_0_BD_ADDR_H_OFFSET_FIELD2_NS_WOFFSET 0x0 +#define DC_B_WINBUF_BD_ADDR_H_OFFSET_FIELD2_NS_0_BD_ADDR_H_OFFSET_FIELD2_NS_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_ADDR_H_OFFSET_FIELD2_NS_0_BD_ADDR_H_OFFSET_FIELD2_NS_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_ADDR_H_OFFSET_FIELD2_NS_0_BD_ADDR_H_OFFSET_FIELD2_NS_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_ADDR_H_OFFSET_FIELD2_NS_0_BD_ADDR_H_OFFSET_FIELD2_NS_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_B_WINBUF_BD_ADDR_V_OFFSET_FIELD2_0 +#define DC_B_WINBUF_BD_ADDR_V_OFFSET_FIELD2_0 _MK_ADDR_CONST(0xde1) +#define DC_B_WINBUF_BD_ADDR_V_OFFSET_FIELD2_0_SECURE 0x0 +#define DC_B_WINBUF_BD_ADDR_V_OFFSET_FIELD2_0_WORD_COUNT 0x1 +#define DC_B_WINBUF_BD_ADDR_V_OFFSET_FIELD2_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_ADDR_V_OFFSET_FIELD2_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_ADDR_V_OFFSET_FIELD2_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_ADDR_V_OFFSET_FIELD2_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_ADDR_V_OFFSET_FIELD2_0_READ_MASK _MK_MASK_CONST(0xffffffff) +#define DC_B_WINBUF_BD_ADDR_V_OFFSET_FIELD2_0_WRITE_MASK _MK_MASK_CONST(0xffffffff) +#define DC_B_WINBUF_BD_ADDR_V_OFFSET_FIELD2_0_BD_ADDR_V_OFFSET_FIELD2_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINBUF_BD_ADDR_V_OFFSET_FIELD2_0_BD_ADDR_V_OFFSET_FIELD2_FIELD _MK_FIELD_CONST(0xffffffff, DC_B_WINBUF_BD_ADDR_V_OFFSET_FIELD2_0_BD_ADDR_V_OFFSET_FIELD2_SHIFT) +#define DC_B_WINBUF_BD_ADDR_V_OFFSET_FIELD2_0_BD_ADDR_V_OFFSET_FIELD2_RANGE 31:0 +#define DC_B_WINBUF_BD_ADDR_V_OFFSET_FIELD2_0_BD_ADDR_V_OFFSET_FIELD2_WOFFSET 0x0 +#define DC_B_WINBUF_BD_ADDR_V_OFFSET_FIELD2_0_BD_ADDR_V_OFFSET_FIELD2_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_ADDR_V_OFFSET_FIELD2_0_BD_ADDR_V_OFFSET_FIELD2_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_ADDR_V_OFFSET_FIELD2_0_BD_ADDR_V_OFFSET_FIELD2_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_ADDR_V_OFFSET_FIELD2_0_BD_ADDR_V_OFFSET_FIELD2_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_B_WINBUF_BD_ADDR_V_OFFSET_FIELD2_NS_0 +#define DC_B_WINBUF_BD_ADDR_V_OFFSET_FIELD2_NS_0 _MK_ADDR_CONST(0xde2) +#define DC_B_WINBUF_BD_ADDR_V_OFFSET_FIELD2_NS_0_SECURE 0x0 +#define DC_B_WINBUF_BD_ADDR_V_OFFSET_FIELD2_NS_0_WORD_COUNT 0x1 +#define DC_B_WINBUF_BD_ADDR_V_OFFSET_FIELD2_NS_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_ADDR_V_OFFSET_FIELD2_NS_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_ADDR_V_OFFSET_FIELD2_NS_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_ADDR_V_OFFSET_FIELD2_NS_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_ADDR_V_OFFSET_FIELD2_NS_0_READ_MASK _MK_MASK_CONST(0xffffffff) +#define DC_B_WINBUF_BD_ADDR_V_OFFSET_FIELD2_NS_0_WRITE_MASK _MK_MASK_CONST(0xffffffff) +#define DC_B_WINBUF_BD_ADDR_V_OFFSET_FIELD2_NS_0_BD_ADDR_V_OFFSET_FIELD2_NS_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINBUF_BD_ADDR_V_OFFSET_FIELD2_NS_0_BD_ADDR_V_OFFSET_FIELD2_NS_FIELD _MK_FIELD_CONST(0xffffffff, DC_B_WINBUF_BD_ADDR_V_OFFSET_FIELD2_NS_0_BD_ADDR_V_OFFSET_FIELD2_NS_SHIFT) +#define DC_B_WINBUF_BD_ADDR_V_OFFSET_FIELD2_NS_0_BD_ADDR_V_OFFSET_FIELD2_NS_RANGE 31:0 +#define DC_B_WINBUF_BD_ADDR_V_OFFSET_FIELD2_NS_0_BD_ADDR_V_OFFSET_FIELD2_NS_WOFFSET 0x0 +#define DC_B_WINBUF_BD_ADDR_V_OFFSET_FIELD2_NS_0_BD_ADDR_V_OFFSET_FIELD2_NS_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_ADDR_V_OFFSET_FIELD2_NS_0_BD_ADDR_V_OFFSET_FIELD2_NS_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_ADDR_V_OFFSET_FIELD2_NS_0_BD_ADDR_V_OFFSET_FIELD2_NS_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_ADDR_V_OFFSET_FIELD2_NS_0_BD_ADDR_V_OFFSET_FIELD2_NS_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Reserved address 3555 [0xde3] + +// Register DC_B_WINBUF_BD_UFLOW_CTRL_0 +#define DC_B_WINBUF_BD_UFLOW_CTRL_0 _MK_ADDR_CONST(0xde4) +#define DC_B_WINBUF_BD_UFLOW_CTRL_0_SECURE 0x0 +#define DC_B_WINBUF_BD_UFLOW_CTRL_0_WORD_COUNT 0x1 +#define DC_B_WINBUF_BD_UFLOW_CTRL_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_UFLOW_CTRL_0_RESET_MASK _MK_MASK_CONST(0x1) +#define DC_B_WINBUF_BD_UFLOW_CTRL_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_UFLOW_CTRL_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_UFLOW_CTRL_0_READ_MASK _MK_MASK_CONST(0x1) +#define DC_B_WINBUF_BD_UFLOW_CTRL_0_WRITE_MASK _MK_MASK_CONST(0x1) +#define DC_B_WINBUF_BD_UFLOW_CTRL_0_BD_UFLOW_CTRL_DBG_MODE_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINBUF_BD_UFLOW_CTRL_0_BD_UFLOW_CTRL_DBG_MODE_FIELD _MK_FIELD_CONST(0x1, DC_B_WINBUF_BD_UFLOW_CTRL_0_BD_UFLOW_CTRL_DBG_MODE_SHIFT) +#define DC_B_WINBUF_BD_UFLOW_CTRL_0_BD_UFLOW_CTRL_DBG_MODE_RANGE 0:0 +#define DC_B_WINBUF_BD_UFLOW_CTRL_0_BD_UFLOW_CTRL_DBG_MODE_WOFFSET 0x0 +#define DC_B_WINBUF_BD_UFLOW_CTRL_0_BD_UFLOW_CTRL_DBG_MODE_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_UFLOW_CTRL_0_BD_UFLOW_CTRL_DBG_MODE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_B_WINBUF_BD_UFLOW_CTRL_0_BD_UFLOW_CTRL_DBG_MODE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_UFLOW_CTRL_0_BD_UFLOW_CTRL_DBG_MODE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_UFLOW_CTRL_0_BD_UFLOW_CTRL_DBG_MODE_DISABLE _MK_ENUM_CONST(0) +#define DC_B_WINBUF_BD_UFLOW_CTRL_0_BD_UFLOW_CTRL_DBG_MODE_ENABLE _MK_ENUM_CONST(1) + + +// Register DC_B_WINBUF_BD_UFLOW_DBG_PIXEL_0 +#define DC_B_WINBUF_BD_UFLOW_DBG_PIXEL_0 _MK_ADDR_CONST(0xde5) +#define DC_B_WINBUF_BD_UFLOW_DBG_PIXEL_0_SECURE 0x0 +#define DC_B_WINBUF_BD_UFLOW_DBG_PIXEL_0_WORD_COUNT 0x1 +#define DC_B_WINBUF_BD_UFLOW_DBG_PIXEL_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_UFLOW_DBG_PIXEL_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_UFLOW_DBG_PIXEL_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_UFLOW_DBG_PIXEL_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_UFLOW_DBG_PIXEL_0_READ_MASK _MK_MASK_CONST(0xffffffff) +#define DC_B_WINBUF_BD_UFLOW_DBG_PIXEL_0_WRITE_MASK _MK_MASK_CONST(0xffffffff) +#define DC_B_WINBUF_BD_UFLOW_DBG_PIXEL_0_BD_UFLOW_DBG_PIXEL_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINBUF_BD_UFLOW_DBG_PIXEL_0_BD_UFLOW_DBG_PIXEL_FIELD _MK_FIELD_CONST(0xffffffff, DC_B_WINBUF_BD_UFLOW_DBG_PIXEL_0_BD_UFLOW_DBG_PIXEL_SHIFT) +#define DC_B_WINBUF_BD_UFLOW_DBG_PIXEL_0_BD_UFLOW_DBG_PIXEL_RANGE 31:0 +#define DC_B_WINBUF_BD_UFLOW_DBG_PIXEL_0_BD_UFLOW_DBG_PIXEL_WOFFSET 0x0 +#define DC_B_WINBUF_BD_UFLOW_DBG_PIXEL_0_BD_UFLOW_DBG_PIXEL_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_UFLOW_DBG_PIXEL_0_BD_UFLOW_DBG_PIXEL_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_UFLOW_DBG_PIXEL_0_BD_UFLOW_DBG_PIXEL_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_UFLOW_DBG_PIXEL_0_BD_UFLOW_DBG_PIXEL_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_B_WINBUF_BD_UFLOW_THRESHOLD_0 +#define DC_B_WINBUF_BD_UFLOW_THRESHOLD_0 _MK_ADDR_CONST(0xde6) +#define DC_B_WINBUF_BD_UFLOW_THRESHOLD_0_SECURE 0x0 +#define DC_B_WINBUF_BD_UFLOW_THRESHOLD_0_WORD_COUNT 0x1 +#define DC_B_WINBUF_BD_UFLOW_THRESHOLD_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_UFLOW_THRESHOLD_0_RESET_MASK _MK_MASK_CONST(0x1fff) +#define DC_B_WINBUF_BD_UFLOW_THRESHOLD_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_UFLOW_THRESHOLD_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_UFLOW_THRESHOLD_0_READ_MASK _MK_MASK_CONST(0x1fff) +#define DC_B_WINBUF_BD_UFLOW_THRESHOLD_0_WRITE_MASK _MK_MASK_CONST(0x1fff) +#define DC_B_WINBUF_BD_UFLOW_THRESHOLD_0_BD_UFLOW_THRESHOLD_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINBUF_BD_UFLOW_THRESHOLD_0_BD_UFLOW_THRESHOLD_FIELD _MK_FIELD_CONST(0x1fff, DC_B_WINBUF_BD_UFLOW_THRESHOLD_0_BD_UFLOW_THRESHOLD_SHIFT) +#define DC_B_WINBUF_BD_UFLOW_THRESHOLD_0_BD_UFLOW_THRESHOLD_RANGE 12:0 +#define DC_B_WINBUF_BD_UFLOW_THRESHOLD_0_BD_UFLOW_THRESHOLD_WOFFSET 0x0 +#define DC_B_WINBUF_BD_UFLOW_THRESHOLD_0_BD_UFLOW_THRESHOLD_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_UFLOW_THRESHOLD_0_BD_UFLOW_THRESHOLD_DEFAULT_MASK _MK_MASK_CONST(0x1fff) +#define DC_B_WINBUF_BD_UFLOW_THRESHOLD_0_BD_UFLOW_THRESHOLD_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_UFLOW_THRESHOLD_0_BD_UFLOW_THRESHOLD_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_B_WINBUF_BD_SPOOL_UP_0 +#define DC_B_WINBUF_BD_SPOOL_UP_0 _MK_ADDR_CONST(0xde7) +#define DC_B_WINBUF_BD_SPOOL_UP_0_SECURE 0x0 +#define DC_B_WINBUF_BD_SPOOL_UP_0_WORD_COUNT 0x1 +#define DC_B_WINBUF_BD_SPOOL_UP_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_SPOOL_UP_0_RESET_MASK _MK_MASK_CONST(0x3) +#define DC_B_WINBUF_BD_SPOOL_UP_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_SPOOL_UP_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_SPOOL_UP_0_READ_MASK _MK_MASK_CONST(0x1fff0003) +#define DC_B_WINBUF_BD_SPOOL_UP_0_WRITE_MASK _MK_MASK_CONST(0x1fff0003) +#define DC_B_WINBUF_BD_SPOOL_UP_0_BD_SPOOL_UP_CTRL_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINBUF_BD_SPOOL_UP_0_BD_SPOOL_UP_CTRL_FIELD _MK_FIELD_CONST(0x1, DC_B_WINBUF_BD_SPOOL_UP_0_BD_SPOOL_UP_CTRL_SHIFT) +#define DC_B_WINBUF_BD_SPOOL_UP_0_BD_SPOOL_UP_CTRL_RANGE 0:0 +#define DC_B_WINBUF_BD_SPOOL_UP_0_BD_SPOOL_UP_CTRL_WOFFSET 0x0 +#define DC_B_WINBUF_BD_SPOOL_UP_0_BD_SPOOL_UP_CTRL_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_SPOOL_UP_0_BD_SPOOL_UP_CTRL_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_B_WINBUF_BD_SPOOL_UP_0_BD_SPOOL_UP_CTRL_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_SPOOL_UP_0_BD_SPOOL_UP_CTRL_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_SPOOL_UP_0_BD_SPOOL_UP_CTRL_MAX _MK_ENUM_CONST(0) +#define DC_B_WINBUF_BD_SPOOL_UP_0_BD_SPOOL_UP_CTRL_PROGRAMMABLE _MK_ENUM_CONST(1) + +#define DC_B_WINBUF_BD_SPOOL_UP_0_BD_SPOOL_UP_EDGE_SHIFT _MK_SHIFT_CONST(1) +#define DC_B_WINBUF_BD_SPOOL_UP_0_BD_SPOOL_UP_EDGE_FIELD _MK_FIELD_CONST(0x1, DC_B_WINBUF_BD_SPOOL_UP_0_BD_SPOOL_UP_EDGE_SHIFT) +#define DC_B_WINBUF_BD_SPOOL_UP_0_BD_SPOOL_UP_EDGE_RANGE 1:1 +#define DC_B_WINBUF_BD_SPOOL_UP_0_BD_SPOOL_UP_EDGE_WOFFSET 0x0 +#define DC_B_WINBUF_BD_SPOOL_UP_0_BD_SPOOL_UP_EDGE_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_SPOOL_UP_0_BD_SPOOL_UP_EDGE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_B_WINBUF_BD_SPOOL_UP_0_BD_SPOOL_UP_EDGE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_SPOOL_UP_0_BD_SPOOL_UP_EDGE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_SPOOL_UP_0_BD_SPOOL_UP_EDGE_NEGEDGE _MK_ENUM_CONST(0) +#define DC_B_WINBUF_BD_SPOOL_UP_0_BD_SPOOL_UP_EDGE_POSEDGE _MK_ENUM_CONST(1) + +#define DC_B_WINBUF_BD_SPOOL_UP_0_BD_SPOOL_UP_DURATION_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINBUF_BD_SPOOL_UP_0_BD_SPOOL_UP_DURATION_FIELD _MK_FIELD_CONST(0x1fff, DC_B_WINBUF_BD_SPOOL_UP_0_BD_SPOOL_UP_DURATION_SHIFT) +#define DC_B_WINBUF_BD_SPOOL_UP_0_BD_SPOOL_UP_DURATION_RANGE 28:16 +#define DC_B_WINBUF_BD_SPOOL_UP_0_BD_SPOOL_UP_DURATION_WOFFSET 0x0 +#define DC_B_WINBUF_BD_SPOOL_UP_0_BD_SPOOL_UP_DURATION_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_SPOOL_UP_0_BD_SPOOL_UP_DURATION_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_SPOOL_UP_0_BD_SPOOL_UP_DURATION_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_SPOOL_UP_0_BD_SPOOL_UP_DURATION_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_B_WINBUF_BD_SCALEFACTOR_THRESHOLD_0 +#define DC_B_WINBUF_BD_SCALEFACTOR_THRESHOLD_0 _MK_ADDR_CONST(0xde8) +#define DC_B_WINBUF_BD_SCALEFACTOR_THRESHOLD_0_SECURE 0x0 +#define DC_B_WINBUF_BD_SCALEFACTOR_THRESHOLD_0_WORD_COUNT 0x1 +#define DC_B_WINBUF_BD_SCALEFACTOR_THRESHOLD_0_RESET_VAL _MK_MASK_CONST(0xffffffff) +#define DC_B_WINBUF_BD_SCALEFACTOR_THRESHOLD_0_RESET_MASK _MK_MASK_CONST(0xffffffff) +#define DC_B_WINBUF_BD_SCALEFACTOR_THRESHOLD_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_SCALEFACTOR_THRESHOLD_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_SCALEFACTOR_THRESHOLD_0_READ_MASK _MK_MASK_CONST(0xffffffff) +#define DC_B_WINBUF_BD_SCALEFACTOR_THRESHOLD_0_WRITE_MASK _MK_MASK_CONST(0xffffffff) +#define DC_B_WINBUF_BD_SCALEFACTOR_THRESHOLD_0_BD_SF_HWM_THRESHOLD_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINBUF_BD_SCALEFACTOR_THRESHOLD_0_BD_SF_HWM_THRESHOLD_FIELD _MK_FIELD_CONST(0xffff, DC_B_WINBUF_BD_SCALEFACTOR_THRESHOLD_0_BD_SF_HWM_THRESHOLD_SHIFT) +#define DC_B_WINBUF_BD_SCALEFACTOR_THRESHOLD_0_BD_SF_HWM_THRESHOLD_RANGE 15:0 +#define DC_B_WINBUF_BD_SCALEFACTOR_THRESHOLD_0_BD_SF_HWM_THRESHOLD_WOFFSET 0x0 +#define DC_B_WINBUF_BD_SCALEFACTOR_THRESHOLD_0_BD_SF_HWM_THRESHOLD_DEFAULT _MK_MASK_CONST(0xffff) +#define DC_B_WINBUF_BD_SCALEFACTOR_THRESHOLD_0_BD_SF_HWM_THRESHOLD_DEFAULT_MASK _MK_MASK_CONST(0xffff) +#define DC_B_WINBUF_BD_SCALEFACTOR_THRESHOLD_0_BD_SF_HWM_THRESHOLD_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_SCALEFACTOR_THRESHOLD_0_BD_SF_HWM_THRESHOLD_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINBUF_BD_SCALEFACTOR_THRESHOLD_0_BD_SF_LWM_THRESHOLD_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINBUF_BD_SCALEFACTOR_THRESHOLD_0_BD_SF_LWM_THRESHOLD_FIELD _MK_FIELD_CONST(0xffff, DC_B_WINBUF_BD_SCALEFACTOR_THRESHOLD_0_BD_SF_LWM_THRESHOLD_SHIFT) +#define DC_B_WINBUF_BD_SCALEFACTOR_THRESHOLD_0_BD_SF_LWM_THRESHOLD_RANGE 31:16 +#define DC_B_WINBUF_BD_SCALEFACTOR_THRESHOLD_0_BD_SF_LWM_THRESHOLD_WOFFSET 0x0 +#define DC_B_WINBUF_BD_SCALEFACTOR_THRESHOLD_0_BD_SF_LWM_THRESHOLD_DEFAULT _MK_MASK_CONST(0xffff) +#define DC_B_WINBUF_BD_SCALEFACTOR_THRESHOLD_0_BD_SF_LWM_THRESHOLD_DEFAULT_MASK _MK_MASK_CONST(0xffff) +#define DC_B_WINBUF_BD_SCALEFACTOR_THRESHOLD_0_BD_SF_LWM_THRESHOLD_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_SCALEFACTOR_THRESHOLD_0_BD_SF_LWM_THRESHOLD_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_B_WINBUF_BD_LATENCY_THRESHOLD_0 +#define DC_B_WINBUF_BD_LATENCY_THRESHOLD_0 _MK_ADDR_CONST(0xde9) +#define DC_B_WINBUF_BD_LATENCY_THRESHOLD_0_SECURE 0x0 +#define DC_B_WINBUF_BD_LATENCY_THRESHOLD_0_WORD_COUNT 0x1 +#define DC_B_WINBUF_BD_LATENCY_THRESHOLD_0_RESET_VAL _MK_MASK_CONST(0xffff) +#define DC_B_WINBUF_BD_LATENCY_THRESHOLD_0_RESET_MASK _MK_MASK_CONST(0xdfffffff) +#define DC_B_WINBUF_BD_LATENCY_THRESHOLD_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_LATENCY_THRESHOLD_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_LATENCY_THRESHOLD_0_READ_MASK _MK_MASK_CONST(0xdfffffff) +#define DC_B_WINBUF_BD_LATENCY_THRESHOLD_0_WRITE_MASK _MK_MASK_CONST(0xdfffffff) +#define DC_B_WINBUF_BD_LATENCY_THRESHOLD_0_BD_RDY4LATENCY_THRESHOLD_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINBUF_BD_LATENCY_THRESHOLD_0_BD_RDY4LATENCY_THRESHOLD_FIELD _MK_FIELD_CONST(0xffff, DC_B_WINBUF_BD_LATENCY_THRESHOLD_0_BD_RDY4LATENCY_THRESHOLD_SHIFT) +#define DC_B_WINBUF_BD_LATENCY_THRESHOLD_0_BD_RDY4LATENCY_THRESHOLD_RANGE 15:0 +#define DC_B_WINBUF_BD_LATENCY_THRESHOLD_0_BD_RDY4LATENCY_THRESHOLD_WOFFSET 0x0 +#define DC_B_WINBUF_BD_LATENCY_THRESHOLD_0_BD_RDY4LATENCY_THRESHOLD_DEFAULT _MK_MASK_CONST(0xffff) +#define DC_B_WINBUF_BD_LATENCY_THRESHOLD_0_BD_RDY4LATENCY_THRESHOLD_DEFAULT_MASK _MK_MASK_CONST(0xffff) +#define DC_B_WINBUF_BD_LATENCY_THRESHOLD_0_BD_RDY4LATENCY_THRESHOLD_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_LATENCY_THRESHOLD_0_BD_RDY4LATENCY_THRESHOLD_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINBUF_BD_LATENCY_THRESHOLD_0_BD_RDY4LATENCY_SPOOLUP_DURATION_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINBUF_BD_LATENCY_THRESHOLD_0_BD_RDY4LATENCY_SPOOLUP_DURATION_FIELD _MK_FIELD_CONST(0x1fff, DC_B_WINBUF_BD_LATENCY_THRESHOLD_0_BD_RDY4LATENCY_SPOOLUP_DURATION_SHIFT) +#define DC_B_WINBUF_BD_LATENCY_THRESHOLD_0_BD_RDY4LATENCY_SPOOLUP_DURATION_RANGE 28:16 +#define DC_B_WINBUF_BD_LATENCY_THRESHOLD_0_BD_RDY4LATENCY_SPOOLUP_DURATION_WOFFSET 0x0 +#define DC_B_WINBUF_BD_LATENCY_THRESHOLD_0_BD_RDY4LATENCY_SPOOLUP_DURATION_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_LATENCY_THRESHOLD_0_BD_RDY4LATENCY_SPOOLUP_DURATION_DEFAULT_MASK _MK_MASK_CONST(0x1fff) +#define DC_B_WINBUF_BD_LATENCY_THRESHOLD_0_BD_RDY4LATENCY_SPOOLUP_DURATION_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_LATENCY_THRESHOLD_0_BD_RDY4LATENCY_SPOOLUP_DURATION_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINBUF_BD_LATENCY_THRESHOLD_0_BD_RDY4LATENCY_SPOOLUP_CTRL_SHIFT _MK_SHIFT_CONST(30) +#define DC_B_WINBUF_BD_LATENCY_THRESHOLD_0_BD_RDY4LATENCY_SPOOLUP_CTRL_FIELD _MK_FIELD_CONST(0x1, DC_B_WINBUF_BD_LATENCY_THRESHOLD_0_BD_RDY4LATENCY_SPOOLUP_CTRL_SHIFT) +#define DC_B_WINBUF_BD_LATENCY_THRESHOLD_0_BD_RDY4LATENCY_SPOOLUP_CTRL_RANGE 30:30 +#define DC_B_WINBUF_BD_LATENCY_THRESHOLD_0_BD_RDY4LATENCY_SPOOLUP_CTRL_WOFFSET 0x0 +#define DC_B_WINBUF_BD_LATENCY_THRESHOLD_0_BD_RDY4LATENCY_SPOOLUP_CTRL_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_LATENCY_THRESHOLD_0_BD_RDY4LATENCY_SPOOLUP_CTRL_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_B_WINBUF_BD_LATENCY_THRESHOLD_0_BD_RDY4LATENCY_SPOOLUP_CTRL_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_LATENCY_THRESHOLD_0_BD_RDY4LATENCY_SPOOLUP_CTRL_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_LATENCY_THRESHOLD_0_BD_RDY4LATENCY_SPOOLUP_CTRL_INIT_ENUM DISALLOW +#define DC_B_WINBUF_BD_LATENCY_THRESHOLD_0_BD_RDY4LATENCY_SPOOLUP_CTRL_DISALLOW _MK_ENUM_CONST(0) +#define DC_B_WINBUF_BD_LATENCY_THRESHOLD_0_BD_RDY4LATENCY_SPOOLUP_CTRL_ALLOW _MK_ENUM_CONST(1) + +#define DC_B_WINBUF_BD_LATENCY_THRESHOLD_0_BD_RDY4LATENCY_THRESHOLD_ENABLE_SHIFT _MK_SHIFT_CONST(31) +#define DC_B_WINBUF_BD_LATENCY_THRESHOLD_0_BD_RDY4LATENCY_THRESHOLD_ENABLE_FIELD _MK_FIELD_CONST(0x1, DC_B_WINBUF_BD_LATENCY_THRESHOLD_0_BD_RDY4LATENCY_THRESHOLD_ENABLE_SHIFT) +#define DC_B_WINBUF_BD_LATENCY_THRESHOLD_0_BD_RDY4LATENCY_THRESHOLD_ENABLE_RANGE 31:31 +#define DC_B_WINBUF_BD_LATENCY_THRESHOLD_0_BD_RDY4LATENCY_THRESHOLD_ENABLE_WOFFSET 0x0 +#define DC_B_WINBUF_BD_LATENCY_THRESHOLD_0_BD_RDY4LATENCY_THRESHOLD_ENABLE_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_LATENCY_THRESHOLD_0_BD_RDY4LATENCY_THRESHOLD_ENABLE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_B_WINBUF_BD_LATENCY_THRESHOLD_0_BD_RDY4LATENCY_THRESHOLD_ENABLE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_LATENCY_THRESHOLD_0_BD_RDY4LATENCY_THRESHOLD_ENABLE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_LATENCY_THRESHOLD_0_BD_RDY4LATENCY_THRESHOLD_ENABLE_INIT_ENUM DISABLE +#define DC_B_WINBUF_BD_LATENCY_THRESHOLD_0_BD_RDY4LATENCY_THRESHOLD_ENABLE_DISABLE _MK_ENUM_CONST(0) +#define DC_B_WINBUF_BD_LATENCY_THRESHOLD_0_BD_RDY4LATENCY_THRESHOLD_ENABLE_ENABLE _MK_ENUM_CONST(1) + + +// Register DC_B_WINBUF_BD_MEMFETCH_DEBUG_STATUS_0 +#define DC_B_WINBUF_BD_MEMFETCH_DEBUG_STATUS_0 _MK_ADDR_CONST(0xdea) +#define DC_B_WINBUF_BD_MEMFETCH_DEBUG_STATUS_0_SECURE 0x0 +#define DC_B_WINBUF_BD_MEMFETCH_DEBUG_STATUS_0_WORD_COUNT 0x1 +#define DC_B_WINBUF_BD_MEMFETCH_DEBUG_STATUS_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_MEMFETCH_DEBUG_STATUS_0_RESET_MASK _MK_MASK_CONST(0x1ffff) +#define DC_B_WINBUF_BD_MEMFETCH_DEBUG_STATUS_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_MEMFETCH_DEBUG_STATUS_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_MEMFETCH_DEBUG_STATUS_0_READ_MASK _MK_MASK_CONST(0x1ffff) +#define DC_B_WINBUF_BD_MEMFETCH_DEBUG_STATUS_0_WRITE_MASK _MK_MASK_CONST(0x1ffff) +#define DC_B_WINBUF_BD_MEMFETCH_DEBUG_STATUS_0_B_UNDERFLOW_LINE0_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINBUF_BD_MEMFETCH_DEBUG_STATUS_0_B_UNDERFLOW_LINE0_FIELD _MK_FIELD_CONST(0x1, DC_B_WINBUF_BD_MEMFETCH_DEBUG_STATUS_0_B_UNDERFLOW_LINE0_SHIFT) +#define DC_B_WINBUF_BD_MEMFETCH_DEBUG_STATUS_0_B_UNDERFLOW_LINE0_RANGE 0:0 +#define DC_B_WINBUF_BD_MEMFETCH_DEBUG_STATUS_0_B_UNDERFLOW_LINE0_WOFFSET 0x0 +#define DC_B_WINBUF_BD_MEMFETCH_DEBUG_STATUS_0_B_UNDERFLOW_LINE0_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_MEMFETCH_DEBUG_STATUS_0_B_UNDERFLOW_LINE0_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_B_WINBUF_BD_MEMFETCH_DEBUG_STATUS_0_B_UNDERFLOW_LINE0_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_MEMFETCH_DEBUG_STATUS_0_B_UNDERFLOW_LINE0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINBUF_BD_MEMFETCH_DEBUG_STATUS_0_B_UNDERFLOW_LINE1_SHIFT _MK_SHIFT_CONST(1) +#define DC_B_WINBUF_BD_MEMFETCH_DEBUG_STATUS_0_B_UNDERFLOW_LINE1_FIELD _MK_FIELD_CONST(0x1, DC_B_WINBUF_BD_MEMFETCH_DEBUG_STATUS_0_B_UNDERFLOW_LINE1_SHIFT) +#define DC_B_WINBUF_BD_MEMFETCH_DEBUG_STATUS_0_B_UNDERFLOW_LINE1_RANGE 1:1 +#define DC_B_WINBUF_BD_MEMFETCH_DEBUG_STATUS_0_B_UNDERFLOW_LINE1_WOFFSET 0x0 +#define DC_B_WINBUF_BD_MEMFETCH_DEBUG_STATUS_0_B_UNDERFLOW_LINE1_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_MEMFETCH_DEBUG_STATUS_0_B_UNDERFLOW_LINE1_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_B_WINBUF_BD_MEMFETCH_DEBUG_STATUS_0_B_UNDERFLOW_LINE1_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_MEMFETCH_DEBUG_STATUS_0_B_UNDERFLOW_LINE1_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINBUF_BD_MEMFETCH_DEBUG_STATUS_0_B_POOL_NOT_EMPTY_SHIFT _MK_SHIFT_CONST(2) +#define DC_B_WINBUF_BD_MEMFETCH_DEBUG_STATUS_0_B_POOL_NOT_EMPTY_FIELD _MK_FIELD_CONST(0x1, DC_B_WINBUF_BD_MEMFETCH_DEBUG_STATUS_0_B_POOL_NOT_EMPTY_SHIFT) +#define DC_B_WINBUF_BD_MEMFETCH_DEBUG_STATUS_0_B_POOL_NOT_EMPTY_RANGE 2:2 +#define DC_B_WINBUF_BD_MEMFETCH_DEBUG_STATUS_0_B_POOL_NOT_EMPTY_WOFFSET 0x0 +#define DC_B_WINBUF_BD_MEMFETCH_DEBUG_STATUS_0_B_POOL_NOT_EMPTY_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_MEMFETCH_DEBUG_STATUS_0_B_POOL_NOT_EMPTY_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_B_WINBUF_BD_MEMFETCH_DEBUG_STATUS_0_B_POOL_NOT_EMPTY_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_MEMFETCH_DEBUG_STATUS_0_B_POOL_NOT_EMPTY_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINBUF_BD_MEMFETCH_DEBUG_STATUS_0_B_DP_POOL_AVAIL_SHIFT _MK_SHIFT_CONST(3) +#define DC_B_WINBUF_BD_MEMFETCH_DEBUG_STATUS_0_B_DP_POOL_AVAIL_FIELD _MK_FIELD_CONST(0x1, DC_B_WINBUF_BD_MEMFETCH_DEBUG_STATUS_0_B_DP_POOL_AVAIL_SHIFT) +#define DC_B_WINBUF_BD_MEMFETCH_DEBUG_STATUS_0_B_DP_POOL_AVAIL_RANGE 3:3 +#define DC_B_WINBUF_BD_MEMFETCH_DEBUG_STATUS_0_B_DP_POOL_AVAIL_WOFFSET 0x0 +#define DC_B_WINBUF_BD_MEMFETCH_DEBUG_STATUS_0_B_DP_POOL_AVAIL_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_MEMFETCH_DEBUG_STATUS_0_B_DP_POOL_AVAIL_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_B_WINBUF_BD_MEMFETCH_DEBUG_STATUS_0_B_DP_POOL_AVAIL_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_MEMFETCH_DEBUG_STATUS_0_B_DP_POOL_AVAIL_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINBUF_BD_MEMFETCH_DEBUG_STATUS_0_B_Y_SSM_NON_IDLE_SHIFT _MK_SHIFT_CONST(4) +#define DC_B_WINBUF_BD_MEMFETCH_DEBUG_STATUS_0_B_Y_SSM_NON_IDLE_FIELD _MK_FIELD_CONST(0x1, DC_B_WINBUF_BD_MEMFETCH_DEBUG_STATUS_0_B_Y_SSM_NON_IDLE_SHIFT) +#define DC_B_WINBUF_BD_MEMFETCH_DEBUG_STATUS_0_B_Y_SSM_NON_IDLE_RANGE 4:4 +#define DC_B_WINBUF_BD_MEMFETCH_DEBUG_STATUS_0_B_Y_SSM_NON_IDLE_WOFFSET 0x0 +#define DC_B_WINBUF_BD_MEMFETCH_DEBUG_STATUS_0_B_Y_SSM_NON_IDLE_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_MEMFETCH_DEBUG_STATUS_0_B_Y_SSM_NON_IDLE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_B_WINBUF_BD_MEMFETCH_DEBUG_STATUS_0_B_Y_SSM_NON_IDLE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_MEMFETCH_DEBUG_STATUS_0_B_Y_SSM_NON_IDLE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINBUF_BD_MEMFETCH_DEBUG_STATUS_0_B_U_SSM_NON_IDLE_SHIFT _MK_SHIFT_CONST(5) +#define DC_B_WINBUF_BD_MEMFETCH_DEBUG_STATUS_0_B_U_SSM_NON_IDLE_FIELD _MK_FIELD_CONST(0x1, DC_B_WINBUF_BD_MEMFETCH_DEBUG_STATUS_0_B_U_SSM_NON_IDLE_SHIFT) +#define DC_B_WINBUF_BD_MEMFETCH_DEBUG_STATUS_0_B_U_SSM_NON_IDLE_RANGE 5:5 +#define DC_B_WINBUF_BD_MEMFETCH_DEBUG_STATUS_0_B_U_SSM_NON_IDLE_WOFFSET 0x0 +#define DC_B_WINBUF_BD_MEMFETCH_DEBUG_STATUS_0_B_U_SSM_NON_IDLE_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_MEMFETCH_DEBUG_STATUS_0_B_U_SSM_NON_IDLE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_B_WINBUF_BD_MEMFETCH_DEBUG_STATUS_0_B_U_SSM_NON_IDLE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_MEMFETCH_DEBUG_STATUS_0_B_U_SSM_NON_IDLE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINBUF_BD_MEMFETCH_DEBUG_STATUS_0_B_V_SSM_NON_IDLE_SHIFT _MK_SHIFT_CONST(6) +#define DC_B_WINBUF_BD_MEMFETCH_DEBUG_STATUS_0_B_V_SSM_NON_IDLE_FIELD _MK_FIELD_CONST(0x1, DC_B_WINBUF_BD_MEMFETCH_DEBUG_STATUS_0_B_V_SSM_NON_IDLE_SHIFT) +#define DC_B_WINBUF_BD_MEMFETCH_DEBUG_STATUS_0_B_V_SSM_NON_IDLE_RANGE 6:6 +#define DC_B_WINBUF_BD_MEMFETCH_DEBUG_STATUS_0_B_V_SSM_NON_IDLE_WOFFSET 0x0 +#define DC_B_WINBUF_BD_MEMFETCH_DEBUG_STATUS_0_B_V_SSM_NON_IDLE_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_MEMFETCH_DEBUG_STATUS_0_B_V_SSM_NON_IDLE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_B_WINBUF_BD_MEMFETCH_DEBUG_STATUS_0_B_V_SSM_NON_IDLE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_MEMFETCH_DEBUG_STATUS_0_B_V_SSM_NON_IDLE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINBUF_BD_MEMFETCH_DEBUG_STATUS_0_B_DP_VALID_NON_IDLE_SHIFT _MK_SHIFT_CONST(7) +#define DC_B_WINBUF_BD_MEMFETCH_DEBUG_STATUS_0_B_DP_VALID_NON_IDLE_FIELD _MK_FIELD_CONST(0x1, DC_B_WINBUF_BD_MEMFETCH_DEBUG_STATUS_0_B_DP_VALID_NON_IDLE_SHIFT) +#define DC_B_WINBUF_BD_MEMFETCH_DEBUG_STATUS_0_B_DP_VALID_NON_IDLE_RANGE 7:7 +#define DC_B_WINBUF_BD_MEMFETCH_DEBUG_STATUS_0_B_DP_VALID_NON_IDLE_WOFFSET 0x0 +#define DC_B_WINBUF_BD_MEMFETCH_DEBUG_STATUS_0_B_DP_VALID_NON_IDLE_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_MEMFETCH_DEBUG_STATUS_0_B_DP_VALID_NON_IDLE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_B_WINBUF_BD_MEMFETCH_DEBUG_STATUS_0_B_DP_VALID_NON_IDLE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_MEMFETCH_DEBUG_STATUS_0_B_DP_VALID_NON_IDLE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINBUF_BD_MEMFETCH_DEBUG_STATUS_0_B_REQ_FIFO_NON_IDLE_SHIFT _MK_SHIFT_CONST(8) +#define DC_B_WINBUF_BD_MEMFETCH_DEBUG_STATUS_0_B_REQ_FIFO_NON_IDLE_FIELD _MK_FIELD_CONST(0x1, DC_B_WINBUF_BD_MEMFETCH_DEBUG_STATUS_0_B_REQ_FIFO_NON_IDLE_SHIFT) +#define DC_B_WINBUF_BD_MEMFETCH_DEBUG_STATUS_0_B_REQ_FIFO_NON_IDLE_RANGE 8:8 +#define DC_B_WINBUF_BD_MEMFETCH_DEBUG_STATUS_0_B_REQ_FIFO_NON_IDLE_WOFFSET 0x0 +#define DC_B_WINBUF_BD_MEMFETCH_DEBUG_STATUS_0_B_REQ_FIFO_NON_IDLE_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_MEMFETCH_DEBUG_STATUS_0_B_REQ_FIFO_NON_IDLE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_B_WINBUF_BD_MEMFETCH_DEBUG_STATUS_0_B_REQ_FIFO_NON_IDLE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_MEMFETCH_DEBUG_STATUS_0_B_REQ_FIFO_NON_IDLE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINBUF_BD_MEMFETCH_DEBUG_STATUS_0_B_RSP_FIFO_NON_IDLE_SHIFT _MK_SHIFT_CONST(9) +#define DC_B_WINBUF_BD_MEMFETCH_DEBUG_STATUS_0_B_RSP_FIFO_NON_IDLE_FIELD _MK_FIELD_CONST(0x1, DC_B_WINBUF_BD_MEMFETCH_DEBUG_STATUS_0_B_RSP_FIFO_NON_IDLE_SHIFT) +#define DC_B_WINBUF_BD_MEMFETCH_DEBUG_STATUS_0_B_RSP_FIFO_NON_IDLE_RANGE 9:9 +#define DC_B_WINBUF_BD_MEMFETCH_DEBUG_STATUS_0_B_RSP_FIFO_NON_IDLE_WOFFSET 0x0 +#define DC_B_WINBUF_BD_MEMFETCH_DEBUG_STATUS_0_B_RSP_FIFO_NON_IDLE_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_MEMFETCH_DEBUG_STATUS_0_B_RSP_FIFO_NON_IDLE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_B_WINBUF_BD_MEMFETCH_DEBUG_STATUS_0_B_RSP_FIFO_NON_IDLE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_MEMFETCH_DEBUG_STATUS_0_B_RSP_FIFO_NON_IDLE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINBUF_BD_MEMFETCH_DEBUG_STATUS_0_B_TAG_FIFO_NON_IDLE_SHIFT _MK_SHIFT_CONST(10) +#define DC_B_WINBUF_BD_MEMFETCH_DEBUG_STATUS_0_B_TAG_FIFO_NON_IDLE_FIELD _MK_FIELD_CONST(0x1, DC_B_WINBUF_BD_MEMFETCH_DEBUG_STATUS_0_B_TAG_FIFO_NON_IDLE_SHIFT) +#define DC_B_WINBUF_BD_MEMFETCH_DEBUG_STATUS_0_B_TAG_FIFO_NON_IDLE_RANGE 10:10 +#define DC_B_WINBUF_BD_MEMFETCH_DEBUG_STATUS_0_B_TAG_FIFO_NON_IDLE_WOFFSET 0x0 +#define DC_B_WINBUF_BD_MEMFETCH_DEBUG_STATUS_0_B_TAG_FIFO_NON_IDLE_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_MEMFETCH_DEBUG_STATUS_0_B_TAG_FIFO_NON_IDLE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_B_WINBUF_BD_MEMFETCH_DEBUG_STATUS_0_B_TAG_FIFO_NON_IDLE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_MEMFETCH_DEBUG_STATUS_0_B_TAG_FIFO_NON_IDLE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINBUF_BD_MEMFETCH_DEBUG_STATUS_0_B_SURFACE_FIFO_NON_IDLE_SHIFT _MK_SHIFT_CONST(11) +#define DC_B_WINBUF_BD_MEMFETCH_DEBUG_STATUS_0_B_SURFACE_FIFO_NON_IDLE_FIELD _MK_FIELD_CONST(0x1, DC_B_WINBUF_BD_MEMFETCH_DEBUG_STATUS_0_B_SURFACE_FIFO_NON_IDLE_SHIFT) +#define DC_B_WINBUF_BD_MEMFETCH_DEBUG_STATUS_0_B_SURFACE_FIFO_NON_IDLE_RANGE 11:11 +#define DC_B_WINBUF_BD_MEMFETCH_DEBUG_STATUS_0_B_SURFACE_FIFO_NON_IDLE_WOFFSET 0x0 +#define DC_B_WINBUF_BD_MEMFETCH_DEBUG_STATUS_0_B_SURFACE_FIFO_NON_IDLE_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_MEMFETCH_DEBUG_STATUS_0_B_SURFACE_FIFO_NON_IDLE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_B_WINBUF_BD_MEMFETCH_DEBUG_STATUS_0_B_SURFACE_FIFO_NON_IDLE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_MEMFETCH_DEBUG_STATUS_0_B_SURFACE_FIFO_NON_IDLE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINBUF_BD_MEMFETCH_DEBUG_STATUS_0_B_FRAME_FIFO_NON_IDLE_SHIFT _MK_SHIFT_CONST(12) +#define DC_B_WINBUF_BD_MEMFETCH_DEBUG_STATUS_0_B_FRAME_FIFO_NON_IDLE_FIELD _MK_FIELD_CONST(0x1, DC_B_WINBUF_BD_MEMFETCH_DEBUG_STATUS_0_B_FRAME_FIFO_NON_IDLE_SHIFT) +#define DC_B_WINBUF_BD_MEMFETCH_DEBUG_STATUS_0_B_FRAME_FIFO_NON_IDLE_RANGE 12:12 +#define DC_B_WINBUF_BD_MEMFETCH_DEBUG_STATUS_0_B_FRAME_FIFO_NON_IDLE_WOFFSET 0x0 +#define DC_B_WINBUF_BD_MEMFETCH_DEBUG_STATUS_0_B_FRAME_FIFO_NON_IDLE_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_MEMFETCH_DEBUG_STATUS_0_B_FRAME_FIFO_NON_IDLE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_B_WINBUF_BD_MEMFETCH_DEBUG_STATUS_0_B_FRAME_FIFO_NON_IDLE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_MEMFETCH_DEBUG_STATUS_0_B_FRAME_FIFO_NON_IDLE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINBUF_BD_MEMFETCH_DEBUG_STATUS_0_B_PIPE0_FIFO_NON_IDLE_SHIFT _MK_SHIFT_CONST(13) +#define DC_B_WINBUF_BD_MEMFETCH_DEBUG_STATUS_0_B_PIPE0_FIFO_NON_IDLE_FIELD _MK_FIELD_CONST(0x1, DC_B_WINBUF_BD_MEMFETCH_DEBUG_STATUS_0_B_PIPE0_FIFO_NON_IDLE_SHIFT) +#define DC_B_WINBUF_BD_MEMFETCH_DEBUG_STATUS_0_B_PIPE0_FIFO_NON_IDLE_RANGE 13:13 +#define DC_B_WINBUF_BD_MEMFETCH_DEBUG_STATUS_0_B_PIPE0_FIFO_NON_IDLE_WOFFSET 0x0 +#define DC_B_WINBUF_BD_MEMFETCH_DEBUG_STATUS_0_B_PIPE0_FIFO_NON_IDLE_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_MEMFETCH_DEBUG_STATUS_0_B_PIPE0_FIFO_NON_IDLE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_B_WINBUF_BD_MEMFETCH_DEBUG_STATUS_0_B_PIPE0_FIFO_NON_IDLE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_MEMFETCH_DEBUG_STATUS_0_B_PIPE0_FIFO_NON_IDLE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINBUF_BD_MEMFETCH_DEBUG_STATUS_0_B_PIPE1_FIFO_NON_IDLE_SHIFT _MK_SHIFT_CONST(14) +#define DC_B_WINBUF_BD_MEMFETCH_DEBUG_STATUS_0_B_PIPE1_FIFO_NON_IDLE_FIELD _MK_FIELD_CONST(0x1, DC_B_WINBUF_BD_MEMFETCH_DEBUG_STATUS_0_B_PIPE1_FIFO_NON_IDLE_SHIFT) +#define DC_B_WINBUF_BD_MEMFETCH_DEBUG_STATUS_0_B_PIPE1_FIFO_NON_IDLE_RANGE 14:14 +#define DC_B_WINBUF_BD_MEMFETCH_DEBUG_STATUS_0_B_PIPE1_FIFO_NON_IDLE_WOFFSET 0x0 +#define DC_B_WINBUF_BD_MEMFETCH_DEBUG_STATUS_0_B_PIPE1_FIFO_NON_IDLE_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_MEMFETCH_DEBUG_STATUS_0_B_PIPE1_FIFO_NON_IDLE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_B_WINBUF_BD_MEMFETCH_DEBUG_STATUS_0_B_PIPE1_FIFO_NON_IDLE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_MEMFETCH_DEBUG_STATUS_0_B_PIPE1_FIFO_NON_IDLE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINBUF_BD_MEMFETCH_DEBUG_STATUS_0_B_ALIGN_FIFO_NON_IDLE_SHIFT _MK_SHIFT_CONST(15) +#define DC_B_WINBUF_BD_MEMFETCH_DEBUG_STATUS_0_B_ALIGN_FIFO_NON_IDLE_FIELD _MK_FIELD_CONST(0x1, DC_B_WINBUF_BD_MEMFETCH_DEBUG_STATUS_0_B_ALIGN_FIFO_NON_IDLE_SHIFT) +#define DC_B_WINBUF_BD_MEMFETCH_DEBUG_STATUS_0_B_ALIGN_FIFO_NON_IDLE_RANGE 15:15 +#define DC_B_WINBUF_BD_MEMFETCH_DEBUG_STATUS_0_B_ALIGN_FIFO_NON_IDLE_WOFFSET 0x0 +#define DC_B_WINBUF_BD_MEMFETCH_DEBUG_STATUS_0_B_ALIGN_FIFO_NON_IDLE_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_MEMFETCH_DEBUG_STATUS_0_B_ALIGN_FIFO_NON_IDLE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_B_WINBUF_BD_MEMFETCH_DEBUG_STATUS_0_B_ALIGN_FIFO_NON_IDLE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_MEMFETCH_DEBUG_STATUS_0_B_ALIGN_FIFO_NON_IDLE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DC_B_WINBUF_BD_MEMFETCH_DEBUG_STATUS_0_BD_DEBUG_ENABLE_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINBUF_BD_MEMFETCH_DEBUG_STATUS_0_BD_DEBUG_ENABLE_FIELD _MK_FIELD_CONST(0x1, DC_B_WINBUF_BD_MEMFETCH_DEBUG_STATUS_0_BD_DEBUG_ENABLE_SHIFT) +#define DC_B_WINBUF_BD_MEMFETCH_DEBUG_STATUS_0_BD_DEBUG_ENABLE_RANGE 16:16 +#define DC_B_WINBUF_BD_MEMFETCH_DEBUG_STATUS_0_BD_DEBUG_ENABLE_WOFFSET 0x0 +#define DC_B_WINBUF_BD_MEMFETCH_DEBUG_STATUS_0_BD_DEBUG_ENABLE_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_MEMFETCH_DEBUG_STATUS_0_BD_DEBUG_ENABLE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_B_WINBUF_BD_MEMFETCH_DEBUG_STATUS_0_BD_DEBUG_ENABLE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_MEMFETCH_DEBUG_STATUS_0_BD_DEBUG_ENABLE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_B_WINBUF_BD_MEMFETCH_CONTROL_0 +#define DC_B_WINBUF_BD_MEMFETCH_CONTROL_0 _MK_ADDR_CONST(0xdeb) +#define DC_B_WINBUF_BD_MEMFETCH_CONTROL_0_SECURE 0x0 +#define DC_B_WINBUF_BD_MEMFETCH_CONTROL_0_WORD_COUNT 0x1 +#define DC_B_WINBUF_BD_MEMFETCH_CONTROL_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_MEMFETCH_CONTROL_0_RESET_MASK _MK_MASK_CONST(0x3) +#define DC_B_WINBUF_BD_MEMFETCH_CONTROL_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x1) +#define DC_B_WINBUF_BD_MEMFETCH_CONTROL_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_B_WINBUF_BD_MEMFETCH_CONTROL_0_READ_MASK _MK_MASK_CONST(0x3) +#define DC_B_WINBUF_BD_MEMFETCH_CONTROL_0_WRITE_MASK _MK_MASK_CONST(0x3) +#define DC_B_WINBUF_BD_MEMFETCH_CONTROL_0_BD_MEMFETCH_RESET_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINBUF_BD_MEMFETCH_CONTROL_0_BD_MEMFETCH_RESET_FIELD _MK_FIELD_CONST(0x1, DC_B_WINBUF_BD_MEMFETCH_CONTROL_0_BD_MEMFETCH_RESET_SHIFT) +#define DC_B_WINBUF_BD_MEMFETCH_CONTROL_0_BD_MEMFETCH_RESET_RANGE 0:0 +#define DC_B_WINBUF_BD_MEMFETCH_CONTROL_0_BD_MEMFETCH_RESET_WOFFSET 0x0 +#define DC_B_WINBUF_BD_MEMFETCH_CONTROL_0_BD_MEMFETCH_RESET_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_MEMFETCH_CONTROL_0_BD_MEMFETCH_RESET_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_B_WINBUF_BD_MEMFETCH_CONTROL_0_BD_MEMFETCH_RESET_SW_DEFAULT _MK_MASK_CONST(0x1) +#define DC_B_WINBUF_BD_MEMFETCH_CONTROL_0_BD_MEMFETCH_RESET_SW_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_B_WINBUF_BD_MEMFETCH_CONTROL_0_BD_MEMFETCH_RESET_DISABLE _MK_ENUM_CONST(0) +#define DC_B_WINBUF_BD_MEMFETCH_CONTROL_0_BD_MEMFETCH_RESET_ENABLE _MK_ENUM_CONST(1) + +#define DC_B_WINBUF_BD_MEMFETCH_CONTROL_0_BD_MEMFETCH_CLK_GATE_OVERRIDE_SHIFT _MK_SHIFT_CONST(1) +#define DC_B_WINBUF_BD_MEMFETCH_CONTROL_0_BD_MEMFETCH_CLK_GATE_OVERRIDE_FIELD _MK_FIELD_CONST(0x1, DC_B_WINBUF_BD_MEMFETCH_CONTROL_0_BD_MEMFETCH_CLK_GATE_OVERRIDE_SHIFT) +#define DC_B_WINBUF_BD_MEMFETCH_CONTROL_0_BD_MEMFETCH_CLK_GATE_OVERRIDE_RANGE 1:1 +#define DC_B_WINBUF_BD_MEMFETCH_CONTROL_0_BD_MEMFETCH_CLK_GATE_OVERRIDE_WOFFSET 0x0 +#define DC_B_WINBUF_BD_MEMFETCH_CONTROL_0_BD_MEMFETCH_CLK_GATE_OVERRIDE_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_MEMFETCH_CONTROL_0_BD_MEMFETCH_CLK_GATE_OVERRIDE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_B_WINBUF_BD_MEMFETCH_CONTROL_0_BD_MEMFETCH_CLK_GATE_OVERRIDE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_MEMFETCH_CONTROL_0_BD_MEMFETCH_CLK_GATE_OVERRIDE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_MEMFETCH_CONTROL_0_BD_MEMFETCH_CLK_GATE_OVERRIDE_DISABLE _MK_ENUM_CONST(0) +#define DC_B_WINBUF_BD_MEMFETCH_CONTROL_0_BD_MEMFETCH_CLK_GATE_OVERRIDE_ENABLE _MK_ENUM_CONST(1) + + +// Register DC_B_WINBUF_BD_OCCUPANCY_THROTTLE_0 +#define DC_B_WINBUF_BD_OCCUPANCY_THROTTLE_0 _MK_ADDR_CONST(0xdec) +#define DC_B_WINBUF_BD_OCCUPANCY_THROTTLE_0_SECURE 0x0 +#define DC_B_WINBUF_BD_OCCUPANCY_THROTTLE_0_WORD_COUNT 0x1 +#define DC_B_WINBUF_BD_OCCUPANCY_THROTTLE_0_RESET_VAL _MK_MASK_CONST(0xffff0000) +#define DC_B_WINBUF_BD_OCCUPANCY_THROTTLE_0_RESET_MASK _MK_MASK_CONST(0xffff0001) +#define DC_B_WINBUF_BD_OCCUPANCY_THROTTLE_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_OCCUPANCY_THROTTLE_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_OCCUPANCY_THROTTLE_0_READ_MASK _MK_MASK_CONST(0xffff0001) +#define DC_B_WINBUF_BD_OCCUPANCY_THROTTLE_0_WRITE_MASK _MK_MASK_CONST(0xffff0001) +#define DC_B_WINBUF_BD_OCCUPANCY_THROTTLE_0_BD_OCCUPANCY_THROTTLE_MODE_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINBUF_BD_OCCUPANCY_THROTTLE_0_BD_OCCUPANCY_THROTTLE_MODE_FIELD _MK_FIELD_CONST(0x1, DC_B_WINBUF_BD_OCCUPANCY_THROTTLE_0_BD_OCCUPANCY_THROTTLE_MODE_SHIFT) +#define DC_B_WINBUF_BD_OCCUPANCY_THROTTLE_0_BD_OCCUPANCY_THROTTLE_MODE_RANGE 0:0 +#define DC_B_WINBUF_BD_OCCUPANCY_THROTTLE_0_BD_OCCUPANCY_THROTTLE_MODE_WOFFSET 0x0 +#define DC_B_WINBUF_BD_OCCUPANCY_THROTTLE_0_BD_OCCUPANCY_THROTTLE_MODE_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_OCCUPANCY_THROTTLE_0_BD_OCCUPANCY_THROTTLE_MODE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DC_B_WINBUF_BD_OCCUPANCY_THROTTLE_0_BD_OCCUPANCY_THROTTLE_MODE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_OCCUPANCY_THROTTLE_0_BD_OCCUPANCY_THROTTLE_MODE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_OCCUPANCY_THROTTLE_0_BD_OCCUPANCY_THROTTLE_MODE_DISABLE _MK_ENUM_CONST(0) +#define DC_B_WINBUF_BD_OCCUPANCY_THROTTLE_0_BD_OCCUPANCY_THROTTLE_MODE_ENABLE _MK_ENUM_CONST(1) + +#define DC_B_WINBUF_BD_OCCUPANCY_THROTTLE_0_BD_OCCUPANCY_MAX_THRESHOLD_SHIFT _MK_SHIFT_CONST(16) +#define DC_B_WINBUF_BD_OCCUPANCY_THROTTLE_0_BD_OCCUPANCY_MAX_THRESHOLD_FIELD _MK_FIELD_CONST(0xffff, DC_B_WINBUF_BD_OCCUPANCY_THROTTLE_0_BD_OCCUPANCY_MAX_THRESHOLD_SHIFT) +#define DC_B_WINBUF_BD_OCCUPANCY_THROTTLE_0_BD_OCCUPANCY_MAX_THRESHOLD_RANGE 31:16 +#define DC_B_WINBUF_BD_OCCUPANCY_THROTTLE_0_BD_OCCUPANCY_MAX_THRESHOLD_WOFFSET 0x0 +#define DC_B_WINBUF_BD_OCCUPANCY_THROTTLE_0_BD_OCCUPANCY_MAX_THRESHOLD_DEFAULT _MK_MASK_CONST(0xffff) +#define DC_B_WINBUF_BD_OCCUPANCY_THROTTLE_0_BD_OCCUPANCY_MAX_THRESHOLD_DEFAULT_MASK _MK_MASK_CONST(0xffff) +#define DC_B_WINBUF_BD_OCCUPANCY_THROTTLE_0_BD_OCCUPANCY_MAX_THRESHOLD_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_OCCUPANCY_THROTTLE_0_BD_OCCUPANCY_MAX_THRESHOLD_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_B_WINBUF_BD_SCRATCH_REGISTER_0_0 +#define DC_B_WINBUF_BD_SCRATCH_REGISTER_0_0 _MK_ADDR_CONST(0xded) +#define DC_B_WINBUF_BD_SCRATCH_REGISTER_0_0_SECURE 0x0 +#define DC_B_WINBUF_BD_SCRATCH_REGISTER_0_0_WORD_COUNT 0x1 +#define DC_B_WINBUF_BD_SCRATCH_REGISTER_0_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_SCRATCH_REGISTER_0_0_RESET_MASK _MK_MASK_CONST(0xffffffff) +#define DC_B_WINBUF_BD_SCRATCH_REGISTER_0_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_SCRATCH_REGISTER_0_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_SCRATCH_REGISTER_0_0_READ_MASK _MK_MASK_CONST(0xffffffff) +#define DC_B_WINBUF_BD_SCRATCH_REGISTER_0_0_WRITE_MASK _MK_MASK_CONST(0xffffffff) +#define DC_B_WINBUF_BD_SCRATCH_REGISTER_0_0_BD_SCRATCH_REGISTER_0_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINBUF_BD_SCRATCH_REGISTER_0_0_BD_SCRATCH_REGISTER_0_FIELD _MK_FIELD_CONST(0xffffffff, DC_B_WINBUF_BD_SCRATCH_REGISTER_0_0_BD_SCRATCH_REGISTER_0_SHIFT) +#define DC_B_WINBUF_BD_SCRATCH_REGISTER_0_0_BD_SCRATCH_REGISTER_0_RANGE 31:0 +#define DC_B_WINBUF_BD_SCRATCH_REGISTER_0_0_BD_SCRATCH_REGISTER_0_WOFFSET 0x0 +#define DC_B_WINBUF_BD_SCRATCH_REGISTER_0_0_BD_SCRATCH_REGISTER_0_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_SCRATCH_REGISTER_0_0_BD_SCRATCH_REGISTER_0_DEFAULT_MASK _MK_MASK_CONST(0xffffffff) +#define DC_B_WINBUF_BD_SCRATCH_REGISTER_0_0_BD_SCRATCH_REGISTER_0_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_SCRATCH_REGISTER_0_0_BD_SCRATCH_REGISTER_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DC_B_WINBUF_BD_SCRATCH_REGISTER_1_0 +#define DC_B_WINBUF_BD_SCRATCH_REGISTER_1_0 _MK_ADDR_CONST(0xdee) +#define DC_B_WINBUF_BD_SCRATCH_REGISTER_1_0_SECURE 0x0 +#define DC_B_WINBUF_BD_SCRATCH_REGISTER_1_0_WORD_COUNT 0x1 +#define DC_B_WINBUF_BD_SCRATCH_REGISTER_1_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_SCRATCH_REGISTER_1_0_RESET_MASK _MK_MASK_CONST(0xffffffff) +#define DC_B_WINBUF_BD_SCRATCH_REGISTER_1_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_SCRATCH_REGISTER_1_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_SCRATCH_REGISTER_1_0_READ_MASK _MK_MASK_CONST(0xffffffff) +#define DC_B_WINBUF_BD_SCRATCH_REGISTER_1_0_WRITE_MASK _MK_MASK_CONST(0xffffffff) +#define DC_B_WINBUF_BD_SCRATCH_REGISTER_1_0_BD_SCRATCH_REGISTER_1_SHIFT _MK_SHIFT_CONST(0) +#define DC_B_WINBUF_BD_SCRATCH_REGISTER_1_0_BD_SCRATCH_REGISTER_1_FIELD _MK_FIELD_CONST(0xffffffff, DC_B_WINBUF_BD_SCRATCH_REGISTER_1_0_BD_SCRATCH_REGISTER_1_SHIFT) +#define DC_B_WINBUF_BD_SCRATCH_REGISTER_1_0_BD_SCRATCH_REGISTER_1_RANGE 31:0 +#define DC_B_WINBUF_BD_SCRATCH_REGISTER_1_0_BD_SCRATCH_REGISTER_1_WOFFSET 0x0 +#define DC_B_WINBUF_BD_SCRATCH_REGISTER_1_0_BD_SCRATCH_REGISTER_1_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_SCRATCH_REGISTER_1_0_BD_SCRATCH_REGISTER_1_DEFAULT_MASK _MK_MASK_CONST(0xffffffff) +#define DC_B_WINBUF_BD_SCRATCH_REGISTER_1_0_BD_SCRATCH_REGISTER_1_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DC_B_WINBUF_BD_SCRATCH_REGISTER_1_0_BD_SCRATCH_REGISTER_1_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// +// REGISTER LIST +// +#define LIST_ARDISPLAY_BD_REGS(_op_) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_0) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_1) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_2) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_3) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_4) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_5) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_6) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_7) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_8) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_9) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_10) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_11) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_12) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_13) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_14) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_15) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_16) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_17) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_18) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_19) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_20) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_21) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_22) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_23) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_24) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_25) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_26) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_27) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_28) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_29) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_30) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_31) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_32) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_33) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_34) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_35) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_36) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_37) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_38) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_39) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_40) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_41) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_42) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_43) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_44) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_45) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_46) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_47) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_48) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_49) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_50) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_51) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_52) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_53) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_54) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_55) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_56) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_57) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_58) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_59) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_60) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_61) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_62) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_63) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_64) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_65) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_66) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_67) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_68) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_69) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_70) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_71) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_72) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_73) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_74) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_75) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_76) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_77) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_78) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_79) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_80) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_81) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_82) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_83) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_84) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_85) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_86) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_87) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_88) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_89) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_90) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_91) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_92) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_93) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_94) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_95) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_96) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_97) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_98) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_99) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_100) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_101) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_102) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_103) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_104) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_105) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_106) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_107) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_108) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_109) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_110) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_111) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_112) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_113) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_114) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_115) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_116) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_117) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_118) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_119) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_120) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_121) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_122) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_123) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_124) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_125) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_126) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_127) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_128) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_129) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_130) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_131) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_132) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_133) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_134) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_135) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_136) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_137) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_138) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_139) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_140) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_141) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_142) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_143) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_144) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_145) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_146) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_147) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_148) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_149) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_150) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_151) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_152) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_153) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_154) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_155) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_156) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_157) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_158) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_159) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_160) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_161) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_162) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_163) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_164) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_165) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_166) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_167) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_168) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_169) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_170) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_171) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_172) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_173) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_174) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_175) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_176) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_177) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_178) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_179) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_180) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_181) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_182) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_183) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_184) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_185) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_186) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_187) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_188) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_189) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_190) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_191) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_192) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_193) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_194) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_195) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_196) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_197) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_198) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_199) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_200) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_201) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_202) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_203) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_204) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_205) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_206) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_207) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_208) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_209) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_210) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_211) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_212) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_213) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_214) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_215) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_216) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_217) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_218) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_219) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_220) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_221) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_222) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_223) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_224) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_225) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_226) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_227) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_228) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_229) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_230) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_231) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_232) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_233) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_234) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_235) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_236) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_237) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_238) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_239) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_240) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_241) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_242) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_243) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_244) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_245) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_246) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_247) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_248) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_249) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_250) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_251) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_252) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_253) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_254) \ +_op_(DC_B_WINC_BD_COLOR_PALETTE_255) \ +_op_(DC_B_WINC_BD_PALETTE_COLOR_EXT_0) \ +_op_(DC_B_WINC_BD_H_FILTER_P00_0) \ +_op_(DC_B_WINC_BD_H_FILTER_P01_0) \ +_op_(DC_B_WINC_BD_H_FILTER_P02_0) \ +_op_(DC_B_WINC_BD_H_FILTER_P03_0) \ +_op_(DC_B_WINC_BD_H_FILTER_P04_0) \ +_op_(DC_B_WINC_BD_H_FILTER_P05_0) \ +_op_(DC_B_WINC_BD_H_FILTER_P06_0) \ +_op_(DC_B_WINC_BD_H_FILTER_P07_0) \ +_op_(DC_B_WINC_BD_H_FILTER_P08_0) \ +_op_(DC_B_WINC_BD_H_FILTER_P09_0) \ +_op_(DC_B_WINC_BD_H_FILTER_P0A_0) \ +_op_(DC_B_WINC_BD_H_FILTER_P0B_0) \ +_op_(DC_B_WINC_BD_H_FILTER_P0C_0) \ +_op_(DC_B_WINC_BD_H_FILTER_P0D_0) \ +_op_(DC_B_WINC_BD_H_FILTER_P0E_0) \ +_op_(DC_B_WINC_BD_H_FILTER_P0F_0) \ +_op_(DC_B_WINC_BD_CSC_YOF_0) \ +_op_(DC_B_WINC_BD_CSC_KYRGB_0) \ +_op_(DC_B_WINC_BD_CSC_KUR_0) \ +_op_(DC_B_WINC_BD_CSC_KVR_0) \ +_op_(DC_B_WINC_BD_CSC_KUG_0) \ +_op_(DC_B_WINC_BD_CSC_KVG_0) \ +_op_(DC_B_WINC_BD_CSC_KUB_0) \ +_op_(DC_B_WINC_BD_CSC_KVB_0) \ +_op_(DC_B_WINC_BD_V_FILTER_P00_0) \ +_op_(DC_B_WINC_BD_V_FILTER_P01_0) \ +_op_(DC_B_WINC_BD_V_FILTER_P02_0) \ +_op_(DC_B_WINC_BD_V_FILTER_P03_0) \ +_op_(DC_B_WINC_BD_V_FILTER_P04_0) \ +_op_(DC_B_WINC_BD_V_FILTER_P05_0) \ +_op_(DC_B_WINC_BD_V_FILTER_P06_0) \ +_op_(DC_B_WINC_BD_V_FILTER_P07_0) \ +_op_(DC_B_WINC_BD_V_FILTER_P08_0) \ +_op_(DC_B_WINC_BD_V_FILTER_P09_0) \ +_op_(DC_B_WINC_BD_V_FILTER_P0A_0) \ +_op_(DC_B_WINC_BD_V_FILTER_P0B_0) \ +_op_(DC_B_WINC_BD_V_FILTER_P0C_0) \ +_op_(DC_B_WINC_BD_V_FILTER_P0D_0) \ +_op_(DC_B_WINC_BD_V_FILTER_P0E_0) \ +_op_(DC_B_WINC_BD_V_FILTER_P0F_0) \ +_op_(DC_B_WINC_BD_H_FILTER_HI_P00_0) \ +_op_(DC_B_WINC_BD_H_FILTER_HI_P01_0) \ +_op_(DC_B_WINC_BD_H_FILTER_HI_P02_0) \ +_op_(DC_B_WINC_BD_H_FILTER_HI_P03_0) \ +_op_(DC_B_WINC_BD_H_FILTER_HI_P04_0) \ +_op_(DC_B_WINC_BD_H_FILTER_HI_P05_0) \ +_op_(DC_B_WINC_BD_H_FILTER_HI_P06_0) \ +_op_(DC_B_WINC_BD_H_FILTER_HI_P07_0) \ +_op_(DC_B_WINC_BD_H_FILTER_HI_P08_0) \ +_op_(DC_B_WINC_BD_H_FILTER_HI_P09_0) \ +_op_(DC_B_WINC_BD_H_FILTER_HI_P0A_0) \ +_op_(DC_B_WINC_BD_H_FILTER_HI_P0B_0) \ +_op_(DC_B_WINC_BD_H_FILTER_HI_P0C_0) \ +_op_(DC_B_WINC_BD_H_FILTER_HI_P0D_0) \ +_op_(DC_B_WINC_BD_H_FILTER_HI_P0E_0) \ +_op_(DC_B_WINC_BD_H_FILTER_HI_P0F_0) \ +_op_(DC_B_WIN_BD_WIN_OPTIONS_0) \ +_op_(DC_B_WIN_BD_BYTE_SWAP_0) \ +_op_(DC_B_WIN_BD_BUFFER_CONTROL_0) \ +_op_(DC_B_WIN_BD_COLOR_DEPTH_0) \ +_op_(DC_B_WIN_BD_POSITION_0) \ +_op_(DC_B_WIN_BD_SIZE_0) \ +_op_(DC_B_WIN_BD_PRESCALED_SIZE_0) \ +_op_(DC_B_WIN_BD_H_INITIAL_DDA_0) \ +_op_(DC_B_WIN_BD_V_INITIAL_DDA_0) \ +_op_(DC_B_WIN_BD_DDA_INCREMENT_0) \ +_op_(DC_B_WIN_BD_LINE_STRIDE_0) \ +_op_(DC_B_WIN_BD_DV_CONTROL_0) \ +_op_(DC_B_WIN_BD_BLEND_LAYER_CONTROL_0) \ +_op_(DC_B_WIN_BD_BLEND_MATCH_SELECT_0) \ +_op_(DC_B_WIN_BD_BLEND_NOMATCH_SELECT_0) \ +_op_(DC_B_WIN_BD_BLEND_ALPHA_1BIT_0) \ +_op_(DC_B_WINBUF_BD_START_ADDR_0) \ +_op_(DC_B_WINBUF_BD_START_ADDR_NS_0) \ +_op_(DC_B_WINBUF_BD_START_ADDR_U_0) \ +_op_(DC_B_WINBUF_BD_START_ADDR_U_NS_0) \ +_op_(DC_B_WINBUF_BD_START_ADDR_V_0) \ +_op_(DC_B_WINBUF_BD_START_ADDR_V_NS_0) \ +_op_(DC_B_WINBUF_BD_ADDR_H_OFFSET_0) \ +_op_(DC_B_WINBUF_BD_ADDR_H_OFFSET_NS_0) \ +_op_(DC_B_WINBUF_BD_ADDR_V_OFFSET_0) \ +_op_(DC_B_WINBUF_BD_ADDR_V_OFFSET_NS_0) \ +_op_(DC_B_WINBUF_BD_UFLOW_STATUS_0) \ +_op_(DC_B_WINBUF_BD_SURFACE_KIND_0) \ +_op_(DC_B_WINBUF_BD_SURFACE_WEIGHT_0) \ +_op_(DC_B_WINBUF_BD_START_ADDR_HI_0) \ +_op_(DC_B_WINBUF_BD_START_ADDR_HI_NS_0) \ +_op_(DC_B_WINBUF_BD_START_ADDR_HI_U_0) \ +_op_(DC_B_WINBUF_BD_START_ADDR_HI_U_NS_0) \ +_op_(DC_B_WINBUF_BD_START_ADDR_HI_V_0) \ +_op_(DC_B_WINBUF_BD_START_ADDR_HI_V_NS_0) \ +_op_(DC_B_WINBUF_BD_START_ADDR_FIELD2_0) \ +_op_(DC_B_WINBUF_BD_START_ADDR_FIELD2_NS_0) \ +_op_(DC_B_WINBUF_BD_START_ADDR_FIELD2_U_0) \ +_op_(DC_B_WINBUF_BD_START_ADDR_FIELD2_U_NS_0) \ +_op_(DC_B_WINBUF_BD_START_ADDR_FIELD2_V_0) \ +_op_(DC_B_WINBUF_BD_START_ADDR_FIELD2_V_NS_0) \ +_op_(DC_B_WINBUF_BD_START_ADDR_FIELD2_HI_0) \ +_op_(DC_B_WINBUF_BD_START_ADDR_FIELD2_HI_NS_0) \ +_op_(DC_B_WINBUF_BD_START_ADDR_FIELD2_HI_U_0) \ +_op_(DC_B_WINBUF_BD_START_ADDR_FIELD2_HI_U_NS_0) \ +_op_(DC_B_WINBUF_BD_START_ADDR_FIELD2_HI_V_0) \ +_op_(DC_B_WINBUF_BD_START_ADDR_FIELD2_HI_V_NS_0) \ +_op_(DC_B_WINBUF_BD_ADDR_H_OFFSET_FIELD2_0) \ +_op_(DC_B_WINBUF_BD_ADDR_H_OFFSET_FIELD2_NS_0) \ +_op_(DC_B_WINBUF_BD_ADDR_V_OFFSET_FIELD2_0) \ +_op_(DC_B_WINBUF_BD_ADDR_V_OFFSET_FIELD2_NS_0) \ +_op_(DC_B_WINBUF_BD_UFLOW_CTRL_0) \ +_op_(DC_B_WINBUF_BD_UFLOW_DBG_PIXEL_0) \ +_op_(DC_B_WINBUF_BD_UFLOW_THRESHOLD_0) \ +_op_(DC_B_WINBUF_BD_SPOOL_UP_0) \ +_op_(DC_B_WINBUF_BD_SCALEFACTOR_THRESHOLD_0) \ +_op_(DC_B_WINBUF_BD_LATENCY_THRESHOLD_0) \ +_op_(DC_B_WINBUF_BD_MEMFETCH_DEBUG_STATUS_0) \ +_op_(DC_B_WINBUF_BD_MEMFETCH_CONTROL_0) \ +_op_(DC_B_WINBUF_BD_OCCUPANCY_THROTTLE_0) \ +_op_(DC_B_WINBUF_BD_SCRATCH_REGISTER_0_0) \ +_op_(DC_B_WINBUF_BD_SCRATCH_REGISTER_1_0) + + +// +// ADDRESS SPACES +// + +#define BASE_ADDRESS_DC_B_WINC 0x00000c00 +#define BASE_ADDRESS_DC_B_WIN 0x00000d80 +#define BASE_ADDRESS_DC_B_WINBUF 0x00000dc0 + +// +// ARDISPLAY_BD REGISTER BANKS +// + +#define DC_B_WINC0_FIRST_REG 0x0c00 // DC_B_WINC_BD_COLOR_PALETTE_0 +#define DC_B_WINC0_LAST_REG 0x0d38 // DC_B_WINC_BD_H_FILTER_HI_P0F_0 +#define DC_B_WIN0_FIRST_REG 0x0d80 // DC_B_WIN_BD_WIN_OPTIONS_0 +#define DC_B_WIN0_LAST_REG 0x0d8a // DC_B_WIN_BD_LINE_STRIDE_0 +#define DC_B_WIN1_FIRST_REG 0x0d8e // DC_B_WIN_BD_DV_CONTROL_0 +#define DC_B_WIN1_LAST_REG 0x0d8e // DC_B_WIN_BD_DV_CONTROL_0 +#define DC_B_WIN2_FIRST_REG 0x0d96 // DC_B_WIN_BD_BLEND_LAYER_CONTROL_0 +#define DC_B_WIN2_LAST_REG 0x0d99 // DC_B_WIN_BD_BLEND_ALPHA_1BIT_0 +#define DC_B_WINBUF0_FIRST_REG 0x0dc0 // DC_B_WINBUF_BD_START_ADDR_0 +#define DC_B_WINBUF0_LAST_REG 0x0de2 // DC_B_WINBUF_BD_ADDR_V_OFFSET_FIELD2_NS_0 +#define DC_B_WINBUF1_FIRST_REG 0x0de4 // DC_B_WINBUF_BD_UFLOW_CTRL_0 +#define DC_B_WINBUF1_LAST_REG 0x0dee // DC_B_WINBUF_BD_SCRATCH_REGISTER_1_0 + +// To satisfy various compilers and platforms, +// we let users control the types and syntax of certain constants, using macros. +#ifndef _MK_SHIFT_CONST + #define _MK_SHIFT_CONST(_constant_) _constant_ +#endif +#ifndef _MK_MASK_CONST + #define _MK_MASK_CONST(_constant_) _constant_ +#endif +#ifndef _MK_ENUM_CONST + #define _MK_ENUM_CONST(_constant_) (_constant_ ## UL) +#endif +#ifndef _MK_ADDR_CONST + #define _MK_ADDR_CONST(_constant_) _constant_ +#endif +#ifndef _MK_FIELD_CONST + #define _MK_FIELD_CONST(_mask_, _shift_) (_MK_MASK_CONST(_mask_) << _MK_SHIFT_CONST(_shift_)) +#endif + +#endif // ifndef ___ARDISPLAY_BD_H_INC_ diff --git a/src/soc/nvidia/tegra124/include/soc/ardpaux.h b/src/soc/nvidia/tegra124/include/soc/ardpaux.h new file mode 100644 index 0000000..7eb7959 --- /dev/null +++ b/src/soc/nvidia/tegra124/include/soc/ardpaux.h @@ -0,0 +1,1865 @@ +// +// Copyright (c) 2013 NVIDIA Corporation. +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// +// Neither the name of the NVIDIA Corporation nor the names of its contributors +// may be used to endorse or promote products derived from this software +// without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// + +// +// DO NOT EDIT - generated by simspec! +// + +#ifndef ___ARDPAUX_H_INC_ +#define ___ARDPAUX_H_INC_ + +// Register DPAUX_CTXSW_0 +#define DPAUX_CTXSW_0 _MK_ADDR_CONST(0x0) +#define DPAUX_CTXSW_0_SECURE 0x0 +#define DPAUX_CTXSW_0_WORD_COUNT 0x1 +#define DPAUX_CTXSW_0_RESET_VAL _MK_MASK_CONST(0xf000f800) +#define DPAUX_CTXSW_0_RESET_MASK _MK_MASK_CONST(0xf3fffbff) +#define DPAUX_CTXSW_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DPAUX_CTXSW_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DPAUX_CTXSW_0_READ_MASK _MK_MASK_CONST(0xf3fffbff) +#define DPAUX_CTXSW_0_WRITE_MASK _MK_MASK_CONST(0xfbff) +#define DPAUX_CTXSW_0_CURR_CLASS_SHIFT _MK_SHIFT_CONST(0) +#define DPAUX_CTXSW_0_CURR_CLASS_FIELD _MK_FIELD_CONST(0x3ff, DPAUX_CTXSW_0_CURR_CLASS_SHIFT) +#define DPAUX_CTXSW_0_CURR_CLASS_RANGE 9:0 +#define DPAUX_CTXSW_0_CURR_CLASS_WOFFSET 0x0 +#define DPAUX_CTXSW_0_CURR_CLASS_DEFAULT _MK_MASK_CONST(0x0) +#define DPAUX_CTXSW_0_CURR_CLASS_DEFAULT_MASK _MK_MASK_CONST(0x3ff) +#define DPAUX_CTXSW_0_CURR_CLASS_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DPAUX_CTXSW_0_CURR_CLASS_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DPAUX_CTXSW_0_AUTO_ACK_SHIFT _MK_SHIFT_CONST(11) +#define DPAUX_CTXSW_0_AUTO_ACK_FIELD _MK_FIELD_CONST(0x1, DPAUX_CTXSW_0_AUTO_ACK_SHIFT) +#define DPAUX_CTXSW_0_AUTO_ACK_RANGE 11:11 +#define DPAUX_CTXSW_0_AUTO_ACK_WOFFSET 0x0 +#define DPAUX_CTXSW_0_AUTO_ACK_DEFAULT _MK_MASK_CONST(0x1) +#define DPAUX_CTXSW_0_AUTO_ACK_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DPAUX_CTXSW_0_AUTO_ACK_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DPAUX_CTXSW_0_AUTO_ACK_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DPAUX_CTXSW_0_AUTO_ACK_MANUAL _MK_ENUM_CONST(0) +#define DPAUX_CTXSW_0_AUTO_ACK_AUTOACK _MK_ENUM_CONST(1) + +#define DPAUX_CTXSW_0_CURR_CHANNEL_SHIFT _MK_SHIFT_CONST(12) +#define DPAUX_CTXSW_0_CURR_CHANNEL_FIELD _MK_FIELD_CONST(0xf, DPAUX_CTXSW_0_CURR_CHANNEL_SHIFT) +#define DPAUX_CTXSW_0_CURR_CHANNEL_RANGE 15:12 +#define DPAUX_CTXSW_0_CURR_CHANNEL_WOFFSET 0x0 +#define DPAUX_CTXSW_0_CURR_CHANNEL_DEFAULT _MK_MASK_CONST(0xf) +#define DPAUX_CTXSW_0_CURR_CHANNEL_DEFAULT_MASK _MK_MASK_CONST(0xf) +#define DPAUX_CTXSW_0_CURR_CHANNEL_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DPAUX_CTXSW_0_CURR_CHANNEL_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DPAUX_CTXSW_0_NEXT_CLASS_SHIFT _MK_SHIFT_CONST(16) +#define DPAUX_CTXSW_0_NEXT_CLASS_FIELD _MK_FIELD_CONST(0x3ff, DPAUX_CTXSW_0_NEXT_CLASS_SHIFT) +#define DPAUX_CTXSW_0_NEXT_CLASS_RANGE 25:16 +#define DPAUX_CTXSW_0_NEXT_CLASS_WOFFSET 0x0 +#define DPAUX_CTXSW_0_NEXT_CLASS_DEFAULT _MK_MASK_CONST(0x0) +#define DPAUX_CTXSW_0_NEXT_CLASS_DEFAULT_MASK _MK_MASK_CONST(0x3ff) +#define DPAUX_CTXSW_0_NEXT_CLASS_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DPAUX_CTXSW_0_NEXT_CLASS_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DPAUX_CTXSW_0_NEXT_CHANNEL_SHIFT _MK_SHIFT_CONST(28) +#define DPAUX_CTXSW_0_NEXT_CHANNEL_FIELD _MK_FIELD_CONST(0xf, DPAUX_CTXSW_0_NEXT_CHANNEL_SHIFT) +#define DPAUX_CTXSW_0_NEXT_CHANNEL_RANGE 31:28 +#define DPAUX_CTXSW_0_NEXT_CHANNEL_WOFFSET 0x0 +#define DPAUX_CTXSW_0_NEXT_CHANNEL_DEFAULT _MK_MASK_CONST(0xf) +#define DPAUX_CTXSW_0_NEXT_CHANNEL_DEFAULT_MASK _MK_MASK_CONST(0xf) +#define DPAUX_CTXSW_0_NEXT_CHANNEL_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DPAUX_CTXSW_0_NEXT_CHANNEL_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DPAUX_INTR_EN_AUX_0 +#define DPAUX_INTR_EN_AUX_0 _MK_ADDR_CONST(0x1) +#define DPAUX_INTR_EN_AUX_0_SECURE 0x0 +#define DPAUX_INTR_EN_AUX_0_WORD_COUNT 0x1 +#define DPAUX_INTR_EN_AUX_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DPAUX_INTR_EN_AUX_0_RESET_MASK _MK_MASK_CONST(0xf) +#define DPAUX_INTR_EN_AUX_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DPAUX_INTR_EN_AUX_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DPAUX_INTR_EN_AUX_0_READ_MASK _MK_MASK_CONST(0xf) +#define DPAUX_INTR_EN_AUX_0_WRITE_MASK _MK_MASK_CONST(0xf) +#define DPAUX_INTR_EN_AUX_0_PLUG_EVENT_SHIFT _MK_SHIFT_CONST(0) +#define DPAUX_INTR_EN_AUX_0_PLUG_EVENT_FIELD _MK_FIELD_CONST(0x1, DPAUX_INTR_EN_AUX_0_PLUG_EVENT_SHIFT) +#define DPAUX_INTR_EN_AUX_0_PLUG_EVENT_RANGE 0:0 +#define DPAUX_INTR_EN_AUX_0_PLUG_EVENT_WOFFSET 0x0 +#define DPAUX_INTR_EN_AUX_0_PLUG_EVENT_DEFAULT _MK_MASK_CONST(0x0) +#define DPAUX_INTR_EN_AUX_0_PLUG_EVENT_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DPAUX_INTR_EN_AUX_0_PLUG_EVENT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DPAUX_INTR_EN_AUX_0_PLUG_EVENT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DPAUX_INTR_EN_AUX_0_PLUG_EVENT_INIT_ENUM DISABLED +#define DPAUX_INTR_EN_AUX_0_PLUG_EVENT_DISABLED _MK_ENUM_CONST(0) +#define DPAUX_INTR_EN_AUX_0_PLUG_EVENT_ENABLED _MK_ENUM_CONST(1) + +#define DPAUX_INTR_EN_AUX_0_UNPLUG_EVENT_SHIFT _MK_SHIFT_CONST(1) +#define DPAUX_INTR_EN_AUX_0_UNPLUG_EVENT_FIELD _MK_FIELD_CONST(0x1, DPAUX_INTR_EN_AUX_0_UNPLUG_EVENT_SHIFT) +#define DPAUX_INTR_EN_AUX_0_UNPLUG_EVENT_RANGE 1:1 +#define DPAUX_INTR_EN_AUX_0_UNPLUG_EVENT_WOFFSET 0x0 +#define DPAUX_INTR_EN_AUX_0_UNPLUG_EVENT_DEFAULT _MK_MASK_CONST(0x0) +#define DPAUX_INTR_EN_AUX_0_UNPLUG_EVENT_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DPAUX_INTR_EN_AUX_0_UNPLUG_EVENT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DPAUX_INTR_EN_AUX_0_UNPLUG_EVENT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DPAUX_INTR_EN_AUX_0_UNPLUG_EVENT_INIT_ENUM DISABLED +#define DPAUX_INTR_EN_AUX_0_UNPLUG_EVENT_DISABLED _MK_ENUM_CONST(0) +#define DPAUX_INTR_EN_AUX_0_UNPLUG_EVENT_ENABLED _MK_ENUM_CONST(1) + +#define DPAUX_INTR_EN_AUX_0_IRQ_EVENT_SHIFT _MK_SHIFT_CONST(2) +#define DPAUX_INTR_EN_AUX_0_IRQ_EVENT_FIELD _MK_FIELD_CONST(0x1, DPAUX_INTR_EN_AUX_0_IRQ_EVENT_SHIFT) +#define DPAUX_INTR_EN_AUX_0_IRQ_EVENT_RANGE 2:2 +#define DPAUX_INTR_EN_AUX_0_IRQ_EVENT_WOFFSET 0x0 +#define DPAUX_INTR_EN_AUX_0_IRQ_EVENT_DEFAULT _MK_MASK_CONST(0x0) +#define DPAUX_INTR_EN_AUX_0_IRQ_EVENT_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DPAUX_INTR_EN_AUX_0_IRQ_EVENT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DPAUX_INTR_EN_AUX_0_IRQ_EVENT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DPAUX_INTR_EN_AUX_0_IRQ_EVENT_INIT_ENUM DISABLED +#define DPAUX_INTR_EN_AUX_0_IRQ_EVENT_DISABLED _MK_ENUM_CONST(0) +#define DPAUX_INTR_EN_AUX_0_IRQ_EVENT_ENABLED _MK_ENUM_CONST(1) + +#define DPAUX_INTR_EN_AUX_0_AUX_DONE_SHIFT _MK_SHIFT_CONST(3) +#define DPAUX_INTR_EN_AUX_0_AUX_DONE_FIELD _MK_FIELD_CONST(0x1, DPAUX_INTR_EN_AUX_0_AUX_DONE_SHIFT) +#define DPAUX_INTR_EN_AUX_0_AUX_DONE_RANGE 3:3 +#define DPAUX_INTR_EN_AUX_0_AUX_DONE_WOFFSET 0x0 +#define DPAUX_INTR_EN_AUX_0_AUX_DONE_DEFAULT _MK_MASK_CONST(0x0) +#define DPAUX_INTR_EN_AUX_0_AUX_DONE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DPAUX_INTR_EN_AUX_0_AUX_DONE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DPAUX_INTR_EN_AUX_0_AUX_DONE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DPAUX_INTR_EN_AUX_0_AUX_DONE_INIT_ENUM DISABLED +#define DPAUX_INTR_EN_AUX_0_AUX_DONE_DISABLED _MK_ENUM_CONST(0) +#define DPAUX_INTR_EN_AUX_0_AUX_DONE_ENABLED _MK_ENUM_CONST(1) + + +// Register DPAUX_INTR_EN_AUX +#define DPAUX_INTR_EN_AUX _MK_ADDR_CONST(0x1) +#define DPAUX_INTR_EN_AUX_SECURE 0x0 +#define DPAUX_INTR_EN_AUX_WORD_COUNT 0x1 +#define DPAUX_INTR_EN_AUX_RESET_VAL _MK_MASK_CONST(0x0) +#define DPAUX_INTR_EN_AUX_RESET_MASK _MK_MASK_CONST(0xf) +#define DPAUX_INTR_EN_AUX_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DPAUX_INTR_EN_AUX_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DPAUX_INTR_EN_AUX_READ_MASK _MK_MASK_CONST(0xf) +#define DPAUX_INTR_EN_AUX_WRITE_MASK _MK_MASK_CONST(0xf) +#define DPAUX_INTR_EN_AUX_PLUG_EVENT_SHIFT _MK_SHIFT_CONST(0) +#define DPAUX_INTR_EN_AUX_PLUG_EVENT_FIELD _MK_FIELD_CONST(0x1, DPAUX_INTR_EN_AUX_PLUG_EVENT_SHIFT) +#define DPAUX_INTR_EN_AUX_PLUG_EVENT_RANGE 0:0 +#define DPAUX_INTR_EN_AUX_PLUG_EVENT_WOFFSET 0x0 +#define DPAUX_INTR_EN_AUX_PLUG_EVENT_DEFAULT _MK_MASK_CONST(0x0) +#define DPAUX_INTR_EN_AUX_PLUG_EVENT_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DPAUX_INTR_EN_AUX_PLUG_EVENT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DPAUX_INTR_EN_AUX_PLUG_EVENT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DPAUX_INTR_EN_AUX_PLUG_EVENT_INIT_ENUM DISABLED +#define DPAUX_INTR_EN_AUX_PLUG_EVENT_DISABLED _MK_ENUM_CONST(0) +#define DPAUX_INTR_EN_AUX_PLUG_EVENT_ENABLED _MK_ENUM_CONST(1) + +#define DPAUX_INTR_EN_AUX_UNPLUG_EVENT_SHIFT _MK_SHIFT_CONST(1) +#define DPAUX_INTR_EN_AUX_UNPLUG_EVENT_FIELD _MK_FIELD_CONST(0x1, DPAUX_INTR_EN_AUX_UNPLUG_EVENT_SHIFT) +#define DPAUX_INTR_EN_AUX_UNPLUG_EVENT_RANGE 1:1 +#define DPAUX_INTR_EN_AUX_UNPLUG_EVENT_WOFFSET 0x0 +#define DPAUX_INTR_EN_AUX_UNPLUG_EVENT_DEFAULT _MK_MASK_CONST(0x0) +#define DPAUX_INTR_EN_AUX_UNPLUG_EVENT_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DPAUX_INTR_EN_AUX_UNPLUG_EVENT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DPAUX_INTR_EN_AUX_UNPLUG_EVENT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DPAUX_INTR_EN_AUX_UNPLUG_EVENT_INIT_ENUM DISABLED +#define DPAUX_INTR_EN_AUX_UNPLUG_EVENT_DISABLED _MK_ENUM_CONST(0) +#define DPAUX_INTR_EN_AUX_UNPLUG_EVENT_ENABLED _MK_ENUM_CONST(1) + +#define DPAUX_INTR_EN_AUX_IRQ_EVENT_SHIFT _MK_SHIFT_CONST(2) +#define DPAUX_INTR_EN_AUX_IRQ_EVENT_FIELD _MK_FIELD_CONST(0x1, DPAUX_INTR_EN_AUX_IRQ_EVENT_SHIFT) +#define DPAUX_INTR_EN_AUX_IRQ_EVENT_RANGE 2:2 +#define DPAUX_INTR_EN_AUX_IRQ_EVENT_WOFFSET 0x0 +#define DPAUX_INTR_EN_AUX_IRQ_EVENT_DEFAULT _MK_MASK_CONST(0x0) +#define DPAUX_INTR_EN_AUX_IRQ_EVENT_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DPAUX_INTR_EN_AUX_IRQ_EVENT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DPAUX_INTR_EN_AUX_IRQ_EVENT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DPAUX_INTR_EN_AUX_IRQ_EVENT_INIT_ENUM DISABLED +#define DPAUX_INTR_EN_AUX_IRQ_EVENT_DISABLED _MK_ENUM_CONST(0) +#define DPAUX_INTR_EN_AUX_IRQ_EVENT_ENABLED _MK_ENUM_CONST(1) + +#define DPAUX_INTR_EN_AUX_AUX_DONE_SHIFT _MK_SHIFT_CONST(3) +#define DPAUX_INTR_EN_AUX_AUX_DONE_FIELD _MK_FIELD_CONST(0x1, DPAUX_INTR_EN_AUX_AUX_DONE_SHIFT) +#define DPAUX_INTR_EN_AUX_AUX_DONE_RANGE 3:3 +#define DPAUX_INTR_EN_AUX_AUX_DONE_WOFFSET 0x0 +#define DPAUX_INTR_EN_AUX_AUX_DONE_DEFAULT _MK_MASK_CONST(0x0) +#define DPAUX_INTR_EN_AUX_AUX_DONE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DPAUX_INTR_EN_AUX_AUX_DONE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DPAUX_INTR_EN_AUX_AUX_DONE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DPAUX_INTR_EN_AUX_AUX_DONE_INIT_ENUM DISABLED +#define DPAUX_INTR_EN_AUX_AUX_DONE_DISABLED _MK_ENUM_CONST(0) +#define DPAUX_INTR_EN_AUX_AUX_DONE_ENABLED _MK_ENUM_CONST(1) + + +// Register DPAUX_INTR_AUX_0 +#define DPAUX_INTR_AUX_0 _MK_ADDR_CONST(0x5) +#define DPAUX_INTR_AUX_0_SECURE 0x0 +#define DPAUX_INTR_AUX_0_WORD_COUNT 0x1 +#define DPAUX_INTR_AUX_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DPAUX_INTR_AUX_0_RESET_MASK _MK_MASK_CONST(0xf) +#define DPAUX_INTR_AUX_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DPAUX_INTR_AUX_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DPAUX_INTR_AUX_0_READ_MASK _MK_MASK_CONST(0xf) +#define DPAUX_INTR_AUX_0_WRITE_MASK _MK_MASK_CONST(0xf) +#define DPAUX_INTR_AUX_0_PLUG_EVENT_SHIFT _MK_SHIFT_CONST(0) +#define DPAUX_INTR_AUX_0_PLUG_EVENT_FIELD _MK_FIELD_CONST(0x1, DPAUX_INTR_AUX_0_PLUG_EVENT_SHIFT) +#define DPAUX_INTR_AUX_0_PLUG_EVENT_RANGE 0:0 +#define DPAUX_INTR_AUX_0_PLUG_EVENT_WOFFSET 0x0 +#define DPAUX_INTR_AUX_0_PLUG_EVENT_DEFAULT _MK_MASK_CONST(0x0) +#define DPAUX_INTR_AUX_0_PLUG_EVENT_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DPAUX_INTR_AUX_0_PLUG_EVENT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DPAUX_INTR_AUX_0_PLUG_EVENT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DPAUX_INTR_AUX_0_PLUG_EVENT_INIT_ENUM NOT_PENDING +#define DPAUX_INTR_AUX_0_PLUG_EVENT_NOT_PENDING _MK_ENUM_CONST(0) +#define DPAUX_INTR_AUX_0_PLUG_EVENT_PENDING _MK_ENUM_CONST(1) + +#define DPAUX_INTR_AUX_0_UNPLUG_EVENT_SHIFT _MK_SHIFT_CONST(1) +#define DPAUX_INTR_AUX_0_UNPLUG_EVENT_FIELD _MK_FIELD_CONST(0x1, DPAUX_INTR_AUX_0_UNPLUG_EVENT_SHIFT) +#define DPAUX_INTR_AUX_0_UNPLUG_EVENT_RANGE 1:1 +#define DPAUX_INTR_AUX_0_UNPLUG_EVENT_WOFFSET 0x0 +#define DPAUX_INTR_AUX_0_UNPLUG_EVENT_DEFAULT _MK_MASK_CONST(0x0) +#define DPAUX_INTR_AUX_0_UNPLUG_EVENT_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DPAUX_INTR_AUX_0_UNPLUG_EVENT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DPAUX_INTR_AUX_0_UNPLUG_EVENT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DPAUX_INTR_AUX_0_UNPLUG_EVENT_INIT_ENUM NOT_PENDING +#define DPAUX_INTR_AUX_0_UNPLUG_EVENT_NOT_PENDING _MK_ENUM_CONST(0) +#define DPAUX_INTR_AUX_0_UNPLUG_EVENT_PENDING _MK_ENUM_CONST(1) + +#define DPAUX_INTR_AUX_0_IRQ_EVENT_SHIFT _MK_SHIFT_CONST(2) +#define DPAUX_INTR_AUX_0_IRQ_EVENT_FIELD _MK_FIELD_CONST(0x1, DPAUX_INTR_AUX_0_IRQ_EVENT_SHIFT) +#define DPAUX_INTR_AUX_0_IRQ_EVENT_RANGE 2:2 +#define DPAUX_INTR_AUX_0_IRQ_EVENT_WOFFSET 0x0 +#define DPAUX_INTR_AUX_0_IRQ_EVENT_DEFAULT _MK_MASK_CONST(0x0) +#define DPAUX_INTR_AUX_0_IRQ_EVENT_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DPAUX_INTR_AUX_0_IRQ_EVENT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DPAUX_INTR_AUX_0_IRQ_EVENT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DPAUX_INTR_AUX_0_IRQ_EVENT_INIT_ENUM NOT_PENDING +#define DPAUX_INTR_AUX_0_IRQ_EVENT_NOT_PENDING _MK_ENUM_CONST(0) +#define DPAUX_INTR_AUX_0_IRQ_EVENT_PENDING _MK_ENUM_CONST(1) + +#define DPAUX_INTR_AUX_0_AUX_DONE_SHIFT _MK_SHIFT_CONST(3) +#define DPAUX_INTR_AUX_0_AUX_DONE_FIELD _MK_FIELD_CONST(0x1, DPAUX_INTR_AUX_0_AUX_DONE_SHIFT) +#define DPAUX_INTR_AUX_0_AUX_DONE_RANGE 3:3 +#define DPAUX_INTR_AUX_0_AUX_DONE_WOFFSET 0x0 +#define DPAUX_INTR_AUX_0_AUX_DONE_DEFAULT _MK_MASK_CONST(0x0) +#define DPAUX_INTR_AUX_0_AUX_DONE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DPAUX_INTR_AUX_0_AUX_DONE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DPAUX_INTR_AUX_0_AUX_DONE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DPAUX_INTR_AUX_0_AUX_DONE_INIT_ENUM NOT_PENDING +#define DPAUX_INTR_AUX_0_AUX_DONE_NOT_PENDING _MK_ENUM_CONST(0) +#define DPAUX_INTR_AUX_0_AUX_DONE_PENDING _MK_ENUM_CONST(1) + + +// Register DPAUX_INTR_AUX +#define DPAUX_INTR_AUX _MK_ADDR_CONST(0x5) +#define DPAUX_INTR_AUX_SECURE 0x0 +#define DPAUX_INTR_AUX_WORD_COUNT 0x1 +#define DPAUX_INTR_AUX_RESET_VAL _MK_MASK_CONST(0x0) +#define DPAUX_INTR_AUX_RESET_MASK _MK_MASK_CONST(0xf) +#define DPAUX_INTR_AUX_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DPAUX_INTR_AUX_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DPAUX_INTR_AUX_READ_MASK _MK_MASK_CONST(0xf) +#define DPAUX_INTR_AUX_WRITE_MASK _MK_MASK_CONST(0xf) +#define DPAUX_INTR_AUX_PLUG_EVENT_SHIFT _MK_SHIFT_CONST(0) +#define DPAUX_INTR_AUX_PLUG_EVENT_FIELD _MK_FIELD_CONST(0x1, DPAUX_INTR_AUX_PLUG_EVENT_SHIFT) +#define DPAUX_INTR_AUX_PLUG_EVENT_RANGE 0:0 +#define DPAUX_INTR_AUX_PLUG_EVENT_WOFFSET 0x0 +#define DPAUX_INTR_AUX_PLUG_EVENT_DEFAULT _MK_MASK_CONST(0x0) +#define DPAUX_INTR_AUX_PLUG_EVENT_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DPAUX_INTR_AUX_PLUG_EVENT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DPAUX_INTR_AUX_PLUG_EVENT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DPAUX_INTR_AUX_PLUG_EVENT_INIT_ENUM NOT_PENDING +#define DPAUX_INTR_AUX_PLUG_EVENT_NOT_PENDING _MK_ENUM_CONST(0) +#define DPAUX_INTR_AUX_PLUG_EVENT_PENDING _MK_ENUM_CONST(1) + +#define DPAUX_INTR_AUX_UNPLUG_EVENT_SHIFT _MK_SHIFT_CONST(1) +#define DPAUX_INTR_AUX_UNPLUG_EVENT_FIELD _MK_FIELD_CONST(0x1, DPAUX_INTR_AUX_UNPLUG_EVENT_SHIFT) +#define DPAUX_INTR_AUX_UNPLUG_EVENT_RANGE 1:1 +#define DPAUX_INTR_AUX_UNPLUG_EVENT_WOFFSET 0x0 +#define DPAUX_INTR_AUX_UNPLUG_EVENT_DEFAULT _MK_MASK_CONST(0x0) +#define DPAUX_INTR_AUX_UNPLUG_EVENT_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DPAUX_INTR_AUX_UNPLUG_EVENT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DPAUX_INTR_AUX_UNPLUG_EVENT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DPAUX_INTR_AUX_UNPLUG_EVENT_INIT_ENUM NOT_PENDING +#define DPAUX_INTR_AUX_UNPLUG_EVENT_NOT_PENDING _MK_ENUM_CONST(0) +#define DPAUX_INTR_AUX_UNPLUG_EVENT_PENDING _MK_ENUM_CONST(1) + +#define DPAUX_INTR_AUX_IRQ_EVENT_SHIFT _MK_SHIFT_CONST(2) +#define DPAUX_INTR_AUX_IRQ_EVENT_FIELD _MK_FIELD_CONST(0x1, DPAUX_INTR_AUX_IRQ_EVENT_SHIFT) +#define DPAUX_INTR_AUX_IRQ_EVENT_RANGE 2:2 +#define DPAUX_INTR_AUX_IRQ_EVENT_WOFFSET 0x0 +#define DPAUX_INTR_AUX_IRQ_EVENT_DEFAULT _MK_MASK_CONST(0x0) +#define DPAUX_INTR_AUX_IRQ_EVENT_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DPAUX_INTR_AUX_IRQ_EVENT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DPAUX_INTR_AUX_IRQ_EVENT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DPAUX_INTR_AUX_IRQ_EVENT_INIT_ENUM NOT_PENDING +#define DPAUX_INTR_AUX_IRQ_EVENT_NOT_PENDING _MK_ENUM_CONST(0) +#define DPAUX_INTR_AUX_IRQ_EVENT_PENDING _MK_ENUM_CONST(1) + +#define DPAUX_INTR_AUX_AUX_DONE_SHIFT _MK_SHIFT_CONST(3) +#define DPAUX_INTR_AUX_AUX_DONE_FIELD _MK_FIELD_CONST(0x1, DPAUX_INTR_AUX_AUX_DONE_SHIFT) +#define DPAUX_INTR_AUX_AUX_DONE_RANGE 3:3 +#define DPAUX_INTR_AUX_AUX_DONE_WOFFSET 0x0 +#define DPAUX_INTR_AUX_AUX_DONE_DEFAULT _MK_MASK_CONST(0x0) +#define DPAUX_INTR_AUX_AUX_DONE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DPAUX_INTR_AUX_AUX_DONE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DPAUX_INTR_AUX_AUX_DONE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DPAUX_INTR_AUX_AUX_DONE_INIT_ENUM NOT_PENDING +#define DPAUX_INTR_AUX_AUX_DONE_NOT_PENDING _MK_ENUM_CONST(0) +#define DPAUX_INTR_AUX_AUX_DONE_PENDING _MK_ENUM_CONST(1) + + +// Register DPAUX_DP_AUXDATA_WRITE_W0_0 +#define DPAUX_DP_AUXDATA_WRITE_W0_0 _MK_ADDR_CONST(0x9) +#define DPAUX_DP_AUXDATA_WRITE_W0_0_SECURE 0x0 +#define DPAUX_DP_AUXDATA_WRITE_W0_0_WORD_COUNT 0x1 +#define DPAUX_DP_AUXDATA_WRITE_W0_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUXDATA_WRITE_W0_0_RESET_MASK _MK_MASK_CONST(0xffffffff) +#define DPAUX_DP_AUXDATA_WRITE_W0_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUXDATA_WRITE_W0_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUXDATA_WRITE_W0_0_READ_MASK _MK_MASK_CONST(0xffffffff) +#define DPAUX_DP_AUXDATA_WRITE_W0_0_WRITE_MASK _MK_MASK_CONST(0xffffffff) +#define DPAUX_DP_AUXDATA_WRITE_W0_0_REG_SHIFT _MK_SHIFT_CONST(0) +#define DPAUX_DP_AUXDATA_WRITE_W0_0_REG_FIELD _MK_FIELD_CONST(0xffffffff, DPAUX_DP_AUXDATA_WRITE_W0_0_REG_SHIFT) +#define DPAUX_DP_AUXDATA_WRITE_W0_0_REG_RANGE 31:0 +#define DPAUX_DP_AUXDATA_WRITE_W0_0_REG_WOFFSET 0x0 +#define DPAUX_DP_AUXDATA_WRITE_W0_0_REG_DEFAULT _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUXDATA_WRITE_W0_0_REG_DEFAULT_MASK _MK_MASK_CONST(0xffffffff) +#define DPAUX_DP_AUXDATA_WRITE_W0_0_REG_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUXDATA_WRITE_W0_0_REG_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DPAUX_DP_AUXDATA_WRITE_W0 +#define DPAUX_DP_AUXDATA_WRITE_W0 _MK_ADDR_CONST(0x9) +#define DPAUX_DP_AUXDATA_WRITE_W0_SECURE 0x0 +#define DPAUX_DP_AUXDATA_WRITE_W0_WORD_COUNT 0x1 +#define DPAUX_DP_AUXDATA_WRITE_W0_RESET_VAL _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUXDATA_WRITE_W0_RESET_MASK _MK_MASK_CONST(0xffffffff) +#define DPAUX_DP_AUXDATA_WRITE_W0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUXDATA_WRITE_W0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUXDATA_WRITE_W0_READ_MASK _MK_MASK_CONST(0xffffffff) +#define DPAUX_DP_AUXDATA_WRITE_W0_WRITE_MASK _MK_MASK_CONST(0xffffffff) +#define DPAUX_DP_AUXDATA_WRITE_W0_REG_SHIFT _MK_SHIFT_CONST(0) +#define DPAUX_DP_AUXDATA_WRITE_W0_REG_FIELD _MK_FIELD_CONST(0xffffffff, DPAUX_DP_AUXDATA_WRITE_W0_REG_SHIFT) +#define DPAUX_DP_AUXDATA_WRITE_W0_REG_RANGE 31:0 +#define DPAUX_DP_AUXDATA_WRITE_W0_REG_WOFFSET 0x0 +#define DPAUX_DP_AUXDATA_WRITE_W0_REG_DEFAULT _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUXDATA_WRITE_W0_REG_DEFAULT_MASK _MK_MASK_CONST(0xffffffff) +#define DPAUX_DP_AUXDATA_WRITE_W0_REG_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUXDATA_WRITE_W0_REG_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DPAUX_DP_AUXDATA_WRITE_W1_0 +#define DPAUX_DP_AUXDATA_WRITE_W1_0 _MK_ADDR_CONST(0xd) +#define DPAUX_DP_AUXDATA_WRITE_W1_0_SECURE 0x0 +#define DPAUX_DP_AUXDATA_WRITE_W1_0_WORD_COUNT 0x1 +#define DPAUX_DP_AUXDATA_WRITE_W1_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUXDATA_WRITE_W1_0_RESET_MASK _MK_MASK_CONST(0xffffffff) +#define DPAUX_DP_AUXDATA_WRITE_W1_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUXDATA_WRITE_W1_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUXDATA_WRITE_W1_0_READ_MASK _MK_MASK_CONST(0xffffffff) +#define DPAUX_DP_AUXDATA_WRITE_W1_0_WRITE_MASK _MK_MASK_CONST(0xffffffff) +#define DPAUX_DP_AUXDATA_WRITE_W1_0_REG_SHIFT _MK_SHIFT_CONST(0) +#define DPAUX_DP_AUXDATA_WRITE_W1_0_REG_FIELD _MK_FIELD_CONST(0xffffffff, DPAUX_DP_AUXDATA_WRITE_W1_0_REG_SHIFT) +#define DPAUX_DP_AUXDATA_WRITE_W1_0_REG_RANGE 31:0 +#define DPAUX_DP_AUXDATA_WRITE_W1_0_REG_WOFFSET 0x0 +#define DPAUX_DP_AUXDATA_WRITE_W1_0_REG_DEFAULT _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUXDATA_WRITE_W1_0_REG_DEFAULT_MASK _MK_MASK_CONST(0xffffffff) +#define DPAUX_DP_AUXDATA_WRITE_W1_0_REG_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUXDATA_WRITE_W1_0_REG_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DPAUX_DP_AUXDATA_WRITE_W1 +#define DPAUX_DP_AUXDATA_WRITE_W1 _MK_ADDR_CONST(0xd) +#define DPAUX_DP_AUXDATA_WRITE_W1_SECURE 0x0 +#define DPAUX_DP_AUXDATA_WRITE_W1_WORD_COUNT 0x1 +#define DPAUX_DP_AUXDATA_WRITE_W1_RESET_VAL _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUXDATA_WRITE_W1_RESET_MASK _MK_MASK_CONST(0xffffffff) +#define DPAUX_DP_AUXDATA_WRITE_W1_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUXDATA_WRITE_W1_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUXDATA_WRITE_W1_READ_MASK _MK_MASK_CONST(0xffffffff) +#define DPAUX_DP_AUXDATA_WRITE_W1_WRITE_MASK _MK_MASK_CONST(0xffffffff) +#define DPAUX_DP_AUXDATA_WRITE_W1_REG_SHIFT _MK_SHIFT_CONST(0) +#define DPAUX_DP_AUXDATA_WRITE_W1_REG_FIELD _MK_FIELD_CONST(0xffffffff, DPAUX_DP_AUXDATA_WRITE_W1_REG_SHIFT) +#define DPAUX_DP_AUXDATA_WRITE_W1_REG_RANGE 31:0 +#define DPAUX_DP_AUXDATA_WRITE_W1_REG_WOFFSET 0x0 +#define DPAUX_DP_AUXDATA_WRITE_W1_REG_DEFAULT _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUXDATA_WRITE_W1_REG_DEFAULT_MASK _MK_MASK_CONST(0xffffffff) +#define DPAUX_DP_AUXDATA_WRITE_W1_REG_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUXDATA_WRITE_W1_REG_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DPAUX_DP_AUXDATA_WRITE_W2_0 +#define DPAUX_DP_AUXDATA_WRITE_W2_0 _MK_ADDR_CONST(0x11) +#define DPAUX_DP_AUXDATA_WRITE_W2_0_SECURE 0x0 +#define DPAUX_DP_AUXDATA_WRITE_W2_0_WORD_COUNT 0x1 +#define DPAUX_DP_AUXDATA_WRITE_W2_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUXDATA_WRITE_W2_0_RESET_MASK _MK_MASK_CONST(0xffffffff) +#define DPAUX_DP_AUXDATA_WRITE_W2_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUXDATA_WRITE_W2_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUXDATA_WRITE_W2_0_READ_MASK _MK_MASK_CONST(0xffffffff) +#define DPAUX_DP_AUXDATA_WRITE_W2_0_WRITE_MASK _MK_MASK_CONST(0xffffffff) +#define DPAUX_DP_AUXDATA_WRITE_W2_0_REG_SHIFT _MK_SHIFT_CONST(0) +#define DPAUX_DP_AUXDATA_WRITE_W2_0_REG_FIELD _MK_FIELD_CONST(0xffffffff, DPAUX_DP_AUXDATA_WRITE_W2_0_REG_SHIFT) +#define DPAUX_DP_AUXDATA_WRITE_W2_0_REG_RANGE 31:0 +#define DPAUX_DP_AUXDATA_WRITE_W2_0_REG_WOFFSET 0x0 +#define DPAUX_DP_AUXDATA_WRITE_W2_0_REG_DEFAULT _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUXDATA_WRITE_W2_0_REG_DEFAULT_MASK _MK_MASK_CONST(0xffffffff) +#define DPAUX_DP_AUXDATA_WRITE_W2_0_REG_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUXDATA_WRITE_W2_0_REG_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DPAUX_DP_AUXDATA_WRITE_W2 +#define DPAUX_DP_AUXDATA_WRITE_W2 _MK_ADDR_CONST(0x11) +#define DPAUX_DP_AUXDATA_WRITE_W2_SECURE 0x0 +#define DPAUX_DP_AUXDATA_WRITE_W2_WORD_COUNT 0x1 +#define DPAUX_DP_AUXDATA_WRITE_W2_RESET_VAL _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUXDATA_WRITE_W2_RESET_MASK _MK_MASK_CONST(0xffffffff) +#define DPAUX_DP_AUXDATA_WRITE_W2_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUXDATA_WRITE_W2_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUXDATA_WRITE_W2_READ_MASK _MK_MASK_CONST(0xffffffff) +#define DPAUX_DP_AUXDATA_WRITE_W2_WRITE_MASK _MK_MASK_CONST(0xffffffff) +#define DPAUX_DP_AUXDATA_WRITE_W2_REG_SHIFT _MK_SHIFT_CONST(0) +#define DPAUX_DP_AUXDATA_WRITE_W2_REG_FIELD _MK_FIELD_CONST(0xffffffff, DPAUX_DP_AUXDATA_WRITE_W2_REG_SHIFT) +#define DPAUX_DP_AUXDATA_WRITE_W2_REG_RANGE 31:0 +#define DPAUX_DP_AUXDATA_WRITE_W2_REG_WOFFSET 0x0 +#define DPAUX_DP_AUXDATA_WRITE_W2_REG_DEFAULT _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUXDATA_WRITE_W2_REG_DEFAULT_MASK _MK_MASK_CONST(0xffffffff) +#define DPAUX_DP_AUXDATA_WRITE_W2_REG_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUXDATA_WRITE_W2_REG_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DPAUX_DP_AUXDATA_WRITE_W3_0 +#define DPAUX_DP_AUXDATA_WRITE_W3_0 _MK_ADDR_CONST(0x15) +#define DPAUX_DP_AUXDATA_WRITE_W3_0_SECURE 0x0 +#define DPAUX_DP_AUXDATA_WRITE_W3_0_WORD_COUNT 0x1 +#define DPAUX_DP_AUXDATA_WRITE_W3_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUXDATA_WRITE_W3_0_RESET_MASK _MK_MASK_CONST(0xffffffff) +#define DPAUX_DP_AUXDATA_WRITE_W3_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUXDATA_WRITE_W3_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUXDATA_WRITE_W3_0_READ_MASK _MK_MASK_CONST(0xffffffff) +#define DPAUX_DP_AUXDATA_WRITE_W3_0_WRITE_MASK _MK_MASK_CONST(0xffffffff) +#define DPAUX_DP_AUXDATA_WRITE_W3_0_REG_SHIFT _MK_SHIFT_CONST(0) +#define DPAUX_DP_AUXDATA_WRITE_W3_0_REG_FIELD _MK_FIELD_CONST(0xffffffff, DPAUX_DP_AUXDATA_WRITE_W3_0_REG_SHIFT) +#define DPAUX_DP_AUXDATA_WRITE_W3_0_REG_RANGE 31:0 +#define DPAUX_DP_AUXDATA_WRITE_W3_0_REG_WOFFSET 0x0 +#define DPAUX_DP_AUXDATA_WRITE_W3_0_REG_DEFAULT _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUXDATA_WRITE_W3_0_REG_DEFAULT_MASK _MK_MASK_CONST(0xffffffff) +#define DPAUX_DP_AUXDATA_WRITE_W3_0_REG_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUXDATA_WRITE_W3_0_REG_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DPAUX_DP_AUXDATA_WRITE_W3 +#define DPAUX_DP_AUXDATA_WRITE_W3 _MK_ADDR_CONST(0x15) +#define DPAUX_DP_AUXDATA_WRITE_W3_SECURE 0x0 +#define DPAUX_DP_AUXDATA_WRITE_W3_WORD_COUNT 0x1 +#define DPAUX_DP_AUXDATA_WRITE_W3_RESET_VAL _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUXDATA_WRITE_W3_RESET_MASK _MK_MASK_CONST(0xffffffff) +#define DPAUX_DP_AUXDATA_WRITE_W3_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUXDATA_WRITE_W3_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUXDATA_WRITE_W3_READ_MASK _MK_MASK_CONST(0xffffffff) +#define DPAUX_DP_AUXDATA_WRITE_W3_WRITE_MASK _MK_MASK_CONST(0xffffffff) +#define DPAUX_DP_AUXDATA_WRITE_W3_REG_SHIFT _MK_SHIFT_CONST(0) +#define DPAUX_DP_AUXDATA_WRITE_W3_REG_FIELD _MK_FIELD_CONST(0xffffffff, DPAUX_DP_AUXDATA_WRITE_W3_REG_SHIFT) +#define DPAUX_DP_AUXDATA_WRITE_W3_REG_RANGE 31:0 +#define DPAUX_DP_AUXDATA_WRITE_W3_REG_WOFFSET 0x0 +#define DPAUX_DP_AUXDATA_WRITE_W3_REG_DEFAULT _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUXDATA_WRITE_W3_REG_DEFAULT_MASK _MK_MASK_CONST(0xffffffff) +#define DPAUX_DP_AUXDATA_WRITE_W3_REG_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUXDATA_WRITE_W3_REG_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DPAUX_DP_AUXDATA_READ_W0_0 +#define DPAUX_DP_AUXDATA_READ_W0_0 _MK_ADDR_CONST(0x19) +#define DPAUX_DP_AUXDATA_READ_W0_0_SECURE 0x0 +#define DPAUX_DP_AUXDATA_READ_W0_0_WORD_COUNT 0x1 +#define DPAUX_DP_AUXDATA_READ_W0_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUXDATA_READ_W0_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUXDATA_READ_W0_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUXDATA_READ_W0_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUXDATA_READ_W0_0_READ_MASK _MK_MASK_CONST(0xffffffff) +#define DPAUX_DP_AUXDATA_READ_W0_0_WRITE_MASK _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUXDATA_READ_W0_0_REG_SHIFT _MK_SHIFT_CONST(0) +#define DPAUX_DP_AUXDATA_READ_W0_0_REG_FIELD _MK_FIELD_CONST(0xffffffff, DPAUX_DP_AUXDATA_READ_W0_0_REG_SHIFT) +#define DPAUX_DP_AUXDATA_READ_W0_0_REG_RANGE 31:0 +#define DPAUX_DP_AUXDATA_READ_W0_0_REG_WOFFSET 0x0 +#define DPAUX_DP_AUXDATA_READ_W0_0_REG_DEFAULT _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUXDATA_READ_W0_0_REG_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUXDATA_READ_W0_0_REG_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUXDATA_READ_W0_0_REG_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DPAUX_DP_AUXDATA_READ_W0 +#define DPAUX_DP_AUXDATA_READ_W0 _MK_ADDR_CONST(0x19) +#define DPAUX_DP_AUXDATA_READ_W0_SECURE 0x0 +#define DPAUX_DP_AUXDATA_READ_W0_WORD_COUNT 0x1 +#define DPAUX_DP_AUXDATA_READ_W0_RESET_VAL _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUXDATA_READ_W0_RESET_MASK _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUXDATA_READ_W0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUXDATA_READ_W0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUXDATA_READ_W0_READ_MASK _MK_MASK_CONST(0xffffffff) +#define DPAUX_DP_AUXDATA_READ_W0_WRITE_MASK _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUXDATA_READ_W0_REG_SHIFT _MK_SHIFT_CONST(0) +#define DPAUX_DP_AUXDATA_READ_W0_REG_FIELD _MK_FIELD_CONST(0xffffffff, DPAUX_DP_AUXDATA_READ_W0_REG_SHIFT) +#define DPAUX_DP_AUXDATA_READ_W0_REG_RANGE 31:0 +#define DPAUX_DP_AUXDATA_READ_W0_REG_WOFFSET 0x0 +#define DPAUX_DP_AUXDATA_READ_W0_REG_DEFAULT _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUXDATA_READ_W0_REG_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUXDATA_READ_W0_REG_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUXDATA_READ_W0_REG_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DPAUX_DP_AUXDATA_READ_W1_0 +#define DPAUX_DP_AUXDATA_READ_W1_0 _MK_ADDR_CONST(0x1d) +#define DPAUX_DP_AUXDATA_READ_W1_0_SECURE 0x0 +#define DPAUX_DP_AUXDATA_READ_W1_0_WORD_COUNT 0x1 +#define DPAUX_DP_AUXDATA_READ_W1_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUXDATA_READ_W1_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUXDATA_READ_W1_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUXDATA_READ_W1_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUXDATA_READ_W1_0_READ_MASK _MK_MASK_CONST(0xffffffff) +#define DPAUX_DP_AUXDATA_READ_W1_0_WRITE_MASK _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUXDATA_READ_W1_0_REG_SHIFT _MK_SHIFT_CONST(0) +#define DPAUX_DP_AUXDATA_READ_W1_0_REG_FIELD _MK_FIELD_CONST(0xffffffff, DPAUX_DP_AUXDATA_READ_W1_0_REG_SHIFT) +#define DPAUX_DP_AUXDATA_READ_W1_0_REG_RANGE 31:0 +#define DPAUX_DP_AUXDATA_READ_W1_0_REG_WOFFSET 0x0 +#define DPAUX_DP_AUXDATA_READ_W1_0_REG_DEFAULT _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUXDATA_READ_W1_0_REG_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUXDATA_READ_W1_0_REG_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUXDATA_READ_W1_0_REG_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DPAUX_DP_AUXDATA_READ_W1 +#define DPAUX_DP_AUXDATA_READ_W1 _MK_ADDR_CONST(0x1d) +#define DPAUX_DP_AUXDATA_READ_W1_SECURE 0x0 +#define DPAUX_DP_AUXDATA_READ_W1_WORD_COUNT 0x1 +#define DPAUX_DP_AUXDATA_READ_W1_RESET_VAL _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUXDATA_READ_W1_RESET_MASK _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUXDATA_READ_W1_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUXDATA_READ_W1_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUXDATA_READ_W1_READ_MASK _MK_MASK_CONST(0xffffffff) +#define DPAUX_DP_AUXDATA_READ_W1_WRITE_MASK _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUXDATA_READ_W1_REG_SHIFT _MK_SHIFT_CONST(0) +#define DPAUX_DP_AUXDATA_READ_W1_REG_FIELD _MK_FIELD_CONST(0xffffffff, DPAUX_DP_AUXDATA_READ_W1_REG_SHIFT) +#define DPAUX_DP_AUXDATA_READ_W1_REG_RANGE 31:0 +#define DPAUX_DP_AUXDATA_READ_W1_REG_WOFFSET 0x0 +#define DPAUX_DP_AUXDATA_READ_W1_REG_DEFAULT _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUXDATA_READ_W1_REG_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUXDATA_READ_W1_REG_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUXDATA_READ_W1_REG_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DPAUX_DP_AUXDATA_READ_W2_0 +#define DPAUX_DP_AUXDATA_READ_W2_0 _MK_ADDR_CONST(0x21) +#define DPAUX_DP_AUXDATA_READ_W2_0_SECURE 0x0 +#define DPAUX_DP_AUXDATA_READ_W2_0_WORD_COUNT 0x1 +#define DPAUX_DP_AUXDATA_READ_W2_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUXDATA_READ_W2_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUXDATA_READ_W2_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUXDATA_READ_W2_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUXDATA_READ_W2_0_READ_MASK _MK_MASK_CONST(0xffffffff) +#define DPAUX_DP_AUXDATA_READ_W2_0_WRITE_MASK _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUXDATA_READ_W2_0_REG_SHIFT _MK_SHIFT_CONST(0) +#define DPAUX_DP_AUXDATA_READ_W2_0_REG_FIELD _MK_FIELD_CONST(0xffffffff, DPAUX_DP_AUXDATA_READ_W2_0_REG_SHIFT) +#define DPAUX_DP_AUXDATA_READ_W2_0_REG_RANGE 31:0 +#define DPAUX_DP_AUXDATA_READ_W2_0_REG_WOFFSET 0x0 +#define DPAUX_DP_AUXDATA_READ_W2_0_REG_DEFAULT _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUXDATA_READ_W2_0_REG_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUXDATA_READ_W2_0_REG_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUXDATA_READ_W2_0_REG_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DPAUX_DP_AUXDATA_READ_W2 +#define DPAUX_DP_AUXDATA_READ_W2 _MK_ADDR_CONST(0x21) +#define DPAUX_DP_AUXDATA_READ_W2_SECURE 0x0 +#define DPAUX_DP_AUXDATA_READ_W2_WORD_COUNT 0x1 +#define DPAUX_DP_AUXDATA_READ_W2_RESET_VAL _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUXDATA_READ_W2_RESET_MASK _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUXDATA_READ_W2_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUXDATA_READ_W2_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUXDATA_READ_W2_READ_MASK _MK_MASK_CONST(0xffffffff) +#define DPAUX_DP_AUXDATA_READ_W2_WRITE_MASK _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUXDATA_READ_W2_REG_SHIFT _MK_SHIFT_CONST(0) +#define DPAUX_DP_AUXDATA_READ_W2_REG_FIELD _MK_FIELD_CONST(0xffffffff, DPAUX_DP_AUXDATA_READ_W2_REG_SHIFT) +#define DPAUX_DP_AUXDATA_READ_W2_REG_RANGE 31:0 +#define DPAUX_DP_AUXDATA_READ_W2_REG_WOFFSET 0x0 +#define DPAUX_DP_AUXDATA_READ_W2_REG_DEFAULT _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUXDATA_READ_W2_REG_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUXDATA_READ_W2_REG_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUXDATA_READ_W2_REG_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DPAUX_DP_AUXDATA_READ_W3_0 +#define DPAUX_DP_AUXDATA_READ_W3_0 _MK_ADDR_CONST(0x25) +#define DPAUX_DP_AUXDATA_READ_W3_0_SECURE 0x0 +#define DPAUX_DP_AUXDATA_READ_W3_0_WORD_COUNT 0x1 +#define DPAUX_DP_AUXDATA_READ_W3_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUXDATA_READ_W3_0_RESET_MASK _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUXDATA_READ_W3_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUXDATA_READ_W3_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUXDATA_READ_W3_0_READ_MASK _MK_MASK_CONST(0xffffffff) +#define DPAUX_DP_AUXDATA_READ_W3_0_WRITE_MASK _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUXDATA_READ_W3_0_REG_SHIFT _MK_SHIFT_CONST(0) +#define DPAUX_DP_AUXDATA_READ_W3_0_REG_FIELD _MK_FIELD_CONST(0xffffffff, DPAUX_DP_AUXDATA_READ_W3_0_REG_SHIFT) +#define DPAUX_DP_AUXDATA_READ_W3_0_REG_RANGE 31:0 +#define DPAUX_DP_AUXDATA_READ_W3_0_REG_WOFFSET 0x0 +#define DPAUX_DP_AUXDATA_READ_W3_0_REG_DEFAULT _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUXDATA_READ_W3_0_REG_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUXDATA_READ_W3_0_REG_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUXDATA_READ_W3_0_REG_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DPAUX_DP_AUXDATA_READ_W3 +#define DPAUX_DP_AUXDATA_READ_W3 _MK_ADDR_CONST(0x25) +#define DPAUX_DP_AUXDATA_READ_W3_SECURE 0x0 +#define DPAUX_DP_AUXDATA_READ_W3_WORD_COUNT 0x1 +#define DPAUX_DP_AUXDATA_READ_W3_RESET_VAL _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUXDATA_READ_W3_RESET_MASK _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUXDATA_READ_W3_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUXDATA_READ_W3_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUXDATA_READ_W3_READ_MASK _MK_MASK_CONST(0xffffffff) +#define DPAUX_DP_AUXDATA_READ_W3_WRITE_MASK _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUXDATA_READ_W3_REG_SHIFT _MK_SHIFT_CONST(0) +#define DPAUX_DP_AUXDATA_READ_W3_REG_FIELD _MK_FIELD_CONST(0xffffffff, DPAUX_DP_AUXDATA_READ_W3_REG_SHIFT) +#define DPAUX_DP_AUXDATA_READ_W3_REG_RANGE 31:0 +#define DPAUX_DP_AUXDATA_READ_W3_REG_WOFFSET 0x0 +#define DPAUX_DP_AUXDATA_READ_W3_REG_DEFAULT _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUXDATA_READ_W3_REG_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUXDATA_READ_W3_REG_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUXDATA_READ_W3_REG_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DPAUX_DP_AUXADDR_0 +#define DPAUX_DP_AUXADDR_0 _MK_ADDR_CONST(0x29) +#define DPAUX_DP_AUXADDR_0_SECURE 0x0 +#define DPAUX_DP_AUXADDR_0_WORD_COUNT 0x1 +#define DPAUX_DP_AUXADDR_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUXADDR_0_RESET_MASK _MK_MASK_CONST(0xfffff) +#define DPAUX_DP_AUXADDR_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUXADDR_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUXADDR_0_READ_MASK _MK_MASK_CONST(0xfffff) +#define DPAUX_DP_AUXADDR_0_WRITE_MASK _MK_MASK_CONST(0xfffff) +#define DPAUX_DP_AUXADDR_0_REG_SHIFT _MK_SHIFT_CONST(0) +#define DPAUX_DP_AUXADDR_0_REG_FIELD _MK_FIELD_CONST(0xfffff, DPAUX_DP_AUXADDR_0_REG_SHIFT) +#define DPAUX_DP_AUXADDR_0_REG_RANGE 19:0 +#define DPAUX_DP_AUXADDR_0_REG_WOFFSET 0x0 +#define DPAUX_DP_AUXADDR_0_REG_DEFAULT _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUXADDR_0_REG_DEFAULT_MASK _MK_MASK_CONST(0xfffff) +#define DPAUX_DP_AUXADDR_0_REG_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUXADDR_0_REG_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DPAUX_DP_AUXADDR +#define DPAUX_DP_AUXADDR _MK_ADDR_CONST(0x29) +#define DPAUX_DP_AUXADDR_SECURE 0x0 +#define DPAUX_DP_AUXADDR_WORD_COUNT 0x1 +#define DPAUX_DP_AUXADDR_RESET_VAL _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUXADDR_RESET_MASK _MK_MASK_CONST(0xfffff) +#define DPAUX_DP_AUXADDR_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUXADDR_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUXADDR_READ_MASK _MK_MASK_CONST(0xfffff) +#define DPAUX_DP_AUXADDR_WRITE_MASK _MK_MASK_CONST(0xfffff) +#define DPAUX_DP_AUXADDR_REG_SHIFT _MK_SHIFT_CONST(0) +#define DPAUX_DP_AUXADDR_REG_FIELD _MK_FIELD_CONST(0xfffff, DPAUX_DP_AUXADDR_REG_SHIFT) +#define DPAUX_DP_AUXADDR_REG_RANGE 19:0 +#define DPAUX_DP_AUXADDR_REG_WOFFSET 0x0 +#define DPAUX_DP_AUXADDR_REG_DEFAULT _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUXADDR_REG_DEFAULT_MASK _MK_MASK_CONST(0xfffff) +#define DPAUX_DP_AUXADDR_REG_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUXADDR_REG_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DPAUX_DP_AUXCTL_0 +#define DPAUX_DP_AUXCTL_0 _MK_ADDR_CONST(0x2d) +#define DPAUX_DP_AUXCTL_0_SECURE 0x0 +#define DPAUX_DP_AUXCTL_0_WORD_COUNT 0x1 +#define DPAUX_DP_AUXCTL_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUXCTL_0_RESET_MASK _MK_MASK_CONST(0x8331f1ff) +#define DPAUX_DP_AUXCTL_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUXCTL_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUXCTL_0_READ_MASK _MK_MASK_CONST(0x8331f1ff) +#define DPAUX_DP_AUXCTL_0_WRITE_MASK _MK_MASK_CONST(0x8031f1ff) +#define DPAUX_DP_AUXCTL_0_RST_SHIFT _MK_SHIFT_CONST(31) +#define DPAUX_DP_AUXCTL_0_RST_FIELD _MK_FIELD_CONST(0x1, DPAUX_DP_AUXCTL_0_RST_SHIFT) +#define DPAUX_DP_AUXCTL_0_RST_RANGE 31:31 +#define DPAUX_DP_AUXCTL_0_RST_WOFFSET 0x0 +#define DPAUX_DP_AUXCTL_0_RST_DEFAULT _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUXCTL_0_RST_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DPAUX_DP_AUXCTL_0_RST_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUXCTL_0_RST_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUXCTL_0_RST_INIT_ENUM DEASSERT +#define DPAUX_DP_AUXCTL_0_RST_DEASSERT _MK_ENUM_CONST(0) +#define DPAUX_DP_AUXCTL_0_RST_ASSERT _MK_ENUM_CONST(1) + +#define DPAUX_DP_AUXCTL_0_SEMA_GRANT_SHIFT _MK_SHIFT_CONST(24) +#define DPAUX_DP_AUXCTL_0_SEMA_GRANT_FIELD _MK_FIELD_CONST(0x3, DPAUX_DP_AUXCTL_0_SEMA_GRANT_SHIFT) +#define DPAUX_DP_AUXCTL_0_SEMA_GRANT_RANGE 25:24 +#define DPAUX_DP_AUXCTL_0_SEMA_GRANT_WOFFSET 0x0 +#define DPAUX_DP_AUXCTL_0_SEMA_GRANT_DEFAULT _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUXCTL_0_SEMA_GRANT_DEFAULT_MASK _MK_MASK_CONST(0x3) +#define DPAUX_DP_AUXCTL_0_SEMA_GRANT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUXCTL_0_SEMA_GRANT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUXCTL_0_SEMA_GRANT_INIT_ENUM NONE +#define DPAUX_DP_AUXCTL_0_SEMA_GRANT_NONE _MK_ENUM_CONST(0) +#define DPAUX_DP_AUXCTL_0_SEMA_GRANT_RM _MK_ENUM_CONST(1) +#define DPAUX_DP_AUXCTL_0_SEMA_GRANT_VBIOS _MK_ENUM_CONST(2) +#define DPAUX_DP_AUXCTL_0_SEMA_GRANT_PMU _MK_ENUM_CONST(3) + +#define DPAUX_DP_AUXCTL_0_SEMA_REQUEST_SHIFT _MK_SHIFT_CONST(20) +#define DPAUX_DP_AUXCTL_0_SEMA_REQUEST_FIELD _MK_FIELD_CONST(0x3, DPAUX_DP_AUXCTL_0_SEMA_REQUEST_SHIFT) +#define DPAUX_DP_AUXCTL_0_SEMA_REQUEST_RANGE 21:20 +#define DPAUX_DP_AUXCTL_0_SEMA_REQUEST_WOFFSET 0x0 +#define DPAUX_DP_AUXCTL_0_SEMA_REQUEST_DEFAULT _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUXCTL_0_SEMA_REQUEST_DEFAULT_MASK _MK_MASK_CONST(0x3) +#define DPAUX_DP_AUXCTL_0_SEMA_REQUEST_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUXCTL_0_SEMA_REQUEST_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUXCTL_0_SEMA_REQUEST_INIT_ENUM RELEASE +#define DPAUX_DP_AUXCTL_0_SEMA_REQUEST_RELEASE _MK_ENUM_CONST(0) +#define DPAUX_DP_AUXCTL_0_SEMA_REQUEST_RM _MK_ENUM_CONST(1) +#define DPAUX_DP_AUXCTL_0_SEMA_REQUEST_VBIOS _MK_ENUM_CONST(2) +#define DPAUX_DP_AUXCTL_0_SEMA_REQUEST_PMU _MK_ENUM_CONST(3) + +#define DPAUX_DP_AUXCTL_0_TRANSACTREQ_SHIFT _MK_SHIFT_CONST(16) +#define DPAUX_DP_AUXCTL_0_TRANSACTREQ_FIELD _MK_FIELD_CONST(0x1, DPAUX_DP_AUXCTL_0_TRANSACTREQ_SHIFT) +#define DPAUX_DP_AUXCTL_0_TRANSACTREQ_RANGE 16:16 +#define DPAUX_DP_AUXCTL_0_TRANSACTREQ_WOFFSET 0x0 +#define DPAUX_DP_AUXCTL_0_TRANSACTREQ_DEFAULT _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUXCTL_0_TRANSACTREQ_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DPAUX_DP_AUXCTL_0_TRANSACTREQ_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUXCTL_0_TRANSACTREQ_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUXCTL_0_TRANSACTREQ_INIT_ENUM DONE +#define DPAUX_DP_AUXCTL_0_TRANSACTREQ_DONE _MK_ENUM_CONST(0) +#define DPAUX_DP_AUXCTL_0_TRANSACTREQ_PENDING _MK_ENUM_CONST(1) + +#define DPAUX_DP_AUXCTL_0_CMD_SHIFT _MK_SHIFT_CONST(12) +#define DPAUX_DP_AUXCTL_0_CMD_FIELD _MK_FIELD_CONST(0xf, DPAUX_DP_AUXCTL_0_CMD_SHIFT) +#define DPAUX_DP_AUXCTL_0_CMD_RANGE 15:12 +#define DPAUX_DP_AUXCTL_0_CMD_WOFFSET 0x0 +#define DPAUX_DP_AUXCTL_0_CMD_DEFAULT _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUXCTL_0_CMD_DEFAULT_MASK _MK_MASK_CONST(0xf) +#define DPAUX_DP_AUXCTL_0_CMD_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUXCTL_0_CMD_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUXCTL_0_CMD_INIT_ENUM I2CWR +#define DPAUX_DP_AUXCTL_0_CMD_I2CWR _MK_ENUM_CONST(0) +#define DPAUX_DP_AUXCTL_0_CMD_I2CRD _MK_ENUM_CONST(1) +#define DPAUX_DP_AUXCTL_0_CMD_I2CREQWSTAT _MK_ENUM_CONST(2) +#define DPAUX_DP_AUXCTL_0_CMD_MOTWR _MK_ENUM_CONST(4) +#define DPAUX_DP_AUXCTL_0_CMD_MOTRD _MK_ENUM_CONST(5) +#define DPAUX_DP_AUXCTL_0_CMD_MOTREQWSTAT _MK_ENUM_CONST(6) +#define DPAUX_DP_AUXCTL_0_CMD_AUXWR _MK_ENUM_CONST(8) +#define DPAUX_DP_AUXCTL_0_CMD_AUXRD _MK_ENUM_CONST(9) + +#define DPAUX_DP_AUXCTL_0_ADDRESS_ONLY_SHIFT _MK_SHIFT_CONST(8) +#define DPAUX_DP_AUXCTL_0_ADDRESS_ONLY_FIELD _MK_FIELD_CONST(0x1, DPAUX_DP_AUXCTL_0_ADDRESS_ONLY_SHIFT) +#define DPAUX_DP_AUXCTL_0_ADDRESS_ONLY_RANGE 8:8 +#define DPAUX_DP_AUXCTL_0_ADDRESS_ONLY_WOFFSET 0x0 +#define DPAUX_DP_AUXCTL_0_ADDRESS_ONLY_DEFAULT _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUXCTL_0_ADDRESS_ONLY_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DPAUX_DP_AUXCTL_0_ADDRESS_ONLY_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUXCTL_0_ADDRESS_ONLY_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUXCTL_0_ADDRESS_ONLY_INIT_ENUM NO +#define DPAUX_DP_AUXCTL_0_ADDRESS_ONLY_NO _MK_ENUM_CONST(0) +#define DPAUX_DP_AUXCTL_0_ADDRESS_ONLY_YES _MK_ENUM_CONST(1) + +#define DPAUX_DP_AUXCTL_0_CMDLEN_SHIFT _MK_SHIFT_CONST(0) +#define DPAUX_DP_AUXCTL_0_CMDLEN_FIELD _MK_FIELD_CONST(0xff, DPAUX_DP_AUXCTL_0_CMDLEN_SHIFT) +#define DPAUX_DP_AUXCTL_0_CMDLEN_RANGE 7:0 +#define DPAUX_DP_AUXCTL_0_CMDLEN_WOFFSET 0x0 +#define DPAUX_DP_AUXCTL_0_CMDLEN_DEFAULT _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUXCTL_0_CMDLEN_DEFAULT_MASK _MK_MASK_CONST(0xff) +#define DPAUX_DP_AUXCTL_0_CMDLEN_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUXCTL_0_CMDLEN_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DPAUX_DP_AUXCTL +#define DPAUX_DP_AUXCTL _MK_ADDR_CONST(0x2d) +#define DPAUX_DP_AUXCTL_SECURE 0x0 +#define DPAUX_DP_AUXCTL_WORD_COUNT 0x1 +#define DPAUX_DP_AUXCTL_RESET_VAL _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUXCTL_RESET_MASK _MK_MASK_CONST(0x8331f1ff) +#define DPAUX_DP_AUXCTL_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUXCTL_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUXCTL_READ_MASK _MK_MASK_CONST(0x8331f1ff) +#define DPAUX_DP_AUXCTL_WRITE_MASK _MK_MASK_CONST(0x8031f1ff) +#define DPAUX_DP_AUXCTL_RST_SHIFT _MK_SHIFT_CONST(31) +#define DPAUX_DP_AUXCTL_RST_FIELD _MK_FIELD_CONST(0x1, DPAUX_DP_AUXCTL_RST_SHIFT) +#define DPAUX_DP_AUXCTL_RST_RANGE 31:31 +#define DPAUX_DP_AUXCTL_RST_WOFFSET 0x0 +#define DPAUX_DP_AUXCTL_RST_DEFAULT _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUXCTL_RST_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DPAUX_DP_AUXCTL_RST_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUXCTL_RST_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUXCTL_RST_INIT_ENUM DEASSERT +#define DPAUX_DP_AUXCTL_RST_DEASSERT _MK_ENUM_CONST(0) +#define DPAUX_DP_AUXCTL_RST_ASSERT _MK_ENUM_CONST(1) + +#define DPAUX_DP_AUXCTL_SEMA_GRANT_SHIFT _MK_SHIFT_CONST(24) +#define DPAUX_DP_AUXCTL_SEMA_GRANT_FIELD _MK_FIELD_CONST(0x3, DPAUX_DP_AUXCTL_SEMA_GRANT_SHIFT) +#define DPAUX_DP_AUXCTL_SEMA_GRANT_RANGE 25:24 +#define DPAUX_DP_AUXCTL_SEMA_GRANT_WOFFSET 0x0 +#define DPAUX_DP_AUXCTL_SEMA_GRANT_DEFAULT _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUXCTL_SEMA_GRANT_DEFAULT_MASK _MK_MASK_CONST(0x3) +#define DPAUX_DP_AUXCTL_SEMA_GRANT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUXCTL_SEMA_GRANT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUXCTL_SEMA_GRANT_INIT_ENUM NONE +#define DPAUX_DP_AUXCTL_SEMA_GRANT_NONE _MK_ENUM_CONST(0) +#define DPAUX_DP_AUXCTL_SEMA_GRANT_RM _MK_ENUM_CONST(1) +#define DPAUX_DP_AUXCTL_SEMA_GRANT_VBIOS _MK_ENUM_CONST(2) +#define DPAUX_DP_AUXCTL_SEMA_GRANT_PMU _MK_ENUM_CONST(3) + +#define DPAUX_DP_AUXCTL_SEMA_REQUEST_SHIFT _MK_SHIFT_CONST(20) +#define DPAUX_DP_AUXCTL_SEMA_REQUEST_FIELD _MK_FIELD_CONST(0x3, DPAUX_DP_AUXCTL_SEMA_REQUEST_SHIFT) +#define DPAUX_DP_AUXCTL_SEMA_REQUEST_RANGE 21:20 +#define DPAUX_DP_AUXCTL_SEMA_REQUEST_WOFFSET 0x0 +#define DPAUX_DP_AUXCTL_SEMA_REQUEST_DEFAULT _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUXCTL_SEMA_REQUEST_DEFAULT_MASK _MK_MASK_CONST(0x3) +#define DPAUX_DP_AUXCTL_SEMA_REQUEST_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUXCTL_SEMA_REQUEST_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUXCTL_SEMA_REQUEST_INIT_ENUM RELEASE +#define DPAUX_DP_AUXCTL_SEMA_REQUEST_RELEASE _MK_ENUM_CONST(0) +#define DPAUX_DP_AUXCTL_SEMA_REQUEST_RM _MK_ENUM_CONST(1) +#define DPAUX_DP_AUXCTL_SEMA_REQUEST_VBIOS _MK_ENUM_CONST(2) +#define DPAUX_DP_AUXCTL_SEMA_REQUEST_PMU _MK_ENUM_CONST(3) + +#define DPAUX_DP_AUXCTL_TRANSACTREQ_SHIFT _MK_SHIFT_CONST(16) +#define DPAUX_DP_AUXCTL_TRANSACTREQ_FIELD _MK_FIELD_CONST(0x1, DPAUX_DP_AUXCTL_TRANSACTREQ_SHIFT) +#define DPAUX_DP_AUXCTL_TRANSACTREQ_RANGE 16:16 +#define DPAUX_DP_AUXCTL_TRANSACTREQ_WOFFSET 0x0 +#define DPAUX_DP_AUXCTL_TRANSACTREQ_DEFAULT _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUXCTL_TRANSACTREQ_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DPAUX_DP_AUXCTL_TRANSACTREQ_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUXCTL_TRANSACTREQ_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUXCTL_TRANSACTREQ_INIT_ENUM DONE +#define DPAUX_DP_AUXCTL_TRANSACTREQ_DONE _MK_ENUM_CONST(0) +#define DPAUX_DP_AUXCTL_TRANSACTREQ_PENDING _MK_ENUM_CONST(1) + +#define DPAUX_DP_AUXCTL_CMD_SHIFT _MK_SHIFT_CONST(12) +#define DPAUX_DP_AUXCTL_CMD_FIELD _MK_FIELD_CONST(0xf, DPAUX_DP_AUXCTL_CMD_SHIFT) +#define DPAUX_DP_AUXCTL_CMD_RANGE 15:12 +#define DPAUX_DP_AUXCTL_CMD_WOFFSET 0x0 +#define DPAUX_DP_AUXCTL_CMD_DEFAULT _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUXCTL_CMD_DEFAULT_MASK _MK_MASK_CONST(0xf) +#define DPAUX_DP_AUXCTL_CMD_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUXCTL_CMD_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUXCTL_CMD_INIT_ENUM I2CWR +#define DPAUX_DP_AUXCTL_CMD_I2CWR _MK_ENUM_CONST(0) +#define DPAUX_DP_AUXCTL_CMD_I2CRD _MK_ENUM_CONST(1) +#define DPAUX_DP_AUXCTL_CMD_I2CREQWSTAT _MK_ENUM_CONST(2) +#define DPAUX_DP_AUXCTL_CMD_MOTWR _MK_ENUM_CONST(4) +#define DPAUX_DP_AUXCTL_CMD_MOTRD _MK_ENUM_CONST(5) +#define DPAUX_DP_AUXCTL_CMD_MOTREQWSTAT _MK_ENUM_CONST(6) +#define DPAUX_DP_AUXCTL_CMD_AUXWR _MK_ENUM_CONST(8) +#define DPAUX_DP_AUXCTL_CMD_AUXRD _MK_ENUM_CONST(9) + +#define DPAUX_DP_AUXCTL_ADDRESS_ONLY_SHIFT _MK_SHIFT_CONST(8) +#define DPAUX_DP_AUXCTL_ADDRESS_ONLY_FIELD _MK_FIELD_CONST(0x1, DPAUX_DP_AUXCTL_ADDRESS_ONLY_SHIFT) +#define DPAUX_DP_AUXCTL_ADDRESS_ONLY_RANGE 8:8 +#define DPAUX_DP_AUXCTL_ADDRESS_ONLY_WOFFSET 0x0 +#define DPAUX_DP_AUXCTL_ADDRESS_ONLY_DEFAULT _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUXCTL_ADDRESS_ONLY_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DPAUX_DP_AUXCTL_ADDRESS_ONLY_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUXCTL_ADDRESS_ONLY_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUXCTL_ADDRESS_ONLY_INIT_ENUM NO +#define DPAUX_DP_AUXCTL_ADDRESS_ONLY_NO _MK_ENUM_CONST(0) +#define DPAUX_DP_AUXCTL_ADDRESS_ONLY_YES _MK_ENUM_CONST(1) + +#define DPAUX_DP_AUXCTL_CMDLEN_SHIFT _MK_SHIFT_CONST(0) +#define DPAUX_DP_AUXCTL_CMDLEN_FIELD _MK_FIELD_CONST(0xff, DPAUX_DP_AUXCTL_CMDLEN_SHIFT) +#define DPAUX_DP_AUXCTL_CMDLEN_RANGE 7:0 +#define DPAUX_DP_AUXCTL_CMDLEN_WOFFSET 0x0 +#define DPAUX_DP_AUXCTL_CMDLEN_DEFAULT _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUXCTL_CMDLEN_DEFAULT_MASK _MK_MASK_CONST(0xff) +#define DPAUX_DP_AUXCTL_CMDLEN_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUXCTL_CMDLEN_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DPAUX_DP_AUXSTAT_0 +#define DPAUX_DP_AUXSTAT_0 _MK_ADDR_CONST(0x31) +#define DPAUX_DP_AUXSTAT_0_SECURE 0x0 +#define DPAUX_DP_AUXSTAT_0_WORD_COUNT 0x1 +#define DPAUX_DP_AUXSTAT_0_RESET_VAL _MK_MASK_CONST(0x10000000) +#define DPAUX_DP_AUXSTAT_0_RESET_MASK _MK_MASK_CONST(0x10f00f00) +#define DPAUX_DP_AUXSTAT_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUXSTAT_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUXSTAT_0_READ_MASK _MK_MASK_CONST(0x10ff0fff) +#define DPAUX_DP_AUXSTAT_0_WRITE_MASK _MK_MASK_CONST(0xf00) +#define DPAUX_DP_AUXSTAT_0_HPD_STATUS_SHIFT _MK_SHIFT_CONST(28) +#define DPAUX_DP_AUXSTAT_0_HPD_STATUS_FIELD _MK_FIELD_CONST(0x1, DPAUX_DP_AUXSTAT_0_HPD_STATUS_SHIFT) +#define DPAUX_DP_AUXSTAT_0_HPD_STATUS_RANGE 28:28 +#define DPAUX_DP_AUXSTAT_0_HPD_STATUS_WOFFSET 0x0 +#define DPAUX_DP_AUXSTAT_0_HPD_STATUS_DEFAULT _MK_MASK_CONST(0x1) +#define DPAUX_DP_AUXSTAT_0_HPD_STATUS_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DPAUX_DP_AUXSTAT_0_HPD_STATUS_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUXSTAT_0_HPD_STATUS_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUXSTAT_0_HPD_STATUS_INIT_ENUM PLUGGED +#define DPAUX_DP_AUXSTAT_0_HPD_STATUS_UNPLUG _MK_ENUM_CONST(0) +#define DPAUX_DP_AUXSTAT_0_HPD_STATUS_PLUGGED _MK_ENUM_CONST(1) + +#define DPAUX_DP_AUXSTAT_0_AUXCTL_STATE_SHIFT _MK_SHIFT_CONST(20) +#define DPAUX_DP_AUXSTAT_0_AUXCTL_STATE_FIELD _MK_FIELD_CONST(0xf, DPAUX_DP_AUXSTAT_0_AUXCTL_STATE_SHIFT) +#define DPAUX_DP_AUXSTAT_0_AUXCTL_STATE_RANGE 23:20 +#define DPAUX_DP_AUXSTAT_0_AUXCTL_STATE_WOFFSET 0x0 +#define DPAUX_DP_AUXSTAT_0_AUXCTL_STATE_DEFAULT _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUXSTAT_0_AUXCTL_STATE_DEFAULT_MASK _MK_MASK_CONST(0xf) +#define DPAUX_DP_AUXSTAT_0_AUXCTL_STATE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUXSTAT_0_AUXCTL_STATE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUXSTAT_0_AUXCTL_STATE_INIT_ENUM IDLE +#define DPAUX_DP_AUXSTAT_0_AUXCTL_STATE_IDLE _MK_ENUM_CONST(0) +#define DPAUX_DP_AUXSTAT_0_AUXCTL_STATE_SYNC _MK_ENUM_CONST(1) +#define DPAUX_DP_AUXSTAT_0_AUXCTL_STATE_START1 _MK_ENUM_CONST(2) +#define DPAUX_DP_AUXSTAT_0_AUXCTL_STATE_COMMAND _MK_ENUM_CONST(3) +#define DPAUX_DP_AUXSTAT_0_AUXCTL_STATE_ADDRESS _MK_ENUM_CONST(4) +#define DPAUX_DP_AUXSTAT_0_AUXCTL_STATE_LENGTH _MK_ENUM_CONST(5) +#define DPAUX_DP_AUXSTAT_0_AUXCTL_STATE_WRITE1 _MK_ENUM_CONST(6) +#define DPAUX_DP_AUXSTAT_0_AUXCTL_STATE_READ1 _MK_ENUM_CONST(7) +#define DPAUX_DP_AUXSTAT_0_AUXCTL_STATE_GET_M _MK_ENUM_CONST(8) +#define DPAUX_DP_AUXSTAT_0_AUXCTL_STATE_STOP1 _MK_ENUM_CONST(9) +#define DPAUX_DP_AUXSTAT_0_AUXCTL_STATE_STOP2 _MK_ENUM_CONST(10) +#define DPAUX_DP_AUXSTAT_0_AUXCTL_STATE_REPLY _MK_ENUM_CONST(11) +#define DPAUX_DP_AUXSTAT_0_AUXCTL_STATE_CLEANUP _MK_ENUM_CONST(12) + +#define DPAUX_DP_AUXSTAT_0_REPLYTYPE_SHIFT _MK_SHIFT_CONST(16) +#define DPAUX_DP_AUXSTAT_0_REPLYTYPE_FIELD _MK_FIELD_CONST(0xf, DPAUX_DP_AUXSTAT_0_REPLYTYPE_SHIFT) +#define DPAUX_DP_AUXSTAT_0_REPLYTYPE_RANGE 19:16 +#define DPAUX_DP_AUXSTAT_0_REPLYTYPE_WOFFSET 0x0 +#define DPAUX_DP_AUXSTAT_0_REPLYTYPE_DEFAULT _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUXSTAT_0_REPLYTYPE_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUXSTAT_0_REPLYTYPE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUXSTAT_0_REPLYTYPE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUXSTAT_0_REPLYTYPE_ACK _MK_ENUM_CONST(0) +#define DPAUX_DP_AUXSTAT_0_REPLYTYPE_NACK _MK_ENUM_CONST(1) +#define DPAUX_DP_AUXSTAT_0_REPLYTYPE_DEFER _MK_ENUM_CONST(2) +#define DPAUX_DP_AUXSTAT_0_REPLYTYPE_I2CNACK _MK_ENUM_CONST(4) +#define DPAUX_DP_AUXSTAT_0_REPLYTYPE_I2CDEFER _MK_ENUM_CONST(8) + +#define DPAUX_DP_AUXSTAT_0_NO_STOP_ERROR_SHIFT _MK_SHIFT_CONST(11) +#define DPAUX_DP_AUXSTAT_0_NO_STOP_ERROR_FIELD _MK_FIELD_CONST(0x1, DPAUX_DP_AUXSTAT_0_NO_STOP_ERROR_SHIFT) +#define DPAUX_DP_AUXSTAT_0_NO_STOP_ERROR_RANGE 11:11 +#define DPAUX_DP_AUXSTAT_0_NO_STOP_ERROR_WOFFSET 0x0 +#define DPAUX_DP_AUXSTAT_0_NO_STOP_ERROR_DEFAULT _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUXSTAT_0_NO_STOP_ERROR_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DPAUX_DP_AUXSTAT_0_NO_STOP_ERROR_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUXSTAT_0_NO_STOP_ERROR_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUXSTAT_0_NO_STOP_ERROR_INIT_ENUM NOT_PENDING +#define DPAUX_DP_AUXSTAT_0_NO_STOP_ERROR_NOT_PENDING _MK_ENUM_CONST(0) +#define DPAUX_DP_AUXSTAT_0_NO_STOP_ERROR_PENDING _MK_ENUM_CONST(1) + +#define DPAUX_DP_AUXSTAT_0_SINKSTAT_ERROR_SHIFT _MK_SHIFT_CONST(10) +#define DPAUX_DP_AUXSTAT_0_SINKSTAT_ERROR_FIELD _MK_FIELD_CONST(0x1, DPAUX_DP_AUXSTAT_0_SINKSTAT_ERROR_SHIFT) +#define DPAUX_DP_AUXSTAT_0_SINKSTAT_ERROR_RANGE 10:10 +#define DPAUX_DP_AUXSTAT_0_SINKSTAT_ERROR_WOFFSET 0x0 +#define DPAUX_DP_AUXSTAT_0_SINKSTAT_ERROR_DEFAULT _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUXSTAT_0_SINKSTAT_ERROR_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DPAUX_DP_AUXSTAT_0_SINKSTAT_ERROR_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUXSTAT_0_SINKSTAT_ERROR_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUXSTAT_0_SINKSTAT_ERROR_INIT_ENUM NOT_PENDING +#define DPAUX_DP_AUXSTAT_0_SINKSTAT_ERROR_NOT_PENDING _MK_ENUM_CONST(0) +#define DPAUX_DP_AUXSTAT_0_SINKSTAT_ERROR_PENDING _MK_ENUM_CONST(1) + +#define DPAUX_DP_AUXSTAT_0_RX_ERROR_SHIFT _MK_SHIFT_CONST(9) +#define DPAUX_DP_AUXSTAT_0_RX_ERROR_FIELD _MK_FIELD_CONST(0x1, DPAUX_DP_AUXSTAT_0_RX_ERROR_SHIFT) +#define DPAUX_DP_AUXSTAT_0_RX_ERROR_RANGE 9:9 +#define DPAUX_DP_AUXSTAT_0_RX_ERROR_WOFFSET 0x0 +#define DPAUX_DP_AUXSTAT_0_RX_ERROR_DEFAULT _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUXSTAT_0_RX_ERROR_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DPAUX_DP_AUXSTAT_0_RX_ERROR_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUXSTAT_0_RX_ERROR_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUXSTAT_0_RX_ERROR_INIT_ENUM NOT_PENDING +#define DPAUX_DP_AUXSTAT_0_RX_ERROR_NOT_PENDING _MK_ENUM_CONST(0) +#define DPAUX_DP_AUXSTAT_0_RX_ERROR_PENDING _MK_ENUM_CONST(1) + +#define DPAUX_DP_AUXSTAT_0_TIMEOUT_ERROR_SHIFT _MK_SHIFT_CONST(8) +#define DPAUX_DP_AUXSTAT_0_TIMEOUT_ERROR_FIELD _MK_FIELD_CONST(0x1, DPAUX_DP_AUXSTAT_0_TIMEOUT_ERROR_SHIFT) +#define DPAUX_DP_AUXSTAT_0_TIMEOUT_ERROR_RANGE 8:8 +#define DPAUX_DP_AUXSTAT_0_TIMEOUT_ERROR_WOFFSET 0x0 +#define DPAUX_DP_AUXSTAT_0_TIMEOUT_ERROR_DEFAULT _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUXSTAT_0_TIMEOUT_ERROR_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DPAUX_DP_AUXSTAT_0_TIMEOUT_ERROR_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUXSTAT_0_TIMEOUT_ERROR_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUXSTAT_0_TIMEOUT_ERROR_INIT_ENUM NOT_PENDING +#define DPAUX_DP_AUXSTAT_0_TIMEOUT_ERROR_NOT_PENDING _MK_ENUM_CONST(0) +#define DPAUX_DP_AUXSTAT_0_TIMEOUT_ERROR_PENDING _MK_ENUM_CONST(1) + +#define DPAUX_DP_AUXSTAT_0_REPLY_M_SHIFT _MK_SHIFT_CONST(0) +#define DPAUX_DP_AUXSTAT_0_REPLY_M_FIELD _MK_FIELD_CONST(0xff, DPAUX_DP_AUXSTAT_0_REPLY_M_SHIFT) +#define DPAUX_DP_AUXSTAT_0_REPLY_M_RANGE 7:0 +#define DPAUX_DP_AUXSTAT_0_REPLY_M_WOFFSET 0x0 +#define DPAUX_DP_AUXSTAT_0_REPLY_M_DEFAULT _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUXSTAT_0_REPLY_M_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUXSTAT_0_REPLY_M_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUXSTAT_0_REPLY_M_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DPAUX_DP_AUXSTAT +#define DPAUX_DP_AUXSTAT _MK_ADDR_CONST(0x31) +#define DPAUX_DP_AUXSTAT_SECURE 0x0 +#define DPAUX_DP_AUXSTAT_WORD_COUNT 0x1 +#define DPAUX_DP_AUXSTAT_RESET_VAL _MK_MASK_CONST(0x10000000) +#define DPAUX_DP_AUXSTAT_RESET_MASK _MK_MASK_CONST(0x10f00f00) +#define DPAUX_DP_AUXSTAT_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUXSTAT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUXSTAT_READ_MASK _MK_MASK_CONST(0x10ff0fff) +#define DPAUX_DP_AUXSTAT_WRITE_MASK _MK_MASK_CONST(0xf00) +#define DPAUX_DP_AUXSTAT_HPD_STATUS_SHIFT _MK_SHIFT_CONST(28) +#define DPAUX_DP_AUXSTAT_HPD_STATUS_FIELD _MK_FIELD_CONST(0x1, DPAUX_DP_AUXSTAT_HPD_STATUS_SHIFT) +#define DPAUX_DP_AUXSTAT_HPD_STATUS_RANGE 28:28 +#define DPAUX_DP_AUXSTAT_HPD_STATUS_WOFFSET 0x0 +#define DPAUX_DP_AUXSTAT_HPD_STATUS_DEFAULT _MK_MASK_CONST(0x1) +#define DPAUX_DP_AUXSTAT_HPD_STATUS_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DPAUX_DP_AUXSTAT_HPD_STATUS_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUXSTAT_HPD_STATUS_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUXSTAT_HPD_STATUS_INIT_ENUM PLUGGED +#define DPAUX_DP_AUXSTAT_HPD_STATUS_UNPLUG _MK_ENUM_CONST(0) +#define DPAUX_DP_AUXSTAT_HPD_STATUS_PLUGGED _MK_ENUM_CONST(1) + +#define DPAUX_DP_AUXSTAT_AUXCTL_STATE_SHIFT _MK_SHIFT_CONST(20) +#define DPAUX_DP_AUXSTAT_AUXCTL_STATE_FIELD _MK_FIELD_CONST(0xf, DPAUX_DP_AUXSTAT_AUXCTL_STATE_SHIFT) +#define DPAUX_DP_AUXSTAT_AUXCTL_STATE_RANGE 23:20 +#define DPAUX_DP_AUXSTAT_AUXCTL_STATE_WOFFSET 0x0 +#define DPAUX_DP_AUXSTAT_AUXCTL_STATE_DEFAULT _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUXSTAT_AUXCTL_STATE_DEFAULT_MASK _MK_MASK_CONST(0xf) +#define DPAUX_DP_AUXSTAT_AUXCTL_STATE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUXSTAT_AUXCTL_STATE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUXSTAT_AUXCTL_STATE_INIT_ENUM IDLE +#define DPAUX_DP_AUXSTAT_AUXCTL_STATE_IDLE _MK_ENUM_CONST(0) +#define DPAUX_DP_AUXSTAT_AUXCTL_STATE_SYNC _MK_ENUM_CONST(1) +#define DPAUX_DP_AUXSTAT_AUXCTL_STATE_START1 _MK_ENUM_CONST(2) +#define DPAUX_DP_AUXSTAT_AUXCTL_STATE_COMMAND _MK_ENUM_CONST(3) +#define DPAUX_DP_AUXSTAT_AUXCTL_STATE_ADDRESS _MK_ENUM_CONST(4) +#define DPAUX_DP_AUXSTAT_AUXCTL_STATE_LENGTH _MK_ENUM_CONST(5) +#define DPAUX_DP_AUXSTAT_AUXCTL_STATE_WRITE1 _MK_ENUM_CONST(6) +#define DPAUX_DP_AUXSTAT_AUXCTL_STATE_READ1 _MK_ENUM_CONST(7) +#define DPAUX_DP_AUXSTAT_AUXCTL_STATE_GET_M _MK_ENUM_CONST(8) +#define DPAUX_DP_AUXSTAT_AUXCTL_STATE_STOP1 _MK_ENUM_CONST(9) +#define DPAUX_DP_AUXSTAT_AUXCTL_STATE_STOP2 _MK_ENUM_CONST(10) +#define DPAUX_DP_AUXSTAT_AUXCTL_STATE_REPLY _MK_ENUM_CONST(11) +#define DPAUX_DP_AUXSTAT_AUXCTL_STATE_CLEANUP _MK_ENUM_CONST(12) + +#define DPAUX_DP_AUXSTAT_REPLYTYPE_SHIFT _MK_SHIFT_CONST(16) +#define DPAUX_DP_AUXSTAT_REPLYTYPE_FIELD _MK_FIELD_CONST(0xf, DPAUX_DP_AUXSTAT_REPLYTYPE_SHIFT) +#define DPAUX_DP_AUXSTAT_REPLYTYPE_RANGE 19:16 +#define DPAUX_DP_AUXSTAT_REPLYTYPE_WOFFSET 0x0 +#define DPAUX_DP_AUXSTAT_REPLYTYPE_DEFAULT _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUXSTAT_REPLYTYPE_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUXSTAT_REPLYTYPE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUXSTAT_REPLYTYPE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUXSTAT_REPLYTYPE_ACK _MK_ENUM_CONST(0) +#define DPAUX_DP_AUXSTAT_REPLYTYPE_NACK _MK_ENUM_CONST(1) +#define DPAUX_DP_AUXSTAT_REPLYTYPE_DEFER _MK_ENUM_CONST(2) +#define DPAUX_DP_AUXSTAT_REPLYTYPE_I2CNACK _MK_ENUM_CONST(4) +#define DPAUX_DP_AUXSTAT_REPLYTYPE_I2CDEFER _MK_ENUM_CONST(8) + +#define DPAUX_DP_AUXSTAT_NO_STOP_ERROR_SHIFT _MK_SHIFT_CONST(11) +#define DPAUX_DP_AUXSTAT_NO_STOP_ERROR_FIELD _MK_FIELD_CONST(0x1, DPAUX_DP_AUXSTAT_NO_STOP_ERROR_SHIFT) +#define DPAUX_DP_AUXSTAT_NO_STOP_ERROR_RANGE 11:11 +#define DPAUX_DP_AUXSTAT_NO_STOP_ERROR_WOFFSET 0x0 +#define DPAUX_DP_AUXSTAT_NO_STOP_ERROR_DEFAULT _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUXSTAT_NO_STOP_ERROR_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DPAUX_DP_AUXSTAT_NO_STOP_ERROR_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUXSTAT_NO_STOP_ERROR_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUXSTAT_NO_STOP_ERROR_INIT_ENUM NOT_PENDING +#define DPAUX_DP_AUXSTAT_NO_STOP_ERROR_NOT_PENDING _MK_ENUM_CONST(0) +#define DPAUX_DP_AUXSTAT_NO_STOP_ERROR_PENDING _MK_ENUM_CONST(1) + +#define DPAUX_DP_AUXSTAT_SINKSTAT_ERROR_SHIFT _MK_SHIFT_CONST(10) +#define DPAUX_DP_AUXSTAT_SINKSTAT_ERROR_FIELD _MK_FIELD_CONST(0x1, DPAUX_DP_AUXSTAT_SINKSTAT_ERROR_SHIFT) +#define DPAUX_DP_AUXSTAT_SINKSTAT_ERROR_RANGE 10:10 +#define DPAUX_DP_AUXSTAT_SINKSTAT_ERROR_WOFFSET 0x0 +#define DPAUX_DP_AUXSTAT_SINKSTAT_ERROR_DEFAULT _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUXSTAT_SINKSTAT_ERROR_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DPAUX_DP_AUXSTAT_SINKSTAT_ERROR_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUXSTAT_SINKSTAT_ERROR_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUXSTAT_SINKSTAT_ERROR_INIT_ENUM NOT_PENDING +#define DPAUX_DP_AUXSTAT_SINKSTAT_ERROR_NOT_PENDING _MK_ENUM_CONST(0) +#define DPAUX_DP_AUXSTAT_SINKSTAT_ERROR_PENDING _MK_ENUM_CONST(1) + +#define DPAUX_DP_AUXSTAT_RX_ERROR_SHIFT _MK_SHIFT_CONST(9) +#define DPAUX_DP_AUXSTAT_RX_ERROR_FIELD _MK_FIELD_CONST(0x1, DPAUX_DP_AUXSTAT_RX_ERROR_SHIFT) +#define DPAUX_DP_AUXSTAT_RX_ERROR_RANGE 9:9 +#define DPAUX_DP_AUXSTAT_RX_ERROR_WOFFSET 0x0 +#define DPAUX_DP_AUXSTAT_RX_ERROR_DEFAULT _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUXSTAT_RX_ERROR_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DPAUX_DP_AUXSTAT_RX_ERROR_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUXSTAT_RX_ERROR_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUXSTAT_RX_ERROR_INIT_ENUM NOT_PENDING +#define DPAUX_DP_AUXSTAT_RX_ERROR_NOT_PENDING _MK_ENUM_CONST(0) +#define DPAUX_DP_AUXSTAT_RX_ERROR_PENDING _MK_ENUM_CONST(1) + +#define DPAUX_DP_AUXSTAT_TIMEOUT_ERROR_SHIFT _MK_SHIFT_CONST(8) +#define DPAUX_DP_AUXSTAT_TIMEOUT_ERROR_FIELD _MK_FIELD_CONST(0x1, DPAUX_DP_AUXSTAT_TIMEOUT_ERROR_SHIFT) +#define DPAUX_DP_AUXSTAT_TIMEOUT_ERROR_RANGE 8:8 +#define DPAUX_DP_AUXSTAT_TIMEOUT_ERROR_WOFFSET 0x0 +#define DPAUX_DP_AUXSTAT_TIMEOUT_ERROR_DEFAULT _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUXSTAT_TIMEOUT_ERROR_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DPAUX_DP_AUXSTAT_TIMEOUT_ERROR_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUXSTAT_TIMEOUT_ERROR_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUXSTAT_TIMEOUT_ERROR_INIT_ENUM NOT_PENDING +#define DPAUX_DP_AUXSTAT_TIMEOUT_ERROR_NOT_PENDING _MK_ENUM_CONST(0) +#define DPAUX_DP_AUXSTAT_TIMEOUT_ERROR_PENDING _MK_ENUM_CONST(1) + +#define DPAUX_DP_AUXSTAT_REPLY_M_SHIFT _MK_SHIFT_CONST(0) +#define DPAUX_DP_AUXSTAT_REPLY_M_FIELD _MK_FIELD_CONST(0xff, DPAUX_DP_AUXSTAT_REPLY_M_SHIFT) +#define DPAUX_DP_AUXSTAT_REPLY_M_RANGE 7:0 +#define DPAUX_DP_AUXSTAT_REPLY_M_WOFFSET 0x0 +#define DPAUX_DP_AUXSTAT_REPLY_M_DEFAULT _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUXSTAT_REPLY_M_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUXSTAT_REPLY_M_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUXSTAT_REPLY_M_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DPAUX_DP_AUX_SINKSTATLO_0 +#define DPAUX_DP_AUX_SINKSTATLO_0 _MK_ADDR_CONST(0x35) +#define DPAUX_DP_AUX_SINKSTATLO_0_SECURE 0x0 +#define DPAUX_DP_AUX_SINKSTATLO_0_WORD_COUNT 0x1 +#define DPAUX_DP_AUX_SINKSTATLO_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUX_SINKSTATLO_0_RESET_MASK _MK_MASK_CONST(0xffffffff) +#define DPAUX_DP_AUX_SINKSTATLO_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUX_SINKSTATLO_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUX_SINKSTATLO_0_READ_MASK _MK_MASK_CONST(0xffffffff) +#define DPAUX_DP_AUX_SINKSTATLO_0_WRITE_MASK _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUX_SINKSTATLO_0_REG_SHIFT _MK_SHIFT_CONST(0) +#define DPAUX_DP_AUX_SINKSTATLO_0_REG_FIELD _MK_FIELD_CONST(0xffffffff, DPAUX_DP_AUX_SINKSTATLO_0_REG_SHIFT) +#define DPAUX_DP_AUX_SINKSTATLO_0_REG_RANGE 31:0 +#define DPAUX_DP_AUX_SINKSTATLO_0_REG_WOFFSET 0x0 +#define DPAUX_DP_AUX_SINKSTATLO_0_REG_DEFAULT _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUX_SINKSTATLO_0_REG_DEFAULT_MASK _MK_MASK_CONST(0xffffffff) +#define DPAUX_DP_AUX_SINKSTATLO_0_REG_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUX_SINKSTATLO_0_REG_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DPAUX_DP_AUX_SINKSTATLO +#define DPAUX_DP_AUX_SINKSTATLO _MK_ADDR_CONST(0x35) +#define DPAUX_DP_AUX_SINKSTATLO_SECURE 0x0 +#define DPAUX_DP_AUX_SINKSTATLO_WORD_COUNT 0x1 +#define DPAUX_DP_AUX_SINKSTATLO_RESET_VAL _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUX_SINKSTATLO_RESET_MASK _MK_MASK_CONST(0xffffffff) +#define DPAUX_DP_AUX_SINKSTATLO_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUX_SINKSTATLO_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUX_SINKSTATLO_READ_MASK _MK_MASK_CONST(0xffffffff) +#define DPAUX_DP_AUX_SINKSTATLO_WRITE_MASK _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUX_SINKSTATLO_REG_SHIFT _MK_SHIFT_CONST(0) +#define DPAUX_DP_AUX_SINKSTATLO_REG_FIELD _MK_FIELD_CONST(0xffffffff, DPAUX_DP_AUX_SINKSTATLO_REG_SHIFT) +#define DPAUX_DP_AUX_SINKSTATLO_REG_RANGE 31:0 +#define DPAUX_DP_AUX_SINKSTATLO_REG_WOFFSET 0x0 +#define DPAUX_DP_AUX_SINKSTATLO_REG_DEFAULT _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUX_SINKSTATLO_REG_DEFAULT_MASK _MK_MASK_CONST(0xffffffff) +#define DPAUX_DP_AUX_SINKSTATLO_REG_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUX_SINKSTATLO_REG_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DPAUX_DP_AUX_SINKSTATHI_0 +#define DPAUX_DP_AUX_SINKSTATHI_0 _MK_ADDR_CONST(0x39) +#define DPAUX_DP_AUX_SINKSTATHI_0_SECURE 0x0 +#define DPAUX_DP_AUX_SINKSTATHI_0_WORD_COUNT 0x1 +#define DPAUX_DP_AUX_SINKSTATHI_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUX_SINKSTATHI_0_RESET_MASK _MK_MASK_CONST(0xffff) +#define DPAUX_DP_AUX_SINKSTATHI_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUX_SINKSTATHI_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUX_SINKSTATHI_0_READ_MASK _MK_MASK_CONST(0xffff) +#define DPAUX_DP_AUX_SINKSTATHI_0_WRITE_MASK _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUX_SINKSTATHI_0_REG_SHIFT _MK_SHIFT_CONST(0) +#define DPAUX_DP_AUX_SINKSTATHI_0_REG_FIELD _MK_FIELD_CONST(0xffff, DPAUX_DP_AUX_SINKSTATHI_0_REG_SHIFT) +#define DPAUX_DP_AUX_SINKSTATHI_0_REG_RANGE 15:0 +#define DPAUX_DP_AUX_SINKSTATHI_0_REG_WOFFSET 0x0 +#define DPAUX_DP_AUX_SINKSTATHI_0_REG_DEFAULT _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUX_SINKSTATHI_0_REG_DEFAULT_MASK _MK_MASK_CONST(0xffff) +#define DPAUX_DP_AUX_SINKSTATHI_0_REG_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUX_SINKSTATHI_0_REG_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DPAUX_DP_AUX_SINKSTATHI +#define DPAUX_DP_AUX_SINKSTATHI _MK_ADDR_CONST(0x39) +#define DPAUX_DP_AUX_SINKSTATHI_SECURE 0x0 +#define DPAUX_DP_AUX_SINKSTATHI_WORD_COUNT 0x1 +#define DPAUX_DP_AUX_SINKSTATHI_RESET_VAL _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUX_SINKSTATHI_RESET_MASK _MK_MASK_CONST(0xffff) +#define DPAUX_DP_AUX_SINKSTATHI_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUX_SINKSTATHI_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUX_SINKSTATHI_READ_MASK _MK_MASK_CONST(0xffff) +#define DPAUX_DP_AUX_SINKSTATHI_WRITE_MASK _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUX_SINKSTATHI_REG_SHIFT _MK_SHIFT_CONST(0) +#define DPAUX_DP_AUX_SINKSTATHI_REG_FIELD _MK_FIELD_CONST(0xffff, DPAUX_DP_AUX_SINKSTATHI_REG_SHIFT) +#define DPAUX_DP_AUX_SINKSTATHI_REG_RANGE 15:0 +#define DPAUX_DP_AUX_SINKSTATHI_REG_WOFFSET 0x0 +#define DPAUX_DP_AUX_SINKSTATHI_REG_DEFAULT _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUX_SINKSTATHI_REG_DEFAULT_MASK _MK_MASK_CONST(0xffff) +#define DPAUX_DP_AUX_SINKSTATHI_REG_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUX_SINKSTATHI_REG_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DPAUX_HPD_CONFIG_0 +#define DPAUX_HPD_CONFIG_0 _MK_ADDR_CONST(0x3d) +#define DPAUX_HPD_CONFIG_0_SECURE 0x0 +#define DPAUX_HPD_CONFIG_0_WORD_COUNT 0x1 +#define DPAUX_HPD_CONFIG_0_RESET_VAL _MK_MASK_CONST(0x7d000fa) +#define DPAUX_HPD_CONFIG_0_RESET_MASK _MK_MASK_CONST(0xffffffff) +#define DPAUX_HPD_CONFIG_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DPAUX_HPD_CONFIG_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DPAUX_HPD_CONFIG_0_READ_MASK _MK_MASK_CONST(0xffffffff) +#define DPAUX_HPD_CONFIG_0_WRITE_MASK _MK_MASK_CONST(0xffffffff) +#define DPAUX_HPD_CONFIG_0_UNPLUG_MIN_TIME_SHIFT _MK_SHIFT_CONST(16) +#define DPAUX_HPD_CONFIG_0_UNPLUG_MIN_TIME_FIELD _MK_FIELD_CONST(0xffff, DPAUX_HPD_CONFIG_0_UNPLUG_MIN_TIME_SHIFT) +#define DPAUX_HPD_CONFIG_0_UNPLUG_MIN_TIME_RANGE 31:16 +#define DPAUX_HPD_CONFIG_0_UNPLUG_MIN_TIME_WOFFSET 0x0 +#define DPAUX_HPD_CONFIG_0_UNPLUG_MIN_TIME_DEFAULT _MK_MASK_CONST(0x7d0) +#define DPAUX_HPD_CONFIG_0_UNPLUG_MIN_TIME_DEFAULT_MASK _MK_MASK_CONST(0xffff) +#define DPAUX_HPD_CONFIG_0_UNPLUG_MIN_TIME_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DPAUX_HPD_CONFIG_0_UNPLUG_MIN_TIME_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DPAUX_HPD_CONFIG_0_PLUG_MIN_TIME_SHIFT _MK_SHIFT_CONST(0) +#define DPAUX_HPD_CONFIG_0_PLUG_MIN_TIME_FIELD _MK_FIELD_CONST(0xffff, DPAUX_HPD_CONFIG_0_PLUG_MIN_TIME_SHIFT) +#define DPAUX_HPD_CONFIG_0_PLUG_MIN_TIME_RANGE 15:0 +#define DPAUX_HPD_CONFIG_0_PLUG_MIN_TIME_WOFFSET 0x0 +#define DPAUX_HPD_CONFIG_0_PLUG_MIN_TIME_DEFAULT _MK_MASK_CONST(0xfa) +#define DPAUX_HPD_CONFIG_0_PLUG_MIN_TIME_DEFAULT_MASK _MK_MASK_CONST(0xffff) +#define DPAUX_HPD_CONFIG_0_PLUG_MIN_TIME_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DPAUX_HPD_CONFIG_0_PLUG_MIN_TIME_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DPAUX_HPD_CONFIG +#define DPAUX_HPD_CONFIG _MK_ADDR_CONST(0x3d) +#define DPAUX_HPD_CONFIG_SECURE 0x0 +#define DPAUX_HPD_CONFIG_WORD_COUNT 0x1 +#define DPAUX_HPD_CONFIG_RESET_VAL _MK_MASK_CONST(0x7d000fa) +#define DPAUX_HPD_CONFIG_RESET_MASK _MK_MASK_CONST(0xffffffff) +#define DPAUX_HPD_CONFIG_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DPAUX_HPD_CONFIG_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DPAUX_HPD_CONFIG_READ_MASK _MK_MASK_CONST(0xffffffff) +#define DPAUX_HPD_CONFIG_WRITE_MASK _MK_MASK_CONST(0xffffffff) +#define DPAUX_HPD_CONFIG_UNPLUG_MIN_TIME_SHIFT _MK_SHIFT_CONST(16) +#define DPAUX_HPD_CONFIG_UNPLUG_MIN_TIME_FIELD _MK_FIELD_CONST(0xffff, DPAUX_HPD_CONFIG_UNPLUG_MIN_TIME_SHIFT) +#define DPAUX_HPD_CONFIG_UNPLUG_MIN_TIME_RANGE 31:16 +#define DPAUX_HPD_CONFIG_UNPLUG_MIN_TIME_WOFFSET 0x0 +#define DPAUX_HPD_CONFIG_UNPLUG_MIN_TIME_DEFAULT _MK_MASK_CONST(0x7d0) +#define DPAUX_HPD_CONFIG_UNPLUG_MIN_TIME_DEFAULT_MASK _MK_MASK_CONST(0xffff) +#define DPAUX_HPD_CONFIG_UNPLUG_MIN_TIME_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DPAUX_HPD_CONFIG_UNPLUG_MIN_TIME_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DPAUX_HPD_CONFIG_PLUG_MIN_TIME_SHIFT _MK_SHIFT_CONST(0) +#define DPAUX_HPD_CONFIG_PLUG_MIN_TIME_FIELD _MK_FIELD_CONST(0xffff, DPAUX_HPD_CONFIG_PLUG_MIN_TIME_SHIFT) +#define DPAUX_HPD_CONFIG_PLUG_MIN_TIME_RANGE 15:0 +#define DPAUX_HPD_CONFIG_PLUG_MIN_TIME_WOFFSET 0x0 +#define DPAUX_HPD_CONFIG_PLUG_MIN_TIME_DEFAULT _MK_MASK_CONST(0xfa) +#define DPAUX_HPD_CONFIG_PLUG_MIN_TIME_DEFAULT_MASK _MK_MASK_CONST(0xffff) +#define DPAUX_HPD_CONFIG_PLUG_MIN_TIME_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DPAUX_HPD_CONFIG_PLUG_MIN_TIME_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DPAUX_HPD_IRQ_CONFIG_0 +#define DPAUX_HPD_IRQ_CONFIG_0 _MK_ADDR_CONST(0x41) +#define DPAUX_HPD_IRQ_CONFIG_0_SECURE 0x0 +#define DPAUX_HPD_IRQ_CONFIG_0_WORD_COUNT 0x1 +#define DPAUX_HPD_IRQ_CONFIG_0_RESET_VAL _MK_MASK_CONST(0xfa) +#define DPAUX_HPD_IRQ_CONFIG_0_RESET_MASK _MK_MASK_CONST(0xffff) +#define DPAUX_HPD_IRQ_CONFIG_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DPAUX_HPD_IRQ_CONFIG_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DPAUX_HPD_IRQ_CONFIG_0_READ_MASK _MK_MASK_CONST(0xffff) +#define DPAUX_HPD_IRQ_CONFIG_0_WRITE_MASK _MK_MASK_CONST(0xffff) +#define DPAUX_HPD_IRQ_CONFIG_0_MIN_LOW_TIME_SHIFT _MK_SHIFT_CONST(0) +#define DPAUX_HPD_IRQ_CONFIG_0_MIN_LOW_TIME_FIELD _MK_FIELD_CONST(0xffff, DPAUX_HPD_IRQ_CONFIG_0_MIN_LOW_TIME_SHIFT) +#define DPAUX_HPD_IRQ_CONFIG_0_MIN_LOW_TIME_RANGE 15:0 +#define DPAUX_HPD_IRQ_CONFIG_0_MIN_LOW_TIME_WOFFSET 0x0 +#define DPAUX_HPD_IRQ_CONFIG_0_MIN_LOW_TIME_DEFAULT _MK_MASK_CONST(0xfa) +#define DPAUX_HPD_IRQ_CONFIG_0_MIN_LOW_TIME_DEFAULT_MASK _MK_MASK_CONST(0xffff) +#define DPAUX_HPD_IRQ_CONFIG_0_MIN_LOW_TIME_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DPAUX_HPD_IRQ_CONFIG_0_MIN_LOW_TIME_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DPAUX_HPD_IRQ_CONFIG +#define DPAUX_HPD_IRQ_CONFIG _MK_ADDR_CONST(0x41) +#define DPAUX_HPD_IRQ_CONFIG_SECURE 0x0 +#define DPAUX_HPD_IRQ_CONFIG_WORD_COUNT 0x1 +#define DPAUX_HPD_IRQ_CONFIG_RESET_VAL _MK_MASK_CONST(0xfa) +#define DPAUX_HPD_IRQ_CONFIG_RESET_MASK _MK_MASK_CONST(0xffff) +#define DPAUX_HPD_IRQ_CONFIG_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DPAUX_HPD_IRQ_CONFIG_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DPAUX_HPD_IRQ_CONFIG_READ_MASK _MK_MASK_CONST(0xffff) +#define DPAUX_HPD_IRQ_CONFIG_WRITE_MASK _MK_MASK_CONST(0xffff) +#define DPAUX_HPD_IRQ_CONFIG_MIN_LOW_TIME_SHIFT _MK_SHIFT_CONST(0) +#define DPAUX_HPD_IRQ_CONFIG_MIN_LOW_TIME_FIELD _MK_FIELD_CONST(0xffff, DPAUX_HPD_IRQ_CONFIG_MIN_LOW_TIME_SHIFT) +#define DPAUX_HPD_IRQ_CONFIG_MIN_LOW_TIME_RANGE 15:0 +#define DPAUX_HPD_IRQ_CONFIG_MIN_LOW_TIME_WOFFSET 0x0 +#define DPAUX_HPD_IRQ_CONFIG_MIN_LOW_TIME_DEFAULT _MK_MASK_CONST(0xfa) +#define DPAUX_HPD_IRQ_CONFIG_MIN_LOW_TIME_DEFAULT_MASK _MK_MASK_CONST(0xffff) +#define DPAUX_HPD_IRQ_CONFIG_MIN_LOW_TIME_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DPAUX_HPD_IRQ_CONFIG_MIN_LOW_TIME_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DPAUX_DP_AUX_CONFIG_0 +#define DPAUX_DP_AUX_CONFIG_0 _MK_ADDR_CONST(0x45) +#define DPAUX_DP_AUX_CONFIG_0_SECURE 0x0 +#define DPAUX_DP_AUX_CONFIG_0_WORD_COUNT 0x1 +#define DPAUX_DP_AUX_CONFIG_0_RESET_VAL _MK_MASK_CONST(0x190) +#define DPAUX_DP_AUX_CONFIG_0_RESET_MASK _MK_MASK_CONST(0xffff) +#define DPAUX_DP_AUX_CONFIG_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUX_CONFIG_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUX_CONFIG_0_READ_MASK _MK_MASK_CONST(0xffff) +#define DPAUX_DP_AUX_CONFIG_0_WRITE_MASK _MK_MASK_CONST(0xffff) +#define DPAUX_DP_AUX_CONFIG_0_TIMEOUT_SHIFT _MK_SHIFT_CONST(0) +#define DPAUX_DP_AUX_CONFIG_0_TIMEOUT_FIELD _MK_FIELD_CONST(0xffff, DPAUX_DP_AUX_CONFIG_0_TIMEOUT_SHIFT) +#define DPAUX_DP_AUX_CONFIG_0_TIMEOUT_RANGE 15:0 +#define DPAUX_DP_AUX_CONFIG_0_TIMEOUT_WOFFSET 0x0 +#define DPAUX_DP_AUX_CONFIG_0_TIMEOUT_DEFAULT _MK_MASK_CONST(0x190) +#define DPAUX_DP_AUX_CONFIG_0_TIMEOUT_DEFAULT_MASK _MK_MASK_CONST(0xffff) +#define DPAUX_DP_AUX_CONFIG_0_TIMEOUT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUX_CONFIG_0_TIMEOUT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DPAUX_DP_AUX_CONFIG +#define DPAUX_DP_AUX_CONFIG _MK_ADDR_CONST(0x45) +#define DPAUX_DP_AUX_CONFIG_SECURE 0x0 +#define DPAUX_DP_AUX_CONFIG_WORD_COUNT 0x1 +#define DPAUX_DP_AUX_CONFIG_RESET_VAL _MK_MASK_CONST(0x190) +#define DPAUX_DP_AUX_CONFIG_RESET_MASK _MK_MASK_CONST(0xffff) +#define DPAUX_DP_AUX_CONFIG_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUX_CONFIG_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUX_CONFIG_READ_MASK _MK_MASK_CONST(0xffff) +#define DPAUX_DP_AUX_CONFIG_WRITE_MASK _MK_MASK_CONST(0xffff) +#define DPAUX_DP_AUX_CONFIG_TIMEOUT_SHIFT _MK_SHIFT_CONST(0) +#define DPAUX_DP_AUX_CONFIG_TIMEOUT_FIELD _MK_FIELD_CONST(0xffff, DPAUX_DP_AUX_CONFIG_TIMEOUT_SHIFT) +#define DPAUX_DP_AUX_CONFIG_TIMEOUT_RANGE 15:0 +#define DPAUX_DP_AUX_CONFIG_TIMEOUT_WOFFSET 0x0 +#define DPAUX_DP_AUX_CONFIG_TIMEOUT_DEFAULT _MK_MASK_CONST(0x190) +#define DPAUX_DP_AUX_CONFIG_TIMEOUT_DEFAULT_MASK _MK_MASK_CONST(0xffff) +#define DPAUX_DP_AUX_CONFIG_TIMEOUT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DPAUX_DP_AUX_CONFIG_TIMEOUT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DPAUX_HYBRID_PADCTL_0 +#define DPAUX_HYBRID_PADCTL_0 _MK_ADDR_CONST(0x49) +#define DPAUX_HYBRID_PADCTL_0_SECURE 0x0 +#define DPAUX_HYBRID_PADCTL_0_WORD_COUNT 0x1 +#define DPAUX_HYBRID_PADCTL_0_RESET_VAL _MK_MASK_CONST(0x2462) +#define DPAUX_HYBRID_PADCTL_0_RESET_MASK _MK_MASK_CONST(0xf7ff) +#define DPAUX_HYBRID_PADCTL_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DPAUX_HYBRID_PADCTL_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DPAUX_HYBRID_PADCTL_0_READ_MASK _MK_MASK_CONST(0xf7ff) +#define DPAUX_HYBRID_PADCTL_0_WRITE_MASK _MK_MASK_CONST(0xf7ff) +#define DPAUX_HYBRID_PADCTL_0_I2C_SDA_INPUT_RCV_SHIFT _MK_SHIFT_CONST(15) +#define DPAUX_HYBRID_PADCTL_0_I2C_SDA_INPUT_RCV_FIELD _MK_FIELD_CONST(0x1, DPAUX_HYBRID_PADCTL_0_I2C_SDA_INPUT_RCV_SHIFT) +#define DPAUX_HYBRID_PADCTL_0_I2C_SDA_INPUT_RCV_RANGE 15:15 +#define DPAUX_HYBRID_PADCTL_0_I2C_SDA_INPUT_RCV_WOFFSET 0x0 +#define DPAUX_HYBRID_PADCTL_0_I2C_SDA_INPUT_RCV_DEFAULT _MK_MASK_CONST(0x0) +#define DPAUX_HYBRID_PADCTL_0_I2C_SDA_INPUT_RCV_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DPAUX_HYBRID_PADCTL_0_I2C_SDA_INPUT_RCV_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DPAUX_HYBRID_PADCTL_0_I2C_SDA_INPUT_RCV_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DPAUX_HYBRID_PADCTL_0_I2C_SDA_INPUT_RCV_INIT_ENUM DISABLE +#define DPAUX_HYBRID_PADCTL_0_I2C_SDA_INPUT_RCV_DISABLE _MK_ENUM_CONST(0) +#define DPAUX_HYBRID_PADCTL_0_I2C_SDA_INPUT_RCV_ENABLE _MK_ENUM_CONST(1) + +#define DPAUX_HYBRID_PADCTL_0_I2C_SCL_INPUT_RCV_SHIFT _MK_SHIFT_CONST(14) +#define DPAUX_HYBRID_PADCTL_0_I2C_SCL_INPUT_RCV_FIELD _MK_FIELD_CONST(0x1, DPAUX_HYBRID_PADCTL_0_I2C_SCL_INPUT_RCV_SHIFT) +#define DPAUX_HYBRID_PADCTL_0_I2C_SCL_INPUT_RCV_RANGE 14:14 +#define DPAUX_HYBRID_PADCTL_0_I2C_SCL_INPUT_RCV_WOFFSET 0x0 +#define DPAUX_HYBRID_PADCTL_0_I2C_SCL_INPUT_RCV_DEFAULT _MK_MASK_CONST(0x0) +#define DPAUX_HYBRID_PADCTL_0_I2C_SCL_INPUT_RCV_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DPAUX_HYBRID_PADCTL_0_I2C_SCL_INPUT_RCV_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DPAUX_HYBRID_PADCTL_0_I2C_SCL_INPUT_RCV_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DPAUX_HYBRID_PADCTL_0_I2C_SCL_INPUT_RCV_INIT_ENUM DISABLE +#define DPAUX_HYBRID_PADCTL_0_I2C_SCL_INPUT_RCV_DISABLE _MK_ENUM_CONST(0) +#define DPAUX_HYBRID_PADCTL_0_I2C_SCL_INPUT_RCV_ENABLE _MK_ENUM_CONST(1) + +#define DPAUX_HYBRID_PADCTL_0_AUX_CMH_SHIFT _MK_SHIFT_CONST(12) +#define DPAUX_HYBRID_PADCTL_0_AUX_CMH_FIELD _MK_FIELD_CONST(0x3, DPAUX_HYBRID_PADCTL_0_AUX_CMH_SHIFT) +#define DPAUX_HYBRID_PADCTL_0_AUX_CMH_RANGE 13:12 +#define DPAUX_HYBRID_PADCTL_0_AUX_CMH_WOFFSET 0x0 +#define DPAUX_HYBRID_PADCTL_0_AUX_CMH_DEFAULT _MK_MASK_CONST(0x2) +#define DPAUX_HYBRID_PADCTL_0_AUX_CMH_DEFAULT_MASK _MK_MASK_CONST(0x3) +#define DPAUX_HYBRID_PADCTL_0_AUX_CMH_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DPAUX_HYBRID_PADCTL_0_AUX_CMH_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DPAUX_HYBRID_PADCTL_0_AUX_CMH_INIT_ENUM V0_70 +#define DPAUX_HYBRID_PADCTL_0_AUX_CMH_V0_60 _MK_ENUM_CONST(0) +#define DPAUX_HYBRID_PADCTL_0_AUX_CMH_V0_64 _MK_ENUM_CONST(1) +#define DPAUX_HYBRID_PADCTL_0_AUX_CMH_V0_70 _MK_ENUM_CONST(2) +#define DPAUX_HYBRID_PADCTL_0_AUX_CMH_V0_56 _MK_ENUM_CONST(3) + +#define DPAUX_HYBRID_PADCTL_0_AUX_DRVZ_SHIFT _MK_SHIFT_CONST(8) +#define DPAUX_HYBRID_PADCTL_0_AUX_DRVZ_FIELD _MK_FIELD_CONST(0x7, DPAUX_HYBRID_PADCTL_0_AUX_DRVZ_SHIFT) +#define DPAUX_HYBRID_PADCTL_0_AUX_DRVZ_RANGE 10:8 +#define DPAUX_HYBRID_PADCTL_0_AUX_DRVZ_WOFFSET 0x0 +#define DPAUX_HYBRID_PADCTL_0_AUX_DRVZ_DEFAULT _MK_MASK_CONST(0x4) +#define DPAUX_HYBRID_PADCTL_0_AUX_DRVZ_DEFAULT_MASK _MK_MASK_CONST(0x7) +#define DPAUX_HYBRID_PADCTL_0_AUX_DRVZ_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DPAUX_HYBRID_PADCTL_0_AUX_DRVZ_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DPAUX_HYBRID_PADCTL_0_AUX_DRVZ_INIT_ENUM OHM_50 +#define DPAUX_HYBRID_PADCTL_0_AUX_DRVZ_OHM_78 _MK_ENUM_CONST(0) +#define DPAUX_HYBRID_PADCTL_0_AUX_DRVZ_OHM_60 _MK_ENUM_CONST(1) +#define DPAUX_HYBRID_PADCTL_0_AUX_DRVZ_OHM_54 _MK_ENUM_CONST(2) +#define DPAUX_HYBRID_PADCTL_0_AUX_DRVZ_OHM_45 _MK_ENUM_CONST(3) +#define DPAUX_HYBRID_PADCTL_0_AUX_DRVZ_OHM_50 _MK_ENUM_CONST(4) +#define DPAUX_HYBRID_PADCTL_0_AUX_DRVZ_OHM_42 _MK_ENUM_CONST(5) +#define DPAUX_HYBRID_PADCTL_0_AUX_DRVZ_OHM_39 _MK_ENUM_CONST(6) +#define DPAUX_HYBRID_PADCTL_0_AUX_DRVZ_OHM_34 _MK_ENUM_CONST(7) + +#define DPAUX_HYBRID_PADCTL_0_AUX_DRVI_SHIFT _MK_SHIFT_CONST(2) +#define DPAUX_HYBRID_PADCTL_0_AUX_DRVI_FIELD _MK_FIELD_CONST(0x3f, DPAUX_HYBRID_PADCTL_0_AUX_DRVI_SHIFT) +#define DPAUX_HYBRID_PADCTL_0_AUX_DRVI_RANGE 7:2 +#define DPAUX_HYBRID_PADCTL_0_AUX_DRVI_WOFFSET 0x0 +#define DPAUX_HYBRID_PADCTL_0_AUX_DRVI_DEFAULT _MK_MASK_CONST(0x18) +#define DPAUX_HYBRID_PADCTL_0_AUX_DRVI_DEFAULT_MASK _MK_MASK_CONST(0x3f) +#define DPAUX_HYBRID_PADCTL_0_AUX_DRVI_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DPAUX_HYBRID_PADCTL_0_AUX_DRVI_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DPAUX_HYBRID_PADCTL_0_AUX_INPUT_RCV_SHIFT _MK_SHIFT_CONST(1) +#define DPAUX_HYBRID_PADCTL_0_AUX_INPUT_RCV_FIELD _MK_FIELD_CONST(0x1, DPAUX_HYBRID_PADCTL_0_AUX_INPUT_RCV_SHIFT) +#define DPAUX_HYBRID_PADCTL_0_AUX_INPUT_RCV_RANGE 1:1 +#define DPAUX_HYBRID_PADCTL_0_AUX_INPUT_RCV_WOFFSET 0x0 +#define DPAUX_HYBRID_PADCTL_0_AUX_INPUT_RCV_DEFAULT _MK_MASK_CONST(0x1) +#define DPAUX_HYBRID_PADCTL_0_AUX_INPUT_RCV_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DPAUX_HYBRID_PADCTL_0_AUX_INPUT_RCV_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DPAUX_HYBRID_PADCTL_0_AUX_INPUT_RCV_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DPAUX_HYBRID_PADCTL_0_AUX_INPUT_RCV_INIT_ENUM ENABLE +#define DPAUX_HYBRID_PADCTL_0_AUX_INPUT_RCV_DISABLE _MK_ENUM_CONST(0) +#define DPAUX_HYBRID_PADCTL_0_AUX_INPUT_RCV_ENABLE _MK_ENUM_CONST(1) + +#define DPAUX_HYBRID_PADCTL_0_MODE_SHIFT _MK_SHIFT_CONST(0) +#define DPAUX_HYBRID_PADCTL_0_MODE_FIELD _MK_FIELD_CONST(0x1, DPAUX_HYBRID_PADCTL_0_MODE_SHIFT) +#define DPAUX_HYBRID_PADCTL_0_MODE_RANGE 0:0 +#define DPAUX_HYBRID_PADCTL_0_MODE_WOFFSET 0x0 +#define DPAUX_HYBRID_PADCTL_0_MODE_DEFAULT _MK_MASK_CONST(0x0) +#define DPAUX_HYBRID_PADCTL_0_MODE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DPAUX_HYBRID_PADCTL_0_MODE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DPAUX_HYBRID_PADCTL_0_MODE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DPAUX_HYBRID_PADCTL_0_MODE_INIT_ENUM AUX +#define DPAUX_HYBRID_PADCTL_0_MODE_AUX _MK_ENUM_CONST(0) +#define DPAUX_HYBRID_PADCTL_0_MODE_I2C _MK_ENUM_CONST(1) + + +// Register DPAUX_HYBRID_PADCTL +#define DPAUX_HYBRID_PADCTL _MK_ADDR_CONST(0x49) +#define DPAUX_HYBRID_PADCTL_SECURE 0x0 +#define DPAUX_HYBRID_PADCTL_WORD_COUNT 0x1 +#define DPAUX_HYBRID_PADCTL_RESET_VAL _MK_MASK_CONST(0x2462) +#define DPAUX_HYBRID_PADCTL_RESET_MASK _MK_MASK_CONST(0xf7ff) +#define DPAUX_HYBRID_PADCTL_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DPAUX_HYBRID_PADCTL_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DPAUX_HYBRID_PADCTL_READ_MASK _MK_MASK_CONST(0xf7ff) +#define DPAUX_HYBRID_PADCTL_WRITE_MASK _MK_MASK_CONST(0xf7ff) +#define DPAUX_HYBRID_PADCTL_I2C_SDA_INPUT_RCV_SHIFT _MK_SHIFT_CONST(15) +#define DPAUX_HYBRID_PADCTL_I2C_SDA_INPUT_RCV_FIELD _MK_FIELD_CONST(0x1, DPAUX_HYBRID_PADCTL_I2C_SDA_INPUT_RCV_SHIFT) +#define DPAUX_HYBRID_PADCTL_I2C_SDA_INPUT_RCV_RANGE 15:15 +#define DPAUX_HYBRID_PADCTL_I2C_SDA_INPUT_RCV_WOFFSET 0x0 +#define DPAUX_HYBRID_PADCTL_I2C_SDA_INPUT_RCV_DEFAULT _MK_MASK_CONST(0x0) +#define DPAUX_HYBRID_PADCTL_I2C_SDA_INPUT_RCV_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DPAUX_HYBRID_PADCTL_I2C_SDA_INPUT_RCV_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DPAUX_HYBRID_PADCTL_I2C_SDA_INPUT_RCV_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DPAUX_HYBRID_PADCTL_I2C_SDA_INPUT_RCV_INIT_ENUM DISABLE +#define DPAUX_HYBRID_PADCTL_I2C_SDA_INPUT_RCV_DISABLE _MK_ENUM_CONST(0) +#define DPAUX_HYBRID_PADCTL_I2C_SDA_INPUT_RCV_ENABLE _MK_ENUM_CONST(1) + +#define DPAUX_HYBRID_PADCTL_I2C_SCL_INPUT_RCV_SHIFT _MK_SHIFT_CONST(14) +#define DPAUX_HYBRID_PADCTL_I2C_SCL_INPUT_RCV_FIELD _MK_FIELD_CONST(0x1, DPAUX_HYBRID_PADCTL_I2C_SCL_INPUT_RCV_SHIFT) +#define DPAUX_HYBRID_PADCTL_I2C_SCL_INPUT_RCV_RANGE 14:14 +#define DPAUX_HYBRID_PADCTL_I2C_SCL_INPUT_RCV_WOFFSET 0x0 +#define DPAUX_HYBRID_PADCTL_I2C_SCL_INPUT_RCV_DEFAULT _MK_MASK_CONST(0x0) +#define DPAUX_HYBRID_PADCTL_I2C_SCL_INPUT_RCV_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DPAUX_HYBRID_PADCTL_I2C_SCL_INPUT_RCV_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DPAUX_HYBRID_PADCTL_I2C_SCL_INPUT_RCV_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DPAUX_HYBRID_PADCTL_I2C_SCL_INPUT_RCV_INIT_ENUM DISABLE +#define DPAUX_HYBRID_PADCTL_I2C_SCL_INPUT_RCV_DISABLE _MK_ENUM_CONST(0) +#define DPAUX_HYBRID_PADCTL_I2C_SCL_INPUT_RCV_ENABLE _MK_ENUM_CONST(1) + +#define DPAUX_HYBRID_PADCTL_AUX_CMH_SHIFT _MK_SHIFT_CONST(12) +#define DPAUX_HYBRID_PADCTL_AUX_CMH_FIELD _MK_FIELD_CONST(0x3, DPAUX_HYBRID_PADCTL_AUX_CMH_SHIFT) +#define DPAUX_HYBRID_PADCTL_AUX_CMH_RANGE 13:12 +#define DPAUX_HYBRID_PADCTL_AUX_CMH_WOFFSET 0x0 +#define DPAUX_HYBRID_PADCTL_AUX_CMH_DEFAULT _MK_MASK_CONST(0x2) +#define DPAUX_HYBRID_PADCTL_AUX_CMH_DEFAULT_MASK _MK_MASK_CONST(0x3) +#define DPAUX_HYBRID_PADCTL_AUX_CMH_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DPAUX_HYBRID_PADCTL_AUX_CMH_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DPAUX_HYBRID_PADCTL_AUX_CMH_INIT_ENUM V0_70 +#define DPAUX_HYBRID_PADCTL_AUX_CMH_V0_60 _MK_ENUM_CONST(0) +#define DPAUX_HYBRID_PADCTL_AUX_CMH_V0_64 _MK_ENUM_CONST(1) +#define DPAUX_HYBRID_PADCTL_AUX_CMH_V0_70 _MK_ENUM_CONST(2) +#define DPAUX_HYBRID_PADCTL_AUX_CMH_V0_56 _MK_ENUM_CONST(3) + +#define DPAUX_HYBRID_PADCTL_AUX_DRVZ_SHIFT _MK_SHIFT_CONST(8) +#define DPAUX_HYBRID_PADCTL_AUX_DRVZ_FIELD _MK_FIELD_CONST(0x7, DPAUX_HYBRID_PADCTL_AUX_DRVZ_SHIFT) +#define DPAUX_HYBRID_PADCTL_AUX_DRVZ_RANGE 10:8 +#define DPAUX_HYBRID_PADCTL_AUX_DRVZ_WOFFSET 0x0 +#define DPAUX_HYBRID_PADCTL_AUX_DRVZ_DEFAULT _MK_MASK_CONST(0x4) +#define DPAUX_HYBRID_PADCTL_AUX_DRVZ_DEFAULT_MASK _MK_MASK_CONST(0x7) +#define DPAUX_HYBRID_PADCTL_AUX_DRVZ_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DPAUX_HYBRID_PADCTL_AUX_DRVZ_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DPAUX_HYBRID_PADCTL_AUX_DRVZ_INIT_ENUM OHM_50 +#define DPAUX_HYBRID_PADCTL_AUX_DRVZ_OHM_78 _MK_ENUM_CONST(0) +#define DPAUX_HYBRID_PADCTL_AUX_DRVZ_OHM_60 _MK_ENUM_CONST(1) +#define DPAUX_HYBRID_PADCTL_AUX_DRVZ_OHM_54 _MK_ENUM_CONST(2) +#define DPAUX_HYBRID_PADCTL_AUX_DRVZ_OHM_45 _MK_ENUM_CONST(3) +#define DPAUX_HYBRID_PADCTL_AUX_DRVZ_OHM_50 _MK_ENUM_CONST(4) +#define DPAUX_HYBRID_PADCTL_AUX_DRVZ_OHM_42 _MK_ENUM_CONST(5) +#define DPAUX_HYBRID_PADCTL_AUX_DRVZ_OHM_39 _MK_ENUM_CONST(6) +#define DPAUX_HYBRID_PADCTL_AUX_DRVZ_OHM_34 _MK_ENUM_CONST(7) + +#define DPAUX_HYBRID_PADCTL_AUX_DRVI_SHIFT _MK_SHIFT_CONST(2) +#define DPAUX_HYBRID_PADCTL_AUX_DRVI_FIELD _MK_FIELD_CONST(0x3f, DPAUX_HYBRID_PADCTL_AUX_DRVI_SHIFT) +#define DPAUX_HYBRID_PADCTL_AUX_DRVI_RANGE 7:2 +#define DPAUX_HYBRID_PADCTL_AUX_DRVI_WOFFSET 0x0 +#define DPAUX_HYBRID_PADCTL_AUX_DRVI_DEFAULT _MK_MASK_CONST(0x18) +#define DPAUX_HYBRID_PADCTL_AUX_DRVI_DEFAULT_MASK _MK_MASK_CONST(0x3f) +#define DPAUX_HYBRID_PADCTL_AUX_DRVI_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DPAUX_HYBRID_PADCTL_AUX_DRVI_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DPAUX_HYBRID_PADCTL_AUX_INPUT_RCV_SHIFT _MK_SHIFT_CONST(1) +#define DPAUX_HYBRID_PADCTL_AUX_INPUT_RCV_FIELD _MK_FIELD_CONST(0x1, DPAUX_HYBRID_PADCTL_AUX_INPUT_RCV_SHIFT) +#define DPAUX_HYBRID_PADCTL_AUX_INPUT_RCV_RANGE 1:1 +#define DPAUX_HYBRID_PADCTL_AUX_INPUT_RCV_WOFFSET 0x0 +#define DPAUX_HYBRID_PADCTL_AUX_INPUT_RCV_DEFAULT _MK_MASK_CONST(0x1) +#define DPAUX_HYBRID_PADCTL_AUX_INPUT_RCV_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DPAUX_HYBRID_PADCTL_AUX_INPUT_RCV_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DPAUX_HYBRID_PADCTL_AUX_INPUT_RCV_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DPAUX_HYBRID_PADCTL_AUX_INPUT_RCV_INIT_ENUM ENABLE +#define DPAUX_HYBRID_PADCTL_AUX_INPUT_RCV_DISABLE _MK_ENUM_CONST(0) +#define DPAUX_HYBRID_PADCTL_AUX_INPUT_RCV_ENABLE _MK_ENUM_CONST(1) + +#define DPAUX_HYBRID_PADCTL_MODE_SHIFT _MK_SHIFT_CONST(0) +#define DPAUX_HYBRID_PADCTL_MODE_FIELD _MK_FIELD_CONST(0x1, DPAUX_HYBRID_PADCTL_MODE_SHIFT) +#define DPAUX_HYBRID_PADCTL_MODE_RANGE 0:0 +#define DPAUX_HYBRID_PADCTL_MODE_WOFFSET 0x0 +#define DPAUX_HYBRID_PADCTL_MODE_DEFAULT _MK_MASK_CONST(0x0) +#define DPAUX_HYBRID_PADCTL_MODE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DPAUX_HYBRID_PADCTL_MODE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DPAUX_HYBRID_PADCTL_MODE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DPAUX_HYBRID_PADCTL_MODE_INIT_ENUM AUX +#define DPAUX_HYBRID_PADCTL_MODE_AUX _MK_ENUM_CONST(0) +#define DPAUX_HYBRID_PADCTL_MODE_I2C _MK_ENUM_CONST(1) + + +// Register DPAUX_HYBRID_SPARE_0 +#define DPAUX_HYBRID_SPARE_0 _MK_ADDR_CONST(0x4d) +#define DPAUX_HYBRID_SPARE_0_SECURE 0x0 +#define DPAUX_HYBRID_SPARE_0_WORD_COUNT 0x1 +#define DPAUX_HYBRID_SPARE_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DPAUX_HYBRID_SPARE_0_RESET_MASK _MK_MASK_CONST(0xffffffff) +#define DPAUX_HYBRID_SPARE_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DPAUX_HYBRID_SPARE_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DPAUX_HYBRID_SPARE_0_READ_MASK _MK_MASK_CONST(0xffffffff) +#define DPAUX_HYBRID_SPARE_0_WRITE_MASK _MK_MASK_CONST(0xffffffff) +#define DPAUX_HYBRID_SPARE_0_REG_SHIFT _MK_SHIFT_CONST(1) +#define DPAUX_HYBRID_SPARE_0_REG_FIELD _MK_FIELD_CONST(0x7fffffff, DPAUX_HYBRID_SPARE_0_REG_SHIFT) +#define DPAUX_HYBRID_SPARE_0_REG_RANGE 31:1 +#define DPAUX_HYBRID_SPARE_0_REG_WOFFSET 0x0 +#define DPAUX_HYBRID_SPARE_0_REG_DEFAULT _MK_MASK_CONST(0x0) +#define DPAUX_HYBRID_SPARE_0_REG_DEFAULT_MASK _MK_MASK_CONST(0x7fffffff) +#define DPAUX_HYBRID_SPARE_0_REG_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DPAUX_HYBRID_SPARE_0_REG_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DPAUX_HYBRID_SPARE_0_PAD_PWR_SHIFT _MK_SHIFT_CONST(0) +#define DPAUX_HYBRID_SPARE_0_PAD_PWR_FIELD _MK_FIELD_CONST(0x1, DPAUX_HYBRID_SPARE_0_PAD_PWR_SHIFT) +#define DPAUX_HYBRID_SPARE_0_PAD_PWR_RANGE 0:0 +#define DPAUX_HYBRID_SPARE_0_PAD_PWR_WOFFSET 0x0 +#define DPAUX_HYBRID_SPARE_0_PAD_PWR_DEFAULT _MK_MASK_CONST(0x0) +#define DPAUX_HYBRID_SPARE_0_PAD_PWR_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DPAUX_HYBRID_SPARE_0_PAD_PWR_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DPAUX_HYBRID_SPARE_0_PAD_PWR_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DPAUX_HYBRID_SPARE_0_PAD_PWR_INIT_ENUM POWERUP +#define DPAUX_HYBRID_SPARE_0_PAD_PWR_POWERUP _MK_ENUM_CONST(0) +#define DPAUX_HYBRID_SPARE_0_PAD_PWR_POWERDOWN _MK_ENUM_CONST(1) + + +// Register DPAUX_HYBRID_SPARE +#define DPAUX_HYBRID_SPARE _MK_ADDR_CONST(0x4d) +#define DPAUX_HYBRID_SPARE_SECURE 0x0 +#define DPAUX_HYBRID_SPARE_WORD_COUNT 0x1 +#define DPAUX_HYBRID_SPARE_RESET_VAL _MK_MASK_CONST(0x0) +#define DPAUX_HYBRID_SPARE_RESET_MASK _MK_MASK_CONST(0xffffffff) +#define DPAUX_HYBRID_SPARE_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DPAUX_HYBRID_SPARE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DPAUX_HYBRID_SPARE_READ_MASK _MK_MASK_CONST(0xffffffff) +#define DPAUX_HYBRID_SPARE_WRITE_MASK _MK_MASK_CONST(0xffffffff) +#define DPAUX_HYBRID_SPARE_REG_SHIFT _MK_SHIFT_CONST(1) +#define DPAUX_HYBRID_SPARE_REG_FIELD _MK_FIELD_CONST(0x7fffffff, DPAUX_HYBRID_SPARE_REG_SHIFT) +#define DPAUX_HYBRID_SPARE_REG_RANGE 31:1 +#define DPAUX_HYBRID_SPARE_REG_WOFFSET 0x0 +#define DPAUX_HYBRID_SPARE_REG_DEFAULT _MK_MASK_CONST(0x0) +#define DPAUX_HYBRID_SPARE_REG_DEFAULT_MASK _MK_MASK_CONST(0x7fffffff) +#define DPAUX_HYBRID_SPARE_REG_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DPAUX_HYBRID_SPARE_REG_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define DPAUX_HYBRID_SPARE_PAD_PWR_SHIFT _MK_SHIFT_CONST(0) +#define DPAUX_HYBRID_SPARE_PAD_PWR_FIELD _MK_FIELD_CONST(0x1, DPAUX_HYBRID_SPARE_PAD_PWR_SHIFT) +#define DPAUX_HYBRID_SPARE_PAD_PWR_RANGE 0:0 +#define DPAUX_HYBRID_SPARE_PAD_PWR_WOFFSET 0x0 +#define DPAUX_HYBRID_SPARE_PAD_PWR_DEFAULT _MK_MASK_CONST(0x0) +#define DPAUX_HYBRID_SPARE_PAD_PWR_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define DPAUX_HYBRID_SPARE_PAD_PWR_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DPAUX_HYBRID_SPARE_PAD_PWR_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DPAUX_HYBRID_SPARE_PAD_PWR_INIT_ENUM POWERUP +#define DPAUX_HYBRID_SPARE_PAD_PWR_POWERUP _MK_ENUM_CONST(0) +#define DPAUX_HYBRID_SPARE_PAD_PWR_POWERDOWN _MK_ENUM_CONST(1) + + +// Register DPAUX_SCRATCH_REG0_0 +#define DPAUX_SCRATCH_REG0_0 _MK_ADDR_CONST(0x51) +#define DPAUX_SCRATCH_REG0_0_SECURE 0x0 +#define DPAUX_SCRATCH_REG0_0_WORD_COUNT 0x1 +#define DPAUX_SCRATCH_REG0_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DPAUX_SCRATCH_REG0_0_RESET_MASK _MK_MASK_CONST(0xffffffff) +#define DPAUX_SCRATCH_REG0_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DPAUX_SCRATCH_REG0_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DPAUX_SCRATCH_REG0_0_READ_MASK _MK_MASK_CONST(0xffffffff) +#define DPAUX_SCRATCH_REG0_0_WRITE_MASK _MK_MASK_CONST(0xffffffff) +#define DPAUX_SCRATCH_REG0_0_REG_SHIFT _MK_SHIFT_CONST(0) +#define DPAUX_SCRATCH_REG0_0_REG_FIELD _MK_FIELD_CONST(0xffffffff, DPAUX_SCRATCH_REG0_0_REG_SHIFT) +#define DPAUX_SCRATCH_REG0_0_REG_RANGE 31:0 +#define DPAUX_SCRATCH_REG0_0_REG_WOFFSET 0x0 +#define DPAUX_SCRATCH_REG0_0_REG_DEFAULT _MK_MASK_CONST(0x0) +#define DPAUX_SCRATCH_REG0_0_REG_DEFAULT_MASK _MK_MASK_CONST(0xffffffff) +#define DPAUX_SCRATCH_REG0_0_REG_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DPAUX_SCRATCH_REG0_0_REG_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DPAUX_SCRATCH_REG0_0_REG_IDLE _MK_ENUM_CONST(0) +#define DPAUX_SCRATCH_REG0_0_REG_CLEAR_AUTO_RESP _MK_ENUM_CONST(1) +#define DPAUX_SCRATCH_REG0_0_REG_CLEAR_WR_DEFER _MK_ENUM_CONST(2) +#define DPAUX_SCRATCH_REG0_0_REG_CLEAR_WR_NAK _MK_ENUM_CONST(3) +#define DPAUX_SCRATCH_REG0_0_REG_CLEAR_WR_PARTIAL _MK_ENUM_CONST(4) +#define DPAUX_SCRATCH_REG0_0_REG_CLEAR_RD_DEFER _MK_ENUM_CONST(5) +#define DPAUX_SCRATCH_REG0_0_REG_CLEAR_RD_NAK _MK_ENUM_CONST(6) +#define DPAUX_SCRATCH_REG0_0_REG_CLEAR_RD_PARTIAL _MK_ENUM_CONST(7) +#define DPAUX_SCRATCH_REG0_0_REG_SET_AUTO_RESP _MK_ENUM_CONST(8) +#define DPAUX_SCRATCH_REG0_0_REG_SET_WR_DEFER _MK_ENUM_CONST(9) +#define DPAUX_SCRATCH_REG0_0_REG_SET_WR_NAK _MK_ENUM_CONST(10) +#define DPAUX_SCRATCH_REG0_0_REG_SET_WR_PARTIAL _MK_ENUM_CONST(11) +#define DPAUX_SCRATCH_REG0_0_REG_WR_DATA0 _MK_ENUM_CONST(12) +#define DPAUX_SCRATCH_REG0_0_REG_WR_DATA1 _MK_ENUM_CONST(13) +#define DPAUX_SCRATCH_REG0_0_REG_WR_DATA2 _MK_ENUM_CONST(14) +#define DPAUX_SCRATCH_REG0_0_REG_WR_DATA3 _MK_ENUM_CONST(15) +#define DPAUX_SCRATCH_REG0_0_REG_WR_DATA4 _MK_ENUM_CONST(16) +#define DPAUX_SCRATCH_REG0_0_REG_WR_DATA5 _MK_ENUM_CONST(17) +#define DPAUX_SCRATCH_REG0_0_REG_WR_DATA6 _MK_ENUM_CONST(18) +#define DPAUX_SCRATCH_REG0_0_REG_WR_DATA7 _MK_ENUM_CONST(19) +#define DPAUX_SCRATCH_REG0_0_REG_WR_DATA8 _MK_ENUM_CONST(20) +#define DPAUX_SCRATCH_REG0_0_REG_WR_DATA9 _MK_ENUM_CONST(21) +#define DPAUX_SCRATCH_REG0_0_REG_WR_DATA10 _MK_ENUM_CONST(22) +#define DPAUX_SCRATCH_REG0_0_REG_WR_DATA11 _MK_ENUM_CONST(23) +#define DPAUX_SCRATCH_REG0_0_REG_WR_DATA12 _MK_ENUM_CONST(24) +#define DPAUX_SCRATCH_REG0_0_REG_WR_DATA13 _MK_ENUM_CONST(25) +#define DPAUX_SCRATCH_REG0_0_REG_WR_DATA14 _MK_ENUM_CONST(26) +#define DPAUX_SCRATCH_REG0_0_REG_WR_DATA15 _MK_ENUM_CONST(27) +#define DPAUX_SCRATCH_REG0_0_REG_SET_RD_DEFER _MK_ENUM_CONST(28) +#define DPAUX_SCRATCH_REG0_0_REG_SET_RD_NAK _MK_ENUM_CONST(29) +#define DPAUX_SCRATCH_REG0_0_REG_SET_RD_PARTIAL _MK_ENUM_CONST(30) +#define DPAUX_SCRATCH_REG0_0_REG_RD_RESP_DATA0 _MK_ENUM_CONST(31) +#define DPAUX_SCRATCH_REG0_0_REG_RD_RESP_DATA1 _MK_ENUM_CONST(32) +#define DPAUX_SCRATCH_REG0_0_REG_RD_RESP_DATA2 _MK_ENUM_CONST(33) +#define DPAUX_SCRATCH_REG0_0_REG_RD_RESP_DATA3 _MK_ENUM_CONST(34) +#define DPAUX_SCRATCH_REG0_0_REG_RD_RESP_DATA4 _MK_ENUM_CONST(35) +#define DPAUX_SCRATCH_REG0_0_REG_RD_RESP_DATA5 _MK_ENUM_CONST(36) +#define DPAUX_SCRATCH_REG0_0_REG_RD_RESP_DATA6 _MK_ENUM_CONST(37) +#define DPAUX_SCRATCH_REG0_0_REG_RD_RESP_DATA7 _MK_ENUM_CONST(38) +#define DPAUX_SCRATCH_REG0_0_REG_RD_RESP_DATA8 _MK_ENUM_CONST(39) +#define DPAUX_SCRATCH_REG0_0_REG_RD_RESP_DATA9 _MK_ENUM_CONST(40) +#define DPAUX_SCRATCH_REG0_0_REG_RD_RESP_DATA10 _MK_ENUM_CONST(41) +#define DPAUX_SCRATCH_REG0_0_REG_RD_RESP_DATA11 _MK_ENUM_CONST(42) +#define DPAUX_SCRATCH_REG0_0_REG_RD_RESP_DATA12 _MK_ENUM_CONST(43) +#define DPAUX_SCRATCH_REG0_0_REG_RD_RESP_DATA13 _MK_ENUM_CONST(44) +#define DPAUX_SCRATCH_REG0_0_REG_RD_RESP_DATA14 _MK_ENUM_CONST(45) +#define DPAUX_SCRATCH_REG0_0_REG_RD_RESP_DATA15 _MK_ENUM_CONST(46) +#define DPAUX_SCRATCH_REG0_0_REG_RX_CMD _MK_ENUM_CONST(47) +#define DPAUX_SCRATCH_REG0_0_REG_RX_ADDR _MK_ENUM_CONST(48) +#define DPAUX_SCRATCH_REG0_0_REG_RX_DATA_CNT _MK_ENUM_CONST(49) +#define DPAUX_SCRATCH_REG0_0_REG_SET_RX_EXECUTE _MK_ENUM_CONST(50) +#define DPAUX_SCRATCH_REG0_0_REG_CLEAR_RX_EXECUTE _MK_ENUM_CONST(51) +#define DPAUX_SCRATCH_REG0_0_REG_SET_HPD_START _MK_ENUM_CONST(52) +#define DPAUX_SCRATCH_REG0_0_REG_CLEAR_HPD_START _MK_ENUM_CONST(53) +#define DPAUX_SCRATCH_REG0_0_REG_HPD_INIT_VALUE _MK_ENUM_CONST(54) +#define DPAUX_SCRATCH_REG0_0_REG_HPD_END_VALUE _MK_ENUM_CONST(55) +#define DPAUX_SCRATCH_REG0_0_REG_HPD_PULSE_WIDTH _MK_ENUM_CONST(56) +#define DPAUX_SCRATCH_REG0_0_REG_HPD_DISABLE _MK_ENUM_CONST(57) +#define DPAUX_SCRATCH_REG0_0_REG_RELEASE_ALL _MK_ENUM_CONST(58) +#define DPAUX_SCRATCH_REG0_0_REG_START_TIMER _MK_ENUM_CONST(59) +#define DPAUX_SCRATCH_REG0_0_REG_END_TIMER _MK_ENUM_CONST(60) +#define DPAUX_SCRATCH_REG0_0_REG_IF_REG_TEST _MK_ENUM_CONST(61) +#define DPAUX_SCRATCH_REG0_0_REG_SET_RESPONSE_TIMER _MK_ENUM_CONST(62) +#define DPAUX_SCRATCH_REG0_0_REG_RELEASE_RESPONSE_TIMER _MK_ENUM_CONST(63) +#define DPAUX_SCRATCH_REG0_0_REG_SET_RESPONSE_FAULTY _MK_ENUM_CONST(64) +#define DPAUX_SCRATCH_REG0_0_REG_CLEAR_RESPONSE_FAULTY _MK_ENUM_CONST(65) +#define DPAUX_SCRATCH_REG0_0_REG_START_WAIT_TIMER _MK_ENUM_CONST(66) +#define DPAUX_SCRATCH_REG0_0_REG_CLEAR_WAIT_TIMER _MK_ENUM_CONST(67) +#define DPAUX_SCRATCH_REG0_0_REG_SET_IGNORE_AUX_IN _MK_ENUM_CONST(68) +#define DPAUX_SCRATCH_REG0_0_REG_CLEAR_IGNORE_AUX_IN _MK_ENUM_CONST(69) +#define DPAUX_SCRATCH_REG0_0_REG_SET_AUX_IF_TIMER_RESET _MK_ENUM_CONST(70) +#define DPAUX_SCRATCH_REG0_0_REG_CLEAR_AUX_IF_TIMER_RESET _MK_ENUM_CONST(71) +#define DPAUX_SCRATCH_REG0_0_REG_SET_RD_PARTIAL_DATA_COUNT _MK_ENUM_CONST(72) +#define DPAUX_SCRATCH_REG0_0_REG_CLEAR_RD_PARTIAL_DATA_COUNT _MK_ENUM_CONST(73) +#define DPAUX_SCRATCH_REG0_0_REG_SET_WR_PARTIAL_DATA_COUNT _MK_ENUM_CONST(74) +#define DPAUX_SCRATCH_REG0_0_REG_CLEAR_WR_PARTIAL_DATA_COUNT _MK_ENUM_CONST(75) +#define DPAUX_SCRATCH_REG0_0_REG_WR_EXPECTED_MVID _MK_ENUM_CONST(76) +#define DPAUX_SCRATCH_REG0_0_REG_RD_MVID_CHECK _MK_ENUM_CONST(77) +#define DPAUX_SCRATCH_REG0_0_REG_RD_ATTACHED _MK_ENUM_CONST(78) +#define DPAUX_SCRATCH_REG0_0_REG_SET_PWM_START_MON _MK_ENUM_CONST(79) +#define DPAUX_SCRATCH_REG0_0_REG_CLEAR_PWM_START_MON _MK_ENUM_CONST(80) +#define DPAUX_SCRATCH_REG0_0_REG_READ_XTALCLK_COUNT _MK_ENUM_CONST(81) +#define DPAUX_SCRATCH_REG0_0_REG_READ_PCLK0_COUNT _MK_ENUM_CONST(82) +#define DPAUX_SCRATCH_REG0_0_REG_READ_PCLK1_COUNT _MK_ENUM_CONST(83) +#define DPAUX_SCRATCH_REG0_0_REG_READ_PCLK2_COUNT _MK_ENUM_CONST(84) +#define DPAUX_SCRATCH_REG0_0_REG_READ_MONITOR_FAILED _MK_ENUM_CONST(85) +#define DPAUX_SCRATCH_REG0_0_REG_SET_CLK_REC_PATTERN_CHK_DISABLED _MK_ENUM_CONST(86) +#define DPAUX_SCRATCH_REG0_0_REG_SET_FORCE_RESET _MK_ENUM_CONST(87) +#define DPAUX_SCRATCH_REG0_0_REG_SET_TARGET_CR_DRIVE_CURRENT _MK_ENUM_CONST(88) +#define DPAUX_SCRATCH_REG0_0_REG_SET_TARGET_EQ_PRE_EMPHASIS _MK_ENUM_CONST(89) +#define DPAUX_SCRATCH_REG0_0_REG_SET_TARGET_CR_BW _MK_ENUM_CONST(90) +#define DPAUX_SCRATCH_REG0_0_REG_SET_CR_UPDATE_US _MK_ENUM_CONST(91) +#define DPAUX_SCRATCH_REG0_0_REG_CLEAR_CLK_REC_PATTERN_CHK_DISABLED _MK_ENUM_CONST(92) +#define DPAUX_SCRATCH_REG0_0_REG_CLEAR_FORCE_RESET _MK_ENUM_CONST(93) +#define DPAUX_SCRATCH_REG0_0_REG_CLEAR_TARGET_CR_DRIVE_CURRENT _MK_ENUM_CONST(94) +#define DPAUX_SCRATCH_REG0_0_REG_CLEAR_TARGET_CR_BW _MK_ENUM_CONST(95) +#define DPAUX_SCRATCH_REG0_0_REG_CLEAR_CR_UPDATE_US _MK_ENUM_CONST(96) +#define DPAUX_SCRATCH_REG0_0_REG_SET_EQ_UPDATE_US _MK_ENUM_CONST(97) +#define DPAUX_SCRATCH_REG0_0_REG_SET_EQ_PATTERN_CHK_DISABLED _MK_ENUM_CONST(98) +#define DPAUX_SCRATCH_REG0_0_REG_CLEAR_EQ_PATTERN_CHK_DISABLED _MK_ENUM_CONST(99) +#define DPAUX_SCRATCH_REG0_0_REG_RD_AUX_BFM_TIMER _MK_ENUM_CONST(100) +#define DPAUX_SCRATCH_REG0_0_REG_RD_PATTERN_RCVD_STATUS _MK_ENUM_CONST(101) +#define DPAUX_SCRATCH_REG0_0_REG_CLEAR_LANE_PATTERN _MK_ENUM_CONST(102) +#define DPAUX_SCRATCH_REG0_0_REG_ENABLE_LANE_SEQ_MON _MK_ENUM_CONST(103) +#define DPAUX_SCRATCH_REG0_0_REG_DISABLE_LANE_SEQ_MON _MK_ENUM_CONST(104) +#define DPAUX_SCRATCH_REG0_0_REG_READ_PDTXD _MK_ENUM_CONST(105) +#define DPAUX_SCRATCH_REG0_0_REG_PWM_MON_CTL _MK_ENUM_CONST(106) +#define DPAUX_SCRATCH_REG0_0_REG_READ_PWM_COUNTER _MK_ENUM_CONST(107) +#define DPAUX_SCRATCH_REG0_0_REG_READ_PWM_STATUS _MK_ENUM_CONST(108) + + +// Register DPAUX_SCRATCH_REG1_0 +#define DPAUX_SCRATCH_REG1_0 _MK_ADDR_CONST(0x55) +#define DPAUX_SCRATCH_REG1_0_SECURE 0x0 +#define DPAUX_SCRATCH_REG1_0_WORD_COUNT 0x1 +#define DPAUX_SCRATCH_REG1_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DPAUX_SCRATCH_REG1_0_RESET_MASK _MK_MASK_CONST(0xffffffff) +#define DPAUX_SCRATCH_REG1_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DPAUX_SCRATCH_REG1_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DPAUX_SCRATCH_REG1_0_READ_MASK _MK_MASK_CONST(0xffffffff) +#define DPAUX_SCRATCH_REG1_0_WRITE_MASK _MK_MASK_CONST(0xffffffff) +#define DPAUX_SCRATCH_REG1_0_REG_SHIFT _MK_SHIFT_CONST(0) +#define DPAUX_SCRATCH_REG1_0_REG_FIELD _MK_FIELD_CONST(0xffffffff, DPAUX_SCRATCH_REG1_0_REG_SHIFT) +#define DPAUX_SCRATCH_REG1_0_REG_RANGE 31:0 +#define DPAUX_SCRATCH_REG1_0_REG_WOFFSET 0x0 +#define DPAUX_SCRATCH_REG1_0_REG_DEFAULT _MK_MASK_CONST(0x0) +#define DPAUX_SCRATCH_REG1_0_REG_DEFAULT_MASK _MK_MASK_CONST(0xffffffff) +#define DPAUX_SCRATCH_REG1_0_REG_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DPAUX_SCRATCH_REG1_0_REG_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register DPAUX_SCRATCH_REG2_0 +#define DPAUX_SCRATCH_REG2_0 _MK_ADDR_CONST(0x59) +#define DPAUX_SCRATCH_REG2_0_SECURE 0x0 +#define DPAUX_SCRATCH_REG2_0_WORD_COUNT 0x1 +#define DPAUX_SCRATCH_REG2_0_RESET_VAL _MK_MASK_CONST(0x0) +#define DPAUX_SCRATCH_REG2_0_RESET_MASK _MK_MASK_CONST(0xffffffff) +#define DPAUX_SCRATCH_REG2_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define DPAUX_SCRATCH_REG2_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DPAUX_SCRATCH_REG2_0_READ_MASK _MK_MASK_CONST(0xffffffff) +#define DPAUX_SCRATCH_REG2_0_WRITE_MASK _MK_MASK_CONST(0xffffffff) +#define DPAUX_SCRATCH_REG2_0_REG_SHIFT _MK_SHIFT_CONST(0) +#define DPAUX_SCRATCH_REG2_0_REG_FIELD _MK_FIELD_CONST(0xffffffff, DPAUX_SCRATCH_REG2_0_REG_SHIFT) +#define DPAUX_SCRATCH_REG2_0_REG_RANGE 31:0 +#define DPAUX_SCRATCH_REG2_0_REG_WOFFSET 0x0 +#define DPAUX_SCRATCH_REG2_0_REG_DEFAULT _MK_MASK_CONST(0x0) +#define DPAUX_SCRATCH_REG2_0_REG_DEFAULT_MASK _MK_MASK_CONST(0xffffffff) +#define DPAUX_SCRATCH_REG2_0_REG_SW_DEFAULT _MK_MASK_CONST(0x0) +#define DPAUX_SCRATCH_REG2_0_REG_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define DPAUX_SCRATCH_REG2_0_REG_IDLE _MK_ENUM_CONST(0) +#define DPAUX_SCRATCH_REG2_0_REG_DONE _MK_ENUM_CONST(1) + + +// +// REGISTER LIST +// +#define LIST_ARDPAUX_REGS(_op_) \ +_op_(DPAUX_CTXSW_0) \ +_op_(DPAUX_INTR_EN_AUX_0) \ +_op_(DPAUX_INTR_EN_AUX) \ +_op_(DPAUX_INTR_AUX_0) \ +_op_(DPAUX_INTR_AUX) \ +_op_(DPAUX_DP_AUXDATA_WRITE_W0_0) \ +_op_(DPAUX_DP_AUXDATA_WRITE_W0) \ +_op_(DPAUX_DP_AUXDATA_WRITE_W1_0) \ +_op_(DPAUX_DP_AUXDATA_WRITE_W1) \ +_op_(DPAUX_DP_AUXDATA_WRITE_W2_0) \ +_op_(DPAUX_DP_AUXDATA_WRITE_W2) \ +_op_(DPAUX_DP_AUXDATA_WRITE_W3_0) \ +_op_(DPAUX_DP_AUXDATA_WRITE_W3) \ +_op_(DPAUX_DP_AUXDATA_READ_W0_0) \ +_op_(DPAUX_DP_AUXDATA_READ_W0) \ +_op_(DPAUX_DP_AUXDATA_READ_W1_0) \ +_op_(DPAUX_DP_AUXDATA_READ_W1) \ +_op_(DPAUX_DP_AUXDATA_READ_W2_0) \ +_op_(DPAUX_DP_AUXDATA_READ_W2) \ +_op_(DPAUX_DP_AUXDATA_READ_W3_0) \ +_op_(DPAUX_DP_AUXDATA_READ_W3) \ +_op_(DPAUX_DP_AUXADDR_0) \ +_op_(DPAUX_DP_AUXADDR) \ +_op_(DPAUX_DP_AUXCTL_0) \ +_op_(DPAUX_DP_AUXCTL) \ +_op_(DPAUX_DP_AUXSTAT_0) \ +_op_(DPAUX_DP_AUXSTAT) \ +_op_(DPAUX_DP_AUX_SINKSTATLO_0) \ +_op_(DPAUX_DP_AUX_SINKSTATLO) \ +_op_(DPAUX_DP_AUX_SINKSTATHI_0) \ +_op_(DPAUX_DP_AUX_SINKSTATHI) \ +_op_(DPAUX_HPD_CONFIG_0) \ +_op_(DPAUX_HPD_CONFIG) \ +_op_(DPAUX_HPD_IRQ_CONFIG_0) \ +_op_(DPAUX_HPD_IRQ_CONFIG) \ +_op_(DPAUX_DP_AUX_CONFIG_0) \ +_op_(DPAUX_DP_AUX_CONFIG) \ +_op_(DPAUX_HYBRID_PADCTL_0) \ +_op_(DPAUX_HYBRID_PADCTL) \ +_op_(DPAUX_HYBRID_SPARE_0) \ +_op_(DPAUX_HYBRID_SPARE) \ +_op_(DPAUX_SCRATCH_REG0_0) \ +_op_(DPAUX_SCRATCH_REG1_0) \ +_op_(DPAUX_SCRATCH_REG2_0) + + +// +// ADDRESS SPACES +// + +#define BASE_ADDRESS_DPAUX 0x00000000 + +// +// ARDPAUX REGISTER BANKS +// + +#define DPAUX0_FIRST_REG 0x0000 // DPAUX_CTXSW_0 +#define DPAUX0_LAST_REG 0x0059 // DPAUX_SCRATCH_REG2_0 + +// To satisfy various compilers and platforms, +// we let users control the types and syntax of certain constants, using macros. +#ifndef _MK_SHIFT_CONST + #define _MK_SHIFT_CONST(_constant_) _constant_ +#endif +#ifndef _MK_MASK_CONST + #define _MK_MASK_CONST(_constant_) _constant_ +#endif +#ifndef _MK_ENUM_CONST + #define _MK_ENUM_CONST(_constant_) (_constant_ ## UL) +#endif +#ifndef _MK_ADDR_CONST + #define _MK_ADDR_CONST(_constant_) _constant_ +#endif +#ifndef _MK_FIELD_CONST + #define _MK_FIELD_CONST(_mask_, _shift_) (_MK_MASK_CONST(_mask_) << _MK_SHIFT_CONST(_shift_)) +#endif + +#endif // ifndef ___ARDPAUX_H_INC_ diff --git a/src/soc/nvidia/tegra124/include/soc/arsor.h b/src/soc/nvidia/tegra124/include/soc/arsor.h new file mode 100644 index 0000000..ae2a626 --- /dev/null +++ b/src/soc/nvidia/tegra124/include/soc/arsor.h @@ -0,0 +1,10227 @@ +// +// Copyright (c) 2013 NVIDIA Corporation. +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright notice, +// this list of conditions and the following disclaimer in the documentation +// and/or other materials provided with the distribution. +// +// Neither the name of the NVIDIA Corporation nor the names of its contributors +// may be used to endorse or promote products derived from this software +// without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// + +// +// DO NOT EDIT - generated by simspec! +// + +#ifndef ___ARSOR_H_INC_ +#define ___ARSOR_H_INC_ + +// Packet DISPLAY2SOR +#define DISPLAY2SOR_SIZE 39 + +#define DISPLAY2SOR_R_DATA_SHIFT _MK_SHIFT_CONST(0) +#define DISPLAY2SOR_R_DATA_FIELD _MK_FIELD_CONST(0x3ff, DISPLAY2SOR_R_DATA_SHIFT) +#define DISPLAY2SOR_R_DATA_RANGE _MK_SHIFT_CONST(9):_MK_SHIFT_CONST(0) +#define DISPLAY2SOR_R_DATA_ROW 0 + +#define DISPLAY2SOR_G_DATA_SHIFT _MK_SHIFT_CONST(10) +#define DISPLAY2SOR_G_DATA_FIELD _MK_FIELD_CONST(0x3ff, DISPLAY2SOR_G_DATA_SHIFT) +#define DISPLAY2SOR_G_DATA_RANGE _MK_SHIFT_CONST(19):_MK_SHIFT_CONST(10) +#define DISPLAY2SOR_G_DATA_ROW 0 + +#define DISPLAY2SOR_B_DATA_SHIFT _MK_SHIFT_CONST(20) +#define DISPLAY2SOR_B_DATA_FIELD _MK_FIELD_CONST(0x3ff, DISPLAY2SOR_B_DATA_SHIFT) +#define DISPLAY2SOR_B_DATA_RANGE _MK_SHIFT_CONST(29):_MK_SHIFT_CONST(20) +#define DISPLAY2SOR_B_DATA_ROW 0 + +#define DISPLAY2SOR_HBLANK_SHIFT _MK_SHIFT_CONST(30) +#define DISPLAY2SOR_HBLANK_FIELD _MK_FIELD_CONST(0x1, DISPLAY2SOR_HBLANK_SHIFT) +#define DISPLAY2SOR_HBLANK_RANGE _MK_SHIFT_CONST(30):_MK_SHIFT_CONST(30) +#define DISPLAY2SOR_HBLANK_ROW 0 + +#define DISPLAY2SOR_VBLANK_SHIFT _MK_SHIFT_CONST(31) +#define DISPLAY2SOR_VBLANK_FIELD _MK_FIELD_CONST(0x1, DISPLAY2SOR_VBLANK_SHIFT) +#define DISPLAY2SOR_VBLANK_RANGE _MK_SHIFT_CONST(31):_MK_SHIFT_CONST(31) +#define DISPLAY2SOR_VBLANK_ROW 0 + +#define DISPLAY2SOR_HSYNC_SHIFT _MK_SHIFT_CONST(32) +#define DISPLAY2SOR_HSYNC_FIELD _MK_FIELD_CONST(0x1, DISPLAY2SOR_HSYNC_SHIFT) +#define DISPLAY2SOR_HSYNC_RANGE _MK_SHIFT_CONST(32):_MK_SHIFT_CONST(32) +#define DISPLAY2SOR_HSYNC_ROW 0 + +#define DISPLAY2SOR_VSYNC_SHIFT _MK_SHIFT_CONST(33) +#define DISPLAY2SOR_VSYNC_FIELD _MK_FIELD_CONST(0x1, DISPLAY2SOR_VSYNC_SHIFT) +#define DISPLAY2SOR_VSYNC_RANGE _MK_SHIFT_CONST(33):_MK_SHIFT_CONST(33) +#define DISPLAY2SOR_VSYNC_ROW 0 + +#define DISPLAY2SOR_LOADV_SHIFT _MK_SHIFT_CONST(34) +#define DISPLAY2SOR_LOADV_FIELD _MK_FIELD_CONST(0x1, DISPLAY2SOR_LOADV_SHIFT) +#define DISPLAY2SOR_LOADV_RANGE _MK_SHIFT_CONST(34):_MK_SHIFT_CONST(34) +#define DISPLAY2SOR_LOADV_ROW 0 + +#define DISPLAY2SOR_CRC_SHIFT _MK_SHIFT_CONST(35) +#define DISPLAY2SOR_CRC_FIELD _MK_FIELD_CONST(0x1, DISPLAY2SOR_CRC_SHIFT) +#define DISPLAY2SOR_CRC_RANGE _MK_SHIFT_CONST(35):_MK_SHIFT_CONST(35) +#define DISPLAY2SOR_CRC_ROW 0 + +#define DISPLAY2SOR_CSPC_SHIFT _MK_SHIFT_CONST(36) +#define DISPLAY2SOR_CSPC_FIELD _MK_FIELD_CONST(0x1, DISPLAY2SOR_CSPC_SHIFT) +#define DISPLAY2SOR_CSPC_RANGE _MK_SHIFT_CONST(36):_MK_SHIFT_CONST(36) +#define DISPLAY2SOR_CSPC_ROW 0 + +#define DISPLAY2SOR_CTL_SHIFT _MK_SHIFT_CONST(37) +#define DISPLAY2SOR_CTL_FIELD _MK_FIELD_CONST(0x1, DISPLAY2SOR_CTL_SHIFT) +#define DISPLAY2SOR_CTL_RANGE _MK_SHIFT_CONST(37):_MK_SHIFT_CONST(37) +#define DISPLAY2SOR_CTL_ROW 0 + +#define DISPLAY2SOR_VIDEO_PREAMBLE_SHIFT _MK_SHIFT_CONST(38) +#define DISPLAY2SOR_VIDEO_PREAMBLE_FIELD _MK_FIELD_CONST(0x1, DISPLAY2SOR_VIDEO_PREAMBLE_SHIFT) +#define DISPLAY2SOR_VIDEO_PREAMBLE_RANGE _MK_SHIFT_CONST(38):_MK_SHIFT_CONST(38) +#define DISPLAY2SOR_VIDEO_PREAMBLE_ROW 0 + + +// Register SOR_CTXSW_0 +#define SOR_CTXSW_0 _MK_ADDR_CONST(0x0) +#define SOR_CTXSW_0_SECURE 0x0 +#define SOR_CTXSW_0_WORD_COUNT 0x1 +#define SOR_CTXSW_0_RESET_VAL _MK_MASK_CONST(0xf000f800) +#define SOR_CTXSW_0_RESET_MASK _MK_MASK_CONST(0xf3fffbff) +#define SOR_CTXSW_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define SOR_CTXSW_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_CTXSW_0_READ_MASK _MK_MASK_CONST(0xf3fffbff) +#define SOR_CTXSW_0_WRITE_MASK _MK_MASK_CONST(0xfbff) +#define SOR_CTXSW_0_CURR_CLASS_SHIFT _MK_SHIFT_CONST(0) +#define SOR_CTXSW_0_CURR_CLASS_FIELD _MK_FIELD_CONST(0x3ff, SOR_CTXSW_0_CURR_CLASS_SHIFT) +#define SOR_CTXSW_0_CURR_CLASS_RANGE 9:0 +#define SOR_CTXSW_0_CURR_CLASS_WOFFSET 0x0 +#define SOR_CTXSW_0_CURR_CLASS_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_CTXSW_0_CURR_CLASS_DEFAULT_MASK _MK_MASK_CONST(0x3ff) +#define SOR_CTXSW_0_CURR_CLASS_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_CTXSW_0_CURR_CLASS_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define SOR_CTXSW_0_AUTO_ACK_SHIFT _MK_SHIFT_CONST(11) +#define SOR_CTXSW_0_AUTO_ACK_FIELD _MK_FIELD_CONST(0x1, SOR_CTXSW_0_AUTO_ACK_SHIFT) +#define SOR_CTXSW_0_AUTO_ACK_RANGE 11:11 +#define SOR_CTXSW_0_AUTO_ACK_WOFFSET 0x0 +#define SOR_CTXSW_0_AUTO_ACK_DEFAULT _MK_MASK_CONST(0x1) +#define SOR_CTXSW_0_AUTO_ACK_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_CTXSW_0_AUTO_ACK_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_CTXSW_0_AUTO_ACK_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_CTXSW_0_AUTO_ACK_MANUAL _MK_ENUM_CONST(0) +#define SOR_CTXSW_0_AUTO_ACK_AUTOACK _MK_ENUM_CONST(1) + +#define SOR_CTXSW_0_CURR_CHANNEL_SHIFT _MK_SHIFT_CONST(12) +#define SOR_CTXSW_0_CURR_CHANNEL_FIELD _MK_FIELD_CONST(0xf, SOR_CTXSW_0_CURR_CHANNEL_SHIFT) +#define SOR_CTXSW_0_CURR_CHANNEL_RANGE 15:12 +#define SOR_CTXSW_0_CURR_CHANNEL_WOFFSET 0x0 +#define SOR_CTXSW_0_CURR_CHANNEL_DEFAULT _MK_MASK_CONST(0xf) +#define SOR_CTXSW_0_CURR_CHANNEL_DEFAULT_MASK _MK_MASK_CONST(0xf) +#define SOR_CTXSW_0_CURR_CHANNEL_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_CTXSW_0_CURR_CHANNEL_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define SOR_CTXSW_0_NEXT_CLASS_SHIFT _MK_SHIFT_CONST(16) +#define SOR_CTXSW_0_NEXT_CLASS_FIELD _MK_FIELD_CONST(0x3ff, SOR_CTXSW_0_NEXT_CLASS_SHIFT) +#define SOR_CTXSW_0_NEXT_CLASS_RANGE 25:16 +#define SOR_CTXSW_0_NEXT_CLASS_WOFFSET 0x0 +#define SOR_CTXSW_0_NEXT_CLASS_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_CTXSW_0_NEXT_CLASS_DEFAULT_MASK _MK_MASK_CONST(0x3ff) +#define SOR_CTXSW_0_NEXT_CLASS_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_CTXSW_0_NEXT_CLASS_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define SOR_CTXSW_0_NEXT_CHANNEL_SHIFT _MK_SHIFT_CONST(28) +#define SOR_CTXSW_0_NEXT_CHANNEL_FIELD _MK_FIELD_CONST(0xf, SOR_CTXSW_0_NEXT_CHANNEL_SHIFT) +#define SOR_CTXSW_0_NEXT_CHANNEL_RANGE 31:28 +#define SOR_CTXSW_0_NEXT_CHANNEL_WOFFSET 0x0 +#define SOR_CTXSW_0_NEXT_CHANNEL_DEFAULT _MK_MASK_CONST(0xf) +#define SOR_CTXSW_0_NEXT_CHANNEL_DEFAULT_MASK _MK_MASK_CONST(0xf) +#define SOR_CTXSW_0_NEXT_CHANNEL_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_CTXSW_0_NEXT_CHANNEL_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register SOR_NV_PDISP_SOR_SUPER_STATE0_0 +#define SOR_NV_PDISP_SOR_SUPER_STATE0_0 _MK_ADDR_CONST(0x1) +#define SOR_NV_PDISP_SOR_SUPER_STATE0_0_SECURE 0x0 +#define SOR_NV_PDISP_SOR_SUPER_STATE0_0_WORD_COUNT 0x1 +#define SOR_NV_PDISP_SOR_SUPER_STATE0_0_RESET_VAL _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SUPER_STATE0_0_RESET_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SUPER_STATE0_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SUPER_STATE0_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SUPER_STATE0_0_READ_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SUPER_STATE0_0_WRITE_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SUPER_STATE0_0_UPDATE_SHIFT _MK_SHIFT_CONST(0) +#define SOR_NV_PDISP_SOR_SUPER_STATE0_0_UPDATE_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SUPER_STATE0_0_UPDATE_SHIFT) +#define SOR_NV_PDISP_SOR_SUPER_STATE0_0_UPDATE_RANGE 0:0 +#define SOR_NV_PDISP_SOR_SUPER_STATE0_0_UPDATE_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SUPER_STATE0_0_UPDATE_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SUPER_STATE0_0_UPDATE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SUPER_STATE0_0_UPDATE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SUPER_STATE0_0_UPDATE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register SOR_NV_PDISP_SOR_SUPER_STATE1_0 +#define SOR_NV_PDISP_SOR_SUPER_STATE1_0 _MK_ADDR_CONST(0x2) +#define SOR_NV_PDISP_SOR_SUPER_STATE1_0_SECURE 0x0 +#define SOR_NV_PDISP_SOR_SUPER_STATE1_0_WORD_COUNT 0x1 +#define SOR_NV_PDISP_SOR_SUPER_STATE1_0_RESET_VAL _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SUPER_STATE1_0_RESET_MASK _MK_MASK_CONST(0xf) +#define SOR_NV_PDISP_SOR_SUPER_STATE1_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SUPER_STATE1_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SUPER_STATE1_0_READ_MASK _MK_MASK_CONST(0xf) +#define SOR_NV_PDISP_SOR_SUPER_STATE1_0_WRITE_MASK _MK_MASK_CONST(0xf) +#define SOR_NV_PDISP_SOR_SUPER_STATE1_0_ATTACHED_SHIFT _MK_SHIFT_CONST(3) +#define SOR_NV_PDISP_SOR_SUPER_STATE1_0_ATTACHED_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SUPER_STATE1_0_ATTACHED_SHIFT) +#define SOR_NV_PDISP_SOR_SUPER_STATE1_0_ATTACHED_RANGE 3:3 +#define SOR_NV_PDISP_SOR_SUPER_STATE1_0_ATTACHED_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SUPER_STATE1_0_ATTACHED_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SUPER_STATE1_0_ATTACHED_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SUPER_STATE1_0_ATTACHED_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SUPER_STATE1_0_ATTACHED_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SUPER_STATE1_0_ATTACHED_INIT_ENUM NO +#define SOR_NV_PDISP_SOR_SUPER_STATE1_0_ATTACHED_NO _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SUPER_STATE1_0_ATTACHED_YES _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SUPER_STATE1_0_ASY_ORMODE_SHIFT _MK_SHIFT_CONST(2) +#define SOR_NV_PDISP_SOR_SUPER_STATE1_0_ASY_ORMODE_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SUPER_STATE1_0_ASY_ORMODE_SHIFT) +#define SOR_NV_PDISP_SOR_SUPER_STATE1_0_ASY_ORMODE_RANGE 2:2 +#define SOR_NV_PDISP_SOR_SUPER_STATE1_0_ASY_ORMODE_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SUPER_STATE1_0_ASY_ORMODE_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SUPER_STATE1_0_ASY_ORMODE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SUPER_STATE1_0_ASY_ORMODE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SUPER_STATE1_0_ASY_ORMODE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SUPER_STATE1_0_ASY_ORMODE_INIT_ENUM SAFE +#define SOR_NV_PDISP_SOR_SUPER_STATE1_0_ASY_ORMODE_SAFE _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SUPER_STATE1_0_ASY_ORMODE_NORMAL _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SUPER_STATE1_0_ASY_HEAD_OPMODE_SHIFT _MK_SHIFT_CONST(0) +#define SOR_NV_PDISP_SOR_SUPER_STATE1_0_ASY_HEAD_OPMODE_FIELD _MK_FIELD_CONST(0x3, SOR_NV_PDISP_SOR_SUPER_STATE1_0_ASY_HEAD_OPMODE_SHIFT) +#define SOR_NV_PDISP_SOR_SUPER_STATE1_0_ASY_HEAD_OPMODE_RANGE 1:0 +#define SOR_NV_PDISP_SOR_SUPER_STATE1_0_ASY_HEAD_OPMODE_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SUPER_STATE1_0_ASY_HEAD_OPMODE_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SUPER_STATE1_0_ASY_HEAD_OPMODE_DEFAULT_MASK _MK_MASK_CONST(0x3) +#define SOR_NV_PDISP_SOR_SUPER_STATE1_0_ASY_HEAD_OPMODE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SUPER_STATE1_0_ASY_HEAD_OPMODE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SUPER_STATE1_0_ASY_HEAD_OPMODE_SLEEP _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SUPER_STATE1_0_ASY_HEAD_OPMODE_SNOOZE _MK_ENUM_CONST(1) +#define SOR_NV_PDISP_SOR_SUPER_STATE1_0_ASY_HEAD_OPMODE_AWAKE _MK_ENUM_CONST(2) + + +// Register SOR_NV_PDISP_SOR_STATE0_0 +#define SOR_NV_PDISP_SOR_STATE0_0 _MK_ADDR_CONST(0x3) +#define SOR_NV_PDISP_SOR_STATE0_0_SECURE 0x0 +#define SOR_NV_PDISP_SOR_STATE0_0_WORD_COUNT 0x1 +#define SOR_NV_PDISP_SOR_STATE0_0_RESET_VAL _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_STATE0_0_RESET_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_STATE0_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_STATE0_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_STATE0_0_READ_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_STATE0_0_WRITE_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_STATE0_0_UPDATE_SHIFT _MK_SHIFT_CONST(0) +#define SOR_NV_PDISP_SOR_STATE0_0_UPDATE_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_STATE0_0_UPDATE_SHIFT) +#define SOR_NV_PDISP_SOR_STATE0_0_UPDATE_RANGE 0:0 +#define SOR_NV_PDISP_SOR_STATE0_0_UPDATE_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_STATE0_0_UPDATE_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_STATE0_0_UPDATE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_STATE0_0_UPDATE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_STATE0_0_UPDATE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register SOR_NV_PDISP_SOR_STATE1_0 +#define SOR_NV_PDISP_SOR_STATE1_0 _MK_ADDR_CONST(0x4) +#define SOR_NV_PDISP_SOR_STATE1_0_SECURE 0x0 +#define SOR_NV_PDISP_SOR_STATE1_0_WORD_COUNT 0x1 +#define SOR_NV_PDISP_SOR_STATE1_0_RESET_VAL _MK_MASK_CONST(0x40) +#define SOR_NV_PDISP_SOR_STATE1_0_RESET_MASK _MK_MASK_CONST(0x1fffff) +#define SOR_NV_PDISP_SOR_STATE1_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_STATE1_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_STATE1_0_READ_MASK _MK_MASK_CONST(0x1fffff) +#define SOR_NV_PDISP_SOR_STATE1_0_WRITE_MASK _MK_MASK_CONST(0x1fffff) +#define SOR_NV_PDISP_SOR_STATE1_0_ASY_PIXELDEPTH_SHIFT _MK_SHIFT_CONST(17) +#define SOR_NV_PDISP_SOR_STATE1_0_ASY_PIXELDEPTH_FIELD _MK_FIELD_CONST(0xf, SOR_NV_PDISP_SOR_STATE1_0_ASY_PIXELDEPTH_SHIFT) +#define SOR_NV_PDISP_SOR_STATE1_0_ASY_PIXELDEPTH_RANGE 20:17 +#define SOR_NV_PDISP_SOR_STATE1_0_ASY_PIXELDEPTH_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_STATE1_0_ASY_PIXELDEPTH_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_STATE1_0_ASY_PIXELDEPTH_DEFAULT_MASK _MK_MASK_CONST(0xf) +#define SOR_NV_PDISP_SOR_STATE1_0_ASY_PIXELDEPTH_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_STATE1_0_ASY_PIXELDEPTH_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_STATE1_0_ASY_PIXELDEPTH_INIT_ENUM DEFAULTVAL +#define SOR_NV_PDISP_SOR_STATE1_0_ASY_PIXELDEPTH_DEFAULTVAL _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_STATE1_0_ASY_PIXELDEPTH_BPP_16_422 _MK_ENUM_CONST(1) +#define SOR_NV_PDISP_SOR_STATE1_0_ASY_PIXELDEPTH_BPP_18_444 _MK_ENUM_CONST(2) +#define SOR_NV_PDISP_SOR_STATE1_0_ASY_PIXELDEPTH_BPP_20_422 _MK_ENUM_CONST(3) +#define SOR_NV_PDISP_SOR_STATE1_0_ASY_PIXELDEPTH_BPP_24_422 _MK_ENUM_CONST(4) +#define SOR_NV_PDISP_SOR_STATE1_0_ASY_PIXELDEPTH_BPP_24_444 _MK_ENUM_CONST(5) +#define SOR_NV_PDISP_SOR_STATE1_0_ASY_PIXELDEPTH_BPP_30_444 _MK_ENUM_CONST(6) +#define SOR_NV_PDISP_SOR_STATE1_0_ASY_PIXELDEPTH_BPP_32_422 _MK_ENUM_CONST(7) +#define SOR_NV_PDISP_SOR_STATE1_0_ASY_PIXELDEPTH_BPP_36_444 _MK_ENUM_CONST(8) +#define SOR_NV_PDISP_SOR_STATE1_0_ASY_PIXELDEPTH_BPP_48_444 _MK_ENUM_CONST(9) + +#define SOR_NV_PDISP_SOR_STATE1_0_ASY_REPLICATE_SHIFT _MK_SHIFT_CONST(15) +#define SOR_NV_PDISP_SOR_STATE1_0_ASY_REPLICATE_FIELD _MK_FIELD_CONST(0x3, SOR_NV_PDISP_SOR_STATE1_0_ASY_REPLICATE_SHIFT) +#define SOR_NV_PDISP_SOR_STATE1_0_ASY_REPLICATE_RANGE 16:15 +#define SOR_NV_PDISP_SOR_STATE1_0_ASY_REPLICATE_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_STATE1_0_ASY_REPLICATE_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_STATE1_0_ASY_REPLICATE_DEFAULT_MASK _MK_MASK_CONST(0x3) +#define SOR_NV_PDISP_SOR_STATE1_0_ASY_REPLICATE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_STATE1_0_ASY_REPLICATE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_STATE1_0_ASY_REPLICATE_INIT_ENUM OFF +#define SOR_NV_PDISP_SOR_STATE1_0_ASY_REPLICATE_OFF _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_STATE1_0_ASY_REPLICATE_X2 _MK_ENUM_CONST(1) +#define SOR_NV_PDISP_SOR_STATE1_0_ASY_REPLICATE_X4 _MK_ENUM_CONST(2) + +#define SOR_NV_PDISP_SOR_STATE1_0_ASY_DEPOL_SHIFT _MK_SHIFT_CONST(14) +#define SOR_NV_PDISP_SOR_STATE1_0_ASY_DEPOL_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_STATE1_0_ASY_DEPOL_SHIFT) +#define SOR_NV_PDISP_SOR_STATE1_0_ASY_DEPOL_RANGE 14:14 +#define SOR_NV_PDISP_SOR_STATE1_0_ASY_DEPOL_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_STATE1_0_ASY_DEPOL_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_STATE1_0_ASY_DEPOL_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_STATE1_0_ASY_DEPOL_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_STATE1_0_ASY_DEPOL_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_STATE1_0_ASY_DEPOL_POSITIVE_TRUE _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_STATE1_0_ASY_DEPOL_NEGATIVE_TRUE _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_STATE1_0_ASY_VSYNCPOL_SHIFT _MK_SHIFT_CONST(13) +#define SOR_NV_PDISP_SOR_STATE1_0_ASY_VSYNCPOL_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_STATE1_0_ASY_VSYNCPOL_SHIFT) +#define SOR_NV_PDISP_SOR_STATE1_0_ASY_VSYNCPOL_RANGE 13:13 +#define SOR_NV_PDISP_SOR_STATE1_0_ASY_VSYNCPOL_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_STATE1_0_ASY_VSYNCPOL_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_STATE1_0_ASY_VSYNCPOL_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_STATE1_0_ASY_VSYNCPOL_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_STATE1_0_ASY_VSYNCPOL_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_STATE1_0_ASY_VSYNCPOL_POSITIVE_TRUE _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_STATE1_0_ASY_VSYNCPOL_NEGATIVE_TRUE _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_STATE1_0_ASY_HSYNCPOL_SHIFT _MK_SHIFT_CONST(12) +#define SOR_NV_PDISP_SOR_STATE1_0_ASY_HSYNCPOL_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_STATE1_0_ASY_HSYNCPOL_SHIFT) +#define SOR_NV_PDISP_SOR_STATE1_0_ASY_HSYNCPOL_RANGE 12:12 +#define SOR_NV_PDISP_SOR_STATE1_0_ASY_HSYNCPOL_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_STATE1_0_ASY_HSYNCPOL_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_STATE1_0_ASY_HSYNCPOL_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_STATE1_0_ASY_HSYNCPOL_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_STATE1_0_ASY_HSYNCPOL_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_STATE1_0_ASY_HSYNCPOL_POSITIVE_TRUE _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_STATE1_0_ASY_HSYNCPOL_NEGATIVE_TRUE _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_STATE1_0_ASY_PROTOCOL_SHIFT _MK_SHIFT_CONST(8) +#define SOR_NV_PDISP_SOR_STATE1_0_ASY_PROTOCOL_FIELD _MK_FIELD_CONST(0xf, SOR_NV_PDISP_SOR_STATE1_0_ASY_PROTOCOL_SHIFT) +#define SOR_NV_PDISP_SOR_STATE1_0_ASY_PROTOCOL_RANGE 11:8 +#define SOR_NV_PDISP_SOR_STATE1_0_ASY_PROTOCOL_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_STATE1_0_ASY_PROTOCOL_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_STATE1_0_ASY_PROTOCOL_DEFAULT_MASK _MK_MASK_CONST(0xf) +#define SOR_NV_PDISP_SOR_STATE1_0_ASY_PROTOCOL_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_STATE1_0_ASY_PROTOCOL_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_STATE1_0_ASY_PROTOCOL_INIT_ENUM LVDS_CUSTOM +#define SOR_NV_PDISP_SOR_STATE1_0_ASY_PROTOCOL_LVDS_CUSTOM _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_STATE1_0_ASY_PROTOCOL_DP_A _MK_ENUM_CONST(8) +#define SOR_NV_PDISP_SOR_STATE1_0_ASY_PROTOCOL_DP_B _MK_ENUM_CONST(9) +#define SOR_NV_PDISP_SOR_STATE1_0_ASY_PROTOCOL_CUSTOM _MK_ENUM_CONST(15) + +#define SOR_NV_PDISP_SOR_STATE1_0_ASY_CRCMODE_SHIFT _MK_SHIFT_CONST(6) +#define SOR_NV_PDISP_SOR_STATE1_0_ASY_CRCMODE_FIELD _MK_FIELD_CONST(0x3, SOR_NV_PDISP_SOR_STATE1_0_ASY_CRCMODE_SHIFT) +#define SOR_NV_PDISP_SOR_STATE1_0_ASY_CRCMODE_RANGE 7:6 +#define SOR_NV_PDISP_SOR_STATE1_0_ASY_CRCMODE_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_STATE1_0_ASY_CRCMODE_DEFAULT _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_STATE1_0_ASY_CRCMODE_DEFAULT_MASK _MK_MASK_CONST(0x3) +#define SOR_NV_PDISP_SOR_STATE1_0_ASY_CRCMODE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_STATE1_0_ASY_CRCMODE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_STATE1_0_ASY_CRCMODE_INIT_ENUM COMPLETE_RASTER +#define SOR_NV_PDISP_SOR_STATE1_0_ASY_CRCMODE_ACTIVE_RASTER _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_STATE1_0_ASY_CRCMODE_COMPLETE_RASTER _MK_ENUM_CONST(1) +#define SOR_NV_PDISP_SOR_STATE1_0_ASY_CRCMODE_NON_ACTIVE_RASTER _MK_ENUM_CONST(2) + +#define SOR_NV_PDISP_SOR_STATE1_0_ASY_SUBOWNER_SHIFT _MK_SHIFT_CONST(4) +#define SOR_NV_PDISP_SOR_STATE1_0_ASY_SUBOWNER_FIELD _MK_FIELD_CONST(0x3, SOR_NV_PDISP_SOR_STATE1_0_ASY_SUBOWNER_SHIFT) +#define SOR_NV_PDISP_SOR_STATE1_0_ASY_SUBOWNER_RANGE 5:4 +#define SOR_NV_PDISP_SOR_STATE1_0_ASY_SUBOWNER_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_STATE1_0_ASY_SUBOWNER_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_STATE1_0_ASY_SUBOWNER_DEFAULT_MASK _MK_MASK_CONST(0x3) +#define SOR_NV_PDISP_SOR_STATE1_0_ASY_SUBOWNER_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_STATE1_0_ASY_SUBOWNER_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_STATE1_0_ASY_SUBOWNER_INIT_ENUM NONE +#define SOR_NV_PDISP_SOR_STATE1_0_ASY_SUBOWNER_NONE _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_STATE1_0_ASY_SUBOWNER_SUBHEAD0 _MK_ENUM_CONST(1) +#define SOR_NV_PDISP_SOR_STATE1_0_ASY_SUBOWNER_SUBHEAD1 _MK_ENUM_CONST(2) +#define SOR_NV_PDISP_SOR_STATE1_0_ASY_SUBOWNER_BOTH _MK_ENUM_CONST(3) + +#define SOR_NV_PDISP_SOR_STATE1_0_ASY_OWNER_SHIFT _MK_SHIFT_CONST(0) +#define SOR_NV_PDISP_SOR_STATE1_0_ASY_OWNER_FIELD _MK_FIELD_CONST(0xf, SOR_NV_PDISP_SOR_STATE1_0_ASY_OWNER_SHIFT) +#define SOR_NV_PDISP_SOR_STATE1_0_ASY_OWNER_RANGE 3:0 +#define SOR_NV_PDISP_SOR_STATE1_0_ASY_OWNER_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_STATE1_0_ASY_OWNER_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_STATE1_0_ASY_OWNER_DEFAULT_MASK _MK_MASK_CONST(0xf) +#define SOR_NV_PDISP_SOR_STATE1_0_ASY_OWNER_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_STATE1_0_ASY_OWNER_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_STATE1_0_ASY_OWNER_INIT_ENUM NONE +#define SOR_NV_PDISP_SOR_STATE1_0_ASY_OWNER_NONE _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_STATE1_0_ASY_OWNER_HEAD0 _MK_ENUM_CONST(1) +#define SOR_NV_PDISP_SOR_STATE1_0_ASY_OWNER_HEAD1 _MK_ENUM_CONST(2) + + +// Register SOR_NV_PDISP_HEAD_STATE0_0 +#define SOR_NV_PDISP_HEAD_STATE0_0 _MK_ADDR_CONST(0x5) +#define SOR_NV_PDISP_HEAD_STATE0_0_SECURE 0x0 +#define SOR_NV_PDISP_HEAD_STATE0_0_WORD_COUNT 0x1 +#define SOR_NV_PDISP_HEAD_STATE0_0_RESET_VAL _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_HEAD_STATE0_0_RESET_MASK _MK_MASK_CONST(0x3f) +#define SOR_NV_PDISP_HEAD_STATE0_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_HEAD_STATE0_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_HEAD_STATE0_0_READ_MASK _MK_MASK_CONST(0x3f) +#define SOR_NV_PDISP_HEAD_STATE0_0_WRITE_MASK _MK_MASK_CONST(0x3f) +#define SOR_NV_PDISP_HEAD_STATE0_0_INTERLACED_SHIFT _MK_SHIFT_CONST(4) +#define SOR_NV_PDISP_HEAD_STATE0_0_INTERLACED_FIELD _MK_FIELD_CONST(0x3, SOR_NV_PDISP_HEAD_STATE0_0_INTERLACED_SHIFT) +#define SOR_NV_PDISP_HEAD_STATE0_0_INTERLACED_RANGE 5:4 +#define SOR_NV_PDISP_HEAD_STATE0_0_INTERLACED_WOFFSET 0x0 +#define SOR_NV_PDISP_HEAD_STATE0_0_INTERLACED_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_HEAD_STATE0_0_INTERLACED_DEFAULT_MASK _MK_MASK_CONST(0x3) +#define SOR_NV_PDISP_HEAD_STATE0_0_INTERLACED_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_HEAD_STATE0_0_INTERLACED_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_HEAD_STATE0_0_INTERLACED_INIT_ENUM PROGRESSIVE +#define SOR_NV_PDISP_HEAD_STATE0_0_INTERLACED_PROGRESSIVE _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_HEAD_STATE0_0_INTERLACED_INTERLACED _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_HEAD_STATE0_0_RANGECOMPRESS_SHIFT _MK_SHIFT_CONST(3) +#define SOR_NV_PDISP_HEAD_STATE0_0_RANGECOMPRESS_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_HEAD_STATE0_0_RANGECOMPRESS_SHIFT) +#define SOR_NV_PDISP_HEAD_STATE0_0_RANGECOMPRESS_RANGE 3:3 +#define SOR_NV_PDISP_HEAD_STATE0_0_RANGECOMPRESS_WOFFSET 0x0 +#define SOR_NV_PDISP_HEAD_STATE0_0_RANGECOMPRESS_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_HEAD_STATE0_0_RANGECOMPRESS_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_HEAD_STATE0_0_RANGECOMPRESS_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_HEAD_STATE0_0_RANGECOMPRESS_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_HEAD_STATE0_0_RANGECOMPRESS_INIT_ENUM DISABLE +#define SOR_NV_PDISP_HEAD_STATE0_0_RANGECOMPRESS_DISABLE _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_HEAD_STATE0_0_RANGECOMPRESS_ENABLE _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_HEAD_STATE0_0_DYNRANGE_SHIFT _MK_SHIFT_CONST(2) +#define SOR_NV_PDISP_HEAD_STATE0_0_DYNRANGE_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_HEAD_STATE0_0_DYNRANGE_SHIFT) +#define SOR_NV_PDISP_HEAD_STATE0_0_DYNRANGE_RANGE 2:2 +#define SOR_NV_PDISP_HEAD_STATE0_0_DYNRANGE_WOFFSET 0x0 +#define SOR_NV_PDISP_HEAD_STATE0_0_DYNRANGE_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_HEAD_STATE0_0_DYNRANGE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_HEAD_STATE0_0_DYNRANGE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_HEAD_STATE0_0_DYNRANGE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_HEAD_STATE0_0_DYNRANGE_INIT_ENUM VESA +#define SOR_NV_PDISP_HEAD_STATE0_0_DYNRANGE_VESA _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_HEAD_STATE0_0_DYNRANGE_CEA _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_HEAD_STATE0_0_COLORSPACE_SHIFT _MK_SHIFT_CONST(0) +#define SOR_NV_PDISP_HEAD_STATE0_0_COLORSPACE_FIELD _MK_FIELD_CONST(0x3, SOR_NV_PDISP_HEAD_STATE0_0_COLORSPACE_SHIFT) +#define SOR_NV_PDISP_HEAD_STATE0_0_COLORSPACE_RANGE 1:0 +#define SOR_NV_PDISP_HEAD_STATE0_0_COLORSPACE_WOFFSET 0x0 +#define SOR_NV_PDISP_HEAD_STATE0_0_COLORSPACE_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_HEAD_STATE0_0_COLORSPACE_DEFAULT_MASK _MK_MASK_CONST(0x3) +#define SOR_NV_PDISP_HEAD_STATE0_0_COLORSPACE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_HEAD_STATE0_0_COLORSPACE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_HEAD_STATE0_0_COLORSPACE_INIT_ENUM RGB +#define SOR_NV_PDISP_HEAD_STATE0_0_COLORSPACE_RGB _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_HEAD_STATE0_0_COLORSPACE_YUV_601 _MK_ENUM_CONST(1) +#define SOR_NV_PDISP_HEAD_STATE0_0_COLORSPACE_YUV_709 _MK_ENUM_CONST(2) + + +// Register SOR_NV_PDISP_HEAD_STATE0 +#define SOR_NV_PDISP_HEAD_STATE0 _MK_ADDR_CONST(0x5) +#define SOR_NV_PDISP_HEAD_STATE0_SECURE 0x0 +#define SOR_NV_PDISP_HEAD_STATE0_WORD_COUNT 0x1 +#define SOR_NV_PDISP_HEAD_STATE0_RESET_VAL _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_HEAD_STATE0_RESET_MASK _MK_MASK_CONST(0x3f) +#define SOR_NV_PDISP_HEAD_STATE0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_HEAD_STATE0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_HEAD_STATE0_READ_MASK _MK_MASK_CONST(0x3f) +#define SOR_NV_PDISP_HEAD_STATE0_WRITE_MASK _MK_MASK_CONST(0x3f) +#define SOR_NV_PDISP_HEAD_STATE0_INTERLACED_SHIFT _MK_SHIFT_CONST(4) +#define SOR_NV_PDISP_HEAD_STATE0_INTERLACED_FIELD _MK_FIELD_CONST(0x3, SOR_NV_PDISP_HEAD_STATE0_INTERLACED_SHIFT) +#define SOR_NV_PDISP_HEAD_STATE0_INTERLACED_RANGE 5:4 +#define SOR_NV_PDISP_HEAD_STATE0_INTERLACED_WOFFSET 0x0 +#define SOR_NV_PDISP_HEAD_STATE0_INTERLACED_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_HEAD_STATE0_INTERLACED_DEFAULT_MASK _MK_MASK_CONST(0x3) +#define SOR_NV_PDISP_HEAD_STATE0_INTERLACED_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_HEAD_STATE0_INTERLACED_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_HEAD_STATE0_INTERLACED_INIT_ENUM PROGRESSIVE +#define SOR_NV_PDISP_HEAD_STATE0_INTERLACED_PROGRESSIVE _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_HEAD_STATE0_INTERLACED_INTERLACED _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_HEAD_STATE0_RANGECOMPRESS_SHIFT _MK_SHIFT_CONST(3) +#define SOR_NV_PDISP_HEAD_STATE0_RANGECOMPRESS_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_HEAD_STATE0_RANGECOMPRESS_SHIFT) +#define SOR_NV_PDISP_HEAD_STATE0_RANGECOMPRESS_RANGE 3:3 +#define SOR_NV_PDISP_HEAD_STATE0_RANGECOMPRESS_WOFFSET 0x0 +#define SOR_NV_PDISP_HEAD_STATE0_RANGECOMPRESS_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_HEAD_STATE0_RANGECOMPRESS_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_HEAD_STATE0_RANGECOMPRESS_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_HEAD_STATE0_RANGECOMPRESS_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_HEAD_STATE0_RANGECOMPRESS_INIT_ENUM DISABLE +#define SOR_NV_PDISP_HEAD_STATE0_RANGECOMPRESS_DISABLE _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_HEAD_STATE0_RANGECOMPRESS_ENABLE _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_HEAD_STATE0_DYNRANGE_SHIFT _MK_SHIFT_CONST(2) +#define SOR_NV_PDISP_HEAD_STATE0_DYNRANGE_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_HEAD_STATE0_DYNRANGE_SHIFT) +#define SOR_NV_PDISP_HEAD_STATE0_DYNRANGE_RANGE 2:2 +#define SOR_NV_PDISP_HEAD_STATE0_DYNRANGE_WOFFSET 0x0 +#define SOR_NV_PDISP_HEAD_STATE0_DYNRANGE_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_HEAD_STATE0_DYNRANGE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_HEAD_STATE0_DYNRANGE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_HEAD_STATE0_DYNRANGE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_HEAD_STATE0_DYNRANGE_INIT_ENUM VESA +#define SOR_NV_PDISP_HEAD_STATE0_DYNRANGE_VESA _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_HEAD_STATE0_DYNRANGE_CEA _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_HEAD_STATE0_COLORSPACE_SHIFT _MK_SHIFT_CONST(0) +#define SOR_NV_PDISP_HEAD_STATE0_COLORSPACE_FIELD _MK_FIELD_CONST(0x3, SOR_NV_PDISP_HEAD_STATE0_COLORSPACE_SHIFT) +#define SOR_NV_PDISP_HEAD_STATE0_COLORSPACE_RANGE 1:0 +#define SOR_NV_PDISP_HEAD_STATE0_COLORSPACE_WOFFSET 0x0 +#define SOR_NV_PDISP_HEAD_STATE0_COLORSPACE_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_HEAD_STATE0_COLORSPACE_DEFAULT_MASK _MK_MASK_CONST(0x3) +#define SOR_NV_PDISP_HEAD_STATE0_COLORSPACE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_HEAD_STATE0_COLORSPACE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_HEAD_STATE0_COLORSPACE_INIT_ENUM RGB +#define SOR_NV_PDISP_HEAD_STATE0_COLORSPACE_RGB _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_HEAD_STATE0_COLORSPACE_YUV_601 _MK_ENUM_CONST(1) +#define SOR_NV_PDISP_HEAD_STATE0_COLORSPACE_YUV_709 _MK_ENUM_CONST(2) + + +// Register SOR_NV_PDISP_HEAD_STATE0_1 +#define SOR_NV_PDISP_HEAD_STATE0_1 _MK_ADDR_CONST(0x6) +#define SOR_NV_PDISP_HEAD_STATE0_1_SECURE 0x0 +#define SOR_NV_PDISP_HEAD_STATE0_1_WORD_COUNT 0x1 +#define SOR_NV_PDISP_HEAD_STATE0_1_RESET_VAL _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_HEAD_STATE0_1_RESET_MASK _MK_MASK_CONST(0x3f) +#define SOR_NV_PDISP_HEAD_STATE0_1_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_HEAD_STATE0_1_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_HEAD_STATE0_1_READ_MASK _MK_MASK_CONST(0x3f) +#define SOR_NV_PDISP_HEAD_STATE0_1_WRITE_MASK _MK_MASK_CONST(0x3f) +#define SOR_NV_PDISP_HEAD_STATE0_1_INTERLACED_SHIFT _MK_SHIFT_CONST(4) +#define SOR_NV_PDISP_HEAD_STATE0_1_INTERLACED_FIELD _MK_FIELD_CONST(0x3, SOR_NV_PDISP_HEAD_STATE0_1_INTERLACED_SHIFT) +#define SOR_NV_PDISP_HEAD_STATE0_1_INTERLACED_RANGE 5:4 +#define SOR_NV_PDISP_HEAD_STATE0_1_INTERLACED_WOFFSET 0x0 +#define SOR_NV_PDISP_HEAD_STATE0_1_INTERLACED_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_HEAD_STATE0_1_INTERLACED_DEFAULT_MASK _MK_MASK_CONST(0x3) +#define SOR_NV_PDISP_HEAD_STATE0_1_INTERLACED_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_HEAD_STATE0_1_INTERLACED_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_HEAD_STATE0_1_INTERLACED_INIT_ENUM PROGRESSIVE +#define SOR_NV_PDISP_HEAD_STATE0_1_INTERLACED_PROGRESSIVE _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_HEAD_STATE0_1_INTERLACED_INTERLACED _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_HEAD_STATE0_1_RANGECOMPRESS_SHIFT _MK_SHIFT_CONST(3) +#define SOR_NV_PDISP_HEAD_STATE0_1_RANGECOMPRESS_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_HEAD_STATE0_1_RANGECOMPRESS_SHIFT) +#define SOR_NV_PDISP_HEAD_STATE0_1_RANGECOMPRESS_RANGE 3:3 +#define SOR_NV_PDISP_HEAD_STATE0_1_RANGECOMPRESS_WOFFSET 0x0 +#define SOR_NV_PDISP_HEAD_STATE0_1_RANGECOMPRESS_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_HEAD_STATE0_1_RANGECOMPRESS_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_HEAD_STATE0_1_RANGECOMPRESS_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_HEAD_STATE0_1_RANGECOMPRESS_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_HEAD_STATE0_1_RANGECOMPRESS_INIT_ENUM DISABLE +#define SOR_NV_PDISP_HEAD_STATE0_1_RANGECOMPRESS_DISABLE _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_HEAD_STATE0_1_RANGECOMPRESS_ENABLE _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_HEAD_STATE0_1_DYNRANGE_SHIFT _MK_SHIFT_CONST(2) +#define SOR_NV_PDISP_HEAD_STATE0_1_DYNRANGE_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_HEAD_STATE0_1_DYNRANGE_SHIFT) +#define SOR_NV_PDISP_HEAD_STATE0_1_DYNRANGE_RANGE 2:2 +#define SOR_NV_PDISP_HEAD_STATE0_1_DYNRANGE_WOFFSET 0x0 +#define SOR_NV_PDISP_HEAD_STATE0_1_DYNRANGE_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_HEAD_STATE0_1_DYNRANGE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_HEAD_STATE0_1_DYNRANGE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_HEAD_STATE0_1_DYNRANGE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_HEAD_STATE0_1_DYNRANGE_INIT_ENUM VESA +#define SOR_NV_PDISP_HEAD_STATE0_1_DYNRANGE_VESA _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_HEAD_STATE0_1_DYNRANGE_CEA _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_HEAD_STATE0_1_COLORSPACE_SHIFT _MK_SHIFT_CONST(0) +#define SOR_NV_PDISP_HEAD_STATE0_1_COLORSPACE_FIELD _MK_FIELD_CONST(0x3, SOR_NV_PDISP_HEAD_STATE0_1_COLORSPACE_SHIFT) +#define SOR_NV_PDISP_HEAD_STATE0_1_COLORSPACE_RANGE 1:0 +#define SOR_NV_PDISP_HEAD_STATE0_1_COLORSPACE_WOFFSET 0x0 +#define SOR_NV_PDISP_HEAD_STATE0_1_COLORSPACE_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_HEAD_STATE0_1_COLORSPACE_DEFAULT_MASK _MK_MASK_CONST(0x3) +#define SOR_NV_PDISP_HEAD_STATE0_1_COLORSPACE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_HEAD_STATE0_1_COLORSPACE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_HEAD_STATE0_1_COLORSPACE_INIT_ENUM RGB +#define SOR_NV_PDISP_HEAD_STATE0_1_COLORSPACE_RGB _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_HEAD_STATE0_1_COLORSPACE_YUV_601 _MK_ENUM_CONST(1) +#define SOR_NV_PDISP_HEAD_STATE0_1_COLORSPACE_YUV_709 _MK_ENUM_CONST(2) + + +// Register SOR_NV_PDISP_HEAD_STATE1_0 +#define SOR_NV_PDISP_HEAD_STATE1_0 _MK_ADDR_CONST(0x7) +#define SOR_NV_PDISP_HEAD_STATE1_0_SECURE 0x0 +#define SOR_NV_PDISP_HEAD_STATE1_0_WORD_COUNT 0x1 +#define SOR_NV_PDISP_HEAD_STATE1_0_RESET_VAL _MK_MASK_CONST(0x1011000) +#define SOR_NV_PDISP_HEAD_STATE1_0_RESET_MASK _MK_MASK_CONST(0x7fff7fff) +#define SOR_NV_PDISP_HEAD_STATE1_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_HEAD_STATE1_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_HEAD_STATE1_0_READ_MASK _MK_MASK_CONST(0x7fff7fff) +#define SOR_NV_PDISP_HEAD_STATE1_0_WRITE_MASK _MK_MASK_CONST(0x7fff7fff) +#define SOR_NV_PDISP_HEAD_STATE1_0_VTOTAL_SHIFT _MK_SHIFT_CONST(16) +#define SOR_NV_PDISP_HEAD_STATE1_0_VTOTAL_FIELD _MK_FIELD_CONST(0x7fff, SOR_NV_PDISP_HEAD_STATE1_0_VTOTAL_SHIFT) +#define SOR_NV_PDISP_HEAD_STATE1_0_VTOTAL_RANGE 30:16 +#define SOR_NV_PDISP_HEAD_STATE1_0_VTOTAL_WOFFSET 0x0 +#define SOR_NV_PDISP_HEAD_STATE1_0_VTOTAL_DEFAULT _MK_MASK_CONST(0x101) +#define SOR_NV_PDISP_HEAD_STATE1_0_VTOTAL_DEFAULT_MASK _MK_MASK_CONST(0x7fff) +#define SOR_NV_PDISP_HEAD_STATE1_0_VTOTAL_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_HEAD_STATE1_0_VTOTAL_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define SOR_NV_PDISP_HEAD_STATE1_0_HTOTAL_SHIFT _MK_SHIFT_CONST(0) +#define SOR_NV_PDISP_HEAD_STATE1_0_HTOTAL_FIELD _MK_FIELD_CONST(0x7fff, SOR_NV_PDISP_HEAD_STATE1_0_HTOTAL_SHIFT) +#define SOR_NV_PDISP_HEAD_STATE1_0_HTOTAL_RANGE 14:0 +#define SOR_NV_PDISP_HEAD_STATE1_0_HTOTAL_WOFFSET 0x0 +#define SOR_NV_PDISP_HEAD_STATE1_0_HTOTAL_DEFAULT _MK_MASK_CONST(0x1000) +#define SOR_NV_PDISP_HEAD_STATE1_0_HTOTAL_DEFAULT_MASK _MK_MASK_CONST(0x7fff) +#define SOR_NV_PDISP_HEAD_STATE1_0_HTOTAL_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_HEAD_STATE1_0_HTOTAL_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register SOR_NV_PDISP_HEAD_STATE1 +#define SOR_NV_PDISP_HEAD_STATE1 _MK_ADDR_CONST(0x7) +#define SOR_NV_PDISP_HEAD_STATE1_SECURE 0x0 +#define SOR_NV_PDISP_HEAD_STATE1_WORD_COUNT 0x1 +#define SOR_NV_PDISP_HEAD_STATE1_RESET_VAL _MK_MASK_CONST(0x1011000) +#define SOR_NV_PDISP_HEAD_STATE1_RESET_MASK _MK_MASK_CONST(0x7fff7fff) +#define SOR_NV_PDISP_HEAD_STATE1_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_HEAD_STATE1_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_HEAD_STATE1_READ_MASK _MK_MASK_CONST(0x7fff7fff) +#define SOR_NV_PDISP_HEAD_STATE1_WRITE_MASK _MK_MASK_CONST(0x7fff7fff) +#define SOR_NV_PDISP_HEAD_STATE1_VTOTAL_SHIFT _MK_SHIFT_CONST(16) +#define SOR_NV_PDISP_HEAD_STATE1_VTOTAL_FIELD _MK_FIELD_CONST(0x7fff, SOR_NV_PDISP_HEAD_STATE1_VTOTAL_SHIFT) +#define SOR_NV_PDISP_HEAD_STATE1_VTOTAL_RANGE 30:16 +#define SOR_NV_PDISP_HEAD_STATE1_VTOTAL_WOFFSET 0x0 +#define SOR_NV_PDISP_HEAD_STATE1_VTOTAL_DEFAULT _MK_MASK_CONST(0x101) +#define SOR_NV_PDISP_HEAD_STATE1_VTOTAL_DEFAULT_MASK _MK_MASK_CONST(0x7fff) +#define SOR_NV_PDISP_HEAD_STATE1_VTOTAL_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_HEAD_STATE1_VTOTAL_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define SOR_NV_PDISP_HEAD_STATE1_HTOTAL_SHIFT _MK_SHIFT_CONST(0) +#define SOR_NV_PDISP_HEAD_STATE1_HTOTAL_FIELD _MK_FIELD_CONST(0x7fff, SOR_NV_PDISP_HEAD_STATE1_HTOTAL_SHIFT) +#define SOR_NV_PDISP_HEAD_STATE1_HTOTAL_RANGE 14:0 +#define SOR_NV_PDISP_HEAD_STATE1_HTOTAL_WOFFSET 0x0 +#define SOR_NV_PDISP_HEAD_STATE1_HTOTAL_DEFAULT _MK_MASK_CONST(0x1000) +#define SOR_NV_PDISP_HEAD_STATE1_HTOTAL_DEFAULT_MASK _MK_MASK_CONST(0x7fff) +#define SOR_NV_PDISP_HEAD_STATE1_HTOTAL_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_HEAD_STATE1_HTOTAL_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register SOR_NV_PDISP_HEAD_STATE1_1 +#define SOR_NV_PDISP_HEAD_STATE1_1 _MK_ADDR_CONST(0x8) +#define SOR_NV_PDISP_HEAD_STATE1_1_SECURE 0x0 +#define SOR_NV_PDISP_HEAD_STATE1_1_WORD_COUNT 0x1 +#define SOR_NV_PDISP_HEAD_STATE1_1_RESET_VAL _MK_MASK_CONST(0x1011000) +#define SOR_NV_PDISP_HEAD_STATE1_1_RESET_MASK _MK_MASK_CONST(0x7fff7fff) +#define SOR_NV_PDISP_HEAD_STATE1_1_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_HEAD_STATE1_1_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_HEAD_STATE1_1_READ_MASK _MK_MASK_CONST(0x7fff7fff) +#define SOR_NV_PDISP_HEAD_STATE1_1_WRITE_MASK _MK_MASK_CONST(0x7fff7fff) +#define SOR_NV_PDISP_HEAD_STATE1_1_VTOTAL_SHIFT _MK_SHIFT_CONST(16) +#define SOR_NV_PDISP_HEAD_STATE1_1_VTOTAL_FIELD _MK_FIELD_CONST(0x7fff, SOR_NV_PDISP_HEAD_STATE1_1_VTOTAL_SHIFT) +#define SOR_NV_PDISP_HEAD_STATE1_1_VTOTAL_RANGE 30:16 +#define SOR_NV_PDISP_HEAD_STATE1_1_VTOTAL_WOFFSET 0x0 +#define SOR_NV_PDISP_HEAD_STATE1_1_VTOTAL_DEFAULT _MK_MASK_CONST(0x101) +#define SOR_NV_PDISP_HEAD_STATE1_1_VTOTAL_DEFAULT_MASK _MK_MASK_CONST(0x7fff) +#define SOR_NV_PDISP_HEAD_STATE1_1_VTOTAL_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_HEAD_STATE1_1_VTOTAL_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define SOR_NV_PDISP_HEAD_STATE1_1_HTOTAL_SHIFT _MK_SHIFT_CONST(0) +#define SOR_NV_PDISP_HEAD_STATE1_1_HTOTAL_FIELD _MK_FIELD_CONST(0x7fff, SOR_NV_PDISP_HEAD_STATE1_1_HTOTAL_SHIFT) +#define SOR_NV_PDISP_HEAD_STATE1_1_HTOTAL_RANGE 14:0 +#define SOR_NV_PDISP_HEAD_STATE1_1_HTOTAL_WOFFSET 0x0 +#define SOR_NV_PDISP_HEAD_STATE1_1_HTOTAL_DEFAULT _MK_MASK_CONST(0x1000) +#define SOR_NV_PDISP_HEAD_STATE1_1_HTOTAL_DEFAULT_MASK _MK_MASK_CONST(0x7fff) +#define SOR_NV_PDISP_HEAD_STATE1_1_HTOTAL_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_HEAD_STATE1_1_HTOTAL_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register SOR_NV_PDISP_HEAD_STATE2_0 +#define SOR_NV_PDISP_HEAD_STATE2_0 _MK_ADDR_CONST(0x9) +#define SOR_NV_PDISP_HEAD_STATE2_0_SECURE 0x0 +#define SOR_NV_PDISP_HEAD_STATE2_0_WORD_COUNT 0x1 +#define SOR_NV_PDISP_HEAD_STATE2_0_RESET_VAL _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_HEAD_STATE2_0_RESET_MASK _MK_MASK_CONST(0x7fff7fff) +#define SOR_NV_PDISP_HEAD_STATE2_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_HEAD_STATE2_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_HEAD_STATE2_0_READ_MASK _MK_MASK_CONST(0x7fff7fff) +#define SOR_NV_PDISP_HEAD_STATE2_0_WRITE_MASK _MK_MASK_CONST(0x7fff7fff) +#define SOR_NV_PDISP_HEAD_STATE2_0_VSYNC_END_SHIFT _MK_SHIFT_CONST(16) +#define SOR_NV_PDISP_HEAD_STATE2_0_VSYNC_END_FIELD _MK_FIELD_CONST(0x7fff, SOR_NV_PDISP_HEAD_STATE2_0_VSYNC_END_SHIFT) +#define SOR_NV_PDISP_HEAD_STATE2_0_VSYNC_END_RANGE 30:16 +#define SOR_NV_PDISP_HEAD_STATE2_0_VSYNC_END_WOFFSET 0x0 +#define SOR_NV_PDISP_HEAD_STATE2_0_VSYNC_END_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_HEAD_STATE2_0_VSYNC_END_DEFAULT_MASK _MK_MASK_CONST(0x7fff) +#define SOR_NV_PDISP_HEAD_STATE2_0_VSYNC_END_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_HEAD_STATE2_0_VSYNC_END_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define SOR_NV_PDISP_HEAD_STATE2_0_HSYNC_END_SHIFT _MK_SHIFT_CONST(0) +#define SOR_NV_PDISP_HEAD_STATE2_0_HSYNC_END_FIELD _MK_FIELD_CONST(0x7fff, SOR_NV_PDISP_HEAD_STATE2_0_HSYNC_END_SHIFT) +#define SOR_NV_PDISP_HEAD_STATE2_0_HSYNC_END_RANGE 14:0 +#define SOR_NV_PDISP_HEAD_STATE2_0_HSYNC_END_WOFFSET 0x0 +#define SOR_NV_PDISP_HEAD_STATE2_0_HSYNC_END_DEFAULT _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_HEAD_STATE2_0_HSYNC_END_DEFAULT_MASK _MK_MASK_CONST(0x7fff) +#define SOR_NV_PDISP_HEAD_STATE2_0_HSYNC_END_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_HEAD_STATE2_0_HSYNC_END_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register SOR_NV_PDISP_HEAD_STATE2 +#define SOR_NV_PDISP_HEAD_STATE2 _MK_ADDR_CONST(0x9) +#define SOR_NV_PDISP_HEAD_STATE2_SECURE 0x0 +#define SOR_NV_PDISP_HEAD_STATE2_WORD_COUNT 0x1 +#define SOR_NV_PDISP_HEAD_STATE2_RESET_VAL _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_HEAD_STATE2_RESET_MASK _MK_MASK_CONST(0x7fff7fff) +#define SOR_NV_PDISP_HEAD_STATE2_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_HEAD_STATE2_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_HEAD_STATE2_READ_MASK _MK_MASK_CONST(0x7fff7fff) +#define SOR_NV_PDISP_HEAD_STATE2_WRITE_MASK _MK_MASK_CONST(0x7fff7fff) +#define SOR_NV_PDISP_HEAD_STATE2_VSYNC_END_SHIFT _MK_SHIFT_CONST(16) +#define SOR_NV_PDISP_HEAD_STATE2_VSYNC_END_FIELD _MK_FIELD_CONST(0x7fff, SOR_NV_PDISP_HEAD_STATE2_VSYNC_END_SHIFT) +#define SOR_NV_PDISP_HEAD_STATE2_VSYNC_END_RANGE 30:16 +#define SOR_NV_PDISP_HEAD_STATE2_VSYNC_END_WOFFSET 0x0 +#define SOR_NV_PDISP_HEAD_STATE2_VSYNC_END_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_HEAD_STATE2_VSYNC_END_DEFAULT_MASK _MK_MASK_CONST(0x7fff) +#define SOR_NV_PDISP_HEAD_STATE2_VSYNC_END_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_HEAD_STATE2_VSYNC_END_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define SOR_NV_PDISP_HEAD_STATE2_HSYNC_END_SHIFT _MK_SHIFT_CONST(0) +#define SOR_NV_PDISP_HEAD_STATE2_HSYNC_END_FIELD _MK_FIELD_CONST(0x7fff, SOR_NV_PDISP_HEAD_STATE2_HSYNC_END_SHIFT) +#define SOR_NV_PDISP_HEAD_STATE2_HSYNC_END_RANGE 14:0 +#define SOR_NV_PDISP_HEAD_STATE2_HSYNC_END_WOFFSET 0x0 +#define SOR_NV_PDISP_HEAD_STATE2_HSYNC_END_DEFAULT _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_HEAD_STATE2_HSYNC_END_DEFAULT_MASK _MK_MASK_CONST(0x7fff) +#define SOR_NV_PDISP_HEAD_STATE2_HSYNC_END_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_HEAD_STATE2_HSYNC_END_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register SOR_NV_PDISP_HEAD_STATE2_1 +#define SOR_NV_PDISP_HEAD_STATE2_1 _MK_ADDR_CONST(0xa) +#define SOR_NV_PDISP_HEAD_STATE2_1_SECURE 0x0 +#define SOR_NV_PDISP_HEAD_STATE2_1_WORD_COUNT 0x1 +#define SOR_NV_PDISP_HEAD_STATE2_1_RESET_VAL _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_HEAD_STATE2_1_RESET_MASK _MK_MASK_CONST(0x7fff7fff) +#define SOR_NV_PDISP_HEAD_STATE2_1_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_HEAD_STATE2_1_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_HEAD_STATE2_1_READ_MASK _MK_MASK_CONST(0x7fff7fff) +#define SOR_NV_PDISP_HEAD_STATE2_1_WRITE_MASK _MK_MASK_CONST(0x7fff7fff) +#define SOR_NV_PDISP_HEAD_STATE2_1_VSYNC_END_SHIFT _MK_SHIFT_CONST(16) +#define SOR_NV_PDISP_HEAD_STATE2_1_VSYNC_END_FIELD _MK_FIELD_CONST(0x7fff, SOR_NV_PDISP_HEAD_STATE2_1_VSYNC_END_SHIFT) +#define SOR_NV_PDISP_HEAD_STATE2_1_VSYNC_END_RANGE 30:16 +#define SOR_NV_PDISP_HEAD_STATE2_1_VSYNC_END_WOFFSET 0x0 +#define SOR_NV_PDISP_HEAD_STATE2_1_VSYNC_END_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_HEAD_STATE2_1_VSYNC_END_DEFAULT_MASK _MK_MASK_CONST(0x7fff) +#define SOR_NV_PDISP_HEAD_STATE2_1_VSYNC_END_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_HEAD_STATE2_1_VSYNC_END_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define SOR_NV_PDISP_HEAD_STATE2_1_HSYNC_END_SHIFT _MK_SHIFT_CONST(0) +#define SOR_NV_PDISP_HEAD_STATE2_1_HSYNC_END_FIELD _MK_FIELD_CONST(0x7fff, SOR_NV_PDISP_HEAD_STATE2_1_HSYNC_END_SHIFT) +#define SOR_NV_PDISP_HEAD_STATE2_1_HSYNC_END_RANGE 14:0 +#define SOR_NV_PDISP_HEAD_STATE2_1_HSYNC_END_WOFFSET 0x0 +#define SOR_NV_PDISP_HEAD_STATE2_1_HSYNC_END_DEFAULT _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_HEAD_STATE2_1_HSYNC_END_DEFAULT_MASK _MK_MASK_CONST(0x7fff) +#define SOR_NV_PDISP_HEAD_STATE2_1_HSYNC_END_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_HEAD_STATE2_1_HSYNC_END_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register SOR_NV_PDISP_HEAD_STATE3_0 +#define SOR_NV_PDISP_HEAD_STATE3_0 _MK_ADDR_CONST(0xb) +#define SOR_NV_PDISP_HEAD_STATE3_0_SECURE 0x0 +#define SOR_NV_PDISP_HEAD_STATE3_0_WORD_COUNT 0x1 +#define SOR_NV_PDISP_HEAD_STATE3_0_RESET_VAL _MK_MASK_CONST(0x10011) +#define SOR_NV_PDISP_HEAD_STATE3_0_RESET_MASK _MK_MASK_CONST(0x7fff7fff) +#define SOR_NV_PDISP_HEAD_STATE3_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_HEAD_STATE3_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_HEAD_STATE3_0_READ_MASK _MK_MASK_CONST(0x7fff7fff) +#define SOR_NV_PDISP_HEAD_STATE3_0_WRITE_MASK _MK_MASK_CONST(0x7fff7fff) +#define SOR_NV_PDISP_HEAD_STATE3_0_VBLANK_END_SHIFT _MK_SHIFT_CONST(16) +#define SOR_NV_PDISP_HEAD_STATE3_0_VBLANK_END_FIELD _MK_FIELD_CONST(0x7fff, SOR_NV_PDISP_HEAD_STATE3_0_VBLANK_END_SHIFT) +#define SOR_NV_PDISP_HEAD_STATE3_0_VBLANK_END_RANGE 30:16 +#define SOR_NV_PDISP_HEAD_STATE3_0_VBLANK_END_WOFFSET 0x0 +#define SOR_NV_PDISP_HEAD_STATE3_0_VBLANK_END_DEFAULT _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_HEAD_STATE3_0_VBLANK_END_DEFAULT_MASK _MK_MASK_CONST(0x7fff) +#define SOR_NV_PDISP_HEAD_STATE3_0_VBLANK_END_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_HEAD_STATE3_0_VBLANK_END_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define SOR_NV_PDISP_HEAD_STATE3_0_HBLANK_END_SHIFT _MK_SHIFT_CONST(0) +#define SOR_NV_PDISP_HEAD_STATE3_0_HBLANK_END_FIELD _MK_FIELD_CONST(0x7fff, SOR_NV_PDISP_HEAD_STATE3_0_HBLANK_END_SHIFT) +#define SOR_NV_PDISP_HEAD_STATE3_0_HBLANK_END_RANGE 14:0 +#define SOR_NV_PDISP_HEAD_STATE3_0_HBLANK_END_WOFFSET 0x0 +#define SOR_NV_PDISP_HEAD_STATE3_0_HBLANK_END_DEFAULT _MK_MASK_CONST(0x11) +#define SOR_NV_PDISP_HEAD_STATE3_0_HBLANK_END_DEFAULT_MASK _MK_MASK_CONST(0x7fff) +#define SOR_NV_PDISP_HEAD_STATE3_0_HBLANK_END_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_HEAD_STATE3_0_HBLANK_END_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register SOR_NV_PDISP_HEAD_STATE3 +#define SOR_NV_PDISP_HEAD_STATE3 _MK_ADDR_CONST(0xb) +#define SOR_NV_PDISP_HEAD_STATE3_SECURE 0x0 +#define SOR_NV_PDISP_HEAD_STATE3_WORD_COUNT 0x1 +#define SOR_NV_PDISP_HEAD_STATE3_RESET_VAL _MK_MASK_CONST(0x10011) +#define SOR_NV_PDISP_HEAD_STATE3_RESET_MASK _MK_MASK_CONST(0x7fff7fff) +#define SOR_NV_PDISP_HEAD_STATE3_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_HEAD_STATE3_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_HEAD_STATE3_READ_MASK _MK_MASK_CONST(0x7fff7fff) +#define SOR_NV_PDISP_HEAD_STATE3_WRITE_MASK _MK_MASK_CONST(0x7fff7fff) +#define SOR_NV_PDISP_HEAD_STATE3_VBLANK_END_SHIFT _MK_SHIFT_CONST(16) +#define SOR_NV_PDISP_HEAD_STATE3_VBLANK_END_FIELD _MK_FIELD_CONST(0x7fff, SOR_NV_PDISP_HEAD_STATE3_VBLANK_END_SHIFT) +#define SOR_NV_PDISP_HEAD_STATE3_VBLANK_END_RANGE 30:16 +#define SOR_NV_PDISP_HEAD_STATE3_VBLANK_END_WOFFSET 0x0 +#define SOR_NV_PDISP_HEAD_STATE3_VBLANK_END_DEFAULT _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_HEAD_STATE3_VBLANK_END_DEFAULT_MASK _MK_MASK_CONST(0x7fff) +#define SOR_NV_PDISP_HEAD_STATE3_VBLANK_END_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_HEAD_STATE3_VBLANK_END_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define SOR_NV_PDISP_HEAD_STATE3_HBLANK_END_SHIFT _MK_SHIFT_CONST(0) +#define SOR_NV_PDISP_HEAD_STATE3_HBLANK_END_FIELD _MK_FIELD_CONST(0x7fff, SOR_NV_PDISP_HEAD_STATE3_HBLANK_END_SHIFT) +#define SOR_NV_PDISP_HEAD_STATE3_HBLANK_END_RANGE 14:0 +#define SOR_NV_PDISP_HEAD_STATE3_HBLANK_END_WOFFSET 0x0 +#define SOR_NV_PDISP_HEAD_STATE3_HBLANK_END_DEFAULT _MK_MASK_CONST(0x11) +#define SOR_NV_PDISP_HEAD_STATE3_HBLANK_END_DEFAULT_MASK _MK_MASK_CONST(0x7fff) +#define SOR_NV_PDISP_HEAD_STATE3_HBLANK_END_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_HEAD_STATE3_HBLANK_END_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register SOR_NV_PDISP_HEAD_STATE3_1 +#define SOR_NV_PDISP_HEAD_STATE3_1 _MK_ADDR_CONST(0xc) +#define SOR_NV_PDISP_HEAD_STATE3_1_SECURE 0x0 +#define SOR_NV_PDISP_HEAD_STATE3_1_WORD_COUNT 0x1 +#define SOR_NV_PDISP_HEAD_STATE3_1_RESET_VAL _MK_MASK_CONST(0x10011) +#define SOR_NV_PDISP_HEAD_STATE3_1_RESET_MASK _MK_MASK_CONST(0x7fff7fff) +#define SOR_NV_PDISP_HEAD_STATE3_1_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_HEAD_STATE3_1_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_HEAD_STATE3_1_READ_MASK _MK_MASK_CONST(0x7fff7fff) +#define SOR_NV_PDISP_HEAD_STATE3_1_WRITE_MASK _MK_MASK_CONST(0x7fff7fff) +#define SOR_NV_PDISP_HEAD_STATE3_1_VBLANK_END_SHIFT _MK_SHIFT_CONST(16) +#define SOR_NV_PDISP_HEAD_STATE3_1_VBLANK_END_FIELD _MK_FIELD_CONST(0x7fff, SOR_NV_PDISP_HEAD_STATE3_1_VBLANK_END_SHIFT) +#define SOR_NV_PDISP_HEAD_STATE3_1_VBLANK_END_RANGE 30:16 +#define SOR_NV_PDISP_HEAD_STATE3_1_VBLANK_END_WOFFSET 0x0 +#define SOR_NV_PDISP_HEAD_STATE3_1_VBLANK_END_DEFAULT _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_HEAD_STATE3_1_VBLANK_END_DEFAULT_MASK _MK_MASK_CONST(0x7fff) +#define SOR_NV_PDISP_HEAD_STATE3_1_VBLANK_END_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_HEAD_STATE3_1_VBLANK_END_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define SOR_NV_PDISP_HEAD_STATE3_1_HBLANK_END_SHIFT _MK_SHIFT_CONST(0) +#define SOR_NV_PDISP_HEAD_STATE3_1_HBLANK_END_FIELD _MK_FIELD_CONST(0x7fff, SOR_NV_PDISP_HEAD_STATE3_1_HBLANK_END_SHIFT) +#define SOR_NV_PDISP_HEAD_STATE3_1_HBLANK_END_RANGE 14:0 +#define SOR_NV_PDISP_HEAD_STATE3_1_HBLANK_END_WOFFSET 0x0 +#define SOR_NV_PDISP_HEAD_STATE3_1_HBLANK_END_DEFAULT _MK_MASK_CONST(0x11) +#define SOR_NV_PDISP_HEAD_STATE3_1_HBLANK_END_DEFAULT_MASK _MK_MASK_CONST(0x7fff) +#define SOR_NV_PDISP_HEAD_STATE3_1_HBLANK_END_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_HEAD_STATE3_1_HBLANK_END_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register SOR_NV_PDISP_HEAD_STATE4_0 +#define SOR_NV_PDISP_HEAD_STATE4_0 _MK_ADDR_CONST(0xd) +#define SOR_NV_PDISP_HEAD_STATE4_0_SECURE 0x0 +#define SOR_NV_PDISP_HEAD_STATE4_0_WORD_COUNT 0x1 +#define SOR_NV_PDISP_HEAD_STATE4_0_RESET_VAL _MK_MASK_CONST(0x110100) +#define SOR_NV_PDISP_HEAD_STATE4_0_RESET_MASK _MK_MASK_CONST(0x7fff7fff) +#define SOR_NV_PDISP_HEAD_STATE4_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_HEAD_STATE4_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_HEAD_STATE4_0_READ_MASK _MK_MASK_CONST(0x7fff7fff) +#define SOR_NV_PDISP_HEAD_STATE4_0_WRITE_MASK _MK_MASK_CONST(0x7fff7fff) +#define SOR_NV_PDISP_HEAD_STATE4_0_VBLANK_START_SHIFT _MK_SHIFT_CONST(16) +#define SOR_NV_PDISP_HEAD_STATE4_0_VBLANK_START_FIELD _MK_FIELD_CONST(0x7fff, SOR_NV_PDISP_HEAD_STATE4_0_VBLANK_START_SHIFT) +#define SOR_NV_PDISP_HEAD_STATE4_0_VBLANK_START_RANGE 30:16 +#define SOR_NV_PDISP_HEAD_STATE4_0_VBLANK_START_WOFFSET 0x0 +#define SOR_NV_PDISP_HEAD_STATE4_0_VBLANK_START_DEFAULT _MK_MASK_CONST(0x11) +#define SOR_NV_PDISP_HEAD_STATE4_0_VBLANK_START_DEFAULT_MASK _MK_MASK_CONST(0x7fff) +#define SOR_NV_PDISP_HEAD_STATE4_0_VBLANK_START_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_HEAD_STATE4_0_VBLANK_START_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define SOR_NV_PDISP_HEAD_STATE4_0_HBLANK_START_SHIFT _MK_SHIFT_CONST(0) +#define SOR_NV_PDISP_HEAD_STATE4_0_HBLANK_START_FIELD _MK_FIELD_CONST(0x7fff, SOR_NV_PDISP_HEAD_STATE4_0_HBLANK_START_SHIFT) +#define SOR_NV_PDISP_HEAD_STATE4_0_HBLANK_START_RANGE 14:0 +#define SOR_NV_PDISP_HEAD_STATE4_0_HBLANK_START_WOFFSET 0x0 +#define SOR_NV_PDISP_HEAD_STATE4_0_HBLANK_START_DEFAULT _MK_MASK_CONST(0x100) +#define SOR_NV_PDISP_HEAD_STATE4_0_HBLANK_START_DEFAULT_MASK _MK_MASK_CONST(0x7fff) +#define SOR_NV_PDISP_HEAD_STATE4_0_HBLANK_START_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_HEAD_STATE4_0_HBLANK_START_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register SOR_NV_PDISP_HEAD_STATE4 +#define SOR_NV_PDISP_HEAD_STATE4 _MK_ADDR_CONST(0xd) +#define SOR_NV_PDISP_HEAD_STATE4_SECURE 0x0 +#define SOR_NV_PDISP_HEAD_STATE4_WORD_COUNT 0x1 +#define SOR_NV_PDISP_HEAD_STATE4_RESET_VAL _MK_MASK_CONST(0x110100) +#define SOR_NV_PDISP_HEAD_STATE4_RESET_MASK _MK_MASK_CONST(0x7fff7fff) +#define SOR_NV_PDISP_HEAD_STATE4_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_HEAD_STATE4_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_HEAD_STATE4_READ_MASK _MK_MASK_CONST(0x7fff7fff) +#define SOR_NV_PDISP_HEAD_STATE4_WRITE_MASK _MK_MASK_CONST(0x7fff7fff) +#define SOR_NV_PDISP_HEAD_STATE4_VBLANK_START_SHIFT _MK_SHIFT_CONST(16) +#define SOR_NV_PDISP_HEAD_STATE4_VBLANK_START_FIELD _MK_FIELD_CONST(0x7fff, SOR_NV_PDISP_HEAD_STATE4_VBLANK_START_SHIFT) +#define SOR_NV_PDISP_HEAD_STATE4_VBLANK_START_RANGE 30:16 +#define SOR_NV_PDISP_HEAD_STATE4_VBLANK_START_WOFFSET 0x0 +#define SOR_NV_PDISP_HEAD_STATE4_VBLANK_START_DEFAULT _MK_MASK_CONST(0x11) +#define SOR_NV_PDISP_HEAD_STATE4_VBLANK_START_DEFAULT_MASK _MK_MASK_CONST(0x7fff) +#define SOR_NV_PDISP_HEAD_STATE4_VBLANK_START_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_HEAD_STATE4_VBLANK_START_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define SOR_NV_PDISP_HEAD_STATE4_HBLANK_START_SHIFT _MK_SHIFT_CONST(0) +#define SOR_NV_PDISP_HEAD_STATE4_HBLANK_START_FIELD _MK_FIELD_CONST(0x7fff, SOR_NV_PDISP_HEAD_STATE4_HBLANK_START_SHIFT) +#define SOR_NV_PDISP_HEAD_STATE4_HBLANK_START_RANGE 14:0 +#define SOR_NV_PDISP_HEAD_STATE4_HBLANK_START_WOFFSET 0x0 +#define SOR_NV_PDISP_HEAD_STATE4_HBLANK_START_DEFAULT _MK_MASK_CONST(0x100) +#define SOR_NV_PDISP_HEAD_STATE4_HBLANK_START_DEFAULT_MASK _MK_MASK_CONST(0x7fff) +#define SOR_NV_PDISP_HEAD_STATE4_HBLANK_START_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_HEAD_STATE4_HBLANK_START_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register SOR_NV_PDISP_HEAD_STATE4_1 +#define SOR_NV_PDISP_HEAD_STATE4_1 _MK_ADDR_CONST(0xe) +#define SOR_NV_PDISP_HEAD_STATE4_1_SECURE 0x0 +#define SOR_NV_PDISP_HEAD_STATE4_1_WORD_COUNT 0x1 +#define SOR_NV_PDISP_HEAD_STATE4_1_RESET_VAL _MK_MASK_CONST(0x110100) +#define SOR_NV_PDISP_HEAD_STATE4_1_RESET_MASK _MK_MASK_CONST(0x7fff7fff) +#define SOR_NV_PDISP_HEAD_STATE4_1_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_HEAD_STATE4_1_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_HEAD_STATE4_1_READ_MASK _MK_MASK_CONST(0x7fff7fff) +#define SOR_NV_PDISP_HEAD_STATE4_1_WRITE_MASK _MK_MASK_CONST(0x7fff7fff) +#define SOR_NV_PDISP_HEAD_STATE4_1_VBLANK_START_SHIFT _MK_SHIFT_CONST(16) +#define SOR_NV_PDISP_HEAD_STATE4_1_VBLANK_START_FIELD _MK_FIELD_CONST(0x7fff, SOR_NV_PDISP_HEAD_STATE4_1_VBLANK_START_SHIFT) +#define SOR_NV_PDISP_HEAD_STATE4_1_VBLANK_START_RANGE 30:16 +#define SOR_NV_PDISP_HEAD_STATE4_1_VBLANK_START_WOFFSET 0x0 +#define SOR_NV_PDISP_HEAD_STATE4_1_VBLANK_START_DEFAULT _MK_MASK_CONST(0x11) +#define SOR_NV_PDISP_HEAD_STATE4_1_VBLANK_START_DEFAULT_MASK _MK_MASK_CONST(0x7fff) +#define SOR_NV_PDISP_HEAD_STATE4_1_VBLANK_START_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_HEAD_STATE4_1_VBLANK_START_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define SOR_NV_PDISP_HEAD_STATE4_1_HBLANK_START_SHIFT _MK_SHIFT_CONST(0) +#define SOR_NV_PDISP_HEAD_STATE4_1_HBLANK_START_FIELD _MK_FIELD_CONST(0x7fff, SOR_NV_PDISP_HEAD_STATE4_1_HBLANK_START_SHIFT) +#define SOR_NV_PDISP_HEAD_STATE4_1_HBLANK_START_RANGE 14:0 +#define SOR_NV_PDISP_HEAD_STATE4_1_HBLANK_START_WOFFSET 0x0 +#define SOR_NV_PDISP_HEAD_STATE4_1_HBLANK_START_DEFAULT _MK_MASK_CONST(0x100) +#define SOR_NV_PDISP_HEAD_STATE4_1_HBLANK_START_DEFAULT_MASK _MK_MASK_CONST(0x7fff) +#define SOR_NV_PDISP_HEAD_STATE4_1_HBLANK_START_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_HEAD_STATE4_1_HBLANK_START_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register SOR_NV_PDISP_HEAD_STATE5_0 +#define SOR_NV_PDISP_HEAD_STATE5_0 _MK_ADDR_CONST(0xf) +#define SOR_NV_PDISP_HEAD_STATE5_0_SECURE 0x0 +#define SOR_NV_PDISP_HEAD_STATE5_0_WORD_COUNT 0x1 +#define SOR_NV_PDISP_HEAD_STATE5_0_RESET_VAL _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_HEAD_STATE5_0_RESET_MASK _MK_MASK_CONST(0x7fff7fff) +#define SOR_NV_PDISP_HEAD_STATE5_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_HEAD_STATE5_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_HEAD_STATE5_0_READ_MASK _MK_MASK_CONST(0x7fff7fff) +#define SOR_NV_PDISP_HEAD_STATE5_0_WRITE_MASK _MK_MASK_CONST(0x7fff7fff) +#define SOR_NV_PDISP_HEAD_STATE5_0_VBLANK_END_2_SHIFT _MK_SHIFT_CONST(16) +#define SOR_NV_PDISP_HEAD_STATE5_0_VBLANK_END_2_FIELD _MK_FIELD_CONST(0x7fff, SOR_NV_PDISP_HEAD_STATE5_0_VBLANK_END_2_SHIFT) +#define SOR_NV_PDISP_HEAD_STATE5_0_VBLANK_END_2_RANGE 30:16 +#define SOR_NV_PDISP_HEAD_STATE5_0_VBLANK_END_2_WOFFSET 0x0 +#define SOR_NV_PDISP_HEAD_STATE5_0_VBLANK_END_2_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_HEAD_STATE5_0_VBLANK_END_2_DEFAULT_MASK _MK_MASK_CONST(0x7fff) +#define SOR_NV_PDISP_HEAD_STATE5_0_VBLANK_END_2_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_HEAD_STATE5_0_VBLANK_END_2_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define SOR_NV_PDISP_HEAD_STATE5_0_VBLANK_START_2_SHIFT _MK_SHIFT_CONST(0) +#define SOR_NV_PDISP_HEAD_STATE5_0_VBLANK_START_2_FIELD _MK_FIELD_CONST(0x7fff, SOR_NV_PDISP_HEAD_STATE5_0_VBLANK_START_2_SHIFT) +#define SOR_NV_PDISP_HEAD_STATE5_0_VBLANK_START_2_RANGE 14:0 +#define SOR_NV_PDISP_HEAD_STATE5_0_VBLANK_START_2_WOFFSET 0x0 +#define SOR_NV_PDISP_HEAD_STATE5_0_VBLANK_START_2_DEFAULT _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_HEAD_STATE5_0_VBLANK_START_2_DEFAULT_MASK _MK_MASK_CONST(0x7fff) +#define SOR_NV_PDISP_HEAD_STATE5_0_VBLANK_START_2_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_HEAD_STATE5_0_VBLANK_START_2_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register SOR_NV_PDISP_HEAD_STATE5 +#define SOR_NV_PDISP_HEAD_STATE5 _MK_ADDR_CONST(0xf) +#define SOR_NV_PDISP_HEAD_STATE5_SECURE 0x0 +#define SOR_NV_PDISP_HEAD_STATE5_WORD_COUNT 0x1 +#define SOR_NV_PDISP_HEAD_STATE5_RESET_VAL _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_HEAD_STATE5_RESET_MASK _MK_MASK_CONST(0x7fff7fff) +#define SOR_NV_PDISP_HEAD_STATE5_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_HEAD_STATE5_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_HEAD_STATE5_READ_MASK _MK_MASK_CONST(0x7fff7fff) +#define SOR_NV_PDISP_HEAD_STATE5_WRITE_MASK _MK_MASK_CONST(0x7fff7fff) +#define SOR_NV_PDISP_HEAD_STATE5_VBLANK_END_2_SHIFT _MK_SHIFT_CONST(16) +#define SOR_NV_PDISP_HEAD_STATE5_VBLANK_END_2_FIELD _MK_FIELD_CONST(0x7fff, SOR_NV_PDISP_HEAD_STATE5_VBLANK_END_2_SHIFT) +#define SOR_NV_PDISP_HEAD_STATE5_VBLANK_END_2_RANGE 30:16 +#define SOR_NV_PDISP_HEAD_STATE5_VBLANK_END_2_WOFFSET 0x0 +#define SOR_NV_PDISP_HEAD_STATE5_VBLANK_END_2_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_HEAD_STATE5_VBLANK_END_2_DEFAULT_MASK _MK_MASK_CONST(0x7fff) +#define SOR_NV_PDISP_HEAD_STATE5_VBLANK_END_2_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_HEAD_STATE5_VBLANK_END_2_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define SOR_NV_PDISP_HEAD_STATE5_VBLANK_START_2_SHIFT _MK_SHIFT_CONST(0) +#define SOR_NV_PDISP_HEAD_STATE5_VBLANK_START_2_FIELD _MK_FIELD_CONST(0x7fff, SOR_NV_PDISP_HEAD_STATE5_VBLANK_START_2_SHIFT) +#define SOR_NV_PDISP_HEAD_STATE5_VBLANK_START_2_RANGE 14:0 +#define SOR_NV_PDISP_HEAD_STATE5_VBLANK_START_2_WOFFSET 0x0 +#define SOR_NV_PDISP_HEAD_STATE5_VBLANK_START_2_DEFAULT _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_HEAD_STATE5_VBLANK_START_2_DEFAULT_MASK _MK_MASK_CONST(0x7fff) +#define SOR_NV_PDISP_HEAD_STATE5_VBLANK_START_2_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_HEAD_STATE5_VBLANK_START_2_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register SOR_NV_PDISP_HEAD_STATE5_1 +#define SOR_NV_PDISP_HEAD_STATE5_1 _MK_ADDR_CONST(0x10) +#define SOR_NV_PDISP_HEAD_STATE5_1_SECURE 0x0 +#define SOR_NV_PDISP_HEAD_STATE5_1_WORD_COUNT 0x1 +#define SOR_NV_PDISP_HEAD_STATE5_1_RESET_VAL _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_HEAD_STATE5_1_RESET_MASK _MK_MASK_CONST(0x7fff7fff) +#define SOR_NV_PDISP_HEAD_STATE5_1_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_HEAD_STATE5_1_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_HEAD_STATE5_1_READ_MASK _MK_MASK_CONST(0x7fff7fff) +#define SOR_NV_PDISP_HEAD_STATE5_1_WRITE_MASK _MK_MASK_CONST(0x7fff7fff) +#define SOR_NV_PDISP_HEAD_STATE5_1_VBLANK_END_2_SHIFT _MK_SHIFT_CONST(16) +#define SOR_NV_PDISP_HEAD_STATE5_1_VBLANK_END_2_FIELD _MK_FIELD_CONST(0x7fff, SOR_NV_PDISP_HEAD_STATE5_1_VBLANK_END_2_SHIFT) +#define SOR_NV_PDISP_HEAD_STATE5_1_VBLANK_END_2_RANGE 30:16 +#define SOR_NV_PDISP_HEAD_STATE5_1_VBLANK_END_2_WOFFSET 0x0 +#define SOR_NV_PDISP_HEAD_STATE5_1_VBLANK_END_2_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_HEAD_STATE5_1_VBLANK_END_2_DEFAULT_MASK _MK_MASK_CONST(0x7fff) +#define SOR_NV_PDISP_HEAD_STATE5_1_VBLANK_END_2_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_HEAD_STATE5_1_VBLANK_END_2_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define SOR_NV_PDISP_HEAD_STATE5_1_VBLANK_START_2_SHIFT _MK_SHIFT_CONST(0) +#define SOR_NV_PDISP_HEAD_STATE5_1_VBLANK_START_2_FIELD _MK_FIELD_CONST(0x7fff, SOR_NV_PDISP_HEAD_STATE5_1_VBLANK_START_2_SHIFT) +#define SOR_NV_PDISP_HEAD_STATE5_1_VBLANK_START_2_RANGE 14:0 +#define SOR_NV_PDISP_HEAD_STATE5_1_VBLANK_START_2_WOFFSET 0x0 +#define SOR_NV_PDISP_HEAD_STATE5_1_VBLANK_START_2_DEFAULT _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_HEAD_STATE5_1_VBLANK_START_2_DEFAULT_MASK _MK_MASK_CONST(0x7fff) +#define SOR_NV_PDISP_HEAD_STATE5_1_VBLANK_START_2_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_HEAD_STATE5_1_VBLANK_START_2_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register SOR_NV_PDISP_SOR_CRC_CNTRL_0 +#define SOR_NV_PDISP_SOR_CRC_CNTRL_0 _MK_ADDR_CONST(0x11) +#define SOR_NV_PDISP_SOR_CRC_CNTRL_0_SECURE 0x0 +#define SOR_NV_PDISP_SOR_CRC_CNTRL_0_WORD_COUNT 0x1 +#define SOR_NV_PDISP_SOR_CRC_CNTRL_0_RESET_VAL _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_CRC_CNTRL_0_RESET_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_CRC_CNTRL_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_CRC_CNTRL_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_CRC_CNTRL_0_READ_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_CRC_CNTRL_0_WRITE_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_CRC_CNTRL_0_ARM_CRC_ENABLE_SHIFT _MK_SHIFT_CONST(0) +#define SOR_NV_PDISP_SOR_CRC_CNTRL_0_ARM_CRC_ENABLE_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_CRC_CNTRL_0_ARM_CRC_ENABLE_SHIFT) +#define SOR_NV_PDISP_SOR_CRC_CNTRL_0_ARM_CRC_ENABLE_RANGE 0:0 +#define SOR_NV_PDISP_SOR_CRC_CNTRL_0_ARM_CRC_ENABLE_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_CRC_CNTRL_0_ARM_CRC_ENABLE_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_CRC_CNTRL_0_ARM_CRC_ENABLE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_CRC_CNTRL_0_ARM_CRC_ENABLE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_CRC_CNTRL_0_ARM_CRC_ENABLE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_CRC_CNTRL_0_ARM_CRC_ENABLE_INIT_ENUM NO +#define SOR_NV_PDISP_SOR_CRC_CNTRL_0_ARM_CRC_ENABLE_NO _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_CRC_CNTRL_0_ARM_CRC_ENABLE_YES _MK_ENUM_CONST(1) +#define SOR_NV_PDISP_SOR_CRC_CNTRL_0_ARM_CRC_ENABLE_DIS _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_CRC_CNTRL_0_ARM_CRC_ENABLE_EN _MK_ENUM_CONST(1) + + +// Register SOR_NV_PDISP_SOR_DP_DEBUG_MVID_0 +#define SOR_NV_PDISP_SOR_DP_DEBUG_MVID_0 _MK_ADDR_CONST(0x12) +#define SOR_NV_PDISP_SOR_DP_DEBUG_MVID_0_SECURE 0x0 +#define SOR_NV_PDISP_SOR_DP_DEBUG_MVID_0_WORD_COUNT 0x1 +#define SOR_NV_PDISP_SOR_DP_DEBUG_MVID_0_RESET_VAL _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_DEBUG_MVID_0_RESET_MASK _MK_MASK_CONST(0xffffff) +#define SOR_NV_PDISP_SOR_DP_DEBUG_MVID_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_DEBUG_MVID_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_DEBUG_MVID_0_READ_MASK _MK_MASK_CONST(0xffffff) +#define SOR_NV_PDISP_SOR_DP_DEBUG_MVID_0_WRITE_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_DEBUG_MVID_0_VALUE_SHIFT _MK_SHIFT_CONST(0) +#define SOR_NV_PDISP_SOR_DP_DEBUG_MVID_0_VALUE_FIELD _MK_FIELD_CONST(0xffffff, SOR_NV_PDISP_SOR_DP_DEBUG_MVID_0_VALUE_SHIFT) +#define SOR_NV_PDISP_SOR_DP_DEBUG_MVID_0_VALUE_RANGE 23:0 +#define SOR_NV_PDISP_SOR_DP_DEBUG_MVID_0_VALUE_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_DP_DEBUG_MVID_0_VALUE_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_DEBUG_MVID_0_VALUE_DEFAULT_MASK _MK_MASK_CONST(0xffffff) +#define SOR_NV_PDISP_SOR_DP_DEBUG_MVID_0_VALUE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_DEBUG_MVID_0_VALUE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register SOR_NV_PDISP_SOR_CLK_CNTRL_0 +#define SOR_NV_PDISP_SOR_CLK_CNTRL_0 _MK_ADDR_CONST(0x13) +#define SOR_NV_PDISP_SOR_CLK_CNTRL_0_SECURE 0x0 +#define SOR_NV_PDISP_SOR_CLK_CNTRL_0_WORD_COUNT 0x1 +#define SOR_NV_PDISP_SOR_CLK_CNTRL_0_RESET_VAL _MK_MASK_CONST(0x18) +#define SOR_NV_PDISP_SOR_CLK_CNTRL_0_RESET_MASK _MK_MASK_CONST(0x7f) +#define SOR_NV_PDISP_SOR_CLK_CNTRL_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_CLK_CNTRL_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_CLK_CNTRL_0_READ_MASK _MK_MASK_CONST(0x7f) +#define SOR_NV_PDISP_SOR_CLK_CNTRL_0_WRITE_MASK _MK_MASK_CONST(0x7f) +#define SOR_NV_PDISP_SOR_CLK_CNTRL_0_DP_CLK_SEL_SHIFT _MK_SHIFT_CONST(0) +#define SOR_NV_PDISP_SOR_CLK_CNTRL_0_DP_CLK_SEL_FIELD _MK_FIELD_CONST(0x3, SOR_NV_PDISP_SOR_CLK_CNTRL_0_DP_CLK_SEL_SHIFT) +#define SOR_NV_PDISP_SOR_CLK_CNTRL_0_DP_CLK_SEL_RANGE 1:0 +#define SOR_NV_PDISP_SOR_CLK_CNTRL_0_DP_CLK_SEL_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_CLK_CNTRL_0_DP_CLK_SEL_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_CLK_CNTRL_0_DP_CLK_SEL_DEFAULT_MASK _MK_MASK_CONST(0x3) +#define SOR_NV_PDISP_SOR_CLK_CNTRL_0_DP_CLK_SEL_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_CLK_CNTRL_0_DP_CLK_SEL_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_CLK_CNTRL_0_DP_CLK_SEL_INIT_ENUM SINGLE_PCLK +#define SOR_NV_PDISP_SOR_CLK_CNTRL_0_DP_CLK_SEL_SINGLE_PCLK _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_CLK_CNTRL_0_DP_CLK_SEL_DIFF_PCLK _MK_ENUM_CONST(1) +#define SOR_NV_PDISP_SOR_CLK_CNTRL_0_DP_CLK_SEL_SINGLE_DPCLK _MK_ENUM_CONST(2) +#define SOR_NV_PDISP_SOR_CLK_CNTRL_0_DP_CLK_SEL_DIFF_DPCLK _MK_ENUM_CONST(3) + +#define SOR_NV_PDISP_SOR_CLK_CNTRL_0_DP_LINK_SPEED_SHIFT _MK_SHIFT_CONST(2) +#define SOR_NV_PDISP_SOR_CLK_CNTRL_0_DP_LINK_SPEED_FIELD _MK_FIELD_CONST(0x1f, SOR_NV_PDISP_SOR_CLK_CNTRL_0_DP_LINK_SPEED_SHIFT) +#define SOR_NV_PDISP_SOR_CLK_CNTRL_0_DP_LINK_SPEED_RANGE 6:2 +#define SOR_NV_PDISP_SOR_CLK_CNTRL_0_DP_LINK_SPEED_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_CLK_CNTRL_0_DP_LINK_SPEED_DEFAULT _MK_MASK_CONST(0x6) +#define SOR_NV_PDISP_SOR_CLK_CNTRL_0_DP_LINK_SPEED_DEFAULT_MASK _MK_MASK_CONST(0x1f) +#define SOR_NV_PDISP_SOR_CLK_CNTRL_0_DP_LINK_SPEED_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_CLK_CNTRL_0_DP_LINK_SPEED_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_CLK_CNTRL_0_DP_LINK_SPEED_INIT_ENUM G1_62 +#define SOR_NV_PDISP_SOR_CLK_CNTRL_0_DP_LINK_SPEED_G1_62 _MK_ENUM_CONST(6) +#define SOR_NV_PDISP_SOR_CLK_CNTRL_0_DP_LINK_SPEED_G2_7 _MK_ENUM_CONST(10) +#define SOR_NV_PDISP_SOR_CLK_CNTRL_0_DP_LINK_SPEED_LVDS _MK_ENUM_CONST(7) +#define SOR_NV_PDISP_SOR_CLK_CNTRL_0_DP_LINK_SPEED_G5_4 _MK_ENUM_CONST(20) + + +// Register SOR_NV_PDISP_SOR_CAP_0 +#define SOR_NV_PDISP_SOR_CAP_0 _MK_ADDR_CONST(0x14) +#define SOR_NV_PDISP_SOR_CAP_0_SECURE 0x0 +#define SOR_NV_PDISP_SOR_CAP_0_WORD_COUNT 0x1 +#define SOR_NV_PDISP_SOR_CAP_0_RESET_VAL _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_CAP_0_RESET_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_CAP_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_CAP_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_CAP_0_READ_MASK _MK_MASK_CONST(0x83113f0f) +#define SOR_NV_PDISP_SOR_CAP_0_WRITE_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_CAP_0_SINGLE_LVDS_18_SHIFT _MK_SHIFT_CONST(0) +#define SOR_NV_PDISP_SOR_CAP_0_SINGLE_LVDS_18_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_CAP_0_SINGLE_LVDS_18_SHIFT) +#define SOR_NV_PDISP_SOR_CAP_0_SINGLE_LVDS_18_RANGE 0:0 +#define SOR_NV_PDISP_SOR_CAP_0_SINGLE_LVDS_18_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_CAP_0_SINGLE_LVDS_18_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_CAP_0_SINGLE_LVDS_18_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_CAP_0_SINGLE_LVDS_18_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_CAP_0_SINGLE_LVDS_18_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_CAP_0_SINGLE_LVDS_18_FALSE _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_CAP_0_SINGLE_LVDS_18_TRUE _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_CAP_0_SINGLE_LVDS_24_SHIFT _MK_SHIFT_CONST(1) +#define SOR_NV_PDISP_SOR_CAP_0_SINGLE_LVDS_24_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_CAP_0_SINGLE_LVDS_24_SHIFT) +#define SOR_NV_PDISP_SOR_CAP_0_SINGLE_LVDS_24_RANGE 1:1 +#define SOR_NV_PDISP_SOR_CAP_0_SINGLE_LVDS_24_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_CAP_0_SINGLE_LVDS_24_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_CAP_0_SINGLE_LVDS_24_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_CAP_0_SINGLE_LVDS_24_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_CAP_0_SINGLE_LVDS_24_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_CAP_0_SINGLE_LVDS_24_FALSE _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_CAP_0_SINGLE_LVDS_24_TRUE _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_CAP_0_DUAL_LVDS_18_SHIFT _MK_SHIFT_CONST(2) +#define SOR_NV_PDISP_SOR_CAP_0_DUAL_LVDS_18_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_CAP_0_DUAL_LVDS_18_SHIFT) +#define SOR_NV_PDISP_SOR_CAP_0_DUAL_LVDS_18_RANGE 2:2 +#define SOR_NV_PDISP_SOR_CAP_0_DUAL_LVDS_18_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_CAP_0_DUAL_LVDS_18_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_CAP_0_DUAL_LVDS_18_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_CAP_0_DUAL_LVDS_18_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_CAP_0_DUAL_LVDS_18_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_CAP_0_DUAL_LVDS_18_FALSE _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_CAP_0_DUAL_LVDS_18_TRUE _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_CAP_0_DUAL_LVDS_24_SHIFT _MK_SHIFT_CONST(3) +#define SOR_NV_PDISP_SOR_CAP_0_DUAL_LVDS_24_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_CAP_0_DUAL_LVDS_24_SHIFT) +#define SOR_NV_PDISP_SOR_CAP_0_DUAL_LVDS_24_RANGE 3:3 +#define SOR_NV_PDISP_SOR_CAP_0_DUAL_LVDS_24_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_CAP_0_DUAL_LVDS_24_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_CAP_0_DUAL_LVDS_24_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_CAP_0_DUAL_LVDS_24_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_CAP_0_DUAL_LVDS_24_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_CAP_0_DUAL_LVDS_24_FALSE _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_CAP_0_DUAL_LVDS_24_TRUE _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_CAP_0_SINGLE_TMDS_A_SHIFT _MK_SHIFT_CONST(8) +#define SOR_NV_PDISP_SOR_CAP_0_SINGLE_TMDS_A_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_CAP_0_SINGLE_TMDS_A_SHIFT) +#define SOR_NV_PDISP_SOR_CAP_0_SINGLE_TMDS_A_RANGE 8:8 +#define SOR_NV_PDISP_SOR_CAP_0_SINGLE_TMDS_A_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_CAP_0_SINGLE_TMDS_A_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_CAP_0_SINGLE_TMDS_A_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_CAP_0_SINGLE_TMDS_A_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_CAP_0_SINGLE_TMDS_A_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_CAP_0_SINGLE_TMDS_A_FALSE _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_CAP_0_SINGLE_TMDS_A_TRUE _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_CAP_0_SINGLE_TMDS_B_SHIFT _MK_SHIFT_CONST(9) +#define SOR_NV_PDISP_SOR_CAP_0_SINGLE_TMDS_B_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_CAP_0_SINGLE_TMDS_B_SHIFT) +#define SOR_NV_PDISP_SOR_CAP_0_SINGLE_TMDS_B_RANGE 9:9 +#define SOR_NV_PDISP_SOR_CAP_0_SINGLE_TMDS_B_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_CAP_0_SINGLE_TMDS_B_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_CAP_0_SINGLE_TMDS_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_CAP_0_SINGLE_TMDS_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_CAP_0_SINGLE_TMDS_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_CAP_0_SINGLE_TMDS_B_FALSE _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_CAP_0_SINGLE_TMDS_B_TRUE _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_CAP_0_DUAL_SINGLE_TMDS_SHIFT _MK_SHIFT_CONST(10) +#define SOR_NV_PDISP_SOR_CAP_0_DUAL_SINGLE_TMDS_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_CAP_0_DUAL_SINGLE_TMDS_SHIFT) +#define SOR_NV_PDISP_SOR_CAP_0_DUAL_SINGLE_TMDS_RANGE 10:10 +#define SOR_NV_PDISP_SOR_CAP_0_DUAL_SINGLE_TMDS_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_CAP_0_DUAL_SINGLE_TMDS_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_CAP_0_DUAL_SINGLE_TMDS_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_CAP_0_DUAL_SINGLE_TMDS_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_CAP_0_DUAL_SINGLE_TMDS_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_CAP_0_DUAL_SINGLE_TMDS_FALSE _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_CAP_0_DUAL_SINGLE_TMDS_TRUE _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_CAP_0_DUAL_TMDS_SHIFT _MK_SHIFT_CONST(11) +#define SOR_NV_PDISP_SOR_CAP_0_DUAL_TMDS_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_CAP_0_DUAL_TMDS_SHIFT) +#define SOR_NV_PDISP_SOR_CAP_0_DUAL_TMDS_RANGE 11:11 +#define SOR_NV_PDISP_SOR_CAP_0_DUAL_TMDS_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_CAP_0_DUAL_TMDS_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_CAP_0_DUAL_TMDS_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_CAP_0_DUAL_TMDS_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_CAP_0_DUAL_TMDS_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_CAP_0_DUAL_TMDS_FALSE _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_CAP_0_DUAL_TMDS_TRUE _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_CAP_0_SINGLE_TMDS_225_MHZ_SHIFT _MK_SHIFT_CONST(12) +#define SOR_NV_PDISP_SOR_CAP_0_SINGLE_TMDS_225_MHZ_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_CAP_0_SINGLE_TMDS_225_MHZ_SHIFT) +#define SOR_NV_PDISP_SOR_CAP_0_SINGLE_TMDS_225_MHZ_RANGE 12:12 +#define SOR_NV_PDISP_SOR_CAP_0_SINGLE_TMDS_225_MHZ_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_CAP_0_SINGLE_TMDS_225_MHZ_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_CAP_0_SINGLE_TMDS_225_MHZ_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_CAP_0_SINGLE_TMDS_225_MHZ_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_CAP_0_SINGLE_TMDS_225_MHZ_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_CAP_0_SINGLE_TMDS_225_MHZ_FALSE _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_CAP_0_SINGLE_TMDS_225_MHZ_TRUE _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_CAP_0_DISPLAY_OVER_PCIE_SHIFT _MK_SHIFT_CONST(13) +#define SOR_NV_PDISP_SOR_CAP_0_DISPLAY_OVER_PCIE_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_CAP_0_DISPLAY_OVER_PCIE_SHIFT) +#define SOR_NV_PDISP_SOR_CAP_0_DISPLAY_OVER_PCIE_RANGE 13:13 +#define SOR_NV_PDISP_SOR_CAP_0_DISPLAY_OVER_PCIE_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_CAP_0_DISPLAY_OVER_PCIE_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_CAP_0_DISPLAY_OVER_PCIE_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_CAP_0_DISPLAY_OVER_PCIE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_CAP_0_DISPLAY_OVER_PCIE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_CAP_0_DISPLAY_OVER_PCIE_FALSE _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_CAP_0_DISPLAY_OVER_PCIE_TRUE _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_CAP_0_SDI_SHIFT _MK_SHIFT_CONST(16) +#define SOR_NV_PDISP_SOR_CAP_0_SDI_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_CAP_0_SDI_SHIFT) +#define SOR_NV_PDISP_SOR_CAP_0_SDI_RANGE 16:16 +#define SOR_NV_PDISP_SOR_CAP_0_SDI_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_CAP_0_SDI_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_CAP_0_SDI_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_CAP_0_SDI_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_CAP_0_SDI_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_CAP_0_SDI_FALSE _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_CAP_0_SDI_TRUE _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_CAP_0_DDI_SHIFT _MK_SHIFT_CONST(20) +#define SOR_NV_PDISP_SOR_CAP_0_DDI_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_CAP_0_DDI_SHIFT) +#define SOR_NV_PDISP_SOR_CAP_0_DDI_RANGE 20:20 +#define SOR_NV_PDISP_SOR_CAP_0_DDI_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_CAP_0_DDI_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_CAP_0_DDI_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_CAP_0_DDI_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_CAP_0_DDI_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_CAP_0_DDI_FALSE _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_CAP_0_DDI_TRUE _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_CAP_0_DP_A_SHIFT _MK_SHIFT_CONST(24) +#define SOR_NV_PDISP_SOR_CAP_0_DP_A_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_CAP_0_DP_A_SHIFT) +#define SOR_NV_PDISP_SOR_CAP_0_DP_A_RANGE 24:24 +#define SOR_NV_PDISP_SOR_CAP_0_DP_A_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_CAP_0_DP_A_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_CAP_0_DP_A_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_CAP_0_DP_A_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_CAP_0_DP_A_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_CAP_0_DP_A_FALSE _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_CAP_0_DP_A_TRUE _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_CAP_0_DP_B_SHIFT _MK_SHIFT_CONST(25) +#define SOR_NV_PDISP_SOR_CAP_0_DP_B_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_CAP_0_DP_B_SHIFT) +#define SOR_NV_PDISP_SOR_CAP_0_DP_B_RANGE 25:25 +#define SOR_NV_PDISP_SOR_CAP_0_DP_B_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_CAP_0_DP_B_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_CAP_0_DP_B_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_CAP_0_DP_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_CAP_0_DP_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_CAP_0_DP_B_FALSE _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_CAP_0_DP_B_TRUE _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_CAP_0_LVDS_ONLY_SHIFT _MK_SHIFT_CONST(31) +#define SOR_NV_PDISP_SOR_CAP_0_LVDS_ONLY_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_CAP_0_LVDS_ONLY_SHIFT) +#define SOR_NV_PDISP_SOR_CAP_0_LVDS_ONLY_RANGE 31:31 +#define SOR_NV_PDISP_SOR_CAP_0_LVDS_ONLY_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_CAP_0_LVDS_ONLY_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_CAP_0_LVDS_ONLY_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_CAP_0_LVDS_ONLY_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_CAP_0_LVDS_ONLY_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_CAP_0_LVDS_ONLY_FALSE _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_CAP_0_LVDS_ONLY_TRUE _MK_ENUM_CONST(1) + + +// Register SOR_NV_PDISP_SOR_PWR_0 +#define SOR_NV_PDISP_SOR_PWR_0 _MK_ADDR_CONST(0x15) +#define SOR_NV_PDISP_SOR_PWR_0_SECURE 0x0 +#define SOR_NV_PDISP_SOR_PWR_0_WORD_COUNT 0x1 +#define SOR_NV_PDISP_SOR_PWR_0_RESET_VAL _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_PWR_0_RESET_MASK _MK_MASK_CONST(0x80030003) +#define SOR_NV_PDISP_SOR_PWR_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_PWR_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_PWR_0_READ_MASK _MK_MASK_CONST(0x91030003) +#define SOR_NV_PDISP_SOR_PWR_0_WRITE_MASK _MK_MASK_CONST(0x80030003) +#define SOR_NV_PDISP_SOR_PWR_0_SETTING_NEW_SHIFT _MK_SHIFT_CONST(31) +#define SOR_NV_PDISP_SOR_PWR_0_SETTING_NEW_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_PWR_0_SETTING_NEW_SHIFT) +#define SOR_NV_PDISP_SOR_PWR_0_SETTING_NEW_RANGE 31:31 +#define SOR_NV_PDISP_SOR_PWR_0_SETTING_NEW_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_PWR_0_SETTING_NEW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_PWR_0_SETTING_NEW_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_PWR_0_SETTING_NEW_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_PWR_0_SETTING_NEW_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_PWR_0_SETTING_NEW_INIT_ENUM DONE +#define SOR_NV_PDISP_SOR_PWR_0_SETTING_NEW_DONE _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_PWR_0_SETTING_NEW_PENDING _MK_ENUM_CONST(1) +#define SOR_NV_PDISP_SOR_PWR_0_SETTING_NEW_TRIGGER _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_PWR_0_MODE_SHIFT _MK_SHIFT_CONST(28) +#define SOR_NV_PDISP_SOR_PWR_0_MODE_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_PWR_0_MODE_SHIFT) +#define SOR_NV_PDISP_SOR_PWR_0_MODE_RANGE 28:28 +#define SOR_NV_PDISP_SOR_PWR_0_MODE_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_PWR_0_MODE_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_PWR_0_MODE_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_PWR_0_MODE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_PWR_0_MODE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_PWR_0_MODE_NORMAL _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_PWR_0_MODE_SAFE _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_PWR_0_HALT_DELAY_SHIFT _MK_SHIFT_CONST(24) +#define SOR_NV_PDISP_SOR_PWR_0_HALT_DELAY_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_PWR_0_HALT_DELAY_SHIFT) +#define SOR_NV_PDISP_SOR_PWR_0_HALT_DELAY_RANGE 24:24 +#define SOR_NV_PDISP_SOR_PWR_0_HALT_DELAY_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_PWR_0_HALT_DELAY_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_PWR_0_HALT_DELAY_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_PWR_0_HALT_DELAY_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_PWR_0_HALT_DELAY_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_PWR_0_HALT_DELAY_DONE _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_PWR_0_HALT_DELAY_ACTIVE _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_PWR_0_SAFE_START_SHIFT _MK_SHIFT_CONST(17) +#define SOR_NV_PDISP_SOR_PWR_0_SAFE_START_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_PWR_0_SAFE_START_SHIFT) +#define SOR_NV_PDISP_SOR_PWR_0_SAFE_START_RANGE 17:17 +#define SOR_NV_PDISP_SOR_PWR_0_SAFE_START_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_PWR_0_SAFE_START_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_PWR_0_SAFE_START_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_PWR_0_SAFE_START_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_PWR_0_SAFE_START_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_PWR_0_SAFE_START_INIT_ENUM NORMAL +#define SOR_NV_PDISP_SOR_PWR_0_SAFE_START_NORMAL _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_PWR_0_SAFE_START_ALT _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_PWR_0_SAFE_STATE_SHIFT _MK_SHIFT_CONST(16) +#define SOR_NV_PDISP_SOR_PWR_0_SAFE_STATE_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_PWR_0_SAFE_STATE_SHIFT) +#define SOR_NV_PDISP_SOR_PWR_0_SAFE_STATE_RANGE 16:16 +#define SOR_NV_PDISP_SOR_PWR_0_SAFE_STATE_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_PWR_0_SAFE_STATE_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_PWR_0_SAFE_STATE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_PWR_0_SAFE_STATE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_PWR_0_SAFE_STATE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_PWR_0_SAFE_STATE_INIT_ENUM PD +#define SOR_NV_PDISP_SOR_PWR_0_SAFE_STATE_PD _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_PWR_0_SAFE_STATE_PU _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_PWR_0_NORMAL_START_SHIFT _MK_SHIFT_CONST(1) +#define SOR_NV_PDISP_SOR_PWR_0_NORMAL_START_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_PWR_0_NORMAL_START_SHIFT) +#define SOR_NV_PDISP_SOR_PWR_0_NORMAL_START_RANGE 1:1 +#define SOR_NV_PDISP_SOR_PWR_0_NORMAL_START_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_PWR_0_NORMAL_START_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_PWR_0_NORMAL_START_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_PWR_0_NORMAL_START_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_PWR_0_NORMAL_START_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_PWR_0_NORMAL_START_INIT_ENUM NORMAL +#define SOR_NV_PDISP_SOR_PWR_0_NORMAL_START_NORMAL _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_PWR_0_NORMAL_START_ALT _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_PWR_0_NORMAL_STATE_SHIFT _MK_SHIFT_CONST(0) +#define SOR_NV_PDISP_SOR_PWR_0_NORMAL_STATE_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_PWR_0_NORMAL_STATE_SHIFT) +#define SOR_NV_PDISP_SOR_PWR_0_NORMAL_STATE_RANGE 0:0 +#define SOR_NV_PDISP_SOR_PWR_0_NORMAL_STATE_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_PWR_0_NORMAL_STATE_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_PWR_0_NORMAL_STATE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_PWR_0_NORMAL_STATE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_PWR_0_NORMAL_STATE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_PWR_0_NORMAL_STATE_INIT_ENUM PD +#define SOR_NV_PDISP_SOR_PWR_0_NORMAL_STATE_PD _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_PWR_0_NORMAL_STATE_PU _MK_ENUM_CONST(1) + + +// Register SOR_NV_PDISP_SOR_TEST_0 +#define SOR_NV_PDISP_SOR_TEST_0 _MK_ADDR_CONST(0x16) +#define SOR_NV_PDISP_SOR_TEST_0_SECURE 0x0 +#define SOR_NV_PDISP_SOR_TEST_0_WORD_COUNT 0x1 +#define SOR_NV_PDISP_SOR_TEST_0_RESET_VAL _MK_MASK_CONST(0x800000) +#define SOR_NV_PDISP_SOR_TEST_0_RESET_MASK _MK_MASK_CONST(0xfff30042) +#define SOR_NV_PDISP_SOR_TEST_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_TEST_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_TEST_0_READ_MASK _MK_MASK_CONST(0xfff3f742) +#define SOR_NV_PDISP_SOR_TEST_0_WRITE_MASK _MK_MASK_CONST(0xfff30042) +#define SOR_NV_PDISP_SOR_TEST_0_TESTMUX_SHIFT _MK_SHIFT_CONST(24) +#define SOR_NV_PDISP_SOR_TEST_0_TESTMUX_FIELD _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_TEST_0_TESTMUX_SHIFT) +#define SOR_NV_PDISP_SOR_TEST_0_TESTMUX_RANGE 31:24 +#define SOR_NV_PDISP_SOR_TEST_0_TESTMUX_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_TEST_0_TESTMUX_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_TEST_0_TESTMUX_DEFAULT_MASK _MK_MASK_CONST(0xff) +#define SOR_NV_PDISP_SOR_TEST_0_TESTMUX_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_TEST_0_TESTMUX_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_TEST_0_TESTMUX_INIT_ENUM AVSS +#define SOR_NV_PDISP_SOR_TEST_0_TESTMUX_AVSS _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_TEST_0_TESTMUX_CLOCKIN _MK_ENUM_CONST(2) +#define SOR_NV_PDISP_SOR_TEST_0_TESTMUX_PLL_VOL _MK_ENUM_CONST(4) +#define SOR_NV_PDISP_SOR_TEST_0_TESTMUX_SLOWCLKINT _MK_ENUM_CONST(8) +#define SOR_NV_PDISP_SOR_TEST_0_TESTMUX_AVDD _MK_ENUM_CONST(16) +#define SOR_NV_PDISP_SOR_TEST_0_TESTMUX_VDDREG _MK_ENUM_CONST(32) +#define SOR_NV_PDISP_SOR_TEST_0_TESTMUX_REGREF_VDDREG _MK_ENUM_CONST(64) +#define SOR_NV_PDISP_SOR_TEST_0_TESTMUX_REGREF_AVDD _MK_ENUM_CONST(128) + +#define SOR_NV_PDISP_SOR_TEST_0_CRC_SHIFT _MK_SHIFT_CONST(23) +#define SOR_NV_PDISP_SOR_TEST_0_CRC_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_TEST_0_CRC_SHIFT) +#define SOR_NV_PDISP_SOR_TEST_0_CRC_RANGE 23:23 +#define SOR_NV_PDISP_SOR_TEST_0_CRC_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_TEST_0_CRC_DEFAULT _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_TEST_0_CRC_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_TEST_0_CRC_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_TEST_0_CRC_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_TEST_0_CRC_INIT_ENUM POST_DESERIALIZE +#define SOR_NV_PDISP_SOR_TEST_0_CRC_PRE_SERIALIZE _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_TEST_0_CRC_POST_DESERIALIZE _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_TEST_0_TPAT_SHIFT _MK_SHIFT_CONST(20) +#define SOR_NV_PDISP_SOR_TEST_0_TPAT_FIELD _MK_FIELD_CONST(0x7, SOR_NV_PDISP_SOR_TEST_0_TPAT_SHIFT) +#define SOR_NV_PDISP_SOR_TEST_0_TPAT_RANGE 22:20 +#define SOR_NV_PDISP_SOR_TEST_0_TPAT_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_TEST_0_TPAT_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_TEST_0_TPAT_DEFAULT_MASK _MK_MASK_CONST(0x7) +#define SOR_NV_PDISP_SOR_TEST_0_TPAT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_TEST_0_TPAT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_TEST_0_TPAT_INIT_ENUM LO +#define SOR_NV_PDISP_SOR_TEST_0_TPAT_LO _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_TEST_0_TPAT_TDAT _MK_ENUM_CONST(1) +#define SOR_NV_PDISP_SOR_TEST_0_TPAT_RAMP _MK_ENUM_CONST(2) +#define SOR_NV_PDISP_SOR_TEST_0_TPAT_WALK _MK_ENUM_CONST(3) +#define SOR_NV_PDISP_SOR_TEST_0_TPAT_MAXSTEP _MK_ENUM_CONST(4) +#define SOR_NV_PDISP_SOR_TEST_0_TPAT_MINSTEP _MK_ENUM_CONST(5) + +#define SOR_NV_PDISP_SOR_TEST_0_DSRC_SHIFT _MK_SHIFT_CONST(16) +#define SOR_NV_PDISP_SOR_TEST_0_DSRC_FIELD _MK_FIELD_CONST(0x3, SOR_NV_PDISP_SOR_TEST_0_DSRC_SHIFT) +#define SOR_NV_PDISP_SOR_TEST_0_DSRC_RANGE 17:16 +#define SOR_NV_PDISP_SOR_TEST_0_DSRC_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_TEST_0_DSRC_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_TEST_0_DSRC_DEFAULT_MASK _MK_MASK_CONST(0x3) +#define SOR_NV_PDISP_SOR_TEST_0_DSRC_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_TEST_0_DSRC_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_TEST_0_DSRC_INIT_ENUM NORMAL +#define SOR_NV_PDISP_SOR_TEST_0_DSRC_NORMAL _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_TEST_0_DSRC_DEBUG _MK_ENUM_CONST(1) +#define SOR_NV_PDISP_SOR_TEST_0_DSRC_TGEN _MK_ENUM_CONST(2) + +#define SOR_NV_PDISP_SOR_TEST_0_HEAD_NUMBER_SHIFT _MK_SHIFT_CONST(12) +#define SOR_NV_PDISP_SOR_TEST_0_HEAD_NUMBER_FIELD _MK_FIELD_CONST(0xf, SOR_NV_PDISP_SOR_TEST_0_HEAD_NUMBER_SHIFT) +#define SOR_NV_PDISP_SOR_TEST_0_HEAD_NUMBER_RANGE 15:12 +#define SOR_NV_PDISP_SOR_TEST_0_HEAD_NUMBER_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_TEST_0_HEAD_NUMBER_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_TEST_0_HEAD_NUMBER_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_TEST_0_HEAD_NUMBER_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_TEST_0_HEAD_NUMBER_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_TEST_0_HEAD_NUMBER_NONE _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_TEST_0_HEAD_NUMBER_HEAD0 _MK_ENUM_CONST(1) +#define SOR_NV_PDISP_SOR_TEST_0_HEAD_NUMBER_HEAD1 _MK_ENUM_CONST(2) + +#define SOR_NV_PDISP_SOR_TEST_0_ATTACHED_SHIFT _MK_SHIFT_CONST(10) +#define SOR_NV_PDISP_SOR_TEST_0_ATTACHED_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_TEST_0_ATTACHED_SHIFT) +#define SOR_NV_PDISP_SOR_TEST_0_ATTACHED_RANGE 10:10 +#define SOR_NV_PDISP_SOR_TEST_0_ATTACHED_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_TEST_0_ATTACHED_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_TEST_0_ATTACHED_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_TEST_0_ATTACHED_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_TEST_0_ATTACHED_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_TEST_0_ATTACHED_FALSE _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_TEST_0_ATTACHED_TRUE _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_TEST_0_ACT_HEAD_OPMODE_SHIFT _MK_SHIFT_CONST(8) +#define SOR_NV_PDISP_SOR_TEST_0_ACT_HEAD_OPMODE_FIELD _MK_FIELD_CONST(0x3, SOR_NV_PDISP_SOR_TEST_0_ACT_HEAD_OPMODE_SHIFT) +#define SOR_NV_PDISP_SOR_TEST_0_ACT_HEAD_OPMODE_RANGE 9:8 +#define SOR_NV_PDISP_SOR_TEST_0_ACT_HEAD_OPMODE_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_TEST_0_ACT_HEAD_OPMODE_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_TEST_0_ACT_HEAD_OPMODE_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_TEST_0_ACT_HEAD_OPMODE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_TEST_0_ACT_HEAD_OPMODE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_TEST_0_ACT_HEAD_OPMODE_SLEEP _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_TEST_0_ACT_HEAD_OPMODE_SNOOZE _MK_ENUM_CONST(1) +#define SOR_NV_PDISP_SOR_TEST_0_ACT_HEAD_OPMODE_AWAKE _MK_ENUM_CONST(2) + +#define SOR_NV_PDISP_SOR_TEST_0_INVD_SHIFT _MK_SHIFT_CONST(6) +#define SOR_NV_PDISP_SOR_TEST_0_INVD_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_TEST_0_INVD_SHIFT) +#define SOR_NV_PDISP_SOR_TEST_0_INVD_RANGE 6:6 +#define SOR_NV_PDISP_SOR_TEST_0_INVD_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_TEST_0_INVD_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_TEST_0_INVD_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_TEST_0_INVD_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_TEST_0_INVD_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_TEST_0_INVD_INIT_ENUM DISABLE +#define SOR_NV_PDISP_SOR_TEST_0_INVD_DISABLE _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_TEST_0_INVD_ENABLE _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_TEST_0_TEST_ENABLE_SHIFT _MK_SHIFT_CONST(1) +#define SOR_NV_PDISP_SOR_TEST_0_TEST_ENABLE_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_TEST_0_TEST_ENABLE_SHIFT) +#define SOR_NV_PDISP_SOR_TEST_0_TEST_ENABLE_RANGE 1:1 +#define SOR_NV_PDISP_SOR_TEST_0_TEST_ENABLE_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_TEST_0_TEST_ENABLE_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_TEST_0_TEST_ENABLE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_TEST_0_TEST_ENABLE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_TEST_0_TEST_ENABLE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_TEST_0_TEST_ENABLE_INIT_ENUM DISABLE +#define SOR_NV_PDISP_SOR_TEST_0_TEST_ENABLE_DISABLE _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_TEST_0_TEST_ENABLE_ENABLE _MK_ENUM_CONST(1) + + +// Register SOR_NV_PDISP_SOR_PLL0_0 +#define SOR_NV_PDISP_SOR_PLL0_0 _MK_ADDR_CONST(0x17) +#define SOR_NV_PDISP_SOR_PLL0_0_SECURE 0x0 +#define SOR_NV_PDISP_SOR_PLL0_0_WORD_COUNT 0x1 +#define SOR_NV_PDISP_SOR_PLL0_0_RESET_VAL _MK_MASK_CONST(0xf0003d5) +#define SOR_NV_PDISP_SOR_PLL0_0_RESET_MASK _MK_MASK_CONST(0xf0f3ff5) +#define SOR_NV_PDISP_SOR_PLL0_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_PLL0_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_PLL0_0_READ_MASK _MK_MASK_CONST(0xf0f3ff5) +#define SOR_NV_PDISP_SOR_PLL0_0_WRITE_MASK _MK_MASK_CONST(0xf0f3ff5) +#define SOR_NV_PDISP_SOR_PLL0_0_ICHPMP_SHIFT _MK_SHIFT_CONST(24) +#define SOR_NV_PDISP_SOR_PLL0_0_ICHPMP_FIELD _MK_FIELD_CONST(0xf, SOR_NV_PDISP_SOR_PLL0_0_ICHPMP_SHIFT) +#define SOR_NV_PDISP_SOR_PLL0_0_ICHPMP_RANGE 27:24 +#define SOR_NV_PDISP_SOR_PLL0_0_ICHPMP_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_PLL0_0_ICHPMP_DEFAULT _MK_MASK_CONST(0xf) +#define SOR_NV_PDISP_SOR_PLL0_0_ICHPMP_DEFAULT_MASK _MK_MASK_CONST(0xf) +#define SOR_NV_PDISP_SOR_PLL0_0_ICHPMP_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_PLL0_0_ICHPMP_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_PLL0_0_ICHPMP_INIT_ENUM RST +#define SOR_NV_PDISP_SOR_PLL0_0_ICHPMP_RST _MK_ENUM_CONST(15) + +#define SOR_NV_PDISP_SOR_PLL0_0_FILTER_SHIFT _MK_SHIFT_CONST(16) +#define SOR_NV_PDISP_SOR_PLL0_0_FILTER_FIELD _MK_FIELD_CONST(0xf, SOR_NV_PDISP_SOR_PLL0_0_FILTER_SHIFT) +#define SOR_NV_PDISP_SOR_PLL0_0_FILTER_RANGE 19:16 +#define SOR_NV_PDISP_SOR_PLL0_0_FILTER_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_PLL0_0_FILTER_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_PLL0_0_FILTER_DEFAULT_MASK _MK_MASK_CONST(0xf) +#define SOR_NV_PDISP_SOR_PLL0_0_FILTER_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_PLL0_0_FILTER_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_PLL0_0_FILTER_INIT_ENUM RST +#define SOR_NV_PDISP_SOR_PLL0_0_FILTER_RST _MK_ENUM_CONST(0) + +#define SOR_NV_PDISP_SOR_PLL0_0_TXREG_LEVEL_SHIFT _MK_SHIFT_CONST(12) +#define SOR_NV_PDISP_SOR_PLL0_0_TXREG_LEVEL_FIELD _MK_FIELD_CONST(0x3, SOR_NV_PDISP_SOR_PLL0_0_TXREG_LEVEL_SHIFT) +#define SOR_NV_PDISP_SOR_PLL0_0_TXREG_LEVEL_RANGE 13:12 +#define SOR_NV_PDISP_SOR_PLL0_0_TXREG_LEVEL_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_PLL0_0_TXREG_LEVEL_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_PLL0_0_TXREG_LEVEL_DEFAULT_MASK _MK_MASK_CONST(0x3) +#define SOR_NV_PDISP_SOR_PLL0_0_TXREG_LEVEL_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_PLL0_0_TXREG_LEVEL_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_PLL0_0_TXREG_LEVEL_INIT_ENUM V25 +#define SOR_NV_PDISP_SOR_PLL0_0_TXREG_LEVEL_V25 _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_PLL0_0_TXREG_LEVEL_V15 _MK_ENUM_CONST(1) +#define SOR_NV_PDISP_SOR_PLL0_0_TXREG_LEVEL_V35 _MK_ENUM_CONST(2) +#define SOR_NV_PDISP_SOR_PLL0_0_TXREG_LEVEL_V45 _MK_ENUM_CONST(3) + +#define SOR_NV_PDISP_SOR_PLL0_0_VCOCAP_SHIFT _MK_SHIFT_CONST(8) +#define SOR_NV_PDISP_SOR_PLL0_0_VCOCAP_FIELD _MK_FIELD_CONST(0xf, SOR_NV_PDISP_SOR_PLL0_0_VCOCAP_SHIFT) +#define SOR_NV_PDISP_SOR_PLL0_0_VCOCAP_RANGE 11:8 +#define SOR_NV_PDISP_SOR_PLL0_0_VCOCAP_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_PLL0_0_VCOCAP_DEFAULT _MK_MASK_CONST(0x3) +#define SOR_NV_PDISP_SOR_PLL0_0_VCOCAP_DEFAULT_MASK _MK_MASK_CONST(0xf) +#define SOR_NV_PDISP_SOR_PLL0_0_VCOCAP_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_PLL0_0_VCOCAP_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_PLL0_0_VCOCAP_INIT_ENUM RST +#define SOR_NV_PDISP_SOR_PLL0_0_VCOCAP_RST _MK_ENUM_CONST(3) + +#define SOR_NV_PDISP_SOR_PLL0_0_PLLREG_LEVEL_SHIFT _MK_SHIFT_CONST(6) +#define SOR_NV_PDISP_SOR_PLL0_0_PLLREG_LEVEL_FIELD _MK_FIELD_CONST(0x3, SOR_NV_PDISP_SOR_PLL0_0_PLLREG_LEVEL_SHIFT) +#define SOR_NV_PDISP_SOR_PLL0_0_PLLREG_LEVEL_RANGE 7:6 +#define SOR_NV_PDISP_SOR_PLL0_0_PLLREG_LEVEL_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_PLL0_0_PLLREG_LEVEL_DEFAULT _MK_MASK_CONST(0x3) +#define SOR_NV_PDISP_SOR_PLL0_0_PLLREG_LEVEL_DEFAULT_MASK _MK_MASK_CONST(0x3) +#define SOR_NV_PDISP_SOR_PLL0_0_PLLREG_LEVEL_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_PLL0_0_PLLREG_LEVEL_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_PLL0_0_PLLREG_LEVEL_INIT_ENUM V45 +#define SOR_NV_PDISP_SOR_PLL0_0_PLLREG_LEVEL_V25 _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_PLL0_0_PLLREG_LEVEL_V15 _MK_ENUM_CONST(1) +#define SOR_NV_PDISP_SOR_PLL0_0_PLLREG_LEVEL_V35 _MK_ENUM_CONST(2) +#define SOR_NV_PDISP_SOR_PLL0_0_PLLREG_LEVEL_V45 _MK_ENUM_CONST(3) + +#define SOR_NV_PDISP_SOR_PLL0_0_PULLDOWN_SHIFT _MK_SHIFT_CONST(5) +#define SOR_NV_PDISP_SOR_PLL0_0_PULLDOWN_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_PLL0_0_PULLDOWN_SHIFT) +#define SOR_NV_PDISP_SOR_PLL0_0_PULLDOWN_RANGE 5:5 +#define SOR_NV_PDISP_SOR_PLL0_0_PULLDOWN_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_PLL0_0_PULLDOWN_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_PLL0_0_PULLDOWN_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_PLL0_0_PULLDOWN_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_PLL0_0_PULLDOWN_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_PLL0_0_PULLDOWN_INIT_ENUM DISABLE +#define SOR_NV_PDISP_SOR_PLL0_0_PULLDOWN_DISABLE _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_PLL0_0_PULLDOWN_ENABLE _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_PLL0_0_RESISTORSEL_SHIFT _MK_SHIFT_CONST(4) +#define SOR_NV_PDISP_SOR_PLL0_0_RESISTORSEL_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_PLL0_0_RESISTORSEL_SHIFT) +#define SOR_NV_PDISP_SOR_PLL0_0_RESISTORSEL_RANGE 4:4 +#define SOR_NV_PDISP_SOR_PLL0_0_RESISTORSEL_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_PLL0_0_RESISTORSEL_DEFAULT _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_PLL0_0_RESISTORSEL_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_PLL0_0_RESISTORSEL_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_PLL0_0_RESISTORSEL_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_PLL0_0_RESISTORSEL_INIT_ENUM EXT +#define SOR_NV_PDISP_SOR_PLL0_0_RESISTORSEL_INT _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_PLL0_0_RESISTORSEL_EXT _MK_ENUM_CONST(1) +#define SOR_NV_PDISP_SOR_PLL0_0_RESISTORSEL_RST _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_PLL0_0_VCOPD_SHIFT _MK_SHIFT_CONST(2) +#define SOR_NV_PDISP_SOR_PLL0_0_VCOPD_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_PLL0_0_VCOPD_SHIFT) +#define SOR_NV_PDISP_SOR_PLL0_0_VCOPD_RANGE 2:2 +#define SOR_NV_PDISP_SOR_PLL0_0_VCOPD_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_PLL0_0_VCOPD_DEFAULT _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_PLL0_0_VCOPD_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_PLL0_0_VCOPD_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_PLL0_0_VCOPD_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_PLL0_0_VCOPD_INIT_ENUM ASSERT +#define SOR_NV_PDISP_SOR_PLL0_0_VCOPD_RESCIND _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_PLL0_0_VCOPD_ASSERT _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_PLL0_0_PWR_SHIFT _MK_SHIFT_CONST(0) +#define SOR_NV_PDISP_SOR_PLL0_0_PWR_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_PLL0_0_PWR_SHIFT) +#define SOR_NV_PDISP_SOR_PLL0_0_PWR_RANGE 0:0 +#define SOR_NV_PDISP_SOR_PLL0_0_PWR_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_PLL0_0_PWR_DEFAULT _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_PLL0_0_PWR_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_PLL0_0_PWR_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_PLL0_0_PWR_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_PLL0_0_PWR_INIT_ENUM OFF +#define SOR_NV_PDISP_SOR_PLL0_0_PWR_ON _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_PLL0_0_PWR_OFF _MK_ENUM_CONST(1) + + +// Register SOR_NV_PDISP_SOR_PLL1_0 +#define SOR_NV_PDISP_SOR_PLL1_0 _MK_ADDR_CONST(0x18) +#define SOR_NV_PDISP_SOR_PLL1_0_SECURE 0x0 +#define SOR_NV_PDISP_SOR_PLL1_0_WORD_COUNT 0x1 +#define SOR_NV_PDISP_SOR_PLL1_0_RESET_VAL _MK_MASK_CONST(0x1000) +#define SOR_NV_PDISP_SOR_PLL1_0_RESET_MASK _MK_MASK_CONST(0x23f01f3f) +#define SOR_NV_PDISP_SOR_PLL1_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_PLL1_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_PLL1_0_READ_MASK _MK_MASK_CONST(0x23f09f3f) +#define SOR_NV_PDISP_SOR_PLL1_0_WRITE_MASK _MK_MASK_CONST(0x23f01f3f) +#define SOR_NV_PDISP_SOR_PLL1_0_COHERENTMODE_SHIFT _MK_SHIFT_CONST(29) +#define SOR_NV_PDISP_SOR_PLL1_0_COHERENTMODE_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_PLL1_0_COHERENTMODE_SHIFT) +#define SOR_NV_PDISP_SOR_PLL1_0_COHERENTMODE_RANGE 29:29 +#define SOR_NV_PDISP_SOR_PLL1_0_COHERENTMODE_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_PLL1_0_COHERENTMODE_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_PLL1_0_COHERENTMODE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_PLL1_0_COHERENTMODE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_PLL1_0_COHERENTMODE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_PLL1_0_COHERENTMODE_INIT_ENUM DISABLE +#define SOR_NV_PDISP_SOR_PLL1_0_COHERENTMODE_DISABLE _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_PLL1_0_COHERENTMODE_ENABLE _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_PLL1_0_LVDSCM_SHIFT _MK_SHIFT_CONST(24) +#define SOR_NV_PDISP_SOR_PLL1_0_LVDSCM_FIELD _MK_FIELD_CONST(0x3, SOR_NV_PDISP_SOR_PLL1_0_LVDSCM_SHIFT) +#define SOR_NV_PDISP_SOR_PLL1_0_LVDSCM_RANGE 25:24 +#define SOR_NV_PDISP_SOR_PLL1_0_LVDSCM_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_PLL1_0_LVDSCM_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_PLL1_0_LVDSCM_DEFAULT_MASK _MK_MASK_CONST(0x3) +#define SOR_NV_PDISP_SOR_PLL1_0_LVDSCM_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_PLL1_0_LVDSCM_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define SOR_NV_PDISP_SOR_PLL1_0_LOADADJ_SHIFT _MK_SHIFT_CONST(20) +#define SOR_NV_PDISP_SOR_PLL1_0_LOADADJ_FIELD _MK_FIELD_CONST(0xf, SOR_NV_PDISP_SOR_PLL1_0_LOADADJ_SHIFT) +#define SOR_NV_PDISP_SOR_PLL1_0_LOADADJ_RANGE 23:20 +#define SOR_NV_PDISP_SOR_PLL1_0_LOADADJ_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_PLL1_0_LOADADJ_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_PLL1_0_LOADADJ_DEFAULT_MASK _MK_MASK_CONST(0xf) +#define SOR_NV_PDISP_SOR_PLL1_0_LOADADJ_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_PLL1_0_LOADADJ_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_PLL1_0_LOADADJ_INIT_ENUM CENTER +#define SOR_NV_PDISP_SOR_PLL1_0_LOADADJ_CENTER _MK_ENUM_CONST(0) + +#define SOR_NV_PDISP_SOR_PLL1_0_TERM_COMPOUT_SHIFT _MK_SHIFT_CONST(15) +#define SOR_NV_PDISP_SOR_PLL1_0_TERM_COMPOUT_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_PLL1_0_TERM_COMPOUT_SHIFT) +#define SOR_NV_PDISP_SOR_PLL1_0_TERM_COMPOUT_RANGE 15:15 +#define SOR_NV_PDISP_SOR_PLL1_0_TERM_COMPOUT_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_PLL1_0_TERM_COMPOUT_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_PLL1_0_TERM_COMPOUT_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_PLL1_0_TERM_COMPOUT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_PLL1_0_TERM_COMPOUT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_PLL1_0_TERM_COMPOUT_LOW _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_PLL1_0_TERM_COMPOUT_HIGH _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_PLL1_0_TMDS_TERMADJ_SHIFT _MK_SHIFT_CONST(9) +#define SOR_NV_PDISP_SOR_PLL1_0_TMDS_TERMADJ_FIELD _MK_FIELD_CONST(0xf, SOR_NV_PDISP_SOR_PLL1_0_TMDS_TERMADJ_SHIFT) +#define SOR_NV_PDISP_SOR_PLL1_0_TMDS_TERMADJ_RANGE 12:9 +#define SOR_NV_PDISP_SOR_PLL1_0_TMDS_TERMADJ_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_PLL1_0_TMDS_TERMADJ_DEFAULT _MK_MASK_CONST(0x8) +#define SOR_NV_PDISP_SOR_PLL1_0_TMDS_TERMADJ_DEFAULT_MASK _MK_MASK_CONST(0xf) +#define SOR_NV_PDISP_SOR_PLL1_0_TMDS_TERMADJ_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_PLL1_0_TMDS_TERMADJ_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_PLL1_0_TMDS_TERMADJ_INIT_ENUM OHM500 +#define SOR_NV_PDISP_SOR_PLL1_0_TMDS_TERMADJ_OHM500 _MK_ENUM_CONST(8) + +#define SOR_NV_PDISP_SOR_PLL1_0_TMDS_TERM_SHIFT _MK_SHIFT_CONST(8) +#define SOR_NV_PDISP_SOR_PLL1_0_TMDS_TERM_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_PLL1_0_TMDS_TERM_SHIFT) +#define SOR_NV_PDISP_SOR_PLL1_0_TMDS_TERM_RANGE 8:8 +#define SOR_NV_PDISP_SOR_PLL1_0_TMDS_TERM_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_PLL1_0_TMDS_TERM_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_PLL1_0_TMDS_TERM_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_PLL1_0_TMDS_TERM_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_PLL1_0_TMDS_TERM_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_PLL1_0_TMDS_TERM_INIT_ENUM DISABLE +#define SOR_NV_PDISP_SOR_PLL1_0_TMDS_TERM_DISABLE _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_PLL1_0_TMDS_TERM_ENABLE _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_PLL1_0_IOCURRENT_SHIFT _MK_SHIFT_CONST(0) +#define SOR_NV_PDISP_SOR_PLL1_0_IOCURRENT_FIELD _MK_FIELD_CONST(0x3f, SOR_NV_PDISP_SOR_PLL1_0_IOCURRENT_SHIFT) +#define SOR_NV_PDISP_SOR_PLL1_0_IOCURRENT_RANGE 5:0 +#define SOR_NV_PDISP_SOR_PLL1_0_IOCURRENT_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_PLL1_0_IOCURRENT_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_PLL1_0_IOCURRENT_DEFAULT_MASK _MK_MASK_CONST(0x3f) +#define SOR_NV_PDISP_SOR_PLL1_0_IOCURRENT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_PLL1_0_IOCURRENT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_PLL1_0_IOCURRENT_INIT_ENUM RST +#define SOR_NV_PDISP_SOR_PLL1_0_IOCURRENT_RST _MK_ENUM_CONST(0) + + +// Register SOR_NV_PDISP_SOR_PLL2_0 +#define SOR_NV_PDISP_SOR_PLL2_0 _MK_ADDR_CONST(0x19) +#define SOR_NV_PDISP_SOR_PLL2_0_SECURE 0x0 +#define SOR_NV_PDISP_SOR_PLL2_0_WORD_COUNT 0x1 +#define SOR_NV_PDISP_SOR_PLL2_0_RESET_VAL _MK_MASK_CONST(0x1c00000) +#define SOR_NV_PDISP_SOR_PLL2_0_RESET_MASK _MK_MASK_CONST(0x3fffff3) +#define SOR_NV_PDISP_SOR_PLL2_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_PLL2_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_PLL2_0_READ_MASK _MK_MASK_CONST(0x3fffff3) +#define SOR_NV_PDISP_SOR_PLL2_0_WRITE_MASK _MK_MASK_CONST(0x3fffff3) +#define SOR_NV_PDISP_SOR_PLL2_0_AUX9_SHIFT _MK_SHIFT_CONST(25) +#define SOR_NV_PDISP_SOR_PLL2_0_AUX9_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_PLL2_0_AUX9_SHIFT) +#define SOR_NV_PDISP_SOR_PLL2_0_AUX9_RANGE 25:25 +#define SOR_NV_PDISP_SOR_PLL2_0_AUX9_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_PLL2_0_AUX9_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_PLL2_0_AUX9_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_PLL2_0_AUX9_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_PLL2_0_AUX9_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_PLL2_0_AUX9_INIT_ENUM LVDSEN_ALLOW +#define SOR_NV_PDISP_SOR_PLL2_0_AUX9_LVDSEN_ALLOW _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_PLL2_0_AUX9_LVDSEN_OVERRIDE _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_PLL2_0_AUX8_SHIFT _MK_SHIFT_CONST(24) +#define SOR_NV_PDISP_SOR_PLL2_0_AUX8_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_PLL2_0_AUX8_SHIFT) +#define SOR_NV_PDISP_SOR_PLL2_0_AUX8_RANGE 24:24 +#define SOR_NV_PDISP_SOR_PLL2_0_AUX8_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_PLL2_0_AUX8_DEFAULT _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_PLL2_0_AUX8_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_PLL2_0_AUX8_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_PLL2_0_AUX8_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_PLL2_0_AUX8_INIT_ENUM SEQ_PLLCAPPD_ENFORCE_ENABLE +#define SOR_NV_PDISP_SOR_PLL2_0_AUX8_SEQ_PLLCAPPD_ENFORCE_DISABLE _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_PLL2_0_AUX8_SEQ_PLLCAPPD_ENFORCE_ENABLE _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_PLL2_0_AUX7_SHIFT _MK_SHIFT_CONST(23) +#define SOR_NV_PDISP_SOR_PLL2_0_AUX7_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_PLL2_0_AUX7_SHIFT) +#define SOR_NV_PDISP_SOR_PLL2_0_AUX7_RANGE 23:23 +#define SOR_NV_PDISP_SOR_PLL2_0_AUX7_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_PLL2_0_AUX7_DEFAULT _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_PLL2_0_AUX7_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_PLL2_0_AUX7_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_PLL2_0_AUX7_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_PLL2_0_AUX7_INIT_ENUM PORT_POWERDOWN_ENABLE +#define SOR_NV_PDISP_SOR_PLL2_0_AUX7_PORT_POWERDOWN_DISABLE _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_PLL2_0_AUX7_PORT_POWERDOWN_ENABLE _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_PLL2_0_AUX6_SHIFT _MK_SHIFT_CONST(22) +#define SOR_NV_PDISP_SOR_PLL2_0_AUX6_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_PLL2_0_AUX6_SHIFT) +#define SOR_NV_PDISP_SOR_PLL2_0_AUX6_RANGE 22:22 +#define SOR_NV_PDISP_SOR_PLL2_0_AUX6_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_PLL2_0_AUX6_DEFAULT _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_PLL2_0_AUX6_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_PLL2_0_AUX6_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_PLL2_0_AUX6_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_PLL2_0_AUX6_INIT_ENUM BANDGAP_POWERDOWN_ENABLE +#define SOR_NV_PDISP_SOR_PLL2_0_AUX6_BANDGAP_POWERDOWN_DISABLE _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_PLL2_0_AUX6_BANDGAP_POWERDOWN_ENABLE _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_PLL2_0_AUX5_SHIFT _MK_SHIFT_CONST(21) +#define SOR_NV_PDISP_SOR_PLL2_0_AUX5_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_PLL2_0_AUX5_SHIFT) +#define SOR_NV_PDISP_SOR_PLL2_0_AUX5_RANGE 21:21 +#define SOR_NV_PDISP_SOR_PLL2_0_AUX5_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_PLL2_0_AUX5_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_PLL2_0_AUX5_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_PLL2_0_AUX5_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_PLL2_0_AUX5_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_PLL2_0_AUX5_INIT_ENUM SINGLE_LINK_LVDS +#define SOR_NV_PDISP_SOR_PLL2_0_AUX5_SINGLE_LINK_LVDS _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_PLL2_0_AUX5_DUAL_LINK_LVDS _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_PLL2_0_AUX4_SHIFT _MK_SHIFT_CONST(20) +#define SOR_NV_PDISP_SOR_PLL2_0_AUX4_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_PLL2_0_AUX4_SHIFT) +#define SOR_NV_PDISP_SOR_PLL2_0_AUX4_RANGE 20:20 +#define SOR_NV_PDISP_SOR_PLL2_0_AUX4_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_PLL2_0_AUX4_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_PLL2_0_AUX4_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_PLL2_0_AUX4_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_PLL2_0_AUX4_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_PLL2_0_AUX4_INIT_ENUM DUPLICATE_CTRL_DISABLE +#define SOR_NV_PDISP_SOR_PLL2_0_AUX4_DUPLICATE_CTRL_DISABLE _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_PLL2_0_AUX4_DUPLICATE_CTRL_ENABLE _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_PLL2_0_AUX3_SHIFT _MK_SHIFT_CONST(19) +#define SOR_NV_PDISP_SOR_PLL2_0_AUX3_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_PLL2_0_AUX3_SHIFT) +#define SOR_NV_PDISP_SOR_PLL2_0_AUX3_RANGE 19:19 +#define SOR_NV_PDISP_SOR_PLL2_0_AUX3_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_PLL2_0_AUX3_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_PLL2_0_AUX3_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_PLL2_0_AUX3_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_PLL2_0_AUX3_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_PLL2_0_AUX3_INIT_ENUM ROTATE_DISABLE +#define SOR_NV_PDISP_SOR_PLL2_0_AUX3_ROTATE_DISABLE _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_PLL2_0_AUX3_ROTATE_ENABLE _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_PLL2_0_AUX2_SHIFT _MK_SHIFT_CONST(18) +#define SOR_NV_PDISP_SOR_PLL2_0_AUX2_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_PLL2_0_AUX2_SHIFT) +#define SOR_NV_PDISP_SOR_PLL2_0_AUX2_RANGE 18:18 +#define SOR_NV_PDISP_SOR_PLL2_0_AUX2_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_PLL2_0_AUX2_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_PLL2_0_AUX2_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_PLL2_0_AUX2_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_PLL2_0_AUX2_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_PLL2_0_AUX2_INIT_ENUM OVERRIDE_POWERDOWN +#define SOR_NV_PDISP_SOR_PLL2_0_AUX2_OVERRIDE_POWERDOWN _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_PLL2_0_AUX2_ALLOW_POWERDOWN _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_PLL2_0_AUX1_SHIFT _MK_SHIFT_CONST(17) +#define SOR_NV_PDISP_SOR_PLL2_0_AUX1_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_PLL2_0_AUX1_SHIFT) +#define SOR_NV_PDISP_SOR_PLL2_0_AUX1_RANGE 17:17 +#define SOR_NV_PDISP_SOR_PLL2_0_AUX1_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_PLL2_0_AUX1_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_PLL2_0_AUX1_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_PLL2_0_AUX1_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_PLL2_0_AUX1_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_PLL2_0_AUX1_INIT_ENUM SEQ_PLLCAPPD_ALLOW +#define SOR_NV_PDISP_SOR_PLL2_0_AUX1_SEQ_PLLCAPPD_ALLOW _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_PLL2_0_AUX1_SEQ_PLLCAPPD_OVERRIDE _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_PLL2_0_AUX0_SHIFT _MK_SHIFT_CONST(16) +#define SOR_NV_PDISP_SOR_PLL2_0_AUX0_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_PLL2_0_AUX0_SHIFT) +#define SOR_NV_PDISP_SOR_PLL2_0_AUX0_RANGE 16:16 +#define SOR_NV_PDISP_SOR_PLL2_0_AUX0_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_PLL2_0_AUX0_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_PLL2_0_AUX0_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_PLL2_0_AUX0_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_PLL2_0_AUX0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_PLL2_0_AUX0_INIT_ENUM SEQ_PLL_PULLDOWN_ALLOW +#define SOR_NV_PDISP_SOR_PLL2_0_AUX0_SEQ_PLL_PULLDOWN_ALLOW _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_PLL2_0_AUX0_SEQ_PLL_PULLDOWN_OVERRIDE _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_PLL2_0_PLL_MDIV_SHIFT _MK_SHIFT_CONST(12) +#define SOR_NV_PDISP_SOR_PLL2_0_PLL_MDIV_FIELD _MK_FIELD_CONST(0xf, SOR_NV_PDISP_SOR_PLL2_0_PLL_MDIV_SHIFT) +#define SOR_NV_PDISP_SOR_PLL2_0_PLL_MDIV_RANGE 15:12 +#define SOR_NV_PDISP_SOR_PLL2_0_PLL_MDIV_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_PLL2_0_PLL_MDIV_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_PLL2_0_PLL_MDIV_DEFAULT_MASK _MK_MASK_CONST(0xf) +#define SOR_NV_PDISP_SOR_PLL2_0_PLL_MDIV_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_PLL2_0_PLL_MDIV_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define SOR_NV_PDISP_SOR_PLL2_0_PLL_NDIV_SHIFT _MK_SHIFT_CONST(8) +#define SOR_NV_PDISP_SOR_PLL2_0_PLL_NDIV_FIELD _MK_FIELD_CONST(0xf, SOR_NV_PDISP_SOR_PLL2_0_PLL_NDIV_SHIFT) +#define SOR_NV_PDISP_SOR_PLL2_0_PLL_NDIV_RANGE 11:8 +#define SOR_NV_PDISP_SOR_PLL2_0_PLL_NDIV_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_PLL2_0_PLL_NDIV_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_PLL2_0_PLL_NDIV_DEFAULT_MASK _MK_MASK_CONST(0xf) +#define SOR_NV_PDISP_SOR_PLL2_0_PLL_NDIV_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_PLL2_0_PLL_NDIV_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_PLL2_0_PLL_NDIV_INIT_ENUM BY_3 +#define SOR_NV_PDISP_SOR_PLL2_0_PLL_NDIV_BY_3 _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_PLL2_0_PLL_NDIV_BY_5 _MK_ENUM_CONST(1) +#define SOR_NV_PDISP_SOR_PLL2_0_PLL_NDIV_BY_6 _MK_ENUM_CONST(2) +#define SOR_NV_PDISP_SOR_PLL2_0_PLL_NDIV_BY_7 _MK_ENUM_CONST(3) +#define SOR_NV_PDISP_SOR_PLL2_0_PLL_NDIV_BY_10 _MK_ENUM_CONST(4) + +#define SOR_NV_PDISP_SOR_PLL2_0_PLL_PDIV_SHIFT _MK_SHIFT_CONST(4) +#define SOR_NV_PDISP_SOR_PLL2_0_PLL_PDIV_FIELD _MK_FIELD_CONST(0xf, SOR_NV_PDISP_SOR_PLL2_0_PLL_PDIV_SHIFT) +#define SOR_NV_PDISP_SOR_PLL2_0_PLL_PDIV_RANGE 7:4 +#define SOR_NV_PDISP_SOR_PLL2_0_PLL_PDIV_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_PLL2_0_PLL_PDIV_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_PLL2_0_PLL_PDIV_DEFAULT_MASK _MK_MASK_CONST(0xf) +#define SOR_NV_PDISP_SOR_PLL2_0_PLL_PDIV_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_PLL2_0_PLL_PDIV_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_PLL2_0_PLL_PDIV_INIT_ENUM BY_1 +#define SOR_NV_PDISP_SOR_PLL2_0_PLL_PDIV_BY_1 _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_PLL2_0_PLL_PDIV_BY_2 _MK_ENUM_CONST(1) +#define SOR_NV_PDISP_SOR_PLL2_0_PLL_PDIV_BY_2B _MK_ENUM_CONST(2) +#define SOR_NV_PDISP_SOR_PLL2_0_PLL_PDIV_BY_4 _MK_ENUM_CONST(3) + +#define SOR_NV_PDISP_SOR_PLL2_0_DIV_RATIO_OVERRIDE_SHIFT _MK_SHIFT_CONST(1) +#define SOR_NV_PDISP_SOR_PLL2_0_DIV_RATIO_OVERRIDE_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_PLL2_0_DIV_RATIO_OVERRIDE_SHIFT) +#define SOR_NV_PDISP_SOR_PLL2_0_DIV_RATIO_OVERRIDE_RANGE 1:1 +#define SOR_NV_PDISP_SOR_PLL2_0_DIV_RATIO_OVERRIDE_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_PLL2_0_DIV_RATIO_OVERRIDE_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_PLL2_0_DIV_RATIO_OVERRIDE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_PLL2_0_DIV_RATIO_OVERRIDE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_PLL2_0_DIV_RATIO_OVERRIDE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_PLL2_0_DIV_RATIO_OVERRIDE_INIT_ENUM DISABLE +#define SOR_NV_PDISP_SOR_PLL2_0_DIV_RATIO_OVERRIDE_DISABLE _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_PLL2_0_DIV_RATIO_OVERRIDE_ENABLE _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_PLL2_0_DCIR_PLL_RESET_SHIFT _MK_SHIFT_CONST(0) +#define SOR_NV_PDISP_SOR_PLL2_0_DCIR_PLL_RESET_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_PLL2_0_DCIR_PLL_RESET_SHIFT) +#define SOR_NV_PDISP_SOR_PLL2_0_DCIR_PLL_RESET_RANGE 0:0 +#define SOR_NV_PDISP_SOR_PLL2_0_DCIR_PLL_RESET_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_PLL2_0_DCIR_PLL_RESET_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_PLL2_0_DCIR_PLL_RESET_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_PLL2_0_DCIR_PLL_RESET_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_PLL2_0_DCIR_PLL_RESET_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_PLL2_0_DCIR_PLL_RESET_INIT_ENUM OVERRIDE +#define SOR_NV_PDISP_SOR_PLL2_0_DCIR_PLL_RESET_OVERRIDE _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_PLL2_0_DCIR_PLL_RESET_ALLOW _MK_ENUM_CONST(1) + + +// Register SOR_NV_PDISP_SOR_PLL3_0 +#define SOR_NV_PDISP_SOR_PLL3_0 _MK_ADDR_CONST(0x1a) +#define SOR_NV_PDISP_SOR_PLL3_0_SECURE 0x0 +#define SOR_NV_PDISP_SOR_PLL3_0_WORD_COUNT 0x1 +#define SOR_NV_PDISP_SOR_PLL3_0_RESET_VAL _MK_MASK_CONST(0x38002220) +#define SOR_NV_PDISP_SOR_PLL3_0_RESET_MASK _MK_MASK_CONST(0xffff7ff3) +#define SOR_NV_PDISP_SOR_PLL3_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_PLL3_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_PLL3_0_READ_MASK _MK_MASK_CONST(0xffff7ff3) +#define SOR_NV_PDISP_SOR_PLL3_0_WRITE_MASK _MK_MASK_CONST(0xffff7ff3) +#define SOR_NV_PDISP_SOR_PLL3_0_BG_TEMP_COEF_SHIFT _MK_SHIFT_CONST(28) +#define SOR_NV_PDISP_SOR_PLL3_0_BG_TEMP_COEF_FIELD _MK_FIELD_CONST(0xf, SOR_NV_PDISP_SOR_PLL3_0_BG_TEMP_COEF_SHIFT) +#define SOR_NV_PDISP_SOR_PLL3_0_BG_TEMP_COEF_RANGE 31:28 +#define SOR_NV_PDISP_SOR_PLL3_0_BG_TEMP_COEF_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_PLL3_0_BG_TEMP_COEF_DEFAULT _MK_MASK_CONST(0x3) +#define SOR_NV_PDISP_SOR_PLL3_0_BG_TEMP_COEF_DEFAULT_MASK _MK_MASK_CONST(0xf) +#define SOR_NV_PDISP_SOR_PLL3_0_BG_TEMP_COEF_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_PLL3_0_BG_TEMP_COEF_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define SOR_NV_PDISP_SOR_PLL3_0_BG_VREF_LEVEL_SHIFT _MK_SHIFT_CONST(24) +#define SOR_NV_PDISP_SOR_PLL3_0_BG_VREF_LEVEL_FIELD _MK_FIELD_CONST(0xf, SOR_NV_PDISP_SOR_PLL3_0_BG_VREF_LEVEL_SHIFT) +#define SOR_NV_PDISP_SOR_PLL3_0_BG_VREF_LEVEL_RANGE 27:24 +#define SOR_NV_PDISP_SOR_PLL3_0_BG_VREF_LEVEL_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_PLL3_0_BG_VREF_LEVEL_DEFAULT _MK_MASK_CONST(0x8) +#define SOR_NV_PDISP_SOR_PLL3_0_BG_VREF_LEVEL_DEFAULT_MASK _MK_MASK_CONST(0xf) +#define SOR_NV_PDISP_SOR_PLL3_0_BG_VREF_LEVEL_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_PLL3_0_BG_VREF_LEVEL_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define SOR_NV_PDISP_SOR_PLL3_0_TEST_REFCLK_EN_SHIFT _MK_SHIFT_CONST(16) +#define SOR_NV_PDISP_SOR_PLL3_0_TEST_REFCLK_EN_FIELD _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_PLL3_0_TEST_REFCLK_EN_SHIFT) +#define SOR_NV_PDISP_SOR_PLL3_0_TEST_REFCLK_EN_RANGE 23:16 +#define SOR_NV_PDISP_SOR_PLL3_0_TEST_REFCLK_EN_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_PLL3_0_TEST_REFCLK_EN_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_PLL3_0_TEST_REFCLK_EN_DEFAULT_MASK _MK_MASK_CONST(0xff) +#define SOR_NV_PDISP_SOR_PLL3_0_TEST_REFCLK_EN_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_PLL3_0_TEST_REFCLK_EN_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define SOR_NV_PDISP_SOR_PLL3_0_PLL_BYPASS_SHIFT _MK_SHIFT_CONST(14) +#define SOR_NV_PDISP_SOR_PLL3_0_PLL_BYPASS_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_PLL3_0_PLL_BYPASS_SHIFT) +#define SOR_NV_PDISP_SOR_PLL3_0_PLL_BYPASS_RANGE 14:14 +#define SOR_NV_PDISP_SOR_PLL3_0_PLL_BYPASS_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_PLL3_0_PLL_BYPASS_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_PLL3_0_PLL_BYPASS_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_PLL3_0_PLL_BYPASS_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_PLL3_0_PLL_BYPASS_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_PLL3_0_PLL_BYPASS_INIT_ENUM DISABLE +#define SOR_NV_PDISP_SOR_PLL3_0_PLL_BYPASS_DISABLE _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_PLL3_0_PLL_BYPASS_ENABLE _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_PLL3_0_PLLVDD_MODE_SHIFT _MK_SHIFT_CONST(13) +#define SOR_NV_PDISP_SOR_PLL3_0_PLLVDD_MODE_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_PLL3_0_PLLVDD_MODE_SHIFT) +#define SOR_NV_PDISP_SOR_PLL3_0_PLLVDD_MODE_RANGE 13:13 +#define SOR_NV_PDISP_SOR_PLL3_0_PLLVDD_MODE_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_PLL3_0_PLLVDD_MODE_DEFAULT _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_PLL3_0_PLLVDD_MODE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_PLL3_0_PLLVDD_MODE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_PLL3_0_PLLVDD_MODE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_PLL3_0_PLLVDD_MODE_INIT_ENUM V3_3 +#define SOR_NV_PDISP_SOR_PLL3_0_PLLVDD_MODE_V1_8 _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_PLL3_0_PLLVDD_MODE_V3_3 _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_PLL3_0_CLKDIST_MODE_SHIFT _MK_SHIFT_CONST(12) +#define SOR_NV_PDISP_SOR_PLL3_0_CLKDIST_MODE_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_PLL3_0_CLKDIST_MODE_SHIFT) +#define SOR_NV_PDISP_SOR_PLL3_0_CLKDIST_MODE_RANGE 12:12 +#define SOR_NV_PDISP_SOR_PLL3_0_CLKDIST_MODE_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_PLL3_0_CLKDIST_MODE_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_PLL3_0_CLKDIST_MODE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_PLL3_0_CLKDIST_MODE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_PLL3_0_CLKDIST_MODE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_PLL3_0_CLKDIST_MODE_INIT_ENUM CMOS +#define SOR_NV_PDISP_SOR_PLL3_0_CLKDIST_MODE_CMOS _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_PLL3_0_CLKDIST_MODE_CML _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_PLL3_0_AVDD10_LEVEL_SHIFT _MK_SHIFT_CONST(8) +#define SOR_NV_PDISP_SOR_PLL3_0_AVDD10_LEVEL_FIELD _MK_FIELD_CONST(0xf, SOR_NV_PDISP_SOR_PLL3_0_AVDD10_LEVEL_SHIFT) +#define SOR_NV_PDISP_SOR_PLL3_0_AVDD10_LEVEL_RANGE 11:8 +#define SOR_NV_PDISP_SOR_PLL3_0_AVDD10_LEVEL_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_PLL3_0_AVDD10_LEVEL_DEFAULT _MK_MASK_CONST(0x2) +#define SOR_NV_PDISP_SOR_PLL3_0_AVDD10_LEVEL_DEFAULT_MASK _MK_MASK_CONST(0xf) +#define SOR_NV_PDISP_SOR_PLL3_0_AVDD10_LEVEL_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_PLL3_0_AVDD10_LEVEL_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_PLL3_0_AVDD10_LEVEL_INIT_ENUM V1_05 +#define SOR_NV_PDISP_SOR_PLL3_0_AVDD10_LEVEL_V0_95 _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_PLL3_0_AVDD10_LEVEL_V1_00 _MK_ENUM_CONST(1) +#define SOR_NV_PDISP_SOR_PLL3_0_AVDD10_LEVEL_V1_05 _MK_ENUM_CONST(2) +#define SOR_NV_PDISP_SOR_PLL3_0_AVDD10_LEVEL_V1_10 _MK_ENUM_CONST(3) + +#define SOR_NV_PDISP_SOR_PLL3_0_AVDD14_LEVEL_SHIFT _MK_SHIFT_CONST(4) +#define SOR_NV_PDISP_SOR_PLL3_0_AVDD14_LEVEL_FIELD _MK_FIELD_CONST(0xf, SOR_NV_PDISP_SOR_PLL3_0_AVDD14_LEVEL_SHIFT) +#define SOR_NV_PDISP_SOR_PLL3_0_AVDD14_LEVEL_RANGE 7:4 +#define SOR_NV_PDISP_SOR_PLL3_0_AVDD14_LEVEL_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_PLL3_0_AVDD14_LEVEL_DEFAULT _MK_MASK_CONST(0x2) +#define SOR_NV_PDISP_SOR_PLL3_0_AVDD14_LEVEL_DEFAULT_MASK _MK_MASK_CONST(0xf) +#define SOR_NV_PDISP_SOR_PLL3_0_AVDD14_LEVEL_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_PLL3_0_AVDD14_LEVEL_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_PLL3_0_AVDD14_LEVEL_INIT_ENUM V1_45 +#define SOR_NV_PDISP_SOR_PLL3_0_AVDD14_LEVEL_V1_35 _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_PLL3_0_AVDD14_LEVEL_V1_40 _MK_ENUM_CONST(1) +#define SOR_NV_PDISP_SOR_PLL3_0_AVDD14_LEVEL_V1_45 _MK_ENUM_CONST(2) +#define SOR_NV_PDISP_SOR_PLL3_0_AVDD14_LEVEL_V1_50 _MK_ENUM_CONST(3) + +#define SOR_NV_PDISP_SOR_PLL3_0_KICKSTART_SHIFT _MK_SHIFT_CONST(0) +#define SOR_NV_PDISP_SOR_PLL3_0_KICKSTART_FIELD _MK_FIELD_CONST(0x3, SOR_NV_PDISP_SOR_PLL3_0_KICKSTART_SHIFT) +#define SOR_NV_PDISP_SOR_PLL3_0_KICKSTART_RANGE 1:0 +#define SOR_NV_PDISP_SOR_PLL3_0_KICKSTART_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_PLL3_0_KICKSTART_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_PLL3_0_KICKSTART_DEFAULT_MASK _MK_MASK_CONST(0x3) +#define SOR_NV_PDISP_SOR_PLL3_0_KICKSTART_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_PLL3_0_KICKSTART_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_PLL3_0_KICKSTART_INIT_ENUM DISABLE +#define SOR_NV_PDISP_SOR_PLL3_0_KICKSTART_DISABLE _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_PLL3_0_KICKSTART_LOOP_40 _MK_ENUM_CONST(1) +#define SOR_NV_PDISP_SOR_PLL3_0_KICKSTART_LOOP_50 _MK_ENUM_CONST(2) +#define SOR_NV_PDISP_SOR_PLL3_0_KICKSTART_LOOP_60 _MK_ENUM_CONST(3) + + +// Register SOR_NV_PDISP_SOR_CSTM_0 +#define SOR_NV_PDISP_SOR_CSTM_0 _MK_ADDR_CONST(0x1b) +#define SOR_NV_PDISP_SOR_CSTM_0_SECURE 0x0 +#define SOR_NV_PDISP_SOR_CSTM_0_WORD_COUNT 0x1 +#define SOR_NV_PDISP_SOR_CSTM_0_RESET_VAL _MK_MASK_CONST(0x1c800) +#define SOR_NV_PDISP_SOR_CSTM_0_RESET_MASK _MK_MASK_CONST(0x7f2ffbff) +#define SOR_NV_PDISP_SOR_CSTM_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_CSTM_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_CSTM_0_READ_MASK _MK_MASK_CONST(0x7f2ffbff) +#define SOR_NV_PDISP_SOR_CSTM_0_WRITE_MASK _MK_MASK_CONST(0x7f2ffbff) +#define SOR_NV_PDISP_SOR_CSTM_0_ROTDAT_SHIFT _MK_SHIFT_CONST(28) +#define SOR_NV_PDISP_SOR_CSTM_0_ROTDAT_FIELD _MK_FIELD_CONST(0x7, SOR_NV_PDISP_SOR_CSTM_0_ROTDAT_SHIFT) +#define SOR_NV_PDISP_SOR_CSTM_0_ROTDAT_RANGE 30:28 +#define SOR_NV_PDISP_SOR_CSTM_0_ROTDAT_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_CSTM_0_ROTDAT_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_CSTM_0_ROTDAT_DEFAULT_MASK _MK_MASK_CONST(0x7) +#define SOR_NV_PDISP_SOR_CSTM_0_ROTDAT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_CSTM_0_ROTDAT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_CSTM_0_ROTDAT_INIT_ENUM RST +#define SOR_NV_PDISP_SOR_CSTM_0_ROTDAT_RST _MK_ENUM_CONST(0) + +#define SOR_NV_PDISP_SOR_CSTM_0_ROTCLK_SHIFT _MK_SHIFT_CONST(24) +#define SOR_NV_PDISP_SOR_CSTM_0_ROTCLK_FIELD _MK_FIELD_CONST(0xf, SOR_NV_PDISP_SOR_CSTM_0_ROTCLK_SHIFT) +#define SOR_NV_PDISP_SOR_CSTM_0_ROTCLK_RANGE 27:24 +#define SOR_NV_PDISP_SOR_CSTM_0_ROTCLK_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_CSTM_0_ROTCLK_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_CSTM_0_ROTCLK_DEFAULT_MASK _MK_MASK_CONST(0xf) +#define SOR_NV_PDISP_SOR_CSTM_0_ROTCLK_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_CSTM_0_ROTCLK_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_CSTM_0_ROTCLK_INIT_ENUM RST +#define SOR_NV_PDISP_SOR_CSTM_0_ROTCLK_RST _MK_ENUM_CONST(0) + +#define SOR_NV_PDISP_SOR_CSTM_0_PLLDIV_SHIFT _MK_SHIFT_CONST(21) +#define SOR_NV_PDISP_SOR_CSTM_0_PLLDIV_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_CSTM_0_PLLDIV_SHIFT) +#define SOR_NV_PDISP_SOR_CSTM_0_PLLDIV_RANGE 21:21 +#define SOR_NV_PDISP_SOR_CSTM_0_PLLDIV_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_CSTM_0_PLLDIV_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_CSTM_0_PLLDIV_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_CSTM_0_PLLDIV_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_CSTM_0_PLLDIV_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_CSTM_0_PLLDIV_INIT_ENUM BY_7 +#define SOR_NV_PDISP_SOR_CSTM_0_PLLDIV_BY_7 _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_CSTM_0_PLLDIV_BY_10 _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_CSTM_0_BALANCED_SHIFT _MK_SHIFT_CONST(19) +#define SOR_NV_PDISP_SOR_CSTM_0_BALANCED_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_CSTM_0_BALANCED_SHIFT) +#define SOR_NV_PDISP_SOR_CSTM_0_BALANCED_RANGE 19:19 +#define SOR_NV_PDISP_SOR_CSTM_0_BALANCED_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_CSTM_0_BALANCED_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_CSTM_0_BALANCED_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_CSTM_0_BALANCED_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_CSTM_0_BALANCED_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_CSTM_0_BALANCED_INIT_ENUM DISABLE +#define SOR_NV_PDISP_SOR_CSTM_0_BALANCED_DISABLE _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_CSTM_0_BALANCED_ENABLE _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_CSTM_0_NEW_MODE_SHIFT _MK_SHIFT_CONST(18) +#define SOR_NV_PDISP_SOR_CSTM_0_NEW_MODE_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_CSTM_0_NEW_MODE_SHIFT) +#define SOR_NV_PDISP_SOR_CSTM_0_NEW_MODE_RANGE 18:18 +#define SOR_NV_PDISP_SOR_CSTM_0_NEW_MODE_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_CSTM_0_NEW_MODE_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_CSTM_0_NEW_MODE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_CSTM_0_NEW_MODE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_CSTM_0_NEW_MODE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_CSTM_0_NEW_MODE_INIT_ENUM DISABLE +#define SOR_NV_PDISP_SOR_CSTM_0_NEW_MODE_DISABLE _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_CSTM_0_NEW_MODE_ENABLE _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_CSTM_0_DUP_SYNC_SHIFT _MK_SHIFT_CONST(17) +#define SOR_NV_PDISP_SOR_CSTM_0_DUP_SYNC_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_CSTM_0_DUP_SYNC_SHIFT) +#define SOR_NV_PDISP_SOR_CSTM_0_DUP_SYNC_RANGE 17:17 +#define SOR_NV_PDISP_SOR_CSTM_0_DUP_SYNC_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_CSTM_0_DUP_SYNC_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_CSTM_0_DUP_SYNC_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_CSTM_0_DUP_SYNC_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_CSTM_0_DUP_SYNC_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_CSTM_0_DUP_SYNC_INIT_ENUM DISABLE +#define SOR_NV_PDISP_SOR_CSTM_0_DUP_SYNC_DISABLE _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_CSTM_0_DUP_SYNC_ENABLE _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_CSTM_0_LVDS_EN_SHIFT _MK_SHIFT_CONST(16) +#define SOR_NV_PDISP_SOR_CSTM_0_LVDS_EN_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_CSTM_0_LVDS_EN_SHIFT) +#define SOR_NV_PDISP_SOR_CSTM_0_LVDS_EN_RANGE 16:16 +#define SOR_NV_PDISP_SOR_CSTM_0_LVDS_EN_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_CSTM_0_LVDS_EN_DEFAULT _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_CSTM_0_LVDS_EN_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_CSTM_0_LVDS_EN_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_CSTM_0_LVDS_EN_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_CSTM_0_LVDS_EN_INIT_ENUM ENABLE +#define SOR_NV_PDISP_SOR_CSTM_0_LVDS_EN_DISABLE _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_CSTM_0_LVDS_EN_ENABLE _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_CSTM_0_LINKACTB_SHIFT _MK_SHIFT_CONST(15) +#define SOR_NV_PDISP_SOR_CSTM_0_LINKACTB_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_CSTM_0_LINKACTB_SHIFT) +#define SOR_NV_PDISP_SOR_CSTM_0_LINKACTB_RANGE 15:15 +#define SOR_NV_PDISP_SOR_CSTM_0_LINKACTB_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_CSTM_0_LINKACTB_DEFAULT _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_CSTM_0_LINKACTB_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_CSTM_0_LINKACTB_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_CSTM_0_LINKACTB_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_CSTM_0_LINKACTB_INIT_ENUM ENABLE +#define SOR_NV_PDISP_SOR_CSTM_0_LINKACTB_DISABLE _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_CSTM_0_LINKACTB_ENABLE _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_CSTM_0_LINKACTA_SHIFT _MK_SHIFT_CONST(14) +#define SOR_NV_PDISP_SOR_CSTM_0_LINKACTA_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_CSTM_0_LINKACTA_SHIFT) +#define SOR_NV_PDISP_SOR_CSTM_0_LINKACTA_RANGE 14:14 +#define SOR_NV_PDISP_SOR_CSTM_0_LINKACTA_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_CSTM_0_LINKACTA_DEFAULT _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_CSTM_0_LINKACTA_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_CSTM_0_LINKACTA_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_CSTM_0_LINKACTA_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_CSTM_0_LINKACTA_INIT_ENUM ENABLE +#define SOR_NV_PDISP_SOR_CSTM_0_LINKACTA_DISABLE _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_CSTM_0_LINKACTA_ENABLE _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_CSTM_0_MODE_SHIFT _MK_SHIFT_CONST(12) +#define SOR_NV_PDISP_SOR_CSTM_0_MODE_FIELD _MK_FIELD_CONST(0x3, SOR_NV_PDISP_SOR_CSTM_0_MODE_SHIFT) +#define SOR_NV_PDISP_SOR_CSTM_0_MODE_RANGE 13:12 +#define SOR_NV_PDISP_SOR_CSTM_0_MODE_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_CSTM_0_MODE_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_CSTM_0_MODE_DEFAULT_MASK _MK_MASK_CONST(0x3) +#define SOR_NV_PDISP_SOR_CSTM_0_MODE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_CSTM_0_MODE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_CSTM_0_MODE_INIT_ENUM LVDS +#define SOR_NV_PDISP_SOR_CSTM_0_MODE_LVDS _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_CSTM_0_MODE_DP _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_CSTM_0_UPPER_SHIFT _MK_SHIFT_CONST(11) +#define SOR_NV_PDISP_SOR_CSTM_0_UPPER_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_CSTM_0_UPPER_SHIFT) +#define SOR_NV_PDISP_SOR_CSTM_0_UPPER_RANGE 11:11 +#define SOR_NV_PDISP_SOR_CSTM_0_UPPER_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_CSTM_0_UPPER_DEFAULT _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_CSTM_0_UPPER_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_CSTM_0_UPPER_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_CSTM_0_UPPER_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_CSTM_0_UPPER_INIT_ENUM TRUE +#define SOR_NV_PDISP_SOR_CSTM_0_UPPER_FALSE _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_CSTM_0_UPPER_TRUE _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXCB_SHIFT _MK_SHIFT_CONST(9) +#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXCB_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_CSTM_0_PD_TXCB_SHIFT) +#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXCB_RANGE 9:9 +#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXCB_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXCB_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXCB_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXCB_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXCB_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXCB_INIT_ENUM ENABLE +#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXCB_ENABLE _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXCB_DISABLE _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXCA_SHIFT _MK_SHIFT_CONST(8) +#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXCA_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_CSTM_0_PD_TXCA_SHIFT) +#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXCA_RANGE 8:8 +#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXCA_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXCA_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXCA_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXCA_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXCA_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXCA_INIT_ENUM ENABLE +#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXCA_ENABLE _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXCA_DISABLE _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXDB_3_SHIFT _MK_SHIFT_CONST(7) +#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXDB_3_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_CSTM_0_PD_TXDB_3_SHIFT) +#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXDB_3_RANGE 7:7 +#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXDB_3_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXDB_3_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXDB_3_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXDB_3_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXDB_3_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXDB_3_INIT_ENUM ENABLE +#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXDB_3_ENABLE _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXDB_3_DISABLE _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXDB_2_SHIFT _MK_SHIFT_CONST(6) +#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXDB_2_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_CSTM_0_PD_TXDB_2_SHIFT) +#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXDB_2_RANGE 6:6 +#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXDB_2_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXDB_2_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXDB_2_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXDB_2_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXDB_2_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXDB_2_INIT_ENUM ENABLE +#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXDB_2_ENABLE _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXDB_2_DISABLE _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXDB_1_SHIFT _MK_SHIFT_CONST(5) +#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXDB_1_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_CSTM_0_PD_TXDB_1_SHIFT) +#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXDB_1_RANGE 5:5 +#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXDB_1_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXDB_1_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXDB_1_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXDB_1_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXDB_1_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXDB_1_INIT_ENUM ENABLE +#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXDB_1_ENABLE _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXDB_1_DISABLE _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXDB_0_SHIFT _MK_SHIFT_CONST(4) +#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXDB_0_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_CSTM_0_PD_TXDB_0_SHIFT) +#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXDB_0_RANGE 4:4 +#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXDB_0_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXDB_0_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXDB_0_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXDB_0_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXDB_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXDB_0_INIT_ENUM ENABLE +#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXDB_0_ENABLE _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXDB_0_DISABLE _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXDA_3_SHIFT _MK_SHIFT_CONST(3) +#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXDA_3_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_CSTM_0_PD_TXDA_3_SHIFT) +#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXDA_3_RANGE 3:3 +#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXDA_3_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXDA_3_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXDA_3_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXDA_3_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXDA_3_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXDA_3_INIT_ENUM ENABLE +#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXDA_3_ENABLE _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXDA_3_DISABLE _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXDA_2_SHIFT _MK_SHIFT_CONST(2) +#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXDA_2_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_CSTM_0_PD_TXDA_2_SHIFT) +#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXDA_2_RANGE 2:2 +#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXDA_2_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXDA_2_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXDA_2_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXDA_2_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXDA_2_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXDA_2_INIT_ENUM ENABLE +#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXDA_2_ENABLE _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXDA_2_DISABLE _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXDA_1_SHIFT _MK_SHIFT_CONST(1) +#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXDA_1_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_CSTM_0_PD_TXDA_1_SHIFT) +#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXDA_1_RANGE 1:1 +#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXDA_1_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXDA_1_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXDA_1_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXDA_1_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXDA_1_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXDA_1_INIT_ENUM ENABLE +#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXDA_1_ENABLE _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXDA_1_DISABLE _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXDA_0_SHIFT _MK_SHIFT_CONST(0) +#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXDA_0_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_CSTM_0_PD_TXDA_0_SHIFT) +#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXDA_0_RANGE 0:0 +#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXDA_0_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXDA_0_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXDA_0_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXDA_0_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXDA_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXDA_0_INIT_ENUM ENABLE +#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXDA_0_ENABLE _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_CSTM_0_PD_TXDA_0_DISABLE _MK_ENUM_CONST(1) + + +// Register SOR_NV_PDISP_SOR_LVDS_0 +#define SOR_NV_PDISP_SOR_LVDS_0 _MK_ADDR_CONST(0x1c) +#define SOR_NV_PDISP_SOR_LVDS_0_SECURE 0x0 +#define SOR_NV_PDISP_SOR_LVDS_0_WORD_COUNT 0x1 +#define SOR_NV_PDISP_SOR_LVDS_0_RESET_VAL _MK_MASK_CONST(0x1c800) +#define SOR_NV_PDISP_SOR_LVDS_0_RESET_MASK _MK_MASK_CONST(0x7f2ffbff) +#define SOR_NV_PDISP_SOR_LVDS_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_LVDS_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_LVDS_0_READ_MASK _MK_MASK_CONST(0x7f2ffbff) +#define SOR_NV_PDISP_SOR_LVDS_0_WRITE_MASK _MK_MASK_CONST(0x7f0e82f8) +#define SOR_NV_PDISP_SOR_LVDS_0_ROTDAT_SHIFT _MK_SHIFT_CONST(28) +#define SOR_NV_PDISP_SOR_LVDS_0_ROTDAT_FIELD _MK_FIELD_CONST(0x7, SOR_NV_PDISP_SOR_LVDS_0_ROTDAT_SHIFT) +#define SOR_NV_PDISP_SOR_LVDS_0_ROTDAT_RANGE 30:28 +#define SOR_NV_PDISP_SOR_LVDS_0_ROTDAT_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_LVDS_0_ROTDAT_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_LVDS_0_ROTDAT_DEFAULT_MASK _MK_MASK_CONST(0x7) +#define SOR_NV_PDISP_SOR_LVDS_0_ROTDAT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_LVDS_0_ROTDAT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_LVDS_0_ROTDAT_INIT_ENUM RST +#define SOR_NV_PDISP_SOR_LVDS_0_ROTDAT_RST _MK_ENUM_CONST(0) + +#define SOR_NV_PDISP_SOR_LVDS_0_ROTCLK_SHIFT _MK_SHIFT_CONST(24) +#define SOR_NV_PDISP_SOR_LVDS_0_ROTCLK_FIELD _MK_FIELD_CONST(0xf, SOR_NV_PDISP_SOR_LVDS_0_ROTCLK_SHIFT) +#define SOR_NV_PDISP_SOR_LVDS_0_ROTCLK_RANGE 27:24 +#define SOR_NV_PDISP_SOR_LVDS_0_ROTCLK_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_LVDS_0_ROTCLK_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_LVDS_0_ROTCLK_DEFAULT_MASK _MK_MASK_CONST(0xf) +#define SOR_NV_PDISP_SOR_LVDS_0_ROTCLK_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_LVDS_0_ROTCLK_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_LVDS_0_ROTCLK_INIT_ENUM RST +#define SOR_NV_PDISP_SOR_LVDS_0_ROTCLK_RST _MK_ENUM_CONST(0) + +#define SOR_NV_PDISP_SOR_LVDS_0_PLLDIV_SHIFT _MK_SHIFT_CONST(21) +#define SOR_NV_PDISP_SOR_LVDS_0_PLLDIV_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_LVDS_0_PLLDIV_SHIFT) +#define SOR_NV_PDISP_SOR_LVDS_0_PLLDIV_RANGE 21:21 +#define SOR_NV_PDISP_SOR_LVDS_0_PLLDIV_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_LVDS_0_PLLDIV_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_LVDS_0_PLLDIV_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_LVDS_0_PLLDIV_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_LVDS_0_PLLDIV_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_LVDS_0_PLLDIV_INIT_ENUM BY_7 +#define SOR_NV_PDISP_SOR_LVDS_0_PLLDIV_BY_7 _MK_ENUM_CONST(0) + +#define SOR_NV_PDISP_SOR_LVDS_0_BALANCED_SHIFT _MK_SHIFT_CONST(19) +#define SOR_NV_PDISP_SOR_LVDS_0_BALANCED_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_LVDS_0_BALANCED_SHIFT) +#define SOR_NV_PDISP_SOR_LVDS_0_BALANCED_RANGE 19:19 +#define SOR_NV_PDISP_SOR_LVDS_0_BALANCED_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_LVDS_0_BALANCED_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_LVDS_0_BALANCED_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_LVDS_0_BALANCED_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_LVDS_0_BALANCED_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_LVDS_0_BALANCED_INIT_ENUM DISABLE +#define SOR_NV_PDISP_SOR_LVDS_0_BALANCED_DISABLE _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_LVDS_0_BALANCED_ENABLE _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_LVDS_0_NEW_MODE_SHIFT _MK_SHIFT_CONST(18) +#define SOR_NV_PDISP_SOR_LVDS_0_NEW_MODE_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_LVDS_0_NEW_MODE_SHIFT) +#define SOR_NV_PDISP_SOR_LVDS_0_NEW_MODE_RANGE 18:18 +#define SOR_NV_PDISP_SOR_LVDS_0_NEW_MODE_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_LVDS_0_NEW_MODE_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_LVDS_0_NEW_MODE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_LVDS_0_NEW_MODE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_LVDS_0_NEW_MODE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_LVDS_0_NEW_MODE_INIT_ENUM DISABLE +#define SOR_NV_PDISP_SOR_LVDS_0_NEW_MODE_DISABLE _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_LVDS_0_NEW_MODE_ENABLE _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_LVDS_0_DUP_SYNC_SHIFT _MK_SHIFT_CONST(17) +#define SOR_NV_PDISP_SOR_LVDS_0_DUP_SYNC_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_LVDS_0_DUP_SYNC_SHIFT) +#define SOR_NV_PDISP_SOR_LVDS_0_DUP_SYNC_RANGE 17:17 +#define SOR_NV_PDISP_SOR_LVDS_0_DUP_SYNC_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_LVDS_0_DUP_SYNC_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_LVDS_0_DUP_SYNC_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_LVDS_0_DUP_SYNC_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_LVDS_0_DUP_SYNC_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_LVDS_0_DUP_SYNC_INIT_ENUM DISABLE +#define SOR_NV_PDISP_SOR_LVDS_0_DUP_SYNC_DISABLE _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_LVDS_0_DUP_SYNC_ENABLE _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_LVDS_0_LVDS_EN_SHIFT _MK_SHIFT_CONST(16) +#define SOR_NV_PDISP_SOR_LVDS_0_LVDS_EN_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_LVDS_0_LVDS_EN_SHIFT) +#define SOR_NV_PDISP_SOR_LVDS_0_LVDS_EN_RANGE 16:16 +#define SOR_NV_PDISP_SOR_LVDS_0_LVDS_EN_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_LVDS_0_LVDS_EN_DEFAULT _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_LVDS_0_LVDS_EN_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_LVDS_0_LVDS_EN_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_LVDS_0_LVDS_EN_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_LVDS_0_LVDS_EN_INIT_ENUM ENABLE +#define SOR_NV_PDISP_SOR_LVDS_0_LVDS_EN_ENABLE _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_LVDS_0_LINKACTB_SHIFT _MK_SHIFT_CONST(15) +#define SOR_NV_PDISP_SOR_LVDS_0_LINKACTB_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_LVDS_0_LINKACTB_SHIFT) +#define SOR_NV_PDISP_SOR_LVDS_0_LINKACTB_RANGE 15:15 +#define SOR_NV_PDISP_SOR_LVDS_0_LINKACTB_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_LVDS_0_LINKACTB_DEFAULT _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_LVDS_0_LINKACTB_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_LVDS_0_LINKACTB_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_LVDS_0_LINKACTB_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_LVDS_0_LINKACTB_INIT_ENUM ENABLE +#define SOR_NV_PDISP_SOR_LVDS_0_LINKACTB_DISABLE _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_LVDS_0_LINKACTB_ENABLE _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_LVDS_0_LINKACTA_SHIFT _MK_SHIFT_CONST(14) +#define SOR_NV_PDISP_SOR_LVDS_0_LINKACTA_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_LVDS_0_LINKACTA_SHIFT) +#define SOR_NV_PDISP_SOR_LVDS_0_LINKACTA_RANGE 14:14 +#define SOR_NV_PDISP_SOR_LVDS_0_LINKACTA_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_LVDS_0_LINKACTA_DEFAULT _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_LVDS_0_LINKACTA_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_LVDS_0_LINKACTA_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_LVDS_0_LINKACTA_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_LVDS_0_LINKACTA_INIT_ENUM ENABLE +#define SOR_NV_PDISP_SOR_LVDS_0_LINKACTA_ENABLE _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_LVDS_0_MODE_SHIFT _MK_SHIFT_CONST(12) +#define SOR_NV_PDISP_SOR_LVDS_0_MODE_FIELD _MK_FIELD_CONST(0x3, SOR_NV_PDISP_SOR_LVDS_0_MODE_SHIFT) +#define SOR_NV_PDISP_SOR_LVDS_0_MODE_RANGE 13:12 +#define SOR_NV_PDISP_SOR_LVDS_0_MODE_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_LVDS_0_MODE_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_LVDS_0_MODE_DEFAULT_MASK _MK_MASK_CONST(0x3) +#define SOR_NV_PDISP_SOR_LVDS_0_MODE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_LVDS_0_MODE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_LVDS_0_MODE_INIT_ENUM LVDS +#define SOR_NV_PDISP_SOR_LVDS_0_MODE_LVDS _MK_ENUM_CONST(0) + +#define SOR_NV_PDISP_SOR_LVDS_0_UPPER_SHIFT _MK_SHIFT_CONST(11) +#define SOR_NV_PDISP_SOR_LVDS_0_UPPER_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_LVDS_0_UPPER_SHIFT) +#define SOR_NV_PDISP_SOR_LVDS_0_UPPER_RANGE 11:11 +#define SOR_NV_PDISP_SOR_LVDS_0_UPPER_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_LVDS_0_UPPER_DEFAULT _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_LVDS_0_UPPER_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_LVDS_0_UPPER_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_LVDS_0_UPPER_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_LVDS_0_UPPER_INIT_ENUM TRUE +#define SOR_NV_PDISP_SOR_LVDS_0_UPPER_FALSE _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_LVDS_0_UPPER_TRUE _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXCB_SHIFT _MK_SHIFT_CONST(9) +#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXCB_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_LVDS_0_PD_TXCB_SHIFT) +#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXCB_RANGE 9:9 +#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXCB_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXCB_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXCB_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXCB_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXCB_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXCB_INIT_ENUM ENABLE +#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXCB_ENABLE _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXCB_DISABLE _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXCA_SHIFT _MK_SHIFT_CONST(8) +#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXCA_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_LVDS_0_PD_TXCA_SHIFT) +#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXCA_RANGE 8:8 +#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXCA_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXCA_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXCA_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXCA_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXCA_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXCA_INIT_ENUM ENABLE +#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXCA_ENABLE _MK_ENUM_CONST(0) + +#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXDB_3_SHIFT _MK_SHIFT_CONST(7) +#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXDB_3_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_LVDS_0_PD_TXDB_3_SHIFT) +#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXDB_3_RANGE 7:7 +#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXDB_3_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXDB_3_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXDB_3_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXDB_3_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXDB_3_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXDB_3_INIT_ENUM ENABLE +#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXDB_3_ENABLE _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXDB_3_DISABLE _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXDB_2_SHIFT _MK_SHIFT_CONST(6) +#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXDB_2_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_LVDS_0_PD_TXDB_2_SHIFT) +#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXDB_2_RANGE 6:6 +#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXDB_2_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXDB_2_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXDB_2_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXDB_2_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXDB_2_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXDB_2_INIT_ENUM ENABLE +#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXDB_2_ENABLE _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXDB_2_DISABLE _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXDB_1_SHIFT _MK_SHIFT_CONST(5) +#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXDB_1_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_LVDS_0_PD_TXDB_1_SHIFT) +#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXDB_1_RANGE 5:5 +#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXDB_1_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXDB_1_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXDB_1_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXDB_1_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXDB_1_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXDB_1_INIT_ENUM ENABLE +#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXDB_1_ENABLE _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXDB_1_DISABLE _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXDB_0_SHIFT _MK_SHIFT_CONST(4) +#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXDB_0_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_LVDS_0_PD_TXDB_0_SHIFT) +#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXDB_0_RANGE 4:4 +#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXDB_0_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXDB_0_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXDB_0_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXDB_0_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXDB_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXDB_0_INIT_ENUM ENABLE +#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXDB_0_ENABLE _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXDB_0_DISABLE _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXDA_3_SHIFT _MK_SHIFT_CONST(3) +#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXDA_3_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_LVDS_0_PD_TXDA_3_SHIFT) +#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXDA_3_RANGE 3:3 +#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXDA_3_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXDA_3_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXDA_3_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXDA_3_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXDA_3_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXDA_3_INIT_ENUM ENABLE +#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXDA_3_ENABLE _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXDA_3_DISABLE _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXDA_2_SHIFT _MK_SHIFT_CONST(2) +#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXDA_2_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_LVDS_0_PD_TXDA_2_SHIFT) +#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXDA_2_RANGE 2:2 +#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXDA_2_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXDA_2_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXDA_2_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXDA_2_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXDA_2_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXDA_2_INIT_ENUM ENABLE +#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXDA_2_ENABLE _MK_ENUM_CONST(0) + +#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXDA_1_SHIFT _MK_SHIFT_CONST(1) +#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXDA_1_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_LVDS_0_PD_TXDA_1_SHIFT) +#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXDA_1_RANGE 1:1 +#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXDA_1_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXDA_1_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXDA_1_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXDA_1_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXDA_1_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXDA_1_INIT_ENUM ENABLE +#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXDA_1_ENABLE _MK_ENUM_CONST(0) + +#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXDA_0_SHIFT _MK_SHIFT_CONST(0) +#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXDA_0_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_LVDS_0_PD_TXDA_0_SHIFT) +#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXDA_0_RANGE 0:0 +#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXDA_0_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXDA_0_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXDA_0_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXDA_0_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXDA_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXDA_0_INIT_ENUM ENABLE +#define SOR_NV_PDISP_SOR_LVDS_0_PD_TXDA_0_ENABLE _MK_ENUM_CONST(0) + + +// Register SOR_NV_PDISP_SOR_CRCA_0 +#define SOR_NV_PDISP_SOR_CRCA_0 _MK_ADDR_CONST(0x1d) +#define SOR_NV_PDISP_SOR_CRCA_0_SECURE 0x0 +#define SOR_NV_PDISP_SOR_CRCA_0_WORD_COUNT 0x1 +#define SOR_NV_PDISP_SOR_CRCA_0_RESET_VAL _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_CRCA_0_RESET_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_CRCA_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_CRCA_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_CRCA_0_READ_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_CRCA_0_WRITE_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_CRCA_0_VALID_SHIFT _MK_SHIFT_CONST(0) +#define SOR_NV_PDISP_SOR_CRCA_0_VALID_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_CRCA_0_VALID_SHIFT) +#define SOR_NV_PDISP_SOR_CRCA_0_VALID_RANGE 0:0 +#define SOR_NV_PDISP_SOR_CRCA_0_VALID_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_CRCA_0_VALID_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_CRCA_0_VALID_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_CRCA_0_VALID_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_CRCA_0_VALID_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_CRCA_0_VALID_INIT_ENUM FALSE +#define SOR_NV_PDISP_SOR_CRCA_0_VALID_FALSE _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_CRCA_0_VALID_TRUE _MK_ENUM_CONST(1) +#define SOR_NV_PDISP_SOR_CRCA_0_VALID_RST _MK_ENUM_CONST(1) + + +// Register SOR_NV_PDISP_SOR_CRCB_0 +#define SOR_NV_PDISP_SOR_CRCB_0 _MK_ADDR_CONST(0x1e) +#define SOR_NV_PDISP_SOR_CRCB_0_SECURE 0x0 +#define SOR_NV_PDISP_SOR_CRCB_0_WORD_COUNT 0x1 +#define SOR_NV_PDISP_SOR_CRCB_0_RESET_VAL _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_CRCB_0_RESET_MASK _MK_MASK_CONST(0xffffffff) +#define SOR_NV_PDISP_SOR_CRCB_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_CRCB_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_CRCB_0_READ_MASK _MK_MASK_CONST(0xffffffff) +#define SOR_NV_PDISP_SOR_CRCB_0_WRITE_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_CRCB_0_CRC_SHIFT _MK_SHIFT_CONST(0) +#define SOR_NV_PDISP_SOR_CRCB_0_CRC_FIELD _MK_FIELD_CONST(0xffffffff, SOR_NV_PDISP_SOR_CRCB_0_CRC_SHIFT) +#define SOR_NV_PDISP_SOR_CRCB_0_CRC_RANGE 31:0 +#define SOR_NV_PDISP_SOR_CRCB_0_CRC_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_CRCB_0_CRC_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_CRCB_0_CRC_DEFAULT_MASK _MK_MASK_CONST(0xffffffff) +#define SOR_NV_PDISP_SOR_CRCB_0_CRC_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_CRCB_0_CRC_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register SOR_NV_PDISP_SOR_BLANK_0 +#define SOR_NV_PDISP_SOR_BLANK_0 _MK_ADDR_CONST(0x1f) +#define SOR_NV_PDISP_SOR_BLANK_0_SECURE 0x0 +#define SOR_NV_PDISP_SOR_BLANK_0_WORD_COUNT 0x1 +#define SOR_NV_PDISP_SOR_BLANK_0_RESET_VAL _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_BLANK_0_RESET_MASK _MK_MASK_CONST(0x3) +#define SOR_NV_PDISP_SOR_BLANK_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_BLANK_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_BLANK_0_READ_MASK _MK_MASK_CONST(0x7) +#define SOR_NV_PDISP_SOR_BLANK_0_WRITE_MASK _MK_MASK_CONST(0x3) +#define SOR_NV_PDISP_SOR_BLANK_0_STATUS_SHIFT _MK_SHIFT_CONST(2) +#define SOR_NV_PDISP_SOR_BLANK_0_STATUS_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_BLANK_0_STATUS_SHIFT) +#define SOR_NV_PDISP_SOR_BLANK_0_STATUS_RANGE 2:2 +#define SOR_NV_PDISP_SOR_BLANK_0_STATUS_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_BLANK_0_STATUS_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_BLANK_0_STATUS_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_BLANK_0_STATUS_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_BLANK_0_STATUS_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_BLANK_0_STATUS_NOT_BLANKED _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_BLANK_0_STATUS_BLANKED _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_BLANK_0_TRANSITION_SHIFT _MK_SHIFT_CONST(1) +#define SOR_NV_PDISP_SOR_BLANK_0_TRANSITION_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_BLANK_0_TRANSITION_SHIFT) +#define SOR_NV_PDISP_SOR_BLANK_0_TRANSITION_RANGE 1:1 +#define SOR_NV_PDISP_SOR_BLANK_0_TRANSITION_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_BLANK_0_TRANSITION_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_BLANK_0_TRANSITION_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_BLANK_0_TRANSITION_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_BLANK_0_TRANSITION_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_BLANK_0_TRANSITION_INIT_ENUM IMMEDIATE +#define SOR_NV_PDISP_SOR_BLANK_0_TRANSITION_IMMEDIATE _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_BLANK_0_TRANSITION_NEXT_VSYNC _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_BLANK_0_OVERRIDE_SHIFT _MK_SHIFT_CONST(0) +#define SOR_NV_PDISP_SOR_BLANK_0_OVERRIDE_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_BLANK_0_OVERRIDE_SHIFT) +#define SOR_NV_PDISP_SOR_BLANK_0_OVERRIDE_RANGE 0:0 +#define SOR_NV_PDISP_SOR_BLANK_0_OVERRIDE_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_BLANK_0_OVERRIDE_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_BLANK_0_OVERRIDE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_BLANK_0_OVERRIDE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_BLANK_0_OVERRIDE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_BLANK_0_OVERRIDE_INIT_ENUM FALSE +#define SOR_NV_PDISP_SOR_BLANK_0_OVERRIDE_FALSE _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_BLANK_0_OVERRIDE_TRUE _MK_ENUM_CONST(1) + + +// Register SOR_NV_PDISP_SOR_SEQ_CTL_0 +#define SOR_NV_PDISP_SOR_SEQ_CTL_0 _MK_ADDR_CONST(0x20) +#define SOR_NV_PDISP_SOR_SEQ_CTL_0_SECURE 0x0 +#define SOR_NV_PDISP_SOR_SEQ_CTL_0_WORD_COUNT 0x1 +#define SOR_NV_PDISP_SOR_SEQ_CTL_0_RESET_VAL _MK_MASK_CONST(0x8800) +#define SOR_NV_PDISP_SOR_SEQ_CTL_0_RESET_MASK _MK_MASK_CONST(0x1000ffff) +#define SOR_NV_PDISP_SOR_SEQ_CTL_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_CTL_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_CTL_0_READ_MASK _MK_MASK_CONST(0x500fffff) +#define SOR_NV_PDISP_SOR_SEQ_CTL_0_WRITE_MASK _MK_MASK_CONST(0x4000fff0) +#define SOR_NV_PDISP_SOR_SEQ_CTL_0_SWITCH_SHIFT _MK_SHIFT_CONST(30) +#define SOR_NV_PDISP_SOR_SEQ_CTL_0_SWITCH_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_CTL_0_SWITCH_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_CTL_0_SWITCH_RANGE 30:30 +#define SOR_NV_PDISP_SOR_SEQ_CTL_0_SWITCH_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_CTL_0_SWITCH_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_CTL_0_SWITCH_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_CTL_0_SWITCH_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_CTL_0_SWITCH_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_CTL_0_SWITCH_WAIT _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_CTL_0_SWITCH_FORCE _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_CTL_0_STATUS_SHIFT _MK_SHIFT_CONST(28) +#define SOR_NV_PDISP_SOR_SEQ_CTL_0_STATUS_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_CTL_0_STATUS_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_CTL_0_STATUS_RANGE 28:28 +#define SOR_NV_PDISP_SOR_SEQ_CTL_0_STATUS_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_CTL_0_STATUS_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_CTL_0_STATUS_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_CTL_0_STATUS_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_CTL_0_STATUS_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_CTL_0_STATUS_INIT_ENUM STOPPED +#define SOR_NV_PDISP_SOR_SEQ_CTL_0_STATUS_STOPPED _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_CTL_0_STATUS_RUNNING _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_CTL_0_PC_SHIFT _MK_SHIFT_CONST(16) +#define SOR_NV_PDISP_SOR_SEQ_CTL_0_PC_FIELD _MK_FIELD_CONST(0xf, SOR_NV_PDISP_SOR_SEQ_CTL_0_PC_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_CTL_0_PC_RANGE 19:16 +#define SOR_NV_PDISP_SOR_SEQ_CTL_0_PC_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_CTL_0_PC_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_CTL_0_PC_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_CTL_0_PC_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_CTL_0_PC_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define SOR_NV_PDISP_SOR_SEQ_CTL_0_PD_PC_ALT_SHIFT _MK_SHIFT_CONST(12) +#define SOR_NV_PDISP_SOR_SEQ_CTL_0_PD_PC_ALT_FIELD _MK_FIELD_CONST(0xf, SOR_NV_PDISP_SOR_SEQ_CTL_0_PD_PC_ALT_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_CTL_0_PD_PC_ALT_RANGE 15:12 +#define SOR_NV_PDISP_SOR_SEQ_CTL_0_PD_PC_ALT_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_CTL_0_PD_PC_ALT_DEFAULT _MK_MASK_CONST(0x8) +#define SOR_NV_PDISP_SOR_SEQ_CTL_0_PD_PC_ALT_DEFAULT_MASK _MK_MASK_CONST(0xf) +#define SOR_NV_PDISP_SOR_SEQ_CTL_0_PD_PC_ALT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_CTL_0_PD_PC_ALT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define SOR_NV_PDISP_SOR_SEQ_CTL_0_PD_PC_SHIFT _MK_SHIFT_CONST(8) +#define SOR_NV_PDISP_SOR_SEQ_CTL_0_PD_PC_FIELD _MK_FIELD_CONST(0xf, SOR_NV_PDISP_SOR_SEQ_CTL_0_PD_PC_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_CTL_0_PD_PC_RANGE 11:8 +#define SOR_NV_PDISP_SOR_SEQ_CTL_0_PD_PC_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_CTL_0_PD_PC_DEFAULT _MK_MASK_CONST(0x8) +#define SOR_NV_PDISP_SOR_SEQ_CTL_0_PD_PC_DEFAULT_MASK _MK_MASK_CONST(0xf) +#define SOR_NV_PDISP_SOR_SEQ_CTL_0_PD_PC_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_CTL_0_PD_PC_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define SOR_NV_PDISP_SOR_SEQ_CTL_0_PU_PC_ALT_SHIFT _MK_SHIFT_CONST(4) +#define SOR_NV_PDISP_SOR_SEQ_CTL_0_PU_PC_ALT_FIELD _MK_FIELD_CONST(0xf, SOR_NV_PDISP_SOR_SEQ_CTL_0_PU_PC_ALT_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_CTL_0_PU_PC_ALT_RANGE 7:4 +#define SOR_NV_PDISP_SOR_SEQ_CTL_0_PU_PC_ALT_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_CTL_0_PU_PC_ALT_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_CTL_0_PU_PC_ALT_DEFAULT_MASK _MK_MASK_CONST(0xf) +#define SOR_NV_PDISP_SOR_SEQ_CTL_0_PU_PC_ALT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_CTL_0_PU_PC_ALT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define SOR_NV_PDISP_SOR_SEQ_CTL_0_PU_PC_SHIFT _MK_SHIFT_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_CTL_0_PU_PC_FIELD _MK_FIELD_CONST(0xf, SOR_NV_PDISP_SOR_SEQ_CTL_0_PU_PC_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_CTL_0_PU_PC_RANGE 3:0 +#define SOR_NV_PDISP_SOR_SEQ_CTL_0_PU_PC_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_CTL_0_PU_PC_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_CTL_0_PU_PC_DEFAULT_MASK _MK_MASK_CONST(0xf) +#define SOR_NV_PDISP_SOR_SEQ_CTL_0_PU_PC_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_CTL_0_PU_PC_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0 +#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0 _MK_ADDR_CONST(0x21) +#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_SECURE 0x0 +#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_WORD_COUNT 0x1 +#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_RESET_VAL _MK_MASK_CONST(0x11000) +#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_RESET_MASK _MK_MASK_CONST(0x8011f000) +#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_READ_MASK _MK_MASK_CONST(0x9011f3ff) +#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_WRITE_MASK _MK_MASK_CONST(0x8011f000) +#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_SETTING_NEW_SHIFT _MK_SHIFT_CONST(31) +#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_SETTING_NEW_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_SETTING_NEW_SHIFT) +#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_SETTING_NEW_RANGE 31:31 +#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_SETTING_NEW_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_SETTING_NEW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_SETTING_NEW_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_SETTING_NEW_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_SETTING_NEW_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_SETTING_NEW_INIT_ENUM DONE +#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_SETTING_NEW_DONE _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_SETTING_NEW_PENDING _MK_ENUM_CONST(1) +#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_SETTING_NEW_TRIGGER _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_SEQ_STATE_SHIFT _MK_SHIFT_CONST(28) +#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_SEQ_STATE_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_SEQ_STATE_SHIFT) +#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_SEQ_STATE_RANGE 28:28 +#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_SEQ_STATE_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_SEQ_STATE_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_SEQ_STATE_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_SEQ_STATE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_SEQ_STATE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_SEQ_STATE_IDLE _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_SEQ_STATE_BUSY _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_SEQUENCE_SHIFT _MK_SHIFT_CONST(20) +#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_SEQUENCE_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_SEQUENCE_SHIFT) +#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_SEQUENCE_RANGE 20:20 +#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_SEQUENCE_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_SEQUENCE_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_SEQUENCE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_SEQUENCE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_SEQUENCE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_SEQUENCE_INIT_ENUM UP +#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_SEQUENCE_UP _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_SEQUENCE_DOWN _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_NEW_POWER_STATE_SHIFT _MK_SHIFT_CONST(16) +#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_NEW_POWER_STATE_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_NEW_POWER_STATE_SHIFT) +#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_NEW_POWER_STATE_RANGE 16:16 +#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_NEW_POWER_STATE_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_NEW_POWER_STATE_DEFAULT _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_NEW_POWER_STATE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_NEW_POWER_STATE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_NEW_POWER_STATE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_NEW_POWER_STATE_INIT_ENUM PD +#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_NEW_POWER_STATE_PU _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_NEW_POWER_STATE_PD _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_DELAY_SHIFT _MK_SHIFT_CONST(12) +#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_DELAY_FIELD _MK_FIELD_CONST(0xf, SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_DELAY_SHIFT) +#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_DELAY_RANGE 15:12 +#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_DELAY_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_DELAY_DEFAULT _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_DELAY_DEFAULT_MASK _MK_MASK_CONST(0xf) +#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_DELAY_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_DELAY_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE9_STATE_SHIFT _MK_SHIFT_CONST(9) +#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE9_STATE_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE9_STATE_SHIFT) +#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE9_STATE_RANGE 9:9 +#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE9_STATE_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE9_STATE_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE9_STATE_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE9_STATE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE9_STATE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE9_STATE_POWERUP _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE9_STATE_POWERDOWN _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE8_STATE_SHIFT _MK_SHIFT_CONST(8) +#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE8_STATE_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE8_STATE_SHIFT) +#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE8_STATE_RANGE 8:8 +#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE8_STATE_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE8_STATE_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE8_STATE_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE8_STATE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE8_STATE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE8_STATE_POWERUP _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE8_STATE_POWERDOWN _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE7_STATE_SHIFT _MK_SHIFT_CONST(7) +#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE7_STATE_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE7_STATE_SHIFT) +#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE7_STATE_RANGE 7:7 +#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE7_STATE_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE7_STATE_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE7_STATE_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE7_STATE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE7_STATE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE7_STATE_POWERUP _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE7_STATE_POWERDOWN _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE6_STATE_SHIFT _MK_SHIFT_CONST(6) +#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE6_STATE_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE6_STATE_SHIFT) +#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE6_STATE_RANGE 6:6 +#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE6_STATE_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE6_STATE_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE6_STATE_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE6_STATE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE6_STATE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE6_STATE_POWERUP _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE6_STATE_POWERDOWN _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE5_STATE_SHIFT _MK_SHIFT_CONST(5) +#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE5_STATE_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE5_STATE_SHIFT) +#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE5_STATE_RANGE 5:5 +#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE5_STATE_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE5_STATE_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE5_STATE_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE5_STATE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE5_STATE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE5_STATE_POWERUP _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE5_STATE_POWERDOWN _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE4_STATE_SHIFT _MK_SHIFT_CONST(4) +#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE4_STATE_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE4_STATE_SHIFT) +#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE4_STATE_RANGE 4:4 +#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE4_STATE_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE4_STATE_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE4_STATE_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE4_STATE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE4_STATE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE4_STATE_POWERUP _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE4_STATE_POWERDOWN _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE3_STATE_SHIFT _MK_SHIFT_CONST(3) +#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE3_STATE_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE3_STATE_SHIFT) +#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE3_STATE_RANGE 3:3 +#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE3_STATE_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE3_STATE_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE3_STATE_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE3_STATE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE3_STATE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE3_STATE_POWERUP _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE3_STATE_POWERDOWN _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE2_STATE_SHIFT _MK_SHIFT_CONST(2) +#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE2_STATE_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE2_STATE_SHIFT) +#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE2_STATE_RANGE 2:2 +#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE2_STATE_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE2_STATE_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE2_STATE_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE2_STATE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE2_STATE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE2_STATE_POWERUP _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE2_STATE_POWERDOWN _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE1_STATE_SHIFT _MK_SHIFT_CONST(1) +#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE1_STATE_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE1_STATE_SHIFT) +#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE1_STATE_RANGE 1:1 +#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE1_STATE_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE1_STATE_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE1_STATE_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE1_STATE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE1_STATE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE1_STATE_POWERUP _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE1_STATE_POWERDOWN _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE0_STATE_SHIFT _MK_SHIFT_CONST(0) +#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE0_STATE_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE0_STATE_SHIFT) +#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE0_STATE_RANGE 0:0 +#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE0_STATE_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE0_STATE_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE0_STATE_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE0_STATE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE0_STATE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE0_STATE_POWERUP _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0_LANE0_STATE_POWERDOWN _MK_ENUM_CONST(1) + + +// Register SOR_NV_PDISP_SOR_SEQ_INST0_0 +#define SOR_NV_PDISP_SOR_SEQ_INST0_0 _MK_ADDR_CONST(0x22) +#define SOR_NV_PDISP_SOR_SEQ_INST0_0_SECURE 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INST0_0_WORD_COUNT 0x1 +#define SOR_NV_PDISP_SOR_SEQ_INST0_0_RESET_VAL _MK_MASK_CONST(0x1008000) +#define SOR_NV_PDISP_SOR_SEQ_INST0_0_RESET_MASK _MK_MASK_CONST(0xffefb3ff) +#define SOR_NV_PDISP_SOR_SEQ_INST0_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST0_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST0_0_READ_MASK _MK_MASK_CONST(0xffefb3ff) +#define SOR_NV_PDISP_SOR_SEQ_INST0_0_WRITE_MASK _MK_MASK_CONST(0xffefb3ff) +#define SOR_NV_PDISP_SOR_SEQ_INST0_0_PLL_PULLDOWN_SHIFT _MK_SHIFT_CONST(31) +#define SOR_NV_PDISP_SOR_SEQ_INST0_0_PLL_PULLDOWN_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST0_0_PLL_PULLDOWN_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INST0_0_PLL_PULLDOWN_RANGE 31:31 +#define SOR_NV_PDISP_SOR_SEQ_INST0_0_PLL_PULLDOWN_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INST0_0_PLL_PULLDOWN_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST0_0_PLL_PULLDOWN_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INST0_0_PLL_PULLDOWN_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST0_0_PLL_PULLDOWN_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST0_0_PLL_PULLDOWN_INIT_ENUM DISABLE +#define SOR_NV_PDISP_SOR_SEQ_INST0_0_PLL_PULLDOWN_DISABLE _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INST0_0_PLL_PULLDOWN_ENABLE _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INST0_0_POWERDOWN_MACRO_SHIFT _MK_SHIFT_CONST(30) +#define SOR_NV_PDISP_SOR_SEQ_INST0_0_POWERDOWN_MACRO_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST0_0_POWERDOWN_MACRO_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INST0_0_POWERDOWN_MACRO_RANGE 30:30 +#define SOR_NV_PDISP_SOR_SEQ_INST0_0_POWERDOWN_MACRO_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INST0_0_POWERDOWN_MACRO_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST0_0_POWERDOWN_MACRO_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INST0_0_POWERDOWN_MACRO_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST0_0_POWERDOWN_MACRO_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST0_0_POWERDOWN_MACRO_INIT_ENUM NORMAL +#define SOR_NV_PDISP_SOR_SEQ_INST0_0_POWERDOWN_MACRO_NORMAL _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INST0_0_POWERDOWN_MACRO_POWERDOWN _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INST0_0_ASSERT_PLL_RESET_SHIFT _MK_SHIFT_CONST(29) +#define SOR_NV_PDISP_SOR_SEQ_INST0_0_ASSERT_PLL_RESET_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST0_0_ASSERT_PLL_RESET_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INST0_0_ASSERT_PLL_RESET_RANGE 29:29 +#define SOR_NV_PDISP_SOR_SEQ_INST0_0_ASSERT_PLL_RESET_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INST0_0_ASSERT_PLL_RESET_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST0_0_ASSERT_PLL_RESET_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INST0_0_ASSERT_PLL_RESET_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST0_0_ASSERT_PLL_RESET_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST0_0_ASSERT_PLL_RESET_INIT_ENUM NORMAL +#define SOR_NV_PDISP_SOR_SEQ_INST0_0_ASSERT_PLL_RESET_NORMAL _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INST0_0_ASSERT_PLL_RESET_RST _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INST0_0_BLANK_V_SHIFT _MK_SHIFT_CONST(28) +#define SOR_NV_PDISP_SOR_SEQ_INST0_0_BLANK_V_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST0_0_BLANK_V_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INST0_0_BLANK_V_RANGE 28:28 +#define SOR_NV_PDISP_SOR_SEQ_INST0_0_BLANK_V_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INST0_0_BLANK_V_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST0_0_BLANK_V_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INST0_0_BLANK_V_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST0_0_BLANK_V_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST0_0_BLANK_V_INIT_ENUM NORMAL +#define SOR_NV_PDISP_SOR_SEQ_INST0_0_BLANK_V_NORMAL _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INST0_0_BLANK_V_INACTIVE _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INST0_0_BLANK_H_SHIFT _MK_SHIFT_CONST(27) +#define SOR_NV_PDISP_SOR_SEQ_INST0_0_BLANK_H_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST0_0_BLANK_H_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INST0_0_BLANK_H_RANGE 27:27 +#define SOR_NV_PDISP_SOR_SEQ_INST0_0_BLANK_H_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INST0_0_BLANK_H_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST0_0_BLANK_H_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INST0_0_BLANK_H_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST0_0_BLANK_H_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST0_0_BLANK_H_INIT_ENUM NORMAL +#define SOR_NV_PDISP_SOR_SEQ_INST0_0_BLANK_H_NORMAL _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INST0_0_BLANK_H_INACTIVE _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INST0_0_BLANK_DE_SHIFT _MK_SHIFT_CONST(26) +#define SOR_NV_PDISP_SOR_SEQ_INST0_0_BLANK_DE_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST0_0_BLANK_DE_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INST0_0_BLANK_DE_RANGE 26:26 +#define SOR_NV_PDISP_SOR_SEQ_INST0_0_BLANK_DE_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INST0_0_BLANK_DE_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST0_0_BLANK_DE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INST0_0_BLANK_DE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST0_0_BLANK_DE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST0_0_BLANK_DE_INIT_ENUM NORMAL +#define SOR_NV_PDISP_SOR_SEQ_INST0_0_BLANK_DE_NORMAL _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INST0_0_BLANK_DE_INACTIVE _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INST0_0_BLACK_DATA_SHIFT _MK_SHIFT_CONST(25) +#define SOR_NV_PDISP_SOR_SEQ_INST0_0_BLACK_DATA_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST0_0_BLACK_DATA_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INST0_0_BLACK_DATA_RANGE 25:25 +#define SOR_NV_PDISP_SOR_SEQ_INST0_0_BLACK_DATA_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INST0_0_BLACK_DATA_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST0_0_BLACK_DATA_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INST0_0_BLACK_DATA_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST0_0_BLACK_DATA_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST0_0_BLACK_DATA_INIT_ENUM NORMAL +#define SOR_NV_PDISP_SOR_SEQ_INST0_0_BLACK_DATA_NORMAL _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INST0_0_BLACK_DATA_BLACK _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INST0_0_TRISTATE_IOS_SHIFT _MK_SHIFT_CONST(24) +#define SOR_NV_PDISP_SOR_SEQ_INST0_0_TRISTATE_IOS_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST0_0_TRISTATE_IOS_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INST0_0_TRISTATE_IOS_RANGE 24:24 +#define SOR_NV_PDISP_SOR_SEQ_INST0_0_TRISTATE_IOS_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INST0_0_TRISTATE_IOS_DEFAULT _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INST0_0_TRISTATE_IOS_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INST0_0_TRISTATE_IOS_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST0_0_TRISTATE_IOS_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST0_0_TRISTATE_IOS_INIT_ENUM TRISTATE +#define SOR_NV_PDISP_SOR_SEQ_INST0_0_TRISTATE_IOS_ENABLE_PINS _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INST0_0_TRISTATE_IOS_TRISTATE _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INST0_0_DRIVE_PWM_OUT_LO_SHIFT _MK_SHIFT_CONST(23) +#define SOR_NV_PDISP_SOR_SEQ_INST0_0_DRIVE_PWM_OUT_LO_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST0_0_DRIVE_PWM_OUT_LO_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INST0_0_DRIVE_PWM_OUT_LO_RANGE 23:23 +#define SOR_NV_PDISP_SOR_SEQ_INST0_0_DRIVE_PWM_OUT_LO_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INST0_0_DRIVE_PWM_OUT_LO_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST0_0_DRIVE_PWM_OUT_LO_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INST0_0_DRIVE_PWM_OUT_LO_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST0_0_DRIVE_PWM_OUT_LO_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST0_0_DRIVE_PWM_OUT_LO_INIT_ENUM FALSE +#define SOR_NV_PDISP_SOR_SEQ_INST0_0_DRIVE_PWM_OUT_LO_FALSE _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INST0_0_DRIVE_PWM_OUT_LO_TRUE _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INST0_0_PIN_B_SHIFT _MK_SHIFT_CONST(22) +#define SOR_NV_PDISP_SOR_SEQ_INST0_0_PIN_B_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST0_0_PIN_B_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INST0_0_PIN_B_RANGE 22:22 +#define SOR_NV_PDISP_SOR_SEQ_INST0_0_PIN_B_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INST0_0_PIN_B_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST0_0_PIN_B_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INST0_0_PIN_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST0_0_PIN_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST0_0_PIN_B_INIT_ENUM LOW +#define SOR_NV_PDISP_SOR_SEQ_INST0_0_PIN_B_LOW _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INST0_0_PIN_B_HIGH _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INST0_0_PIN_A_SHIFT _MK_SHIFT_CONST(21) +#define SOR_NV_PDISP_SOR_SEQ_INST0_0_PIN_A_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST0_0_PIN_A_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INST0_0_PIN_A_RANGE 21:21 +#define SOR_NV_PDISP_SOR_SEQ_INST0_0_PIN_A_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INST0_0_PIN_A_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST0_0_PIN_A_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INST0_0_PIN_A_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST0_0_PIN_A_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST0_0_PIN_A_INIT_ENUM LOW +#define SOR_NV_PDISP_SOR_SEQ_INST0_0_PIN_A_LOW _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INST0_0_PIN_A_HIGH _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INST0_0_SEQUENCE_SHIFT _MK_SHIFT_CONST(19) +#define SOR_NV_PDISP_SOR_SEQ_INST0_0_SEQUENCE_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST0_0_SEQUENCE_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INST0_0_SEQUENCE_RANGE 19:19 +#define SOR_NV_PDISP_SOR_SEQ_INST0_0_SEQUENCE_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INST0_0_SEQUENCE_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST0_0_SEQUENCE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INST0_0_SEQUENCE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST0_0_SEQUENCE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST0_0_SEQUENCE_INIT_ENUM UP +#define SOR_NV_PDISP_SOR_SEQ_INST0_0_SEQUENCE_UP _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INST0_0_SEQUENCE_DOWN _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INST0_0_LANE_SEQ_SHIFT _MK_SHIFT_CONST(18) +#define SOR_NV_PDISP_SOR_SEQ_INST0_0_LANE_SEQ_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST0_0_LANE_SEQ_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INST0_0_LANE_SEQ_RANGE 18:18 +#define SOR_NV_PDISP_SOR_SEQ_INST0_0_LANE_SEQ_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INST0_0_LANE_SEQ_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST0_0_LANE_SEQ_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INST0_0_LANE_SEQ_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST0_0_LANE_SEQ_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST0_0_LANE_SEQ_INIT_ENUM STOP +#define SOR_NV_PDISP_SOR_SEQ_INST0_0_LANE_SEQ_STOP _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INST0_0_LANE_SEQ_RUN _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INST0_0_PDPORT_SHIFT _MK_SHIFT_CONST(17) +#define SOR_NV_PDISP_SOR_SEQ_INST0_0_PDPORT_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST0_0_PDPORT_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INST0_0_PDPORT_RANGE 17:17 +#define SOR_NV_PDISP_SOR_SEQ_INST0_0_PDPORT_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INST0_0_PDPORT_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST0_0_PDPORT_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INST0_0_PDPORT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST0_0_PDPORT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST0_0_PDPORT_INIT_ENUM NO +#define SOR_NV_PDISP_SOR_SEQ_INST0_0_PDPORT_NO _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INST0_0_PDPORT_YES _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INST0_0_PDPLL_SHIFT _MK_SHIFT_CONST(16) +#define SOR_NV_PDISP_SOR_SEQ_INST0_0_PDPLL_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST0_0_PDPLL_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INST0_0_PDPLL_RANGE 16:16 +#define SOR_NV_PDISP_SOR_SEQ_INST0_0_PDPLL_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INST0_0_PDPLL_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST0_0_PDPLL_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INST0_0_PDPLL_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST0_0_PDPLL_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST0_0_PDPLL_INIT_ENUM NO +#define SOR_NV_PDISP_SOR_SEQ_INST0_0_PDPLL_NO _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INST0_0_PDPLL_YES _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INST0_0_HALT_SHIFT _MK_SHIFT_CONST(15) +#define SOR_NV_PDISP_SOR_SEQ_INST0_0_HALT_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST0_0_HALT_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INST0_0_HALT_RANGE 15:15 +#define SOR_NV_PDISP_SOR_SEQ_INST0_0_HALT_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INST0_0_HALT_DEFAULT _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INST0_0_HALT_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INST0_0_HALT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST0_0_HALT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST0_0_HALT_INIT_ENUM TRUE +#define SOR_NV_PDISP_SOR_SEQ_INST0_0_HALT_FALSE _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INST0_0_HALT_TRUE _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INST0_0_WAIT_UNITS_SHIFT _MK_SHIFT_CONST(12) +#define SOR_NV_PDISP_SOR_SEQ_INST0_0_WAIT_UNITS_FIELD _MK_FIELD_CONST(0x3, SOR_NV_PDISP_SOR_SEQ_INST0_0_WAIT_UNITS_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INST0_0_WAIT_UNITS_RANGE 13:12 +#define SOR_NV_PDISP_SOR_SEQ_INST0_0_WAIT_UNITS_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INST0_0_WAIT_UNITS_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST0_0_WAIT_UNITS_DEFAULT_MASK _MK_MASK_CONST(0x3) +#define SOR_NV_PDISP_SOR_SEQ_INST0_0_WAIT_UNITS_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST0_0_WAIT_UNITS_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST0_0_WAIT_UNITS_INIT_ENUM US +#define SOR_NV_PDISP_SOR_SEQ_INST0_0_WAIT_UNITS_US _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INST0_0_WAIT_UNITS_MS _MK_ENUM_CONST(1) +#define SOR_NV_PDISP_SOR_SEQ_INST0_0_WAIT_UNITS_VSYNC _MK_ENUM_CONST(2) + +#define SOR_NV_PDISP_SOR_SEQ_INST0_0_WAIT_TIME_SHIFT _MK_SHIFT_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INST0_0_WAIT_TIME_FIELD _MK_FIELD_CONST(0x3ff, SOR_NV_PDISP_SOR_SEQ_INST0_0_WAIT_TIME_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INST0_0_WAIT_TIME_RANGE 9:0 +#define SOR_NV_PDISP_SOR_SEQ_INST0_0_WAIT_TIME_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INST0_0_WAIT_TIME_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST0_0_WAIT_TIME_DEFAULT_MASK _MK_MASK_CONST(0x3ff) +#define SOR_NV_PDISP_SOR_SEQ_INST0_0_WAIT_TIME_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST0_0_WAIT_TIME_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register SOR_NV_PDISP_SOR_SEQ_INST1_0 +#define SOR_NV_PDISP_SOR_SEQ_INST1_0 _MK_ADDR_CONST(0x23) +#define SOR_NV_PDISP_SOR_SEQ_INST1_0_SECURE 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INST1_0_WORD_COUNT 0x1 +#define SOR_NV_PDISP_SOR_SEQ_INST1_0_RESET_VAL _MK_MASK_CONST(0x1008000) +#define SOR_NV_PDISP_SOR_SEQ_INST1_0_RESET_MASK _MK_MASK_CONST(0xffefb3ff) +#define SOR_NV_PDISP_SOR_SEQ_INST1_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST1_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST1_0_READ_MASK _MK_MASK_CONST(0xffefb3ff) +#define SOR_NV_PDISP_SOR_SEQ_INST1_0_WRITE_MASK _MK_MASK_CONST(0xffefb3ff) +#define SOR_NV_PDISP_SOR_SEQ_INST1_0_PLL_PULLDOWN_SHIFT _MK_SHIFT_CONST(31) +#define SOR_NV_PDISP_SOR_SEQ_INST1_0_PLL_PULLDOWN_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST1_0_PLL_PULLDOWN_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INST1_0_PLL_PULLDOWN_RANGE 31:31 +#define SOR_NV_PDISP_SOR_SEQ_INST1_0_PLL_PULLDOWN_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INST1_0_PLL_PULLDOWN_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST1_0_PLL_PULLDOWN_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INST1_0_PLL_PULLDOWN_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST1_0_PLL_PULLDOWN_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST1_0_PLL_PULLDOWN_INIT_ENUM DISABLE +#define SOR_NV_PDISP_SOR_SEQ_INST1_0_PLL_PULLDOWN_DISABLE _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INST1_0_PLL_PULLDOWN_ENABLE _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INST1_0_POWERDOWN_MACRO_SHIFT _MK_SHIFT_CONST(30) +#define SOR_NV_PDISP_SOR_SEQ_INST1_0_POWERDOWN_MACRO_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST1_0_POWERDOWN_MACRO_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INST1_0_POWERDOWN_MACRO_RANGE 30:30 +#define SOR_NV_PDISP_SOR_SEQ_INST1_0_POWERDOWN_MACRO_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INST1_0_POWERDOWN_MACRO_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST1_0_POWERDOWN_MACRO_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INST1_0_POWERDOWN_MACRO_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST1_0_POWERDOWN_MACRO_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST1_0_POWERDOWN_MACRO_INIT_ENUM NORMAL +#define SOR_NV_PDISP_SOR_SEQ_INST1_0_POWERDOWN_MACRO_NORMAL _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INST1_0_POWERDOWN_MACRO_POWERDOWN _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INST1_0_ASSERT_PLL_RESET_SHIFT _MK_SHIFT_CONST(29) +#define SOR_NV_PDISP_SOR_SEQ_INST1_0_ASSERT_PLL_RESET_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST1_0_ASSERT_PLL_RESET_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INST1_0_ASSERT_PLL_RESET_RANGE 29:29 +#define SOR_NV_PDISP_SOR_SEQ_INST1_0_ASSERT_PLL_RESET_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INST1_0_ASSERT_PLL_RESET_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST1_0_ASSERT_PLL_RESET_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INST1_0_ASSERT_PLL_RESET_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST1_0_ASSERT_PLL_RESET_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST1_0_ASSERT_PLL_RESET_INIT_ENUM NORMAL +#define SOR_NV_PDISP_SOR_SEQ_INST1_0_ASSERT_PLL_RESET_NORMAL _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INST1_0_ASSERT_PLL_RESET_RST _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INST1_0_BLANK_V_SHIFT _MK_SHIFT_CONST(28) +#define SOR_NV_PDISP_SOR_SEQ_INST1_0_BLANK_V_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST1_0_BLANK_V_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INST1_0_BLANK_V_RANGE 28:28 +#define SOR_NV_PDISP_SOR_SEQ_INST1_0_BLANK_V_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INST1_0_BLANK_V_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST1_0_BLANK_V_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INST1_0_BLANK_V_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST1_0_BLANK_V_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST1_0_BLANK_V_INIT_ENUM NORMAL +#define SOR_NV_PDISP_SOR_SEQ_INST1_0_BLANK_V_NORMAL _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INST1_0_BLANK_V_INACTIVE _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INST1_0_BLANK_H_SHIFT _MK_SHIFT_CONST(27) +#define SOR_NV_PDISP_SOR_SEQ_INST1_0_BLANK_H_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST1_0_BLANK_H_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INST1_0_BLANK_H_RANGE 27:27 +#define SOR_NV_PDISP_SOR_SEQ_INST1_0_BLANK_H_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INST1_0_BLANK_H_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST1_0_BLANK_H_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INST1_0_BLANK_H_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST1_0_BLANK_H_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST1_0_BLANK_H_INIT_ENUM NORMAL +#define SOR_NV_PDISP_SOR_SEQ_INST1_0_BLANK_H_NORMAL _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INST1_0_BLANK_H_INACTIVE _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INST1_0_BLANK_DE_SHIFT _MK_SHIFT_CONST(26) +#define SOR_NV_PDISP_SOR_SEQ_INST1_0_BLANK_DE_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST1_0_BLANK_DE_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INST1_0_BLANK_DE_RANGE 26:26 +#define SOR_NV_PDISP_SOR_SEQ_INST1_0_BLANK_DE_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INST1_0_BLANK_DE_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST1_0_BLANK_DE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INST1_0_BLANK_DE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST1_0_BLANK_DE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST1_0_BLANK_DE_INIT_ENUM NORMAL +#define SOR_NV_PDISP_SOR_SEQ_INST1_0_BLANK_DE_NORMAL _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INST1_0_BLANK_DE_INACTIVE _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INST1_0_BLACK_DATA_SHIFT _MK_SHIFT_CONST(25) +#define SOR_NV_PDISP_SOR_SEQ_INST1_0_BLACK_DATA_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST1_0_BLACK_DATA_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INST1_0_BLACK_DATA_RANGE 25:25 +#define SOR_NV_PDISP_SOR_SEQ_INST1_0_BLACK_DATA_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INST1_0_BLACK_DATA_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST1_0_BLACK_DATA_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INST1_0_BLACK_DATA_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST1_0_BLACK_DATA_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST1_0_BLACK_DATA_INIT_ENUM NORMAL +#define SOR_NV_PDISP_SOR_SEQ_INST1_0_BLACK_DATA_NORMAL _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INST1_0_BLACK_DATA_BLACK _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INST1_0_TRISTATE_IOS_SHIFT _MK_SHIFT_CONST(24) +#define SOR_NV_PDISP_SOR_SEQ_INST1_0_TRISTATE_IOS_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST1_0_TRISTATE_IOS_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INST1_0_TRISTATE_IOS_RANGE 24:24 +#define SOR_NV_PDISP_SOR_SEQ_INST1_0_TRISTATE_IOS_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INST1_0_TRISTATE_IOS_DEFAULT _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INST1_0_TRISTATE_IOS_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INST1_0_TRISTATE_IOS_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST1_0_TRISTATE_IOS_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST1_0_TRISTATE_IOS_INIT_ENUM TRISTATE +#define SOR_NV_PDISP_SOR_SEQ_INST1_0_TRISTATE_IOS_ENABLE_PINS _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INST1_0_TRISTATE_IOS_TRISTATE _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INST1_0_DRIVE_PWM_OUT_LO_SHIFT _MK_SHIFT_CONST(23) +#define SOR_NV_PDISP_SOR_SEQ_INST1_0_DRIVE_PWM_OUT_LO_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST1_0_DRIVE_PWM_OUT_LO_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INST1_0_DRIVE_PWM_OUT_LO_RANGE 23:23 +#define SOR_NV_PDISP_SOR_SEQ_INST1_0_DRIVE_PWM_OUT_LO_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INST1_0_DRIVE_PWM_OUT_LO_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST1_0_DRIVE_PWM_OUT_LO_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INST1_0_DRIVE_PWM_OUT_LO_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST1_0_DRIVE_PWM_OUT_LO_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST1_0_DRIVE_PWM_OUT_LO_INIT_ENUM FALSE +#define SOR_NV_PDISP_SOR_SEQ_INST1_0_DRIVE_PWM_OUT_LO_FALSE _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INST1_0_DRIVE_PWM_OUT_LO_TRUE _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INST1_0_PIN_B_SHIFT _MK_SHIFT_CONST(22) +#define SOR_NV_PDISP_SOR_SEQ_INST1_0_PIN_B_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST1_0_PIN_B_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INST1_0_PIN_B_RANGE 22:22 +#define SOR_NV_PDISP_SOR_SEQ_INST1_0_PIN_B_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INST1_0_PIN_B_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST1_0_PIN_B_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INST1_0_PIN_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST1_0_PIN_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST1_0_PIN_B_INIT_ENUM LOW +#define SOR_NV_PDISP_SOR_SEQ_INST1_0_PIN_B_LOW _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INST1_0_PIN_B_HIGH _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INST1_0_PIN_A_SHIFT _MK_SHIFT_CONST(21) +#define SOR_NV_PDISP_SOR_SEQ_INST1_0_PIN_A_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST1_0_PIN_A_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INST1_0_PIN_A_RANGE 21:21 +#define SOR_NV_PDISP_SOR_SEQ_INST1_0_PIN_A_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INST1_0_PIN_A_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST1_0_PIN_A_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INST1_0_PIN_A_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST1_0_PIN_A_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST1_0_PIN_A_INIT_ENUM LOW +#define SOR_NV_PDISP_SOR_SEQ_INST1_0_PIN_A_LOW _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INST1_0_PIN_A_HIGH _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INST1_0_SEQUENCE_SHIFT _MK_SHIFT_CONST(19) +#define SOR_NV_PDISP_SOR_SEQ_INST1_0_SEQUENCE_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST1_0_SEQUENCE_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INST1_0_SEQUENCE_RANGE 19:19 +#define SOR_NV_PDISP_SOR_SEQ_INST1_0_SEQUENCE_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INST1_0_SEQUENCE_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST1_0_SEQUENCE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INST1_0_SEQUENCE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST1_0_SEQUENCE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST1_0_SEQUENCE_INIT_ENUM UP +#define SOR_NV_PDISP_SOR_SEQ_INST1_0_SEQUENCE_UP _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INST1_0_SEQUENCE_DOWN _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INST1_0_LANE_SEQ_SHIFT _MK_SHIFT_CONST(18) +#define SOR_NV_PDISP_SOR_SEQ_INST1_0_LANE_SEQ_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST1_0_LANE_SEQ_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INST1_0_LANE_SEQ_RANGE 18:18 +#define SOR_NV_PDISP_SOR_SEQ_INST1_0_LANE_SEQ_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INST1_0_LANE_SEQ_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST1_0_LANE_SEQ_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INST1_0_LANE_SEQ_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST1_0_LANE_SEQ_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST1_0_LANE_SEQ_INIT_ENUM STOP +#define SOR_NV_PDISP_SOR_SEQ_INST1_0_LANE_SEQ_STOP _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INST1_0_LANE_SEQ_RUN _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INST1_0_PDPORT_SHIFT _MK_SHIFT_CONST(17) +#define SOR_NV_PDISP_SOR_SEQ_INST1_0_PDPORT_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST1_0_PDPORT_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INST1_0_PDPORT_RANGE 17:17 +#define SOR_NV_PDISP_SOR_SEQ_INST1_0_PDPORT_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INST1_0_PDPORT_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST1_0_PDPORT_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INST1_0_PDPORT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST1_0_PDPORT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST1_0_PDPORT_INIT_ENUM NO +#define SOR_NV_PDISP_SOR_SEQ_INST1_0_PDPORT_NO _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INST1_0_PDPORT_YES _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INST1_0_PDPLL_SHIFT _MK_SHIFT_CONST(16) +#define SOR_NV_PDISP_SOR_SEQ_INST1_0_PDPLL_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST1_0_PDPLL_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INST1_0_PDPLL_RANGE 16:16 +#define SOR_NV_PDISP_SOR_SEQ_INST1_0_PDPLL_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INST1_0_PDPLL_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST1_0_PDPLL_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INST1_0_PDPLL_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST1_0_PDPLL_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST1_0_PDPLL_INIT_ENUM NO +#define SOR_NV_PDISP_SOR_SEQ_INST1_0_PDPLL_NO _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INST1_0_PDPLL_YES _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INST1_0_HALT_SHIFT _MK_SHIFT_CONST(15) +#define SOR_NV_PDISP_SOR_SEQ_INST1_0_HALT_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST1_0_HALT_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INST1_0_HALT_RANGE 15:15 +#define SOR_NV_PDISP_SOR_SEQ_INST1_0_HALT_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INST1_0_HALT_DEFAULT _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INST1_0_HALT_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INST1_0_HALT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST1_0_HALT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST1_0_HALT_INIT_ENUM TRUE +#define SOR_NV_PDISP_SOR_SEQ_INST1_0_HALT_FALSE _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INST1_0_HALT_TRUE _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INST1_0_WAIT_UNITS_SHIFT _MK_SHIFT_CONST(12) +#define SOR_NV_PDISP_SOR_SEQ_INST1_0_WAIT_UNITS_FIELD _MK_FIELD_CONST(0x3, SOR_NV_PDISP_SOR_SEQ_INST1_0_WAIT_UNITS_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INST1_0_WAIT_UNITS_RANGE 13:12 +#define SOR_NV_PDISP_SOR_SEQ_INST1_0_WAIT_UNITS_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INST1_0_WAIT_UNITS_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST1_0_WAIT_UNITS_DEFAULT_MASK _MK_MASK_CONST(0x3) +#define SOR_NV_PDISP_SOR_SEQ_INST1_0_WAIT_UNITS_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST1_0_WAIT_UNITS_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST1_0_WAIT_UNITS_INIT_ENUM US +#define SOR_NV_PDISP_SOR_SEQ_INST1_0_WAIT_UNITS_US _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INST1_0_WAIT_UNITS_MS _MK_ENUM_CONST(1) +#define SOR_NV_PDISP_SOR_SEQ_INST1_0_WAIT_UNITS_VSYNC _MK_ENUM_CONST(2) + +#define SOR_NV_PDISP_SOR_SEQ_INST1_0_WAIT_TIME_SHIFT _MK_SHIFT_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INST1_0_WAIT_TIME_FIELD _MK_FIELD_CONST(0x3ff, SOR_NV_PDISP_SOR_SEQ_INST1_0_WAIT_TIME_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INST1_0_WAIT_TIME_RANGE 9:0 +#define SOR_NV_PDISP_SOR_SEQ_INST1_0_WAIT_TIME_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INST1_0_WAIT_TIME_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST1_0_WAIT_TIME_DEFAULT_MASK _MK_MASK_CONST(0x3ff) +#define SOR_NV_PDISP_SOR_SEQ_INST1_0_WAIT_TIME_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST1_0_WAIT_TIME_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register SOR_NV_PDISP_SOR_SEQ_INST2_0 +#define SOR_NV_PDISP_SOR_SEQ_INST2_0 _MK_ADDR_CONST(0x24) +#define SOR_NV_PDISP_SOR_SEQ_INST2_0_SECURE 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INST2_0_WORD_COUNT 0x1 +#define SOR_NV_PDISP_SOR_SEQ_INST2_0_RESET_VAL _MK_MASK_CONST(0x1008000) +#define SOR_NV_PDISP_SOR_SEQ_INST2_0_RESET_MASK _MK_MASK_CONST(0xffefb3ff) +#define SOR_NV_PDISP_SOR_SEQ_INST2_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST2_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST2_0_READ_MASK _MK_MASK_CONST(0xffefb3ff) +#define SOR_NV_PDISP_SOR_SEQ_INST2_0_WRITE_MASK _MK_MASK_CONST(0xffefb3ff) +#define SOR_NV_PDISP_SOR_SEQ_INST2_0_PLL_PULLDOWN_SHIFT _MK_SHIFT_CONST(31) +#define SOR_NV_PDISP_SOR_SEQ_INST2_0_PLL_PULLDOWN_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST2_0_PLL_PULLDOWN_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INST2_0_PLL_PULLDOWN_RANGE 31:31 +#define SOR_NV_PDISP_SOR_SEQ_INST2_0_PLL_PULLDOWN_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INST2_0_PLL_PULLDOWN_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST2_0_PLL_PULLDOWN_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INST2_0_PLL_PULLDOWN_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST2_0_PLL_PULLDOWN_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST2_0_PLL_PULLDOWN_INIT_ENUM DISABLE +#define SOR_NV_PDISP_SOR_SEQ_INST2_0_PLL_PULLDOWN_DISABLE _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INST2_0_PLL_PULLDOWN_ENABLE _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INST2_0_POWERDOWN_MACRO_SHIFT _MK_SHIFT_CONST(30) +#define SOR_NV_PDISP_SOR_SEQ_INST2_0_POWERDOWN_MACRO_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST2_0_POWERDOWN_MACRO_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INST2_0_POWERDOWN_MACRO_RANGE 30:30 +#define SOR_NV_PDISP_SOR_SEQ_INST2_0_POWERDOWN_MACRO_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INST2_0_POWERDOWN_MACRO_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST2_0_POWERDOWN_MACRO_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INST2_0_POWERDOWN_MACRO_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST2_0_POWERDOWN_MACRO_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST2_0_POWERDOWN_MACRO_INIT_ENUM NORMAL +#define SOR_NV_PDISP_SOR_SEQ_INST2_0_POWERDOWN_MACRO_NORMAL _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INST2_0_POWERDOWN_MACRO_POWERDOWN _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INST2_0_ASSERT_PLL_RESET_SHIFT _MK_SHIFT_CONST(29) +#define SOR_NV_PDISP_SOR_SEQ_INST2_0_ASSERT_PLL_RESET_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST2_0_ASSERT_PLL_RESET_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INST2_0_ASSERT_PLL_RESET_RANGE 29:29 +#define SOR_NV_PDISP_SOR_SEQ_INST2_0_ASSERT_PLL_RESET_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INST2_0_ASSERT_PLL_RESET_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST2_0_ASSERT_PLL_RESET_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INST2_0_ASSERT_PLL_RESET_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST2_0_ASSERT_PLL_RESET_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST2_0_ASSERT_PLL_RESET_INIT_ENUM NORMAL +#define SOR_NV_PDISP_SOR_SEQ_INST2_0_ASSERT_PLL_RESET_NORMAL _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INST2_0_ASSERT_PLL_RESET_RST _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INST2_0_BLANK_V_SHIFT _MK_SHIFT_CONST(28) +#define SOR_NV_PDISP_SOR_SEQ_INST2_0_BLANK_V_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST2_0_BLANK_V_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INST2_0_BLANK_V_RANGE 28:28 +#define SOR_NV_PDISP_SOR_SEQ_INST2_0_BLANK_V_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INST2_0_BLANK_V_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST2_0_BLANK_V_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INST2_0_BLANK_V_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST2_0_BLANK_V_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST2_0_BLANK_V_INIT_ENUM NORMAL +#define SOR_NV_PDISP_SOR_SEQ_INST2_0_BLANK_V_NORMAL _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INST2_0_BLANK_V_INACTIVE _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INST2_0_BLANK_H_SHIFT _MK_SHIFT_CONST(27) +#define SOR_NV_PDISP_SOR_SEQ_INST2_0_BLANK_H_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST2_0_BLANK_H_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INST2_0_BLANK_H_RANGE 27:27 +#define SOR_NV_PDISP_SOR_SEQ_INST2_0_BLANK_H_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INST2_0_BLANK_H_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST2_0_BLANK_H_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INST2_0_BLANK_H_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST2_0_BLANK_H_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST2_0_BLANK_H_INIT_ENUM NORMAL +#define SOR_NV_PDISP_SOR_SEQ_INST2_0_BLANK_H_NORMAL _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INST2_0_BLANK_H_INACTIVE _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INST2_0_BLANK_DE_SHIFT _MK_SHIFT_CONST(26) +#define SOR_NV_PDISP_SOR_SEQ_INST2_0_BLANK_DE_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST2_0_BLANK_DE_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INST2_0_BLANK_DE_RANGE 26:26 +#define SOR_NV_PDISP_SOR_SEQ_INST2_0_BLANK_DE_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INST2_0_BLANK_DE_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST2_0_BLANK_DE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INST2_0_BLANK_DE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST2_0_BLANK_DE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST2_0_BLANK_DE_INIT_ENUM NORMAL +#define SOR_NV_PDISP_SOR_SEQ_INST2_0_BLANK_DE_NORMAL _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INST2_0_BLANK_DE_INACTIVE _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INST2_0_BLACK_DATA_SHIFT _MK_SHIFT_CONST(25) +#define SOR_NV_PDISP_SOR_SEQ_INST2_0_BLACK_DATA_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST2_0_BLACK_DATA_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INST2_0_BLACK_DATA_RANGE 25:25 +#define SOR_NV_PDISP_SOR_SEQ_INST2_0_BLACK_DATA_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INST2_0_BLACK_DATA_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST2_0_BLACK_DATA_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INST2_0_BLACK_DATA_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST2_0_BLACK_DATA_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST2_0_BLACK_DATA_INIT_ENUM NORMAL +#define SOR_NV_PDISP_SOR_SEQ_INST2_0_BLACK_DATA_NORMAL _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INST2_0_BLACK_DATA_BLACK _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INST2_0_TRISTATE_IOS_SHIFT _MK_SHIFT_CONST(24) +#define SOR_NV_PDISP_SOR_SEQ_INST2_0_TRISTATE_IOS_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST2_0_TRISTATE_IOS_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INST2_0_TRISTATE_IOS_RANGE 24:24 +#define SOR_NV_PDISP_SOR_SEQ_INST2_0_TRISTATE_IOS_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INST2_0_TRISTATE_IOS_DEFAULT _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INST2_0_TRISTATE_IOS_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INST2_0_TRISTATE_IOS_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST2_0_TRISTATE_IOS_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST2_0_TRISTATE_IOS_INIT_ENUM TRISTATE +#define SOR_NV_PDISP_SOR_SEQ_INST2_0_TRISTATE_IOS_ENABLE_PINS _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INST2_0_TRISTATE_IOS_TRISTATE _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INST2_0_DRIVE_PWM_OUT_LO_SHIFT _MK_SHIFT_CONST(23) +#define SOR_NV_PDISP_SOR_SEQ_INST2_0_DRIVE_PWM_OUT_LO_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST2_0_DRIVE_PWM_OUT_LO_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INST2_0_DRIVE_PWM_OUT_LO_RANGE 23:23 +#define SOR_NV_PDISP_SOR_SEQ_INST2_0_DRIVE_PWM_OUT_LO_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INST2_0_DRIVE_PWM_OUT_LO_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST2_0_DRIVE_PWM_OUT_LO_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INST2_0_DRIVE_PWM_OUT_LO_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST2_0_DRIVE_PWM_OUT_LO_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST2_0_DRIVE_PWM_OUT_LO_INIT_ENUM FALSE +#define SOR_NV_PDISP_SOR_SEQ_INST2_0_DRIVE_PWM_OUT_LO_FALSE _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INST2_0_DRIVE_PWM_OUT_LO_TRUE _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INST2_0_PIN_B_SHIFT _MK_SHIFT_CONST(22) +#define SOR_NV_PDISP_SOR_SEQ_INST2_0_PIN_B_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST2_0_PIN_B_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INST2_0_PIN_B_RANGE 22:22 +#define SOR_NV_PDISP_SOR_SEQ_INST2_0_PIN_B_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INST2_0_PIN_B_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST2_0_PIN_B_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INST2_0_PIN_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST2_0_PIN_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST2_0_PIN_B_INIT_ENUM LOW +#define SOR_NV_PDISP_SOR_SEQ_INST2_0_PIN_B_LOW _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INST2_0_PIN_B_HIGH _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INST2_0_PIN_A_SHIFT _MK_SHIFT_CONST(21) +#define SOR_NV_PDISP_SOR_SEQ_INST2_0_PIN_A_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST2_0_PIN_A_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INST2_0_PIN_A_RANGE 21:21 +#define SOR_NV_PDISP_SOR_SEQ_INST2_0_PIN_A_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INST2_0_PIN_A_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST2_0_PIN_A_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INST2_0_PIN_A_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST2_0_PIN_A_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST2_0_PIN_A_INIT_ENUM LOW +#define SOR_NV_PDISP_SOR_SEQ_INST2_0_PIN_A_LOW _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INST2_0_PIN_A_HIGH _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INST2_0_SEQUENCE_SHIFT _MK_SHIFT_CONST(19) +#define SOR_NV_PDISP_SOR_SEQ_INST2_0_SEQUENCE_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST2_0_SEQUENCE_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INST2_0_SEQUENCE_RANGE 19:19 +#define SOR_NV_PDISP_SOR_SEQ_INST2_0_SEQUENCE_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INST2_0_SEQUENCE_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST2_0_SEQUENCE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INST2_0_SEQUENCE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST2_0_SEQUENCE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST2_0_SEQUENCE_INIT_ENUM UP +#define SOR_NV_PDISP_SOR_SEQ_INST2_0_SEQUENCE_UP _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INST2_0_SEQUENCE_DOWN _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INST2_0_LANE_SEQ_SHIFT _MK_SHIFT_CONST(18) +#define SOR_NV_PDISP_SOR_SEQ_INST2_0_LANE_SEQ_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST2_0_LANE_SEQ_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INST2_0_LANE_SEQ_RANGE 18:18 +#define SOR_NV_PDISP_SOR_SEQ_INST2_0_LANE_SEQ_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INST2_0_LANE_SEQ_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST2_0_LANE_SEQ_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INST2_0_LANE_SEQ_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST2_0_LANE_SEQ_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST2_0_LANE_SEQ_INIT_ENUM STOP +#define SOR_NV_PDISP_SOR_SEQ_INST2_0_LANE_SEQ_STOP _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INST2_0_LANE_SEQ_RUN _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INST2_0_PDPORT_SHIFT _MK_SHIFT_CONST(17) +#define SOR_NV_PDISP_SOR_SEQ_INST2_0_PDPORT_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST2_0_PDPORT_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INST2_0_PDPORT_RANGE 17:17 +#define SOR_NV_PDISP_SOR_SEQ_INST2_0_PDPORT_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INST2_0_PDPORT_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST2_0_PDPORT_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INST2_0_PDPORT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST2_0_PDPORT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST2_0_PDPORT_INIT_ENUM NO +#define SOR_NV_PDISP_SOR_SEQ_INST2_0_PDPORT_NO _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INST2_0_PDPORT_YES _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INST2_0_PDPLL_SHIFT _MK_SHIFT_CONST(16) +#define SOR_NV_PDISP_SOR_SEQ_INST2_0_PDPLL_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST2_0_PDPLL_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INST2_0_PDPLL_RANGE 16:16 +#define SOR_NV_PDISP_SOR_SEQ_INST2_0_PDPLL_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INST2_0_PDPLL_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST2_0_PDPLL_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INST2_0_PDPLL_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST2_0_PDPLL_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST2_0_PDPLL_INIT_ENUM NO +#define SOR_NV_PDISP_SOR_SEQ_INST2_0_PDPLL_NO _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INST2_0_PDPLL_YES _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INST2_0_HALT_SHIFT _MK_SHIFT_CONST(15) +#define SOR_NV_PDISP_SOR_SEQ_INST2_0_HALT_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST2_0_HALT_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INST2_0_HALT_RANGE 15:15 +#define SOR_NV_PDISP_SOR_SEQ_INST2_0_HALT_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INST2_0_HALT_DEFAULT _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INST2_0_HALT_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INST2_0_HALT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST2_0_HALT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST2_0_HALT_INIT_ENUM TRUE +#define SOR_NV_PDISP_SOR_SEQ_INST2_0_HALT_FALSE _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INST2_0_HALT_TRUE _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INST2_0_WAIT_UNITS_SHIFT _MK_SHIFT_CONST(12) +#define SOR_NV_PDISP_SOR_SEQ_INST2_0_WAIT_UNITS_FIELD _MK_FIELD_CONST(0x3, SOR_NV_PDISP_SOR_SEQ_INST2_0_WAIT_UNITS_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INST2_0_WAIT_UNITS_RANGE 13:12 +#define SOR_NV_PDISP_SOR_SEQ_INST2_0_WAIT_UNITS_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INST2_0_WAIT_UNITS_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST2_0_WAIT_UNITS_DEFAULT_MASK _MK_MASK_CONST(0x3) +#define SOR_NV_PDISP_SOR_SEQ_INST2_0_WAIT_UNITS_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST2_0_WAIT_UNITS_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST2_0_WAIT_UNITS_INIT_ENUM US +#define SOR_NV_PDISP_SOR_SEQ_INST2_0_WAIT_UNITS_US _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INST2_0_WAIT_UNITS_MS _MK_ENUM_CONST(1) +#define SOR_NV_PDISP_SOR_SEQ_INST2_0_WAIT_UNITS_VSYNC _MK_ENUM_CONST(2) + +#define SOR_NV_PDISP_SOR_SEQ_INST2_0_WAIT_TIME_SHIFT _MK_SHIFT_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INST2_0_WAIT_TIME_FIELD _MK_FIELD_CONST(0x3ff, SOR_NV_PDISP_SOR_SEQ_INST2_0_WAIT_TIME_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INST2_0_WAIT_TIME_RANGE 9:0 +#define SOR_NV_PDISP_SOR_SEQ_INST2_0_WAIT_TIME_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INST2_0_WAIT_TIME_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST2_0_WAIT_TIME_DEFAULT_MASK _MK_MASK_CONST(0x3ff) +#define SOR_NV_PDISP_SOR_SEQ_INST2_0_WAIT_TIME_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST2_0_WAIT_TIME_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register SOR_NV_PDISP_SOR_SEQ_INST3_0 +#define SOR_NV_PDISP_SOR_SEQ_INST3_0 _MK_ADDR_CONST(0x25) +#define SOR_NV_PDISP_SOR_SEQ_INST3_0_SECURE 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INST3_0_WORD_COUNT 0x1 +#define SOR_NV_PDISP_SOR_SEQ_INST3_0_RESET_VAL _MK_MASK_CONST(0x1008000) +#define SOR_NV_PDISP_SOR_SEQ_INST3_0_RESET_MASK _MK_MASK_CONST(0xffefb3ff) +#define SOR_NV_PDISP_SOR_SEQ_INST3_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST3_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST3_0_READ_MASK _MK_MASK_CONST(0xffefb3ff) +#define SOR_NV_PDISP_SOR_SEQ_INST3_0_WRITE_MASK _MK_MASK_CONST(0xffefb3ff) +#define SOR_NV_PDISP_SOR_SEQ_INST3_0_PLL_PULLDOWN_SHIFT _MK_SHIFT_CONST(31) +#define SOR_NV_PDISP_SOR_SEQ_INST3_0_PLL_PULLDOWN_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST3_0_PLL_PULLDOWN_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INST3_0_PLL_PULLDOWN_RANGE 31:31 +#define SOR_NV_PDISP_SOR_SEQ_INST3_0_PLL_PULLDOWN_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INST3_0_PLL_PULLDOWN_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST3_0_PLL_PULLDOWN_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INST3_0_PLL_PULLDOWN_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST3_0_PLL_PULLDOWN_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST3_0_PLL_PULLDOWN_INIT_ENUM DISABLE +#define SOR_NV_PDISP_SOR_SEQ_INST3_0_PLL_PULLDOWN_DISABLE _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INST3_0_PLL_PULLDOWN_ENABLE _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INST3_0_POWERDOWN_MACRO_SHIFT _MK_SHIFT_CONST(30) +#define SOR_NV_PDISP_SOR_SEQ_INST3_0_POWERDOWN_MACRO_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST3_0_POWERDOWN_MACRO_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INST3_0_POWERDOWN_MACRO_RANGE 30:30 +#define SOR_NV_PDISP_SOR_SEQ_INST3_0_POWERDOWN_MACRO_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INST3_0_POWERDOWN_MACRO_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST3_0_POWERDOWN_MACRO_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INST3_0_POWERDOWN_MACRO_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST3_0_POWERDOWN_MACRO_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST3_0_POWERDOWN_MACRO_INIT_ENUM NORMAL +#define SOR_NV_PDISP_SOR_SEQ_INST3_0_POWERDOWN_MACRO_NORMAL _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INST3_0_POWERDOWN_MACRO_POWERDOWN _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INST3_0_ASSERT_PLL_RESET_SHIFT _MK_SHIFT_CONST(29) +#define SOR_NV_PDISP_SOR_SEQ_INST3_0_ASSERT_PLL_RESET_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST3_0_ASSERT_PLL_RESET_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INST3_0_ASSERT_PLL_RESET_RANGE 29:29 +#define SOR_NV_PDISP_SOR_SEQ_INST3_0_ASSERT_PLL_RESET_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INST3_0_ASSERT_PLL_RESET_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST3_0_ASSERT_PLL_RESET_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INST3_0_ASSERT_PLL_RESET_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST3_0_ASSERT_PLL_RESET_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST3_0_ASSERT_PLL_RESET_INIT_ENUM NORMAL +#define SOR_NV_PDISP_SOR_SEQ_INST3_0_ASSERT_PLL_RESET_NORMAL _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INST3_0_ASSERT_PLL_RESET_RST _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INST3_0_BLANK_V_SHIFT _MK_SHIFT_CONST(28) +#define SOR_NV_PDISP_SOR_SEQ_INST3_0_BLANK_V_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST3_0_BLANK_V_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INST3_0_BLANK_V_RANGE 28:28 +#define SOR_NV_PDISP_SOR_SEQ_INST3_0_BLANK_V_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INST3_0_BLANK_V_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST3_0_BLANK_V_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INST3_0_BLANK_V_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST3_0_BLANK_V_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST3_0_BLANK_V_INIT_ENUM NORMAL +#define SOR_NV_PDISP_SOR_SEQ_INST3_0_BLANK_V_NORMAL _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INST3_0_BLANK_V_INACTIVE _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INST3_0_BLANK_H_SHIFT _MK_SHIFT_CONST(27) +#define SOR_NV_PDISP_SOR_SEQ_INST3_0_BLANK_H_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST3_0_BLANK_H_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INST3_0_BLANK_H_RANGE 27:27 +#define SOR_NV_PDISP_SOR_SEQ_INST3_0_BLANK_H_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INST3_0_BLANK_H_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST3_0_BLANK_H_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INST3_0_BLANK_H_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST3_0_BLANK_H_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST3_0_BLANK_H_INIT_ENUM NORMAL +#define SOR_NV_PDISP_SOR_SEQ_INST3_0_BLANK_H_NORMAL _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INST3_0_BLANK_H_INACTIVE _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INST3_0_BLANK_DE_SHIFT _MK_SHIFT_CONST(26) +#define SOR_NV_PDISP_SOR_SEQ_INST3_0_BLANK_DE_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST3_0_BLANK_DE_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INST3_0_BLANK_DE_RANGE 26:26 +#define SOR_NV_PDISP_SOR_SEQ_INST3_0_BLANK_DE_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INST3_0_BLANK_DE_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST3_0_BLANK_DE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INST3_0_BLANK_DE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST3_0_BLANK_DE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST3_0_BLANK_DE_INIT_ENUM NORMAL +#define SOR_NV_PDISP_SOR_SEQ_INST3_0_BLANK_DE_NORMAL _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INST3_0_BLANK_DE_INACTIVE _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INST3_0_BLACK_DATA_SHIFT _MK_SHIFT_CONST(25) +#define SOR_NV_PDISP_SOR_SEQ_INST3_0_BLACK_DATA_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST3_0_BLACK_DATA_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INST3_0_BLACK_DATA_RANGE 25:25 +#define SOR_NV_PDISP_SOR_SEQ_INST3_0_BLACK_DATA_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INST3_0_BLACK_DATA_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST3_0_BLACK_DATA_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INST3_0_BLACK_DATA_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST3_0_BLACK_DATA_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST3_0_BLACK_DATA_INIT_ENUM NORMAL +#define SOR_NV_PDISP_SOR_SEQ_INST3_0_BLACK_DATA_NORMAL _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INST3_0_BLACK_DATA_BLACK _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INST3_0_TRISTATE_IOS_SHIFT _MK_SHIFT_CONST(24) +#define SOR_NV_PDISP_SOR_SEQ_INST3_0_TRISTATE_IOS_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST3_0_TRISTATE_IOS_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INST3_0_TRISTATE_IOS_RANGE 24:24 +#define SOR_NV_PDISP_SOR_SEQ_INST3_0_TRISTATE_IOS_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INST3_0_TRISTATE_IOS_DEFAULT _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INST3_0_TRISTATE_IOS_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INST3_0_TRISTATE_IOS_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST3_0_TRISTATE_IOS_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST3_0_TRISTATE_IOS_INIT_ENUM TRISTATE +#define SOR_NV_PDISP_SOR_SEQ_INST3_0_TRISTATE_IOS_ENABLE_PINS _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INST3_0_TRISTATE_IOS_TRISTATE _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INST3_0_DRIVE_PWM_OUT_LO_SHIFT _MK_SHIFT_CONST(23) +#define SOR_NV_PDISP_SOR_SEQ_INST3_0_DRIVE_PWM_OUT_LO_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST3_0_DRIVE_PWM_OUT_LO_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INST3_0_DRIVE_PWM_OUT_LO_RANGE 23:23 +#define SOR_NV_PDISP_SOR_SEQ_INST3_0_DRIVE_PWM_OUT_LO_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INST3_0_DRIVE_PWM_OUT_LO_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST3_0_DRIVE_PWM_OUT_LO_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INST3_0_DRIVE_PWM_OUT_LO_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST3_0_DRIVE_PWM_OUT_LO_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST3_0_DRIVE_PWM_OUT_LO_INIT_ENUM FALSE +#define SOR_NV_PDISP_SOR_SEQ_INST3_0_DRIVE_PWM_OUT_LO_FALSE _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INST3_0_DRIVE_PWM_OUT_LO_TRUE _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INST3_0_PIN_B_SHIFT _MK_SHIFT_CONST(22) +#define SOR_NV_PDISP_SOR_SEQ_INST3_0_PIN_B_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST3_0_PIN_B_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INST3_0_PIN_B_RANGE 22:22 +#define SOR_NV_PDISP_SOR_SEQ_INST3_0_PIN_B_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INST3_0_PIN_B_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST3_0_PIN_B_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INST3_0_PIN_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST3_0_PIN_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST3_0_PIN_B_INIT_ENUM LOW +#define SOR_NV_PDISP_SOR_SEQ_INST3_0_PIN_B_LOW _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INST3_0_PIN_B_HIGH _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INST3_0_PIN_A_SHIFT _MK_SHIFT_CONST(21) +#define SOR_NV_PDISP_SOR_SEQ_INST3_0_PIN_A_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST3_0_PIN_A_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INST3_0_PIN_A_RANGE 21:21 +#define SOR_NV_PDISP_SOR_SEQ_INST3_0_PIN_A_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INST3_0_PIN_A_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST3_0_PIN_A_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INST3_0_PIN_A_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST3_0_PIN_A_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST3_0_PIN_A_INIT_ENUM LOW +#define SOR_NV_PDISP_SOR_SEQ_INST3_0_PIN_A_LOW _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INST3_0_PIN_A_HIGH _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INST3_0_SEQUENCE_SHIFT _MK_SHIFT_CONST(19) +#define SOR_NV_PDISP_SOR_SEQ_INST3_0_SEQUENCE_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST3_0_SEQUENCE_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INST3_0_SEQUENCE_RANGE 19:19 +#define SOR_NV_PDISP_SOR_SEQ_INST3_0_SEQUENCE_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INST3_0_SEQUENCE_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST3_0_SEQUENCE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INST3_0_SEQUENCE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST3_0_SEQUENCE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST3_0_SEQUENCE_INIT_ENUM UP +#define SOR_NV_PDISP_SOR_SEQ_INST3_0_SEQUENCE_UP _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INST3_0_SEQUENCE_DOWN _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INST3_0_LANE_SEQ_SHIFT _MK_SHIFT_CONST(18) +#define SOR_NV_PDISP_SOR_SEQ_INST3_0_LANE_SEQ_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST3_0_LANE_SEQ_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INST3_0_LANE_SEQ_RANGE 18:18 +#define SOR_NV_PDISP_SOR_SEQ_INST3_0_LANE_SEQ_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INST3_0_LANE_SEQ_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST3_0_LANE_SEQ_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INST3_0_LANE_SEQ_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST3_0_LANE_SEQ_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST3_0_LANE_SEQ_INIT_ENUM STOP +#define SOR_NV_PDISP_SOR_SEQ_INST3_0_LANE_SEQ_STOP _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INST3_0_LANE_SEQ_RUN _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INST3_0_PDPORT_SHIFT _MK_SHIFT_CONST(17) +#define SOR_NV_PDISP_SOR_SEQ_INST3_0_PDPORT_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST3_0_PDPORT_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INST3_0_PDPORT_RANGE 17:17 +#define SOR_NV_PDISP_SOR_SEQ_INST3_0_PDPORT_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INST3_0_PDPORT_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST3_0_PDPORT_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INST3_0_PDPORT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST3_0_PDPORT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST3_0_PDPORT_INIT_ENUM NO +#define SOR_NV_PDISP_SOR_SEQ_INST3_0_PDPORT_NO _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INST3_0_PDPORT_YES _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INST3_0_PDPLL_SHIFT _MK_SHIFT_CONST(16) +#define SOR_NV_PDISP_SOR_SEQ_INST3_0_PDPLL_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST3_0_PDPLL_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INST3_0_PDPLL_RANGE 16:16 +#define SOR_NV_PDISP_SOR_SEQ_INST3_0_PDPLL_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INST3_0_PDPLL_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST3_0_PDPLL_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INST3_0_PDPLL_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST3_0_PDPLL_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST3_0_PDPLL_INIT_ENUM NO +#define SOR_NV_PDISP_SOR_SEQ_INST3_0_PDPLL_NO _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INST3_0_PDPLL_YES _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INST3_0_HALT_SHIFT _MK_SHIFT_CONST(15) +#define SOR_NV_PDISP_SOR_SEQ_INST3_0_HALT_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST3_0_HALT_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INST3_0_HALT_RANGE 15:15 +#define SOR_NV_PDISP_SOR_SEQ_INST3_0_HALT_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INST3_0_HALT_DEFAULT _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INST3_0_HALT_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INST3_0_HALT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST3_0_HALT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST3_0_HALT_INIT_ENUM TRUE +#define SOR_NV_PDISP_SOR_SEQ_INST3_0_HALT_FALSE _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INST3_0_HALT_TRUE _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INST3_0_WAIT_UNITS_SHIFT _MK_SHIFT_CONST(12) +#define SOR_NV_PDISP_SOR_SEQ_INST3_0_WAIT_UNITS_FIELD _MK_FIELD_CONST(0x3, SOR_NV_PDISP_SOR_SEQ_INST3_0_WAIT_UNITS_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INST3_0_WAIT_UNITS_RANGE 13:12 +#define SOR_NV_PDISP_SOR_SEQ_INST3_0_WAIT_UNITS_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INST3_0_WAIT_UNITS_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST3_0_WAIT_UNITS_DEFAULT_MASK _MK_MASK_CONST(0x3) +#define SOR_NV_PDISP_SOR_SEQ_INST3_0_WAIT_UNITS_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST3_0_WAIT_UNITS_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST3_0_WAIT_UNITS_INIT_ENUM US +#define SOR_NV_PDISP_SOR_SEQ_INST3_0_WAIT_UNITS_US _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INST3_0_WAIT_UNITS_MS _MK_ENUM_CONST(1) +#define SOR_NV_PDISP_SOR_SEQ_INST3_0_WAIT_UNITS_VSYNC _MK_ENUM_CONST(2) + +#define SOR_NV_PDISP_SOR_SEQ_INST3_0_WAIT_TIME_SHIFT _MK_SHIFT_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INST3_0_WAIT_TIME_FIELD _MK_FIELD_CONST(0x3ff, SOR_NV_PDISP_SOR_SEQ_INST3_0_WAIT_TIME_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INST3_0_WAIT_TIME_RANGE 9:0 +#define SOR_NV_PDISP_SOR_SEQ_INST3_0_WAIT_TIME_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INST3_0_WAIT_TIME_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST3_0_WAIT_TIME_DEFAULT_MASK _MK_MASK_CONST(0x3ff) +#define SOR_NV_PDISP_SOR_SEQ_INST3_0_WAIT_TIME_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST3_0_WAIT_TIME_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register SOR_NV_PDISP_SOR_SEQ_INST4_0 +#define SOR_NV_PDISP_SOR_SEQ_INST4_0 _MK_ADDR_CONST(0x26) +#define SOR_NV_PDISP_SOR_SEQ_INST4_0_SECURE 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INST4_0_WORD_COUNT 0x1 +#define SOR_NV_PDISP_SOR_SEQ_INST4_0_RESET_VAL _MK_MASK_CONST(0x1008000) +#define SOR_NV_PDISP_SOR_SEQ_INST4_0_RESET_MASK _MK_MASK_CONST(0xffefb3ff) +#define SOR_NV_PDISP_SOR_SEQ_INST4_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST4_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST4_0_READ_MASK _MK_MASK_CONST(0xffefb3ff) +#define SOR_NV_PDISP_SOR_SEQ_INST4_0_WRITE_MASK _MK_MASK_CONST(0xffefb3ff) +#define SOR_NV_PDISP_SOR_SEQ_INST4_0_PLL_PULLDOWN_SHIFT _MK_SHIFT_CONST(31) +#define SOR_NV_PDISP_SOR_SEQ_INST4_0_PLL_PULLDOWN_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST4_0_PLL_PULLDOWN_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INST4_0_PLL_PULLDOWN_RANGE 31:31 +#define SOR_NV_PDISP_SOR_SEQ_INST4_0_PLL_PULLDOWN_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INST4_0_PLL_PULLDOWN_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST4_0_PLL_PULLDOWN_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INST4_0_PLL_PULLDOWN_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST4_0_PLL_PULLDOWN_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST4_0_PLL_PULLDOWN_INIT_ENUM DISABLE +#define SOR_NV_PDISP_SOR_SEQ_INST4_0_PLL_PULLDOWN_DISABLE _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INST4_0_PLL_PULLDOWN_ENABLE _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INST4_0_POWERDOWN_MACRO_SHIFT _MK_SHIFT_CONST(30) +#define SOR_NV_PDISP_SOR_SEQ_INST4_0_POWERDOWN_MACRO_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST4_0_POWERDOWN_MACRO_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INST4_0_POWERDOWN_MACRO_RANGE 30:30 +#define SOR_NV_PDISP_SOR_SEQ_INST4_0_POWERDOWN_MACRO_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INST4_0_POWERDOWN_MACRO_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST4_0_POWERDOWN_MACRO_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INST4_0_POWERDOWN_MACRO_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST4_0_POWERDOWN_MACRO_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST4_0_POWERDOWN_MACRO_INIT_ENUM NORMAL +#define SOR_NV_PDISP_SOR_SEQ_INST4_0_POWERDOWN_MACRO_NORMAL _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INST4_0_POWERDOWN_MACRO_POWERDOWN _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INST4_0_ASSERT_PLL_RESET_SHIFT _MK_SHIFT_CONST(29) +#define SOR_NV_PDISP_SOR_SEQ_INST4_0_ASSERT_PLL_RESET_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST4_0_ASSERT_PLL_RESET_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INST4_0_ASSERT_PLL_RESET_RANGE 29:29 +#define SOR_NV_PDISP_SOR_SEQ_INST4_0_ASSERT_PLL_RESET_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INST4_0_ASSERT_PLL_RESET_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST4_0_ASSERT_PLL_RESET_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INST4_0_ASSERT_PLL_RESET_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST4_0_ASSERT_PLL_RESET_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST4_0_ASSERT_PLL_RESET_INIT_ENUM NORMAL +#define SOR_NV_PDISP_SOR_SEQ_INST4_0_ASSERT_PLL_RESET_NORMAL _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INST4_0_ASSERT_PLL_RESET_RST _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INST4_0_BLANK_V_SHIFT _MK_SHIFT_CONST(28) +#define SOR_NV_PDISP_SOR_SEQ_INST4_0_BLANK_V_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST4_0_BLANK_V_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INST4_0_BLANK_V_RANGE 28:28 +#define SOR_NV_PDISP_SOR_SEQ_INST4_0_BLANK_V_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INST4_0_BLANK_V_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST4_0_BLANK_V_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INST4_0_BLANK_V_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST4_0_BLANK_V_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST4_0_BLANK_V_INIT_ENUM NORMAL +#define SOR_NV_PDISP_SOR_SEQ_INST4_0_BLANK_V_NORMAL _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INST4_0_BLANK_V_INACTIVE _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INST4_0_BLANK_H_SHIFT _MK_SHIFT_CONST(27) +#define SOR_NV_PDISP_SOR_SEQ_INST4_0_BLANK_H_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST4_0_BLANK_H_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INST4_0_BLANK_H_RANGE 27:27 +#define SOR_NV_PDISP_SOR_SEQ_INST4_0_BLANK_H_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INST4_0_BLANK_H_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST4_0_BLANK_H_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INST4_0_BLANK_H_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST4_0_BLANK_H_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST4_0_BLANK_H_INIT_ENUM NORMAL +#define SOR_NV_PDISP_SOR_SEQ_INST4_0_BLANK_H_NORMAL _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INST4_0_BLANK_H_INACTIVE _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INST4_0_BLANK_DE_SHIFT _MK_SHIFT_CONST(26) +#define SOR_NV_PDISP_SOR_SEQ_INST4_0_BLANK_DE_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST4_0_BLANK_DE_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INST4_0_BLANK_DE_RANGE 26:26 +#define SOR_NV_PDISP_SOR_SEQ_INST4_0_BLANK_DE_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INST4_0_BLANK_DE_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST4_0_BLANK_DE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INST4_0_BLANK_DE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST4_0_BLANK_DE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST4_0_BLANK_DE_INIT_ENUM NORMAL +#define SOR_NV_PDISP_SOR_SEQ_INST4_0_BLANK_DE_NORMAL _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INST4_0_BLANK_DE_INACTIVE _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INST4_0_BLACK_DATA_SHIFT _MK_SHIFT_CONST(25) +#define SOR_NV_PDISP_SOR_SEQ_INST4_0_BLACK_DATA_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST4_0_BLACK_DATA_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INST4_0_BLACK_DATA_RANGE 25:25 +#define SOR_NV_PDISP_SOR_SEQ_INST4_0_BLACK_DATA_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INST4_0_BLACK_DATA_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST4_0_BLACK_DATA_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INST4_0_BLACK_DATA_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST4_0_BLACK_DATA_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST4_0_BLACK_DATA_INIT_ENUM NORMAL +#define SOR_NV_PDISP_SOR_SEQ_INST4_0_BLACK_DATA_NORMAL _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INST4_0_BLACK_DATA_BLACK _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INST4_0_TRISTATE_IOS_SHIFT _MK_SHIFT_CONST(24) +#define SOR_NV_PDISP_SOR_SEQ_INST4_0_TRISTATE_IOS_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST4_0_TRISTATE_IOS_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INST4_0_TRISTATE_IOS_RANGE 24:24 +#define SOR_NV_PDISP_SOR_SEQ_INST4_0_TRISTATE_IOS_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INST4_0_TRISTATE_IOS_DEFAULT _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INST4_0_TRISTATE_IOS_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INST4_0_TRISTATE_IOS_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST4_0_TRISTATE_IOS_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST4_0_TRISTATE_IOS_INIT_ENUM TRISTATE +#define SOR_NV_PDISP_SOR_SEQ_INST4_0_TRISTATE_IOS_ENABLE_PINS _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INST4_0_TRISTATE_IOS_TRISTATE _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INST4_0_DRIVE_PWM_OUT_LO_SHIFT _MK_SHIFT_CONST(23) +#define SOR_NV_PDISP_SOR_SEQ_INST4_0_DRIVE_PWM_OUT_LO_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST4_0_DRIVE_PWM_OUT_LO_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INST4_0_DRIVE_PWM_OUT_LO_RANGE 23:23 +#define SOR_NV_PDISP_SOR_SEQ_INST4_0_DRIVE_PWM_OUT_LO_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INST4_0_DRIVE_PWM_OUT_LO_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST4_0_DRIVE_PWM_OUT_LO_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INST4_0_DRIVE_PWM_OUT_LO_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST4_0_DRIVE_PWM_OUT_LO_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST4_0_DRIVE_PWM_OUT_LO_INIT_ENUM FALSE +#define SOR_NV_PDISP_SOR_SEQ_INST4_0_DRIVE_PWM_OUT_LO_FALSE _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INST4_0_DRIVE_PWM_OUT_LO_TRUE _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INST4_0_PIN_B_SHIFT _MK_SHIFT_CONST(22) +#define SOR_NV_PDISP_SOR_SEQ_INST4_0_PIN_B_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST4_0_PIN_B_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INST4_0_PIN_B_RANGE 22:22 +#define SOR_NV_PDISP_SOR_SEQ_INST4_0_PIN_B_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INST4_0_PIN_B_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST4_0_PIN_B_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INST4_0_PIN_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST4_0_PIN_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST4_0_PIN_B_INIT_ENUM LOW +#define SOR_NV_PDISP_SOR_SEQ_INST4_0_PIN_B_LOW _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INST4_0_PIN_B_HIGH _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INST4_0_PIN_A_SHIFT _MK_SHIFT_CONST(21) +#define SOR_NV_PDISP_SOR_SEQ_INST4_0_PIN_A_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST4_0_PIN_A_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INST4_0_PIN_A_RANGE 21:21 +#define SOR_NV_PDISP_SOR_SEQ_INST4_0_PIN_A_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INST4_0_PIN_A_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST4_0_PIN_A_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INST4_0_PIN_A_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST4_0_PIN_A_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST4_0_PIN_A_INIT_ENUM LOW +#define SOR_NV_PDISP_SOR_SEQ_INST4_0_PIN_A_LOW _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INST4_0_PIN_A_HIGH _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INST4_0_SEQUENCE_SHIFT _MK_SHIFT_CONST(19) +#define SOR_NV_PDISP_SOR_SEQ_INST4_0_SEQUENCE_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST4_0_SEQUENCE_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INST4_0_SEQUENCE_RANGE 19:19 +#define SOR_NV_PDISP_SOR_SEQ_INST4_0_SEQUENCE_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INST4_0_SEQUENCE_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST4_0_SEQUENCE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INST4_0_SEQUENCE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST4_0_SEQUENCE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST4_0_SEQUENCE_INIT_ENUM UP +#define SOR_NV_PDISP_SOR_SEQ_INST4_0_SEQUENCE_UP _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INST4_0_SEQUENCE_DOWN _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INST4_0_LANE_SEQ_SHIFT _MK_SHIFT_CONST(18) +#define SOR_NV_PDISP_SOR_SEQ_INST4_0_LANE_SEQ_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST4_0_LANE_SEQ_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INST4_0_LANE_SEQ_RANGE 18:18 +#define SOR_NV_PDISP_SOR_SEQ_INST4_0_LANE_SEQ_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INST4_0_LANE_SEQ_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST4_0_LANE_SEQ_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INST4_0_LANE_SEQ_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST4_0_LANE_SEQ_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST4_0_LANE_SEQ_INIT_ENUM STOP +#define SOR_NV_PDISP_SOR_SEQ_INST4_0_LANE_SEQ_STOP _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INST4_0_LANE_SEQ_RUN _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INST4_0_PDPORT_SHIFT _MK_SHIFT_CONST(17) +#define SOR_NV_PDISP_SOR_SEQ_INST4_0_PDPORT_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST4_0_PDPORT_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INST4_0_PDPORT_RANGE 17:17 +#define SOR_NV_PDISP_SOR_SEQ_INST4_0_PDPORT_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INST4_0_PDPORT_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST4_0_PDPORT_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INST4_0_PDPORT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST4_0_PDPORT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST4_0_PDPORT_INIT_ENUM NO +#define SOR_NV_PDISP_SOR_SEQ_INST4_0_PDPORT_NO _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INST4_0_PDPORT_YES _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INST4_0_PDPLL_SHIFT _MK_SHIFT_CONST(16) +#define SOR_NV_PDISP_SOR_SEQ_INST4_0_PDPLL_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST4_0_PDPLL_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INST4_0_PDPLL_RANGE 16:16 +#define SOR_NV_PDISP_SOR_SEQ_INST4_0_PDPLL_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INST4_0_PDPLL_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST4_0_PDPLL_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INST4_0_PDPLL_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST4_0_PDPLL_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST4_0_PDPLL_INIT_ENUM NO +#define SOR_NV_PDISP_SOR_SEQ_INST4_0_PDPLL_NO _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INST4_0_PDPLL_YES _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INST4_0_HALT_SHIFT _MK_SHIFT_CONST(15) +#define SOR_NV_PDISP_SOR_SEQ_INST4_0_HALT_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST4_0_HALT_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INST4_0_HALT_RANGE 15:15 +#define SOR_NV_PDISP_SOR_SEQ_INST4_0_HALT_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INST4_0_HALT_DEFAULT _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INST4_0_HALT_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INST4_0_HALT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST4_0_HALT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST4_0_HALT_INIT_ENUM TRUE +#define SOR_NV_PDISP_SOR_SEQ_INST4_0_HALT_FALSE _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INST4_0_HALT_TRUE _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INST4_0_WAIT_UNITS_SHIFT _MK_SHIFT_CONST(12) +#define SOR_NV_PDISP_SOR_SEQ_INST4_0_WAIT_UNITS_FIELD _MK_FIELD_CONST(0x3, SOR_NV_PDISP_SOR_SEQ_INST4_0_WAIT_UNITS_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INST4_0_WAIT_UNITS_RANGE 13:12 +#define SOR_NV_PDISP_SOR_SEQ_INST4_0_WAIT_UNITS_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INST4_0_WAIT_UNITS_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST4_0_WAIT_UNITS_DEFAULT_MASK _MK_MASK_CONST(0x3) +#define SOR_NV_PDISP_SOR_SEQ_INST4_0_WAIT_UNITS_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST4_0_WAIT_UNITS_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST4_0_WAIT_UNITS_INIT_ENUM US +#define SOR_NV_PDISP_SOR_SEQ_INST4_0_WAIT_UNITS_US _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INST4_0_WAIT_UNITS_MS _MK_ENUM_CONST(1) +#define SOR_NV_PDISP_SOR_SEQ_INST4_0_WAIT_UNITS_VSYNC _MK_ENUM_CONST(2) + +#define SOR_NV_PDISP_SOR_SEQ_INST4_0_WAIT_TIME_SHIFT _MK_SHIFT_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INST4_0_WAIT_TIME_FIELD _MK_FIELD_CONST(0x3ff, SOR_NV_PDISP_SOR_SEQ_INST4_0_WAIT_TIME_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INST4_0_WAIT_TIME_RANGE 9:0 +#define SOR_NV_PDISP_SOR_SEQ_INST4_0_WAIT_TIME_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INST4_0_WAIT_TIME_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST4_0_WAIT_TIME_DEFAULT_MASK _MK_MASK_CONST(0x3ff) +#define SOR_NV_PDISP_SOR_SEQ_INST4_0_WAIT_TIME_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST4_0_WAIT_TIME_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register SOR_NV_PDISP_SOR_SEQ_INST5_0 +#define SOR_NV_PDISP_SOR_SEQ_INST5_0 _MK_ADDR_CONST(0x27) +#define SOR_NV_PDISP_SOR_SEQ_INST5_0_SECURE 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INST5_0_WORD_COUNT 0x1 +#define SOR_NV_PDISP_SOR_SEQ_INST5_0_RESET_VAL _MK_MASK_CONST(0x1008000) +#define SOR_NV_PDISP_SOR_SEQ_INST5_0_RESET_MASK _MK_MASK_CONST(0xffefb3ff) +#define SOR_NV_PDISP_SOR_SEQ_INST5_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST5_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST5_0_READ_MASK _MK_MASK_CONST(0xffefb3ff) +#define SOR_NV_PDISP_SOR_SEQ_INST5_0_WRITE_MASK _MK_MASK_CONST(0xffefb3ff) +#define SOR_NV_PDISP_SOR_SEQ_INST5_0_PLL_PULLDOWN_SHIFT _MK_SHIFT_CONST(31) +#define SOR_NV_PDISP_SOR_SEQ_INST5_0_PLL_PULLDOWN_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST5_0_PLL_PULLDOWN_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INST5_0_PLL_PULLDOWN_RANGE 31:31 +#define SOR_NV_PDISP_SOR_SEQ_INST5_0_PLL_PULLDOWN_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INST5_0_PLL_PULLDOWN_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST5_0_PLL_PULLDOWN_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INST5_0_PLL_PULLDOWN_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST5_0_PLL_PULLDOWN_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST5_0_PLL_PULLDOWN_INIT_ENUM DISABLE +#define SOR_NV_PDISP_SOR_SEQ_INST5_0_PLL_PULLDOWN_DISABLE _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INST5_0_PLL_PULLDOWN_ENABLE _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INST5_0_POWERDOWN_MACRO_SHIFT _MK_SHIFT_CONST(30) +#define SOR_NV_PDISP_SOR_SEQ_INST5_0_POWERDOWN_MACRO_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST5_0_POWERDOWN_MACRO_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INST5_0_POWERDOWN_MACRO_RANGE 30:30 +#define SOR_NV_PDISP_SOR_SEQ_INST5_0_POWERDOWN_MACRO_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INST5_0_POWERDOWN_MACRO_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST5_0_POWERDOWN_MACRO_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INST5_0_POWERDOWN_MACRO_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST5_0_POWERDOWN_MACRO_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST5_0_POWERDOWN_MACRO_INIT_ENUM NORMAL +#define SOR_NV_PDISP_SOR_SEQ_INST5_0_POWERDOWN_MACRO_NORMAL _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INST5_0_POWERDOWN_MACRO_POWERDOWN _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INST5_0_ASSERT_PLL_RESET_SHIFT _MK_SHIFT_CONST(29) +#define SOR_NV_PDISP_SOR_SEQ_INST5_0_ASSERT_PLL_RESET_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST5_0_ASSERT_PLL_RESET_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INST5_0_ASSERT_PLL_RESET_RANGE 29:29 +#define SOR_NV_PDISP_SOR_SEQ_INST5_0_ASSERT_PLL_RESET_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INST5_0_ASSERT_PLL_RESET_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST5_0_ASSERT_PLL_RESET_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INST5_0_ASSERT_PLL_RESET_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST5_0_ASSERT_PLL_RESET_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST5_0_ASSERT_PLL_RESET_INIT_ENUM NORMAL +#define SOR_NV_PDISP_SOR_SEQ_INST5_0_ASSERT_PLL_RESET_NORMAL _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INST5_0_ASSERT_PLL_RESET_RST _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INST5_0_BLANK_V_SHIFT _MK_SHIFT_CONST(28) +#define SOR_NV_PDISP_SOR_SEQ_INST5_0_BLANK_V_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST5_0_BLANK_V_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INST5_0_BLANK_V_RANGE 28:28 +#define SOR_NV_PDISP_SOR_SEQ_INST5_0_BLANK_V_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INST5_0_BLANK_V_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST5_0_BLANK_V_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INST5_0_BLANK_V_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST5_0_BLANK_V_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST5_0_BLANK_V_INIT_ENUM NORMAL +#define SOR_NV_PDISP_SOR_SEQ_INST5_0_BLANK_V_NORMAL _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INST5_0_BLANK_V_INACTIVE _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INST5_0_BLANK_H_SHIFT _MK_SHIFT_CONST(27) +#define SOR_NV_PDISP_SOR_SEQ_INST5_0_BLANK_H_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST5_0_BLANK_H_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INST5_0_BLANK_H_RANGE 27:27 +#define SOR_NV_PDISP_SOR_SEQ_INST5_0_BLANK_H_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INST5_0_BLANK_H_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST5_0_BLANK_H_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INST5_0_BLANK_H_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST5_0_BLANK_H_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST5_0_BLANK_H_INIT_ENUM NORMAL +#define SOR_NV_PDISP_SOR_SEQ_INST5_0_BLANK_H_NORMAL _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INST5_0_BLANK_H_INACTIVE _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INST5_0_BLANK_DE_SHIFT _MK_SHIFT_CONST(26) +#define SOR_NV_PDISP_SOR_SEQ_INST5_0_BLANK_DE_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST5_0_BLANK_DE_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INST5_0_BLANK_DE_RANGE 26:26 +#define SOR_NV_PDISP_SOR_SEQ_INST5_0_BLANK_DE_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INST5_0_BLANK_DE_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST5_0_BLANK_DE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INST5_0_BLANK_DE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST5_0_BLANK_DE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST5_0_BLANK_DE_INIT_ENUM NORMAL +#define SOR_NV_PDISP_SOR_SEQ_INST5_0_BLANK_DE_NORMAL _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INST5_0_BLANK_DE_INACTIVE _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INST5_0_BLACK_DATA_SHIFT _MK_SHIFT_CONST(25) +#define SOR_NV_PDISP_SOR_SEQ_INST5_0_BLACK_DATA_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST5_0_BLACK_DATA_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INST5_0_BLACK_DATA_RANGE 25:25 +#define SOR_NV_PDISP_SOR_SEQ_INST5_0_BLACK_DATA_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INST5_0_BLACK_DATA_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST5_0_BLACK_DATA_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INST5_0_BLACK_DATA_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST5_0_BLACK_DATA_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST5_0_BLACK_DATA_INIT_ENUM NORMAL +#define SOR_NV_PDISP_SOR_SEQ_INST5_0_BLACK_DATA_NORMAL _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INST5_0_BLACK_DATA_BLACK _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INST5_0_TRISTATE_IOS_SHIFT _MK_SHIFT_CONST(24) +#define SOR_NV_PDISP_SOR_SEQ_INST5_0_TRISTATE_IOS_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST5_0_TRISTATE_IOS_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INST5_0_TRISTATE_IOS_RANGE 24:24 +#define SOR_NV_PDISP_SOR_SEQ_INST5_0_TRISTATE_IOS_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INST5_0_TRISTATE_IOS_DEFAULT _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INST5_0_TRISTATE_IOS_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INST5_0_TRISTATE_IOS_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST5_0_TRISTATE_IOS_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST5_0_TRISTATE_IOS_INIT_ENUM TRISTATE +#define SOR_NV_PDISP_SOR_SEQ_INST5_0_TRISTATE_IOS_ENABLE_PINS _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INST5_0_TRISTATE_IOS_TRISTATE _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INST5_0_DRIVE_PWM_OUT_LO_SHIFT _MK_SHIFT_CONST(23) +#define SOR_NV_PDISP_SOR_SEQ_INST5_0_DRIVE_PWM_OUT_LO_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST5_0_DRIVE_PWM_OUT_LO_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INST5_0_DRIVE_PWM_OUT_LO_RANGE 23:23 +#define SOR_NV_PDISP_SOR_SEQ_INST5_0_DRIVE_PWM_OUT_LO_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INST5_0_DRIVE_PWM_OUT_LO_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST5_0_DRIVE_PWM_OUT_LO_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INST5_0_DRIVE_PWM_OUT_LO_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST5_0_DRIVE_PWM_OUT_LO_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST5_0_DRIVE_PWM_OUT_LO_INIT_ENUM FALSE +#define SOR_NV_PDISP_SOR_SEQ_INST5_0_DRIVE_PWM_OUT_LO_FALSE _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INST5_0_DRIVE_PWM_OUT_LO_TRUE _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INST5_0_PIN_B_SHIFT _MK_SHIFT_CONST(22) +#define SOR_NV_PDISP_SOR_SEQ_INST5_0_PIN_B_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST5_0_PIN_B_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INST5_0_PIN_B_RANGE 22:22 +#define SOR_NV_PDISP_SOR_SEQ_INST5_0_PIN_B_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INST5_0_PIN_B_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST5_0_PIN_B_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INST5_0_PIN_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST5_0_PIN_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST5_0_PIN_B_INIT_ENUM LOW +#define SOR_NV_PDISP_SOR_SEQ_INST5_0_PIN_B_LOW _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INST5_0_PIN_B_HIGH _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INST5_0_PIN_A_SHIFT _MK_SHIFT_CONST(21) +#define SOR_NV_PDISP_SOR_SEQ_INST5_0_PIN_A_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST5_0_PIN_A_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INST5_0_PIN_A_RANGE 21:21 +#define SOR_NV_PDISP_SOR_SEQ_INST5_0_PIN_A_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INST5_0_PIN_A_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST5_0_PIN_A_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INST5_0_PIN_A_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST5_0_PIN_A_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST5_0_PIN_A_INIT_ENUM LOW +#define SOR_NV_PDISP_SOR_SEQ_INST5_0_PIN_A_LOW _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INST5_0_PIN_A_HIGH _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INST5_0_SEQUENCE_SHIFT _MK_SHIFT_CONST(19) +#define SOR_NV_PDISP_SOR_SEQ_INST5_0_SEQUENCE_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST5_0_SEQUENCE_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INST5_0_SEQUENCE_RANGE 19:19 +#define SOR_NV_PDISP_SOR_SEQ_INST5_0_SEQUENCE_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INST5_0_SEQUENCE_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST5_0_SEQUENCE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INST5_0_SEQUENCE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST5_0_SEQUENCE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST5_0_SEQUENCE_INIT_ENUM UP +#define SOR_NV_PDISP_SOR_SEQ_INST5_0_SEQUENCE_UP _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INST5_0_SEQUENCE_DOWN _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INST5_0_LANE_SEQ_SHIFT _MK_SHIFT_CONST(18) +#define SOR_NV_PDISP_SOR_SEQ_INST5_0_LANE_SEQ_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST5_0_LANE_SEQ_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INST5_0_LANE_SEQ_RANGE 18:18 +#define SOR_NV_PDISP_SOR_SEQ_INST5_0_LANE_SEQ_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INST5_0_LANE_SEQ_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST5_0_LANE_SEQ_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INST5_0_LANE_SEQ_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST5_0_LANE_SEQ_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST5_0_LANE_SEQ_INIT_ENUM STOP +#define SOR_NV_PDISP_SOR_SEQ_INST5_0_LANE_SEQ_STOP _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INST5_0_LANE_SEQ_RUN _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INST5_0_PDPORT_SHIFT _MK_SHIFT_CONST(17) +#define SOR_NV_PDISP_SOR_SEQ_INST5_0_PDPORT_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST5_0_PDPORT_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INST5_0_PDPORT_RANGE 17:17 +#define SOR_NV_PDISP_SOR_SEQ_INST5_0_PDPORT_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INST5_0_PDPORT_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST5_0_PDPORT_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INST5_0_PDPORT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST5_0_PDPORT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST5_0_PDPORT_INIT_ENUM NO +#define SOR_NV_PDISP_SOR_SEQ_INST5_0_PDPORT_NO _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INST5_0_PDPORT_YES _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INST5_0_PDPLL_SHIFT _MK_SHIFT_CONST(16) +#define SOR_NV_PDISP_SOR_SEQ_INST5_0_PDPLL_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST5_0_PDPLL_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INST5_0_PDPLL_RANGE 16:16 +#define SOR_NV_PDISP_SOR_SEQ_INST5_0_PDPLL_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INST5_0_PDPLL_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST5_0_PDPLL_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INST5_0_PDPLL_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST5_0_PDPLL_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST5_0_PDPLL_INIT_ENUM NO +#define SOR_NV_PDISP_SOR_SEQ_INST5_0_PDPLL_NO _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INST5_0_PDPLL_YES _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INST5_0_HALT_SHIFT _MK_SHIFT_CONST(15) +#define SOR_NV_PDISP_SOR_SEQ_INST5_0_HALT_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST5_0_HALT_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INST5_0_HALT_RANGE 15:15 +#define SOR_NV_PDISP_SOR_SEQ_INST5_0_HALT_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INST5_0_HALT_DEFAULT _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INST5_0_HALT_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INST5_0_HALT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST5_0_HALT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST5_0_HALT_INIT_ENUM TRUE +#define SOR_NV_PDISP_SOR_SEQ_INST5_0_HALT_FALSE _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INST5_0_HALT_TRUE _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INST5_0_WAIT_UNITS_SHIFT _MK_SHIFT_CONST(12) +#define SOR_NV_PDISP_SOR_SEQ_INST5_0_WAIT_UNITS_FIELD _MK_FIELD_CONST(0x3, SOR_NV_PDISP_SOR_SEQ_INST5_0_WAIT_UNITS_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INST5_0_WAIT_UNITS_RANGE 13:12 +#define SOR_NV_PDISP_SOR_SEQ_INST5_0_WAIT_UNITS_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INST5_0_WAIT_UNITS_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST5_0_WAIT_UNITS_DEFAULT_MASK _MK_MASK_CONST(0x3) +#define SOR_NV_PDISP_SOR_SEQ_INST5_0_WAIT_UNITS_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST5_0_WAIT_UNITS_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST5_0_WAIT_UNITS_INIT_ENUM US +#define SOR_NV_PDISP_SOR_SEQ_INST5_0_WAIT_UNITS_US _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INST5_0_WAIT_UNITS_MS _MK_ENUM_CONST(1) +#define SOR_NV_PDISP_SOR_SEQ_INST5_0_WAIT_UNITS_VSYNC _MK_ENUM_CONST(2) + +#define SOR_NV_PDISP_SOR_SEQ_INST5_0_WAIT_TIME_SHIFT _MK_SHIFT_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INST5_0_WAIT_TIME_FIELD _MK_FIELD_CONST(0x3ff, SOR_NV_PDISP_SOR_SEQ_INST5_0_WAIT_TIME_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INST5_0_WAIT_TIME_RANGE 9:0 +#define SOR_NV_PDISP_SOR_SEQ_INST5_0_WAIT_TIME_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INST5_0_WAIT_TIME_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST5_0_WAIT_TIME_DEFAULT_MASK _MK_MASK_CONST(0x3ff) +#define SOR_NV_PDISP_SOR_SEQ_INST5_0_WAIT_TIME_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST5_0_WAIT_TIME_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register SOR_NV_PDISP_SOR_SEQ_INST6_0 +#define SOR_NV_PDISP_SOR_SEQ_INST6_0 _MK_ADDR_CONST(0x28) +#define SOR_NV_PDISP_SOR_SEQ_INST6_0_SECURE 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INST6_0_WORD_COUNT 0x1 +#define SOR_NV_PDISP_SOR_SEQ_INST6_0_RESET_VAL _MK_MASK_CONST(0x1008000) +#define SOR_NV_PDISP_SOR_SEQ_INST6_0_RESET_MASK _MK_MASK_CONST(0xffefb3ff) +#define SOR_NV_PDISP_SOR_SEQ_INST6_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST6_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST6_0_READ_MASK _MK_MASK_CONST(0xffefb3ff) +#define SOR_NV_PDISP_SOR_SEQ_INST6_0_WRITE_MASK _MK_MASK_CONST(0xffefb3ff) +#define SOR_NV_PDISP_SOR_SEQ_INST6_0_PLL_PULLDOWN_SHIFT _MK_SHIFT_CONST(31) +#define SOR_NV_PDISP_SOR_SEQ_INST6_0_PLL_PULLDOWN_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST6_0_PLL_PULLDOWN_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INST6_0_PLL_PULLDOWN_RANGE 31:31 +#define SOR_NV_PDISP_SOR_SEQ_INST6_0_PLL_PULLDOWN_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INST6_0_PLL_PULLDOWN_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST6_0_PLL_PULLDOWN_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INST6_0_PLL_PULLDOWN_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST6_0_PLL_PULLDOWN_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST6_0_PLL_PULLDOWN_INIT_ENUM DISABLE +#define SOR_NV_PDISP_SOR_SEQ_INST6_0_PLL_PULLDOWN_DISABLE _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INST6_0_PLL_PULLDOWN_ENABLE _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INST6_0_POWERDOWN_MACRO_SHIFT _MK_SHIFT_CONST(30) +#define SOR_NV_PDISP_SOR_SEQ_INST6_0_POWERDOWN_MACRO_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST6_0_POWERDOWN_MACRO_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INST6_0_POWERDOWN_MACRO_RANGE 30:30 +#define SOR_NV_PDISP_SOR_SEQ_INST6_0_POWERDOWN_MACRO_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INST6_0_POWERDOWN_MACRO_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST6_0_POWERDOWN_MACRO_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INST6_0_POWERDOWN_MACRO_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST6_0_POWERDOWN_MACRO_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST6_0_POWERDOWN_MACRO_INIT_ENUM NORMAL +#define SOR_NV_PDISP_SOR_SEQ_INST6_0_POWERDOWN_MACRO_NORMAL _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INST6_0_POWERDOWN_MACRO_POWERDOWN _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INST6_0_ASSERT_PLL_RESET_SHIFT _MK_SHIFT_CONST(29) +#define SOR_NV_PDISP_SOR_SEQ_INST6_0_ASSERT_PLL_RESET_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST6_0_ASSERT_PLL_RESET_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INST6_0_ASSERT_PLL_RESET_RANGE 29:29 +#define SOR_NV_PDISP_SOR_SEQ_INST6_0_ASSERT_PLL_RESET_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INST6_0_ASSERT_PLL_RESET_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST6_0_ASSERT_PLL_RESET_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INST6_0_ASSERT_PLL_RESET_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST6_0_ASSERT_PLL_RESET_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST6_0_ASSERT_PLL_RESET_INIT_ENUM NORMAL +#define SOR_NV_PDISP_SOR_SEQ_INST6_0_ASSERT_PLL_RESET_NORMAL _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INST6_0_ASSERT_PLL_RESET_RST _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INST6_0_BLANK_V_SHIFT _MK_SHIFT_CONST(28) +#define SOR_NV_PDISP_SOR_SEQ_INST6_0_BLANK_V_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST6_0_BLANK_V_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INST6_0_BLANK_V_RANGE 28:28 +#define SOR_NV_PDISP_SOR_SEQ_INST6_0_BLANK_V_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INST6_0_BLANK_V_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST6_0_BLANK_V_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INST6_0_BLANK_V_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST6_0_BLANK_V_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST6_0_BLANK_V_INIT_ENUM NORMAL +#define SOR_NV_PDISP_SOR_SEQ_INST6_0_BLANK_V_NORMAL _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INST6_0_BLANK_V_INACTIVE _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INST6_0_BLANK_H_SHIFT _MK_SHIFT_CONST(27) +#define SOR_NV_PDISP_SOR_SEQ_INST6_0_BLANK_H_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST6_0_BLANK_H_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INST6_0_BLANK_H_RANGE 27:27 +#define SOR_NV_PDISP_SOR_SEQ_INST6_0_BLANK_H_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INST6_0_BLANK_H_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST6_0_BLANK_H_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INST6_0_BLANK_H_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST6_0_BLANK_H_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST6_0_BLANK_H_INIT_ENUM NORMAL +#define SOR_NV_PDISP_SOR_SEQ_INST6_0_BLANK_H_NORMAL _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INST6_0_BLANK_H_INACTIVE _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INST6_0_BLANK_DE_SHIFT _MK_SHIFT_CONST(26) +#define SOR_NV_PDISP_SOR_SEQ_INST6_0_BLANK_DE_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST6_0_BLANK_DE_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INST6_0_BLANK_DE_RANGE 26:26 +#define SOR_NV_PDISP_SOR_SEQ_INST6_0_BLANK_DE_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INST6_0_BLANK_DE_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST6_0_BLANK_DE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INST6_0_BLANK_DE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST6_0_BLANK_DE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST6_0_BLANK_DE_INIT_ENUM NORMAL +#define SOR_NV_PDISP_SOR_SEQ_INST6_0_BLANK_DE_NORMAL _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INST6_0_BLANK_DE_INACTIVE _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INST6_0_BLACK_DATA_SHIFT _MK_SHIFT_CONST(25) +#define SOR_NV_PDISP_SOR_SEQ_INST6_0_BLACK_DATA_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST6_0_BLACK_DATA_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INST6_0_BLACK_DATA_RANGE 25:25 +#define SOR_NV_PDISP_SOR_SEQ_INST6_0_BLACK_DATA_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INST6_0_BLACK_DATA_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST6_0_BLACK_DATA_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INST6_0_BLACK_DATA_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST6_0_BLACK_DATA_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST6_0_BLACK_DATA_INIT_ENUM NORMAL +#define SOR_NV_PDISP_SOR_SEQ_INST6_0_BLACK_DATA_NORMAL _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INST6_0_BLACK_DATA_BLACK _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INST6_0_TRISTATE_IOS_SHIFT _MK_SHIFT_CONST(24) +#define SOR_NV_PDISP_SOR_SEQ_INST6_0_TRISTATE_IOS_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST6_0_TRISTATE_IOS_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INST6_0_TRISTATE_IOS_RANGE 24:24 +#define SOR_NV_PDISP_SOR_SEQ_INST6_0_TRISTATE_IOS_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INST6_0_TRISTATE_IOS_DEFAULT _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INST6_0_TRISTATE_IOS_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INST6_0_TRISTATE_IOS_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST6_0_TRISTATE_IOS_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST6_0_TRISTATE_IOS_INIT_ENUM TRISTATE +#define SOR_NV_PDISP_SOR_SEQ_INST6_0_TRISTATE_IOS_ENABLE_PINS _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INST6_0_TRISTATE_IOS_TRISTATE _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INST6_0_DRIVE_PWM_OUT_LO_SHIFT _MK_SHIFT_CONST(23) +#define SOR_NV_PDISP_SOR_SEQ_INST6_0_DRIVE_PWM_OUT_LO_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST6_0_DRIVE_PWM_OUT_LO_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INST6_0_DRIVE_PWM_OUT_LO_RANGE 23:23 +#define SOR_NV_PDISP_SOR_SEQ_INST6_0_DRIVE_PWM_OUT_LO_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INST6_0_DRIVE_PWM_OUT_LO_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST6_0_DRIVE_PWM_OUT_LO_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INST6_0_DRIVE_PWM_OUT_LO_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST6_0_DRIVE_PWM_OUT_LO_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST6_0_DRIVE_PWM_OUT_LO_INIT_ENUM FALSE +#define SOR_NV_PDISP_SOR_SEQ_INST6_0_DRIVE_PWM_OUT_LO_FALSE _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INST6_0_DRIVE_PWM_OUT_LO_TRUE _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INST6_0_PIN_B_SHIFT _MK_SHIFT_CONST(22) +#define SOR_NV_PDISP_SOR_SEQ_INST6_0_PIN_B_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST6_0_PIN_B_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INST6_0_PIN_B_RANGE 22:22 +#define SOR_NV_PDISP_SOR_SEQ_INST6_0_PIN_B_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INST6_0_PIN_B_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST6_0_PIN_B_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INST6_0_PIN_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST6_0_PIN_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST6_0_PIN_B_INIT_ENUM LOW +#define SOR_NV_PDISP_SOR_SEQ_INST6_0_PIN_B_LOW _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INST6_0_PIN_B_HIGH _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INST6_0_PIN_A_SHIFT _MK_SHIFT_CONST(21) +#define SOR_NV_PDISP_SOR_SEQ_INST6_0_PIN_A_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST6_0_PIN_A_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INST6_0_PIN_A_RANGE 21:21 +#define SOR_NV_PDISP_SOR_SEQ_INST6_0_PIN_A_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INST6_0_PIN_A_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST6_0_PIN_A_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INST6_0_PIN_A_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST6_0_PIN_A_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST6_0_PIN_A_INIT_ENUM LOW +#define SOR_NV_PDISP_SOR_SEQ_INST6_0_PIN_A_LOW _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INST6_0_PIN_A_HIGH _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INST6_0_SEQUENCE_SHIFT _MK_SHIFT_CONST(19) +#define SOR_NV_PDISP_SOR_SEQ_INST6_0_SEQUENCE_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST6_0_SEQUENCE_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INST6_0_SEQUENCE_RANGE 19:19 +#define SOR_NV_PDISP_SOR_SEQ_INST6_0_SEQUENCE_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INST6_0_SEQUENCE_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST6_0_SEQUENCE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INST6_0_SEQUENCE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST6_0_SEQUENCE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST6_0_SEQUENCE_INIT_ENUM UP +#define SOR_NV_PDISP_SOR_SEQ_INST6_0_SEQUENCE_UP _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INST6_0_SEQUENCE_DOWN _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INST6_0_LANE_SEQ_SHIFT _MK_SHIFT_CONST(18) +#define SOR_NV_PDISP_SOR_SEQ_INST6_0_LANE_SEQ_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST6_0_LANE_SEQ_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INST6_0_LANE_SEQ_RANGE 18:18 +#define SOR_NV_PDISP_SOR_SEQ_INST6_0_LANE_SEQ_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INST6_0_LANE_SEQ_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST6_0_LANE_SEQ_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INST6_0_LANE_SEQ_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST6_0_LANE_SEQ_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST6_0_LANE_SEQ_INIT_ENUM STOP +#define SOR_NV_PDISP_SOR_SEQ_INST6_0_LANE_SEQ_STOP _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INST6_0_LANE_SEQ_RUN _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INST6_0_PDPORT_SHIFT _MK_SHIFT_CONST(17) +#define SOR_NV_PDISP_SOR_SEQ_INST6_0_PDPORT_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST6_0_PDPORT_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INST6_0_PDPORT_RANGE 17:17 +#define SOR_NV_PDISP_SOR_SEQ_INST6_0_PDPORT_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INST6_0_PDPORT_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST6_0_PDPORT_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INST6_0_PDPORT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST6_0_PDPORT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST6_0_PDPORT_INIT_ENUM NO +#define SOR_NV_PDISP_SOR_SEQ_INST6_0_PDPORT_NO _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INST6_0_PDPORT_YES _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INST6_0_PDPLL_SHIFT _MK_SHIFT_CONST(16) +#define SOR_NV_PDISP_SOR_SEQ_INST6_0_PDPLL_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST6_0_PDPLL_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INST6_0_PDPLL_RANGE 16:16 +#define SOR_NV_PDISP_SOR_SEQ_INST6_0_PDPLL_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INST6_0_PDPLL_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST6_0_PDPLL_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INST6_0_PDPLL_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST6_0_PDPLL_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST6_0_PDPLL_INIT_ENUM NO +#define SOR_NV_PDISP_SOR_SEQ_INST6_0_PDPLL_NO _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INST6_0_PDPLL_YES _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INST6_0_HALT_SHIFT _MK_SHIFT_CONST(15) +#define SOR_NV_PDISP_SOR_SEQ_INST6_0_HALT_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST6_0_HALT_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INST6_0_HALT_RANGE 15:15 +#define SOR_NV_PDISP_SOR_SEQ_INST6_0_HALT_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INST6_0_HALT_DEFAULT _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INST6_0_HALT_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INST6_0_HALT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST6_0_HALT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST6_0_HALT_INIT_ENUM TRUE +#define SOR_NV_PDISP_SOR_SEQ_INST6_0_HALT_FALSE _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INST6_0_HALT_TRUE _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INST6_0_WAIT_UNITS_SHIFT _MK_SHIFT_CONST(12) +#define SOR_NV_PDISP_SOR_SEQ_INST6_0_WAIT_UNITS_FIELD _MK_FIELD_CONST(0x3, SOR_NV_PDISP_SOR_SEQ_INST6_0_WAIT_UNITS_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INST6_0_WAIT_UNITS_RANGE 13:12 +#define SOR_NV_PDISP_SOR_SEQ_INST6_0_WAIT_UNITS_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INST6_0_WAIT_UNITS_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST6_0_WAIT_UNITS_DEFAULT_MASK _MK_MASK_CONST(0x3) +#define SOR_NV_PDISP_SOR_SEQ_INST6_0_WAIT_UNITS_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST6_0_WAIT_UNITS_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST6_0_WAIT_UNITS_INIT_ENUM US +#define SOR_NV_PDISP_SOR_SEQ_INST6_0_WAIT_UNITS_US _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INST6_0_WAIT_UNITS_MS _MK_ENUM_CONST(1) +#define SOR_NV_PDISP_SOR_SEQ_INST6_0_WAIT_UNITS_VSYNC _MK_ENUM_CONST(2) + +#define SOR_NV_PDISP_SOR_SEQ_INST6_0_WAIT_TIME_SHIFT _MK_SHIFT_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INST6_0_WAIT_TIME_FIELD _MK_FIELD_CONST(0x3ff, SOR_NV_PDISP_SOR_SEQ_INST6_0_WAIT_TIME_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INST6_0_WAIT_TIME_RANGE 9:0 +#define SOR_NV_PDISP_SOR_SEQ_INST6_0_WAIT_TIME_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INST6_0_WAIT_TIME_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST6_0_WAIT_TIME_DEFAULT_MASK _MK_MASK_CONST(0x3ff) +#define SOR_NV_PDISP_SOR_SEQ_INST6_0_WAIT_TIME_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST6_0_WAIT_TIME_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register SOR_NV_PDISP_SOR_SEQ_INST7_0 +#define SOR_NV_PDISP_SOR_SEQ_INST7_0 _MK_ADDR_CONST(0x29) +#define SOR_NV_PDISP_SOR_SEQ_INST7_0_SECURE 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INST7_0_WORD_COUNT 0x1 +#define SOR_NV_PDISP_SOR_SEQ_INST7_0_RESET_VAL _MK_MASK_CONST(0x1008000) +#define SOR_NV_PDISP_SOR_SEQ_INST7_0_RESET_MASK _MK_MASK_CONST(0xffefb3ff) +#define SOR_NV_PDISP_SOR_SEQ_INST7_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST7_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST7_0_READ_MASK _MK_MASK_CONST(0xffefb3ff) +#define SOR_NV_PDISP_SOR_SEQ_INST7_0_WRITE_MASK _MK_MASK_CONST(0xffefb3ff) +#define SOR_NV_PDISP_SOR_SEQ_INST7_0_PLL_PULLDOWN_SHIFT _MK_SHIFT_CONST(31) +#define SOR_NV_PDISP_SOR_SEQ_INST7_0_PLL_PULLDOWN_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST7_0_PLL_PULLDOWN_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INST7_0_PLL_PULLDOWN_RANGE 31:31 +#define SOR_NV_PDISP_SOR_SEQ_INST7_0_PLL_PULLDOWN_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INST7_0_PLL_PULLDOWN_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST7_0_PLL_PULLDOWN_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INST7_0_PLL_PULLDOWN_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST7_0_PLL_PULLDOWN_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST7_0_PLL_PULLDOWN_INIT_ENUM DISABLE +#define SOR_NV_PDISP_SOR_SEQ_INST7_0_PLL_PULLDOWN_DISABLE _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INST7_0_PLL_PULLDOWN_ENABLE _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INST7_0_POWERDOWN_MACRO_SHIFT _MK_SHIFT_CONST(30) +#define SOR_NV_PDISP_SOR_SEQ_INST7_0_POWERDOWN_MACRO_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST7_0_POWERDOWN_MACRO_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INST7_0_POWERDOWN_MACRO_RANGE 30:30 +#define SOR_NV_PDISP_SOR_SEQ_INST7_0_POWERDOWN_MACRO_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INST7_0_POWERDOWN_MACRO_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST7_0_POWERDOWN_MACRO_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INST7_0_POWERDOWN_MACRO_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST7_0_POWERDOWN_MACRO_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST7_0_POWERDOWN_MACRO_INIT_ENUM NORMAL +#define SOR_NV_PDISP_SOR_SEQ_INST7_0_POWERDOWN_MACRO_NORMAL _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INST7_0_POWERDOWN_MACRO_POWERDOWN _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INST7_0_ASSERT_PLL_RESET_SHIFT _MK_SHIFT_CONST(29) +#define SOR_NV_PDISP_SOR_SEQ_INST7_0_ASSERT_PLL_RESET_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST7_0_ASSERT_PLL_RESET_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INST7_0_ASSERT_PLL_RESET_RANGE 29:29 +#define SOR_NV_PDISP_SOR_SEQ_INST7_0_ASSERT_PLL_RESET_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INST7_0_ASSERT_PLL_RESET_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST7_0_ASSERT_PLL_RESET_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INST7_0_ASSERT_PLL_RESET_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST7_0_ASSERT_PLL_RESET_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST7_0_ASSERT_PLL_RESET_INIT_ENUM NORMAL +#define SOR_NV_PDISP_SOR_SEQ_INST7_0_ASSERT_PLL_RESET_NORMAL _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INST7_0_ASSERT_PLL_RESET_RST _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INST7_0_BLANK_V_SHIFT _MK_SHIFT_CONST(28) +#define SOR_NV_PDISP_SOR_SEQ_INST7_0_BLANK_V_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST7_0_BLANK_V_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INST7_0_BLANK_V_RANGE 28:28 +#define SOR_NV_PDISP_SOR_SEQ_INST7_0_BLANK_V_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INST7_0_BLANK_V_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST7_0_BLANK_V_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INST7_0_BLANK_V_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST7_0_BLANK_V_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST7_0_BLANK_V_INIT_ENUM NORMAL +#define SOR_NV_PDISP_SOR_SEQ_INST7_0_BLANK_V_NORMAL _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INST7_0_BLANK_V_INACTIVE _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INST7_0_BLANK_H_SHIFT _MK_SHIFT_CONST(27) +#define SOR_NV_PDISP_SOR_SEQ_INST7_0_BLANK_H_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST7_0_BLANK_H_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INST7_0_BLANK_H_RANGE 27:27 +#define SOR_NV_PDISP_SOR_SEQ_INST7_0_BLANK_H_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INST7_0_BLANK_H_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST7_0_BLANK_H_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INST7_0_BLANK_H_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST7_0_BLANK_H_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST7_0_BLANK_H_INIT_ENUM NORMAL +#define SOR_NV_PDISP_SOR_SEQ_INST7_0_BLANK_H_NORMAL _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INST7_0_BLANK_H_INACTIVE _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INST7_0_BLANK_DE_SHIFT _MK_SHIFT_CONST(26) +#define SOR_NV_PDISP_SOR_SEQ_INST7_0_BLANK_DE_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST7_0_BLANK_DE_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INST7_0_BLANK_DE_RANGE 26:26 +#define SOR_NV_PDISP_SOR_SEQ_INST7_0_BLANK_DE_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INST7_0_BLANK_DE_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST7_0_BLANK_DE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INST7_0_BLANK_DE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST7_0_BLANK_DE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST7_0_BLANK_DE_INIT_ENUM NORMAL +#define SOR_NV_PDISP_SOR_SEQ_INST7_0_BLANK_DE_NORMAL _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INST7_0_BLANK_DE_INACTIVE _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INST7_0_BLACK_DATA_SHIFT _MK_SHIFT_CONST(25) +#define SOR_NV_PDISP_SOR_SEQ_INST7_0_BLACK_DATA_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST7_0_BLACK_DATA_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INST7_0_BLACK_DATA_RANGE 25:25 +#define SOR_NV_PDISP_SOR_SEQ_INST7_0_BLACK_DATA_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INST7_0_BLACK_DATA_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST7_0_BLACK_DATA_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INST7_0_BLACK_DATA_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST7_0_BLACK_DATA_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST7_0_BLACK_DATA_INIT_ENUM NORMAL +#define SOR_NV_PDISP_SOR_SEQ_INST7_0_BLACK_DATA_NORMAL _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INST7_0_BLACK_DATA_BLACK _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INST7_0_TRISTATE_IOS_SHIFT _MK_SHIFT_CONST(24) +#define SOR_NV_PDISP_SOR_SEQ_INST7_0_TRISTATE_IOS_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST7_0_TRISTATE_IOS_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INST7_0_TRISTATE_IOS_RANGE 24:24 +#define SOR_NV_PDISP_SOR_SEQ_INST7_0_TRISTATE_IOS_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INST7_0_TRISTATE_IOS_DEFAULT _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INST7_0_TRISTATE_IOS_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INST7_0_TRISTATE_IOS_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST7_0_TRISTATE_IOS_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST7_0_TRISTATE_IOS_INIT_ENUM TRISTATE +#define SOR_NV_PDISP_SOR_SEQ_INST7_0_TRISTATE_IOS_ENABLE_PINS _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INST7_0_TRISTATE_IOS_TRISTATE _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INST7_0_DRIVE_PWM_OUT_LO_SHIFT _MK_SHIFT_CONST(23) +#define SOR_NV_PDISP_SOR_SEQ_INST7_0_DRIVE_PWM_OUT_LO_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST7_0_DRIVE_PWM_OUT_LO_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INST7_0_DRIVE_PWM_OUT_LO_RANGE 23:23 +#define SOR_NV_PDISP_SOR_SEQ_INST7_0_DRIVE_PWM_OUT_LO_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INST7_0_DRIVE_PWM_OUT_LO_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST7_0_DRIVE_PWM_OUT_LO_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INST7_0_DRIVE_PWM_OUT_LO_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST7_0_DRIVE_PWM_OUT_LO_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST7_0_DRIVE_PWM_OUT_LO_INIT_ENUM FALSE +#define SOR_NV_PDISP_SOR_SEQ_INST7_0_DRIVE_PWM_OUT_LO_FALSE _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INST7_0_DRIVE_PWM_OUT_LO_TRUE _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INST7_0_PIN_B_SHIFT _MK_SHIFT_CONST(22) +#define SOR_NV_PDISP_SOR_SEQ_INST7_0_PIN_B_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST7_0_PIN_B_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INST7_0_PIN_B_RANGE 22:22 +#define SOR_NV_PDISP_SOR_SEQ_INST7_0_PIN_B_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INST7_0_PIN_B_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST7_0_PIN_B_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INST7_0_PIN_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST7_0_PIN_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST7_0_PIN_B_INIT_ENUM LOW +#define SOR_NV_PDISP_SOR_SEQ_INST7_0_PIN_B_LOW _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INST7_0_PIN_B_HIGH _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INST7_0_PIN_A_SHIFT _MK_SHIFT_CONST(21) +#define SOR_NV_PDISP_SOR_SEQ_INST7_0_PIN_A_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST7_0_PIN_A_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INST7_0_PIN_A_RANGE 21:21 +#define SOR_NV_PDISP_SOR_SEQ_INST7_0_PIN_A_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INST7_0_PIN_A_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST7_0_PIN_A_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INST7_0_PIN_A_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST7_0_PIN_A_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST7_0_PIN_A_INIT_ENUM LOW +#define SOR_NV_PDISP_SOR_SEQ_INST7_0_PIN_A_LOW _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INST7_0_PIN_A_HIGH _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INST7_0_SEQUENCE_SHIFT _MK_SHIFT_CONST(19) +#define SOR_NV_PDISP_SOR_SEQ_INST7_0_SEQUENCE_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST7_0_SEQUENCE_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INST7_0_SEQUENCE_RANGE 19:19 +#define SOR_NV_PDISP_SOR_SEQ_INST7_0_SEQUENCE_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INST7_0_SEQUENCE_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST7_0_SEQUENCE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INST7_0_SEQUENCE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST7_0_SEQUENCE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST7_0_SEQUENCE_INIT_ENUM UP +#define SOR_NV_PDISP_SOR_SEQ_INST7_0_SEQUENCE_UP _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INST7_0_SEQUENCE_DOWN _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INST7_0_LANE_SEQ_SHIFT _MK_SHIFT_CONST(18) +#define SOR_NV_PDISP_SOR_SEQ_INST7_0_LANE_SEQ_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST7_0_LANE_SEQ_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INST7_0_LANE_SEQ_RANGE 18:18 +#define SOR_NV_PDISP_SOR_SEQ_INST7_0_LANE_SEQ_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INST7_0_LANE_SEQ_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST7_0_LANE_SEQ_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INST7_0_LANE_SEQ_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST7_0_LANE_SEQ_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST7_0_LANE_SEQ_INIT_ENUM STOP +#define SOR_NV_PDISP_SOR_SEQ_INST7_0_LANE_SEQ_STOP _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INST7_0_LANE_SEQ_RUN _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INST7_0_PDPORT_SHIFT _MK_SHIFT_CONST(17) +#define SOR_NV_PDISP_SOR_SEQ_INST7_0_PDPORT_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST7_0_PDPORT_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INST7_0_PDPORT_RANGE 17:17 +#define SOR_NV_PDISP_SOR_SEQ_INST7_0_PDPORT_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INST7_0_PDPORT_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST7_0_PDPORT_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INST7_0_PDPORT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST7_0_PDPORT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST7_0_PDPORT_INIT_ENUM NO +#define SOR_NV_PDISP_SOR_SEQ_INST7_0_PDPORT_NO _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INST7_0_PDPORT_YES _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INST7_0_PDPLL_SHIFT _MK_SHIFT_CONST(16) +#define SOR_NV_PDISP_SOR_SEQ_INST7_0_PDPLL_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST7_0_PDPLL_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INST7_0_PDPLL_RANGE 16:16 +#define SOR_NV_PDISP_SOR_SEQ_INST7_0_PDPLL_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INST7_0_PDPLL_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST7_0_PDPLL_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INST7_0_PDPLL_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST7_0_PDPLL_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST7_0_PDPLL_INIT_ENUM NO +#define SOR_NV_PDISP_SOR_SEQ_INST7_0_PDPLL_NO _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INST7_0_PDPLL_YES _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INST7_0_HALT_SHIFT _MK_SHIFT_CONST(15) +#define SOR_NV_PDISP_SOR_SEQ_INST7_0_HALT_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST7_0_HALT_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INST7_0_HALT_RANGE 15:15 +#define SOR_NV_PDISP_SOR_SEQ_INST7_0_HALT_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INST7_0_HALT_DEFAULT _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INST7_0_HALT_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INST7_0_HALT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST7_0_HALT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST7_0_HALT_INIT_ENUM TRUE +#define SOR_NV_PDISP_SOR_SEQ_INST7_0_HALT_FALSE _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INST7_0_HALT_TRUE _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INST7_0_WAIT_UNITS_SHIFT _MK_SHIFT_CONST(12) +#define SOR_NV_PDISP_SOR_SEQ_INST7_0_WAIT_UNITS_FIELD _MK_FIELD_CONST(0x3, SOR_NV_PDISP_SOR_SEQ_INST7_0_WAIT_UNITS_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INST7_0_WAIT_UNITS_RANGE 13:12 +#define SOR_NV_PDISP_SOR_SEQ_INST7_0_WAIT_UNITS_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INST7_0_WAIT_UNITS_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST7_0_WAIT_UNITS_DEFAULT_MASK _MK_MASK_CONST(0x3) +#define SOR_NV_PDISP_SOR_SEQ_INST7_0_WAIT_UNITS_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST7_0_WAIT_UNITS_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST7_0_WAIT_UNITS_INIT_ENUM US +#define SOR_NV_PDISP_SOR_SEQ_INST7_0_WAIT_UNITS_US _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INST7_0_WAIT_UNITS_MS _MK_ENUM_CONST(1) +#define SOR_NV_PDISP_SOR_SEQ_INST7_0_WAIT_UNITS_VSYNC _MK_ENUM_CONST(2) + +#define SOR_NV_PDISP_SOR_SEQ_INST7_0_WAIT_TIME_SHIFT _MK_SHIFT_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INST7_0_WAIT_TIME_FIELD _MK_FIELD_CONST(0x3ff, SOR_NV_PDISP_SOR_SEQ_INST7_0_WAIT_TIME_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INST7_0_WAIT_TIME_RANGE 9:0 +#define SOR_NV_PDISP_SOR_SEQ_INST7_0_WAIT_TIME_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INST7_0_WAIT_TIME_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST7_0_WAIT_TIME_DEFAULT_MASK _MK_MASK_CONST(0x3ff) +#define SOR_NV_PDISP_SOR_SEQ_INST7_0_WAIT_TIME_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST7_0_WAIT_TIME_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register SOR_NV_PDISP_SOR_SEQ_INST8_0 +#define SOR_NV_PDISP_SOR_SEQ_INST8_0 _MK_ADDR_CONST(0x2a) +#define SOR_NV_PDISP_SOR_SEQ_INST8_0_SECURE 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INST8_0_WORD_COUNT 0x1 +#define SOR_NV_PDISP_SOR_SEQ_INST8_0_RESET_VAL _MK_MASK_CONST(0x1008000) +#define SOR_NV_PDISP_SOR_SEQ_INST8_0_RESET_MASK _MK_MASK_CONST(0xffefb3ff) +#define SOR_NV_PDISP_SOR_SEQ_INST8_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST8_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST8_0_READ_MASK _MK_MASK_CONST(0xffefb3ff) +#define SOR_NV_PDISP_SOR_SEQ_INST8_0_WRITE_MASK _MK_MASK_CONST(0xffefb3ff) +#define SOR_NV_PDISP_SOR_SEQ_INST8_0_PLL_PULLDOWN_SHIFT _MK_SHIFT_CONST(31) +#define SOR_NV_PDISP_SOR_SEQ_INST8_0_PLL_PULLDOWN_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST8_0_PLL_PULLDOWN_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INST8_0_PLL_PULLDOWN_RANGE 31:31 +#define SOR_NV_PDISP_SOR_SEQ_INST8_0_PLL_PULLDOWN_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INST8_0_PLL_PULLDOWN_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST8_0_PLL_PULLDOWN_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INST8_0_PLL_PULLDOWN_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST8_0_PLL_PULLDOWN_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST8_0_PLL_PULLDOWN_INIT_ENUM DISABLE +#define SOR_NV_PDISP_SOR_SEQ_INST8_0_PLL_PULLDOWN_DISABLE _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INST8_0_PLL_PULLDOWN_ENABLE _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INST8_0_POWERDOWN_MACRO_SHIFT _MK_SHIFT_CONST(30) +#define SOR_NV_PDISP_SOR_SEQ_INST8_0_POWERDOWN_MACRO_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST8_0_POWERDOWN_MACRO_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INST8_0_POWERDOWN_MACRO_RANGE 30:30 +#define SOR_NV_PDISP_SOR_SEQ_INST8_0_POWERDOWN_MACRO_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INST8_0_POWERDOWN_MACRO_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST8_0_POWERDOWN_MACRO_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INST8_0_POWERDOWN_MACRO_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST8_0_POWERDOWN_MACRO_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST8_0_POWERDOWN_MACRO_INIT_ENUM NORMAL +#define SOR_NV_PDISP_SOR_SEQ_INST8_0_POWERDOWN_MACRO_NORMAL _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INST8_0_POWERDOWN_MACRO_POWERDOWN _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INST8_0_ASSERT_PLL_RESET_SHIFT _MK_SHIFT_CONST(29) +#define SOR_NV_PDISP_SOR_SEQ_INST8_0_ASSERT_PLL_RESET_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST8_0_ASSERT_PLL_RESET_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INST8_0_ASSERT_PLL_RESET_RANGE 29:29 +#define SOR_NV_PDISP_SOR_SEQ_INST8_0_ASSERT_PLL_RESET_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INST8_0_ASSERT_PLL_RESET_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST8_0_ASSERT_PLL_RESET_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INST8_0_ASSERT_PLL_RESET_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST8_0_ASSERT_PLL_RESET_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST8_0_ASSERT_PLL_RESET_INIT_ENUM NORMAL +#define SOR_NV_PDISP_SOR_SEQ_INST8_0_ASSERT_PLL_RESET_NORMAL _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INST8_0_ASSERT_PLL_RESET_RST _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INST8_0_BLANK_V_SHIFT _MK_SHIFT_CONST(28) +#define SOR_NV_PDISP_SOR_SEQ_INST8_0_BLANK_V_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST8_0_BLANK_V_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INST8_0_BLANK_V_RANGE 28:28 +#define SOR_NV_PDISP_SOR_SEQ_INST8_0_BLANK_V_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INST8_0_BLANK_V_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST8_0_BLANK_V_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INST8_0_BLANK_V_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST8_0_BLANK_V_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST8_0_BLANK_V_INIT_ENUM NORMAL +#define SOR_NV_PDISP_SOR_SEQ_INST8_0_BLANK_V_NORMAL _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INST8_0_BLANK_V_INACTIVE _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INST8_0_BLANK_H_SHIFT _MK_SHIFT_CONST(27) +#define SOR_NV_PDISP_SOR_SEQ_INST8_0_BLANK_H_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST8_0_BLANK_H_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INST8_0_BLANK_H_RANGE 27:27 +#define SOR_NV_PDISP_SOR_SEQ_INST8_0_BLANK_H_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INST8_0_BLANK_H_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST8_0_BLANK_H_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INST8_0_BLANK_H_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST8_0_BLANK_H_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST8_0_BLANK_H_INIT_ENUM NORMAL +#define SOR_NV_PDISP_SOR_SEQ_INST8_0_BLANK_H_NORMAL _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INST8_0_BLANK_H_INACTIVE _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INST8_0_BLANK_DE_SHIFT _MK_SHIFT_CONST(26) +#define SOR_NV_PDISP_SOR_SEQ_INST8_0_BLANK_DE_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST8_0_BLANK_DE_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INST8_0_BLANK_DE_RANGE 26:26 +#define SOR_NV_PDISP_SOR_SEQ_INST8_0_BLANK_DE_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INST8_0_BLANK_DE_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST8_0_BLANK_DE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INST8_0_BLANK_DE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST8_0_BLANK_DE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST8_0_BLANK_DE_INIT_ENUM NORMAL +#define SOR_NV_PDISP_SOR_SEQ_INST8_0_BLANK_DE_NORMAL _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INST8_0_BLANK_DE_INACTIVE _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INST8_0_BLACK_DATA_SHIFT _MK_SHIFT_CONST(25) +#define SOR_NV_PDISP_SOR_SEQ_INST8_0_BLACK_DATA_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST8_0_BLACK_DATA_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INST8_0_BLACK_DATA_RANGE 25:25 +#define SOR_NV_PDISP_SOR_SEQ_INST8_0_BLACK_DATA_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INST8_0_BLACK_DATA_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST8_0_BLACK_DATA_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INST8_0_BLACK_DATA_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST8_0_BLACK_DATA_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST8_0_BLACK_DATA_INIT_ENUM NORMAL +#define SOR_NV_PDISP_SOR_SEQ_INST8_0_BLACK_DATA_NORMAL _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INST8_0_BLACK_DATA_BLACK _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INST8_0_TRISTATE_IOS_SHIFT _MK_SHIFT_CONST(24) +#define SOR_NV_PDISP_SOR_SEQ_INST8_0_TRISTATE_IOS_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST8_0_TRISTATE_IOS_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INST8_0_TRISTATE_IOS_RANGE 24:24 +#define SOR_NV_PDISP_SOR_SEQ_INST8_0_TRISTATE_IOS_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INST8_0_TRISTATE_IOS_DEFAULT _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INST8_0_TRISTATE_IOS_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INST8_0_TRISTATE_IOS_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST8_0_TRISTATE_IOS_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST8_0_TRISTATE_IOS_INIT_ENUM TRISTATE +#define SOR_NV_PDISP_SOR_SEQ_INST8_0_TRISTATE_IOS_ENABLE_PINS _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INST8_0_TRISTATE_IOS_TRISTATE _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INST8_0_DRIVE_PWM_OUT_LO_SHIFT _MK_SHIFT_CONST(23) +#define SOR_NV_PDISP_SOR_SEQ_INST8_0_DRIVE_PWM_OUT_LO_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST8_0_DRIVE_PWM_OUT_LO_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INST8_0_DRIVE_PWM_OUT_LO_RANGE 23:23 +#define SOR_NV_PDISP_SOR_SEQ_INST8_0_DRIVE_PWM_OUT_LO_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INST8_0_DRIVE_PWM_OUT_LO_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST8_0_DRIVE_PWM_OUT_LO_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INST8_0_DRIVE_PWM_OUT_LO_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST8_0_DRIVE_PWM_OUT_LO_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST8_0_DRIVE_PWM_OUT_LO_INIT_ENUM FALSE +#define SOR_NV_PDISP_SOR_SEQ_INST8_0_DRIVE_PWM_OUT_LO_FALSE _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INST8_0_DRIVE_PWM_OUT_LO_TRUE _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INST8_0_PIN_B_SHIFT _MK_SHIFT_CONST(22) +#define SOR_NV_PDISP_SOR_SEQ_INST8_0_PIN_B_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST8_0_PIN_B_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INST8_0_PIN_B_RANGE 22:22 +#define SOR_NV_PDISP_SOR_SEQ_INST8_0_PIN_B_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INST8_0_PIN_B_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST8_0_PIN_B_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INST8_0_PIN_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST8_0_PIN_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST8_0_PIN_B_INIT_ENUM LOW +#define SOR_NV_PDISP_SOR_SEQ_INST8_0_PIN_B_LOW _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INST8_0_PIN_B_HIGH _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INST8_0_PIN_A_SHIFT _MK_SHIFT_CONST(21) +#define SOR_NV_PDISP_SOR_SEQ_INST8_0_PIN_A_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST8_0_PIN_A_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INST8_0_PIN_A_RANGE 21:21 +#define SOR_NV_PDISP_SOR_SEQ_INST8_0_PIN_A_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INST8_0_PIN_A_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST8_0_PIN_A_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INST8_0_PIN_A_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST8_0_PIN_A_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST8_0_PIN_A_INIT_ENUM LOW +#define SOR_NV_PDISP_SOR_SEQ_INST8_0_PIN_A_LOW _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INST8_0_PIN_A_HIGH _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INST8_0_SEQUENCE_SHIFT _MK_SHIFT_CONST(19) +#define SOR_NV_PDISP_SOR_SEQ_INST8_0_SEQUENCE_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST8_0_SEQUENCE_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INST8_0_SEQUENCE_RANGE 19:19 +#define SOR_NV_PDISP_SOR_SEQ_INST8_0_SEQUENCE_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INST8_0_SEQUENCE_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST8_0_SEQUENCE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INST8_0_SEQUENCE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST8_0_SEQUENCE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST8_0_SEQUENCE_INIT_ENUM UP +#define SOR_NV_PDISP_SOR_SEQ_INST8_0_SEQUENCE_UP _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INST8_0_SEQUENCE_DOWN _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INST8_0_LANE_SEQ_SHIFT _MK_SHIFT_CONST(18) +#define SOR_NV_PDISP_SOR_SEQ_INST8_0_LANE_SEQ_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST8_0_LANE_SEQ_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INST8_0_LANE_SEQ_RANGE 18:18 +#define SOR_NV_PDISP_SOR_SEQ_INST8_0_LANE_SEQ_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INST8_0_LANE_SEQ_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST8_0_LANE_SEQ_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INST8_0_LANE_SEQ_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST8_0_LANE_SEQ_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST8_0_LANE_SEQ_INIT_ENUM STOP +#define SOR_NV_PDISP_SOR_SEQ_INST8_0_LANE_SEQ_STOP _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INST8_0_LANE_SEQ_RUN _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INST8_0_PDPORT_SHIFT _MK_SHIFT_CONST(17) +#define SOR_NV_PDISP_SOR_SEQ_INST8_0_PDPORT_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST8_0_PDPORT_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INST8_0_PDPORT_RANGE 17:17 +#define SOR_NV_PDISP_SOR_SEQ_INST8_0_PDPORT_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INST8_0_PDPORT_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST8_0_PDPORT_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INST8_0_PDPORT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST8_0_PDPORT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST8_0_PDPORT_INIT_ENUM NO +#define SOR_NV_PDISP_SOR_SEQ_INST8_0_PDPORT_NO _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INST8_0_PDPORT_YES _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INST8_0_PDPLL_SHIFT _MK_SHIFT_CONST(16) +#define SOR_NV_PDISP_SOR_SEQ_INST8_0_PDPLL_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST8_0_PDPLL_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INST8_0_PDPLL_RANGE 16:16 +#define SOR_NV_PDISP_SOR_SEQ_INST8_0_PDPLL_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INST8_0_PDPLL_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST8_0_PDPLL_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INST8_0_PDPLL_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST8_0_PDPLL_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST8_0_PDPLL_INIT_ENUM NO +#define SOR_NV_PDISP_SOR_SEQ_INST8_0_PDPLL_NO _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INST8_0_PDPLL_YES _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INST8_0_HALT_SHIFT _MK_SHIFT_CONST(15) +#define SOR_NV_PDISP_SOR_SEQ_INST8_0_HALT_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST8_0_HALT_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INST8_0_HALT_RANGE 15:15 +#define SOR_NV_PDISP_SOR_SEQ_INST8_0_HALT_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INST8_0_HALT_DEFAULT _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INST8_0_HALT_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INST8_0_HALT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST8_0_HALT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST8_0_HALT_INIT_ENUM TRUE +#define SOR_NV_PDISP_SOR_SEQ_INST8_0_HALT_FALSE _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INST8_0_HALT_TRUE _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INST8_0_WAIT_UNITS_SHIFT _MK_SHIFT_CONST(12) +#define SOR_NV_PDISP_SOR_SEQ_INST8_0_WAIT_UNITS_FIELD _MK_FIELD_CONST(0x3, SOR_NV_PDISP_SOR_SEQ_INST8_0_WAIT_UNITS_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INST8_0_WAIT_UNITS_RANGE 13:12 +#define SOR_NV_PDISP_SOR_SEQ_INST8_0_WAIT_UNITS_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INST8_0_WAIT_UNITS_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST8_0_WAIT_UNITS_DEFAULT_MASK _MK_MASK_CONST(0x3) +#define SOR_NV_PDISP_SOR_SEQ_INST8_0_WAIT_UNITS_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST8_0_WAIT_UNITS_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST8_0_WAIT_UNITS_INIT_ENUM US +#define SOR_NV_PDISP_SOR_SEQ_INST8_0_WAIT_UNITS_US _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INST8_0_WAIT_UNITS_MS _MK_ENUM_CONST(1) +#define SOR_NV_PDISP_SOR_SEQ_INST8_0_WAIT_UNITS_VSYNC _MK_ENUM_CONST(2) + +#define SOR_NV_PDISP_SOR_SEQ_INST8_0_WAIT_TIME_SHIFT _MK_SHIFT_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INST8_0_WAIT_TIME_FIELD _MK_FIELD_CONST(0x3ff, SOR_NV_PDISP_SOR_SEQ_INST8_0_WAIT_TIME_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INST8_0_WAIT_TIME_RANGE 9:0 +#define SOR_NV_PDISP_SOR_SEQ_INST8_0_WAIT_TIME_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INST8_0_WAIT_TIME_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST8_0_WAIT_TIME_DEFAULT_MASK _MK_MASK_CONST(0x3ff) +#define SOR_NV_PDISP_SOR_SEQ_INST8_0_WAIT_TIME_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST8_0_WAIT_TIME_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register SOR_NV_PDISP_SOR_SEQ_INST9_0 +#define SOR_NV_PDISP_SOR_SEQ_INST9_0 _MK_ADDR_CONST(0x2b) +#define SOR_NV_PDISP_SOR_SEQ_INST9_0_SECURE 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INST9_0_WORD_COUNT 0x1 +#define SOR_NV_PDISP_SOR_SEQ_INST9_0_RESET_VAL _MK_MASK_CONST(0x1008000) +#define SOR_NV_PDISP_SOR_SEQ_INST9_0_RESET_MASK _MK_MASK_CONST(0xffefb3ff) +#define SOR_NV_PDISP_SOR_SEQ_INST9_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST9_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST9_0_READ_MASK _MK_MASK_CONST(0xffefb3ff) +#define SOR_NV_PDISP_SOR_SEQ_INST9_0_WRITE_MASK _MK_MASK_CONST(0xffefb3ff) +#define SOR_NV_PDISP_SOR_SEQ_INST9_0_PLL_PULLDOWN_SHIFT _MK_SHIFT_CONST(31) +#define SOR_NV_PDISP_SOR_SEQ_INST9_0_PLL_PULLDOWN_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST9_0_PLL_PULLDOWN_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INST9_0_PLL_PULLDOWN_RANGE 31:31 +#define SOR_NV_PDISP_SOR_SEQ_INST9_0_PLL_PULLDOWN_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INST9_0_PLL_PULLDOWN_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST9_0_PLL_PULLDOWN_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INST9_0_PLL_PULLDOWN_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST9_0_PLL_PULLDOWN_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST9_0_PLL_PULLDOWN_INIT_ENUM DISABLE +#define SOR_NV_PDISP_SOR_SEQ_INST9_0_PLL_PULLDOWN_DISABLE _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INST9_0_PLL_PULLDOWN_ENABLE _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INST9_0_POWERDOWN_MACRO_SHIFT _MK_SHIFT_CONST(30) +#define SOR_NV_PDISP_SOR_SEQ_INST9_0_POWERDOWN_MACRO_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST9_0_POWERDOWN_MACRO_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INST9_0_POWERDOWN_MACRO_RANGE 30:30 +#define SOR_NV_PDISP_SOR_SEQ_INST9_0_POWERDOWN_MACRO_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INST9_0_POWERDOWN_MACRO_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST9_0_POWERDOWN_MACRO_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INST9_0_POWERDOWN_MACRO_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST9_0_POWERDOWN_MACRO_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST9_0_POWERDOWN_MACRO_INIT_ENUM NORMAL +#define SOR_NV_PDISP_SOR_SEQ_INST9_0_POWERDOWN_MACRO_NORMAL _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INST9_0_POWERDOWN_MACRO_POWERDOWN _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INST9_0_ASSERT_PLL_RESET_SHIFT _MK_SHIFT_CONST(29) +#define SOR_NV_PDISP_SOR_SEQ_INST9_0_ASSERT_PLL_RESET_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST9_0_ASSERT_PLL_RESET_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INST9_0_ASSERT_PLL_RESET_RANGE 29:29 +#define SOR_NV_PDISP_SOR_SEQ_INST9_0_ASSERT_PLL_RESET_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INST9_0_ASSERT_PLL_RESET_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST9_0_ASSERT_PLL_RESET_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INST9_0_ASSERT_PLL_RESET_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST9_0_ASSERT_PLL_RESET_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST9_0_ASSERT_PLL_RESET_INIT_ENUM NORMAL +#define SOR_NV_PDISP_SOR_SEQ_INST9_0_ASSERT_PLL_RESET_NORMAL _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INST9_0_ASSERT_PLL_RESET_RST _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INST9_0_BLANK_V_SHIFT _MK_SHIFT_CONST(28) +#define SOR_NV_PDISP_SOR_SEQ_INST9_0_BLANK_V_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST9_0_BLANK_V_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INST9_0_BLANK_V_RANGE 28:28 +#define SOR_NV_PDISP_SOR_SEQ_INST9_0_BLANK_V_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INST9_0_BLANK_V_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST9_0_BLANK_V_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INST9_0_BLANK_V_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST9_0_BLANK_V_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST9_0_BLANK_V_INIT_ENUM NORMAL +#define SOR_NV_PDISP_SOR_SEQ_INST9_0_BLANK_V_NORMAL _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INST9_0_BLANK_V_INACTIVE _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INST9_0_BLANK_H_SHIFT _MK_SHIFT_CONST(27) +#define SOR_NV_PDISP_SOR_SEQ_INST9_0_BLANK_H_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST9_0_BLANK_H_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INST9_0_BLANK_H_RANGE 27:27 +#define SOR_NV_PDISP_SOR_SEQ_INST9_0_BLANK_H_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INST9_0_BLANK_H_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST9_0_BLANK_H_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INST9_0_BLANK_H_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST9_0_BLANK_H_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST9_0_BLANK_H_INIT_ENUM NORMAL +#define SOR_NV_PDISP_SOR_SEQ_INST9_0_BLANK_H_NORMAL _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INST9_0_BLANK_H_INACTIVE _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INST9_0_BLANK_DE_SHIFT _MK_SHIFT_CONST(26) +#define SOR_NV_PDISP_SOR_SEQ_INST9_0_BLANK_DE_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST9_0_BLANK_DE_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INST9_0_BLANK_DE_RANGE 26:26 +#define SOR_NV_PDISP_SOR_SEQ_INST9_0_BLANK_DE_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INST9_0_BLANK_DE_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST9_0_BLANK_DE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INST9_0_BLANK_DE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST9_0_BLANK_DE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST9_0_BLANK_DE_INIT_ENUM NORMAL +#define SOR_NV_PDISP_SOR_SEQ_INST9_0_BLANK_DE_NORMAL _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INST9_0_BLANK_DE_INACTIVE _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INST9_0_BLACK_DATA_SHIFT _MK_SHIFT_CONST(25) +#define SOR_NV_PDISP_SOR_SEQ_INST9_0_BLACK_DATA_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST9_0_BLACK_DATA_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INST9_0_BLACK_DATA_RANGE 25:25 +#define SOR_NV_PDISP_SOR_SEQ_INST9_0_BLACK_DATA_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INST9_0_BLACK_DATA_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST9_0_BLACK_DATA_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INST9_0_BLACK_DATA_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST9_0_BLACK_DATA_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST9_0_BLACK_DATA_INIT_ENUM NORMAL +#define SOR_NV_PDISP_SOR_SEQ_INST9_0_BLACK_DATA_NORMAL _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INST9_0_BLACK_DATA_BLACK _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INST9_0_TRISTATE_IOS_SHIFT _MK_SHIFT_CONST(24) +#define SOR_NV_PDISP_SOR_SEQ_INST9_0_TRISTATE_IOS_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST9_0_TRISTATE_IOS_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INST9_0_TRISTATE_IOS_RANGE 24:24 +#define SOR_NV_PDISP_SOR_SEQ_INST9_0_TRISTATE_IOS_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INST9_0_TRISTATE_IOS_DEFAULT _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INST9_0_TRISTATE_IOS_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INST9_0_TRISTATE_IOS_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST9_0_TRISTATE_IOS_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST9_0_TRISTATE_IOS_INIT_ENUM TRISTATE +#define SOR_NV_PDISP_SOR_SEQ_INST9_0_TRISTATE_IOS_ENABLE_PINS _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INST9_0_TRISTATE_IOS_TRISTATE _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INST9_0_DRIVE_PWM_OUT_LO_SHIFT _MK_SHIFT_CONST(23) +#define SOR_NV_PDISP_SOR_SEQ_INST9_0_DRIVE_PWM_OUT_LO_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST9_0_DRIVE_PWM_OUT_LO_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INST9_0_DRIVE_PWM_OUT_LO_RANGE 23:23 +#define SOR_NV_PDISP_SOR_SEQ_INST9_0_DRIVE_PWM_OUT_LO_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INST9_0_DRIVE_PWM_OUT_LO_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST9_0_DRIVE_PWM_OUT_LO_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INST9_0_DRIVE_PWM_OUT_LO_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST9_0_DRIVE_PWM_OUT_LO_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST9_0_DRIVE_PWM_OUT_LO_INIT_ENUM FALSE +#define SOR_NV_PDISP_SOR_SEQ_INST9_0_DRIVE_PWM_OUT_LO_FALSE _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INST9_0_DRIVE_PWM_OUT_LO_TRUE _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INST9_0_PIN_B_SHIFT _MK_SHIFT_CONST(22) +#define SOR_NV_PDISP_SOR_SEQ_INST9_0_PIN_B_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST9_0_PIN_B_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INST9_0_PIN_B_RANGE 22:22 +#define SOR_NV_PDISP_SOR_SEQ_INST9_0_PIN_B_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INST9_0_PIN_B_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST9_0_PIN_B_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INST9_0_PIN_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST9_0_PIN_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST9_0_PIN_B_INIT_ENUM LOW +#define SOR_NV_PDISP_SOR_SEQ_INST9_0_PIN_B_LOW _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INST9_0_PIN_B_HIGH _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INST9_0_PIN_A_SHIFT _MK_SHIFT_CONST(21) +#define SOR_NV_PDISP_SOR_SEQ_INST9_0_PIN_A_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST9_0_PIN_A_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INST9_0_PIN_A_RANGE 21:21 +#define SOR_NV_PDISP_SOR_SEQ_INST9_0_PIN_A_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INST9_0_PIN_A_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST9_0_PIN_A_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INST9_0_PIN_A_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST9_0_PIN_A_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST9_0_PIN_A_INIT_ENUM LOW +#define SOR_NV_PDISP_SOR_SEQ_INST9_0_PIN_A_LOW _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INST9_0_PIN_A_HIGH _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INST9_0_SEQUENCE_SHIFT _MK_SHIFT_CONST(19) +#define SOR_NV_PDISP_SOR_SEQ_INST9_0_SEQUENCE_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST9_0_SEQUENCE_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INST9_0_SEQUENCE_RANGE 19:19 +#define SOR_NV_PDISP_SOR_SEQ_INST9_0_SEQUENCE_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INST9_0_SEQUENCE_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST9_0_SEQUENCE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INST9_0_SEQUENCE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST9_0_SEQUENCE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST9_0_SEQUENCE_INIT_ENUM UP +#define SOR_NV_PDISP_SOR_SEQ_INST9_0_SEQUENCE_UP _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INST9_0_SEQUENCE_DOWN _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INST9_0_LANE_SEQ_SHIFT _MK_SHIFT_CONST(18) +#define SOR_NV_PDISP_SOR_SEQ_INST9_0_LANE_SEQ_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST9_0_LANE_SEQ_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INST9_0_LANE_SEQ_RANGE 18:18 +#define SOR_NV_PDISP_SOR_SEQ_INST9_0_LANE_SEQ_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INST9_0_LANE_SEQ_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST9_0_LANE_SEQ_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INST9_0_LANE_SEQ_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST9_0_LANE_SEQ_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST9_0_LANE_SEQ_INIT_ENUM STOP +#define SOR_NV_PDISP_SOR_SEQ_INST9_0_LANE_SEQ_STOP _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INST9_0_LANE_SEQ_RUN _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INST9_0_PDPORT_SHIFT _MK_SHIFT_CONST(17) +#define SOR_NV_PDISP_SOR_SEQ_INST9_0_PDPORT_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST9_0_PDPORT_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INST9_0_PDPORT_RANGE 17:17 +#define SOR_NV_PDISP_SOR_SEQ_INST9_0_PDPORT_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INST9_0_PDPORT_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST9_0_PDPORT_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INST9_0_PDPORT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST9_0_PDPORT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST9_0_PDPORT_INIT_ENUM NO +#define SOR_NV_PDISP_SOR_SEQ_INST9_0_PDPORT_NO _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INST9_0_PDPORT_YES _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INST9_0_PDPLL_SHIFT _MK_SHIFT_CONST(16) +#define SOR_NV_PDISP_SOR_SEQ_INST9_0_PDPLL_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST9_0_PDPLL_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INST9_0_PDPLL_RANGE 16:16 +#define SOR_NV_PDISP_SOR_SEQ_INST9_0_PDPLL_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INST9_0_PDPLL_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST9_0_PDPLL_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INST9_0_PDPLL_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST9_0_PDPLL_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST9_0_PDPLL_INIT_ENUM NO +#define SOR_NV_PDISP_SOR_SEQ_INST9_0_PDPLL_NO _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INST9_0_PDPLL_YES _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INST9_0_HALT_SHIFT _MK_SHIFT_CONST(15) +#define SOR_NV_PDISP_SOR_SEQ_INST9_0_HALT_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INST9_0_HALT_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INST9_0_HALT_RANGE 15:15 +#define SOR_NV_PDISP_SOR_SEQ_INST9_0_HALT_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INST9_0_HALT_DEFAULT _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INST9_0_HALT_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INST9_0_HALT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST9_0_HALT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST9_0_HALT_INIT_ENUM TRUE +#define SOR_NV_PDISP_SOR_SEQ_INST9_0_HALT_FALSE _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INST9_0_HALT_TRUE _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INST9_0_WAIT_UNITS_SHIFT _MK_SHIFT_CONST(12) +#define SOR_NV_PDISP_SOR_SEQ_INST9_0_WAIT_UNITS_FIELD _MK_FIELD_CONST(0x3, SOR_NV_PDISP_SOR_SEQ_INST9_0_WAIT_UNITS_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INST9_0_WAIT_UNITS_RANGE 13:12 +#define SOR_NV_PDISP_SOR_SEQ_INST9_0_WAIT_UNITS_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INST9_0_WAIT_UNITS_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST9_0_WAIT_UNITS_DEFAULT_MASK _MK_MASK_CONST(0x3) +#define SOR_NV_PDISP_SOR_SEQ_INST9_0_WAIT_UNITS_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST9_0_WAIT_UNITS_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST9_0_WAIT_UNITS_INIT_ENUM US +#define SOR_NV_PDISP_SOR_SEQ_INST9_0_WAIT_UNITS_US _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INST9_0_WAIT_UNITS_MS _MK_ENUM_CONST(1) +#define SOR_NV_PDISP_SOR_SEQ_INST9_0_WAIT_UNITS_VSYNC _MK_ENUM_CONST(2) + +#define SOR_NV_PDISP_SOR_SEQ_INST9_0_WAIT_TIME_SHIFT _MK_SHIFT_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INST9_0_WAIT_TIME_FIELD _MK_FIELD_CONST(0x3ff, SOR_NV_PDISP_SOR_SEQ_INST9_0_WAIT_TIME_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INST9_0_WAIT_TIME_RANGE 9:0 +#define SOR_NV_PDISP_SOR_SEQ_INST9_0_WAIT_TIME_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INST9_0_WAIT_TIME_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST9_0_WAIT_TIME_DEFAULT_MASK _MK_MASK_CONST(0x3ff) +#define SOR_NV_PDISP_SOR_SEQ_INST9_0_WAIT_TIME_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INST9_0_WAIT_TIME_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register SOR_NV_PDISP_SOR_SEQ_INSTA_0 +#define SOR_NV_PDISP_SOR_SEQ_INSTA_0 _MK_ADDR_CONST(0x2c) +#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_SECURE 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_WORD_COUNT 0x1 +#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_RESET_VAL _MK_MASK_CONST(0x1008000) +#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_RESET_MASK _MK_MASK_CONST(0xffefb3ff) +#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_READ_MASK _MK_MASK_CONST(0xffefb3ff) +#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_WRITE_MASK _MK_MASK_CONST(0xffefb3ff) +#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_PLL_PULLDOWN_SHIFT _MK_SHIFT_CONST(31) +#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_PLL_PULLDOWN_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INSTA_0_PLL_PULLDOWN_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_PLL_PULLDOWN_RANGE 31:31 +#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_PLL_PULLDOWN_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_PLL_PULLDOWN_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_PLL_PULLDOWN_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_PLL_PULLDOWN_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_PLL_PULLDOWN_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_PLL_PULLDOWN_INIT_ENUM DISABLE +#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_PLL_PULLDOWN_DISABLE _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_PLL_PULLDOWN_ENABLE _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_POWERDOWN_MACRO_SHIFT _MK_SHIFT_CONST(30) +#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_POWERDOWN_MACRO_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INSTA_0_POWERDOWN_MACRO_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_POWERDOWN_MACRO_RANGE 30:30 +#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_POWERDOWN_MACRO_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_POWERDOWN_MACRO_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_POWERDOWN_MACRO_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_POWERDOWN_MACRO_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_POWERDOWN_MACRO_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_POWERDOWN_MACRO_INIT_ENUM NORMAL +#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_POWERDOWN_MACRO_NORMAL _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_POWERDOWN_MACRO_POWERDOWN _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_ASSERT_PLL_RESET_SHIFT _MK_SHIFT_CONST(29) +#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_ASSERT_PLL_RESET_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INSTA_0_ASSERT_PLL_RESET_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_ASSERT_PLL_RESET_RANGE 29:29 +#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_ASSERT_PLL_RESET_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_ASSERT_PLL_RESET_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_ASSERT_PLL_RESET_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_ASSERT_PLL_RESET_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_ASSERT_PLL_RESET_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_ASSERT_PLL_RESET_INIT_ENUM NORMAL +#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_ASSERT_PLL_RESET_NORMAL _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_ASSERT_PLL_RESET_RST _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_BLANK_V_SHIFT _MK_SHIFT_CONST(28) +#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_BLANK_V_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INSTA_0_BLANK_V_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_BLANK_V_RANGE 28:28 +#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_BLANK_V_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_BLANK_V_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_BLANK_V_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_BLANK_V_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_BLANK_V_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_BLANK_V_INIT_ENUM NORMAL +#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_BLANK_V_NORMAL _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_BLANK_V_INACTIVE _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_BLANK_H_SHIFT _MK_SHIFT_CONST(27) +#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_BLANK_H_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INSTA_0_BLANK_H_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_BLANK_H_RANGE 27:27 +#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_BLANK_H_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_BLANK_H_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_BLANK_H_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_BLANK_H_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_BLANK_H_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_BLANK_H_INIT_ENUM NORMAL +#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_BLANK_H_NORMAL _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_BLANK_H_INACTIVE _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_BLANK_DE_SHIFT _MK_SHIFT_CONST(26) +#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_BLANK_DE_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INSTA_0_BLANK_DE_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_BLANK_DE_RANGE 26:26 +#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_BLANK_DE_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_BLANK_DE_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_BLANK_DE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_BLANK_DE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_BLANK_DE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_BLANK_DE_INIT_ENUM NORMAL +#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_BLANK_DE_NORMAL _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_BLANK_DE_INACTIVE _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_BLACK_DATA_SHIFT _MK_SHIFT_CONST(25) +#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_BLACK_DATA_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INSTA_0_BLACK_DATA_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_BLACK_DATA_RANGE 25:25 +#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_BLACK_DATA_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_BLACK_DATA_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_BLACK_DATA_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_BLACK_DATA_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_BLACK_DATA_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_BLACK_DATA_INIT_ENUM NORMAL +#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_BLACK_DATA_NORMAL _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_BLACK_DATA_BLACK _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_TRISTATE_IOS_SHIFT _MK_SHIFT_CONST(24) +#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_TRISTATE_IOS_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INSTA_0_TRISTATE_IOS_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_TRISTATE_IOS_RANGE 24:24 +#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_TRISTATE_IOS_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_TRISTATE_IOS_DEFAULT _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_TRISTATE_IOS_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_TRISTATE_IOS_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_TRISTATE_IOS_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_TRISTATE_IOS_INIT_ENUM TRISTATE +#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_TRISTATE_IOS_ENABLE_PINS _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_TRISTATE_IOS_TRISTATE _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_DRIVE_PWM_OUT_LO_SHIFT _MK_SHIFT_CONST(23) +#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_DRIVE_PWM_OUT_LO_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INSTA_0_DRIVE_PWM_OUT_LO_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_DRIVE_PWM_OUT_LO_RANGE 23:23 +#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_DRIVE_PWM_OUT_LO_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_DRIVE_PWM_OUT_LO_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_DRIVE_PWM_OUT_LO_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_DRIVE_PWM_OUT_LO_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_DRIVE_PWM_OUT_LO_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_DRIVE_PWM_OUT_LO_INIT_ENUM FALSE +#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_DRIVE_PWM_OUT_LO_FALSE _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_DRIVE_PWM_OUT_LO_TRUE _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_PIN_B_SHIFT _MK_SHIFT_CONST(22) +#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_PIN_B_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INSTA_0_PIN_B_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_PIN_B_RANGE 22:22 +#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_PIN_B_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_PIN_B_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_PIN_B_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_PIN_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_PIN_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_PIN_B_INIT_ENUM LOW +#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_PIN_B_LOW _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_PIN_B_HIGH _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_PIN_A_SHIFT _MK_SHIFT_CONST(21) +#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_PIN_A_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INSTA_0_PIN_A_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_PIN_A_RANGE 21:21 +#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_PIN_A_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_PIN_A_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_PIN_A_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_PIN_A_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_PIN_A_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_PIN_A_INIT_ENUM LOW +#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_PIN_A_LOW _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_PIN_A_HIGH _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_SEQUENCE_SHIFT _MK_SHIFT_CONST(19) +#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_SEQUENCE_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INSTA_0_SEQUENCE_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_SEQUENCE_RANGE 19:19 +#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_SEQUENCE_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_SEQUENCE_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_SEQUENCE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_SEQUENCE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_SEQUENCE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_SEQUENCE_INIT_ENUM UP +#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_SEQUENCE_UP _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_SEQUENCE_DOWN _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_LANE_SEQ_SHIFT _MK_SHIFT_CONST(18) +#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_LANE_SEQ_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INSTA_0_LANE_SEQ_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_LANE_SEQ_RANGE 18:18 +#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_LANE_SEQ_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_LANE_SEQ_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_LANE_SEQ_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_LANE_SEQ_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_LANE_SEQ_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_LANE_SEQ_INIT_ENUM STOP +#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_LANE_SEQ_STOP _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_LANE_SEQ_RUN _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_PDPORT_SHIFT _MK_SHIFT_CONST(17) +#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_PDPORT_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INSTA_0_PDPORT_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_PDPORT_RANGE 17:17 +#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_PDPORT_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_PDPORT_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_PDPORT_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_PDPORT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_PDPORT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_PDPORT_INIT_ENUM NO +#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_PDPORT_NO _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_PDPORT_YES _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_PDPLL_SHIFT _MK_SHIFT_CONST(16) +#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_PDPLL_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INSTA_0_PDPLL_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_PDPLL_RANGE 16:16 +#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_PDPLL_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_PDPLL_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_PDPLL_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_PDPLL_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_PDPLL_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_PDPLL_INIT_ENUM NO +#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_PDPLL_NO _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_PDPLL_YES _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_HALT_SHIFT _MK_SHIFT_CONST(15) +#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_HALT_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INSTA_0_HALT_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_HALT_RANGE 15:15 +#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_HALT_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_HALT_DEFAULT _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_HALT_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_HALT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_HALT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_HALT_INIT_ENUM TRUE +#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_HALT_FALSE _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_HALT_TRUE _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_WAIT_UNITS_SHIFT _MK_SHIFT_CONST(12) +#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_WAIT_UNITS_FIELD _MK_FIELD_CONST(0x3, SOR_NV_PDISP_SOR_SEQ_INSTA_0_WAIT_UNITS_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_WAIT_UNITS_RANGE 13:12 +#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_WAIT_UNITS_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_WAIT_UNITS_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_WAIT_UNITS_DEFAULT_MASK _MK_MASK_CONST(0x3) +#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_WAIT_UNITS_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_WAIT_UNITS_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_WAIT_UNITS_INIT_ENUM US +#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_WAIT_UNITS_US _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_WAIT_UNITS_MS _MK_ENUM_CONST(1) +#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_WAIT_UNITS_VSYNC _MK_ENUM_CONST(2) + +#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_WAIT_TIME_SHIFT _MK_SHIFT_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_WAIT_TIME_FIELD _MK_FIELD_CONST(0x3ff, SOR_NV_PDISP_SOR_SEQ_INSTA_0_WAIT_TIME_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_WAIT_TIME_RANGE 9:0 +#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_WAIT_TIME_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_WAIT_TIME_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_WAIT_TIME_DEFAULT_MASK _MK_MASK_CONST(0x3ff) +#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_WAIT_TIME_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTA_0_WAIT_TIME_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register SOR_NV_PDISP_SOR_SEQ_INSTB_0 +#define SOR_NV_PDISP_SOR_SEQ_INSTB_0 _MK_ADDR_CONST(0x2d) +#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_SECURE 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_WORD_COUNT 0x1 +#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_RESET_VAL _MK_MASK_CONST(0x1008000) +#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_RESET_MASK _MK_MASK_CONST(0xffefb3ff) +#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_READ_MASK _MK_MASK_CONST(0xffefb3ff) +#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_WRITE_MASK _MK_MASK_CONST(0xffefb3ff) +#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_PLL_PULLDOWN_SHIFT _MK_SHIFT_CONST(31) +#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_PLL_PULLDOWN_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INSTB_0_PLL_PULLDOWN_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_PLL_PULLDOWN_RANGE 31:31 +#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_PLL_PULLDOWN_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_PLL_PULLDOWN_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_PLL_PULLDOWN_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_PLL_PULLDOWN_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_PLL_PULLDOWN_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_PLL_PULLDOWN_INIT_ENUM DISABLE +#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_PLL_PULLDOWN_DISABLE _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_PLL_PULLDOWN_ENABLE _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_POWERDOWN_MACRO_SHIFT _MK_SHIFT_CONST(30) +#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_POWERDOWN_MACRO_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INSTB_0_POWERDOWN_MACRO_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_POWERDOWN_MACRO_RANGE 30:30 +#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_POWERDOWN_MACRO_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_POWERDOWN_MACRO_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_POWERDOWN_MACRO_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_POWERDOWN_MACRO_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_POWERDOWN_MACRO_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_POWERDOWN_MACRO_INIT_ENUM NORMAL +#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_POWERDOWN_MACRO_NORMAL _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_POWERDOWN_MACRO_POWERDOWN _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_ASSERT_PLL_RESET_SHIFT _MK_SHIFT_CONST(29) +#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_ASSERT_PLL_RESET_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INSTB_0_ASSERT_PLL_RESET_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_ASSERT_PLL_RESET_RANGE 29:29 +#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_ASSERT_PLL_RESET_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_ASSERT_PLL_RESET_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_ASSERT_PLL_RESET_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_ASSERT_PLL_RESET_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_ASSERT_PLL_RESET_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_ASSERT_PLL_RESET_INIT_ENUM NORMAL +#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_ASSERT_PLL_RESET_NORMAL _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_ASSERT_PLL_RESET_RST _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_BLANK_V_SHIFT _MK_SHIFT_CONST(28) +#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_BLANK_V_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INSTB_0_BLANK_V_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_BLANK_V_RANGE 28:28 +#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_BLANK_V_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_BLANK_V_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_BLANK_V_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_BLANK_V_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_BLANK_V_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_BLANK_V_INIT_ENUM NORMAL +#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_BLANK_V_NORMAL _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_BLANK_V_INACTIVE _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_BLANK_H_SHIFT _MK_SHIFT_CONST(27) +#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_BLANK_H_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INSTB_0_BLANK_H_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_BLANK_H_RANGE 27:27 +#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_BLANK_H_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_BLANK_H_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_BLANK_H_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_BLANK_H_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_BLANK_H_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_BLANK_H_INIT_ENUM NORMAL +#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_BLANK_H_NORMAL _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_BLANK_H_INACTIVE _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_BLANK_DE_SHIFT _MK_SHIFT_CONST(26) +#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_BLANK_DE_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INSTB_0_BLANK_DE_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_BLANK_DE_RANGE 26:26 +#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_BLANK_DE_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_BLANK_DE_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_BLANK_DE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_BLANK_DE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_BLANK_DE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_BLANK_DE_INIT_ENUM NORMAL +#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_BLANK_DE_NORMAL _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_BLANK_DE_INACTIVE _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_BLACK_DATA_SHIFT _MK_SHIFT_CONST(25) +#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_BLACK_DATA_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INSTB_0_BLACK_DATA_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_BLACK_DATA_RANGE 25:25 +#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_BLACK_DATA_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_BLACK_DATA_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_BLACK_DATA_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_BLACK_DATA_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_BLACK_DATA_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_BLACK_DATA_INIT_ENUM NORMAL +#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_BLACK_DATA_NORMAL _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_BLACK_DATA_BLACK _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_TRISTATE_IOS_SHIFT _MK_SHIFT_CONST(24) +#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_TRISTATE_IOS_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INSTB_0_TRISTATE_IOS_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_TRISTATE_IOS_RANGE 24:24 +#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_TRISTATE_IOS_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_TRISTATE_IOS_DEFAULT _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_TRISTATE_IOS_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_TRISTATE_IOS_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_TRISTATE_IOS_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_TRISTATE_IOS_INIT_ENUM TRISTATE +#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_TRISTATE_IOS_ENABLE_PINS _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_TRISTATE_IOS_TRISTATE _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_DRIVE_PWM_OUT_LO_SHIFT _MK_SHIFT_CONST(23) +#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_DRIVE_PWM_OUT_LO_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INSTB_0_DRIVE_PWM_OUT_LO_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_DRIVE_PWM_OUT_LO_RANGE 23:23 +#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_DRIVE_PWM_OUT_LO_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_DRIVE_PWM_OUT_LO_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_DRIVE_PWM_OUT_LO_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_DRIVE_PWM_OUT_LO_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_DRIVE_PWM_OUT_LO_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_DRIVE_PWM_OUT_LO_INIT_ENUM FALSE +#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_DRIVE_PWM_OUT_LO_FALSE _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_DRIVE_PWM_OUT_LO_TRUE _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_PIN_B_SHIFT _MK_SHIFT_CONST(22) +#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_PIN_B_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INSTB_0_PIN_B_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_PIN_B_RANGE 22:22 +#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_PIN_B_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_PIN_B_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_PIN_B_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_PIN_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_PIN_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_PIN_B_INIT_ENUM LOW +#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_PIN_B_LOW _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_PIN_B_HIGH _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_PIN_A_SHIFT _MK_SHIFT_CONST(21) +#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_PIN_A_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INSTB_0_PIN_A_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_PIN_A_RANGE 21:21 +#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_PIN_A_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_PIN_A_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_PIN_A_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_PIN_A_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_PIN_A_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_PIN_A_INIT_ENUM LOW +#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_PIN_A_LOW _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_PIN_A_HIGH _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_SEQUENCE_SHIFT _MK_SHIFT_CONST(19) +#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_SEQUENCE_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INSTB_0_SEQUENCE_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_SEQUENCE_RANGE 19:19 +#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_SEQUENCE_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_SEQUENCE_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_SEQUENCE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_SEQUENCE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_SEQUENCE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_SEQUENCE_INIT_ENUM UP +#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_SEQUENCE_UP _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_SEQUENCE_DOWN _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_LANE_SEQ_SHIFT _MK_SHIFT_CONST(18) +#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_LANE_SEQ_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INSTB_0_LANE_SEQ_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_LANE_SEQ_RANGE 18:18 +#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_LANE_SEQ_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_LANE_SEQ_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_LANE_SEQ_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_LANE_SEQ_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_LANE_SEQ_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_LANE_SEQ_INIT_ENUM STOP +#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_LANE_SEQ_STOP _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_LANE_SEQ_RUN _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_PDPORT_SHIFT _MK_SHIFT_CONST(17) +#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_PDPORT_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INSTB_0_PDPORT_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_PDPORT_RANGE 17:17 +#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_PDPORT_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_PDPORT_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_PDPORT_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_PDPORT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_PDPORT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_PDPORT_INIT_ENUM NO +#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_PDPORT_NO _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_PDPORT_YES _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_PDPLL_SHIFT _MK_SHIFT_CONST(16) +#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_PDPLL_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INSTB_0_PDPLL_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_PDPLL_RANGE 16:16 +#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_PDPLL_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_PDPLL_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_PDPLL_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_PDPLL_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_PDPLL_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_PDPLL_INIT_ENUM NO +#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_PDPLL_NO _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_PDPLL_YES _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_HALT_SHIFT _MK_SHIFT_CONST(15) +#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_HALT_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INSTB_0_HALT_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_HALT_RANGE 15:15 +#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_HALT_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_HALT_DEFAULT _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_HALT_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_HALT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_HALT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_HALT_INIT_ENUM TRUE +#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_HALT_FALSE _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_HALT_TRUE _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_WAIT_UNITS_SHIFT _MK_SHIFT_CONST(12) +#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_WAIT_UNITS_FIELD _MK_FIELD_CONST(0x3, SOR_NV_PDISP_SOR_SEQ_INSTB_0_WAIT_UNITS_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_WAIT_UNITS_RANGE 13:12 +#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_WAIT_UNITS_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_WAIT_UNITS_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_WAIT_UNITS_DEFAULT_MASK _MK_MASK_CONST(0x3) +#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_WAIT_UNITS_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_WAIT_UNITS_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_WAIT_UNITS_INIT_ENUM US +#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_WAIT_UNITS_US _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_WAIT_UNITS_MS _MK_ENUM_CONST(1) +#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_WAIT_UNITS_VSYNC _MK_ENUM_CONST(2) + +#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_WAIT_TIME_SHIFT _MK_SHIFT_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_WAIT_TIME_FIELD _MK_FIELD_CONST(0x3ff, SOR_NV_PDISP_SOR_SEQ_INSTB_0_WAIT_TIME_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_WAIT_TIME_RANGE 9:0 +#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_WAIT_TIME_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_WAIT_TIME_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_WAIT_TIME_DEFAULT_MASK _MK_MASK_CONST(0x3ff) +#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_WAIT_TIME_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTB_0_WAIT_TIME_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register SOR_NV_PDISP_SOR_SEQ_INSTC_0 +#define SOR_NV_PDISP_SOR_SEQ_INSTC_0 _MK_ADDR_CONST(0x2e) +#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_SECURE 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_WORD_COUNT 0x1 +#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_RESET_VAL _MK_MASK_CONST(0x1008000) +#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_RESET_MASK _MK_MASK_CONST(0xffefb3ff) +#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_READ_MASK _MK_MASK_CONST(0xffefb3ff) +#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_WRITE_MASK _MK_MASK_CONST(0xffefb3ff) +#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_PLL_PULLDOWN_SHIFT _MK_SHIFT_CONST(31) +#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_PLL_PULLDOWN_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INSTC_0_PLL_PULLDOWN_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_PLL_PULLDOWN_RANGE 31:31 +#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_PLL_PULLDOWN_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_PLL_PULLDOWN_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_PLL_PULLDOWN_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_PLL_PULLDOWN_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_PLL_PULLDOWN_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_PLL_PULLDOWN_INIT_ENUM DISABLE +#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_PLL_PULLDOWN_DISABLE _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_PLL_PULLDOWN_ENABLE _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_POWERDOWN_MACRO_SHIFT _MK_SHIFT_CONST(30) +#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_POWERDOWN_MACRO_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INSTC_0_POWERDOWN_MACRO_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_POWERDOWN_MACRO_RANGE 30:30 +#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_POWERDOWN_MACRO_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_POWERDOWN_MACRO_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_POWERDOWN_MACRO_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_POWERDOWN_MACRO_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_POWERDOWN_MACRO_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_POWERDOWN_MACRO_INIT_ENUM NORMAL +#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_POWERDOWN_MACRO_NORMAL _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_POWERDOWN_MACRO_POWERDOWN _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_ASSERT_PLL_RESET_SHIFT _MK_SHIFT_CONST(29) +#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_ASSERT_PLL_RESET_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INSTC_0_ASSERT_PLL_RESET_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_ASSERT_PLL_RESET_RANGE 29:29 +#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_ASSERT_PLL_RESET_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_ASSERT_PLL_RESET_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_ASSERT_PLL_RESET_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_ASSERT_PLL_RESET_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_ASSERT_PLL_RESET_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_ASSERT_PLL_RESET_INIT_ENUM NORMAL +#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_ASSERT_PLL_RESET_NORMAL _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_ASSERT_PLL_RESET_RST _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_BLANK_V_SHIFT _MK_SHIFT_CONST(28) +#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_BLANK_V_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INSTC_0_BLANK_V_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_BLANK_V_RANGE 28:28 +#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_BLANK_V_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_BLANK_V_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_BLANK_V_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_BLANK_V_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_BLANK_V_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_BLANK_V_INIT_ENUM NORMAL +#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_BLANK_V_NORMAL _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_BLANK_V_INACTIVE _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_BLANK_H_SHIFT _MK_SHIFT_CONST(27) +#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_BLANK_H_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INSTC_0_BLANK_H_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_BLANK_H_RANGE 27:27 +#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_BLANK_H_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_BLANK_H_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_BLANK_H_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_BLANK_H_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_BLANK_H_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_BLANK_H_INIT_ENUM NORMAL +#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_BLANK_H_NORMAL _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_BLANK_H_INACTIVE _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_BLANK_DE_SHIFT _MK_SHIFT_CONST(26) +#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_BLANK_DE_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INSTC_0_BLANK_DE_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_BLANK_DE_RANGE 26:26 +#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_BLANK_DE_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_BLANK_DE_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_BLANK_DE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_BLANK_DE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_BLANK_DE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_BLANK_DE_INIT_ENUM NORMAL +#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_BLANK_DE_NORMAL _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_BLANK_DE_INACTIVE _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_BLACK_DATA_SHIFT _MK_SHIFT_CONST(25) +#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_BLACK_DATA_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INSTC_0_BLACK_DATA_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_BLACK_DATA_RANGE 25:25 +#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_BLACK_DATA_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_BLACK_DATA_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_BLACK_DATA_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_BLACK_DATA_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_BLACK_DATA_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_BLACK_DATA_INIT_ENUM NORMAL +#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_BLACK_DATA_NORMAL _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_BLACK_DATA_BLACK _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_TRISTATE_IOS_SHIFT _MK_SHIFT_CONST(24) +#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_TRISTATE_IOS_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INSTC_0_TRISTATE_IOS_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_TRISTATE_IOS_RANGE 24:24 +#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_TRISTATE_IOS_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_TRISTATE_IOS_DEFAULT _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_TRISTATE_IOS_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_TRISTATE_IOS_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_TRISTATE_IOS_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_TRISTATE_IOS_INIT_ENUM TRISTATE +#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_TRISTATE_IOS_ENABLE_PINS _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_TRISTATE_IOS_TRISTATE _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_DRIVE_PWM_OUT_LO_SHIFT _MK_SHIFT_CONST(23) +#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_DRIVE_PWM_OUT_LO_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INSTC_0_DRIVE_PWM_OUT_LO_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_DRIVE_PWM_OUT_LO_RANGE 23:23 +#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_DRIVE_PWM_OUT_LO_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_DRIVE_PWM_OUT_LO_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_DRIVE_PWM_OUT_LO_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_DRIVE_PWM_OUT_LO_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_DRIVE_PWM_OUT_LO_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_DRIVE_PWM_OUT_LO_INIT_ENUM FALSE +#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_DRIVE_PWM_OUT_LO_FALSE _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_DRIVE_PWM_OUT_LO_TRUE _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_PIN_B_SHIFT _MK_SHIFT_CONST(22) +#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_PIN_B_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INSTC_0_PIN_B_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_PIN_B_RANGE 22:22 +#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_PIN_B_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_PIN_B_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_PIN_B_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_PIN_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_PIN_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_PIN_B_INIT_ENUM LOW +#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_PIN_B_LOW _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_PIN_B_HIGH _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_PIN_A_SHIFT _MK_SHIFT_CONST(21) +#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_PIN_A_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INSTC_0_PIN_A_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_PIN_A_RANGE 21:21 +#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_PIN_A_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_PIN_A_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_PIN_A_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_PIN_A_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_PIN_A_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_PIN_A_INIT_ENUM LOW +#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_PIN_A_LOW _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_PIN_A_HIGH _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_SEQUENCE_SHIFT _MK_SHIFT_CONST(19) +#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_SEQUENCE_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INSTC_0_SEQUENCE_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_SEQUENCE_RANGE 19:19 +#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_SEQUENCE_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_SEQUENCE_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_SEQUENCE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_SEQUENCE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_SEQUENCE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_SEQUENCE_INIT_ENUM UP +#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_SEQUENCE_UP _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_SEQUENCE_DOWN _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_LANE_SEQ_SHIFT _MK_SHIFT_CONST(18) +#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_LANE_SEQ_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INSTC_0_LANE_SEQ_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_LANE_SEQ_RANGE 18:18 +#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_LANE_SEQ_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_LANE_SEQ_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_LANE_SEQ_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_LANE_SEQ_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_LANE_SEQ_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_LANE_SEQ_INIT_ENUM STOP +#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_LANE_SEQ_STOP _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_LANE_SEQ_RUN _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_PDPORT_SHIFT _MK_SHIFT_CONST(17) +#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_PDPORT_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INSTC_0_PDPORT_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_PDPORT_RANGE 17:17 +#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_PDPORT_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_PDPORT_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_PDPORT_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_PDPORT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_PDPORT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_PDPORT_INIT_ENUM NO +#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_PDPORT_NO _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_PDPORT_YES _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_PDPLL_SHIFT _MK_SHIFT_CONST(16) +#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_PDPLL_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INSTC_0_PDPLL_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_PDPLL_RANGE 16:16 +#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_PDPLL_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_PDPLL_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_PDPLL_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_PDPLL_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_PDPLL_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_PDPLL_INIT_ENUM NO +#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_PDPLL_NO _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_PDPLL_YES _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_HALT_SHIFT _MK_SHIFT_CONST(15) +#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_HALT_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INSTC_0_HALT_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_HALT_RANGE 15:15 +#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_HALT_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_HALT_DEFAULT _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_HALT_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_HALT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_HALT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_HALT_INIT_ENUM TRUE +#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_HALT_FALSE _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_HALT_TRUE _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_WAIT_UNITS_SHIFT _MK_SHIFT_CONST(12) +#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_WAIT_UNITS_FIELD _MK_FIELD_CONST(0x3, SOR_NV_PDISP_SOR_SEQ_INSTC_0_WAIT_UNITS_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_WAIT_UNITS_RANGE 13:12 +#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_WAIT_UNITS_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_WAIT_UNITS_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_WAIT_UNITS_DEFAULT_MASK _MK_MASK_CONST(0x3) +#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_WAIT_UNITS_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_WAIT_UNITS_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_WAIT_UNITS_INIT_ENUM US +#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_WAIT_UNITS_US _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_WAIT_UNITS_MS _MK_ENUM_CONST(1) +#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_WAIT_UNITS_VSYNC _MK_ENUM_CONST(2) + +#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_WAIT_TIME_SHIFT _MK_SHIFT_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_WAIT_TIME_FIELD _MK_FIELD_CONST(0x3ff, SOR_NV_PDISP_SOR_SEQ_INSTC_0_WAIT_TIME_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_WAIT_TIME_RANGE 9:0 +#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_WAIT_TIME_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_WAIT_TIME_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_WAIT_TIME_DEFAULT_MASK _MK_MASK_CONST(0x3ff) +#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_WAIT_TIME_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTC_0_WAIT_TIME_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register SOR_NV_PDISP_SOR_SEQ_INSTD_0 +#define SOR_NV_PDISP_SOR_SEQ_INSTD_0 _MK_ADDR_CONST(0x2f) +#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_SECURE 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_WORD_COUNT 0x1 +#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_RESET_VAL _MK_MASK_CONST(0x1008000) +#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_RESET_MASK _MK_MASK_CONST(0xffefb3ff) +#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_READ_MASK _MK_MASK_CONST(0xffefb3ff) +#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_WRITE_MASK _MK_MASK_CONST(0xffefb3ff) +#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_PLL_PULLDOWN_SHIFT _MK_SHIFT_CONST(31) +#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_PLL_PULLDOWN_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INSTD_0_PLL_PULLDOWN_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_PLL_PULLDOWN_RANGE 31:31 +#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_PLL_PULLDOWN_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_PLL_PULLDOWN_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_PLL_PULLDOWN_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_PLL_PULLDOWN_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_PLL_PULLDOWN_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_PLL_PULLDOWN_INIT_ENUM DISABLE +#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_PLL_PULLDOWN_DISABLE _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_PLL_PULLDOWN_ENABLE _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_POWERDOWN_MACRO_SHIFT _MK_SHIFT_CONST(30) +#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_POWERDOWN_MACRO_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INSTD_0_POWERDOWN_MACRO_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_POWERDOWN_MACRO_RANGE 30:30 +#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_POWERDOWN_MACRO_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_POWERDOWN_MACRO_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_POWERDOWN_MACRO_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_POWERDOWN_MACRO_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_POWERDOWN_MACRO_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_POWERDOWN_MACRO_INIT_ENUM NORMAL +#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_POWERDOWN_MACRO_NORMAL _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_POWERDOWN_MACRO_POWERDOWN _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_ASSERT_PLL_RESET_SHIFT _MK_SHIFT_CONST(29) +#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_ASSERT_PLL_RESET_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INSTD_0_ASSERT_PLL_RESET_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_ASSERT_PLL_RESET_RANGE 29:29 +#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_ASSERT_PLL_RESET_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_ASSERT_PLL_RESET_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_ASSERT_PLL_RESET_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_ASSERT_PLL_RESET_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_ASSERT_PLL_RESET_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_ASSERT_PLL_RESET_INIT_ENUM NORMAL +#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_ASSERT_PLL_RESET_NORMAL _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_ASSERT_PLL_RESET_RST _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_BLANK_V_SHIFT _MK_SHIFT_CONST(28) +#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_BLANK_V_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INSTD_0_BLANK_V_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_BLANK_V_RANGE 28:28 +#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_BLANK_V_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_BLANK_V_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_BLANK_V_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_BLANK_V_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_BLANK_V_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_BLANK_V_INIT_ENUM NORMAL +#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_BLANK_V_NORMAL _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_BLANK_V_INACTIVE _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_BLANK_H_SHIFT _MK_SHIFT_CONST(27) +#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_BLANK_H_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INSTD_0_BLANK_H_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_BLANK_H_RANGE 27:27 +#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_BLANK_H_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_BLANK_H_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_BLANK_H_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_BLANK_H_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_BLANK_H_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_BLANK_H_INIT_ENUM NORMAL +#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_BLANK_H_NORMAL _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_BLANK_H_INACTIVE _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_BLANK_DE_SHIFT _MK_SHIFT_CONST(26) +#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_BLANK_DE_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INSTD_0_BLANK_DE_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_BLANK_DE_RANGE 26:26 +#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_BLANK_DE_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_BLANK_DE_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_BLANK_DE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_BLANK_DE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_BLANK_DE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_BLANK_DE_INIT_ENUM NORMAL +#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_BLANK_DE_NORMAL _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_BLANK_DE_INACTIVE _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_BLACK_DATA_SHIFT _MK_SHIFT_CONST(25) +#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_BLACK_DATA_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INSTD_0_BLACK_DATA_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_BLACK_DATA_RANGE 25:25 +#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_BLACK_DATA_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_BLACK_DATA_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_BLACK_DATA_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_BLACK_DATA_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_BLACK_DATA_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_BLACK_DATA_INIT_ENUM NORMAL +#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_BLACK_DATA_NORMAL _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_BLACK_DATA_BLACK _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_TRISTATE_IOS_SHIFT _MK_SHIFT_CONST(24) +#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_TRISTATE_IOS_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INSTD_0_TRISTATE_IOS_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_TRISTATE_IOS_RANGE 24:24 +#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_TRISTATE_IOS_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_TRISTATE_IOS_DEFAULT _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_TRISTATE_IOS_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_TRISTATE_IOS_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_TRISTATE_IOS_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_TRISTATE_IOS_INIT_ENUM TRISTATE +#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_TRISTATE_IOS_ENABLE_PINS _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_TRISTATE_IOS_TRISTATE _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_DRIVE_PWM_OUT_LO_SHIFT _MK_SHIFT_CONST(23) +#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_DRIVE_PWM_OUT_LO_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INSTD_0_DRIVE_PWM_OUT_LO_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_DRIVE_PWM_OUT_LO_RANGE 23:23 +#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_DRIVE_PWM_OUT_LO_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_DRIVE_PWM_OUT_LO_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_DRIVE_PWM_OUT_LO_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_DRIVE_PWM_OUT_LO_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_DRIVE_PWM_OUT_LO_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_DRIVE_PWM_OUT_LO_INIT_ENUM FALSE +#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_DRIVE_PWM_OUT_LO_FALSE _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_DRIVE_PWM_OUT_LO_TRUE _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_PIN_B_SHIFT _MK_SHIFT_CONST(22) +#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_PIN_B_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INSTD_0_PIN_B_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_PIN_B_RANGE 22:22 +#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_PIN_B_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_PIN_B_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_PIN_B_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_PIN_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_PIN_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_PIN_B_INIT_ENUM LOW +#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_PIN_B_LOW _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_PIN_B_HIGH _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_PIN_A_SHIFT _MK_SHIFT_CONST(21) +#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_PIN_A_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INSTD_0_PIN_A_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_PIN_A_RANGE 21:21 +#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_PIN_A_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_PIN_A_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_PIN_A_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_PIN_A_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_PIN_A_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_PIN_A_INIT_ENUM LOW +#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_PIN_A_LOW _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_PIN_A_HIGH _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_SEQUENCE_SHIFT _MK_SHIFT_CONST(19) +#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_SEQUENCE_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INSTD_0_SEQUENCE_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_SEQUENCE_RANGE 19:19 +#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_SEQUENCE_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_SEQUENCE_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_SEQUENCE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_SEQUENCE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_SEQUENCE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_SEQUENCE_INIT_ENUM UP +#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_SEQUENCE_UP _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_SEQUENCE_DOWN _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_LANE_SEQ_SHIFT _MK_SHIFT_CONST(18) +#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_LANE_SEQ_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INSTD_0_LANE_SEQ_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_LANE_SEQ_RANGE 18:18 +#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_LANE_SEQ_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_LANE_SEQ_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_LANE_SEQ_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_LANE_SEQ_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_LANE_SEQ_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_LANE_SEQ_INIT_ENUM STOP +#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_LANE_SEQ_STOP _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_LANE_SEQ_RUN _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_PDPORT_SHIFT _MK_SHIFT_CONST(17) +#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_PDPORT_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INSTD_0_PDPORT_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_PDPORT_RANGE 17:17 +#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_PDPORT_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_PDPORT_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_PDPORT_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_PDPORT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_PDPORT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_PDPORT_INIT_ENUM NO +#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_PDPORT_NO _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_PDPORT_YES _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_PDPLL_SHIFT _MK_SHIFT_CONST(16) +#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_PDPLL_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INSTD_0_PDPLL_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_PDPLL_RANGE 16:16 +#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_PDPLL_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_PDPLL_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_PDPLL_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_PDPLL_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_PDPLL_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_PDPLL_INIT_ENUM NO +#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_PDPLL_NO _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_PDPLL_YES _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_HALT_SHIFT _MK_SHIFT_CONST(15) +#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_HALT_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INSTD_0_HALT_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_HALT_RANGE 15:15 +#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_HALT_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_HALT_DEFAULT _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_HALT_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_HALT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_HALT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_HALT_INIT_ENUM TRUE +#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_HALT_FALSE _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_HALT_TRUE _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_WAIT_UNITS_SHIFT _MK_SHIFT_CONST(12) +#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_WAIT_UNITS_FIELD _MK_FIELD_CONST(0x3, SOR_NV_PDISP_SOR_SEQ_INSTD_0_WAIT_UNITS_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_WAIT_UNITS_RANGE 13:12 +#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_WAIT_UNITS_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_WAIT_UNITS_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_WAIT_UNITS_DEFAULT_MASK _MK_MASK_CONST(0x3) +#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_WAIT_UNITS_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_WAIT_UNITS_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_WAIT_UNITS_INIT_ENUM US +#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_WAIT_UNITS_US _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_WAIT_UNITS_MS _MK_ENUM_CONST(1) +#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_WAIT_UNITS_VSYNC _MK_ENUM_CONST(2) + +#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_WAIT_TIME_SHIFT _MK_SHIFT_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_WAIT_TIME_FIELD _MK_FIELD_CONST(0x3ff, SOR_NV_PDISP_SOR_SEQ_INSTD_0_WAIT_TIME_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_WAIT_TIME_RANGE 9:0 +#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_WAIT_TIME_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_WAIT_TIME_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_WAIT_TIME_DEFAULT_MASK _MK_MASK_CONST(0x3ff) +#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_WAIT_TIME_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTD_0_WAIT_TIME_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register SOR_NV_PDISP_SOR_SEQ_INSTE_0 +#define SOR_NV_PDISP_SOR_SEQ_INSTE_0 _MK_ADDR_CONST(0x30) +#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_SECURE 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_WORD_COUNT 0x1 +#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_RESET_VAL _MK_MASK_CONST(0x1008000) +#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_RESET_MASK _MK_MASK_CONST(0xffefb3ff) +#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_READ_MASK _MK_MASK_CONST(0xffefb3ff) +#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_WRITE_MASK _MK_MASK_CONST(0xffefb3ff) +#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_PLL_PULLDOWN_SHIFT _MK_SHIFT_CONST(31) +#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_PLL_PULLDOWN_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INSTE_0_PLL_PULLDOWN_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_PLL_PULLDOWN_RANGE 31:31 +#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_PLL_PULLDOWN_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_PLL_PULLDOWN_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_PLL_PULLDOWN_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_PLL_PULLDOWN_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_PLL_PULLDOWN_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_PLL_PULLDOWN_INIT_ENUM DISABLE +#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_PLL_PULLDOWN_DISABLE _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_PLL_PULLDOWN_ENABLE _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_POWERDOWN_MACRO_SHIFT _MK_SHIFT_CONST(30) +#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_POWERDOWN_MACRO_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INSTE_0_POWERDOWN_MACRO_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_POWERDOWN_MACRO_RANGE 30:30 +#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_POWERDOWN_MACRO_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_POWERDOWN_MACRO_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_POWERDOWN_MACRO_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_POWERDOWN_MACRO_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_POWERDOWN_MACRO_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_POWERDOWN_MACRO_INIT_ENUM NORMAL +#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_POWERDOWN_MACRO_NORMAL _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_POWERDOWN_MACRO_POWERDOWN _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_ASSERT_PLL_RESET_SHIFT _MK_SHIFT_CONST(29) +#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_ASSERT_PLL_RESET_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INSTE_0_ASSERT_PLL_RESET_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_ASSERT_PLL_RESET_RANGE 29:29 +#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_ASSERT_PLL_RESET_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_ASSERT_PLL_RESET_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_ASSERT_PLL_RESET_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_ASSERT_PLL_RESET_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_ASSERT_PLL_RESET_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_ASSERT_PLL_RESET_INIT_ENUM NORMAL +#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_ASSERT_PLL_RESET_NORMAL _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_ASSERT_PLL_RESET_RST _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_BLANK_V_SHIFT _MK_SHIFT_CONST(28) +#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_BLANK_V_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INSTE_0_BLANK_V_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_BLANK_V_RANGE 28:28 +#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_BLANK_V_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_BLANK_V_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_BLANK_V_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_BLANK_V_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_BLANK_V_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_BLANK_V_INIT_ENUM NORMAL +#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_BLANK_V_NORMAL _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_BLANK_V_INACTIVE _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_BLANK_H_SHIFT _MK_SHIFT_CONST(27) +#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_BLANK_H_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INSTE_0_BLANK_H_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_BLANK_H_RANGE 27:27 +#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_BLANK_H_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_BLANK_H_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_BLANK_H_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_BLANK_H_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_BLANK_H_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_BLANK_H_INIT_ENUM NORMAL +#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_BLANK_H_NORMAL _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_BLANK_H_INACTIVE _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_BLANK_DE_SHIFT _MK_SHIFT_CONST(26) +#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_BLANK_DE_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INSTE_0_BLANK_DE_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_BLANK_DE_RANGE 26:26 +#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_BLANK_DE_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_BLANK_DE_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_BLANK_DE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_BLANK_DE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_BLANK_DE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_BLANK_DE_INIT_ENUM NORMAL +#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_BLANK_DE_NORMAL _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_BLANK_DE_INACTIVE _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_BLACK_DATA_SHIFT _MK_SHIFT_CONST(25) +#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_BLACK_DATA_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INSTE_0_BLACK_DATA_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_BLACK_DATA_RANGE 25:25 +#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_BLACK_DATA_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_BLACK_DATA_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_BLACK_DATA_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_BLACK_DATA_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_BLACK_DATA_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_BLACK_DATA_INIT_ENUM NORMAL +#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_BLACK_DATA_NORMAL _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_BLACK_DATA_BLACK _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_TRISTATE_IOS_SHIFT _MK_SHIFT_CONST(24) +#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_TRISTATE_IOS_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INSTE_0_TRISTATE_IOS_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_TRISTATE_IOS_RANGE 24:24 +#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_TRISTATE_IOS_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_TRISTATE_IOS_DEFAULT _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_TRISTATE_IOS_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_TRISTATE_IOS_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_TRISTATE_IOS_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_TRISTATE_IOS_INIT_ENUM TRISTATE +#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_TRISTATE_IOS_ENABLE_PINS _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_TRISTATE_IOS_TRISTATE _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_DRIVE_PWM_OUT_LO_SHIFT _MK_SHIFT_CONST(23) +#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_DRIVE_PWM_OUT_LO_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INSTE_0_DRIVE_PWM_OUT_LO_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_DRIVE_PWM_OUT_LO_RANGE 23:23 +#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_DRIVE_PWM_OUT_LO_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_DRIVE_PWM_OUT_LO_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_DRIVE_PWM_OUT_LO_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_DRIVE_PWM_OUT_LO_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_DRIVE_PWM_OUT_LO_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_DRIVE_PWM_OUT_LO_INIT_ENUM FALSE +#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_DRIVE_PWM_OUT_LO_FALSE _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_DRIVE_PWM_OUT_LO_TRUE _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_PIN_B_SHIFT _MK_SHIFT_CONST(22) +#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_PIN_B_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INSTE_0_PIN_B_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_PIN_B_RANGE 22:22 +#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_PIN_B_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_PIN_B_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_PIN_B_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_PIN_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_PIN_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_PIN_B_INIT_ENUM LOW +#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_PIN_B_LOW _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_PIN_B_HIGH _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_PIN_A_SHIFT _MK_SHIFT_CONST(21) +#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_PIN_A_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INSTE_0_PIN_A_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_PIN_A_RANGE 21:21 +#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_PIN_A_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_PIN_A_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_PIN_A_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_PIN_A_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_PIN_A_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_PIN_A_INIT_ENUM LOW +#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_PIN_A_LOW _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_PIN_A_HIGH _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_SEQUENCE_SHIFT _MK_SHIFT_CONST(19) +#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_SEQUENCE_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INSTE_0_SEQUENCE_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_SEQUENCE_RANGE 19:19 +#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_SEQUENCE_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_SEQUENCE_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_SEQUENCE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_SEQUENCE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_SEQUENCE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_SEQUENCE_INIT_ENUM UP +#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_SEQUENCE_UP _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_SEQUENCE_DOWN _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_LANE_SEQ_SHIFT _MK_SHIFT_CONST(18) +#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_LANE_SEQ_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INSTE_0_LANE_SEQ_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_LANE_SEQ_RANGE 18:18 +#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_LANE_SEQ_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_LANE_SEQ_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_LANE_SEQ_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_LANE_SEQ_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_LANE_SEQ_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_LANE_SEQ_INIT_ENUM STOP +#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_LANE_SEQ_STOP _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_LANE_SEQ_RUN _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_PDPORT_SHIFT _MK_SHIFT_CONST(17) +#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_PDPORT_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INSTE_0_PDPORT_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_PDPORT_RANGE 17:17 +#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_PDPORT_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_PDPORT_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_PDPORT_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_PDPORT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_PDPORT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_PDPORT_INIT_ENUM NO +#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_PDPORT_NO _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_PDPORT_YES _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_PDPLL_SHIFT _MK_SHIFT_CONST(16) +#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_PDPLL_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INSTE_0_PDPLL_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_PDPLL_RANGE 16:16 +#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_PDPLL_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_PDPLL_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_PDPLL_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_PDPLL_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_PDPLL_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_PDPLL_INIT_ENUM NO +#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_PDPLL_NO _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_PDPLL_YES _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_HALT_SHIFT _MK_SHIFT_CONST(15) +#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_HALT_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INSTE_0_HALT_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_HALT_RANGE 15:15 +#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_HALT_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_HALT_DEFAULT _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_HALT_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_HALT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_HALT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_HALT_INIT_ENUM TRUE +#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_HALT_FALSE _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_HALT_TRUE _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_WAIT_UNITS_SHIFT _MK_SHIFT_CONST(12) +#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_WAIT_UNITS_FIELD _MK_FIELD_CONST(0x3, SOR_NV_PDISP_SOR_SEQ_INSTE_0_WAIT_UNITS_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_WAIT_UNITS_RANGE 13:12 +#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_WAIT_UNITS_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_WAIT_UNITS_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_WAIT_UNITS_DEFAULT_MASK _MK_MASK_CONST(0x3) +#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_WAIT_UNITS_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_WAIT_UNITS_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_WAIT_UNITS_INIT_ENUM US +#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_WAIT_UNITS_US _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_WAIT_UNITS_MS _MK_ENUM_CONST(1) +#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_WAIT_UNITS_VSYNC _MK_ENUM_CONST(2) + +#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_WAIT_TIME_SHIFT _MK_SHIFT_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_WAIT_TIME_FIELD _MK_FIELD_CONST(0x3ff, SOR_NV_PDISP_SOR_SEQ_INSTE_0_WAIT_TIME_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_WAIT_TIME_RANGE 9:0 +#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_WAIT_TIME_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_WAIT_TIME_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_WAIT_TIME_DEFAULT_MASK _MK_MASK_CONST(0x3ff) +#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_WAIT_TIME_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTE_0_WAIT_TIME_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register SOR_NV_PDISP_SOR_SEQ_INSTF_0 +#define SOR_NV_PDISP_SOR_SEQ_INSTF_0 _MK_ADDR_CONST(0x31) +#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_SECURE 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_WORD_COUNT 0x1 +#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_RESET_VAL _MK_MASK_CONST(0x1008000) +#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_RESET_MASK _MK_MASK_CONST(0xffefb3ff) +#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_READ_MASK _MK_MASK_CONST(0xffefb3ff) +#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_WRITE_MASK _MK_MASK_CONST(0xffefb3ff) +#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_PLL_PULLDOWN_SHIFT _MK_SHIFT_CONST(31) +#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_PLL_PULLDOWN_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INSTF_0_PLL_PULLDOWN_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_PLL_PULLDOWN_RANGE 31:31 +#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_PLL_PULLDOWN_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_PLL_PULLDOWN_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_PLL_PULLDOWN_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_PLL_PULLDOWN_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_PLL_PULLDOWN_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_PLL_PULLDOWN_INIT_ENUM DISABLE +#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_PLL_PULLDOWN_DISABLE _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_PLL_PULLDOWN_ENABLE _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_POWERDOWN_MACRO_SHIFT _MK_SHIFT_CONST(30) +#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_POWERDOWN_MACRO_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INSTF_0_POWERDOWN_MACRO_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_POWERDOWN_MACRO_RANGE 30:30 +#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_POWERDOWN_MACRO_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_POWERDOWN_MACRO_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_POWERDOWN_MACRO_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_POWERDOWN_MACRO_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_POWERDOWN_MACRO_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_POWERDOWN_MACRO_INIT_ENUM NORMAL +#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_POWERDOWN_MACRO_NORMAL _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_POWERDOWN_MACRO_POWERDOWN _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_ASSERT_PLL_RESET_SHIFT _MK_SHIFT_CONST(29) +#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_ASSERT_PLL_RESET_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INSTF_0_ASSERT_PLL_RESET_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_ASSERT_PLL_RESET_RANGE 29:29 +#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_ASSERT_PLL_RESET_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_ASSERT_PLL_RESET_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_ASSERT_PLL_RESET_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_ASSERT_PLL_RESET_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_ASSERT_PLL_RESET_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_ASSERT_PLL_RESET_INIT_ENUM NORMAL +#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_ASSERT_PLL_RESET_NORMAL _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_ASSERT_PLL_RESET_RST _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_BLANK_V_SHIFT _MK_SHIFT_CONST(28) +#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_BLANK_V_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INSTF_0_BLANK_V_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_BLANK_V_RANGE 28:28 +#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_BLANK_V_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_BLANK_V_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_BLANK_V_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_BLANK_V_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_BLANK_V_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_BLANK_V_INIT_ENUM NORMAL +#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_BLANK_V_NORMAL _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_BLANK_V_INACTIVE _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_BLANK_H_SHIFT _MK_SHIFT_CONST(27) +#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_BLANK_H_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INSTF_0_BLANK_H_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_BLANK_H_RANGE 27:27 +#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_BLANK_H_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_BLANK_H_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_BLANK_H_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_BLANK_H_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_BLANK_H_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_BLANK_H_INIT_ENUM NORMAL +#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_BLANK_H_NORMAL _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_BLANK_H_INACTIVE _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_BLANK_DE_SHIFT _MK_SHIFT_CONST(26) +#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_BLANK_DE_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INSTF_0_BLANK_DE_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_BLANK_DE_RANGE 26:26 +#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_BLANK_DE_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_BLANK_DE_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_BLANK_DE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_BLANK_DE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_BLANK_DE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_BLANK_DE_INIT_ENUM NORMAL +#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_BLANK_DE_NORMAL _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_BLANK_DE_INACTIVE _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_BLACK_DATA_SHIFT _MK_SHIFT_CONST(25) +#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_BLACK_DATA_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INSTF_0_BLACK_DATA_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_BLACK_DATA_RANGE 25:25 +#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_BLACK_DATA_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_BLACK_DATA_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_BLACK_DATA_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_BLACK_DATA_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_BLACK_DATA_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_BLACK_DATA_INIT_ENUM NORMAL +#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_BLACK_DATA_NORMAL _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_BLACK_DATA_BLACK _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_TRISTATE_IOS_SHIFT _MK_SHIFT_CONST(24) +#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_TRISTATE_IOS_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INSTF_0_TRISTATE_IOS_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_TRISTATE_IOS_RANGE 24:24 +#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_TRISTATE_IOS_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_TRISTATE_IOS_DEFAULT _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_TRISTATE_IOS_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_TRISTATE_IOS_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_TRISTATE_IOS_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_TRISTATE_IOS_INIT_ENUM TRISTATE +#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_TRISTATE_IOS_ENABLE_PINS _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_TRISTATE_IOS_TRISTATE _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_DRIVE_PWM_OUT_LO_SHIFT _MK_SHIFT_CONST(23) +#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_DRIVE_PWM_OUT_LO_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INSTF_0_DRIVE_PWM_OUT_LO_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_DRIVE_PWM_OUT_LO_RANGE 23:23 +#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_DRIVE_PWM_OUT_LO_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_DRIVE_PWM_OUT_LO_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_DRIVE_PWM_OUT_LO_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_DRIVE_PWM_OUT_LO_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_DRIVE_PWM_OUT_LO_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_DRIVE_PWM_OUT_LO_INIT_ENUM FALSE +#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_DRIVE_PWM_OUT_LO_FALSE _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_DRIVE_PWM_OUT_LO_TRUE _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_PIN_B_SHIFT _MK_SHIFT_CONST(22) +#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_PIN_B_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INSTF_0_PIN_B_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_PIN_B_RANGE 22:22 +#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_PIN_B_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_PIN_B_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_PIN_B_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_PIN_B_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_PIN_B_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_PIN_B_INIT_ENUM LOW +#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_PIN_B_LOW _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_PIN_B_HIGH _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_PIN_A_SHIFT _MK_SHIFT_CONST(21) +#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_PIN_A_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INSTF_0_PIN_A_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_PIN_A_RANGE 21:21 +#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_PIN_A_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_PIN_A_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_PIN_A_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_PIN_A_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_PIN_A_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_PIN_A_INIT_ENUM LOW +#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_PIN_A_LOW _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_PIN_A_HIGH _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_SEQUENCE_SHIFT _MK_SHIFT_CONST(19) +#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_SEQUENCE_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INSTF_0_SEQUENCE_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_SEQUENCE_RANGE 19:19 +#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_SEQUENCE_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_SEQUENCE_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_SEQUENCE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_SEQUENCE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_SEQUENCE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_SEQUENCE_INIT_ENUM UP +#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_SEQUENCE_UP _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_SEQUENCE_DOWN _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_LANE_SEQ_SHIFT _MK_SHIFT_CONST(18) +#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_LANE_SEQ_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INSTF_0_LANE_SEQ_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_LANE_SEQ_RANGE 18:18 +#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_LANE_SEQ_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_LANE_SEQ_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_LANE_SEQ_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_LANE_SEQ_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_LANE_SEQ_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_LANE_SEQ_INIT_ENUM STOP +#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_LANE_SEQ_STOP _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_LANE_SEQ_RUN _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_PDPORT_SHIFT _MK_SHIFT_CONST(17) +#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_PDPORT_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INSTF_0_PDPORT_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_PDPORT_RANGE 17:17 +#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_PDPORT_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_PDPORT_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_PDPORT_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_PDPORT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_PDPORT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_PDPORT_INIT_ENUM NO +#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_PDPORT_NO _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_PDPORT_YES _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_PDPLL_SHIFT _MK_SHIFT_CONST(16) +#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_PDPLL_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INSTF_0_PDPLL_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_PDPLL_RANGE 16:16 +#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_PDPLL_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_PDPLL_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_PDPLL_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_PDPLL_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_PDPLL_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_PDPLL_INIT_ENUM NO +#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_PDPLL_NO _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_PDPLL_YES _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_HALT_SHIFT _MK_SHIFT_CONST(15) +#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_HALT_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_SEQ_INSTF_0_HALT_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_HALT_RANGE 15:15 +#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_HALT_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_HALT_DEFAULT _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_HALT_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_HALT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_HALT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_HALT_INIT_ENUM TRUE +#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_HALT_FALSE _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_HALT_TRUE _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_WAIT_UNITS_SHIFT _MK_SHIFT_CONST(12) +#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_WAIT_UNITS_FIELD _MK_FIELD_CONST(0x3, SOR_NV_PDISP_SOR_SEQ_INSTF_0_WAIT_UNITS_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_WAIT_UNITS_RANGE 13:12 +#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_WAIT_UNITS_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_WAIT_UNITS_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_WAIT_UNITS_DEFAULT_MASK _MK_MASK_CONST(0x3) +#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_WAIT_UNITS_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_WAIT_UNITS_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_WAIT_UNITS_INIT_ENUM US +#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_WAIT_UNITS_US _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_WAIT_UNITS_MS _MK_ENUM_CONST(1) +#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_WAIT_UNITS_VSYNC _MK_ENUM_CONST(2) + +#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_WAIT_TIME_SHIFT _MK_SHIFT_CONST(0) +#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_WAIT_TIME_FIELD _MK_FIELD_CONST(0x3ff, SOR_NV_PDISP_SOR_SEQ_INSTF_0_WAIT_TIME_SHIFT) +#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_WAIT_TIME_RANGE 9:0 +#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_WAIT_TIME_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_WAIT_TIME_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_WAIT_TIME_DEFAULT_MASK _MK_MASK_CONST(0x3ff) +#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_WAIT_TIME_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_SEQ_INSTF_0_WAIT_TIME_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register SOR_NV_PDISP_SOR_PWM_DIV_0 +#define SOR_NV_PDISP_SOR_PWM_DIV_0 _MK_ADDR_CONST(0x32) +#define SOR_NV_PDISP_SOR_PWM_DIV_0_SECURE 0x0 +#define SOR_NV_PDISP_SOR_PWM_DIV_0_WORD_COUNT 0x1 +#define SOR_NV_PDISP_SOR_PWM_DIV_0_RESET_VAL _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_PWM_DIV_0_RESET_MASK _MK_MASK_CONST(0xffffff) +#define SOR_NV_PDISP_SOR_PWM_DIV_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_PWM_DIV_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_PWM_DIV_0_READ_MASK _MK_MASK_CONST(0xffffff) +#define SOR_NV_PDISP_SOR_PWM_DIV_0_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define SOR_NV_PDISP_SOR_PWM_DIV_0_DIVIDE_SHIFT _MK_SHIFT_CONST(0) +#define SOR_NV_PDISP_SOR_PWM_DIV_0_DIVIDE_FIELD _MK_FIELD_CONST(0xffffff, SOR_NV_PDISP_SOR_PWM_DIV_0_DIVIDE_SHIFT) +#define SOR_NV_PDISP_SOR_PWM_DIV_0_DIVIDE_RANGE 23:0 +#define SOR_NV_PDISP_SOR_PWM_DIV_0_DIVIDE_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_PWM_DIV_0_DIVIDE_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_PWM_DIV_0_DIVIDE_DEFAULT_MASK _MK_MASK_CONST(0xffffff) +#define SOR_NV_PDISP_SOR_PWM_DIV_0_DIVIDE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_PWM_DIV_0_DIVIDE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register SOR_NV_PDISP_SOR_PWM_CTL_0 +#define SOR_NV_PDISP_SOR_PWM_CTL_0 _MK_ADDR_CONST(0x33) +#define SOR_NV_PDISP_SOR_PWM_CTL_0_SECURE 0x0 +#define SOR_NV_PDISP_SOR_PWM_CTL_0_WORD_COUNT 0x1 +#define SOR_NV_PDISP_SOR_PWM_CTL_0_RESET_VAL _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_PWM_CTL_0_RESET_MASK _MK_MASK_CONST(0xc0ffffff) +#define SOR_NV_PDISP_SOR_PWM_CTL_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_PWM_CTL_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_PWM_CTL_0_READ_MASK _MK_MASK_CONST(0xc0ffffff) +#define SOR_NV_PDISP_SOR_PWM_CTL_0_WRITE_MASK _MK_MASK_CONST(0xc0ffffff) +#define SOR_NV_PDISP_SOR_PWM_CTL_0_SETTING_NEW_SHIFT _MK_SHIFT_CONST(31) +#define SOR_NV_PDISP_SOR_PWM_CTL_0_SETTING_NEW_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_PWM_CTL_0_SETTING_NEW_SHIFT) +#define SOR_NV_PDISP_SOR_PWM_CTL_0_SETTING_NEW_RANGE 31:31 +#define SOR_NV_PDISP_SOR_PWM_CTL_0_SETTING_NEW_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_PWM_CTL_0_SETTING_NEW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_PWM_CTL_0_SETTING_NEW_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_PWM_CTL_0_SETTING_NEW_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_PWM_CTL_0_SETTING_NEW_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_PWM_CTL_0_SETTING_NEW_INIT_ENUM DONE +#define SOR_NV_PDISP_SOR_PWM_CTL_0_SETTING_NEW_DONE _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_PWM_CTL_0_SETTING_NEW_PENDING _MK_ENUM_CONST(1) +#define SOR_NV_PDISP_SOR_PWM_CTL_0_SETTING_NEW_TRIGGER _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_PWM_CTL_0_CLKSEL_SHIFT _MK_SHIFT_CONST(30) +#define SOR_NV_PDISP_SOR_PWM_CTL_0_CLKSEL_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_PWM_CTL_0_CLKSEL_SHIFT) +#define SOR_NV_PDISP_SOR_PWM_CTL_0_CLKSEL_RANGE 30:30 +#define SOR_NV_PDISP_SOR_PWM_CTL_0_CLKSEL_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_PWM_CTL_0_CLKSEL_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_PWM_CTL_0_CLKSEL_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_PWM_CTL_0_CLKSEL_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_PWM_CTL_0_CLKSEL_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_PWM_CTL_0_CLKSEL_INIT_ENUM PCLK +#define SOR_NV_PDISP_SOR_PWM_CTL_0_CLKSEL_PCLK _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_PWM_CTL_0_CLKSEL_XTAL _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_PWM_CTL_0_DUTY_CYCLE_SHIFT _MK_SHIFT_CONST(0) +#define SOR_NV_PDISP_SOR_PWM_CTL_0_DUTY_CYCLE_FIELD _MK_FIELD_CONST(0xffffff, SOR_NV_PDISP_SOR_PWM_CTL_0_DUTY_CYCLE_SHIFT) +#define SOR_NV_PDISP_SOR_PWM_CTL_0_DUTY_CYCLE_RANGE 23:0 +#define SOR_NV_PDISP_SOR_PWM_CTL_0_DUTY_CYCLE_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_PWM_CTL_0_DUTY_CYCLE_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_PWM_CTL_0_DUTY_CYCLE_DEFAULT_MASK _MK_MASK_CONST(0xffffff) +#define SOR_NV_PDISP_SOR_PWM_CTL_0_DUTY_CYCLE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_PWM_CTL_0_DUTY_CYCLE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register SOR_NV_PDISP_SOR_VCRCA0_0 +#define SOR_NV_PDISP_SOR_VCRCA0_0 _MK_ADDR_CONST(0x34) +#define SOR_NV_PDISP_SOR_VCRCA0_0_SECURE 0x0 +#define SOR_NV_PDISP_SOR_VCRCA0_0_WORD_COUNT 0x1 +#define SOR_NV_PDISP_SOR_VCRCA0_0_RESET_VAL _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_VCRCA0_0_RESET_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_VCRCA0_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_VCRCA0_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_VCRCA0_0_READ_MASK _MK_MASK_CONST(0xffffffff) +#define SOR_NV_PDISP_SOR_VCRCA0_0_WRITE_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_VCRCA0_0_CRCM_SHIFT _MK_SHIFT_CONST(16) +#define SOR_NV_PDISP_SOR_VCRCA0_0_CRCM_FIELD _MK_FIELD_CONST(0xffff, SOR_NV_PDISP_SOR_VCRCA0_0_CRCM_SHIFT) +#define SOR_NV_PDISP_SOR_VCRCA0_0_CRCM_RANGE 31:16 +#define SOR_NV_PDISP_SOR_VCRCA0_0_CRCM_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_VCRCA0_0_CRCM_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_VCRCA0_0_CRCM_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_VCRCA0_0_CRCM_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_VCRCA0_0_CRCM_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define SOR_NV_PDISP_SOR_VCRCA0_0_CRCL_SHIFT _MK_SHIFT_CONST(0) +#define SOR_NV_PDISP_SOR_VCRCA0_0_CRCL_FIELD _MK_FIELD_CONST(0xffff, SOR_NV_PDISP_SOR_VCRCA0_0_CRCL_SHIFT) +#define SOR_NV_PDISP_SOR_VCRCA0_0_CRCL_RANGE 15:0 +#define SOR_NV_PDISP_SOR_VCRCA0_0_CRCL_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_VCRCA0_0_CRCL_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_VCRCA0_0_CRCL_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_VCRCA0_0_CRCL_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_VCRCA0_0_CRCL_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register SOR_NV_PDISP_SOR_VCRCA1_0 +#define SOR_NV_PDISP_SOR_VCRCA1_0 _MK_ADDR_CONST(0x35) +#define SOR_NV_PDISP_SOR_VCRCA1_0_SECURE 0x0 +#define SOR_NV_PDISP_SOR_VCRCA1_0_WORD_COUNT 0x1 +#define SOR_NV_PDISP_SOR_VCRCA1_0_RESET_VAL _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_VCRCA1_0_RESET_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_VCRCA1_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_VCRCA1_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_VCRCA1_0_READ_MASK _MK_MASK_CONST(0xffff) +#define SOR_NV_PDISP_SOR_VCRCA1_0_WRITE_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_VCRCA1_0_CRCH_SHIFT _MK_SHIFT_CONST(0) +#define SOR_NV_PDISP_SOR_VCRCA1_0_CRCH_FIELD _MK_FIELD_CONST(0xffff, SOR_NV_PDISP_SOR_VCRCA1_0_CRCH_SHIFT) +#define SOR_NV_PDISP_SOR_VCRCA1_0_CRCH_RANGE 15:0 +#define SOR_NV_PDISP_SOR_VCRCA1_0_CRCH_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_VCRCA1_0_CRCH_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_VCRCA1_0_CRCH_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_VCRCA1_0_CRCH_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_VCRCA1_0_CRCH_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register SOR_NV_PDISP_SOR_VCRCB0_0 +#define SOR_NV_PDISP_SOR_VCRCB0_0 _MK_ADDR_CONST(0x36) +#define SOR_NV_PDISP_SOR_VCRCB0_0_SECURE 0x0 +#define SOR_NV_PDISP_SOR_VCRCB0_0_WORD_COUNT 0x1 +#define SOR_NV_PDISP_SOR_VCRCB0_0_RESET_VAL _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_VCRCB0_0_RESET_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_VCRCB0_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_VCRCB0_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_VCRCB0_0_READ_MASK _MK_MASK_CONST(0xffffffff) +#define SOR_NV_PDISP_SOR_VCRCB0_0_WRITE_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_VCRCB0_0_CRCM_SHIFT _MK_SHIFT_CONST(16) +#define SOR_NV_PDISP_SOR_VCRCB0_0_CRCM_FIELD _MK_FIELD_CONST(0xffff, SOR_NV_PDISP_SOR_VCRCB0_0_CRCM_SHIFT) +#define SOR_NV_PDISP_SOR_VCRCB0_0_CRCM_RANGE 31:16 +#define SOR_NV_PDISP_SOR_VCRCB0_0_CRCM_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_VCRCB0_0_CRCM_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_VCRCB0_0_CRCM_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_VCRCB0_0_CRCM_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_VCRCB0_0_CRCM_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define SOR_NV_PDISP_SOR_VCRCB0_0_CRCL_SHIFT _MK_SHIFT_CONST(0) +#define SOR_NV_PDISP_SOR_VCRCB0_0_CRCL_FIELD _MK_FIELD_CONST(0xffff, SOR_NV_PDISP_SOR_VCRCB0_0_CRCL_SHIFT) +#define SOR_NV_PDISP_SOR_VCRCB0_0_CRCL_RANGE 15:0 +#define SOR_NV_PDISP_SOR_VCRCB0_0_CRCL_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_VCRCB0_0_CRCL_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_VCRCB0_0_CRCL_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_VCRCB0_0_CRCL_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_VCRCB0_0_CRCL_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register SOR_NV_PDISP_SOR_VCRCB1_0 +#define SOR_NV_PDISP_SOR_VCRCB1_0 _MK_ADDR_CONST(0x37) +#define SOR_NV_PDISP_SOR_VCRCB1_0_SECURE 0x0 +#define SOR_NV_PDISP_SOR_VCRCB1_0_WORD_COUNT 0x1 +#define SOR_NV_PDISP_SOR_VCRCB1_0_RESET_VAL _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_VCRCB1_0_RESET_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_VCRCB1_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_VCRCB1_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_VCRCB1_0_READ_MASK _MK_MASK_CONST(0xffff) +#define SOR_NV_PDISP_SOR_VCRCB1_0_WRITE_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_VCRCB1_0_CRCH_SHIFT _MK_SHIFT_CONST(0) +#define SOR_NV_PDISP_SOR_VCRCB1_0_CRCH_FIELD _MK_FIELD_CONST(0xffff, SOR_NV_PDISP_SOR_VCRCB1_0_CRCH_SHIFT) +#define SOR_NV_PDISP_SOR_VCRCB1_0_CRCH_RANGE 15:0 +#define SOR_NV_PDISP_SOR_VCRCB1_0_CRCH_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_VCRCB1_0_CRCH_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_VCRCB1_0_CRCH_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_VCRCB1_0_CRCH_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_VCRCB1_0_CRCH_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register SOR_NV_PDISP_SOR_CCRCA0_0 +#define SOR_NV_PDISP_SOR_CCRCA0_0 _MK_ADDR_CONST(0x38) +#define SOR_NV_PDISP_SOR_CCRCA0_0_SECURE 0x0 +#define SOR_NV_PDISP_SOR_CCRCA0_0_WORD_COUNT 0x1 +#define SOR_NV_PDISP_SOR_CCRCA0_0_RESET_VAL _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_CCRCA0_0_RESET_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_CCRCA0_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_CCRCA0_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_CCRCA0_0_READ_MASK _MK_MASK_CONST(0xffffffff) +#define SOR_NV_PDISP_SOR_CCRCA0_0_WRITE_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_CCRCA0_0_CRCM_SHIFT _MK_SHIFT_CONST(16) +#define SOR_NV_PDISP_SOR_CCRCA0_0_CRCM_FIELD _MK_FIELD_CONST(0xffff, SOR_NV_PDISP_SOR_CCRCA0_0_CRCM_SHIFT) +#define SOR_NV_PDISP_SOR_CCRCA0_0_CRCM_RANGE 31:16 +#define SOR_NV_PDISP_SOR_CCRCA0_0_CRCM_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_CCRCA0_0_CRCM_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_CCRCA0_0_CRCM_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_CCRCA0_0_CRCM_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_CCRCA0_0_CRCM_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define SOR_NV_PDISP_SOR_CCRCA0_0_CRCL_SHIFT _MK_SHIFT_CONST(0) +#define SOR_NV_PDISP_SOR_CCRCA0_0_CRCL_FIELD _MK_FIELD_CONST(0xffff, SOR_NV_PDISP_SOR_CCRCA0_0_CRCL_SHIFT) +#define SOR_NV_PDISP_SOR_CCRCA0_0_CRCL_RANGE 15:0 +#define SOR_NV_PDISP_SOR_CCRCA0_0_CRCL_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_CCRCA0_0_CRCL_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_CCRCA0_0_CRCL_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_CCRCA0_0_CRCL_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_CCRCA0_0_CRCL_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register SOR_NV_PDISP_SOR_CCRCA1_0 +#define SOR_NV_PDISP_SOR_CCRCA1_0 _MK_ADDR_CONST(0x39) +#define SOR_NV_PDISP_SOR_CCRCA1_0_SECURE 0x0 +#define SOR_NV_PDISP_SOR_CCRCA1_0_WORD_COUNT 0x1 +#define SOR_NV_PDISP_SOR_CCRCA1_0_RESET_VAL _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_CCRCA1_0_RESET_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_CCRCA1_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_CCRCA1_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_CCRCA1_0_READ_MASK _MK_MASK_CONST(0xffff) +#define SOR_NV_PDISP_SOR_CCRCA1_0_WRITE_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_CCRCA1_0_CRCH_SHIFT _MK_SHIFT_CONST(0) +#define SOR_NV_PDISP_SOR_CCRCA1_0_CRCH_FIELD _MK_FIELD_CONST(0xffff, SOR_NV_PDISP_SOR_CCRCA1_0_CRCH_SHIFT) +#define SOR_NV_PDISP_SOR_CCRCA1_0_CRCH_RANGE 15:0 +#define SOR_NV_PDISP_SOR_CCRCA1_0_CRCH_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_CCRCA1_0_CRCH_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_CCRCA1_0_CRCH_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_CCRCA1_0_CRCH_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_CCRCA1_0_CRCH_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register SOR_NV_PDISP_SOR_CCRCB0_0 +#define SOR_NV_PDISP_SOR_CCRCB0_0 _MK_ADDR_CONST(0x3a) +#define SOR_NV_PDISP_SOR_CCRCB0_0_SECURE 0x0 +#define SOR_NV_PDISP_SOR_CCRCB0_0_WORD_COUNT 0x1 +#define SOR_NV_PDISP_SOR_CCRCB0_0_RESET_VAL _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_CCRCB0_0_RESET_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_CCRCB0_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_CCRCB0_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_CCRCB0_0_READ_MASK _MK_MASK_CONST(0xffffffff) +#define SOR_NV_PDISP_SOR_CCRCB0_0_WRITE_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_CCRCB0_0_CRCM_SHIFT _MK_SHIFT_CONST(16) +#define SOR_NV_PDISP_SOR_CCRCB0_0_CRCM_FIELD _MK_FIELD_CONST(0xffff, SOR_NV_PDISP_SOR_CCRCB0_0_CRCM_SHIFT) +#define SOR_NV_PDISP_SOR_CCRCB0_0_CRCM_RANGE 31:16 +#define SOR_NV_PDISP_SOR_CCRCB0_0_CRCM_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_CCRCB0_0_CRCM_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_CCRCB0_0_CRCM_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_CCRCB0_0_CRCM_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_CCRCB0_0_CRCM_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define SOR_NV_PDISP_SOR_CCRCB0_0_CRCL_SHIFT _MK_SHIFT_CONST(0) +#define SOR_NV_PDISP_SOR_CCRCB0_0_CRCL_FIELD _MK_FIELD_CONST(0xffff, SOR_NV_PDISP_SOR_CCRCB0_0_CRCL_SHIFT) +#define SOR_NV_PDISP_SOR_CCRCB0_0_CRCL_RANGE 15:0 +#define SOR_NV_PDISP_SOR_CCRCB0_0_CRCL_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_CCRCB0_0_CRCL_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_CCRCB0_0_CRCL_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_CCRCB0_0_CRCL_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_CCRCB0_0_CRCL_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register SOR_NV_PDISP_SOR_CCRCB1_0 +#define SOR_NV_PDISP_SOR_CCRCB1_0 _MK_ADDR_CONST(0x3b) +#define SOR_NV_PDISP_SOR_CCRCB1_0_SECURE 0x0 +#define SOR_NV_PDISP_SOR_CCRCB1_0_WORD_COUNT 0x1 +#define SOR_NV_PDISP_SOR_CCRCB1_0_RESET_VAL _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_CCRCB1_0_RESET_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_CCRCB1_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_CCRCB1_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_CCRCB1_0_READ_MASK _MK_MASK_CONST(0xffff) +#define SOR_NV_PDISP_SOR_CCRCB1_0_WRITE_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_CCRCB1_0_CRCH_SHIFT _MK_SHIFT_CONST(0) +#define SOR_NV_PDISP_SOR_CCRCB1_0_CRCH_FIELD _MK_FIELD_CONST(0xffff, SOR_NV_PDISP_SOR_CCRCB1_0_CRCH_SHIFT) +#define SOR_NV_PDISP_SOR_CCRCB1_0_CRCH_RANGE 15:0 +#define SOR_NV_PDISP_SOR_CCRCB1_0_CRCH_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_CCRCB1_0_CRCH_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_CCRCB1_0_CRCH_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_CCRCB1_0_CRCH_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_CCRCB1_0_CRCH_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register SOR_NV_PDISP_SOR_EDATAA0_0 +#define SOR_NV_PDISP_SOR_EDATAA0_0 _MK_ADDR_CONST(0x3c) +#define SOR_NV_PDISP_SOR_EDATAA0_0_SECURE 0x0 +#define SOR_NV_PDISP_SOR_EDATAA0_0_WORD_COUNT 0x1 +#define SOR_NV_PDISP_SOR_EDATAA0_0_RESET_VAL _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_EDATAA0_0_RESET_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_EDATAA0_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_EDATAA0_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_EDATAA0_0_READ_MASK _MK_MASK_CONST(0xffffffff) +#define SOR_NV_PDISP_SOR_EDATAA0_0_WRITE_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_EDATAA0_0_VAL_SHIFT _MK_SHIFT_CONST(0) +#define SOR_NV_PDISP_SOR_EDATAA0_0_VAL_FIELD _MK_FIELD_CONST(0xffffffff, SOR_NV_PDISP_SOR_EDATAA0_0_VAL_SHIFT) +#define SOR_NV_PDISP_SOR_EDATAA0_0_VAL_RANGE 31:0 +#define SOR_NV_PDISP_SOR_EDATAA0_0_VAL_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_EDATAA0_0_VAL_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_EDATAA0_0_VAL_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_EDATAA0_0_VAL_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_EDATAA0_0_VAL_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register SOR_NV_PDISP_SOR_EDATAA1_0 +#define SOR_NV_PDISP_SOR_EDATAA1_0 _MK_ADDR_CONST(0x3d) +#define SOR_NV_PDISP_SOR_EDATAA1_0_SECURE 0x0 +#define SOR_NV_PDISP_SOR_EDATAA1_0_WORD_COUNT 0x1 +#define SOR_NV_PDISP_SOR_EDATAA1_0_RESET_VAL _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_EDATAA1_0_RESET_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_EDATAA1_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_EDATAA1_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_EDATAA1_0_READ_MASK _MK_MASK_CONST(0xff) +#define SOR_NV_PDISP_SOR_EDATAA1_0_WRITE_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_EDATAA1_0_VAL_SHIFT _MK_SHIFT_CONST(0) +#define SOR_NV_PDISP_SOR_EDATAA1_0_VAL_FIELD _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_EDATAA1_0_VAL_SHIFT) +#define SOR_NV_PDISP_SOR_EDATAA1_0_VAL_RANGE 7:0 +#define SOR_NV_PDISP_SOR_EDATAA1_0_VAL_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_EDATAA1_0_VAL_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_EDATAA1_0_VAL_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_EDATAA1_0_VAL_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_EDATAA1_0_VAL_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register SOR_NV_PDISP_SOR_EDATAB0_0 +#define SOR_NV_PDISP_SOR_EDATAB0_0 _MK_ADDR_CONST(0x3e) +#define SOR_NV_PDISP_SOR_EDATAB0_0_SECURE 0x0 +#define SOR_NV_PDISP_SOR_EDATAB0_0_WORD_COUNT 0x1 +#define SOR_NV_PDISP_SOR_EDATAB0_0_RESET_VAL _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_EDATAB0_0_RESET_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_EDATAB0_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_EDATAB0_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_EDATAB0_0_READ_MASK _MK_MASK_CONST(0xffffffff) +#define SOR_NV_PDISP_SOR_EDATAB0_0_WRITE_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_EDATAB0_0_VAL_SHIFT _MK_SHIFT_CONST(0) +#define SOR_NV_PDISP_SOR_EDATAB0_0_VAL_FIELD _MK_FIELD_CONST(0xffffffff, SOR_NV_PDISP_SOR_EDATAB0_0_VAL_SHIFT) +#define SOR_NV_PDISP_SOR_EDATAB0_0_VAL_RANGE 31:0 +#define SOR_NV_PDISP_SOR_EDATAB0_0_VAL_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_EDATAB0_0_VAL_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_EDATAB0_0_VAL_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_EDATAB0_0_VAL_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_EDATAB0_0_VAL_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register SOR_NV_PDISP_SOR_EDATAB1_0 +#define SOR_NV_PDISP_SOR_EDATAB1_0 _MK_ADDR_CONST(0x3f) +#define SOR_NV_PDISP_SOR_EDATAB1_0_SECURE 0x0 +#define SOR_NV_PDISP_SOR_EDATAB1_0_WORD_COUNT 0x1 +#define SOR_NV_PDISP_SOR_EDATAB1_0_RESET_VAL _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_EDATAB1_0_RESET_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_EDATAB1_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_EDATAB1_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_EDATAB1_0_READ_MASK _MK_MASK_CONST(0xff) +#define SOR_NV_PDISP_SOR_EDATAB1_0_WRITE_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_EDATAB1_0_VAL_SHIFT _MK_SHIFT_CONST(0) +#define SOR_NV_PDISP_SOR_EDATAB1_0_VAL_FIELD _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_EDATAB1_0_VAL_SHIFT) +#define SOR_NV_PDISP_SOR_EDATAB1_0_VAL_RANGE 7:0 +#define SOR_NV_PDISP_SOR_EDATAB1_0_VAL_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_EDATAB1_0_VAL_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_EDATAB1_0_VAL_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_EDATAB1_0_VAL_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_EDATAB1_0_VAL_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register SOR_NV_PDISP_SOR_COUNTA0_0 +#define SOR_NV_PDISP_SOR_COUNTA0_0 _MK_ADDR_CONST(0x40) +#define SOR_NV_PDISP_SOR_COUNTA0_0_SECURE 0x0 +#define SOR_NV_PDISP_SOR_COUNTA0_0_WORD_COUNT 0x1 +#define SOR_NV_PDISP_SOR_COUNTA0_0_RESET_VAL _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_COUNTA0_0_RESET_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_COUNTA0_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_COUNTA0_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_COUNTA0_0_READ_MASK _MK_MASK_CONST(0xffffffff) +#define SOR_NV_PDISP_SOR_COUNTA0_0_WRITE_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_COUNTA0_0_TX1_SHIFT _MK_SHIFT_CONST(16) +#define SOR_NV_PDISP_SOR_COUNTA0_0_TX1_FIELD _MK_FIELD_CONST(0xffff, SOR_NV_PDISP_SOR_COUNTA0_0_TX1_SHIFT) +#define SOR_NV_PDISP_SOR_COUNTA0_0_TX1_RANGE 31:16 +#define SOR_NV_PDISP_SOR_COUNTA0_0_TX1_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_COUNTA0_0_TX1_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_COUNTA0_0_TX1_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_COUNTA0_0_TX1_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_COUNTA0_0_TX1_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define SOR_NV_PDISP_SOR_COUNTA0_0_TX0_SHIFT _MK_SHIFT_CONST(0) +#define SOR_NV_PDISP_SOR_COUNTA0_0_TX0_FIELD _MK_FIELD_CONST(0xffff, SOR_NV_PDISP_SOR_COUNTA0_0_TX0_SHIFT) +#define SOR_NV_PDISP_SOR_COUNTA0_0_TX0_RANGE 15:0 +#define SOR_NV_PDISP_SOR_COUNTA0_0_TX0_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_COUNTA0_0_TX0_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_COUNTA0_0_TX0_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_COUNTA0_0_TX0_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_COUNTA0_0_TX0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register SOR_NV_PDISP_SOR_COUNTA1_0 +#define SOR_NV_PDISP_SOR_COUNTA1_0 _MK_ADDR_CONST(0x41) +#define SOR_NV_PDISP_SOR_COUNTA1_0_SECURE 0x0 +#define SOR_NV_PDISP_SOR_COUNTA1_0_WORD_COUNT 0x1 +#define SOR_NV_PDISP_SOR_COUNTA1_0_RESET_VAL _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_COUNTA1_0_RESET_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_COUNTA1_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_COUNTA1_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_COUNTA1_0_READ_MASK _MK_MASK_CONST(0xffff) +#define SOR_NV_PDISP_SOR_COUNTA1_0_WRITE_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_COUNTA1_0_TX2_SHIFT _MK_SHIFT_CONST(0) +#define SOR_NV_PDISP_SOR_COUNTA1_0_TX2_FIELD _MK_FIELD_CONST(0xffff, SOR_NV_PDISP_SOR_COUNTA1_0_TX2_SHIFT) +#define SOR_NV_PDISP_SOR_COUNTA1_0_TX2_RANGE 15:0 +#define SOR_NV_PDISP_SOR_COUNTA1_0_TX2_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_COUNTA1_0_TX2_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_COUNTA1_0_TX2_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_COUNTA1_0_TX2_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_COUNTA1_0_TX2_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register SOR_NV_PDISP_SOR_COUNTB0_0 +#define SOR_NV_PDISP_SOR_COUNTB0_0 _MK_ADDR_CONST(0x42) +#define SOR_NV_PDISP_SOR_COUNTB0_0_SECURE 0x0 +#define SOR_NV_PDISP_SOR_COUNTB0_0_WORD_COUNT 0x1 +#define SOR_NV_PDISP_SOR_COUNTB0_0_RESET_VAL _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_COUNTB0_0_RESET_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_COUNTB0_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_COUNTB0_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_COUNTB0_0_READ_MASK _MK_MASK_CONST(0xffffffff) +#define SOR_NV_PDISP_SOR_COUNTB0_0_WRITE_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_COUNTB0_0_TX1_SHIFT _MK_SHIFT_CONST(16) +#define SOR_NV_PDISP_SOR_COUNTB0_0_TX1_FIELD _MK_FIELD_CONST(0xffff, SOR_NV_PDISP_SOR_COUNTB0_0_TX1_SHIFT) +#define SOR_NV_PDISP_SOR_COUNTB0_0_TX1_RANGE 31:16 +#define SOR_NV_PDISP_SOR_COUNTB0_0_TX1_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_COUNTB0_0_TX1_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_COUNTB0_0_TX1_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_COUNTB0_0_TX1_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_COUNTB0_0_TX1_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define SOR_NV_PDISP_SOR_COUNTB0_0_TX0_SHIFT _MK_SHIFT_CONST(0) +#define SOR_NV_PDISP_SOR_COUNTB0_0_TX0_FIELD _MK_FIELD_CONST(0xffff, SOR_NV_PDISP_SOR_COUNTB0_0_TX0_SHIFT) +#define SOR_NV_PDISP_SOR_COUNTB0_0_TX0_RANGE 15:0 +#define SOR_NV_PDISP_SOR_COUNTB0_0_TX0_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_COUNTB0_0_TX0_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_COUNTB0_0_TX0_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_COUNTB0_0_TX0_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_COUNTB0_0_TX0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register SOR_NV_PDISP_SOR_COUNTB1_0 +#define SOR_NV_PDISP_SOR_COUNTB1_0 _MK_ADDR_CONST(0x43) +#define SOR_NV_PDISP_SOR_COUNTB1_0_SECURE 0x0 +#define SOR_NV_PDISP_SOR_COUNTB1_0_WORD_COUNT 0x1 +#define SOR_NV_PDISP_SOR_COUNTB1_0_RESET_VAL _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_COUNTB1_0_RESET_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_COUNTB1_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_COUNTB1_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_COUNTB1_0_READ_MASK _MK_MASK_CONST(0xffff) +#define SOR_NV_PDISP_SOR_COUNTB1_0_WRITE_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_COUNTB1_0_TX2_SHIFT _MK_SHIFT_CONST(0) +#define SOR_NV_PDISP_SOR_COUNTB1_0_TX2_FIELD _MK_FIELD_CONST(0xffff, SOR_NV_PDISP_SOR_COUNTB1_0_TX2_SHIFT) +#define SOR_NV_PDISP_SOR_COUNTB1_0_TX2_RANGE 15:0 +#define SOR_NV_PDISP_SOR_COUNTB1_0_TX2_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_COUNTB1_0_TX2_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_COUNTB1_0_TX2_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_COUNTB1_0_TX2_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_COUNTB1_0_TX2_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register SOR_NV_PDISP_SOR_DEBUGA0_0 +#define SOR_NV_PDISP_SOR_DEBUGA0_0 _MK_ADDR_CONST(0x44) +#define SOR_NV_PDISP_SOR_DEBUGA0_0_SECURE 0x0 +#define SOR_NV_PDISP_SOR_DEBUGA0_0_WORD_COUNT 0x1 +#define SOR_NV_PDISP_SOR_DEBUGA0_0_RESET_VAL _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DEBUGA0_0_RESET_MASK _MK_MASK_CONST(0xffffffff) +#define SOR_NV_PDISP_SOR_DEBUGA0_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DEBUGA0_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DEBUGA0_0_READ_MASK _MK_MASK_CONST(0xffffffff) +#define SOR_NV_PDISP_SOR_DEBUGA0_0_WRITE_MASK _MK_MASK_CONST(0xffffffff) +#define SOR_NV_PDISP_SOR_DEBUGA0_0_VAL_SHIFT _MK_SHIFT_CONST(0) +#define SOR_NV_PDISP_SOR_DEBUGA0_0_VAL_FIELD _MK_FIELD_CONST(0xffffffff, SOR_NV_PDISP_SOR_DEBUGA0_0_VAL_SHIFT) +#define SOR_NV_PDISP_SOR_DEBUGA0_0_VAL_RANGE 31:0 +#define SOR_NV_PDISP_SOR_DEBUGA0_0_VAL_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_DEBUGA0_0_VAL_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DEBUGA0_0_VAL_DEFAULT_MASK _MK_MASK_CONST(0xffffffff) +#define SOR_NV_PDISP_SOR_DEBUGA0_0_VAL_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DEBUGA0_0_VAL_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DEBUGA0_0_VAL_INIT_ENUM RST +#define SOR_NV_PDISP_SOR_DEBUGA0_0_VAL_RST _MK_ENUM_CONST(0) + + +// Register SOR_NV_PDISP_SOR_DEBUGA1_0 +#define SOR_NV_PDISP_SOR_DEBUGA1_0 _MK_ADDR_CONST(0x45) +#define SOR_NV_PDISP_SOR_DEBUGA1_0_SECURE 0x0 +#define SOR_NV_PDISP_SOR_DEBUGA1_0_WORD_COUNT 0x1 +#define SOR_NV_PDISP_SOR_DEBUGA1_0_RESET_VAL _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DEBUGA1_0_RESET_MASK _MK_MASK_CONST(0xff) +#define SOR_NV_PDISP_SOR_DEBUGA1_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DEBUGA1_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DEBUGA1_0_READ_MASK _MK_MASK_CONST(0xff) +#define SOR_NV_PDISP_SOR_DEBUGA1_0_WRITE_MASK _MK_MASK_CONST(0xff) +#define SOR_NV_PDISP_SOR_DEBUGA1_0_VAL_SHIFT _MK_SHIFT_CONST(0) +#define SOR_NV_PDISP_SOR_DEBUGA1_0_VAL_FIELD _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_DEBUGA1_0_VAL_SHIFT) +#define SOR_NV_PDISP_SOR_DEBUGA1_0_VAL_RANGE 7:0 +#define SOR_NV_PDISP_SOR_DEBUGA1_0_VAL_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_DEBUGA1_0_VAL_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DEBUGA1_0_VAL_DEFAULT_MASK _MK_MASK_CONST(0xff) +#define SOR_NV_PDISP_SOR_DEBUGA1_0_VAL_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DEBUGA1_0_VAL_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DEBUGA1_0_VAL_INIT_ENUM RST +#define SOR_NV_PDISP_SOR_DEBUGA1_0_VAL_RST _MK_ENUM_CONST(0) + + +// Register SOR_NV_PDISP_SOR_DEBUGB0_0 +#define SOR_NV_PDISP_SOR_DEBUGB0_0 _MK_ADDR_CONST(0x46) +#define SOR_NV_PDISP_SOR_DEBUGB0_0_SECURE 0x0 +#define SOR_NV_PDISP_SOR_DEBUGB0_0_WORD_COUNT 0x1 +#define SOR_NV_PDISP_SOR_DEBUGB0_0_RESET_VAL _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DEBUGB0_0_RESET_MASK _MK_MASK_CONST(0xffffffff) +#define SOR_NV_PDISP_SOR_DEBUGB0_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DEBUGB0_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DEBUGB0_0_READ_MASK _MK_MASK_CONST(0xffffffff) +#define SOR_NV_PDISP_SOR_DEBUGB0_0_WRITE_MASK _MK_MASK_CONST(0xffffffff) +#define SOR_NV_PDISP_SOR_DEBUGB0_0_VAL_SHIFT _MK_SHIFT_CONST(0) +#define SOR_NV_PDISP_SOR_DEBUGB0_0_VAL_FIELD _MK_FIELD_CONST(0xffffffff, SOR_NV_PDISP_SOR_DEBUGB0_0_VAL_SHIFT) +#define SOR_NV_PDISP_SOR_DEBUGB0_0_VAL_RANGE 31:0 +#define SOR_NV_PDISP_SOR_DEBUGB0_0_VAL_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_DEBUGB0_0_VAL_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DEBUGB0_0_VAL_DEFAULT_MASK _MK_MASK_CONST(0xffffffff) +#define SOR_NV_PDISP_SOR_DEBUGB0_0_VAL_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DEBUGB0_0_VAL_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DEBUGB0_0_VAL_INIT_ENUM RST +#define SOR_NV_PDISP_SOR_DEBUGB0_0_VAL_RST _MK_ENUM_CONST(0) + + +// Register SOR_NV_PDISP_SOR_DEBUGB1_0 +#define SOR_NV_PDISP_SOR_DEBUGB1_0 _MK_ADDR_CONST(0x47) +#define SOR_NV_PDISP_SOR_DEBUGB1_0_SECURE 0x0 +#define SOR_NV_PDISP_SOR_DEBUGB1_0_WORD_COUNT 0x1 +#define SOR_NV_PDISP_SOR_DEBUGB1_0_RESET_VAL _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DEBUGB1_0_RESET_MASK _MK_MASK_CONST(0xff) +#define SOR_NV_PDISP_SOR_DEBUGB1_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DEBUGB1_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DEBUGB1_0_READ_MASK _MK_MASK_CONST(0xff) +#define SOR_NV_PDISP_SOR_DEBUGB1_0_WRITE_MASK _MK_MASK_CONST(0xff) +#define SOR_NV_PDISP_SOR_DEBUGB1_0_VAL_SHIFT _MK_SHIFT_CONST(0) +#define SOR_NV_PDISP_SOR_DEBUGB1_0_VAL_FIELD _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_DEBUGB1_0_VAL_SHIFT) +#define SOR_NV_PDISP_SOR_DEBUGB1_0_VAL_RANGE 7:0 +#define SOR_NV_PDISP_SOR_DEBUGB1_0_VAL_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_DEBUGB1_0_VAL_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DEBUGB1_0_VAL_DEFAULT_MASK _MK_MASK_CONST(0xff) +#define SOR_NV_PDISP_SOR_DEBUGB1_0_VAL_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DEBUGB1_0_VAL_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DEBUGB1_0_VAL_INIT_ENUM RST +#define SOR_NV_PDISP_SOR_DEBUGB1_0_VAL_RST _MK_ENUM_CONST(0) + + +// Register SOR_NV_PDISP_SOR_TRIG_0 +#define SOR_NV_PDISP_SOR_TRIG_0 _MK_ADDR_CONST(0x48) +#define SOR_NV_PDISP_SOR_TRIG_0_SECURE 0x0 +#define SOR_NV_PDISP_SOR_TRIG_0_WORD_COUNT 0x1 +#define SOR_NV_PDISP_SOR_TRIG_0_RESET_VAL _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_TRIG_0_RESET_MASK _MK_MASK_CONST(0xffffff) +#define SOR_NV_PDISP_SOR_TRIG_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_TRIG_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_TRIG_0_READ_MASK _MK_MASK_CONST(0xffffff) +#define SOR_NV_PDISP_SOR_TRIG_0_WRITE_MASK _MK_MASK_CONST(0xffffff) +#define SOR_NV_PDISP_SOR_TRIG_0_VAL_SHIFT _MK_SHIFT_CONST(0) +#define SOR_NV_PDISP_SOR_TRIG_0_VAL_FIELD _MK_FIELD_CONST(0xffffff, SOR_NV_PDISP_SOR_TRIG_0_VAL_SHIFT) +#define SOR_NV_PDISP_SOR_TRIG_0_VAL_RANGE 23:0 +#define SOR_NV_PDISP_SOR_TRIG_0_VAL_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_TRIG_0_VAL_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_TRIG_0_VAL_DEFAULT_MASK _MK_MASK_CONST(0xffffff) +#define SOR_NV_PDISP_SOR_TRIG_0_VAL_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_TRIG_0_VAL_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_TRIG_0_VAL_INIT_ENUM RST +#define SOR_NV_PDISP_SOR_TRIG_0_VAL_RST _MK_ENUM_CONST(0) + + +// Register SOR_NV_PDISP_SOR_MSCHECK_0 +#define SOR_NV_PDISP_SOR_MSCHECK_0 _MK_ADDR_CONST(0x49) +#define SOR_NV_PDISP_SOR_MSCHECK_0_SECURE 0x0 +#define SOR_NV_PDISP_SOR_MSCHECK_0_WORD_COUNT 0x1 +#define SOR_NV_PDISP_SOR_MSCHECK_0_RESET_VAL _MK_MASK_CONST(0x80000000) +#define SOR_NV_PDISP_SOR_MSCHECK_0_RESET_MASK _MK_MASK_CONST(0x80000000) +#define SOR_NV_PDISP_SOR_MSCHECK_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_MSCHECK_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_MSCHECK_0_READ_MASK _MK_MASK_CONST(0x8000ffff) +#define SOR_NV_PDISP_SOR_MSCHECK_0_WRITE_MASK _MK_MASK_CONST(0x80000000) +#define SOR_NV_PDISP_SOR_MSCHECK_0_CTL_SHIFT _MK_SHIFT_CONST(31) +#define SOR_NV_PDISP_SOR_MSCHECK_0_CTL_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_MSCHECK_0_CTL_SHIFT) +#define SOR_NV_PDISP_SOR_MSCHECK_0_CTL_RANGE 31:31 +#define SOR_NV_PDISP_SOR_MSCHECK_0_CTL_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_MSCHECK_0_CTL_DEFAULT _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_MSCHECK_0_CTL_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_MSCHECK_0_CTL_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_MSCHECK_0_CTL_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_MSCHECK_0_CTL_INIT_ENUM RUN +#define SOR_NV_PDISP_SOR_MSCHECK_0_CTL_CLEAR _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_MSCHECK_0_CTL_RUN _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_MSCHECK_0_DATA_ENABLE_T2F_SHIFT _MK_SHIFT_CONST(12) +#define SOR_NV_PDISP_SOR_MSCHECK_0_DATA_ENABLE_T2F_FIELD _MK_FIELD_CONST(0xf, SOR_NV_PDISP_SOR_MSCHECK_0_DATA_ENABLE_T2F_SHIFT) +#define SOR_NV_PDISP_SOR_MSCHECK_0_DATA_ENABLE_T2F_RANGE 15:12 +#define SOR_NV_PDISP_SOR_MSCHECK_0_DATA_ENABLE_T2F_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_MSCHECK_0_DATA_ENABLE_T2F_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_MSCHECK_0_DATA_ENABLE_T2F_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_MSCHECK_0_DATA_ENABLE_T2F_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_MSCHECK_0_DATA_ENABLE_T2F_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define SOR_NV_PDISP_SOR_MSCHECK_0_DATA_ENABLE_F2T_SHIFT _MK_SHIFT_CONST(8) +#define SOR_NV_PDISP_SOR_MSCHECK_0_DATA_ENABLE_F2T_FIELD _MK_FIELD_CONST(0xf, SOR_NV_PDISP_SOR_MSCHECK_0_DATA_ENABLE_F2T_SHIFT) +#define SOR_NV_PDISP_SOR_MSCHECK_0_DATA_ENABLE_F2T_RANGE 11:8 +#define SOR_NV_PDISP_SOR_MSCHECK_0_DATA_ENABLE_F2T_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_MSCHECK_0_DATA_ENABLE_F2T_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_MSCHECK_0_DATA_ENABLE_F2T_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_MSCHECK_0_DATA_ENABLE_F2T_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_MSCHECK_0_DATA_ENABLE_F2T_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define SOR_NV_PDISP_SOR_MSCHECK_0_CRC_ENABLE_T2F_SHIFT _MK_SHIFT_CONST(4) +#define SOR_NV_PDISP_SOR_MSCHECK_0_CRC_ENABLE_T2F_FIELD _MK_FIELD_CONST(0xf, SOR_NV_PDISP_SOR_MSCHECK_0_CRC_ENABLE_T2F_SHIFT) +#define SOR_NV_PDISP_SOR_MSCHECK_0_CRC_ENABLE_T2F_RANGE 7:4 +#define SOR_NV_PDISP_SOR_MSCHECK_0_CRC_ENABLE_T2F_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_MSCHECK_0_CRC_ENABLE_T2F_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_MSCHECK_0_CRC_ENABLE_T2F_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_MSCHECK_0_CRC_ENABLE_T2F_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_MSCHECK_0_CRC_ENABLE_T2F_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define SOR_NV_PDISP_SOR_MSCHECK_0_CRC_ENABLE_F2T_SHIFT _MK_SHIFT_CONST(0) +#define SOR_NV_PDISP_SOR_MSCHECK_0_CRC_ENABLE_F2T_FIELD _MK_FIELD_CONST(0xf, SOR_NV_PDISP_SOR_MSCHECK_0_CRC_ENABLE_F2T_SHIFT) +#define SOR_NV_PDISP_SOR_MSCHECK_0_CRC_ENABLE_F2T_RANGE 3:0 +#define SOR_NV_PDISP_SOR_MSCHECK_0_CRC_ENABLE_F2T_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_MSCHECK_0_CRC_ENABLE_F2T_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_MSCHECK_0_CRC_ENABLE_F2T_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_MSCHECK_0_CRC_ENABLE_F2T_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_MSCHECK_0_CRC_ENABLE_F2T_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register SOR_NV_PDISP_SOR_XBAR_CTRL_0 +#define SOR_NV_PDISP_SOR_XBAR_CTRL_0 _MK_ADDR_CONST(0x4a) +#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_SECURE 0x0 +#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_WORD_COUNT 0x1 +#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_RESET_VAL _MK_MASK_CONST(0x8d111a23) +#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_RESET_MASK _MK_MASK_CONST(0xffffffff) +#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_READ_MASK _MK_MASK_CONST(0xffffffff) +#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_WRITE_MASK _MK_MASK_CONST(0xffffffff) +#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK1_XSEL_4_SHIFT _MK_SHIFT_CONST(29) +#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK1_XSEL_4_FIELD _MK_FIELD_CONST(0x7, SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK1_XSEL_4_SHIFT) +#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK1_XSEL_4_RANGE 31:29 +#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK1_XSEL_4_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK1_XSEL_4_DEFAULT _MK_MASK_CONST(0x4) +#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK1_XSEL_4_DEFAULT_MASK _MK_MASK_CONST(0x7) +#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK1_XSEL_4_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK1_XSEL_4_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK1_XSEL_4_ZERO _MK_ENUM_CONST(7) + +#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK1_XSEL_3_SHIFT _MK_SHIFT_CONST(26) +#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK1_XSEL_3_FIELD _MK_FIELD_CONST(0x7, SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK1_XSEL_3_SHIFT) +#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK1_XSEL_3_RANGE 28:26 +#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK1_XSEL_3_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK1_XSEL_3_DEFAULT _MK_MASK_CONST(0x3) +#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK1_XSEL_3_DEFAULT_MASK _MK_MASK_CONST(0x7) +#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK1_XSEL_3_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK1_XSEL_3_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK1_XSEL_3_ZERO _MK_ENUM_CONST(7) + +#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK1_XSEL_2_SHIFT _MK_SHIFT_CONST(23) +#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK1_XSEL_2_FIELD _MK_FIELD_CONST(0x7, SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK1_XSEL_2_SHIFT) +#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK1_XSEL_2_RANGE 25:23 +#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK1_XSEL_2_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK1_XSEL_2_DEFAULT _MK_MASK_CONST(0x2) +#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK1_XSEL_2_DEFAULT_MASK _MK_MASK_CONST(0x7) +#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK1_XSEL_2_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK1_XSEL_2_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK1_XSEL_2_ZERO _MK_ENUM_CONST(7) + +#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK1_XSEL_1_SHIFT _MK_SHIFT_CONST(20) +#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK1_XSEL_1_FIELD _MK_FIELD_CONST(0x7, SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK1_XSEL_1_SHIFT) +#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK1_XSEL_1_RANGE 22:20 +#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK1_XSEL_1_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK1_XSEL_1_DEFAULT _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK1_XSEL_1_DEFAULT_MASK _MK_MASK_CONST(0x7) +#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK1_XSEL_1_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK1_XSEL_1_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK1_XSEL_1_ZERO _MK_ENUM_CONST(7) + +#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK1_XSEL_0_SHIFT _MK_SHIFT_CONST(17) +#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK1_XSEL_0_FIELD _MK_FIELD_CONST(0x7, SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK1_XSEL_0_SHIFT) +#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK1_XSEL_0_RANGE 19:17 +#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK1_XSEL_0_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK1_XSEL_0_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK1_XSEL_0_DEFAULT_MASK _MK_MASK_CONST(0x7) +#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK1_XSEL_0_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK1_XSEL_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK1_XSEL_0_ZERO _MK_ENUM_CONST(7) + +#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK0_XSEL_4_SHIFT _MK_SHIFT_CONST(14) +#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK0_XSEL_4_FIELD _MK_FIELD_CONST(0x7, SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK0_XSEL_4_SHIFT) +#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK0_XSEL_4_RANGE 16:14 +#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK0_XSEL_4_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK0_XSEL_4_DEFAULT _MK_MASK_CONST(0x4) +#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK0_XSEL_4_DEFAULT_MASK _MK_MASK_CONST(0x7) +#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK0_XSEL_4_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK0_XSEL_4_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK0_XSEL_4_ZERO _MK_ENUM_CONST(7) + +#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK0_XSEL_3_SHIFT _MK_SHIFT_CONST(11) +#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK0_XSEL_3_FIELD _MK_FIELD_CONST(0x7, SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK0_XSEL_3_SHIFT) +#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK0_XSEL_3_RANGE 13:11 +#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK0_XSEL_3_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK0_XSEL_3_DEFAULT _MK_MASK_CONST(0x3) +#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK0_XSEL_3_DEFAULT_MASK _MK_MASK_CONST(0x7) +#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK0_XSEL_3_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK0_XSEL_3_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK0_XSEL_3_ZERO _MK_ENUM_CONST(7) + +#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK0_XSEL_2_SHIFT _MK_SHIFT_CONST(8) +#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK0_XSEL_2_FIELD _MK_FIELD_CONST(0x7, SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK0_XSEL_2_SHIFT) +#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK0_XSEL_2_RANGE 10:8 +#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK0_XSEL_2_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK0_XSEL_2_DEFAULT _MK_MASK_CONST(0x2) +#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK0_XSEL_2_DEFAULT_MASK _MK_MASK_CONST(0x7) +#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK0_XSEL_2_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK0_XSEL_2_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK0_XSEL_2_ZERO _MK_ENUM_CONST(7) + +#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK0_XSEL_1_SHIFT _MK_SHIFT_CONST(5) +#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK0_XSEL_1_FIELD _MK_FIELD_CONST(0x7, SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK0_XSEL_1_SHIFT) +#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK0_XSEL_1_RANGE 7:5 +#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK0_XSEL_1_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK0_XSEL_1_DEFAULT _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK0_XSEL_1_DEFAULT_MASK _MK_MASK_CONST(0x7) +#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK0_XSEL_1_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK0_XSEL_1_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK0_XSEL_1_ZERO _MK_ENUM_CONST(7) + +#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK0_XSEL_0_SHIFT _MK_SHIFT_CONST(2) +#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK0_XSEL_0_FIELD _MK_FIELD_CONST(0x7, SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK0_XSEL_0_SHIFT) +#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK0_XSEL_0_RANGE 4:2 +#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK0_XSEL_0_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK0_XSEL_0_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK0_XSEL_0_DEFAULT_MASK _MK_MASK_CONST(0x7) +#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK0_XSEL_0_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK0_XSEL_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK0_XSEL_0_ZERO _MK_ENUM_CONST(7) + +#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK_SWAP_SHIFT _MK_SHIFT_CONST(1) +#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK_SWAP_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK_SWAP_SHIFT) +#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK_SWAP_RANGE 1:1 +#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK_SWAP_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK_SWAP_DEFAULT _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK_SWAP_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK_SWAP_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_LINK_SWAP_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_BYPASS_SHIFT _MK_SHIFT_CONST(0) +#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_BYPASS_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_XBAR_CTRL_0_BYPASS_SHIFT) +#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_BYPASS_RANGE 0:0 +#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_BYPASS_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_BYPASS_DEFAULT _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_BYPASS_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_BYPASS_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_XBAR_CTRL_0_BYPASS_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register SOR_NV_PDISP_SOR_XBAR_POL_0 +#define SOR_NV_PDISP_SOR_XBAR_POL_0 _MK_ADDR_CONST(0x4b) +#define SOR_NV_PDISP_SOR_XBAR_POL_0_SECURE 0x0 +#define SOR_NV_PDISP_SOR_XBAR_POL_0_WORD_COUNT 0x1 +#define SOR_NV_PDISP_SOR_XBAR_POL_0_RESET_VAL _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_XBAR_POL_0_RESET_MASK _MK_MASK_CONST(0x3ff) +#define SOR_NV_PDISP_SOR_XBAR_POL_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_XBAR_POL_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_XBAR_POL_0_READ_MASK _MK_MASK_CONST(0x3ff) +#define SOR_NV_PDISP_SOR_XBAR_POL_0_WRITE_MASK _MK_MASK_CONST(0x3ff) +#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK1_4_SHIFT _MK_SHIFT_CONST(9) +#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK1_4_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK1_4_SHIFT) +#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK1_4_RANGE 9:9 +#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK1_4_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK1_4_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK1_4_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK1_4_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK1_4_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK1_4_INIT_ENUM NORMAL +#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK1_4_NORMAL _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK1_4_INVERT _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK1_3_SHIFT _MK_SHIFT_CONST(8) +#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK1_3_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK1_3_SHIFT) +#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK1_3_RANGE 8:8 +#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK1_3_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK1_3_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK1_3_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK1_3_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK1_3_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK1_3_INIT_ENUM NORMAL +#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK1_3_NORMAL _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK1_3_INVERT _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK1_2_SHIFT _MK_SHIFT_CONST(7) +#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK1_2_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK1_2_SHIFT) +#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK1_2_RANGE 7:7 +#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK1_2_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK1_2_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK1_2_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK1_2_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK1_2_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK1_2_INIT_ENUM NORMAL +#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK1_2_NORMAL _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK1_2_INVERT _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK1_1_SHIFT _MK_SHIFT_CONST(6) +#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK1_1_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK1_1_SHIFT) +#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK1_1_RANGE 6:6 +#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK1_1_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK1_1_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK1_1_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK1_1_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK1_1_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK1_1_INIT_ENUM NORMAL +#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK1_1_NORMAL _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK1_1_INVERT _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK1_0_SHIFT _MK_SHIFT_CONST(5) +#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK1_0_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK1_0_SHIFT) +#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK1_0_RANGE 5:5 +#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK1_0_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK1_0_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK1_0_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK1_0_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK1_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK1_0_INIT_ENUM NORMAL +#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK1_0_NORMAL _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK1_0_INVERT _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK0_4_SHIFT _MK_SHIFT_CONST(4) +#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK0_4_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK0_4_SHIFT) +#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK0_4_RANGE 4:4 +#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK0_4_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK0_4_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK0_4_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK0_4_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK0_4_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK0_4_INIT_ENUM NORMAL +#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK0_4_NORMAL _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK0_4_INVERT _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK0_3_SHIFT _MK_SHIFT_CONST(3) +#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK0_3_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK0_3_SHIFT) +#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK0_3_RANGE 3:3 +#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK0_3_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK0_3_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK0_3_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK0_3_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK0_3_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK0_3_INIT_ENUM NORMAL +#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK0_3_NORMAL _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK0_3_INVERT _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK0_2_SHIFT _MK_SHIFT_CONST(2) +#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK0_2_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK0_2_SHIFT) +#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK0_2_RANGE 2:2 +#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK0_2_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK0_2_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK0_2_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK0_2_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK0_2_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK0_2_INIT_ENUM NORMAL +#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK0_2_NORMAL _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK0_2_INVERT _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK0_1_SHIFT _MK_SHIFT_CONST(1) +#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK0_1_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK0_1_SHIFT) +#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK0_1_RANGE 1:1 +#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK0_1_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK0_1_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK0_1_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK0_1_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK0_1_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK0_1_INIT_ENUM NORMAL +#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK0_1_NORMAL _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK0_1_INVERT _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK0_0_SHIFT _MK_SHIFT_CONST(0) +#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK0_0_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK0_0_SHIFT) +#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK0_0_RANGE 0:0 +#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK0_0_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK0_0_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK0_0_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK0_0_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK0_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK0_0_INIT_ENUM NORMAL +#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK0_0_NORMAL _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_XBAR_POL_0_POL_LINK0_0_INVERT _MK_ENUM_CONST(1) + + +// Register SOR_NV_PDISP_SOR_DP_LINKCTL0_0 +#define SOR_NV_PDISP_SOR_DP_LINKCTL0_0 _MK_ADDR_CONST(0x4c) +#define SOR_NV_PDISP_SOR_DP_LINKCTL0_0_SECURE 0x0 +#define SOR_NV_PDISP_SOR_DP_LINKCTL0_0_WORD_COUNT 0x1 +#define SOR_NV_PDISP_SOR_DP_LINKCTL0_0_RESET_VAL _MK_MASK_CONST(0x100) +#define SOR_NV_PDISP_SOR_DP_LINKCTL0_0_RESET_MASK _MK_MASK_CONST(0x901f45fd) +#define SOR_NV_PDISP_SOR_DP_LINKCTL0_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_LINKCTL0_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_LINKCTL0_0_READ_MASK _MK_MASK_CONST(0x901f45fd) +#define SOR_NV_PDISP_SOR_DP_LINKCTL0_0_WRITE_MASK _MK_MASK_CONST(0x901f45fd) +#define SOR_NV_PDISP_SOR_DP_LINKCTL0_0_FORCE_IDLEPTTRN_SHIFT _MK_SHIFT_CONST(31) +#define SOR_NV_PDISP_SOR_DP_LINKCTL0_0_FORCE_IDLEPTTRN_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_DP_LINKCTL0_0_FORCE_IDLEPTTRN_SHIFT) +#define SOR_NV_PDISP_SOR_DP_LINKCTL0_0_FORCE_IDLEPTTRN_RANGE 31:31 +#define SOR_NV_PDISP_SOR_DP_LINKCTL0_0_FORCE_IDLEPTTRN_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_DP_LINKCTL0_0_FORCE_IDLEPTTRN_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_LINKCTL0_0_FORCE_IDLEPTTRN_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_DP_LINKCTL0_0_FORCE_IDLEPTTRN_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_LINKCTL0_0_FORCE_IDLEPTTRN_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_LINKCTL0_0_FORCE_IDLEPTTRN_INIT_ENUM NO +#define SOR_NV_PDISP_SOR_DP_LINKCTL0_0_FORCE_IDLEPTTRN_NO _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_DP_LINKCTL0_0_FORCE_IDLEPTTRN_YES _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_DP_LINKCTL0_0_COMPLIANCEPTTRN_SHIFT _MK_SHIFT_CONST(28) +#define SOR_NV_PDISP_SOR_DP_LINKCTL0_0_COMPLIANCEPTTRN_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_DP_LINKCTL0_0_COMPLIANCEPTTRN_SHIFT) +#define SOR_NV_PDISP_SOR_DP_LINKCTL0_0_COMPLIANCEPTTRN_RANGE 28:28 +#define SOR_NV_PDISP_SOR_DP_LINKCTL0_0_COMPLIANCEPTTRN_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_DP_LINKCTL0_0_COMPLIANCEPTTRN_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_LINKCTL0_0_COMPLIANCEPTTRN_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_DP_LINKCTL0_0_COMPLIANCEPTTRN_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_LINKCTL0_0_COMPLIANCEPTTRN_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_LINKCTL0_0_COMPLIANCEPTTRN_INIT_ENUM NOPATTERN +#define SOR_NV_PDISP_SOR_DP_LINKCTL0_0_COMPLIANCEPTTRN_NOPATTERN _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_DP_LINKCTL0_0_COMPLIANCEPTTRN_COLORSQARE _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_DP_LINKCTL0_0_LANECOUNT_SHIFT _MK_SHIFT_CONST(16) +#define SOR_NV_PDISP_SOR_DP_LINKCTL0_0_LANECOUNT_FIELD _MK_FIELD_CONST(0x1f, SOR_NV_PDISP_SOR_DP_LINKCTL0_0_LANECOUNT_SHIFT) +#define SOR_NV_PDISP_SOR_DP_LINKCTL0_0_LANECOUNT_RANGE 20:16 +#define SOR_NV_PDISP_SOR_DP_LINKCTL0_0_LANECOUNT_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_DP_LINKCTL0_0_LANECOUNT_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_LINKCTL0_0_LANECOUNT_DEFAULT_MASK _MK_MASK_CONST(0x1f) +#define SOR_NV_PDISP_SOR_DP_LINKCTL0_0_LANECOUNT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_LINKCTL0_0_LANECOUNT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_LINKCTL0_0_LANECOUNT_INIT_ENUM ZERO +#define SOR_NV_PDISP_SOR_DP_LINKCTL0_0_LANECOUNT_ZERO _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_DP_LINKCTL0_0_LANECOUNT_ONE _MK_ENUM_CONST(1) +#define SOR_NV_PDISP_SOR_DP_LINKCTL0_0_LANECOUNT_TWO _MK_ENUM_CONST(3) +#define SOR_NV_PDISP_SOR_DP_LINKCTL0_0_LANECOUNT_FOUR _MK_ENUM_CONST(15) + +#define SOR_NV_PDISP_SOR_DP_LINKCTL0_0_ENHANCEDFRAME_SHIFT _MK_SHIFT_CONST(14) +#define SOR_NV_PDISP_SOR_DP_LINKCTL0_0_ENHANCEDFRAME_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_DP_LINKCTL0_0_ENHANCEDFRAME_SHIFT) +#define SOR_NV_PDISP_SOR_DP_LINKCTL0_0_ENHANCEDFRAME_RANGE 14:14 +#define SOR_NV_PDISP_SOR_DP_LINKCTL0_0_ENHANCEDFRAME_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_DP_LINKCTL0_0_ENHANCEDFRAME_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_LINKCTL0_0_ENHANCEDFRAME_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_DP_LINKCTL0_0_ENHANCEDFRAME_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_LINKCTL0_0_ENHANCEDFRAME_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_LINKCTL0_0_ENHANCEDFRAME_INIT_ENUM DISABLE +#define SOR_NV_PDISP_SOR_DP_LINKCTL0_0_ENHANCEDFRAME_DISABLE _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_DP_LINKCTL0_0_ENHANCEDFRAME_ENABLE _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_DP_LINKCTL0_0_SYNCMODE_SHIFT _MK_SHIFT_CONST(10) +#define SOR_NV_PDISP_SOR_DP_LINKCTL0_0_SYNCMODE_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_DP_LINKCTL0_0_SYNCMODE_SHIFT) +#define SOR_NV_PDISP_SOR_DP_LINKCTL0_0_SYNCMODE_RANGE 10:10 +#define SOR_NV_PDISP_SOR_DP_LINKCTL0_0_SYNCMODE_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_DP_LINKCTL0_0_SYNCMODE_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_LINKCTL0_0_SYNCMODE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_DP_LINKCTL0_0_SYNCMODE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_LINKCTL0_0_SYNCMODE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_LINKCTL0_0_SYNCMODE_INIT_ENUM DISABLE +#define SOR_NV_PDISP_SOR_DP_LINKCTL0_0_SYNCMODE_DISABLE _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_DP_LINKCTL0_0_SYNCMODE_ENABLE _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_DP_LINKCTL0_0_TUSIZE_SHIFT _MK_SHIFT_CONST(2) +#define SOR_NV_PDISP_SOR_DP_LINKCTL0_0_TUSIZE_FIELD _MK_FIELD_CONST(0x7f, SOR_NV_PDISP_SOR_DP_LINKCTL0_0_TUSIZE_SHIFT) +#define SOR_NV_PDISP_SOR_DP_LINKCTL0_0_TUSIZE_RANGE 8:2 +#define SOR_NV_PDISP_SOR_DP_LINKCTL0_0_TUSIZE_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_DP_LINKCTL0_0_TUSIZE_DEFAULT _MK_MASK_CONST(0x40) +#define SOR_NV_PDISP_SOR_DP_LINKCTL0_0_TUSIZE_DEFAULT_MASK _MK_MASK_CONST(0x7f) +#define SOR_NV_PDISP_SOR_DP_LINKCTL0_0_TUSIZE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_LINKCTL0_0_TUSIZE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define SOR_NV_PDISP_SOR_DP_LINKCTL0_0_ENABLE_SHIFT _MK_SHIFT_CONST(0) +#define SOR_NV_PDISP_SOR_DP_LINKCTL0_0_ENABLE_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_DP_LINKCTL0_0_ENABLE_SHIFT) +#define SOR_NV_PDISP_SOR_DP_LINKCTL0_0_ENABLE_RANGE 0:0 +#define SOR_NV_PDISP_SOR_DP_LINKCTL0_0_ENABLE_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_DP_LINKCTL0_0_ENABLE_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_LINKCTL0_0_ENABLE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_DP_LINKCTL0_0_ENABLE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_LINKCTL0_0_ENABLE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_LINKCTL0_0_ENABLE_INIT_ENUM NO +#define SOR_NV_PDISP_SOR_DP_LINKCTL0_0_ENABLE_NO _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_DP_LINKCTL0_0_ENABLE_YES _MK_ENUM_CONST(1) + + +// Register SOR_NV_PDISP_SOR_DP_LINKCTL1_0 +#define SOR_NV_PDISP_SOR_DP_LINKCTL1_0 _MK_ADDR_CONST(0x4d) +#define SOR_NV_PDISP_SOR_DP_LINKCTL1_0_SECURE 0x0 +#define SOR_NV_PDISP_SOR_DP_LINKCTL1_0_WORD_COUNT 0x1 +#define SOR_NV_PDISP_SOR_DP_LINKCTL1_0_RESET_VAL _MK_MASK_CONST(0x100) +#define SOR_NV_PDISP_SOR_DP_LINKCTL1_0_RESET_MASK _MK_MASK_CONST(0x901f45fd) +#define SOR_NV_PDISP_SOR_DP_LINKCTL1_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_LINKCTL1_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_LINKCTL1_0_READ_MASK _MK_MASK_CONST(0x901f45fd) +#define SOR_NV_PDISP_SOR_DP_LINKCTL1_0_WRITE_MASK _MK_MASK_CONST(0x901f45fd) +#define SOR_NV_PDISP_SOR_DP_LINKCTL1_0_FORCE_IDLEPTTRN_SHIFT _MK_SHIFT_CONST(31) +#define SOR_NV_PDISP_SOR_DP_LINKCTL1_0_FORCE_IDLEPTTRN_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_DP_LINKCTL1_0_FORCE_IDLEPTTRN_SHIFT) +#define SOR_NV_PDISP_SOR_DP_LINKCTL1_0_FORCE_IDLEPTTRN_RANGE 31:31 +#define SOR_NV_PDISP_SOR_DP_LINKCTL1_0_FORCE_IDLEPTTRN_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_DP_LINKCTL1_0_FORCE_IDLEPTTRN_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_LINKCTL1_0_FORCE_IDLEPTTRN_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_DP_LINKCTL1_0_FORCE_IDLEPTTRN_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_LINKCTL1_0_FORCE_IDLEPTTRN_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_LINKCTL1_0_FORCE_IDLEPTTRN_INIT_ENUM NO +#define SOR_NV_PDISP_SOR_DP_LINKCTL1_0_FORCE_IDLEPTTRN_NO _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_DP_LINKCTL1_0_FORCE_IDLEPTTRN_YES _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_DP_LINKCTL1_0_COMPLIANCEPTTRN_SHIFT _MK_SHIFT_CONST(28) +#define SOR_NV_PDISP_SOR_DP_LINKCTL1_0_COMPLIANCEPTTRN_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_DP_LINKCTL1_0_COMPLIANCEPTTRN_SHIFT) +#define SOR_NV_PDISP_SOR_DP_LINKCTL1_0_COMPLIANCEPTTRN_RANGE 28:28 +#define SOR_NV_PDISP_SOR_DP_LINKCTL1_0_COMPLIANCEPTTRN_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_DP_LINKCTL1_0_COMPLIANCEPTTRN_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_LINKCTL1_0_COMPLIANCEPTTRN_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_DP_LINKCTL1_0_COMPLIANCEPTTRN_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_LINKCTL1_0_COMPLIANCEPTTRN_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_LINKCTL1_0_COMPLIANCEPTTRN_INIT_ENUM NOPATTERN +#define SOR_NV_PDISP_SOR_DP_LINKCTL1_0_COMPLIANCEPTTRN_NOPATTERN _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_DP_LINKCTL1_0_COMPLIANCEPTTRN_COLORSQARE _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_DP_LINKCTL1_0_LANECOUNT_SHIFT _MK_SHIFT_CONST(16) +#define SOR_NV_PDISP_SOR_DP_LINKCTL1_0_LANECOUNT_FIELD _MK_FIELD_CONST(0x1f, SOR_NV_PDISP_SOR_DP_LINKCTL1_0_LANECOUNT_SHIFT) +#define SOR_NV_PDISP_SOR_DP_LINKCTL1_0_LANECOUNT_RANGE 20:16 +#define SOR_NV_PDISP_SOR_DP_LINKCTL1_0_LANECOUNT_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_DP_LINKCTL1_0_LANECOUNT_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_LINKCTL1_0_LANECOUNT_DEFAULT_MASK _MK_MASK_CONST(0x1f) +#define SOR_NV_PDISP_SOR_DP_LINKCTL1_0_LANECOUNT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_LINKCTL1_0_LANECOUNT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_LINKCTL1_0_LANECOUNT_INIT_ENUM ZERO +#define SOR_NV_PDISP_SOR_DP_LINKCTL1_0_LANECOUNT_ZERO _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_DP_LINKCTL1_0_LANECOUNT_ONE _MK_ENUM_CONST(1) +#define SOR_NV_PDISP_SOR_DP_LINKCTL1_0_LANECOUNT_TWO _MK_ENUM_CONST(3) +#define SOR_NV_PDISP_SOR_DP_LINKCTL1_0_LANECOUNT_FOUR _MK_ENUM_CONST(15) + +#define SOR_NV_PDISP_SOR_DP_LINKCTL1_0_ENHANCEDFRAME_SHIFT _MK_SHIFT_CONST(14) +#define SOR_NV_PDISP_SOR_DP_LINKCTL1_0_ENHANCEDFRAME_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_DP_LINKCTL1_0_ENHANCEDFRAME_SHIFT) +#define SOR_NV_PDISP_SOR_DP_LINKCTL1_0_ENHANCEDFRAME_RANGE 14:14 +#define SOR_NV_PDISP_SOR_DP_LINKCTL1_0_ENHANCEDFRAME_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_DP_LINKCTL1_0_ENHANCEDFRAME_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_LINKCTL1_0_ENHANCEDFRAME_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_DP_LINKCTL1_0_ENHANCEDFRAME_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_LINKCTL1_0_ENHANCEDFRAME_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_LINKCTL1_0_ENHANCEDFRAME_INIT_ENUM DISABLE +#define SOR_NV_PDISP_SOR_DP_LINKCTL1_0_ENHANCEDFRAME_DISABLE _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_DP_LINKCTL1_0_ENHANCEDFRAME_ENABLE _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_DP_LINKCTL1_0_SYNCMODE_SHIFT _MK_SHIFT_CONST(10) +#define SOR_NV_PDISP_SOR_DP_LINKCTL1_0_SYNCMODE_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_DP_LINKCTL1_0_SYNCMODE_SHIFT) +#define SOR_NV_PDISP_SOR_DP_LINKCTL1_0_SYNCMODE_RANGE 10:10 +#define SOR_NV_PDISP_SOR_DP_LINKCTL1_0_SYNCMODE_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_DP_LINKCTL1_0_SYNCMODE_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_LINKCTL1_0_SYNCMODE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_DP_LINKCTL1_0_SYNCMODE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_LINKCTL1_0_SYNCMODE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_LINKCTL1_0_SYNCMODE_INIT_ENUM DISABLE +#define SOR_NV_PDISP_SOR_DP_LINKCTL1_0_SYNCMODE_DISABLE _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_DP_LINKCTL1_0_SYNCMODE_ENABLE _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_DP_LINKCTL1_0_TUSIZE_SHIFT _MK_SHIFT_CONST(2) +#define SOR_NV_PDISP_SOR_DP_LINKCTL1_0_TUSIZE_FIELD _MK_FIELD_CONST(0x7f, SOR_NV_PDISP_SOR_DP_LINKCTL1_0_TUSIZE_SHIFT) +#define SOR_NV_PDISP_SOR_DP_LINKCTL1_0_TUSIZE_RANGE 8:2 +#define SOR_NV_PDISP_SOR_DP_LINKCTL1_0_TUSIZE_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_DP_LINKCTL1_0_TUSIZE_DEFAULT _MK_MASK_CONST(0x40) +#define SOR_NV_PDISP_SOR_DP_LINKCTL1_0_TUSIZE_DEFAULT_MASK _MK_MASK_CONST(0x7f) +#define SOR_NV_PDISP_SOR_DP_LINKCTL1_0_TUSIZE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_LINKCTL1_0_TUSIZE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define SOR_NV_PDISP_SOR_DP_LINKCTL1_0_ENABLE_SHIFT _MK_SHIFT_CONST(0) +#define SOR_NV_PDISP_SOR_DP_LINKCTL1_0_ENABLE_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_DP_LINKCTL1_0_ENABLE_SHIFT) +#define SOR_NV_PDISP_SOR_DP_LINKCTL1_0_ENABLE_RANGE 0:0 +#define SOR_NV_PDISP_SOR_DP_LINKCTL1_0_ENABLE_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_DP_LINKCTL1_0_ENABLE_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_LINKCTL1_0_ENABLE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_DP_LINKCTL1_0_ENABLE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_LINKCTL1_0_ENABLE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_LINKCTL1_0_ENABLE_INIT_ENUM NO +#define SOR_NV_PDISP_SOR_DP_LINKCTL1_0_ENABLE_NO _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_DP_LINKCTL1_0_ENABLE_YES _MK_ENUM_CONST(1) + + +// Register SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT0_0 +#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT0_0 _MK_ADDR_CONST(0x4e) +#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT0_0_SECURE 0x0 +#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT0_0_WORD_COUNT 0x1 +#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT0_0_RESET_VAL _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT0_0_RESET_MASK _MK_MASK_CONST(0xffffffff) +#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT0_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT0_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT0_0_READ_MASK _MK_MASK_CONST(0xffffffff) +#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT0_0_WRITE_MASK _MK_MASK_CONST(0xffffffff) +#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT0_0_LANE3_DP_LANE3_SHIFT _MK_SHIFT_CONST(24) +#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT0_0_LANE3_DP_LANE3_FIELD _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT0_0_LANE3_DP_LANE3_SHIFT) +#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT0_0_LANE3_DP_LANE3_RANGE 31:24 +#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT0_0_LANE3_DP_LANE3_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT0_0_LANE3_DP_LANE3_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT0_0_LANE3_DP_LANE3_DEFAULT_MASK _MK_MASK_CONST(0xff) +#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT0_0_LANE3_DP_LANE3_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT0_0_LANE3_DP_LANE3_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT0_0_LANE3_DP_LANE3_P0_LEVEL0 _MK_ENUM_CONST(17) +#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT0_0_LANE3_DP_LANE3_P1_LEVEL0 _MK_ENUM_CONST(21) +#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT0_0_LANE3_DP_LANE3_P2_LEVEL0 _MK_ENUM_CONST(26) +#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT0_0_LANE3_DP_LANE3_P3_LEVEL0 _MK_ENUM_CONST(34) +#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT0_0_LANE3_DP_LANE3_P0_LEVEL1 _MK_ENUM_CONST(26) +#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT0_0_LANE3_DP_LANE3_P1_LEVEL1 _MK_ENUM_CONST(32) +#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT0_0_LANE3_DP_LANE3_P2_LEVEL1 _MK_ENUM_CONST(39) +#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT0_0_LANE3_DP_LANE3_P0_LEVEL2 _MK_ENUM_CONST(34) +#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT0_0_LANE3_DP_LANE3_P1_LEVEL2 _MK_ENUM_CONST(43) +#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT0_0_LANE3_DP_LANE3_P0_LEVEL3 _MK_ENUM_CONST(51) + +#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT0_0_LANE2_DP_LANE0_SHIFT _MK_SHIFT_CONST(16) +#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT0_0_LANE2_DP_LANE0_FIELD _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT0_0_LANE2_DP_LANE0_SHIFT) +#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT0_0_LANE2_DP_LANE0_RANGE 23:16 +#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT0_0_LANE2_DP_LANE0_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT0_0_LANE2_DP_LANE0_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT0_0_LANE2_DP_LANE0_DEFAULT_MASK _MK_MASK_CONST(0xff) +#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT0_0_LANE2_DP_LANE0_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT0_0_LANE2_DP_LANE0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT0_0_LANE2_DP_LANE0_P0_LEVEL0 _MK_ENUM_CONST(17) +#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT0_0_LANE2_DP_LANE0_P1_LEVEL0 _MK_ENUM_CONST(21) +#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT0_0_LANE2_DP_LANE0_P2_LEVEL0 _MK_ENUM_CONST(26) +#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT0_0_LANE2_DP_LANE0_P3_LEVEL0 _MK_ENUM_CONST(34) +#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT0_0_LANE2_DP_LANE0_P0_LEVEL1 _MK_ENUM_CONST(26) +#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT0_0_LANE2_DP_LANE0_P1_LEVEL1 _MK_ENUM_CONST(32) +#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT0_0_LANE2_DP_LANE0_P2_LEVEL1 _MK_ENUM_CONST(39) +#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT0_0_LANE2_DP_LANE0_P0_LEVEL2 _MK_ENUM_CONST(34) +#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT0_0_LANE2_DP_LANE0_P1_LEVEL2 _MK_ENUM_CONST(43) +#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT0_0_LANE2_DP_LANE0_P0_LEVEL3 _MK_ENUM_CONST(51) + +#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT0_0_LANE1_DP_LANE1_SHIFT _MK_SHIFT_CONST(8) +#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT0_0_LANE1_DP_LANE1_FIELD _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT0_0_LANE1_DP_LANE1_SHIFT) +#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT0_0_LANE1_DP_LANE1_RANGE 15:8 +#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT0_0_LANE1_DP_LANE1_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT0_0_LANE1_DP_LANE1_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT0_0_LANE1_DP_LANE1_DEFAULT_MASK _MK_MASK_CONST(0xff) +#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT0_0_LANE1_DP_LANE1_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT0_0_LANE1_DP_LANE1_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT0_0_LANE1_DP_LANE1_P0_LEVEL0 _MK_ENUM_CONST(17) +#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT0_0_LANE1_DP_LANE1_P1_LEVEL0 _MK_ENUM_CONST(21) +#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT0_0_LANE1_DP_LANE1_P2_LEVEL0 _MK_ENUM_CONST(26) +#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT0_0_LANE1_DP_LANE1_P3_LEVEL0 _MK_ENUM_CONST(34) +#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT0_0_LANE1_DP_LANE1_P0_LEVEL1 _MK_ENUM_CONST(26) +#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT0_0_LANE1_DP_LANE1_P1_LEVEL1 _MK_ENUM_CONST(32) +#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT0_0_LANE1_DP_LANE1_P2_LEVEL1 _MK_ENUM_CONST(39) +#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT0_0_LANE1_DP_LANE1_P0_LEVEL2 _MK_ENUM_CONST(34) +#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT0_0_LANE1_DP_LANE1_P1_LEVEL2 _MK_ENUM_CONST(43) +#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT0_0_LANE1_DP_LANE1_P0_LEVEL3 _MK_ENUM_CONST(51) + +#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT0_0_LANE0_DP_LANE2_SHIFT _MK_SHIFT_CONST(0) +#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT0_0_LANE0_DP_LANE2_FIELD _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT0_0_LANE0_DP_LANE2_SHIFT) +#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT0_0_LANE0_DP_LANE2_RANGE 7:0 +#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT0_0_LANE0_DP_LANE2_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT0_0_LANE0_DP_LANE2_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT0_0_LANE0_DP_LANE2_DEFAULT_MASK _MK_MASK_CONST(0xff) +#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT0_0_LANE0_DP_LANE2_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT0_0_LANE0_DP_LANE2_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT0_0_LANE0_DP_LANE2_P0_LEVEL0 _MK_ENUM_CONST(17) +#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT0_0_LANE0_DP_LANE2_P1_LEVEL0 _MK_ENUM_CONST(21) +#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT0_0_LANE0_DP_LANE2_P2_LEVEL0 _MK_ENUM_CONST(26) +#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT0_0_LANE0_DP_LANE2_P3_LEVEL0 _MK_ENUM_CONST(34) +#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT0_0_LANE0_DP_LANE2_P0_LEVEL1 _MK_ENUM_CONST(26) +#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT0_0_LANE0_DP_LANE2_P1_LEVEL1 _MK_ENUM_CONST(32) +#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT0_0_LANE0_DP_LANE2_P2_LEVEL1 _MK_ENUM_CONST(39) +#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT0_0_LANE0_DP_LANE2_P0_LEVEL2 _MK_ENUM_CONST(34) +#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT0_0_LANE0_DP_LANE2_P1_LEVEL2 _MK_ENUM_CONST(43) +#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT0_0_LANE0_DP_LANE2_P0_LEVEL3 _MK_ENUM_CONST(51) + + +// Register SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT1_0 +#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT1_0 _MK_ADDR_CONST(0x4f) +#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT1_0_SECURE 0x0 +#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT1_0_WORD_COUNT 0x1 +#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT1_0_RESET_VAL _MK_MASK_CONST(0x80808080) +#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT1_0_RESET_MASK _MK_MASK_CONST(0xffffffff) +#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT1_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT1_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT1_0_READ_MASK _MK_MASK_CONST(0xffffffff) +#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT1_0_WRITE_MASK _MK_MASK_CONST(0xffffffff) +#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT1_0_LANE3_DP_LANE3_SHIFT _MK_SHIFT_CONST(24) +#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT1_0_LANE3_DP_LANE3_FIELD _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT1_0_LANE3_DP_LANE3_SHIFT) +#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT1_0_LANE3_DP_LANE3_RANGE 31:24 +#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT1_0_LANE3_DP_LANE3_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT1_0_LANE3_DP_LANE3_DEFAULT _MK_MASK_CONST(0x80) +#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT1_0_LANE3_DP_LANE3_DEFAULT_MASK _MK_MASK_CONST(0xff) +#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT1_0_LANE3_DP_LANE3_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT1_0_LANE3_DP_LANE3_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT1_0_LANE3_DP_LANE3_P0_LEVEL0 _MK_ENUM_CONST(17) +#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT1_0_LANE3_DP_LANE3_P1_LEVEL0 _MK_ENUM_CONST(21) +#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT1_0_LANE3_DP_LANE3_P2_LEVEL0 _MK_ENUM_CONST(26) +#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT1_0_LANE3_DP_LANE3_P3_LEVEL0 _MK_ENUM_CONST(34) +#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT1_0_LANE3_DP_LANE3_P0_LEVEL1 _MK_ENUM_CONST(26) +#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT1_0_LANE3_DP_LANE3_P1_LEVEL1 _MK_ENUM_CONST(32) +#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT1_0_LANE3_DP_LANE3_P2_LEVEL1 _MK_ENUM_CONST(39) +#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT1_0_LANE3_DP_LANE3_P0_LEVEL2 _MK_ENUM_CONST(34) +#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT1_0_LANE3_DP_LANE3_P1_LEVEL2 _MK_ENUM_CONST(43) +#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT1_0_LANE3_DP_LANE3_P0_LEVEL3 _MK_ENUM_CONST(51) + +#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT1_0_LANE2_DP_LANE0_SHIFT _MK_SHIFT_CONST(16) +#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT1_0_LANE2_DP_LANE0_FIELD _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT1_0_LANE2_DP_LANE0_SHIFT) +#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT1_0_LANE2_DP_LANE0_RANGE 23:16 +#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT1_0_LANE2_DP_LANE0_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT1_0_LANE2_DP_LANE0_DEFAULT _MK_MASK_CONST(0x80) +#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT1_0_LANE2_DP_LANE0_DEFAULT_MASK _MK_MASK_CONST(0xff) +#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT1_0_LANE2_DP_LANE0_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT1_0_LANE2_DP_LANE0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT1_0_LANE2_DP_LANE0_P0_LEVEL0 _MK_ENUM_CONST(17) +#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT1_0_LANE2_DP_LANE0_P1_LEVEL0 _MK_ENUM_CONST(21) +#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT1_0_LANE2_DP_LANE0_P2_LEVEL0 _MK_ENUM_CONST(26) +#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT1_0_LANE2_DP_LANE0_P3_LEVEL0 _MK_ENUM_CONST(34) +#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT1_0_LANE2_DP_LANE0_P0_LEVEL1 _MK_ENUM_CONST(26) +#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT1_0_LANE2_DP_LANE0_P1_LEVEL1 _MK_ENUM_CONST(32) +#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT1_0_LANE2_DP_LANE0_P2_LEVEL1 _MK_ENUM_CONST(39) +#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT1_0_LANE2_DP_LANE0_P0_LEVEL2 _MK_ENUM_CONST(34) +#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT1_0_LANE2_DP_LANE0_P1_LEVEL2 _MK_ENUM_CONST(43) +#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT1_0_LANE2_DP_LANE0_P0_LEVEL3 _MK_ENUM_CONST(51) + +#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT1_0_LANE1_DP_LANE1_SHIFT _MK_SHIFT_CONST(8) +#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT1_0_LANE1_DP_LANE1_FIELD _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT1_0_LANE1_DP_LANE1_SHIFT) +#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT1_0_LANE1_DP_LANE1_RANGE 15:8 +#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT1_0_LANE1_DP_LANE1_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT1_0_LANE1_DP_LANE1_DEFAULT _MK_MASK_CONST(0x80) +#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT1_0_LANE1_DP_LANE1_DEFAULT_MASK _MK_MASK_CONST(0xff) +#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT1_0_LANE1_DP_LANE1_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT1_0_LANE1_DP_LANE1_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT1_0_LANE1_DP_LANE1_P0_LEVEL0 _MK_ENUM_CONST(17) +#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT1_0_LANE1_DP_LANE1_P1_LEVEL0 _MK_ENUM_CONST(21) +#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT1_0_LANE1_DP_LANE1_P2_LEVEL0 _MK_ENUM_CONST(26) +#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT1_0_LANE1_DP_LANE1_P3_LEVEL0 _MK_ENUM_CONST(34) +#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT1_0_LANE1_DP_LANE1_P0_LEVEL1 _MK_ENUM_CONST(26) +#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT1_0_LANE1_DP_LANE1_P1_LEVEL1 _MK_ENUM_CONST(32) +#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT1_0_LANE1_DP_LANE1_P2_LEVEL1 _MK_ENUM_CONST(39) +#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT1_0_LANE1_DP_LANE1_P0_LEVEL2 _MK_ENUM_CONST(34) +#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT1_0_LANE1_DP_LANE1_P1_LEVEL2 _MK_ENUM_CONST(43) +#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT1_0_LANE1_DP_LANE1_P0_LEVEL3 _MK_ENUM_CONST(51) + +#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT1_0_LANE0_DP_LANE2_SHIFT _MK_SHIFT_CONST(0) +#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT1_0_LANE0_DP_LANE2_FIELD _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT1_0_LANE0_DP_LANE2_SHIFT) +#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT1_0_LANE0_DP_LANE2_RANGE 7:0 +#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT1_0_LANE0_DP_LANE2_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT1_0_LANE0_DP_LANE2_DEFAULT _MK_MASK_CONST(0x80) +#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT1_0_LANE0_DP_LANE2_DEFAULT_MASK _MK_MASK_CONST(0xff) +#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT1_0_LANE0_DP_LANE2_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT1_0_LANE0_DP_LANE2_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT1_0_LANE0_DP_LANE2_P0_LEVEL0 _MK_ENUM_CONST(17) +#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT1_0_LANE0_DP_LANE2_P1_LEVEL0 _MK_ENUM_CONST(21) +#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT1_0_LANE0_DP_LANE2_P2_LEVEL0 _MK_ENUM_CONST(26) +#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT1_0_LANE0_DP_LANE2_P3_LEVEL0 _MK_ENUM_CONST(34) +#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT1_0_LANE0_DP_LANE2_P0_LEVEL1 _MK_ENUM_CONST(26) +#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT1_0_LANE0_DP_LANE2_P1_LEVEL1 _MK_ENUM_CONST(32) +#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT1_0_LANE0_DP_LANE2_P2_LEVEL1 _MK_ENUM_CONST(39) +#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT1_0_LANE0_DP_LANE2_P0_LEVEL2 _MK_ENUM_CONST(34) +#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT1_0_LANE0_DP_LANE2_P1_LEVEL2 _MK_ENUM_CONST(43) +#define SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT1_0_LANE0_DP_LANE2_P0_LEVEL3 _MK_ENUM_CONST(51) + + +// Register SOR_NV_PDISP_SOR_LANE4_DRIVE_CURRENT0_0 +#define SOR_NV_PDISP_SOR_LANE4_DRIVE_CURRENT0_0 _MK_ADDR_CONST(0x50) +#define SOR_NV_PDISP_SOR_LANE4_DRIVE_CURRENT0_0_SECURE 0x0 +#define SOR_NV_PDISP_SOR_LANE4_DRIVE_CURRENT0_0_WORD_COUNT 0x1 +#define SOR_NV_PDISP_SOR_LANE4_DRIVE_CURRENT0_0_RESET_VAL _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_LANE4_DRIVE_CURRENT0_0_RESET_MASK _MK_MASK_CONST(0xff) +#define SOR_NV_PDISP_SOR_LANE4_DRIVE_CURRENT0_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_LANE4_DRIVE_CURRENT0_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_LANE4_DRIVE_CURRENT0_0_READ_MASK _MK_MASK_CONST(0xff) +#define SOR_NV_PDISP_SOR_LANE4_DRIVE_CURRENT0_0_WRITE_MASK _MK_MASK_CONST(0xff) +#define SOR_NV_PDISP_SOR_LANE4_DRIVE_CURRENT0_0_LANE4_SHIFT _MK_SHIFT_CONST(0) +#define SOR_NV_PDISP_SOR_LANE4_DRIVE_CURRENT0_0_LANE4_FIELD _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_LANE4_DRIVE_CURRENT0_0_LANE4_SHIFT) +#define SOR_NV_PDISP_SOR_LANE4_DRIVE_CURRENT0_0_LANE4_RANGE 7:0 +#define SOR_NV_PDISP_SOR_LANE4_DRIVE_CURRENT0_0_LANE4_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_LANE4_DRIVE_CURRENT0_0_LANE4_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_LANE4_DRIVE_CURRENT0_0_LANE4_DEFAULT_MASK _MK_MASK_CONST(0xff) +#define SOR_NV_PDISP_SOR_LANE4_DRIVE_CURRENT0_0_LANE4_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_LANE4_DRIVE_CURRENT0_0_LANE4_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register SOR_NV_PDISP_SOR_LANE4_DRIVE_CURRENT1_0 +#define SOR_NV_PDISP_SOR_LANE4_DRIVE_CURRENT1_0 _MK_ADDR_CONST(0x51) +#define SOR_NV_PDISP_SOR_LANE4_DRIVE_CURRENT1_0_SECURE 0x0 +#define SOR_NV_PDISP_SOR_LANE4_DRIVE_CURRENT1_0_WORD_COUNT 0x1 +#define SOR_NV_PDISP_SOR_LANE4_DRIVE_CURRENT1_0_RESET_VAL _MK_MASK_CONST(0x80) +#define SOR_NV_PDISP_SOR_LANE4_DRIVE_CURRENT1_0_RESET_MASK _MK_MASK_CONST(0xff) +#define SOR_NV_PDISP_SOR_LANE4_DRIVE_CURRENT1_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_LANE4_DRIVE_CURRENT1_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_LANE4_DRIVE_CURRENT1_0_READ_MASK _MK_MASK_CONST(0xff) +#define SOR_NV_PDISP_SOR_LANE4_DRIVE_CURRENT1_0_WRITE_MASK _MK_MASK_CONST(0xff) +#define SOR_NV_PDISP_SOR_LANE4_DRIVE_CURRENT1_0_LANE4_SHIFT _MK_SHIFT_CONST(0) +#define SOR_NV_PDISP_SOR_LANE4_DRIVE_CURRENT1_0_LANE4_FIELD _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_LANE4_DRIVE_CURRENT1_0_LANE4_SHIFT) +#define SOR_NV_PDISP_SOR_LANE4_DRIVE_CURRENT1_0_LANE4_RANGE 7:0 +#define SOR_NV_PDISP_SOR_LANE4_DRIVE_CURRENT1_0_LANE4_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_LANE4_DRIVE_CURRENT1_0_LANE4_DEFAULT _MK_MASK_CONST(0x80) +#define SOR_NV_PDISP_SOR_LANE4_DRIVE_CURRENT1_0_LANE4_DEFAULT_MASK _MK_MASK_CONST(0xff) +#define SOR_NV_PDISP_SOR_LANE4_DRIVE_CURRENT1_0_LANE4_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_LANE4_DRIVE_CURRENT1_0_LANE4_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register SOR_NV_PDISP_SOR_LANE_PREEMPHASIS0_0 +#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS0_0 _MK_ADDR_CONST(0x52) +#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS0_0_SECURE 0x0 +#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS0_0_WORD_COUNT 0x1 +#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS0_0_RESET_VAL _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS0_0_RESET_MASK _MK_MASK_CONST(0xffffffff) +#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS0_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS0_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS0_0_READ_MASK _MK_MASK_CONST(0xffffffff) +#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS0_0_WRITE_MASK _MK_MASK_CONST(0xffffffff) +#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS0_0_LANE3_DP_LANE3_SHIFT _MK_SHIFT_CONST(24) +#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS0_0_LANE3_DP_LANE3_FIELD _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_LANE_PREEMPHASIS0_0_LANE3_DP_LANE3_SHIFT) +#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS0_0_LANE3_DP_LANE3_RANGE 31:24 +#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS0_0_LANE3_DP_LANE3_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS0_0_LANE3_DP_LANE3_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS0_0_LANE3_DP_LANE3_DEFAULT_MASK _MK_MASK_CONST(0xff) +#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS0_0_LANE3_DP_LANE3_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS0_0_LANE3_DP_LANE3_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS0_0_LANE3_DP_LANE3_D0_LEVEL0 _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS0_0_LANE3_DP_LANE3_D1_LEVEL0 _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS0_0_LANE3_DP_LANE3_D2_LEVEL0 _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS0_0_LANE3_DP_LANE3_D3_LEVEL0 _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS0_0_LANE3_DP_LANE3_D0_LEVEL1 _MK_ENUM_CONST(4) +#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS0_0_LANE3_DP_LANE3_D1_LEVEL1 _MK_ENUM_CONST(6) +#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS0_0_LANE3_DP_LANE3_D2_LEVEL1 _MK_ENUM_CONST(17) +#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS0_0_LANE3_DP_LANE3_D0_LEVEL2 _MK_ENUM_CONST(8) +#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS0_0_LANE3_DP_LANE3_D1_LEVEL2 _MK_ENUM_CONST(13) +#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS0_0_LANE3_DP_LANE3_D0_LEVEL3 _MK_ENUM_CONST(17) + +#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS0_0_LANE2_DP_LANE0_SHIFT _MK_SHIFT_CONST(16) +#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS0_0_LANE2_DP_LANE0_FIELD _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_LANE_PREEMPHASIS0_0_LANE2_DP_LANE0_SHIFT) +#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS0_0_LANE2_DP_LANE0_RANGE 23:16 +#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS0_0_LANE2_DP_LANE0_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS0_0_LANE2_DP_LANE0_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS0_0_LANE2_DP_LANE0_DEFAULT_MASK _MK_MASK_CONST(0xff) +#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS0_0_LANE2_DP_LANE0_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS0_0_LANE2_DP_LANE0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS0_0_LANE2_DP_LANE0_D0_LEVEL0 _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS0_0_LANE2_DP_LANE0_D1_LEVEL0 _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS0_0_LANE2_DP_LANE0_D2_LEVEL0 _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS0_0_LANE2_DP_LANE0_D3_LEVEL0 _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS0_0_LANE2_DP_LANE0_D0_LEVEL1 _MK_ENUM_CONST(4) +#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS0_0_LANE2_DP_LANE0_D1_LEVEL1 _MK_ENUM_CONST(6) +#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS0_0_LANE2_DP_LANE0_D2_LEVEL1 _MK_ENUM_CONST(17) +#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS0_0_LANE2_DP_LANE0_D0_LEVEL2 _MK_ENUM_CONST(8) +#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS0_0_LANE2_DP_LANE0_D1_LEVEL2 _MK_ENUM_CONST(13) +#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS0_0_LANE2_DP_LANE0_D0_LEVEL3 _MK_ENUM_CONST(17) + +#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS0_0_LANE1_DP_LANE1_SHIFT _MK_SHIFT_CONST(8) +#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS0_0_LANE1_DP_LANE1_FIELD _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_LANE_PREEMPHASIS0_0_LANE1_DP_LANE1_SHIFT) +#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS0_0_LANE1_DP_LANE1_RANGE 15:8 +#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS0_0_LANE1_DP_LANE1_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS0_0_LANE1_DP_LANE1_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS0_0_LANE1_DP_LANE1_DEFAULT_MASK _MK_MASK_CONST(0xff) +#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS0_0_LANE1_DP_LANE1_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS0_0_LANE1_DP_LANE1_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS0_0_LANE1_DP_LANE1_D0_LEVEL0 _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS0_0_LANE1_DP_LANE1_D1_LEVEL0 _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS0_0_LANE1_DP_LANE1_D2_LEVEL0 _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS0_0_LANE1_DP_LANE1_D3_LEVEL0 _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS0_0_LANE1_DP_LANE1_D0_LEVEL1 _MK_ENUM_CONST(4) +#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS0_0_LANE1_DP_LANE1_D1_LEVEL1 _MK_ENUM_CONST(6) +#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS0_0_LANE1_DP_LANE1_D2_LEVEL1 _MK_ENUM_CONST(17) +#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS0_0_LANE1_DP_LANE1_D0_LEVEL2 _MK_ENUM_CONST(8) +#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS0_0_LANE1_DP_LANE1_D1_LEVEL2 _MK_ENUM_CONST(13) +#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS0_0_LANE1_DP_LANE1_D0_LEVEL3 _MK_ENUM_CONST(17) + +#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS0_0_LANE0_DP_LANE2_SHIFT _MK_SHIFT_CONST(0) +#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS0_0_LANE0_DP_LANE2_FIELD _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_LANE_PREEMPHASIS0_0_LANE0_DP_LANE2_SHIFT) +#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS0_0_LANE0_DP_LANE2_RANGE 7:0 +#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS0_0_LANE0_DP_LANE2_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS0_0_LANE0_DP_LANE2_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS0_0_LANE0_DP_LANE2_DEFAULT_MASK _MK_MASK_CONST(0xff) +#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS0_0_LANE0_DP_LANE2_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS0_0_LANE0_DP_LANE2_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS0_0_LANE0_DP_LANE2_D0_LEVEL0 _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS0_0_LANE0_DP_LANE2_D1_LEVEL0 _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS0_0_LANE0_DP_LANE2_D2_LEVEL0 _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS0_0_LANE0_DP_LANE2_D3_LEVEL0 _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS0_0_LANE0_DP_LANE2_D0_LEVEL1 _MK_ENUM_CONST(4) +#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS0_0_LANE0_DP_LANE2_D1_LEVEL1 _MK_ENUM_CONST(6) +#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS0_0_LANE0_DP_LANE2_D2_LEVEL1 _MK_ENUM_CONST(17) +#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS0_0_LANE0_DP_LANE2_D0_LEVEL2 _MK_ENUM_CONST(8) +#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS0_0_LANE0_DP_LANE2_D1_LEVEL2 _MK_ENUM_CONST(13) +#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS0_0_LANE0_DP_LANE2_D0_LEVEL3 _MK_ENUM_CONST(17) + + +// Register SOR_NV_PDISP_SOR_LANE_PREEMPHASIS1_0 +#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS1_0 _MK_ADDR_CONST(0x53) +#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS1_0_SECURE 0x0 +#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS1_0_WORD_COUNT 0x1 +#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS1_0_RESET_VAL _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS1_0_RESET_MASK _MK_MASK_CONST(0xffffffff) +#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS1_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS1_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS1_0_READ_MASK _MK_MASK_CONST(0xffffffff) +#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS1_0_WRITE_MASK _MK_MASK_CONST(0xffffffff) +#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS1_0_LANE3_DP_LANE3_SHIFT _MK_SHIFT_CONST(24) +#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS1_0_LANE3_DP_LANE3_FIELD _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_LANE_PREEMPHASIS1_0_LANE3_DP_LANE3_SHIFT) +#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS1_0_LANE3_DP_LANE3_RANGE 31:24 +#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS1_0_LANE3_DP_LANE3_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS1_0_LANE3_DP_LANE3_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS1_0_LANE3_DP_LANE3_DEFAULT_MASK _MK_MASK_CONST(0xff) +#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS1_0_LANE3_DP_LANE3_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS1_0_LANE3_DP_LANE3_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS1_0_LANE3_DP_LANE3_D0_LEVEL0 _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS1_0_LANE3_DP_LANE3_D1_LEVEL0 _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS1_0_LANE3_DP_LANE3_D2_LEVEL0 _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS1_0_LANE3_DP_LANE3_D3_LEVEL0 _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS1_0_LANE3_DP_LANE3_D0_LEVEL1 _MK_ENUM_CONST(4) +#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS1_0_LANE3_DP_LANE3_D1_LEVEL1 _MK_ENUM_CONST(6) +#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS1_0_LANE3_DP_LANE3_D2_LEVEL1 _MK_ENUM_CONST(17) +#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS1_0_LANE3_DP_LANE3_D0_LEVEL2 _MK_ENUM_CONST(8) +#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS1_0_LANE3_DP_LANE3_D1_LEVEL2 _MK_ENUM_CONST(13) +#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS1_0_LANE3_DP_LANE3_D0_LEVEL3 _MK_ENUM_CONST(17) + +#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS1_0_LANE2_DP_LANE0_SHIFT _MK_SHIFT_CONST(16) +#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS1_0_LANE2_DP_LANE0_FIELD _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_LANE_PREEMPHASIS1_0_LANE2_DP_LANE0_SHIFT) +#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS1_0_LANE2_DP_LANE0_RANGE 23:16 +#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS1_0_LANE2_DP_LANE0_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS1_0_LANE2_DP_LANE0_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS1_0_LANE2_DP_LANE0_DEFAULT_MASK _MK_MASK_CONST(0xff) +#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS1_0_LANE2_DP_LANE0_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS1_0_LANE2_DP_LANE0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS1_0_LANE2_DP_LANE0_D0_LEVEL0 _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS1_0_LANE2_DP_LANE0_D1_LEVEL0 _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS1_0_LANE2_DP_LANE0_D2_LEVEL0 _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS1_0_LANE2_DP_LANE0_D3_LEVEL0 _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS1_0_LANE2_DP_LANE0_D0_LEVEL1 _MK_ENUM_CONST(4) +#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS1_0_LANE2_DP_LANE0_D1_LEVEL1 _MK_ENUM_CONST(6) +#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS1_0_LANE2_DP_LANE0_D2_LEVEL1 _MK_ENUM_CONST(17) +#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS1_0_LANE2_DP_LANE0_D0_LEVEL2 _MK_ENUM_CONST(8) +#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS1_0_LANE2_DP_LANE0_D1_LEVEL2 _MK_ENUM_CONST(13) +#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS1_0_LANE2_DP_LANE0_D0_LEVEL3 _MK_ENUM_CONST(17) + +#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS1_0_LANE1_DP_LANE1_SHIFT _MK_SHIFT_CONST(8) +#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS1_0_LANE1_DP_LANE1_FIELD _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_LANE_PREEMPHASIS1_0_LANE1_DP_LANE1_SHIFT) +#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS1_0_LANE1_DP_LANE1_RANGE 15:8 +#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS1_0_LANE1_DP_LANE1_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS1_0_LANE1_DP_LANE1_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS1_0_LANE1_DP_LANE1_DEFAULT_MASK _MK_MASK_CONST(0xff) +#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS1_0_LANE1_DP_LANE1_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS1_0_LANE1_DP_LANE1_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS1_0_LANE1_DP_LANE1_D0_LEVEL0 _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS1_0_LANE1_DP_LANE1_D1_LEVEL0 _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS1_0_LANE1_DP_LANE1_D2_LEVEL0 _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS1_0_LANE1_DP_LANE1_D3_LEVEL0 _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS1_0_LANE1_DP_LANE1_D0_LEVEL1 _MK_ENUM_CONST(4) +#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS1_0_LANE1_DP_LANE1_D1_LEVEL1 _MK_ENUM_CONST(6) +#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS1_0_LANE1_DP_LANE1_D2_LEVEL1 _MK_ENUM_CONST(17) +#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS1_0_LANE1_DP_LANE1_D0_LEVEL2 _MK_ENUM_CONST(8) +#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS1_0_LANE1_DP_LANE1_D1_LEVEL2 _MK_ENUM_CONST(13) +#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS1_0_LANE1_DP_LANE1_D0_LEVEL3 _MK_ENUM_CONST(17) + +#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS1_0_LANE0_DP_LANE2_SHIFT _MK_SHIFT_CONST(0) +#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS1_0_LANE0_DP_LANE2_FIELD _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_LANE_PREEMPHASIS1_0_LANE0_DP_LANE2_SHIFT) +#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS1_0_LANE0_DP_LANE2_RANGE 7:0 +#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS1_0_LANE0_DP_LANE2_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS1_0_LANE0_DP_LANE2_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS1_0_LANE0_DP_LANE2_DEFAULT_MASK _MK_MASK_CONST(0xff) +#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS1_0_LANE0_DP_LANE2_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS1_0_LANE0_DP_LANE2_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS1_0_LANE0_DP_LANE2_D0_LEVEL0 _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS1_0_LANE0_DP_LANE2_D1_LEVEL0 _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS1_0_LANE0_DP_LANE2_D2_LEVEL0 _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS1_0_LANE0_DP_LANE2_D3_LEVEL0 _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS1_0_LANE0_DP_LANE2_D0_LEVEL1 _MK_ENUM_CONST(4) +#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS1_0_LANE0_DP_LANE2_D1_LEVEL1 _MK_ENUM_CONST(6) +#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS1_0_LANE0_DP_LANE2_D2_LEVEL1 _MK_ENUM_CONST(17) +#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS1_0_LANE0_DP_LANE2_D0_LEVEL2 _MK_ENUM_CONST(8) +#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS1_0_LANE0_DP_LANE2_D1_LEVEL2 _MK_ENUM_CONST(13) +#define SOR_NV_PDISP_SOR_LANE_PREEMPHASIS1_0_LANE0_DP_LANE2_D0_LEVEL3 _MK_ENUM_CONST(17) + + +// Register SOR_NV_PDISP_SOR_LANE4_PREEMPHASIS0_0 +#define SOR_NV_PDISP_SOR_LANE4_PREEMPHASIS0_0 _MK_ADDR_CONST(0x54) +#define SOR_NV_PDISP_SOR_LANE4_PREEMPHASIS0_0_SECURE 0x0 +#define SOR_NV_PDISP_SOR_LANE4_PREEMPHASIS0_0_WORD_COUNT 0x1 +#define SOR_NV_PDISP_SOR_LANE4_PREEMPHASIS0_0_RESET_VAL _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_LANE4_PREEMPHASIS0_0_RESET_MASK _MK_MASK_CONST(0xff) +#define SOR_NV_PDISP_SOR_LANE4_PREEMPHASIS0_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_LANE4_PREEMPHASIS0_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_LANE4_PREEMPHASIS0_0_READ_MASK _MK_MASK_CONST(0xff) +#define SOR_NV_PDISP_SOR_LANE4_PREEMPHASIS0_0_WRITE_MASK _MK_MASK_CONST(0xff) +#define SOR_NV_PDISP_SOR_LANE4_PREEMPHASIS0_0_LANE4_SHIFT _MK_SHIFT_CONST(0) +#define SOR_NV_PDISP_SOR_LANE4_PREEMPHASIS0_0_LANE4_FIELD _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_LANE4_PREEMPHASIS0_0_LANE4_SHIFT) +#define SOR_NV_PDISP_SOR_LANE4_PREEMPHASIS0_0_LANE4_RANGE 7:0 +#define SOR_NV_PDISP_SOR_LANE4_PREEMPHASIS0_0_LANE4_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_LANE4_PREEMPHASIS0_0_LANE4_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_LANE4_PREEMPHASIS0_0_LANE4_DEFAULT_MASK _MK_MASK_CONST(0xff) +#define SOR_NV_PDISP_SOR_LANE4_PREEMPHASIS0_0_LANE4_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_LANE4_PREEMPHASIS0_0_LANE4_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register SOR_NV_PDISP_SOR_LANE4_PREEMPHASIS1_0 +#define SOR_NV_PDISP_SOR_LANE4_PREEMPHASIS1_0 _MK_ADDR_CONST(0x55) +#define SOR_NV_PDISP_SOR_LANE4_PREEMPHASIS1_0_SECURE 0x0 +#define SOR_NV_PDISP_SOR_LANE4_PREEMPHASIS1_0_WORD_COUNT 0x1 +#define SOR_NV_PDISP_SOR_LANE4_PREEMPHASIS1_0_RESET_VAL _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_LANE4_PREEMPHASIS1_0_RESET_MASK _MK_MASK_CONST(0xff) +#define SOR_NV_PDISP_SOR_LANE4_PREEMPHASIS1_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_LANE4_PREEMPHASIS1_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_LANE4_PREEMPHASIS1_0_READ_MASK _MK_MASK_CONST(0xff) +#define SOR_NV_PDISP_SOR_LANE4_PREEMPHASIS1_0_WRITE_MASK _MK_MASK_CONST(0xff) +#define SOR_NV_PDISP_SOR_LANE4_PREEMPHASIS1_0_LANE4_SHIFT _MK_SHIFT_CONST(0) +#define SOR_NV_PDISP_SOR_LANE4_PREEMPHASIS1_0_LANE4_FIELD _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_LANE4_PREEMPHASIS1_0_LANE4_SHIFT) +#define SOR_NV_PDISP_SOR_LANE4_PREEMPHASIS1_0_LANE4_RANGE 7:0 +#define SOR_NV_PDISP_SOR_LANE4_PREEMPHASIS1_0_LANE4_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_LANE4_PREEMPHASIS1_0_LANE4_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_LANE4_PREEMPHASIS1_0_LANE4_DEFAULT_MASK _MK_MASK_CONST(0xff) +#define SOR_NV_PDISP_SOR_LANE4_PREEMPHASIS1_0_LANE4_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_LANE4_PREEMPHASIS1_0_LANE4_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register SOR_NV_PDISP_SOR_POSTCURSOR0_0 +#define SOR_NV_PDISP_SOR_POSTCURSOR0_0 _MK_ADDR_CONST(0x56) +#define SOR_NV_PDISP_SOR_POSTCURSOR0_0_SECURE 0x0 +#define SOR_NV_PDISP_SOR_POSTCURSOR0_0_WORD_COUNT 0x1 +#define SOR_NV_PDISP_SOR_POSTCURSOR0_0_RESET_VAL _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_POSTCURSOR0_0_RESET_MASK _MK_MASK_CONST(0xffffffff) +#define SOR_NV_PDISP_SOR_POSTCURSOR0_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_POSTCURSOR0_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_POSTCURSOR0_0_READ_MASK _MK_MASK_CONST(0xffffffff) +#define SOR_NV_PDISP_SOR_POSTCURSOR0_0_WRITE_MASK _MK_MASK_CONST(0xffffffff) +#define SOR_NV_PDISP_SOR_POSTCURSOR0_0_LANE3_DP_LANE3_SHIFT _MK_SHIFT_CONST(24) +#define SOR_NV_PDISP_SOR_POSTCURSOR0_0_LANE3_DP_LANE3_FIELD _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_POSTCURSOR0_0_LANE3_DP_LANE3_SHIFT) +#define SOR_NV_PDISP_SOR_POSTCURSOR0_0_LANE3_DP_LANE3_RANGE 31:24 +#define SOR_NV_PDISP_SOR_POSTCURSOR0_0_LANE3_DP_LANE3_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_POSTCURSOR0_0_LANE3_DP_LANE3_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_POSTCURSOR0_0_LANE3_DP_LANE3_DEFAULT_MASK _MK_MASK_CONST(0xff) +#define SOR_NV_PDISP_SOR_POSTCURSOR0_0_LANE3_DP_LANE3_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_POSTCURSOR0_0_LANE3_DP_LANE3_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define SOR_NV_PDISP_SOR_POSTCURSOR0_0_LANE2_DP_LANE0_SHIFT _MK_SHIFT_CONST(16) +#define SOR_NV_PDISP_SOR_POSTCURSOR0_0_LANE2_DP_LANE0_FIELD _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_POSTCURSOR0_0_LANE2_DP_LANE0_SHIFT) +#define SOR_NV_PDISP_SOR_POSTCURSOR0_0_LANE2_DP_LANE0_RANGE 23:16 +#define SOR_NV_PDISP_SOR_POSTCURSOR0_0_LANE2_DP_LANE0_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_POSTCURSOR0_0_LANE2_DP_LANE0_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_POSTCURSOR0_0_LANE2_DP_LANE0_DEFAULT_MASK _MK_MASK_CONST(0xff) +#define SOR_NV_PDISP_SOR_POSTCURSOR0_0_LANE2_DP_LANE0_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_POSTCURSOR0_0_LANE2_DP_LANE0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define SOR_NV_PDISP_SOR_POSTCURSOR0_0_LANE1_DP_LANE1_SHIFT _MK_SHIFT_CONST(8) +#define SOR_NV_PDISP_SOR_POSTCURSOR0_0_LANE1_DP_LANE1_FIELD _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_POSTCURSOR0_0_LANE1_DP_LANE1_SHIFT) +#define SOR_NV_PDISP_SOR_POSTCURSOR0_0_LANE1_DP_LANE1_RANGE 15:8 +#define SOR_NV_PDISP_SOR_POSTCURSOR0_0_LANE1_DP_LANE1_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_POSTCURSOR0_0_LANE1_DP_LANE1_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_POSTCURSOR0_0_LANE1_DP_LANE1_DEFAULT_MASK _MK_MASK_CONST(0xff) +#define SOR_NV_PDISP_SOR_POSTCURSOR0_0_LANE1_DP_LANE1_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_POSTCURSOR0_0_LANE1_DP_LANE1_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define SOR_NV_PDISP_SOR_POSTCURSOR0_0_LANE0_DP_LANE2_SHIFT _MK_SHIFT_CONST(0) +#define SOR_NV_PDISP_SOR_POSTCURSOR0_0_LANE0_DP_LANE2_FIELD _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_POSTCURSOR0_0_LANE0_DP_LANE2_SHIFT) +#define SOR_NV_PDISP_SOR_POSTCURSOR0_0_LANE0_DP_LANE2_RANGE 7:0 +#define SOR_NV_PDISP_SOR_POSTCURSOR0_0_LANE0_DP_LANE2_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_POSTCURSOR0_0_LANE0_DP_LANE2_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_POSTCURSOR0_0_LANE0_DP_LANE2_DEFAULT_MASK _MK_MASK_CONST(0xff) +#define SOR_NV_PDISP_SOR_POSTCURSOR0_0_LANE0_DP_LANE2_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_POSTCURSOR0_0_LANE0_DP_LANE2_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register SOR_NV_PDISP_SOR_POSTCURSOR1_0 +#define SOR_NV_PDISP_SOR_POSTCURSOR1_0 _MK_ADDR_CONST(0x57) +#define SOR_NV_PDISP_SOR_POSTCURSOR1_0_SECURE 0x0 +#define SOR_NV_PDISP_SOR_POSTCURSOR1_0_WORD_COUNT 0x1 +#define SOR_NV_PDISP_SOR_POSTCURSOR1_0_RESET_VAL _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_POSTCURSOR1_0_RESET_MASK _MK_MASK_CONST(0xffffffff) +#define SOR_NV_PDISP_SOR_POSTCURSOR1_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_POSTCURSOR1_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_POSTCURSOR1_0_READ_MASK _MK_MASK_CONST(0xffffffff) +#define SOR_NV_PDISP_SOR_POSTCURSOR1_0_WRITE_MASK _MK_MASK_CONST(0xffffffff) +#define SOR_NV_PDISP_SOR_POSTCURSOR1_0_LANE3_DP_LANE3_SHIFT _MK_SHIFT_CONST(24) +#define SOR_NV_PDISP_SOR_POSTCURSOR1_0_LANE3_DP_LANE3_FIELD _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_POSTCURSOR1_0_LANE3_DP_LANE3_SHIFT) +#define SOR_NV_PDISP_SOR_POSTCURSOR1_0_LANE3_DP_LANE3_RANGE 31:24 +#define SOR_NV_PDISP_SOR_POSTCURSOR1_0_LANE3_DP_LANE3_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_POSTCURSOR1_0_LANE3_DP_LANE3_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_POSTCURSOR1_0_LANE3_DP_LANE3_DEFAULT_MASK _MK_MASK_CONST(0xff) +#define SOR_NV_PDISP_SOR_POSTCURSOR1_0_LANE3_DP_LANE3_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_POSTCURSOR1_0_LANE3_DP_LANE3_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define SOR_NV_PDISP_SOR_POSTCURSOR1_0_LANE2_DP_LANE0_SHIFT _MK_SHIFT_CONST(16) +#define SOR_NV_PDISP_SOR_POSTCURSOR1_0_LANE2_DP_LANE0_FIELD _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_POSTCURSOR1_0_LANE2_DP_LANE0_SHIFT) +#define SOR_NV_PDISP_SOR_POSTCURSOR1_0_LANE2_DP_LANE0_RANGE 23:16 +#define SOR_NV_PDISP_SOR_POSTCURSOR1_0_LANE2_DP_LANE0_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_POSTCURSOR1_0_LANE2_DP_LANE0_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_POSTCURSOR1_0_LANE2_DP_LANE0_DEFAULT_MASK _MK_MASK_CONST(0xff) +#define SOR_NV_PDISP_SOR_POSTCURSOR1_0_LANE2_DP_LANE0_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_POSTCURSOR1_0_LANE2_DP_LANE0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define SOR_NV_PDISP_SOR_POSTCURSOR1_0_LANE1_DP_LANE1_SHIFT _MK_SHIFT_CONST(8) +#define SOR_NV_PDISP_SOR_POSTCURSOR1_0_LANE1_DP_LANE1_FIELD _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_POSTCURSOR1_0_LANE1_DP_LANE1_SHIFT) +#define SOR_NV_PDISP_SOR_POSTCURSOR1_0_LANE1_DP_LANE1_RANGE 15:8 +#define SOR_NV_PDISP_SOR_POSTCURSOR1_0_LANE1_DP_LANE1_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_POSTCURSOR1_0_LANE1_DP_LANE1_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_POSTCURSOR1_0_LANE1_DP_LANE1_DEFAULT_MASK _MK_MASK_CONST(0xff) +#define SOR_NV_PDISP_SOR_POSTCURSOR1_0_LANE1_DP_LANE1_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_POSTCURSOR1_0_LANE1_DP_LANE1_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define SOR_NV_PDISP_SOR_POSTCURSOR1_0_LANE0_DP_LANE2_SHIFT _MK_SHIFT_CONST(0) +#define SOR_NV_PDISP_SOR_POSTCURSOR1_0_LANE0_DP_LANE2_FIELD _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_POSTCURSOR1_0_LANE0_DP_LANE2_SHIFT) +#define SOR_NV_PDISP_SOR_POSTCURSOR1_0_LANE0_DP_LANE2_RANGE 7:0 +#define SOR_NV_PDISP_SOR_POSTCURSOR1_0_LANE0_DP_LANE2_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_POSTCURSOR1_0_LANE0_DP_LANE2_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_POSTCURSOR1_0_LANE0_DP_LANE2_DEFAULT_MASK _MK_MASK_CONST(0xff) +#define SOR_NV_PDISP_SOR_POSTCURSOR1_0_LANE0_DP_LANE2_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_POSTCURSOR1_0_LANE0_DP_LANE2_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register SOR_NV_PDISP_SOR_DP_CONFIG0_0 +#define SOR_NV_PDISP_SOR_DP_CONFIG0_0 _MK_ADDR_CONST(0x58) +#define SOR_NV_PDISP_SOR_DP_CONFIG0_0_SECURE 0x0 +#define SOR_NV_PDISP_SOR_DP_CONFIG0_0_WORD_COUNT 0x1 +#define SOR_NV_PDISP_SOR_DP_CONFIG0_0_RESET_VAL _MK_MASK_CONST(0x94000000) +#define SOR_NV_PDISP_SOR_DP_CONFIG0_0_RESET_MASK _MK_MASK_CONST(0x950f7f3f) +#define SOR_NV_PDISP_SOR_DP_CONFIG0_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_CONFIG0_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_CONFIG0_0_READ_MASK _MK_MASK_CONST(0x950f7f3f) +#define SOR_NV_PDISP_SOR_DP_CONFIG0_0_WRITE_MASK _MK_MASK_CONST(0x950f7f3f) +#define SOR_NV_PDISP_SOR_DP_CONFIG0_0_RD_RESET_VAL_SHIFT _MK_SHIFT_CONST(31) +#define SOR_NV_PDISP_SOR_DP_CONFIG0_0_RD_RESET_VAL_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_DP_CONFIG0_0_RD_RESET_VAL_SHIFT) +#define SOR_NV_PDISP_SOR_DP_CONFIG0_0_RD_RESET_VAL_RANGE 31:31 +#define SOR_NV_PDISP_SOR_DP_CONFIG0_0_RD_RESET_VAL_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_DP_CONFIG0_0_RD_RESET_VAL_DEFAULT _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_DP_CONFIG0_0_RD_RESET_VAL_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_DP_CONFIG0_0_RD_RESET_VAL_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_CONFIG0_0_RD_RESET_VAL_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_CONFIG0_0_RD_RESET_VAL_INIT_ENUM NEGATIVE +#define SOR_NV_PDISP_SOR_DP_CONFIG0_0_RD_RESET_VAL_POSITIVE _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_DP_CONFIG0_0_RD_RESET_VAL_NEGATIVE _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_DP_CONFIG0_0_IDLE_BEFORE_ATTACH_SHIFT _MK_SHIFT_CONST(28) +#define SOR_NV_PDISP_SOR_DP_CONFIG0_0_IDLE_BEFORE_ATTACH_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_DP_CONFIG0_0_IDLE_BEFORE_ATTACH_SHIFT) +#define SOR_NV_PDISP_SOR_DP_CONFIG0_0_IDLE_BEFORE_ATTACH_RANGE 28:28 +#define SOR_NV_PDISP_SOR_DP_CONFIG0_0_IDLE_BEFORE_ATTACH_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_DP_CONFIG0_0_IDLE_BEFORE_ATTACH_DEFAULT _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_DP_CONFIG0_0_IDLE_BEFORE_ATTACH_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_DP_CONFIG0_0_IDLE_BEFORE_ATTACH_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_CONFIG0_0_IDLE_BEFORE_ATTACH_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_CONFIG0_0_IDLE_BEFORE_ATTACH_INIT_ENUM ENABLE +#define SOR_NV_PDISP_SOR_DP_CONFIG0_0_IDLE_BEFORE_ATTACH_DISABLE _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_DP_CONFIG0_0_IDLE_BEFORE_ATTACH_ENABLE _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_DP_CONFIG0_0_ACTIVESYM_CNTL_SHIFT _MK_SHIFT_CONST(26) +#define SOR_NV_PDISP_SOR_DP_CONFIG0_0_ACTIVESYM_CNTL_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_DP_CONFIG0_0_ACTIVESYM_CNTL_SHIFT) +#define SOR_NV_PDISP_SOR_DP_CONFIG0_0_ACTIVESYM_CNTL_RANGE 26:26 +#define SOR_NV_PDISP_SOR_DP_CONFIG0_0_ACTIVESYM_CNTL_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_DP_CONFIG0_0_ACTIVESYM_CNTL_DEFAULT _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_DP_CONFIG0_0_ACTIVESYM_CNTL_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_DP_CONFIG0_0_ACTIVESYM_CNTL_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_CONFIG0_0_ACTIVESYM_CNTL_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_CONFIG0_0_ACTIVESYM_CNTL_INIT_ENUM ENABLE +#define SOR_NV_PDISP_SOR_DP_CONFIG0_0_ACTIVESYM_CNTL_DISABLE _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_DP_CONFIG0_0_ACTIVESYM_CNTL_ENABLE _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_DP_CONFIG0_0_ACTIVESYM_POLARITY_SHIFT _MK_SHIFT_CONST(24) +#define SOR_NV_PDISP_SOR_DP_CONFIG0_0_ACTIVESYM_POLARITY_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_DP_CONFIG0_0_ACTIVESYM_POLARITY_SHIFT) +#define SOR_NV_PDISP_SOR_DP_CONFIG0_0_ACTIVESYM_POLARITY_RANGE 24:24 +#define SOR_NV_PDISP_SOR_DP_CONFIG0_0_ACTIVESYM_POLARITY_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_DP_CONFIG0_0_ACTIVESYM_POLARITY_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_CONFIG0_0_ACTIVESYM_POLARITY_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_DP_CONFIG0_0_ACTIVESYM_POLARITY_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_CONFIG0_0_ACTIVESYM_POLARITY_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_CONFIG0_0_ACTIVESYM_POLARITY_INIT_ENUM NEGATIVE +#define SOR_NV_PDISP_SOR_DP_CONFIG0_0_ACTIVESYM_POLARITY_NEGATIVE _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_DP_CONFIG0_0_ACTIVESYM_POLARITY_POSITIVE _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_DP_CONFIG0_0_ACTIVESYM_FRAC_SHIFT _MK_SHIFT_CONST(16) +#define SOR_NV_PDISP_SOR_DP_CONFIG0_0_ACTIVESYM_FRAC_FIELD _MK_FIELD_CONST(0xf, SOR_NV_PDISP_SOR_DP_CONFIG0_0_ACTIVESYM_FRAC_SHIFT) +#define SOR_NV_PDISP_SOR_DP_CONFIG0_0_ACTIVESYM_FRAC_RANGE 19:16 +#define SOR_NV_PDISP_SOR_DP_CONFIG0_0_ACTIVESYM_FRAC_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_DP_CONFIG0_0_ACTIVESYM_FRAC_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_CONFIG0_0_ACTIVESYM_FRAC_DEFAULT_MASK _MK_MASK_CONST(0xf) +#define SOR_NV_PDISP_SOR_DP_CONFIG0_0_ACTIVESYM_FRAC_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_CONFIG0_0_ACTIVESYM_FRAC_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define SOR_NV_PDISP_SOR_DP_CONFIG0_0_ACTIVESYM_COUNT_SHIFT _MK_SHIFT_CONST(8) +#define SOR_NV_PDISP_SOR_DP_CONFIG0_0_ACTIVESYM_COUNT_FIELD _MK_FIELD_CONST(0x7f, SOR_NV_PDISP_SOR_DP_CONFIG0_0_ACTIVESYM_COUNT_SHIFT) +#define SOR_NV_PDISP_SOR_DP_CONFIG0_0_ACTIVESYM_COUNT_RANGE 14:8 +#define SOR_NV_PDISP_SOR_DP_CONFIG0_0_ACTIVESYM_COUNT_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_DP_CONFIG0_0_ACTIVESYM_COUNT_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_CONFIG0_0_ACTIVESYM_COUNT_DEFAULT_MASK _MK_MASK_CONST(0x7f) +#define SOR_NV_PDISP_SOR_DP_CONFIG0_0_ACTIVESYM_COUNT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_CONFIG0_0_ACTIVESYM_COUNT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define SOR_NV_PDISP_SOR_DP_CONFIG0_0_WATERMARK_SHIFT _MK_SHIFT_CONST(0) +#define SOR_NV_PDISP_SOR_DP_CONFIG0_0_WATERMARK_FIELD _MK_FIELD_CONST(0x3f, SOR_NV_PDISP_SOR_DP_CONFIG0_0_WATERMARK_SHIFT) +#define SOR_NV_PDISP_SOR_DP_CONFIG0_0_WATERMARK_RANGE 5:0 +#define SOR_NV_PDISP_SOR_DP_CONFIG0_0_WATERMARK_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_DP_CONFIG0_0_WATERMARK_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_CONFIG0_0_WATERMARK_DEFAULT_MASK _MK_MASK_CONST(0x3f) +#define SOR_NV_PDISP_SOR_DP_CONFIG0_0_WATERMARK_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_CONFIG0_0_WATERMARK_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register SOR_NV_PDISP_SOR_DP_CONFIG1_0 +#define SOR_NV_PDISP_SOR_DP_CONFIG1_0 _MK_ADDR_CONST(0x59) +#define SOR_NV_PDISP_SOR_DP_CONFIG1_0_SECURE 0x0 +#define SOR_NV_PDISP_SOR_DP_CONFIG1_0_WORD_COUNT 0x1 +#define SOR_NV_PDISP_SOR_DP_CONFIG1_0_RESET_VAL _MK_MASK_CONST(0x94000000) +#define SOR_NV_PDISP_SOR_DP_CONFIG1_0_RESET_MASK _MK_MASK_CONST(0x950f7f3f) +#define SOR_NV_PDISP_SOR_DP_CONFIG1_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_CONFIG1_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_CONFIG1_0_READ_MASK _MK_MASK_CONST(0x950f7f3f) +#define SOR_NV_PDISP_SOR_DP_CONFIG1_0_WRITE_MASK _MK_MASK_CONST(0x950f7f3f) +#define SOR_NV_PDISP_SOR_DP_CONFIG1_0_RD_RESET_VAL_SHIFT _MK_SHIFT_CONST(31) +#define SOR_NV_PDISP_SOR_DP_CONFIG1_0_RD_RESET_VAL_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_DP_CONFIG1_0_RD_RESET_VAL_SHIFT) +#define SOR_NV_PDISP_SOR_DP_CONFIG1_0_RD_RESET_VAL_RANGE 31:31 +#define SOR_NV_PDISP_SOR_DP_CONFIG1_0_RD_RESET_VAL_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_DP_CONFIG1_0_RD_RESET_VAL_DEFAULT _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_DP_CONFIG1_0_RD_RESET_VAL_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_DP_CONFIG1_0_RD_RESET_VAL_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_CONFIG1_0_RD_RESET_VAL_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_CONFIG1_0_RD_RESET_VAL_INIT_ENUM NEGATIVE +#define SOR_NV_PDISP_SOR_DP_CONFIG1_0_RD_RESET_VAL_POSITIVE _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_DP_CONFIG1_0_RD_RESET_VAL_NEGATIVE _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_DP_CONFIG1_0_IDLE_BEFORE_ATTACH_SHIFT _MK_SHIFT_CONST(28) +#define SOR_NV_PDISP_SOR_DP_CONFIG1_0_IDLE_BEFORE_ATTACH_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_DP_CONFIG1_0_IDLE_BEFORE_ATTACH_SHIFT) +#define SOR_NV_PDISP_SOR_DP_CONFIG1_0_IDLE_BEFORE_ATTACH_RANGE 28:28 +#define SOR_NV_PDISP_SOR_DP_CONFIG1_0_IDLE_BEFORE_ATTACH_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_DP_CONFIG1_0_IDLE_BEFORE_ATTACH_DEFAULT _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_DP_CONFIG1_0_IDLE_BEFORE_ATTACH_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_DP_CONFIG1_0_IDLE_BEFORE_ATTACH_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_CONFIG1_0_IDLE_BEFORE_ATTACH_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_CONFIG1_0_IDLE_BEFORE_ATTACH_INIT_ENUM ENABLE +#define SOR_NV_PDISP_SOR_DP_CONFIG1_0_IDLE_BEFORE_ATTACH_DISABLE _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_DP_CONFIG1_0_IDLE_BEFORE_ATTACH_ENABLE _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_DP_CONFIG1_0_ACTIVESYM_CNTL_SHIFT _MK_SHIFT_CONST(26) +#define SOR_NV_PDISP_SOR_DP_CONFIG1_0_ACTIVESYM_CNTL_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_DP_CONFIG1_0_ACTIVESYM_CNTL_SHIFT) +#define SOR_NV_PDISP_SOR_DP_CONFIG1_0_ACTIVESYM_CNTL_RANGE 26:26 +#define SOR_NV_PDISP_SOR_DP_CONFIG1_0_ACTIVESYM_CNTL_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_DP_CONFIG1_0_ACTIVESYM_CNTL_DEFAULT _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_DP_CONFIG1_0_ACTIVESYM_CNTL_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_DP_CONFIG1_0_ACTIVESYM_CNTL_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_CONFIG1_0_ACTIVESYM_CNTL_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_CONFIG1_0_ACTIVESYM_CNTL_INIT_ENUM ENABLE +#define SOR_NV_PDISP_SOR_DP_CONFIG1_0_ACTIVESYM_CNTL_DISABLE _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_DP_CONFIG1_0_ACTIVESYM_CNTL_ENABLE _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_DP_CONFIG1_0_ACTIVESYM_POLARITY_SHIFT _MK_SHIFT_CONST(24) +#define SOR_NV_PDISP_SOR_DP_CONFIG1_0_ACTIVESYM_POLARITY_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_DP_CONFIG1_0_ACTIVESYM_POLARITY_SHIFT) +#define SOR_NV_PDISP_SOR_DP_CONFIG1_0_ACTIVESYM_POLARITY_RANGE 24:24 +#define SOR_NV_PDISP_SOR_DP_CONFIG1_0_ACTIVESYM_POLARITY_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_DP_CONFIG1_0_ACTIVESYM_POLARITY_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_CONFIG1_0_ACTIVESYM_POLARITY_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_DP_CONFIG1_0_ACTIVESYM_POLARITY_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_CONFIG1_0_ACTIVESYM_POLARITY_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_CONFIG1_0_ACTIVESYM_POLARITY_INIT_ENUM NEGATIVE +#define SOR_NV_PDISP_SOR_DP_CONFIG1_0_ACTIVESYM_POLARITY_NEGATIVE _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_DP_CONFIG1_0_ACTIVESYM_POLARITY_POSITIVE _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_DP_CONFIG1_0_ACTIVESYM_FRAC_SHIFT _MK_SHIFT_CONST(16) +#define SOR_NV_PDISP_SOR_DP_CONFIG1_0_ACTIVESYM_FRAC_FIELD _MK_FIELD_CONST(0xf, SOR_NV_PDISP_SOR_DP_CONFIG1_0_ACTIVESYM_FRAC_SHIFT) +#define SOR_NV_PDISP_SOR_DP_CONFIG1_0_ACTIVESYM_FRAC_RANGE 19:16 +#define SOR_NV_PDISP_SOR_DP_CONFIG1_0_ACTIVESYM_FRAC_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_DP_CONFIG1_0_ACTIVESYM_FRAC_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_CONFIG1_0_ACTIVESYM_FRAC_DEFAULT_MASK _MK_MASK_CONST(0xf) +#define SOR_NV_PDISP_SOR_DP_CONFIG1_0_ACTIVESYM_FRAC_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_CONFIG1_0_ACTIVESYM_FRAC_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define SOR_NV_PDISP_SOR_DP_CONFIG1_0_ACTIVESYM_COUNT_SHIFT _MK_SHIFT_CONST(8) +#define SOR_NV_PDISP_SOR_DP_CONFIG1_0_ACTIVESYM_COUNT_FIELD _MK_FIELD_CONST(0x7f, SOR_NV_PDISP_SOR_DP_CONFIG1_0_ACTIVESYM_COUNT_SHIFT) +#define SOR_NV_PDISP_SOR_DP_CONFIG1_0_ACTIVESYM_COUNT_RANGE 14:8 +#define SOR_NV_PDISP_SOR_DP_CONFIG1_0_ACTIVESYM_COUNT_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_DP_CONFIG1_0_ACTIVESYM_COUNT_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_CONFIG1_0_ACTIVESYM_COUNT_DEFAULT_MASK _MK_MASK_CONST(0x7f) +#define SOR_NV_PDISP_SOR_DP_CONFIG1_0_ACTIVESYM_COUNT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_CONFIG1_0_ACTIVESYM_COUNT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define SOR_NV_PDISP_SOR_DP_CONFIG1_0_WATERMARK_SHIFT _MK_SHIFT_CONST(0) +#define SOR_NV_PDISP_SOR_DP_CONFIG1_0_WATERMARK_FIELD _MK_FIELD_CONST(0x3f, SOR_NV_PDISP_SOR_DP_CONFIG1_0_WATERMARK_SHIFT) +#define SOR_NV_PDISP_SOR_DP_CONFIG1_0_WATERMARK_RANGE 5:0 +#define SOR_NV_PDISP_SOR_DP_CONFIG1_0_WATERMARK_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_DP_CONFIG1_0_WATERMARK_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_CONFIG1_0_WATERMARK_DEFAULT_MASK _MK_MASK_CONST(0x3f) +#define SOR_NV_PDISP_SOR_DP_CONFIG1_0_WATERMARK_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_CONFIG1_0_WATERMARK_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register SOR_NV_PDISP_SOR_DP_MN0_0 +#define SOR_NV_PDISP_SOR_DP_MN0_0 _MK_ADDR_CONST(0x5a) +#define SOR_NV_PDISP_SOR_DP_MN0_0_SECURE 0x0 +#define SOR_NV_PDISP_SOR_DP_MN0_0_WORD_COUNT 0x1 +#define SOR_NV_PDISP_SOR_DP_MN0_0_RESET_VAL _MK_MASK_CONST(0x8000) +#define SOR_NV_PDISP_SOR_DP_MN0_0_RESET_MASK _MK_MASK_CONST(0xcfffffff) +#define SOR_NV_PDISP_SOR_DP_MN0_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_MN0_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_MN0_0_READ_MASK _MK_MASK_CONST(0xcfffffff) +#define SOR_NV_PDISP_SOR_DP_MN0_0_WRITE_MASK _MK_MASK_CONST(0xcfffffff) +#define SOR_NV_PDISP_SOR_DP_MN0_0_M_MOD_SHIFT _MK_SHIFT_CONST(30) +#define SOR_NV_PDISP_SOR_DP_MN0_0_M_MOD_FIELD _MK_FIELD_CONST(0x3, SOR_NV_PDISP_SOR_DP_MN0_0_M_MOD_SHIFT) +#define SOR_NV_PDISP_SOR_DP_MN0_0_M_MOD_RANGE 31:30 +#define SOR_NV_PDISP_SOR_DP_MN0_0_M_MOD_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_DP_MN0_0_M_MOD_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_MN0_0_M_MOD_DEFAULT_MASK _MK_MASK_CONST(0x3) +#define SOR_NV_PDISP_SOR_DP_MN0_0_M_MOD_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_MN0_0_M_MOD_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_MN0_0_M_MOD_INIT_ENUM NONE +#define SOR_NV_PDISP_SOR_DP_MN0_0_M_MOD_NONE _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_DP_MN0_0_M_MOD_INC _MK_ENUM_CONST(1) +#define SOR_NV_PDISP_SOR_DP_MN0_0_M_MOD_DEC _MK_ENUM_CONST(2) + +#define SOR_NV_PDISP_SOR_DP_MN0_0_M_DELTA_SHIFT _MK_SHIFT_CONST(24) +#define SOR_NV_PDISP_SOR_DP_MN0_0_M_DELTA_FIELD _MK_FIELD_CONST(0xf, SOR_NV_PDISP_SOR_DP_MN0_0_M_DELTA_SHIFT) +#define SOR_NV_PDISP_SOR_DP_MN0_0_M_DELTA_RANGE 27:24 +#define SOR_NV_PDISP_SOR_DP_MN0_0_M_DELTA_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_DP_MN0_0_M_DELTA_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_MN0_0_M_DELTA_DEFAULT_MASK _MK_MASK_CONST(0xf) +#define SOR_NV_PDISP_SOR_DP_MN0_0_M_DELTA_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_MN0_0_M_DELTA_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define SOR_NV_PDISP_SOR_DP_MN0_0_N_VAL_SHIFT _MK_SHIFT_CONST(0) +#define SOR_NV_PDISP_SOR_DP_MN0_0_N_VAL_FIELD _MK_FIELD_CONST(0xffffff, SOR_NV_PDISP_SOR_DP_MN0_0_N_VAL_SHIFT) +#define SOR_NV_PDISP_SOR_DP_MN0_0_N_VAL_RANGE 23:0 +#define SOR_NV_PDISP_SOR_DP_MN0_0_N_VAL_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_DP_MN0_0_N_VAL_DEFAULT _MK_MASK_CONST(0x8000) +#define SOR_NV_PDISP_SOR_DP_MN0_0_N_VAL_DEFAULT_MASK _MK_MASK_CONST(0xffffff) +#define SOR_NV_PDISP_SOR_DP_MN0_0_N_VAL_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_MN0_0_N_VAL_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register SOR_NV_PDISP_SOR_DP_MN1_0 +#define SOR_NV_PDISP_SOR_DP_MN1_0 _MK_ADDR_CONST(0x5b) +#define SOR_NV_PDISP_SOR_DP_MN1_0_SECURE 0x0 +#define SOR_NV_PDISP_SOR_DP_MN1_0_WORD_COUNT 0x1 +#define SOR_NV_PDISP_SOR_DP_MN1_0_RESET_VAL _MK_MASK_CONST(0x8000) +#define SOR_NV_PDISP_SOR_DP_MN1_0_RESET_MASK _MK_MASK_CONST(0xcfffffff) +#define SOR_NV_PDISP_SOR_DP_MN1_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_MN1_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_MN1_0_READ_MASK _MK_MASK_CONST(0xcfffffff) +#define SOR_NV_PDISP_SOR_DP_MN1_0_WRITE_MASK _MK_MASK_CONST(0xcfffffff) +#define SOR_NV_PDISP_SOR_DP_MN1_0_M_MOD_SHIFT _MK_SHIFT_CONST(30) +#define SOR_NV_PDISP_SOR_DP_MN1_0_M_MOD_FIELD _MK_FIELD_CONST(0x3, SOR_NV_PDISP_SOR_DP_MN1_0_M_MOD_SHIFT) +#define SOR_NV_PDISP_SOR_DP_MN1_0_M_MOD_RANGE 31:30 +#define SOR_NV_PDISP_SOR_DP_MN1_0_M_MOD_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_DP_MN1_0_M_MOD_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_MN1_0_M_MOD_DEFAULT_MASK _MK_MASK_CONST(0x3) +#define SOR_NV_PDISP_SOR_DP_MN1_0_M_MOD_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_MN1_0_M_MOD_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_MN1_0_M_MOD_INIT_ENUM NONE +#define SOR_NV_PDISP_SOR_DP_MN1_0_M_MOD_NONE _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_DP_MN1_0_M_MOD_INC _MK_ENUM_CONST(1) +#define SOR_NV_PDISP_SOR_DP_MN1_0_M_MOD_DEC _MK_ENUM_CONST(2) + +#define SOR_NV_PDISP_SOR_DP_MN1_0_M_DELTA_SHIFT _MK_SHIFT_CONST(24) +#define SOR_NV_PDISP_SOR_DP_MN1_0_M_DELTA_FIELD _MK_FIELD_CONST(0xf, SOR_NV_PDISP_SOR_DP_MN1_0_M_DELTA_SHIFT) +#define SOR_NV_PDISP_SOR_DP_MN1_0_M_DELTA_RANGE 27:24 +#define SOR_NV_PDISP_SOR_DP_MN1_0_M_DELTA_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_DP_MN1_0_M_DELTA_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_MN1_0_M_DELTA_DEFAULT_MASK _MK_MASK_CONST(0xf) +#define SOR_NV_PDISP_SOR_DP_MN1_0_M_DELTA_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_MN1_0_M_DELTA_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define SOR_NV_PDISP_SOR_DP_MN1_0_N_VAL_SHIFT _MK_SHIFT_CONST(0) +#define SOR_NV_PDISP_SOR_DP_MN1_0_N_VAL_FIELD _MK_FIELD_CONST(0xffffff, SOR_NV_PDISP_SOR_DP_MN1_0_N_VAL_SHIFT) +#define SOR_NV_PDISP_SOR_DP_MN1_0_N_VAL_RANGE 23:0 +#define SOR_NV_PDISP_SOR_DP_MN1_0_N_VAL_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_DP_MN1_0_N_VAL_DEFAULT _MK_MASK_CONST(0x8000) +#define SOR_NV_PDISP_SOR_DP_MN1_0_N_VAL_DEFAULT_MASK _MK_MASK_CONST(0xffffff) +#define SOR_NV_PDISP_SOR_DP_MN1_0_N_VAL_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_MN1_0_N_VAL_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register SOR_NV_PDISP_SOR_DP_PADCTL0_0 +#define SOR_NV_PDISP_SOR_DP_PADCTL0_0 _MK_ADDR_CONST(0x5c) +#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_SECURE 0x0 +#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_WORD_COUNT 0x1 +#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_RESET_VAL _MK_MASK_CONST(0x800000) +#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_RESET_MASK _MK_MASK_CONST(0xffffffff) +#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_READ_MASK _MK_MASK_CONST(0xffffffff) +#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_WRITE_MASK _MK_MASK_CONST(0xffffffff) +#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_SPARE_SHIFT _MK_SHIFT_CONST(25) +#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_SPARE_FIELD _MK_FIELD_CONST(0x7f, SOR_NV_PDISP_SOR_DP_PADCTL0_0_SPARE_SHIFT) +#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_SPARE_RANGE 31:25 +#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_SPARE_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_SPARE_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_SPARE_DEFAULT_MASK _MK_MASK_CONST(0x7f) +#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_SPARE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_SPARE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_VCO_2X_SHIFT _MK_SHIFT_CONST(24) +#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_VCO_2X_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_DP_PADCTL0_0_VCO_2X_SHIFT) +#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_VCO_2X_RANGE 24:24 +#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_VCO_2X_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_VCO_2X_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_VCO_2X_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_VCO_2X_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_VCO_2X_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_VCO_2X_INIT_ENUM DISABLE +#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_VCO_2X_DISABLE _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_VCO_2X_ENABLE _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_PAD_CAL_PD_SHIFT _MK_SHIFT_CONST(23) +#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_PAD_CAL_PD_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_DP_PADCTL0_0_PAD_CAL_PD_SHIFT) +#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_PAD_CAL_PD_RANGE 23:23 +#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_PAD_CAL_PD_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_PAD_CAL_PD_DEFAULT _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_PAD_CAL_PD_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_PAD_CAL_PD_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_PAD_CAL_PD_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_PAD_CAL_PD_INIT_ENUM POWERDOWN +#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_PAD_CAL_PD_POWERUP _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_PAD_CAL_PD_POWERDOWN _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_TX_PU_SHIFT _MK_SHIFT_CONST(22) +#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_TX_PU_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_DP_PADCTL0_0_TX_PU_SHIFT) +#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_TX_PU_RANGE 22:22 +#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_TX_PU_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_TX_PU_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_TX_PU_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_TX_PU_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_TX_PU_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_TX_PU_INIT_ENUM DISABLE +#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_TX_PU_DISABLE _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_TX_PU_ENABLE _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_REG_CTRL_SHIFT _MK_SHIFT_CONST(20) +#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_REG_CTRL_FIELD _MK_FIELD_CONST(0x3, SOR_NV_PDISP_SOR_DP_PADCTL0_0_REG_CTRL_SHIFT) +#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_REG_CTRL_RANGE 21:20 +#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_REG_CTRL_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_REG_CTRL_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_REG_CTRL_DEFAULT_MASK _MK_MASK_CONST(0x3) +#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_REG_CTRL_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_REG_CTRL_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_VCMMODE_SHIFT _MK_SHIFT_CONST(16) +#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_VCMMODE_FIELD _MK_FIELD_CONST(0xf, SOR_NV_PDISP_SOR_DP_PADCTL0_0_VCMMODE_SHIFT) +#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_VCMMODE_RANGE 19:16 +#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_VCMMODE_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_VCMMODE_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_VCMMODE_DEFAULT_MASK _MK_MASK_CONST(0xf) +#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_VCMMODE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_VCMMODE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_VCMMODE_INIT_ENUM TRISTATE +#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_VCMMODE_TRISTATE _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_VCMMODE_TEST_MUX _MK_ENUM_CONST(1) +#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_VCMMODE_WEAK_PULLDOWN _MK_ENUM_CONST(2) +#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_VCMMODE_STRONG_PULLDOWN _MK_ENUM_CONST(4) + +#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_TX_PU_VALUE_SHIFT _MK_SHIFT_CONST(8) +#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_TX_PU_VALUE_FIELD _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_DP_PADCTL0_0_TX_PU_VALUE_SHIFT) +#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_TX_PU_VALUE_RANGE 15:8 +#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_TX_PU_VALUE_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_TX_PU_VALUE_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_TX_PU_VALUE_DEFAULT_MASK _MK_MASK_CONST(0xff) +#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_TX_PU_VALUE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_TX_PU_VALUE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_COMMONMODE_TXD_3_DP_TXD_3_SHIFT _MK_SHIFT_CONST(7) +#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_COMMONMODE_TXD_3_DP_TXD_3_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_DP_PADCTL0_0_COMMONMODE_TXD_3_DP_TXD_3_SHIFT) +#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_COMMONMODE_TXD_3_DP_TXD_3_RANGE 7:7 +#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_COMMONMODE_TXD_3_DP_TXD_3_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_COMMONMODE_TXD_3_DP_TXD_3_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_COMMONMODE_TXD_3_DP_TXD_3_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_COMMONMODE_TXD_3_DP_TXD_3_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_COMMONMODE_TXD_3_DP_TXD_3_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_COMMONMODE_TXD_3_DP_TXD_3_INIT_ENUM DISABLE +#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_COMMONMODE_TXD_3_DP_TXD_3_DISABLE _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_COMMONMODE_TXD_3_DP_TXD_3_ENABLE _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_COMMONMODE_TXD_2_DP_TXD_0_SHIFT _MK_SHIFT_CONST(6) +#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_COMMONMODE_TXD_2_DP_TXD_0_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_DP_PADCTL0_0_COMMONMODE_TXD_2_DP_TXD_0_SHIFT) +#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_COMMONMODE_TXD_2_DP_TXD_0_RANGE 6:6 +#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_COMMONMODE_TXD_2_DP_TXD_0_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_COMMONMODE_TXD_2_DP_TXD_0_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_COMMONMODE_TXD_2_DP_TXD_0_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_COMMONMODE_TXD_2_DP_TXD_0_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_COMMONMODE_TXD_2_DP_TXD_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_COMMONMODE_TXD_2_DP_TXD_0_INIT_ENUM DISABLE +#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_COMMONMODE_TXD_2_DP_TXD_0_DISABLE _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_COMMONMODE_TXD_2_DP_TXD_0_ENABLE _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_COMMONMODE_TXD_1_DP_TXD_1_SHIFT _MK_SHIFT_CONST(5) +#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_COMMONMODE_TXD_1_DP_TXD_1_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_DP_PADCTL0_0_COMMONMODE_TXD_1_DP_TXD_1_SHIFT) +#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_COMMONMODE_TXD_1_DP_TXD_1_RANGE 5:5 +#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_COMMONMODE_TXD_1_DP_TXD_1_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_COMMONMODE_TXD_1_DP_TXD_1_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_COMMONMODE_TXD_1_DP_TXD_1_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_COMMONMODE_TXD_1_DP_TXD_1_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_COMMONMODE_TXD_1_DP_TXD_1_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_COMMONMODE_TXD_1_DP_TXD_1_INIT_ENUM DISABLE +#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_COMMONMODE_TXD_1_DP_TXD_1_DISABLE _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_COMMONMODE_TXD_1_DP_TXD_1_ENABLE _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_COMMONMODE_TXD_0_DP_TXD_2_SHIFT _MK_SHIFT_CONST(4) +#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_COMMONMODE_TXD_0_DP_TXD_2_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_DP_PADCTL0_0_COMMONMODE_TXD_0_DP_TXD_2_SHIFT) +#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_COMMONMODE_TXD_0_DP_TXD_2_RANGE 4:4 +#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_COMMONMODE_TXD_0_DP_TXD_2_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_COMMONMODE_TXD_0_DP_TXD_2_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_COMMONMODE_TXD_0_DP_TXD_2_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_COMMONMODE_TXD_0_DP_TXD_2_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_COMMONMODE_TXD_0_DP_TXD_2_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_COMMONMODE_TXD_0_DP_TXD_2_INIT_ENUM DISABLE +#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_COMMONMODE_TXD_0_DP_TXD_2_DISABLE _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_COMMONMODE_TXD_0_DP_TXD_2_ENABLE _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_PD_TXD_3_SHIFT _MK_SHIFT_CONST(3) +#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_PD_TXD_3_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_DP_PADCTL0_0_PD_TXD_3_SHIFT) +#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_PD_TXD_3_RANGE 3:3 +#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_PD_TXD_3_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_PD_TXD_3_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_PD_TXD_3_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_PD_TXD_3_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_PD_TXD_3_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_PD_TXD_3_INIT_ENUM YES +#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_PD_TXD_3_YES _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_PD_TXD_3_NO _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_PD_TXD_0_SHIFT _MK_SHIFT_CONST(2) +#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_PD_TXD_0_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_DP_PADCTL0_0_PD_TXD_0_SHIFT) +#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_PD_TXD_0_RANGE 2:2 +#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_PD_TXD_0_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_PD_TXD_0_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_PD_TXD_0_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_PD_TXD_0_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_PD_TXD_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_PD_TXD_0_INIT_ENUM YES +#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_PD_TXD_0_YES _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_PD_TXD_0_NO _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_PD_TXD_1_SHIFT _MK_SHIFT_CONST(1) +#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_PD_TXD_1_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_DP_PADCTL0_0_PD_TXD_1_SHIFT) +#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_PD_TXD_1_RANGE 1:1 +#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_PD_TXD_1_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_PD_TXD_1_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_PD_TXD_1_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_PD_TXD_1_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_PD_TXD_1_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_PD_TXD_1_INIT_ENUM YES +#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_PD_TXD_1_YES _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_PD_TXD_1_NO _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_PD_TXD_2_SHIFT _MK_SHIFT_CONST(0) +#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_PD_TXD_2_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_DP_PADCTL0_0_PD_TXD_2_SHIFT) +#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_PD_TXD_2_RANGE 0:0 +#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_PD_TXD_2_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_PD_TXD_2_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_PD_TXD_2_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_PD_TXD_2_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_PD_TXD_2_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_PD_TXD_2_INIT_ENUM YES +#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_PD_TXD_2_YES _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_DP_PADCTL0_0_PD_TXD_2_NO _MK_ENUM_CONST(1) + + +// Register SOR_NV_PDISP_SOR_DP_PADCTL1_0 +#define SOR_NV_PDISP_SOR_DP_PADCTL1_0 _MK_ADDR_CONST(0x5d) +#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_SECURE 0x0 +#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_WORD_COUNT 0x1 +#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_RESET_VAL _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_RESET_MASK _MK_MASK_CONST(0xffffffff) +#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_READ_MASK _MK_MASK_CONST(0xffffffff) +#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_WRITE_MASK _MK_MASK_CONST(0xffffffff) +#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_SPARE_SHIFT _MK_SHIFT_CONST(25) +#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_SPARE_FIELD _MK_FIELD_CONST(0x7f, SOR_NV_PDISP_SOR_DP_PADCTL1_0_SPARE_SHIFT) +#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_SPARE_RANGE 31:25 +#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_SPARE_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_SPARE_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_SPARE_DEFAULT_MASK _MK_MASK_CONST(0x7f) +#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_SPARE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_SPARE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_VCO_2X_SHIFT _MK_SHIFT_CONST(24) +#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_VCO_2X_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_DP_PADCTL1_0_VCO_2X_SHIFT) +#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_VCO_2X_RANGE 24:24 +#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_VCO_2X_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_VCO_2X_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_VCO_2X_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_VCO_2X_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_VCO_2X_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_VCO_2X_INIT_ENUM DISABLE +#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_VCO_2X_DISABLE _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_VCO_2X_ENABLE _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_PAD_CAL_PD_SHIFT _MK_SHIFT_CONST(23) +#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_PAD_CAL_PD_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_DP_PADCTL1_0_PAD_CAL_PD_SHIFT) +#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_PAD_CAL_PD_RANGE 23:23 +#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_PAD_CAL_PD_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_PAD_CAL_PD_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_PAD_CAL_PD_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_PAD_CAL_PD_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_PAD_CAL_PD_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_PAD_CAL_PD_INIT_ENUM POWERUP +#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_PAD_CAL_PD_POWERUP _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_PAD_CAL_PD_POWERDOWN _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_TX_PU_SHIFT _MK_SHIFT_CONST(22) +#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_TX_PU_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_DP_PADCTL1_0_TX_PU_SHIFT) +#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_TX_PU_RANGE 22:22 +#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_TX_PU_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_TX_PU_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_TX_PU_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_TX_PU_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_TX_PU_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_TX_PU_INIT_ENUM DISABLE +#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_TX_PU_DISABLE _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_TX_PU_ENABLE _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_REG_CTRL_SHIFT _MK_SHIFT_CONST(20) +#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_REG_CTRL_FIELD _MK_FIELD_CONST(0x3, SOR_NV_PDISP_SOR_DP_PADCTL1_0_REG_CTRL_SHIFT) +#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_REG_CTRL_RANGE 21:20 +#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_REG_CTRL_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_REG_CTRL_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_REG_CTRL_DEFAULT_MASK _MK_MASK_CONST(0x3) +#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_REG_CTRL_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_REG_CTRL_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_VCMMODE_SHIFT _MK_SHIFT_CONST(16) +#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_VCMMODE_FIELD _MK_FIELD_CONST(0xf, SOR_NV_PDISP_SOR_DP_PADCTL1_0_VCMMODE_SHIFT) +#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_VCMMODE_RANGE 19:16 +#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_VCMMODE_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_VCMMODE_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_VCMMODE_DEFAULT_MASK _MK_MASK_CONST(0xf) +#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_VCMMODE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_VCMMODE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_VCMMODE_INIT_ENUM TRISTATE +#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_VCMMODE_TRISTATE _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_VCMMODE_TEST_MUX _MK_ENUM_CONST(1) +#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_VCMMODE_WEAK_PULLDOWN _MK_ENUM_CONST(2) +#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_VCMMODE_STRONG_PULLDOWN _MK_ENUM_CONST(4) + +#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_TX_PU_VALUE_SHIFT _MK_SHIFT_CONST(8) +#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_TX_PU_VALUE_FIELD _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_DP_PADCTL1_0_TX_PU_VALUE_SHIFT) +#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_TX_PU_VALUE_RANGE 15:8 +#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_TX_PU_VALUE_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_TX_PU_VALUE_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_TX_PU_VALUE_DEFAULT_MASK _MK_MASK_CONST(0xff) +#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_TX_PU_VALUE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_TX_PU_VALUE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_COMMONMODE_TXD_3_DP_TXD_3_SHIFT _MK_SHIFT_CONST(7) +#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_COMMONMODE_TXD_3_DP_TXD_3_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_DP_PADCTL1_0_COMMONMODE_TXD_3_DP_TXD_3_SHIFT) +#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_COMMONMODE_TXD_3_DP_TXD_3_RANGE 7:7 +#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_COMMONMODE_TXD_3_DP_TXD_3_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_COMMONMODE_TXD_3_DP_TXD_3_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_COMMONMODE_TXD_3_DP_TXD_3_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_COMMONMODE_TXD_3_DP_TXD_3_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_COMMONMODE_TXD_3_DP_TXD_3_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_COMMONMODE_TXD_3_DP_TXD_3_INIT_ENUM DISABLE +#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_COMMONMODE_TXD_3_DP_TXD_3_DISABLE _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_COMMONMODE_TXD_3_DP_TXD_3_ENABLE _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_COMMONMODE_TXD_2_DP_TXD_0_SHIFT _MK_SHIFT_CONST(6) +#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_COMMONMODE_TXD_2_DP_TXD_0_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_DP_PADCTL1_0_COMMONMODE_TXD_2_DP_TXD_0_SHIFT) +#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_COMMONMODE_TXD_2_DP_TXD_0_RANGE 6:6 +#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_COMMONMODE_TXD_2_DP_TXD_0_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_COMMONMODE_TXD_2_DP_TXD_0_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_COMMONMODE_TXD_2_DP_TXD_0_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_COMMONMODE_TXD_2_DP_TXD_0_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_COMMONMODE_TXD_2_DP_TXD_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_COMMONMODE_TXD_2_DP_TXD_0_INIT_ENUM DISABLE +#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_COMMONMODE_TXD_2_DP_TXD_0_DISABLE _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_COMMONMODE_TXD_2_DP_TXD_0_ENABLE _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_COMMONMODE_TXD_1_DP_TXD_1_SHIFT _MK_SHIFT_CONST(5) +#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_COMMONMODE_TXD_1_DP_TXD_1_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_DP_PADCTL1_0_COMMONMODE_TXD_1_DP_TXD_1_SHIFT) +#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_COMMONMODE_TXD_1_DP_TXD_1_RANGE 5:5 +#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_COMMONMODE_TXD_1_DP_TXD_1_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_COMMONMODE_TXD_1_DP_TXD_1_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_COMMONMODE_TXD_1_DP_TXD_1_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_COMMONMODE_TXD_1_DP_TXD_1_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_COMMONMODE_TXD_1_DP_TXD_1_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_COMMONMODE_TXD_1_DP_TXD_1_INIT_ENUM DISABLE +#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_COMMONMODE_TXD_1_DP_TXD_1_DISABLE _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_COMMONMODE_TXD_1_DP_TXD_1_ENABLE _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_COMMONMODE_TXD_0_DP_TXD_2_SHIFT _MK_SHIFT_CONST(4) +#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_COMMONMODE_TXD_0_DP_TXD_2_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_DP_PADCTL1_0_COMMONMODE_TXD_0_DP_TXD_2_SHIFT) +#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_COMMONMODE_TXD_0_DP_TXD_2_RANGE 4:4 +#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_COMMONMODE_TXD_0_DP_TXD_2_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_COMMONMODE_TXD_0_DP_TXD_2_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_COMMONMODE_TXD_0_DP_TXD_2_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_COMMONMODE_TXD_0_DP_TXD_2_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_COMMONMODE_TXD_0_DP_TXD_2_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_COMMONMODE_TXD_0_DP_TXD_2_INIT_ENUM DISABLE +#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_COMMONMODE_TXD_0_DP_TXD_2_DISABLE _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_COMMONMODE_TXD_0_DP_TXD_2_ENABLE _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_PD_TXD_3_SHIFT _MK_SHIFT_CONST(3) +#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_PD_TXD_3_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_DP_PADCTL1_0_PD_TXD_3_SHIFT) +#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_PD_TXD_3_RANGE 3:3 +#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_PD_TXD_3_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_PD_TXD_3_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_PD_TXD_3_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_PD_TXD_3_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_PD_TXD_3_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_PD_TXD_3_INIT_ENUM YES +#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_PD_TXD_3_YES _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_PD_TXD_3_NO _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_PD_TXD_0_SHIFT _MK_SHIFT_CONST(2) +#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_PD_TXD_0_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_DP_PADCTL1_0_PD_TXD_0_SHIFT) +#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_PD_TXD_0_RANGE 2:2 +#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_PD_TXD_0_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_PD_TXD_0_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_PD_TXD_0_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_PD_TXD_0_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_PD_TXD_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_PD_TXD_0_INIT_ENUM YES +#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_PD_TXD_0_YES _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_PD_TXD_0_NO _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_PD_TXD_1_SHIFT _MK_SHIFT_CONST(1) +#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_PD_TXD_1_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_DP_PADCTL1_0_PD_TXD_1_SHIFT) +#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_PD_TXD_1_RANGE 1:1 +#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_PD_TXD_1_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_PD_TXD_1_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_PD_TXD_1_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_PD_TXD_1_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_PD_TXD_1_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_PD_TXD_1_INIT_ENUM YES +#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_PD_TXD_1_YES _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_PD_TXD_1_NO _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_PD_TXD_2_SHIFT _MK_SHIFT_CONST(0) +#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_PD_TXD_2_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_DP_PADCTL1_0_PD_TXD_2_SHIFT) +#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_PD_TXD_2_RANGE 0:0 +#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_PD_TXD_2_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_PD_TXD_2_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_PD_TXD_2_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_PD_TXD_2_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_PD_TXD_2_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_PD_TXD_2_INIT_ENUM YES +#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_PD_TXD_2_YES _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_DP_PADCTL1_0_PD_TXD_2_NO _MK_ENUM_CONST(1) + + +// Register SOR_NV_PDISP_SOR_DP_DEBUG0_0 +#define SOR_NV_PDISP_SOR_DP_DEBUG0_0 _MK_ADDR_CONST(0x5e) +#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_SECURE 0x0 +#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_WORD_COUNT 0x1 +#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_RESET_VAL _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_RESET_MASK _MK_MASK_CONST(0x1ffff) +#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_READ_MASK _MK_MASK_CONST(0x1ffff) +#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_WRITE_MASK _MK_MASK_CONST(0x1ffff) +#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE3_FIFO_OVERFLOW_SHIFT _MK_SHIFT_CONST(16) +#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE3_FIFO_OVERFLOW_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE3_FIFO_OVERFLOW_SHIFT) +#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE3_FIFO_OVERFLOW_RANGE 16:16 +#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE3_FIFO_OVERFLOW_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE3_FIFO_OVERFLOW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE3_FIFO_OVERFLOW_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE3_FIFO_OVERFLOW_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE3_FIFO_OVERFLOW_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE3_FIFO_OVERFLOW_INIT_ENUM NO +#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE3_FIFO_OVERFLOW_NO _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE3_FIFO_OVERFLOW_YES _MK_ENUM_CONST(1) +#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE3_FIFO_OVERFLOW_RST _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE2_FIFO_OVERFLOW_SHIFT _MK_SHIFT_CONST(15) +#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE2_FIFO_OVERFLOW_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE2_FIFO_OVERFLOW_SHIFT) +#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE2_FIFO_OVERFLOW_RANGE 15:15 +#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE2_FIFO_OVERFLOW_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE2_FIFO_OVERFLOW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE2_FIFO_OVERFLOW_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE2_FIFO_OVERFLOW_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE2_FIFO_OVERFLOW_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE2_FIFO_OVERFLOW_INIT_ENUM NO +#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE2_FIFO_OVERFLOW_NO _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE2_FIFO_OVERFLOW_YES _MK_ENUM_CONST(1) +#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE2_FIFO_OVERFLOW_RST _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE1_FIFO_OVERFLOW_SHIFT _MK_SHIFT_CONST(14) +#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE1_FIFO_OVERFLOW_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE1_FIFO_OVERFLOW_SHIFT) +#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE1_FIFO_OVERFLOW_RANGE 14:14 +#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE1_FIFO_OVERFLOW_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE1_FIFO_OVERFLOW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE1_FIFO_OVERFLOW_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE1_FIFO_OVERFLOW_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE1_FIFO_OVERFLOW_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE1_FIFO_OVERFLOW_INIT_ENUM NO +#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE1_FIFO_OVERFLOW_NO _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE1_FIFO_OVERFLOW_YES _MK_ENUM_CONST(1) +#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE1_FIFO_OVERFLOW_RST _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE0_FIFO_OVERFLOW_SHIFT _MK_SHIFT_CONST(13) +#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE0_FIFO_OVERFLOW_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE0_FIFO_OVERFLOW_SHIFT) +#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE0_FIFO_OVERFLOW_RANGE 13:13 +#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE0_FIFO_OVERFLOW_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE0_FIFO_OVERFLOW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE0_FIFO_OVERFLOW_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE0_FIFO_OVERFLOW_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE0_FIFO_OVERFLOW_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE0_FIFO_OVERFLOW_INIT_ENUM NO +#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE0_FIFO_OVERFLOW_NO _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE0_FIFO_OVERFLOW_YES _MK_ENUM_CONST(1) +#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE0_FIFO_OVERFLOW_RST _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_SPKT_OVERRUN_SHIFT _MK_SHIFT_CONST(12) +#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_SPKT_OVERRUN_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_DP_DEBUG0_0_SPKT_OVERRUN_SHIFT) +#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_SPKT_OVERRUN_RANGE 12:12 +#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_SPKT_OVERRUN_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_SPKT_OVERRUN_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_SPKT_OVERRUN_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_SPKT_OVERRUN_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_SPKT_OVERRUN_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_SPKT_OVERRUN_INIT_ENUM NO +#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_SPKT_OVERRUN_NO _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_SPKT_OVERRUN_YES _MK_ENUM_CONST(1) +#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_SPKT_OVERRUN_RST _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE3_STEER_ERROR_SHIFT _MK_SHIFT_CONST(11) +#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE3_STEER_ERROR_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE3_STEER_ERROR_SHIFT) +#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE3_STEER_ERROR_RANGE 11:11 +#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE3_STEER_ERROR_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE3_STEER_ERROR_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE3_STEER_ERROR_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE3_STEER_ERROR_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE3_STEER_ERROR_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE3_STEER_ERROR_INIT_ENUM NO +#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE3_STEER_ERROR_NO _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE3_STEER_ERROR_YES _MK_ENUM_CONST(1) +#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE3_STEER_ERROR_RST _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE2_STEER_ERROR_SHIFT _MK_SHIFT_CONST(10) +#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE2_STEER_ERROR_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE2_STEER_ERROR_SHIFT) +#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE2_STEER_ERROR_RANGE 10:10 +#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE2_STEER_ERROR_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE2_STEER_ERROR_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE2_STEER_ERROR_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE2_STEER_ERROR_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE2_STEER_ERROR_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE2_STEER_ERROR_INIT_ENUM NO +#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE2_STEER_ERROR_NO _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE2_STEER_ERROR_YES _MK_ENUM_CONST(1) +#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE2_STEER_ERROR_RST _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE1_STEER_ERROR_SHIFT _MK_SHIFT_CONST(9) +#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE1_STEER_ERROR_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE1_STEER_ERROR_SHIFT) +#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE1_STEER_ERROR_RANGE 9:9 +#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE1_STEER_ERROR_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE1_STEER_ERROR_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE1_STEER_ERROR_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE1_STEER_ERROR_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE1_STEER_ERROR_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE1_STEER_ERROR_INIT_ENUM NO +#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE1_STEER_ERROR_NO _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE1_STEER_ERROR_YES _MK_ENUM_CONST(1) +#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE1_STEER_ERROR_RST _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE0_STEER_ERROR_SHIFT _MK_SHIFT_CONST(8) +#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE0_STEER_ERROR_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE0_STEER_ERROR_SHIFT) +#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE0_STEER_ERROR_RANGE 8:8 +#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE0_STEER_ERROR_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE0_STEER_ERROR_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE0_STEER_ERROR_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE0_STEER_ERROR_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE0_STEER_ERROR_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE0_STEER_ERROR_INIT_ENUM NO +#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE0_STEER_ERROR_NO _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE0_STEER_ERROR_YES _MK_ENUM_CONST(1) +#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE0_STEER_ERROR_RST _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE3_PIXPACK_OVERFLOW_SHIFT _MK_SHIFT_CONST(7) +#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE3_PIXPACK_OVERFLOW_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE3_PIXPACK_OVERFLOW_SHIFT) +#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE3_PIXPACK_OVERFLOW_RANGE 7:7 +#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE3_PIXPACK_OVERFLOW_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE3_PIXPACK_OVERFLOW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE3_PIXPACK_OVERFLOW_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE3_PIXPACK_OVERFLOW_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE3_PIXPACK_OVERFLOW_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE3_PIXPACK_OVERFLOW_INIT_ENUM NO +#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE3_PIXPACK_OVERFLOW_NO _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE3_PIXPACK_OVERFLOW_YES _MK_ENUM_CONST(1) +#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE3_PIXPACK_OVERFLOW_RST _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE2_PIXPACK_OVERFLOW_SHIFT _MK_SHIFT_CONST(6) +#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE2_PIXPACK_OVERFLOW_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE2_PIXPACK_OVERFLOW_SHIFT) +#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE2_PIXPACK_OVERFLOW_RANGE 6:6 +#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE2_PIXPACK_OVERFLOW_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE2_PIXPACK_OVERFLOW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE2_PIXPACK_OVERFLOW_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE2_PIXPACK_OVERFLOW_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE2_PIXPACK_OVERFLOW_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE2_PIXPACK_OVERFLOW_INIT_ENUM NO +#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE2_PIXPACK_OVERFLOW_NO _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE2_PIXPACK_OVERFLOW_YES _MK_ENUM_CONST(1) +#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE2_PIXPACK_OVERFLOW_RST _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE1_PIXPACK_OVERFLOW_SHIFT _MK_SHIFT_CONST(5) +#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE1_PIXPACK_OVERFLOW_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE1_PIXPACK_OVERFLOW_SHIFT) +#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE1_PIXPACK_OVERFLOW_RANGE 5:5 +#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE1_PIXPACK_OVERFLOW_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE1_PIXPACK_OVERFLOW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE1_PIXPACK_OVERFLOW_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE1_PIXPACK_OVERFLOW_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE1_PIXPACK_OVERFLOW_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE1_PIXPACK_OVERFLOW_INIT_ENUM NO +#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE1_PIXPACK_OVERFLOW_NO _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE1_PIXPACK_OVERFLOW_YES _MK_ENUM_CONST(1) +#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE1_PIXPACK_OVERFLOW_RST _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE0_PIXPACK_OVERFLOW_SHIFT _MK_SHIFT_CONST(4) +#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE0_PIXPACK_OVERFLOW_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE0_PIXPACK_OVERFLOW_SHIFT) +#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE0_PIXPACK_OVERFLOW_RANGE 4:4 +#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE0_PIXPACK_OVERFLOW_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE0_PIXPACK_OVERFLOW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE0_PIXPACK_OVERFLOW_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE0_PIXPACK_OVERFLOW_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE0_PIXPACK_OVERFLOW_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE0_PIXPACK_OVERFLOW_INIT_ENUM NO +#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE0_PIXPACK_OVERFLOW_NO _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE0_PIXPACK_OVERFLOW_YES _MK_ENUM_CONST(1) +#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE0_PIXPACK_OVERFLOW_RST _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE3_FIFO_UNDERFLOW_SHIFT _MK_SHIFT_CONST(3) +#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE3_FIFO_UNDERFLOW_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE3_FIFO_UNDERFLOW_SHIFT) +#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE3_FIFO_UNDERFLOW_RANGE 3:3 +#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE3_FIFO_UNDERFLOW_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE3_FIFO_UNDERFLOW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE3_FIFO_UNDERFLOW_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE3_FIFO_UNDERFLOW_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE3_FIFO_UNDERFLOW_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE3_FIFO_UNDERFLOW_INIT_ENUM NO +#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE3_FIFO_UNDERFLOW_NO _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE3_FIFO_UNDERFLOW_YES _MK_ENUM_CONST(1) +#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE3_FIFO_UNDERFLOW_RST _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE2_FIFO_UNDERFLOW_SHIFT _MK_SHIFT_CONST(2) +#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE2_FIFO_UNDERFLOW_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE2_FIFO_UNDERFLOW_SHIFT) +#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE2_FIFO_UNDERFLOW_RANGE 2:2 +#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE2_FIFO_UNDERFLOW_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE2_FIFO_UNDERFLOW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE2_FIFO_UNDERFLOW_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE2_FIFO_UNDERFLOW_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE2_FIFO_UNDERFLOW_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE2_FIFO_UNDERFLOW_INIT_ENUM NO +#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE2_FIFO_UNDERFLOW_NO _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE2_FIFO_UNDERFLOW_YES _MK_ENUM_CONST(1) +#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE2_FIFO_UNDERFLOW_RST _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE1_FIFO_UNDERFLOW_SHIFT _MK_SHIFT_CONST(1) +#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE1_FIFO_UNDERFLOW_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE1_FIFO_UNDERFLOW_SHIFT) +#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE1_FIFO_UNDERFLOW_RANGE 1:1 +#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE1_FIFO_UNDERFLOW_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE1_FIFO_UNDERFLOW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE1_FIFO_UNDERFLOW_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE1_FIFO_UNDERFLOW_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE1_FIFO_UNDERFLOW_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE1_FIFO_UNDERFLOW_INIT_ENUM NO +#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE1_FIFO_UNDERFLOW_NO _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE1_FIFO_UNDERFLOW_YES _MK_ENUM_CONST(1) +#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE1_FIFO_UNDERFLOW_RST _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE0_FIFO_UNDERFLOW_SHIFT _MK_SHIFT_CONST(0) +#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE0_FIFO_UNDERFLOW_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE0_FIFO_UNDERFLOW_SHIFT) +#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE0_FIFO_UNDERFLOW_RANGE 0:0 +#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE0_FIFO_UNDERFLOW_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE0_FIFO_UNDERFLOW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE0_FIFO_UNDERFLOW_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE0_FIFO_UNDERFLOW_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE0_FIFO_UNDERFLOW_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE0_FIFO_UNDERFLOW_INIT_ENUM NO +#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE0_FIFO_UNDERFLOW_NO _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE0_FIFO_UNDERFLOW_YES _MK_ENUM_CONST(1) +#define SOR_NV_PDISP_SOR_DP_DEBUG0_0_LANE0_FIFO_UNDERFLOW_RST _MK_ENUM_CONST(1) + + +// Register SOR_NV_PDISP_SOR_DP_DEBUG1_0 +#define SOR_NV_PDISP_SOR_DP_DEBUG1_0 _MK_ADDR_CONST(0x5f) +#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_SECURE 0x0 +#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_WORD_COUNT 0x1 +#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_RESET_VAL _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_RESET_MASK _MK_MASK_CONST(0x1ffff) +#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_READ_MASK _MK_MASK_CONST(0x1ffff) +#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_WRITE_MASK _MK_MASK_CONST(0x1ffff) +#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE3_FIFO_OVERFLOW_SHIFT _MK_SHIFT_CONST(16) +#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE3_FIFO_OVERFLOW_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE3_FIFO_OVERFLOW_SHIFT) +#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE3_FIFO_OVERFLOW_RANGE 16:16 +#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE3_FIFO_OVERFLOW_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE3_FIFO_OVERFLOW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE3_FIFO_OVERFLOW_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE3_FIFO_OVERFLOW_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE3_FIFO_OVERFLOW_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE3_FIFO_OVERFLOW_INIT_ENUM NO +#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE3_FIFO_OVERFLOW_NO _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE3_FIFO_OVERFLOW_YES _MK_ENUM_CONST(1) +#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE3_FIFO_OVERFLOW_RST _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE2_FIFO_OVERFLOW_SHIFT _MK_SHIFT_CONST(15) +#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE2_FIFO_OVERFLOW_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE2_FIFO_OVERFLOW_SHIFT) +#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE2_FIFO_OVERFLOW_RANGE 15:15 +#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE2_FIFO_OVERFLOW_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE2_FIFO_OVERFLOW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE2_FIFO_OVERFLOW_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE2_FIFO_OVERFLOW_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE2_FIFO_OVERFLOW_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE2_FIFO_OVERFLOW_INIT_ENUM NO +#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE2_FIFO_OVERFLOW_NO _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE2_FIFO_OVERFLOW_YES _MK_ENUM_CONST(1) +#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE2_FIFO_OVERFLOW_RST _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE1_FIFO_OVERFLOW_SHIFT _MK_SHIFT_CONST(14) +#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE1_FIFO_OVERFLOW_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE1_FIFO_OVERFLOW_SHIFT) +#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE1_FIFO_OVERFLOW_RANGE 14:14 +#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE1_FIFO_OVERFLOW_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE1_FIFO_OVERFLOW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE1_FIFO_OVERFLOW_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE1_FIFO_OVERFLOW_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE1_FIFO_OVERFLOW_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE1_FIFO_OVERFLOW_INIT_ENUM NO +#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE1_FIFO_OVERFLOW_NO _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE1_FIFO_OVERFLOW_YES _MK_ENUM_CONST(1) +#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE1_FIFO_OVERFLOW_RST _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE0_FIFO_OVERFLOW_SHIFT _MK_SHIFT_CONST(13) +#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE0_FIFO_OVERFLOW_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE0_FIFO_OVERFLOW_SHIFT) +#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE0_FIFO_OVERFLOW_RANGE 13:13 +#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE0_FIFO_OVERFLOW_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE0_FIFO_OVERFLOW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE0_FIFO_OVERFLOW_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE0_FIFO_OVERFLOW_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE0_FIFO_OVERFLOW_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE0_FIFO_OVERFLOW_INIT_ENUM NO +#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE0_FIFO_OVERFLOW_NO _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE0_FIFO_OVERFLOW_YES _MK_ENUM_CONST(1) +#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE0_FIFO_OVERFLOW_RST _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_SPKT_OVERRUN_SHIFT _MK_SHIFT_CONST(12) +#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_SPKT_OVERRUN_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_DP_DEBUG1_0_SPKT_OVERRUN_SHIFT) +#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_SPKT_OVERRUN_RANGE 12:12 +#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_SPKT_OVERRUN_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_SPKT_OVERRUN_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_SPKT_OVERRUN_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_SPKT_OVERRUN_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_SPKT_OVERRUN_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_SPKT_OVERRUN_INIT_ENUM NO +#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_SPKT_OVERRUN_NO _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_SPKT_OVERRUN_YES _MK_ENUM_CONST(1) +#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_SPKT_OVERRUN_RST _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE3_STEER_ERROR_SHIFT _MK_SHIFT_CONST(11) +#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE3_STEER_ERROR_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE3_STEER_ERROR_SHIFT) +#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE3_STEER_ERROR_RANGE 11:11 +#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE3_STEER_ERROR_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE3_STEER_ERROR_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE3_STEER_ERROR_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE3_STEER_ERROR_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE3_STEER_ERROR_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE3_STEER_ERROR_INIT_ENUM NO +#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE3_STEER_ERROR_NO _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE3_STEER_ERROR_YES _MK_ENUM_CONST(1) +#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE3_STEER_ERROR_RST _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE2_STEER_ERROR_SHIFT _MK_SHIFT_CONST(10) +#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE2_STEER_ERROR_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE2_STEER_ERROR_SHIFT) +#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE2_STEER_ERROR_RANGE 10:10 +#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE2_STEER_ERROR_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE2_STEER_ERROR_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE2_STEER_ERROR_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE2_STEER_ERROR_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE2_STEER_ERROR_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE2_STEER_ERROR_INIT_ENUM NO +#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE2_STEER_ERROR_NO _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE2_STEER_ERROR_YES _MK_ENUM_CONST(1) +#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE2_STEER_ERROR_RST _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE1_STEER_ERROR_SHIFT _MK_SHIFT_CONST(9) +#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE1_STEER_ERROR_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE1_STEER_ERROR_SHIFT) +#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE1_STEER_ERROR_RANGE 9:9 +#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE1_STEER_ERROR_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE1_STEER_ERROR_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE1_STEER_ERROR_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE1_STEER_ERROR_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE1_STEER_ERROR_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE1_STEER_ERROR_INIT_ENUM NO +#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE1_STEER_ERROR_NO _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE1_STEER_ERROR_YES _MK_ENUM_CONST(1) +#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE1_STEER_ERROR_RST _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE0_STEER_ERROR_SHIFT _MK_SHIFT_CONST(8) +#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE0_STEER_ERROR_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE0_STEER_ERROR_SHIFT) +#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE0_STEER_ERROR_RANGE 8:8 +#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE0_STEER_ERROR_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE0_STEER_ERROR_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE0_STEER_ERROR_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE0_STEER_ERROR_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE0_STEER_ERROR_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE0_STEER_ERROR_INIT_ENUM NO +#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE0_STEER_ERROR_NO _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE0_STEER_ERROR_YES _MK_ENUM_CONST(1) +#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE0_STEER_ERROR_RST _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE3_PIXPACK_OVERFLOW_SHIFT _MK_SHIFT_CONST(7) +#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE3_PIXPACK_OVERFLOW_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE3_PIXPACK_OVERFLOW_SHIFT) +#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE3_PIXPACK_OVERFLOW_RANGE 7:7 +#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE3_PIXPACK_OVERFLOW_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE3_PIXPACK_OVERFLOW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE3_PIXPACK_OVERFLOW_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE3_PIXPACK_OVERFLOW_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE3_PIXPACK_OVERFLOW_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE3_PIXPACK_OVERFLOW_INIT_ENUM NO +#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE3_PIXPACK_OVERFLOW_NO _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE3_PIXPACK_OVERFLOW_YES _MK_ENUM_CONST(1) +#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE3_PIXPACK_OVERFLOW_RST _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE2_PIXPACK_OVERFLOW_SHIFT _MK_SHIFT_CONST(6) +#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE2_PIXPACK_OVERFLOW_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE2_PIXPACK_OVERFLOW_SHIFT) +#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE2_PIXPACK_OVERFLOW_RANGE 6:6 +#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE2_PIXPACK_OVERFLOW_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE2_PIXPACK_OVERFLOW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE2_PIXPACK_OVERFLOW_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE2_PIXPACK_OVERFLOW_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE2_PIXPACK_OVERFLOW_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE2_PIXPACK_OVERFLOW_INIT_ENUM NO +#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE2_PIXPACK_OVERFLOW_NO _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE2_PIXPACK_OVERFLOW_YES _MK_ENUM_CONST(1) +#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE2_PIXPACK_OVERFLOW_RST _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE1_PIXPACK_OVERFLOW_SHIFT _MK_SHIFT_CONST(5) +#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE1_PIXPACK_OVERFLOW_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE1_PIXPACK_OVERFLOW_SHIFT) +#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE1_PIXPACK_OVERFLOW_RANGE 5:5 +#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE1_PIXPACK_OVERFLOW_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE1_PIXPACK_OVERFLOW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE1_PIXPACK_OVERFLOW_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE1_PIXPACK_OVERFLOW_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE1_PIXPACK_OVERFLOW_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE1_PIXPACK_OVERFLOW_INIT_ENUM NO +#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE1_PIXPACK_OVERFLOW_NO _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE1_PIXPACK_OVERFLOW_YES _MK_ENUM_CONST(1) +#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE1_PIXPACK_OVERFLOW_RST _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE0_PIXPACK_OVERFLOW_SHIFT _MK_SHIFT_CONST(4) +#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE0_PIXPACK_OVERFLOW_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE0_PIXPACK_OVERFLOW_SHIFT) +#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE0_PIXPACK_OVERFLOW_RANGE 4:4 +#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE0_PIXPACK_OVERFLOW_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE0_PIXPACK_OVERFLOW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE0_PIXPACK_OVERFLOW_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE0_PIXPACK_OVERFLOW_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE0_PIXPACK_OVERFLOW_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE0_PIXPACK_OVERFLOW_INIT_ENUM NO +#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE0_PIXPACK_OVERFLOW_NO _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE0_PIXPACK_OVERFLOW_YES _MK_ENUM_CONST(1) +#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE0_PIXPACK_OVERFLOW_RST _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE3_FIFO_UNDERFLOW_SHIFT _MK_SHIFT_CONST(3) +#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE3_FIFO_UNDERFLOW_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE3_FIFO_UNDERFLOW_SHIFT) +#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE3_FIFO_UNDERFLOW_RANGE 3:3 +#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE3_FIFO_UNDERFLOW_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE3_FIFO_UNDERFLOW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE3_FIFO_UNDERFLOW_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE3_FIFO_UNDERFLOW_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE3_FIFO_UNDERFLOW_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE3_FIFO_UNDERFLOW_INIT_ENUM NO +#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE3_FIFO_UNDERFLOW_NO _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE3_FIFO_UNDERFLOW_YES _MK_ENUM_CONST(1) +#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE3_FIFO_UNDERFLOW_RST _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE2_FIFO_UNDERFLOW_SHIFT _MK_SHIFT_CONST(2) +#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE2_FIFO_UNDERFLOW_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE2_FIFO_UNDERFLOW_SHIFT) +#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE2_FIFO_UNDERFLOW_RANGE 2:2 +#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE2_FIFO_UNDERFLOW_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE2_FIFO_UNDERFLOW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE2_FIFO_UNDERFLOW_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE2_FIFO_UNDERFLOW_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE2_FIFO_UNDERFLOW_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE2_FIFO_UNDERFLOW_INIT_ENUM NO +#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE2_FIFO_UNDERFLOW_NO _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE2_FIFO_UNDERFLOW_YES _MK_ENUM_CONST(1) +#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE2_FIFO_UNDERFLOW_RST _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE1_FIFO_UNDERFLOW_SHIFT _MK_SHIFT_CONST(1) +#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE1_FIFO_UNDERFLOW_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE1_FIFO_UNDERFLOW_SHIFT) +#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE1_FIFO_UNDERFLOW_RANGE 1:1 +#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE1_FIFO_UNDERFLOW_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE1_FIFO_UNDERFLOW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE1_FIFO_UNDERFLOW_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE1_FIFO_UNDERFLOW_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE1_FIFO_UNDERFLOW_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE1_FIFO_UNDERFLOW_INIT_ENUM NO +#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE1_FIFO_UNDERFLOW_NO _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE1_FIFO_UNDERFLOW_YES _MK_ENUM_CONST(1) +#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE1_FIFO_UNDERFLOW_RST _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE0_FIFO_UNDERFLOW_SHIFT _MK_SHIFT_CONST(0) +#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE0_FIFO_UNDERFLOW_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE0_FIFO_UNDERFLOW_SHIFT) +#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE0_FIFO_UNDERFLOW_RANGE 0:0 +#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE0_FIFO_UNDERFLOW_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE0_FIFO_UNDERFLOW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE0_FIFO_UNDERFLOW_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE0_FIFO_UNDERFLOW_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE0_FIFO_UNDERFLOW_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE0_FIFO_UNDERFLOW_INIT_ENUM NO +#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE0_FIFO_UNDERFLOW_NO _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE0_FIFO_UNDERFLOW_YES _MK_ENUM_CONST(1) +#define SOR_NV_PDISP_SOR_DP_DEBUG1_0_LANE0_FIFO_UNDERFLOW_RST _MK_ENUM_CONST(1) + + +// Register SOR_NV_PDISP_SOR_DP_SPARE0_0 +#define SOR_NV_PDISP_SOR_DP_SPARE0_0 _MK_ADDR_CONST(0x60) +#define SOR_NV_PDISP_SOR_DP_SPARE0_0_SECURE 0x0 +#define SOR_NV_PDISP_SOR_DP_SPARE0_0_WORD_COUNT 0x1 +#define SOR_NV_PDISP_SOR_DP_SPARE0_0_RESET_VAL _MK_MASK_CONST(0x2) +#define SOR_NV_PDISP_SOR_DP_SPARE0_0_RESET_MASK _MK_MASK_CONST(0xffffffff) +#define SOR_NV_PDISP_SOR_DP_SPARE0_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_SPARE0_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_SPARE0_0_READ_MASK _MK_MASK_CONST(0xffffffff) +#define SOR_NV_PDISP_SOR_DP_SPARE0_0_WRITE_MASK _MK_MASK_CONST(0xffffffff) +#define SOR_NV_PDISP_SOR_DP_SPARE0_0_REG_SHIFT _MK_SHIFT_CONST(3) +#define SOR_NV_PDISP_SOR_DP_SPARE0_0_REG_FIELD _MK_FIELD_CONST(0x1fffffff, SOR_NV_PDISP_SOR_DP_SPARE0_0_REG_SHIFT) +#define SOR_NV_PDISP_SOR_DP_SPARE0_0_REG_RANGE 31:3 +#define SOR_NV_PDISP_SOR_DP_SPARE0_0_REG_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_DP_SPARE0_0_REG_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_SPARE0_0_REG_DEFAULT_MASK _MK_MASK_CONST(0x1fffffff) +#define SOR_NV_PDISP_SOR_DP_SPARE0_0_REG_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_SPARE0_0_REG_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define SOR_NV_PDISP_SOR_DP_SPARE0_0_SOR_CLK_SEL_SHIFT _MK_SHIFT_CONST(2) +#define SOR_NV_PDISP_SOR_DP_SPARE0_0_SOR_CLK_SEL_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_DP_SPARE0_0_SOR_CLK_SEL_SHIFT) +#define SOR_NV_PDISP_SOR_DP_SPARE0_0_SOR_CLK_SEL_RANGE 2:2 +#define SOR_NV_PDISP_SOR_DP_SPARE0_0_SOR_CLK_SEL_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_DP_SPARE0_0_SOR_CLK_SEL_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_SPARE0_0_SOR_CLK_SEL_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_DP_SPARE0_0_SOR_CLK_SEL_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_SPARE0_0_SOR_CLK_SEL_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_SPARE0_0_SOR_CLK_SEL_INIT_ENUM SAFE_SORCLK +#define SOR_NV_PDISP_SOR_DP_SPARE0_0_SOR_CLK_SEL_SAFE_SORCLK _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_DP_SPARE0_0_SOR_CLK_SEL_MACRO_SORCLK _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_DP_SPARE0_0_PANEL_SHIFT _MK_SHIFT_CONST(1) +#define SOR_NV_PDISP_SOR_DP_SPARE0_0_PANEL_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_DP_SPARE0_0_PANEL_SHIFT) +#define SOR_NV_PDISP_SOR_DP_SPARE0_0_PANEL_RANGE 1:1 +#define SOR_NV_PDISP_SOR_DP_SPARE0_0_PANEL_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_DP_SPARE0_0_PANEL_DEFAULT _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_DP_SPARE0_0_PANEL_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_DP_SPARE0_0_PANEL_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_SPARE0_0_PANEL_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_SPARE0_0_PANEL_INIT_ENUM INTERNAL +#define SOR_NV_PDISP_SOR_DP_SPARE0_0_PANEL_EXTERNAL _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_DP_SPARE0_0_PANEL_INTERNAL _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_DP_SPARE0_0_SEQ_ENABLE_SHIFT _MK_SHIFT_CONST(0) +#define SOR_NV_PDISP_SOR_DP_SPARE0_0_SEQ_ENABLE_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_DP_SPARE0_0_SEQ_ENABLE_SHIFT) +#define SOR_NV_PDISP_SOR_DP_SPARE0_0_SEQ_ENABLE_RANGE 0:0 +#define SOR_NV_PDISP_SOR_DP_SPARE0_0_SEQ_ENABLE_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_DP_SPARE0_0_SEQ_ENABLE_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_SPARE0_0_SEQ_ENABLE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_DP_SPARE0_0_SEQ_ENABLE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_SPARE0_0_SEQ_ENABLE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_SPARE0_0_SEQ_ENABLE_INIT_ENUM NO +#define SOR_NV_PDISP_SOR_DP_SPARE0_0_SEQ_ENABLE_NO _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_DP_SPARE0_0_SEQ_ENABLE_YES _MK_ENUM_CONST(1) + + +// Register SOR_NV_PDISP_SOR_DP_SPARE1_0 +#define SOR_NV_PDISP_SOR_DP_SPARE1_0 _MK_ADDR_CONST(0x61) +#define SOR_NV_PDISP_SOR_DP_SPARE1_0_SECURE 0x0 +#define SOR_NV_PDISP_SOR_DP_SPARE1_0_WORD_COUNT 0x1 +#define SOR_NV_PDISP_SOR_DP_SPARE1_0_RESET_VAL _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_SPARE1_0_RESET_MASK _MK_MASK_CONST(0xffffffff) +#define SOR_NV_PDISP_SOR_DP_SPARE1_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_SPARE1_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_SPARE1_0_READ_MASK _MK_MASK_CONST(0xffffffff) +#define SOR_NV_PDISP_SOR_DP_SPARE1_0_WRITE_MASK _MK_MASK_CONST(0xffffffff) +#define SOR_NV_PDISP_SOR_DP_SPARE1_0_REG_SHIFT _MK_SHIFT_CONST(3) +#define SOR_NV_PDISP_SOR_DP_SPARE1_0_REG_FIELD _MK_FIELD_CONST(0x1fffffff, SOR_NV_PDISP_SOR_DP_SPARE1_0_REG_SHIFT) +#define SOR_NV_PDISP_SOR_DP_SPARE1_0_REG_RANGE 31:3 +#define SOR_NV_PDISP_SOR_DP_SPARE1_0_REG_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_DP_SPARE1_0_REG_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_SPARE1_0_REG_DEFAULT_MASK _MK_MASK_CONST(0x1fffffff) +#define SOR_NV_PDISP_SOR_DP_SPARE1_0_REG_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_SPARE1_0_REG_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define SOR_NV_PDISP_SOR_DP_SPARE1_0_SOR_CLK_SEL_SHIFT _MK_SHIFT_CONST(2) +#define SOR_NV_PDISP_SOR_DP_SPARE1_0_SOR_CLK_SEL_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_DP_SPARE1_0_SOR_CLK_SEL_SHIFT) +#define SOR_NV_PDISP_SOR_DP_SPARE1_0_SOR_CLK_SEL_RANGE 2:2 +#define SOR_NV_PDISP_SOR_DP_SPARE1_0_SOR_CLK_SEL_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_DP_SPARE1_0_SOR_CLK_SEL_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_SPARE1_0_SOR_CLK_SEL_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_DP_SPARE1_0_SOR_CLK_SEL_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_SPARE1_0_SOR_CLK_SEL_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_SPARE1_0_SOR_CLK_SEL_INIT_ENUM SAFE_SORCLK +#define SOR_NV_PDISP_SOR_DP_SPARE1_0_SOR_CLK_SEL_SAFE_SORCLK _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_DP_SPARE1_0_SOR_CLK_SEL_MACRO_SORCLK _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_DP_SPARE1_0_PANEL_SHIFT _MK_SHIFT_CONST(1) +#define SOR_NV_PDISP_SOR_DP_SPARE1_0_PANEL_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_DP_SPARE1_0_PANEL_SHIFT) +#define SOR_NV_PDISP_SOR_DP_SPARE1_0_PANEL_RANGE 1:1 +#define SOR_NV_PDISP_SOR_DP_SPARE1_0_PANEL_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_DP_SPARE1_0_PANEL_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_SPARE1_0_PANEL_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_DP_SPARE1_0_PANEL_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_SPARE1_0_PANEL_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_SPARE1_0_PANEL_INIT_ENUM EXTERNAL +#define SOR_NV_PDISP_SOR_DP_SPARE1_0_PANEL_EXTERNAL _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_DP_SPARE1_0_PANEL_INTERNAL _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_DP_SPARE1_0_SEQ_ENABLE_SHIFT _MK_SHIFT_CONST(0) +#define SOR_NV_PDISP_SOR_DP_SPARE1_0_SEQ_ENABLE_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_DP_SPARE1_0_SEQ_ENABLE_SHIFT) +#define SOR_NV_PDISP_SOR_DP_SPARE1_0_SEQ_ENABLE_RANGE 0:0 +#define SOR_NV_PDISP_SOR_DP_SPARE1_0_SEQ_ENABLE_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_DP_SPARE1_0_SEQ_ENABLE_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_SPARE1_0_SEQ_ENABLE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_DP_SPARE1_0_SEQ_ENABLE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_SPARE1_0_SEQ_ENABLE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_SPARE1_0_SEQ_ENABLE_INIT_ENUM NO +#define SOR_NV_PDISP_SOR_DP_SPARE1_0_SEQ_ENABLE_NO _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_DP_SPARE1_0_SEQ_ENABLE_YES _MK_ENUM_CONST(1) + + +// Register SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0 +#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0 _MK_ADDR_CONST(0x62) +#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_SECURE 0x0 +#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_WORD_COUNT 0x1 +#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_RESET_VAL _MK_MASK_CONST(0x1f0001) +#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_RESET_MASK _MK_MASK_CONST(0x801fffcd) +#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_READ_MASK _MK_MASK_CONST(0x803fffcd) +#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_WRITE_MASK _MK_MASK_CONST(0x801fffcd) +#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_NEW_SETTINGS_SHIFT _MK_SHIFT_CONST(31) +#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_NEW_SETTINGS_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_NEW_SETTINGS_SHIFT) +#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_NEW_SETTINGS_RANGE 31:31 +#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_NEW_SETTINGS_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_NEW_SETTINGS_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_NEW_SETTINGS_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_NEW_SETTINGS_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_NEW_SETTINGS_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_NEW_SETTINGS_INIT_ENUM DONE +#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_NEW_SETTINGS_DONE _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_NEW_SETTINGS_PENDING _MK_ENUM_CONST(1) +#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_NEW_SETTINGS_TRIGGER _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_MUTE_STATUS_SHIFT _MK_SHIFT_CONST(21) +#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_MUTE_STATUS_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_MUTE_STATUS_SHIFT) +#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_MUTE_STATUS_RANGE 21:21 +#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_MUTE_STATUS_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_MUTE_STATUS_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_MUTE_STATUS_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_MUTE_STATUS_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_MUTE_STATUS_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_MUTE_STATUS_DISABLE _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_MUTE_STATUS_ENABLE _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_CA_SELECT_SHIFT _MK_SHIFT_CONST(20) +#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_CA_SELECT_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_CA_SELECT_SHIFT) +#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_CA_SELECT_RANGE 20:20 +#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_CA_SELECT_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_CA_SELECT_DEFAULT _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_CA_SELECT_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_CA_SELECT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_CA_SELECT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_CA_SELECT_INIT_ENUM HW +#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_CA_SELECT_SW _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_CA_SELECT_HW _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_SS_SELECT_SHIFT _MK_SHIFT_CONST(19) +#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_SS_SELECT_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_SS_SELECT_SHIFT) +#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_SS_SELECT_RANGE 19:19 +#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_SS_SELECT_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_SS_SELECT_DEFAULT _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_SS_SELECT_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_SS_SELECT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_SS_SELECT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_SS_SELECT_INIT_ENUM HW +#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_SS_SELECT_SW _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_SS_SELECT_HW _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_SF_SELECT_SHIFT _MK_SHIFT_CONST(18) +#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_SF_SELECT_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_SF_SELECT_SHIFT) +#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_SF_SELECT_RANGE 18:18 +#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_SF_SELECT_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_SF_SELECT_DEFAULT _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_SF_SELECT_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_SF_SELECT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_SF_SELECT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_SF_SELECT_INIT_ENUM HW +#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_SF_SELECT_SW _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_SF_SELECT_HW _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_CC_SELECT_SHIFT _MK_SHIFT_CONST(17) +#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_CC_SELECT_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_CC_SELECT_SHIFT) +#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_CC_SELECT_RANGE 17:17 +#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_CC_SELECT_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_CC_SELECT_DEFAULT _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_CC_SELECT_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_CC_SELECT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_CC_SELECT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_CC_SELECT_INIT_ENUM HW +#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_CC_SELECT_SW _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_CC_SELECT_HW _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_CT_SELECT_SHIFT _MK_SHIFT_CONST(16) +#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_CT_SELECT_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_CT_SELECT_SHIFT) +#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_CT_SELECT_RANGE 16:16 +#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_CT_SELECT_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_CT_SELECT_DEFAULT _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_CT_SELECT_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_CT_SELECT_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_CT_SELECT_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_CT_SELECT_INIT_ENUM HW +#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_CT_SELECT_SW _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_CT_SELECT_HW _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_PACKET_ID_SHIFT _MK_SHIFT_CONST(8) +#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_PACKET_ID_FIELD _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_PACKET_ID_SHIFT) +#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_PACKET_ID_RANGE 15:8 +#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_PACKET_ID_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_PACKET_ID_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_PACKET_ID_DEFAULT_MASK _MK_MASK_CONST(0xff) +#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_PACKET_ID_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_PACKET_ID_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_GENERIC_INFOFRAME_ENABLE_SHIFT _MK_SHIFT_CONST(7) +#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_GENERIC_INFOFRAME_ENABLE_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_GENERIC_INFOFRAME_ENABLE_SHIFT) +#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_GENERIC_INFOFRAME_ENABLE_RANGE 7:7 +#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_GENERIC_INFOFRAME_ENABLE_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_GENERIC_INFOFRAME_ENABLE_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_GENERIC_INFOFRAME_ENABLE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_GENERIC_INFOFRAME_ENABLE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_GENERIC_INFOFRAME_ENABLE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_GENERIC_INFOFRAME_ENABLE_INIT_ENUM NO +#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_GENERIC_INFOFRAME_ENABLE_NO _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_GENERIC_INFOFRAME_ENABLE_YES _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_INFOFRAME_HEADER_OVERRIDE_SHIFT _MK_SHIFT_CONST(6) +#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_INFOFRAME_HEADER_OVERRIDE_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_INFOFRAME_HEADER_OVERRIDE_SHIFT) +#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_INFOFRAME_HEADER_OVERRIDE_RANGE 6:6 +#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_INFOFRAME_HEADER_OVERRIDE_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_INFOFRAME_HEADER_OVERRIDE_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_INFOFRAME_HEADER_OVERRIDE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_INFOFRAME_HEADER_OVERRIDE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_INFOFRAME_HEADER_OVERRIDE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_INFOFRAME_HEADER_OVERRIDE_INIT_ENUM DISABLE +#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_INFOFRAME_HEADER_OVERRIDE_DISABLE _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_INFOFRAME_HEADER_OVERRIDE_ENABLE _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_MUTE_SHIFT _MK_SHIFT_CONST(2) +#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_MUTE_FIELD _MK_FIELD_CONST(0x3, SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_MUTE_SHIFT) +#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_MUTE_RANGE 3:2 +#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_MUTE_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_MUTE_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_MUTE_DEFAULT_MASK _MK_MASK_CONST(0x3) +#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_MUTE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_MUTE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_MUTE_INIT_ENUM AUTO +#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_MUTE_AUTO _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_MUTE_DISABLE _MK_ENUM_CONST(1) +#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_MUTE_ENABLE _MK_ENUM_CONST(2) + +#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_ENABLE_SHIFT _MK_SHIFT_CONST(0) +#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_ENABLE_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_ENABLE_SHIFT) +#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_ENABLE_RANGE 0:0 +#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_ENABLE_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_ENABLE_DEFAULT _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_ENABLE_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_ENABLE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_ENABLE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_ENABLE_INIT_ENUM YES +#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_ENABLE_NO _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0_ENABLE_YES _MK_ENUM_CONST(1) + + +// Register SOR_NV_PDISP_SOR_DP_AUDIO_HBLANK_SYMBOLS_0 +#define SOR_NV_PDISP_SOR_DP_AUDIO_HBLANK_SYMBOLS_0 _MK_ADDR_CONST(0x63) +#define SOR_NV_PDISP_SOR_DP_AUDIO_HBLANK_SYMBOLS_0_SECURE 0x0 +#define SOR_NV_PDISP_SOR_DP_AUDIO_HBLANK_SYMBOLS_0_WORD_COUNT 0x1 +#define SOR_NV_PDISP_SOR_DP_AUDIO_HBLANK_SYMBOLS_0_RESET_VAL _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_AUDIO_HBLANK_SYMBOLS_0_RESET_MASK _MK_MASK_CONST(0x1ffff) +#define SOR_NV_PDISP_SOR_DP_AUDIO_HBLANK_SYMBOLS_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_AUDIO_HBLANK_SYMBOLS_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_AUDIO_HBLANK_SYMBOLS_0_READ_MASK _MK_MASK_CONST(0x1ffff) +#define SOR_NV_PDISP_SOR_DP_AUDIO_HBLANK_SYMBOLS_0_WRITE_MASK _MK_MASK_CONST(0x1ffff) +#define SOR_NV_PDISP_SOR_DP_AUDIO_HBLANK_SYMBOLS_0_VALUE_SHIFT _MK_SHIFT_CONST(0) +#define SOR_NV_PDISP_SOR_DP_AUDIO_HBLANK_SYMBOLS_0_VALUE_FIELD _MK_FIELD_CONST(0x1ffff, SOR_NV_PDISP_SOR_DP_AUDIO_HBLANK_SYMBOLS_0_VALUE_SHIFT) +#define SOR_NV_PDISP_SOR_DP_AUDIO_HBLANK_SYMBOLS_0_VALUE_RANGE 16:0 +#define SOR_NV_PDISP_SOR_DP_AUDIO_HBLANK_SYMBOLS_0_VALUE_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_DP_AUDIO_HBLANK_SYMBOLS_0_VALUE_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_AUDIO_HBLANK_SYMBOLS_0_VALUE_DEFAULT_MASK _MK_MASK_CONST(0x1ffff) +#define SOR_NV_PDISP_SOR_DP_AUDIO_HBLANK_SYMBOLS_0_VALUE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_AUDIO_HBLANK_SYMBOLS_0_VALUE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register SOR_NV_PDISP_SOR_DP_AUDIO_VBLANK_SYMBOLS_0 +#define SOR_NV_PDISP_SOR_DP_AUDIO_VBLANK_SYMBOLS_0 _MK_ADDR_CONST(0x64) +#define SOR_NV_PDISP_SOR_DP_AUDIO_VBLANK_SYMBOLS_0_SECURE 0x0 +#define SOR_NV_PDISP_SOR_DP_AUDIO_VBLANK_SYMBOLS_0_WORD_COUNT 0x1 +#define SOR_NV_PDISP_SOR_DP_AUDIO_VBLANK_SYMBOLS_0_RESET_VAL _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_AUDIO_VBLANK_SYMBOLS_0_RESET_MASK _MK_MASK_CONST(0x1fffff) +#define SOR_NV_PDISP_SOR_DP_AUDIO_VBLANK_SYMBOLS_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_AUDIO_VBLANK_SYMBOLS_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_AUDIO_VBLANK_SYMBOLS_0_READ_MASK _MK_MASK_CONST(0x1fffff) +#define SOR_NV_PDISP_SOR_DP_AUDIO_VBLANK_SYMBOLS_0_WRITE_MASK _MK_MASK_CONST(0x1fffff) +#define SOR_NV_PDISP_SOR_DP_AUDIO_VBLANK_SYMBOLS_0_VALUE_SHIFT _MK_SHIFT_CONST(0) +#define SOR_NV_PDISP_SOR_DP_AUDIO_VBLANK_SYMBOLS_0_VALUE_FIELD _MK_FIELD_CONST(0x1fffff, SOR_NV_PDISP_SOR_DP_AUDIO_VBLANK_SYMBOLS_0_VALUE_SHIFT) +#define SOR_NV_PDISP_SOR_DP_AUDIO_VBLANK_SYMBOLS_0_VALUE_RANGE 20:0 +#define SOR_NV_PDISP_SOR_DP_AUDIO_VBLANK_SYMBOLS_0_VALUE_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_DP_AUDIO_VBLANK_SYMBOLS_0_VALUE_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_AUDIO_VBLANK_SYMBOLS_0_VALUE_DEFAULT_MASK _MK_MASK_CONST(0x1fffff) +#define SOR_NV_PDISP_SOR_DP_AUDIO_VBLANK_SYMBOLS_0_VALUE_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_AUDIO_VBLANK_SYMBOLS_0_VALUE_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_HEADER_0 +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_HEADER_0 _MK_ADDR_CONST(0x65) +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_HEADER_0_SECURE 0x0 +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_HEADER_0_WORD_COUNT 0x1 +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_HEADER_0_RESET_VAL _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_HEADER_0_RESET_MASK _MK_MASK_CONST(0xffffffff) +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_HEADER_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_HEADER_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_HEADER_0_READ_MASK _MK_MASK_CONST(0xffffffff) +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_HEADER_0_WRITE_MASK _MK_MASK_CONST(0xffffffff) +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_HEADER_0_HB3_SHIFT _MK_SHIFT_CONST(24) +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_HEADER_0_HB3_FIELD _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_HEADER_0_HB3_SHIFT) +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_HEADER_0_HB3_RANGE 31:24 +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_HEADER_0_HB3_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_HEADER_0_HB3_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_HEADER_0_HB3_DEFAULT_MASK _MK_MASK_CONST(0xff) +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_HEADER_0_HB3_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_HEADER_0_HB3_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_HEADER_0_HB2_SHIFT _MK_SHIFT_CONST(16) +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_HEADER_0_HB2_FIELD _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_HEADER_0_HB2_SHIFT) +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_HEADER_0_HB2_RANGE 23:16 +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_HEADER_0_HB2_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_HEADER_0_HB2_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_HEADER_0_HB2_DEFAULT_MASK _MK_MASK_CONST(0xff) +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_HEADER_0_HB2_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_HEADER_0_HB2_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_HEADER_0_HB1_SHIFT _MK_SHIFT_CONST(8) +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_HEADER_0_HB1_FIELD _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_HEADER_0_HB1_SHIFT) +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_HEADER_0_HB1_RANGE 15:8 +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_HEADER_0_HB1_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_HEADER_0_HB1_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_HEADER_0_HB1_DEFAULT_MASK _MK_MASK_CONST(0xff) +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_HEADER_0_HB1_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_HEADER_0_HB1_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_HEADER_0_HB0_SHIFT _MK_SHIFT_CONST(0) +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_HEADER_0_HB0_FIELD _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_HEADER_0_HB0_SHIFT) +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_HEADER_0_HB0_RANGE 7:0 +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_HEADER_0_HB0_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_HEADER_0_HB0_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_HEADER_0_HB0_DEFAULT_MASK _MK_MASK_CONST(0xff) +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_HEADER_0_HB0_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_HEADER_0_HB0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK0_0 +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK0_0 _MK_ADDR_CONST(0x66) +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK0_0_SECURE 0x0 +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK0_0_WORD_COUNT 0x1 +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK0_0_RESET_VAL _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK0_0_RESET_MASK _MK_MASK_CONST(0xffffffff) +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK0_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK0_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK0_0_READ_MASK _MK_MASK_CONST(0xffffffff) +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK0_0_WRITE_MASK _MK_MASK_CONST(0xffffffff) +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK0_0_DB3_SHIFT _MK_SHIFT_CONST(24) +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK0_0_DB3_FIELD _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK0_0_DB3_SHIFT) +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK0_0_DB3_RANGE 31:24 +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK0_0_DB3_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK0_0_DB3_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK0_0_DB3_DEFAULT_MASK _MK_MASK_CONST(0xff) +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK0_0_DB3_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK0_0_DB3_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK0_0_DB2_SHIFT _MK_SHIFT_CONST(16) +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK0_0_DB2_FIELD _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK0_0_DB2_SHIFT) +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK0_0_DB2_RANGE 23:16 +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK0_0_DB2_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK0_0_DB2_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK0_0_DB2_DEFAULT_MASK _MK_MASK_CONST(0xff) +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK0_0_DB2_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK0_0_DB2_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK0_0_DB1_SHIFT _MK_SHIFT_CONST(8) +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK0_0_DB1_FIELD _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK0_0_DB1_SHIFT) +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK0_0_DB1_RANGE 15:8 +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK0_0_DB1_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK0_0_DB1_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK0_0_DB1_DEFAULT_MASK _MK_MASK_CONST(0xff) +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK0_0_DB1_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK0_0_DB1_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK0_0_DB0_SHIFT _MK_SHIFT_CONST(0) +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK0_0_DB0_FIELD _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK0_0_DB0_SHIFT) +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK0_0_DB0_RANGE 7:0 +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK0_0_DB0_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK0_0_DB0_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK0_0_DB0_DEFAULT_MASK _MK_MASK_CONST(0xff) +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK0_0_DB0_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK0_0_DB0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK1_0 +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK1_0 _MK_ADDR_CONST(0x67) +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK1_0_SECURE 0x0 +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK1_0_WORD_COUNT 0x1 +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK1_0_RESET_VAL _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK1_0_RESET_MASK _MK_MASK_CONST(0xffffffff) +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK1_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK1_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK1_0_READ_MASK _MK_MASK_CONST(0xffffffff) +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK1_0_WRITE_MASK _MK_MASK_CONST(0xffffffff) +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK1_0_DB7_SHIFT _MK_SHIFT_CONST(24) +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK1_0_DB7_FIELD _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK1_0_DB7_SHIFT) +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK1_0_DB7_RANGE 31:24 +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK1_0_DB7_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK1_0_DB7_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK1_0_DB7_DEFAULT_MASK _MK_MASK_CONST(0xff) +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK1_0_DB7_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK1_0_DB7_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK1_0_DB6_SHIFT _MK_SHIFT_CONST(16) +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK1_0_DB6_FIELD _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK1_0_DB6_SHIFT) +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK1_0_DB6_RANGE 23:16 +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK1_0_DB6_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK1_0_DB6_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK1_0_DB6_DEFAULT_MASK _MK_MASK_CONST(0xff) +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK1_0_DB6_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK1_0_DB6_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK1_0_DB5_SHIFT _MK_SHIFT_CONST(8) +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK1_0_DB5_FIELD _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK1_0_DB5_SHIFT) +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK1_0_DB5_RANGE 15:8 +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK1_0_DB5_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK1_0_DB5_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK1_0_DB5_DEFAULT_MASK _MK_MASK_CONST(0xff) +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK1_0_DB5_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK1_0_DB5_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK1_0_DB4_SHIFT _MK_SHIFT_CONST(0) +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK1_0_DB4_FIELD _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK1_0_DB4_SHIFT) +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK1_0_DB4_RANGE 7:0 +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK1_0_DB4_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK1_0_DB4_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK1_0_DB4_DEFAULT_MASK _MK_MASK_CONST(0xff) +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK1_0_DB4_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK1_0_DB4_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK2_0 +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK2_0 _MK_ADDR_CONST(0x68) +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK2_0_SECURE 0x0 +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK2_0_WORD_COUNT 0x1 +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK2_0_RESET_VAL _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK2_0_RESET_MASK _MK_MASK_CONST(0xffffffff) +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK2_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK2_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK2_0_READ_MASK _MK_MASK_CONST(0xffffffff) +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK2_0_WRITE_MASK _MK_MASK_CONST(0xffffffff) +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK2_0_DB11_SHIFT _MK_SHIFT_CONST(24) +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK2_0_DB11_FIELD _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK2_0_DB11_SHIFT) +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK2_0_DB11_RANGE 31:24 +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK2_0_DB11_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK2_0_DB11_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK2_0_DB11_DEFAULT_MASK _MK_MASK_CONST(0xff) +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK2_0_DB11_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK2_0_DB11_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK2_0_DB10_SHIFT _MK_SHIFT_CONST(16) +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK2_0_DB10_FIELD _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK2_0_DB10_SHIFT) +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK2_0_DB10_RANGE 23:16 +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK2_0_DB10_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK2_0_DB10_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK2_0_DB10_DEFAULT_MASK _MK_MASK_CONST(0xff) +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK2_0_DB10_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK2_0_DB10_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK2_0_DB9_SHIFT _MK_SHIFT_CONST(8) +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK2_0_DB9_FIELD _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK2_0_DB9_SHIFT) +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK2_0_DB9_RANGE 15:8 +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK2_0_DB9_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK2_0_DB9_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK2_0_DB9_DEFAULT_MASK _MK_MASK_CONST(0xff) +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK2_0_DB9_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK2_0_DB9_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK2_0_DB8_SHIFT _MK_SHIFT_CONST(0) +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK2_0_DB8_FIELD _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK2_0_DB8_SHIFT) +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK2_0_DB8_RANGE 7:0 +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK2_0_DB8_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK2_0_DB8_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK2_0_DB8_DEFAULT_MASK _MK_MASK_CONST(0xff) +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK2_0_DB8_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK2_0_DB8_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK3_0 +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK3_0 _MK_ADDR_CONST(0x69) +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK3_0_SECURE 0x0 +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK3_0_WORD_COUNT 0x1 +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK3_0_RESET_VAL _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK3_0_RESET_MASK _MK_MASK_CONST(0xffffffff) +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK3_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK3_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK3_0_READ_MASK _MK_MASK_CONST(0xffffffff) +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK3_0_WRITE_MASK _MK_MASK_CONST(0xffffffff) +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK3_0_DB15_SHIFT _MK_SHIFT_CONST(24) +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK3_0_DB15_FIELD _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK3_0_DB15_SHIFT) +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK3_0_DB15_RANGE 31:24 +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK3_0_DB15_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK3_0_DB15_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK3_0_DB15_DEFAULT_MASK _MK_MASK_CONST(0xff) +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK3_0_DB15_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK3_0_DB15_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK3_0_DB14_SHIFT _MK_SHIFT_CONST(16) +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK3_0_DB14_FIELD _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK3_0_DB14_SHIFT) +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK3_0_DB14_RANGE 23:16 +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK3_0_DB14_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK3_0_DB14_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK3_0_DB14_DEFAULT_MASK _MK_MASK_CONST(0xff) +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK3_0_DB14_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK3_0_DB14_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK3_0_DB13_SHIFT _MK_SHIFT_CONST(8) +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK3_0_DB13_FIELD _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK3_0_DB13_SHIFT) +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK3_0_DB13_RANGE 15:8 +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK3_0_DB13_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK3_0_DB13_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK3_0_DB13_DEFAULT_MASK _MK_MASK_CONST(0xff) +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK3_0_DB13_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK3_0_DB13_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK3_0_DB12_SHIFT _MK_SHIFT_CONST(0) +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK3_0_DB12_FIELD _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK3_0_DB12_SHIFT) +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK3_0_DB12_RANGE 7:0 +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK3_0_DB12_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK3_0_DB12_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK3_0_DB12_DEFAULT_MASK _MK_MASK_CONST(0xff) +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK3_0_DB12_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK3_0_DB12_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK4_0 +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK4_0 _MK_ADDR_CONST(0x6a) +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK4_0_SECURE 0x0 +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK4_0_WORD_COUNT 0x1 +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK4_0_RESET_VAL _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK4_0_RESET_MASK _MK_MASK_CONST(0xffffffff) +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK4_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK4_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK4_0_READ_MASK _MK_MASK_CONST(0xffffffff) +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK4_0_WRITE_MASK _MK_MASK_CONST(0xffffffff) +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK4_0_DB19_SHIFT _MK_SHIFT_CONST(24) +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK4_0_DB19_FIELD _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK4_0_DB19_SHIFT) +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK4_0_DB19_RANGE 31:24 +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK4_0_DB19_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK4_0_DB19_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK4_0_DB19_DEFAULT_MASK _MK_MASK_CONST(0xff) +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK4_0_DB19_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK4_0_DB19_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK4_0_DB18_SHIFT _MK_SHIFT_CONST(16) +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK4_0_DB18_FIELD _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK4_0_DB18_SHIFT) +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK4_0_DB18_RANGE 23:16 +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK4_0_DB18_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK4_0_DB18_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK4_0_DB18_DEFAULT_MASK _MK_MASK_CONST(0xff) +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK4_0_DB18_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK4_0_DB18_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK4_0_DB17_SHIFT _MK_SHIFT_CONST(8) +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK4_0_DB17_FIELD _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK4_0_DB17_SHIFT) +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK4_0_DB17_RANGE 15:8 +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK4_0_DB17_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK4_0_DB17_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK4_0_DB17_DEFAULT_MASK _MK_MASK_CONST(0xff) +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK4_0_DB17_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK4_0_DB17_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK4_0_DB16_SHIFT _MK_SHIFT_CONST(0) +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK4_0_DB16_FIELD _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK4_0_DB16_SHIFT) +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK4_0_DB16_RANGE 7:0 +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK4_0_DB16_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK4_0_DB16_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK4_0_DB16_DEFAULT_MASK _MK_MASK_CONST(0xff) +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK4_0_DB16_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK4_0_DB16_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK5_0 +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK5_0 _MK_ADDR_CONST(0x6b) +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK5_0_SECURE 0x0 +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK5_0_WORD_COUNT 0x1 +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK5_0_RESET_VAL _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK5_0_RESET_MASK _MK_MASK_CONST(0xffffffff) +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK5_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK5_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK5_0_READ_MASK _MK_MASK_CONST(0xffffffff) +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK5_0_WRITE_MASK _MK_MASK_CONST(0xffffffff) +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK5_0_DB23_SHIFT _MK_SHIFT_CONST(24) +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK5_0_DB23_FIELD _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK5_0_DB23_SHIFT) +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK5_0_DB23_RANGE 31:24 +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK5_0_DB23_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK5_0_DB23_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK5_0_DB23_DEFAULT_MASK _MK_MASK_CONST(0xff) +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK5_0_DB23_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK5_0_DB23_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK5_0_DB22_SHIFT _MK_SHIFT_CONST(16) +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK5_0_DB22_FIELD _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK5_0_DB22_SHIFT) +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK5_0_DB22_RANGE 23:16 +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK5_0_DB22_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK5_0_DB22_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK5_0_DB22_DEFAULT_MASK _MK_MASK_CONST(0xff) +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK5_0_DB22_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK5_0_DB22_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK5_0_DB21_SHIFT _MK_SHIFT_CONST(8) +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK5_0_DB21_FIELD _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK5_0_DB21_SHIFT) +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK5_0_DB21_RANGE 15:8 +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK5_0_DB21_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK5_0_DB21_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK5_0_DB21_DEFAULT_MASK _MK_MASK_CONST(0xff) +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK5_0_DB21_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK5_0_DB21_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK5_0_DB20_SHIFT _MK_SHIFT_CONST(0) +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK5_0_DB20_FIELD _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK5_0_DB20_SHIFT) +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK5_0_DB20_RANGE 7:0 +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK5_0_DB20_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK5_0_DB20_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK5_0_DB20_DEFAULT_MASK _MK_MASK_CONST(0xff) +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK5_0_DB20_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK5_0_DB20_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK6_0 +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK6_0 _MK_ADDR_CONST(0x6c) +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK6_0_SECURE 0x0 +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK6_0_WORD_COUNT 0x1 +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK6_0_RESET_VAL _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK6_0_RESET_MASK _MK_MASK_CONST(0xffffffff) +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK6_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK6_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK6_0_READ_MASK _MK_MASK_CONST(0xffffffff) +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK6_0_WRITE_MASK _MK_MASK_CONST(0xffffffff) +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK6_0_DB27_SHIFT _MK_SHIFT_CONST(24) +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK6_0_DB27_FIELD _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK6_0_DB27_SHIFT) +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK6_0_DB27_RANGE 31:24 +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK6_0_DB27_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK6_0_DB27_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK6_0_DB27_DEFAULT_MASK _MK_MASK_CONST(0xff) +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK6_0_DB27_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK6_0_DB27_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK6_0_DB26_SHIFT _MK_SHIFT_CONST(16) +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK6_0_DB26_FIELD _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK6_0_DB26_SHIFT) +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK6_0_DB26_RANGE 23:16 +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK6_0_DB26_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK6_0_DB26_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK6_0_DB26_DEFAULT_MASK _MK_MASK_CONST(0xff) +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK6_0_DB26_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK6_0_DB26_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK6_0_DB25_SHIFT _MK_SHIFT_CONST(8) +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK6_0_DB25_FIELD _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK6_0_DB25_SHIFT) +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK6_0_DB25_RANGE 15:8 +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK6_0_DB25_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK6_0_DB25_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK6_0_DB25_DEFAULT_MASK _MK_MASK_CONST(0xff) +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK6_0_DB25_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK6_0_DB25_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK6_0_DB24_SHIFT _MK_SHIFT_CONST(0) +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK6_0_DB24_FIELD _MK_FIELD_CONST(0xff, SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK6_0_DB24_SHIFT) +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK6_0_DB24_RANGE 7:0 +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK6_0_DB24_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK6_0_DB24_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK6_0_DB24_DEFAULT_MASK _MK_MASK_CONST(0xff) +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK6_0_DB24_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK6_0_DB24_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register SOR_NV_PDISP_SOR_DP_TPG_0 +#define SOR_NV_PDISP_SOR_DP_TPG_0 _MK_ADDR_CONST(0x6d) +#define SOR_NV_PDISP_SOR_DP_TPG_0_SECURE 0x0 +#define SOR_NV_PDISP_SOR_DP_TPG_0_WORD_COUNT 0x1 +#define SOR_NV_PDISP_SOR_DP_TPG_0_RESET_VAL _MK_MASK_CONST(0x50505050) +#define SOR_NV_PDISP_SOR_DP_TPG_0_RESET_MASK _MK_MASK_CONST(0x7f7f7f7f) +#define SOR_NV_PDISP_SOR_DP_TPG_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_TPG_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_TPG_0_READ_MASK _MK_MASK_CONST(0x7f7f7f7f) +#define SOR_NV_PDISP_SOR_DP_TPG_0_WRITE_MASK _MK_MASK_CONST(0x7f7f7f7f) +#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE3_CHANNELCODING_SHIFT _MK_SHIFT_CONST(30) +#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE3_CHANNELCODING_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_DP_TPG_0_LANE3_CHANNELCODING_SHIFT) +#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE3_CHANNELCODING_RANGE 30:30 +#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE3_CHANNELCODING_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE3_CHANNELCODING_DEFAULT _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE3_CHANNELCODING_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE3_CHANNELCODING_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE3_CHANNELCODING_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE3_CHANNELCODING_INIT_ENUM ENABLE +#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE3_CHANNELCODING_DISABLE _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE3_CHANNELCODING_ENABLE _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE3_SCRAMBLEREN_SHIFT _MK_SHIFT_CONST(28) +#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE3_SCRAMBLEREN_FIELD _MK_FIELD_CONST(0x3, SOR_NV_PDISP_SOR_DP_TPG_0_LANE3_SCRAMBLEREN_SHIFT) +#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE3_SCRAMBLEREN_RANGE 29:28 +#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE3_SCRAMBLEREN_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE3_SCRAMBLEREN_DEFAULT _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE3_SCRAMBLEREN_DEFAULT_MASK _MK_MASK_CONST(0x3) +#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE3_SCRAMBLEREN_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE3_SCRAMBLEREN_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE3_SCRAMBLEREN_INIT_ENUM ENABLE_GALIOS +#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE3_SCRAMBLEREN_DISABLE _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE3_SCRAMBLEREN_ENABLE_GALIOS _MK_ENUM_CONST(1) +#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE3_SCRAMBLEREN_ENABLE_FIBONACCI _MK_ENUM_CONST(2) + +#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE3_PATTERN_SHIFT _MK_SHIFT_CONST(24) +#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE3_PATTERN_FIELD _MK_FIELD_CONST(0xf, SOR_NV_PDISP_SOR_DP_TPG_0_LANE3_PATTERN_SHIFT) +#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE3_PATTERN_RANGE 27:24 +#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE3_PATTERN_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE3_PATTERN_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE3_PATTERN_DEFAULT_MASK _MK_MASK_CONST(0xf) +#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE3_PATTERN_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE3_PATTERN_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE3_PATTERN_INIT_ENUM NOPATTERN +#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE3_PATTERN_NOPATTERN _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE3_PATTERN_TRAINING1 _MK_ENUM_CONST(1) +#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE3_PATTERN_TRAINING2 _MK_ENUM_CONST(2) +#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE3_PATTERN_TRAINING3 _MK_ENUM_CONST(3) +#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE3_PATTERN_D102 _MK_ENUM_CONST(4) +#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE3_PATTERN_SBLERRRATE _MK_ENUM_CONST(5) +#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE3_PATTERN_PRBS7 _MK_ENUM_CONST(6) +#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE3_PATTERN_CSTM _MK_ENUM_CONST(7) +#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE3_PATTERN_HBR2_COMPLIANCE _MK_ENUM_CONST(8) + +#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE2_CHANNELCODING_SHIFT _MK_SHIFT_CONST(22) +#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE2_CHANNELCODING_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_DP_TPG_0_LANE2_CHANNELCODING_SHIFT) +#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE2_CHANNELCODING_RANGE 22:22 +#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE2_CHANNELCODING_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE2_CHANNELCODING_DEFAULT _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE2_CHANNELCODING_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE2_CHANNELCODING_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE2_CHANNELCODING_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE2_CHANNELCODING_INIT_ENUM ENABLE +#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE2_CHANNELCODING_DISABLE _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE2_CHANNELCODING_ENABLE _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE2_SCRAMBLEREN_SHIFT _MK_SHIFT_CONST(20) +#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE2_SCRAMBLEREN_FIELD _MK_FIELD_CONST(0x3, SOR_NV_PDISP_SOR_DP_TPG_0_LANE2_SCRAMBLEREN_SHIFT) +#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE2_SCRAMBLEREN_RANGE 21:20 +#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE2_SCRAMBLEREN_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE2_SCRAMBLEREN_DEFAULT _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE2_SCRAMBLEREN_DEFAULT_MASK _MK_MASK_CONST(0x3) +#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE2_SCRAMBLEREN_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE2_SCRAMBLEREN_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE2_SCRAMBLEREN_INIT_ENUM ENABLE_GALIOS +#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE2_SCRAMBLEREN_DISABLE _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE2_SCRAMBLEREN_ENABLE_GALIOS _MK_ENUM_CONST(1) +#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE2_SCRAMBLEREN_ENABLE_FIBONACCI _MK_ENUM_CONST(2) + +#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE2_PATTERN_SHIFT _MK_SHIFT_CONST(16) +#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE2_PATTERN_FIELD _MK_FIELD_CONST(0xf, SOR_NV_PDISP_SOR_DP_TPG_0_LANE2_PATTERN_SHIFT) +#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE2_PATTERN_RANGE 19:16 +#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE2_PATTERN_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE2_PATTERN_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE2_PATTERN_DEFAULT_MASK _MK_MASK_CONST(0xf) +#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE2_PATTERN_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE2_PATTERN_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE2_PATTERN_INIT_ENUM NOPATTERN +#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE2_PATTERN_NOPATTERN _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE2_PATTERN_TRAINING1 _MK_ENUM_CONST(1) +#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE2_PATTERN_TRAINING2 _MK_ENUM_CONST(2) +#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE2_PATTERN_TRAINING3 _MK_ENUM_CONST(3) +#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE2_PATTERN_D102 _MK_ENUM_CONST(4) +#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE2_PATTERN_SBLERRRATE _MK_ENUM_CONST(5) +#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE2_PATTERN_PRBS7 _MK_ENUM_CONST(6) +#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE2_PATTERN_CSTM _MK_ENUM_CONST(7) +#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE2_PATTERN_HBR2_COMPLIANCE _MK_ENUM_CONST(8) + +#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE1_CHANNELCODING_SHIFT _MK_SHIFT_CONST(14) +#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE1_CHANNELCODING_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_DP_TPG_0_LANE1_CHANNELCODING_SHIFT) +#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE1_CHANNELCODING_RANGE 14:14 +#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE1_CHANNELCODING_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE1_CHANNELCODING_DEFAULT _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE1_CHANNELCODING_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE1_CHANNELCODING_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE1_CHANNELCODING_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE1_CHANNELCODING_INIT_ENUM ENABLE +#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE1_CHANNELCODING_DISABLE _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE1_CHANNELCODING_ENABLE _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE1_SCRAMBLEREN_SHIFT _MK_SHIFT_CONST(12) +#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE1_SCRAMBLEREN_FIELD _MK_FIELD_CONST(0x3, SOR_NV_PDISP_SOR_DP_TPG_0_LANE1_SCRAMBLEREN_SHIFT) +#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE1_SCRAMBLEREN_RANGE 13:12 +#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE1_SCRAMBLEREN_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE1_SCRAMBLEREN_DEFAULT _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE1_SCRAMBLEREN_DEFAULT_MASK _MK_MASK_CONST(0x3) +#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE1_SCRAMBLEREN_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE1_SCRAMBLEREN_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE1_SCRAMBLEREN_INIT_ENUM ENABLE_GALIOS +#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE1_SCRAMBLEREN_DISABLE _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE1_SCRAMBLEREN_ENABLE_GALIOS _MK_ENUM_CONST(1) +#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE1_SCRAMBLEREN_ENABLE_FIBONACCI _MK_ENUM_CONST(2) + +#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE1_PATTERN_SHIFT _MK_SHIFT_CONST(8) +#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE1_PATTERN_FIELD _MK_FIELD_CONST(0xf, SOR_NV_PDISP_SOR_DP_TPG_0_LANE1_PATTERN_SHIFT) +#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE1_PATTERN_RANGE 11:8 +#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE1_PATTERN_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE1_PATTERN_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE1_PATTERN_DEFAULT_MASK _MK_MASK_CONST(0xf) +#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE1_PATTERN_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE1_PATTERN_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE1_PATTERN_INIT_ENUM NOPATTERN +#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE1_PATTERN_NOPATTERN _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE1_PATTERN_TRAINING1 _MK_ENUM_CONST(1) +#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE1_PATTERN_TRAINING2 _MK_ENUM_CONST(2) +#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE1_PATTERN_TRAINING3 _MK_ENUM_CONST(3) +#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE1_PATTERN_D102 _MK_ENUM_CONST(4) +#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE1_PATTERN_SBLERRRATE _MK_ENUM_CONST(5) +#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE1_PATTERN_PRBS7 _MK_ENUM_CONST(6) +#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE1_PATTERN_CSTM _MK_ENUM_CONST(7) +#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE1_PATTERN_HBR2_COMPLIANCE _MK_ENUM_CONST(8) + +#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE0_CHANNELCODING_SHIFT _MK_SHIFT_CONST(6) +#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE0_CHANNELCODING_FIELD _MK_FIELD_CONST(0x1, SOR_NV_PDISP_SOR_DP_TPG_0_LANE0_CHANNELCODING_SHIFT) +#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE0_CHANNELCODING_RANGE 6:6 +#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE0_CHANNELCODING_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE0_CHANNELCODING_DEFAULT _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE0_CHANNELCODING_DEFAULT_MASK _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE0_CHANNELCODING_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE0_CHANNELCODING_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE0_CHANNELCODING_INIT_ENUM ENABLE +#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE0_CHANNELCODING_DISABLE _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE0_CHANNELCODING_ENABLE _MK_ENUM_CONST(1) + +#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE0_SCRAMBLEREN_SHIFT _MK_SHIFT_CONST(4) +#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE0_SCRAMBLEREN_FIELD _MK_FIELD_CONST(0x3, SOR_NV_PDISP_SOR_DP_TPG_0_LANE0_SCRAMBLEREN_SHIFT) +#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE0_SCRAMBLEREN_RANGE 5:4 +#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE0_SCRAMBLEREN_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE0_SCRAMBLEREN_DEFAULT _MK_MASK_CONST(0x1) +#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE0_SCRAMBLEREN_DEFAULT_MASK _MK_MASK_CONST(0x3) +#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE0_SCRAMBLEREN_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE0_SCRAMBLEREN_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE0_SCRAMBLEREN_INIT_ENUM ENABLE_GALIOS +#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE0_SCRAMBLEREN_DISABLE _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE0_SCRAMBLEREN_ENABLE_GALIOS _MK_ENUM_CONST(1) +#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE0_SCRAMBLEREN_ENABLE_FIBONACCI _MK_ENUM_CONST(2) + +#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE0_PATTERN_SHIFT _MK_SHIFT_CONST(0) +#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE0_PATTERN_FIELD _MK_FIELD_CONST(0xf, SOR_NV_PDISP_SOR_DP_TPG_0_LANE0_PATTERN_SHIFT) +#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE0_PATTERN_RANGE 3:0 +#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE0_PATTERN_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE0_PATTERN_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE0_PATTERN_DEFAULT_MASK _MK_MASK_CONST(0xf) +#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE0_PATTERN_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE0_PATTERN_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE0_PATTERN_INIT_ENUM NOPATTERN +#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE0_PATTERN_NOPATTERN _MK_ENUM_CONST(0) +#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE0_PATTERN_TRAINING1 _MK_ENUM_CONST(1) +#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE0_PATTERN_TRAINING2 _MK_ENUM_CONST(2) +#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE0_PATTERN_TRAINING3 _MK_ENUM_CONST(3) +#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE0_PATTERN_D102 _MK_ENUM_CONST(4) +#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE0_PATTERN_SBLERRRATE _MK_ENUM_CONST(5) +#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE0_PATTERN_PRBS7 _MK_ENUM_CONST(6) +#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE0_PATTERN_CSTM _MK_ENUM_CONST(7) +#define SOR_NV_PDISP_SOR_DP_TPG_0_LANE0_PATTERN_HBR2_COMPLIANCE _MK_ENUM_CONST(8) + + +// Register SOR_NV_PDISP_SOR_DP_TPG_CONFIG_0 +#define SOR_NV_PDISP_SOR_DP_TPG_CONFIG_0 _MK_ADDR_CONST(0x6e) +#define SOR_NV_PDISP_SOR_DP_TPG_CONFIG_0_SECURE 0x0 +#define SOR_NV_PDISP_SOR_DP_TPG_CONFIG_0_WORD_COUNT 0x1 +#define SOR_NV_PDISP_SOR_DP_TPG_CONFIG_0_RESET_VAL _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_TPG_CONFIG_0_RESET_MASK _MK_MASK_CONST(0x1ffff) +#define SOR_NV_PDISP_SOR_DP_TPG_CONFIG_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_TPG_CONFIG_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_TPG_CONFIG_0_READ_MASK _MK_MASK_CONST(0x1ffff) +#define SOR_NV_PDISP_SOR_DP_TPG_CONFIG_0_WRITE_MASK _MK_MASK_CONST(0x1ffff) +#define SOR_NV_PDISP_SOR_DP_TPG_CONFIG_0_HBR2_COMPLIANCE_PERIOD_SHIFT _MK_SHIFT_CONST(0) +#define SOR_NV_PDISP_SOR_DP_TPG_CONFIG_0_HBR2_COMPLIANCE_PERIOD_FIELD _MK_FIELD_CONST(0x1ffff, SOR_NV_PDISP_SOR_DP_TPG_CONFIG_0_HBR2_COMPLIANCE_PERIOD_SHIFT) +#define SOR_NV_PDISP_SOR_DP_TPG_CONFIG_0_HBR2_COMPLIANCE_PERIOD_RANGE 16:0 +#define SOR_NV_PDISP_SOR_DP_TPG_CONFIG_0_HBR2_COMPLIANCE_PERIOD_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_DP_TPG_CONFIG_0_HBR2_COMPLIANCE_PERIOD_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_TPG_CONFIG_0_HBR2_COMPLIANCE_PERIOD_DEFAULT_MASK _MK_MASK_CONST(0x1ffff) +#define SOR_NV_PDISP_SOR_DP_TPG_CONFIG_0_HBR2_COMPLIANCE_PERIOD_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_TPG_CONFIG_0_HBR2_COMPLIANCE_PERIOD_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register SOR_NV_PDISP_SOR_DP_LQ_CSTM0_0 +#define SOR_NV_PDISP_SOR_DP_LQ_CSTM0_0 _MK_ADDR_CONST(0x6f) +#define SOR_NV_PDISP_SOR_DP_LQ_CSTM0_0_SECURE 0x0 +#define SOR_NV_PDISP_SOR_DP_LQ_CSTM0_0_WORD_COUNT 0x1 +#define SOR_NV_PDISP_SOR_DP_LQ_CSTM0_0_RESET_VAL _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_LQ_CSTM0_0_RESET_MASK _MK_MASK_CONST(0xffffffff) +#define SOR_NV_PDISP_SOR_DP_LQ_CSTM0_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_LQ_CSTM0_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_LQ_CSTM0_0_READ_MASK _MK_MASK_CONST(0xffffffff) +#define SOR_NV_PDISP_SOR_DP_LQ_CSTM0_0_WRITE_MASK _MK_MASK_CONST(0xffffffff) +#define SOR_NV_PDISP_SOR_DP_LQ_CSTM0_0_SYM_SHIFT _MK_SHIFT_CONST(0) +#define SOR_NV_PDISP_SOR_DP_LQ_CSTM0_0_SYM_FIELD _MK_FIELD_CONST(0xffffffff, SOR_NV_PDISP_SOR_DP_LQ_CSTM0_0_SYM_SHIFT) +#define SOR_NV_PDISP_SOR_DP_LQ_CSTM0_0_SYM_RANGE 31:0 +#define SOR_NV_PDISP_SOR_DP_LQ_CSTM0_0_SYM_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_DP_LQ_CSTM0_0_SYM_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_LQ_CSTM0_0_SYM_DEFAULT_MASK _MK_MASK_CONST(0xffffffff) +#define SOR_NV_PDISP_SOR_DP_LQ_CSTM0_0_SYM_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_LQ_CSTM0_0_SYM_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register SOR_NV_PDISP_SOR_DP_LQ_CSTM1_0 +#define SOR_NV_PDISP_SOR_DP_LQ_CSTM1_0 _MK_ADDR_CONST(0x70) +#define SOR_NV_PDISP_SOR_DP_LQ_CSTM1_0_SECURE 0x0 +#define SOR_NV_PDISP_SOR_DP_LQ_CSTM1_0_WORD_COUNT 0x1 +#define SOR_NV_PDISP_SOR_DP_LQ_CSTM1_0_RESET_VAL _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_LQ_CSTM1_0_RESET_MASK _MK_MASK_CONST(0xffffffff) +#define SOR_NV_PDISP_SOR_DP_LQ_CSTM1_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_LQ_CSTM1_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_LQ_CSTM1_0_READ_MASK _MK_MASK_CONST(0xffffffff) +#define SOR_NV_PDISP_SOR_DP_LQ_CSTM1_0_WRITE_MASK _MK_MASK_CONST(0xffffffff) +#define SOR_NV_PDISP_SOR_DP_LQ_CSTM1_0_SYM_SHIFT _MK_SHIFT_CONST(0) +#define SOR_NV_PDISP_SOR_DP_LQ_CSTM1_0_SYM_FIELD _MK_FIELD_CONST(0xffffffff, SOR_NV_PDISP_SOR_DP_LQ_CSTM1_0_SYM_SHIFT) +#define SOR_NV_PDISP_SOR_DP_LQ_CSTM1_0_SYM_RANGE 31:0 +#define SOR_NV_PDISP_SOR_DP_LQ_CSTM1_0_SYM_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_DP_LQ_CSTM1_0_SYM_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_LQ_CSTM1_0_SYM_DEFAULT_MASK _MK_MASK_CONST(0xffffffff) +#define SOR_NV_PDISP_SOR_DP_LQ_CSTM1_0_SYM_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_LQ_CSTM1_0_SYM_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// Register SOR_NV_PDISP_SOR_DP_LQ_CSTM2_0 +#define SOR_NV_PDISP_SOR_DP_LQ_CSTM2_0 _MK_ADDR_CONST(0x71) +#define SOR_NV_PDISP_SOR_DP_LQ_CSTM2_0_SECURE 0x0 +#define SOR_NV_PDISP_SOR_DP_LQ_CSTM2_0_WORD_COUNT 0x1 +#define SOR_NV_PDISP_SOR_DP_LQ_CSTM2_0_RESET_VAL _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_LQ_CSTM2_0_RESET_MASK _MK_MASK_CONST(0xffffffff) +#define SOR_NV_PDISP_SOR_DP_LQ_CSTM2_0_SW_DEFAULT_VAL _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_LQ_CSTM2_0_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_LQ_CSTM2_0_READ_MASK _MK_MASK_CONST(0xffffffff) +#define SOR_NV_PDISP_SOR_DP_LQ_CSTM2_0_WRITE_MASK _MK_MASK_CONST(0xffffffff) +#define SOR_NV_PDISP_SOR_DP_LQ_CSTM2_0_SYM_SHIFT _MK_SHIFT_CONST(0) +#define SOR_NV_PDISP_SOR_DP_LQ_CSTM2_0_SYM_FIELD _MK_FIELD_CONST(0xffffffff, SOR_NV_PDISP_SOR_DP_LQ_CSTM2_0_SYM_SHIFT) +#define SOR_NV_PDISP_SOR_DP_LQ_CSTM2_0_SYM_RANGE 31:0 +#define SOR_NV_PDISP_SOR_DP_LQ_CSTM2_0_SYM_WOFFSET 0x0 +#define SOR_NV_PDISP_SOR_DP_LQ_CSTM2_0_SYM_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_LQ_CSTM2_0_SYM_DEFAULT_MASK _MK_MASK_CONST(0xffffffff) +#define SOR_NV_PDISP_SOR_DP_LQ_CSTM2_0_SYM_SW_DEFAULT _MK_MASK_CONST(0x0) +#define SOR_NV_PDISP_SOR_DP_LQ_CSTM2_0_SYM_SW_DEFAULT_MASK _MK_MASK_CONST(0x0) + + +// +// REGISTER LIST +// +#define LIST_ARSOR_REGS(_op_) \ +_op_(SOR_CTXSW_0) \ +_op_(SOR_NV_PDISP_SOR_SUPER_STATE0_0) \ +_op_(SOR_NV_PDISP_SOR_SUPER_STATE1_0) \ +_op_(SOR_NV_PDISP_SOR_STATE0_0) \ +_op_(SOR_NV_PDISP_SOR_STATE1_0) \ +_op_(SOR_NV_PDISP_HEAD_STATE0_0) \ +_op_(SOR_NV_PDISP_HEAD_STATE0) \ +_op_(SOR_NV_PDISP_HEAD_STATE0_1) \ +_op_(SOR_NV_PDISP_HEAD_STATE1_0) \ +_op_(SOR_NV_PDISP_HEAD_STATE1) \ +_op_(SOR_NV_PDISP_HEAD_STATE1_1) \ +_op_(SOR_NV_PDISP_HEAD_STATE2_0) \ +_op_(SOR_NV_PDISP_HEAD_STATE2) \ +_op_(SOR_NV_PDISP_HEAD_STATE2_1) \ +_op_(SOR_NV_PDISP_HEAD_STATE3_0) \ +_op_(SOR_NV_PDISP_HEAD_STATE3) \ +_op_(SOR_NV_PDISP_HEAD_STATE3_1) \ +_op_(SOR_NV_PDISP_HEAD_STATE4_0) \ +_op_(SOR_NV_PDISP_HEAD_STATE4) \ +_op_(SOR_NV_PDISP_HEAD_STATE4_1) \ +_op_(SOR_NV_PDISP_HEAD_STATE5_0) \ +_op_(SOR_NV_PDISP_HEAD_STATE5) \ +_op_(SOR_NV_PDISP_HEAD_STATE5_1) \ +_op_(SOR_NV_PDISP_SOR_CRC_CNTRL_0) \ +_op_(SOR_NV_PDISP_SOR_DP_DEBUG_MVID_0) \ +_op_(SOR_NV_PDISP_SOR_CLK_CNTRL_0) \ +_op_(SOR_NV_PDISP_SOR_CAP_0) \ +_op_(SOR_NV_PDISP_SOR_PWR_0) \ +_op_(SOR_NV_PDISP_SOR_TEST_0) \ +_op_(SOR_NV_PDISP_SOR_PLL0_0) \ +_op_(SOR_NV_PDISP_SOR_PLL1_0) \ +_op_(SOR_NV_PDISP_SOR_PLL2_0) \ +_op_(SOR_NV_PDISP_SOR_PLL3_0) \ +_op_(SOR_NV_PDISP_SOR_CSTM_0) \ +_op_(SOR_NV_PDISP_SOR_LVDS_0) \ +_op_(SOR_NV_PDISP_SOR_CRCA_0) \ +_op_(SOR_NV_PDISP_SOR_CRCB_0) \ +_op_(SOR_NV_PDISP_SOR_BLANK_0) \ +_op_(SOR_NV_PDISP_SOR_SEQ_CTL_0) \ +_op_(SOR_NV_PDISP_SOR_LANE_SEQ_CTL_0) \ +_op_(SOR_NV_PDISP_SOR_SEQ_INST0_0) \ +_op_(SOR_NV_PDISP_SOR_SEQ_INST1_0) \ +_op_(SOR_NV_PDISP_SOR_SEQ_INST2_0) \ +_op_(SOR_NV_PDISP_SOR_SEQ_INST3_0) \ +_op_(SOR_NV_PDISP_SOR_SEQ_INST4_0) \ +_op_(SOR_NV_PDISP_SOR_SEQ_INST5_0) \ +_op_(SOR_NV_PDISP_SOR_SEQ_INST6_0) \ +_op_(SOR_NV_PDISP_SOR_SEQ_INST7_0) \ +_op_(SOR_NV_PDISP_SOR_SEQ_INST8_0) \ +_op_(SOR_NV_PDISP_SOR_SEQ_INST9_0) \ +_op_(SOR_NV_PDISP_SOR_SEQ_INSTA_0) \ +_op_(SOR_NV_PDISP_SOR_SEQ_INSTB_0) \ +_op_(SOR_NV_PDISP_SOR_SEQ_INSTC_0) \ +_op_(SOR_NV_PDISP_SOR_SEQ_INSTD_0) \ +_op_(SOR_NV_PDISP_SOR_SEQ_INSTE_0) \ +_op_(SOR_NV_PDISP_SOR_SEQ_INSTF_0) \ +_op_(SOR_NV_PDISP_SOR_PWM_DIV_0) \ +_op_(SOR_NV_PDISP_SOR_PWM_CTL_0) \ +_op_(SOR_NV_PDISP_SOR_VCRCA0_0) \ +_op_(SOR_NV_PDISP_SOR_VCRCA1_0) \ +_op_(SOR_NV_PDISP_SOR_VCRCB0_0) \ +_op_(SOR_NV_PDISP_SOR_VCRCB1_0) \ +_op_(SOR_NV_PDISP_SOR_CCRCA0_0) \ +_op_(SOR_NV_PDISP_SOR_CCRCA1_0) \ +_op_(SOR_NV_PDISP_SOR_CCRCB0_0) \ +_op_(SOR_NV_PDISP_SOR_CCRCB1_0) \ +_op_(SOR_NV_PDISP_SOR_EDATAA0_0) \ +_op_(SOR_NV_PDISP_SOR_EDATAA1_0) \ +_op_(SOR_NV_PDISP_SOR_EDATAB0_0) \ +_op_(SOR_NV_PDISP_SOR_EDATAB1_0) \ +_op_(SOR_NV_PDISP_SOR_COUNTA0_0) \ +_op_(SOR_NV_PDISP_SOR_COUNTA1_0) \ +_op_(SOR_NV_PDISP_SOR_COUNTB0_0) \ +_op_(SOR_NV_PDISP_SOR_COUNTB1_0) \ +_op_(SOR_NV_PDISP_SOR_DEBUGA0_0) \ +_op_(SOR_NV_PDISP_SOR_DEBUGA1_0) \ +_op_(SOR_NV_PDISP_SOR_DEBUGB0_0) \ +_op_(SOR_NV_PDISP_SOR_DEBUGB1_0) \ +_op_(SOR_NV_PDISP_SOR_TRIG_0) \ +_op_(SOR_NV_PDISP_SOR_MSCHECK_0) \ +_op_(SOR_NV_PDISP_SOR_XBAR_CTRL_0) \ +_op_(SOR_NV_PDISP_SOR_XBAR_POL_0) \ +_op_(SOR_NV_PDISP_SOR_DP_LINKCTL0_0) \ +_op_(SOR_NV_PDISP_SOR_DP_LINKCTL1_0) \ +_op_(SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT0_0) \ +_op_(SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT1_0) \ +_op_(SOR_NV_PDISP_SOR_LANE4_DRIVE_CURRENT0_0) \ +_op_(SOR_NV_PDISP_SOR_LANE4_DRIVE_CURRENT1_0) \ +_op_(SOR_NV_PDISP_SOR_LANE_PREEMPHASIS0_0) \ +_op_(SOR_NV_PDISP_SOR_LANE_PREEMPHASIS1_0) \ +_op_(SOR_NV_PDISP_SOR_LANE4_PREEMPHASIS0_0) \ +_op_(SOR_NV_PDISP_SOR_LANE4_PREEMPHASIS1_0) \ +_op_(SOR_NV_PDISP_SOR_POSTCURSOR0_0) \ +_op_(SOR_NV_PDISP_SOR_POSTCURSOR1_0) \ +_op_(SOR_NV_PDISP_SOR_DP_CONFIG0_0) \ +_op_(SOR_NV_PDISP_SOR_DP_CONFIG1_0) \ +_op_(SOR_NV_PDISP_SOR_DP_MN0_0) \ +_op_(SOR_NV_PDISP_SOR_DP_MN1_0) \ +_op_(SOR_NV_PDISP_SOR_DP_PADCTL0_0) \ +_op_(SOR_NV_PDISP_SOR_DP_PADCTL1_0) \ +_op_(SOR_NV_PDISP_SOR_DP_DEBUG0_0) \ +_op_(SOR_NV_PDISP_SOR_DP_DEBUG1_0) \ +_op_(SOR_NV_PDISP_SOR_DP_SPARE0_0) \ +_op_(SOR_NV_PDISP_SOR_DP_SPARE1_0) \ +_op_(SOR_NV_PDISP_SOR_DP_AUDIO_CTRL_0) \ +_op_(SOR_NV_PDISP_SOR_DP_AUDIO_HBLANK_SYMBOLS_0) \ +_op_(SOR_NV_PDISP_SOR_DP_AUDIO_VBLANK_SYMBOLS_0) \ +_op_(SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_HEADER_0) \ +_op_(SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK0_0) \ +_op_(SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK1_0) \ +_op_(SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK2_0) \ +_op_(SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK3_0) \ +_op_(SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK4_0) \ +_op_(SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK5_0) \ +_op_(SOR_NV_PDISP_SOR_DP_GENERIC_INFOFRAME_SUBPACK6_0) \ +_op_(SOR_NV_PDISP_SOR_DP_TPG_0) \ +_op_(SOR_NV_PDISP_SOR_DP_TPG_CONFIG_0) \ +_op_(SOR_NV_PDISP_SOR_DP_LQ_CSTM0_0) \ +_op_(SOR_NV_PDISP_SOR_DP_LQ_CSTM1_0) \ +_op_(SOR_NV_PDISP_SOR_DP_LQ_CSTM2_0) + + +// +// ADDRESS SPACES +// + +#define BASE_ADDRESS_SOR 0x00000000 + +// +// ARSOR REGISTER BANKS +// + +#define SOR0_FIRST_REG 0x0000 // SOR_CTXSW_0 +#define SOR0_LAST_REG 0x0071 // SOR_NV_PDISP_SOR_DP_LQ_CSTM2_0 + +// To satisfy various compilers and platforms, +// we let users control the types and syntax of certain constants, using macros. +#ifndef _MK_SHIFT_CONST + #define _MK_SHIFT_CONST(_constant_) _constant_ +#endif +#ifndef _MK_MASK_CONST + #define _MK_MASK_CONST(_constant_) _constant_ +#endif +#ifndef _MK_ENUM_CONST + #define _MK_ENUM_CONST(_constant_) (_constant_ ## UL) +#endif +#ifndef _MK_ADDR_CONST + #define _MK_ADDR_CONST(_constant_) _constant_ +#endif +#ifndef _MK_FIELD_CONST + #define _MK_FIELD_CONST(_mask_, _shift_) (_MK_MASK_CONST(_mask_) << _MK_SHIFT_CONST(_shift_)) +#endif + +#endif // ifndef ___ARSOR_H_INC_ diff --git a/src/soc/nvidia/tegra124/include/soc/clock.h b/src/soc/nvidia/tegra124/include/soc/clock.h index 056a38b..675fbfb 100644 --- a/src/soc/nvidia/tegra124/include/soc/clock.h +++ b/src/soc/nvidia/tegra124/include/soc/clock.h @@ -149,13 +149,69 @@ enum { #define CLOCK_PLL_STABLE_DELAY_US 300 #define IO_STABILIZATION_DELAY (2) -/* Calculate clock fractional divider value from ref and target frequencies */ +/* Calculate clock fractional divider value from ref and target frequencies. + * This is for a U7.1 format. This is not well written up in the book and + * there have been some questions about this macro, so here we go. + * U7.1 format is defined as (ddddddd+1) + (h*.5) + * The lowest order bit is actually a fractional bit. + * Hence, the divider can be thought of as 9 bits. + * So: + * divider = ((ref/freq) << 1 - 1) (upper 7 bits) | + * (ref/freq & 1) (low order half-bit) + * however we can't do fractional arithmetic ... these are integers! + * So we normalize by shifting the result left 1 bit, and extracting + * ddddddd and h directly to the returned u8. + * divider = 2*(ref/freq); + * We want to + * preserve 7 bits of divisor and one bit of fraction, in 8 bits, as well as + * subtract one from ddddddd. Since we computed ref*2, the dddddd is now nicely + * situated in the upper 7 bits, and the h is sitting there in the low order + * bit. To subtract 1 from ddddddd, just subtract 2 from the 8-bit number + * and voila, upper 7 bits are (ref/freq-1), and lowest bit is h. Since you + * will assign this to a u8, it gets nicely truncated for you. + */ #define CLK_DIVIDER(REF, FREQ) ((((REF) * 2) / FREQ) - 2) -/* Calculate clock frequency value from reference and clock divider value */ +/* Calculate clock frequency value from reference and clock divider value + * The discussion in the book is pretty lacking. + * The idea is that we need to divide a ref clock by a divisor + * in U7.1 format, where 7 upper bits are the integer + * and lowest order bit is a fraction. + * from the book, U7.1 is (ddddddd+1) + (h*.5) + * To normalize to an actual number, we might do this: + * ((d>>7+1)&0x7f) + (d&1 >> 1) + * but as you might guess, the low order bit would be lost. + * Since we can't express the fractional bit, we need to multiply it all by 2. + * ((d + 2)&0xfe) + (d & 1) + * Since we're just adding +2, the lowest order bit is preserved. Hence + * (d+2) is the same as ((d + 2)&0xfe) + (d & 1) + * + * Since you multiply denominator * 2 (by NOT shifting it), + * you multiply numerator * 2 to cancel it out. + */ #define CLK_FREQUENCY(REF, REG) (((REF) * 2) / (REG + 2)) +/* Warning: Some devices just use different bits for the same sources for no + * apparent reason. *Always* double-check the TRM before trusting this macro. */ +#define clock_configure_source(device, src, freq) \ + clrsetbits_le32(&clk_rst->clk_src_##device, \ + CLK_SOURCE_MASK | CLK_DIVISOR_MASK, \ + src << CLK_SOURCE_SHIFT | CLK_DIVIDER(TEGRA_##src##_KHZ, freq)); + +enum clock_source { /* Careful: Not true for all sources, always check TRM! */ + PLLP = 0, + PLLC2 = 1, + PLLC = 2, + PLLD = 2, + PLLC3 = 3, + PLLA = 3, + PLLM = 4, + PLLD2 = 5, + CLK_M = 6, +}; + /* soc-specific */ +#define TEGRA_CLK_M_KHZ clock_get_osc_khz() #define TEGRA_PLLX_KHZ (1900000) #define TEGRA_PLLP_KHZ (408000) #define TEGRA_PLLC_KHZ (600000) @@ -165,7 +221,7 @@ enum { int clock_get_osc_khz(void); void clock_early_uart(void); void clock_cpu0_config_and_reset(void * entry); -void clock_config(void); +void clock_enable_clear_reset(u32 l, u32 h, u32 u, u32 v, u32 w); void clock_init(void); -void clock_ll_set_source_divisor(u32 *reg, u32 source, u32 divisor); +void clock_init_arm_generic_timer(void); #endif /* __SOC_NVIDIA_TEGRA124_CLOCK_H__ */ diff --git a/src/soc/nvidia/tegra124/include/soc/display.h b/src/soc/nvidia/tegra124/include/soc/display.h index 8c7e3e7..868fee4 100644 --- a/src/soc/nvidia/tegra124/include/soc/display.h +++ b/src/soc/nvidia/tegra124/include/soc/display.h @@ -18,5 +18,8 @@ #define __SOC_NVIDIA_TEGRA124_INCLUDE_SOC_DISPLAY_H__ void setup_display(struct soc_nvidia_tegra124_config *config); - +void init_dca_regs(void); +void init_dpaux_regs(void); +void init_sor_regs(void); +void dp_io_powerup(void); #endif /* __SOC_NVIDIA_TEGRA124_INCLUDE_SOC_DISPLAY_H__ */ diff --git a/src/soc/nvidia/tegra124/pmc.h b/src/soc/nvidia/tegra124/pmc.h index 1134abd..c2e4f4d 100644 --- a/src/soc/nvidia/tegra124/pmc.h +++ b/src/soc/nvidia/tegra124/pmc.h @@ -62,7 +62,9 @@ struct tegra_pmc_regs { u32 no_iopower; u32 pwr_det; u32 pwr_det_latch; - u32 scratch[24]; + u32 scratch[20]; + u32 odmdata; + u32 scratch21[24 - 21]; u32 secure_scratch[6]; u32 cpupwrgood_timer; u32 cpupwroff_timer; diff --git a/src/soc/nvidia/tegra124/sor.c b/src/soc/nvidia/tegra124/sor.c new file mode 100644 index 0000000..6a47833 --- /dev/null +++ b/src/soc/nvidia/tegra124/sor.c @@ -0,0 +1,169 @@ +/* + * drivers/video/tegra/dc/sor.c + * + * Copyright (c) 2011-2013, NVIDIA Corporation. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include <console/console.h> +#include <arch/io.h> +#include <stdint.h> +#include <lib.h> +#include <stdlib.h> +#include <delay.h> +#include <soc/addressmap.h> +#include <device/device.h> +#include <stdlib.h> +#include <string.h> +#include <cpu/cpu.h> +#include <boot/tables.h> +#include <cbmem.h> +#include <soc/nvidia/tegra/dc.h> +#include "sor.h" +#include <soc/nvidia/tegra/displayport.h> +#include "clk_rst.h" +#include <soc/clock.h> +#include "chip.h" +#include <soc/display.h> + +#define APBDEV_PMC_DPD_SAMPLE (0x20) +#define APBDEV_PMC_DPD_SAMPLE_ON_DISABLE (0) +#define APBDEV_PMC_DPD_SAMPLE_ON_ENABLE (1) +#define APBDEV_PMC_SEL_DPD_TIM (0x1c8) +#define APBDEV_PMC_SEL_DPD_TIM_SEL_DPD_TIM_DEFAULT (0x7f) +#define APBDEV_PMC_IO_DPD2_REQ (0x1c0) +#define APBDEV_PMC_IO_DPD2_REQ_LVDS_SHIFT (25) +#define APBDEV_PMC_IO_DPD2_REQ_LVDS_OFF (0 << 25) +#define APBDEV_PMC_IO_DPD2_REQ_LVDS_ON (1 << 25) +#define APBDEV_PMC_IO_DPD2_REQ_CODE_SHIFT (30) +#define APBDEV_PMC_IO_DPD2_REQ_CODE_DEFAULT_MASK (0x3 << 30) +#define APBDEV_PMC_IO_DPD2_REQ_CODE_IDLE (0 << 30) +#define APBDEV_PMC_IO_DPD2_REQ_CODE_DPD_OFF (1 << 30) +#define APBDEV_PMC_IO_DPD2_REQ_CODE_DPD_ON (2 << 30) +#define APBDEV_PMC_IO_DPD2_STATUS (0x1c4) +#define APBDEV_PMC_IO_DPD2_STATUS_LVDS_SHIFT (25) +#define APBDEV_PMC_IO_DPD2_STATUS_LVDS_OFF (0 << 25) +#define APBDEV_PMC_IO_DPD2_STATUS_LVDS_ON (1 << 25) + + +static inline u32 tegra_sor_readl(struct tegra_dc_sor_data *sor, u32 reg) +{ + u32 reg_val = readl((sor->base + reg * 4)); + return reg_val; +} + +static inline void tegra_sor_writel(struct tegra_dc_sor_data *sor, + u32 reg, u32 val) +{ + writel(val, (sor->base + reg * 4)); +} + +static inline void tegra_sor_write_field(struct tegra_dc_sor_data *sor, + u32 reg, u32 mask, u32 val) +{ + u32 reg_val = tegra_sor_readl(sor, reg); + reg_val &= ~mask; + reg_val |= val; + tegra_sor_writel(sor, reg, reg_val); +} + +void tegra_dc_sor_set_dp_linkctl(struct tegra_dc_sor_data *sor, int ena, + u8 training_pattern, const struct tegra_dc_dp_link_config *cfg) +{ + u32 reg_val; + + reg_val = tegra_sor_readl(sor, NV_SOR_DP_LINKCTL(sor->portnum)); + + if (ena) + reg_val |= NV_SOR_DP_LINKCTL_ENABLE_YES; + else + reg_val &= NV_SOR_DP_LINKCTL_ENABLE_NO; + + reg_val &= ~NV_SOR_DP_LINKCTL_TUSIZE_MASK; + reg_val |= (cfg->tu_size << NV_SOR_DP_LINKCTL_TUSIZE_SHIFT); + + if (cfg->enhanced_framing) + reg_val |= NV_SOR_DP_LINKCTL_ENHANCEDFRAME_ENABLE; + + tegra_sor_writel(sor, NV_SOR_DP_LINKCTL(sor->portnum), reg_val); + + switch (training_pattern) { + case trainingPattern_1: + tegra_sor_writel(sor, NV_SOR_DP_TPG, 0x41414141); + break; + case trainingPattern_2: + case trainingPattern_3: + reg_val = (cfg->link_bw == NV_SOR_LINK_SPEED_G5_4) ? + 0x43434343 : 0x42424242; + tegra_sor_writel(sor, NV_SOR_DP_TPG, reg_val); + break; + default: + tegra_sor_writel(sor, NV_SOR_DP_TPG, 0x50505050); + break; + } +} + +void tegra_dc_sor_set_dp_lanedata(struct tegra_dc_sor_data *sor, + u32 lane, u32 pre_emphasis, u32 drive_current, u32 tx_pu) +{ + u32 d_cur; + u32 p_emp; + + + d_cur = tegra_sor_readl(sor, NV_SOR_DC(sor->portnum)); + p_emp = tegra_sor_readl(sor, NV_SOR_PR(sor->portnum)); + + switch (lane) { + case 0: + p_emp &= ~NV_SOR_PR_LANE2_DP_LANE0_MASK; + p_emp |= (pre_emphasis << + NV_SOR_PR_LANE2_DP_LANE0_SHIFT); + d_cur &= ~NV_SOR_DC_LANE2_DP_LANE0_MASK; + d_cur |= (drive_current << + NV_SOR_DC_LANE2_DP_LANE0_SHIFT); + break; + case 1: + p_emp &= ~NV_SOR_PR_LANE1_DP_LANE1_MASK; + p_emp |= (pre_emphasis << + NV_SOR_PR_LANE1_DP_LANE1_SHIFT); + d_cur &= ~NV_SOR_DC_LANE1_DP_LANE1_MASK; + d_cur |= (drive_current << + NV_SOR_DC_LANE1_DP_LANE1_SHIFT); + break; + case 2: + p_emp &= ~NV_SOR_PR_LANE0_DP_LANE2_MASK; + p_emp |= (pre_emphasis << + NV_SOR_PR_LANE0_DP_LANE2_SHIFT); + d_cur &= ~NV_SOR_DC_LANE0_DP_LANE2_MASK; + d_cur |= (drive_current << + NV_SOR_DC_LANE0_DP_LANE2_SHIFT); + break; + case 3: + p_emp &= ~NV_SOR_PR_LANE3_DP_LANE3_MASK; + p_emp |= (pre_emphasis << + NV_SOR_PR_LANE3_DP_LANE3_SHIFT); + d_cur &= ~NV_SOR_DC_LANE3_DP_LANE3_MASK; + d_cur |= (drive_current << + NV_SOR_DC_LANE3_DP_LANE3_SHIFT); + break; + default: + printk(BIOS_SPEW, "dp: sor lane count %d is invalid\n", lane); + } + + tegra_sor_write_field(sor, NV_SOR_DP_LINKCTL(sor->portnum), + NV_SOR_DP_PADCTL_TX_PU_VALUE_DEFAULT_MASK, + tx_pu << NV_SOR_DP_PADCTL_TX_PU_VALUE_SHIFT); + + tegra_sor_writel(sor, NV_SOR_DC(sor->portnum), d_cur); + tegra_sor_writel(sor, NV_SOR_PR(sor->portnum), p_emp); +} + diff --git a/src/soc/nvidia/tegra124/sor.h b/src/soc/nvidia/tegra124/sor.h new file mode 100644 index 0000000..dec2692 --- /dev/null +++ b/src/soc/nvidia/tegra124/sor.h @@ -0,0 +1,908 @@ +/* + * drivers/video/tegra/dc/sor_regs.h + * + * Copyright (c) 2011-2013, NVIDIA Corporation. + * + * This software is licensed under the terms of the GNU General Public + * License version 2, as published by the Free Software Foundation, and + * may be copied, distributed, and modified under those terms. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef __TEGRA124_SOR_H__ +#define __TEGRA124_SOR_H__ + + +#define NV_SOR_SUPER_STATE0 (0x1) +#define NV_SOR_SUPER_STATE0_UPDATE_SHIFT (0) +#define NV_SOR_SUPER_STATE0_UPDATE_DEFAULT_MASK (0x1) +#define NV_SOR_SUPER_STATE1 (0x2) +#define NV_SOR_SUPER_STATE1_ATTACHED_SHIFT (3) +#define NV_SOR_SUPER_STATE1_ATTACHED_NO (0 << 3) +#define NV_SOR_SUPER_STATE1_ATTACHED_YES (1 << 3) +#define NV_SOR_SUPER_STATE1_ASY_ORMODE_SHIFT (2) +#define NV_SOR_SUPER_STATE1_ASY_ORMODE_SAFE (0 << 2) +#define NV_SOR_SUPER_STATE1_ASY_ORMODE_NORMAL (1 << 2) +#define NV_SOR_SUPER_STATE1_ASY_HEAD_OP_SHIFT (0) +#define NV_SOR_SUPER_STATE1_ASY_HEAD_OP_DEFAULT_MASK (0x3) +#define NV_SOR_SUPER_STATE1_ASY_HEAD_OP_SLEEP (0) +#define NV_SOR_SUPER_STATE1_ASY_HEAD_OP_SNOOZE (1) +#define NV_SOR_SUPER_STATE1_ASY_HEAD_OP_AWAKE (2) +#define NV_SOR_STATE0 (0x3) +#define NV_SOR_STATE0_UPDATE_SHIFT (0) +#define NV_SOR_STATE0_UPDATE_DEFAULT_MASK (0x1) +#define NV_SOR_STATE1 (0x4) +#define NV_SOR_STATE1_ASY_PIXELDEPTH_SHIFT (17) +#define NV_SOR_STATE1_ASY_PIXELDEPTH_DEFAULT_MASK (0xf << 17) +#define NV_SOR_STATE1_ASY_PIXELDEPTH_BPP_16_422 (1 << 17) +#define NV_SOR_STATE1_ASY_PIXELDEPTH_BPP_18_444 (2 << 17) +#define NV_SOR_STATE1_ASY_PIXELDEPTH_BPP_20_422 (3 << 17) +#define NV_SOR_STATE1_ASY_PIXELDEPTH_BPP_24_422 (4 << 17) +#define NV_SOR_STATE1_ASY_PIXELDEPTH_BPP_24_444 (5 << 17) +#define NV_SOR_STATE1_ASY_PIXELDEPTH_BPP_30_444 (6 << 17) +#define NV_SOR_STATE1_ASY_PIXELDEPTH_BPP_32_422 (7 << 17) +#define NV_SOR_STATE1_ASY_PIXELDEPTH_BPP_36_444 (8 << 17) +#define NV_SOR_STATE1_ASY_PIXELDEPTH_BPP_48_444 (9 << 17) +#define NV_SOR_STATE1_ASY_REPLICATE_SHIFT (15) +#define NV_SOR_STATE1_ASY_REPLICATE_DEFAULT_MASK (0x3 << 15) +#define NV_SOR_STATE1_ASY_REPLICATE_OFF (0 << 15) +#define NV_SOR_STATE1_ASY_REPLICATE_X2 (1 << 15) +#define NV_SOR_STATE1_ASY_REPLICATE_X4 (2 << 15) +#define NV_SOR_STATE1_ASY_DEPOL_SHIFT (14) +#define NV_SOR_STATE1_ASY_DEPOL_DEFAULT_MASK (0x1 << 14) +#define NV_SOR_STATE1_ASY_DEPOL_POSITIVE_TRUE (0 << 14) +#define NV_SOR_STATE1_ASY_DEPOL_NEGATIVE_TRUE (1 << 14) +#define NV_SOR_STATE1_ASY_VSYNCPOL_SHIFT (13) +#define NV_SOR_STATE1_ASY_VSYNCPOL_DEFAULT_MASK (0x1 << 13) +#define NV_SOR_STATE1_ASY_VSYNCPOL_POSITIVE_TRUE (0 << 13) +#define NV_SOR_STATE1_ASY_VSYNCPOL_NEGATIVE_TRUE (1 << 13) +#define NV_SOR_STATE1_ASY_HSYNCPOL_SHIFT (12) +#define NV_SOR_STATE1_ASY_HSYNCPOL_DEFAULT_MASK (0x1 << 12) +#define NV_SOR_STATE1_ASY_HSYNCPOL_POSITIVE_TRUE (0 << 12) +#define NV_SOR_STATE1_ASY_HSYNCPOL_NEGATIVE_TRUE (1 << 12) +#define NV_SOR_STATE1_ASY_PROTOCOL_SHIFT (8) +#define NV_SOR_STATE1_ASY_PROTOCOL_DEFAULT_MASK (0xf << 8) +#define NV_SOR_STATE1_ASY_PROTOCOL_LVDS_CUSTOM (0 << 8) +#define NV_SOR_STATE1_ASY_PROTOCOL_DP_A (8 << 8) +#define NV_SOR_STATE1_ASY_PROTOCOL_DP_B (9 << 8) +#define NV_SOR_STATE1_ASY_PROTOCOL_CUSTOM (15 << 8) +#define NV_SOR_STATE1_ASY_CRCMODE_SHIFT (6) +#define NV_SOR_STATE1_ASY_CRCMODE_DEFAULT_MASK (0x3 << 6) +#define NV_SOR_STATE1_ASY_CRCMODE_ACTIVE_RASTER (0 << 6) +#define NV_SOR_STATE1_ASY_CRCMODE_COMPLETE_RASTER (1 << 6) +#define NV_SOR_STATE1_ASY_CRCMODE_NON_ACTIVE_RASTER (2 << 6) +#define NV_SOR_STATE1_ASY_SUBOWNER_SHIFT (4) +#define NV_SOR_STATE1_ASY_SUBOWNER_DEFAULT_MASK (0x3 << 4) +#define NV_SOR_STATE1_ASY_SUBOWNER_NONE (0 << 4) +#define NV_SOR_STATE1_ASY_SUBOWNER_SUBHEAD0 (1 << 4) +#define NV_SOR_STATE1_ASY_SUBOWNER_SUBHEAD1 (2 << 4) +#define NV_SOR_STATE1_ASY_SUBOWNER_BOTH (3 << 4) +#define NV_SOR_STATE1_ASY_OWNER_SHIFT (0) +#define NV_SOR_STATE1_ASY_OWNER_DEFAULT_MASK (0xf) +#define NV_SOR_STATE1_ASY_OWNER_NONE (0) +#define NV_SOR_STATE1_ASY_OWNER_HEAD0 (1) +#define NV_SOR_STATE1_ASY_OWNER_HEAD1 (2) +#define NV_HEAD_STATE0(i) (0x5) +#define NV_HEAD_STATE0_INTERLACED_SHIFT (4) +#define NV_HEAD_STATE0_INTERLACED_DEFAULT_MASK (0x3 << 4) +#define NV_HEAD_STATE0_INTERLACED_PROGRESSIVE (0 << 4) +#define NV_HEAD_STATE0_INTERLACED_INTERLACED (1 << 4) +#define NV_HEAD_STATE0_RANGECOMPRESS_SHIFT (3) +#define NV_HEAD_STATE0_RANGECOMPRESS_DEFAULT_MASK (0x1 << 3) +#define NV_HEAD_STATE0_RANGECOMPRESS_DISABLE (0 << 3) +#define NV_HEAD_STATE0_RANGECOMPRESS_ENABLE (1 << 3) +#define NV_HEAD_STATE0_DYNRANGE_SHIFT (2) +#define NV_HEAD_STATE0_DYNRANGE_DEFAULT_MASK (0x1 << 2) +#define NV_HEAD_STATE0_DYNRANGE_VESA (0 << 2) +#define NV_HEAD_STATE0_DYNRANGE_CEA (1 << 2) +#define NV_HEAD_STATE0_COLORSPACE_SHIFT (0) +#define NV_HEAD_STATE0_COLORSPACE_DEFAULT_MASK (0x3) +#define NV_HEAD_STATE0_COLORSPACE_RGB (0) +#define NV_HEAD_STATE0_COLORSPACE_YUV_601 (1) +#define NV_HEAD_STATE0_COLORSPACE_YUV_709 (2) +#define NV_HEAD_STATE1(i) (0x7 + i) +#define NV_HEAD_STATE1_VTOTAL_SHIFT (16) +#define NV_HEAD_STATE1_VTOTAL_DEFAULT_MASK (0x7fff << 16) +#define NV_HEAD_STATE1_HTOTAL_SHIFT (0) +#define NV_HEAD_STATE1_HTOTAL_DEFAULT_MASK (0x7fff) +#define NV_HEAD_STATE2(i) (0x9 + i) +#define NV_HEAD_STATE2_VSYNC_END_SHIFT (16) +#define NV_HEAD_STATE2_VSYNC_END_DEFAULT_MASK (0x7fff << 16) +#define NV_HEAD_STATE2_HSYNC_END_SHIFT (0) +#define NV_HEAD_STATE2_HSYNC_END_DEFAULT_MASK (0x7fff) +#define NV_HEAD_STATE3(i) (0xb + i) +#define NV_HEAD_STATE3_VBLANK_END_SHIFT (16) +#define NV_HEAD_STATE3_VBLANK_END_DEFAULT_MASK (0x7fff << 16) +#define NV_HEAD_STATE3_HBLANK_END_SHIFT (0) +#define NV_HEAD_STATE3_HBLANK_END_DEFAULT_MASK (0x7fff) +#define NV_HEAD_STATE4(i) (0xd + i) +#define NV_HEAD_STATE4_VBLANK_START_SHIFT (16) +#define NV_HEAD_STATE4_VBLANK_START_DEFAULT_MASK (0x7fff << 16) +#define NV_HEAD_STATE4_HBLANK_START_SHIFT (0) +#define NV_HEAD_STATE4_HBLANK_START_DEFAULT_MASK (0x7fff) +#define NV_HEAD_STATE5(i) (0xf + i) +#define NV_SOR_CRC_CNTRL (0x11) +#define NV_SOR_CRC_CNTRL_ARM_CRC_ENABLE_SHIFT (0) +#define NV_SOR_CRC_CNTRL_ARM_CRC_ENABLE_NO (0) +#define NV_SOR_CRC_CNTRL_ARM_CRC_ENABLE_YES (1) +#define NV_SOR_CRC_CNTRL_ARM_CRC_ENABLE_DIS (0) +#define NV_SOR_CRC_CNTRL_ARM_CRC_ENABLE_EN (1) +#define NV_SOR_CLK_CNTRL (0x13) +#define NV_SOR_CLK_CNTRL_DP_CLK_SEL_SHIFT (0) +#define NV_SOR_CLK_CNTRL_DP_CLK_SEL_MASK (0x3) +#define NV_SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_PCLK (0) +#define NV_SOR_CLK_CNTRL_DP_CLK_SEL_DIFF_PCLK (1) +#define NV_SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_DPCLK (2) +#define NV_SOR_CLK_CNTRL_DP_CLK_SEL_DIFF_DPCLK (3) +#define NV_SOR_CLK_CNTRL_DP_LINK_SPEED_SHIFT (2) +#define NV_SOR_CLK_CNTRL_DP_LINK_SPEED_MASK (0x1f << 2) +#define NV_SOR_CLK_CNTRL_DP_LINK_SPEED_G1_62 (6 << 2) +#define NV_SOR_CLK_CNTRL_DP_LINK_SPEED_G2_7 (10 << 2) +#define NV_SOR_CLK_CNTRL_DP_LINK_SPEED_LVDS (7 << 2) +#define NV_SOR_CAP (0x14) +#define NV_SOR_CAP_DP_A_SHIFT (24) +#define NV_SOR_CAP_DP_A_DEFAULT_MASK (0x1 << 24) +#define NV_SOR_CAP_DP_A_FALSE (0 << 24) +#define NV_SOR_CAP_DP_A_TRUE (1 << 24) +#define NV_SOR_CAP_DP_B_SHIFT (25) +#define NV_SOR_CAP_DP_B_DEFAULT_MASK (0x1 << 24) +#define NV_SOR_CAP_DP_B_FALSE (0 << 24) +#define NV_SOR_CAP_DP_B_TRUE (1 << 24) +#define NV_SOR_PWR (0x15) +#define NV_SOR_PWR_SETTING_NEW_SHIFT (31) +#define NV_SOR_PWR_SETTING_NEW_DEFAULT_MASK (0x1 << 31) +#define NV_SOR_PWR_SETTING_NEW_DONE (0 << 31) +#define NV_SOR_PWR_SETTING_NEW_PENDING (1 << 31) +#define NV_SOR_PWR_SETTING_NEW_TRIGGER (1 << 31) +#define NV_SOR_PWR_MODE_SHIFT (28) +#define NV_SOR_PWR_MODE_DEFAULT_MASK (0x1 << 28) +#define NV_SOR_PWR_MODE_NORMAL (0 << 28) +#define NV_SOR_PWR_MODE_SAFE (1 << 28) +#define NV_SOR_PWR_HALT_DELAY_SHIFT (24) +#define NV_SOR_PWR_HALT_DELAY_DEFAULT_MASK (0x1 << 24) +#define NV_SOR_PWR_HALT_DELAY_DONE (0 << 24) +#define NV_SOR_PWR_HALT_DELAY_ACTIVE (1 << 24) +#define NV_SOR_PWR_SAFE_START_SHIFT (17) +#define NV_SOR_PWR_SAFE_START_DEFAULT_MASK (0x1 << 17) +#define NV_SOR_PWR_SAFE_START_NORMAL (0 << 17) +#define NV_SOR_PWR_SAFE_START_ALT (1 << 17) +#define NV_SOR_PWR_SAFE_STATE_SHIFT (16) +#define NV_SOR_PWR_SAFE_STATE_DEFAULT_MASK (0x1 << 16) +#define NV_SOR_PWR_SAFE_STATE_PD (0 << 16) +#define NV_SOR_PWR_SAFE_STATE_PU (1 << 16) +#define NV_SOR_PWR_NORMAL_START_SHIFT (1) +#define NV_SOR_PWR_NORMAL_START_DEFAULT_MASK (0x1 << 1) +#define NV_SOR_PWR_NORMAL_START_NORMAL (0 << 16) +#define NV_SOR_PWR_NORMAL_START_ALT (1 << 16) +#define NV_SOR_PWR_NORMAL_STATE_SHIFT (0) +#define NV_SOR_PWR_NORMAL_STATE_DEFAULT_MASK (0x1) +#define NV_SOR_PWR_NORMAL_STATE_PD (0) +#define NV_SOR_PWR_NORMAL_STATE_PU (1) +#define NV_SOR_TEST (0x16) +#define NV_SOR_TEST_TESTMUX_SHIFT (24) +#define NV_SOR_TEST_TESTMUX_DEFAULT_MASK (0xff << 24) +#define NV_SOR_TEST_TESTMUX_AVSS (0 << 24) +#define NV_SOR_TEST_TESTMUX_CLOCKIN (2 << 24) +#define NV_SOR_TEST_TESTMUX_PLL_VOL (4 << 24) +#define NV_SOR_TEST_TESTMUX_SLOWCLKINT (8 << 24) +#define NV_SOR_TEST_TESTMUX_AVDD (16 << 24) +#define NV_SOR_TEST_TESTMUX_VDDREG (32 << 24) +#define NV_SOR_TEST_TESTMUX_REGREF_VDDREG (64 << 24) +#define NV_SOR_TEST_TESTMUX_REGREF_AVDD (128 << 24) +#define NV_SOR_TEST_CRC_SHIFT (23) +#define NV_SOR_TEST_CRC_PRE_SERIALIZE (0 << 23) +#define NV_SOR_TEST_CRC_POST_DESERIALIZE (1 << 23) +#define NV_SOR_TEST_TPAT_SHIFT (20) +#define NV_SOR_TEST_TPAT_DEFAULT_MASK (0x7 << 20) +#define NV_SOR_TEST_TPAT_LO (0 << 20) +#define NV_SOR_TEST_TPAT_TDAT (1 << 20) +#define NV_SOR_TEST_TPAT_RAMP (2 << 20) +#define NV_SOR_TEST_TPAT_WALK (3 << 20) +#define NV_SOR_TEST_TPAT_MAXSTEP (4 << 20) +#define NV_SOR_TEST_TPAT_MINSTEP (5 << 20) +#define NV_SOR_TEST_DSRC_SHIFT (16) +#define NV_SOR_TEST_DSRC_DEFAULT_MASK (0x3 << 16) +#define NV_SOR_TEST_DSRC_NORMAL (0 << 16) +#define NV_SOR_TEST_DSRC_DEBUG (1 << 16) +#define NV_SOR_TEST_DSRC_TGEN (2 << 16) +#define NV_SOR_TEST_HEAD_NUMBER_SHIFT (12) +#define NV_SOR_TEST_HEAD_NUMBER_DEFAULT_MASK (0x3 << 12) +#define NV_SOR_TEST_HEAD_NUMBER_NONE (0 << 12) +#define NV_SOR_TEST_HEAD_NUMBER_HEAD0 (1 << 12) +#define NV_SOR_TEST_HEAD_NUMBER_HEAD1 (2 << 12) +#define NV_SOR_TEST_ATTACHED_SHIFT (10) +#define NV_SOR_TEST_ATTACHED_DEFAULT_MASK (0x1 << 10) +#define NV_SOR_TEST_ATTACHED_FALSE (0 << 10) +#define NV_SOR_TEST_ATTACHED_TRUE (1 << 10) +#define NV_SOR_TEST_ACT_HEAD_OPMODE_SHIFT (8) +#define NV_SOR_TEST_ACT_HEAD_OPMODE_DEFAULT_MASK (0x3 << 8) +#define NV_SOR_TEST_ACT_HEAD_OPMODE_SLEEP (0 << 8) +#define NV_SOR_TEST_ACT_HEAD_OPMODE_SNOOZE (1 << 8) +#define NV_SOR_TEST_ACT_HEAD_OPMODE_AWAKE (2 << 8) +#define NV_SOR_TEST_INVD_SHIFT (6) +#define NV_SOR_TEST_INVD_DISABLE (0 << 6) +#define NV_SOR_TEST_INVD_ENABLE (1 << 6) +#define NV_SOR_TEST_TEST_ENABLE_SHIFT (1) +#define NV_SOR_TEST_TEST_ENABLE_DISABLE (0 << 1) +#define NV_SOR_TEST_TEST_ENABLE_ENABLE (1 << 1) +#define NV_SOR_PLL0 (0x17) +#define NV_SOR_PLL0_ICHPMP_SHFIT (24) +#define NV_SOR_PLL0_ICHPMP_DEFAULT_MASK (0xf << 24) +#define NV_SOR_PLL0_VCOCAP_SHIFT (8) +#define NV_SOR_PLL0_VCOCAP_DEFAULT_MASK (0xf << 8) +#define NV_SOR_PLL0_PLLREG_LEVEL_SHIFT (6) +#define NV_SOR_PLL0_PLLREG_LEVEL_DEFAULT_MASK (0x3 << 6) +#define NV_SOR_PLL0_PLLREG_LEVEL_V25 (0 << 6) +#define NV_SOR_PLL0_PLLREG_LEVEL_V15 (1 << 6) +#define NV_SOR_PLL0_PLLREG_LEVEL_V35 (2 << 6) +#define NV_SOR_PLL0_PLLREG_LEVEL_V45 (3 << 6) +#define NV_SOR_PLL0_PULLDOWN_SHIFT (5) +#define NV_SOR_PLL0_PULLDOWN_DEFAULT_MASK (0x1 << 5) +#define NV_SOR_PLL0_PULLDOWN_DISABLE (0 << 5) +#define NV_SOR_PLL0_PULLDOWN_ENABLE (1 << 5) +#define NV_SOR_PLL0_RESISTORSEL_SHIFT (4) +#define NV_SOR_PLL0_RESISTORSEL_DEFAULT_MASK (0x1 << 4) +#define NV_SOR_PLL0_RESISTORSEL_INT (0 << 4) +#define NV_SOR_PLL0_RESISTORSEL_EXT (1 << 4) +#define NV_SOR_PLL0_VCOPD_SHIFT (2) +#define NV_SOR_PLL0_VCOPD_MASK (1 << 2) +#define NV_SOR_PLL0_VCOPD_RESCIND (0 << 2) +#define NV_SOR_PLL0_VCOPD_ASSERT (1 << 2) +#define NV_SOR_PLL0_PWR_SHIFT (0) +#define NV_SOR_PLL0_PWR_MASK (1) +#define NV_SOR_PLL0_PWR_ON (0) +#define NV_SOR_PLL0_PWR_OFF (1) +#define NV_SOR_PLL1_TMDS_TERM_SHIFT (8) +#define NV_SOR_PLL1_TMDS_TERM_DISABLE (0 << 8) +#define NV_SOR_PLL1_TMDS_TERM_ENABLE (1 << 8) +#define NV_SOR_PLL1 (0x18) +#define NV_SOR_PLL1_TERM_COMPOUT_SHIFT (15) +#define NV_SOR_PLL1_TERM_COMPOUT_LOW (0 << 15) +#define NV_SOR_PLL1_TERM_COMPOUT_HIGH (1 << 15) +#define NV_SOR_PLL2 (0x19) +#define NV_SOR_PLL2_DCIR_PLL_RESET_SHIFT (0) +#define NV_SOR_PLL2_DCIR_PLL_RESET_OVERRIDE (0 << 0) +#define NV_SOR_PLL2_DCIR_PLL_RESET_ALLOW (1 << 0) +#define NV_SOR_PLL2_AUX1_SHIFT (17) +#define NV_SOR_PLL2_AUX1_SEQ_MASK (1 << 17) +#define NV_SOR_PLL2_AUX1_SEQ_PLLCAPPD_ALLOW (0 << 17) +#define NV_SOR_PLL2_AUX1_SEQ_PLLCAPPD_OVERRIDE (1 << 17) +#define NV_SOR_PLL2_AUX2_SHIFT (18) +#define NV_SOR_PLL2_AUX2_MASK (1 << 18) +#define NV_SOR_PLL2_AUX2_OVERRIDE_POWERDOWN (0 << 18) +#define NV_SOR_PLL2_AUX2_ALLOW_POWERDOWN (1 << 18) +#define NV_SOR_PLL2_AUX6_SHIFT (22) +#define NV_SOR_PLL2_AUX6_BANDGAP_POWERDOWN_MASK (1 << 22) +#define NV_SOR_PLL2_AUX6_BANDGAP_POWERDOWN_DISABLE (0 << 22) +#define NV_SOR_PLL2_AUX6_BANDGAP_POWERDOWN_ENABLE (1 << 22) +#define NV_SOR_PLL2_AUX7_SHIFT (23) +#define NV_SOR_PLL2_AUX7_PORT_POWERDOWN_MASK (1 << 23) +#define NV_SOR_PLL2_AUX7_PORT_POWERDOWN_DISABLE (0 << 23) +#define NV_SOR_PLL2_AUX7_PORT_POWERDOWN_ENABLE (1 << 23) +#define NV_SOR_PLL2_AUX8_SHIFT (24) +#define NV_SOR_PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_MASK (1 << 24) +#define NV_SOR_PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_DISABLE (0 << 24) +#define NV_SOR_PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_ENABLE (1 << 24) +#define NV_SOR_PLL2_AUX9_SHIFT (25) +#define NV_SOR_PLL2_AUX9_LVDSEN_ALLOW (0 << 25) +#define NV_SOR_PLL2_AUX9_LVDSEN_OVERRIDE (1 << 25) +#define NV_SOR_PLL3 (0x1a) +#define NV_SOR_PLL3_PLLVDD_MODE_SHIFT (13) +#define NV_SOR_PLL3_PLLVDD_MODE_MASK (1 << 13) +#define NV_SOR_PLL3_PLLVDD_MODE_V1_8 (0 << 13) +#define NV_SOR_PLL3_PLLVDD_MODE_V3_3 (1 << 13) +#define NV_SOR_CSTM (0x1b) +#define NV_SOR_CSTM_ROTDAT_SHIFT (28) +#define NV_SOR_CSTM_ROTDAT_DEFAULT_MASK (0x7 << 28) +#define NV_SOR_CSTM_ROTCLK_SHIFT (24) +#define NV_SOR_CSTM_ROTCLK_DEFAULT_MASK (0xf << 24) +#define NV_SOR_CSTM_LVDS_EN_SHIFT (16) +#define NV_SOR_CSTM_LVDS_EN_DISABLE (0 << 16) +#define NV_SOR_CSTM_LVDS_EN_ENABLE (1 << 16) +#define NV_SOR_CSTM_LINKACTB_SHIFT (15) +#define NV_SOR_CSTM_LINKACTB_DISABLE (0 << 15) +#define NV_SOR_CSTM_LINKACTB_ENABLE (1 << 15) +#define NV_SOR_CSTM_LINKACTA_SHIFT (14) +#define NV_SOR_CSTM_LINKACTA_DISABLE (0 << 14) +#define NV_SOR_CSTM_LINKACTA_ENABLE (1 << 14) +#define NV_SOR_LVDS (0x1c) +#define NV_SOR_LVDS_ROTDAT_SHIFT (28) +#define NV_SOR_LVDS_ROTDAT_DEFAULT_MASK (0x7 << 28) +#define NV_SOR_LVDS_ROTDAT_RST (0 << 28) +#define NV_SOR_LVDS_ROTCLK_SHIFT (24) +#define NV_SOR_LVDS_ROTCLK_DEFAULT_MASK (0xf << 24) +#define NV_SOR_LVDS_ROTCLK_RST (0 << 24) +#define NV_SOR_LVDS_PLLDIV_SHIFT (21) +#define NV_SOR_LVDS_PLLDIV_DEFAULT_MASK (0x1 << 21) +#define NV_SOR_LVDS_PLLDIV_BY_7 (0 << 21) +#define NV_SOR_LVDS_BALANCED_SHIFT (19) +#define NV_SOR_LVDS_BALANCED_DEFAULT_MASK (0x1 << 19) +#define NV_SOR_LVDS_BALANCED_DISABLE (0 << 19) +#define NV_SOR_LVDS_BALANCED_ENABLE (1 << 19) +#define NV_SOR_LVDS_NEW_MODE_SHIFT (18) +#define NV_SOR_LVDS_NEW_MODE_DEFAULT_MASK (0x1 << 18) +#define NV_SOR_LVDS_NEW_MODE_DISABLE (0 << 18) +#define NV_SOR_LVDS_NEW_MODE_ENABLE (1 << 18) +#define NV_SOR_LVDS_DUP_SYNC_SHIFT (17) +#define NV_SOR_LVDS_DUP_SYNC_DEFAULT_MASK (0x1 << 17) +#define NV_SOR_LVDS_DUP_SYNC_DISABLE (0 << 17) +#define NV_SOR_LVDS_DUP_SYNC_ENABLE (1 << 17) +#define NV_SOR_LVDS_LVDS_EN_SHIFT (16) +#define NV_SOR_LVDS_LVDS_EN_DEFAULT_MASK (0x1 << 16) +#define NV_SOR_LVDS_LVDS_EN_ENABLE (1 << 16) +#define NV_SOR_LVDS_LINKACTB_SHIFT (15) +#define NV_SOR_LVDS_LINKACTB_DEFAULT_MASK (0x1 << 15) +#define NV_SOR_LVDS_LINKACTB_DISABLE (0 << 15) +#define NV_SOR_LVDS_LINKACTB_ENABLE (1 << 15) +#define NV_SOR_LVDS_LINKACTA_SHIFT (14) +#define NV_SOR_LVDS_LINKACTA_DEFAULT_MASK (0x1 << 14) +#define NV_SOR_LVDS_LINKACTA_ENABLE (1 << 14) +#define NV_SOR_LVDS_MODE_SHIFT (12) +#define NV_SOR_LVDS_MODE_DEFAULT_MASK (0x3 << 12) +#define NV_SOR_LVDS_MODE_LVDS (0 << 12) +#define NV_SOR_LVDS_UPPER_SHIFT (11) +#define NV_SOR_LVDS_UPPER_DEFAULT_MASK (0x1 << 11) +#define NV_SOR_LVDS_UPPER_FALSE (0 << 11) +#define NV_SOR_LVDS_UPPER_TRUE (1 << 11) +#define NV_SOR_LVDS_PD_TXCB_SHIFT (9) +#define NV_SOR_LVDS_PD_TXCB_DEFAULT_MASK (0x1 << 9) +#define NV_SOR_LVDS_PD_TXCB_ENABLE (0 << 9) +#define NV_SOR_LVDS_PD_TXCB_DISABLE (1 << 9) +#define NV_SOR_LVDS_PD_TXCA_SHIFT (8) +#define NV_SOR_LVDS_PD_TXCA_DEFAULT_MASK (0x1 << 8) +#define NV_SOR_LVDS_PD_TXCA_ENABLE (0 << 8) +#define NV_SOR_LVDS_PD_TXDB_3_SHIFT (7) +#define NV_SOR_LVDS_PD_TXDB_3_DEFAULT_MASK (0x1 << 7) +#define NV_SOR_LVDS_PD_TXDB_3_ENABLE (0 << 7) +#define NV_SOR_LVDS_PD_TXDB_3_DISABLE (1 << 7) +#define NV_SOR_LVDS_PD_TXDB_2_SHIFT (6) +#define NV_SOR_LVDS_PD_TXDB_2_DEFAULT_MASK (0x1 << 6) +#define NV_SOR_LVDS_PD_TXDB_2_ENABLE (0 << 6) +#define NV_SOR_LVDS_PD_TXDB_2_DISABLE (1 << 6) +#define NV_SOR_LVDS_PD_TXDB_1_SHIFT (5) +#define NV_SOR_LVDS_PD_TXDB_1_DEFAULT_MASK (0x1 << 5) +#define NV_SOR_LVDS_PD_TXDB_1_ENABLE (0 << 5) +#define NV_SOR_LVDS_PD_TXDB_1_DISABLE (1 << 5) +#define NV_SOR_LVDS_PD_TXDB_0_SHIFT (4) +#define NV_SOR_LVDS_PD_TXDB_0_DEFAULT_MASK (0x1 << 4) +#define NV_SOR_LVDS_PD_TXDB_0_ENABLE (0 << 4) +#define NV_SOR_LVDS_PD_TXDB_0_DISABLE (1 << 4) +#define NV_SOR_LVDS_PD_TXDA_3_SHIFT (3) +#define NV_SOR_LVDS_PD_TXDA_3_DEFAULT_MASK (0x1 << 3) +#define NV_SOR_LVDS_PD_TXDA_3_ENABLE (0 << 3) +#define NV_SOR_LVDS_PD_TXDA_3_DISABLE (1 << 3) +#define NV_SOR_LVDS_PD_TXDA_2_SHIFT (2) +#define NV_SOR_LVDS_PD_TXDA_2_DEFAULT_MASK (0x1 << 2) +#define NV_SOR_LVDS_PD_TXDA_2_ENABLE (0 << 2) +#define NV_SOR_LVDS_PD_TXDA_1_SHIFT (1) +#define NV_SOR_LVDS_PD_TXDA_1_DEFAULT_MASK (0x1 << 1) +#define NV_SOR_LVDS_PD_TXDA_1_ENABLE (0 << 1) +#define NV_SOR_LVDS_PD_TXDA_0_SHIFT (0) +#define NV_SOR_LVDS_PD_TXDA_0_DEFAULT_MASK (0x1) +#define NV_SOR_LVDS_PD_TXDA_0_ENABLE (0) +#define NV_SOR_CRCA (0x1d) +#define NV_SOR_CRCA_VALID_FALSE (0) +#define NV_SOR_CRCA_VALID_TRUE (1) +#define NV_SOR_CRCA_VALID_RST (1) +#define NV_SOR_CRCB (0x1e) +#define NV_SOR_CRCB_CRC_DEFAULT_MASK (0xffffffff) +#define NV_SOR_SEQ_CTL (0x20) +#define NV_SOR_SEQ_CTL_SWITCH_SHIFT (30) +#define NV_SOR_SEQ_CTL_SWITCH_MASK (0x1 << 30) +#define NV_SOR_SEQ_CTL_SWITCH_WAIT (0 << 30) +#define NV_SOR_SEQ_CTL_SWITCH_FORCE (1 << 30) +#define NV_SOR_SEQ_CTL_STATUS_SHIFT (28) +#define NV_SOR_SEQ_CTL_STATUS_MASK (0x1 << 28) +#define NV_SOR_SEQ_CTL_STATUS_STOPPED (0 << 28) +#define NV_SOR_SEQ_CTL_STATUS_RUNNING (1 << 28) +#define NV_SOR_SEQ_CTL_PC_SHIFT (16) +#define NV_SOR_SEQ_CTL_PC_MASK (0xf << 16) +#define NV_SOR_SEQ_CTL_PD_PC_ALT_SHIFT (12) +#define NV_SOR_SEQ_CTL_PD_PC_ALT_MASK (0xf << 12) +#define NV_SOR_SEQ_CTL_PD_PC_SHIFT (8) +#define NV_SOR_SEQ_CTL_PD_PC_MASK (0xf << 8) +#define NV_SOR_SEQ_CTL_PU_PC_ALT_SHIFT (4) +#define NV_SOR_SEQ_CTL_PU_PC_ALT_MASK (0xf << 4) +#define NV_SOR_SEQ_CTL_PU_PC_SHIFT (0) +#define NV_SOR_SEQ_CTL_PU_PC_MASK (0xf) +#define NV_SOR_LANE_SEQ_CTL (0x21) +#define NV_SOR_LANE_SEQ_CTL_SETTING_NEW_SHIFT (31) +#define NV_SOR_LANE_SEQ_CTL_SETTING_MASK (1 << 31) +#define NV_SOR_LANE_SEQ_CTL_SETTING_NEW_DONE (0 << 31) +#define NV_SOR_LANE_SEQ_CTL_SETTING_NEW_PENDING (1 << 31) +#define NV_SOR_LANE_SEQ_CTL_SETTING_NEW_TRIGGER (1 << 31) +#define NV_SOR_LANE_SEQ_CTL_SEQ_STATE_SHIFT (28) +#define NV_SOR_LANE_SEQ_CTL_SEQ_STATE_IDLE (0 << 28) +#define NV_SOR_LANE_SEQ_CTL_SEQ_STATE_BUSY (1 << 28) +#define NV_SOR_LANE_SEQ_CTL_SEQUENCE_SHIFT (20) +#define NV_SOR_LANE_SEQ_CTL_SEQUENCE_UP (0 << 20) +#define NV_SOR_LANE_SEQ_CTL_SEQUENCE_DOWN (1 << 20) +#define NV_SOR_LANE_SEQ_CTL_NEW_POWER_STATE_SHIFT (16) +#define NV_SOR_LANE_SEQ_CTL_NEW_POWER_STATE_PU (0 << 16) +#define NV_SOR_LANE_SEQ_CTL_NEW_POWER_STATE_PD (1 << 16) +#define NV_SOR_LANE_SEQ_CTL_DELAY_SHIFT (12) +#define NV_SOR_LANE_SEQ_CTL_DELAY_DEFAULT_MASK (0xf << 12) +#define NV_SOR_LANE_SEQ_CTL_LANE9_STATE_SHIFT (9) +#define NV_SOR_LANE_SEQ_CTL_LANE9_STATE_POWERUP (0 << 9) +#define NV_SOR_LANE_SEQ_CTL_LANE9_STATE_POWERDOWN (1 << 9) +#define NV_SOR_LANE_SEQ_CTL_LANE8_STATE_SHIFT (8) +#define NV_SOR_LANE_SEQ_CTL_LANE8_STATE_POWERUP (0 << 8) +#define NV_SOR_LANE_SEQ_CTL_LANE8_STATE_POWERDOWN (1 << 8) +#define NV_SOR_LANE_SEQ_CTL_LANE7_STATE_SHIFT (7) +#define NV_SOR_LANE_SEQ_CTL_LANE7_STATE_POWERUP (0 << 7) +#define NV_SOR_LANE_SEQ_CTL_LANE7_STATE_POWERDOWN (1 << 7) +#define NV_SOR_LANE_SEQ_CTL_LANE6_STATE_SHIFT (6) +#define NV_SOR_LANE_SEQ_CTL_LANE6_STATE_POWERUP (0 << 6) +#define NV_SOR_LANE_SEQ_CTL_LANE6_STATE_POWERDOWN (1 << 6) +#define NV_SOR_LANE_SEQ_CTL_LANE5_STATE_SHIFT (5) +#define NV_SOR_LANE_SEQ_CTL_LANE5_STATE_POWERUP (0 << 5) +#define NV_SOR_LANE_SEQ_CTL_LANE5_STATE_POWERDOWN (1 << 5) +#define NV_SOR_LANE_SEQ_CTL_LANE4_STATE_SHIFT (4) +#define NV_SOR_LANE_SEQ_CTL_LANE4_STATE_POWERUP (0 << 4) +#define NV_SOR_LANE_SEQ_CTL_LANE4_STATE_POWERDOWN (1 << 4) +#define NV_SOR_LANE_SEQ_CTL_LANE3_STATE_SHIFT (3) +#define NV_SOR_LANE_SEQ_CTL_LANE3_STATE_POWERUP (0 << 3) +#define NV_SOR_LANE_SEQ_CTL_LANE3_STATE_POWERDOWN (1 << 3) +#define NV_SOR_LANE_SEQ_CTL_LANE2_STATE_SHIFT (2) +#define NV_SOR_LANE_SEQ_CTL_LANE2_STATE_POWERUP (0 << 2) +#define NV_SOR_LANE_SEQ_CTL_LANE2_STATE_POWERDOWN (1 << 2) +#define NV_SOR_LANE_SEQ_CTL_LANE1_STATE_SHIFT (1) +#define NV_SOR_LANE_SEQ_CTL_LANE1_STATE_POWERUP (0 << 1) +#define NV_SOR_LANE_SEQ_CTL_LANE1_STATE_POWERDOWN (1 << 1) +#define NV_SOR_LANE_SEQ_CTL_LANE0_STATE_SHIFT (0) +#define NV_SOR_LANE_SEQ_CTL_LANE0_STATE_POWERUP (0) +#define NV_SOR_LANE_SEQ_CTL_LANE0_STATE_POWERDOWN (1) +#define NV_SOR_SEQ_INST(i) (0x22 + i) +#define NV_SOR_SEQ_INST_PLL_PULLDOWN_SHIFT (31) +#define NV_SOR_SEQ_INST_PLL_PULLDOWN_DISABLE (0 << 31) +#define NV_SOR_SEQ_INST_PLL_PULLDOWN_ENABLE (1 << 31) +#define NV_SOR_SEQ_INST_POWERDOWN_MACRO_SHIFT (30) +#define NV_SOR_SEQ_INST_POWERDOWN_MACRO_NORMAL (0 << 30) +#define NV_SOR_SEQ_INST_POWERDOWN_MACRO_POWERDOWN (1 << 30) +#define NV_SOR_SEQ_INST_ASSERT_PLL_RESET_SHIFT (29) +#define NV_SOR_SEQ_INST_ASSERT_PLL_RESET_NORMAL (0 << 29) +#define NV_SOR_SEQ_INST_ASSERT_PLL_RESET_RST (1 << 29) +#define NV_SOR_SEQ_INST_BLANK_V_SHIFT (28) +#define NV_SOR_SEQ_INST_BLANK_V_NORMAL (0 << 28) +#define NV_SOR_SEQ_INST_BLANK_V_INACTIVE (1 << 28) +#define NV_SOR_SEQ_INST_BLANK_H_SHIFT (27) +#define NV_SOR_SEQ_INST_BLANK_H_NORMAL (0 << 27) +#define NV_SOR_SEQ_INST_BLANK_H_INACTIVE (1 << 27) +#define NV_SOR_SEQ_INST_BLANK_DE_SHIFT (26) +#define NV_SOR_SEQ_INST_BLANK_DE_NORMAL (0 << 26) +#define NV_SOR_SEQ_INST_BLANK_DE_INACTIVE (1 << 26) +#define NV_SOR_SEQ_INST_BLACK_DATA_SHIFT (25) +#define NV_SOR_SEQ_INST_BLACK_DATA_NORMAL (0 << 25) +#define NV_SOR_SEQ_INST_BLACK_DATA_BLACK (1 << 25) +#define NV_SOR_SEQ_INST_TRISTATE_IOS_SHIFT (24) +#define NV_SOR_SEQ_INST_TRISTATE_IOS_ENABLE_PINS (0 << 24) +#define NV_SOR_SEQ_INST_TRISTATE_IOS_TRISTATE (1 << 24) +#define NV_SOR_SEQ_INST_DRIVE_PWM_OUT_LO_SHIFT (23) +#define NV_SOR_SEQ_INST_DRIVE_PWM_OUT_LO_FALSE (0 << 23) +#define NV_SOR_SEQ_INST_DRIVE_PWM_OUT_LO_TRUE (1 << 23) +#define NV_SOR_SEQ_INST_PIN_B_SHIFT (22) +#define NV_SOR_SEQ_INST_PIN_B_LOW (0 << 22) +#define NV_SOR_SEQ_INST_PIN_B_HIGH (1 << 22) +#define NV_SOR_SEQ_INST_PIN_A_SHIFT (21) +#define NV_SOR_SEQ_INST_PIN_A_LOW (0 << 21) +#define NV_SOR_SEQ_INST_PIN_A_HIGH (1 << 21) +#define NV_SOR_SEQ_INST_SEQUENCE_SHIFT (19) +#define NV_SOR_SEQ_INST_SEQUENCE_UP (0 << 19) +#define NV_SOR_SEQ_INST_SEQUENCE_DOWN (1 << 19) +#define NV_SOR_SEQ_INST_LANE_SEQ_SHIFT (18) +#define NV_SOR_SEQ_INST_LANE_SEQ_STOP (0 << 18) +#define NV_SOR_SEQ_INST_LANE_SEQ_RUN (1 << 18) +#define NV_SOR_SEQ_INST_PDPORT_SHIFT (17) +#define NV_SOR_SEQ_INST_PDPORT_NO (0 << 17) +#define NV_SOR_SEQ_INST_PDPORT_YES (1 << 17) +#define NV_SOR_SEQ_INST_PDPLL_SHIFT (16) +#define NV_SOR_SEQ_INST_PDPLL_NO (0 << 16) +#define NV_SOR_SEQ_INST_PDPLL_YES (1 << 16) +#define NV_SOR_SEQ_INST_HALT_SHIFT (15) +#define NV_SOR_SEQ_INST_HALT_FALSE (0 << 15) +#define NV_SOR_SEQ_INST_HALT_TRUE (1 << 15) +#define NV_SOR_SEQ_INST_WAIT_UNITS_SHIFT (12) +#define NV_SOR_SEQ_INST_WAIT_UNITS_DEFAULT_MASK (0x3 << 12) +#define NV_SOR_SEQ_INST_WAIT_UNITS_US (0 << 12) +#define NV_SOR_SEQ_INST_WAIT_UNITS_MS (1 << 12) +#define NV_SOR_SEQ_INST_WAIT_UNITS_VSYNC (2 << 12) +#define NV_SOR_SEQ_INST_WAIT_TIME_SHIFT (0) +#define NV_SOR_SEQ_INST_WAIT_TIME_DEFAULT_MASK (0x3ff) +#define NV_SOR_PWM_DIV (0x32) +#define NV_SOR_PWM_DIV_DIVIDE_DEFAULT_MASK (0xffffff) +#define NV_SOR_PWM_CTL (0x33) +#define NV_SOR_PWM_CTL_SETTING_NEW_SHIFT (31) +#define NV_SOR_PWM_CTL_SETTING_NEW_DONE (0 << 31) +#define NV_SOR_PWM_CTL_SETTING_NEW_PENDING (1 << 31) +#define NV_SOR_PWM_CTL_SETTING_NEW_TRIGGER (1 << 31) +#define NV_SOR_PWM_CTL_CLKSEL_SHIFT (30) +#define NV_SOR_PWM_CTL_CLKSEL_PCLK (0 << 30) +#define NV_SOR_PWM_CTL_CLKSEL_XTAL (1 << 30) +#define NV_SOR_PWM_CTL_DUTY_CYCLE_SHIFT (0) +#define NV_SOR_PWM_CTL_DUTY_CYCLE_MASK (0xffffff) +#define NV_SOR_MSCHECK (0x49) +#define NV_SOR_MSCHECK_CTL_SHIFT (31) +#define NV_SOR_MSCHECK_CTL_CLEAR (0 << 31) +#define NV_SOR_MSCHECK_CTL_RUN (1 << 31) +#define NV_SOR_XBAR_CTRL (0x4a) +#define NV_SOR_DP_LINKCTL(i) (0x4c + (i)) +#define NV_SOR_DP_LINKCTL_FORCE_IDLEPTTRN_SHIFT (31) +#define NV_SOR_DP_LINKCTL_FORCE_IDLEPTTRN_NO (0 << 31) +#define NV_SOR_DP_LINKCTL_FORCE_IDLEPTTRN_YES (1 << 31) +#define NV_SOR_DP_LINKCTL_COMPLIANCEPTTRN_SHIFT (28) +#define NV_SOR_DP_LINKCTL_COMPLIANCEPTTRN_NOPATTERN (0 << 28) +#define NV_SOR_DP_LINKCTL_COMPLIANCEPTTRN_COLORSQARE (1 << 28) +#define NV_SOR_DP_LINKCTL_LANECOUNT_SHIFT (16) +#define NV_SOR_DP_LINKCTL_LANECOUNT_MASK (0x1f << 16) +#define NV_SOR_DP_LINKCTL_LANECOUNT_ZERO (0 << 16) +#define NV_SOR_DP_LINKCTL_LANECOUNT_ONE (1 << 16) +#define NV_SOR_DP_LINKCTL_LANECOUNT_TWO (3 << 16) +#define NV_SOR_DP_LINKCTL_LANECOUNT_FOUR (15 << 16) +#define NV_SOR_DP_LINKCTL_ENHANCEDFRAME_SHIFT (14) +#define NV_SOR_DP_LINKCTL_ENHANCEDFRAME_DISABLE (0 << 14) +#define NV_SOR_DP_LINKCTL_ENHANCEDFRAME_ENABLE (1 << 14) +#define NV_SOR_DP_LINKCTL_SYNCMODE_SHIFT (10) +#define NV_SOR_DP_LINKCTL_SYNCMODE_DISABLE (0 << 10) +#define NV_SOR_DP_LINKCTL_SYNCMODE_ENABLE (1 << 10) +#define NV_SOR_DP_LINKCTL_TUSIZE_SHIFT (2) +#define NV_SOR_DP_LINKCTL_TUSIZE_MASK (0x7f << 2) +#define NV_SOR_DP_LINKCTL_ENABLE_SHIFT (0) +#define NV_SOR_DP_LINKCTL_ENABLE_NO (0) +#define NV_SOR_DP_LINKCTL_ENABLE_YES (1) +#define NV_SOR_DC(i) (0x4e + (i)) +#define NV_SOR_DC_LANE3_DP_LANE3_SHIFT (24) +#define NV_SOR_DC_LANE3_DP_LANE3_MASK (0xff << 24) +#define NV_SOR_DC_LANE3_DP_LANE3_P0_LEVEL0 (17 << 24) +#define NV_SOR_DC_LANE3_DP_LANE3_P1_LEVEL0 (21 << 24) +#define NV_SOR_DC_LANE3_DP_LANE3_P2_LEVEL0 (26 << 24) +#define NV_SOR_DC_LANE3_DP_LANE3_P3_LEVEL0 (34 << 24) +#define NV_SOR_DC_LANE3_DP_LANE3_P0_LEVEL1 (26 << 24) +#define NV_SOR_DC_LANE3_DP_LANE3_P1_LEVEL1 (32 << 24) +#define NV_SOR_DC_LANE3_DP_LANE3_P2_LEVEL1 (39 << 24) +#define NV_SOR_DC_LANE3_DP_LANE3_P0_LEVEL2 (34 << 24) +#define NV_SOR_DC_LANE3_DP_LANE3_P1_LEVEL2 (43 << 24) +#define NV_SOR_DC_LANE3_DP_LANE3_P0_LEVEL3 (51 << 24) +#define NV_SOR_DC_LANE2_DP_LANE0_SHIFT (16) +#define NV_SOR_DC_LANE2_DP_LANE0_MASK (0xff << 16) +#define NV_SOR_DC_LANE2_DP_LANE0_P0_LEVEL0 (17 << 16) +#define NV_SOR_DC_LANE2_DP_LANE0_P1_LEVEL0 (21 << 16) +#define NV_SOR_DC_LANE2_DP_LANE0_P2_LEVEL0 (26 << 16) +#define NV_SOR_DC_LANE2_DP_LANE0_P3_LEVEL0 (34 << 16) +#define NV_SOR_DC_LANE2_DP_LANE0_P0_LEVEL1 (26 << 16) +#define NV_SOR_DC_LANE2_DP_LANE0_P1_LEVEL1 (32 << 16) +#define NV_SOR_DC_LANE2_DP_LANE0_P2_LEVEL1 (39 << 16) +#define NV_SOR_DC_LANE2_DP_LANE0_P0_LEVEL2 (34 << 16) +#define NV_SOR_DC_LANE2_DP_LANE0_P1_LEVEL2 (43 << 16) +#define NV_SOR_DC_LANE2_DP_LANE0_P0_LEVEL3 (51 << 16) +#define NV_SOR_DC_LANE1_DP_LANE1_SHIFT (8) +#define NV_SOR_DC_LANE1_DP_LANE1_MASK (0xff << 8) +#define NV_SOR_DC_LANE1_DP_LANE1_P0_LEVEL0 (17 << 8) +#define NV_SOR_DC_LANE1_DP_LANE1_P1_LEVEL0 (21 << 8) +#define NV_SOR_DC_LANE1_DP_LANE1_P2_LEVEL0 (26 << 8) +#define NV_SOR_DC_LANE1_DP_LANE1_P3_LEVEL0 (34 << 8) +#define NV_SOR_DC_LANE1_DP_LANE1_P0_LEVEL1 (26 << 8) +#define NV_SOR_DC_LANE1_DP_LANE1_P1_LEVEL1 (32 << 8) +#define NV_SOR_DC_LANE1_DP_LANE1_P2_LEVEL1 (39 << 8) +#define NV_SOR_DC_LANE1_DP_LANE1_P0_LEVEL2 (34 << 8) +#define NV_SOR_DC_LANE1_DP_LANE1_P1_LEVEL2 (43 << 8) +#define NV_SOR_DC_LANE1_DP_LANE1_P0_LEVEL3 (51 << 8) +#define NV_SOR_DC_LANE0_DP_LANE2_SHIFT (0) +#define NV_SOR_DC_LANE0_DP_LANE2_MASK (0xff) +#define NV_SOR_DC_LANE0_DP_LANE2_P0_LEVEL0 (17) +#define NV_SOR_DC_LANE0_DP_LANE2_P1_LEVEL0 (21) +#define NV_SOR_DC_LANE0_DP_LANE2_P2_LEVEL0 (26) +#define NV_SOR_DC_LANE0_DP_LANE2_P3_LEVEL0 (34) +#define NV_SOR_DC_LANE0_DP_LANE2_P0_LEVEL1 (26) +#define NV_SOR_DC_LANE0_DP_LANE2_P1_LEVEL1 (32) +#define NV_SOR_DC_LANE0_DP_LANE2_P2_LEVEL1 (39) +#define NV_SOR_DC_LANE0_DP_LANE2_P0_LEVEL2 (34) +#define NV_SOR_DC_LANE0_DP_LANE2_P1_LEVEL2 (43) +#define NV_SOR_DC_LANE0_DP_LANE2_P0_LEVEL3 (51) +#define NV_SOR_LANE_DRIVE_CURRENT(i) (0x4e + (i)) +#define NV_SOR_PR(i) (0x52 + (i)) +#define NV_SOR_PR_LANE3_DP_LANE3_SHIFT (24) +#define NV_SOR_PR_LANE3_DP_LANE3_MASK (0xff << 24) +#define NV_SOR_PR_LANE3_DP_LANE3_D0_LEVEL0 (0 << 24) +#define NV_SOR_PR_LANE3_DP_LANE3_D1_LEVEL0 (0 << 24) +#define NV_SOR_PR_LANE3_DP_LANE3_D2_LEVEL0 (0 << 24) +#define NV_SOR_PR_LANE3_DP_LANE3_D3_LEVEL0 (0 << 24) +#define NV_SOR_PR_LANE3_DP_LANE3_D0_LEVEL1 (4 << 24) +#define NV_SOR_PR_LANE3_DP_LANE3_D1_LEVEL1 (6 << 24) +#define NV_SOR_PR_LANE3_DP_LANE3_D2_LEVEL1 (17 << 24) +#define NV_SOR_PR_LANE3_DP_LANE3_D0_LEVEL2 (8 << 24) +#define NV_SOR_PR_LANE3_DP_LANE3_D1_LEVEL2 (13 << 24) +#define NV_SOR_PR_LANE3_DP_LANE3_D0_LEVEL3 (17 << 24) +#define NV_SOR_PR_LANE2_DP_LANE0_SHIFT (16) +#define NV_SOR_PR_LANE2_DP_LANE0_MASK (0xff << 16) +#define NV_SOR_PR_LANE2_DP_LANE0_D0_LEVEL0 (0 << 16) +#define NV_SOR_PR_LANE2_DP_LANE0_D1_LEVEL0 (0 << 16) +#define NV_SOR_PR_LANE2_DP_LANE0_D2_LEVEL0 (0 << 16) +#define NV_SOR_PR_LANE2_DP_LANE0_D3_LEVEL0 (0 << 16) +#define NV_SOR_PR_LANE2_DP_LANE0_D0_LEVEL1 (4 << 16) +#define NV_SOR_PR_LANE2_DP_LANE0_D1_LEVEL1 (6 << 16) +#define NV_SOR_PR_LANE2_DP_LANE0_D2_LEVEL1 (17 << 16) +#define NV_SOR_PR_LANE2_DP_LANE0_D0_LEVEL2 (8 << 16) +#define NV_SOR_PR_LANE2_DP_LANE0_D1_LEVEL2 (13 << 16) +#define NV_SOR_PR_LANE2_DP_LANE0_D0_LEVEL3 (17 << 16) +#define NV_SOR_PR_LANE1_DP_LANE1_SHIFT (8) +#define NV_SOR_PR_LANE1_DP_LANE1_MASK (0xff >> 8) +#define NV_SOR_PR_LANE1_DP_LANE1_D0_LEVEL0 (0 >> 8) +#define NV_SOR_PR_LANE1_DP_LANE1_D1_LEVEL0 (0 >> 8) +#define NV_SOR_PR_LANE1_DP_LANE1_D2_LEVEL0 (0 >> 8) +#define NV_SOR_PR_LANE1_DP_LANE1_D3_LEVEL0 (0 >> 8) +#define NV_SOR_PR_LANE1_DP_LANE1_D0_LEVEL1 (4 >> 8) +#define NV_SOR_PR_LANE1_DP_LANE1_D1_LEVEL1 (6 >> 8) +#define NV_SOR_PR_LANE1_DP_LANE1_D2_LEVEL1 (17 >> 8) +#define NV_SOR_PR_LANE1_DP_LANE1_D0_LEVEL2 (8 >> 8) +#define NV_SOR_PR_LANE1_DP_LANE1_D1_LEVEL2 (13 >> 8) +#define NV_SOR_PR_LANE1_DP_LANE1_D0_LEVEL3 (17 >> 8) +#define NV_SOR_PR_LANE0_DP_LANE2_SHIFT (0) +#define NV_SOR_PR_LANE0_DP_LANE2_MASK (0xff) +#define NV_SOR_PR_LANE0_DP_LANE2_D0_LEVEL0 (0) +#define NV_SOR_PR_LANE0_DP_LANE2_D1_LEVEL0 (0) +#define NV_SOR_PR_LANE0_DP_LANE2_D2_LEVEL0 (0) +#define NV_SOR_PR_LANE0_DP_LANE2_D3_LEVEL0 (0) +#define NV_SOR_PR_LANE0_DP_LANE2_D0_LEVEL1 (4) +#define NV_SOR_PR_LANE0_DP_LANE2_D1_LEVEL1 (6) +#define NV_SOR_PR_LANE0_DP_LANE2_D2_LEVEL1 (17) +#define NV_SOR_PR_LANE0_DP_LANE2_D0_LEVEL2 (8) +#define NV_SOR_PR_LANE0_DP_LANE2_D1_LEVEL2 (13) +#define NV_SOR_PR_LANE0_DP_LANE2_D0_LEVEL3 (17) +#define NV_SOR_LANE4_PREEMPHASIS(i) (0x54 + (i)) +#define NV_SOR_POSTCURSOR(i) (0x56 + (i)) +#define NV_SOR_DP_CONFIG(i) (0x58 + (i)) +#define NV_SOR_DP_CONFIG_RD_RESET_VAL_SHIFT (31) +#define NV_SOR_DP_CONFIG_RD_RESET_VAL_POSITIVE (0 << 31) +#define NV_SOR_DP_CONFIG_RD_RESET_VAL_NEGATIVE (1 << 31) +#define NV_SOR_DP_CONFIG_IDLE_BEFORE_ATTACH_SHIFT (28) +#define NV_SOR_DP_CONFIG_IDLE_BEFORE_ATTACH_DISABLE (0 << 28) +#define NV_SOR_DP_CONFIG_IDLE_BEFORE_ATTACH_ENABLE (1 << 28) +#define NV_SOR_DP_CONFIG_ACTIVESYM_CNTL_SHIFT (26) +#define NV_SOR_DP_CONFIG_ACTIVESYM_CNTL_DISABLE (0 << 26) +#define NV_SOR_DP_CONFIG_ACTIVESYM_CNTL_ENABLE (1 << 26) +#define NV_SOR_DP_CONFIG_ACTIVESYM_POLARITY_SHIFT (24) +#define NV_SOR_DP_CONFIG_ACTIVESYM_POLARITY_NEGATIVE (0 << 24) +#define NV_SOR_DP_CONFIG_ACTIVESYM_POLARITY_POSITIVE (1 << 24) +#define NV_SOR_DP_CONFIG_ACTIVESYM_FRAC_SHIFT (16) +#define NV_SOR_DP_CONFIG_ACTIVESYM_FRAC_MASK (0xf << 16) +#define NV_SOR_DP_CONFIG_ACTIVESYM_COUNT_SHIFT (8) +#define NV_SOR_DP_CONFIG_ACTIVESYM_COUNT_MASK (0x7f << 8) +#define NV_SOR_DP_CONFIG_WATERMARK_SHIFT (0) +#define NV_SOR_DP_CONFIG_WATERMARK_MASK (0x3f) +#define NV_SOR_DP_MN(i) (0x5a + i) +#define NV_SOR_DP_MN_M_MOD_SHIFT (30) +#define NV_SOR_DP_MN_M_MOD_DEFAULT_MASK (0x3 << 30) +#define NV_SOR_DP_MN_M_MOD_NONE (0 << 30) +#define NV_SOR_DP_MN_M_MOD_INC (1 << 30) +#define NV_SOR_DP_MN_M_MOD_DEC (2 << 30) +#define NV_SOR_DP_MN_M_DELTA_SHIFT (24) +#define NV_SOR_DP_MN_M_DELTA_DEFAULT_MASK (0xf << 24) +#define NV_SOR_DP_MN_N_VAL_SHIFT (0) +#define NV_SOR_DP_MN_N_VAL_DEFAULT_MASK (0xffffff) +#define NV_SOR_DP_PADCTL(i) (0x5c + (i)) +#define NV_SOR_DP_PADCTL_SPARE_SHIFT (25) +#define NV_SOR_DP_PADCTL_SPARE_DEFAULT_MASK (0x7f << 25) +#define NV_SOR_DP_PADCTL_VCO_2X_SHIFT (24) +#define NV_SOR_DP_PADCTL_VCO_2X_DISABLE (0 << 24) +#define NV_SOR_DP_PADCTL_VCO_2X_ENABLE (1 << 24) +#define NV_SOR_DP_PADCTL_PAD_CAL_PD_SHIFT (23) +#define NV_SOR_DP_PADCTL_PAD_CAL_PD_POWERUP (0 << 23) +#define NV_SOR_DP_PADCTL_PAD_CAL_PD_POWERDOWN (1 << 23) +#define NV_SOR_DP_PADCTL_TX_PU_SHIFT (22) +#define NV_SOR_DP_PADCTL_TX_PU_DISABLE (0 << 22) +#define NV_SOR_DP_PADCTL_TX_PU_ENABLE (1 << 22) +#define NV_SOR_DP_PADCTL_REG_CTRL_SHIFT (20) +#define NV_SOR_DP_PADCTL_REG_CTRL_DEFAULT_MASK (0x3 << 20) +#define NV_SOR_DP_PADCTL_VCMMODE_SHIFT (16) +#define NV_SOR_DP_PADCTL_VCMMODE_DEFAULT_MASK (0xf << 16) +#define NV_SOR_DP_PADCTL_VCMMODE_TRISTATE (0 << 16) +#define NV_SOR_DP_PADCTL_VCMMODE_TEST_MUX (1 << 16) +#define NV_SOR_DP_PADCTL_VCMMODE_WEAK_PULLDOWN (2 << 16) +#define NV_SOR_DP_PADCTL_VCMMODE_STRONG_PULLDOWN (4 << 16) +#define NV_SOR_DP_PADCTL_TX_PU_VALUE_SHIFT (8) +#define NV_SOR_DP_PADCTL_TX_PU_VALUE_DEFAULT_MASK (0xff << 8) +#define NV_SOR_DP_PADCTL_COMODE_TXD_3_DP_TXD_3_SHIFT (7) +#define NV_SOR_DP_PADCTL_COMODE_TXD_3_DP_TXD_3_DISABLE (0 << 7) +#define NV_SOR_DP_PADCTL_COMODE_TXD_3_DP_TXD_3_ENABLE (1 << 7) +#define NV_SOR_DP_PADCTL_COMODE_TXD_2_DP_TXD_0_SHIFT (6) +#define NV_SOR_DP_PADCTL_COMODE_TXD_2_DP_TXD_0_DISABLE (0 << 6) +#define NV_SOR_DP_PADCTL_COMODE_TXD_2_DP_TXD_0_ENABLE (1 << 6) +#define NV_SOR_DP_PADCTL_COMODE_TXD_1_DP_TXD_1_SHIFT (5) +#define NV_SOR_DP_PADCTL_COMODE_TXD_1_DP_TXD_1_DISABLE (0 << 5) +#define NV_SOR_DP_PADCTL_COMODE_TXD_1_DP_TXD_1_ENABLE (1 << 5) +#define NV_SOR_DP_PADCTL_COMODE_TXD_0_DP_TXD_2_SHIFT (4) +#define NV_SOR_DP_PADCTL_COMODE_TXD_0_DP_TXD_2_DISABLE (0 << 4) +#define NV_SOR_DP_PADCTL_COMODE_TXD_0_DP_TXD_2_ENABLE (1 << 4) +#define NV_SOR_DP_PADCTL_PD_TXD_3_SHIFT (3) +#define NV_SOR_DP_PADCTL_PD_TXD_3_YES (0 << 3) +#define NV_SOR_DP_PADCTL_PD_TXD_3_NO (1 << 3) +#define NV_SOR_DP_PADCTL_PD_TXD_0_SHIFT (2) +#define NV_SOR_DP_PADCTL_PD_TXD_0_YES (0 << 2) +#define NV_SOR_DP_PADCTL_PD_TXD_0_NO (1 << 2) +#define NV_SOR_DP_PADCTL_PD_TXD_1_SHIFT (1) +#define NV_SOR_DP_PADCTL_PD_TXD_1_YES (0 << 1) +#define NV_SOR_DP_PADCTL_PD_TXD_1_NO (1 << 1) +#define NV_SOR_DP_PADCTL_PD_TXD_2_SHIFT (0) +#define NV_SOR_DP_PADCTL_PD_TXD_2_YES (0) +#define NV_SOR_DP_PADCTL_PD_TXD_2_NO (1) +#define NV_SOR_DP_DEBUG(i) (0x5e + i) +#define NV_SOR_DP_SPARE(i) (0x60 + (i)) +#define NV_SOR_DP_SPARE_REG_SHIFT (3) +#define NV_SOR_DP_SPARE_REG_DEFAULT_MASK (0x1fffffff << 3) +#define NV_SOR_DP_SPARE_SOR_CLK_SEL_SHIFT (2) +#define NV_SOR_DP_SPARE_SOR_CLK_SEL_DEFAULT_MASK (0x1 << 2) +#define NV_SOR_DP_SPARE_SOR_CLK_SEL_SAFE_SORCLK (0 << 2) +#define NV_SOR_DP_SPARE_SOR_CLK_SEL_MACRO_SORCLK (1 << 2) +#define NV_SOR_DP_SPARE_PANEL_SHIFT (1) +#define NV_SOR_DP_SPARE_PANEL_EXTERNAL (0 << 1) +#define NV_SOR_DP_SPARE_PANEL_INTERNAL (1 << 1) +#define NV_SOR_DP_SPARE_SEQ_ENABLE_SHIFT (0) +#define NV_SOR_DP_SPARE_SEQ_ENABLE_NO (0) +#define NV_SOR_DP_SPARE_SEQ_ENABLE_YES (1) +#define NV_SOR_DP_AUDIO_CTRL (0x62) +#define NV_SOR_DP_AUDIO_HBLANK_SYMBOLS (0x63) +#define NV_SOR_DP_AUDIO_HBLANK_SYMBOLS_MASK (0x1ffff) +#define NV_SOR_DP_AUDIO_HBLANK_SYMBOLS_VALUE_SHIFT (0) +#define NV_SOR_DP_AUDIO_VBLANK_SYMBOLS (0x64) +#define NV_SOR_DP_AUDIO_VBLANK_SYMBOLS_MASK (0x1ffff) +#define NV_SOR_DP_AUDIO_VBLANK_SYMBOLS_SHIFT (0) +#define NV_SOR_DP_GENERIC_INFOFRAME_HEADER (0x65) +#define NV_SOR_DP_GENERIC_INFOFRAME_SUBPACK(i) (0x66 + (i)) +#define NV_SOR_DP_TPG (0x6d) +#define NV_SOR_DP_TPG_LANE3_CHANNELCODING_SHIFT (30) +#define NV_SOR_DP_TPG_LANE3_CHANNELCODING_DISABLE (0 << 30) +#define NV_SOR_DP_TPG_LANE3_CHANNELCODING_ENABLE (1 << 30) +#define NV_SOR_DP_TPG_LANE3_SCRAMBLEREN_SHIFT (28) +#define NV_SOR_DP_TPG_LANE3_SCRAMBLEREN_ENABLE_GALIOS (1 << 28) +#define NV_SOR_DP_TPG_LANE3_SCRAMBLEREN_ENABLE_FIBONACCI (2 << 28) +#define NV_SOR_DP_TPG_LANE3_PATTERN_SHIFT (24) +#define NV_SOR_DP_TPG_LANE3_PATTERN_DEFAULT_MASK (0xf << 24) +#define NV_SOR_DP_TPG_LANE3_PATTERN_NOPATTERN (0 << 24) +#define NV_SOR_DP_TPG_LANE3_PATTERN_TRAINING1 (1 << 24) +#define NV_SOR_DP_TPG_LANE3_PATTERN_TRAINING2 (2 << 24) +#define NV_SOR_DP_TPG_LANE3_PATTERN_TRAINING3 (3 << 24) +#define NV_SOR_DP_TPG_LANE3_PATTERN_D102 (4 << 24) +#define NV_SOR_DP_TPG_LANE3_PATTERN_SBLERRRATE (5 << 24) +#define NV_SOR_DP_TPG_LANE3_PATTERN_PRBS7 (6 << 24) +#define NV_SOR_DP_TPG_LANE3_PATTERN_CSTM (7 << 24) +#define NV_SOR_DP_TPG_LANE3_PATTERN_HBR2_COMPLIANCE (8 << 24) +#define NV_SOR_DP_TPG_LANE2_CHANNELCODING_SHIFT (22) +#define NV_SOR_DP_TPG_LANE2_CHANNELCODING_DISABLE (0 << 22) +#define NV_SOR_DP_TPG_LANE2_CHANNELCODING_ENABLE (1 << 22) +#define NV_SOR_DP_TPG_LANE2_SCRAMBLEREN_SHIFT (20) +#define NV_SOR_DP_TPG_LANE2_SCRAMBLEREN_DEFAULT_MASK (0x3 << 20) +#define NV_SOR_DP_TPG_LANE2_SCRAMBLEREN_DISABLE (0 << 20) +#define NV_SOR_DP_TPG_LANE2_SCRAMBLEREN_ENABLE_GALIOS (1 << 20) +#define NV_SOR_DP_TPG_LANE2_SCRAMBLEREN_ENABLE_FIBONACCI (2 << 20) +#define NV_SOR_DP_TPG_LANE2_PATTERN_SHIFT (16) +#define NV_SOR_DP_TPG_LANE2_PATTERN_DEFAULT_MASK (0xf << 16) +#define NV_SOR_DP_TPG_LANE2_PATTERN_NOPATTERN (0 << 16) +#define NV_SOR_DP_TPG_LANE2_PATTERN_TRAINING1 (1 << 16) +#define NV_SOR_DP_TPG_LANE2_PATTERN_TRAINING2 (2 << 16) +#define NV_SOR_DP_TPG_LANE2_PATTERN_TRAINING3 (3 << 16) +#define NV_SOR_DP_TPG_LANE2_PATTERN_D102 (4 << 16) +#define NV_SOR_DP_TPG_LANE2_PATTERN_SBLERRRATE (5 << 16) +#define NV_SOR_DP_TPG_LANE2_PATTERN_PRBS7 (6 << 16) +#define NV_SOR_DP_TPG_LANE2_PATTERN_CSTM (7 << 16) +#define NV_SOR_DP_TPG_LANE2_PATTERN_HBR2_COMPLIANCE (8 << 16) +#define NV_SOR_DP_TPG_LANE1_CHANNELCODING_SHIFT (14) +#define NV_SOR_DP_TPG_LANE1_CHANNELCODING_DISABLE (0 << 14) +#define NV_SOR_DP_TPG_LANE1_CHANNELCODING_ENABLE (1 << 14) +#define NV_SOR_DP_TPG_LANE1_SCRAMBLEREN_SHIFT (12) +#define NV_SOR_DP_TPG_LANE1_SCRAMBLEREN_DEFAULT_MASK (0x3 << 12) +#define NV_SOR_DP_TPG_LANE1_SCRAMBLEREN_DISABLE (0 << 12) +#define NV_SOR_DP_TPG_LANE1_SCRAMBLEREN_ENABLE_GALIOS (1 << 12) +#define NV_SOR_DP_TPG_LANE1_SCRAMBLEREN_ENABLE_FIBONACCI (2 << 12) +#define NV_SOR_DP_TPG_LANE1_PATTERN_SHIFT (8) +#define NV_SOR_DP_TPG_LANE1_PATTERN_DEFAULT_MASK (0xf << 8) +#define NV_SOR_DP_TPG_LANE1_PATTERN_NOPATTERN (0 << 8) +#define NV_SOR_DP_TPG_LANE1_PATTERN_TRAINING1 (1 << 8) +#define NV_SOR_DP_TPG_LANE1_PATTERN_TRAINING2 (2 << 8) +#define NV_SOR_DP_TPG_LANE1_PATTERN_TRAINING3 (3 << 8) +#define NV_SOR_DP_TPG_LANE1_PATTERN_D102 (4 << 8) +#define NV_SOR_DP_TPG_LANE1_PATTERN_SBLERRRATE (5 << 8) +#define NV_SOR_DP_TPG_LANE1_PATTERN_PRBS7 (6 << 8) +#define NV_SOR_DP_TPG_LANE1_PATTERN_CSTM (7 << 8) +#define NV_SOR_DP_TPG_LANE1_PATTERN_HBR2_COMPLIANCE (8 << 8) +#define NV_SOR_DP_TPG_LANE0_CHANNELCODING_SHIFT (6) +#define NV_SOR_DP_TPG_LANE0_CHANNELCODING_DISABLE (0 << 6) +#define NV_SOR_DP_TPG_LANE0_CHANNELCODING_ENABLE (1 << 6) +#define NV_SOR_DP_TPG_LANE0_SCRAMBLEREN_SHIFT (4) +#define NV_SOR_DP_TPG_LANE0_SCRAMBLEREN_DEFAULT_MASK (0x3 << 4) +#define NV_SOR_DP_TPG_LANE0_SCRAMBLEREN_DISABLE (0 << 4) +#define NV_SOR_DP_TPG_LANE0_SCRAMBLEREN_ENABLE_GALIOS (1 << 4) +#define NV_SOR_DP_TPG_LANE0_SCRAMBLEREN_ENABLE_FIBONACCI (2 << 4) +#define NV_SOR_DP_TPG_LANE0_PATTERN_SHIFT (0) +#define NV_SOR_DP_TPG_LANE0_PATTERN_DEFAULT_MASK (0xf) +#define NV_SOR_DP_TPG_LANE0_PATTERN_NOPATTERN (0) +#define NV_SOR_DP_TPG_LANE0_PATTERN_TRAINING1 (1) +#define NV_SOR_DP_TPG_LANE0_PATTERN_TRAINING2 (2) +#define NV_SOR_DP_TPG_LANE0_PATTERN_TRAINING3 (3) +#define NV_SOR_DP_TPG_LANE0_PATTERN_D102 (4) +#define NV_SOR_DP_TPG_LANE0_PATTERN_SBLERRRATE (5) +#define NV_SOR_DP_TPG_LANE0_PATTERN_PRBS7 (6) +#define NV_SOR_DP_TPG_LANE0_PATTERN_CSTM (7) +#define NV_SOR_DP_TPG_LANE0_PATTERN_HBR2_COMPLIANCE (8) + +enum { + trainingPattern_Disabled = 0, + trainingPattern_1 = 1, + trainingPattern_2 = 2, + trainingPattern_3 = 3, + trainingPattern_None = 0xff +}; + +enum tegra_dc_sor_protocol { + SOR_DP, + SOR_LVDS, +}; + +#define NV_SOR_LINK_SPEED_G1_62 6 +#define NV_SOR_LINK_SPEED_G2_7 10 +#define NV_SOR_LINK_SPEED_G5_4 20 +#define NV_SOR_LINK_SPEED_LVDS 7 + +/* todo: combine this and the intel_dp struct into one struct. */ +struct tegra_dc_dp_link_config { + int is_valid; + + /* Supported configuration */ + u8 max_link_bw; + u8 max_lane_count; + int downspread; + int support_enhanced_framing; + u32 bits_per_pixel; + int alt_scramber_reset_cap; /* true for eDP */ + int only_enhanced_framing; /* enhanced_frame_en ignored */ + + /* Actual configuration */ + u8 link_bw; + u8 lane_count; + int enhanced_framing; + int scramble_ena; + + u32 activepolarity; + u32 active_count; + u32 tu_size; + u32 active_frac; + u32 watermark; + + s32 hblank_sym; + s32 vblank_sym; + + /* Training data */ + u32 drive_current; + u32 preemphasis; + u32 postcursor; +}; + +/* TODO: just pull these up into one struct? Need to see how this impacts + * having two channels. + */ +struct tegra_dc_sor_data { + struct tegra_dc *dc; + void *base; + u8 portnum; /* 0 or 1 */ + const struct tegra_dc_dp_link_config *link_cfg; + + int power_is_up; +}; + +#define TEGRA_SOR_TIMEOUT_MS 1000 +#define TEGRA_SOR_ATTACH_TIMEOUT_MS 100000 + +void tegra_dc_sor_set_dp_linkctl(struct tegra_dc_sor_data *sor, + int ena, + u8 training_pattern, + const struct tegra_dc_dp_link_config *cfg); +void tegra_dc_sor_set_dp_lanedata(struct tegra_dc_sor_data *sor, + u32 lane, u32 pre_emphasis, + u32 drive_current, u32 tx_pu); + + +#endif /*__TEGRA124_SOR_H__ */ diff --git a/src/soc/nvidia/tegra124/spi.c b/src/soc/nvidia/tegra124/spi.c index f7e0750..45fbf62 100644 --- a/src/soc/nvidia/tegra124/spi.c +++ b/src/soc/nvidia/tegra124/spi.c @@ -26,6 +26,7 @@ #include <stdint.h> #include <stdlib.h> #include <string.h> +#include <arch/cache.h> #include <arch/io.h> #include <console/console.h> #include <soc/addressmap.h> @@ -46,8 +47,7 @@ */ #define SPI_PACKET_SIZE_BYTES 1 #define SPI_MAX_TRANSFER_BYTES_FIFO (64 * SPI_PACKET_SIZE_BYTES) -#define SPI_MAX_TRANSFER_BYTES_DMA ((65536 * SPI_PACKET_SIZE_BYTES) - \ - TEGRA_DMA_ALIGN_BYTES) +#define SPI_MAX_TRANSFER_BYTES_DMA (65535 * SPI_PACKET_SIZE_BYTES) /* COMMAND1 */ #define SPI_CMD1_GO (1 << 31) @@ -114,32 +114,9 @@ #define SPI_DMA_CTL_TX_TRIG_SHIFT 15 /* SPI_DMA_BLK */ -#define SPI_DMA_CTL_BLOCK_SIZE_MASK 0xff +#define SPI_DMA_CTL_BLOCK_SIZE_MASK 0xffff #define SPI_DMA_CTL_BLOCK_SIZE_SHIFT 0 -struct tegra_spi_regs { - u32 command1; /* 0x000: SPI_COMMAND1 */ - u32 command2; /* 0x004: SPI_COMMAND2 */ - u32 timing1; /* 0x008: SPI_CS_TIM1 */ - u32 timing2; /* 0x00c: SPI_CS_TIM2 */ - u32 trans_status; /* 0x010: SPI_TRANS_STATUS */ - u32 fifo_status; /* 0x014: SPI_FIFO_STATUS */ - u32 tx_data; /* 0x018: SPI_TX_DATA */ - u32 rx_data; /* 0x01c: SPI_RX_DATA */ - u32 dma_ctl; /* 0x020: SPI_DMA_CTL */ - u32 dma_blk; /* 0x024: SPI_DMA_BLK */ - u32 rsvd[56]; /* 0x028-0x107: reserved */ - u32 tx_fifo; /* 0x108: SPI_FIFO1 */ - u32 rsvd2[31]; /* 0x10c-0x187 reserved */ - u32 rx_fifo; /* 0x188: SPI_FIFO2 */ - u32 spare_ctl; /* 0x18c: SPI_SPARE_CTRL */ -} __attribute__((packed)); - -struct tegra_spi_channel { - struct spi_slave slave; - struct tegra_spi_regs *regs; -}; - static struct tegra_spi_channel tegra_spi_channels[] = { /* * Note: Tegra pinmux must be setup for corresponding SPI channel in @@ -175,40 +152,35 @@ static struct tegra_spi_channel tegra_spi_channels[] = { }, }; -static void flush_fifos(struct tegra_spi_regs *regs) -{ - setbits_le32(&regs->fifo_status, SPI_FIFO_STATUS_RX_FIFO_FLUSH | - SPI_FIFO_STATUS_TX_FIFO_FLUSH); - while (read32(&regs->fifo_status) & - (SPI_FIFO_STATUS_RX_FIFO_FLUSH | SPI_FIFO_STATUS_TX_FIFO_FLUSH)) - ; -} +enum spi_direction { + SPI_SEND, + SPI_RECEIVE, +}; -void tegra_spi_init(unsigned int bus) +struct tegra_spi_channel *tegra_spi_init(unsigned int bus) { int i; + struct tegra_spi_channel *spi = NULL; for (i = 0; i < ARRAY_SIZE(tegra_spi_channels); i++) { - struct tegra_spi_regs *regs; - - if (tegra_spi_channels[i].slave.bus == bus) - regs = tegra_spi_channels[i].regs; - else - continue; - - /* software drives chip-select, set value to high */ - setbits_le32(&regs->command1, - SPI_CMD1_CS_SW_HW | SPI_CMD1_CS_SW_VAL); + if (tegra_spi_channels[i].slave.bus == bus) { + spi = &tegra_spi_channels[i]; + break; + } + } + if (!spi) + return NULL; - /* 8-bit transfers, unpacked mode, most significant bit first */ - clrbits_le32(&regs->command1, - SPI_CMD1_BIT_LEN_MASK | SPI_CMD1_PACKED); - setbits_le32(&regs->command1, 7 << SPI_CMD1_BIT_LEN_SHIFT); + /* software drives chip-select, set value to high */ + setbits_le32(&spi->regs->command1, + SPI_CMD1_CS_SW_HW | SPI_CMD1_CS_SW_VAL); - flush_fifos(regs); - } - printk(BIOS_INFO, "Tegra SPI bus %d initialized.\n", bus); + /* 8-bit transfers, unpacked mode, most significant bit first */ + clrbits_le32(&spi->regs->command1, + SPI_CMD1_BIT_LEN_MASK | SPI_CMD1_PACKED); + setbits_le32(&spi->regs->command1, 7 << SPI_CMD1_BIT_LEN_SHIFT); + return spi; } static struct tegra_spi_channel * const to_tegra_spi(int bus) { @@ -221,27 +193,6 @@ static unsigned int tegra_spi_speed(unsigned int bus) return 50000000; } -/* - * This calls udelay() with a calculated value based on the SPI speed and - * number of bytes remaining to be transferred. It assumes that if the - * calculated delay period is less than MIN_DELAY_US then it is probably - * not worth the overhead of yielding. - */ -#define MIN_DELAY_US 250 -static void tegra_spi_delay(struct tegra_spi_channel *spi, - unsigned int bytes_remaining) -{ - unsigned int ns_per_byte, delay_us; - - ns_per_byte = 1000000000 / (tegra_spi_speed(spi->slave.bus) / 8); - delay_us = (ns_per_byte * bytes_remaining) / 1000; - - if (delay_us < MIN_DELAY_US) - return; - - udelay(delay_us); -} - void spi_cs_activate(struct spi_slave *slave) { struct tegra_spi_regs *regs = to_tegra_spi(slave->bus)->regs; @@ -343,22 +294,6 @@ static void dump_dma_regs(struct apb_dma_channel *dma) read32(&dma->regs->word_transfer)); } -static void dump_regs(struct tegra_spi_channel *spi, - struct apb_dma_channel *dma) -{ - if (dma) - dump_dma_regs(dma); - if (spi) { - dump_spi_regs(spi); - dump_fifo_status(spi); - } -} - -static int fifo_error(struct tegra_spi_channel *spi) -{ - return read32(&spi->regs->fifo_status) & SPI_FIFO_STATUS_ERR ? 1 : 0; -} - static inline unsigned int spi_byte_count(struct tegra_spi_channel *spi) { /* FIXME: Make this take total packet size into account */ @@ -366,102 +301,111 @@ static inline unsigned int spi_byte_count(struct tegra_spi_channel *spi) (SPI_STATUS_BLOCK_COUNT << SPI_STATUS_BLOCK_COUNT_SHIFT); } -static int tegra_spi_fifo_receive(struct tegra_spi_channel *spi, - u8 *din, unsigned int in_bytes) +/* + * This calls udelay() with a calculated value based on the SPI speed and + * number of bytes remaining to be transferred. It assumes that if the + * calculated delay period is less than MIN_DELAY_US then it is probably + * not worth the overhead of yielding. + */ +#define MIN_DELAY_US 250 +static void spi_delay(struct tegra_spi_channel *spi, + unsigned int bytes_remaining) { - unsigned int received = 0, remaining = in_bytes; + unsigned int ns_per_byte, delay_us; - printk(BIOS_SPEW, "%s: Receiving %d bytes\n", __func__, in_bytes); - setbits_le32(&spi->regs->command1, SPI_CMD1_RX_EN); + ns_per_byte = 1000000000 / (tegra_spi_speed(spi->slave.bus) / 8); + delay_us = (ns_per_byte * bytes_remaining) / 1000; - while (remaining) { - unsigned int from_fifo, count; + if (delay_us < MIN_DELAY_US) + return; - from_fifo = MIN(in_bytes, SPI_MAX_TRANSFER_BYTES_FIFO); - remaining -= from_fifo; + udelay(delay_us); +} - /* BLOCK_SIZE in SPI_DMA_BLK register applies to both DMA and - * PIO transfers */ - write32(from_fifo - 1, &spi->regs->dma_blk); +static void tegra_spi_wait(struct tegra_spi_channel *spi) +{ + unsigned int count, dma_blk; - setbits_le32(&spi->regs->trans_status, SPI_STATUS_RDY); - setbits_le32(&spi->regs->command1, SPI_CMD1_GO); + dma_blk = 1 + (read32(&spi->regs->dma_blk) & + (SPI_DMA_CTL_BLOCK_SIZE_MASK << SPI_DMA_CTL_BLOCK_SIZE_SHIFT)); - while ((count = spi_byte_count(spi)) != from_fifo) { - tegra_spi_delay(spi, from_fifo - count); - if (fifo_error(spi)) - goto done; - } + while ((count = spi_byte_count(spi)) != dma_blk) + spi_delay(spi, dma_blk - count); +} - received += from_fifo; - while (from_fifo) { - *din = read8(&spi->regs->rx_fifo); - din++; - from_fifo--; - } - } -done: - clrbits_le32(&spi->regs->command1, SPI_CMD1_RX_EN); - if ((received != in_bytes) || fifo_error(spi)) { - printk(BIOS_ERR, "%s: ERROR: Received %u bytes, expected %u\n", - __func__, received, in_bytes); - dump_regs(spi, NULL); - return -1; - } - return in_bytes; +static int fifo_error(struct tegra_spi_channel *spi) +{ + return read32(&spi->regs->fifo_status) & SPI_FIFO_STATUS_ERR ? 1 : 0; } -static int tegra_spi_fifo_send(struct tegra_spi_channel *spi, - const u8 *dout, unsigned int out_bytes) +static int tegra_spi_pio_prepare(struct tegra_spi_channel *spi, + unsigned int bytes, enum spi_direction dir) { - unsigned int sent = 0, remaining = out_bytes; - - printk(BIOS_SPEW, "%s: Sending %d bytes\n", __func__, out_bytes); - setbits_le32(&spi->regs->command1, SPI_CMD1_TX_EN); + u8 *p = spi->out_buf; + unsigned int todo = MIN(bytes, SPI_MAX_TRANSFER_BYTES_FIFO); + u32 flush_mask, enable_mask; + + if (dir == SPI_SEND) { + flush_mask = SPI_FIFO_STATUS_TX_FIFO_FLUSH; + enable_mask = SPI_CMD1_TX_EN; + } else { + flush_mask = SPI_FIFO_STATUS_RX_FIFO_FLUSH; + enable_mask = SPI_CMD1_RX_EN; + } - while (remaining) { - unsigned int to_fifo, tmp; + setbits_le32(&spi->regs->fifo_status, flush_mask); + while (read32(&spi->regs->fifo_status) & flush_mask) + ; - to_fifo = MIN(out_bytes, SPI_MAX_TRANSFER_BYTES_FIFO); + setbits_le32(&spi->regs->command1, enable_mask); - /* BLOCK_SIZE in SPI_DMA_BLK register applies to both DMA and - * PIO transfers */ - write32(to_fifo - 1, &spi->regs->dma_blk); + /* BLOCK_SIZE in SPI_DMA_BLK register applies to both DMA and + * PIO transfers */ + write32(todo - 1, &spi->regs->dma_blk); - tmp = to_fifo; - while (tmp) { - write32(*dout, &spi->regs->tx_fifo); - dout++; - tmp--; + if (dir == SPI_SEND) { + unsigned int to_fifo = bytes; + while (to_fifo) { + write32(*p, &spi->regs->tx_fifo); + p++; + to_fifo--; } + } - setbits_le32(&spi->regs->trans_status, SPI_STATUS_RDY); - setbits_le32(&spi->regs->command1, SPI_CMD1_GO); + return todo; +} - while (!(read32(&spi->regs->fifo_status) & - SPI_FIFO_STATUS_TX_FIFO_EMPTY)) { - tegra_spi_delay(spi, to_fifo - spi_byte_count(spi)); - if (fifo_error(spi)) - goto done; - } +static void tegra_spi_pio_start(struct tegra_spi_channel *spi) +{ + setbits_le32(&spi->regs->trans_status, SPI_STATUS_RDY); + setbits_le32(&spi->regs->command1, SPI_CMD1_GO); +} + +static int tegra_spi_pio_finish(struct tegra_spi_channel *spi) +{ + u8 *p = spi->in_buf; + + clrbits_le32(&spi->regs->command1, SPI_CMD1_RX_EN | SPI_CMD1_TX_EN); - remaining -= to_fifo; - sent += to_fifo; + while (!(read32(&spi->regs->fifo_status) & + SPI_FIFO_STATUS_RX_FIFO_EMPTY)) { + *p = read8(&spi->regs->rx_fifo); + p++; } -done: - clrbits_le32(&spi->regs->command1, SPI_CMD1_TX_EN); - if ((sent != out_bytes) || fifo_error(spi)) { - printk(BIOS_ERR, "%s: ERROR: Sent %u bytes, expected " - "to send %u\n", __func__, sent, out_bytes); - dump_regs(spi, NULL); + if (fifo_error(spi)) { + printk(BIOS_ERR, "%s: ERROR:\n", __func__); + dump_spi_regs(spi); + dump_fifo_status(spi); return -1; } - return out_bytes; + + return 0; } -static void tegra2_spi_dma_setup(struct apb_dma_channel *dma) +static void setup_dma_params(struct tegra_spi_channel *spi, + struct apb_dma_channel *dma) { /* APB bus width = 8-bits, address wrap for each word */ clrbits_le32(&dma->regs->apb_seq, 0x7 << 28); @@ -473,219 +417,365 @@ static void tegra2_spi_dma_setup(struct apb_dma_channel *dma) setbits_le32(&dma->regs->csr, 1 << 27); } -/* - * Notes for DMA transmit and receive, experimentally determined (need to - * verify): - * - WCOUNT seems to be an "n-1" count, but the documentation does not - * make this clear. Without the -1 dma_byte_sta will show 1 AHB word - * (4 bytes) higher than it should and Tx overrun / Rx underrun will - * likely occur. - * - * - dma_byte_sta is always a multiple 4, so we check for - * dma_byte_sta < length - * - * - The RDY bit in SPI_TRANS_STATUS needs to be cleared manually - * (set bit to clear) between each transaction. Otherwise the next - * transaction does not start. - */ - -static int tegra_spi_dma_receive(struct tegra_spi_channel *spi, - const void *din, unsigned int in_bytes) +static int tegra_spi_dma_prepare(struct tegra_spi_channel *spi, + unsigned int bytes, enum spi_direction dir) { - struct apb_dma_channel *dma; + unsigned int todo, wcount; - dma = dma_claim(); - if (!dma) { - printk(BIOS_ERR, "%s: Unable to claim DMA channel\n", __func__); - return -1; + /* + * For DMA we need to think of things in terms of word count. + * AHB width is fixed at 32-bits. To avoid overrunning + * the in/out buffers we must align down. (Note: lowest 2-bits + * in WCOUNT register are ignored, and WCOUNT seems to count + * words starting at n-1) + * + * Example: If "bytes" is 7 and we are transferring 1-byte at a time, + * WCOUNT should be 4. The remaining 3 bytes must be transferred + * using PIO. + */ + todo = MIN(bytes, SPI_MAX_TRANSFER_BYTES_DMA - TEGRA_DMA_ALIGN_BYTES); + todo = ALIGN_DOWN(todo, TEGRA_DMA_ALIGN_BYTES); + wcount = ALIGN_DOWN(todo - TEGRA_DMA_ALIGN_BYTES, TEGRA_DMA_ALIGN_BYTES); + + if (dir == SPI_SEND) { + spi->dma_out = dma_claim(); + if (!spi->dma_out) + return -1; + + /* ensure bytes to send will be visible to DMA controller */ + dcache_clean_by_mva(spi->out_buf, bytes); + + write32((u32)&spi->regs->tx_fifo, &spi->dma_out->regs->apb_ptr); + write32((u32)spi->out_buf, &spi->dma_out->regs->ahb_ptr); + setbits_le32(&spi->dma_out->regs->csr, APBDMACHAN_CSR_DIR); + setup_dma_params(spi, spi->dma_out); + write32(wcount, &spi->dma_out->regs->wcount); + } else { + spi->dma_in = dma_claim(); + if (!spi->dma_in) + return -1; + + /* avoid data collisions */ + dcache_clean_invalidate_by_mva(spi->in_buf, bytes); + + write32((u32)&spi->regs->rx_fifo, &spi->dma_in->regs->apb_ptr); + write32((u32)spi->in_buf, &spi->dma_in->regs->ahb_ptr); + clrbits_le32(&spi->dma_in->regs->csr, APBDMACHAN_CSR_DIR); + setup_dma_params(spi, spi->dma_in); + write32(wcount, &spi->dma_in->regs->wcount); } - printk(BIOS_SPEW, "%s: Receiving %d bytes\n", __func__, in_bytes); - tegra2_spi_dma_setup(dma); - - /* set AHB & APB address pointers */ - write32((u32)din, &dma->regs->ahb_ptr); - write32((u32)&spi->regs->rx_fifo, &dma->regs->apb_ptr); + /* BLOCK_SIZE starts at n-1 */ + write32(todo - 1, &spi->regs->dma_blk); + return todo; +} - setbits_le32(&spi->regs->command1, SPI_CMD1_RX_EN); +static void tegra_spi_dma_start(struct tegra_spi_channel *spi) +{ + /* + * The RDY bit in SPI_TRANS_STATUS needs to be cleared manually + * (set bit to clear) between each transaction. Otherwise the next + * transaction does not start. + */ + setbits_le32(&spi->regs->trans_status, SPI_STATUS_RDY); - /* FIXME: calculate word count so that it corresponds to bus width */ - write32(in_bytes - 1, &dma->regs->wcount); + if (spi->dma_out) + setbits_le32(&spi->regs->command1, SPI_CMD1_TX_EN); + if (spi->dma_in) + setbits_le32(&spi->regs->command1, SPI_CMD1_RX_EN); - /* specify BLOCK_SIZE in SPI_DMA_BLK */ - write32(in_bytes - 1, &spi->regs->dma_blk); + /* + * To avoid underrun conditions, enable APB DMA before SPI DMA for + * Tx and enable SPI DMA before APB DMA before Rx. + */ + if (spi->dma_out) + dma_start(spi->dma_out); + setbits_le32(&spi->regs->dma_ctl, SPI_DMA_CTL_DMA); + if (spi->dma_in) + dma_start(spi->dma_in); - /* Set DMA direction for APB (SPI) --> AHB (DRAM) */ - clrbits_le32(&dma->regs->csr, 1 << 28); - /* write to SPI_TRANS_STATUS RDY bit to clear it */ - setbits_le32(&spi->regs->trans_status, SPI_STATUS_RDY); +} - /* set DMA bit in SPI_DMA_CTL to start */ - setbits_le32(&spi->regs->dma_ctl, SPI_DMA_CTL_DMA); +static int tegra_spi_dma_finish(struct tegra_spi_channel *spi) +{ + int ret; + unsigned int todo; - /* start APBDMA after SPI DMA so we don't read empty bytes - * from Rx FIFO */ - dma_start(dma); + todo = read32(&spi->dma_in->regs->wcount); - while (spi_byte_count(spi) != in_bytes) - tegra_spi_delay(spi, in_bytes - spi_byte_count(spi)); - clrbits_le32(&spi->regs->command1, SPI_CMD1_RX_EN); + if (spi->dma_in) { + while ((read32(&spi->dma_in->regs->dma_byte_sta) < todo) || + dma_busy(spi->dma_in)) + ; /* this shouldn't take long, no udelay */ + dma_stop(spi->dma_in); + clrbits_le32(&spi->regs->command1, SPI_CMD1_RX_EN); + } - while ((read32(&dma->regs->dma_byte_sta) < in_bytes) || dma_busy(dma)) - ; /* this shouldn't take long, no udelay */ - dma_stop(dma); - dma_release(dma); + if (spi->dma_out) { + while ((read32(&spi->dma_out->regs->dma_byte_sta) < todo) || + dma_busy(spi->dma_out)) + spi_delay(spi, todo - spi_byte_count(spi)); + clrbits_le32(&spi->regs->command1, SPI_CMD1_TX_EN); + dma_stop(spi->dma_out); + } - if ((spi_byte_count(spi) != in_bytes) || fifo_error(spi)) { - printk(BIOS_ERR, "%s: ERROR: Received %u bytes, expected %u\n", - __func__, spi_byte_count(spi), in_bytes); - dump_regs(spi, dma); - return -1; + if (fifo_error(spi)) { + printk(BIOS_ERR, "%s: ERROR:\n", __func__); + dump_dma_regs(spi->dma_out); + dump_dma_regs(spi->dma_in); + dump_spi_regs(spi); + dump_fifo_status(spi); + ret = -1; + goto done; } - return in_bytes; + ret = 0; +done: + spi->dma_in = NULL; + spi->dma_out = NULL; + return ret; } -static int tegra_spi_dma_send(struct tegra_spi_channel *spi, - const u8 *dout, unsigned int out_bytes) +/* + * xfer_setup() prepares a transfer. It does sanity checking, alignment, and + * sets transfer mode used by this channel (if not set already). + * + * A few caveats to watch out for: + * - The number of bytes which can be transferred may be smaller than the + * number of bytes the caller specifies. The number of bytes ready for + * a transfer will be returned (unless an error occurs). + * + * - Only one mode can be used for both RX and TX. The transfer mode of the + * SPI channel (spi->xfer_mode) is checked each time this function is called. + * If conflicting modes are detected, spi->xfer_mode will be set to + * XFER_MODE_NONE and an error will be returned. + * + * Returns bytes ready for transfer if successful, <0 to indicate error. + */ +static int xfer_setup(struct tegra_spi_channel *spi, void *buf, + unsigned int bytes, enum spi_direction dir) { - struct apb_dma_channel *dma; - unsigned int count; + unsigned int line_size = dcache_line_bytes(); + unsigned int align; + int ret = -1; - dma = dma_claim(); - if (!dma) { - printk(BIOS_ERR, "%s: Unable to claim DMA channel\n", __func__); - return -1; - } + if (!bytes) + return 0; - printk(BIOS_SPEW, "%s: Sending %d bytes\n", __func__, out_bytes); - tegra2_spi_dma_setup(dma); + if (dir == SPI_SEND) + spi->out_buf = buf; + else if (dir == SPI_RECEIVE) + spi->in_buf = buf; - /* set AHB & APB address pointers */ - write32((u32)dout, &dma->regs->ahb_ptr); - write32((u32)&spi->regs->tx_fifo, &dma->regs->apb_ptr); + /* + * Alignment consideratons: + * When we enable caching we'll need to clean/invalidate portions of + * memory. So we need to be careful about memory alignment. Also, DMA + * likes to operate on 4-bytes at a time on the AHB side. So for + * example, if we only want to receive 1 byte, 4 bytes will be be + * written in memory even if those extra 3 bytes are beyond the length + * we want. + * + * For now we'll use PIO to send/receive unaligned bytes. We may + * consider setting aside some space for a kind of bounce buffer to + * stay in DMA mode once we have a chance to benchmark the two + * approaches. + */ - setbits_le32(&spi->regs->command1, SPI_CMD1_TX_EN); + if (bytes < line_size) { + if (spi->xfer_mode == XFER_MODE_DMA) { + spi->xfer_mode = XFER_MODE_NONE; + ret = -1; + } else { + spi->xfer_mode = XFER_MODE_PIO; + ret = tegra_spi_pio_prepare(spi, bytes, dir); + } + goto done; + } - /* FIXME: calculate word count so that it corresponds to bus width */ - write32(out_bytes - 1, &dma->regs->wcount); + /* transfer bytes before the aligned boundary */ + align = line_size - ((uintptr_t)buf % line_size); + if ((align != 0) && (align != line_size)) { + if (spi->xfer_mode == XFER_MODE_DMA) { + spi->xfer_mode = XFER_MODE_NONE; + ret = -1; + } else { + spi->xfer_mode = XFER_MODE_PIO; + ret = tegra_spi_pio_prepare(spi, align, dir); + } + goto done; + } - /* specify BLOCK_SIZE in SPI_DMA_BLK */ - write32(out_bytes - 1, &spi->regs->dma_blk); + /* do aligned DMA transfer */ + align = (((uintptr_t)buf + bytes) % line_size); + if (bytes - align > 0) { + unsigned int dma_bytes = bytes - align; + + if (spi->xfer_mode == XFER_MODE_PIO) { + spi->xfer_mode = XFER_MODE_NONE; + ret = -1; + } else { + spi->xfer_mode = XFER_MODE_DMA; + ret = tegra_spi_dma_prepare(spi, dma_bytes, dir); + } - /* Set DMA direction for AHB (DRAM) --> APB (SPI) */ - setbits_le32(&dma->regs->csr, (1 << 28)); + goto done; + } - /* write to SPI_TRANS_STATUS RDY bit to clear it */ - setbits_le32(&spi->regs->trans_status, SPI_STATUS_RDY); + /* transfer any remaining unaligned bytes */ + if (align) { + if (spi->xfer_mode == XFER_MODE_DMA) { + spi->xfer_mode = XFER_MODE_NONE; + ret = -1; + } else { + spi->xfer_mode = XFER_MODE_PIO; + ret = tegra_spi_pio_prepare(spi, align, dir); + } + goto done; + } - dma_start(dma); - /* set DMA bit in SPI_DMA_CTL to start */ - setbits_le32(&spi->regs->dma_ctl, SPI_DMA_CTL_DMA); +done: + return ret; +} - while ((read32(&dma->regs->dma_byte_sta) < out_bytes) || dma_busy(dma)) - tegra_spi_delay(spi, out_bytes - spi_byte_count(spi)); - dma_stop(dma); +static void xfer_start(struct tegra_spi_channel *spi) +{ + if (spi->xfer_mode == XFER_MODE_DMA) + tegra_spi_dma_start(spi); + else + tegra_spi_pio_start(spi); +} - while ((count = spi_byte_count(spi)) != out_bytes) - tegra_spi_delay(spi, out_bytes - count); - clrbits_le32(&spi->regs->command1, SPI_CMD1_TX_EN); +static void xfer_wait(struct tegra_spi_channel *spi) +{ + tegra_spi_wait(spi); +} - dma_release(dma); +static int xfer_finish(struct tegra_spi_channel *spi) +{ + int ret; - if ((spi_byte_count(spi) != out_bytes) || fifo_error(spi)) { - printk(BIOS_ERR, "%s: ERROR: Sent %u bytes, expected %u\n", - __func__, spi_byte_count(spi), out_bytes); - dump_regs(spi, dma); - return -1; - } + if (spi->xfer_mode == XFER_MODE_DMA) + ret = tegra_spi_dma_finish(spi); + else + ret = tegra_spi_pio_finish(spi); - return out_bytes; + spi->xfer_mode = XFER_MODE_NONE; + return ret; } -int spi_xfer(struct spi_slave *slave, const void *dout, unsigned int bitsout, - void *din, unsigned int bitsin) +int spi_xfer(struct spi_slave *slave, const void *dout, + unsigned int bitsout, void *din, unsigned int bitsin) { unsigned int out_bytes = bitsout / 8, in_bytes = bitsin / 8; struct tegra_spi_channel *spi = to_tegra_spi(slave->bus); - int ret = 0; u8 *out_buf = (u8 *)dout; u8 *in_buf = (u8 *)din; + unsigned int todo; + int ret = 0, frame_started = 1; ASSERT(bitsout % 8 == 0 && bitsin % 8 == 0); /* tegra bus numbers start at 1 */ ASSERT(slave->bus >= 1 && slave->bus <= ARRAY_SIZE(tegra_spi_channels)); - flush_fifos(spi->regs); - - /* - * DMA operates on 4 bytes at a time, so to avoid accessing memory - * outside the specified buffers we'll only use DMA for 4-byte aligned - * transactions accesses and transfer remaining bytes manually using - * the Rx/Tx FIFOs. - */ - - while (out_bytes > 0) { - unsigned int dma_out, fifo_out; + if (spi->rx_frame_header_enable) { + memset(in_buf, ~spi->frame_header, in_bytes); + frame_started = 0; + } - dma_out = MIN(out_bytes, SPI_MAX_TRANSFER_BYTES_DMA); - fifo_out = dma_out % TEGRA_DMA_ALIGN_BYTES; - dma_out -= fifo_out; + while (out_bytes || in_bytes) { + int x = 0; - if (dma_out) { - ret = tegra_spi_dma_send(spi, out_buf, dma_out); - if (ret != dma_out) { - ret = -1; - goto spi_xfer_exit; + if (out_bytes == 0) + todo = in_bytes; + else if (in_bytes == 0) + todo = out_bytes; + else + todo = MIN(out_bytes, in_bytes); + + if (out_bytes) { + x = xfer_setup(spi, out_buf, todo, SPI_SEND); + if (x < 0) { + if (spi->xfer_mode == XFER_MODE_NONE) { + spi->xfer_mode = XFER_MODE_PIO; + continue; + } else { + ret = -1; + break; + } } - out_buf += dma_out; - out_bytes -= dma_out; } - if (fifo_out) { - ret = tegra_spi_fifo_send(spi, out_buf, fifo_out); - if (ret != fifo_out) { - ret = -1; - goto spi_xfer_exit; + if (in_bytes) { + x = xfer_setup(spi, in_buf, todo, SPI_RECEIVE); + if (x < 0) { + if (spi->xfer_mode == XFER_MODE_NONE) { + spi->xfer_mode = XFER_MODE_PIO; + continue; + } else { + ret = -1; + break; + } } - out_buf += fifo_out; - out_bytes -= fifo_out; } - } - - while (in_bytes > 0) { - unsigned int dma_in, fifo_in; - dma_in = MIN(in_bytes, SPI_MAX_TRANSFER_BYTES_DMA); - fifo_in = dma_in % TEGRA_DMA_ALIGN_BYTES; - dma_in -= fifo_in; + /* + * Note: Some devices (such as Chrome EC) are sensitive to + * delays, so be careful when adding debug prints not to + * cause timeouts between transfers. + */ + xfer_start(spi); + xfer_wait(spi); + if (xfer_finish(spi)) { + ret = -1; + break; + } - if (dma_in) { - ret = tegra_spi_dma_receive(spi, in_buf, dma_in); - if (ret != dma_in) { - ret = -1; - goto spi_xfer_exit; - } - in_buf += dma_in; - in_bytes -= dma_in; + /* + * Post-processing. For output, we only need to increment + * the buffer and decrement the counter. Same for input if + * there is no frame header to be concerned with. + * + * If a frame header is used and is found, the input buffer + * is shifted so that the header starts at offset 0, and + * in_bytes and in_buf are incremented/decremented according + * to the offset where the header was originally found. + */ + if (out_bytes) { + out_bytes -= x; + out_buf += x; } - if (fifo_in) { - ret = tegra_spi_fifo_receive(spi, in_buf, fifo_in); - if (ret != fifo_in) { - ret = -1; - goto spi_xfer_exit; + if (in_bytes) { + if (spi->rx_frame_header_enable && !frame_started) { + int i; + + for (i = 0; i < x; i++) { + if (in_buf[i] == spi->frame_header) { + frame_started = 1; + i++; /* discard frame header */ + break; + } + } + + if (frame_started) { + memmove(&in_buf[0], &in_buf[i], x - i); + in_bytes -= x - i; + in_buf += x - i; + } + } else { + in_bytes -= x; + in_buf += x; } - in_buf += fifo_in; - in_bytes -= fifo_in; } } - ret = 0; - -spi_xfer_exit: - if (ret < 0) + if (ret < 0) { + printk(BIOS_ERR, "%s: Error detected\n", __func__); + printk(BIOS_ERR, "Transaction size: %u, bytes remaining: " + "%u out / %u in\n", todo, out_bytes, in_bytes); clear_fifo_status(spi); + } return ret; } diff --git a/src/soc/nvidia/tegra124/spi.h b/src/soc/nvidia/tegra124/spi.h index 02495ab..dfe9be2 100644 --- a/src/soc/nvidia/tegra124/spi.h +++ b/src/soc/nvidia/tegra124/spi.h @@ -17,13 +17,55 @@ #ifndef __NVIDIA_TEGRA124_SPI_H__ #define __NVIDIA_TEGRA124_SPI_H__ +#include <spi-generic.h> #include <stddef.h> +#include "dma.h" + +struct tegra_spi_regs { + u32 command1; /* 0x000: SPI_COMMAND1 */ + u32 command2; /* 0x004: SPI_COMMAND2 */ + u32 timing1; /* 0x008: SPI_CS_TIM1 */ + u32 timing2; /* 0x00c: SPI_CS_TIM2 */ + u32 trans_status; /* 0x010: SPI_TRANS_STATUS */ + u32 fifo_status; /* 0x014: SPI_FIFO_STATUS */ + u32 tx_data; /* 0x018: SPI_TX_DATA */ + u32 rx_data; /* 0x01c: SPI_RX_DATA */ + u32 dma_ctl; /* 0x020: SPI_DMA_CTL */ + u32 dma_blk; /* 0x024: SPI_DMA_BLK */ + u32 rsvd[56]; /* 0x028-0x107: reserved */ + u32 tx_fifo; /* 0x108: SPI_FIFO1 */ + u32 rsvd2[31]; /* 0x10c-0x187 reserved */ + u32 rx_fifo; /* 0x188: SPI_FIFO2 */ + u32 spare_ctl; /* 0x18c: SPI_SPARE_CTRL */ +} __attribute__((packed)); + +enum spi_xfer_mode { + XFER_MODE_NONE = 0, + XFER_MODE_PIO, + XFER_MODE_DMA, +}; + +struct tegra_spi_channel { + struct spi_slave slave; + struct tegra_spi_regs *regs; + + /* stuff that is specific to the attached device */ + int rx_frame_header_enable; + u8 frame_header; + + /* context (used internally) */ + u8 *in_buf, *out_buf; + struct apb_dma_channel *dma_out, *dma_in; + enum spi_xfer_mode xfer_mode; + +}; + struct cbfs_media; int initialize_tegra_spi_cbfs_media(struct cbfs_media *media, void *buffer_address, size_t buffer_size); -void tegra_spi_init(unsigned int bus); +struct tegra_spi_channel *tegra_spi_init(unsigned int bus); #endif /* __NVIDIA_TEGRA124_SPI_H__ */ diff --git a/src/soc/nvidia/tegra124/sysctr.h b/src/soc/nvidia/tegra124/sysctr.h new file mode 100644 index 0000000..33f4e4b --- /dev/null +++ b/src/soc/nvidia/tegra124/sysctr.h @@ -0,0 +1,54 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef __SOC_NVIDIA_TEGRA124_SYSCTR_H__ +#define __SOC_NVIDIA_TEGRA124_SYSCTR_H__ + +#include <stdint.h> + +enum { + SYSCTR_CNTCR_EN = 1 << 0, + SYSCTR_CNTCR_HDBG = 1 << 1, + SYSCTR_CNTCR_FCREQ = 1 << 8 +}; + +struct sysctr_regs { + uint32_t cntcr; + uint32_t cntsr; + uint32_t cntcv0; + uint32_t cntcv1; + uint8_t _rsv0[0x10]; + uint32_t cntfid0; + uint32_t cntfid1; + uint8_t _rsv1[0xfa8]; + uint32_t counterid4; + uint32_t counterid5; + uint32_t counterid6; + uint32_t counterid7; + uint32_t counterid0; + uint32_t counterid1; + uint32_t counterid2; + uint32_t counterid3; + uint32_t counterid8; + uint32_t counterid9; + uint32_t counterid10; + uint32_t counterid11; +}; + +#endif /* __SOC_NVIDIA_TEGRA124_SYSCTR_H__ */ diff --git a/src/soc/nvidia/tegra124/usb.h b/src/soc/nvidia/tegra124/usb.h new file mode 100644 index 0000000..ec5a144 --- /dev/null +++ b/src/soc/nvidia/tegra124/usb.h @@ -0,0 +1,50 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2013, Google Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef __SOC_NVIDIA_TEGRA124_USB_H_ +#define __SOC_NVIDIA_TEGRA124_USB_H_ + +#include <console/console.h> +#include <soc/addressmap.h> +#include <soc/nvidia/tegra/usb.h> + +static inline void usb_setup_utmip1(void) +{ + struct usb_ctlr *usb = (void *)TEGRA_USBD_BASE; + usb_setup_utmip(usb); + usb_ehci_reset_and_prepare(usb, USB_PHY_UTMIP); + printk(BIOS_DEBUG, "USBD controller set up with UTMI+ PHY\n"); +} + +static inline void usb_setup_utmip2(void) +{ + struct usb_ctlr *usb = (void *)TEGRA_USB2_BASE; + usb_setup_utmip(usb); + usb_ehci_reset_and_prepare(usb, USB_PHY_UTMIP); + printk(BIOS_DEBUG, "USB2 controller set up with UTMI+ PHY\n"); +} + +static inline void usb_setup_utmip3(void) +{ + struct usb_ctlr *usb = (void *)TEGRA_USB3_BASE; + usb_setup_utmip(usb); + usb_ehci_reset_and_prepare(usb, USB_PHY_UTMIP); + printk(BIOS_DEBUG, "USB3 controller set up with UTMI+ PHY\n"); +} + +#endif /* __SOC_NVIDIA_TEGRA124_USB_H_ */

1 0

Patch set updated for coreboot: 9c94f1b tegra124/nyan: rougly stable code base
by Isaac Christensen 10 Sep '14

10 Sep '14

Isaac Christensen (isaac.christensen(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6869 -gerrit commit 9c94f1bb582efd8bf3e44a0e5d9319b51e2dcd1b Author: Gabe Black <gabeblack(a)google.com> Date: Wed Oct 9 23:45:07 2013 -0700 tegra124/nyan: rougly stable code base nyan: Clock setup. Reviewed-on: https://chromium-review.googlesource.com/172106 (cherry picked from commit 3697b6454c0aceebcf735436de90ba2441c9b7b1) tegra124: Call into the mainboard bootblock init if one exists. Reviewed-on: https://chromium-review.googlesource.com/172581 (cherry picked from commit 3a0cd48a0d1a9ce6b32ed614cd81fb81f5f82aec) nyan: Add a mainboard specific bootblock. Reviewed-on: https://chromium-review.googlesource.com/172582 (cherry picked from commit a83d065d660a26fe71ed79879c25f84a1b669f69) nyan: tegra124: Redestribute the clock code between the mainboard and soc. Reviewed-on: https://chromium-review.googlesource.com/172583 (cherry picked from commit ea703137fc37befa7d5a65afc982e298a0daca1b) nyan: Initialize the i2c pins and controllers. Reviewed-on: https://chromium-review.googlesource.com/172584 (cherry picked from commit 9c10a3074ef834688fea46c03551c2e3e54e44a8) nyan: Initialize the PMIC. Reviewed-on: https://chromium-review.googlesource.com/172585 (cherry picked from commit f6be8b0e607e05b73b5e4a84afcf04c879eee88a) tegra124: add a chip.h and use it in NYAN Reviewed-on: https://chromium-review.googlesource.com/172773 (cherry picked from commit 4dd5f1f091f2dcae5ce38203bb86c62994609f8f) tegra: Reorder GPIO register accesses to avoid glitching Reviewed-on: https://chromium-review.googlesource.com/172730 (cherry picked from commit 61bedbf0f839e19b284d21af2ad10f2ff15e17d5) tegra: Turn GPIO wrappers into macros to make them easier to write Reviewed-on: https://chromium-review.googlesource.com/172731 (cherry picked from commit 94550fdfa5a8005d2e6a313041de212ab7ac470c) tegra: Change GPIO functions to allow variable arguments Reviewed-on: https://chromium-review.googlesource.com/172916 (cherry picked from commit e95ccd984f718a04b6067ff6ad5049a2cd74466d) tegra124: Implement starting up the main CPUs. Reviewed-on: https://chromium-review.googlesource.com/172917 (cherry picked from commit 7c5169a197310e18a3df0f176c499669e3c2bda3) tegra: Simplify the I2C constants. Reviewed-on: https://chromium-review.googlesource.com/172953 (cherry picked from commit 130a07c86dfa5ba5ac4580f29db927c91f045c76) tegra124: Fix SPI base addresses Reviewed-on: https://chromium-review.googlesource.com/173322 (cherry picked from commit da808e46919ebd3b9f2377a5889f0d5f10b92357) tegra124: Scrub the clock constants. Reviewed-on: https://chromium-review.googlesource.com/172954 (cherry picked from commit 9305ff0696a6d556a97f928b8683770833a309a4) tegra124: add DMA support Reviewed-on: https://chromium-review.googlesource.com/172951 (cherry picked from commit 4d2a5a56b922ac37d2326d7b139697567aac37b8) tegra124: add basic SPI driver Reviewed-on: https://chromium-review.googlesource.com/172952 (cherry picked from commit 5f861f13c7fd2dd881f3cbd0f1b4d4a9994ce429) tegra124: Add an assembly stub which is run first on the main CPUs. Reviewed-on: https://chromium-review.googlesource.com/173541 (cherry picked from commit e142b9572a89f43fe984c4fc87e3203f380ff4de) nyan: tegra124: Set up dynamic cbmem. Reviewed-on: https://chromium-review.googlesource.com/173542 (cherry picked from commit b6e1a70103446abb5c3440f145617e6566879c6f) tegra124: Add an soc.c which sets up the chip operations and memory resource. Reviewed-on: https://chromium-review.googlesource.com/173543 (cherry picked from commit af49a5bd1f589cf053c4808510138aae26e20db4) tegra124: extend chip.h to include video settings Reviewed-on: https://chromium-review.googlesource.com/173600 (cherry picked from commit 87687633a2116f58fad7333b3b639cee9089ad29) tegra124 and nyan: fill in the devicetree a bit more, add defines Reviewed-on: https://chromium-review.googlesource.com/173684 (cherry picked from commit c107eaca3dea42be89f61690d0d6cb2181acb147) tegra124: clean-ups for SPI driver Reviewed-on: https://chromium-review.googlesource.com/173599 (cherry picked from commit 1e2f9fd442ea336bf0663c3c8ea51f771e21beb7) tegra124: add a #define for DMA alignment size Reviewed-on: https://chromium-review.googlesource.com/173638 (cherry picked from commit f9dc2a8d8016fa7db974fb6cb01c3275e26832af) tegra124: Add FIFO transmit functions to SPI driver Reviewed-on: https://chromium-review.googlesource.com/173639 (cherry picked from commit 97e61f36ad96ce2f9b12a7ef765ee73d3f4285f7) tegra124: clean-ups for DMA driver Reviewed-on: https://chromium-review.googlesource.com/173598 (cherry picked from commit 750c0a5d6942748dd21f3a3f884ad94a561e86e0) tegra124: early display and display code. Reviewed-on: https://chromium-review.googlesource.com/173622 (cherry picked from commit 651c7ab96b1f136865e4673a120de7afc1218558) tegra124: Move transfer size handling to spi_xfer() Reviewed-on: https://chromium-review.googlesource.com/173680 (cherry picked from commit 4a9b7b47b3c09d70063ea843054ffef98f554621) tegra124: strict error detection and reporting for SPI Reviewed-on: https://chromium-review.googlesource.com/173681 (cherry picked from commit c056fa954e1dab40a56faec6c50385763a2eb010) tegra124: add thread-friendly delays to SPI driver Reviewed-on: https://chromium-review.googlesource.com/173648 (cherry picked from commit c1a321c8f61942801627f895c5db74c518e2aa8e) Tegra124: Take the SPI1 controller out of reset and enable its clock. Reviewed-on: https://chromium-review.googlesource.com/173787 (cherry picked from commit c026a3fb861e157f1e17a121fc2ef70b903f36f2) tegra124: add two more clock setting values Reviewed-on: https://chromium-review.googlesource.com/173772 (cherry picked from commit 7d79d7dd9f0c1fd7127a7ba41652d809ccff7a57) nyan: Set up the ChromeOS related GPIOs and SPI bus 1 which goes to the EC. Reviewed-on: https://chromium-review.googlesource.com/173788 (cherry picked from commit ff172bfe30f75983a1e8efa2ead0a4519583d0a8) tegra124: Add some stub functions to the Tegra SPI driver. Reviewed-on: https://chromium-review.googlesource.com/173789 (cherry picked from commit 8bc527aa4afd301c046b0e844c7fa400630af0d2) tegra124: Build source files into the various stges needed by CONFIG_CHROMEOS. Reviewed-on: https://chromium-review.googlesource.com/173790 (cherry picked from commit 86a6423b668ca912295c47d8c6e3ef6c6f8c6084) nyan: Implement the code which reads GPIOs for ChromeOS. Reviewed-on: https://chromium-review.googlesource.com/173791 (cherry picked from commit 4c394dfbce762574fc79edcb6e4ac6bf346e48a3) nyan: Enable the CHROMEOS and ChromeOS EC related kconfig options. Reviewed-on: https://chromium-review.googlesource.com/173792 (cherry picked from commit 2845a4487159aa4b1dba58d977f52c449574fc8e) Tegra124: SDMMC: Take the SDMMC 3 and 4 out of reset and ungate their clocks. Reviewed-on: https://chromium-review.googlesource.com/173793 (cherry picked from commit c238b87bcd9d35afd828476d6ee88322ac5d0f88) tegra124: fix clear_fifo_status() in SPI driver Reviewed-on: https://chromium-review.googlesource.com/173738 (cherry picked from commit f415d2c0aaffc0f1a3592551a2db782d538f8f4f) ARM: Include stdint.h in cpu.h. Reviewed-on: https://chromium-review.googlesource.com/173774 (cherry picked from commit f1930faea3f14b2a2560a6c4058ef38532b6f1a6) tegra124: When setting up the main CPU, set its CPSR appropriately. Reviewed-on: https://chromium-review.googlesource.com/173775 (cherry picked from commit bc2ba9c15cfd22aeaca4f80b1d13a8b5e0178ead) tegra124: fix wrong names in clk_rst.h Reviewed-on: https://chromium-review.googlesource.com/173955 (cherry picked from commit 19dd9c85e4a3d1f77b23828bcbdd4bd8c2688b8d) tegra124: Fix up the PLLX divider table. Reviewed-on: https://chromium-review.googlesource.com/173778 (cherry picked from commit 3362cf3a7d6f5eaec879dda42323345922f6df17) tegra124: clock: Get rid of cpcon and dccon. Reviewed-on: https://chromium-review.googlesource.com/173779 (cherry picked from commit 08626ffac4a7e9ea3d4738af87e9e4cced7be2c7) Tegra124: SPI: Set and unset CS in spi_claim_bus and spi_release_bus. Reviewed-on: https://chromium-review.googlesource.com/173953 (cherry picked from commit a2df8f3a9c9c54c62d6ff37d3baff1d30ee6d355) armv7: expose dcache_line_bytes() in cache API Reviewed-on: https://chromium-review.googlesource.com/173975 (cherry picked from commit 6727f65702c7668fcb33848b4113bc3d3cc04e12) libpayload: expose dcache_line_bytes() in ARM cache API Reviewed-on: https://chromium-review.googlesource.com/174099 (cherry picked from commit 9387b02dff85b42944d95c3bccf59059c93fb4a9) armv4: add a stub for dcache_line_bytes() Reviewed-on: https://chromium-review.googlesource.com/173976 (cherry picked from commit 924f61ea895b9268c716791466637009bbac6469) tegra124: Base early UART on CLK_M to enable debugging of PLL init code Reviewed-on: https://chromium-review.googlesource.com/174339 (cherry picked from commit 8d9387432f0a0d9b257b040304238e543cced1aa) tegra124: Add additional PLLs and redesign the divisor table Reviewed-on: https://chromium-review.googlesource.com/174380 (cherry picked from commit f6a5f5c4562f1ca733505717c175be00413f2384) Squashed 49 commits for tegra124/nyan that included a lot of churn on different pieces. Change-Id: I00e8f5b74e835e01b28ca2e9c4af3709c9363d56 Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com> --- payloads/libpayload/arch/arm/cache.c | 15 +- payloads/libpayload/include/arm/arch/cache.h | 3 + src/arch/arm/armv4/cache.c | 11 + src/arch/arm/armv7/cache.c | 15 +- src/arch/arm/include/armv4/arch/cache.h | 3 + src/arch/arm/include/armv7/arch/cache.h | 3 + src/arch/arm/include/armv7/arch/cpu.h | 2 + src/mainboard/google/nyan/Kconfig | 24 + src/mainboard/google/nyan/Makefile.inc | 5 + src/mainboard/google/nyan/bootblock.c | 80 +++ src/mainboard/google/nyan/chromeos.c | 99 +++ src/mainboard/google/nyan/devicetree.cb | 48 ++ src/mainboard/google/nyan/mainboard.c | 36 +- src/mainboard/google/nyan/pmic.c | 78 +++ src/mainboard/google/nyan/pmic.h | 25 + src/mainboard/google/nyan/romstage.c | 23 + src/soc/nvidia/tegra/dc.h | 564 ++++++++++++++++ src/soc/nvidia/tegra/gpio.c | 210 +++--- src/soc/nvidia/tegra/gpio.h | 62 +- src/soc/nvidia/tegra/i2c.c | 44 +- src/soc/nvidia/tegra/i2c.h | 179 ++--- src/soc/nvidia/tegra124/Kconfig | 1 + src/soc/nvidia/tegra124/Makefile.inc | 24 + src/soc/nvidia/tegra124/bootblock.c | 46 +- src/soc/nvidia/tegra124/cbfs.c | 6 +- src/soc/nvidia/tegra124/cbmem.c | 27 + src/soc/nvidia/tegra124/chip.h | 91 +++ src/soc/nvidia/tegra124/clk_rst.h | 626 +++++++++-------- src/soc/nvidia/tegra124/clock.c | 361 +++++++++- src/soc/nvidia/tegra124/clock.h | 22 - src/soc/nvidia/tegra124/cpug.S | 56 ++ src/soc/nvidia/tegra124/cpug.h | 29 + src/soc/nvidia/tegra124/display.c | 304 +++++++++ src/soc/nvidia/tegra124/dma.c | 236 +++++++ src/soc/nvidia/tegra124/dma.h | 61 ++ src/soc/nvidia/tegra124/early_display.c | 61 ++ src/soc/nvidia/tegra124/flow.h | 49 ++ src/soc/nvidia/tegra124/gpio.h | 7 +- src/soc/nvidia/tegra124/include/soc/addressmap.h | 22 +- src/soc/nvidia/tegra124/include/soc/clock.h | 171 +++++ src/soc/nvidia/tegra124/include/soc/display.h | 22 + src/soc/nvidia/tegra124/pmc.h | 200 ++++++ src/soc/nvidia/tegra124/power.c | 87 +++ src/soc/nvidia/tegra124/power.h | 29 + src/soc/nvidia/tegra124/soc.c | 66 ++ src/soc/nvidia/tegra124/spi.c | 815 +++++++++++++++++++++++ src/soc/nvidia/tegra124/spi.h | 29 + 47 files changed, 4357 insertions(+), 620 deletions(-) diff --git a/payloads/libpayload/arch/arm/cache.c b/payloads/libpayload/arch/arm/cache.c index 3944818..4c222ea 100644 --- a/payloads/libpayload/arch/arm/cache.c +++ b/payloads/libpayload/arch/arm/cache.c @@ -195,17 +195,20 @@ void dcache_invalidate_all(void) dcache_foreach(OP_DCISW); } -static unsigned int line_bytes(void) +unsigned int dcache_line_bytes(void) { uint32_t ccsidr; - unsigned int size; + static unsigned int line_bytes = 0; + + if (line_bytes) + return line_bytes; ccsidr = read_ccsidr(); /* [2:0] - Indicates (Log2(number of words in cache line)) - 2 */ - size = 1 << ((ccsidr & 0x7) + 2); /* words per line */ - size *= sizeof(unsigned int); /* bytes per line */ + line_bytes = 1 << ((ccsidr & 0x7) + 2); /* words per line */ + line_bytes *= sizeof(unsigned int); /* bytes per line */ - return size; + return line_bytes; } /* @@ -219,7 +222,7 @@ static void dcache_op_mva(void const *vaddr, size_t len, enum dcache_op op) unsigned long line, linesize; unsigned long paddr = virt_to_phys(vaddr); - linesize = line_bytes(); + linesize = dcache_line_bytes(); line = paddr & ~(linesize - 1); dsb(); diff --git a/payloads/libpayload/include/arm/arch/cache.h b/payloads/libpayload/include/arm/arch/cache.h index ffdb55a..5210dfe 100644 --- a/payloads/libpayload/include/arm/arch/cache.h +++ b/payloads/libpayload/include/arm/arch/cache.h @@ -304,6 +304,9 @@ void dcache_clean_all(void); /* dcache invalidate all (on current level given by CCSELR) */ void dcache_invalidate_all(void); +/* returns number of bytes per cache line */ +unsigned int dcache_line_bytes(void); + /* dcache and MMU disable */ void dcache_mmu_disable(void); diff --git a/src/arch/arm/armv4/cache.c b/src/arch/arm/armv4/cache.c index 729b82c..e5cf293 100644 --- a/src/arch/arm/armv4/cache.c +++ b/src/arch/arm/armv4/cache.c @@ -55,6 +55,17 @@ void dcache_invalidate_all(void) { } +unsigned int dcache_line_bytes(void) +{ + /* + * TODO: Implement this correctly. For now we just return a + * reasonable value. It was added during Nyan development and + * may be used in bootblock code. It matters only if dcache is + * turned on. + */ + return 64; +} + void dcache_clean_by_mva(void const *addr, size_t len) { } diff --git a/src/arch/arm/armv7/cache.c b/src/arch/arm/armv7/cache.c index acd1f9a..4ee2687 100644 --- a/src/arch/arm/armv7/cache.c +++ b/src/arch/arm/armv7/cache.c @@ -194,17 +194,20 @@ void dcache_invalidate_all(void) dcache_foreach(OP_DCISW); } -static unsigned int line_bytes(void) +unsigned int dcache_line_bytes(void) { uint32_t ccsidr; - unsigned int size; + static unsigned int line_bytes = 0; + + if (line_bytes) + return line_bytes; ccsidr = read_ccsidr(); /* [2:0] - Indicates (Log2(number of words in cache line)) - 2 */ - size = 1 << ((ccsidr & 0x7) + 2); /* words per line */ - size *= sizeof(unsigned int); /* bytes per line */ + line_bytes = 1 << ((ccsidr & 0x7) + 2); /* words per line */ + line_bytes *= sizeof(unsigned int); /* bytes per line */ - return size; + return line_bytes; } /* @@ -217,7 +220,7 @@ static void dcache_op_mva(void const *addr, size_t len, enum dcache_op op) { unsigned long line, linesize; - linesize = line_bytes(); + linesize = dcache_line_bytes(); line = (uint32_t)addr & ~(linesize - 1); dsb(); diff --git a/src/arch/arm/include/armv4/arch/cache.h b/src/arch/arm/include/armv4/arch/cache.h index db4379a..6a3f593 100644 --- a/src/arch/arm/include/armv4/arch/cache.h +++ b/src/arch/arm/include/armv4/arch/cache.h @@ -57,6 +57,9 @@ void dcache_clean_all(void); /* dcache invalidate all (on current level given by CCSELR) */ void dcache_invalidate_all(void); +/* returns number of bytes per cache line */ +unsigned int dcache_line_bytes(void); + /* dcache and MMU disable */ void dcache_mmu_disable(void); diff --git a/src/arch/arm/include/armv7/arch/cache.h b/src/arch/arm/include/armv7/arch/cache.h index ffdb55a..5210dfe 100644 --- a/src/arch/arm/include/armv7/arch/cache.h +++ b/src/arch/arm/include/armv7/arch/cache.h @@ -304,6 +304,9 @@ void dcache_clean_all(void); /* dcache invalidate all (on current level given by CCSELR) */ void dcache_invalidate_all(void); +/* returns number of bytes per cache line */ +unsigned int dcache_line_bytes(void); + /* dcache and MMU disable */ void dcache_mmu_disable(void); diff --git a/src/arch/arm/include/armv7/arch/cpu.h b/src/arch/arm/include/armv7/arch/cpu.h index 52cc8a3..275bb8c 100644 --- a/src/arch/arm/include/armv7/arch/cpu.h +++ b/src/arch/arm/include/armv7/arch/cpu.h @@ -20,6 +20,8 @@ #ifndef __ARCH_CPU_H__ #define __ARCH_CPU_H__ +#include <stdint.h> + #define asmlinkage #if !defined(__PRE_RAM__) diff --git a/src/mainboard/google/nyan/Kconfig b/src/mainboard/google/nyan/Kconfig index 5ac58d3..652cef1 100644 --- a/src/mainboard/google/nyan/Kconfig +++ b/src/mainboard/google/nyan/Kconfig @@ -22,6 +22,10 @@ if BOARD_GOOGLE_NYAN config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select SOC_NVIDIA_TEGRA124 + select MAINBOARD_HAS_CHROMEOS + select EC_GOOGLE_CHROMEEC + select EC_GOOGLE_CHROMEEC_SPI + select MAINBOARD_HAS_BOOTBLOCK_INIT select BOARD_ROMSIZE_KB_1024 config MAINBOARD_DIR @@ -54,4 +58,24 @@ config BCT_CFG_EMMC endchoice +config BOOT_MEDIA_SPI_BUS + int "SPI bus with boot media ROM" + range 1 6 + depends on BCT_CFG_SPI + default 4 + help + Which SPI bus the boot media is connected to. + +config BOOT_MEDIA_SPI_CHIP_SELECT + int "Chip select for SPI boot media" + range 0 3 + depends on BCT_CFG_SPI + default 0 + help + Which chip select to use for boot media. + +config EC_GOOGLE_CHROMEEC_SPI_BUS + hex + default 1 + endif # BOARD_GOOGLE_NYAN diff --git a/src/mainboard/google/nyan/Makefile.inc b/src/mainboard/google/nyan/Makefile.inc index 3cf7dd2..49ccf39 100644 --- a/src/mainboard/google/nyan/Makefile.inc +++ b/src/mainboard/google/nyan/Makefile.inc @@ -27,6 +27,11 @@ $(obj)/generated/bct.cfg: subdirs-y += bct +bootblock-y += bootblock.c +bootblock-y += pmic.c + romstage-y += romstage.c +romstage-$(CONFIG_CHROMEOS) += chromeos.c ramstage-y += mainboard.c +ramstage-$(CONFIG_CHROMEOS) += chromeos.c diff --git a/src/mainboard/google/nyan/bootblock.c b/src/mainboard/google/nyan/bootblock.c new file mode 100644 index 0000000..49133ca --- /dev/null +++ b/src/mainboard/google/nyan/bootblock.c @@ -0,0 +1,80 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <bootblock_common.h> +#include <console/console.h> +#include <device/i2c.h> +#include <soc/clock.h> +#include <soc/nvidia/tegra/i2c.h> +#include <soc/nvidia/tegra124/pinmux.h> +#include <soc/nvidia/tegra124/spi.h> /* FIXME: move back to soc code? */ + +#include "pmic.h" + +void bootblock_mainboard_init(void) +{ + clock_config(); + + // I2C1 clock. + pinmux_set_config(PINMUX_GEN1_I2C_SCL_INDEX, + PINMUX_GEN1_I2C_SCL_FUNC_I2C1 | PINMUX_INPUT_ENABLE); + // I2C1 data. + pinmux_set_config(PINMUX_GEN1_I2C_SDA_INDEX, + PINMUX_GEN1_I2C_SDA_FUNC_I2C1 | PINMUX_INPUT_ENABLE); + // I2C2 clock. + pinmux_set_config(PINMUX_GEN2_I2C_SCL_INDEX, + PINMUX_GEN2_I2C_SCL_FUNC_I2C2 | PINMUX_INPUT_ENABLE); + // I2C2 data. + pinmux_set_config(PINMUX_GEN2_I2C_SDA_INDEX, + PINMUX_GEN2_I2C_SDA_FUNC_I2C2 | PINMUX_INPUT_ENABLE); + // I2C3 (cam) clock. + pinmux_set_config(PINMUX_CAM_I2C_SCL_INDEX, + PINMUX_CAM_I2C_SCL_FUNC_I2C3 | PINMUX_INPUT_ENABLE); + // I2C3 (cam) data. + pinmux_set_config(PINMUX_CAM_I2C_SDA_INDEX, + PINMUX_CAM_I2C_SDA_FUNC_I2C3 | PINMUX_INPUT_ENABLE); + // I2C5 (PMU) clock. + pinmux_set_config(PINMUX_PWR_I2C_SCL_INDEX, + PINMUX_PWR_I2C_SCL_FUNC_I2CPMU | PINMUX_INPUT_ENABLE); + // I2C5 (PMU) data. + pinmux_set_config(PINMUX_PWR_I2C_SDA_INDEX, + PINMUX_PWR_I2C_SDA_FUNC_I2CPMU | PINMUX_INPUT_ENABLE); + + i2c_init(0); + i2c_init(1); + i2c_init(2); + i2c_init(4); + + pmic_init(4); + + /* SPI4 data out (MOSI) */ + pinmux_set_config(PINMUX_SDMMC1_CMD_INDEX, + PINMUX_SDMMC1_CMD_FUNC_SPI4 | PINMUX_INPUT_ENABLE); + /* SPI4 data in (MISO) */ + pinmux_set_config(PINMUX_SDMMC1_DAT1_INDEX, + PINMUX_SDMMC1_DAT1_FUNC_SPI4 | PINMUX_INPUT_ENABLE); + /* SPI4 clock */ + pinmux_set_config(PINMUX_SDMMC1_DAT2_INDEX, + PINMUX_SDMMC1_DAT2_FUNC_SPI4 | PINMUX_INPUT_ENABLE); + /* SPI4 chip select 0 */ + pinmux_set_config(PINMUX_SDMMC1_DAT3_INDEX, + PINMUX_SDMMC1_DAT3_FUNC_SPI4 | PINMUX_INPUT_ENABLE); +// spi_init(); + tegra_spi_init(4); +} diff --git a/src/mainboard/google/nyan/chromeos.c b/src/mainboard/google/nyan/chromeos.c new file mode 100644 index 0000000..5b8b9c0 --- /dev/null +++ b/src/mainboard/google/nyan/chromeos.c @@ -0,0 +1,99 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <boot/coreboot_tables.h> +#include <console/console.h> +#include <ec/google/chromeec/ec.h> +#include <ec/google/chromeec/ec_commands.h> +#include <string.h> +#include <vendorcode/google/chromeos/chromeos.h> +#include <bootmode.h> +#include <soc/nvidia/tegra124/gpio.h> + +void fill_lb_gpios(struct lb_gpios *gpios) +{ + int count = 0; + + /* Write Protect: active low */ + gpios->gpios[count].port = GPIO_R1_INDEX; + gpios->gpios[count].polarity = ACTIVE_LOW; + gpios->gpios[count].value = gpio_get_in_value(GPIO_R1_INDEX); + strncpy((char *)gpios->gpios[count].name, "write protect", + GPIO_MAX_NAME_LENGTH); + count++; + + /* Recovery: active high */ + gpios->gpios[count].port = -1; + gpios->gpios[count].polarity = ACTIVE_HIGH; + gpios->gpios[count].value = get_recovery_mode_switch(); + strncpy((char *)gpios->gpios[count].name, "recovery", + GPIO_MAX_NAME_LENGTH); + count++; + + /* Lid: active high */ + gpios->gpios[count].port = GPIO_R4_INDEX; + gpios->gpios[count].polarity = ACTIVE_HIGH; + gpios->gpios[count].value = gpio_get_in_value(GPIO_R4_INDEX); + strncpy((char *)gpios->gpios[count].name, "lid", GPIO_MAX_NAME_LENGTH); + count++; + + /* Power: active low */ + gpios->gpios[count].port = GPIO_Q0_INDEX; + gpios->gpios[count].polarity = ACTIVE_LOW; + gpios->gpios[count].value = gpio_get_in_value(GPIO_Q0_INDEX); + strncpy((char *)gpios->gpios[count].name, "power", + GPIO_MAX_NAME_LENGTH); + count++; + + /* Developer: virtual GPIO active high */ + gpios->gpios[count].port = -1; + gpios->gpios[count].polarity = ACTIVE_HIGH; + gpios->gpios[count].value = get_developer_mode_switch(); + strncpy((char *)gpios->gpios[count].name, "developer", + GPIO_MAX_NAME_LENGTH); + count++; + + gpios->size = sizeof(*gpios) + (count * sizeof(struct lb_gpio)); + gpios->count = count; + + printk(BIOS_ERR, "Added %d GPIOS size %d\n", count, gpios->size); +} + +int get_developer_mode_switch(void) +{ + return gpio_get_in_value(GPIO_Q6_INDEX); +} + +int get_recovery_mode_switch(void) +{ + uint32_t ec_events; + + /* The GPIO is active low. */ + if (!gpio_get_in_value(GPIO_Q7_INDEX)) // RECMODE_GPIO + return 1; + + ec_events = google_chromeec_get_events_b(); + return !!(ec_events & + EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY)); +} + +int get_write_protect_state(void) +{ + return !gpio_get_in_value(GPIO_R1_INDEX); +} diff --git a/src/mainboard/google/nyan/devicetree.cb b/src/mainboard/google/nyan/devicetree.cb index 392a5ae..623c5a1 100644 --- a/src/mainboard/google/nyan/devicetree.cb +++ b/src/mainboard/google/nyan/devicetree.cb @@ -19,4 +19,52 @@ chip soc/nvidia/tegra124 device cpu_cluster 0 on end +# N.B. We ae not using the device tree in an effective way. +# We need to change this in future such that the on-soc +# devices are 'chips', which will allow us to go at them +# in parallel. This is even easier on the ARM SOCs since there +# are no single-access resources such as the infamous +# cf8/cfc registers found on PCs. + register "display_controller" = "TEGRA_ARM_DISPLAYA" + register "xres" = "2560" + register "yres" = "1700" + register "framebuffer_bits_per_pixel" = "24" + register "cache_policy" = "DCACHE_WRITETHROUGH" + + # With some help from the mainbaord designer + register "backlight_en_gpio" = "GPIO(H2)" + register "lvds_shutdown_gpio" = "0" + register "backlight_vdd_gpio" = "GPIO(P2)" + register "panel_vdd_gpio" = "0" + register "pwm" = "GPIO(H1)" + +# taken from u-boot; these look wrong however. + register "vdd_delay" = "400" + register "vdd_data_delay" = "4" + register "data_backlight_delay" = "203" + register "backlight_pwm_delay" = "17" + register "pwm_backlight_en_delay" = "15" + +# How to compute these: xrandr --verbose will give you this: +#Detailed mode: Clock 285.250 MHz, 272 mm x 181 mm +# 2560 2608 2640 2720 hborder 0 +# 1700 1703 1713 1749 vborder 0 +#Then you can compute your values: +#H front porch = 2608 - 2560 = 48 +#H sync = 2640 - 2608 = 32 +#H back porch = 2720 - 2640 = 80 +#V front porch = 1703 - 1700 = 3 +#V sync = 1713 - 1703 = 10 +#V back porch = 1749 - 1713 = 36 +#href_to_sync and vref_to_sync are from the vendor + + register "href_to_sync" = "11" + register "hfront_porch" = "48" + register "hsync_width" = "32" + register "hback_porch" = "80" + + register "vref_to_sync" = "1" + register "vfront_porch" = "3" + register "vsync_width" = "10" + register "vback_porch" = "36" end diff --git a/src/mainboard/google/nyan/mainboard.c b/src/mainboard/google/nyan/mainboard.c index 9e08021..c7258ff 100644 --- a/src/mainboard/google/nyan/mainboard.c +++ b/src/mainboard/google/nyan/mainboard.c @@ -19,10 +19,44 @@ #include <device/device.h> #include <boot/coreboot_tables.h> +#include <soc/nvidia/tegra124/gpio.h> + +static void setup_pinmux(void) +{ + // Write protect. + gpio_input_pullup(GPIO(R1)); + // Recovery mode. + gpio_input_pullup(GPIO(Q7)); + // Lid switch. + gpio_input_pullup(GPIO(R4)); + // Power switch. + gpio_input_pullup(GPIO(Q0)); + // Developer mode. + gpio_input_pullup(GPIO(Q6)); + // EC in RW. + gpio_input_pullup(GPIO(U4)); + + // SPI1 MOSI + pinmux_set_config(PINMUX_ULPI_CLK_INDEX, PINMUX_ULPI_CLK_FUNC_SPI1 | + PINMUX_PULL_UP | + PINMUX_INPUT_ENABLE); + // SPI1 MISO + pinmux_set_config(PINMUX_ULPI_DIR_INDEX, PINMUX_ULPI_DIR_FUNC_SPI1 | + PINMUX_PULL_UP | + PINMUX_INPUT_ENABLE); + // SPI1 SCLK + pinmux_set_config(PINMUX_ULPI_NXT_INDEX, PINMUX_ULPI_NXT_FUNC_SPI1 | + PINMUX_PULL_NONE | + PINMUX_INPUT_ENABLE); + // SPI1 CS0 + pinmux_set_config(PINMUX_ULPI_STP_INDEX, PINMUX_ULPI_STP_FUNC_SPI1 | + PINMUX_PULL_NONE | + PINMUX_INPUT_ENABLE); +} -/* this happens after cpu_init where exynos resources are set */ static void mainboard_init(device_t dev) { + setup_pinmux(); } static void mainboard_enable(device_t dev) diff --git a/src/mainboard/google/nyan/pmic.c b/src/mainboard/google/nyan/pmic.c new file mode 100644 index 0000000..ab951ea --- /dev/null +++ b/src/mainboard/google/nyan/pmic.c @@ -0,0 +1,78 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2013 Google Inc. + * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <delay.h> +#include <device/i2c.h> +#include <stdint.h> +#include <stdlib.h> + +#include "pmic.h" + +struct pmic_write +{ + uint8_t reg; // Register to write. + uint8_t val; // Value to write. +}; + +enum { + AS3722_I2C_ADDR = 0x40 +}; + +static struct pmic_write pmic_writes[] = +{ + /* Don't need to set up VDD_CORE - already done - by OTP */ + + /* First set VDD_CPU to 1.0V, then enable the VDD_CPU regulator. */ + { 0x00, 0x28 }, + + /* Don't write SDCONTROL - it's already 0x7F, i.e. all SDs enabled. */ + + /* First set VDD_GPU to 1.0V, then enable the VDD_GPU regulator. */ + { 0x06, 0x28 }, + + /* Don't write SDCONTROL - it's already 0x7F, i.e. all SDs enabled. */ + + /* First set VPP_FUSE to 1.2V, then enable the VPP_FUSE regulator. */ + { 0x12, 0x10 }, + + /* Don't write LDCONTROL - it's already 0xFF, i.e. all LDOs enabled. */ + + /* + * Bring up VDD_SDMMC via the AS3722 PMIC on the PWR I2C bus. + * First set it to bypass 3.3V straight thru, then enable the regulator + * + * NOTE: We do this early because doing it later seems to hose the CPU + * power rail/partition startup. Need to debug. + */ + { 0x16, 0x3f } + + /* Don't write LDCONTROL - it's already 0xFF, i.e. all LDOs enabled. */ +}; + +void pmic_init(unsigned bus) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(pmic_writes); i++) { + i2c_write(bus, AS3722_I2C_ADDR, pmic_writes[i].reg, 1, + &pmic_writes[i].val, 1); + udelay(10 * 1000); + } +} diff --git a/src/mainboard/google/nyan/pmic.h b/src/mainboard/google/nyan/pmic.h new file mode 100644 index 0000000..78c9f0d --- /dev/null +++ b/src/mainboard/google/nyan/pmic.h @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef __MAINBOARD_GOOGLE_NYAN_PMIC_H__ +#define __MAINBOARD_GOOGLE_NYAN_PMIC_H__ + +void pmic_init(unsigned bus); + +#endif /* __MAINBOARD_GOOGLE_NYAN_PMIC_H__ */ diff --git a/src/mainboard/google/nyan/romstage.c b/src/mainboard/google/nyan/romstage.c index c52fbd2..5a66dde 100644 --- a/src/mainboard/google/nyan/romstage.c +++ b/src/mainboard/google/nyan/romstage.c @@ -18,12 +18,35 @@ */ #include <arch/stages.h> +#include <device/device.h> #include <cbfs.h> +#include <cbmem.h> #include <console/console.h> +#include "soc/nvidia/tegra124/chip.h" +#include <soc/display.h> void main(void) { void *entry; + const struct device *soc; + const struct soc_nvidia_tegra124_config *config; + + /* for quality of the user interface, it's important to get + * the video going ASAP. Because there are long delays in some + * of the powerup steps, we do some very early setup here in + * romstage. We don't do this in the bootblock because video + * setup is finicky and subject to change; hence, we do it as + * early as we can in the RW stage, but never in the RO stage. + */ + + soc = dev_find_slot(DEVICE_PATH_CPU_CLUSTER, 0); + printk(BIOS_SPEW, "s%s: soc is %p\n", __func__, soc); + if (soc && soc->chip_info){ + config = soc->chip_info; + setup_display((struct soc_nvidia_tegra124_config *)config); + } + + cbmem_initialize_empty(); entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, "fallback/coreboot_ram"); stage_exit(entry); diff --git a/src/soc/nvidia/tegra/dc.h b/src/soc/nvidia/tegra/dc.h new file mode 100644 index 0000000..33dbe53 --- /dev/null +++ b/src/soc/nvidia/tegra/dc.h @@ -0,0 +1,564 @@ +/* + * Copyright 2013 Google Inc. + * (C) Copyright 2010 + * NVIDIA Corporation <www.nvidia.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __SOC_NVIDIA_TEGRA_DC_H +#define __SOC_NVIDIA_TEGRA_DC_H + +/* Register definitions for the Tegra display controller */ + +/* CMD register 0x000 ~ 0x43 */ +struct dc_cmd_reg { + /* Address 0x000 ~ 0x002 */ + u32 gen_incr_syncpt; /* _CMD_GENERAL_INCR_SYNCPT_0 */ + u32 gen_incr_syncpt_ctrl; /* _CMD_GENERAL_INCR_SYNCPT_CNTRL_0 */ + u32 gen_incr_syncpt_err; /* _CMD_GENERAL_INCR_SYNCPT_ERROR_0 */ + + u32 reserved0[5]; /* reserved_0[5] */ + + /* Address 0x008 ~ 0x00a */ + u32 win_a_incr_syncpt; /* _CMD_WIN_A_INCR_SYNCPT_0 */ + u32 win_a_incr_syncpt_ctrl; /* _CMD_WIN_A_INCR_SYNCPT_CNTRL_0 */ + u32 win_a_incr_syncpt_err; /* _CMD_WIN_A_INCR_SYNCPT_ERROR_0 */ + + u32 reserved1[5]; /* reserved_1[5] */ + + /* Address 0x010 ~ 0x012 */ + u32 win_b_incr_syncpt; /* _CMD_WIN_B_INCR_SYNCPT_0 */ + u32 win_b_incr_syncpt_ctrl; /* _CMD_WIN_B_INCR_SYNCPT_CNTRL_0 */ + u32 win_b_incr_syncpt_err; /* _CMD_WIN_B_INCR_SYNCPT_ERROR_0 */ + + u32 reserved2[5]; /* reserved_2[5] */ + + /* Address 0x018 ~ 0x01a */ + u32 win_c_incr_syncpt; /* _CMD_WIN_C_INCR_SYNCPT_0 */ + u32 win_c_incr_syncpt_ctrl; /* _CMD_WIN_C_INCR_SYNCPT_CNTRL_0 */ + u32 win_c_incr_syncpt_err; /* _CMD_WIN_C_INCR_SYNCPT_ERROR_0 */ + + u32 reserved3[13]; /* reserved_3[13] */ + + /* Address 0x028 */ + u32 cont_syncpt_vsync; /* _CMD_CONT_SYNCPT_VSYNC_0 */ + + u32 reserved4[7]; /* reserved_4[7] */ + + /* Address 0x030 ~ 0x033 */ + u32 ctxsw; /* _CMD_CTXSW_0 */ + u32 disp_cmd_opt0; /* _CMD_DISPLAY_COMMAND_OPTION0_0 */ + u32 disp_cmd; /* _CMD_DISPLAY_COMMAND_0 */ + u32 sig_raise; /* _CMD_SIGNAL_RAISE_0 */ + + u32 reserved5[2]; /* reserved_0[2] */ + + /* Address 0x036 ~ 0x03e */ + u32 disp_pow_ctrl; /* _CMD_DISPLAY_POWER_CONTROL_0 */ + u32 int_stat; /* _CMD_INT_STATUS_0 */ + u32 int_mask; /* _CMD_INT_MASK_0 */ + u32 int_enb; /* _CMD_INT_ENABLE_0 */ + u32 int_type; /* _CMD_INT_TYPE_0 */ + u32 int_polarity; /* _CMD_INT_POLARITY_0 */ + u32 sig_raise1; /* _CMD_SIGNAL_RAISE1_0 */ + u32 sig_raise2; /* _CMD_SIGNAL_RAISE2_0 */ + u32 sig_raise3; /* _CMD_SIGNAL_RAISE3_0 */ + + u32 reserved6; /* reserved_6 */ + + /* Address 0x040 ~ 0x043 */ + u32 state_access; /* _CMD_STATE_ACCESS_0 */ + u32 state_ctrl; /* _CMD_STATE_CONTROL_0 */ + u32 disp_win_header; /* _CMD_DISPLAY_WINDOW_HEADER_0 */ + u32 reg_act_ctrl; /* _CMD_REG_ACT_CONTROL_0 */ +}; + +enum { + PIN_REG_COUNT = 4, + PIN_OUTPUT_SEL_COUNT = 7, +}; + +/* COM register 0x300 ~ 0x329 */ +struct dc_com_reg { + /* Address 0x300 ~ 0x301 */ + u32 crc_ctrl; /* _COM_CRC_CONTROL_0 */ + u32 crc_checksum; /* _COM_CRC_CHECKSUM_0 */ + + /* _COM_PIN_OUTPUT_ENABLE0/1/2/3_0: Address 0x302 ~ 0x305 */ + u32 pin_output_enb[PIN_REG_COUNT]; + + /* _COM_PIN_OUTPUT_POLARITY0/1/2/3_0: Address 0x306 ~ 0x309 */ + u32 pin_output_polarity[PIN_REG_COUNT]; + + /* _COM_PIN_OUTPUT_DATA0/1/2/3_0: Address 0x30a ~ 0x30d */ + u32 pin_output_data[PIN_REG_COUNT]; + + /* _COM_PIN_INPUT_ENABLE0_0: Address 0x30e ~ 0x311 */ + u32 pin_input_enb[PIN_REG_COUNT]; + + /* Address 0x312 ~ 0x313 */ + u32 pin_input_data0; /* _COM_PIN_INPUT_DATA0_0 */ + u32 pin_input_data1; /* _COM_PIN_INPUT_DATA1_0 */ + + /* _COM_PIN_OUTPUT_SELECT0/1/2/3/4/5/6_0: Address 0x314 ~ 0x31a */ + u32 pin_output_sel[PIN_OUTPUT_SEL_COUNT]; + + /* Address 0x31b ~ 0x329 */ + u32 pin_misc_ctrl; /* _COM_PIN_MISC_CONTROL_0 */ + u32 pm0_ctrl; /* _COM_PM0_CONTROL_0 */ + u32 pm0_duty_cycle; /* _COM_PM0_DUTY_CYCLE_0 */ + u32 pm1_ctrl; /* _COM_PM1_CONTROL_0 */ + u32 pm1_duty_cycle; /* _COM_PM1_DUTY_CYCLE_0 */ + u32 spi_ctrl; /* _COM_SPI_CONTROL_0 */ + u32 spi_start_byte; /* _COM_SPI_START_BYTE_0 */ + u32 hspi_wr_data_ab; /* _COM_HSPI_WRITE_DATA_AB_0 */ + u32 hspi_wr_data_cd; /* _COM_HSPI_WRITE_DATA_CD */ + u32 hspi_cs_dc; /* _COM_HSPI_CS_DC_0 */ + u32 scratch_reg_a; /* _COM_SCRATCH_REGISTER_A_0 */ + u32 scratch_reg_b; /* _COM_SCRATCH_REGISTER_B_0 */ + u32 gpio_ctrl; /* _COM_GPIO_CTRL_0 */ + u32 gpio_debounce_cnt; /* _COM_GPIO_DEBOUNCE_COUNTER_0 */ + u32 crc_checksum_latched; /* _COM_CRC_CHECKSUM_LATCHED_0 */ +}; + +enum dc_disp_h_pulse_pos { + H_PULSE0_POSITION_A, + H_PULSE0_POSITION_B, + H_PULSE0_POSITION_C, + H_PULSE0_POSITION_D, + H_PULSE0_POSITION_COUNT, +}; + +struct _disp_h_pulse { + /* _DISP_H_PULSE0/1/2_CONTROL_0 */ + u32 h_pulse_ctrl; + /* _DISP_H_PULSE0/1/2_POSITION_A/B/C/D_0 */ + u32 h_pulse_pos[H_PULSE0_POSITION_COUNT]; +}; + +enum dc_disp_v_pulse_pos { + V_PULSE0_POSITION_A, + V_PULSE0_POSITION_B, + V_PULSE0_POSITION_C, + V_PULSE0_POSITION_COUNT, +}; + +struct _disp_v_pulse0 { + /* _DISP_H_PULSE0/1_CONTROL_0 */ + u32 v_pulse_ctrl; + /* _DISP_H_PULSE0/1_POSITION_A/B/C_0 */ + u32 v_pulse_pos[V_PULSE0_POSITION_COUNT]; +}; + +struct _disp_v_pulse2 { + /* _DISP_H_PULSE2/3_CONTROL_0 */ + u32 v_pulse_ctrl; + /* _DISP_H_PULSE2/3_POSITION_A_0 */ + u32 v_pulse_pos_a; +}; + +enum dc_disp_h_pulse_reg { + H_PULSE0, + H_PULSE1, + H_PULSE2, + H_PULSE_COUNT, +}; + +enum dc_disp_pp_select { + PP_SELECT_A, + PP_SELECT_B, + PP_SELECT_C, + PP_SELECT_D, + PP_SELECT_COUNT, +}; + +/* DISP register 0x400 ~ 0x4c1 */ +struct dc_disp_reg { + /* Address 0x400 ~ 0x40a */ + u32 disp_signal_opt0; /* _DISP_DISP_SIGNAL_OPTIONS0_0 */ + u32 disp_signal_opt1; /* _DISP_DISP_SIGNAL_OPTIONS1_0 */ + u32 disp_win_opt; /* _DISP_DISP_WIN_OPTIONS_0 */ + u32 mem_high_pri; /* _DISP_MEM_HIGH_PRIORITY_0 */ + u32 mem_high_pri_timer; /* _DISP_MEM_HIGH_PRIORITY_TIMER_0 */ + u32 disp_timing_opt; /* _DISP_DISP_TIMING_OPTIONS_0 */ + u32 ref_to_sync; /* _DISP_REF_TO_SYNC_0 */ + u32 sync_width; /* _DISP_SYNC_WIDTH_0 */ + u32 back_porch; /* _DISP_BACK_PORCH_0 */ + u32 disp_active; /* _DISP_DISP_ACTIVE_0 */ + u32 front_porch; /* _DISP_FRONT_PORCH_0 */ + + /* Address 0x40b ~ 0x419: _DISP_H_PULSE0/1/2_ */ + struct _disp_h_pulse h_pulse[H_PULSE_COUNT]; + + /* Address 0x41a ~ 0x421 */ + struct _disp_v_pulse0 v_pulse0; /* _DISP_V_PULSE0_ */ + struct _disp_v_pulse0 v_pulse1; /* _DISP_V_PULSE1_ */ + + /* Address 0x422 ~ 0x425 */ + struct _disp_v_pulse2 v_pulse3; /* _DISP_V_PULSE2_ */ + struct _disp_v_pulse2 v_pulse4; /* _DISP_V_PULSE3_ */ + + /* Address 0x426 ~ 0x429 */ + u32 m0_ctrl; /* _DISP_M0_CONTROL_0 */ + u32 m1_ctrl; /* _DISP_M1_CONTROL_0 */ + u32 di_ctrl; /* _DISP_DI_CONTROL_0 */ + u32 pp_ctrl; /* _DISP_PP_CONTROL_0 */ + + /* Address 0x42a ~ 0x42d: _DISP_PP_SELECT_A/B/C/D_0 */ + u32 pp_select[PP_SELECT_COUNT]; + + /* Address 0x42e ~ 0x435 */ + u32 disp_clk_ctrl; /* _DISP_DISP_CLOCK_CONTROL_0 */ + u32 disp_interface_ctrl; /* _DISP_DISP_INTERFACE_CONTROL_0 */ + u32 disp_color_ctrl; /* _DISP_DISP_COLOR_CONTROL_0 */ + u32 shift_clk_opt; /* _DISP_SHIFT_CLOCK_OPTIONS_0 */ + u32 data_enable_opt; /* _DISP_DATA_ENABLE_OPTIONS_0 */ + u32 serial_interface_opt; /* _DISP_SERIAL_INTERFACE_OPTIONS_0 */ + u32 lcd_spi_opt; /* _DISP_LCD_SPI_OPTIONS_0 */ + u32 border_color; /* _DISP_BORDER_COLOR_0 */ + + /* Address 0x436 ~ 0x439 */ + u32 color_key0_lower; /* _DISP_COLOR_KEY0_LOWER_0 */ + u32 color_key0_upper; /* _DISP_COLOR_KEY0_UPPER_0 */ + u32 color_key1_lower; /* _DISP_COLOR_KEY1_LOWER_0 */ + u32 color_key1_upper; /* _DISP_COLOR_KEY1_UPPER_0 */ + + u32 reserved0[2]; /* reserved_0[2] */ + + /* Address 0x43c ~ 0x442 */ + u32 cursor_foreground; /* _DISP_CURSOR_FOREGROUND_0 */ + u32 cursor_background; /* _DISP_CURSOR_BACKGROUND_0 */ + u32 cursor_start_addr; /* _DISP_CURSOR_START_ADDR_0 */ + u32 cursor_start_addr_ns; /* _DISP_CURSOR_START_ADDR_NS_0 */ + u32 cursor_pos; /* _DISP_CURSOR_POSITION_0 */ + u32 cursor_pos_ns; /* _DISP_CURSOR_POSITION_NS_0 */ + u32 seq_ctrl; /* _DISP_INIT_SEQ_CONTROL_0 */ + + /* Address 0x442 ~ 0x446 */ + u32 spi_init_seq_data_a; /* _DISP_SPI_INIT_SEQ_DATA_A_0 */ + u32 spi_init_seq_data_b; /* _DISP_SPI_INIT_SEQ_DATA_B_0 */ + u32 spi_init_seq_data_c; /* _DISP_SPI_INIT_SEQ_DATA_C_0 */ + u32 spi_init_seq_data_d; /* _DISP_SPI_INIT_SEQ_DATA_D_0 */ + + u32 reserved1[0x39]; /* reserved1[0x39], */ + + /* Address 0x480 ~ 0x484 */ + u32 dc_mccif_fifoctrl; /* _DISP_DC_MCCIF_FIFOCTRL_0 */ + u32 mccif_disp0a_hyst; /* _DISP_MCCIF_DISPLAY0A_HYST_0 */ + u32 mccif_disp0b_hyst; /* _DISP_MCCIF_DISPLAY0B_HYST_0 */ + u32 mccif_disp0c_hyst; /* _DISP_MCCIF_DISPLAY0C_HYST_0 */ + u32 mccif_disp1b_hyst; /* _DISP_MCCIF_DISPLAY1B_HYST_0 */ + + u32 reserved2[0x3b]; /* reserved2[0x3b] */ + + /* Address 0x4c0 ~ 0x4c1 */ + u32 dac_crt_ctrl; /* _DISP_DAC_CRT_CTRL_0 */ + u32 disp_misc_ctrl; /* _DISP_DISP_MISC_CONTROL_0 */ +}; + +enum dc_winc_filter_p { + WINC_FILTER_COUNT = 0x10, +}; + +/* Window A/B/C register 0x500 ~ 0x628 */ +struct dc_winc_reg { + + /* Address 0x500 */ + u32 color_palette; /* _WINC_COLOR_PALETTE_0 */ + + u32 reserved0[0xff]; /* reserved_0[0xff] */ + + /* Address 0x600 */ + u32 palette_color_ext; /* _WINC_PALETTE_COLOR_EXT_0 */ + + /* _WINC_H_FILTER_P00~0F_0 */ + /* Address 0x601 ~ 0x610 */ + u32 h_filter_p[WINC_FILTER_COUNT]; + + /* Address 0x611 ~ 0x618 */ + u32 csc_yof; /* _WINC_CSC_YOF_0 */ + u32 csc_kyrgb; /* _WINC_CSC_KYRGB_0 */ + u32 csc_kur; /* _WINC_CSC_KUR_0 */ + u32 csc_kvr; /* _WINC_CSC_KVR_0 */ + u32 csc_kug; /* _WINC_CSC_KUG_0 */ + u32 csc_kvg; /* _WINC_CSC_KVG_0 */ + u32 csc_kub; /* _WINC_CSC_KUB_0 */ + u32 csc_kvb; /* _WINC_CSC_KVB_0 */ + + /* Address 0x619 ~ 0x628: _WINC_V_FILTER_P00~0F_0 */ + u32 v_filter_p[WINC_FILTER_COUNT]; +}; + +/* WIN A/B/C Register 0x700 ~ 0x714*/ +struct dc_win_reg { + /* Address 0x700 ~ 0x714 */ + u32 win_opt; /* _WIN_WIN_OPTIONS_0 */ + u32 byte_swap; /* _WIN_BYTE_SWAP_0 */ + u32 buffer_ctrl; /* _WIN_BUFFER_CONTROL_0 */ + u32 color_depth; /* _WIN_COLOR_DEPTH_0 */ + u32 pos; /* _WIN_POSITION_0 */ + u32 size; /* _WIN_SIZE_0 */ + u32 prescaled_size; /* _WIN_PRESCALED_SIZE_0 */ + u32 h_initial_dda; /* _WIN_H_INITIAL_DDA_0 */ + u32 v_initial_dda; /* _WIN_V_INITIAL_DDA_0 */ + u32 dda_increment; /* _WIN_DDA_INCREMENT_0 */ + u32 line_stride; /* _WIN_LINE_STRIDE_0 */ + u32 buf_stride; /* _WIN_BUF_STRIDE_0 */ + u32 uv_buf_stride; /* _WIN_UV_BUF_STRIDE_0 */ + u32 buffer_addr_mode; /* _WIN_BUFFER_ADDR_MODE_0 */ + u32 dv_ctrl; /* _WIN_DV_CONTROL_0 */ + u32 blend_nokey; /* _WIN_BLEND_NOKEY_0 */ + u32 blend_1win; /* _WIN_BLEND_1WIN_0 */ + u32 blend_2win_x; /* _WIN_BLEND_2WIN_X_0 */ + u32 blend_2win_y; /* _WIN_BLEND_2WIN_Y_0 */ + u32 blend_3win_xy; /* _WIN_BLEND_3WIN_XY_0 */ + u32 hp_fetch_ctrl; /* _WIN_HP_FETCH_CONTROL_0 */ +}; + +/* WINBUF A/B/C Register 0x800 ~ 0x80a */ +struct dc_winbuf_reg { + /* Address 0x800 ~ 0x80a */ + u32 start_addr; /* _WINBUF_START_ADDR_0 */ + u32 start_addr_ns; /* _WINBUF_START_ADDR_NS_0 */ + u32 start_addr_u; /* _WINBUF_START_ADDR_U_0 */ + u32 start_addr_u_ns; /* _WINBUF_START_ADDR_U_NS_0 */ + u32 start_addr_v; /* _WINBUF_START_ADDR_V_0 */ + u32 start_addr_v_ns; /* _WINBUF_START_ADDR_V_NS_0 */ + u32 addr_h_offset; /* _WINBUF_ADDR_H_OFFSET_0 */ + u32 addr_h_offset_ns; /* _WINBUF_ADDR_H_OFFSET_NS_0 */ + u32 addr_v_offset; /* _WINBUF_ADDR_V_OFFSET_0 */ + u32 addr_v_offset_ns; /* _WINBUF_ADDR_V_OFFSET_NS_0 */ + u32 uflow_status; /* _WINBUF_UFLOW_STATUS_0 */ +}; + +/* Display Controller (DC_) regs */ +struct display_controller { + struct dc_cmd_reg cmd; /* CMD register 0x000 ~ 0x43 */ + u32 reserved0[0x2bc]; + + struct dc_com_reg com; /* COM register 0x300 ~ 0x329 */ + u32 reserved1[0xd6]; + + struct dc_disp_reg disp; /* DISP register 0x400 ~ 0x4c1 */ + u32 reserved2[0x3e]; + + struct dc_winc_reg winc; /* Window A/B/C 0x500 ~ 0x628 */ + u32 reserved3[0xd7]; + + struct dc_win_reg win; /* WIN A/B/C 0x700 ~ 0x714*/ + u32 reserved4[0xeb]; + + struct dc_winbuf_reg winbuf; /* WINBUF A/B/C 0x800 ~ 0x80a */ +}; + +#define BIT(pos) (1U << pos) + +/* DC_CMD_DISPLAY_COMMAND 0x032 */ +#define CTRL_MODE_SHIFT 5 +#define CTRL_MODE_MASK (0x3 << CTRL_MODE_SHIFT) +enum { + CTRL_MODE_STOP, + CTRL_MODE_C_DISPLAY, + CTRL_MODE_NC_DISPLAY, +}; + +/* _WIN_COLOR_DEPTH_0 */ +enum win_color_depth_id { + COLOR_DEPTH_P1, + COLOR_DEPTH_P2, + COLOR_DEPTH_P4, + COLOR_DEPTH_P8, + COLOR_DEPTH_B4G4R4A4, + COLOR_DEPTH_B5G5R5A, + COLOR_DEPTH_B5G6R5, + COLOR_DEPTH_AB5G5R5, + COLOR_DEPTH_B8G8R8A8 = 12, + COLOR_DEPTH_R8G8B8A8, + COLOR_DEPTH_B6x2G6x2R6x2A8, + COLOR_DEPTH_R6x2G6x2B6x2A8, + COLOR_DEPTH_YCbCr422, + COLOR_DEPTH_YUV422, + COLOR_DEPTH_YCbCr420P, + COLOR_DEPTH_YUV420P, + COLOR_DEPTH_YCbCr422P, + COLOR_DEPTH_YUV422P, + COLOR_DEPTH_YCbCr422R, + COLOR_DEPTH_YUV422R, + COLOR_DEPTH_YCbCr422RA, + COLOR_DEPTH_YUV422RA, +}; + +/* DC_CMD_DISPLAY_POWER_CONTROL 0x036 */ +#define PW0_ENABLE BIT(0) +#define PW1_ENABLE BIT(2) +#define PW2_ENABLE BIT(4) +#define PW3_ENABLE BIT(6) +#define PW4_ENABLE BIT(8) +#define PM0_ENABLE BIT(16) +#define PM1_ENABLE BIT(18) +#define SPI_ENABLE BIT(24) +#define HSPI_ENABLE BIT(25) + +/* DC_CMD_STATE_CONTROL 0x041 */ +#define GENERAL_ACT_REQ BIT(0) +#define WIN_A_ACT_REQ BIT(1) +#define WIN_B_ACT_REQ BIT(2) +#define WIN_C_ACT_REQ BIT(3) +#define GENERAL_UPDATE BIT(8) +#define WIN_A_UPDATE BIT(9) +#define WIN_B_UPDATE BIT(10) +#define WIN_C_UPDATE BIT(11) + +/* DC_CMD_DISPLAY_WINDOW_HEADER 0x042 */ +#define WINDOW_A_SELECT BIT(4) +#define WINDOW_B_SELECT BIT(5) +#define WINDOW_C_SELECT BIT(6) + +/* DC_DISP_DISP_CLOCK_CONTROL 0x42e */ +#define SHIFT_CLK_DIVIDER_SHIFT 0 +#define SHIFT_CLK_DIVIDER_MASK (0xff << SHIFT_CLK_DIVIDER_SHIFT) +#define PIXEL_CLK_DIVIDER_SHIFT 8 +#define PIXEL_CLK_DIVIDER_MSK (0xf << PIXEL_CLK_DIVIDER_SHIFT) +enum { + PIXEL_CLK_DIVIDER_PCD1, + PIXEL_CLK_DIVIDER_PCD1H, + PIXEL_CLK_DIVIDER_PCD2, + PIXEL_CLK_DIVIDER_PCD3, + PIXEL_CLK_DIVIDER_PCD4, + PIXEL_CLK_DIVIDER_PCD6, + PIXEL_CLK_DIVIDER_PCD8, + PIXEL_CLK_DIVIDER_PCD9, + PIXEL_CLK_DIVIDER_PCD12, + PIXEL_CLK_DIVIDER_PCD16, + PIXEL_CLK_DIVIDER_PCD18, + PIXEL_CLK_DIVIDER_PCD24, + PIXEL_CLK_DIVIDER_PCD13, +}; + +/* DC_DISP_DISP_INTERFACE_CONTROL 0x42f */ +#define DATA_FORMAT_SHIFT 0 +#define DATA_FORMAT_MASK (0xf << DATA_FORMAT_SHIFT) +enum { + DATA_FORMAT_DF1P1C, + DATA_FORMAT_DF1P2C24B, + DATA_FORMAT_DF1P2C18B, + DATA_FORMAT_DF1P2C16B, + DATA_FORMAT_DF2S, + DATA_FORMAT_DF3S, + DATA_FORMAT_DFSPI, + DATA_FORMAT_DF1P3C24B, + DATA_FORMAT_DF1P3C18B, +}; +#define DATA_ALIGNMENT_SHIFT 8 +enum { + DATA_ALIGNMENT_MSB, + DATA_ALIGNMENT_LSB, +}; +#define DATA_ORDER_SHIFT 9 +enum { + DATA_ORDER_RED_BLUE, + DATA_ORDER_BLUE_RED, +}; + +/* DC_DISP_DATA_ENABLE_OPTIONS 0x432 */ +#define DE_SELECT_SHIFT 0 +#define DE_SELECT_MASK (0x3 << DE_SELECT_SHIFT) +#define DE_SELECT_ACTIVE_BLANK 0x0 +#define DE_SELECT_ACTIVE 0x1 +#define DE_SELECT_ACTIVE_IS 0x2 +#define DE_CONTROL_SHIFT 2 +#define DE_CONTROL_MASK (0x7 << DE_CONTROL_SHIFT) +enum { + DE_CONTROL_ONECLK, + DE_CONTROL_NORMAL, + DE_CONTROL_EARLY_EXT, + DE_CONTROL_EARLY, + DE_CONTROL_ACTIVE_BLANK, +}; + +/* DC_WIN_WIN_OPTIONS 0x700 */ +#define H_DIRECTION BIT(0) +enum { + H_DIRECTION_INCREMENT, + H_DIRECTION_DECREMENT, +}; +#define V_DIRECTION BIT(2) +enum { + V_DIRECTION_INCREMENT, + V_DIRECTION_DECREMENT, +}; +#define COLOR_EXPAND BIT(6) +#define CP_ENABLE BIT(16) +#define DV_ENABLE BIT(20) +#define WIN_ENABLE BIT(30) + +/* DC_WIN_BYTE_SWAP 0x701 */ +#define BYTE_SWAP_SHIFT 0 +#define BYTE_SWAP_MASK (3 << BYTE_SWAP_SHIFT) +enum { + BYTE_SWAP_NOSWAP, + BYTE_SWAP_SWAP2, + BYTE_SWAP_SWAP4, + BYTE_SWAP_SWAP4HW +}; + +/* DC_WIN_POSITION 0x704 */ +#define H_POSITION_SHIFT 0 +#define H_POSITION_MASK (0x1FFF << H_POSITION_SHIFT) +#define V_POSITION_SHIFT 16 +#define V_POSITION_MASK (0x1FFF << V_POSITION_SHIFT) + +/* DC_WIN_SIZE 0x705 */ +#define H_SIZE_SHIFT 0 +#define H_SIZE_MASK (0x1FFF << H_SIZE_SHIFT) +#define V_SIZE_SHIFT 16 +#define V_SIZE_MASK (0x1FFF << V_SIZE_SHIFT) + +/* DC_WIN_PRESCALED_SIZE 0x706 */ +#define H_PRESCALED_SIZE_SHIFT 0 +#define H_PRESCALED_SIZE_MASK (0x7FFF << H_PRESCALED_SIZE) +#define V_PRESCALED_SIZE_SHIFT 16 +#define V_PRESCALED_SIZE_MASK (0x1FFF << V_PRESCALED_SIZE) + +/* DC_WIN_DDA_INCREMENT 0x709 */ +#define H_DDA_INC_SHIFT 0 +#define H_DDA_INC_MASK (0xFFFF << H_DDA_INC_SHIFT) +#define V_DDA_INC_SHIFT 16 +#define V_DDA_INC_MASK (0xFFFF << V_DDA_INC_SHIFT) + +/* This holds information about a window which can be displayed */ +/* TODO: do we really need this for basic setup? Not sure yet. */ +struct disp_ctl_win { + enum win_color_depth_id fmt; /* Color depth/format */ + u32 bpp; /* Bits per pixel */ + u32 phys_addr; /* Physical address in memory */ + u32 x; /* Horizontal address offset (bytes) */ + u32 y; /* Veritical address offset (bytes) */ + u32 w; /* Width of source window */ + u32 h; /* Height of source window */ + u32 stride; /* Number of bytes per line */ + u32 out_x; /* Left edge of output window (col) */ + u32 out_y; /* Top edge of output window (row) */ + u32 out_w; /* Width of output window in pixels */ + u32 out_h; /* Height of output window in pixels */ +}; + +void display_startup(device_t dev); +#endif /* __SOC_NVIDIA_TEGRA_DC_H */ diff --git a/src/soc/nvidia/tegra/gpio.c b/src/soc/nvidia/tegra/gpio.c index d4b5bdd..0615320 100644 --- a/src/soc/nvidia/tegra/gpio.c +++ b/src/soc/nvidia/tegra/gpio.c @@ -26,41 +26,25 @@ #include "gpio.h" #include "pinmux.h" -static void gpio_input_common(int gpio_index, int pinmux_index, - uint32_t pconfig) +void __gpio_input(gpio_t gpio, u32 pull) { - pconfig |= PINMUX_INPUT_ENABLE; - gpio_set_int_enable(gpio_index, 0); - gpio_set_mode(gpio_index, GPIO_MODE_GPIO); - gpio_set_out_enable(gpio_index, 0); - pinmux_set_config(pinmux_index, pconfig); -} - -void gpio_input(int gpio_index, int pinmux_index) -{ - gpio_input_common(gpio_index, pinmux_index, PINMUX_PULL_NONE); -} + u32 pinmux_config = PINMUX_INPUT_ENABLE | PINMUX_TRISTATE | pull; -void gpio_input_pullup(int gpio_index, int pinmux_index) -{ - gpio_input_common(gpio_index, pinmux_index, PINMUX_PULL_UP); -} - -void gpio_input_pulldown(int gpio_index, int pinmux_index) -{ - gpio_input_common(gpio_index, pinmux_index, PINMUX_PULL_DOWN); + gpio_set_int_enable(gpio, 0); + gpio_set_out_enable(gpio, 0); + gpio_set_mode(gpio, GPIO_MODE_GPIO); + pinmux_set_config(gpio >> GPIO_PINMUX_SHIFT, pinmux_config); } -void gpio_output(int gpio_index, int pinmux_index, int value) +void gpio_output(gpio_t gpio, int value) { - uint32_t pconfig = PINMUX_PULL_NONE; + /* TODO: Set OPEN_DRAIN based on what pin it is? */ - pinmux_set_config(pinmux_index, pconfig | PINMUX_TRISTATE); - gpio_set_int_enable(gpio_index, 0); - gpio_set_mode(gpio_index, GPIO_MODE_GPIO); - gpio_set_out_enable(gpio_index, 1); - gpio_set_out_value(gpio_index, value); - pinmux_set_config(pinmux_index, pconfig); + gpio_set_int_enable(gpio, 0); + gpio_set_out_value(gpio, value); + gpio_set_out_enable(gpio, 1); + gpio_set_mode(gpio, GPIO_MODE_GPIO); + pinmux_set_config(gpio >> GPIO_PINMUX_SHIFT, PINMUX_PULL_NONE); } enum { @@ -74,167 +58,173 @@ enum { struct gpio_bank { // Values - uint32_t config[GPIO_PORTS_PER_BANK]; - uint32_t out_enable[GPIO_PORTS_PER_BANK]; - uint32_t out_value[GPIO_PORTS_PER_BANK]; - uint32_t in_value[GPIO_PORTS_PER_BANK]; - uint32_t int_status[GPIO_PORTS_PER_BANK]; - uint32_t int_enable[GPIO_PORTS_PER_BANK]; - uint32_t int_level[GPIO_PORTS_PER_BANK]; - uint32_t int_clear[GPIO_PORTS_PER_BANK]; + u32 config[GPIO_PORTS_PER_BANK]; + u32 out_enable[GPIO_PORTS_PER_BANK]; + u32 out_value[GPIO_PORTS_PER_BANK]; + u32 in_value[GPIO_PORTS_PER_BANK]; + u32 int_status[GPIO_PORTS_PER_BANK]; + u32 int_enable[GPIO_PORTS_PER_BANK]; + u32 int_level[GPIO_PORTS_PER_BANK]; + u32 int_clear[GPIO_PORTS_PER_BANK]; // Masks - uint32_t config_mask[GPIO_PORTS_PER_BANK]; - uint32_t out_enable_mask[GPIO_PORTS_PER_BANK]; - uint32_t out_value_mask[GPIO_PORTS_PER_BANK]; - uint32_t in_value_mask[GPIO_PORTS_PER_BANK]; - uint32_t int_status_mask[GPIO_PORTS_PER_BANK]; - uint32_t int_enable_mask[GPIO_PORTS_PER_BANK]; - uint32_t int_level_mask[GPIO_PORTS_PER_BANK]; - uint32_t int_clear_mask[GPIO_PORTS_PER_BANK]; + u32 config_mask[GPIO_PORTS_PER_BANK]; + u32 out_enable_mask[GPIO_PORTS_PER_BANK]; + u32 out_value_mask[GPIO_PORTS_PER_BANK]; + u32 in_value_mask[GPIO_PORTS_PER_BANK]; + u32 int_status_mask[GPIO_PORTS_PER_BANK]; + u32 int_enable_mask[GPIO_PORTS_PER_BANK]; + u32 int_level_mask[GPIO_PORTS_PER_BANK]; + u32 int_clear_mask[GPIO_PORTS_PER_BANK]; }; static const struct gpio_bank *gpio_banks = (void *)TEGRA_GPIO_BASE; -static uint32_t gpio_read_port(int index, size_t offset) +static u32 gpio_read_port(int index, size_t offset) { int bank = index / GPIO_GPIOS_PER_BANK; int port = (index - bank * GPIO_GPIOS_PER_BANK) / GPIO_GPIOS_PER_PORT; - return read32((uint8_t *)&gpio_banks[bank] + offset + - port * sizeof(uint32_t)); + return read32((u8 *)&gpio_banks[bank] + offset + + port * sizeof(u32)); } -static void gpio_write_port(int index, size_t offset, - uint32_t mask, uint32_t value) +static void gpio_write_port(int index, size_t offset, u32 mask, u32 value) { int bank = index / GPIO_GPIOS_PER_BANK; int port = (index - bank * GPIO_GPIOS_PER_BANK) / GPIO_GPIOS_PER_PORT; - uint32_t reg = read32((uint8_t *)&gpio_banks[bank] + offset + - port * sizeof(uint32_t)); - uint32_t new_reg = (reg & ~mask) | (value & mask); + u32 reg = read32((u8 *)&gpio_banks[bank] + offset + + port * sizeof(u32)); + u32 new_reg = (reg & ~mask) | (value & mask); if (new_reg != reg) { - write32(new_reg, (uint8_t *)&gpio_banks[bank] + offset + - port * sizeof(uint32_t)); + write32(new_reg, (u8 *)&gpio_banks[bank] + offset + + port * sizeof(u32)); } } -void gpio_set_mode(int gpio_index, enum gpio_mode mode) +void gpio_set_mode(gpio_t gpio, enum gpio_mode mode) { - int bit = gpio_index % GPIO_GPIOS_PER_PORT; - gpio_write_port(gpio_index, offsetof(struct gpio_bank, config), + int bit = gpio % GPIO_GPIOS_PER_PORT; + gpio_write_port(gpio & ((1 << GPIO_PINMUX_SHIFT) - 1), + offsetof(struct gpio_bank, config), 1 << bit, mode ? (1 << bit) : 0); } -int gpio_get_mode(int gpio_index) +int gpio_get_mode(gpio_t gpio) { - int bit = gpio_index % GPIO_GPIOS_PER_PORT; - uint32_t port = gpio_read_port(gpio_index, - offsetof(struct gpio_bank, config)); + int bit = gpio % GPIO_GPIOS_PER_PORT; + u32 port = gpio_read_port(gpio & ((1 << GPIO_PINMUX_SHIFT) - 1), + offsetof(struct gpio_bank, config)); return (port & (1 << bit)) != 0; } -void gpio_set_lock(int gpio_index) +void gpio_set_lock(gpio_t gpio) { - int bit = gpio_index % GPIO_GPIOS_PER_PORT + GPIO_GPIOS_PER_PORT; - gpio_write_port(gpio_index, offsetof(struct gpio_bank, config), + int bit = gpio % GPIO_GPIOS_PER_PORT + GPIO_GPIOS_PER_PORT; + gpio_write_port(gpio & ((1 << GPIO_PINMUX_SHIFT) - 1), + offsetof(struct gpio_bank, config), 1 << bit, 1 << bit); } -int gpio_get_lock(int gpio_index) +int gpio_get_lock(gpio_t gpio) { - int bit = gpio_index % GPIO_GPIOS_PER_PORT + GPIO_GPIOS_PER_PORT; - uint32_t port = gpio_read_port(gpio_index, - offsetof(struct gpio_bank, config)); + int bit = gpio % GPIO_GPIOS_PER_PORT + GPIO_GPIOS_PER_PORT; + u32 port = gpio_read_port(gpio & ((1 << GPIO_PINMUX_SHIFT) - 1), + offsetof(struct gpio_bank, config)); return (port & (1 << bit)) != 0; } -void gpio_set_out_enable(int gpio_index, int enable) +void gpio_set_out_enable(gpio_t gpio, int enable) { - int bit = gpio_index % GPIO_GPIOS_PER_PORT; - gpio_write_port(gpio_index, offsetof(struct gpio_bank, out_enable), + int bit = gpio % GPIO_GPIOS_PER_PORT; + gpio_write_port(gpio & ((1 << GPIO_PINMUX_SHIFT) - 1), + offsetof(struct gpio_bank, out_enable), 1 << bit, enable ? (1 << bit) : 0); } -int gpio_get_out_enable(int gpio_index) +int gpio_get_out_enable(gpio_t gpio) { - int bit = gpio_index % GPIO_GPIOS_PER_PORT; - uint32_t port = gpio_read_port(gpio_index, - offsetof(struct gpio_bank, out_enable)); + int bit = gpio % GPIO_GPIOS_PER_PORT; + u32 port = gpio_read_port(gpio & ((1 << GPIO_PINMUX_SHIFT) - 1), + offsetof(struct gpio_bank, out_enable)); return (port & (1 << bit)) != 0; } -void gpio_set_out_value(int gpio_index, int value) +void gpio_set_out_value(gpio_t gpio, int value) { - int bit = gpio_index % GPIO_GPIOS_PER_PORT; - gpio_write_port(gpio_index, offsetof(struct gpio_bank, out_value), + int bit = gpio % GPIO_GPIOS_PER_PORT; + gpio_write_port(gpio & ((1 << GPIO_PINMUX_SHIFT) - 1), + offsetof(struct gpio_bank, out_value), 1 << bit, value ? (1 << bit) : 0); } -int gpio_get_out_value(int gpio_index) +int gpio_get_out_value(gpio_t gpio) { - int bit = gpio_index % GPIO_GPIOS_PER_PORT; - uint32_t port = gpio_read_port(gpio_index, - offsetof(struct gpio_bank, out_value)); + int bit = gpio % GPIO_GPIOS_PER_PORT; + u32 port = gpio_read_port(gpio & ((1 << GPIO_PINMUX_SHIFT) - 1), + offsetof(struct gpio_bank, out_value)); return (port & (1 << bit)) != 0; } -int gpio_get_in_value(int gpio_index) +int gpio_get_in_value(gpio_t gpio) { - int bit = gpio_index % GPIO_GPIOS_PER_PORT; - uint32_t port = gpio_read_port(gpio_index, - offsetof(struct gpio_bank, in_value)); + int bit = gpio % GPIO_GPIOS_PER_PORT; + u32 port = gpio_read_port(gpio & ((1 << GPIO_PINMUX_SHIFT) - 1), + offsetof(struct gpio_bank, in_value)); return (port & (1 << bit)) != 0; } -int gpio_get_int_status(int gpio_index) +int gpio_get_int_status(gpio_t gpio) { - int bit = gpio_index % GPIO_GPIOS_PER_PORT; - uint32_t port = gpio_read_port(gpio_index, - offsetof(struct gpio_bank, int_status)); + int bit = gpio % GPIO_GPIOS_PER_PORT; + u32 port = gpio_read_port(gpio & ((1 << GPIO_PINMUX_SHIFT) - 1), + offsetof(struct gpio_bank, int_status)); return (port & (1 << bit)) != 0; } -void gpio_set_int_enable(int gpio_index, int enable) +void gpio_set_int_enable(gpio_t gpio, int enable) { - int bit = gpio_index % GPIO_GPIOS_PER_PORT; - gpio_write_port(gpio_index, offsetof(struct gpio_bank, int_enable), + int bit = gpio % GPIO_GPIOS_PER_PORT; + gpio_write_port(gpio & ((1 << GPIO_PINMUX_SHIFT) - 1), + offsetof(struct gpio_bank, int_enable), 1 << bit, enable ? (1 << bit) : 0); } -int gpio_get_int_enable(int gpio_index) +int gpio_get_int_enable(gpio_t gpio) { - int bit = gpio_index % GPIO_GPIOS_PER_PORT; - uint32_t port = gpio_read_port(gpio_index, - offsetof(struct gpio_bank, int_enable)); + int bit = gpio % GPIO_GPIOS_PER_PORT; + u32 port = gpio_read_port(gpio & ((1 << GPIO_PINMUX_SHIFT) - 1), + offsetof(struct gpio_bank, int_enable)); return (port & (1 << bit)) != 0; } -void gpio_set_int_level(int gpio_index, int high_rise, int edge, int delta) +void gpio_set_int_level(gpio_t gpio, int high_rise, int edge, int delta) { - int bit = gpio_index % GPIO_GPIOS_PER_PORT; - uint32_t value = (high_rise ? (0x000001 << bit) : 0) | + int bit = gpio % GPIO_GPIOS_PER_PORT; + u32 value = (high_rise ? (0x000001 << bit) : 0) | (edge ? (0x000100 << bit) : 0) | - (delta ? (0x010000 << bit) : 0); - gpio_write_port(gpio_index, offsetof(struct gpio_bank, config), + (delta ? (0x010000 << bit) : 0); + gpio_write_port(gpio & ((1 << GPIO_PINMUX_SHIFT) - 1), + offsetof(struct gpio_bank, config), 0x010101 << bit, value); } -void gpio_get_int_level(int gpio_index, int *high_rise, int *edge, int *delta) +void gpio_get_int_level(gpio_t gpio, int *high_rise, int *edge, int *delta) { - int bit = gpio_index % GPIO_GPIOS_PER_PORT; - uint32_t port = gpio_read_port(gpio_index, - offsetof(struct gpio_bank, int_level)); + int bit = gpio % GPIO_GPIOS_PER_PORT; + u32 port = gpio_read_port(gpio & ((1 << GPIO_PINMUX_SHIFT) - 1), + offsetof(struct gpio_bank, int_level)); *high_rise = ((port & (0x000001 << bit)) != 0); *edge = ((port & (0x000100 << bit)) != 0); *delta = ((port & (0x010000 << bit)) != 0); } -void gpio_set_int_clear(int gpio_index) +void gpio_set_int_clear(gpio_t gpio) { - int bit = gpio_index % GPIO_GPIOS_PER_PORT; - gpio_write_port(gpio_index, offsetof(struct gpio_bank, int_clear), + int bit = gpio % GPIO_GPIOS_PER_PORT; + gpio_write_port(gpio & ((1 << GPIO_PINMUX_SHIFT) - 1), + offsetof(struct gpio_bank, int_clear), 1 << bit, 1 << bit); } diff --git a/src/soc/nvidia/tegra/gpio.h b/src/soc/nvidia/tegra/gpio.h index b62dc90..546ea05 100644 --- a/src/soc/nvidia/tegra/gpio.h +++ b/src/soc/nvidia/tegra/gpio.h @@ -22,12 +22,34 @@ #include <stdint.h> -/* Higher level functions for common GPIO configurations. */ +#include "pinmux.h" -void gpio_input(int gpio_index, int pinmux_index); -void gpio_input_pullup(int gpio_index, int pinmux_index); -void gpio_input_pulldown(int gpio_index, int pinmux_index); -void gpio_output(int gpio_index, int pinmux_index, int value); +/* Wrapper type for GPIOs. Always use GPIO() macro to generate. */ +typedef u32 gpio_t; + +#define GPIO_PINMUX_SHIFT 16 +#define GPIO(name) ((gpio_t)(GPIO_##name##_INDEX | \ + (PINMUX_GPIO_##name << GPIO_PINMUX_SHIFT))) + +/* Higher level function wrappers for common GPIO configurations. */ + +void gpio_output(gpio_t gpio, int value); +void __gpio_input(gpio_t gpio, u32 pull); + +static inline void gpio_input(gpio_t gpio) +{ + __gpio_input(gpio, PINMUX_PULL_NONE); +} + +static inline void gpio_input_pulldown(gpio_t gpio) +{ + __gpio_input(gpio, PINMUX_PULL_DOWN); +} + +static inline void gpio_input_pullup(gpio_t gpio) +{ + __gpio_input(gpio, PINMUX_PULL_UP); +} /* Functions to modify specific GPIO control values. */ @@ -35,29 +57,29 @@ enum gpio_mode { GPIO_MODE_SPIO = 0, GPIO_MODE_GPIO = 1 }; -void gpio_set_mode(int gpio_index, enum gpio_mode); -int gpio_get_mode(int gpio_index); +void gpio_set_mode(gpio_t gpio, enum gpio_mode); +int gpio_get_mode(gpio_t gpio); // Lock a GPIO with extreme caution since they can't be unlocked. -void gpio_set_lock(int gpio_index); -int gpio_get_lock(int gpio_index); +void gpio_set_lock(gpio_t gpio); +int gpio_get_lock(gpio_t gpio); -void gpio_set_out_enable(int gpio_index, int enable); -int gpio_get_out_enable(int gpio_index); +void gpio_set_out_enable(gpio_t gpio, int enable); +int gpio_get_out_enable(gpio_t gpio); -void gpio_set_out_value(int gpio_index, int value); -int gpio_get_out_value(int gpio_index); +void gpio_set_out_value(gpio_t gpio, int value); +int gpio_get_out_value(gpio_t gpio); -int gpio_get_in_value(int gpio_index); +int gpio_get_in_value(gpio_t gpio); -int gpio_get_int_status(int gpio_index); +int gpio_get_int_status(gpio_t gpio); -void gpio_set_int_enable(int gpio_index, int enable); -int gpio_get_int_enable(int gpio_index); +void gpio_set_int_enable(gpio_t gpio, int enable); +int gpio_get_int_enable(gpio_t gpio); -void gpio_set_int_level(int gpio_index, int high_rise, int edge, int delta); -void gpio_get_int_level(int gpio_index, int *high_rise, int *edge, int *delta); +void gpio_set_int_level(gpio_t gpio, int high_rise, int edge, int delta); +void gpio_get_int_level(gpio_t gpio, int *high_rise, int *edge, int *delta); -void gpio_set_int_clear(int gpio_index); +void gpio_set_int_clear(gpio_t gpio); #endif /* __SOC_NVIDIA_TEGRA_GPIO_H__ */ diff --git a/src/soc/nvidia/tegra/i2c.c b/src/soc/nvidia/tegra/i2c.c index ddb54a5..e9001f0 100644 --- a/src/soc/nvidia/tegra/i2c.c +++ b/src/soc/nvidia/tegra/i2c.c @@ -32,12 +32,10 @@ static int tegra_i2c_send_recv(struct tegra_i2c_regs *regs, int read, { while (data_len) { uint32_t status = read32(&regs->fifo_status); - int tx_empty = - status & TEGRA_I2C_FIFO_STATUS_TX_FIFO_EMPTY_CNT_MASK; - tx_empty >>= TEGRA_I2C_FIFO_STATUS_TX_FIFO_EMPTY_CNT_SHIFT; - int rx_full = - status & TEGRA_I2C_FIFO_STATUS_RX_FIFO_FULL_CNT_MASK; - rx_full >>= TEGRA_I2C_FIFO_STATUS_RX_FIFO_FULL_CNT_SHIFT; + int tx_empty = status & I2C_FIFO_STATUS_TX_FIFO_EMPTY_CNT_MASK; + tx_empty >>= I2C_FIFO_STATUS_TX_FIFO_EMPTY_CNT_SHIFT; + int rx_full = status & I2C_FIFO_STATUS_RX_FIFO_FULL_CNT_MASK; + rx_full >>= I2C_FIFO_STATUS_RX_FIFO_FULL_CNT_SHIFT; while (header_words && tx_empty) { write32(*headers++, &regs->tx_packet_fifo); @@ -73,19 +71,17 @@ static int tegra_i2c_send_recv(struct tegra_i2c_regs *regs, int read, uint32_t transfer_status = read32(&regs->packet_transfer_status); - if (transfer_status & TEGRA_I2C_PKT_STATUS_NOACK_ADDR_MASK) { + if (transfer_status & I2C_PKT_STATUS_NOACK_ADDR) { printk(BIOS_ERR, "%s: The address was not acknowledged.\n", __func__); return -1; - } else if (transfer_status & - TEGRA_I2C_PKT_STATUS_NOACK_DATA_MASK) { + } else if (transfer_status & I2C_PKT_STATUS_NOACK_DATA) { printk(BIOS_ERR, "%s: The data was not acknowledged.\n", __func__); return -1; - } else if (transfer_status & - TEGRA_I2C_PKT_STATUS_ARB_LOST_MASK) { + } else if (transfer_status & I2C_PKT_STATUS_ARB_LOST) { printk(BIOS_ERR, "%s: Lost arbitration.\n", __func__); @@ -108,25 +104,22 @@ static int tegra_i2c_request(int bus, unsigned chip, int cont, int restart, return -1; } - headers[0] = (0 << IOHEADER_WORD0_PROTHDRSZ_SHIFT) | - (1 << IOHEADER_WORD0_PKTID_SHIFT) | - (bus << IOHEADER_WORD0_CONTROLLER_ID_SHIFT) | - IOHEADER_WORD0_PROTOCOL_I2C | - IOHEADER_WORD0_PKTTYPE_REQUEST; + headers[0] = (0 << IOHEADER_PROTHDRSZ_SHIFT) | + (1 << IOHEADER_PKTID_SHIFT) | + (bus << IOHEADER_CONTROLLER_ID_SHIFT) | + IOHEADER_PROTOCOL_I2C | IOHEADER_PKTTYPE_REQUEST; - headers[1] = (data_len - 1) << IOHEADER_WORD1_PAYLOADSIZE_SHIFT; + headers[1] = (data_len - 1) << IOHEADER_PAYLOADSIZE_SHIFT; uint32_t slave_addr = (chip << 1) | (read ? 1 : 0); - headers[2] = IOHEADER_I2C_REQ_ADDRESS_MODE_7BIT | + headers[2] = IOHEADER_I2C_REQ_ADDR_MODE_7BIT | (slave_addr << IOHEADER_I2C_REQ_SLAVE_ADDR_SHIFT); if (read) - headers[2] |= IOHEADER_I2C_REQ_READ_WRITE_READ; - else - headers[2] |= IOHEADER_I2C_REQ_READ_WRITE_WRITE; + headers[2] |= IOHEADER_I2C_REQ_READ; if (restart) - headers[2] |= IOHEADER_I2C_REQ_REPEAT_START_STOP_START; + headers[2] |= IOHEADER_I2C_REQ_REPEAT_START; if (cont) - headers[2] |= IOHEADER_I2C_REQ_CONTINUE_XFER_MASK; + headers[2] |= IOHEADER_I2C_REQ_CONTINUE_XFER; return tegra_i2c_send_recv(regs, read, headers, ARRAY_SIZE(headers), data, data_len); @@ -136,8 +129,7 @@ static int i2c_readwrite(unsigned bus, unsigned chip, unsigned addr, unsigned alen, uint8_t *buf, unsigned len, int read) { const uint32_t max_payload = - (IOHEADER_WORD1_PAYLOADSIZE_MASK + 1) >> - IOHEADER_WORD1_PAYLOADSIZE_SHIFT; + (IOHEADER_PAYLOADSIZE_MASK + 1) >> IOHEADER_PAYLOADSIZE_SHIFT; uint8_t abuf[sizeof(addr)]; int i; @@ -176,5 +168,5 @@ void i2c_init(unsigned bus) { struct tegra_i2c_regs * const regs = tegra_i2c_bases[bus]; - write32(TEGRA_I2C_CNFG_PACKET_MODE_EN_MASK, &regs->cnfg); + write32(I2C_CNFG_PACKET_MODE_EN, &regs->cnfg); } diff --git a/src/soc/nvidia/tegra/i2c.h b/src/soc/nvidia/tegra/i2c.h index 630d890..997ec9c 100644 --- a/src/soc/nvidia/tegra/i2c.h +++ b/src/soc/nvidia/tegra/i2c.h @@ -24,133 +24,90 @@ void i2c_init(unsigned bus); -#define IOHEADER_BITFIELD(name, shift, mask) \ - IOHEADER_##name##_SHIFT = shift, \ - IOHEADER_##name##_MASK = \ - mask << IOHEADER_##name##_SHIFT - -#define IOHEADER_BITFIELD_VAL(field, name, val) \ - IOHEADER_##field##_##name = \ - val << IOHEADER_##field##_SHIFT - enum { /* Word 0 */ - IOHEADER_BITFIELD(WORD0_PROTHDRSZ, 28, 0x3), - - IOHEADER_BITFIELD(WORD0_PKTID, 16, 0xff), - - IOHEADER_BITFIELD(WORD0_CONTROLLER_ID, 12, 0xf), - - IOHEADER_BITFIELD(WORD0_PROTOCOL, 4, 0xf), - IOHEADER_BITFIELD_VAL(WORD0_PROTOCOL, I2C, 1), - - IOHEADER_BITFIELD(WORD0_PKTTYPE, 0, 0x7), - IOHEADER_BITFIELD_VAL(WORD0_PKTTYPE, REQUEST, 0), - IOHEADER_BITFIELD_VAL(WORD0_PKTTYPE, RESPONSE, 1), - IOHEADER_BITFIELD_VAL(WORD0_PKTTYPE, INTERRUPT, 2), - IOHEADER_BITFIELD_VAL(WORD0_PKTTYPE, STOP, 3), + IOHEADER_PROTHDRSZ_SHIFT = 28, + IOHEADER_PROTHDRSZ_MASK = 0x3 << IOHEADER_PROTHDRSZ_SHIFT, + IOHEADER_PKTID_SHIFT = 16, + IOHEADER_PKTID_MASK = 0xff << IOHEADER_PKTID_SHIFT, + IOHEADER_CONTROLLER_ID_SHIFT = 12, + IOHEADER_CONTROLLER_ID_MASK = 0xf << IOHEADER_CONTROLLER_ID_SHIFT, + IOHEADER_PROTOCOL_SHIFT = 4, + IOHEADER_PROTOCOL_MASK = 0xf << IOHEADER_PROTOCOL_SHIFT, + IOHEADER_PROTOCOL_I2C = 1 << IOHEADER_PROTOCOL_SHIFT, + IOHEADER_PKTTYPE_SHIFT = 0, + IOHEADER_PKTTYPE_MASK = 0x7 << IOHEADER_PKTTYPE_SHIFT, + IOHEADER_PKTTYPE_REQUEST = 0 << IOHEADER_PKTTYPE_SHIFT, + IOHEADER_PKTTYPE_RESPONSE = 1 << IOHEADER_PKTTYPE_SHIFT, + IOHEADER_PKTTYPE_INTERRUPT = 2 << IOHEADER_PKTTYPE_SHIFT, + IOHEADER_PKTTYPE_STOP = 3 << IOHEADER_PKTTYPE_SHIFT, /* Word 1 */ - IOHEADER_BITFIELD(WORD1_PAYLOADSIZE, 0, 0xfff) + IOHEADER_PAYLOADSIZE_SHIFT = 0, + IOHEADER_PAYLOADSIZE_MASK = 0xfff << IOHEADER_PAYLOADSIZE_SHIFT }; enum { - IOHEADER_BITFIELD(I2C_REQ_RESP_PKT_FREQ_SHIFT, 25, 0x1), - IOHEADER_BITFIELD_VAL(I2C_REQ_RESP_PKT_FREQ_SHIFT, END, 0), - IOHEADER_BITFIELD_VAL(I2C_REQ_RESP_PKT_FREQ_SHIFT, EACH, 1), - - IOHEADER_BITFIELD(I2C_REQ_RESP_PKT_ENABLE, 24, 0x1), - - IOHEADER_BITFIELD(I2C_REQ_HS_MODE, 22, 0x1), - - IOHEADER_BITFIELD(I2C_REQ_CONTINUE_ON_NACK, 21, 0x1), - - IOHEADER_BITFIELD(I2C_REQ_SEND_START_BYTE, 20, 0x1), - - IOHEADER_BITFIELD(I2C_REQ_READ_WRITE, 19, 0x1), - IOHEADER_BITFIELD_VAL(I2C_REQ_READ_WRITE, WRITE, 0), - IOHEADER_BITFIELD_VAL(I2C_REQ_READ_WRITE, READ, 1), - - IOHEADER_BITFIELD(I2C_REQ_ADDRESS_MODE, 18, 0x1), - IOHEADER_BITFIELD_VAL(I2C_REQ_ADDRESS_MODE, 7BIT, 0), - IOHEADER_BITFIELD_VAL(I2C_REQ_ADDRESS_MODE, 10BIT, 1), - - IOHEADER_BITFIELD(I2C_REQ_IE, 17, 0x1), - - IOHEADER_BITFIELD(I2C_REQ_REPEAT_START_STOP, 16, 0x1), - IOHEADER_BITFIELD_VAL(I2C_REQ_REPEAT_START_STOP, STOP, 0), - IOHEADER_BITFIELD_VAL(I2C_REQ_REPEAT_START_STOP, START, 1), - - IOHEADER_BITFIELD(I2C_REQ_CONTINUE_XFER, 15, 0x1), - - IOHEADER_BITFIELD(I2C_REQ_HS_MASTER_ADDR, 12, 0x7), - - IOHEADER_BITFIELD(I2C_REQ_SLAVE_ADDR, 0, 0x3ff) + IOHEADER_I2C_REQ_RESP_FREQ_MASK = 0x1 << 25, + IOHEADER_I2C_REQ_RESP_FREQ_END = 0 << 25, + IOHEADER_I2C_REQ_RESP_FREQ_EACH = 1 << 25, + IOHEADER_I2C_REQ_RESP_ENABLE = 0x1 << 24, + IOHEADER_I2C_REQ_HS_MODE = 0x1 << 22, + IOHEADER_I2C_REQ_CONTINUE_ON_NACK = 0x1 << 21, + IOHEADER_I2C_REQ_SEND_START_BYTE = 0x1 << 20, + IOHEADER_I2C_REQ_READ = 0x1 << 19, + IOHEADER_I2C_REQ_ADDR_MODE_MASK = 0x1 << 18, + IOHEADER_I2C_REQ_ADDR_MODE_7BIT = 0 << 18, + IOHEADER_I2C_REQ_ADDR_MODE_10BIT = 1 << 18, + IOHEADER_I2C_REQ_IE = 0x1 << 17, + IOHEADER_I2C_REQ_REPEAT_START = 0x1 << 16, + IOHEADER_I2C_REQ_STOP = 0x0 << 16, + IOHEADER_I2C_REQ_CONTINUE_XFER = 0x1 << 15, + IOHEADER_I2C_REQ_HS_MASTER_ADDR_SHIFT = 12, + IOHEADER_I2C_REQ_HS_MASTER_ADDR_MASK = + 0x7 << IOHEADER_I2C_REQ_HS_MASTER_ADDR_SHIFT, + IOHEADER_I2C_REQ_SLAVE_ADDR_SHIFT = 0, + IOHEADER_I2C_REQ_SLAVE_ADDR_MASK = + 0x3ff << IOHEADER_I2C_REQ_SLAVE_ADDR_SHIFT }; enum { - TEGRA_I2C_CNFG_MSTR_CLR_BUS_ON_TIMEOUT_SHIFT = 15, - TEGRA_I2C_CNFG_MSTR_CLR_BUS_ON_TIMEOUT_MASK = - 0x1 << TEGRA_I2C_CNFG_MSTR_CLR_BUS_ON_TIMEOUT_SHIFT, - TEGRA_I2C_CNFG_DEBOUNCE_CNT_SHIFT = 12, - TEGRA_I2C_CNFG_DEBOUNCE_CNT_MASK = - 0x7 << TEGRA_I2C_CNFG_DEBOUNCE_CNT_SHIFT, - TEGRA_I2C_CNFG_NEW_MASTER_FSM_SHIFT = 11, - TEGRA_I2C_CNFG_NEW_MASTER_FSM_MASK = - 0x1 << TEGRA_I2C_CNFG_NEW_MASTER_FSM_SHIFT, - TEGRA_I2C_CNFG_PACKET_MODE_EN_SHIFT = 10, - TEGRA_I2C_CNFG_PACKET_MODE_EN_MASK = - 0x1 << TEGRA_I2C_CNFG_PACKET_MODE_EN_SHIFT, - TEGRA_I2C_CNFG_SEND_SHIFT = 9, - TEGRA_I2C_CNFG_SEND_MASK = 0x1 << TEGRA_I2C_CNFG_SEND_SHIFT, - TEGRA_I2C_CNFG_NOACK_SHIFT = 8, - TEGRA_I2C_CNFG_NOACK_MASK = 0x1 << TEGRA_I2C_CNFG_NOACK_SHIFT, - TEGRA_I2C_CNFG_CMD2_SHIFT = 7, - TEGRA_I2C_CNFG_CMD2_MASK = 0x1 << TEGRA_I2C_CNFG_CMD2_SHIFT, - TEGRA_I2C_CNFG_CMD1_SHIFT = 6, - TEGRA_I2C_CNFG_CMD1_MASK = 0x1 << TEGRA_I2C_CNFG_CMD1_SHIFT, - TEGRA_I2C_CNFG_START_SHIFT = 5, - TEGRA_I2C_CNFG_START_MASK = 0x1 << TEGRA_I2C_CNFG_START_SHIFT, - TEGRA_I2C_CNFG_SLV2_SHIFT = 4, - TEGRA_I2C_CNFG_SLV2_MASK = 0x1 << TEGRA_I2C_CNFG_SLV2_SHIFT, - TEGRA_I2C_CNFG_LENGTH_SHIFT = 1, - TEGRA_I2C_CNFG_LENGTH_MASK = 0x7 << TEGRA_I2C_CNFG_LENGTH_SHIFT, - TEGRA_I2C_CNFG_A_MOD_SHIFT = 0, - TEGRA_I2C_CNFG_A_MOD_MASK = 0x1 << TEGRA_I2C_CNFG_A_MOD_SHIFT + I2C_CNFG_MSTR_CLR_BUS_ON_TIMEOUT = 0x1 << 15, + I2C_CNFG_DEBOUNCE_CNT_SHIFT = 12, + I2C_CNFG_DEBOUNCE_CNT_MASK = 0x7 << I2C_CNFG_DEBOUNCE_CNT_SHIFT, + I2C_CNFG_NEW_MASTER_FSM = 0x1 << 11, + I2C_CNFG_PACKET_MODE_EN = 0x1 << 10, + I2C_CNFG_SEND = 0x1 << 9, + I2C_CNFG_NOACK = 0x1 << 8, + I2C_CNFG_CMD2 = 0x1 << 7, + I2C_CNFG_CMD1 = 0x1 << 6, + I2C_CNFG_START = 0x1 << 5, + I2C_CNFG_SLV2_SHIFT = 4, + I2C_CNFG_SLV2_MASK = 0x1 << I2C_CNFG_SLV2_SHIFT, + I2C_CNFG_LENGTH_SHIFT = 1, + I2C_CNFG_LENGTH_MASK = 0x7 << I2C_CNFG_LENGTH_SHIFT, + I2C_CNFG_A_MOD = 0x1 << 0, }; enum { - TEGRA_I2C_PKT_STATUS_COMPLETE_SHIFT = 24, - TEGRA_I2C_PKT_STATUS_COMPLETE_MASK = - 0x1 << TEGRA_I2C_PKT_STATUS_COMPLETE_SHIFT, - TEGRA_I2C_PKT_STATUS_PKT_ID_SHIFT = 16, - TEGRA_I2C_PKT_STATUS_PKT_ID_MASK = - 0xff << TEGRA_I2C_PKT_STATUS_PKT_ID_SHIFT, - TEGRA_I2C_PKT_STATUS_BYTENUM_SHIFT = 4, - TEGRA_I2C_PKT_STATUS_BYTENUM_MASK = - 0xfff << TEGRA_I2C_PKT_STATUS_BYTENUM_SHIFT, - TEGRA_I2C_PKT_STATUS_NOACK_ADDR_SHIFT = 3, - TEGRA_I2C_PKT_STATUS_NOACK_ADDR_MASK = - 0x1 << TEGRA_I2C_PKT_STATUS_NOACK_ADDR_SHIFT, - TEGRA_I2C_PKT_STATUS_NOACK_DATA_SHIFT = 2, - TEGRA_I2C_PKT_STATUS_NOACK_DATA_MASK = - 0x1 << TEGRA_I2C_PKT_STATUS_NOACK_DATA_SHIFT, - TEGRA_I2C_PKT_STATUS_ARB_LOST_SHIFT = 1, - TEGRA_I2C_PKT_STATUS_ARB_LOST_MASK = - 0x1 << TEGRA_I2C_PKT_STATUS_ARB_LOST_SHIFT, - TEGRA_I2C_PKT_STATUS_BUSY_SHIFT = 0, - TEGRA_I2C_PKT_STATUS_BUSY_MASK = - 0x1 << TEGRA_I2C_PKT_STATUS_BUSY_SHIFT, + I2C_PKT_STATUS_COMPLETE = 0x1 << 24, + I2C_PKT_STATUS_PKT_ID_SHIFT = 16, + I2C_PKT_STATUS_PKT_ID_MASK = 0xff << I2C_PKT_STATUS_PKT_ID_SHIFT, + I2C_PKT_STATUS_BYTENUM_SHIFT = 4, + I2C_PKT_STATUS_BYTENUM_MASK = 0xfff << I2C_PKT_STATUS_BYTENUM_SHIFT, + I2C_PKT_STATUS_NOACK_ADDR = 0x1 << 3, + I2C_PKT_STATUS_NOACK_DATA = 0x1 << 2, + I2C_PKT_STATUS_ARB_LOST = 0x1 << 1, + I2C_PKT_STATUS_BUSY = 0x1 << 0 }; enum { - TEGRA_I2C_FIFO_STATUS_TX_FIFO_EMPTY_CNT_SHIFT = 4, - TEGRA_I2C_FIFO_STATUS_TX_FIFO_EMPTY_CNT_MASK = - 0xf << TEGRA_I2C_FIFO_STATUS_TX_FIFO_EMPTY_CNT_SHIFT, - - TEGRA_I2C_FIFO_STATUS_RX_FIFO_FULL_CNT_SHIFT = 0, - TEGRA_I2C_FIFO_STATUS_RX_FIFO_FULL_CNT_MASK = - 0xf << TEGRA_I2C_FIFO_STATUS_RX_FIFO_FULL_CNT_SHIFT + I2C_FIFO_STATUS_TX_FIFO_EMPTY_CNT_SHIFT = 4, + I2C_FIFO_STATUS_TX_FIFO_EMPTY_CNT_MASK = + 0xf << I2C_FIFO_STATUS_TX_FIFO_EMPTY_CNT_SHIFT, + I2C_FIFO_STATUS_RX_FIFO_FULL_CNT_SHIFT = 0, + I2C_FIFO_STATUS_RX_FIFO_FULL_CNT_MASK = + 0xf << I2C_FIFO_STATUS_RX_FIFO_FULL_CNT_SHIFT }; extern void * const tegra_i2c_bases[]; diff --git a/src/soc/nvidia/tegra124/Kconfig b/src/soc/nvidia/tegra124/Kconfig index 4e5bd62..30c9feb 100644 --- a/src/soc/nvidia/tegra124/Kconfig +++ b/src/soc/nvidia/tegra124/Kconfig @@ -4,6 +4,7 @@ config SOC_NVIDIA_TEGRA124 select ARCH_RAMSTAGE_ARMV7 select HAVE_UART_SPECIAL select BOOTBLOCK_CONSOLE + select DYNAMIC_CBMEM select ARM_BOOTBLOCK_CUSTOM bool default n diff --git a/src/soc/nvidia/tegra124/Makefile.inc b/src/soc/nvidia/tegra124/Makefile.inc index 1a04051..d78553d 100644 --- a/src/soc/nvidia/tegra124/Makefile.inc +++ b/src/soc/nvidia/tegra124/Makefile.inc @@ -2,8 +2,13 @@ bootblock-y += bootblock.c bootblock-y += bootblock_asm.S bootblock-y += cbfs.c bootblock-y += clock.c +bootblock-y += cpug.S +bootblock-y += dma.c bootblock-y += i2c.c +bootblock-y += dma.c bootblock-y += monotonic_timer.c +bootblock-y += power.c +bootblock-y += spi.c bootblock-y += ../tegra/gpio.c bootblock-y += ../tegra/i2c.c bootblock-y += ../tegra/pingroup.c @@ -14,12 +19,31 @@ bootblock-$(CONFIG_CONSOLE_SERIAL) += uart.c endif romstage-y += cbfs.c +romstage-y += cbmem.c +romstage-y += early_display.c +romstage-y += dma.c +romstage-y += i2c.c romstage-y += monotonic_timer.c +romstage-y += spi.c +romstage-y += ../tegra/gpio.c +romstage-y += ../tegra/i2c.c +romstage-y += ../tegra/pinmux.c romstage-y += timer.c romstage-$(CONFIG_CONSOLE_SERIAL) += uart.c ramstage-y += cbfs.c +ramstage-y += cbmem.c +ramstage-y += cpug.S +ramstage-y += clock.c +ramstage-y += display.c +ramstage-y += dma.c +ramstage-y += i2c.c ramstage-y += monotonic_timer.c +ramstage-y += soc.c +ramstage-y += spi.c +ramstage-y += ../tegra/gpio.c +ramstage-y += ../tegra/i2c.c +ramstage-y += ../tegra/pinmux.c ramstage-y += timer.c ramstage-$(CONFIG_CONSOLE_SERIAL) += uart.c diff --git a/src/soc/nvidia/tegra124/bootblock.c b/src/soc/nvidia/tegra124/bootblock.c index a3bed23..2698611 100644 --- a/src/soc/nvidia/tegra124/bootblock.c +++ b/src/soc/nvidia/tegra124/bootblock.c @@ -18,38 +18,19 @@ */ #include <arch/hlt.h> -#include <arch/io.h> +#include <bootblock_common.h> #include <cbfs.h> #include <console/console.h> -#include <delay.h> +#include <soc/clock.h> -#include "clock.h" #include "pinmux.h" - -static void hacky_hardcoded_uart_setup_function(void) -{ - // Assert UART reset and enable clock. - setbits_le32((void *)(0x60006000 + 4 + 0), 1 << 6); - - // Enable the clock. - setbits_le32((void *)(0x60006000 + 4 * 4 + 0), 1 << 6); - - // Set the clock source. - clrbits_le32((void *)(0x60006000 + 0x100 + 4 * 0x1e), 3 << 30); - - udelay(2); - - // De-assert reset to UART. - clrbits_le32((void *)(0x60006000 + 4 + 0), 1 << 6); -} +#include "power.h" void main(void) { void *entry; - set_avp_clock_to_clkm(); - - hacky_hardcoded_uart_setup_function(); + clock_early_uart(); // Serial out, tristate off. pinmux_set_config(PINMUX_KB_ROW9_INDEX, PINMUX_KB_ROW9_FUNC_UA3); @@ -61,7 +42,26 @@ void main(void) if (CONFIG_BOOTBLOCK_CONSOLE) console_init(); + clock_init(); + + bootblock_mainboard_init(); + + pinmux_set_config(PINMUX_CORE_PWR_REQ_INDEX, + PINMUX_CORE_PWR_REQ_FUNC_PWRON); + pinmux_set_config(PINMUX_CPU_PWR_REQ_INDEX, + PINMUX_CPU_PWR_REQ_FUNC_CPU); + pinmux_set_config(PINMUX_PWR_INT_N_INDEX, + PINMUX_PWR_INT_N_FUNC_PMICINTR | + PINMUX_TRISTATE | + PINMUX_INPUT_ENABLE); + + power_enable_cpu_rail(); + power_ungate_cpu(); + entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, "fallback/romstage"); + if (entry) + clock_cpu0_config_and_reset(entry); + hlt(); } diff --git a/src/soc/nvidia/tegra124/cbfs.c b/src/soc/nvidia/tegra124/cbfs.c index ede9146..4497d6a 100644 --- a/src/soc/nvidia/tegra124/cbfs.c +++ b/src/soc/nvidia/tegra124/cbfs.c @@ -20,7 +20,11 @@ #include <cbfs.h> /* This driver serves as a CBFS media source. */ +#include "spi.h" + int init_default_cbfs_media(struct cbfs_media *media) { - return -1; + return initialize_tegra_spi_cbfs_media(media, + (void*)CONFIG_CBFS_CACHE_ADDRESS, + CONFIG_CBFS_CACHE_SIZE); } diff --git a/src/soc/nvidia/tegra124/cbmem.c b/src/soc/nvidia/tegra124/cbmem.c new file mode 100644 index 0000000..d80b3a0 --- /dev/null +++ b/src/soc/nvidia/tegra124/cbmem.c @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <cbmem.h> +#include <soc/addressmap.h> + +void *cbmem_top(void) +{ + return (void *)(CONFIG_SYS_SDRAM_BASE + + ((CONFIG_DRAM_SIZE_MB - FB_SIZE_MB)<< 20UL)); +} diff --git a/src/soc/nvidia/tegra124/chip.h b/src/soc/nvidia/tegra124/chip.h new file mode 100644 index 0000000..b05bcc7 --- /dev/null +++ b/src/soc/nvidia/tegra124/chip.h @@ -0,0 +1,91 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef __SOC_NVIDIA_TEGRA124_CHIP_H__ +#define __SOC_NVIDIA_TEGRA124_CHIP_H__ +#include <arch/cache.h> +#include <soc/addressmap.h> +#include "gpio.h" + +/* this is a misuse of the device tree. We're going to let it go for now but + * we should at minimum have a struct for the display controller, since + * the chip supports two. + */ +struct soc_nvidia_tegra124_config { + int xres; + int yres; + int framebuffer_bits_per_pixel; + int cache_policy; + /* there are two. It's not unimaginable that we might someday + * have two of these structs in a single mainboard. + */ + u32 display_controller; + u32 framebuffer_base; + /* Technically, we can compute this. At the same time, some platforms + * might want to specify a specific size for their own reasons. If it is + * zero the soc code will compute it as xres*yres*framebuffer_bits_per_pixel/4 + */ + u32 framebuffer_size; + /* GPIOs -- all, some, or none are used. Unused ones can be ignored + * in devicetree.cb since if they are not set there they default to 0, + * and 0 for a gpio means 'unused GPIO'. + */ + gpio_t backlight_en_gpio; + gpio_t lvds_shutdown_gpio; + gpio_t backlight_vdd_gpio; + gpio_t panel_vdd_gpio; + + /* required info. */ + /* pwm to use to set display contrast */ + int pwm; + /* timings -- five numbers, all relative to the previous + * event, not to absolute time. e.g., vdd_data_delay is the + * delay from vdd on to data, not from power on to data. + * This is stated to be four timings in the + * u-boot docs. In any event, in coreboot, we generally + * only delay long enough to let the panel wake up and then + * do the control operations -- meaming, for *coreboot* + * we probably only need the vdd_delay, but payloads may + * need the other info. + */ + /* Delay before from power on asserting vdd */ + int vdd_delay; + /* delay between panel_vdd-rise and data-rise*/ + int vdd_data_delay; + /* delay between data-rise and backlight_vdd-rise */ + int data_backlight_delay; + /* delay between backlight_vdd and pwm-rise */ + int backlight_pwm_delay; + /* delay between pwm-rise and backlight_en-rise */ + int pwm_backlight_en_delay; + /* display timing. + * we have not found a dts in which these are set */ + int href_to_sync; /* u-boot code says 'set to 1' */ + int hsync_width; + int hback_porch; + int hfront_porch; + int vref_to_sync; /* u-boot code says 'set to 1' */ + int vsync_width; + int vback_porch; + int vfront_porch; + + int pixel_clock; +}; + +#endif /* __SOC_NVIDIA_TEGRA124_CHIP_H__ */ diff --git a/src/soc/nvidia/tegra124/clk_rst.h b/src/soc/nvidia/tegra124/clk_rst.h index badb58b..4280f3c 100644 --- a/src/soc/nvidia/tegra124/clk_rst.h +++ b/src/soc/nvidia/tegra124/clk_rst.h @@ -17,203 +17,275 @@ #ifndef _TEGRA124_CLK_RST_H_ #define _TEGRA124_CLK_RST_H_ -/* PLL registers - there are several PLLs in the clock controller */ -struct clk_pll { - u32 pll_base; /* the control register */ - /* pll_out[0] is output A control, pll_out[1] is output B control */ - u32 pll_out[2]; - u32 pll_misc; /* other misc things */ -}; - -/* PLL registers - there are several PLLs in the clock controller */ -struct clk_pll_simple { - u32 pll_base; /* the control register */ - u32 pll_misc; /* other misc things */ -}; - -struct clk_pllm { - u32 pllm_base; /* the control register */ - u32 pllm_out; /* output control */ - u32 pllm_misc1; /* misc1 */ - u32 pllm_misc2; /* misc2 */ -}; - -/* RST_DEV_(L,H,U,V,W)_(SET,CLR) and CLK_ENB_(L,H,U,V,W)_(SET,CLR) */ -struct clk_set_clr { - u32 set; - u32 clr; -}; - -/* - * Most PLLs use the clk_pll structure, but some have a simpler two-member - * structure for which we use clk_pll_simple. The reason for this non- - * othogonal setup is not stated. - */ -enum { - TEGRA_CLK_PLLS = 6, /* Number of normal PLLs */ - TEGRA_CLK_SIMPLE_PLLS = 3, /* Number of simple PLLs */ - TEGRA_CLK_REGS = 3, /* Number of clock enable regs L/H/U */ - TEGRA_CLK_SOURCES = 64, /* Number of ppl clock sources L/H/U */ - TEGRA_CLK_REGS_VW = 2, /* Number of clock enable regs V/W */ - TEGRA_CLK_SOURCES_VW = 32, /* Number of ppl clock sources V/W */ - TEGRA_CLK_SOURCES_X = 32, /* Number of ppl clock sources X */ -}; - /* Clock/Reset Controller (CLK_RST_CONTROLLER_) regs */ -struct clk_rst_ctlr { - u32 crc_rst_src; /* _RST_SOURCE_0,0x00 */ - u32 crc_rst_dev[TEGRA_CLK_REGS]; /* _RST_DEVICES_L/H/U_0 */ - u32 crc_clk_out_enb[TEGRA_CLK_REGS]; /* _CLK_OUT_ENB_L/H/U_0 */ - u32 crc_reserved0; /* reserved_0, 0x1C */ - u32 crc_cclk_brst_pol; /* _CCLK_BURST_POLICY_0, 0x20 */ - u32 crc_super_cclk_div; /* _SUPER_CCLK_DIVIDER_0,0x24 */ - u32 crc_sclk_brst_pol; /* _SCLK_BURST_POLICY_0, 0x28 */ - u32 crc_super_sclk_div; /* _SUPER_SCLK_DIVIDER_0,0x2C */ - u32 crc_clk_sys_rate; /* _CLK_SYSTEM_RATE_0, 0x30 */ - u32 crc_reserved01; /* reserved_0_1, 0x34 */ - u32 crc_reserved02; /* reserved_0_2, 0x38 */ - u32 crc_reserved1; /* reserved_1, 0x3C */ - u32 crc_cop_clk_skip_plcy; /* _COP_CLK_SKIP_POLICY_0,0x40 */ - u32 crc_clk_mask_arm; /* _CLK_MASK_ARM_0, 0x44 */ - u32 crc_misc_clk_enb; /* _MISC_CLK_ENB_0, 0x48 */ - u32 crc_clk_cpu_cmplx; /* _CLK_CPU_CMPLX_0, 0x4C */ - u32 crc_osc_ctrl; /* _OSC_CTRL_0, 0x50 */ - u32 crc_pll_lfsr; /* _PLL_LFSR_0, 0x54 */ - u32 crc_osc_freq_det; /* _OSC_FREQ_DET_0, 0x58 */ - u32 crc_osc_freq_det_stat; /* _OSC_FREQ_DET_STATUS_0,0x5C */ - u32 crc_reserved2[8]; /* reserved_2[8], 0x60-7C */ - - struct clk_pll crc_pll[TEGRA_CLK_PLLS]; /* PLLs from 0x80 to 0xdc */ - - /* PLLs from 0xe0 to 0xf4 */ - struct clk_pll_simple crc_pll_simple[TEGRA_CLK_SIMPLE_PLLS]; - - u32 crc_reserved10; /* _reserved_10, 0xF8 */ - u32 crc_reserved11; /* _reserved_11, 0xFC */ - - u32 crc_clk_src[TEGRA_CLK_SOURCES]; /*_I2S1_0... 0x100-1fc */ - - u32 crc_reserved20[32]; /* _reserved_20, 0x200-27c */ - - u32 crc_clk_out_enb_x; /* _CLK_OUT_ENB_X_0, 0x280 */ - u32 crc_clk_enb_x_set; /* _CLK_ENB_X_SET_0, 0x284 */ - u32 crc_clk_enb_x_clr; /* _CLK_ENB_X_CLR_0, 0x288 */ - - u32 crc_rst_devices_x; /* _RST_DEVICES_X_0, 0x28c */ - u32 crc_rst_dev_x_set; /* _RST_DEV_X_SET_0, 0x290 */ - u32 crc_rst_dev_x_clr; /* _RST_DEV_X_CLR_0, 0x294 */ - - u32 crc_reserved21[23]; /* _reserved_21, 0x298-2f0 */ - - u32 crc_dfll_base; /* _DFLL_BASE_0, 0x2f4 */ - - u32 crc_reserved22[2]; /* _reserved_22, 0x2f8-2fc */ - - /* _RST_DEV_L/H/U_SET_0 0x300 ~ 0x314 */ - struct clk_set_clr crc_rst_dev_ex[TEGRA_CLK_REGS]; - - u32 crc_reserved30[2]; /* _reserved_30, 0x318, 0x31c */ - - /* _CLK_ENB_L/H/U_CLR_0 0x320 ~ 0x334 */ - struct clk_set_clr crc_clk_enb_ex[TEGRA_CLK_REGS]; - - u32 crc_reserved31; /* _reserved_31, 0x338 */ - - u32 crc_ccplex_pg_sm_ovrd; /* _CCPLEX_PG_SM_OVRD_0, 0x33c */ - - u32 crc_rst_cpu_cmplx_set; /* _RST_CPU_CMPLX_SET_0, 0x340 */ - u32 crc_rst_cpu_cmplx_clr; /* _RST_CPU_CMPLX_CLR_0, 0x344 */ - u32 crc_clk_cpu_cmplx_set; /* _CLK_CPU_CMPLX_SET_0, 0x348 */ - u32 crc_clk_cpu_cmplx_clr; /* _CLK_CPU_CMPLX_SET_0, 0x34c */ - - u32 crc_reserved32[2]; /* _reserved_32, 0x350,0x354 */ - - u32 crc_rst_dev_vw[TEGRA_CLK_REGS_VW]; /* _RST_DEVICES_V/W_0 */ - u32 crc_clk_out_enb_vw[TEGRA_CLK_REGS_VW]; /* _CLK_OUT_ENB_V/W_0 */ - u32 crc_cclkg_brst_pol; /* _CCLKG_BURST_POLICY_0, 0x368 */ - u32 crc_super_cclkg_div; /* _SUPER_CCLKG_DIVIDER_0, 0x36C */ - u32 crc_cclklp_brst_pol; /* _CCLKLP_BURST_POLICY_0, 0x370 */ - u32 crc_super_cclkp_div; /* _SUPER_CCLKLP_DIVIDER_0, 0x374 */ - u32 crc_clk_cpug_cmplx; /* _CLK_CPUG_CMPLX_0, 0x378 */ - u32 crc_clk_cpulp_cmplx; /* _CLK_CPULP_CMPLX_0, 0x37C */ - u32 crc_cpu_softrst_ctrl; /* _CPU_SOFTRST_CTRL_0, 0x380 */ - u32 crc_cpu_softrst_ctrl1; /* _CPU_SOFTRST_CTRL1_0, 0x384 */ - u32 crc_cpu_softrst_ctrl2; /* _CPU_SOFTRST_CTRL2_0, 0x388 */ - u32 crc_reserved33[9]; /* _reserved_33, 0x38c-3ac */ - u32 crc_clk_src_vw[TEGRA_CLK_SOURCES_VW]; /* 0x3B0-0x42C */ - /* _RST_DEV_V/W_SET_0 0x430 ~ 0x43c */ - struct clk_set_clr crc_rst_dev_ex_vw[TEGRA_CLK_REGS_VW]; - /* _CLK_ENB_V/W_CLR_0 0x440 ~ 0x44c */ - struct clk_set_clr crc_clk_enb_ex_vw[TEGRA_CLK_REGS_VW]; - u32 crc_rst_cpug_cmplx_set; /* _RST_CPUG_CMPLX_SET_0, 0x450*/ - u32 crc_rst_cpug_cmplx_clr; /* _RST_CPUG_CMPLX_CLR_0, 0x454*/ - u32 crc_rst_cpulp_cmplx_set; /* _RST_CPULP_CMPLX_SET_0, 0x458*/ - u32 crc_rst_cpulp_cmplx_clr; /* _RST_CPULP_CMPLX_CLR_0, 0x45C*/ - u32 crc_clk_cpug_cmplx_set; /* _CLK_CPUG_CMPLX_SET_0, 0x460 */ - u32 crc_clk_cpug_cmplx_clr; /* _CLK_CPUG_CMPLX_CLR_0, 0x464 */ - u32 crc_clk_cpulp_cmplx_set; /* _CLK_CPULP_CMPLX_SET_0, 0x468 */ - u32 crc_clk_cpulp_cmplx_clr; /* _CLK_CPULP_CMPLX_CLR_0, 0x46C */ - u32 crc_cpu_cmplx_status; /* _CPU_CMPLX_STATUS_0, 0x470 */ - u32 crc_reserved40[1]; /* _reserved_40, 0x474 */ - u32 crc_intstatus; /* __INTSTATUS_0, 0x478 */ - u32 crc_intmask; /* __INTMASK_0, 0x47C */ - u32 crc_utmip_pll_cfg0; /* _UTMIP_PLL_CFG0_0, 0x480 */ - u32 crc_utmip_pll_cfg1; /* _UTMIP_PLL_CFG1_0, 0x484 */ - u32 crc_utmip_pll_cfg2; /* _UTMIP_PLL_CFG2_0, 0x488 */ - - u32 crc_plle_aux; /* _PLLE_AUX_0, 0x48C */ - u32 crc_sata_pll_cfg0; /* _SATA_PLL_CFG0_0, 0x490 */ - u32 crc_sata_pll_cfg1; /* _SATA_PLL_CFG1_0, 0x494 */ - u32 crc_pcie_pll_cfg0; /* _PCIE_PLL_CFG0_0, 0x498 */ - - u32 crc_prog_audio_dly_clk; /* _PROG_AUDIO_DLY_CLK_0, 0x49C */ - u32 crc_audio_sync_clk_i2s0; /* _AUDIO_SYNC_CLK_I2S0_0, 0x4A0 */ - u32 crc_audio_sync_clk_i2s1; /* _AUDIO_SYNC_CLK_I2S1_0, 0x4A4 */ - u32 crc_audio_sync_clk_i2s2; /* _AUDIO_SYNC_CLK_I2S2_0, 0x4A8 */ - u32 crc_audio_sync_clk_i2s3; /* _AUDIO_SYNC_CLK_I2S3_0, 0x4AC */ - u32 crc_audio_sync_clk_i2s4; /* _AUDIO_SYNC_CLK_I2S4_0, 0x4B0 */ - u32 crc_audio_sync_clk_spdif; /* _AUDIO_SYNC_CLK_SPDIF_0, 0x4B4 */ - - u32 crc_plld2_base; /* _PLLD2_BASE_0, 0x4B8 */ - u32 crc_plld2_misc; /* _PLLD2_MISC_0, 0x4BC */ - u32 crc_utmip_pll_cfg3; /* _UTMIP_PLL_CFG3_0, 0x4C0 */ - u32 crc_pllrefe_base; /* _PLLREFE_BASE_0, 0x4C4 */ - u32 crc_pllrefe_misc; /* _PLLREFE_MISC_0, 0x4C8 */ - u32 crs_reserved_50[7]; /* _reserved_50, 0x4CC-0x4E4 */ - u32 crc_pllc2_base; /* _PLLC2_BASE_0, 0x4E8 */ - u32 crc_pllc2_misc0; /* _PLLC2_MISC_0_0, 0x4EC */ - u32 crc_pllc2_misc1; /* _PLLC2_MISC_1_0, 0x4F0 */ - u32 crc_pllc2_misc2; /* _PLLC2_MISC_2_0, 0x4F4 */ - u32 crc_pllc2_misc3; /* _PLLC2_MISC_3_0, 0x4F8 */ - u32 crc_pllc3_base; /* _PLLC3_BASE_0, 0x4FC */ - u32 crc_pllc3_misc0; /* _PLLC3_MISC_0_0, 0x500 */ - u32 crc_pllc3_misc1; /* _PLLC3_MISC_1_0, 0x504 */ - u32 crc_pllc3_misc2; /* _PLLC3_MISC_2_0, 0x508 */ - u32 crc_pllc3_misc3; /* _PLLC3_MISC_3_0, 0x50C */ - u32 crc_pllx_misc1; /* _PLLX_MISC_1_0, 0x510 */ - u32 crc_pllx_misc2; /* _PLLX_MISC_2_0, 0x514 */ - u32 crc_pllx_misc3; /* _PLLX_MISC_3_0, 0x518 */ - u32 crc_xusbio_pll_cfg0; /* _XUSBIO_PLL_CFG0_0, 0x51C */ - u32 crc_xusbio_pll_cfg1; /* _XUSBIO_PLL_CFG0_1, 0x520 */ - u32 crc_plle_aux1; /* _PLLE_AUX1_0, 0x524 */ - u32 crc_pllp_reshift; /* _PLLP_RESHIFT_0, 0x528 */ - u32 crc_utmipll_hw_pwrdn_cfg0; /* _UTMIPLL_HW_PWRDN_CFG0_0, 0x52C */ - u32 crc_pllu_hw_pwrdn_cfg0; /* _PLLU_HW_PWRDN_CFG0_0, 0x530 */ - u32 crc_xusb_pll_cfg0; /* _XUSB_PLL_CFG0_0, 0x534 */ - u32 crc_reserved51[1]; /* _reserved_51, 0x538 */ - u32 crc_clk_cpu_misc; /* _CLK_CPU_MISC_0, 0x53C */ - u32 crc_clk_cpug_misc; /* _CLK_CPUG_MISC_0, 0x540 */ - u32 crc_clk_cpulp_misc; /* _CLK_CPULP_MISC_0, 0x544 */ - u32 crc_pllx_hw_ctrl_cfg; /* _PLLX_HW_CTRL_CFG_0, 0x548 */ - u32 crc_pllx_sw_ramp_cfg; /* _PLLX_SW_RAMP_CFG_0, 0x54C */ - u32 crc_pllx_hw_ctrl_status; /* _PLLX_HW_CTRL_STATUS_0, 0x550 */ - u32 crc_reserved52[1]; /* _reserved_52, 0x554 */ - u32 crc_super_gr3d_clk_div; /* _SUPER_GR3D_CLK_DIVIDER_0, 0x558 */ - u32 crc_spare_reg0; /* _SPARE_REG0_0, 0x55C */ - - /* T124 - skip to 0x600 here for new CLK_SOURCE_ regs */ - u32 crc_reserved60[40]; /* _reserved_60, 0x560 - 0x5FC */ - u32 crc_clk_src_x[TEGRA_CLK_SOURCES_X]; /* XUSB, etc, 0x600-0x678 */ +struct __attribute__ ((__packed__)) clk_rst_ctlr { + u32 rst_src; /* _RST_SOURCE, 0x000 */ + u32 rst_dev_l; /* _RST_DEVICES_L, 0x004 */ + u32 rst_dev_h; /* _RST_DEVICES_H, 0x008 */ + u32 rst_dev_u; /* _RST_DEVICES_U, 0x00c */ + u32 clk_out_enb_l; /* _CLK_OUT_ENB_L, 0x010 */ + u32 clk_out_enb_h; /* _CLK_OUT_ENB_H, 0x014 */ + u32 clk_out_enb_u; /* _CLK_OUT_ENB_U, 0x018 */ + u32 _rsv0; /* 0x01c */ + u32 cclk_brst_pol; /* _CCLK_BURST_POLICY, 0x020 */ + u32 super_cclk_div; /* _SUPER_CCLK_DIVIDER, 0x024 */ + u32 sclk_brst_pol; /* _SCLK_BURST_POLICY, 0x028 */ + u32 super_sclk_div; /* _SUPER_SCLK_DIVIDER, 0x02C */ + u32 clk_sys_rate; /* _CLK_SYSTEM_RATE, 0x030 */ + u32 _rsv1[3]; /* 0x034-03c */ + u32 cop_clk_skip_plcy; /* _COP_CLK_SKIP_POLICY, 0x040 */ + u32 clk_mask_arm; /* _CLK_MASK_ARM, 0x044 */ + u32 misc_clk_enb; /* _MISC_CLK_ENB, 0x048 */ + u32 clk_cpu_cmplx; /* _CLK_CPU_CMPLX, 0x04C */ + u32 osc_ctrl; /* _OSC_CTRL, 0x050 */ + u32 pll_lfsr; /* _PLL_LFSR, 0x054 */ + u32 osc_freq_det; /* _OSC_FREQ_DET, 0x058 */ + u32 osc_freq_det_stat; /* _OSC_FREQ_DET_STATUS, 0x05C */ + u32 _rsv2[8]; /* 0x060-07C */ + u32 pllc_base; /* _PLLC_BASE, 0x080 */ + u32 pllc_out; /* _PLLC_OUT, 0x084 */ + u32 pllc_misc2; /* _PLLC_MISC2, 0x088 */ + u32 pllc_misc; /* _PLLC_MISC, 0x08c */ + u32 pllm_base; /* _PLLM_BASE, 0x090 */ + u32 pllm_out; /* _PLLM_OUT, 0x094 */ + u32 pllm_misc1; /* _PLLM_MISC1, 0x098 */ + u32 pllm_misc2; /* _PLLM_MISC2, 0x09c */ + u32 pllp_base; /* _PLLP_BASE, 0x0a0 */ + u32 pllp_outa; /* _PLLP_OUTA, 0x0a4 */ + u32 pllp_outb; /* _PLLP_OUTB, 0x0a8 */ + u32 pllp_misc; /* _PLLP_MISC, 0x0ac */ + u32 plla_base; /* _PLLA_BASE, 0x0b0 */ + u32 plla_out; /* _PLLA_OUT, 0x0b4 */ + u32 _rsv3; /* 0x0b8 */ + u32 plla_misc; /* _PLLA_MISC, 0x0bc */ + u32 pllu_base; /* _PLLU_BASE, 0x0c0 */ + u32 _rsv4[2]; /* 0x0c4-0c8 */ + u32 pllu_misc; /* _PLLU_MISC, 0x0cc */ + u32 plld_base; /* _PLLD_BASE, 0x0d0 */ + u32 _rsv5[2]; /* 0x0d4-0d8 */ + u32 plld_misc; /* _PLLD_MISC, 0x0dc */ + u32 pllx_base; /* _PLLX_BASE, 0x0e0 */ + u32 pllx_misc; /* _PLLX_MISC, 0x0e4 */ + u32 plle_base; /* _PLLE_BASE, 0x0e8 */ + u32 plle_misc; /* _PLLE_MISC, 0x0ec */ + u32 plls_base; /* _PLLS_BASE, 0x0f0 */ + u32 plls_misc; /* _PLLS_MISC, 0x0f4 */ + u32 _rsv6[2]; /* 0x0f8-0fc */ + u32 clk_src_i2s1; /* _CLK_SOURCE_I2S1, 0x100 */ + u32 clk_src_i2s2; /* _CLK_SOURCE_I2S2, 0x104 */ + u32 clk_src_spdif_out; /* _CLK_SOURCE_SPDIF_OUT, 0x108 */ + u32 clk_src_spdif_in; /* _CLK_SOURCE_SPDIF_IN, 0x10c */ + u32 clk_src_pwm; /* _CLK_SOURCE_PWM, 0x110 */ + u32 _rsv7; /* 0x114 */ + u32 clk_src_sbc2; /* _CLK_SOURCE_SBC2, 0x118 */ + u32 clk_src_sbc3; /* _CLK_SOURCE_SBC3, 0x11c */ + u32 _rsv8; /* 0x120 */ + u32 clk_src_i2c1; /* _CLK_SOURCE_I2C1, 0x124 */ + u32 clk_src_i2c5; /* _CLK_SOURCE_I2C5, 0x128 */ + u32 _rsv9[2]; /* 0x12c-130 */ + u32 clk_src_sbc1; /* _CLK_SOURCE_SBC1, 0x134 */ + u32 clk_src_disp1; /* _CLK_SOURCE_DISP1, 0x138 */ + u32 clk_src_disp2; /* _CLK_SOURCE_DISP2, 0x13c */ + u32 _rsv10[2]; /* 0x140-144 */ + u32 clk_src_vi; /* _CLK_SOURCE_VI, 0x148 */ + u32 _rsv11; /* 0x14c */ + u32 clk_src_sdmmc1; /* _CLK_SOURCE_SDMMC1, 0x150 */ + u32 clk_src_sdmmc2; /* _CLK_SOURCE_SDMMC2, 0x154 */ + u32 clk_src_g3d; /* _CLK_SOURCE_G3D, 0x158 */ + u32 clk_src_g2d; /* _CLK_SOURCE_G2D, 0x15c */ + u32 clk_src_ndflash; /* _CLK_SOURCE_NDFLASH, 0x160 */ + u32 clk_src_sdmmc4; /* _CLK_SOURCE_SDMMC4, 0x164 */ + u32 clk_src_vfir; /* _CLK_SOURCE_VFIR, 0x168 */ + u32 clk_src_epp; /* _CLK_SOURCE_EPP, 0x16c */ + u32 clk_src_mpe; /* _CLK_SOURCE_MPE, 0x170 */ + u32 clk_src_hsi; /* _CLK_SOURCE_HSI, 0x174 */ + u32 clk_src_uarta; /* _CLK_SOURCE_UARTA, 0x178 */ + u32 clk_src_uartb; /* _CLK_SOURCE_UARTB, 0x17c */ + u32 clk_src_host1x; /* _CLK_SOURCE_HOST1X, 0x180 */ + u32 _rsv12[2]; /* 0x184-188 */ + u32 clk_src_hdmi; /* _CLK_SOURCE_HDMI, 0x18c */ + u32 _rsv13[2]; /* 0x190-194 */ + u32 clk_src_i2c2; /* _CLK_SOURCE_I2C2, 0x198 */ + u32 clk_src_emc; /* _CLK_SOURCE_EMC, 0x19c */ + u32 clk_src_uartc; /* _CLK_SOURCE_UARTC, 0x1a0 */ + u32 _rsv14; /* 0x1a4 */ + u32 clk_src_vi_sensor; /* _CLK_SOURCE_VI_SENSOR, 0x1a8 */ + u32 _rsv15[2]; /* 0x1ac-1b0 */ + u32 clk_src_sbc4; /* _CLK_SOURCE_SBC4, 0x1b4 */ + u32 clk_src_i2c3; /* _CLK_SOURCE_I2C3, 0x1b8 */ + u32 clk_src_sdmmc3; /* _CLK_SOURCE_SDMMC3, 0x1bc */ + u32 clk_src_uartd; /* _CLK_SOURCE_UARTD, 0x1c0 */ + u32 clk_src_uarte; /* _CLK_SOURCE_UARTE, 0x1c4 */ + u32 clk_src_vde; /* _CLK_SOURCE_VDE, 0x1c8 */ + u32 clk_src_owr; /* _CLK_SOURCE_OWR, 0x1cc */ + u32 clk_src_nor; /* _CLK_SOURCE_NOR, 0x1d0 */ + u32 clk_src_csite; /* _CLK_SOURCE_CSITE, 0x1d4 */ + u32 clk_src_i2s0; /* _CLK_SOURCE_I2S0, 0x1d8 */ + u32 clk_src_dtv; /* _CLK_SOURCE_DTV, 0x1dc */ + u32 _rsv16[4]; /* 0x1e0-1ec */ + u32 clk_src_msenc; /* _CLK_SOURCE_MSENC, 0x1f0 */ + u32 clk_src_tsec; /* _CLK_SOURCE_TSEC, 0x1f4 */ + u32 _rsv17; /* 0x1f8 */ + u32 clk_src_osc; /* _CLK_SOURCE_OSC, 0x1fc */ + u32 _rsv18[32]; /* 0x200-27c */ + u32 clk_out_enb_x; /* _CLK_OUT_ENB_X_0, 0x280 */ + u32 clk_enb_x_set; /* _CLK_ENB_X_SET_0, 0x284 */ + u32 clk_enb_x_clr; /* _CLK_ENB_X_CLR_0, 0x288 */ + u32 rst_devices_x; /* _RST_DEVICES_X_0, 0x28c */ + u32 rst_dev_x_set; /* _RST_DEV_X_SET_0, 0x290 */ + u32 rst_dev_x_clr; /* _RST_DEV_X_CLR_0, 0x294 */ + u32 _rsv19[23]; /* 0x298-2f0 */ + u32 dfll_base; /* _DFLL_BASE_0, 0x2f4 */ + u32 _rsv20[2]; /* 0x2f8-2fc */ + u32 rst_dev_l_set; /* _RST_DEV_L_SET 0x300 */ + u32 rst_dev_l_clr; /* _RST_DEV_L_CLR 0x304 */ + u32 rst_dev_h_set; /* _RST_DEV_H_SET 0x308 */ + u32 rst_dev_h_clr; /* _RST_DEV_H_CLR 0x30c */ + u32 rst_dev_u_set; /* _RST_DEV_U_SET 0x310 */ + u32 rst_dev_u_clr; /* _RST_DEV_U_CLR 0x314 */ + u32 _rsv21[2]; /* 0x318-31c */ + u32 clk_enb_l_set; /* _CLK_ENB_L_SET 0x320 */ + u32 clk_enb_l_clr; /* _CLK_ENB_L_CLR 0x324 */ + u32 clk_enb_h_set; /* _CLK_ENB_H_SET 0x328 */ + u32 clk_enb_h_clr; /* _CLK_ENB_H_CLR 0x32c */ + u32 clk_enb_u_set; /* _CLK_ENB_U_SET 0x330 */ + u32 clk_enb_u_clk; /* _CLK_ENB_U_CLR 0x334 */ + u32 _rsv22; /* 0x338 */ + u32 ccplex_pg_sm_ovrd; /* _CCPLEX_PG_SM_OVRD, 0x33c */ + u32 rst_cpu_cmplx_set; /* _RST_CPU_CMPLX_SET, 0x340 */ + u32 rst_cpu_cmplx_clr; /* _RST_CPU_CMPLX_CLR, 0x344 */ + u32 clk_cpu_cmplx_set; /* _CLK_CPU_CMPLX_SET, 0x348 */ + u32 clk_cpu_cmplx_clr; /* _CLK_CPU_CMPLX_SET, 0x34c */ + u32 _rsv23[2]; /* 0x350-354 */ + u32 rst_dev_v; /* _RST_DEVICES_V, 0x358 */ + u32 rst_dev_w; /* _RST_DEVICES_W, 0x35c */ + u32 clk_out_enb_v; /* _CLK_OUT_ENB_V, 0x360 */ + u32 clk_out_enb_w; /* _CLK_OUT_ENB_W, 0x364 */ + u32 cclkg_brst_pol; /* _CCLKG_BURST_POLICY, 0x368 */ + u32 super_cclkg_div; /* _SUPER_CCLKG_DIVIDER, 0x36c */ + u32 cclklp_brst_pol; /* _CCLKLP_BURST_POLICY, 0x370 */ + u32 super_cclkp_div; /* _SUPER_CCLKLP_DIVIDER, 0x374 */ + u32 clk_cpug_cmplx; /* _CLK_CPUG_CMPLX, 0x378 */ + u32 clk_cpulp_cmplx; /* _CLK_CPULP_CMPLX, 0x37c */ + u32 cpu_softrst_ctrl; /* _CPU_SOFTRST_CTRL, 0x380 */ + u32 cpu_softrst_ctrl1; /* _CPU_SOFTRST_CTRL1, 0x384 */ + u32 cpu_softrst_ctrl2; /* _CPU_SOFTRST_CTRL2, 0x388 */ + u32 _rsv24[9]; /* 0x38c-3ac */ + u32 clk_src_g3d2; /* _CLK_SOURCE_G3D2, 0x3b0 */ + u32 clk_src_mselect; /* _CLK_SOURCE_MSELECT, 0x3b4 */ + u32 clk_src_tsensor; /* _CLK_SOURCE_TSENSOR, 0x3b8 */ + u32 clk_src_i2s3; /* _CLK_SOURCE_I2S3, 0x3bc */ + u32 clk_src_i2s4; /* _CLK_SOURCE_I2S4, 0x3c0 */ + u32 clk_src_i2c4; /* _CLK_SOURCE_I2C4, 0x3c4 */ + u32 clk_src_sbc5; /* _CLK_SOURCE_SBC5, 0x3c8 */ + u32 clk_src_sbc6; /* _CLK_SOURCE_SBC6, 0x3cc */ + u32 clk_src_audio; /* _CLK_SOURCE_AUDIO, 0x3d0 */ + u32 _rsv25; /* 0x3d4 */ + u32 clk_src_dam0; /* _CLK_SOURCE_DAM0, 0x3d8 */ + u32 clk_src_dam1; /* _CLK_SOURCE_DAM1, 0x3dc */ + u32 clk_src_dam2; /* _CLK_SOURCE_DAM2, 0x3e0 */ + u32 clk_src_hda2codec_2x; /* _CLK_SOURCE_HDA2CODEC_2X,0x3e4 */ + u32 clk_src_actmon; /* _CLK_SOURCE_ACTMON, 0x3e8 */ + u32 clk_src_extperiph1; /* _CLK_SOURCE_EXTPERIPH1, 0x3ec */ + u32 clk_src_extperiph2; /* _CLK_SOURCE_EXTPERIPH2, 0x3f0 */ + u32 clk_src_extperiph3; /* _CLK_SOURCE_EXTPERIPH3, 0x3f4 */ + u32 clk_src_nand_speed; /* _CLK_SOURCE_NAND_SPEED, 0x3f8 */ + u32 clk_src_i2c_slow; /* _CLK_SOURCE_I2C_SLOW, 0x3fc */ + u32 clk_src_sys; /* _CLK_SOURCE_SYS, 0x400 */ + u32 _rsv26[7]; /* 0x404-41c */ + u32 clk_src_sata_oob; /* _CLK_SOURCE_SATA_OOB, 0x420 */ + u32 clk_src_sata; /* _CLK_SOURCE_SATA, 0x424 */ + u32 clk_src_hda; /* _CLK_SOURCE_HDA, 0x428 */ + u32 _rsv27; /* 0x42c */ + u32 rst_dev_v_set; /* _RST_DEV_V_SET, 0x430 */ + u32 rst_dev_v_clr; /* _RST_DEV_V_CLR, 0x434 */ + u32 rst_dev_w_set; /* _RST_DEV_W_SET, 0x438 */ + u32 rst_dev_w_clr; /* _RST_DEV_W_CLR, 0x43c */ + u32 clk_enb_v_set; /* _CLK_ENB_V_SET, 0x440 */ + u32 clk_enb_v_clr; /* _CLK_ENB_V_CLR, 0x444 */ + u32 clk_enb_w_set; /* _CLK_ENB_W_SET, 0x448 */ + u32 clk_enb_w_clr; /* _CLK_ENB_W_CLR, 0x44c */ + u32 rst_cpug_cmplx_set; /* _RST_CPUG_CMPLX_SET, 0x450 */ + u32 rst_cpug_cmplx_clr; /* _RST_CPUG_CMPLX_CLR, 0x454 */ + u32 rst_cpulp_cmplx_set; /* _RST_CPULP_CMPLX_SET, 0x458 */ + u32 rst_cpulp_cmplx_clr; /* _RST_CPULP_CMPLX_CLR, 0x45C */ + u32 clk_cpug_cmplx_set; /* _CLK_CPUG_CMPLX_SET, 0x460 */ + u32 clk_cpug_cmplx_clr; /* _CLK_CPUG_CMPLX_CLR, 0x464 */ + u32 clk_cpulp_cmplx_set; /* _CLK_CPULP_CMPLX_SET, 0x468 */ + u32 clk_cpulp_cmplx_clr; /* _CLK_CPULP_CMPLX_CLR, 0x46c */ + u32 cpu_cmplx_status; /* _CPU_CMPLX_STATUS, 0x470 */ + u32 _rsv28; /* 0x474 */ + u32 intstatus; /* _INTSTATUS, 0x478 */ + u32 intmask; /* _INTMASK, 0x47c */ + u32 utmip_pll_cfg0; /* _UTMIP_PLL_CFG0, 0x480 */ + u32 utmip_pll_cfg1; /* _UTMIP_PLL_CFG1, 0x484 */ + u32 utmip_pll_cfg2; /* _UTMIP_PLL_CFG2, 0x488 */ + u32 plle_aux; /* _PLLE_AUX, 0x48c */ + u32 sata_pll_cfg0; /* _SATA_PLL_CFG0, 0x490 */ + u32 sata_pll_cfg1; /* _SATA_PLL_CFG1, 0x494 */ + u32 pcie_pll_cfg0; /* _PCIE_PLL_CFG0, 0x498 */ + u32 prog_audio_dly_clk; /* _PROG_AUDIO_DLY_CLK, 0x49c */ + u32 audio_sync_clk_i2s0; /* _AUDIO_SYNC_CLK_I2S0, 0x4a0 */ + u32 audio_sync_clk_i2s1; /* _AUDIO_SYNC_CLK_I2S1, 0x4a4 */ + u32 audio_sync_clk_i2s2; /* _AUDIO_SYNC_CLK_I2S2, 0x4a8 */ + u32 audio_sync_clk_i2s3; /* _AUDIO_SYNC_CLK_I2S3, 0x4ac */ + u32 audio_sync_clk_i2s4; /* _AUDIO_SYNC_CLK_I2S4, 0x4b0 */ + u32 audio_sync_clk_spdif; /* _AUDIO_SYNC_CLK_SPDIF, 0x4b4 */ + u32 plld2_base; /* _PLLD2_BASE, 0x4b8 */ + u32 plld2_misc; /* _PLLD2_MISC, 0x4bc */ + u32 utmip_pll_cfg3; /* _UTMIP_PLL_CFG3, 0x4c0 */ + u32 pllrefe_base; /* _PLLREFE_BASE, 0x4c4 */ + u32 pllrefe_misc; /* _PLLREFE_MISC, 0x4c8 */ + u32 _rsv29[7]; /* 0x4cc-4e4 */ + u32 pllc2_base; /* _PLLC2_BASE, 0x4e8 */ + u32 pllc2_misc0; /* _PLLC2_MISC_0, 0x4ec */ + u32 pllc2_misc1; /* _PLLC2_MISC_1, 0x4f0 */ + u32 pllc2_misc2; /* _PLLC2_MISC_2, 0x4f4 */ + u32 pllc2_misc3; /* _PLLC2_MISC_3, 0x4f8 */ + u32 pllc3_base; /* _PLLC3_BASE, 0x4fc */ + u32 pllc3_misc0; /* _PLLC3_MISC_0, 0x500 */ + u32 pllc3_misc1; /* _PLLC3_MISC_1, 0x504 */ + u32 pllc3_misc2; /* _PLLC3_MISC_2, 0x508 */ + u32 pllc3_misc3; /* _PLLC3_MISC_3, 0x50c */ + u32 pllx_misc1; /* _PLLX_MISC_1, 0x510 */ + u32 pllx_misc2; /* _PLLX_MISC_2, 0x514 */ + u32 pllx_misc3; /* _PLLX_MISC_3, 0x518 */ + u32 xusbio_pll_cfg0; /* _XUSBIO_PLL_CFG0, 0x51c */ + u32 xusbio_pll_cfg1; /* _XUSBIO_PLL_CFG1, 0x520 */ + u32 plle_aux1; /* _PLLE_AUX1, 0x524 */ + u32 pllp_reshift; /* _PLLP_RESHIFT, 0x528 */ + u32 utmipll_hw_pwrdn_cfg0; /* _UTMIPLL_HW_PWRDN_CFG0, 0x52c */ + u32 pllu_hw_pwrdn_cfg0; /* _PLLU_HW_PWRDN_CFG0, 0x530 */ + u32 xusb_pll_cfg0; /* _XUSB_PLL_CFG0, 0x534 */ + u32 _rsv30; /* 0x538 */ + u32 clk_cpu_misc; /* _CLK_CPU_MISC, 0x53c */ + u32 clk_cpug_misc; /* _CLK_CPUG_MISC, 0x540 */ + u32 clk_cpulp_misc; /* _CLK_CPULP_MISC, 0x544 */ + u32 pllx_hw_ctrl_cfg; /* _PLLX_HW_CTRL_CFG, 0x548 */ + u32 pllx_sw_ramp_cfg; /* _PLLX_SW_RAMP_CFG, 0x54c */ + u32 pllx_hw_ctrl_status; /* _PLLX_HW_CTRL_STATUS, 0x550 */ + u32 _rsv31; /* 0x554 */ + u32 super_gr3d_clk_div; /* _SUPER_GR3D_CLK_DIVIDER, 0x558 */ + u32 spare_reg0; /* _SPARE_REG0, 0x55c */ + u32 _rsv32[40]; /* 0x560-5fc */ + u32 clk_src_xusb_core_host; /* _CLK_SOURCE_XUSB_CORE_HOST 0x600 */ + u32 clk_src_xusb_falcon; /* _CLK_SOURCE_XUSB_FALCON 0x604 */ + u32 clk_src_xusb_fs; /* _CLK_SOURCE_XUSB_FS 0x608 */ + u32 clk_src_xusb_core_dev; /* _CLK_SOURCE_XUSB_CORE_DEV 0x60c */ + u32 clk_src_xusb_ss; /* _CLK_SOURCE_XUSB_SS 0x610 */ + u32 clk_src_cilab; /* _CLK_SOURCE_CILAB 0x614 */ + u32 clk_src_cilcd; /* _CLK_SOURCE_CILCD 0x618 */ + u32 clk_src_cile; /* _CLK_SOURCE_CILE 0x61c */ + u32 clk_src_dsia_lp; /* _CLK_SOURCE_DSIA_LP 0x620 */ + u32 clk_src_dsib_lp; /* _CLK_SOURCE_DSIB_LP 0x624 */ + u32 clk_src_entropy; /* _CLK_SOURCE_ENTROPY 0x628 */ + u32 clk_src_dvfs_ref; /* _CLK_SOURCE_DVFS_REF 0x62c */ + u32 clk_src_dvfs_soc; /* _CLK_SOURCE_DVFS_SOC 0x630 */ + u32 clk_src_traceclkin; /* _CLK_SOURCE_TRACECLKIN 0x634 */ + u32 clk_src_adx0; /* _CLK_SOURCE_ADX0 0x638 */ + u32 clk_src_amx0; /* _CLK_SOURCE_AMX0 0x63c */ + u32 clk_src_emc_latency; /* _CLK_SOURCE_EMC_LATENCY 0x640 */ + u32 clk_src_soc_therm; /* _CLK_SOURCE_SOC_THERM 0x644 */ }; #define TEGRA_DEV_L 0 @@ -254,31 +326,32 @@ struct clk_rst_ctlr { #define OSC_FREQ_OSC38P4 5 /* 38.4MHz */ #define OSC_FREQ_OSC48 9 /* 48.0MHz */ -/* CLK_RST_CONTROLLER_PLLx_BASE_0 */ -#define PLL_BYPASS_SHIFT 31 -#define PLL_BYPASS_MASK (1U << PLL_BYPASS_SHIFT) +/* CLK_RST_CONTROLLER_PLL*_BASE_0 */ +#define PLL_BASE_BYPASS (1U << 31) +#define PLL_BASE_ENABLE (1U << 30) +#define PLL_BASE_REF_DIS (1U << 29) +#define PLL_BASE_OVRRIDE (1U << 28) +#define PLL_BASE_LOCK (1U << 27) -#define PLL_ENABLE_SHIFT 30 -#define PLL_ENABLE_MASK (1U << PLL_ENABLE_SHIFT) +#define PLL_BASE_DIVP_SHIFT 20 +#define PLL_BASE_DIVP_MASK (7U << PLL_BASE_DIVP_SHIFT) -#define PLL_BASE_OVRRIDE_MASK (1U << 28) -#define PLL_BASE_LOCK_MASK (1U << 27) +#define PLL_BASE_DIVN_SHIFT 8 +#define PLL_BASE_DIVN_MASK (0x3ffU << PLL_BASE_DIVN_SHIFT) -#define PLL_DIVP_SHIFT 20 -#define PLL_DIVP_MASK (7U << PLL_DIVP_SHIFT) - -#define PLL_DIVN_SHIFT 8 -#define PLL_DIVN_MASK (0x3ffU << PLL_DIVN_SHIFT) - -#define PLL_DIVM_SHIFT 0 -#define PLL_DIVM_MASK (0x1f << PLL_DIVM_SHIFT) +#define PLL_BASE_DIVM_SHIFT 0 +#define PLL_BASE_DIVM_MASK (0x1f << PLL_BASE_DIVM_SHIFT) /* SPECIAL CASE: PLLM, PLLC and PLLX use different-sized fields here */ -#define PLLCMX_DIVP_MASK (0xfU << PLL_DIVP_SHIFT) -#define PLLCMX_DIVN_MASK (0xffU << PLL_DIVN_SHIFT) -#define PLLCMX_DIVM_MASK (0xffU << PLL_DIVM_SHIFT) +#define PLLCMX_BASE_DIVP_MASK (0xfU << PLL_BASE_DIVP_SHIFT) +#define PLLCMX_BASE_DIVN_MASK (0xffU << PLL_BASE_DIVN_SHIFT) +#define PLLCMX_BASE_DIVM_MASK (0xffU << PLL_BASE_DIVM_SHIFT) -/* CLK_RST_CONTROLLER_PLLx_OUTx_0 */ +/* Generic, indiscriminate divisor mask. May catch some innocent bystander bits + * on the side that we don't particularly care about. */ +#define PLL_BASE_DIV_MASK (0xffffff) + +/* CLK_RST_CONTROLLER_PLL*_OUT*_0 */ #define PLL_OUT_RSTN (1 << 0) #define PLL_OUT_CLKEN (1 << 1) #define PLL_OUT_OVRRIDE (1 << 2) @@ -293,21 +366,22 @@ struct clk_rst_ctlr { #define PLL_OUT2_RATIO_SHIFT 24 #define PLL_OUT2_RATIO_MASK (0xffU << PLL_OUT2_RATIO_SHIFT) -/* CLK_RST_CONTROLLER_PLLx_MISC_0 */ -#define PLL_DCCON_SHIFT 20 -#define PLL_DCCON_MASK (1U << PLL_DCCON_SHIFT) +/* CLK_RST_CONTROLLER_PLL*_MISC_0 */ +#define PLL_MISC_DCCON (1 << 20) -#define PLL_LOCK_ENABLE_SHIFT 18 -#define PLL_LOCK_ENABLE_MASK (1U << PLL_LOCK_ENABLE_SHIFT) +#define PLL_MISC_CPCON_SHIFT 8 +#define PLL_MISC_CPCON_MASK (0xfU << PLL_MISC_CPCON_SHIFT) -#define PLL_CPCON_SHIFT 8 -#define PLL_CPCON_MASK (15U << PLL_CPCON_SHIFT) +#define PLL_MISC_LFCON_SHIFT 4 +#define PLL_MISC_LFCON_MASK (0xfU << PLL_MISC_LFCON_SHIFT) -#define PLL_LFCON_SHIFT 4 -#define PLL_LFCON_MASK (15U << PLL_LFCON_SHIFT) +/* This bit is different all over the place. Oh joy... */ +#define PLLC_MISC_LOCK_ENABLE (1 << 24) +#define PLLUD_MISC_LOCK_ENABLE (1 << 22) +#define PLLPAXS_MISC_LOCK_ENABLE (1 << 18) +#define PLLE_MISC_LOCK_ENABLE (1 << 9) -#define PLLU_VCO_FREQ_SHIFT 20 -#define PLLU_VCO_FREQ_MASK (1U << PLLU_VCO_FREQ_SHIFT) +#define PLLU_MISC_VCO_FREQ (1 << 20) #define PLLP_OUT1_OVR (1 << 2) #define PLLP_OUT2_OVR (1 << 18) @@ -334,19 +408,6 @@ enum { IN_408_OUT_9_6_DIVISOR = 83, }; -/* CRC_PLLP_MISC_0 0xac */ -#define PLLP_MISC_PLLP_CPCON_8 (8 << 8) -#define PLLP_MISC_PLLP_LOCK_ENABLE (1 << 18) - -/* CRC_PLLU_BASE_0 0xc0 */ -#define PLLU_BYPASS_ENABLE (1 << 31) -#define PLLU_ENABLE_ENABLE (1 << 30) -#define PLLU_REF_DIS_REF_DISABLE (1 << 29) -#define PLLU_OVERRIDE_ENABLE (1 << 24) - -/* CRC_PLLU_MISC_0 0xcc */ -#define PLLU_LOCK_ENABLE_ENABLE (1 << 22) - /* PLLX_BASE_0 0xe0 */ #define PLLX_BASE_PLLX_ENABLE (1 << 30) @@ -371,17 +432,19 @@ enum { * get_periph_clock_source()) but it does not seem worth it since the code * already checks the ranges of values it is writing, in clk_get_divider(). */ -#define OUT_CLK_DIVISOR_SHIFT 0 -#define OUT_CLK_DIVISOR_MASK (0xffff << OUT_CLK_DIVISOR_SHIFT) +#define CLK_DIVISOR_SHIFT 0 +#define CLK_DIVISOR_MASK (0xffff << CLK_DIVISOR_SHIFT) -#define OUT_CLK_SOURCE_SHIFT 30 -#define OUT_CLK_SOURCE_MASK (3U << OUT_CLK_SOURCE_SHIFT) +#define CLK_SOURCE_SHIFT 30 +#define CLK_SOURCE_MASK (3U << CLK_SOURCE_SHIFT) -#define OUT_CLK_SOURCE3_SHIFT 29 -#define OUT_CLK_SOURCE3_MASK (7U << OUT_CLK_SOURCE3_SHIFT) +#define CLK_SOURCE3_SHIFT 29 +#define CLK_SOURCE3_MASK (7U << CLK_SOURCE3_SHIFT) -#define OUT_CLK_SOURCE4_SHIFT 28 -#define OUT_CLK_SOURCE4_MASK (15U << OUT_CLK_SOURCE4_SHIFT) +#define CLK_SOURCE4_SHIFT 28 +#define CLK_SOURCE4_MASK (15U << CLK_SOURCE4_SHIFT) + +#define CLK_UART_DIV_OVERRIDE (1 << 24) /* CLK_RST_CONTROLLER_SCLK_BURST_POLICY */ #define SCLK_SYS_STATE_SHIFT 28U @@ -449,33 +512,6 @@ enum { #define CLK_SYS_RATE_APB_RATE_SHIFT 0 #define CLK_SYS_RATE_APB_RATE_MASK (3 << CLK_SYS_RATE_AHB_RATE_SHIFT) -/* CLK_RST_CONTROLLER_RST_CPUxx_CMPLX_CLR 0x344 */ -#define CLR_CPURESET0 (1 << 0) -#define CLR_CPURESET1 (1 << 1) -#define CLR_CPURESET2 (1 << 2) -#define CLR_CPURESET3 (1 << 3) -#define CLR_DBGRESET0 (1 << 12) -#define CLR_DBGRESET1 (1 << 13) -#define CLR_DBGRESET2 (1 << 14) -#define CLR_DBGRESET3 (1 << 15) -#define CLR_CORERESET0 (1 << 16) -#define CLR_CORERESET1 (1 << 17) -#define CLR_CORERESET2 (1 << 18) -#define CLR_CORERESET3 (1 << 19) -#define CLR_CXRESET0 (1 << 20) -#define CLR_CXRESET1 (1 << 21) -#define CLR_CXRESET2 (1 << 22) -#define CLR_CXRESET3 (1 << 23) -#define CLR_L2RESET (1 << 24) -#define CLR_NONCPURESET (1 << 29) -#define CLR_PRESETDBG (1 << 30) - -/* CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR 0x34c */ -#define CLR_CPU3_CLK_STP (1 << 11) -#define CLR_CPU2_CLK_STP (1 << 10) -#define CLR_CPU1_CLK_STP (1 << 9) -#define CLR_CPU0_CLK_STP (1 << 8) - /* CRC_CLK_SOURCE_MSELECT_0 0x3b4 */ #define MSELECT_CLK_SRC_PLLP_OUT0 (0 << 29) @@ -494,4 +530,46 @@ enum { #define UTMIP_FORCE_PD_SAMP_B_POWERDOWN (1 << 2) #define UTMIP_FORCE_PD_SAMP_A_POWERDOWN (1 << 0) +// CCLK_BRST_POL +enum { + CRC_CCLK_BRST_POL_PLLX_OUT0 = 0x8, + CRC_CCLK_BRST_POL_CPU_STATE_RUN = 0x2 +}; + +// SUPER_CCLK_DIVIDER +enum { + CRC_SUPER_CCLK_DIVIDER_SUPER_CDIV_ENB = 1 << 31 +}; + +// CLK_CPU_CMPLX_CLR +enum { + CRC_CLK_CLR_CPU0_STP = 0x1 << 8, + CRC_CLK_CLR_CPU1_STP = 0x1 << 9, + CRC_CLK_CLR_CPU2_STP = 0x1 << 10, + CRC_CLK_CLR_CPU3_STP = 0x1 << 11 +}; + +// RST_CPUG_CMPLX_CLR +enum { + CRC_RST_CPUG_CLR_CPU0 = 0x1 << 0, + CRC_RST_CPUG_CLR_CPU1 = 0x1 << 1, + CRC_RST_CPUG_CLR_CPU2 = 0x1 << 2, + CRC_RST_CPUG_CLR_CPU3 = 0x1 << 3, + CRC_RST_CPUG_CLR_DBG0 = 0x1 << 12, + CRC_RST_CPUG_CLR_DBG1 = 0x1 << 13, + CRC_RST_CPUG_CLR_DBG2 = 0x1 << 14, + CRC_RST_CPUG_CLR_DBG3 = 0x1 << 15, + CRC_RST_CPUG_CLR_CORE0 = 0x1 << 16, + CRC_RST_CPUG_CLR_CORE1 = 0x1 << 17, + CRC_RST_CPUG_CLR_CORE2 = 0x1 << 18, + CRC_RST_CPUG_CLR_CORE3 = 0x1 << 19, + CRC_RST_CPUG_CLR_CX0 = 0x1 << 20, + CRC_RST_CPUG_CLR_CX1 = 0x1 << 21, + CRC_RST_CPUG_CLR_CX2 = 0x1 << 22, + CRC_RST_CPUG_CLR_CX3 = 0x1 << 23, + CRC_RST_CPUG_CLR_L2 = 0x1 << 24, + CRC_RST_CPUG_CLR_NONCPU = 0x1 << 29, + CRC_RST_CPUG_CLR_PDBG = 0x1 << 30, +}; + #endif /* _TEGRA124_CLK_RST_H_ */ diff --git a/src/soc/nvidia/tegra124/clock.c b/src/soc/nvidia/tegra124/clock.c index af01b56..9dce867 100644 --- a/src/soc/nvidia/tegra124/clock.c +++ b/src/soc/nvidia/tegra124/clock.c @@ -13,31 +13,368 @@ * You should have received a copy of the GNU General Public License * along with this program. If not, see <http://www.gnu.org/licenses/>. */ - +#include <console/console.h> #include <delay.h> #include <arch/io.h> #include <soc/addressmap.h> - +#include <soc/clock.h> #include "clk_rst.h" -#include "clock.h" +#include "cpug.h" +#include "flow.h" +#include "pmc.h" static struct clk_rst_ctlr *clk_rst = (void *)TEGRA_CLK_RST_BASE; -/* - * On poweron, AVP clock source (also called system clock) is set to PLLP_out0 - * with frequency set at 1MHz. Before initializing PLLP, we need to move the - * system clock's source to CLK_M temporarily. And then switch it to PLLP_out4 - * (204MHz) at a later time. +static struct flow_ctlr *flow = (void *)TEGRA_FLOW_BASE; +static struct tegra_pmc_regs *pmc = (void*)TEGRA_PMC_BASE; + +struct pll_dividers { + u32 n : 10; + u32 m : 8; + u32 p : 4; + u32 cpcon: 4; + u32 : 6; +}; + +/* Some PLLs have more restrictive divider bit lengths or are missing some + * fields. Make sure to use the right struct in the osc_table definition to get + * compile-time checking, but keep the bits aligned with struct pll_dividers so + * they can be used interchangeably at run time. Add new formats as required. */ +struct pllcx_dividers { + u32 n : 8; + u32 : 2; + u32 m : 8; + u32 p : 4; + u32 : 10; +}; +struct pllpad_dividers { + u32 n : 10; + u32 m : 5; + u32 : 3; + u32 p : 3; + u32 : 1; + u32 cpcon : 4; + u32 : 6; +}; +struct pllu_dividers { + u32 n : 10; + u32 m : 5; + u32 : 3; + u32 p : 1; + u32 : 3; + u32 cpcon : 4; + u32 : 6; +}; + +union __attribute__((transparent_union)) pll_fields { + u32 raw; + struct pll_dividers div; + struct pllcx_dividers cx; + struct pllpad_dividers pad; + struct pllu_dividers u; +}; + +/* This table defines the frequency dividers for every PLL to turn the external + * OSC clock into the frequencies defined by TEGRA_PLL*_KHZ in soc/clock.h. + * All PLLs have three dividers (N, M and P), with the governing formula for + * the output frequency being OUT = (IN / m) * N / (2^P). */ +struct { + int khz; + struct pllcx_dividers pllx; /* target: 1900 MHz */ + struct pllpad_dividers pllp; /* target: 408 MHz */ + struct pllcx_dividers pllc; /* target: 600 MHz */ + struct pllpad_dividers plld; /* target: 925 MHz */ + struct pllu_dividers pllu; /* target; 960 MHz */ +} static const osc_table[16] = { + [OSC_FREQ_OSC12]{ + .khz = 12000, + .pllx = {.n = 158, .m = 1, .p = 0}, /* 1896 MHz */ + .pllp = {.n = 34, .m = 1, .p = 0, .cpcon = 2}, + .pllc = {.n = 50, .m = 1, .p = 0}, + .plld = {.n = 925, .m = 12, .p = 0, .cpcon = 12}, + .pllu = {.n = 80, .m = 1, .p = 0, .cpcon = 3}, + }, + [OSC_FREQ_OSC13]{ + .khz = 13000, + .pllx = {.n = 146, .m = 1, .p = 0}, /* 1898 MHz */ + .pllp = {.n = 408, .m = 13, .p = 0, .cpcon = 8}, + .pllc = {.n = 231, .m = 5, .p = 0}, /* 600.6 MHz */ + .plld = {.n = 925, .m = 13, .p = 0, .cpcon = 12}, + .pllu = {.n = 960, .m = 13, .p = 0, .cpcon = 12}, + }, + [OSC_FREQ_OSC16P8]{ + .khz = 16800, + .pllx = {.n = 113, .m = 1, .p = 0}, /* 1898.4 MHz */ + .pllp = {.n = 170, .m = 7, .p = 0, .cpcon = 4}, + .pllc = {.n = 250, .m = 7, .p = 0}, + .plld = {.n = 936, .m = 17, .p = 0, .cpcon = 12},/* 924.9 MHz */ + .pllu = {.n = 400, .m = 7, .p = 0, .cpcon = 8}, + }, + [OSC_FREQ_OSC19P2]{ + .khz = 19200, + .pllx = {.n = 98, .m = 1, .p = 0}, /* 1881.6 MHz */ + .pllp = {.n = 85, .m = 4, .p = 0, .cpcon = 3}, + .pllc = {.n = 125, .m = 4, .p = 0}, + .plld = {.n = 819, .m = 17, .p = 0, .cpcon = 12},/* 924.9 MHz */ + .pllu = {.n = 50, .m = 1, .p = 0, .cpcon = 2}, + }, + [OSC_FREQ_OSC26]{ + .khz = 26000, + .pllx = {.n = 73, .m = 1, .p = 0}, /* 1898 MHz */ + .pllp = {.n = 204, .m = 13, .p = 0, .cpcon = 5}, + .pllc = {.n = 23, .m = 1, .p = 0}, /* 598 MHz */ + .plld = {.n = 925, .m = 26, .p = 0, .cpcon = 12}, + .pllu = {.n = 480, .m = 13, .p = 0, .cpcon = 8}, + }, + [OSC_FREQ_OSC38P4]{ + .khz = 38400, + .pllx = {.n = 98, .m = 1, .p = 0}, /* 1881.6 MHz */ + .pllp = {.n = 85, .m = 4, .p = 0, .cpcon = 3}, + .pllc = {.n = 125, .m = 4, .p = 0}, + .plld = {.n = 819, .m = 17, .p = 0, .cpcon = 12},/* 924.9 MHz */ + .pllu = {.n = 50, .m = 1, .p = 0, .cpcon = 2}, + }, + [OSC_FREQ_OSC48]{ + .khz = 48000, + .pllx = {.n = 158, .m = 1, .p = 0}, /* 1896 MHz */ + .pllp = {.n = 24, .m = 1, .p = 0, .cpcon = 2}, + .pllc = {.n = 50, .m = 1, .p = 0}, + .plld = {.n = 925, .m = 12, .p = 0, .cpcon = 12}, + .pllu = {.n = 80, .m = 1, .p = 0, .cpcon = 3}, + }, +}; + +void clock_ll_set_source_divisor(u32 *reg, u32 source, u32 divisor) +{ + u32 value; + + value = readl(reg); + + value &= ~CLK_SOURCE_MASK; + value |= source << CLK_SOURCE_SHIFT; + + value &= ~CLK_DIVISOR_MASK; + value |= divisor << CLK_DIVISOR_SHIFT; + + writel(value, reg); +} + +/* Get the oscillator frequency, from the corresponding hardware + * configuration field. This is actually a per-soc thing. Avoid the + * temptation to make it common. */ -void set_avp_clock_to_clkm(void) +static u32 clock_get_osc_bits(void) +{ + return readl(&clk_rst->osc_ctrl) >> OSC_CTRL_OSC_FREQ_SHIFT; +} + +int clock_get_osc_khz(void) +{ + return osc_table[clock_get_osc_bits()].khz; +} + +static void adjust_pllp_out_freqs(void) +{ + u32 reg; + /* Set T30 PLLP_OUT1, 2, 3 & 4 freqs to 9.6, 48, 102 & 204MHz */ + reg = readl(&clk_rst->pllp_outa); // OUTA contains OUT2 / OUT1 + reg |= (IN_408_OUT_48_DIVISOR << PLLP_OUT2_RATIO) | PLLP_OUT2_OVR + | (IN_408_OUT_9_6_DIVISOR << PLLP_OUT1_RATIO) | PLLP_OUT1_OVR; + writel(reg, &clk_rst->pllp_outa); + + reg = readl(&clk_rst->pllp_outb); // OUTB, contains OUT4 / OUT3 + reg |= (IN_408_OUT_204_DIVISOR << PLLP_OUT4_RATIO) | PLLP_OUT4_OVR + | (IN_408_OUT_102_DIVISOR << PLLP_OUT3_RATIO) | PLLP_OUT3_OVR; + writel(reg, &clk_rst->pllp_outb); +} + +static void init_pll(u32 *base, u32 *misc, const union pll_fields pll) +{ + u32 dividers = pll.div.n << PLL_BASE_DIVN_SHIFT | + pll.div.m << PLL_BASE_DIVM_SHIFT | + pll.div.p << PLL_BASE_DIVP_SHIFT; + + /* Write dividers but BYPASS the PLL while we're messing with it. */ + writel(dividers | PLL_BASE_BYPASS, base); + + /* Set CPCON field (defaults to 0 if it doesn't exist for this PLL) */ + writel(pll.div.cpcon << PLL_MISC_CPCON_SHIFT, misc); + + /* enable PLL and take it back out of BYPASS (we don't wait for lock + * because we assume that to be done by the time we start using it). */ + writel(dividers | PLL_BASE_ENABLE, base); +} + +/* Initialize the UART and put it on CLK_M so we can use it during clock_init(). + * Will later move it to PLLP in clock_config(). The divisor must be very small + * to accomodate 12KHz OSCs, so we override the 16.0 UART divider with the 15.1 + * CLK_SOURCE divider to get more precision. (This might still not be enough for + * some OSCs... if you use 13KHz, be prepared to have a bad time.) The 1800 has + * been determined through trial and error (must lead to div 13 at 24MHz). */ +void clock_early_uart(void) +{ + clock_ll_set_source_divisor(&clk_rst->clk_src_uarta, 3, + CLK_UART_DIV_OVERRIDE | CLK_DIVIDER(clock_get_osc_khz(), 1800)); + setbits_le32(&clk_rst->clk_out_enb_l, CLK_L_UARTA); + udelay(2); + clrbits_le32(&clk_rst->rst_dev_l, CLK_L_UARTA); +} + +void clock_cpu0_config_and_reset(void *entry) +{ + void * const evp_cpu_reset = (uint8_t *)TEGRA_EVP_BASE + 0x100; + + write32(CONFIG_STACK_TOP, &cpug_stack_pointer); + write32((uintptr_t)entry, &cpug_entry_point); + write32((uintptr_t)&cpug_setup, evp_cpu_reset); + + // Set up cclk_brst and divider. + write32((CRC_CCLK_BRST_POL_PLLX_OUT0 << 0) | + (CRC_CCLK_BRST_POL_PLLX_OUT0 << 4) | + (CRC_CCLK_BRST_POL_PLLX_OUT0 << 8) | + (CRC_CCLK_BRST_POL_PLLX_OUT0 << 12) | + (CRC_CCLK_BRST_POL_CPU_STATE_RUN << 28), + &clk_rst->cclk_brst_pol); + write32(CRC_SUPER_CCLK_DIVIDER_SUPER_CDIV_ENB, + &clk_rst->super_cclk_div); + + // Enable the clocks for CPUs 0-3. + uint32_t cpu_cmplx_clr = read32(&clk_rst->clk_cpu_cmplx_clr); + cpu_cmplx_clr |= CRC_CLK_CLR_CPU0_STP | CRC_CLK_CLR_CPU1_STP | + CRC_CLK_CLR_CPU2_STP | CRC_CLK_CLR_CPU3_STP; + write32(cpu_cmplx_clr, &clk_rst->clk_cpu_cmplx_clr); + + // Enable other CPU related clocks. + setbits_le32(&clk_rst->clk_out_enb_l, CLK_L_CPU); + setbits_le32(&clk_rst->clk_out_enb_v, CLK_V_CPUG); + + // Disable the reset on the non-CPU parts of the fast cluster. + write32(CRC_RST_CPUG_CLR_NONCPU, + &clk_rst->rst_cpug_cmplx_clr); + // Disable the various resets on the CPUs. + write32(CRC_RST_CPUG_CLR_CPU0 | CRC_RST_CPUG_CLR_CPU1 | + CRC_RST_CPUG_CLR_CPU2 | CRC_RST_CPUG_CLR_CPU3 | + CRC_RST_CPUG_CLR_DBG0 | CRC_RST_CPUG_CLR_DBG1 | + CRC_RST_CPUG_CLR_DBG2 | CRC_RST_CPUG_CLR_DBG3 | + CRC_RST_CPUG_CLR_CORE0 | CRC_RST_CPUG_CLR_CORE1 | + CRC_RST_CPUG_CLR_CORE2 | CRC_RST_CPUG_CLR_CORE3 | + CRC_RST_CPUG_CLR_CX0 | CRC_RST_CPUG_CLR_CX1 | + CRC_RST_CPUG_CLR_CX2 | CRC_RST_CPUG_CLR_CX3 | + CRC_RST_CPUG_CLR_L2 | CRC_RST_CPUG_CLR_PDBG, + &clk_rst->rst_cpug_cmplx_clr); +} + +/** + * The T124 requires some special clock initialization, including setting up + * the DVC I2C, turning on MSELECT and selecting the G CPU cluster + */ +void clock_init(void) { u32 val; + u32 osc = clock_get_osc_bits(); + /* + * On poweron, AVP clock source (also called system clock) is set to + * PLLP_out0 with frequency set at 1MHz. Before initializing PLLP, we + * need to move the system clock's source to CLK_M temporarily. And + * then switch it to PLLP_out4 (204MHz) at a later time. + */ val = (SCLK_SOURCE_CLKM << SCLK_SWAKEUP_FIQ_SOURCE_SHIFT) | (SCLK_SOURCE_CLKM << SCLK_SWAKEUP_IRQ_SOURCE_SHIFT) | (SCLK_SOURCE_CLKM << SCLK_SWAKEUP_RUN_SOURCE_SHIFT) | (SCLK_SOURCE_CLKM << SCLK_SWAKEUP_IDLE_SOURCE_SHIFT) | (SCLK_SYS_STATE_RUN << SCLK_SYS_STATE_SHIFT); - writel(val, &clk_rst->crc_sclk_brst_pol); - /* Wait 2-3us for the clock to flush thru the logic as per the TRM */ - udelay(3); + writel(val, &clk_rst->sclk_brst_pol); + udelay(2); + + /* Set active CPU cluster to G */ + clrbits_le32(&flow->cluster_control, 1); + + /* Change the oscillator drive strength */ + val = readl(&clk_rst->osc_ctrl); + val &= ~OSC_XOFS_MASK; + val |= (OSC_DRIVE_STRENGTH << OSC_XOFS_SHIFT); + writel(val, &clk_rst->osc_ctrl); + + /* Ambiguous quote from u-boot. TODO: what's this mean? + * "should update same value in PMC_OSC_EDPD_OVER XOFS + field for warmboot "*/ + val = readl(&pmc->osc_edpd_over); + val &= ~PMC_OSC_EDPD_OVER_XOFS_MASK; + val |= (OSC_DRIVE_STRENGTH << PMC_OSC_EDPD_OVER_XOFS_SHIFT); + writel(val, &pmc->osc_edpd_over); + + /* Disable IDDQ for PLLX before we set it up (from U-Boot -- why?) */ + val = readl(&clk_rst->pllx_misc3); + val &= ~PLLX_IDDQ_MASK; + writel(val, &clk_rst->pllx_misc3); + udelay(2); + + /* Set PLLC dynramp_step A to 0x2b and B to 0xb (from U-Boot -- why? */ + writel(0x2b << 17 | 0xb << 9, &clk_rst->pllc_misc2); + + adjust_pllp_out_freqs(); + + init_pll(&clk_rst->pllx_base, &clk_rst->pllx_misc, osc_table[osc].pllx); + init_pll(&clk_rst->pllp_base, &clk_rst->pllp_misc, osc_table[osc].pllp); + init_pll(&clk_rst->pllc_base, &clk_rst->pllc_misc, osc_table[osc].pllc); + init_pll(&clk_rst->plld_base, &clk_rst->plld_misc, osc_table[osc].plld); + init_pll(&clk_rst->pllu_base, &clk_rst->pllu_misc, osc_table[osc].pllu); + + val = (1 << CLK_SYS_RATE_AHB_RATE_SHIFT); + writel(val, &clk_rst->clk_sys_rate); +} + +void clock_config(void) +{ + /* Enable clocks for the required peripherals. */ + /* TODO: can (should?) we use the _SET and _CLR registers here? */ + setbits_le32(&clk_rst->clk_out_enb_l, + CLK_L_CACHE2 | CLK_L_GPIO | CLK_L_TMR | CLK_L_I2C1 | + CLK_L_SDMMC4); + setbits_le32(&clk_rst->clk_out_enb_h, + CLK_H_EMC | CLK_H_I2C2 | CLK_H_I2C5 | CLK_H_SBC1 | + CLK_H_PMC | CLK_H_APBDMA | CLK_H_MEM); + setbits_le32(&clk_rst->clk_out_enb_u, + CLK_U_I2C3 | CLK_U_CSITE | CLK_U_SDMMC3); + setbits_le32(&clk_rst->clk_out_enb_v, CLK_V_MSELECT); + setbits_le32(&clk_rst->clk_out_enb_w, CLK_W_DVFS); + + /* + * Set MSELECT clock source as PLLP (00)_REG, and ask for a clock + * divider that would set the MSELECT clock at 102MHz for a + * PLLP base of 408MHz. + */ + clock_ll_set_source_divisor(&clk_rst->clk_src_mselect, 0, + CLK_DIVIDER(TEGRA_PLLP_KHZ, 102000)); + + /* Give clock time to stabilize */ + udelay(IO_STABILIZATION_DELAY); + + /* I2C1 gets CLK_M and a divisor of 17 */ + clock_ll_set_source_divisor(&clk_rst->clk_src_i2c1, 3, 16); + /* I2C2 gets CLK_M and a divisor of 17 */ + clock_ll_set_source_divisor(&clk_rst->clk_src_i2c2, 3, 16); + /* I2C3 (cam) gets CLK_M and a divisor of 17 */ + clock_ll_set_source_divisor(&clk_rst->clk_src_i2c3, 3, 16); + /* I2C5 (PMU) gets CLK_M and a divisor of 17 */ + clock_ll_set_source_divisor(&clk_rst->clk_src_i2c5, 3, 16); + + /* UARTA gets PLLP, deactivate CLK_UART_DIV_OVERRIDE */ + writel(0 << CLK_SOURCE_SHIFT, &clk_rst->clk_src_uarta); + + /* Give clock time to stabilize. */ + udelay(IO_STABILIZATION_DELAY); + + /* Take required peripherals out of reset. */ + + clrbits_le32(&clk_rst->rst_dev_l, + CLK_L_CACHE2 | CLK_L_GPIO | CLK_L_TMR | CLK_L_I2C1 | + CLK_L_SDMMC4); + clrbits_le32(&clk_rst->rst_dev_h, + CLK_H_EMC | CLK_H_I2C2 | CLK_H_I2C5 | CLK_H_SBC1 | + CLK_H_PMC | CLK_H_APBDMA | CLK_H_MEM); + clrbits_le32(&clk_rst->rst_dev_u, + CLK_U_I2C3 | CLK_U_CSITE | CLK_U_SDMMC3); + clrbits_le32(&clk_rst->rst_dev_v, CLK_V_MSELECT); + clrbits_le32(&clk_rst->rst_dev_w, CLK_W_DVFS); } diff --git a/src/soc/nvidia/tegra124/clock.h b/src/soc/nvidia/tegra124/clock.h deleted file mode 100644 index 688505a..0000000 --- a/src/soc/nvidia/tegra124/clock.h +++ /dev/null @@ -1,22 +0,0 @@ -/* - * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. - */ - -#ifndef __SOC_NVIDIA_TEGRA124_CLOCK_H__ -#define __SOC_NVIDIA_TEGRA124_CLOCK_H__ - -void set_avp_clock_to_clkm(void); - -#endif /* __SOC_NVIDIA_TEGRA124_CLOCK_H__ */ diff --git a/src/soc/nvidia/tegra124/cpug.S b/src/soc/nvidia/tegra124/cpug.S new file mode 100644 index 0000000..7f761e8 --- /dev/null +++ b/src/soc/nvidia/tegra124/cpug.S @@ -0,0 +1,56 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2013 Google Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + + .align 6 + .arm + + .global cpug_stack_pointer +cpug_stack_pointer: + .word 0 + + .global cpug_entry_point +cpug_entry_point: + .word 0 + + .global cpug_setup + .type cpug_setup, function + cpug_setup: + + /* + * Set the cpu to System mode with IRQ and FIQ disabled. Prefetch/Data + * aborts may happen early and crash before the abort handlers are + * installed, but at least the problem will show up near the code that + * causes it. + */ + msr cpsr_cxf, #0xdf + + ldr sp, cpug_stack_pointer + eor lr, lr + ldr r0, cpug_entry_point + bx r0 diff --git a/src/soc/nvidia/tegra124/cpug.h b/src/soc/nvidia/tegra124/cpug.h new file mode 100644 index 0000000..842843a --- /dev/null +++ b/src/soc/nvidia/tegra124/cpug.h @@ -0,0 +1,29 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef __SOC_NVIDIA_TEGRA124_CPUG_H__ +#define __SOC_NVIDIA_TEGRA124_CPUG_H__ + +#include <stdint.h> + +extern u32 cpug_stack_pointer; +extern u32 cpug_entry_point; +void cpug_setup(void); + +#endif /* __SOC_NVIDIA_TEGRA124_CPUG_H__ */ diff --git a/src/soc/nvidia/tegra124/display.c b/src/soc/nvidia/tegra124/display.c new file mode 100644 index 0000000..b7d3d7f --- /dev/null +++ b/src/soc/nvidia/tegra124/display.c @@ -0,0 +1,304 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <arch/io.h> +#include <stdint.h> +#include <lib.h> +#include <stdlib.h> +#include <delay.h> +#include <soc/addressmap.h> +#include <device/device.h> +#include <stdlib.h> +#include <string.h> +#include <cpu/cpu.h> +#include <boot/tables.h> +#include <cbmem.h> +#include <soc/clock.h> +#include <soc/nvidia/tegra/dc.h> +#include "clk_rst.h" +#include "chip.h" +#include <soc/display.h> + +static struct clk_rst_ctlr *clk_rst = (void *)TEGRA_CLK_RST_BASE; + +static const u32 rgb_enb_tab[PIN_REG_COUNT] = { + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, +}; + +static const u32 rgb_polarity_tab[PIN_REG_COUNT] = { + 0x00000000, + 0x01000000, + 0x00000000, + 0x00000000, +}; + +static const u32 rgb_data_tab[PIN_REG_COUNT] = { + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, +}; + +static const u32 rgb_sel_tab[PIN_OUTPUT_SEL_COUNT] = { + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00210222, + 0x00002200, + 0x00020000, +}; + +static int update_display_mode(struct dc_disp_reg *disp, + struct soc_nvidia_tegra124_config *config) +{ + u32 val; + u32 rate; + u32 div; + + writel(0x0, &disp->disp_timing_opt); + + writel(config->vref_to_sync << 16 | config->href_to_sync, + &disp->ref_to_sync); + writel(config->vsync_width << 16 | config->hsync_width, &disp->sync_width); + writel(config->vback_porch << 16 | config->hback_porch, &disp->back_porch); + writel(config->vfront_porch << 16 | config->hfront_porch, + &disp->front_porch); + + writel(config->xres | (config->yres << 16), &disp->disp_active); + + val = DE_SELECT_ACTIVE << DE_SELECT_SHIFT; + val |= DE_CONTROL_NORMAL << DE_CONTROL_SHIFT; + writel(val, &disp->data_enable_opt); + + val = DATA_FORMAT_DF1P1C << DATA_FORMAT_SHIFT; + val |= DATA_ALIGNMENT_MSB << DATA_ALIGNMENT_SHIFT; + val |= DATA_ORDER_RED_BLUE << DATA_ORDER_SHIFT; + writel(val, &disp->disp_interface_ctrl); + + /* + * The pixel clock divider is in 7.1 format (where the bottom bit + * represents 0.5). Here we calculate the divider needed to get from + * the display clock (typically 600MHz) to the pixel clock. We round + * up or down as requried. + * We use pllp for now. + */ + rate = 600 * 1000000; + div = ((rate * 2 + config->pixel_clock / 2) / config->pixel_clock) - 2; + printk(BIOS_SPEW, "Display clock %d, divider %d\n", rate, div); + + writel(0x00010001, &disp->shift_clk_opt); + + val = PIXEL_CLK_DIVIDER_PCD1 << PIXEL_CLK_DIVIDER_SHIFT; + val |= div << SHIFT_CLK_DIVIDER_SHIFT; + writel(val, &disp->disp_clk_ctrl); + + return 0; +} + +static int setup_window(struct disp_ctl_win *win, + struct soc_nvidia_tegra124_config *config) +{ + int log2_bpp = log2(config->framebuffer_bits_per_pixel); + win->x = 0; + win->y = 0; + win->w = config->xres; + win->h = config->yres; + win->out_x = 0; + win->out_y = 0; + win->out_w = config->xres; + win->out_h = config->yres; + win->phys_addr = config->framebuffer_base; + win->stride = config->xres * (1 << log2_bpp) / 8; + printk(BIOS_SPEW, "%s: depth = %d\n", __func__, log2_bpp); + switch (log2_bpp) { + case 5: + case 24: + win->fmt = COLOR_DEPTH_R8G8B8A8; + win->bpp = 32; + break; + case 4: + win->fmt = COLOR_DEPTH_B5G6R5; + win->bpp = 16; + break; + + default: + printk(BIOS_SPEW, "Unsupported LCD bit depth"); + return -1; + } + + return 0; +} + +static void update_window(struct display_controller *dc, + struct disp_ctl_win *win, + struct soc_nvidia_tegra124_config *config) +{ + u32 h_dda, v_dda; + u32 val; + + val = readl(&dc->cmd.disp_win_header); + val |= WINDOW_A_SELECT; + writel(val, &dc->cmd.disp_win_header); + + writel(win->fmt, &dc->win.color_depth); + + clrsetbits_le32(&dc->win.byte_swap, BYTE_SWAP_MASK, + BYTE_SWAP_NOSWAP << BYTE_SWAP_SHIFT); + + val = win->out_x << H_POSITION_SHIFT; + val |= win->out_y << V_POSITION_SHIFT; + writel(val, &dc->win.pos); + + val = win->out_w << H_SIZE_SHIFT; + val |= win->out_h << V_SIZE_SHIFT; + writel(val, &dc->win.size); + + val = (win->w * win->bpp / 8) << H_PRESCALED_SIZE_SHIFT; + val |= win->h << V_PRESCALED_SIZE_SHIFT; + writel(val, &dc->win.prescaled_size); + + writel(0, &dc->win.h_initial_dda); + writel(0, &dc->win.v_initial_dda); + + h_dda = (win->w * 0x1000) / MAX(win->out_w - 1, 1); + v_dda = (win->h * 0x1000) / MAX(win->out_h - 1, 1); + + val = h_dda << H_DDA_INC_SHIFT; + val |= v_dda << V_DDA_INC_SHIFT; + writel(val, &dc->win.dda_increment); + + writel(win->stride, &dc->win.line_stride); + writel(0, &dc->win.buf_stride); + + val = WIN_ENABLE; + if (win->bpp < 24) + val |= COLOR_EXPAND; + writel(val, &dc->win.win_opt); + + writel((u32) win->phys_addr, &dc->winbuf.start_addr); + writel(win->x, &dc->winbuf.addr_h_offset); + writel(win->y, &dc->winbuf.addr_v_offset); + + writel(0xff00, &dc->win.blend_nokey); + writel(0xff00, &dc->win.blend_1win); + + val = GENERAL_ACT_REQ | WIN_A_ACT_REQ; + val |= GENERAL_UPDATE | WIN_A_UPDATE; + writel(val, &dc->cmd.state_ctrl); +} + +/* this is really aimed at the lcd panel. That said, there are two display + * devices on this part and we may someday want to extend it for other boards. + */ +void display_startup(device_t dev) +{ + u32 val; + int i; + struct soc_nvidia_tegra124_config *config = dev->chip_info; + struct display_controller *dc = (void *)config->display_controller; + struct disp_ctl_win window; + + /* should probably just make it all MiB ... in future */ + u32 framebuffer_size_mb = config->framebuffer_size / MiB; + u32 framebuffer_base_mb= config->framebuffer_base / MiB; + + printk(BIOS_SPEW, + "%s: xres %d yres %d framebuffer_bits_per_pixel %d\n", + __func__, + config->xres, config->yres, config->framebuffer_bits_per_pixel); + if (framebuffer_size_mb == 0){ + framebuffer_size_mb = ALIGN_UP(config->xres * config->yres * + (config->framebuffer_bits_per_pixel / 8), MiB)/MiB; + } + + if (! framebuffer_base_mb) + framebuffer_base_mb = FB_BASE_MB; + + mmu_config_range(framebuffer_base_mb, framebuffer_size_mb, + config->cache_policy); + + /* Enable flushing after LCD writes if requested */ + /* I don't understand this part yet. + lcd_set_flush_dcache(config.cache_type & FDT_LCD_CACHE_FLUSH); + */ + printk(BIOS_SPEW, "LCD frame buffer at %dMiB to %dMiB\n", framebuffer_base_mb, + framebuffer_base_mb + framebuffer_size_mb); + + /* GPIO magic here if needed to start powering up things. You + * really only want to enable vdd, wait a bit, and then enable + * the panel. However ... the timings in the tegra20 dts make + * no sense to me. I'm pretty sure they're wrong. + * The panel_vdd is done in the romstage, so we need only + * light things up here once we're sure it's all working. + */ + setbits_le32(&clk_rst->rst_dev_l, CLK_L_DISP1 | CLK_L_HOST1X); + + clock_ll_set_source_divisor(&clk_rst->clk_src_host1x, 4, + CLK_DIVIDER(TEGRA_PLLP_KHZ, 144000)); + /* u-boot uses PLLC for DISP1. + * But the u-boot code does not work and we don't set up PLLC anyway. + * PLLP seems quite good enough, so run with that for now. */ + clock_ll_set_source_divisor(&clk_rst->clk_src_disp1, 0 /* 4 */, + CLK_DIVIDER(TEGRA_PLLP_KHZ, 600000)); + + udelay(2); + + clrbits_le32(&clk_rst->rst_dev_l, CLK_L_DISP1|CLK_L_HOST1X); + + writel(0x00000100, &dc->cmd.gen_incr_syncpt_ctrl); + writel(0x0000011a, &dc->cmd.cont_syncpt_vsync); + writel(0x00000000, &dc->cmd.int_type); + writel(0x00000000, &dc->cmd.int_polarity); + writel(0x00000000, &dc->cmd.int_mask); + writel(0x00000000, &dc->cmd.int_enb); + + val = PW0_ENABLE | PW1_ENABLE | PW2_ENABLE; + val |= PW3_ENABLE | PW4_ENABLE | PM0_ENABLE; + val |= PM1_ENABLE; + writel(val, &dc->cmd.disp_pow_ctrl); + + val = readl(&dc->cmd.disp_cmd); + val |= CTRL_MODE_C_DISPLAY << CTRL_MODE_SHIFT; + writel(val, &dc->cmd.disp_cmd); + + writel(0x00000020, &dc->disp.mem_high_pri); + writel(0x00000001, &dc->disp.mem_high_pri_timer); + + for (i = 0; i < PIN_REG_COUNT; i++) { + writel(rgb_enb_tab[i], &dc->com.pin_output_enb[i]); + writel(rgb_polarity_tab[i], &dc->com.pin_output_polarity[i]); + writel(rgb_data_tab[i], &dc->com.pin_output_data[i]); + } + + for (i = 0; i < PIN_OUTPUT_SEL_COUNT; i++) + writel(rgb_sel_tab[i], &dc->com.pin_output_sel[i]); + + if (config->pixel_clock) + update_display_mode(&dc->disp, config); + + if (!setup_window(&window, config)) + update_window(dc, &window, config); + +} + diff --git a/src/soc/nvidia/tegra124/dma.c b/src/soc/nvidia/tegra124/dma.c new file mode 100644 index 0000000..964bb7b --- /dev/null +++ b/src/soc/nvidia/tegra124/dma.c @@ -0,0 +1,236 @@ +/* + * (C) Copyright 2010,2011 + * NVIDIA Corporation <www.nvidia.com> + * Copyright 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#include <inttypes.h> +#include <stddef.h> +#include <stdlib.h> +#include <console/console.h> + +#include <arch/io.h> +#include <soc/addressmap.h> + +#include "dma.h" + +/* + * Note: Many APB DMA controller registers are laid out such that each + * bit controls or represents the status for the corresponding channel. + * So we will not bother to list each individual bit in this case. + */ +#define APBDMA_COMMAND_GEN (1 << 31) + +#define APBDMA_CNTRL_REG_COUNT_VALUE_MASK 0xffff +#define APBDMA_CNTRL_REG_COUNT_VALUE_SHIFT 0 + +struct apb_dma { + u32 command; /* 0x00 */ + u32 status; /* 0x04 */ + u32 rsvd1[2]; + u32 cntrl_reg; /* 0x10 */ + u32 irq_sta_cpu; /* 0x14 */ + u32 irq_sta_cop; /* 0x18 */ + u32 irq_mask; /* 0x1c */ + u32 irq_mask_set; /* 0x20 */ + u32 irq_mask_clr; /* 0x24 */ + u32 trig_reg; /* 0x28 */ + u32 channel_trig_reg; /* 0x2c */ + u32 dma_status; /* 0x30 */ + u32 channel_en_reg; /* 0x34 */ + u32 security_reg; /* 0x38 */ + u32 channel_swid; /* 0x3c */ + u32 rsvd[1]; + u32 chan_wt_reg0; /* 0x44 */ + u32 chan_wt_reg1; /* 0x48 */ + u32 chan_wt_reg2; /* 0x4c */ + u32 chan_wr_reg3; /* 0x50 */ + u32 channel_swid1; /* 0x54 */ +} __attribute__((packed)); +struct apb_dma * const apb_dma = (struct apb_dma *)TEGRA_APB_DMA_BASE; + +/* + * Naming in the doc included a superfluous _CHANNEL_n_ for + * each entry and was left out for the sake of conciseness. + */ +#define APBDMACHAN_CSR_ENB (1 << 31) +#define APBDMACHAN_CSR_IE_EOC (1 << 30) +#define APBDMACHAN_CSR_HOLD (1 << 29) +#define APBDMACHAN_CSR_DIR (1 << 28) +#define APBDMACHAN_CSR_ONCE (1 << 27) +#define APBDMACHAN_CSR_FLOW (1 << 21) +#define APBDMACHAN_CSR_REQ_SEL_MASK 0x1f +#define APBDMACHAN_CSR_REQ_SEL_SHIFT 16 + +#define APBDMACHAN_STA_BSY (1 << 31) +#define APBDMACHAN_STA_ISE_EOC (1 << 30) +#define APBDMACHAN_STA_HALT (1 << 29) +#define APBDMACHAN_STA_PING_PONG_STA (1 << 28) +#define APBDMACHAN_STA_DMA_ACTIVITY (1 << 27) +#define APBDMACHAN_STA_CHANNEL_PAUSE (1 << 26) + +#define APBDMACHAN_CSRE_CHANNEL_PAUSE (1 << 31) +#define APBDMACHAN_CSRE_TRIG_SEL_MASK 0x3f +#define APBDMACHAN_CSRE_TRIG_SEL_SHIFT 14 + +#define APBDMACHAN_AHB_PTR_MASK (0x3fffffff) +#define APBDMACHAN_AHB_PTR_SHIFT 2 + +#define APBDMACHAN_AHB_SEQ_INTR_ENB (1 << 31) +#define APBDMACHAN_AHB_SEQ_AHB_BUS_WIDTH_MASK 0x7 +#define APBDMACHAN_AHB_SEQ_AHB_BUS_WIDTH_SHIFT 28 +#define APBDMACHAN_AHB_SEQ_AHB_DATA_SWAP (1 << 27) +#define APBDMACHAN_AHB_SEQ_AHB_BURST_MASK 0x7 +#define APBDMACHAN_AHB_SEQ_AHB_BURST_SHIFT 24 +#define APBDMACHAN_AHB_SEQ_DBL_BUF (1 << 19) +#define APBDMACHAN_AHB_SEQ_WRAP_MASK 0x7 +#define APBDMACHAN_AHB_SEQ_WRAP_SHIFT 16 + +#define APBDMACHAN_AHB_SEQ_AHB_BUS_WIDTH_MASK 0x7 +#define APBDMACHAN_AHB_SEQ_AHB_BUS_WIDTH_SHIFT 28 + +#define APBDMACHAN_APB_PTR_MASK 0x3fffffff +#define APBDMACHAN_APB_PTR_SHIFT 2 + +#define APBDMACHAN_APB_SEQ_APB_BUS_WIDTH_MASK 0x7 +#define APBDMACHAN_APB_SEQ_APB_BUS_WIDTH_SHIFT 28 +#define APBDMACHAN_APB_SEQ_APB_DATA_SWAP (1 << 27) +#define APBDMACHAN_APB_SEQ_APB_ADDR_WRAP_MASK 0x7 +#define APBDMACHAN_APB_SEQ_APB_ADDR_WRAP_SHIFT 16 + +#define APBDMACHAN_WORD_TRANSFER_ + +#define APBDMACHAN_WORD_TRANSFER_MASK 0x0fffffff +#define APBDMACHAN_WORD_TRANSFER_SHIFT 2 + +#define APB_DMA_OFFSET(n) \ + (struct apb_dma_channel_regs *)(TEGRA_APB_DMA_BASE + n) +struct apb_dma_channel apb_dma_channels[] = { + { .num = 0, .regs = APB_DMA_OFFSET(0x1000) }, + { .num = 1, .regs = APB_DMA_OFFSET(0x1040) }, + { .num = 2, .regs = APB_DMA_OFFSET(0x1080) }, + { .num = 3, .regs = APB_DMA_OFFSET(0x10c0) }, + { .num = 4, .regs = APB_DMA_OFFSET(0x1100) }, + { .num = 5, .regs = APB_DMA_OFFSET(0x1140) }, + { .num = 6, .regs = APB_DMA_OFFSET(0x1180) }, + { .num = 7, .regs = APB_DMA_OFFSET(0x11c0) }, + { .num = 8, .regs = APB_DMA_OFFSET(0x1200) }, + { .num = 9, .regs = APB_DMA_OFFSET(0x1240) }, + { .num = 10, .regs = APB_DMA_OFFSET(0x1280) }, + { .num = 11, .regs = APB_DMA_OFFSET(0x12c0) }, + { .num = 12, .regs = APB_DMA_OFFSET(0x1300) }, + { .num = 13, .regs = APB_DMA_OFFSET(0x1340) }, + { .num = 14, .regs = APB_DMA_OFFSET(0x1380) }, + { .num = 15, .regs = APB_DMA_OFFSET(0x13c0) }, + { .num = 16, .regs = APB_DMA_OFFSET(0x1400) }, + { .num = 17, .regs = APB_DMA_OFFSET(0x1440) }, + { .num = 18, .regs = APB_DMA_OFFSET(0x1480) }, + { .num = 19, .regs = APB_DMA_OFFSET(0x14c0) }, + { .num = 20, .regs = APB_DMA_OFFSET(0x1500) }, + { .num = 21, .regs = APB_DMA_OFFSET(0x1540) }, + { .num = 22, .regs = APB_DMA_OFFSET(0x1580) }, + { .num = 23, .regs = APB_DMA_OFFSET(0x15c0) }, + { .num = 24, .regs = APB_DMA_OFFSET(0x1600) }, + { .num = 25, .regs = APB_DMA_OFFSET(0x1640) }, + { .num = 26, .regs = APB_DMA_OFFSET(0x1680) }, + { .num = 27, .regs = APB_DMA_OFFSET(0x16c0) }, + { .num = 28, .regs = APB_DMA_OFFSET(0x1700) }, + { .num = 29, .regs = APB_DMA_OFFSET(0x1740) }, + { .num = 30, .regs = APB_DMA_OFFSET(0x1780) }, + { .num = 31, .regs = APB_DMA_OFFSET(0x17c0) }, +}; + +int dma_busy(struct apb_dma_channel * const channel) +{ + /* + * In continuous mode, the BSY_n bit in APB_DMA_STATUS and + * BSY in APBDMACHAN_CHANNEL_n_STA_0 will remain set as '1' so long + * as the channel is enabled. So for this function we'll use the + * DMA_ACTIVITY bit. + */ + return read32(&channel->regs->sta) & APBDMACHAN_STA_DMA_ACTIVITY ? 1 : 0; +} +/* claim a DMA channel */ +struct apb_dma_channel * const dma_claim(void) +{ + int i; + struct apb_dma_channel_regs *regs = NULL; + + /* + * Set global enable bit, otherwise register access to channel + * DMA registers will not be possible. + */ + setbits_le32(&apb_dma->command, APBDMA_COMMAND_GEN); + + for (i = 0; i < ARRAY_SIZE(apb_dma_channels); i++) { + regs = apb_dma_channels[i].regs; + + if (!apb_dma_channels[i].in_use) { + u32 status = read32(&regs->sta); + if (status & (1 << i)) { + /* FIXME: should this be fatal? */ + printk(BIOS_DEBUG, "%s: DMA channel %d busy?\n", + __func__, i); + } + break; + } + } + + if (i == ARRAY_SIZE(apb_dma_channels)) + return NULL; + + apb_dma_channels[i].in_use = 1; + return &apb_dma_channels[i]; +} + +/* release a DMA channel */ +void dma_release(struct apb_dma_channel * const channel) +{ + int i; + + /* FIXME: make this "thread" friendly */ + while (dma_busy(channel)) + ; + + channel->in_use = 0; + + /* clear the global enable bit if no channels are in use */ + for (i = 0; i < ARRAY_SIZE(apb_dma_channels); i++) { + if (apb_dma_channels[i].in_use) + return; + } + + clrbits_le32(&apb_dma->command, APBDMA_COMMAND_GEN); +} + +int dma_start(struct apb_dma_channel * const channel) +{ + struct apb_dma_channel_regs *regs = channel->regs; + + /* Set ENB bit for this channel */ + setbits_le32(&regs->csr, APBDMACHAN_CSR_ENB); + + return 0; +} + +int dma_stop(struct apb_dma_channel * const channel) +{ + struct apb_dma_channel_regs *regs = channel->regs; + + /* Clear ENB bit for this channel */ + clrbits_le32(&regs->csr, APBDMACHAN_CSR_ENB); + + return 0; +} diff --git a/src/soc/nvidia/tegra124/dma.h b/src/soc/nvidia/tegra124/dma.h new file mode 100644 index 0000000..d7e9090 --- /dev/null +++ b/src/soc/nvidia/tegra124/dma.h @@ -0,0 +1,61 @@ +/* + * (C) Copyright 2010,2011 + * NVIDIA Corporation <www.nvidia.com> + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef __NVIDIA_TEGRA124_DMA_H__ +#define __NVIDIA_TEGRA124_DMA_H__ + +#include <inttypes.h> +#include <soc/addressmap.h> + +/* + * The DMA engine operates on 4 bytes at a time, so make sure any data + * passed via DMA is aligned to avoid underrun/overrun. + */ +#define TEGRA_DMA_ALIGN_BYTES 4 + +struct apb_dma_channel_regs { + u32 csr; /* 0x00 */ + u32 sta; /* 0x04 */ + u32 dma_byte_sta; /* 0x08 */ + u32 csre; /* 0x0c */ + u32 ahb_ptr; /* 0x10 */ + u32 ahb_seq; /* 0x14 */ + u32 apb_ptr; /* 0x18 */ + u32 apb_seq; /* 0x1c */ + u32 wcount; /* 0x20 */ + u32 word_transfer; /* 0x24 */ +} __attribute__((packed)); + +struct apb_dma_channel { + const int num; + struct apb_dma_channel_regs *regs; + + /* + * Basic high-level semaphore that can be used to "claim" + * a DMA channel e.g. by SPI, I2C, or other peripheral driver. + */ + int in_use; +}; + +struct apb_dma_channel * const dma_claim(void); +void dma_release(struct apb_dma_channel * const channel); +int dma_start(struct apb_dma_channel * const channel); +int dma_stop(struct apb_dma_channel * const channel); +int dma_busy(struct apb_dma_channel * const channel); + +#endif /* __NVIDIA_TEGRA124_DMA_H__ */ diff --git a/src/soc/nvidia/tegra124/early_display.c b/src/soc/nvidia/tegra124/early_display.c new file mode 100644 index 0000000..4356a62 --- /dev/null +++ b/src/soc/nvidia/tegra124/early_display.c @@ -0,0 +1,61 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <stdlib.h> +#include <stddef.h> +#include <arch/cache.h> +#include "chip.h" +#include <soc/display.h> +#include "gpio.h" + +/* the primary purpose of this function is to kick off things in + * romstage that are time consuming. No more should be done at this + * point than the bare minimum that will allow us to pick up the work + * in the ramstage and not require lots of udelays. ramstage will do + * the rest. As it happens, that merely means 'turn off everything you can, + * save the minimum long-delay bit that you need to get graphics going'. It's + * important not to have the backlight on as people don't like display trash + * on startup, even if I do. + */ +void setup_display(struct soc_nvidia_tegra124_config *config) +{ + if (config->panel_vdd_gpio){ + gpio_output(config->panel_vdd_gpio, 1); + printk(BIOS_SPEW,"%s: setting gpio %08x to %d\n", + __func__, config->panel_vdd_gpio, 1); + } + if (config->lvds_shutdown_gpio){ + gpio_output(config->lvds_shutdown_gpio, 0); + printk(BIOS_SPEW,"%s: setting gpio %08x to %d\n", + __func__, config->lvds_shutdown_gpio, 0); + } + if (config->backlight_en_gpio){ + gpio_output(config->backlight_en_gpio, 0); + printk(BIOS_SPEW,"%s: setting gpio %08x to %d\n", + __func__, config->backlight_en_gpio, 0); + } + if (config->backlight_vdd_gpio){ + gpio_output(config->backlight_vdd_gpio, 0); + printk(BIOS_SPEW,"%s: setting gpio %08x to %d\n", + __func__, config->backlight_vdd_gpio, 0); + } + +} + diff --git a/src/soc/nvidia/tegra124/flow.h b/src/soc/nvidia/tegra124/flow.h new file mode 100644 index 0000000..a974f09 --- /dev/null +++ b/src/soc/nvidia/tegra124/flow.h @@ -0,0 +1,49 @@ +/* + * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef _TEGRA124_FLOW_H_ +#define _TEGRA124_FLOW_H_ + +struct flow_ctlr { + u32 halt_cpu_events; /* offset 0x00 */ + u32 halt_cop_events; /* offset 0x04 */ + u32 cpu_csr; /* offset 0x08 */ + u32 cop_csr; /* offset 0x0c */ + u32 xrq_events; /* offset 0x10 */ + u32 halt_cpu1_events; /* offset 0x14 */ + u32 cpu1_csr; /* offset 0x18 */ + u32 halt_cpu2_events; /* offset 0x1c */ + u32 cpu2_csr; /* offset 0x20 */ + u32 halt_cpu3_events; /* offset 0x24 */ + u32 cpu3_csr; /* offset 0x28 */ + u32 cluster_control; /* offset 0x2c */ + u32 halt_cop1_events; /* offset 0x30 */ + u32 halt_cop1_csr; /* offset 0x34 */ + u32 cpu_pwr_csr; /* offset 0x38 */ + u32 mpid; /* offset 0x3c */ + u32 ram_repair; /* offset 0x40 */ +}; + +/* HALT_COP_EVENTS_0, 0x04 */ +#define EVENT_MSEC (1 << 24) +#define EVENT_USEC (1 << 25) +#define EVENT_JTAG (1 << 28) +#define EVENT_MODE_STOP (2 << 29) + +/* FLOW_CTLR_CLUSTER_CONTROL_0 0x2c */ +#define ACTIVE_LP (1 << 0) + +#endif /* _TEGRA124_FLOW_H_ */ diff --git a/src/soc/nvidia/tegra124/gpio.h b/src/soc/nvidia/tegra124/gpio.h index 83d727d..f7d1c30 100644 --- a/src/soc/nvidia/tegra124/gpio.h +++ b/src/soc/nvidia/tegra124/gpio.h @@ -23,11 +23,14 @@ #include <soc/nvidia/tegra/gpio.h> #include <stdint.h> +#include "pinmux.h" /* for pinmux constants in GPIO macro */ + /* GPIO index constants. */ #define GPIO_PORT_CONSTANTS(port) \ - GPIO_##port##0, GPIO_##port##1, GPIO_##port##2, GPIO_##port##3, \ - GPIO_##port##4, GPIO_##port##5, GPIO_##port##6, GPIO_##port##7 + GPIO_##port##0_INDEX, GPIO_##port##1_INDEX, GPIO_##port##2_INDEX, \ + GPIO_##port##3_INDEX, GPIO_##port##4_INDEX, GPIO_##port##5_INDEX, \ + GPIO_##port##6_INDEX, GPIO_##port##7_INDEX enum { GPIO_PORT_CONSTANTS(A), diff --git a/src/soc/nvidia/tegra124/include/soc/addressmap.h b/src/soc/nvidia/tegra124/include/soc/addressmap.h index bf59d75..9836215 100644 --- a/src/soc/nvidia/tegra124/include/soc/addressmap.h +++ b/src/soc/nvidia/tegra124/include/soc/addressmap.h @@ -21,6 +21,8 @@ #ifndef __SOC_NVIDIA_TEGRA124_INCLUDE_SOC_ADDRESS_MAP_H__ #define __SOC_NVIDIA_TEGRA124_INCLUDE_SOC_ADDRESS_MAP_H__ +#include <stddef.h> + enum { TEGRA_SRAM_BASE = 0x40000000, TEGRA_SRAM_SIZE = 0x20000 @@ -28,12 +30,15 @@ enum { enum { TEGRA_ARM_PERIPHBASE = 0x50040000, + TEGRA_ARM_DISPLAYA = 0x54200000, + TEGRA_ARM_DISPLAYB = 0x54240000, TEGRA_PG_UP_BASE = 0x60000000, TEGRA_TMRUS_BASE = 0x60005010, TEGRA_CLK_RST_BASE = 0x60006000, TEGRA_FLOW_BASE = 0x60007000, TEGRA_GPIO_BASE = 0x6000D000, TEGRA_EVP_BASE = 0x6000F000, + TEGRA_APB_DMA_BASE = 0x60020000, TEGRA_APB_MISC_BASE = 0x70000000, TEGRA_APB_MISC_GP_BASE = TEGRA_APB_MISC_BASE + 0x0800, TEGRA_APB_PINGROUP_BASE = TEGRA_APB_MISC_BASE + 0x0868, @@ -51,12 +56,12 @@ enum { TEGRA_I2C4_BASE = TEGRA_APB_MISC_BASE + 0xC700, TEGRA_I2C5_BASE = TEGRA_APB_MISC_BASE + 0xD000, TEGRA_I2C6_BASE = TEGRA_APB_MISC_BASE + 0xD100, - TEGRA_SLINK1_BASE = TEGRA_APB_MISC_BASE + 0xD400, - TEGRA_SLINK2_BASE = TEGRA_APB_MISC_BASE + 0xD600, - TEGRA_SLINK3_BASE = TEGRA_APB_MISC_BASE + 0xD800, - TEGRA_SLINK4_BASE = TEGRA_APB_MISC_BASE + 0xDA00, - TEGRA_SLINK5_BASE = TEGRA_APB_MISC_BASE + 0xDC00, - TEGRA_SLINK6_BASE = TEGRA_APB_MISC_BASE + 0xDE00, + TEGRA_SPI1_BASE = TEGRA_APB_MISC_BASE + 0xD400, + TEGRA_SPI2_BASE = TEGRA_APB_MISC_BASE + 0xD600, + TEGRA_SPI3_BASE = TEGRA_APB_MISC_BASE + 0xD800, + TEGRA_SPI4_BASE = TEGRA_APB_MISC_BASE + 0xDA00, + TEGRA_SPI5_BASE = TEGRA_APB_MISC_BASE + 0xDC00, + TEGRA_SPI6_BASE = TEGRA_APB_MISC_BASE + 0xDE00, TEGRA_DVC_BASE = TEGRA_APB_MISC_BASE + 0xD000, TEGRA_PMC_BASE = TEGRA_APB_MISC_BASE + 0xE400, TEGRA_EMC_BASE = TEGRA_APB_MISC_BASE + 0xF400, @@ -69,4 +74,9 @@ enum { TEGRA_I2C_BASE_COUNT = 6, }; +enum { + FB_SIZE_MB = (32), + FB_BASE_MB = (CONFIG_SYS_SDRAM_BASE/MiB + (CONFIG_DRAM_SIZE_MB - FB_SIZE_MB)), +}; + #endif /* __SOC_NVIDIA_TEGRA124_INCLUDE_SOC_ADDRESS_MAP_H__ */ diff --git a/src/soc/nvidia/tegra124/include/soc/clock.h b/src/soc/nvidia/tegra124/include/soc/clock.h new file mode 100644 index 0000000..056a38b --- /dev/null +++ b/src/soc/nvidia/tegra124/include/soc/clock.h @@ -0,0 +1,171 @@ +/* + * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef __SOC_NVIDIA_TEGRA124_CLOCK_H__ +#define __SOC_NVIDIA_TEGRA124_CLOCK_H__ + +enum { + CLK_L_CPU = 0x1 << 0, + CLK_L_COP = 0x1 << 1, + CLK_L_TRIG_SYS = 0x1 << 2, + CLK_L_RTC = 0x1 << 4, + CLK_L_TMR = 0x1 << 5, + CLK_L_UARTA = 0x1 << 6, + CLK_L_UARTB = 0x1 << 7, + CLK_L_GPIO = 0x1 << 8, + CLK_L_SDMMC2 = 0x1 << 9, + CLK_L_SPDIF = 0x1 << 10, + CLK_L_I2S1 = 0x1 << 11, + CLK_L_I2C1 = 0x1 << 12, + CLK_L_NDFLASH = 0x1 << 13, + CLK_L_SDMMC1 = 0x1 << 14, + CLK_L_SDMMC4 = 0x1 << 15, + CLK_L_PWM = 0x1 << 17, + CLK_L_I2S2 = 0x1 << 18, + CLK_L_EPP = 0x1 << 19, + CLK_L_VI = 0x1 << 20, + CLK_L_2D = 0x1 << 21, + CLK_L_USBD = 0x1 << 22, + CLK_L_ISP = 0x1 << 23, + CLK_L_3D = 0x1 << 24, + CLK_L_DISP2 = 0x1 << 26, + CLK_L_DISP1 = 0x1 << 27, + CLK_L_HOST1X = 0x1 << 28, + CLK_L_VCP = 0x1 << 29, + CLK_L_I2S0 = 0x1 << 30, + CLK_L_CACHE2 = 0x1 << 31, + + CLK_H_MEM = 0x1 << 0, + CLK_H_AHBDMA = 0x1 << 1, + CLK_H_APBDMA = 0x1 << 2, + CLK_H_KBC = 0x1 << 4, + CLK_H_STAT_MON = 0x1 << 5, + CLK_H_PMC = 0x1 << 6, + CLK_H_FUSE = 0x1 << 7, + CLK_H_KFUSE = 0x1 << 8, + CLK_H_SBC1 = 0x1 << 9, + CLK_H_SNOR = 0x1 << 10, + CLK_H_JTAG2TBC = 0x1 << 11, + CLK_H_SBC2 = 0x1 << 12, + CLK_H_SBC3 = 0x1 << 14, + CLK_H_I2C5 = 0x1 << 15, + CLK_H_DSI = 0x1 << 16, + CLK_H_HSI = 0x1 << 18, + CLK_H_HDMI = 0x1 << 19, + CLK_H_CSI = 0x1 << 20, + CLK_H_I2C2 = 0x1 << 22, + CLK_H_UARTC = 0x1 << 23, + CLK_H_MIPI_CAL = 0x1 << 24, + CLK_H_EMC = 0x1 << 25, + CLK_H_USB2 = 0x1 << 26, + CLK_H_USB3 = 0x1 << 27, + CLK_H_MPE = 0x1 << 28, + CLK_H_VDE = 0x1 << 29, + CLK_H_BSEA = 0x1 << 30, + CLK_H_BSEV = 0x1 << 31, + + CLK_U_UARTD = 0x1 << 1, + CLK_U_UARTE = 0x1 << 2, + CLK_U_I2C3 = 0x1 << 3, + CLK_U_SBC4 = 0x1 << 4, + CLK_U_SDMMC3 = 0x1 << 5, + CLK_U_PCIE = 0x1 << 6, + CLK_U_OWR = 0x1 << 7, + CLK_U_AFI = 0x1 << 8, + CLK_U_CSITE = 0x1 << 9, + CLK_U_PCIEXCLK = 0x1 << 10, + CLK_U_AVPUCQ = 0x1 << 11, + CLK_U_TRACECLKIN = 0x1 << 13, + CLK_U_SOC_THERM = 0x1 << 14, + CLK_U_DTV = 0x1 << 15, + CLK_U_NAND_SPEED = 0x1 << 16, + CLK_U_I2C_SLOW = 0x1 << 17, + CLK_U_DSIB = 0x1 << 18, + CLK_U_TSEC = 0x1 << 19, + CLK_U_IRAMA = 0x1 << 20, + CLK_U_IRAMB = 0x1 << 21, + CLK_U_IRAMC = 0x1 << 22, + + // Clock reset. + CLK_U_EMUCIF = 0x1 << 23, + // Clock enable. + CLK_U_IRAMD = 0x1 << 23, + + CLK_U_CRAM2 = 0x2 << 24, + CLK_U_XUSB_HOST = 0x1 << 25, + CLK_U_MSENC = 0x1 << 27, + CLK_U_SUS_OUT = 0x1 << 28, + CLK_U_DEV2_OUT = 0x1 << 29, + CLK_U_DEV1_OUT = 0x1 << 30, + CLK_U_XUSB_DEV = 0x1 << 31, + + CLK_V_CPUG = 0x1 << 0, + CLK_V_CPULP = 0x1 << 1, + CLK_V_3D2 = 0x1 << 2, + CLK_V_MSELECT = 0x1 << 3, + CLK_V_I2S3 = 0x1 << 5, + CLK_V_I2S4 = 0x1 << 6, + CLK_V_I2C4 = 0x1 << 7, + CLK_V_SBC5 = 0x1 << 8, + CLK_V_SBC6 = 0x1 << 9, + CLK_V_AUDIO = 0x1 << 10, + CLK_V_APBIF = 0x1 << 11, + CLK_V_DAM0 = 0x1 << 12, + CLK_V_DAM1 = 0x1 << 13, + CLK_V_DAM2 = 0x1 << 14, + CLK_V_HDA2CODEC_2X = 0x1 << 15, + CLK_V_ATOMICS = 0x1 << 16, + CLK_V_ACTMON = 0x1 << 23, + CLK_V_SATA = 0x1 << 28, + CLK_V_HDA = 0x1 << 29, + + CLK_W_HDA2HDMICODEC = 0x1 << 0, + CLK_W_SATACOLD = 0x1 << 1, + CLK_W_CEC = 0x1 << 8, + CLK_W_XUSB_PADCTL = 0x1 << 14, + CLK_W_ENTROPY = 0x1 << 21, + CLK_W_AMX0 = 0x1 << 25, + CLK_W_ADX0 = 0x1 << 26, + CLK_W_DVFS = 0x1 << 27, + CLK_W_XUSB_SS = 0x1 << 28, + CLK_W_MC1 = 0x1 << 30, + CLK_W_EMC1 = 0x1 << 31 +}; + +/* PLL stabilization delay in usec */ +#define CLOCK_PLL_STABLE_DELAY_US 300 + +#define IO_STABILIZATION_DELAY (2) +/* Calculate clock fractional divider value from ref and target frequencies */ +#define CLK_DIVIDER(REF, FREQ) ((((REF) * 2) / FREQ) - 2) + +/* Calculate clock frequency value from reference and clock divider value */ +#define CLK_FREQUENCY(REF, REG) (((REF) * 2) / (REG + 2)) + +/* soc-specific */ +#define TEGRA_PLLX_KHZ (1900000) +#define TEGRA_PLLP_KHZ (408000) +#define TEGRA_PLLC_KHZ (600000) +#define TEGRA_PLLD_KHZ (925000) +#define TEGRA_PLLU_KHZ (960000) + +int clock_get_osc_khz(void); +void clock_early_uart(void); +void clock_cpu0_config_and_reset(void * entry); +void clock_config(void); +void clock_init(void); +void clock_ll_set_source_divisor(u32 *reg, u32 source, u32 divisor); +#endif /* __SOC_NVIDIA_TEGRA124_CLOCK_H__ */ diff --git a/src/soc/nvidia/tegra124/include/soc/display.h b/src/soc/nvidia/tegra124/include/soc/display.h new file mode 100644 index 0000000..8c7e3e7 --- /dev/null +++ b/src/soc/nvidia/tegra124/include/soc/display.h @@ -0,0 +1,22 @@ +/* + * Copyright 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef __SOC_NVIDIA_TEGRA124_INCLUDE_SOC_DISPLAY_H__ +#define __SOC_NVIDIA_TEGRA124_INCLUDE_SOC_DISPLAY_H__ + +void setup_display(struct soc_nvidia_tegra124_config *config); + +#endif /* __SOC_NVIDIA_TEGRA124_INCLUDE_SOC_DISPLAY_H__ */ diff --git a/src/soc/nvidia/tegra124/pmc.h b/src/soc/nvidia/tegra124/pmc.h new file mode 100644 index 0000000..1134abd --- /dev/null +++ b/src/soc/nvidia/tegra124/pmc.h @@ -0,0 +1,200 @@ +/* + * Copyright (c) 2010 - 2013, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef _TEGRA124_PMC_H_ +#define _TEGRA124_PMC_H_ + +#include <stdint.h> + +enum { + POWER_PARTID_CRAIL = 0, + POWER_PARTID_TD = 1, + POWER_PARTID_VE = 2, + POWER_PARTID_VDE = 4, + POWER_PARTID_L2C = 5, + POWER_PARTID_MPE = 6, + POWER_PARTID_HEG = 7, + POWER_PARTID_CE1 = 9, + POWER_PARTID_CE2 = 10, + POWER_PARTID_CE3 = 11, + POWER_PARTID_CELP = 12, + POWER_PARTID_CE0 = 14, + POWER_PARTID_C0NC = 15, + POWER_PARTID_C1NC = 16, + POWER_PARTID_DIS = 18, + POWER_PARTID_DISB = 19, + POWER_PARTID_XUSBA = 20, + POWER_PARTID_XUSBB = 21, + POWER_PARTID_XUSBC = 22 +}; + +struct tegra_pmc_regs { + u32 cntrl; + u32 sec_disable; + u32 pmc_swrst; + u32 wake_mask; + u32 wake_lvl; + u32 wake_status; + u32 sw_wake_status; + u32 dpd_pads_oride; + u32 dpd_sample; + u32 dpd_enable; + u32 pwrgate_timer_off; + u32 clamp_status; + u32 pwrgate_toggle; + u32 remove_clamping_cmd; + u32 pwrgate_status; + u32 pwrgood_timer; + u32 blink_timer; + u32 no_iopower; + u32 pwr_det; + u32 pwr_det_latch; + u32 scratch[24]; + u32 secure_scratch[6]; + u32 cpupwrgood_timer; + u32 cpupwroff_timer; + u32 pg_mask; + u32 pg_mask_1; + u32 auto_wake_lvl; + u32 auto_wake_lvl_mask; + u32 wake_delay; + u32 pwr_det_val; + u32 ddr_pwr; + u32 usb_debounce_del; + u32 usb_a0; + u32 crypto_op; + u32 pllp_wb0_override; + u32 scratch24[43 - 24]; + u32 bondout_mirror[3]; + u32 sys_33v_en; + u32 bondout_mirror_access; + u32 gate; + u32 wake2_mask; + u32 wake2_lvl; + u32 wake2_status; + u32 sw_wake2_status; + u32 auto_wake2_lvl_mask; + u32 pg_mask_2; + u32 pg_mask_ce1; + u32 pg_mask_ce2; + u32 pg_mask_ce3; + u32 pwrgate_timer_ce[7]; + u32 pcx_edpd_cntrl; + u32 osc_edpd_over; + u32 clk_out_cntrl; + u32 sata_pwrgt; + u32 sensor_ctrl; + u32 rst_status; + u32 io_dpd_req; + u32 io_dpd_status; + u32 io_dpd2_req; + u32 io_dpd2_status; + u32 sel_dpd_tim; + u32 vddp_sel; + u32 ddr_cfg; + u32 e_no_vttgen; + u8 _rsv0[4]; + u32 pllm_wb0_override_freq; + u32 test_pwrgate; + u32 pwrgate_timer_mult; + u32 dis_sel_dpd; + u32 utmip_uhsic_triggers; + u32 utmip_uhsic_saved_state; + u32 utmip_pad_cfg; + u32 utmip_term_pad_cfg; + u32 utmip_uhsic_sleep_cfg; + u32 utmip_uhsic_sleepwalk_cfg; + u32 utmip_sleepwalk_p[3]; + u32 uhsic_sleepwalk_p0; + u32 utmip_uhsic_status; + u32 utmip_uhsic_fake; + u32 bondout_mirror3[5 - 3]; + u32 secure_scratch6[8 - 6]; + u32 scratch43[56 - 43]; + u32 scratch_eco[3]; + u32 utmip_uhsic_line_wakeup; + u32 utmip_bias_master_cntrl; + u32 utmip_master_config; + u32 td_pwrgate_inter_part_timer; + u32 utmip_uhsic2_triggers; + u32 utmip_uhsic2_saved_state; + u32 utmip_uhsic2_sleep_cfg; + u32 utmip_uhsic2_sleepwalk_cfg; + u32 uhsic2_sleepwalk_p1; + u32 utmip_uhsic2_status; + u32 utmip_uhsic2_fake; + u32 utmip_uhsic2_line_wakeup; + u32 utmip_master2_config; + u32 utmip_uhsic_rpd_cfg; + u32 pg_mask_ce0; + u32 pg_mask3[5 - 3]; + u32 pllm_wb0_override2; + u32 tsc_mult; + u32 cpu_vsense_override; + u32 glb_amap_cfg; + u32 sticky_bits; + u32 sec_disable2; + u32 weak_bias; + u32 reg_short; + u32 pg_mask_andor; + u8 _rsv1[0x2c]; + u32 secure_scratch8[24 - 8]; + u32 scratch56[120 - 56]; +}; + +enum { + PMC_PWRGATE_TOGGLE_PARTID_MASK = 0x1f, + PMC_PWRGATE_TOGGLE_PARTID_SHIFT = 0, + PMC_PWRGATE_TOGGLE_START = 0x1 << 8 +}; + +enum { + PMC_CNTRL_KBC_CLK_DIS = 0x1 << 0, + PMC_CNTRL_RTC_CLK_DIS = 0x1 << 1, + PMC_CNTRL_RTC_RST = 0x1 << 2, + PMC_CNTRL_KBC_RST = 0x1 << 3, + PMC_CNTRL_MAIN_RST = 0x1 << 4, + PMC_CNTRL_LATCHWAKE_EN = 0x1 << 5, + PMC_CNTRL_GLITCHDET_DIS = 0x1 << 6, + PMC_CNTRL_BLINK_EN = 0x1 << 7, + PMC_CNTRL_PWRREQ_POLARITY = 0x1 << 8, + PMC_CNTRL_PWRREQ_OE = 0x1 << 9, + PMC_CNTRL_SYSCLK_POLARITY = 0x1 << 10, + PMC_CNTRL_SYSCLK_OE = 0x1 << 11, + PMC_CNTRL_PWRGATE_DIS = 0x1 << 12, + PMC_CNTRL_AOINIT = 0x1 << 13, + PMC_CNTRL_SIDE_EFFECT_LP0 = 0x1 << 14, + PMC_CNTRL_CPUPWRREQ_POLARITY = 0x1 << 15, + PMC_CNTRL_CPUPWRREQ_OE = 0x1 << 16, + PMC_CNTRL_INTR_POLARITY = 0x1 << 17, + PMC_CNTRL_FUSE_OVERRIDE = 0x1 << 18, + PMC_CNTRL_CPUPWRGOOD_EN = 0x1 << 19, + PMC_CNTRL_CPUPWRGOOD_SEL_SHIFT = 20, + PMC_CNTRL_CPUPWRGOOD_SEL_MASK = + 0x3 << PMC_CNTRL_CPUPWRGOOD_SEL_SHIFT +}; + +enum { + PMC_CNTRL2_HOLD_CKE_LOW_EN = 0x1 << 12 +}; + +enum { + PMC_OSC_EDPD_OVER_XOFS_SHIFT = 1, + PMC_OSC_EDPD_OVER_XOFS_MASK = + 0x3f << PMC_OSC_EDPD_OVER_XOFS_SHIFT +}; + +#endif /* _TEGRA124_PMC_H_ */ diff --git a/src/soc/nvidia/tegra124/power.c b/src/soc/nvidia/tegra124/power.c new file mode 100644 index 0000000..a3cf5ef --- /dev/null +++ b/src/soc/nvidia/tegra124/power.c @@ -0,0 +1,87 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2013 Google Inc. + * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <console/console.h> +#include <soc/addressmap.h> + +#include "pmc.h" +#include "power.h" + +static struct tegra_pmc_regs * const pmc = (void *)TEGRA_PMC_BASE; + +static int partition_powered(int id) +{ + return read32(&pmc->pwrgate_status) & (0x1 << id); +} + +static void power_ungate_partition(uint32_t id) +{ + printk(BIOS_INFO, "Ungating power partition %d.\n", id); + + if (!partition_powered(id)) { + uint32_t pwrgate_toggle = read32(&pmc->pwrgate_toggle); + pwrgate_toggle &= ~(PMC_PWRGATE_TOGGLE_PARTID_MASK); + pwrgate_toggle |= (id << PMC_PWRGATE_TOGGLE_PARTID_SHIFT); + pwrgate_toggle |= PMC_PWRGATE_TOGGLE_START; + write32(pwrgate_toggle, &pmc->pwrgate_toggle); + + // Wait for the request to be accepted. + while (read32(&pmc->pwrgate_toggle) & PMC_PWRGATE_TOGGLE_START) + ; + printk(BIOS_DEBUG, "Power gate toggle request accepted.\n"); + + // Wait for the partition to be powered. + while (!partition_powered(id)) + ; + } + + printk(BIOS_INFO, "Ungated power partition %d.\n", id); +} + +void power_enable_cpu_rail(void) +{ + // Set the power gate timer multiplier to 8 (why 8?). + uint32_t pwrgate_timer_mult = read32(&pmc->pwrgate_timer_mult); + pwrgate_timer_mult |= (0x3 << 0); + + /* + * From U-Boot: + * Set CPUPWRGOOD_TIMER - APB clock is 1/2 of SCLK (102MHz), + * set it for 5ms as per SysEng (102MHz/5mS = 510000). + */ + write32(510000, &pmc->cpupwrgood_timer); + + power_ungate_partition(POWER_PARTID_CRAIL); + + uint32_t cntrl = read32(&pmc->cntrl); + cntrl &= ~PMC_CNTRL_CPUPWRREQ_POLARITY; + cntrl |= PMC_CNTRL_CPUPWRREQ_OE; + write32(cntrl, &pmc->cntrl); +} + +void power_ungate_cpu(void) +{ + // Ungate power to the non-core parts of the fast cluster. + power_ungate_partition(POWER_PARTID_C0NC); + + // Ungate power to CPU0 in the fast cluster. + power_ungate_partition(POWER_PARTID_CE0); +} diff --git a/src/soc/nvidia/tegra124/power.h b/src/soc/nvidia/tegra124/power.h new file mode 100644 index 0000000..6454699 --- /dev/null +++ b/src/soc/nvidia/tegra124/power.h @@ -0,0 +1,29 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef __SOC_NVIDIA_TEGRA124_POWER_H__ +#define __SOC_NVIDIA_TEGRA124_POWER_H__ + +// This function does not enable the external power to the rail, it enables +// the rail itself internal to the SOC. +void power_enable_cpu_rail(void); + +void power_ungate_cpu(void); + +#endif /* __SOC_NVIDIA_TEGRA124_POWER_H__ */ diff --git a/src/soc/nvidia/tegra124/soc.c b/src/soc/nvidia/tegra124/soc.c new file mode 100644 index 0000000..e996c11 --- /dev/null +++ b/src/soc/nvidia/tegra124/soc.c @@ -0,0 +1,66 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. + * Copyright 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <device/device.h> +#include <soc/nvidia/tegra/dc.h> +#include <soc/addressmap.h> + +/* this sucks, but for now, fb size/location are hardcoded. + * Will break if we get 2. Sigh. + * We assume it's all multiples of MiB for MMUs sake. + */ +static void soc_enable(device_t dev) +{ + unsigned long fb_size = FB_SIZE_MB; + u32 lcdbase = FB_BASE_MB; + ram_resource(dev, 0, CONFIG_SYS_SDRAM_BASE/KiB, + (CONFIG_DRAM_SIZE_MB - fb_size)*KiB); + mmio_resource(dev, 1, lcdbase*KiB, fb_size*KiB); +} + +static void soc_init(device_t dev) +{ + display_startup(dev); + printk(BIOS_INFO, "CPU: Tegra124\n"); +} + +static void soc_noop(device_t dev) +{ +} + +static struct device_operations soc_ops = { + .read_resources = soc_noop, + .set_resources = soc_noop, + .enable_resources = soc_enable, + .init = soc_init, + .scan_bus = 0, +}; + +static void enable_tegra124_dev(device_t dev) +{ + dev->ops = &soc_ops; +} + +struct chip_operations soc_nvidia_tegra124_ops = { + CHIP_NAME("SOC Nvidia Tegra124") + .enable_dev = enable_tegra124_dev, +}; diff --git a/src/soc/nvidia/tegra124/spi.c b/src/soc/nvidia/tegra124/spi.c new file mode 100644 index 0000000..f7e0750 --- /dev/null +++ b/src/soc/nvidia/tegra124/spi.c @@ -0,0 +1,815 @@ +/* + * NVIDIA Tegra SPI controller (T114 and later) + * + * Copyright (c) 2010-2013 NVIDIA Corporation + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <assert.h> +#include <cbfs.h> +#include <cbfs_core.h> +#include <inttypes.h> +#include <spi-generic.h> +#include <stdint.h> +#include <stdlib.h> +#include <string.h> +#include <arch/io.h> +#include <console/console.h> +#include <soc/addressmap.h> +#include <delay.h> + +#include "dma.h" +#include "spi.h" + +#if defined(CONFIG_DEBUG_SPI) && CONFIG_DEBUG_SPI +# define DEBUG_SPI(x,...) printk(BIOS_DEBUG, "TEGRA_SPI: " x) +#else +# define DEBUG_SPI(x,...) +#endif + +/* + * 64 packets in FIFO mode, BLOCK_SIZE packets in DMA mode. Packets can vary + * in size from 4 to 32 bits. To keep things simple we'll use 8-bit packets. + */ +#define SPI_PACKET_SIZE_BYTES 1 +#define SPI_MAX_TRANSFER_BYTES_FIFO (64 * SPI_PACKET_SIZE_BYTES) +#define SPI_MAX_TRANSFER_BYTES_DMA ((65536 * SPI_PACKET_SIZE_BYTES) - \ + TEGRA_DMA_ALIGN_BYTES) + +/* COMMAND1 */ +#define SPI_CMD1_GO (1 << 31) +#define SPI_CMD1_M_S (1 << 30) +#define SPI_CMD1_MODE_MASK 0x3 +#define SPI_CMD1_MODE_SHIFT 28 +#define SPI_CMD1_CS_SEL_MASK 0x3 +#define SPI_CMD1_CS_SEL_SHIFT 26 +#define SPI_CMD1_CS_POL_INACTIVE3 (1 << 25) +#define SPI_CMD1_CS_POL_INACTIVE2 (1 << 24) +#define SPI_CMD1_CS_POL_INACTIVE1 (1 << 23) +#define SPI_CMD1_CS_POL_INACTIVE0 (1 << 22) +#define SPI_CMD1_CS_SW_HW (1 << 21) +#define SPI_CMD1_CS_SW_VAL (1 << 20) +#define SPI_CMD1_IDLE_SDA_MASK 0x3 +#define SPI_CMD1_IDLE_SDA_SHIFT 18 +#define SPI_CMD1_BIDIR (1 << 17) +#define SPI_CMD1_LSBI_FE (1 << 16) +#define SPI_CMD1_LSBY_FE (1 << 15) +#define SPI_CMD1_BOTH_EN_BIT (1 << 14) +#define SPI_CMD1_BOTH_EN_BYTE (1 << 13) +#define SPI_CMD1_RX_EN (1 << 12) +#define SPI_CMD1_TX_EN (1 << 11) +#define SPI_CMD1_PACKED (1 << 5) +#define SPI_CMD1_BIT_LEN_MASK 0x1f +#define SPI_CMD1_BIT_LEN_SHIFT 0 + +/* COMMAND2 */ +#define SPI_CMD2_TX_CLK_TAP_DELAY (1 << 6) +#define SPI_CMD2_TX_CLK_TAP_DELAY_MASK (0x3F << 6) +#define SPI_CMD2_RX_CLK_TAP_DELAY (1 << 0) +#define SPI_CMD2_RX_CLK_TAP_DELAY_MASK (0x3F << 0) + +/* SPI_TRANS_STATUS */ +#define SPI_STATUS_RDY (1 << 30) +#define SPI_STATUS_SLV_IDLE_COUNT_MASK 0xff +#define SPI_STATUS_SLV_IDLE_COUNT_SHIFT 16 +#define SPI_STATUS_BLOCK_COUNT 0xffff +#define SPI_STATUS_BLOCK_COUNT_SHIFT 0 + +/* SPI_FIFO_STATUS */ +#define SPI_FIFO_STATUS_CS_INACTIVE (1 << 31) +#define SPI_FIFO_STATUS_FRAME_END (1 << 30) +#define SPI_FIFO_STATUS_RX_FIFO_FLUSH (1 << 15) +#define SPI_FIFO_STATUS_TX_FIFO_FLUSH (1 << 14) +#define SPI_FIFO_STATUS_ERR (1 << 8) +#define SPI_FIFO_STATUS_TX_FIFO_OVF (1 << 7) +#define SPI_FIFO_STATUS_TX_FIFO_UNR (1 << 6) +#define SPI_FIFO_STATUS_RX_FIFO_OVF (1 << 5) +#define SPI_FIFO_STATUS_RX_FIFO_UNR (1 << 4) +#define SPI_FIFO_STATUS_TX_FIFO_FULL (1 << 3) +#define SPI_FIFO_STATUS_TX_FIFO_EMPTY (1 << 2) +#define SPI_FIFO_STATUS_RX_FIFO_FULL (1 << 1) +#define SPI_FIFO_STATUS_RX_FIFO_EMPTY (1 << 0) + +/* SPI_DMA_CTL */ +#define SPI_DMA_CTL_DMA (1 << 31) +#define SPI_DMA_CTL_CONT (1 << 30) +#define SPI_DMA_CTL_IE_RX (1 << 29) +#define SPI_DMA_CTL_IE_TX (1 << 28) +#define SPI_DMA_CTL_RX_TRIG_MASK 0x3 +#define SPI_DMA_CTL_RX_TRIG_SHIFT 19 +#define SPI_DMA_CTL_TX_TRIG_MASK 0x3 +#define SPI_DMA_CTL_TX_TRIG_SHIFT 15 + +/* SPI_DMA_BLK */ +#define SPI_DMA_CTL_BLOCK_SIZE_MASK 0xff +#define SPI_DMA_CTL_BLOCK_SIZE_SHIFT 0 + +struct tegra_spi_regs { + u32 command1; /* 0x000: SPI_COMMAND1 */ + u32 command2; /* 0x004: SPI_COMMAND2 */ + u32 timing1; /* 0x008: SPI_CS_TIM1 */ + u32 timing2; /* 0x00c: SPI_CS_TIM2 */ + u32 trans_status; /* 0x010: SPI_TRANS_STATUS */ + u32 fifo_status; /* 0x014: SPI_FIFO_STATUS */ + u32 tx_data; /* 0x018: SPI_TX_DATA */ + u32 rx_data; /* 0x01c: SPI_RX_DATA */ + u32 dma_ctl; /* 0x020: SPI_DMA_CTL */ + u32 dma_blk; /* 0x024: SPI_DMA_BLK */ + u32 rsvd[56]; /* 0x028-0x107: reserved */ + u32 tx_fifo; /* 0x108: SPI_FIFO1 */ + u32 rsvd2[31]; /* 0x10c-0x187 reserved */ + u32 rx_fifo; /* 0x188: SPI_FIFO2 */ + u32 spare_ctl; /* 0x18c: SPI_SPARE_CTRL */ +} __attribute__((packed)); + +struct tegra_spi_channel { + struct spi_slave slave; + struct tegra_spi_regs *regs; +}; + +static struct tegra_spi_channel tegra_spi_channels[] = { + /* + * Note: Tegra pinmux must be setup for corresponding SPI channel in + * order for its registers to be accessible. If pinmux has not been + * set up, access to the channel's registers will simply hang. + * + * TODO(dhendrix): Clarify or remove this comment (is clock setup + * necessary first, or just pinmux, or both?) + */ + { + .slave = { .bus = 1, }, + .regs = (struct tegra_spi_regs *)TEGRA_SPI1_BASE, + }, + { + .slave = { .bus = 2, }, + .regs = (struct tegra_spi_regs *)TEGRA_SPI2_BASE, + }, + { + .slave = { .bus = 3, }, + .regs = (struct tegra_spi_regs *)TEGRA_SPI3_BASE, + }, + { + .slave = { .bus = 4, }, + .regs = (struct tegra_spi_regs *)TEGRA_SPI4_BASE, + }, + { + .slave = { .bus = 5, }, + .regs = (struct tegra_spi_regs *)TEGRA_SPI5_BASE, + }, + { + .slave = { .bus = 6, }, + .regs = (struct tegra_spi_regs *)TEGRA_SPI6_BASE, + }, +}; + +static void flush_fifos(struct tegra_spi_regs *regs) +{ + setbits_le32(&regs->fifo_status, SPI_FIFO_STATUS_RX_FIFO_FLUSH | + SPI_FIFO_STATUS_TX_FIFO_FLUSH); + while (read32(&regs->fifo_status) & + (SPI_FIFO_STATUS_RX_FIFO_FLUSH | SPI_FIFO_STATUS_TX_FIFO_FLUSH)) + ; +} + +void tegra_spi_init(unsigned int bus) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(tegra_spi_channels); i++) { + struct tegra_spi_regs *regs; + + if (tegra_spi_channels[i].slave.bus == bus) + regs = tegra_spi_channels[i].regs; + else + continue; + + /* software drives chip-select, set value to high */ + setbits_le32(&regs->command1, + SPI_CMD1_CS_SW_HW | SPI_CMD1_CS_SW_VAL); + + /* 8-bit transfers, unpacked mode, most significant bit first */ + clrbits_le32(&regs->command1, + SPI_CMD1_BIT_LEN_MASK | SPI_CMD1_PACKED); + setbits_le32(&regs->command1, 7 << SPI_CMD1_BIT_LEN_SHIFT); + + flush_fifos(regs); + } + printk(BIOS_INFO, "Tegra SPI bus %d initialized.\n", bus); + +} + +static struct tegra_spi_channel * const to_tegra_spi(int bus) { + return &tegra_spi_channels[bus - 1]; +} + +static unsigned int tegra_spi_speed(unsigned int bus) +{ + /* FIXME: implement this properly, for now use max value (50MHz) */ + return 50000000; +} + +/* + * This calls udelay() with a calculated value based on the SPI speed and + * number of bytes remaining to be transferred. It assumes that if the + * calculated delay period is less than MIN_DELAY_US then it is probably + * not worth the overhead of yielding. + */ +#define MIN_DELAY_US 250 +static void tegra_spi_delay(struct tegra_spi_channel *spi, + unsigned int bytes_remaining) +{ + unsigned int ns_per_byte, delay_us; + + ns_per_byte = 1000000000 / (tegra_spi_speed(spi->slave.bus) / 8); + delay_us = (ns_per_byte * bytes_remaining) / 1000; + + if (delay_us < MIN_DELAY_US) + return; + + udelay(delay_us); +} + +void spi_cs_activate(struct spi_slave *slave) +{ + struct tegra_spi_regs *regs = to_tegra_spi(slave->bus)->regs; + u32 val; + + val = read32(&regs->command1); + + /* select appropriate chip-select line */ + val &= ~(SPI_CMD1_CS_SEL_MASK << SPI_CMD1_CS_SEL_SHIFT); + val |= (slave->cs << SPI_CMD1_CS_SEL_SHIFT); + + /* drive chip-select with the inverse of the "inactive" value */ + if (val & (SPI_CMD1_CS_POL_INACTIVE0 << slave->cs)) + val &= ~SPI_CMD1_CS_SW_VAL; + else + val |= SPI_CMD1_CS_SW_VAL; + + write32(val, &regs->command1); +} + +void spi_cs_deactivate(struct spi_slave *slave) +{ + struct tegra_spi_regs *regs = to_tegra_spi(slave->bus)->regs; + u32 val; + + val = read32(&regs->command1); + + if (val & (SPI_CMD1_CS_POL_INACTIVE0 << slave->cs)) + val |= SPI_CMD1_CS_SW_VAL; + else + val &= ~SPI_CMD1_CS_SW_VAL; + + write32(val, &regs->command1); +} + +static void dump_fifo_status(struct tegra_spi_channel *spi) +{ + u32 status = read32(&spi->regs->fifo_status); + + printk(BIOS_INFO, "Raw FIFO status: 0x%08x\n", status); + if (status & SPI_FIFO_STATUS_TX_FIFO_OVF) + printk(BIOS_INFO, "\tTx overflow detected\n"); + if (status & SPI_FIFO_STATUS_TX_FIFO_UNR) + printk(BIOS_INFO, "\tTx underrun detected\n"); + if (status & SPI_FIFO_STATUS_RX_FIFO_OVF) + printk(BIOS_INFO, "\tRx overflow detected\n"); + if (status & SPI_FIFO_STATUS_RX_FIFO_UNR) + printk(BIOS_INFO, "\tRx underrun detected\n"); + + printk(BIOS_INFO, "TX_FIFO: 0x%08x, TX_DATA: 0x%08x\n", + read32(&spi->regs->tx_fifo), read32(&spi->regs->tx_data)); + printk(BIOS_INFO, "RX_FIFO: 0x%08x, RX_DATA: 0x%08x\n", + read32(&spi->regs->rx_fifo), read32(&spi->regs->rx_data)); +} + +static void clear_fifo_status(struct tegra_spi_channel *spi) +{ + clrbits_le32(&spi->regs->fifo_status, + SPI_FIFO_STATUS_ERR | + SPI_FIFO_STATUS_TX_FIFO_OVF | + SPI_FIFO_STATUS_TX_FIFO_UNR | + SPI_FIFO_STATUS_RX_FIFO_OVF | + SPI_FIFO_STATUS_RX_FIFO_UNR); +} + +static void dump_spi_regs(struct tegra_spi_channel *spi) +{ + printk(BIOS_INFO, "SPI regs:\n" + "\tdma_blk: 0x%08x\n" + "\tcommand1: 0x%08x\n" + "\tdma_ctl: 0x%08x\n" + "\ttrans_status: 0x%08x\n", + read32(&spi->regs->dma_blk), + read32(&spi->regs->command1), + read32(&spi->regs->dma_ctl), + read32(&spi->regs->trans_status)); +} + +static void dump_dma_regs(struct apb_dma_channel *dma) +{ + printk(BIOS_INFO, "DMA regs:\n" + "\tahb_ptr: 0x%08x\n" + "\tapb_ptr: 0x%08x\n" + "\tahb_seq: 0x%08x\n" + "\tapb_seq: 0x%08x\n" + "\tcsr: 0x%08x\n" + "\tcsre: 0x%08x\n" + "\twcount: 0x%08x\n" + "\tdma_byte_sta: 0x%08x\n" + "\tword_transfer: 0x%08x\n", + read32(&dma->regs->ahb_ptr), + read32(&dma->regs->apb_ptr), + read32(&dma->regs->ahb_seq), + read32(&dma->regs->apb_seq), + read32(&dma->regs->csr), + read32(&dma->regs->csre), + read32(&dma->regs->wcount), + read32(&dma->regs->dma_byte_sta), + read32(&dma->regs->word_transfer)); +} + +static void dump_regs(struct tegra_spi_channel *spi, + struct apb_dma_channel *dma) +{ + if (dma) + dump_dma_regs(dma); + if (spi) { + dump_spi_regs(spi); + dump_fifo_status(spi); + } +} + +static int fifo_error(struct tegra_spi_channel *spi) +{ + return read32(&spi->regs->fifo_status) & SPI_FIFO_STATUS_ERR ? 1 : 0; +} + +static inline unsigned int spi_byte_count(struct tegra_spi_channel *spi) +{ + /* FIXME: Make this take total packet size into account */ + return read32(&spi->regs->trans_status) & + (SPI_STATUS_BLOCK_COUNT << SPI_STATUS_BLOCK_COUNT_SHIFT); +} + +static int tegra_spi_fifo_receive(struct tegra_spi_channel *spi, + u8 *din, unsigned int in_bytes) +{ + unsigned int received = 0, remaining = in_bytes; + + printk(BIOS_SPEW, "%s: Receiving %d bytes\n", __func__, in_bytes); + setbits_le32(&spi->regs->command1, SPI_CMD1_RX_EN); + + while (remaining) { + unsigned int from_fifo, count; + + from_fifo = MIN(in_bytes, SPI_MAX_TRANSFER_BYTES_FIFO); + remaining -= from_fifo; + + /* BLOCK_SIZE in SPI_DMA_BLK register applies to both DMA and + * PIO transfers */ + write32(from_fifo - 1, &spi->regs->dma_blk); + + setbits_le32(&spi->regs->trans_status, SPI_STATUS_RDY); + setbits_le32(&spi->regs->command1, SPI_CMD1_GO); + + while ((count = spi_byte_count(spi)) != from_fifo) { + tegra_spi_delay(spi, from_fifo - count); + if (fifo_error(spi)) + goto done; + } + + received += from_fifo; + while (from_fifo) { + *din = read8(&spi->regs->rx_fifo); + din++; + from_fifo--; + } + } + +done: + clrbits_le32(&spi->regs->command1, SPI_CMD1_RX_EN); + if ((received != in_bytes) || fifo_error(spi)) { + printk(BIOS_ERR, "%s: ERROR: Received %u bytes, expected %u\n", + __func__, received, in_bytes); + dump_regs(spi, NULL); + return -1; + } + return in_bytes; +} + +static int tegra_spi_fifo_send(struct tegra_spi_channel *spi, + const u8 *dout, unsigned int out_bytes) +{ + unsigned int sent = 0, remaining = out_bytes; + + printk(BIOS_SPEW, "%s: Sending %d bytes\n", __func__, out_bytes); + setbits_le32(&spi->regs->command1, SPI_CMD1_TX_EN); + + while (remaining) { + unsigned int to_fifo, tmp; + + to_fifo = MIN(out_bytes, SPI_MAX_TRANSFER_BYTES_FIFO); + + /* BLOCK_SIZE in SPI_DMA_BLK register applies to both DMA and + * PIO transfers */ + write32(to_fifo - 1, &spi->regs->dma_blk); + + tmp = to_fifo; + while (tmp) { + write32(*dout, &spi->regs->tx_fifo); + dout++; + tmp--; + } + + setbits_le32(&spi->regs->trans_status, SPI_STATUS_RDY); + setbits_le32(&spi->regs->command1, SPI_CMD1_GO); + + while (!(read32(&spi->regs->fifo_status) & + SPI_FIFO_STATUS_TX_FIFO_EMPTY)) { + tegra_spi_delay(spi, to_fifo - spi_byte_count(spi)); + if (fifo_error(spi)) + goto done; + } + + remaining -= to_fifo; + sent += to_fifo; + } + +done: + clrbits_le32(&spi->regs->command1, SPI_CMD1_TX_EN); + if ((sent != out_bytes) || fifo_error(spi)) { + printk(BIOS_ERR, "%s: ERROR: Sent %u bytes, expected " + "to send %u\n", __func__, sent, out_bytes); + dump_regs(spi, NULL); + return -1; + } + return out_bytes; +} + +static void tegra2_spi_dma_setup(struct apb_dma_channel *dma) +{ + /* APB bus width = 8-bits, address wrap for each word */ + clrbits_le32(&dma->regs->apb_seq, 0x7 << 28); + /* AHB 1 word burst, bus width = 32 bits (fixed in hardware), + * no address wrapping */ + clrsetbits_le32(&dma->regs->ahb_seq, + (0x7 << 24) | (0x7 << 16), 0x4 << 24); + /* Set ONCE mode to transfer one "blocK" at a time (64KB). */ + setbits_le32(&dma->regs->csr, 1 << 27); +} + +/* + * Notes for DMA transmit and receive, experimentally determined (need to + * verify): + * - WCOUNT seems to be an "n-1" count, but the documentation does not + * make this clear. Without the -1 dma_byte_sta will show 1 AHB word + * (4 bytes) higher than it should and Tx overrun / Rx underrun will + * likely occur. + * + * - dma_byte_sta is always a multiple 4, so we check for + * dma_byte_sta < length + * + * - The RDY bit in SPI_TRANS_STATUS needs to be cleared manually + * (set bit to clear) between each transaction. Otherwise the next + * transaction does not start. + */ + +static int tegra_spi_dma_receive(struct tegra_spi_channel *spi, + const void *din, unsigned int in_bytes) +{ + struct apb_dma_channel *dma; + + dma = dma_claim(); + if (!dma) { + printk(BIOS_ERR, "%s: Unable to claim DMA channel\n", __func__); + return -1; + } + + printk(BIOS_SPEW, "%s: Receiving %d bytes\n", __func__, in_bytes); + tegra2_spi_dma_setup(dma); + + /* set AHB & APB address pointers */ + write32((u32)din, &dma->regs->ahb_ptr); + write32((u32)&spi->regs->rx_fifo, &dma->regs->apb_ptr); + + setbits_le32(&spi->regs->command1, SPI_CMD1_RX_EN); + + /* FIXME: calculate word count so that it corresponds to bus width */ + write32(in_bytes - 1, &dma->regs->wcount); + + /* specify BLOCK_SIZE in SPI_DMA_BLK */ + write32(in_bytes - 1, &spi->regs->dma_blk); + + /* Set DMA direction for APB (SPI) --> AHB (DRAM) */ + clrbits_le32(&dma->regs->csr, 1 << 28); + + /* write to SPI_TRANS_STATUS RDY bit to clear it */ + setbits_le32(&spi->regs->trans_status, SPI_STATUS_RDY); + + /* set DMA bit in SPI_DMA_CTL to start */ + setbits_le32(&spi->regs->dma_ctl, SPI_DMA_CTL_DMA); + + /* start APBDMA after SPI DMA so we don't read empty bytes + * from Rx FIFO */ + dma_start(dma); + + while (spi_byte_count(spi) != in_bytes) + tegra_spi_delay(spi, in_bytes - spi_byte_count(spi)); + clrbits_le32(&spi->regs->command1, SPI_CMD1_RX_EN); + + while ((read32(&dma->regs->dma_byte_sta) < in_bytes) || dma_busy(dma)) + ; /* this shouldn't take long, no udelay */ + dma_stop(dma); + dma_release(dma); + + if ((spi_byte_count(spi) != in_bytes) || fifo_error(spi)) { + printk(BIOS_ERR, "%s: ERROR: Received %u bytes, expected %u\n", + __func__, spi_byte_count(spi), in_bytes); + dump_regs(spi, dma); + return -1; + } + + return in_bytes; +} + +static int tegra_spi_dma_send(struct tegra_spi_channel *spi, + const u8 *dout, unsigned int out_bytes) +{ + struct apb_dma_channel *dma; + unsigned int count; + + dma = dma_claim(); + if (!dma) { + printk(BIOS_ERR, "%s: Unable to claim DMA channel\n", __func__); + return -1; + } + + printk(BIOS_SPEW, "%s: Sending %d bytes\n", __func__, out_bytes); + tegra2_spi_dma_setup(dma); + + /* set AHB & APB address pointers */ + write32((u32)dout, &dma->regs->ahb_ptr); + write32((u32)&spi->regs->tx_fifo, &dma->regs->apb_ptr); + + setbits_le32(&spi->regs->command1, SPI_CMD1_TX_EN); + + /* FIXME: calculate word count so that it corresponds to bus width */ + write32(out_bytes - 1, &dma->regs->wcount); + + /* specify BLOCK_SIZE in SPI_DMA_BLK */ + write32(out_bytes - 1, &spi->regs->dma_blk); + + /* Set DMA direction for AHB (DRAM) --> APB (SPI) */ + setbits_le32(&dma->regs->csr, (1 << 28)); + + /* write to SPI_TRANS_STATUS RDY bit to clear it */ + setbits_le32(&spi->regs->trans_status, SPI_STATUS_RDY); + + dma_start(dma); + /* set DMA bit in SPI_DMA_CTL to start */ + setbits_le32(&spi->regs->dma_ctl, SPI_DMA_CTL_DMA); + + while ((read32(&dma->regs->dma_byte_sta) < out_bytes) || dma_busy(dma)) + tegra_spi_delay(spi, out_bytes - spi_byte_count(spi)); + dma_stop(dma); + + while ((count = spi_byte_count(spi)) != out_bytes) + tegra_spi_delay(spi, out_bytes - count); + clrbits_le32(&spi->regs->command1, SPI_CMD1_TX_EN); + + dma_release(dma); + + if ((spi_byte_count(spi) != out_bytes) || fifo_error(spi)) { + printk(BIOS_ERR, "%s: ERROR: Sent %u bytes, expected %u\n", + __func__, spi_byte_count(spi), out_bytes); + dump_regs(spi, dma); + return -1; + } + + return out_bytes; +} + +int spi_xfer(struct spi_slave *slave, const void *dout, unsigned int bitsout, + void *din, unsigned int bitsin) +{ + unsigned int out_bytes = bitsout / 8, in_bytes = bitsin / 8; + struct tegra_spi_channel *spi = to_tegra_spi(slave->bus); + int ret = 0; + u8 *out_buf = (u8 *)dout; + u8 *in_buf = (u8 *)din; + + ASSERT(bitsout % 8 == 0 && bitsin % 8 == 0); + + /* tegra bus numbers start at 1 */ + ASSERT(slave->bus >= 1 && slave->bus <= ARRAY_SIZE(tegra_spi_channels)); + + flush_fifos(spi->regs); + + /* + * DMA operates on 4 bytes at a time, so to avoid accessing memory + * outside the specified buffers we'll only use DMA for 4-byte aligned + * transactions accesses and transfer remaining bytes manually using + * the Rx/Tx FIFOs. + */ + + while (out_bytes > 0) { + unsigned int dma_out, fifo_out; + + dma_out = MIN(out_bytes, SPI_MAX_TRANSFER_BYTES_DMA); + fifo_out = dma_out % TEGRA_DMA_ALIGN_BYTES; + dma_out -= fifo_out; + + if (dma_out) { + ret = tegra_spi_dma_send(spi, out_buf, dma_out); + if (ret != dma_out) { + ret = -1; + goto spi_xfer_exit; + } + out_buf += dma_out; + out_bytes -= dma_out; + } + if (fifo_out) { + ret = tegra_spi_fifo_send(spi, out_buf, fifo_out); + if (ret != fifo_out) { + ret = -1; + goto spi_xfer_exit; + } + out_buf += fifo_out; + out_bytes -= fifo_out; + } + } + + while (in_bytes > 0) { + unsigned int dma_in, fifo_in; + + dma_in = MIN(in_bytes, SPI_MAX_TRANSFER_BYTES_DMA); + fifo_in = dma_in % TEGRA_DMA_ALIGN_BYTES; + dma_in -= fifo_in; + + if (dma_in) { + ret = tegra_spi_dma_receive(spi, in_buf, dma_in); + if (ret != dma_in) { + ret = -1; + goto spi_xfer_exit; + } + in_buf += dma_in; + in_bytes -= dma_in; + } + if (fifo_in) { + ret = tegra_spi_fifo_receive(spi, in_buf, fifo_in); + if (ret != fifo_in) { + ret = -1; + goto spi_xfer_exit; + } + in_buf += fifo_in; + in_bytes -= fifo_in; + } + } + + ret = 0; + +spi_xfer_exit: + if (ret < 0) + clear_fifo_status(spi); + return ret; +} + +/* SPI as CBFS media. */ +struct tegra_spi_media { + struct spi_slave *slave; + struct cbfs_simple_buffer buffer; +}; + +static int tegra_spi_cbfs_open(struct cbfs_media *media) +{ + DEBUG_SPI("tegra_spi_cbfs_open\n"); + return 0; +} + +static int tegra_spi_cbfs_close(struct cbfs_media *media) +{ + DEBUG_SPI("tegra_spi_cbfs_close\n"); + return 0; +} + +#define JEDEC_READ 0x03 +#define JEDEC_READ_OUTSIZE 0x04 +/* JEDEC_READ_INSIZE : any length */ + +static size_t tegra_spi_cbfs_read(struct cbfs_media *media, void *dest, + size_t offset, size_t count) +{ + struct tegra_spi_media *spi = (struct tegra_spi_media *)media->context; + u8 spi_read_cmd[JEDEC_READ_OUTSIZE]; + int ret = count; + + /* TODO: Dual mode (BOTH_EN_BIT) and packed mode */ + spi_read_cmd[0] = JEDEC_READ; + spi_read_cmd[1] = (offset >> 16) & 0xff; + spi_read_cmd[2] = (offset >> 8) & 0xff; + spi_read_cmd[3] = offset & 0xff; + + /* assert /CS */ + spi_cs_activate(spi->slave); + + if (spi_xfer(spi->slave, spi_read_cmd, + sizeof(spi_read_cmd) * 8, NULL, 0) < 0) { + ret = -1; + printk(BIOS_ERR, "%s: Failed to transfer %u bytes\n", + __func__, sizeof(spi_read_cmd)); + goto tegra_spi_cbfs_read_exit; + } + + if (spi_xfer(spi->slave, NULL, 0, dest, count * 8)) { + ret = -1; + printk(BIOS_ERR, "%s: Failed to transfer %u bytes\n", + __func__, count); + } + +tegra_spi_cbfs_read_exit: + /* de-assert /CS */ + spi_cs_deactivate(spi->slave); + return (ret < 0) ? 0 : ret; +} + +static void *tegra_spi_cbfs_map(struct cbfs_media *media, size_t offset, + size_t count) +{ + struct tegra_spi_media *spi = (struct tegra_spi_media*)media->context; + void *map; + DEBUG_SPI("tegra_spi_cbfs_map\n"); + map = cbfs_simple_buffer_map(&spi->buffer, media, offset, count); + printk(BIOS_INFO, "%s: map: 0x%p\n", __func__, map); + return map; +} + +static void *tegra_spi_cbfs_unmap(struct cbfs_media *media, + const void *address) +{ + struct tegra_spi_media *spi = (struct tegra_spi_media*)media->context; + DEBUG_SPI("tegra_spi_cbfs_unmap\n"); + return cbfs_simple_buffer_unmap(&spi->buffer, address); +} + +int initialize_tegra_spi_cbfs_media(struct cbfs_media *media, + void *buffer_address, + size_t buffer_size) +{ + // TODO Replace static variable to support multiple streams. + static struct tegra_spi_media context; + static struct tegra_spi_channel *channel; + + channel = &tegra_spi_channels[CONFIG_BOOT_MEDIA_SPI_BUS - 1]; + channel->slave.cs = CONFIG_BOOT_MEDIA_SPI_CHIP_SELECT; + + DEBUG_SPI("Initializing CBFS media on SPI\n"); + + context.slave = &channel->slave; + context.buffer.allocated = context.buffer.last_allocate = 0; + context.buffer.buffer = buffer_address; + context.buffer.size = buffer_size; + media->context = (void*)&context; + media->open = tegra_spi_cbfs_open; + media->close = tegra_spi_cbfs_close; + media->read = tegra_spi_cbfs_read; + media->map = tegra_spi_cbfs_map; + media->unmap = tegra_spi_cbfs_unmap; + + return 0; +} + +struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs) +{ + struct tegra_spi_channel *channel = to_tegra_spi(bus); + if (!channel) + return NULL; + + return &channel->slave; +} + +int spi_claim_bus(struct spi_slave *slave) +{ + tegra_spi_init(slave->bus); + spi_cs_activate(slave); + return 0; +} + +void spi_release_bus(struct spi_slave *slave) +{ + spi_cs_deactivate(slave); +} diff --git a/src/soc/nvidia/tegra124/spi.h b/src/soc/nvidia/tegra124/spi.h new file mode 100644 index 0000000..02495ab --- /dev/null +++ b/src/soc/nvidia/tegra124/spi.h @@ -0,0 +1,29 @@ +/* + * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef __NVIDIA_TEGRA124_SPI_H__ +#define __NVIDIA_TEGRA124_SPI_H__ + +#include <stddef.h> + +struct cbfs_media; +int initialize_tegra_spi_cbfs_media(struct cbfs_media *media, + void *buffer_address, + size_t buffer_size); + +void tegra_spi_init(unsigned int bus); + +#endif /* __NVIDIA_TEGRA124_SPI_H__ */

1 0

Patch set updated for coreboot: 04f152f mainboard/google/parrot: fix ACPI interrupt storm on lid switch change
by Andrew Litt 10 Sep '14

10 Sep '14

Andrew Litt (ajlitt(a)splunge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6858 -gerrit commit 04f152f863b476cb93e39c7fa8e71ec211f62009 Author: Andrew Litt <ajlitt(a)splunge.net> Date: Tue Sep 9 10:49:19 2014 -0500 mainboard/google/parrot: fix ACPI interrupt storm on lid switch change This fixes the ACPI interrupt storm on Parrot that happens when closing the lid or entering suspend by lid close (seen in /sys/firmware/acpi/interrupts/gpe1F). This patch inverts the interrupt trigger level every time the interrupt is received so that it doesn't fire until the next state change. http://askubuntu.com/questions/310196 is a good example of what this is trying to solve. Change-Id: I8b095914e9330c3217a4ceb058613fa952f4a234 Signed-off-by: Andrew Litt <ajlitt(a)splunge.net> --- src/mainboard/google/parrot/acpi/mainboard.asl | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/src/mainboard/google/parrot/acpi/mainboard.asl b/src/mainboard/google/parrot/acpi/mainboard.asl index 4ab9733..503e44b 100644 --- a/src/mainboard/google/parrot/acpi/mainboard.asl +++ b/src/mainboard/google/parrot/acpi/mainboard.asl @@ -22,6 +22,13 @@ Scope (\_GPE) { Method(_L1F, 0x0, NotSerialized) { + /* + * Invert the interrupt level bit for the lid GPIO + * so we don't get another _SB.LID0 until the state + * changes again. GIV1 is the interrupt level control + * register for GPIO bits 15:8 + */ + Xor(GIV1, 0x80, GIV1) Notify(\_SB.LID0,0x80) } }

1 0

New patch to review for coreboot: c1a6bf3 tegra124/nyan: rougly stable code base
by Isaac Christensen 10 Sep '14

10 Sep '14

Isaac Christensen (isaac.christensen(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6869 -gerrit commit c1a6bf3856345e1d531ae345919087f1234702a9 Author: Gabe Black <gabeblack(a)google.com> Date: Wed Oct 9 23:45:07 2013 -0700 tegra124/nyan: rougly stable code base nyan: Clock setup. Reviewed-on: https://chromium-review.googlesource.com/172106 (cherry picked from commit 3697b6454c0aceebcf735436de90ba2441c9b7b1) tegra124: Call into the mainboard bootblock init if one exists. Reviewed-on: https://chromium-review.googlesource.com/172581 (cherry picked from commit 3a0cd48a0d1a9ce6b32ed614cd81fb81f5f82aec) nyan: Add a mainboard specific bootblock. Reviewed-on: https://chromium-review.googlesource.com/172582 (cherry picked from commit a83d065d660a26fe71ed79879c25f84a1b669f69) nyan: tegra124: Redestribute the clock code between the mainboard and soc. Reviewed-on: https://chromium-review.googlesource.com/172583 (cherry picked from commit ea703137fc37befa7d5a65afc982e298a0daca1b) nyan: Initialize the i2c pins and controllers. Reviewed-on: https://chromium-review.googlesource.com/172584 (cherry picked from commit 9c10a3074ef834688fea46c03551c2e3e54e44a8) nyan: Initialize the PMIC. Reviewed-on: https://chromium-review.googlesource.com/172585 (cherry picked from commit f6be8b0e607e05b73b5e4a84afcf04c879eee88a) tegra124: add a chip.h and use it in NYAN Reviewed-on: https://chromium-review.googlesource.com/172773 (cherry picked from commit 4dd5f1f091f2dcae5ce38203bb86c62994609f8f) tegra: Reorder GPIO register accesses to avoid glitching Reviewed-on: https://chromium-review.googlesource.com/172730 (cherry picked from commit 61bedbf0f839e19b284d21af2ad10f2ff15e17d5) tegra: Turn GPIO wrappers into macros to make them easier to write Reviewed-on: https://chromium-review.googlesource.com/172731 (cherry picked from commit 94550fdfa5a8005d2e6a313041de212ab7ac470c) tegra: Change GPIO functions to allow variable arguments Reviewed-on: https://chromium-review.googlesource.com/172916 (cherry picked from commit e95ccd984f718a04b6067ff6ad5049a2cd74466d) tegra124: Implement starting up the main CPUs. Reviewed-on: https://chromium-review.googlesource.com/172917 (cherry picked from commit 7c5169a197310e18a3df0f176c499669e3c2bda3) tegra: Simplify the I2C constants. Reviewed-on: https://chromium-review.googlesource.com/172953 (cherry picked from commit 130a07c86dfa5ba5ac4580f29db927c91f045c76) tegra124: Fix SPI base addresses Reviewed-on: https://chromium-review.googlesource.com/173322 (cherry picked from commit da808e46919ebd3b9f2377a5889f0d5f10b92357) tegra124: Scrub the clock constants. Reviewed-on: https://chromium-review.googlesource.com/172954 (cherry picked from commit 9305ff0696a6d556a97f928b8683770833a309a4) tegra124: add DMA support Reviewed-on: https://chromium-review.googlesource.com/172951 (cherry picked from commit 4d2a5a56b922ac37d2326d7b139697567aac37b8) tegra124: add basic SPI driver Reviewed-on: https://chromium-review.googlesource.com/172952 (cherry picked from commit 5f861f13c7fd2dd881f3cbd0f1b4d4a9994ce429) tegra124: Add an assembly stub which is run first on the main CPUs. Reviewed-on: https://chromium-review.googlesource.com/173541 (cherry picked from commit e142b9572a89f43fe984c4fc87e3203f380ff4de) nyan: tegra124: Set up dynamic cbmem. Reviewed-on: https://chromium-review.googlesource.com/173542 (cherry picked from commit b6e1a70103446abb5c3440f145617e6566879c6f) tegra124: Add an soc.c which sets up the chip operations and memory resource. Reviewed-on: https://chromium-review.googlesource.com/173543 (cherry picked from commit af49a5bd1f589cf053c4808510138aae26e20db4) tegra124: extend chip.h to include video settings Reviewed-on: https://chromium-review.googlesource.com/173600 (cherry picked from commit 87687633a2116f58fad7333b3b639cee9089ad29) tegra124 and nyan: fill in the devicetree a bit more, add defines Reviewed-on: https://chromium-review.googlesource.com/173684 (cherry picked from commit c107eaca3dea42be89f61690d0d6cb2181acb147) tegra124: clean-ups for SPI driver Reviewed-on: https://chromium-review.googlesource.com/173599 (cherry picked from commit 1e2f9fd442ea336bf0663c3c8ea51f771e21beb7) tegra124: add a #define for DMA alignment size Reviewed-on: https://chromium-review.googlesource.com/173638 (cherry picked from commit f9dc2a8d8016fa7db974fb6cb01c3275e26832af) tegra124: Add FIFO transmit functions to SPI driver Reviewed-on: https://chromium-review.googlesource.com/173639 (cherry picked from commit 97e61f36ad96ce2f9b12a7ef765ee73d3f4285f7) tegra124: clean-ups for DMA driver Reviewed-on: https://chromium-review.googlesource.com/173598 (cherry picked from commit 750c0a5d6942748dd21f3a3f884ad94a561e86e0) tegra124: early display and display code. Reviewed-on: https://chromium-review.googlesource.com/173622 (cherry picked from commit 651c7ab96b1f136865e4673a120de7afc1218558) tegra124: Move transfer size handling to spi_xfer() Reviewed-on: https://chromium-review.googlesource.com/173680 (cherry picked from commit 4a9b7b47b3c09d70063ea843054ffef98f554621) tegra124: strict error detection and reporting for SPI Reviewed-on: https://chromium-review.googlesource.com/173681 (cherry picked from commit c056fa954e1dab40a56faec6c50385763a2eb010) tegra124: add thread-friendly delays to SPI driver Reviewed-on: https://chromium-review.googlesource.com/173648 (cherry picked from commit c1a321c8f61942801627f895c5db74c518e2aa8e) Tegra124: Take the SPI1 controller out of reset and enable its clock. Reviewed-on: https://chromium-review.googlesource.com/173787 (cherry picked from commit c026a3fb861e157f1e17a121fc2ef70b903f36f2) tegra124: add two more clock setting values Reviewed-on: https://chromium-review.googlesource.com/173772 (cherry picked from commit 7d79d7dd9f0c1fd7127a7ba41652d809ccff7a57) nyan: Set up the ChromeOS related GPIOs and SPI bus 1 which goes to the EC. Reviewed-on: https://chromium-review.googlesource.com/173788 (cherry picked from commit ff172bfe30f75983a1e8efa2ead0a4519583d0a8) tegra124: Add some stub functions to the Tegra SPI driver. Reviewed-on: https://chromium-review.googlesource.com/173789 (cherry picked from commit 8bc527aa4afd301c046b0e844c7fa400630af0d2) tegra124: Build source files into the various stges needed by CONFIG_CHROMEOS. Reviewed-on: https://chromium-review.googlesource.com/173790 (cherry picked from commit 86a6423b668ca912295c47d8c6e3ef6c6f8c6084) nyan: Implement the code which reads GPIOs for ChromeOS. Reviewed-on: https://chromium-review.googlesource.com/173791 (cherry picked from commit 4c394dfbce762574fc79edcb6e4ac6bf346e48a3) nyan: Enable the CHROMEOS and ChromeOS EC related kconfig options. Reviewed-on: https://chromium-review.googlesource.com/173792 (cherry picked from commit 2845a4487159aa4b1dba58d977f52c449574fc8e) Tegra124: SDMMC: Take the SDMMC 3 and 4 out of reset and ungate their clocks. Reviewed-on: https://chromium-review.googlesource.com/173793 (cherry picked from commit c238b87bcd9d35afd828476d6ee88322ac5d0f88) tegra124: fix clear_fifo_status() in SPI driver Reviewed-on: https://chromium-review.googlesource.com/173738 (cherry picked from commit f415d2c0aaffc0f1a3592551a2db782d538f8f4f) ARM: Include stdint.h in cpu.h. Reviewed-on: https://chromium-review.googlesource.com/173774 (cherry picked from commit f1930faea3f14b2a2560a6c4058ef38532b6f1a6) tegra124: When setting up the main CPU, set its CPSR appropriately. Reviewed-on: https://chromium-review.googlesource.com/173775 (cherry picked from commit bc2ba9c15cfd22aeaca4f80b1d13a8b5e0178ead) tegra124: fix wrong names in clk_rst.h Reviewed-on: https://chromium-review.googlesource.com/173955 (cherry picked from commit 19dd9c85e4a3d1f77b23828bcbdd4bd8c2688b8d) tegra124: Fix up the PLLX divider table. Reviewed-on: https://chromium-review.googlesource.com/173778 (cherry picked from commit 3362cf3a7d6f5eaec879dda42323345922f6df17) tegra124: clock: Get rid of cpcon and dccon. Reviewed-on: https://chromium-review.googlesource.com/173779 (cherry picked from commit 08626ffac4a7e9ea3d4738af87e9e4cced7be2c7) Tegra124: SPI: Set and unset CS in spi_claim_bus and spi_release_bus. Reviewed-on: https://chromium-review.googlesource.com/173953 (cherry picked from commit a2df8f3a9c9c54c62d6ff37d3baff1d30ee6d355) armv7: expose dcache_line_bytes() in cache API Reviewed-on: https://chromium-review.googlesource.com/173975 (cherry picked from commit 6727f65702c7668fcb33848b4113bc3d3cc04e12) libpayload: expose dcache_line_bytes() in ARM cache API Reviewed-on: https://chromium-review.googlesource.com/174099 (cherry picked from commit 9387b02dff85b42944d95c3bccf59059c93fb4a9) armv4: add a stub for dcache_line_bytes() Reviewed-on: https://chromium-review.googlesource.com/173976 (cherry picked from commit 924f61ea895b9268c716791466637009bbac6469) tegra124: Base early UART on CLK_M to enable debugging of PLL init code Reviewed-on: https://chromium-review.googlesource.com/174339 (cherry picked from commit 8d9387432f0a0d9b257b040304238e543cced1aa) tegra124: Add additional PLLs and redesign the divisor table Reviewed-on: https://chromium-review.googlesource.com/174380 (cherry picked from commit f6a5f5c4562f1ca733505717c175be00413f2384) Squashed 49 commits for tegra124/nyan that included a lot of churn on different pieces. Change-Id: I00e8f5b74e835e01b28ca2e9c4af3709c9363d56 Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com> --- payloads/libpayload/arch/arm/cache.c | 15 +- payloads/libpayload/include/arm/arch/cache.h | 3 + src/arch/arm/armv4/cache.c | 11 + src/arch/arm/armv7/cache.c | 15 +- src/arch/arm/include/armv4/arch/cache.h | 3 + src/arch/arm/include/armv7/arch/cache.h | 3 + src/arch/arm/include/armv7/arch/cpu.h | 2 + src/mainboard/google/nyan/Kconfig | 23 + src/mainboard/google/nyan/Makefile.inc | 3 + src/mainboard/google/nyan/bootblock.c | 80 +++ src/mainboard/google/nyan/chromeos.c | 103 +++ src/mainboard/google/nyan/devicetree.cb | 48 ++ src/mainboard/google/nyan/mainboard.c | 36 +- src/mainboard/google/nyan/pmic.c | 78 +++ src/mainboard/google/nyan/pmic.h | 25 + src/mainboard/google/nyan/romstage.c | 23 + src/soc/nvidia/tegra/dc.h | 564 ++++++++++++++++ src/soc/nvidia/tegra/gpio.c | 210 +++--- src/soc/nvidia/tegra/gpio.h | 62 +- src/soc/nvidia/tegra/i2c.c | 44 +- src/soc/nvidia/tegra/i2c.h | 179 ++--- src/soc/nvidia/tegra124/Kconfig | 1 + src/soc/nvidia/tegra124/Makefile.inc | 24 + src/soc/nvidia/tegra124/bootblock.c | 46 +- src/soc/nvidia/tegra124/cbfs.c | 6 +- src/soc/nvidia/tegra124/cbmem.c | 27 + src/soc/nvidia/tegra124/chip.h | 91 +++ src/soc/nvidia/tegra124/clk_rst.h | 626 +++++++++-------- src/soc/nvidia/tegra124/clock.c | 361 +++++++++- src/soc/nvidia/tegra124/clock.h | 22 - src/soc/nvidia/tegra124/cpug.S | 56 ++ src/soc/nvidia/tegra124/cpug.h | 29 + src/soc/nvidia/tegra124/display.c | 304 +++++++++ src/soc/nvidia/tegra124/dma.c | 236 +++++++ src/soc/nvidia/tegra124/dma.h | 61 ++ src/soc/nvidia/tegra124/early_display.c | 61 ++ src/soc/nvidia/tegra124/flow.h | 49 ++ src/soc/nvidia/tegra124/gpio.h | 7 +- src/soc/nvidia/tegra124/include/soc/addressmap.h | 22 +- src/soc/nvidia/tegra124/include/soc/clock.h | 171 +++++ src/soc/nvidia/tegra124/include/soc/display.h | 22 + src/soc/nvidia/tegra124/pmc.h | 200 ++++++ src/soc/nvidia/tegra124/power.c | 87 +++ src/soc/nvidia/tegra124/power.h | 29 + src/soc/nvidia/tegra124/soc.c | 66 ++ src/soc/nvidia/tegra124/spi.c | 815 +++++++++++++++++++++++ src/soc/nvidia/tegra124/spi.h | 29 + 47 files changed, 4358 insertions(+), 620 deletions(-) diff --git a/payloads/libpayload/arch/arm/cache.c b/payloads/libpayload/arch/arm/cache.c index 3944818..4c222ea 100644 --- a/payloads/libpayload/arch/arm/cache.c +++ b/payloads/libpayload/arch/arm/cache.c @@ -195,17 +195,20 @@ void dcache_invalidate_all(void) dcache_foreach(OP_DCISW); } -static unsigned int line_bytes(void) +unsigned int dcache_line_bytes(void) { uint32_t ccsidr; - unsigned int size; + static unsigned int line_bytes = 0; + + if (line_bytes) + return line_bytes; ccsidr = read_ccsidr(); /* [2:0] - Indicates (Log2(number of words in cache line)) - 2 */ - size = 1 << ((ccsidr & 0x7) + 2); /* words per line */ - size *= sizeof(unsigned int); /* bytes per line */ + line_bytes = 1 << ((ccsidr & 0x7) + 2); /* words per line */ + line_bytes *= sizeof(unsigned int); /* bytes per line */ - return size; + return line_bytes; } /* @@ -219,7 +222,7 @@ static void dcache_op_mva(void const *vaddr, size_t len, enum dcache_op op) unsigned long line, linesize; unsigned long paddr = virt_to_phys(vaddr); - linesize = line_bytes(); + linesize = dcache_line_bytes(); line = paddr & ~(linesize - 1); dsb(); diff --git a/payloads/libpayload/include/arm/arch/cache.h b/payloads/libpayload/include/arm/arch/cache.h index ffdb55a..5210dfe 100644 --- a/payloads/libpayload/include/arm/arch/cache.h +++ b/payloads/libpayload/include/arm/arch/cache.h @@ -304,6 +304,9 @@ void dcache_clean_all(void); /* dcache invalidate all (on current level given by CCSELR) */ void dcache_invalidate_all(void); +/* returns number of bytes per cache line */ +unsigned int dcache_line_bytes(void); + /* dcache and MMU disable */ void dcache_mmu_disable(void); diff --git a/src/arch/arm/armv4/cache.c b/src/arch/arm/armv4/cache.c index 729b82c..e5cf293 100644 --- a/src/arch/arm/armv4/cache.c +++ b/src/arch/arm/armv4/cache.c @@ -55,6 +55,17 @@ void dcache_invalidate_all(void) { } +unsigned int dcache_line_bytes(void) +{ + /* + * TODO: Implement this correctly. For now we just return a + * reasonable value. It was added during Nyan development and + * may be used in bootblock code. It matters only if dcache is + * turned on. + */ + return 64; +} + void dcache_clean_by_mva(void const *addr, size_t len) { } diff --git a/src/arch/arm/armv7/cache.c b/src/arch/arm/armv7/cache.c index acd1f9a..4ee2687 100644 --- a/src/arch/arm/armv7/cache.c +++ b/src/arch/arm/armv7/cache.c @@ -194,17 +194,20 @@ void dcache_invalidate_all(void) dcache_foreach(OP_DCISW); } -static unsigned int line_bytes(void) +unsigned int dcache_line_bytes(void) { uint32_t ccsidr; - unsigned int size; + static unsigned int line_bytes = 0; + + if (line_bytes) + return line_bytes; ccsidr = read_ccsidr(); /* [2:0] - Indicates (Log2(number of words in cache line)) - 2 */ - size = 1 << ((ccsidr & 0x7) + 2); /* words per line */ - size *= sizeof(unsigned int); /* bytes per line */ + line_bytes = 1 << ((ccsidr & 0x7) + 2); /* words per line */ + line_bytes *= sizeof(unsigned int); /* bytes per line */ - return size; + return line_bytes; } /* @@ -217,7 +220,7 @@ static void dcache_op_mva(void const *addr, size_t len, enum dcache_op op) { unsigned long line, linesize; - linesize = line_bytes(); + linesize = dcache_line_bytes(); line = (uint32_t)addr & ~(linesize - 1); dsb(); diff --git a/src/arch/arm/include/armv4/arch/cache.h b/src/arch/arm/include/armv4/arch/cache.h index db4379a..6a3f593 100644 --- a/src/arch/arm/include/armv4/arch/cache.h +++ b/src/arch/arm/include/armv4/arch/cache.h @@ -57,6 +57,9 @@ void dcache_clean_all(void); /* dcache invalidate all (on current level given by CCSELR) */ void dcache_invalidate_all(void); +/* returns number of bytes per cache line */ +unsigned int dcache_line_bytes(void); + /* dcache and MMU disable */ void dcache_mmu_disable(void); diff --git a/src/arch/arm/include/armv7/arch/cache.h b/src/arch/arm/include/armv7/arch/cache.h index ffdb55a..5210dfe 100644 --- a/src/arch/arm/include/armv7/arch/cache.h +++ b/src/arch/arm/include/armv7/arch/cache.h @@ -304,6 +304,9 @@ void dcache_clean_all(void); /* dcache invalidate all (on current level given by CCSELR) */ void dcache_invalidate_all(void); +/* returns number of bytes per cache line */ +unsigned int dcache_line_bytes(void); + /* dcache and MMU disable */ void dcache_mmu_disable(void); diff --git a/src/arch/arm/include/armv7/arch/cpu.h b/src/arch/arm/include/armv7/arch/cpu.h index 52cc8a3..275bb8c 100644 --- a/src/arch/arm/include/armv7/arch/cpu.h +++ b/src/arch/arm/include/armv7/arch/cpu.h @@ -20,6 +20,8 @@ #ifndef __ARCH_CPU_H__ #define __ARCH_CPU_H__ +#include <stdint.h> + #define asmlinkage #if !defined(__PRE_RAM__) diff --git a/src/mainboard/google/nyan/Kconfig b/src/mainboard/google/nyan/Kconfig index 5ac58d3..85a8b89 100644 --- a/src/mainboard/google/nyan/Kconfig +++ b/src/mainboard/google/nyan/Kconfig @@ -22,6 +22,9 @@ if BOARD_GOOGLE_NYAN config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select SOC_NVIDIA_TEGRA124 + select EC_GOOGLE_CHROMEEC + select EC_GOOGLE_CHROMEEC_SPI + select MAINBOARD_HAS_BOOTBLOCK_INIT select BOARD_ROMSIZE_KB_1024 config MAINBOARD_DIR @@ -54,4 +57,24 @@ config BCT_CFG_EMMC endchoice +config BOOT_MEDIA_SPI_BUS + int "SPI bus with boot media ROM" + range 1 6 + depends on BCT_CFG_SPI + default 4 + help + Which SPI bus the boot media is connected to. + +config BOOT_MEDIA_SPI_CHIP_SELECT + int "Chip select for SPI boot media" + range 0 3 + depends on BCT_CFG_SPI + default 0 + help + Which chip select to use for boot media. + +config EC_GOOGLE_CHROMEEC_SPI_BUS + hex + default 1 + endif # BOARD_GOOGLE_NYAN diff --git a/src/mainboard/google/nyan/Makefile.inc b/src/mainboard/google/nyan/Makefile.inc index 3cf7dd2..f154a3b 100644 --- a/src/mainboard/google/nyan/Makefile.inc +++ b/src/mainboard/google/nyan/Makefile.inc @@ -27,6 +27,9 @@ $(obj)/generated/bct.cfg: subdirs-y += bct +bootblock-y += bootblock.c +bootblock-y += pmic.c + romstage-y += romstage.c ramstage-y += mainboard.c diff --git a/src/mainboard/google/nyan/bootblock.c b/src/mainboard/google/nyan/bootblock.c new file mode 100644 index 0000000..49133ca --- /dev/null +++ b/src/mainboard/google/nyan/bootblock.c @@ -0,0 +1,80 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <bootblock_common.h> +#include <console/console.h> +#include <device/i2c.h> +#include <soc/clock.h> +#include <soc/nvidia/tegra/i2c.h> +#include <soc/nvidia/tegra124/pinmux.h> +#include <soc/nvidia/tegra124/spi.h> /* FIXME: move back to soc code? */ + +#include "pmic.h" + +void bootblock_mainboard_init(void) +{ + clock_config(); + + // I2C1 clock. + pinmux_set_config(PINMUX_GEN1_I2C_SCL_INDEX, + PINMUX_GEN1_I2C_SCL_FUNC_I2C1 | PINMUX_INPUT_ENABLE); + // I2C1 data. + pinmux_set_config(PINMUX_GEN1_I2C_SDA_INDEX, + PINMUX_GEN1_I2C_SDA_FUNC_I2C1 | PINMUX_INPUT_ENABLE); + // I2C2 clock. + pinmux_set_config(PINMUX_GEN2_I2C_SCL_INDEX, + PINMUX_GEN2_I2C_SCL_FUNC_I2C2 | PINMUX_INPUT_ENABLE); + // I2C2 data. + pinmux_set_config(PINMUX_GEN2_I2C_SDA_INDEX, + PINMUX_GEN2_I2C_SDA_FUNC_I2C2 | PINMUX_INPUT_ENABLE); + // I2C3 (cam) clock. + pinmux_set_config(PINMUX_CAM_I2C_SCL_INDEX, + PINMUX_CAM_I2C_SCL_FUNC_I2C3 | PINMUX_INPUT_ENABLE); + // I2C3 (cam) data. + pinmux_set_config(PINMUX_CAM_I2C_SDA_INDEX, + PINMUX_CAM_I2C_SDA_FUNC_I2C3 | PINMUX_INPUT_ENABLE); + // I2C5 (PMU) clock. + pinmux_set_config(PINMUX_PWR_I2C_SCL_INDEX, + PINMUX_PWR_I2C_SCL_FUNC_I2CPMU | PINMUX_INPUT_ENABLE); + // I2C5 (PMU) data. + pinmux_set_config(PINMUX_PWR_I2C_SDA_INDEX, + PINMUX_PWR_I2C_SDA_FUNC_I2CPMU | PINMUX_INPUT_ENABLE); + + i2c_init(0); + i2c_init(1); + i2c_init(2); + i2c_init(4); + + pmic_init(4); + + /* SPI4 data out (MOSI) */ + pinmux_set_config(PINMUX_SDMMC1_CMD_INDEX, + PINMUX_SDMMC1_CMD_FUNC_SPI4 | PINMUX_INPUT_ENABLE); + /* SPI4 data in (MISO) */ + pinmux_set_config(PINMUX_SDMMC1_DAT1_INDEX, + PINMUX_SDMMC1_DAT1_FUNC_SPI4 | PINMUX_INPUT_ENABLE); + /* SPI4 clock */ + pinmux_set_config(PINMUX_SDMMC1_DAT2_INDEX, + PINMUX_SDMMC1_DAT2_FUNC_SPI4 | PINMUX_INPUT_ENABLE); + /* SPI4 chip select 0 */ + pinmux_set_config(PINMUX_SDMMC1_DAT3_INDEX, + PINMUX_SDMMC1_DAT3_FUNC_SPI4 | PINMUX_INPUT_ENABLE); +// spi_init(); + tegra_spi_init(4); +} diff --git a/src/mainboard/google/nyan/chromeos.c b/src/mainboard/google/nyan/chromeos.c new file mode 100644 index 0000000..75c99ba --- /dev/null +++ b/src/mainboard/google/nyan/chromeos.c @@ -0,0 +1,103 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <boot/coreboot_tables.h> +#include <console/console.h> +#include <ec/google/chromeec/ec.h> +#include <ec/google/chromeec/ec_commands.h> +#include <string.h> +#include <vendorcode/google/chromeos/chromeos.h> +#include <soc/nvidia/tegra124/gpio.h> + +enum { + ACTIVE_LOW = 0, + ACTIVE_HIGH = 1 +}; + +void fill_lb_gpios(struct lb_gpios *gpios) +{ + int count = 0; + + /* Write Protect: active low */ + gpios->gpios[count].port = GPIO_R1_INDEX; + gpios->gpios[count].polarity = ACTIVE_LOW; + gpios->gpios[count].value = gpio_get_in_value(GPIO_R1_INDEX); + strncpy((char *)gpios->gpios[count].name, "write protect", + GPIO_MAX_NAME_LENGTH); + count++; + + /* Recovery: active high */ + gpios->gpios[count].port = -1; + gpios->gpios[count].polarity = ACTIVE_HIGH; + gpios->gpios[count].value = get_recovery_mode_switch(); + strncpy((char *)gpios->gpios[count].name, "recovery", + GPIO_MAX_NAME_LENGTH); + count++; + + /* Lid: active high */ + gpios->gpios[count].port = GPIO_R4_INDEX; + gpios->gpios[count].polarity = ACTIVE_HIGH; + gpios->gpios[count].value = gpio_get_in_value(GPIO_R4_INDEX); + strncpy((char *)gpios->gpios[count].name, "lid", GPIO_MAX_NAME_LENGTH); + count++; + + /* Power: active low */ + gpios->gpios[count].port = GPIO_Q0_INDEX; + gpios->gpios[count].polarity = ACTIVE_LOW; + gpios->gpios[count].value = gpio_get_in_value(GPIO_Q0_INDEX); + strncpy((char *)gpios->gpios[count].name, "power", + GPIO_MAX_NAME_LENGTH); + count++; + + /* Developer: virtual GPIO active high */ + gpios->gpios[count].port = -1; + gpios->gpios[count].polarity = ACTIVE_HIGH; + gpios->gpios[count].value = get_developer_mode_switch(); + strncpy((char *)gpios->gpios[count].name, "developer", + GPIO_MAX_NAME_LENGTH); + count++; + + gpios->size = sizeof(*gpios) + (count * sizeof(struct lb_gpio)); + gpios->count = count; + + printk(BIOS_ERR, "Added %d GPIOS size %d\n", count, gpios->size); +} + +int get_developer_mode_switch(void) +{ + return gpio_get_in_value(GPIO_Q6_INDEX); +} + +int get_recovery_mode_switch(void) +{ + uint32_t ec_events; + + /* The GPIO is active low. */ + if (!gpio_get_in_value(GPIO_Q7_INDEX)) // RECMODE_GPIO + return 1; + + ec_events = google_chromeec_get_events_b(); + return !!(ec_events & + EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY)); +} + +int get_write_protect_state(void) +{ + return !gpio_get_in_value(GPIO_R1_INDEX); +} diff --git a/src/mainboard/google/nyan/devicetree.cb b/src/mainboard/google/nyan/devicetree.cb index 392a5ae..623c5a1 100644 --- a/src/mainboard/google/nyan/devicetree.cb +++ b/src/mainboard/google/nyan/devicetree.cb @@ -19,4 +19,52 @@ chip soc/nvidia/tegra124 device cpu_cluster 0 on end +# N.B. We ae not using the device tree in an effective way. +# We need to change this in future such that the on-soc +# devices are 'chips', which will allow us to go at them +# in parallel. This is even easier on the ARM SOCs since there +# are no single-access resources such as the infamous +# cf8/cfc registers found on PCs. + register "display_controller" = "TEGRA_ARM_DISPLAYA" + register "xres" = "2560" + register "yres" = "1700" + register "framebuffer_bits_per_pixel" = "24" + register "cache_policy" = "DCACHE_WRITETHROUGH" + + # With some help from the mainbaord designer + register "backlight_en_gpio" = "GPIO(H2)" + register "lvds_shutdown_gpio" = "0" + register "backlight_vdd_gpio" = "GPIO(P2)" + register "panel_vdd_gpio" = "0" + register "pwm" = "GPIO(H1)" + +# taken from u-boot; these look wrong however. + register "vdd_delay" = "400" + register "vdd_data_delay" = "4" + register "data_backlight_delay" = "203" + register "backlight_pwm_delay" = "17" + register "pwm_backlight_en_delay" = "15" + +# How to compute these: xrandr --verbose will give you this: +#Detailed mode: Clock 285.250 MHz, 272 mm x 181 mm +# 2560 2608 2640 2720 hborder 0 +# 1700 1703 1713 1749 vborder 0 +#Then you can compute your values: +#H front porch = 2608 - 2560 = 48 +#H sync = 2640 - 2608 = 32 +#H back porch = 2720 - 2640 = 80 +#V front porch = 1703 - 1700 = 3 +#V sync = 1713 - 1703 = 10 +#V back porch = 1749 - 1713 = 36 +#href_to_sync and vref_to_sync are from the vendor + + register "href_to_sync" = "11" + register "hfront_porch" = "48" + register "hsync_width" = "32" + register "hback_porch" = "80" + + register "vref_to_sync" = "1" + register "vfront_porch" = "3" + register "vsync_width" = "10" + register "vback_porch" = "36" end diff --git a/src/mainboard/google/nyan/mainboard.c b/src/mainboard/google/nyan/mainboard.c index 9e08021..c7258ff 100644 --- a/src/mainboard/google/nyan/mainboard.c +++ b/src/mainboard/google/nyan/mainboard.c @@ -19,10 +19,44 @@ #include <device/device.h> #include <boot/coreboot_tables.h> +#include <soc/nvidia/tegra124/gpio.h> + +static void setup_pinmux(void) +{ + // Write protect. + gpio_input_pullup(GPIO(R1)); + // Recovery mode. + gpio_input_pullup(GPIO(Q7)); + // Lid switch. + gpio_input_pullup(GPIO(R4)); + // Power switch. + gpio_input_pullup(GPIO(Q0)); + // Developer mode. + gpio_input_pullup(GPIO(Q6)); + // EC in RW. + gpio_input_pullup(GPIO(U4)); + + // SPI1 MOSI + pinmux_set_config(PINMUX_ULPI_CLK_INDEX, PINMUX_ULPI_CLK_FUNC_SPI1 | + PINMUX_PULL_UP | + PINMUX_INPUT_ENABLE); + // SPI1 MISO + pinmux_set_config(PINMUX_ULPI_DIR_INDEX, PINMUX_ULPI_DIR_FUNC_SPI1 | + PINMUX_PULL_UP | + PINMUX_INPUT_ENABLE); + // SPI1 SCLK + pinmux_set_config(PINMUX_ULPI_NXT_INDEX, PINMUX_ULPI_NXT_FUNC_SPI1 | + PINMUX_PULL_NONE | + PINMUX_INPUT_ENABLE); + // SPI1 CS0 + pinmux_set_config(PINMUX_ULPI_STP_INDEX, PINMUX_ULPI_STP_FUNC_SPI1 | + PINMUX_PULL_NONE | + PINMUX_INPUT_ENABLE); +} -/* this happens after cpu_init where exynos resources are set */ static void mainboard_init(device_t dev) { + setup_pinmux(); } static void mainboard_enable(device_t dev) diff --git a/src/mainboard/google/nyan/pmic.c b/src/mainboard/google/nyan/pmic.c new file mode 100644 index 0000000..ab951ea --- /dev/null +++ b/src/mainboard/google/nyan/pmic.c @@ -0,0 +1,78 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2013 Google Inc. + * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <delay.h> +#include <device/i2c.h> +#include <stdint.h> +#include <stdlib.h> + +#include "pmic.h" + +struct pmic_write +{ + uint8_t reg; // Register to write. + uint8_t val; // Value to write. +}; + +enum { + AS3722_I2C_ADDR = 0x40 +}; + +static struct pmic_write pmic_writes[] = +{ + /* Don't need to set up VDD_CORE - already done - by OTP */ + + /* First set VDD_CPU to 1.0V, then enable the VDD_CPU regulator. */ + { 0x00, 0x28 }, + + /* Don't write SDCONTROL - it's already 0x7F, i.e. all SDs enabled. */ + + /* First set VDD_GPU to 1.0V, then enable the VDD_GPU regulator. */ + { 0x06, 0x28 }, + + /* Don't write SDCONTROL - it's already 0x7F, i.e. all SDs enabled. */ + + /* First set VPP_FUSE to 1.2V, then enable the VPP_FUSE regulator. */ + { 0x12, 0x10 }, + + /* Don't write LDCONTROL - it's already 0xFF, i.e. all LDOs enabled. */ + + /* + * Bring up VDD_SDMMC via the AS3722 PMIC on the PWR I2C bus. + * First set it to bypass 3.3V straight thru, then enable the regulator + * + * NOTE: We do this early because doing it later seems to hose the CPU + * power rail/partition startup. Need to debug. + */ + { 0x16, 0x3f } + + /* Don't write LDCONTROL - it's already 0xFF, i.e. all LDOs enabled. */ +}; + +void pmic_init(unsigned bus) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(pmic_writes); i++) { + i2c_write(bus, AS3722_I2C_ADDR, pmic_writes[i].reg, 1, + &pmic_writes[i].val, 1); + udelay(10 * 1000); + } +} diff --git a/src/mainboard/google/nyan/pmic.h b/src/mainboard/google/nyan/pmic.h new file mode 100644 index 0000000..78c9f0d --- /dev/null +++ b/src/mainboard/google/nyan/pmic.h @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef __MAINBOARD_GOOGLE_NYAN_PMIC_H__ +#define __MAINBOARD_GOOGLE_NYAN_PMIC_H__ + +void pmic_init(unsigned bus); + +#endif /* __MAINBOARD_GOOGLE_NYAN_PMIC_H__ */ diff --git a/src/mainboard/google/nyan/romstage.c b/src/mainboard/google/nyan/romstage.c index c52fbd2..5a66dde 100644 --- a/src/mainboard/google/nyan/romstage.c +++ b/src/mainboard/google/nyan/romstage.c @@ -18,12 +18,35 @@ */ #include <arch/stages.h> +#include <device/device.h> #include <cbfs.h> +#include <cbmem.h> #include <console/console.h> +#include "soc/nvidia/tegra124/chip.h" +#include <soc/display.h> void main(void) { void *entry; + const struct device *soc; + const struct soc_nvidia_tegra124_config *config; + + /* for quality of the user interface, it's important to get + * the video going ASAP. Because there are long delays in some + * of the powerup steps, we do some very early setup here in + * romstage. We don't do this in the bootblock because video + * setup is finicky and subject to change; hence, we do it as + * early as we can in the RW stage, but never in the RO stage. + */ + + soc = dev_find_slot(DEVICE_PATH_CPU_CLUSTER, 0); + printk(BIOS_SPEW, "s%s: soc is %p\n", __func__, soc); + if (soc && soc->chip_info){ + config = soc->chip_info; + setup_display((struct soc_nvidia_tegra124_config *)config); + } + + cbmem_initialize_empty(); entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, "fallback/coreboot_ram"); stage_exit(entry); diff --git a/src/soc/nvidia/tegra/dc.h b/src/soc/nvidia/tegra/dc.h new file mode 100644 index 0000000..33dbe53 --- /dev/null +++ b/src/soc/nvidia/tegra/dc.h @@ -0,0 +1,564 @@ +/* + * Copyright 2013 Google Inc. + * (C) Copyright 2010 + * NVIDIA Corporation <www.nvidia.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __SOC_NVIDIA_TEGRA_DC_H +#define __SOC_NVIDIA_TEGRA_DC_H + +/* Register definitions for the Tegra display controller */ + +/* CMD register 0x000 ~ 0x43 */ +struct dc_cmd_reg { + /* Address 0x000 ~ 0x002 */ + u32 gen_incr_syncpt; /* _CMD_GENERAL_INCR_SYNCPT_0 */ + u32 gen_incr_syncpt_ctrl; /* _CMD_GENERAL_INCR_SYNCPT_CNTRL_0 */ + u32 gen_incr_syncpt_err; /* _CMD_GENERAL_INCR_SYNCPT_ERROR_0 */ + + u32 reserved0[5]; /* reserved_0[5] */ + + /* Address 0x008 ~ 0x00a */ + u32 win_a_incr_syncpt; /* _CMD_WIN_A_INCR_SYNCPT_0 */ + u32 win_a_incr_syncpt_ctrl; /* _CMD_WIN_A_INCR_SYNCPT_CNTRL_0 */ + u32 win_a_incr_syncpt_err; /* _CMD_WIN_A_INCR_SYNCPT_ERROR_0 */ + + u32 reserved1[5]; /* reserved_1[5] */ + + /* Address 0x010 ~ 0x012 */ + u32 win_b_incr_syncpt; /* _CMD_WIN_B_INCR_SYNCPT_0 */ + u32 win_b_incr_syncpt_ctrl; /* _CMD_WIN_B_INCR_SYNCPT_CNTRL_0 */ + u32 win_b_incr_syncpt_err; /* _CMD_WIN_B_INCR_SYNCPT_ERROR_0 */ + + u32 reserved2[5]; /* reserved_2[5] */ + + /* Address 0x018 ~ 0x01a */ + u32 win_c_incr_syncpt; /* _CMD_WIN_C_INCR_SYNCPT_0 */ + u32 win_c_incr_syncpt_ctrl; /* _CMD_WIN_C_INCR_SYNCPT_CNTRL_0 */ + u32 win_c_incr_syncpt_err; /* _CMD_WIN_C_INCR_SYNCPT_ERROR_0 */ + + u32 reserved3[13]; /* reserved_3[13] */ + + /* Address 0x028 */ + u32 cont_syncpt_vsync; /* _CMD_CONT_SYNCPT_VSYNC_0 */ + + u32 reserved4[7]; /* reserved_4[7] */ + + /* Address 0x030 ~ 0x033 */ + u32 ctxsw; /* _CMD_CTXSW_0 */ + u32 disp_cmd_opt0; /* _CMD_DISPLAY_COMMAND_OPTION0_0 */ + u32 disp_cmd; /* _CMD_DISPLAY_COMMAND_0 */ + u32 sig_raise; /* _CMD_SIGNAL_RAISE_0 */ + + u32 reserved5[2]; /* reserved_0[2] */ + + /* Address 0x036 ~ 0x03e */ + u32 disp_pow_ctrl; /* _CMD_DISPLAY_POWER_CONTROL_0 */ + u32 int_stat; /* _CMD_INT_STATUS_0 */ + u32 int_mask; /* _CMD_INT_MASK_0 */ + u32 int_enb; /* _CMD_INT_ENABLE_0 */ + u32 int_type; /* _CMD_INT_TYPE_0 */ + u32 int_polarity; /* _CMD_INT_POLARITY_0 */ + u32 sig_raise1; /* _CMD_SIGNAL_RAISE1_0 */ + u32 sig_raise2; /* _CMD_SIGNAL_RAISE2_0 */ + u32 sig_raise3; /* _CMD_SIGNAL_RAISE3_0 */ + + u32 reserved6; /* reserved_6 */ + + /* Address 0x040 ~ 0x043 */ + u32 state_access; /* _CMD_STATE_ACCESS_0 */ + u32 state_ctrl; /* _CMD_STATE_CONTROL_0 */ + u32 disp_win_header; /* _CMD_DISPLAY_WINDOW_HEADER_0 */ + u32 reg_act_ctrl; /* _CMD_REG_ACT_CONTROL_0 */ +}; + +enum { + PIN_REG_COUNT = 4, + PIN_OUTPUT_SEL_COUNT = 7, +}; + +/* COM register 0x300 ~ 0x329 */ +struct dc_com_reg { + /* Address 0x300 ~ 0x301 */ + u32 crc_ctrl; /* _COM_CRC_CONTROL_0 */ + u32 crc_checksum; /* _COM_CRC_CHECKSUM_0 */ + + /* _COM_PIN_OUTPUT_ENABLE0/1/2/3_0: Address 0x302 ~ 0x305 */ + u32 pin_output_enb[PIN_REG_COUNT]; + + /* _COM_PIN_OUTPUT_POLARITY0/1/2/3_0: Address 0x306 ~ 0x309 */ + u32 pin_output_polarity[PIN_REG_COUNT]; + + /* _COM_PIN_OUTPUT_DATA0/1/2/3_0: Address 0x30a ~ 0x30d */ + u32 pin_output_data[PIN_REG_COUNT]; + + /* _COM_PIN_INPUT_ENABLE0_0: Address 0x30e ~ 0x311 */ + u32 pin_input_enb[PIN_REG_COUNT]; + + /* Address 0x312 ~ 0x313 */ + u32 pin_input_data0; /* _COM_PIN_INPUT_DATA0_0 */ + u32 pin_input_data1; /* _COM_PIN_INPUT_DATA1_0 */ + + /* _COM_PIN_OUTPUT_SELECT0/1/2/3/4/5/6_0: Address 0x314 ~ 0x31a */ + u32 pin_output_sel[PIN_OUTPUT_SEL_COUNT]; + + /* Address 0x31b ~ 0x329 */ + u32 pin_misc_ctrl; /* _COM_PIN_MISC_CONTROL_0 */ + u32 pm0_ctrl; /* _COM_PM0_CONTROL_0 */ + u32 pm0_duty_cycle; /* _COM_PM0_DUTY_CYCLE_0 */ + u32 pm1_ctrl; /* _COM_PM1_CONTROL_0 */ + u32 pm1_duty_cycle; /* _COM_PM1_DUTY_CYCLE_0 */ + u32 spi_ctrl; /* _COM_SPI_CONTROL_0 */ + u32 spi_start_byte; /* _COM_SPI_START_BYTE_0 */ + u32 hspi_wr_data_ab; /* _COM_HSPI_WRITE_DATA_AB_0 */ + u32 hspi_wr_data_cd; /* _COM_HSPI_WRITE_DATA_CD */ + u32 hspi_cs_dc; /* _COM_HSPI_CS_DC_0 */ + u32 scratch_reg_a; /* _COM_SCRATCH_REGISTER_A_0 */ + u32 scratch_reg_b; /* _COM_SCRATCH_REGISTER_B_0 */ + u32 gpio_ctrl; /* _COM_GPIO_CTRL_0 */ + u32 gpio_debounce_cnt; /* _COM_GPIO_DEBOUNCE_COUNTER_0 */ + u32 crc_checksum_latched; /* _COM_CRC_CHECKSUM_LATCHED_0 */ +}; + +enum dc_disp_h_pulse_pos { + H_PULSE0_POSITION_A, + H_PULSE0_POSITION_B, + H_PULSE0_POSITION_C, + H_PULSE0_POSITION_D, + H_PULSE0_POSITION_COUNT, +}; + +struct _disp_h_pulse { + /* _DISP_H_PULSE0/1/2_CONTROL_0 */ + u32 h_pulse_ctrl; + /* _DISP_H_PULSE0/1/2_POSITION_A/B/C/D_0 */ + u32 h_pulse_pos[H_PULSE0_POSITION_COUNT]; +}; + +enum dc_disp_v_pulse_pos { + V_PULSE0_POSITION_A, + V_PULSE0_POSITION_B, + V_PULSE0_POSITION_C, + V_PULSE0_POSITION_COUNT, +}; + +struct _disp_v_pulse0 { + /* _DISP_H_PULSE0/1_CONTROL_0 */ + u32 v_pulse_ctrl; + /* _DISP_H_PULSE0/1_POSITION_A/B/C_0 */ + u32 v_pulse_pos[V_PULSE0_POSITION_COUNT]; +}; + +struct _disp_v_pulse2 { + /* _DISP_H_PULSE2/3_CONTROL_0 */ + u32 v_pulse_ctrl; + /* _DISP_H_PULSE2/3_POSITION_A_0 */ + u32 v_pulse_pos_a; +}; + +enum dc_disp_h_pulse_reg { + H_PULSE0, + H_PULSE1, + H_PULSE2, + H_PULSE_COUNT, +}; + +enum dc_disp_pp_select { + PP_SELECT_A, + PP_SELECT_B, + PP_SELECT_C, + PP_SELECT_D, + PP_SELECT_COUNT, +}; + +/* DISP register 0x400 ~ 0x4c1 */ +struct dc_disp_reg { + /* Address 0x400 ~ 0x40a */ + u32 disp_signal_opt0; /* _DISP_DISP_SIGNAL_OPTIONS0_0 */ + u32 disp_signal_opt1; /* _DISP_DISP_SIGNAL_OPTIONS1_0 */ + u32 disp_win_opt; /* _DISP_DISP_WIN_OPTIONS_0 */ + u32 mem_high_pri; /* _DISP_MEM_HIGH_PRIORITY_0 */ + u32 mem_high_pri_timer; /* _DISP_MEM_HIGH_PRIORITY_TIMER_0 */ + u32 disp_timing_opt; /* _DISP_DISP_TIMING_OPTIONS_0 */ + u32 ref_to_sync; /* _DISP_REF_TO_SYNC_0 */ + u32 sync_width; /* _DISP_SYNC_WIDTH_0 */ + u32 back_porch; /* _DISP_BACK_PORCH_0 */ + u32 disp_active; /* _DISP_DISP_ACTIVE_0 */ + u32 front_porch; /* _DISP_FRONT_PORCH_0 */ + + /* Address 0x40b ~ 0x419: _DISP_H_PULSE0/1/2_ */ + struct _disp_h_pulse h_pulse[H_PULSE_COUNT]; + + /* Address 0x41a ~ 0x421 */ + struct _disp_v_pulse0 v_pulse0; /* _DISP_V_PULSE0_ */ + struct _disp_v_pulse0 v_pulse1; /* _DISP_V_PULSE1_ */ + + /* Address 0x422 ~ 0x425 */ + struct _disp_v_pulse2 v_pulse3; /* _DISP_V_PULSE2_ */ + struct _disp_v_pulse2 v_pulse4; /* _DISP_V_PULSE3_ */ + + /* Address 0x426 ~ 0x429 */ + u32 m0_ctrl; /* _DISP_M0_CONTROL_0 */ + u32 m1_ctrl; /* _DISP_M1_CONTROL_0 */ + u32 di_ctrl; /* _DISP_DI_CONTROL_0 */ + u32 pp_ctrl; /* _DISP_PP_CONTROL_0 */ + + /* Address 0x42a ~ 0x42d: _DISP_PP_SELECT_A/B/C/D_0 */ + u32 pp_select[PP_SELECT_COUNT]; + + /* Address 0x42e ~ 0x435 */ + u32 disp_clk_ctrl; /* _DISP_DISP_CLOCK_CONTROL_0 */ + u32 disp_interface_ctrl; /* _DISP_DISP_INTERFACE_CONTROL_0 */ + u32 disp_color_ctrl; /* _DISP_DISP_COLOR_CONTROL_0 */ + u32 shift_clk_opt; /* _DISP_SHIFT_CLOCK_OPTIONS_0 */ + u32 data_enable_opt; /* _DISP_DATA_ENABLE_OPTIONS_0 */ + u32 serial_interface_opt; /* _DISP_SERIAL_INTERFACE_OPTIONS_0 */ + u32 lcd_spi_opt; /* _DISP_LCD_SPI_OPTIONS_0 */ + u32 border_color; /* _DISP_BORDER_COLOR_0 */ + + /* Address 0x436 ~ 0x439 */ + u32 color_key0_lower; /* _DISP_COLOR_KEY0_LOWER_0 */ + u32 color_key0_upper; /* _DISP_COLOR_KEY0_UPPER_0 */ + u32 color_key1_lower; /* _DISP_COLOR_KEY1_LOWER_0 */ + u32 color_key1_upper; /* _DISP_COLOR_KEY1_UPPER_0 */ + + u32 reserved0[2]; /* reserved_0[2] */ + + /* Address 0x43c ~ 0x442 */ + u32 cursor_foreground; /* _DISP_CURSOR_FOREGROUND_0 */ + u32 cursor_background; /* _DISP_CURSOR_BACKGROUND_0 */ + u32 cursor_start_addr; /* _DISP_CURSOR_START_ADDR_0 */ + u32 cursor_start_addr_ns; /* _DISP_CURSOR_START_ADDR_NS_0 */ + u32 cursor_pos; /* _DISP_CURSOR_POSITION_0 */ + u32 cursor_pos_ns; /* _DISP_CURSOR_POSITION_NS_0 */ + u32 seq_ctrl; /* _DISP_INIT_SEQ_CONTROL_0 */ + + /* Address 0x442 ~ 0x446 */ + u32 spi_init_seq_data_a; /* _DISP_SPI_INIT_SEQ_DATA_A_0 */ + u32 spi_init_seq_data_b; /* _DISP_SPI_INIT_SEQ_DATA_B_0 */ + u32 spi_init_seq_data_c; /* _DISP_SPI_INIT_SEQ_DATA_C_0 */ + u32 spi_init_seq_data_d; /* _DISP_SPI_INIT_SEQ_DATA_D_0 */ + + u32 reserved1[0x39]; /* reserved1[0x39], */ + + /* Address 0x480 ~ 0x484 */ + u32 dc_mccif_fifoctrl; /* _DISP_DC_MCCIF_FIFOCTRL_0 */ + u32 mccif_disp0a_hyst; /* _DISP_MCCIF_DISPLAY0A_HYST_0 */ + u32 mccif_disp0b_hyst; /* _DISP_MCCIF_DISPLAY0B_HYST_0 */ + u32 mccif_disp0c_hyst; /* _DISP_MCCIF_DISPLAY0C_HYST_0 */ + u32 mccif_disp1b_hyst; /* _DISP_MCCIF_DISPLAY1B_HYST_0 */ + + u32 reserved2[0x3b]; /* reserved2[0x3b] */ + + /* Address 0x4c0 ~ 0x4c1 */ + u32 dac_crt_ctrl; /* _DISP_DAC_CRT_CTRL_0 */ + u32 disp_misc_ctrl; /* _DISP_DISP_MISC_CONTROL_0 */ +}; + +enum dc_winc_filter_p { + WINC_FILTER_COUNT = 0x10, +}; + +/* Window A/B/C register 0x500 ~ 0x628 */ +struct dc_winc_reg { + + /* Address 0x500 */ + u32 color_palette; /* _WINC_COLOR_PALETTE_0 */ + + u32 reserved0[0xff]; /* reserved_0[0xff] */ + + /* Address 0x600 */ + u32 palette_color_ext; /* _WINC_PALETTE_COLOR_EXT_0 */ + + /* _WINC_H_FILTER_P00~0F_0 */ + /* Address 0x601 ~ 0x610 */ + u32 h_filter_p[WINC_FILTER_COUNT]; + + /* Address 0x611 ~ 0x618 */ + u32 csc_yof; /* _WINC_CSC_YOF_0 */ + u32 csc_kyrgb; /* _WINC_CSC_KYRGB_0 */ + u32 csc_kur; /* _WINC_CSC_KUR_0 */ + u32 csc_kvr; /* _WINC_CSC_KVR_0 */ + u32 csc_kug; /* _WINC_CSC_KUG_0 */ + u32 csc_kvg; /* _WINC_CSC_KVG_0 */ + u32 csc_kub; /* _WINC_CSC_KUB_0 */ + u32 csc_kvb; /* _WINC_CSC_KVB_0 */ + + /* Address 0x619 ~ 0x628: _WINC_V_FILTER_P00~0F_0 */ + u32 v_filter_p[WINC_FILTER_COUNT]; +}; + +/* WIN A/B/C Register 0x700 ~ 0x714*/ +struct dc_win_reg { + /* Address 0x700 ~ 0x714 */ + u32 win_opt; /* _WIN_WIN_OPTIONS_0 */ + u32 byte_swap; /* _WIN_BYTE_SWAP_0 */ + u32 buffer_ctrl; /* _WIN_BUFFER_CONTROL_0 */ + u32 color_depth; /* _WIN_COLOR_DEPTH_0 */ + u32 pos; /* _WIN_POSITION_0 */ + u32 size; /* _WIN_SIZE_0 */ + u32 prescaled_size; /* _WIN_PRESCALED_SIZE_0 */ + u32 h_initial_dda; /* _WIN_H_INITIAL_DDA_0 */ + u32 v_initial_dda; /* _WIN_V_INITIAL_DDA_0 */ + u32 dda_increment; /* _WIN_DDA_INCREMENT_0 */ + u32 line_stride; /* _WIN_LINE_STRIDE_0 */ + u32 buf_stride; /* _WIN_BUF_STRIDE_0 */ + u32 uv_buf_stride; /* _WIN_UV_BUF_STRIDE_0 */ + u32 buffer_addr_mode; /* _WIN_BUFFER_ADDR_MODE_0 */ + u32 dv_ctrl; /* _WIN_DV_CONTROL_0 */ + u32 blend_nokey; /* _WIN_BLEND_NOKEY_0 */ + u32 blend_1win; /* _WIN_BLEND_1WIN_0 */ + u32 blend_2win_x; /* _WIN_BLEND_2WIN_X_0 */ + u32 blend_2win_y; /* _WIN_BLEND_2WIN_Y_0 */ + u32 blend_3win_xy; /* _WIN_BLEND_3WIN_XY_0 */ + u32 hp_fetch_ctrl; /* _WIN_HP_FETCH_CONTROL_0 */ +}; + +/* WINBUF A/B/C Register 0x800 ~ 0x80a */ +struct dc_winbuf_reg { + /* Address 0x800 ~ 0x80a */ + u32 start_addr; /* _WINBUF_START_ADDR_0 */ + u32 start_addr_ns; /* _WINBUF_START_ADDR_NS_0 */ + u32 start_addr_u; /* _WINBUF_START_ADDR_U_0 */ + u32 start_addr_u_ns; /* _WINBUF_START_ADDR_U_NS_0 */ + u32 start_addr_v; /* _WINBUF_START_ADDR_V_0 */ + u32 start_addr_v_ns; /* _WINBUF_START_ADDR_V_NS_0 */ + u32 addr_h_offset; /* _WINBUF_ADDR_H_OFFSET_0 */ + u32 addr_h_offset_ns; /* _WINBUF_ADDR_H_OFFSET_NS_0 */ + u32 addr_v_offset; /* _WINBUF_ADDR_V_OFFSET_0 */ + u32 addr_v_offset_ns; /* _WINBUF_ADDR_V_OFFSET_NS_0 */ + u32 uflow_status; /* _WINBUF_UFLOW_STATUS_0 */ +}; + +/* Display Controller (DC_) regs */ +struct display_controller { + struct dc_cmd_reg cmd; /* CMD register 0x000 ~ 0x43 */ + u32 reserved0[0x2bc]; + + struct dc_com_reg com; /* COM register 0x300 ~ 0x329 */ + u32 reserved1[0xd6]; + + struct dc_disp_reg disp; /* DISP register 0x400 ~ 0x4c1 */ + u32 reserved2[0x3e]; + + struct dc_winc_reg winc; /* Window A/B/C 0x500 ~ 0x628 */ + u32 reserved3[0xd7]; + + struct dc_win_reg win; /* WIN A/B/C 0x700 ~ 0x714*/ + u32 reserved4[0xeb]; + + struct dc_winbuf_reg winbuf; /* WINBUF A/B/C 0x800 ~ 0x80a */ +}; + +#define BIT(pos) (1U << pos) + +/* DC_CMD_DISPLAY_COMMAND 0x032 */ +#define CTRL_MODE_SHIFT 5 +#define CTRL_MODE_MASK (0x3 << CTRL_MODE_SHIFT) +enum { + CTRL_MODE_STOP, + CTRL_MODE_C_DISPLAY, + CTRL_MODE_NC_DISPLAY, +}; + +/* _WIN_COLOR_DEPTH_0 */ +enum win_color_depth_id { + COLOR_DEPTH_P1, + COLOR_DEPTH_P2, + COLOR_DEPTH_P4, + COLOR_DEPTH_P8, + COLOR_DEPTH_B4G4R4A4, + COLOR_DEPTH_B5G5R5A, + COLOR_DEPTH_B5G6R5, + COLOR_DEPTH_AB5G5R5, + COLOR_DEPTH_B8G8R8A8 = 12, + COLOR_DEPTH_R8G8B8A8, + COLOR_DEPTH_B6x2G6x2R6x2A8, + COLOR_DEPTH_R6x2G6x2B6x2A8, + COLOR_DEPTH_YCbCr422, + COLOR_DEPTH_YUV422, + COLOR_DEPTH_YCbCr420P, + COLOR_DEPTH_YUV420P, + COLOR_DEPTH_YCbCr422P, + COLOR_DEPTH_YUV422P, + COLOR_DEPTH_YCbCr422R, + COLOR_DEPTH_YUV422R, + COLOR_DEPTH_YCbCr422RA, + COLOR_DEPTH_YUV422RA, +}; + +/* DC_CMD_DISPLAY_POWER_CONTROL 0x036 */ +#define PW0_ENABLE BIT(0) +#define PW1_ENABLE BIT(2) +#define PW2_ENABLE BIT(4) +#define PW3_ENABLE BIT(6) +#define PW4_ENABLE BIT(8) +#define PM0_ENABLE BIT(16) +#define PM1_ENABLE BIT(18) +#define SPI_ENABLE BIT(24) +#define HSPI_ENABLE BIT(25) + +/* DC_CMD_STATE_CONTROL 0x041 */ +#define GENERAL_ACT_REQ BIT(0) +#define WIN_A_ACT_REQ BIT(1) +#define WIN_B_ACT_REQ BIT(2) +#define WIN_C_ACT_REQ BIT(3) +#define GENERAL_UPDATE BIT(8) +#define WIN_A_UPDATE BIT(9) +#define WIN_B_UPDATE BIT(10) +#define WIN_C_UPDATE BIT(11) + +/* DC_CMD_DISPLAY_WINDOW_HEADER 0x042 */ +#define WINDOW_A_SELECT BIT(4) +#define WINDOW_B_SELECT BIT(5) +#define WINDOW_C_SELECT BIT(6) + +/* DC_DISP_DISP_CLOCK_CONTROL 0x42e */ +#define SHIFT_CLK_DIVIDER_SHIFT 0 +#define SHIFT_CLK_DIVIDER_MASK (0xff << SHIFT_CLK_DIVIDER_SHIFT) +#define PIXEL_CLK_DIVIDER_SHIFT 8 +#define PIXEL_CLK_DIVIDER_MSK (0xf << PIXEL_CLK_DIVIDER_SHIFT) +enum { + PIXEL_CLK_DIVIDER_PCD1, + PIXEL_CLK_DIVIDER_PCD1H, + PIXEL_CLK_DIVIDER_PCD2, + PIXEL_CLK_DIVIDER_PCD3, + PIXEL_CLK_DIVIDER_PCD4, + PIXEL_CLK_DIVIDER_PCD6, + PIXEL_CLK_DIVIDER_PCD8, + PIXEL_CLK_DIVIDER_PCD9, + PIXEL_CLK_DIVIDER_PCD12, + PIXEL_CLK_DIVIDER_PCD16, + PIXEL_CLK_DIVIDER_PCD18, + PIXEL_CLK_DIVIDER_PCD24, + PIXEL_CLK_DIVIDER_PCD13, +}; + +/* DC_DISP_DISP_INTERFACE_CONTROL 0x42f */ +#define DATA_FORMAT_SHIFT 0 +#define DATA_FORMAT_MASK (0xf << DATA_FORMAT_SHIFT) +enum { + DATA_FORMAT_DF1P1C, + DATA_FORMAT_DF1P2C24B, + DATA_FORMAT_DF1P2C18B, + DATA_FORMAT_DF1P2C16B, + DATA_FORMAT_DF2S, + DATA_FORMAT_DF3S, + DATA_FORMAT_DFSPI, + DATA_FORMAT_DF1P3C24B, + DATA_FORMAT_DF1P3C18B, +}; +#define DATA_ALIGNMENT_SHIFT 8 +enum { + DATA_ALIGNMENT_MSB, + DATA_ALIGNMENT_LSB, +}; +#define DATA_ORDER_SHIFT 9 +enum { + DATA_ORDER_RED_BLUE, + DATA_ORDER_BLUE_RED, +}; + +/* DC_DISP_DATA_ENABLE_OPTIONS 0x432 */ +#define DE_SELECT_SHIFT 0 +#define DE_SELECT_MASK (0x3 << DE_SELECT_SHIFT) +#define DE_SELECT_ACTIVE_BLANK 0x0 +#define DE_SELECT_ACTIVE 0x1 +#define DE_SELECT_ACTIVE_IS 0x2 +#define DE_CONTROL_SHIFT 2 +#define DE_CONTROL_MASK (0x7 << DE_CONTROL_SHIFT) +enum { + DE_CONTROL_ONECLK, + DE_CONTROL_NORMAL, + DE_CONTROL_EARLY_EXT, + DE_CONTROL_EARLY, + DE_CONTROL_ACTIVE_BLANK, +}; + +/* DC_WIN_WIN_OPTIONS 0x700 */ +#define H_DIRECTION BIT(0) +enum { + H_DIRECTION_INCREMENT, + H_DIRECTION_DECREMENT, +}; +#define V_DIRECTION BIT(2) +enum { + V_DIRECTION_INCREMENT, + V_DIRECTION_DECREMENT, +}; +#define COLOR_EXPAND BIT(6) +#define CP_ENABLE BIT(16) +#define DV_ENABLE BIT(20) +#define WIN_ENABLE BIT(30) + +/* DC_WIN_BYTE_SWAP 0x701 */ +#define BYTE_SWAP_SHIFT 0 +#define BYTE_SWAP_MASK (3 << BYTE_SWAP_SHIFT) +enum { + BYTE_SWAP_NOSWAP, + BYTE_SWAP_SWAP2, + BYTE_SWAP_SWAP4, + BYTE_SWAP_SWAP4HW +}; + +/* DC_WIN_POSITION 0x704 */ +#define H_POSITION_SHIFT 0 +#define H_POSITION_MASK (0x1FFF << H_POSITION_SHIFT) +#define V_POSITION_SHIFT 16 +#define V_POSITION_MASK (0x1FFF << V_POSITION_SHIFT) + +/* DC_WIN_SIZE 0x705 */ +#define H_SIZE_SHIFT 0 +#define H_SIZE_MASK (0x1FFF << H_SIZE_SHIFT) +#define V_SIZE_SHIFT 16 +#define V_SIZE_MASK (0x1FFF << V_SIZE_SHIFT) + +/* DC_WIN_PRESCALED_SIZE 0x706 */ +#define H_PRESCALED_SIZE_SHIFT 0 +#define H_PRESCALED_SIZE_MASK (0x7FFF << H_PRESCALED_SIZE) +#define V_PRESCALED_SIZE_SHIFT 16 +#define V_PRESCALED_SIZE_MASK (0x1FFF << V_PRESCALED_SIZE) + +/* DC_WIN_DDA_INCREMENT 0x709 */ +#define H_DDA_INC_SHIFT 0 +#define H_DDA_INC_MASK (0xFFFF << H_DDA_INC_SHIFT) +#define V_DDA_INC_SHIFT 16 +#define V_DDA_INC_MASK (0xFFFF << V_DDA_INC_SHIFT) + +/* This holds information about a window which can be displayed */ +/* TODO: do we really need this for basic setup? Not sure yet. */ +struct disp_ctl_win { + enum win_color_depth_id fmt; /* Color depth/format */ + u32 bpp; /* Bits per pixel */ + u32 phys_addr; /* Physical address in memory */ + u32 x; /* Horizontal address offset (bytes) */ + u32 y; /* Veritical address offset (bytes) */ + u32 w; /* Width of source window */ + u32 h; /* Height of source window */ + u32 stride; /* Number of bytes per line */ + u32 out_x; /* Left edge of output window (col) */ + u32 out_y; /* Top edge of output window (row) */ + u32 out_w; /* Width of output window in pixels */ + u32 out_h; /* Height of output window in pixels */ +}; + +void display_startup(device_t dev); +#endif /* __SOC_NVIDIA_TEGRA_DC_H */ diff --git a/src/soc/nvidia/tegra/gpio.c b/src/soc/nvidia/tegra/gpio.c index d4b5bdd..0615320 100644 --- a/src/soc/nvidia/tegra/gpio.c +++ b/src/soc/nvidia/tegra/gpio.c @@ -26,41 +26,25 @@ #include "gpio.h" #include "pinmux.h" -static void gpio_input_common(int gpio_index, int pinmux_index, - uint32_t pconfig) +void __gpio_input(gpio_t gpio, u32 pull) { - pconfig |= PINMUX_INPUT_ENABLE; - gpio_set_int_enable(gpio_index, 0); - gpio_set_mode(gpio_index, GPIO_MODE_GPIO); - gpio_set_out_enable(gpio_index, 0); - pinmux_set_config(pinmux_index, pconfig); -} - -void gpio_input(int gpio_index, int pinmux_index) -{ - gpio_input_common(gpio_index, pinmux_index, PINMUX_PULL_NONE); -} + u32 pinmux_config = PINMUX_INPUT_ENABLE | PINMUX_TRISTATE | pull; -void gpio_input_pullup(int gpio_index, int pinmux_index) -{ - gpio_input_common(gpio_index, pinmux_index, PINMUX_PULL_UP); -} - -void gpio_input_pulldown(int gpio_index, int pinmux_index) -{ - gpio_input_common(gpio_index, pinmux_index, PINMUX_PULL_DOWN); + gpio_set_int_enable(gpio, 0); + gpio_set_out_enable(gpio, 0); + gpio_set_mode(gpio, GPIO_MODE_GPIO); + pinmux_set_config(gpio >> GPIO_PINMUX_SHIFT, pinmux_config); } -void gpio_output(int gpio_index, int pinmux_index, int value) +void gpio_output(gpio_t gpio, int value) { - uint32_t pconfig = PINMUX_PULL_NONE; + /* TODO: Set OPEN_DRAIN based on what pin it is? */ - pinmux_set_config(pinmux_index, pconfig | PINMUX_TRISTATE); - gpio_set_int_enable(gpio_index, 0); - gpio_set_mode(gpio_index, GPIO_MODE_GPIO); - gpio_set_out_enable(gpio_index, 1); - gpio_set_out_value(gpio_index, value); - pinmux_set_config(pinmux_index, pconfig); + gpio_set_int_enable(gpio, 0); + gpio_set_out_value(gpio, value); + gpio_set_out_enable(gpio, 1); + gpio_set_mode(gpio, GPIO_MODE_GPIO); + pinmux_set_config(gpio >> GPIO_PINMUX_SHIFT, PINMUX_PULL_NONE); } enum { @@ -74,167 +58,173 @@ enum { struct gpio_bank { // Values - uint32_t config[GPIO_PORTS_PER_BANK]; - uint32_t out_enable[GPIO_PORTS_PER_BANK]; - uint32_t out_value[GPIO_PORTS_PER_BANK]; - uint32_t in_value[GPIO_PORTS_PER_BANK]; - uint32_t int_status[GPIO_PORTS_PER_BANK]; - uint32_t int_enable[GPIO_PORTS_PER_BANK]; - uint32_t int_level[GPIO_PORTS_PER_BANK]; - uint32_t int_clear[GPIO_PORTS_PER_BANK]; + u32 config[GPIO_PORTS_PER_BANK]; + u32 out_enable[GPIO_PORTS_PER_BANK]; + u32 out_value[GPIO_PORTS_PER_BANK]; + u32 in_value[GPIO_PORTS_PER_BANK]; + u32 int_status[GPIO_PORTS_PER_BANK]; + u32 int_enable[GPIO_PORTS_PER_BANK]; + u32 int_level[GPIO_PORTS_PER_BANK]; + u32 int_clear[GPIO_PORTS_PER_BANK]; // Masks - uint32_t config_mask[GPIO_PORTS_PER_BANK]; - uint32_t out_enable_mask[GPIO_PORTS_PER_BANK]; - uint32_t out_value_mask[GPIO_PORTS_PER_BANK]; - uint32_t in_value_mask[GPIO_PORTS_PER_BANK]; - uint32_t int_status_mask[GPIO_PORTS_PER_BANK]; - uint32_t int_enable_mask[GPIO_PORTS_PER_BANK]; - uint32_t int_level_mask[GPIO_PORTS_PER_BANK]; - uint32_t int_clear_mask[GPIO_PORTS_PER_BANK]; + u32 config_mask[GPIO_PORTS_PER_BANK]; + u32 out_enable_mask[GPIO_PORTS_PER_BANK]; + u32 out_value_mask[GPIO_PORTS_PER_BANK]; + u32 in_value_mask[GPIO_PORTS_PER_BANK]; + u32 int_status_mask[GPIO_PORTS_PER_BANK]; + u32 int_enable_mask[GPIO_PORTS_PER_BANK]; + u32 int_level_mask[GPIO_PORTS_PER_BANK]; + u32 int_clear_mask[GPIO_PORTS_PER_BANK]; }; static const struct gpio_bank *gpio_banks = (void *)TEGRA_GPIO_BASE; -static uint32_t gpio_read_port(int index, size_t offset) +static u32 gpio_read_port(int index, size_t offset) { int bank = index / GPIO_GPIOS_PER_BANK; int port = (index - bank * GPIO_GPIOS_PER_BANK) / GPIO_GPIOS_PER_PORT; - return read32((uint8_t *)&gpio_banks[bank] + offset + - port * sizeof(uint32_t)); + return read32((u8 *)&gpio_banks[bank] + offset + + port * sizeof(u32)); } -static void gpio_write_port(int index, size_t offset, - uint32_t mask, uint32_t value) +static void gpio_write_port(int index, size_t offset, u32 mask, u32 value) { int bank = index / GPIO_GPIOS_PER_BANK; int port = (index - bank * GPIO_GPIOS_PER_BANK) / GPIO_GPIOS_PER_PORT; - uint32_t reg = read32((uint8_t *)&gpio_banks[bank] + offset + - port * sizeof(uint32_t)); - uint32_t new_reg = (reg & ~mask) | (value & mask); + u32 reg = read32((u8 *)&gpio_banks[bank] + offset + + port * sizeof(u32)); + u32 new_reg = (reg & ~mask) | (value & mask); if (new_reg != reg) { - write32(new_reg, (uint8_t *)&gpio_banks[bank] + offset + - port * sizeof(uint32_t)); + write32(new_reg, (u8 *)&gpio_banks[bank] + offset + + port * sizeof(u32)); } } -void gpio_set_mode(int gpio_index, enum gpio_mode mode) +void gpio_set_mode(gpio_t gpio, enum gpio_mode mode) { - int bit = gpio_index % GPIO_GPIOS_PER_PORT; - gpio_write_port(gpio_index, offsetof(struct gpio_bank, config), + int bit = gpio % GPIO_GPIOS_PER_PORT; + gpio_write_port(gpio & ((1 << GPIO_PINMUX_SHIFT) - 1), + offsetof(struct gpio_bank, config), 1 << bit, mode ? (1 << bit) : 0); } -int gpio_get_mode(int gpio_index) +int gpio_get_mode(gpio_t gpio) { - int bit = gpio_index % GPIO_GPIOS_PER_PORT; - uint32_t port = gpio_read_port(gpio_index, - offsetof(struct gpio_bank, config)); + int bit = gpio % GPIO_GPIOS_PER_PORT; + u32 port = gpio_read_port(gpio & ((1 << GPIO_PINMUX_SHIFT) - 1), + offsetof(struct gpio_bank, config)); return (port & (1 << bit)) != 0; } -void gpio_set_lock(int gpio_index) +void gpio_set_lock(gpio_t gpio) { - int bit = gpio_index % GPIO_GPIOS_PER_PORT + GPIO_GPIOS_PER_PORT; - gpio_write_port(gpio_index, offsetof(struct gpio_bank, config), + int bit = gpio % GPIO_GPIOS_PER_PORT + GPIO_GPIOS_PER_PORT; + gpio_write_port(gpio & ((1 << GPIO_PINMUX_SHIFT) - 1), + offsetof(struct gpio_bank, config), 1 << bit, 1 << bit); } -int gpio_get_lock(int gpio_index) +int gpio_get_lock(gpio_t gpio) { - int bit = gpio_index % GPIO_GPIOS_PER_PORT + GPIO_GPIOS_PER_PORT; - uint32_t port = gpio_read_port(gpio_index, - offsetof(struct gpio_bank, config)); + int bit = gpio % GPIO_GPIOS_PER_PORT + GPIO_GPIOS_PER_PORT; + u32 port = gpio_read_port(gpio & ((1 << GPIO_PINMUX_SHIFT) - 1), + offsetof(struct gpio_bank, config)); return (port & (1 << bit)) != 0; } -void gpio_set_out_enable(int gpio_index, int enable) +void gpio_set_out_enable(gpio_t gpio, int enable) { - int bit = gpio_index % GPIO_GPIOS_PER_PORT; - gpio_write_port(gpio_index, offsetof(struct gpio_bank, out_enable), + int bit = gpio % GPIO_GPIOS_PER_PORT; + gpio_write_port(gpio & ((1 << GPIO_PINMUX_SHIFT) - 1), + offsetof(struct gpio_bank, out_enable), 1 << bit, enable ? (1 << bit) : 0); } -int gpio_get_out_enable(int gpio_index) +int gpio_get_out_enable(gpio_t gpio) { - int bit = gpio_index % GPIO_GPIOS_PER_PORT; - uint32_t port = gpio_read_port(gpio_index, - offsetof(struct gpio_bank, out_enable)); + int bit = gpio % GPIO_GPIOS_PER_PORT; + u32 port = gpio_read_port(gpio & ((1 << GPIO_PINMUX_SHIFT) - 1), + offsetof(struct gpio_bank, out_enable)); return (port & (1 << bit)) != 0; } -void gpio_set_out_value(int gpio_index, int value) +void gpio_set_out_value(gpio_t gpio, int value) { - int bit = gpio_index % GPIO_GPIOS_PER_PORT; - gpio_write_port(gpio_index, offsetof(struct gpio_bank, out_value), + int bit = gpio % GPIO_GPIOS_PER_PORT; + gpio_write_port(gpio & ((1 << GPIO_PINMUX_SHIFT) - 1), + offsetof(struct gpio_bank, out_value), 1 << bit, value ? (1 << bit) : 0); } -int gpio_get_out_value(int gpio_index) +int gpio_get_out_value(gpio_t gpio) { - int bit = gpio_index % GPIO_GPIOS_PER_PORT; - uint32_t port = gpio_read_port(gpio_index, - offsetof(struct gpio_bank, out_value)); + int bit = gpio % GPIO_GPIOS_PER_PORT; + u32 port = gpio_read_port(gpio & ((1 << GPIO_PINMUX_SHIFT) - 1), + offsetof(struct gpio_bank, out_value)); return (port & (1 << bit)) != 0; } -int gpio_get_in_value(int gpio_index) +int gpio_get_in_value(gpio_t gpio) { - int bit = gpio_index % GPIO_GPIOS_PER_PORT; - uint32_t port = gpio_read_port(gpio_index, - offsetof(struct gpio_bank, in_value)); + int bit = gpio % GPIO_GPIOS_PER_PORT; + u32 port = gpio_read_port(gpio & ((1 << GPIO_PINMUX_SHIFT) - 1), + offsetof(struct gpio_bank, in_value)); return (port & (1 << bit)) != 0; } -int gpio_get_int_status(int gpio_index) +int gpio_get_int_status(gpio_t gpio) { - int bit = gpio_index % GPIO_GPIOS_PER_PORT; - uint32_t port = gpio_read_port(gpio_index, - offsetof(struct gpio_bank, int_status)); + int bit = gpio % GPIO_GPIOS_PER_PORT; + u32 port = gpio_read_port(gpio & ((1 << GPIO_PINMUX_SHIFT) - 1), + offsetof(struct gpio_bank, int_status)); return (port & (1 << bit)) != 0; } -void gpio_set_int_enable(int gpio_index, int enable) +void gpio_set_int_enable(gpio_t gpio, int enable) { - int bit = gpio_index % GPIO_GPIOS_PER_PORT; - gpio_write_port(gpio_index, offsetof(struct gpio_bank, int_enable), + int bit = gpio % GPIO_GPIOS_PER_PORT; + gpio_write_port(gpio & ((1 << GPIO_PINMUX_SHIFT) - 1), + offsetof(struct gpio_bank, int_enable), 1 << bit, enable ? (1 << bit) : 0); } -int gpio_get_int_enable(int gpio_index) +int gpio_get_int_enable(gpio_t gpio) { - int bit = gpio_index % GPIO_GPIOS_PER_PORT; - uint32_t port = gpio_read_port(gpio_index, - offsetof(struct gpio_bank, int_enable)); + int bit = gpio % GPIO_GPIOS_PER_PORT; + u32 port = gpio_read_port(gpio & ((1 << GPIO_PINMUX_SHIFT) - 1), + offsetof(struct gpio_bank, int_enable)); return (port & (1 << bit)) != 0; } -void gpio_set_int_level(int gpio_index, int high_rise, int edge, int delta) +void gpio_set_int_level(gpio_t gpio, int high_rise, int edge, int delta) { - int bit = gpio_index % GPIO_GPIOS_PER_PORT; - uint32_t value = (high_rise ? (0x000001 << bit) : 0) | + int bit = gpio % GPIO_GPIOS_PER_PORT; + u32 value = (high_rise ? (0x000001 << bit) : 0) | (edge ? (0x000100 << bit) : 0) | - (delta ? (0x010000 << bit) : 0); - gpio_write_port(gpio_index, offsetof(struct gpio_bank, config), + (delta ? (0x010000 << bit) : 0); + gpio_write_port(gpio & ((1 << GPIO_PINMUX_SHIFT) - 1), + offsetof(struct gpio_bank, config), 0x010101 << bit, value); } -void gpio_get_int_level(int gpio_index, int *high_rise, int *edge, int *delta) +void gpio_get_int_level(gpio_t gpio, int *high_rise, int *edge, int *delta) { - int bit = gpio_index % GPIO_GPIOS_PER_PORT; - uint32_t port = gpio_read_port(gpio_index, - offsetof(struct gpio_bank, int_level)); + int bit = gpio % GPIO_GPIOS_PER_PORT; + u32 port = gpio_read_port(gpio & ((1 << GPIO_PINMUX_SHIFT) - 1), + offsetof(struct gpio_bank, int_level)); *high_rise = ((port & (0x000001 << bit)) != 0); *edge = ((port & (0x000100 << bit)) != 0); *delta = ((port & (0x010000 << bit)) != 0); } -void gpio_set_int_clear(int gpio_index) +void gpio_set_int_clear(gpio_t gpio) { - int bit = gpio_index % GPIO_GPIOS_PER_PORT; - gpio_write_port(gpio_index, offsetof(struct gpio_bank, int_clear), + int bit = gpio % GPIO_GPIOS_PER_PORT; + gpio_write_port(gpio & ((1 << GPIO_PINMUX_SHIFT) - 1), + offsetof(struct gpio_bank, int_clear), 1 << bit, 1 << bit); } diff --git a/src/soc/nvidia/tegra/gpio.h b/src/soc/nvidia/tegra/gpio.h index b62dc90..546ea05 100644 --- a/src/soc/nvidia/tegra/gpio.h +++ b/src/soc/nvidia/tegra/gpio.h @@ -22,12 +22,34 @@ #include <stdint.h> -/* Higher level functions for common GPIO configurations. */ +#include "pinmux.h" -void gpio_input(int gpio_index, int pinmux_index); -void gpio_input_pullup(int gpio_index, int pinmux_index); -void gpio_input_pulldown(int gpio_index, int pinmux_index); -void gpio_output(int gpio_index, int pinmux_index, int value); +/* Wrapper type for GPIOs. Always use GPIO() macro to generate. */ +typedef u32 gpio_t; + +#define GPIO_PINMUX_SHIFT 16 +#define GPIO(name) ((gpio_t)(GPIO_##name##_INDEX | \ + (PINMUX_GPIO_##name << GPIO_PINMUX_SHIFT))) + +/* Higher level function wrappers for common GPIO configurations. */ + +void gpio_output(gpio_t gpio, int value); +void __gpio_input(gpio_t gpio, u32 pull); + +static inline void gpio_input(gpio_t gpio) +{ + __gpio_input(gpio, PINMUX_PULL_NONE); +} + +static inline void gpio_input_pulldown(gpio_t gpio) +{ + __gpio_input(gpio, PINMUX_PULL_DOWN); +} + +static inline void gpio_input_pullup(gpio_t gpio) +{ + __gpio_input(gpio, PINMUX_PULL_UP); +} /* Functions to modify specific GPIO control values. */ @@ -35,29 +57,29 @@ enum gpio_mode { GPIO_MODE_SPIO = 0, GPIO_MODE_GPIO = 1 }; -void gpio_set_mode(int gpio_index, enum gpio_mode); -int gpio_get_mode(int gpio_index); +void gpio_set_mode(gpio_t gpio, enum gpio_mode); +int gpio_get_mode(gpio_t gpio); // Lock a GPIO with extreme caution since they can't be unlocked. -void gpio_set_lock(int gpio_index); -int gpio_get_lock(int gpio_index); +void gpio_set_lock(gpio_t gpio); +int gpio_get_lock(gpio_t gpio); -void gpio_set_out_enable(int gpio_index, int enable); -int gpio_get_out_enable(int gpio_index); +void gpio_set_out_enable(gpio_t gpio, int enable); +int gpio_get_out_enable(gpio_t gpio); -void gpio_set_out_value(int gpio_index, int value); -int gpio_get_out_value(int gpio_index); +void gpio_set_out_value(gpio_t gpio, int value); +int gpio_get_out_value(gpio_t gpio); -int gpio_get_in_value(int gpio_index); +int gpio_get_in_value(gpio_t gpio); -int gpio_get_int_status(int gpio_index); +int gpio_get_int_status(gpio_t gpio); -void gpio_set_int_enable(int gpio_index, int enable); -int gpio_get_int_enable(int gpio_index); +void gpio_set_int_enable(gpio_t gpio, int enable); +int gpio_get_int_enable(gpio_t gpio); -void gpio_set_int_level(int gpio_index, int high_rise, int edge, int delta); -void gpio_get_int_level(int gpio_index, int *high_rise, int *edge, int *delta); +void gpio_set_int_level(gpio_t gpio, int high_rise, int edge, int delta); +void gpio_get_int_level(gpio_t gpio, int *high_rise, int *edge, int *delta); -void gpio_set_int_clear(int gpio_index); +void gpio_set_int_clear(gpio_t gpio); #endif /* __SOC_NVIDIA_TEGRA_GPIO_H__ */ diff --git a/src/soc/nvidia/tegra/i2c.c b/src/soc/nvidia/tegra/i2c.c index ddb54a5..e9001f0 100644 --- a/src/soc/nvidia/tegra/i2c.c +++ b/src/soc/nvidia/tegra/i2c.c @@ -32,12 +32,10 @@ static int tegra_i2c_send_recv(struct tegra_i2c_regs *regs, int read, { while (data_len) { uint32_t status = read32(&regs->fifo_status); - int tx_empty = - status & TEGRA_I2C_FIFO_STATUS_TX_FIFO_EMPTY_CNT_MASK; - tx_empty >>= TEGRA_I2C_FIFO_STATUS_TX_FIFO_EMPTY_CNT_SHIFT; - int rx_full = - status & TEGRA_I2C_FIFO_STATUS_RX_FIFO_FULL_CNT_MASK; - rx_full >>= TEGRA_I2C_FIFO_STATUS_RX_FIFO_FULL_CNT_SHIFT; + int tx_empty = status & I2C_FIFO_STATUS_TX_FIFO_EMPTY_CNT_MASK; + tx_empty >>= I2C_FIFO_STATUS_TX_FIFO_EMPTY_CNT_SHIFT; + int rx_full = status & I2C_FIFO_STATUS_RX_FIFO_FULL_CNT_MASK; + rx_full >>= I2C_FIFO_STATUS_RX_FIFO_FULL_CNT_SHIFT; while (header_words && tx_empty) { write32(*headers++, &regs->tx_packet_fifo); @@ -73,19 +71,17 @@ static int tegra_i2c_send_recv(struct tegra_i2c_regs *regs, int read, uint32_t transfer_status = read32(&regs->packet_transfer_status); - if (transfer_status & TEGRA_I2C_PKT_STATUS_NOACK_ADDR_MASK) { + if (transfer_status & I2C_PKT_STATUS_NOACK_ADDR) { printk(BIOS_ERR, "%s: The address was not acknowledged.\n", __func__); return -1; - } else if (transfer_status & - TEGRA_I2C_PKT_STATUS_NOACK_DATA_MASK) { + } else if (transfer_status & I2C_PKT_STATUS_NOACK_DATA) { printk(BIOS_ERR, "%s: The data was not acknowledged.\n", __func__); return -1; - } else if (transfer_status & - TEGRA_I2C_PKT_STATUS_ARB_LOST_MASK) { + } else if (transfer_status & I2C_PKT_STATUS_ARB_LOST) { printk(BIOS_ERR, "%s: Lost arbitration.\n", __func__); @@ -108,25 +104,22 @@ static int tegra_i2c_request(int bus, unsigned chip, int cont, int restart, return -1; } - headers[0] = (0 << IOHEADER_WORD0_PROTHDRSZ_SHIFT) | - (1 << IOHEADER_WORD0_PKTID_SHIFT) | - (bus << IOHEADER_WORD0_CONTROLLER_ID_SHIFT) | - IOHEADER_WORD0_PROTOCOL_I2C | - IOHEADER_WORD0_PKTTYPE_REQUEST; + headers[0] = (0 << IOHEADER_PROTHDRSZ_SHIFT) | + (1 << IOHEADER_PKTID_SHIFT) | + (bus << IOHEADER_CONTROLLER_ID_SHIFT) | + IOHEADER_PROTOCOL_I2C | IOHEADER_PKTTYPE_REQUEST; - headers[1] = (data_len - 1) << IOHEADER_WORD1_PAYLOADSIZE_SHIFT; + headers[1] = (data_len - 1) << IOHEADER_PAYLOADSIZE_SHIFT; uint32_t slave_addr = (chip << 1) | (read ? 1 : 0); - headers[2] = IOHEADER_I2C_REQ_ADDRESS_MODE_7BIT | + headers[2] = IOHEADER_I2C_REQ_ADDR_MODE_7BIT | (slave_addr << IOHEADER_I2C_REQ_SLAVE_ADDR_SHIFT); if (read) - headers[2] |= IOHEADER_I2C_REQ_READ_WRITE_READ; - else - headers[2] |= IOHEADER_I2C_REQ_READ_WRITE_WRITE; + headers[2] |= IOHEADER_I2C_REQ_READ; if (restart) - headers[2] |= IOHEADER_I2C_REQ_REPEAT_START_STOP_START; + headers[2] |= IOHEADER_I2C_REQ_REPEAT_START; if (cont) - headers[2] |= IOHEADER_I2C_REQ_CONTINUE_XFER_MASK; + headers[2] |= IOHEADER_I2C_REQ_CONTINUE_XFER; return tegra_i2c_send_recv(regs, read, headers, ARRAY_SIZE(headers), data, data_len); @@ -136,8 +129,7 @@ static int i2c_readwrite(unsigned bus, unsigned chip, unsigned addr, unsigned alen, uint8_t *buf, unsigned len, int read) { const uint32_t max_payload = - (IOHEADER_WORD1_PAYLOADSIZE_MASK + 1) >> - IOHEADER_WORD1_PAYLOADSIZE_SHIFT; + (IOHEADER_PAYLOADSIZE_MASK + 1) >> IOHEADER_PAYLOADSIZE_SHIFT; uint8_t abuf[sizeof(addr)]; int i; @@ -176,5 +168,5 @@ void i2c_init(unsigned bus) { struct tegra_i2c_regs * const regs = tegra_i2c_bases[bus]; - write32(TEGRA_I2C_CNFG_PACKET_MODE_EN_MASK, &regs->cnfg); + write32(I2C_CNFG_PACKET_MODE_EN, &regs->cnfg); } diff --git a/src/soc/nvidia/tegra/i2c.h b/src/soc/nvidia/tegra/i2c.h index 630d890..997ec9c 100644 --- a/src/soc/nvidia/tegra/i2c.h +++ b/src/soc/nvidia/tegra/i2c.h @@ -24,133 +24,90 @@ void i2c_init(unsigned bus); -#define IOHEADER_BITFIELD(name, shift, mask) \ - IOHEADER_##name##_SHIFT = shift, \ - IOHEADER_##name##_MASK = \ - mask << IOHEADER_##name##_SHIFT - -#define IOHEADER_BITFIELD_VAL(field, name, val) \ - IOHEADER_##field##_##name = \ - val << IOHEADER_##field##_SHIFT - enum { /* Word 0 */ - IOHEADER_BITFIELD(WORD0_PROTHDRSZ, 28, 0x3), - - IOHEADER_BITFIELD(WORD0_PKTID, 16, 0xff), - - IOHEADER_BITFIELD(WORD0_CONTROLLER_ID, 12, 0xf), - - IOHEADER_BITFIELD(WORD0_PROTOCOL, 4, 0xf), - IOHEADER_BITFIELD_VAL(WORD0_PROTOCOL, I2C, 1), - - IOHEADER_BITFIELD(WORD0_PKTTYPE, 0, 0x7), - IOHEADER_BITFIELD_VAL(WORD0_PKTTYPE, REQUEST, 0), - IOHEADER_BITFIELD_VAL(WORD0_PKTTYPE, RESPONSE, 1), - IOHEADER_BITFIELD_VAL(WORD0_PKTTYPE, INTERRUPT, 2), - IOHEADER_BITFIELD_VAL(WORD0_PKTTYPE, STOP, 3), + IOHEADER_PROTHDRSZ_SHIFT = 28, + IOHEADER_PROTHDRSZ_MASK = 0x3 << IOHEADER_PROTHDRSZ_SHIFT, + IOHEADER_PKTID_SHIFT = 16, + IOHEADER_PKTID_MASK = 0xff << IOHEADER_PKTID_SHIFT, + IOHEADER_CONTROLLER_ID_SHIFT = 12, + IOHEADER_CONTROLLER_ID_MASK = 0xf << IOHEADER_CONTROLLER_ID_SHIFT, + IOHEADER_PROTOCOL_SHIFT = 4, + IOHEADER_PROTOCOL_MASK = 0xf << IOHEADER_PROTOCOL_SHIFT, + IOHEADER_PROTOCOL_I2C = 1 << IOHEADER_PROTOCOL_SHIFT, + IOHEADER_PKTTYPE_SHIFT = 0, + IOHEADER_PKTTYPE_MASK = 0x7 << IOHEADER_PKTTYPE_SHIFT, + IOHEADER_PKTTYPE_REQUEST = 0 << IOHEADER_PKTTYPE_SHIFT, + IOHEADER_PKTTYPE_RESPONSE = 1 << IOHEADER_PKTTYPE_SHIFT, + IOHEADER_PKTTYPE_INTERRUPT = 2 << IOHEADER_PKTTYPE_SHIFT, + IOHEADER_PKTTYPE_STOP = 3 << IOHEADER_PKTTYPE_SHIFT, /* Word 1 */ - IOHEADER_BITFIELD(WORD1_PAYLOADSIZE, 0, 0xfff) + IOHEADER_PAYLOADSIZE_SHIFT = 0, + IOHEADER_PAYLOADSIZE_MASK = 0xfff << IOHEADER_PAYLOADSIZE_SHIFT }; enum { - IOHEADER_BITFIELD(I2C_REQ_RESP_PKT_FREQ_SHIFT, 25, 0x1), - IOHEADER_BITFIELD_VAL(I2C_REQ_RESP_PKT_FREQ_SHIFT, END, 0), - IOHEADER_BITFIELD_VAL(I2C_REQ_RESP_PKT_FREQ_SHIFT, EACH, 1), - - IOHEADER_BITFIELD(I2C_REQ_RESP_PKT_ENABLE, 24, 0x1), - - IOHEADER_BITFIELD(I2C_REQ_HS_MODE, 22, 0x1), - - IOHEADER_BITFIELD(I2C_REQ_CONTINUE_ON_NACK, 21, 0x1), - - IOHEADER_BITFIELD(I2C_REQ_SEND_START_BYTE, 20, 0x1), - - IOHEADER_BITFIELD(I2C_REQ_READ_WRITE, 19, 0x1), - IOHEADER_BITFIELD_VAL(I2C_REQ_READ_WRITE, WRITE, 0), - IOHEADER_BITFIELD_VAL(I2C_REQ_READ_WRITE, READ, 1), - - IOHEADER_BITFIELD(I2C_REQ_ADDRESS_MODE, 18, 0x1), - IOHEADER_BITFIELD_VAL(I2C_REQ_ADDRESS_MODE, 7BIT, 0), - IOHEADER_BITFIELD_VAL(I2C_REQ_ADDRESS_MODE, 10BIT, 1), - - IOHEADER_BITFIELD(I2C_REQ_IE, 17, 0x1), - - IOHEADER_BITFIELD(I2C_REQ_REPEAT_START_STOP, 16, 0x1), - IOHEADER_BITFIELD_VAL(I2C_REQ_REPEAT_START_STOP, STOP, 0), - IOHEADER_BITFIELD_VAL(I2C_REQ_REPEAT_START_STOP, START, 1), - - IOHEADER_BITFIELD(I2C_REQ_CONTINUE_XFER, 15, 0x1), - - IOHEADER_BITFIELD(I2C_REQ_HS_MASTER_ADDR, 12, 0x7), - - IOHEADER_BITFIELD(I2C_REQ_SLAVE_ADDR, 0, 0x3ff) + IOHEADER_I2C_REQ_RESP_FREQ_MASK = 0x1 << 25, + IOHEADER_I2C_REQ_RESP_FREQ_END = 0 << 25, + IOHEADER_I2C_REQ_RESP_FREQ_EACH = 1 << 25, + IOHEADER_I2C_REQ_RESP_ENABLE = 0x1 << 24, + IOHEADER_I2C_REQ_HS_MODE = 0x1 << 22, + IOHEADER_I2C_REQ_CONTINUE_ON_NACK = 0x1 << 21, + IOHEADER_I2C_REQ_SEND_START_BYTE = 0x1 << 20, + IOHEADER_I2C_REQ_READ = 0x1 << 19, + IOHEADER_I2C_REQ_ADDR_MODE_MASK = 0x1 << 18, + IOHEADER_I2C_REQ_ADDR_MODE_7BIT = 0 << 18, + IOHEADER_I2C_REQ_ADDR_MODE_10BIT = 1 << 18, + IOHEADER_I2C_REQ_IE = 0x1 << 17, + IOHEADER_I2C_REQ_REPEAT_START = 0x1 << 16, + IOHEADER_I2C_REQ_STOP = 0x0 << 16, + IOHEADER_I2C_REQ_CONTINUE_XFER = 0x1 << 15, + IOHEADER_I2C_REQ_HS_MASTER_ADDR_SHIFT = 12, + IOHEADER_I2C_REQ_HS_MASTER_ADDR_MASK = + 0x7 << IOHEADER_I2C_REQ_HS_MASTER_ADDR_SHIFT, + IOHEADER_I2C_REQ_SLAVE_ADDR_SHIFT = 0, + IOHEADER_I2C_REQ_SLAVE_ADDR_MASK = + 0x3ff << IOHEADER_I2C_REQ_SLAVE_ADDR_SHIFT }; enum { - TEGRA_I2C_CNFG_MSTR_CLR_BUS_ON_TIMEOUT_SHIFT = 15, - TEGRA_I2C_CNFG_MSTR_CLR_BUS_ON_TIMEOUT_MASK = - 0x1 << TEGRA_I2C_CNFG_MSTR_CLR_BUS_ON_TIMEOUT_SHIFT, - TEGRA_I2C_CNFG_DEBOUNCE_CNT_SHIFT = 12, - TEGRA_I2C_CNFG_DEBOUNCE_CNT_MASK = - 0x7 << TEGRA_I2C_CNFG_DEBOUNCE_CNT_SHIFT, - TEGRA_I2C_CNFG_NEW_MASTER_FSM_SHIFT = 11, - TEGRA_I2C_CNFG_NEW_MASTER_FSM_MASK = - 0x1 << TEGRA_I2C_CNFG_NEW_MASTER_FSM_SHIFT, - TEGRA_I2C_CNFG_PACKET_MODE_EN_SHIFT = 10, - TEGRA_I2C_CNFG_PACKET_MODE_EN_MASK = - 0x1 << TEGRA_I2C_CNFG_PACKET_MODE_EN_SHIFT, - TEGRA_I2C_CNFG_SEND_SHIFT = 9, - TEGRA_I2C_CNFG_SEND_MASK = 0x1 << TEGRA_I2C_CNFG_SEND_SHIFT, - TEGRA_I2C_CNFG_NOACK_SHIFT = 8, - TEGRA_I2C_CNFG_NOACK_MASK = 0x1 << TEGRA_I2C_CNFG_NOACK_SHIFT, - TEGRA_I2C_CNFG_CMD2_SHIFT = 7, - TEGRA_I2C_CNFG_CMD2_MASK = 0x1 << TEGRA_I2C_CNFG_CMD2_SHIFT, - TEGRA_I2C_CNFG_CMD1_SHIFT = 6, - TEGRA_I2C_CNFG_CMD1_MASK = 0x1 << TEGRA_I2C_CNFG_CMD1_SHIFT, - TEGRA_I2C_CNFG_START_SHIFT = 5, - TEGRA_I2C_CNFG_START_MASK = 0x1 << TEGRA_I2C_CNFG_START_SHIFT, - TEGRA_I2C_CNFG_SLV2_SHIFT = 4, - TEGRA_I2C_CNFG_SLV2_MASK = 0x1 << TEGRA_I2C_CNFG_SLV2_SHIFT, - TEGRA_I2C_CNFG_LENGTH_SHIFT = 1, - TEGRA_I2C_CNFG_LENGTH_MASK = 0x7 << TEGRA_I2C_CNFG_LENGTH_SHIFT, - TEGRA_I2C_CNFG_A_MOD_SHIFT = 0, - TEGRA_I2C_CNFG_A_MOD_MASK = 0x1 << TEGRA_I2C_CNFG_A_MOD_SHIFT + I2C_CNFG_MSTR_CLR_BUS_ON_TIMEOUT = 0x1 << 15, + I2C_CNFG_DEBOUNCE_CNT_SHIFT = 12, + I2C_CNFG_DEBOUNCE_CNT_MASK = 0x7 << I2C_CNFG_DEBOUNCE_CNT_SHIFT, + I2C_CNFG_NEW_MASTER_FSM = 0x1 << 11, + I2C_CNFG_PACKET_MODE_EN = 0x1 << 10, + I2C_CNFG_SEND = 0x1 << 9, + I2C_CNFG_NOACK = 0x1 << 8, + I2C_CNFG_CMD2 = 0x1 << 7, + I2C_CNFG_CMD1 = 0x1 << 6, + I2C_CNFG_START = 0x1 << 5, + I2C_CNFG_SLV2_SHIFT = 4, + I2C_CNFG_SLV2_MASK = 0x1 << I2C_CNFG_SLV2_SHIFT, + I2C_CNFG_LENGTH_SHIFT = 1, + I2C_CNFG_LENGTH_MASK = 0x7 << I2C_CNFG_LENGTH_SHIFT, + I2C_CNFG_A_MOD = 0x1 << 0, }; enum { - TEGRA_I2C_PKT_STATUS_COMPLETE_SHIFT = 24, - TEGRA_I2C_PKT_STATUS_COMPLETE_MASK = - 0x1 << TEGRA_I2C_PKT_STATUS_COMPLETE_SHIFT, - TEGRA_I2C_PKT_STATUS_PKT_ID_SHIFT = 16, - TEGRA_I2C_PKT_STATUS_PKT_ID_MASK = - 0xff << TEGRA_I2C_PKT_STATUS_PKT_ID_SHIFT, - TEGRA_I2C_PKT_STATUS_BYTENUM_SHIFT = 4, - TEGRA_I2C_PKT_STATUS_BYTENUM_MASK = - 0xfff << TEGRA_I2C_PKT_STATUS_BYTENUM_SHIFT, - TEGRA_I2C_PKT_STATUS_NOACK_ADDR_SHIFT = 3, - TEGRA_I2C_PKT_STATUS_NOACK_ADDR_MASK = - 0x1 << TEGRA_I2C_PKT_STATUS_NOACK_ADDR_SHIFT, - TEGRA_I2C_PKT_STATUS_NOACK_DATA_SHIFT = 2, - TEGRA_I2C_PKT_STATUS_NOACK_DATA_MASK = - 0x1 << TEGRA_I2C_PKT_STATUS_NOACK_DATA_SHIFT, - TEGRA_I2C_PKT_STATUS_ARB_LOST_SHIFT = 1, - TEGRA_I2C_PKT_STATUS_ARB_LOST_MASK = - 0x1 << TEGRA_I2C_PKT_STATUS_ARB_LOST_SHIFT, - TEGRA_I2C_PKT_STATUS_BUSY_SHIFT = 0, - TEGRA_I2C_PKT_STATUS_BUSY_MASK = - 0x1 << TEGRA_I2C_PKT_STATUS_BUSY_SHIFT, + I2C_PKT_STATUS_COMPLETE = 0x1 << 24, + I2C_PKT_STATUS_PKT_ID_SHIFT = 16, + I2C_PKT_STATUS_PKT_ID_MASK = 0xff << I2C_PKT_STATUS_PKT_ID_SHIFT, + I2C_PKT_STATUS_BYTENUM_SHIFT = 4, + I2C_PKT_STATUS_BYTENUM_MASK = 0xfff << I2C_PKT_STATUS_BYTENUM_SHIFT, + I2C_PKT_STATUS_NOACK_ADDR = 0x1 << 3, + I2C_PKT_STATUS_NOACK_DATA = 0x1 << 2, + I2C_PKT_STATUS_ARB_LOST = 0x1 << 1, + I2C_PKT_STATUS_BUSY = 0x1 << 0 }; enum { - TEGRA_I2C_FIFO_STATUS_TX_FIFO_EMPTY_CNT_SHIFT = 4, - TEGRA_I2C_FIFO_STATUS_TX_FIFO_EMPTY_CNT_MASK = - 0xf << TEGRA_I2C_FIFO_STATUS_TX_FIFO_EMPTY_CNT_SHIFT, - - TEGRA_I2C_FIFO_STATUS_RX_FIFO_FULL_CNT_SHIFT = 0, - TEGRA_I2C_FIFO_STATUS_RX_FIFO_FULL_CNT_MASK = - 0xf << TEGRA_I2C_FIFO_STATUS_RX_FIFO_FULL_CNT_SHIFT + I2C_FIFO_STATUS_TX_FIFO_EMPTY_CNT_SHIFT = 4, + I2C_FIFO_STATUS_TX_FIFO_EMPTY_CNT_MASK = + 0xf << I2C_FIFO_STATUS_TX_FIFO_EMPTY_CNT_SHIFT, + I2C_FIFO_STATUS_RX_FIFO_FULL_CNT_SHIFT = 0, + I2C_FIFO_STATUS_RX_FIFO_FULL_CNT_MASK = + 0xf << I2C_FIFO_STATUS_RX_FIFO_FULL_CNT_SHIFT }; extern void * const tegra_i2c_bases[]; diff --git a/src/soc/nvidia/tegra124/Kconfig b/src/soc/nvidia/tegra124/Kconfig index 4e5bd62..30c9feb 100644 --- a/src/soc/nvidia/tegra124/Kconfig +++ b/src/soc/nvidia/tegra124/Kconfig @@ -4,6 +4,7 @@ config SOC_NVIDIA_TEGRA124 select ARCH_RAMSTAGE_ARMV7 select HAVE_UART_SPECIAL select BOOTBLOCK_CONSOLE + select DYNAMIC_CBMEM select ARM_BOOTBLOCK_CUSTOM bool default n diff --git a/src/soc/nvidia/tegra124/Makefile.inc b/src/soc/nvidia/tegra124/Makefile.inc index 1a04051..d78553d 100644 --- a/src/soc/nvidia/tegra124/Makefile.inc +++ b/src/soc/nvidia/tegra124/Makefile.inc @@ -2,8 +2,13 @@ bootblock-y += bootblock.c bootblock-y += bootblock_asm.S bootblock-y += cbfs.c bootblock-y += clock.c +bootblock-y += cpug.S +bootblock-y += dma.c bootblock-y += i2c.c +bootblock-y += dma.c bootblock-y += monotonic_timer.c +bootblock-y += power.c +bootblock-y += spi.c bootblock-y += ../tegra/gpio.c bootblock-y += ../tegra/i2c.c bootblock-y += ../tegra/pingroup.c @@ -14,12 +19,31 @@ bootblock-$(CONFIG_CONSOLE_SERIAL) += uart.c endif romstage-y += cbfs.c +romstage-y += cbmem.c +romstage-y += early_display.c +romstage-y += dma.c +romstage-y += i2c.c romstage-y += monotonic_timer.c +romstage-y += spi.c +romstage-y += ../tegra/gpio.c +romstage-y += ../tegra/i2c.c +romstage-y += ../tegra/pinmux.c romstage-y += timer.c romstage-$(CONFIG_CONSOLE_SERIAL) += uart.c ramstage-y += cbfs.c +ramstage-y += cbmem.c +ramstage-y += cpug.S +ramstage-y += clock.c +ramstage-y += display.c +ramstage-y += dma.c +ramstage-y += i2c.c ramstage-y += monotonic_timer.c +ramstage-y += soc.c +ramstage-y += spi.c +ramstage-y += ../tegra/gpio.c +ramstage-y += ../tegra/i2c.c +ramstage-y += ../tegra/pinmux.c ramstage-y += timer.c ramstage-$(CONFIG_CONSOLE_SERIAL) += uart.c diff --git a/src/soc/nvidia/tegra124/bootblock.c b/src/soc/nvidia/tegra124/bootblock.c index a3bed23..2698611 100644 --- a/src/soc/nvidia/tegra124/bootblock.c +++ b/src/soc/nvidia/tegra124/bootblock.c @@ -18,38 +18,19 @@ */ #include <arch/hlt.h> -#include <arch/io.h> +#include <bootblock_common.h> #include <cbfs.h> #include <console/console.h> -#include <delay.h> +#include <soc/clock.h> -#include "clock.h" #include "pinmux.h" - -static void hacky_hardcoded_uart_setup_function(void) -{ - // Assert UART reset and enable clock. - setbits_le32((void *)(0x60006000 + 4 + 0), 1 << 6); - - // Enable the clock. - setbits_le32((void *)(0x60006000 + 4 * 4 + 0), 1 << 6); - - // Set the clock source. - clrbits_le32((void *)(0x60006000 + 0x100 + 4 * 0x1e), 3 << 30); - - udelay(2); - - // De-assert reset to UART. - clrbits_le32((void *)(0x60006000 + 4 + 0), 1 << 6); -} +#include "power.h" void main(void) { void *entry; - set_avp_clock_to_clkm(); - - hacky_hardcoded_uart_setup_function(); + clock_early_uart(); // Serial out, tristate off. pinmux_set_config(PINMUX_KB_ROW9_INDEX, PINMUX_KB_ROW9_FUNC_UA3); @@ -61,7 +42,26 @@ void main(void) if (CONFIG_BOOTBLOCK_CONSOLE) console_init(); + clock_init(); + + bootblock_mainboard_init(); + + pinmux_set_config(PINMUX_CORE_PWR_REQ_INDEX, + PINMUX_CORE_PWR_REQ_FUNC_PWRON); + pinmux_set_config(PINMUX_CPU_PWR_REQ_INDEX, + PINMUX_CPU_PWR_REQ_FUNC_CPU); + pinmux_set_config(PINMUX_PWR_INT_N_INDEX, + PINMUX_PWR_INT_N_FUNC_PMICINTR | + PINMUX_TRISTATE | + PINMUX_INPUT_ENABLE); + + power_enable_cpu_rail(); + power_ungate_cpu(); + entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, "fallback/romstage"); + if (entry) + clock_cpu0_config_and_reset(entry); + hlt(); } diff --git a/src/soc/nvidia/tegra124/cbfs.c b/src/soc/nvidia/tegra124/cbfs.c index ede9146..4497d6a 100644 --- a/src/soc/nvidia/tegra124/cbfs.c +++ b/src/soc/nvidia/tegra124/cbfs.c @@ -20,7 +20,11 @@ #include <cbfs.h> /* This driver serves as a CBFS media source. */ +#include "spi.h" + int init_default_cbfs_media(struct cbfs_media *media) { - return -1; + return initialize_tegra_spi_cbfs_media(media, + (void*)CONFIG_CBFS_CACHE_ADDRESS, + CONFIG_CBFS_CACHE_SIZE); } diff --git a/src/soc/nvidia/tegra124/cbmem.c b/src/soc/nvidia/tegra124/cbmem.c new file mode 100644 index 0000000..d80b3a0 --- /dev/null +++ b/src/soc/nvidia/tegra124/cbmem.c @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <cbmem.h> +#include <soc/addressmap.h> + +void *cbmem_top(void) +{ + return (void *)(CONFIG_SYS_SDRAM_BASE + + ((CONFIG_DRAM_SIZE_MB - FB_SIZE_MB)<< 20UL)); +} diff --git a/src/soc/nvidia/tegra124/chip.h b/src/soc/nvidia/tegra124/chip.h new file mode 100644 index 0000000..b05bcc7 --- /dev/null +++ b/src/soc/nvidia/tegra124/chip.h @@ -0,0 +1,91 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef __SOC_NVIDIA_TEGRA124_CHIP_H__ +#define __SOC_NVIDIA_TEGRA124_CHIP_H__ +#include <arch/cache.h> +#include <soc/addressmap.h> +#include "gpio.h" + +/* this is a misuse of the device tree. We're going to let it go for now but + * we should at minimum have a struct for the display controller, since + * the chip supports two. + */ +struct soc_nvidia_tegra124_config { + int xres; + int yres; + int framebuffer_bits_per_pixel; + int cache_policy; + /* there are two. It's not unimaginable that we might someday + * have two of these structs in a single mainboard. + */ + u32 display_controller; + u32 framebuffer_base; + /* Technically, we can compute this. At the same time, some platforms + * might want to specify a specific size for their own reasons. If it is + * zero the soc code will compute it as xres*yres*framebuffer_bits_per_pixel/4 + */ + u32 framebuffer_size; + /* GPIOs -- all, some, or none are used. Unused ones can be ignored + * in devicetree.cb since if they are not set there they default to 0, + * and 0 for a gpio means 'unused GPIO'. + */ + gpio_t backlight_en_gpio; + gpio_t lvds_shutdown_gpio; + gpio_t backlight_vdd_gpio; + gpio_t panel_vdd_gpio; + + /* required info. */ + /* pwm to use to set display contrast */ + int pwm; + /* timings -- five numbers, all relative to the previous + * event, not to absolute time. e.g., vdd_data_delay is the + * delay from vdd on to data, not from power on to data. + * This is stated to be four timings in the + * u-boot docs. In any event, in coreboot, we generally + * only delay long enough to let the panel wake up and then + * do the control operations -- meaming, for *coreboot* + * we probably only need the vdd_delay, but payloads may + * need the other info. + */ + /* Delay before from power on asserting vdd */ + int vdd_delay; + /* delay between panel_vdd-rise and data-rise*/ + int vdd_data_delay; + /* delay between data-rise and backlight_vdd-rise */ + int data_backlight_delay; + /* delay between backlight_vdd and pwm-rise */ + int backlight_pwm_delay; + /* delay between pwm-rise and backlight_en-rise */ + int pwm_backlight_en_delay; + /* display timing. + * we have not found a dts in which these are set */ + int href_to_sync; /* u-boot code says 'set to 1' */ + int hsync_width; + int hback_porch; + int hfront_porch; + int vref_to_sync; /* u-boot code says 'set to 1' */ + int vsync_width; + int vback_porch; + int vfront_porch; + + int pixel_clock; +}; + +#endif /* __SOC_NVIDIA_TEGRA124_CHIP_H__ */ diff --git a/src/soc/nvidia/tegra124/clk_rst.h b/src/soc/nvidia/tegra124/clk_rst.h index badb58b..4280f3c 100644 --- a/src/soc/nvidia/tegra124/clk_rst.h +++ b/src/soc/nvidia/tegra124/clk_rst.h @@ -17,203 +17,275 @@ #ifndef _TEGRA124_CLK_RST_H_ #define _TEGRA124_CLK_RST_H_ -/* PLL registers - there are several PLLs in the clock controller */ -struct clk_pll { - u32 pll_base; /* the control register */ - /* pll_out[0] is output A control, pll_out[1] is output B control */ - u32 pll_out[2]; - u32 pll_misc; /* other misc things */ -}; - -/* PLL registers - there are several PLLs in the clock controller */ -struct clk_pll_simple { - u32 pll_base; /* the control register */ - u32 pll_misc; /* other misc things */ -}; - -struct clk_pllm { - u32 pllm_base; /* the control register */ - u32 pllm_out; /* output control */ - u32 pllm_misc1; /* misc1 */ - u32 pllm_misc2; /* misc2 */ -}; - -/* RST_DEV_(L,H,U,V,W)_(SET,CLR) and CLK_ENB_(L,H,U,V,W)_(SET,CLR) */ -struct clk_set_clr { - u32 set; - u32 clr; -}; - -/* - * Most PLLs use the clk_pll structure, but some have a simpler two-member - * structure for which we use clk_pll_simple. The reason for this non- - * othogonal setup is not stated. - */ -enum { - TEGRA_CLK_PLLS = 6, /* Number of normal PLLs */ - TEGRA_CLK_SIMPLE_PLLS = 3, /* Number of simple PLLs */ - TEGRA_CLK_REGS = 3, /* Number of clock enable regs L/H/U */ - TEGRA_CLK_SOURCES = 64, /* Number of ppl clock sources L/H/U */ - TEGRA_CLK_REGS_VW = 2, /* Number of clock enable regs V/W */ - TEGRA_CLK_SOURCES_VW = 32, /* Number of ppl clock sources V/W */ - TEGRA_CLK_SOURCES_X = 32, /* Number of ppl clock sources X */ -}; - /* Clock/Reset Controller (CLK_RST_CONTROLLER_) regs */ -struct clk_rst_ctlr { - u32 crc_rst_src; /* _RST_SOURCE_0,0x00 */ - u32 crc_rst_dev[TEGRA_CLK_REGS]; /* _RST_DEVICES_L/H/U_0 */ - u32 crc_clk_out_enb[TEGRA_CLK_REGS]; /* _CLK_OUT_ENB_L/H/U_0 */ - u32 crc_reserved0; /* reserved_0, 0x1C */ - u32 crc_cclk_brst_pol; /* _CCLK_BURST_POLICY_0, 0x20 */ - u32 crc_super_cclk_div; /* _SUPER_CCLK_DIVIDER_0,0x24 */ - u32 crc_sclk_brst_pol; /* _SCLK_BURST_POLICY_0, 0x28 */ - u32 crc_super_sclk_div; /* _SUPER_SCLK_DIVIDER_0,0x2C */ - u32 crc_clk_sys_rate; /* _CLK_SYSTEM_RATE_0, 0x30 */ - u32 crc_reserved01; /* reserved_0_1, 0x34 */ - u32 crc_reserved02; /* reserved_0_2, 0x38 */ - u32 crc_reserved1; /* reserved_1, 0x3C */ - u32 crc_cop_clk_skip_plcy; /* _COP_CLK_SKIP_POLICY_0,0x40 */ - u32 crc_clk_mask_arm; /* _CLK_MASK_ARM_0, 0x44 */ - u32 crc_misc_clk_enb; /* _MISC_CLK_ENB_0, 0x48 */ - u32 crc_clk_cpu_cmplx; /* _CLK_CPU_CMPLX_0, 0x4C */ - u32 crc_osc_ctrl; /* _OSC_CTRL_0, 0x50 */ - u32 crc_pll_lfsr; /* _PLL_LFSR_0, 0x54 */ - u32 crc_osc_freq_det; /* _OSC_FREQ_DET_0, 0x58 */ - u32 crc_osc_freq_det_stat; /* _OSC_FREQ_DET_STATUS_0,0x5C */ - u32 crc_reserved2[8]; /* reserved_2[8], 0x60-7C */ - - struct clk_pll crc_pll[TEGRA_CLK_PLLS]; /* PLLs from 0x80 to 0xdc */ - - /* PLLs from 0xe0 to 0xf4 */ - struct clk_pll_simple crc_pll_simple[TEGRA_CLK_SIMPLE_PLLS]; - - u32 crc_reserved10; /* _reserved_10, 0xF8 */ - u32 crc_reserved11; /* _reserved_11, 0xFC */ - - u32 crc_clk_src[TEGRA_CLK_SOURCES]; /*_I2S1_0... 0x100-1fc */ - - u32 crc_reserved20[32]; /* _reserved_20, 0x200-27c */ - - u32 crc_clk_out_enb_x; /* _CLK_OUT_ENB_X_0, 0x280 */ - u32 crc_clk_enb_x_set; /* _CLK_ENB_X_SET_0, 0x284 */ - u32 crc_clk_enb_x_clr; /* _CLK_ENB_X_CLR_0, 0x288 */ - - u32 crc_rst_devices_x; /* _RST_DEVICES_X_0, 0x28c */ - u32 crc_rst_dev_x_set; /* _RST_DEV_X_SET_0, 0x290 */ - u32 crc_rst_dev_x_clr; /* _RST_DEV_X_CLR_0, 0x294 */ - - u32 crc_reserved21[23]; /* _reserved_21, 0x298-2f0 */ - - u32 crc_dfll_base; /* _DFLL_BASE_0, 0x2f4 */ - - u32 crc_reserved22[2]; /* _reserved_22, 0x2f8-2fc */ - - /* _RST_DEV_L/H/U_SET_0 0x300 ~ 0x314 */ - struct clk_set_clr crc_rst_dev_ex[TEGRA_CLK_REGS]; - - u32 crc_reserved30[2]; /* _reserved_30, 0x318, 0x31c */ - - /* _CLK_ENB_L/H/U_CLR_0 0x320 ~ 0x334 */ - struct clk_set_clr crc_clk_enb_ex[TEGRA_CLK_REGS]; - - u32 crc_reserved31; /* _reserved_31, 0x338 */ - - u32 crc_ccplex_pg_sm_ovrd; /* _CCPLEX_PG_SM_OVRD_0, 0x33c */ - - u32 crc_rst_cpu_cmplx_set; /* _RST_CPU_CMPLX_SET_0, 0x340 */ - u32 crc_rst_cpu_cmplx_clr; /* _RST_CPU_CMPLX_CLR_0, 0x344 */ - u32 crc_clk_cpu_cmplx_set; /* _CLK_CPU_CMPLX_SET_0, 0x348 */ - u32 crc_clk_cpu_cmplx_clr; /* _CLK_CPU_CMPLX_SET_0, 0x34c */ - - u32 crc_reserved32[2]; /* _reserved_32, 0x350,0x354 */ - - u32 crc_rst_dev_vw[TEGRA_CLK_REGS_VW]; /* _RST_DEVICES_V/W_0 */ - u32 crc_clk_out_enb_vw[TEGRA_CLK_REGS_VW]; /* _CLK_OUT_ENB_V/W_0 */ - u32 crc_cclkg_brst_pol; /* _CCLKG_BURST_POLICY_0, 0x368 */ - u32 crc_super_cclkg_div; /* _SUPER_CCLKG_DIVIDER_0, 0x36C */ - u32 crc_cclklp_brst_pol; /* _CCLKLP_BURST_POLICY_0, 0x370 */ - u32 crc_super_cclkp_div; /* _SUPER_CCLKLP_DIVIDER_0, 0x374 */ - u32 crc_clk_cpug_cmplx; /* _CLK_CPUG_CMPLX_0, 0x378 */ - u32 crc_clk_cpulp_cmplx; /* _CLK_CPULP_CMPLX_0, 0x37C */ - u32 crc_cpu_softrst_ctrl; /* _CPU_SOFTRST_CTRL_0, 0x380 */ - u32 crc_cpu_softrst_ctrl1; /* _CPU_SOFTRST_CTRL1_0, 0x384 */ - u32 crc_cpu_softrst_ctrl2; /* _CPU_SOFTRST_CTRL2_0, 0x388 */ - u32 crc_reserved33[9]; /* _reserved_33, 0x38c-3ac */ - u32 crc_clk_src_vw[TEGRA_CLK_SOURCES_VW]; /* 0x3B0-0x42C */ - /* _RST_DEV_V/W_SET_0 0x430 ~ 0x43c */ - struct clk_set_clr crc_rst_dev_ex_vw[TEGRA_CLK_REGS_VW]; - /* _CLK_ENB_V/W_CLR_0 0x440 ~ 0x44c */ - struct clk_set_clr crc_clk_enb_ex_vw[TEGRA_CLK_REGS_VW]; - u32 crc_rst_cpug_cmplx_set; /* _RST_CPUG_CMPLX_SET_0, 0x450*/ - u32 crc_rst_cpug_cmplx_clr; /* _RST_CPUG_CMPLX_CLR_0, 0x454*/ - u32 crc_rst_cpulp_cmplx_set; /* _RST_CPULP_CMPLX_SET_0, 0x458*/ - u32 crc_rst_cpulp_cmplx_clr; /* _RST_CPULP_CMPLX_CLR_0, 0x45C*/ - u32 crc_clk_cpug_cmplx_set; /* _CLK_CPUG_CMPLX_SET_0, 0x460 */ - u32 crc_clk_cpug_cmplx_clr; /* _CLK_CPUG_CMPLX_CLR_0, 0x464 */ - u32 crc_clk_cpulp_cmplx_set; /* _CLK_CPULP_CMPLX_SET_0, 0x468 */ - u32 crc_clk_cpulp_cmplx_clr; /* _CLK_CPULP_CMPLX_CLR_0, 0x46C */ - u32 crc_cpu_cmplx_status; /* _CPU_CMPLX_STATUS_0, 0x470 */ - u32 crc_reserved40[1]; /* _reserved_40, 0x474 */ - u32 crc_intstatus; /* __INTSTATUS_0, 0x478 */ - u32 crc_intmask; /* __INTMASK_0, 0x47C */ - u32 crc_utmip_pll_cfg0; /* _UTMIP_PLL_CFG0_0, 0x480 */ - u32 crc_utmip_pll_cfg1; /* _UTMIP_PLL_CFG1_0, 0x484 */ - u32 crc_utmip_pll_cfg2; /* _UTMIP_PLL_CFG2_0, 0x488 */ - - u32 crc_plle_aux; /* _PLLE_AUX_0, 0x48C */ - u32 crc_sata_pll_cfg0; /* _SATA_PLL_CFG0_0, 0x490 */ - u32 crc_sata_pll_cfg1; /* _SATA_PLL_CFG1_0, 0x494 */ - u32 crc_pcie_pll_cfg0; /* _PCIE_PLL_CFG0_0, 0x498 */ - - u32 crc_prog_audio_dly_clk; /* _PROG_AUDIO_DLY_CLK_0, 0x49C */ - u32 crc_audio_sync_clk_i2s0; /* _AUDIO_SYNC_CLK_I2S0_0, 0x4A0 */ - u32 crc_audio_sync_clk_i2s1; /* _AUDIO_SYNC_CLK_I2S1_0, 0x4A4 */ - u32 crc_audio_sync_clk_i2s2; /* _AUDIO_SYNC_CLK_I2S2_0, 0x4A8 */ - u32 crc_audio_sync_clk_i2s3; /* _AUDIO_SYNC_CLK_I2S3_0, 0x4AC */ - u32 crc_audio_sync_clk_i2s4; /* _AUDIO_SYNC_CLK_I2S4_0, 0x4B0 */ - u32 crc_audio_sync_clk_spdif; /* _AUDIO_SYNC_CLK_SPDIF_0, 0x4B4 */ - - u32 crc_plld2_base; /* _PLLD2_BASE_0, 0x4B8 */ - u32 crc_plld2_misc; /* _PLLD2_MISC_0, 0x4BC */ - u32 crc_utmip_pll_cfg3; /* _UTMIP_PLL_CFG3_0, 0x4C0 */ - u32 crc_pllrefe_base; /* _PLLREFE_BASE_0, 0x4C4 */ - u32 crc_pllrefe_misc; /* _PLLREFE_MISC_0, 0x4C8 */ - u32 crs_reserved_50[7]; /* _reserved_50, 0x4CC-0x4E4 */ - u32 crc_pllc2_base; /* _PLLC2_BASE_0, 0x4E8 */ - u32 crc_pllc2_misc0; /* _PLLC2_MISC_0_0, 0x4EC */ - u32 crc_pllc2_misc1; /* _PLLC2_MISC_1_0, 0x4F0 */ - u32 crc_pllc2_misc2; /* _PLLC2_MISC_2_0, 0x4F4 */ - u32 crc_pllc2_misc3; /* _PLLC2_MISC_3_0, 0x4F8 */ - u32 crc_pllc3_base; /* _PLLC3_BASE_0, 0x4FC */ - u32 crc_pllc3_misc0; /* _PLLC3_MISC_0_0, 0x500 */ - u32 crc_pllc3_misc1; /* _PLLC3_MISC_1_0, 0x504 */ - u32 crc_pllc3_misc2; /* _PLLC3_MISC_2_0, 0x508 */ - u32 crc_pllc3_misc3; /* _PLLC3_MISC_3_0, 0x50C */ - u32 crc_pllx_misc1; /* _PLLX_MISC_1_0, 0x510 */ - u32 crc_pllx_misc2; /* _PLLX_MISC_2_0, 0x514 */ - u32 crc_pllx_misc3; /* _PLLX_MISC_3_0, 0x518 */ - u32 crc_xusbio_pll_cfg0; /* _XUSBIO_PLL_CFG0_0, 0x51C */ - u32 crc_xusbio_pll_cfg1; /* _XUSBIO_PLL_CFG0_1, 0x520 */ - u32 crc_plle_aux1; /* _PLLE_AUX1_0, 0x524 */ - u32 crc_pllp_reshift; /* _PLLP_RESHIFT_0, 0x528 */ - u32 crc_utmipll_hw_pwrdn_cfg0; /* _UTMIPLL_HW_PWRDN_CFG0_0, 0x52C */ - u32 crc_pllu_hw_pwrdn_cfg0; /* _PLLU_HW_PWRDN_CFG0_0, 0x530 */ - u32 crc_xusb_pll_cfg0; /* _XUSB_PLL_CFG0_0, 0x534 */ - u32 crc_reserved51[1]; /* _reserved_51, 0x538 */ - u32 crc_clk_cpu_misc; /* _CLK_CPU_MISC_0, 0x53C */ - u32 crc_clk_cpug_misc; /* _CLK_CPUG_MISC_0, 0x540 */ - u32 crc_clk_cpulp_misc; /* _CLK_CPULP_MISC_0, 0x544 */ - u32 crc_pllx_hw_ctrl_cfg; /* _PLLX_HW_CTRL_CFG_0, 0x548 */ - u32 crc_pllx_sw_ramp_cfg; /* _PLLX_SW_RAMP_CFG_0, 0x54C */ - u32 crc_pllx_hw_ctrl_status; /* _PLLX_HW_CTRL_STATUS_0, 0x550 */ - u32 crc_reserved52[1]; /* _reserved_52, 0x554 */ - u32 crc_super_gr3d_clk_div; /* _SUPER_GR3D_CLK_DIVIDER_0, 0x558 */ - u32 crc_spare_reg0; /* _SPARE_REG0_0, 0x55C */ - - /* T124 - skip to 0x600 here for new CLK_SOURCE_ regs */ - u32 crc_reserved60[40]; /* _reserved_60, 0x560 - 0x5FC */ - u32 crc_clk_src_x[TEGRA_CLK_SOURCES_X]; /* XUSB, etc, 0x600-0x678 */ +struct __attribute__ ((__packed__)) clk_rst_ctlr { + u32 rst_src; /* _RST_SOURCE, 0x000 */ + u32 rst_dev_l; /* _RST_DEVICES_L, 0x004 */ + u32 rst_dev_h; /* _RST_DEVICES_H, 0x008 */ + u32 rst_dev_u; /* _RST_DEVICES_U, 0x00c */ + u32 clk_out_enb_l; /* _CLK_OUT_ENB_L, 0x010 */ + u32 clk_out_enb_h; /* _CLK_OUT_ENB_H, 0x014 */ + u32 clk_out_enb_u; /* _CLK_OUT_ENB_U, 0x018 */ + u32 _rsv0; /* 0x01c */ + u32 cclk_brst_pol; /* _CCLK_BURST_POLICY, 0x020 */ + u32 super_cclk_div; /* _SUPER_CCLK_DIVIDER, 0x024 */ + u32 sclk_brst_pol; /* _SCLK_BURST_POLICY, 0x028 */ + u32 super_sclk_div; /* _SUPER_SCLK_DIVIDER, 0x02C */ + u32 clk_sys_rate; /* _CLK_SYSTEM_RATE, 0x030 */ + u32 _rsv1[3]; /* 0x034-03c */ + u32 cop_clk_skip_plcy; /* _COP_CLK_SKIP_POLICY, 0x040 */ + u32 clk_mask_arm; /* _CLK_MASK_ARM, 0x044 */ + u32 misc_clk_enb; /* _MISC_CLK_ENB, 0x048 */ + u32 clk_cpu_cmplx; /* _CLK_CPU_CMPLX, 0x04C */ + u32 osc_ctrl; /* _OSC_CTRL, 0x050 */ + u32 pll_lfsr; /* _PLL_LFSR, 0x054 */ + u32 osc_freq_det; /* _OSC_FREQ_DET, 0x058 */ + u32 osc_freq_det_stat; /* _OSC_FREQ_DET_STATUS, 0x05C */ + u32 _rsv2[8]; /* 0x060-07C */ + u32 pllc_base; /* _PLLC_BASE, 0x080 */ + u32 pllc_out; /* _PLLC_OUT, 0x084 */ + u32 pllc_misc2; /* _PLLC_MISC2, 0x088 */ + u32 pllc_misc; /* _PLLC_MISC, 0x08c */ + u32 pllm_base; /* _PLLM_BASE, 0x090 */ + u32 pllm_out; /* _PLLM_OUT, 0x094 */ + u32 pllm_misc1; /* _PLLM_MISC1, 0x098 */ + u32 pllm_misc2; /* _PLLM_MISC2, 0x09c */ + u32 pllp_base; /* _PLLP_BASE, 0x0a0 */ + u32 pllp_outa; /* _PLLP_OUTA, 0x0a4 */ + u32 pllp_outb; /* _PLLP_OUTB, 0x0a8 */ + u32 pllp_misc; /* _PLLP_MISC, 0x0ac */ + u32 plla_base; /* _PLLA_BASE, 0x0b0 */ + u32 plla_out; /* _PLLA_OUT, 0x0b4 */ + u32 _rsv3; /* 0x0b8 */ + u32 plla_misc; /* _PLLA_MISC, 0x0bc */ + u32 pllu_base; /* _PLLU_BASE, 0x0c0 */ + u32 _rsv4[2]; /* 0x0c4-0c8 */ + u32 pllu_misc; /* _PLLU_MISC, 0x0cc */ + u32 plld_base; /* _PLLD_BASE, 0x0d0 */ + u32 _rsv5[2]; /* 0x0d4-0d8 */ + u32 plld_misc; /* _PLLD_MISC, 0x0dc */ + u32 pllx_base; /* _PLLX_BASE, 0x0e0 */ + u32 pllx_misc; /* _PLLX_MISC, 0x0e4 */ + u32 plle_base; /* _PLLE_BASE, 0x0e8 */ + u32 plle_misc; /* _PLLE_MISC, 0x0ec */ + u32 plls_base; /* _PLLS_BASE, 0x0f0 */ + u32 plls_misc; /* _PLLS_MISC, 0x0f4 */ + u32 _rsv6[2]; /* 0x0f8-0fc */ + u32 clk_src_i2s1; /* _CLK_SOURCE_I2S1, 0x100 */ + u32 clk_src_i2s2; /* _CLK_SOURCE_I2S2, 0x104 */ + u32 clk_src_spdif_out; /* _CLK_SOURCE_SPDIF_OUT, 0x108 */ + u32 clk_src_spdif_in; /* _CLK_SOURCE_SPDIF_IN, 0x10c */ + u32 clk_src_pwm; /* _CLK_SOURCE_PWM, 0x110 */ + u32 _rsv7; /* 0x114 */ + u32 clk_src_sbc2; /* _CLK_SOURCE_SBC2, 0x118 */ + u32 clk_src_sbc3; /* _CLK_SOURCE_SBC3, 0x11c */ + u32 _rsv8; /* 0x120 */ + u32 clk_src_i2c1; /* _CLK_SOURCE_I2C1, 0x124 */ + u32 clk_src_i2c5; /* _CLK_SOURCE_I2C5, 0x128 */ + u32 _rsv9[2]; /* 0x12c-130 */ + u32 clk_src_sbc1; /* _CLK_SOURCE_SBC1, 0x134 */ + u32 clk_src_disp1; /* _CLK_SOURCE_DISP1, 0x138 */ + u32 clk_src_disp2; /* _CLK_SOURCE_DISP2, 0x13c */ + u32 _rsv10[2]; /* 0x140-144 */ + u32 clk_src_vi; /* _CLK_SOURCE_VI, 0x148 */ + u32 _rsv11; /* 0x14c */ + u32 clk_src_sdmmc1; /* _CLK_SOURCE_SDMMC1, 0x150 */ + u32 clk_src_sdmmc2; /* _CLK_SOURCE_SDMMC2, 0x154 */ + u32 clk_src_g3d; /* _CLK_SOURCE_G3D, 0x158 */ + u32 clk_src_g2d; /* _CLK_SOURCE_G2D, 0x15c */ + u32 clk_src_ndflash; /* _CLK_SOURCE_NDFLASH, 0x160 */ + u32 clk_src_sdmmc4; /* _CLK_SOURCE_SDMMC4, 0x164 */ + u32 clk_src_vfir; /* _CLK_SOURCE_VFIR, 0x168 */ + u32 clk_src_epp; /* _CLK_SOURCE_EPP, 0x16c */ + u32 clk_src_mpe; /* _CLK_SOURCE_MPE, 0x170 */ + u32 clk_src_hsi; /* _CLK_SOURCE_HSI, 0x174 */ + u32 clk_src_uarta; /* _CLK_SOURCE_UARTA, 0x178 */ + u32 clk_src_uartb; /* _CLK_SOURCE_UARTB, 0x17c */ + u32 clk_src_host1x; /* _CLK_SOURCE_HOST1X, 0x180 */ + u32 _rsv12[2]; /* 0x184-188 */ + u32 clk_src_hdmi; /* _CLK_SOURCE_HDMI, 0x18c */ + u32 _rsv13[2]; /* 0x190-194 */ + u32 clk_src_i2c2; /* _CLK_SOURCE_I2C2, 0x198 */ + u32 clk_src_emc; /* _CLK_SOURCE_EMC, 0x19c */ + u32 clk_src_uartc; /* _CLK_SOURCE_UARTC, 0x1a0 */ + u32 _rsv14; /* 0x1a4 */ + u32 clk_src_vi_sensor; /* _CLK_SOURCE_VI_SENSOR, 0x1a8 */ + u32 _rsv15[2]; /* 0x1ac-1b0 */ + u32 clk_src_sbc4; /* _CLK_SOURCE_SBC4, 0x1b4 */ + u32 clk_src_i2c3; /* _CLK_SOURCE_I2C3, 0x1b8 */ + u32 clk_src_sdmmc3; /* _CLK_SOURCE_SDMMC3, 0x1bc */ + u32 clk_src_uartd; /* _CLK_SOURCE_UARTD, 0x1c0 */ + u32 clk_src_uarte; /* _CLK_SOURCE_UARTE, 0x1c4 */ + u32 clk_src_vde; /* _CLK_SOURCE_VDE, 0x1c8 */ + u32 clk_src_owr; /* _CLK_SOURCE_OWR, 0x1cc */ + u32 clk_src_nor; /* _CLK_SOURCE_NOR, 0x1d0 */ + u32 clk_src_csite; /* _CLK_SOURCE_CSITE, 0x1d4 */ + u32 clk_src_i2s0; /* _CLK_SOURCE_I2S0, 0x1d8 */ + u32 clk_src_dtv; /* _CLK_SOURCE_DTV, 0x1dc */ + u32 _rsv16[4]; /* 0x1e0-1ec */ + u32 clk_src_msenc; /* _CLK_SOURCE_MSENC, 0x1f0 */ + u32 clk_src_tsec; /* _CLK_SOURCE_TSEC, 0x1f4 */ + u32 _rsv17; /* 0x1f8 */ + u32 clk_src_osc; /* _CLK_SOURCE_OSC, 0x1fc */ + u32 _rsv18[32]; /* 0x200-27c */ + u32 clk_out_enb_x; /* _CLK_OUT_ENB_X_0, 0x280 */ + u32 clk_enb_x_set; /* _CLK_ENB_X_SET_0, 0x284 */ + u32 clk_enb_x_clr; /* _CLK_ENB_X_CLR_0, 0x288 */ + u32 rst_devices_x; /* _RST_DEVICES_X_0, 0x28c */ + u32 rst_dev_x_set; /* _RST_DEV_X_SET_0, 0x290 */ + u32 rst_dev_x_clr; /* _RST_DEV_X_CLR_0, 0x294 */ + u32 _rsv19[23]; /* 0x298-2f0 */ + u32 dfll_base; /* _DFLL_BASE_0, 0x2f4 */ + u32 _rsv20[2]; /* 0x2f8-2fc */ + u32 rst_dev_l_set; /* _RST_DEV_L_SET 0x300 */ + u32 rst_dev_l_clr; /* _RST_DEV_L_CLR 0x304 */ + u32 rst_dev_h_set; /* _RST_DEV_H_SET 0x308 */ + u32 rst_dev_h_clr; /* _RST_DEV_H_CLR 0x30c */ + u32 rst_dev_u_set; /* _RST_DEV_U_SET 0x310 */ + u32 rst_dev_u_clr; /* _RST_DEV_U_CLR 0x314 */ + u32 _rsv21[2]; /* 0x318-31c */ + u32 clk_enb_l_set; /* _CLK_ENB_L_SET 0x320 */ + u32 clk_enb_l_clr; /* _CLK_ENB_L_CLR 0x324 */ + u32 clk_enb_h_set; /* _CLK_ENB_H_SET 0x328 */ + u32 clk_enb_h_clr; /* _CLK_ENB_H_CLR 0x32c */ + u32 clk_enb_u_set; /* _CLK_ENB_U_SET 0x330 */ + u32 clk_enb_u_clk; /* _CLK_ENB_U_CLR 0x334 */ + u32 _rsv22; /* 0x338 */ + u32 ccplex_pg_sm_ovrd; /* _CCPLEX_PG_SM_OVRD, 0x33c */ + u32 rst_cpu_cmplx_set; /* _RST_CPU_CMPLX_SET, 0x340 */ + u32 rst_cpu_cmplx_clr; /* _RST_CPU_CMPLX_CLR, 0x344 */ + u32 clk_cpu_cmplx_set; /* _CLK_CPU_CMPLX_SET, 0x348 */ + u32 clk_cpu_cmplx_clr; /* _CLK_CPU_CMPLX_SET, 0x34c */ + u32 _rsv23[2]; /* 0x350-354 */ + u32 rst_dev_v; /* _RST_DEVICES_V, 0x358 */ + u32 rst_dev_w; /* _RST_DEVICES_W, 0x35c */ + u32 clk_out_enb_v; /* _CLK_OUT_ENB_V, 0x360 */ + u32 clk_out_enb_w; /* _CLK_OUT_ENB_W, 0x364 */ + u32 cclkg_brst_pol; /* _CCLKG_BURST_POLICY, 0x368 */ + u32 super_cclkg_div; /* _SUPER_CCLKG_DIVIDER, 0x36c */ + u32 cclklp_brst_pol; /* _CCLKLP_BURST_POLICY, 0x370 */ + u32 super_cclkp_div; /* _SUPER_CCLKLP_DIVIDER, 0x374 */ + u32 clk_cpug_cmplx; /* _CLK_CPUG_CMPLX, 0x378 */ + u32 clk_cpulp_cmplx; /* _CLK_CPULP_CMPLX, 0x37c */ + u32 cpu_softrst_ctrl; /* _CPU_SOFTRST_CTRL, 0x380 */ + u32 cpu_softrst_ctrl1; /* _CPU_SOFTRST_CTRL1, 0x384 */ + u32 cpu_softrst_ctrl2; /* _CPU_SOFTRST_CTRL2, 0x388 */ + u32 _rsv24[9]; /* 0x38c-3ac */ + u32 clk_src_g3d2; /* _CLK_SOURCE_G3D2, 0x3b0 */ + u32 clk_src_mselect; /* _CLK_SOURCE_MSELECT, 0x3b4 */ + u32 clk_src_tsensor; /* _CLK_SOURCE_TSENSOR, 0x3b8 */ + u32 clk_src_i2s3; /* _CLK_SOURCE_I2S3, 0x3bc */ + u32 clk_src_i2s4; /* _CLK_SOURCE_I2S4, 0x3c0 */ + u32 clk_src_i2c4; /* _CLK_SOURCE_I2C4, 0x3c4 */ + u32 clk_src_sbc5; /* _CLK_SOURCE_SBC5, 0x3c8 */ + u32 clk_src_sbc6; /* _CLK_SOURCE_SBC6, 0x3cc */ + u32 clk_src_audio; /* _CLK_SOURCE_AUDIO, 0x3d0 */ + u32 _rsv25; /* 0x3d4 */ + u32 clk_src_dam0; /* _CLK_SOURCE_DAM0, 0x3d8 */ + u32 clk_src_dam1; /* _CLK_SOURCE_DAM1, 0x3dc */ + u32 clk_src_dam2; /* _CLK_SOURCE_DAM2, 0x3e0 */ + u32 clk_src_hda2codec_2x; /* _CLK_SOURCE_HDA2CODEC_2X,0x3e4 */ + u32 clk_src_actmon; /* _CLK_SOURCE_ACTMON, 0x3e8 */ + u32 clk_src_extperiph1; /* _CLK_SOURCE_EXTPERIPH1, 0x3ec */ + u32 clk_src_extperiph2; /* _CLK_SOURCE_EXTPERIPH2, 0x3f0 */ + u32 clk_src_extperiph3; /* _CLK_SOURCE_EXTPERIPH3, 0x3f4 */ + u32 clk_src_nand_speed; /* _CLK_SOURCE_NAND_SPEED, 0x3f8 */ + u32 clk_src_i2c_slow; /* _CLK_SOURCE_I2C_SLOW, 0x3fc */ + u32 clk_src_sys; /* _CLK_SOURCE_SYS, 0x400 */ + u32 _rsv26[7]; /* 0x404-41c */ + u32 clk_src_sata_oob; /* _CLK_SOURCE_SATA_OOB, 0x420 */ + u32 clk_src_sata; /* _CLK_SOURCE_SATA, 0x424 */ + u32 clk_src_hda; /* _CLK_SOURCE_HDA, 0x428 */ + u32 _rsv27; /* 0x42c */ + u32 rst_dev_v_set; /* _RST_DEV_V_SET, 0x430 */ + u32 rst_dev_v_clr; /* _RST_DEV_V_CLR, 0x434 */ + u32 rst_dev_w_set; /* _RST_DEV_W_SET, 0x438 */ + u32 rst_dev_w_clr; /* _RST_DEV_W_CLR, 0x43c */ + u32 clk_enb_v_set; /* _CLK_ENB_V_SET, 0x440 */ + u32 clk_enb_v_clr; /* _CLK_ENB_V_CLR, 0x444 */ + u32 clk_enb_w_set; /* _CLK_ENB_W_SET, 0x448 */ + u32 clk_enb_w_clr; /* _CLK_ENB_W_CLR, 0x44c */ + u32 rst_cpug_cmplx_set; /* _RST_CPUG_CMPLX_SET, 0x450 */ + u32 rst_cpug_cmplx_clr; /* _RST_CPUG_CMPLX_CLR, 0x454 */ + u32 rst_cpulp_cmplx_set; /* _RST_CPULP_CMPLX_SET, 0x458 */ + u32 rst_cpulp_cmplx_clr; /* _RST_CPULP_CMPLX_CLR, 0x45C */ + u32 clk_cpug_cmplx_set; /* _CLK_CPUG_CMPLX_SET, 0x460 */ + u32 clk_cpug_cmplx_clr; /* _CLK_CPUG_CMPLX_CLR, 0x464 */ + u32 clk_cpulp_cmplx_set; /* _CLK_CPULP_CMPLX_SET, 0x468 */ + u32 clk_cpulp_cmplx_clr; /* _CLK_CPULP_CMPLX_CLR, 0x46c */ + u32 cpu_cmplx_status; /* _CPU_CMPLX_STATUS, 0x470 */ + u32 _rsv28; /* 0x474 */ + u32 intstatus; /* _INTSTATUS, 0x478 */ + u32 intmask; /* _INTMASK, 0x47c */ + u32 utmip_pll_cfg0; /* _UTMIP_PLL_CFG0, 0x480 */ + u32 utmip_pll_cfg1; /* _UTMIP_PLL_CFG1, 0x484 */ + u32 utmip_pll_cfg2; /* _UTMIP_PLL_CFG2, 0x488 */ + u32 plle_aux; /* _PLLE_AUX, 0x48c */ + u32 sata_pll_cfg0; /* _SATA_PLL_CFG0, 0x490 */ + u32 sata_pll_cfg1; /* _SATA_PLL_CFG1, 0x494 */ + u32 pcie_pll_cfg0; /* _PCIE_PLL_CFG0, 0x498 */ + u32 prog_audio_dly_clk; /* _PROG_AUDIO_DLY_CLK, 0x49c */ + u32 audio_sync_clk_i2s0; /* _AUDIO_SYNC_CLK_I2S0, 0x4a0 */ + u32 audio_sync_clk_i2s1; /* _AUDIO_SYNC_CLK_I2S1, 0x4a4 */ + u32 audio_sync_clk_i2s2; /* _AUDIO_SYNC_CLK_I2S2, 0x4a8 */ + u32 audio_sync_clk_i2s3; /* _AUDIO_SYNC_CLK_I2S3, 0x4ac */ + u32 audio_sync_clk_i2s4; /* _AUDIO_SYNC_CLK_I2S4, 0x4b0 */ + u32 audio_sync_clk_spdif; /* _AUDIO_SYNC_CLK_SPDIF, 0x4b4 */ + u32 plld2_base; /* _PLLD2_BASE, 0x4b8 */ + u32 plld2_misc; /* _PLLD2_MISC, 0x4bc */ + u32 utmip_pll_cfg3; /* _UTMIP_PLL_CFG3, 0x4c0 */ + u32 pllrefe_base; /* _PLLREFE_BASE, 0x4c4 */ + u32 pllrefe_misc; /* _PLLREFE_MISC, 0x4c8 */ + u32 _rsv29[7]; /* 0x4cc-4e4 */ + u32 pllc2_base; /* _PLLC2_BASE, 0x4e8 */ + u32 pllc2_misc0; /* _PLLC2_MISC_0, 0x4ec */ + u32 pllc2_misc1; /* _PLLC2_MISC_1, 0x4f0 */ + u32 pllc2_misc2; /* _PLLC2_MISC_2, 0x4f4 */ + u32 pllc2_misc3; /* _PLLC2_MISC_3, 0x4f8 */ + u32 pllc3_base; /* _PLLC3_BASE, 0x4fc */ + u32 pllc3_misc0; /* _PLLC3_MISC_0, 0x500 */ + u32 pllc3_misc1; /* _PLLC3_MISC_1, 0x504 */ + u32 pllc3_misc2; /* _PLLC3_MISC_2, 0x508 */ + u32 pllc3_misc3; /* _PLLC3_MISC_3, 0x50c */ + u32 pllx_misc1; /* _PLLX_MISC_1, 0x510 */ + u32 pllx_misc2; /* _PLLX_MISC_2, 0x514 */ + u32 pllx_misc3; /* _PLLX_MISC_3, 0x518 */ + u32 xusbio_pll_cfg0; /* _XUSBIO_PLL_CFG0, 0x51c */ + u32 xusbio_pll_cfg1; /* _XUSBIO_PLL_CFG1, 0x520 */ + u32 plle_aux1; /* _PLLE_AUX1, 0x524 */ + u32 pllp_reshift; /* _PLLP_RESHIFT, 0x528 */ + u32 utmipll_hw_pwrdn_cfg0; /* _UTMIPLL_HW_PWRDN_CFG0, 0x52c */ + u32 pllu_hw_pwrdn_cfg0; /* _PLLU_HW_PWRDN_CFG0, 0x530 */ + u32 xusb_pll_cfg0; /* _XUSB_PLL_CFG0, 0x534 */ + u32 _rsv30; /* 0x538 */ + u32 clk_cpu_misc; /* _CLK_CPU_MISC, 0x53c */ + u32 clk_cpug_misc; /* _CLK_CPUG_MISC, 0x540 */ + u32 clk_cpulp_misc; /* _CLK_CPULP_MISC, 0x544 */ + u32 pllx_hw_ctrl_cfg; /* _PLLX_HW_CTRL_CFG, 0x548 */ + u32 pllx_sw_ramp_cfg; /* _PLLX_SW_RAMP_CFG, 0x54c */ + u32 pllx_hw_ctrl_status; /* _PLLX_HW_CTRL_STATUS, 0x550 */ + u32 _rsv31; /* 0x554 */ + u32 super_gr3d_clk_div; /* _SUPER_GR3D_CLK_DIVIDER, 0x558 */ + u32 spare_reg0; /* _SPARE_REG0, 0x55c */ + u32 _rsv32[40]; /* 0x560-5fc */ + u32 clk_src_xusb_core_host; /* _CLK_SOURCE_XUSB_CORE_HOST 0x600 */ + u32 clk_src_xusb_falcon; /* _CLK_SOURCE_XUSB_FALCON 0x604 */ + u32 clk_src_xusb_fs; /* _CLK_SOURCE_XUSB_FS 0x608 */ + u32 clk_src_xusb_core_dev; /* _CLK_SOURCE_XUSB_CORE_DEV 0x60c */ + u32 clk_src_xusb_ss; /* _CLK_SOURCE_XUSB_SS 0x610 */ + u32 clk_src_cilab; /* _CLK_SOURCE_CILAB 0x614 */ + u32 clk_src_cilcd; /* _CLK_SOURCE_CILCD 0x618 */ + u32 clk_src_cile; /* _CLK_SOURCE_CILE 0x61c */ + u32 clk_src_dsia_lp; /* _CLK_SOURCE_DSIA_LP 0x620 */ + u32 clk_src_dsib_lp; /* _CLK_SOURCE_DSIB_LP 0x624 */ + u32 clk_src_entropy; /* _CLK_SOURCE_ENTROPY 0x628 */ + u32 clk_src_dvfs_ref; /* _CLK_SOURCE_DVFS_REF 0x62c */ + u32 clk_src_dvfs_soc; /* _CLK_SOURCE_DVFS_SOC 0x630 */ + u32 clk_src_traceclkin; /* _CLK_SOURCE_TRACECLKIN 0x634 */ + u32 clk_src_adx0; /* _CLK_SOURCE_ADX0 0x638 */ + u32 clk_src_amx0; /* _CLK_SOURCE_AMX0 0x63c */ + u32 clk_src_emc_latency; /* _CLK_SOURCE_EMC_LATENCY 0x640 */ + u32 clk_src_soc_therm; /* _CLK_SOURCE_SOC_THERM 0x644 */ }; #define TEGRA_DEV_L 0 @@ -254,31 +326,32 @@ struct clk_rst_ctlr { #define OSC_FREQ_OSC38P4 5 /* 38.4MHz */ #define OSC_FREQ_OSC48 9 /* 48.0MHz */ -/* CLK_RST_CONTROLLER_PLLx_BASE_0 */ -#define PLL_BYPASS_SHIFT 31 -#define PLL_BYPASS_MASK (1U << PLL_BYPASS_SHIFT) +/* CLK_RST_CONTROLLER_PLL*_BASE_0 */ +#define PLL_BASE_BYPASS (1U << 31) +#define PLL_BASE_ENABLE (1U << 30) +#define PLL_BASE_REF_DIS (1U << 29) +#define PLL_BASE_OVRRIDE (1U << 28) +#define PLL_BASE_LOCK (1U << 27) -#define PLL_ENABLE_SHIFT 30 -#define PLL_ENABLE_MASK (1U << PLL_ENABLE_SHIFT) +#define PLL_BASE_DIVP_SHIFT 20 +#define PLL_BASE_DIVP_MASK (7U << PLL_BASE_DIVP_SHIFT) -#define PLL_BASE_OVRRIDE_MASK (1U << 28) -#define PLL_BASE_LOCK_MASK (1U << 27) +#define PLL_BASE_DIVN_SHIFT 8 +#define PLL_BASE_DIVN_MASK (0x3ffU << PLL_BASE_DIVN_SHIFT) -#define PLL_DIVP_SHIFT 20 -#define PLL_DIVP_MASK (7U << PLL_DIVP_SHIFT) - -#define PLL_DIVN_SHIFT 8 -#define PLL_DIVN_MASK (0x3ffU << PLL_DIVN_SHIFT) - -#define PLL_DIVM_SHIFT 0 -#define PLL_DIVM_MASK (0x1f << PLL_DIVM_SHIFT) +#define PLL_BASE_DIVM_SHIFT 0 +#define PLL_BASE_DIVM_MASK (0x1f << PLL_BASE_DIVM_SHIFT) /* SPECIAL CASE: PLLM, PLLC and PLLX use different-sized fields here */ -#define PLLCMX_DIVP_MASK (0xfU << PLL_DIVP_SHIFT) -#define PLLCMX_DIVN_MASK (0xffU << PLL_DIVN_SHIFT) -#define PLLCMX_DIVM_MASK (0xffU << PLL_DIVM_SHIFT) +#define PLLCMX_BASE_DIVP_MASK (0xfU << PLL_BASE_DIVP_SHIFT) +#define PLLCMX_BASE_DIVN_MASK (0xffU << PLL_BASE_DIVN_SHIFT) +#define PLLCMX_BASE_DIVM_MASK (0xffU << PLL_BASE_DIVM_SHIFT) -/* CLK_RST_CONTROLLER_PLLx_OUTx_0 */ +/* Generic, indiscriminate divisor mask. May catch some innocent bystander bits + * on the side that we don't particularly care about. */ +#define PLL_BASE_DIV_MASK (0xffffff) + +/* CLK_RST_CONTROLLER_PLL*_OUT*_0 */ #define PLL_OUT_RSTN (1 << 0) #define PLL_OUT_CLKEN (1 << 1) #define PLL_OUT_OVRRIDE (1 << 2) @@ -293,21 +366,22 @@ struct clk_rst_ctlr { #define PLL_OUT2_RATIO_SHIFT 24 #define PLL_OUT2_RATIO_MASK (0xffU << PLL_OUT2_RATIO_SHIFT) -/* CLK_RST_CONTROLLER_PLLx_MISC_0 */ -#define PLL_DCCON_SHIFT 20 -#define PLL_DCCON_MASK (1U << PLL_DCCON_SHIFT) +/* CLK_RST_CONTROLLER_PLL*_MISC_0 */ +#define PLL_MISC_DCCON (1 << 20) -#define PLL_LOCK_ENABLE_SHIFT 18 -#define PLL_LOCK_ENABLE_MASK (1U << PLL_LOCK_ENABLE_SHIFT) +#define PLL_MISC_CPCON_SHIFT 8 +#define PLL_MISC_CPCON_MASK (0xfU << PLL_MISC_CPCON_SHIFT) -#define PLL_CPCON_SHIFT 8 -#define PLL_CPCON_MASK (15U << PLL_CPCON_SHIFT) +#define PLL_MISC_LFCON_SHIFT 4 +#define PLL_MISC_LFCON_MASK (0xfU << PLL_MISC_LFCON_SHIFT) -#define PLL_LFCON_SHIFT 4 -#define PLL_LFCON_MASK (15U << PLL_LFCON_SHIFT) +/* This bit is different all over the place. Oh joy... */ +#define PLLC_MISC_LOCK_ENABLE (1 << 24) +#define PLLUD_MISC_LOCK_ENABLE (1 << 22) +#define PLLPAXS_MISC_LOCK_ENABLE (1 << 18) +#define PLLE_MISC_LOCK_ENABLE (1 << 9) -#define PLLU_VCO_FREQ_SHIFT 20 -#define PLLU_VCO_FREQ_MASK (1U << PLLU_VCO_FREQ_SHIFT) +#define PLLU_MISC_VCO_FREQ (1 << 20) #define PLLP_OUT1_OVR (1 << 2) #define PLLP_OUT2_OVR (1 << 18) @@ -334,19 +408,6 @@ enum { IN_408_OUT_9_6_DIVISOR = 83, }; -/* CRC_PLLP_MISC_0 0xac */ -#define PLLP_MISC_PLLP_CPCON_8 (8 << 8) -#define PLLP_MISC_PLLP_LOCK_ENABLE (1 << 18) - -/* CRC_PLLU_BASE_0 0xc0 */ -#define PLLU_BYPASS_ENABLE (1 << 31) -#define PLLU_ENABLE_ENABLE (1 << 30) -#define PLLU_REF_DIS_REF_DISABLE (1 << 29) -#define PLLU_OVERRIDE_ENABLE (1 << 24) - -/* CRC_PLLU_MISC_0 0xcc */ -#define PLLU_LOCK_ENABLE_ENABLE (1 << 22) - /* PLLX_BASE_0 0xe0 */ #define PLLX_BASE_PLLX_ENABLE (1 << 30) @@ -371,17 +432,19 @@ enum { * get_periph_clock_source()) but it does not seem worth it since the code * already checks the ranges of values it is writing, in clk_get_divider(). */ -#define OUT_CLK_DIVISOR_SHIFT 0 -#define OUT_CLK_DIVISOR_MASK (0xffff << OUT_CLK_DIVISOR_SHIFT) +#define CLK_DIVISOR_SHIFT 0 +#define CLK_DIVISOR_MASK (0xffff << CLK_DIVISOR_SHIFT) -#define OUT_CLK_SOURCE_SHIFT 30 -#define OUT_CLK_SOURCE_MASK (3U << OUT_CLK_SOURCE_SHIFT) +#define CLK_SOURCE_SHIFT 30 +#define CLK_SOURCE_MASK (3U << CLK_SOURCE_SHIFT) -#define OUT_CLK_SOURCE3_SHIFT 29 -#define OUT_CLK_SOURCE3_MASK (7U << OUT_CLK_SOURCE3_SHIFT) +#define CLK_SOURCE3_SHIFT 29 +#define CLK_SOURCE3_MASK (7U << CLK_SOURCE3_SHIFT) -#define OUT_CLK_SOURCE4_SHIFT 28 -#define OUT_CLK_SOURCE4_MASK (15U << OUT_CLK_SOURCE4_SHIFT) +#define CLK_SOURCE4_SHIFT 28 +#define CLK_SOURCE4_MASK (15U << CLK_SOURCE4_SHIFT) + +#define CLK_UART_DIV_OVERRIDE (1 << 24) /* CLK_RST_CONTROLLER_SCLK_BURST_POLICY */ #define SCLK_SYS_STATE_SHIFT 28U @@ -449,33 +512,6 @@ enum { #define CLK_SYS_RATE_APB_RATE_SHIFT 0 #define CLK_SYS_RATE_APB_RATE_MASK (3 << CLK_SYS_RATE_AHB_RATE_SHIFT) -/* CLK_RST_CONTROLLER_RST_CPUxx_CMPLX_CLR 0x344 */ -#define CLR_CPURESET0 (1 << 0) -#define CLR_CPURESET1 (1 << 1) -#define CLR_CPURESET2 (1 << 2) -#define CLR_CPURESET3 (1 << 3) -#define CLR_DBGRESET0 (1 << 12) -#define CLR_DBGRESET1 (1 << 13) -#define CLR_DBGRESET2 (1 << 14) -#define CLR_DBGRESET3 (1 << 15) -#define CLR_CORERESET0 (1 << 16) -#define CLR_CORERESET1 (1 << 17) -#define CLR_CORERESET2 (1 << 18) -#define CLR_CORERESET3 (1 << 19) -#define CLR_CXRESET0 (1 << 20) -#define CLR_CXRESET1 (1 << 21) -#define CLR_CXRESET2 (1 << 22) -#define CLR_CXRESET3 (1 << 23) -#define CLR_L2RESET (1 << 24) -#define CLR_NONCPURESET (1 << 29) -#define CLR_PRESETDBG (1 << 30) - -/* CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR 0x34c */ -#define CLR_CPU3_CLK_STP (1 << 11) -#define CLR_CPU2_CLK_STP (1 << 10) -#define CLR_CPU1_CLK_STP (1 << 9) -#define CLR_CPU0_CLK_STP (1 << 8) - /* CRC_CLK_SOURCE_MSELECT_0 0x3b4 */ #define MSELECT_CLK_SRC_PLLP_OUT0 (0 << 29) @@ -494,4 +530,46 @@ enum { #define UTMIP_FORCE_PD_SAMP_B_POWERDOWN (1 << 2) #define UTMIP_FORCE_PD_SAMP_A_POWERDOWN (1 << 0) +// CCLK_BRST_POL +enum { + CRC_CCLK_BRST_POL_PLLX_OUT0 = 0x8, + CRC_CCLK_BRST_POL_CPU_STATE_RUN = 0x2 +}; + +// SUPER_CCLK_DIVIDER +enum { + CRC_SUPER_CCLK_DIVIDER_SUPER_CDIV_ENB = 1 << 31 +}; + +// CLK_CPU_CMPLX_CLR +enum { + CRC_CLK_CLR_CPU0_STP = 0x1 << 8, + CRC_CLK_CLR_CPU1_STP = 0x1 << 9, + CRC_CLK_CLR_CPU2_STP = 0x1 << 10, + CRC_CLK_CLR_CPU3_STP = 0x1 << 11 +}; + +// RST_CPUG_CMPLX_CLR +enum { + CRC_RST_CPUG_CLR_CPU0 = 0x1 << 0, + CRC_RST_CPUG_CLR_CPU1 = 0x1 << 1, + CRC_RST_CPUG_CLR_CPU2 = 0x1 << 2, + CRC_RST_CPUG_CLR_CPU3 = 0x1 << 3, + CRC_RST_CPUG_CLR_DBG0 = 0x1 << 12, + CRC_RST_CPUG_CLR_DBG1 = 0x1 << 13, + CRC_RST_CPUG_CLR_DBG2 = 0x1 << 14, + CRC_RST_CPUG_CLR_DBG3 = 0x1 << 15, + CRC_RST_CPUG_CLR_CORE0 = 0x1 << 16, + CRC_RST_CPUG_CLR_CORE1 = 0x1 << 17, + CRC_RST_CPUG_CLR_CORE2 = 0x1 << 18, + CRC_RST_CPUG_CLR_CORE3 = 0x1 << 19, + CRC_RST_CPUG_CLR_CX0 = 0x1 << 20, + CRC_RST_CPUG_CLR_CX1 = 0x1 << 21, + CRC_RST_CPUG_CLR_CX2 = 0x1 << 22, + CRC_RST_CPUG_CLR_CX3 = 0x1 << 23, + CRC_RST_CPUG_CLR_L2 = 0x1 << 24, + CRC_RST_CPUG_CLR_NONCPU = 0x1 << 29, + CRC_RST_CPUG_CLR_PDBG = 0x1 << 30, +}; + #endif /* _TEGRA124_CLK_RST_H_ */ diff --git a/src/soc/nvidia/tegra124/clock.c b/src/soc/nvidia/tegra124/clock.c index af01b56..9dce867 100644 --- a/src/soc/nvidia/tegra124/clock.c +++ b/src/soc/nvidia/tegra124/clock.c @@ -13,31 +13,368 @@ * You should have received a copy of the GNU General Public License * along with this program. If not, see <http://www.gnu.org/licenses/>. */ - +#include <console/console.h> #include <delay.h> #include <arch/io.h> #include <soc/addressmap.h> - +#include <soc/clock.h> #include "clk_rst.h" -#include "clock.h" +#include "cpug.h" +#include "flow.h" +#include "pmc.h" static struct clk_rst_ctlr *clk_rst = (void *)TEGRA_CLK_RST_BASE; -/* - * On poweron, AVP clock source (also called system clock) is set to PLLP_out0 - * with frequency set at 1MHz. Before initializing PLLP, we need to move the - * system clock's source to CLK_M temporarily. And then switch it to PLLP_out4 - * (204MHz) at a later time. +static struct flow_ctlr *flow = (void *)TEGRA_FLOW_BASE; +static struct tegra_pmc_regs *pmc = (void*)TEGRA_PMC_BASE; + +struct pll_dividers { + u32 n : 10; + u32 m : 8; + u32 p : 4; + u32 cpcon: 4; + u32 : 6; +}; + +/* Some PLLs have more restrictive divider bit lengths or are missing some + * fields. Make sure to use the right struct in the osc_table definition to get + * compile-time checking, but keep the bits aligned with struct pll_dividers so + * they can be used interchangeably at run time. Add new formats as required. */ +struct pllcx_dividers { + u32 n : 8; + u32 : 2; + u32 m : 8; + u32 p : 4; + u32 : 10; +}; +struct pllpad_dividers { + u32 n : 10; + u32 m : 5; + u32 : 3; + u32 p : 3; + u32 : 1; + u32 cpcon : 4; + u32 : 6; +}; +struct pllu_dividers { + u32 n : 10; + u32 m : 5; + u32 : 3; + u32 p : 1; + u32 : 3; + u32 cpcon : 4; + u32 : 6; +}; + +union __attribute__((transparent_union)) pll_fields { + u32 raw; + struct pll_dividers div; + struct pllcx_dividers cx; + struct pllpad_dividers pad; + struct pllu_dividers u; +}; + +/* This table defines the frequency dividers for every PLL to turn the external + * OSC clock into the frequencies defined by TEGRA_PLL*_KHZ in soc/clock.h. + * All PLLs have three dividers (N, M and P), with the governing formula for + * the output frequency being OUT = (IN / m) * N / (2^P). */ +struct { + int khz; + struct pllcx_dividers pllx; /* target: 1900 MHz */ + struct pllpad_dividers pllp; /* target: 408 MHz */ + struct pllcx_dividers pllc; /* target: 600 MHz */ + struct pllpad_dividers plld; /* target: 925 MHz */ + struct pllu_dividers pllu; /* target; 960 MHz */ +} static const osc_table[16] = { + [OSC_FREQ_OSC12]{ + .khz = 12000, + .pllx = {.n = 158, .m = 1, .p = 0}, /* 1896 MHz */ + .pllp = {.n = 34, .m = 1, .p = 0, .cpcon = 2}, + .pllc = {.n = 50, .m = 1, .p = 0}, + .plld = {.n = 925, .m = 12, .p = 0, .cpcon = 12}, + .pllu = {.n = 80, .m = 1, .p = 0, .cpcon = 3}, + }, + [OSC_FREQ_OSC13]{ + .khz = 13000, + .pllx = {.n = 146, .m = 1, .p = 0}, /* 1898 MHz */ + .pllp = {.n = 408, .m = 13, .p = 0, .cpcon = 8}, + .pllc = {.n = 231, .m = 5, .p = 0}, /* 600.6 MHz */ + .plld = {.n = 925, .m = 13, .p = 0, .cpcon = 12}, + .pllu = {.n = 960, .m = 13, .p = 0, .cpcon = 12}, + }, + [OSC_FREQ_OSC16P8]{ + .khz = 16800, + .pllx = {.n = 113, .m = 1, .p = 0}, /* 1898.4 MHz */ + .pllp = {.n = 170, .m = 7, .p = 0, .cpcon = 4}, + .pllc = {.n = 250, .m = 7, .p = 0}, + .plld = {.n = 936, .m = 17, .p = 0, .cpcon = 12},/* 924.9 MHz */ + .pllu = {.n = 400, .m = 7, .p = 0, .cpcon = 8}, + }, + [OSC_FREQ_OSC19P2]{ + .khz = 19200, + .pllx = {.n = 98, .m = 1, .p = 0}, /* 1881.6 MHz */ + .pllp = {.n = 85, .m = 4, .p = 0, .cpcon = 3}, + .pllc = {.n = 125, .m = 4, .p = 0}, + .plld = {.n = 819, .m = 17, .p = 0, .cpcon = 12},/* 924.9 MHz */ + .pllu = {.n = 50, .m = 1, .p = 0, .cpcon = 2}, + }, + [OSC_FREQ_OSC26]{ + .khz = 26000, + .pllx = {.n = 73, .m = 1, .p = 0}, /* 1898 MHz */ + .pllp = {.n = 204, .m = 13, .p = 0, .cpcon = 5}, + .pllc = {.n = 23, .m = 1, .p = 0}, /* 598 MHz */ + .plld = {.n = 925, .m = 26, .p = 0, .cpcon = 12}, + .pllu = {.n = 480, .m = 13, .p = 0, .cpcon = 8}, + }, + [OSC_FREQ_OSC38P4]{ + .khz = 38400, + .pllx = {.n = 98, .m = 1, .p = 0}, /* 1881.6 MHz */ + .pllp = {.n = 85, .m = 4, .p = 0, .cpcon = 3}, + .pllc = {.n = 125, .m = 4, .p = 0}, + .plld = {.n = 819, .m = 17, .p = 0, .cpcon = 12},/* 924.9 MHz */ + .pllu = {.n = 50, .m = 1, .p = 0, .cpcon = 2}, + }, + [OSC_FREQ_OSC48]{ + .khz = 48000, + .pllx = {.n = 158, .m = 1, .p = 0}, /* 1896 MHz */ + .pllp = {.n = 24, .m = 1, .p = 0, .cpcon = 2}, + .pllc = {.n = 50, .m = 1, .p = 0}, + .plld = {.n = 925, .m = 12, .p = 0, .cpcon = 12}, + .pllu = {.n = 80, .m = 1, .p = 0, .cpcon = 3}, + }, +}; + +void clock_ll_set_source_divisor(u32 *reg, u32 source, u32 divisor) +{ + u32 value; + + value = readl(reg); + + value &= ~CLK_SOURCE_MASK; + value |= source << CLK_SOURCE_SHIFT; + + value &= ~CLK_DIVISOR_MASK; + value |= divisor << CLK_DIVISOR_SHIFT; + + writel(value, reg); +} + +/* Get the oscillator frequency, from the corresponding hardware + * configuration field. This is actually a per-soc thing. Avoid the + * temptation to make it common. */ -void set_avp_clock_to_clkm(void) +static u32 clock_get_osc_bits(void) +{ + return readl(&clk_rst->osc_ctrl) >> OSC_CTRL_OSC_FREQ_SHIFT; +} + +int clock_get_osc_khz(void) +{ + return osc_table[clock_get_osc_bits()].khz; +} + +static void adjust_pllp_out_freqs(void) +{ + u32 reg; + /* Set T30 PLLP_OUT1, 2, 3 & 4 freqs to 9.6, 48, 102 & 204MHz */ + reg = readl(&clk_rst->pllp_outa); // OUTA contains OUT2 / OUT1 + reg |= (IN_408_OUT_48_DIVISOR << PLLP_OUT2_RATIO) | PLLP_OUT2_OVR + | (IN_408_OUT_9_6_DIVISOR << PLLP_OUT1_RATIO) | PLLP_OUT1_OVR; + writel(reg, &clk_rst->pllp_outa); + + reg = readl(&clk_rst->pllp_outb); // OUTB, contains OUT4 / OUT3 + reg |= (IN_408_OUT_204_DIVISOR << PLLP_OUT4_RATIO) | PLLP_OUT4_OVR + | (IN_408_OUT_102_DIVISOR << PLLP_OUT3_RATIO) | PLLP_OUT3_OVR; + writel(reg, &clk_rst->pllp_outb); +} + +static void init_pll(u32 *base, u32 *misc, const union pll_fields pll) +{ + u32 dividers = pll.div.n << PLL_BASE_DIVN_SHIFT | + pll.div.m << PLL_BASE_DIVM_SHIFT | + pll.div.p << PLL_BASE_DIVP_SHIFT; + + /* Write dividers but BYPASS the PLL while we're messing with it. */ + writel(dividers | PLL_BASE_BYPASS, base); + + /* Set CPCON field (defaults to 0 if it doesn't exist for this PLL) */ + writel(pll.div.cpcon << PLL_MISC_CPCON_SHIFT, misc); + + /* enable PLL and take it back out of BYPASS (we don't wait for lock + * because we assume that to be done by the time we start using it). */ + writel(dividers | PLL_BASE_ENABLE, base); +} + +/* Initialize the UART and put it on CLK_M so we can use it during clock_init(). + * Will later move it to PLLP in clock_config(). The divisor must be very small + * to accomodate 12KHz OSCs, so we override the 16.0 UART divider with the 15.1 + * CLK_SOURCE divider to get more precision. (This might still not be enough for + * some OSCs... if you use 13KHz, be prepared to have a bad time.) The 1800 has + * been determined through trial and error (must lead to div 13 at 24MHz). */ +void clock_early_uart(void) +{ + clock_ll_set_source_divisor(&clk_rst->clk_src_uarta, 3, + CLK_UART_DIV_OVERRIDE | CLK_DIVIDER(clock_get_osc_khz(), 1800)); + setbits_le32(&clk_rst->clk_out_enb_l, CLK_L_UARTA); + udelay(2); + clrbits_le32(&clk_rst->rst_dev_l, CLK_L_UARTA); +} + +void clock_cpu0_config_and_reset(void *entry) +{ + void * const evp_cpu_reset = (uint8_t *)TEGRA_EVP_BASE + 0x100; + + write32(CONFIG_STACK_TOP, &cpug_stack_pointer); + write32((uintptr_t)entry, &cpug_entry_point); + write32((uintptr_t)&cpug_setup, evp_cpu_reset); + + // Set up cclk_brst and divider. + write32((CRC_CCLK_BRST_POL_PLLX_OUT0 << 0) | + (CRC_CCLK_BRST_POL_PLLX_OUT0 << 4) | + (CRC_CCLK_BRST_POL_PLLX_OUT0 << 8) | + (CRC_CCLK_BRST_POL_PLLX_OUT0 << 12) | + (CRC_CCLK_BRST_POL_CPU_STATE_RUN << 28), + &clk_rst->cclk_brst_pol); + write32(CRC_SUPER_CCLK_DIVIDER_SUPER_CDIV_ENB, + &clk_rst->super_cclk_div); + + // Enable the clocks for CPUs 0-3. + uint32_t cpu_cmplx_clr = read32(&clk_rst->clk_cpu_cmplx_clr); + cpu_cmplx_clr |= CRC_CLK_CLR_CPU0_STP | CRC_CLK_CLR_CPU1_STP | + CRC_CLK_CLR_CPU2_STP | CRC_CLK_CLR_CPU3_STP; + write32(cpu_cmplx_clr, &clk_rst->clk_cpu_cmplx_clr); + + // Enable other CPU related clocks. + setbits_le32(&clk_rst->clk_out_enb_l, CLK_L_CPU); + setbits_le32(&clk_rst->clk_out_enb_v, CLK_V_CPUG); + + // Disable the reset on the non-CPU parts of the fast cluster. + write32(CRC_RST_CPUG_CLR_NONCPU, + &clk_rst->rst_cpug_cmplx_clr); + // Disable the various resets on the CPUs. + write32(CRC_RST_CPUG_CLR_CPU0 | CRC_RST_CPUG_CLR_CPU1 | + CRC_RST_CPUG_CLR_CPU2 | CRC_RST_CPUG_CLR_CPU3 | + CRC_RST_CPUG_CLR_DBG0 | CRC_RST_CPUG_CLR_DBG1 | + CRC_RST_CPUG_CLR_DBG2 | CRC_RST_CPUG_CLR_DBG3 | + CRC_RST_CPUG_CLR_CORE0 | CRC_RST_CPUG_CLR_CORE1 | + CRC_RST_CPUG_CLR_CORE2 | CRC_RST_CPUG_CLR_CORE3 | + CRC_RST_CPUG_CLR_CX0 | CRC_RST_CPUG_CLR_CX1 | + CRC_RST_CPUG_CLR_CX2 | CRC_RST_CPUG_CLR_CX3 | + CRC_RST_CPUG_CLR_L2 | CRC_RST_CPUG_CLR_PDBG, + &clk_rst->rst_cpug_cmplx_clr); +} + +/** + * The T124 requires some special clock initialization, including setting up + * the DVC I2C, turning on MSELECT and selecting the G CPU cluster + */ +void clock_init(void) { u32 val; + u32 osc = clock_get_osc_bits(); + /* + * On poweron, AVP clock source (also called system clock) is set to + * PLLP_out0 with frequency set at 1MHz. Before initializing PLLP, we + * need to move the system clock's source to CLK_M temporarily. And + * then switch it to PLLP_out4 (204MHz) at a later time. + */ val = (SCLK_SOURCE_CLKM << SCLK_SWAKEUP_FIQ_SOURCE_SHIFT) | (SCLK_SOURCE_CLKM << SCLK_SWAKEUP_IRQ_SOURCE_SHIFT) | (SCLK_SOURCE_CLKM << SCLK_SWAKEUP_RUN_SOURCE_SHIFT) | (SCLK_SOURCE_CLKM << SCLK_SWAKEUP_IDLE_SOURCE_SHIFT) | (SCLK_SYS_STATE_RUN << SCLK_SYS_STATE_SHIFT); - writel(val, &clk_rst->crc_sclk_brst_pol); - /* Wait 2-3us for the clock to flush thru the logic as per the TRM */ - udelay(3); + writel(val, &clk_rst->sclk_brst_pol); + udelay(2); + + /* Set active CPU cluster to G */ + clrbits_le32(&flow->cluster_control, 1); + + /* Change the oscillator drive strength */ + val = readl(&clk_rst->osc_ctrl); + val &= ~OSC_XOFS_MASK; + val |= (OSC_DRIVE_STRENGTH << OSC_XOFS_SHIFT); + writel(val, &clk_rst->osc_ctrl); + + /* Ambiguous quote from u-boot. TODO: what's this mean? + * "should update same value in PMC_OSC_EDPD_OVER XOFS + field for warmboot "*/ + val = readl(&pmc->osc_edpd_over); + val &= ~PMC_OSC_EDPD_OVER_XOFS_MASK; + val |= (OSC_DRIVE_STRENGTH << PMC_OSC_EDPD_OVER_XOFS_SHIFT); + writel(val, &pmc->osc_edpd_over); + + /* Disable IDDQ for PLLX before we set it up (from U-Boot -- why?) */ + val = readl(&clk_rst->pllx_misc3); + val &= ~PLLX_IDDQ_MASK; + writel(val, &clk_rst->pllx_misc3); + udelay(2); + + /* Set PLLC dynramp_step A to 0x2b and B to 0xb (from U-Boot -- why? */ + writel(0x2b << 17 | 0xb << 9, &clk_rst->pllc_misc2); + + adjust_pllp_out_freqs(); + + init_pll(&clk_rst->pllx_base, &clk_rst->pllx_misc, osc_table[osc].pllx); + init_pll(&clk_rst->pllp_base, &clk_rst->pllp_misc, osc_table[osc].pllp); + init_pll(&clk_rst->pllc_base, &clk_rst->pllc_misc, osc_table[osc].pllc); + init_pll(&clk_rst->plld_base, &clk_rst->plld_misc, osc_table[osc].plld); + init_pll(&clk_rst->pllu_base, &clk_rst->pllu_misc, osc_table[osc].pllu); + + val = (1 << CLK_SYS_RATE_AHB_RATE_SHIFT); + writel(val, &clk_rst->clk_sys_rate); +} + +void clock_config(void) +{ + /* Enable clocks for the required peripherals. */ + /* TODO: can (should?) we use the _SET and _CLR registers here? */ + setbits_le32(&clk_rst->clk_out_enb_l, + CLK_L_CACHE2 | CLK_L_GPIO | CLK_L_TMR | CLK_L_I2C1 | + CLK_L_SDMMC4); + setbits_le32(&clk_rst->clk_out_enb_h, + CLK_H_EMC | CLK_H_I2C2 | CLK_H_I2C5 | CLK_H_SBC1 | + CLK_H_PMC | CLK_H_APBDMA | CLK_H_MEM); + setbits_le32(&clk_rst->clk_out_enb_u, + CLK_U_I2C3 | CLK_U_CSITE | CLK_U_SDMMC3); + setbits_le32(&clk_rst->clk_out_enb_v, CLK_V_MSELECT); + setbits_le32(&clk_rst->clk_out_enb_w, CLK_W_DVFS); + + /* + * Set MSELECT clock source as PLLP (00)_REG, and ask for a clock + * divider that would set the MSELECT clock at 102MHz for a + * PLLP base of 408MHz. + */ + clock_ll_set_source_divisor(&clk_rst->clk_src_mselect, 0, + CLK_DIVIDER(TEGRA_PLLP_KHZ, 102000)); + + /* Give clock time to stabilize */ + udelay(IO_STABILIZATION_DELAY); + + /* I2C1 gets CLK_M and a divisor of 17 */ + clock_ll_set_source_divisor(&clk_rst->clk_src_i2c1, 3, 16); + /* I2C2 gets CLK_M and a divisor of 17 */ + clock_ll_set_source_divisor(&clk_rst->clk_src_i2c2, 3, 16); + /* I2C3 (cam) gets CLK_M and a divisor of 17 */ + clock_ll_set_source_divisor(&clk_rst->clk_src_i2c3, 3, 16); + /* I2C5 (PMU) gets CLK_M and a divisor of 17 */ + clock_ll_set_source_divisor(&clk_rst->clk_src_i2c5, 3, 16); + + /* UARTA gets PLLP, deactivate CLK_UART_DIV_OVERRIDE */ + writel(0 << CLK_SOURCE_SHIFT, &clk_rst->clk_src_uarta); + + /* Give clock time to stabilize. */ + udelay(IO_STABILIZATION_DELAY); + + /* Take required peripherals out of reset. */ + + clrbits_le32(&clk_rst->rst_dev_l, + CLK_L_CACHE2 | CLK_L_GPIO | CLK_L_TMR | CLK_L_I2C1 | + CLK_L_SDMMC4); + clrbits_le32(&clk_rst->rst_dev_h, + CLK_H_EMC | CLK_H_I2C2 | CLK_H_I2C5 | CLK_H_SBC1 | + CLK_H_PMC | CLK_H_APBDMA | CLK_H_MEM); + clrbits_le32(&clk_rst->rst_dev_u, + CLK_U_I2C3 | CLK_U_CSITE | CLK_U_SDMMC3); + clrbits_le32(&clk_rst->rst_dev_v, CLK_V_MSELECT); + clrbits_le32(&clk_rst->rst_dev_w, CLK_W_DVFS); } diff --git a/src/soc/nvidia/tegra124/clock.h b/src/soc/nvidia/tegra124/clock.h deleted file mode 100644 index 688505a..0000000 --- a/src/soc/nvidia/tegra124/clock.h +++ /dev/null @@ -1,22 +0,0 @@ -/* - * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License - * along with this program. If not, see <http://www.gnu.org/licenses/>. - */ - -#ifndef __SOC_NVIDIA_TEGRA124_CLOCK_H__ -#define __SOC_NVIDIA_TEGRA124_CLOCK_H__ - -void set_avp_clock_to_clkm(void); - -#endif /* __SOC_NVIDIA_TEGRA124_CLOCK_H__ */ diff --git a/src/soc/nvidia/tegra124/cpug.S b/src/soc/nvidia/tegra124/cpug.S new file mode 100644 index 0000000..7f761e8 --- /dev/null +++ b/src/soc/nvidia/tegra124/cpug.S @@ -0,0 +1,56 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2013 Google Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + + .align 6 + .arm + + .global cpug_stack_pointer +cpug_stack_pointer: + .word 0 + + .global cpug_entry_point +cpug_entry_point: + .word 0 + + .global cpug_setup + .type cpug_setup, function + cpug_setup: + + /* + * Set the cpu to System mode with IRQ and FIQ disabled. Prefetch/Data + * aborts may happen early and crash before the abort handlers are + * installed, but at least the problem will show up near the code that + * causes it. + */ + msr cpsr_cxf, #0xdf + + ldr sp, cpug_stack_pointer + eor lr, lr + ldr r0, cpug_entry_point + bx r0 diff --git a/src/soc/nvidia/tegra124/cpug.h b/src/soc/nvidia/tegra124/cpug.h new file mode 100644 index 0000000..842843a --- /dev/null +++ b/src/soc/nvidia/tegra124/cpug.h @@ -0,0 +1,29 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef __SOC_NVIDIA_TEGRA124_CPUG_H__ +#define __SOC_NVIDIA_TEGRA124_CPUG_H__ + +#include <stdint.h> + +extern u32 cpug_stack_pointer; +extern u32 cpug_entry_point; +void cpug_setup(void); + +#endif /* __SOC_NVIDIA_TEGRA124_CPUG_H__ */ diff --git a/src/soc/nvidia/tegra124/display.c b/src/soc/nvidia/tegra124/display.c new file mode 100644 index 0000000..b7d3d7f --- /dev/null +++ b/src/soc/nvidia/tegra124/display.c @@ -0,0 +1,304 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <arch/io.h> +#include <stdint.h> +#include <lib.h> +#include <stdlib.h> +#include <delay.h> +#include <soc/addressmap.h> +#include <device/device.h> +#include <stdlib.h> +#include <string.h> +#include <cpu/cpu.h> +#include <boot/tables.h> +#include <cbmem.h> +#include <soc/clock.h> +#include <soc/nvidia/tegra/dc.h> +#include "clk_rst.h" +#include "chip.h" +#include <soc/display.h> + +static struct clk_rst_ctlr *clk_rst = (void *)TEGRA_CLK_RST_BASE; + +static const u32 rgb_enb_tab[PIN_REG_COUNT] = { + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, +}; + +static const u32 rgb_polarity_tab[PIN_REG_COUNT] = { + 0x00000000, + 0x01000000, + 0x00000000, + 0x00000000, +}; + +static const u32 rgb_data_tab[PIN_REG_COUNT] = { + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, +}; + +static const u32 rgb_sel_tab[PIN_OUTPUT_SEL_COUNT] = { + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00210222, + 0x00002200, + 0x00020000, +}; + +static int update_display_mode(struct dc_disp_reg *disp, + struct soc_nvidia_tegra124_config *config) +{ + u32 val; + u32 rate; + u32 div; + + writel(0x0, &disp->disp_timing_opt); + + writel(config->vref_to_sync << 16 | config->href_to_sync, + &disp->ref_to_sync); + writel(config->vsync_width << 16 | config->hsync_width, &disp->sync_width); + writel(config->vback_porch << 16 | config->hback_porch, &disp->back_porch); + writel(config->vfront_porch << 16 | config->hfront_porch, + &disp->front_porch); + + writel(config->xres | (config->yres << 16), &disp->disp_active); + + val = DE_SELECT_ACTIVE << DE_SELECT_SHIFT; + val |= DE_CONTROL_NORMAL << DE_CONTROL_SHIFT; + writel(val, &disp->data_enable_opt); + + val = DATA_FORMAT_DF1P1C << DATA_FORMAT_SHIFT; + val |= DATA_ALIGNMENT_MSB << DATA_ALIGNMENT_SHIFT; + val |= DATA_ORDER_RED_BLUE << DATA_ORDER_SHIFT; + writel(val, &disp->disp_interface_ctrl); + + /* + * The pixel clock divider is in 7.1 format (where the bottom bit + * represents 0.5). Here we calculate the divider needed to get from + * the display clock (typically 600MHz) to the pixel clock. We round + * up or down as requried. + * We use pllp for now. + */ + rate = 600 * 1000000; + div = ((rate * 2 + config->pixel_clock / 2) / config->pixel_clock) - 2; + printk(BIOS_SPEW, "Display clock %d, divider %d\n", rate, div); + + writel(0x00010001, &disp->shift_clk_opt); + + val = PIXEL_CLK_DIVIDER_PCD1 << PIXEL_CLK_DIVIDER_SHIFT; + val |= div << SHIFT_CLK_DIVIDER_SHIFT; + writel(val, &disp->disp_clk_ctrl); + + return 0; +} + +static int setup_window(struct disp_ctl_win *win, + struct soc_nvidia_tegra124_config *config) +{ + int log2_bpp = log2(config->framebuffer_bits_per_pixel); + win->x = 0; + win->y = 0; + win->w = config->xres; + win->h = config->yres; + win->out_x = 0; + win->out_y = 0; + win->out_w = config->xres; + win->out_h = config->yres; + win->phys_addr = config->framebuffer_base; + win->stride = config->xres * (1 << log2_bpp) / 8; + printk(BIOS_SPEW, "%s: depth = %d\n", __func__, log2_bpp); + switch (log2_bpp) { + case 5: + case 24: + win->fmt = COLOR_DEPTH_R8G8B8A8; + win->bpp = 32; + break; + case 4: + win->fmt = COLOR_DEPTH_B5G6R5; + win->bpp = 16; + break; + + default: + printk(BIOS_SPEW, "Unsupported LCD bit depth"); + return -1; + } + + return 0; +} + +static void update_window(struct display_controller *dc, + struct disp_ctl_win *win, + struct soc_nvidia_tegra124_config *config) +{ + u32 h_dda, v_dda; + u32 val; + + val = readl(&dc->cmd.disp_win_header); + val |= WINDOW_A_SELECT; + writel(val, &dc->cmd.disp_win_header); + + writel(win->fmt, &dc->win.color_depth); + + clrsetbits_le32(&dc->win.byte_swap, BYTE_SWAP_MASK, + BYTE_SWAP_NOSWAP << BYTE_SWAP_SHIFT); + + val = win->out_x << H_POSITION_SHIFT; + val |= win->out_y << V_POSITION_SHIFT; + writel(val, &dc->win.pos); + + val = win->out_w << H_SIZE_SHIFT; + val |= win->out_h << V_SIZE_SHIFT; + writel(val, &dc->win.size); + + val = (win->w * win->bpp / 8) << H_PRESCALED_SIZE_SHIFT; + val |= win->h << V_PRESCALED_SIZE_SHIFT; + writel(val, &dc->win.prescaled_size); + + writel(0, &dc->win.h_initial_dda); + writel(0, &dc->win.v_initial_dda); + + h_dda = (win->w * 0x1000) / MAX(win->out_w - 1, 1); + v_dda = (win->h * 0x1000) / MAX(win->out_h - 1, 1); + + val = h_dda << H_DDA_INC_SHIFT; + val |= v_dda << V_DDA_INC_SHIFT; + writel(val, &dc->win.dda_increment); + + writel(win->stride, &dc->win.line_stride); + writel(0, &dc->win.buf_stride); + + val = WIN_ENABLE; + if (win->bpp < 24) + val |= COLOR_EXPAND; + writel(val, &dc->win.win_opt); + + writel((u32) win->phys_addr, &dc->winbuf.start_addr); + writel(win->x, &dc->winbuf.addr_h_offset); + writel(win->y, &dc->winbuf.addr_v_offset); + + writel(0xff00, &dc->win.blend_nokey); + writel(0xff00, &dc->win.blend_1win); + + val = GENERAL_ACT_REQ | WIN_A_ACT_REQ; + val |= GENERAL_UPDATE | WIN_A_UPDATE; + writel(val, &dc->cmd.state_ctrl); +} + +/* this is really aimed at the lcd panel. That said, there are two display + * devices on this part and we may someday want to extend it for other boards. + */ +void display_startup(device_t dev) +{ + u32 val; + int i; + struct soc_nvidia_tegra124_config *config = dev->chip_info; + struct display_controller *dc = (void *)config->display_controller; + struct disp_ctl_win window; + + /* should probably just make it all MiB ... in future */ + u32 framebuffer_size_mb = config->framebuffer_size / MiB; + u32 framebuffer_base_mb= config->framebuffer_base / MiB; + + printk(BIOS_SPEW, + "%s: xres %d yres %d framebuffer_bits_per_pixel %d\n", + __func__, + config->xres, config->yres, config->framebuffer_bits_per_pixel); + if (framebuffer_size_mb == 0){ + framebuffer_size_mb = ALIGN_UP(config->xres * config->yres * + (config->framebuffer_bits_per_pixel / 8), MiB)/MiB; + } + + if (! framebuffer_base_mb) + framebuffer_base_mb = FB_BASE_MB; + + mmu_config_range(framebuffer_base_mb, framebuffer_size_mb, + config->cache_policy); + + /* Enable flushing after LCD writes if requested */ + /* I don't understand this part yet. + lcd_set_flush_dcache(config.cache_type & FDT_LCD_CACHE_FLUSH); + */ + printk(BIOS_SPEW, "LCD frame buffer at %dMiB to %dMiB\n", framebuffer_base_mb, + framebuffer_base_mb + framebuffer_size_mb); + + /* GPIO magic here if needed to start powering up things. You + * really only want to enable vdd, wait a bit, and then enable + * the panel. However ... the timings in the tegra20 dts make + * no sense to me. I'm pretty sure they're wrong. + * The panel_vdd is done in the romstage, so we need only + * light things up here once we're sure it's all working. + */ + setbits_le32(&clk_rst->rst_dev_l, CLK_L_DISP1 | CLK_L_HOST1X); + + clock_ll_set_source_divisor(&clk_rst->clk_src_host1x, 4, + CLK_DIVIDER(TEGRA_PLLP_KHZ, 144000)); + /* u-boot uses PLLC for DISP1. + * But the u-boot code does not work and we don't set up PLLC anyway. + * PLLP seems quite good enough, so run with that for now. */ + clock_ll_set_source_divisor(&clk_rst->clk_src_disp1, 0 /* 4 */, + CLK_DIVIDER(TEGRA_PLLP_KHZ, 600000)); + + udelay(2); + + clrbits_le32(&clk_rst->rst_dev_l, CLK_L_DISP1|CLK_L_HOST1X); + + writel(0x00000100, &dc->cmd.gen_incr_syncpt_ctrl); + writel(0x0000011a, &dc->cmd.cont_syncpt_vsync); + writel(0x00000000, &dc->cmd.int_type); + writel(0x00000000, &dc->cmd.int_polarity); + writel(0x00000000, &dc->cmd.int_mask); + writel(0x00000000, &dc->cmd.int_enb); + + val = PW0_ENABLE | PW1_ENABLE | PW2_ENABLE; + val |= PW3_ENABLE | PW4_ENABLE | PM0_ENABLE; + val |= PM1_ENABLE; + writel(val, &dc->cmd.disp_pow_ctrl); + + val = readl(&dc->cmd.disp_cmd); + val |= CTRL_MODE_C_DISPLAY << CTRL_MODE_SHIFT; + writel(val, &dc->cmd.disp_cmd); + + writel(0x00000020, &dc->disp.mem_high_pri); + writel(0x00000001, &dc->disp.mem_high_pri_timer); + + for (i = 0; i < PIN_REG_COUNT; i++) { + writel(rgb_enb_tab[i], &dc->com.pin_output_enb[i]); + writel(rgb_polarity_tab[i], &dc->com.pin_output_polarity[i]); + writel(rgb_data_tab[i], &dc->com.pin_output_data[i]); + } + + for (i = 0; i < PIN_OUTPUT_SEL_COUNT; i++) + writel(rgb_sel_tab[i], &dc->com.pin_output_sel[i]); + + if (config->pixel_clock) + update_display_mode(&dc->disp, config); + + if (!setup_window(&window, config)) + update_window(dc, &window, config); + +} + diff --git a/src/soc/nvidia/tegra124/dma.c b/src/soc/nvidia/tegra124/dma.c new file mode 100644 index 0000000..964bb7b --- /dev/null +++ b/src/soc/nvidia/tegra124/dma.c @@ -0,0 +1,236 @@ +/* + * (C) Copyright 2010,2011 + * NVIDIA Corporation <www.nvidia.com> + * Copyright 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#include <inttypes.h> +#include <stddef.h> +#include <stdlib.h> +#include <console/console.h> + +#include <arch/io.h> +#include <soc/addressmap.h> + +#include "dma.h" + +/* + * Note: Many APB DMA controller registers are laid out such that each + * bit controls or represents the status for the corresponding channel. + * So we will not bother to list each individual bit in this case. + */ +#define APBDMA_COMMAND_GEN (1 << 31) + +#define APBDMA_CNTRL_REG_COUNT_VALUE_MASK 0xffff +#define APBDMA_CNTRL_REG_COUNT_VALUE_SHIFT 0 + +struct apb_dma { + u32 command; /* 0x00 */ + u32 status; /* 0x04 */ + u32 rsvd1[2]; + u32 cntrl_reg; /* 0x10 */ + u32 irq_sta_cpu; /* 0x14 */ + u32 irq_sta_cop; /* 0x18 */ + u32 irq_mask; /* 0x1c */ + u32 irq_mask_set; /* 0x20 */ + u32 irq_mask_clr; /* 0x24 */ + u32 trig_reg; /* 0x28 */ + u32 channel_trig_reg; /* 0x2c */ + u32 dma_status; /* 0x30 */ + u32 channel_en_reg; /* 0x34 */ + u32 security_reg; /* 0x38 */ + u32 channel_swid; /* 0x3c */ + u32 rsvd[1]; + u32 chan_wt_reg0; /* 0x44 */ + u32 chan_wt_reg1; /* 0x48 */ + u32 chan_wt_reg2; /* 0x4c */ + u32 chan_wr_reg3; /* 0x50 */ + u32 channel_swid1; /* 0x54 */ +} __attribute__((packed)); +struct apb_dma * const apb_dma = (struct apb_dma *)TEGRA_APB_DMA_BASE; + +/* + * Naming in the doc included a superfluous _CHANNEL_n_ for + * each entry and was left out for the sake of conciseness. + */ +#define APBDMACHAN_CSR_ENB (1 << 31) +#define APBDMACHAN_CSR_IE_EOC (1 << 30) +#define APBDMACHAN_CSR_HOLD (1 << 29) +#define APBDMACHAN_CSR_DIR (1 << 28) +#define APBDMACHAN_CSR_ONCE (1 << 27) +#define APBDMACHAN_CSR_FLOW (1 << 21) +#define APBDMACHAN_CSR_REQ_SEL_MASK 0x1f +#define APBDMACHAN_CSR_REQ_SEL_SHIFT 16 + +#define APBDMACHAN_STA_BSY (1 << 31) +#define APBDMACHAN_STA_ISE_EOC (1 << 30) +#define APBDMACHAN_STA_HALT (1 << 29) +#define APBDMACHAN_STA_PING_PONG_STA (1 << 28) +#define APBDMACHAN_STA_DMA_ACTIVITY (1 << 27) +#define APBDMACHAN_STA_CHANNEL_PAUSE (1 << 26) + +#define APBDMACHAN_CSRE_CHANNEL_PAUSE (1 << 31) +#define APBDMACHAN_CSRE_TRIG_SEL_MASK 0x3f +#define APBDMACHAN_CSRE_TRIG_SEL_SHIFT 14 + +#define APBDMACHAN_AHB_PTR_MASK (0x3fffffff) +#define APBDMACHAN_AHB_PTR_SHIFT 2 + +#define APBDMACHAN_AHB_SEQ_INTR_ENB (1 << 31) +#define APBDMACHAN_AHB_SEQ_AHB_BUS_WIDTH_MASK 0x7 +#define APBDMACHAN_AHB_SEQ_AHB_BUS_WIDTH_SHIFT 28 +#define APBDMACHAN_AHB_SEQ_AHB_DATA_SWAP (1 << 27) +#define APBDMACHAN_AHB_SEQ_AHB_BURST_MASK 0x7 +#define APBDMACHAN_AHB_SEQ_AHB_BURST_SHIFT 24 +#define APBDMACHAN_AHB_SEQ_DBL_BUF (1 << 19) +#define APBDMACHAN_AHB_SEQ_WRAP_MASK 0x7 +#define APBDMACHAN_AHB_SEQ_WRAP_SHIFT 16 + +#define APBDMACHAN_AHB_SEQ_AHB_BUS_WIDTH_MASK 0x7 +#define APBDMACHAN_AHB_SEQ_AHB_BUS_WIDTH_SHIFT 28 + +#define APBDMACHAN_APB_PTR_MASK 0x3fffffff +#define APBDMACHAN_APB_PTR_SHIFT 2 + +#define APBDMACHAN_APB_SEQ_APB_BUS_WIDTH_MASK 0x7 +#define APBDMACHAN_APB_SEQ_APB_BUS_WIDTH_SHIFT 28 +#define APBDMACHAN_APB_SEQ_APB_DATA_SWAP (1 << 27) +#define APBDMACHAN_APB_SEQ_APB_ADDR_WRAP_MASK 0x7 +#define APBDMACHAN_APB_SEQ_APB_ADDR_WRAP_SHIFT 16 + +#define APBDMACHAN_WORD_TRANSFER_ + +#define APBDMACHAN_WORD_TRANSFER_MASK 0x0fffffff +#define APBDMACHAN_WORD_TRANSFER_SHIFT 2 + +#define APB_DMA_OFFSET(n) \ + (struct apb_dma_channel_regs *)(TEGRA_APB_DMA_BASE + n) +struct apb_dma_channel apb_dma_channels[] = { + { .num = 0, .regs = APB_DMA_OFFSET(0x1000) }, + { .num = 1, .regs = APB_DMA_OFFSET(0x1040) }, + { .num = 2, .regs = APB_DMA_OFFSET(0x1080) }, + { .num = 3, .regs = APB_DMA_OFFSET(0x10c0) }, + { .num = 4, .regs = APB_DMA_OFFSET(0x1100) }, + { .num = 5, .regs = APB_DMA_OFFSET(0x1140) }, + { .num = 6, .regs = APB_DMA_OFFSET(0x1180) }, + { .num = 7, .regs = APB_DMA_OFFSET(0x11c0) }, + { .num = 8, .regs = APB_DMA_OFFSET(0x1200) }, + { .num = 9, .regs = APB_DMA_OFFSET(0x1240) }, + { .num = 10, .regs = APB_DMA_OFFSET(0x1280) }, + { .num = 11, .regs = APB_DMA_OFFSET(0x12c0) }, + { .num = 12, .regs = APB_DMA_OFFSET(0x1300) }, + { .num = 13, .regs = APB_DMA_OFFSET(0x1340) }, + { .num = 14, .regs = APB_DMA_OFFSET(0x1380) }, + { .num = 15, .regs = APB_DMA_OFFSET(0x13c0) }, + { .num = 16, .regs = APB_DMA_OFFSET(0x1400) }, + { .num = 17, .regs = APB_DMA_OFFSET(0x1440) }, + { .num = 18, .regs = APB_DMA_OFFSET(0x1480) }, + { .num = 19, .regs = APB_DMA_OFFSET(0x14c0) }, + { .num = 20, .regs = APB_DMA_OFFSET(0x1500) }, + { .num = 21, .regs = APB_DMA_OFFSET(0x1540) }, + { .num = 22, .regs = APB_DMA_OFFSET(0x1580) }, + { .num = 23, .regs = APB_DMA_OFFSET(0x15c0) }, + { .num = 24, .regs = APB_DMA_OFFSET(0x1600) }, + { .num = 25, .regs = APB_DMA_OFFSET(0x1640) }, + { .num = 26, .regs = APB_DMA_OFFSET(0x1680) }, + { .num = 27, .regs = APB_DMA_OFFSET(0x16c0) }, + { .num = 28, .regs = APB_DMA_OFFSET(0x1700) }, + { .num = 29, .regs = APB_DMA_OFFSET(0x1740) }, + { .num = 30, .regs = APB_DMA_OFFSET(0x1780) }, + { .num = 31, .regs = APB_DMA_OFFSET(0x17c0) }, +}; + +int dma_busy(struct apb_dma_channel * const channel) +{ + /* + * In continuous mode, the BSY_n bit in APB_DMA_STATUS and + * BSY in APBDMACHAN_CHANNEL_n_STA_0 will remain set as '1' so long + * as the channel is enabled. So for this function we'll use the + * DMA_ACTIVITY bit. + */ + return read32(&channel->regs->sta) & APBDMACHAN_STA_DMA_ACTIVITY ? 1 : 0; +} +/* claim a DMA channel */ +struct apb_dma_channel * const dma_claim(void) +{ + int i; + struct apb_dma_channel_regs *regs = NULL; + + /* + * Set global enable bit, otherwise register access to channel + * DMA registers will not be possible. + */ + setbits_le32(&apb_dma->command, APBDMA_COMMAND_GEN); + + for (i = 0; i < ARRAY_SIZE(apb_dma_channels); i++) { + regs = apb_dma_channels[i].regs; + + if (!apb_dma_channels[i].in_use) { + u32 status = read32(&regs->sta); + if (status & (1 << i)) { + /* FIXME: should this be fatal? */ + printk(BIOS_DEBUG, "%s: DMA channel %d busy?\n", + __func__, i); + } + break; + } + } + + if (i == ARRAY_SIZE(apb_dma_channels)) + return NULL; + + apb_dma_channels[i].in_use = 1; + return &apb_dma_channels[i]; +} + +/* release a DMA channel */ +void dma_release(struct apb_dma_channel * const channel) +{ + int i; + + /* FIXME: make this "thread" friendly */ + while (dma_busy(channel)) + ; + + channel->in_use = 0; + + /* clear the global enable bit if no channels are in use */ + for (i = 0; i < ARRAY_SIZE(apb_dma_channels); i++) { + if (apb_dma_channels[i].in_use) + return; + } + + clrbits_le32(&apb_dma->command, APBDMA_COMMAND_GEN); +} + +int dma_start(struct apb_dma_channel * const channel) +{ + struct apb_dma_channel_regs *regs = channel->regs; + + /* Set ENB bit for this channel */ + setbits_le32(&regs->csr, APBDMACHAN_CSR_ENB); + + return 0; +} + +int dma_stop(struct apb_dma_channel * const channel) +{ + struct apb_dma_channel_regs *regs = channel->regs; + + /* Clear ENB bit for this channel */ + clrbits_le32(&regs->csr, APBDMACHAN_CSR_ENB); + + return 0; +} diff --git a/src/soc/nvidia/tegra124/dma.h b/src/soc/nvidia/tegra124/dma.h new file mode 100644 index 0000000..d7e9090 --- /dev/null +++ b/src/soc/nvidia/tegra124/dma.h @@ -0,0 +1,61 @@ +/* + * (C) Copyright 2010,2011 + * NVIDIA Corporation <www.nvidia.com> + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef __NVIDIA_TEGRA124_DMA_H__ +#define __NVIDIA_TEGRA124_DMA_H__ + +#include <inttypes.h> +#include <soc/addressmap.h> + +/* + * The DMA engine operates on 4 bytes at a time, so make sure any data + * passed via DMA is aligned to avoid underrun/overrun. + */ +#define TEGRA_DMA_ALIGN_BYTES 4 + +struct apb_dma_channel_regs { + u32 csr; /* 0x00 */ + u32 sta; /* 0x04 */ + u32 dma_byte_sta; /* 0x08 */ + u32 csre; /* 0x0c */ + u32 ahb_ptr; /* 0x10 */ + u32 ahb_seq; /* 0x14 */ + u32 apb_ptr; /* 0x18 */ + u32 apb_seq; /* 0x1c */ + u32 wcount; /* 0x20 */ + u32 word_transfer; /* 0x24 */ +} __attribute__((packed)); + +struct apb_dma_channel { + const int num; + struct apb_dma_channel_regs *regs; + + /* + * Basic high-level semaphore that can be used to "claim" + * a DMA channel e.g. by SPI, I2C, or other peripheral driver. + */ + int in_use; +}; + +struct apb_dma_channel * const dma_claim(void); +void dma_release(struct apb_dma_channel * const channel); +int dma_start(struct apb_dma_channel * const channel); +int dma_stop(struct apb_dma_channel * const channel); +int dma_busy(struct apb_dma_channel * const channel); + +#endif /* __NVIDIA_TEGRA124_DMA_H__ */ diff --git a/src/soc/nvidia/tegra124/early_display.c b/src/soc/nvidia/tegra124/early_display.c new file mode 100644 index 0000000..4356a62 --- /dev/null +++ b/src/soc/nvidia/tegra124/early_display.c @@ -0,0 +1,61 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <stdlib.h> +#include <stddef.h> +#include <arch/cache.h> +#include "chip.h" +#include <soc/display.h> +#include "gpio.h" + +/* the primary purpose of this function is to kick off things in + * romstage that are time consuming. No more should be done at this + * point than the bare minimum that will allow us to pick up the work + * in the ramstage and not require lots of udelays. ramstage will do + * the rest. As it happens, that merely means 'turn off everything you can, + * save the minimum long-delay bit that you need to get graphics going'. It's + * important not to have the backlight on as people don't like display trash + * on startup, even if I do. + */ +void setup_display(struct soc_nvidia_tegra124_config *config) +{ + if (config->panel_vdd_gpio){ + gpio_output(config->panel_vdd_gpio, 1); + printk(BIOS_SPEW,"%s: setting gpio %08x to %d\n", + __func__, config->panel_vdd_gpio, 1); + } + if (config->lvds_shutdown_gpio){ + gpio_output(config->lvds_shutdown_gpio, 0); + printk(BIOS_SPEW,"%s: setting gpio %08x to %d\n", + __func__, config->lvds_shutdown_gpio, 0); + } + if (config->backlight_en_gpio){ + gpio_output(config->backlight_en_gpio, 0); + printk(BIOS_SPEW,"%s: setting gpio %08x to %d\n", + __func__, config->backlight_en_gpio, 0); + } + if (config->backlight_vdd_gpio){ + gpio_output(config->backlight_vdd_gpio, 0); + printk(BIOS_SPEW,"%s: setting gpio %08x to %d\n", + __func__, config->backlight_vdd_gpio, 0); + } + +} + diff --git a/src/soc/nvidia/tegra124/flow.h b/src/soc/nvidia/tegra124/flow.h new file mode 100644 index 0000000..a974f09 --- /dev/null +++ b/src/soc/nvidia/tegra124/flow.h @@ -0,0 +1,49 @@ +/* + * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef _TEGRA124_FLOW_H_ +#define _TEGRA124_FLOW_H_ + +struct flow_ctlr { + u32 halt_cpu_events; /* offset 0x00 */ + u32 halt_cop_events; /* offset 0x04 */ + u32 cpu_csr; /* offset 0x08 */ + u32 cop_csr; /* offset 0x0c */ + u32 xrq_events; /* offset 0x10 */ + u32 halt_cpu1_events; /* offset 0x14 */ + u32 cpu1_csr; /* offset 0x18 */ + u32 halt_cpu2_events; /* offset 0x1c */ + u32 cpu2_csr; /* offset 0x20 */ + u32 halt_cpu3_events; /* offset 0x24 */ + u32 cpu3_csr; /* offset 0x28 */ + u32 cluster_control; /* offset 0x2c */ + u32 halt_cop1_events; /* offset 0x30 */ + u32 halt_cop1_csr; /* offset 0x34 */ + u32 cpu_pwr_csr; /* offset 0x38 */ + u32 mpid; /* offset 0x3c */ + u32 ram_repair; /* offset 0x40 */ +}; + +/* HALT_COP_EVENTS_0, 0x04 */ +#define EVENT_MSEC (1 << 24) +#define EVENT_USEC (1 << 25) +#define EVENT_JTAG (1 << 28) +#define EVENT_MODE_STOP (2 << 29) + +/* FLOW_CTLR_CLUSTER_CONTROL_0 0x2c */ +#define ACTIVE_LP (1 << 0) + +#endif /* _TEGRA124_FLOW_H_ */ diff --git a/src/soc/nvidia/tegra124/gpio.h b/src/soc/nvidia/tegra124/gpio.h index 83d727d..f7d1c30 100644 --- a/src/soc/nvidia/tegra124/gpio.h +++ b/src/soc/nvidia/tegra124/gpio.h @@ -23,11 +23,14 @@ #include <soc/nvidia/tegra/gpio.h> #include <stdint.h> +#include "pinmux.h" /* for pinmux constants in GPIO macro */ + /* GPIO index constants. */ #define GPIO_PORT_CONSTANTS(port) \ - GPIO_##port##0, GPIO_##port##1, GPIO_##port##2, GPIO_##port##3, \ - GPIO_##port##4, GPIO_##port##5, GPIO_##port##6, GPIO_##port##7 + GPIO_##port##0_INDEX, GPIO_##port##1_INDEX, GPIO_##port##2_INDEX, \ + GPIO_##port##3_INDEX, GPIO_##port##4_INDEX, GPIO_##port##5_INDEX, \ + GPIO_##port##6_INDEX, GPIO_##port##7_INDEX enum { GPIO_PORT_CONSTANTS(A), diff --git a/src/soc/nvidia/tegra124/include/soc/addressmap.h b/src/soc/nvidia/tegra124/include/soc/addressmap.h index bf59d75..9836215 100644 --- a/src/soc/nvidia/tegra124/include/soc/addressmap.h +++ b/src/soc/nvidia/tegra124/include/soc/addressmap.h @@ -21,6 +21,8 @@ #ifndef __SOC_NVIDIA_TEGRA124_INCLUDE_SOC_ADDRESS_MAP_H__ #define __SOC_NVIDIA_TEGRA124_INCLUDE_SOC_ADDRESS_MAP_H__ +#include <stddef.h> + enum { TEGRA_SRAM_BASE = 0x40000000, TEGRA_SRAM_SIZE = 0x20000 @@ -28,12 +30,15 @@ enum { enum { TEGRA_ARM_PERIPHBASE = 0x50040000, + TEGRA_ARM_DISPLAYA = 0x54200000, + TEGRA_ARM_DISPLAYB = 0x54240000, TEGRA_PG_UP_BASE = 0x60000000, TEGRA_TMRUS_BASE = 0x60005010, TEGRA_CLK_RST_BASE = 0x60006000, TEGRA_FLOW_BASE = 0x60007000, TEGRA_GPIO_BASE = 0x6000D000, TEGRA_EVP_BASE = 0x6000F000, + TEGRA_APB_DMA_BASE = 0x60020000, TEGRA_APB_MISC_BASE = 0x70000000, TEGRA_APB_MISC_GP_BASE = TEGRA_APB_MISC_BASE + 0x0800, TEGRA_APB_PINGROUP_BASE = TEGRA_APB_MISC_BASE + 0x0868, @@ -51,12 +56,12 @@ enum { TEGRA_I2C4_BASE = TEGRA_APB_MISC_BASE + 0xC700, TEGRA_I2C5_BASE = TEGRA_APB_MISC_BASE + 0xD000, TEGRA_I2C6_BASE = TEGRA_APB_MISC_BASE + 0xD100, - TEGRA_SLINK1_BASE = TEGRA_APB_MISC_BASE + 0xD400, - TEGRA_SLINK2_BASE = TEGRA_APB_MISC_BASE + 0xD600, - TEGRA_SLINK3_BASE = TEGRA_APB_MISC_BASE + 0xD800, - TEGRA_SLINK4_BASE = TEGRA_APB_MISC_BASE + 0xDA00, - TEGRA_SLINK5_BASE = TEGRA_APB_MISC_BASE + 0xDC00, - TEGRA_SLINK6_BASE = TEGRA_APB_MISC_BASE + 0xDE00, + TEGRA_SPI1_BASE = TEGRA_APB_MISC_BASE + 0xD400, + TEGRA_SPI2_BASE = TEGRA_APB_MISC_BASE + 0xD600, + TEGRA_SPI3_BASE = TEGRA_APB_MISC_BASE + 0xD800, + TEGRA_SPI4_BASE = TEGRA_APB_MISC_BASE + 0xDA00, + TEGRA_SPI5_BASE = TEGRA_APB_MISC_BASE + 0xDC00, + TEGRA_SPI6_BASE = TEGRA_APB_MISC_BASE + 0xDE00, TEGRA_DVC_BASE = TEGRA_APB_MISC_BASE + 0xD000, TEGRA_PMC_BASE = TEGRA_APB_MISC_BASE + 0xE400, TEGRA_EMC_BASE = TEGRA_APB_MISC_BASE + 0xF400, @@ -69,4 +74,9 @@ enum { TEGRA_I2C_BASE_COUNT = 6, }; +enum { + FB_SIZE_MB = (32), + FB_BASE_MB = (CONFIG_SYS_SDRAM_BASE/MiB + (CONFIG_DRAM_SIZE_MB - FB_SIZE_MB)), +}; + #endif /* __SOC_NVIDIA_TEGRA124_INCLUDE_SOC_ADDRESS_MAP_H__ */ diff --git a/src/soc/nvidia/tegra124/include/soc/clock.h b/src/soc/nvidia/tegra124/include/soc/clock.h new file mode 100644 index 0000000..056a38b --- /dev/null +++ b/src/soc/nvidia/tegra124/include/soc/clock.h @@ -0,0 +1,171 @@ +/* + * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef __SOC_NVIDIA_TEGRA124_CLOCK_H__ +#define __SOC_NVIDIA_TEGRA124_CLOCK_H__ + +enum { + CLK_L_CPU = 0x1 << 0, + CLK_L_COP = 0x1 << 1, + CLK_L_TRIG_SYS = 0x1 << 2, + CLK_L_RTC = 0x1 << 4, + CLK_L_TMR = 0x1 << 5, + CLK_L_UARTA = 0x1 << 6, + CLK_L_UARTB = 0x1 << 7, + CLK_L_GPIO = 0x1 << 8, + CLK_L_SDMMC2 = 0x1 << 9, + CLK_L_SPDIF = 0x1 << 10, + CLK_L_I2S1 = 0x1 << 11, + CLK_L_I2C1 = 0x1 << 12, + CLK_L_NDFLASH = 0x1 << 13, + CLK_L_SDMMC1 = 0x1 << 14, + CLK_L_SDMMC4 = 0x1 << 15, + CLK_L_PWM = 0x1 << 17, + CLK_L_I2S2 = 0x1 << 18, + CLK_L_EPP = 0x1 << 19, + CLK_L_VI = 0x1 << 20, + CLK_L_2D = 0x1 << 21, + CLK_L_USBD = 0x1 << 22, + CLK_L_ISP = 0x1 << 23, + CLK_L_3D = 0x1 << 24, + CLK_L_DISP2 = 0x1 << 26, + CLK_L_DISP1 = 0x1 << 27, + CLK_L_HOST1X = 0x1 << 28, + CLK_L_VCP = 0x1 << 29, + CLK_L_I2S0 = 0x1 << 30, + CLK_L_CACHE2 = 0x1 << 31, + + CLK_H_MEM = 0x1 << 0, + CLK_H_AHBDMA = 0x1 << 1, + CLK_H_APBDMA = 0x1 << 2, + CLK_H_KBC = 0x1 << 4, + CLK_H_STAT_MON = 0x1 << 5, + CLK_H_PMC = 0x1 << 6, + CLK_H_FUSE = 0x1 << 7, + CLK_H_KFUSE = 0x1 << 8, + CLK_H_SBC1 = 0x1 << 9, + CLK_H_SNOR = 0x1 << 10, + CLK_H_JTAG2TBC = 0x1 << 11, + CLK_H_SBC2 = 0x1 << 12, + CLK_H_SBC3 = 0x1 << 14, + CLK_H_I2C5 = 0x1 << 15, + CLK_H_DSI = 0x1 << 16, + CLK_H_HSI = 0x1 << 18, + CLK_H_HDMI = 0x1 << 19, + CLK_H_CSI = 0x1 << 20, + CLK_H_I2C2 = 0x1 << 22, + CLK_H_UARTC = 0x1 << 23, + CLK_H_MIPI_CAL = 0x1 << 24, + CLK_H_EMC = 0x1 << 25, + CLK_H_USB2 = 0x1 << 26, + CLK_H_USB3 = 0x1 << 27, + CLK_H_MPE = 0x1 << 28, + CLK_H_VDE = 0x1 << 29, + CLK_H_BSEA = 0x1 << 30, + CLK_H_BSEV = 0x1 << 31, + + CLK_U_UARTD = 0x1 << 1, + CLK_U_UARTE = 0x1 << 2, + CLK_U_I2C3 = 0x1 << 3, + CLK_U_SBC4 = 0x1 << 4, + CLK_U_SDMMC3 = 0x1 << 5, + CLK_U_PCIE = 0x1 << 6, + CLK_U_OWR = 0x1 << 7, + CLK_U_AFI = 0x1 << 8, + CLK_U_CSITE = 0x1 << 9, + CLK_U_PCIEXCLK = 0x1 << 10, + CLK_U_AVPUCQ = 0x1 << 11, + CLK_U_TRACECLKIN = 0x1 << 13, + CLK_U_SOC_THERM = 0x1 << 14, + CLK_U_DTV = 0x1 << 15, + CLK_U_NAND_SPEED = 0x1 << 16, + CLK_U_I2C_SLOW = 0x1 << 17, + CLK_U_DSIB = 0x1 << 18, + CLK_U_TSEC = 0x1 << 19, + CLK_U_IRAMA = 0x1 << 20, + CLK_U_IRAMB = 0x1 << 21, + CLK_U_IRAMC = 0x1 << 22, + + // Clock reset. + CLK_U_EMUCIF = 0x1 << 23, + // Clock enable. + CLK_U_IRAMD = 0x1 << 23, + + CLK_U_CRAM2 = 0x2 << 24, + CLK_U_XUSB_HOST = 0x1 << 25, + CLK_U_MSENC = 0x1 << 27, + CLK_U_SUS_OUT = 0x1 << 28, + CLK_U_DEV2_OUT = 0x1 << 29, + CLK_U_DEV1_OUT = 0x1 << 30, + CLK_U_XUSB_DEV = 0x1 << 31, + + CLK_V_CPUG = 0x1 << 0, + CLK_V_CPULP = 0x1 << 1, + CLK_V_3D2 = 0x1 << 2, + CLK_V_MSELECT = 0x1 << 3, + CLK_V_I2S3 = 0x1 << 5, + CLK_V_I2S4 = 0x1 << 6, + CLK_V_I2C4 = 0x1 << 7, + CLK_V_SBC5 = 0x1 << 8, + CLK_V_SBC6 = 0x1 << 9, + CLK_V_AUDIO = 0x1 << 10, + CLK_V_APBIF = 0x1 << 11, + CLK_V_DAM0 = 0x1 << 12, + CLK_V_DAM1 = 0x1 << 13, + CLK_V_DAM2 = 0x1 << 14, + CLK_V_HDA2CODEC_2X = 0x1 << 15, + CLK_V_ATOMICS = 0x1 << 16, + CLK_V_ACTMON = 0x1 << 23, + CLK_V_SATA = 0x1 << 28, + CLK_V_HDA = 0x1 << 29, + + CLK_W_HDA2HDMICODEC = 0x1 << 0, + CLK_W_SATACOLD = 0x1 << 1, + CLK_W_CEC = 0x1 << 8, + CLK_W_XUSB_PADCTL = 0x1 << 14, + CLK_W_ENTROPY = 0x1 << 21, + CLK_W_AMX0 = 0x1 << 25, + CLK_W_ADX0 = 0x1 << 26, + CLK_W_DVFS = 0x1 << 27, + CLK_W_XUSB_SS = 0x1 << 28, + CLK_W_MC1 = 0x1 << 30, + CLK_W_EMC1 = 0x1 << 31 +}; + +/* PLL stabilization delay in usec */ +#define CLOCK_PLL_STABLE_DELAY_US 300 + +#define IO_STABILIZATION_DELAY (2) +/* Calculate clock fractional divider value from ref and target frequencies */ +#define CLK_DIVIDER(REF, FREQ) ((((REF) * 2) / FREQ) - 2) + +/* Calculate clock frequency value from reference and clock divider value */ +#define CLK_FREQUENCY(REF, REG) (((REF) * 2) / (REG + 2)) + +/* soc-specific */ +#define TEGRA_PLLX_KHZ (1900000) +#define TEGRA_PLLP_KHZ (408000) +#define TEGRA_PLLC_KHZ (600000) +#define TEGRA_PLLD_KHZ (925000) +#define TEGRA_PLLU_KHZ (960000) + +int clock_get_osc_khz(void); +void clock_early_uart(void); +void clock_cpu0_config_and_reset(void * entry); +void clock_config(void); +void clock_init(void); +void clock_ll_set_source_divisor(u32 *reg, u32 source, u32 divisor); +#endif /* __SOC_NVIDIA_TEGRA124_CLOCK_H__ */ diff --git a/src/soc/nvidia/tegra124/include/soc/display.h b/src/soc/nvidia/tegra124/include/soc/display.h new file mode 100644 index 0000000..8c7e3e7 --- /dev/null +++ b/src/soc/nvidia/tegra124/include/soc/display.h @@ -0,0 +1,22 @@ +/* + * Copyright 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef __SOC_NVIDIA_TEGRA124_INCLUDE_SOC_DISPLAY_H__ +#define __SOC_NVIDIA_TEGRA124_INCLUDE_SOC_DISPLAY_H__ + +void setup_display(struct soc_nvidia_tegra124_config *config); + +#endif /* __SOC_NVIDIA_TEGRA124_INCLUDE_SOC_DISPLAY_H__ */ diff --git a/src/soc/nvidia/tegra124/pmc.h b/src/soc/nvidia/tegra124/pmc.h new file mode 100644 index 0000000..1134abd --- /dev/null +++ b/src/soc/nvidia/tegra124/pmc.h @@ -0,0 +1,200 @@ +/* + * Copyright (c) 2010 - 2013, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef _TEGRA124_PMC_H_ +#define _TEGRA124_PMC_H_ + +#include <stdint.h> + +enum { + POWER_PARTID_CRAIL = 0, + POWER_PARTID_TD = 1, + POWER_PARTID_VE = 2, + POWER_PARTID_VDE = 4, + POWER_PARTID_L2C = 5, + POWER_PARTID_MPE = 6, + POWER_PARTID_HEG = 7, + POWER_PARTID_CE1 = 9, + POWER_PARTID_CE2 = 10, + POWER_PARTID_CE3 = 11, + POWER_PARTID_CELP = 12, + POWER_PARTID_CE0 = 14, + POWER_PARTID_C0NC = 15, + POWER_PARTID_C1NC = 16, + POWER_PARTID_DIS = 18, + POWER_PARTID_DISB = 19, + POWER_PARTID_XUSBA = 20, + POWER_PARTID_XUSBB = 21, + POWER_PARTID_XUSBC = 22 +}; + +struct tegra_pmc_regs { + u32 cntrl; + u32 sec_disable; + u32 pmc_swrst; + u32 wake_mask; + u32 wake_lvl; + u32 wake_status; + u32 sw_wake_status; + u32 dpd_pads_oride; + u32 dpd_sample; + u32 dpd_enable; + u32 pwrgate_timer_off; + u32 clamp_status; + u32 pwrgate_toggle; + u32 remove_clamping_cmd; + u32 pwrgate_status; + u32 pwrgood_timer; + u32 blink_timer; + u32 no_iopower; + u32 pwr_det; + u32 pwr_det_latch; + u32 scratch[24]; + u32 secure_scratch[6]; + u32 cpupwrgood_timer; + u32 cpupwroff_timer; + u32 pg_mask; + u32 pg_mask_1; + u32 auto_wake_lvl; + u32 auto_wake_lvl_mask; + u32 wake_delay; + u32 pwr_det_val; + u32 ddr_pwr; + u32 usb_debounce_del; + u32 usb_a0; + u32 crypto_op; + u32 pllp_wb0_override; + u32 scratch24[43 - 24]; + u32 bondout_mirror[3]; + u32 sys_33v_en; + u32 bondout_mirror_access; + u32 gate; + u32 wake2_mask; + u32 wake2_lvl; + u32 wake2_status; + u32 sw_wake2_status; + u32 auto_wake2_lvl_mask; + u32 pg_mask_2; + u32 pg_mask_ce1; + u32 pg_mask_ce2; + u32 pg_mask_ce3; + u32 pwrgate_timer_ce[7]; + u32 pcx_edpd_cntrl; + u32 osc_edpd_over; + u32 clk_out_cntrl; + u32 sata_pwrgt; + u32 sensor_ctrl; + u32 rst_status; + u32 io_dpd_req; + u32 io_dpd_status; + u32 io_dpd2_req; + u32 io_dpd2_status; + u32 sel_dpd_tim; + u32 vddp_sel; + u32 ddr_cfg; + u32 e_no_vttgen; + u8 _rsv0[4]; + u32 pllm_wb0_override_freq; + u32 test_pwrgate; + u32 pwrgate_timer_mult; + u32 dis_sel_dpd; + u32 utmip_uhsic_triggers; + u32 utmip_uhsic_saved_state; + u32 utmip_pad_cfg; + u32 utmip_term_pad_cfg; + u32 utmip_uhsic_sleep_cfg; + u32 utmip_uhsic_sleepwalk_cfg; + u32 utmip_sleepwalk_p[3]; + u32 uhsic_sleepwalk_p0; + u32 utmip_uhsic_status; + u32 utmip_uhsic_fake; + u32 bondout_mirror3[5 - 3]; + u32 secure_scratch6[8 - 6]; + u32 scratch43[56 - 43]; + u32 scratch_eco[3]; + u32 utmip_uhsic_line_wakeup; + u32 utmip_bias_master_cntrl; + u32 utmip_master_config; + u32 td_pwrgate_inter_part_timer; + u32 utmip_uhsic2_triggers; + u32 utmip_uhsic2_saved_state; + u32 utmip_uhsic2_sleep_cfg; + u32 utmip_uhsic2_sleepwalk_cfg; + u32 uhsic2_sleepwalk_p1; + u32 utmip_uhsic2_status; + u32 utmip_uhsic2_fake; + u32 utmip_uhsic2_line_wakeup; + u32 utmip_master2_config; + u32 utmip_uhsic_rpd_cfg; + u32 pg_mask_ce0; + u32 pg_mask3[5 - 3]; + u32 pllm_wb0_override2; + u32 tsc_mult; + u32 cpu_vsense_override; + u32 glb_amap_cfg; + u32 sticky_bits; + u32 sec_disable2; + u32 weak_bias; + u32 reg_short; + u32 pg_mask_andor; + u8 _rsv1[0x2c]; + u32 secure_scratch8[24 - 8]; + u32 scratch56[120 - 56]; +}; + +enum { + PMC_PWRGATE_TOGGLE_PARTID_MASK = 0x1f, + PMC_PWRGATE_TOGGLE_PARTID_SHIFT = 0, + PMC_PWRGATE_TOGGLE_START = 0x1 << 8 +}; + +enum { + PMC_CNTRL_KBC_CLK_DIS = 0x1 << 0, + PMC_CNTRL_RTC_CLK_DIS = 0x1 << 1, + PMC_CNTRL_RTC_RST = 0x1 << 2, + PMC_CNTRL_KBC_RST = 0x1 << 3, + PMC_CNTRL_MAIN_RST = 0x1 << 4, + PMC_CNTRL_LATCHWAKE_EN = 0x1 << 5, + PMC_CNTRL_GLITCHDET_DIS = 0x1 << 6, + PMC_CNTRL_BLINK_EN = 0x1 << 7, + PMC_CNTRL_PWRREQ_POLARITY = 0x1 << 8, + PMC_CNTRL_PWRREQ_OE = 0x1 << 9, + PMC_CNTRL_SYSCLK_POLARITY = 0x1 << 10, + PMC_CNTRL_SYSCLK_OE = 0x1 << 11, + PMC_CNTRL_PWRGATE_DIS = 0x1 << 12, + PMC_CNTRL_AOINIT = 0x1 << 13, + PMC_CNTRL_SIDE_EFFECT_LP0 = 0x1 << 14, + PMC_CNTRL_CPUPWRREQ_POLARITY = 0x1 << 15, + PMC_CNTRL_CPUPWRREQ_OE = 0x1 << 16, + PMC_CNTRL_INTR_POLARITY = 0x1 << 17, + PMC_CNTRL_FUSE_OVERRIDE = 0x1 << 18, + PMC_CNTRL_CPUPWRGOOD_EN = 0x1 << 19, + PMC_CNTRL_CPUPWRGOOD_SEL_SHIFT = 20, + PMC_CNTRL_CPUPWRGOOD_SEL_MASK = + 0x3 << PMC_CNTRL_CPUPWRGOOD_SEL_SHIFT +}; + +enum { + PMC_CNTRL2_HOLD_CKE_LOW_EN = 0x1 << 12 +}; + +enum { + PMC_OSC_EDPD_OVER_XOFS_SHIFT = 1, + PMC_OSC_EDPD_OVER_XOFS_MASK = + 0x3f << PMC_OSC_EDPD_OVER_XOFS_SHIFT +}; + +#endif /* _TEGRA124_PMC_H_ */ diff --git a/src/soc/nvidia/tegra124/power.c b/src/soc/nvidia/tegra124/power.c new file mode 100644 index 0000000..a3cf5ef --- /dev/null +++ b/src/soc/nvidia/tegra124/power.c @@ -0,0 +1,87 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2013 Google Inc. + * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <console/console.h> +#include <soc/addressmap.h> + +#include "pmc.h" +#include "power.h" + +static struct tegra_pmc_regs * const pmc = (void *)TEGRA_PMC_BASE; + +static int partition_powered(int id) +{ + return read32(&pmc->pwrgate_status) & (0x1 << id); +} + +static void power_ungate_partition(uint32_t id) +{ + printk(BIOS_INFO, "Ungating power partition %d.\n", id); + + if (!partition_powered(id)) { + uint32_t pwrgate_toggle = read32(&pmc->pwrgate_toggle); + pwrgate_toggle &= ~(PMC_PWRGATE_TOGGLE_PARTID_MASK); + pwrgate_toggle |= (id << PMC_PWRGATE_TOGGLE_PARTID_SHIFT); + pwrgate_toggle |= PMC_PWRGATE_TOGGLE_START; + write32(pwrgate_toggle, &pmc->pwrgate_toggle); + + // Wait for the request to be accepted. + while (read32(&pmc->pwrgate_toggle) & PMC_PWRGATE_TOGGLE_START) + ; + printk(BIOS_DEBUG, "Power gate toggle request accepted.\n"); + + // Wait for the partition to be powered. + while (!partition_powered(id)) + ; + } + + printk(BIOS_INFO, "Ungated power partition %d.\n", id); +} + +void power_enable_cpu_rail(void) +{ + // Set the power gate timer multiplier to 8 (why 8?). + uint32_t pwrgate_timer_mult = read32(&pmc->pwrgate_timer_mult); + pwrgate_timer_mult |= (0x3 << 0); + + /* + * From U-Boot: + * Set CPUPWRGOOD_TIMER - APB clock is 1/2 of SCLK (102MHz), + * set it for 5ms as per SysEng (102MHz/5mS = 510000). + */ + write32(510000, &pmc->cpupwrgood_timer); + + power_ungate_partition(POWER_PARTID_CRAIL); + + uint32_t cntrl = read32(&pmc->cntrl); + cntrl &= ~PMC_CNTRL_CPUPWRREQ_POLARITY; + cntrl |= PMC_CNTRL_CPUPWRREQ_OE; + write32(cntrl, &pmc->cntrl); +} + +void power_ungate_cpu(void) +{ + // Ungate power to the non-core parts of the fast cluster. + power_ungate_partition(POWER_PARTID_C0NC); + + // Ungate power to CPU0 in the fast cluster. + power_ungate_partition(POWER_PARTID_CE0); +} diff --git a/src/soc/nvidia/tegra124/power.h b/src/soc/nvidia/tegra124/power.h new file mode 100644 index 0000000..6454699 --- /dev/null +++ b/src/soc/nvidia/tegra124/power.h @@ -0,0 +1,29 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef __SOC_NVIDIA_TEGRA124_POWER_H__ +#define __SOC_NVIDIA_TEGRA124_POWER_H__ + +// This function does not enable the external power to the rail, it enables +// the rail itself internal to the SOC. +void power_enable_cpu_rail(void); + +void power_ungate_cpu(void); + +#endif /* __SOC_NVIDIA_TEGRA124_POWER_H__ */ diff --git a/src/soc/nvidia/tegra124/soc.c b/src/soc/nvidia/tegra124/soc.c new file mode 100644 index 0000000..e996c11 --- /dev/null +++ b/src/soc/nvidia/tegra124/soc.c @@ -0,0 +1,66 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. + * Copyright 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <device/device.h> +#include <soc/nvidia/tegra/dc.h> +#include <soc/addressmap.h> + +/* this sucks, but for now, fb size/location are hardcoded. + * Will break if we get 2. Sigh. + * We assume it's all multiples of MiB for MMUs sake. + */ +static void soc_enable(device_t dev) +{ + unsigned long fb_size = FB_SIZE_MB; + u32 lcdbase = FB_BASE_MB; + ram_resource(dev, 0, CONFIG_SYS_SDRAM_BASE/KiB, + (CONFIG_DRAM_SIZE_MB - fb_size)*KiB); + mmio_resource(dev, 1, lcdbase*KiB, fb_size*KiB); +} + +static void soc_init(device_t dev) +{ + display_startup(dev); + printk(BIOS_INFO, "CPU: Tegra124\n"); +} + +static void soc_noop(device_t dev) +{ +} + +static struct device_operations soc_ops = { + .read_resources = soc_noop, + .set_resources = soc_noop, + .enable_resources = soc_enable, + .init = soc_init, + .scan_bus = 0, +}; + +static void enable_tegra124_dev(device_t dev) +{ + dev->ops = &soc_ops; +} + +struct chip_operations soc_nvidia_tegra124_ops = { + CHIP_NAME("SOC Nvidia Tegra124") + .enable_dev = enable_tegra124_dev, +}; diff --git a/src/soc/nvidia/tegra124/spi.c b/src/soc/nvidia/tegra124/spi.c new file mode 100644 index 0000000..f7e0750 --- /dev/null +++ b/src/soc/nvidia/tegra124/spi.c @@ -0,0 +1,815 @@ +/* + * NVIDIA Tegra SPI controller (T114 and later) + * + * Copyright (c) 2010-2013 NVIDIA Corporation + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <assert.h> +#include <cbfs.h> +#include <cbfs_core.h> +#include <inttypes.h> +#include <spi-generic.h> +#include <stdint.h> +#include <stdlib.h> +#include <string.h> +#include <arch/io.h> +#include <console/console.h> +#include <soc/addressmap.h> +#include <delay.h> + +#include "dma.h" +#include "spi.h" + +#if defined(CONFIG_DEBUG_SPI) && CONFIG_DEBUG_SPI +# define DEBUG_SPI(x,...) printk(BIOS_DEBUG, "TEGRA_SPI: " x) +#else +# define DEBUG_SPI(x,...) +#endif + +/* + * 64 packets in FIFO mode, BLOCK_SIZE packets in DMA mode. Packets can vary + * in size from 4 to 32 bits. To keep things simple we'll use 8-bit packets. + */ +#define SPI_PACKET_SIZE_BYTES 1 +#define SPI_MAX_TRANSFER_BYTES_FIFO (64 * SPI_PACKET_SIZE_BYTES) +#define SPI_MAX_TRANSFER_BYTES_DMA ((65536 * SPI_PACKET_SIZE_BYTES) - \ + TEGRA_DMA_ALIGN_BYTES) + +/* COMMAND1 */ +#define SPI_CMD1_GO (1 << 31) +#define SPI_CMD1_M_S (1 << 30) +#define SPI_CMD1_MODE_MASK 0x3 +#define SPI_CMD1_MODE_SHIFT 28 +#define SPI_CMD1_CS_SEL_MASK 0x3 +#define SPI_CMD1_CS_SEL_SHIFT 26 +#define SPI_CMD1_CS_POL_INACTIVE3 (1 << 25) +#define SPI_CMD1_CS_POL_INACTIVE2 (1 << 24) +#define SPI_CMD1_CS_POL_INACTIVE1 (1 << 23) +#define SPI_CMD1_CS_POL_INACTIVE0 (1 << 22) +#define SPI_CMD1_CS_SW_HW (1 << 21) +#define SPI_CMD1_CS_SW_VAL (1 << 20) +#define SPI_CMD1_IDLE_SDA_MASK 0x3 +#define SPI_CMD1_IDLE_SDA_SHIFT 18 +#define SPI_CMD1_BIDIR (1 << 17) +#define SPI_CMD1_LSBI_FE (1 << 16) +#define SPI_CMD1_LSBY_FE (1 << 15) +#define SPI_CMD1_BOTH_EN_BIT (1 << 14) +#define SPI_CMD1_BOTH_EN_BYTE (1 << 13) +#define SPI_CMD1_RX_EN (1 << 12) +#define SPI_CMD1_TX_EN (1 << 11) +#define SPI_CMD1_PACKED (1 << 5) +#define SPI_CMD1_BIT_LEN_MASK 0x1f +#define SPI_CMD1_BIT_LEN_SHIFT 0 + +/* COMMAND2 */ +#define SPI_CMD2_TX_CLK_TAP_DELAY (1 << 6) +#define SPI_CMD2_TX_CLK_TAP_DELAY_MASK (0x3F << 6) +#define SPI_CMD2_RX_CLK_TAP_DELAY (1 << 0) +#define SPI_CMD2_RX_CLK_TAP_DELAY_MASK (0x3F << 0) + +/* SPI_TRANS_STATUS */ +#define SPI_STATUS_RDY (1 << 30) +#define SPI_STATUS_SLV_IDLE_COUNT_MASK 0xff +#define SPI_STATUS_SLV_IDLE_COUNT_SHIFT 16 +#define SPI_STATUS_BLOCK_COUNT 0xffff +#define SPI_STATUS_BLOCK_COUNT_SHIFT 0 + +/* SPI_FIFO_STATUS */ +#define SPI_FIFO_STATUS_CS_INACTIVE (1 << 31) +#define SPI_FIFO_STATUS_FRAME_END (1 << 30) +#define SPI_FIFO_STATUS_RX_FIFO_FLUSH (1 << 15) +#define SPI_FIFO_STATUS_TX_FIFO_FLUSH (1 << 14) +#define SPI_FIFO_STATUS_ERR (1 << 8) +#define SPI_FIFO_STATUS_TX_FIFO_OVF (1 << 7) +#define SPI_FIFO_STATUS_TX_FIFO_UNR (1 << 6) +#define SPI_FIFO_STATUS_RX_FIFO_OVF (1 << 5) +#define SPI_FIFO_STATUS_RX_FIFO_UNR (1 << 4) +#define SPI_FIFO_STATUS_TX_FIFO_FULL (1 << 3) +#define SPI_FIFO_STATUS_TX_FIFO_EMPTY (1 << 2) +#define SPI_FIFO_STATUS_RX_FIFO_FULL (1 << 1) +#define SPI_FIFO_STATUS_RX_FIFO_EMPTY (1 << 0) + +/* SPI_DMA_CTL */ +#define SPI_DMA_CTL_DMA (1 << 31) +#define SPI_DMA_CTL_CONT (1 << 30) +#define SPI_DMA_CTL_IE_RX (1 << 29) +#define SPI_DMA_CTL_IE_TX (1 << 28) +#define SPI_DMA_CTL_RX_TRIG_MASK 0x3 +#define SPI_DMA_CTL_RX_TRIG_SHIFT 19 +#define SPI_DMA_CTL_TX_TRIG_MASK 0x3 +#define SPI_DMA_CTL_TX_TRIG_SHIFT 15 + +/* SPI_DMA_BLK */ +#define SPI_DMA_CTL_BLOCK_SIZE_MASK 0xff +#define SPI_DMA_CTL_BLOCK_SIZE_SHIFT 0 + +struct tegra_spi_regs { + u32 command1; /* 0x000: SPI_COMMAND1 */ + u32 command2; /* 0x004: SPI_COMMAND2 */ + u32 timing1; /* 0x008: SPI_CS_TIM1 */ + u32 timing2; /* 0x00c: SPI_CS_TIM2 */ + u32 trans_status; /* 0x010: SPI_TRANS_STATUS */ + u32 fifo_status; /* 0x014: SPI_FIFO_STATUS */ + u32 tx_data; /* 0x018: SPI_TX_DATA */ + u32 rx_data; /* 0x01c: SPI_RX_DATA */ + u32 dma_ctl; /* 0x020: SPI_DMA_CTL */ + u32 dma_blk; /* 0x024: SPI_DMA_BLK */ + u32 rsvd[56]; /* 0x028-0x107: reserved */ + u32 tx_fifo; /* 0x108: SPI_FIFO1 */ + u32 rsvd2[31]; /* 0x10c-0x187 reserved */ + u32 rx_fifo; /* 0x188: SPI_FIFO2 */ + u32 spare_ctl; /* 0x18c: SPI_SPARE_CTRL */ +} __attribute__((packed)); + +struct tegra_spi_channel { + struct spi_slave slave; + struct tegra_spi_regs *regs; +}; + +static struct tegra_spi_channel tegra_spi_channels[] = { + /* + * Note: Tegra pinmux must be setup for corresponding SPI channel in + * order for its registers to be accessible. If pinmux has not been + * set up, access to the channel's registers will simply hang. + * + * TODO(dhendrix): Clarify or remove this comment (is clock setup + * necessary first, or just pinmux, or both?) + */ + { + .slave = { .bus = 1, }, + .regs = (struct tegra_spi_regs *)TEGRA_SPI1_BASE, + }, + { + .slave = { .bus = 2, }, + .regs = (struct tegra_spi_regs *)TEGRA_SPI2_BASE, + }, + { + .slave = { .bus = 3, }, + .regs = (struct tegra_spi_regs *)TEGRA_SPI3_BASE, + }, + { + .slave = { .bus = 4, }, + .regs = (struct tegra_spi_regs *)TEGRA_SPI4_BASE, + }, + { + .slave = { .bus = 5, }, + .regs = (struct tegra_spi_regs *)TEGRA_SPI5_BASE, + }, + { + .slave = { .bus = 6, }, + .regs = (struct tegra_spi_regs *)TEGRA_SPI6_BASE, + }, +}; + +static void flush_fifos(struct tegra_spi_regs *regs) +{ + setbits_le32(&regs->fifo_status, SPI_FIFO_STATUS_RX_FIFO_FLUSH | + SPI_FIFO_STATUS_TX_FIFO_FLUSH); + while (read32(&regs->fifo_status) & + (SPI_FIFO_STATUS_RX_FIFO_FLUSH | SPI_FIFO_STATUS_TX_FIFO_FLUSH)) + ; +} + +void tegra_spi_init(unsigned int bus) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(tegra_spi_channels); i++) { + struct tegra_spi_regs *regs; + + if (tegra_spi_channels[i].slave.bus == bus) + regs = tegra_spi_channels[i].regs; + else + continue; + + /* software drives chip-select, set value to high */ + setbits_le32(&regs->command1, + SPI_CMD1_CS_SW_HW | SPI_CMD1_CS_SW_VAL); + + /* 8-bit transfers, unpacked mode, most significant bit first */ + clrbits_le32(&regs->command1, + SPI_CMD1_BIT_LEN_MASK | SPI_CMD1_PACKED); + setbits_le32(&regs->command1, 7 << SPI_CMD1_BIT_LEN_SHIFT); + + flush_fifos(regs); + } + printk(BIOS_INFO, "Tegra SPI bus %d initialized.\n", bus); + +} + +static struct tegra_spi_channel * const to_tegra_spi(int bus) { + return &tegra_spi_channels[bus - 1]; +} + +static unsigned int tegra_spi_speed(unsigned int bus) +{ + /* FIXME: implement this properly, for now use max value (50MHz) */ + return 50000000; +} + +/* + * This calls udelay() with a calculated value based on the SPI speed and + * number of bytes remaining to be transferred. It assumes that if the + * calculated delay period is less than MIN_DELAY_US then it is probably + * not worth the overhead of yielding. + */ +#define MIN_DELAY_US 250 +static void tegra_spi_delay(struct tegra_spi_channel *spi, + unsigned int bytes_remaining) +{ + unsigned int ns_per_byte, delay_us; + + ns_per_byte = 1000000000 / (tegra_spi_speed(spi->slave.bus) / 8); + delay_us = (ns_per_byte * bytes_remaining) / 1000; + + if (delay_us < MIN_DELAY_US) + return; + + udelay(delay_us); +} + +void spi_cs_activate(struct spi_slave *slave) +{ + struct tegra_spi_regs *regs = to_tegra_spi(slave->bus)->regs; + u32 val; + + val = read32(&regs->command1); + + /* select appropriate chip-select line */ + val &= ~(SPI_CMD1_CS_SEL_MASK << SPI_CMD1_CS_SEL_SHIFT); + val |= (slave->cs << SPI_CMD1_CS_SEL_SHIFT); + + /* drive chip-select with the inverse of the "inactive" value */ + if (val & (SPI_CMD1_CS_POL_INACTIVE0 << slave->cs)) + val &= ~SPI_CMD1_CS_SW_VAL; + else + val |= SPI_CMD1_CS_SW_VAL; + + write32(val, &regs->command1); +} + +void spi_cs_deactivate(struct spi_slave *slave) +{ + struct tegra_spi_regs *regs = to_tegra_spi(slave->bus)->regs; + u32 val; + + val = read32(&regs->command1); + + if (val & (SPI_CMD1_CS_POL_INACTIVE0 << slave->cs)) + val |= SPI_CMD1_CS_SW_VAL; + else + val &= ~SPI_CMD1_CS_SW_VAL; + + write32(val, &regs->command1); +} + +static void dump_fifo_status(struct tegra_spi_channel *spi) +{ + u32 status = read32(&spi->regs->fifo_status); + + printk(BIOS_INFO, "Raw FIFO status: 0x%08x\n", status); + if (status & SPI_FIFO_STATUS_TX_FIFO_OVF) + printk(BIOS_INFO, "\tTx overflow detected\n"); + if (status & SPI_FIFO_STATUS_TX_FIFO_UNR) + printk(BIOS_INFO, "\tTx underrun detected\n"); + if (status & SPI_FIFO_STATUS_RX_FIFO_OVF) + printk(BIOS_INFO, "\tRx overflow detected\n"); + if (status & SPI_FIFO_STATUS_RX_FIFO_UNR) + printk(BIOS_INFO, "\tRx underrun detected\n"); + + printk(BIOS_INFO, "TX_FIFO: 0x%08x, TX_DATA: 0x%08x\n", + read32(&spi->regs->tx_fifo), read32(&spi->regs->tx_data)); + printk(BIOS_INFO, "RX_FIFO: 0x%08x, RX_DATA: 0x%08x\n", + read32(&spi->regs->rx_fifo), read32(&spi->regs->rx_data)); +} + +static void clear_fifo_status(struct tegra_spi_channel *spi) +{ + clrbits_le32(&spi->regs->fifo_status, + SPI_FIFO_STATUS_ERR | + SPI_FIFO_STATUS_TX_FIFO_OVF | + SPI_FIFO_STATUS_TX_FIFO_UNR | + SPI_FIFO_STATUS_RX_FIFO_OVF | + SPI_FIFO_STATUS_RX_FIFO_UNR); +} + +static void dump_spi_regs(struct tegra_spi_channel *spi) +{ + printk(BIOS_INFO, "SPI regs:\n" + "\tdma_blk: 0x%08x\n" + "\tcommand1: 0x%08x\n" + "\tdma_ctl: 0x%08x\n" + "\ttrans_status: 0x%08x\n", + read32(&spi->regs->dma_blk), + read32(&spi->regs->command1), + read32(&spi->regs->dma_ctl), + read32(&spi->regs->trans_status)); +} + +static void dump_dma_regs(struct apb_dma_channel *dma) +{ + printk(BIOS_INFO, "DMA regs:\n" + "\tahb_ptr: 0x%08x\n" + "\tapb_ptr: 0x%08x\n" + "\tahb_seq: 0x%08x\n" + "\tapb_seq: 0x%08x\n" + "\tcsr: 0x%08x\n" + "\tcsre: 0x%08x\n" + "\twcount: 0x%08x\n" + "\tdma_byte_sta: 0x%08x\n" + "\tword_transfer: 0x%08x\n", + read32(&dma->regs->ahb_ptr), + read32(&dma->regs->apb_ptr), + read32(&dma->regs->ahb_seq), + read32(&dma->regs->apb_seq), + read32(&dma->regs->csr), + read32(&dma->regs->csre), + read32(&dma->regs->wcount), + read32(&dma->regs->dma_byte_sta), + read32(&dma->regs->word_transfer)); +} + +static void dump_regs(struct tegra_spi_channel *spi, + struct apb_dma_channel *dma) +{ + if (dma) + dump_dma_regs(dma); + if (spi) { + dump_spi_regs(spi); + dump_fifo_status(spi); + } +} + +static int fifo_error(struct tegra_spi_channel *spi) +{ + return read32(&spi->regs->fifo_status) & SPI_FIFO_STATUS_ERR ? 1 : 0; +} + +static inline unsigned int spi_byte_count(struct tegra_spi_channel *spi) +{ + /* FIXME: Make this take total packet size into account */ + return read32(&spi->regs->trans_status) & + (SPI_STATUS_BLOCK_COUNT << SPI_STATUS_BLOCK_COUNT_SHIFT); +} + +static int tegra_spi_fifo_receive(struct tegra_spi_channel *spi, + u8 *din, unsigned int in_bytes) +{ + unsigned int received = 0, remaining = in_bytes; + + printk(BIOS_SPEW, "%s: Receiving %d bytes\n", __func__, in_bytes); + setbits_le32(&spi->regs->command1, SPI_CMD1_RX_EN); + + while (remaining) { + unsigned int from_fifo, count; + + from_fifo = MIN(in_bytes, SPI_MAX_TRANSFER_BYTES_FIFO); + remaining -= from_fifo; + + /* BLOCK_SIZE in SPI_DMA_BLK register applies to both DMA and + * PIO transfers */ + write32(from_fifo - 1, &spi->regs->dma_blk); + + setbits_le32(&spi->regs->trans_status, SPI_STATUS_RDY); + setbits_le32(&spi->regs->command1, SPI_CMD1_GO); + + while ((count = spi_byte_count(spi)) != from_fifo) { + tegra_spi_delay(spi, from_fifo - count); + if (fifo_error(spi)) + goto done; + } + + received += from_fifo; + while (from_fifo) { + *din = read8(&spi->regs->rx_fifo); + din++; + from_fifo--; + } + } + +done: + clrbits_le32(&spi->regs->command1, SPI_CMD1_RX_EN); + if ((received != in_bytes) || fifo_error(spi)) { + printk(BIOS_ERR, "%s: ERROR: Received %u bytes, expected %u\n", + __func__, received, in_bytes); + dump_regs(spi, NULL); + return -1; + } + return in_bytes; +} + +static int tegra_spi_fifo_send(struct tegra_spi_channel *spi, + const u8 *dout, unsigned int out_bytes) +{ + unsigned int sent = 0, remaining = out_bytes; + + printk(BIOS_SPEW, "%s: Sending %d bytes\n", __func__, out_bytes); + setbits_le32(&spi->regs->command1, SPI_CMD1_TX_EN); + + while (remaining) { + unsigned int to_fifo, tmp; + + to_fifo = MIN(out_bytes, SPI_MAX_TRANSFER_BYTES_FIFO); + + /* BLOCK_SIZE in SPI_DMA_BLK register applies to both DMA and + * PIO transfers */ + write32(to_fifo - 1, &spi->regs->dma_blk); + + tmp = to_fifo; + while (tmp) { + write32(*dout, &spi->regs->tx_fifo); + dout++; + tmp--; + } + + setbits_le32(&spi->regs->trans_status, SPI_STATUS_RDY); + setbits_le32(&spi->regs->command1, SPI_CMD1_GO); + + while (!(read32(&spi->regs->fifo_status) & + SPI_FIFO_STATUS_TX_FIFO_EMPTY)) { + tegra_spi_delay(spi, to_fifo - spi_byte_count(spi)); + if (fifo_error(spi)) + goto done; + } + + remaining -= to_fifo; + sent += to_fifo; + } + +done: + clrbits_le32(&spi->regs->command1, SPI_CMD1_TX_EN); + if ((sent != out_bytes) || fifo_error(spi)) { + printk(BIOS_ERR, "%s: ERROR: Sent %u bytes, expected " + "to send %u\n", __func__, sent, out_bytes); + dump_regs(spi, NULL); + return -1; + } + return out_bytes; +} + +static void tegra2_spi_dma_setup(struct apb_dma_channel *dma) +{ + /* APB bus width = 8-bits, address wrap for each word */ + clrbits_le32(&dma->regs->apb_seq, 0x7 << 28); + /* AHB 1 word burst, bus width = 32 bits (fixed in hardware), + * no address wrapping */ + clrsetbits_le32(&dma->regs->ahb_seq, + (0x7 << 24) | (0x7 << 16), 0x4 << 24); + /* Set ONCE mode to transfer one "blocK" at a time (64KB). */ + setbits_le32(&dma->regs->csr, 1 << 27); +} + +/* + * Notes for DMA transmit and receive, experimentally determined (need to + * verify): + * - WCOUNT seems to be an "n-1" count, but the documentation does not + * make this clear. Without the -1 dma_byte_sta will show 1 AHB word + * (4 bytes) higher than it should and Tx overrun / Rx underrun will + * likely occur. + * + * - dma_byte_sta is always a multiple 4, so we check for + * dma_byte_sta < length + * + * - The RDY bit in SPI_TRANS_STATUS needs to be cleared manually + * (set bit to clear) between each transaction. Otherwise the next + * transaction does not start. + */ + +static int tegra_spi_dma_receive(struct tegra_spi_channel *spi, + const void *din, unsigned int in_bytes) +{ + struct apb_dma_channel *dma; + + dma = dma_claim(); + if (!dma) { + printk(BIOS_ERR, "%s: Unable to claim DMA channel\n", __func__); + return -1; + } + + printk(BIOS_SPEW, "%s: Receiving %d bytes\n", __func__, in_bytes); + tegra2_spi_dma_setup(dma); + + /* set AHB & APB address pointers */ + write32((u32)din, &dma->regs->ahb_ptr); + write32((u32)&spi->regs->rx_fifo, &dma->regs->apb_ptr); + + setbits_le32(&spi->regs->command1, SPI_CMD1_RX_EN); + + /* FIXME: calculate word count so that it corresponds to bus width */ + write32(in_bytes - 1, &dma->regs->wcount); + + /* specify BLOCK_SIZE in SPI_DMA_BLK */ + write32(in_bytes - 1, &spi->regs->dma_blk); + + /* Set DMA direction for APB (SPI) --> AHB (DRAM) */ + clrbits_le32(&dma->regs->csr, 1 << 28); + + /* write to SPI_TRANS_STATUS RDY bit to clear it */ + setbits_le32(&spi->regs->trans_status, SPI_STATUS_RDY); + + /* set DMA bit in SPI_DMA_CTL to start */ + setbits_le32(&spi->regs->dma_ctl, SPI_DMA_CTL_DMA); + + /* start APBDMA after SPI DMA so we don't read empty bytes + * from Rx FIFO */ + dma_start(dma); + + while (spi_byte_count(spi) != in_bytes) + tegra_spi_delay(spi, in_bytes - spi_byte_count(spi)); + clrbits_le32(&spi->regs->command1, SPI_CMD1_RX_EN); + + while ((read32(&dma->regs->dma_byte_sta) < in_bytes) || dma_busy(dma)) + ; /* this shouldn't take long, no udelay */ + dma_stop(dma); + dma_release(dma); + + if ((spi_byte_count(spi) != in_bytes) || fifo_error(spi)) { + printk(BIOS_ERR, "%s: ERROR: Received %u bytes, expected %u\n", + __func__, spi_byte_count(spi), in_bytes); + dump_regs(spi, dma); + return -1; + } + + return in_bytes; +} + +static int tegra_spi_dma_send(struct tegra_spi_channel *spi, + const u8 *dout, unsigned int out_bytes) +{ + struct apb_dma_channel *dma; + unsigned int count; + + dma = dma_claim(); + if (!dma) { + printk(BIOS_ERR, "%s: Unable to claim DMA channel\n", __func__); + return -1; + } + + printk(BIOS_SPEW, "%s: Sending %d bytes\n", __func__, out_bytes); + tegra2_spi_dma_setup(dma); + + /* set AHB & APB address pointers */ + write32((u32)dout, &dma->regs->ahb_ptr); + write32((u32)&spi->regs->tx_fifo, &dma->regs->apb_ptr); + + setbits_le32(&spi->regs->command1, SPI_CMD1_TX_EN); + + /* FIXME: calculate word count so that it corresponds to bus width */ + write32(out_bytes - 1, &dma->regs->wcount); + + /* specify BLOCK_SIZE in SPI_DMA_BLK */ + write32(out_bytes - 1, &spi->regs->dma_blk); + + /* Set DMA direction for AHB (DRAM) --> APB (SPI) */ + setbits_le32(&dma->regs->csr, (1 << 28)); + + /* write to SPI_TRANS_STATUS RDY bit to clear it */ + setbits_le32(&spi->regs->trans_status, SPI_STATUS_RDY); + + dma_start(dma); + /* set DMA bit in SPI_DMA_CTL to start */ + setbits_le32(&spi->regs->dma_ctl, SPI_DMA_CTL_DMA); + + while ((read32(&dma->regs->dma_byte_sta) < out_bytes) || dma_busy(dma)) + tegra_spi_delay(spi, out_bytes - spi_byte_count(spi)); + dma_stop(dma); + + while ((count = spi_byte_count(spi)) != out_bytes) + tegra_spi_delay(spi, out_bytes - count); + clrbits_le32(&spi->regs->command1, SPI_CMD1_TX_EN); + + dma_release(dma); + + if ((spi_byte_count(spi) != out_bytes) || fifo_error(spi)) { + printk(BIOS_ERR, "%s: ERROR: Sent %u bytes, expected %u\n", + __func__, spi_byte_count(spi), out_bytes); + dump_regs(spi, dma); + return -1; + } + + return out_bytes; +} + +int spi_xfer(struct spi_slave *slave, const void *dout, unsigned int bitsout, + void *din, unsigned int bitsin) +{ + unsigned int out_bytes = bitsout / 8, in_bytes = bitsin / 8; + struct tegra_spi_channel *spi = to_tegra_spi(slave->bus); + int ret = 0; + u8 *out_buf = (u8 *)dout; + u8 *in_buf = (u8 *)din; + + ASSERT(bitsout % 8 == 0 && bitsin % 8 == 0); + + /* tegra bus numbers start at 1 */ + ASSERT(slave->bus >= 1 && slave->bus <= ARRAY_SIZE(tegra_spi_channels)); + + flush_fifos(spi->regs); + + /* + * DMA operates on 4 bytes at a time, so to avoid accessing memory + * outside the specified buffers we'll only use DMA for 4-byte aligned + * transactions accesses and transfer remaining bytes manually using + * the Rx/Tx FIFOs. + */ + + while (out_bytes > 0) { + unsigned int dma_out, fifo_out; + + dma_out = MIN(out_bytes, SPI_MAX_TRANSFER_BYTES_DMA); + fifo_out = dma_out % TEGRA_DMA_ALIGN_BYTES; + dma_out -= fifo_out; + + if (dma_out) { + ret = tegra_spi_dma_send(spi, out_buf, dma_out); + if (ret != dma_out) { + ret = -1; + goto spi_xfer_exit; + } + out_buf += dma_out; + out_bytes -= dma_out; + } + if (fifo_out) { + ret = tegra_spi_fifo_send(spi, out_buf, fifo_out); + if (ret != fifo_out) { + ret = -1; + goto spi_xfer_exit; + } + out_buf += fifo_out; + out_bytes -= fifo_out; + } + } + + while (in_bytes > 0) { + unsigned int dma_in, fifo_in; + + dma_in = MIN(in_bytes, SPI_MAX_TRANSFER_BYTES_DMA); + fifo_in = dma_in % TEGRA_DMA_ALIGN_BYTES; + dma_in -= fifo_in; + + if (dma_in) { + ret = tegra_spi_dma_receive(spi, in_buf, dma_in); + if (ret != dma_in) { + ret = -1; + goto spi_xfer_exit; + } + in_buf += dma_in; + in_bytes -= dma_in; + } + if (fifo_in) { + ret = tegra_spi_fifo_receive(spi, in_buf, fifo_in); + if (ret != fifo_in) { + ret = -1; + goto spi_xfer_exit; + } + in_buf += fifo_in; + in_bytes -= fifo_in; + } + } + + ret = 0; + +spi_xfer_exit: + if (ret < 0) + clear_fifo_status(spi); + return ret; +} + +/* SPI as CBFS media. */ +struct tegra_spi_media { + struct spi_slave *slave; + struct cbfs_simple_buffer buffer; +}; + +static int tegra_spi_cbfs_open(struct cbfs_media *media) +{ + DEBUG_SPI("tegra_spi_cbfs_open\n"); + return 0; +} + +static int tegra_spi_cbfs_close(struct cbfs_media *media) +{ + DEBUG_SPI("tegra_spi_cbfs_close\n"); + return 0; +} + +#define JEDEC_READ 0x03 +#define JEDEC_READ_OUTSIZE 0x04 +/* JEDEC_READ_INSIZE : any length */ + +static size_t tegra_spi_cbfs_read(struct cbfs_media *media, void *dest, + size_t offset, size_t count) +{ + struct tegra_spi_media *spi = (struct tegra_spi_media *)media->context; + u8 spi_read_cmd[JEDEC_READ_OUTSIZE]; + int ret = count; + + /* TODO: Dual mode (BOTH_EN_BIT) and packed mode */ + spi_read_cmd[0] = JEDEC_READ; + spi_read_cmd[1] = (offset >> 16) & 0xff; + spi_read_cmd[2] = (offset >> 8) & 0xff; + spi_read_cmd[3] = offset & 0xff; + + /* assert /CS */ + spi_cs_activate(spi->slave); + + if (spi_xfer(spi->slave, spi_read_cmd, + sizeof(spi_read_cmd) * 8, NULL, 0) < 0) { + ret = -1; + printk(BIOS_ERR, "%s: Failed to transfer %u bytes\n", + __func__, sizeof(spi_read_cmd)); + goto tegra_spi_cbfs_read_exit; + } + + if (spi_xfer(spi->slave, NULL, 0, dest, count * 8)) { + ret = -1; + printk(BIOS_ERR, "%s: Failed to transfer %u bytes\n", + __func__, count); + } + +tegra_spi_cbfs_read_exit: + /* de-assert /CS */ + spi_cs_deactivate(spi->slave); + return (ret < 0) ? 0 : ret; +} + +static void *tegra_spi_cbfs_map(struct cbfs_media *media, size_t offset, + size_t count) +{ + struct tegra_spi_media *spi = (struct tegra_spi_media*)media->context; + void *map; + DEBUG_SPI("tegra_spi_cbfs_map\n"); + map = cbfs_simple_buffer_map(&spi->buffer, media, offset, count); + printk(BIOS_INFO, "%s: map: 0x%p\n", __func__, map); + return map; +} + +static void *tegra_spi_cbfs_unmap(struct cbfs_media *media, + const void *address) +{ + struct tegra_spi_media *spi = (struct tegra_spi_media*)media->context; + DEBUG_SPI("tegra_spi_cbfs_unmap\n"); + return cbfs_simple_buffer_unmap(&spi->buffer, address); +} + +int initialize_tegra_spi_cbfs_media(struct cbfs_media *media, + void *buffer_address, + size_t buffer_size) +{ + // TODO Replace static variable to support multiple streams. + static struct tegra_spi_media context; + static struct tegra_spi_channel *channel; + + channel = &tegra_spi_channels[CONFIG_BOOT_MEDIA_SPI_BUS - 1]; + channel->slave.cs = CONFIG_BOOT_MEDIA_SPI_CHIP_SELECT; + + DEBUG_SPI("Initializing CBFS media on SPI\n"); + + context.slave = &channel->slave; + context.buffer.allocated = context.buffer.last_allocate = 0; + context.buffer.buffer = buffer_address; + context.buffer.size = buffer_size; + media->context = (void*)&context; + media->open = tegra_spi_cbfs_open; + media->close = tegra_spi_cbfs_close; + media->read = tegra_spi_cbfs_read; + media->map = tegra_spi_cbfs_map; + media->unmap = tegra_spi_cbfs_unmap; + + return 0; +} + +struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs) +{ + struct tegra_spi_channel *channel = to_tegra_spi(bus); + if (!channel) + return NULL; + + return &channel->slave; +} + +int spi_claim_bus(struct spi_slave *slave) +{ + tegra_spi_init(slave->bus); + spi_cs_activate(slave); + return 0; +} + +void spi_release_bus(struct spi_slave *slave) +{ + spi_cs_deactivate(slave); +} diff --git a/src/soc/nvidia/tegra124/spi.h b/src/soc/nvidia/tegra124/spi.h new file mode 100644 index 0000000..02495ab --- /dev/null +++ b/src/soc/nvidia/tegra124/spi.h @@ -0,0 +1,29 @@ +/* + * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef __NVIDIA_TEGRA124_SPI_H__ +#define __NVIDIA_TEGRA124_SPI_H__ + +#include <stddef.h> + +struct cbfs_media; +int initialize_tegra_spi_cbfs_media(struct cbfs_media *media, + void *buffer_address, + size_t buffer_size); + +void tegra_spi_init(unsigned int bus); + +#endif /* __NVIDIA_TEGRA124_SPI_H__ */

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Patch merged into coreboot/master: 8932f11 tegra124: Make tegra124 compilable with serial turned off.
by gerrit＠coreboot.org 10 Sep '14

10 Sep '14

the following patch was just integrated into master: commit 8932f11c91d9f8b80af562936c8b5c82af9a3c29 Author: Gabe Black <gabeblack(a)google.com> Date: Wed Oct 9 23:45:07 2013 -0700 tegra124: Make tegra124 compilable with serial turned off. The bootblock and romstage UART consoles were being built in based only on whether or not the bootblock and romstage consoles were selected, ignoring whether serial console support was compiled in generally. Change-Id: I3866519c422a990c44ced66885108eff24894563 Signed-off-by: Gabe Black <gabeblack(a)google.com> Reviewed-on: https://chromium-review.googlesource.com/172580 Reviewed-by: Ronald Minnich <rminnich(a)chromium.org> Commit-Queue: Gabe Black <gabeblack(a)chromium.org> Tested-by: Gabe Black <gabeblack(a)chromium.org> (cherry picked from commit a4f2dd4902a05884693e6e350b6be29276d16981) Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com> Reviewed-on: http://review.coreboot.org/6862 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> See http://review.coreboot.org/6862 for details. -gerrit

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Patch merged into coreboot/master: 58f3062 nyan: Use the new pinmux functions as part of UART setup.
by gerrit＠coreboot.org 10 Sep '14

10 Sep '14

the following patch was just integrated into master: commit 58f306258067f1df231d9c01a60930c2ee815dbc Author: Gabe Black <gabeblack(a)google.com> Date: Fri Oct 4 06:17:22 2013 -0700 nyan: Use the new pinmux functions as part of UART setup. The pins for the UART had been configured manually using hardcoded offsets and values. Now that we have pinmux functions for that sort of thing, we should use that instead. This also provides a very simple test for the pinmux code. Ultimately this code should be wrapped in a function which handles setting up any of the UARTs which is appropriately parameterized and which would be called from the bootblock main instead of being in it, but for now this is sufficient. Old-Change-Id: I69e36fa5fc9b6f3f5ef7f1be3e9f18cdbfdd7fe9 Signed-off-by: Gabe Black <gabeblack(a)google.com> Reviewed-on: https://chromium-review.googlesource.com/171807 Reviewed-by: Ronald Minnich <rminnich(a)chromium.org> Reviewed-by: David Hendricks <dhendrix(a)chromium.org> Commit-Queue: Gabe Black <gabeblack(a)chromium.org> Tested-by: Gabe Black <gabeblack(a)chromium.org> (cherry picked from commit d29e655b68143e86199ab1d74f89e125b16b67cc) tegra124: Call the set_avp_clock_to_clkm function in the bootblock. We had a hardcoded version of the set_avp_clock_to_clkm function in the bootblock, and we had to use it until now because the real version uses udelay, and until now that hadn't been implemented. Also, replace the delay loop in the hacky_hardcoded_uart_setup_function with a call to the real thing. Old-Change-Id: I6df9421bcad484e0855c67649683d474d78e4883 Signed-off-by: Gabe Black <gabeblack(a)google.com> Reviewed-on: https://chromium-review.googlesource.com/172045 Reviewed-by: Gabe Black <gabeblack(a)chromium.org> Commit-Queue: Gabe Black <gabeblack(a)chromium.org> Tested-by: Gabe Black <gabeblack(a)chromium.org> (cherry picked from commit 4c6dd4c7cade7d922a258e0371e43972bce77249) Squashed two tegra124 bootblock related commits. Change-Id: I0ce6321a04b11b7f1250ef3816fe46732777988d Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com> Reviewed-on: http://review.coreboot.org/6861 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix(a)chromium.org> See http://review.coreboot.org/6861 for details. -gerrit

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Patch merged into coreboot/master: dda0e66 Exynos5420: Fix up the i2c driver for use with the TPM driver
by gerrit＠coreboot.org 10 Sep '14

10 Sep '14

the following patch was just integrated into master: commit dda0e66d9c0d834acb5cda6dc85c273eeaecd48a Author: Gabe Black <gabeblack(a)google.com> Date: Wed Nov 6 11:21:48 2013 -0800 Exynos5420: Fix up the i2c driver for use with the TPM driver The TPM driver expects to call i2c_read with zero address length. The i2c driver wasn't prepared to handle that particularly in the case of reads because it expected to send an address before switching over to read mode for the data. This change also fixes up the read and write calls to consistently be read32 and write32 instead of readl and writel. Change-Id: I33dee89b83d4cd9d3e1b90e84b40e761bb8d4de4 Signed-off-by: Gabe Black <gabeblack(a)google.com> Reviewed-on: https://chromium-review.googlesource.com/175966 Reviewed-by: Stefan Reinauer <reinauer(a)chromium.org> Tested-by: Stefan Reinauer <reinauer(a)chromium.org> Commit-Queue: Gabe Black <gabeblack(a)chromium.org> (cherry picked from commit cf686269424ea938d6f953d0f76103182eb71297) Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com> Reviewed-on: http://review.coreboot.org/6857 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> See http://review.coreboot.org/6857 for details. -gerrit

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Patch merged into coreboot/master: 9b47231 samus: Fix 8GB SPD
by gerrit＠coreboot.org 10 Sep '14

10 Sep '14

the following patch was just integrated into master: commit 9b47231d2edfbdf47ade686ebc614810a26c0675 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Wed Nov 13 14:49:51 2013 +0800 samus: Fix 8GB SPD The 8GB variant is x16 with 11 column bits and 4Gb density. Change-Id: I3aa647aba88dbc928fefd826cbd01e4fa8273660 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/176640 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Commit-Queue: Aaron Durbin <adurbin(a)chromium.org> (cherry picked from commit d18462f6fc0d40328e9619525240778ea6b1a426) Signed-off-by: Isaac Christensen <isaac.christensen(a)se-eng.com> Reviewed-on: http://review.coreboot.org/6856 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> See http://review.coreboot.org/6856 for details. -gerrit

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coreboot-gerrit September 2014